1984_Rockwell_Data_Book 1984 Rockwell Data Book
User Manual: 1984_Rockwell_Data_Book
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1984
DATA BOOK
Second Edition
Rockwell International
Semiconductor Products Division
©Rockwell International Corporation 1984
All Rights Reserved
Printed in U.S.A.
Order No.1
March, 1984
Rockwell Semiconductor Products Division Is headquanered In Newpon Beach,
California with Field Sales Offices located throughout the United States, Canada
Europe and the Far East. Their listings, plus those of domestic· and International
representatives and distributors, appear on pages A-1 through A-5 of this
publication.
NOTICE
Rockwell International does not assume any liability arising out of the application or use
of any products, circuit or software described herein, neither does it convey any license
under its patent rights nor the patent rights of others. Rockwell International further
reserves the right to make changes in any products described herein without notice.
Specifications in the Data Book are subject to change without notice. Preliminary
specifications have tentative parameters which may be subject to change after final
product characterization is· completed.
ii
TABLE OF CONTENTS
Rockwell Semiconductor Cross-Reference
Guide ........................... '......... .
Application Note ,Index ................. '. . . . . . .
2
Index By Product Family. . . . . . . . . . . . . . . . . . . . . .
3
SECTION
RS800 Microprocessor and Peripherals. . . . . . .
Product Family Overview. . . . . .. . . . . . . .. . . . . .
R68000 16-Bit Microprocessing Unit (MPU) . . . . .
R68465 Double;.Density Floppy Disk
Controller (DDFDC) . . . . . . . . . . . . . . . . . .. . . . .
R68560 and R68561 Multi-Protocol
Communications Controller (MPCC) .........
R68802 Local Network Controller (LNET) . . . . . ..
R68C552 Dual Asynchronous Communications
Interface Adapter (DACIA) .................
2
3
8-Blt Microprocessors and Peripherals . . . . . . .
Product Family Overview ... '. . .. . . . . . . . . . . . . .
R6500 Family Products
R650X and R651 X Microprocessors (CPU). . . •. .
R6501Q and R6511Q One-Chip Microprocessors
R6520 Peripheral Interface Adapter (PIA) . . . . . . .
R6522 Versatile Interface Adapter (VIA) . . . . . . . .
R6530 ROM-RAM-I/O-Timer (RRIOT) ..........
R6531 ROM-RAM-I/O-Counter (RRIOC) ........
R6532 RAM-I/O-Timer (RIOT) ................
R6541Q, R6500/41, R6500/42 and R6500/43
One-Chip Intelligent Peripheral Controller. . . . .
R6545-1 CRT Controller (CRTC). . .. . . . . . . . . ..
R6551 Asynchronous Communications
Interface Adapter (ACIA) . . . . . . . . . . . . . . . . . ..
R6565 Double-Density Floppy Disk
Controller (DDFDC) . . . . . . . . . . . . . . . . . . . . . ..
R6592 Single Chip Printer Controller . . . . . . . . ..
R65560 Multi-Protocol Communications
Controller (MPCC) ........................
R65C02, R65Cl02 and R65Cl12 CMOS
Microprocessors (CPU) ... , . . . . . . . .. . . . . . ..
R65C21 CMOS Peripheral Interface
Adapter (PIA) .................. , . . . . . . . ..
R65C24 CMOS Peripheral Interface
Adapter Timer (PlAT) .....................
R65C51 CMOS Asynchronous Communications
Interface Adapter (ACIA) .. , " . . . . . . . . . . . . ..
R65C52 CMOS Dual Asynchronous
Communications Interface Adapter (DACIA) . ..
~1I0/8080 Bus Compatible Products
R6265 Micro Floppy Disk
Controller (MFDC) . . . . . . . . . . . . . . . . . . . . . . ..
R6765 Double;.Density Floppy Disk
Controller (DDFDC) . . . . . . . . . . . . . . . . . . . . . ..
R6500/- Microcomputers. . . . . . . . . . . . . . . . . . .
Product Family Overview. . . . . . . . . . . . . . . . . . . .
R65COO/21 and R65C29 Dual CMOS
Microcomputer and Dual CMOS
Microprocessor ................... . . . . . . .
R65Fll and R65F12 FORTH One-Chip
Microcomputers. . . ... . . . . . . . . . . . . . . . . . . . .
R65FRX.and R65FKX RSC FORTH
Development and Kernel ROMs. . . . . . . . . . . . .
1-1
1-2
1-3
1-58
1-83
1-115
4
1-135
2-1
2-2
2-3
2-18
2-24
2-36
2-58
2-69
2-82
2-92
2-100
2-116
2-136
2-161
5
' 2-172
2-202
2-217
2-229
2-249
6
2-269
2-288
2-313
3-1
3-2
3-3
3-35
3-67
iii
R6501Q One-Chip Microprocessor ........... .
R6500/1 One-Chip Microcomputer .......•.....
R6500/1 E Emulator Device ................. .
R6500/1 EB and R6500/1 EAB Backpack
Emulator .. , ...................... .
R6500/11 and R6500/12 One;.Chip
Microcomputers ...... ,' ............. : .... .
R65/11 EB and R65/11 EAB, Backpack Emulator ..
R6500/13 and R6511 Q One-Chip
Microcomputer and One-Chip
Microprocessor .......... : .............. .
R6500/41 and R6500/42 One;.Chip Intelligent
Peripheral Controllers .................... .
R65/41 EB and R65/41 EAB Backpack Emulator ..
R6500/43 and R6541Q One-Chip Intelligent
Peripheral Controllers .................... .
3-75
3-104
3-135
Memory Products ................... ~ .... .
Product Family Overview ................... .
Masked ROMs
R2332A and R2332B 32K NMOS Static ROM .. .
R2364A 64K NMOS Static ROM ............. .
R2364B 64K NMOS Static ROM ............. .
R23C64 64K CMOS Static ROM ............. .
R23128 128K NMOS Static ROM ............ .
UV Erasable and One-Time PROMs
R27C64P 64K CMOS One-Time PROM ....... .
R87C32 32K CMOS UV EPROM ............. .
R87C64 64K CMOS UV EPROM ............•.
EEROMs
R5213/2816 16K EEROM ................... .
R52B33 64K ,Latched EEROM ............... .
R2816A and R551SA 16K Latched
EEPROM with Timer .............. c•.••••••
NVRAM
R2000 64 x 8 Non-Volatile RAM ............ .
EPROM Pinouts Guide: .................... .
4-1
4-2
Intelligent Display Controllers .. ; ........... .
Product Family Overview ................... .
10937 Alphanumeric Display Controller
10938 and 10939 Dot Matrix Display Controller ..
10939, 10942 and 10943 Dot Matrix
Display Controller .............. , ........ .
10941 and 10939 Alphanumeric and Bargraph
Display Controller . " ..................... .
10951 Bargraph and Numeric Display Controller .
Microcomputer Development Systems ...... .
Product Family Overview ............•.......
Rockwell Design Center (RDC)
RDC-l00l and RDC-l002 ROC System .... : ...
RDC-1XX apd RDC-3XX ROC R6500/Personality Set .............•.......... , ..
RDC-502 and RDC-504 R6502-R65C02
Personality ~et ................... '..... ',.
RDC-2000 R6500 Cross Assembler for Intel
Development System ................... ,..
System 65 Development System
(Optional Modules)
M65-1XX and M65-2XX System 65 R6500/Personality Set . " ............. ',' ........ .
M65-001, M65-002, and M65-003 User 65
Module ................................ .
M65-031 and M65-032 16K Static RAM Module ..
3-142
3-147
3-182
3-187
3-222
3-251
3-256
4-3
4-7
4-11
4-15
4~19
4-23
4-29
4-35
4-41
4-49
4-57
4-65
4-71
5-1
5-2
5-3
5-11
5-20
5-32
5-41
6-1
6-2
6-3
6-9
6-13
6-17
6-19
6-23
6-28
TABLE OF CONTENTS (Continued)
7
8
9
M65-040 PROM Programmer Module. . . . . . . . . .
M65-045 PROM/ROM Module . . . . . . . . . . . . . . . .
M65-060 Extender Card . . . . . . . . . . . . . . . . . . . . .
M65-071 Design Prototyping Module. . . . . . . . . . .
M65-660 Macro Assembler and Linking Loader. .
Software Preparation System
SPS-200 Software Preparation System Peripheral
Connector Module. . . . . . . . . . . . . . . . . . . . . . . .
6-31
6-39
6-43
6-44
6-46
AIM 65 Microcomputer Family. . . . . .. . . . . . . . .
Product Family Overview. .. . . . . . . . . . . . . . . . . .
A65-100 and A65-400 AIM 65 Microcomputer. . .
A65-0500 AIM 65 Microcomputer System. . . . . . .
A65-002 and AS5-006 AIM 65 Microcomputer
Enclosure. . . . ... . . . .. ... . . . .. . . ... .. . . . .
A65-003 Service Test Board .................
A65-004-03 Power Supply and Cable . . . . . . . .. .
A65-010 Assembler ROM. . . . . . . . . . . . . . . . . . . .
A65-020 BASIC Interpreter ROMs. . . . . . . . . . . . .
A65-024 BASIC Compiler. . . . . . . . . . . . . . . . . . . .
A65-030 PU65 Compiler ROMs. . . . . . . . . . . . . . .
A65-040 Math Package ROM. . . . . . . . . . . . . . . • .
A65-050 FORTH ROMs .. . . . . . . . . . . . . . . . . . . .
A65-052 FORTH Target Compiler . . . . . . . . . . . . .
A65-060 Instant Pascal ROMs ............. , . .
A65-090 Disk Operating System (DOS 1.0) ROM
A65-901 PROM Programmer and CO-ED Module
A65-905 Memory Cartridge ..................
7-1
7-2
7-3
7-10
AIM 65/40 Microcomputer Family. . . . . . . . . . . .
Product Family Overview. . . . . . . . . . . . . . . . . . . .
A65/40-8X15 Series 8000 Microcomputer System
A65/40-2000, A65/40-3000, A65/40-4000 and
A65/40-5000 AIM 65140 Microcomputer. . . . . . .
A65/40-1000 Single Board Computer. . . . . . . . . .
A65/40-0004 Power Supply and Cable . . . . . . . . .
A65/40-0200 and A65/40-0210 Standard and
Extended Keyboards. .. . . . . . . . . . . . . . . . . . . .
A65/40-0400 40-Character Display ............
A65/40-0600 Graphics Printer . . . . . . . . . . . . . . . .
A65/40-0800 Video Display Controller Module . . .
A65/40-7010 Assembler ROM. . . . . . . . . . . . . . . .
A65/40-7012 Macro Assembler and Linking
Loader .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. .
A65/40-7020 BASIC Interpreter ROMs. . . . . . . . .
A65/40,7024 BASIC Compiler ...... , . , . . . . . . .
A65/40-7040 Math Package ROM ... , . . . . . . . . .
A65/40-7050 FORTH ROMs. . . . . . . . . . . .. . . . . .
A65/40-7052 FORTH Target Compiler. . . .. . . . . .
A65/40-7090 Disk Operating System Version 1.0
(DOS 1.0) ROM ....... , . . . . . . . . . . . . . . . . . .
A65/40-7092 Bootstrap Disk Operating System
Version 1.0 Upgrade Kit. . . . . . . . . . . . . . . . . . .
RM 65 Microcomputer Module Family ....... .
Product Family Overview ................... .
RM65-1000E Single Board Computer (SBC)
Module ................................ .
RM65-0110 I/O ROM ...................... .
RM65-0122 Run-Time BASIC INTERPRETER
ROM .................................. .
RM65-0152 Run-Time FORTH ROM ......... , .
RM65-2901 E PROM Programmer Module ..... .
RM65-3108E 8K Static RAM Module. . . . . . . . . . .
RM65-3132E 32K Dynamic RAM Module. .. . . . .
RM65-3216E 16K PROM/ROM Module. . . . . . . . .
RM65-3264NE Univeral Memory Module .......
RM65-51 01 E Floppy Disk Controller (FDC)
Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RM65-5102E CRT Controller (CRTC) Module. . . .
RM65-5104E Direct Memory Access Controller
Module . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .
RM65-5222E General Purpose Input/Output
(GPIO) and Timer Module. . . . . . . . . . . . . . . . . .
RM65-5223E Multi-Function Peripheral Interface
(MPI) Module. . . . . . . . . . . . . . . . . . . . . . . . . . . .
RM65-5302E and RM65-5303E Analog Input
Module and Analog Input/Output Module .. . . .
RM65-5451 E Asynchronous Communications
Interface Adapter (ACIA) Module. . . . . . . . . . . .
RM65-7004E and RM65-7004NE 4-Slot
Piggyback Module Stack and Motherboard. . . .
RM65-7008E and RM65-7008NE 8-Slot Card
Cage and Motherboard. . . . . . . . . . . . . . . . . . . .
RM65-7016E and RM65-7016NE 16-Slot Card
Cage and Motherboard. . . . . . . . . . . . . . .. . . . .
RM65-71 01 E Single Card Adapter Module for
AIM 65 .................................
RM65-7102E IEEE-488 Bus Interface Module ...
RM65-7104E Adapter/Buffer Module·for AIM 65.
RM65-7116E RM65 Cable Driver Adapter/Buffer
Module for AIM 65 .......................
RM65-7141E Adapter Cable and Buffer Module
for AIM 65/40 . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RM65-7201 E Design Prototyping Module. . . . . ..
RM65-7211E Extender Module. . . .. ... . .. . . ..
6-48
7-12
7-14
7-16
7-18
7-20
7-22
7-24
7-26
7-28
7-33
7-38
7-41
7-42
7-46
8-1
8-2
8-3
8-10
8-22
8-30
10 Integral Modems. . . . . . . . . . . . . . . . . . . . . . . . . .
Product Family Overview. . . . . . . . . ... . . . . . . . . .
High Speed
R96FAX 9600 BPS Facsimile Modem. .. .. . . . . .
R96DP 9600 BPS Data Pump Modem.. . . . . . ..
R96FT 9600 BPS Fast Train Modem ..........
V96P/l 9600 BPS Modem. . . . . . . . . .. . . . . . . ..
R48DP 4800 BPS Data. Pump Modem .. . . . . . ..
V27P/l 4800 BPS Modem ........... '. . . . . . ..
Low to Medium Speed
R1212 1200 BPS Full Duplex Modem. . . . . . . . ..
R2424 2400 BPS Full Duplex Modem. . . . . . . . ..
R24DC 2400 BPS Direct Connect Modem. . . . ..
R24LL 2400 BPS Leased Line Modem. . . . . . . ..
R242400 BPS Integral Modem ...............
Modem Interfacing Products
R24MEB Modem Evaluation Board ............
RDAA Rockwell Data Access Arrangement
Module .................................
8-32
8-36
8-43
8-49
8-56
8-58
8-59
8-61
8-63
8-65
8-70
8-75
8-76
9-21
9-25
9-29
9-33
9-37
9-43
9-49
9-54
9-58
9-63
9-69
9-73
9-78
9-83
9-88
9-94
9-99
9-105
9-111
9-116
9-120
10-1
10-2
10-3
10-13
10-26
10-28
10-36
10-49
10-56
10-70
10-84
10-92
10-101
10-109
10-111
11 T-1 and T-1fCEPT Pulse Code Modulation
Protocol Devices ....................... .
11-1
Product Family Overview ...... , ............ .
11-2
11-3
RB040 Tri-Port Memory .................... .
RB050 T-l Serial Transmitter ................ .
11-9
RB060 T-l Serial Receiver .................. . 11-17
RB070 T-l/CEPT Pulse Code Modulation
Transceiver ............................ . 11-23
9-1
9-2
9-3
9-7
9-8
9-10
9-15
Sales Offices, Representatives and Distributors ..
iv
A-l
ROCKWELL SEIlICONDUCTORS CROSS·REFERENCE GUIDE'
t
SYNERTEK
ROCKWELL
5Y6502 .......•.... : • .. .... R6502
5Y6503 ... :. .. . .. . .. .... ... R6503
5Y~ ..................... R~4
5Y6505 .................... R6595
5Y6506 • .. . .. • .. .. .. .. . .... R6506
SY6507 .. .. .. .. .. . .. .. .. ... R6507
5Y6512 ..................... R6512
SY6513 ....................... R6513.
SY6514 ...................• R6514
5Y6515 ............... : .... R6515
5Y6520 . .. .. .. .. . . . . . .. . ... R6520
5Y6522 .. .. .. .. .. ...... .. ... R6522
5Y6530 . . .. . .. .. . . .. . . .. ... R6530
SY6532 ..................... R6532
5Y6545-1 . . . . . . . . . . . • . . • . . .. R6545-1
5Y6551 ..................•. R6551
INTEL
2816 .......................
8272 .......................
281E\A .............
1'2764 .......... .' ..... :: ...
P2732A ........... : ....... 0'
L
. . . . . . . . .•
•••••
ROCKWELL
R5213
R6765
R6S..1SA .
R2764P
R27C32P
MOTOROLA
I'lOCKWELL
MC6820 .. .. .. .. .. .. .. .. ..R6520 .
(1)MC6821 ................. : R6520
(2)MC6845 .................. R6545-1
(2)MC6645M .................. R6545-1
MC6S000 .. .. . .. .. . .. .. ... R68000
(1) except oppllcotion of (2) TTL load.
,
.
. ,
NCR
NCR6500/1 E ................
NCR6500/1 ... :..............
NCR6500/11 ................
NCR6500112 ................
NCR6500113 .•...•........•.
NCR6500/11E ...............
NCR65Q0/41 ................
NCR6500/42 ................
NCR6500/43 ........... : .....
NCR6500/41E ...............
NCR65C02 .................
521312816 ..................
5516A ....... , ..............
5133A ............ , ........
52833 .................. ,..
ROCKWELL
R65OQ/1 EC
R6500/1
R6500/11
R6500/12.
R6500/~3
R6511Q
R6500/41
R6500/42
R6sOo/4a
R6541Q
R65C02
ROCKWELL
R521312816
R5516A12816A
R2764P
R52B33
GTE
ROCKWELL
G655C02 ............... , ... R65C02
G655C21 .. . . . . . .. .. . . . .. ... R65C21
--~------- ~-G65SC5-f
..-.... -~ .. :-:- :-:-:- ..... R65C51
R23Cj34
RICOH
ROCKWELL
RD5H32
R87C32
RD5H64.. . . . . . . .. .. . . .. . ... R87C64
NATIONAL
ROCKWELL
NM027C32 .. , .....•.... .'" .. R87C32
NMC9716E .......... ,....... R5213
AMI
(2) uk customer for evaluation
'.,~.
ROCKWELL
52333 ...... , ... ; ........... R2332
MOS TECHNOLOGY
MPl;I6502. . .. . .. . .. . . . . .. ...
MP56503. .. . . .. . . . . . . .. .. ..
MP56504 ........ ~ ..........
MP56505.. . .. .. . .. .. . . .. ...
MP56506. . . .. .. . .. .. . . .. ...
MP56507 ...................
MP56512 ....................
MP56513 ...................
MP56514 ...................
MPS6515 ...................
MP56520.. .. .. . . .. . . . . . . . ..
MP56522 ...................
MP56530 ...................
MP56532 .. .. . .. . .. . . .. .. ...
ROCKWELL
R6502
R6503
R6504
R6505
R6506
R6507
R651.2
R6513
R6514
R6515
R6520
R6522
R6530
R6532
52364 ..................... R2364
523128 .................... R2312a
56551 ..... , .............. ' R6551
FUJITSU
ROCKWELL
MBM27G64 ................. R87C64
ROCKWELL
AMD
AM2764 .................... R87C64
RCA
ROCKWELL
CDP65564 .................. R23C84
ROCKWELL
NEC
765 ........................ R6765
APPLICATION NOTE INDEX
Title
Order No.
Order No.
Title
Development Systems
R6500 Mlcrciproceeeors and Peripherals
223
R6502lR6532 Timer Interrupt Precautions
224
System 65 to AIM 65 Microcomputer Interface
296
R6502 Interfacing Higher Speed R6502's to Lower
Speed 1/0 & Memory
Printer qontrol with R6522 VIA (Versatile Interface
AdaPter)
R6531 ROM·AAM·11O Counter (RRIOC)
240
User 65 Emulation with less than 512 Bytes of RAM
258
228
227
225
208
231
R6531 Addreae Lines for Contiguous ROM
Generating Non-Standard Baud Rates with the R6551
ACIA (Asynchronous Communication Interface Adapter)
Low-Cost CryStal Oscillator for Clock Input Frequency
Generator
278
Interfacing R6500 Microprocessors to a FDC (F;loppy
Disk Controller).
Crystal Considerations for R6500 Family Devices
287
Using R65XX Family Peripheral Devices with Z80 CPU
246
System 65 Bus Interface
2129
OS3.1 Monitor ROM & Macro AssembleriLinking Loader
2158
CMOS User 65 System 65 Development System
2186
R6500 Software Preparation System Development
Configurations
AIM 85 Microcomputer
230
241
RS·232C Interface for AIM 65 Microcomputer
prepari~g an
AIM 65 Basic Program for PROM/ROM
Operation
273
R85001" Microcomputers
2171
AIM 65 Program Timer
Adding Analog I/O to AIM. 65 Microcomputer
239
Interlacing R6500/1 to SIOC (Serial Input Display
Controller)
237
258
2183
R6500/1 Microcomputer·Based Printer Controller
607
.R24 Modem Options
A Logical Tester for R6500/1 On8-Chip Microcomputer
608
auallty ~ Received Data for R24 Modem
819
R24OC'lnterface to EIA RS·232-C
2~82
2178
Integral Modems
A Dot Matrix Controller System Design Using the
,
10938110939 Display Drivers and R8500/1EB
Microcomputer
A Low Cost DeVelopment Module for the
R65F11/r:1.65F1.2 FORTH Microcomputer
Design Considerations for Conversion to Rockwell
R6500111 and R6501Q from Intel 8051/6031
2175
622
R24DC Interface to U.S. Switched Telephone Network
624
R240C Modem Options
634
A24~L and R24DC Modem Control Signal To LED
Interiace
Intelligent Display Controllers
2183
,
A Dot Matrix Controller System Design Using the
10938110939 Display Drivers and R6500/1EB
Microcomputer
Display Controller Designer Notes
632
R24LL Modem lriterface to EIA RS·232-C
635
R24LLModem Options
617
480019600 BPS Modem Interfacing
637
Picture Plotter Data Transmissi.
System
co'
"
2
PRODUCT INDEX
R68000 Microprocessor and Peripherals
8-BIT Microprocessors and Peripherals
R6500/* Microcomputers
~M_e_m_o_~__p_r_o_du_c_t_s______________________________~~
Intelligent Display Controllers
Microcomputer Development Systems
AIM 65 Microcomputer Family
AIM 65/40 Microcomputer Family
RM 65 Microcomputer Module Family
I Integral Modems
T-1 and T-1/CEPT Pulse Code Modulation Protocol Devices
3
D
SECTION 1
R68000 MICROPROCESSOR AND PERIPHERALS
Page
Product Family Overview ............................... : . . . . . . . . . . . . .. . . . .
1-2
R68000 16-Bit Microprocessing Unit (MPU) ...................................
1-3
R68465 Double-Density Floppy Disk Controller (DDFDC) ........................
1-58
R68560 and· R68561 Multi-Protocol Communications ContrOller (MPCC) . . . . . . . .. . . . . 1-83
.
.
R68802 Local Network Controller (LN ET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-115
R68C552 Dual Asynchronous Communications Interface Adapter (DACIA) ........... 1-135
1-1
R6S000 MICROPROCESSOR AND PERIPHERAL FAMILY
16-bit Speed and Data Capacity, Peripherals to Build Efficient
Systems
ever made commercially available. It operates up to
4 Mbits/sec and supports all major communication protocols.
It's available to work with either 16-bit or 8-bit busses and
can be adapted to function with essentially any of today's
more common busses.
The R68465 double density floppy disk controller
(DDFOC) is an intelligent device that can run up to four disk'
drives without the many support devices previously
required.
TheR68802" provides a flexible local area network
(LNEn controller for the R6800e. It supports both the
IEEE 802.3 and Ethernet" standards based on the proven
CSMAlCD technique together with network statistics.
Rockwell lets you build efficient and economical 16-bit
systems through families of 16-bit and 8-bit peripherals, all
compatible. No other supplier offers you more.
Rockwell peripherals give a designer everything the
68000 family promises. They allow you to design. functional
systems utilizing all the speed and data handling potential
of the 16-bit 68000 family.
First of these are the Rockwell designed 16-bit
peripherals-multi-protocol communications controller,
double density floppy disk controller, local area netWork
controller-each a significant "first" that eliminates the
"glue parts" between a CPU and peripherals.
Not to be ignored, however, is the very wide and
complete family of 8-bit devices-processors, peripherals,
memory,single-chip microcomputers--<:ompatible with the
R68000 family. All of the R6500 family of devices described
in this Data Book are directly compatible with the R68000
bus. They often provide efficient, economical and very
flexible ways of implementing system designs.
The Rockwell R68000 16-bit microprocessor (MPU)
operates at clock speeds of 4, 6, 8, 10 or 12.5 MHz to
match essentially any application.
The R68561 multi-protocol communications controller
(MPCC) is the highest throughput communicaiions device
"R68802 is a trademark of the Rookwelllntemational Corp.
"Ethernet is a trademark of the Xerox Corp.
R68000/R6500 Peripheral Migration
1-2
,R68000
'1'
Rockwell
R68000
16-BIT MICROPROCESSING UNIT (MPU)
PRELIMINARY
DESCRIPTION
The R680000ffers seventeen 32-bi,t registers in addition to tlie
32-bit program counter and a 16-bit status register. The first eight
registers (00'-07) are used as data registers for byte (8-bit), word
(16-bit), and long word (32-bit) data operations. The second set
of seven registers (AO-A6) and the system stack pOinter may be
used as software stack pointers and base address registers. In
addition, these registers may be used for word and long word
address .operations. All 17.registers may be used as index
registers.
The RS8000 microprocessor is designed for high performance
where operational computation and versatility is required. The
R68000 provides powerful mass-memory handling capability and
architectural features designed to fit the broad range of 16-bit
needs. The Rockwell family of 16-bit products al$O include.s a
wide range of peripherals that will allow complete system design
and manufacture.
FEATUR.ES
31
16 15
87
• 16M byte (8M word) Linear Addessing Range
• 14 Operand Addressing Modes
• 56 Powerful Instruction Types
• Instruction Set Supports Structured High-Level Languages
• Pipelining Instruction Execution
• 32-Bit Program Counter
.
0
DO
D1
02
D3 EIGHT
4 DATA
REGISTERS
• 16-Bit Data Bus
• 23-Line Address Bus
• 32-Bit Data and Address Registers Including:
- Eight General Purpose Data Registers
- Seven Address Registers
- Two Stack Pointers (User, Supervisory)
• All 17 Registers Can Be Index Registers
• Memory Mapped Peripheral Devices
• Vector Generated Exception Processing
• Seven Unique Autovectors for Interrupt Service Routines
• Trace Mode for Software Debugging
• Operations Occur on Five Main Data Types
-Bit
-BCD
- Byte
-Word
- Long Word
• Asynchronous and Synchronous Peripheral Interface
Capability
• Many Peripheral Chips Available
- R68560.Multi-Protocol Communications Controller
--'R68465' Double Density Floppy Disk Controller
- R68802 Local Network Controller
• Up to 12.5 MHz Input Clock
• + 5 VDC Power Supply
~5
D6
D7
1615
31
0
A1
A2 SEVEN
A3 ADDRESS
A4 REGISTERS
A5
A6
--USER-STACKPOINTER-(UsP)--'
A7 TWO STACK
!.U!~'!.V.!.SE!! !T~£.K.!'~I!!T.!~ l!l!!'!.
POINTERS
o
31
15
87
o
PROGRAM
COUNTER
STATUS
REGISTER
SYSTEM BYTE USER BYTE
R680aa REGISTERS
Document No. 68650N01
1·3
Product Description Order No. 700
Rev. 4, August 1983
o
R68000
16-Bit MPU
64 PIN QUIP,
64·PIN OIP
"
..
,
D4
03
02
01
00
~ ': '.I'
63
62
61
60
59
58
57
56
~
IJ"DS
LDI
RiW
DTm<
BG
~
·BR
VCC
ClK
GNO
HALT
52
51
50
49
48
47
46
45
44
43
42
41
RESET
.VDA
E
"
VPA
BERR
IPl2
iPLf
jJS[lf
40
FC2
FC1
FCO
A1
' 39
38
37
36
35
34
33
A2
A3
A4
06
07
08
09
010
011
012
013
014
015
GNO
A23
A22
A21
VCC
A20
A19
A18
A17
04
03
02
01
00
AS
UOS
LOS'
RiW
OTACK
BG
BGACK
BR
Vec
ClK
GNO
HALT
RESET
VMA
E
VPA
BERR
, iJS[2
jj5[f
IPlO
FC2
FC1
FCO
A1
A14
A13
A12
A11
A10
A9
A8
A7
A2
A3
A4
AS
R68000 PIN CONFIGURATION
ORDERING INFORMATION
Order
Number
R68000C4
R68000C6
R68000C8
R68000C10
R68000C12
R68000Q8
R68000Q10
Package
Type
Ceramic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
Plastic QUIP
Plastic QUIP
Tempe~at~re
Ra~ge
Frequency
4
6
8
10
12.S
8
10
MHz
MHz
MHz
MHz
MHz
MHz
MHz
O°C
O·C
O·C
O·C
O·C
O·C
O·C
to
to
to
to
to
to
to
+ 70·C
+70·C
+70·C
+70·C
+70·C
+SS·C
'+ SS·C
1·4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
'55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
-j
05
06
07
08
D9
010
011
01'2
013
014
015
GNO
A23
A22
A21
VCC
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
AS
16-Bit MPU
R68000
SIGNAL DESCRIPTION
Address Strobe (AS). The AS output indicates that there is a
valid address on the address bus.
The following paragraphs briefly describe the input and output
signals and also reference (if applicable) other paragraphs that
contain more detail about the function being performed. Bus
operation during the various machine cycles and operations is
also discussed. The input and output signals can be functionally
organized into the groups shown in Figure 1.
Read/Write (RIW). The RiW output defines the data bus transfer
as a read or write cycle. The RiW signal also works in conjunction
with the upper and lower data strobes as explained in the follow·
ingparagraph.
Upper and Lower Data Strobes (UDS, LDS). The UOS and LOS
outputs control the data on the data bus, as shown in Table 1.
When the Rm line is high, the processor reads from the data
bus as indicated. When the RiW line is low, the processor writes
to the data bus as shown.
Note
The terms assertion and negation are used to avoid con·
fusion when dealing with a mixture of "active·low" and
"active·high" signals. The terms assert, or assertion, indio
cates that a signal is active, or true, independent of
whether that voltage is low or high. The term negate, or
negation, indicates that a signal is inactive or false.
Data TranSfer Acknowledge (DTACK). The OTACK input indio
cates that the data transfer is completed. When the processor
recognizes OTACK during a read cycle, data is latched and the
bus cycle terminated. When OTACK is recognized during a write
cycle, the bus cycle terminates. Refer to' ASYNCHRONOUS
VERSUS SYNCHRONOUS OPERATIQN.
ADDRESS BUS (A1 THROUGH A23). This 23·bit, unidirectional,
three·state bus can address eight megawords of data. Itpro·
vides the address for bus operation during all cycles except inter·
rupt cycles. During interrupt cycles, address lines A 1, A2, and
A3 encode the interrupt level to be serviced while address lines
A4 through A23 are all set high.
BUS ARBITRATION CONTROL. These three signals form a bus
arbitration circuit to determine which device will be the bus
master device.
Bus Request (BR). The BR input indicates to the processor, that
some other device desires to become the bus master. This input
can be externally ORed with all other devices that could be bus
masters.
DATA BUS (DO THROUGHD15). This 16·bit, bidirectional,
three·state bus is the general purpose data path. It transfers and
accepts data in either word or byte length. During an interrupt
acknowledge cycle, an external device supplies the vector
number on data lines 00·07.
Bus Grant (BG). The BG output indicates to all other potential
bus master devices that the processor will release bus control
at the .end of the current bus cycle.
'
ASYNCHRONOUS BUS CONTROL. Asynchronous data
transfers are handled using the following control signals: address
strobe, read/write, upper and lower data strobes, and data
transfer acknowlege. These signals are explained in the follow·
ing paragraphs.
Bus Grant Acknowledge (BGACK). The BGACK input indicates
that some other device has become the bus master. This signal
cannot be asserted until the following four conditions are met:
1. a bus grant (BG) has been received,
2. address strobe (AS) is inactive which indicates that the
processor is not using the bus
ADDRESS
Vc c(2)
Table 1.
A1·A23
BUS
GNO(2)
00·015
BUS
~
VAS
CLK
"V
RIW
FCO
PRO·
{
CESSOR
STATUS
R6500
{
PERIPH·
ERAL
CONTROL
SYSTEM {
CONTROL
FC1
FC2
E
VMA
VPA
UOS
R68000
MPU
LOS
DTAcK
-BR
BUS
BG
} ARBITRA·
TION
BGACK CONTROL
BERR
IPLO
~
IPL1
HALT
IPL2
Figure 1.
ASYNCHRO·
} NOUS BUS
CONTROL
INTERRUPT
} CONTROL
Data Strobe Control otData Bus
UOS
LOS
R/W
High
High
-
No valid data
No valid data
Valid data bits
0·7
08·D15
00·07
Low
Low
High
Valid data bits
8·15
High
Low
High
No valid data
Valid data bits,
0·7
Low
High
High
Valid data bits
8·15
No valid data
Low
Low
Low
Valid data bits
8·15
Valid data bits
0·7
High
Low
Low
Valid data bits
0·1'
Valid data bits
0-7
Low
High
Low
Valid data bits
8-15'
Valid data bits
8-15"
"These conditions are a result of current implementation and may not
appear on future devices.
Input and Output Signals
1-5
1
16-Bit MPU
R68000
3. data transfer acknowledge (DTACK) is inactive which
indicates that neither memory nor peripherals are using the
bus, and
4. bus grant acknowledge (BGACK) is inactive which
indicates that no other device is still claiming bus mastership.
R6500 PERIPHERAL CONTROL. These control Signals are
used to allow the interfaCing of synchronous R6500 peripheral
devices with the asynchronous R68aOa. These signals are
explained in the following paragraphs.
Enable (E). The E output signal is the standard enable signal
(\&2 clock) common to all R6500 type peri'pheral devices. The
period for this output is ten R680aO clock periods (six clocks
low; four clocks high). Enable is generated by an internal ring
counter which may come up in any state (i.e., at power on, it
is impossible to guarantee phase relationship of E to CLK). E
is a free-running clock and runs regardless of the state of the
bus on the MPU.
INTERRUPT CONTROL (IPLO, IPL 1, IPL2). These input pins
indicate the encoded priority level of the device requesting an
interrupt. Level seven is the highest priority while level zero indicates that no interrupts are requested. Level seven cannot be
masked. IPLO is the least significant bit while IPL2 is the most
significant bit. To insure an interrupt is recognized, the interrupt control lines (lPLX) must remain stable until the processor
signals interrupt acknowledge (FCO, FC1, and FC2 all high).
Valid Peripheral Address (VPA). The VPA input indicates that
the device or region addressed is a R6500 family device and
that data transfer should be synchronized with the enable (E)
signal. This input also indicates that the processor should use
automatic vectoring for an interrupt. Refer to INTERFACE WITH
R6500 PERIPHERALS.
SYSTEM CONTROL. The system control inputs either reset or
halt the processor or indicate to the processor that bus errors
have occurred. The three system control inputs are explained
in the following paragraphs.
Bus Error (BERR). The BERR input informs the processor that
a problem exists with the cycle currently being executed.
Problems may be a result of:
1. nonresponding devices,
2. interrupt vector number acquisition failure.,
3. illegalaccessrequest as determined by a memory management unit, or
4. other application dependent errors.
Valid Memory Address (VMA). The VMA output indicates to
R6500 peripheral devices that there is a valid address on the
address bus and that the processor is synchronized to enable.
This signal only responds to a valid peripheral address (VPA)
input which indicates that the peripheral is a R65aO family device.
PROCESSOR STATUS (FCO, FC1, FC2). These function code
outputs indicate the state (user or supervisor) and the cycle type
currently being executed, as shown in Table 2. The information
indicated by the function code outputs is valid whenever address
strobe (AS) is active.
The Bus Error (BERR) signal interacts with the HALT signal to
determine if exception processing should be performed or the
current bus cycle s.hould be retried.
CLOCK (CLK). The clock input is a TTL-compatible signal that
is internally buffered for development of the internal clocks
needed by the processor. The clock input should not be gated
off at any time and the clock signal must conform to minimum
and maximum pulse width times.
Refer to BUS ERROR AND HALT OPERATION paragraph for
additional information about the interaction of the bus error and
halt signals.
Reset (RESET). This bidirectional signal line acts to reset (initiate
a system initialization sequence) the processor and system in
response to an external reset signal. An internally generated
reset (result of a RESET instruction) resets all external devices
while not affecting the internal state of the processor. A total
system reset (processor and external devices) is the result of
external HALT and RESET signals applied simultaneously. Refer
to RESET OPERATION paragraph for additional information.
SIGNAL SUMMARY. Table 3 summarizes all the signals discussed in the previous paragraphs.
Table 2.
Halt (HALT). The bidirectional HALT line, when driven by an
external device, will cause. the processor to stop at the completion of the current bus cycle. Halting the processor using HALT
causes all control signals to go inactive and all three-state lines
to go to their high-impedance state. Refer to BUS ERROR AND
HALT OPERATION paragraph for additional information about
the interaction between the HALT and BERR signals.
When the processor has stopped executing instructions, such
as in a double bus fault condition, the HALT line is driven by
the processor to indicateto external devices that the processor
has stopped. Refer to paragaph on Double Bus Faults.
1-6
Function Code Outputs
FC2
FCl
FCD
Cycle Type
Low
Low
Low
(Undefined, Reserved)
Low
Low
High
User Data
Low
High
Low
User Program
Low
High
High
(Undefined, Reserved)
High
Low
Low
(Undefined, Reserved)
High
Low
. High
High
High
Low
Supervisor Program
High
High
High
Interrupt Acknowledge
Supervisor Data
16-Bit MPU
R68000
Table 3.
Signal Summary
HI-Z
Signal Name
Mnemonic
Active State
On HALT
On BGACK
Oulput
High
Yes
Yes
Input/Output
A1.-A23
Address Bus
Data Bus
DO-D15
Input/Output
High
Yes
Yes
Address Strobe
AS
Output
Low
No
Yes
No
Yes
Yes
ReadlWrite
RNi
Output
Read-High
Write-Low
Upper and Lower Data Strobes
UDS, LDS
Output
Low
No
Data Transfer Acknowledge
DTACK
Input
Low
No
No
Bus Request
BR
Input
Low
No
No
Bus Grant
BG
Output
Low
No
No
Bus Grant Acknowledge
BGACK
Input
Low
No
No
Interrupt Priority Level
IPLO, IPL1, IPL2
Input
Low
No
No
Bus Error
BERR
Input
Low
No
No
Reset
RESET
Input/Output
low
No'
No'
Halt
HALT
Input/Output
low
No'
No'
Enable
E
Output
High
No
No
Valid Memory Address
VMA
Output
low
No
Yes
Valid Peripheral Address
VPA
Input
low
No
No
Function Code Output
FeO, FC1, FC2
Output
High
No
Yes
Clock
ClK
Input
High
No
No
Power Input
VCC
Input
-
-
Ground
GND
Input
-
-
-
-"-
'Open drain,
REGISTER DESCRIPTION AND DATA
ORGANIZATION
OPERAND SIZE
STATUS REGISTER. The status register contains the eight level
interrupt mask as well as the cOl1dition codes; extend (X),
negative (N), zero (Z),· overflow (V), and carry (C), Additional
mode
status bits indicate that the processor is in a trace
andlor in a supervisor (8) state,
Operand sizes are defined as follows: a byte equals 8 bits, a
word equals 16 bits, and a long word equals 32 bits, The operand
size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation, Implicit
instructions support some subset of all three sizes,
(n
.
SYSTEM BYTE
15
13
.
•
10
DATA ORGANIZATION IN REGISTERS
USER BYTE'
8
The eight data registers support data operands of I, 8, 16, or
32 bits, The seven address registers together with the active
stack pointer support address operands of 32 bits,
1
4
0
IT~S~12Hlo~xINlzlvlcl
,TRACE MODE
I
I
----r-'
INTERRUPT
SUPERVISOR
MASK
STATE
DATA REGISTERS. Each data register is 32 bits wide, Byte
operands occupy the low order bits, Word operands the low
order 16 bits, and long word operands the entire 32 bits, The
least significant bit is addressed as bit zero; the most significant bit is addressed as bit 31, When a data register is used
as either a source or destination operand, only the appropriate
low-order portion is changed; the remaining high order portion
is neither used nor changed,
11\
EXTEND
NEGATIVE
ZERO
a
OVERFLOW
CARRY
'CONDITION CODE REGISTER
Status Register
1-7
R68000
16-Bit MPU
15
14
13
12
11
10
9
7
8
6
5
4
3
2
o
WORD 100000
BYTE 000000
BYTE 000001
WORD tOOO02
BYTE 000002
BYTE 000003
7
I
I
"-
WORD FFFFFE
I
BYTI; FFFFFE
Figure 2.
BYTE FFFFFF
Word Organization In Memory
The address and data buses are separate parallel buses which
transfer data using an asynchronous bus structure. In all cycles,
the bus master assumes responsibility for deskewing al" signals
it issues at both the start and end of a cycle. In addition, the
bus master is responsible for deskewing the acknowledge and
data signals from the slave device.
ADDRESS REGISTERS. Each address register and the stack
pOinter is 32 bits wide and holds a full 32-bit address. Address
registers do not support byte sized operands. Therefore, when
an address register is used asa source operand, either the low
order word or the entire long word operand is used depending
upon the operation size. When an address register is used as
the destination operand, the entire register is affected regardless
of the operation size. If the operation size is word, any other
operands are sign extended to 32 bits before the operation is
performed.
The following paragraphs explain the read, write, and readmodify-write cycles. The indivisible read-modify-write cycle is the
method used by the R68000 for interlocked multiprocessor
communications.
DATA ORGANIZATION IN MEMORY
Read Cycle. During a read cycle, the processor receives data
from memory or a peripheral device~ The processor reads bytes
of data in all cases, and for a word (or double word) operation,
the processor reads both upper and lower bytes simultaneously
by asserting both upper and lower data strobes. When the
instruction specifies byte operation, the processor IISesan
internal AD bit to determine which byte to read and then issues
the data strobe required for that byte. When the AD bit equals
zero, the upper data strobe is issued,and when the AD bit equals
one, the lower data strobe is issued. The processor borrectly
positions the received data inte-rnally.
.
Bytes are individually addressable with the high order byte
having an even address the same as the word, as shown in
Figure 2. The low order byte has an odd address that is one
higher than the word address. Instructions and multi-byte data
are accessed only on word (even byte) boundaries. If along word
datum is located at address n (n even), then the second word
of that datum is located at address n + 2.
The .data types supported by the R68000 are: bit data, integer
data of 8, 16,or 32 bits, 32-bit addresses and binary coded
decimal data. Each of'these data types is Pllt in memory, as
shown in Figure 3. The numbers indicate the order in which data
is accessed from the processor.
A word read cycle flow chart is given in Figure 4. A byte read
cycle flow chart is given in Figure 5. Read cycle timing is given
in Figure 6. Figure 7 details word and byte read cycle operations.
BUS OPERATION
Write Cycle. During.a write cycle, the processor sends bytes
of data to memory or a peripheral device. If the instruction
specifies a word operation, the processor writes both bytes.
When the instruction specifies.a byte operation, the processor
uses an internal AD bit to determine which byte to write and then
issues the data strobe required for that byte. When the AD bit
equals zero; the upper data strobe is issued and when the AD
bit equals one, the lower data strobe is issued. A word write cycle
flow chart is given in Figure 8. A byte write cycle flow chart is
given in Figure 9. Write cycle timing is given in Figure 6.
Figure 10 details word and byte write cycle operation.
The following paragraphs explain control signal and bus operation during data transfer operations, bus arbitration, bus error
and halt conditions, and reset operation. .
.
DATA TRANSFER OPERATIONS. Transfer of data between
devices involves the following signals:
• Address Bus A1 through A23
• Data Bus DO through 015
• Control Signals
1-8
R68000:,
16-B.it MPU
BIT DATA
1 BYTE = 8 BITS
7
5
6
o
2
3
4
INTEGER DATA
1 BYTE = 8 BITS
15
14
13
I
12
11
9
10
8
MSB
6
7
BYTE 0
LSB
BYTE 2
4
5
I
3
2
0
2
0
BYTE 1
BYTE 3
1 WORD = 16 BITS
; 15
14
13
12
11
10
9
7
8
6
,4
5
3
WORD 0
I"·
UBI
WORD 1
WORD 2
1 LONG WORD = 32 BITS
14
15
13
12
11
10
9
MSB
8
7
4
5
6
HIGH ORDER
. LONG WORD 0 -
-
-
-
-
-
LONG WORD 1 - -
-
LONG WORD 2 - -
-
-
-
-
LSB
-----
-
-
-
-
-
0
------
---
LOW ORDER
--
2
3
-
- - ----
-
-
-
-
-
-
-
-
-
-
ADDRESSES
1 ADDRESS
32 BITS
=
15
14
13
12
11
10
9
MSB
-
8
7
6
4
5
o
2
3
HIGH ORDER
ADDRESS 0- -
-
-
-
LOW ORDE"
ADDRESS 1 - -
-
-
-ADDRESS 2- -
~---
-
-
-
-
-' -
LSB
-
-
~
-
-
-
-
~
-
-
-
-
-'-
MSB = MOST SIGNIFICANT BIT
LSB = LEAST SIGNIFICANT BIT
DECIMAL DATA
2 BINARY CODED DECIMAL DIGITS
15
14
MSD
13
12
11
10
9
BCD,O
BCD 1
BCD 4
BCD 5
8
7
LSD
6
=
1 BYTE
5
4
BCD 6
BCD 7
=
Data Organization In Memory
1·9
2
BCD 3
MSD
MOST SIGNIFICANT DIGIT
LSD = LEAST SIGNIFICANT DIGIT
Figure 3.
3
BCD 2'
o
16-BitMPU
R68000
BUS MASTER
BUS MASTER
ADDRESS DEVICE
ADDRESS DEVICE
1)
2)
3)
4)
5)
SLAVE
SET R/W TO READ
PLACE FUNCTION CODE ON FCO-FC2
PLACE ADDRESS ON A1-A23_
ASSERT ADDRESS STROBE (AS)_
ASSERT UPPER DATA STROBE (UDS) AND
LOWER DATA STROBE (LOS)
1)
2)
3)
4)
5)
,
SET R/W TO READ
PLACE FUNCTION CODE ON FCO-FC2
PLACE ADDRESS ON A1-A23
ASSERT ADDRESS STROBE (AS)_
ASSERT UPPER DATA STROBE (UDS) OR
LOWER DATA STROBE (LOS) (BASED ON AO)
,
I
INPUT DATA
INPUT DATA
1) DECODE ADDRESS
2) PLACE DATA ON 00-07 or 08-015 (BASED ON
UDS OR LOS)
3) ASSERT DATA TRANSFER ACKNOWLEDGE
(DTACK)
1) DECODE ADDRESS
2) PLACE DATA ON 00-015
3) ASSERT DATA TRANSFER ACKNOWLEDGE
(DTACK)
,
I
+
ACQUIRE DATA
1) LATCH DATA
2) NEGATE UDS AND LOS
3) NEGATE AS
ACQUIRE DATA
1) LATCH DATA
2) NEGATE UDS ORILDS
3) NEGATE AS
,
TERMINATE CYCLE
,
TERMINATE CYCLE
,
1) REMOVE DATA FROM 00-015
2) NEGATE DTACK
1) REMOVE DATA FROM 00-015 OR 08-015
2) NEGATE DTACK
START NEXT CYCLE
Figure 4_
I
START NEtT CYCLE
Figure 5.
Word Read Cycle Flow Chart
Read-Modify-Write Cycle. The read-modify-write cycle performs
a read, modifies the data in the arithmetic-logic unit, and writes
the data back to the same address. In the R68000 this cycle
is indivisible in that .the address strobe is asserted throughout
the entire cycle. The test and set (TAS) instruction uses this cycle
to provide meaningful communication between processors in a
multiple processor environment. TAS is the only instruction that
uses the read-modify-write cycles. Since the test and set instruction only operates on bytes, all read-modify-write cycles are byte
operations. A read-modify-write cycle flow chart is given in
Figure 11 and a timing diagram is given in Figure 12.
Byte Read Cycle Flow Chart
Figure 13 is a flow chart showing the detail involved in a request
from a single device. Figure 14 is a timing diagram for the same
operation. This technique allows processing of bus requests during data transfer cycles.
The timing diagram shows that the bus request is negated at
the time that an acknowledge is asserted. This is true for a
system consisting of the processor and one device capable of
bus mastership. However, in systems having a number of
devices capable of bus mastership, the bus request line from
each device is ORed to the processor. In this system, it is easy
to see that there could be more than one bus request being
made. The timing diagram shows that the bus grant signals
negate a few clock cycles after the transition of the acknowledge
(BGACK) signal.
BUS ARBITRATION. Bus arbitration is a technique used by
master-type devices to request,be granted, and knowledge bus
mastership. In its Simplest form, it consists of:
1. asserting a bus mastership request,
2. receiving a grant that the bus is available at the end of the
current cycle, and
3. acknowledging that mastership has been assumed.
However, if the bus requests are still pending, the processor will
assert another bus grant within a few clock cycles after negation. This additional assertion of bus grant allows external arbitration circuitry to select the next bus master before the current
bus master has completed its requirements. The following paragraphs provide additional information about the three steps in
the arbitration process.
1-10
16-Bit MPU
R68000
ClK
~~~
AS
\
UDS
\
\
lOS
H ______~~__~r
H
______~~~
____~~~
I
I
I
\
R/W
OTACK
08-015
00-07
FCO-FC2
\
I
(
)
)
\~----------~~;--
\
I
J
\
r--\
\
\~
____________
I
I
\
~r-
r-
\
r
~~~~3}=:=
__________________ r
=::x
X
(
(
(
)
(
C
)
~
~r
X
I-
Figure 6.
.1
..
.. I..
READ
WRITE - -....
~II 4 - - - - - S l 0 W READ
Read and Write Cycle Timing Diagram
SO Sl S2 S3 S4 S5 S6 S7 SO Sl S2 S3 S4 S5 S6 S7 SO Sl S2 S3 S4 S5 S6 87
AO"
AS
\
UOS
\
lOS
RIW
\
I
I
\
I
\
\
(
)
00-07
(
>
FCO-FC2
I
==><_______ X
I---- WORD REAO-........*'I-I... ODD BYTE READ
....J
"INTERNAL SIGNAL ONLY
Figure 7.
\
I
(
rr-
\
I
r--\
OTACK
08-015
>-
H
H
I
\
(
>
>----
r-
X
·1 ..
r-
EVEN BYTE READ--l
Word and Byte Read Cycle Timing Diagram
Receiving the Bus Grant. Normally the processor asserts bus
grant (BG) as soon as possible after internal synchronization. The
only exception occurs when the processor has made an internal decision to execute the next bus cycle but has not progressed
far enough into the cycle to have asserted the address strobe
(AS) signal. In this case, bus grant will not be asserted until one
clock after address strobe is asserted to indicate to external
devices that a bus cycle is being executed.
Requesting the Bus. External devices capable of becoming bus
masters request the bus by asserting the bus request (BR) signal.
This ORed signal (although it need not be constructed from open
collector devices) indicates to the processor that some external
device requires control of the external bus. The processor, at
a lower bus priority level than the external device, will relinquish
the bus after it has completed the last bus cycle it has started.
If no acknowledge is received before the bus request signal goes
inactive, the processor will continue processing when it detects
that the bus request is inactive. This allows ordinary processing
to continue if the arbitration circuitry inadvertently responded
to noise.
The bus grant signal may be routed through a daisy-chained
network or through a specific priority-encoded network. The processor is not affected by the external method of arbitration as
long as the protocol is obeyed.
1-11
R68000
16-Bit MPU
BUS MASTER
SLAVE
BUS MASTER
ADDRESS DEVICE
1)
2)
3)
4)
5)
6)
PLACE FUNCTION CODE ON FCO·FC2
PLACE ADDRESS ON A1-A23_
ASSEI!I ADDRESS STROBE (AS)
Set R/W TO WRITE
PLACE DATA ON 00-015
ASSERT UPPER DATA STROBE (UDS) AND
LOWER DATA STROBE (LOS)
PLACE FUNCTION CODE ON FCO·FC2
PLACE ADDRESS ON A1-A23
ASSEI!I ADDRESS STROBE (AS)
Set RIW TO WRITE
PLACE DATA ON 00-07 or 08-015 (ACCORDING
TO AO)
6) ASSERT UPPER DATA STROBE (UDS) OR
LOWER DATA STROBE (LOS) (BASED ON AO),
,
INPUT DATA
INPUT DATA
1) DECODE ADDRESS
2) STORE DATA ON 00-015
3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)
1) DECODE ADDRESS
2) STORE DATA ON 00-07 if LOS IS ASSERTED
STORE DATA ON 08-015 IF UDS IS ASSERTED
3) ASSERT DATA TRANSFER
ACKNOWLEDGE. (DTACK)
I
•
1) NEGATE UDS AND LOS
2) NEGATE AS
3) REMOV.E. DATA FROM 00-015.
4) SET R/W TO READ
I
•
TERMINATE OUTPUT TRANSFER
TERMINATE OUTPUT TRANSFER
1)
2)
3)
4)
t
NEGATE UDS OR LOS
NEGATE AS
REMOV.E. DATA FROM 00-07 OR 08-015
SET R/W TO READ
t
TERMINATE CYCLE
1) NEGATE DTACK
TERMINATE CYCLE
1) NEGATE DTACK
I
•
I
1)
2)
3)
4)
5)
,
•
START NEXT CYCLE
Figure 8.
SLAVE
ADDRESS DEVICE
START NEXT CYCLE
Figure 9.
Word Write Cycle Flow Chart
Byte Write Cycle Flow Chart
SO Sl S2 S3 S4 S5 S6 S7 SO Sl S2 S3 S4 S5 S6 S7 SO Sl S2 S3 S4 S5 S6 S7
AO'
AS~
UDS
\
I
I
LOS
\
I
08-015
00-07
FCO·FC2
==>--<
==>--<
\
r\
\
I
(
>
R/WJ\
DTACK
I
\
\
)
.J(
(
X
\
I
I
\
;-
\
I
r\
I
>
>
X
r
(
(
'INTERNAL SIGNAL ONLY
I----
WORD WRITE
Figure 10.
.. I..
ODD BYTE WRITE
"I"
EVEN BYTE WRITE-.j
Word and Byte Write Cycle Timing Diagram
1-12
>
>
>
I
16-Bit MPU
R680aa
,
BUS MASTER
ADDRESS DEVICE
1)
2)
3)
4)
5)
SET Rffl TO READ
PLACE FUNCTION CODE ON FCO-FC2
PLACE ADDRESS ON A1-A23_
ASSERT ADDRESS STROBE (AS)_
ASSERT UPPER DATA STROBE (UDS) OR
LOWER DATA STROBE (LDS)
INPUT DATA
1) DECODE ADDRESS
2) PLACE DATA ON DO-D7 OR D8-D15
3) ASSERT DATA TRANSFER ACKNOWLEDGE
(DTACK)
,
I
f
ACQUIRE DATA
TERMINATE CYCLE
1) LATCH DATA
2) NEGATE UDS OR LDS
3) START DATA MODIFICATION
1) REMOVE ~ROM DO-D7 OR D8-D15
2) NEGATE DTACK
I
+
I
•
START OUTPUT TRANSFER
1) SET RJW TO WRITE
2) PLACE DATA ON DO-D7 or D8-D1~
3) ASSERT UPPER DATA STROBE (UDS) OR
LOWER DATA STROBE (LDS)
INPUT DATA
1) STORE DATA ON DO-D7 OR D8-D15
2) ~SERT DATA TRANSFER ACKNOWLEDGE
(DTACK)
I
t
i
TERMINATE OUTPUT TRANSFER
1) NEGATE UDS OR LDS
2) NEGATE AS
3) REMOVE. DATA FROM DO-D7 OR D8-D15
41 SET RIW TO READ
TERMINATE CYCLE
1) NEGATE DTACK
,
I
START NEXT CYCLE
Figure 11.
Read-Modify-Write Cycle Flow Chart
CLK
~==============~--~I
1
\I--__....;Ir-----
AS
\'--______
UDS OR LDS - - - - - - \
RIW
DTACK
\ ; - - -
1
\
\;---
D8-D15~:==~(
~~~:)t=====:j(~~~~}=x
C"
FCO-FC2
'"'1
._
..
. . . , - - - - - - -
Figure 12.
INDIVISIBLE CYCLE
--------~~I
Read-Modify-Write Cycle Timing Diagram
1-13
16-Bit MPU
R68000
The bus request from the granted device should be dropped"after
bus grant acknowledge ,.is asserted. If a bus request is still
pending, another bus grant will be asserted within a few clocks
of the negation of bus grant. Refer to Bus Arbitration Control
section. The processor dO,esriot perform any external bus cycles
before it reasserts bus grant.
REQUESTING DEVICE
PROCESSOR
REQUEST THE BUS
1) ASSERT BUS REQUEST (BR)
•
I.
GRANT BUS ARBITRATION
. 1) ASSERT BUS GRANT (BG)
I
1
BUS ARBITRATION CONTROL. The bus arbitration control unit
in the R68000 is implemented with a finite state machine. A state
diagram of this machine is shown in Figure 15. All asynchronous
signals to the R68000 are synchrOnized before being used internally. This synchronization is accomplished in a maximum of
one cycle of the system clock, assuming that the asynchronous
input setup time (#47) lias been met (see Figure 16). The input
signal is sampled on the falling edge of the clock and is valid
internally after the next falling edge. If BR and BGACK meet
the asynchronous set-up time tASI (#47), then tBGKBR (#37A)
can be ignored. If BR and BGACK are asserted asynchronously
with respect to the clock, BGACK has to be asserted before BR
is negated.
+
ACKNOWLEDGE BUS MASTERSHIP
1) EXTERNAL ARBITRATION DETERMINES
NEXT BUS MASTER
2) NEXt BUS MASTER WAITS FOR CURRENT CYCLE TO .COMPLETE
3) NEXT BUS MASTER ASSERTS BUS
GRANT ACKNOWLEDGE (BGACK) TO
TO BECOME NEW MASTER
4) BUS MASTER NEGATES BR
I
I
+
TERMINATE ARBITRATION
1) NEGATE BG (AND WAIT FOR
BGACK TO BE NEGATED)
I
As shown in Figure 15, input signals labeled R and A are inter"
nally synchronized on the bus Jequest and bus grant
acknowledge pins respectively. The bus grant output is labeled
"G and the internal three-state control Signal T. If T is true, the
address, data, and control buses are placed in a high-impedance
state when AS is negated. All signals-sre shown in positive logic
(active high) regardless of their true active voltage level.
1
•
OPERATE AS BUS MASTER
1) PERFORM DATA TRANSFER (READ AND
WRITE CYCLES) ACCORDING TO THE
SAME RULES THE PROCESSOR USES.
State changes (valid outputs) occur on the next rising clock edge
alter the internal signal is valid.
+
RELEASE BUS MASTERSHIP
1) NEGATE BGACK
I
+
RE-ARBITRATE OR RESUME
PROCESSOR OPERATION
Figure 13.
A timing diagram of the bus arbitration sequence during a
processor bus cycle is shown in Figure 17. The bus arbitration
sequence while the bus is inactive (i.e., executing internal operatiOns such as a multiply instruction) is shown in Figure 18.
I
If a bus request (BR) is made at a time when the MPU has
already b~n a bus cycle but AS has not been asserted (bus
state SO). BG will not be asserted on the next riSing edge. Instead
BG will be delayed until the second rising edge follOWing its internal assertion. This sequence is shown in Figure 19.
Bus Arbitration Cycle Flow Chart
Acknowledgment of Mastership. Upon receiving a bus grant
(BG), the requesting device waits until address strobe (AS), data
transfer acknowledge (DTACK), and bus grant acknowledge
(BGACK) are negated before issuing its own BGACK. The negation olthe address strobe indicates that the previous master has
completed its cycle, while the negation of bus grant acknowledge
indicates that the previous master has released the bus. (I'
address strobe is asserted no device is allowed to "break into"
a cycle.) The negation of data. transfer acknowledge indicates
the previous slave has terminated its connection to the previous
master. In some applications data transfer acknowledge may
not be required. In this case the devices would use the address
strobe. When bus grant acknowledge is issued the device is bus
master. Only after the bus cycle(s) is (are) completed should bus
grant acknowledge be negated to terminate bus mastership.
BUS ERROR AND HALT OPERATION. In a bus architecture
that requires a handshake from an external device, the possibility
exists that the handshake might not occur. Since different
systems will require a different maximum response time. a bus
error input is provided.
External circuitry must be used to determine the duration
between address strobe and data transfer acknowledge before
issuing a bus error signal. When a bus error signal is received,
the processor has two options: initiate a bus error exception
sequence or try running the bus cycle again.
1-14
R68000
16-Bit MPU.
I
BG
BGACK
I
\
I
\
\
I
PROCESSOR~ DMA DEVICE
Figure 14.
I
\
\
·1--
PROCESSOR
·1--
DMA DEVICE
•
Bus Arbitration Cycle Timing Diagram
RA
INTERNAL SIGNAL VALIDl
EXTERNAL SIGNAL~
SAMPLED
, ,
CLK
I
BGACK----~------~
'THIS DELAY TIME IS EQUAL TO PARAMETER #33, tCHGL
Figure 16. Timing Relationship of External
Asynchronous Inputs to Internal Signals
R
A
G
T
X
= BUS REQUEST INTERNAL
=
Bus Error Operation .. WhenBERR is asserted, the current bus
cycle is terminated. If BE:RR is asserted before the falling edge
. of 82, A8 will be negated in 87 in either a read or write cycle.
As long as BERR remains asserted, the data and address buses
will be in the high-impedance state. When BERR is negated,
the processor will begin stacking for exception processing.
Figure 20 is a timing diagram for the exception sequence. The
sequence is composed of the following elements:
1. stacking the program counter and status register,
2. stacking the error information,
3. reading the bus error vector table entry, and
4. executing the bus error handler routine.
BUS GRANT ACKNOWLEDGE INTERNAL
= BUS GRANT
= THREE-STATE CONTROL TO BUS CONTROL LOGIC2
= DON'T CARE
1. STATE MACHINE WILL NOT CHANGE STATE IF BUS IS
IN SO OR Sl. REFER TO BUS ARBITRATION CONTROL
FOR ADDITIONAL INFORMATION.
2. THE ADDRESS BUS WILL BE PLACED IN THE HIGH
IMPEDANCE STATE IF T IS ASSERTED AND AS
NEGATED.
Figure 15.
State Diagram of R68000 Bus
Arbitration Unit
1-15
R68000
16-Bit MPU
BUS THREE STATED--------,
BG ASSERTED
BR VALID INTERNAL
BR SAMPLED
BR ASSERTED
BUS RELEASED FROM THREE
STATE AND PROCESSOR
STARTS NEXT BUS CYCLE
BGACK NEGATED INTERNAL
BGACK SAMPLED
BGACK NEGATED
CLK
SO S1 S2 S3 S4 S5 S6 S7
BR
\
BG
/
\
BGACK
)
AS
\
UDS
\
\
LDS
Rfiii
==x
}-C
(
r
r
r
(
)C
PROCESSOR
r--
\
'---/
..
r-r-r--
~
~
~
)
DTACK
DO·D15
I
\
A1·A23
FCII-FC2
SO S1 S2 S3 S4 S5 S6 S7 SO S1
/
-I-
ALTERNATE BUS MASTER
.. I-
PROCESSOR
..
Figure 17. Bus Arbitration During Processor Bus Cycle
BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE----.,
BGACKNEGATED _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.,
ill
BClASSERTED AND BUS THREE STATED
BR VALID INTERNAL _ _ _ _ __
SR SAMPLED - - - - - - - BR ASSERTED--------;r,.
CLK
$0 S1 S2 S3 S4 55 S& S7
SO 51 S2 S3 S4
BR _____~__________~\======~~/
BG
\
/
BGACK------~---------~--~~=\\----J
/
' - - - _ __ _ J
A1.A23=~=:j~~========~~==========~========================;=~(~~===
AS
r---\
I
\
-----,
~_ _~_ _ _ _ ___,.'
L~
\
I
\
/
UDS'
LDS
F<;:'tFC::2
r-----------~
__________________
__'~
":Y..===========~)~----------_C===
_________ J - - - -
·WW----------~--~
DTACK----~'----!r----------------------~--------~~'---
DII-D15--~:::::::(C=======»:.~::::~-----~::=:::~:::::_-~~:::::::_
PROCESSOR
• I.. BUS INACTIVE .. I ...
ALTERNATE BUS MASTER
_ I ':ROCESSO~
Figure 18.
Bus Arbitration with Bus Inactive
1-16
16-Bit MPU
R68000
BUS RELEASED FROM THREE
STATE AND PROCESSOR
STARTS NEXT BUS CYCLE - - - - - - ,
BGACK NEGATED INTERNAL
BGACK SAMPLED -------,
BGACK NEGATED
BR ASSERTED
BR SAMPLED
BUS THREE S T A T E O l l
BG ASSERTED
BR VALID INTERNAL
SO S1 S2 S3 S4 S5S6 S7 SO S1
SO S1 S2 S3 S4 S5 S6 S7
BR~_~========~------__~I
BG ____________\~====~----~I
BGACK
A1·A23
AS
\
/
==r-<2~~;====~)~'=-=-=-=-=-====~~---:=i(;=====;~~=i:
-.I
-.I
LDS -.I
\'--__--'!''----------------.....J~'________'I
\!'
~
Ir--\!'
~
UDS
r-C
FCO.FC2~)
RAM--fr------------------~~--------------------~/r----------------------
DTACK=~~_~~~~~{:=====~---~~~~-----\~====c===I=====
DO·D15
..
PROCESSOR
Figure 19.
•
I..
ALTERNATE BUS MASTER
•
I..
PROCESSOR
Bus Arbitration During Processor Bus Cycle Special Case
\~---------------~J./~-----'
\
AS
LOS UDS -------,\
RtW
\
DTACK--------------------------------~------------~
DO·D15
FCO·2
BERR
\
=::::==~(~~~~~~~~~~~~~~~~.=:j~~---.. ....:.========
=x=:!....;:=========:::;:-_______
--,_-:I'-.
~.
\
HALT--~---------~~================~·~--~---, INITIATE,
.. READ" ""
,
I...
INITIATE BUS
~""
...f-----BUS ERROR DETECTION ---I.~ ""~ER-R-O..;;.R.:..;;S.;;;;T-"A-'-C..;;.KI-NG
RESPONSE FAILURE-l...
Figure 20.
Bus Error Timing Diagram
1·17
16-Bit MPU
R68000
The single-step mode, derived from correctly timed transitions
on the HALT signal input, forces the processor to execute a
single bus-cycle by entering the "run" mode until the processor
starts abus cycle then changing to the "halt" mode. Thus, the
single-step mode allows the user to proceed through (and
therefore debug) processor operations one bus cycle at a time.
The stacking of the program counter and the status register is
identical to the interrupt sequence. Several additional items are
stacked when a bus error occurs. These items are used to determine the nature of the error and correct it, if possible. The bus
error vector is vector number two located at address $000008.
The processor loads the new program counter from this location. A software bus error handler routine is then executed by
the processor. Refer to EXCEPTION PROCESSING for additional information.
Figure 22 details the timing required for correct single-step
operations. Some care must be exercised to avoid harmful interactions between BERR and HALT when using the single cycle
mode as a debugging tool. This is also true of interactions
between.the HALT and RESET lines since these can reset the
machine.
Re-Running the Bus Cycle. When, during a bus cycle, the
processor receives a BERR, and HALT is being driven by an
external device, the processor enters the re-run sequence.
Figure 21 is a timing diagram for re-running the bus cycle.
When the processor completes a bus cycle after recognizing
that HALT is active, most three-state signals are put in the highimpedance state. These include:
1. address lines, and
2. data lines.
The processor terminates the bus cycle, then puts the address
and data outpu!lines in the high-impedance state. The processor
remains "halted" and will not run another bus cycle untilexternal logic negates HALT. Then the processor will re-run the
previous bus cycle using the same address, the same function
codes, the same data (for a write operation), and the same controls. BERR should be negated at least one clock cycle before
HALT is negated.
This is required for correct performance of the re-run bus cycle
operation.
Honoring the halt request has no effect on bus arbitration. Only
the bus arbitra.tion function removes the control signals from the
bus.
Note
Total debugging flexibility is derived from the software debugging
package, the halt function, and the hardware trace capability.
These processor capabilities allow the hardware debugger to
trace single bus cycles or single instructions at a time.
The processor will not re-run a read-modify-write cycle.
This restriction is made to guarantee that the entire cycle
runs correctly and that the write operation of a Test-andSet operation is performed without ever releasing AS. If
BERR and HALT are asserted during read-modify-write
bus cycle, a bus error operation results.
a
Double Bus Faults. When a bus error exception occurs, the
processor will attempt to stack several words containing information about the state of the machine. If a bus error exception
occurs during the stacking operation, there have been two bus
errors in a row, or a double bus fault. A,double bus fault causes
the processor to halt. Once a bus error exception has occu rred,
any bus error exception occurring before the execution of the
next instruction constitutes a double bus fault.
Halt Operation with No Bus Error. The HALT input signal to
the R680DO performs a Halt/Run/Single-Step function in a similar
fashion to the R6S00 halt functions. When the HALT signal is
constantly active the processor "halts" (does nothing) and when
the HALT signal is constantly inactive the processor "runs"
(does something).
\ _____--.J!
r-~-~~---~~--~\
!~---
\
r::====~;;;;;;~)~=====================:(~~~~~
====~
__~X~======~==============~x====
'-----'---t., eeoc, ' ..'ODi.lt::----------------.10(
Figure 21.
I""'...
HAL T - - - - - - 1.... f----RE-RUN
Re-Run Bus Cycle Timing Diagram
1-18
----.-.11
R68000
16-Bit MPU
f
1'----
\""' _ _ _..J
r-----------------~\
~----------------~I
...
,-----'lo+ot----..... HALT - - - - I
.•
~I ---READ
Figure 22.
-----.l>il
Halt Signal Timing Waveforms
THE RELATIONSHIP OF DTACK, BERR, AND
HALT
Note that a bus cycle which is re-run does not constitute a bus
error exception, and does not contribute to a double bus fault.
This means that as long as the external hardware requests it,
the processor will continue to re-run the same bus cycle.
In order to properly .control termination of a bus ~for are-run
or a bus error condition, DTACK, BERR, and HALT should be
asserted and negated on the rising edge of R68000 clock. This
will assure that when two signals are asserted simultaneously,
the required setup time (#47) for both of them will be met during
the same bus state.
The bus error (BERR) pin also has an effect on processor operation after the processor receives an external reset input. The
processor reads the vector table atter a reset to determine the
address.to start program execution. If a bus error occurs while
reading the vector table (or ,at.any time before the first instruction is executed), the prOCeSsor reacts as if a double bus fault
has occurred and it halts. Only an external reset will start a halted
processor.
This, or some equivalent precaution, should be designed external to the R680oo. Parameter #48 is intended to ensure this
operation in a totally asynchronous system, and may be ignored
if the above conditions are met.
RESET OPERATION. The reset signal is a bidirectional signal
that allows. either the processor or an external signal to reset
the system. Figure 23 is a timing diagram for reset operations.
Both HALT and RESET must be applied to ensure total reset
of the processor.
The preferred bus cycle terminations may be summarized as
follows (case numbers refer to Table 4):
Normal, Termination: DTACK occurs first(case1).
Halt Termlnatlo.n: HALT is asserted at same time, or precedes
DTACK (no BERR) cases 2 and 3.
When the RESET and HALT are driven by an external device
the entire system, including the processor, is reset. The
processor responds by reading the rellet vector table entry (vector number zero, address $000000) and loads it into the supervisor stack pointer (SSP). Vector table entry number one at
address $000004 is read next andl~ed into the program
counter. The processor initializes the status register to an interrupt lev\ill of seven, with no other register being affected.
Bus Error Termination: BERR is asserted in lieu of, at same
time, or preceding DTACK (case 4); BERR negated at same
time, or after DTACK.
Re-Run Termination: HAlT and BERR asserted in lieu of, at
the same time, or pefore DTACK (cases 6 anli 7); HALT must
be negated at least one cycle after BERR. (Case 5 indicates
BERR may precede HALT which allows fully asynchronous
assertion).
Execution. of the RESET instruction drives the reset pin low for
124 clock periods. In this case, the processor is trying to reset
the rest of the system. The internal state of the processor, including the processor's internal registers and the status register, is
unaffected by the execution of a RESET instruction. AII.external
devices connected to the reset line will be reset at the completion of the RESET instruction.
Table 4 d6taiis the resulting bus cycle termination under various
combinations of control signal sequences. The negation ofthese
same control signals under several conditions is shown in
Table 5. (DTACK is assumed to be negated normally in all
cases; for best results, both DTACK and BERR should be
negated when address strobe is negated).
Asserting RESET and HALT for 10 clock cycleS Will cause a
processor reset; except when Vcc is initially applied to the
processor. In this case, an external reset must be applied for
100 milliseconds.
Example A: A system uses a watch-dog timer to terminate
accesses to unpopulated address space: The timer asserts
DTACK and BERR simultaneously after timeout (case 4).
1-19
16-BitMPU
R68000
CLK
PLUS 5 VQLTS
VCC
RESET
HALT
l~
____________________~__-"
1----11 <4 CLOCKS
BUS CYCLES XX'fX)QO(~W~)(.X)~------------'---'--z.
__...x__.JL
2
NOTES:'
1) INTERNAL START-UP TIME
2) SSP HIGH READ.IN HERE
3) SSP LOW READ IN HERE
4) PC HIGH READ IN HERE
5) PC LOW READ IN HERE
6) FIRST .INSTRUCTION FETCHE.D HERE.
Figure 23.
3
4
5
6
"I:t/tX
BUS STATE UNKNOWN (ALL
. CONTROL SIGNALS INACTIVE)
>----:-< DATA BUS IN READ MODE
Reset Operation Timing Diagram
".
ExampleB: A system uses error detection on RAM contents.
Designer may (a) delay DTACK until data verified, and return
BEAR and HALT ~neously to ,re-run error cycle,lcase 6),
or if valid, return DTACK (case 1); (b) delay, DTACK until data
verified and return B~R at same time. as
if da.ta in
error (case 4).
.
The BERA signal is allowed to be asserted after the. DTACK
signal is asserted. SERR must be asserted within the time given
as parameter #48 after DTACK is asserted in anya!3ynchronous
system to insure proper operation, If this max.imum delay time
is violated, the pr0t;essor may exhibit, erratic behavior.
i5l'ACi<
Synchronous Opttratipn
To allow for those systems 'which use the system clock as a
signal to·generate DTACK 'and 'other asynchronous inputs; the
asynchronous inputs setup time is given as parameter #47. If
thiS'setup is met on an input, such as DTACK, the processor is
guaranteed to recognize that signal on the next falling edge of
the system clock. However, the converse is not true-if the input
signal does not meet the setup time it is not guaranteed not to
be recognized. In addition, if DTACK is recognized on a falling
edge, valid data will be latched into the' processor (on a read
cycle) on lhe next falling edge provided that the data meets the
setup time given as Parameter #27. Given this, parameter #31
may be ignored. Note that if DTACK is asserted, with the required
setup time, before the falling edge of 54, no wait states will be
incurred and the bus cycle will run at its maximum speed of four
clock periOds.
ASYNCHRONOUS VERSUS SYNCHRONOUS
OPERATION
Asynchronous Operation
To achieve clock frequency independence at a 'system level, the
R68000 can be used in an asynchronous manner. This eilialls
using only the bus handshake lines (AS, UDS, LD$,,DTACK,
BERR, HALT, and VPA) ,to control tile data transfer. Using this
method, AS signals the start of a bus cycle and the dll-ta strobes
are used as a condition for valid data on a write cycle. The slave
device (memory or peripheral) then responds by placing the
requested data Pn the data bus for a read cycle or latching data
on a write cycle and asserting the data transfer aCknowledge
signal (DTACK) to terminate the bus cycle. If no slave reponds
or the access is invalid, external control logic asserts the BERR,
or BERR and HALT, signal to abort or rerun the bus cycle.
In order to assure proper operation in a synchronous system
when BEAR is asserted after DTACK, the following conditions
must be met. Within one clock cycle after DTACKwas recognized, BERR must meet the setup time parameter #27A prior
to the falling edge of the next clock. The setup time is critical
to proper operation, and the R68000 may exhibit erratic behavior
if'it is violated.
, Note
The DTACK signal is allowed to be asse.rted before t.he data from
a slave device is valid on a read cycle. The length of time that
DTACK.may precElde data is given as parameter #31 :(See
Figure 45) and it must lle met in any asynchronous system to
insure that valid data is lalched into the processor .. Notice that
there is no maximum time specified from the assertion of AS
to the assertion of DTACK. This is because the MPU
will insert wait cycles of one clock period each until DTACK is
recognized.
During an active bus cycle, VPA and BERR are sampled
on every falling edge of the clock starting with SO. DTACK
is sampled on every falling edge of the clock starting with
54 and data ilil latched on the falling edge of 56 during
a read. The bus cycle will then be .terminated i~ept
when BERR is asserted .in the absence of DTACK, in
which case it will terminate one clock cycle later in S!l.
1-20
16-Bit MPU
R68000
Table 4.
DTACK, BERR, HALT Assertion Results
Asserted on Rising
Edge of State
Case
No.
Control
Signal
N
1
DTACK
BERR
HALT
A
NA
NA
2
DTACK
BERR
HALT
A
NA
A
X
3
DTACK
BERR
HALT
NA
NA
A
A
NA
5
DTACK
BERR
HALT
X
X
4
A
NA
5
NA
5
DTACK
BERR
HALT
NA
A
NA
5
A
DTACK
BERR
HALT
X
X
6
A
A
5
5
7
DTACK
BERR
HALT
NA
NA
A
A
5
Legend:
N A NA X 5 -
5
Normal cycle terminate and continue.
X
X
5
Normal cycle terminate and hall. Continue when HALT removed.
5
Normal cycle terminate and hall. Continue when HALT removed.
Terminate and take
bu~
error trap.
X
Terminate and re-run.
--
Terminate and re-run when HALT removed.
X
Terminate and re-run when HALT removed.
the number of the current even bus state (e.g., 54, 56, etc.)
signal is asserted in this bus state
signal is not asserted in this state
don't care
signal was asserted in previous state and remains asserted in this state
Table 5.
Conditions of
TermInation In
Tabla 4-4
•
Resuit
N + 2
BERR AND HALT Negation Results
Negated on Rising
Edge of State
Control
Signal
Bus Error
BERR
HALT
Re-run
BERR
HALT
Re-run
BERR
HALT
Normal
BERR
HALT
Normal
BERR
HALT
N + 2
N
•
•
•
•
•
•
•
•
or
or
or
or
or
••
•
•
•
•
none
= 5ignal is negated in this bus state.
1-21
Resul.ts - Next Cycle
Takes bus error trap.
Illegal sequence; usually traps to vector number O.
Re-runs the bus cycle.
May lengthen next cycle.
If next cycle is started it will be terminated as a bus error.
16-Bit MPU
R68000
All exception processing is done in the supervisor state,
regardless of the setting of the S-bit. The bus cycles generated
during exception processing are classified as supervisor
references. All stacking operations during exception processing
use the supervisor stack pOinter.
PROCESSING STATES
The following paragraphs describe the actions of the R68000
which are outside the normal processing associated with the
execution of instructions. The functions of the bits in the supervisor portion of the status register are covered: the supervisor/user bit, the trace enable bit, and the processor interrupt
priority mask. The sequence of memory references and actions
taken by the processor on exception conditions are detailed.
USER STATE. The user state is the lower state of privilege. For
instruction execution, the user state is determined by negating
(low) the S-bit of the status register.
The R68000 is always in one of three processing states: normal, exception, or halted. The normal processing state
associated with instruction execution; the memory references
are to fetch instructions and operands, and to store results. A
special case of the normal state is the stopped state which the
processor enters when a STOP instruction is executed. In this
state, no further references are made.
Most instructions execute the same in user state as in the super·
visor state. However, some instructions which have important
system effects are made privileged. User programs are not per·
mitted to execute the STOP instruction, or the RESET instruc·
tion. To ensure that a user program cannot enter the supervisor
state except in a controlled manner, the instructions which
modify the whole state register are priviled. To aid in debugging
programs which are to be used as operating systems, the move
to user stack pOinter (MOVE to USP) and move from user stack
pointer (MOVE from USP) instructions are also privileged.
The exception processing state is associated with interrupts, trap
instructions, tracing and other exceptional conditions. The
exception may be internally generated by an instruction or by
an unusual condition arising during the execution of an instruction. Externally, exception Proceslling can be forced by an interrupt, by a bus error, or by a reset. Exception processing is
designed to provide an efficient context switch. so that the
processor may handle unusual conditions.
The bus cycles generated by an instruction executed in user
state are classified as user state references. This allows an external memory management device to translate the address and
to control access to protected portions of the address space.
While the processor is in user privilege state, those.instructions
which use either the system stack pOinter implicitly or address
register seven explicitly, access the user stack pointer.
The halted processing state is an indication of a catastrophic
hardware failure. For example, if during the exception processing
of a bus error another bus error occurs, the processor assumes
that the system is unusable and halts. Only an external reset
can restart a halted processor. Note that a processor in the
stopped state is not in the halted state, nor vice versa.
PRIVILEGE STATE CHANGES. Once the processor is in the
user state and executing instructions, only exception processing
can change the privilege state. During exception processing,
the current setting of the S-bit of the status register is saved and
the S-bit is asserted, putting the processing in the supervisor
state. Therefore, when instruction execution resumes to process
the exception, the processor is in the supervisor privilege state.
PRIVILEGE STATES
The processor operates in one of two states of privilege: the
"user" state or the "supervisor" state. The privilege state determines legal operations. It is used to choose between the supervisor stack pointer and the user stack pointer in instruction
references, and by the external memory management device
to control and translate accesses.
REFERENCE CLASSIFICATION. When the processor makes
a reference, it classifies the kind of reference being made by
using the encoding on the three function code output lines. This
allows external translation of addresses, control of access, and
differentiation of speCial processor states, such as interrupt
acknowledge. Table 6 lists the classification of references.
The privilege state is a mechanism for providing security in a
computer system by allowing most programs to execute in user
state. In this state, the accesses are controlled, and the effects
on other parts of the system are limited. Programs should access
only their own code and data areas, and ought to be restricted
from accessing information.
Tabie 6.
ReferenceClassification
Function Code Output
The operating system which executes in the supervisor state,
has access to all resources and performs the overhead tasks
for the user state programs.
SUPERVISORSTATE. The supervisor state is the higher state
of privilege. For instruction execution, the supeniisor state is
determined by asserting (high) the S-bit of the status register.
All instructions can be executed in the supervisor state. The bus
cycles generated by instructions executed in the supervisor state
are classified as supervisor references. While the processor is
in the supervisor privilege state, those instructions which use
either the system stack pointer implicitly or address register
seven explicitly access the supervisor stack pointer.
1-22
Reference Class
FC2
FCI
FCO
0
0
0
(Unassigned)
0
0
1
User Data
0
1
0
User Program
0
1
1
(Unassigned)
(Unassigned)
1
0
0
1
0
1
Supervisor Data
1
1
0
Supervisor Program
1
1
1
Interrupt Acknowledge
R68000
16-Bit MPU
WORD 0
NEW PROGRAM COUNTER (HIGH)
AO=O, Al=O
WORD 1
NEW PROGRAM COUNTER (LOW)
AO=O,Al=l
Figure 24.
Exception Vector Format
015
0807
DO
IGNORED
WHERE:
v7 IS THE MSB OF THE VECTOR NUMBER
YO IS THE LSB OF THE VECTOR NUMBER
Figure 25.
Peripheral Vector Number Format
A23
Al0 A9 A8 A7 A6 A5 A4 A3 A2 Al
AD
ALL ZEROES
Figure 26.
Address Translated From 8·Blt Vector Number
EXCEPTION PROCESSING
address 1023. This provides 255 unique vectors; some of these
are reserved for TRAPS and other system functions. Of the 255,
there are 192 reserved for user interrupt vectors. However, there
is no protection on the first 64 entries, so user interrupt vectors
may overlap at the discretion of the systems designer.
Before discussing the details of interrupts, traps, and tracing,
a general description of exception processing is in order. The
processing of an exception occurs in four steps, with variations
for different exception causes. During the first step, a temporary
copy of the status register is made, and the status register is
set for exception processing. In the second step the exception
vector is determined, and the third step is the saving of the cur·
rent processor contents. In the fourth step a new context is
obtained, and the processor switches to instruction processing.
KINDS OF EXCEPTIONS. Exceptions can be generated either
internally or externally. Externally generated exceptions include
interrupts (IRQ), bus error (BERR), and reset (RESEn requests.
Interrupts are requests from peripheral devices for processor
action while BERR and RESET inputs are used for access con·
trol and processor restart. Internally generated exceptions come
from instructions, from address errors, or from traCing. The trap
(TRAP), trap on overflow (TRAPV), check register against bounds
(CHI<) and divide (DIV) instructions can all generate exceptions
as part of their instruction execution. In addition, illegal instruc·
tions, word fetches from odd addresses and privilege violations
cause exceptions. Tracing behaves like a very high priority, inter·
nally generated interrupt after each instruction execution.
EXCEPTION VECTORS. Exception vectors are memory loca·
tions from which the processor fetches the address of a routine
which will handle that exception. All exception vectors are two
words in length (Figure 24), except for the reset vector, which
is four words. All exception vectors lie in the supervisor data
space, except for the reset vector which is in the supervisor program space. A vector number is an eight·bit number which, when
multipled by four, gives the address of an exception vector. Vector numbers are generated internally or externally, depending
on the cause af the excep.tion. In the case of interrupts, during
the interrupt acknowledge bus cycle, a peripheral provides an
8-bit vector number (Figure 25) to the processor on data bus lines
DO through 07. The processor translates the vector number into
a full 24-bit address, as shown in Figure 26. The memory layout
for exception vectors is given in Table 7.
EXCEPTION PROCESSING SEQUENCE. Exception processing
occurs in four identifiable steps. In the first step, an internal copy
is made of the status register. After the copy is made, the S·bit
is asserted, pUlling the processor into the supervisor privilege
state. Also, the T·bit is negated which will allow the exception
handler to execute unhindered by tracing. For the reset and inter·
rupt exceptions, the interrupt priority mask is also updated.
As shown in Table 7, Ule memory layout is 512 words long
(1024 bytes). It starts at address 0 and proceeds through
1·23
16-Bit MPU
R6S000
Table 7.
Exception Vector Assignment
Address
Vector
Number(s)
Dec
Hex
Space
Assignment
0
000
SP
Reset: Initial SSP
4
004
SP
Reset: Initial PC
2
8
008
SO
Bus Error
3
12
OOC
SO
Address Error
0
-
4
16
010
SO
Illegal Instruction
5
20
014
SO.
Zero Divide
6
24
018
SO
CHK Instruction
7
28
01C
SO
TRAPV Instruction
8
32
020
SO
Privilege Violation
9
36
024
SO
Trace
10
40
028
SO
Line 1010 Emulator
11
44
02C
SO.
Line 1111 Emulator
12-
48
030
SO
(Unassigned, r.rved)
13-
52
034
SO
(Unassigned, reserved)
14-
56
038
SO
(Unassigned, reserved)
15
60
03C
SO
Uninitialized Interrupt Vector
64
04C
SO
(Unassigned, reserved)
16-23-
-
95
05F
24
96
060
SO
Spurious Interrupt
25
100
064
SO
Level 1 Interrupt Autovector
26
104
068
SO
Level 2 Interrupt Autovector
27
108
06C
SO
Level 3 Interrupt Autovector
28
112
070
SO
Level 4 Interrupt Autovector
29
116
074
SO
Level 5 Interrupt Autovector
30
120
078
SO
Level 6 Interrupt Autovector
31
124
07C
SO
Level 7 Interrupt Autovector
32·47
128
080
SO
TRAP Instruction Vectors
191
OBF
192
OCO
SO
(Unassigned, reserved)
255
OFF
256
100
SO
User Interrupt Vectors
1023
3FF
48·63-
64·255
-
-
-Vector numbers 12, 13, 14, 16 through 23, and 48 through 63 are reserved for future enhancements. No user peripheral devices should be assigned
these numbers.
1·24
16-BitMPU
R68000
SSP..-
STATUS REGISTER
HIGH
r-PROGRAM COUNTER- - - - - LOW
Figure 27.
Table 8.
1
Group
0
HIGHER
ADDRESSES
1
Exception Stack Order (Groups 1 and 2)
2
In the second step, the vector number of the exception is determined. For interrupts, the vector number is obtained by a
processor fetch, classified as an interrupt acknowledge. For all
other exceptions, internal logic provides the vector number. This
vector number is then used to generate the address of the exception vector.
Exception Grouping and Priority
Exception
Processing
Reset
Address Error
Bus Error
Exception processing begins
within two clock cycles.
Trace
Interrupt
Illegal Instruction
Privilege Violation
Exception processing begins
before the next instruction.
TRAP, TRAPV, CHK,
Zero Divide
Exception processing is started
by normal instruction execution
The priority relation between two exceptions determines which
is taken first if the conditions for both arise simultaneously.
Therefore, if a bus error occurs during a TRAP instruction, the
bus error takes precedence, and the TRAP instruction processing is aborted. In another example, if an interrupt request
occurs during the execution of an instruction while the T-bit is
asserted, the trace exception has priority, and is processed first.
Before instruction processing resumes, however, the interrupt
exception is also processed, and instruction processing commences finally in the interrupt handler routine. Table 8 gives a
summary of exception grouping and priority.
The third step is to save the current processor status except for
the reset exception. The current program counter value and the
saved copy of the status register are stacked using the supervisor stack pointer as shown in Figure 27. The program counter
value stacked usually points to the next unexecuted instruction;
however, for bus error and address error, the value stacked for
the program counter is unpredictable, and may be incremented
from the address of the instruction which caused the error. Additional information defining the current context is stacked for the
bus error and address error exceptions.
The last step is the same for all exceptions. The new program
counter value is fetched from the exception vector. The
processor then resumes instruction execution. The instruction
at the address given in the exception vector is fetched, and
normal instruction decoding .and execution is started.
EXCEPTION PROCESSING DETAILED DISCUSSION
Exceptions have a number of sources, and each exception has
a unique processing sequence. The following paragraphs detail
the sources of exceptions, how each arises, and how each is
processed.
.
'MULTIPLE EXCEPTIONS. These paragraphs describe the proceSSing which occurs when multiple exceptions arise
simultaneously. Exceptions can be grouped according to their
occurrence and priority. The Group 0 exceptions are reset, bus
error, and address error. These exceptions cause the instruction currently being executed to be aborted, and the exception
processing to commence within two clock cycles. The Group 1
exceptions are trace and interrupt, as well as the privilege violations and illegal instructions. These exceptions allow the current instruction to execute to completion, but preempt the execution of the next instruction by forcing exception processing to
occur (privilege violations and illegal instructions are detected
when they are the next instruction to be executed). The Group 2
exceptions occur as part of the normal processing. of instructions. The TRAP, TRAPV, CHK, and zero divide exceptions are
in this group .. For these exceptions, the normal execution of an
instruction may lead to exception processing.
RESET. The reset input provides the highest exception level.
The processing of the reset signal is designed for system initiation, and recovery from catastrophic failure. Any processing in
progress at the time of the reset is aborted and cannot be
recovered: The processor is forced into the supervisor state and
the trace state is forced off. The processor interrupt priority mask
is set at level seven. The vector number is internally generated
to reference the reset exception vector at location 0 in the supervisor program space. Because no assumptions can be made
about the validity of register contents, in particular the supervisor stack pointer, neither the program counter nor the status
register is saved. The address contained. in the first two words
of the reset exception vector is fetched as the initial supervisor
stack pOinter, and the address in the last two words of the reset
exception vector is fetched as the initial program counter. Finally,
instruction execution is started at the address in the program
counter. The powerup/restart code should be pointed to by the
initial program counter.
Group 0 exceptions have highest priority, while Group 2 exceptions have lowest priority. Within Group 0, reset has highest
priority, followed by address error and then bus error. Within
Group 1, trace has priority .over external interrupts, which in turn
takes priority over illegal instruction and privilege violation. Since
only one instruction can be executed at a time, there is no priority
relation within Group 2.
The RESET instruction does not cause loading of the reset vector, but does assert the reset line to reset external devices. This
allows the software to reset the system to a known state and
then continue processing with the next instruction.
1-25
R6S000
16·Bit MPU
INTERRUPTS. Seven levels of interrupt priorities are provided.
Devices may be chained externally within interrupt priority levels,
allowing an unlimited number of peripheral devices to interrupt
the processor. Interrupt priority levels are numbered from one
to seven, level seven being the highest priority. The status
register contains a three-bit m!!sk which indicates the current
processor priority. Interrupts are inhibited for all priority levels
less than or equal to the current processor priority.
PROCESSOR
,
INTERRUPTING DEVICE
REQUEST INTERRUPT
GRANT INTERRUPT
1) COMPARE INTERRUPT LEVEL IN STATUS
REGISTER AND WAIT FOR CURRENT
INSTRUCTION TO COMPLETE
2) PLACE INTERRUPT LEVEL ON A1, A2, A3
3) SET FUNCTION CODE TO INTERRUPT
ACKNOWLEDGE
4) ASSERT ADDRESSSTROB~S)
5) ASSERT DATA STROBES (LDS AND UDS')
An interrupt request is made to the processor by encoding the
interrupt request level on the interrupt request lines; a zero indicates no interrupt request. Interrupt requests arriving at the
processor do not face immediate exception processing, but are
made pending. Pending interrupts are detected between instruction executions. If the priority of the pending interrupt is lower
than or equal to the current processor priority, execution continues with the next instruction and the interrupt exception
processing is postponed. (The recognition of level seven is
slightly different, as explained in a following paragraph.)
,
PROVIDE VECTOR NUMBER
1) PLACE VECTOR NUMBER OF DO-D7
2) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)
,
If the priority of the pending interrupt is greater than the current
processor priority, the exception processing sequence is started.
First a copy of the status register is saved, and the privilege state
is set to supervisor, then tracing is suppressed, and the
processor priority level is set to the level of the interrupt being
acknowledged; The processor fetches the vector number from
the interrupting device, classifying the reference as an interrupt
acknowledge and displaying the level number of the interrupt
being acknowledged on the address bus. If external logic
requests an automatic vectoring, the processor internally
generates a vector number which is determined by the interrupt
level number. If external logic indicates a bus error, the interrupt is taken to be spurious, and the generated vector number
references the spurious interrupt vector. The processor then proceeds with the usual exception processing, saving the program
counter and status register on the supervisor stack. The saved
value of the program counter is the address of the instruction
which would have been executed had the interrupt not been
present. The content of the interrupt vector whose vector number
was previously obtained is fetched and loaded into the program
counter, and normal instruction execution commences in the
interrupt handling routine. A flow chart for the interrupt
acknowledge sequence is given in Figure 28, a timing diagram
is given in Figure 29, and the interrupt exception timing
sequence is shown in Figure 30.
'1
ACQUIRE VECTOR NUMBER
1) LATCH VECTOR NUMBER
2) NEGATE LOS AND UDS
3) NEGATE AS
+
RELEASE
1) NEGATE DTACK
t
START INTERRUPT PROCESSING
• ALTHOUGH A VECTOR NUMBER IS ONE BYTE, SOTH
DATA STROBES ARE ASSERTED DUE TO THE
MICROCODE USED FOR EXCEPTION PROCESSING. THE'
PROCESSOR DOES NOT RECOGNIZE ANYTHING ON
DATA LINES D8 THROUGH 015 AT THE TIME.
Figure 28.
Priority level seven is a special case. Level seven interrupts cannot be inhibited by ihe interrupt priority mask, thus providing
a "non-maskable interrupt" capability. An interrupt is generated
each time the interrupt request level changes from some lower
level to level seven. Note that a level seven interrupt may still
be caused by the level comparison if the request level is a seven
and the processor priority is set to a lower level by an instruction.
Interrupt Acknowledge Sequence Flow Chart
SPURIOUS INTERRUPT. If during the interrupt acknowledge
cycle no device responds by asserting DTACK or VPA, the bus
error line should be asserted to terminate the vector acquisition.
The processor separates the processing of this error from bus
error by fetching the spurious interrupt vector instead of the bus
error vector. The processor then proceeds with the usual exception processing.
UNINITIALIZED INTERRUPT. An interrupting device asserts
VPA or provides an interrupt vector during an interrupt
acknowledge cycle to the R68000. If the vector register has not
been initialized,the responding R68000 Family peripheral will
provide vector 15, the uninitialized interrupt vector. This provides
a uniform way to recover from a programming error.
INSTRUCTION TRAPS. Traps are exceptions caused by instructions. They arise either from processor recognition of abnormal
conditions during instruction execution, or from use of instructions whose normal behavior is trapping.
1-26
16-Bit MPU
R68000
CLK
U~.~~-----J
,-__
\~__________-J~~_ _~;-
r----I\r--"""\
LDS ____~====~~~
7
\
DTACK----~\-~-_-~_-_~~~
RiW
\
08-015
00-07
FCO-FC2
::x
IPLO-IPL2
~============~
~~----~
\~____~/r~~\~------
<
~
(~~.
(
( ) (
:_
.
r=-
__ \
~
X'"_____
I t-..,.(S""'S~P;,.) ~I. . . .
LAST BUS CYCLE
OF INSTRUCTION
S!~~K
lACK CYCLE
STACK AND
- .....
(VECTOR NUMBER ACQUISITION)+ VECTOR FETCH-:1
(READ OR ........•....
WRITE)
.
~I
·ALTHOUGH A VECTOR NUMBER IS ONE; BYTE, BOTH DATA STROBES ARE ASSERTED DUE TO THE MICROCODE USED
FOR EXCEPTION PROCESSING. THE PROCESSOR DOES NOT RECOGNIZE ANYTHING ON DATA LINES DB THROUGH 015
AT THIS TIME.
Figure 29. Interrupt Acknowledge Sequence Timing Diagram
LAST BUS CYCLE
OF INSTRUCTION
(DURING WHICH
INTERRUPT WAS
RECOGNIZED)
~
STACK
PCL
(AT SSP-2)
l-+
READ
VECTOR
HIGH
(A16-A23)
r-----
lACK
CYCLE
(VECTOR NUMBER
ACQUISITION)
r-----
READ
VECTOR
LOW
(AO-A15)
Figure 30.
,....
r-----
STACK
STATUS
(AT Ssp-a)
FETCH FIRST
WORD OF
INSTRUCTION
OF INTERRUPT
ROUTINE
Interrupt Exception Timing Sequence
1·27
r-----
STACK
PCH
(AT SSP-4)
-
NOTE:
SSP REFERS TO THE
VALUE OR THe SUPERVISOR STACK POINTER
BEFORE THE INTERRUPT
OCCURS
R6S000
16-Bit MPU
Some instructions are used specifically to generate traps. The
.. TRAP instruction always forces an exception, and is useful for
implementing system calls for user programs. The TRAPV and
CH K instructions force an exception if the user program detects
a runtime error, which may be an arithmetic overflow or a
subscript out of bounds.
is pending on completion, the trace exception is processed
before the interrupt exception. If, during the execution of the
instruction, an exception is forced by that instruction, the forced
exception is processed before the trace exception.
As an extreme illustration of the above rules, consider the arrival
of an interrupt during the execution of a TRAP instruction while
tracing is enabled. First the trap exception is processed, then
the trace exception, and finally the interrupt exception. Instruction execution resumes in the interrupt handler routine.
The signed divide (DIVS) and unsigned divide (DIVU) instructions will force an exception if a division operation is attempted
with a divisor of zero.
BUS ERROR. Bus error exceptions occur when the external logic
requests that a bus error be processed by an exception. The
current bus cycle which the processor is making is then aborted.
Whether the processor was dOing instruction or exception
processing, that processing is terminated, and the processor
immediately begins exception processing.
ILLEGAL AND UNIMPLEMENTED INSTRUCTIONS, Illegal
instruction refers to any of the word bit patterns which are not
the bit pattern of the first word of a legal instruction. During
instruction execution, if such an instruction is fetched, an illegal
instruction exception occurs. Rockwell reserves the right to
define instructions whose opcodes may be any of the illegal
instructions. Three bit patterns will always force an illegal instruction trap on all R68000 Family compatible microprocessors. They
are: $4AFA, $4AFB, and $4AFC. Two of the patterns, $4AFA
and $4AFB, are reserved for Rockwell system products. The third
pattern, $4AFC, is reserved for customer use.
Exception processing for bus error follows the usual sequence
of steps. The status register is copied, the supervisor staie is
entered, and the trace state is turned off. The vector number
is generated to refer to the bus error vector. Since the processor
was not between instructions when the bus error exception
request was made, the context of the processor is more detailed.
To save more of this context, additional information is saved on
the supervisor stack. The program counter and the copy of the
status register are of course saved. The value saved for the program counter is advanced by some amount, two to ten bytes
beyond the address of the first word of the instruction which
made the reference causing the bus error. If the bus error
occurred during the fetch of the next instruction, the saved pro·
gram counter has a value in the vicinity of the current instruc·
tion, even if the current instruction is a branch, ajump, or a return
instruction. Besides the usual information, the processor saves
its internal copy of the first word of the instruction being
processed, and the address which was being accessed by the
aborted bus cycle. Specific information about the access is also
saved: whether it was a read or a write, whether the processor
was processing an instruction or not, and the classification
displayed on the function code outputs when the bus error
occurred. The processor is processing an instruction if in the
normal state or processing a Group 2 exception; the processor
is not processing an instruction when processing a Group 0 or
a Group 1 exception. Figure 31 illustates how the information
is organized on the supervisor stack. Although this information
is not sufficient to effect full recovery from the bus error, it does
allow software diagnosis. Finally, the processor commences
instruction processing at the address contained in the vector.
It is the responsibility of the error handler routine to clean up
the stack and determine where to continue execution.
Word patterns with bits 15 through 12 equaling 1010 or 1111
are distinguished as unimplemented instructions and separate
exception vectors are given to these patterns to permit efficient
emulation. This facility allows the operating system to detect program errors, or to emulate unimplemented instructions in
software.
PRIVILEGE VIOLATIONS. In order to provide system security,
various instructions are privileged. An attempt to execute one
of the privileged instructions while in the user state will cause
an exception. The privileged instructions are:
STOP
AND Immediate to SR
EOR Immediate to SR
RESET
RTE
OR Immediate to SR
MOVE USP
MOVE to SR
TRACING. To aid in program development, the R68000 includes
a facility to allow instruction by instruction tracing. In the trace
state, after each instruction is executed an exeception is forced,
allowing a debugging program to monitor the execution of the
program under test.
The trace facility uses the T-bit in the supervisor portion of the
status register. If the T-bit is negated (off), tracing is disabled,
and instruction execution proceeds from instruction to instruction as normal. If the T-bit is asserted (on) at the beginning of
the execution of an instruction, a trace exception will be
generated after the execution of that instruction is completed.
If the instruction is not executed, either because an interrupt
is taken, or the instruction is illegal or privileged, the trace exception does not occur. The trace exception also does not occur
if the instruction is aborted by a reset, bus error, or address error
exception. If the instruction is indeed executed and an interrupt
If a bus error occurs during the exception processing for a bus
error, address error; or reset, the processor is halted, and all
processing ceases. This simplifies the detection of catastrophic
system failure, Since the processor removes itself from the
system rather than destroy all memory contents. Only the RESET
pin can restart a halted processor.
1·28
·
R68000
.
16-Bit MPU
15
14
13
12
11
10
9
7
8
8
4
5
3
SSP
I RJWII/NI
D
o
2
FUNCTION
CODE
HIGH
----------------------
-ACCESS ADDRESS
lOW
1
HIGHER'
ADDRESS
INSTRUCTION R.EGISTER
STATUS REGISTER
r- - PROGRAM COUNTER
-
- _._--'---....,.. ----------HIGH
lOW
RIW (READIWRITE): WRITE • 0, READ
= 1. I/N (INSTRUCTION/NOT): INSTRUCTION = 0, NOT = 1 •
Figure 31. Supervisor Stack Order (Group 0)
ClK
'\
-====i~;=======;t~~;======~~==~
\
\\-----~~~======~--~""
A1-A23
AS -
"UDS
LDS
- - - - - ' \ , _ _ _ _-'
\
\
I
,RJWj
DTACK ------~""'\\'______,--I
~
\
I
DO·D15
\
\
'--
'--
'--
---~{(====:J>_<:===)>--:-:-~..,r_--:----{(==
I..
ADDRESS ERROR
I ·-....:::=:.::WRITE
READ---··.......
•
8 CLOCKS
IAPPROX.
• IDLE
.. , .
Figure 32. Address Error Timing
ADDRESS ERI:IOR. Adqress error exceptions occur when the
processor attempts to access .a word or e long word operand
or an instruction at an odd address. The effect is much like ,an
internally generated bus error, so that the bus cycle is aborted,
and the processor ceases whatever processing it is currently
doing and begins exception processing. After exception
processing commences, the sequence is the same as that for
bus error including the information that is stacked, except that
the vector number refers to the address error vector instead.
Likewise, if an address error occurs during the exception
processing for a bus error, addreSlj error, or reset, the processor
is halted. As shown in Figure 32, an addre.ss error will execute
a short bus cycle followed by an exception processing.
1-29
_~
WRITE STACK~
16~Bit
R68000
INTERFACE WITH R6500 PERIPHERALS
MPU
chip select equation of the peripheral. This ensures that the
R6500 peripherals are selected and deselected at the correct
time. The peripheral now runs its cycle during the high portion
of the E signal. Figures 34 and 35 depict the best anc:! worst case
R6500...2X2!e timing. This cycle length is dependent strictly upon
when VPA is asserted in relationship the E clock.
Rockwell's line of R6500 peripherals are directly compatible with
the R6S000. Some of these devices that are particularly useful
are:
R6520 Peripheral Interlace Adapter (PIA)
R6522 Versatile Interlace Adapter (VIA)
R6545 CRT Controller (CRTC)
R6551 Asynchronous Communication Interface Adapter
(ACIA)
If we assume that external circuitry asserts VPA as soon as
possible after the assertion of AS, then VPA will be recognized
as being asserted on the falling edge of 54. In this case, no
"extra" wait cycles will be inserted prior to the recognition of
VPA assertion and only thewait cycles inserted to synchronize
with the E clock will determine the. total length of the cycle. In
any case, the synchronization delay will be some integral number
of clock cycles within the following two extremes:
1. B.est Case-VPA is recognized as being asserted on the
falling edge three clock cycles before E rises (or three clock
cycles after Efalls).
2. Worst Case-VPA is recognized as being asserted on the
falling edge two clock cycles before E rises (or four clock
cycles after E falls).
To interface the Synchronous R6500 peripherals with the asynchronous R68000, the processor modifies its bus cycle to meet
the R6500 cycle requirements whenever an R6500 device
address is detected. This is possible since both processors use
memory mapped I/O. Figure 33 is a flow chart of the interlace
operation between the processor and R6500 devices. 6800
peripherals are also compatible with the R68000 processor.
DATA TRANSFER OPERATION
Three signals on the processor provide the R6500 interface.
They are: enable (E), valid memory address (VMA), and valid
Peripheral address (VPA). Enable corresponds to the E or !b2
signal in existing R6500 systems. The bus frequency is one tenth
of the incoming R68000 cloCk frequency. The tinning of E allows
1 MHz peripherals to be used with an S MHz R68000. Enable
has a 6.0l40 duty cycle; that is, it is low for six input clocks and
high .for four input clocks. This duty cycle allows the processor
to do successive VPA accesses on successive E pulses.
Near the end of a read cycle, the processor latches the
peripheral's data in state 6. For all cycles, the processor negates
the address and data strobes one half clock cycle later in state 7,
and the Enable signal goes low at this time. Another half clock
later, the address bus is put in the high-impedance state. Upon
write cycle completion, the data bus is put in the high-impedance
state and the read/write signal is switched high. The peripheral
logic must remove VPA within one clock after address strobe
is negated.
Figures 34 and 35 give a general R6500 to R68000 interlace
timing, while Figures 36 and 37 detail the specific timing
parameters involved in the interlace. At state zero (SO) in the
cycle, the address bus is in the high-impedance state. A function code is asserted on the function code output lines. Onehalf clock later, in state 1, the address bus is released from the
high-impedance state.
DTACK should not be asserted while VPA is asserted. Note
that the R68000 VMA is active low. This allows the processor
to put its buses in the high-impedance state on DMArequests
without inadvertently selecting peripherals.
During state 2, the address strobe (AS) is asserted to indicate
thai there is a valid address on the address .bus. If the bus cycle
is a read cycle, the upper and/or lower data strobes are also
asserted in state 2. If the bus cycle is a write cycle, the read/write
(RtW) signal is switched to a low (write) during state 2. Qne-half
clock later, in state 3, the write data is placed on .the data bus,
and in state 4 the data strobes are issued to indicate valid data
on the data bus. The processor now inserts wait states until it
recognizes the assertion of VPA.
During an interrupt acknowledge cycle while the processor is
fetching the vector, if VPA is asserted, the R68000 will assert
VMA and complete a normal R6500 read cycle as shown in
Figure 38. The processor will then use an internally generated
vector, called an autovector, that is a function of the interrupt
being served. The seven autovectors are vector numbers 25
through 31 (decimal).
The VPA input signals the processor that the address on the
bus is the address of an R6500 device (or an area reserved for
R6500 devices) and that the bus should conform to the !b2
transfer characteristics of the R6500 bus. Valid peripheral
address (VPA) is derived by decoding the address bus,
conditi.oned by address strobe (AS). Chip select for the R6500
peripherals should be derived by decoding the address bus conditioned by VMA.
Autovectors operate in the same fashion (but are not restricted
to) the R6500 interrupt sequence. The basic difference is that
there are six normal interrupt vectors and one NMI type vector.
As with both the R6500 and the R68ODO's normal vectored interrupt, the interrupt service routine can be located anywhere in
the address space. This is due to the fact that while the vector
numbers are fixed, the contents of the vector table entries are
assigned by the user.
After the recognition of VPA, the processor assures that the
Enable @is low, by waiting if necessary, and subsequently
asserts VMA. Valid memory address is then used as part of the
Since VMA is asserted during autovectoring, the R6500
peripheral address decoding should prevent unintended
accesses.
INTERRUPT OPERATION
1-30
16-BitMPU
CLK
J-<'--_______. . ;. . . __.,..--__>-C
F\
r--\....
A1·A23
AS
DTACK
~~~~~(~~~~~~~~~~~;;;2}-
OUT :
DATA
DATAIN
FCD-FC2
(
::x'--_________-;::====~---'x=
\~====~-----JI
\1......-_
E __
VPA
VMA
}-----
r--\....
\
-----===~\-------______________--J!~
.
~
, Figure 34.
R68000 to R6S00 Peripheral Timing-Best Case
~~~ww~wwwwwwwwwwwwh~
CLK
A1·A23
=><______. . ;. .________
~
AS~
>-C
I
DTACK
>(
)L
~~~(~~~~~~~~~~~~~~;;;;2
:::x
x:::
=:=-=- :--_ ~ ==~\-.......-------.-:;:::::::=:~
/
L
DATA
IN :
DATA
OUT
FCD-FC2
E
VPi
--J-;./.
"
~
r
\
VMA
Figure 3S.
_ _ _---J
\
R68000 to R6S00 Peripheral Timing-Worst Case
1·31
r
o
::D
(J)
CD
Q
Q
Q
M'
SO
S1
S3
w
,S4
w
w
vi
w
w
w
w
w
w
w
w'
S5
S6
S7
SO
elK
A1-A23
AS
E
~
VPA
~
VMA
DATA OUT - - - - - -
I
DATAIN _ _ _ _ _ _ _ _ _ _ _ ....!..
*
III, )
~
------------------------------
NOTES:
THIS FIGURE REPRESENTS,THE BEST CASE 1'16500 TIMING WHERE VPA FALLS BEFORE THE THIRD SYSTEM CLOCK CYCLE
AFTER THE FALLING EDGE OF E.
THIS TIMING DIAGRAM IS INCLUDED FOR THOSE WHO WISH TO DESIGN THEIR OWN CIRCUIT TO GENERATE VMA 1"1' SHOWS
THE BEST CASE POSSIBLY ATTAINABLE.
....
(J)
•
m
=
Figure 36. R6500 Timing-Best Case
==
"1J
C
16-Bit MPU
R68000
PROCESSOR
Included in the register indirect addressing modes is the capa·
bility to do postincrementing, predecrernenting, offsetting and
indexing. Program counter r,el;ltive moOe can also be modified
via indexing and 'offsetting.
'
SLAVE
INITIATE CYCLE
1) THE PROCESSOR STARTS A
NORMAL READ OR WRITE CYCLE
I
Table 9.
+
Mode
DEFINE R6500 CYCLE
1) EXTERNAL HARDWARE ASSER~
VALID PERIPHERAL ADDRESS (VPA)
•
AbSQlute Data Addrassing
Absolute Short
Absolute Long
I
+
TRANSFER DATA
1) THE PERIPHERAL WAITS UNTIL E
IS ACTIVE AND THEN TRANSFERS
THE DATA
J
TERMINATE CYCLE
1) THE PROCESSOR WAITS UNTIL E
GOES LOW. (ON A READ CYCLE THE'
DATA IS LATCHED AS E GOES LOW
INTERNALLY)
2) THE PROCESSOR NEGATES'VMA_
3) THE PROCESSOR NEGATES AS, UDS,
and LDS
Generation
EA = On
EA'= An
,EA - (Next Word)
EA = (Next Two Words)
Program Counter Relative
Addressing
Relative with Offset
Relative with Index and Offset
EA = (PC) + d16
EA = (PC) + (Xn) + dS
Register Indlract Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offs!'t
Inilex!id Register Indirect with offset
EA ,= (An)
EA = (An), An~ An + N
An- An - N, EA = (An)
EA = (An) + d16
EA = (An) + (Xn~ + dS
Immediate Data Addrasslng
Immediate
Quick Immediate
DATA
Next Word(s)
Inherent Data
=
Irilpti~ Addressing
Implied Register
"
-
t
START NEXT CYCLE
Figure 33.
,
Register Direct Addressing
Data Register Direct
Address Register Direct
SYNCH!'IONIZE WITH ENABLE
1) THE PR~ESSOR MONITORS ENABLE
(E) UNTIL IT IS LOW (PHASE 1)
2) THE PROCESSOR ASSERTS VALID
MEMORY ADDRESS (VMA)
+
Addressing Modes
R6SDD Interfacing Flow Chart
DATA TYPES AND ADDRESSING MODES
"
Five basic data types are supported. These data types are:
Bits
BCD Digits (4-bits)
Bytes (a-bits)
Word (l6-bits)
Long Words (32-bits)
NOTES:
EA = Effective Address
An "" Address Register'
,On = Data Register
Xn = Address or qata Register
used as Index Register
SR - Status, F:!eg!~ter
PC' = Program Counter
( ) = Contents of
dS = Eight-bit Offiiet
(displaCement)
d16 .. Sixteen-bit Offset
(displacement)
EA = SR, USP, SP, PC
N = 1 for Byte, 2 for
Words and 4 for
Long Word. Ii An
is the stack pointer
and the operand
size is byte, N = 2
.to keep the stack,
pointer on a word
boundry.
_ = Replaces
INSTRUCTION SET OVERVIEW
The RSBOOO instrllction set is shown in Table 10. Some additional instructions are variations, or subsets, of these and they
appear in Table 11. Special emphasis has been given to the
instruction set's support of structured high-level languages to
facilitate ~e of programming. Each instruction, with few exceptions, operates 6n bytes, words, and long words and most
instructions can use any of the 14 addressing modes . .combining
instruction tYpes, datil. tYPeS, and addressing mpejes, over 1000
useful instructions are provided. These instructions include
signed and unsigned multiply and divide, "quick" arithmetic'
operations. BCD arithmetic and expanded operations (through
traps).
,.
In addition, operations on other data types such as memory
addresses, status word data, etc., are provided for in the instruction set.
'
The 14 addressing modes, shown in Table 9, include six basic
types:
Program Counter Relative
Register Direct
Implied
Register Indirect
Absolute
Immediate
1-33
R68000
16-Bit MPU
SO S1 S2 S3 S4 w w W w w w w w w w w w w w w w w w w w w w w w w w. w w S5 S6 S7 SO
CLK
E
A1·A23
DATA OUT---DATA, IN_ - - -
-----------------------------.:..........:::::..-f=::~:}
NOTE: THIS TIMING DIAGRAM IS INCLUDED FOR THOSE WHO WISH TO DESIGN THEIR OWN CIRCUIT TO GENERATE VMA.
IT SHOWS THE WORST CASE POSSIBLY ATTAINABLE.
Figure 37., RC680~0 to R6500 Peripheral Timing Diagram - Worst Case
SO S2 S4 S6 SOS2 S4 w
w w
w w w w
W
w w 56 SO S2
CLK
>-<
A1-A3
A4-A23
AS
UDS·
LOS
RJW
DTACK
011-015
00-07
FCO-FC2
IPLO-IPL2'
""\....J
--c:J
-----c:::)
y
X
'C
~
E
L-
\
VPA
\
VMA
I+NO~AL __
' CYCLE
I_
AUTOVECTOR OPERATION
";-I
·ALTHOUGH A VECTOR NUMBER IS ONE BYTE, BOTH DATA STROBES ARE ASSERTED DUE TO ,THE MICROCODE USED
FOR EXCEPTION PROCESSING. THE PROCESSOR DOES NOT RECOGNliE ANYTHING ON DATA LINES 08 THROUGH'
015 AT THIS TIME.
'
'
Figure 38.
Autovector Operation Timing Diagram
1-34
R68.GOO·
16-81t MPU
Table 10. Instruction Set Summary
Mnemonic
Description
Mnemonic
ADBC
AbO
AND
ASL
ASR
Add Decimal with Extend
Add
Logical And
Arithmetic Shift Left
Arithmetic Shift Right
BCC
BCHG
BCLR
BRA
BSET
BSR
BTST'
Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and Set
Branch to Subroutine
Bit Test
CHK
Check Register Against
Bounds
'Clear Operand
Compare
CLR
CMP
EOR
EXG
EXT
Test Condition, Decrement and
Branch
Signed Divide
Unsigned Divide
DBCC
DIVS
DIVU
Exchange Registers
Sign Extend
JMP
JSR
Jump
Jump to Subroutine
LEA
LINK
LSL
LSR
Load Effective Address
Link Stack
Logical Shift Left
Logical Shift Right
MOVE
MULS
MULU
Move
Signed Multiply
Unsigned Multiply
NBCD
NEG
NOP
NOT
Negate Decimal with Extend
Negate
No Operation
One's Complement
OR
Logical Or
Table
n.
D"SCrlpil~n
Mnemoljlc
Description
'. Exclusive Or
PEA
Push Effective Address
RESET
ROL
ROR
ROXL
ROXR
RTE
RTR
RTS
Reset External Devices
Rotate Left without Extend
Rotate Right without Extend
Rotate Left with Extend
Roiete Right with Extend
Return from Exception
Return and Restore
Return from Subroutine
SBCD
SCC
STOP
SUB
SWAP
Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves
TAS
TRAP
TRAPV
TST
Test and Set Operand
Trap
Trap on Overflow
Test
UNLK
Unlink
Variations of Instruction Types
..
InstNction
Type
ADD
ADD
ADDA
ADDQ
ADDI
ADDX
AND
AND
ANDI
ANDI to CCR
AND I to SR
Add
Add
Add
Add
Add
Logical And
And Immediate
And immediate to
Condition Codes
And Immediate' to
Status 'Register
CMP
CMPA
CMPM
CMPI
Compare
Compare Address
'Compare Memory
Compare Immediate
EOR
EOR
EORI
EORI toCCR
Exclusive Or
Exclusive '0r Immediate
Exclusive Or Immediate
to Condition ·Codes
Exclusive Or Immediate
to Status Register
1-35
Variation
Deacrlptlon
MOVE
MOVE
MOVEA
MOVEM
MOVEP
MOVEQ
MOVE fromSR
MOVE to SR
MOVE toCCR
MOVE USP
Move
Move Address
Move Multiple Registers
Move Peripheral Data
Move Quick.
Move from Stetus Register .
Move to St _Destination
BCC
Branch Conditionally
If CC then PC + d -PC
-
- - - -
- «bit number» OF Destination._Z
- «bit number» OF Destination _
OF Destination
-
-
a Bit and
U
'
0
0
0
0
··-
-
BCHG
Test
BClR
Test a Bit and Clear
o _
- «bit number» OF Destination _Z
_OF Destination
-
-
BRA
Branch Always
PC + d ... PC
-
-
Test a Bit and Set
- «bit number» OF Destination _Z
1 _ OF Destination
BSR
Branch to Subroutine
PC _(SP); PC + d ... PC
BTST
Test a Bit
- «bit number» OF Destination _Z
- ·
- - - -
- - -
CHK
Check Register Against Bounds
If Dn <0 or On> «ea» then TRAP
-
ClR
Clear and Operand
o _Destination
CMP
Compare
(Destination) - (Source)
CMPA
Compare Address
(Destination) - (Source)
CMPI
Compare Immediate
(Destination) - Immediate Data
CMPM
Compare Memory
(Destination) - (Source)
DBce
Test Condition, Decrement and Branch If - CC then On '- 1 _On; if Dn
DIVS
Signed Divide
(Destination)/(Source) _Destination
DIVU
Unsigned Divide
(Destination)/(Source) _Destination
EOR
Exclusive OR logical
(Destination) ., (Source) _Destination
EORI
Exclusive OR Immediate
(Destination) ., Immediate Data _Destination
EORI to CCR
Exclusive OR Immediate
to Condition Codes
(Source) ., CCR ... eCR
EiSET
NOTES:
A = logical
= logical
= logical
= logical
•.,
-
AND
OR
exclusive OR
complement
Change
U
.
0
1
U
=
=
=
=
=
affected
unaffected
cleared
set
undefined
1·42
- - -
-
·
-
-
U
U
U
-
·
0
1
0
0
-
· · · ·
····
···
- · · · ·
- - - - - · · ·
- · · ·
- · ·
- · ·
··· ··
-
*
- 1 then PC + d _PC
0
0
0
0
0
0
R68000
16·Bit MPU
Table 22.
Instruction Set (Continued)
Condition Codes
Mnemonic
Description
Operation
X
N
Z
V
C
EORI to SR
Exclusive OR Immediate
to Status Register
(Source) ., SR -.-SR
·····
EXG
Exchange Register
Rx_Ry
-
EXT
Sign Extend
(Destination) Sign·Extended +- Destination
-
··
0
0
JMP
Jump
Destination -.- PC
-
- -
-
-
JSR
Jump to Subroutine
PC -.- - (SP); Destination _ PC
-
- -
LEA
Load Effective Address
_An
-
-
LINK
Link and Allocate
An _(SP); SP _An; SP + Displacement _SP
-
-
LSL, LSR
Logical Shift
(DestinatiOn) Shifted by < count> _ Destination
MOVE
Move Data from Source to Destination
(Source) _ Destination
MOVE to CCR
Move to Condition Code
(Source) _CCR
MOVE to SR
Move to the Status Register
(Source) - SR
··
·
· ·
··
-
~~
MOVE from SR Move from the Status Register
SR _ Destination
MOVE USP
Move User Stack Pointer
USP _An; An _USP
MOVEA
Move Address
(Source) _ Destination
MOVEM
Move Multiple Registers
Register _ Destination
(Source) _ Registers
MOVEP
Move Peripheral Data
(Source) _ Destination
MOVEQ
Move Quick
Immediate Data _Destination
MULS
Signed Multiply
(Destination)X(Source) +- Destination
MULU
Unsigned Multiply
(Destination)X(Source) +- Destination
NBCD
Negate Decimal with Extend
NEG
Negate
NEGX
Negate with Extend
ooo-
NOP
No Operation
-
NOT
Logical Complement
- (Destination) +- Destination
OR
Inclusive OR Logical
(Destination) • (Source) +- Destination
ORI
Inclusive OR Immediate
(Destination) • Immediate Data -Destination
ORI toCCR
Inclusive OR Immediate
to Condition Codes
(Source)
P
CCR +- CCR
ORI to SR
Inclusive OR Immediate
to Status Register
(Source)
P
SR -SR
---
(Destination)lO - X _Destination
(Destination) - Destination
(Destination) - X +- Destination
-
- -
-
-
0
0
-
0
0
0
0
··
··
- · ·
· · ·
· · · · ·
· · · · ·
- - - - - · ·
- · ·
- · ·
· · · · ·
··· ··
U
_ - (SP)
-
-
ROL, ROR
Rotate (Without Extend)
(Destination) Rotated by < count> _ Destination
-
=
undefined
1-43
0
- -
Push Effective Address
U
·
·
···
· · r-·
- - -
Reset External Device
.
0
0
U
0
_.._-,"-
= affected
- = unaffected
0 = cleared
1 = set
·
- - - - - - - - - - - -
PEA
AND
OR
exclusive OR
complement
- - - - - -
-
RESET
NOTES;
A = logical
p
= logical
., = logical
- = logical
- - - -
-
0
0
0
0
0
-
- - - - - -
· ·
0
·
16-Bit MPU
R6S000
Table 22.
Instruction Set (Continued)
Condition Codes
Mnemonic
Description
Operation
ROXL, ROXR
Rotate with Extend
(Destination) Rotated by _Destination
RTE
Return from Exception
(SP) + . . SR; (SP) + .. PC
RTR
Return and Restore Condition Codes
(SP) + . . CC; (SP) + _PC
RTS
Return from Subroutine
(SP) + _PC
SBCD
Subtract Decimal with Extend
(Destination)lO - (Source)lO - X _Destination
SCC
Set According to Condition
If CC then 1's -.-Destination else O's -Destination
STOP
Load Status Register and Stop
Immediate Data _ SR; STOP
SUB
Subtract Binary
(Destination) - (Source) _ Destination
SUBA
Subtract Address
(Destination) - (Source) - Destination
SUBI
Subtract Immediate
(Destination) - Immediate Data _Destination
SUBQ
Subtract Quick
(Destination) - Immediate Data __ Destination
SUBX
Subtract with Extend
(Destination) - (Source) - X -Destination
SWAP
Swap Register Halves
Register [31:16[_Register [15:0J
TAS
Test and Set an Operand
(Destination) Tested _CC; 1 -[7] OF Destination
Trap
PC _ - (SSP); SR _ - (SSP); (Vector) -PC
TRAPV
Trap on Overflow
If
TST
Test and Operand
(Destination) Tested - CC
UNLK
Unlink
An -SP; (SP) + _An
NOTES:
[ ] = bit number
A
= logical AND
p
= logical OR
= logical exclusive OR
= logical complement
.-
.
0
1
U
=
=
=
=
=
N
Z
V
C
· · · ·
·· ···
·· · ·
0
- - - - -
TRAP
p
X
then TRAP
U
- -
·
-
···
··
- - · ·
· ·
· · ·
- · ·
- · ·
U
-
-
··
·
- -
·
·
· ·
0
0
0
0
- - - - - - - - 0 0
- - - - -
··
affected
unaffected
cleared
set
undefined
STANDARD INSTRUCTION CLOCK PERIODS
Note
The number of clock periods shown in Table 26 delineate the
time required to perform the operations, store the results, and
read the next instruction. The number of bus read and write
cycles is shown in parenthesis as (r/w). The number of clock
periods and the number of read and write cycles must be added
respectively to those of the effective address calculation where
indicated.
The number of periods includes instruction fetch and all
applicable operand fetches and stores.
EFFECTIVE ADDRESS OPERAND
CALCULATION TIMING
Table 23 lists the number of clock periods required to compute
an instruction:s effective address. It includes fetching of any
extension words, the address computation, and fetching of the
memory operand. The number of bus read and write cycles is
shown in parenthesis as (r/w). Note there are no write cycles
involved in processing the effective address.
In Table 26, the headings have the following meanings:
An =address register operand, Dn =data register operand,
ea = an operand specified by an effective address, and
M = memory effective address operand.
MOVE INSTRUCTION CLOCK PERIODS
IMMEDIATE INSTRUCTION CLOCK PERIODS
Tables 24 and 25 indicate the number of clock periods for the
move instruction. This data includes instruction fetch, operand
reads, and operand writes. The number of bus read and write
cycles is shown in parenthesis as (r/w).
The number of clock periods shown in Table 27 includes the
time to fetch immediate operands, perform the operations, store
the results, and read the next operation. The number of bus read
and write cycles is shown in parenthesis as (r/w). The number
1-44
16-BitMPU
R68000
Table 23.
Effective Address Calculation Tinting
Addressing Mode
Byte, Word
Long
Register
On
An
Data Register Direct
Address 'Register Direct
(An)
(An) +
0(0/0)
0(0/0)
0(0/0)
0(0/0)
Address Register Indirect
Address Register Indirect with Postincrement
4(1/0)
4(1/0)
8(2/0)
8(2/0)
-(An)
deAn)
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
6(t/O)
8(2/0)
10(2/0)
12(3/0)
deAn, ix)*
xxx,W
Address Register Indirect with Index
Absolute Short
10(2/0)
,8(2/0)
14(3/0)
12(3/0)
xxx.L
d(PC)
Absolute Long
Program Counter with Displacement
12(3/0)
8(2/0)
16(4/0)
12(3/0)
d(PC, ix)*
#xxx
Program Counter with Index
Immediate
10(2/0)
4(1/0)
14(3/0)
8(2/0)
Memory
*The size of the index register (ix) does not affect execution time.
Table 24.
Move Byte and Word Instruction Clock Periods
Oesiination
On
An
(AnY'
(An) +
-(An)
deAn)
d(An,lx)*
xxx.W
xxx.L
4(1/0)
4(1/0)
8(2/0)
4(1/0)
4(1/0)
8(2/0)
8(1/1)
8(1/1)
12(2/1)
8(1/1)
8(1/1)
12(2/1)
8(1/1)
8(1/1)
12(2/1)
12(2/1)
12(2/1)
16(3/1)
14(2/1)
14(2/1)
18(3/1)
12(2/1)
12(2/1)
16(3/1)
16(3/1)
16(3/1)
20(4/1)
(An) +
-(An)
deAn)
8(2/0)
10(2/0)
12(3/0)
8(2/0)
10(2/0)
12(3/0) .
12(2/1)
14(2/1)
16(3/1)
12(2/1)
14(2/1)
16(3/1)
12(2/1)
14(2/1)
16(3/1)
16(3/1)
18(3/1)
20(4/1)
18(3/1)
20(3/1)
22(4/1)
16(3/1)
18(3/1)
20(4/1)
20(4/1)
22(4/1)
24(5/1)
deAn, ix)*
xxx.W
xxx.L
14(3/0)
12(3/0)
16(4/0)
14(3/0)
12(3/0)
16(4/0)
18(3/1)
16(3/1)
20(4/1)
18(3/1)
16(3/1)
20(4/1)
18(3/1)
16(3/1)
20(4/1)
22(4/1)
20(4/1)
24(5/1)
24(4/1)
22(4/1)
26(5/1)
22(4/1)
20(4/1)
24(5/1)
26(5/1)
24(5/1)
28(6/1)
d(PC)
d(PC, ix)"
#xxx
12(3/0)
14(3/0)
8(2/0)
12(3/0)
14(3/0)
8(2/0)
16(3/1)
18(3/1)
12(2/1)
16(3/1)
18(3/1)
12(2/1)
16(3/1)
18(3/1)
12(2/1)
20(4/1)
22(4/1)
16(3/1)
22(4/1)
24(4/1) .
18(3/1)
20(4/1)
22(4/1)
16(3/1)
24(5/1)
26(5/1)
20(4/1)
Source
On
An
(An)
"The size of the index register (ix) does not affect execution time,
of clock periods and the number of read and write cycles must
be added respectively to those of the effective adress calculation where indicated,
SINGLE OPERAND INSTRUCTION CLOCK PERIODS
Table 28 indicates the number of clock periods for the single
operand instructions. The number of bus read and write cycles
i.s shown in parenthesis as (r/w) , The number of clock periods
and the number of read and write cycles must be added respectively to those of the effective address calculation where
indicated.
In Table 27, the headings have the following meanings:
# = immediate operand, Dn =data register operand,
An = address register operand, M = memory operand, and
SR = status register.
1-45
R68000
16-Bit MPU
Table 25.
Move Long Instruction Clock Periods
Destination
Source
On
An
(An) +
-(An)
dIAn)
12(112)
12(112)
12(112)
12(112)
20(3/2)
12(112)
12(112)
20(3/2)
20(3/2)
22(3/2)
24(4/2)
20(3/2)
22(3/2)
24(4/2)
Dn
An
(An)
4(110)
4(1/0)
4(110)
12(3/0)
4(1/0)
12(3/0)
(An) +
-(An)
dIAn)
12(3/0)
14(3/0)
16(4/0)
12(3/0)
20(3/2)
14(3/0)
16(4/0)
22(3/2)
24(4/2)
deAn, ix)'
xxx.W
xxx.L
18(4/0)
16(4/0)
20(5/0)
18(4/0)
16(4/0)
20(5/0)
26(4/2)
28(5/2)
26(4/2)
24(4/2)
28(5/2).
d(PC)
d(PC, ix)"
#xxx
16(4/0)
18(4/0)
12(3/0)
16(4/0)
18(4/0)
24(4/2)
26(4/2)
20(3/2)
24(4/2)
26(4/2)
20(3/2)
20(3/2)
24(4/2)
12(3/0)
..
(An)
deAn, ix)'
xxx.. W
xxx.L
16(2/2)
18(2/2)
16(2/2)
16(2/2)
24(4/2)
18(2/2)
26(4/2)
16(2/2)
24(4/2)
20(3/2)
20(3/2)
28(5/2)
24(4/2)
26(4/2)
28(5/2)
26(4/2)
28(4/2)
30(5/2)
24(4/2)
26(4/2)
28(5/2)
28(5/2)
30(5/2)
32(6/2)
26(4/2)
24(4/2)
28(5/2)
30(5/2)
28(5/2)
32(6/2)
32(5/2)
30(5/2)
34(6/2)
30(5/2)
28(5/2)
32(6/2)
32(6/2)
36(7/2)
24(4/2)
26(4/2)
20(3/2)
28(5/2)
30(5/2)
24(4/2)
30(5/2)
32(5/2)
26(4/2)
28(5/2)
30(5/2)
24(4/2)
32(5/2)
34(6/2)
28(5/2)
34(6/2)
'The size of the index register (ix) does not affect execution time.
Table 26.
Instruction
Standard Instruction Clock Periods
Size
op, Ant
ADD
Byte, Word
Long
8(110)+
6(1/0) + "
op, On
4(1/0) +
6(1/0) + "
8(111)+
12(1/2)+
AND
Byte, Word
Long
-
4(110) +
6(1/0) +"
8(1/1)+
12(1/2) +
CMP
Byte, Word
Long
DIVS
-
-
158(1/0) +'
DIVU
-
-
140(1/0) +'
EOR
Byte, Word
Long
-
4(1/0)""
8(1/0)' ..
MULS
-
-
MULU
-
-
OR
Byte, Word
Long
-
SUB
Byte, Word
Long
4(110)+
6(110)+
6(1/0)+
6(1/0)+
op On,
.~'"
_. _ _ _ 0. _ _ _ _
70(110) +'
70(1/0) + '
8(1/0) +
6(1/0)+ ..
8(1/1)+
12(1/2) +
-
4(110)+
6(1/0)+ ..
8(1/1)+
12(1/2)+
4(1/0)+
6(110)+ ..
8(111) +
12(1/2) +
NOTES:
+ add effective address calculation time
t word or long only
, indicates maximum value
. " The ba~e time of six clock periods is increased to eight if the effective address mode is register direct or immediate (effective address time
should also be added).
'" Only available effective address mode is data register direct
DIVS, DIVU The divide algorithm used by the R6S000 provides less than 10% difference between the best and worst case timings.
MULS, MULU The multiply algorithm requires 38 + 2n clocks where n is defined as:
MULU: n = the number of ories in each
MULU: n = concatanate the with a zero as the LSB; n is the resultant number of 10 or 01 patterns in the 17-bit source; I.e., worst
case happens when the source is $5555.
1-46
R68000
16-Bit MPU
Table 27.
Immediate Instruction Clock Periods
Size
op #, On
op If, An
opt, M
ADDI
Byte. Word
Long
8(2/0)
16(3/0)
-
12(2/1)+
20(3/2)+
ADDQ
Byte. Word
Long
4(1/0)
8(1/0)
ANDI
Byte. Word
Long
8(2/0)
16(3/0)
-
12(2/1)+
20(3/1)+
CMPI
Byte. Word
Long
8(2/0)
14(3/0)
-
8(2/0)+
1"\,,,0)+
EORI
Byte. Word
Long
8(2/0)
16(3/0)
12(2/1)+
20(3/2)+
MOVEa
Long
ORI
Byte. Word
Long
8(2/0)
16(3/0)
-
SUBI
Byte. Word
Long
8(2/0)
16(3/0)
SUBa
Byte. Word
Long
4(1/0)
8(1/0)
Instruction
8(1/0)*
8(1/0)
4(1/0)
8(1/0)*
8(1/0)
8(1/1)+
12(112)+
12(2/1)+
20(3/2)+
12(2/1)+
20(312)+
8(1/1) +
12(1/2)+
+ add effective address calculation time
* word only
Table 28.
Single Operand Instruction Clock Periods
Size
Register
CLR
Byte. Word
Long
4(1/0)
6(1/0)
.8(1/1)+
12(1/2) +
NBCD
Byte
6(1/0)
8(1/1)+
NEG
Byte. Word
Long
4(1/0)
6(1/0)
8(1/1)+
12(1/2) +
NEGX
Byte. Word
Long
4(1/0)
6(1/0)
8(1/1) +
12(1/2) +
NOT
Byte. Word
Long
4(1/0)
6(110)
8(1/1)+
12(112)+
Byte. False
Byte. True
4(1/0)
6(110)
8(1/1) +
8(1/1)+
TAS
Byte
4(1/0)
10(1/1)+
TST
Byte. Word
Long
4(110)
4(1/0)
4(110)+
4(1/0)+
Instruction
SCC
~
+ add effective address calculation time
1-47
Memory
16-Bit MPU
R68000
SHIFT/ROTATE INSTRUCTION CLOCK PERIODS
CONDITIONAL INSTRUCTION CLOCK PERIODS
Table 29 delineates the number of clock periods for the shift
and rotate instructions. The number of bus read and write cycles
is shown in parenthesis as: (r/w). The number of clock periods
and the number of read and write cycles must be added respectively to those of the effective address calculation where
indicated.
Table 31 delineates the number of clock periods required for
the conditional instructions. The number of bus read and write
cycles is indicated in parenthesis as: (r/w). The number of clock
periods and the number of read and write cycles must be added
respectively to those of the effective address calculation where
indicated.
BIT MANIPULATION INSTRUCTION CLOCK PERIODS
JMP, JSR, LEA, PWA, MOVEM INSTRUCTION CLOCK
PERIODS
Table 30 indicates the number of clock periods required for the
bit manipulation instructions. The number of bus read and write
cycles is shown in parenthesis as: (r/w). The number of clock
periods and the number of read and write cycles must be added
respectively to those of the effective address calculation where
indicated.
Table 29.
Table 32 indicates the number of clock periods required for the
jump, jump to subroutine, load effective address, push effective address, and move multiple registers instructions. The
number of bus read and write cycles is shown in parenthesis
as: (r/w).
Shift/Rotate Instruction Clock Periods
Size
Register
Memory
ASR,ASL
Byte, Word
Long
6 + 2n(1/0)
8 + 2n(1I0)
8(111)+
LSR, lSl
Byte, Word
long
6 + 2n(1/0)
8(1/1)+
8 + 2n(1/0)
-
ROR,ROL
Byte, Word
long
6 + 2n(1/0)
8(1/1)+
8 + 2n(1/0)
-
ROXR, ROXl
Byte, Word
Long
6 + 2n(1/0)
8(1/1)+
-
Instruction
-
8 + 2n(1/0)
+ add effective address calculation time
n is shift or rotate count
Table 30.
Bit Manipulation Instruction Clock Periods
Dynamic
Static
Instruction
Size
Register
Memory
BCHG
Byte
long
-
8(1/1)+
8(110)·
BClR
Byte
long
10(1/0)'
-
BSET
Byte
long
-
8(1/1)+
8(110)·
BTST
Byte
long
-
-
+ add effective address calculation time
* indicates maximum value
1-48
Memory
-
12(2/1) +
-
12(2/0)'
-
8(1/1)+
14(2/ot
12(2/1) +
-
12(2/1) +
-
12(2/0)'
4(1/0)+
-
-
6(1/0)
Register
10(2/0)
8(2/0)+
-
16-Bit MPU
R68000
Table 31.
Instruction
Displacement
BCC
10(2/0)
10(2/0)
BRA
Byte
Word
10(2/0)
BSR
Byte
Word
1812/21
18(2/2)
DBCC
CC true
CC false
Size
(An)
Branch Not Taken ..
Branch Taken
Byte
Word
Table 32.
Instr
Conditional Instruction Clock Periods
8(110)
12(210)
-
10(210)
-
-
12(210)
10(2/0)
14(3/0)
JMP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK PERIODS
(An) +
-(An)
deAn)
xxx.W
dIAn, Ix)" +
xxx.L
d(PC)
d(PC, Ix)"
JMP
-
8(2/0)
-
-
10(2/0)
14(3/0)
10(2/0)
12(3/0)
10(2/0)
14(3/0)
JSR
-
16(2/2)
-
-
18(2/2)
22(2/2)
18(212)
20(3/2)
18(2/2)
22(2/2)
4(110)
-
-
8(210)
12(2/0)
8(210)
12(3/0)
8(210)
12(210)
12(112)
-
-
16(212)
20(212)
16(2/2)
20(3/2)
16(2/2)
20(212)
LEA
PEA
MOVEM
M-R
MOVEM
R-M
Word
12 + 4n
(3 + n/O)
12 + 4n
(3 + n/O)
-
16 + 4n
(4 + n/O)
18 +4n
(4 + n/O)
16 + 4n
(4 + n/O)
20 + 4n
(5 + n/O)
16 + 4n
(4 + n/O)
18 + 4n
(4 + n/O)
Long
12 + 8n
(3 + 2n/0)
12 + 8n
(3 + 2n/0)
-
16 + 8n
(4 + 2n/0)
18 + 8n
(4 + 2n/0)
16 + 8n
(4 + 2n/0)
20 + 8n
(5 + 2n/0)
16 + 8n
(4 + 2n/0)
18 + 8n
(4 + 2n/0)
-
-
--
-
Word
Long
8 + 4n
(2/n)
8 + 8n
(2/2n)
-
8 + 4n
12 + 4n
14 + 4n
12 + 4n
16 + 4n
(2/n)
(3/n)
(3/n)
(3/n)
(4/n)
-
8 + 8n
(212n)
12 + 8n
14 + 8n
12 + 8n
16 + 8n
(3/2n)
(3/2n)
(3/2n)
(4/2n)
-
n Is the number of registers to move
" The size of the index register (ix) does not affect the instruction's execution time
Table 33.
MUL TI·PRECISION INSTRUCTION CLOCK PERIODS
Table 33 delineates the number of clock periods for the multiprecision instructions. The number of clock periods includes the
time to fetch both operands, perform the operations, store the
results, and read the next instructions. The number of read and
write cycles is shown in parenthesis as: (r/w).
In Table 33, the headings have the following meanings: On = data
register operand and M = memory operand.
1-49
Multi·Precision Instruction Clock Periods
Instruction
Size
op On, On
op M, M
ADDX
Byte, Word
Long
4(1/0)
8(110)
18(3/1)
30(5/2)
CMPM
Byte, Word
Long
-
12(3/0)
20(5/0)
SUBX
Byte, Word
Long
4(110)
8(110)
18(3/1)
30(5/2)
ABCD
Byte
6(110)
18(3/1)
SBCD
Byte
6(110)
18(3/1)
R68000
16-Bit MPU
MISCELLANEOUS INSTRUCTION CLOCK PERIODS
EXCEPTION PROCESSING CLOCK PERIODS
Table 34 and 35 indicate the number of clock periods for the
following miscellaneous instructions. The number of bus read
and write cycles, is llhown in parenthesis as: (r/w). The !lumber
of clock periods'plus the number of read and write cycles must
be added to those of the effective address calculation where
indicated.
Table 36 delineates the number of clock periods for exception
processing'. The number of clock periods includes the time for
all stacking,the vector fetch, and the fetch of the first instruction of the handler,routine. The number of bus read and write
cycles is shown in parenthesis as (r/w).
Table 34.. Miscellaneous Instruction Clock Periods
,Size
Register
AND I to CCR
Byte
20(310)
-
ANDI to SR
Word
20(310)
-
10(110)+
Instruction
Memory
Instruction
Size
Register
LINK
-
16(212)
MOVE from USP
-
4(110)
-
-
MOVE to USP
4(1/0)
-
4(110)
-
EORI to CCR
Byte
20(3/0)
-
NOP
-
EORI to SR
~ord
20(310)
-
RESET
-
ORI toCCR
Byte
20(310)
-
RTE
ORI to SR
Word
20(3/0)
-
RTR
-
RTS
-
-
CHK
MOVE from SR
MOVE to CCR
MOVE to SR
-
-
EXG
Word
Long
EXT
6(110)
8(111)+
12(210)
12(210)+
STOP
12(210)
12(210)+
SWAP
6(110)
-
TRAPV
-
-
UNLK
-
4(110)
4(110)
Memory
-
132(110)
-
20(5/0)
' 20(5/0)
-
16(410)
-
·4(0/0).
-
4(110)
-
4(110)
-
12(310)
-
+ add effective address c!!lculation time
Table 35.
Move Peripheral Instruction Execution Times
Instruction
Size
Register_ Memory
Memory_Register.
MOVEP
Word
Long
16(212)
24(214)
16(410)
24(610)
Table 36.
Exception Processing Clock Periods
Exception
Periods
Address Error
50(417)
Bus Error
50(4/7)
CHK 'Instruction
44(5/4)+
Divide by Zero
42(5/4)
Illegal Instruction
34(4/3)
Interrupt
44(5/3)"
Privilege Violation
34(4/3)
RESET"
Trace
40(6/0)
.
34(4/3)
TRAP Instruction
38(4/4)
TRAPV I nSlruation
34(4/3)
+ add effective address calculation time
" The interrupt acknowledge cycle,is !!ssumed to take four clock
periods.
"" Indicates the time from when RESET and HALT are first sampled
.
as negated to when instruction execution starts.
I-50
16-Bit MPU
R68000
MAXIMUM RATINGS
Where:
Rating
Symbol
Value
Unit
Supply Voltage
VCC
-0.3 to +7.0
V
Input Voltage
VIN
-0.3 to + 7.0
V
TA
Tl to TH
o to 70
·C
TSTG
-56 to 150
·C
Operating Temperature Range
Storage Temperature
T A '" Ambient Temperature, °c
OJA '" Package Thermal Resistance, Junction-toAmbient, oelW
Po '" PINT + PI/O
PINT" ICC • VCC, Watts-Chip Internal Power
PliO .. Power Dissipation on Input and Output PinsUser Determined
THERMAL CHARACTERISTICS
Characteristic
Value
Unit
30
55 ±5
·CIW
·CIW
Symbol
Thermal Resistance
64-Pin Ceramic
64-Pin Plastic Dip
9JA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields; however,
it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate logic voltage level (e.g.,
either VSS or VCC.
POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in ·e can be
obtained from:
(1)
TJ = TA + (PD· 0JA)
DC ELECTRICAL CHARACTERISTICS
Vec
= 5.0 Vdc ±5%,
VSS
= 0 Vdc,
TA
= TL to TH
For most applications PliO
+5V
~
R' =740 Il
TEST
POINT
>
~ 910 Il
) 2.9 kll
MM07000
OR EQUIVALENT
- ' - 70 pF
1130 pF
I
Cl= 130 pF
(INCLUDES All PARASITICS)
R~6.0kIlFO~
AS, A1-A23, BG, 00-015, E
FCO-FC2, lOS, R/W, UOS, VMA
R-=1.22 kll FORA1-A23, BG,
FCO-FC2
Figure 41. RESET Test Load
~igure
Figure 42. HALT Test Load
43 .. Test Loads
CLOCK TIMING (See Figure 44)
8 MHz
4 MHz
Min .
Max
Min
Max
Min
Max
Min
Max
Min
Max
F
2.0
4.0
2.0
6.0
2.0
8.0
2.0
10.0
4.0
12.5
MHz
Cycle Time
tcyc
250
500
167
500
125
500
100
500
80
250
ns
Clock Pulse Width
ICl
ICH
115
115
250
250
75
75
250
250
55
55
250
250
45
45
250
250
35
35
125
t25
ns
ICr
ICI
-
10
10
-
10
10
-
10
10
-
5
5
ns
Characteristic
Symbol
Frequency 01 Operation
Rise and Fall Times
10
10
6 MHz
-
-
-
10 MHz
-
~-------tcyc-------'J~
tCH
Figure 44. Input Clock Waveform
1-52
12.5 MHz
-
Unit
16-Bit MPU
R6S000
AC ELECTRICAL SPECIFICATIONS (Vee
= 5.0 Vdc
±5%, VSS
READ AND WRITE CYCLES
= 0 Vdc; TA = TL to TH,
see Figures 45 and 46)
6 MHz.
4 MHz
Charac1eristlc
Num.
Symbol
Min
8 MHz
Max
Min
10 MHz
Max
Min
Max
ICYC
250
500
167
500
125
500
Min
12.5 MHz
Unit
Max
Min
Max
100
500
80
250
ns
1
Clock Period
2
Clock Width low
ICl
115
250
75
250
55
250
45
250
35
125
ns
3
Clock Widlh High
ICH
115
250
75
250
55
250
45
250
35
125
ns
4
Clock Fall Time
ICt
-
10
ns
5
Clock Rise Time
ICr
10
6
Clock low 10 Address
ICLAV
-
6A
10
-
10
-
10
-
5
10
-
10
-
10
5
ns
70
60
-
55
ns
70
-
-
60
-
55
ns
80
-
70
-
60
ns
-
ns
55
ns
Clock High 10 FC Valid
tcHFCV
-
90
-
7
Clock High 10 Address Data
High Impedance (Maximum)
ICHAZx
-
120
-
8
Clock High 10 Address/FC
Invalid (Minimum)
ICHAZn
9'
Clock High 10 AS, OS Low
(Maximum)
ICHSLx
10
Clock High 10 AS, OS Low
(Minimum)
ICHSLn
0
-
0
-
0
-
0
-
0
-
ns
112
Address to AS, OS (Read)
Low/AS Wrile
IAVSL
55
-
35
-
30
-
20
-
0
-
ns
llA2
FC Valid 10 AS, OS (Read)
Low/AS Write
IFCVSL
80
-
70
-
60
-
50
-
40
-
ns
90
0
-
-
80
100
0
-
80
80
-
70
0
-
60
0
-
55
0
-
12'
Clock Low 10 AS, OS High
tCLSH
-
90
-
80
70
-
55
-
50
ns
AS,OS High 10 Address/FC
Invalid
tSHAZ
60
-
-
132
40
-
30
-
20
-
10
-
ns
142
AS, OS Widlh Low (Read)/AS
Wrile
ISL
535
"-
337
-
240
-
195
-
160
-
ns
IOWPW
285
-
170
115
-
80
-
150
105
-
65
ICHSZ
-
120
-
100
80
-
70
ns
ISHRH
tCHRHx
60
50
-
40
20
-
-
80
-
-
-
60
-
-
-
ns
180
-
95
285
-
-
ISH
70
-
60
0
14A2
OS Width Low (Wrile)
152
AS, OS Widlh High
16
Clock High 10 AS, OS High
OS High
-
ns
60
ns
-
ns
-
60
ns
-
20
ns
-
ns
30
-
ns
30
-
ns
55
ns
60
ns
15
10
172
AS,
18'
Clock High to RIW High
(Maximum)
19
Clock High to RIW High
(Minimum)
tCHRHn
20'
Clock High 10 RtW Low
tCHRL
-
90
-
80
-
70
-
60
AS Low 10 RIW Valid
tASRV
-
20
-
20
-
20
-
20
tAVRL
45
25
-
20
0
-
0
70
-
60
-
50
140
-
80
-
50
-
80
-
70
100
-
80
-
20AB
212
21A2
10 RIW High
Address Valid 10 RIW Low
FC Valid 10 RIW Low
-
tFCVRL
80
200
-
RIW Low 10 OS Low (Wrile)
tRLSL
23
Clock Low to Data Oul Valid
ICLOO
24
Clock High 10 RIW,
High Impedance
252
OS High 10 Data
262
Oala Out Valid 10 OS low
(Write)
Oala In 10 Clock low
(Setup Time)
27A
late E!ERR low to Clock low
(Selup Time)
282
AS,
OS High
90
-
222
275
-
0
-
0
-
0
iiMA
tcHRZ
-
Out Invalid
tSHOO
80
-
40
-
30
-
20
IOOSl
55
-
35
-
30
-
20
tOICl
30
-
25
-
15
-
tBElCl
45
-
45
-
45
-
tSHOAH
0
490
0
325
0
245
10 OTACK High
-
90
120
1-53
-
-
55
70
ns
0
-
-
ns
15
-
ns
10
-
10
-
ns
45
-
45
-
ns
190
0
150
ns
0
D
16·Bit MPU
R68000
AC ELECTRICAL SPECIFICATIONS -
READ AND WRITE CYCLES (CONTINUED)
4 MHz
Characteristic
Mum.
29
OS
High to Data Invalid
(Hold Time)
High to ~ High
30
AS, OS
31 2
DTACK Low to
Data In
Symbol
tSHDI
tSHBEH
tDALDI
Min
0
0
-
6 MHz
Max
Min,
-
180
0
0
-
-
120
(Setup Time)
32
HALT and til:m:T Input
Transition Time
tRHr,1
0
33
Clock High to ~ Low
tCHGL
34
Clock High to
1m High
tCHGH
-
35
B'R Low to ~
3S
BR High to E
37
37A
200
90
90
0
-
10 MHz
8 MHz
Max
200
80
SO
Min
Max
Min
0
-
0
0
0
-
90
0
-
200
70
70
0
-
12.5 MHz
Max
65
200
SO
SO
Min
0
0
0
-
Max
-
Unit
ns
ns
50
ns
200
ns
50
ns
50
ns
Clk. Per.
tBRLGL
1.5
3.5
1.5
3.5
1.5
3.5
1.5
' 3.5
1.5
3.5
tBRHGH
1.5
3.5
1.5
3.5
1.5
3.5
1.5
3.5
1.5
3.5
Clk. Per.
BGACK Low to EHigh
tGALGH
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
Clk. Per.
!mACK Low to BR High
tBGKBR
30
-
25
-
20
-
20
-
20
-
ns
tGLZ
-
120
-
100
-
80
-
70
-
60
ns
tGH
1.5
-
1.5
-
1.5
-
1.5
.-
1.5
Low
High
(to Prevent Rearbitration)
38
E Low to Bus High
Impedance (with AS High)
39
BG Width
40
Clock Low to VMA Low
41
Clock Low to E Transition
42
E Output Rise and Fall Time
43
High
tCLC
-
100
85
tEr,f
-
-
-
25
-
25
VMA Low to E High
tvMLEH
325
-
240
-
44
AS, OS
tSHVPH
45
E Low to AddressNMAlFC
Invalid
tELAI
55
4S
BGACKWidth
tBGL
475
Asynchronous Input
Setup Time
tASI
High to VPA High
tCLVML
90
-
80
-
25
ns
150
-
90
-
ns
0
120
0
90
0
70
ns
-
30
-
10
-
10
-
ns
1.5
-
1.5
-
1..5
1..5
25
-
-
-
20
-
1.5
30
20
-
20
-
25
-80
E Width High
tEH
900
-
600
-
51
E Width Low
tEL
1400
-
900
-
52
E Extended Rise Time
tclEHX
53
Data Hold from Clock High
tCHDO
0
-
54
Data Hold from E Low (Write)
tELDOZ
SO
-
40
5.5
RIW to Data Bus Impedance
Change
tRLDO
55
-
35
-
564
HALT/RESET Pulse Width
tHRPW
10
-
10
-
50
25
ISO
-
tBELDAL
-
ns
-
0
-
OS Invalid
200
ns
4.5
5.5
35
30
E Low to AS.
25
Clk. Per.
-
-80
BERR Low to DTACK Low
49
-
70
-
70
240
0
tELSI
483
70
-
70
-
80
0
80
-
-
Clk. Per.
ns
20
-
20
-
20
-
ns
-80
-
-80
-
-80
-
ns
450
-
3.50
-
280
-
ns
700
-
5.50
-
440
-
ns
-
80
-
SO
-
80
ns
0
-
30
-
10
-
30
0
-
0
-
ns
20
-
15
-
ns
20
-
10
-
ns
10
-
10
-
Clk. Per.
Notes:
1. For a loading capacitance of less than or equal to 50 picofarads, subtract 5 nanoseconds from the value given in these columns.
2. Actual value depends on cleek period.
3. If #47 is satisfied for both DTACK and BERR, #48 may be 0 nanoseconds.
4. For power up, the MPU must be held in RESET state for 100 ms to stabilize all on-chip circuitry. After the system is powered up, #.5S refers
to the minimum pulse width required to reset the system.
5. If the asynchronous setup time (#47) requirements are satisfied the DTACK low-te-data setup time (#31) requirement can be ignored. The data
must only satisfy the data-in clock-low setup time (#27) for the following cycle.
S. When AS and
RJW are
equally loaded (±20%), subtract 10 nanoseconds from the value given in these columns.
1-54
R68000
16-BitMPU
Sl
A1-A23
S2
S3
S4
S5
S6
S7
----t--tt-'r
@,~~oj{.
LDSIUDS _ _ _
..J~;~;;~---'-----""'--J
RIW
FCO-FC2 _ _ _ _ _+_~Jr~~--r_+_-------t_-----_t__t+_---------
ASYNCHRONOUS~-------------~----+---'~---+--------+-~~--------
INPUTS
(NOTE 1)
BERRIBR -------------------------,.
(NOTE 2)
DATA IN -
-
-- -
-
-
-
-
-- - - -
-
-
-
NOTES:
1. SETUP TIME FOR THE ASYNCHRONOUS INPUTS BGACK, IPLO-IPL2, AND VPA GUARANTEES THEIR RECOGNITION AT THE
NEXT FALLING EDGE OF THE CLOCK.
2. BR NEEDS FALL AT THIS TIME ONLY IN ORDER TO INSURE BEING RECOGNIZED AT THE END OF THIS BUS CYCLE.
3. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE OF
2.0 VOLTS, UNLESS OTHERWISE NOTED.
Figure 45.
Read Cycle Timing
1-55
16-Bit MPU
R68000
SO
CLK
---'
-
-r-
1+-0
.J p.- ~I@
...J
-
:..-
-
~®
FCD-FC2
ASYNCHRONOUS
INPUTS
X
14
SO
S7
... 0
---+
... ~ t-@-
--
'IL
@-
e
..-----..
\.
/
@-+ l -
..- ®
0 ~e-
e I+--
S6
~ tc---J
-0
@- ...
~
S5
~@
140
DATA OUT
S4
S3
S2
~~C-J
~
~
Al-M3
LDS/UDS
Sl
~
~@
t-
t-
...
r- t-®
~@
r-@-
~
@
""-
I;,-@
)
,..
~ f+@
@- I+-
~
®
I--@- ~®-.
~
rt-®'"
'rr-
-
}f-
t-®
-
Ie
~@-----
Ie--
~
@ /-4-+
NOTES:
1. BECAUSE OF LOADING VARIATIONS, RiW MAY BE VALID AFTER AS EVEN THOUGH BOTH ARE INITIATED BY THE RISING
EDGE OF S2 (SPECIFICATION 20A).
2. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE OF
2.0 VOLTS, UNLESS OTHERWISE NOTED.
Figure 46.
Write Cycle Timing
16-Bit MPU
R6S000
AC ELECTRICAL SPECIFICATIONS (Vee
= 5.0 Vdc ± 5%,
VSS
= 0 Vdc,
BUS ARBITRATION
T A = OOto 7.0 0 e. See Figure 47..)
..
Num.
Symbol
Characteristic
6 MHz
4 MHz
10 MHz
8 MHz
12.5 MHz
Min
Max
Min
Max
Min
Max
Min
Max
-
90
60
70
-
60
70
-
3.5
1.5
33
Clock High 10 BG Low
tCHGL
34
Clock High 10 BG High
tCHGH
-
90
-
80
-
35
BR Low 10 BG Low
IBRLGL
1.5
3.5
1.5
3.5
1.5
36
BR High to BG High
IBRHGH
1.5
3.5
'1.5
3,5
1.5
3.5
37
BGACK Low to BG High
tGALGH
1.5
3,0
1.5
3.0
1.5
3.0
37A
BGACK Low 10 BR High
(to Prevent Rearbitralion)
tBGKBR
30
-
25
-
20
-
38
BG Low to Bus High
Impedance (with AS High)
IGLZ
-
120
-
100
-
39
BG Width High
tGH
1.5
ISGL
1.5
-
1.5
BGACK Widlh
-
1.5
46
1.5
1.5
Min
Unit
Max
50
60
-
50
ns
3.5
1.5
3.5
Clk. Per.
1.5
3,5
1.5
3.5
Clk. Per.
1.5
3.0
1.5
3.0
Clk. Per.
20
-
20
-
ns
80
-
70
-
60
ns
-
1.5
-
1.5
-
Clk. Per.
1.5
-
1.5
-
Clk. Per.
ns
THESE WAVEFORMS SHOULD ONLY BE REFERENCED IN REGARD TO THE EDGE-TO-EDGE MEASUREMENT OF THE TIMING
SPECIFICATIONS. THEY ARE NOT INTENDED AS A FUNCTIONAL DESCRIPTION OF THE INPUT AND OUTPUT SIGNALS.
REFER TO OTHER FUNCTIONAL DESCRIPTIONS AND THEIR RELATED DIAGRAMS FOR DEVICE OPERATION.
STROBES
AND RrW _ _ _ _ _ _ _--J
;------1@
--~------------------,
BG
CLK
NOTES:
1. SETUP TIME FOR THE ASYNCHRONOUS INPUTS BERR, BGACK, BR, DTACK, IPLO-IPL2, AND VPA GUARANTEES THEIR
RECOGNITION AT THE NEXT FALLING EDGE OF THE CLOCK.
2. WAVEFORM MEASUREMENTS FOR ALL INPUTS AND OUTPUTS ARE SPECIFIED AT: LOGIC HIGH=2.0 VOLTS,
LOGIC LOW = 0.8 VOLTS
Figure 47..
AC ELECTRICAL Waveforms':" Bus Arbitration
1-57.
II
R68465
'1'
Rockwell
R68465
DOUBLE-DENSITY FLOPPY DISK
CONTROLLER (DDFDC)
,PRELIMINARY
DESCRIPTION
FEATURES
,The R68465 Double-Density Floppy Disk Controller (DDFDC)
interfaces up to four floppy disk drives to a 68000/68008
microproCessor-based system. The DDFoC simpiifies the System
design by minimIZing both the number of extemal hardware components and software steps needed. to implement the floppy disk
drive (FOD) interface. Control signals supplied by the DDFDC
reduce the number of components required in extemal phase
locked loop and write precompensation circuitry. Memorymapped registers containing commands, status and data simplify
the software interface. Built-in functions reduce the software
overhead needed to control the FDD ihterface. The DDFDC supports both the leM 3740 Single-Density (FM) and IBM System
34 Double-Density (MFM) formats.
.
• Address mark detection circUitry
• Software control 91
-Track stepping rate
-Head load time
-Head unload time
• IBM compatible in both single- and double-density recording
formats
• Programmable data record lengths: 128, 256, 512, 1024,
2048, 4096 or 8192 bytes/sector
• Mul~i-sector and' mult~track 'transfer capability
• Controls up to four floppy disk drives
The DDFDC interfaces directly to the 68000/68008 asynchronous
microprocessor bus and operates with 8-bit byte length data
transferred on the bus. The DDFDe will operate in either DMA
or non-DMA mode. In DMA mode, the MPU need only load the
command into the DDFDC and all data transfers occur under
DMA control. The DDFDe is directly compatible with the
MC68440 Dual Direct Memory Access Controller (ODMAC). In
non-DMA mode, the DDFDC generates an interrupt to the MPU
indicating that a byte 01 data is available.
'
• Data scan capability-will scan a single sector or an entire
track oldata fields, comparing on a byte-by-bYie basis data
in the processor's memory with d,ata read from the disk
• Datli transfers in DMA or non-DMA mode
• Parallel seek operations on up to four drives
• Directly compatible with 68000 1.6-bit and 68008 6-bit asynchronous microprocessor bus
• Single phase 8 MHz Clock
Controller commands, command or device status, and data are
transferred between the DDFDC and the MPU via six Internal
registers. The Main Status 'Register (MSR) stores the DDFOe
status iliformation while four additional status registltrs provicie
result Information to the MPU following each controller command. The Data Register (DR) stores actual disk data, parameters, controller commands and FOD status information for use
by the MPU.
• Single + 5 Volt Power Supply
ORDERING INFORMATION
The R68465 executes 15 separate multi-byte commands:
Read Data
Write Data
Read Deleted Data
Write Deleted Data
Read a Track
Read ID
Seek
Recalibrate(Restore to Track 0)
Part Number
Spe<;ify
Foi'tnata Track
Scan Equal
,
SCan High or Equal
Scan Low or Equal
Sense Interrupt Status
Sense Drive Status
R68465
l
Document No. 68650N08
1-58
eLK Frequency
Temperature Range
8 MHz
O·C to 7O·C
Package: C _ Ceramic
P = PlastiC
Product Description Order No. 707
Rev. 3, March 1984
Double-Density Floppy Disk Controller (DDFDC)
R68465
RDW
DO-07 - " \
RDD
-V
veo
WDA
ASYNCHRONOUS
BUS
INTERFACE
WE
RESET
PSO-PS1 "
cs
RS
ROY
IRQ
RIW
DTACK
DMAC
INTERFACE
FDD
SERIAL
DATA
INTERFACE
WCK
{
V
IDX
R68465
DDFDC
WPITS
FlTITRKO
lCTIDIR
DACK
FRlSTP
DONE
RWISEEK
REQ
HDl
ClK
USO
Vee
US1
HDSEl
GND
-
FDD
. STATUS
INTERFACE
MFM
Figure 1. DDFDC Input and Output Signals
PIN DESCRIPTION
RS-DatalStetua Reglater Select. This input selects the Data
or Status Register for reading from or writing to. When
RS = high, the Data Register is select8!! and the state of RIW
determines whether it is a read (R/W .. high) or a write
(RIW .. low) operation. when RS = low, the Status Register is
selected. This register may only be read (Riii ,. high); the state
FlW .. low is invalid when the Status Register is selected.
Throughout this document signals are presented using the terms
active and inactive. or asserted and negated. independent of
whether the signal is active in the high-voltage state or lowvoltage state. (The active state of each logic pin is described
below.) Active low signals are denoted by a superscript bar. For
example. RiW indicates read is activelpigh and a write is active
'
low.
IRQ-Interrupt Request. This active low output is the interrupt
request generated by the'OOFDC to the MPU. IRQ is asserted
upon completion of some OOFDC commands and before a data
byte is transferred between the OOFOC and the data bus (in the
Non-OMA mode).
BUS INTERFACE
DO-D7-Data Lines. The bidirectional data lines transfer data
between the OOFDC and the a-bit data bus.
RIW-ReadIWrHe. This input defines the data bus transfer as a
read or write cycle. When high (read), the data transfer is from
the OOFOC to the data bus. When low (write), the data transfer
is from the data bus to the OOFDC.
ClK-ClOCK. The clock is a TTL compatible a MHz square
wave signal.
DTACK-Data Transfer Acknowladge. This signal is the asynchronous handshake line for information transfer on the 68000
system bus. It is generated by the ODFOC as an acknowledge
to the CS signal in an asynchronous transfer. A low output
indicates that valid data is on the bus (read cycle) or that data
has been written (write cycle). Except when being asserted, this
signal is normally in the high impedance state.
RESET-RESET. This active high input places the OOFDC in the
idle state and resets the output lines to the floppy disk drives
to the low state.
CS-Chlp Select. The OOFOC is selected when the CS input
is low.
1-59
R68465
Double-Density Floppy Disk Controller (DDFDC)
The output characteristics of DTACK are the same as other
system interface signals with allowances for an external pullup resistor such that the output is driven to the high level first
and then to the high impedance state.
FDD STATUS INTERFACE
DIRECT MEMORY ACCESS CONTROLLER
(DMAC) INTERFACE
lOX-Index. An active high input signal from the FDD indicates
the index hole is under the index sensor. Index is used to synchronize DDFDC timing.
OACK-OMA Acknowledge. The DMA transfer acknowledge
signal is a TIL compatible input generated by the DMA controller
(DMAC) contrOlling the DDFDC. The DMA cycle is active when
DACK is low and the DDFDC is performing a DMA transfer.
REQ-Oata DMA Request. The transfer request signal is a TTL
compatible output generated by the DDFDC to request a data
transfer operation under control of the DMAC (in the DMA mode).
The request is active when REQ = low. The signal is reset
inactive when DMA Acknowledge (DACK) is asserted (lOW).
DONE-DMA Transfer Complete. This Input signal is issued to
the DDFDC when the DMA transfer for a channel is complete.
The signal is active low concurrent with the DACK Input when
the DMA operation is complete as a result of that transfer.
ROY-Ready. An active high input signal indicates the FDD is
ready. to send data to, or receive data from, the DDFDC.
RWISEEK-Read WritelSeek. Mode selection signal to the FDD
which controls the multiplexer from the multiplexed signals.
When RW/SEEK is low, the Read/Write mode is commanded;
when RW/SEEK is high, the Seek mode is commanded.
RW/sEEK
Mode
. Active FDD Interface Signals
Low
ReadlWrite
Wp, FLT, l.CT, FR
High
Seek
TS, TRKO, DIR, STP
WPITS-Wrlte Protect/1Wo Side. An active high multiplexed
input Signal from the FDD. In the Read/Write mode, WP/TS high
indlcatas the media is write-protected. In the Seek mode, WP/TS
high Indicates the media is two-Sided.
FDD SERIAL DATA INTERFACE
ROD-Read Data. Read Data input from the floppy disk drive
(FDD) containing clock and data bits.
.
ROW-Read Data Window. Data Window input generated by
the Phase Locked Loop (PLL) and used to sample data from
the FDD.
VCO-Varlable Frequency Oscillator Sync;. This output signal
'inhibits the VCO in the PLL circuit when low and enables the
VCOln the PLL circuit when high. This inhibits ROD and ROW
from being generated until valid data is detected from the FDD.
FLTITRKO-Faultm'llck Zero. An active hi9.!!..!!:Jultiplexed input
from the FDD. In the Read/Wrlte mode (AW/SEEK
low),
FLTITRKO high indicates an FDD fault. In the Seek mode,
FLTITRKO high indicates that the read/write head is positioned
over track zero.
=
,RESET
OTACK
RiW
WCK-Wrlte Clock. This input clock determines the Write Data
rate to the FDD. The data rate is 500 KHz in the FM mode
(MFM = low) and '1 MHz in the MFM mode (MFM = high). The
pulse width is 250 ns (typical) in both modes.
WDA~Wrlte
Data. Serial write data output to the FDD containing both clock and data bits.
WE-Write Enable. This output signal enables the Write Data
into the FDD when high.
PSO-PS1-P.....,Ift. These outputs are encoded to convey write
compensation status during the MFM mode to determine. early,
late or normal times as follOWS:
Preshlft Outputs
o
Write PrecompenBlltlon Ststue
PSO
PSI
Normal
Late
Early
Invalid
0
0
1
1
0
1
0
1
z
Low, 1 = High
CS
RS
00
Dl
02
D3
D4
05
D6
D7
REQ
DACK
DONE
IDX
IRQ
ClK
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
38
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
R68465 Pin Diagram
vec
RW/sEEK
lCT/OIR
FRlSTP
HOl
ROY
WP/TS
FlTITRKO
PSO
PSI
WDA
USO
USI
HDSEl
MFM
WE
veo
RDO
ROW
WCK
Double-Density Floppy Disk Controller (DDFDC)
R68465
"'' '"' -""'-,
USO-US1-Unlt Select. Output signals for floppy disk drive
LCTIDIR-Low Current/Direction. A multiplexed output to the
FOO. In the ReadlWrite mode, LCT/OIR is low when the
read/write head is to be positioned over the inner tracks and the
LCTIOIR is high when the head is to be positioned over the outer
tracks. In the Seek mode, LCT/OIR controls the head direction.
When LCT/DIR is high, the head steps to the outside of the disk;
when LCT/DIR is low, the head steps to the inside of the disk.
Unit Select
FR/STP-Fault Reset/Step. A multiplexed output to the FOO.
In the ReadlWrite mode, FR/STP high resets the fault indicator
in the FOD. An FR pulse is issued at the beginning of each read
or write command prior to issuing HOL. In the Seek mode,
FR/STP provides the step pulses to move the read/write head
to another track in the direction indicated by the LCT/DIR signal.
uso
US1
0
0
1
1
0
1
0
1
o = Low, 1
Floppy Disk
Drive Select
0
1
2
3
= High
MFM-MFM Mode. Output signal to the FOD to indicate MFM
or FM mode. Selects'the MFM mode when MFM = high and
low.
the FM mode when MFM
=
HDL-Head Load. An active high output to notify the FDO that
the read/write head should be loaded (placed in contact with
the media). A low level indicates the head should be unloaded.
VCC-Power. + 5V dc.
GND-Ground (V..).
HD-Head Select. An output to the FDD to select the proper
high and
read/write head. Head One is selected when HO
Head Zero is selected when HD
low.
=
=
......
I/O
BUFFERS
DO·D7
....
RESET
Rfii
CS
ROD
VCO
WCK
OPERATION
CONTROL
SERIAL
WRITE
CONTROL
RS
DTACK
ROW
SERIAL
READ
CONTROL
I
WDA
WE
PSO, PS1
rn
ROY
:l
III
....I
c(
P
z
II:
'ir ';
w
DMA
CONTROL
CLK
VCC
GND
WP/TS
DRIVE
INTERFACE
CONTROL
FLT/TRKO
LCT/DIR
Fe
..
....
lOX
INPUT
PORT
OUTPUT
PORT
FRISTP
~
RW/SEEK
HDL
f----f-----
HDSEL
USO
US1
r-------
Figure 2.
DDFDC Block Diagram
1-61
MFM
D
R68465
Double-Density Floppy Disk Contr911er (DDFDC)
DDFDC REGISTERS
The DIO and ROM timing chart Is shown in Figure S.
The DDFDC contains six registers which may be accessed by
the processor or DMA controller via the system (i.e., microprocessor) bus: a Main Status Register, a Data Register, and
four Result Status Registers. The 8-bit Main Status Register
(MSR) contains the status information of the DDFDC, and may
be accessed at any time. The 8-bit Data Register, consisting of
several registers in a stack with only one register presented to
the data bus at a time, stores data, commands, parameters and
FDD status information. Bytes of data are read out of, or Written
into,the Data Register in order to initiate a command or to obtain
the results of a command execution.
MSR
·7 ROM -Request for Master.
Data Register is not ready.
1
Data Register is ready.
o
MSR
6 DIO
-Data InpuUOutput.
Data transfer is from system to the Data Register.
1
Data transfer is from Data Register to the syStem.
o
MSR
5 EXM -Execution Mode. (Non-DMA mode only).
Execution phase ended, result phase begun.
1
Execution phase started.
o
The read-only Main Status Register facilitates the transfer of data
between the system and the DDFDC. The other Status Registers
(STO, ST1, ST2 and STS) are only available durIng the result
phase, and may be read only after completing a command. The
particular command which has been executed determines how
many of the Status Registers will be read.
The relationship between the status/data registers and the
and RS signals is shown below.
RS
.RIW
function
0
0
1
0
0
1
0
Read Main Status Register
Illegal
Read from Data Register
Write into Data Register
0= LOW,.1
1
2
MSR
!
o
RiW
CB
-Controller (DDFDC) Busy.
DDFDC is not busy, will accept a command.
DDFDC is busy, will not accept a command..
MSR
!
o
D3B
-Floppy Disk Drive (FDD) 3 Busy.
FDD S is not busy, DDFDC will accept read or write
command.
FDD S is busy, DDFDC will not accept read or write
command.
MSR
2
o
High
Table 1 shows each of the status registers used by the DDFDC
and each bit assignment within the individual registers. Table 2
defines the symbols used throughout the command definitions.
Each register bit symbol is defined in the register definition that
follows Table 2.
D2B
-FDD 2 Busy.
FDD 2 is not busy, DDFDC will accept read or write
command.
FDD 2 is busy, DDFDC will not accept read or write
command.
MSR
1 D1B
-FDD 1 Busy.
FDD 1 is flot busy, DDFDC will accept read or write
command.
_
FDD 1 is busy, DDFDC will not accept read or write
command.
o
REGISTER DEFINITIONS
MSR
Main Status Register (MSR)
o
2
D2B
o
0
D1B
DOB
The Main Status Register (MSR) contains the status information of the DDFDC, and must be read by the processor before
each byte is written to, or read from, the Data Register during
the command or result phase. MSR readS are not required during the execution phase. The Data InpuUOutput (DIO) and
Request for Master (ROM) bits in the MSR indicate when data
is ready and in which direction data will be transferred on the
data bus. The maximum time between the last RiW during
command or result phases and the DIO and ROM getting set
or reset is 12 p.S. For this reason, every time the MSR is read
the processor should wait 12 p.S. The maximum time from the
end of the last read in the result phase to when bit 4 (DDFDC
Busy) goes low is also 12 p.S.
DOB
-FDD 0 Busy.
FDD 0 is not busy, DDFDC will accept read or write
command.
FDD 0 is busy, DDFDC will not accept read or write
command.
Status Register 0 (STO)
7
I
IC
6
5
SE
4
EC
3
NR
2
HD
1
I
0
US
USl
I USO
The Status Register 0 (STO) as well as the other status registers
(ST1-STS), are available only during the result phase, and may
be read only after completing a command. The particular command executed determines which status registers are used and
maybe read.
1-62
R68465
Double-Density Floppy Disk Controller (DDFDC)
Table 1. DDFDC Status Register Bit Assignments
Bit Number
Main Status Register (MSFi)
7
6
5
4
3
2
ROM
010
EXM
CB
D3B
D2B
SE
EC
NR
HD
"
1
0
D1B
DOB
.
IC
Status Register 0 (STO)
US
US1
USO
MA
Status Register 1 (ST1)
EN
0
DE
OR
.0
NO
NW
Status Register 2 (ST2)
0
CM
DO
WT
SH
SN
BT
MD
Status Register 3 (ST3)
FLT
WP
ROY
TRKO
TS
HD
US1
usa
Table 2. Command Symbol Description
Name
Symbol
0
00-07
DTL
EaT
Data
Data Bus
Data Length
End of Track
GPL
Gap Length
H
HD(H)
HLT
HUT
MF
MT
Head Address
Head
Head Load Time
Head Unload TIme
FM or MFM Mode
Multi-Track
N
NO
NTN
PTN
R
RS
R/W
ST
SK
SRT
Bytes/Sector
Non-DMA Mode
New Track Number
Present Track Number
Record (Sector)
Register SeleCt
ReadlWrite
SectorslTrack
Skip
Step Rate Time
ST2
ST3
STP
Status 0
Statull1
Stetus 2
Status 3
Sector Test Process
T
USO,US1
Track Number
Unit Select
.. STO
sn
Descrtptlon
The data pattern which is going to be written into a sector.
8-blt data bus, where DO is the least significant data line and 07 is the most significant data line.
When N is defined as 00, DTL is the number of data bytes to read from or write into the sector.
The final sector number on a track. During read or write operation, the DDFDC stopS data transfer
after reading from or writing to the sector equal to EaT.
The length of Gap 3. During readlwrlte commands this value determinas the number of bytas that the
VCO will stay low after two CRC bytas. During the Format a Track command It determlnas the size of
Gap 3.
Head number Oor 1, as specified in 10 field.
A selected head number 0 or 1 which controls th, polarity of pin 27. (H = HI) In all command words).
The head load time in the FDD (2 to 254 ms in 2 ms increments).
The head unload time after a read or write operation hall occurred (16 to 240 ms In 16 ms increments).
VIIhen MF .. 0, FMmode is selected; and when MF .. 1, MFM mode is selected.
When MT = 1, a multi-track operation is to be performed. After finishing a readlwrlte operation on side
0, the DDFDC will automatically start searching for sector 1 on side 1.
.
The number of data bytes written in a sector.
When NO .. 1, operation is in the Non-DMA mode; when NO .. 0, operation is in the DMA mode.
A new' track number, which will be reached as a result of the Seek command. Desired head position..
The track number at the complation of Sense Interrupt Status command. Pr8S!lnt head position.
The sector number to be read or written.
Controls selection of Main Status Register (RS = low) or Data Register (RS .. high).
Either read (R) or write (W) signal
The number of sectors per track.
Skip Deletad Data Address Mark.
The stepping rate for the FDD (1 to 16 ms In 1 ms increments). Stepping rate applies to all drives
(F = 1 ms, E .. 2 ms, etc.)
Four registars which store the status information after a command has been executed. This Information
is available during the result phase after command eXecution. These registers should not be confused
with the Main Status Register (selected by RS .,; low). STO-ST3 may be read only after a command hes
been executed and contein information relevant to that particular command.
During a Scan command, If STP' = 01, the date in contiguous sectors is compared byte by byte with date
sent from the processor (or DMA controller); and ·If STP= 02,then alternate sectors are read and
compared.
The current/selected track number of the medium (0-255).
A selected drive number (0-3).
1-63
I
Double-Density Floppy Disk Controller (DDFDC)
R68465--
ST1
4 OR
-Over Run.
No error.
DDFDC was not serviced by the system during data
1
transfers, within a predetermined time interval.
STO
7 6 IC
o
-Interrupt Code.
Normal Termination (NT). Command was propefly executed and completed. .
Abnormal Termination (AT). Command execution was
started, but was not successfully completed.
Invalid Command (IC). Received command was invalid.
Abnormal Termination (AT). The Ready (ROY) signal
from. the FDD changed state during command
execution.
0
o
o
1
o
ST1
3. .
ST1
2
o
STO
5 SE
-Seek End.
Seek command is not completed.
Seek command completed by DDFDC. _
o
o
1
EC
-Equipment Check.
No error.
Either a fault signal is received from the FDD or the
track 0 signal failed to occur after 256 step _pulses
(Recalibrate Command).
2. DDFDe cannot read 10 field without an error during
. Read 10 command.
3. DDFoe cannot find starting sector during execution
of Read a Track command. .
ST1
1 NW
-Not Writable.
o No error.
D.OFDCc;letected II write protect signal from FDD dur1
ing execution of Write Data, Write Deleted Data or
Form,t a Track commands.
STO
~ NR
-Not Ready.
o
FDD is ready:
1FDD is not ready at issue of read or write command. If
a read l>r'writecommand is issued to side 1 of a singlesided drive, this bit is also set.
ST1
STO
o
! .HD
o
1-
NO
-No Data.
No error.
3 possible errors.
1. DDFDC cannot find sector specified in 10 Register
during execution of Read Data, Write Deleted Data
or Scan commands.
STO
1.
-Not Used. Always Zero.
o
..,...Hil.d Address. (At Interrupt).
Head Select O.
Head Select 1.
MA
-Missing Address Mark:
No error.
2 possible errors.
STO
1. DDFDC cannot detect the 10 Address Mark after
encountering the index hole twice.
~ US-Unit Select. (At Interrupt).
O. 0
FDD 0 selected:
o 1 FDD 1 selected,
1 0
FDD 2 selected.
1 1 - fOOD 3 selected.
2. DDFDC cannot detect the Data Address Mark or
Deleted Data Address Mark. The MD (Missing
Address Mark in Data field) of Status Register 2 is also
set.
!
Status Register 1 (ST1)
6
o
DE
o~1
Status Register 2 (ST2)
o
NW
MA
·5
DD
sn
7
o
1
EN
-End of Track.
No error.
DDFOC attempted to access a sector beyond the last
sector of a track.
ST2
7
!
o
-Not Used. Always Zero.
ST1
~
o
3
2
SH
SN
o
BT
MD
-Not Used. Always Zero.
ST2
sn
!
4
WT
DE
-Data Error.
No error.
DDFoe detected a CRC error in 10 field or the Data field.
1-64
CM-Control Mark.
iIIo error.
DDFDe encountered a sector which contained a Deleted
Data Address Mark during execution of a Read Data,
Read a Track, or Scan command, or the DDFoe encountered a sector which contained a Data Address Mark during execution of a Read Deleted Data command.
Double-Density'Floppy Disk Controller (DDFDC)
R68465
ST2
5 DO
-Data Error in Data Field.
No error.
DDFDC detected a CRC error in the Data field.
ST3
4 TRKO -Track O.
Track 0 (TRKO) signal from the FDD is low.
Track 0 (TRKO) signal is from the FDD is high.
ST2
4 WT
-Wrong Track.
o No error.
Contents of T on the disk is different from that stored
in lOR. Bit is related to NO (Bit 2) of Status Register 1.
ST3
3 TS
-Two Side.
Two Side (TS) signal from the FDD 15 low.
Two Side (TS) signal from the FDD is high.
o
o
o
ST3
2 HD
-Head Select.
Head Select (HD) signal to the FDD is low.
Head Select (HD) signal to the FDD is high.
ST2
3 SH
-Scan Equal Hit.
o No "equal" condition during a scan command.
"Equal" condition satisfied during a scan command.
o
ST3
-Unit Select 1.
1 US1
Unit Select 1 (US1) signal to the FDD is low.
1
Unit Select 1 (US1) signal to the FDD is high.
ST2
~
o
o
SN
-Scan Not Satisfied.
No error.
DDFDC cannot find a sector on the track which meets
the scan command condition.
ST3
o usa
o
ST2
!
o
BT
-Bad Track.
No error.
Contents of T on the disk is different from that stored
in the lOR and T = FF. Bit is related to NO (Bit 2) of
Statos Register 1.
COMMAND SEQUENCE
The DDFDC is capable of performing 15 diff"rent commands.
Each command is initiated by a multi-byte transfer of data from
the system. After command execution, the result of the command may be a multi-byte transfer of data back to the system.
Because of this multi-byte transfer of information between the
DDFDC and the system, each command consists of three
phases:
ST2
o
o
MD
-Missing Address Mark in Data Field.
No error.
DDFDC cannot find a Data Address Mark or Deleted
Data Address Mark during a data read from the disk.
Status
Regist~r
Command Phase-The DDFDC receives all infotmation
required to perform particular operation from ttie system.
'a
3 (ST3)
HD
Execution Phase-The DDFDC performs the instructed
.
operation.
o
2
USl
usa
Result Phase-After completion of the operation, status and
other housekeeping information are made available to the
system.
Status Register 3 (ST3) holds the results of the Sense Drive
Status command.
ST3
7 FL T
-Fault.
Fault (FLT) signal from the FDD is low.
Fault (FLT) signal from the FDD is high.
The bytes of data sent to the DDFDC to form a cOl)'lmand, and
read out of the DDFDC .in the result phase, must occur in the
order shown for each command sequence. That is, the command
Code byte must be sent first followed by the other bytes in the
specified sequence. All command bytes must be written and all
result bytes must be read in each phase. After the last byte of
data in the command phase is receiv!ld by the DDFDC, the
execution phase starts. Similarly, when the last byte of data is
read out in the Result Phase, the command is ended and the
DDFDC is ready to accept a new command. A command can
be terminated by asserting the DONE signal to the DDFDC. This
ensures that the processor can always get the DDFDC's attention even if the command in process hangs up in an abnormal
manner.
o
ST3
6 WP
-Write Protect.
o Write Protect (WP) signal from the FDD is low.
1
Write Protect (WP) signal from the FDD is high.
ST3
~
.0
-Unit Select O.
Unit Select 0 (USO) signal to the FDD is low.
Unit SelectO (US1) signal to the FDD is high.
ROY
-Ready.
Ready(RDY) signal from the FDD is low.
Ready (ROY) signal from the FDD is high.
1-65
o
R68465
Double-D.ensity Floppy Disk Controller (DDFDC)
COMMAND DESCRIPTION
When N = 0 in command byte 6 (FM mode). the Data Length
(DTL) in command byte 9 defines the data length that the DDFDC
must treat as a sector. If DTL is smaller than the actual data
·Iength ina sector. the data beyond the DTL is not sent to the
data bus. The DDFDC reads (internally) the complete sector.
performs the CRC check. and depending upon the manner of
command termination. may perform a multi-sector Read operation. When N is non-zero (MFM mode). DTL has no meaning
and should be: set to FF.
READ DATA
A command set of nine bytes places the DDFDC into the Read
Data mode. After the Read Data command has been received
the DDFDC loads the head (if it is unloaded). waits the specified
Head Settling Time (defined in the Specify command). then
begins reading 10 Address Marks and 10 fields from the disk.
When the current sector number (R) stored in the 10 Register
(IDR) matches the sector n.umber read from the disk. the DDFDC
transfers data from the disk Data field to the data bus.
At the completion of the. Read Data command. the head is not
unloaded until the Head Unload Time (HUT) interval defined in
the Specify command has elapsed. The head settling time may
be avoided between subsequent reads if the processor issues
another command before the head unloads. This time savings
is considerable when disk contents are copied from one drive
to another.
After completion of the read operation from the current sector.
the DDFDCincrements the Sector Number (R) by one. and the
data from the next sector is read and output to the data bus.
This continuous read function is called a "Multi-Sector Read
Operation." The Read Command terminates after reading the
last data byte from sector R when R = EOT. STO bits 7 and
6 are set to 0 and 1. respectively. and STI bit 7 (EN) is set to a 1.
If the DDFDC detects the Index Hole twice in sl!ccession without
finding the right sector (indicated in R), then the DDFDC sets
the No Data (NO) flag in Status Register 1 (ST1) to a 1. sets
Status Register 0 (STO) bits 7 and 6 to 0 and 1. respectively.
and terminates the Read Data commC\nd.
The Read Data command can also be terminated by a low DONE
signal. DONE should be issued at the same time that the DACK
for the last byte of data is sent. Upon receipt of TC. the DDFDC
stops outputting data to the data bus. but continues to read data
from the current sector. checks CRC (Cyclic Redundancy Count)
bytes. and then atthe end of that secto(terminatesthe Read
Data command and sets bits 7 and 6 in STO to 0; The amount
of data which can be handled .with a single command to the
DDFDC depends upon MT (Multi-Track). MF (MFM/FM1.and N
(Number of Bytes/Sector) values. Table 3 shows the transfer
capacity.
After reading the 10 and Data fields in each sector. the DDFDC
checks the CRC bytes. If a read error is detecied (incorrect CRC
in 10 field). the DDFDC sets the Data Error (DE) flag in STI to
a 1. sets the Data Error in Data Field (DO) flag in ST2 to a 1
if a GRC error occurs in the Data field. sets bits 7 and 6 in STO
to 0 and 1, respectively. and terminates the· command.
If the DDfDC reads a Deleted Data Address Mark from the disk.
and the Skip Deleted Data Address Mark bit in the first command byte is not set (SK = 0), then the DDFDC reads all the
data in the sector. sets the Control Mark (CM) flag in ST2 to a
1, and terminates the command. If SK = 1. the DDFDC skips
the sector with the Deleted Data Address Mark and reads the
next sector. The CRC bits in the deleted data field are not
checked when SK = 1.
The multi-track function (MT) allows the DDFDC to reao data
from both sides of the disk. For a particular track. data is transferred starting at sector 1. side 0 and completed at sector L. side
1 (sector L = last sector on the side). This function pertains to
only one track (the same track) on each side of the disk.
Table 3.
DDFDC Transfer Capacity
Multi-Track
(MT)
MFM/FM
(MF)
Bytes/Sector
(N)
0
0
0
1
00
01
(128) (26) =
(256) (26) =
1
1
a
1
00
01
(128) (52) = 6,656
(256) (52) = 13,312
0
0
.0
1
01
02
(256) (15) =
(51.2) (15) =
1
1
a
01
02
(256) (30) = 7,680
(512) (30) = 15,360
a
a
a
1
02
03
(512) (8)
(1024) (8)
1
1
0
1
02
03
(512) (16) = 8,192
(1024) (16)= 16,384
1
.
Maximum Transfer Capacity
(Bytes/Sector) (Number of Sectors)
1-66
=
=
3,328
6,656
3,840
7,680
4,096
8,192
Final Sector Read
from Disk
26 at Side 0
or 26 at Side 1
26 at Side 1
15 at Side 0
or 15 at Side 1
15 at Side 1
8at Side a
or 8 at Side 1
8 at Side 1
Double-Density Floppy Disk Controller (DDFDC)
R68465
WRITE DATA
During disk data transfers from the OOFOC to the· system, the
OOFOC must be serviced.by the system within 27.,.s in the FM
mode, and within 13 p.S in the MFM mode, otherwise the OOFOC
sets the Over Run (OR) flag in ST1 to a 1, sets bits 7 and 6 in
STO to 0 and 1, respectively, aQd terminates the command.
A command set of nine bytes places the OOFOC in the Write
Data mode. After the Write Data command has been received
the OOFOC loads the head (if it is unloaded), waits the specified
Head Settling Time (defined in the Specify command), then
begins reading 10 fields from the disk. When the four bytes (T,
H, R, N) loaded during the command match the four bytes of
the 10 field from the disk, the OOFOC transfers data from the
data bus to the disk Data field.
If the processor terminates a read (or write) operation in the
OOFOC, then the 10 information in the result phase is dependent
upon the state of the MT bit in the first command byte and the
End of Track (EOT) byte. Table 4 shows the values for Track
Number (T), Head Number (H), Sector Number (R), and Number
of Data Bytes/Sector (N), when the processor terminates the
command.
After writing data into the current sector, the DDFDC increments
the sector number (R) by one, and writes into the Data field in
the next sector. The DDFDC continues this multi-sector write
operation until the last byte is written to sector R when R = EOT.
STO bits 7 and 6 are set to 0 and 1, respectively, and STI bit
7 (EN) is set to a 1.
Command Phase:
RIW
BYTE
7
6
5
4
3
2
1
W
1
MT
MF
SK
0
0
1
1
0
2
X
X
X
X
X
HD
USl
usa
3
Track Number (T)
\,
4
Head Number (H)
5
Sector Number (R)
6
Number of Data Bytes per Sector (N)
7
End of Track (EDT)
8
Gap Length (GPL)
9
Data Length (DTL)
0
TtJe command can also be terminated by a low on DONE. If
DONE is sent to the DDFDC while writing into the current sector, then the remainder of the Data field is filled with 00 (zeros).
In this case, STO bits 7 and 6 are set to 0 and the command
is terminated.
The DDFDC reads the ID field of each sector and checks the
CRC bytes. If the DDFDC detects a read error (incorrect CRC)
in one of the ID fields, it terminates the Write Data command,
sets the DE flag in ST1 to a 1, and sets bits 7 and 6 in STO to
and I, respectively.
o
The Write Data command operates in much the same manner
as the Read Data command. Refer to the Read Data command
for the handling of the following items:
Result Phase:
R
1
Status Register 0 (STO)
2
Status Register 1 (ST1)
3
Status. Register 2 (ST2)
4
Track Number (T)
5
Head Number (H)
6
Sector Number (R)
7
Number of Data Bytes
•
•
•
•
•
p~r
Transfer Capacity
End of Track (EN) flag
No Data (ND) flag
Head Unload Time (HUT) interval
ID information when the processor terminates command
(see Table 4)
• Definition of Data Length (DTL) when N = 0 and when N
0
*
Sector (N)
Table 4.
DDFDC Command Termination Values
Command Phase 10
Multi·
Track
(MT)
0
1
Result Phase 10
Head
Number
(HO)
Final Sector Transferred
to/from Data Bus
Track
Number
(T)
Head
Number
(H)
Sector
Number
(R)
No. of
Data Bytes
(N)
0
0
Less than EDT
NC
NC
R+ 1
NC
Equal to EDT
T + 1
NC
01
NC
1
Less than EDT
NC
NC
R+ 1
NC
1
Equal to EDT
T + 1
NC
01
NC
a
Less than EDT
NC
NC
R+ 1
NC
0
Equal to EDT
NC
LSB
01
NC
1
Less than EDT
NC
NC
R + 1
NC
1
Equal to EDT
T + 1
LSB
01
NC
Notes:
1. NC (No Change): The same value as the one at the beginning of command execution.
2. LSB (Least Significant Bit): The least significant bit of H is complemented.
1-67
Double-Density Floppy Disk Controller (DDFDC)
R68465
Result Phase:
In the Write Data mode, data transfers from the data bus to the
DDFDC must occur within 27 P.s in the FM mode, and within
13 p.S in th.e MFM mode. If the time interval between data
transfers is longer than this, then the DDFDC terminates the
Write Data command, sets the Over Run (OR) flag in STI to a
1, and sets bits 7 and 6 in STO to 0 and 1, respectively.
Command Phase:
BYTE
7
RIW
W
6
5
4
3
2
1
R
Status Register' (ST')
3
Status Register 2 (ST2)
4
Track Number (T)
Head Number (H)
0
6
Sector Number (R)
7
Number of Data Bytes per Sector(N)
I
MT
MF
a
a
0
I
a
I
2
X
X
X
X
X
HD
USI
usa
3
Track Number (T)
READ DELETED DATA
4
Head Number (H)
5
Sector Number (R)
6
Number of Data Bytes per Sector (N)
The Read Deleted Data command is the same as the Read Data
command except that if SK = 0 when the DDFDC detects a Data
Address Mark at the beginning of a Data field, it reads all the
data in the sector and sets the CM flag in ST2 to aI, and then
terminates the command. If SK = 1, then the DDFDC skips the
sector with the Data Address Mark and reads the next sector.
7
End of Track (EOT)
8
Gap length (GPl)
9
Data length (DTl)
Command Phase:
RIW
BYTE
7
W
,
Status Register a (STO)
2
Status Register I (STf)
3
Status Register 2 (ST2)
4
Track Number (T)
5
Head Number (H)
6
7
Sector Number (R)
Number of Data Bytes per Sector (N)
R
The Write Deleted Data command is the same as the Write Data
command except a Deleted Data Address Mark is written at the
beginning of the Data field instead of the normal Data Address
Mark.
Command Phase:
RIW
BYTE
7
I
,
6
5
4
MT
MF
SK
0
, ,
2
X
X
X
X
X
3
Track Number (T)
3
2
HD
1
0
US,
usa
4
Head Number (H)
5
Sector Number (R)
6
Number of Data Bytes per Sector (N)
7
End of Track (EOT)
8
Gap length (GPL)
9
Data Length (DTl)
0
a
Result Phase:
WRITE DELETED DATA
W
Status Register a (STO)
5
Result Phase:
R
I
2
6
5
4
1
MF
0
0
,
2
MT
0
a
,
X
X
X
X
HD
US,
usa
3
0
,
Status Register a (STO)
2
Status Register' (STI)
3
Status Register 2 (ST2)
4
Track Number (T)
5
Head Number (H)
6
Sector Number (R)
7
Number of Data Bytes per Sector (N)
2
X
3
Track Number (T)
READ A TRACK
4
Head Number (H)
The Read a Track command is similar to the Read Data command except that this is a continuous read operation where all
Data fields from each of the sectors on a track are read and
transferred to the data bus. Immediately after encountering the
Index Hole, the DDFDC starts reading the Data fields as continuous blocks of data. This command terminates when the
number of sectors read is equal to EOT. Multi-track operations
are not allowed with this command.
5
Sector Number (R)
6
Number of Data Bytes per Sector (N)
7
End of Track (EOT)
8
Gap length (GPl)
9
Data length (DTl)
1-68
Double-Density· Floppy Disk Controller (DDFDC)
R68465
Command Phase:
If the DDFDC finds an error in the ID or Data CRC check bytes,
it continues to read data from the track. The DDFDC compares
the ID information read from each sector with the value stored
in the IDR, and sets the ND flag in ST1 to a 1 if there is no match.
If the DDFDC does not find an ID Address Mark on the disk after
it encounters the Index Hole for the second time it terminates
the command, sets the Missing Address Mark (MA) flag in ST1
to a 1, and sets bits 7 and 6 of STO to 0 and 1, respectively.
RJW
BYTE
7
6
5
4
3
2
1
W
1
0
MF
0
0
1
0
1
0
2
X
X
X
X X
HD
US1
usa
Result Phase:
R
Command Phase:
1
Status Register 0 (STO)
2
Status Register 1 (STt)
3
Status Register 2 (ST2)
4
Track Number (T)
5
Head Number (H)
RJW
BYTE
7
6
5
4
3
2
1
0
6
Sector Number (R) .
W
1
0
MF
SK
0
0
0
1
0
7
Number of Data Bytes per Sector (N)
2
X
X
X
US1
usa
3
Track Number (T)
4
Head Number (H)
X X HD
5
Sector Number (R)
6
Number of Data Bytes per Sector (N)
7
End of Track (EOT)
8
Gap Length (GPL)
9
Data Length (DTL)
FORMAT A TRACK
The six-byte Format a Track command formats an entire track.
After the Index Hole is detected, data is written on the disk: Gaps,
Address Marks, ID fields and Data fields; all are recorded in
either the double-density IBM System 34 format (MF = 1) or
the single-density IBM 3740 format (MF = 0). The particular format written is also controlled by the .values of Number of
Bytes/Sector (N), Sectors/Track (ST), Gap Length (GPL) and
Data Pattern (D) which are supplied by the processor during the
command phase. The Data field is filled with the data pattern
stored in D.
The ID field for each sector is supplied by the processor in
response to four data requests per sector issued by the DDFDC.
The type of data request depends upon the Non-DMA flag (ND)
in the Specify command. In the DMA mode (ND= 0), the
DDFDC asserts the DMA Request (DRQ) output four times per
sector. In the Non-DMA mode (ND = 1), the DOFDC asserts
Interrupt Request (IRQ) output four times per sector.
Result Phase:
R
1
Status Register 0 (STO)
2
Status Register 1 (STt)
3
Status Register 2 (ST2)
4
Track Number (T)
5
Head Number (H)
6
Sector Number (R)
7
Number of Data Bytes per Sector (N)
0
The processClr must write one data byte in response to each
request, sending (in the consecutive order) the Track Number
(T), Head Number (H), Sector Number (R) and Number of Bytes!
Sector (N). This allows the disk to be formatted with nonsequential sector numbers, if deSired.
The processor must send new values for T, H, R, and N to the
DDFDC for each sector on the track. For sequential fClrmatting
R is incremented by one after each sector is formatted, thus,
R contains the tCltal numbers of sectors formatted when it is read
during the result phase. This incrementing and formatting continues for the whole track until the DDFDC, upon encountering
the Index Hole for the second time, terminates the command
and sets bits 7 and 6 in STO to O.
READ 10
The two-byte Read ID command returns the present position of
the read/write head. The DDFDC obtains the value from the first
ID field it is able to read, sets bits 7 and 6 in STO to 0 and terminates the command.
If no proper ID Address Mark is found on the disk before the
Index Hole is encountered for the second time then the Missing
Address Mark (MA) flag in ST1 is set to a 1 ,and if no data is
found then the ND flag to a 1 is also set in ST1. Bits 7 and 6
in STO are set to 0 and 1, respectively and the command is
terminated.
If the Fault (FLT) signal is high from the FDD at the end of a
write operation, the DDFDC sets the Equipment Check (EC) flag
in STO to a 1, sets bits 7 and 6 of STO to 0 and 1, respectively,
and terminates the command. Also, a low (RDY) signal ai the
beginning of a command execution phase causes bits 7 and 6
of STO to be set to 0 and 1, respectively.
During this command there is no data transfer between DDFDC
and the data bus except during the result phase.
Table 5 shows the relationship between N, ST, and GPL for
various disk and sector sizes.
1-69
D
R68465
Double-Density Floppy Disk Controller (DDFOC)
Table 5., Standard Floppy Disk Sector Size Relationship
Disk
Size
Sector Size
BytesJSectar
Made
No. of
SectarslTracks
(ST)
00
01
02
03
lA
OF
08
04
02
01
128
256
512
1024
2048
4096
FM
8"
MFM3
FM
5'4"
MFM3
.
No. of Data
Bytes/Sector
(N)
04
05
lA
OF
Oap Length (OPL)·
ReadlWrlte
Cammand1
Format
Cammaitd2
07
OE
lB
47
C8
C8
lB
2A
3A
8A
FFFF
IBM Disk 1
IBM Disk 2
OE
lB
35
99
C8
36
IBM Disk 20
256
512
1024
2048
4096
8,9:2
01
O?
03
128
128
256
512
1024
2048
00
00
04
46
03
04
02
01
C8
C8
256
256
512
1024
2048
4096
01
01
02
03
04
05
12
10
08
04
02
01
OA
20
08
04
04
05
06
01
02
02
01
C8
12
10
08
07
10
18
2A
80
C8
C8
54
74
FF
FF
FF
Remarks
IBM Disk 20
09
19
30
87
FF
FF
OC
32
50
FO
FF
FF
Nates:
1. Suggested values 01 GPL in Read or Write commands to, avoid overlapping between Data field and 10 field of contiguous sections.
2. Suggested values of GPl in Format a Track command.
3. In, MFM mode the DDFDC cannot perform, a read/write/format operation with 128 bytes/sector (N = 00).
4. Values of ST and GPl are in hexadecimal.
Command Phase:
SCAN COMMANDS
RIW
BYTE
7
6
5
4
3
2
1
0
W
1
0
MF
0
0
1
1
0
1
2
X
X
X
X
X
HD
USI'
USO
3
Number of Bytes per Sector (N)
4
Sectors per Track (ST)
5
Gap Length (GPl)
6
Data Pattern (D)
Result Phase'
R
1
Status Register 0 (STO)
2
Status Register 1 (Sn)
3
Status Register 2 (ST2)
4
Track Number (T).
5
Head Number (H)·
6
Sector 'Number (R)·
7
Number of Data Bytes per Sector (N)·
.,
The scan commands compare data read from the disk to data
supplied from the data bus. The DDFDC compares the data, and
looks for a sector of data which meets the conditions of
DFDD = Deus, 0FDD s Deus, or DFDD ;z: Deus (0 = the data
pattern in hexadecimal). A magnitude comparison is performed
(FF = largest number. 00 = smaliest number). The hexadecimal byte of FF either from the bus or from FDD can be
used as a mask byte because it always meets the condition of
the compare. After a whole sector of data is compared, if the
conditions are not met. the sector number is incremented
(R + STP - R), and the scan operation is continued, The scan
operation continues until one of the following events occur: the
conditions for scan are met (equal, low or equal, or high or equal).
the last sector on the track is reached (EOT), or DONE is
received.
,0tf conditions for scan are met. the ODFDC sets the Scan Hit (SH)
flag in ST2 to aI, and terminates the command. " the conditions for scan are not m,et between the starting sector (as
specified by R) and the last sector on the track (EOT). then the
DDFDC sets the Scan Not Satisfied (SN) flag in ST2 to aI, and
terminates the command. The receipt of DONE from the processor or DMA controller during the scan operation will cause the
DDFDC to complete the comparison of the particular byte which
is in process. and then to terminate the command. Table 6 shows
the status of bits SH and SN under various conditions of scan.
• The 10 information has no meaning in this command.
1-70
Double-Density Floppy Disk Controller (DDFOC)
R68465
Table 6.
Scan Status Codes
Status Register 2
Command
Blt2=SN
Bit 3 = SH
a
1
DFDD
DFDD
*
Deus
Deus
1
DFDD
DFDD
DFDD
<
>
Deus
Deus
Deus
DFDD
DFDD
DFDD
>
<
Deus
Deus
Deus
Scan Equal
a
a
o
a
a
Scan Low or Equal
1
a
1
a
Scan High or Equal
Comments
o
a
Result Phase:
If SK = 0 and the DDFDC encounters a Deleted Data Address
Mark on one of the sectors, it regards that sector as the last sector of the track, sets the Control Mark (eM) bit in ST2 to a 1 and
terminates the command. If SK = 1, the DDFDC skips the sector with the Deleted Data Address Mark, sets the CM flag to a
1 in order to show that a Deleted Sector has been encountered,
and reads the next sector.
R
When either the STP sectors are read (contiguous sectors = 01,
or alternate sectors = 02) or MT (Multi-Track) is set, the last
sector on the track must be read. For example, if STP = 02,
MT = 0, the sectors are numbered sequentially 1 through 26,
and the scan command starts reading at sector 21. Sectors 21,
23, and 25 are read, then the next sector (26) is skipped and
the Index Hole is encountered before the EDT value of 26 can
be read. This results in an abnormal termination of the command.
If the EDT had been set at 25 or the scanning started at sector
20, then the scan command would be completed in a normal
manner.
a (STO)
1
Status Register
2
Status Register 1 (ST1)
3
Status Register 2 (ST2)
4
Track Number (T)
5
Head Number (H)
6
Sector Number (R)
7
Number of Data Bytes per Sector (N)
SCAN LOW OR EQUAL
Command Phase:
During a scan command data is supplied from the data bus for
comparison against the data read from the disk. In order to avoid
having the Over Run (OR) flag set in ST1 , data must be available
from the data bus in less than 27 P.s (FM mode) or 13 P.s (MFM
mode). If an OR occurs, the DDFDC terminates the command
and sets bits 7 and 6 of STO to 0 and 1, respectively.
RIW
BYTE
7
6
5
4
3
2
1
W
1
MT
MF
SK
1
1
a
a
1
2
X
X
X
X
X
HD
USl
usa
3
Track Number (T)
4
Head Number (H)
5
Sec;tor Number (R)
The following tables specify the command bytes and describe
the result bytes for the three scan commands.
6
Number of Data Bytes per Sector (N)
7
End of Track (EOT)
SCAN EQUAL
8
Gap Length (GPL)
9
Sector Test Process (STP)
Command Phase'
RIW
BYTE
7
6
5
4
3
2
1
W
1
MT
MF
SK
1
a a
0
1
2
X
X
X
X
X
USl
usa
3
Track Number (T)
1
Status Register a (STa)
4
Head Number (H)
2
Status Register. 1 (STl)
5
Sector Number (R)
3
Status Register 2 (ST2)
6
Number of Data Bytes per Sector (N)
4
Track Number (T)
Head Number (H)
HD
0
Result Phase:
R
7
End of Track (EOT)
5
8
Gap Length (GPL)
6
Sector Number (R)
9
Sector Test Process (STP)
7
Number of Data Bytes per Sector (N)
1-71
0
Double-Density Floppy Disk Controller (DDFDC)
R68465
SCAN HIGH OR EQUAL
Command Phase:
RfW
BYTE 7
W
6
5
4
3
2
1
1
MT
MF
SK
1
1
1
0
1
2
X
X
X
X
X
HD
US1
usa
3
Track Number (T)
4
Head Number (H)
5
Sector Number (R)
6
Number of Data Bytes per Sector (N)
7
End of Track (EOT)
8
Gap Length (GPL)
9
Sector Test Process (STP)
During the command phase of the Seek operation the DDFDC
sets the Controller Busy (CB) flag in the MSR to 1; but during
the execution phase the CB flag is set to 0 to indicate DDFDC
non-busy. While the DDFDG is in the non-l;lUsy state, another
Seek command may be issued, and in this manner parallel seek
operations may be performed on all drives at once.
0
No command other than Seek will be accepted while the DDFDC
is sending step pulses to any FDD. If a different command type
is attempted, the DDFDC will set bits 7 and 6 in STO to a 1 and
0, respectively, to indicate an invalid command.
If the FDD is in a not ready state at the beginning of the command execution phase or during the seek operation, then the
DDFDC sets the Not Ready (NR) flag in STO to a 1, sets STO
bits 7 and 6 to 0 and 1, respectively, and terminates the
commancf·
ResUlt Phase:
R
1
Status Register 0 (STO)
2
Status Aegister 1 (ST1)
3
Status Aegister 2 (ST2)
4
Track Number (T)
5
Head Number (H)
6
Sector Number (A)
7
Number of Data Bytes per Sector (N)
If the time to write the three bytes of the Seek command exceeds 150 p,s, the time between the first two step pulses may
be shorter than the Step Rate Time (SRT) defined by the Specify
command by as much as 1 ms.
Command Phase:
'RfW
BYTE
7
W
6
5
4
3
2
1
1
0
0
0
0
1
1
1
1
2
X
X
X
X
X
0
US1
usa
3
New Track Number (NTN)
0
SEEK
The three-byte Seek command steps the FDD read/write head
from track to track. The DDFDC has two independent Present
Track Registers for each drive. They are cleared only by the
Recalibrate command. The DDFDC compares the Present Track
Number (PTN) which is the current head position with the New
Track Number (NTN), and if there is a difference, performs the
following operation:
Result Phase: None.
RECALIBRATE
This two-byte command retracts the FDD read/write head to the
Track 0 position. The DDfDC clears the contents of the PTN
counters, and checks the status of the Track 0 signal from the
FDD. As long as the Track 0 signal (TRKO) is low, the direction
signal (LCTIDIR) output remains low and step pulses are issued
on FR/STP. When TRKO goes high the DDFDC sets the Seek
End (SE) flag in STO to a 1 and terminates the command. If the
TRKO is still low after 256 step pulses have been issued, the
DDFDC sets Seek End (SE) and Equipment Check (EG) flags
in STO to 1s, sets bits 7 and 6 of STO to 0 and 1, respectively,
and terminates the command.
If PTN < NTN: Sets the direction output (LCT/DIR) high
and issues step pulses (FR/STP) to the
FDD to cause the read/write head to step
in.
If PTN
> NTN: Sets the direction output (LCTIDIR) low
and issues step pulses to the FDD to
cause the read/write head to step out.
The rate at which step pulses are issued is controlled by the
Step Rate Time (SRT) in the Specify command. After each step
pulse is issued, NTN is compared against PTN. When
NTN = PTN, then the Seek End (SE) flag in STO is set to aI,
bits 7 and 6 in STO are set to 0, and the command is terminated.
At this pOint DDFDC asserts IRQ.
The ability to do overlap Recalibrate commands to multiple FDDs
and the loss of the RDY Signal, as described in the Seek command, also applies to the Recalibrate command.
Command Phase:
BYTE 7
RfW
The FDD Busy flag (bit 0-3) in the Main Status Register (MSR)
corresponding to the FDD performing the Seek operation is set
to a 1.
W
After command termination, all FDD Busy bits set are cleared
by the Sense Interrupt Status command.
6
5
4
3
2
1
1
0
0
0
0
0
1
1
1
2
X
X
X
X
X
0
US1
usa
Result Phase: None,
1-72
0
Double.-Density Floppy Disk Controller (DDFDC)
R68465
SENSE INTERRUPT STATUS
SPECIFY
Interrupt request (IRQ) is asserted by the DDFDC when any of
the following conditions occur:
.
The, three-byte s,peci/Y command sets the initial ,values for each
of the three internal timers. The Head Unload Time (HUl) defines
the time from the end of the execution phase of one of the
read/write commands to the head unload state. This timer is
programmable from 16 to 240 ms in increments of 16 ms
(1 = 16 ms. 2 = 32 mS, ... F = 240 ms).
1. Upon entering the result phase of:
a. Read Data command
b. Read a Track command
c. Read 10 command
d. Read Deleted Data command
e. Write Data command
f. Format a Track command
g. Write Deleted Data command
h. Scan commands
2. Ready (ROY) line from the FDD changes state
3. Seek or Recalibrate command termination
4. During execution phase in the Non-DMA mode
The Step Rate Time (SRl) defines the time interval between
adjacent step pulses. This timer is programmable from 1 to
16 ms in increments of 1 ms (F = 1 ms, E = 2 ms, 0 = 3 ms, ...
o = 16 ms).
The Head Load Time (Hll) defines the time between the Head
Load (HDL) Signal' going high and the start of the read/write
operation. This timer is programmable from 2 to 254 ms in
increments of 2 ms (01 = 2 ms, 02 = 4 ms, 03 = 6· ms, ...
7f = 254 ms).
IRQ caused by reasons 1 and 4 above occur during normal
command operations and are easily discernible by the processor.
During an execution phase in Non-DMA mode, bit 5 in the MSR
is set to 1. Upon entering result phase this bit is set to O.
Reasons 1 and 4 do not require the Sense Interrupt Status command. The interrupt is cleared by reading or writing data to
DDFDC. Interrupts caused by reasons 2 and 3 are identified with
the aid of the Sense Interrupt Status command. This command
resets I RQ and sets/resets bits 5, 6, and 7 of STO to identify the
cause of the interrupt. Table 7 definas the seek and interrupt
codes.
The time intervals are a direct function of the clock (elK on
pin 19). Times indicated above are for an 8 MHz clock. If the
clock is reduced to 4 MHz (mini-floppy application) then all time
intervals are increased by a factor of two.
The choice of DMA or Non-DMA operation is made by the NonDMA mode (NO) bit. When this bit = 1 the Non-DMA mode is
0 the DMA mode is selected.
selected, and when NO
=
Neither the Seek or Recalibrate command has a result phase.
Therefore, it is mandatory to use the Sense Interrupt Status command after these commands to effectively terminate them and
to verify where the head is positioned by checking the Present
'
Track Number (PTN).
Command Phase:
RIW
BYTE
W
1
Issuing a Sense Interrupt Status command without an interrupt
pending is treated as an invalid command.
SRT HUT HLT NO -
Command Phase:
RIW
w
BYTE
7
J6 I5
14
3
1
o 1 0 1 0 10 01
2
SRT
3
HLT
2
0
1
1
1
1
1
1
0
1
HUT
1 NO
Step Rate Time
Head Unload Time
Head Load Time
Non-OMA mode
Result Phase: None.
SENSE DRIVE STATUS
Result Phase:
This two-byte command obtains and reports the status of the
FDDs. Status Register 3 (ST3) is returned in the result phase
and contains the drive status.
Status Register 0 (STO)
Present Track Number (PTN)
Table 7.
STO Seek and Interrupt Code Definition for Sense Interrupt Status
Status Register 0 (STO) Bits
Interrupt Code (IC)
Seek End (SE)
Cause
7
6
5
1
1
0
0
0
1
Normal termination of Seek or Recalibrate command
0
1
1
Abnormal termination of Seek or Recalibrate command
RDY line changed state, either. polarity
1-73
0
Double-Density Floppy Disk Controller (DDFDC)
R68465
Command Phase:
RIW
BYTE
W
7
6
5
4.
2
3
1
Bytes must be read to successfully complete the Read Data command. The DDFDC.will not accept a new command until al.1
seven bYtes have been read. Other commands may require
fewer bytes to be read during the result phase.
0
1
0
0
0
0
0
1
0
0
2
X
X
X
X
X
HD
' US1
usa
INTERRUPT REQUEST MODE
Result Phase:
I
R
I
During the execution phase, the MSR need not be read. The
receipt of each data byte from the FDD is indicated by IRQ low
on pin 18. When the DDFDC is in Non-DMA mode, IRQ is
asserted during .the execution phase. When the DDFDC is in
the DMA mode, IRQ is asserted at the result phase. The IRQ
signal is reset by a read (RIW high) or write (RIW low) of data
to the DDFDC. A further explanation of the IRQ signal is
described in the Sense'lnterrupt Status command on page 16.
If the system cannot handle interrupts fast enough (within 13 p.S
for MFM mode or 27 p.S for FM mode), it should poll bit 7 (RQM)
in the MSR. In this case, RQM in the MSR functions as an Interrupt Request (IRQ). If the RQM bit is not set, the Over Run (OR)
flag in ST1 will be set to a 1 and bits 7 and 6 of STO will be set
to a 0 and 1, respectively.
Status Register 3 (ST3)
INVALID COMMAND
If an invalid command (i.e., a command not previously defined)
is received by the DDFDC, then the DDFDC terminates the command after setting bits 7 and 6 of STO to 1 and 0, respectively.
The DDFDC does not generate an interrupt during this condition. Bits 6 and 7 (DIO and RQM) in the MSR are both set to
a 1 indicating to the processor that the DDFDC is in the result
phase and that sro must be read. A hex 80 in STO indicates
an invalid command was receil(ed.
DMAMODE
When the DDFDC is in the DMA mode (ND = 0 in the third command byte ottheSpecify command), DRQ (DMARequElst)is
assert~ during the execution phase (rather than IRQ) to request
the transfer of a data byte between the data bus and thE! DDFDC.
A Sense Interrupt Status command m.ust.be sent after a Seek
or Recalibrate interrupt, otherwise the DDFDC considers the next
command to be an invalid command.
In some applicatitms'the user may wish to use this command
as a llio-op command, to place the DDFDC in Ii standby or no
operation state.
Command Phase:
7 IB~TE 17
6
I5
During a read command, the DDFDC asserts REQ as each byte
of data is avail&Qle to be read. The DMA controller responds
to this request with both DACK low CDMA Acknowledge) and RiW
high (read). When DACK goes low the DMA Reqllest is reset
(REQ high). After the execution phase has been completed
DONE low or the EOT sector is read), IRQ is asserted to indicate
the beginning of the result phase. When the first byte of data
is read during the result phase, IRQ is reset high.
o
Invalid Codes
Result Phase:
R
Status Register 0 (STO) ..
During a write command, the DDFDC asserts REQ as each byte
of data is required. The DMA controller responds to this request
with DACK low (DMA Acknowledge) and RIW low (write). When
DACK goes low the DMA Request is reset (REQ high). After the
execution phase has been completed (DONE low or the EOT
sector is written), IRQ is asserted. This signals the beginning of
the result phase. When the first byte of data is read during the
result phase, the IRQ is reset high.
aD
PROCESSOR INTERFACE
During the command or result phases, the Main Status Register
(MSR) must be read by the Pfocessor before each byte of information is transferred to, or from, the DDFDC.Data Register. After
each byte of data is written to, or read from, the Data Register,
the processor should wait 12 P.s before reading the MSA. Bits
6 and 7 in the MSR must be a 0 and 1, respectively, before each
command byte can be written to the DDFDC. During the result
phase, bits 6 and 7 of the MSRmust both be 1sprior to reading
each byte from the Data Register onto the data bus. Note that
this status reading of bits 6 and 7 of the MSR before each byte
transfer to and from the DDFDC is required in only the command
and result phases and not during the execution phase.
FDD POLLING
After the Specify command has been received by the DDFDC,
the Unit Select lines (USO and US1) begin the polling mode.
Between commands (and between step pulses in the Seek Command) the DDFDC polls all the FDD's looking for a change in
the RDY line from any of the drIves. If the RDY line changes
state (usually due to the door opef]ing or closing) then the
DDFDC asserts IRQ. When Status Register 0 (STO) is read (after
Sense Interrupt Status command is issued), Not Ready (NR = 1)
will be indicated. The pOlling of the RDY line by the DDFDC
occurs continuously between commands, thus notifying the processor which drives are on- or off-line. Each drive is polled every
1.024 ms except during readlwrite' commands.
During the result phase all bytes shown in the result phase must
be read by the processor. The Read Data command, for
example, has seven bytes of data in the result phase: All seven
1-74
Double~Denslty Floppy Disk Controller
(DDFDC)
.
R68465
DATAIN/OUT
(DIO)
(MSR BIT 6)
REQUEST
FOR MASTER
(RQM)
(MSR BIT 7)
CHIP SELECT (CS)
READIWRITE
(RIW)
FROM DDFDC TO DATA BUS
FROM DATA BUS TO DDFDC
L
II
I 1
1
I
I
I
1READY 1
L
I,--------+---.
il..J
I
LJ
1
I
I
1
I
I
I
I
A
I B
I
1
I
I
I
J-----!:--,u
I
I I I
I 1
I
.1 I
A
IBI A
I
1I
I
C
1 I
I
I
D
NOTES
o
DATA REGISTER READY TO BE WRITTEN INTO
[!] DATA REGISTER NOT READY TO BE WRITTEN INTO
Figure 3.
[£] DATA REGISTER READY FOR NEXT DATA BYTE TO BE READ
~ DATA REGISTER NOT READY FOR NEXT DATA BYTE TO BE READ
DDFDC and System Data Transfer Timing
1-75
D
:0
CJ)
Q)
01:00
CJ)
U'I
Al·A23
ADDRESS BUS
00-015
DATA BUS
R/W
>-
LOS'
UD'
C-
AS
DTACK
C
BGACK
~! ~I
R68000
MPU
~
-
BR
8G
~I ~I
c
n~
~I
~
~I
'lll
!I ~I
~{>-
~~'
~s
~!
~I ~I
r~
r-
II
~
~
":
1:
~I ~l
~I
~
'-;
~
'l
~
":
:><
~I
~~
~ ~
~
BUS
":
[:l
--
c0
~I
ROW
MFM
REO
VCO
ROD
~
MEMORY
DAcK
68440DMAC
PSO
PS'
WOA
DONE
w-.---;=L
FC'
FC2
A1
lACK
"~
i
n
~
FLTITRKO
~I
R68465
'PA
~~
r---
lPL1
lPl2
RMUX
I
LS
WRITE
CLOCK
GEN
I
LeT/ClR
weK
E
WRITE DATA
WRITE PROTECT
TWO·SIDE
FAULT
r----~ FAULT RESET
FA/STP
iRa
--
READ DATA
TRACK 0
DDFoe
LS
138
IPLO
DATA
RECOVERY
WP{TS
A2
A3
~
R'WISEEK
MUX
~
~f----
STEP
LOW CURRENT
DIRECTION
ROY
READY
WE
iRa
lOX
'40
HOL
WRITE ENABLE
INDEX
HEAD LOAD
HOSEL
'----
L
1
2
8 MHz
~
USO
eLK
RESET
...
us,
HEAD SELECT
UNIT SELECT Q
UNIT SElECT 1
c
2:
CD
C•
CD
~
fb
;:::;:
'<
!!
0
't:J
~
C
...
0
C;;"
-..
0
~
2-
Signal not used in interface to 68008 MPU.
UOS changed to OS when interfaced to 68008 MPU.
CD
C
C
Figure 4.
R68465 DDFDe Interface to R68000
"0C
-
Double-Density Floppy Disk Controller (DOFOC)
R68465
eLK
-.J'
/
Figure 5.
Clock Timing
RS
DATA OUT
(Do-D7)
Figure 6.
DDFDC Read Cycle Timing
Figure 7.
DDFDC Write Cycle Timing
RS
DATA IN
(Do-D7)
1-77
Double-Density Floppy Disk Controller (DDFDC)
R68465
TXRQ
---i
1-l@
DACK
f
DONE
Figure 8.
@
t-
- ..
/
--
{
DMA Operation Timing
WRITE CLOCK
(WCK)
23
WRITE ENABLE
(WE)
PRESHIFT 0 OR 1
(PSO, PS1)
WRITE DATA
(WDA)
Figure 9.
FDD Write Operation Timing
READ DATA
(ROD)
READ DATA WINDOW
(ROW)
-------""~------_Jl~-
NOTE:
EITHER POLARITY DATA WINDOW IS VALID
Figure 10.
FDD Read Operation Timing
1-78
Double-Density Floppy Disk Controller (DDFDC)
R68465
... ~ ~-,---------~
'------
SEEK
(RW/sEEK)
DIRECTION
(LCT/DIR)
STEP
(FRlSTP) _ _ _ _ _ _.JI
I---@-----I
Figure 11. Seek Operation Timing
M
INDEX
(lOX)
FAULT RESET
(FR) _ _ _• ~~ ._,_ __
Figure 13.
Figure 12. Fault Reset Timing
Index Timing
-tF
47 '
RESET
(RST)
Figure 14. T.rminal Count Timing
INPUT/OUT
FigUre 15. Reset Timing
CLOCK
TEST POINT
/I
.'
2.4V~2.0V'jiOVV"'-0.45V---f\0.8V
"
TEST POINT
'
"
3.0V~"'2-.4V-7"';'""2-.4""'V~
0.8v/~
'
O.3V - - ' \ 0 . 6 5 V 0.65V"----
INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" AND 0.45 V FOR
A LOGIC "0:' TIMING ME;ASUREMENTS ARE MADE AT 2.0V FOR
A LOGIC "1" AND 0.8V FOR A LOGIC "0:'
Figure 16.
,
CLOCKS ARE DRIVEN AT 3.OV FOR A LOGIC "1" AND 0.3V FOR A
LOGIC "0:' TIMING MEASUREMENTS ARE MADE AT 2.4V FOR A
LOGIC "1" AND 0.65V FOR A LOGIC "0:'
AC Timing Measurement Conditions
1-79
Double-Density Floppy Disk Controller (DDFDC)
R68465
AC CHARACTERISTICS
01cc = 5.0 Vdc ±5%, Vss = 0 Vdc, TA
Ref.
Fig.
7
8
9
10
11
70·C)
Symbol
Alt. Sym.
Typ.
Max.
Unit
1
Clock Period
lev
ev
120
125
500
ns
2
Clock High, low Widlh
lCA
<1>0
40
62.5
-
ns
3
Clock Rise Time
ICLCH
<1>,
20
ns
4
Clock Fall Time
ICHCL
f
-
5
CS High 10 RIW High
ISR
40
-
6
Address Valid 10 CS Low
IRA
0
-
7
CS High 10 Address Invalid
ISHAX
IAH
0
-
8
CS High
ISHSL
ISH
150
-
9
DTACK Low 10 Data Valid
tOLDV
tRO
-
-
10
CS High 10 OUlput High Z
tSHOZ
IOF
20
11
CS High 10 DTACK High
tSHOH
IDTK
-
12
Address Valid to RIW Low.
IAVRL
tws
20
13
RIW Low to CS Low
IRLSL
tWH
80
14
CS Low Pulse Width
tSLSH
tSL
250
15
Data Valid to CS High
IOVSH
tosu
150
16
CS High 10 Data Invalid
tSHOZ
IOHW
5
17
IRQ Delay from CS High
IILSH
tlRQ
18
TXRQ Cycle Period
ITQev
tTCY
19
ACK Low to TXRQ Low
tAKTH
tACK
-
20
DONE Low Width
tNLNH
tOONE
21
WCK Cycle Time
IKCY
tev
13
1
-
22
WCK High Widlh
tKHKL
10
WCK Rise Time
tKLKH
t,
-
80
24
WCK Fall Time
tKHKL
If
-
25
WCK High to PSO, PSl Valid (Delay)
20
PSO, PSl Valid to WDA High (Delay)
tKHPV
IpvOH
Icp
26
Ico
20
27
WDA High Width
IOHOL
Iwoo
tEHKH
t WCY
twcH -50
28
WE High to WCK High or WE Low 10 WCK low
30
ROW Cycle Time
tWE
20
Iwev
I WRO
-
31
ROW Valid to ROD High (Setup)
32
ROD Low to ROW Invalid (Hold)
tWVRH
I RLWI
tROW
15
33
ROD High Width
tRHRL
tROO
40
35
USO, USl Valid to SEEK High (Setup)
tUVSH
tus
12
36
SEEK Low to USO. USl Invalid (Hold)
ISLUI
tsu
15
37
SEEK High to OIR Valid (Setup)
tso
7
38
OIR Invalid 10 SEEK Low (Hold)
tsHov
t OXSL
tos
30
39
OIR Valid to STP High (Selup)
tOVTH
tOST
1
40
STP Low to DIR Invalid (Hold)
tTLOX
ISTO
24
41
STP Low 10 USC, USl Invalid (Hold)
ITLUX
tSTu
5
42
STP High Widlh
ITHTL
ISTp ·
43
STP Cycle Time
tTCY
tsc
333
10
12
44
FR High Width
tFHFL
45
lOX High Width
tlHIL
tFA
t lOX
14
46
DONE Low Width
tTHTL
tlC
15
47
RESET Low Width
tRHRL
IRST
Notes:
MFM
Mini
Standard
0
4"s
2pS
1
2 P.s
ljLS
1
14
ns
90
ns
-
ns
120
ns
500
pS
ns
lev
ns
100
ns
-
7
-
-
ns
-
ns
100
ns
-
ns
ClK
=
8 MHz
P.s
ns
ns
ItS
P.s
p.S
ItS
-
,..s
-
,..s
,..S
-
ItS
note 3
Its
10
8 MHz
ns
100
-
=
ns
ns
-
ClK
ItS
20
-
100 pF
ns
20
-
=
ns
350
-
CL
ns
-
-
8 MHz
ns
200
-
=
ns
-
ClK
ns
-
-
Test
Conditions
ns
250
6
8
ns
ns
-
note 2
15
20
-
-
note 1
23
13
1.
Min.
ISHRH
I AVSL
6
and
to
Characteristic
No.
5
O·C
"s
tev
lev
tCY
2. For MFM = 0: Typ. = 2 P.s
For MFM = 1: Typ. = 1 jLS
3. tsc = 33 "s min. is for different drive units. In Ihe case of the same unil,
tsc can be ranged from 1 ms to 16 ms with 8 MHz clock period, and
2 ms to 32 ms with 4 MHz clock, under software control.
1·80
Double-Density Floppy Disk Controller (DDFDC)
A68465
ABSOLUTE MAXIMUM RATINGS *
Symbol
Value
Supply Voltage
Vee
-0.3 to +7.0
V
Input Voltage
VIN
-0.3 to +7.0
V
Output Voltage
VOUT
-0.3 to + 7.0
V
TA
Oto+70
C·
-55 to +150
C·
Parameter
Operating Temperature Range
Storage Temperature Range
TSTG
·NOTE: Stresses above those listed under ABSOLUTE MAXI·
MUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in other
sections of this document is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Unit
OPERATING CONDITIONS
Parametar
Renge
5.0V· ±5%
Vee Power Supply
Operating Temperature
O·C to 70·C
DC CHARACTERISTICS
(Vee = 5.0 Vdi: ±5%, Vss = 0 Vdc, TA = O"C to 7O"C, unless otherwise noted)
Parameter
Symbol
Input Low Voltage
Logic
ClK and WCK
VIL
Input High Voltage
Logie
ClK and WCK
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
Vee Supply Current
lee
Input Load Current
Min
Max
Unit
Test Conditions
V
-0.5
-0.5
0.8
0.65
2.0
2.4
Vee + 0.5
Vee + 0.5
V
2.4
0.45
V
Vee = 4.75V, 10L = 2.0 mA
Vee
V
Vee. 4.75V,loH = -200 pA
rnA
Vee = 4.75V
10
pA
VIN = Vee
-10
pA
VIN = OV
150
IlL
All Inputs
High I..svel Output Leakage Current
ILDH
10
pA
Vee = OV to 5.25V, Vss = OV
VOUT - Vee
Low I..svel Output Leakage Current
ILDL
-10
pA
Vee ~ OV to 5.25V, Vss = OV
VOUT = +O.45V
Internal Power Dissipation
PINT
1.0
W
TA = 25·C
-
CAPACITANCE
(TA .. 25OC; f.
= 1 MHz; Vee
= OV)
Parameter
Symbol
Max Limit
Unit
Clock Input
CIN(O)
20
pF
Input
C IN
10
pF
Output
COUT
20
pF
Note: All pins except pin under test tied to ground.
1-81
Doubte-Density Floppy Disk Controller (DDFDC)
R68465
PACKAGE DIMENSIONS
40-PIN CERAMIC DIP
DIM
[: D~ :]Jl
IJ.J
I_ _
A
B
C
D
F
G
H
.
J
~F II IIII IIIII I III
H
J':JLiii
f f
c
iy,rrctNJ~
SEATINGPLAN~~ L IJ
~~
iii iii iii
D
t
---1
K
K
L
M
N
MILLIMETERS
MIN
MAX
50.29 51.31
14.86 15.62
2.54
4.19
0.38 -0.53
0.76
1.40
2.54BSC
0.76
1.78
0.20
0.33
2.54
4.19
14.80 15.37
10·
o·
0.51
1.52
INCHES
MIN
MAX
1.980
0.585
0.100
0.015
0.030
0.100
0.030
0.008
0.100
0.575
o·
0.020
2.020
0.615
0.165
0.021
0.055
BSC
0.070
0.013
0:165
0.605
10·
0.060
M
40-PIN PLASTIC DIP
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
51.28 52.32 2.040 2.060
B
C
D.
F
G
H
J
K
L
M
N
1-82
13.72 14.22
3.55
5.08
0.36
0.51
1.02
1.52
2.54B8C
1.65
2.16
0.20
0.30
3.05
3.56
15.24B8C
7·
10·
0.51
1.02
0.540 0.560
0.140 0.200
0.014 0.020
0.040 0.060
0.100 BSC
0.065.1 0.085
0.0081 0.012
0.120 1 0,140
0.600 B8C
7· .1 10·
0,020.1 0.040
R68560 • R68561
'1'
Rockwell
R68560, R68561
MULTI-PROTOCOL COMMUNICATIONS
CONTROLLER (MPCC)
PRELIMINARY
DESCRIPTION
FEATURES
The R68560, R68561 Multi-Protocol Communications Controller
(MPCC) interfaces a single serial communications channel to
a 68008/68000 microcomputer-based system using either asynchronous or synchronous protocol. High speed bit rate, automatic formatting, low overhead programming, eight character
buffering, two channel DMA interface and three separate interrupt vector numbers optimize MPCC performance to take full
advantage of ~he 68008168000 processing capabilities and
asynchronous bus structure.
• Full duplex synchronous/asynchronous receiver and
transmitter
• Fully implements IBM Binary Synchronous Communications
(BSC) in two coding formats: ASCII and EBCDIC
• Supports other synchronous character-oriented protocols
(COP), such as six-bit BSC, X3.28, ISO IS1745, ECMA-16,
etc.
• Supports synChronous bit-oriented protocols (BOP), such as
SDLC, HDLC, X.25, etc.
• Asynchronous and is.ochronous modes
• Modem handshake interface
• High speed serial data rate (DC to 4 MHz)
• Internal oscillator and Baud Rate Generator (BRG) with programmable data rate
.
• Crystal or TTL level clock input and buffered clock output
(8 MHz)
• Direct interface to 68008/68000 asynchronous bus
• Eight-character receiver and transmitter buffer registers
• 22 directly addressable registers for flexible option selection,
complete status reporting, and data transfer
• Three separate programmable interrupt vector numbers for
receill'er, transmitter and serial interface
• Maskable interrupt conditions for receiver, transmitter and
serial interface
• Programmable microprocessor bus data transfer: polled,
interrupt and two-channel DMA transfer compatible with
MC68440/MC68450
• Clock control register for receiver clock divisor and receiver
and transmitter clock routing
• Selectable full/half duplex, autoecho and local loop-back
modes
• Selectable parity (enable, odd, even) and CRC (control field
enable, CRC-16, CCITT V.41" VRC/LRC)
In synchronous operation; the MPCC supports bit-oriented
protocols (BOP), such as SDLC/HDLC, and character-oriented
protocols (COP), such as IBM Bisync (BSC) in either ASCII or
EBCDIC coding. Formatting, synchronizing, validation and error
detection is performed automatically in accordance with protocol
requirements and selected options. Asynchronous (ASYNC) and
isochronous (ISOC) modes are also supported. In addition,
modem interface handshake sighals are available for gEineral
use.
Control, status and data are transferred between the MPCC and
the microcomputer bus via 22 directly addressable registers and
aOMA interface. Two first-in first-out (FIFO) registers, addressable through separate receiver and transmitter data registers,
ea.ch buffer up to eight characters at a time to allow more MPU
processing time to service data received or to .be transmitted
and to maximize bus throughput, especially during DMA operation. The two-channel Direct Memory Access (DMA) interface
operates with the MC68440IMC68450 DMA Controllers. Three
prioritized interrupt vector numbers separately support receiver,
transmitter and modem interface operation.
An on-chip oscillator drives the internal baUd rate generator
(BRG) and an external clock output with an 8 MHz input crystal
or clock frequency. The BRG, in conjunction with two selectable
prescalers and 16-bit programmable divisor, provides a .data bit
rate of DC to 4 MHz.
ORDERING INFORMATION
Part Number
The 48-pin R68561-supports word-length (16-bit) operation when
connected to the 68000 16-bit asynchronous bus, as well as bytelength (a-bit) operation when connected to the 68008 8-bit bus.
The 4O-pin R68560 supports byte-length operation on the 68008
bus.
R6856 _
_
~L
Document No. 68650N06
Fnlquency
Temperatura Range
4 MHz
O·C to 70·C
Package: C = Ceramic
P = Plastic
Number of pins: 0 = 40
1 = 48
Product Description Order No. 705
Rev. 3. March 1984
1-83
Multi-Protocol Communications Controller (MPCC)
R68S60, R68S61
Vee ------.GNO~
8 BYTE
(4 WORD)
TxFIFO
1-....______•
lxD
TO Ax LOGIC
(TEST MODE)
A1~A4
lACK
iRQ
00-071
00-015 2
CS
CTACK
RJW
MICROPROCESSOR
BUS
INT·ERFACE,
'-
CONTROL
REGISTERS
AND
STATUS
REGISTERS
LDSlDS3
UDS/Ao'
~------------+------.'xC
RESET
RxFIFO READ
, . . : - - - - _.. BClK
TxFIFO WRITE
EXTAL
XTAl
TDSR
RDSR
~----+------- RxC
DMA
INTERFACE
DACK
DlC
DONE
RxFIFO READ
To Tx LOGIC
(ECHO MODE)
1+-_ _ _ _....___
NOTES:
1. R6B56D ONLY.
2. R6B561 ONLY.
3. UOS ON R6B561 AO ON R6B560
4. LOS ON R6B561 OS ON R68560
Figure 1.
MPCC Block Diagram
1·84
RxD
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
PIN DESCRIPTION
write cycles it is asserted after data has been accepted at the
data bus. OTACK is driven high after assertion prior to being
tri-stated. A holding resistor is required to maintain OTACK high
between bus cycles.
Throughout the document, signals are presented using the terms
active and inactive or asserted and negated independent of
whether the signal is active in the high-voltage state or lowvoltage state. (The active state of each logic pin is described
below.) Active low signals are denoted by a superscript bar. RiW
indicates a write is active low and a read active high.
OS-Data Strobe (R68560). Ouring a write (RiW ,low), the
OS positive transition latches data on data bus lines DO - 07
into the MPCC. During a read (RiW high), OS low enables data
from the MPCC to data bus lines DO - 07.
Note: The R68561 interface is described for word mode operation only and the R68560 interface is described for byte
mode operation only.
LDS-Low.r Data Strob. (A68561). During a writ. (RiW low),
the positive transition latches'data on the data bus lines 00 - 07
(and on . 08 - 015 if UOS is low) into the MPOC. During a read
(RNi high), LOS low enables data from the MPOC to 00-07
(and to 08 - 015 if UOS is law).
A 1 - A4-Addres& Lines. A 1 - A4 are active high inputs used
in conjunction with the CS input to access the internal registers.
The address map for these registers is shown in Table 1.
AO-Address Line Ao (R68560). When interfacing to an 8-bit
data bus system such as the 68008, address line AO is used
to access an internal register. AO= 0 defines an even register
and AO = 1 defines an odd register. See Table 1b.
DO - D15-Data Lines. The bidirectional data lines transfer data
between the MPCC and the MPU, memory or other peripheral
device. DO - 015 are used when connected to the 16-bit 68000
bus and operating in the MPCC word mode. DO - 07 are used
when connected to the 16-bit 68000 bus or the 8-bit 68008 bus
and operatin~ the MPCC byte mode. The data bus is threestated when CS is inactive. (See exceptions in OMA mode.)
UDS-Upper Data Strobe (R68561). When interfacing to a
16-bit data bus system such as the 68000, a Iowan control bus
signal UOS enables access to the upper data byte on 08 - 015.
A high on UOS disables access to 08 - 015. Data is latched and
enabled in conjunction with LOS.
CS~Chlp Select. CS low selects the MPCO for programmed
transfers with the host. The MPOO is deselected when the OS
input is inactive in non-OMA mode. OS must be decoded from
the address bus and gated with address strobe (AS).
IRQ-Interrupt Request. The active low IRQ output requests
interrupt service by the MPU. IRQ is driven high after assertion
prior to being tri-stated.
RIW-ReadlWrlte. RiW controls the direction of data flow
through the bidirectional data bus by indicating that the current
bus cycle is a read (high) or write (low) cycle.
lACK-Interrupt Acknowledge. The active low lACK input
indicates that the current bus cycle is an interrupt acknowledge
cycle. When lACK is asserted the MPCC places an interrupt
vector on the lower byte (DO - 07) of the data bus.
DTACK-Data Transfer Acknowledge. OTACK is an active
low output that signals the completion of the bus cycle. During
read or interrupt acknowledge cycles, OTACK is asserted by
the MPCC after data has been provided on the data bus; during
DATA
BUS
ADDRESS
BUS
<,
{
RTS
CTS
DTR
DSR
DCD
"
A1-A4
RIW
DMA
CONTROL
INTERRUPT
CONTROL
00-015
UDS/AO
LDS/DS
CS
ASYNCHRONOUS
BUS
CONTROL
TDSR-Transmitter Data Service Request. When Transmitter OMA mode is active. the low TOSR output requests OMA
service.
DTACK
RESET
TDSR
RDSR
DACK
DONE
DTC
IRQ
lACK
Figure 2.
'"
R685601
R68561
MPCC
}
TxD
TxC
} T,RANSMITTER
INTERFACE
RxD
RxC
RECEIVER
} INTERFACE
EXTAL
XTAL
BCLK
CLOCK
} INTERFACE
Vee
GND
MPCC Input and Output Signals
1-85
MODEM
INTERFACE
R68560, R68561·
Multi-Protocol Communications Controller (MPCC)
RDSR.,..Recelver Data Service Request. When receiver OMA
mode is active, the low ROSR output requests OMA service.
RTS-Request to Send. The RTS active low output is general
purpose in nature, and is controlled by the RTSLVL bit in the
SICA.
DACK-DMA Acknowledge. The OACK low input indicates
that the data bus has been acquired by the OMAC and that the
.
requested bus cycle is beginning.
CTS-Clear to Send. The CTS active low input positive transition and level are reported in the erST and CTSLVL bits in the
Serial Interface Status Register (SISR), respectively.
DTC-Data Tranliter Complete. The OTe low input indicates
that a OMA data transfer is complete. OTC in response to a
ROSR in~icates that the data has been successfully stored
in memory. OTC in response to a TOSR indicates that the
data is present on the data bus for strobing into the MPCC. OTC
is used in conjunction with RiW to incfement the TxFIFO or
RxFIFO pointer.
DSR-Data Set Ready. The OSR active low input negative
transition and level are reporteQ-in the OSRT and OSRLVL bits
in the SISR, respectively. OSRis also an !'utput for RSYN.
DCD-Data Carrier Detect. The OCO active low input positive
transition and level are reported· in the OCOT and OCOLVL bits
in the the SISR, respectively.
TxD-Transmitted Data. The MPCC transmits serial data On the
TxO output. The TxO output changes on the negative going edgE:!
of TxC.
DONE-Done. DONE is a bidirectional active low signal. The
DONE signal is asserted by the OMAC when the OMA transfer
count is exhausted and there is no more data to be transferred,
or asserted by the MPCC when the status byte following the last
character of a frame (block) is being transferred in response to
a ROSA. The DONE signal asserted by the OMAC in response
to a TOSR ~iII be stored to track with the data byte (lower
byte for .word transfer) through the TxFIFO.
RxD-Recetved Data. The MPCC receives serial data on the RxO
input. The RxO input is shifted into the receiver with the negative
going edge of RxC.
TxC-lnInsmltter Clock. TxC can be programmed to be an input
or an output. When TxC is selected to be an input, the transmitter
clock must be provided externally. When TxC is programmed to
be an output, a clock is generated by the MPCC'sinternal. baud
rate generator. The Iaw-ta-high transition of the clock signal nominally indicates the center of a serial data present on the TxO output.
RESET-Reset. RESET is an active low, ~mpedance
input that initializes all MPCC functions. RESET must be
asserted for at least 500 ns to initialize the MPCC.
DTR-Data Terminal Ready. The OTR active low output is
general purpose in nature, and is controlled by the OTRLVL bit
in the Serial Interface Control Register (SICR).
AxC-Recelver Clock. RxC provides the MPCC receiver with
received data timing -information.
lACK
LOS
OTC
09
CS
OACK
GNO
00
08
D1
02
UOS
OTACK
RxO
010
OTR
OSR
OCO
011
ROSR
A1
GNO
A4
AO
DTACi(
RxO
OTR
OSR
DCO
ROSR
A1
GNO
A4
A2
D3
04
05
06
015
D7
RESET
CTS
A2
A3
RxC
012
BCLK
EXTAL
XTAL
013
A3
RxC
TxC
BCLK
EXTAL
XTAL
Vet;
014
DONE
TxD
TDSR
RJW
IRQ
RTS
RJW
IRQ
RTS
R68561
lACK
2
3
4
5
6
7
8
39
9
10
11
12
13
14
15
16
17
18
19
20
Pin Configuration
1-86
38
OTC
37
36
35
34
33
32
31
CS
30
29
28
27
26
25
24
23
22
21
R68560
OS
OACK
GNO
DO
D1
02
D3
D4
05
DB
07
RESET
CTS
Vet;
OONE
TxD
TDSR
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
MPCC REGISTERS
EXTAL-CrystaI/External Clock Input.
XTAL Crystal Return. E:XTAL and XTAL connect an 8 MHz
external crystal to the. MPCC internal oscillator. The pin EXTAL
may also be used as a TTL level input to supply a DC to 8 MHz
reference timing from an external clock source. XTAL must be
tied to ground when applying an external clock to the EXTAL
input.
Twenty-two registers control and monitor the MPCC operation.' .
The registers and their addresses are identified in Table 1a
(R68561 operation in word mode) and in Table 1b (R68560
operation in byte mode). When the R68561 is operated in the
word mode, two registers are read or written at a time starting
at an even boundary. When the R68560 is operated in the byte
mode, each register is explicitly addressed based on AO.
BCLK-Buflered Clock. BCLK is the internal oscillator buffered
output available to other MPCC devices eliminating the need for
additional crystals.
Table 2 summarizes the MPCC register bit assignments and their
access. A read from all unassigned location results in a read
from a "null register." A nun register returns all ones for data
and results in a nortnal bus cycle. Unused bits of a defined
register are read as zeros unless otherwise noted.
Vee-Power. 5V ± 5%.
GND-Ground. Ground (Vss).
Table 1a.
R68561 Accessible Registers (Word Mode)
Address Lines
A4 A3 A2 A1
Reglster(s)
8
15
Receiver Control Register (RCR)
o
7
Receiver Status Register (RSR)
Receiver Data Register (RDR)-16 bits'
RJW
00
0
0
0
R
02
0
0
0
1
04
0
0
1
0
0
0
Receiver Interrupt Enable Register (RIER)
Receiver Interrupt Vector Number Register (RIVNR)
R/W
Transmitter Control Register (TCR)
Transmitter Status Register (TSR)
RIW
08
0
1
0
W
OA
0
1
0
1
RJW
OC
0
1
1
0
0
Transmitter Data Register (TDR)-16 bits2
Transmitter Interrupt Enable Register (TIER)
Transmitter Interrupt Vector Number Register (TIVNR)
Serial Interface Control Register (SICR)
Serial Interface Status Register (SISR)
Reserved3
Serial Interrupt Enable Register (SIER)
RJW
10
1
0
0
RIW
12
1
0
0
1
Serial Interrupt Vector Number Register (SIVNR)
RJW
14
1
0
1
0
0
Reserved3
Protocol Select Register 2 (PSR2)
Protocol Select Register (PSR1)
RIW
18
1
1
0
Address Register 2 (AR2)
Address Register 1 (AR1)
RIW
lA
1
1
0
1
Band Rate Divider Register 2 (BRDR2)
Baud Rate Divider Register 1 (BRDR1)
RJW
lC
1
1
1
0
Error Control Register (ECR)
Clock Control Register (CCRj
RIW
lE
1
1
1
1
Notea:
1. Accessible register of the fpur word RxFIFO. The data is not initialized, howaver, RES resets the. RxFIFO pointer to the start of the first word.
2. Accessible register of the four word TxFIFO. The data is. not initialized, however, RES resets the TxFIFO pointer to the start of the first word.
3. Reserved registers may contain random bit values.
.
. . .
1·87
1
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
Table 1b.
R61S60 Accessible Registers (Byte Mode)
Reglster(s)
RIW
Addr
(Hex.) -
o
7
I
Address_ Lines
A3
A2
Al
A4
AD
Receiver Status Register (RSR)
RIW
00
0
0
0
0
Receiver Control Register (RCR)
RIW
01
0
0
0
0
1
R
O~
0
0
0
1
0
Receiver Data Register (RDR)-8 bits 1
0
03
0
0
0
1
1
Receiver Interrupt Vector Number Register (RIVNR)
RIW
04
0
0
1
0
0
Receiver Interrupt Enable Register (RIE-R)
RIW
05
0
0
1
0
1
Transmitter Status Register (TSR)
RIW
08
0
1
0
0
0
Transmitter Control Register (TCR)
RIW
09
0
1
0
0
1
W
OA
0
1
0
1
0
OB
0
1
0
1
1
Transmitter Interrupt Vector Number Register (TIVNR)
RIW
OC
0
1
1
0
0
Transmitter Interrupt Enable Register (TIER)
RIW
00
0
1
1
0
1
Serial Interface Status Register (SISR)
RIW
10
1
0
0
0
0
Serial Interface Control Re.oister (SICR)
RIW
11
1
0
0
0
1
12
1
0
0
1
0
Reserved3
Transmitter Data Register (TDR)2-8 bits
,
Reserved3
Reserved3
13
1
0
0
1
1
Serial Interrupt Vector NumbEir Register (SIVNR)
RIW
14
1
0
1
0
0
Serial Interrup(Enable Register (SIER)
R/W
15
1
()
1
0
1
ProtOCllI Select Register 1 (PSR1)
RNI
18
1
1
0
0
0
Protocol Select Register 2 (PSR2)
RNI
19
1
1
0
0
1
Address Register 1 (AR1)
RNI
lA
1
t
0
1
0
Address Register 2 (AR2)
RNI
lB
1
1
0
1
1
Band Rate Divider Register 1 (BRDR1)
RNI
lC
1
1
1
0
0
Reserved3
';"
--
Baud Rate Divider Register 2 (BR.DR2)
RNI
10
1
1
1
0
1
Clock Control Register (CCR)
RNI
lE
1
1
1
1
0
Error Control Register (ECR)
RNI
1F
1
1
1
1
1
Notes:
1. Accessible register of the eighi' bytEi RxFIFo. The data is not initialized, however, RES resets the RxFIFO pointer to the start of the filSt bytEi.
2. AccesSible register of the eight byte TxFIFO_ The data is not initialized, however, RES resets the TxFIFO pointer to the start of the filSt bytEi.
3. Reserved registers may contain random bit values.
-
1·88
Multi-Protocol Communications Controlter (MPCC)
R68S60, R68S61
Table 2.
MPCC Register Bit Assignments
Bit Number
ReHtI11
RJW
kee..
7
6
5
4
3
2
1
0
VIIlue
RIW
RDA
EOF
0
ClPERR
FRERR
ROVRN
RAJB
RIDLE
00
Receiver Status
Register (RSR)
RIW
0
RDSREN
DONEEN
RSYNEN
STRSYN
2ADCMP
RABTEN
RRES
01
Receiver Control
Register (RCR)
R
RECEIVED DATA (RxFIFOj2
--
RIW
RECEIVER INTE;RRUPT VECtOR NUMBER (RIVN)
OF
Receiver Interrupt Vector
Number Register (RIVNR)
Receiver Interrupt Enable
Register (RIER)
Receiver Data
Register (RDR)
RIW
RDA
IE
EOF
IE
0
C/PERR
IE
FRERR
IE
ROVRN
IE
RA/B
IE
0
00
RIW
TDRA
TFC
0
0
0
TUNRN
TFERR
0
,60
Transmitter status
Register (TSR)
RIW
TEN
TDSREN
TICS
THW
TLAST
TSYN
TABT
TRES
01
Transmitter Control
Register (TCR)
Transmitter Data
Register (TOR)
W
TRANSMITTED DATA (TxFIFOj2
--
RIW
TRANSMITTER INTERRUPT VECtOR NUMBER (TIVN)
OF
Transmitter Interrupt Vector
Number Register (TIVNR)
RIW
TDRA
IE
TFC
IE
0
0
0
TUNRN
IE
TFERR
IE
0
00
Transmitter Interrupt Enable
Register (TIER)
RIW '
CTST
DSRT
DCor
CTSLVL
DSRLVL
DCDLVL
0
0
00
Serial Interface Status
Register (SISR)
RTSLVL
DTRLVL
0
0
0
ECHO
TEST
NAZI
00
Serial Interface Control
Register (SICR)
RIW
12
RANDOM .BIT VALUES
(reserved)
13
RANDOM BIT VALUES
(reserved)
OF
Serial Interrupt Vector
Number Register (SIVNR)
0
00
Serial Interrupt Enable
Register (SIER)
ADDEX
00
Protocol Select
Register 1 (PSR1)
od
Protocol Select,
Register 2 (PSR2)
SERIAL INTERRUPT VECtOR NUMBER (SIVN)
" RIW
RIW
CTS
IE
DSR
IE
DCD
IE
RIW
0
0
0
RIW
WD/rNT
RIW
" 0
0,
0
0
0
0
0
CTLEX
I
SlOP BIT SEL
CHAR LEN SEL
PROTOCOL SEL
SB1
CL2
PS3
SB2
I CL1
I PS2 r PS1
BOP ADDRESSIBSC & COP PAD
00
Address Register 1 (AR1)
RIW
BOP ADDRESSIBSC.& COP SYN
00
Addrese Register 2 (AR2)
RIW
BAUD RATE DIVIDER (LSH)
01
Baud Rate Divider
Register 1 (BRDR1)
RIW
BAUD
00
Baud Rate Divider
Register 2 (BRDR2)
00
Clock Control
Register (CCR)
04
Error Control
Register (ECR)
RATe
DIVIDER (MSH)
RIW
0
0
0
PSCDIV
TCLKO
RCLKIN
RIW
PAREN
ODDPAR
0
0
CTLCRC
CRCPRE
Natee:
1. RESET = Register contenIB upon power up or RESET.
2. l6-bits for R68581 (word mode); 6-bits for R68560 (byte mode).
HI9
CLK SEL
CK2 I CK1
CRCSEL
CR2 I CRl
R68560, R6856t
Multi-Protocol Communications Controller (MPCC)
REGISTER DEFINITIONS
RSR
~
o
RECEIVER REGISTERS
Receiver Status Register (RSR)
Reset Value = $00
RSR
The Receiver Status Register (RSR) contains the status of the
receiver including error-conditions. Status bits are cleared by
writing a 1 into respt;jotive positions, by writing a 1 into the RCR
.RRES bit or by .RESET. If an EOF, C/PERR, or FRERR is set
in the RSR, the data reflecting the error (the first byte or word
in the RxFIFO) must be read prior to resetting the correspond·
ing status bit in the RSA. The IRQ output is asserted if any
of the conditions.reported by the status bits occur and the cor·
responding interrupt enable bit in the RIER is set.
1o
1
J!.
o
RDA
-Reclliver Data Available. (RSR only).
The RxFIFO is empty (Le.,no received data is
available).
Received data is available in the RxFIFO and can be
read via the ROA.
o
Sta~us (R~fl)
For the BSC and BOP protocols which have defined mellsage
blocks. or frames, a "frame status" byte will be loaded into the
RxFIFO following the last data byte of each block. The frame
status contains all the status contained within the RSR with the
exception of ROA and RIOLE. But, in addition to the RSR con·
tents, the frame status byte has a RHW status in bit 5 which
indicates either an even or odd boundary (applicable to word
mode only).
RSR
.!.
RIDLE
-Receiver Id!e. (RSR orily).
Receiver not idle.
15 or more consecutive "1's" have been received and
the receiver is. in an inactive idle state.
• Fnlme
RSA
O·
RA/B
-Receiver Abort/Break.
Normal Operation.
ABORT detected after an opening flag (BOP), ENQ
detected in a block of text data (BSC), or BREAK
detected (ASYNC).
RSR
The RSR format is the saine as the frame status format (see
below) except as noted.
L
ROVRN
-Receiver Overrun.
No receiver overrun detected.
Receiver overrun detected. Indicates that receiver data
was attempted to be transferred into the RxFIFO when
it wasJull, resulting in loss of received data. The data
that is already in RxFIFO are not affected and may be
read by the processor. .
EOF
-End cif Frame.
No end of frame or block detected.
End of frame or block detected (BOP and BSC).
RSR
i
o
RHW
-Receive Half Word. (Frame Status only)"
The last word of the frame contains data on the upper
half (08 - 015) and frame status on the lower half
(DO - (7) of the data bus.
The lower haif of the data bus (DO - 07) contains the
frame status but the upper half (08 - 015) is blank or
invalid.
If the MPCC is in word mode and the last data byte was on an
even byte boundary (I.e., there was an even number of bytes
in the message), a blank byte will be.loaded il'\to the RxFIFO
prior to loading the frame status byte in order to force the "ftame
status" byte and the next frame to be on an even boundary.
When RHW = 0, the last word of the frame contains data on
the upper half and status on the lower half of the data bus. ·If
RHW = 1, the lower half of the bus contains status but the upper
half is a blank or invalid byte .
RSR
.!.
o
C/PERR
-CRC/Parity Error.
No CRC or parity error detected.
CRC error detected (BOP, BSC), Parity error detected
(ASYNC,ISOC and COP).
In the byte mode, the status byte will always immediately follow
the .Iast data byte of the block/frame (see Figure 3). The EOF
status in the RSR is then set when the bytelword containing the
frame status is the next byte/word to be read from the RxFIFO.
RSR
3 FRERR
-Frame Error.
'0
NC):frame error detected.
1
Short Frame or a closing FLAG detected off boundary
(BOPl, Frame error (ASYNC, ISOC) or receiver
overrun.
In the receiver OMA mode, when the EOFstatus in the RSR
is set, DONE is asserted to the OMAC. Thus the last byte
accessed by the OMAC is always a status byte,. which the
processor may read to check the validity of entire frame.
1-90
R68560,R68561
Multi-Protocol Communications Controller (MPCC)
D15
WORD
D8
DO
D7
WORD
D15
N
WORD MODE
(RHW
= 0)
DATA
N + 1
BLANK
STATUS
N+2
NEXT
(RHW
BYTE
D7
BYTE MODE
BYTE
DO
DATA
M
FRAME
=
D7
M
1)
DO
DATA
M + 1
STATUS
M + 1
STATUS
M + 2
NEXT FRAME
M + 2
NEXT FRAME
Figure 3.
D
DO
D8 D7
DATA
BSC/BOP Block/Frame Status Location
Receiver Control Register (RCR)
RCR
.!.
RABTEN -Receiver Abort Enable (BOP only).
Do not abort frame upQti error detection.
1.
Abort frame upon RxFIFO overrun (ROVAN bit
I in
the ASR) or CFCRC error detection (C/PERR bit = 1
in the RSR). If either error occurs, the MPCC ignores
the remainder of the current frame and searches for
the beginning of the next frame.
o
Reset value
= $01
The Receiver Control Register (RCR) selects receiver control
options.
=
RCR
-Not used.
L
RCR
o
'0
RCR
.!. RDSREN .....Recelver Data Service Request Enable.
o
Disable receiver DMA mode.
Enable receiver DMA mode ..
RCR
5
'0
1
DONEEN -DONE Output Enable.
Disable DONE output.
Enable DONE output. (When the receiver is in the DMA
mode, i.e., RDSREN =: 1).
RRES
-Receiver Reset Command.
Enable normal receiver operation .
Reset receiver. Resets the receiver section including
the RxFIFO and the ASR (but not the RCR). RRES is
set by RESET or by writing a 1 into this bit for one write
cycle and is cleared by writing a 0 into this bit. RRES
requires clearing after RESET.
Receiver Data Register (RDR)
R68S61 (Word Mode)
RCR
4 RSYNEN
-
o
1
....,.RSYNEN Output Enable. Selects the
DSR signal input or the RSYN SYNC
signal output on the DSR pin.
Input DSR on DSA.
Output RSYN on DSA.
R68560 (Byte Mode)
4
MSB
RCR
3 STRSYN -Strip SYN Character (COP only).
'0
Do not strip SYN character.
Strip SYN character.
1
3
Byte
o· .
.0
2
LSB
The receiver has an 8-byte (or 4-word) First In First Out (FIFO)
register file (RxFIFO) where received data are stored before
being transferred to the bus. The received data is transferred
out of the RxFIFO via theRDR in S-bit bytes or 16-bit·words
depending on the WD/BYT bit setting In PSR2. When the
RxFIFO has a data bytelword ready to be transferred, the RDA
status bit in the RSR is set to 1.
RCR
2 2ADCMP -OnelTwo Addreaa Compare (BOP only).
'0
Compare one address byte with the contents of ARI.
1
Compare two. address bytes with the contents of ARI
and AR2.
1-91
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
Receiver Interrupt Vector Number Register (RIVNR)
TRANSMITTER REGISTERS
Transmitter Status Register (TSR)
TFERR
Reset value - $OF
Resei value = $80
If a receiver interrupt condition occurs (as reported by status
bits in the RSR that correspond to interrupt enable bits in the
RIER) and the corresponding bit is set in the RIER, IRQ output
is asserted to request MPU receiver interrupt service. When the
lACK input is asserted from the bus, the Receiver Interrupt Vector Number (RIVN) from the Receiver Interrupt Vector Number
Register (RIVNR) is placed on the data bus.
The Transmitter Status Register (TSR) contains the transmitter
status including error conditions. The transmitter status bits are
,'cleared by writing a 1 into their respective positions, by writing
a 1 into the TCR TRES bit, or by RESET. The IRQ output is
asserted if any of the conditions reported by the status bits occur
and the corresponding interrupt enable bit in the TIER is set.
Receiver Interrupt Enable Register lRIER)
TSR
7
6
5
4
3
2
1
0
RDA
IE
EOF
IE
0
C/PERR
IE
FRERR
IE
ROVRN
IE
RAJB
0
:J...
o
IE
1
Reset value ~ $00
TSR
The Receiver Interrupt Enable Register (RIER) contains interrupt enable bits for the Receiver Status Register (RSR). When
output is asserted when the corresponding
enabled. the
conditi,onis detected and raported in the RSR.
~
mo
0,
1
RIER
:J...
o
1
RDA IE
~Recelver Da~a
Available Interrupt
Enable. ,
Disable RDA Interrupt.'
Enable RDA Interrupt.
o
1
TSR
.!. TUNRN
-Not used.
RIER
.!.
o
o
CIPERR IE -CRCIParlty Error Interrupt Enable.
Disable C/PERR Interrupt.
Enable C/PERR Interrupt.
o
1
-Transmitter Underrun (BOP, BSC and
COP only). A transmitter underrun occurs
when the transmitter runs out of data during a transmission. For BOP, the underrun
condition is treated as an abort. For BSC
and COP, SYN characters are transmitted
until. more data is available in the TxFIFO.
No transmitter underrun occurred .
Transmitter underrun Occurred.
TSR
.1.
RIER
1.'
-Not used.
TSR
EOF IE
-End of Frame Interrupt Enable.
Disable EOFlnterrupt.
Enable EOF Interrupt.
RIER
~
-Transmitted Frame Complete. (BOP, BSC
and COP only).
Frame not complete.
Closing FLAG or ABORT character lias been transmit-,
ted (BOP); Trailing PAD has been transmitted (BSC),
or the last character of a frame or block as defined by
TLAST (TCR bit 3) has been transmitted (COP).
TFC
.H.
RIER
~
TDRA
-Transmitter Data Register Available.
The TxFIFO is full. '
The TxFIFO is not full (i.e., available) and data to
transmit can be loaded via the TOR.
o
FRERR IE -Frame Error Interrupt Enable.
Disable FRERR Interrupt.
Enable FRERR Interrupt.
1
TFERR
-Transmit Frame Error (BOP only).
No frame error has occurred.
No control field was present (short frame).
Transmitter Control Register (TCR)
RIER
.!.
o
1
ROVRN IE -Recel,ver Overrun Interrupt Enable.
Disable ROVRN Interrupt.
Enable ROVRN Interrupt.
Reset vallie = $01
The Transmitter Control Register (TCR) selects transmitter control function .
RIER
'RAIS IE -Receiver Abort/Break Interrupt Enable.
Disable RAtB Interrupt.
Enable RAtB Interrupt.
1
.1.
o
TCR
:J...
TEN
-Transmitter Enable'.
ODisable transmitter. TxD OlltPUt is idled. The TxFIFO
may be' loaded while the transmitter is disabled .
Enable transmitter.
RIER
.Q.
-Not used.
1-92
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
TCR
TCR
.§..
o
J!.
TDSREN
-Transmitter Data Service Request
Enable.
Disable transmitter DMA mode.
Enable transmitter DMA mode.
TRES
-Transmitter Reset Command.
Enable normal transmitter operation.
Reset transmitter. Clears the transmitter section
including the TxFIFO and the TSR (but not the TCR).
The TxD output Is held in "Mark" condition. TRES is
set by RESET or by writing a 1 into this bit for one write
cycle and is cleared by writing a 0 into this bit. TRES
requires clearing after RESET.
o
1
TCR
.!.
o
-Transmitter Idle Character Select. Selects
the idle character to be transmitted when
the transmitter is in an active idle mode
(transmitter enabled or disabled).
Mark Idle (TxD output is held high).
Content of AR2 (BSC and COP), BREAK condition
(ASYNC and ISOC), or FLAG character (BOP).
TICS
Tranamlt Data Register (TOR)
TCR
.!.
o
RBISSO (Byte Mode)
-Transmit Half Word. (R68561, word mode·
only). This bit is used when the frame or
block ends on an odd boundary in conjunction with the TLAST bit and indicates that
the last word in the TxFIFO contains valid
data in the upper byte only. This bit must
always be 0 in byte mode (R68560).
Transmit full word (16 bits) from the TxFIFO.
Transmit upper byte (8 bits) from the TxFIFO.
THW
4
o
o
2
lSB
The transmitter has an 8-byte (or 4-word) FIFO register file
(TxFIFO). Data to be transmitted Is transferred from the bus into
the TxFIFO via the TDR in 8-bit bytes or 16-bit words depending on the WD/BYT bit setting in PSR2. The TDRA status bit
in the TSR is set to 1 when the TxFIFO is ready to accept another
data wordlbyte.
TCR
~
3
Byte 0
Transmitter Interrupt Vector Number Register (TIVNR)
-Transmit Last Character (BOP, BSC and
COP only).
The next character is not the last character in a frame
or block.
The next character to be written into the TDR is the
last character of the message. The TLAST bit
automatically returns to a 0 when the associated
word/byte is written to the TxFIFO. If the transmitter
DMA mode is enabled, TLAST is set to a 1 by DONE
from the DMAC. In this case the character written into
the TDR in the current cycle is the last character.
TLAST
Reset value - $OF
If a transmitter interrupt condition occurs (as reported by status
bits in the TSR that correspond to interrupt enable bits in the
TIER) and the corresponding bit in the TIER is set, the IRQ
output is asserted to request MPUtransmitter interrupt service.
When the lACK input is IlSserted from the bus, the Transmitter
Interrupt Vector Number (TIVN) from ttie Transmitter Interrupt
Vector Number Register (TIVNR) is placed on the data bus.
TCR
.!.
o
1
TSYN
-Transmit SYN (BSC and COP only).
Do not transmit SYN characters.
Transmit SYN characters. Causes a pair of SYN
characters to be transmitted immediately following the
current character. If BSC transparent mode is active,
a DLE SYN sequence is transmitted. The TSYN bit
automatically returns to a 0 when the SYN character
is loaded into the Transmitter Shift Register.
Transmitter Interrupt Enable Register (TIER)
o
B
5
4
3
2
1
0
TFC
IE
0
0
0
TUNRN
IE
TFERR
IE
-
Reset value - $00
The Transmitter Interrupt Enable Register (TIER) contains
interrupt enable bits for the Transmitter Status Register. When
enabled, the IRQ output is asserted when the corresponding
condition is detected and reported in the TSR.
TCR
~
7
TORA
IE
TABT
-Transmit ABORT (BOP only).
Enable normal transmitter operation.
Causes an abort by sending eight consecutive 1's. A
data word/byte must be loaded into the TxFIFO after
setting this bit in order to complete the command. The
TABT bit clears automatically when the subsequent
data word/byte is loaded into the TxFiFO.
TIER
L
o
1-93
TDRA IE
-Transmitter Data Register (TDR) Available Interrupt Enable.
Disable TDRA Interrupt.
Enable TDRA Interrupt.
D
R68560, R68561
Multi·Protocol Communications Controller (MPCC)
TIER
.§.. TFC IE
o
SISR
-Transmit Frame Complete (TFC) Interrupt
Enable.
Disable TFC Interrupt.
Enable TFC Interrupt.
.1.
o
1
DSRLVL -Data Set Ready Level.
DSR input level is negated (high).
DSR input level is asserted (lOW).
SISR
~
TIER
M
o
-Not used.
TIER
~
o
DCDLVL -Data Carrier Detect Level.
DCD input level is negated (high).
DCD input level is asserted (low).
SISR
TUNRN IE -Transmitter Underrun (TUNRN) Interrupt
Enable.
Disable TUNRN Interrupt.
Enable TUNRN Interrupt.
-Not used.
1.:2.
Serial Interface Control Register (SICR)
TIER
J.-
o
TFERR IE -Transmit Frame Error (TFERR) Interrupt
Enable.
Disable TFERR Interrupt.
Enable TFERR Interrupt.
Reset value = $00
The Serial Interface Control Register (SICR) controls various
serial interface signals and test functions.
TIER
~
SICR
-Not used.
L
o
SERIAL INTERFACE REGISTERS
RTSL VL -Request to Send Level.
Negate RTS output (high).
Assert RTS output (low).
NOTE
In BOP, BSC, or COP, when the RTSLVL bit is cleared
in the middle of data transmission, the RTS outputremains asserted until the end of the current frame
or block has been transmitted. In ASYNC or ISOC, the
RTS output is negated when the TxFIFO is empty. If
the transmitter is idling when the RTSLVL bit is reset,
the RTS output is negated within two bit times.
Reset value = $00
The Serial Interface Status Register (SISR) contains the serial
interface status information. The transition status bits (CTST,
DSRT and DCDT) are cleared by writing a 1 into their respective positions, or by RESET. The level status bits (CTSLVL,
DSRLVL and DCDLVL) reflect the state of their respective inputs
and cannot be cleared internally. The IRQ output is asserted
if any of the conditions reported by the transition slatus bits occur
and the corresponding interrupt enable bit in the SIER is set.
SICR
SISR
SICR
L
o
~
o
M
CTST
-Clear to Send Transition Status.
CTS has transitioned positive (from active to inactive).
(TRES must be zero).
CTS has not transitioned positive.
DTRLVL -Data Terminal Ready Level.
Negate DTR output (high).
Assert DTR output (low).
-Not used. These bits are initialized to 0 by
RESET and must not be set to 1.
SICR
~
o
SISR
-Data Set Ready Transition Status •
.§.. DSRT
DSR has transitioned negative (from inactive to active).
1
DSR has not transitioned negative.
o
SISR
-Data Carrier Detect Transition Status.
~ DCDT
DCD has transitioned positive (from active to inactive).
1
DCD has not transitioned positive.
o
ECHO
-Echo Mode Enable.
Disable Echo mode (enable normal operation).
Enable Echo mode. Received data (RxD) is routed
back through the transmitter to TxD. The contents of
the TxFIFO is undisturbed. This mode may be used
for remote test purposes.
SICR
J.-
o
SISR
4
CTSLVL -Clear to Send Level.
CTS input level is negated (high).
o
CTS input level is asserted (low).
1-94
TEST
-Self-test Enable.
Disable self-test (enable normal operation).
Enable self-test. The transmitted data (TxD) and clock
(TxC) are routed back through to the receiver through
RxD and RxC, respectively (DCD and CTS are
ignored). This "Ioopback" self-test may be used for
all protocols. RxC is external regardless of the state
of CCR bit 2. CCR bit 3 may be a 0 or a 1.
_ . ,. .~_'~. . . ')~
SICR
J!.
-NRZI Data Format Select. Selects the
transmit and receive data format to be NAZ
or NAZI.
Select NAZ data format. NAZ coding-high
1 and
low = O.
Select NRZI data format. The serial data remains in
the same state to send a binary 1 and switches to the
opposite state to send a binary O. A 1 bit delay is added
to the TxD output to allow for encoding.
I : I : I I I : I I CT~EX I
NRZI
=
o
D
AD~EX
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
I
Reset value = $00
Protocol Select Register 1 (PSR1) selects BOP protocol related
options.
PSRl
7-2
Serial Interrupt Vector Number Register (SIVNR)
-Not used.
PSRl
~
CTLEX
-Control Field Extend (BOP only).
Select S-bit control field.
Select f6-bit control field.
o
Reset value = $OF
If a serial interface. interrupt condition occurs (as reportee! by
status bits in the SISR that correspond to interrupt enable bits
in the StER) and the corresponding bit in the SIER is set, 'the
IRQ output is asserted to request MPUserial interface interrupt
service. When the lACK input is asserted from the bLls, the Serial
Interrupt Vector Number (SIVN) from the Serial Interrupt Vector
Number Register (SIVNR) is placed on the data bus.
PSRl
ADDEX
-Address Extend (BOP only).
Disable address extension. All eight bits of the
address byte are utilized for addressing.
Enable address extension. When bit 0 in the address
byte is a 0 the address field is extended by one byte.
An exception to the address field extension occurs
when the first address byte is all O's (null address).
J!.
o
Serial Interrupt Enable Register (SIER)
7
6
5
4
3
2
1
0
CTS
IE
DSR
IE
DCD
IE
0
0
0
0
0
Protocol Select Register 2 (PSR2)
7
1
o
CTS IE
-Clear to Send (CTS) Interrupt Enable.
Disable CTS Interrupt.
Enable CTS Interrupt.
1
L
o
I
3
I SBl
CL2
I
Cll
I
0
1
2
PROTOCOL SEL
PS3
1 PS2 1 PSl
DSR IE
-Data Set Ready (DSR) Interrupt Enable.
Disable DSR Interrupt.
Enable DSR Interrupt.
-Data Carrier Detect (DCD) Interrupt
Enable.
Disable DCD Interrupt.
Enable DCD Interrupt.
WD/BYT -Data Bus Word/Byte Mode.
Select byte mode. Selects the number of data bits to
be transferred from the RxFIFO and the registers to
the data bus and to be transferred from the data bus
to the TxFIFO and the registers. The MPCC is initialIz.ed by RESET to the byte mode.
Select word mode. For operation with the 16-bit bus,
select the word mode by sending $80 on 07 - DO to
address $19 prior to transferring subsequent data
between the MPCC and the data bus.
PSR2
6-5
STOP BIT SEL
SIER
4-0
I
PSR2
SIER
~ DCD IE
o
4
Protocol Select Register 2 (PSR2) selects protocols, character
size, the number of stop bits, and word/byte mode.
SIER
~
5
Reset value = $00
SIER
o
I
STOP BIT SEL CHAR LEN SEL
SB2
The Serial Interrupt Enable Register (SIER) contains interrupt
enable bits for the Serial Interface Status Register. When an
interrupt enable bit is set, the IRQ output is asserted when the
corresponding condition occurs as reported in the SISR.
L
6
WD/BYT
Reset value =' $00
-Not used.
-Number of Stop Bits Select.
Selects the number of stop bits
transmitted at the end of the data
bins In ASYNC and ISOC modes.
GLOBAL REGISTERS
No. of Stop Bits
The global registers contain command information applying to
different modes of operation and protocols. After changing global
register data, TRES in the TCR and RRES in the RCR should
be set then cleared prior to performing normal mode processing.
1-95
6
5
SB2
SBl
0
0
0
1
0
ASYNC
1
1-1/2
2
ISOC
1
2
2
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
Baud Rate Divider Register 1 (BRDR1)
PSR2
4-3 CHAR LEN'SEL -Character Length Select. Selects
the character length except in BOP
and BSC where the character length
is always eight bits. Parity is not
included in the character length.
3,
4
Character Length
CL1
CL2
5 bits
0
0
6 bits
1
0
.7 bits
1
0
8 bits
1
2
o
PS1
o
.0
o
1
o
,I
1
o
o
o
o
o
o
1
.1
o
1
o
1
1
1
3
o
2
Reset value = $01
Baud Rate Divider Register 2 (BRDR2)
7
5
6
4
'3
o
2
,BAUD RATE DIVIDER (MSH)
Reset value = $00
The two 8-bit Baud Rate Divider Registers (BRDRI and BRDR2)
hold the divisor of the Baud Rate Divider circuit. BRDRI contains the least significant half (LSH) and BRDR2 contains the
most significant half (MSH), With an 8.064 MHz EXTAL input,
standard bit rates can be selected using the combination of
Prescaler Divider (in the CCR) and Baud Rate Divider values
shown in Table 3. For isochronous or synchronous protocols,
the Baud Rate Divider value must be multiplied by two for the
same Prescaler Divider value.
Protocol
BOP (Primary)
BOP (Secondary)
Reserved
COP
BSC EBCDIC
BSC ASCII
ASYNC
ISOC
1
.1 4 1
5
BAUD RATE DIVIDER (lSH)
PSR2
2.() PROTOCOL SEL -Protocol Select. Selects protocol
and defines the protQCol dependent
control bits.
PS3
1 '6 1
7
The Baud Rate Divider (BRD) value can be computed for other
crystal frequency, prescaler divider and desired baud rate values
as follows:
BRD = Crystal Frequency
(Prescaler Divider) (Baud Rate) (I<)
Address Register 1 (AR1)
I
7
1
1 514
6
'1
3
2
BOP ADDRESS/BSC & COP PAD
K = 1 for isochronous or synchronous
2 for asynchronous
where:
o
Reset value = $00
Clock Control Register (CCR)
Address Register 2 (AR2)
o
7
6
5
4
3
2
0
0
0
PSCDIV
TClKO
RClKIN
CK2
BOP ADDRESS/BSC & COP SYN
Reset value =
t
I
0
ClK SEl
I CKI
Reset value = $00
$00
The CCR selects various clock options.
The protocol selected in PSR2 (BOP, BSC and COP only) determines the function of the'two 8-bit Address Registers (ARI and
AR2). As a secondary station in BOP, the contents of the address
registers are used for addre$s matching depending on the
2 ADCMP seleCtion in theRCR. In BSC and COP, ARI and AR2
contain programmable leading PAD and programmable SYN
characters, respectively.
CCR
-H..
CCR
.!.
Address Register (AR) Contents
Protocol Selected
2ADCMP
ARt
AM
BOP (Primary)
BOP (Secondary)
X
BSC EBCDIC
BSCASCII
COP
X
X
X
X
Address
Address
leading PAD
leading PAD
leading PAD
X
X
Address
SYN
SYN
SYN
0
1
-Not used.
o
1
PSCDIV
-Prescaler Divider. The Prescaler Divider
network reduces the externalloscillatorfrequency to a value for use by the internal
Baud Rate Generator.
Divide by 2.
Divide by 3.
CCR
.!.
o
·1
'X = Not used
1-96
TCLKO
-Transmitter Clock Output Select.
Seiect TxC to be an input.
Select TxC to be an output.
R68560, R68561
Multi.;Protocol Communications Controller (MPCC)
Table 3.
Standard Baud Selection (8.064 MHz Crystal)
Baud Rate Divider
Hexadecimal Value
Decimal'
Value
50
75
110
135
150
300
1200
1800
2400
3800
4600
7200
1
Decimal
Value
26,880
26,880
12,218
14,933
8,960
6,720
1,126
1,120
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
3
2
2
2
3
2
3
3
3
9600
o
PSCDIV
(0 to 1)
3
2
3
2
3
2
19200
38400
CCR
.!.
BRDRl
(LSH)
Decimal
Value
BRDR2
(MSH)
BRDRl
(LSH)
69
69
2F
SA
23
lA
04
04
03
02
01
01
00
00
00
00
00
53,760
53,760
24,436
29,866
17,,920
13,440
2,240
2,240
1,660
1,120
560
560
260
140
70
02
02
5F
74
46
34
00
00
74
e4Cl
560
280
260
140
70
35
BA
55
00
40
60
60
46
30
1..8
18
BC
46
23
.!.
-Receiver Clock Internal Select (ASYNC
only).
'
Select External RxC.
Select Internal Rxe.
CLK DIY
o
1
00
80
CO
CO
06
90
04
02
02
01
00
00
60
30
30
18
BC
46
CK2
CK1
o
o
0
.!.
o
1 (lSOC)
16
32
64
o
6
7
5
4
- -
3
2
CFCRC
-Control Field CRC Enable.
Disable control field CRC. Enables an intermediate
CRC remainder to be appended after the address/control field in transmitted BOP frames and checked in
received framllS. The CRC generator is reset after control field CRe calculation.
ECR
.!.
CRCCTL CRCPRE
-Not used.
ECR
Divider
1
ODDPAR ,-Odd/Even Parity Select (Effective only
when PAREN .1).
Generatelcheck even parity.
Generatelcheck Odd parity.
ECR
5-4
-External Receiver Clock Divider. Selects
the divider of the external RxC to detemiine
the receiver data rate.
PAREN OOOPAR
1
I
o
1
0
CRCSEL
CR21cRI
CRCPRE -CRC Generator PresetSelect.
Preset CRC Generator to O.
Preset CRC Generator to 1 and transmit the 1's complement of the resulting remainder.
ECR
~
Reset value = $04
CRCSEL'
.J
The Error Control Register (ECR) selects the error detection
method used by the MPCC.
ECR
o
08
08
AA
ECR
RCLKIN
Error Control Register (ECR)
L
Hoadae,lmsl Velue
BRDR2 '
(NSH)
CCR
~
Isochronous eRel Synchronoua
Aaynch~nous
Pl'IIfC8ler Divider
Desired
Baud Rate
(Bit Rate)
PAREN
-Parity Enable. (ASYNC, ISOC and COP
only).
Disable parity generation/checking.
Enable parity generation/checking.
1
0
CR2
CR1
0
0
0
1
0
1
1
-CRC Polynomial Select. Selects one of the
RC polynominals.
Polynomlnal
XI6+XI2+X5+1 (CCITT V.41)
XI6+XI5+X2+1 (CRC-1S)
(VRC/LRC),
x8 +1
Not used.
·VRC: Odd-parity check is performed of' each
character including the LRC character.
1-97
D
Multi·ProtocolCommunications Cont.roller (MPCC)
R68560,R68561
INPUT/OUTPUT FUNCTIONS
MPCC .and the OMAC illl accompliShed by a two-signal
requeSt/acknowledge handshake. Since the MPCC 'has only one
ac1tnowledge input (OACK) for its two OMA request lines, an
external OR function must be provided to combine the two OMA
acknowledge signals. The MPCC uses the ANi input to
distinguish between the Transmitter Data Service Request (TOSR
acknowledge and the Receiver Data Service Request (ROSR)
acknowledge.
MPUINTERFACE
Transfer of data between the MPCC and the system bus involVes
the followirig signals:
R68561
A()';'A4
Al-A4
AddresS lines
0()';'015
Data lines
.00-07
Read/Write
ANi
Data Transfer Acknowledge
OTACK
OTACK
'CS
Chip Select
CS
Data Strobes
U013 and lOS
OS
ANi
Receiver DMA Mode
The re6e.iver OMA mode is enabled when the RDSREN bit in the
RCR is set to 1. When data is available in the RxFIFO, Receiver
Oafa Service Request (ROSR) is asserted for one receiver clock
period to initiate the MPCC to memory DMA transfer. The next
ROS!,! cycle may be initiated as sapn as the current ROSR cycle
is completed (i.e., a full sequence of OACK, OS, and DTC).
Figures 10 and 11 show typical interface connections.
Read/Write Operation
The RJW input controls the direction of data flow on the data bus.
CS (Chip Select) enables the MPCC for access to the internal
registers and other operations. When CS is asserted, the data
1/0 buner acts as an output driVer during a read operation and
as an input buffer during a write operation. CS must be decoded
from the address bus and gated with address strobe (AS). .
In response to ROSR assertion, the DMAC sets the ANi line to
write, asserts the memory address, addre~ strobe, and OMA
acknowledge. The MPCC outputs data frorn the RxFIFO to the
data bus and the DMAC asserts the data strobes. The memory
latches the d!lta and asserts OTACK to complete the data transfer.
The DMAC aSserts OTC to indicate to the MPCCthat data transfer
is complete. Figwe 13 shows the timing relationships for the
receiver OMA mode.
.
When the R!)8561 is connected to the 16-bit bus for .9peration
in the word mode (WO/BYT =. lil11he PSR2), address lines
Al-A4 select the internal register(s) (the 8-bitcontrol/status
registers are accesed two at a time and the 16-bit data registers
are accessed on even address boundaries). Wilen the MPCC is
selected (CS low) during a read (ANi high), 16 bits of register
data are placed on the data bus when the c;jata strobes (lOS and
UOS) are asserted. lOS strobes the eight data bits from the even
numbered registers to the lower data bus lines (O()';'O7) and UPS
strobes the eight data bits from the odd numbered registers to
the upper data bus .lines (08--015). The ~PCC asserts Data
Transfer Acknowledge (OTACK prior to placing data on the data
bus. Conversely, when the MPCC is selected (CS low) during
a write (ANi low) lOS. and UOS $trobEl data from the DO - 07
and 08-015 data bus lines into the addressed even and odd
numbered registers, respectively, and the MPCCasserts OTACK.
OTACK is negated when CS is negated. Figures 12 and 13
show the read and write timing relationships.
ROSR is inhibited when either ROSREN is reset'to 0 or RRES
is set to 1 (both in the RCR), or when RESET is asserted.
Transmitter DMA Mode
The transmitter OMA mode is enabled when the TOSREN bit in
the TCR is set to 1. When the TxFIFO is.available, Transmitter
Data Service Request (TOSR) is asserted for one transmitter clock
period to initiate the memory to MPCC OMA transfer. The next
TOSR cycle may be initiated as soon as the current TOSR cycle
is completed.
In the transmitter OMA mode, the TxFIFO Is implicitly addressed.
That is, when the transfer is from memory to the TxFIFO, only
the memory is addressed. In response to TOSR assertion, the
OMAC sets the ANi line to read, asserts the memory address,
the address strobe, the data strobes and OMA acknowledge: The
memory places data on thedata bus and asserts OTACK. Data
is valid at this time and will remain valid until the data sirobes
are negated. The OMAC asserts OTC to indicate to the MPCC
that data is avallabl.e. The MPCC loads the data into the TxFIFO
on the negation (rising edge) of OS and the transfer is complete.
A timing diagram for the transmitter OM~ Mode is .shown in
Figure 15.
When the R68560 is .connected to the 8-bit bus for operation in
the byte mode (WO/BYT = 0 in the PSR2), address lines AO-A4
select one internal8-bit register. When the MPCC is selected (CS
low) during a read (RJW high), eight bits of register data are placed
on data bus lines O()';'07 when the data strobe (OS) is asserted.
When the MPCC is selected (CS low) for a write (ANi low), OS
strobes data from the 0()';'07 data lines into the selected register.
DMA INTERFACE
TOSR is inhibited when either TOSREN is reset to 0 or TRES
i.s set to 1 (both in the TCR), or when .RESET is asserted.
The MPCC is capable of pr~viding DMA data transfers up to 2
Mbytes per second when used with the MC68440 or MC68450
OMAC in the single address mode. Based on 4 Mb/s serial data
rate and 5 bitslcharacter, the maximum OMA required transfer
rate is 800 Kbyt~s per second.
DONE Signal
When the OMA transfer count is exhausted in transmitter OMA
mode, the OMAC asserts DONE which sets the TLAST bit in the
TCR to indicate that the last wordlbyte has been transferred. In
the receiver OMA mode, DONE is asserted by the MPCC when
the last character of the frame/block is being transferred from the
RxFIFO to the data bus if the DONEEN bit is set to a 1 in the RCA.
The MPCC has separate DMA enable bits for the transmitter and
receiver, each of which requires a OMA channel. Both the
transmitter and receiver data are implicitly addressed (TOR or
ROR) therefore addressing of the data register is not required
before data may be transferred. Communication between the
1-98
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
INTERRUPTS
DSR (Data Set Ready) Input/RSYN Output
If an interrupt generating status occurs and the interrupt is
enabled, the Mpcc asserts thelAQ output. Upon receiving lACK
for the pending interrupt request, the MPCC places an interrupt
vector on 00-07 data bus and asserts DTACK.
The DSRT input from theDCE indicates the status of the local
set. The DSRT bit in the SISR contains the transition status of
the DSR input while the DSRlVL bit in the SrSR reports the
current level. A negative transition on the DSR pin asserts the
IRQ output if the DSRIE bit in the SIER is set.
The MPCC has three vector registers: Receiver Interrupt Vector
Number Register (RIVNR), Transmitter Interrupt Vector Number
Register (TIVNR), and Serial Interrupt Vector Number Register
(SIVNR).The receiver interrupt has higher priority over the
transmitter interrupt, and the transmitter interrupt has priority over
the serial interface interrupt. For example, if a pending interrupt
request has been generated simultaneously by the receiver and
the transmitter, the Receiver Interrupt Vector Number (RIVN) is
placed on 00-07 when acknowledged by the MPU. Upon completion of the first interrupt request cycle (which clears the receiver
interrupt), IRQ will remain low to start the transmitter interrupt
cycle. IRQ is negated by clearing all bits set in a status register
that could have caused the interrupt.
When the RSYN bit in the RCR is setto 1, the frame synchronization signal ~N) in the receiver is output on the DSR pin. In
this mode, DSR output low indicates detection of SYN in BSC
or COP, or an address match in BOP.
DTR (Data Terminal Ready) Output
The DTR outpuUs general purpose in nature and can be used
to control switchin.Q of theDCE. The DTR output is controlled by
the DTRlVl bit in the SICA.
TxC (Transmitter Clock) Input/Output
The transmitter clock (TxC) may be programmed to be input or
an output. When the TClKO control bit in the CCR is set to a
1, the TxC pin becomes an output and provides the DCE with
a clock whose frequency is determined by the internal baud rate
generator. When the TClKO control bit is reset, TxC is an input
and the transmitter shift timing must be provided externally. The
TxD output changes state on the negative-going edge of the
transmitter clock. In the asynchronous mode when TClKO ~ 0
in the CCR, the TxCinput frequency must be two times the
desired baud rate.
A timing diagram for the interrupt. acknowledge sequence. is
shown in Figure 15.
SERIAL INTERFACE
The MPCC is a high speed, high performance device supporting
the more popular bit and character oriented data protocols. The
lower speed asynchronous (ASYNC) and isochronous (ISOCH)
modes are also supported. An on-chip clock oscillator and baud
rate generator provide an output data clock at a frequency of DC
to 4 MHz. The clock can also be used in the ASYNC mode to
provide a receive clock for the incoming data. The serial interface consists of the following signals:
TxD (Transmitted Data) Output
The serial data transmitted from the MPCC is coded in NAZ or
NAZI (zero complement) data format as selected by the NAZI control bit in the SICA.
RTS (Request to Send) Output
The RTS output to the DCE is controlled by the RTSlVl bit in
the SICR in conjunction with the state of the transmitter section.
When the RTSlVl bit is set to 1, the RTS output is asserted.
When the RTSlVl bit is reset to 0, the RTS output remains
asserted until the TxFIFO becomes empty or the end of the
message (or frame), complete with CRC code if any, has been
transmitted. RTS also is negated when the RTSlVl bit is reset
during transmitter idle, or when the RESET input is asserted.
RxC (Receiver Clock) Input
The receiver latches data on the negative transition of the RxC.
RxD (Received Data) Input
The serial data received by the MPCC can be coded in NRZ or
NAZI data format. The MPCC will decode the received data in
accordance with the NAZI control bit setting in the SICA.
CTS (Clear to Send) Input
Serial Interface Timing
The CTS input signal is normally generated by the DCE to indicate whether or not the data set is ready to transmit data. The
CTST bit in the SISR reflects the transition status of the CTS input
while the CTSlVl bit in the SISR reflects the current level. A
positive transition on the CTS pin asserts
if the CTS IE bit
in the SIER is set. The CTS input in an inactive state disables
the start of transmission.
The timing for the serial interface clock and data lines is shown
in Figure 18. The MPCC supports high speed synchronous operation. As shown, the TxD output changes with the negative-going
edge of TxC and the received data on RxD is latched on the
negative edge of RxC. This assures high speed two-way operation between two MPCCs connected as shown in Figure 17.
iRa
DCD (Data Carrier Detect) Input
For low speed operation between the MPCC and a modem or
R5-232C Data Communications Equipment (DCE), an inverter can
be used in the TxC output lines as shown in Figure 17. RS-232
and RS-423 (covering serial data interface up to 100K baud)
require that data be centered ± 25% about the negative-going
edge of the RxC. This criteria is met for frequencies up to 1.25
MHz using the inverter. Use of the inverter also allows MPCC
to MPCC operation up to 2.17 MHz.
The DCD input signal is normally generated by the DCE and indicates that the DCE is receiving a data carrier signal suitable for
demodulation. The DCDT bit in the SISR reports the transition
status of the DCD input while the DCDlVl bit in the SISR contains the current level. A positive transition on the DCD pin asserts
the IRQ output if the DCD IE bit in the SIER is set. A negated
DCD input disables the start of the receiver.
1-99
0
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
SERIAL COMMUNICATION MODES
AND PROTOCOLS
tion. The character assembly process does not start if the start
bit is less than one-half bit time. Framing and parity errors are
detected and buffered along with the character on which errors
occurred. They are passed on to the RxFIFO and set appropriate
status bits in the RSR when the character with an error reaches
the last RxFIFO register where it is ready to be transferred onto
the data bus via the RDA.
ASYNCHRONOUS AND ISOCHRONOUS MODES
Asynchronous and isochronous data are transferred in frames.
Each frame consists of a start bit, 5 to 8 data bits plus optional
even or odd parity, and 1, 1'/2, or 2 stop bits. The data character
is transmitted with the least significant bit (lSB) first. The data
line is normally held high (MARK) between frames,' however, a
BREAK (minimum of one frame length for which the line is held
low) is used for control purposes. Figure 4 illustrates the frame
format supported by the MPCC.
Isochronous Receive
In the isochronous (ISOC) mode, a 1 times clock on RxC is
required with the data on RxD and the serial data bit is latched
on the falling edge of each clock pulse. The requirement for the
detection of a valid start bit, or the beginning of a break, is satisfied
by the detection of a high-ta-Iow transition on the serial data input
line. Error detection and status indication are the same as the
asynchronous mode.
Asynchronous Receive
In the asynchronous (ASYNC) mode, data received on RxD occurs
in three phases: (1) detection of the start bit and bit synchronization, (2) character assembly and optional parity check, and
(3) stop bit detection. The receiver bit stream may be synchronized by the internal baud rate generator clock or by an external
clock on RxC. When RClKIN in the CCR is set to 0, an external
clock with a frequency of 16, 32, or 64 times the data rate
establishes the data bit midpoint and maintains bit synchroniza-
ASYNCHRONOUS FRAME FORMAT
I
START
.
---, --,-- .,..--...,
I ___ ~~ _____ .L
I ___ L
I __ ..JI
I
IL..l_L_
I I
__ L
,-_~I
I
In asynchronous and isochronous transmit modes, output data
tansmission on TxD begins with the start bit. This is followed by
the data character which is transmitted lSB first. If parity generation is enabled, the parity bit is transmitted after the MSB of the
character.
r - - T - ---r(- -
--,
DATA
Asynchronous and Isochronous Transmit
1
lBS
I
I
I...
5 TO 8 BITS
MSS
1 PARITY 1 STOP
(OPT)
(1, 1'12, OR 2 SITS)
I
.1
ISOCHRONOUS FRAME FORMAT
elK
DATA
I
j--l----((-----l--l-- I
1 __
!-._ _......
1
START
I
lBS
I
I...
Figure 4.
__
-t'r----.J..--.J..--.J
I MSB I ~~:~~Y I
5 TO 8 BITS
.1
Asynchronous and Isochronous Frame Format
1-100
,-,I
I
L_.....l._
STOP
(1 OR 2 BITS)
I
R68560, R68561
Multi..protocol Communications Controller (MPCC)
SYNCHRONOUS MODES
The end of the frame is determined by the detection of the closing
Flag special character which is the sam.e is the opening Flag.
In synchronous modes, a one-.imes clock is provided along with
the data. Serial output data isshl~ out and input data is latched
on, the falling edge of the clock. .
Witl'\ the control options offered by.the MPCC, commonly used
bit oriented protocols such as SOLO, HOLC and X.25 atandards
can be supported. Figure 6 compares the requirements of these
options.
BIT ORIENTED PROTOCOLS (BOP)
In bit oriented protocols (BOP), messages (data) are transmitted
and received in frames. Each frame contains an opening flag,
address field, control field, frame check sequeliCe, and a closing
lIag. A frame may also contain· an infOrl1'l8tion field: (See FlQure 5).
BOP Receiver Operation
In BOP, the receiver starts assembling characters and accumulating CRC immed'l8tely after the detection of a Flag. The receiver
alsO continues to search for additional Flag, or Abort, characters
on a bit-by-bit basis. zero deletion is implemented in the Receiver
ShlftR8gister after the FI8g detection logic and befOre the CRC
circuitry. The receiver recognizes the shar8d lIag (the closing flag
for one frame serves as the openil'lg lIag fOr the next frame) and
the sliared zero (the ending Oof a closing nag serves as the beginning 0 of an opening flag forming the pattern
"011111101111110."
The .opening flag is a special character whose bit pattern is
01111110. It marks the frame boundaries and is the Interframe
fill character. The addresS field of a frame contains the address
of the seCondary station which is receiving or responding to a
command. The address field may be one or more bytes 10ng:The
address field can be extended by setting the AOOEX bit to a 1
in PSR1. ·In this case, the address field will be extended until the
occurrence of an address byte with a 1 in bit O. Up to two bytes
of the address field may be automatically checked when the
MPCC .Is programmed to .be a secondary station in BOP. An
automatic check for global (11111111) or null (00000000) address
is also made. The controilleid of one or two bytes is transparent
to the MPCC and sent directly. to the host without interpretation.
Character assembly and CRC aCcumulation are stopped when
a closingFlag·or Abort is detactilcl. The CRC aCcumulation includes all the characters between the opening Flag and the.closing Flag. The contents of the CRC register are che.cked at the
close of a frame and the C/PERA bit in the ASA is updated. The
FCS and the Flag are not passed on to the RxFIFO.
The optional information field consists of 8-bit characters. Cyclic
redundancy checking is used for error detection and the CRC
remainder resulting from the calculation is transmitted as the
frame .check sequenCE! field. For BOP, the polynomial X16 + X12
+ X5 + 1 (CRC-CCITT) should be used, i.e., selected in the
CRC SEL· bits in the ECR. The registers representing the
CRCCCITT polynomial are generally preset to 8)11 s, and the 1.s
complement of the resulting remainder is transmitted. (See
X.~ Recommendation.)
If the Flag is a closing flag, checks for short frame (no cont~1
field) and CAC error conditions are made and the appropriate
status is updated. When an Abort (seven 1s) is detected, the remaining frame is discarded and the RA/B bit is set in the.RSA.
When a link idle (15 or more consecutive 1s) is detected, the RIOLE status bit is set in the RSA. The zeros that have been inserted
to distinguish data from special characters are detected. and
deleted from the data stream befOre characters are assembled.
The MPCC programmed as a secondary station provides
automatic; address . matChing of up to two bytes. If there is no
aqdress match, the receiv,r (secondary .station) ignores the
remainder of the frame by searching fOr the Flag. If th,re is a
match, the addresS bytes are transferred to the AxFIFO as they
are assembled.
.
zero insertion/deletion is employed to prevent valid frame data
from l?eing QOnfus8d with the spacial characters. A 0 Is inserted
by the trlinsmitter after fi.lery fifth consecutive 1 in the data stream.
These inserted zeros are removed by the receiver to restore the
data to its original fOrm. The inserted zeros are not included in
the CRC calculation.
I
FLAG
01111110
ADDRESS
I
10RN
BYTes
'
...
I
CONTROL
10R
2 BYTES
I
INFORMATION
FCS
~
2 BYTES
BYTES
FLAG
01111110
(OPTIONAL)
-
Figure .5. Bit Oriented Protocol (BOP) Frame Format
IBM SDLS FRAME FORMAT
FLAG
ADDRESS
CONTROL
FCS
FLAG
01111110
1 BYTE
1 BYTE
N BYTES
2 BYTES
01111110
ADDRESS
CONTROL
INFORMATION
FCS
FLAG
N BYTES
10R
2 BYTES
N BYTES
2 BYTES
01111110
·INFORMATION
. ADCCPIHDLC FRAME FORMAT
FLAG
01111110
Figure 6.
Implemented Bit Oriented Protocols
1-101
1
Multi~Protocol
R6856Q, R68561
non-transparent EBCDIC and for transparent ASCII coded
messages.. VRC/LR9 should be selected for non-transparent
ASCII ..coded m~ages, .asc .l1Jessages are formatted using
defined data-link control charaCters. Data-link control characters
generated and recognized by the MPCC are listed in Table 4.
For the control field, one or two bytes are assembled and passed
on to the RxFIFO depending on the state of the extended control field bit.
If, the CFCRC bit in the ECR is set to 1, anintermedi~t.e CRC
check will be made after the address and .control field. The Frame
Check Sequence is still calculated over the remainder of the
frame.
Table 4.
BSC Control Sequences-Inclusion
in CRC Accumulation
ASCII
EBCDIC
Byte 1
Byte 1 Byte 2
Bvte,2 ComlJlBnd
ColJllJland
SYN
SYN
32"
16"
01
01
SOH
SOH
02
STX
STX
02
ETB
17
EOB (ETS)
26
ETX
03
ETX
03
ENQ
.05
ENQ
20
OLE
10
OLE
10
ITB
IF
ITB.
1F
EOT
EOl'
04.
37
ACKW
10
ACKO
10
70
30-37
NAK
15
ACK 1
10
61
.
3B
WACK
10
NAK
30
FM
10
3C
WACK
10
6B
RVI
10
7C
Nqte: "Programmable
-,
." .
BOP Transmitter Operation
In BOP, the TxFIFO can be preloaded through the TDR while
the transmitter is disabled (TEN = 0 in the TCRl.When the
transmitter .is enabled (TEN = 1 in the TCR), the leading Flag
is automatically sent priOr to transmitting data from tl'le TxFIFO.
The TDRA bit is set to. 1 in the TSR as long as TxFIFO is not
full. If an underrun occurs, the.TUNRNbit in the rS.R is set to
a 1 and an Abort (1111.1.111) is transmitted followed by continuous
Flags or marks until a new seque!1ce is initiated.
The TLAST bit in the TCR must be set prior to loading the last
character of the message to signal the transmitter to append the
two-byte Frame Check Sequence (FOS) following..the las!
character. If the transmitter DMA mOde is selected (the TDSREN
bit set to 1 in the TCR)the TLAST bit is set by the OON'E Signal
from the DMA~:' .
,
A message may be terminated at anytime by setting the. TABT
bit in the TCR to 1. This causes the transmitter to send an Abort
character followed by the remainder of the current frame data·
in the TxFIFO.
'
The serial data from the Transmitter Shift Register is continuously
monitored for five consecutive 1s, and Ii 0 is inserted in the data
stream each time this condition occurS (excluding Rag and Abort
characters),
.
CRC accumulation begins with the first non-Flag character and
includes all subsequent characters. The CRC remainder is
transmitted as the FCS following the last data character. If the
CTLCRC bit in the ECR is set to 1, an intermediate CRC
remainder is appended after the Address and Control field. The
final Frame Check Sequence is calculated over the balance of
the frame.
BISYNC (BSC)
The structure of messages utilizing the IBM Binary Synchronous
Communications (BSC) protocol, commonly called Bisync, is'
shown in Figure 7. The MPCC can process both transparent and
nontransparent messages using either the EBCDIC or the ASCII
codes. The CRC-16 polynomial should be selected by setting the
appropriate CRCSEL bits in the ECR for both transparent and
LEADING PAD
1 BYTE
(AR1)
SYN
1 BYTE
(AR2)
SYN
1 BYTE
(AR2)
Figure 7.
Communications Controller (MPCC)
-
--
-
-
-
-
-
A heading is a block of data starting with an SOH and cOntaining
one or more characters that are used for message control'(e.g.,
message identification, routing, and priority). The SOH initiates
the block-check-dlaracter (BCC) accumulation, but is not included
in the accumulation. The heading is terminated by STX when it
is part of a block containing both heading and text. Ii. block containing only a heading is terminated with an ITB or an ETB
followed by the BCC. Only the first SOH or STX in a transmission block following a line turnaround causes the Bec to reset.
All succeeding STX or SOH characters are included in the BCC.
This permits the entire transmission (excluding the firsi SOH or
STX) to .be blo,ck-checked.
The text data is transmitted in complete units called meSsages,
which are initiated by sti and concluded with ETX. A message
can be subdivided into smaller blocks for ease in proceSSing and
more efficient error control. Each block starts with STX and ends
with ETB (except for the last block of a message, which ends with
ETX). A single transmission can contain any number of blocks
(ending with ETB) or messages (ending with ETX). An EOTfollowing the last ETX block indicates a normal end of transmission.
Message blocking without line turnaround can be accomplished
by USing ITB (see the Additional Data Link Capabilities section,
IBM GA 27-3004-2).
BODY
I
BSC Block Format
1-102
BCC
TRAILING
PAD
11111111
:II
Q)
CO
CONTROURESPONSE BLOCKS:
U1
CD
ENQ
ADDRESS
F'
FOLLOWINGPAD
:II
Q)
CO
U1
....
Q)
i:
c
2f.
•
"'U
NEGATIVE ACKNOWLEDGEMENT
~n
HEADING AND TEXT BLOCKS:
RESET BCC
~
o
c.>
ILE::~NG I
SYN
SYN
-j ,
SOH
'j
INCLUDED IN BCC
'HEAi:NG '
ETB
BCC
J~~
2(')
o
3
3
HEADING ONLY
RESET BCC
'I
----INCLUDED IN BCC
'-------'----'------'---'-----'------j"":'NG
1
on
I.,.
,~
1
c
rlNCLUDED IN B C C - I
1
~---'-T
I----yBCC----,I----,~~L~A~-1
ETx
I------T
j-
L-~-A-DD-IN-G'I-S-Y-N--r-S-Y-N---'---DL-E-·I-ST-X-....;I'----T-l;,
'I
1
~
as·
~
NONTRANSPARENT HEADING AND TEXT
RESET BCC---t'NCLUDED IN BCCi
~
(1;-
fI)
'I
INCLUDED IN BCC'
f]
-2...
~
SY.
1
:
TRANSPARENT TEXT
.c<'
m
1
.00
1=-1
• OLE EXCLUDED FROM Bec CALCULATION
CD
3:
"'U
J;
Figure 8.
BSC Messagjil Format Examples
B
Multi-Protocol Communications Controller {MPCCj
R68560, R68561
Two modes of data transfers are used in BSC. In non-transparent
mode, data link control characters may not appear as text data.
In transparent mode, each control character is preceded by a data
link escape (OLE) character to differentiate it from the text data.
Table 5 indicates which control characters are excluded in the
CRe generation. All characters not shown in the table are included
in theCRC generation. Figure 8 shows various formats for
Control/Response B.locks and Heading and Text Blocks.
Table 5.
BSC Control Sequences In CRC Accumulation
is detected only the EOF bit is set. If the closing character was
an ITB, BCC accumulation and character assembly starts again
on the first character following the BCC.
BSC Transmitter Operation
BSC transmission begins with the sending of an opening pad
(PAD) and two sync (SYN) characters. These characters are programmable and stored in AR1(PAo) and AR2(SYN). SOH or STX
initiates the block-check-character (BCC) accumulation. An initial
SOH or STX is not included in the BCC accumulation. Should
an underrun condition occur, the content of AR2 (normally SYN
character) is transmitted until new characters become available.
The message is terminated by the transmission of the BCC
followed by a closing pad when an ETB, ITB, or ETX is fetched
from the TxFIFO. The clOSing PAD is generated by the MPCC.
Inclusion
Included In CRC Accumulation
Charactar CIt Sequence
TSYN
TSOH
TSlX"
TETB
TETX
TOLE
Yes
No
-
-
-
ere
ElX
(OLE)OLE
OLESYN
OLESOH
OLESlX
OLE
OLE
OLE(OLE)
In transparent mode, the BCC accumulation is initiated by OLESTX and is terminated by the sequences OLE-ETX, oLE-ETB,
or OLE-ITB. See Table 5 for character sequence and inclusion
in CRC accumulation. If an underrun occurs, OLE-SYN characters
will be transmitted until new characters are available in the
TxFIFO, ETC, ETX, ITB, or ENQ with a TLAST tag is treated as
a control character and the MPCC automatically inserts a OLE
immediately preceding these characters, OLE-ETB, OLE-ETX,
OLE-ITB, or OLE-ENQ terminates a block of transparent text, and
returns the data link to normal mode. BCC generation is not used
for messages beginning with characters other than SOH, STX,
OLE-SOH, or OLE-STX. On all message types, if the TSYN bit
is set to 1 in the TCR, a SYN-SYN (OLE-SYN sequence on
transparent messages) sequence is transmitted before the next
character is fetched from the TxFIFO.
"If not preceded within the same block by transparent heading
information.
BSC Receiver Operation
Character length defaults to eight bits in BSC mode. When ASCII
is selected, the eighth bit is used for parity provided that VRC/LRC
polynomial is selected. Character assembly starts after the receipt
of two consecutive SYN characters. Serial data bits are shifted
through the Receiver Shift Register into the Serial-to-Parallel
Register and transferred to the RxFIFO. The ROA status bit in
the RSR is set to 1 each time data is transferred to the RxFIFO.
The SYN character in non-transparent mode and OLE-SYN pairs
in transparent mode are discarded.
CHARACTER ORIENTED PROTOCOLS
The character oriented protocol (COP) option uses the format
shown in Figure 9. It may be used for various character oriented
protocols with 5-8 bit character sizes and optional parity checking. The input data is checked on a bit-by-bit basis for a pair of
consecutive SYN characters to establish character synchronization. These SYN characters are discarded after detection. The
PAD and SYN characters maybe 5-8 bits long and are user programmable as stored in AR1 and AR2, respectively.
The receiver starts each block in the non-transparent mode. It
switches to transparent mode if a block begins with a OLE-SOH
or OLE-STX pair. The receiver remains in transparent mode until
a oLE-ITB, oLE-ETB, OLE-ETX or oLE-ENQ pair is received.
accumulation begins after an opening SOH, STX, or OLESTX. SYN characters in non-transparent mode or OLE-SYN pairs
in transparent mode are excluded from the BCC accumulation.
The first OLE of a OLE-OLE sequence is not included in the BCC
accumulation and is discarded. The BCCis checked after receipt
of an ITB, ETB, or ETX in non-transparent mode or OLE-ITB, oLEETB, oLE-ETX in transparent mode. If a CRC error is detected,
the C/PERR and EOF bits in the RSR are set to 1. If no error
sec
LEADING PAD
5-8 BITS
(ARt)
SYN
5-8 BITS
(ARt)
SYN
5-8 BITS
If parity checking is enabled the characters assembled after
character sync are checked for parity errors. If STRSYN is set
in the RCR, all SYN characters detected within the message will
be discarded and will not be passed on to the RxFIFO. If STRSYN
is reset, SYNs detected within the message will be treated as data.
MESSAGE
~-------5-8 BIT CHARACTERS-------~
(AR2)
Figure 9.
Character Oriented Protocol Format
1-104
:D
C»
Q)
CIt
C»
$'
:tI
C»
Q)
A1-A23
I'"
CIt
C»
....
00015
R/W
L-
.!:Q!
r--
UDS
AS
DTACK
SA
Bii
R6BOOO
MPU
BGACK
I--
~
s:
c
74LSl48
~II ~II~II~II~II ~
FCO
-
~
'FC2
.--
~
~ I~I
~A3
... 2
A1
B
Vl
A
Y2
G2A
~G2B
Y5
Y6
REal
i"
!:
"~
~
ACK1
n
RDSA
AeKa
MC66440
DMAC
MEMORY
2-
DACK
_
aTC
DONE
o
o
R6aS61
",pce
l~
Y3
~.
1]1
REaO~TDS.R
<0
clio
~II ,,~
~
!Q
...
74lS138
~llill~!I~11 ~
~
mo
El
::;
r~IHIT~
~I
=
IACK5
lACK
IACK6
3
3
IRa
EXTAl
+5V~~
SYSTEM CLOCK
;!
c
::I
n"
a
0"
::I
In
oo
~
~
a
a
CD
...
1o
NOTE: UDS MAY BE TIED LOW (GROUND).
Figure 10.
.n
Typical Interface to 68000·Based System
II
::D
0)
OC)
en
0)
5'
::D
0)
OC)
AO-A1P
00-07
Me6Saoa
r----
AS
r--J-~
r----
~
BG
BGACK
-
I:
0
~
~
iPLO
IPL1
"LS1"
~
~
r""fc2
-
'----
DS
OR
I~
-.a.
-
DTACK
MPU
en
0)
-
R/W
~
r--T
~I ~I
IR05
CJI~
(I)
CJ
~I ~
":
~I ~I
<0
~06
El
~
g:1 ~I~I
r---'-
5/
fl!
Jl
?'
"
~
"~ ~"I
0>
c
A3
A2
~
B
A
Al
r------'-
ACK1
YO
r-v2
j
74LSl38 ~
G2B
lK
+5"~Gl
+.
YB
~
I~
r-;;:;-
~
"
~I
~I
a
j
WI
» »
C>
l>~"
I~~~
0) JJ
(/)
II
0
~l ~
3:
c
;:;
~
"
"tI
a
TOSA
~
DONE
~
YI
G2A
Lc
ACKO
MC68440
DMAC
l>
'"
'
~!
(II
0
REOO
MEMORY
J
01
REal
o
~I
C>
~
'~'
~
;~
l~'
Y
BUS
.--
6'
ROSA
(')
DACK
2-
oo
A6aS60
MPCC
~,
gt,
-o--
Rx TIMING (DO)
Rx DATA (BB)
LOW SPEED (RS·232) INTERFACE
Figure 17. Serial Interface
1·110
Multi..;ProtoC'el Communications Controlle'r (MPCC)
R68560, R68561
.
.
HIGH SPEED APPLICATION
TxC/RxC
TxD/RxD
LOW SPEED APPLICATION (R8-232 COMPATIBLE)
j~~-1
TxC
-
TxD
DATA A
t
I
j,....----:
'-----I
.... - - - - - "
~----~--------~
r-~--------------,
DATAC
RxC (TxC)
Figure 18. Serial Interface Timing
RxD
________________________
J/I~
_____________________
TxD
NOTE:
TIMING MEASUREMENTSS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE
OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.
Figure 19. Serial Interface Echo Mode Timing
1·111
Multi·Protocol Communications Controller (MPCC)
R68560, R68561
AC CHARACTERISTICS
(Vee = 5.0 Vdc ±5"Al, Vss = 0 Vdc, TA
OOC to 70°C)
Max
Unit
ns
30
-
!clDAl
0
60
ns
CS, OS Low to Data Valid
tSLDV
0
140
ns
5
CS, OS High to Data Invalid
tSHDXR
10
150
ns
6
CS, OS High to DTACK High
tSHDAT
0
40
ns
7
CS, OS High to Address Invalid
tSHAI
20
8
CS, OS High to RIW Low
tSHRl
20
-
ns
Number
Parameter
Symbol
Min
1
AIW High to CS, OS Low
t RHSl
0
2
3(1)
Address Valid to CS, OS Low
tAVSl
CS Low to DTACK Low
4(1)
ns
ns
AIW Low to CS, OS Low
~lSl
0
-
ns
10
CS High, OS High to AIW High
tSHRH
20
ns
11
Data Valid to CS, OS High
tovsH
60
-
12
CS, OS High to Data Invalid
tSHOXW
0
-
ns
17
DTC Low to OS High
!cLSH
60
-
ns
18
DACK Low to Data Valid, DONE Low
tALDV
0
140
ns
9
ns
19
OS High to Data Invalid
tSHDXDR
10
150
ns
21
Data Valid to OS High
tovsH
60
-
ns
22
OS High to Data Invalid
tSHOXDW
0
-
ns
25
lACK Low to DTACK Low
tlALAl
0
40
ns
26
lACK, OS Low to Data Valid
tlALOV
0
140
ns
27
OS High to Data Invalid
tlSHOI
10
150
ns
28
lACK High to DTACK High
tlAHOAT
0
40
ns
30
AxC and TxC Period
!cp
-
ns
31
TxC Low to TxO Delay
tTClTO
0
200
ns
32
AxC Low to RxD Transition (Hold)
tRClRO
0
-
ns
33
RxD Transition to AxC Low (Setup)
tRDRCL
30
-
ns
34
RxD to TxD Delay (Echo Mode)
tROTO
-
200
ns
35
AIW Low to DTACK Low (Setup)
tRLAL
0
ns
36
DACK High to DONE High
tAHOH
0
-
248
ns
Note:
1. For read cycle timing, the MPCC asserts DTACK within the MPU S4 clock low setup time requirement and establishes
valid data (Data In) within the MPU S6 clock low setup time requirement.
1·112
. .
.
Multi-Protocol Communications Controller. c(MPCC)
R68560,. R68561
ABSOLUTE MAXIMUM RATINGS·
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 to +7.0
V
Input Voltage
VIN
-0.3 to +7.0
Operating Temperatura Rlinge
Til
Storage Temperature
T STG
Parameter
o to
'NOTE: Stresses above those listed under ABSOLUTE MAX·
IMUM RATINGS may cause permanent dhmagetO the device.
This is.8 stress rating orly and functional operation of the device
at these or any other conditions above those indicated in other
sections of this document is not implied. Exposure to absolute
maximum. rating conditions for extended periods may affect
device reliability.
V
·C
+70
·C
-55 to +150
THERMAL CHARACTERISTICS
Pa.rameter
Symbol
Thermal Resistance
Ceramic
Plastic
8JII
Value
Ranng
·CIW
50
68
OPERATING CONDITIONS
Parameter
Range
Vee Power Supply
5.0V:l:5%
Operating Temperature
o·e to 70·C
DC CHARACTERISTICS
(Vee" 5.0 Vdc ±5%, Vss = 0 Vdc, TA ..
ooe to 70 e unless otherwise noted)
0
Symbol
Min
Mu
Unit
Input High Voltage
All Inputs
VIH
2.0
Vee
V
Input Low Voltage
All Inputs
VIL
-0.3
+O.B
V
Inpu!...Leakaga Current (YIN = 0 to 5.25V)
AIW,RESET,CS
liN
-
10.0
pA
VIN
0 to 5.25V
Vee = 0
Th!!!!"State (Off State) Input Currant (YIN = 0.4 to 2.4)
IRQ,DTACK,OO-D15
TTSI
-
10.0
pA
VIN = 0.4 to 2.4V
Vee - 5.0V
Output High Voltage
RDSR, TDSR, IRQ, DTACK, 00-015, DSR, DTR, RTS,
TxD, TxC
VOH
Vss + 2.4
-
V
Vc6 = 4.75V
ILOAO .. -4OOpA
C LOAD .. 130 pF
V OH
Vss + 2.4
-
V
Vee = 4.75V
ILOAD = 0
C LOAD .. 30 pF
0.5
V
Vee =.4.75V
ILOIlO = 3.2 rnA
Paramater
BCLK
Output Low Voltage
RDSR, mSR. IRQ. DTACK 00-015. DSR. DTR. RTS,
TxD, TxC. BCLK,
VOL
-
Tnt Condltfons
=
Vee .. 4.75V
ILOAO = B.B mA
DONE
Intarnal Power DiSsipation
PINT
Input Capacitance
C IN
1·113
-
1
W
TA - 25·C
13
pF
VIN = OV
TA = 25.·C
f = 1 MHz
R6856~,
R68561
Multi·ProtocGI·Comrnunications Controller.(MPCC)
PACKAGE'DIMENSIONS
48-PIN CERAMIC DIP
[:0:0
MtLUMETEAS
~I==~~~==~l
"
~.
JL D
I
-lG 1-
,A 6Q.36
61.57
2.376
2.424
B 14.63
15.34
0.576
0.604
FlI-.j\r
..
-If.- J
i-
L
MAX
3.05
4.~
·0-.120
0.160
D
0.381
0.533 0.015
0.021
F
0.762
1.397 0.030
0.055
a
-2.54BSC
0.203
2.~ ·~.19.
L
14.99
II
0"
N
Hi.55
10"
1.016
O.l00BSC
0.330 0.004
0.013
,0.100
0.'165
0.590
0.616
(1'
10"
1.52' 0.040
·1·:·
0.606
M
--l
MlLUMETERS
INCHES
011
MIN
.MAX
MIN
MAX
A
51~28
52.32
2.040
2.060
B
13.12
14.22
0.540
0.580
C
3.55
5.08
0.140
0.200
D
0.36
0.51
0.0"4' 0.020
f
1.02
1.52
0.040
G
2.54
H
1-114
MIN
C
K,
~1+H-H!+:lIi-lfH-Ytt..i
4O-PIN PLASTIC DIP
MAX
J
----A----l
INCHES
DIM MIN
esc
T 2.1~
U~5
0,100
0.065,
0.060
esc
o.aes
J
0.20
0.30
0.008
0.012"
K
'3.05
3.56
0.120
0.140
L
II
15.24 esc
..,.
10"
N
0.51
1.02
0.800 esc
.,.
10"
0.020
0.040
I"
,
R68802
'1'
Rockwell
R68802
LOCAL NETWORK CONTROLLER (LNET)
PRELIMINARY
DESCRIPTION
FEATURES
The RS8802' Local Network Controller (LNET) implements the
IEEE 802.3 CSMNCD Access ~ethod local network standard.
More generally, it is designed to support a variety of local network designs with varying performance requirements.
• Serial data rates as high as 10M bps
• Compatible with a variety of 8- or 1S-bit processors and DMA
controllers
• Meets the IEEE 802.3 (as well as Ethernet') specifications for
local networks
• Interfaces to SEEQ 8002 Manchester Code Converter (MCG)
• Programmable interframe wait times for smaller topologies
and lower data rates
The basic function of the LNET is to execute the CSMNCD
algorithm, perform parallel-to-serial and serial-to-parallel conversions of the 10M bps packet data stream, and assemble and
disassemble·the packet format. In addition, the LNET provides
the necessary asynchronous handshake signals to the S8000
family processors, the required DMA interfaces, and the proper
interface to the Manchester Interface (MI) component(s) used
to connect the LNET to an IEEE 802.3 defined Media Attachment Unit (MAU).
• CSMNCD algorithm:
-Wait before transmit
-Jam on colliSion
-Binary exponential backoff
•
•
•
•
•
•
The controller can interface data terminal equipment to local
networks with differing performance requirements. At the high
end, the R68802meets the IEEE 802.3 10M bps speCification
and supports the implementation of ISO layers one and two. For
low cost networks, the controll",r can be run at greatly reduced
data rates and inexpensive system components (drivers, cables,
etc.) may be selected.
Programmable 2- or 6-byte address recognition
Supports three modes of node self-test
Programmable disable on reception
32-bit CRC generation and reception
Broadband apPlications
TTL compatible I/O
• 40-pin DIP
• Single 5V power supply
• R68802 is a trademark of the Rockwellintemational Corporaffon.
The LNET controller implements a protocol known as Carrier
Sense Multiple Access with Collision Detection (CSMNCD),
which allows. multiple Data Terminal Equipment to share the
same communication medium without the need for a central
arbiter of medium utilization.
•Et hemet is s' trademark
'of the Xer:ox Corporation.
VCC
Ethernet nodes needing to transmit wait exactly 9.6 I-'S before
transmitting data to provide recovery time for other controllers
and the cable itself..If a collision with another station is detected,
the transmission is aborted and a jam signal transmitted to alert
other nodes. Following a jam, the station waits a random amount
of time based on a Binary Exponential Back-off algorithm before
retransmitting. Repeated collisions result in repeated retries and
an increase in the randomly selected time interval to improve
trafficking.
RJW
RESET
DO
01
02
03
04
05
D6
07
D8
D9
ORDERING INFORMATION
010
011
012
013
014
015
Part Number
R68802 _ Temperature Range: O°C to 70°C
CS
LpaCkage:
C ~ Ceramic
P ~ Plastic
Mii:iFiEo
MAUAVAtL
ISOLATE
TXCLK
TXOATA
TXEN
SIGQUAL
SENSE
RXCLK
RXOATA
MILQOP
TXREQ
RXREQ
DiCK
DONE
IRQ
DTiCK
OS
lACK
GNO
R68802 Pin Assignments
Document No. 68650N07
1-115
Product Description Order No. 706
Rev. 2 January 1984
IRQ
lACK
TO-SERIAL
~TRANSMIT
REGISTER
,/\
lJ
en
....
PARALLEL-
INTERRUPT
INTERFACE
i
o
I\)
eRe
GENERATOR
....
TRANSMIT
MUX
~
TXDATA
--...
~
I
TRANSMIT
CONTROL
os
cs
iiiAcK
~
~
Ol
00-015
<=>
DACK
RxReQ
COUNTER
PAD
GENERATOR
PREAMBLE &
DELIMITEA
JAM
GENERATOR
GENERATOR
INTERFRAMe
DELAY
COUNTER
~
BINARY
EXPONENTIAL
BACK-OFF
CSMA/CD
CONTROL
COUNTER
r+-
14-
TXEN
SIGOUAl
SENSE
.1
BUS
CONTROL
INTERNAL DATA BUS
K
TXReQ
DONE
TRANSMIT
LENGTH
1
TXClK
TRANSMITIER
CLOCK
V
32-BYTE
TRANSMIT
FIFO
(TXFIFO)
1\
RJW
INTERNAL
~
EXTERNAL
DMAC
INTERFACE
~
7\
1\
r-
~l
1
V
1
32-BYTE
RECEIVE
CONTROL
RECEIVE
FIFO
(RXFIFO)
I)
ADDRESS
RECOGNITION
)
vi
RECEIVE
LENGTH
COUNTER
REGISTER
et
\I
INTERRUPT
STATUS
!MODE
COMMAND
--+
MAUFiEci
---... MiiQQp
---+ iSOLATE
(
MAUAvAiL
++-
J
SERIAL-TOPARALLEL
8
DELIMITER
RECOGNITION
RECEIVE
CRC
z
!.
:eo
""I
~
INTERNAL
RECEIVER
CLOCK
0lIl--
RXCLK
oo
:J
AXDATA
C;
CD
""I
rZ
Figure 1. LNET Block Diagram
--- ----
-- --
--
--
-!!J
Local Network Controller'.(LNET)
R68802
PIN DESCRIPTION
iACK-:-lnterrupt Acknowledge. The active low lACK input
i.ndicates that the current bus Cycle is ;1n interrupt ackn!;>w1edge
cycle. When lACK is asserted the LNET places an interrupt
vector on the lower byte (DO-D7) of the data bus.
Throughout the document, signals are:presented using the
terms. active and inactive or asserted and negated independent
of whether the signal is ~ive in the ~jgh-voltage state or low:
voltage state. (The active state of .eachlOgic pin is described
below.) Active low signals are cjenoted by a, !luperscript ~r.
R/W indicates a write is active low and a read active high.
DATA
aus
ASYNCHRONOUS
aus
CONTROL
lIMA
CONT....
INTERRUPT
CONTROL
{
{
{
{
QACK-DMA Acknowledge: The DAqi< low.input indicates
that the data bus has been acquired by the DMAC and that the
requested bus cycle is beginning.
DONE-Done. DONE is a bidirectional active .lOW signal. The
DONE signal·is asserted by the DMACwhen.the DMA transfer
count is exhausted,and there is-no more data to be transferred,
or is asserted by the LNET when either ttie last byte of receive
data is transferred or a collision is detected during a transmission.
iii
co
. RiW
6iiCK
iiEsET
.......
RESET-ReseL Tne active low. high impedance RESET input
initializes all LNET functions. RESET must be asserted for at
least 500 TXCLKs to initialize the LNET.
MANCHESTER
LNET
INTERFAcE
SENSE
RxiiiQ
RXCLK
DiCK
. RXDATA
iiOiii
iiit'OOP
Figure 2.
iRa
lACK
RXREQ-Receive DMA Request. When receive data becomes
available in the RXFIFO, ~ output is asserted and held
low for 16 (single address burst modeY DMAC cycles (16
sequential DACK pulses) or until the end of the receive block.
When the last data byte of the receive block is transferred.
DONE is asserted by the LNET with the last ..PACK strobe and
the negation of mmEO'. .
. .
vic
OND
LNET Input and Output Signals
TXREQ-Transmit DMARequest. Whe~ansmitter
Enable bit .is set in Command Register 1. TXREQ output is
asserted and held low for 16 (single address burst mode) DMAC
cycles (16 sequential DACK pulses) or until the end of the
transmit data block as signaled by the DMAC's assertion of
DO-D1S-Data' Lines. The bidirectional data. lines transfer'data
between the LNET and the MPU, rriemory or other peripheral
device. 00-015 are used when connected to the 16-bit 68000
bus and operating in the word mode. DO-D7.are used when connectedto the 16-bit 68000 bus or'the. 8-bit '68008 bus and
operating in ihe byte mode. The data bus is tri-stated when CS
is inactive. (See exceptions in DMA mode.)
iSON'E.
MI,-OOP MI Lqopbacj(. With an active MILOOP Oljtput. th~
MI shunts its LNET data-in path to its LNET data-out· patn,
effectively routing the LNET TXDATA output into the. LNET
RXDATA input. .
CS~hlp SelecL CS low selects the LNET for programm~
transfers with the host. The LNET is deselected when the CS
input is inactive in non-DMA mode. CS' must ~'decoded from
the address bus and gated with address strobe (AS).
RXDATA-.Recelve Data. The LNET receives serial data via
the RXDATA input. The RXDATA input is shitt6'd into the receiver
on the~sitive going edge of RXCLK.
RJW-ReadJWrlte. PiW controls the direct~n 9f data flow
through the bidirectional data bus by indicating that the current
bus cycle isa read (high) or write (low) cycle.
RXCLK-Recelve Clock. The free-running Receive Clock provides the LNET with receiwd data timing InformatiOn. The. positive (Iow-to-high) cloc.k trans.ition I'1nables an RXDATA bit into
thE!LNET.
DTAcK-Data Transfer Acknowledge~ .DTACKis an active
low output that signals the completion of the bus cycie. During
read or interrupt acknowledge cycles, DTACK is asserted by the
.LNET after data has been provided '~n the data bus; during
write cycles it is asserted after data has been accept!KIat the
data bus. A pull up resistor is required to maintain CTACK hign
between. bus cycles. ,
sENSE-Carrier Sense. The active high SENSE. input indicates the presence oldata on the RXOATAserlal input line.
SIGQUAL-8lgnal Quality•. The ~sertlon' of the active high'
SIGQUAL input, by the MI .indicates an error co~dition on t~e
medium. During the transmission mode the LNET Iryte[prets thiS
as. a collision.
DS":"'Data Strobe. During a write (RiW low), the DSpositive
transiilon latches data from the external data bus lines into the
LNEJ. During a read (RiiiJ high), DS low enables datalrom the
LNET onto data bus lines.
TXEN-Tra'nsmlt Enable. The active high TXEN output indicates to the MI that data is present on the TXDATA output.
IRQ-Interrupt Request. The active low IRQ output requests
interrupt service by the MPU.
1-117
Local Network Controller (LNET)
·R68802·
INITIALIZATION REGISTERS
TXDATA-Transmit Data. The LNET transmits serial data on
theTXOATAline. The TXOATA output changes on the positive
going'edge of TXCLK.
'
The initialization registers contain command informatiOn to configure the LNET for normaloperation. The registers are·the onebyte Mode Register (MR)', the one:byte Interrupt Vector Number
Register (IVNR) and the two-or six-byte Station Address Register (SAR): ThEise registers must be loaded upon RESET (either
caused by power Lip or initiated during normal operation) or upon
setting of the RESET bit in Command Register 1. Any of these
conditions reset the LNET by clearing the Mode Register, Station Address Register, Command Registers ,and Status Registers. The Interrupt Vector Number Register is auto-initialized to
its defauk value of $OF.
TXCLK-Transmit Clock. The Transmit Clock input is a freerunning clock supplied by the MI that provides both a system
clock and a means of shifting out serial data bit on the TXOATA
output line.
ISOLATE-Isolate MAU. The active low ISOLATE output' is
asserted when the Isolate bit in Command Register 1 is set to
1 to isolate the MAU from the medium. As long as ISOLATE is
low, the MAU is unable to transmit or.receive on the medium.
All initialization registers must be written to by the MPU'insli'uc, tion sequence immediately after a reset in,the mannerdecribed
below even if no data is phanged in a register. The number of
bytes written depends upon the number of bytes in the Station
Address as selected in bit 4 of the Mode Register.
MAUAVAIL-MAU Available. When the active low MAUAVAIL
input is asserted, the transmission algorithm can proceed.
M,AUREQ-MAU Request:The active low MAUREQ output is
asserted prior to transmission if MAUAVAIL is not asserted.
~-Power.
After the proper number' of write cycles have been comp·leted,
the LNET Initialized bit in Status Register 1 is set and further
MPU writes to ,the LNETwil,l address only Command Register
1 or Command Register 2. All MPU reads o,f the LNET after
initialization is complete will access only Status Register 1 or
: Status Register 2 .
5 V :!:: 5%.
GHD-Ground. Ground.
LNET REGISTERS
. The LNET contains three groups of registers accessible from
the MPU bus which iniiialize the LNET, control and monitor
LNET operation, and transfer data between the LNET and the
MPU bus. These registe~ groups; specific registers within each
group, and the size, access and mode of each register are listed
in Table 1.
Initialization Procedure for 16-Bit MPU Bus
Write cyclel--;write the Mode byte on the lower byte of the
d
t--~
Iii
8G
IGACK
MPU
.---
I..I"'~
IPL1
-~
t---7-
~
r-+
~1~KlliIH
n
IRQfi
~Q8
~
EI
~
;
~
;:
)0
-:-
§
T "~!
aa~l~
I
1;
ill:
' 1; ~iI ~
lII:
.me
A2
AI
.--C
8
A
L
V~
+5V
~
~
~
G2A
GI
L..--
~
VI
r-n-
,
II"
US
~I
III
IACKli
IACKI
i;1
III
MAUREQ
REOO
IXREO
REQ,
ACKO
ACKi
DOIIA
~~Ii~j
"J "
~~Ig
"
;
RXREQ
~ Jt.5ACK
~
iiiiiiE
, ;1
DONE
MAUAVAIL
_.
LNET
ISOLATE
TXCLK
TXDATA
TlCEN
SlGQUAL
SENSE
IRQ
RJCLK
RXDATA
lACK
iiiLliOP
SYSTEM CLOCK
I
1\..-
PCLO
!;
74UI38~
G28
"
gJ ~I
-
~~
MEMORY
A3
~
D
"
,.:1:1)"ml
~11
!~
I---
74LS1. ~
~
~
.
~~I
r
8
!!!.
z
!.
:e
o...
j;1
~
CLOCK
Ole
(')
o
a.
a
i"
...
Figure 4. Typical Interface to 611QOO.Based System
~
~
II
-
i
gg
o
~
AD-A19
DlI-07
r--
R/W
t-t--
LOS
t--.~
Ai
DTACIe
.....
BG
IGAeK
MPU
I"
14
~
~
a
~
f---i"r--=--
l,tO
;m
r"
7"l.S148~
;! .. l
~ fRo5
"
~06
~
r-
EI
.r-2-
iIIl
"P en
.
,.
9
TS
n~ ;
!'lIt'll
~
l
~'l'
A3
C
A2
B
A
AI
Lc
"t~! ~
~
:II
us
G2A
~
G28
VB
IK
+EiV --"Nv- G 1
'---
"~
DDMA
~I ~I
~
" "
lACKS
aI~1 ~
011
~
REGO
TXREQ
RE01
RXREO
MAUREQ
MAUAYAll
ISOLATE
ACKa~tt DACK
:t:?~
!!lml
TXCLK
I..... TXDATA
DON~
R6B8D.
r-!Z-
lXEN
LNET
SIGQUAL
T
SENSE
IRQ
RXCLK
RXDATA
lACK
lACKS
SYSTEM CLOCK
I
~I
t. )-
PCLO
74LS13B ~
~
~~w
~I
G.
r - - t-=va
'"'*-§-
t l: "ml~
~
",Iiel
6......
MEMORY
!!l
.
j
,. t'll
!~;
r--
r--
....
....
t-- ~
j
BR
~
J;I
MILoa.
.....
r
8
!!.
z
!
=e
o
~
~
CLOCK
(')
DSC
o
Figure 5.
Typical Interface to 68008-8ased System
a
a
CD
~
r
Z
~
Local Network Controller (LNET)
R68802
0
.
~
\:J
~
~
~~
..lr-
~~
It-
RXCLK
..... ....--
~
RXDATA
j
SENSE
j~
~
...-
~"~
j~
~"-
i'iiQ
os
NOTE: Timing measurements are referenced to and from a low voltage of
0.8 volts and a high voltage of 2.0 volts. unless otherwise noted.
Figure 6.
~
Manchester Interface Serial Receiver Timing
TXCLK
TXDATA
TXEN
SIGQUAL
DS
MILOOP
ISOLATE
-t~-NOTE: Timing measurements are referenced to and from a low voltage of
0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
"IRQ assertion on collision not required-Bit 3 of the mode register
(MR) determines whether or not IRQ asserts on collision.
Figure 7.
Manchester Interface Serial Transmitter Timing
1-127
o
R68802
Local Network Controller (LNET)
00-07/00-015------------------~r
~------:lr
NOTE:
Timing measurements are referenced to and from a low yoltage of 0.8 yolts and a high Yoltage of 2.0 Yolts, unless otherwise noted.
Figure 8.
LNET Read Cycle Timing
cs
os
Rfiii
ifi'Aci(
19
00-07/00-015
NOTE:
Timing measurements are referenced to and from a low yoltage of 0.8 Yolts and a high yoltage of 2.0 Yolts, unless otherwise noted.
Figure g. LNET Write Cycle Timing
1-128
R68802
Local Network Controller (LNET)
o
I»D711»D15
i4----{34)----.!
NOTES: 1. Timing m.surements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise
noted.
2. Word mode only.
Figure 10. LNET to Memory DMA Transfer Cycle Timing
1·129
Local Network Controlter (LNET)
R68802
MPU
CLOCK
01).07/01).015
DONE (TO LNET)
OONE (FROM LNET)
NOTES: 1. Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise
noted.
2. Word mode only.
Figure 11. Memory to LNET DMA Transfer Cycle Timing
1-130
Local Network Controller (LNET)
R68802
D
IRQ
lACK
DTACK
DO-D7
NOTE: Timing measurements sre referenced to and from a 1_ voltage of 0.8 volta and a high voltage of 2.0 volts, unless
otherwise noted.
Figure 12. Interrupt Request Cycle Timing
1·131
Local Network Controller (LNET)
R68802
SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (Vee
Number
= 5.0Vdc
± 5%, V s
Characteristic
= OVdc, T A = 0 to 7.0°C)
Min
Symbol
1
Clock Period
tcp
90
2
Receive Clock Pulse Width
tCFR
45
3
Receive Data/Sense Setup
tRxs
30
4
RXDATA, Sense Hold Time
tRXH
20
5
IRQ Delay from RXCLK
tRIO
0
6
OS to IRQ Clear (Status Read)
tOlD
50
7
TXDATA'TXEN Delay (C l = 35pF)
tTXO
20
8
SIGQUAL Hold Time
tCPH
0
9
IRQ Delay from SIGOUAL Edge (Optional)'
tlso
10
MAU/MI Control Output Delay
tMOO
0
11
R/W High to CS, DS Low
t RHSL
0
I
12
CS Low to DTACK Low
tClOAL
20
~, DS High to R/W Low
tSHRL
20
14
CS High to DTACK Tristate
tSHOAT
20
15
CS, DS Low to Data Valid
tsuov
16
CS, DS High to Data Invalid
17
R/W Low to as, DS
18
CS, OS High to
19
R/W High
Max
1000
-
Unit
ns
ns
80
60
-
ns
ns
ns
ns
ns
ns
ns
0
13
Low
Typ
80
80
40
ns
ns
-
ns
ns
80
ns
0
140
ns
tSHOI
10
150
ns
tRlSl
0
40
-
ns
ns
tSHRH
20
Data Valid to CS, OS High
IOVSH
100
20
Cs. DS High to Data Invalid
tSHOI
10
21
lACK Low to OTACK Low
tlALAl
20
40
22
lACK High to DTACK Tristate
tlAHOAT
20
40
80
ns
23
lACK Low to Data Valid
IIAlOV
0
140
ns
80
ns
ns
ns
24
OS High to Dala Invalid
tlSHOI
10
50
ns
25
DACK Low 10 DONE/Data Valid
toLov
0
50
ns
26
DTACK High to DONE Invalid/Data
t OHOV
0
40
ns
27
OS Low 10 OACK High
tOlOH
0
50
ns
28
OS High to Data Invalid
tSHOI
0
29
Data Invalid 10 OS High
IOVSH
65
-
30
Clock Low to DONE (to LNET) Low
tClOl
0
100
ns
31
External DONE Pulse Width
leopw
70
250
ns
40
ns
ns
32
DACK Low 10 Internal DONE Low Delay
lOU~
80
ns
33
OACK High to Internal DONE High Delay
tOHIO
80
ns
34
DONE Low to RXREQ High
IOlRXH
2
RXCLK
35
OS High to IRQ High
IOSHIH
2
RXCLK
Note:
'IRQ assertion on collision dependent on btt 3 of mode register (MR).
1-132
Local Network Controller (LNET)
R68802
THERMAL CHARACTERISTICS
MAXIMUM RATINGS
Symbol
Value
Supply Vottage
Characteristics
Vee
-0.3 to + 7.0V
Input Vottage
VIN
-0.3 to + 7.0V
Operating Temperatures
Storage Temperatures
Characteristics
Symbol
Thermal Resistance
Ceramic
Plastic
TA
o to 70·C
TSTG
-55 to +150·C
Value
Rating
50
68
·CIW
·C/W
8JA
Note:
This device contains circuitry to protect the inputs against
damage due to high static vottages or electric fields; however,
normal precautions should be taken to avoid application of any
vottage higher than maximum-rated vottages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs
are tied to an appropriate logic voltage level (e.g., e~her V ss or
V ec ).
DC ELECTRICAL CHARACTERISTICS (Vee = 5.0Vdc ± 5%, Vss = OVdc, T A = 0 to 70·C unless otherwise noted)
Symbol
Min
Max
Unit
Input High Vottage
Characteriatics
V IH
+2.0
Vee
V
V
Input Low Vottage
V IL
-0.3
+0.8
Input Lsakage Cu~
R/W, RESET, CS
liN
-
10
Input Leakage Current for Three-State (Oft)
DTACK, DO-D15
I TSI
Output High Vottage _ _
RXREQ,TXREQ,DTACK,_____
DO-D15, MILOOP, MAUREQ, ISOLATE
TXEN, TXDATA
VOH
OutputLow~
VOL
-
RXREQ, TXREQ, TXEN, TXDATA, DTACK, DO-D15
MILOOP, MAUREQ, ISOLATE
IRQ, DONE
Power Dissipation
PINT
Input Capacitance
CIN
pA
VIN .= 0 to 5.25V
Vee = OV
10
pA
VIN '= 0.4 tei 2.4V
Vee = OV
-
V
V
V
Vee
ILOAD
ILOAD
ILOAD
0.5
V
Vee = 4.75V
I LOAD = 3.2 rnA
+2.4
+2.4
+2.4
1-133
Teat Conditions
=
=
=
=
4.75V
-400 pA, C LOAD = 130 pF
-400 pA, CLOAD = 32 pF
0, CLOAD = 30 pF
0.5
V
I LOAD = 8.8 rnA
1.0
W
TA = 25·C
13
pF
Vee = 5.0V
VIN = OV
f = 1 MHz
TA = 250C
o
R68802
Local Network Controller (LNET)
PACKAGE DIMENSIONS
40-PIN CERAMIC DIP
]]
~
[ D
~.
I
I
A
iF
1M
A
B
C
D
'n
I
HJ~LD
'
"'iW'
PLAN~~' L 9~~J
IN
I'
SEATING
M
-i
F
G
H
J
K
L
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
50.29 51.31 1.980 2.020
14.86 15.62 0.585 0.615
2.54
0.38
0.76
2.54
0.76
0.20
2.54
14.60
4.19 0.100
0.53 0.015
1.40 0.030
sse
0.100
1.78 0.030
0.33 O.OOB
4.19 0.100
15.37 0.575
M
cr
10'
N
0.51
1.52
0'
0.020
0.165
0.021
0.055
sse
0.1.170
0.013
0.165
0.605
10'
0.060
40-PIN PLASTIC DIP
[~~::~: ~: :~~::: ]J
DIM
A
B
~~wwLfN '~_
..
·
H~-.jG'- ~ l'F
I
..jl-o
~\;;
~
lJ
J-
M
1·134
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
51.28 52.32 2.040 2.060
13.72 14.22 0.540 0.'560
C
3.55
D
0.36
5.08 0:140
0.51 0.014
1.02
1.52
F
G
H
J
K
L
M
N
0.200
0.020
0.040 0.060
0.100 sse
2.54 sse
2.16 0.065 0.085
1.65
0.30 0.008 0.012
3.56 0.120 0.140
15.24 Bse
0,600
10'
7'
7'
lcr
0.51
1.02 0.020 0.040
0.20
3.05
sse
R68C552
'1'
Rockwell
R68C552
DUAL ASYNCHRONOUS COMMUNICATIONS
INTERFACE ADAPTER (DACIA)
PRELIMINARY
DESCRIPTION
FEATURES
The Rockwell CMOS R68C552 Dual Asynchronous Communications Interface Adapter (DACIA) provides an easily implemented,
program controlled interface between 16-bit microprocessor-based
systems and serial communication data sets and modems.
•
•
The DACIA has an internal baud rate generator. This feature eliminates the need for multiple component support circuits, a crystal
being the only other part required. The Transmitter baud rate can
be selected under program control to be either 1 of 15 different
rates from 50 to 38,400 baud, or at 1/16 times an external clock
rate. The Receiver baud rate may be selected under program control to be either the Transmitter rate, or at 1/16 times the external
clock rate. The DACIA is programmable for word lengths of 5,6,
7 or 8 bits; even, odd, or no parity; and 1 or 2 stop bits.
Data set/modem control functions
'! Internal baud rate generator with 15 programmable baud 'rates
(50 to 38,400)
The DACIA is designed for maximum programmed control from
the microprocessor (MPU) to simplify hardware implementation.
Dual sets of registers allow independent control and monit~ring
of each channeL The DACIA also provides a unique, programmable Automatic Address Recognition mode for use In a mUltidrop environment.
•
Program-selectable internally or externally controlled receiver
rate
•
Programmable word lengths, number of stop bits; and parity
bit generation ,and detection
•
Programmable interrupt control '
•
Programmable control of edge detect for OCD, DSR, DTR,
RTS, and CTS
• , Program-selectable serial echo mode for each channel
•
Automatic Address Recognition mode for multi-clrop operations
• 5.0 Vdc
The Control Register and Status Register permit the MPU to
easily select the R68C552's operating modes and determine
operational status.
± 5% supply requirements
•
40-pin plastic or ceramic DIP
•
Full TTL or CMOS input/output compatibility
• Compatible with R68000 microprocessor family
The Interrupt Enable Registers (IER) and Interrupt Status
Registers (lSR) allow the MPU to control and monitor the interrupt
capabilities of the DACIA.
The Control and Format Register (CFR) permits seleCtion of !;laud
rates, word lengths, parity and stop bits as well as control of DTR
and RTS output signals.
RES
OTACK
XTALI
XTALO
CLKOUT
IACK2
,OSR2
DC02
CTS2
RTS2
The Status Register (SR) gives the MPU access to the state of
the modem control lines, framing error, transmitter underrun and
.
break conditions.
The Compare Data Registers (CDR) hold the data value to be
used in the compare mode.
The IRQ Vector Register (IVR) holds the interrupt vector for use
in the interrupt acknowledge state, or commands a Transmit
Break and provides for parity/addrass recognition during Automatic Address Recognition mode.
IRQ2
Rx02
RSO
IACK1
DSR1
DC01
C'i'S1
RTS1
iffiii
05
04
Vss
Figure 1.
Document No. 68650N09
RiW
RS2
RS1
Tx02
De
Package:
C = Ceramic
P = Plastic
CS
OTR2
07
Part Number:
R68C552
~
IRQ1
Rx01
TxC
ORDERING INFORMATION
L
Low power CMOS N-well silicon gate technology
• Two independent full duplex chaiinels with buffered raceivers
and transmitters.
Tx01
AxC
00
01
02
03
R68C552 Pin Configuration
Product Description Order No. 708
Rev. 1, February 1984
1-135
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
INTERFACE SIGNALS
RESET (RES)
Figure 2 shows the DACIA interface signals associated with the
microprocessor and the modem.
During system initialization a low level on the RES input causes a
RESET to occur. At this time the IER's are set to $80, the DTR and
RTS lines go to the high state, theRDR register is cleared,
the IVR is set to $OF, the compare mode is disabled, and the CTS,
DCD, DSR flags are cleared. No other bits are affected.
DATA BUS (00-07)
The DO-D7 pins are eight data lines that transfer data between
the microprocessor (MPU) and the DACIA. These lines are bidirectional and are normally high-impedance except during READ cycle
when the DACIA is selected.
TRANSMIT DATA (TX01, TXD2)
The TxD outputs transfer serial non-return to zero (NRZ) data to
the data communications equipment (DC E). The data is transferred, LSB first, at a rate determined by the baud rate generator.
REGISTER SELECTS (RSO, RS1., RS2)
RECEIVE DATA (RXD1, RXD2)
The three register select lines are normally connected to the processor address lines to allow the MPU to select the various internal registers. Table 1 shows the internal register select coding
and identifies the abbreviations (ABBR) used throughout the text
for each register. Table 2 summarizes the control and status
registers and shows each bit allocation.
The RxD inputs transfer serial NRZ data into the DACIA from the
DCE, LSB first. The receiver baud rate is determined by the baud
rate generator.
CLEAR TO SEND (CTS1, CTS2)
The CTS control line inputs allow handshaking by the transmitter.
When CTS is low, the data is transmitted continuously. When CTS
is high, the Transmit Data Register empty bit in the ISR is not set.
The word presently in the Transmit Shift Register is sent normally.
Any active transition on the CTS lines sets the CTS bit in the
appropriate ISA. The CTS status bit in the SR reflects the current high or low state of CTS.
REAOIWRITE (RIW)
The Rm input, generated by the microprocessor, controls the
direction of data transfer. A high on the Rm line indicates a read
cycle, while a low indicates a write cycle.
CHIP SELECT (CS)
DATA CARRIER DETECT (DCD1, DCD2)
The chip select input is normally connected to the processor
address lines either directly or through decoders. The DACIA
latches address and Rm inputs on the falling edge of CS and
latches the data bus inputs on the rising edge of CS.
•
IACKI
R68000
BUS
IACKI
LOGIC
IRQl
ACIAI
INTERRUPT
LOGIC
R/W
CS
RES
OTACK
RSO
RS1
RS2
1/0 CONTROL
AND
REGISTER
SELECT
LOGIC
(
IRQ2
IACK2
.
.
00-07.)
"V
.."
These two lines may be used as general purpose inputs. An active
transition sets the DCD bit in the ISA. The DCD bit in the SR
reflects the current state of the DCD line.
ACIAI
REGISTERS
AND
CONTROL
LOGIC
CTSI
DCDI
DSR1
RxDl
TxDl
DTRI
RTSI
)
ACIA
CHANNEL 1
ACIAI BAUD
RATE SELECT
~
DATA
BUS
BUFFERS
DTACK
LOGIC
CLOCK
LOGIC
DATA
I/O
MUX
ACIA2
INTERRUPT
LOGIC
Figure 2.
ACIA2 BAUD
RATE SELECT
ACIA2
REGISTERS
AND
CONTROL
LOGIC
IACK2
LOGIC
DACIA Interface Signals
1-136
RxC
XTALI
CLKOUT
XTALO
TxC
RTS2
DTR2
TxD2
RxD2
DSR2
DCD2
CTS2
)
ACIA
CHANNEL 2
.Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
1
DATA SET READY (DSR1, DSR2)
CRYSTAL (XT All, XTAlO)
These two lines may be used as general purpose inputs. An active
transition sets the DSR bit in the ISR. The DSR bit in the SR
reflects the current state of the DSR line.
These pins are normally connected to an external 3.6864 MHz
crystal used as the time base for the baud rate generator. As an
alternative, the XTALI pin may be driven with an externally
generated clock in which case the XT AlO pin must float.
REQUEST TO SEND (RTS1, RTS2)
These two lines may be used as general purpose outputs. They
are set high upon reset. Their state may be programmed by set~the appropriate bits in the CFR high or low. The state of the
RTS line is reflected by the RTS bit in the SR.
RECEIVER CLOCK (RxC)
This pin is the Receiver 16x clock input when the baud rate generator is programmed for External Clock. Figure 15 shows timing considerations for RxC.
DATA TERMINAL READY (DTR1, DTR2)
These two lines may be used as general purpose outputs. They
are set high upon reset. Their state may be programmed by setting the appropriate bits in the CFR high or low. The state of the
DTR line is reflected by the DTR bit in the SR.
TRANSMITTER CLOCK (TxC)
This pin is. the transmitter 16x clock input when the baud rate
generator is programmed for External Clock. Figure 16 shwos timing considerations for TxC.
INTERRUPT REQUEST (IRQ1, IRQ2)
The IRQ lines are open-drain outputs from the interrupt control
logic. IRQ1 is associated with ACIA 1 and IRQ2 is associated with
ACIA2. These lines are normally high but go low when one of the
flags in the ISR is set, provided that its corresponding enable bit
is set in the IER.
Note
When RxC and TxC are used for external clock input,
XTALI must be tied to ground (Vss) and XTAlO must be
left open (floating).
CLOCK CIRCUIT
The internal clock oscillator supplies the time base for the baud
rate generator. The oscillator can be driven by a crystal or an
external clock, or it can be disabled, iii which case the time base
for the baud rate is generated by the Receiver External Clock
(RxC) and Transmitter External Clock (TxC) input pins. Figure 3
shows the three possible clock configurations.
RECEIVER
EXTERNAL
CLOCK
XTALI
RxC
TRANSMITTER
EXTERNAL
CLOCK
TxC
XTALO
OPEN
CIRCUIT
CLOCK OUT (ClK OUT)
This output is a buffered output from the 3.6864 MHz crystal
oscillator. It may be used to drive the XTAll input of another
DACIA. This allows multiple DACIA chips to be used in a system
with only one crystal needed. ClK OUT is in phase with XTALI.
XTALI
EXTERN~
CLOCK
XTALI
OPEN .~ XTALO
CIRCUIT
EXTERNAL
INTERNAL
CLOCK
CLOCK
XTALO
EXTERNAL
CLOCK
Figure 3.
DACIA Clock Generation
1·137
R68C552
Dual Asynchronous Communications· Interface Adapter (DACIA)
TJlO1
iAffir.
DClff
imI1
CT.'
lII01
D1'JR
Ri'Si
RxD1
DATA
CLKOUT
XTALO
""C
",02
~~~_ _ _ _ _ _ _ _ _ _ ~2
F~~~t:==:;--:------- DT. .
~ ~------------~
riN~:';;;r1-""++---- CTS2
14----- = 8-BITDATALINES
IfjUlTt-BIT
~:TROL LINES
Figure 4. DACIA Block Diagram
1-138
Dual Asynchronous .Communications· Interface· Adapter (DACIA)
R68C552
FUNCTIONAL DESCRIPTION
Figure 5 shows an example of a Single transmitted or received
data word. In this example, the dataword is formatted with 8 data
bits, parity, and two stop bits, Figure 5 also shows a single
character transmitted or received in Address Recognition mode.
In this example, the address or data word is 8 bits, there is no
parity bit, and. there are two stop bits. The 10th bit, (normal parity
bit) is an address/data indicator bit. A 1 means the 8 bits are an
address that will be compared with the address stored in the Compare Data Register. A 0 means the 8 bits are data.
Figure 4 is a block diagram of the DACIA which consists of two
asynchronous communications interface adapters. with common
microprocessor interface control logic .and data bus buffers. The
individual functional elements of the OACIA are described in the
following paragraphs.
DATA BUS BUFFER
The Data Bus Buffer is a bidirectional interface between the
system data lines and the internal data bus. When RiW is high and
CS is low the Data Bus Buffer passes data from the internal data
bus to th~ system data lines. When Rm is high, CS is high, and
either lACK line is low, the IRQ vector is passed to the system
data bus. When RiW is low and CS is low, data is brought into the
DACIA from the system data bus. The following table summarizes
the Data Bus Buffer states.
PARITY MODE
I
[0
I
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Control Signals
CS IACK1 IACK2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
I
2 13 14
15 16 17
•
-,
START
BIT
_
DATA
Ip
11$12S
I
JI-~
PARITY STOP
BIT
BITS
ADDRESS/DATA MODE
Data Bus Buffer Summary
RJW
11
L
I
Data Bus Buffer State
ILLEGAL MODE - TRI STATE
ILLEGAL MODE - TRI STATE
ILLEGAL MODE - TRI STATE
WRITE MODE - TRI STATE
ILLEGAL MODE - TRI STATE
ILLEGAL MODE - TRI STATE
ILLEGAL MODE - TRI STATE
TRISTATE
ILLEGAL MODE - OUTPUT $OF
ILLEGAL MODE _ OUTPUT $OF
ILLEGAL MODE - OUTPUT $OF
READ MODE ~ OUTPUT DATA
ILLEGAL MODE - OUTPUT $OF
OUTPUT IRQ VECTOR 1
OUTPUT IRQ VECTOR 2
TRISTATE
I
I
0 11
I
2 1 3 14
t
I
5 16
START
BIT
17 J~DI1S 12S I
JI~
,
STOP
BITS
ADDRESS
OR
DATA
Figure 5.
o
Typical Data Word
INTERRUPT LOGIC
The interrupt logic causes the IRQ lines (IRQ1 or IRQ2) to go low
when conditions are metthat require the attention of the MPU.
There are two registers (the Interrupt Enable Register and the
Interrupt StatuS Register) involved in the control of interrupts in
the DACIA. Corresponding bits in both registers must be set to
cause an IRQ.
INTERRUPT ENABLE REGISTER (IER)
TRANSMIT AND RECEIVE DATA REGISTERS
The Interrupt Enable Register (IER) is a write-only register that
allows each of the possible IHQsources to be enabled, or disabled, individually without affecting any of the other interrupt
enable bits in the register. IRQ sources are enabled by writing
to the IER with bit 7 set to a 1 and every bit set to I!- 1 that corresponds to the IRQ source to be enabled. IRQ sources are
disabled by writing to the IER with bit 7 set to a 0 and every bit
set to a 1 that corresponds to the IRQ source to be disabled. Any
bit (except bit 7) to which a 0 is writtenis unaffected and remains
in its original state. As an example, writing $7F to the IER will
disable all IRQ source bits, but writing $FFto the IER will enable
all IRQ source bits. A hardware reset. (RES) clears all IRQ
source bits to the 0 state. Bit assignments for the IER are as
follows:
These registers are used as temporary data storage for the DACIA
Transmit and Receive circuits. The Transmit Data Register is
characterized as follows:
•
•
Bit 0 is the leading. bit to be transmitted.
Unused data bits are the high-order bits and are "don't care"
for transmission.
• Write.Only Register.
The Receive Data Register is characterized in a similar fashion
as follows:
Bit 0 is the leading bit received.
Unused data bits are the high order bits and are "0" for the
receiver.
• Parity bits are not contained in the Receive Data Register, but
are stripped off after being used for external parity checking.
Parity and all unused high-order bits are "0".
•
•
7
CLEARI
SET
BITS
• Read·Only Register
1-139
6
TDR
EMPTY
IE
5
CTS
IE
4
DCD
IE
3
DSR
IE
2
1
0
PARITY
ERROR
IE
FRM
OVR
BRK
IE
RDR
FULL
IE
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
Table 1.
CONTROL &FORMAT
REGISTER BITS
REGISTER SELECT
LINES
HEX
00
L
L
L
01
L
L
H
02
L
H
DACIA Register Selection
L
REG
REGISTER ACCESS
-
-
IERl
ISRl
INTERRUPT ENABLE
REGISTER 1
INTERRUPT STATUS
REGISTER 1
0
-
CFRl
SRl
CONTROL
REGISTER 1
STATUS
REGISTER 1
1
-
CFRl
FORMAT
REGISTER 1
INVALID
-
0
CDRl
COMPARE
DATA
REGISTER 1
INVALID
-
1
IVRl
IRQ
VECTOR 1
INVALID
03
L
H
H
-
-
TDRl
RDRl
TRANSMIT DATA
REGISTER 1
RECEIVE DATA
REGISTER 1
04
H
L
L
-
-
IER2
ISR2
INTERRUPT ENABLE
REGISTER 2
INTERRUPT STATUS
REGISTER 2
0
-
05
H
L
H
CFR2
SR2
CONTROL
REGISTER 2
STATUS
REGISTER 2
1
-
CFR2
FORMAT
REGISTER 2
INVALID
-
0
CDR2
COMPARE
DATA
REGISTER 2
INVALID
-
1
IVR2
IRQ
VECTOR 2
INVALID
-
-
TDR2
RDR2
TRANSMIT DATA
REGISTER 2
RECEIVE DATA
REGISTER 2
06
07
H
H
L.
H
H
H
Table 2.
Control.and Status Registers Format Summary
REGISTER BIT NUMBERS
REGISTER
7
6
5
4
3
2
1
0
CLEARISET
BITS
TDR
EMPTY
IE
CTS
IE
DCD
IE
DSR
IE
PARITY
ERROR
IE
FRM
OVR
BRK
IE
RDR
FULL
IE
INTERRUPT
ENABLE
REGISTERS
ANY
BIT
SET
TDR
EMPTY
CTS
TRANS
DCD
TRANS
DSR
TRANS
PARITY
ERROR
FRM
OVR
BRK
RDR
FULL
INTERRUPT
STATUS
REGISTERS
FRAMING
ERROR
TRANS
UNDR
CTS
STATUS
OCD
STATUS
DSR
STATUS
REC
BREAK
DTR
STATUS
RTS
STATUS
STATUS
REGISTERS
0
IVRICDR
REG
NO.
STOP
BITS
ECHO
1
NUMBER OF
DATA BITS
PARITY
SELECTION
CONTROL
REGISTERS
BAUD RATE SELECTION
PARITY'
ENABLE
DTR
CONTROL
$80
RTS
CONTROL
AND
FORMAT
REGISTERS
COMPARE
DATA
REGISTER
COMPARE BITS (ADDRESS RECOGNITION)
IAMODE
IRQ VECTOR ADDRESS
IRQ SOURCE
TRANS
BRK
NOT USED
1-140
PARI
ADDR
INTERRUPT
VECTOR
REGISTER
TIR MODE
$OF
R68C552
Dual Asynchronous Communications Interface Adapter (DACIA)
INTERRUPT STATUS REGISTER (ISR)
INTERRUPT VECTOR REGISTER (IVR)
The Interrupt Status Register (ISR) is a read-only register that
identifies the current status condition for each DACIA internal IRQ
source. Bits 6 through 0 of the ISR are set to a 1 whenever the
corresponding IRQ source condition has occurred in the DACIA.
Bit 7 identifies if any of the IRQ source status bits have been set
in the ISR.
The DACIA has two Interrupt Vector Registers which are write2 (OUT)
• IRQ inierrupt
iRa
S.D.
2 (OuT)
4IQ 11M
R/W
DO
0'
02
d.
0'
d.
06
07
A9
II
R6500 Microprocessors (CPU)
R650X, R651 X
tP,
R6513 FEATURES
vss
RES
(IN)
tP2 (IN)
R/W
iRQ
• 4K addressable bytes of memory (AO-A 11)
NMI
• Two phase clock input
vee
• IRQ interrupt
• NMI interrupt
• 8-bit bidirectional data bus
AO
A1
A2
A3
A4
A5
A6"
A7
AS
00
01
02
03
04
05
06
07
A11
A10
A9
vss
RES
• 28-pin DIP
tP,
R6514 FEATURES
(IN)
IRQ
tP2 (IN)
R/W
vee
DO
01
02
AO
A1
A2
A3
A4
A5
A6
A7
AS
A9
• 8K addressable bytes of memory (AO-A12)
• Two phase clock input
• IRQ interrupt
• 8-bit bidirectional data bus
vss
ROY
tP, (IN)
IRQ
R6515 FEATURES
vee
• 4K addressable bytes of memory (AO-A 11)
AO
A1
A2
A3
A4
A5
A6
A7
AS
• Two phase clock input
• IRQ interrupt
• RDY signal
• 8-bit bidirectional data bus
2-6
03·
04
05
06
07
A12
A11
A10
RES
tP2 (IN)
R/W
DO
01
02
03
04
05
06
07
All
A10
AS
R650X, R651 X
R6500 Microprocessors (CPU)
RES
VSS
q,1 (OUT)
fRQ
R6506 FEATURES
• 4K addressable bytes of memory (AO-A 11)
•
•
•
•
VCC
AO
Al
A2
A3
A4
AS
A6
A7
AS
On-chip clock
IRQ interrupt
Two phase output clock for timing of support chips
8-bit bidirectional data bus
• 28-pin DIP
RES
vss
q,2 (OUT)
q,o (IN)
RiW
DO
01
02
03
04
06
06
07
All
Al0
A9
<1>2 (OUT)
"
lIr5
~
I
AI''4-
1
P
R6500 Microprocessors· (CPU)
R650X,R651X
INSTRUCTION SET
The R6S00 CPU has 56 instruction types which are enhanced
by up to 13 addressing modes for each instruction. The accu-
mulator, index registers, Program Counter, Stack Pointer and
Processor Status Register are illustrated below.
Alphabetic Listing of Instruction Set
Mnemonic
Function
Mnemonic
Function
ADC
AND
ASL
Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)
JMP
JSR
Jump to New Location
Jump to New Location Saving Return Address
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRK
BVC
BVS
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set
LOA
LOX
LOY
LSR
Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or Accumulator)
NOP
No Operation
ORA
"OR" Memory with Accumulator
CLC
CLD
CLI
CLV
CMP
CPX
CPY
Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable
Clear Overflow Flag
Compare Memory a/ld
Compare Memory and
Compare Memory and
PHA
PHP
PLA
PLP
Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from StaCk
Pull Processor Status from Stack
ROL
ROR
RT!
RTS
Rotate One Bit Left (Memory or Accumulator)
Rotate One Bit Right (Memory or Accumulator)
Return from Interrupt
Return from Subroutine
DEC
DEX
DEY
Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One
EOR
"Exclusive-OR" Memory with Accumulator
SBC
SEC
SED
SEI
STA
STX
STY
Subtract Memory from Accumulator with Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt .Disable Status
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
INC
INX
INY
Increment Memory by One
Increment Index X by One
Increment Index Y by One
TAX
TAY
TSX
TXA
TXS
TYA
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
7
I7
15
I
I7
y
[
X
I
PCl
I
S
8 7
11
Accumulator
Index X
Index Y
7
0
A
7
PCH
Bit
I ACCUMULATOR
A
0
( INDEX REGISTER
0
(INDEX REGISTER
0
PROGRAM COUNTER
0
STACK POINTER
X
I
I
0
LN-.! V-.!1 I
Y
Accumulator to Index X
Accumulator to Index Y
Stack Pointer to Index X
Index X to Accumulator
Index X to Stack Register
Index Y to Accumulator
BI 0 II J Z ICI PROCESSOR STATUS REG 'P"
~
L
LCARRY
"PC"
US"
ZERO
1=TRUE
1 = RESULT ZERO
IRQ DISABLE
'----~
DECIMAL MODE
'------BRK COMMAND
~------OVERFlOW
' - - - - - - - - NEGATIVE
Programming Model
2-10
1 = DISABLE
1 = TRUE
1 = BRK
1 =TRUE
1 = NEG.
R6500. Microprocessors (CPU)
R650X, R651X
ADDRESSING MODES
the base address. This type of indexing allows any location referencing and the index to modify multiple fields, resulting in
reduced coding and execution time.
The R6500 CPU family has 13 addressing modes. In the following
discussion of these addressing modes, a bracketed expression follows the title of the mode. This expression is the term used in the
Instruction Set Op Code Matrix table (later in this product description) to make it easier to identify the actual addressing mode used
by the instruction.
IMPLIED ADDRESSING [Implied]-In the implied addressing
mode. the address containing the operand is implicitly stated in
the operation code of the instruction.
ACCUMULATOR ADDRESSING [Accum]-This form of addressing is represented with a one byte instruction, implying an
operation on the accumulator.
RELATIVE ADDRESSING [Relatlve]-Relative addressing is
used only with branch instructions and establishes a destination
for the conditional branch.
IMMEDIATE ADDRESSING [IMM]-In immediate addressing,
the second byte of the instruction contains the operand, with no
further memory addressing required.
The second byte of the instruction becomes the operand which
is an "Offset" added to the contents of the lower eight bits of
the program counter when the counter is. set at the ne1 PAD-PA7
}
CAl
CA2
R/W
PERIPHERAL
DEVICE
A
IISO
RS1
CSO
CSl
CS2
RES
IRQA
IROB
V5S
VCC
R6520
PIA
..
CBl ' }
CB2
,
L-
18\
Figure 3. Interface Signals Relationship
2-27
~ PBD-PB7
PERIPHERAL
DEVICE
B
Peripheral Interface Adapter (PIA)
R6520
Registers (CRA, CRB) the Data Direction Registers (DDRA,
DDRB) and the Peripheral Output Registers (ORA, ORB). In
addition, the processor may directly read the contents of the
Control Registers and the Data Direction Registers. Accessing
the Peripheral Output Register for the purpose of reading data
back into the processor operates differently on the ORA and the
ORB registers and therefore are shown separately in Table 2.
by CRB bit O. Likewise, bit 6 (IROB2) in CRB is set by an active
transition on CB2, and IROB from this flag is controlled by CRB
bit 3.
Also, both bit 6 and bit 7 of CRB are reset by a "Read Peripheral
B Output Register" operation. A summary of IROB control is
shown in Table 3.
Table 3.
Table 2.
ORA and ORB Register Addressing
Register
Data Direction
Select Lines
Control
Register
Address
(Hex)
RSI
0
0
1
2
2
3
L
L
L
H
H
H
RSO
L
L
H
L
L
H
CRA
CRB
(Bit 2) (Bit 2)
1
0
-
1
0
-
Register Operation
R,w=H
Read
Read
Read
Read
Read
Read
PIBA
DORA
CRA
PIBB
DDRB
CRB
RiW=L
Write
Write
Write
Write
Write
Write
IROA and IROB Control Summary
Control Register Bits
ORA
DORA
CRA
ORB
DDRB
CRB
Action
CRA-7=1 and CRA-O=1
IROA goes low (Active)
CRA-6=1 and CRA-3=1
IROA goes low (Active)
CRB-7=1 and CRB-O=1
IROB goes low (Active)
CRB-6=1 and CRB-3=1
IROB goes low (Active)
Note:
The flags act as the link between the peripheral interrupt signals
and the processor interrupt inputs. The interrupt disable bits allow
the processor to control the interrupt function.
INTERRUPT INPUT/PERIPHERAL CONTROL LINES
(CA1, CA2, CB1, CB2)
INTERRUPT REQUEST LINES (IRQA, IRQB)
The four interrupt input/peripheral control lines provide a number
of special peripheral control functions. These lines greatly
enhance the power of the two general purpose interface ports
(PAO-PA7, PBO-PB7). Figure 4 summariles the operation of
these control lines.
The active low Interrupt Request lines (IROA and IROB) act to
interrupt the microprocessor either directly or through external
interrupt priority circuitry. These lines are open drain and are
capable of sinking 1.6 milliamps from an external source. This
permits all interrupt request lines to be tied together in a wiredOR configuration. The A and B in the titles of these lines correspond to the peripheral port A and the peripheral port B so
that each interrupt request line services one peripheral data
port.
CAl is an interrupt input only. An active transition of the signal
on this input will set bit 7 of the Control Register A to a logic 1.
The active transition can be programmed by setting a "0" in bit
1 of the CRA if the interrupt flag (bit 7 of CRA) is to be set on
a negative transition of the CAl Signal or a "1" if it is to be set
on a positive tranSition.
Each Interrupt Request line has two interrupt flag bits which can
cause the Interrupt Request line to go low. These flags are bits
6 and 7 in the two Control Registers (CRA, CRB). These flags
act as the fink between the peripheral interrupt signals and the
microprocessor interrupt inputs. Each flag has a corresponding
interrupt disable bit which allows the processor to enable or disable the interrupt from each of the four interrupt inputs (CAl,
CA2, CB1, CB2). The four interrupt flags are set (enabled) by
active transitions of the signal on the interrupt input (CA 1, CA2,
CBt, CB2).
Note:
A negative transition is defined as a transition from a high
to a low, and a positive transition is defined as a transition
from a low to a high voltage.
CA2 can act as a totally independent interrupt or as a peripheral
control output. As an input (CRA, bit 5 = 0) it acts to set the
interrupt flag, bit 6 of CRA. to a logic 1 on the active transition
selected by bit 4 of CRA.
CRA bit 7 (IROA1) is always set by an active transition of the
CAl interrupt input signal. However, IROA can be disabled by
setting bit 0 in CRA to a O. Likewise, CRA bit 6 (IROA2) can be
set by an active transition of the CA2 interrupt input signal and
IRQA can be disabled by setting bit 3 in CRA to a O.
These control register bits and interrupt inputs serve the same
basic function as that described above for CAl. The input signal
sets the interrupt flag which serves as the link between the
peripheral device and the processor interrupt structure. The
interrupt disable bit allows the processor to exercise control over
the system interrupt.
Both bit 6 and bit 7 in CRA are reset by a "Read Peripheral
Output Register A" operation. This is defined as an operation
in which the read/write, proper data direction register and register select signals are provided to allow the processor to read
the Peripheral A I/O port. A summary of IROA control is shown
in Table 3.
in the output mode (CRA, bit 5 = 1), CA2 can operate independently to generate a simple pulse each time the microprocessor reads the data on the Peripheral A I/O port. This mode
is selected by setting eRA, bit 4 to a 0 and CRA, bit 3 to a 1.
This pulse output can be used to control the counters, shift registers, etc., which make sequential data available on the Peripheral input lines.
Control of IROB is performed in. exactly the same manner as
that described above for IRCA. Bit 7 in CRB (IROBt) is set by
an active transrrion on CBl and IROB from this flag is controlled
2-28
Peripheral Interface Adapter· (PIA)
R6520
CONTROL REGISTER A (CRA)
CA2 INPUT MODE (BIT 5 - 0)
7
6
5
4
3
2
1
0
IROA1
FLAG
IROA2
FLAG
CA21NPUT
MODE SELECT
(=0)
IROA2
POSITIVE
TRANSITION
IROA
ENABLE
FOR IROA2
ORA
SELECT
IROAI
POSITIVE
TRANSITION
IROA
ENABLE
FOR IROA1
IRONIROA2
CONTROL
mAJIROA1
CONTROL
CA2 OUTPUT MODE (BIT 5 = 1)
7
6
5
4
3
2
1
0
IROAI
FLAG
0
CA20UTPUT
MODE SELECT
(=1)
CA2
OUTPUT
CONTROL
CA2
RESTORE
CONTROL
ORA
SELECT
IROA1
POSITIVE
TRANSITION
IROA
ENABLE
FOR IROA1
IRONIROA1
CONTROL
CA2
CONTROL
CA21NPUT OR OUTPUT MODE (BIT 5 = 0 or 1)
Bit 7
1
o
IRQA1 FLAG
A transition has occurred on CAl that satisfies the bit 1 IROA1 transition polartty criteria. This bit is cleared by a read of Output Register
A or by RES.
No transition has occurred on CAl that satisfies the bit 1 IROA1 transition polarity criteria.
Bit 2
1
OUTPlIT REGISTER A SELECT
Select Output Register A
Select Data Direction Register A
Bit 1
1
IRQA1 POSITIVE TRANSITION
Set IROAI Flag (bit 7) on a positive (Iow-to-high) transition of CAl.
Set IROAI Flag (bit 7) on a negative (high-to-Iow) transition of CAl.
Bit 0
1
IRQA ENABLE FOR IRQA1
Enable assertion of IROA when IROAI Flag (bit 7) is set.
Disable assertion of IROA when IROAI Flag (bit 7) is set.
o
o
o
CA2 OUTPUT MODE (BIT 5 = 1)
CA2 INPUT MODE (BIT 5 = 0)
Bit 6
1
o
IRQA2 FLAG
A transition has occurred on CA2 that satisfies the bit 4
IROA2 transition polarity criteria. This flag is cleared by
a read of Output Register A or by RES.
No transition has occurred on CA2 that satisfies the bit
4 IROA2 transition polarity criteria.
Bit 5
CA2 MODE SELECT
Select CA2 Input Mode.
Bit 4
1
IRQA2 POSITIVE TRANSITION
Set IROA2 Flag (bit 6) on a positive (Iow-to-high)
transition of CA2.
Set IROA2 Flag (bit 6) on a negative (high-to-Iow)
transition of CA2.
o
o
Bit 3
1
o
Bit 6
NOT USED
Always zero.
Bit 5
1
CA2 MODE SELECT
Select CA2 Output Mode.
Bit 4
1
CA2 OUTPUT .CONTROL
CA2 goes low when a zero is written into CRA bit 3.
CA2 goes high when acme is written into CRA bit 3.
CA2 goes low 6n' the first negative (high-ta-Iow) .2
clock transition following a read of Output Register A
CA2 returns high as specified by bit 3.
o
o
Bit 3
o
IRQA ENABLE FOR IRQA2
Enable assertion of IROA when IROA2 Flag (bit 6) is
set.
Disable assertion of IROA when IROA2 Flag (bit 6) is
set.
Figure 4.
CA2 READ STROBE RESTORE CONTROL (4 = 0)
CA2 returns high on tl:1e neXt 02 clock nilgative
transition followillg a read of Output Register A.
CA2 returns high on the next active CAl transition
following a read 6f Output Register A as specified by
bit 1.
Control Line Operations Summary (1 of 2)
2-29
fI
R6520
Peripheral Interface Adapter (PIA)
CB2 INPUT MODE (BIT 5
CONTROL REGISTER B (CRB)
=0)
7
6
5
4
3
2
1
0
IROB1
FLAG
IROB2
FLAG
CB21NPUT
MODE SELECT
(=0)
IROB2
POSITIVE
TRANSITION
IROB
ENABLE
FOR IROB2
ORB
SELECT
IROB1
POSITIVE
TRANSITION
IROB
ENABLE
FOR IROB1
IROB/IROB2
CONTROL
CB2 OUTPUT' MODE (BIT 5
IROB/IROB1
CONTROL
= 1)
7
6
5
4
3
2
1
0
IROB1
FLAG
0
CB2 OUTPUT
MODE SELECT
(=1)
CB2
OUTPUT
CONTROL
CB2
RESTORE
CONTROL
ORB
SELECT
IROB1
POSITIVE
TRANSITION
IROB
ENABLE
FOR IROB1
CB2
CONTROL
IROB/IROB1
CONTROL
CB2 INPUT OR OUTPUT MODE (BIT 5 = 0 or 1)
Bit 7
1
o
IRQB1 FLAG
A transttion has occurred on CB1 that satisfies the bit 1 .IROB1 transition polarity criteria. This bit is cleared by a read of Output Register
. B or by RES.
No transttion has occurred on CB1 that satisfies the bit 1.IROBI transition polarity criteria.
Bit 2
1
OUTPUT REGISTER B SELECT .
Select Output Reg~r B.
Select Data Direction Register B.
Bil 1
1
IRQB1 POSITIVE TRANSITION
Set IROB1 Flag (bit 7) on a positive (Iow-to-high) transition of CB1.
Set IROB1 Flag (bit 7) on a negative (high-to-Iow) transttion of CB1.
Bit 0
1
IRQB ENABLE FOR IRQB1
Enable assertion of iRQe when IROB1 Flag (bit 7) is set.
Disable assertion of IROB when IROB1 Flag (bit 7) is set.
o
o
o
CB2 INPUT MODE (BIT 5 = 0)
Bit 6
1
o
CB2 OUTPUT MODE (BIT 5
IRQB2 FLAG
A transition has occurred on CB2 that satisfies'the bit 4
IROB2 transition polarity criteria. This flag is cleared by
a read of Output Register B or by RES.
No transition has occurred on CB2 that satisfies the bit
4 IROB2 transition polarity -criteria.
Bit 5
CB2 MODE SELECT
Select CB2 Input MQde.
Bit 4
IRQB2 POSITIVE TRANSITION
Set.IROB2 Flag (bit 6) on a positive (Iow-to-high)
transition of CB2.
Set IROB2 Flag (bit 6) on a negative (high-to-Iow)
transition of CB2.
o
o
NOT USED
A'rN8Ifs zero.
Bit 5
1
CB2 MODE SELECT
Select. CB2 Output Mode.
Bit 4
1
CB2 OUTPUT CONTROL
CB2 goes low when a zero is written into CRB bit 3.
CB2 goes high when a one is written into CRB bit 3.
CB2 goes low on the first negative (high-to-Iow) 02
clock transition following a write to Output Register S.
CB2 returns high as specified by bit 3.
o
o
Bit 3
1
iiiQB ENABLE FOR IRQB2
Enable assertion of iRQB when IROB2 Flag (bit 6) is
o
set.
.Disable assertion of iRCiB when IROB2 Flag (bit 6) is
set.
Figure 4_
Bit 3
o
CB2 WRITE STROBE RESTORE CONTROL
(BIT 4 0)
CB2 returns high on the next 02 clock negative
transition following a write to Output Register B.
CB2 returns high on the next active CB1 transition
following a write to Output Register B as specified by
bit 1.
=
Control Line Operations Summary (2 of 2)
2-30
=1)
Bit 6
Peripheral Interface Adapter (PIA)
R8520
transfers the data on the Peripheral A 1/0 lines to the data bus.
In this situation, the data bus will contain both the input and output data. The processor must be programmed to reCognize and
interpret only those bits Which are important to the particular
peripherst operation being performed.
A second output mode allows CA2 to be used in conjunction
with CAl to "handshake" between the processor and the
peripheral device. On the A side, this technique allows positive
control of data transfers from the peripheral device into the
microprocessor. The CA 1 input signals the processor that data
is available by interrupting the processor. The processor reads
the data and sets CA2low. This signals the peripheral device
that it can make new data available.
Since the processor always reads the Peripheral A 1/0 port pins
instead of the actual Peripheral Output Register (ORA), it is
possible for the data read by the proceSsor to differ from the
contents of the Peripheral Output Register for an output line.
This is,;t~ue when the 110 p.ln is not .allowed to go to a full
+2.4V DC when the Peripheral Output register contains a
logic 1. In th'is case, the processor will read a 0 from the
Peripheral A pin, even though the corresponding bit in the
Peripheral Output register is a 1.
The final output mode can be selected by setting bit 4 of CRA
to a 1. In this mode, CA2 is a simple peripheral control output
which can be set high or lOW by setting bit 3 or CRA to a 1 or
a 0 respectively.
CBl operates as an Interrupt Input only in the same manner as
CAl. Bit 7 of CRB is set by the active transition selected by bit
oof CRB. Likewise, the CB2 input mode operates exactly the
same as the CA2 input modes. The CB2 output modes, CRB
bit 5 - 1, differ somewhat from those of CA2. The pulse output
occurs when the processor writes data Into the Peripheral B Output Register. Also, the "handshaking" operates on data transfers
from the processor into the peripheral device.
READING THE PERiPHERAL B I/orJoin
Reading the Peripheral B I/O port yields a combination of input
and output data Ina manner similar to the Peripheral A port.
However, data Is reiid directly from thil Peripheral B Output
Register (ORB) for those lines programmed to act as outputs.
It is therefore possible to load down the Peripheral B Output lines
without causing incorrect data to be transferred back to the
.
processor on a Read operation.
READING THE PERIPHERAL A 1/0 PORT
Performing a Read operation with RSl = 0, RSO = 0 and the
Data Direction Register Access Control bit (CRA-2) ... 1, directly
-
1... -
Ic:vc
Ie....,.. -Itc
"'-
II
-
IACR-
RSO, RSl,
CSO, CS1, CS2
~
~
1I
-\
f-IcAR
~
\iJ\
I--lpCR .....
PAD-PA7
PBO-PB7
~
I- ...
!coRDO-D7
DATA IN
CA2
(PULSE OUT)
~
~
-
~IHR
le.u I -
\
-
- loe
CA1
IRS'r-
7
1,.
ft-
~
~
-
CA2
(HAND SHAKE)
\
Figure 5.
Read Timing Waveforms
2-31
IRSZ
2
Peripheral Interface Adapter (PIA)
R6520
RSO, RS1,
CSO,CS1, CS2
RIW
00·07
DATA OUT _ _ _ _--'
PBO·PB7
PAO·PA7
~~~§§~~~~~~l======l============
.2:
CB2
(PULSE OUT)
CBl
CB2
(HAND SHAKE)
Figure 6.
Write Timing Waveforms
2·32
R6520
Peripheral Interface Adapter (PIA)
BUS TIMING CHARACTERISTICS
2 MHz
1 MHz
P....meter "
112 CYcle
112 Pulse Widlh
112 Rise and Fall Time
Symbol'
'. !eve
'"
Min.
Max.
Min.
1.0
-
0.5
470
In:. lj,,'
-
25
25
IACR
150
0
-
!c
235
-
Miix.
-
25
15
Unit
lOS
ns
ns
READ TIMING
Address Sel-Up Time
Address Hold Time
Peripheral Data Sel-Up Time
Data Bus Delay TIme
Dala Bue Hold Time
leAR
IPCR
!cOR
IHR
300
IACW
!cAW
180
0
130
50
-
10
-
395
-
90
0
150
-
10
190
-
ns
ns
ns
ns
ns
WRITE TIMING
Addrass Set-Up Time
Address Hold Time
RiW Sel-Up Time
RiW Hold Time
Data, Bils Sel-Up Time
Dala Bus Hold' Time
Peripheral, Data Delay Time
Peripheral Data Delay Time
CMOS Level,
Iwcw
Icww
to
locw
IHW
!cPW
!cMOS
300
IPCR
!cA2
IRSi
IRS2
'!cB2
300
10
-
1.0.
2.0
90
0
65
25
150
10
-
-
-
ns
ns
ns
ns
ns
ns
0.5
1.0
lOS
lOS
-
os
PERIPHERAL INTERFACE TIMING
PeripheralOata Set-up
112 Lpw 10CA2 Low Delay
112 Low 10 CA2 High Delay
CAl Active 10 CA2 High Delay
112 High 10 CB2 Low Delay
Peripheral
Valid to CB2 Low Delay
112 High to CB2 High Delay
CBl Active 10 CB2 High Delay
CAl., CA2. CBl and CB2
Inpul Rise and Fan Time
Ostia
Ioc
IRs,
IRS2
Ir. "
0
-
2-33
-
1.0
1.0
2.0
1,0
1.5
1.0
2.0
1.0
150
0
-
0.,5
0.5
1.0
0.5
0.75
0.5
1.0
1.0
p.S
lOS
p.S
lOS
lOS
lOS
p.S
p.S
R6520
Peripheral Interface Adapter (PIA)
ABSOLUTE MAXIMUM RATINGS*
Paramater,
Symbol
Value
Unit
Vee
-0.3 to +7.0
Vdc
-0.3 to +Vee
Vdc
Supply Voltage
Input Voltage'
VIN
Operating Temperature Range
Commercial
Industrial
TA
TH
o to +70
-40 to +85
·C
Storage Temperature
TSTG
-55 to +150
·C
T~
·NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in the other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
OPERATING CONDITIONS
Symbol
Value
Supply Voltage
Parameter
Vee
5V ±5%
Temperature Range
Commercial
Industrial
TA
O·C to 70·C
-40°C to +85·C
DC CHARACTERISTICS
(Vee
=
5.0V ±5%. Vss -
O. T A - TL to TH. unless otherwise noted)
Min.
Typ.3
Max.
Unlt1
VIH
+2.0
-
Vee
V
VI~
-0.3
Symbol
Parameter
Input High Voltage
-
THt'Coridltions
+0.8
V
liN
-
-
Input Leakage Current
R/W, RES, RSO, RS1, CSC, CS1, CS2,
CA1, CB1, \62
±1
±2.5
pA
VIN = OV to 5.25V
Vee = OV
Output Leakage Current lor Three-State Off
00-07, PBO-PB7,CB2
Irsl
-
±2
±10
pA
VI~ • 0.4V to 2.4V
Input High Current
PAO-PA7, CA2
IIH
-100
-250
-
Input Low Current
PAO-PA7, CA2
II~
Output High Voltage
All outlluts
PBO-P87, C82 (Darlington Drive}
VOH
Output Low Voltage
VO~
Input Low Voltage
'
Output High Current (Sourcing)
Logic
PBO-PB7, CB2 (Darlington Drive)
IOH
Output Low Current (Sinking}
Vee
= 5.25V
pA
VIH
= 2.4V
-1.6
mA
VII:': 0.4V
-
-1 '
2.4
1.5
-
-
V
V
Vee - 4.75V
I~OAO = - 100pA
I~OAO = -1.0 mA
-
+0.4
V
Vee
-
= 4.75V
I~OAO • 1.6 mA
-100
-1.0
-1000
-2.5
-
-10
mA
VOH = 2.4V
VOH - 1.5V
-
pA
lo~
1.6
-
mA
Vo~ = 0.4V
Output Leakage Current (Off State)
IRQA,IRQB
IOFF
-
1
±10
pA
VOH = 2.4V
Vee = 5.25V
200
500
mW
-
10
7.0
20
Power Dissipation
Po
Input Capacitance
00-07, PAO-PA7, PBO-PB7, CA2, CB2
R/W, RES, RSO,RS1,CSO,CS1,CS2
CAl, CB1, \12
CIN
Output Capacitance
COUT
pF
-
-
-
Notes:
1. All units are direct current (dc) except lor capacitance.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. Typical values are shown for Vee = 5.0V and TA = 25°C.
2-34
10
pF
Vee - 5.0V
VIN = OV
1= 2 MHz
TA = 25°C
Peripheral Interface Adapter (PIA)
R6520
PACKAGE DIMENSIONS
40·PIN CERAMIC DIP
D ::III
f,~:
MILLIM~TERS
1M
A
B
C
~---===---"""I
D
F
- - - - - - A ------j.
i~
Hm
~'-
F
.
.
SEATING
0
j
F===1l
PLANEj~ I [
•
G--
I
C
-j~J
G
H
J
K
L
M
N
INCHES
MAX
MIN
MAX
51.31 1.980 2.020
14.86 15.62 0.585 0.615
2.54
4.19 0,100 0.165
038 0.53 0,015 0,021
MIN
50.29
0.76
2.54
0.76
0.20
, .40
0.030 0.055
0.100 esc
0.070
0.33 0.008 0.013
esc
2,54
14.60
0'
0.51
'.78 0030
4,19 ,0.100, 0.165
15,37 0.575 0605
10·
a
1,52 0020
10
0.060
M..,'"
40-PIN PLASTIC DIP
-
MILLIMETERS
DIM MIN
MAX
51,28 5232
A
B
13.72 14.22
5.08
C
355
D
0.36
0.51
1,02
F
1.52
0,140
0.014
0.040
2.060
0.560
0200
0.020
0060
1.65
2.16
0.30
0.100 esc
0065 0.085
0.008 0.012
K
3,56
0.120
H
J
2-35
2.040
'0.540
0.20
3.05
G
2.54
esc
INCHES
MIN
MAX
0.140
0.600 esc
7
10
10
'.02 0.020 0.040
L
15.24 Bse
M
7
N'
0.51
R6522
'1'
R6522
VERSATILE INTERFACE
ADAPTER (VIA)
Rockwell
DESCRIPTION
FEATURES
The R6522 Versatile Interface Adapter (VIA) is a very flexible 110
control device. In addition, this device contains a pair of very
powerful 16-bit interval timers, a serial-to-parallel/parallel-to
serial shift register and input data latching on the peripheral
ports. Expanded handshaking capability allows control of
bidirectional data transfers between VIA's in multiple processor
systems.
• Two a-bit bidirectional I/O ports
• Two 16-bit programmable timer/counters
• Serial data port
• TIL compatible
• CMOS compatible peripheral control lines
• Expanded "handshake" capability allows positive control of
data transfers between processor and peripheral devices.
Control of peripheral devices is handled primarily through two
a-bit bidirectional ports. Each line can be programmed as either
an Input or an output. Several peripheral I/O lines can be
controlled directly from the interval timers for generating
programmable frequency square waves or for counting externally generated pulses. To./acilitate control of the many powerful
features of this chip, an interrupt flag register, an interrupt enable
register and a pair of function control registers are provided.
• Latched output and input registers
• 1 MHz and 2 MHz operation
• Single
+ 5V power supply
ORDERING INFORMATION
Part Number:
R6522
VSS
PAO
PAl
PA2
L '~. n""~_
PA3
PM
PAS
Blank = 40·C to + 70·C
E = 40°C to + B5°C
Package
C = Ceramic
P = Plastic
Frequency
No Letter = 1 MHz
A = 2 MHz
CAl
CA2
RSO
RSl
RS2
RS3
RES
PA6
PA7
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
CSl
CBl
CS2
CB2
VCC
IRQ
DO
01
02
03
04
05
06
07
2
Riw
R6522 Pin Configuration
Document No. 29000047
2-36
Data Sheet Order No. 047
Rev. 7, February 1984
Versatile Interface Adapter (VIA)
R6522
INTERFACE SIGNALS
RESET (RES)
CHIP SELECTS (CS1, CS2)
A low reset (RES) input clears all R6522 internal registers to logic
The two chip select inputs are normally connected to processor
o(except T1 and T21atches and counters and the Shift Register).
address lines either directly or through decoding. The selected
R6522 register is accessed when CS1 is high and ~ is low.
This places all peripheral interlace lines in the Input state, disables the timers, shift register, etc. and disables interrupting from
the chip.
REGISTER SELECTS (RSO-RS3)
INPUT CLOCK (PHASE 2)
The coding of the four Register Select inputs select one of the 16
internal registers of the R6522, as shown In Table 1.
The input Clock is the system rp2 clock and triggers all data
transfers between processor bus and the R6522.
READIWRITE
INTERRUPT REQUEST (IRQ)
(RIW)
The Interrupt Request output goes low whenever an internal
interrupt flag Is set and the corresponding interrupt enable bit is a
logic 1. This output Is open-drain to allow the Interrupt request
signal io be wire-OR'ed with other equivalent signals in the
system.
The direction of the data transfers between the R6522 and the
system processor is controlled by the RW line in conjunction with
the CS1 and CS2 inputs. When R/W is low, (write operation) and
the R6522 is selected), data is transferred from the processor bus
into the selected R6522 register. When R!W is high, (read operation) and the R6522 is selected, data is transferred from the
selected R6522 register to the processor bus.
PERIPHERAL PORT A (PAO-PA7)
Port A consists of eight lines which can be Individuallly programmed to act as inputs or outputs under control of Data Direc.tion Register A. The polarity of output pins is controlled by an
Output Register and input data may be latched into an internal
register iJnder control of the CA 1 line. All of these modes of operation are controlled by the system processor through the internal
control registers. These lines represent one standard TTL load in
the Input mode and will drive one standard TTL load in the output
mode. Figure 2 illustrates the output circuit.
DATA BUS (00-07)
The eight bidirectional data bus lines transfer data between the
R6522 and the system processor bus. During read cycles, the
contents of the selected R6522 register are placed on the data
bus lines. During write cycles, these lines are high-impedance
inputs and data is transferred from the processor bus into the
selected register. When the R6522 is not selected, the data bus
lines are high-impedance.
DO-07
PAO-PA7
<1>2
R6500
MICROPROCESSOR
BUS
INTERFACE
CA1
Rfii
CS1, CS2
RSO-RS3
CA2
2
R6522
VIA
3
CB1
CB2
RES
IRQ
PBO-PB7
Figure 1. R6522 VIA Interface Signals
2-37
PERIPHERAL
INTERFACE
EI
Versatile Interface Adapter (VIA)
R6522
PORT A CONTROL LINES (CA 1, CA2)
The two Port A control lines act as interrupt inputs or as handshake outputs. Each line controls an internal interrupt flag with a
corresponding interrupt enable bit. In addition, CAl controls the
latching of data on Port A input lines. CA1 is a high-impedance
input only while CA2 represents one standard TTL load in the
input mode. CA2 will drive one standard TTL load in the output
mode.
the input mode and will drive one standard TTL load in the output
mode. In addition, they are capable of sourcing 1.0 mA at 1.5 Vdc
in the output mode to allow the outputs to directly drive Darlington
tranSistor circuits. Figure 3 is the circuit schematic.
PORT B CONTROL LINES (CB1, CB2)
The Port B control lines act as interrupt inputs or as handshake
outputs. As with CAl and CA2, each line controls an interrupt
flag with a corresponding interrupt enable bit. In addition, these
lines act as a serial port under control of the Shift Register. These
lines represent one standard TTL load in the input mode and
will drive one standard TTL load in the output mode. CB2 can
also drive a Darlington transistor circuit; however, CBl cannot.
PORT B (PBO-PB7)
Peripheral Port B consists of eight bidirectional lines which are
controlled by an output register and a daia direction register in
much the same manner as the Port A. In addition, the polarity of
the PB7 output signal can be controlled by one of the interval timers while the second timer can be programmed to count pulses
on the PB6 pin. Port 8 lines represent one standard TTL load in
Table 1_ R6522 Register AddreSSing
RS CodIng
Reglstsr
Number
ftlS3
0
0
0
0
0
0
0
0
1
1
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
1
1
Rl:I2
0
<0
R51
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
RSO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Register
Deslg.
ORBIIRB
ORA/IRA
DDRB
DORA
T1C-L
tlC-H
T1L-L
T1L-H
T2C-L
T2C-H
SR
ACR
PCR
IFR
IER
ORA/IRA
Write (RiW - L)
Output Register B
Output Register A
Data Direction Register B
Data Direction Register A
Register/Description
Reed (RIW - H)
I
I Input Register S
T1 Low-Order Latches
Tl High-Order Counter
Tl Low-Order Latches
T1 High-Order LatChes
T2 Low-Order Latches
T2 High-Order Counter
Shift Register
Auxiliary Control Register
Peripheral Control Register
Interrupt Flag Register
Interrupt Enable Register
Output Register S*
I
Input Register A
1
Tl Low-Order Counter
I
1
T2 Low-Order Counter
1
Input Register B*
NOTE: *Same as Register 1 excepl no handshake.
+5V
+5V
INPUT
OUTPUT-----~~\-~
CONTROL
~_--+_ PBO-PB7,
PAO-PA7,
CA2
CB1, CB2
1I0CONTROL~
OUTPUT DATA
OUTPUT-+______~
DATA
--L-/" I
INPUTDATA+---------------------~
INPUT DATA - - - - - - - - - - '
Figure 2. Port A Output Circuit
Figure 3. Port B Output Circuit
2-38
Versatile Interface Adapter (VIA)
R6522
FUNCTIONAL DESCRIPTION
The Intemal orgaiIJzaUon of the R6522 VIA Is Illustrated in Figure
Reading a peripheral port causes the contents of the Input Register (IRA, IRB) to be transfelT8!l onto the Data Bus. With Input
latching disabled, IRA will always reflect the levels on the PA
pins. With input latching enabled, IRA will reflect the levels on the
PA pins at the time the latching occurred (via CA1).
4.
PORT A AND PORT B OPERATIQN
The R6522 VIA has two 8-blt bidirectional 1/0 ports (Port A and
Port B) and eac.h port has two associated control lines.
The IRB register operates similar to the IRA reg1ster. However,
for pins programmed as outputs there is a difference. When
reading IRA, the ·/eve' on the pin determines whether a 0 or a 1 Is
sensed. When reading IRB, however, the bit stored In the output
register, ORB, is the bit sensed. Thus, for outputs which have
large loading effects and which pull an output "f" down or which
pull an output "0" up,reading IRA may result in reading a "0"
when· a "1" was aCtually programmed, and reading· a "1" when
a "0" was programmed. Reading IRB, on the other hand, will
read the" 1" or "0" level actuallY programmed, no matter what
the loading on the pin.
Each 8-blt peripheral port has a Data Direction Register (DDRA,
DORB) for Specifying whether the peripheral pins are to act
inputs or outputs. A 0 in a bit of the Data Direction Register
causes the corresponding perlpherel pin to act as an input. A 1
causes the pin to act as an output.
.
as
Each peripheral pin is also controlled by a bit in the Output Register (ORA, ORB) and the Input Register (IRA, IRB). When the pin is
programmed as an output, the voltage on the pin is controlled by
the corresponding bit of the Output Register. A 1 In the Output
Register causes the output to go high, and a "0" causes the outputto go low. Data may be written into Output Register bits corresponding to pins which are programmed as Inputs. In this case,
however, the output signal Is unaffected.
INTERRUPT
CONTROL
FLAGS
(IFR)
Figures 5 through 8 illustrate the formats of the port registers.
In addition, the input latching modes are selected by the Auxiliary
Control Register (Figure 14).
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IRQ
NPUTLATCH
(IRA)
-OUTPUT--
-ENASLE-
PORTA
(ORA)
(IER)
-DATA-OIFf
DATA
BUS
(DDRA)
r-:PO:RT~:A~I~----~~--~---CAl
________ 1-------- CA2
0
PORT B
LATCH
(Tl L-H)
RES
RIW
'LATCH
(Tl L-LI
!
COUNTER1COUN;r"ER
(Tl C-H)
2
CSl
CS2
ACCESS
RSO
CONTROL
CHIP
II
HANDSHAKE
CONTROL
rsS~HliFFTiiR~E~Gl..----J-L------_ CBl
LJ(!!SR!)_.r---e...---- CB2
: (Tl C-L)
TIMER 1
INPUT LATCH
(IRB)
--------
RSl
RS2
OUTPUT
(ORB)
RS3
-DATA-Diif
(DDRE)
Figure 4. R6522 VIA Block Diagram
2-39
PORTB
R6522
Versatile Interface Adapter (VIA)
HANDSHAKE CONTROL OF DATA TRANSFERS
The R6522 allows positivjl control of data transfers between the
system proc:es!lOr and peripheral devices through the operation
of "handshake" lines. Port A lines (CA1, CA2) handshake data
on ~h a read and a write operation while the Port B lines (CB1 ,
CB2jhandshake ona write operation only.
data, causing generation of a "Data Taken" signal. The peripheral device responds by making new data available. This process
continues until the data transfer is complete.
In the R6p22, automatic "Read" Handshaking is possible on the
Peripheral A port only. The CA1 interrupt input pin accepts the
"Data Reaely" signal and CA2 generates the "Data Taken" signal. The "Data Reaely" signal will set an intemalflag which may
interrupt the proces.sor or which may be polled under program.
control. The "Data Taken" signal ca.n either be a pulse or a level
which is set low by the system processor and is clear8(l by the
"Data Reaely" .signal. These options are shown in Figure 9 which
illustrates the normal Read Handshake Sequence.
Read Handshake
Positive. control of data transfers from periphera.l devices into the
system processor can be accOmplished very effectively uSil'1g
Read Handshaking. In this case, the peripheral device must generate the equivalent of a'''Oata Ready" signal to the processor
signifying that valid data is present on the pelipheral port; T~is
signal normally interrupts the processor, which then reads the
REG O--oRB/IRB
REG 1-0RAlIRA
t'I 1'I 1'I , lot
4
6
2
~'BO
'AO
'B'
P02
PB'
'B4
'B'
PA'
OUTPUT REGISTER
"B" (ORB) OR
INPUT REGISTER
"B" (IRB)
' - - - - - - 'A4
'-------PA'
1..-------
PB6
P46
I..-_ _ _ _ _ _ PA'
P9'
PIN
DATA OIRECT1ON
BEL"""ON
OUTPUT REQISTER
"A" (ORA) OR
INPuT REGISTER
"A" (IRA)
PA2
I..-~-- PA,
WArn;
PIN
DATA DIRECTION
READ
WRIlE
READ
SELECl10N
COM .. "1" (Olm"JT)
MPUWRI'TES OI..rTPUTLEYEL.
(ORB)
00R8 .. ''0'' (INPUT)
MPU WRITES INTO ORB, BUT
NO EF.FEOT ON PIN LEVa.,
(INPlIT LATCHING DISABLED)
MPU READS OUTPUT .REGISTeR
81T IN OAB. PIN lEVEL HAS NO
AFf'ECT
CORA .. "," (OUTPUT)
MPU WAITES OUl'PlIT LEvel
(INPUT LATCHING DI8A8l.ED)
(ORA)
DORA - "1" (Oum.JT)
(INPUT LATCHNG ENABLED)
MPU READS INPI1T LEVEL ON PH
MPUREAOSlRABITWHlCHlSTHE
LEVEL OF THE PA PIN ATTHE TIME
OF THE LAST CA1 ACTIVE
TRANsmON
PIN
UN'T1L ~RE! CHANGED
DDAB .. "0" (WUT)
(INPUT LATCItNG ENABLED)
DDAA ... "f1' (INPUt)
(INPUT LATCHING DISABLED)
MPUFIEADSIRBBIT,WHICHISTHE
L!VE1..OFTHEPBPlNATTHETIME
OF THE LAST C81 ACTIVE
=-(:::"p""un=---i
......smON
i-::DDRA=-."",....
MPU READS LEVEL ON PA PIN
MPUWRITES INTO ORA, BUT
NO EFf&CT ON PIN LEVEL
MPU READS LEVEL ON PA PIN
MPU READS !MBIT. WHICHISTHE
UNTlL DORA CHANGED
(INPUT LATCHING ~D)
LEVELOFTijEPAPINATTHETIME
OF THE LAST CA1 ACTIVE
TAANSmON
Figure 5. Output Register B (ORB). Input Register .B (lAB)
Figure 6. Output Reglater A (ORA). Input Register A (IRA)
REG2-DDRB
REG3-DDRA
1'101,1+1 1,1 1
2
0
~··o
'8'
E
P.AO
PA'
P82
'B'
' - - - - - _ PB4IPA4
'A2
DATA DIREctiON
REGiSTER "B" (DDRB)
PA'
PA4
' - -_ _ _ _ _ PBS/PAS
PA'
' - -_ _ _ _ _ _ PB6/PA6
PAS
L...-_ _ _ _ _ _ _ PB7/PA7
"0"
'A'
ASSOCIATED PB PIN IS AN INPUT
"0"
ASSOCIATED PA PIN IS AN INPUT
"1"
(HIGH IMPEDANCE)
ASSOCIATED PA PIN IS AN OUTPUT
WHOse LEVEL IS DETERMINED BY
(HIGH IMPEDANCE)
"1"
DATA DIRECTION
REGISTER "A" (DDRA)
ASSOCIATED PB PIN IS AN OUTPUT
WHOSE LEVEL IS DETERMINED 9Y
ORB REGISTER BIT
ORA REGISTER BIT
Figure 7. Data Direction Register B (DDRB)
Figure 8. Data Direction Register A (DDRAO)
2-40
Versatile Interface Adapter (VIA)
R8522
....rLJ'"L...rL
1/>2
DATA READY
(CA1)
I
. IRQ OUTPUT
I
j
'I
I
R
I,
II
fJ
~ll
N
PU~E"ODE
I
~I
:
READ IRA OPERATION
"DATA TAKEN"
HANDSHAKE "ODE
(CA2)
"DATA TAKEN"
.1
(CA2)
Figure 9. Read Handshake Timing (Port A, Only)
Write Handshake
The sequence of operations which alloWs handshaking dala from
the system processor to a peripheral device is' very similar 10 thai
described for Read Handshaking. However, for Write Hands\laklng, the R6522 generates the "Oata Ready" signal and the
peripheral device must respond with Ihe "Data Taken" signal.
This can be accomplished on both the PA port and the PB port on
the R6522. CA2 or CB2 act as a "Oata Ready" output in either
the handshake mode or pulse mode and CA1 or CB1 accept the
"Data Taken'" signal from the peripheral device, setting the interrupt flag and clearing the "Data Ready'" output. This sequence
is shown in Figure 10.
REG 12-PERIPHERAL CONTROL REGISTER
"'_""'''''''0'
C82CONTROL~
TICA',NTERRUPT CONTROL
1 6 5 OPERATION
o 0 0 INPUT·NEGATIVE ACTIVE EDGE
o 0 1 INDEPENDENT INtERt:lUPT
.
CA2CONTROL
INPUT·NEG,EDGE
Q 1 0 INPUT-POSITIVE ACTIVE EDGE
o
1 1 INDEPENDENT INT£RRUPT
INPUT·POS EDGE
,
,
,.
1
0
0
,.
1
3 2 I OPERATION
0 0 INPUT·NEGATIVE ACTIVE EDGE
o
U 0 1 INDEPENDENT INTERRUPT
IflipUT ·NEG EDGE
0 HANDSHAKE OUTPUT
1 PULSE OUTPUT
0 LOW OUTPUT
1 HIGH OUf1I'UT
CB1 INTERRUPT CQt4TROL
Selection of operating modes for CA1, CA2, CB1, and CB2 is
accomplished by the Peripheral Control Register (Agure 11).
I~ • POSITIVE ACTIVE EDGE
~ NEGATIVE AcnvE eDGE
0" NEGATIVE ACTIVE EDGE
1 '" POSITIVE ACTIVE EDGE
o ,. 0 IIIIPUT·PQ:ITIVE ACTIVE EDGE
o ,. ,. INDEPENDENT INTERRUPT
INPUT·pen EPt.E
1 0 0 HANDSHAKE OUTPUT
'" 0 I PULSE OUTPUT
1 ,. 0 LOW OU1PUT
,. 1 1 I=tIGI-I OU:rPUT
I
. Figure 11. Peripheral Control Register (PCR)
4>2~1l~1l~'
I . I.
.
. ,
,
WRITE ORA. OR"
"D':r~":~~:Y"
HANDSHAKE ..ODE
. I
I
IIII
'.
.
. llllll.'
(CA2. CB2)
DATA READY - - - - - .
r--ll-ll-----I~----PULSE MODE
'----'
(CA2, CB2)
"DATA TAKEN
I
(CA1, CB1)
I
U
iRa OUTPUT
-rI I
·1
I
.I
'1(,
.1f2?7«V4!.zz:l.
j
I
..r-
Figure 10. Write Handshake TIming
2-41
.·.. 1. ,.
II .
I
Versatile Interface Adapter (VIA)
R6522
COUNTER/TIMERS
There are two Independent til-bit counter/timers (called Timer 1
and Timer 2) In the R6522. Each timer Is controlled by writing bits
into the Auxiliary Control Register (ACR) to select. the mode of
operation (Figure 14).
the latches Into the counter and continues to decrement. In addition, the timer may be programmed to Invert the output signal
on a peripheral pin (PB7) each time it "times-out". Each of these
modes is discussed separately below.
Timer 1 Operation
Note that the processor does no/write directly into the low-order
counter (T1 Col). Instead, this half.olthe countei" is loaded automatically from the low order latcp (TtL-L) when. the processor
writes into the high order counter (T1 C-H).lnfact, it may not be
necessary to write to the low order countEk. in·some applications
since the timing operation is triggered by writing to the. high order
latch.
Interval Timer T1 consists of two S-bit latches (Figure 12) and a
16-bit counter (Figure 13). The latches store data which is.to be
loaded into the counter. After loading, the counter decrements
at 02 clock rate. Upon reaching zero, an interrupt flag is set, and
IRQ goes low if the T1 interrupt is enabled. Timer 1 then disables
anv further interruDts. or automattcallv transfers thecofltents of
REG 6-TIMER 1 LOW-ORDER LATCH
REG 7-TIMER 1 HIGH-ORDER LATCH·
1,16151_131'1'101
I~4096
L. ·.~
~.LL=. • . ~ : CO"~
~
COUNT
VALUE
VALUE
'--_-----3'
81'92
'--'-'----~---
'---~-----~
'---·_·_-;-,-_ _ _ _ 128
'---~----''--------
WRITE - 8 BITS LOADED INTO T1 LOW-ORDER
LATCHES. THIS OPERATION IS NO
DIFFERENT THAN A WRITE INTO
16384
3'768
WRITE - 8 BITS LOADED INTO T1 HIGH-ORDER
LATCHES. UNLIKE REG 4 OPERATION
, NO LATCH-TO·COUNTER TRANSFERS
TAKE PLACE.
REG-4.
READ - 8 BITS FROM T1 LOW-OADER LATCHES
TRANSFERRED'TO MPU. UNLIKE REG 4
READ - 8 BITS FROM T1 'HIGI't-QROER LATCHES
TRANSFERRED TO MPU.
OPERATION, THIS OOES NOT,CAUSE
RESET OF T1 INTERRUPT FLAG
Figure 12. Timer 1 (T1) Latch Registers
REG 4'-TIMER 1 LOW-ORQER .COUNTER
REG 5-TIMER 1 HIGH-ORDER COUNTER
COUNT
VALUE
'---.,--.---16
COUNT
VALUE
'--------8192
'---------16384
'----------32768
'--------32
'-----'--'-----6.
'----'---------128
WRITE - 8 BITS LOADED INTO T1 LOW.QRDEFI
LATCHES. LATCH CONTENTS ARE
TRANSFERRED INTO LOW-ORDER
COUNTER ,AT THE TIME THE HIGH·
ORDER COUNTER IS LOADED (REG 5).
READ - B BITS FROM T1 LOW-ORDER COUNTER
TRANSFERRED TO MPU. IN ADDITION,
T1 INTERRUPT FLAG IS RESET (BIT 6
IN INTERRUPT FLAG REGISTER).
WRITE - B BITS LODED INTO T1 HIGH-ORDER
LATCHES. ALSO, AT THIS TIME BOTH
HIGH· AND L.OW·ORDER L.ATCHES
TRANSFERRED INTO T1 COUNTER.
T1 INTEPIRUPT FLAG ALSO IS RESET.
READ - 8 IBTS FROM T1 HIGH-ORDER COUNTER
TRANSFERRED TO MPU.
Figure 13. Timer 1 (T1) Counter Registers
2-42
Versatile Interface Adapter (VIA)
R6522.
REG 11-AUXlLIARY CONTROL REGISTER'
'. . ,6'1'"".'I1'"•..,.....,
13,-,'1'"
I,T'0'"
,r-,"T,
T
T1 TIMER CONTROL.
1 6 ()PEAATION
o 0 TIMEO INTERRUPT
pe7
EACH TIME T1 IS
LOADED
o
1 CON'tINUOUS
,
Q
DISABLED
INTERRUPTS
TIMED INTERRUPT
EACH TIME T1 IS
ONE·SHOT
OUTPUT
~OADED
,
~'''QUARE
1, ONTINUOUS
INTERRUPTS
WAVE
OUTPUT
5 OPERATION' '.'
o
TIME INTERRUPT
, COUNT DOWN WITHl
PULSES ON PBS
I
Flglire14. Auxiliary Control Reglal.r (ACR)
Timing for the R6522 Interval timer one-shot modes Is shown in
Figure 15.
Timer 1 One-Shot Mode
The Timer 1 one:.shot mode generates a single interrupt for each
timer load operation. As with any interval timer; the delay
between the ''write T1 C_H" operation and generation of the processor Interrupt is a direct function of the data loaded. into the tim.Ing counter. In addition to generating a single"interrupt,. Timer 1
can be programmed to produce a single negative pulse on the
PB7 periphral pin. WithJhe output enabled (ACfl7=1) a :'wrile
T1C-H" operation will cause PB7 to go low. PB7 will return high
when Timer 1 times out. The' result is a single programmable
width pulse.
'
In the one-shot mode, writing into the T1 L-Hhas no effect on the
operation of Timer 1. However, it will be necessary to assure that
the low order latch contains the proper data before initiating the
count-down wHh a "write T1 C_H" operation. When the processor
writes Into the high order counter (T1 C-H), the T1 interrupt flag
win be cleared, the contents oUh.!I low .order latch win be
transferred into the low order counter, and tlie timer will begin to
decrement at system clock rate. If the PB7 output Is enabled; this
signal will go low on the 2 following the write operation.
When the counter reaches zero, theT1 Interrupt flag .will be set,
the IRQ pin will go low (interrupt enabled), and ti11i sigrial on PB7
will go high. At this time the counter will continue to decrement at
system clock rate. this allows the system processor to read the
contents of the counter to determine the time since Interrupt
However, the T1 interrupt flag cannot be set again unless it has
been cleared as described in this specification.
T1 interrupt flag wlU be set, the IRQ pin will go \ow (interrupt enabled), and the signal on PB7will go high. Atthis time the.counter
will continue to decrement at syStem clock rate. This allows the
system processor to read the conteirts of the counter to determine the time since interrupt. However, the T1 interrupt flag cannot be set again unless it has been cleared as described in this
specifiCation.
I I'
WRITE T1C-H
IRQ OUTPUT
---III
Ii
----.....;-+.-----------.,;I}?.....;---,;,...;~
~--~~----------
o
, Figure 15. Timer 1 One-Shot Mode Timing
2-43
I N-1 I N-2 I N-3 I
R6522
Timer 1
Versatile Interface Adapter (VIA)
Fre~Run
counter will always re-initialize the time-out period. In fact, the
time-out can be prevented completely if the processor continues
to rewrite the timer before it reaches. zero. Timer t will operate in
this manner if the processor writes into the high order counter
(TI C-H). However, by loading the latches only, the processor can
access the timer during each down-counting operation without
affecting the time-out in process. Instead, the data loaded into
the latches will determine the length of the next time-out period.
This capability is particularly valuable in the free-running mode
with the output enabled. In this mode, the signal on PB7 is
inverted and the interrupt flag is' set with .each time-out. By
responding to the inter~upts with new data for the latches, the
processor can.determine the period of the next half cycle during
eaCh half· cycle of the output sigrial on .PB7. In this manner, very
complex waveforms can be generated.
Mode
The most important advantage associated with the latches in Tl
is the ability to produc,e a continuous series of evenly spaced
interrupts and the ability to produce a square wave on PB7
whose frequency is riot affected by variations in the processor
interrupt response time. This is accomplished in the "freerunning" mode.
In the free-running mode, the interrupt flag is set and the signal
on PB7 is inverted each time the counter reacheS zero. However,
instead of continuing to decrement from zero after a time-out, the
timer automatically transfers the contents of the latch into the
counter (16 bits) and continues to decrement from there. The
interrupt flag can be clearap by writing T1 C-H,by. reading Tl Col,
or by writing directly into the flag as described later. However, it is
not necessary to rewrite the timer to enable setting the interrupt
flag on the next time-out.
A precaution to take in the use of PB7 as the timer output concerns the Data Direction Register contents for PB7. 80th DDRB
bit 7 andACR bit 7 must be 1 for PB7 to function as the timer output. If one is 1 and the other is 0, then PB7 functions as a normal
output pin, controlled by ORB bit 7.
All interval timers in the R6522 are "re-triggerable". Rewriting the
¢2~
~:~~~~~~H ~~ --------r---~--------~----------~-------IRQ OUTPUT
PB7 OUTPUT
I
"
~~(------~~------~i:~;----~~~--~
k
N + 1.5 CYCLES
j'
-,-~.I~·---~ N + 2 CYCLES ---~.~I
Figure 16. Timer 1 Free-Run Mode Timing
Timer 2 Operation
decrementing again through zero. The processor must rewrite
T2C~H to enable setting of the inierrupt flag.' The interrupt flag
is cleared by reading T2C-L or by writing T2C-H. Timing for this
operation is shown in Figure 18.
Timer 2 operates as an interval timer (in the "one-slot" mode
only), or as a counter for counting negativ$ pulses on the PB6
peripheral pin. A single control.bit in the Auxiliary Control Register
selects between these two modes. This timer is comprised of a
"write~only" lower-order latch (T2L-L), a "read~only" low-order
counter (T2C-L) and a read/write high order counter (T2C-H).
The counter registers act as a IS-bit counter which decrements
at 02 rate. Figure 17 illustrates the T2Latch/Counter Registers.
Timer 2 Pulse Counting Mode
In .th$ pulse counting mode, T2 counts a predetermined number
of negative-going pulses on .PBS. This is accomplished by first
loading a numb$r Into T2. Writing into T2C-H clears the interrupt
flag and allows the counter to decrement each time a pulse is
applied to PBS. The interrupt flag is set when T2 counts down
past zero. The counter will then continue to decrement with each
pulse \'lnPB6. However, it is necessary to rewrite T2C-H to allow
the interrupt flag to set on a subsequent time-out. Timing for
this mode is shown in Figure 19. The pulse must be Iowan .the
. leading edge of <1>2.
Timer 2 One-Shot Mode
As an interval timer, T2 operates in the "one-shot" mode similar
to Time 1. In this mode, T2 provides a single .interrupt for each
"write T2C-H" operation. After timing out,4he counter will continue to decrement. However, setting of' the interrupt flag is
disabled after initial time-out so that it will not be set by the counter
2-44
Versatile Interface Adapter (VIA)
R6522
REG 9-TIMER 2 HIGH-ORDER LATCH/COUNTER
REG 8-TIMER 2 LOW-ORDER LATCH/COUNTER
256
512
fJ
1024
'-____ 1.
....
COUNT
VALUE
COUNT
VALUE
2048
L...._ _ _ _ _ 32
8192
' -_ _ _ _ _ _ 64
1638.
L...._ _ _ _ _ _ _ 128
31788
WRITE -
8 BITS LOADED INTO T2 LOW·ORDER
READ -
8 BITS FROM 12 LOW.()RDER COUNTER
WRITE -
LATCH
8 BITS LOADED INTO T'! tUGH·ORDER
COUNTER. ALSO, LOW ORDER LATCH
T-AANSFERREO TO LOW·ORDER
COUNTER. IN ADDITION, 12 INTeRRUPT
TRANSfERRED TO MPU. 12 INTERRUPT
FLAG IS RESET.
READ -
FLAG IS RESET.
8 BITS FROM T2 HIGH-ORDER COUNTER
TRANSFERRED TO MPU.
Figure 17. Timer 2 (T2) Latch/Counter Registers
,j'
WRITE T2C·H
IRQ OUTPUT
N
N·l
I N·2 I N-3 I
.1-------
N
I
o
N·l
I
N·2
I
N-3
+ 1.5 CYCLES -----.-...1
Figure 18. Timer 2 Ona-Shot Mode Timing
WRITE T2C-H
OPERATION
PB61NPUT
........,
~
1________------------------------------------------;/
u
u
u
u
IRQ OUTPUT
N
N·2
N·l
II
Figure 19. Timer 2 Pulse Counting Mode
2-45
o
-1
I
Versatile Interface Adapter (VIA)
R6522
SHIFT REGISTER OPERATION
The shifting operation is triggered by the read or write of the SR
if the SA flag is set in the IFA. Otherwise the first shift will occur
at the next time-out of T2 after a read or write of the SA. Data
is shifted first into the low order bit of SR and is then shifted into
the next higher order bit of the shift register on the negative-going
edge of each clock pulse. The input data should change before
the positive-going edge of the CBI clock pulse. This data is shifted
into the shift register during the 02 clock cycle following the
positive-going edge of the CBI clock pulse. After 8 CBI clock
pulses, the shift register interrupt flag will set and IRQ will go low.
The Shift Register (SA) performs serial data transfers into and
out of the CB2 pin under control of an internal modul0-8 counter.
Shift pulses can be applied to the CB 1 pin from an external
source or, with the proper mode selection, shift pulses generated
internally will appear on the CBl pin for controlling external
devices.
The control bits which select the various shift register operating
modes are located In the AUXiliary Control Aegister. Figure 20
illustrates the configuration of-the SA data bits and Figure 21
shows the SA control bits of the ACA.
SR Mode 2 ..,.. Shift In Under <1>2 Control
SR Mode 0 - Disabled
In mode 2, the shift rate is a direct function of the system clock
frequency (Figure 23). CBl becomes an output which generates
shift pulses for controlling external devices. Timer 2 operates as
an independent interval timer and has no effect on SA. Th.e shifting operation is triggered by reading or writing the Shift Register.
Data is shifted, first into bit 0 and is then shifted into the next
higher order bit of the shift register on the trailing edge of each <1>2
clock pulse. After 8 clock pulses, the shift register interrupt flag
will be set, and the output clock pulses on CBl will stop.
Mode 0 disables the Shift Register. In this mode the microprocessor can write or read the SA and the SR will shift on each CBl
Positive edge shifting in the value on CB2. In this mode the SR
Interrupt Flag is disabled (held to a logic 0).
SR Mode 1 -
Shift In Under ContrOl. of T2
In mode 1, the shifting rate is controlled by the low order 8 bits of
T2 (Figure 22). Sl\ift pulse.s are generated on the CBl pi('l.to control shifting in external devices. The time between transitions of
this output clock is a function of the system clock period and the
contents of the low order T2 latch (N).
REG 10-SHIFT REGISTER
REG 11-AUXILIARY CONTROL REGISTER
I'I'I'~
1,1+1-1+1,101
JJ...L
L
SHIFT
REGISTER
BITS
SHIFT REGISTER
MODE CONTROL
4
0
0
0
0
NOTES:
,. WHEN SHIFTING OUT. BIT 7!S THE FIRST BIT
OUT AND SIMUl TANEOUSLY IS ROTATED BAck
1
1
1
1
0
, 0,
INTO BIT O.
2.
3
0
0
~:iEoNAS~6F;~~~$F~~T; i6~1~LDLS\~~~~A
1
Figure 20. Shift Registers
,
2
OPERATION
0
DISABLED
1
0
1
0
1
0
1
SHIFT IN uNDER CONTROL OF T2
SHIFT IN UN.DER CONTROL OF 'I'
SHIFT IN UNDER CONTROL OF EXT eLK
SHIFT OUT FREE·RUNNING AT T2 RATE
SHIFT OUT UNDER CONTROL OF T2
SHIFT OUT UNDER CONTROL OF "'2
SHIFT OUT UNDER CONTROL OF EXT eLK
Figure 21. Shift Register Modes
<1>2
WRITE OR READ
SHIFT REG
IRQ
----'
Figure 22. SR Mode 1 -
Shift In Under T2 Control
2-46
Versatile Interface Adapter (VIA)
R6522
T2. However, in mode 4 the SR Counter does not stop the shifting
operation (Figure 25). Since the Shift Register bit 7 (SR7) is
recirculated back into bit 0, the 8 bits loaded into the shift register
will be clocked onto CB2 repetitively. In this mode the shift register counter is disabled.
SR Mode 3 - Shift In Under CB1 Control
In mode 3, external pin CBl becomes an input (Figure 24). This
allows an external device to load the shift register at its own pace.
The shift register counter will interrupt the processor each time 8
bits have been shifted in. However, the sh)ft register counter
does not stop the shifting operation; it acts simply as a pulse
counter. Reading or writing the Shift Register resets the Interrupt
Flag and initializes the SR counter to count another 8 pulses.
SR Mode 5 - Shift Out UnderT2 Control
.In mode 5, the shift rate is controlled by T2 (as in mode 4). The
shifting operation Is triggered by the read .or write of the SR if the
SR flag is set in the IFR (Figure 26). Otherwise the first shift will
occur at the next time-out of T2 after a read or wrHe of the SA.
However, with each read or write of the shift register the SR
Counter is reset and 8 bHs are shifted onto CB2. At the same
time, 8 shift pulses are generated on CBl to control shifting in
external devices. After the 8 shift pulses, the shifting is disabled,
the SR Interrupt Flag is set and CB2 remains at the last data
level.
Note that the data Is shifted during the first system clock cycle following the positive-going edge of the CBl shift pulse. For this
reason, data must be held stable during the first full cycle following CBl going high.
SR Mode 4 - Shift Out Under T2 Control (Free-Run)
Mode 4 is very similar to mode 5 in which the shifting rate is set by
Figure 23. SR Mode 2 - ShIH In Center 2 Control
Figure 24. SR Mode 3 - Shift In Under CBl Control
",2
WRITE SR
--.Jl
I I.....+--I_+.~!--+_+_I--+_+--II
I
I I I I __I' - I
~8
9
N + 2 CYCLES+-------+----+
CB10UTPUT
1
SHIFT CLOCK
X
CB2 INPUT _'»~\~
......--'-_..J.
DATA
-
Figure 25. SR Mode 4 -
2
X
.
3
8
Shift Our Under T2 Control (Free-Run)
2-47
x:::::c
II
Versatile Interface Adapter (VIA)
R6522
SR Mode 6 - Shift Out Under c/J2 Control
Interrupt Flag each time it counts8 pulses but it does riot disable
the shifting function. Each time the microprocessor,. writes or
reads the shift register, the SR Interrupt Flag is reset and the SR
counter is initialized to begin counting the next 8 Shift pulses on
pin CBl. After 8 shift pulses, the Interrupt Flag is set. The
microprocessor can then load the shift register with the next byte
of data.
In mode 6, the shift rate is controlled by the <1>2 system clock (Figure 27).
SR Mode 7 -
Shift Out Under CB1 Control
In mode 7, shifting is controlled by pulses applied to the CBl pin
by an external device (Figure 28). The SR counter sets the SR
,JL1Lf1SLI"l-
<1>2
WRITE SR
!--
--t:l~2CCYYcC:LLEEiSi:\:I. ==::.t:I.==::::::.~INi++22~cyrcc:t~E5sSi---t--iL--/.-..-i-il--8---71
=.
~=:F~~~6~~ - - - - - -.....1
1-1----11
2
1-1--'---'1.----=3;......-I! / I !
g:~~UTPUT -'\~'lli\B,~__'_ ___=___...JX'-_~2=____...JX'__...::.3--1/P
.
___
8=--+-!_ __
I
Figure 2.6. SR MOde 5 - Shift Out Under T2 Contro.1
I
WRITE SR
I
-----.rlL-._-+---+_-+---+_-+---+_+---+_-+_+--+_+-____
CB10UTPUT
SHIFT CLOCK
CB2 OUTPUT
DATA
~~'*'\\~'\~"\\~~'-----4_..:8~__
~f--:!---A---!-J
Figure 27. SR Mode 6 - Shift Out Under q,2 Control
<1>2
WRITESR
CB1 INPUT
SHIFT CLOCK
~
~ =~I
I
1.._ _....1
CB2 OUTPUT ~.-------:'---~X
DATA
2
r;81·;
I
Figure 28. SR Mode 7 - Shift Out Under CBl Control
2-48
Versatile .Interface Adapter (VIA)
R6522
Interrupt Operation
Controlling interrupts within the R6522 involves three principal
operations. These are flagging the interrupts, enabling interrupts
and signaling to the processor that an active interrupt exists
within the chip. Interrupt flags are set in the Interrupt Flag Register (IFR) by conditions detected within the R6522 or on inputs to
the R6522. These flags normally remain set until the interrupt
has been serviced. To determine the source of an interrupt, the
microprocessor must examine these flags in order, from highest
to lowest priority.
Associated with each interrupt flag is an interrupt enable bit in
the Interrupt Enable Register (IER). This can be set or cleared
by the processor to enable interrupting the processor from the
corresponding interrupt flag. If an interrupt flag is set to a logic 1
by an interrupting condition, and the corresponding interrupt
enable bit is set to a 1, the Interrupt Request Output (IRQ) will
go low. IRQ is an "open-collector" output which can be "wireOR'ed" with other devices in the system to interrupt the processor.
Interrupt Flag Register (IFR)
In the R6522, all the interrupt flags are contained in one register,
i.e., the IFR (Figure 29). In addition, bit 7 of this register will be
read as a logic 1 when an interrupt exists within the chip. This
allows very convenient polling of several devices within a system
to locate the source of an interrupt.
The Interrupt Flag Register (IRF) may be read directly by the processor. In addition, individual flag bits may be cleared by writing
a "1" into the appropriate bit of the IFA. When the proper chip
select and register signals are appplied to the chip, the contents
of this register are placed on the data bus. Bit 7 indicates the
REG 13-INTERRUPT FLAG REGISTER
!7!.! 5!-13!2!'!0!
l,
SET BY
LCA2 CA2 ACTIVE EDGE
CB2
CB'
TIMER 2
LTIMER 1
IRO
CB2 ACTIVE EDGE
CB1 ACTIVE EDGE
TIME-OUT OF T2
SHIFT REG
READ OR WRITE ORBREAD OR.· AITE ORB
READ T2 l.OW OR
WRITE T2 HIGH
ANY ENABLED
INTERRUPT
OR.
READ T1 LOW OR
WRITE T1 HIGH
CLEAR All
INTERRUPTS
• IF THE CA2/CB2CONTROl tN THE peA ISSELECTED AS
"INDEPENDENT" INTERRUPT INPUT, THEN READING OR
WRITING THE bUTPUT REGISTER ORA/ORB WILL NOT
CLEAR THE FLAG BIT. INSTEAD, THE.9'IT MUST BE
CLEARED BY WRITING INTO THE IFR. AS DESCRIBED
PREVIOUSLY.
Figure 29. Interrupt Flag Register (IFR)
II
The" IFR. bit 7 is. no,t a flag.. Theref.,ore, this bit. is not directly Cleared. ,
by wdting a logic 1 into it. It can only be cleared by clearing all the
flags in the register or by disabling all the active interrupts as dis-.
cussed in the next'section.
.Interrupt Enable Register (IER)
For each interrupt flag in IFR, there is .acorresponding bit in the
Interrupt Enable Register (IER) (Figure 30). Individual bits in the
IER can be selor cleared to facilitate controlling individual interrupts without affecting others. This is accomplished by writing to
the (IER) after bit 7 set or cleared to, in turn, set or clear selected
enable bits. If bit 7 of the data placed' on the system data bus
during this write operation is a 0, each 1. in bits 6 through 0 clears
the corresponding bit in the Interrupt Enable Register. For each
zero in bits 6 through 0, the corresponding bit is unaffected.
Selected bits in the IER can be set by writing to the IER with bit 7
in the data word set to a 1. In this case, each 1 in bits 6 through 0
will set the corresponding bit .. For each zero, the corresponding
bit will be unaffected. This individUal control of the setting. and
clearing operations allows very convenient control of the interrupts during system operation.
In addition to setting and clearing IER bits, the 'contents of this
register can be read at any time. Bit 7 will be read as a logic 1,
however.
CLEARED BY
READ OR WRITE
REG' (ORAl'
READ OR WRITE
REG lORA)
READ OR WR ITE
TIME-OUT-OF Tt
Note:
x = logic AND,· += Logic
REG 14-'NTERRUPT ENABLE REGISTER
COMPLETE 8 SHIFTS
CAl--- CA1 ACTIVE EDGE
SHIFT REG
status of the IRQoutpul. This bit corresponds to the logic, function: IRQ = IFR6 x IER6 + IFR5 x IERS + IFR4 x IER4 +
IFR3 x IER3 + IFR2 x IER2 + IFR1 x IER1 + IFRO x-IERO.
1'1-1
jl iii' jllh~"."
TIMER 2
o=
INTERRUPT
DISABLED
='NTERRUPT
ENABLED
' - - - - - - - - TIMER 1
'---------SET/CLEAR
NOTES;
1. IF BIT liS A "0", THEN EACH "'" IN BITS 0 ~ 6 DISABLES THE
CORRESPONDING INTERRUPT.
.
.
2. IF BIT 115 A"''', THEN'EACH "1" IN BITS 0 - 6 ENAI!LES THE
CORRESPONDING INTERRUPT.
3. _'F A READ OF THIS REGISTER IS DONE,_ BIT 7 ~llL BE "1" AND
ALL OTHER BITS WILL REFLECT THEIR ENABLE/DISABLE STATE.
Figure 30. Interrupt Enable Register (IER)
R6$~2
Versatile Interface Adapter (VIA)
PERIPHERAL INTERFACE CHARACTERI$TICS
Symbol
Charactertstlc
Figure
Min.
Max.
Unit
t" ~
Rise and Fall Time for CAl. CB1, CA2 and CB2 Input Signals
-
1.0
-
tCA2
Delay Time, Clock Negative Transition to CA2 Negative Transition (read handshake or
pulse m o d e ) " c
' . .
1.0
p.S
31a,31b
t Rs ,
Delay Time, Clock Negative Transition to CA2 Positive Transition (pulse mode)
-
"S
1.0
1'5.
31a
tRS2
Delay flrne, CAl Active Transition to CA2 Positive 'Transition (handshake mode)
-
2.0
p.S
31b
0.05
1.0
"S
31c, 31d
0.20
1.5
"S
31c,31d
-
1.0
'tWHS
Delay Time, Clock Positive Tr.ansitionto CA2 or CB2 Negative Transition
(write handshake)
to CB2 Nega\ive Transition
los
Delay Time, Peripheral Data Valid
t RS3
DelaY Time, Clock Positive Transition to CA2 or CB2 Positive Transition (pulse. mode)
"S
31c
tRS4
Delay Time, CAlor CBl Active Transition to CA2 or CB2 Positive Transition
:.
(handshake mod~)
-
2.0
p.S
31d
· t2,
Delay Time Required from CA2 Output to CAl Active Transition (handshake mode)
400
-
ns
tii..
Setup Time, Peripheral D'ataValid to CAlor CBl Active Transition (input latching)
300
-
ns
31e
CAl, CB1~etup P~iorto Transition to Arm Latch
300
-.'.
ns
31e
31e
...
tAL
tpDH
. '.' Peripheral Data Hold After CA 1, CB 1 Transition
Shift-Out Delay Time ...::. Time froin2Fitiling Edge to CB2 Data Out
tSR2
Shift·ln Setup Time...;.. Time from CB2 Data Into <1>2 RsingEdge
.tSR3
,
External Shift· Clock. (CB1) .Setup Time Relativetd <1>2 Trailing Edge
:tl"w
PulSe Width -
PB6 Input Pul.se
tlcw
Pulse Width -
CBl ,Input Clock
tiPS'
Pulae Spacing...,. PB61npIJt Pulse
tiCS
Pulse Spacing -
CBl Input Pulse
..
,
,
'.
-
ns
300
ns
31f
300
-
ns
31g
100
Tey
ns
31g
2 x TCY
2 x TCY
.....
2·50
31d
-
150
'SR'
'.
-
31i
31h
2 x TCY
-
31i
2x TCY
-
31h
Versatile Interface Adapter (VIA)
R6522 ,
"
PERIPHERAL INTERFACE WAVEFORMS
fI
READ IRA
OPERATION
CA2
"DATA,TAKEN"
Figure 31a. CA2 Timing for Read Handshake, Pulse Mode
READ IRA
OPERATION
/
"CA2
"DATA TAKEN"
'
'"
y.OV
---xf ~ .
"
" ,
~~~TA ----------:--:----:-------1:1-:
READY"
LACTIVE
TRANSITION
Figure 31b. CA2 Timing for Read Handshake, Handshake Mode
WRITE ORA, ORB
OPERATION
CA2,CB2
"DATA READY"
I----~----I
PA,PB
PERIPHERAL
DATA
Figure 31c. CA2, CB2 Timing for Write Haridshake, Pulse Mode
2·51
R6S22
Versatile Interface Adapter (VIA)
WRITE ORA, ORB
OPERATION
CA2,CB2
"DATA READY"
PA,PB
PERIPHERAL
DATA
CA1, CB1
"DATA TAKEN"
Figure 31d. CAa,CB2Tlmlng for WrI.te Handshake, Handshake Mode
PA,PB
PERIPHERAL
INPUT DATA
~;~~~TCHING
______
J~ ,. .·: : .:.-t-AL~.: t'-L-·~- ~ ~-f:.-..~~
TRANSITION
Figure 31e. Peripheral Data Input Latching Timing
CB2
SHIFT DATA
(OUTPUT)
CB1
SHIFT CLOCK
(INPUT OR
OUTPUT)
DELAY TIME MEASURED FROM THE FIRST ~ ..
FALLING EDG~ AFTER CB1 FALLING EDGE.
Figure 31f. Tlinlng for Shift Out with Intemal or Extemal Shift Clocking
2·52
Versatilelnterf,ce Adapter(~IA)
R6522
.""
CB2
SHIFT DATA
(INPUT)
CB1
SHIFT CLOCK
(INPUT OR
OUTPUT)
SET UP, :rIM!: MEASURED TO THE FI!,!ST.pz
RISINGEDG.E ~ CB1 RISING EDGE.
Figure 31g~ Timing for Shift in with Internal or Extemal Shift Clocking
CB1
SHIFT CLOCK
INPUT
2 0V
tlew
-lrtt-_
V
_ _-,.o_.8_
.__ _ _ tiCs
Figure 31h. Extemal Shift. Clock Timing
PB6
PUI:.SECoUNT
INPUT
\1'~
F
O_'8~VJ
tIPw _ _ _
L-'-tIPs
I
COUNTER T2
DECREMENTS
HERE
Figure 311. PU.lse Count Input Timing
2-53
~
. 'Cl.V.'~. ""'._'
._.1'
2.
.
R6522
Versatile Interface Adapter (VIA)
BUS TIMING CHARACTERISTICS
Parameter
READ TIMING
Cycle Time
TCY
1
10
0.&
Address Set-Up Time
TACR
180
90
Address Hold Time
Peripheral Data Set-Up Time
TeAR
TpCR
300
Data Bus Delay Time'
TCDR
-
-
Data Bus Hold Time
THR
10
-
0
0
10
-
i
••
." ,
A.
M
A3
AO
ROMSEL .
A•
V
AS
••
A'
!l{;:
,
::-p
I
:4>
L.. _ _ _
A4
"AM
'2
AI
:~
.'0 11..{:::
A7
I
RAMSEL.
~
-
CO2
I/O'
A'
'7
I
- - -...,.. -
-- - --
,.
A.
I
A.
--'
A4
A3
A3
A'
A2
AI
"
AO
AO
RSS30 One-Chip Addreas Encoding Diagram
Table 2, Addreasing Decode for I/O Register and Timer
Addressing Decode
Function
ROM Select
RAM Select
I/O Timer Select
RiW
A3
Ai
,Al
AD
Read ROM
Write RAM
Read RAM
Write DORA
Read DORA
Write DDRB
Read DORB
Write Per. Reg. A
Read Per. Reg. A
Write Per. Reg. B
Read Per. Reg. B
Write Timer
+IT
+8T
+64T
+1024T
Read TImer
Read Interrupt Flag
1
0
0
0
0
0
0,
0
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
O.
0
0
0
0
0
0
0
0
D
0
0
0
0
0
0
0
0
0
0
0
0
0
Notes: *A3 = 1 Enables im:i to PB7
A3 = 0 Disables IRQ to PB7
2-64
0
0
0
1
1
··
··
·
X
0
0
1
1
X
X
1
1
1
0
0
0
0
0
1
0
1
0
1
R6530
ROM-RAM-I/O-Tlmer CRRIOT)
TIMING CHARACTERISTICS
Read. Timing
Characteristic
RiW valid before posHive transition of clock
Address valid before posHive transHion of clock
Peripheral data valid before posHive transHion of clock
Data Bus valid after poSitive transition of clock
ata: Bus Hold Time
IRQ (Interval Timer Interrupt) valid before positive
lrahsHibn of clock
Note: Loading =
30 pF
= 130 pF
SymbQl
Min
TWCR
ACR
180
180
PCR
30C
TCOR
HR
TIc
Max
Unit
-
ns
ns
ns
ns
ns
ns
395
10
200
+ 1 TTL load for PAO-PA7. PBO-PB7
+ 1 TTL load for 00-07
Write Timing
CharaClllrlatlc
Clock Period
Rise & Fall Times
Clock Pulse Width
R/W valid before pOsHive transition of clock
Address valid before positive transition of clock
Data Bus valid before negative transHion of clock
Data Bus Hold Time
Peripheral data valid after negative transHion of clock
Peripheral data valid after negative transition of clock
driving CMOS (Level = VCC - 30%)
Symbol
Min
Tcyc
TR• TF
Tc
Twcw
TAcw
470
180
180
DeW
300
THw
Tcpw
TCMOS
2·65
1
Max
Unit
10
25
",S
ns
ns
ns
ns
ns
ns
1
2
,.s
10
",5
R6S3D
ROM-RAM-I/O-Timer (RRIOT)
READ TIMING WAVEFORMS
CLOCK INPUT
7f
2.4V
~O.4V
/!2.4V
R/W
-----t-------- 0.4V
_..;..-+..;....-----+-------+-------~ 2.4V
ADDRESS
- - - + - - - - - + - - - - - - - + - - - - - - - - O.4V
2.4V
PERIPHERAL
DATA
----+------+-------+-------- O.4V
THR
2.4V
DATA BUS
O.4V
~
PB7(IRQ)
TIC
2.4V
_ _ _ _ _ _ _ _ _ _ _ O.4V
WRITE TIMING WAVEFORM~S T C Y C 9
L :1
Tc
TR
CLOCK INPUT
I r.
------;7- I
24V
rTF
04~vl
4V~
I~
~
, . . - - - - - - - - - - - - 2.4V
R/W
O.4V
/ " " - - - - - - -_ _ _ _ 2.4V
ADDRESS
2.0V
O.BV
' - - - - - - - - - - - - O.4V
- - - - - - - - - - - - 2.4V
DATA BUS
- - - - - - - - - - - - - 0.4V
T DCW
-+___ ......TCpW
~
Vee
·30%
--ao~
1/""t-:-2.~0~V-------- 2.4V
PERIPHERAL
DATA
8V
_t-0_ ._
_ _ _ _ _ _ _ _ OAV
2·66
ROM-RAM-I/O'!'Timer (RRIOT)
R6530
MAXIMUM RATINGS*
Symbol
Rating
Supply 'vbttage
Unit
Value
Vee
-0.310 +7.0
V
InplJl/Output ~It~e
VIN
-0.3 to +7.0
V
Operating Temperature
TA
Ot070
'C
Storage Tem~erature
TSTG
-55 to +150
'C
"Note: All inputs contain protection. circuitry to prevent damage due to
high static charges. Care shOuld be taken to prevent unnecessary
application of voltage outside the specification range.
DC CHARACTERISTICS
(V co
:=
5.0V
±
5%, V~S
:=
bv, O·C to 70·C, unless otherwise noted)
CharacteristiC
Typ.
Min.
VIH
+2.4
Input Low Voltage
V IL
-0.3
+0.4
V
Input Leakage Current
AQ..A9, RSO;MY, !=IES, 02, PB6(3), PBS(')
liN
1.0
2.5
p.A
VIN = 0 to +5.0V
Vee = q
Input Leakage Current for Three State Off
00-07
ITSI
±1.0
±10
p.A
VIN = 0.4V to 2.4V
,Vee = 5.25V
Input High Current
PAO-PA7, PBO-PB7
'IIH
p.A
VIN = 2.4V
Input Low Current;
PAC-PA7 PBO-PB7
IlL
mA
VIN = 0.4V
Output High Voltage
PAO-PAY, ~BO-PB7 (TTL drive), 00-07
PBO-PB7, (other drive, e.g., Darlington)
VOH
Output Low Vottage
Vee
-100
-300
-1.0
-1.B
Unit
V
V
Vee = 4.25V
'LOAD = -100 p.A
ILOAO = 3.0 rnA
V
Vee = 4.25V
ILOAD -= 1.6 rnA
+2.4
+1.5
.
+0.4
VOL
Output High Current (Sourcing)
PAO-PA7, PBQ..I:'B7 (TTL drive), 00-07
PBO-PB7 (other drive)
IOH
Output Low Current (Sinking)
PAC-PA7, PBO-PB7
IOL
Power Dissipation
Po
Input Capacitanc:e
~2
Logic
CCLK
C'N
Output Capacitance
Max.
Taet Condltlona
Symbol
Input High ~'tage
-100
-3.0
-1000
-5.0
p.A
rnA
I.B
CO UT
Note: 1. All units are direct current (DC).
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. When programmed as address pins.
mA
500
1000
mW
30
10
pF
pF
VO H = 2.4V
VOH = I.SV
VOL = 0.4V
V'N=O,f-= 1 MHz
TA = 25'C
R6530
ROM-RAM-I/O-Timer (RRIOT)
PACKAGE DIMENSIONS
40-PIN CERAMIC DIP
'""--[-=D~]JJ
f4'--1.
INCHES
MILLIMETERS
MAX
MAX
MIN
DIM MIN
A
50.29 51.31 1.980 2.020
B
C
D
~A_---.l~1
F
G
H
J
~F
K
L
M
N
14.86 15.62 0.585
2.54
4.19 0:100
0.38 0.53 0.015
0.76
1.40 0:030
2.54 BSC
0.100
0.76
1.78 0.030
0.20
0.33 0.008
2.54 4.19 0.100
14.60 15.31 0.575
o·
0'
10'
0.51
1,52 0.020
0.6'1'5
0.165
0.021
0.055
sse
0.070
0.013
0.165
0.605
10
0.060
40-PIN PLASTIC DIP
INCHES
MILLIMETERS
MAX
MIN
MAX
DIM MIN
51.28 52.32 2.040 2060
A
13.72 14.22 0.540 0.560
B
3.55
5.08 0.140 0.200
C
D
0.36
0.51 0.014 0.020
F
1.02
1.52 0.040 0.060
2.54
0.1008SC
G
2.16 0.065 0.085
H
1.65
0.20
0.30 0:008 0.012
J
3.05 3.56 0,120 0.140
K
0600 esc
15.24 SSC'
L
1(y
7
10
M
7
0.51
1.02 0020 0.040
N
sse
2·68
R6531
'1'
Rockwell
R6531
ROM-RAM-I/O COUNTER (RRIOC)
II
DESCRIPTION
FEATURES
The R6531 ROM-RAM-I/O-Counter (RRIOe) Integrates· readonly memory, random access memory, variouS 1/0 data port configurations and timer functions into a single peripheral device
\'ihich operafesin conjunction with any CPU in the R6500
microprocessor family. The R6531 provides innovative system
designers with a two-chip solution to a wide range of applications. It can also be combined In a variety of multi-chip system
configurations with other R6531's,. ROMS, !'lAMs and other 1/0
deVices.
• 2048 x 8 mask programmable ROM
• 128 x 8 static .RAM
• 16-bit multi-mode counter/latch
- intemal timer (one shot or free-running)
- pulse generator (one-shot or free-running)
- event counter
- external trigger
• 8-bit serial channel
• TTL compatible 110, drive one TTL load
• 15 bidirectional 1/0 lines (2 ports - 40-pin package)
• Expansion 8-bit output port and 4-bit input port (52-pin package)
• 1/0 handshake control
• Four edge sensitive interrupt inputs
• 1 MHz or 2 MHz operation
• ROM-less versions .available for prototyping
• Single + 5V power supply
There are two R6531 versions: a 40-pin dual-in-fine package;
another with expanded I/O in a compact 52,pin quad-In.line
package. ~oth versions contain a 2048 x 8 mask-programmable
ROM, a 128 x 8 statiC RAM, a software programmable multimode counter, an 8-blt serial data channel, and 15 bidirectional
data lines (two ports) with a handshake control mode and four
interrupt inputs. The 52-pln·version has an8-bit output port and a
4-l:)lt input port for a total of 27 .1/0 lines. Several mask options are
available to provide a RAM standby power pin and chip ~elects
for .multl-chip systems.
Prototyping circuits are available in both the 40- and 52-pin packages, and 1- and 2-MHz versions. They are offer~ as part
numbers R6531-098.and R6531-098A for the 4Q-pin part, and.as
part numbers R6531-099 and R6531-099A for the 52-pin part.
R6S00
MICROPROCESSOR
BUS
In
PERIPHERAL
INTERFACE
DO-D7
ORDERING INFORMATION
PAG-PA7
Part Number:
R6S31
PBG-PBS
AG-A11
]1.' .....
Tsmperatu.r.e Range:. L-Th)
..
Blank = 0° to + 70°C
'.
E = -,40°C tp +85°C
(T.
;2-......,----1...
ANi .".--...-..,
Package:
C = 40-Pin DIP, Ceramic
P = 40-Pin .DIP, Plastic
Q = 52-Pin QUIP, Plastic
PCO-PC7'
CS1-CS3---+I
I R Q - - -....
R E S - - -......
PDO-PD4'
VRR··---.......
' - - - - - Frequency Range:
No letters .. 1 MHz
A = 2 MHz
VCC-----....
NOTE: Contact your local Rockwell representative for
availability.
'52-PIN VERSION ONLY
"OPTIONAL
Interface Signals
Document No. 29000052
2-69
Data Sheet Order No. 052
Rev. 5, October 1983
ROM-RAM-I/O Counter (RRIOC)
R6531
PHASE 2 CLOCK (<1>2)
INTERFACE SIGNALS
The P~ase2 Clock (112) input is the system cloCk that triggers all
data 1ransfer~ between the data, bus and the R6531.·
RESET (RES)
PERIPHERAL DATA PORTS (PAO-PA7, PBO-PB6,
PCO-PC7, PDO-PD3)
This active low signal initializes the R6531. It clears all internal
registers (except the counter and serial registers) to logic zero.
This action places all bidirectional 110 lines in the input state and
the Port C outputs in the high state. The timer, shift register, and
interrupts are disabled. The RES signal must be low for at least
four clock periods when reset is required.
Both versions of the R6531 have 15 pins available for peripheral
110 operations. Each pin is software programmable to act as an
input or an output. The pins are grouped into an a-bit port;
PAO-PA7, and a 7-bit port, PBO-PBf;>. The lines of the PB port
may serve other functions. Ports PA and PBhave associated
data direction registE;lrs.
ADDRESS BUS (AO-All) AND CHIP SELECTS
(CS1-CS3)
Memory and register selection is accomplished using the 12
address lines and, in multiple device systemS,alsousing one or
more of the three Chip Select mask options. When PB4, PB5, or
PD2 are chosen as chip selects,they cannot be used as peripheral 110 pins.
The expanded I/O of the 52-pin version provides 1\n 8~bit output
only part, PCO-PC?, and a 4-bit input only port PDO-PD3. PD2
and PD3 may be assigned other functions as described later.
The OUtput!! .a.re push/pull type drivers capable 01 driving a single
TIL load. When inputs are selected the drivers float. If PBS is
DATA BUS (DO-D7)
programmed as the IRQ request output, the line is driven low and
requires an eicternal pull-up, thus allowing the-Wire OR-ing of IRQ
from other devices.
The R6531 has eight data bus lines, which "allow data to be
transferred, to or from~he microprocessor. The outpu.t buffers
remain in the off-state except when the R6531 is selected for a
read operation.
RAM ,RETENTION VOLT AGE (VRR)
A separate pin for a power supply for the readlwrite memory is
available as a mask option. This allows the retention of RAM data
by using a battery back-up for the RAM only. Pin PB6 in the
4O-pin version or PD3 in the 52-pin version is mask programmable as the VRR pin. Address line A 1Q must be held in the logic
state which deselects RAM (user-defined) in order to protect the
RAM data when VCC falls below the specified level or is turned
off.
READIWRITE (R/W)
The RfiJ input controls the transfer of data to and from the
microprocessor and the R6531. A high on the RfW pin allows the
processor to read (with proper addressing) the data supplied by
the R6531. A low on the RfW pin allows a write (with proper
addressing) to the R6531.
. PA7
PAO
PBS
PBO
PC7
NOTE: "52-PIN VERSION ONLY
R6531 Block Diagram
2-70
PCO
PD3
PDO
R$531 .
RONI-RAM..I(O Counter (RRIOC)
. vss
PBaISOJO·
VSS
(CS2) PB4ICNTO
(CS1) PB5ICNT1
:RIW
PB2/¢LJ(
PB1/CA2
PBO/eA1
PA7
PB8nRCi
FiES
D7
De
05
07
D8
D3
.048
PA3
pAl
D2
PAt
D1
PAO
1/>2
04
PAS
PA4
14.&
14.8
Poi
D3
D2
D1
DO
. 14.2
00
14.0
14.11
14.9
14.10
PAl
05
AI
14.7
,p2
PAS
PA4
AS
AI
RIW.
PB2/SCLK
1!'131/CA2
PBoiCA1
PA7
RES
PAi.
14.7
PB31S0JO
(OS2) .PB4/CN1'O
(CS1). P$5/CNT.t
PA3
pAz.
PA1
PAO
14.2
14.0
14.11
14.9
14.10.
14.4
14.1
14.3.
vee
14.4
14.1
14.$
vee
VRR
PBIOPTlON
VRR OPTlON
R6531· 40-Pln DIP Conflguratlonl
vss
VS~
PB31SDJO
RiW
(CS2) PIWCNTO
(CS1) PB5"/CNT1
PB8I1RQ
PC6
PB21SCLK
P131/0A2
PBO/CA1
Pc7
RES
D1
PDO
02
01
00
(CS3) PD2
AI
PD1
D4
14.9
14.10
14.8
PC3
03
PA3
PA2
PD~
1tA1
D2
D1
PAD
14.2
14.4
PC2
·00 .
AD
14.11
PCO
PC1
14.1
14.11
PCO
PAS
PA4
PC4
AS
14.7
t/>2
"4PCZ
.AD
PA7
PAl
. DI
PC3 .
PA3
PA2
,PA1
PAO
14.2
D3
05
PC7
14.8
PD1
D4
D?
PB2/SCLK
PB1·ICA2
PSO/CA1
PC5
RES
PeS
14.7
t/>2
PCI
PB81iRa
PA7
PA8
PAS
PA4
PC4
AS
D6
D5
PD3
(CS3)¥02
AI
PB31SDJO
RiW
(CS2) PB4/CNTO ..
(CS1) PB5/CJrr1
,PCt
14.1
14.3
14.9
14.3.
14.10
vee
vcc
VRR
PD3 OPTlON
VRROPTlON
R6531Q 52~Pln QUIP ConfIguratIons
2-71
fI
R6531,
ROM-RAM"I/O Counter (RRIOC)
'Table 1_ R6531 Addressing
INTERNAL ORGANIZATION
Chip
Selects
The R6531 Is dlvldel:Hnto three basic functions: ROM, RAM, and '
VO. The selection of anyone of these three is accomplish9d by
issuing the appropriate address information on the address bus
when the chip Is selected
R6531
Function
ROM-2K BYTES (16K BITS)
CS3 CS2.
Add,_lnputs IAO-A111
CSI
11 10191817J6J5141312:1'1 0
ROM
)(
X
X
X
RAM
V
V
V V
1/0
Z
z'
V,
Z·
2K RQM Decode
l.v IV IV
Z z IZ IZ IZ
I
128 RAM Decode
12 Jz12 110 Dec~de
The x, Y, arid ,Z bits maybe selected as hlgh,low or no effect.
The 16K ROM is a 2048 x.8bit configuration. An address on
lines AO-A10 uniquely selects one byte of ROM. Additionally,
address .line A 11 and the chip'selects are required to select the
ROM function on a given chip. In a system with multiple'RS531's,
the CS 1, CS2, and CS3maSk options allow up to seven devices
•with 14K bytes of ROM without the need for external decoding.
The chip Select pins are also discretlilllO pins PB5, PB4, and'
PD2. The pins are ind!ilpendent of each other in that anyone may
be used as a chip iielect. The user specifies as mask options
which pins are to be used as 110 and which as chip selects,
RAM-128 BYTES (1024 BITS)
40·PIN PROTOTYPING CIRCUIT
The 128 x 8 static RAM of a given RS531 is addressed by lines
AO-AS. Additionally, address lines A7-A11 and chip selects CS1,
CS2, and CS3 provide selection of the RAM section of the device
as well as the device itself when additional RAM devices or
R6531's are in the system.
Prototyping circuits R6531-D98 (1 MHz) and RS531-098A (2
MHz) are packaged in a 40-pin dual in-line pac~ge that has the
same pinouts as the 40-pin RS531 with PBS option, In this
prototyping circuit, the ROM is disableq and there is no VRR
option. Access codes for this prototyping circuit are shown in
Table 2.
INPUT/OUTPUT
Table 2. R6531-G98 Addreulng
The input/output section is comprised of the data ports, direction
registers, colJnt,er and $Ssoclated latcheS, co/ltrolregisters, an~
interrupt registers. These 1/0 functions are all accessible by the
R6502 CPU's instruction set using address bits AO-A3 for the
specific function of the device. Address bits A4-A11 and CS1,
CS2, and CS3 additionally may be decoded to select a given
RS531 device in a multichip system,
R6531-098
Function
Control Registers
N means No Effect, H means High and L means Low,
Chip
Selects
RAM
I/O
Two cont,rol registers allow software selection of various 1/0 functions. The Peripheral Control Register (PCR) is primarily associated with Port Bfunctions and the Auxiliary Control Register
(ACR) is associated wlth'the counter and serial data functions
which also affect Port B.
Add,_lnputslAO - AnI
CS2 CSI
N
N
N
N
11
10
9 8 7
L
L
'L
H
L N L
H H L
61
5j 4j 3j
21'1 0
128 RAM Decode
LJLJI/O Decode
LJ.
52·PIN PROTOTYPING CIRCUIT
Prototyping circuits R6531.Q99 (1 MHz) and R6531-099A (2 MHz)
are packaged in the 52:point quad in-line package, with VRR
option, PD2 is used as a chip select (CS3), and PB4 and PB5
are available as I/O lines_ Access codes for the prototyping circuit are shown in Table,'3,'
ADDRESSING
Table
Addressing of the R6531 offers many variations to the user for
system configuration flexibility. Combination with other R6531
ROMs, RAMs or 1/0 devices is possible without need for external
address decoding. Each of the three basic functions on the
device has its own decode mask for unique selection.
The specific addressrangas and chip selects are defined by the
user and are dependent on tlie number of chips in the system.
The programmed options to be fixed by masking are shown in
Table 1.
3. R6531-0GG Addressing
R6531-099
Function
Chip'
Selects
Add,esslnputs lAO-AlII
ROM
RAM
eS3 CS2 CSI
H
N
N
L
N
N
L
N
N
11 1019i8iUaltl41ai2itLO
H
2K ROM Oecode
L L1L1Nlid 128 RAM Decode
L H1H1H1L1L1LI LiI/OD"code
1/0
The 128 words or RAM have been mapped into the first half of
both Page 0 and Page 1, to accommodate zero page addressing
and stack operations. The full 110 capabilities described for the,
R6531 are available in the prototyping circUit, except that 110
lines PD2 and PD3 are dedicated to the VRR and CS3 mask
options.
2-72
,ROM-RAM-I/O Counter (RRIOC)
R6S3i
REGISTERS
REGISTER SELECTION,'
The register selection and/or general operation performed by the
15 R6531 addresses in conjuncllOnWilh the R!W state is shown
In Table 4.
Table 4. Register Selection
Hex
Address Line
A1
A2'
OperatIOn
IWI- Low
RIW = High
AO
Addr
A3
0
1
L
L
L
L
L
t
H
'2
L
L
L
H
L
-
Write Port C Data
3
L
L
H
H
-
Write Port 0 Data
4
5
6
7
8
9
A
L
H
L
Read Lower Counter
Write Lower Latch
L
H
L
L
H
Read IJpp!lr Counter
Write Upper Latch and Download
L
H
H
L
L
H
H
H
H
L
L
L
Read Serial Data Register
Write Serial Data Register "
H
L
L
H
Write Interrupt Flag Register
H
H
L
Read Interrupt Flag Register
Read Interrupt Enable Register
H
H
Read AU~lIiary Control R!lgister
Write Auxiliary Control Register
Write Peripheral Control RegIster
Write Port A Data
ReadPortA Data
Read Port 8 Data
Write Port 8 Data
-
Write Lower Latch
-
Write Upper Latch
B
H
L
L
C
0
H
H
L
L
Read Peripheral Control Register
H
H
H
-
E
H
H
L
H
Write InterruPt Enable R!lgister
Write Port A Data Direction R!lgister
-
L
Write Port 8 Data Direction Register
Peripheral Control Register (peR)
Auxiliary Control Register (ACR)
Some Port 8 operating options aresoflWare selectable bywritlng
control bits to the Peripheral Control Register (PCR).
Operating Modes for the TImer/Counter, PB2IPB3 Serial
input/output and PB4 Pilise output are selected by writing bits
to the Auxiliary ,Control Register (ACR).
AUXIUARY CON1'ROL
17
_ _ CONTROL_,(PCI'I)
171_ 11'1
3
1 2 1'1
0
_
AND PS. CONTROL
o•
COUNTER
CON1ROL
3
1 2 1'10
LC..'
COUIfTEII SOURCE SELECTION
00 • COUNTER OFF
,1 • PHASE 2. EXT TRIGGER LOW
01 .. ,PA HAJl:J8HAICE
tx. NEG EDGE,OETECT
AND _
_nil (ACII)
~!:~ EVENT (PU)
00 • STATIC 110
'---- _
I
'1_1'1
L....J
1
~
=:..
PULSE IlENEAAnON CONTROL
o = PULsE OUTPUT o~ ..
CONTROL
• • PULSE OUTPUT ON (pac)
STATIC I/O
FlEE RuN ODNtIIOL
1 = POI EDCE DETECT
D.ONESHOT
1 . FREE RUN
' - - - - - - PBe CON'I1IOL '
O. IT_new
SERIAL CLOCK SOUIICI!
00 .' IEIIIAL OFF
,
•• IiiC5_EST
OUTPUT.
0' • EXT&AIW. CLOCK (P12)
••• PHASE 2 CLOCK (pili OUT)
' - - - - - - - - - SPAAE(UNUSED)
°SERIAL
• DATA DlIlECnON
.... SERIAL OUT
SERIAL IN (P83)
(P83)
SPAIIE (UNUSED)
2-73
fJ
ROM-RAM-I/O Counter (RRIQC)
86531
PERIPHERAL DATA PORTS
Interrupt Enable and Flag Registers
Ea?h line of the 8-blt data Port A may be individually selecied as
an Input or output. Associated with the port is Data Direction RegIster..,.. PortA (DORA). Each line of the 7-bit date. Port B may be
Individually selected as .an input or an output. This port also has a
Data Direction Register (DORB). The two data direction registers
(A and B) control the direction of the data into and out of the
jieripheral p!ns. ,A "1." wrllteninto the Data pireclion Register
sets up the comtspondlng peripheral pin as an output. Therefore
anything written .Intothe data regiisJer will.appear on.. that carre:
,. ~diFigperlpheralc.pln •.A "O!·' written Into the DDR"inhiblts the
outpUt bUffer from transmitting data from the data register. For
example, a "I" loaded into DORA, position 3, sets up peripheral
pin PA3as an oulpl,ll. If a "0" had been loaded, PA3 would be
configured as an .input and would be In a float ~ate.·
.
Two registers /ire provided for interrupt control. Corresponding
bits In the enable and flag registers are logically ANOed to set tbe
Interrupt Request Pending flag. If the pending flag is set and PBS
is selected as an IRQ Request Output, then PBS will be set low to
request th.e RSS02 CPU 10 service IRQ.
The Interrupt enable bits are set or reset by writing inlo'the Interrupt EnableRegl~er. Th~ in~errupt flagbltsIFRO~.IFR6 can be
cleared directly by wrltlng'a byteito the flag register which has1's
in those bft positions to b$.clearei:t.
.
.
IFR4 and IFR5 may also be cleared by reading orwriilng the Port
A or Serial Data Registersrespecti.vely. IFR~ may also be
cleared by reading the 10wer'COI;Inter with I/O /ilddress hex 4 writing the upper latch with 110 addresses. hex 5 or .7.
,
These registers and their bit assl\2nments are illustrated.
, Note that wtien lines in Ih. PB port are used altemately as control
Ii~es fpr ~8r on-chip functions, DIrection Register B must also
be loaded to set up the proper direclion- the Control Registers
have no effect on data direCtion.'
, \,he B-blt Port C is an output only port. The 4-bit data Port 0 is an
'Input only port.
.Fqr, thqse lines being u,sed as outputs, th~ data registers are
uHd to latch data from the Data Bus during a Write operation so
:
the"perlpheral'device can read the data supplied by the
. , mlCr0prQC8ssor.
.
For the .lines being Used as inputs, the microprocessor is reading
the penpheral data pins: For the peripheral data pins whi.ch are
programmed as outputs the microprocessor will read the corresponding data bits of the Output data.
EDGE DETECT LOGIC
PSO NEGATIVE
EDGE DeTEcT
Operating. In:'par~"elwith the 110 operation. of PBO-PB3 is edge
delect logiC that IS enabled by Peripheral Control Register bits 1
and 2. PCRI enables logic that upon detection of a negative
edge on PBO or PB1 will set a corresponding flag in the Interrupt
Flag Register. PCR2 enables logic that upon detection of a poSitive edge on PB2 or PB3 will set corresponding flEi9S in the Interrupt Flag Register. If corresponding bits are set in the Interrupt
Enable Register, then the Inferrupt Request Pending flag will be
PB1 NEGATIVE
EDGE DETECT
PB2' POSl'flVE
EDGE DETECT
.PB3 POSITIVE
. EDGE DETECT
PORT A NEEDS SERVICE
IN HANDSHAKE MODE
set.
·seRIAL REGISTER
. FULUEMPTY, EXT. CLOCK
HANDSHAKE OPERATIONS
. COUNTER OVl!RFLOW
'lNTERRUPT
REQUEST PENDING
PBO and PB1 may be used ElS handshake control lines for date
transmissions pver Port PA; see PCR defil'ition. PBO is a contrpl
input, PS11s a control output. PB1switches low on a read or write
to Port PA, and switches high in response to a negative transition
on PBO.
.
IFR4 in the Flag Register is set by a negative transition on PBO,
and cleared by a Read or Write to Port PA; see Handshake Timing Diagram for timing detailS.
2-74
R6531
ROM-RAM-I/O Counter (RRIOC)
ADDR
}
o
FR4
LOAD PA
0\ 0
o
o
o
PBO (IN)
PB1 (OUT)
o o
PBO SAMPLED
PA (DATA OUT)
IRQ
---)~~=========s~-----------J~==============~-PB1 CONTROL
SET BY:
RESET,
WRITE PCR, OR
NEGATIVE TRANSITION ON PBO
RESET BY:
WRITE PORT PA
OR READ PORT PA
R6531 Timing for Handshake Mode
4>2
ADDR
RIW
FRO, 1,2,3
IRQ
PBO, PB1
PB2, PB3
PB SAMPLED
(4)2 LOW)
0
0
I I
0
;z!
0
NEG. TRANSITIONS
POS TRANSITIONS
U
INTERRUPT FLAG REG. CONTROL .
SET BY INPUT ACTIVE TRANSITIONS
',~!
RESET BY RESET OR WRITE "1"
TO. CORRESPONDING IFR BIT
R6531 Timing for Interrupt Mode
2-75
I
R6531
ROM-RAM-I/O Counter (RRIOC)
SERIAL DATA CHANNEL
The R6531 has an a-bit serial channel. PB2 and PB3 are software selectable as the serial clOCk (Sell<) and serial data (SOlO)
lines respectively.
Auxiliary Control Register bit 6 sets the"serial data direction. Data
are shifted in or out, most significant bit first, under control of the
shift clock.
The software sets Auxiliary Control Register bits 4 and 5 to enable the serial channel and to specify the source of the shift clock.
Selection of the internal clock will shift data at one half the system
~2 clock rate. If the external clock is used, data may be shifted at
any rate up to one half the system ~2 clock rate. In the external
clock mode, the counter may be"operated in the free run pulse
generation mode using the CNTO line externally connected to the
SClK .lIne to provide the desired shift rate.
In the external clock mode, the completion of eight shifts of the
serial register will set bit 5 of the interrupt flag register. If the corresponding bit of the Interrupt Enable Register is also set an
Interrupt Request PEmding flag will be set.
2
3
4
5
6
7
13
14
15
16
18
~
ADDR (WRITE)
W.
R/W (WRITE) ~....,........;:r",""""""""
flb
-0-
DATA B!JS
(WRITE)
MSB
1 or 1"
SER DATA
I
SER elK
INPUT SMPl
17
L_J
m
rn
ADDR (READ)
R/W (READ)
DATA BUS (READ)
R6531 Serial If0 Timing
2-76
m
ROM-RAM-I/O Counter (RRIOC)
R6531
COUNTERITIMER
The R6531 contains a multi-mode 16-bit counterltimer with an
associated 16-blt latch whose modes are softw~re selectable by
setting appropriate bits in the Auxiliary ContrOl Register. The
latch holds the counter preset value and all 16 bits download to
the counter simultaneously upon command (1/0 address hex S)
of t1)e software or automatically in free run modes upon overflow
of the counter. The counter Is a decrementing counter and
causes the setting of a flag in the Interrupt Flag Register when It
overftows. This interrupt flag, bit 6, is logically ANDed with a cor.responding counter overftow interrupt enabled bit to set the Interrupt Request Pending flag. The Auxiliary Control Register is used
.to set four bas.ic modes which specify the source of the count
information, and to select two mode modifiers that apply equally
to the three active modes.
Mode 0
- Counter Off
Mode 1
- Event Counter - counts extemal event
inputs (negative transitions) at PBS
Mode 2
-Interval Timer - counts 162 system clock
pulses.
- Extemal Trigger - counts 92 system clock
pulses starting with a negative transition on
PBS.
Mode 3
Mode Modifier A -Pulse Generation Control - causes the
output level on PB4 to switch low each time
the counter Is loaded using VO address
hex. S. At counter overflow, PB4 switches
high. If in the free run mode,' PB4 oontin\les
to toggle at each subsequent counter over-.
flow; Otherwise there are no further transi"
tions until the cOunter Is reactivated by the
software.
Mode Modifier B -Free-Run Control- causes the full 16-bit
latch to be downloaded to the counter, continues to count, and sets the counter overflow flag bit every time the counter
overflows. Otherwise the counter is a one
shot mode in which the counter overflow
flag Is set one time only' until the counter is
reactivated by the software.
ADDR"IJ..
lOAD TIMER
R/W~
=4
COUNTER: ONE-SHOT
COUNTER: FREE-RUN
FRS: ONE-SHOT
FRS: FREE-RUN
~
PB4: ONE-SHOT
~
PB4: FREE-RUN
~
IRQ
COUNTER EXT STROBE
0
0
0
0
I
4
4
I
~
~
PBS
COUNTER EXT CLOCK
PBS
~4
4;: 4
~ :;;3
2
I
1
'2J!-!222'
PBS SAMPLES @ 1/>01
R6531 CounterlTlmer Timing
2-77
I
0
FF
I
FE
I
1
1
I
1
I
FD
I
1
I
1/>2 ClK
MAX RATE
2
R6531
ROM-RAM-I/O Counter (RRIOC)
BUS TIMING CHARACTERISTICS
'.
R6531
(1 MHz)
Characteristic
Clock Period
R6531 A
(2 MHz)
Symbol
Min
Max
Min
Max
Unit
Tcyc
1.0
10
0.5
10
floS
-
235
-
ns
25
-
15
ns
120
-
ns
12Q
-
ns
135
-
ns
180
ns
Clock Pulse Width
Tc
.470
Rise & Fa/I Tlme,s
TR • TF
-
RIW valid before poSitive transition of clock'
TWCR
180
Address valid before positiVe transHlon of clock
180
Peripheral data valid before positive transition of clock
T"CR
TpCR
270
Data Bus valid after positive transition of clock
TCDA
-
350
Data Bu.s Holq Time
THA
10
-
10
-
nil
TIC
-
900
-
450
ns
.
Twcw
180
-
ns
T"cw
180
120 .:
270
135
-
ns
Tocw
-
120
ciock
THW
10
-
10
-
ns
Tcpw
-
900
-
450
ns
READ TIMING
.am valjd. ~fter. negative; transition. of cl(ICk,
-
....
-
WRITE TIMING
RiW valid before positive trs.nsHlon "f cloCk
Address valid, bl9fo~e positive transition of
Data Bus valid before negative transition of clOck
Data "'us Hold Time
....
Peripheral data valid. after negative. transition of qlock
NOTES:
Load
= 100 pF + 1 TTL for PAO-PA7. PBO-PB6. and PCO-PC7.
= 100 pF + 1 TTL for 00-07 (R6531 A).
= 130 pF + 1 TTL for 00-07 (R6531).
2-78
ns
-
(RRIOC)
--------------~J~~A~M~-I~/O~~C=Ou=n~m_r
_____
_
ROM-R~
R6531
-:--=:-:-~WAVa;QiEFORRMSMS"~h
~ever~.
READ TIMING
~
--~-
2.0V
<1>2
RtW
O.4V
2.4V
ADDRESS
--+----+----
PERIPHERAL
DATA
0.4V
2.4V
O.4V
--+------
DATA BUS
2.4V
O.4V
2.4V
PB7 (IRQ)
WRITE
0.4V
l
-1 i:=" ::11" .y
T!MIN~
r.: WAVEFORMS
•
. "
T eve
-Yl'2.0V
0.8~ _ _.
<1>2 _ _ _
_ _ _ _ _ _ __
2.4V
RtW
O.4V
2.4V
ADORESS
O.4V
=----
DATA BUS
2.4V
----------VV
cece
2.0V
O.8V
PERIPHERAL
DATA
2-79
O.4V
-30%
2.4V
O.4V
ROM-RAM-I/O Counter (RRIOC)
R6531
MAXIMUM RATINGS·
Rating
Symbol
Value
• Note: This device contains circuitry to protect the inputs against
damage due to high static voltages, however, normal precautions
should be taken to avoid application 01 any voltage higher than maximum rated voltages to this circuit.
Unit
Supply Voltage
Vcc
-0.3 to 7.0
Vdc
Input Voltage
Vin
-0.3 to +7.0
Vdc
Operating Temperature Range
Commercial
Industrial
TA
Oto +70
-40 to +85
°C
°C
Storage Temperature Range
Tstg
-55 to +150
°C
DC CHARACTERISTICS
(Vee 5.0V ± 10%, Vee = 5.0V ± 5% A, Vss = 0, TA = T L to T H' unless otherwise noted)
Symbol
Min
Max
Unlt(1)
Input High Voltage
V,H
2.0
Vee
V
Input Low Voltage
V,L
-0.3
+0.8
V
Input Leakage Current
AO-All,CS1-CS3, RAN, RES, ~2, PDO-PD3
liN
-
2.5
pA
Y,N = OV to 5.0V
Vee = OV
Leakage Current tor Three-State Off
(Three State) DO-D7, PAO-PA7, PBO-PBS
ITSI
-
±10
pA
Y'N = 0.4V to 2.4V
Vee = 5.0V
Input High Current
PAO-PA7, PBD-PBS, PDO-PD3
I'H
-100
-
pA
Y'N
Input Low Current
PAO-PA7,PBO-PBS,PDO-PD3
I,L
1.S
-
mA
Y'N =; O.4V
+2.4
-
Characteristic
Output High Voltage
DO-D7, PAD-PA7, PBO-PBS, PCO-PC7
VOH
Output Low Voltage
DO-D7, PAO-PA7, PBO-PBS, PCO-PC7
VOL
Output High Current (Sourcing);
PAO-PA7, PBO-PBS, PCO-PC7
IOH
Output Low Current (Sinking)
PAO-PAl, PBO-PS7, PCO-PC7
IOL
V
+0.4
V
-
mA
20
10
pF
pF
COUT
10
pF
Po
1.0
W
-200
2.1
Logic
Output Capacitance
Power Dissipation
CClk
C'N
NOTES:
1. All units are direct current (DC).
2. Negative sign indicates current flow, positive indicates inward Ilow.
2-80
= 2.4V
Vee = 4,75V
ILOAO = -200
~A
Vee = 4.75V
ILOAD = 2.5 mA
VOH
= 2.4V
VOL
= 0.4V
Vee
= 5.0V,
pA
Input Capacitance
~2
Test Conditions
Y'N = OV,
1 = 1 MHz,
TA = 25°C
R6531
ROM-RAM-I/O Counter (RRIOC)
PACKAGE DIMENSIONS
40·PIN DIP
52·PIN PLASTIC QUIP
10° MAX
D q'~ ~
DOT OR NOTCH
TO LOCATE
PINNO'
II
--r
o
060DMAXri:S87}
0625
jo(~)U:5~
LO
0155 MAX
(393 MMI
2020 MAX
(5130 MM)
~~Tvpjr.
L m~~
11.01) 0.040
(a. 55} ~ TYP.
(O.4S) 0.018
0.010 MIN
1.91Q
(48.51 MM)
1.890
~
'i'D.25M'MT
19 EaUAL SPACES
0.100
Ci TOL
NONCUM.
12.54 MMI
NOTE:
Pin No.1 is in lower left corner when
symbolization is in normal orientation
2·81
R6532
'1'
R6532
RAM-IIO-TIMER (RIOT)
Rockwell
DESCRIPTION
FEATURES
The R6532 RAM-I/O-Timer (RIOT) integrates random access
memory (RAM), parallel I/O data ports and timer functions into
a single peripheral device which operates in conjunction with
any CPU in the R6500 microprocessor family. It is comprised
of a 128 x 8 static RAM, two software-controlled, 8-bit bidirectional data ports allowing direct int~rfacing between the microcomputer and peripheral devices, a ·software programmable
interval timer with interrupt, capable of timing in various intervals
from 1 to 262,144 clock periods, and a programmable edgedetect circuit.
•
•
•
•
•
•
•
•
•
•
VSS
AS
A4
A3
A2
Al
AO
PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
PB7
PB6
PBS
PB4
Vee
ORDERING INFORMATION
Part Number:
.L
R6532"T __
Temperature Range:
Blank = O"C to + 70"C
E
=
-40"C to +85"C
Package:
C = Ceramic DIP
P = Plastic DIP
' - - - - Frequency:
No Letter = 1 MHz
A
=
128 x 8 static RAM
Two 8 bit bidirectional data ports
Programmable interval timerwith interrupt capability
TTL & CMOS compatible peripheral lines
One port has direct transistor drive capability
Programmable edge-sensitive interrupt input
8 bit bidirectional data bus
6500/6800 bus compatible
1 MHz and 2 MHz parts available
Single +5V powersupply
A6
<;1>2
eSl
eS2
RS
RIW
RES
DO
01
02
03
04
05
06
07
IRQ
PBO
PBl
PB2
PB3
R6532 Pin Configuration
2 MHz
Document No. 29000042
Data Sheet Order No. 042
Rev. 6, October 1983
2-82
R6532
RAM-I/O-Timer (RIOT)
INTERFACE SIGNALS
RESET (RES)
ADDRESS LINES (AO-A6)
5uri~g' system inttialization, a low RES' input causes a zeroing .
There are seven address pins (AO-A6). In addition, there is the
RAM SELECT (RS) pin. The pins AO-A6 and RS are always used
as addreSSing pins. There are two additional pins which are used
as CHIP SELECTS. They are pins CSI and CS2. Tables 1 and 2
identify-the functions selected and registers addressed depending
upon the address line and RS inputs in conjunction with the RMi
level.
.
of all four I/O registers. This in turn causes all I/O buses to act
as inputs thus protecting external components from Possible
damage and erroneous data while the system is being configured under software control. The·Data Bus Buffers are put into
an OFF~STATE during Reset. Interrupt capability is disabled wtth
the RES signal. The RES signal must be. held low for.at least
two clock periods when reset is required.
READIWRITE (RIW)
I/O PORTS (PAO- PA7, PBO-PB7) .
The. RJWSignal is suppliEjd by the microprocessor and controls
the transfer of data to and from the R6532. A high on the RJW
pin allows the processor to read (wtth proper addressing) the
data supplied by the R6532. A low on the RJW pin allows a write
(with proper addressing) to the R6532.
The R6532 has 16 pins available for peripheral I/O operations.
Each pin is individually software programmable to act as either
an input or an output. The 16 pins are divided into two 8-bit
ports, PAO-PA7 and PBO-PB7. (PA7 also has another use
which is discussed lateL) Each is set upas an input by writing
a "0" into the corresponding bit of the data direction register. A
"I" written into the data direction register causes its corresponding bit to be an output. When in the input mode, the
peripheral output buffers are in the "I" state and the internal
pull-up device acts as less than one TTL load to the peripheral
data lines. On a Read operation, the microprocessor reads the
peripheral pin. When the peripheral device gets information
from the R6532 it receives data stored in the data register. The
microprocesfl;Or reads valid pin information if the' peripheral lines
are greater Ihan 2.0 volts for a "I" and less than 0.8 volt for a
"0" as the peripheral pins are all TTL compatible. PinsPBOPB7 are also capable of sourcing 3 ma at 1.5V, thus making
them capable of Darlington drive.
INTERRUPT REQUEST (IRQ)
The IRQ pin is an interrupt pin from the interrupt control logic.
The pin will be normally' high wtth a low indicating an interrupt
from the R6532. An external 3K pull-up resistor is required. The
IRQ pin may be activated by a transition on PA7 or timeout of
the interval timer.
DATA BUS (00- 07)
The R6532 has eight bidirectional data pins (00-07). These pins
connect to the system's data lines and transfer data between ihe
R6532 and the microprocessor data bus. The output buffers
remain off, or tri-stated, except when the R6532 is selected for
a Read operation.
OO-D7
<
(,8)
"1~
Ao-A6
(10)
--'"
:
,
PAO-PA7
(lI)
.
v
.,
R6500
MICROPROCESSOR
BUS
INTERFACE
R6532
RIOT
PERIPHERAL
INTERFACE
(8)
RIOT Interface Signals
2-83
)
PBO:-PB7
R6532
RAM·I/O·Timer (RIOT)
Table 1. Address Decoding
A4
A3
A2
A1
AO '
-
--
-
,-
-
-
-
-
0
0
0
0\
0
0
0
0
0
0
1
1 ,
0
0
1
1
0
0
0
0
1
1
"
1
,1
1'
1
1
1
1
0
0
1
1
0
1
RS
R!W
Write RAM
Read RAM
0
0
0
1
Write Output Reg A
Read Output Reg A
1
1
0
1
-
Write DORA
Read DORA
1
1
0
-
Write Output Reg B
Read Output Reg B
1
1
0
1
1
0
1
Operation
,
Write DDRB
Read DDRB
.. '
Notes:
- = Don't Care, "1"
,
1
= High level (;,,2.4y),
"0"
= Low
(a) A3
A3
= 0 to disable interrupt from timer.tolRa
= 1 to enable interrupt from timerto IRO
(b) AI
, ,.' AI
= 0.19. disable interrupt frqm PA7 to'IRO
= 1 to enable interrupt from PA7, to IRO
---
-
--
0
0
0
0
1
1
0
1
1
1
1
1
-
-
1
1.
Write Timer
+1T
+8T
+64T
+1024T
Read Timer
Readlhtetrupt Flag
Write Edge Detect COIitrol
-
-
1
,
(a)
(a)
(a)
(a)
1
1
1
1
-
(a)
-
-
0
-
'~
(b)
0
1
0
1
(c)
level ("OAY)
(c) AO
AO
= 0 lor negative edge-detect
= 1 lor posHive edge-detect
"
;..
Table 2
Start
Address
$0
$1
$2
$3
$4
$4
$5
$5
$6
+
Register Addressing
Start
Address
Register/Function
ORA ('A' side data register)
DORA ('A' side data direction register)
ORB ('B' side data register)
DDRB (' B' side data direction register)
,Read timer (disable interrupt)
WrHe edge-detect control (negative edge-detect,
disable interrupt)
Read il)lerrupt flag register (bit 7 = timer, bit 6 =
PA7 edge-detect) Clear PA7 flag
Write edge-detect control (positive edge-detect,
disable interrupt)
Write edge-detect control (negative edge-detect,
enable interrupt)
$7
$C
$14
$15
$16
$17
$1C
$10
$1E
$11"
2,84
+
Register/Function
Write edge-detect control (posHive edge-detece,
enable interrupt)
Read timer (enable interrupt)
Write timer (divide by 1, disable interrupt)
Write timer (divide by 8, disable interrupt)
Write timer (divide by 64, disable interrupt)
Write timer (divide by 1024, disable interrupt)
Write timer (divide by 1, enable interrupt)
Write timer (divide by 8, enable interrupt)
Write timer (divide by 64, enable interrupt)
WrHe timer (divide by 1024, enable interrupt)
.
R6582 .
.
"
,
.' RAM-I/O-Timer (RIOT)
'NTERNAL ORGANIZATION
The R65S~ is divided into four basic sections, RAM, VO, Timer,
and Interrupt Control. The RAM int.erface.s directly,wit!:l.·the
microprocessor through the system data bus and address lines.
The
section oonsists of two 8-bit halves. Each half contains
a Data DirectiOn Register (DDR) and a Data Register (DR).
Data is·read directlyfrcim the data pins during any read operation. For any output pin, the data transferred into the processor,
will be the same as that contained in the Data Register if the
voltage on the pin is allowed to go to 2.4V for a logic one. Note
that for input lines, the processor can write. into the corre·
sponding bit of the Data Register. This will not affect the polarity
on the pin untiLthe corresponding bit of .oCRA is set to a logic
.one to allow the VO line to act as an output.
va
RAM-128 BYTES (1024 BITS)
The. 1,26 x8 Read/Write Memory acts as a conventional static
RAM. and can be accessed from the microprocessor by sel~ting
the chip (CS1 = high, CS2 = low) and by setting RS low.
Address lines AD through A6 then select the. desired byte of
storage.
The operation of the Port B is·exactly the same as the normal
I/O operation of the Port A. Each of 1t)6'eight lines can each be
programmed to act as either an input or as an output by placing
a D or a 1 into the Port B Data Direction register (DDRB). In the
output mode, the lioltagebna peripheral pin is controlled by the
Port B Data Register (ORB). .
1/0 PPRTS AND REGISTERS
The primary difference between Port A and the Port B is in the
operation of the output buffers which drive these pins. The Port
B output buffers' are push·pull deviGes whic:h are capable of
sourcing 3 rna at 1.5V. This allows these pins to directly drive
transistor switches. To assure that the midroprocessorwiII·read
proper data on a "Read Port B" operation, logic in the R6532
allows the microprocessor to read the Output Register instead
of reading the peripheral pin as on Port A.
The 110 Ports consist of eight lines which can be individually programmed to act as either an input or an output. A logie zero In
a bit of the Port A Data Direction Register (DORA) causes the
corresponding line of Port A to act as an input. A logic one
causes the corresponding Port A line to act as an output. The
voltage on any line programmed to be an output is determined
by the corresponding bit in the Port A Data Register (ORA).
PA7 PBO
PAD
+} -DATA
DIRECTION
REGISTER
A
DATA
BUS
BUFFER
DATA
REGISTER
A
r-+
07
A6
•P!i;RIPHERAL
OATA BUF!FER
E!,
CHIP
SELECT
128
1t
CS2
CS1
R/W
<1>2
x
RAM
R/W
j-- -1
AD
-l·:l---~t ~
PERIPHERAL
DATA BUFFER
A
ADDRESS
OECODER
t--- ~t
DO
,
PB7
RS
R6532 Bloc.k Diagram
2·85
B
r--
DATA
REGISTER
.
B
INTERRUPT
CONTROL
1
IRQ
~
DATA
DIRECTION
REGISTER
B
INTERVAL
TIMER
2
R6532
RAM-I/O-Timer (RIOT)
EDGE DETECTING WITH PA7
In addition to acting as a pe(ipheral I/O line, the PA7 line can
be used as an edge,delecting input. In'thismode, an aclive Irans~ion sets the internalinterrllptflag (bit 6 of the Interrupt Flag
register). Setting the interrupt flag causes IRQ output to go low
if the PA7 interrupt has been enabled.
DUring system initialization, the interruptflag may inadvertently
be- set--by.an unexpected trans~lon onthePA7. II is therefore
recommended that the interrupt flag be cleared before enabling
interrupting from· PA7. To clear PA7 interrupt flag, simply read
the interrupt Flag Register,
Control of the PA7 edge detecting mode is accomplished by
. writing to one of four addresses. In this operation, AOcontrols
the polarity of the active transition and. A1acts to enable or disable inlerruptingofthe processor. Tt)e data which is placed on
the .Data ellS during this ope rat jon is discarded and has no
effect on the control.of PA7. ,
INTERVAL TIMER
The Timer section of the R6532 contains three basic parts: preliminary divide down register, programmable 8'bit register and
interrupt logic.
The Timer can b.e programmed to count up to 255 time intervals.
Each time interval can be either 1T, ST, 64T or 1024T increments, where T is the system clock period. When a full count
is reached, an interrupt flag is set to logic"1". After the interrupt
flag is set the internal clock begins counting down at the system
clock rate to a maximum of ;-255T.. Thus, !lfter the interrupt flag
is set,a Rea9 of the timer
tell how long since the flag was
set up t6 a m!pst interface.
The ODR serves as a temporary storage for data from the
device to the Host.
Interr4Pt Flag Register (IFR)
and Interrupt Enable Register (IER)
A Host Status Flag RegiSter facilitates a software protocol
The device includes an Interrupt Flag Register and an Interrupt Enable Register which flags and controls I/O and counter
status.
that permits independent and uninterrupted flow of data
asynchronously between the Host Compuler and the deVies:
The Host ~atus Flag Register contains eight fla9bits that
can be read at any time byejther the Host or tile device.
. . . .,Q
II
INT~C II
I .... II
l.. mu.!I00RT1
I
II
I
~1CIj I
CLKc:KTS
EDGEDO
R=:R
CPu
UK
PORTA
ROM,
PORTC.
..
PAO-PA7.
(P_
PAQ.PA7
(P....PED)
~~
(PA1-NED)
_
(P~
::.=......r..
.P80-P87
(DOr.D7,"Tfl.STATE)* ,
TE)..
... .
~.,
PCO-PCS
(AO, A1, AI, A3.
liii,RIW,INT)"
.... .u.
. . . . . INT)·
CCNTROL REO "
HIIOoH87 .
J INP~:-TA H~ciDAT"1
HfIO.HB1
......,.....
PGOoPG7
.......
~~~~
________
PCRT G
II
I
rtNi
SYNC
PEG-PE7
PCRT •
PFOoPF7
PCRT F
ReIiOO/42
~~-N.
·MUL1IP..-q.~
• MULTIPLEXED OPTION
2-94
Darlington Output Onty
I........
.-o
MEMORY MAP
RB500/41 AND RB500/42
NORMAL BUS MODE
FFFE 1
FFFC
IRQ VECTOR
'RES VECTOR
c
ABBREVIATED BUS MODE
I
Iilo VECTOR
FFFE
FFF
FFfA
RES VECTOR
FFFC
FHA
ROM (I.6KI
FAoO
.....
I
IRO- VECTOR
-RES VECTOR"
(WIBOOT STIW' IIOMI
FFFE
,
-me
. I
FHA
ROM (I.&KI
(W/O BOOT STUP 110M)
IROVECTOR
FFFE:
IRO
(OP RESET VECTORI
FFFC
FFFA
RES
NMIVECTOR
,
I
FAOOI
FAOO
-
_1 • R1181143
~
MULTIPLEXED BUS MODE
FFFd
ROM 11.6KI
I...
I
~
t
NMI
4K
USER
PROGRAM
4K
USER PROG RAM
FOOl
FOOD
INTERIAL.REGlSTERS
READ
RESERVED
RESERVED
;
I
NOT AVAILABLE
L
RESERVED
TUFF
f
F
PERJPHERAL
ADDRESSES
(161
I...!Il
1,00
ODIF
EXTERNAL MEMORY
4096-128
I~
001
0040
OOlf
110 & REGISTERS
ou...~
--Hast
OIl IIF
011IlE
011 110
B•• Buffer 011 ITC
L_l.atchA
Upper LalehA· #
Upper IJotchA
til Ij8
til IA
00 19
01 18
--Mod. Control Ron.
:
In_pI Enoble Reg.
In_pt Flog Rag.
Intor..pl E...... Reg.
iliad fF
Clr Intorrupl Flag Reg.
12
0011
0010
--
00117
16
15
14
I~
oooF
I
I
lID PORTS E. F,. G
(R_142 ONLY)
NOT AVAILABLE
VO PORTC
0DD8
DOO4
0003
'02
va PORT B
110 & REGISTe RS I
I/O PORT A
ODOO
"-ANDSIART COUNTER
CLEAR FLAG
#
o:s
1,
':r
-a"
S'
~-.,
,"...
::t
0007
OOIF
OOIF.
• 1!DDO
ADDILEss
-HBB SlIItus Regist..
NOT AVAILABLE
RESERVED
RESERVEn
r
110:a REGISTERS
0040I
Ii';;' R'~ Buffi,.
-
Mo!ILControlRag.
I
IljHRNAL,
RAM (641
INTERNAL
RAM (64)
RESERVED
11000
:
007F
I•••t
--
I
I
EXTERNAL
MEMORY·
4058-128
008
0100
OD7F
INTERNAL RAM(MI
110 & REGISTERS
0000
BOOTSTRAP.
ROM (266)
;;'~IIS Register
t::,Coo!nllrA#
Countor A
I
RESET vECTOR
HBB
~rCounllrA
I
Off F
NOT
AVAILABLE
RESUVED
110 & REGISTERS
oFOD
0040
0040
RESERVED
0000
::;
;!
INTERNAL RAM (641
INTERNAL RAM (641
,
oFFC
OFFB
LOloO
007F
1107
0040
OFFf
c
c
::;
;!
007F
1000
WRITE
0000
~
~,
i
e.
9
-f
:t,
i,
II
One-Chip Intelligent PeripheralCo'ntrolier
R6541Q.• R6500/41, 142,/43
KEY REGISTER SUMMARY
CPU Registers
7
I
I ACCUMULATOR
A
7
.
I
I
7
,.
1"1
vi
1"1
OJI
I
INDEX REa.STER
I zl
ci
L
INDEX REGISTER Y
0
I7
PC"
A
0
I
:~.,'
Processor Status Register
0
x
0
PCL
I PAOGRAM COUNTER
PC
I7
0
SP
I
STACK
POINTER
S
I7
0
I-Ivl I" lol' I1 I0 I PROCI!SSOR S7ATUS REG P
CARRY (e) (1)
1 = carry Set
0"" carry CI,.r
_(1)(1)
1 = Zero Result
o
=
Non-Zero Reauh
INTERRUPT DISABLE (I) (2)
1 "" IRQ Interrupt Di••bJed
o = IRQ Interrupt Enabled
DECIMAL MODE (D) (1)
1 '" Decimal Mode
0= BInary Mode
BREAK COMMAND (B) (1)
Mode Control Register
1 "'" Break Command
o ." Non·B.... k Command
MeR
OVERFLOW M (1)
ADDA 0014
1 = Ov,rflow Sel
o '" Overftow Clear
NEGATIVE (N) (1)
"0TES
(1). Mat InJtlalized bV RES
(2) ~ to Laglc 1 by RES
1 '" N"atlve Value
D '" PoSitiVe Value
INTERVAL TIMER
PULSE GENERATOR
EVENT COUNTER
NOT USED
BUS SELECT
o = 850011100 SUS
PULSE WIDTH MEASUREMENT
Interrupt Enable and Flag Registers
1 =·Do/8080 BUS
IN'fSELECT
0"" pea
1 .lIif
IER
ADDA 0012
PORT B ALL INPUTS
PORT BALL OUTPln'S
ABBAEYIATEP'8US MODE
MULnpLEXED BUS MODE
ADDR 0011
.Host Status Flag Register
HSFR
PAO POSITIVE
EDGE DETECT
INTERRUPT ENABLE
ADDA 001E
PA1 NEGATIVE
EDGE DETECT
INTERRUPT ENABLE
INTERNAL INTERRUPT
REQUEST INTERRUPT ENABLE
EXTERNAL INTERRUPTS REQUEST 1,
I,..T-1 ENABLe
INPUT DATA REGISTER
FULL FLAG
EXTERNAL INTERRUPT REQUEST 2,
INT-2 ENABLE
COUNTER UNDERFLOW
lNTERRUPT ENABLE
OUTPUT DATA REGISTER
FULL FLAG
Host Addressing Matrix
RS(Ao>
COPIES RS ON
WRITE FROM HOST
WRITE
1
COMMAND
INPUT
0
DATA REG
INPUT
DATA REG
OUTPUT
GENERAL PURPOSE
FLAGS STATUS REGISTER
2·96
READ
HOST
STATUS FLAG
R6541Q. R6500/41, /42,143
One-Chip Intelligent Peripheral Controller
!~,.,,- .
(2.54 MU)
DOT OR NOTCH
TO lOCATE
PIN NO. 1
0.155 MAX
(3.93 MM)
.t
'nterrace Diagram
-,.,'"
0.010 MIN
r.--
(0,25 MM)
~~----')
.--'"-<'-'--'-_40
E (iiii) 2
(48.51 MU)
(48.00 MM)
RiW(WA) 3
RS (AD)
•
HD2 7
2.050 MAX
(51.30 111M)
19 EDUAl SPACES
0.100 de control register allows noninterlaced video
display modes at 50 or SO Hz refresh rate. The internal status
~ter may be used to monitor the RS545-1 operation. The
RES input allows the CRTC-ger:terated field rate to be dynamically-synchronized wah line frequency jitter.
vss
REs
LPEN
CCO/MAO
CC1/MAl
CC2/MA2
CC3/MA3
CC4/MA4
CC5/MA5
CC6/MA6
CC7/MA7
CRO/MA8
CR1/MA9
CR2/MA10
CR3IMA11
CR4IMA12
CR5/MA13
DISPLAY ENABLE
CURSOR
ORDERING INFORMATION
Part Number: R6545-1 __ _
[
Light pen register
Addresses refresh RAM to 1SK characters
No external DMA required
Internal status register
40-Pin ceramic or plastic DIP
Pin-compatible with MCS845
Single +5 ±5% Volt Power Supply
Operating Temperature (T l to T H)
No letter = DOC to 7Doc
E = -40°C to 85°C
Package
P = Plastic
C = Ceramic
vec
Operating Frequency
No Letter = 1 MHz
VSYNC
HSYNC
RAO
RAl
RA2
RA3
RA4
DO
D1
D2
D3
D4
D5
D6
D7
cs
RS
'2
RNi
CCLK
R6545-1 Pin Configuration
A=2MHz
Document No. 29000067
2-100
Data Sheet Order No. 067
Rev. 1, June 1983
CRT Controller (CRlC)
R6545·1
INTERFACE SIGNAL DESCRIPTION
VIDEO INTERFACE
Figurlil 1 iUustrates the interface between the CPU, the R6545-1,
.and the video circuitry. Figure 2 shows typical timing waveforms
at the video interface.
Vee
00-01
GNO
HSYNC (Horlzontal.Sync)
The HSYNC active~high output signal determines ti)e horizontal
position o/displayed text. It may drive a CRT monitor directly
or may b",.used for composite video generation. HSYNC time
position and width are fully programmable.
VIDEO ifF.
~=::>f""""--~r"""~ HSYNe
'VSYNC
DISPLAY ENABLE
. CURSOR
LPEN
CCLK
RES
02
Rfji
CS
RS
VSYNC (Vertical Sync)
The VSYNC active-high output signal determines the vertical
position of displayed text. Like HSVNC, VSYNC may.drive a
CRT monitor or compOSite video generation Circuits. VSYNC
time position and width are both programmable.
DISPLAY ENABLE (Display Enable)
MAo-MA13 RAo-RA4
REFRESH RAM AND CHARACTER ROM
The OISPLAY ENABLE active-high output signal indicates when
theR6545-1is generating active display information. The number
othorizontal display characters per row and the number. of vertical display rows are both fully programmable and together generate the DISPLAY ENABLE signal. DISPLAY ENABLE delays
one ci)aracter time by setting bit 4 of RS to a 1.
Figure 1. R6545-1 Interface Diagram
CPU INTERFACE
82 (Phase 2 Clock)
CURSOR (Cursor Coincidence)
The Phase 2 (fJ2) input clock triggers all data transfers between
the systlilm .proclilssor (CPU) and the R6545-1. Since theflil is
no maximum limit to the allowable ~2 clock .time, if is not nec.essary for it to be a continuous clock. This capability permits
the R6545-1 to be easily interfaced to non-6500 compatible
microprocessors.
The CURSOR active-high output signal indicates when the scan
coincides with the programmed cursor position. The cursor
position is programmable to any character in the address field.
Furthermore, within the character, the cursor may be programmed to be any block of scan lines, since the start scan line
and the end scan line are' both programmable. The cursor
position may be delayed by one character time by setting Bit 5
ofRBtoa1.
RIW (Read/Write)
The RJW input Signal glilnerated by the processor contrqls the
diflilction of data transfers. A high on the R/W pin allows the
processor to read the data supplied by the R6545-1, a 10";' on
the RJW pin allows data on data lines 00-07 to be written into
the R6545-1.
LPEN (Light Pen Strobe)
The LPEN edge-sensitive input signal loads the internal Light
Pen Rlilgister with the contents of the Refresh Scan Counter at
the time the active edge occurs. The low-to-high transition
activates LPEN.
CS(Chip Select)
The Chip Select input is normally connected to the prOcessor
address bus either directly or through a decoder. The R6545~1
is selected when CS is low.
CCLK (Clock)
The CCLK character timing clock input Signal is the time base
for all internal count/control functions.
RS (Register Select)
The Register Select input accesses internal registers. A low on
this pin permits wiites (RJW = low) into the Address Register
.and reads (RJW = high) frOm the Status Register. The contents
of the Address Register is the identity of the register accessed
when RS is high.
RES
m
The
active-low input signal initializes all internal scan
counter circuits. When RES is low, all internal counters stop and
clear all $can and video outputs go low with no affect on control
registers. RES must stay low for at least one CCLK period. All
scan timing initiates when RES goes high. In this way, RES can
synchronize display frame timing with line frequency. RES may
also synchronize multiple CRTC's in horizontal and/or vertical
.
split screen operation.
00-07 (Data Bus)
The eight data lines (00-07) transfer data between the processor and the R6545-1. These lines are bidiflilctional and.are
normaily high-impedence except during rel!,d cycles when the
chip is selected (CS = low).
2-101
2
R6545-1
CRT Controller (CRTC)
REFRESH RAM AND CHARACTER ROM
INTERFACE
RAQ-RA4 (Raster Address Lines)
These five active-high output signals ~elect each raster. scan
within an individual character row. The number of raster scan
lines is programmable and determines the character height,
including spaces between character rows,
MAQ-MA13 (Refresh RAM Address Lines)
These 14 active-high output signals address the Refresh RAM
for character storage and display operations. The fully programrnable starting scan'address and endil1g scan address de.termines the total number 'of characters displayed, in terrns' of
characters/line and lines/frame.
The high-order line, RA4, is unique in thaI. it can also function
as a strobe output pin when the R6S4S-1 is programmed to
operatEl in the "Transparent Address Mode." In this case the
strobe is an active-high output and is true at the time the Refresh
RAM update address gates on to the address lines, MAO-MA13,
In this way, updates and readouts of the Video Display RAM
can be made under control of the R6S4S-1.with only a small
amount of external circuitry,
There are two selectable address modes. for MAO-MA 13:
In. the. straight binary mode (R8, Mode Control, bit :2 = 0), characters are .storedin successive memory locations, Thus, the
software design. ,must translate row and column character
coordinates into sequentially-numbered addresses. In the row/
column mode (R8, Mode Control, bit 2 = 1), MAO-MA7 become
column addresses CCO-CC7 and MA8-MA13 become row
addresses CRO-CRS. In this case, the software manipulai~s
characters in terms of row and column locations, but additional
address compression circuits are needed to convert the GCOCC7 and CRO-CRS addresses into a memory-efficient binary
address scheme.
-l
1 COMPLETE FIELD (VERTICAL TOTAL)
VERTICAL DISPLAYED
I
DISPLAY
ENABLE
HSYNC
VSYNC
--
RA~RA4
~
1 COMPLETE SCAN LINE (HORIZONTAL
TOTA~
HORIZONTAL DISPLAYED
I
CCLK
DISPLAY
ENABLE
~
------------------1
1-1
HSYNC
RA~RA4
____~~~------------------------------------------------~~--
Figure 2.
Vertical and Horizontal Timing
2-102
CRT Controller (CRTC)
R6S4&-1
INTERNAL REGISTER DESCRIPTION
STATUS REGISTER (SR)
Table.1 summarizes the internal registers and indicates their
address selection and read/write capabilities.
3
ADDRESS REGISTER
2
o
This 8-bit register contains the status of the CRTC. Only three
bits are assigned, as follows:.
o
Ao
SR
7
This 5~bit write-only register is used as a "PI>inter" to direct
CRTC/CPU data .transfers within the CRTC. It contains the
number of the desired register (0-31). With. CS and RSlow, this
register may be loaded; with CS low and RS high, the selected
register is the one whose identity is stored in this address
register.
-0
UR -Update Ready
This bit goes to 0 when register R31 has been either
read or written by the CPU.
This bit goes to 1 when an Update strobe occurs.
SR
6
-0
1
SR
5
-0
LRF -LPEN Register Full
Register R16 or R17 has been read by the CPl).
LPEN strobe has been received.
VRF -Vertical Re.Trace
Scan is not currently in the vqrtical re-trace time.
Scan currently i.n its vertical re-tr~ time. Note that
this bit actually goes to a 1 when vertical re-trace
starts; but goes to a 0 five character clock times
befOre vertical re-trace ends to ensure that criticil.1 timings for refresh RAM oper",tlOns are avoided. .
SR
+0
-Not used.
Table 1. Internal Register Summary
g:=~:: ~::e~it b~ ~~::~er. Reading this bit is always 0, except for R31, which daBs
not drive the.data bus at all, and for CS "" 1 which operates Hkewlse.
2-103
II
CRT Controller (CRTC)
R6545-1
RO-HORIZONTAL TOTAL CHARACTERS
7
1 6.1
14 1
1 2·1
to the line frequency to ensure flicker-free appearance. If the
frame time is adjusted to be longer than the~ period of the line
frequency, then ~ may provide absolute synchronism.
o
5
3
NUMBER OF CHARACTERS -1
RS-VERTICAL TOTAL LINE ADJUST
This a-bit write-only register contains the total of displayed and
non-displayed characters, minus one, per horizontal line. This
register determines the frequency of HSYNC.
1
1 6.
,I .
5,
14
I' 3
12 11 10
NUMBER OF CHARACTERS
R6-VERTICAL DISPLAYED ROWS
This a-bit write-only register contains the number 01 displayed
characters per horizontal line.
o
DISPLAYED CHAR. ROWS
R2-HORIZONTAL SYNC POSITION
7
16 1
5
14 13 12
o
The S-bit write-only Vertical Total Line Adjust Register (RS) contains the number of additional scan lines needed to complete
an entire frame scan and is intended as a fine adjustment for
the video frame time.
R1-HORIZONTAL DISPLAYED CHARACTERS
7
1
\.1
10
This 7-bit write-only register contains the number of displayed
character rows in each frame. This determines the vertical size
of the displayed text.
HOfllZONTAL SYNC POSITION
This a-bit write-only register cO!'!tains the position of HSYNC on
the horizontal,line, ,in ierms of the ,character location number on
t~ line. TI16 position of the HSYNC determipes the left to right
location of tlie displayed text on the video Screen: In this way,
the side margins are adjusted.
R7-VERTICAL SYNC POSITION
I
~
1
6
5
1
I,
4
I
3
1
2
I
1
o
VERTICAL POSITION
This 7-bit write-only register selects the character row time at
which the vertical SYNC pulse is desired to occur and, thus,
positions the displayed text in the vertical direction.
R3-HORIZONTAL AND VERTICAL SYNC WIDTHS
RS-MODE CONTROL (MC)
o
o
This a-bit write-only register contains the widths of both HSYNC
and VSYNC, as follows:
HVSW
VSYNC Pulse Width
7·4
This a-bit write-only register selects the operating modes of the
R6545-1, as follows: .
The width of the vertical sync pulse (VSYNC) in the
number of scan lines. When bits 4-7 are all 0, VSYNC
is 16 scan lines wide.
'
MC
7
HVSW
3-0
HSYNC Pulse Width
()
The width of the horizontal sync pulse (HSYNC) in
the number of character clock times (CCLK).
UM(T) -Update/Read Mode (Transparent Mode)
Update occurs during horizontal and vertical blanking
times with update strobe.
Update interleaves during 162 portion of cycle.
MC
Control of these parameters allows the R6S45-1 to interface with
a variety of CRT monitors, since the HSYNC arid VSYNC timing
signals may be accommoqated without the use of external one
shot timing.
6
()
1
US(T) -Update Strobe (Transparent Mode)
Pin 34 functions as memory address.
Pin 34 functions as update strobe.
MC
R4-VERTICAL TOTAL ROWS
5
()
1
MC
4
The 7-bit Vertical Total Register contains the total number of
character rows in ,a frame, minus one. This register, along with
RS, determines the overall frame rate, which should be close
()
2-104
CSK
-Cursor Skew
No delay
Delays Cursor one character time.
DES
-Display Enable Skew
No delay
Display Enable delays one character time.
CRT C.ontroller (CRTC)
R6545-1
MC
,3
RRA -Refresh RAM
If
These registers form a 14-bit register whose 'contents is the
memory address of the first character of the displayed scan (the
character
the topleffof the vi,deo display, as in Figure 1).
Subsequent memory addresses are generated by the R6545-1
as a result of CCLI< input pulses. Scrolling of the ~isplay is
accomplished by changing R12 and R13 to the memory address
associated with the first character of the desired lineet text to
be displayed first. Entire pages of text may be scrolled or
changed as well via R12 and R13.
~cess
on
Shared memory access
Transparent memory access
1
MC
2
RAD
o
-R~sh
RAM Addressing Mode
Straight binary addressing
Row/column addressing
1
MC
R14-CURSOR POSITION HIGH
-Not Used-don't care
1
5
4
MC
3
1
o
2
CURSOR-POSITION HIGH'
o
-Not Used-must be a O.
R15-CURSOR POSITION LOW
R9-ROW SCAN UNES
3
o
2
7
6
R10-CURSOR START LINE
3
o
2
START SCAN LINE
3
o
2
END SCAN LINE
80
0
0
1
1
0
1
0
1
Cursor Operating Mode
Display Cursor Continuously
Blank Cursor
Blink Cursor at 1/16 Field Rate
Blink Cursor at 1/32 Field Rate
UNDERL.INE
CURSOR
A one character wide cursor can be controlled by storing values
into the Cursor Start Line (Rl 0) and Cursor End Line (Rll) regi~ers and into the Cursor Position Address High (R14) and
Cursor Position Low, (R15) registers.
0
1
R12-DISPLAY START ADDRESS HIGH
DISPLAY START ADDRESS HIGH
R13-DISPLAY START ADDRESS LOW
7
6
5
1
4
1 3
I
2
1
31
I·
2
o
The cursor is positioned on the screen by loading the Cursor
Position Address High (R14) and Cursor Position Address.Low
(R15) . registers. with the desired refresh RAM address. The
cursor can be positiQlledir'l any of the '16K character poSitions.
Hardware paging and data scrolling is thus allowed without loss
of cursor position. Figure 3 is an example of the display cursor
scan line.
These 5-bit write-only registers select the starting and ending
scan lines for the. c:ursor. In addition, bits 5 arid 6 of Rl0 are
used to select the cursor blink mode, as follows: .
B,
4
A cursor' of up to 32 characters in height can be displayed on
and between the scan lines as lOaded into the Cursor Start Line
(Rl0) and Cursor End Line (Rll) Registers.
R11-CURSOR END UNE
4
1
These registers form a 14-bit .register whose contents is the
memory address of the current cursor position. When the video
display scan counter (MA lines) matches the contents of this register, and when the scan line counter (M lilies) falls within the
bounds set by Rl0 and Rl1, then the CURSOR output becomes
active. Bit 5 of the Mode Control.Register (RS) may be used to
delay the CURSOR output by a full CCLK time to accommodate
slow access memories.
This 5-bit write-only register contains the number of scan lines,
minus one, per charaCter row, including spacing.
41
5
CURSOR POSITION LOW'
SCAN LINES -1
o
DISPLAY START ADDRESS LOW
OVERLINE
CURSOR
0
1
2
2
3
4
5
4
5
6
6
3
7
e
7
·8
9
10
9
n
10
11
BOX
CURSOR
0
1
2
3
4
5
6
7
8
9
10
'11
CURSOR START
LINE = 9
CURSOR START
LINE = 1
CURSOR START
LINE = 1
CURSOR END
LINE = 9
CURSOR END
LINE ""1
CURSOR END
LINE =9
Figure 3. Cursor DI!ilplayScan Line COntrol Examples
2-105
fJ
R6545-1
CRT Controller (CRTC)
R16-LIGHT PEN HIGH
7
I ~ Is
3
4
These registers together comprise a 14-bit register whose contents is the memory address at which the next read or update
will occur (for transparent address mode, only). Whenever a
read/update occurs, the update location automatically increments to allow for fast updates or readouts of consecutive character locations. This is described elsewhere in this document.
The section on REFRESH RAM ADDRESSING describes this
more fully.
o
2
LPEN HIGH
A17-LlGHT PEN LOW
3
o
2
LPEN LOW
R31-DUMMY LOCATION
These registers form a 14-bit register whose contents is the light
pen strobe position, in term.s of the video display address at
which the strobe occurred. When the LPEN input changes from
low to high, then, on the next negative-going edge of CCLK, the
contents of the internal scan counter is stored in registers R16
and R17.
3
I ~ I~ I
o
REGISTER FORMATS
UPDATE ADDRESS HIGH
Register pairs R121R13, R141R15, R16IR17,.and R1B/R19 are
formatted in one of two ways:
R19-UPDATE ADDRESS LOW·
7
6
sl
4
I
3
I
(1) Straight binary, if register RB, bit 2 = 0
(2) Row/Column, il register RB, bit 2 = 1. In this case the low
byte is the Character Column and the high byte is the Character Row.
o
2
UPDATE ADDRESS LOW
NUMBER OF HORIZONTAL TOTAL CHARACTERS (RO)
rr--------------------~A~-----------------NUMBER OF HORIZONTAL DISPLAYED CHARACTERS (R1)
I
o
This register does not store any data, but is required to detect
when transparent addressing updates occur. This is necessary
to increment the Update Address Register and to set the Update
Ready bit in the status register.
R18-UPDATE ADDRESS HIGH
s
2
/'
DISPLAY START
AD~RESS HIGH (R12)*
__~,
'
~ DISPLAY START ADDRESS LOW (R13)*
11i1l1l~1I~~;;~~~~~~~~~~~~~}
.~
SCAN LINES (R9)
NUMBEROF
CURSOR START LINE (R10)
~CURSOR END LINE (R11)
L\
NUMBER OF
VERTICAL
TOTAL
ROWS
(R4)
b~RSOR POSITION ADDRESS HIGH (R14)
CURSOR POSITION ADDRESS LOW (R1S)
NUMBER OF
VERTICAL
DISPLAY
ROWS
(RS)
HORIZONTAL
RETRACE
PERIOD
(NON-DISPLAY)
DISPLAY PERIOD
'~~--------------------~--------,
VERTICAL RETRACE PERIOD
(NON-DISPLAY)
VERTICAL
TOTAL
{
ADJUST (RS) .
Figure 4.
Video Display Format
2-106
CRT Controller (CRTC)
R6545-1
Shared Memory Mode (R8, BIT 3 = 0)
DESCRIPTION OF OPERATION
In this mode, the Refresh RAM address lines (MAQ-MA13)
directly reflect the contents of the internalrefr'esh scan character
counter. MuHiplex control, to permit addressing and selection of
the RAM by both the CPU and the CRTC, must be provided
external to the CRTC. In the Row/ColUmn address mode, lines
MAO-MA7 become character column addre,sses (CCO-CC7) and
MA8-MM3 become character row addresses (CRO-CR5). Figure
5 illustrates the system configuration.
VIDEO DISPLAY
Figure 4 indicates the relationship of the various program registers in the R6545-1 and the resuRant video display.
Non-displayed areas of the Video Display are for horizontal and
vertical retrace 'functions oftheCRTmon~or. The horizontal and
vertical sync signals, HSYNC and VSYNC, are programmed to
occur during these intervals and trigger the retrace in the CRT
monitor. 'The pulse widths are constrained by the monitor
r~quirements. The time position of the pulses may be adjusted
to vary the display margins (left, right, top, and bottom).
Transparent Memory Addressing
For this mode, the display RAM .is not directly accessible by the
CPU, but is controlled entirely by the R6545-1: All CPU accesses
are made via the R6545-1 and a small amount of external circuits.' Figure 6 shows the system configuration for this approach.
~EFRESH RAM ADDRESSING '
There are two modes of addressing for the video display memory:
SYSTEM
BUS
VSYNC
HSVNC
R854$-1
CRT CONTROLLER
DISPLAY ENABLE
RAG-RA4
TO
VIDEO
CIRCUITS
CURSOR
CPU
SCAN UNE
COUNT
CtlARACTER
DATA
Figure 5.
StllFT
'REGISTER
' - -_ _,.j
SCAN UNE
DOT PATTERN
Shared Memory System Configuration
SYSTEM
BUS
Rase1
CRT CONTROLLER
RA4
CPU
MAG-MA13
UPDATE
STROBE
RAG-RA3
DISPLAY/UPDATE
ADDRESS
SCAN UNE
COUNT
CHARACTE
GENERATO
ROM
CtlARACTER
DATA
Figure 6.
CHARACTER
DATA
Transparent Memory Addressing System Configuration
(Data Hold Latch Needed for HorlzontalNertical Blanking Updates, Only).
fJ
R6545-1
CRT Controller (CRTC)
viable technique, since the Display Enable signal controls the
actual video display blanking. Figure 7 illustrates Refresh RAM
addressing for both row/column and binary addressing for 80
columns and 24 rows with 10 non-displayed columns and 10
non-displayed rows.
ADDRESSING MODES
Figure 7 illustrates the address sequence for both modes of the
Refresh RAM address.
Row/Column
Note that the straight-binary mode has the advantage that all
display memory addresses are stored in a continuous memory
block, starting with address 0 and ending at 191 g. The disadvantage with this method is that, if it is desired to cf)ange adisplayed character location, the row and column identity of the
location must. be converted to its binary address before the
memory may be wr,itten. Therow/column mode, .on the otber
hand, does not need to undergo this conversion. However,
memory is not used as efficiently, since the memory addresses
are not continuous, gaps exist. This requires that the system be
equipped with more memory than actually used' and this extra
memory is wasted. Alternatively, address compression log.ic
may be employed to translate the row/column format into a continuous address block.
'
In this mode, the CRTC address lines (MA()-MA13) generate as
8 column (MAO-MA7) and 6 row (MA8-MA13) addresses. Extra
hardware is needed to compress this addressing into a straight
binary sequence in order to conserve memory in the refresh
RAM (register R8, bit 2 is a 1).
Binary
In this mode, the CRTC addres.slines are straight binary and
no compression circUits are needed. However, software complexity increases since the CRT characters cannot be stored in
terms of their row and column locations, but must be sequential
(register R8, bit 2 is a 0).
USE OF DYNAMIC RAM FOR REFRESH MEMORY
The user selects whichever mode is best for the given application. The trade-offs between the modes are software versus
hardware. Straight-binary mode minimizes hardware requirements and row/column minimizes software requirements.
The R6545-1 permits use of dynamic RAMS as storage devices
for the Refresh RAM by continuing' to increment memory
addresses in the non-display intervals' of the ·scan. This is a
r-----~--TO~L=~------------'I
rl------ TOTAL"
I
~
r------ DISPLAY = 80 ---"1
r - - - - COLUMN ADDRESS CMAO-MA7)
90 ~--------,
DISPLAY
I;!;~
II,
~
~
~
ic
,80:
,8 ',
6
'2
82
- - - ., - - 17
--- --- 157
162 - - - - - - 237
78
79
158159
80
1150
S1" - - - 89
161 _M_ 1"69
238
240
241 - - - 249
239
.._'":1....~:,:
II1
I~
~
L
77
78
79
2
_ .. - - - - 77
258 - - - - - - 333
78
334
514 ------589590
I
-------,
80
81
79
335
80
336
81
337
89 '
591
59~
593 --- 601
,
345
i :,I-:-,:+-+-+--+-+-t-+.;--t-+---+-t---i--i
2; ~:-+-I-+---I--+--+-I--C+-f-+-+....;.;
E' 22 563256335634 - - - - -- 5709 5710 5711 57125713 - - - 5721
6l
L
I
176017611762--- .-- 183718381839 1840 1841----1849
1920 1921 1922 - -
~
..
~
- - - 1997 1998 1999 2000 2001 - - - 2009
"
"
264026412642--- --- 2717 27182719 27202721 .. -- 2729
5888' 5889 5890
..0.
-
-
-
-
-
5965 59665967 5968
596~
- - '. 5977
ROW/COLUMN ADDRESSING SEQUENCE
STRAIGHT BINARY ADDRESSING SEQUENCE
Figure 7.
.
24 6144 6145 6146 -, - - - - - 6221 6222 6223 6214 6225 - - - 6233
L: : : :::~ : : ~ -~ ~ ~~ : : : : : : : : :::~ -~ : :
2000 2001 2002 - - - - - - 2077 2078 2079 2080 2081 - - - 2089
,,
D
~.~
1917 191819191920 '921 _.- 192'9
Display Address Sequences (with Start Address =0) for 80 x 24 Example
2-108
I
89
:5',:
~ ~ ~
~ ~;
18401841 1842 -- - - [
= 80
CRT Controller (CRTC)
TRANSPARENT MEMORY ADDRESSING
MEMORY CONTENTION SCHEMES FOR
SHARED MEMORY ADDRESSING
In this mode of operation, the video display memory address
lines are not switched by contention circuits, but are generated
by the R6545-1. In effect, the contention is handled by the
R6545-1. As a resuR, the schemes for accomplishing CPU
memory access are different:
From the diagram of Figure 5, it is clear that both the R65~-1
and the system CPU must address the video display memoty.
The R6545-1 repetitively fetches character information to generate the video signals in order to keep the screen display
active. The CPU occasionally accesses the memory to change
the displayed information or to read out current data characters.
Three ways of resolving this dual-contention requirement are
apparent:
• 1/cP2 Interleaving
This mode is similar to the Interleave mode used with shared
memory. In thiS case, however, the q,2 address is generated
from the Update Address Register (R18 and R19) in the
R6545-1. Thus, the CPU must first load the address to be
accessed into R18/R19 and then this address is always gated
onto the MA lines during cP2. Figure 9 shows the timing.
• CPU Priority
In this technique, the address lines to the video display
memory are normally driven by the R6545-1 unless the CPU
needs access, in which case the CPU addresses immediately
override those from the R6545-1 giving the CPU immediate
access.
• <1>1/<1>2 Memory Interleaving
This method permits both the R6545-1 and the CPU access
to the video. display memory by time-sharing via the system
<1>1 and <1>2 clocks. During the <1>1 portion of each cycle (the
time when <1>2 is low), the R6545,1 address outputs are gated
to the video display memory. In the <1>2 time, the CPU address
lines are switched in. In this way, both the R6545-1 and the
CPU have unimpeded access to the memory. Figure 8 illustrates the timings.
_
CPU CYCLE
--1---
1/<1>2 Transparent InterleaVing
1/<1>2 Interleaving
• Vertical Blanking
With this approach, the address circuitry is identical to the
case for CPU Priority updates. The only difference is that the
Vertical Retrace status bit (bit 5 of the Status Register) is
used by the CPU so that access to the video display memory
is only made during vertical blanking time (when bit 5 is a 1).
In this way, no visible screen perturbations result. See Figure
10 for details.
CURSOR AND DISPLAY ENABLE SKEW CONTROL
Bits 4 and 5 of the Mode Control register (RS) are used to delay
the Display Enable and Curser outputs, respectively. Figure 12
illustrates the effect of the delays.
2-109
fI
R6545-1
CRT Controller (CRTC)
FRAME
FRAME
VERTICAL DISPLAYED
VERTICAL
BLANKING
DISPLAY
ENABLE
VERTICAL
BLANKING
STATUS
BIT
~
~:~J~T~R
IL-____"~O·_·_=~D~IS~P_L_A_Y_A_C~T_IV_E____~
BITS)
SWITCHES STATE AT
END OF LAST DISPLAYED
SCAN LINE.
Figure 1O.
"'" = VERTICAL
BLANKING
ACTIVE
Operation of Vertical Blanking Status Big
2·110
CRT Controller (CRTC)
R6545-1
CCLK
\
CRT DISPLAY
ADDR~SSES
:
NON·DlSPLAY
'---t---i--....;.I--Ir----.....U . - - - - - - . . . I
:
I
I
I
'I r-~~--~!_ ... I~:
I.
:~3~
~~:~~S
I
I
I
I
I
UPSTB
II
I
DISPLAY'
DI$PLAY
ENABLE
I
:
1,\\\\\\\\\\\\LrrI
n ""--4r-------------------------------------
-----------------,I---J
I
I
I
I
Figure 11. Retrace Update Timing
CCLK
,.
,~{
,,
(NO DELAY)
{
~, {
(WrrH DELAY)
~~,
(NO DELAY)
ENABLE
POSFTIVE
EDGE
(WITH DELAY)
(NO DELAY)
ENABLE
NEGATIVE
EDGE
CRT DISPLAY ADDRESSES
I
(WrrH DELAY)
Figure 12. Cursor and Display Enable Skew
2·111
R6545-1
CRT Controller (CRTC)
WRITE TIMING CHARACTERISTICS
(V cc
= 5.0V
± 5%, T A
= T L to T H,
unless otherwise noted)
R6545-1
Symbol
Characteristic
Min.
!CYC
CyCle' Time
1.0
Ic
2 Pulse Width
440
IACW
Address Set-Up Time
180
tCAH
Address Hold Time
!wcw
R/W Set-Up Time
tCWH
R/W Hold Time
tDew'
Data Bus' Set-Up Time'
tHw
(tA and tF
-
0
,
180
Min.
Max.
Unit
0.5
-
200
-
ns
90
-
ns
0
-
ns
90
-
p,s
ns
265
-
100
-
ns
10
-
10
-
ns
0
Data Bus Hold Time
R6545A-1
Max.
0
ns
= 101030 ns)
READ TIMtNG CHARACTE RISTICS
(V cc = 5.0V ± 5%, T A = T L to T H, unless otherwise noted)
R6545-1
Symbol
Min.
R6545A-1
Max.
Unit
ICYC
Cycle Time
1.0
-
0.5
-
p,s
tc
2 Pulse Widlh
440
-
200
-
ns
IACR
Address Se!'Up Time
180
-
90
-
ns
ICAR
Address Hold Time
0
-
0
ns
IWCA
R/W Sel-Up Time
180
-
90
-
ICDR
Read Access Time (Valid Dala)
-
340
-
150
ns
IHR
Read Hold Time
10
-
10
-
ns
ICDA
Dala Bus Active Time (Invalid Dala)
40
-
40
-
ns
(IR and IF
Characteristic
Max.
Min.
ns
= 101030 ns)
READ TIMING WAVEFORMS
WRITE TIMING WAVEFORMS
CS,
RS
R/W,
DATA BUS
2-112
CRT Controller (CRIC)
R6546"1
MEMORY AND VIDEO INTERFACE CHARACTERISTICS
(Vcc = 5.0V ± 5%, TA = T L to T H, unleSll,otherwise not~d)
R6545-:~
Symbol
Characteristic
R6545A-1
Mali. '
Min.
U,,1t
MaX.
Min.
tCCY
Character Clock Cycle Time
0.40
-
0.40
-
!,-S
tCCH
Character Clock PUlse Width
200
-
200
-
ns
(X)tMAO
MAO-MAI3 Propagation Delay
-
300
(X)tRAO
RAO-RM Propagation Delay
-
. . 300
(X)tOTD
DISPLAY ENABLE Propagation ~!aY
-
450
-
450
-
(X)tHSO
HSYNC Propagation Delay
(X)tvso
VSYNC Propagation Delay
(X)lcoo
CURSOR Propagation DelaY
-.
450
-
ITAD
MAO-MA13 Swftchlng Delay
-
200
-
,
450
300
ris
300
.. ns
450
ns
450
ns
450
ns
450
ns
200
ns
Note:
I .. IF = 20 ns (m~).
.,
TRANSPARENT ADDRESSING
WAVEFORMS (cf>1/cf>2 INTERLEAVING)
SYSTEM TIMING WAVEFORMS
--.J
Icev'
, FIccH:::!
CCLK~
,
j;x
OUTPUTS
(SEE TABLE)
~
.,---"'-_ __
LIGHT PEN STROBE TIMING CHARACTERISTICS
R6545-1
Symbol
Min.
Characteristic
tLPH .
LPEN· Hold Time
150
t LP1
LPEN Selup Time
20
ILP2
CCLJ( 10 LPEN Delay
0
Max.
Min.
-
150
-
20
0
Note:
t .. IF =20 ns (max)
LIGHT PEN STROBE TIMING WAVEFORMS
JX,-___
MAG-MA13 _ _ _n_'_ _
n+_1_ _J
X
11+2'·
'X,-__
NOTE: "Safe" time position for LPEN posltlveeclge to cause
addrass n+2 to load Into Light Pe,n Register.
Iu>z and V1 are time positions causing uncertain' results.
2-113
.,
R6545A-1
Max.
-
Unit
ns
ns
ns
II
CRT Controller (CRTC)
R6545-1
ABSOLUTE MAXIMUM RATINGS*
Symbol
Value
Unit
Vee
-0.3 to +7.0
Vde
Input Voltage
VIN
-0.3 to +7:0
Operating Temperature Range
COmmercial
Industrial
TA
Storage Temperature
TSTG
Rating,
,"
Supply Voltage, ,
*NOTE: Stresses above those listed under "Absolute' Maximum
Flatings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those, indicated' in the
operational sections of this specification is not implied, Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Vde
°C
Oto +70
-40 to +85
-55 to +150
DC CHARACTERISTICS (Vee
=
°C
5.0V ±5%, T A = T L to T H, unless otherwise noted)
Characteristic
Min
Symbol
Input Hig h Voltage
V IH
2.4
-0,3
Input Low Voltage
VIL
Input Leakage (f12, R/W, RES, CS, RS, LPEN, 'CCLK)
liN
-
Three-State Input Leakage (00-07)
(\lIN = 0.4't02.4Vj
I TS1
-
Max
Unit
Vee
Vde
0.4
Vde
2.5
!LAde
±10.0
,
OUtputHig/l Vpltage'
I LOAD = 2,05 !LAde (OO-D7)
I WAO = 100 ",Ade (all others)
-
2.4
VOH
..
",Ade
Vde
"
"
"
Output Low Voltage
I LOAO = 1.6 mAde
VOL
Power Dissipation
Po
Input Capacitance
,~2, R/W, RES,CS, RS,LPEN,'CCLK
00-07
CIN
-
Ouiput .Ca,pacitanee
COUT
-
-
0.4
','
TeST LOAD
Vcc
2.4K!l'
R,6545-1 PIN
c
r
R
R = tlK!lFOR 00-07
, '" 2,4K!l FOR ALL OTHei'l QUTPUTS
C 130 pF TOTAL FOR 00-D7
= 30 pF ALL OTHER OUTPUTS
=
2-~
14
Vde
900
mW
10.0,
12,5
pF
pF
10.0
pF
;
,.
CRT Controller (CRTC)
R6545-1
PACKAGE. DIMENSIONS
4O-PIN CERAMIC DIP
Jl
b;11
I·
•
.
~.
I
V1ts;i
F1
.
-lol--··
~~
Wi'111111111111111
JL
D
I
•
~~.
DIM
K
-Il-J
\-
L
---I
M
NIN
MAX
,
INctES',
MIN
MAX
A
50.29. 51.56
1.980' 2.030
B
14.73' 15.49
0.580
0.619
c
1,78
3.05
0.070
0.120
D
0.38
0.58
0.015
0.023
f
'.02
1.65
0..Q40
0.065
C
2.29
2.80 0.090
0.110
J
0.20
0.38
0.015
0.008
K
3.18
3.81
0.125
0.150
L
14.99
16.51
0.590
0.650
M
rt'
N
0.S8
10"
00.
1.78
0.020
100
0.070
.
4O-PIN PLASTIC DIP
IIILUMETEAS
[:::::::::::::::::::u
I · ...
A
I
cC =:J
L
J~.~
K_tM J--;--
"It
MAX
MIN
MAX
A
51'.28
52.32
2.040
2.060
•
13.72
'4.22
0.540
C
3.56
5.08
0.140
0.200
D
0.38
:0.5;
0.014
0.020
F
-.1.02
1.52 0.040
0.060
Q
H
2.54 BSC
I
0.560.
p.100 esc
1.65
2.16 0.0&5
J
0.20
0.30
0.008. 0.012
K
3.05
3.56
0.120
L
15.24 esc
MOO
..
r
T'
NO.5'
2-115
INCHES
DIM
"0"
1.02 0.020
0.085
0.140
esc
10"
0.040
II
R6551
'1'
Rockwell
R6551
ASYNCHRONOUS COMMUNICATIONS
INTERFACE ADAPTER (ACIA)
DESCRIPTION
FEATURES
The Rockwell R6551 Asynchronous Communications Interface
Adapter (AGIA) provides an easily implemented, program controlled interface betWeen a-bit microprocessor-based systems
and serial comml,lnication data sets-and modems.
•
•
•
•
Compatible with a-bit microprocessors
Full dupleX operation with buffered receiver and transmitter
Data set/modem control functions
Internal baud rate· generator with 15 programmable baud
rates (50 to 19,200)
• Program-selectable internally or externally controlled receiver
rate
• Programmable word lengths, number of stop bits, and parity
bit generation and detect ion
• Programmable interrupt control
The ACIA has an internal baud rate generator. This feature eliminates the need for multiPle component support circuits, a crystal
being the only other part required. The. Transmitter baud rate
can be selected under program control to be eithet 1 of 15 d_ifferent rates from 50 to 19,200 baud, or at 1/16 times an external
clock rate. The Receiver baud rate may be selected under program control to be either the Transmitter rate, or at 1116 times
the external clock rate. The ACIA; has programmable word
lengths of 5, 6,7, or 8 bits; even, odd, or no parity; 1, 1~, or
2 stopbits.
•
•
•
•
•
•
•
•
The ACtA is designed fQr maximum. programmed control from
the microprQgessor (MPU), to simplify hardware implementation. Three separate registers permit the MPU to easily select
t.he R6551's operating-mOdes and data checking parameters
and determine operational status.
Program reset
Program-selectable serial echo mode
Two chip selects
2 or 1 MHz operation
5,0 Vdc ± 5% supply requirements
28-pin plastic or ceramic DIP
Full TTL compatibility
Compatible with R6500, R6500r and R65COO microprocessors
The Command Register controls parity, receiver echo mode,
transmitter interrupt control, the state of the FITS line. receiver
interrupt control, and the state of the DTR line.
The Control Register controls the number of stop bits, word
length, receiver clock source, and baud rate.
VSS
CSO
The Status Register indicates the states of the IRQ, DSR, and
DCD lines, Transmitter and Receiver Data Registers, and
Overrun; Framing, and Parity Error conditions.
~
RE!
RxC
The Transmitter and Receiver Data Registers are used for temporary data storage by the ACIA Transmit and Receiver circuits.
XTLI
XTLO
RTS
CTS
TxD
OTR
RxD
RSO
RS1
ORDERING INFORMATION
Part No.: R6551 __ _
[
Temperature Range (T L to T H):
Blank = O"C to + 7QoC
- E = -40"C to +85°C
Frequency Range:
1
2
3
4
5
RIW
.2
iRa
D7
D6
6
7
8
21
9
[It ~J
10
11
12
13
14
D5
D4
D3
D2
18
DO '
DSR
OCD
VCC
1 = 1 MHz
2=2MHz
-Package:
C;" Ceramic
P = Plastic
Figure 1. R6551 ACIA Pin Configuration
Document No. 29651N90
2-116
Product Description Order No_ 284
Rev_ 2, March 1984
Asynchronous Communications Interface Adapter (ACIA)
R6551
T.D
DQ-D7
oeD
fRO
DSR
RM>
R.C
CSO
XTlI
ffi
XTLD
RSO
iffi'(
RS1
RTS
;2
R.D
RES
Figure 2.
ACIA Internal Organization
FUNCTIONAL DESCRIPTION
TIMING AND CONTROL
A block diagram of the ACIA is presented in Figure 2 followed
by a description of each functional element of the device.
The Timing and Control logic controls the timing of data transfers on the internal data bus and the registers, the Data Bus
Buffer, and the microprocessor data bus, and the hardware
reset features.
DATA BUS BUFFERS
Timing is controlled by the system 152 clock input. The chip will
perform data transfers to or from the microcomputer data bus
during the jif2 high period when selected.
The Data Bus Buffer interfaces the system data lines to the
internal data bus. The Data Bus Buffer is bi-directional. When
the RJIN line is high and the chip is selected, the Data Bus Buffer
passes the data from the system data lines to the ACIA internal
data bus. When the RJW line is low and the chip is selected, the
Data Bus Buffer writes the data from the internal data bus to the
system data bus.
All registers will be initialized by the Timing and Control Logic
when the Reset (RES) line goes low. See the individual register
description for the state of the registers following a hardware
reset.
INTERRUPT LOGIC
The Interrupt Logic will cause the IRQ line to the microprocessor
to go low when conditions are met that require the attention of
the microprocessor. The conditions which can cause an interrupt will set bit 7 and the appropriate bit of bits 3 through 6 in
the Status Register, if enabled. Bits 5 and 6 correspond to the
Data Carrier Detect (DCD) logic and the Data Set Ready (DSR)
logic. Bits 3 and 4 correspond to the Receiver Data Register full
and the Transmitter Data Register empty conditions. These conditions can cause an interrupt request if enabled by the Command Register.
TRANSMITTER AND RECEIVER DATA REGISTERS
These registers are used as temporary data storage for the
ACIA Transmit and Receive Circuits. Both the Transmitter and
Receiver are selected by a Register Select 0 (RSO) and Register
Select 1 (RS1) low condition. The Read/Write (RJIN) line determines which actually uses the internal data bus; the Transmitter
Data Register is write only and the Receiver Data Register is
read only.
Bit 0 is the first bit to be transmitted from the Transmitter Data
Register (least significant bit first). The higher order bits follow
in order. Unused bits in this register are "don't care".
1/0 CONTROL
The I/O Control Logic controls the selaction of internal registers
in preparation for a data transfer on the internal data bus and
the direction of the transfer to or from the register.
The Receiver Data Register holds the first received data bit in
bit 0 (least significant bit first). Unused high-order bits are "0".
Parity bits are not contained in the Receiver Data Register. They
are stripped off after being used for parity checking.
The registers are selected by the Receiver Select (RS1, RSO)
and Read/Write (RJIN) lines as described later in Table 1.
2-117
R6551
Asynchronous Communications Interface Adapter (ACIA)
STATUS REGISTER
Parity Error (Bit 0). Framing Error (Bit 1). and
Overrun (2)
The Status Register indicates the state of interrupt conditions
and other non-interrupt status lines. The interrupt conditions are
the Data Set Ready, Data Carrier Detect, Transmitter Data Register Empty and Receiver Data Register Full as reported in bits
6 through 3, respectively. If any of these bits are set, the Interrupt (IRQ) indicator (bit 7) is also set. Overrun, Framing Error,
and Parity Error are also reported (bits 2 throughQ respectively).
7
6
5
4
3
2
None of these bits causes a processor interrupt to occur, but
they are normally checked at the time the Receiver Data Register is read so that the validity of the data can be verified. These
bits are self clearing (Le., they are automatically cleared after
a read of the Receiver Data Register).
o
Receiver Data Register Full (Bit 3)
PE
Bit 7
Q
Interrupt (IRQ)
No interrupt
Interrupt has occurred
Bit 6
Q
Data Set Ready (DSR)
DSR low (ready)
~ high (not ready)
Bit 5
Q
Data Carrier Detect (DCD)
DCD low (detected)
l5Ci5 high (not detected)
Bit 4
Q
Transmitter Data Register Empty
Not empty
Empty
Bit 3
Q
Receiver Data Register Full
Not full
Full
Bit 2
Q
Overrun'
No overrun
Overrun has occurred
Bit 1
Q
Framing Error'
No framing error
Framing error detected
Bit 0
Parity Error'
No parity error
Parity error detected
0
This bit goes to a 1 when the ACIA transfers data from the
Receiver Shift Register to the Receiver Data Register, and goes
to a 0 (is cleared) when the processor reads the Receiver Data
Register.
Transmitter Data Register Empty (Bit 4)
This bit goes to a 1 when the ACIA transfers data from the
Transmitter Data Register to the Transmitter Shift Register, and
goes to a 0 (is cleared) when the processor writes new data
onto the Transmitter Data Register.
Data Carrier Detect (Bit 5) and Data Set Ready
(Bit 6)
These bits reflect the levels of the DCD and DSR inputs to the
ACIA. A Qindicates a low level (true condition) and a 1 indicates
a high level (false). Whene'!er either of these inputs change
state, an immediate processor interrupt (IRQ) occurs, unless bit
1 of the Command Register (IRD) is set to a 1 to disable IRQ.
When the interrupt occurs, the status bits indicate the levels of
the inputs immediately after the change of state occurred. Subsequent level changes will not affect the status bits until the
Status Register is interrogated by the processor. At that time,
another interrupt will immediately occur and the status bits
reflect the new input levels. These bits are not automatically
cleared (or reset) by an internal operation.
Interrupt (Bit 7)
* No interrupt occurs for these conditions
This bit goes to a 1 whenever an interrupt condition occurs and
g09S to a Q (is cleared) when the StaWs Register is read.
Reset Initialization
Hardware reset
Program reset
2-118
Asynchronous Communications Interface Adapter (ACIA)
R6551
CONTROL REGISTER
Selected Baud Rate (Bits 0, 1, 2,3)
The Control Register selects the desired baud rate, frequency
source, word length, and the number of stop bits.
These bits select the Transmitter baud rate, which can be at
'/,6 an external clock rate or one of 15 other rates controlled by
the internal baud rate generator.
If the Receiver clock uses the same baud rate as the transmitter,
then RxC becomes an output and can be used to slave other
circuits to the ACIA. Figure 3 shows the Transmitter and Receiver
layout.
Bit 7
0
1
1
. Stop Bit Number (SBN)
1 Stop bit
2 Stop bits
1V2 Stop bits
For WL = 5 and no parity
1 Stop bit
For WL = 8 and parity
Bits 6-5
..§.. ..§...
0
0
0
1
0
1
1
1
Bit 4
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Word Length (WL)
No. Bits
-87
6
5
...- - - - - - - - - - RxC
Receiver Clock Source (RCS)
External receiver clock
Baud rate
Bits 3-0
..2..
14-..--RxD
~
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
XTLI
XTLO --T'T""'"TT
Selected Baud Rate (SBR)
J... .Q. Baud
16x External CloCk
0
0
0
1
50
1
75
0
109.92
1
1
134.58
0
0
1
150
0
0
300
1
1
1
600
0
1200
0
1800
0
1
1
2400
0
1
1
3600
4800
0
0
1
7200
0
0
9600
1
19,200
Figure 3.
Receiver Clock Source (Bit 4)
This bit controls the clock source to the Receiver. A 0 causes
the Receiver to operate at a bau.d rate of '/,6 an E!xternal clock.
A 1 causes the Receiver to operate at the same baud rate as
is selected for the transmitter.
Word Length (Bits 5, 6)
Reset Initialization
These bits determine the word length to be used (5, 6, 7 or 8
bits).
7654321 0
I~I~I~I~I~I~I~I~I
Transmitter/Receiver Clock Circuits
Hardware reset (RES)
Stop Bit Number (Bit 7)
Program reset
This bit determines the number of stop bits used. A 0 always
indicates one stop bit. A 1 indicates 1V2 stop bits if the word
length is 5 with no parity selected, 1 stop bit if the word length
is 8 with parity selected, or 2 stop bits in all other configurations.
2-119
II
'Asynchronous Communications Interface Adapter (ACIA)
R6551
COMMAND REGISTER
Data Terminal Ready (Bit 0)
The Command Register controls specific modes and functions.
This bit enables all ,selected interrupts and controls the state of
the Data Terminal Ready (DTR) line. A 0 indicates the microcomputer system is not ready by setting the DTR line high. A
1 indicates the microcomputer system is ready by setting the
DTR line low.
Bits 7-6
2. .§..
o
0
1
1
0
o
.
BitS
0
Bit 4
o
1.
Receiver Interrupt Control (Bit 1)
Parity Mode Control (PMC)
This bit disables the Receiver from gMerating an interrupt when
set to a 1. The Receiver interrupt is enabled when this bit is set
to a 0 and Bit 0 is set to a 1.
Odd parity transmitted/received
Even parity transmitted/received
Mark parity bit transmitted
Parity check disabled
Space parity bit transmitted
Parity check disabled
Transmitter Interrupt Control (Bits 2, 3)
These bits control the state of tlie Ready to Send (RTS) line and
the Transmitter interrupt.
Parity Mode Enabled (PM E)
Parity mode, disabled
No parity bit generated
Parity check disabled .
Parity mode enabled
Receiver Echo Mode (Bit 4)
A 1 enables the Receiver Echo Mode and a 0 enables the
Receiver Echo Mode. When bit 4 is a 1., bits 2 and 3 must be
O. In the Receiver Echo, Mode, the -Transmitter returns each
tranSl)1ission received by the .Receiver delayed by one-half bit
time.
.
Receiver ,Echo Mode (REM)
Receiver nqrmal mode
ReCeiver echo mode bits 2 and 3'
Must be zero for receiver echo mode, RTS will
Parity Mode Enable (Bit 5)
be low.
Bits 3-2
3
This bit enables parity bit generation and checking. A 0 disables
parity bit generation bY the Transmitter and parity bit checking
by the Receiver. A 1 bit enables generation and checking of
parity bits.
Transmitter Interrupt Control (TIC)
2
'0 '0
o 1
o
1
Bit 1
o
1
Bit 0
o
RTS = High, transmit interrupt disabled
RTS = Low, transmit interrupt enabled
RTS = Low, transmit interrupt disabled
RTS = Low, transmit interrupt disabled
transmit break on TxD
Parity Mode Control (Bits 6, 7)
These bits determine the type of parity generated by the Transmitter, (even, odd, mark or space) and the type of parity check
done by the Receiver (even, odd, or no check).
Interrupt Request Disabled (IRD)
IRQ enabled '
IRQ disabled
Data Terminal Ready (DTR)
Data terminal nof ready (DTR high)
Data terminal ready (DTR low)
Reset Initialization
76543 2 1 0
I 0 10 I 0 10 I 0 10 10 I 0 I Hardware reset
- - - 0 0 0 0 0 .Program reset
(RES)
2-120
Asynchronous Communications Interface Adapter (ACIA)
R6551
INTERFACE SIGNALS
Interrupt Request (IRQ)
Figure 4 shows the ACIA interface signals associated with the
microprocessor and the modeni.
The IRQ pin is an interrupt output from the interrupt control logic.
It is an open drain output, permitting several devices to be connected to the common IRQ microprocessor input. Normally a
high level, IRQ goes low when an interrupt occurs.
Data Bus (00-07)
CTS
The eight data line (00-07) pins transfer data between the processor and the ACIA. These lines are bi-directional and are normally high-impedance except during Read cycles when the
ACIA is selected.
TxD
IRQ
DeD
RM
eso
DSR
eSl
Rxe
RSO
XTLI
RSl
XTLO
Chip Selects (CSO, CS1)
The two chip select inputs are normally connected to the processor address lines either directly or through decoders. The
ACIA is selected when CSO is high and CSI is low. When the
ACIA is selected, the internal registers are addressed in accordance with the register select lines (RSO, RS1).
~
DTR
RES
RTS
Register Selects (RSO, RS1)
The two register select lines are normally connected to the processor address lines to allow the processor to select the various
ACIA internal registers. Table 1 shows the internal register
select coding.
vee
RxD
VSS
Figure 4.
~
..
ACIA Interface Diagram
Table 1.
ACIA Register Selection
Register Operation
MICROPROCESSOR INTERFACE
Reset (RE§)
During system initialization a low on the RES input causes a
hardware reset to occur. Upon reset, the Command Register
and the Control Register are cleared (all bits set to 0). The
Status Register is cleared with the exception of the indications
of Data Set Read~d Data Carrier Detect, which are externally
controlled by the DSR and DCD lines, and the transmitter Empty
bit, which is set. RES must be held low for one ~2 clock cycle
for a reset to occur.
R/W = High
RSI
RSO
R/w = Low
L
L
Write Transmit Data
Register
Read Receiver
Data Register
L
H
Programmed Reset
(Data is "Don't
Care")
Read Status
Register
H
L
Write Command
Register
Read Command
Register
H
H
Write Control
Register
Read Control
Register
Input Clock ~2)
The input clock is the system ~2 clock and clocks all data transfers between the system microprocessor and the ACIA.
Only the Command and Control registers can both be read and
written. The programmed Reset operation does not cause any
data transfer, but is used to clear bits 4 through 0 in the Command register and bit 2 in the Status Register. The Control Register is unchanged by a programmed Reset. it should be noted
that the programmed Reset is slightly different from the hardware Reset (RES); refer to the register description.
Read/Write (RJW)
The R/W input, generated by the microprocessor controls the
direction of data transfers. A high on the R/W pin allows the
processor to read the data supplied by the ACIA, a low allows
a write to the ACIA.
2-121
2
Asynchronous Communications Interface Adapter (ACIA)
R6551
ACIA/MODEM INTERFACE
Clear to Send (CTS)
CrystalPins (XTLI, XTLO)
The CTS input pin conlrols the transmitter operation. The enable
state is with CTS loW. The transmitter is automatically disabled
.
if CTS is high.
These pins are normally directly connected to the external
crystal (1.8432 MHz) to derive the various baud rates. Alternatively, an externally generated clock can drive the XTLI pin,
in which case the XTLO pin must float. XTLI is the input pin for
the transmit clock.
Data Terminal Ready (DTR)
This output pin indicates the status of the ACIA to the modem.
A low on DTR indicates the ACIA is enabled, a high indicates
it is disabled. The processor controls this pin via bit 0 of the
Command Register.
Transmit qata(TxD)
The TxD output line transfers serial nonreturn-to-zero (NRZ)
data to the modem. The least significant bit (LSB) of the Transmit
Data Register is the first data bit transmitted and the rate of data
transmission is determined by the baud rate selected or under
control olan external clock. This selection is made by programming the Control Register.
.
Data Set Ready (DSR)
The DSR input pin indicates to the ACIA the status of the
modem. A low indicates. the "ready" state and a high, "notready."
Data Carrier
Receive Data (RxD)
The RxDinput line transfers serial NRZ data into the,ACIA from
the modem, LSB first. Thereceiver data rate is e.ither the programmed baud rate or under the control of an externally generated receiver clock. The selection is made by programming
the Control Register.
Receive Clock (RxC)
Continuous Data Transmit
In the normal operating mode, the interrupt request output (IRQ)
signals when the. ACIA is ready to accept the next data word to
be transmitted. This interrupt occurs at the beginning of the Start
Bit. When the processor reads the Status Register of the ACIA,
the interrupt is cleared.
Request to Send (RTS)
The RTS output pin controls the modem from the processor.
The state of the RTS pin is determined by the contents of the
Command Register.
CHAR#n
T,D
...'
The processor must then idEmtify that the Tracsmit Data Register is ready to be loaded and must then load it with the next
data word. This must occur before the end of the Stop Bit, otherwise a continuous "MARK" will be transmitted. Fig!Jre 5 shows
the continuous Data Transmit timing relationship.
CHAR#n+1
,/
."
(DCD)
TRANSMITTER AND RECEIVER .
OPERATION
The. Rxe is a bi-directidnal pin which is either the receiver 16x
clock input or the receiver 16x clock output: The latter mode
results if the internal baud rate generator is selected for receiver
data clocking.
/
Det~t
The DCD input pin indicates to the ACIA the status of the carrierdetect output of the modem. A low indicates that the modem
carrier signal is present and a high, that it is riot
CHAR#n+2
I
,/
I
.'
CHAR#n+3
,/
I
,
lS""5"GJ ~ ~ 5E]s.opIS""5"GJ ~ ~ rns,opls·. ·ffi ~ ~rnSto+.{80Fr ~ [ilis.o{
I
I
I
I
I
I
..""~. /
INTERRUPT
(TRANSMIT DATA
'REGISTER EMPTY)
Lllt
r '
/LJl]
\ ~ ~ '~ ."~: '
PROCESSOR READS STATUS
REGiStER CAUSES
TO CLEAR'
IN THIS TIME
INTERVAL: OTHERWISE.
CONTINUOUS "MARK"
IS TRANSMITTED
i"RO
Figure 5.
Continuous Data Transmit
2-122
t
I
LJI]
L
R6551
Asynchronous Communications Interface Adapter (ACIA)
Continuous Data Receive
to
read the data word before the next interrupt, otherwise the
Overrun cdnditiono~curs. Figure 6 shows the continuous Data
Receive Timing Relationship.
Similar
the Continuous Data Transmit case, the nOrmal
operation of this mode is to assert IRQ when the ACIA has
received a full data word. This occurs at about 9/'6 point through
the Stop Bit. The processor must read the Status Register and
.---------------C-H-A-R-#-n------------------C-H-A-R-#-,-'.-,------------------C-H-A-R-#-n-.-2-----------------C~'H-A-R~#-n-.-3--~------,
,"
I
I "
/
RxD
"-. /
",
! "
"
"-. /
"
' , ' ,
':
c
,"-./'
,
.
lStart5"EJ ~ ~ hlJSto+t.~GJ"8l~ ~ [gjs,~pls..rtG"EJ: ]SE]s,opls''''5"EJ ~ ~ GEJs,opL
'
"
.•..
" ' " .,,,.;
PROCESSOR
INTERRUPT OCCURS
"
) '-'\
'
I
I
IlJn .
~
"
,
,,'
ABOUT 9/16 I N T O .
~:::-T~~v~I~RUN.
PROCESSOR R,EADS ~TU$
AND FRAMING ERROR
'
I ·
I
Lnr
,
,
'
'
'
I
I
I
I
L
Lll1
,
-
PROCESsOR MUST READ
RECEIVER DATA IN tHIS
TIME INTERVAL: OTttERWISE,
OVERRUN OCCURS
~~~I~:!=. CAUSES IRQ
ALSO. UPDATED
Figure 6,.
Continuous Data Receive
Transmit Data Register Not Loaded by Processor
When the processor finally loads new data, a Start Bit immediately occurs, the data word transmission is started, and another
interrupt is initiated, signaling for (he' next data word. Figure 7
shows the timing relationship for this mode of operation.
Iftheprocessor is unable to load the Transmit Data Register in
the allocated time, then the TxD line goes to the "MARK" condition until the data is loaded. IRQ interrupts continue to occur
at the same rate as previously. except nodala is transmitted.
CONTINUOUS '~MARK"
CHAR#n
CHAR#n+2
C..,AR#n+-'
I
/
TxD
Rs.
....--.---.......;"-.:,----- ----..,/
"-. /
rtGF1l~ ]~EJStOpl'
. -ISt"t'rn~~5ESto'ISt
I'
'I_CHA~~~TER
LJ1],
1
~~i::~~~
~
-I
I
ILITJ--
".',,~/ " '
FOR DATA
REGISTER
INTERRUPTS
CONTINUe AT
EMPTY
CHARACTER RATE,
EVEN THOUGH
PROCESSOR
REAOS
STATUS
REGISTER
NO DATA IS
TRANSMITTED
\
WHEN p~OCeSSOR FINALlV LOADS
NEW bATA, TRANSMISSION STARTS
IMMEOIATEL V ANO INTERRUPT
OCCURS, INDICATING TRANSMIT
DATA REGISTER EMPTY
Figure 7.
Transmit Data Register Not Loaded by Processor
2-123
I
. t5lSl ~~~
'fI',
'
Asynchronous Communications Interface Adapter (ACIA)
R6551
Effect of CTS on Transmitter
indicates that the Transmitter Data Register is not empty and
IRQ is not asserted. CTS is a transmit control line only, and has
no effect on the ACI.A Receiver Operation. Figure 8 shows. the
timing relationship ·forthis rnode of operation.
CIS is tl19Clear-to-Send signal generated bY.ihe rnodem. It is
norrnally lo~ (true state) but rnay go high in the event of some
modem problems. When this occurs, ,!heTxD line goes to the
"MARK" condition after the entire last character (including parity
and stop bit) have been transmitted. Bit 4 in the Status Register
CHAR#n+l
I
CHAR#n
.
CONTINUOUS "MARK"
"./
h~ISt.rtGEJ~~-
I
.L-.L...,..&.......-+--.&0...0.....1.---'-!
------------------------;~
~~~-----------------------------~---~----,S-N-~~TASSERTED
NOT CLEAR-TO-SEND
AGAIN UNTIL ~
GOES lOW
ClEAR.TO·~END
t
'm
GOES HIGH••
INDICATING ",OOE",
.
IS NOT READY TO
RECEi1IE DATA. TxO
GOES TO ""'ARK" CONDITION
j"A~EA !GQMPLET': CHARACTER
I~ TR~NSMITT£O.
Figure 8.
Effect of CTS on Transmitter
Effect of Overrun on Receiver
ff the. processor does not read the Rece,iver data Register in the
allocated time, then, -.yhen the following interrupt occurs, the
new data word is not transferred to the Receiver Data Register,
but the Overrun status bit is set. Thus, the Data Regis,ter will
contain the. last valid
INPUT
PORT
WPITS
DRIVE
INTERFACE
CONTROL
FLTITRKO
..
VCC
GND
WE
PSO, PSI
III
CLK
VCO
~
..
....
OUTPUT
PORT
LCT/DIR
FRlSTP
--
RW/SEEK
HDL
HD
USC
US1
MFM
'-
Figure 2.
DDFDe Block Diagram
2-139
II
,
R6565
Double-Density Floppy Disk Controller (DDFDC)
The relationship between the statusJdataregistars and the
and. RS signals is shown below.
RS
R/W
Function
0
0
1
0
1
1
0
Read Main Status Register
Illegal
Read from Data Register
Write into Data Register
1
o = Low, 1 = High
RiW
MSR
3 D3B
-Floppy Disk Drive (FDD) 3 Busy.
o FDO 3 is not busy, DDFDC will accept read or write
command.
FDD 3 is busy, DDFDC will not accept read .or write
command.
MSR
-FOD 2 Busy.
2 02B
o FDD 2 is not busy, DOFOC will accept read or write
command.
FOD 2 is busy, DDFDC will not accept read or write
command.
..
Table 1 shows each of the status registers used by the DOFOC
and each bit assignment within the individual registers. Table 2
defines the symbols used throughout the command definitions.
Each register bit symbol· is defined in the register descriptions
that follow Table 2.
MSR
1 01B
-FDD 1 Busy.
.
o FDD 1 is not busy, DDFDC will accept read or. write
command.
FDD 1 is busy, DDFDC will not accept read or write
command.
REGISTER DEFINITIONS
MSR
o
o
Main Status Reglster~. (MSR)
o
D1B
DOB
Status Register 0 (STO)
The Main Status Register (MSR) contains the status information
of the OOFOC, and must be read by the processor before each
byte is written to, or read from, the Data Register during the .command or result phase. MSR reads are not required during the
execution phase. The Data Input/Output (010) and Request for
Master (ROM) bits in the MSR indicate when data is ready and
in which direction data will be transferred on the data bus. The
maximum time between the last Rm during command or result
phases and the 010 and ROM getting set or reset is 12 JLS. For
this reason, every time the MSR is read the processor should wait
12 JLS. The maximum time trom the end of the last read in the
result phase to when bit 4 (OOFOC Busy) goes low is also 12 JLS.
7
6
5
SE
4
EC
3
NR
2
1
I 0
I usa
US
HD
US1
The Status Register 0 (STO) as well as the other status registers
(ST1-ST3), are available only during the result phase, and may
be read only after completing a command. The particular command executed determines which status registers are used and
may be read.
5TO
7 6
MSR
7 ROM -Request for Master,
o Data Register is not ready.
Data Register is ready.
o
0
o
1
o
MSR
6 010
-Data Input/Output.
o Data transfer is from system to the Data Register.
Data transfer is from Data Register to the system.
IC
-Interrupt Code.
Normal Termination (NT). Command was properly executed and completed.
Abnormal Termination (AT). Command execution was
started, but was not successfully completed.
Invalid Command (IC). Received command was invalid.
Abnormal Termination (AT). The Ready (RDY) signal
from the FDD changed state during command
execution.
STO
5 5E
-Seek End.
o Seek command is not completed.
Seek command completed by DOFDC.
MSR
o
I
IC
The 010 and ROM timing chart is shown in Figure 3.
§
DOB
-FOO 0 Busy.
FDD 0 is not busy, DDFOC will accept read or write
command.
FDD Ois bUSy, DDFDG will not accept read or write
command.
EXM
-Execution Mode, (Non-OMA mode only).
Execution phase ended, result phase begun.
Execution phase started.
STO
4 EC
-'Equipment Check.
o No error.
Either a fault signal is received from the FOD or the track
osignal failed to occur after 256 step pulses (Recalibrate
Command).
MSR
4 CB
-Controller (DDFDC) Busy.
o
DDFDC is not busy, will accept a command.
OOFDC is busy, will not accept a command.
2-140
Double-Density Floppy Disk Controller (DDFDC)
R6565
Table 1. DDFDC Status Register Bit Assignments
Bit Number
Main Status Register (MSR)
7
6
5
4
3
2
1
0
ROM
010
EXM
CB
D3B
D2B
D1B
DOB
SE
EC
NR
HD
IC
Status Register 0 (STO)
US
US1
USO
MA
Status Register 1 (ST1)
EN
0
DE
OR
0
NO
NW
Status Register 2 (ST2)
0
CM
DO
WT
SH
SN
BT
MD
Status Register 3 (ST3)
FLT
WP
ROY
TRKO
TS
HD
US1
USO
Table 2. Command Symbol Description
Description
Name
Symbol
0
Data
The data pattern which is going to be written into a sector.
00-07
Data Bus
8-bit data bus. where DO is the least significant data line and 07 is the most significant data line.
DTL
Data Length
When N is defined as 00. DTL is the number of data bytes to read from or write into the sector.
EaT
End of Track
The final sector number on a track. During read or write operation. the DDFDC stopa data transfer
after reading from or writing to the sector equal to EaT.
GPL
Gap Length
The length of Gap 3. During readlwrite commands this value determines the number of bytes that the
VCO will stay low after two CRC bytes. During the Format a Track command it determines the size of
Gap 3.
as specified in 10 field.
H
Head Address
Head number 0 or 1,
HD (H)
Head
A selected head number 0 or 1 which controls the polarity of pin 27. (H
HLT
Head Load Time
The head load time in the FDD (2 to 254 ms in 2 ms increments).
HUT
Head Unload Time
The head unload time after a read or write operation has occurred (16 to 240 ms in 16 ms increments).
MF
FM or MFM Mode
When MF = 0, FM mod'e Is selected; and when MF
MT
Multi·Track
When MT = 1, a multi-track oPeration is to be performed. After finishing a readlwrite operation on side
0, the DDFDC will automatically start searching for sector 1 on side 1.
= HD in all command words).
= 1, MFM mode is selected.
N
Bytes/Sector
The number of data bytes written in a sector.
NO
Non·DMA Mode
Wheri NO = 1, operation is in the Non-DMA mode; Vlhen NO = 0, operation is in the DMA mode.
NTN
New Track Number
A new track number, which will be reached
PTN
Present Track Number'
The track number at the completion of Sense Interrupt Status command. Present head poSition.
R
Record (Sector)
The sector number to be read or written.
RS
Register Select
Controls selection"of Main Status Register (RS = low) or Data Register (RS = high).
RIW
Read~ritlil
Either read (R) or write 0N) signal.
ST
Sectors/Traek
The number of sectors per track,.
as a result of the Seek command. Desired head position.
SK
Skip
Skip Deleted Data Address Mark.
SRT
Step Rate Time
The stepping rate for the FDD (1 to 16 msin 1 ms increments). Stepping rate applies to all drives
(F= 1 ms, E = 2 ms, etc.)
STO
ST1
ST2
ST3
Status
Status
Status
Status
STP
Sector Test Process
01, the data in contiguous sectors is compared byte by byte with data
During a Scan command, if STP
sent from the processor (or DMA controller); and if STP = 02, then alternate sectors are read and
compared.
T
Track Number
The current/selected track number of the medium (0-255).
USO,US1
Unit Select
A selected drive number (0-3).
0
1
2
3
Four registers which store the status information after a command has been executed. This information
is available during the result phase after command execution. These registers should not be confused
with the Main Status Register (selected by RS
low). STO-ST3 may be read only after a command has
been executed and contain information relevant to that particular command.
=
=
2·141
II
Double~Density
R6565·
STO
3 NR
-Not Ready.
FDD is ready.
FDD is not ready at issue of read or write command. If
a read or write command is issued to side 1 of a singlesided drive, this bit is also set.
ST1
STO
2 HD
-Head Address. (At Interrupt).
Head Select O.
Head Select 1.
ST1
1
o
o
1
-Missing Address Mark.
No error.
2 possible errors.
o
1. DDFDC cannot detect the ID Address Mark after
encountering the index hole twice.
STO
1 0
o
1
o
US
FDD
FDD
FDD
FDD
-Not Writable.
NW
No error.
DDFDC. detected a write protect signal from FDD during
exec~tion of Write Data, Write Deleted Data or Format
a Track commands.
Q MA
a
o0
Floppy Disk Controller (DDFDC)
-Unit Select. (At Interrupt).
0 selected.
2. DDFDC cannot detect the Data Address Mark or
1 selected.
2 selected.
3 selected.
Deleted Data Address Mark. The MD (Missing Address
Mark in Data field) of Status Register 2 is also set.
Status Register 1 (ST1)
6
5
4
3
2
o
DE
OR
o
ND
Status Register· 2 (ST2)
o
NW
MA
7
6
5
4
3
2
o
eM
DD
WT
SH
SN
o
BT
MD
ST1
7
o
EN
-End qf Track.
No error.
DDFDC attempted to access
sector of a track.
. . .
last
ST2
a sector beyond the
7
ST2
ST1
~
~
-Not Used. Always Zero.
o
- 1
ST1
~
o
-Not Used. Always Zero.
DE
-Data Error.
No error.
DDFDC detected a CRC error in ID field or the Data field.
eM
-Control Mark.
No error.
DDFDC encountered a sector which contained a Deleted
Data Address Mark during execution of a Read Data,
Read a Track, or Scan command, or which contained a
Data Address Mark during execution of a Read Deleted
. Data command.
ST1
4
o
ST1
!
ST2
OR
-Over Run.
No error.
DDFDC was not serviced by the system during data
transfers, within a predetermined time interval.
. -Not Used.
5
a
1
ST2
4 WT
-Wrong Track.
o No error.
Contents of T on the disk is different from that stored in
IDR. Bit is related to NO (Bit 2) of Status Register 1.
Always Zero.
ST1
g
o
DO
-Data Error In Data Field.
No error.
DDFDC detected a CRC error in the Data field.
NO
-No Data.
No error.
3 possible errors.
ST2
!
1. DDFDC cannot find sector specified inlD Register
during execution of Read Data, Write Deieted Data or
Scan commands.
o
1
SH
"":Scan Equal Hit.
No "equal" condition during a scan command.
"Equal" condition satisfied during a scan command.
ST2
2. DDFDC cannot read ID field without an error during
Read ID command.
g
o
3. DDFDC cannot find starting sector during execution
of Read a Track command.
2-142
SN
-Scan Not Satisfied.
No error.
DDFDC cannot find a sector on the track which meets
the scan command condition.
Rises
Double-Density Flop,?y D,isk Controlltitr (DDFDC1
COMMAND SEqUENCE
','\'
ST2"
1 BT
-BadTrack.,"
o
No error.
1
Contents of T on the disk is different from that stOred In "
the lOR and T - FF. Bit is related to NO (Bit 2) of Status
,Register 1 . '
,
The OOFDC"is capable of performing 15differ,ant CQIIl~andS.
Each command is initiated by a multi4>yte transfer of data from
the SV$tem. AftElr, command ,execUtion, the r8$ulJ of the command
may bea multi:obytetransfer of data back to th$,system; BecauSE!
ST2
of this multi-byte, transfe,r of'i"nform,ation betwe,"en the ODFOC, and
the,system,
eachcornmand consists of three p!lases:
o
-Missing Add..... Malt( In Data Field.
'
OOF'DC cannot find a oata Address, Mark or Deleted Data
Address Malt( during a data read from" the disk;
MD
P~The
ONa error.
Command
1
required to pet10rm
DOFbc
rece~es
II'
all information
a partjcularoperatibn from the system;
Execution Phase-The DoFOC performs" the in~ructed
operation;
,
Status Register 3 (ST3)
Result Phase-After' comPletion of the operation; status and'
ather housekeeping Inforlnation
available to ttle syStem.'
are made
The bytes of data sent to the, OOFDC to form a corhmand",' and
read out of the, OOFDC in the ~esult phase, must occur in the
order shown for eachcOmmarld sequence. That Is, 'tti~cPminand
code byte must"be sent first followed by ihe Other bytes"in the
specified sequence; All command bytes must be wmten arid aU
reSult bytes must ~e read in lilach phase. Aftf3r the rl!st
of
data in the camm!lnd phase Is received IlYthe DOFDC,lhe execu.
tion phase staita. Similarly; when the last byte of data is
in the result phase, the command is ended and the OOFDCis
~ady to acx:ept a new command. AlXlmmand can b!J terminated '
bY assertiilg the DONE'~IOnal to the DOFOG; Th'is 'ensures that
the processOr can always {let theOOFOC's aitentiol1 even If the '
command·i~~,process. ha~s up
an ~normal m~~'~er:
:.~.
Status Registl!r 3 (SJ3) holds the results of the Sense ,~rive Status
command'.
'
,
ST3
7 FLT
-FauH.
Fault (FLT) signal from the FOO is low.
1
Fault (FLT) $Ignal from the FOO is high.
bYte
reacfout
a
ST3
!
o
1
WP
-WrH,a Protect.
Write Protect (wp)signal from the FOO is low.
Write Protect (Wp)signal from the FOO is high.
in
COMMAND DESCRIPTION
S13
5 RDY
-Ready.
Ready (ROY) signal from the ROD is low.
Ready (ROY) signal from the FOD is high.
a
READ DATA
A QOmmand set of ni!"e byi~ pi\lC8s th~ OOF~. intp tile Read,
Data mode. After th!J ,Read Data command hilS~nreceiv8d.
ttie OOFOG lOads th~ he~(ii it I~ uiilOl1ded), waits the, sj)Qcified,
Head Settling Time (defined ,in the Specify comrmD1d), then ~jr\s
reading 10 AddreSs Martls and 10 fields .from the disk. when the
current sector number (~) stored in the 10 Register (lOR) matches
the sector number read from the disk, the ODFDC transfers datil.
from the disk Data field to the data bus.
ST3
4 TAKO -Track O.
"0 "Track 0 (TRKO) signal from the FOD is low.
1
Track 0 (TRKO) signal is from the FDO is high.
ST3
3 TS
-TWo Side.
Two Side (TS) signal from the FOO is low.
1
Two Side (TS) signal from theFOO is high.
a
After completion of the readoparation frQrnthecurrentsector, "
the OOFOG incremenll!.the S8ct0rNumber (R) by one, and the'
data from the next sector is read at'l~ ,output to the data bus. Tllis
continuous read function is called a "Multl-S8ctor Read Operation." The Read command terminates after reading th~ last data '
byte from sector R when,R.- EOT'. STO bits 7 and 6 'are set to
o and 1, respectWely, and S:T1bit 7 (EN)is set to a 1.
ST3
2 HD
-Head Select.
Head, Select (HO) signal to the FOD is low.
1
Head' Select (HO) signal to the FOOis high.
a
ST3
1
o
1
S13
o
a
,
US1
.....Unit Select 1.
Unit Select 1 (US1) signal to the FOO is low.
Unit Select 1 (US1) signal to the FOO is /:1igh.
The'Read Data command can also be terminated by a lOw DONE
si\;lnal. OONE should be iSsliecjat,thesame time that the,i5ACK
for the last byte of data is sent Updn l"SCliIipt of DONE" the OOF;OC
stops outputting data 10 the data bus; but cOntinues to read data
from the current sector, checks CRC (Cyclic Redundancy Count)
bytes, and then at the end of that sector tE!Jmlnates.the Read Data
command lind sets bits ., and 6 in STO to O. The amount of data
usa
-Unit Select O.
Unit Select 0 (USO) signal to theFOD is low.
Unit Select Q (US1) signal to the FOO is high.
2-143
"
Double-Density Floppy Disk Controller (DDFDC)
,R6565
which can be handled with a single command, to the DDFDC
depends upon MT (Multi-Track), MF (MFM/FM), and N (Number
of Bytes/Sector) values. Table 3 shows the transfer capacity.
If the DDFDC reads a Deleted Data Address Mark from the disk,
and the Skip Deleted Data Address Mark bit in the first command
byte is not set (SK = 0), then the DDFDC reads all the data in
the sector, sets the COl1trol Mark (CM) flag in ST2 to a 1, and
terminates the, command. If SK = 1, the DDFDC skips the sector with the Deleted Data Address Mark and reads the next sector. The CRC bits in the deleted data field are not checked when
SK
1.
The multi-track function (MT) allows the DDFDC to read data from
both sides of thEfdisk. For a particular traci<, data is transferred
starting, at sector 1, 'side 0 and completed at sector l, side 1
(sector l = last sector on the side). This function pertains to only
one track (the same track) on each side of the disk.
=
During disk data transfers from the DDFDC to the system, the
DDFDC must be serviced by the system within 27 J1S in the FM
mode, and within 13 J1S in the MFM mode, otherwise the DDFDC
sets the Over Run (OR) flag in ST1 to a 1, sets bits 7 and 6 in
STO to 0 and 1, respectively, and terminates the command.
When i'{= 0 in command byte 6 (FM mqde),the Data length
(DTL) in command byte 9 defines the data length that the DDFDC
must treat as a sector. If DTl is smaller than the actual data
length in a sector, the data beyond the DTL is not sent to the
data bus. Tl:1e DDFDC reads (internally) the complete sector, performs the CRC check, and depending upon the manner of command termination, may perform a multi-sector Read operation.
When N is non-zero (MFM, mode), DTl haS no meaning and
should be set to FF.
If the processor terminates a read (or write), operation in the
DDFDC, then the 10 information in the result phase is dependent
upon· the state of the MT bit in the fir!!t command byte and the
End of Track (EOT) byte. Table 4 shows the values for Track
Number (T), Head Number (H), Sector Number (R), and Number
01 Data Bytes/Sector (N), when'the processor terminates the
command.
Atthe completion of the Read Data cQmmand, the head is not
unlOaded unti,1 the Head ,Unload Time (HUT) interval defined in
t,h,e SPecif{colT)mand has elapsed. The head settling time may
be aVoided betWeen subsequent reads if the processor issues
<;InothElr command before the he<;ld unloads. This time savings
Is consideral:Jle when diSk contents are copied from one drive to
another.
'
Command Phase:
If the DDFDC detects the Index Hole twice in succ,ession without
finding the right sector (indicated' in R), then the DDFDC sets the
No Data (NO) flag in Status Aegister t (ST1) to a 1, sets Status
Register 0 (STO) bits 7 and 6 to 0 and 1, respectively, and terminates the Read Data command.
RIW
BYTE
7
6
5
4
3
2
1
W
1
MT
MF
SK
0
0
1
1
0
2
X
X
X
X
X
HD
US1
usa
3
Track Numb.er (T)
After reading the 10 and Data fields in each sector, the DDFDC
checks the CRC bytes. If a read error is detected (incorrect CRe
in ID field), the DDFDC sets the Data Error (DE) flag in ST1 to
a 1, sets the Data Error in Data Fiel\! (DO) flag in 8T2 to a 1 if
a CRC error occurs in the pata field, ,$e1S bits 7 and 6 in STO
to.o and 1, respectively, and terminates the command.
Table 3_
4
Head Number (H)
5
Sector Number (R)
6
Number of Data Bytes per Sector (N)
7
End of Track (EOT)
8
Gap Length (GPL)
9
Data Length (DTL)
DDFDC Transfer Capacity
Multi-TraCk
(MT)
MFM/FM
(MF)
Bytes/Sector
(N)
0
0
0
1
00
01
(128) (26) = 3,328
(256) (26) = 6,656
1
1
0
1
00
01
(128) (52)
(256) (52)
0
0
0
1
01
02
(256) (15)
(512) (15) "
1
1
0
1
01
02
(256) (30) = 7,680
(512) (30) = 15,360
0
0
0
1
02
03
(512) (8)
(1024) (8)
1
1
0
1
02
03
(512) (16)
(1024) (16)
,-
Maximum Transfer Capacity
(Bytes/Sector) (Number of Sectors)
2-144
=
=
=
=
=
=
=
6,656
13,312
3,840
7,680
4,096
6,,192
8,192
16,384
Final Sector Read
from Disk
26 at Side 0
or 26 at Side 1
26 at Side 1
15 at Side 0
or 15 at Side 1
15 at Side 1
8 al Side 0
or 8 at Side 1
8 at Side 1
0
. R6565
Double.;Density Floppy DiskC6ntroller(DDFDC)
Table
Cor!Ima"" Phase 10
MUlti-
.. 0
Bus
1
. FleIIu\t Ph_ID
T-.ck
Number·
(T)
Number
(H)
sector
Number
(R)
No. of
Data Bytes
(N)
Head
0
Less than EaT
NC
NC
R + 1
NC
0
Equal to EaT
T.+1
NC
01
NC
NC
NC
R +1
NC
T + 1
NC
01
NC
.. Less than EaT
1
..
··DDFDC Command Termination Values
.Final Sector T~nsfe~
to/from Dam
HMeI
Number
(HD)
T!l!Ck
(MT)
4~
1
Equal to eaT
0
Less than EaT
NC
NC
0
Equal to EaT
NC
LSB
01
.NC
1
Lessman EaT
NC
NC
R + 1
NC
1
Equal to EaT
T + 1
LSB
01
NC
R
+1
II
Ne
Notes:
1. Ne·(No Change): The same Wlueas the one at the beginning of command execution.
2. LSB (Least Significant Bit): The least significant bit of H is complemented.
Result Phase"
R
1
Status Register 0 (STO)
2
Status Register 1 (Sn)
3
. Status Register 2 (ST2)
4
Track Number (I)
5
Head· Number (H)
6
Sector Number (R) .
7
N~mber
01. Dam Bytes
per Sector (N)
WRITE.· DATA
A cornman(! set of nine bytes placeS the DDFDC in the Write Data
l'f'Iode: fAfter the Write bata coiTlmand has been rElCeived the'
DDFOC loads the head lif. it Is unloaded). ~ thespecifiedHead·
SettlingTl.me (defined'in the Specify command), then· begins
reading IDfields from the disk. When the four bytes (T, H, R,N)
loaded during the command match the fOur bytes of the 10 field
from the disk; the DDFDC transfers data from the data bus to·
the disk Data field.
.
After writing data into the current sector, the DI;>FDC increlTl$nts
the sector number (R) by one, and writes into the Data field in
the next sector. The DDf'[)C cOntinues this multi_or writ~
operation until the last byte is written to sector R when R - EaT.
STO bits 7 arid 6 are set to 0 and 1; respectively, and 8T1 bit
7 (EN) is set to a 1.
.
The command can also be tenninated by a low on DONE. If
DONE is sent to tile DDFDC while Writing into the current sector,
then the remainder of the Data field is filled with 00 (zeros). In
this case, 810 bilS 7 and 6 are set to 0 and the command is
terminated.
.
The DDFDC reads the 10 field of each sector and checks the CRC
bytes. If the DDFDC detects a read error (incorrect CRC) in one
of the 10 fields, it terminates the Write Data command, sets the
DE flag' in 8T1 to a 1, and sets bits 7 and 6 in SiO to 0 and 1,
respectively.
.
The Write Data command operates in much the same manner'
as the .Read Data command. Reter to the Read Data command.
for the handling of the following items:
• Transfer Capac;ity
• End of Track (EN) flag'
• No Data (NO) flag
• Head Unload Time (HUl) interval
.IDinformatlonwh," the processor terminates command
(see Table 4 ) .
.
• Definition of ~ta Length (DTL) whenN = 0 a~ when N '" 0
,
.
I,
' , ; '
In the Write Data mOde, 'data tranStersfroin the d8tabus to the··
DDFOG must occur within 'ZT ~ In theFM mode, 8!ild wlt!'!in 13 /IS
in the MfM mode. If the time interval between d$l transfers is
longer than this; the.n the DDFOGte,rminateSthe Write Data command, _the OvetRon(OR) flllQin ST1to 1.• and sets bits
.
7 and 6' in STO te 0 and·l', respectively.
a:
cOmmand Phase:
RIW
BYTE
7
6
5
4
3
2
1
W
1
MT
MF
0
0
0
1
0
1
2
X
X
X'
x
X HD
US1
usa
3
Track Number (I) .
4
Head. Number (H)
5
6
"
,.
.
0
.'
SeGtor Nuinber .(R)
Number of
Date Bytes per Sector' (N)
7
En~, of Track (EOn;,..
,
8
Gap LenQlh {GPL). •
:
9
Date Length (DTL)
'
Double-Density Floppy Disk Controller (DDFD.C)
R656S
Result Phase:
R
,Command Phase:
1
Status Register 0 (STOj
RIW
2
Status. Register 1 (S:£.l)·
W'
3
Status Register 2 (sT2)
4
Track Number
en
Head Number (H)
6
Sector Number (R)
7
Number of Data Bytes per Seclor (N)
The Write Deleted Data command is the same as the Write.Data
command except a Deleted Data Address Mark is written at the
beginning of the Data field instead of the normal Data Address
Mark.
W
.'.
4
31
2
1
0
0
111
0
.0
2
X
X
X
X
XTHD
US1
3
Track Number (1)
Head Number (H)
Sector Number (R)
6
Number of Data Bytes per Sector (N)
7
End of Track (EOl)
8
Gap Length (GPL)
9
Data Length (DTL)
R
1
Status Register 0 (STO)
2
Status Register 1 (ST1)
3
Status Register 2 (ST2)
.,
.6
.5
4
3
2
1
0
4
Track Number (1)
MT
'MF
0
0
1
0
"0
1
5
Head Number (H)
2
X
X
X
X
X
HD
US1
usd
3
Track Number (1)
~n:E
•1
. 4 ,.
Head Numb9r (H)'
5
Secto~ Number (1'1)
6
Number of Data Bytes PElf Sector (N)
7
End of Track (EOl)
8
Gap Length (GPL)
9
Data Length (OTL)
1
Status Reljister'iHSTO)
~
SlIltus Regisler1 (ST1)
3
Status Register 2 (5T2)
4'
Track Nurriber (T)
5
Head Number (H)
.6
Sectcr Number (R)
7·
Number of Data Bytes per Sector(N)
usa
.'
Result Phase:
'.
"
6
Sector NUIllb8r (R)
7
Number of Data Bytes Pilr Sectcr (N)
READ A TRACK
The Read a Track command is similar to the Read Data command except that this is a continuous read operation wQere all
Data fields from each of the sectors on a track are read and'
transferred to the data bus. Immediately after encountering the
Index Hole, the-DDFDC starts reading the Dli;lta fields as conti,;uous bloc~. of data. This command terminates wilen the lJum~
ber of sectors' read is equal to EOT. Multi-track operations are
not allowed with,this command.
Result Phase"
R
5
SK
'5
WRITE DELETED DATA
RIW
6
MF
1.
4
5
Command Phase:
7
MT
BYTE
.
If th.e DDFOC finds an error in the 10 or Data CRe check bytes,
it continues to read data from the track. The DOFDC compares
the 10 information read from each sector with the value stored
in,the lOR, ar)d sets the NO flag in 8T1 to a 1 ifthere is no match.
If the DDFOe does not find an 10 Address Mark On the .disk after
it encounters the Index I-Iole for the s9CO!1d time it terminates the
command, sets the.Missing Address Mark (MA) flag in ST1 to
a 1, and sets bits 7 and 6 of 8TO to 0 and .1, respectively.
READ D(:LETED DATA
The Read Deleted Data command is the~ame ~s the Read Data
command except that if 8K .. 0 When the DDFDC detects a Data
Addresa Mark.at the beginning of a Data field, it 'reads all the
data in the sector and s~!S the eM flag in 8T2 to a 1, and then
terminates the command: If SK .. 1, then the DDFDC skips the
sector with the Data Addresa Mark and reads the next sector. '
2-146
RSS8S
Double-Density Floppy Disk Controller (ODFDC)
Command Phase:
BYTE
7
RIW
W
1
,
FORMAT A TRACK,
,8
5
0
MF
SK
X
X
3
2
0, 0
0
,
0
HD
US,
USO
4
2
X
3
Track Number (T)
4
Head Number (H)
5
Sector-Number (R)
X
x-
1
=
6
Num~r of Dala Byt~ per Sector (N)
7
End of Track (EOT)
·8
Gap length (GPL)
9
Data L.8ngth (DTL)
The six-byte Format a Track command formats an entire track.
After the Index Hole Is detected, data is written on the disk: Gaps,
Address Marks, 10 fields and Dilta fleIcIs; all are reccl'ded in either
the doubl&.denslty IBM System 34 format (MF - 1) or the single-
0
d,ensity IBM 3740 format (M, F 0). The partiCU, lar format written
is also controlled by the values of Number of Bytes/Sector (N),
SectorsITraCk (ST), Gap Length (GPL) and Dais Pattem (0) which
are supplied by the processor during the command phase. The
Data field is filled with the data pattern stored"in O.
The 10 field for each sector is supplied by the processor in
response to four data requests Per _ r issued,l>y the DDFDC.
The type of data request depends upon ·the Non-OMA flag (NO)
in the Specily command. In the PMA mode, (NO = 0), the OOFOe
asserts the OMA Request (TXRQ) output four times per sector.
In the Non-DMA mode (NO .. 1), the DOFDC asserts Interrupt
Request (IRQ) output four tirT!es per sector.
'Result Phase:
,
R
Status Register 0 (STO)
2
Status Register 1 (ST1)
3
Status Register 2 (ST2)
4
Track Number (T)
The processor must write one data byte in response to each
request, sending (In the consecutive order) the Track Number (T),
Head Number (H), Sector Number (R) and Number of BytesJ
Sector (N). This allows the' disk to be formatted with nonsequential sector numbers, if desired.
5
Head Number (H)
6
SectOr Number (R)
7
Number of Data Byt~ per Sector (N)
The processor must send new values for T, H, R, and N to the
DDFDC for ·each sector on the track. For sequential formatting
R Is Incremented by one after each sectOr Is ,formatted, thus; R
contains the total numbers of septQrs formatted when it is read
during the result phase. Thls inCrementing and formatting continues for the whole track until the .DOFoe, ~~ enccunte~ng
the Index Hole for the second time, terminates the command and
sets bits 7 and 6 in STOto O.
READID
The two-byte Read 10 command returns the p~ent pOsition of
the readlwrite head. The DOFDC obtains the value from the first
10 field it is able to read, sets bits 7 and 6 in srO to 0 and terminates the command.
If the Fault (FLT) signal is high from the FDO at the end of a write
operation, the pOFDC sets the Equlplrient Check (EC)~ag In STO
If no proper 10 Address Mark is found on the disk before the Index
Hole is enccuntered for the, seccnd time then the MiSSing Address
Mark (MA) flag in ST1 is 'set to ~ 1, and if no data is found then
the NDflag in ST1 isalsa set to a 1. Bits 7 and 6 in STO are
set to 0 and 1, res~~iYely and the command is terminated.
to a 1, sets bits 7 and of STO to ,0 and,1, reepectlvoly, "and terminates the command. Also, a low (ROY) signal at thE! beginning
of a command execut\Ol1phaSe causes bits 7 and 6 Of STO to
be set to o and 1, respectively.
During this command there is no data transfer between OOFOe
and the data bus except during the result phase.
Table 5 shows the relationship between N. ST, and GPL for
various di$k and sector sizes.
'
Command Phase:
BYTE
7
RIW
8
5
4
0
MF
0
0
,
0
,
,0
1
2
X
X
X
X
Jc:
AD
US1
USO
W
3
2
"~
a
Command Phase"
0
RIW
W
Result Phase:
R
"
Status Register 0 (S~O)
2
Status Register' (Sn)
3
Status Register 2 (ST2)
4
TraCk Number (T)
5
Head Number (Hi
6
Sector Number (R)
7
Number of Data Bytes per Seetor (N)
2-147
BYTE
2
,
7
8
5
4
3
0
MF
0
0
1
,
0
,
2
X
X
X
X X
HD
USl
USO, ,
3
Number of Bytes per Sector (N),
4
Sector$ per Track (ST)
5
Gap Length (GPL)
6
Data Patiern (D),
1
0
g'
,
R6565
Double-Density Floppy Disk Controller (DDFDC)
Table 5. Standard Floppy Disk Sector Size, Relationship
Sector SIze
Disk
Size
Mode
Bytes/Sector
128
256
512
1024
FM
S"
5V."
"
,
Command~
00
01
02
1A
OF
1B
2A
03
07
OE
1B
47
OS
OS
FFFF
OE
1B
36
54
IBM Disk 20
35
74
FF'
Ff!
FF
IBM Disk 20
08
OS
256
512
01
02
03
04
05
06
1A
OF
08
04
02
01
128
128
256
512
'1024,
2048
00
,00
01
02
12
10
256
256
01
01
02
~'
,
Format
Command1
04
512
1024
MFM3
CST)
2048
8~92
4096
Gap Length (GPL)4
AeadIWrIte '
4096
4096
FM
No. of
SectorslTi'acks
04
02
01
10114
2048
MFM3
No. of Data
8ytea1Sector
(N)
03
04
03
04
05
99
C8
C8
08
07
10
lS
04
02
01
08
OS
12
10
OS
04
02
01
46
OA
20
2A
80
OS
OS
Remarks
IBM Disk 1
IBM Disk 2
3A
SA
09
19
30
S7
FF
FF
OC
32
50
FO
Ff!
FF
Notes:
'1~SUgges\ed
values of GPL in R~ or Write C\lmll)and~-toavoid overlapping between Data field and 10 field of contiguous sections,
2. Suggested values of GPl in Format a Track cOmmand.
3. In MFM mOde the DDFDC cannot perform a readlwriteJforrnat operation wHh 128 bytes/sector (N = 00).
4. ValUes of ST and GPL are in h8xadecimal.
Result Phase:
R
1
Status Register 0 (STO)
2
' Status Register 1 (ST1)
3
Status Register 2 (ST2)
4
Track Number (1)'
5
Head Number (H)'
6
Sector Number (R)*
7
Number of Data Bytes per Sector (N)'
the sector number is incremented (R + STP - R), and the scan
operation is continUed. The scan operation continues until one
of the following events, occur: the conditions for scan ,are met
(equal, low or equal, or high or equal), the last sector on the track
is reached (EOT), or DONE is received.
If conditions for scan are met, the DDFDC sets the Scan Hit (SH)
flag in ST2 to a 1, and terminates the command. If the condi"
tions for scan are not met between the starting sectqr (as specified
by R) and the last sector on the track (EOT), then the DDFDC
sets the Scan Not Satisfied (S~n ST2 to a 1, and tenninates
the command. The receipt of DONE from the processor or DMA
controller during the scan operation will cause the DDFDC to complete the comparison of the particular byte which is in process,
and then to terminate the command. Table 6 shows the status
of bits SH and SN under various coMitions of scan.
, The 10 information has no meaning in this command.
!;CAN COMMANDS
The scan commands compare data read from the disk to data
supplied from the data bus. The DDFDC compares the data, and
loqks for a sector of data which meets ,the conditions of DFOo =
Deus, DFOo S Deus, or DFOo ;:: D~us (D = the data pattern in
hexadecimal). A magnitude comparison is perfprmed (FF =
largest number, 00 = smallest number). The hexadecimal byte
of FF either from the bus or from FDD can be used as a mask
byte because it always meets the condition of the compare. After
a whole sector of data is compared, if the conditions are not met,
If SK = 0 and the DDFDC encounters a Deleted Data Address
Mark on one of the sectors, it regards tliat sector as the last sector of the track, sets the Control Mark (CM) bit in ST2 to a 1 and
tenninates the command. If SK = 1, the DDFDC skips the sector with the Deleted Data Address Mark, sets the CM flag to a
1 in order to show that a Deleted Sector has been encountered,
and reads the next sector.
2-148
R6565
Double-Density Floppy Disk Controller (DDFDC)
Table 6.
Scan Status Codes
Status Register 2
Command
Bit 2 .. SN
Scan Equal
.0
I
I
.0
.0
.0
I
Scan Low or Equal
.0
.0
I
R
During a scan command data is supplied frem the data bus fer
comparison against the data read frem the disk. In .order to aveid
having the Over Run (OR) flag set in ST1 , data must be available
frem the data bus in less than 27 p.S (FM mede) .or 13 p.S (MFM
mede). If an OR .occurs, the DDFDC terminates the cemmand
and sets bits 7 and 6 .of STO to 0 and 1, respectively.
W
4
2
3
I
MT
MF
SK
I
a a
2
X
X
X
X
X
3
Track Number (1)
HD
Sector Number (R)
7
Number of Data Bytes per Sector (N)
BYTE
7
6
5
4
3
2
1
W
I
MT
MF
SK
I
I
a
a
I
2
X
X
X
X
X
HD
USI
USa
3
Track Number (1)
4
Head Number (H)
5
Sector Number (R)
Number of Data Bytes per Sector (N)
.0
I
8
Gap Length (GPL)
USI
US.o
9
Sector Test Process (STP)
6
Number of Data Bytes per Sector (N)
9
Head Number (H)
6
End of Track (EOT)
Sector Number (R)
Gap Length (GPL)
Track Number (1)
7
Head Number (H)
End of Track (EOT)
4
5
6
4
7
Status Register 2 (ST2)
0
1
5
8
Status Register I (STI)
3
RIW
Command Phase:
5
Status Register .0 (STa)
Command Phase:
SCAN EQUAL
6
I
2
SCAN LOW OR EQUAL
The follewing tables specify the cemmand bytes and describe
the result bytes for the three scan cemmands.
7
DFDD = Daus
DFDD > Daus
DFDD < Daus
Result Phase:
When either the STP secters are read (centigueus secters .. 01,
.or alternate secters .. 02) or MT (Multi-Track) is set, the last sector on the track must be read. Fer example, if STP = 02, MT
= 0, the secters are numbered sequentially 1 threugh 26, and
the scan command starts reading at secter 21. Secters 21, 23,
and 25 are read, then the next secter (26) is skipped and the Index
Hele is enceuntered before the EOT value .of 26 can be read.
This results in an abnermal terminatien .of the cemmand. If the
EOT had been set at 25 .or the scanning started at secter 20, then
the scan command weuld be cempleted in a nermal manner.
BYTE
*
.0
.0
I
R/W
DFDD = Daus
D FDO
Daus
D FDO = Daus
D FDo < Daus
DFDD > Daus
.0
.0
I
Scan High or Equal
Comments
= SH
Bit 3
Result Phase:
R
Sector Test Process (STP)
2-149
a (ST.o)
I
Status Register
2
Status Register .1 (STI)
3
Status Register 2 (ST2)
4
Track Number (1)
5
Head Number (H)
6
Sector Number (R)
7
Number of Data Bytes per Sector (N)
0
Double-Density Floppy Disk Controller (DDFDC)
R6565
During the command phase of the Seek operation the DDFDC
sets the Controller Busy, (CB) flag in the MSR to 1; but during
the execution phase the CB flag is set to 0 to indicate DDFDC
non-busy. While, the DDFDC is in the non:-bu!ly state, another
Seek command may be issued, and in this manner parallel seek
operations may be performed on all drives at' once.
SCAN HIGH OR EQUAL
Command Phase:
R/W
W
,
.,
6
5
MT
MF
SK
2
X
X
X
3
Track Number (T)
4.
Head Number (H)
5
Sector Number (R)
BYTE
4
3
2
, , ,
X
X
HD
1
0
0
,
US,
USO
6
Number of Data Bytes per Sector (N)
7
End of Track (EOT)
8
Gap Length (GPL)
9
Sector Test Process (STP)
No command other than Seek will be accepted while the DDFDC
is sending step pulses to any FDD. If a different command type
is attempted, the DDFDC will set bits 7 and 6 in STO to a 1 and
0, respectively, to indicate an invalid command.
If the FDD is in a not ready state at the beginning of the command execution phase or during the seek operation, then the
DDFDC sets the Not Ready (NR) flag in STO to a 1, sets STO
bits 7 and 6 to 0 and 1, respectjyely, and terminates the command ..
If the time to write the three bytes of the Seek cOmmand exceeds
150 p,S, the time between the first two step pulses may be shorter
than the Step Rate Tilne (SRT) defined by the Specify command
by as much as 1 ms.
Result Phase:
R
,
Status Register 0 (STO)
2
Status Register , (STl)
3
Status Register 2 (ST2)
,4
Track Number (T)
Command Phase:
RIW
BYTE 7
6
5
4
3
2
1
0
0
0
0
0
, , , ,
X
X
X
X
0
US,
usa
W
,
5
Head Number (H)
2
X
6
Sector Number (R)
3
New Track Number (N1N)
7
Number of Data Bytes per Sector (N)
Aesult Phase: None.
SEEK
The three-byte Seek command steps the FDD readlwrite head
from track to traCk. The DDFDC has two independent Present
Track Registers for each drive. They are cleared only by the
Recalibrate command. The DDFDC compares the Present Track
Number (PTN) which is the current head position with the New
Track Number (NTN), and if there Is a difference, performs the
following operation:
If PTN
RECALIBRATE
This two-byte command retracts the FDD readiwrite head to the
Track 0 position. The DDFDC clears the contents of the PTN
counters, and checks the status of the Track 0 Signal from the
FDD. As long as the Track 0 signal (TRKO) is low, the direction
signal (LCT/DIR) output remains low and step pulses are issued
on FA/STP. When TRKO goes high the DDFDC sets the Seek
End (SE) flag in STO to a 1 and terminates the command. If the
TRKO is still low after 256 step pulses have been issued, the
DDFDC sets Seek End (SE) and Equipment Check (EC) flags in
STO to 15, sets bits 7 and 6 of STO to 0 and 1, respectively, and
terminates the command.
< NTN: Sets
the direction output (LCT/DIR) high
and iSsues step pulses (FA/STP) to the FDD
to cause the readlwrite head to step in.
If PTN > NTN: Sets the direction output (LCT/DIR) low and
issues step pulses to the FDD to cause the
readlwrite head to step out.
The rate at which step pulses are issued is controlled bY,the Step
Rate Time (SRT) in the Specify command. After each step pulse
is issued, NTN is compared against PTN. When NTN = PTN,
then the Seek End (SE) flag in 8TO is set to a 1, bits 7 and 6
in STO are set to 0, and the command is terminated. At this point
DDFDC asserts IRQ.
The ability to do overlap Recalibrate commands to multiple FDDs
and the loss of the ROY signal, as described in the Seek command, also applies to the Recalibrate command.
Command Phase:
BYTE 7
RIW
The FDD Busy flag (bit 0-3) in the Main Status Register (MSR)
corresponding to the FDD performing the Seek operation is set
to a1.
W
After command termination, all FDD Busy bits set are cleared by
the Sense Interrupt Status command.
,
6
5
4
3
2
1
0
0
0
0
0
0
, , ,
2
X
X
X
X
X
0
US1
USO
Result Phase: None.
2-150
Double-Density Floppy Disk Controller (DDFDC)
R6S6S
SENSE INTERRUPT STATUS
SPECIFY
Interrupt Request (IRQ) is asserted by the DDFDC when any of
the following conditions occur:
The three-byte Specify command sets the initial values for each
of the three internal timers. The Head Unload TIme (HUl) defines
the time from the end of the execution phase of one of the
readlwrite commands to the head unload state. This timer is programmable from 16 to 240 ms in increments of 16 ms (1 = 16 ms,
2 = 32 mS, ... F = 240 ms).
1. Upon entering the result phase of:
a. Read Data command
b. Read a Track command
c. Read 10 command
d. Read Deleted Data command
e. Write Data command
f. Format a Track command
g. Write Deleted Data command
h. Scan commands
2. Ready (ROY) line from the FDD changes state
3. Seek or Recalibrate command termination
4. During execution phase in the Non-DMA mode
The.Step Rate Time (SAl) defines the time interval between adjacent step pulses. This timer is programmable from 1 to 16 ms in
increments of 1 ms (F == 1 ms, E == 2 ms, 0 = 3 ms, ... 0 == 16 ms.
The Head Load Time (HLl) defines the time between the Head
Load (HDL) signal going high and the. start of the readlwrite operation. This timer is programmable from 2 to 254 ms in increments
of 2 ms (01 = 2 ms, 02 = 4 ms, 03 = 6 ms, ... 7F = 254 ms).
The time intervals are a direct function of the clock (ClK on pin 19).
Times indicated above are for an 8 MHz clock. If the clock is
reduced to 4 MHz (mini-floppy application) then all time intervals
are increased by a factor of two.
IRQ caused by reasons 1 and 4 above ocqur during normal
command operations and are easily discernible by the processor.
During an execution phase in Non-DMA mode, bit 5 in the MSR
is set to 1. Upon entering result phase this bit is set to O. ReasOns
1 and 4 do not require the Sense Interrupt Status command. The
interrupt is cleared by reading or writing data to DDFDC. Interrupts caused by reasons 2 and 3 are identified with the aid of
the Sense Interrupt Status command. This command resets IRQ
and sets/resets bits 5, 6, and 7 of STO to identify the cause of
the interrupt. Table 7 defines the seek and interrupt codes.
The choice of DMA or Non-DMA operation is made by the NonDMA mode (NO) bit. When this bit = 1 the Non-DMA mode is
selected, and when NO = 0 the DMA mode is selected.
Command Phase:
Neither the Seek or Recalibrate command has a result phase.
Therefore, it is mandatory to use the Sense Interrupt Status command after these commands to effectively terminate them and
to verify where the head is positioned by checking the Present
Track Number (PTN).
RIW
BYTE
W
1
SRT HUT HLT NO -
Issuing a Sense Interrupt Status command without an interrupt
pending is treated as an invalid command.
7J6151 4 3 I 2 I 1 1 0
o 1 0 1 0 I 0 o 1 0 1 1 .1 1
2
SRT
3
HLT
HUT
Step Rate Time
Head Unload Time
Head Load Time
Non .oMA mode
Result Phase: None.
Command Phase:
Status Register 0 (STO)
Present Track Number (PTN)
Table 7.
STO Seek and Interrupt Code Definition for Sense Interrupt Status
Status Reglstsr 0 (STO) Bits
Seek End (SE)
Interrupt Code (Ie)
7
6
5
1
1
0
0
0
1
0
1
1
CsU811
ROY line changed state, either polarity
Normal termination of Seek or Recalibrate command
Abnormal termination of seek or Recslibrate ·command
2-151
I
NO
2
R6565
Double-Density Floppy Disk Controller (DDFDe)
SENSE DRIVE STATUS
During the result phase all bytes shown in the result phase must
be read by the processor. The Read Data command, for example,
has seven bytes of data in the result phase. All seven bytes must
be read to successfully complete the Read Data command. The
DDFDC will not accept a new command until all seven bytes have
been read. Other commands may require fewer bytes to be read
during the result phase.
This !1t\O-byte command obtains and reports the status of the FDDs.
Status Register 3 (ST3) is returned in the result phase and contains the drive status.
Command Phase:
a
RJW
BYTE
7
6
5
4
3
2
1
w
1
0
0
0
0
0
1
0
0
2
X
X
X
X
X
HD
US1
usa
INTERRUPT REQUEST MODE
During the execution phase, the MSR need not be read. The
receipt of each data byte from the FDD. is indicated by IRQ low
on pin 18. When the DDFDC is in Non-DMA mode, iRa is
asserted during the execution phase. When the DDFDC is in the
DMA mode, the IRQ is asserted at the result phase. The IRQ
signal is reset by a r!!ad (RiiJ high) or write (RiiJ low) of data
to the DDFDC. A further explanation of the IRQ signal is described
in the Sense Interrupt Status command on page 16. If the system
cannot handle interrupts fast enough (within 13 p.S fOr MFM mode
or 27 p.S for FM mode). it should poll bit 7 (RQM) in the MSR.
In this case, RQM in the MSR functions as an Interrupt REiquest
. (IRQ). If the ROM bit is not set, the Over Run (OR) flag in sri
will be set to.~t 1 and bits 7 and 6. of S10 will be set to a 0 and
.1,·respectively.
.
Result Phase:
I
R
I
Status Register 3 (Si3)
INVALID COMMAND
If an invalid command Q.e., a command not previously defined)
is received by the DDFDC, then .the DDFDC terminates the command after setting bits 7 and 6 of sro to 1 and O. respectively. The
DDf'DC does nOt generate an interrupt during this condition •. Bits
6 and 7 (DiD and RQM) in the MSR are both set to a 1 indicating
to the processor that the DDFDC is in the result phase and thlilt
sro must be read. A hex 80 in Sro indicates that an invalid command was received.
DMAMO,DE
When the DDFDC is in th" DMA mode (ND = 0 in the third command byte of the Specify command). TXRQ (DMA Request) is
asserted during the execution phase (ratherthan IRQ) to request
the transfer of a data byte between the data bus and the DDFDC ..
A Sense Interrupt Status command must be sent after a Seek or
Recalibrate interrupt, otherwise the DDFDC considers the next
command to be an invalid command.
During a read command, the DDFDC asserts TXRQ as each byte
of data is available to be read. The DMA controller responds to
this request with DACK low (DMA Acknowledge) and RiiJ high
(read). When DACK goes row the DMA Request is reset
(TXRQ low). After the execution phase has been completed
(DONE low or the EDT sector is read). IRQ is asserted to indicate
the start of the result phase. When the first byte of data is read
during the result phase, IRQ is reset high.
In some applications the user may wish to use this command as
a No-Op command, to place the DDFDC in a standby. or no opera·
tion state.
Command Phase:
RJW
w
I ~TE 17Invalid Codes
.6
o
During a write command, the DDFDC asserts TXRQ as each byte
of data is required. The DMA controller responds to this request
with DACK low (DMA Acknowledge) and RiW low (write).
When DACK goes low the DMA Request is reset (TXRQ lOW).
After the execution phase has been completed (DONE low or
the EDT sector is written), IRQ is asserted. This signals the beginning of the result phase. When the first byte of data is read during the result phase, the IRQ is reset high.
Result Phase:
I
R
I
Status Register 0 (STIl) = 80
PROCESSOR INTERFACE
FDD POLLING
During the command or result phases, the Main Status Register
(MSR) must be read by the processor before each byte of information is transferred to, or from, the DDFDC Data Register. After
each byte of data is written to, or read from. the Data Register,
the processor should wait 12 p.S before reading the MSR. Bits 6
and 7 in the MSR must be a 0 and 1, respectively, before each
command byte can be written to the DDFDC. During the result
phase, bits 6 and 7 of the MSR must both be 1s prior. to reading
each byte from the Data Register onto the data bus. Note that
this status reading of bits 6 and 7 of the MSR before each byte
transfer to and from the DDFDC is required in only the command
and result phases and not during the execution "hase.
After the Specify command has been received by the DDFDC,
the Unit Select lines (USO and US1) begin the polling mode.
Between commands (and between step pulses in the Seek Command) the DDFDC polls all the FDD's looking for a change in
the RDY line from any of the drives. If the RDY line changes state
(usually due to the door opening or closing) then the DDFDC
asserts IRQ. When Status Register 0 (STO) is read (after Sense
Interrupt Status command is issued). Not Ready (NR = 1) will
be indicated. The polling of the RDY line by the DDFDC occurs
continuously between commands, thus notifying the processor
which drives are on- or off-line. Each drive is polled every 1.024 ms
except during readlwrite commands.
2-152
R6565
Double-Density Floppy Disk Controller (DDFDC)
DATAIN/OUT
(DIO)
.
(MSR BIT 6)
REQUEST
FOR MASTER
(RQM)
(MSR BIT 7)
ENABLE (.2)
READI
WRITE
(RIW)
FROM DDFDC TO DATA BUS
FROMDATABUSTO~
,
,
,
,
,
1
1
'READV'
,
I
NOT
hJ
'
'"
,
I
: ill--'
--+--.J I,
""1
-lj--tl---+I-+,-II I
1 ,
,
1 ,
'
I, I
I I I I I I c Ic I
i LJ
1
1-1
1
I,
1
I
A
B
A
B
A
I D
D IBI A
NOTES
o
DATA REGISTER READY TO BE WRITTEN INTO
[!J DATA REGISTER NOT READY TO BE WRITTEN INTO
Figure 3,
[£J DATA REGISTER READY FOR NEXT DATA BYTE TO BE READ
~ DATA REGISTER NOT READY FOR NEXT DATA BYTE TO BE READ
DDFDC and System Data Transfer Timing
2·153
II
:u
G)
Ul
G»
Ul
A14A15
...."
~
~
...
REs
..
R/W
~I
~
,,Ittr... ~
iI
~
9
It
~
<
.....
....
_ROW
--- ~
yeo
PSG
MPU
PSI
WOA
~
MEllO"
eLK
WP/TS
F1.TItMD
l~
I
I
OSC
.....
FRlSTP
-
urr....
DOFDC
I
1
I
WfInE.
I
wei(
I :'KI
ClJ[
RWISEEK
IIDY
WE
lOX
HDL
HOSEL
IAQ
IRQ
USO
USI
RECOVERY
EJ-I: '
IIUX
---~
READ DATA
WRITE DATA
WAITE PROTECT
lWo-SIDE
FAULT
TRAc:K 0
FAU.,T RESET
".x ~
'-'-'- DIRECTION
~
STEP
LOWCUAFENT
READY
wAnE ENABLE
INDEX
. . . . LQAD
HEAD SELECT
uNIT SELECT 0
UNTSELECT 1
b
0
Ie
2:
CD
C•
..
CD
:s
::;:
'<
"1'1
0'
~
I~
-a...
(')
0
:s
CD
C
C
"1'1
C
Figure 4.
R6S6S DDFDC Interface to R6500
!!
RSSSS,
Double-Density Floppy. Disk Controller (DDFDC)
~_CLK_J___. _~_.2_._'_2~···.·_4_··
_1____
FigureS. Clock Tlmln!l
.2 ____
~
Rfii_~___r---~~~
00-07
(DATA OUT)
@1 . @t
------...4J
DATA VALID·.
--.,.....---------
Figure 6. Read Cycle Timing.
0
~0- ~0-
'2
RS
-"
C
0
I--
- -,
if
0
RS VALID
~
~
'I(':
~
@- @)
Figure 7. Write Cycle Timing
2-155
~
DOOc
11
Double-Density Floppy Disk Controller (DDFDC)
R6565
TXRQ
Figure 8.DMA Operation Timing
WRITE ENABLE
(WE)
PRESHIFT 0 OR 1
(PSO, PS1)
WRITE DATA
(WDA)
Figure 9. .FDD Write Operation Timing
READ DATA
(ROD)
READ DATA WINDOW
(ROY/)
-~_-_ _---J~-----_-Jl'1t,--
NOTE:
EITHER POLARITY DATA WINDOW IS VALID
Figure 10.
FDD Read Operation Timing
2-156
Double-Density Fioppy Disk Controller· (DDfDC)
R656S
~,""
=?j----------...., "------
II
SEEK
(RW/SEEK)
DIRECTION
(LCTJDIR)
STEP
(FR/STP) _ _ _ _ _ _
Figure 11.
0
FAULT RESET
(FR) _ _ _
~
Seek Operation Timing
INDEX
......_ __
(lOX)
@
Figure 13.
Figure 12. ..Fault Reset Timing
Index Timing
DO
.N
. .E
..
-.
U.
.-1~@
.
Figure 15.
Figure 14. DONE Timing
INPUT/OUT
..
CLOCK
TEST POINT
.;{
---f\ O.BV
O.BV
3.0V==X::::lo:::X=-
1"-.-
INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" AND 0.45 V FOR
A LOGIC "0:' riMING MEASUREMENTS ARE MADE AT 2.0V FOR
A LOGIC "1" AND O.BV FOR A LOGIC "0:'
Figure 16.
TEST POINT
f
2.4V---Y:2.0v7 2.0V~
0.45V
RESET. Timing
CLOCKS ARE DRIVEN AT 3.0V FORA LOGIC "1" AND 0.3V FOR A
LOGIC "0:' TIMING MEASUReMENTS ARE MADE AT 2.4V FOR A
LOGIC "1" AND 0.65V FOR A LOGIC "0:'
AC Timing Measurement Conditions
2-157
Double-Density Floppy Di.sk Controller (DDFDC)
R6565
AC CHARACTERISTICS
01cc = 5.0 Vde ± 5%, vss = 0 Vde, T A = O"C to 7O"C)
Ref.
Fig.
9
10
11
Min.
Typ.
Max .
Unit
Clock Period
lev
leA
r;y
120
125
500
ns
Clock High, Low Width
0
80
125.
ns
3
Clock Rise Time
icLCH
,
4
Clock Fall Time
icHCL
f
-
-
5
\12 Clock Cycle Time
icr;y
t2CY
500
6
\12 Clock Low
icL
.12CL
210
7
\12 Clock High
icH
I2CH
220
8
Address Setup Time
tNC:H
lAS
70
9
Address Hold Time
icLAX
IAH
10
10
Data Aceess Time
tAVDV
tACC
-
11
Dala Setup Time
los
60
12
Dala Hold
tOVCL
t MOX
IoH
10
13
TXRQ Setup 10\12 High
IlVCH
tTSH
120
14
TXRQ Sstup to \12 Low
tlVCL
ITSL
210
15
TXRQ Hold from \12 High
&
8
All. Sym.
1
6
12
Symbol
2
5
7
Characteristic
. No.
....
16 , TXRQ Hoi!! frolll \12 Low
17 . DACK Delay Time
icHTX
ITHH
10
icLTX
ITHL
10
tC~L
tAD
-
ns
100
ns
WCK .FaIl.Time
tKHKL
tf
25
WCK High 10 PSO, PSI val.id (Delay)
tKHPV
icp
20
26
PSO, PSI .valld toWDA High (Delay)
tpvoH
ico
20
27
WDA High Width
tOHOL
twoo
twcH-50
28
WE High to WCK High or WE Low to WCK Low
ROW Cycle Time
tWE
twcy
20
30
tEHKH
twcy
31
ROW valid 10 ROD High (Setup)
tWVAH
IWRO
32
ROD Low to ROW Invalid (Hoi!!)
tALWI
IROW
15
33
ROD High Wi!!th
tAHRL
tAOO
40
35
USO, USI vali!! to SEEK High (Setup)
tUVSH
tus
12
36
SEEK
tSWI
tsu
15
80
15
SEEK Higl) to DIR vali!! (Setup)
tSHOY
Iso
7
38
39
40
DIR Invalid to SEEK Low (Hoi!!)
tOXSL
tos
30
DIR Valid to STP High (Setup)
tDVTH
tOST
1
STP Low to DIR Invalid (Hold)
ITLOX
tsro
.24
41
STP Low to USO,USI Invalid (Hold)
tTwX
ISTU
5
42
STp High Widlh
1STl'
6
46
DONE Low Width
t";TL
15
47
RES Low Width
tAHRL
note 2
37
14
-
Isc
333
tFR
t lOX
8
10
tre
t AST
14
1
-
7
-
-
p.S
210
p.S
100
-
-
ns
ns
~s
ns
ns
-
ns
nole3
10
-
"
p.S
-
-
ClK = 8 MHz
ns
ns
24
-
IIHIL
ns
100
t,
lOX High Width
ns
-
ns
tKLKH
45'
ns
ns
20
tKHK
WCK Rise Time
13
ns
ns
WCK High Width
23
IFHFL
ns
20
22
lev
10
FR High Widlh
ns
150
C L =I00pF
ns
350
WCK Cycle Time
STP Cycle Time
-
ns.
ns
2,5.0
21
44
-
250
-
ClK = 8 MHz
ns
-
too
43
-
ns
note 1
tAH
icLOL
tKCY
12
-
-
-
-
icLAH
OPNE Delay Time
tTHTL
tlC"(
-
-
ns
ns
-
30
DACK Hold Time
Invall!! (Hoi!!)
-
-
-
-
18
19
LOw to USO, USI
--
Test
Condilions
~s
p.S
p.S
p.S
~s
ClK = 8 MHz
~s
p.S
~.s
p.S
p.S
lev
lev
lev
Noles:
1.
MFM
. Mini
0
4~
1
2p.S
. Standard
2p.S
"
IpS
2. For MFM = 0: Typ. = 2 p.S
For MFM ,= .1: Typ. = 1 ~
3. Isc = 33 p.S min. is for different drive units, In the case of Ihe same unit,
tsc can range from 1 ms to 16 ms with 8 MHz clock period, and 2 ms
to 32 ms with 4 MHz clock, under software conlrol.
2-158
Double-Density Floppy Disk Controller (DDFDC)
R6565
ABSOLUTE MAXIMUM RATINGS·
Symbol
Value
Supply Voltage
Parameter
Vee
-0.3 to + 7.0
V
·NOTE: Stresses above those listed under ABSOLUTE .MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in other sections of this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Unit
Input Voltage
VIN
-0.3 to + 7.0
V
Output Voltage
VOUT
-0.3 to + 7.0
V
Operating Temperature Range
TA
Oto +70
C·
Storage Temperature Range
TSTG
-55 to + 150
C·
OPERATING CONDITIONS
Parameter
Range
Vee Power Supply
5.0V ±5%
Operating Ternperature
O·C to 70·C
DC CHARACTERISTICS
(Vee = 5.0 Vde ±50/0, Vss = 0 Vde, TA = OOC to 70°C, unless otherwise noted)
Symbol
Parameter
Input Low Voltage
Logic
CLK and WCK
VIL
Input High Voltage
Logic
CLK and WCK
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
Vee Supply Current
Icc
Input Load Current
IlL
Min
Max
-0.5
-0.5
0.8
0.65
2.0
2.4
Vee + 0.5
Vee + 0.5
V
2.4
0.45
V
Vee
V
150
10
rnA
pA
-10
pA
High Level Output Leakage Current
110H
10
pA
Low Level Output Leakage Current
llOL
-10
pA
Internal Power Dissipation
PINT
1.0
W
-
CAPACITANCE
,;
25°C;
fo = 1 MHz; Vee = OV)
Parameter
Symbol
Max Limit
Unit
Clock Input
CIN(O)
20
pF
Input
CIN
10
pF
20
pF
Output
COUT
Test Conditions
V
AlllnpulS
(TA
Unit
Note: All pins except pin under test tied to ground.
2-159
= 4.75V, 10L = 2:0 rnA
= 4.75V, 10H = -200 pA
Vee = 4.75V
VIN = Vee
VIN = OV
Vee = OV to 5.25V, VSS = OV
VOUT = Vee
Vee = OV to 5.25\1, Vss = OV
VOUT = +O.45V
TA = 25°C
Vee
Vee
II
Double-Density Floppy Disk Controller (DDFDC)
R6565
PACKAGE DIMENSIONS
4o-PIN CERAMIC DIP
DIM
A
B
~F I 1I I I I II 1I II [I J
H
J'
j'Liiiiiiiiiiiiiiij,fl
'-
o
SEATING PLANE I
tNJU
I
--l
C
ILK -+-J
I
G-i
M-1
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
50.29
14.88
2.54
0.36
0.76
2.54
0.76
0.20
2.54
14.80
51.31
15.62
4.19
-0:53
1.40
Bse
1.78
0.33
4.19
15.37
10'
O'
0.51
1.52
INCHES
MIN
MAX
1.980
0.585
0.100
0.015
0.030
0.100
0.030
0.008
0.100
0.575
O'
0.020
2.020
0.615
0.165
0.021
0.055
Bse
0.070
0.013
0.165
0:605
10'
0.060
40-PIN PLASTIC DIP
DIM
A
B
e
0
F
G
H
J
K
L
M
N
2·160
MILLIMETERS
MIN 'MAX
51.28
13.72
3.55
0.36
1.02
2.54
1.65
0.20
3.05
15,.24
7'
0.51
52.32
14.22
5.08
0.51
1.52
BSC
2.16
0.30
3,56
BSC
10'
1.02
INCHES
MIN
MAX
2,040
0.540
0.140
2.080
0.560
0.200
0.014 0.020
0.040 0.080
0.100 Bse
0.065 0.065
0.008 0.012
0.120 0.140
0.600 Bse
7'
10'
0.020 0.040
R6592
R6500 Microcomputer System
'1'
R6592
SINGLE-CHIP PRINTER CONTROLLER
Rockwell
INTRODUCTION
• Six Special ASCII Characters (7 Bit Code)
• Up to 10 ASCII Commands Accepted (Printer Dependent)
The Rockwell R6592 is a single-chip printer controller for
eight different EPSON* dot-matrix impact printers, models
210, 220, 240, 511l, 512, 522, 541l, and 542. The R6592
offers the flexibility to support any of these models with a
minimum of circuitry. Generation of 96 standard ASCII
upper and lower case characters and 6 special characters
is provided. In addition, up to 10 ASCII control commands
are accepted, depending upon the printer. logic is included
in the R6592 to print up to 26 columns on the 210, 220,
and 240 models, and up to 40 columns on the 511l, 512,
522, 541 land 542 models.
• Selectable Serial or Parallel Input Data Operation
• Centronics Standard Parallel Interface
- Seven Data Lines Plus Data Strobe and Input Drive
Input
- Busy and Acknowledge Output
• RS-232C Serial Interface
- Baud Rate from 50 to 7200 Bits per Second
- Received Data and Data Set Ready Input
- Data Terminal Ready Output
• Single
• 1 MHz operation (2 MHz external crystal)
VRR
PCL3
PCL2
PCL1
NC
PM1
*EPSON is a trade name of Shinshu Seiki Co., Ltd., a
member of the Seiko Group. EPSON printers are distributed
in the United-States by C. Itoh Electronics, Inc. The R6592
meets the printer specifications listed in this data sheet.
SER DET
ACK
BUSY/DTR
XTLI
XTLO
VSS
MDS
PS7
PS6
PS5
PS4
PS3
PS2
PS1
FEATURES
• Controls EPSON Dot-Matrix Impact Printers:
Model
Model
Model
Model
210
220
240
511l
Model
Model
Model
Model
+ 5V ± 10% power supply
• 40 pin plastic or ceramic DIP
Input data may be selected to be in the RS-232 serial format with selectable baud rate from 50 to 7200 bits/second
or the parallel format. External circuitry is required to convert RS-232 logic levels to R6592 interface logic levels. An
external latch may be required for the R6592 to sample
parallel data. If both selectable serial and parallel data interface capability is desired, two external multiplexers are
required; one to combine four serial baud select lines and
four parallel data interface lines into four R6592 input iines
and the other to combine two serial data/control lines and
two parallel control lines into two other R6592 input lines.
512
522
541 l
542
• Minimal Support Circuitry Required
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC (+5 Vdc)
RES
PTR TIM
DS/RSD
SER S!:L
PRT
PM2
PM3
RR
RLIRL
VCC
DL1
DL2
DL3
DL4
DL5
DL6
DL7
INP/DSR
SER eLK
• On-Chip 5 x 7 Dot-Matrix Character Generation
• 96 Standard Upper and lower Case ASCII Characters
(7 Bit Code)
R6592
Document No. 29000058
2-161
Pin Configuration
Data Sheet Order No. 058
Rev. 1, August 1983
II
Single-Chip Printer Controller
R6592
SERIAL
INTERFACE
(RS 232)
~~=:>
r¢2SERIAL
IIQ1'ERFACE
LOGIC
t-!~
,
2 .......
~9~
~9::>
"
SERIAL
INPUT
COMMAND
PROCESSING
PARALLEL
INPUT
NON-PRINT
COMMAND
CONTROL
CHARACTER
PREBUFFER
PRINTER
MOTOR
CONTROL
MOTOR
DRIVE
CIRCUIT
CHARACTER
DECODE
PRINT HEAD
SOLENOID
CONTROL
CONSTANT
CURRENT
SOLENOID
DRIVER
SERIAU
PARALLEL
SELECT
CHARACTER
PROCESSING
TIMING &
DIRECTION
MONITOR
'RESET'
,SWITCH
LINE DATA
BUFFER
PARALLEL
'PARALLEL
INTERFACE
INTERFACE
(CENTRONICS) ~2- LOGIC
k=2"-
2 MHZ
CRYS,TAL
~2~
B3:)
-'
;:3~
~7::::>
....
K...
MAGNET
DRIVERS
~c:>
~7:)
SEIKO
DOT-MATRIX
IMPACT
PRINTER
(2008.500
SERIES)
3
PRINT
SWITCH
DOT-MATRIX
CHARACTER
c;ODES
~c
PRINTER
MODEL
R6592 Interface Diagram
Active low output control lines used to issue various nonprint commands to the printer. These lines are inputs to
+24V drivers. When low, these lines cause magnets to be
energized in the printer; when high, the magnets, are to be
de-energized, These lines are assigned to specific signals
depending upon printer model: '
INTERFACE SIGNALS
PRINTER SOLENOID
PRINTER SOLENQID
PRINTER SOLEIIIOID
PRINTER SOLENOID
PRINTER SOLENOID
PRINTER SOLENOID
1
2
3
4
5
6
(PS1)
(PS2)
(PS3)
(PSIi)
(PS5)
(PS6)
R6592 Signal Name
Active low output signals used to command seven constant
current print head solenoid drivers, When low, the respective solenoid will be energized to print a dot; and when
high, the solenoid will be de-energized \0 not print a dot.
Each ,solenojd line corresponds to a dot position on the
seven row print head. Line ffi corresponds to the top dot
and PS7 corresponds to the bottom dot. The output lines
are activated by the positive edge of the timing signal
(TIM). The TIM signal should also be used to gate PS1
through PS7 to the current drivers and to de-energize the
current driver inputs within 600 ± 20 fLsec' of the start of the
TIM signal by means of a one-shotflip-fiop.
Printer
Model
PCL1
210
220
240
511l
512
522
541l
542
NA
Paper Feed (R)
NA
NA
NA
Paper Feed (Rl
NA
NA
NA = Not Assigned
PRINTER CONTROL LINE 1 (PCL 1)
PRINTER CONTROL LINE 2 (PCL2)
PRINTER CONTROL LINE 3 (PCL3)
TIMING (TIM)
RESET LEFT (RLlRL)
RESET RIGHT (RR)
2-162
PCL2
PCL3
Paper Feed
Change Color
Paper Feed (ll
Paper Feed
Slip Release
Paper Feed
NA
Paper Feed
NA
Paper FE!ed (ll ' Stamp an!! Cut Paper
Paper Feed
Paper Release
Paper Feed
Paper Release
R6592
Single-Chip Printer Controller
Input signals used to indicate print cycle Timing. The R6592
Initiates a print cycle on the leading edge (positive transition) of the TIM signal information to the R6592. The RESET
signals are active low for the 500 serres (RR and RL) and
are active high for the 200 series (RL). The printer timing
and reset lines are assigned as follows:
SERIAL SELECT (SER SEL)
Active high Input line used to indicate the desired data transmission mode to the R6592. When high (open), input data
will be received and processed from the _serial interface
(RS-232C). When low (GND), input data will be received and
processed from the parallel interface (Centronics).
fl6592 Signal
Printer
Model
TIM
RURL
210
220
240
511L
T Detector
T Detector
T Detector
Timing Signal
512
Timing Signal
522
Timing Signal
541L
Timing Signal
542
Timing Signal
A Detector (AL)
A Detector (AL)
R Detector (RL)
Reset Signal R-L
(RLI
Reset Signal R-L
(RLI
Reset Signal R-L
(RLI
Reset Signal R-L
(RLI
Reset Signal R-L
(RLI
RR
If both transmission modes are to be implemented (but not
simultaneously), the SERSEl"Iine should be used to select
either serial or parallel signals through multiplexer circuits. If
either serial or parallel dat. transmission is exclusively
used, multiplexing of the indicated serial/parallel signals is
not required.
NA
NA
NA
NA
Aaset Signal R-A
(RRI
Reset Signal A-R
(RRI
NA
DATA LINE 1/BAUD RATE 1 (DL1/BR1)
DATA LINE 21BAUO RATE 2 (DL2IBR2)
DATA LINE 3/BAUD RATE 3 (OL3/BR3)
DATA LINE 41BAUD RATE 4 (DL4/BR4)
Active high input signals used as parallel data lines if parallel data transfer mode is selected, or used as baud rate
select lines if serial data transier mode is selected.
Reset Signal R-R
(RRI
See Detail Timing Diagrams in Printer Specifications.
If parallel data transfer mode is selected (SER SEL = low)
these lines represent four of the seven total data lines (see
below). DU/BR1 represents the least significant bit when
ASCII characters are decoded. If serial data transfer mQde
is selected (SER SEL = high), the data transier baud rate
in bits per second is:
MOTOR DRIVE SIGNAL (MDS)
Active low output signal used to control application of power
from a driver circuit to the printer motor. When high, the
motor drive is turned off and when low, the motor drive is
turned on. The driver circuit for the 500 series must supply
10 to 30 ma at TTL levels. The driver circuit for the 200
series must additionally provide motor braking.
Data Line/Baud Rate Line
PRINTER MODEL 1 (PM1)
PRINTER MODEL 2 (PM2)
PRINTER MODEL 3 (PM3)
Encoded input lines used to determine which printer model
is conne9ted to the R6592. A connection to GND (low)
causes "0" to be read. An open input (high) causes logic
"1" to be read. The encoding for the printer model is:
Printer
Model
210
220
240
511L
512
522
-541L
542
0
0
0
0
1
1
1
1
PM2
0
0
1
1
0
0
1
1
DL4/BR4
50
75
110
135
150
300
0
0
0
eOO
1200
1800
2400
3600
4800
7200'
Printer MOdel Line
PM3
Baud
PM1
0
1
0
1
0
1
0
1
ci
0
0
0
0
1
1
1
1
1
DL$/BR3
0
0
0
.0
1
1
1
1
0
0
0
0
1
DL2/BR2
DLlIBR1
0
0
-1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
P
1
0
1
0
1
0
Note: 1 = HIgh (open), 0 = Low (GNDI.
• Data 'cannot be sent to the R6592 while the print head is
moving.
DATA LINE 5 (DL3)
DATA LINE 6 (01:.4)
DATA LlNE.7 (OL5)
PRINT (PAT)
Active high input signals used as data lines when parallel
data transfer mode is selected (SER SEL = low). DL7 represents the most significant bit (MSB) when ASCII characters are decoded .. Not used when serial data transfer mode
is selected (SER SEL = high).
Active low input line used. to command R6592 to print a
line. When low (GND) print commands will continue to be
issued. If the print buffer is . partially filled, a line will be
printed. Line feeds will subsequently be issued while PRT is
low. When high (open), print commands will not be issued_
2-163
II
Single-Chip Printer Controller
R6592
receive data. When low, DTR Indicates that the R6592 is
ready to receive, dalj!\. i5i'R is switched high during character
print and while non-print CQmmands are being processed.
INPut PRIME (IP)IDATA SET READY (DSR) ,
Input line IT\Ultiplexed between .,a paraliel communications
control Iirie(INPUT PRIME) and a serial communications
eontrolline (DATA SET READY).
ACKNOWLEDGE (ACK)
Active low output signal used to' inform the parallel data transmitter that an input character has been received. ACK is
switched low for ,5 jJ.S8C to iridicate receipt of a character.
If the parallel data transfer mode is selected (SEl! SEl
low), this line isass'igned to INPUT PRIME (IP). When
jplDSR is high, the R6592 issues prints commands to the
printer in a normal fashion. WhendP1DSR is low, the R6592
Will 'disable printing. Thi, line can, therefore, be used as a
print disable line to selected p~nters in a multiprinler system.
"
SERIAL CLOCK (SER ClK)
II the serial data transfer mode is selected (SER SEL =
high), the line is assigned to DATA SET READY ,(DSR).
When high, DSR indicates that the transmitter is operative
,and the R6592 will accept data, When low, DSR indicates
that the transmitter is not reiidy to operate' and the R6592
will not accept serial data.
A bi-directlonal line used to detect the start of the received
serial data and to then clock ill the serial data bits. When
DETENAis low, this line mO!,!itors the input serial data
stream for the ,start bit. When ttle leading (falling) edge of
the start bit is, detected, the DET ENA is switched high and
t~is line is switched 10 an output. Output pulses are generated on this line to clock the received serial data into the
R6592 at the selected baud rate.
DATA STROBE (DS)/REOEIVED SERIAL DATA (RSD)
SERIAL DETECT ,ENABLE (DET ENA)
Input line multiplexe
N
I
n
-
?
a
-
0
DEL
1
2
"
7
CAN
5
4
100
.
(
)
8
9
:
+
;
<
-
;
I
Line Feed
VertiCal Tabulation
Form Feed
Carriage Return
Device Control 1
Device Control 2
Device Control 3
Device Control 4
X
Y
Z
CAN - Cancel
¥
-Yen
t
- Pound
Q:
-Cent
12 -One-Half
N
- No Tax
T
T
X
Note: Valid control commands are dependent upon printer model.
2-166
4 Tax
S
t
u
f
v
9
h
w
i
j
x
Y
z
{
I
}
Single-Chip Printer Controller
R6592
PARALLEL DATA INTERFACE
-
BUSY
BUSY RET
11·
29
BUSY/DTR
~
INPUT PRIME
INPUT PRIME RET
31
30 ~'
DATA STROBE
DATA STROBE RET
1
19
ACKNOWLEDGE
ACKNOWLEDGE RET
10
28
'NOT REQUIRED IF PARALLEL DATA
IS HELD FOR 2:50,.s AFTER LEADING
EDGE OF DS OR UNTIL ACK IS RECEIVED.
DATA 1
DATA 1 RET
2
20
DATA 2
DATA 2 RET
3
21
DATA 3
DATA 3 RET
4
22
DATA 4
DATA 4 RET
5
23
DATA 5
DATA 5 RET
6
24
DATA 6
DATA 6 RET
7
25
DATA 7
DATA 7 RET
8
26
DATA 8
DATA 8 RET
CENTRONICS PARALLEL INTERFACE
9
iP/DSR
22
DS
~
37
ACK
~_L;
8
R6592
DL1/BR1
29
~
DL2/BR2
28
~
DL3/BR3
~
LATCH' DL4/BR4
27
26
~
DL5
~
DL6
~
DL7
25
24
23
~
9~
......
R6592 INTERFACE
27~
;
PAR.ALLEL DATA TIMING
------~,
INPUT PRIME (iP)
DATA STROBE (DS)
- -- -----~r-- U~-~S
L
11'S - - '
(MIN)
l--
I .
PARALLEL DATA (DL1-DL7j
-----If ~f---1 Jf----
1-1
--"'O---If-"- -~ f- - - -
---~f f---1f----f f
1-5
.
50I'S(MIN)',
.
-_. . . .I.. ' . '. .f. s----;
.' L---ff----{f---{
S~--
ACKNOWLEDGE (ACK)
BUSY
--.....,......--~J~f_ _.......r~~J~_'OR UNTILACK IS RECEIVED.
2-167
EI
Single-Chip Printer Controller
R6592
SERIAL DATA INTERFACE
DET ENA
.----------.....;;.;;.;..;;;;.~~7
~~---S-E-R~C-LK~·~21
CLK
RECEIVED SERIAL
DATA (RSD)
2
0
Q'
OS/RSD
37
5
R6592
7474
DATA SET READY (DSR)
iP/DSR
I--------------"-----.....;;;",,;.;;..;..;.;;-t~
6
22
+12V
DATA TERMINAL READY (DTR)
BUSY/DTR
20 . .- - - - 0 < 1-_ _ _ _ _ _-..;;;.;;..:;..:..:..:;..;;.;.;...--1
9
-12V
~
~
RS-232 INTERFACE
SERIAL OAT A TIMING
R6592 INTERFACE
---------------~fHHS!---
DATA SET READY (DSR)
-
-- -- -
-
-
-
-
-
-
-
-
-
-
-
-----{f-~r__{f_ - - -
I~J--/r---l~
SERIAL DETECT ENABLE (DET ENA)
~-------------~
SERIAL CLOCK (SER CLK)
7 BIT CODE DATA SAMPLES:
t t t tt t t
RECEIVED SERIAL DATA (RSD)
RECEIVED SERIAL DATA (RSD)
_ _ _.......11
STA", m,
k~BI314·151617IM:BI
~ , '"
'.
.
COO';:=:\- 'A"OY Brr AND ~
2 OR ~JtJ BITS
RECEIVED DATA BITS.
DATA TERMINAL READY (DTR)
DATA TERMINAL READY (DTR)
2-168
f Hf-{
Single-Chip Printer Controller
R6592
PRINTER INTERFACE SPECIFICATIONS
The R6592 is designed to meet the interface requirements
stated in the following printer specification:
For further printer information, contact:
EPSON America, Inc.
23844 Hawthorne Blvd. Ltd.
Torrance, CA 90505
Phone: (213) 378-2220
TWX: 910-344-7390
Model-210 Impact Dot Matrix Mini-Printer (Preliminary)
Rev. 4, AUGUST 30, 1978
Model-220 Impact Dot Matrix Mini-Printer,
SEPTEMBER 18, 1978
C. Itoh Electronics, Inc.
5301 Beethoven Street
Los Angeles, Calif. 90066
Phone: (213) 390-7778
Telex: WU 65-2451
Model-240 Impact Dot Matrix Mini-Printer,
SEPTEMBER 18, 1978
Model-511L Impact Dot Matrix Printer (Enlarged Character)
Revision 1 JULY 13, 1978
C. Itoh Electronics, Inc.
280 Park Avenue
New York, New York, 10017
Phone: (212) 682-0420
Telex: WUD-12-5059
Model 512 Dot-Matrix Impact Printer (P512DF),
APRIL 10, 1978
Model 522 Dot-Matrix Impact Printer (P522DF),
MARCH 1, 1978
Model 541Llmpact Dot Matrix Printer (Enlarged Character),
Revision 1, July 19, 1978
Model 542 Dot-Matrix Impact Printer (P542DF),
MARCH 1, 1978
2-169
II
Single-Chip Printer Controller
R6592·
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
.
Value
Unit
Vec
-0.3 to +7.0
Vde
Input Voltage
VIN
-0.3 to Vee +0.3
Vdc
Output Voltage
VOUT
-0.3 to Vcc +0.3
Vdc
Operating Temperature
Commercial
Industrial
TA
Storage Temperature
TSTG
Supply Voltage
°NOTE: Str~sses above those listed may cause permanent
damage to the device. Tnis is stress rating only and functional
operation of the device at these or any other conditions above
those indicated in the other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
a
°C
o to +70
-40 to +85
_55 to+ 150
·C
STATIC DC CHARACTERISTICS
(Vee = 5.0V ±10%)
Parameter
Symbol
Min.
Typ.
Max.
-
500
-
mW
-
Vcc
Vdc
-0.3
-:-
+0.8
Vde
0.8
-
2.0
Vde
Power Dissipation (Outputs High)
Po
Input High V(lltage (Normal Operating Levels)
V1H
+2.0
Input Low Voltage (Normal Operating Levels)
VIL
Input Threshold Voltage
VIT
Input Leakage Current
. V ln = 0 to 5.0 Vdc
RES
Unit
pAde
'iN
-
±1.0
±2.5
Input High Voltage (XTLI)
VIHXT
+4.0
-
Vee
Vdc
Input Low Voltage (XTLI)
VILXT
-0.3
-
+0.8
Vdc
Input Low Current
(Vll = 0.4 Vdc)
IlL
-1.0
-1.6
mAde
Output High Voltage
(Vee = min, Iload = -100 pAdc)
VOH
Output Low Voltage
(Vce = min, 'load
VOL
-
= 1.6 mAde)
Output High Current (Sourcing)
(VOH = 2.4 Vdc)
10H
Output Low Current (Sinking)
(VOL = 0.4 Vdc)
10L
Input CapaCitance
(V ln - 0, TA = 25°C, f = 1.0 MHz)
Pins 2-9, 13-29 and 31-38
XTLI, XTLO
Cin
2.4
-
-
-
-0.4
Vdc
pAdc
-
-
-100
1.6
-
Vde
mAdc
pF
-
-
Output Capacitance
COUT
(Vin - 0, TA = 25°C, f = 1.0 MHz)
Note: Negative sign indicates outward current flow, positive indicates inward flow.
-
2-170
-
-
10
50
-
10
pF
R6592
Single-Chip Printer Controller
PACKAGE DIMENSIONS
0;15S,MAX
(3.93 MM),
'
--*-[
LOtJ
·L
DOT OR NOTCH
TO LOCATE
PIN NO. 1
. '
.
.'
.' ....
t
0.600 MAX
(15.87) 0.825
(15.24 MM)
l15.m.
JO~"
2.020 MAX
10' MAX
~
o:m
j
ffiffi=r==F~'
t·
.
: :~: ~::: J
TYP.
~~TYP
(0.45) 0.018
"
.
0.0,0 MIN
(0.25 MM)
(1.910) (43.61 MM)
(1.890) (48.00 MM)'
(51.30MM)
19 EQUAL SPACES
0.100 It TOL NO.NCUM.
(2.5~ MM)
NOTE: PIN NO.1 IS IN LOWER LEFT CORNER WHEN SYMBOLIZATION IS IN NORMAL. ORIENTATION.
2-17.1
II
R65560
'1' ·
Rockwell
R65560
MULTI-PROTOCOL ·.COMMUNICATIONS
CONTROLLER (MPCC)
PRELIMINARY
DESCRIPTION
FEATURES.
The R65560 Multi-Protocol Communications Controller (MPqc)
interfaces II single serial communications channel to a 65001
6800 microcomputer-based system using either asynchronous
or synchronous protocol. High speed .bit rate, automatic formatting, low overhead programming, liIight character buffering, and
two channel DMA interface optimi:!:e MP,CC performance to take
full advantage of the 65OO/s800 processing capabilities.
• Full duplex synchronolJll/asynchronous receiver and tranSm~r
In .synchronous .operation, the MPCC scipports bit-orient8d
protocols (BOP), such all $Dt.,C/HDLC, anq. c.~aracter-or'I'"ted
protocols (COP), such 'as IBM Bisync (SSC) ,in eithet ASCII or
EBCDIC coding. Formatting, synchronizing, valle/ation and error
deteCtion Is perfol1l1ed automatic;ally in~roanp8 withprot~1
requirements and select~ options. Asynehrono\ls (ASYNO) and
isochronous (ISOC) modes are also sUPJ)9rted. Iii addition,
modem interface handshake signals are. available for general
use.
Control, status and data are transferred between the MPCC and
the microcomputer bus via 19 directly addressable registers and
a DMA interface. Two first-in first-out (FIFO) registers. addressable through separate receiver and transmitter data registers,
each buffer up to eight characters at a time to allow more CPU!
MPU proceSSing time to service data received or to be
transmitted and to maximize bus throughput, especially during
DMA operation. The tw<>channel Direct Memory Access (DMA)
interface operates with theMC6844 DMA Controller.
An on-chlposcillator drives the internal baud rate generator
(SRG) and an external clock output with an 8 MHz input crYstal
or clock frequency. The BRG, in conjunction with two selectable
prescalers and HI-bit programmable divisor, provides a data bit
rate of DC to 4 MHz.
• Fully implements IBM Binary Synchronous Communications
(BSC) in two coding formats: ASCII and EBCDIC
• Supports other synchronous .chara~ter-oriellted protocols
(COP). such as six-bit BSC. )(3.28. ISO IS1745, ECMA-16,
elc.
• Supports synchronous bil-oriented protocols (BOP), such as
SDLC, HDLC!X.25, etc.
• Asynchronous and isochronous modes
• Modem handshakeh,terface
• High speed serial. data rate (Dc to 4 MHz)
• Internal oscillator and Baud Rate Generetor (BRG) With programmable data rate
'
• Crystal or TTL level clock input and buffered clock output
(8 MHz)
,
• Direct Interface to 6500/6800 microprocessor bus
• Eight-character receiver and transmitter buffer registers
• 19 directly addressable registers for flexible option selection,
complete Iltatus repbrting, and data transfer
• Maslalble Interrupt cOl'1ditions for receiver, transmitter and
serial· interface
• Programmable microprocessor bus- data transfer: polled.
interrupt and twO-Channel DMA transfer' compatible with
MC6844
• Clock eontrolJegister for receiver clock divisor and receiver
and transmitter clock routing
• Selectable full/half duplex, autoecho and local loop-back
mOdes
ORDERING INFORMATION
•
Part Number
.R65560
1
Frequency
Temperature Range
4 MHz
0·0 to 70·0
Selectabl~ parity (enable, odd, even) and CRe (control field
enable,CJ;lC-16, CCITTV.41 .. VRC/LRC)
Package: 0 = CeramiC
P
Plastic
=
Document No. 29651 N50
Product Description Order No_ 2147
Rev_ t, March 1984
Multi';'Protocol·Comri'lunications Controller (MPCC)
R65560
Ycc - - - "
GND----+
8 BYTE
TItFiFO
Txt>
TO Rx LOGIC
~TEST MODE)
Ao-"4
iRa
MICROPROCESSOR
BUS
INTERFACE,
Iffl;
IIfS
1JO.01
CTs
CONTROL
C$
Rfii
12
6'Co
REGISTERS
DSR
AND
StATUS
REGISTERS
BAUD RATE GENERATOR
TxC
ReS
RxAFa.REAO
BCLK
TxFIFO W:RITE
EXTAL
XTAL
TDSR
ROsA
pMA
INTERFACE
R.C
DACK
DTS
iXiiiiE
AxFIFO READ
To Tx LOGIC
(ECHO,~DE)
•• 0
Figure 1. MPCC Block Dlagrem
2·173
Multi-Protocol Communications Controller (MPCC)
R65560
PIN DESCRIPTION
ROSR-Receiver Data Service Request. When receiver OMA
mode. is active, the low ROSR output requests OMA service.
Throughout the document, signals are presented using the terms
active and inactive or asserted and negated independent of
whether the signal is active in the high"voltage state or lowvoltage state. (The active state of each logic pin is described
below.) Active low signals are denoted by a superscript bar. RiW
indicates a write is active low and a read activei~ig!:l.
DACK,-DMA Acknowledge. The DACK low input indicates that
that the data bus has been acquired by the DMAC and that the
requested bus cycle is beginning.
OTS-OMA Transfer Strobe. The DTS low input causes a DMA
transfer to occur on the next ~2 cycle. When RiW is high, data is
transferred into the TxFIFO; when RiW is low, data is transferred
frQr:n th.e RxFIFO.
AO - A4-Address Lines. AO - A4 are active high inputs used
in conjunction with the CS input to access the internal registers.
The address map for these registers is shown in Table 1.
DO - 07-0ata Lines. The bidirectional data lines transfer data
between the MPCC and the CPU, memo~r other peripheral
device. The data bus is tri-stated when CS is inactive. (See
exceptions in DMA mode.)
CS-Chlp Select. ,CS low selects the MPCC for programmed
transfers with the'host. The MPCC is deselected when the CS
input is inactive in non-DMA' mode.
DONE-Done. DONE is a bidirectional active low Signal. The
DONE signal is asserted by the DMAC when the DMA transfer
count is exhausted and there is no more data to be transferred.
DONE will also be asserted by the MPCC, if enabled by bit 5 in
t!:le RCR, when t!:le status byte folloiwng the last character of
a frame (block) is being transferred in response to a ROSA. The
DONE signal asserted by the DMAC in response to a TDSR will
be stored to traCk. with the data byte through the TxFIFO.
RtW-ReadlWrlte, Rm controls the direction of data flow
through the bidirectiona,1 data bus by indicating that the current
.
bus cycle is a read (high) or write(I~W) cycle;
RES-Reset. RES is an active low; high impedance input that
initializes all MPCC functiohs. RES must be asserted for at
least 500 ns to initialize the MPCC.
!t2,"",Pl1ase 2. During a write (RfN low), the 02 negative trElnsition
latches data onc:lata bus lines 00- D7 into the MPCC. During
a read (RiW), ~2 high enables data from theMPCC to data bus
OTR-Oata Terminal Ready. The DTR active low output is
general purpose in nature, and is controlled by the DTRLVL bit
in the Serial Interface Control Register (SICR)
IRQ-Interrupt Request. The active low IRQ output requests
interrupt service by the CPU. IRQ is driven high after assertion
prior to being tri-stated,
RTS-'-Request to Send. The RTS active low output is general
CTS-Clear to Send. The CTS active low input positive transiition and level are reported in the CTST and CTSLVL bits in the
Serial Interface Status Register (SISRl, respectively.
TOSR-Transmitter Data Service Request. When Transmitter
DMA mode is active; the low TOSR output requests DMA service.
DATA
BUS
ADDRESS
BUS
BUS
INTERFACE
.
<'"
DO-D7
A1-A4
L
112
{
RTS
CTS
OTR
DSR
DCD
..
.
CS
R/W
MPCC
DMA
CONTROL
{
""
INTERRUPT
CONTROL
TxD
TxC
RES
R65560
TDSR
RDSR
DACK
DONE
DTS
IRQ
Figure 2.
}
~
"
""
RxD
RxC
EXTAL
XTAL
BCLK
"
Vee
GND
MPCC Input and Output Signals
2-174
MODEM
INTERFACE
} TRANSMITTER
INTERFACE
}
RECEIVER
INTERFACE
}
CLOCK
INTERFACE
R65560
Multi-Protocol Communications Controller (MPCC)
DSR-Data Set Ready. The DSR active low input negative
transition and level are reported in the DSRT and DSRLVL bits
in the SISR, respectively. DSR is also an outputlor RSYN.
EXTAL""Crystal/External Clock Input.
XTAL Crystal Return. EXTAL and XTAL connect an 8 MHz
external crystal to the MPCC internal oscillator. The pin EXTAL
may also be used as a TIL level input to supply a DC to 8 MHz
reference timing from an external clock source. XTAL must be
tied to ground when applying an external clock to the EXTAI,.
DCD-Data Carrier Detect. The DCD active low input positive
transition and level are reported in the DCDr and DCDLVL bits
in the the SISR, respectively.
input.
TxD-Transmitted Data. The MPCC transmits serial data on
the TxD output. The TxD output changes on the negative going
edge of TxC.
BCLK-Buffered Clock. BCLK is the internal oscillator buffered
output available to other MPCC devices eliminating the need
for additional cry$tals.
RxD-Reeelved Dllta. The MPCC receives serial data on the
RxD input. The RxD input is Shifted into .the receiver with the
negative going edge ofAxC.
Vee-Power. 5V
GND-Ground. Ground (Vss).
lXC-Transmitter Clock. TxC can be programmed to be an input
or an output. When TxC is selected to be an input, the transmitter
clock must be provided externally. When TxC is programmed to
bean output, a clock is generated by the. MPCC'sinternal baud
rate generator.' The Iow-ta-high transition of the clock signal nominally indicates the center of a serial data present on the TxD
output.
MPCC REGISTERS
Nineteen 8-bit registers define, control and monitor the data communications process. These registers and their access are listed
jn Table 1.
Table 2 summarizes the MPCC register bit assignments and their
access. A read from an unassigned location results in a read
from a "nUll register." A null register returns all ones for data
and results in a normal bus cycle. Unused bits of a defined
register are read as zeros unless. otherwise noted.
RxC-ReeeiverCloek. RxC provides the MPCC receiver with
received data timing information. The clock transition from
low-ta-high nominally indicates the center of each serial data
bit on the RxD input.
AO
NOT USED
RxD
O.TR
DSR
DCD
ROSR
A1
GND
A4
A2
A3
RxC
TxC
BCLK
EXTAL
XTAL
RiW
IRQ
RTS
± 5%.
2
3
4.
5
6
7
8
9
10
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
11
12
13
14
15
16
17
18
19
20
NOT USED"
'2
DTS
CS
OACK
GNO
DO
01
02
03
D4
05
D6
07
RES
CTS
Vee
DONE
TxD
TOSR
"Must be connected to Vcc.
R65560
Pin Configuration
2-175
2
Multi-Protocol Communications Controller (MPCC)
R65560
Table 1.
R65560 Accessible Registers
Register(s)
A4
Address Lines
A3
A2
A1
AD
0
o
7
Receiver Status Register (RSR)
RIW
00
0
0
0
0
Receiver Control Register (RCR)
RIW
01
0
0
0
0
1
R
02
0
0
0
1
0
RIW
05
0
0
1
0
1
0
Receiver Data Register (RDRJ1
Receiver Interrupt Enable Register (RIER)
Transmitter Statue Register (TSR)
RIW
08
0
1
0
0
Transmitter Control Register (TCR)
RIW
09
0
1
0
0
1
W
OA
0
1
0
1
0
RIW
00
0
1
1
0
1
Serial Interface Status Register (SISR)
RIW
10
1
0
0
0
0
Serial Interface Control Register (SICR)
R/W
11
1
0
0
.0
1
Serial Interrupt Enable Register (SIER)
RIW
15
1
0
1
0
1
0
Transmitter Data Register (TDR)2
Transmitter Interrupt Enable Register (TIER)
Protocol Select Register t(PSR1)
RIW
18
1
1
0
0
Protocol Select Register 2 (PSR2)
RIW
19
1
1
0
0
1
Address Register 1 (AR1)
RIW
1A
1
1
0
1
0
Address Register 2 (AR2)
RIW
1B
1
1
0
1
1
Baud Rate Divider Register 1 (BRDR1)
RIW
1C
1
1
1
0
0
Baud Rate Divider Register 2 (BRDR2)
RIW
10
1
1
1
0
1
Clock Control Register (CCR)
RIW
1E
1
1
1
1
0
Error Control Register (ECR)
RIW
1F
1
1
1
1
1
Notes:
1. Accessible register of the eight byte RxFIFO. The data is nol initialized, however, RES resets the RxFIFO pointer to the start of the first byte.
2. Accessible register of the eight byte TxFIFO. The daia ·is not initialized, however. RES resets the TxFIFO pointer to the start of the first byte.
3. Reserved registers may contain ranqom bit values.
Multi-Protocol Communications Controller (MPCC)
R65560
Table 2. MPCC Register Bit Assignments .
Bit Number
RIW
Reset··
Access
7
6
5
'4
3
2
1
0
Value
RIW
RDA
EOF
0
C/PERR
FRERR
ROVRN
RAiB
RIDLE
00
Receiver Status
Register (RSR)
RIW
0
RDSREN
DONEEN
RSYNEN
STRSYN
2ADCMP
RABTEN
RRES
01
Receiver Control
Register (RCR)
--
RECEIVED DATA (RxFIFO)
R
Receiver Data
Register (RDR)
0
C/PERR
IE
FRERR
IE
ROVRN
IE
RAiB
IE
0
00
Reeeiver Interrupt Enable
Register (RIER)
TFC
0
0
0
TUNRN
TFERR
0
80
Transmitter Status
Register (TSR)
TDSREN
TICS
THW
TLAST
TSYN
TABT
TRES
01
Transmitter Control
Register (TCR)
RIW
RDA
IE
EOF
IE
RIW
TDRA
RIW
TEN
--
TRANSMITTED DATA (TxFIFO)
W
Transmitter Data
Register (TDR)
RIW
TDRA
IE
TFC
IE
0
0
0
TUNRN
IE
TFERR
IE
0
00
Transmitter Interrupt Enable
Register (TIER)
RIW
CTST
DSRT
DCDT
CTSLVL
DSRLVL
DCDLVL
0
0
00
Serial Interface StatU5
Register (SISR)
R/W
RTSLVL
DTRLVL
0
0
0
ECHO
TEST
NRZI
00
Sellal I nterface Control
Register (SICR)
RIW
CTS
IE
DSR
IE
DCD
IE
0
0
0
0
0
00
Serial Interrupt Enabl$
Ragister (SIER)
RIW
0
0
0
0
0
0
CTLEX
ADDEX
00
Protocol Select
Register 1 (PSR1)
RIW
0
00
Protocol Select
Register 2 (PSR2)
STOP BIT SEL
SB1
SB2
I
PROTOCOL SEL
CHAR LEN SEL
CL2
I CL1
PS3
I
PS2
I
PS1
RIW
BOP ADDRESS/BSC & COP PAD
00
Address Register 1 (AR1)
RIW
BOP ADDRESS/BSC & COP SYN
00
Address Register 2 (AA2)
RIW
BAUD RATE DIVIDER (LSH)
01
Baud Rate Divider
Register 1 (BRDR1)
RIW
BAUD RATE DIVIDER (MSH)
00
Baud Rate Divider
Register 2 (BRDR2)
00
Clock Control
Register (CCR)
04
Error Control
Register (ECR)
R/W
0
0
0
PSCDIV
TCLKO
RCLKIN
R/W
PAREN
ODDPAR
0
0
CTLCRC
CRCPRE
Notes:
""RESET = Register contents upon power up or RES.
2-177
CLKSEL
CK2
I CK1
CRC SEL
CR2
CR1
1
II
R65560
Multi..ProtocolCommunications Controller (MPCC)
REGISTER DEFINITIONS
RSR
.1.
o
RECEIVER REGISTERS
Receiver Status Register (RSR)
RSR
The Receiver Status Register (RSR) contains the status of the
receiver including error conditions. Status bits are cleared by
writing a 1 int9 respectiv.e positions, by writing a 1 into the RCR
RRES bit or by RES. If an EOF, C/PERR, or FRERR is set in
the RSR, the data reflecting the error (the first byte or word in
the RxFIFO) must be read prior to resetting the corresponding
status bit in the R$R. The IRQ output is asserted if any of the
conditions reported by the status bits occur and the corresponding interrupt enable bit in the RIER is set.
i
o
.Q.
o
RDA
-Receiver Data Available. (RSR only).
The RxFIFO is empty (Le., no received data is
available).
Received data i.s aliailable in .the RxFIFO and can be
read via the RDA..
For the BSC and BOP protocols which have defined messllge
blocks or frames, a "frame statl,ls" byte will be loaded into the
.RxFIFO following t/:le last datil byte of each,block (see Figure
3). The EOF status in the RSR is then set when the byte/word
containing the frame status is the next byte/word to be read from
the RxFIFO.
RSR
.§.
o
RSR
~
RIDLE
-Receiver Idle. (RSR only).
Receiver not idle.
15 or more consecutive" 1's" have been received and
the receiver is in an inactive idle state.
Frame Status (RSR)
RSR
o
RA/B
-Receiver Abort/Break.
Normal Operation.
ABORT detected after an opening flag (BOP), ENQ
detected in a block of text data (BSC), or BREAK
detected (ASYNC).
RSR
The RSR format is the same as the frame status format (see
below) except as noted.
L
ROVRN
-Receiver Overrun.
No receiver overrun detected.
Receiver overrun detected. Indicates that receiver data
was attempted to be transferred into the RxFIFO when
it was full, resulting in loss of received data. The data
that is already in RxFIFO are not affected and may be
read by the processor.
EOF
-End of·Frame.
No end of frame or block detected.
End of frame or block detected (BOP and SSC).
In the receiver OMA mode, when the EOF status in the RSR
is set, DONE is asserted to the OMAC. Thus the last byte
accessed by the OMAC is always' a status byte, which the
processor may read to check the validity of entire frame.
-Not Used.
RSR
~
o
The frame status contains a/l the status contained within the RSR
with the exception 01 RDA and RIOLE.
.
C/PERR
-CRC/Parity Error.
No CRC or parity error detected.
CRC error detected (BOP, BSC), Parity error detected
(ASYNC, ISOC and COP).
RSR
~
o
.1
FRERR
-'-Frame Error.
No frame error detected .
Short Frame or a closing FLAG detected off boundary
(BOP), Frame error (ASYNC, ISOC) or receiver
overrun.
2-178
Multi·Protocol Communications Controller (MPCC)'
R65560
BYTE
D7
DATA
, M+1
M+2
Figure 3.
STATUS
NEXT FRAME
BSC/BOP Block/Frame Status Location
RCR
Receiver Control Register (RCR)
1-
o
Reset value = $01
The Receiver Control Register (RCR) selects receiver control
options.
RCR
L
o
RABTEN -Receiver Abort Enable (BOP only).
Do not abort frame upon error detection.
Abort frame upon RxFIFO overrun (ROVRN bit = 1 in
the RSR) or CFCRC error detection (C/PERR bit = 1
in the RSR). If either error occurs, the MPCC ignores
the remainder of the current frame and searches for
the beginning of the next frame:
RCR
-Not used.
~
o
RCR
~
fI
DO
,"M
RDSREN -Receiver Data Service Request Enable.
Disable receiver DMA mode.
Enable receiver DMA li10de.
RCR
5 DONEEN -DONE Output Enable.
'0
Disable DONE output.
1
Enable DONE output. (When the receiver is in the DMA
mode, i.e., RDSREN = 1).
RRES
-Receiver Reset Command.
Enable normal receiver operation.
Reset receiver. Resets the receiver section including
the RxFIFO and the RSR (but not the RCR). RRES is
set by RES or by writing a 1 into this bit for one write
cycle and is cleared by writing a 0 into this bit. RRES
requires clearing after RES,
Receiver Data Register (RDR)
RCR
.!. RSYNEN -RSYNEN Output Enable. Selects the
o
1
DSR signal input or the RSYN SYNC
signal output on the DSR pin.
Input DSR on DSA.
Output RSYN on DSR.
The receiver has an a-byte First In' First Out (FIFO) register file
(RxFIFO) where received data are stored befor,e being
transferred to the bus. The received data is transferred out of
the RxFIFO via the RDA. When the RxFIFO has a data byte
ready to be transferred, the RDA status bit in the RSR is set to 1.
RCR
1..
o
STRSYN -StrlpSYN Character (COP only).
Do not strip SYN character.
Strip SYN character.
RCR
1..
o
2ADCMP -OnelTwo Address Compare (BOP only).
Compare one address byte with the contents of AR1.
Compare two address bytes with the contents of AR1
and AR2.
2-179
R65560
Multi-Protocol Communications Controller (MPCC)
The Transmitter Status Register (TSR) contains the transmitter
status including error conditions. The transmitter status bits are
cleared by writing a 1 into their~ective positions, by writing
a 1 into the TCR TRES bit, or by RES. The IRQ output is asserted
if any of the conditions reported by the status bits occur and
the corresponding interrupt enable bit in the TIER is set.
Receiver Interrupt Enable Register (RIER)
7
6
5
4
3
2
1
0
RDA
IE
EOF
IE
0
C/PERR
IE
FRERR
IE
ROVRN
IE
RAlB
IE
-
Reset value = $00
The Receiver Interrupt Enable Register (RIER) contains interrupt enable bits for the Receiver Status Register (RSR). When
enabled, the TR"O output is asserted when the corresponding
condition is detected and reported in the RSR.
TSR
L
o
TDRA
-Transmitter Data Register Available.
The TxFIFO is full.
The TxFIFO is not full (i.e., available) and data to
transmit can be loaded via the TOR.
RIER
L
o
RDA IE
-Receiver Data Available Interrupt
Enable.
Disable RDA Interrupt.
Enable RDA Interrupt.
TSR
.!. TFC
o
RIER
.!. EOF IE
o
-End of Frame Interrupt Enable.
Disable EOF Interrupt.
Enable EOF Interrupt.
- TransmlHed Frame Complete. (BOP, BSC
and COP only).
Frame not complete.
Closing FLAG or ABORT character has been transmitted (BOP), Trailing PAD has been transmitted (BSC),
or the last character of a frame or block as defined by
TLAST (TCR bit 3) has been transmitted (COP).
TSR
-Not used.
i
TS.R
1.
RIER
..!. C/PERR IE--CRC/Plirity Error Interrupt Enable.
o
Disable C/PERR Interrupt.
Enable C/PERR Interrupt.
RIER
.1.
o
FRERR IE -Frame Error Interrupt Enable.
Disable FRERR Interrupt.
Enable FRERR Interrupt.
o
o
1
.1.
ROVi'tN IE -Receiver Overrun Interrupt Enable.
Disable ROVRN Interrupt.
Enable ROVRN Interrupt.
o
o
TFERR
-Transmit Frame Error (BOP only).
No frame error has occurred.
No control field was present (short frame).
Transmitter Control Register (TCR)
RIER
.1.
-Transmitter Underrun (BOP, aSCand
COP only). A transmitter underrunoccurs
when the transmitter runs out of data during a transmission. For BOP, the underrun
condition is treated as an abort. For BSC
and COP, SYN characters are transmitted
until more data is available in the TxFIFO .
No transmitter underrun occurred.
Transmitter underrun occurred.
TUNRN
TSR
RIER
1.
-Not used.
..H.
RIER
RA/B IE
-Receiver Abort/Break Interrupt Enable.
Disable RNB Interrupt.
Enable RNB Interrupt.
Reset value
RIER
..!l
=
$01
The Transmitter Control Register (TCR) selects transmitter control function.
-Not used .
TCR
TRANSMITTER REGISTERS
L
o
Transmitter Status Regil;ter. (TSR)
TFERR
Reset value = $80
2-180
TEN
-Transmitter Enable.
Disable transmitter. TxD output is idled. The TxFIFO
may be loaded while the transmitter is disabled.
Enable 'transmitter. .
R65560
Multi-Protocol Communications Controller (MPCC)
TCR
.!.
o
1
Transmit Data Register (TOR)
TDSREN
-Transmitter Data ServiCe Request
Enable.
Disable transmitter DMA mode.
Enable transmitter DMA mode.
TCR
.!.
o
The transmitter has an 8-byte FIFO register file (TxFIFO). Data
to be transmitted is transferred from the bus into the TxFIFO
via the TOR. The TDRA status bit in the TSR is set to 1 when
the TxFIFO is ready to accept another data byte. '
.
-Transmitter Idle Character Select. Selects
the idle character to be transmitted when
the transmitter is in an active idle mode
(transmitter enabled Or disabled).
Mark Idle (TxD output is held high).
Content of AR2 (BSC and COP), BR~AK condition
(ASYNC and ISOC) , or FLAG character (BOP).
TICS
Transmitter Interrupt Enable Register (TIER)
TCR
-Not Used. This bit is initialized to 0 by RES
and must not be set to 1.
.!.
o
6
5
4
3
2
1
TFC
IE
0"
0
0
TUNRN
IE
TFERR
IE
0
-
Reset value = $00
The Transmitter Interrupt Enable Register (TIER) contains
interrupt enable bits for the Transmitter Status Register. When
enabled, the IRQ output is asserted when the corresponding
condition is detected and reported in the TSR.
TCR
~
7
TDRA
IE
-Transmit Last Character (BOP, BSC and
COP only).
The next character is. not the last character in a frame
or block.
The next character to be written into the TDR is the
last character of the message. The TLAST bit
automatically returns to a 0 when the associated
word/byte is written to the TxFIFO. If the transmitter
DMA mode is enabled, TLAST is set to a 1 by DONE
from the DMAC. In this case the character written into
the TDR in the current cycle is the last character.
TLAST
TIER
1.
o
TORA IE
-Transmitter Data Register (TOR) Available Interrupt Enable.
Disable TDRA Interrupt.
Enable TDRA Interrupt.
TIER
.!.
TCR
~
o
1
TSYN
-Transmit SYN (BSCand COP only).
Do not transmit SYN characters.
Transmit SYN characters. Causes a pair of SYN
characters to be transmitted immediately following the
current character. If BSC transparent mode is active,
a OLE SYN sequence is transmitted. The TSYNbit
automatically returns to a 0 when the SYN character
is loaded into- the Transmitter Shift Register.
o
1
TIER
.H.
o
~
TABT
-Transmit ABORT (BOP only).
Enable normal transmitter operation.
Causes an abort by sending eight consecutive 1 ',so A
9ata word/byte must be loaded into the TxFIFO after
setting this bit in order to COmplete the command. The
TABT bit clears automatically when the subsequent
data word/byte is loaded into the TxFIF;O.
o
o
1
TUNRN IE -Transmitter Underrun(TUNRN) Interrupt
Enable •
Disable TUNRN Interrupt.
Enable TUNRN Interrupt.
TIER
.!.
o
1
TCR
Jt
-Not used.
TIER
TCR
.!.
-1\'ansmit Frame Complete (TFC) Interrupt
Enable.
Disable TFC Interrupt.
Enable TFC Interrupt.
TFC IE
TRES
- Trllnsmitter Reset Command.
Enable normal transmitter operation.
Reset transmitter: Clears the transmitter section
including the TxFIFO and the TSR (but not the TCR).
The TxD output is held in "Mark" condition. TRES is
set by RES or, by writing a 1 into this bit for one write
cycle and is cleared by writing a 0 into this bit. TRES
requires clearing after RES.
TFERR IE -Transmit Frame Error (TFERR) Interrupt
En,able.
Disable TFERR Intefrupt.
Enable TFERR Interrupt.
TIER
Jt
2-181
-Not USed.
fI''
Multi-Protocol Communications Controller (MPCC)
R65560
SERIAL INTERFACE REGISTERS
The Serial Interface Control Register (SICR) controls various
serial interface signals and test functions.
Serial Interface Status Register (SISR)
SICR
7
RTSLVL -Request to Send Level.
Negate RTS output (high).
Assert RTS output (low).
o
Reset value = $00
NOTE
The Serial Interface Status Register (SISR) contains the serial
inte.rface status information. The transition status bits (CTST,
DSRT and DCDT) are cleared by writing a 1 into their respectivepositions, or by RESET. The level status bits (CTSLVL,
DSRLVL and D9DLVL) reflect the state of their respective inputs
and cannot be cleared internally. The IRQ output is asserted
if any 01 the conditions reported by the transition status bits occur
and the corresponding interrupt enable bit in the SIER is set.
In BOP, BSC, or COP, when the RTSLVL bit is cleared
in the' middle of data transmission, the RTS outputremains asserted until the end of the current frame
or block has beentransmitted. In ASYNC orlSOC, the
RTS output is negated when the TxFIFO is empty. If
the transmitter is idling when the RTSLVL bit is reset,
the .RTS output is negated within two bit times.
SISR
7
, 1-
o
SICR
6
DTRLVL -Data Terminal Ready Level.
Negate DTR output (high).
Assert DTR output (lOW).
CTST
-Clear to Send Transition Status.
CTS has transitioned positive (fro'm active to inactive).
~S must be a zero).
CTS has not transitioned' positive.
o
SICR
SISR
Jl
1
o
1
o
.!.
o
DCDT
-Data Carrier Detect Transition S,atus.
DCD has transitioned positive (from active to inactive).
DCD has not transitioned positive.
SISR
4 CTSLVL -Clear to Send Level.
CTS input level is negated (high).
CTS input level is asserted (low).
1.
o
SISR
o
DSRLVL -Data Set Ready Level.
DSR input level is negated (high).
DSR input level is asserted (low).
SISR
2
DCDLVL -'-Data Carrier Detect Level.
DCD input level is negated (high).
DCD input level is asserted (lOW).
J!.
o
SISR
-Not used.
Serial Interface. Control Register (SICR)
0'
TEST
TEST
-Self·testEnable.
Disable self-tesqenable normal operation).
Enable self-test. The transmitted data (TxD) and clock
(TxC) are routed back through to the receiver through
RxD and, RxC, respectively (DCD and CTS are
ignored). This "Ioopback" self-test may be used for
all protocols, RxC is external regardless of the slate
of GGR bit 2. CCR bit 3 may be a 0 or a 1.
SICR
o
.HI.
'ECHO
-Echo Mode Enable.
Disable Echo mode .(enable'normal operation).
e:nable Echo mode. Rec.eived data (RxD) is routed
back through the transmitter to TxD. The contents of
the TxFIFO i.s undisturbed. This mode may be used
for remote test. purposes.
SICR
o
.!.
RESET
SICR
SISR
~
,-Not used. These bits an,! initialized to 0 by
and must not be set to 1.
5-3
DSRT
-Data Set Ready Transl,tlon Status.
DSR has tralisltioned negative (from inactive to . active).
DSR has. not transi.tioned negative.
NRZI
Reset value =$00
2-182
-NRZI Data Format Select. Selects the
transmit and receive data format to be NRZ
or NRZI.
Select NRZdata fOrmat. NRZ coding-high: 1 and
low: O.
Select NRZI data format. The serial data remains in
the same state to send a binary 1 and switches to the
opposite state to send a binary O. A ,1 bit delay is added
'to the TxD output to allow for encoding.
NRZI
'Multi-PrOto~()1 Communication.: Controller (MPCG)
R66560
~T~~TT3i '1'10 I
Protocol Select Reglater 2 (PSR2)
I'
I
1
6
4
3
5
WD/BYT STOP BIT SEL CHAR LEN SEL
SB2
I SBI
I OI-l
CL2
2
T'I
PS3
-L PS2..f PSI,
Reset value .. $00
Reset value .. $00
The Serial Interrupt Enable. Register (SIER) contains interrupt
enable bits for the Serial Interface Status Register. When an
interrupt enable bit is set, the IRQ output is asserted when the
corresponding condition occurs as repor:ted in; the SISR.
Protocol Select R,egister 2 (PSR2) selects
cols,
size, the number of stop bits, and word/byte, ,~ode.
pr~t.o.
o
1
CTS IE. ~Clear to Send (CTS) Interrupt Enable.
Disable CTS Interrupt.
'
Enable CTS Interrupt.
o
1
o
.1
"
-Not Used. This bit is initialized to 0 by RES
and must not ,be changed to 1.
PSR2
6-5 STOP BIT SEl
-Number' 'of Stop, Blt& SeleCt.
Selects the numbElr' of stop bits
transmitted at the end of the dala
bins in ASvNC and ISOC mOdft.
DSR IE
-Data Set Ready (DSR) Interrupt Enable.
Disable DSR Interrupt.
Enable DSR Interrupt.
SIER
~ DCD IE
.', " No. ofSto!;! Blta
ASYNC
ISOC
1
1
1-1/2, '
2
2
2
5
6
SB2
-Data Carrier Detect (OeD)' Interrupt
Enable.
'Disable DCD Interrupt.
Enable DCP Interrupt.
SB1
0
0
0
1
0
SIER
-Not used.
4-0
PSR2
4-3 CHAR lEN SEl "-Character length Select. Selects
tile character length except in BOP
arid esc where the character length
is always eight bits. Parity is not
inch,lded in the character length.
GLOBAL REGISTERS
The global registers contain command information applying to
different mOdes of operation and protOCOls. After changing global
register data, TRES in the TCA and RRES in the RCR should
be set then cleared prior to performing normal mode processing.
Protocol Select Register 1 (PSR1)
4
3
CL2
Cll
0
0
0
Reset value .. $00
Protocol Select Register 1 (PSR1) selects BOP protocol related
options.
.,
7-2
-Not used.
PSR1
~
o
1
CTlEX
-Control Field Extend (BOP only).
Select S-bit control field.
Select 16-bit control field.
PSR1
Jl
o
1
0,
1
Character Length
5 bits
6 bits
7 bits'
8 bits
PSR2
2'() PROTOCOL SEl-Protocol Select. Selects .protocol
and defines the protoc;ol dependsAt
control bits.
'
PSR1
ADDEX
.-Address Extend (BOP only).
Disable address extension. All eight bits of the
address byte a[e utilized for addressing.
Enable address extension. When bit 0 in the addresll
byte is a 0 the address field is extended by one byte.
An exception to the addr8!ls field extension .occurs
when the first address byte is all O's (null address).
2
PS3
"1
'PS2'
PS1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
0
1
0
2·183
,fl'
,
-
L
SIER
.§.
ch~raci~r
,
PSR2
SI~R
L
I ,0
PROTOCOL SEl
ProtOCol
BOP(F.'rimary)
BOP (Sec()ndaiy)
Reserved
COP,BSC EBCDIC
BSC ASCII
ASVNC
ISOC
Nlulti~PF()t()col
865560
The Baud Aate Divider (BRD) value can be computed for other
crystal frequency, prescaler divider and desired baud rate values.
as follows;
Address Register 1 (AR1),
1.
lal.5 I
'1
..
Reset value
o
4
3
2
. Bap AI;>DRESSlBSC& COP PAD
,
,
= $00
BAD = Crystal Frequency
(Prescaler Divider) (Baud Rate) (K)
Mdress Register 2 (AR2)
=
K = 1 for isochronous or synchronous
where:
-r"
01
t
BOP ADDRESSIBSC & COP SYN
!'leeet value
Comrn,mications Controller (MPCC)
. '2 for asynchronous
.
Clock ContrOl Aeglster (CCR)
$00
7
The protocolselected in PSA2 (BOP ,BSC IUld COP only) determin!,!s the function of the two S-bit Address Aegisters (AA1 and
As a secondary station in BOP; the contents of the address
f!lllisters .are. used., for-address matchingde~nding on the
2 ADCMP seleption il'1 the.RCR. In BSC and COP, AA1 and AR2
C9lltllin programmable leading PAD and programmable SYN
c~racters, respectively.,
a
.- -
5
~
PSCDIV
-
3
2
TelKO
R9L.KIN
AR2r
1
10
ClK SEl
CK2
I CK1
Reset value = $00
The CCR selects various clock options.
CCR
,
7-5
Address Aeglster (AR) Contents
:··Pmtocol Selected
AR1
'AR2
X
~
0
1
X
.X
X
AQdress
Address
. Leading PAD
leadingPAO
lllading PAD
X
X
: .. ·2ADCMP
!30P (Primary)
sOP (SecondarY)
BSCEBCDIC
SSCASCII
COP
-Not
used.
CCR
.!.
Address
SYN
SYN
SYN
o
1
oJ( - Not uSee!
PSCDIV
-Presealer Divld,,; ThePrescaler Divider
n~ork reduces the:externalloscillator frequency to a value for use by the internal
Baud Rate Generator.
Divide by 2.
Divide by 3.
CCR
.I:
7
I al
...
Reset value • $01
5
4
3
o
o
2
1
BAUD RATE DIVIDER (lSH)
CCR
.t
Baud Rate Divider Regiater 2 (BRDR2)
I
7
I
a
t
5
I
4
I
3
I
2
1.
o
o
1
BAUD RATE DIVIDER (MSH)
Reset value. =
TCI.KO ,..,.,..Transmlner Clock Output Select.· .
Select TxC to be an· input.
Selee! TxC to be an output.
RClKIN
-R.ecelver Clock Internal Select (ASYNC
only).
. '.
Select External AxC.
Select Internal Rxe.
cCR
$00
.1:!!.
The two 8-bit Baud Rate Divider Registers (BRDAl and BADA2)
hold the divisor of the Baud Rate Divider circuit. BADRl contains the least significant half (LSH) and BRDR2 contains the
most significant half (MSH),.With an B.064 MHz EXTAL input,
standard. \)iHates can be ~alected using the combination of
Prescaler Divider (in the CCA) and Baud Rate Divider values
shown inlable 3. For isochronous or. synchronous protocols,
the Baud Rilte pivider value. must be multiplied by two for the
sarile PreSc!lI~r Divider value.
2-184.
ClK DIV
-External Receiver Clock Divider. Selects
the divider,pf the external AxC to dete~mlne
the receive·r data rate.
CK2
O'
CK1
'0'
0
1
1
1
0
Divider
1 (ISOC)
16
32
64
R65560
Multi';Protocbl Communications CC)ntrolier (MPCC)
Tole 3. Standard Baud Selection (8.064 MHz Crystal)
Baud RIde Divider
P_ler DIvIder
DesIred
Decimal
Value
PSCDIV
(0 to 1)
~Iinal
3
2
3
2
3
2
3
2
2
2
3
2
3
3
3
1
0
1
0
1
0
1
?6,\180
,50
75
110
135
150
300
1200
1800
2400
3800
4800
7200
9600
19200
38400
Value
BADR2
(MSH)
69
69
2F
3A
0
0
1
0
liao
03
02,
01
01 '
1
1
1
140
70
35
00
00
00
0
7
6
5
PAREN
OOOPAR
'4
- -
CRCCTL
o
1
04
04
2
1
CRCPRE
.'
I
02
02
5F
74
46
34
08
06
06
5~
02
560
280
140
70
02
sO
01
00
18
8C
46
60
48
30
18
18
8C
46
23
o
'CRCSEL
C~rCR1
I
BRDRl
(LSH)
00
00
74
AA
00'
80
CO,
CO
90
80
04
30
00
CFCRC ,...:control Field CRC Enable. "
Disable control field CRC, Enables an intermediate
CRC remainder to be appended after the add~esslcon.
trol field in transmitted BOP fr~mes an!1"check~ in
,received frames, The ,CRCgenerator is r~ after con·
trol field CFlC calculation.
'
ECR,
, ','
2 CRCPRE -CRC Generator PresetSelect.
'0'
Preset CRC Generator ,to O.
1
Pre!let CRP Generator to 1 and transmit the .1's complein,entof the r~ulting remainder. '
.'
-Pal'ltY J!n~. (ASYNC, I~OC. and..cOP
only).
'
,
'
.Disable parity generation/checking.
Enable parity generation/checking.
PAREN
ECR
.
.Hl CRC~EL -CRC pOly~omlal Select. Seleclaone of the
RCpolynomfnal~.
1
.!. ODDP",.
ECR
5-4
53,760
53,760
24,436
29,866
17,920
13,440
2,240
2,240
1,680
1,120
fl9
.!.
0
ECR
o
00
65
00
40
lA
The Error Conttol Register (ECR) sel~s the error detection
method used by the MPCC.
J;CR,'
BRDM
(MSH)
ECR
'3
Reset value = $04
DecImal
Value
SA
23
Error Control Register (ECR)
BRDR1
(LSH)
00
26,880
12;218
14,933
8,960
,6,720
1,120
1,1~
840
580
260
and Synchronous
Hexadecimal Value
Hexadectmal "Valua
BaUd Rate
(Btl Rate)
:r.
I8ochro~us
Asynchl'!)noue
-Odd/Even parity ,Select (Effec,tive, Clnly
when PAREN = 1).
Generate/check even !)Wlty.
Generate/check odd parity.
'
0
CR2 CR1
o
0
o
1
1
,1
0,
~Po~ILy~np~.m~,t~n~a~I~______________~
X1B+)(12+xS+l (CCITT V.4l)
X16+Xl~+X2+ fCCRC-16)
xii + 1
Not used.
(VRC/LRC)'
'VRC: Odd-p8ri~ehliekis performed on each
character including the LRC character.
.,...Notusecl.
2-185
"'"
',.',',
,.,,'"
."".'
..
' "
Multi-Pr~tocol'Communications
R65560
INPUT/OUTPUT FUNCTIONS
MPUINTERFACE
Transfer of data between ,the MPCC and the system bus invalves :
the following signals: Address lines AO through A4, Data Bus Lines
DO through 07, and cbntrol signals consisting of RiW, CS, anct
02. Figures 1() anp 11 show typical interf~ce connections.
ReadlWrlte Operation
The RiW input controls the direction of data flow on the data bus.
CS (Chip Select) enables the MPCC for access to the internal
registers arid 9ther operation!!. When CS is asserted, the data,'
1/0 buffer acts as arI- output driver during a read operation and
'.,
as an input buffer during a_ write operation.
When the MPCC is selected (CS low) during a re8d (RiW high),
eight \)its of register data are plac~d on data bus lines DO - 07
when 02 is asserted. When the MPCC is selected (CS low) for
low), 02 strobes data from the DO - D7 data lines
a write
into the selected regi$ter. Figures 12 and 13 show the read anp
write timing relationships.
(RiW
DMA INTERFACE
The MPCCis capable of providing DMA data transfers up to
2 Mbytes per ,second when used w,ith the, MC68440 DMAC ii)"thl'
s!ngle address mQde. Based on: 4 ~b/s serial datar~te and'5
bits/Character, the maximum DMA required transfer rate is8OQ-KbYtes per second._
The MPCC has separate DMA enable bits for the transmitter and
receiver, each of which requires a DMA channel. Both the
transmitter and receiver data are impliCitly addressed (TDR or
RDR) therefore addressing of ihe data register is not required
before data may be transferred. CommUnication between the
MPCC and the' DMAC is aCC(lrilplished by a two-signal
request/acknowledge handshake. Since the MPCC has only one
acknowledge, input (DACK) for itS
DMA request lines, an
external OR function must be provided to c6rilbini:! the two DMA
-acknowledge signals. The, MPCC uses the, RiW input, to
distinguish between the Transmitter Daia. ,!)ervice R!! the data bus during ~2. The memory latches
the data to complete the data transfer. Figure 13 shows the timing
relationships for the receiver DMA mode.
,
Controller (MPCC)
, ROSR is inhibited when either RDSREN is reset to 0 or RRES
is set to 1 (both in the RCR), or When RES Is asserted.
Transmitter DMA ,Mode
The transmitter DMA mode is enabl99 when the TDSREt)I bit in
the rCR is set to 1. When the TxFIFO is available, TranSl)1itter
Data Service Request (TOSR) i$ asserted for one transmillerclock
period to initiate the memory to MPCC OMA transfer., The next
TDSR ,cycle may be initiated as soon as the current TOSR cycle
is completed.
In the transmitter OMA mode, the TxFIFO Is implicitly addressed.
Thans, when the transfer is from memory to the TxFIFO, only
the -memory is addressed. In response to rOSR assertion, the
DMAc setS the RiW line to read and asserts the memory address,
DMf\transfer strobe (DTS) and OMA acknowledge (DACK). The
The ,memory places data on the data bus and the MPCC loads
the' ~ata into the TxFIFO to complete the data transfer. A timing
diagram for, the tr/ilnsmitter DMA mode is,shown in Figure 15.
TDSR is inhibited when either TDSREN is reset to 0 or TRES
is set to 1 (both in the TCR), or when RES is asserted.
DONE Signal
When theOMA transfe~ c~ ~x~austed in transmitt~r DMA
mode, the,OMAC,asserts DONE Which sets the TLAST bitin the
TeR to.liidicate-that the last wordlbyt&has,been trailsferfed. In
the receiver DMA m9Qe, DONE i~ asserted by the MPCCwhen
the last character of the framelblock is being trans!erre4from the
RxFIFO to the data bus if the DONEEN bit is set to a 1 in the RCA.
INTERRUPTS
There are three possible sources of an interrupt request (IRQ):
the receiver section (as reported in thE! RSR), the transmiuer
section (as reported in the TSRj. ancfthe serial interface(es
reported in the SISR). When an interrupt generating stat,us occurs
and the interrupt is enabled by"a corresponding bit in tlie
associated interrupt eriabl~'regiSter, IRO is asserted. The inter-I
rupt proceSSing software must examine all status registers that
have interrupt status bitS enabled to determine the cause of the
Interr!:!E!.,.and perfOml the required processing to clear tile interrupt. IRO will remain asserted' until all interrupt causing conditions reported in status registers have been cleared.
SERIAL INTERFACE
The MPCC is a high speed. high perfprmance device supporting
the more popular bit and characte-r oriented data protocols. The
lower speed aSynchre:>nous (ASYNC) and isochronous (ISOCH)
modes are als,o supported. An on-chip clock oscillator and baud
rate generator provide an output data clock at a frequency of ,DC
to 4 MHz. The clock can also be used in the ASYNC mode to
provide a receive clock for the incoming data. The serial interface ce:>nsists of the following signals:
Multi-Protocol Communications Controller (MPCC)
R6S560
RTS (Request to Send) Output
TxD (Transmitted Data) Output
The RTS output to the DCE is controlled by the RTSLVL bit in
the SICR in conjunction with the state of the transmitter section. When the RTSLVL bit is set to 1, the FiTS output Is asserted.
When the RTSLVL bit Is reset to 0, the RTS output remains
asserted until the TxFIFO becomes emptY or the end of the
message (or frame), complete with CRC 110delfanY,11a:s been'
transmitted. RTS also is negated when the, RTSLVL bit is reset
during transmitter idle, or when the RES input ,is asserted.
The serial data transmitted from the MPCC is COded in NAZ or
NRZI (Zero complement) data format as selected by the NAZI
control bit in the SICR.
RxD (Received Data) Input
m
The serial data received by the MPCC can be coded in NRZ
or NAZI data format. The MPCC will decode the received data
in accordance with the NAZI COl)lrol bit setting in the SICR.
RxC (Receiver Clock) Input
Therece,iver la,tches data on the negative tranSition of the RxC.
(Clear to Send) Input
The CTS input signal is normally generated by the DCE to indicate whether or not the data set is ready to transmit data. The
CTST bit in the SISR reflects, the transition status of the CTS
input while the CTSLVL bit in the SISR reflects the current level.
A positive transition on the CTS pin asserts IRQ if the CTS IE bit
In the SIER is set. The CTS input in an inactive state disables
the start of transmission.
Serial Interface Timing
The timing for the serial interface clock and data lines is shown
in Figure 16. The MPCC supports high speed synchronous
operatio". As shown, the TxD outpu(changes with the negativegoing edge of TxC and the received dalaon RxD is latched on
the negative edge of RxC. This assures high speed two:.way
operation between two MPCCs connected as shown in
Figure 18.
DCD (Data Carrier Detect) Input
The DCD input signal is normally generated bY the DCE and indicates that the DCE is receiving a data carrier signal suitable for
demodulation. The DCDT bit in the SISR reports the transition
status of the DCD input while the DCD,LVL bit'in the SISR contains the current level. A positive transition on the DCD pin
asserts the IRQ output if the DCD IE bit in the SIER is set.
A negated OCD input disables the start of the receiver.
For 10Yf speed ope~atjon between the, MPCC and a modem or
RS-232C Data Communications Equipment (DCE), an inverter
can be used in the TxC output lines as shown in Figure 18.
RS-232 and RS-42S,(coveringserial data interface up to 100K
baud) require that data be centered ±25% about the negativegoing edge of the AxC. This criteria is met for frequencies up
to 1.25 MHz using the invertef. Use of the inverter also allows
MPCC to MPCC operation up to 2.17 MHz.
D$R (Data Set Ready) InputJRSYN Output
SERiAL COMMUNICATION MODES
AND PROTOCOLS
The DSR input from the DCE indicates the status of the local data
set. The DSRT bit in the SISR contains the transition status of the
DSR input whilB the DSRLVL bit in the SISR reports the current
level. A negative transition on the DSR pin asserts the IRQ output if the DSR IE bit in the SIER is set. "
'
ASYNCHRONOUS AND ISOCHRONOUS MODES
Asynchronous' and lsoc"ronous data are transferred in frames.
Each frame consists of a start bit, 5 to 8 data bits plus optional
even or odd parity, and 1, 1Yz, or 2 stop bits. The data character
is tr~.smltted ,with the, least siqnific~t bit (LSB) first. The, data
line is normally heldhigh,(MARK) ~etween frames, however, a
BREAK (minimutl) of one fram~ length for whi,ch the line I!! held
low) il! us~ for control purposes. Figure 4 iIII!s,!rates the .frame
format supported by t~e,MPCC.,
,
When the RSYN bit In the RCR is set to 1, the frame s~ronlza
tion Signal (RSYN)in the receiver is output on the DSR pin~ In
this mode, DSR oUtput low indicates detection of SYN in BSC
or COP, or an address match in BOP.
D'fR (Data Terminal
Ready) Output
Asynchr()rious 'Receive
The DTA output is general purpose in nature,alid ,can be used
to control switching oftheDCE. The DTR output is controlled Ily
the DTRLVL bit in the SICA.
'
TxC rrran~mitter Clock)"lnputJOutput'
•
In the asynchronous (ASYNC) mode, data received on RxD
occurs in three phases: (1) det~lol1of the start bit and bit
synchronization,(2)charac;ter, !lssernbly and op~ional ,parity
cheek, and (3) stoP,Qit (letEK:tion:The reeeiY$! bit I!tream, may
be synchronized by'the inter.,al baud' rate g'enE\rator clock or
by an el\lerl1al'clockon'~C. When RCLKINin the CCR is set
to Q, ali external clock with a frequency of 16, 32; or 64 times
the data rate establishes the data bit midpoint and maintains
bit synchronization. The character· assembly process does not
start if the start bit is less than one-half bit tirlle. Framing and
parity errors are detected and, buffered along with the character
on which ermrs QCcurred. They are pllSSed on to the ~xFIFO
and set appropriate status bits in the,RSR when the character
with an error re,aches the last RxFIFO register where it is ready
to be transferred onto the data bus via the RDR;
I. •
Thetransmittsr clock (TxC) may be programmed to be input or
ali output. When the TCLKO control bit in the CCR ,is set toa
1, the TxC pinbe~mes an output and pl'ovides:the DCE with
a clock whose frequency is determined by the internal baud rate
generator. When the TCLKO control bit is reset, TxC is: an input
and the transmitter shift timing must b.e provided externally. The
TxD output changes state on the negative-going edge of the
transmitter clock. In the asynchronous modewhenTCLKO", 0
in the CCR, the TxC input frequency must be two times the
desired baud rate.
2-187
2
Multi-Protocol CommlJnications Controller (MPCC)
R65560
ASYNCHRONOUS FRAME FORMAt
--,
DATA
I
!-_~
I
...
i--T----r~----,--_r--,.....- I-T-r
I
I
I
I
I I I
I
START
I
_l.. ..... __ ~~ _----l.---L--..J
lBS
I
·IIIIII~I------"--·
I
MSB
.1
I PARITY
(OPT)
I
L...l_ L_ .
STOP
(1, 1v.., OR 2 BITS)
.1
S TO 8.BITS
ISOCHRONOUS FRAME FORMAT
ClK
DATA
I.....
I
,
....
r ...... -l~--~~----.,--:t~I.
"
"
~_~I_ ........ ·---~r---~..J..-..;...-L-:
STARTl
lBS
I
~,.
.
·:1
STO SBITS
MSB
I
..J
I ~~~Y I
STOP
1 OR 2 BITS
.1
Figure 4. Asynchronous and Isochronous Frame Format
Isochronous Receive
BIT ORIENTED PROTOCOLS (BO.P)
In the iso!:hronous (ISOC)mode, ~1 tim~sclock onRxC is
required with the data on RxD and the serial data bit is latched
on the falling edge of each clock pulse. The requirement for the
detection ofa valid start. bit, or the beginning of a break,· is
satisfied by the detection of a high-to-Iow transition on the serial
data input line. Error detection and status indil;ation are the same
as the asynchronous mode.
'
In bit oriented protocols (BOP), messages (data) are transmitted
and received in frames. Each frame contains an opening flag,
address field, control field, frame check sequence, and a closing flag. A frame may also contain an information field. (See
Figure 5).
The opening flag is a special character whose bit pattern is
01111110. It marks the frame boundaries and is the interframe
fill character. The address field of a frame contains the address
o( the secondary station which is receiving or responding to a
command. The address field may be one .or mare bytes long.
The address field can be extended by setting the ADDEX bit
to a 1 in PSR1. In this case, the address field will·be extended
t,lntil the occurrence.of an address byte with a 1 in bit O. Up to
two bytes of the'address field maybe automatically checked
when the MPCC is programmed to be a secondary station in
BOP. An automatic check for global (11111111) or null
(00000000) address is alsO made. The control field of one or two
bytes is transparent to the MPCC and sent directly to the host
without interpretation .
Asynchronous and Isochronous Transmit
In asynchronous and isocl'!ronous transmit mOdes, output data
tansmission on .TxD begins with the start bit. This is followed
by the data character which i!l. transmitted LSB first. If parity
generation is enabled, the parity bit is transmitted after the MSB
of the character. .
.
SYNCHRONOUS MODES
In synchronous modes; a one-times clock is provided along with
the data. Serial output data is shifted out and input data is latched
. on the falling edge of the clock.
2-188
Multi.:.Protocol Communications Controller (MPCC)
R65S60
The optional information field consistS of 8-bit oharacters. Cyclic
redundancy checking is, uSed for error detection and the.CRC
remainder resulting from the calculation is transmitted as the
frame .check sequence field. For BOP, the polynomial X16 +
X12 + X5 + 1 (CRC-CCIn) should be used,i.e., selected in
theCRC SEL bits in the ECR. The registers representing the
CRC-CCITT polynomial are generally preset to allls, and the
ls complement of the resulting remainder is transmitted. (See
X.25 Recommendation.)
at the close of a frame and the C/PERR bit in the RSR is updated.
The FCS and the Flag are not passed onto the RxFIFO.
If the Flag is a closing flag, checks for short frame (no control
field) and CRC error conditions are made and the appropriate
status is updated. When an Abort (seven lS) is detected, the
remaining frame is discarded and the FAtB bit is set in the RSR.
When a link Idle (15 or more consecutive 1S) is detected, the
RIOLE status bit is set in the RSR. The zeros that have been
inserted to distinguish data from special characters are detected
and deleted from the data stream before characters are assembled. The MPCC programmed as a secondary station provides
automatic address matchi!1S!, of up to two bytes. If there is no
address matCh, the receiver (secondary station) ignoreS the
remainder of the frame by searching for the Flag. If there is a
match, the address bytes are transferred to the RxFIFO as they
are assembled.
Zero insertion/deletion is employed to prevent valid frame data
from being confused with the special characters. A 0 is inserted
by the transmitter after every fifth consecutive 1 in the data
stream. These inserted zeros are removed by the receiver to
restore the data to its original form. The inserted zeros are not
includ.ed in the CRC calculation.
The end of the frame is determined by the detection of the
closing Flag special character which is the same is the opening
Flag.
For the control field, one or two bytes are assembled and passed
on to the RxFIFO depending on the state of the extended control
field bit.
With the control options offered by the MPCC, commony used
bit oriented protocols such as SOLC, HOLC and X.25 standards
can be supported. Figure 6 compares the requirements of these
options.
If the CFCRC bit in the ECR is set to 1, an intermediate CRC
check will be made after the address and control field. The Frame
Check Sequence is still 'calculated over the remainder of the
frame.
BOP Receiver Operation
BOP. Transmitter Operation
In BOP, the receiver starts assembling characters and accumulating CRC immediately after the deteCtion of a Flag. The receiver
also continues to search for additional Flag, or Abort, characters
on a bit-by-bit basis. Zero deletion is Implemented in the Receiver
Shift Register after the Flag detection kigic, and before the CRC
circuitry. The receiver recognizes the shared flag (the closing
flag for one frame serves as the opening flag for the next frame)
and the shared zero (the ending 0 of a closing flag serves as
the beginning 0 of an opening flag forming the pattern
"011111.101111,110."
In BOP,the TxFIFO can be prelOaded through theTOR while
the transmitter is disabled (TEN =, 0 in the TCR). When the
transmitter is enabled (TEN .. 1 in the TCR), the leading FLAG
is automatically sent prior to transmitting data from the TxFIFO.
The TORA bit is set to 1 in the TSR as long as TxFIFO is not
full. If an underrunoccurs, the TUNRN bit iii the TSR is set to
a 1 and an ABORT (11111111) is transmitted followed by continuous FLAGSs or marks until a new sequence is initiated.
Character assembly and CRC accumulation are stopped when
a closing Flag or Abort is detected. The CRC accumulation
includes all the charlilqters between the opening Flag and the
closing Flag. The contents of the CRC register are checked
The TLAST bit in the TCR must be set prior to loading the last
character of the message .to signal the transmi,tter to append
the two-byte Frame Check Sequence (FCS) following the last
character. If the transmitter OMA mode is selected (the TOSREN
bit set to 1 in the TCR) the TLAST bit Is set by the DONE signal
from the OMAC.
'
FLAG,
01111110
ADDRESS
lOR N
BYTES
I
Flgure.5.
CONTROL
lOR
2 BYTES
I
INFORMATION
N BYTES
(OPTIONAL)
I
FCS
2 BYTES
FLAG
I
01111110
Bit Ortente.d Protocol.(BOP) Frame Format
IBM SDLS FRAME FORMAT
FLAG
01111110
ADDRESS
1 BYTE
CONTROL
1 BYTE
INFORMATION
NBYUS
FCS
FLAG
2 BYTES
0111~HO
CONTROL
lOR
2 BYTES
INFORMATION
N BYTES
FCS
FLAG
2 BYTES
01111110
ADCCP/HDLC FRAME FORMAT
FLAG
01111110
ADDRESS
NBYTES
Figure 6.
Implemented Bit Oriented Protocol.
2-189
II
Multl';'Protocol Communications Controller (MPCC)
R65560
A message may be terminated at any time by setting the TABT
bit in the TCR to 1. This causes the. transmitter to send an Abort
character followed by the remainder of tlie current frame data
in the TxFIFO.
The serial data from the Transmitter Shift Register is continuously monitored for five consecutive 1s, and aO is inserted in
the data stream each time this conditiOn occurs (excluding Flag
and Abort characters).
CRC accumulation begins with the first non-Flag character and
includes all subsequent characters. The CRC remainder is
transmitted as the FCS fOllowing the last data character. If the
CTLCRC .bit In the ECR is sst to 1, an intermediate CRC
remainder is appended after the Address and Control field. The
final Frame Check Sequence is calculated over the balance of
the frame.
BISYNC casC) ,
The structure of messages utilizing the IBM Binary Synchronous
Communicati!)ns (BSC) protocol, commonly called Bisync, is
shown in Figure 7. The MPCC Can process both transparent and
nontransparent messages using either the EBCDIC or the ASCII
codes. The CRC-16 polynomial should be selected by setting
the appropriate CRCSEL bits in th~ ECR for both transparent
and non-transparent EBCDIC and for transparent ASCII coded
messages. VRC/LRC should be selected for non-transparent
ASCII c(lded mel!Sages~ eSC messages are formlltted using
defined d~-Iink control characters. Data-link control characters
generatediir)d recognized by the Mpcc are listed in. Table 14.
Table 4. BSC Data-Llnk Control Characters
ASCII
Command
SYN
SOH
STX
Byte 1
16·
01
ET8
ETX
EBCDIC
Byte 2
02
17
03
ENQ
OLE
ITB
EOT
ACK N·
NAK
WACK
RVI
0Ii.
10
1F
04
10
15
10
10
30-37
3B
3C
Command
SYN
SOH
Byte 1
Byte 2
32·
-
01
STX
()2
EOB (ETB)
ETX
ENQ
OLE
ITB
EOT
ACKO
ACK 1
NAK
WACK
RVI
26
03
20
10
1F
37
10
10
3D
10
10
1 BYTE
(AR1)
SYN
18YTE
(AR2)
The text. data is tr'an;mitted in ~mplete units called messages,
which are initiated by STX and concluded with ETX. A message
can be subdivided into smaller blocks for ease in processing
and more efficient error control. Each block starts with STX and
ends with ETB (except for,tl1e last block of a message, Which
ends with ETX). A single transmission can contain any number
of blocks (ending with ETB) or messages (ending with ETX). An
EOT following the last ETX block indicates a normal end of
transmission. Message blocking without line' turnaround can be
accomplished by using ITB(see the Additional Data Link
Capabilities section, IBMGA 27-3004-2).
BSC.
Two modes of data transfers are usiKf in
In non·transparent
mode, data link COntrol characters may not appear as text data.
In transparent mode, each control character is preceded by a
data ·link escape (OLE) charscter to differentiate it from the text
data. Table 5 indicates which. control characters are excluded
in the CRC generation. All characters not sh.own in the table are
included in the CRC generation. Figure 8 shows variOusiormats
for Control/Response Blocks and Heading and Text Blocks.
Table 5.
-
-..,..
-
Included In
SYN
Yee
-
TSYN
TSOH
TSTX·
TETB
TETX
TOLE
-
6B
7C
BSC Controf Sequences - Inclusion
In CRC Accumulation
.Character of Sequence
70
61
Note: ·Programmable
LEADING PAD
A heading is a block of data starting with an SOH and containing one or more characters that are used. for. message control
(e.g., message identification, routing, and priOrity). The SOH
initiates the block-check-cliaracter (BCC) accumulation, but is
not included in the accumulation. The heading is terminated by
STX when it is part of a block containing both heading and text.
A block containing only a heading is terminated with an ITB or
an ETB followed by the BCC. Only the first SOH or STX in a
transmission block following a line turnaround·causes the BCC
to reset. All succeeding STX or SOH characters are included
in the BCC. This permits the entire trsnsmission (excluding the
first SOH or STX) to beblock-cliecked.
ETB
ETX
(DLE)DLE
CAe Accumuiatlon
No
DLESYN
DLESOH
DLESTX
DLE
OLE
DLE(DLE)
·If not preceded within the same block by transparent heading
information.
.BODY
1 BYTE
(AR2)
Figure 7. BSC Block Fonnat
Bce
TRAILING
PAD
.'
11111111
:II
CD
UI
UI
CD
CONTROURESPONSE BLOCKS:
o
FOLLOWING PAD
ADDRESS
SYN
POLLING OR SELECTION
SYN
FOLLOWING PAD
ACKO
POSITIVE ACKNOWLEDGEMENT
LEADING
PAD
3:
E.
NEGATIVE ACKNOWLEDGEMENT
' i'
~
"'U
~
HEADING AND TEXT BLOCKS:
RESET BCC
~
ILE::~NGI
SYN
SYN
SOH
-I
INCLUDED IN BCC
""
I
;'
HEA~:NG
I
ETB
BCC
~
IFOLLOw-1
ING PAD
n
o
3
I
I
HEADING ONLY
'I'
RESET BCC
ILEADING
PAD
SYN
SYN
SOH
INCLUDED IN BCC
;
I
HEADING
I
TE~T
STX
I
I
SYN
SYN
DLE
STX
TEXT
SYN
I-
I
DLE
SYN
I
I
c
rlNCLUDED IN B C C - I
I~'
I
I
NONTRANSPARENT HEADING AND TEXT
RESET BCC --rNCLUDE~IN BCCi
LEADING
PAD
3
-I
I
TRANSPARENT TEXT
:
I
~
~
ci"
I
BCC
I
IFOLLow-1
ING PAD
a0'
~
(I)
INCLUDED IN BCC"
IDLE"
-I
I
IFOL~
ETX
BCC
ING PAD
I
I
'DLE EXCLUDED FROM BCC CALCULATION
~
-...2~
i'
'i
"'U
n
Figure 8.
.9
BSC Message Format Examples
II
R65560
Multi-Protocol Communications Controller (MPCC)
BSC Receiver Operation
The message is terminated by the transmission of the BCC
followed by a closing pad when an ErB, ITB, or ETX is fetched
from the TxFIFO. The closing PAD is generated by the MPCC.
Character length defaults to ei!:'lht bits in BSC mode. When ASCII
is selected, the ei!:'lhth bit is used for. parity provided that
VRC/LRC polynomial is selected. Character assembly starts after
the receipt of two consecutive SYN characters. Serial data bits
are shifted through the Receiver Shift Register into the Serialto-Parallel Register and. transferred to the RxFIFO. The ROA
status bit in the RSR is set to 1 each time data is transferred
to the RxFIFO. The SYN character in non-transparent mode and
OLE-SYN pairs in transparent mode are discarded.
In transparent mode, the SCC accumulation is initiated by OLE·
STX and is terminated by the sequences OLE·ETX, OLE-ETB,
or OLE·ITS. See Table 5 for character sequence and inclusion
in CRC accumulation. I·f an underrun occurs, OLE-SYN charac·
ters will be transmitted until new characters are available in the
TxFIFO, ETC, ETX, ITS, or ENO with a TLAST tag is treated
as a control character and the MPCC automatically inserts a OLE
immediately preceding these characters, OLE·ETB, OLE-ETX,
OLE·ITS, or OLE·ENO terminates a block of transparent text,
and returns the data fink to normal mode. BCC generation is
not used. for messages beginning with characters other than
SOH, STX, OLE·SOH, or OLE·STX. On all message types, if the
TSYN bit is set to 1 in the TCR, a SYN·SYN (OLE·SYN sequence
on transparent messages) sequence is transmitted before the
next character is fetched from the TxFIFO.
The receiver starts each block in the non-transparent mode. It
switches to transparent mode if a block begins with a OLE-SOH
or OLE·STX pair. The receiver remains in transparent mode until
a OLE-ITB, OLE-ETB, OLE·ETX or OLE·ENO pair is received.
BCC accumulation begins after an opening SOH, STX, or OLESTX. SYN characters in non-transparent mode. or OLE-SYN pairs
in transparent mode are excluded from the BCC accu~ulation.
The first OLE of a OLE-OLE sequence is not included in the BCC
accumulation and is discarded. TheBCC is checked after receipt
of an ITB, ETB, or ETX in non-transparent mode or OLE·ITB,
OLE·ETB, OLE·ETX in transparent mode. If a CRC error is
detected, the C/PERR and EOF. bits in the RSR are set to 1.
If no error is detected only the EOF bit is set. If the closing
char2
IRQ
-&-::11 C
'" ~I:!:....
»
'I'
~
0
(1 MHz)
~TxO ~
.- TxC ..
RxO
TO MODEM
OROCO
-: RxC
CLOCK
GENERATOR
~
C
--
~
·3
3
c
:::I
(;'
ao·
:::I
In
f)
a
a
...CD
3:
ra
(')
.9
Figure 10. Typical Interface to 6500-Based System
II
lJ
0)
(II
(II
Q)
o
Ao-A15
00-.07
.-----
RIW
r--
r-
p-
f-f--
VMA
MC6800
MPU
iRll
l:II C
~16
....
"-.--
.~<
t
< •
;: T'
• !:
:II
C
T'
C
~ ....
'"
'"j,
~
::looi
:
'"
C
~
~
:hI
~
TXRQO
~
ClK
R
~
MEMORY
01>1
<1>2
MC6844
oMAC
MC6875
CLOCK
GENERATOR
BUS <1>2
oMA REQ
oMA GRANT
t2
TXRQl
OC
<1>2
IRQIDENo
oRQT
TXSTB
oGRNT
TXAKA
.
r-f~
r--D
~
'"
~I
0;>
0
....
R65560
MPCC
t--
....
-
•.
0;>
'i""
"tI
~
.
TDSR
RoSR
·V
!JI
3C
5.
•
()
2(")
TO MODEM
ORoCo
o
3
3
c
.
. DTS
oACK
::::s
n"
::::s
CD
~
3C
"tI
(")
Figure 11.
Typical Interface to 6800-Based System
,g
Multi-Protocol Communications Controller (MPCC)
R65560
AI).A4
II
CS
,2
RtW
01).07
NOTES: TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A.1.9W VOLTAGE OF 0.8 VOLTS AND A
HIGH VOLTAGE OF 2.0 VOLTS. UNLESS OTHERWISE NOTED.
Figure 12. MPCC Read Cycle Timing
AO·A4
CS
00·07
NOTES: TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A
HIGH VOLTAGE OF 2.0 VOLTS. UNLESS OTHERWISE NOTED.
Figure 13.
MPCC Write Cycle Timing
2·195
Multi-Protocol Communications Controller (MPCC)
R65560
INTERNAL
RECEIVER
CLOCK
(BAUD
RATE)
EXTERNALLY
LATCHED
RDSR
DO-D7
\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
IllllIIIIIIIIIII
NOTES: TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH
VOLTAGE OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.
Figure 14.
MPCC to Memory DMA Transfer Cycle Timing (Receiver DMA Mode).
2-196
Multi-PrQtoc.ol Communications Controller (MPCC)
R6556.0
II
INTEAN",L
TA...NSMlTTEA
CLOCK
ASSERT FOR
1 CLOCK CYCLE
EXTERN...LLY
UTCHEO
TDiii
~~
______________~r
DOo07
1OUlnmumllOllOlllmou
\\\\\\\\\\\\\\\
NOTES: TIMING MEASUREMENTS ...RI: REFERENCED 10 ...NO FROM ... LOW VOLTo\GE OF D•• VOLTS -'NO ... HIGH
VOLTo\GE OF 2.0 VOLTS. UNLESS OTHERWISE NOTEO.
FlglJre 15. Memory to MPCC DMA Transfer Cycle Timing (Transmitter DMA Mode).
2·197
Multi.;.Prototol Communications Controller (MPCC)
R65560
HIGH SPEED APPLICATION
~----------(30r---------~
TxC/RxC
DATA
TxD/RxD
B
LOW SPEED APPLICATION (RS·232 COMPATIBLE)
TxC
TxD
DATA A
Figure 16. Serial Interface Timing
RxD
TxD
NOTE: TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH
VOLTAGE OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.
Figure 17.
Serial Interface Echo Mode Timing
2·198
Multi~Protocol
R65560
AC CHARACTERISTICS
01cc = 5.0 Vdc ±5%, Vss = 0 Vdc,
Number
TA
Communications Controller (MPCC)
= O°C to 70°C)
Parameter
Min
Max
IAVSl
0
30
OS Low to 02 High
tSL2H
30
-
4
02 High to Data Valid
12HDV
0
140
ns
5
02 Low to Data Invalid
t2lDXA
10
150
ns
6
02 Low 10 RIW Low
12lRl
20
-
ns
1
2
Address Valid 10
3
Symbol
R/W High 10 02 High
IRH2H
CS Low
-
Unit
ns
ns
ns
7
02 Low to Address Invalid
12LAI
20
8
R/W Low to 02 High
IRl2H
0
9
Data Valid to 02 Low
tOV2L
60
10
02 Low 10 Data Invalid
t2lDXW
11
02 Low tei R/W High
t2LRH
20
15
DACK Low to 02 High
tAl2H
125
16
02 Low to DAOK High
t2LAH
65
17
DTS Low to 02 Low
tSL2l
60
-
ns
18
DACK Low to Data Valid, DONE Low
tALDV
19
02 Low 10 Data Invalid
12LDXDR
20
DACK, DONE Low to 02 High
21
0
-
ns
ns
ns
ns
ns
ns
ns
0
140
ns
10
150
ns
tAl2H
125
-
ns
Data Valid to 02 Low
tOV2L
60
-
ns
22
02 Low to Dala Invalid
t2LOXDW
23
02 Low to DACK, DONE High
t2lDH
30
RxC and TxO Period
tcp
31
TxC Low to TxD Delay
tTClTO
0
200
ns
32
RxO Low 10 RxD Transition (Hold)
IRCLRO
0
-
ns
33
RxD Transition 10 RxC Low (Selup)
IRDRCl
30
-
ns
34
RxD 10 TxD Delay (Echo Mode)
IROTD
-
200
ns
0
65
248
-
ns
ns
ns
MDCC1
MPCC2
MPCC 1
MODEM/DCE
TxC
RxC
TxC
TxD
RxD
TxD
Rx DATA (BB)
RxC
TxC
RxC
Tx TIMING (DA)
RxD
TxD
RxD
Tx DATA (BA)
-t>o-
Rx TIMING (DO)
LOW SPEED (RS·232) INTERFACE
HIGH SPEED INTERFACE
Figure 18. Serial Interface
2-199
II
Multi-Protocol Communications Controller (MPCC)
R65560
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Value
Supply Voltage
Vee
-0.3 to +7.0
V
Input Voltage
VIN
-0.3 to + 7.0
V
Operating Temperature
TA
Oto + 70
·C
-55 to + 150
·C
Storage Temperature
TSTG
'NOTE: Stresses above those· listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the 'device.
This is a stress rating only and functional operation of the device
at these Or any other conditions above those indicated in other
sections. of this document is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Unit
THERMAL CHARACTERISTICS
Parameter
Symbol
Thermal Resistance
Ceramic
Plastic
8JA
Value
Rating
·CIW
50
68
OPERATING CONDITIO,NS
Paramete(
Range
5,OV ±5%
Vee Power Supply
Operating Temperature
O·Cto 70·C
DC CHARACTERISTICS
(yee
= 5,0 Vdc
±5%, Vss
=0
Vdc, TA
= O·C to 70·C
unless otherwise noted)
Symbol
Min
Max
Unit
Input High Voltage
Afllnputs
VIH
+2,0
Vee
V
Input low Voltage
All Inputs
VIL
-0.3
+0.8
V
Input leakage Current
RiW, RES,CS
liN
-
10.0
pA
VIN = 0 to 5.25V
Vee = 0
Three-State (Off State) Input Current
IRQ, DO-D7
TTSI
-
10,0
pA
VIN = 0.4 to 2.4V
Vee = 5.0V
Output High Voltage
ROSR, TOSR, IRQ, 00-07, DSR, OTR, RTS,
TxD, TxC
VOH
Vss + 2.4
-
V
Vee = 4.75V
ILOAD = - 400pA,
CLOAD = 130 pF
VOH
Vss + 2.4
-
V
Vee = 4.75V
ILOAD = 0
ClOAO = 30 pF
0.5
V
Vee = 4.75V
ILOAD = 3.2 rnA
Parameter
BCLK
Output low Volta£!!..
ROSR, TOSR, IRQ, 00-07, DSR, DTR, RTS,
TxD, TxC, BClK
VOL
-
Test Conditions
Vee = 4.75Y
ILOAD = 8.8 rnA
DONE
= 25·C
Internal Power Dissipation
PINT
-
1
W
TA
Input Capacitance
CIN
-
13
pF
VIN = OV
TA = 25·C
1= 1 MHz
2-200
R65560
Multi-Protocol Communications Controller CMPCC)
PACKAGE DIMENSIONS
4D-PIN CERAMIC DIP
. . 1iIu.uIETE...
b~
.Jl
I---~----tl
~F
J .
i~ IlnHIIIIIIIIIIIR1~fI
JL
D
I:EJJGI~_ ~~J
\K
-l
L----l
~
INCHES
blM
MIN
MAX
.IN
MAX
A
50.29
51.58
1.980
2.030
B
0.580. :0.610
14.73
15.49
C
1.78
3.05
0.010
0.120'
D
0.38
0.58
0.015
0.023
F
1.02
1.65
0.040
0.065
G
2.29
2.80
0.090
0.110
J
0.20
0.38
0:008
0.015
K
3..18
3.81
0.125
0,150
L
14.99
16.51
0.590
0.850
M
~ (J'
10"
0"
N
o.s8
1.78 0.020
10"
0.010
M
4D-PIN PLASTIC DIP
IllLUMETE.RS
Max
DIll MIN
2-201
INCHES
MAX
111M
A
51.28
52.32
2.040
2.060
•
13.72
14.22
0.540
0580
C
3.55
5.08
0.140
0.200
D"
0.38
0.51
0.Q14
0.020
F
un
1.52
o.~
0.060
Q
2.548SC
"
Q.100esc
1.65
2.18
0.0115
0,_
01
0.20
0.30 0.008
0.012
K
3.05
3.se
L
15.24
i
sse
..
7"
10"
N
0.51
1.~
O,1ao
0.800
0.140
esc
r
10'
0.020
0.040
II
R65C02. R65C1 02. R65C112
'1'
Rockwell
R65C02, R65C102, AND R65C112
R65COO MICROPROCESSORS ,(CPU)
DESCRIPTION.
FEATURES
The 8-blt R65COO microprocessor family of devices are produced using CMOS Silicon gate technology which proviqe$
advanced system architeCture for performance speed and system
cost-effectiveness enhancements over their NMOS counterparts, the R65CO family of microprocessor devices.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Three CPU devices are available. All are software-compatible
and provide 64Kbytes of addressable memory, interrupt input,
and on-chip clock oscillators and drivers options. All are buscompatible with the NMOS R6500 family devices.
The CMOS family includes two microprocessors (R65C02 and
R65C102) with on-boardclook oscillators and drivers and one
microprocesSor (R6SC112) driven by extemal clocks. The onchip clockvereions are aimed at high performance, low-cost
applications where single phase inputs, crystal or RC inputs
provide the time 1;18$&. The slave processor version is geared
for multiprocessor system applications where maximum timing
control is manda10ry. All fl65COO microprocessors are available
in ceramic and plastic packaging, operating frequency of 1 MHz,
2 MHz, 3 MHz and 4 MHz, and commerCial and industrial
temperature versions. All three devices are housed in 40-pin
packages.
ENHANCEMENTS OVER R6502
The CMOS family of microprocessor devices has been designed
with many enhancements over the R6502 NMOS device while
maintaining software compatibility. Besides the increased speed
and lower power consumption inherent in CMOS technology,
the R65COO family has added the following characteristics.
•
•
•
•
•
12 new instructions for a total of 68
59 new op codes, for a total of 210
Two new addressing modes
Seven software/operational enhancements
Two hardware enhancements
CMOS silicon gate technology
Low Power (4mNMHz)
Software compatible with R6502
Single 5V +5% power supply requirements
Eight bit parallel prOcessing
Decimal and binary arithmetic
True indexing capability
Programmable stack pointer
Interrupt capability
Non-maskable interrupt
Eight-bit bidirectional data bus
Addressable memory range of up to 64K bytes
"Ready" inpUt
Direct memory access (DMA) capability
Memory lock output
1 MHz, 2 MHz, 3 MHz, and 4 MHz versions
Choice of external or on-chip clocks
On-chip clock options
-External single clock input
-Direct crystal input (+ 4)
• Commercial and industrial temperature versions
• Pipeline architecture
• Slave processor version (R65C112)
ORDERING INFORMATION
r
Part Number:
R65C02 __ _
R65C102 __ _
R65C112
Temp. Re,.. (T,IO T..J
Blank = O°C to + 70°C
E = -40"C to +65°C
Frequency Range
1=1MHz
2=2MHz
3 = 3 MHz
4=4MHz
.
~Package
C = Ceramic
P = Plastic
Document No_ 29651N52
Product Description Order No. 2149
Rev. 2, February 1984
2-202
R65COO Mlcroprocetaora. (CPU)
R65C02, R65C102, and R65C112
FUNCTIONAL DESCRIPTION
With the exception of a ci'ystal osclliator, clock signals, Memory
Latch (MI.), and Bus Enable (BE) sIgnals, the internal architecture of the three members of the R65COO CPU of devlc,:es is Identical. Figure 1 shows the block diagram of the R6SCOO CPU
Internal architecture for. all three devices. This blClOk dlagr.m
supports the following text that describes the function of eacn
of the device's major elements.
....-.:- REGISTER SECTION,
CONTROl- SECTION - - - .
iti iFlQNii
l~
r-
AD
A1
A2
AS
A4
AS
AS
A7
ADDRESS
BUS
AS
ItS
A10
A11
A12
A13
A14
... r -
...
...
...
....
....
....
....
J
X.
ABL
~9
-
~
'4
E
INDEX
REGISTER
STACK
POINT
REGISTER(S)'
RDY
L
t?
SYNC
XTLO(S)
L.---
---
-,....
w
;::::::
~
~
:;;l
I~
i!l
el
Bd
0
L
:z:
ACCUM~LA~l;
~l-
-----
4LU
MLII)
-
m
z
¢::
•
INTERRUPT
LOcalC
y
.... r -
...
...
...
...
E
INDEX
REGISTER
's.
TIMING .\
CONTROL
r-
i!
~
PCL
C=r-~
PCH
~
~
ABH
A15 4 - -
----:
9
t~ INPUT
DATA ~
LATCH (DL)
,PROCESSOR
STATUS
REGISTER P
1
IG~~~RFIN"
~"'OU
'20U
'10UT(1
.........
'-
.
DATA BUS
BUFFER
'0
}::O ....
.~
INSTRUCTION
REcalSTER
t f.
l'
1.
NOTES:
(1) R65C02 ONLY
(2) R65C02, R65C1 02 ONLY
(3) R65C102 ONLY
(4) R65C112 ONLY
(5) R65C102, R65C112 ONLY
I
II
DO
D1
D2
D3
D4
D5
De
Figure 1. R65COO Internal Architecture
SO
AiW
BE(4)
D7
2-203
2IN(4)
.LEGEND:
DATA
BUS
11'8
t
BIT LINE
SIN caLE LINE
R65C02,' R65C10.2, and R65C112
R65COO Microprocessors (CPU)
and modifies the address by adding·the index register to' it prior
CRYSTAL OSCILLATOR (R65C102 Only)
to performing .the desired operation. Pre- or. post-indexing, of
The crystal Oscillator, driven by a crystal across XTlO and XTAI,
divides the crystal frequency by four to provide the basic 02
clock signal that drives the internal clock generator.
indirect addresses is possible (~ee addressing modes).
STACK POINTER
The stack pointer is an' a-bit register used to control the
addressing of the variable-length stack on page one. The stack
pointer is autoriiatically incremented and decremented under
control of the microprocessor to perform stack manipulations
under direction of either the program or interrupts (NMI and
IRQ). The stack allows simple implementation of nested subroutinesi!nd multiple level interrupts. The stack pointer shOUld
be initialized before any interrupts or stack operations occur.
CLOCK GENERATOR
The clock generator develops all intemalclock signals, and
(where applicable) external clock signals, aSSOCiated with the
device. It is the .clock generator that dri.ves the timing control'
unit and the external timing for slave mode operations.
TIMING CONTROL
The timing control unit keeps track of the instruction cycle being
monitored. The unit is set to zero each time an.instruction fetch
is executed and is advanced at the beginning of each phase
one clock pulse for as many cycles .as is required to complete
the instruction. Each data transfer which takes place between
·the registers depends upon decoding the contents of both the
instruction register and the timing control unit.
PROCESSOR STATUS REGISTER
The 8~bit processor status register contains seven status flags.
Some of the flags are controlled by the program, others may be
.Controlled both by the program and the CPU. The R6SCOO
instruction set contains a number of conditional branch instruct.ions which are designed to allow testing of these flags.
.
0.
1;
,
HA,RDWARE ENHANCEMENTS
PROGRAM COUNTER
The R6SCOO family of CPU devices have incorparated hardware
enhancements over their NMOS counterpart, the' R6502. These
hardware enhancements are:
The 16-bit program counter provides the address.es wl:lich $tap
the microprocessor through sequ&ntlal instructiOns.in a program.
• The NMOS device wO,uld ignore the 8l!sertion of a Ready
(ROy) d4ring write operation. The CMOS family will stop
the processor during 1'2 clock if ROY· is as!!8rted during a
write pperation .
• 0" the NMOS device, unused input-only·pins (IRQ, NMI,
ROY, RES, and SO) must be connected to a low impedance signal to avoid noise problems. These unused pins on
the CMOS devices are internally connected by a high impedance to Vee (approximately 250K ohms).
Each time the microprocessor fetches an instruction from program memory, the lower byte of the program counter (PCl) is
placed on the low-order bits of the address bus and the higher
byte of the program counter (PCH) is placed on the high-order
a pits. The counter is incremented each time an instruction or
data is fetched from program memory.
a
INSTRUCTION REGISTER AND DECODE
Instructions fetched from memory are gated onto the internal
data bOs. These instructions are latched into the instruction register, then decoded, along with timing and interrupt signals, to
generate control si~r,als for the various registers.
MAJOR FEATURES AND DIFFERENCES
The functional aspects of and differences between the microprocesSor cOnfigurations are shown in Table 1.
ARITHMETIC AND LOGIC UNIT (ALU)
Table 1. Family Compariaon Chart
All arithmetic and logic operations take place in the ALU including
incrementing and decrementing internal registers (except the
program counter). The AlU has no internal memory and is used
only to perform logical and transient numerical operations.
Feature
ACCUMULATOR
;
.Pin compatible wnh NMOS R6502
64K addressable bytes of memory
IRQ interrupt
On-chip clock oscillator
EXtemai clock only
TTL level single phase clock input
RC time base clock input
Crystal time base clock input
Single phase clock input
Two phase oiJtput clock
SYNC and ROY signals
Bus Enable (BE) signal
Memory Lock (ML) output signal
Direct Memory Access (DMA) capacity
NMI interrupt signal
The acbumulator is a general purpose 8-bit register that stores
the resutts of most arithmetic and logic operations,. and· in
addition, the accumulator usually contains one of the two data
words used in these operations;
INDEX REGISTERS
There are two a-bit index registers (X and y), which may be
used to count program steps or to provide an index value to be
used in generating an effective aqdress.
When executing an instruction which specifies indexed
addressing, the CPU fetches the op code and the base address,
2-204
s us
i
X
X
X
X
18
II:
X
X
X
~
U
18
II:
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R65C02, . R65C10~, and' R65C112
R65COO.Microprocessors .(CPU)
PIN ASSIGNMENTS
Figure 2 shows the pin assignments fbr the three members of
the R65COO CPU family. All three devices are housed in 4O-pin,
dual-in-line, ceramic or plastic packages.
R65C102
R65C02.
VSS
ROY
RES
'2 (OUT)
VSS
ROY
'1 (OUT)
SO
.!!tOUT)
IRQ
'0 (IN)
IRQ
N.C.
NMI
SYNC
VCC
AD
A1
A2
A3
A4
AS
A6
A7
AS
A9
A1D
A11
N.C.
N.C.
01
02
03
04
All
A1
AZ
A3
A4
AS
A6
A7
A8
00
os
06
07
A1S
A14
A13
A12
VSS
'2 (OUT)
SO
XTLI
BE
XTLO
NMi
SYNC
VCC
V$S
ROY
~.
RES
ML
Rf!i
R65C112·
IRQ
ML
NMI
SYNC
VCC
RJW
DO
01
02
03
04
05
06
07
A1S
A14
A13
.A12
A9
A1D.
A11
VSS
AD
A1
All
A3
A4
AS
A6
A7
A8
A9
A1D
A11
RES
;g.
"(IN)
BE .
N.C.
Rt'ii
DO
01
02
03
D4
05
06
07
A1S
A1.4
A13
A12
VSS
Note: N.C. means no connection (not used)
Figure 2.
Pin Assignments
SIGNAL DESCRIPTIONS
CLOCK SIGNALS (R65C112)
Reference the timing diagrams for the particular device in the
following discussion.
.
All internal clock signals for the R65Ct12 are generated by the
input' clock Signal ~2 (IN). Since this device is intended to be
operated in the slave mode it does riot have internal clock generation, but rather requires the extemal clock~ (IN) from a host
device.
.
CLOCK SIGNALS (R65C02)
ADDRESS BUS (AO·A15)
The R65C02 requires an external f,DO clock. f,DO is a TTL level
input that is used to generate the internal clocks of the R65C02.
Two fuU level oytput clocks are generated by the R65C02. The
~2 clock Is In phase with ~. The ~1 clock output is 180 0 out of
phase with ~. When the input clock Is stopped, the CPU is in
the standby mode.
Ao-A15 forms a 16-bit address bus for memory and va
exchanges on the data bus. The output of each address line is
TTL compatible, capable of driVing one standard TTL load and
130pF.
DATA BUS (QO·D7)
For non-critical timing donfigurations, a simple BC or crystal
network may be straipped between f,DO (IN) and ~1 (OUn.
the data lines (00.07) constitUte an 8-bit bidirectional data bus
used for data exchanges to and from the device and peripherals.
The outputs are tri-state buffers capable of drivi ng one TTL load
and 130pF.
.
CLOCK SIGNALS (R65C102)
The R65C102 internal clocks may be. generated by a TTL level
single phase input, an RC time base input, or a crystal time base
input (+ 4) using the XTLO and XTLI input pins. Two full level
output clocks are generated by the R65C102. The ~2 clock
output provides timing for external R1W operations. Addresses
are valid after the address setup time (tAOS) referenced to the
falling edge of 02 (OUn. The ~4 output is a quadrature output
clock that is delayed from the falling edge of the ~2 clock by
delay time tAVS' Using the ~4 clock, addresses are valid at the
rising edge of 04.
BUS ENABLE (BE)
This signal allows external control 01 the data and the address
output buffers and RNi. For normal ~eration, BE
is high causing the address buffers and RJW to be active
and the data buffers to be active during a write cycle. For external control, BE is held low to disable the buffers; BE is an asynchronous signal am;! therefore not related to, or controlled by
the CPU internal clOck signals.
.
2-205
fI
R65COO Microprocesjors (CPU)
R65C02, R65C102, and R65C112
INTERRUPT REQUEST (IAQ)
This TTL compatible input requests that an interrupt sequenc!l
begin within the microprocessor. The IRO is sampled during 02
operation; if the interrupt flag in the processor status register is
zero, the current instruction is completed and the interrupt
sequence begins during 01. Tile program counter and processor
status register are stored In the. stack. The microprocessor will
then set the interrupt mask flag high so that no further IROs may
occur. At the end of thii!l cycle, the program counter low byte will
be loaded from address FFFE, and program couriter high byte
from location FFFF, thus transferring program control to the'
memory vector .lOcated at these addresses. The ROYslgnar
must be in the high state for any interrupt to be recogniz~d. A
3K ohm external resistor should be used for proper wire OR
operation.
MEMORY LOCK (ML)
In a multiprocessor system, the ML output indicates the need
to defer the rearbitration of thE! next bus cycle to ensl!re the
integrity of read,modify-write instructions. JV1[ goes Jow during
A,SL, OE;C, INC, 'LSR, ROL, ROR, TRB, TSB memoryref9r; encing instructions. This signal Is loW for the modify and write .
cycles.
.
NON-MAS «ABLE INTERRUPT (NMI)
A negative-going edge on this input requests that a non-maskable interrupt sequence be' Qenerated within the microprocessor. The NMI is sampled during 02; the current instruction
is completed and the interrupt sequence begins during'01. The
program counter Is loaded with the interrupt vector from locations FFFA (low byte) andFFFB (high byte), thereby transferring
program control to the non-maskable interrupt routine.
02 in which the ready signal is low. This feature allows microprocessor interfacing with low-s~ memory as well as direct
memory access (OMA).
READIWRITE (RIW)
This Signal is normally in the high state indicating that the
microprocessor is reading data from memory or VO bus. In the
low state the data bus has valid data from the microprocessor'
to be stored at the addressed memory location.
SET OVERFLOW (SO)
A negative transition on this line sets the overflow bit (V) in the
processor status register. The signal is sampled prior to the
leading edge of 02 by the processor control time (tRWS>'
RESET (RES)
This input resets the microprocessor. Reset must be held low
for at least two clock cycles after vcc reaches operating voltage
from a power down. A positive transistion on this pin will then
cause an Initialization sequence to begin. Likewise, after the
system has been operating, a low on this line of at least two
cycles will cease microprocessin~ivity, folloWed by initialization after the positive edge on~S.
When a positive edge is, detected, there is an initialization
sequence lasting six clock cyc~s. Then the interrupt mask flag
is set, the decimal mode is cleared, and the' program counter
is loaded with the restart vector from locations FFFC (low byte)
and FFFO (high byte). This is the start location for program control. This input should be high in normal operation.
SYNCH~ONIZE
(SYNC)
This output line identifies those cycles during which the microprocessor is fetching the instruction operation code COP CODE).
The SYNC line goes high during 01 of an OP CODE fetch and
stays high for the remainder of that cycle. If the ROY line is
pulled low during the 01 clock pulse in which SYNC went high,
the processor will stop in its current state and will remain in the
state until the ROY line goes high. In this manner, the SYNC
signal can be used to control ROY to cause single instruction
execution.
NOTE
Since this interrupt isnon-maskable, another NMI can
occur before the first is finished. Care should be taken
'
when using NMI to avoid this.
READY (ROy)
This input allows the user to slngle-cycle the microprocessor on
all cycles Including write cycles. A negative transition to the low
state, during or coincideot with 01, will halt the microprocessor
with the output address lines reflecting the current address
being fetched. This condition will remain through a subsequent
OPERATIONAL ENHANCEMENTS
Table 2 lists the' operational enhancements that have been
added to the CMOS family of CPU devices and compares the
results with their NMOS R6502 counterpart.
Table 2. CMOS Operational Enhancements
Function
NMOS R8602 Mlcroproce..or
CMOS R65COO Famlly Microprocessor
Indexed addressing across. page bounda/)'.
Extra read of invalid address.
Extra read of last instruction byte.
Execution of invalid op codes.
Some terminate only by reset. Results are
undefined.
All are NOPs (reserved for future use).
Jump indirect, operand = XXFF.
Page address does not increment.
Page address increments and adds one addHional cycle.
Read/modify/write instructions at effective
address.
One read and two write cycles.
Two read and one write cycle.
Decimal flag.
Indeterminate after reset.
Initialized to blna/), mode (0=0) after reset
and interrupts.
Flags after decjmal op8ration.
Invalid N, V and Z flags.
Valid flag adds one additional cycle.
Interrupt after fetch of BRK instruction.
Interrupt vector is loaded, BRK vector is
ignored.
BRK is executed, then interrupt is executed.
2-206
R85COO MlCroprocessOri. (CPU)
fl65CQ2, R85C102, and R65Ct1.2
ADDRESSING MODES
INDEXED ABSOLUTE INDIRECT [(ABS, X)]"
The contents.of the second and third instruction bytes are added
to the X-register. The sixteen-bit result Isa memory address containing the effective address. (JMP'(ABS, X) only)..
The. R65COO CPU family has 15 addressing modes (two more
than the NMOS equivalent family). In the following discussiOn
of these addressing modes, a bracketed expression follows the
. title of the mode. This expression is the term used in the Instruction Set Op COde Matrix table (later in this product description)
to make it easier to identify the actual addressing mcide used
by the instruction.
IMPLIED ADDRe:SSING [lmpllec:J]-ln the implied addressing
mode, the address containing the operand is implicitly stated in
the operation code of the instruction.
.
ACCUMULATOR ADDRESSING [Accum]-This form of addressing is represented with a one byte instruction, implying an
operation on the accumulator.
RELATIVE .ADDRe:SSING [Relatlve]-Relative addressing is
used only with branch instructions and establishes a destination
for the conditional branch.
IMMEDIATE ADDRESSING. [lMMJ-ln immediate addressing,
the second byte of thlil instruction contains the operand, with no
further memory addressing required.
The second byte of tblil instruction becomes the operand which
is an "Offset" added to the contents of the lower eight bits of
the program counter when the counter is set at the next instruction. The range of the offset is -128 to +127 bytes from the
next instruction.
.
ABSOLUTE ADDRESSING [ABS]-In absolute addressing, the
second byte of the instruction specifies the eight low order bits
of the effective address while the third byte specifies the eight
high order bits. Thus the absolute addressing mode allows
access to the entire 64K bytes of addressable memory.
INDEXe:D . INDIRECT ADDRe:SSING [(INO, X)l-In indexed
indirect addressing (referred to as (Indirect, X», the second byte
of the instruction is added to the contents of the X index register,
discarding the carry. The result of this addition points to a
memory location on page zero whose con!ents are the low order
eight bits of the effective address. The next memory location in
page zero contains the high order eight bits of the effective
address. Both memory location~ specifying the high and low
order bytes of the effective address must be in page zero.
ZERO PAGE ADDRESSING [ZP]-The zero page instructions
allow for shorter code and execution times by fetching only the
second byte oUhe instruction and assuming a zero high address
byte, Careful use .of the' zero page can result in significant
increase in code efficiency,
INDIRe:CT. INDEXED ADDRe:SSING [(IND), Y]-In indirect
indexed addressing (referred to as (Indirect), V), the second
byte of the Instruction points to a memory location in page zero.
The contents of this merhpry location are added to the contents
of the V index register, the result being the low order eight bits
of the effective address. The carry from this addition Is added
to the contents of the next page zero memory locatioN, the result
being the high order eight bits of the effective address.
ZERO PAGE INDEXED ADDRESSING [ZP, X or Y]-(X, V
indexing)-This form of addressing is used with the index register and is referred to as "Zero Page, X;' or "Zero Page, V".
The effective address is calculated by adding the second byte
to the contents of the index register. Since this is a form of "Zero
Page" addressing, the content of the second byte references
a location in page zero. Additionally, due to the "Zero Page"
addressing nature of this mOde, no. carry is added to the high
order eight bits of memory and croSSing of page boundaries
does not occur.
ABSOLUTE INDIRECT [(ABS)]-The ~nd byte of the instruction contains the .Iow order eight bits of a memory location. The
high order eight bits of that memory location are contained in
the third pyteof the il!Slructlon. The .contents of the fully specified
memory location are the low order byte of the effective address.
The next memory location contains the /'Iigh order byte of the
effective address whlc;h Is loaded jnto thE! Sixteen bits of the
.
program counter. (JMP CABS) only.)
ABSOLUTE INDEXED ADDRESSING [ABS, X or Y]-(x, V
indexing)--This form of addressing is used in conjunction with
X and V index register and Is referred to as "Absolute, X" and
"Absolute, V". The effective address is formed by adding the
contents of X or V to the address contained in the second and
third bytes of the Instruction. This mode allows the index register
to contain the index ot count value and the instruction to contain
the base address. This type of indexing allows any location referenCing and the index to modify multiple fields, resulting in
. reduced coding and execution time.
INDIRECT [(IND)]*-The second byte of the instruction contains a zero page address serving as the indirect pointer.
NOTE
"These addreSSing modes are not available to the NMOS CPU
family (e.g., the R6502).
2-207
II
R65C02, R6.5C102, and R65C1,2
RE)5COO Microprocessors (CPU)
INSTRUCTION SET
Table 3 lists the instruction set for the CMOS CPU family in
alphabetIC order aecording to mnemonic.· Table' 4 lists the hexadecimal'codesfor each of the instructions that are new to the
CMOS family and were not available in the NMOS R6502 device
Table 3.
(1)
(1)
(2)
(1)
ADC
AND
ASL
Add Memory·to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)
BBR
BBS
Bec
BCS
BEQ
BIT
BMI
BNE
BPL
BRA
BRK
Branch on Bit Reset
Branch on Bit Set
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch
Result Minus .
,
Branch on Result not Zero
Branch en Result Plus
Branch Always
Force Break
Branch on Overflow Clear
Branch on OverfloW Set
BVC
BVS
CLC
CLD
Cli
CLV
(2)
(2)
Alphabetic Listing of. Instruction Set
CMP
CPX
CPY
Mnemonic
Function
MnemoniC
(2)
(2)
family, Table 5 lists those instructions that were available on the
NMOSfamily,but have been assigned new addressing. modes
in the CMOS CPU family.
(2)
(1)
(1)
on
(1)
(1)
(1)
"Clear Carry Flag
Clear Decimal Mod~'
Clear Interrupt Disa,ble Bit
Clear Overflow Flag
Compare Memory and Ac:cumulator
Compare Memory and Index X
Compare Memory and Index Y
(1 )
(2)
DEC
DEX
DEY'
Decrement Memory by One
Decrement Index X by One
Decremel)t Index Y by One
(2)
EOR
"ExclusiVe-OR" Memory with Accumulator
(2)
INC
INX
INY
Increment Memory by One
Increment Index X by One
Increment Index Y by One
(2)
JMP
JSR
Jump to New Location
Jump to New Location Saving Return Address
(2)
LDA
LDX
LDY
LSR
LOad Accumulator with, Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or Accumulator)
(1)
(1)
(1)
NOP
No Operation
ORA
"OR" Memory with Accumlator
PHA
PHP
PHX
PHY
PLA
PLP
PLx
PLY
Push Accumulator .on Stack
Push Processor Status on Stack
PushX Register on Stack
Push Y Register on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack
PUIIX Register from Stack
Pull Y Register from Stack
RMB.
ROL
ROR
RTI
RTS
Fieset Memory Bit
Rotate One Bit Left (Memory or. Accumulator)
Rotate One Bit Right (Memory or Accuml,llator)
Return from Interrupt
Return from Subroutine
SBC
SEC
SED
SEI
5MB
STA
STX
STY
STZ
Subtract Memory from Accumulator with' Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator in Memory
Store Index X in Memory
Store JndexY in Memory
Store Zero
TAX
TAY
TRB
TSB
TSX
TXA
TX5'
TVA
Transfer Accumulator to Index X
Transfer Accumulator to index Y
Test and Reset Bits
Test and Set Bits
Transfer Stack Pointer to Index X
Transfer Index X to Accumulator
Transfer Index X to Stack Register
Transfer Index Y to Accumulator
Notes:
(1) Instruction not available on the NMOS family.
(2) R6502 instruction with additional addreSSing models).
2-208
Function
R65C92, R65C102, endR65C112
Table 4.
Hex
R65COO Microproc.ssors (CPU)
Hexadecimal Codes For New InstructIons In The CMOS Family
Mnemonic
80
3A
1A
DA
SA
FA
7A
BAA
DEC
INC
PHX
PHY
PLX
PLY
9C
STZ
9E
84
74
1C
14
DC
04
89
OF-7Ft"
8F-FF'"
07-17(1)
87-F7'"
STZ
STZ
STZ
TRB
TRB
TSB
TSB
BIT
BBR
BBS
RMB
5MB
Deacrlptlon
Branch relative always [Relative]
Decrement accumulator [Accum]
Increment accumulator [Accum]
PU$h X on stack [Implied!
Push Y on stack [Implied!
. Pull X from stack [Implied!
Pull Y from stack [Implh"d]
Store zero [Absolute]
Store zero [ABS, X]
. Store zero [ZP]
Store zero [ZP, Xl
Test and reset memory bits with accurilul~tor [ABS)
Te~ and reset memory bits with accumulator [ZP]
Test and set memory bits with accumulator [ABS]
Test and set memory bits with accumulator [ZP]
Test Immediate with accumulator [IMM]
Branch on bit reset [Bit Manipulation, ZP, REL]
Branch on bit set [Bit Manipulation, ZP, REL]
Reset memory bit [Bit Manipulation, ZP]
Set memory bit [Bit Manipulation, ZPI
Note:
1. Most significant digit change only.
Table 5.
HexadecImal Codes For InstructIons With New CMOS Addressing Modes
Hex
Mnemonic
DeSC;rlption
72
32
3C
34
02
52
7C
B2
12
F2
92
AOC
AND
BIT
BIT
CMP
EOR
JMP
LOA
ORA
SBC
STA.
Add memory to accumulator With carry [(IN D)]
AND memory with accumulator [(INDII
Test memory bits with accumulator [ABS, XI
Test memory bits with accumulator [ZP, Xl
Compare memory and accumulator [(I NO))
Exclusive Or memory with accumulator [(IND)]
Jump (New addres,ing mode) [(ABS, Xl]
Load accumulator With. memory WNO)I
OR memory with accumulator [(IN D)]
Subtract Memory from accumulator with borrow [(IND)]
Store accumulator in memory [(INO»)
2-209
R65C02, R65C102,and' R65C112
R65COO Microprocessors (CPU)
INSTRUCTION SET OP CODE MATRIX
The following matrix shows ,the 210 Op Codes associated with
the R6SCOO family of CPU devices. The matrix identifies the
hexadecimal code, the mnemonic code, the addressing mode,
JSA
ABS
3 6
3
5
BVC
EOA
Aelative (IND), Y
2 2""
2 5"
6
ATS
Implied
I 6
ADC
Relative (IND), Y
2 2" 2 S"t
?
BRA
9
A
B
C
D
E
F
LOY
IMM
2 2
LOA
(IND, X)
2 6
BCS
LOA
Relative (lNO), Y
2 2"
2 5"
CPY
IMM
2 2
CPX
IMM
2 2
OAA
ABS, X
3 4"
ASL
ABS, X
3 7
BBA,
ZP
3 5""
BIT
ABS
3 4
AND
ABS
AOL
ABS
BBA2
ZP
3 4
3 6
3 5""
BIT
ABS,X
3 4"
AND
ABS.X
3 4"
AOL
ABS, X
3 7
BBR3
ZP
3 5""
JMP
ABS
EOA
ABS
3 4
LSA
ABS
3 6
BBA4
ZP
3 S""
EOA
ABS, X
3 4"
LSR
ABS, X
3 7
BBRS
ZP
ADC
ABS
3 4t
AOA
ABS
3 6
3 5"
AOA
ABS.X
3 ?
BBA7
ZP
3 S"
STA
ABS
3 4
STX
ABS
3 4
BBSe
ZP
3 5"
STZ
ABS
4
STA
ABS, X
3 5
STZ
ABS, X
3 S
3 5"
LOY
ABS
4
LOA
ABS
3 4
LOX
ABS
BBS2
ZP
3 4
3 S..
LOY
ABS, X
3 4"
LDA
ABS, X
3 4"
LOX
ABS,Y
3 4"
BBS3
ZP
CPY
ABS
3 4
CMP
ABS
3 4
DEC
ABS
3 6
3 5"
CMP
ABS, X
3 4"
DEC
ABS,X
3 7
3 5"
SBC
ABS
3 4t
INC
ABS
3 6
SBC
ABS, X
3 4"t
INC
ABS,X
3 ?
D
E
AMBI
ZP
2 5
CLC
Implied
2
OAA
ABS,Y
3 4"
BIT
ZP
3
AND
ZP
2 3
AOL
ZP
2 5
AMB2
ZP
2 5
PLP
Implied
4
AND
IMM
2 2
BIT
ZP, X
2 4
AND
Zp,X
2 4
AOL
Zp, X
2 6
AMB3
ZP
2 S
SEC
Implied
2
AND
ABS, Y
3 4"
EOA
ZP
AMB4
ZP
2 5
PHA
Implied
2 3
LSA
ZP
2 S
EOA
IMM
2 2
EOR
ZP, X
2 4
LSA
Zp,X
2 6
AMB5
ZP
2 5
CLI
Implied
2
EOA
ABS,Y
3 4"
PHY
Implied
STZ
ZP
2 3
ADC
ZP
2 3t
AOA
ZP
AMB6
ZP
Accum
2 5
ADC
IMM
2 2t
AOA
2 5
PLA
Implied
4
STZ
ZP,X
2 4
ADC
ZP, X
2 4t
AOA
ZP,X
2 6
AMB?
ZP
2 5
SEI
Implied
I 2
ADC
ABS,Y
3 4"t
PLY
Implied
4'
STY
ZP
2 3
STA
ZP
STX
ZP
2
2
3
5MBO
ZP
2 S
DEY
Implied
I 2
BIT
IMM
2 2
TXA
Implied
I 2
STY
ABS
3 4
STA
(IND)
2 S
STY
Zp, X
2 4
STA
ZP, X
2 4
STX
ZP, Y
2 4
5MB,
ZP
2 5
TYA
Implied
1 2
STA
ABS,Y
3 5
TXS
Implied
1 2
3
LOX
IMM
2 2
LOY
ZP
2 3
LOA
ZP
2 3
LOX
ZP
2 3
5MB2
ZP
TAY
Implied
I 2
LOA
IMM
2
TAX
Implied
I 2
3
LOA
(IND)
2 5
LOY
ZP,X
2 4
LOA
Zp, X
2 4
LOX
ZP, Y
2 4
5MB3
ZP
CLV
Implied
I 2
LOA
ABS,Y
3 4"
TSX
Implied
CPY
ZP
2 3
'CMP
ZP
2 3
DEC
ZP
2 S
5MB4
ZP
INY
Implied
1 2
CMP
IMM
2 2
DEX
Implied
2
CMP
ZP, X
2 4
DEC
ZP, X
2 6
5MB5
ZP
2 5
CLD
Implied
1 2
CMP
ABS,Y
3 4"
PHX
Implied
SBC
ZP
2 3t
INC
ZP
2 5
5MB6
ZP
2 5
INX
Implied
1 2
SBC
IMM
2 2t
NOP
Implied
1 2
SBC
ZP,X
2 4t
INC
ZP, X
2 6
5MB?
ZP
2 5
SED
Implied
2
SBC
ABS, Y
3 4"t
PLX
Implied
4
8
9
A
2
AND
(IND)
2 5
2
EOR
(IND)
2 S
ADC
(IN D)
2 St
CMP
(IND)
2 S
CPX
ZP
2 3
SBC
(IND)
2 St
New Opcode
3
AMBO
ZP
2
2 5
2 5
2
,
5
5
3
,
,
,
,
3
,
,
4
2
D-
TAB
ABS
3 6
ASL
Zp, X
2 6
SBC
(IND, X)
2 6t
BEQ
SBC
Relative (IND), Y
2 2"
2 S"t
F
BBAO
ZP
3 5"
OAA
ZP,X
2 4
CMP
(IND,X)
2 6
BNE
CMP
Relative (IND), Y
2 2"
2 5"
E
ASL
ABS
3 6
TAB
ZP
2 S
ORA
(IND)
2 5
STA
BCC
STA
Relative (IND), Y
2 2"
2 6
o
OAA
ABS
3 4
2 5
Relative (IND, X)
2 3"
2 6
8
C
TSB
ABS
3 6
B
3
ADC
(IND, X)
2 6t
BVS
A
ASL
ASL
ZP
RTI
EOA
Implied (INO,X)
I 6
2 6
4
9
OAA
IMM
2 2
5
OAA
ZP
AND
(IND, X)
2 6
BMI
AND
Relative (IND), Y
2 2""
2 5"
8
PHP
Implied
4
TSB
ZP
2 5
2
OAA
BAK
Implied (IND. X)
I 7
2 6
BPL
ORA
Aelative (IND). Y
2 2""
2 5"
the number of instruction bytes, and the number of machine
cycllils associated with each OpCode. Also, refer to the inslfuction set summary for additional information on these OpCodes.
,
2
o
o
BRK
Implied
,
7
-op Code
-Addressing Mode
-Instruction Bytes; Machine Cycles
2-210
,
Accum
2
INC
,
Accum
2
AOL
Accum
I
2
DEC
Accum
,
2
LSR
Accum
i 2
,
,
3 3
3
JMP
(ABS)
3 6
2
ADC
JMP
ABS, X) ABS,X
3 4"t
3 6
,
,
2
,
,
3
CPX
ABS
3 4
,
B
tAdd ,
"Add'
"Add'
Add 2
C
to
to
to
to
N
N
N
N
3
3
4
5"
BBR6
ZP
7
BBS,
ZP
A
B
3 5"
BBS4
ZP
BBSS
ZP
BBSS
ZP
3 5"
BBS?
ZP
3
5""
F
if in decimal mode.
if page boundary is crossed.
if branch occurs to same page;
if branch occurs to different page.
C
D
E
F
ADDRESSING MOOES
MNEMONIC
C-
BBR [#(0-7)1
Branch on Mb = ~
88S I#(P))
Branch on M 6 ", 1
8EQ
BIT
8MI
8NE
8Pl
BAA
aAK
BVC
BVS
CLC
ClD
CLI
CLV
eMP
CPX
CPV
DEC
DEX
DEY
EOA
INC
INX
INY
JMP
JSA
LOA
LOX
LOY
I
L5A
NOP
OAA
PHA
PHP
PHX
PHY
PlA
PLP
PlX
PlV
IMM£DlATE
A+M+C-A(l) (5) (7)
ADC
AND
ASl
acc
acs
~
OPERATtON
A M-A
(1)
=.
Branch on C
Branch on C = 1
Branch on Z = 1
A>M(6)
Branch on N = 1
Branch on Z
Branch on N:= j1
Branch Alwavs
Break
Branch on V = IiJ
Branch on V = 1
'-C
JI-D
'-I
="
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ACCUM.
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TAV
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TXA
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A AM-M
AVM-M
S-X
X-A
X-S
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2. Add 1 to N if branch occurs to- sam~ page.
Add 2 to NIf branch occurs to- different page.
3. Carry not (C) "" BorreM'.
4. Effects a·bit data field of the ~Ified -z.ero _page address.
5. Add 1 to N if in Decimal Mode:
6. On the Bit immediate instruction, the results ofthe M1 and Me bits (N and V flags) are indeterminate and shook:! be considered invalid.
7. If in Decimal Mode, Z flag is invalid. ~umUlator must be checked for Zttro re5UII.
8. JMP (OP Code 6C} is an Absolul. IndirecIAdd....,ng Mode (ABS}.
....
C·
Z
Z
C
C
i
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Index X
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Aocumuaator
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SubIrad
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Exclusive or
~
Number.oI cycles
Number 01 Bytes
II
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z
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0
0
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Memory Bi1 6
Add
=
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m
en
i:
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N
M ~ Memory per effective address
M. ~ Memooy per SlaCk pointer
M. ~ Selecter zero page memory bit
M, ~ Memooy Bi1 7
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I
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3:
;
N
2
2
Notes:
2
....0
i:
(Restored)
N
N
96 4
AA2
A8 2
N
N
N
:D
m
en
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(Restored)
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6E 6
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4C 3
20 6
2 AD 4
2 AE 4
2 AC 4
4E 6
4
P n
61
21
AIS. X
n •
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3
3
3
3
(4)
Rtrn Int
Atrn Sub
A-M C-A (1) (3) (5)
1-C
1-0
I-I
0-M
119 2
•
ONO). Y Z. PABE,.X
n •
P n •
0
X+i-X
Y+l-Y
Jump Sub
M-A
(1)
M--'--X
(I)
M-V
III
0- ~
No Operation
(1)
AVM-A
A-Ms 5-1-5
P--Ms 5-1-5
X-Ms 5-1-8
Y-Ms 5-1-5
5+1-8 Ms-A
5+ 1-8 Ms-P
8+1-5 Ms-X
8+1--8 Ms-Y
P n
(lID. X)
2'
4
4
2 C 4
CE 6
EE 6
IMPLIED
1
I·
C9 2
E' 2
CSf 2'
(1)
•.
ZPR£L
P n •
:F
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Alllll.UTE ERO PAGE
PROCESSOR 5T ATUS
S
...
'0
"0
c:
R65C02,R65C102, and R65C112
R65COO Microprocessors (CPU)
CLOCK TIMING
02 Cycle Time
teve
1000
Note 1
500
Note 1
333
Note 1
250
Note 1
02 Low Pulse Width
tCl
430
5000
210
5000
150
5000
100
5000
02 High Pulse Width
tCH
450
-
220
-
00 Low
tSK2
-
50
-
50
02 Low to 01 High Skew(3)
tSK1
-20
20
~20
20
XTLI High to 02 Lowl4)
tOXI
-
100
to 02 LoW Skew(2)
XTLO Low to 02
Lowl4)
02 Low to 04 High Delay(4)
04 Low Pulse Width(4)
toxo
, t AVS
250
75
-
-
100
125
-
-
ns
40
-
30
ns
20
-20
20
ns
100
-
100
ns
75
-
75
ns
-
65
ns
-
-20
85
~l
430
t04H
450
Clock Rise and Fall Times
tA' tF
-
25
-
?Q
-
15
-
220
5000
150
160
ns
110
ISO
04 High Pulse Width(4)
5000
210
75
ns
5000
100
110
-
ns
5000
ns
-
12
ns
75
-
SO
ns
-
15
-
ns
60
ns
ns
READIWRITE TIMING
tAWS
-
125
100
-
RIW Hold Time
tHAW
15
-
15
-
15
Address Setup Time
tAOS
-
125
-
100
-
Address Valid to 04 High(4)
tM'
100
10
-
0
tHA
15
15
-
tACe
775
340
-
15
Read Access Time
-
-
Address Hold TIme
160
-
RIW Setup Time
25
15
-
215
Re.ad Data Setup Time
tosu
100
-
60
-
40
Read Data Hold Time
tfiR
10
-
10
10
Write Data Delay TIme(2)
tMos
-
200
Write Data Delay Time(')
toow
-
200
Write Data Delay Time(6)
tOO12
-
450
-
-
30
-
Write Data Hold Time
,tHW
75
-
-
85
85
235
-
170
30
-
30
75
110
110
-
ns
ns
30
-
ns
10
-
ns
-
55
ns
-
55
ns
120
ns
30
-
ns
ns
CONTROL LINE TIMING
SYNC Delay
tSYS
-
125
-
100
-
60
tAOS
200
-
110
-
80
60
-
ns
SO Setup Time
tsos
75
-
50
-
-
-
RDY Setup Time
>10
-
30
ns
125
-
100
-
-
75
-
SO
ns
10
-
10
10
ns
15
-
15
-
-
40
40
ns
60
ML Delay Time(5)
tMLS
-
ML Hold Time(4)
tMlH
10
ML Hold Time(6)
tMlH
15
-
BE Delay Time(5)(9)
teE
-
40
'BE Setup Time(5)(9)
tev
-
60
-
IRQ, RES Setup Time
tiS
200
110
NMI Setup Time
tNMI
200
-
150
-
-
15
40
ns
-
60-
-
60
ns
80
-
60
ns
100
-
-
70
-
ns
Notes:
1. RS5C02 and RS5Cl02 minimum operating frequency is limited by 02 low pulse width. All processors can be stopped with 02 held high.
2. R65C02 only.
3. R65C02 and RS5Cl02 only.
4. R65Cl02 only.
5. R65Cl02 and RS5C112 only.
S. R65C112 only.
7. Volta:ge levels shown are V l ,,; 0.4V and VH ;;,: 2.4V unless otherwise stated.
8. Measurement pOints shown are 0.8V (low) and 2.0V (high) for inputs and I.5V (low and high) for outputs, unless otherwise specified.
9. BE signal is asynchronous.
2-212
R65C02,R65C102, and R6SCt12
~(IN)
"1
(OUT)
R65COO···Microproc~ssors·.(CP~)
>
=3- ~tDLV
\...,-____~I
... }
-~
t DLV1
.,2 (OUT)
AO-A1S,
RJW
SYNC
------~----+----J·~-------------4----~~------~~~--~r~------
00-07
(READ) ____________+-J~~~~~~~~~~~~~~~~~~--~~~~~~~
00-07
(WRITE) ------------+---..J("""\lIC.OLfoo=~QoI:;l'-'li.oQol:;lU\"~------__-------_I..J("\Q~/!"o~~
ML
-------------~,~_+----------4+----------------_+--~~~-----
ROY, IRQ -------~ r----+--t--'----------*---------''-----~.lt:_+--------'--
NMI,RES
--------J~-~~~~---------4+--------------J~4_---'-------tSDS
SO
--------------~~~------~1~_+-----------------------------
BE" _________--'
NOTE: ALL TIMING IS REFERENCED FROM A HIGH VOLTAGE OF 2.4 VOLTS AND A LOW Of 0.5 VOLTS.
"ML (MEMORY LOCK) AND" BE (BUS ENABLE) NOT APPLICABLE TO R6SC02.
"
Figure 3.
Timing Diagram for the R65C02 and R65C112
2·213
R$5C02, R65C1 02, and R65C112
Rti5COO Microprocessors (CPU)
XTLI(IN)
-I
XTLO (OUT)
!
I.
.2
.4
(OUT)
(OUT)
R~AD
tllRW,tllA -
RJW,
SYNC,
AO-A15, ML·
(RJW =
WRITE (Rm
HIGH)
= LOW)
00-07
(READ)
00-07
(WRITE)
tHW
SO
ROY, IRQ,
NMI, RES
IBE
BE·
tBY
NOTE: ALL TIMING IS REFERENCED FROM A HIGH VOLTAGE OF 2.4 VOLTS AND.A LOW OF 0.5 VOLTS.
Figure 4.
Timing Diagram for the R65C102
CRYSTAL/CLOCK CONSIDERATIONS
Table 6.
CRYSTAUCLOCK CIRCUITS
Figure 5 shows a time base generation scheme, for 4 MHz operation of the R65C02, that has been tested and proven reliable for
normal environments. As with any clock oscillator circuit, stray
capacitance due to board layout can cause unpredictable results
requiring "fine tuning" of the circuit. Figure 6 shows a possible
external clock scheme for a R65C102 and R65C112 mastertslave
configuration. Table 6 identifies nominal crystal parameters for
five crystal frequencies.
Nominal Crystal Parameters
FREQ
3.58
4.0
6.0
8.0
16.0
MHz
RS
60
3.5
.015
740K
50
30-50
6.5
4-6
.025
730K
.01-.02
720K
20-40
4-6
.01-.02
720K
10-30
3-5
.01-.02
720K
!l
pF
pF
K
CO
C1
Q
Note: These represent ai-cut crystal parameters only. Others may
be used.
2-214
R65C02,R65C102, and R65C112
R65COO Microprocessors (CPU)
UK
3.0K
7404
7404
7404
....-----10 t-------J
NOTES:
II
39
t2
'CRYSTAL: CTS KNIGHTS MP SERiES, OR EQUIVALENT.
"SEE CAUTION FOR STANDBY OPERATION.
Figure 5.
Example of R65C02 Time Base Generation
STOPPING THE CLOCK-STANDBY MODE
Caution must be exercised when configuring the R65C02
or R65C112 in the standby mode (i.e., 00 IN or 02 IN clock
stopped). The input clock can be held in the high state indefinitely; however, if the input clock is held in the low state longer
than 5 microseconds. internal register and data status can be
lost. Figure 7 shows a circuit that will stop the 00 IN (R65C02)
or 02 IN (R65CI12) clock in the high state during standby mode.
Vee
R65C112
t21N
(SLAVEMODE)
37
39
I
t2(OUT) R65C102
XTLI
XTLO
37
F
35
HD~
-'-
C'N
F
16
8
6
4
MHz
MHz
MHz
MHz
COUT
CIN
16
18
20
24
I
pF
pF
pF
pF
16
18
20
24
pF
pF
pF
pF
-'-
I
COUT
-
t2
4
2
1.S
1
STOP
L=STANDBY
H=ACTIVE
MHz
MHz
MHz
MHz
TIME
BASE
(SEE
FIGURE S")
THE OSCILLATOR IN THE R6SC1021S SERIES RESONANT.
THE CRYSTAL INPUT IS DIVIDED BY 4: (R65C102 ONLY)
SYNC
CPU
HC74
Cl R Q
.2(OUT)
+5V
t2 = XT:L
NOTE:
1. R65C02 = to (IN)
R65C112 = .2 (IN)
SEE CAUTION FOR STANDBY OPERATION.
Figure 6. Example of External Clock for R65C102
Figure 7.
2-215
Standby Mode Circuit
R65COO Microprocessors .(CPU)
R65C02, R65C102, and R65Ct 12
MAXIMUM RATINGS*
Parameter
"Note
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 to +7.0
Vdc
Input Voltage
VIN
-0.3 to Vee +0.3
Vdc
VOUT
-0.3 to Vee +0.3
Vdc
Output Voltage
Operating Temperature
Commercial
Industrial
Storage Temperature
TA
Stresses above those listed may cause permanent damage to
the device. This is a stress rating only and functional operation
of the device at these or any other .conditions above those
indicated in other $ections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
°C
o to
+70
-40 to +85
TSTG
-55 to +150
°C
OPERATING CONDITIONS
Parameter
Symbol
Value
Vee
5V ±50/o
Supply Voltage
Temperature Range
Commercial
Industrial
TA
0° to 70°C
-40°C to +85°C
DC CHARACTERISTICS
Parameter
Symbol
Inpul High Vpltage
All Other Input Pins
~O on R.65C02
02 on R65Cl12
VIH
Input Low Voltage
All Other Input Pins
00 on R65C02
02 on R6SCl12
V IL
Ine!:!!-.Leakage Current _ _
NMI. IRQ, BE, ROY, RES, SO
02 IN, 00 IN, XTLI
liN
Three-State (Off Statel Input Current
Data Lines
ITSI
Output High Voltage
SYNC, Data, AO-A1S, RiW, 01, 02, 04, ML
Output Low Voltage
SYNC, Data, AO-A1S, RiW, 01, 02,04, ML
Supply Current
Standby4
Active (R6SC02)
Active (1;I6SC102)
Active (R65Cl12)
Low Power (R65C02)
Low Power (R6SC102)
Low Power (R6SC 112)
Capacitance
NMI, IRQ, SO, BE, ROY
Data, 01, 02, 04, ML, XTLO
AO-A1S, Rm, SYNC
00 (IN), XTU
02 (IN)
Min
Typ
Milx
Vee + 0.3
Vee +0.3
Vee + 0.3
-0.3
-0.3
-0.3
+0.8
+0.4
+0.4
-
-50
1.0
-
10
VOH
2.4
-
VOL
-
C
CIN
COUT
Co
C2
Test Conditions
V
2.0
2.4
Vee - 0.4
Icc
Unit
V
-
+0.4
2
2.6
5
2
1.1
3
0.7
10
4
7
4
2
4
1
7
10
-
10
30
2-216
VIN = OV to S.2SV
Vee = OV
p.A
VIN = O.4V to 2.4V
Vee = S.2SV
V
Vee = 4.75V
I LOAD = -100 p.A
V
Vee = 4.7SV
ILOAI:! = 1.6 p.A
p.A
rnA/MHz
rnA/MHz
rnA/MHz
rnA/MHz
rnA/MHz .'
rnA/MHz
Vee = S.OV
ROY = 0
ROY = 0
pF
-
Notes:
1. All units are direct current (de).
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. IRQ and'NMI require external pull-up resistor.
4. Typical values are shown for Vee = 5.0V and T" = 25°C.
p.A
Vee =5.0V
VIN = OV
f = 1 MHz
TA = 2SoC
, R65C21
'1'
Rockwell
R65C21
PERIPHERAL INTERFACE ADAPTER (PIA)
PRELIMINARY
DESCRIPTION
The R65C21 Peripheral Interface Adapter (PIA) is designed to
solve a broad range of peripheral control problem's in the implementation of microcomputer systems. This device allows a very
effective trade-off betWeen software and hardware by providing
significant capability and flexibility in a low costchip. When cou~
pled with the power and speed of the R6500, R6500/* or R65COO
family of microprocessors, the R65C21 allows implementation
of very complex systems at a minimum overall cost.
Control of peripheral devices is handled primarilY through two
8-bit bidirectional ports. Each of these lines can be programmed
to act as either an input or an output. In addition, four periPheral
control/interrupt input lines are provided. These lines can be
used to interrupt the processor or to "handshake" data between
the processor and a peripheral device.
FEATURES
• Low power CMOS N-well silicon gate technology
• Directreplacement for NMOS R6520 or MC6821 PIA
• Two 8-bit bidirectional 1/0 ports with individual data direction
control
• Automatic "Handshake" control of data transfers
• Two interrupts (cine for each port) with program control
• 1,2, 3, and 4 MHz versions
• Commercial and ,industrial temperature range versions
• 40-pin plastiC and ceramic versions
, .5 volt ±5% supply requirements
• Compatible with the R6500, R6500/* and'R65COO family of
microprocessors
ORDERING INFORMATION
The ,R65C21 is available in both a ceramic and a plastic 40-pin
package, a commerciai or industrial operating temperature range,
and operating frequencies of 1, 2, 3, or 4 MHz. These versions
are coded into the part number as follows:
Part Number:
R65C2L __
Temperature Range (T L to T H):
Blank = O°C to + 700C
E = -400C to + 85°C
L
Frequency Range:
1 = 1 MHz'
2 =2 MHz
3 = 3 MHz
4 =4 MHz
vss
PAO
PAt
PA2
PA3
PA4
PAS
Document No. 29651 N53
IRQA
IRQB
RSO
RSt
RES
PA6
PA7
"00
PBO
O~
01
PBt
03
P~2
[)jI
PB3
PB4
06
PBS
07
O,S
PB6
02
PB,7
CSt
CBt
CB2
Package:
. C = Ceramic
P = Plastic
CAt
CA2
vee
eS2
eso
R/W
Figure 1. R65C21 ~In Configuration
Product Description Order No. 2150
Rev. 2, March 1984
Peripheral Interface Adapter (PIA)
R65C21
FUNCTIONAL DESCRIPTION
The R65C21 PIA is organized into two ingepenqfW Sections
referred toas'the A Side and the BSide. Ea9h section consists
,of a Control Register (CRA, 'CRB), Data DirestlonRegister
(DORA, DORB), Output Register (ORA, ORB), Interrupt Status
Control (ISOA, ISOB), and the buffers necessary to drive the
Peripheral Interface buses. Data Bus Buffers (DBB) interface
IRQA
t
.....
'~
DO
CONTROL
REGISTER A
(CRA)
.,
Df
I
D2
DATA BUS
BUFFE;R
(DBB)
D3
D4
OUTPUT BUS
...~
DS
D6 C'
D7
REGISTER A
(ORA)
DATA INPUT
REGISTER
'(DIR)
,
I
~
, '
PERIPHERAL
OUTPUT
REGISTER B
(ORB)
CSO
CSl
I
p
RSO
RSl
.2
RES
:
-.ole
,I
~~::RAL1"l,
U
RfN
'.
"
"
CS2
data from the two sections to the data pus, while the pat~ Input
Register (DIR) int~rJ!ces data fr(im·t~e, PBB to the ~!A re!;Jisters.
Chip Select andR/W control cirCuitry interface,!6'the processor
bus control lines. Figure 2 is C\l block diagram of the R65C21
PIA.
"
,
L
~
;"
,
'
b
b
~L
IRQB
Figure 2.
R65C21 PIA Block Diagram
2-218
DATA DIRECTION
REGISTER A
(DORA)
=
PERIPHERAL
INTERFACE
BUFFER A
(PIBA) ,
PA~
I"
,
::
...
...
PERIPHERAL
INTERFACE
BUFFER B
(PIBB)
--.
,-
- "'!
;-
PA2
PA3
PA4
~j
"'!
~
pAS
PA6
PA7
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
n
•
:
CA2
PAO
INPUT BUS
CONTROL
REGISTER B
(CRB)
CA1
[-:-
\},
",
,CHIP
SELECT
&RiW
CONTROL
iNTERRUPT STATUS
CONTROl, A (ItiCA)
DATA DIRECTION
REGISTER B
(DDRB)
"
INTERRUPT STATUS
CONTROL B (ISCB)
CSl
CB2
Peripheral Interface Adapter (PIA)
R65C21
DATA INPUT REGISTER (DIR)
PERIPHERAL OUTPUT REGISTERS (ORA, ORB)
When the microprocessor writes data into the PIA, the data
which appears on the data bus during the 112 clock pulse is
latched into the Data Input Register (DIR). The data is then
transferred into one of six internal registers of the PIA after the
trailing edge of the 112 clock. This assures that the data on the
peripheral output lines will make smooth transitions from high
to low (or from low to high) and the voltage will remain stable
except when it is going to the opposite polarity.
The Peripheral Output Registers (ORA, ORB) store the output
data from the Data Bus Buffers (DBB) which appears on the
Peripheral I/O port. If a line on the Peripheral A Portis programmed as an output by the DORA, writing a 0 into the corresponding bit in the ORA causes that line to go low «0.4 V);
writing a 1 causes the line to go high. The lines of the Peripheral
B Port are controlled by ORB in the same manner.
INTERRUPT STATUS CONTROL (ISCA, ISCB)
CONTROL REGISTERS (CRA AND CRB)
The four interrupt/peripheral control lines (CA 1, CA2, CB1, CB2)
are controlled by the Interrupt Status Control logic (A, B). This
logic interprets the contents of the corresponding Control Register and detects active transitions on the interrupt inputs.
Table 1 illustrates the bit designation and functions in the two
control registers. The control registers allow the microprocessor
to control the operation of the Interrupt Control inputs (CA 1,
CA2, CB1, CB2), and Peripheral Control outpu1s (CA2, CB2).
Bit 2 in each register controls the add ressing of the Data Direc,
tion Registers (DORA, DDRB) and the Output Registers (ORA,
ORB). In addition, two bits (bit 6 and 7) in each control register
indicate the status of the Interrupt Input lines (CA1, CA2, CB1,
CB2). These Interrupt Status bits (IRQA1, IRQA2 or IRGlB1,
IRQB2) are normally interrogated by the microprocessor during
the IRQ interrupt service routine to determine the source of the
interrupt.
PERIPHERAL 1/0 PORTS (PAO·PA7, PBO·PB7)
The Peripheral A and Peripheral B VO ports allow the microprocessor to interface to the input lines on the peripheral device
by writing data into the. Peripheral Output Register. They also
allow the processor to interface with the peripheral device output
lines by reading the data on the Peripheral Port input lines
directly onto the data bus and into the internal registers of the
processor.
DATA DIRECTION REGISTERS (DORA, DDRB)
Each of the Peripheral I/O lines can be programmed to act as
an input or an output. This is accomplished by setting a 1 in the
corresponding bit in the Data Direction Register for those lines
which are to act as outputs. A 0 in a bit of the Data Direction
Register causes the corresponding Peripheral 1/0 lines to act
as an input.
The Data Direction Registers (DORA, DDRB) allow the processor to program each line in the 8-bit Peripheral 1/0 port to
be e~her an input Of an output. Each bit in DORA controls the
corresponding line inthe Peripheral A port and each bit in DDRB
controls the corresponding line in the Peripheral B port. Writing
a "0" in a b~ poSition in the Data Direction Register causes the
corresponding Peripheral 1/0 line to act as an input; a "1"
causes it to act as an output.
The buffers which drive the Peripheral A I/O lines contain "passive" pull-up devices. These pull-up devices are resistive in
nature and therefore allow the output voltage to go to VCC for
a logic 1. The switches can sink a full 3.2 mA, making these
buffers capable of driving two standard TTL loads.
Bit 2 (DORA, DDRB) in each Control Register (CRA and CRB)
controls the accessing to the Data Direction Register or the
Peripheral interface. If bit 2 is a "1," a Peripheral Output register
(ORA, ORB) is selected, and if bit 2 is a "0;" a Data Direction
Register (DORA, DDRB) is selected. The Data Direction Register Access Control bit, together with the Register Select lines
(RSO, RS1) selects the various internal registers as shown in
Table 2.
In the input mode, the pull-up devices are still connected to the
1/0 pin and still supply current to this pin. For this reason, these
lines also represent two standard TTL loads in the input mOde.
The Peripheral B I/O port duplicates many of the functions of
the Peripheral A port. The process of programming these lines
to act as an input or an output is similar to the Peripheral A port,
as is the effect of reading or writing this port. However, there
are several characteristics of the buffers driving these lines
which affect their use in peripheral interfaCing.
In order to write data into DORA, ORA, DDRB, or ORB registers,
bit 2in the proper Control Register must first be set. The desired
register may then be accessed with the address determined by
the address interconnect technique used.
Table 1.
7
CRA
CRB
6
IROA1
IROA2
7
6
IROB1
IROB2
5
Control Registers Bit Designations
4
3
CA2 Control
5
4
CB2 Control
2-219
2
1
DORA
Access
3
2
DDRB
Access
0
CA1 Control
1
0
CB1 Control
R65C21
Peripheral ·Interface Adapter (PIA)
The Peripheral B VO port ~ulfers are push-pull devices i.e., the
pull-up devices are switched OFF in the 0 state and ON, for a
logic 1. Since these pUll-ups are active devices, the logic 1
voltage will not go higherthan, :r2.4V.
Figure 1 (on the front page) shows the pin assignments for these
interface Signals and Figure 3 shows the interface relationship
of these sign!'!1 as they pertain to theGPU and the peripheral
. .
devices.
Another difference between the PAO-PA7 lines and the PBO
through PB7 lines is that they have three-state capability which
allows them to enter a high impedance state when programmed
to be used as input lines. In addition, data o.n these lines will be
read properly, WhEln programmed as output lines, eVe,n if the
data signals fall below 2.0 volts for a "high:' state or are above
O.B volts for.a "low" state. When programmed as. output, each
line can drive at least a two TIL load and may also be used as
a source of up to 3.2 milliamperes at 1.5 volts to directly drive
the base of a transistor switch, such as a Darlington pair.
The PIA is selected when CSO and CS1 are high and CS2 is
low. These three Chip select lines are normally connected to the
processor address lines either directly or through external
decoder circuits. When the PIA is selected, data will be transferred between the data lines and PIA registers, and/or peripheral interface lines as determined by the RlW,RSO, and RS1
lines and th~contents of Conlrol Registers A and B.
Because these outputs. are deSigned to drive transistors directly,
the output data is read directly from the Peripheral Output Register for those lines programmed to act as inputs.
The Reset (RES) input initializes the R65C21 PIA. A low signal
on the RES input cause's aU internal registers to'be cleared.
CHIP SELECT (Csa, CS1, CS2)
RESET SIGNAL (RES)
CLOCK SIGNAL (112)
The final characteristic is the high-impedance input state which
is a functiOn' of .the Peripheral B push-PUll buffers. When the
Peripheral B YOUnes 'are programmed to act as inputs, the
output buffer. enters the high' impedance state.
The Phase 2 Clock Signal (02) is the system block that triggers
all data. transfers between the CPU and the PIA. 02is.generated by the CPU and is therefore the synchronizing signal
between the CPU and'the PIA.
DATA BUS BUFFERS (DBB)
READIWRITE SIGNAL (R/W) ,
The Data Bus BufferEiare 8-bit bidirectional bullers used for data
exchange, on the DO-D7 Data Bus, between the microprocessor
and the PIA. These buffers ar!:! tri-state and are capabllil of
driving a two .TTL load. (when operating in an output mode) and
represent a one TTL load to the microprocessor (when operating in an input mode).
Read/Write (R/W) controls the direction of data transfers between
the PIA and the data lines associated wit/l the CPU and the
peripheral devices. A high on the RiW line permits the peripheral
devices to transfer data to the CPU from the PIA. A low on the
RlW line allows data to be transfered from the CPU to the
peripheral devices from the PIA.
INTERFACE SIGNALS
REGISTER SELECT (RSO, RS1)
The PIA interfaces to the R6500, Ra500r or the R6SCOa microprocessor family with a reset line, a 02 cloCk line, a read/write
line, two interrupt request lines, two register' select lines, three
chip select lines, and an B-bit bidirectional data bus.
The two Re,gister Select lines (RSO, RS1), in conjunction ~ith
the Control Registers (CRA, CRB) Data Direction Register access
bits (see Table 1, bit 2) select the various R65C21 registers to
be accessed py the CPU. RSO and RSl are normally connected
to the microprocessor (CPU) address output lines. Through eontrol of these lines. the CPU can write directly into the Control
The PIA interfaces to the peripheral devices with four interrupti
control lines and two B-bit bidirectional data buses.
00-07
,
,2
R6500,
RS500/'
OR
R65COO
MICROPROCESSOR
FAMILY
RNi
RSO
RSl
CSO
CSl
rn
RES
iRaA
IROB
VSS
VCC
...
~
(8)
.J
---
(8)
J PAD-PA7 }
CAl
CA2
PERIPHERAL
DEVICE
A
R65C21
PtA
--
~
..
..
~
(8)
~
Figure 3. Interface Signals Relationship
2-220
..
CBl
CB2
;> PBO-PB7
}
PERIPHERAL
DEVICE
B
Peripheral Interface Adapter (PIA)
R65C21
Registers (CRA, CRB) the Data Direction Registers (DDRA,
DDRB) and the Peripheral Output Registers (ORA, ORB). In
addition, the processor may directly read the contents of the
Control Registers and the Data Direction Registers. Accessing
the Peripheral Output Register for the purpose of reading data
back into the processor operates differently on the ORA and the
ORB registers and therefore are shown separately in Table 2.
by CRB bit O. Likewise, bit 6 (IROB2) in CRB is set by an active
transition on CB2, and IROB from this flag is controlled by CRB
bit 3.
Also, both bit 6 and bit 7 of CRB are reset by a "Read Peripheral
B Output· Register" operation, A summary of IROB control is
shown in Table 3.
Table 3.
Table 2.
ORA and ORB Register Addressing
Register
Register
Address
(Hex)
0
0
1
2
2
3
~lectLines
RS1
RSO
L
L
L
H
H
H
L
L
H
L
L
H
Data Direction
Control
Register Qperation
CRA
CRB
(Bit 2) (Bit 2)
RiW=H
1
0
-
--
-
1
0
-
Read
Read
Read
Read
Read
Read
PIBA
DDRA
CRA
PIBB
DDRB
CRB
RiW=L
Write
Write
Write
Write
Write
Write
iFiQA and
IRaB Control Summary
Control Register Bits
ORA
DDRA
CRA
ORB
DDRB
CRB
Action
CRA-7=1 and CFiA-O=1
IROA goes low (Active)
CRA-6=1 and CRA-3=1
IROA goes low (Active)
CRB-7=1 and CRB-O=1
IROB goes low (Active)
CRB-6=1 and CRB-3=1
IROB goes low (Active)
Note:
The flags act as the link between the peripheral interrupt signals
and the processor interrupt inputs. The interrupt disable bits allow
the processor to control the interrupt function.
INTERRUPT INPUT/PERIPHERAL CONTROL LINES
(CA 1, CA2, C81, C82)
INTERRUPT REQUEST LINES (IRQA, IRQ8)
The four interrupt input/peripheral control lines provide a number
of special peripheral control functions. These lines greatly
enhance the pOwer of the two general purpose interface ports
(PAO-PA7, PBO-PB7). Figure 4 summarizes the operation of
these control lines.
The active low Interrupt Request lines (IROA and IROB) act to
interrupt the microprocessor e~her directly or through external
interrupt priority circuitry. These lines are open drain and are
capable of sinking 1.6 milliamps from an external source. This
permits all interrupt request lines to be tied together in a wiredOR configuration. The A and B in the titles of these lines correspond to the peripheral port A and the peripheral port B so
that each interrupt request line services one peripheral data
port.
CA 1 is an interrupt input only. An active transition of the signal
on this input will set bit 7 of the Control Register A to a logic 1.
The active transition can be programmed by setting a "0" in bit
1 of the CRA if the interrupt flag (bit 7010RA) is to be set on
a negative trans~ion of the CA 1 Signal or a "1" if it is to be set
on a positive transition.
Each Interrupt Request line has two interrupt flag bits which can
cause the Interrupt Request line to go low. These flags are bits
6 and 7 in the two Control Registers (CRA, CRB). These flags
act as the link between the peripheral interrupt signals and the
microprocessor interrupt inputs. Each flag has a corresponding
interrupt disable bit which allows the processor to enable or disable the interrupt from each of the four interrupt inputs (CA 1,
CA2, CB1, CB2). The four interrupt flags are set (enabled) by
active transitions of the signal on the interrupt input (CA 1, CA2;
CB1,OB2).
NOTE:
A negative transition is defined as a transition from a high
to a low, and a pOsitive transition is defined as a transition
from a low to a high voltage.
CA2 can act as a totally independent interrupt or as a peripheral
control output. As an input (CRA, bit 5 = 0) it acts to set the
interrupt flag, bit 6 of CRA, to a logiC 1 on the active transition
selected by bit 4 of CRA.
CRA bit 7 (IROA1) is always set by an active transition of the
CA1 interrupt input signal. However, IROA c.an be disabled by
setting bit 0 inCRA to a O. Like.wise, CRA bit 6 (lROA2) can be
set by an activeArans~ion of the CA2 interrupt input signal and
IROA can be disabled by setting bit 3 in CRA to a O.
These control register bits and interrupt inputs serve the same
basic function as that described above for CA 1. The input signal
sets the interrupt flag which serves as the link between the
peripheral device and. the processor interrupt structure. The
interrupt disable bit allows the processor to exercise control over
the system interrupt.
Both bit 6 and bit 7 in CRA are raset by a "Read Peripheral
Output Register A" operation. This is defined as an operation
in which the read/write, proper data direction register and register select signals are provided to allow the processor to read
the Peripheral A I/O port. A summary of IROA control is shown
in Table 3.
In the output mode (CRA, bit 5 ?' 1), CA2can operate independently to generate a simple pulse each time the microprocessor reads the data on the Peripheral A
port. This mode
is selected by setting CRA, bit 4 to a 0 and CRA, bit 3 to a 1.
This pulse output can be used to controlthe counters, shift registers, etc., which make sequential data available on the Peripheral input lines.
va
Control of IROB is performed in exactly the same. manner as
that described above for IROA. Bit 7 in CRB (IROB1) is set by
an active transition on CB1 and IROB from this flag is controlled
2-221
II
R65C21
Peripheral Interface Adapter (PIA)
CA2 INPlIT MODE (BIT 5
CONTROL REGISTER A (CRA)
= 0)
7
6
5
4
3
2
1
0
IRQAl
FLAG
IRQA2
FLAG
CA2INPUT
MODE SELECT
(=0)
IRQA2
POSITIVE
TRANSITION
IRQA
ENABLE
FOR IRQA2
ORA
SELECT
IRQA1
POSITIVE
TRANSITION
IRQA
ENABLE
FOR IRQAl
IRQNIRQA2
CONTROL
...
IRQNlRQAl
CONTROL
CA20UTPlIT MODE (BIT 5 = 1)
7
6
5
4
3
2
1
0
IRQAl
FLAG
0
CA2 OUTPUT
MODE SELECT
(=1)
CA2
OUTPUT
CONTROL
CA2
RESTORE
CONTROL
ORA
SELECT
IRQAl
POSITIVE
TRANSITION
IRQA
ENABLE
FOR IRQAl
IRQNlRQA1
CONTROL
CA2
CONTROL
CA2 INPUT OR OuTPlIT MODE (BIT 5 == 0 or 1)
Bit 7
1
o
Bit 2
1
o
IRQA 1 FLAG
A transition has occurred on CAl that satisfies the bit 1 IRQA1 transition polarity cnteria. This bit is cleared by a read of OlllJlut Register
A or by R.ES.
No transition has occurred on CA1 that satisfies thE! bit 1 IRQA1 transition polarity criteria.
OUTPUT REGISTER A SELECT
Select Olllput Register A.
Select Data Direction Register A.
Bit 1
1
IRQA1 POSITIVE TRANSITION
Set IRQAl Flag (bit 7) on a positive (Iow-to-high) transition of CAl.
Set IRQA1 Flag (bit 7) on a negative (high-to-Iow) transition of CA1.
Bit 0
IRQA ENABLE FOR IRQA1
Enable assertion of IRQA when IRQAl Flag (bit 7) is set.
Disable assertion of IRQ A when IRQA1 Flag (bit 7) is set.
o
1
o
CA2 INPUT MODE (BIT 5
Bit 6
1
o
Bit 5
o
Bit 4
1
o
Bit 3
1
o
=0)
CA2 OUTPUT MODE (BIT 5
Bit 6
IRQA2 FLAG
A transition has occurred on CA2 that satisfies the bit 4
IRQA2 transition polarity criteria. This flag is cleared by
a read of Output Register A or by RES.
No transition has occurred on CA2 that satisfies the bit
4 IRQA2 transition polarity criteria.
a
CA2 MODE SELECT
Select CA2 Input Mode.
Bit 5
1
CA2 MODE SELECT
Select CA2 Output Mode.
Bit 4
·1
CA2 OUTPUT CONTROL
CA2 goes low when a zero is written into CRA bit 3.
CA2 gdes high when a one is written into CRA bit 3.
CA2 goes low on the first negative (high-to-Iow) 1/12
clock transition following a read of Outp~t Register A.
CA2 returns high as specified by bit 3.
o
IRQA2 POSITIVE TRANSITION
Set IRQA2 Flag (bit 6) on a positive (Iow-to-high)
transition of CA2.
Set IRQA2 Flag (bit 6) on.a negative (high-to-Iow)
transition of CA2.
Bit 3
1
o
IRQA ENABLE FOR IRQA2
Enable assertion of IRQA when IRClA2 Flag (bit 6) is
set.
Disable assertion of IRQA when IRQA2 Flag (bit 6) is
sel.
Figure 4.
CA2 READ STROBE RESTORE CONTROL (4 = 0)
CA2 returns high on the next 1/12 clock negative
transition following a read of Output Register A.
CA2 returns high on the next active CA1 transition
following a read of Output Register A as specified by
bit 1.
Control Line Operations Summary (1 of 2)
2-222
=1)
NOT USED
Always zero.
Peripheral Interface Adapter (PIA)
R65C21
CB2 INPUT MODE (BIT 5
CONTROL REGISTER B (CRB)
=0)
7
6
5
4
3
2
1
()
IROBI
FLAG
IROB2
FLAG
C621NPUT
MODE SELECT
(=0)
IROB2
POSITIVE
TRANSITION
IROB
ENABLE
FOR IROB2
ORB
SELECT
IROBI
POSITIVE
TRANsrnON
IROB'
ENABLE
FOR IROBI
IROB/IROBI
CONTROL
IROB/IROB2
CONTROL
CB2 OUTPUT MODE (BIT 5
= 1)
7
8
S
4
3
2
1
0
IROBI
FLAG
0
CB20UTPUT
MODE SELECT
(=1)
CB2
OUTPUT
CONTROL
CB2
RESTORE
CONTROL
ORB
SELECT
IROB1'
POSITIVE
TRANSITION
IROB
ENABLE
FOR IROBl
CB2
CONTROL
CB21NPUT OR OUTPUT MODE (BIT 5
Bit 7
1
o
IROB/IROBl
CONTROL
= 0 or 1)
IRQB1 FLAG
A trans~ion has occurred on CBl that satisfies the bit 1 IROBI transition polarity criteria. This bit is cleared by a read of Output Register
Bor by RES.
No transition has occurred on CBl that satisfies the bit 1 IROBl transition polarity criteria.
Bit 2
1
OUTPUT REGISTER B SELECT
Select Output Register B.
Select Data Direction Register B.
Bit 1
1
IRQB1 POSITIVE TRANSITION
Set IROBl Flag (bit 7) on a positive (Iow-to-high) transition of CB1.
Set IROBl Flag (bit 7) on a negative (high-to-Iow) transition of CB1.
Bit 0
1
IRQB ENABLE FOR IRQB1
Enable assertion of iRffii when IROBl Flag (bit 7) is set.
Disable assertion of IROti! when IROBl Flag (bit 7) is set.
o
o
o
CB2 INPUT MODE (BIT 5
Bit 6
1
o
= 0)
CB2 OUTPUT MODE (BIT 5 = 1)
IRQB2 FLAG
A transition has OCcurred onCB2 that satisfies the bit 4
IROB2 trans~ion polarity criteria. This flag is cleared by
a read of Output Register B or by RES.
No transition has occurred on CB2 that satisfies the bit
4 IROB2 transition polarity criteria.
Bit 5
CB2 MODE SELECT
Select CB2 Input Mode.
Bit 4
IRQB2 POSITIVE TRANSITION
Set IROB2 Flag (bit 6) on a pos~ive (Iow-to-nigh)'
transition of CB2.
Set IROB2 Flag (bit 6) on a negative (high-tO-low)
transition of CB2.
o
Blt6
NOT USED
Always zero. '
BitS
1
CB2 MODE SELECT
Select CB2 Output Mode.
Bit 4
1
CB2 OUTPUT CONTROL
CB2 goes low when a zel'Q is written into CRB b~ 3.
CB2 goes high when a one is written into CRB b~ 3.
CB2 goes low on the first negntrol Registers A and B.
Bit 7 of the CMCR determines whether the IRQTline is enabled
or disabled for generating an interrupt request 011 the IRQ output
to the processor. When bit 7 is set to a 1, IRQT is enabled so
that an Underflow Flag (UF bit in the Status Register set to a
1) will cause IRQ to be asserted. When bit 7 is set to a 0, the
IRQT is d i s a b l e d . '
.
Note:
An R65C24 PlAT may be installed in a circuit in place of
an R65C21 PIA subject to Chip selectcohsiderations.
SinCE! the R65C21 has a CS1 input and tlJEi R65C24 does
BIt 4 of the CMCR enables or disables the Prescaler. A1: in bit
4 causes the Prescaler to be enabled so thatthi! CounlElr/Timer
is operating in a divide-by-sixteen mode. When this bit is a 0,
the Prescaler is disabled SO that the Counter/Timer is operating
in a normal (divide-by-one) rhode ..
.-
00-07 ~
(8)
not have. a CS1input, the PlAT will be selected in the
same addresses as the PIA and maybe more depending
upon external address decoding circuitry.
..
,
:'~
8)
r
> PAo-PA7
,
f62
R6500,
R&500r
OR
R65COO
MICROPROCESSOR
.
FAMILY
CAl
CA2
RiW
RSO
RSl
RS2
esO.
CS2
.RES
IRQ
VSS
VCC
R&5C24
PlAT
..
CN'f.R
CB1
CB2
'
...
I
~ PBo-PB7
18)
r
Figure 4. Interface Signals Relatlonahlp
2-233
'}
.' . . . PERIPHERAL
DEVICE
A
}
PERIPHERAL
DEVICE
B
2
Peripheral Interface AdapterlTimer (PlAT.)
,R65C24
Register Select line RS2 determines whether the, addressed
registers are part of the CQunter/Timer or the peripheral, Port A
ard Port B sections of the PIAT.When RS2 is high, the Port AI
Port B registers shown in Table 2 are selected. When the RS2
is low,the Counter/Timer registers are selected and ,operated
upon as shown in Table 3.
RESET SIGNAL (RES)
The Reset (RES) input initializes the R65C24 PlAT. A low signal
on the RES input causes all internal registers to be Cleared.
Cl.OCK SIGNAL (162)
The Phase 2 Clock Signal (¢2) is the system clock that triggers
all data transfers between the CPU and the PlAT. ¢2 i~gen
erated by the CPU and is therefore the synchronizing signal
between the CPU and the PlAT. '
Table3.
Resister
Address
(Hex) RS2 RSt ASO
R~AD/wRITE ~IGNAL (FI/W)
Read/Write (R/W)controls.th~ direction of data transfers betWeen
the PlAT and the data 'lines assOciated wiih the CPU and the
peripheral devices. A high on the R!W line permits the peripheral
devices to transfer data to the CPU'from the PlAT. A 10vJ on the
R!Wline allows 'data to be transfereCl frortl the CPU to the
peripheral devices from the PlAT.
'
REGISTER $ELECT (RSO,, '.,RS1, RS2)
.'
CounterlTlmer Register Addressing
.Reglst8r
SeleCt Lines
(R/W
= L)
0
L
L
L Read Snapshot
Latch (SL)
SL ..... DO-D7
0 ..... UF
1
L
L
H F:lead Upper " WritE! Upper Latch
Counler(UC)
(ULI
UC ..... OO-D7
DO,D7 ..... "UL
2
L
H
L Read Lower
Counter (LC)
LC':"" DO-D7
UC ..... SL
Writ~
3
L
H
H ABad', Status
Regi$ler (SR)
S~"'" Od-D7
0 ..... UF"
Write Counter Control
Mocte Flegister '
. (CMCR)
DO-D7 ..... CMCR
" ,
Two of the Register Select lines (RSO, RS1), in conjunction with
the Control Registers (CRA, CRI3)'Data Direction Register access
bits select various R65C24 registers to be accessed ,by the
CPU. RSO and RSl are normall¥ connected 10,the microprocessor (CPU) address output
Through C9ntrol of these
lines,. the CPU can writ!'! di~ctly into theContro!, Registers
(CRA, CRB) the Data Oirection Registers (DDRA;DDR~) and,
the Peripheral OutpUt Registers (ORA, ORB). In addition, the
processor may directly read the contentsot the Control Regis~
ters and the Data Direction.Registers. Accessing the Peripheral
Output Reg~r for the purpose of reading data blilCk into the
processor operates differently on .the ORA ar)d the ORB registers and therefore are shown separately in Table 2.
Counter/Timer Operation
(Afii = H)
Ii!:les.
Write Upper Latch
(UL)
00-07 ..... UL
0 ..... UF
!,Qad and Enable
Counter
UL ..... UC.
LL .... LC
!,ower Latch
(LL)
00-07 ..... LL
UC':""SL
"
INTERRUPT REQUEST LINE (IRQ)
Note:
Three internal active low Interrupt Request lines (IROA, IROB,
and IROn act to interrupt the microprocessor through the
externallRO output. IRO is an open drain output and is capable
of sinking 1.6 milliamps .from an external source. This permits
all interrupt request lines to be tied together in a wired-OR configuration. The A and B in the titles of these internal lines correspond to the peripheral port A and the peripheral port B so
that each interrupt request line services one peripheral data
port. The T corresponds to the Counter/Timer generated interrupt·request.
In order to address the ORA and ORB Registers in the
PlAT, Register Select line RS2 must be high When RS2
is low, thE! CounterlTimer regiSters are selected (aashown
in Table 3).
Table 2.
Peripheral Register Addressing
Data
Direction
Register
Control
Register
Select
Linea
Register
Address
CRA CRB
(Hex) RS2 RSt RSO (Bit 2) (Bit 21
4
H
L
L
1
-
RJW= H
RJW = L
Read PISA
Write ORA
4
H
L
L
0
-
Read DDRA Write DDRA
5
H
L
H
-
-
Rf;ladCRA
Write CRA
6
H
H
L
-
1
Read PISS
WriteORS"
6
H
H
L
0
Read DDRS Write DORA
7
H
H
H
-
-
IRQA and IRQ~ Lines-These two internal Interrupt Request
lines are associated with the Port A and Port B sections of the
PlAT and are controlled by Control Registers CRA and CAB,
and the Peripheral Control lines CAl, CA2, CB1, and CB2.
Register Operation
Read CRB
These Interrupt Request lines have three i(lterrypt flag bits
which 'can cause the Interrupt Request line 10 go low. These
flags are bits 6 arid 7 in the two Control Registers (CRA, CRB).
These flags act as the link between the peripheral interrupt signals and "the microprocessor interrupt inputs. Each flag has a
corresponding interrupt disable bit whl,ch allows the processor
to enable or disable the interrupt from each of the four interrupt
WriteCRS
2-234
R65C24,'
Peripheral Interface Adapterrrimer (PlAT)
CM is. an interrupt input only. An active transition of the signal
on this input will set bit 7 of the Control Register A to a logic 1.
The active transition can be programmed by setting a "0" in bit
1 of the CRA if the interrupt flag (bit 7 of CRA) is to be set on
a negative transition of the CAl signal ora "I" if it is to be set
on a positive transition.
inputs (CAl, CA2, CB1, CB2). The four interropt flags are set
(enabled) by active transitions of the signal on the interrupt input
(CAl, CA2, CB1, CB2).
CRA bit 7 (IROA1). is always set by an active transition of the
CAl interrupt input signal. However, IROA can be disabled by
setting bit 0 in CRA to .a O. Ukew.ise, CRA bit 6 (IROA2) can be
sebbY an active transition of the CA2 interrupt input signal and
IR A can be disabled by setting bit 3 in CRA to a O.
Note:
A negative transition is defined as a transition from a high
to a low, and a positive transition is defined as a transition
from a low to a high voltage.
Both bit 6 and bit 7 in CRA are reset by II "Read Pfilripheral
Output Register A" operation. This is defined as an operation
in which the read/write, proper data direction register and register select signals are provided to allow the processor to read
the Peripheral A I/Opor!. 'A summary of iRQA control is ShOwn
in Table 3.
CA2 can act as a totally independent interrupt or as a peripheral
control output. As. an input (CRA, i:)it 5 ; 0) it acts to set the
interrupt flag, bit 6 of CRA, to a logic 1 on the active transition
selected by bit 4 of CRA.
Control of IROB is performed in exactly the same manner as
that described above for IROA. Bit 7 in CRB (lROB1) is set by
an active transition on CBl and IROB from this flag is controlled
by CRB bit O. Ukewise, bit6 (IROB2) in CRB is set by an active
transition on CB2, and IROB from this flag is controlled by CRB
bit 3.
These control ,register bits and interrupt .inputs serve the same
basic function 'as that described above for CAl. The input signal
sets the interrupt flag which serves as the link between the
peripheral device and the processor interrupt structure. The
interrupt disable bit allows the processor to exercise control over
the system interrupt.
Also, both bit 6 and bit 7 of CRB are reset by a "Read Peripheral
B Output Register" operation. A summary of IROB control is
shown in Table 4.
Table 4.
IRQA and
In the output mode (CRA, bit 5 ; 1), .CA2 can operate independently to generate a Simple pulse each time the microprocessor reads the data on the Peripheral A VO port. This mode
is selected by setting CRA, bit 4 to a 0 and CRA, bit 3 to a 1.
This pulse output can be used to control the counters, shift registers, etc. which make sequential data a'vallable on the Periph.
eral input lines.
iRQii Control Summary
Control Register Bits
Action
CRA-7;1 and CRA-O;1
IROA goes low (Active)
CRA-6=1 and CRA-3=1
IROA goes low (Active)
CRB-7=1 andCRB-O=!
IROB goes low (Active)
CRB-S;! and CRB-3;1
A .,second output mode allo~s CA2 to be used in conjunction
with CAl to "handshake" between the processor and the
peripheral device. On the A side, this technique allov.is positive
control of data transfers from ttie peripheral. device into the
microprocessor. The CAl input signals the processor that data
is available by interrupting thep;OCessor. The processor reads
the data and sets CA2 low. This Signals the peripheral device
that it can make new data available.
IROB goes low (Active)
Note:
The flags act as the link between the peripheral interrupt signals
and the processor interrupt inputs. The interrupt disable Ms allow
the processor to control the Interrupt function.
The final output mode can be selected by setting. bit 4 of CRA
to a 1. In this mode,· CA2 is a simple. peripheral control output
wh,ic;hcan be set high or .low by setting bit 3 of CRA to a 1 or
a 0 respectively.
IRQT Line-The internal IROT line is associated with the
Counter/Timer and is controlled by the IROT Enable bit in the
Counter Mode Control Register and the Underflow Flag in the
Status Register. A thorough discussion of the functions and
operation of thelROTline is given in the Counter/Timer Operation section ofthis product description.
CBl operates as an interrupt input only in the same manner as
CAl; Bit 7 of CRB is set by the active transition selected by bit
of CRB. Likewise, the CB2 input mode operates exactly the
same .as the CA2inpUt modes. TI'\e CB2 output modes, .CR.B
bit 5 = .1, differ somewhat from those of CA2. The pulse output
occurs when the processor writes data irito tile Peripheral B
Output Register. Also, the "handshaking" operates on data
transfers from the processor into the peripheral device.
o
INTERRUPT INPUT/PERIPHERAL CONTROL LINES
(CA1,
~,
CB1, CB2)
The four interrupt input/peripheral control lines provide a number
of special peripheral control functions. These lines greatly
enhance the. power of the two general purpose interface ports
(PAO-PA7, PBO-PB7). Figure 5 summarizes the operation of
these control lines.
2-235
R65024
Peripheral Interface Adapter/Timer (PlAT)
CONTROL REGISfER A (CRA)
CA21NPUT MODE (SIT 5 = 0)
7
IRQAl
. FLAG
6
5
4
3
2
1
0
IRQA2
FLAG
CA2INPUT
MODE SELECT
(=0)
IRQA2
POSITIVE
TRANSITION
IROA
ENABLE
FOR IROA2
ORA
SELECT
IROAl
POSITIVE
TRANSITION
IROA
ENABLE
FOR IROAl
fRQA/IRQAl
CONTROL
IROA/IRQA2
CONTROL
CA2 OUTPUT MODE (BIT 5
= 1)
7
6
5
4.
3
2
1
Il
IROAl
FLAG
0
CA2 OUTPUT
MODE SELECT
(=1)
CA2
OUTPUT
CONTROL
CA2
RESTORE
CONTROL
ORA
SELECT
IROAl
POSITIVE
TRANSITION
IROA
ENABLE
FORIBQAl
CA2
CONTROL
CA2 INPUT OR OUTPUT MODE (BIT
Bit 7
1
o
Bit 2
1
o
5 == Ocr 1)
IRQA1 ~LAG
A tr!iflsition hilS occurred o.n CA1 that satisfies the bit 1 ,ROA1 transition polarity criteria. This bit is cleared by a read of Output Register
Aor by R E S . ·
.
No transnion has occurred on CAl that satisfies the bit 1 IROA 1 transition polarity criteria.
OUTPUT REGISTER A SELECT
Select Output Register A.
Select Data Direction Register A.
BIt.1
1.
IRQA1 POSITive TRANSITION
Set IROAl Flag (bit 7) on a positive (Iow-to-high) transftlon of CAl.
Set IROAt. Flag (bit 7) on a negative (high-to-loW) transition of CA1.
Bit 0
IRQA ENABLE FOR IRQA1
Enable assertion of IROA when iROAl Flag (bit 7) is set.
Disable assertion of IROA when IROAl Flag (bit 7) is set.
o
1
o
CA2 '''!PUT MODE (BIT 5
Bit 6
1
o
=0)
IRQA2 FLAG,
A transitiOn has occurred onCA2 that satisfies the bit 4 IROA2 transition polarity criteria. This flag is cleared by· a read of Output
Register A or by RES.
No transition has. occurred on CA2 that satisfies .the bit 4 IRQA2 transition,. polarity criteria.
Bit 5
CA2 MOOE SELECT
select CA2 Input Mode.
Bit 4
IRGlA2 POSITIVE TRANSITION
Set IROA2Flag (bit 6) on a positive (Iow-to-high) transition of CA2.
Set IROA2 Flag (bit 6) on a negative (high-to-Iow) transition of CA2.
o
1
o
Bit 3
.1
o
IRQAIIROAl
CONTROL
iRQA ENABLE: FOR .IRQA2
Enable as~rtion of IRQA When IROA2 Flag (bit 6)i5 set.
Disable assertion of IRQ A when IRQA2 Flag (bit 6)· is set.
CA2 OUTPUT MODE (BIT 5 = 1)
Bit 6
NOT USED
Always zero.
Bit 5
1
CA2 MODE SELECT
Select CA2 Output Mode.
Bit 4
1
CA2 OUTPUT CONTROL
CA2 goes low when a zero is written into CRA bit 3. CA2 goes high when a one is written into CRA bit 3.
CA2 goes low on the first negatilie (high-to-Iow) rjJ2 clock transition follOWing a read of Output Register A. CA2 returns high as specified
by bit 3.
Bit 3
CA2 READ STROBE RESTORE CONTROL (BIT 4 0)
CA2 returns high on the next jZl2 clock negative transition following a read of Output Register A.
CA2 returns high on the next active CAl transition following a read of Output Register A as specified by bit 1.
o
o
1
o
=
Figure 5_ Summary of Control Lines Operation (1 of 2)
2-236
R65C24
Peripheral Interface AdapterlTimer (PlAT)
CONTROL REGISTER B (CRB)
CB2 INPUT MODE (BIT 5 = 0)
7
6
5
4
3
2
1
0
IROBl
FLAG
IROB2
FLAG
CB21NPUT
MODE SELECT
(=0)
IROB2
POSITIVE
TRANSITION
IROB
ENABLE
FOR IROB2
ORB
SELECT
IROBl
POSITIVE
TRANSITION
IROB
ENABLE
FOR IROBl
IROBflROB2
CONTROL
CB2 OUTPUT MODE (BIT 5
IROB/lROBl
CONTROL
= 1)
7
6
5
4
3
2
1
0
IROBl
FLAG
0
CB2 OUTPUT
MODE SELECT
CB2
OUTPUT
CONTROL
CB2
RESTORE
CONTROL
ORB
SELECT
IROBl
POSITIVE
TRANSITION
IROB
ENABLE
FOR IROBl
(=1)
CB2
CONTROL
CB21NPUT OR OUTPUT MODE (BIT 5
Bit 7
o
=0 or 1)
IRQBl FLAG
A transition has occurred on CBl that satisfies the bit 1 IROBl transition polarity criteria. This bit is cleared by a read of Output Register
B or by RES.
No transition has occulted on CBl that satisfies the bit 1 IROBl transition polarity criteria.
Bit 2
1
OUTPUT REGISTER B SELECT
Select Output Register B.
Select Data Direction Register B.
Bit 1
1
IRQBl POSITIVE TRANSITION
Set IROBl Flag (bit 7) on a positive (low-tO-high) transITion of CBt.
Set IROBl Flag (bit 7) on a negative (high-to-low) transition of CBt.
o
o
Bit 0
1
o
IRQB ENABLE FOR IRQBl
Enable assertion of IROB when IROBt Flag (bit 7) is set.
Disable assertion of IROB when .IROBt Flag (bit 7) is set.
CB21NPUT MODE (BIT 5
Bit 6
o
=0)
IRQB2 FLAG
A tranSITion has occurred on CB2 that satisfies the bit 4 IROB2 transition polarity criteria. This flag is cleared by a read. of Output
Register B or by RES.
No transition has occurred on CB2 that satisfies the bit 4 IROB2 transition polarity criteria.
Bit 5
CB2 MODE SELECT
Select CB2 Input Mode.
Bit 4
1
IRQB2 PQSITIVE TRANSITION
Set IROB2 Flag (bit 6) on a positive (low-to-high) transition of CB2.
Set IROB2 Flag (bit 6) on a negative (high-to-Iow) transition of CB2.
Bit 3
1
IRQB ENABLE FOR IRQB2
Enable assertion of IROB when IROB2 Flag (bit 6) is set.
Disable assertion of IROB when IROB2 Flag (bit 6) is set.
o
o
o
IROB/lROBl
CONTROL
CB2 OUTPUT MODE (BIT 5 = 1)
Bit 6
NOT USED
Always zerO.
Bit 5
1
CB2 MODE SELECT
Select CB2 Output Mode.
Bit 4
1
CB2 OUTPUT CONTROL
CB2 goes low when a zero is written into CRB bit 3. CB2 goes high when a one is written into CRB bit 3.
CB2 goes low on the first negative (high-to-IOw)¢2 clock transition following a write to Output Register B. CB2 returns high as specified
by bit 3.
Bit 3
1
o
CB.2 WRITE STROBE RESTORE CONTROL (BIT 4 0)
CB2 returns high on the next 912 clock negative transition following a write to Output RegisterB.
CB2 returns high on the next active CBt transition following a write to Output Register B as specified by bit 1.
o
o
=
Figure 5_
Summary of Control Lines Operation (2 of 2)
2-237
II
R65C24
'oj.
Peripheral Interface Adapter/Timer (PlAT)
,:"
COUNTERfTlMER REGISTERS
Bit 7
o
1
COUNTER MOPE CONTROL REGISTER (CMCR)
The 8-bitCounter Mode Control Register (CMCR) selects the
Counter/Timer mQde of operation and enables or disables both
the internal iRCif arid the Prescaler. The format of the CMCR
is:
7
IRQT
Enablec:i,
Bit 7
6
5
0
0
4
2
3
Prescaier
Enabled'
1
Bit 6
o
Bit 5-0
0
1
Bits 6-5
Bit 4
1
Sit 3
as shown In register
Not used, don't care value during write.
Not used, don't care value during write.
Bits 2-0
000
o
0 1
010
o 1 1
1 0 0
101
1
1
0
1
1
1
LOWER LATCH (LL)
CounterlTimer Mode
Mode O-Oisable Counter/Timer
Mode 1-One-Shot Interval Timer
Mode 2-Free-Run hlterval Timer
Mode 3-Pulse Width Measurement
Mode 4-Event Counter
Mode 5-One-Shot Pulse Width Generation
Mode 6-Free-Run Pulse Generation
Mode 7-Retriggerable Interval Timer
The Lower Latch (LL) holds the least significa,nt 8-bits of the
16-bit latch value. The LL is written from the datI! bus (00-07)
when the register address is 2 arid R/W is 10w.,When the LL is
loaded, the contents of the UC are copied into the Snapshot
Latc!) (SL) without affecting the counting operation of the UC.
UPPER LATCH (OL)
The Upper Latch (UL) holds the most Significant a-bits of the
16-bit latch value. The UL is written from the data bus (00-07)
when R/W is low and the register address is either 0 or 1: The
difference in the two register address functions are:
The CMCR can be written into at any time without disabling or
stopping the Counter/TImer. This allows the Counter/Timer mode
of operation to be changed while it is still in operation. However,
selecting Mode 0 disables the Counter/Timer and stops its
operation. The Prescaler and the IRQT interrupt clm also be
enablEid or disabled at any time. The CMCR is written to when
the register address is 3 and Riw is low.
Register Address 0
1. The UL is loaded from 00-07.
2. The contents of the Latch(UL and LL) are transferred to the
Counter (UC and LC,respe"ctively).
3. The UF bit'is cleared in the SR.
4. The Counter is enabled, i.e., the count in UC and LC is decremented by one upon detection of a rising edge on either
02 or CNTR (depending upon mode selection) as scaled by
the Prescaler.
STATUS REGISTER (SR)
The 8-bit Status Register (SR) reports the status of two interrupt
conditions: Counter underflow (iRCif) and Port A interrupt
(tRQA). The format of the Status Register is:
7
Not ,,!sed, always read
figure.
The Counter underflow (UF)"bit 7, is updated in the same clock
cycle that an underfiow condition occurs on the CounterlTimer.
The iRQA interrupt flag (bit 6) is updated at the rising edge of
the next ¢2 clock immediately following the setting of corresponding interrupt bits (IRQA1, IRQA2) in the CRA register.
IROA is set whenever IRQA1 or IRQA2 is set The underflow
bit is cleared whenever the Status Register is read, the Snapshot Latch is read, the UI,. is written to at register address 0,
Mode 0 is selected in the CMCR,or a RES occurs. Reading the
Status Register also clears the IRQA interrupt flag. The Status
Register is read when the register address is 3 and R/W is high.
PreS(:aler Enabled
Prescaler Disabled (+ 1)
Prescaler Enabled (+16)
o
IRQA Interrupt Flag
Port A interrupt has not occurred.
Port A interrupt has not occurred.
CounterlTimer Mode
0
IRQT Enabled
IROT Disabled
IROT Enabled
o
Counter Underflow (UF) Interrupt Flag
Counter underflow has not occurred.
Counter underflow has occurred.
5
6
UF (IRQT) IRQA
Interrupt Interrupt
,Flag
Flag
4
3
2
1
0
1
1
1
1
1
Register Address 1
0
1. The UL is loaded from 00-07.
2. All other elements of the Counter/Timer are unaffected.
2-238
R65C24
Peripheral Interface AdapterlTimer (PIA:f)
LOWER COUNTER (LC)
UL and LL values are loaded into the UCand LC, respectively,
and the counter is enabled. The counter then decrements one
count for every posHive edge (low to high) transHion detected
on the 02 or CNTR input (depending on the selected mode) as
scaled by the Prescaler. In most modes, each time the counter
underflows below $0000, the underflOW bit is set in the SR, the
cO!lnter reloads to the latch value and the down-counting con·
tinues. If the UF bit is set when the IROT is enabled in the
CMCR, the IRO output will be asserted to the processor.
The Lower Counter (LC) holds the least significant B-bits of the
16-bit counter.
When the LC decrements below $00, 1 is borrowed from the
UC to load $FF into the LC.
The LC is read to the data bus (00-07) when the register
address is 2 and PJW is high. When LC is read, the B-bit contents of the UC is transferred to the Snapshot Latch w~hout
affecting the operation of the counter (i.e., the count-down continues w~hout interruption).
MODE O-DISABLE ,COUNTERITIMER
The Counter/Timer is disabled (all counting stops), the IROT
interrupt (bit 7 in the CMCR) is disabled, and the counter underflow (bit 7 in the SR) is cleared. Mode 0 may be selected at any
time by selecting Mode 0 in the CMCR or upon RES which
initializes the CMCR to $00. Selecting Mode 0 in the CMCR
does not affect any data in the LL or UL, any count in the LC
or UC, or any dilla in the SL.
UPPER COUNTER
The Upper Counter (UC) holds the most significant B-b~s of the
16-bit counter. The UC is read to the data bus (00-07) when
the register address is 1 and R/iN is high. When the, UC is read,
there is no other effect on the Counter/Timer operation. Counter
underflow occurs when the LC borrows a 1 from the UC value
of $00.
'
MODE 1-0NE SHOT INTERVAL TIMER
The counter counts down once from the latch value at the 02
clock rate (as scaled by the Prescaler) and sets the UF bH in
the SR upon underflow. The counter starts when data is wrHten
to the UL at register address 0, .which causes the UL and LL
values to be loaded into the UC and LC, respectively. When the
counter decrements below $0000, the UF bit in the SR is set.
The set UF bit causes IRO to be asserted if the IROT Enable
bit is set in the CMCR. Upon decrementing below $0000, the
UC and LC are automatically reset to a value of $FFFF and the
counter continues down-counting. However, the UF bit in the
SR will not be set again (due to the counter again decrementing
through $0000) until the UL is again wrHten at register address
O. The CNTR line is not used in this mode. Figure 6 shows the
timing relationship for Mode 1 operation.
Note:
When reading the UC directly, the value read can be one
count too high if the LC value is just above $0000 at the
start of the read since an underflow in the LC will result'
in decrementing the UC by one count. The Snapshot
Latch should be read to obtain the UC value corresponding to the LC value.
SNAPSHOT LATCH (SL)
The Snapshot Latch holds the value of the UC corresponding
to the LC value. The SL is loaded w~h the value of the UC when
the LL is written to, or when the LC is read. The SL is read to
the data bus (00-07) when the register address is 0 and RlW
is high, w~hout affecting the counting operation. When the SL
is read, the UF in the SR is cleared. Since .the SL is loaded with
the value of the UC whenever the, LC is read, an aCcurille count
of the total 16-bit counter can be made w~hout the need for
further calculations to account for delays between the reading
of the, LC and the UC.
Typical Application: Can be used for an accurate time delay
such as would be required to control the duration of time to have
a thermal printer element activated.
MODE 2~FREE"RUN INTERVAL TIMER
The counter repetitively counts down at the ¢2 clock rate, as
scaled. ,by the Prescaler, and sets the UF bH in the SR each time
the counter underflows. The counter is in~ialized to the UL and
LL values and starts down counting ill the clock rate when the
UL value is wrHten to register address O. Each time the counter
decrements below $0000, the UF bH in the SR is set, the counter
is reloaded wHh the UL and LL value, and the count-down cycle
continues. If the IROT Enable bH is set in the CMCR, iRa will
thus be asserted upon each time-out. The CNTR line is not used
in this mode. Figure 7 shows the timing relationship for Mode
2 operation.
COUNTER/TIMER OPERATION
The CounterlTimer has eight modes of operation. The Counter/
Timer is always either disabled (mode 0) or operating in one of
the other seven modes as selected in the Counter Mode Control
Register (CMCR).
To operate the Counter/Timer, first issue Mode 0 to stop any
counting in progress due to a previously selected mode, to clear
the counter underflow bit in the SR and to disable the IROT
interrupt. The order of mode selection and latch loading depends
upon the desired mode. Generally, if a timer mode based on the
¢2 clock rate is to be selected, first select the mode then wrHe
the timer initialization value to the latch. Write the LL first then
the UL value (to register address 0). When the UL is wrHt!!n, the
Typical Application: Can be used for a timed interrupt structure when a hardware location needs updating at specific intervals, such as would ,be required to update a multiplexed display.
2-239
II
,
Peripheral Interface Adapter/Timer (PlAT)
R65C24
0
2
WRITE
-~~:---'-tl"".-·~-~-~;Ll-:
----I
/1--------1/
~----------~ ~~»~----------~,~~------~------------
StATUS _____
__
REGISTER
«
l
READ
SNAPSHOT------------------------q~~----------.(¥~-------J,
LATCH
1 \~.---------
FigureS. Mode 1-0he·Shot Interval Timer Timing
WRI;:~~·
"nn-ng"tul-i~
UPPE~A~~~C:,
'~t'.'
'.
IRQ
.
READ
.....
-
. N+2·
CYCLES·
STATUS
REGISTER
SNA~:~
'.
:
.
.
N..
?l
./
N-
(~
('
. N + 1 CYCLES
~~)
. '-t. __________.)~)----------------------tl
't))
,~.
t','
,V
)
?\~,~)--------~--------------
LATCH
Figure 7. Mode 2-Free·Run Intenial Timer Timing
2·240
Peripheral Interface Adapter/Timer (PlAT)
R65C24
MODE 3-PULSE WIDTH MEASUREMENT
MODE 4-EVENT COUNTER
The counter counts down from the latch value at the ¢2 clock
rate (scaled by the Prescaler) from the time the CNTR input
goes low until CNTR goes high to provide a measurement of
the CNTR low pulse duration. The counter is loaded with the
value of the UL and LL upon writing UL to register address O.
The counter starts decrementing at the scaled 1212 clock rate
when the CNTR line goes low and stops decrementing when
the CNTR line returns high. If the counter decrements below
$0000 before the CNTR line goes low, the UF bit in the SR is
set, the counter is reloaded with the UL and LL value, and the
cycle continues down until CNTR goes high. Once the CNTR
line has cycled from high to low and back to high, the Counter/
Timer will ignore any additional high to low transitions on the
CNTR line. To reinitiate Mode 3, it is necessary to reload the
UL by writing to register address O. Figure 8 shows the timing
relationships for a Mode 3 operation.
CNTRis an input and the Counter/Timer counts the number oj
positive transttions on CNTR. The counter is initially loaded with
the UL and LL value when the UL is written to register address
O. The counter then decremeRts one count on the rising edge
of the ¢2 clock after a rising edge .(Iow to high transition) is
detected on the CNTR input (as scaled by the Prescaler). The
maximum rate at which this rising edge can be detected is onehalf the ¢2 clock rate. When the counter decrements below
$0000, the UF bit in the SR is set, the counter is reloaded with
the UL and LL value and the operation repeats. Figure 9 shows
the timing relationship of a Mode 4 operation.
Typical Application: Can be used with a timed software loop
to count external events (i.e., a frequency counter).
Typical Application: Can be used to measure the duration of
an event from an external device. Allows an accurate measurement of the duration of a logical low pulse on the CNTR line.
J'
_, _, _; _. ~i) ~~.........\'-___
I I I I
L
TIME;R DOES NOT DECREMENT
...L.._----,I
Figure 8. Mode 3-Pulse Width Measurement Timing
<1>2
CNTR
~'-'
-+-r---"
....Jlr+-!I
____
COUNTER
DECREMENTED
III
' - - - - -..... COUNTER
,
Ir---l~----'
'------....
DECREMENTED
PAST $0000, UF BIT SET
AND UC, LC RELOADED FROM UL, LL
"COUNTER
DECREMENTED
1
,'--_ _ _ _ _..J
READ
r---\
SNAPSHOT----------------------------~/
LATCH
Figure 9. Mode 4-Event Counter Timing
2-241
. ,~-----
II
Peripheral Interface Adapter/Tlmer (PlAT)
R65C24
MODE 5-0NE-SHOT PULSE WIDTH GENERATION·
(if low upon mode selection) when data is written to the· UL at
register address 0 which also starts the counter. The counter
decrements at the ¢2 clock rate as S9aled by the.Prescaler.
When the counter ~ecrernents.below $0000; CNTR toggles from
low to high (or high to low depending upon its initial state), the
counter is reloaded with the UL and LL value and the counter
continues down-counting. The UF bit in the SR is set the first
time the counter decrements past $0000 and is cleared only if
a new write to UL at register address 0 occurs. Figure 11 shows
the timing relationship of a Mode 6 operation.
CNTR is an output which can be pulsed low for a programmed
time interval. When this mode is selected in the CMCR, the
CNTR output goes high "(if the UFbit is set) or goes low (if the
UF bit is cleared). The CNTR line then goes low when data is
written to the UL at register address 0, which also starts the
counter. The counter decrements from the UL and LL value at
the .¢2 clock rate as scaled by the Prescaler. When the counter
decrements below $0000. theCNTR .output goes high, the UF
bit is set in the SR, the counter is reloaded with $FFFF and the
count-down.coi'ltinues. Figure 10shows.the timing relationship
of Mode 5 operation.
.
• .
This mode can be used to generate an ~yrrimetrical waveform
by toggling .the UL and LL with the CNTR high and low times.
Immediately after starting the counter with the first CNTR low
ti.me, load the LL and UL (by writing to register address 1, which
does not re$tart the counter) with the CNTR high.time. Wheri
the first counter underflow occurs, the counter loads the new
latch value (i.e., the CNTR high time) into the counter and continues counting. During the IRQ interrupt processing resulting
from the first counter time-out, load the LL and UL (at register
address 1) with the original CNTR low time. Continue to alfernate loading of the high and low time latch values during the
interrupt processing for the duration of the mode.
Note that clearing the UF bit after it is set upon the first timeout
causes CNTR to go low, in which case CNTR will again go high
upon the next counter timeout.
Typical Application: Can be used to hold-off (delay) an extemal
hardware event on an asynchronous basis such as disallowing
a motor startup until certain parameters are met.
MODE 6-FREE-RUN PULSE GENERATION
CNTR is an output and the Counter/Timer can be programmed
to generate a sYmmetrical waveform, an asymmetrical waveform, or a string of varying width pulses onCNTR. The CNTR
line is forced low (if high upori mode selection) or remains low
Typical Application: Can be used to supply external. circuitry
with a software variable clock based upon the system ¢2 clock
(e.g., a tone generator for audio feedback).
figure 10. Mode 5-0ne-Shot Pulse Width Generation Timing
<1>2
_ ...._ _ N+1
N + 1
CYCLES
Figure
CYCLES
11. Mode 6-free-Run Pulse Generation Timing
2-242
Periphe~allnterfac~AdapterlTimer
R65C24
MODE 7-RETRIGGERABLE INTERVAL TIMER
LDA
STA
LDA
STA
The Counter/Timer operates as a timer which is retriggered, Le.,
reinitialized to its starting value, upon detection of a negative
transijion on the CNTR input. The counter is initially loaded with
the UL and LL value when the UL is wrnten to register address
O. The counter statts decrementing at the \212 clock rate (as
scaled by the Prescaler) Wheri a falling edge (high to low transition) is detected on CNTR. The counter is reinitialized to the
UL and LL value whenever a falling 'edgeis subsequently
detectlld on CNTR. If the counter decrements pa'st$OOOO before
the falling edge is detected, the UF bit is set in the SR, thll
counter is initialized to the UL and LL value and the count-down
continues.
#$Iovalue
LL
#$hivalue
ULEC
(PlAT)
; lower latch value
;write to lower latch
;upper latch value
, ;writeto upper latch
;clear underflow flag, and enable
counter
The following instructions is a way to change modes while the
Counter/Timer is in operation:
LOA
#$mode
STA
CMCR
;select desired mode, except
mode 0
;write to mode register
The change of mode operation will take effect immediately.
Thus, the Free-Run Internal Timer mode (Mode 2) could be systematicallystopped by changing to the One-Shot Interval Timer
mode (Mode 1). The. Counter/Timer will then halt operation
wilen the underflow condition occurs. This technique can also
be used to enable or disable IRO during program execution.
Typical Application: Can be used to monitor signals that should
be periodic and can interrupt the processor if the signal being
monitored does not occur within a specified time frame; such
as a synchronous motor that has fallen out of synchronization.
PRESCALER
READING THE COUNTER/TIMER
The Counter/Timer operates in either the divide by one or divide
by sixteen mode. In the divide by one mode, the counter holds
from 1 to 65,535 counts. The counter capacity is therefore 1 /LS
to 65,535,..s at 1 MHz \212 clock rate or 0.25 ,..s to 16,383 /LS
at a 4 MHz \212 clock rate. Timer intervals greater than the maximum counter value can be easily measured by counting underflow flags or IRO interrupt requests.
To service an interrupt request, the following sequence can be
used:
BIT
BNE
LDA
.LOX
The divide by sixteen prescaler can be enabled to extend the
timing interval by 16. This provides timing from 1048.56 ms (1
MHz) to 260.21 ms (4 MHz). The prescalerclocks the Counter/
Timer at the \212 clock rate divided by sixteen, except for Mode
4. In Mode 4, sixteen positive CNTR. edges must occur to decrement the Counter/Timer by one count.
$status
error
$LC
$SL
;get underflow flag
;check if flag is set
;get low counter value for overflOW
;get high counter value for overflow
;underflow flag is cleared
By reading the LC and SL, it is possible to determine the amount
of time between the interrupt request and servicing the interrupt.
To read a timer value at any time, the suggested technique is
as follows:
LDA
$LC
INITIALIZING tHE COUNTERfTlMER
;get low counter value
;upper counter transferred to
sna~hot
The following program segment is one suggested technique for
initializing the Counter/Timer:
LDA
$SL
; any miscellaneous code to store
value if desired
;get high counter value
; Data Definition
= $XXXO
= $XXX1
= $XXX2
= $XXX3
= $XXXO
= $XXX1
= $XXX2·
=$XXX3
;Snapshot Latch
;Upper Counter
;Lower Counter
;Status Register
; Upper Latch and Enable Counter
;Upper Latch
; Lowe r Latc h
;Counter Mode Control Register
LDA
STA
LDA
#$modeO
CMCR
#$mode
STA
CMCR
;disable Counter/Timer
;write to mode register
;select mode and Prescaler and
IROT enable/disable
;write to mode register
SL
UC
LC
SR
ULEC
UL
LL
CMCR
READIWRIl'E TIMING
CHARACTERISTICS OF PlAT
Figure 12 is a timing diagram for theR65C24 PlAT during a
Read op(jration (input mode). Figure 13 isa timing diagram for
the PlAT durilJg a Write operation {outpl1t mode). Table 5 shows
the characteristics of the times shown in. Fi~ures 12 and 13.
; Program
2-243
R65C24
Peripheral Interface Adapterrrimer (PlAT)
CNTR~----..
. UNDERFLOW MUST
OCcUR BY 'tHIS TIME TO,
,SET UNDERFLOW FLAG
f - - - - - - , - ' TIME DEC~MENTS, POSSIBLE TO'----I------'--TIMER STILL DECREMENTS
IF NO UNDERFLOW HAS
SET UNDERFLOW FLAG
OCCURRED
Figure 12. Mode 7-Retrlggerable Interval rimer Timing
2 _________-'1
RSO, RS1, RS2
~50000QI
~_
-+___+ _______+-__________
_
DO-D7
DATA IN
CA2
(PULSE OUT)
CA1
CA2
(HAND SHAKE)
Figure 13. Read Timing Diagram
2-244
Peripheral Interface AdapterfTimer (PlAT)
R65C24
II
SSD, RS1, RS2
CSO, CS2
RIW
DD-D7
DATA OUT _ _ _ __
Vcc -3D%
PAD-PA7
PSD-PB7
~~~~~~~~~~t------1-------------
,"~~~:.o.c.c.::.~;.Jff 11~+-------+-----------
CS2
(PULSE OUT)
CB1
--------------rr--------------~
CS2
(HAND SHAKE)
Figure 14_ Write Timing Diagram
READING THE PERIPHERAL A I/O PORT
when the Peripheral Output register contains a logic 1. In this
case, the processor will read a 0 from the Peripheral A pin, even
though the corresponding bit in the Peripheral Output register
is a 1.
Performing a Read operation with RS1 = 0, RSO = 0 and the
Data Direction Register Access Control bit (CRA-2)= 1, directly
transfers the data on the Peripheral A VO lines to the data bus.
In this situation, the data bus will contain both the input and
output data. The processor must be programmed to recognize
and interpret only those bits which are important to the particular
peripheral operation being performed.
READING THE PERIPHERAL B 1/0 PORT
Reading the Peripheral B VO port yields a combination of input
and output data in a manner similar to the Peripheral A port. .
However, data is read directly from the Peripheral B Output
Register (ORB) for those lines programmed to act as outputs.
It is therefore possible to load down the Peripheral B Output
lines without causing incorrect data to be transferred back to the
processor on a Read operation.
Since the processor always reads the Peripheral A VO port pins
instead of the actual Peripheral Output Register (ORA), it is possible for the data read by the processor to differ from the contents of the- Peripheral Output Register for an output line. This
is true when the VO pin is not allowed to go to a full +2.4V DC
2-245
R65C24
Peripheral Interface Adapter/Timer (PlAT)
BUS TIMING CHARACTERISTICS
1MHz
Parameter
2MHz
Symbol
Min
Max
4>2 Cycle
Tcvc
1.0
4>2 Pulse Width
Ie
480
-
4>2 Rise and Fall Time
trOt t,c
-
Min
3MHz
Max
. Min
Min
Max
Unit
0.33
-
0.25
180
-
120
-
ns
12
10
ns
-
ns
75
ns
-
ns
240
-
25
-
15
-
-
70
-
53
0.5
4MHz
Max
-
p.S
READ TIMING
Address Set-Up Time
tACA.
140
Address Hold Time
tCAR
0
-
110
-
190
-
100
20
-
20
-
-
Peripheral Data Set-Up Time
tpCR
300
Data Bus Delay Time
tCOR
-
Data Bus Hold Time
tHR
20
-
395
0
150
-
0
35
0
75
20
ns
ns
WRITE TIMING
Address Set-Up Time
tAcw
140
-
70
-
53
53
tCAW
0
-
0
0
-
0
RIW Set-Up Time·
Iwcw
180
-
-
-
Address Hold Time
90
-
67
-
0
0
45
-
ns
ns
ns
RIW Hold Time
tcww
0
90
67
-
ns
180
45
tHW
10
10
-
10
10
Peripheral Data Delay Time
!cpw
-
1.0
-
-
-
ns
Data Bus Hold Time
-
-
-
tDcw
-
0
Data Bus Set-Up Time
0.5
-
0.33
-
0.25
p.S
tCMOS
-
2.0
-
1.0
-
0.7
~
0.5
"S
Peripheral Data Delay Time
to CMOS Level
ns
PERIPHERAL INTERFACE TIMING
1MHz
Parameter
Symbol
2MHz
3M Hz
4MHz
Min
Max
Min
Max
Min
Max
Min
Max
Unit
-
150
-
110
-
75
-
ns
0.25
"s
0.25
"s
0.5
"s
0.25
"S
Peripheral Data Setup
tpCR
300
4>2 Low to CA2 Low Delay
tCA2
-
1.0
2 Low to CA2 High Delay
tRs,
-
1.0
CA 1 Aclive to CA2 High Delay
I RS2
-
2.0
2 High 10 CB2 Low Delay
!cS2
-
Peripheral Dala Valid to CB2 Low Delay
toe
2 High to CB2 Hgh Delay
CB1 Active to CB2 High Delay
tRS'
t RS2
CA1, CA2, CB1 and CB2
Input Rise and Fall Time
Ir.lf
0.5
-
0.33
-
0.5
-
0.33
1.0
-
0.67
1.0
-
0.5
-
0.33
-
0
1.5
0
0.75
0
0.5
0
0.37
p.S
-
1.0
0.5
-
0.33
-
0.25
"s
-
2.0
-
1.0
-
0.67
-
0.5
"s
1.0
-
1.0
-
1.0
"s
1.0
2-246
R65C24
Peripheral Interface Adapterrrimer (PlAT)
ABSOLUTE MAXIMUM RATINGS*
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 to +7.0
Vde
Input Voltage
Y'N
VOUT
-0.3 to Vee +0.3
Vde
-0.3 to Vee +0.3
Vde
Parameter
Output Voltage
Operating Temperature
Commercial
Industrial
TA
Storage Temperature
TSTG
• Note: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
°C
o to
+70
-40 to +85
-55 to + t50
°C
OPERATING· CONDITIONS
Symbol
Value
Supply Voltage
Parameter
Vee
5V ±5%
Temperature Range
Commercial
Industrial
TA
0° to 70°C
-40· to +85°C
DC CHARACTERISTICS
Vee = 5.0V ±5%, Vss = 0, TA = TL to TH, (unless otherwise noted)
Parameter
Symbol
Min
Typ3
Max
Unit'
V'H
+2.0
-
Vee
V
V'L
-0.3
-
+0.8
V
±I
±2.5
pA
V'N = OV to Vee
Vee = S.25V
±IO
p.A
Y'N = O.4V to 2.4V
Vee = S.25V
pA
V,H = 2.4V
-3.2
rnA
V,L = 0.4V
-
V
V
+0.4
V
Input High Voltage
Input Low Voltage
Input Leakage Current:
Rm, RES, RSO, RSI, RS2, CSO, CS2, CAl,
CBI, <1>2
I'N
-
Input Leakage Current lor Three-State Off
00-07, PBO-PB7, CB2
ITSI
-
±2
Input High Current
PAO-PA7, CA2
I'H
Input Low Current
PAO-PA7, CA2
I,L
Output High Voltage
Logic
PBO-PB7, CB2 (Darlington Drive)
VOH
Output Low Voltage
PAO-PA7, CA2, PBO-PB7, CB2
00-07, IRQ, CNTR
VOL
Output High Current (Sourcing)
Logic
PBO-PB7, CB2 (Darlington Drive)
10H
Output Low Current (Sinking)
PAO-PA7, PBO-PB7, CB2, CA2
00-07, IRQ, CNTR
10L
Output Leakage Current (Olf State):
IRQ
-200
-400
-
-2
2.4
1.5
-
-
-
-
-
-
-200
-3.2
-1500
-6
-
rnA
3.2
1.6
-
-
rnA
rnA
10FF
-
I
±IO
pA
-
7
10
mW/MHz
-
-
-
10
7
20
pF
pF
pF
-
10
pF
Power Dissipation
Po
Input CapaCitance
00-07, PAO-PA7, PBO-PB7, CA2,CB2,CNTR
Rm, RES, RSO, RSI, RS2, CSO,CS2
CAl, CBt, <1>2
C'N
Output CapaCitance
COUT
-
Noles:
I. All units are direct current (de) except for capacitance.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. Typical values are shown for Vee = S.OV and TA = 25·C.
2-247
pA
Test Conditions
Vee = 4.7SV
ILOAD = 200pA
ILOAD' = -3.2 rnA
Vee = 4.75V
ILOAD = 3.2 rnA
ILOAD = 1.6 rnA
VOH = 2.4V
VOH = 1.5V
VOL = 0.4V
VOH = 2.4V
Vee = 5.25V
Vee = 5.0V
Y'N = OV
1= 2 MHz
TA = 25·C
II
R65C24
Peripheral Interface Adapterrrimer (PlAT)
PACKAGE DIMENSIONS
40-PIN CERAMIC DIP
[: D JII
MILLIMETERS
1M MIN MAX
A
50.29 51.31
14.86 15.62
B
2.54
4.19
C
0.38 0.53
0
F
0.76 1.40
2.54'BSC
G
H
0.76
1.78
O.~O
033
J
2.54
4.19
K
14.60 15.37
L
M
0'
10"
N
051
1.52
f4-1~
. =--=--=-=A=====:~I
W
F
INCHES
MIN
MAX
1.980 2.020
0.585 0.615
0.100 0.165
0.015 0.021
0.030 0.055
0.100 sse
0.030 0,070
0.008 0.013
0.'1(10 0.165
0.575 0.605
10'
0"
o.o~o
0.060
40-PIN PLASTIC DIP
MILLIMETERS
DIM MIN MAX
51.28 52.32
A
B
13.72 14.22
3.55
C
508
0.36 0.51
D
1.02
152
F
2.54 sse
G
1.65
2.16
H
0.30
J
o.~o
3.05
3.56
K
15.24 sse
L
M
7'
10'
051
1.02
N
2-248
INCHES
MAX
MIN
2040 2.060
0.540 0.560
0.140 o.~oo
0.014 0.020
0.040 0.060
0.100 sse
0.065 0.085
0.008 0.012
0.120 0.140
0.600 SSC
7'
10
0.020 0040
R6se5,1
'1'
R65C51
ASYNCHRONOUS COMMUNICATIONS
INTERFACE ADAPTER (ACIA)
Rockwell
DESCRIPTION
FEATURES
The Rockwell CMOS R65C51 'Asynchronous Communications
Interface Adapter (ACIA) provides ar(easlly implemented, prpgram controlled interface between a-bit microprocessor~based
systems and serial communication data. sets and modems.
• Low power CMOS N-well siliqon gate technology
•• Direct replacement for NMOS R6551 ACIA
• Full duplex operation with buffered receiver and :transmitter
• Data set/modem control.functions
• Internal baud rate generator with 15 programmable baud
rates (50 to 19,200) ~
• Program-selectable internally or externally controlled receiver
rate
• Programmable word lengths, number of stop bits, and parity
bit generation and detection
• Programmable interrupt control
The ACIA has an internal baud rate generator. This feature eliminates the need for muttiple component support circuits, a ctyst!l-I
being the only other part required. The Transmitter baud raie
can be selected under"progtam control to be either 1 of 15 different rates from 50 to 19,200 baud,or at 1/16 times an external
clock rate. The Receiver baud rate may be selected under pro-.
gram control to be either the Transmitter rate, or at 1/16 times
the external clock rate. The ACIAbas programmable word
lengths of 5, 6, 7, or 8 bits; even;' odd, or no parity; 1, 1V2, or
2 stop bits.
The ACIA is designed for maximum programmed control from
the microprocessor (MPU), to simplify hardwareimplementation. Three separate registers permifthe MPU to easily select
the R65C51 's operating modes and data checking parameters
and determine operational status.
The Command Register controls parity, receiver echo mode,
'transmitter interrupt control, the state of the RTS line, receiver
interrupt control, and the state of the DTR line.
•
•
•
•
•
•
•
•
Program reset
Program-selectable serial echo mode
Two chip selects
2 or 4 MHz operation
5.0 Vdc ± 5% supply requirements
28-pin plastic or ceramic DIP
Full TTL compatibility'
Compatible with R6500, R6500/* and R65COO microprocessors
The Control Register controls the number ·of stop bits, word
length, receiver clock source, and baud rate,
The Status Register indicates the states of the IRQ, DSR, and
DCD lines, Transmitter and Receiver Data Registers, and
Overrun, Framing, and Parity Error conditions.
The lransmitterand Receiver Data Registers are used for temporary data storage by the ACIA Transmit and Receiver circl,lits.
VSS
CSO
ffi
RES
RxC
XTLI
XTLO
RTS
CTS
TxO
DTR
RxO
RSO
RS1
ORDERING INFORMATION
IL T"'.".~
Part No.: R65CSL __
""""
~ ,.; T.'
Blank = COC
to + 70°C
E = ~4O"C to + 85°C
Frequency Range:
1 = 1 MHz
2=2MHZ
3 = 3MHz'
4 = 4 MHz
RJW
2
'2
3
IRQ
07
06
05
4
5
6
7
8
9
10
.11
12
13
14
04
03
02
01
00
DSR
OCO
VCC
-Package:
C = Ceramic
P =PliIstic
Figure 1.
Document No. 29651N60
R6SCS1 ACIA PI.n Configuration
Product Description Order No. 2157
Rev. 2, February 1984
2-249
D
Asynchronous Communications Interface Adapter (ACIA)
R65C51
,
I.
.~
00-07
IRQ
DATA
BUS
BUFFER
INTERRUPT
LOGIC
~
--
-,..
;:>J
I
N
T
E
R
N
A
~
'2
RES
1/0
CONTROL
~
TIMING
& CONTROL
.·STATUS
REGISTER
t.
D
A
T
A
B
U
S
RIW
. CSO.
CS1
RSO
RS1
TRANSMIT
DATA
REGISTER
jo
J
~
;:>I
CONTROL
REGISTER
I
CTS
TRANSMIT
SHIFT
REGISTER
~TXD
DCD
DSR
RxC
BA4D
RATE
t---.XTLI
GENERATOR ~XTLO
I-+----
DTR
COMMAND
REGISTER
I DATA
RECEIVE
-
TRANSMIT
CONTROL
REGISTER
RECEIVE
SHIFT
REGISTER
•
RECEIVE
CONTROL
Figure 2.
r-r-
RTS
RxD
J-
ACIA Internal Organization
FUNCTIONAL DESCRIPTION
TIMING AND. CONTROL
A block diagram of the ACIA is presented in Figure 2 followed
i:1y a description of each functional element of the device.
The Timing and Control logic controls the timing of data transfers on the internal data bus and the. registers, the Data Bus
Buffer, and the microprocessor data bus, and the hardware
reset features.
DATA BUS BUFFERS
The Data Bus Buffer interfaces the system data lines to the
internal data bus. The Data Bus Buffer is bi-directional. When
ihe RJW line is high apd the chip is selected, the Data Bus Buffer
passes the data from the system data. lines to the ACIA internal
data bus. When the RJW line is low and the chip is sel.ected, the
Data Bus Buffer writes the data from the internal data bus to the
system data bus.
Timing is controlled by the system ~2 clock input. The chip will
perform data transfers to or from the microcomputer data bus
during the ~2 high period when selected.
All registers will be initialized by the Timing and Control Logic
when the Reset (RES) line goes low. See the individual register
description tor the state of the registers following a hardware
reset.
INTERRUPT LOGIC
The Interrupt Logic will cause the IRQ line to the microprocessor
to go 16w when conditions are met that require the attention of
the microprocessor. The conditions which can cause an interrupt will set bit 7 and the appropriate bit of bits 3 through 6 in
the Status Register, if enabled. Bits 5 and 6 correspond to the
Data Carrier Detect (DCD) logic and the Data Set Ready (DSR)
logic. Bits 3 and 4 correspond to the Receiver Data Register full
and the Transmitter Data Register empty conditions. These conditions can cause aD interrupt request.if enabled by the Command Register.
TRANSMittER AND RECEIVER DATA REGISTERS
These registers are used astemporary data storage for the
ACIA Transmit and Receive Circuits. Both the Transmitter and
Receiver are selected bya Register Select 0 (RSO) and Register
Select 1 (RS1) low condition. The Read/Write (RJiiii) line determines which actually uses the internal data bus; the Transmitter
Data Register is write only and the Receiver Data Register is
read only.
Bit 0 is the first bit to i:1e transmitted from the Transmitter Data
Register (least significant bit first). The higher order bits follow
in order. Unused bits in this register are "don't care".
I/O CONTROL
The VO Control Logic controls the selection of internal registers
in preparation for a data transfer on the internal. data bus and
the direction of the transfer to or from the register.
The Receiver Data Register holds the first received data bit in
bit 0 (least significant bit first). Unused high-order bits are "0".
Parity bits are not contained in the Receiver Data Register. They
are stripped off after being used for paritychecking.
The registers are selected by the Receiver Select (RS1, RSO)
and ReacVWrite (RJW) lines as described later in Table 1.
2-250
Asynchronous Communications Interface Adapter (ACIA)
R65C51
STATUS REGISTER
Parity Error (Bit 0), Framing Error (Bit 1), and
Overrun (2)
The Status Register indicates the state of interrupt conditions
and other non-interrupt status lines. The interrupt conditions are
the Data Set Ready, Data Carrier Detect, Transmitter Data Register Empty and Receiver Data Register Full as reported in bits
6 through 3, respectively. If any of these bits are set, the Interrupt (IRQ) indicator (bit 7) is also set. Overrun, Framing Error,
and Parity Error are also reported (bits 2 through 0 respectively).
7
6
5
4
3
2
None of these bits causes a processor interrupt to occur, but
they are normally checked at the time the Receiver Data Register is read so that the validity of the data can be verified. These
bits are self clearing (i.e., they are' automatically cleared after
a read of the Receiver Data Register).
o
Receiver Data Register Full (Bit 3)
PE
Bit7
0
I nterrupt (I RQ)
No interrupt
Interrupt has occurred
Bit 6
0
Data Set Ready (OSR)
DSR low (ready)
DSR high (not ready)
Bit 5
0
Data Carrier Detect (OCO)
DCD low (detected)
DCD high (not detected)
Bit 4
0
Transmitter Data Register Empty
Not empty
Empty
Bit 3
0
1
Receiver Data Register Full
Not full
Full
Bit 2
0
1
Overrun'
No overrun
Overrun has occurred
Bit 1
0
1
Framing Error'
No framing error
Framing error detected
Bit 0
0
Parity Error'
No parity error
Parity error detected
This bit goes to a 1 when the ACIA transfers data from the
Receiver Shift Register to the Receiver Data Register, and goes
to a 0 (is cleared) when the processor reads the Receiver Data
Register.
Transmitter Data Register Empty (Bit 4)
This bit goes to a 1 when the ACIA transfers data from the
Transmitter Data Register to the Transmitter Shift Register, and
goes to a 0 (is cleared) when the processor writes new data
onto the Transmitter Data Register.
Data Carrier Detect (Bit 5) and Data Set Ready
(Bit 6)
These bits reflect the levels of the DCD and DSR inputs to the
ACIA. A 0 indicates a low level (true condition) and a 1 indicates
a high level (false). Whenever either of these inputs change
state, an immediate processor interrupt (IRQ) occurs, unless btt
1 of the Command Register (IRD) is set to a 1 to disable IRQ.
When the interrupt occurs, the status bits indicate the levels of
the inputs immediately after the change of state occurred. Subsequent level changes will not affect the, status bits until the
Status Register is interrogated by the processor. At that time,
another interrupt will immediately occur and the status bits
reflect the new input levels. These bits are not automatically
cleared (or reset) by an internal operation.
Interrupt (Bit 7)
• No interrupt occurs for these conditions
This bit goes to a 1 whenever an interrupt condition occurs and
goes to a 0 (is cleared) when the Status Register is read.
Reset Initialization
76543210
I~I=I=I~I~I ~I~I~I
Hardware reset
Program reset
2-251
II
Asynchronous Communications Interface Adapter (ACIA)
R65C51
CONTROL REGISTER
Selected Baud Rate (Bits 0, 1, 2, 3)
The Control Register selects the desired baud rate. frequency
source, word length, and the number of stop bits.
These bits select the Transmitter baud rate, which can be at
'/,6 an external clock rate or one of 15 other rates controlled by
the internal baud rate generator.
If the Receiver clock uses the same baud rate as the transmitter,
then RxC becomes an output and can be used to slave other
circuits to the ACIA. Figure 3 shows the Transmitter and ReceiVer
layout.
Stop Bit Number (SBN)
Bit 7
o
1 Stop bit
2 Stop bits
1Y2 Stop bits
For WL = 5 and no parity
1 Stop bit
For WL = 8 and parity
Bits 6·5
~2...
o
o
0
1
0
1
1
Bit 4
1
Bits 3·0
o
o
o
o
o
o
o
o
1
1
1
10
0
0
0
1
0
0
0
o
.....--RxD
Word Length (WL)
No. Bits
8
7
h.~===----- RxC
6
5
Receiver Clock Source (RCS)
External receiver clock
Baud rate
o
.2...
. .-
XTLI
XTLO
Selected Baud Aate (SBR)
..L JL Baud
16x
0
0
0
1
50
75
0
1
1
109.92
134.58
0
0
1
0
150
1
0
300
1
1
600
0
0
1200
1
1800
0
1
2400
0
1
1
3600
0
0
4800
1
7200
0
0
9600
1
19,200
Figure 3.
Transmitter/Receiver Clock Circuits
Receiver Clock Source (Bit 4)
This bit controls the clock source to the Receiver. A 0 causes
the Receiver to operate at a baud rate of '/,6 an external clock.
A 1 causes the Receiver to operate at the same baud rate as
is selected for the transmitter.
Word Length (Bits 5, 6)
Reset .Initialization
These bits determine the word length to be used (5, 6, 7 or 8
bits).
Hardware reset (RES)
Stop Bit Number (Bit 7)
Program reset
This bit determines the number of stop bits used. A 0 always
indicates one stop bit. A 1 indicates 1 Y2 stop bits if the word
length is 5 with no parity selected, 1 stop bit if the word length
is 8 with parity selected, and 2 stop bits in all other configurations.
2-252
R6SC61
Asynchronous Communications Interface Adapter (ACIA)
COMMAND REGISTER
Data Terminal Ready (Bit 0)
The Command Register control~ specifIC modes 'and functions.
This bit enables all selected inlerruptsarid controls the state of
the Data Terminal Ready (OTR)'line. A 0 indicates the microcomputer system is not ready by setting the OTR line high. A
1 indicates the microcomputer system is ready by setting the
OTR line low.
Bits 7-6
.1..
.§..
0
1
0
o
o
1
Bit 5
o
o
Odd par~y transmitted/received
Even par~y transmitted/received
Mark par~ bit transmitted
Parity check disabled
Space par~ bit transmitted
Parity cheCk disabled
Trahl~mltter
Parity MocIe E;nabled (PME)
Receiver Echo Mode (Bit 4)
o
A 1, enables the Receiver Echo Mode and a
enables the
Receiver Echo Mode. When bit 4 is a 1 bits 2 and 3 must be
O. In the Receiver Echo Mode, the Transmitter returns each
transmission received by the Receiver delayed by one-half bit
time.
Receiver Echo Mode (REM)
Bits 3-2
3
2
Transmitter Interrupt Control (TIC)
0" 0-
RTS = High, transmit interrupt disabled
RTS = Low, transmit interrupt enabled
RTS = Low, transmit interrupt disabled
RTS = Low, transmit interrupt disabled
transm~ break on TxO
o
1
1
1
0
1
Bit 1
o
1
Bit 0
Interrupt Control (Bits 2, 3)
These bits control the state of the Ready to Send (RTS) line and
the Transmitter interrupt.
Receiver normal mode
Receiver echo mode bits 2 and 3
Must be zero for receiver echo mo~, RTS will
'
be low.
1
1
This bit disables the Receiver from generating an interrupt when
set to a 1. The Receiver interrupt is enabled when this bit is set
to a 0 and Bit 0 is setto a 1.
Parity mode disabled
No parity bit generated
Par~y check disabled
Parity mode enabled
Bit 4
o
Receiver Interrupt Control (Bit 1)
Parity Mocie Control (PMC)
Parity Mode Enable (Bit 5),
This bit enables parity bit generation and cheeking.A 0 disables
parity bit generation by the Transmitter and parity bit checking
by the Receiver. A ,1 b,1t enables generation and checking of
parity bits.
Parity Mode, Control (Bits 6, 7)
These bits determine the type of parity generated by the Transmitter, (even, odd, mark or space) and the type of parity check'
done by the Receiver (even, odd, or no check).
Interrupt Request Disabled (IRD)
IRQ enabled
iRQ disabled
Data Terminal Ready (DTR)
Data terminal not ready (OTR high)
Data terminal ready (OTR low)
Reset Initialization
76543210
I~I~I~I ~ I~ I~ I~ I~ 11=~:::.:e~=t (RES)
2-253
II
R65051
Async.hronous Communications-interface Adapter (ACIA)
INTERFACE SIGNALS
Interrupt Request (IRQ)
Figure 4 shows the. AOIA inter·face signals asspciated with the
miCroprocessor and the mOdem.
The IRQ pin is an interrupt output fr()m the interrupt control logic.
It is an open drain output, permitting several devices to be connected to ~common fRO micrQprocessor input. Normally a
high level, IRQ goes low when an interrupt occurs.
Data Bus (Oo-D7)
CTS
DO-D7
The eight data line (DO-D7) pins translerdata between the processor and the ACIA. These lines are bi-directlonal and are normally high-impedance except during Read cycles when the
ACIA is selected.
TxD
IRQ
RJW
DCD
CSO
DSR
CS1
RSD
RxC
RS1
XTLO
Chip Selects (CSO,
CSi)
The two chip select inputs are normally connected to the processor address lines: either directly or through decoders. The
ACIA'is selected when OSO is high and CSi is low. When the
ACIA is selected, the internal registers are addressed in accordance w~h the register select lines (RSO, RS1).
XTLI
112
,- ~
DfR
RES
-
Register Selects (RSO, RS 1)
RTS
The two register select lines are normally ,Connected to the processor addre~ lines, to allow the procesSor to select the various
ACIA internal registers. Table f shows th,e internal register
select coding.
RxD
Figure 4. ACIAlnteiface Diagram
Table 1. ACIA Register Selection
Register Op8J'atlon
MICROPROCESSOR INTERFACE
Reset (RES)
During system in~ialization a low on the REs input causes a
hardware reset to occur. Upon reset, the Command Register
and the Control Register are cleared (all bits set to 0). The
Status Register is cleared wtth the exception of the indications
of Data Set Ready and Data Carrier Detect, which are externally
controlled by the DSR and OeD lines, and the transmitter Empty
bit, which is set. RES must be held low for one Sif2 clock cycle
for a reset to occur.
R/W = High
RS1
RSD
R/W = Low
L
L
Write. Transmit Data
Register
Read Receiver
Data Register
L
H
Programmed Reset
(Data is "Don't
Care")
Read Status
Register
H
L
Write Command
Register
Read Command
Register
H
H
Write Control
Register
Read Control
Register
Input Clock (/12)
The input clock is the system ~2 clock and clocks all data tr.ansfers between the system microprocessor and the ACIA.
Only the command and Control registers can both be read and
written. The programmed Reset operation does not cause any
data transler, but is used to clear bits 4 through 0 in the Command register and bH 2 in the Status Register. The Control Register is unchanged by a programmed Reset. It should be noted
that the programmed Reset is slightly different from the hardware Reset (RES); reler to the register description.
Read/Wrlte (RJW)
The R/W input, generated by the microprocessor controls the
direction of data transfers. A high on the R/W pin allows the
processor to read the data supplied by the ACIA, a low allows
a write to the AOIA.
2-254
R65C51
Asynchronous Communications Interface Adapter (ACIA)
ACIAIMODEM INTERFACE
Clear to Send (CTS)
Crystal Pins (XTLI, XTLO)
The CTS input pin controls the transmitter operation. The enable
state is with C'fS low. The transmitter is automatically disabled
if CTS is high.
These pins are normally directly connected to the external
crystal (1.8432. MHz) to derive the various baud rates. Alternatively, an externally generated clock can drive the XTLI pin,
in which case 1he XTLO pin must float. XTLI is the input pin for
the transmit clock.
Data Terminal Ready (DTR)
This output pin indicates the· status of the ACIA to the modem.
A low on DTR indicates the ACIA is enabled, a high indicates
it is disabled. The processor controls this pin via bit 0 of the
Command Register.
Transmit Data (TxD)
The TxD output line transfers serial nonreturMo-zero (NRZ)
data to the modem. The least significant bit (LSB) of the Transmit
Data Register is the first data bit transmitted and the rate of data
transmission is determined by the baud rate selected or under
control of an extemal clock. This selection is made by programming the Control Register.
Data Set Ready (~)
The DSR input pin indicates to the ACIA the status of the
modem. A low indicates the "ready" state and a high, "notready."
Data Carrier Detect (DCD)
Receive Data (RxD)
The DCD input pin indicates to the ACIA the status of the carrierdetect output of the modem. A low indicates that the modem
carrier signal is present and a high, that it is not.
The RxD input line transfers serial NRZ data into the ACIA from
the modem, LSB first. The receiver data rate is either the programmed baud rate or under the control of an externally generated receiver clock. The selection is made by programming
the Control Register.
TRANSMITTER AND RECEIVER OPERATION
Continuous Data Transmit
Receive Clock (RxC)
In the normal operating mode, the interrupt request output (IRQ)
Signals when the ACIA is ready to accept the next data word to
be transmitted. This interrupt occurs at the beginning of the Start
Bit. When the processor reads the Status Register of the ACIA,
the interrupt is cleared.
The RxC is a bi-directional pin which is either the receiver 16x
clock input or the receiver 16x clock output. The latter mode
results if the internal baud rate generator is selected for receiver
data clocking.
The processor must then identify that the Transmit Data Reg-·
ister is ready to be loaded and must then load it with the next
data word. This must occur before the end of the Stop Bit, otherwise a continuous "MARK" will be transmitted. Figure 5 shows
the continuous Data Transmit timing relationship.
Request to Send (RTS)
The FiTS output pin controls the modem from the processor.
The state of the RTS pin is determined by the contents of the
Command Register.
,
Llll
Figure 5.
Continuous Data Transmit
2-255
II
Asynchronous Communications Interface Adapter (ACIA)
R65C51
Continuous Data Receive
read the data word before the next interrupt, otherwise the
Overrun condition occurs. Figure 6 shows the continuous Data
Receive Timing Relationship.
Similar to the Continuous Data Transmit case, the normal
operation of this mode is to assert fRQ when the ACIA has
received a full data word. This occurs at about 9/'6 point through
the Stop Bit. The processor must read the Status Register and
CHAR#n
.
RxD
/
CHAR#n+1
I
'.../
CHAR#n+2
!
,,/
!
"
lstart5"GJ ~ ~ rn~••IStart5"GJ: ~ rnSt·plStartfBOE] ~ ~ lSOEJSt.• lstart[qBJ ~ ~ 8jSto{
,
rna
CHAR#n+3
I
,/
I
I
1
I
I
I
I
I
'
I
I
I
LJI]
L
-.lU~'----;)u
mc
\' =====~=::/I/Llll
W
PROCESSOR
INTERRUPT OCC. URS
ABOUT 9/16 IIIITO
.
LAST STOP BIT.
PARITY. OVERRUN.
AND FRAMING ERROR
ALSO. UPDATED
PROCESSOR MUST READ
RECEIVIlER DATA IN THIS
PROCESSOR READS ~TUS
~g~I~!=. CAUSES IRO
Figure 6.
TIME INTERVAL; OTHERWISE.
OVERRUN OCCURS
Continuous Data Receive
Transmit Data Register Not Loaded by Processor
When the proCessor finally loads new data, a Start Bit immediately occurs, the data word transmission is started, and another
interrupt is initiated, signaling for the next data word. Figure 7
shows the timing relationship for this mode of operation.
If the processor is unable to load the Transmit Data Register in
the allocated time, then the TxD line goes to the "MARK"' condition until the data is loaded. IRQ interrupts' continue to occur
at the same rate as previously, except no data is transmitted.
CHAR# n
/
TxO
CONTINUOUS "MARK"
I "
RstartRBiI ~ 58 '·.1
iRa
I_CH~I~~TER_I
LJI]'
I
I
/~u
~~~~J~~~ "-"
~
FOR DATA
\
INTERRUPTS
REGISTER
EMPTY
PROCESSOR
CONTINUE AT
CHARACTER RATE,
EVEN THOUGH
READS
STATUS
REGISTER
NO DATA IS
TRANSMITTED
Figure 7.
CHAR#n+2
/~_ _ _ _'--_ __
"
lstartrn ~ ~ @~}topls.art[%F] ~ ~ EI
.-
s
I
CHAR #n+1
/
WHEN PROCESSOR FINALLY LOADS
NEW DATA, TRANSMISSION STARTS
IMMEDIATELY ANO INTERRUPT
OCCURS, INDICATING TRANSMIT
DATA REGISTER EMPTY
Transmit Data Register Not Loaded by Processor
2-256
I
Asynchronous Communications ,Interface Adapter (ACIA)
R65C51·
Effect of CrS on Transmitter
CTS is the Clear-to--Send signal generated by the modem. it is
normally low (true state) but may go high in the event of some
modem problems. When this occurs, the TxD line goes to the
"MARK" condition after the entire last character (including parity
and stop bit) have been transmitted. Bit 4 in the Status Register
indicates that the Transmitter Data Register is not empty and
IRQ is not asserted. C'fS is a transmit control line only\, and has
no effect on the ACIA Receiver Operation. Figure 8 shows the
timing relationship for this mode of operation.
CHAR#n
II
CONTINUOUS ''MARK''
T.D
/
lila IS NOT ASSERTED
NOT CLEAR-TO-SEND
AGAIN UNTIL 'IlTI
GOES LOW
CLEAR·TO.sEND
f
'IlTIGOESHIGH,
INDICATING MODEM
::E&RED'A~X.T-&D
GOES TO "MARK" CONDITION
AFTER COMPLETE CHARACTER
IS TRANSMITTED.
Figure 8. Effect of CTS on Transmitter
Effect of Overrun
on
Receiver
If the processor does not read the, Receiver data Register in the
allocated time, then, when the following interrupt occurs, the
new data word Is not transferred to the Receiver Data Register,
CHAR#n
~/
RKD
'
but the Overrun status bit is set. Thus, the Data Register will
contain the last valid data word received and all following data
is lost., Figure 9 shows the timing relationship for this mode ..
CHAR#n+1
.•
'-/
CHAR#n+Z
,I,.
,,/,,'
CHA,R#n+3
'-/
:
'
J:1s. "5"Gl~~LiliJ~..ls. rtr::-I5I~LiliJ~.I~."fBOE]~~·liEJs...l-fBOE]~~~
I
.
PROCESSOR
INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL
I
. I I
RECEIVER DATA REGISTER
NOT UPDATED. BECAUSE .
PROCESSOR DI D NOT READ
PREVIOUS DATA. OVERRUN
BIT SET IN STATUS
REGISTER
PROCESSOR
READS
STATUS
REGISTER
OVERRUN tilT SET IN
STATUS REGISTER
Figure 9. Effect of Overrun on Receiver
2-257
R65C51
Asynchronous Communications Interface Adapter (ACIA)
Echo Mode Timing
In Echo Mode, the TxD line re-trarismits the data on the· RxD
line, delayed by V:i of the bit time, as shown in Figure 10.
Figure 10.
Echo Mode Timing
Effect of CTS ol'l.Echo Mode Operation
In Echo Mode, the Receiver operation is unaffected. by CTS,
however, the Transmitter is affected when Ci'S goes high, i.e.,
the TxD line immediately goes to a continuous "MARK" condition. In this case, however, the S\atusRequest indicates that
the Receiver Data Register is full in response to an IRO, so the
processor has no way of knowing that the Transmitter has
ceased to echo. See Figure 11 for the timing relationship of this
mode.
CHAR#n+1
CHAR#n
CHAR#n+2
CHAR#n+3
NOT -CLEAR-TO-SEND
I
~E::[~I~I J
BN
I
I p s,opIS""1 BO I 8, I B~
CONTINUOUS "MARK" UNTIL
II
l_~"~)
"FALse" CONDITION
I
NORMAL
_
RECEIVER DATA
FULL
INTERRUPTS
REGISTER
Figure 11.
Effect of CTS on Echo Mode
2~258
ffi
GOES LOW
"-
R65C51
Asynchronous Communications Interface Adapter (ACIA)
Overrun In Echo Mode
If Overrun occurs in Echo Mode, the Receiver is affected the
same way as a normal overrun in Receive Mode. For the retransmitted data, when overrun occurs, the TxD line goes to the
"MARK" condition until the first Start Bit after the Receiver Data
Register is read by the processor. Figure 12 shows'ttle timing
relationship for this mode.
CHAR#_
..--...,.-~ 1-1-.....,-...-..,/
,CHAR#_+,
!
"
/
!
'--.. . _'--~ l-'-_,--p. .IStopISt.~G"El ~ ~ ffi~OpISu"~ ~ ~ ~
LJlJ
Lll1
I~""""--IL-....I= =5r
T_D
I
T_DDATA
PROCESSOR FINALLV
RESUMES
READS RECEIVER
DATA REGISTER,
,LAST VALID
CHARACTER (#nl
PROCESSOR
INTERRUPT
FORCHAR#_
IN RECEIVER
DATA REGISTER.
PROCESSDR
INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL
PROCESSOR
READS
STATUS
REGISTER
OVERRUN OCCURS
T.D GOES TO
''MARK''
CoNDITION
Figure 12. Overrun In Echo Mode
Framing Error
Framing Error is caused by the absence of Stop Bit(s) on
received data. A Framing Error is indicated by the selling of bit
4 in the Status Register at the same time the Receiver Data
Re~erFuli bit is set, also ill the Status Register. In response
to IRQ, generated by RDRF, the Status Register can also be
R_D
(EXPECTEDI ....._
checked for the Framing Error, Subsequent data, words are
tested for Framing Error separately, so the status bit will always
reflect the last data word received. See Figure 13 for Framing
Error, timing relationship.
..........
RoD
(ACTUALI ................;...I
PROCESSOR
INTERRUPT,
FRAMING
ERROR
BIT SET
NOTES: ,. FRAMING ERROR DOES NOT
INHIBIT RECEIVER OPERATION.
2. IF NEXT DATA WORD IS OK,
FRAMING ERROR IS CLEARED.
Figure 13, Framing Error
2-259
R65C51
Effect of
Asynchronous Communications Interface Adapter (ACIA)
oeD on Receiver
oeD is a modem output indicating the status of the carrier-frequency-detection circuit of the modem. This line goes high for
a loss of carrier. Normally, when this occurs, the modem will
stop transmitting data some time later. The ACIA asserts IRQ
whenever DCD changes state and indicates this condition via
bit 5 in the Status Register.
Once such a change of state occurs, subsequent transitions will
not cause interrupts or changes in the Status Register until the
first interrupt is serviced. When the Status Register is read by
the processor, the ACIA automatically checks the level of the
DCD line, and if it has changed, another IRQ occurs (see Figure
14).
CONTINUOUS "MARK"
,I,
r-....I . .
I
t
NORMAL
PROCESSOR
INTERRUPT
PROCESSOR
INTERRUPT
FOR 00ii
GOING HIGH
Figure 14.
AS LONG AS
iiCii IS HIGH.
NO FURTHER
INTERRUPTS
FOR RECEIVER
WILL OCCUR
PROCESSOR
INTERRUPT
FOil OCD
GOING LOW
NO INTERRUPT
WILL OCCUR
HERE. SINCE
RECEIVER IS NOT
ENABLED UNTIL
FIRST START BIT
DETECTED
PROCESSOR /
INTERRUPT
FOR
RECEIVER
DATA
Effect of DeD on Receiver
Timing with 1112 Stop Bits
It is possible to select 1V2 Stop Bits, but this occurs only for
5-bit data words with no parity bit. In this case, the IRQ asserted
for Receiver Data Register Full occurs halfway through the
trailing half-Stop Bit. Figure 1.5 shows the timing relationship for
this mode.
CHAR#n
CHAR#n+1
RxD
Llll
1
PROCESSOR INTERRUPT
OCCURS HALFWAY
THROUGHT THE 112
STOP BIT
Figure 15.
Timing with 11/z Stop Bits
2-260
L
Asynchronous Communications Interface Adapter (ACIA)
R65C51
Transmit Continuous "BREAK"
Note
This mode is selected via the ACIA Comman.d Register and
causes the Transmitter to send continuous "BREAK" characters, beginning with the next character transmitted. At least one
full "BREAK" character will be transmitted, even if the processor
quickly re-progrems the Command Register transmit mode.
Later, when the Command Register is programmed bac~ to
normal tr~nsmit mode, an immediate Stop Bit will be generated
and transmission will resume. Figure 16 shows the timing relationship for this mode.
If, while operating in the Transmit Continuous "BREAK"
mode, the C'i'S should go to a high, the TxD will be
overridden by the CTS and will go to continuous "MARK"
at the beginning of the next character transmitted after the
CTS goes high.
~
PERIOD DURING
_ICH PROCESSOR
1 - - - - - - - - - 1 - SELECTS
CONTINUOUS
"BREAK" MODE
POINT AT WHICH
PROCESSOR
SELECTS
NORMAL
TRANSMIT
MODE
NORMAL
INTERRUPT
PROCESSOR
INTERRUPT
TO LOAD
TRANSMIT
OATA
Figure 16. Transmit Continuous "BREAK"
Receive Continuous "BREAK"
shows the timing relationship for continuous "BREAK"
characters.
In the event the modem transmits continuous "BREAK" characters, the ACIA will terminate receiving. Reception will resume
only after a Stop Bit is encountered by the ACIA. Figure 17
- - - - - - -__,
RxD
CONTINUOUS "BREAK"
]~Lt'E·t'" 1 "
U
1
PROCESSOR
~~TRERRUPT
RECEIVER
DATA REGISTER
FULL
1 B_N...I......
1._ ...
P ...I_S'':' '...
,· I-
;
Head number 0 or 1, as specified in 10 field. ,
FM. or MFM Mode
'
. When MT· ~ '1, a mult~track operation is to be perlOrmed. After IInlshlng a readfwrite operation on side.
0., the ODFDC will automatically start searching for.sector 1 on slde.l.
.
, '.
....
.;
The number of data Ilytes written ina Sector•.,
Multi·Track
N
BytllSlSector
NO
Non-DMA MOde
= HD In all' command woi'Qs).
"
When NO -.1, oper'atlon is in the Non.DMA mode; when NO = 0, operationi!! In Ihe DMA melds.
NTN
New Track Number
A n~ track number, which will be reached as a result of the
PTN
Present Track Number
The traOk. number at the completion of Sense InterruptStatus connmand. Pranl head·positlon.
R
Record (Sector)
The sectorn~mber to. be read or written.
RIW
Fiead/write
ST
SK
Sel?torsfTrack
Skip
SRT
Step Rete Time
S.taW~ 0
STl
ST2
ST3
STP
Status 1
Status 2
Stat~3
T
Track Number
USo,USl
Unit Select
Sector Test Process
P~iied head pOsition.
Ellher reIId (R) or write (W) signal.
The number of sectors per track.
, .
. Skip ..Deleted .Data Address Mark.
Ttle Stepping rata fOr the FOP (1 to 16 ma In 1 ms increments). Stepping rate applies to all drives
,(F ".1 me,' E .. 2 rns, etc~)
Fo~r registers which store the statu~ i(!formation alter a command has been executed. This Informa~n .'
Is available. during the result phase sfter command ,execution. Theile reg~rS should not be confused
with the Main Status Register (selected by AO .. low). STO-ST3 may be read only alter a co,mmand has
bean eXjI!luteij'and contarn InfOrmstlOn relevant to thet partlcurar command.
.
During a sCan ~ommand.jl STP -01, the data In contiguous sectors iscomps~llyte by byte· with data
sent from the proceSSor (or DMA COntroller):' and If STP
02, then alternate sectors are read and
compered.
The .current/selected traCl\ number of the medium (0-255).
A Selected drive number (0-3).
"
.
"
STO
See/! !l!)mmand.
=
.
2·293
R6265.
MicroFloppy Disk Controller (MFDC)
STO
3 NR. ,....Not Ready.
!"DD is ready.
,
FDD is not ready at issue of read or write command.
If a.read or write command is issued to side 1 a single-:
sided drive; ,this bit is also set.
ST1
S{O
sn
1
1
o
o
1
of
HD
-Head AddresS~ (At Interrupt).
Head Sel~tO.
Head Select 1-:
2
O.
o
o
0
o
1
FDD
FDO
FDD
.fDD
-Missing Address Mark.
No error.
2 possible errors.
encountering the index hole twice.
.....Unlt Select, (At Interrupt).
0 selected.
1 selected.
2 selected.
3 selectEid.
2. M.FOC cannot detect the Data Address Mark or
Deleted Data Address Mark. The MD (Missing
Address Mark in Data fieldl,of Status Registe~ 2 is
also set.
SUitus Register 1 (ST1)
Status Register 2 (512)'
3
(j
'I
',.2
NO
',1"
ST1
t
'0
MICOC detected a write protect signal, from FDD during
execution of Write Data, Write Deleted Data or Format
a Track commands.
1. MFDC cannot detect the 10 Address Mark after
~U S
1
-Not Writable.
NQ errOr,
'~MA
STO
!
o
NW
:I
0
NW,
MA
I.
WT
,EN
.:....End of Track,
. No error.
.'
MFDC .attempted to access a sector beyon Daus
Blt2=SN
Scan Equal
Scan Low or Equal
0
0
Scan High or Equal
0
0
1
0
0
1
1
SCAN LOW OR EQUAL
During a scan command data is supplied from the data bus for
comparison against the data read from the disk. In order to ,avoid
having the Over Run (OR) flag set in ST1, data must be available
from the (jata bus in lesS than 27 p.S (FM mode) or 13,.s (MFM
mode). If an OR occurs, the MFDC terminates the command
and sets bits 7 and 6 of STO to 0 and 1, respectively.
Command Phase:
RIW
BYTE
7
8
5
4
3
2
W
I
MT
MF
SK
I
I
0
2
X
X
X
3
Track Number (T)
4
Head Number (H)
The following tables specify the command bytes and describe
the result bytes for the three scan commands. ,
X X HD
1
"0
US1
SCAN EQUAL
5
Sector Number (R)
Command Phase:
6
Number of Data Bytes per Sector (N)
RIW
W
BYTE
7
8
5
4
3
2
0
7
End of Track (EOl)
0
I
B
Gap Length (GPL)
USI
usa
9
Seator Test Process (STP)
1
a
1
MY
MF
SK
2
X
X
X
3
Track Number (T)
4
Head Number (H)
5
Sector Number (R)
6
Number of Data Bytes ,per Seator (N)
7
End of Track (EOl)
8
Gap Length (GPL)
9
Sector, Test Process (STP)
1
0
X X HD
Result Phase:
R
,
,
Result Phase:
R
I
Status Register 0 (STO)
2
Status Register I (STI)
3
Status Register 2 (ST2)
4
Track Number
'5
m
Head Number (H)
6
Seator Number (R)
7
Number of Data Bytes per S,ector (N)
II
DFDO ~ 'Daus
DFOO > Daus
DFOO < Daus
1
0
0
2-301
I
Status Register 0 (STO)
2
Status Register I (STI)
3
Status Register 2 (ST2)
4
Track Number
5
Head Number (H)
(Tj
6
Sector Number (R)
7
Number of Data Bytes per Sector (N)
0
1
usa
Micro Floppy Disk Controller (MFDC)
R6265
SCAN HIGH OR EQUAL
After command termination, all FDD Busy bits set are cleared
by the Sense Interrupt Status command.
Command Phase:
RIW
,
7
6
5
MT
MF
SK
2
X
X
X
3
Track Number (T)
4
Head Number (H)
5
Sector Number (R)
BYTE
W
4
3
2
1
0
,
X
X
HD
US,
usa
,, ,
6
Number of Data Bytes per Sector (N)
7
End of Track (EOT)
8
Gap Length (GPL)
9
Sector Test Process (STP)
During the command phase of the Seek operation the MFDC
sets the Controller Busy (CB) flag in the MSR to 1; but during
the execution phase the CB flag is set to 0 to indicate MFDC
non-busy. While the MFDC is in the non-busy state, another Seek
command may be issued, and in this manner parallel seek operations may be performed on all drives at once.
0
No command other than Seek will be accepted while the MFDC
is sending step pulses to any FDD. If a different command type
is attempted, the MFDC will set bits? and 6 in STO to a 1 and
0, respectively, to indicate an invalid command.
If ihe FDD is in a not ready state at the beginning of the command execution phase or during the Seek operation, them the
MFDC sets the Not Ready (NR) flag InSTO to a 1, setsSTO bits
7 and 6 to 0 and 1, respectively, and terminates the command.
Result Phase:
R
,
Status Register 0 (STO)
2
Status Register 1. (ST1)
If the time to write the three bytes of the Seek command exceeds
150 p.S, the time between the first two step pulses may be shorter
than the Step Rate Time (SRT) defined by the Specify command
by as much as 1 ms.
.
3
Status Register 2 (ST2)
4
Track Number (T)
5
Heac;! Number (H)
RIW
BYTE
7
6
5
4
3
6
Sector Number(R)
W
1
0
a
0
0
1
7
Number of Data Bytes per Sector (N)
2
X
X
X
X X
3
New track Number (NTN)
Command Phase:
SEEK
1
0
0
US1
usa
, ,
1
Result Phase: None.
The three-byte Seek command steps the FDD read/write head
from track to track. The MFDC has two independent Present
Track Registers for each drive. They are cleared only by the
Recalibrate command. The MFDC compares the Present Track
Number (PTN) which is the current head position with the New
Track Number (NTN); and .if there is a difference, performs the
following operation:
If PTN
2
RECALIBRATE
This two-byte command retracts the FDD read/write head to the
Track 0 position. The MFDC clears the contents of the PTN
counters, and checks the status of the Track 0 signal from the
FDD. As long as the Track 0 Signal (TRKO) is low, the direction
signal (LCT/DIR) output remains low and step pulses are issued
on FRISTP. When TRKO goes high the MFDC sets the Seek End
(SE) flag in STO to a 1 and terminates the command. If the TRKO
is still low after 256 step pulses have been issued, the MFDC
sets Seek End (SE) and Equipment Check (EC) fiags in STO to
1s, sets bits 7 and 6 of STO to 0 and 1, respectively, and terminates the command.
< NTN: Sets the direction output (LCT/DIR) high
and issues step pulses (FR/STP) to the
FDD to cause the read/write head to step
in.
If PTN > NTN: Sets the direction output (LCT/DIR) low
and issues step pulses to the FDD to
cause the read/write head step out.
The ability to do overlap Recalibrate commands to multiple FDDs
and the loss of the ROY Signal, as described in the Seek command, also applies to the Recalibratecommand.
The rate at which step pulses are issued is controlled by the
Step Rate Time (SRT) in the Specify command. After each step
pulse is issued, NTN is compared against PTN. When
NTN = PTN, then the Seek End (SE) flag in STO is set to a 1,
bits 7 and 6 in STO are set to 0, and the command is terminated.
At this point MFDC asserts INT.
Command Phase:
The FDD Busy flag (bit 0-3) in the Main Status Register (MSR)
corresponding to the FDD performing the Seek operation is set
to a 1.
RIW
BYTE
7
6
5
4
3
1
0
0
0
0
0
,
1
W
1
1
2
X
X
X
X X
0
US1
usa
Result Phase: None.
2-302
2
0
R6265
Micro Floppy Disk Controller (MFDC)
SENSE INTERRUPT STATUS
SPECIFY
Interrupt Request (I NT) is asserted by the MFDC when any of
the following conditions occur:
The three-byte Specify command sets the initial values for each
of the three intemal timers. The Head Unload Time (HUT) defines
the time from the end of the execution phase of one of the
read/write commands to the head unload state. This timer is programmablefrom 16t0240msin incrementsof16ms(1 ~·16 ms,
2 ~ 32ms, ... F
240ms).
1. Upon entering the result phase of:
a. Read Data command
b. Read a TracR command
c. Read ID command
d; Read Deleted Data command
e. Write Data command
f. Forrnat a Track command
g. Write Deleted Data command
h. Scan commands
2. Ready (RDY) line from the FDD cllanges state
3. Seek or Recalibrate command termination
4. During execution phase in the. Non-DMA mode
=
The Step Rate Time (SRT) defines the time interval between
adjacent step pulses. This timer is programmable from 1 to 16
ms in increments of 1 ms (F ~ 1 ms, E ~ 2 ms, D ~ 3 ms, ...
o ~ 16 ms.)
The Head Load Time (HLT) defines the time between the Head
load (HDL) signal going high and the start of the read/write
operation. This timer is programmable from 2 to 254 ms in
6 ms, ...
increments of 2 ms (01 ~ 2 ms, 02 ~ 4 ms, 03
7F = 254 ms).
=
INT caused by reasons 1 and 4 above occur during normal
command operations and are easily discernible by the processor.
During an execution phase in Non-DMA mode, bit 5 in the MSR
is set to 1. Upon entering result phase this bit is selto O. Reasons
1 and 4 do not require the Senae Interrupt Status command.
The interrupt is cleared by reading or writing data to MFDC. Interrupts caused by reasons 2 and 3 are identified with the aid of
the Sense Interrupt Status command. This command resets INT
and sets/resets bits 5, 6, and 7 of STO to identify the cause of
th~ interrupt. Table 7 defines the seek and interrupt codes.
The time intervals are a direct function of the clock (ClK on
pin 19). Times indicated above are for an 8 MHz clock. If the clock
is reduced to 4 MHz (mini-floppy application) then all time intervals are increased by a factor of two.
<
The choice of DMA or Non-DMA operation is rnade by the NonDMA mode (ND) bit. When this bit = 1 the Non-DMA mode is
selected, and when ND ~ 0 the DMA mode is selected.
Command Phase:
Neither the Seek ()r Recalibrate command, has a result phase.
Therefore, it is mandatory to use the Sense Interrupt Status
command after these commands to effectively terminate them
and to verify where the head is positioned by checking the
Present Track Number (PTN).
Issuing a Sense Interrupt Status command without an interrupt
pending is treated as an invalid command.
RIW
BYTE
W
I
7 I 6 I 51 4 31 2 T 1 1
01 0 1 0 I 0 01 0 I 11
2
S,RT
3
HLT
Result Phase: None.
Result Phase:
Status Register 0 (STO)
Present Track Number (PTN)
Table 7.STO Seek and Interrupt Code Definition for Sense Interrupt Status
Status Register 0 (STa) Bits
Interrupt Code
A
I~
o
i
I
Ir-.-i-I--.....
4
I I
I 10 IBI
C
A
NOTES
o
DATA REGISTER READY TO BE WRITTEN INTO
[!] DATA REGISTER NOT READY TO BE WRITTEN INTO
Figure 3.
~ DATA REGISTER READY FOR NEXT DATA BYTE TO IiJE READ
~ DATA REGISTER NOT READY FOR NEXT DATA BYTE TO BE'READ
MFDC and System Data Transfer Timing
2-305
II
i
N
0)
0'1
A1-A15
/'-DO-D7
I~
;)l
-......r
~
RST
NJ
j:jj)
J:::::
...wB..
II
~
~I
~
r-
~
-,-ll~1 ~.~
...,
I~
t1
Z-80
i
.
IS~
" f;J1
...
.iJI)W.
~
..N..
...... DATA
-iJ RECOVERY
READ
.....J'PRE-COMP
WRITE DATA
:.1"
RDD
~
PSt
CPU
WDA
MEMORY
'.
,
'WPI1'S
. FLTIII'IML
RUB5
MFDC
n
FRlSTP
LCTIDIR
I""
elK
I-
'"
.J
I
OSC
L
J
DAtA
9SO·
RWISEEK
.:.
.
elK
INT
F
~
----- t---1
MUX.
~
MUX
.t"-1
J. WRITE L WCK
LCLOCK
GEN J
.a
.
INT
RDY
WE
ILDX
HDL
HD
...:.Y.SO
.JIl:i1
WRiTE PfIOrECf
TWOaDE
FAULT
.
.TRACKO·'
FAULT RESET·
STEP
LOW CURf!ENT
DlREcrION
~
..;;.
~
:...
:EADY
WRI1l;.a4ABL£
.a
HEAD LOAD
INQEX ,
..... HEAD SELEcr
SELECf 0
..... INIT
INIT SELECT 1
.a
i:
.(l)"
a
-n
0'
"
,~
o
;"
'"
o
o
-a
::l
i"
....
i:
Figure 4.
R6265 MFDC Interfaee to Z-80
-n
o
.9
Micro. Floppy Disk Controller (MFDC)
Fl82~5 ...
CLK
~~§~..~_/_II
-.-J'----'--._
..
I....-------
Figure 5.
Clock Timing
DATAOI,JT
DO-D7
INT
Figure 6.
Read Cycle Timing
AO,CS;DACK
DATA IN
DO-D7
INT
Figure 7. WrHeCycle Timing
2·307
R~265
Micro Floppy Disk Controller (MFDC)
~------~17J--------~
DRQ
WR OR RD
Figure 8.
WRITE CLOCK
(WCK)
DMA Operation Timing
23
WRITE ENABLE
. (WE)
PRESHIFT 0 OR 1
(PSO, PS1)
WRITE DATA
(WDA)
Figure 9.. FDD Write Operation Timing
READ DATA (ROD)
READ DATA WINDOW (ROW)
-------
NOTE:
EITHER POLARITY DATA WINDOW IS VALID
Figure 10. FDD Read Operation Timing
2·308
Micro Floppy Disk Controller (MI=DC)
R6265
U~ ~_ _ _ _......_ _ _ _....,. '__ _ _ __
_
SEEK
(RWISEEK)
DIRECTION
(LCT/DIR)
STEP
(FRlSTP) _ _ _ _ _ _. ,
Figure 11. Seek Operation Timing
~UUR~n
(FR)
0
___
INDEX
(IDX)
' - -_ _
@
Figure 12. Fault Reset Timing
I
TERMINAL COUNT
Figure 13. Index nmlng
I
I
..,..-=t
(TC)~
I
---t
RESET
lL-
(RST)~
I
.
r-@
FIgure 14. Terminal Count TimIng
INPUT/OUT
~
·,1
.....,
t-@
FIgure 15. Reset Timing
TEST POINT
CLOCK
.
"
O::=X::?::X=
INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" AND 0.45 V FOR
A LOGIC "0:' TIMING MEASUREMENTS ARE MADE AT 2.OV FOR
A LOGIC "1" AND O.av FOR A LOGIC "0:'
.
II
..,.--,. .
.
TEST ..POINT
... ··4
o~~:J:.::lo:;:L
CLOCKS ARE DRIVEN AT 3.OV FOR A LOGIC "1" AND 0.3V FOR A
LOGIC "0:' TIMING. MEASUREMENTS ARE MADE; AT 2.4V FOR A
LOGIC "1" AND 0.85V FOR A LOGIC "0:'
Figure 16. AC Timing Measurement Conditions
2-309
Micro Floppy Disk Controller (MFDC)
R6265
AC CHARACTERISTICS
(Vcc =5.0Vdc ±5%, Vss = OVdc, TA
Ref.
Rg.
No.
1
2
3
4
5
6
7
8
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
9
10
21
22
23
24
25
26
27
28
30
31
32
33
11
12
13
14
15
35
36
37
38
39
40
41
42
43
44
45
48
47
= OOCto 7O"C)
Characteristic
Symbol
Clock Period
Clock High, Low Width
Clock Rise Time
Clock Fall Time
PD, CS, DACK Valid to RD Low (Setup)
RD High to NJ, CS, DACK Invalid (Hold)
RD Low Width
RD Low to Data Valid (Access)
RO High to Output High Z
RO High to INT High
PD, CS, OACK Valid to WR Low (Setup)
WR High to NJ, CS, DACK InValid (Hold)
WR Low Width
Data Valid to WR High (Setup)
WR High to Data Invalid (Hold) .
WR High to INT High.
ORO Cycle Time
ORO High to RO, WR High (Response)
DACK Low to ORO Low (Delay)
ORO High to RD Low (Delay)
ORO High to WR Low (Delay)
WCK Cycle Time
WCK High Width
WCK Rise TIme,
WCK Fall Time
WCK High to PSO, PSl Valid (Delay)
PSO, PSl Valid to WDA High (Delay)
WDA High Width
WE High to WCK High or WE Low to WCK Low
ROW Cycle Time
ROW Valid to ROD High (Setup)
ROD Low to ROW Invalid (Hold)
ROD High Width
USO, USl Valid to SEEK High (Setup)
SEEK Low to USO, US1 Invalid (Hold)
SEEK High to OIR Valid (Setup)
OIR Invalid to SEEK Low (Hold)
OIR Valid to STP High (Setup)
STP Low to DIR Invalid (Hold)
STP Low to USO, USl Invalid (Hold)
STP High Width
STP Cycle Time
FR High Width
lOX High Width
1C High Width
RST High Width
Alt. Sym.
lev
Cf
leA
<1>0
!cU:H'
!cHCL
tSLRL
<1>,
~HSH
tRLRH
tRLOV
tRHOZ
tRHIH
tSLWL
tWHSH
tWLWH
tOVWH
tWHoX
tWHIH
Iacv
laHXH
tALCt.
laHRL
IaHwL
tKCV
tKHKL
tKLKH
tKHKL
tKHPV
tpvOH
tOHOL
tEHKH
tWCf
tWVRH
tRLWI
tRHRL
tUVSH
isWI
tsHOV
tOXSL
tOVTH
tTLOX
tTWX
tTHTL
tTCY
tFHFl
t!tilL
tTHTL
tRHRL
<1>1
Min.
"iYP.
Max.
Unit
120
40
125
62.5
500
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
p.S
p.S
ns
ns
ns
p.S
ns
ns
ns
ns
ns
ns
ns
p.S
ns
ns
ns
p.S
0
0
250
tAR
tRA
tRR
tRO
tOF
tRI
tAW
tWA
tWw
tow
two
20
-
0
0
250
150
5
-
Iwl
tMCf
tMAW
tAM
tMR
tMW
13
-
-
800
250
80
-
lev
10
t,
It
tcp
tco
twoo
tWE
tWCf
tWRO
tROW
tROO
tus
tsu
tso
tos
tosr
tsro
tSTU
tsrp
tsc
tFR
tl'ox
tTC
tRsr
20
20
twcH -50
20
15
15
40
12
15
7
30
1
24
5
6
333
8
10
1
14
--
-
-
-20
20
-
200
100
500
-
-
-
500
-
-
-
-,...
note 1
250
12
200
-
-
-
350
20
20
100
100
-
100
-
-
-
-
note 2
-
-
-
-
-
-
-
7
,.-
-
-
-
note 3
10
-
Test
Conditione
ClK = 8 MHz
CL - 100 pF
ClK = 8 MHz
I'S
1'8
p.S
p.S
p.S
I'S
p.S
p.S
p.S
ClK = 8 MHz
tCf
tCf
tCf
Notes:
1.
MFM
Mini
'Standard
0
4p.S
2p.S
1
2p.S
lp.S
=
0: Typ. = 2 I'S
2: For MFM
For MFM = 1: Typ. = 1 !'8
3. Isc = 331'8 min. is for different drive· units. In the case of the same unit,
tsc can range from 1 ms to 16 ms with 8 MHz clock period.
2-310
Micro Floppy Disk Controller (MFDC)
R6265
ABSOLUTE MAXIMUM RATINGS·
Symbol
value
Supply Voltage
Vee
-0.3 to + 7.0
V
Input Voltage
V IN
-0.3 to + 7.0
V
Output Voltage
VOUT
-0.3 to + 7.0
V
Operating Temperature Range .
TA
Storage Temperature Range
TSTG
Parameter
o to
·NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause \lermanent damage to the deVice.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in other
sections of this documeht is not implied. Exposure to absolute
maximum rating conditions for extended periods. may affect
device reliability.
Unit
C·
+70
C·
-55 to +150
OPERATING CONDITIONS
Parameter
Range
5.0V ±5%
Vee Power Supply,
Operating Temperature
O·C to 70·C
DC CHARACTERISTICS
(Vee = 5.0 Vdc ±5%, VSS = 0 Vdc, TA = O"C to 7O"C. unless otherwise noted)
Symbol
Parameter
Input Low Voltage
Logic
ClK and WCK
V IL
Input High Voltage
Logic
CLI< and WCK
V IH
Output Low Voltage
VOL
Output High Voltage
VOH
Vee Supply Current
lee
Input Load Current
IlL
Max
Min
Unit
Test Conditions
V
-0.5
-0.5
0.8
0.65
2.0
2.4
Vee + 0.5
Vee + 0.5
V
2.4
0.45
V
Vce = 4.75V,l oL .; 2.0 mA
Vee
V
Vee ,;, 4.75V. IOH = -200 pA
mA
Vee - 4.75V
10
pA
VIN
-10
pA
VIN
150
All Inputs
= Vee
= fN
High Level Output Leakage Current
ILDH
10
pA
Vee = IN to 5.25V, Vss .. OV
VOUT = Vee
Low Level Output Leakage Current
ILDL
-10
pA
Vee = IN to 5.25V. Vss
VOUT = +O.45V
Internal Power Dissipation
PINT
1.0
W
TA
CAPACITANCE
= 25°C; fc = 1 MHz;
(TA
-
Vee = OV)
Parameter
Symbol
Max limit
Unit
Clock Input
CIN(O)
20
pF
CIN
10
pF
Cour
20
pF
Input
Output
Note: All pins except pin under test tied
to ground.
2-311
= 25°C
= CN
II
Micro Floppy Disk Controller (MFDC)
R6265
PACKAGE DIMENSIONS
[: ~·o ]]
4G-PIN CERAMIC DIP
MlWMETI!RS
INCHES
DIM MIN
MAX MIN •MAX
A
50.29 51.31 1.980 2.020
I~----==~A~~~--~--~~I
B
C
0
F
J~'II I II!!!!!!I !!1Bdn.
ILK
H
,j l l l l l l l l l l l l l l i l l
I
G-J
SEATING PLANE
I--
D
N
I
-+-J
.
M
-1
G
H
J
K
L
M
N
14.86
2.54
0.36
0.76
2.54
0.76
0.20
2.54
14.60
O·
0.51
15.62
4.19
-0.53
1.40
BSC
1.76
0.33
4.19
15.37
10·
'1.52
0.585
0.100
0.015
0,030
0.100
0.030
0.006
0.100
0.575
O·
0.020
0.615
0.165
0.021
O.OSS
BSC
0.070
0.013
0.165
0.605
10·
0.060
4G-PIN PLASTIC DIP
DIM
A
B
C
0
F
G
H
J
K
L
M
N
2-312
MilliMETERS
MIN
MAX
51.26 '52.32
13.72 14.22
5.06
3.55
0.36
0.51
1.02
1.52
2.54 esc
1.65
2.18
0.30
0.20
3.58
3.05
15.24 esc
7·
10·
0.51
1.02
INCHES
MIN
MAX
2.040
2.060
0.560'
0.200
0.020
0.060
a.540
0.140
0.014
0.040
0.100
esc
0.085 0.085
0.006 0.012
0.120 0.140
O.800BSC
10·
.7·
0.020 0.040
R6765
'1'
Rockwell
R6765
DOUBLE-DENSITY FLOPPY DISK
CONTROLLER (DDFDC)
fI
PRELIMINARY
DESCRIPTION
FEATURES
The R6765 Double-Density Floppy Disk Controller (DDFDC)
interfaces up to four floppy disk drives to an 8-bit or 16-bit
microprocessor-based system includingZ-80, 8080A, 808SA,
8086, and 8088. The DDFDC simplifies the system design by
minimizing both the number of external hardware components
and software steps needed to implement the floppy disk drive
(FDD) interface. Control signals supplied by the DDFDC reduce
the number of components required in external phase locked
loop and write precompensation circuitry. Memory-mapped
registers containing commands, status and data simplify the software interface. Built-in functions reduce the software overhead
needed to control the FDD interface. The DDFDC supports both
the IBM 3740 Single-Density (FM) and IBM System 34 DoubleDensity (MFM) formats.
• Address mark detection cirCUitry
• Software control of
-Track stepping rate
-Head load time
-Head unload time
• IBM compatible in both single- and double.
FOO'
SERIAL·.
DATA
INTERFACE
lOX
WPITS
FLTITRKO
t.CT/OiR
OACK
FRlSTP
TC
RWISEEK
ORQ
HDL
AD
CLK
USa
Vee
USl
GND
MFM.
Figure 1.
DDFDC Input and Output Signals
PIN DESCRIPTION
.
FOO
STATUS
INTERFACE
INT-Interrupt Request. This active high output is the interrupt
request generated by the DDFDC to the CPU.INT is asserted
upon completion of some DDFDC commands and before a data
byte is transferred between the DDFDC and the data bus (in the
Non-DMA mode).
Throughout this document signals are presented using the terms
active and inactive, or asserted and negated, independent of
whether the signal is active in the high-voltage state or lowvoltage state. (The active state of each logiC; pin is described
below.) Active low signals are dimoted by a superscript bar.
RD-Read. This active low input defines the data bus transfer
as a read eyele. When low. the. data transfer is from the DDFDC
to the data bus.
BUS INTERFACE
DO-D7-Data lines. The bidirectional data lines transfer data
between the DDFOC and the a-bit data bus.
WR-Write. This active ,low input defines the data bus transfer
as a write eyele. When low, the data transfer is from the data bus
to the DDFDC.
ClK-ClOCK. The clock is a TIL compatible 4 or a MHz square
wave signal.
DIRECT MEMORY ACCESS CONTROLLER
(DMAC) INTERFACE
RST-RESET. This active high input places the DDFDC in the
idle state and resets the output lines to the floppy disk drive
(FDD) to the low state.
DACK--;-DMA Ack!lowledge. The DMA transfer acknowledge
signal is a TIL compatible input generated by the DMA controller
(DMAC) controlling the DDFDC. The DMA cycle is active wher
DACK is low and the DDFDC is performing a DMA transfer.
CS-Chip Select. The DDFDC is selected when the CS input
is low.
AD-Data/Status Register Select. This input selects the Data
or Status Register for reading from or writing to. When AO =
high, the Data Register is selected and the state of RD or WR
determines whether it is a read (RD = low) or a write (WR = low)
operation. When AD low, the Status Register is selected. This
register may only be read (RD = low); the state WR = low is
invalid when the Status Register is selected.
ORQ-Oata DMA Request. The transfer request signal is a TIL
compatible output generated by the DDFDC to request a data
transfer operation under control of the DMAC (in the DMA mode).
The request is active when DRO = high. The signal is reset
inactive when DMA Acknowledge (DACK) is asserted(low).
=
2-314
j
~t'
""
t.
t
.'?:.
ott' ,
t, •. · · :
",'
FDO SERIAL ~i. INTERFACE
WCK-WrJte Clock. This input clock determines the Write Data
rate to the FDD. The data rate Is 500 KHz in the FM mOde (MFM
- low) and 1 MHz in the MFM mode (MFM • high). The pulse
width Is 250 ns (typical) in both modes.
WE-Write Enable. This output Signal enables the Write Data
into the FDD when high.
0
0
0
1
1
0
1
".
RST
IJD
1
40
' 39
Wii
5.
AO
DO:
01
02
03
ROY-Ready. An active high input signal ,indicates the FDD i~,
ready to send data to, or receive data from., the DDFDC..
D4
05
D6
07
IDX-lndex•. An active high illPut lIignal fro"", the FDD indicates
the index hole is under the index sensor.lndel( is used to synchronize DDFDC timing.
"
ORO
OACK
TC
lOX
INT
ClK
GND
RWISEEK-Read WrJtelSeek. Mode selection signal to the FDD
which controls. the muJtiple)!:er from the multiplexed signals.
when RWIS!:EK is low, the ReadlWrlte mode is commanded;
when RW/SEEK is high, the Seek mode is comm~nded.
Seek
·"'-.f ': .' ... " ,',' ,,' ", ",
P....hlft Outputs
PSD
PSl
FDD STATUS INTERFACE
High
. ' ,
HDL-Head Load. An active high output to notify the FDD that
the readlwrlte heed should be loaded (placed in contact with the
media). A low level indicateS the head should be unloaded.
PSo-PS1-Preahlft. These outputs are encoded to convey write
compensation status during the MFM mode to determine early,
late or normal times as follows:
Mode
t.
FRlSTP-Fault ResetIStep. A multiplexed output to thi) FDD.,ln
the ReadlWrlte mode,FRlSTP high resets the fault Indicator in
the FDD. An FR pulse Is Issued at the beginning of e,ach ~ad
or write command prior to issuing HDL. In the Seek mode, FRlSTP
provides the step pulses to move the readlwrite head to another
track in the direction indicated by the LCTIDIR Signal.
WOA-Wrlte Data. Serial write data output to the FDD containing both clock and data bits.
ReadlWrite
7""
LCTIDIR-LOw CurrentlDlrectlon. A multiplexed output 10 the
F[)D. In the ReadlWrtts mode, i.CrIDIR is low when the readlwrtte
head Is to be positioned CNer the Inner tracks and the lCl'/DIR
Is high 'when the head is to be positioned O\I8r the outer tracks:
II'! the Seek mode.LCT/DIR ~ntrols the.;heac;J.dir:ection.When
LCT/DIR. is high, the head ~P.S ~ the outBideof the disk; when
LCT/DIR is low, the head steps to the inside of the disk.
.,
VCo-Variable Frequency Oscillator Sync. This output signal
Inhibits the VCOln'the PLL clreultwhen low and'lInables the
VCO In the PLL circuit wheilhigh. This inhibits RDD and ROW
.trombelng generated until val.id data is detected from the FD~.
Low
,'" ..
Zero.
ROW-Read D* W1i1dC)w. Data Window Inputgener'ated by the
Phase Locked LDop (PLL) anduslld to sampht data from the FDO.
RWISEEK
,':'"
FLTITRKO-Faultmack Zero. An active hlQ!l.!!lultlplexed Input
from the FDD. In the ReadlWrlte mode (RWISEEK • low),.
FLTrr.RKO, . high Indicates an FOP fault. In the. Seek mode,
FLTlTRKD high Indicates that the readlWrlte head Is positioned CNer
track
RDD..;.,R..d Data. Read Data lnj:nlt from the floppy disk· drive
(FDD) containing clock and data bits.
.
Normsl
late
Early
Invalid
o - low, ,1 • High
"..
WPlTS-Wrlte Protectl1Wo SIde; An.~high;rnultlplMd Input
signal fromtlie'FDD. In the ReacflWrite mode, Wp/rs high indi~
cates the media is write-protected. In the Seek mode. WPITS high
indicates the media Is two-sIded.
TC-Termlnal COunt. This input signal Is Issued to the COfFOe
when the DMA transfer for a channelll complete. The signal
Is. adtlye high c:;Ql)current .wlth t.he DAC.' Input when tre DMA
operation Is complete as. a result. of that tran!Sf••r.. ,,"
Write Precompen88tlon Status
1
ActIve FDD Interface Signals
WP, FlT,LCf, FR
1S. TRKO, OIR, STP
3
4
5
6
7
8
9
lD
11
12
13
14
15
16
17
18
19
20
38
31
vee
RWISEEK
LCl'IDIR
FRlSTP
36
HOl
35
34
ROY
WPITS
FLTmu INTERFACE
CONTROL
LCTIOIR
FRISTP
ft> OUTPUT
PORT
•
...
RW/SEEK
HOl
-
HO
usa
USI
MFM
'-
Figure 2.
DDFDC Block Diagram
2-316
Double-Density Floppy Disk Controller (DDFOe)
R6765·
The relationship between the status/data registers and the WR,
RD andAO signals is shown below.
AO
RD
WR
Function
0
0
0
0
0
0
1
1
1
1
0
0
0
0
/liegal
Read Main Status Register
/liegal
/liegal
Read from Data Register
Write into Data Register
1
1
0
1
o = Low,
1
~
High
Table 1 shows each of the status registers used by the DDFDG
and each bit assignment within the individual registers. Table 2
defines the symbols used throughout the command definitions.
Each register bit symbol is defined in the register descriptions
that follow Table 2.
MSR
3 D3B
-Floppy Disk Drive (FOD) 3 Busy.
FDD 3 is not busy, DDFDC will accept read or write
command.
FOP 3· is busy, DDFDG will not accept read or write
command.
o
MSR
2 D2B
-FDD 2 Busy.
o FDD 2 is not busy, DDFDC will accept read or write
.
command.
FDD 2 is busy, DDFDG will not accept read or write
command.
MSR
1
DIB . -FDD 1 Busy.
FDD 1 is not busy, DDFDG will accept read or write
command.
FOD 1 is busy, DDFDC will not accept read or write
command.
o
REGISTER DEFINITIONS
MSR
Main Status Register (MSR)
D2B
o
D1B
DOB
"the Main Status Register (MSR) contains the status information
ofthe DDFDC, and must be read by the processor before each
byte is written to, or read from, the Data Register during the command or result phase. MSR reads are not required during the .
execution phase. The DatalnpuVOutput (010) and Request for
Master {ROM) bits in the MSR indicate when .data is ready and .
in which direction data will be tralisferred on the data bus. The
maximum time between the last RD or WR during command
or result phases and the 010 and ROM getting set or reset is .
12
For this reason, every time the MSR is read the processor
should wait 12 !IS. The maximum time from the trailing edge of
the lastJ1[) in the result phase to when bit 4 (DDFDG Busy)
goes low is also 12 !IS.
;..s.
7
6
1
5
5
SE
4
EC
3
NR
2
1
I
0
US
HD
1 usa
The Status Register 0 (STO) as well as the other status registers
(ST1-ST3), are available only during the result phase, and may
be read only after completing a command. The particular commandexecuted determines which status registers are used and
may be read.
o
ROM -Request for Master;
Data. Register is not ready.
Data Register is ready.
o
010
~Oata Input/Output.
Data transfer is from system to the Data Register.
Data transfer is from Data Register to the system.
-Interrupt Code.
(Nn. Command was properlyexecuted and completed.
Abnqrmal Termination (An. Command execution was
started, but was. not successfully completed.
Invalid Command (IC). Received command was invalid.
Abnormal Termination (An. The Ready (ROy) signal
f~om the~DD changed state during command
execution.
No~mal·Termination
STO
!
o
MSR
o
6
US1
MSR
o
J
IC
o0
MSR
7
Status Register 0 (S:rO)
STO
7 6 IC
The 010 and ROM timing chart is shown in Figure 3.
o
-FDD o Busy.
FDD 0 is not busy, DDFDC will accept read or write
command.
FDD 0 is busy, DDFDG will not accept read or write
command.
Q DOB
o
2
1
EXM
-execution Mode. (Non-OMA mode only).
Execution phase ended, result phase begun.
Execution phase started.
SE
-Seek End.
Seek command .. is not completed.
Seek command .completed by DDFDC.
STO
!
o
MSR
4 CB
-Controller (DDFOC) Busy.
o DDFDC is not busy, will accept a command.
DDFDC is busy, will not accept a command.
1
2·317
EC
-Equipment Check.
No error.
Either a fault signal is received from the FDD or the track
osignal failed to occur after 256 step pulses (Recalibrate
command).
II
Double-Density Floppy Disk Controller (DDFDC)
R6765
Table 1. DDFDC Status Register Bit Assignments
Bit Number
Main Status Register (MSR)
7
6
5
4
.a
2
1
0
ROM
010
EXM
CB
D3B
D2B
D1B
DOB
SE
EC
NR
HD
DE
OR
0
NO
NW
MA
DO'
WT
SH
SN
BT
MD
TRKO
TS
HD
US1
080
IC
Status Register 0 (STO)
Status Register 1 (STI)
EN
0
Status Register 2 (ST2)
0
CM
FLT
WP
Status Register 3 (ST3) .
,
Table 2.
Symbol
ROY
US
US1
USO
Command Symbol Description
Description
Name
AO
Address line AO
Controls selection of Main Status Register (AO = low) or Data Register (AO = high):
0
Data
The data pattern which is going to be written into a sector.
00-07
Data Bus
DTL
batalength
·:When N is defined lIS 00, DTL, is the number of data bytes tOJ,ead from or write info the sector.
EOT
End of Track
The final sector number on a tracl<. Dl,Jiing read or write' operanon. the OOFDC stops data transfer
after reading from or writing to the sector equal to EOT.
GPL
GlIpLength
Tbe length of Gap 3. During readlwrite COmmands this value d~termines, the number of bytes that the
VCO will stay low after two CRC bytes. During the Format a Track command it determines the size of
.
Gap 3.
8-bit data bus, where 00 ,is the least significant data line and 07 is the most Significant data line.
' Head number 0 orl, as specified in 10 field.
H
Head Address
HD (H)
Head
A selected head numllerO or 1 which controls the polarity of pin 27. (H = HD in all command words).
HLT
Head Load Time
The head load time in the FDD (2 to 254 ms in 2 msincremerits).
HUT
Head Unload Time
The head unload time after a read or write operation has occurred (16 to 240, ms in16 ms increments).
MF
FM or MFM Mode
When MF = 0, FM mode is selected; and when MF= 1, MFM mode is selected.
MT
Multi-Track
When MT = 1, a multi-track operation is to be performed. After finishing a read/write operation on side
0, the DDFDC will automatically start searching for sector 1 on side 1.
N
Bytes/Sector
The number of data bytes written in a sector.
NO
Non-DMA Mode
When NO = 1. operation is in the Non-DMA mode; when NO = O. operation is in the DMA mode.
NTN
New Track Number
Anew track number, which will be reached as a result of the Seek command, Desired head position.
PTN
Present Track Number
The track number at the completion of Sense Interrupt Status command. Present head position.
R
Record, (Sector)
The sector number to be read or written.
R/W
ReadlWri\e
Either read ~Rl or write (W) signal.
ST
SectorsfTrack
The number of sectors per track.
SK
Skip
Skip Deleted Data Address Mark.
SRT
Step Rate Time
The stepping rate for the FDD (1 to 16 ms in I' ms increments). Stepping rate applies to all drives
(F = l,ms,
= 2 ms, etc.)
STO
STI
ST2
ST3
status 0
Status 1
Status 2
Status 3
Four registers which store the status information after a command has been executed. This information
is avaiiSble during the result phase after command execution. These registers should not be confused
with the Main Status Register (selected by AO = low). STO-ST3 may be read only after a command has
been executed and contain information releVant to that particular command.
STP
Sector Test Process
During a Scan command, if STP = 01, the data in contiguous sectors is compared bYte by byte with data
sent from the processor (or DMA controller); and if STP = 02, then alternate sectors are read and
compared.
T
Track Number
The current/selected track number of the medillm (!J.'.255).
USO,USI
Unit Select
A selected drive number (0-3).
e
2-318
. "
R676$.
[)Quble-Density Floppy Disk Controller (DDFDe)
ST1
1 NW
-Not Writable.
No error.
DDFDC detected a write pr.otect signat frOm'FeD during
execution of Write Data, Write Delated Data or Format
a Track commands.
STO
NR
-Not Ready.
FDD Iii ready.
FDD is not ready at issue of read or. write command. If
a read or write command Is iss~ tO'side 1 of a singlesided drive, this bit is ,,~set.-'
3
o
1
o
'
STO
o2
1
HD
ST1 MA
-Mlaalng Address.Mark.
No error.
2 possible errors..
o
-Head Address. (At Interrupt).
o.
Head Select
Head Select 1.
.
o
.
1. DDFOC'cannot deteCt the 10
STO
1 0 US'
'0 '0
o 1.
1 0
1
1
0 selected.
1 selected.
2.DDFDC cannot detect the Data Address 'Mark or
Deleted Data Address Mark. The MD (Missing Address
Mark in Data field) of Status Register 2 is also set.
2 seleCted.
3 selected.
Status Register 1 (ST1)
Status Register 2 (812)
7
6
0
eM
I I
ST1
!
o
1
!
1
o
3
SH
I
2
1
0
SN
BT
MD
I
ST2
!
o
-Not Used. Always Zero. .
1
DE
-Data Error.
No error.. ,
DDFDC detected aORC error in 10 field or the Data field.
CM
-Control Mark.
No error.
DDFOe encounter.ed a sector which contained a Deleted
Data Address Mark during executlon·pf a Read Data,
Read a Track, or Scan command, or which contained a
Data Address Mark during eXecution of a A88!I peleted
Data command.
ST2
ST1
4
I
4
WT
-Not Used. Always Zero.
!
ST1
5
5
DO
ST2
EN
-End of Track.
No error.
DDFDC attempted to access a sector beyond the last
. sector of a track.
ST1
o
after
encountering the index hole twice.
-Unit Select. (At Interrupt).
FDD
FDD
FDD
FDD
~ress'Mark
5
OR
"'-Over Run.
No error..
DDFDC 'waS not serviced by the system during data
transfers, within a pr.edetermined time Interval..
o
1
-Data Errol' In Data Field.
No error.
DDFDC detected a CRC error in the Data field.
DO
ST2
ST1
!
II
o4
-Not Used. Always Zero.
1
ST1
2 ND
-No ,Data.
No err.or.
1
3 poSsible errors.
o
WT
-Wrong T• • .
No error.
'
Contents of T on the disk is different from that stor.ed in
lOR. Bit is related to NO (Bit 2) of Status Register 1.
ST2
3 SH
Equal Hit.
No "equal" condition during a ~ command.
1
"Equal" condition satisfied during a scan comrriand.
o
1. DDFDC cannot find sector specified In 10 Register
during execution of Read Data, Writa Deleted Data or
ScarJ commands.
--scan
ST2
2 SN
--scan Not Satisfied.
No error.
DDFOe cannot find a sector on the track which meets
the scan command condition.
2. DDFDC cannot read 10 field without an error during
Read 10 command.
o
3. DDFDC cannot find starting S$CtOr during execution
of Read a Track command.
2-319
R6765"·
ST2
! .BT
o
1
';DoulJte-Density Floppy Disk. Controller (DDFDe)
,
.1
Fh~ld.
MD
...,.MlsslngAddress.Mark·trM)ata
No error.
.
., ,
:
. '
,
"
~:l'
',I"
:
:
ReSult Philse;"After completion of the operation, status and
other housekeeping information are made8Vai!able to the system.
rhe bytes of data Sent to the DDi=OC to form a command, and
rea\! out of the oOFOC in the result phase, must occur in the
order shown for each command sequence. Tha! is,thec:ommand
code byte must b~ sent first followed by'the other bytes in the .
speci(iedseq!,lence. All com1)1E\n4 qyies must bEl written and all
result~ytes must be rlNld in each phase. After thetast byte of
data in .tht} command ph~ .is receiVed. by the,ODFOC, the
execution phase starts. Similarly! when the last byte of data is
read out in tile result phase, th.e command is ended and tl:le
ODFOC is ready to 'acCept a new.command. A command·'can
be terminated by asserting the Terminal Count (TO) signal to
tl:le ooFD(;. Thisefl~~EI& th!iYtl:le.procaS$Ot9Bn aJwaysget the
DOFOC's attention even if the command in process l:Iangs up
in an abnormal manner.
Statl,lS Register 3 (ST3) holds the I'E!SUIIl!l Qft~; Se~ Drive ~us.
c:ommllnd.
ST3,.
L FLT
o
1
..,..Falllt.:,.
......
i .
Fault (FLT) signal from the FDDIs I!>W.
Fault (FLT) signal from the FDD iehigh.
sra
& WP
o
-Write Protect.
Write Protect (WP) signal from the FDD is low.
Write Protect (WP) signal from the FD'O is high.
COMMAND DESCRIPTION
ST3
5
'0
1"
ROY
-Ready.
Ready (ROY) signal from the FDOts low.
Ready (ROY) signal from the FDOishrgh.
READ DATA
A command set of nine bytes places the oDf=oC into the Read
Data mode. Aftet'the Aeed Data command has been received
the DOFoC loads the head (if it is unloaded), waits the speclfiec!
Head Settling Time (defined in the Specify c:ommand), then begins
reading 10 Address Marks and 10 fields from the disk. When the
current sector numbe~. (A) storec;t ifl the 10 Aegl~er (tOR) matches
the sector nomber read from thEi disk, the ODF-OC transfers data
from the disk Data fi~ld lathe data bus.
ST3
~
o
1
TAKO
-Track O.
Track 0 (TRKO) signal from Il\e FOD, is low.
Track 0 (TRKO) signal is tram the FDD is high.
ST3
!
o
TS
-Two Side.
Two Side (lS) signal from .the FDD Is low.
Two Side (TS) signal from the FOD is high.
After completion of the read o~ration from the current sector,
the DDFDC increments the Sector Number (R) by one, and the
dElta from the next sector is read and output to the data bus. This
continuous read function is. called a "Multi·Sector Read Opera·
tion;" The Read Command terminates after reading the last data
byte from s$Ctor R when R - EOT. 8\0 bi~ 7 and 6, are set to
o and 1" respectively, and ST1. bit. 7 (EN) is set to a 1.
ST3
2
o
HO
-Head Select~
Hell(! Select (HD) signal to the FOD is low.
Head Select (HO) signal to the FOD is high.
ST3
1
o
US1
..,..Unlt Select ,.
.'
Unit Select 1 (US1) signal 'to the FDD is low.
Unit Select 1 (US1) signal to the FOO is high.
The Read Data commahd can. also' be terminated by a high
. Terminal Count (IC) signal. TC should be issued at the same
time that the DACK f~r the
byte of data Is sen!. Upon receipt
of TC, the OoFOC stops olltputting data to the data bus, but con·
tinues to read data from the current sector, checkS CRC (Cyclic
Redundancy Count) bYtes,aildtheri al'tI'Ie end ofthats8ctor ter·
minates the Read Data command' and sets bits 7 and 6 in' STO
last
ST3
o usa
o
1
1" • • " . " . 0 ..
Execution . Phase-The ODFOC perfOrms the instructed
operation.
.
Statu"Reglster 3 (S1'3)'
,',
,"
CommandPhlUle"":'TheOOFDC .reCEHves ~II information·
required to perfOrm a particular operation' from t~e sy$iem .
DDfOG cannot find a ~~tess'MarkorOelE!ted Data
. Address lIIJark during a data 'rea\! from the disk.
. ',."
"f!'
The OOFDe is capable of performing '15 differenjcommands.
E!lC1t comm!ilnd iSifli!iated by a multi-byte transfer otdaia from
the System. After ccirrlh\!l!ld exeCution, tl:le reSult of the oommand
may be amIJlti-bYte transfer'of datil badk io the syStem. Because
of this multi-byte transfer of infarh1ition between the ODFDC and
the system, each command consists of three phases:
No error.
. '
.
C;OI'ltet:\tS of T .Oll the disk Is dJffe~ntfrom that $tared In
:the. 10Ft and T .. FF.Bit is relatedtoNp(Bit 2) of Status
Register 1 . '
~ . / .'
" . '
COMMAND SEQUENCE
-sad Track.
.. ST2
oo
",.'.
-Unit Select O.
Unit Select O(USO) signaltotheFDD is low.
Unit Select 0 (US1) signal to,the FOois high.
2-320
'Double-Density Floppy Disk Controller (DDFDC)
R6765
to o. The amount of data whiCh can be handled with a single command to the DDFDC depends upon MT (Multi-Track), MF
(MFM/FM), and N (Number of Bytes/Sector) values. Table 3 shows
the transfer capacity.
If the DDFOG reads a Deleted Data Add..... Mark from the disk,
and the Skip Deleted Data Address Mark bit in the first command
byte is not set (SK '" 0), then the DDFDC .reads all the data in
the sector, sets the Control Mark (CM) flag ,in ST2 to aI, and
terminates the command. If SK
I, the DDFDC skips the sector with the Deleted Data Add..... Mark and reads the next sec:tor. The. CRC bits in the delated data. field. are not checked wh.en
SK = 1.
=
The multi-track function (Ml) allows the DDFDC to read data from
both sides of the disk. For a particular track, data is transferred
starting at sector I, side 0 and completed at sector L, side 1
(sector L = last sector on the side). ThiS function pertains to only
one track (the same track) on each side of the disk.
During diSk data transfers from the DDFOG to the system, the
DDFOG must be serviced by the system within 27/1S in the FM
mode, and within 13 /IS in the MFM mode, otherwise the DDFOG
sets the Over Run (OR) flag in STI to.a 1; sets bits 7 and 6 in
STO to 0 and I, respectively, and terminates the command.
When N = 0 in command byte 6 (FM mode), the Data Length
(DTL) in command byte 9 defines the data length that the DDFOG
must treat as a sector. If DTL is smaller than the actual data
length in a sector, the data beyond the DTL is not sent to the
data bus. The DDFOC reads (internally) the complete sector, performs the CRC check, and depending upon the manner of command termination, may perform a multi-sector Read operation.
When N is non-zero (MFM mode), DTL has no meaning and
should be set to FF.
If the processor terminates a read (or write) operation in the
DDFOC, then the 10 information In the result phase is dependent
upon the state of the MT bit in the first command byte and the
End of Track (EOl) byte. Table 4 shows the values for Track
Number (1), Head Number (H), Sector Number (R), and Number
of Data Bytes/Sector (N), when the processor terminates the
command.
At the completion of the Read Data command, the head is not
unloaded until·the Head Unload Time (HUl) interval defined in
the Specify command has elapsed. The head settling time may
be avoided between subsequent reads H the processor issues
another command before the head unloads. This time savings
is considerable wlien disk contenfs are copied from one drive to
another.
Command Phase·
If the DDFOG detects the Index Hole twice in succession without
finding the right sector (indicated in R), then the DDFDC sets the
No Data (NO) flag in Status Register 1 (ST1) to a t, sets Status
Register 0 (STO) bits 7 and 6 to 0 and I, respectively, and ter'
minates the Read Data command.
/WI
BYTE
7
6
5
4
3
2
1
iN
1
MT
MF
.SK
0
0
1
1
0
2
X
X
X
X
X
HD
US1
USO
3
Track Number (T)
4
Head Number (H)
After reading the 10 and Data fields in each sector, the DDFDC
checks the CRC bytes. If a read error is detected (incorrectCRC
in 10 field), the DDFDC sets the Data Error (DE) flag in sn to
a 1,setS the Data: Error In Data Field (DO) flag hi ST2 to a 1 if
a CRe error occurs in the Data field, sets bits 7 arid' 6 in STO
to 0 illld I, respectively, and terminates'the command.
Ta~
Sector Number (R)
6
Number,ot.Data .Bytes per Sector (N)
7
End of Track (EOl)
8
Gap Length (GPL)
9
Data Length (DTL)
3. DDFDC Transfer Capacity
MultI-Track
(MT)
MFMIFM
(MF)
ByteslSector
0
0
0
1
00
1
1
0
1
00
(N)
5
Maximum Transfer CapacIty
(BytaslSectOl') (Number of Sectora)
(128) (26)=
(256) (26) -
0'1
3,328
6,656
01
(128) (52) = 6,656
(256) (52) = 13,312
3,840
7,660
0
0
0
1
01
02
(256) (15) (512) (15) =
1
1
0
1
01
02
(256) (30) = 7,660
(512) (30) = 15,360
0
0
0
1
02
03
(512) (8)
(1024) (8)
1
1
0
1
02
03
(512) (16) = 6,192
(1024) (16) " 16,364
2-321
.
=
4,096
8,192
Final Sector Read
fromDl8k
26 at Side 0
or 26 at Side 1
26 at Side 1
15 at Side 0
or 15 at Side 1
15 at Side 1
8 at Side 0
or 8 at Side 1
8 at Side 1
0
fI
DQuble-Density .Floppy Ois~, Ccmtr.Qller (DDFDe)
R.6765
Table 4. 'DDFDC Command Termination Values
Command 'Pha.. ID '
MultlTrack.
(MT)
,
Reaul~
Final Seclor Tran.rerrecl
. lolfrom Data ,eua .
Head
Number',
(HD)
"
0
,
'.
b
less th!lO .EOT
.0 .
Equal to,EOT
Heacl
Number
(H)
(T)
NC
T' + 1
NC
:' .01 "
R+1
NC.
01
NC
R+ 1
NC
NC
0
Less than EOT
NC
0
Equel to EOT
NC
·less th." EOT
NC
NC
T ,+ 1
.lSB
'.1.·
"
1
.,
Equal to EOT
,','
..
(R)
NC
T + 1
NC
".
NO'
NC
..lSB
'.
No. of
. Data BytH
(N)
'R + 1
E.qual to EOT
,
plI... 10
. sector
Number
NC
Less than EOT
1
1
1
Track
Number
-
NC
' 01
NC
Fi + 1
NC
NC,
01
;'.
Not..:.
1. Ne (No Change): The 'me value ss the' one at the beginning of command execution.
2. l$B (Least Significant, B~): The least significant bilot H is cOmplemented.
Result Phase:
R
1
2
Status Register 1 (ST1)
Status Register 2 (ST2)
4
Track.,Number
5
:6
7
in ,one ofthe,ID.fields, it terminates the Write Data command,
sets the DE flag inSTl to a 1, and sets. bits 7 aIId.6 in,STO to
o,and " respe~ively,
'Status Register 0 (STO)
3
,
The Write. Data comtnand operates in muc/! the same manner
as the Rea!,! ·Plltac9mmand. Refer to tl)I' Read Qata cOlllmand
for the handling of the following Items:
en
Head Numl;ler (H)
• TransfeJ Capacjty
-End of Track (EN) flag
• No Data (NO) flag
• Head Unload Time (HUT) interval
• 10 information when the processor terminates command
(see Table 4)
• Definition of Dina Lel'lgth (DTL) wilen N .. Oand when N ",0
Sector Number (R)
Number ilt Data Bytes per S~or (N)
WRITE DATA
A command set Of nine bytes places the DDFDC in the Write Data
mode. After the Write Data command has been received the
DDFDC loads the hea!:l(if it is.unloaded), waits the specified Head
Settling Time (defined in the Specify command), then begins'
reading 10 field!' from the disk. Wilen the four bytes (T, H,. R, N)
loaded during the command match the four bytes of the 10 field
from the disk, the DDFDC transferS data from the data bus to
the disk Data field.
'
In .the Wri~eData m~e,!:latS transfers from the,data bU$ to the
DDFDC must, occur within' 27 pS in the FM mode, and within 13 pS
in the MFM mode. If the time interval between data transfers is
longer than this, then the DDFDC terminates the Write Data command, sets the Over Run (OR) flag in STl to a 1, and sets bits
7 and 6 in STO to 0 and 1, respectively.
Command Phase:
After writing data into the current sector, the DDFDC increments
the sector number«R) by one, and writeS Into the Data field,,"
the next sector. The DDFDC coniinues ·this multi,sector write
operation until the last byte is Written to sector R when R = EOT.
STO bitS. 7 and 6.are set to 0 and 1, resP891ively,and STl bit
.
7 (EN) is set to a 1.
The command can also· be terminated by a high on Terminal
Count (TC). If TC is sent to the DDFOC while writing Into the
current sector, iheh the remainder of the Data field is filled with
00 (zeros). In this case, STO bits 7 and 6 are set to 0 and the
command is terminated.
The DDFDC reads the 10 field of each sector and checks the
CRC bytes. If the DDFDC detects a read error (inc»rrect CRC)
2-322
RIW
BYTE
7
6
5
4
3
2
1
W
1
MT
MF
0
0
0
1
0
1
2
X
X
X
X
X
HD
US1
USO
3
Track Number
4
Head Number (H)
5
Sector Number (R)
6
Number of Data Bytes per Sector (N)
en
7
End ot Track (EOT)
8
Gap length (GPL)
9
Data length (OTL)
0
Double-Demsity Floppy Disk ContrOller (DDFDC)
R6765
·0
Result Phase:
R
Command Phase-
1
Status Register 0 (STO)
RIW
BYTE
5
4
3
2
1
0
2
Status Registar 1 (ST1)
W
1,
MT MF
SK
0
1
1
0
0
3
Status Aegistar 2 (ST2)
X
HD
US1
usa
4
Track Number
en
7
8
2
.Jt
3
Track Number
Head Number (H)
X
X X
en
5
Head Number (H)
4
6
sector Number (1'1)
5
Sector Number (1'1)..
7
Number .of Data Bytes per sector (N)
6
Number of Data Bytes per Sector (N)
7
End of Track (eOT)
8
Gap Length ,(GPL)
9
Data Length (DTL)
WRITE DELETED DATA
The Write Deleted Data command is the same as the Write Data
command except a Deleted Data Address Mark is written at the
beginning of the Data field instead 01 the normal Data Address
Mark.
Result Pha..R
Command Phase:
RIW
BYTE
7
8
5
4
3
2
1
0
W
1
MT
MF
0
0 ,1
0
0
1
2
X
X
X
X X HD
US1
usa
3
Track Number
4
Head Number (H)
5
Sector Number (R)
6
Number of Data Bytes per Sector (N)
7
End of Track (EOT)
en
8
Gap Length (GPL)
9
Data Length ,(DTL)
,
i
Status Reglstar 0 (STO)
2
Status Register 1 (ST1)
3
Status Register 2 (ST2)
4
Track Number
en
5,
Head Number (H)
6
Sector Number (R)
7
Number of Data Bytes per Sector (N)
READ A TRACK
The Read a 'Track command is Similar to the Read Data command except that this is a continuous read oPeration where all
Data fields from each Of the sectors on a track are read and
transferred to the data bus. Immediately after encountering the
Index Hole, the DDFDe starts reading the Data fields as co.!I~
tlnuous blocks of data. This command terminates when the
number of sectors read Is equal to EOT. MUlti-track operations
are not allowed with this command.
Result Phase:
R
1
Status Register 0 (STO)
2
Status Register 1 (ST1)
3
Status Register 2 (ST2)
4
Track Number (T)
5
Head Number (H)
6
SecIor Number (R)
7
Number of Data·Bytes per s8Ct0r(N)
If the DDFDC finds an error in the 10 or Data eRe check bytes,
it continues to read data from the track. The DDFOe compares
the 10 information read from each sector with the value stored
In the lOR, and Sets the NO flag in STI toa 1 if there is no match.
If the DDFDC does not find an '10 Address Mark on the disk after
it encounters the Index Hole for the second time it terminates the
command, sets the Missing Address M~rk (MA) flag in ST1 to
ai, and sets bits 7 and 6 of STO to 0 and 1, respectively.
READ DELETED DATA
The Read Deleted Data command is. the same as the Read Data
command except that if SK = 0 when the DDFDC detects a Data
Add..... Mark .at the beginning of a Data field, it reads all the
data in the sector and sets the eM Ilagin ST2 to a 1, and then
terminates the command. If SK = 1, then the DDFDC skips the
sector with the Data Add..... Mark and reads the next sector.
2~23
fJ
Double-Density Floppy Disk Controller (DDFDC)
R6765
FORMAT A TRACK
Command Phase"
RIW
W
BYTE
7
6
5'
4
3
2
1
0
1
0
MF
SK· .0
0
0
1
a
2
x
X
x x
X
HD
USI
usa
3
Track Number (T)
4
Head. Number ,(H)
5
-8llQ1Or Number (R)
·6
Number of Data ByteS per Sector (N)
7
End Of Track (EOT)
8
Gap Length (GPL)
9
Data Length (DTL)
The.six-bytaFormat aTrack command formats an entire track.
After the Index Hole is detected,data is written on the disk: Gaps,
Address Marks, ID fields and Data fields; all are recorded in either
the double-density IBM System 34 format (MF = 1) or the singledensity IBM 3740 format (MF = 0). The particl,llar format written
is also controlled by the values pf Number of Bytes/Sector (N),
Sectowr!'8ck (sT), Gap Length (GPL) an(! Data PalWm (0) which
are supplied by the processor during the command 'phase. The
Data field is filled with the dat!! pattern stored in P.
The 10 field for each sector is supplied by the processor in
response to four data requests per sector issl,led ,by .the qO~I?C.
The type of data request depends uPon the Non-DMA flag (NO)
in the Specify command. In the DMA mode (NO = 0), the OOFDC
asserts the. ·DMA Request. (DRa) output four times per sector.
In the Non-OMA mode (NO = I), the' DOFDC asserts Interrupt
Request (INT) output four times per sector.
Result Phase:
R
1
,Status Register 0 (STa)
2
Status Register 1. (BTl)
~3
,4
Status Register 2 (ST2)
Track Number (T)
The processor must write one data byte in respOnse to each
request, sending (in the consecutive order) the Track Number (T);
Head Number (H), sector N\Jmber (R) and Number of!3yte$l
Seetor (N). This..allowsthe disk to. be formatted with nonsequential
sector
numbers,
'.,
/. .
.
. . . if desired.
...
5
. Head Number (Hj ,
6
Sector Number (Rj
7
.Number of Data BYtes per Sector (N)
.'
The processor mllst Send new' values for T,'H, R, and N to the
OOFOC for each sector on the track. For sequential formatting
R is incremented by OnE! after each sector is formatted, thus, A
contains the toial numbers of sectors formatted when it is read
during the. r~ult phase. This incrementing and formatting continues for the Whole track until the OOFbc, upon encountering
the Index Hole for the second time, terminates the command and
sets bits 7 and 6 in STO to O.
,READID
The lWo-byte Read 10 command returns the present position of
the readtwrite head. The OOFDC obtains the value from the first
ID field it is able to read, sets bits 7 and 6 in STO to 0 and terminates the command.
If no proper 10 Address Mark is found on the disk before the Index
Hole is encountered for the second time then the Missing Address
Mark (MA) flag in srI is set to a 1, an!! if no data is found then
the NO fiag ii,.ST1 is also setto a 1~ 8its7 and 6in STO are set
to 0 and 1, r~speCtively and the command is terminated.
If the Fault (FLT) signal is high from the FDD at tlie end of a write
operation, the OOFDC. sets the Equipment Check (Ee) flag In STO
to a 1, sets bits 7 and 6 of STO 10 0 and 1, respectively, and lerminales the command. Also, a low (ROY) signal at tlJebeginnlng
of a command execution phase causes bits 7 and 6 of STO to
be set to 0 and 1, respectively. '
.
During this command there is no data transfer between OOFOC
and the data b~ except during.the result phase.
Table 5 shows the relationship b$tWeen N, ST, an!i GPL for
variOUS disk and sector sizes.
Command Phase:
RIW
BYTE
7
6
5
4
3
2
1
0
W
1
0
MF
a
a
1
a
1
a
2
x
X
x x
X
HD
USI
uSa
Command Phase"
Result Phase:
R
1
Status Register a (STa)
2
~tus Register I (STI)
:3
Status Register 2 (ST2)
4
Track Number (T)
5
Head Number (H)
6
Sector Number (R)
7
Number of Data Bytes per Sector (N)
2-324
RIW
BYTE
7
6
5
4
3
2
1
w
I
a
MF
a
a
I
1
0
1
2
X
X
X
X
X
HO
US1
usa
3
Num.ber of Bytes per sector (N)
4
SeciOrliper Track (ST)
5
Gap Length (GPL)
6
Data Pattern (D)
a
Do-..ble-Oens.ity Floppy Disk Controller (DDF9C)
R6765
..
Table 5. Standard Floppy Disk SeetorSlZe Relationship
Sector Size
ByteafSector
Dlek
Mode
128
256
512
1024
2048
FM
8"
MFM3
MFM3
Aeacl/Wrtte
Fonnat
Command1
Commanc12
00
01
02
1A
OF
08
lB
03
04-
04
07
OE
lB
47
C8
C8
256
512
1024
2048
4096
8192
01
02
128
128
00
00
01
02
256
256
512'
1024
2048
5'4"
Sector,rrracka.
CST)
05
512
1024
2048
4096
.
Gap Length (GPLj4
NO. of
(N)
409s
256
FM
No. of Data
BytetllSeCtor
02
01
DE
lA
OF
08
03
04
lB
35
99
04
05
011
03
04
01
01
02
04
05
3A
SA
FF·
FF
36
54
74
FF
FF
02
01
ca.
C8
FF
12
10
08
04
02
01
07
10.
18
09
12
10
08
04
02
01
03
2A
.
Relllllrka
IBM Disk 1
IBM Disk 2
.~
19
30
87
d8
C8
FF
OA
20
DC
32
2A
50
80
C8
C8
FF
FF
IBM Disk 20
IBM Disk 20
,.
FF
FO
Notes:
1. Suggested values of GPL in Read or Write cqmmandsto avoid overlapping between bata field and 10 field of contiguous sections.
2. Suggested values of GPL in Format a Track command.
3. In MFM mode the DDFDC cannot perform a readlwrilelformatoperation with 128 bytes/sactor (N - 00).
4. Values of ST and GPL are in hexedecimal.
Result Phase:
R
1
Status REiglster 0 (S1;"P)
2
Status Register 1 (ST1)
3
Status Register 2 (ST2)
4
Track Number (T).
5
Heed Number (HI" _
6
Sactor Number (R)"
7
Number of Data EIytes per Sactor (N)"
the sector numbllr is incremented (R + STP - R), and the scan
operation is continued. The SCfln operatioo continulISuntii one
of the following events occur: the conditions for scan are met
(equal, low or equal. or high or equal), the last sector on the track
is reached (EOT), or.Te Is·recelvlld.
If co/ldltiQns for scan are met, theODFDC. se~ the Scan Hit (SH)
flag in ST2 .to ai, and terminates the command; If the condl·
tions for scanar$ not met between the starting sector (asi specified
by R) and the last seator on the track (EdT), thllnlhe DDFDC
~ !he Scan Not Satisfied (SN) flag inST2 to a 1; and tenninates
the C9ffil11alld. The receiPt of TC from the proCessor or DMA con- .
trollerduril\fj the scan operation WiII,cause the ODF.CCto com·
plete tlie cori\parisc)nof.thl! particular byte which is in process,
and then to terminate the Command. Table 6 shows the status
of bIts SM and SN uiKfer various conditions of sean.
• The 10 in.formation hl\S no meaning in this commancl.
SCAN COMMANDS
The scan commands cO'inpare data read from the disk to data·
supplied from the data bus. Thl! DDFoc compares the data, and
looks for a seclor of data which mllets the conditions of DFOO ..
Deus, DFOO ~ DBus, or DFOO i2: Deus (0 = thl! data pattern In
hexadecimal). A magnitude comparison' Is perfonned (FF ..
largest number, 00 smallest nurnber). T~e hexaaecimal byte'
of FF either from the bus or from FDD can be used as a mask
byte because it always mllets thl!. condition of the compare. After
a whole sector of data is compared, if the conditions are not met,
If SK ... 0 and the OOFOC encounters a Deleted DataAddr~
Mark on one. of the sectors, It regards that sector as the last sector of the track, sets the Control Mark (eM) bit in ST2 to a 1 and
terminatllS the command. If SK - l,the DDFDC skips the sector with the De!eted Data Adc!ress Mark, sets the eM flag to a
1 in order to show that a Deletlld Sector has been encountered,
and reads .the next sector.
=
2-325
Double-Density Floppy Disk Controller (DDFDC)
Table 6. ,Sean Status Codes
Stal'!~ Register 2
Command
BI12
,
=
SN
1
0
1
\lFOo ";"Deus
DFOo ¢ Deus
Scan Low or Equal
0
0
1
1
0
0
DFOO = Deus
DFOO < 'Deus
DFOD > Daus
Scan High or Equal
0
0
1
1
0
0
DFOD = Daus
DFOD > Daus
' DFOo < Daus
0
Scan Equal
When eiltler the STP sectorS'are reali (contiguous sectors .. 01,
or ,alternate sectors ,:= 02) or MT (Mu~"Track)' is, set, the last sector on ,the track must be read. For example, if STP = 02, MT '
= 0, the sectors are numbered sequentially 1 through 26, and '
the scaj1command starts readlng.t. sector 21. S~tors 21, 23,
~d 25 are read, then the n,e1d sectOr. (26) is si4Pped and llie Index
Hole is encountered betore,~~e EOT,value, Of 26 can be read.
This results In, an abnormal termlnatioJ.1.of the command.' If the
EOT had been set at 25 or the scanning started at sector 20, then
the scan comml1lnd Would be completed In a normal, manner.
During a ~an ,command d~~ Is SUPPII~d from tlie data bus for
comparison aga,ns\the data'read frOm'the disk. In order to avoid
having the()Ver Ruri(pR)'nag set In ST1, datainust be available
from the data, bus In less than 27 p.S (FM mode) or 13p.S (MFM
mode). If an OR occurs, the OOFOC terminates the command
and sets bits 7 and 6 of STO to 0 and I, respectively,
Result Phase:
R
W
6'
5
4
SK
1
0
0
0
1
X x x
X
liD
USl
uso
1
MT
2
X
3
Track Number (1)
MF
2
3
1
4
Head Numllei (H)
Sect9r Number (R)
6
Number of Data Bytes per Sector (N)
7
s
9
Status Fiegister 2 (ST2)
4
Track Number (1)
,5
Head Numl:ier(H)
6
Sector Number (R)
7
Num!;lEjrof Data Bytes per &!cIor (N)
BYTE
7
6
5
4
3
2
1
W
1
MT
MF
SK
1
1
0
0
1
2
X
X
X
X
X
HD
USI
uso
3
Track Number (T)
0
,.
5
Status Rel:lister 1 (ST1)
3
RIW
Command Phase:
7
'Status Register 0 (STO)
Command Phase:
SCAN EQUAL ' '
BYTE
1
2
SCAN. LOW OR EQUAL
The following tables specify the command bytes and describe
the result bytes for the three scan commands.
RIW
Comments
Bit 3= SH
l'
4
Head Number (H)
5
Sector Number (R)
6
Num~r of Data ,Bytes per Sector (N)
7
End of Track (EOl)
8
Gap Length (GPL)
9
8eclor Test Process (STP)
Result Phase:
R
Elld of TlBck'(EOT)
1
Status Register 0 (STO)
2
Status Register 1 (STt)
"
Gap Length (GPL)
..
SectOr Test Process (STP)
2·326
3
Status Register 2'(ST2)
4
Track Number (T)
5
Head Number (H)
6
Sector Number (R)
7
Number of Data Bytes ~r Sector (N)
0
SCAN HIGH QR EQUAL
Comm,nd Phase:
R/W","
BYTE
7
6
4
3
.~
1~
1
1
X x X
x
l!'
X
3
Track Number (1)
4
Head Number (H) '.',
6
'SeQtor r4umilClr'(R)
·the ~4;lClJtion ph_the OBflagfs _10'0 to Indice& OOFDC
, nol1:'busy. While the DDFDC .is' liI't!:i8 .nci~u8y stIlte.~et
seek command may be i$Sued; and in thIS manner ~Iel Seek
.operationsmay be performed 0(1 all I;trMIsat QIIC8:... , .
O.
US1
0
'1
~command.othei"thanSeekWillbe~Whil.'~ODFOc •.
USO
is.sending. st.ep.. pulses to any FpD.If.a dl~.
. nt.:co.mmand type
is attempted, tile DDFDC Willl!iet.bits 7 arid 6 In STO'to a1 and
.' 0;""re8pectiYely•. to Indicate an .invaildcommanC!,
': ,
"
• ..,
~
per S'9'Or(N) ','
Number of Data Bytes
7
End of, Track (E~m
9
Sector Test Process (STP)
....
Hthe time to write the threebyt8s 01 theSEiekeommand ~s
1~ p$, the tlme.between the first two step pulses may ,be sI:Iorter
th.an the StepR"" Time (SRn defined brthe Specify command
!iV' as much as 1"m s . ' . , ! ,
' I
"
Status Register a (srO)
2
Status Register 1 (ST1) ,
3
statUs RegiSter 2 (ST2)
COmmand Phase:
BYTE"
RiW
w,.,
Track Number (T)
6
Head Number (H)
e
Sector Number (R)
7
Nu~r
"
7
:~
5
3
2
1
~.
.I)
0
0 .. .1
1
1
1.
X
X
X
US1
'USO'
"
.'
2
,"3
Of Data Bytas per Sector (N)
X
'.
4
X "0
N~ TraCk Number (NnIJ",
,
0' ,
. Result Phase: None.
I,
SEEK·
readYs~~ ~t~e'b89lnnitlgoUh; ~
If the FDD Is In not
mandexecutlonph8se or during the seek ~lOn.then the
DDFOC setsthell!c;IIReady.(NR)~·ln,sl'O toal • • StO
··bIts Tand 6 to 0 1II!d,,~ ,res~.~d terminates theeqmrn8nd.
."
1
'4
<
,
.HD
6
Reault Phase'
R
$
SK
the~rnmandPhase'~~he;~k~alIOn t~QDfDC'
sets the .COntrolier Busy (CB) flag In the MSFh01;butduring
....
MT ,MF
W
D\lring
' ",
~
The three-byte Seek command steps .the FDD readlwrlte head
fi'Omtrack.tO track. The Di:;>FDC has two i(ldependent Present
Track Registers for each drive, ,They are Cleared only by the
RElC8/ibrste command. The DDFOCcompare& the Present TraCk
Number (PTN) Which IS.the current head positlon,Withine New
Track Number (NTN), and H thera Is a differencel performs the
following operation:
.
'. RECALIBRATE
This two-byte comrnandret.rac:t$the FDOreadlwrite head to the
Track 0 pOSitlo(l' The. DOFbC Cl8ars the,cor1Cents of .the PTN
counters', an~ checks the. status 01. th~ Track O.sign8J from the
FDD. As long as the Track 0 signal (rR!«l) Is lOw; the direction
signal (LeT/DIRl output ..,mains I~ and step,pulses
I~u~
on· FRISTP. When TRKO goest:righ. the DOFOe sets'the Seek
End (SE) flag inSTO to.a 1 and terminates the command. If the
TRKO is still lOw after 2&6 step 'pulses have ~n~u8d. the
DDFDCsets Seet( End(SE) an.d Equiprne~t Chl!Ck (Ee) Bags in
STO to 1s;sets bils 7 and 6 ofSTO to o and 1, respect~y•.:8!"ld
terminates the command.
'
are
If PTN < NTN: Sets the direction output (LCT/DIR) high
and .issues step pulsell(FRIS:TP> to the FDD
to cause the re~rlte head to step in.
If PTN > ~TN: Sets thedlrectiQn output (lCTIDIR) loW and
issues step pulses to the fDD to cause the
readlwrite he", to step OUt.
' '
Thea:bIlJty to do overiapRecaJibrai~ commands to_multiple FODs
and the lOSS ·ofthe. fli)Y signal, as described In' the Seel( Coin·
mand. alsO appnesti) the Recallbl'ate command .
The rate at which step pulses are Issued Is controlled by the Step
Rate Time (SRn.in the SPecify C()mmand. After eac" step pulse
.is issuBd, NTN is compared against PTN. When NTN = .PTN,
then the Seek End (SE) flag in 8TO Is set to a 1. bits 7 and
in STO are setto O. and the commaiid is terinlnated. At this'pOirii"
DDFDC asserts INT.
.
e
"
Command Phase:
R1W.'
The FOO Busy flag (bit 0-3) in the Main Status Register (MSR)
,qorresponding to the FDDperformlng the Seek operation is set
'to a 1.
.,
.BYTE
W
2
After comma~d termination, .all FDD'BUSY bits set are clear!ld by
the Sense Interrupt Status command.'
.,
7
6
5 .4
3
2 "1
0,
.p
0
0
0
. 1
'x
'X
X
X
X
Reault Phaa.: None.
2~327
o
US1
o
USO·
2""
'
"
.
."
.
Double-Density Floppy Dis.,k Controller (QDFDC)
R6765
SENSE' INTERfI\:IPt. ~!ATUS
Interrupt Request (INl) is: asserted
the foIlowingC9~ltiQns yte of infor~
mation istr,ansferredto~ or from, the OOFDC Data Register. After
each byte of data Is written to, or readlrom, the DatSRegiSter,
the processor should walt 12 ,.s before reading the. MSR. BitS 6
and 7 in the MSR must ,be 8 0, and 1,'respectiVely,before eaCh
command !:Iyte can be written to the DDFDC. During the result
phase, bits 6 and 7,01 the MSR must,bot/I be 1.S prior to reading
,each byte from the Data Register onto the data bus,Note that
this status reading of bits. 6 and 7 of the MSR befora each byte
transfer to and from the DDFDC is required in only the COmin~Od
and l'ElSuli phases and not during the execution phase.
After theSllecify c;ommand haS been received by the DDFOG,
the ,Unit Select nnes {USO and USt) ,begin· the pOlling mode.
Between cOmmands (and between step pulseS In ,the Seek Command) IheDOFDC polls all the FOD's looking lor a, change ,in
the ROY lineirom any of the.drives. If the ROY line ch~ state
(usu~IIY due to the door opening or closing) then the DDFOC
asserts INT. When Status Register o (STO) is read (after Sense
Interrupt suiius, camman,d isissu~), Not Ready (NR = 1) Will
be Indicated. The polling of the RDYUneby theODFDC occurS
continuously between commands, thus notifying 'tj:leProcesSol
which drives I!f8 on- or off-line.· Each dr1\fe is pOlled every 1.(),24 ms
except during read/wrlte COmml\nds.
' .
'
I
2"
'
Double-Density Floppy Disk Controller (DDFDC)
R6765
DATA IN/OUT
(010)
,
(MSR BIT'S)
REQUEST
FOR I\IIASTER
(RQM)
(MSR BIT 7)
WRITE(WR)
FROM DD,FDC TO DATA BUS
FROM DATA BUS TO DDFDC
I
I
I
hJi---'-Ilf---oLJ
I
I
I
II
I
I
I I
I I
I
I "EADY I
I
READ (RD)
L
II
I
A
I B
I
II
, I
I
A
I
I
II
IBI A
I
I
I
I
I
I
II
I
I
I
I
LJ
IC
i
I
I
o
I
ur-~t----;
I I
I clDIBI A
NOTES
o
DATARE;GISTER READY TO BE WRITTEN INTO
[!] DATA REGISTER NOT READY TO BE WRITTEN INTO
@] DATA REGISTER READY FOR NEXT DATA BYTE TO BE READ
~
DATA REGI$TER NOT READY FOR NEXT DATA BYTE TO BE READ
Flgur~ 3. DDFDCand System DataTran~f,r Timing
2-330
.~
CD
U'I
ol1-A1$
1l~
L
0...07
....
iiSr
l1li
Viii
~I-
.
TI ,ill
I
z.oo
~
I~
nil1; l{ul~"
1>-
.0.
~
~L....-
a
~
a.
~ ~\
-ODW
PSII
CPU
PS'
WDA
-§~1IECO\'EJn'
I
WRITE PROTECT
TWC>
WRLowWidth
13
tWLWH
14
DeJa valid to WR High (Setup)
tDIIWH
15
WR High to DaJa Invalid (Hold)
tWHOX
WR High to INT High
t6
twHlH
17 DRO Cycle Time
Iocv
DRQ High to RD, WR High (Response)
18
IoHXH
19 . DACK Low to DRQ Low (Delay)
~L.QL
DRQ High to RD Low (DelllY)
IaHRL
20
DRQ High to WR Low (Delay)
!aHWL
WCK Cycle Time
I tKcv·
21
22
WCKHigh Width
~KL
23 WCK RiSe TIme '
tKLKH
WCKFaliTime
24
~HKL
WCK High to PSO-;-PSI valid (Delay)
25
tKHPII
PSO, PSI, valid to WDA High (Delay)
26
tPVOH
27
WDA High Width
tOHOL
28
WE High to WCK High or WE Low to WCK Low
!eHKH
ROW' Cycle TIme
30
Iwcv
31 . ROW valid to, ROD High (Setup)
IwvRH
ROD Low to ROW Invalid (Holll)
32
tRLWI
ROD High Width
33
tRHRL
Uso,.US1 VSlldto SEEK High (Setup)
35
IuVSH
36
SEEK Low to'USO,USllnvalid(Hold)
IaWI
SEEK High to DIR valid (Setup)
37
IsHbV
DIR Invalid to SEEK Low (Hold)
38
IoxsL
DIR valid to STP High (Setup)
39
IovrH
tTLOX
40 STP Low to DIR Invalid (Hold)
41
STP Low to USO, USI Invalid (Hold)
tTWX
42
STP High Width
tlHTL
43
STP Cycle TIme
tTCY
44
FR High Width
!roHFL
lOX High Width
45
tlHIL
46
TC High Width
tTHTL
47
RST High Width
IAHRL
3
4
5
6
7
8
IPr
t
tAR
tRA
IAR
tRo
tOF
tRI
tAw
!IIln.
240
'tYp.
li:!L
I!O
~
12t)
40
IIl!.O
-
0
0
250
20
-
25
Ic;y.
-
10
60
nole 1
250
tww
low
two
tWI
tiAc;y
iMRW
tAM
tMR
tWi
t,.
t,
lep
leo
Iwoo
tWE
0
0
250
150
5
-
13
-
20
.20
twcH-50 .
20
tWcv
-
'wRD
15
111
tROW
tROD
tus
tsu
.Iso.
tos
toST
Isro
tSTU
tSTP
tsc.
note 2
40
12
15
7
30
1
24
5'
6
333
~
8
t lOX
10
1
14
tTO
lAST
-
?O
ns
100
500
-
--
7
-..,-
Teat
Condltlona
'z
~
~··!UoIU1Z
~-~
'iLI\ • IIl\11t1Z
ns
ns .'
AS
:·",·ns
". ns
ns:
,CL -100pF
n$
ns
ns
- ' . lis
-
50D
12
200
350
20
20
100
100.
. ,.
--
100
:;:.....
-
20
ns
ns
ns
ns
ns
200
.,-
50U
-.
-
-
809
2M
Iwt.
Unit
.,~
-
--
Max.
~'
.,',note, 3
10
.;...
--
.ns
ns
,is
!is' "
ns
ns
ClK _ 8 MHz
AS
,.s ,
.'
ns
·ns·
ns
ns
ns
'ns
ns
,.s
i
ns
ns
ns
.
,.s
,.s
,.s
,pS
,..s
• 'elK - 8 MHz
,.s
'pS
,.s
pS
pos
....!!;r,
~
Ic;y
,
Notee:
1.
MFM
Mini
Standard
0
4pS
2pS
1
2pS
1"s
2. For MFtot ;" 0: Typ. - 2 pS
For MFM = 1: Typ. - 1.p.S
3. tso - 33 pS min. is for different drive units. In the .case of the same unit,
Iso can range from 1 rns to 16 ms with 8 MHz clock period, and 2 ms
to 32 ma with 4 MHz clock, under software control.
2·335
R6765
Double-Density Floppy Disk Controller (DDFDC)
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Value
·NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at
ihese or any other conditions above those indicated in other sectionsofthis document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Unit
Supply Voltage
Vee
-0.3 to + 7.0
V
Input Voltage
VIN
-0.3to +7.0
V
Output Voltage
VOUT
-0.3 to + 7.0
V
Operating Temperature Range
TA
Oto +70
GO
Storage Temperature Range
TSTG
-55to +150
Co
OPERATING CONDITIONS
Parameter
Range
Vee Power..supply·
5.0V ±5%.
Operating Temperature
OOCto 70°C
DC CHARACTI;RISTICS
(Vee
= 5.0 Vde
±5%, VSS
= 0 Vde, TA = OOC to 70°C, unless otherwise noted)
Parameter
Min
Symbol
Input Low Voltage
Logic
CLKaild WCK
Vll
Input High Voltage
. Logic
CLK and WCK
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
Vee Supply CUrrent
Icc
Input Load Current
Unit
Test cardilions
V
-0.5
-0.5
0.8
0.65
2.0
2.4
Vee + 0.5
Vee + 0.5
V
2.4
III
All Inputs
0.45
V
Vee = 4.75V.l ol = 2.0 rnA
Vee
V
Vee = 4.75V, 10H = -200 pA
150
mA
Vee = 4.75V
10
pA
VIN = Vee
-10
pA
VIN = OV
'.
High Level Output Leakage Current
ILOH
10
pA
Vee = OV to 5.25V, Vss = OV
Vour = Vee
Low Level Output Leakage Current
ILOl
-10
pA
Vee = OV to 5.25V, Vss = OV
V OUT = +O.45V
Internal Power Dissipation
PINT
1.0
W
TA = 25°C
-
CAPACITANCE
(TA
Max
= 25°C; fe = 1 MHZ; Vee = OV)
Parameter
Symbol
Clock Input
CIN(O) .
Max Limit
Unit
20
pF
Input
'CIN
10
pF
Output
COUT
20
pF
Note: All pins except pin under ·test tied to ground.
2-336
R6765
Double-Density Floppy Disk Controller (DDFDC)
PACKAGE DIMENSIONS
40-PIN CERAMIC DIP
DIM
A
a
C
D
H
r=l
J~'IIIII ! III! II rIjiBd
L lJ
~L D
SEATINGPLAN~~
K
M
~\.-
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
50.29
14.86
2.54
0.38
0.76
2.54
0.76
0.20
2.54
14.60
D°
0.51
51.31
15.62
4.19
-0.53
1.40
asc
1.78
0.33
4.19
15.37
10'
1.52
INCHES
MAX
MIN
1.980
0.585
0.100
0.015
0.030
0.100
0.030
0.008
0.100
0.575
0°
0.020
2.020
0.615
0.165
0.021
0.055
asc
0.070
0.013
0.165
0.605
10'
0.060
40-PIN PLASTIC DIP
DIM
A
B
C
D
F
G
H
J
K
L
M
N
2-337
MILLIMETERS
MIN
MAX
51.28
INCHES
MIN
MAX
52.32 2.040
13.72 14.22 0.540
5.08 0.140
3.55
0.36
0.51 0.014
1.52 0.040
1.02
2.54 asc
O.lDO
1.65
2.16 0.065
0.20
0.30 0.008
3.05
3.56 0.120
0.600
15.24.BSC
7'
10'
7°
0.51
1.02 0.020
2.060
0.560
0.200
0.020
0.060
BSC
0.085
0.012
0,140
BSC
10'
0.040
fJ
SECTION 3
R6500/*MICROCOMPUTERS
Page
Product Family Overview ............. , ........ ; ................... '" . . . . .
3-2
R65COO/21 and R65C29 Dual CMOS Microcomputer
and Dual CMOS Microprocessor ................... . . . . . . . . .. . . . . . . . . . . . . . .
3-3
R65F11 and R65F12 FORTH One-Chip Microcomputers. . . . . . . . . . . ... . . . . . . . . . . ..
3-35
R65FRX and R65FKX RSC FORTH Development and Kernel ROMs. . . . . . . . . . . . . ..
3-67
R6501 Q One-Chip Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ..
3-75
R6500/1 One-Chip Microcomputer ........................................... 3-104
R6500/1E Emulator Device ................................................. 3-135
R6500/1 EB and R6500/1 EAB Backpack Emulator .............................. 3-142
R6500/11 and R6500/12 One-Chip Microcomputers ............................. 3-147
R65/11EB and R65/11EAB Backpack Emulator ........ , ........................ 3-182
R6500/13 and R6511Q One-Chip Microcomputer and One-Chip Microprocessor ..... 3-187
R6500/41 and R6500/42 One-Chip Intelligent Peripheral Controllers .. , ............. 3-222
R65/41 EB and R65/41 EAB Backpack Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-251
R6500/43 and R6541Q One-Chip hltelligent Peripheral Controllers ................ 3-256
3-1
R6500/* SINGLE-CHIP MICROCOMPUTER FAMILY
Higher Performance, Broader Applications, Software Compatibility
The R65001* single-chip microcomputers are completely
software compatible with the 8-bit multi-chip, family: They let
you move easily from a multi-chip to a single-chip system
solution when the application warrants it. They also function
as intelligent peripheral controllers. The family continues to
expand to inc,lude dual processors and CMOS versions. The
R6500/' devices have faster execution speeds for most
applications, based on our competitors own figures, even
though some others use higher frequency crystals.
Features include 1.5 to 3K bytes of ROM, 64 to 192 bytes
of RAM, 23 to 56 I/O ports, multiple use counter/timers,
serial communication channels, new bit manipulation
instructions, expansion bus, multiple bus interfaces, directly
executable RAM with low power standby, multiple interr.upts,
all from a single 5V power supply.
Three intelligent ,peripheral controllers offer design
effective upgrading potentials for existing 6800, 8080, Z80
and 6500 systems. They're also available in ROM-less
versions, for large memory system applications and for
developing and simulating products in prototype, with
external memory.
And, two versions even have all, system software on chip,
including an operating system and high level FORTH
language. It's an extremely versatile single-chipper.
Three different sets of development ROM permit systems
from 16 to 40 I/O and 8K to 48K of application program
memory.
As the highest performance single-chip family, the
R6500/' devices are in use now in applications such as
printers, telephone answering equipment, fixed disk drives,
stereos, industrial controllers, telecom, cash registers,
sewing machines, test equipment and more.
Check for yourself and see how a Rockwell R65001* can
solve your system problem, There are no higher performing
8-bit single chippers, regardless of clock speeds.
ROCKWELL NMOS MICROCOMPUTERS~THE TOP PERFORMERS IN INDUSTRY
Features/Models
• ROM (x8)
• RAM (x8)
.110 Lines
• Serial Comm.
• 16-Bit Cou n1ers
• HosllSlave Bus
• Expansion Bus
• Interrupts
- External
-Internal
-Host
R6500/1
R6500l1t
R6500/12
R6501Q/11Q
2048
64
3072
192
3072
192
192
32
USART
TWO
56
USART
32
ONE
~
6
4
6
4
6
4
-
• Package
12
40 DIP
Alternatives for
8048/49
-
1536
64
1536
256
64
ONE
65K
35
40 DIP
R6541Q
-
16K
4
1
R6500/42
32
USART
TWO
16K
-
• Standby RAM (mW)
TWO
-
-
-
R6500/41
23
64 QUIP
8051
12
64 QUIP
8031
3-2
23
-
-
80/65
ONE
80165
80/65
4K
4K
8K14K
-
4
1
2
-
12
64
47
40 DIP
ONE
4
1
2
64 QUIP
8041
5
1
2
64 QUIP
R65COO/21.R65C29
'1'
Rockwell
R65C00121 DUAL CMOS MICROCOMPUTER
·AND R65C29 DUAL CMOS
MICROPROCESSOR
PRELIMINARY
INTRODUCTION
FEATURES
• Nine interrupts
.,--Positjve and negative edge detect
-Low level detect (external IRQ)
-Counter/Timer A and B underflow
-Inter-processor communication
--'- Host computer data transfer
-Non-maskable
-Reset
• Flexible system operation
-Memory mapped I/O for easy programming
-Page zero location for memory efficient access
• Low power at norma.1 frequency (4.0 mw at 2 MHz)
• Re(juc~d power at low. frequency (2 ..0 mw at 2 MHz/128)
• System. clock rates from 1.0 KHz to 4 riIIHz
• 5V j:·10%power supply
• 64-pin QUIP
• Two enhanced 'CMOS R65D2 CPU's in one device
-Common memory and I/O
-Shared data and subroutines
-Independent CPU registers and interrupt vectors
-Independent reset operation and programs
-A65D2 software and timinIJ compatible
• 1.0 n.ew instructions for faster and smaller programs
-Unsigned Muttiply (MUL)
-Set a.nd Reset Memory Bit (SMB and RMB)
-Branch on Bit Set and Reset (BBS and BBR)
- Unconditional Bra.nch(BRA)
-Push and Pull Index Registers (PHX,PHV; PLX, PLY)
• .Microcomputer/microprocessor/peripheral. controller operation
-Stand-alone· microoomputer
2.048 x 8 mask programmable ROM
128 x 8 random access memory (RAM)
-Enhanced microprocessor
Built-in RAM, ROM and I/O with expand ability
8-, 12- or 16-bit extension address bus
-programmable peripheral controller
Host data bus interface (Z8D/8D8D or 65.0.0/68.0.0 option)
Self'contained or expandable
• 16-bit Counter/Timer A with eight modes, and prescaler
- Timer Off
-Free-Run Event Counter
-Free-Run Pulse Width Measurement
-One-Shot Retriggerable Timer
-One-Shot Interval Timer
-Free-Run Interval Timer
-One-Shot Pulse Generator
-Free-Run Pulse Generator
• 16-bit Counter/Timer B with four modes
-Free-Run Interval Timer
-Free-Run Pulse Generator
-Event Counter
- Pulse Width Measurement
• Up to 52 general purpose input/output lines
-Five bidirectional 8-bit ports (PA, PB, PC, PO and PF)
-One 8-bit output port (PE)
-One 4-bit input port (PG)
-Multi-purpose operation for selected ports
SUMMARY
The Rockwell R65CDD/21 is a complete, high performance
8-bit. CMOS dual microcomputer in a single chip and is compatible with all R65DD microprocessors except that it has
additional instructions including a lD-clock time multiply.
The R65C.O.O/21 consists of two enhanced instruction set 65.02
CPU's in one device. The device also has 2.048 bytes of ReadOnly Memory (ROM), 128bytes of Random Access Memory
(RAM) and versatile interface circuitry. The interface circuitry
consists of two multimode programmable 16-bit counter/timers
and 52 general purpose input/output lines. Some of these input!
output lines may be used as address, data and control lines
for expanded systems or as data and control lines when the
R65CD.O/21 is used as a programmable· peripheral controller.
The two CPU's in the R65COO/21 are functionally independent.
Each has its own set of registers, its own reset and interrupt
vectors and operates under control of its own program. The two
CPU's do, however, share the same memory and system I/O
resources. This allows direct communication between the two
CPU's and allows sharing of subroutines and common data
areas where desired. Programming and system design for
applications which require simuttaneous control ·of two or more
independent asynchronous processes is thus simplified because
one CPU may control one process while the other controls
Document No. 29651N64
3-3
Product Description Order No. 2161
Rev. 1, March 1984
R65COO/21 • R65C29
Dual CMOS Microcomputer/Microprocessor
DEVELOPMENT SYSTEM SUPPORT
another one.. Consequently, complex programming usually
needed to interleave the control funCtions or to implement an
interrupt driven system, is npt required.
p{ptotYl;lecircuit and software development support are available. using the Rockwell Design Center (ROC) and R65COO/21
Personality Module. Program development and debugging aids
such as text editing, symbolic assemblywifh c;onditionE!ls.and
macros at the absolute and relocatable/linking level, ~nd sillgle/
multiple step execution' wtth instruction/data tracing are provided.. Real-time in-circuit emUlation in the target environment
is also' supported.
In a multiple computer approach, both processors may need the
same subroutines so that some portions' of memory must be
duplicated in both systems. The dual CPU's share the same
program memory, therefore only one set of subroutines is
required and both CPU's may even be using them at the same
time without interference.
In addRion to the dual CPU's, the R65COO/21 also has the
innovative architecture and the demonstrated high performance
of the we II established R6502 CPU, flexible input/output which
provides improvements over the R6522 Versatile Interface
Adapter (VIA) device, and production efficient on-chip ROM and
RAM. These features make the R65COO/21 a leading candidate
for most imbedded microcomplJterapplications.
AI.I descriptions of R65COO/21 operation in th.is document
also apply to the R65C29 except for internal ROM, and
as otherwise noted.
'
A system using the R65COO/21. Dual CMOS Microcomputer will
be simpler in design, use less program memory, require fewer
components, reduce circuit board sizes, simplify test requirements, and minimize field maintenance-all contributing to lower
production and support costs. In addition, simpier designs shorten
development effort and time:--cle,adingtoreduced de,velopment
costs and faster product; to market.
The R65COO/21 Dual CMOS Microcomputer can be ordered in
volume qiJanltties wtth the following Speed capability 'and mask
option indicated in the R65COO/21 ROM Code Order Form (Document Order No. 2134)
NOTE
ORDERING INFORMATION
• 1,.2, 3, or 4 MHz system clock ~2)
• CrystaVrnaster clock or slaved clock input mask option
The R65C29 Dual CMOS MicroprocesSor, a ROM-less version
of tile R65COO/21 wRh permanently extended data and address
bus, is also available, The R65C29 is ideal lor dual CPUapplications requiring changeable ROM and/or extended RAM, ROM
or
and can also be used for R65COO/21 prototype circuit
development. The R65COO/21 can also operate in an emulation
mode, like the R65C29, with tts internal ROM disabled.
The R65C29 Dual CMOS Microprocessor has the following
characteristics:
'
va,
• CrystaVmaster clock input
• 8-bit data bus and 16-bit address bus extension
• No internal ROM
3-4
Dual CMOS Microcomputet/MicroproCeSS9i'
R6SCOO/21 •. R65C29
INTERFACE
The interfaces for the
in Figure 1.
R6~COO/21
.
The interface signals for the R65COO/21 and R65C29 are
described in Table 2. The desCriptions of the selectable, bus
expansiOn pins (16-bit address mode) for the R65COO/21 apply
to permanent bus expansion pins for the R65C29.
and RS5C29 are illustrated
.
The pin assignments for the R65COO/21 and the R65C29 are
shown in Rgure 2. The R65C29 pin aSSignments are the same
as the R65COO/21 except that bus expansion func;:tions are permanently assigned instead of general purpose ports 0 and E.
.VDD
CPU A
CPUB
OSCILLATOR
CLOCK
GENERATOR
2048x8
ROM
R65COO121 ONLY
128x8
RAM
CONTROL
REGISTEiRS
I
I
I
I
II
I
PORTA
PAO-PA7
PORTB
PBOIPB7
PORTC
PCO-PC7
OPTIONAL USE:
HOST DATA BUS
PORTD
PDO-PD7
OPTIONAL USE:
EXP.BUS
. DATA/LOWER ADDR.
PORTE
PEO-PE7
OPTIONAL USE:
EXP.BUS
DATA/LOWER ADDR.
PORTF
PFO-PF7
OPTIONAL USE:
PFO POS. EDGE
DETECT
PF1NEG. EDGE
DETECT
PF2I;XT. IRQ INPUT
PF3 TIMA 110
PF4 TlMB 110
PF5 --PF6 -~PF7 HINT
PORTG
PGO-PG3
OPTIONAL USE:
PGO H'2IHRD
PGt HRJW/HWR
PG2 HRS
PG3'CS
TIMER A
TIMERB
I
8
Figure 1. R65COO/21 and R65C29 Interface Diagram
3-5
B
R65COO/21 • R65C29
Dual CMOS Microcomputer/Microprocessor
XTALI
IIA
SYNC
PE7
02
EMS
R!W
PE6
PE5
PE4
PE3
PE2
PEl
PF7
R65COO/21
PEO
PF6
PF5
PF4
PF3
PF2
PFl
PFO
PA7
PA6
PA5
PF4
PA3
PA2
PAl
Vss
PAO
XTALO
XTALI
02
OA
EMS
SYNC
RM
A15
A14
A13
A12
All
Al0
A9
R65C29
A8
PF7
PF6
PF5
PF4
PF3
PF2
PFl
PFO
PA7
PA6
PA5
PA4
PA3
PA2
PAl
PAO
Vss
Figure 2.
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
.42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Vce
RES
NMIA
NMIB
PGO
PGl
PG2
PG3
POO
POl
P02
P03
P04
P05
P06
P07
PCO
PCl
PC2
PC3
PC4
PC5
PC6
PC7
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
Vec'
NMIA
NMIB
PGO
PG1
PG2
AO/OO
PG3
Al/01
A2/02
A3/03
A4ID4
A5/05
A6/06
A7/D7
PCO
PCl
PC2
PC3
PC4
PC5
PC6
PBO
PC7
PBl
PB2
PB3
PB4
PB5
PB6
R65COO/21 and R65C29 Pin Asignments
3-6
RES
PB7
[)~,al 'CMO~Nlicro~9mpUferfMi.crop"C)cessor
R65COP/?1'. R65C29
Table 1
Signal Name
R65Co0/21 Pin DesC:~Ip1;lons '
PinNa.
I/O'
31·24
va
40-:33, ,
I/O
4B·:4:1
56·49
VO
VO
PEO·PE7
15·8
0
Port E. General purpose 8:bit oUtput PortE. Upper'addrel3S (A8to Al1 or A8 to A15) when
Bus Expansion Mode is seleCted:
'
",
' '
,
"
PFO·PF7
23-16
110
Port F. Gene~al Purpose B-bit 110 'Port
fUnctions as follows: '
PFONEG (PFO)
PF1POS (PF)
PF2LOW (PF2)
TIMA(PF3)
TIMB(PF4)
HINT (PF7)
PGO·PG3
23
22
:!1
20
19
16
60-57
I
PAO-PA7
PBO·PB7
pCO·PC7
PDO·PD7
i
va
I/O
0
I
60
I
HF\lWiHWR (PG1)
~
,I
HRS (PG2)
58
57
I
I
RES
83
I
82
I
NMIB
61
I
EMS
riA
5
3
7
8
4
XTAlO
1
0
XTALI
VCC
VSS
2
I
84
32
F. Onde~ sOftware"contrOl, each line has aHer!l8te
'
"
,
,
II
PFOPoeltive Edge Detect. MaSkable CPU irllernipl on PF0Foskillfi TransHion,
PF1 Negative Edge Detect.'Maskable CPU intel'1'upt on PFl Negative Trans_ion:
PF2 L_ L~IDetect. Maskable CPU inter~uPt ~f>F2 Low (exiernaIIRel).
Timer A External Input/Outpul
Timer B External Input/Output.
Ho8t 1"*ruPt- Active·low' maskable interrupt request to Host.
Po~t ,G. General purpose 4-bit input Port G. Onder software control, PO,rt G!I8r~s as the
Host ,Control Bus as follows:
'
I
"2/HRO (PGb) ,
CS(PG3)
Description
P~rt A. Gel1l!ral purpose B·bit VO Port A.
Port B. (jeneral purpose B·bit I/O Port' 8.
Port C. General purpose B·bit I/O P611 C. Host Data Bus in Host MOde.
Port D. Genera,l purpose 8~bit VO Port O. MuHiplexed ,lower ,address (AO to A7) and Data
Bus (00·07) when Bus Extension Mode is selected:
'
Holli Bus Clock/Reed Strobe Input. to! for 65op/8apo, bus; Read Strobe",for Z8Ol80SQ
bus.,
Host Bus Reed-Wrlte/Wrlte Strobe Input. ~Wfa: 8500/68OQ bus; Write Strobe for
Z8OI8080 bus.
" ,,
Host ,Bus Reglliler Select Input. Low seleetsOata BUffe~; high selects Status
F1ag~.
HQ81 Bue Actlile,i.Ow Chip Select Input. Low selects, Host Bus operation depending O!l
HRS arid HRiW/HWR coding and Host pontrol and Statlls Register ,conte~; high
disables Host 'Bus interface:
',,,
"
"
' , " ",
"
R_t. A'ctive·low Reset input, initializes R65Coo/21 to initial conditions-resets all registers
and 110 Unes.
CPU II. Non-Maekabie Interrupt. Non-maskable negative edge sensHive interrupt input to
CPUA.
CPU B NOn-Maskable Interrupt. Non·maskable negative edge senskive, in\errupt !RPut to
CPU B.
'
"
NMIA
to!
F\lW
SYNC
:,'
0
Exttrnel NJemciry Strobe. Active-low.
,
S)'8t8m Phsse' 2 Clock
MasjQmle as sYStem clock input for slave operation.
Qu.,ut'
.0
Read~rite. ReadlWrne control, output. High during read. low lIuring wrHe.
0
0
Sync. Instruction sync output; ,High When Op COde fetched
a
PhsseA. Phase A cloCk output. High during CPU A bus cycle, low during CPU Bbus
cY,CIe'
Cry818l/Master Clock Return. Output connection 19 <;r~ (or no CQIlnection jf ~xternal
master
clock conneeted
to XTALI). Input frequency is two times system clock (t.!) rate.
'¥'
.. ,
Cry81alJMester Clock Input. Input connection from crystal (or external master clock).
P_er. ,5.0 Vdc.
GNP. I>i~nal and power ground.
"
3-7
,I
Dual .CMOS NlicrocomputerlMicroprocessor·
R6SCOO/21. R6SC29
FUNCTIONAL DESCRIPTION
,._
"
v'-'"
•
INDEX REGISTERS
The R65Coo/21 consists of two central processor units (CPU's),
a 2048 x 8 read-only memory (ROM). a 128 x 8 randem ac~ss
memory (RAM), five 8-bit parallel VO ports, one 8-bit output
port, one 4-bit input port, two ,16.-bit counter/timer systems,. a
variety of VO control registerS,: I!lnd an independent interrupt
control system for each CPU. All of t~ ROM, RAM, VO, internal
buses, and the arithmetic .Iogic unit (ALU) are shared by the two .
CPU's. A memory map of the ~stem is shown in Rgllre 3. An
overall block diagram of the .R65COo/21 is shown in Figure 4..
Eaeh CPU has two index registers, X and Y. Each index regiSter
may be used as a modifier to a base address supplied as a part
of the instruction being processed. The resuHing effective address
is usually the sum of the base add.ress pillS the contents of the
. indicated index register. The index registers are used in a
number of the addreSSing modes including zero page indexed,
absolute indexed, post-indexed indirect· and pre-indexed indirect. Each index register also has. a family of instructions which
allow. loading, storing, incrementing, decrementing, and.comparing the contents of the register. These are discussed thoroughly in the R6500 Programming Manual (Order No. 202).
NOTE
Throughout tliispocument, unless specified otherwis~, all
memory or register address locatioil~ are· specified in'
hexadecimal notation.
ADDRESS {HEX)
INTERNAL MEMORY
0000
001F
0020
INTERNAL READ..()NLy-ftIIEMORV'(ROM)
003F
11040
007f
0080
The ROM in the ~65CoQ/21 c:on§ists, 9f20~8 (2'1<) bytes of (!:lask
programmable memory with an address space from F800 to
FFFF; ROM locations FfF2 through FFfF are assigned to interrupt and reset veCtors for the two CPU's:
.
I/O AND CONTROL REGISTERS
EXTERNAL 110 EXPAN~ION2
NOT ACCESSIBLJ:
INTERNAL RAM (128 BYTESj1
(SHARED WITH 0ISo-0IFF).
DOFF
0100
017l:
0180
'.":
INTERNAL RM~D()M ACCESSMEIIIIORY (RAM)
The int9rnal RAM consists of 128 bytes of read/write memory
with assigned page zero addresses of 0080 through OOFF.
EXTERNAL RAM .EXPANSION2
INTERNAL RAM (128 BYTESj1
(SHARED WITH 0080-00FF)
01FF
0200
EXTERNAL MEMORY AND
I/O EXPANSION2
EFFF
FOOO
F7FF
F800
EXTERNAL MEMORY
External memory can be addressed by selecting the Bus
Expansion. Mode. in the Bus Control Re~ister. Addrel?s space
from 0200 through EFFF. may be accessed for either RA'M,
ROM. or VO purpoSes as the particular application req'uires it.
In addition, there are 32 bytes from 0020 through 003F.which
may be used for VO expansion .and 256 bytes from 0100 through
01 FF which may be external RAM.
.,
NOT ACCESSIBLE
INTERNAL ROM (2048 BYTES)
FFFI
FFF2
FFF3
CPU lOGIC
Each CPU in the R65COO/21 is effectively a standard R6502
CPU with 10 extra instructions utilizing 4:0 operation codes which
are unused in the R6502. Therefore, each CPU has an 8-bit
accumulator, two 8-bit index registers (X and y), an 8-bit Stack
Register, a 16-bit Program Counter. independent interrupt Circuitry. and an instruction register with state counter. The internal
buses, memory, instruction decoding circuitry, and ALU are
shared by the two CPU's on aHernate clock cycles.
..
NMIS VECTOR
FFF4
FFF5
RESB VECTOR
FFF6
FFF7
IROB VECTOR
~~~:
NOT USED
FFFA
FFFB
NMIAVECJOR
FFFC
FFFD
R~SAVECTOR
FFFE
FFFF
IROAVECTOR
Notes:
1. When bit 4 of the BuS Control R9gister (BCR) is a 0 (default value),
the 128 bytes of internal RAM are redundantly mapped into both
page zero and page one and are addressable as either OO8o-OOFF
or 0180-01FF. When BCR bit 4 is a 1, all of page one RAM
(256 bytes) is mapped externally (0100-01 FF) and the 128 bytes
of internal RAM are dedicated to page zero (OO80-00FF),
2. Accessible in bus expansion mode.
ACCUMULATORS
The accumulator in each CPU is a general purpose 8-bit register
that stores the resuHs of most arithmetic and logic operations.
Additionally, the accumulator contains one of the two data words
used in these operations.
Figure 3_
3-8
R65COO/21 Memory Map
Dual CMOS Microcomputer/Microprocessor
R65COO/21. R65C29
I'NTERRU~
CONTROL
INTERRUPT
FLAG
AND STATUS
BITS
F
I
F
I
I
PRESCALER
REGISTER
~
INTERRU~
LATCH
ENABLE
.L
I
NMlA~
INTERRUPT
LOGIC
NMii------ll£
P
I
Rei~
CLEAR
INTERRUPT
FLAG
c
INSTRUCTION
DECODE
REGISTERS
PROCESSOfJ
STATUS
1
CLOCK
SELECT
1
I
f
XTALI
CLOCK
+2
OSCILLATOR
XTAW
J
CLOCK
GEN
"I
I'
OA
t
POWER
CONTROL
REGISTER
I
0'
I
J
I A:~Gf~~S I
.~
TIMER A
CLOCK
SELECT
1
COUNTERmMER A
~~=gL
II AND
STATUS
REGISTER
I
I
,I"I
•I
.1 ;6~~:tL
REGISTER
INSTRUCTION
(+128)
I
I
I
I
I LOWER
I
J LOWER COUNTER J
SNAPsHOT REG. I
UPP&R LATCH
UPPER
LATCH
COUN~R
;=,.
I+--PF3
COUNTeAmMER B
.
!l
I
UPPER LATCH
L
S
e
UPPER COUNTER
I
J
LOWER LATCH
LOWER COUNTER'
I
j
1+--"
I+--
;i
z
I
INDEX
REGISTER
y
i'"
I
-II
INDEX
REGISTER
X
CO~~'oL
AND STATUS
REGI.STER
I
DATA
DIRECTION
IF.
I
I
ALU
I
I
I
I
I
l
ACCUMULATOR
I
STACK
POINTER
PCL
PROGRAM
COUNTER
PCH
I
L
I
~
I
~
DATA
DIREgrlON
I
~
I
RAM
I
1
128)118
ROM
204S x.
I
I
(R6SCOO!21
ONLY)
l
Figure 4.
0
I
I
I
z
Note:fj
Indicates dual registers - one
for CPU A and one for CPU B
DATA
DIRECTION
I
L
BUS
DATA
OIRE;rION
DATA
DIRECT10N
A
I
PORT F
I/O
PORTE
OUTPUT
1
I (HO:,.ag-:::ROL)
1
I
PFO-PF7
(SPECIAL
FUNCTIONS)
I
J
P''''.7
(Aa.A11
OR
I
1
PORTD
I/O
I
I
PDQ-PIl7
(A(t.A7
AND
00-07)
I
PORTe
I/O
1
I (HOS~c::r~7BUS)
J
I
W
1
I
1
l
R65COO/21 and R65C29 Block Diagram
3-9
INPIIT
A8-A15)
I
CONTROL
REGISTER
PORT G
PORTS
I/O
PORTA
I/O
I
I
PS()"~B7
1
J
PAo-PA7
PF'
R65COO/21. R65C29
Dual CMOS Microcomputer/Microprocessor
STACK POINTERS
FFFC) and in CPU B (RESB at FFF4) when power is applied
to the R65COO/21. Each time a processor fetches an instruction
from memory, the lower (least significant) byte of its program
counter (PCL) is placed on the low-order eight bits of the address
bus and the higher (most significant) byte of the program counter
(PCH) is placed on the high-order eight bits of the address bus.
The counter is incremented each time an instruction or operand
is fetched from memory.
Each CPU in the R65COO/21 has its own independent 8-bit
Stack Register located in RAM on page zer%ne and is pointed
to by a Stack Pointer. Each Stack Register is automatically
incremented and decremented under control of the appropriate
CPU to perform proper stack manipulations in response to user
instructions, an IRQ interrupt or an external NMI interrupt of the
appropriate CPU. The Stack Pointers must be initialized by the
user program.
The contents of the program counter are replaced with a new
value when a JMP, JSR, RTS, RTI, BRK, or any of the branch
instructions are executed. Also, the program counter value is
replaced when an external non-maskable interrupt NMIA or
NMIB, an internal interrupt request, an external interrupt request
via PF2 (see Port F description) or reset (RES) occurs.
These stacks allow simple implementation of multiple level
independent interrupts in each CPU, subroutine nesting, and
simplification of many types of data manipulation w~hout
the programmer continually being aware of specific memory
addresses. The JSR, BRK, RTI, RTS, PHA, PLA, PHP, PLP,
PHX, PLX, PHYand PLY instructions'all make use of the stack
and the appropriate CPU's Stack Pointer.
INSTRUCTION REGISTERS AND
INSTRUCTION DECODE
Each stack may be visualized as a deck of cards which may only
be accessed from the bottom of the deck, The value to be stored
is written on a card and then that card is placed on the bottom
of the deck (pushed onto the stack). When the data are to be
read, the ,bottom card is removed from the deck and the value
on it transferred to the appropriate register (pulled from the stack
to the specific register). Each time data are to be used as an
address, the value is stored in the addressed memory cell, and
the Stack Pointer is decremented by 1. When the data are read
(or "pulled") from the stack, the Stack POinter is incremented
by 1 and the resulting value can be used to address the data.
The data are read from the addressed memory cell and then
transferred to the appropriate register in the CPU,
Instructions selected by the program counter are fetched from
ROM or RAM (or Port D if in Expanded Bus Mode) and gated
onto the internal data bus. These instructions are latched into
the proper instruction register and then decoded using common
decoding cirCUits for both CPU's. Timing, status bits, and interrupt controls are interpreted together with the instruction code
to generate control signals for the various registers in the
appropriate CPU.
INTERRUPT LOGIC
Each CPU has its own logic which controls the sequencing of
three types of interrupts: RES, NMI, and IRQ. The same RESET
(RES) pin is used for both CPU's; consequently, reset occurs
on both CPU's at the same time. A different reset vector (RESA
and RESB) exists for each CPU to allow initialization of the separate and independent programs.
Each CPU must have an independent starting location for its
stack. It is the programmer's responsibility to see that the RAM
utilized for each CPU stack does not conflict. It is recommended
that the CPU requiring less depth in its stack be assigned the
OXFF location and the other stack be started a safe distance
below it. The two stacks are physically located either on page
zero (although addressed as page one) for single-chip operation, or externally on page one when extended addressing is
selected. (See Note 1 in Figure 3). The default areas for the
stacks are on page zero. In either case, both stacks are on the
same page.
Separate pins are used for the two processors' non-maskable
interrupts (NMIA and NMIB). Each processor has its own NMI
vector; CPU A uses NMIA Vector at FFFA and CPU Buses
NMIB Vector at FFF2.
Three different types of external interrupt conditions can be
detected by connecting the external signal to one of three Port
F input pins. A positive-going edge, a negative-going edge, and
an external interrupt request (IRQ), I.e., a low level, can be
detected on PFO, PFI and PF2, respectively. Internally, IRQ
conditions can be generated by time-out of either of the two 16bit counter/timers, upon interprocessor-communication request
by the other CPU, or by the Host Interface Port.
ARITHMETIC AND LOGIC UNIT (ALU)
All arithmetic and logic operations for both CPU's take place in
a shared ALU. Incrementing and decrementing of the index registers and memory also take place here. The ALU stores data
for only one cycle. Consequently, data placed on the inputs at
the beginning of a cycle are processed and gated to one of the
registers, or to memory, during the next cycle.
In each case, the interrupt condition is reported as an interrupt
flag in a controVstatus register associated with the functional
area. Each CPU can either enable or disable IRQ generation by
setting or resetting a corresponding interrupt enable bit in the
same or associated controVstatus register.
Each b~ of the ALU has two inputs. These inputs may be tied
to various internal buses or to a logic zero; the ALU then generates the function (AND, OR, SUM, etc.) using the data on the
two inputs.
PROGRAM COUNTERS
Furthermore, each CPU can control whether or not its processing is interrupted when an interrupt request (IRQ) is generated. Each CPU has its own Processor Status Register (PSRA
and PSRB) with the capability of disabling IRQ interrupts when
its own "I flag" bit is a 1.
The 16-bit program counters for each CPU provide addresses
that step each processor through sequential instructions in a
stored program. The program counter for each CPU is initially
set to the value stored as the reset vector in CPU A (RESA at
3-10
R65COO/21. R65C29
Dual' CMOS Microcomputer/Microprocessor
instruction branches if the bit tested is a 1. If the bit tested is not
set to a 1, the next sequential instruction is executed. This
instruction requires five cycles if the branch is not executed, six
cycles if the branch executes to the same page, or seven cycles
if it branches to a different page.
NEW AND MODIFIED INSTRUCTIONS
In addition to the standard R6502 instruction set,. ten new
instructions have been added and minor timing and other
changes have 'been made to a few other instructions. All of these
additions and changes are discussed in this section. Aefer to
the Instruction Set Op Code Matrix for the operation codes and
addressing modes of all instructions. The times indicated for
each instruction are given in terms of CPU clock-times.
BRANCH ON BIT RESET RELATIVE
(BBR m, ADDRESS, DESTINATION)
This instruction is similar to the BBS instruction except that the
branch takes place if the bit tested is a O.
UNSIGNED MULTIPLY (MUL)
The 10 clock-time hardware muHiply instruction muliiplies the 8bit contents of the Y register by the a-bit contents of the A register to give a 16-bit product. At the completion of the' multiply
operation, the most significant half of the product resides in the
A register and the least significant half in the Y register. This
operation uses unsigned numbers only. This instruction uses the
implied addressing mode and, consequently, requires one byte
for the op code.
INDEX REGISTER STACK OPERATIONS
(PHX, PLX, PHY, AND PLY)
These instructions are similar to the PHA and PlA instructions
in the conventional R6502 except that they push or pull the X
or Y registers to and from the stack, respectively. The push
instructions require three instruction cycles and the pull instructions require four cycles.
SET MEMORY BIT (SMB m, ADDRESS.)
UNCONDITIONAL BRANCH (BRA)
This instruction uses zero page addreSSing only and requires
five cycle times. It sets the designated bit in the addressed
memory cell or 110 port to a 1. The' first byte of the two-byte
instruction identifies the operation and the bit to be set while the
second byte designates the address of the word in which the bit
is to be set. Eight op codes are used for the eight bit locations
in a byte.
This unconditional branch is a branch always instruction. It operates similar to the conditional branches of the R6502 except that
tlie relative branch always occurs. It executes in three cycles if
the branch is to the same page orfourcycles if it is not. Two bytes
are required, one for the op code and the other for the relative
address.
INSTRUCTION DIFFERENCES FROM R6502
RESET MEMORY BIT (RMB
m, ADDRESS.)
Decimal add and decimal subtract instructions on the R65COOI
21 require one cycle time longer than their. binary equivalents.
The add and subtract times are the same for both decimal and
binary operation on the R6502.
This instruction operates in the same way as the 5MB instruction except that the bit is set to O.
BRANCH ON BIT SET RELATIVE
(B.BS m, ADDRESS, DESTINATION)
The decimal mode flag (D) in the processor status registers
default to binary (D =0) operation when the R65COO/21 is RESET,
whereas this bit'is uninitialized on the R6502.
This instruction tests one of eight bits designated by a three-bit
immediate field within the first byte of the instruction. The second
byte deSignates the address of the byte to be tested within the
zero page address range (memory or 1/0 ports). The third byte
of the instruction specifies the a-bit relative address to which the
The indirect jump instruction increments the page address when
the indirect pointer crosses a page boundary, whereas on thl!
R6502 it does not.
3-11
3
: Dual, CMOS MicrocomputerlMicroprocessor
R65COO/21,.·R65C29
PROCESSOR STATUS REGistERS
own8~~1
DECIMAL MODE 811' (D)
The decimal mode bit (D)eontrols the arithmetic mode of its
CPU. When this liit is set tO'a ~;, the adder operates as a decimal
adder lorthe Add with Carry (ADC) and the Subtract With Carry
(SBC)instructidns. These instructions, iii the decimal mode,
require'one additional CPU cycle time compared with binary
niode or the decimal inode in the conVentional R6500. (In the
conventional R6500, the decimal and binary arithmetic operations are the same speed.) When the bit is a 0, the arithmetic
is performed in straight binary. T~ declmai mode is controUed
',ooly by thecprogrammer;fQr each o~ the CPU's. The Set Decimal
Mocte (SED) instr\jCIion CaUses decimal arithmetic to be performed and the C,lear Decimal M~ (CLD) instruction causes
biriarY arithmetic to be perlormed by that CPU. The PLP and
IilTI instructions alSo affect the d~mal mode bit
Each CPU has its
Processo/Status Register."Each
register contains seven status, flags;, Some
these flags
are controlled by the user program; others may b~ (lQl)trolled
both by the user's program and the appropriate CPU. The
R65COO/21 instruction set contains a number ,of conditio!)al
branch instructions which are desi!jned to allow testing DUhe,~
flags.
'
0'
CARRY BIT (C)
v;
""
,,
The carry bit (e) ,can be consiqered the nint", bit of ar:larithmetic
'operation. It is set to a'1 if a carry fr:oJTi' the eighth bit has
ciccurred, or It is cleared to 0 if no carry has occurred, as a result
" of. arithmetic or" shift operations.
i
The D bit 'for e~h CPU, is'automat~lly set to the zero state
(binarY mode) when the R65C00/21 is reset by RES.
The carry bit may be set'or.qleared under program cqntrol by
use of the Set Carry (SEC) or Clear Carry (CLC) instructions,
respectively. Other operations which affect the carry bit are
ADC, ASL., CMp, CPX, CPY, LSR, PLp, ROL, ROR. RTI" and
BREAK aIT (B)
sec.,
Zi:'Ro
The break, Pit (8) determines the"type of condition which caused
the IRQ service routine, to be entered. IfthelRQ service routine
Wasernered because a BRK instruCtion, was execl,lled by its
9F'U, tl),e Bbit~t to ,a1. II the S!lrvi¢eroutlnew~ entefl!d
6Bc;auseof an IRQ, signal being generated, the Ef 1$ set to a
There are no inStructions which directly set or clear this bit.
BIT (Z)
The ~ero~it (Z)' is set to a 1 by the CPU during any data movE!,
mems, or cak:ulations, Which sets all eight bits,of theresultt0
zero for thl;iICP/J. This bit is cleared to a 0 when all eight bit!!
of a data movement, or calculation, operations are not all zero
for that CPU: The R6500' instruction set contains no ,instruction
to specifically, set or',clear'tli8 Z flag bit. ThEi;Zflag bit is,hoWever, affected, by the following instructions: ADC, AND"ASL.
BIT, CMP,CPX, CPv; DEC, DE)(: DEY, EOR, INC,INX,INY,
LOA, LOX, LSR, ORA, PLA, PLP, PLX, PLY, ROL., ROR, RTI,
SBC, TAX, TAY, TXA, TSX, and TVA.
o.
OVERFLOW BIT (V)
'The overflow bit (\I) indicates that the result 01 a signed binary
additioo or s!lbtraction operatIOn is a value which cannot be con,tained in seven bits (outside the range of -128 to +127). This
indicator only has meaning when signed arithmetic is performed. In this case, the arithmetic operations are :being performed on the sign and seven magnitude bits lor one byte, or
the most significant byte 01 a longer signed number. When the
ADC or SBC instruction is execl,lled, the overflow bit is set to
a1 il the polarity 01 the sign bit is:changed because,the re~ult
exceeds +127 or -128io absOlute magnitude. Otherwise, the
V bit is cle,ared to a,O. The VQit may be cleared by the programmer by executing-a Clear OverflOW (CLV) inst!Uction in the
appropriate CPU.
1~T..EFlRUPT DI,SABLE BIT (I)
The interrupt disable bit (I) controls the servicing of an interrupt
request (IRQ). If the I bit issetto'a 0 in the ProCessor Status
Register of one, or bOth, of the CPU's, the iRa signal will be
serviced by that particular CPU. If the bitls set to a 1 for one
or both of the CPU's, the IRQ signal will be ignored by that CPU.
Each CPU will set its intElrrupt disable bit to a 1 if a RES, an
IRQ,' or its non-maskable interrupt (NMI) signal is detected.
Interrupting one processor does not affect the other one unless
it is programmed to respond to the same interrupt.
The overflow bit is also affected by the BIT i~struction. The BIT
instruction samples specifiC bits in memory or VO interrupt
status words. Most of the VO devices used in the R6500 family
and most of the interrupt flags in the R65C00I21 have interrupt
flags in the upper two bits of the register. The BIT command
copies these two most significant bits of the addressed word into
the, N and V flags. The V flag is set to the same state ~ bit 6
of the addressed words and the N flag copies bit 7.
The I bit is cleared lor each CPU when that CPU executes a
Clear Interrupt Disable (CLI) instruction and is set under software control by a Set Interrupt Disable (SEI) instruction. This ,bit ,
is also Set by the Break (BRK) instruction. The Return From
Interrupt (RTI) and Pull Processor Status (PLP) instructions also
affect thE! I bit by selting it to the value which was stored on the
stack. '
The instructions which affect the IJ flag are ADC, BIT, CLV, PLp,
RTI and sec.
3;12
Dual CMOS Microcomputer/MicroprocesSOr
R65COO/21 • R65C29
NEGATIVE BIT (N)
The negative bit (N) indicates that the sign bit (bit 7) in the
resulting value of a data movement or arithmetic operation is
a 1. If the val~e represents a signed number, the most significant bit being a 1 indicates a negative number. If the sign bit is
a 0, the 'resu~ is interpreted as a positive value. The BIT instruction copies the most significant bit of the addressed memory cell
or I/O register .into the N flag bit
There are no instructions that set orclear the N bit directly since
the N bit represents only the status of a result. The instructions
which produce a result that affects the stale of the N bit are
AND, ASL, BIT, CMP, CPX, CPY, DEC, DEX, DEY, EOR, INC,
INX, INY, LOA, LOX, LOY, LSR, ORA,PLA,PLP, PU(, PLY,
ROL, ROR, RTI, SBC, TAX, TAY, TSX, TXA, and TYA.
Processor Status Registers (PSRA and PSRB)
7
6
5
4
3
2
1
NEG
(N)
OVFL
(V)
NOT
USED
BRK
(B)
DEC
(D)
IRQ
ENBL
(I)
ZERO
(Z)
Bit 7
1
0
Negative (N)'
Negative Value
Positive Value
Bit 6
1
0
Overflow (0)1
Overflow Set
Overflow Clear
Bit 5
Not Used (Don't care value) ,
Bit 4
Break Command (B)'
Break Command
Non-break Command
-10
Bit 3
-1
0
Bit 2
-10
lli!..!
1
0
Bit 0
-1-
0
0
CARRY
(C)
Decimal Mode (0)3
Decimal Mode
Binary Mode
Interrupt Enable (If
IRQ Interrupt Disable
IRQ Interrupt Enable
Zero (Z)'
Zero ResuK
Non-Zero Resu~
Carry (C)l
Carry Set
Carry Clear
Notes:
1. Nol InHialized, by RES,
2. Set logic 1 by RES.
3. Cleared to logic 0 by RES.
4. There are two Processor Status Registers, one for each CPU.
3-13
Dual.CMOS Microcomputer/Microprocessor
R65COO/21 • RlSC29',.
INPUT/OUTPUT AND CONTROL/STATUS REGISTERS
. REGISTER ADDRESSES
Seven controV~atus" registers control and monitor the basic
operation oUhe R65COO/21. The registers and their', primary
functions are as foll,aWs:
, . '
Table 2 shows the input/output, controVstatus and timer/counter
registers which are addressed on page zero from locations 00
through 1 D. Some of the registers combine other functions when
they are read or written. The table lists both the primary and
secOndary types of functions. Table 3 summarizes the register
formats.
.
.
SCR
Bus Control Register-defines expansion bus
•modes
'.,
.
HCSR . Host COI'ltrcil arid Stirtus Registerc-defines host
bus and interruPts
,
.,
InlemJpjControl and Status Register~nables
ICSR
and reports il1terrupt conditions
Clear Interrupt Flags Register
CIFR
Power Control Register-seleCts low power
PCR
mode
TACSR Timer A ,Control and Status Regist4;lr:-controls
and monitors'Ti{l1er A OPeration ,'"
TBCSR Tirner'S Control' and Status Register-controls
and monitors Time~ B operatio!1
All controVstatus registers and data direction registers are cleared
a RES. Thus, the zero state of each bit defines th~
default operating modes. Eai:h' register is associated with a
functional area in the microcomputer, e.g;. parallel input/output,
timer/counter, bus cOntrol, etc. The detail operation of each register IS,defined in the appropriate sections.
to zero
bY
Thirteen registers are used for input/output functions and nine
registers used for timer/counter functions. The use of these registers is discussed in later sections.
Table 2
Address
00
01
02
03
04
05
06
07
OB
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
1.7
lB
19
I/O, Control/Status and Timer Registers
Read
PA Data
PB Data
PC Data. O-'+tBF3
PC Data. 0-+IBF3
PO Data'
PFDilta
PG Data
-
-
BCR
HCSR
ICSR
-
PCR
TACSR
LCA. UCA-+SLA
SLA
SLA. O->UFA2
lA
lB
lC
10
TBCSR
LCB
UCB
UCB. O-+UFB2
IE
IF
-
~Iater Neme/N,otes
Write
PA Data
PB Data
PC Data. 1.....0BE. O-+RS03
PC Data. 1....0BE. I .... RS03
PO Data'
PE Data'
PFData
PA Direction
PB Direction
PC Direction
PC Direction
PO Direction'
Port A Data I/O
Port B Data I/O
Port C Data I/O
Port C Data I/O
Port 0 Data I/O
Port E Data Output Only
Port F Data I/O
Part G Data Input Only
Port A Direction
Port B Direction
Port C Direction
Port C Direction
Port 0 Direction
;
PF Direction
Port F Direction
BCR
HCSR
ICSR
CIFR
IPCIR
PCR
TACSR
LLA
ULA
ULA. ULA-+UCA.
L~LCA, O-+UFA2
TBCSR
LLB
ULB
ULB. ULB-+uce. LLB-+LCB. O-+UFB2
Bus Control Register
Host Control and Status Register
Interrupt Control and Status Register
Clear Interrupt Flags Register
Inter-Processor Communication Interrupt Register
Power Control Register
Timer A Control and Status Register
Timer A Lower Counter (LCA)/Lower Latch (LLA)
Timer A Snapshot Latch (SLA)ll,Ipper Latch (ULA)
Timer A Snapshot Latch (SLA)/Upper I;atch.
Download and Start Timer
Timer B Control and Status Register
Timer B Lower Counter (LCB)/Lower Latch (LLB)
nmer B Upper Counter (UCB)/Upper Latch (U/-B)
Timer B Upper Counter (UC6)tUpper Latch (ULB).
Download and Start -rimer
-
-
Notes:
1. Addressed externally· when in expanded bus mode.
2. Counter/Timer underflow flags:
UFA ; Timer A Underflow Flag bit in TACSR
UFB ; Timer B Underflow Flag bit in TBCSR
3. R65C00l21 to/from Host data transfer bits in HCSR:
IBF ; Input Buffer Full flag bit
aBE ; Output·Buffer Empty flag bit
RSI ; Register Select Input bit
RSO ; Register Select Output bit
4. - ; Not used-indeterminate data when read
3-14
Dual CMOS Microcomputer/Microprocessor
R65000/2.1. R65C29
Table 3. Control/Status Registers Formats Summary
Address
(Hex)
Bit Number
7
10·
CPUA
. ACTIVE
alP
11
BUFF
FULL
INT
FLAG
(OBF)
IPCA
INT
FLAG
12
IPCB
INT
FLAG
CLR
IPCA
INT
FLAG
13
CLR
IPCB
INT
FLAG
4
5
6
2
PAGE
ONE
EXT
NOT USED
VP
BUFF
FULL
·INT
FLAG
(IBF)
3
va
REG
SEL
(RSI)
(RSO)
NOT
USED
PF2
LOW
INT
FLAG
PF1
NEG
EDGE
INT
FLAG
PFO
NOT
USED
CLR
PF1
NEG
INT
FLAG
1
PORTA
NIBBLE
MODE
VOA
INT
ENBL
0
BUS
EXTENSION
MODE
HOST
INT
ENBL
HOST
BUS
ENBL
.. HOST
IPCA
INT
ENBL
PF2A
INT
ENBL
PF1A
INT
ENBL
PFOA
INT
ENBL
IPCB
INT
ENBL
IPCB
INT
ENBL
PF1B
INT
ENBL
PFOB
INT
ENBL
VOB
BUS
TYPE
INT
ENBL
pas
EDGE
INT
FLAG
BUS
CONTROL
REGISTER
(BCR)
HOST
CONTROL AND
STATUS
RI;:GISTER
(HCSR)
INTERRUPT
CONTROL AND
STATUS
REGISTER
(ICSR)
""
14
CLEAR
INTERRUPT
FLAGS
REGISTER
(CIFR)
CLR
PFO
pas
NOT USED
INT
FLAG
INTERPROCESSOR
COMMUNICATION
INTERRUPT
REGISTER (IPCIR)
" WRITE ONLY REGISTER-NO SPECIFIC BIT (IPCIR)
15
LOW
PWR
CPU B
(LPB)
NOT USED
16
TMRA
UNFL
FLAG
(UFA)
PF3
LEVEL
IND
NOT
USED
TMRA
INT
ENBL
lA
TMR B
UNFL
FLAG
(UFB)
PF4
LEVEL
IND
NOT
USED
TMRB
INT
ENBL
TMRA
CLK
PRESC
SEL
LOW
PWR
CPUA
(LPA)
TIMER A
MODE
SELECT
NOT USED
TIMER B
MODE
SELECT
POWER
CONTROL
REGISTER
(PCR)
TIMERA
CONTROL AND
STATUS
REGISTER
(TACSR)
TIMER B
CONTROL AND
STATUS
REGISTER
(TBCSR)
Note: All control and status registers are cleared to zero by RES
INTERRUPT CONTROL AND STATUS
TACSR Timer A Control and Status Register
TBCSR Timer B Control and Status Register
Unlike other R6500 family devices, the R65COO/21 does not
concentrate the interrupt flags into a single register. The
R65C00/21 , in general, places the interrupt flags in registers
which also have to do wnh the control of the particular function
which can cause the interrupt.
Portions of each of these registers relating to interrupt enables
are duplicated for each of the two CPU's. However, only one
memory address has been allOcated so that each CPU uses the
same address to select its own interrupt enables. The specific
details of the usage of the interrupt control bits are discussed
in the corresponding functional area.
Interrupt enable control is located in the following registers:
HCSR
ICSR
Host Control and Status Register
Interrupt Control and Status Register
3-15
II
,
'
R65COQ/21.:R65C29
>
Dual CMOS Mlcrocomputer/Mlcropr'oo..,or
CLOCK CIRCUITS
POWER CONTRO~ REGISTER,(~R)
CLOCK OSCILLAtoR
Two bits in the PoWer Control Regisler (PCFt) determine' operation of the clock prescaler. Each CPU can se( its own power
control bit an,d read both of them. When ,both power cOntrol bits
are a 1, the system switches to the low power,operation at a
clock rate of 162/128 (g'2PS): The Systemieverts to 'normal
power and speed when either power control bit is a 0 or when
an enabled Interrupt occurs. In the latter case; thE! system con:
tinues to operate at the low rate until the CUrrell! Instruction is
completed, then it switches to the normal rate. The Power Control Register is shown In Fjgure7.
The internal clock oscillator generates the system clock (162)
which clocks all' R65C00I21 operations. The system clock frequency ranges from 10 KHz to 4 MHz (the upper limit determined by the R65COO/21 part number) which is one-half the
external crystal (or master clock) frequency. Each CPU in tum
operates at one-half the 'system Clock frequency (alternate
cycles). All operationS to memory or VO take place at the system
, clock frequency. Silice, each CPU shares tile comr'/lon segments
of the system on alternate system clock cycles, all, internal
operations dccUr at the system cloCk rate but, for CPU timing
purposes, a CPU cycle rate of half the system rate is used. Thus
with a 4 MHz crystal frequency, the system clock rate is 2 MHz
and each CPU operates at an effective 1 MHz rate. Every two
system clock peri6d~ sees one qycle devoted to CPU A and one
cycle devotes:! to CPU ,8.
NOTE
An enabled interrupt automatically clears,the PCR bit for
the affected CPU. It must be set again by software to
resume low power mode.
.2
The
clock is normally routed externally to clock external
memory operations in the extended bus 'mode. A mask option
allows the .2 clock to be configured as an input so the
RSSC00I21 can operate in a slaved clock mode. In this case"
the ci'ystal input (XTALI) 1$ grounded and crystal output (XTALO)
is left open as shown In Figure 5:
Power Control Register (PeR)
I 61
7
5
I
4
I
3
NOT USED
LOW POWER OPERATION
The divide-by-'128 clock prescaler operates in one of three ways
(see Figure 6). One is the prescaler switched completely out
which gives a system clock rate (11'2) at one-half of the crystal
frequency. Another way is to seleCt the low power operation for
bothCPUs which switches in the clock prescaler. The clock
prescaler divides the system clock frequency by 128 ,to generate
the prescaled system clocl< rate (~2PS). This reduces the device
power requirements and also reduces the counting rate of both
counter/timers by a factor of 128. The third operating mode for
the prescaler is to use It for preSCali1J9 Timer A only. This mode is
discussed under the CounterlTimer Operation.
I
2
1
0
LOW
LOW
I'W~
CpOB
(LPa}
CPU A
(LPA)
~
Not U88d (Ooo't care)
Bit'
Low Power Mode select for CPU B (LPB)
Low power mode requested by CPU B
Normal power mode requested by CPU B
-,
o
Bit 0
,
o
Low Power Mode Select for CPU A (LPA)
Low power mode requested by CPU A
Normal power mode requested by CPU A
Notes:
,. Both CPU's can read both bHs.
2. Each CPU can only write its power control bH.
3. Both bRs must be set to enable low power mode.
3-16
I'WR
Dual CMOS Microcomputer/Microprocessor
R65COO/21· •.R65C29
OUTPUT CLOCK
D
INPUT CLOCK
XTALO
. SLAVE
MICROCOMPUTER
MASTER
MICROCOMPUTER
II
INVERTER USED WHEN SLAVE
IS TO OPERATE OUT OF PHASE
WITH MASTER
Figure 5.
V. CRYSTAUMASTER CLOCK ...:i.
Time( £I. ill a Simpler timer t;'~ln' TinierA bJtit Still retains great
flexibility. Unlike Timer.'f\. there is no ,"off" mode (the default
mode is fhe..Free-Run Interval Timer Mode) and there is noeeparateselectable clock prescaler. Ail counting (except for counting
external events)is'done either at '. the f/I2' clock' rate orl~2I.12a
rate'(when loW power mode is selected); Another difference is
that Timer;'B does not have~e snapshot latch register for
freezing the upper timer byte for reading. However, in its normal
modes the ,counter counts through zero tose! the Underflow
Flag B (UFB) so that a snapshot latqh regiSter is not required:
.
Timer A Free-Run Pulse Width Measurement,
Mode 2
, Writing to ULA at 0019 transfers the 16"bil latch to the counter
which operates as a timer in this mode. The initial value in the
timer is decremented at the 1112 rate when the PF3 signal is low.
Otherwise, the counter holds ,its value. Counting Stops when the
PF3 signal goes high and will resume if the signal goes low
again. If the counter counts below zero, the counter initial value
is reloaded from the latches and the UFA flag is set.
Timer A One-Shot RetriggerableTimer, Mode 3
Timer B Mode ContrOl
This mode is similar to Mode 4 except that the timer restarts
each time PF3 goes through a high-to-Iow transition and counts
down until the counter goes through zero. A second difference
is that the clock prescaler may not be used with this mode. The
data direction register bit 3 (PF3):must pe zero to select input.
The oper,ation of Timer B is controlled 'and monitored by the
'
Timer B Control and Status Register (TBCSA).
Bits 0-1 select the Timer B operating mode.
Timer.B Interrupt Enable, bit 4, when set to a 1 by a CPU,
en9S with Timer B:.However, when Timer B is
not using this bit it may be used,as arlY other input or output bit.
In i:\ny eveRt. bit 40f the Port F, Data Direction Register must
be set appropril;ltely for either input or output whe\.hElr or not it
is used witr Timer B.
Timer A Free-Run Interval Timer, Mode 5
. '
Writing ULA at 0019 transfers the 16-bit latch value to the timer
and starts it running. The counter counts down at either the 912,
or the scaled 912 (1d2l128), rate. When the counter counts through
zero the UFA flag is set, the value in the latches is transferred
to the counter, and the counter continues to count down.
.'
B,it 7 in,the TBCSA is. the UF9 bit which .indicates that Timer B
has. counted down through zero. This, may ,be detected by
reading the bit or may be used to cause an fRO interrupt if bit
4 of the TBCSA is set to a 1. The UFB bit is reset by either
reading UCB or writing to ULB at address 001 D.
3-22
R65,COOI21. R65C29
, Dual ,CMOS Microcomputer/Microprocessor
zero,the Timer B Underflow Flag (UFB) is set to a 1, the value
in the latches is transferred to the counter and the counter continues to count down.
Timer B Control and Status Register (TBCSR) ,
6
7
5
4
TMRB
PF4
TMRB
UNFL
NOT
LEVEL
INT
FLAG
USED
ENBL
INO
(UFB)
3
I
NOT USED
1
I
0
TIMERB
MODE
SELECT
Timer B Free-Run Pulse Generation, Mode 1
The data direction register f6rPF4 must be set to a 1 to select
PF4 output befOre starting this mode. Writing to ULB at 001 J)
sets PF4 to 0 to fOrce the PF4 OIItput low and starts the timer.
Each time the timer cOl,lnts through zero, the PF4 output c;:hanges
state'tO generate,asquare wave at a rate dependent upon the
initial value lolided iri!Othe latcl:\es. The timer counts at the fI2
Timer B Underfl_ Flag .(UFB)
Underflow condi~on occ.~rred
No underflOw
Bit 7
1
0,
Part F Bit 4 (PF4) Level Indicator
" PF4High
"PF4 Low
BitS
-1
o
Bit 5
Not Uaad (Don't cere)
Bit 4
§i!!.H.
Timer B Interrupt Enable
Enable Timer B Interrupt
Disable Timer B Interrupt
Not Uaad (Don't care)
Bits H)
Timer B Mode Select (TJlS)
1
o
.1
.Q.
1
1
0
1
0
1
o
o
2
r~te.. eac.h time the c.Quirter counts through zer.,.o. the latch values
a~e automatically transferred to the timer registers and the UF8
flag is set to 1.
.
o·
a
Timer B Ev.ent Counter, M.ode 2
"
'
".!
The data direction register bit for PF4 must be set to a 0 to select
PF4 input prior to selecting this mode. The counter is loaded
with the latch value'when the ULB data is written to address
001 D. Timer B then decrements by 1 at each negative transition
on input Port PF4. The,Timer B Underflow Flag (UFB) is set to
a 1; when Counter B counts through zero. At this same time,
the latch value is reloaded into Timer B. The maximum rate of
the signal on PF4 which may be detected is one-half of the Il2
clock rate.
Free-Run Inlerval'Timer.Mode
Free-Run Pulse (leneratar Mode
Event Counter Mode
Pulse Width Measurement Mode
Timer B Operating Modes
Timer B Pulse Width Measurement, Mode 3
The Timer B operating mode is select$d by setting bits 0 and
1 in the TBCSR to the appropriate code.
Writing to ULB at 0010 transfere the 16-bit latch value to the
(42
courrter. The initial value· in the timer is decremented at
rate when t,lie PF4 Signal is low. Each time the PF4 sigoai goes
hig!). the counter stops and then .continues when. the signal ,is
low ag~in. If the counter counts through zero. the UFB flag Is
set to 1 and the latch value transfers to reinHialize the counter
and tlie countdown continues as long as PF4 is low.
the
Timer B Free-Run Interval 'Timer, Mode 0
Wrtting to Timer B .Upper Latch (ULB) at 0010 transfers the
16-bit latch value to the timer and starts it .running. The counter
counts down at the ¢2 rate. Wheh the counter courits through
3-23
R65COO/21. R65C29 ..
,-"
DuaICMOSMicrocomputer/MIc;:roprocesaor
BUS EXTENSION
:Figure 9, is an overall block diagram of a system using t~e
R65COO/21 in the bus extension mode.
'
'
In addition to its application as a single-chip microcomputer, the
bus extension mode allows the R65COO121 to operate as a microprocessor with extemal memqry and 110.
The CPU A Active signal (bit 7 ot the BCR) is high when CPU
A is controlling the system bus, and low when CPU Bis active.
This bit copies the stalaof thef/lA outpUt slgl1a1. Consequeiitly,
the bit may be sampled in common subroutineS to determine
the ceiling CPU, or for bank selectlOnpufpoSEis. Thus, CPU A
and CPU B may haVe sonie external mernQry or'VO dedicated '
to their exclusive use. Each may separatelY address Ii\S much
as 59.5K bytes of external memory map, o'r ellternal memory:
may be shared.
' !', ,;" ,
BUS EXTENSION MODE
When the R65COO/21 is, used as a single-chip mi~rocomputer,
aU of the output pOr~s may be U$8d
input or output pqrts.
Howevl!r, to use th8 R65C00121 with ex~rri/lI'IiIOM, RAM, or
110, a nuniber of, the portsliCf as extemilions of the internal
address and dai~ buses. Specifically, Port 'D becomes dedicated as a multiplexed 8-bit data and address bus. Port D provides both the data bus (DO jhrough07) and. ,the, l.ow bits of the
address (AD through A7) on pins PDOthrough P07. When a bus
extension mode is selected, the Port D Data Direction Register
must be cleared to zero(Hs default'condition} to configure Port
D ,as all inputs. The R65CO\l/21 then controls Port D as an
extension otthe internal bus structure and provides ari'activelow External Memory Select ,(EMS) strobe signal at the time the
address bits
ava,ilable. ,The, EMS: signal is, present aven
when Port D is being used as a 'normal input/output register.
,as'
Bus Control
7
6
CPUA
ACTIVE
I
5
NOT USED
Reglst8t {BCR)
4·'
PAGE
ONE
EXT
3
(
2
POR1 A
NIBBLE'
MODE
1
,I
0
'.,:
BUS
EXTENSION
MODE
are
CPU A Actilta ,
CPU A active'
CPU B aCtive
Bit 7
-'-1
The R65COO/21 has theoptiQn of using 8-,12- or 16-bit address
bus extensions. Selection of the bus extension mode is cootrolled by bits 0 and 1 onhe Bus Control Register (BCR). When
the S-bit mode is selected, only the PortO multiplexed address!
data bus function is required. HoweVer, if eHhi;,r the 12- or ill:
bit address bus extension is selected,eHher one 'half or aU of
the' bus extension
output Port E also becomes dedicated
function. If a 16~bit bus extension is selected,' then all of Port E
becomes the upper address bits A8 through A15 on pins PEO
through PE7, respectively. If the 12-bit bus extension is selected,
then the address lines AIHhrough All appear on PEO through
PE3. In this case, PE4 through PE7 have their usual output
function.
o
BHs 6·5
Not Uaed (Don't Care)
Bit 4
Page O~ Ibternallinlarnail Mapping
Page One EXternal,':'
Page One Interna,l
1
o
to
BHs 3·2
2
o
o
~
0
1
o
1
Since Port D is multiplexed, it is necessary that external latches
be supplied to hold the lower eight bits of the address bus. The
EMS output is low when the address is being supplied from Port
D. All of the other necessary control bus Signals are also provided; these include ~2 and R/W. The SYNC and 0A signlils are
also brought out for use by development systems and bus analyzers for system debugging.
Bits 1-0
.!. .Q.
o
o
1
1
0
1
0
1
.
PDi't A Write Nibbl. Control'
CPU A writes to both halves (PAO·PA7).
CPU A wrH&s to upper half (PA4-PA7); CPU B
writes to lower half (PAO-PAS).
CPU A wrHes to lower half (PAO·PAS); CPU B writes
to upper half (PA04-PA7).
CPU B writes to both halves (PAO-PA7).
Bus Extension Mode
Bus Extension Mode not selected.
a-bit Address Extension Mode. Rang~ equals 256.
12·bit Address Extension Mode. Range equals 4096.
16·bit Address Extension Mode. Range equals
65,536.
Note:
'EHher CPU may read the full port at ariy time.
In a one-chip configuration, the 128 bytes of internal page one
RAM (address 0180 through 01 FF), is logically combined with
page (0080-00FF). However, when an extended bus is used,
the stack page may be addressed in its normal range in external
, memory (0100-01 FF). When bit 4 of the Bus Control Register
is a O,page one is internal and shared with page zero; when it
is aI, page one is external allowing full 256 bytes available to
the two stacks.
3-24
R65COo,,',121. R6IsC29"
,
"
,',."
,
, ~, DUaICM()S' Microcomputer/MlCroproceas6r "
'
•
PORTA
•
PORTB
PQIJfC
RISCOO/21
DUAL
MICROCoMPUTER
•
PORTF
PORTO
PORT E UPPER ADDR 0, 4, ••
SYNC
~TCH
LOWER
ADDR
•
•
LOWER ,
ft-_ _~A_DDR~____~~
DATA
•
UP TO
59.5K BYTES
EXTERNAL
MEMORY"
AND
PERIPHERALS
NOTE;
·UPPER ADDRESS EXTEN$lON MAY BE 0, 40,R' LINES.
Figure 9. Bus extension Mode Block Diagram,
.'J.
3·25
"
R65COO/21 •• R65C29
Dual CMOS Microcomputer/Microprocessor
Table 4.
·PROGRAMMABLE PERIPHERAL:
TO A HOST MODE
CS
HAW
Htl2
(PCl1.)
. (PGO)
H
L
-
-
-
L
L
L
H
H
L
H
H
L
H
H
H
(PG3)
An overall block diagram of asystern using an R65COO/21 as
an intelligent controller is shown in Figure 10.
In this configuration, three of the R65COO/21 input/output ports
have special significance. Port C becomes the interface with the
host data bus (Port C's Data Direction Register must specify as
the input; i.e., all zeros). Pin PF7becomes an active-low.Host
Interrupt (RINT) line, and the 4-bit input Port G becomes the
control pins Interface to the Host computer.
. The R65COO/21 is configured tooperale as a peripheral for
either the R6500 or 6800 families, or the Z80 or 8080 families.
When operating in the 6500/6800 mode, PGO is an input for the
hoSt rt2 (Hrt2) and PGl is the input for the host R/W (HRW)
control iines.
.
•
When operating in the Z80/8080 mode; PGO accepts the host
AD (HRD) control and PGl provides the hoStWR (FiWR) control.
.In both cases, PGg,serveS asaregister'select (HRS) and PG3
acts as an active-low chip select (CS) from the host.. HRS. is
used in conjunction with the CS and HWRto control reading or
writing of data or status information as shown in Table 4.
Register Select Control
fiRS
(pG2)
L
L
Host Interface D~selected
Write Input Suffer,
HCSR5 !'lSI cleared, set IBF
Read. Output BUffer, Clear OBF,
Write Input Buffer,
HCSR5 RSI set, set IBF
Reacr uPPer 3 bits of HCSR;
OBF, IBF & Rsp .'
H
CS
HRS
HWR
HRD
(PG3)
(PG2)
(PG1)
(PGO)
H
L
-
-
-
L
L
L
H
H
L
L
H
L
H
H
L
L
Host Funetion
(650016800 Mode)
L
Host Functlo.n
(BD1IDIZ80 Mode)
"
Deseleciecf
Write Input Buffer,
HCSR,5 .Rl1lcleared, setlBF
F\ead OutpulBuffer, Clear OBF
. Write Input Buffer,
HCSR5. FlS1 set, set IBF
Read upper 3 bits of HCSR;
OBF, IBF & RSO
H
Host Control and Status Register (IiCSR)
7
Cqntrol of the host mode options is provided by the HoSt Control·
and Status RegiSter (HCSR).
When the host writes a byte into the Input Bulfer (Port C), the
Input Buffer Full (IBF) flag is set to a 1. Similarly, when a byte
is read from the Output Buffer (Port C) by the host, the Output
Buffer Full (OBF) flag is cleared to a O. Setting bit 3 of the HCSR
enables generation of an internal interrupt request (IRQ) when
either the IBF flag is a 1 or the OBF flag is a O. This logic ·is
duplicated for both CPU's.
5
6
OIP
VO
BUFF
FULL
INT
FLAG
(OBE)
BUFF
FULL
INT
FLAG
(IBF)
;
4
VO
REG
NOT
SEL
USED
(RSI)
(RSO)
3
IIOA
INT
ENBL
~
I/OB
tNT
ENBL
2
HOST
INT
ENBL
1
HOST
BUS
ENBL
0
HOST
BUS
TYPE
Output Buffer Empty (OBE) Flag
1
o
Setting bit 2 of the HCSR to. a 1 enables generation of any
interrupt signal to the host computer. In this case, bit 7 01 Port
F is pulled low by either a write to Port C (Output Bufler) or a
read from Port C (Input Buffer), by either of the R65COO/21
CPU's.
Bit 6
1
Input Buffer Full (IBF) Flag
Input Buffer Full
Input Buffer Empty
Bit 5
Register Select
.
. Distinguishes commands from data. Hosi reads
RSO and R65C00/21 reads RSI. Selection of 1 or 0
to represent commands or data is user defined.
o
Bit 5 of the HCSR is actually two different bits representing Register Select Input (RSI) and Register seiect Output (RSO). The
R65COO/21 writes bit RSO and reads bit RSI, while the host
writes RSI and reads RSO. The R65COO(21 writes a Oto this
bit when Port Cis addressed at 0002 and a 1 when Port C .is
addressed at 0003. When the hoSt writes to the R65COO(21
through Port C, the level of the HRS input is copied into the RSI
bit. This bit allows.the communications between the.host'system
and the R65COO(21 to flag the type of data being transferred
so that command information may be distinguished from data.
Output Buffer Full
Output Buffer Empty
!l!!.i.
Not Used. (Don't care)
Bit 3
-1-
Input/Output Buffer Interrupt Enable
Enable IRQIBF = 1)
Disable IRQ .
o
~
1
Host Interrupt iHiNT) Output Enable
Disable R1IiIT Output to Host
Enable HlN'I' Output to Host (OBF = 1)
Bft 1
1
Host aus Enable
Disable Host Bus
Enable Host Bus
8110
1
Hoat BuS Type
Host Bus is Z80/S080
Host Bus is 6500/6800
o
o
o
Note:
Register is cle,ared to all zeros by RES.
3-26
;,,;'1·""
!
I, \. ~
,
,,~~\,; ,I. ,J:. ',''''
"
, "DuaIQMo,S'~'i~r~~omPQterl~iCroproce8$(jr
R65COO/21.R65,C29··
II
R8SCOO(21
S'
DUAL
MICROCOMPUTER
UseD
AS AN
INTELLIGENT
CONtROLLER
PORl'E
SYNC
PORT« ..osy DATA
PGO
BUS a..
H.2JiiiiQ
HOST
t--""O';'=~"""""-----I
SYSTEM
P~ ~~-----~------~ .
·"J1.'",
,
"
EMULATION MODE
The'R65COO/21 can operate in an emulation mode Ijnder external signal oon.trol.
Emulation mode deselects the internal ROM and .enables the
l6-bit Expanded Bus mode, independent of the bus mode programmed in the BUs Control' Register, Since the Expanded Bus
mode uses peripheral Ports D and E,' provision is made for
these to be emulated in external hardware. This is accomplished' by forcing all memory references to Ports Dand E to
be External Bus cycles. Accesses to the Data Direction Register
for Port D' are also forced external.
TOfU~her aid prdgr~m'development in emulation mode, all bus
cyotes w.t\ich perlorrn,a memory or VO write operation, whether
'.Ih9th.ie destin~tiop:mtemal Of external, will assert the External
" 'Memb('y'Strobe (IE S). signal. This allows a copy of internal reg, iSier and'memory ve.lties to be kept in external memory.
, \'
"
',' I=mulation ml>de.' is selected by applying the ~2 output clock
! , signal to the, ,RES input pin.
.
'.
",.
""
Dual ,CMOS Microcomputer/Microprocessor
INSfRuct'iON.SET IN ALPHABETIC SEQUENCE
The following table cootains,a summary of t~ R65C00l21 a.l')d
A65C29 CPU instruction Set. ,For~tailed information, consult
the R6502 Microcomputer System Programming Manual, Order
No, 202.
'
The instructions notated with a ' are added instructions fOr the
. R65COO/21 and R65C29 which are not part of the standard
6502'instruction set.
Instruction Set 1n AlphiilbetlcSequence
'"
Mnemonic
OescrlptlO/1
ADC
AND
ASL
Add Memory to AccUmQII~tor wtth Carry
"AND" ·Memory.wHhAcoumulator .
SMt Laff.One Bit (Memory or Accumulator)
'BRA
'BBR
'BBS
BeC
BCS
BEQ
BIT
8M1
BNE
BPL
BRK
BVC
BVS
Branch Always
Branch 011 Bit Reset Relative
Branch on Bit ~t Relative
BranC;hOlt Carry Clear
Mnemonic
LOA
LOX
LOY
LSR
,
.,
..
Branc~,q, 9a,{rv:~
"
B~nch on FlesullZ~ro
Test $its in Memor.y with Accumulator
",.
Srancll,pn Result Mihus
~r"r:lPl) OIl'Rilauiflli» Zer,a·. ·
Br~h'on Result 'Plus
Foroesl'e8J<'
.
Branch on Overflow' Clear·
~ranch, on Overf(ow\~t '
;,,'
I
"
.,
CLC
CLD
CLI
CLV
CMP
CPX
CPY
Clear9l¥ry Flag
CIe~rqeel!TIal Mode
Clear Interrupt Disable
Clear Overflow Flag
Compare Memory and
Compare Memory and
Compare'Memoryand
DEC
DEl<
DEY
Decrement Memory by, One
Decrement Index X'by One. ..
Decrement Index Y,'by One
EOR
"ExclUSive-Of' Memory with Accumulator
INC
INX
INY
Increme.nt Memory by One
Increment Index X by One
Increment Index Y by One
JMP
JSR
Jump to New Location
Jump to New Location Saving Return Address
"',
Bit
'MUL
'.
3-28
Muttiply
NOP
No Operation
ORA
"OR" Memory with Accumulator
PHA
PHP
'PHX
'PHY
PLA
PLP
'PLX
'PLY
Push Accumu.ator or Stack
Push Processor Status.on Slack
Push Index X
Push Index Y
Pull Accumulator from Stack
Pull Processor Status from Stack
Pull Index X
Pull Index Y
'RMB
ROL
RTI
RTS
Reset Memory Bit
Rotate One Bit Left (Memory or Accumulator)
Rotate One Bit Right (Memory or Accumulator)
Return from Interrupt
Return from Subroutine
SBC
SEC
SED
SEI
'SMB
STA
STX
STY
Subtract Memory from Accumulator with Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
TAX
TAY
TSX
TXA
TXS
TYA
Transfer Accumulator to Index X
Transfer Accumulator to Index Y
Transfer Stack Pointer to Index X
Transfer Index X to Accumulator
Transfer Index X to Stack Register
Transfer Index Y to Accumulator
ROFt
Accumulator
Index X
Index Y
Description
Loa9 Accumulator with Memory
Lc;>ad Index X wHh Memory
Load Index Y wHh Memory
SriffOne Bit Right (Memory or Accumulator)
".
,.
-
ADC
A+M+C-A
(4) (1)
AND
A M-coA
111
ASl
C-
BeC
Z~
A
Bfanch on N = 1 (2)
BPl
BRA
SRK
BVe
Branch cm-N-_ 12)
Branch Nw.,. (1)
Break
Branch on V -. (21
BVS
Branch on V 1 (2)
CLD
Cil
.If~D
'~I
CLV
8'-'1
Y
AT!
RTS
sse
SEC
80
58
B8
cTITolTlcs
, ,
I_V
--'
M·'~M
)(.1_)(
45
E_
lA·
,
_ ,,
,
, --
Y·l-Y
Jump 10 New loc
Jump Sub
(1)
(1)
-(1)
'
AS
AS
....
_-~-C
No OperallOl'l
A.Y-A'5-ll Y 7.0
A'IM-A (1)
-Z
I 3 12
,
I
,
,
5
1 2 -I 051
4
I
2
100 I
4
I
1 3 I 09 I 4 13
N
,.
;
;
•
l
l
l
·D61612rDE~713
CA
..
5
2
2
2
2
i
2
2
1
,
1
E8
2
CO
,
"
6
A'
_
2
••
2
51
5
2
8,
5
,
I
EA
2
..
..,.
8S
Z
Z
Z
l
l
Z
rlll·-I-I'1 I I I II
,
; ;1;1;1=+1:1 11
1
C
C
C
-l
~~I;IJ 1591413
F_
2
l
Z
l
·1
I.
l
C
02
_'12
A-Ms S 1-5
P-Ms S f-5
li:-----Ms S l-S
Y-Ms S l-S
5-1-5 Ms--A
5·1-5 M$-P
5·1-5 Ms-X
I' 1,0 I .1 'I
SS
I 3 1'1
I -I I
48
08
10 '-1_11.61211115121151,41211014131191413
3 11
,
68
28
SA
FA
Ms-.Y
~
~
Rim Sub
!~ 1: I-;T:: 1; I-~ 1!~'I ~ I~ .
a-12121ED14131 Es131.2
A":M e-.A {I} (5)
.'1',
,
,
4 _ 1
4 1
, ..... C
1-0
38
F8
78
(Restored)
N
.071" 171 27
Ell 6121 Fl1 512
F51 41 2 I FO 1 41
31
F9t
4I3
N V
I
1'1'
2
1
2
1
80.1'.1 '18S
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9514121901-5131991513
96 j 4 12
8£4386
V_M
94J 41 2
8C4-384
SA
2
,A 2/'
..
Notes:
1. Add -1 to N jf page boundary is crossed
2. Add 1 to N jf branch occurs
same PaQe
Add 2to N if branch occurs to-different page
3. Carry .not (C) = Borrow
4. If in decimal mode Z flag is invalid
accumulalor must be checked on zero result.
to
5. Effects 8-bit data field of the specified-'zero page address.
2
6 c
z
ien
m
n
en oen
c: i:
3: (I)"
3!: o
- Z
. z
z
z
1F7
'0
C
C
""I
, l>
z ~C
i:
~.
n
o
3
"0
C
S'
~1~1:
.A 2
r-
A-V
x
&-x
X-A
X-S
Y_A
•
I 37 147 I 57 1 67 1 77
(ReslO~ed:
87
St..e("fJ-711 I--Mo.(5)
5T"
A-M
stx
X-M
.
N ••••
;:I:I~I~~
.....
1-.T
N
I·
ii
CJ'I
o
rg
~
:lJ
c:
o
.....
-71
0' ,
Sfl
TAX
TA,
TSX
TxA
TxS
TVA
~
....
•
~ I; I;
cll_,61 2 I 011
SED
STY
o
B 0 I Z C
00 I 7 11
EjJ22EC43E4
qf 2 2 CC ." 3 C4
CE63C6
RM8I#Uf-nl jI-M" (5)
ROL
,RO"
DS
'S
'·J'I'
,
5-1-5
t
~-I:
(2)
.wM-->A III
M-A
M---o"X
M-Y
1
3/l
De
A M
0
2
16j61211E 17_13
_-c
X M
Y M
M '~M
, N- V
.. 3
2C\4t3\241312
&linch on Z - _
CP)(
Cpy
DEC
DEX
DEY
EOA
5
~
M
CMP
OAA
PHA
PHP
PHX
PHY
PLA
PLP
PLX
PLY
,AJ 2 11
~I:
4
17 •
FS
BIT
MUL
~~ 1-_: 1~ I ~: 1; 1~ 1~ I
1 (2)
8MI
I"A
NOP
IZ.PAGE,XI
Bi'anch on C=, 12)
Branch on C= 1 (2)
INC
,.,V
.as,x I ABS,-y IAEUnVEIINDtAECTlz.PAGE,Y BfT,ADDftESSfNG-(QP BY BIT ")
"rOPlnl#lOPlnIIIOPI-nl"-I,OP\ nflrOP\ nllllOPlnl# IOPln 1"IOPlnIIlIOPl nl"IOPI nlll • I 1 1 2 1 3- '- of I 5 1 6 , 7
S
Branch on
INX
INY
JMP
JSA
LDA
LOX
LOY
I
IfIIPLIED '-fIND.X)
(5)
(5)
BCS
eLe
Cf'
BranchonM,.~1
,,
29
BEa
SNE
N
<0
..
r.r::=D 4
~#I8'-7J1 BranchonM.,=O
BBS(#(lI-7))
I
~TEI~tn:EfZE~~~:-ACCUII.
m
o
PROCESSOR STATUS
CODES
ADDRESSING MODE
OPEJIAlION
,
LEGEND
X
= Index X
= Index Y
Y
= Accumulator
A
M == i Memory per_ effective address
M. =" Memory pe(stack pointer
Mb = selectsr zero page memory bit
M7 = Memory Bit 7
m
. !:t
=:
(I):
a
"0
""I
0:
n
CD
I
R65COO/21. R65C29
Dual CMOS Microcomputer/Microprocessor
INSTRUCTION SET OPERATION CODE MATRIX
The following matrix shows the op codes associated with the
R65COO/21 and R65C29 CPUs. The matrix identifies the
hexadecimal code, the mnemonic code, the addressing mode,
o
LSD 0
the' number of instruction bytes, and the number of machine
cycles associated with each op code. Also, refer to the instruction set summary for additional information on these op codes.
S
6
9
A
ORA
zp
2 3
ASL
ZP
2 S
RMBO
ZP
2 S
PHP
Implied
1 3
ORA
IMM
2 2
ASL
Accum
2
ORA
ZP.
2 4
ASL
ZP.
2 6
RMB,
ZP
2 5
CLC
Implied
1 2
ORA
ABS.Y
3 4'
AND
ZP
2 3
ROL
ZP
2 5
RMB2
ZP
2 5
PLP
Implied
1 4
AND
IMM
2 2
BMI
AND
Relative (IND. Y)
2 S'
2 2"
AND
Zp.X
2 4
ROL
ZP. X
2 6
RMB3
ZP
2 5
SEC
Implied
2
AND
ABS.Y
3 4'
RTI
EOR
Implied (IND. X)
1 6
2 6
EOR
ZP
2 3
LSR
ZP
2 5
RMB4
ZP
2 5
PHA
Implied
1 3
EOR
IMM
BVC
EOR
Relative (IND). Y
2 2"
2 5'
EOR
ZP. X
24
LSR
Zp.X
2 6
RMBS
ZP
2 S
eLi
Implied
1 2
EOR
ABS.Y
3 4'
PHY
Implied
RTS
ADC
Implied (IND. X)
1 6
2 6
AOC
ZP
RMB6
ZP
2 5
PLA
Implied
1 4
ADC
IMM
2 2
RDR
Accum
2 3
ROR
ZP
2 5
ADC
ZP.X
2 4
RDR
Zp.X
2 6
RMB7
ZP
2 5
SEI
Implied
AOC
ABS.Y
PLY
Implied
STA
ZP
5MBO
ZP
2 3
STX
ZP
2 3
DEY
Implied
1 2
STX
ZP. Y
2 4
5MB'
ZP
2 4
STA
ZP. X
2 4
LOY
ZP
2 3
LOA
ZP
2 3
LOX
ZP
2 3
LOY.
ZP. X
2 4
LOA
ZP.X
2 4
CPY
ZP
2 3
3
4
B
o
E
ORA
ABS
3 4
ASL
ABS
3 6
C
(/)
::;;
ORA
BRK
Implied (IND. X)
1 7
2 6
MUL
Implied
10
,
BPL
ORA
Relative (IND). Y
2 5'
2 2"
x
JSR
AND
Absolute (IND. X)
2 6
3 6
BIT
ZP
2 3
BVS
ADC
Relative (IND. Y)
2 2"
2 5'
A
B
C
o
E
F
STA
BRA
Relative (IND. X)
2 6
2 3'
STY
ZP
2 3
STA
BCC
Relative (IND. Y)
2"
2 6
2
STY
ZP. X
LOY
IMM
2 2
LOA
(IND. X)
2 6
LOX
IMM
2 2
BCS
LOA
Relative (IND). Y
2 2"
2 5'
CPY
IMM
2 2
CMP
(IND. X)
2 6
BNE
CMP
Relative (IND). y
2 2"
2 5'
CPX
IMM
2 2
SBC
(lND;X)
2 6
CPX
ZP
2 3
BEQ
SBC
Relative (IND), Y
2 2"
2 5'
o
3
BRK
Implied
1 7
2 5
,
,
2
2
2
3 4'
ORA
ASL
ABS.X .ABS.X
3 4'
3 7
ROL
Accum
1 2
,
1 2
,
TXA
Implied
,
2
LOA
IMM
2 2
TAX
Implied
LOX
ZP. Y
2 4
5MB3
ZP
2 5
CLV
Implied
LOA
ABS. Y
3 4'
TSX
Implied
2
'CMP
ZP
2 3
DEC
ZP
2 5
5MB4
ZP
INY
Implied
CMP
IMM
.2 2
DEX
Implied
CMP
ZP. X
2 4
DEC
Zp.X
2 6
5MBS
ZP
2 5
CLD
Implied
2
CMP
ABS,Y
3 4'
PHX
Implied
3
SBC
ZP
2 3
INC
ZP
2 5
5MB6
ZP
2 5
INX
Implied
1 2
SBC
IMM
2 2
NOP
Implied
2
sse
ZP. X
2 4
INC
ZP. X
2 6
5MB7
ZP
SED
Implied
SBC
ABS. Y
3 4'
PLX
Implied
4
5
6
9
A
4
-OP Code
-Addressing Mode
~Instruction Bytes; Machine Cycles
2 5
2
5
D
,
,
2
2
,
,
8
2
3 5
-New Opcode
3-30
,
3
EOR
ABS
3 4
LSR
ABS
3 6
3
3 4'
RDR
ABS.X
3 7
ABS
STA
ABS
STX
ABS
3 4
3 4
3 4
2
LOY
ABS
3 4
2
LOA
ABS
3 4
LOY
LOA
ABS. X ABS.X
3 4'
3 4'
CPY
ABS
3 4
2
,
CPX
ABS
3 4
,
,
BBR3
ZP
5"
3
BBR4
ZP
5"
BBR6
ZP
3 5"
BBR7
ZP
3
5"
BBSO
ZP
3 5"
BBS'
ZP
3 5"
LOX
ABS
34
BBS2
ZP
3 5"
3
CMP
ABS
3 4
DEC
ABS
3 6
3
BBS3
ZP
CMP
ASS. X
3 4'
A
B
5"
BBS4
ZP
5"
C
DEC
ABS.X
3 7
BBSS
ZP
3 5"
o
SBC
ABS
3 4
INC
ABS
3 6
BBSS
ZP
3 5"
E
sse
INC
ABS.X
3 7
BBS7
ZP
5"
F
4'
3
C
2
LOX
ABS.Y
3 4'
ABS. X
B
BBR2
ZP
3 5"
LSR
.BBRS
ABS.X
ZP
3 7
3 5"
STA
ABS.X
3 5
,
,
ROL
ABS.X
3 7
ADC
ABS.X
TXS
Implied
,
AND
ABS.X
3 4'
RDR
ABS
3 6
STY
BBR1
ZP
3 5"
ROL
ABS
3 6
ADC
ABS
3 4
4
TAY
Implied
2
JMP
Indirect
3 5
BBRO
ZP
3 5"
AND
ABS
3 4
EOR
ABS,'X
3 4'
3
5MB2
ZP
2 5
,
JMP
ABS
3 3
,
STA
ABS.Y
2 5
BiT
ABS
3 4
LSR
Accum
2
TYA
Implied
1 2
o
o
x
,
o
E
3
F
'Add 1 to N if page boundary is crossed.
"Add 1 to N if branch occurs to same page;
Add 2to N if branch occurs to different page.
'1"\.1'\1':.""-,,
"~, '.1 ,\ \ ' ,
,.. ,\"·c'V,,
•
~
•
, :. '.~
~f
••
',.
[)uaICMOSMicrocomput.JMiCrdprQc~
,
. ".
. . . . ,'"
. ' . '.
.'. ,6.. ' '"'
110 PORT WAVE~ORMS-ALLPOFtrS
POFiTINPUT
PO,," OUTPUT
I/O PORT TIMIN~-ALL PO,RTS
Parameter
2MHz
4 MHz
Min
Max
SynIbol
Min
Max
35
-,
10
25
-
-
100
"
.
input Oata'Setup)lme
T ps
Input DatI! Hold Time (Port 0)
T pH
Input Data Hold Time
" (All Pdrlll except D)
,
,
25
0
-
0
Output Data Delay Time
50
10
Tpc
3·31
0
,120
0'
0'
R65~OO/21. Fl65C29
Dual CMOS Microcomputer/Microprocessor
EXPANSION BUS TIMING
vcc --,. .50V
" +-
100/.0, TA·= O·G to 70·G
"
2 MHz'
Symbol
Parameter
. RWDeiay Time
PE Address Delay Time
J"'I:J Ad.dressDelay Time
PD Address Hold Time-Read
Dala Delay Time Write
, Data Hold Time Write
wata setup ime Read
ata Hold Time Read
EMS Delav Time Address Valid to EMS Low
EM"""S Delay Time 02 to EMS Low
EMS Hold Time
(42 vycJe Time
pulse Width 02 Low
Pulse Width 02 High
fJA Delay Time -fJ2 to fJA
T RWO
T'ED
T AOO
TADH
. Toow
TbHW
TosR
TOHR
TEMA
T EMC
TEMH
Tcyc
T FWL
TFWH
T2AD
4MH~'
..•.....
..
M!n
Max
. Min
Max
Unit
20
20
20
0
100
100
120
80
120
10
80
80
100'
60
100
ns
ns
ns
ns
ns
20
50
10
10
10
10
0
ns
20
35
10
10
-
ns
150
10
500
235
235
0
ns.
ns
-
ns
ns
ns
ns
ns
ns
·115
...
10
250
115
115
0
265
265
60
135
135
50
Note:
• 162 Frequency
EXPANSION BUS WAVE FORMS
TPWL
-
-
~
TPWH-
\
J-T2AD
TCYC
,
TRWDr--
I - - - TEMC ..=::::j
TEMA-
EMS
.
J
X
PE
I--
'k---
1--
TEMH-
I
'0
"
ADDRH
ADDR H
TAED-l
PO
ADDR L
-TADD-
ADDR L
DATA
--1
-TDDW-
TDHW
READ CYCLE
3-32
r-
TDSRITADH-
WRITE CYCLE
DATA
-
TDHR-
r---
R65COO/21. R65C29 '
Dual CMOS Microcomputer/Microproce$sor
MAXIMUM RATINGS*
..
Parameter
Symbol
Value
Unit
Vee
-0.3 to + 7.0
Vdc
Vdc
Supply Voltage
Input Voltage
V'N
-0.3 to
Operating Temperature
TA
o to
Storage Temperature
TSTG
Vee
+0.3
+70
• NOTE: This device contains circuitry to protect the inputs
against damage due to high static voltages, however,it is
advised that normal precautions be taken to avoid application
of any voltage higher than maximum rated VOltages to this circuit.
·C
-55 to + 150
·C
DC CHARACTERISTICS
Vee = +5.0V ± 10%, TA = O·C to 70·C (unless otherwise specified)
:>"
Parameter
Min
Symbol
Input High Voltage
V,H
+2.0
-
Input Low Voltage
V,L
Output High Voltage
VOH
Input Leakage Current
liN
-
Output Low Voltage
VOL
Output Low Current
(All ports except Port G)
Max
+0.8
-
Unit
Test Condition
V
V
V
Vee"" 4.5V
ILOAD = -100fLA
±10
fLA
V,N = OVor Vee
Vee = OV
-
+0.4
V
Vee = 4.5V
ILOAD = 1.6 rnA
lOUT
-
-1.6
rnA
VOL
= O.4V
Input Capacitance
(XTALO, XTALI)
(All Others)
C'N
25
5
pF
pF
Vee
= 5V
Output Capacitance
COUT
-
10
pF
Operating Frequency
Crystal or Master Clock
02 Clock
-
.02
.01
8.0
4.0
MHz
MHz
Power Dissipation
Po
-
40
rnW
+2.4
-
Note: Negative sign indicates outward current flow, positive sign indicates inward current flow.
3-33
1= 2 MHz
TA
= 25·C
Vee = SV
f = 2 MHz
TA = 2S·C
II
Dual CMOS Microcomputer/Microprocessor
R65COO/21. R65.C29
PACKAGE DIMENSIONS
64 PIN PLASTIC QUIP (QUAD IN·LINE PACKAGE)
F~~ ~G~~Gr-
T
,nn n
DIM
Jnlin nn n "Illn nil nn n~n~'"nnn.n nn
A
B
41.15
17.02
64
C
3.05
0.38
33
D
F
G
H
J
B
~J1
I
32
~u ~u~
T U· U"~"UUU"ll" UUUUUUU" U"H
K
L
I~··
-~H
MILLIMETERS
MIN
MAX
.
A.
-i~D
M
'I~
+T IT
!
41.66
17.53
4.57
MAX
1.620
0:670
1.640
0.51
0.120
0.024
2.54 BSC
1.02
1.14
0.040
1.27
V9
18.92
23.37
TI
7'
4,32
19.81
23.62
0.690
0.180
0.020
0.050 BSC
esc
1·1-~-jJlJ
3·34
INCHES.
MIN
0.100
0.t10
0.745
0.920 .
esc
0.045
7'
0.170
0.755
0.930
RS5F11 • R65F·12
.
'1'
Rockwell
"J~'
(
C
,.
R65F11 AND R65F12
FORTH BASED MICROCOMPUTERS
seCTION 1
INTRODUCTION,
1.1 FEATURES
• Flexible clock circuitry
-2-MHz or 1-MHz internal operation
-Internal clock with external XTAL at two times internal
frequency
-External clock input divided by one or two
• FORTH kernel In ROM
• Enhanced 6502 CPU
-Four new bit manipulation instructions:
Set Memory Bit (SMB)
Reset Memory Bit (RMB)
Branch on Bit Set (BBS)
Branch on Bit ,Reset (BBR)
-Decimal and binary arithmetic modes
-13 addressing modes
-True ind!!xing
• 1 /LS minimum instruction execution time @ 2 MHz
• NMOS silicon gate, depletion load technology
• Single +5V power supply
• 12 mW standby 'power for 32 bytes of the 192-byte RAM
• 4O-pin DIP (R65F11)
• 64-pin QUIP (R65F12) has three' additional a-bit 1/0 ports to
provide a total of 40 110 lines.
• 192-byte static RAM
• 16 bidirectional, TTL-i:ompatible 1/0 lines (two ports, R65F11)
or 40 bidirectional, TTL-i:ompatible 1/0 lines (five ports,
R65F12)
• One a-bit port with programmable latched input
• Two l6-bit programmable counterltimers, with latches
-Pulse width measurement
-Asymmetrical pulse generation
-Pulse generation
-Interval timer
-Event co.l,Jnter
-Retriggerable interval timer
1.2 SUMMARY
The Rock'l./ell R65F11 and R65F12 are complete, high-perfor'
mance. a-bit NMOS single chip microcomputers, and are compatible with all members of the R65CO family.
The kernel of the high lev!!1 Rockwell Single Chip RSC-FORTH
language iscontained in thepreprogrammed ROM oHhe R65F11
and R65F12. RSC.FORTH is based on the popular fig-FORTH
model with extensions. All of the run time functions of RSCFORTH are contained in the ROM, including 16- and 32-bit
mathematical, lOgical arid Stack manipulation, plus memory and
input/output operators. The RSC-FORTH Operating'System
allows an external user program written in RSC-FORTH or
Assembly Language lobe executed from external EPROM,or
development of such program under the control of the R65FRI
RSC-FORTH Development ROM. Other development ROM's
can also be accomm6dated.
• Serial port
-Full-duplex asynchronous operation mode
-Selectable 5· 10 a-bit characters
-Wake-up feature
-SynchronouS shift register mode
-Standard programmable bit rates, programmable up to
62.5K bits/sec
a
• Ten interrupts
-Four edge-sensitive lines; two positive, two negative
-Reset
-Non-maskable
-Two counter
-Serial d.ata received
-Serial data transmitted
• Expandable to 16K bytes of external memory
The R65F11 and R65F12 consist of an enhanced 6502 CPU,
an internal ckx;k OSCillator, 192 bytes of Random Access Merilory
(RAM) and versatile interface circuitry. The interface Circuitry
includes two 16~bitJ)rogrammable timer/counters, 16 bidirectional input/oUtpUt lines (including four edge-sensitive lines and
input latching on one a-bit port), a full-duplex serial 1/0 channel,
ten interrupts and bus expandability.
The innovative architecture and the demonstrated high performanceof the R6502 CPU, as well as instruction Simplicity,
results in system cost-effectiveness and a wide range of
Document No. 29651N49
3-35
Product Description Order No. ,2146
Rev. 2, March 1984
FORTH
R65'11.R65F12
Ba~d
Microcomputers
computational power. These features in combination with the
FORTH high level operating system make the R65Fll and
R65F12 ideal for microcomputer applications.
(Order Number 201). A de~crip!i.ol')of.the instruction capabilit\3s
of the R6502 CPU is contained-ln"ti;le R6S00 Microcomputer
System Programming Manual (Order Number 202).
For systems reqUiring additionalI/O ports, the 64-pin QUIP
version, the R65F12, provides three additional 8-bit ports.
1.3 ORDERING INFORMATioN
Pert No,
A complete RSC-FORTH development system can becreated with three MOS .parts: the R65Fll, one RAM chip and
theR6SFRl Development ROM.
R65FllP
R65FllAP
R65F120
R65Fl2AO
R65FRIP
R65FR2P
R65FK2P
This product description is for the reader familiar with the
R6502 CPU hardware and programming capabilities. A
detailed description of the R6S02 CPU hardware. is included
in the R6500 Microcompuler System Hardware Manual
R65FR3P
R65FK3P
qefjf;rlptlo!'l •
40-Pin FORTtiBased Microcomputer at 1 MHz
40-Pin FORTH Based Microcomputer at 2 MHz
64-Pin FORTH Based Microcomputer at 1 MHz
64-Pin FORTH Based Microcomputer at 2 MHz
FORTH Development ROM for R65Fll or R65F12
FORTH Oevelopment ROM for expanded capacity
FORTH Kernel ROM for expanded capacity
development
FORTH Development ROM forR65010
FORTH Kernel ROM for R65010
Order No.
2148
Description
FORTH Based Microcomputer User's Manual'
Note:
'Included with R65FRI.
3-36
R65F11 • R85F12,
FORTH Based'M'icrocomputers
SECTION 2
INTERFACE REQUIREMENTS
This section describElS the interface requirements for the
R65F11 and R65F12 single chip microcomputers. Figure
2-1 is the Interface Diagram for the R65F11 and R65F12,
Figure 2-2 shows the pin out. configuration and Table 2-1
describes the function of each pin of the R65F11 and R65F12.
Figure 3-1 is a detailed blOck diagram.
Table 2-1.
Signal
Name
Vss
XTLI
R65F11 and R65F12 Pin Descriptions
Pin No.
Pin No.
R65F11
R65F12
21
50
39
12
11
Signal and. power ground (OV)
2
10
ClYstal or clock input for intemal clock oscillator. Also
allows input of XI clock signal if XTlO is connected to
Vss. or X2 or X4 clOck H
XTlO is fIoaled.
9
Crystal output from internal
clock oscillator.
41
The Reset input is used to
initialize the R65Fll. This
signal must nol transition from
ecoc'
PM-PAY tPAO. PAl.
POSITIVE PIl2. PA3
D~PMl
XTLO
flNPVT O,t,TA STR08EJ"
20
,f,O.A3,AIii!.
PIW. A13.lDr (PCO-PC7}
Separate power pin for RAM.
In lhe elllint thaI Vcc power
is lost, this power retains
. RAM data.
40
OSCU.AT()A
NEGATIVE EOGE DETECTS)
DeSllrtptlon
Main poWer s,!pply +5V
"'"All AOM'DI).07 DATA IIU$
IaN to high for at least eighl
cycles after V cc reaches operating range and the internal oscillator has' stabilized.
(PDO-P07)
CONTAOl
REGISTERS
3
13
Clock signal output al inter-
22
51
A negative going edge on the
nal lrequency.
........,
Noli-Masklll* Ir)lerrupt signal requests that a non-
m8$kable Interrupt be
get:I-
ersted within the CPO.
PAO-PA7
P8(),PB7
30-23
38-31
57-64
1-8
PCO-PC7
4-11
25-32
Two 8-bit portS used for either
input/output. Each line of
Ports A and B Consist of an
active transistor to Vss and
a
Figure 2-1. R65F11 and R65F12 Interface Diagram
AO-A3
A12,
PIN
PEo-PE7
PFo-PF7
PGo-PG7
sifItors. Ports C and 0 .lines
form.the external multiplexed
address and data bu8 to allow ,external memory ad-
19-12
dRisSing.
42-49
24-17
14-16,
52-56
On the R65FI2, Port E may
be used for output only. Ports
F and G, are similar to Ports
A and B in construction and
may be ueed for Inputs, or
outputs.
3-37
puM-tlp to Vcc.
pull-up and pull-down tran-
M3, EMS
POO-PO"
A4-A11
00-07
~ive
Port C has an active pull-tlp
transistor. Port 0 has active
II
R65F11. R65F12
FORTH Based Microcomputers
DOT OR NOTCH
TO-LOCATE
,
PIN NO. 1
T!
Int.l1ace Diagram
y"
PBO
P",
(D.25MM)
L
.;
(48.51 MM)
.(48:00MMj
2.050 "'AX
151.30"'''')
111 EQUAL SPACES
D.100'Ci TOl HONeUM.
PM
(2.54""'1
tr
,
--1
L
·-1 "......, 1-.0· ,.
TYP.
O.SOONAX
R65F11 PinOut Designation
r--:--"\.o
40 PIN DIP
R65F11 Dimensional Outline
Plr
P86
PBS
P84
P83
PAD
PA'
PA2
PA3
P......
PBZ
PAS
PIIt
P80
PA&
PA7
XTO
XT1
PG'
'P03
ViS
V~N
P02
.,
PC'
PGO
~5
~
PG6
PG7
Vee
P£O
PF7
~.
Pf5
PF.
Pf3
PF2.
PF1
PFo
:I
A.3
PEt
P£2
PEl
PU
PES
PEe
PE7
~
is
AtDa
=-
==
~ -""'-''-----=:Il
R65F12 Pin Out Designation
R65F12 Dimensional Outline
,COigure 2·2.
Pin Out Configuration
3·38
1.no
(U5MM) 0.065
(D.H "'MI
(1.ol-lIM) 0.040
(0.'5I1MI 0,01'
O.D2Z
R65F11 • R65F12
FORTHBa~d Micr()computers
,,'
SECTION 3
SYSTEM ARCHITECTURE
I
The stack can be envisioned as a deck of cards which may
only be accessed from the top. The address of a memory
location is stored (or "pushed") onto the stack. Each time
data are 10 be pushed onto the stack, the Stack Pointer is
placed on the Address Bus. data are written into the memory
location addressed by the Stack Pointer, and the Stack
Pointer is decremented by I. Each time data are read (or
"puffed") from the stack,' the Stack Pointer is incremented by
I. The Stack Poinferis then placed on the Address Bus, and
data are read from Ihe memory Jocation addressed by the
Pointer.
This section provides a functional description of the R65FII
and R65F12. Functionally the R65Fll consists of a CPU.
RAM memory. two a-bit parallel VO ports (five in the 64-pin
R65F12). a serialVO port. dual counter/latch circuits, a mode
control register, an interrupt flag/enable dual register circuit.
and an internal Operating System. The kernel of FORTH in
ROM complements the system hardware. A blockdisgram
of the system is shown in Figure 3-1.
NOTE
Throughout this document. unless sp8cified
otherwise. all memory or register address locations are specified in hexadecimal notatiOn.
The stack is located on zero page, i.e., memory locations
OOFF-004O. After reset. which leaves the Stack Pointer
indeterminate, normal usage caffs for itS initialization at OOFF.
3.1 CPU LOGIC
3.1.4 Processor Status Register
The R65Fli internal CPU is a standard 6502 configuration
with an a-bit Accumulator register, two B-bit Index Registers
(X and V); an a-bit Stack Pointer register. and ALU. a l6-bit
Program Counter. and standard instruction regiliter/decode
and internal timing control IQglc.
The 8-bitProcessor Status Register contains seven status
flags. Some of these flags are controlled by the user program; others may be controlled both by the user's program
and the Cpu. The R6S00 instruction set contains a number
of conditional branch instructions which are designed to allow
testing of these ,flags. See Appendix B for details.
3.1.1 Accumulator
3.1.5 Program COunter
The accumulator is a general purpose a·bit register that
stores the results of most arithmetic and logic operations. In
addition. the accumulator usually.'contains orie of the" two
data words used in these operations,
The 16-bit Program Counter provides the addresses that are
used to step the processor through sequential instructions
in a program. Each tim~ the processor fetches an instruction
from program memory;, the lower (least significant) byte of
the Program Counter (PCl) is placed on the low-order bits
of the Address Bus'and lhe higher (most Significant) byte of
the Program Counter (PCH) is placed on the high-order a
bits of the Address Bus. The Counter is incremented each
time an instruction or data is hitched from program memory.
3.1.2 Index Registers
There are two a-bit index registers. X Elcnd V. Each i,ndex register can be used as a base to m~ify the address data program counter and thus obtain a new address-the sum of
the program counter contents and the index register contents.
3.1.6 Arithmetic And Logic UnH (ALU)
When executing an instruction which specifies indirect
addressing. the CPU fetches the op code and the address.
and modifies the address from m~mory by addinQ the index
register to it prior to loading or storing the,value of memory.
Each bit of the ALU has two inplI,ts. These inputs can be tied
to variousintemal buses Qr- to, !llogic zero; the ALU then
generates the functiQn (AND, OR, SUM, and so on) using
the data on the two inputs.
Indexing greatly simplifies many types of programs, especlaffy those using data tables.
3.1.7 Instruction
3.1.3 Stack Pointer
R~lster
and Instruction Decode
Instructions are fetched from ROM or RAM and gated onto
the Internal Data Bu$. These instructions are latched into the
Instruction Register then decoded along with timing and
interrupt signals to generate COntrol signals for the various
registers.
The Stack Pointer is an a-bit regillijilr. It is automatICally
incremented and' decremented ul"1der control of the micrOprocessor to perform siack manipulation in response to eitlier
user instructions. an intamal IRQ interrupt. or the external
interrupt line NMI. The Stack, POinter mu~ be" initialized by
the user program.
'
The stack affows simple implementation of multiple I~ef
,interrupts. subroutine nesting and simplification of many types
,of data manipulation. T!le JSR. BRK. RTI and 'ATS'instructions use the stack and Stack Pointer.
3-39
II
<,
t
o
.....
......~ '
r:-l r:I
L:::....J L.:::....J
,_PC>~', _ij
~
PA$-PAI
[EJ
t
CaIPA5"1
t
CA'''''",
5O(1'A&)
1
SI(~ll
I1
A••
o"11
:!IX
.
m
I
ie.
,,,.0'
Figure 3-1. DetaIIed.JHOCk 01198...,
o
l)
o
3
'a
i
;;
R6Sf11 • .,85F12
3.1;8,TlmlngCOnttOl
For ttiEI RAM to ratalntlalaupor'rlQes of,Vc c• VRR'must be
supplied .withln Operating l'iinge."d.~ mustbEl.c;lriven low
atleast~t~c'ac:k pulse~
Vcc:tallsQut Of'oper;!ihg
range. RESmuslllienbe hilldl~;Whlte Vecisout of
ating range and until. at .feast ei9ht_2 cJQek cycles afte(V cit;
is again within operating range and the intetnal ~ oscUlator
is stabilized. V RR must remain within Vce 'ope(atingran'~~
during normal operation. When V cc is out Of operaMgrange;
VRR must remain withintbeVRR retentiOn 'range.lnordeito
retain data. Figure 3-2 shOws typical. waveforms.
T~ Timin,g Col)trollogjp keeps trac~pfthe specific instruc-
be'f9,
.1191l. cycle belhg 8X8,C:IlIe,d. This logic: is seUor'O each time
. al) instniQtion fetch,. is execul~ ~.nd is e.dv,"!1cedatt/le
bitginl)ingofa~ch.-PhfS8' O~a,clock pulsltfor as,Q;1any.cycles
as are requi..a to CClP\pIe.' the instr\lCliol). each data -transfer
which takes place between the registers is caused. by
decoding. the. contents of both the. instruction register and
timing cOntrol unit. '.,
'
oper-
3.1.9 Interrupt LOgIc
RAM OPERATING MODE
, lntellupt logic: c~)I)trola the sequencing of three interrupts;
RES. NMi and IRQ. IRq is generated by anyone of eight
conditions: 2 Counier Overflows. 2~ositive Edge' 'Detects.
2 NegativeEdg4il De*t$, and 2 Serial Port Comlitions.
!
'J'
I. ' •.
. '~I'
RES
.. "
. .
The machine code instruction set of the R65F11 and R65F12
microcomputers areb~d on the popular R6500 microprocessor set They contain all the instructions'in the standard
R6502 set, with the addition of the four new bit instrucliQns
added to the R6511 processor family, Refer to Appendix A
for the Op Code mnemonics addres,Singmatrix for details on
these instruqlions.
3.~
;.!. r.'~~.>~~~~~-A~ '.
::1]°.;
3.2 CPU INSTRUCTION SET
RAM RETEN'rIQN,MODE
~0
~~
·0··.·········'
. ···.
' '
r
TRL0-l I-
1 INITIAL APPL.ICATIOI\!. OF VccAND VliR'
2 LOSS OF Vee. RAM ON STANDBY POWER.
3 REAPPLICATION OF Vcc~
4 >8'2 CLOCK PULSES. AFTER OSCILLATOR STABIUZATIOIII.
5 >8'2 CLOCK PULS",S.
.
...
Figure 3..2. Data Retention Timing
READ;'()NLY-ME.MORY,.(ROMf
.'
.
!
..
3.5 Ct.:OCK OSC.'LLATOR
The ROM consists of preprogramrned memory w~h an
address spacefTom F400 to'FFFF. It contains the rui! time
kEirnelof theffigh level language . RooI<\yell Single Chip
FORTH. There are 133 included functions stote/jiri the
ROM. COdes are in thElformat'OfatwO'byte code field, which
identifies the interpre(er al3sigt1ed to 'exequte that wora, folrowed by a variable length parameter,Field. w~~rcoritains
the instructions aod elata used by t"aUnterpret~,raccording
to the ,programmed intention of that definition. $1,1' flppendix
o for a qamplete list-of the'names .of allinC'luded words, All
. wOrds n~d~ for suppon of the run time operation of dedicated applicationsprograms'are included: Th&.RSC'FORTH
Operating System is also. part of the ROM code' and. is
entered upon Reset. This Operaling System allOW the R65Fl1
ahd R6~F12 to aUlo start a user pr09fam written in either
RSC-FORTH or .Assef,)'1bly ~gua~,orenter .aDevelopmenfROM if one is present. If no auto start program· is found,
an attempt wiff be made to boot. an operating program from
floppY disk,
A reference frequency can. 'be generated with the on-chip
oscillator using an external crystal. The, oscillator refere(lCe
frequency passes throligh an internal <;ountdown network
(diVide by 2) to obtain the internal operating .frequency (see
Figure 3-3a).
Internal timing can als6.be,controlled by driving the ~TLf pin
with an extemalfrequency sourge. Figu,re 3,~b shoW~ tyPical
c?~n$Ctions, Ir XTLO iii! lell floating.
e~ernal Sgyrceis
diVided by the Internal countdown neM~rk. tiOwever, ifXTLO
is tied to Vss, the internal coundown' network is byPassed
causing the. chip to oP!trate at .the frequency of the' .'ltllfll~1
source.
. ,
!he
The· R65Fl1, and R6~Ff2 dperat~ in. the .CLOCK MASTi;FI
mode .. In. this mode afrequencesource (cry~taf or elcternal
source) must be apPji,ed' to'll)e X~LlandXTLQpins.
'
,
,",
r
NOTE: When operalillgat a ;'Mf-:lz"inten1aifrequency place a'
15-22 pI capacitor between Xn.OandGND.'
3.4 RANDOM ACCESS MEMORY (RAM)
The RAM consists of 192 bytes of read/write memory with
~2 is a buffered output sign~IWhich closely approximates the ,
internal timing. When a.common external source is usedta
drive mUltiple devices U1,einternal timin~ betweendeyice~as
well as· their (12 outputs will be skewed in time,. If '~,k~wing
represents a system prqblein. it ean be avoided.by." the
MasterISlave connecti,on ~ndOOPtions ShoY!'1i~~igure3.4.,
an assigned page ZElro ~ddress of 0040 through OOFF. The
,A65Fl1 ahdR65F12 provide a separate power pin (V RR)
"Which may be used for standby power fpr32 bytes located
at 0040-005F. In the event of the losso/Vce power, the
lowest 32 bytes 01 RAM data wili be retained if standby power
is S\lpplied to the V RR pin ~ If the RA/v1 data r,ete'[IIion ill not
required then V RR must be connected to' Vee.' During operation V RR must be at the Vee level.
'
The R65Fll and R65F12i.1iI o~ratedin the CLOCK MASTE,R
MODE. A second processorcolildbe operated in the CLOCK
3-41
FO FlTttBased Microcomputers
R65F11 .R65F12
3.6 MODE CONTROL REGISJ'ER (MCR)
S~VEMODE. Mask "plions in t~ SLAVE unit convert the
jI~. sig~al irto a.,~IOCkIX\put pin which is tightly coupled to the
i~ernel. liming generatqr. As 8, result the internal. timing of.the
MASTER .8l)d SLAV!;: units are ~ynchronized with minimulTI
skew. If the _2 signal to the SLAVE unit is inverted, the
MASTER end SLAVE UNITS WILL OPERATE OUT OF
PHASE.. This apprpacl)" allows the' two devices to share
e'9,erna)l11pmoryu5ing ~ycle stealing techniques.
.~" ,~ ==, OR'"'"
2·4 rlHz 1'\ . '.:
"
',.,
The Mode Control Register containscont;olbits for the mul·
tifunction VO port!? and mode select bits ,for Counter A and
CounterS. Its setting, along with the. setting of the Serlal
Communications Cdhtro,l RegiSter (SCGRI,determines·the
basic configuration of theR65Fllan9 R65F12 in any appli·
catiofl, .The Mode Gonttol Register bit assignment is shown
in Figure' 3~!i. MGR-BItS 7, 6,5 must re'main 1'sin order for
external memory referenping to be enabied.
2X tiNT
IEXT
" •.
.
XTLO
MCR
'Addr 0014
a.C:ry_tal Input
", Vcc
Counter B
Mode sel~t
2-4 MHZ
XTLI
tiNT
1'165Fl1
=
lexT ;:
Bus
1 01'1 2 MHZ
I ' .j
,_~',
ounter A
Mode Select
;:0,-.. 0 Interval Timer
0 - 1 Pulse Ge
.. no.,atlon
1 - 0 ivenl Count.,
1 _ _ ' 1 Pulse Wid~ Me...
0 - , 0' Interv.1
0 _ 11 Asymm!ldric:' Pulse' Gel)ef'ation
1 ._._ 0 Event Counter
1_'_ 1 RetrtgOerabie Interv81'Tlmer
Mode Select
2X liNT
XTLO '
nmer
,Port"B latch
,.... b ~iI-:.!.: En,obled)
VCR
(0 "" Trt smtI H4gh ""~ 1Ioae) not
0 - X Newmlf 1 "I~"·
1-0,Abbr.S1JS _not~.
'~:l'
...30~TLI
liNT
R65Fl1
XTLO
tExT
1_
= '1 OR II MHZ.
=
1iNoW.d.
1 Ilux'CI:-Bu.
liNT
Figure 3.5. M.ode Control Register
Vss-=
b. Clock Inputs
The use of Counter A Mode Select is ,shown in Section 6.1.
The use of Counter B Mode Select is shown in Section 6.2.
Figure 3·3. ClOCk Oscillator Input.Options
The use 01 Port BLatch Enable. is shown in Section 4.4.
R65F11 OR R65F12
XTLI
MASTER
6500/11, ETC.
XTLI
.2
(OUTPUT CLOCK)
INVERTER USED
r-- --, WHEN SLAVE'IS
:
: TO OPERATE
lOUT
- - --..I OF PHASE WITH
MASTER
t
SLAVE
(INPUT CLOCK)
Figure 3·4. MasteriSlave Connections
3·42
FORTH Ba.d Microcomputers
R65Fll.'R65F12
3.7 INTERRUPT FLAG REGI$TER (IFR)
AND 'INTERRUPT ENABLE
REGISTER (IER)
_.0012
An IRQ interwllt ~Ciest can be initiatetl by any or all of eight
possible sources. 'f!;lese sources are all capable of being
enabled or disabled by the use 6f the appropriate interrupt
enabled bHs in the IntEfrrupt Enable Re.2!!ter (IER). Multillie
simultaneousinterruJ31s will cause the IRQ interrupt request
to remain active until all interrullting conditions nave been
serviced and cleared.
IFA
Addr 0011
PMPo.ltl..
E.o.tect
pA1PoaItIVe
E9~
Edg.-
PA2Hepfllle
The ,Interrllpt Flag Register cqntains the information that
indicates which 110 or counterrieetls attention. The contents
of \119 InterruptFIIIQ Register may be examifled at any time
by'rea<;ling at address: 0011. Edge detect IFR bits may be
cleared in low. level code by executing a RMB instruction at
address location 0010. The RMB X. (0010) instruction reads
FF, modifies bit X to a"O",and writes the modified value at
address location 0011. In this way IFR Oits sette) a "1" after
the read cycle of a Read"Modify-Write instruction (such as
RMB) are protected from being cleared, A logic "1" is ignored
when writing to edge detect IFR bits.
'
PA3 ...._
c:au_. . .
u_
EdgeDMeo:t
u
_ _ .....
~,A
A_lv.r
Fl8g
XMTA
Flog
Figure 3-6. Interrupt Enable and Flag Registers
Each IFR bit has a corresponding bit in the Interrupt Enable
Register which can be set to a "1" by writing a "1" in the
respective bit position allocation 0012. Individual IER bits
may be cleared by Writing a "0" in the respective bit position,
or by
If setto a "1", an IRQ will be gel'\erated when the
correspondinglFR bit b$Comes true. The Interrupt Flag Register and Interrupt Enable Registet bit aSSignments are shown
in Figure 3-6 and the functions of each bit are explained in
Table 3-1.
.
REs.
T~ble3-1_ Interrupt Flag Regisler Bit Codes
Bit
Code
Function
IFR 0:
PAO POSitive ,Edge Detect Flag-Set to a "1" when a positive going edge is detected on PAO.
Cleared byRMB, 0 (0010jinstruction or by RES.
IFR 1:
PAl POSitive Edge Detect Flag-Set to a 1 when a positive going edge is detected on PA1.
Cleared bY RMB 1 (0010) instruction, or by RES.
IFR2:
PA2 Negative Edge Detect Flag-Set to a 1 when a negative going edge is detected on PA2.
ciear8d by R,MB 2 (0010) instruction or byRES.
IFR3:
PA3 NeQetive Edge Detect Flag-Set to 1 When a negative going edge is detected on PA3.
.
Cleared by RMB 3 (0010) instructIOn or by RE;S.
IFR4:
Counter A Underflow Flag-Set to a' 1 when Counter A underflow occurs. Cleared by ,..ading
the Lower Counter A at location 0018, by writing to address location oo1A, or by RES.
IFRS:
Counter B UnderflOW Flag-Set to a'1 when COunter B underflow occurs. Cleared by reading
the Lower Counter B at location OO1C, by'writing to address location oo1E, or by RES.
IFR6:
Receiver Interrupt Flag-Set to a 1 when any 01 the Serial Communication Status Register bits
!hrough 3 is set to a 1. Cleared when the Receiver Status bitS (SCSR 0-3) are cleared or by
RES.
IFR7:
Transmitter Interrupt Flag-Set to a 1 when SCSR 6 is set to a l' while SCSR 5 is a 0 or SCSR
7 is set to a 1. Cleared when the Transrriitler Status bits (SCSR 6,& 7) are cleared or by RES.
o
343
3
FORTH. BaSed. ,-,icrocomputers
R65F11. R65F12
3.8 OPERATING SYSTEM
Whether a -warm,or .cOld re.set, the' memory. map is then
searched at every ~.K.byte boundary starting at location 0400
Hex. The first two bytes ate.&ch boundary are checked
against an A55A Hex bit' pattern. This pattern indicates that
an, auto smrt program is installed, The next two bytes are
assl.!mep to point to' the Parameter, F.ield of the highleve.l
R,SC-FORTH word to be executed upOn reset. This may be
the"mainfunctionol a usei'defined prQgram or the start up
routioe of a .Development,ROM. Figure 3-7 details propar
alignment.
v!
The systemsmrtUP function, C~eLD,is, e~ecut~ upon Reset.
-COLD, a high level FORTH word, forms the. baSis of the RSC
Operating System. Upon reSElt this' function' i!1Hializes .the
R65F11 or R65F12 registers to establish the external 16K
byte memcxy map and disable' all interrupt Sources. It also
sets up the serial channel for 1200 baud (assuming a 1 MHz
intemal c.lock) asynchronous transmission (seven bits, parity
disabled~The intemal FORTH structure 'W" is prepared for
use and the low level input/output ve(:tors are forced to point
. to the systein ·.rial channel routines. The FORTH User Area
. POinter, UP, is assi!lned the v~lue 0300 Hex.
•
If no, auto start ROM Is fpund, the Ope~ati~g System turns
conlrOl'pver to a prog~,lhat issu.es a "NO ROM" message.
to,·tlle systems terminal via the serial channel and attempts
to boO,t.a'program from disk. A ·fIoppy disk controller, compatible.with'the. WD1793· type, is assumed to be present at
addlllss0100 Hex. The first half 0,1 Track 0 Sector 1 is'loaded
from a double density boot·.diskette into RAM starting at
address 005F. When ,successfully loaded execution will be
turned over to Ibis boot pro~ram'
'il"
A test is made 01 the variable CLD/wRM in memory location
030E. II thiS'contains a value'other than A55A Hex a'cold
reset is assumed. In this case, Jhe IQw level IRQ vector,
IRQVEC; the low level NMI Vector,.NMNEC, and the high
level interrupt vector, INTVEC, are all forCed to point to the
system reset routine.. This prevents an unintentionally generated interrupt from crashing t!1e system. SyStem variables
TIB, RO, SO, UC/L, UPAD, UR/W and BASE are also initialized to their default values.
•
lOC03
lOC02
lOC01
lOCOO
lOC07
lOCH
lOCOS
lOC04
lOC03
lOC02
lOC01
XXOO
I~I{ ~-~'O,_oro~=
::
{AUTO START ROM PATTERN
1KBOUNDARY
AUTO START FORTH PROGRAM
::. r
AABB
= EN,TRY POINTROVTINE
xxoe
:
{ CCDD =
HH
LL
{HHLL
AS
SA
{AUTO START PATTERN
=lOC04
1KBOUNDARY
MACHINE CODE PROGRAM
AUT~.START
Figure 3-7. Auto Start ROM
3-44
FORTH Based Microcomputers
R65Fl1. R65F12
SECTION 4
PARALLEL INPUT/OUTPUT PORTS
4,2 OUTPUTS
The R65F11 has 16 VO lines grouped into two Scbit ports
(PA, PB} and 16 lines programmed as an Address/Data bus
(PC & PO). Ports A and B may be used either for input or
output individually or in groups of any combination. The
R65F12 has 24 additional port lines grouped into three S-bit
ports (PE, PF, PG).
Outputs for Ports A and B are controlled by writing the
desired VO line output states into the corresponding I/O port
register bit positions. A logic 1 will force a high (>2.4V)
output while a logic 0 will force a low «O.4V) output.
Multifunction I/O's such as Port A are protected from normal
port I/O instructions when they are programmed to perform
a multiplexed function.
4.3 PORT A (PA)
PortA can be programmed via the Mode Control Register
(MCR) and the Serial Communications Control Register
(SCCR) as a standard paralleI8-bit, bit independent,
port
or as serial channel VO lines, counter VO lines, or an input
data strobe for the Port B input latch option. Table 4-3 tabulates the control and usage of Port A.
va
Internal pull-up reSistors (FET's with an impedance range of
3K '" Rpu '" 12K ohm) are provided on all port pins.
The direction of the 110 lines are controlled by 8-bit port registers located in .page zero. This arrangement provides quick
programming access using simple two-byte zero page
address instructions. There are no direction registers associated with the I/O ports, which simplifies I/O handling. The
VO addresses are shown in Table 4-1.
Table 4-1.
In addition to their normal I/O functions,. PAO and PA1 can
detect positive going edges, and PA2 and PA3 can detect
negative going edges. A proper transition on these pins will
set a corresponding status bit in the IFR and generate ah
interrupt request if the respective Interrupt Enable Bit is set.
The maximum rate at which an edge can be detectb j is onehaH the _2 clock rate. Edge detection timing is shown in
AppendixF.4.
1/0 Port Addresses
Port
Address
A
0000
0001
0004
0005
0006
B
E
F
G
4.4 PORT B (PB)
Port B can be programmed as an 8 bit, bit independent I/O
port. It has EI latched input capability which may be enabled
or disabled via the Mode Control Register (MeR). Table
4-.2 tabulates the control and usage of Port B. An Input Data
Stro!;lesignal must be providedthru PAO when Port B is programmed to be used with latched input option. Input data
latch timing for Port B is .shown in Appendix F.4.
AppendixF.4 Shows the I/O Port TIming.
4.1 INPUTS
Table 4·2. Port B Control & Usage
Inputs for Ports A and B are enabled by loading logic 1 into
all VO port register bit positions that are to correspond to
VO input lines. A low «O;SV) input signal will cause a lOgic
to be reae;! when a read instruction is issued to the port
regist!lr. A high (>2.0V) input will cause a logic 1 to be read .
. An
signal forces all VO port registers to logic 1 thus
initially treating all I/O lines as inputs.
.
o
REs
The stEltus of the input lines can be interrogated at any time
by r4ilading the VO port addresses. Note that this will.return
the actual status of the input lines, not the data written into
the VO port registers.
Read/Modify/Write instructions can be used to modify the
operation of PA and PB. During the Read cycle of a Read!
Modify/Write instruction the Port.VO register is
For .all
other read instruction!! the port input lines are read, Read!
M3oo
00
6C
(COLD)
-
W
IP
(N-l)
N
XSAVE
INTVEC
TOS
0380
OOFF
OOC2
0050
037E
(DISK)
0010
So
UClL
UPAD
UF\W
BASE
CLD/WRM
IN
DPL
HLD
OISKNO
CURCYL
BlSIDE
-
3·59
0004
IiOO3
(INK)
(OUT)
0300
00
6C
-
0380
OOFF
OOC2
-
II
FORTH Based Microcomputers
R65F11 • R65F12
JLI.I.o"_AR.
~.~~~~I~I~'
~..!'"
~iii
~~
HHHHJn
.~::~:::!!:~:;o
2 ...
I~
•18
~-l
I.
y ,.
"!
I
3-60
il
=
111;~~s.
F·
FORTH' ~a~d MicrocompUters
'R65P1:r~R85Ft2
APPENDIX' E '.'
ELECTRICAL SPECIFICATIONS
,
*NOTE: Stresses above thoSe listed may cause permanent
dalllage to the device~. This is a stress rating only and functional
operation of the device at these Or
9ttler .conditions .above
those indiCated in the other sections.:" this' documerit Is not
im~lied. Exposure tQ~sQlut~ m~",.u.m.rating conditions. for.
extended periods may affect deviq6 reliability. .
'
MAXIMUMAATINGS·
..
F'a...meter
,
SIlPPIy VOl.
Symbol
Value;
.Unlt
Vcc & Vi'IR
-0.3 to +7;0'
Vdc
VIN
-0.3 to +7.0
Vela
Input VOitagli
. Operating :r~mllo/ature
,Commercial
T
.,',
,
any
°C
Qto+70
Storage Temperature
-55'tO +150
Tm
;.
,
"
.
"
°C
DC CHARACTERISTICS
(Vcc = 5V±5%, Vss
= 0, TA
= 0 to 70 0 C)
Parameter
Symbol
TVp~
Min.
Max.
Unit
Power Dissipation (Outputs High)
Commercial at 25°C
Po
-
1000
mW
RAM Standby VOltage (Retention Mode)
VAIl
3.0.
-
Ycc
Vde
RAM Standby.Current (Retention Mode)
Commercial at 25°C,
-IRR
-
4
-
Input High VOltage. (Except XTll)
V IH
+2.0
Input High Voltage (XTll)
V IH
+4.0
IIIPllt low. VOltage
VIL
-0.3 .'.
Input lealtage Current (RES,
Vln :" 010 5.0. Vde
NMi)
:"
.IIL
(I,
V OH
VOL
',.
Dal1ington Curreilt Drive, pe*
(Vo • 1.~ VdC)
f
.. ; ....
Input Cflp8~itluwJi,
(Yin -C), T":
25",C, f • 1.0 MHz)
PA, PB, PC, PO, PF*, and PG*
XTLI, XTlO..
.
Vdc
-
+0:.$
Vde
:t 1\>.0
pAc:tc
JOH
+2.4
-1:0
-1 ..
a
Tl:6
mAde
-
Vcc
Vdo
-
".
+0.4
Vdc
-
mAde
pF
Cln
=
.
-
--
3.0
6.0.
11:5
KO
-
-
±10
' .'
,.Adc
10
pF
'.'
PAo-P~7,f>""PB7;P<»-PC7, PFO-PF7and POO-PG1
O/llPut ·le~. Current
Tri'Staie.llbli while 'in High Impedance·$tate
OUtput Capacitance
'Trl:Stale IIOS'o\mile in High ·Impedanee Stllte
VIN ~.
T A ,·:," 25°C, f '" 25°C, f - 1..0 MHz
Q",.,
Vde
Vcc
"
'.
0lltput l~,VO~1!
,'(IU:lAO ;; 1:6 mAde)
1I0PQrt PulHJp\Aesistance
. Vcc
liN
Input l.QWCUrr6!11 PA, PB,PC, PF*, and PG*
(VIL .. D.4.yd~1
Output High'VQllalle (ExceptXTI..(» .
10:
Fall ,Time
'
15
.. '"7'
10
0,.:
"
I~
XTLI
(XTLO '" V.,)
Te,,,
T,.
1,5V
T!'WX1
•
02
_ _ T.
TpW02
"
:
FORTH B~sed ~iCr()c~mput~s
F.3 MULTt,~L,EXED MODETIMING"";PC ANQPD ,
,
(MCR 5 - 1MCR
6 - 1, MCI:17 - 1)
-
-
$YM8QL
PARAMETER
2 MHz '
1 MHz
MIt.
MAX
T pcRS
(PC~) RIW Setup Time
-
~~
TPCAS
MIN
-
"A~
140
140
(PC<>,PC4. PC6) Address Setup Time,
-'"
22~
T pBAS
(PO) Address Setup T\fTHI
-
2~
T I'IIS\!
(PO) Data Setup TIme
SO
--'-
as
TPBM,R
(PO) Dllt~ Read Hpld Ti,me
10
10
...,..
TpBHW
(PO) DataWrhe HOld Ti~
-
30
30
T pBDO
(PO), Data Output Delay
-
-
TPCHA
(PCO-PC4. PC6) Address HoIQTime
30
-
TPBHA
(PO) Address Hold Time
10
100
10
TPi:HR
(PCS)
30
10
-
30
-
30
-
30
-
'
,
Rtw Hold Time
30
-
T PcHV
(PC7) EMS Hold Time
T pcvotl)
(PC7) Address
T pcvp
(PC7) EMS Stabilization TIme
30,
"-'
TE5U
EMS Set Up Time
-
350'
to EMS Delay Time
-
17~
30
10
-
140
-
:11
150
80
210
NOTE 1: Valu," aSsume PCo-PQI. PCS and PC7 have 'the same ,capacitive load"
,F.3~ 1
Multiplex Mode Tlmlngl)lagram
READ~_ _...,.-........_----.
WRITE 1 , . - - - - - - - - - , .
-,.....,TPCHR
·'-TP,CKV
~MS
TESU
(pc. 7)
, TPCHA-:-
.-;....
..
t:~cvp
PCO-PC4,
PC6
TPBDD
_,TPBHA
PDoPD7
TPBAS
-:--
TI"(:\'P,
-
,;,---
TPBI1R
3-63
,~
TPBHW
R65Frt1. Ft65F12
FORTH Based Microcomputers
F.4 I/O, EDGE DETECT, COUNTERS, AND SERIAL I/O TIMING
SYMBOL
PARAMETER
1 MHz
2 MHz
MIN
MAX
MIN
Tpow(1)
TCMOSI')
Internal Wr"e to Peripheral Oala Valid
PA,PBTTL
PA,PBCMOS
MAX
-
500
1000
-
-
500
1000
.T POSU
Peripheral Oala Selup Time
PA, PB
200
'20.0
-
,T pHR
Peripheral Oala Hold Time
PA,PB
75
:.
.,
TEPW
PAD-PA3 Edge Delect Pulse Widlh
T,CYC
-
Toyo
-
Topw
Tcol')
CounlersA and B
PA4, P~ Input Pulse Width
PA4, PAS Output Delay
Teye
-
,Teye
-
T pSLW
TPLSU
T pSLH
Pori BLaich Mode
PAoStrobe Pulse Width
PB Oala selUp Time
PB Oaia Hold Time
Teyc
75
-
175
30
sqo
-
-
Tcve
150
,,30
500
--
1:,
-
SerialtiO
TPOW(1)
TeMosl"
Tcpw
Tpow")
TeMos")
-
--
$00,
500
PA6XMTRTTL
PM XMTR CMOS
1000
1000
':""",1
' PA4RCVRS/R ClockWidlh
4 Tcye
4 Tcvc
SOb ','
PA4 XMTR Clock-SIR MOde (TTL)
500
1000
1000
PA4 XMTR Clock-SIR Mode (CMOS)
NOTE 1: Maximum Load CapacRance: SOpF Paseill8 Pull-Up Required.
-
~"'I'
-
F.4.1 1/0 Edge Oetectr6oU'lrtei:~ and ~~kUtlO
,
'.,.
Tcy~ ,"
~
.f
\
1.5v\
)
TPDSU
~
"I
J
PAD-PA7
PBO-PB7
PCO-PC7
PDO-PD7
EDGEDETECTS
(pAo-PA3)
TJ"rng ,
)t
"I
,,;;t
\/
',:,
K
TEPW
AS
1s.
1~SV}
.
1.SV.:2L
1 •SV
TCPW
TOO
CNTR
TCPW
2.4V
(PA4, P AS)
O.4V
"
TCMOS
PAO·PA7
TPDW
2.4V
, VDD-30%1
I
PBO-PB7
O.4V
PB
(LATCH MODE)
1.5V
PAO STFIOBE
TpB\.W------IlllOIl
3-65
TPBLH
FORTH Based Microcomputers
R6SF11. R65F12
APPENDIX G
INCLUDED FORTH FUNC'TIONS IN ROM
BANKEXECUTE
EEC!
?
D.R
#>
INIT
DISK
.BANKEECI
#s
<#
DWRITE
MlMOD
I
MOD
MI
M*
ABS
COLD
ERASE
DABS
S->O
BLANKS
EXPECT
COUNT
SPACE
<
1-
2-
C/L
.
PAD
IN
UPAD
fiB
2
.!
+1
SWAP
DNEGATE
0<
>R
RP!
OR
CMOVE
EMIT
(~O)
BRANCH
(.")
DECIMAL
PICK
u<
CLO/WRM
UC/l
BL
1
C@
BOUNDS
2DRQP
NEGATE
0=
LEAVE
SPI
AND
CR
ENCLOSE
(+LOOP)
EXECUTE
BANKC@
.R
#
SPACES
DREAD
BANKC!
D.
SIGN
SEEK
SELECT
*,f
IMOD
*/MOD
MAX
0+(NUMBER)
FILL
-TRAILING
HEX'
ROT
=
2+
HLD
BASE
RO
*
MIN
+HOLD
QUERY
TYPE
"':DUP
>
1+
DPL
UR/W
so
4
3
(j
CI
@
2DUP
DROP
TO~GLE
()+
R
;S
SP@
UI
?TERMINAL
(FIND)
(LOOP)
CLiT
DUP
OVER
+
R>
RP@
XOR
U*
KEY
DIGIT
OBRANCH
LIT
,.
R65FRx .. R65FKx
'"
'1'
Rockwell
R65FRXAND 'Fl65F,Kx '
R$CFQRTH " ,
Dt:VE~OPMENT AND KERNEL ROMS
INTRODUCTION'
The ~~kwell ~i~~le Chip (~S<;:> FORTH Sy$temcan be con·
figured using the R65F11 , R65F12 microcomp~li!rs or the
R660iQ ROM.'e,~~ mii:~?~p~p,lI~e~. O(\C/ of, theSE;! micr~,om~
putel'll. when usedJn conjUnction wlth:ad8VE!\Ppment,~~at\d
a FORTH kernel ROM, prdvidE! the d8signer \yith' maximum lIex~
: ibility when developirig fORTH applications.
,
)'1•. ·",
,
.'
RSC·FORTH is based on the popular fig·FORTH mbdel with'
extenslons.:Th,E/ R66F.11 and R65F12 bOth have the kernel of
the high level Rockwell Single Chip RSC-FORTH language cpn·
tained in the preprogrammed ,ROM. The R65FK2 and R65FK3
Kernel ROMs are preprogrammed ROMs for use with ttle
R6501Q ""hen developing larger applications'requiring more
memory and I/O line support~ All of the ,run time functions olthe
RSC~FORTH are contained in these ROMs, including 16-and
32·l1i1. mathematical, logioal and stack manipOlation, plus
memory and input/output operators. The RS~FORTH Operating
,System allows an external user program written in RSC·FORTH
or Assembly Language tO~:,executed troin exterrlal EPRb~,
or development of such a program under the control of t~e
,R65FR1, R65FR2 or R65FR3 FISC-FORTH Development ROMs.
This document describeS flYfl different RSY.FORtH sYS\E!m con·
figurations using the develOpment and kernel ROMs.
ORDERJNG INFORMATION
R65FR1P
, fORtt:{tevel~ment RQMforFl65l"l1 br RB,5F12
R65FR2P,
FORl'HDevelopment ROM, for R651l1Q"
R65FR3P
Fe>a1:HOevelop.m'lnt ROMjO,r R6501Q
Rs5FK2P
FOR!I:I Kernel ROM f~r RB501Q', :'
R65FK3P
FOfITt!Ket~el ROM for I'ISQ01Q ,":
R65Fl1P:'
4I).p1"I=ORTfiBa,sedMlcroc?pmpute~ at l,MH~
R65FllAP "40-:"111 FORTH~llsed MlcroCQl1IlIuler.t2, M~%
A65F12Q<
64-PfhFORTHSased:MlcrocornPuter at ,I MH%
R65F12AQ 64-PlilI'dRTH, Based Microcomputer at 2MH%,
R65010
64-PinOne-Ctijp Microprocessor at 1 Mfiz
R6501AQ
64.Piri' Olle-(:hlj) Mlcropr;pCaSS9r at 2MH% "
drdllr No.
, R650~QOnlil.chip Micropr'QceseOr product
21415
, Oescilpti,on,~"
,,!
",',
"
2146
R65F) 1,jmd~II5FI2FOATHl!ased' Mlcrocomput~r
Product DesCription
RSC-FO,!'!TH 'user's Manual
2146
2162
Application NOte: A Low-COSI P8llel,g~rnent Module
for the RB5Fll FORTH Micr:09dmpu'ler
'
FEATVAES
• R65FR1FORTH Development ROM'
"::":81< RoM.
"
' ,', ", ,,' ' .
,
;;",A,",
dd,res,sa,b,'!3 frOm
, , $20,
,00 t, h, ro,U,gh
$3FFF
"opmentconfiguraflollmemor'y
map
" in"FORT,H d, evel·
• -R65Fl1 and R65F12 compatible
,,"
,...,.Opetatesin the R65FllJF12 FORTH deVelopment
configuration
,
• R65FR2 FORTH Development ROM
-8K ROM
, , ,
.
-Addressable from $4000 through $5FFF in the FORTH
development configuration memory map
-1'16501 Q compatible for use In emulation of the R65F11/F12
FORTH development configuration
• R65FR3 FORTH Development ROM
-8K ROM
-Addressable from $0.000 through $DFFF in the FORTH
developrnent configuration memory map "
'
-Operates in the", R6501 Q FORTH' development
configuration
'
• R65FK2 FORTH Kernel ROM
-4KROM
-Addressable from$~400 through $FFFF in the FORTH
developm!:tnt configuration memory map
-::R~501Q compatibl.- for !,Ise in the emulati!jn of the ,
R65f11lF121;'qRTH ~velopment configuration",
-::R~pIilcelithe FO,FlTH, ker"el,containadln the,R65Fll and .
R65F12 i)'jlcrocompi.lters ,during development
..
,'J"
.. R65FK3 FORTH Kernel ROM
-4KROM
"
-Addressable from $F400 through $FFFF,in the FORTH
development and produCtion configuration memory rnaps
-R6501Q obmpatible ' ! ,
-Operaijl$iri~he R6$()1QFORTH development andproduc.
tlonconflgurations
'
aSC-F0Rrt:l SVSTEMCONFIGURATION~
Thathree configurations of theRSC.FORTH$ystem are Ide';'
, tlfledby the CP\J·D~elopmem ROM combinations listed beloW:
RSC·FORTH ~ystem COnfigurations
CPU
R6I1F11
R615FI2
ReS01Q
R6501Q
Kemel
AOM
none,
none
RB5FK2
RBSFK3
OIIvelopment
AOM
RB5FRI
R~FRI
R65FR2
R65FR3
: ASC
Configuration
1
1
2
3
Product Description Order No•.2177
Doc"mentfllo. 296S1.N80
3·67.
II,"
February 1984
'
'
"
,
R65FR1
RSC FORTH ROMs
RSC-FORTH CONFIGURATION 1. (R65FR1)
A~D~RODUCTION
R65F11/R65F12 DEVELOPMENT
.
Although programs may reside in. tile upper 8K bytes of memory
area, normally filled by the R65FR1'Developmen~ ROM, it ill dif-·
ficult to develop code for that,area using this configl.lration of
the RSC-FORTH System.
The RSC-FORTH. Configuration .1' provides the designer witli a
FORTH development and application environment at a minimal
cost. The application program is developed using an R65F11
or R65F12 microcomputer; an R65FR1 Development ROM and
external RAM. Up to 8K bytes of RAM space is available using
this configuration. However, Configuration .1 is limited to 5K or
less bytes of RAM during .dev~lopment"111is is the result of
allocating 2K bytes of RAM fOr dlsk'bl.lffers and at least l.K bytes
of RAM for the "Program beads". The program ',~liIads are con. tained in a dictionary containing the Name (NFA), Link Field
• Address (LFA) and the ParamElter Fi~ld MdressPointer (PFA).
" Thill dictionary isa list of FORTH word words and user-defined
FORTH words used in the development of a' FORTH program
and is not present during the execution of the FORTH program.
The difference in using the R65F11 or. the R65F12 is in the
nU!TIber of 110 lines available to I,h!! user. The R§5F11 supports
f6,110 lines, theR65F12 suppoi1s40 110 lineS:. .
.
Figure l' shows the development and production configurations
fo~thEl R65F11/F12. Configurations 1A arid 1B Ustthe features
memory maps, and the relations/:lip of the R65F11 and R65F12
to the R65FR1 Development ROM in the development'and prodL!ction environment.
APPLICATION
DEVELOPMENT
APPLICATION
EPROM
siKBYTES
RAM
s8K BYTES
R65F111
R65F12
R65F111
R65F12
MICROCOMPUTER
MICRO.
COMPUTER
, R85FR1
APPLICATION
RAM
(OPTIONAL)
DEVELOPMENT
ROM
8K BYTES
PRODUc:rIPN , .
DEVELOPMENT
Figure 1.
R66FR1 Configuration 1 Block Dlagl1!m
3-68
RS.c F.ORTH ROMs
R65FA:1
CONFIGURATION 1A CONSIDERATIONS
CONFIGURATION 18 CONSIDERATIONS
Features
• 8K Bytes of User Memory
• 16 I/O Lines
Features
• 8K Bytes of User Memory
• 40 I/O Lines
Device Configuration
Device Configuration
DEVELOPMENT PRODUCTION
DEVELOPMENT PRODUCTION
R65F11 Microcomputer'
11"
R65FR1 Development ROM
11"
11"
R65F12 Microcomputer
"",
R65FR1 Development ROM
"",
11"
User Memory-I/O Resource Matrix
User Memory-I/O Resource Matrix
User memory may be a mix of ROM, EEROM, UVPROM or
RAM.
User memory may be a mix of ROM, EEROM, UVPROM or
RAM.
48K
1
1
1
48KI
MEMORY
MEMORY
16K
8K
0
16
0
32
Memory Mep
Memory Map
FFFFF9
FOOO
..
KI:R.NE.L,. ..
~F9
... FOOO
, .,'t'
4000 b-...,.....,..-,..---j
4000
R65FR1
2000
b------j
0000
L...,-_ _ _ _.J
40
110 LINES
110 LINES
MUX BUS
USER MEMORY
3·69
{
R65FR1
2000
USER MEMORY
0000
II
R65FR2 .• R65FK2
RSC FORTH. ROMs
RSC-FORTH CONFIGURATION 2
(R65FR2, R65FK2)
R6501Q DEVELOPMENT AND R65F11/F12
PRODUCTION
The RSC-FORTH Cenfiguratien 2 prevides the designer with the
capability ef using the full 16K bytes ef external address space
ef the R65F11 and R65F12.
Using this cenfiguratien, the applicatien pregram can be
develeped using the R6501Q and. then later installed in an
R65F11 er R65F12 micrecemputer witheut medificatien.
TheR6501Q ROM-less· micreprecesser, when used with the
R65FK2 Kernel ROM and the R65FR2 Develepment ROM,
emulates the eperatlen ef the R65F11/F12. Because ef the
greater address space of the R6501 Q, the R65FR2 Devel()pment
ROM can be relecated to. address $4000 and the disk buffers
and HEADS pregram to. $6000. This expands the available user
memery space to. 16K bytes, $0000 threugh $3FFF.
Figure 2 shews the develepment and preductien cenfiguration
fer the R6501 Q. Cenfigurations 2A and2B list the features
memery maps, and· the relatienship ef the R6501Q to. th~
R65FR2 DevelepmentROM ar,ld R65FK2 Kernel ROM in the
deve.lepment and. preductien envirenment. Figure 3 is a
schematic ef the R6501Q, R65FR2, R65FK2 develepment setup.
DISK AND
HEADS RAM
:sSK BYTES
R65FR2
DEVELOPMENT
ROM
SK BYTES
APPLICATION
EPROM
:s16K
. R65FK2
KERNEL
ROM
3K BYTES
R6501Q
MICRO·
PROCESSOR
R65F11f
R65F12
MICRO·
PROCESSOR
APPLICATION
DEVELOPMENT
APPLICATION
RAM
16K BYTES
RAM
:s16KBYTES
PRODUCTION
DEVELOPMENT
Figure 2.
R65FR2 and R65FK2 Configuration 2 Block Diagrams
3-70
RSC FORTH ROMs
R65FR2 • R65FK2
CONFIGURATION 2A CONSIDERATIONS
CONFIGURATION 28 CONSIDERATIONS
Features
• 16K Bytes of User "Headerless" Memory
• 16 1/0 Lines
Features
• 16K Bytes of User "Headerless" Memory
• 40 110 Lines
Device Configuration
Device Configuration
DEVELOPMENT PRODUCTION
DEVELOPMENT PRODUCTION
yI
R65F11 Microcomputer
yI
R65F12 Microcomputer
R6501 Q Microprocessor
yI
R6501 Q Microprocessor
yI
R65FR2 Development ROM
yI
R65FR2 Development ROM
yI
R65FK2 Kernel ROM
yI
R65FK2 Kernel ROM
yI
II
Memory-I/O Matrix
Memory-I/O Matrix
If floppy disk is used in the application, space for the disk buffers must be allocated in memory from $0500 through $3FFF
or $6000 through $7FFF. User memory can be a mix of ROM,
EEROM, UVROM or RAM.
If floppy disk is used in the application, space for the disk buffers must be allocated in memory $0000 through $3FFF. User
memory can be a mix of ROM, EEROM, UVROM or RAM.
1
1
MEMORY
MEMORY
16K
1BK
6K
BK
32
16
16
40
Memory Maps
Memory Maps
PRODUCfION
DEVELOPMENT
R65FK2
FFF
Fn
F400
BOOO
6000
1
FFFF~
1
F400
KERNEL
DEVELOPMENT
~'n
BODO
BK USER RAM
(HEADS)
BODO
R65FR2
4000
0000
USER
MEMORY
CODES ONLy)
32
40
110 LINES
1/0 LINES
'''Fn
PRODUCfION
BK USER RAM
(HEADS)
RB5FR2
40001-----1
USER
MEMORY
0000 (CODES ONLy)
4000
0000
3-71
USER
MEMORY
CODeS ONLy)
4000 I - - - - - f
USER
MEMORY
0000 (CODES ONL.Y)
i
VJ
+5V
121
~.
r-.WE
2KRAM
~
XTLO
XTLI 2
en
m
....0
"III
Z
C
:g
c..
C
~
"III
m
:D
-t
0
"III
r
C
til
~
Z
-t
0
:II
GI
en
......
"II
en
0
(')
'"
!!l
•
e2
::D
CJ)
Pee 4
C
PC1 5
PC2 8
i>c3 7
PC4 8
PC5 9
. pea 10
,PC7 11
:PD7 12
POI 13
c.. PD5 14
..... PD4 15
'ii: PD3 16
o .PD2 17
18
"III PD1
19
- POI 20
Z RES
21
2 Vee 22
"III NMI
en PA7 23
PAl 24
(') PAS 25
'" PA4 2
PA3 27
__ PAZ 28
o
!!l
c.n
':'II
~
59
......c
:II
GI
en
o
....
£)
C;;
....
ADDRESS BUS
"III.
Z
c
DATA BUS
£)
.!
A151-='=----.!J,
A13~'----
!III
PA1
PAt
PB7
PB8
PBS
PB4
PB3
3
paz
PB1
PIlI
VIIR
Vss
~4
U5
US
U7
74lS04
74LS10
74LSOO
+5V
GND
14
14
14
7
7
7
.,NOTES
PIn 22 on R6501Q-Sync SlgIIIII nat COfII18CIad.
~ emu....ng a R65F12 .,.rem PorIII E, F or G
muat be c:onaIJUeIed axtemaJIy UBlng TTL cln:uhs
(contact RoCkweII).
a1n
(g
~
::E:
::0
o
Figure 3. R6501 Q. R65FR2 and R65K2 Application Ccmti9uration Schematic
s:::
fIJ
Rse ;FORTH.FlOM$
A85.FR3 .. R65FK3
RSC-FORTH CONFIGURATION 3
(R65FR3, R65FK3)
CONFIGURATION 3 CONSIDERATIONS
Features
• R6501 a w/FORTH
• 48K Bytes of User Memory
• 30 I/O Lines
R6501~ BASED SYSTEM' DEVELOPMENT
AND PRODUCT.ION
The RSq-FORTH Configuration 3 is designed for thase applications which require a larg,r amount of ROM or RAM sp8C\il than
the R65F11 or R65F12 Clln provide.
Device Conflguretlon
DEVELOPMENT PRODUCTION
In the development configuration, the uset Is provl~ed with up
to 48K bytes of memory. The user memory Is located from $0000
through $BFFF. The program heads wliluse some of this area
but the user will still have considerably more memory space
available then in the previous configurations. .
\
The production configuration provides up to 56K bytes of user
memory. This i.s due to the fact that the R65FR3 Development
ROM, used in the development configurl!.tion, is not required
in the production configuration and releaSes the 8K bytes of
memory space. This memory is located at $COOO through
$DFFF.
rV
ReSOlQ
MICROPROCESSOR
~ ::>
-..::>
V'
R65FK3 Development ROM
V'.
R65FR3 Kernel ROM
V'
II
V'
V'
User Memory-IIO Resource Matrix
All ports act as 1/0 ports. Memory is on the bus.PC6 & PC7
(1/O.lines) are assigned to memory. User memory can be a mix
of ROM, EEROM, UVPROM or RAM.
Figure 4 shows the development and production configurations
for the R6501 a. Configuration 3 lists the features, memory maps,
and the. relationship of the R6501 Q to theR65FR3 Development
ROM and the R65FK3 Kernel ROM in the development and production environment.
r-"\
R6501 Q Microcomputer
ReSF113
DEVELOPMENT
ROM
MEMORY
8K BYTES
==
ROM'
18
4KBYTES
32
110 LINES
APPUCATION
DEVELOPMENT
RAM
Memory Maps
;;48KBYTES
DEVELOPMENT
DEVELOPMENT
FFFF
FOGO
R85fI(3
·R.~FK3
PRODUCTION
FFFF
R85FK3
FOOO
AV.(ILABLE
KERNEL
IioM
FLoPPY' CONTROL
-Q
EOOO
MICRO-
AVAILABLE
E008
E008
',.,-
EOOO
FLOPPY' CONTROL
R8SFR3
PROCESSOR
COOO
APPUCATION
.
RAM
,.sex BYTES
USER
MEMORY
USER
MEMORY
PROOUCTION
00001
Figure 4. R65F1J3 and R65FK3
Configuration 3 Block Diagrams
3-73
J
40
RSC FORTH ROMs
R65FRx • R65FKx
'J'
Ne
A12
A7
A6
AS
A4
A3
A2
A1
AO
00
01'
D2
GNO
2
3
4
5
6 R65FR1
OR
7'
R85FR2
8
OR
9 R65FR3
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
vee
Ne
Ne
A7
A6
AS
A4
A3
A2
A1
AO
,DO
D1
D2
A8
A9
A11
OE
A10
cs
D7
08
D5
D4
03
GNO
1
2
24
23
22
3
4
21
5
20
6 R6~FK2 19
OR
7
18
8 Fi85FK3 17
18
9
10
15
11
13
'14
12
RSC-F~!UH ROM Pin ~gnments
3-74
vee
A8
AI
A11'
OIS
A10
es
D7
D6
D5
04
03
R6501Q
'1'
Rockwell
R6501Q
ONE-CHIP MICROPROCESSOR
SECTION 1
INTRODUCTION
1.1 FEATURES OF THE R6501Q
• Enhanced 6502 CPU
'-Four new bit manipulation instructions
• Set Memory Bit (SMB)
• Reset Memory Bit (RMB)
• Branch on Bit Set (BBS)
• Branch on Bit Reset (BBR)
-Decimal and binary arithmetic modes
-13 addressing modes
- True indexing
• 192-byte statiC RAM
• 32 bidirectional, TTL-compatible I/O lines (four ports)
• One a-bit port may be tri-stated under software control
• One . S-bit port may have .latched inputs under software
control
• Two 16-bit programmable counter/timers, with latches
-Pulse width measurement
-Asymmetrical pulse generation
-Pulse generation
-Interval timer
-Event counter
-Retriggerable interval timer
• Serial port
-Full-duplex asynchronous operation mode
-Selectable 5· to a-bit characters
-Wake-up feature
-Synchronous ,Shift register mode
-Standard programmable bit rates programmable
up to 62.5K bits/sec @ 1 MHZ
• Ten interrupts
-Four edge'sensitive lines; two positive. two negative
...... Reset
-Non.maskable
~ Two counter underflows
-Serial data received
-Serial data transmitted
II
• Bus expandable to 64K bytes of external. memory
• Flexible clock circuitry
-2-MHz or 1-MHz internal operation
-4 MHz Crystal used to generate internal clocks
•
•
•
•
1 JJ,s minimum instruction execution time at 2 MHz
NMOS-3 silicon gate, depletion load technology
Single +5V power supply
12 mW stand-by power for 32 bytes of the 192-byte RAM
• 64'pin QUiP
1.2 SUMMARY
The R,ockwell R6501Q is a complete. high-performanceEl~bit
NMOS·3 rir]icrocomputer on a single chip and is compatible
with all memoorsof the R6500 family.
The. R6501Q consists of an enhanced 6502 CPU, an internal
clock o~cillator. 192 bytes of Random Access Memory (RAM),
and versatile interface circuitry. The interface circuitry i!1cludes two 16-bit programmable timer/counters,32 bidirectional inpuVqutput lines (including four edge-sensitive lines
and input latching,onone S-bit port), a full-duplex serial I/O
. channel, ten interrupts, and bus expandability.
The innoliativearchitecture and the demonstratedl:ligh performance of theR6502 CPU, as well as instruction simplicity,
results in system cOst-effectiveness and a wide range' of
computational power. These features make the R6501 Q a
.
leading cal'ldidatefor microcomputer applications.
Document No. 29651N48
3-75
Product DescrlptionOrder.No. 2145
Rev. 2, 'March 1984
R6501·Q
One-Chip Microproces$or
Rockwell suppOrts development of the R6501Q
System 65 Microcomputer Development System
R6500/* Family of Personality Modules. Complete
emulation with the R65001* Family of Personality
allows total system test .and ev.aluaUon.
1.3 CUSTOMER OPTIQNS
with the
and the
in-circuit
Modules
The R6501 Q has no customer s~ecified mask opttons. It ~as
the following characteristics. .
.
•
•
•
•
•
This product description assumes that the reader is familiar
with· the R6502 CPU hardware and programming capabilities. A detailed description of the· R6502 CPU. hardware is
included in the R6500 Microcomputer System Hardware
Manual (Document Number 29650N31). A description of the
instruction capabilities of the. R6502 CPU is contained in the
R6500 Microcomputer System Programming Manual (Document Number 29650N30).
Crystal Oscillator
Clock Divide by 4
Clock MASTER Mode
Reset Vector at FFFC
Internal pull-up resistors on Ports PA, PB, and PC
1.4 ORDERING INFORMATION
R6501Q.~
R6501AQ
.
4 MHz Xlal. 1 MHz Operation
4 MHz Xtal. 2 MHz Operation
.
1,50
_...'3.81 MM) ........
I I
PD.
PC.
PCS
PC6
Pi07
PD'
PD'
P,,"
PC7
pp:e
PC,
RES
A"
A"
A"
A"
Ai
A.
A7
AS
AS
M
A>
A'
A'
AD
v"
SYNC
NMi
PS7
PBS
PB5
PS.
ps,
pC.
PC,
PC,
PCl
PC,
DS'
DSI
OS,
R6501Q
DS'
DB.
DS,
DS.
DB7
"v"
§
~
g
PAl
PS,
PBI
PAl
PA7
PAO
~
'"'d ~
V••
XTlI
"nD
RIW
PA'
"
~
Cl
p..
_.1_
J
.020 REF
TVP
64 PIN QUIP
Figure 2-1.
Mechanical Outline & Pin Out Configuration
3-76
One-Chip ..Micropro"essor
'A6501Q
SECTIO.N2
R6501 QINTERFACEREQUIAEMENTS
TAIiILE 2-1.A&s01Q Pill Descriptions.
SIGNAL NAME
pjlilNO.
DESCRIPTION
This section. describes .th.e- intel'fl;iQe requirements for the
R6501Q. Figure 2-1 and 2-2 show the Interface Diagram. and ....
the pin oulconfiguration for both devices; Table 2-1 describes
the function of ~h pin. Figure 3-1 has a detailed block diagram of the R6501Q ports which illustrates the internal Junction of the device.
Vec
V,.
21
43
Vss
XTLI
44
42
Main pOwer supply fSV
Separate pewer PI~ fOr RANI.
'In' the event that Vee JlOIrir
is off,. this power retains RAM
data.
.Signal and power ground (OV)
'Cry~I' or clock inPtJt for Intem!!1 clock oScillator. Allqws
InPut of XI Clock signal if
)(TLO is connected to V..
of X4 Clock if XT\,O is 1IQated.
Crystal output from internal
clock oS,pillatQr.
The Reset input is u$ed to
initialize the device. This signal must not transition' from
low to. high for at least 1!ight
cycles after V ce reaches operating. range· and the internal oscllfato{ has stabilized.
Clock signal ,output at'lnternal frequency.
.'
A negative gping edge on the
Non-Maskable'lhterrupi lIignal' requests that
nonmas~able interrupt be gen-.
erated with the CPU.
Four:\8-bit pOrts 'l!sfjd for
eith~iQPut/output. 'EaCh litle
of Ports A, Band C consiSts
olan active transistorto ~as '
and a passive 'pull-uP'to'V"e.
. Port DfUnctions asllillletan
a·btt input or .&'bit oUlpufpoit.·,
It has aCtive Pllli'up'and pun' : ./ :
down transistors.' '
Fourt8en address fines u$ed·. .
to " address a complete
6SK .xternal ad~reSi!l space.
Note: A13 & A14 a(uourced
Il1ro~~~.PC6'.& PC7 Wt1el)ih
the FuilAddress Modli." .,
Eigljt~'9iiElctional dl\!iI. bus
lines used tp transmit data to
anel frorn ,external meinory.
.' SYNC is a pOsitive goil'lg sig"
nal for :the fuR 'i;lock'qycile
IIIhemeverthe ,CPO i!lPerforming'an Op CODE,fetah •
or
XTLO
41
REs
6
.no.---~::::::::~~::::::::~
XTu
EDGIDETECT
,.0:'.7
lID
IIIiI
(PAG, 'A,1,
PAl, PA3:
'EDGE DETECTS)
PBOoP~
45
(LATCHED INPUTS.
D8IPAI)
(DATA STROBE)"
a
PAo,.PA7
PBO-PB7
39-32
3,-24
54-61
62-64,
PCo-~C7
fOoo:.I'>D!
1'5
CAl'''')'
'C8(PAS)'-'
I
SOI"AI),
"'IPAI)
Flgur.· 2-2•..·lnt.~Dlagram
~46
DBo-DB7
,~y~C
',!I
'22",
.......;.:,
,,;'
RIW
Conlnlls the di~on (If C:!8t8
40
.
::
','
3-77
transfer between the CPU
and the 'external, ~' ado,
drl!.s~ !,pa<;e' T.lje $ignal is
high. 'llihen' .r$lding· and Idw
~ari:
wrl!!nc!:
'. , .' ,
II
R6501Q
One-Chip Microprocessor
SECTION 3
.SYSTEM ARCHITECTURE
This section provides a functional description of theR6501 O.
Functionally the R65010 consists ofa CPU, RAM, four 8~bit
parallel I/O ports, a serial I/O port, dual counter/latch circuits,
a mode control register, and an interrupt flag/enable dual
register circuit. A block diagram of the system is shown in
Figure 3-1.
location is stored (or "pushed") onto the stack. Each time
data are to be pushed onto the stack, the Stack Pointer is
placed on the Address Bus, data are written into the memory
location addressed· by the StaCk. Pointer, and the Stack
Pointer· is decremented by 1. Each time data are read (or
"pulled") from the stack, the Stack Pointer is incremented by
1. The Stack POinter is then placed on the Address Bus and
data are read from the memory location addressed by the
POinter.
NOTE
Throughout this document, unless specified otherwise,
all memory or register address locations are specified
in hexadecimal notation.
The stack is located on zero page, Le., memory locations
00FF-0040. After reset, which leaves the Stack Pointer
indeterminate, normal usage calls for its initialization at OOFF.
3.1 CPU LOGIC
3.1.4 Arithmetic And Logic Unit (ALU)
The R65010 intemal CPU is a standard 6502 configuration
with an 8-bit Accumulator register, two 8-bit Index Registers
(X and V); an8-bit Stack Pointer register, an AlU, a 16-bit
Program Count~r. and standard instruction register/decode
and internal timing control logic.
All arithmetic and logic operalions take place in the ALU,
including incrementing and decrementing internal registers
(except the Program Counter). The AlU cannot store data
for more than one cycle. If data are placed on the inputs to
the AlU at the beginning of a cycle, the result is always gated
into orJe of the storage registers or to external memory during
the next cycle.
3.1.1 Accumulator
The accumulator is. a general purpose 8-bit register that
stores. the results ofmost arithmetic and logic operations. In
addition, the accumulator usually contains one of the two
data words used in these operations.
Each bit of the AlU has two inputs. These inputs can be tied
to various internal buses or to a logic zero; the ALU then
generates the function (AND, OR, SUM, and so on) using
the data on the two inputs.
3.1.2 Index Registers
3.1.5 Program Counter
There are two 8-bit index registers, X and Y. Each index register can be used as a base to modify the address data program counter and thus obtain a new address-the sum of
the program counter contents and the index register contents.
The l6-bit Program Counter provides the addresses that are
used to step the processor through sequential instructions
in a program. Each time the processor fetches an instrucliOn
from program memory, the lower (least significant) byte of
the Program Counter (PCl) is placed on the low-order bits
of the Address Bus and the higher (most significant) byte of
the Program Counter (PCH) is placed on the high-order.8
bits of the Address Bus. The Counter is incremented each
time an instruction or data is fetChed from program memory.
When executing an instruction which specifies indirect
addressing, the CPU fetches the op code and the address
and modifies the address from memory by adding the index
register to it prior to loading or storing the value of memory.
Indexing greatly simplifies many types of programs, especially those using data tables.
3.1.6 Instruction Register and lristruction Decode
Instructions are fetched from ROM or RAM and gated onto
the Internal Data Bus. These instructions are latched into the
Instruction Register, then decoded along with timing and
interrupt signals to generate control signals for the various
registers.
3.1.3 Stack Poi nter
The Stack POinter is an 8-bit register, It is automatically
incremented and decremented under control of the microprocessor to perform stack manipulation in response to either
user· instructions, an internal IROinterrupt, or the external
interrupt line NMI. The Stack Pointer must be initialized by
the user program.
3.1.7 Timing Control
The Timing Control Logic keeps track of the specific instruction cycle being executed. This logic is set to TO each time
an instruction fetch is executed and is advanced at the
beginning of each Phase One clock pulse for as many cycles
as are required to complete the instruction. Each data transfer
which takes place between the registers is caused by
decoding the contents of both the instruction register and
timing control unit.
The stack allows Simple implementation of multiple level
interrupts, subroutine nesting and simplification of many types
of data manipulation. The JSR, BRK, RTI and RTS instructions use the stack and Stack Pointer.
The stack can be envisioned as a deck of cards which may
be accessed only from the top. The address of a memory
3-78
One-Chip Microprocessor
II
E
I!!
m
as
is
I
III
11
:"
..
3-79
~
Q
One-Chip'Mlcroprocessbt
3.1.8 Interrupt Logic
3.4 RANDOM ACCESS MEMORY (RAM)
Interrupt logic controls the sequencing of three interrupts;
RES. NMI and IRQ. IRa is generated by any one of eight
conditions: 2 Counter Overflows. 2 Positive Edge Detects;
2 Negative Edge Detect~. and 2 Serial Port Conditions.
The RAM consists of 192 bytes of read/write memory with
an assigned page zero address of 0040 through OOFF. The
R65010 provides a separate power pin (VAA) which may be
used for standby power. for 32 bytes located at 0040·005F.
In the event of the loss ofVee power, the lowest 32 bytes of
RAM data will be retained if standby power is supplied to the
VA. pin: If the RAM data retention is not required then VRA
must be connected to Vee. During operation VRR must be at
the Vee level.
3.2 NEW INSTRUCTIONS
'Inadditlon to the standard R6502 Instruction set, four new
bit.n,anipulation instructions h~YI:j been adcled lothe.R~0,10.
The addedln$VUctions and their format are explained in the.
following parag~hs. Refer tq Appendix A for the. Op Code
mnemonic addressing matrix for these added instrucitlons..
The four added instructions do not impact the CPU proce$sor'
status register,
3.2.1
._ :i=or the RAM to retain daia upon loss. of Vee. VRR must be
'.' 'Sl,Ipplied Withi!.lqperating range and RES must be driven low
at least eight ~2 Olack pulses before Vte falls out of operati.ng
range., RES must then be held low wh!l.e Vee is out of oper·
ating'''range and. until at least eight ~2c'ock cycles after Vee
is again within operating r~nge and the Internal ~~ oscillator
is stabilized. VRR must remain within Vee operating range
'during ",ormal op~ration. "then Vee is out of operating range,
V,AR' ml.lst remain \flthin the. VRA retention range in order, to
retain data. Figure 3.2 shows typical waveforms.
s.t Memory Bit (SMB' m, Add~.)
This instruction sets to "1 ,j one of the,8·bit data field specified
by thezaro page address (memory or I/O port). The first~yte .
of th!, instructio.n specifies the SMI3 operation and onEl.ofeight·
bits ,to be set. T/"Ie second bytedfithe instl'\.!Q\lqn designates
address (0-255) of the byte to beoperatad upon.
.
RAM oPE~AnNQMODE
,'.
~:mW:if::;:~~~-l
3;2~2 Reset Memory. Bit (RMB m, Addt;)
ThistnstructiQr:' is the ~ame operation at')d tbrmat
instruction ex~"t a reset to "0'/ Of t~e biqesults.
as 5MB
'.
-~~0
3.2.3 Bninc,J1 On BIISetRe,lative(BBS m,A~dr~
OESTj'
RA,,!.RI!:rENTIONMODE
.t· · 1
.
2
3
4
5
This instructioh tests one of eight bits designated by a 3"bit
immediate field within the first byte of the instruction. 'The
second byte is used to designate the address of the byte. to'
be tested within the zero page address range (memory or
I/O ports). The third byte of the instruction is. used to specify
the 8·bit relative address to which the instruction branches
ilthe bit tested is a "1". If the bit tested is not set, the next
sequential instruction is executed.
-
,"--11-0
1
,-
--j j.... TRL 0
INITIAL APPLICATION OF Vee AND v...
LOSS OF v oc• flAM ON STANDBY POWER,
REAPPLICATION OF v"".
>8 _2 CLOCK PULSES AFTER OSCILLATOR STABILIZATION.
>8
CLOCK PULSES.
.2
Figure 3·2. Data Retention Timing
3.5 CLOCK OSCILLATOR
The R65010 has been configured for, a prystal OSCillator,
Ii .countdown network, !l~d for Master Mode Operation.
3.2.4 Branch On Bit Reset Relative (BBR m,
. Addr, OeST)
A reference frequency can be generated with the on·chip
oscillator using either an external crystal or an external
oscillator .. The oscillator reference frequency passes
through an internal countdown network to obtain the
internal operating frequency (see Figures 3-3a and 3·3b).
Th~ external crystal generated reference frequency is a
preferred method since the resistor' method can have tol·
erances approaching 50~.
.
This instructioh is the same operation and format as the BBS
- instruction except that a branch takes place if ~he bit :tested
is a "(y'.
3.3 READ.;ONL Y-MEMORY (flQM)
The R65010 has no ROM and its Reset vector is at FFFC.
Note:
When operating. at 1 MHz interval frequency
(R6S01Q) place a 15·22pt capacitor between
XTLO and ground:
:J.80
R6501Q
One-Chip Mlcr,oprocessoi'
simultaneous interrupts calise the ~ interrupt ~uest to
remain active until all interrupting conditions have' been
serviced and cleared ..
Internal timing can also be controlled by driving the.XTLI pin
with an external frequency source. Figure 31~shoWS typical.
connections. If XTI,.O is left floating, the external sOl:lrce is
diviciedby the internal coun~~own network. However, if XTLO
is tied to V•• , the internal countdown network is bypassed.
causing the chip to operate at the frequency of the external
source.
... _
t
a
xn.1
c::::J.
.....Q
•
XTLO
'.
The Interrupt Flag Register contains the information that
indicates which I/O or counter needs attention. The contents
of the Interrupt Flag Register may be examined at ·any time
by reading at address: 001:1. Edge detect IFA bits may be
cleared by executing a AMB Instruction at address location
0010. The AMB x, (0010) instruction reads FF, modifies .bit
X to a "0", and writes the mQdlfled value at address location
0011.ln this way IFR bits seltaa "1" after the read cycle of
a Read-Modify-Wrlte Instruction (suchas RMB) are protected
from being cleared. A logic "1" Is Ig~ored when writing to
edge detect IFR bits .
f, .. , , .. 2 MHz
•• Cryatlillnput
Each IFR bit has a corresponding bit In the Interrupt Enable
Register which can be set to a "1" by writing a "1" In the
'respective bit position at location 0012. Individual IER bits
may be cieareqby.'wrlting a. "0" In the. respective bit position,
or by RES. If set a "1", an IRQ will be generated when the
corresponding I'FR bit becomes true. The Interrupt Flag RegIster and Interrupt· Enable Register bit assiglJments are shown
in Figure 3-6 and the functions of each bit are explained in'
Table 3-1.
300"
XTLI
HMHZ
....,Q
He
',N. =-
,,2MHz
to
XTlO
v"
XTU
f"., ""
_.Q
tu
1 or 2 MHz
,=', .. ,
XTlo
b. CtocklnplllS
MCR
Figure 3·3. Clock O.elllator Input Options
Addr 0014
ounter A
Coun.... B
Mode Select
I I
"_.1"
Ii 0
Tim..
0 - • Pull' Generation
1 - O·Event Counter
1 - 1 Pulse Width M....
0 - 0 Inttrval nmer
o- , Asymmetric Pul.. Generation
BUI Mode Selecl
3.6 MODE CONTROL REGISTER (MCR)
Mod. Select
1_
0 Event COunter
1_
1 Ratrlggerable Interval Timer
Port B Latch
(1 - Enlbled)
Port D Trl-$t.t.
The Mode Control Register contains control bits for the mtrl·
tifunction I/O ports and mode se.lect bi,ts for Counter fJ:. and
Counter 6. Its setting, along with the setting bf the Serial
Communications Control Register (SCeR), determines the
basic configuration of the R6501 Q in any application. Initializing this register Is one of the first actions of any software
program. The Mode Control Register bit assl!lnment is shown
In Figure 3-5.
(0_ Trl Stalo High Impedance Mod.)
0 -, ',0'Full ~dnu
0""'-""'-1 Normt'
.-1.U.
1 - '0 Not UNCI
Figure 3·5. Mode Control Register
The use of Cou{lter A Mode Select is shown in Section 6.1.
3.7 INTERRUPT FLAG REGISTER (IFR)
AND INTERRUPT ENABLE
REGISTER (IER) ,
The us~ of cOunter B Mode Select is shown in Section 6.2.
An iRCl Interrupt request can be Inltiat9dbY any or all of eight
possible sources. These sources ilr:e all capable· of being
enabled or disabled by the use of ,the appropriate interrupt
enabled bits in the Interrupt Enable Register (IER). Multiple
The use 6f Pori 0 In Trl-State Enable is shown in Section
4.6.
'\
The use of Port B Latch Enable is shown in SectiOn 4.4.
The use of Bus Mode Select is shown in Section 4.5 and 4.6.
I"
3-81
II
One-Chip MicroprocessOr
R6501Q
IER
Addr 0012
IFR
Addr 0011
The Carry eit may be set or cleared under program control
by use 01 the Set Carry (SEC) or Clear Carry (CLC) instruction, respectively. Other operations which affect the Carry Bit
are ADC, ASL, CMP, CPX, CPY, LSR, PLP, ROL, ROR, RTI,
and SBC.
PAO Poeiliva
EdgaOetect
. PAl Poaltlve
Edge Oetect
INlvllalDlllzlcl
PA2 Negllllve
Edge Detect
PA3 NegaUve
Edge Oetect
eauntwA
U~F1.g
CaurarB
L
CARRY(C)®
1 = Carry Set
-
Un_Flag
ReceIVer
o ,::
Carry Clear
ZERO(Z)(!)
1
=Zero_"
o = Non..zerG Result
Fleg
XMTR
INTERRUPT DISABLE (Q®
Flag
1
o
Figure 3-6; Interrupt Enable anct Flag Reglste...
\ "
•
c,
= fRQ Interrupt Disabled
=IRQ Interrupt Enabled
;.:.
DECIMAL MODE (D)C!)
1
=_1_1_
o =Binary _ .
3.8 PROCESSOR STATU~' Rr,:GISTet:r.
BREAK COMMAND (alC!)
TIle a-bit Processor Status Register, shown in 'Figure
3-7, con~ins seven status flags. SOI)'leol these flag~ are
cqntrolleQ' by the user program; oth~r:s may be' CiOnt':OIIed
both by the user's program and the CPU. The R6502
instruction set contains a number 01 conditional branch
instructions which are designed to allow lestin9 of these
flags. Each 01 the eight process.or status flags is
described in the loll~wing sections.
I
_a_Com_
o ;: Non arelt Commend
OVERFLOW (010
=
1 Overflow Set
0: Overflow Cloer
NEGAnYE (N) C!)
NOTES
NotlnlUall_ by
n. This bit
muSt be initialized to the desi~ds~~e' by the user pro- ,
gram or erroneous results may Occur..
Break Bit (B)
3.8.6 Overflow Bit (V)
The Overflow Bit (V) is used to indicate that t.he resi:J1t ola
signed, binary addition. or subtraction. oPeration is a value
that cannot be contained in seven bits (-"128.'" Ii '" 1'27).
This indicator only has meaning when ~igned arithmetic (sign
.
and sellen magnitude bits) is performed. When the ADC or ' :
SBCinstruction is performed. the Overflow Bit is set to' logic .
1 if the polarity of the sign bit (bit 7) is changed because the
result exceeds +127 or-128; otherwise the bit is cleared
to logic O. The V bit may also be cleared by the programmer
using a Clear Overflow (CLV) instruction.
The Overflow Bit may also be used with the BIT instructiOn.
The BIT instruction-which may be used to sample interface
devices-allows the overflow Ilag·to reflect the condition 01·
bit 6 in the sampled field. During .aBIT instruction ,the Over-'
flow· Bit is set equal to the content of the bit 6 on the d$ta·
tested with BIT Instruction. When used In this mode, the
overflow has notlling to do with signed. arithmetic,. but is just,
another sense. bit. for the microprocessor. Instructions affecting
the V flag are ADC, BIT, CLV, PLP, .Rrl and $BC.
3.8.7 Negative Bit (N)
The Negative Bit (N) i!! used to indiqate that the. sign bit (bit
7) in the resulting value of a dala"movement 'or data arith'metic operation is slH'to logic .1, If the Sign bit is set to logic
1, the resultingllalueof the~ata movement or arithmetic
operation',is negative; if the sign bit is clear8d, the resul\of
the datamovement.'Qr arimmetic. q,eration is positive. There
are no instr\Jctions ttlat set or clellf the Negative Bit siooe the
N$gativl!! . Bit repreSents only tile sta~us of
result. The
instructions, that effeCt the stll/eot the N$9atlveBit are: AOC,
AND, ASL, BIT, CMP,CPX, CPY, DEC, DEX, DEY, eOR.
INC, INX, INY,LDA, LOX, LOY, \..SR, ORA, PLA, PLP, ROL,
RCR, RTI;.SBC. TAX, TAY, tS)(, T)(A, and, "TYA: '< 2,;"
l
a:
."'.,;.,
3
One-Chip Microproces.or
R6&OtQ·.·
SECTION 4
P.ARALLEL ,I NPUT/OU:rPUT PORTS
& BUS MODES'
Port 0 may only be all ioputs o~ aU outPuts. All inputs is
selected by setting bit 5 of the'Mode ConttQI Regislllr. (MCRS)
The devices have 32 110 lines grouped into four 8-bit ports
(PA,PB; PC. anjj PQ);'Porls A tl;lroug~ C may be used either
for Input oroujput indtv.idually or in groups many COlIlbination ..
Port maybe .use(f'Ii!i. all inputs or all. outputs. .
·toa"O",
o
..'
The status of thElinput Iines·Can beintertpgaledatlanyti~e
by readirig the 1/0:port addresses: Note tha(t/;lill will return
the/lctualstatus of the inpyt lines, not the· datil wr.i\ten i~to
the 1/0 port registers.
."
.
s~~
Mullifunctlonl/O's
as Port A and PortC are. protected
fromnormai port 110 instructions when they are programmed·o·
,
to perform a mullipl!ilxed function:"
Read/MQdlfylWrite inlltruclions ~an be used to modiiythe
operation.ofPA, PB, PC, & PD. During the Fleadcycle of
ReadIMod\fy/W~jt~ inst.ructlon. the, Port I/O regis~r is read.
For allother rttadinstrIlCtiprstl)epoi:\illPut lines are r!'lIi:!.
FleadlMociify~ite instruejio~$atAt:A$., DEC, INC, LSR,
RMtar.ROI:.;ROFl, af'!d:SMB.
a
Intemal'pUII-up resistorS (FEr's with an impedance range of
RL .. 12K 'ohm),' are provided on lill port pins excl:jpt
PortO.
3K ..
. The,~irection of the'i.n 1/0 lines are controlled by four 8-bit
. Pllrt:refjlste~.10Cat89inl'8lle~ero. This arrang~m~. pro,:,
\lidts qiJ~ PragraJtlr11i~g 'acce~ using simple~·I;1~ Z$~ ..
page address i~ions.·The~ .are no dl.rection, reQIste!l$ .. , '
a!I~oc::iat~I'!I'!Iithithe'I/O pOr1s,thus simplify,ngll0 handling.
The"VO.addresseS ar'!!l. shown in Table 4-1. Appendix EA'
stiows the i/O.PQrtTimlng. "
' •.~, .'
...20tlTPUTs
olItp~~,~or Potts . " thru, '.C arl! controlleci. by ~ritill$ltl1e
.... desired I/O !ineoutpUt lltates into. the. ,cO(resP9ndir)!;j 1/0 port
'iregi~tel'bit po$lijons,··"...I&gic 1"'wiH'f,~a .high (>~.4v)
output,lfihilsa i(jQic '0
force a low «0.4V) output. .,.,
will
Tllbl. "·1.
Port
110 Port Addr......
4.3 Port A (PA)
AD"RES$ .
. PORT
OOOO'~:
Port. A can be programmed via the Mode Control'Flegister
(MCR) .and the" Selial Communications Control Register
(SCeR) 8!; a standard p!lralleI8~bit, bit ind"pendent, I/O Port
or as serial' qhannel.I/O lines, counter 1/0 lines, or an input
data strobe for tile port' B input latch option: Table 4-2 tabulates the control and usageofPtmA.
.'
0001"
0002
0000
_,.;,·i,"!,
4.1 'INPUTS,
oall ;6utP(Jts is,¢8IeCtedby
setting
MCR5 to a "1",
. .
..
~,.
In addition to their normal 1/0 functions~ 'PAO and PA1 can
detect. positive going edges and PA2 and PA3can detect
negative going edges. A proper transHion on these pins will
set a corresponding status bit In the IFR and generate an
.' interrupt request if the ~SpeCtive Interrupt Enable Bit is set.
the maximum rate at which an edge can be detected is one·
.half the
clock rate. Edge detection timing is shown in Appendix E.3.
!.-'
Inputs for Ports A, B. and C are enabled by loading logic 1
into all I/O port register bit positions that are to correspond
to 110 input lines. A low «0.8V) input signal will cause a logic
o to be relli:! when a read instruction is issued to the port.
register. A high (>2.0"> input will cause !!Jogic 1to be rea\!.
An RES signal forces a\I:I/O port registers to logic 1 thus
initially treating all 1/0 lines as inputs.
P2
3-84
R6SG.1Q
One-Chip Microproce$sor
.Table 4.2~
Port A ,Control and Usage
PAa I/O
POI'IT B LATCH MpDE
MCR4 = a
MCR4 = 1
SIGNAL
PAO(21
PIN 39
SIGNAL
"
NAME.
TYPE
NAME
TYPE
PAa
1/0
PORTB
LATCH STROBE
INPUT (1)
PA1-PA31/0
PA1 (2)'
PIN 38
PA2(3)
PIN 37
PAS (3)
PIN 36
,
SIGNAL
NAME
TYPE
PAl
PA2
PA3
1/0
II
I/O
I/O
>,
COUNTER A 1/0
PA41/0
PM
PIN 35
MCRa = a
MCRl = 0
seCR7 = a
RCVR SIR MODE = a
(4) (5)
MCRa = 1
MCRl = a
seCR7 = a
RCVR SIR MODE = a
(4)
SIGNAL
seCR7 = a
seCRS = a
MCRl = 1
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
NAME
PA4
I/O
CN:rA
OUTPUT
CNTA
I
I
TYPE
INPUT (1)
SERIAL I/O SHIFT REGISTER 9LOCK
seCR7 = 1
SCCR5 = 1
RCVR SIR MODE = 1
(4)
SIGNAL
I
NAME
XMTR CLOCK
I
SIGNAL
I
TYPE
NAME
OUTPUT
RCVRCLOCK
TYPE
I
INPUT (1)
i
PAS I/O
COUNTERBI/O
MCR3 = a
MCR2= 1
M9R3 = 0
MCR2 = a
.PAS
PIN 34
SIGNAL
.,
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
NAME"
PAS
I/O
CNTe
OUTPUT
CNTB
PA6.
PIN 33. ..
PAellO
SERIAL I/O
XMTR OUTPUT
SeCR7" a
seCR7 =1
SIGNAL
NAME
I
PAS
PA7
PIN 32
SIGNAL'
TYPE
NAME
I/O
XMTR
TYPE
I
OUTPUT
PA71/0
SERIAL 1/0
RCYRINPUT
secRe = 0
SCCRe = 1
SIGNAL
.
MCR3 = 1
MOR2 = X
I
I
TYPE
.INPUT (1)
(1)
(2)
(3)
(4)
HARDWARE 'SUFFER FLOAT
POSITIVE EDGE DETECT
NEGATIVE E~E bETECT
ACVR SlRMOOE = 1 WHEN
. SecR.e.· SCCR5 . seCR.! = 1
(51 For the followin!! mode Cbmbi. nations PA4 is available as an
Input Only pin:
SCCR7'SCCR60SCCR5oMCRl
+seCR7oSCCR~CRl
+SCCR7oSCCR6oSCCR5
+ ScCR7·SCCRSoSCCR40
SIGNAL
NAME
TYPE
NAME
TYPE
PA7
I/O
RCVR
INPUT (1)
R6.501Q
o.ne-Chip Microprocessor
4.4 PORT B . (PB)
4.5 PORT C(PC)
Port B can be programmed as an 8-bit, bit-independent I/O
port. It has a latched input capability.which may be enabled
or disabled via the Mode Control Register (MCR). Table
4-3 tabulates the control and usage of Port B. An Input Data
Strobe signal must be provided tI"\ru PAO when Port B is programmed to be used with latched input option. Input data
latch. timing for Port B is shown in Appendix E.3.
Table 4-3.
31
30
29
28
21
26
25
24
PBO
PB1
PB2
PB3
.PB4
PBS
PB6
PB1
Port D can be programmed as an I/O Port. Mode selection
for Port 0 is made by the Mode Control Register (MeR). The
Port 0 output drivers can be selected as tri-state drivers by
setting bit 5 of the MeR to 1 (one). Table 4-5 shows the f1.E1cessary settings for the MCRto achieve the various modes
for Port O.
LATCH
MODE
MCR4 = 1
MCR4 = 0
PIN
NAME
4.6 PORT D (PD)
Port B Control & Usage
110 MODE
PIN
#
. Port C can be programmed as an I/O port, or as part of the
full address bus. When 9perating in the Full Address Mode
PC6 and PC? serve as At3 and A 14 with peO-PC5 operating
as normal I/O pins.
(2)
. SIGNAL
NAME
PBO ..
PBl
PB2
PB3
PB4
PBS
PBB
P81·
4.7 BUS MODES
SIGNAL
TYPE
(1) "
NAME
TYPE
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VO
1/0
1/0
1/0
110
1/0
110
110
.
In the Full Address Mode, the separate addreSs and data bus
are used in conjUnction with PC6and PC?,which automatically provide A 13 and A14. The remaining ports perform the
normal I/O function.
In the I/O Bus Mode all ports serve as I/(). The address and
data bus are still functional but without A13and A14:: Since
the internal RAM and registers are in the OOXX location, A 15
can be used f~rchip select alid AO-M2 used for selecting
.8Kof external memory.
.
.
(1) ReSISTIVE PULL-UP, ACTivE BUFFER PULL DOWN
(2) INPUT DATA IS STORED IN PORT B LATCH BY PAOPULSE
.err, .....)
KTLO
PORT'
8-BrrS
v,, _ _ _
v••
)
8-IITS
v..
.""
I>OATB
.....
)
v." _ _ _
......,~
v.. _ _ _
......,~
...
, -_ _yo:)
Re511Q OR RHIIOIU
RUllQOR RUClDJ13
PORTA
-----;~
...---......,~
PORTe
)
......,~
pOATe
""
.....
••/TS
PORTD
PORT D
'<"
"13 Pet)
.",P(:7)
'iii
12·
""
SYNC
[ACTIVE
FROM]
OOO
,~
EIrNk .
DEX
X l_X
Y 1....... '1'
EOR
AW-,oA, It!
M·l--M
lSR"
:~
SEC
~se(J
SEI
5MB[#(O-7)]
SfA
STX
STY
3l
3
CS
E4' l312
3
•
C4 3
~
C6
l ' -1·
\ 1 Iso7.
•
N
N
N
N
5
M~C-A
N •
0 • •"
3
A5
3
AS
TYA
3
3
o • • • • •'
. ......Z C
05 3 2
N • • • • -. Z
N ••••
26
66
071 17J 27 \ 37
'1
\471
5'\
67 \,,\
2
2 \'
5'21
52_6A21
I
Est 3 I 2'
z
\-N
r \
Y...... A
85l·12
86 3
84
941 41
3
,. ,-
I
page.boimary ".·oroosad'-
2. Add-' 10 N if branch-qccurs rO-'s'amepage
Add-2 to fq if branch oCcurs)rHt~.nfPage
3. Carry 1101= Borrow
4, If in decimal mode Z'flag--is_lnvafid
accumulator mu~
ctiecktid con ,zero r8S:0lt.
5. ,EIIecIs 8-bi' dlol8.field of 'he
poge~.
b.e
specmed .e'"
98
-
::I;
1
cp
(')
.':/'
901412
N
N
N
2-11
Z
Z'
X
Y
A-
M
M.
M"
M,
M,
: l0\d8xX
<
IndOxY
Accumulator
foAeInooy per effective addnis.
~jlOo'stad< pcIroIaJ •
... ' Sitlecter Zero page memory bit
Memory Bit 7
.
n...
ZoO,
N·
UGo?Nc!
if
i:'
Z·
Z
N
2
8A 2"
9A- ~:
.
o
z (31
V
2
AAj.2.n
SA 2
·AS
C
Z C
(ResOo""'1
67 I 97 I AT 181 IC71 071 E7 IF7
(5-)
'.2
IAesI"""'1
~
N -
c:.c
•
(1)
Z
z
N ••••• Z
2' 4Ai 21 1
.
x-50
NOTES
1. Add 1 to N ff
••
6CI513IB1UIIIIIIII~~~~~~~
3
3 " A4- 3
--3 46 5-
1-0
1_T
A=--i.V.
"S-+X
X-A
•• 0
- 0
D." • . • •
\ • • • _. Z C
• ':' •.• -. Z C
• • • • ··Z·C
••••• Z
l-C
TAY
TSX:
TXA
•
N ••••• Z
N •• ~ •• Z
N ••••• Z
Rtn1 Sub
t"":Mb
Z
N • '.- • • •
~
Rlrn Int
.
TAX
n.8
\
413_1
45 t 3 12
S E6
(1)
~o_ Operation
A...... M
X-M
Y-M
A-X
••
-. --,
--
·6
O-.cc:::::JU ~ C
A
FF
10:-
AVM-A (t)PHA
A-Ms - S - 'l~S
PHP
P-Ms S l--;S:
PLA S-1-S· Ms--A
PLP
S~1-S Ms--P
,.RM8(N(O-7I1 O-M, (5)
rot
Rts
sac
&F 9F ",'BF~n ~16TF
EF
I:
OFlfFrl
M,.M; ...;
\
~CE 16
X·l---X
Y·,· ..... V
NOP
ORA
Z
Z C
DO
C022CC
Jump to NeW Lac .
Jump Sub
M---+A (1)
M--o-X (1)
M_V
Z C
.
FO
Ico,2.,2ICDI4
.eO_ 2- _2' EC
JMP
LOA
N
Z C
o -
INX'
INY
LOX
lOY
B Q '
Y-
N V
CF OF
e
I7 6 5 4 3 2 1 0
I 41 • I • I , IN
N - - • - - Z
INC
JSR
3
30
OCH7 tl
M (1)
M
M
1......l1li
DEY
I
eo
Il--..v
A
X
Y
M
2
2cl.4I,I·2413Iz
Branch on Z '" 0
Branch on N == 0
"CPX
I
N'"
.
(21
Br~onN=-'
(2)
(2)
(2)
ave
1
21'7514121'014'13179\413
2. 35 4 2 39 4 3 39. 4 3.
BBR[#(J-t)1 Branch on M."'o- (51(2i
B88(#(0--'7)) Branch qn M,,~1 (5}{2)
BRK
BIT ADDRESSING lOP BV BIT #)
'clOprn \ ~ lop 1" I-\opl' n I ill OPJ " I #'Iop1 nl. IOPI nJ # lop I n I_ lop I n I. lopl " I .. I OPI n I • .·1
OPE.RATION
@:
.-
P8OCESSOA STATUS
CODES
ENHANCED R6502 INSTRUcnoN SET
. iNSTRUCTIONS
0
: MamoryBitS,
. :: Add
_rae!
•.'
:
And
V
...
n"
#.
:
"
:
:
Or
'~"
...
0
n
CD
Exclusive Or
Number Oh:ydes
Number oI8y1es
.,
"
m'
0'1
ED
-"'"
One~Chip
R6501Q
Microprocessor
A.3 INSTRUCTION. CODE MATRIX
o
BRK
Implied
1 7
O.
o
LSD
;g
o
0
2
BVC
6
7
Rela~ve
EaR
(IND), Y
2 ,2"
2 5'
RTS
ADC
Implied (IND,X)
1 6
2 6
BVS
ADC
Relative (IND, y)
2 2"
2 5'
2 6
9
A
BCC
STA
Relative (IND.Y)
2 2"
2 6
LOY
IMM
LOA
(IND. X)
2 6
2 2
B
C
BCS
LOA
Relative (IND), Y
2 2"
2 5.'
CPY
IMM
2 2
o
E
LOX
IMM
2 2
CMP
(IND, X)
2 6
CPX
SBC
IMM ' (INO,X)
2 6
F
2
3
3 4'
ROL
ABS,X
3 7
EOR
ABS
3 4
LSR
ABS
B8R4
ZP:,
3 6,
3 5"
2 4
ROL
Zp, X
2 6
RMB3
ZP
2 5
SEC
Implied
1 2
EaR
ZP
2 3
LSR
ZP
25
RMB4
ZP
2 5
PHA
eOR
Implied·; IMM
;2 2
1 3
EOR
ZP;X
2 4
LSR
ZP,X
RMBS
ZP
2 6
2 5
AOC
ZP
ROR
ZP
RMBS
ZP
2 3
25
2 5
ADC
ZP,
ROR
ZP, X
RM67
ZP
2 4
2 6
2 5
5MBO
ZP
2 3
2 3
25
STY
ZP. X
STA
Zp.X
STX
ZP, Y
5MB!
ZP
2.4
2 4
2 4
LDY
ZP
2 3
LOA
ZP
2 3
LOX
ZP
2 3
LOY
Zp, X
2 4
LOA
ZP,X
2 4
CPY
ZP
'CMP
ZP
2 3
4
AND
ABS, X
3 4'
AND
IMM
2 2
STX
ZP
BEQ
SBC
Relative (INO). Y
2 2"
2 5'
AND
ABS, Y
PLP
;Implied
1 4
STA
ZP
CPX
ZP
2 3
2 2
BBR2
ZP
3 5"
RMB2
Zp
2 5
STY
ZP
2 3
BNE
CMP
Relative (INO),Y,
2. 2"
2 5'
ROL
ABS
3 6
ROL
ZP
2 5
x
STA
(IND. X)
AND
ABS
3.4
ORA
ABS,Y
2 6
CLC
Implied
1 2
AND
ZP, X
..
BBR1
l';P
35"
RMB1
ZP
2 5
AND
ZP
2 3
RTI
EOR
Implied (IND, X)
f 6
2 6
AS.L
ABS, X
3 7
2 2
ASL
ZP, )(
..
ORA
ABS, X
3 4'
1 3
ORA
ZP,X
24
BMI
AND
Relative (IND, Yl
2 2"
25'
F
BBRO
ZP
3 5"
Implied
BPL
ORA
ReiJItiv9 (IND), Y
2 2"
25'
3
E
ASL
.ABS,
3 6
A
ASL
Accum
1 2
RMBO
ZP
2 5
BIT
ZP
2 3
o
ORA
ABS
3 4
9
ORA
IMM
6
ASL
ZP
2 5
2
5
4
ORA
ZP
2 3
'JSR
AND
Absolute (IND,)t)
3 6
2 6
4
3
BRK
ORA
Implied (IND,X)
I 7
2 6
PHP
eLi
Implied
I 2.
PL~
Implied
1 4
-OPCode
-Addressing Mode
-Instruction Bytes; Machine Cycles
B
C
3 4'
ROL
Accum
1 2
BIT
ABS
3 4
JMP
ABS
3 3
LSR
Accum
1 2.
I
EaR
ABS', Y
34'
EOR
LSR
ABS, X ABS,X
3 7
3 4'
I
ADC
IMM
ROR
Accum
2 2
1
JMP
Indirect
3 5
2
SEI
ADC
Implied ABS, Y
1 2
3 4'
DEY
Implied
1 2
ADC
ABS
34,
AOC
ABS.X
3 4'
STY
ABS
TXA
Implied
I 2
3 4
STA
ABS
3 4
2 5
STA
ABS. Y
3 5
TXS
Implied
1 2
5MB2
ZP
2 5
TAY
Implied
1 2
LOA
IMM
2 2
TAX
Implied
1 2
LOX
ZP,Y
2 4
5MB3
ZP
2 5
CLV
Implied
1 2
LOA
ABS, Y
5MB4
ZP
INY
Implied
1 2
CMP
IMM
2 3
DEC
ZP
2 5
CMP
ZP,X
DEC
ZP,X
5MB5
ZP
2 4
2
e
2 5
CLO
Implied
1 2
SBC
ZP
2 3
INC
ZP
2 5
5MB6
ZP
INX
Implied
1 2
SBC
IMM
2 2
SBC
Zp.X
2 4
INC
Zp.X
2 6
5MB7
ZP
SED
Implied
1 2
SBC
ABS, Y
SBC
ABS, X
3 4'
6
7
2 5
2 5
3.5"
B.BR6
ZP
5"
STX
ABS
BBSO
ZP
3 4
3 5"
BBR7
ZP
BBSI
ZP
3 5"
LOY
ABS
LOA
ABS
LOX
ABS
BBS2
ZP
3 4
3 4
3 4
3 5"
LOY
LDA
ABS. X ABS,.X
3 4'
LOX
ABS,Y
3 4'
3 5'!'''"
CPY
ABS
CMP
ABS
DEC
ABS
B6S4
ZP
3 4
3 4
3 6
3 5"
CMP
ABS,Y
CMP
ABS, X
BBSS
ZP
3 4'
3 4'
DEC
ABS. X
3 7
2
2
9.
Implied
1 2
OEX
Implied
1 2
CPX
ABS
34
NOP
Implied
1 2
A
B
C
BBS3
ZP
A
B
C
o
3 5"
SBC
ABS
INC
ABS
BBSS
ZP
3
3 6
3 5"
3 4'
INC
ABS,X
3 7
3 5"
o
E
F
,4
6
3
3 4'
3 4'
4
BBRS
ZP
3 5"
3 5
rsx
BBR3
ZP
5"
3
ROR
ABS, X
3 7
STA
A.BS.X
TYA
Implied
1 2
2 5
ROR
ABS
3 6
o
BBS7
ZP
E
F
'Add 1 to Nlf page boundary is crossed.
"Add 1 to N if branch occurs to same pag\!;
add 2 to N if branch occurs to different page.
3-96
'R6501Q
APP,ENDIX S.
KEY REGISTER,SUMMARV
7
0
I
0
7
0
I
,.
7
~:,. 4
I ',INDEX AEGISTER Y
1
.. ,'. 2
D, [
I
0
I z I cJ
CARAVICl(j)
0
I
PCH
• •
I ," IV I I • I
I tN~EX, REGISTER JC
I
I
7
I ACCUMULATOR
7
I. PROGRAM COUNTER
PCL
7
;
1 = Carry $M,l,
O.=C.rryC,e-.r
0
I
Sp
I STACK POINTER
T
0
INlvl 1.1 D II I-Ic I .""CESSO.STATUSAEO
ZEAOIZl(j)
1 =Ze,oAoun
o = Non.z.fD RHUIt
,
'
,'I
INTERRU~T O!'SA!3LE tll
CPU Registers
CD
1 '" "."Int~pt DiSlbled
o :~ iRQ l"terru'pt En"bled
DECI~~L ~,OOE (D) CD
1 -::;; [)ec:i~,1 Mode
D=$inaryMoc:le
BREAK COMMAND'(B)
CD
1 = Brelk COMmand
o = Non 8,..11. Command
OVERFL.OW (0) (j) .
1
-= Ovetilow Sel
0== Overflow Clear
NEGATIVE (Ill)
CD
NOtES
Add, 0014
MCR
Pr()Cessor Status' Register
aunt., A
I I
Mode Select
0 - 0 Interval Timer
0 - 1 Pul.. o.ner.UO,n
,
1 _ 4 Event Counter
1f P\lIMi Wldltl Mel•.
0 - 0 IntttVal Tim...
a - 1 ' ASymmetric Pulee Generation
1,-0 E\ttnt eoun_
1 -:--, RfCt'tgger,bile lnterval Timer
Sus Mode hl"t
IFR
Port'OT~"
Addr 0011
I~R
Addr OO,:;!
~~~~~,r~~~r
...... Latch
(1""Enab'-)
.,',
., ;;;;: Negative V,lue
D= Po.til". VII",.
(j)NotinitiIIlHclbYi!iE'S
(!) Set lo'Loglc 1 by ~
,P,ADPOf,itive
EiIg';~
",
(o--T........ Hlghl.. _ _ 1
I:tA 1 ,Po_illve
Edge Detect,
PAZ N~.tIYe
Edge Detect,
PA3 Neiative '
.-·-0 Full Addrea
~"_"
1--0 No\ Uad
,--'1
Not UMd
Edg.~ect
Mode Control Register
COuMerA
UndorflawFlog
COumo,B
ReVR ,Unclorft"", Flog
FliIg
XMTR
Flog
Interruptj:nable and Flag Register.
Addr 001$
"~;Do1" ,"'..
$CSR
O.,..odd Pority
1......Even Parity
o".rlty Disable
1'Pority En.bl.
o
o
I
I
0-8 Blto/Cho'
1 _1 Bllo/Chor
Parity Error
0, - 6 BIt"Chor
1 _'5 Bllo/Cho.
0-:--0 XMTR 8'RCVRASYN Mod.
Frame
o.,.-; 1:,XMTR ASYN. RCIIR SIR
~rror
·W'ke-Up
'-XXMTR'SIR. ReVR ASVN
E'nd of Transmls.ion
Q ReVA, DiAblo
,!lCYR EMbl.
XMTR
o XI!TR Dlolbio
lC:1ITR
IXMTREnoblo
Serial Communications Control Register
Data Reg ~pty
Un~Flun
Serial,Communicstions Status Register
3-97
One~Chip
R6501Q
Microprocessor
APPENDIXC
ADDRESS .ASSIGNMENTS/MEMORY
MAPS/PIN FUNCTIONS
C.1 1/0 AND INTERNAL REGISTER ADDRESSES
ADDRESS
--
I,
00lF
lE
lC
Upper Latch e, Cntr B~Latch 'B, CLR Flag
Upper Latch B, Latch C-Latch B
lower latch B.
--
'·lB
lA,
1!1'
18
--
Lower Courrter, e
Upper Counter e
lower Counter, e, ClR Flag
10
"
WRITE
READ
(I1EX)
'/
.'
--
'lower Counter A
Upper Counter A .'
low~r Counter. A, ClR Flag
.
Serial Receiver Data Register ,Serial Comm,'Status Register
Serial Comm, Control F\egister'
ModEi Control Register
17
16
15
'14
, --
13
12
11
0010
Upper latch A, Cntr A~latch A, ClR Flag
Upper Latch A
lower latch A
Serial Transmitter Data Register
Serial Comm, Status, Reg. Bits 4 & 5 only
Serial. Comm. Control Register.
..
Mode Control Register
---
":
Interrupt Enilble Re!!lister •...
Interrupt Flag. Register
Read FF
Interrupt enable Register
Clear Int Flag (Bits 0-3 only, Write O's only)
OF
OE
00
OC
RESERVED
OB
OA
09
08
07 .
06
These addresses are rese(Ved and are used by the CPU during Read and Write
operation over the external Data Bus (00-07).
.'
05
04
03
02
01
0000
PortO
PortC
PortB
PortA
Port 0
PortC
Port B
PortA
3-98
r--to--
,.,'
"
R6501Q
One-Chip. M. icroproces$or
'"
C.2 FULL ADDRESS . MoDE
MEMORY MAP,
R$501Q'
'FFE
IRQ VECTOR
FFFC
RES VECTOR
FFFA
NMIVECTOR
..
'
USER PROGRAM
OOF.
INTERNAL RAM (192)
I
0040
RESERVED
001 F
0000
I
I
/
/
I
/
/
/
/
/
/
I
001'
/
INTERNAL
REQISTERS
001.
OOOF
RESERVED
I
~
I
0003
1/0 PORTS A, B. C, 0
I/O & REGISTERS
0000
C.4 MULTIPLE FUNCTION PIN ASSIGNMENTS
.
-'-PORT C AND PORTO
FULL' ADDRESS
MODE
PIN
NUMBER
1/0 PORT
FUNCTION
54
pco
pco
55.
56
57
PCl
PC2
PC3
PC1.
PC::!
PC3
58
59
60
61
PC4
PC5
A13
A14
62
63
64
1
POO
POl
P02
P03
PC4
PC5
PC6.
PC7
POO
pm
P02
P03
P04
PQ5
P06
P07
P04
P05
PD6
P07
2
3
4 .
5
.
:3-99
.
-~
,"
,',
,
'"
R650.1Q
One-Chip Microprocessor
APPENDIX D
ELECTRICAL SPECIFICATIONS
Maximum Ratings
RATING
Supply Voltage
VALUE
UNIT
Vee & VRR
-0.3 to +7.0
Vdc
Vi'
-0.3 to +7.0
Vdc
SYMBOL
.Input Voltage
...
Operating Temperature Range, Commercial
'c
'Oto+70
T stg
Storage Temperature Range
'c
-55 to +150
..
NOTE: This.device contains circuitry to protect the inputs against damage due to high static voltages; however, It IS advised that normal
precautions betaken to avoid application of any voltage higher than maximum rated vo~ages to this circuit.
DC Characteristics (Vee - 5V +5%' V RA - V ee,. V 55 -- O' TA - 0 to 70°C)
CHARACTERISTIC
SYMBOL
Power Dissipation (Outputs High)
Commercial @ O°C
MIN
-
Po
TYP
MAX
UNIT
750" 1
1100
mW
.
3.0,··.
RAM Standby Voltage (Retention Mode)
VRR
RAM Standby Current (Retention Mode)
Commercial @ 25'C
IA.
Input High Voltage (Except XTU)
V ,H
+2.0
Input High Voltage (XTLI)
V,H
+4.0
V"
-0.3
-
Vee
•
Vdc
mAdc·
-
4
-
-
Vee
Vdc
-
Vee
Vdc
-
+O.B
...
Input Low Voltage
Input.Leakage Current (RES, NMI)
Vi" = 0 to 5,0 Vdc
lIN
Input Low Current PA, PB, PC, PO
(V" = 0.4 Vdc)
I"
Output High Voltage (Except XTLO)
(I"" ~ .100 ",Adc)
V OH
Output Low Voltage
(1'00' ~ 1.6 mAde)
Input Capacitance
(Vi, -0, T. = 25'C, f
xnl, XTLO
All Others
VOL
= 1.0 MHz)
I/O Port Pull-Up Resistance
PAQ-PA7, PBO-PB7, PCO-PC7
Output Leakage Current
Tri-State I/O's while in
High Impedance State
Output Capacitance
Tri-State I/O's while in
High Impedance State
V,N =OV, TA = 25'C, f = 1.0 MHz
+2.4
-
Vdc
;:10.0
/LAdc
-1.6
mAdc
-
Vee
Vdc
-
+0.4
Vdc
-1.0
pF
C"
-
-
R,
3.0
6.0
11.5
Kfl
lOUT
-
-
;:10
",Adc
-
-
C OUT
.NOTE: Negative sign indicates outward current flow, positive indicates inward flowe
(1) at 25°C
3-100
50
10
10
pF
On.C~lp·MicrC)prO¢e,s.br
R6!i01Q
. 'APPENDIX E'
''1
TIMING REQUIREMENTSANDCHARACTERISTIOS
"'.
,
E.2
E.1 GENERAL.NQTES
.
,
.CLtiCK TIMING
1. Vee = 5V ±5%,OOC"; TA.,;.?O°C
SYMBOL
2. A valid Vee -RESsequenceisrequired before proper
operation is aChieved.
P~RAMETER
MIN
MAX
500
1.0 p.s
·Tcyc
CYcle Time
1000
10.II-S
unless
,TpWX1
XTLI Input Clock
Pulse Width
l
1.5V
0
STROll
.... TpLSU
~
..
',.!lV
Tp8lW
3-102
-I
. - Tp8lH
One-Chip Microprocessor
R6501Q
E.4 MICROPROCESSOR TIMING (00-07,
AO-A 12, A15, SYNC, R/W)
SYMBOL
PARAMETER
1.MHz
2 MHz
MIN
MAX
MIN
MAX
T Rws
R/W Setup Time
-
225
-
140
TAos
AO-A12, A15 Setup
Time
-
150
-
75
T D5U
DO-D7 Data Setup Time
50
-
35
-
THR
DO-D7 Read Hold Time
10
-
10
-
T Hw
DO-D7 Write Hold Time
30
-
30
-
T MOS
DO-D7 Write Output
Delay
-
175
-
130
T SYN
SYNC Setup
-
225
-
175
THA
AO-A12, A15 Hold Time
30
-
30
-
THAW
R!W Hold Time
30
-
30
T ACC
External Memory Access
Time TAce = T CYC-T F TAOS-Tosu
-
T SYH
SYNC Hold Time
30
TACC
7""
-
30
T ACC
-
E.4.1 Microprocessor Timing Diagram
WAITE
READ
_THRW
RrW
TOSU _______
TMOS
DATA 0DATA 7
_ _ _ THR
SYNC
3-103
R6500/1
R6500 Microcomputer System
'1'
Rockwell
R6500/1
ONE·CHIP MICROCOMPUTER
SECTION 1
INTRODUCTION
The Rockwell R6500/1 microcomputer is a complete 8-bit
computer fabricated on a single chip using an N-channel silicon gate MOS process. The R6500/1 complements an
established and growing line of R6500 products and has a
wide range of microcomputer applications,
FEATURES
•
•
•
•
•
•
•
•
The R6500/1 consists of anR6502 Central Processing Unit
(CPU), 2048 bytes of Read Only Memory (ROM), 64 bytes of
Random Access Memory (RAM) and interface circuitry for peripheral devices.
•
•
•
The innovative architecture and the demonstrated high performanceof the R6502 CPU, as well as instruction simplicity, results in system cost-effectiveness and a wide range of
computational power. These features make the R6500/1 a
leading candidate for microcomputer applications.
•
•
•
•
•
•
To faci.litate system and program development for the
R6500/1, Rockwell has developed an R6500/1 E Emulator
part. A description of the R6500/1 E is contained in Appendix D.
•
•
•
This product description is for the reader familiar with the
R6502 CPU hardware and programming capabilities. A
detailed description of the R6502 CPU hardware is included
in the R6500 Microcomputer System Hardware Manual
(Document Number 29650N31). A description of the instruction capabilities of the R6502 CPU is contained in the
R6500 Microcomputer System Programming Manual (DOCUment Number 29650N30).
•
•
Document No. 29650N48
3-104
Single-chip microcomputer
R6502 software compatible
Eight-bit pan~lIel processing
DeCimal or binary arithmetic
Variable lengt~ stack
True indexing capability
Thirteen addressing modes
1 or 2 MHz clock operation, with the following options:
- External single clock input
- RC time base input
- Crystal time base input
Single + 5V power supply
500 mw operating power
Separate power pin for RAM with standby power only 10% of
operating power
2K x 8 ROM on chip
64 x 8 RAM on chip
40-pin dual in-line package
64-pin Emulator part available, with 40 signals identical to
production part
Pipeline architecture
32 bidirectional TTL compatible 1/0 lines
- 1 positive edge sensitive 1/0 line
- 1 negative edge sensitive 110 line
1 bidirectional TTL compatible counter 1/0 line
16-bit timer/counter
Four timer/counter modes
- Internal timer
- Pulse generator
- Event counter
- Pulse width measurement
Three maskable interrupts
- 1 counter overflow
- 2 I/O edge detect
NMI and Reset interrupts
Product Description Order No. 212
June 1979
R6500/1
One-Chip Microcomputer
SECTION 2
R6500/11NTERFACE REQUIREMENTS
configuration and Table 2-1 describes the function of
pin of the R6500/1.
This section describes the interface requirements for the
R6500/1 . single chip microcomputer. Figure 2-1 is the Interface Oiagram for the R6500/1. Figure 2-2 shows the pin out
XTLI
VRR
P07
PD6
PD5
PD4
PD3
PD2
PDl
PDO
XTLI
XTLO
XTLO
8::>PAO-PA7
VCC
8:> PBD-PB7
vss
VRR
vss
8:::> PCO-PC7
PC7
PC6
PC5
PC4
PC3
PC2
PCI
8:::> POD-P07
/4-+CNTR
NMT
RES'
10
11
12
15
16
19
pco
Figure 2-1. R6S00/1 Interface DI,~gram
e~ch
21
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
VCC
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
CNTR
Figure 2,"2. R6S00/1 Pin Out Designation
Table 2-1.R6S00/1 Pin Description
Signal Name
Pin No.
Description
VCC
30
VRR
1
VSS
12
Signal and power ground (OV)
XTLI
10
Cryslal, clock or ~C network input for internal clock oscillator.
Main power supply+SV
Separate power pin for RAM. In the even! that VCC power is lost, this power' retains
RAM daia.
XTLO
1
RES
39
-NMI
40
A negative going edge on, the Non-Maskable Interrupt signal requests that ,a non·,
rnaskable interrupt be generated within the CPU,
38-31
29-22
20·13
9-2
Four 8-bit ports u$ed for either input/output. Each line consists of an active transistcir to
VSS and an optional passive pull-up to VCC. The two lower bits of the PA port
(PAD-PAl) also s9i'Ve as edge detect inputs with maskable interrupts.
21
This line is used as a Counter input/output line. CNTR ,is an input in the Event Counter
and Pulse Width Measurement modes and is an output in the Intervel Timer end Pulse
Generator modes. It ,consists of an active transistor to VSS and an optional PBS$ive
pull-uptoVCC.
PAO·PA7
PBO-PB7
PCO·PC7
PDO-PD7
CNTR
Crystal orAC network output from ..internal clock oscillator.
The Reset input is used to initialize the R6500/1. The signal must not transition from low
to high for at least eight cycles after VCC reaches operating range and the internal ascii.
lator has stabilized (see section 5).
+ 10V inpui enables the test mode.
3-105
D
R6500/1
One-Chip Microcomputer
SECTION 3
SYSTEM ARCHITECTURE
This section provides a functional description of the R6500/1.
A block diagram of the R6500/1 is presented in Figure 3-1 .
either user instructions or the interrupt lines NMI and IRQ.
The Stack Pointer must be initialized by the user program.
3.1 INDEX REGISTERS
The stack allows simple implementation of multiple level
interrupts, subroutine nesting and simplification of many
types of data manipulatidn. The JSR, BRK, RTI and RTS
instructions use the stack and Stack~ointer.
.
,
~!
,
There are two a-bit index registers, X and Y. Each index
register can be used as a base to modify the address data
program counter and thus obtain a new address - the sum
of the program counter contents, and the and the index register contents.
,
The stack can be envisioned as a deck of cards which may
only be accessed from the top. The address of a memory
location is stored (or "pushed") onto the stack. Each time
data are to be pushed onto' the. stack, the Stack Pointer is
placed on the Address Bus, . data are written. into the memory location addressed by the .Stack Pointer, and the Stack
Pointer is decremented by 1. 'Each time data are read (or
"pulled") from tt)e stack, the Stack Pointer is incremented
by 1. The Stack Pointer is then placed on the Address Bus,
and data are read from the memory .location addressed by
the Pointer.
.
When executing all. instruction which specifies indirect
addressillg, the CPU fetches the op code and the address,
and modifies the address' from memory by adding the index
register to it prior to loading or storing the value of memory.
Indexing greatly simplifies many types of programs, especially those using data tables.
3.2 STACK POINTER
3.3 ARITHMETIC AND LOGIC UNIT (ALU)
The Stack Pointer. is an a-bit register. It is automatically
incremented and. decremented under control of the microprocessor to perform stack manipulation in response to
All arithmetic and logic operations take place in the ALU,
including incrementing and decrementing internal registers
Figure 3-1. R6500/1 Block Diagram
3-106
One-Chip Microcomputer
R6500/1
(except the Program Counter), The ALU caMotstore data
for more than one cycle. If data are placed on the inputs to
the ALU at the beginning .of a .cycle, the result is always
gated into one of the storage registers or to external memory during the next cycle.
3.9 CLOCK OSCILLATOR
The Clock Oscillator provides the basic timing signals used
by the R6500/1 CPU. The reference frequency is provided
by an external source, and can be from a crystal, clock or
RC network input. The RC network mode is a mask option.
The external frequency can vary from 200 kHz to 4 MHz.
The internal Phase 2 (1Il2) frequency is one-half the external
reference frequency. Figure 3-2 shows typical connections.
Each bit of the ALU has two inputs. These inputs can be
tied to various internal buses or to a logic zero; the ALU
then generates the function (AND, OR, SUM,and so on)
using the data on the two inputs.
3.4 ACCUMULATOR
XTLI
The accumulator is a general purpose a-bit register that
stores the results of most arithmetic and logic operations. In
addition, the accumulator usually contains one of the two
data words used in these operations.
2·4MHz
R6500/1
XTLO
3.5 PROGRAM COUNTER
a. Crystal Input
The 12-bit. Program Counter provides the addresses that
are used to step the processor through sequential instructions in a program. Each time the processor fetches an
instruction from program memory, the lower (least significant) byte of the Program Counter (PCl) is placed on the
low-order bits of the Address Bus and the higher (most significant) byte of the Program Counter (PCH) is placed on
the high-order 4 bits of the Address Bus. The Counter is
incremented each time an instruction or data is fetched
from program memory.
vce
3.6 INSTRUCTION REGISTER AND
INSTRUCTION DECODE
b.
Instructions are fetched from ROM or. RAM and gated onto the
Internal Data Bus. These instructions are latched into the Instruction Register then decoded along with timing and interrupt signals
to generate control signals for the various registers.
C lock Input
R~4.7Kn
(NOMINAL)
(2MHz EXCITATION
FREQUENCY)
3.7 TIMING CONTROLS
The Timing Control logic keeps track of the specific instruction cycle being executed. This logic is set to TO each time
an instruction fetch is executed and is advanced at the
beginning of each Phase .One clock pulse for as many
cycles as .are required to complete the instruction. Each
data transfer which takes place between the registers is
caused by decoding the contents of both the instruction register and timing control unit.
c. RC Network Input (Mask Option)
NOTE
(1)
(2)
c IS PROVIDED INTERNALLY BY THE R6500/1.
THE RC OPTION IS AVAILABLE ONLY ON THE
1 MHz R6S00/1.
Figure 3-2, Clock O.scllletor Input Options
3.8 INTERRUPT LOGIC
3.10 PROCESSOR STATUS REGISTER
InterruE!....!0gic ~rol~_Jhe sequencing of three interrupts;
RES, NMI and IRQ. IRQ is generated by anyone of three
conditions: Counter Overllow, PAO Positive Edge Detected,
and PAl Negative Edge Detected.
The B-bit Processor Status Register, shown in Figure 3-3,
contains· seven status flags. Some of these flags are control.led by the user program; others may be controlled both
by the user's program and the CPU. The R6500 instruction
3-107
o
One-Chip Microcomputer
R6500/1
not all zero. The R6500 instruction set contains no instruction to specifically set or clear the Zero Bit. The Zero Bit is,
however, affected by the following instructions: ADC, AND,
ASt, BIT, CMF>, CPX, CPY, DEC, DEX, DEY, EOR, INC,
INX, INY, LDA, LOX, LDY, LSR, ORA, PLA, PLP, ROL,
ROR, RTI, SBC, TAX, TAY, TXA, TSX, and TYA.
set contains a number of conditional branch instructions
which are designed to allow testing of these flags. Each of
the eight processor .status flags is described in the following
sections.
3.10.1 CARRY BIT (C)
3.10.3 INTERRUPT DISABLE BIT (I) .
The Carry Bit (C) can be considered as the ninth bit of an
arithmetic operation. It is set to. logic 1 if a carry from the
eighth bit has occurred or cleared to logic 0 if no carry
occurred as the result of arithmetic operations.
The Interrupt Disable Bit (I) is used to control the servicing
of a'1..J!!terrupt request (IRQ). If the I Bit is reset to logic' 0,
the IRQ signal will be serviced. If the bit is set to logic 1,
the IRQ signal will be ignored. The CPU will set the Interrupt Disable Bit to logic 1 if a RESET (RES) or NonMaskable Interrupt (NMI) signal is detected.
The Carry Bit may be set or cleared under program control
by use of the Set Carry (SEC) or Glear Carry (CLC)
instruction, respectively. Other operations which affect the
Carry Bit are ADC, ASL, CMP, CPX, CPY, LSR, PLP, ROL,
ROR, RTI, and SBC.
The I bit is cleared by the Clear Interrupt (CLI) instruction,
the Pull Processor Status from Stack (PLP) instruction, or
as the result of executing a Return from Interrupt (RTI)
instruction (providing the Interrupt Disable Bit was cleared
prior to the interrupt). The Interrupt Disable Bit may be set
or cleared under program control using a Set Interrupt Disable (SEI) or a Clear Interrupt Disable (CLI) instruction,
.
respectively.
3.10.2 ZERO BIT (Z)
The Zero Bit (Z) is set to logic 1 by the CPU during any
pata movement or calculation which sets all 8 bits of the
result to zero. This bit is cleared to logic O. when. the resultant 8 bits of a data movement or calculation operation are
7
I NI
6
5
vii
4
3
BID 1
o
2
II z
-I
C
I
CARRY (C) (1)
1
::::
o ::
Carry Set
Carry Clear
ZERO (Z) (1)
1
=
o ::
Zero Result
Non-Zero Result·
INTERRUPT DISABLE (I) (2)
1
=
o =
I
I RQ Interrupt Disabled
IRQ Interrupt Enabled
DECIMAL MODE (D) (1)
1 =
o =
Decimal Mode
Binary Mode
BREAK COMMAND (B) (1)
1
::::
o =
_Break Command
Not Break Command
OVERFLOW (0) (1)
1
=
o =
Overflow Set
Overflow'Clear
NEGATIVE (N) (1)
NOTES
(1) Not initialized by RES
(2) Set to Logic 1 by RES
1
o
=
Figure 3-3. Processor Status Register
3-108
Negative Value
Positive Value
One-Chip Microcomputer
R6500/1
arithmetic operation is negative; if tile sign bit is cleared,
the result of tilG data mqvement or ,arithmetic operation s
PQsltlve. There are no InstruC\ions that set or clear the Negative Bit since the Negative Bit represents only the status of
a result. The instruCtions that effect the state of the Negative Bit are: AOC, AND, ASL, BIT, CMP, CPX, CPY, DEC,
DEX, DEY, EaR, INC, INX, INY, LOA, LOX, LOY, LSR,
ORA, PLA, PLP, ROL, RDR, RTI, SBC, TAX, TAY, TSX,
TXA, and TVA.
3.10.4 DECIMAL MODE BIT (D)
The Decimal Mode Bit (0), is used to control the arithmetic·
mode of the CPU. When this bit is set io logic 1, the adder
operates as a decimal adder. When this bit is cleared to
logic 0, the adder operates as a straight binary adder. The
adder mode Is controlled only by the programmer. The Set
Oecimal Mode (SED) instruction will set tlJe 0 bjt; the Clear
Decimal Mode (CLD) instruction will clear'· it. The PLP and
ATI instructIOns also effect the OecimalMOde Bit.
3.11 2K X 8 ROM
The R6500/1 2048 byte x 8·bit Read Only Memory, (ROM)
u,S,uailY contai,ns the user's program instructions alld other
fixed constants. These program instructions and bonstants
'are mask-programm~ into the ROM during fabrication of
the R6500/1 device. The R6500/1 ROM is memory mapped
from 800 to FFF.
The Decimal Mode Bit will either set or clear in an
unpredictable manner upon power application to
R6500/1. This bit must be initialized to the desired
state by the user program or erroneous resuHs may
occur.
3.1264
3.10.5 BREAK BIT (B)
8 RAM
The 64 byte x S-bit Random Access Memory (RAM) contains the user program stack and is used for scratch pad
memory during system operation. This RAM is completely
static in operation and requires no clock or dynamic refresh.
The data contained in RAM is read out nondestructively
with the same polarity as the input data., A standby power
pin, VRR allows RAM memory to be maintained on 10% of
the operating pqwer. In the event that vec power is lost
and execution stops, this standby power retains RAM data
until execution resumes.
The Break Bit (B) Is used to determine the condition which
caused the IRO service routine to be entered. If the IRO
service routine was entered because the CPU executed a
BRK command, the Break Bit will be set to ,logic 1. If the
fRO routine was entered as the result of an IRO signal
being generated, the B bit will be cleared to logic o. There
are no instructions which can set or clear this bit.
3.10.~
X
OVERFLOW BIT (V)
The Overflow Bit (V) is used to indicate that the result of a
signed. binary addition, or subtraction, operation is a value
that cannot be contained in seven bits (-128 ,.; n ,.;
11z1). This indicator only has meaning when signed arithme·
tic (sign and seven magnitude bits) is performed. When the
AOC or SBCinstructionisPerformed. the Overflow Sit is
set tQ logic 1 if the polarity 01 tl"leslgn bit (bit 7) is
changed because the result exceeds +127 or -128; otherwise the bit is cleared to logic O. The V bit l'Tlay also be
cleared by the programmer using a Clear OVerllow (CLV)
instruction.
In order. to take advantage of zero page addressing capabilities, the R6500/1 RAM is assigned page zero memory
address 0 to 03F.
3.13 CONTROL REGISTER
The Control Register (CR), shown· in Figure 3-4, is located
at ~ciress oaF. The CR contains five control signals and
three status Signals.
.
The control signa~ are summarized in Table 3-1. The control signals are set to logic 1 by Writing logic 1 il).o the
respectIVe biipositlons and cleared to 1000ic 0 either J:ly writ:
irig logic 0 into the respective bit poSition or by the oqcur·
renee of a RES Signal.
.
The Overflow Bit ma~ 1118(1 be u~d with the BIT instruction;
The BIT instruction which may be used to sample interface
devices, alloWs the overflow flag to refleCt the condition of
bit 6 in the sampled field. Durling a', BIT instruction the
OverflOW Bit is set equaltQ,' Ul~ content of the bit 6. on ,the'
data t~ed with BIT 'instruction; When u$ed inthismQde,
tl)e ov8rflow lias nothing to' do with signed arithmetic, bot Is
juSt another sense' bit for the microprocessor. InstructIOns
which affeci the V flag are AOC, err, CLV, PLP, RTI and
SBC.
TIlb" ~1. Cft COntroISIIl~aI8
Bit
Control Signal ~m.
N,,,mber
0
Counter Mode COntrol 0 (CMCO)
1
Counter Mode ConIroll (CMC1)
3.10.7 NEGATIVE BIT (~)
The Negative Bit (N) is used ~ indicate that the sign bit
(1;111 7);, In the ~sl,llting value of
data movemtnt or data
arithmetic operation, ,is set to logic 1. If the sign bit. is set
to logic 1, tne resulting' value of the data movement or
e,
Inte.~p\.Erial/led
(AlI,e)
i
PAD Interrupt Enabled (AOI!;:)
;3
PAl
Count~rl~pt Enabled (ClIO)
The three status signals are summarized in Table 3-2:
3-109
4
3
One-Chip Microcomputer
R6500/1
I
7
G
5
I
4
3
o
2
CR7'1 AOEDA1EDCI.E
CRG, \. CR5) CR4\ AOIE
CR31 AllE
CR21.GMCl
CR111 CMCO
CRO'J
CTRO
I
I
COUNTER MODE CQNTROL (CMCl & CMCO)
o
0
1
o
Interva-I Timer
Pulse G'Emerator
Event Counter
Pulse Width Measurement
o
1
PAl INTERRUPT ENABLE (AlIE)
1 = Enable PAl Interrupt
0= Disable PAl Interrupt
..
pAo INTERRUPT ENABLE lAOIE)
= Enable
1
PAO Interrupt
Interrupt
o = Disable PAO
COUNTER INTERRUPT ENABLE (CIE)
1 = Enable Counter Interrupt
a=
Disable Counter Interrupt
PAl NEGATIVE EDGE DETECTED (A1ED)
1
=
o =
PAl Negative Edge Detected
PAl Negative Edge Not Detected
PAO POS.ITIVE EDGE DETECTEO(AOED)
1
=
o =
PAO Positive Edge Detected
PAO Positive Edge Not Detected
COUNTER OVERFLOW (CTRO)
1
=
o =
Counter Overflow Occurred
No Counter Overflow
Figure 3-4. Control Register (CRl
Table 3-3. Counter Mode Control Selection
Table 3-2. CR Status Signals
Bit
Number
CMCl
(Bit 1)
CMCO
(Bit 0)
PAl Negative Edge Detected (Al ED)
5
0
0
Interval Timer
PAD Positive Edge Detected (AOED)
6
0
1
Pulse Generator
Counter Overflow (CTRO)
7
1
0
Event Counter
1
1
Pulse Width Measurement
Status Signal Name
The status signals are read·only information. The status bits
are set to logic 1 by hardware monitoring logic and cleared
to logic 0 by the occurrence of RES signal or by specific
address commands. Each of these signals is described in
the following sections.
Mode
The Counter is set to the Interval Timer Mode· (00) when a
RES signal is generated or if. the user program. stores logic
o into Bits 0 and 1 of the Control Register. A complete
description of each of the Counter modeS is given in Section 3.14.1.
3.13.1cOUNTER MODE CONTROL 0 AND 1
Counter Mode Control signals CMCOand CMCI (bits 0 and
1) control the Counter operating modes. The modes of
operation and the corresponding configuration of CMCO and
CMCI are summarized in Table 3-3.
3.13.2 PA1 INTERRUPT ENABLE BIT (A1IE)
!!Jtle PAl Interrupt Enable Bit (CR2) is set to logic 1, an
IRQ interrupt request signal will be generated when the
PAl Negative Edge Detected Bit (CRS) isseI.
These modes are controlled by writing the appropriate bit
values into the Counter Mode Control bits.
3·110
One-Chip Microcomputer
R6500/1
the values contained in the Upper Latch (UL) in address 084 and
in the Lower Latch (LL) in address 085, respectively. Therefore, it
is importantto load the Lower Latch value prior to executing the
Write to Upper Latch and Transfer Latch to Counter (address
088) in order to prevent an unpredicted reoccurrence of Counter
Overflow and, if enabled, an IRQ interrupt request
3.13.3 PAD INtERRUPT ENABLE BIT (AOIE)
If the PAO Interrupt EnableBlt (CR3) is set to logic' 1, the
IRQ interrupt request signal wiHbe .generated wilen tM
PAO Positive Edge Detected Bit (CR6) is set.
3.13.4 COUNTER INTERRUPT ENABLE ,BIT (CIE)
3.14 COUNTER/LATCH
lithe Counter l[1terruptEnable ,Elit (CR4) is set to logic 1,
the IRQ interrupt requel3t, signal Will be generated when
COunter OVerflow (CR7) isseI,
the CounterlLatch conSists of a 16-bifCounter and a 16-bit
Latch. The Counter resides in two 8-bit registers: address
0,
,86conl,ain,
s t"h, e U,PP"
C,oun,t,valu,
(bits, ,8,Count
-15, of value
the cou,
nter)
and address
087 i:1,rcontains
the eLower
(bits
0-7 of the Counter). The Counter contains the count of
either 912 clock periods or extemal events depending on
which counter mode is selected in the Control Register
(Section 3.13.1).
3.13.5 PAl NEGATIVE EDGE DETECTED BIT
(A1EO)
,
The PJ),l Ne,gative Edge, Detected Bit (CR5) is set to logic
1 whenever a negative (falling) edge is detected on PAl.
This bit is cleared to logic 0 by RES or by writing to
address 08A.
The Latch contains the Counter initialization value. The
Latch resides in two 8-bit registers: address 084 contains
the Upper Latch value (bits 8-15 of the Latch) and, address
085 contains the Lower Latch value (bits 0-7 of the Latch).
The 16-bit Latch can hold values from 0 to 65535.
The edge detecting cirCUitry is active when PAl is used
either as an input or as an output. When PAl is used as
an output, Al ED will be set when the negative edge is
detected during a logical 1 to 0 transition.
The Latch registers can be loaded at any time by executing
a write to the Upper Latch Address (084) and the Lower
Latch Address (085). In each case, the contents of the
Accumulator are copied ,into the applicable Latch register.
The Upper Latch and Lower' Latch can be loaded independently; it is not required to load both registers at the same
time or sequentially. The Upper Latch can also be loaded
by writing to address 088.
When PAl is used as an input and the negative edge
detecting circuitry is used,A 1ED should be cleared by the
user program upon initialization and when the PAl Negative
Edge Detected IRQ processing is completed.
3.13.6 PAD POSTIIVE EDGE DETECTED BIT (ADED)
The PAOPositive Edge Detected Bit (CFl6) is set to logic 1
whenever a positive (rising) edge is detected on PAD. The
bit is cleared to logic 0 by RES, or by writing to address
089.
'
The Counter can be initialized at any time by writing to
address 088. The contenis of the Accumulator will be copied into the Upper Latch before the value in the Upper
Latch is transferred to the Upper Counter.
The edge detecting circuitry is active when PAO is, used
either as an input or as an output When PAO is used as
an output, AOED will be set when the positive edge is
detected during a logical 0 to 1 transition.
The Counter will also be initialized to the Latch value whenever the Counter overflows. When the Counter decrements
from 0000, the next Counter value will be the Latch value,
not FFFF.
When PAO is used, as an input and the positive edge
• detecting circuitry is used, AOED should be cleared by the
'user program upon initialization and upon completion of
PAOPosiliveEdge Detected IRQ processing.
Whenever the Counter overflows, the Counter Overflow Bit
(CR7) is set to logic 1. This bit is cleared whenever the
lower eight bits of the counter are read from address 087
or by writing to address 088.
3.13.7 COUNTER OVERFLOWB,IT (CTRO)
Th,e Gaunter Overflow Bit (CR7) is,s~t to logic 1 whenever
a counter overflow occurs in any of the four counter operating mod,es. Overflow Qccurs when the counter is decremented one count from 0000. This bit is cleared to logic 0
by RES or, by reading from address 087 or writing to
address 088.
3.14.1 COUNTER MODES
The Counter operates in any of four modes., These modes
are selected by the Counter Mode Control bits in the Control Register.
Mode
This bit should be cleared by the user program upon
initialization and upon completion of Counter Overflow IRQ
interrupt processing.
Interval Timer
Pul'se Generator
Event Counler
When aCounler Overflow occurs, the Upper Count (UG) haddress 686 and the Lower Count (LG) inaddrass 087 are reset to
Pulse Width Measurement
3-111
CMC1
CMCO
o
o
o
o
D
One-Chip Microcomputer
R6500/1
Counter Timer capacity is therefore II'S to 65.535ms at the 1
MHz 9)2 clock rate or 0.5,..s to 32.768ms at the 2 MHz ~2 clock
rate. Time intervals greater than the maximum Counter value can
be easilL.!!!.easured by counting IRQ interrupt requests in the
counter IRQ interrupt routine.
The Interval Timer, Pulse Generator, and Pulse Width
Measurement Modes are 162 clock counter modes. The
Event Counter Mode counts the, occurrences of an external
event on the CNTR line.
Interval Timer (Mode 0)
In the Interval Timer mode the Counter is initialized to the
Latch value by either of two conditions:
When the Counter decrements from 0000, the Counter
Over:tlolfi (CR7) is set to logic 1 at the, next !1l2 clock pulse.
If the Counter Interrupt enable bit (CR4) is also set, an IRQ
interrupt request, will be genera,ed. The Counter Overflow
bit in the Contr'll Register can be examined in the 'IRQ
Interrupt routine, to determine that the 'IRQ, was generated
by the Counter Over:tlow.
1. When the Counter is decremented from 0000, the next
Counter value is the Latch value (not FFFF).
2. When a write operation is performed to' the Load
Upper Latch and Transfer Latch to counter address
(088), the younter is loaded with the Latch value. Note
that the contents of the Accumulator are loaded into
the Upper Latch before the Latch value is transferred
to the Counter.
While the timer is operating in the Interval Timer Mode, the
Counter OUtlEvent line, is held in the high (output disabled)
state.
The Counter value is decremented by one count at the ~2 clock
rate. The 16-bit Counter can hold from 1 to 65535 counts. The
A timing diagram of the Interval Timer Mode is shown in
,Figure 3-5.
I
COUNTER OVERFLOW
,
COUNTER
3
o
2
I
I
(UL,LLI ,
_
_
(UL, LLI-l
I'
COUNTER INTERRUPT ENABLED
\
SET ANY TIME BEFORE
COUNTER OVERFLOW
COUNTER OVERFLOW
IRQ
CNTR _ \ _ _ _ _
_
_
_
_
_
_
_
__ _
_
_
_
_______ _
HELD HIGH IN MODE 00
Figure 3-5. Interval Timer (Mode 0) Timing Diagram
Pulse Generator Mode (Mode 1)
output on the CNTR line in this mode. The CNTR output is
initialized high by a RES since the Interval Timer mode is
established by RES.
In the Pulse Generator mode, the Counter OutlEvent In line
(CNTR) operates as a Counter Out. The CNTR line toggles
from low to high or from high to low whenever a Counter
Overflow occurs, or a write is performed to address 088.
A one-shot waveform can be easily generated by changing
from Mode 1 Pulse Generator to Mode a (Interval Timer)
after only one occurrence of the output toggle condition.
Either a symmetric or asymmetric output waveform can be
3-112
One~Chlp
R650011
count at the 912 clOQl< rate as long as the CNTR line is held
In tha low state. The Counter Is stopped when CNTR Is In
the high stale.
"
Event Counter Mod. (Mode 2)
In this mode the CNTR line Is u~ as an E:vsnt In line,
and the Counter With decrement' wlfh each rising edge
detected on this line. The maximum rate. at which this edge
can be detected Is one·half the 1112 clock rate.
If the CNTR pin Is left dl~connectEld, this mode may be
selected to stop the Counter since the Inteinal' pull·up
device will cause the CNTR input to be In the high (>2.0V)
state.
The CQlmter can count up to 65,535 occurrence.s before
overflowing. As In~he other ,modes, the. Counter Overflow
bit (CR7) Is ~et~ologlc 1 If the overflow occurs.
A timing diagram' for the "Pulse Width Measurement Mode Is
shown In~lgure 3·7.
'.
Figure 3·6 is a timing diagram of the Event Counter Mode.
Pule. Width
3.15INPUT/OUTPUT PORTS
Measurement Mode (Mode 3)
I
CNTR
i-f.- 1!. ...
•. 2.0V
2.0V
O.BV
-/. O.BV
. ~T..--1f-cT"~
COUNT
~1
J
J
l
\
I
1
fJ
N·2
N·'
N.,
READ
N·2
"
,,,:,"
Figure 3-6. Event Counter Mode (Mode 2)
cNTR
COUNT
READ
...,-...,.._-:-:-...,-_i...
i..::2,;...O_V_r...._T_P_DS_U_ _ _ _ _ _ _
b
T_
N
N
N-4
N-'
Figure 3-7. Pulse Width Measurement (Mode 3)
3-113
II
.
The. R6500/1 proVide.s. four S·blt Input/Output (1/0) ports
(PA, PB, PC, PO). These 32 I/O lines are completely
bldll'Elctlonal. All lines. may be used either for Input or output
in any combination; that Is, there are no line grouping or
port association restrictions.
This mode allows the accurate measurement of a low pulse
duration on the CNTR line. In tbls mode; CNTR is used in
the Event In capacity. The Counter decrements by one
'2
Microcomputer
I
R6500/1 .'
One-Chip Microcomputer
The· direction of the 32 I/O lines are controlled I:IY four 8-l:Iil port
registers located in page zero. This arrangemer1t provides quick
programming access using simple two-l:Iyte zero page address
instructions. There are no direction registers associated with Ihe
I/O ports, which sirriplifiesl/O handling. The I/O addresses. are
shown in Tal:lle 3-4.
The status of the input lines can be interrogated at any
time by reading the 110 port addresses. Note that this will
return the actual status of the inpullines, not the data writ~
ten into the I/O port registers.
Table 3-4. 110 Port Addresses
Outputs are eontrollec! by writing' the desired I/O line output
states into the corresponding I/O port register bit pOsitiOns.
A logic 1 will force a high (>2.4V) oUtl'utwhile a logic 0
will force a low «0.4V) output.
.
pon
3.15.2 OUTPUTS
AddreSs.
A
OlIO
a
081
C
082
0
083
3.15.3 EDGE DET-=CTlON CAPA.BILITY
Ports PAO and PA1 have an edge detection capability. Figure 3-9 sho'llisthe edge detection timing.
Figure 3-8 shows the I/O Port Timings.
PAO Positive Edge Detecting Capability
In additiOn to its normal 110 function, PAO .will detect an
asynchronous positive (rising) edge signal and set the PAO
Positive Edge Detected signal (CRS) to logic 1. The maxi;.
mum rate at which this positive edge can be detected is
one-half the rJ2 clock rate.
'
3.15.1 INPUTS
Inputs are .enabled by loading logic 1 into all I/O port register bit
positions that are to. correspond to I/O input lines. A low «0.8V)
input signal will cause a logic 0 to be read wh~n a read instruction
is issued. to the port register. A high (>2,0V) input will cause a
logic 1 to be read. An RES signal forces all I/O port registers to
logic 1 thus initially treating all I/O lines as inputs.
.;"
,
!
'
If the PAO InterTOpt Enable eit (eR3) is sel, an IRQ interrupt request will also be.llenerated. The PAO Positive Edge
Detected signal can l:Ie cleared by writing to address 089.
I/O PORT OUTPUT TIMING
INTERNAL R/W
I-_________T~P-OW---.
'__________________________~________~I_.
8·
~2CLOCK PULSES AFTER 1>2 OSCILLATO,:, STABILIZATION.
®
;;> 8
tP2 CLOCK PULSES.
Figure
5-2. RAM Retention Mode Timing
The power monitor hardware must s~nse the loss of vce
power in sufficient time io allow the R650011 to save required ePUregister data in RAM. The power loss indication
line can be connected to the NMI interrupt input in order to
cause an immediate R6500/1 interrupt upon power loss
detection.
depending upon cold/warm start condition.
Upon power loss detection, the R6500/1 should save all required
epu regisler data in either the stack or dedicated RAM. The stack
may be preferred if dedicated RAM is not available. If the program
is to restart at the interrupted address, then all epu registers
must be saved, i.e., S, P, PC,A, X, and Y. The stack pointer must
be saved.in a dedicated RAM address. Note that processor status
Pand the program counter, PC, are already sav/ild on the stack by
the NMI interrupt R6500/1 hardware processing. If the warm start
can be performed at a specific address, then the saving of the
register data at power loss detection may not be required. Figure
5-3 shows top level flowcharts of typical power down and
power-up processing.
..
The power monitor hardware should also provide an indication of cold start (Initial vee and VRR power application) or
warm start (Vee power re·application while VRR is retained
on baCkup power) provided as input on a data I/O pin.
A leVel indication is sufficient. The R6500/1 program can
then initialize all, or partial, program variables upon initialization then jump to any other starting address as required
3-118
R650011
One-Chip Microcomputer
ACQUIRE/COMPUTE
AND SAVE DATA
AS REQUIRED
COMMON INITIALIZATION
SAVE A, X, 8< Y IN STACK
SAVE S IN DEDICATED RAM
NO
YES
COLD
START
ADDRESS
INITIALIZE COLD START
UNIQUE VARIABLES
"HANG UP IN SHORT
LOOP UNTIL EXECUTION
TERMINATES
a,
WARM
START
ADDRESS
INITIALIZE WARM START
UNIQUE VARIABLES
Program Recovery at
Address of Interruption
ACQuiRE/COMPUTE 8<
SAVE DATA AS
REQUIRED
COMMON INITIALIZATION
YES
·HANG UP IN SHORT
LOOP UNTIL EXECUTION
TERMINATES
COLD
START
ADORESS
INITIALIZE COLD START
UNIQUE VARIABLES
b.
Program Recovery at
Specific Restart Address
Figure 5-3. Typical R6S00/1 Power Loss Recovery Flowcharts
3-119
NO
WARM
$TART
ADDRESS
INITIALIZE WARM START
UNIQUE VARIAB!-ES
R6500/1
One-Chip Microcomputer
SECTION 6
TEST
application program into RAM. It can easily be adapted to
specific requirements by re-assigning 110 as required. The
loader uses positive handshake between the R6500/1 and
the interfacing host eqUipment. One 110' line is dedicated to
the test mode selection. The other pins asSigned to loader
interface signals may be assigned to normal application 110
interface signals when the test mode is not selected.
6.1 TEST MODE
The R6500/1 test function is multiplexed on the RES input
pin. The three input states for this pin are:
1. <0.8V
Reset state. All .R6500/1 outputs are
forced 10 the high state.
2. >2.0Vand
<5.5V
Normal run state. The low to high transition on the RES pin initiates fetch of the
reset vector from address FFC and FFD
and starts user program execution at the
vectored address.
3. >10.0Vand
<10.5V
110 is aSSigned for the RAM Program Loader as follows:
Teststate. The only internal action that
takes place is switching of the data
source for instruction memory from internal ROM to I/O port "C". Bit 0 of port
"C"is the data least significant bit (LSB).
PAO
Data Ready (DR) - Positive edge indicates data is ready for sampling by the
R6500/1.
PA1
End. of Data (EOD) - Negative edge
indicates that all the data has been
transferred to the R6500/1.
PA2
The test mode allows instructions and data to b.e input externally
through I/O port "C". This capability is used at Rockwell to test all
of the R6500/1 logic, registers and internal data RAM. A ROM
dump may be accomplished by using the test feature to load into
the internal RAM a small program to fetch each byte of ROM and
output it to an I/O port. After this program is loaded the CPU is
directed to begin execution out of RAM, e.g., JMP to OO.After the
jump is executed, the RES line is returned to the normal run state.
The normal run state allows data fetcheS to occur out of the
internal ROM and returns port "C" to its normal function.
Data Taken (DT) Data. Not Taken
1 = Data Taken
o=
PA7
Normal Mode Select (NMS) 0= Test Mode
1 = Normal Mode
PB7-PBO
Data input, i.e., instruction or data (PB7
= MSB, PBO = LSB)
The flowchart in Figure 6-1 shows the loader operation. The
handshake waveforms between the R6500/1 and the host
are illustrated in Figure· 6-2. The following description corresponds to the handshake events identified in Figure 6-2:
1) Host sees PA2 high, which indicates previous data, if
any, has been taken by the R6500/1. The host then
drops PAO low to indicate new data is not ready. This
signal shoUld be initialized low by the host.
The detail support hardware. and software required to use
the R6500/1 test mode is fairly complex and time critical.
For normal application testing, it is recommended that a test
program be loaded into RAM and executed as explained in
Section 6.2.
2) R6500/1 detects PAO low then drops PA2 low to indicate that data has not been taken.
3) Host sees PA2 low then sets up new data.
6.2 PROGRAM LOADING INTO RAM
4) Host sets PAO high to indicate new data is ready.
5) Upon detecting positive edge of PAO, R6500/1 reads
data on PB7-PBO. R6500/1 then sets PA2 high to indicate that the data has been taken.
A test or application program can easily be loaded into the
R6500/1 RAM and executed without forcing the R6500/1
into the test mode. To do this, a shM program loader function must be penmanentiy included in the application program
stored in ROM. Upon test mode selection during R6500/1
initialization, the loader reads instructions or data from an
110 port and stores them into RAM. At the first completion
of the load, the loader then jumps to the first instruction. in
RAM to start program execution.
6 When no more data is available, the host drops
low to indicate end of data (EOD). The R6500/1
jumps to address $000 to start program execution.
RAM is loaded without EOD detected, the R6500/1
jumps to address $000.
PA1
then
If all
also
An assembly listing of the RAM Program Loader is shown
in Table 6-1.
A program is described which may be used to load test or
3-120
One-Chip Mlcrocomputir
R6500t1
INITIALIZE STACK POINTER
$3F+S
CLEAR DECIMAL MODE
INITIALIZE RAM INDEX TO 0
II
CR5
I- PAl NEG EDGE
DETECTED· "ES
PAl NEG EDGE
DETECTED· YES
Figure 6·1, RAM Program Loader Flowchart
3·121
One-Chip Microcomputer
R6500/1
~'----DATA STABLE----J
DATA (PB7-'PBO)
DATA READY (DR) (PAO)
~I
DATA TAKEN (DT) (PA2)
\
- - - - - , - - - . - - - - - 1 1 . . . . '.
~
END OF DATA (EOD) (PAt)
Figure 6-2. R6500/1 RAM Program Load Handshake
3-122
One-Chip Microcomputer
A6500/1
Table 6-1. RAM Program Loader Assembly Listing
R6500/1 RAM LOADER ...... PAGE 001
LINE #
0002
0003
0005
0006
0008
0009
0010
0011
0012
0013
0014
0000
0600
0802
0803
0604
0606
0808
A23F
9A
08
A200
A560
3020
Reset
0016
0017
0018
080A
080C
0800
A580
4A
BO 1C
PAZCK
0020
0021
080F
0811
A9 FB
8580
0023
0024
0025
0813
0815
0817
A920
248F
501A
0027
0028
0030
0031
0032
0033
0034
0819
081B
00810
081F
0821
0823
0824
0826
8589
A581
9500
A9 FF
8560
E8
EO 40
DO E2
0036
0828
4C 00 00
0038
0039
0040
0041
082B
0820
082F
0831
0043
0044
0833
0835
0046
0837
0046
0049
0050
0837
OFFC
OFFE
0004
0029
CODE
,
LOC
0000
0000
0000
0000
0000
LINE
PORTB":$81
PORTA = $80
CLRPAO= $B9
CTLREG=$8F
BEGIN =$000
RDYCK
;Port 6 Address
;Port A Address
;CLR pAo Edge Detect
;Control Register
;RAM First Address
'=$0600
LOX #$3F
TXS
CLD
LOX #$00
LOA PORTA
'BMIINIT
;Initialize Slack Pointer
;Set Binary Add Mode
;Inilialize RAM Index
;Test Mode Selected (PA7=0)?
LOA PORTA
LSRA
BCS EODCK1
;Yes
LOA #$FB
STAPORTA
;No, Reset Data Taken
;O->PA2
LOA #$20
BIT CTLREG
BVC EODCK2
;Dala Ready (PAO Pos Edge Detected)?
;Data Ready High (PAO=1)?
STACLRPAO
LOA PORTB
STABEGIN,X
LOA #$FF
STAPORTA
INX
CPX#$40
BNE PAZCK
;Yes, Clear PAO Pos Edge Detected
;Load Data From Port B
;Store In RAM
JMPBEG
JMP BEGIN
;Yes, Go To !=lAM Program Execution
A920
258F
FOD9
00 F5
EODCK1
LOA #$20
ANDCTLREG
BEQ PAZCK
BNEJMPBEG
;End of Data (PA1 Neg Edge Detected)?
;Yes, Go To RAM Progr!lm Execution
FO DE
DO F1
EODCK2
BEQ RDYCK
BNEJMPBEG
;End of Data (PA1 Neg Edge Detected)?
;Yes, Go To Ram Program Execution
RES
;Is RAM Full?
;Firsl Address of Normal Program
INIT
0008
;Set Data Taken (1->PA2)
;Increment RAM Index
*=$FFC
,WOR RESET
.END
Errors = 0000 <0000>
End of Assembly
3-123
;Reset Vector
II
R6500/1
One-Chip Microcomputer
APPENDIX A -
SYSTEM MEMORY MAP
HEX
IRQ Vector High
FFF
IRQ Vector Low
FFE
RES Vector High
FFD
RES Vector Low
FFC
NMI Vector High
FFB
NMI Vector Low
FFA
ROM
FF9
User Program
800
7FF
R6500/1 E User Program
400
3FF
<>
Unassigned
<
900
Control. Register
08F
08E
< >08B
Unassigned
<
Clear PA1 Neg Edge Detected (Write Only)
(1 )
08A
Clear PAD Pos Edge Detected (Write Only)
(1)
089
Upper Latch and Transfer Latch to Counter (Write Only)
(2)
088
Lower Count (Read Only)
(2)
087
Upper Count (Read Only)
086
Lower Latch (Write Only)
085
Upper Latch (Write Only)
084
PORT D
083
PORT C
082
PORT B
081
PORT A
;>
080
PORT B
-
{ m,
PSO·PB7
SelT
PORTC
PCO·PC7
-
CRYSTAL
XTLO
12 ADDRESS
LINES
R6S00/1
SINGLE CHIP
MICROCOMPUTER
EMULATOR
;>
S BIT
PORT D
PDO'PD7
->
CNTR
S DATA
LINES
EMULATOR
CONTROL
"""
~
iiiMi
r/l2
RES
RDY
SYNC
..
!
PAO-PA7
Vss
r
.
:> PORT A
Rm
Figure 0-1. R6500/1 Emulator Interface Diagram
3-129
.
TO
INTERFACE
DEVICES
One-Chip Microcomputer
R6500/1
Table 0-1. R6500/1E Emulator Pin Description
Signal
Name
Pin
No.
Description
RIW
62
ReadlWrite allows the CPU to control the direction of data transfers between the R6500/1 E Emulator CPU and
external memory. This line Is high when reading data from memory and is low when writing data to memory.
ROY
3
The Ready input delays execution of any cycle during which the ROY line is low. This allows the user to halt
or single step the CPU on all cycles except, write cycles. A negative transition to the low state during the ~2
clock lOw pulse will ha~ the CPU with the address lines containing the current address being fetched. If ROY is
low during a write cycle, it is ignored until the following read operation. This condition will remain through a subsequent ¢2 clock pulse in which the ROY line is low. This feature allows the CPU to interface with memories
having slow access times, such as EPROMS used with the R6500i1 Emulator part during prototype system
development.
SYNC
6
The Sync signal is provided to identity cycles in which the CPU is performing OP CODE fetch. SYNC goes high
during the 162 clock low pulse of an OP CODE fetch and stays high for the remainder,?f that cycle. If the ROY
line is pulled low during the !a2 clock low pulse in which SYNC went high, the CPU will halt in its current state
and will remain in that state until the ROY line goes high. Using this technique, the SYNC signal can be used to
control ROY to cause single instruction execution.
~2
1
Phase 2 (162) clock pulse. Data transfer takes place only during !a2 clock pulse high.
AO-A11
25,37
Address Bus lines. The address bus buffers on the R6500/1 E are push/pull type drivers capable of driving at
least 130pf and one standard TTL load. The address bus always contains known data. The addressing technique involves putting an address on the address bus which is known to be either in program sequence, on the I
same page in program memory, or at' a known point in memory. The I/O address commands are also placed on
these lines.
'
00-07
53-46
Data Bus lines. All transfers of instructions and data between, the CPU and memory, I/O, and other" interfacing
circuitry take place on the data bus lines. The buffers driving the data bus lines have full three-state capability,
which is necessitated by the fact that the lines are bidirectional. Each data bus pin is connected to an input and output
buffer, with the output buffer remaining in the floating cond,ition.
0.3 SYSTEM ARCHITECTURE
8::::> PAO·PA7
Figure 0-3 is a block diagram of the R6500/1 E Emulator.
The function of each block is identical to its counterpart in
the R6500/1 microcomputer. The main differences between
the two products are in the ROM, the clrn;k oscillator, the
input/output ports and write-only monitoring.
- 8::::> PBO·PB 7
R6500/1E
EMULATOR
D.3.1 ROM
To facilitate debugging, theR6500/1 ROM has been removed from the R6500/1E Emulator, and has been replaced
by external memory. Also, an additional 1024 bytes of
memory (400-7FF) are addressable.
_8 ::::> PCO·PC7
8:::::> POO·PO 7
"'--"CNTR
D.3.2 CLOCK OSCILLATOR
The external frequency reference for the R6500/1 E Emulator
may be either a crystal or a clock. The HC option is not
available for this device.
SYNC
4---1
RNV
.---1
Figure 0-3. R6500/1 E Emulator, Block Diagram
D.3.3 INPUT/OUTPUT PORTS
D.3.4 WRITE-ONLY MONITORING
The R6500/1 E has the internal I/O and CNTR port pull-up
resistance only. The option to delete the pull-up resistance
is not included in this device.
The R6500/1 E allows the user to monitor write operations
to the internal RAM and I/O by routing those operations
externally as well as internally. Read operations are not
routed externally.
3-130
!
One-Chip Microcomputer
R6500/1
0.4 R6500/1 E I/O PORT INITIALIZATION
than in the R6S00/1. It is stili required, however, that the
RES line to the R6500/1 E be held low for at least eight /62
clock cycles after vee reaches operating range and the S2,.
clock oscillator has stabilized.
Ports A, B, e and 0 and the eNTR line in R6S00/1 E are
initialized to the logic high state two "2 clock cycles earlier
8 ¢2 clock cycles minimum after ¢2 clock stabilization
I
~~~~~--------------------------~~
RSSOO/1E
I/O
PORTS
~~~~_~~~~~~~~----------------------~--------------~Ar-----
R6500/1~
~
RES transition window
~ Don't care state
this case, type 2716 and 2708 PROMs). Example 1 shows a
connection to a 2K 2716 PROM. Since the R6500/1 has a
2K ROM capacity, the contents of the PROM could be
masked directly into the production R6500/1 ROM.
0.5 TYPICAL R6500/1 E PROGRAM MEMORY INTERCONNECTIONS
Shown below and on the following page are two typical
connections between the R6S00/1 E and program memory (in
Example 1. R6500/1E Connected to One 2716 PROM (2K Bytes)
• SEE RSSOO/1 DETAILED MEMORY MAP
Connection Diagram
R6500I1E
DO
01
02
03
04
05
06
07
00
01
02
03
04
AD
Al
A2
A3
A4
A5
A6
A7
AS
A9
Al0
AD
Al
A2
A3
A4
A5
A6
A7
AS
A9
Al0
All~
Memory Map
FFF
2716
PROM
05
06
07
r-
SOD
7FF
2716
NOT USED
090
OSF
RAM & I/O'
OE
CE
000
3-131
II
One-Chip Microcomputer
R6500/1
program, however, must be reduced to 2K maximum (between addresses 800 and FFF) before committing to
R6500/1 ROM.
Example 2 shows a connection to 3K of 2708 PROMs. The
extra 1K PROM allows expanded or additional programs be
used during R6500/1 firmware development. The production
Example 2. R6500/1 E Connected to Three PROMs (3K Bytes)
Connection Diagram
R6500/1E
DO
01
02
03
04
05
06
07
00
01
02
03
04
05
06
07
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
AO
Al
A2
A3
A4
AS
A6
A7
A8
A9
Irl>J-pAlO
All
00
01
02
03
04
05
00
01
02
03
04
05
06
06
07
07
2708
NO.1
AO
A1
A2
A3
A4
AS
A6
A7
A8
2708
NO.2
~:
I
cs
]
rI
I
I
FFF
2708 NO.3
PROM
COO
BFF
1------
-
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
2708
NO.3
p.cs
1
J
Program Memory
2708 NO.2
PROM
------
800
7FF
2708 NO.1
PROM
} Extended Program
Memory
400
3FF
NOT USED
RAM & 110
.
090
OBF
000
'See R6500/1 E Detailed Memory Map
Truth Table
2708 No.1
CE
PROM Select
2708 No.2
CE
Address
2808 No.3
CE
Selected
Address Range
1
1
0OO-3FF
1
1
400-7FF
1
0
1
BOO-BFF
1
1
0
COO-FFF
All
Al0
0
0
1
0
1
0
1
0
1
1
3-132
One-Chip Microcomputer
R6500/1
0.6 R6500/1 E TIMING
2 MHz
1 MHz
Max.
Unit
RiW setup time from CPU
TRws
300
200
ns
Address setup time from CPU
TAos
300
200
ns
TAcc
525
225
ns
Min.
Symbol
Signal
Memory read access time
Data stabilization time
Tosu
Max.
Min.
150
75
ns
10
ns
Data hold time -
Read
THR
10
Data hold time -
Write
THW
30
ROY setup time
TROY
SYNC delay time from CPU
TSYNC
Address hold time
THA
30
30
THAW
30
30
1.0
0.5
Cycle Time
ns
50
100
10.0
ns
175
350
Tcyc
ns
150
T MOS
R!W hold time
ns
30
200
Data delay time from CPU
ns
ns
10.0
fLS
TCYC
PHASE 2 (¢2) TIMING RE.FERENCE
¢2
O.4V
RtW
TIMING FOR READING DATA FROM
EXTERNAL MEMORY
ADDRESS FROM
CPU
2.0V
DATAFROM ____~------~------~--~~~
MEMORY
RDY
SYNC
---
-
- - THRW
RtW
TtMING FOR WRITING DATA TO
EXTERNAL MEMORY
ADDRESS FROM
CPU
+-______________+-____
DATAFROM ____
CPU
~
_~~
3-133
____~~~
II
One-Chip Microcomputer
R&500/1
0.7 R6500/1 E ELECTRICAL CHARACTERISTICS
Charactl!rlatlc
Syinbol
Input High Threshold Voltage
DO-07, ROY,
V,HT
Input LOw Threshold Voltage
00-07, ROY,
V'LT
Threa-State (Off State) Input Current
(V 0.4 to2.4V, Vee = 5.25V)
00-07
ITSI
Output High Voltage
(ILOAC = 100 .,.Adc, Vee = 4.75V)
00-07, SYNC; Ao-A11 , RIW, ~2
VOH
Output LOw Voltage
(ILOAC = 1.6 mAde, Vee'" 4.75V)
00:07, SYNC, AO-Al1 , RIW,;2
VOL
=
"
Power Dissipation
Po
Capacitance
(Vin = 0, TA = 25·C, f = 1 MHz)
ROY
DO-07
AO-Al1, RIW, SYNC
912
t
C'n
Co..
Co2
3-134
Min
Typ
Max
Unit
Vss +2.4
-
-
Vdc
-
-
Vss+O.$
Vdc
-
-
10
"'"
Ves +2.4
-
-
Vde
-
-
Vss +0,6
Vdc
-
0.50
1.00
W
pF
-
-
50
10
15
12
80
R6500/1E
R6500r Microcomputers
'1'
Rockwell
R6500/1E
MICROPROCESSOR EMULATOR DEVICE
INTRODUCTION
of R6500/1 and R6500/1
functions.
The R6500/1 EC and R6500/1 EO devices provide all the features
of the R650011 Microcomputer in a: ROMless form suitable for
use as an advanced microprocessor complete with 16 bit counter
and 32 I/O lines, and an address and data bus for 4K of external
memory.
The device is available in both 64-pin DIP ceramic (R6500/1 EC)
and 64-pin OUIP Plastic (R6500/1 EO).
To aid in designing R6500/1 microcomputer systems, it may also
be used as an Emulator device. Device architecture is basically
the same as the R6500/1 except that the address, data, and
associated control lines are routed off the chip for connection
to an external memory.
ORDERING INFORMATION
Package
Type
Ceramic
Ceramic
Plastic
Plastic
Part
Number
R6S00/1EC
R6S00/1EAC
R6S00/1EO
R6S00/1EAO
The functions and operation of the devices are identical to the
R6500/1 except for minor differences. The R6500/1 Data Sheet
Order No. 051 (Document No. 2900051) contains a description
XTLO
XTLI
'2
VSS
ROY
RES
NMI
SYNC
PBl
PBS
PBS
PB4
PBS
PB2
PBl
PBO
PA7
PAS
PAS
PA4
PAS
PA2
PA1
PAO
VRR
CNTR
AO
A1
A2
AS
A4
AS
A6
A7
common interface signals and
'2
VSS
ROY
RES
NMI
SYNC
PB7
PBS
PBS
P84
PB3
PO
PB1
PSO
PA7
PAS
PAS
PA4
PAS
PA2
PA1
PAO
VRR
CNTR
RJW
PCO
PC1
PC2
pea
PC4
PCS
PC6
pC7
DO
01
02
03
04
05
OS
07
P07
POS
P05
P04
P03
P02
P01
PDO
A11
A10
A9
A8
vee
AO
AI
A2
A3
A4
AS
AS
A7
Frequency
Option
1 MHz
2 MHZ
1 MHz
2 MHz
1
2
3
4
5
6
7
S
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
4.7
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Temperature
Range
OOC to lOoC
O°C to lO·C
OOC to 70°C
O°C to 70·C
XTLO
XTLI
RiW
PCO
PC1
PC2
PC3
PC4
PCS
PC6
PC7
00
D1
02
03
D4
D5
DB
07
P07
P06
P05
P04
P03
.P02
P01
PDO
A11
A10
AS
AS
vee
RS500/1EQ
R6500/1E
Pin Configuration
Document No. 29000D51S
3-135
Data Sheet Order No. D51S
Rev. 2, February 1984
II
Microprocessor Emulator Device
R6500/1E
Signal
Name
SIGNAL DESCRIPTIONS
All R6500/1 interface signals are provided in the device. While
the pin assignments are different from the R6500/1 in order to
accommodate the 64-pin package, the interfac~ electrical
characteristics are identical. The device provides 24 additional
signals to route the address bus (12 lines), the data bus (Slines),
and control signals (4 lines) off the chip for connection to external
memory.
Pin
No.
<1>2
Phase 2 (<1>2) clock pulse. Data transfer can
take place onlyCiuring <1>2 clock.pulse.
AO-All
25-32
34-37
Address Bus Lines. The address bus buffers on the device are pushlpull type
drivers capable of driving at least .130 pf
and one standard TTL load. The address
bus always contains known data. The
addressing technique involves putting an
address. on the address bus which is
known to be either in program sequence,
on the same page in program memory, Qr
at a known point in memory. The 110
addresses are also placed on these lines.
DO-D7
53-46
Data bus Lines. All transfers of instructions
and data between the CPU and external
memory take place on the data bus lines.
The buffers driving the data bus lines have
full three-state. capability. Each data bus
pin is connected to an input and an output
buffer, with the output buffer remaining in
the floating condition.
MEMORY MAP
An addition~\ 1024 bytes of memory (400-7FF) are addressable
in the device.
EXTERNAL FREQUENCY REFERENCE
The external frequency reference may-be:s crystal or a clock
- the RC option is not available in the d~vice.
I/O PORT PULLUPS
The device has internal 1/0 port pullup resistance only.
DEVICE ADDITIONAL SIGNALS
Signal
Name
Pin
No.
Rm
62
ReadlWrite. The ReadlWrite output cantrolsthe direction of data transfer between
the CPU and external memory. This line
is high when reading data from memory
and low when writing data to memory.
RDY
3
Ready. The Ready input delays execution
of any cycle during which the RDY line is
low. This allows the user to halt 'dr'single
step. the CPU on any cycle except a write
cycle. A negative transition to the low state
during the <1>2 clock low pulse will halt the
CPU With the address lines containing the
current address being fetched. If RDY is
low during a,write cycle, it is ignored until
Ihe following read operation. This condition
will remain through a subsequent <1>2 clock
p\llse in which the RDY line is low.
SYNC
6
,Description
Description
I/O PORT INITIALIZATION
Ports A, B, C and 0 and the CNTR line in the device are initialized to the logic high state two <1>2 clock cycles earlier than in
the R6500/1. It is still required, however, that the RES line be
held low for at least eight <1>2 clock cycles after VCC reaches
operating range (Figure 1).
TYPICAL PROGRAM
MEMORY INTERCONNECTIONS
Sync. The Sync Signal is provided to identify those cycles in which the CPU is performing an OP CODE fetch. SYNC goes
high during <1>2 clock-low pulse during an
OP CODE fetch and stay high for the
remainder of that cycle. If the ROY line is
pulled low during the <1>2 clock low pulse
in which SYNC went high, the CPU will halt
in its current state and will remain in that
state until the RDY line goes high. Using
this technique, the SYNC signal can be
used to control RDY to cause single
instruction execution.
Illustrated are two typical connections between the RSSOO/l E
and program memory (in this case, type 2716 and 270S PROMS).
Figure 2 shows a connection to a 2K 2716 PROM. Since the
R6500/1 has a 2K ROM capacity, the contents of the PROM
could be masked directly into the production R6500/1 ROM.
Figure 3 shows a connection to 3K of 2708 PROMS. The extra
1K PROM allows expanded or additional programs be used during R6500/1 firmware development. The production program,
however, must be reduced to 2K maximum (between addresses
SOO and FFF) before' committing to R6500/1 ROM.
3-136
R6500/1E
Microprocessor Emulator Device
~ RD TRANSITION
~WINDOW
RB
110
{
----m
. ._______
I.;...;..t/>2_C_L_OC..;.,_K_C_Y_CL_E_S_M_I_N_IM_U_M_'...;;..._ _ _...,.~
~
DON',T CARE STATE
~SOOI1E~~~~~------------------~'~
PORTS
. ReSOO/1
~~~~~~~_---:_ _ _ _ _---:_ _ _ _ _ _.~
~
'''''--
:-""""""""""""'1
II
Agure 1. . 1/0 Port Initialization
CONNECTION DIAGRAM
~500/1E
DO
D1
D2
D3
D4
DS
D6
D7
00
01
02
03
04
05
06
07
AD
A1
A2
A3
A4
AS
A6
A7
AD
A1
A2
A3
A4
AS
A6
A7
AI
A9
A10
AI
A9
A10
"
MEMORY MAP
FFF
2716
PROM
100
7FF
NOT USED
2716
090
OIF
RAM .110·
000
A11H>-l= :
Figure 2. Device Connected to One 2716 PROM (2K Bytes)
3-137
R650011E
Microprocessor Emulator Device
MEMORY MAP
CONNECTION DIAGRAM
DO
01
02
03
04
05
06
07
AD
A1
A2
R6500/1E A3
A4
A5
A6
A7
A8
A9
A10
A11
-
00
01
02
03
04
05
06
07
00
01
02
03
04
05
06
07
AD 2708
A1 No. 1
A2
A3
A4
A5
AS
A7
A8
A9
AD
A1
A2
A3
A4
A5
A6
A7
A8
A9
~CE
·1
Figure 3.
ro-
00
01
02
03
04
05
06
07
AD
A1
A2
A3
A4
A5
A6
A7
A8
2708
No. 2
FFF
2708 No.3
PROM
1---,.--,-:- COO
BFF
2708
No. 3
2708 NO.2
PROM
--....,.
--
800
7FF} EXTENDED
MEMORY
400
PROGRAM
2708 NO.1
PROM
3FF
NOT USED
A9
RAM & 1/0
~CE
CE
PROGRAM
MEMORY
.
090
08F
000
'SEE DETAILED
MEMORY MAP
Device Connected to Three PROMS (3K Bytes)
TRUTH TABLE
..
Address
PROM Select
2708 No.3
A11
A10
CE
2708 No.2
CE
2808 No.1
CE
Selected
Address Range
0
0
1
1
0
1
0
1
1
1
1
0
1
1
0
1
1
0
1
1
0OO-3FF
400·7FF
800-BFF
COO-FFF
3-138
. Microproce~sor Emulator Device
DEVICE tiMING
.
.
1 MHz
Slgn.1
'.'
Rm setup time l!'lIm CPU
Min. ,
Symbol
2 MHz
Max.
Min.
....x.
Unit
ns
.TRWS
300
200
Address seiup time ftom CPU
TAOS
300
200
ns
Memory read access time
TACC
525
225
11 s
ns
Data stabilization
time
,1:'.
TDSU
Data hold time ....,.,Reed
THR
10
10
ns
Data hold time -
THW
30
30
ns
Write
Deta, del.y time'lrbii'lCPU
TivlDS
ROY setup lime
TROY,
'~YNC delay tllnefro",'Cpu
150 .
75
':.
200
.
100 ,
150
ns
175
ns
50
ns
350
TSYNC
Address hOld time
THA
30
30
Rm hOld time
THRW
30
30
TCYC
1.0
;
ns
"
Cycle Time
'ns
0.5 '
10.0
10.0
/AS
ELECTRICAL CHARACTERISTICS
,(Vee = 5.0
±5%, VSS
= 0,
TA
= 25°C)
Characteristic '
,
VIHT
Input Low Threshold Voltage
00-07, ROY,
VILT
Three·State (Off State) Input Current
(V = 0.4 to 2.4V, VCC = 5.25V)
00·07
ITSI
Output High Voltage
(I LOAD = 10(li2
' .
,C
1I0Port,Pull·up Resistance'
Min
Symbol
Input High Thrl~shOld Voltage
00·07, ROY,
,
-
-
VSS
+ 0.6
Vdc
,,'
1.20
",0.75
W
pF
-
-.
Cin
"
Cout
C~2
-
RL
',3.0
-
3-139
'I.,
' 80
50
,""
6.0
10
1\i
12
I'
"
1
11.5
kohm
II
Microprocessor Emulator 'Device
R6500/1E
DETAILED MEMORY MAP
!IRIl VIOC OR "Iii"
IIRIl VIOCTOR LOW
'IOC OR "Iii"
IFIE! 'ECTOR LOW
'ECTOR "Iii"
I~IM 'ECTOR LOW
R65OOl1 USER PROGRAM
R6500(,1 E lOA I "'~~"'.,
..."'.............
1<
I CONTROL
I)
..~... AREA(t)
~i::
UNASSIGNED
L.EAR
CLEAR
"1AO NEG
EDGE
POSEDGE
,.~;~AND
~'CH
( OUNT,
L.OWERLATC"
upp'EI! LA'CH
PO~IT,!)
1PORT
IPO~
~
087
086
085
084
083
082
INPUT/OUTPUT
I~:!
...,
IPO~
HEX
FFF
FFE
ROM
FFD
FFC
FFB
NOTES:
FFA
( 1) Additional 1024 bytes are de~~ed for, external
FF9
memory ad~ressing. This area can be used during
800
debut, but cannot be used '''I a masked ROM
7FF
R650011.
"
400
(2) I/O command only; I.e•• no ,stored data.
~
(3) Clears Counter Overflow - Bit? in Control Register
(4) CAUTION: The ,device allQWS RAM mapping' into
040·07F. 100.13F. 140·17F. 200·23F, 240·27F,
300·33F, and 340·37F; as well as OOO·03F.The
luolA
production R6500/1, however allows RAM mapping
only at 000·03F.
'
I~::
1000 }RAM(4)
IUSER RAM
TIMING DIAGRAMS
PHASE 2 (<1>2) TIMING REFERENCE
., ~
TCYC:'----\1~
0.4V()0.4V
TIMING FOR READING FROM MEMORY
,TIMING FOR WRITING TO MEMORY
ADDRESS --+"'ft
FROM'CPU
ADDRESS-.....FROM CPU,_-+__
--+---
+-__
DATAFROMI_-+____~----+_--~
MEMORY
~~__-M~
DATAFROM_-r__________
CPU
ROY
SYNC
3-140
~
0.8V 1"'--+"1'-
Micr~processor Emulator Device
R6500/1J:
PACKAGE DIMENSIONS
R6500/1 EC 64-PIN DIP CERAMIC
DD'
"[],
.' D
... '. ~ g
. . ,".
U
.-
DENOTES PIN NO.1""
(:\~C:)
(:~i~:)
B
.
~m~1 I~:
:~: . t~~ =:\1:
J l,,,I,.. :::
Ii::::
=.
.015(.36 MM)
.019 (.48 MMI
"
NOTE: PIN NO. 11S IN LOWER LEFt CORNER WHEN
SYl!laoLIZATION IS IN .NORMAL ORIENTATION
(3.05 MM)
LEADS .100
(2.54 MM)
It. TO It.
R650011 EQ 64-PIN QUIP PLASTIC
J<."
o
0,
:go
-,,-
~w
4iI;;,'"
.200-
, , :,O'.'.S,,: .
(5.08MM)
"I,,;
,
';.1i;;; ,
,
L---==3...,2_..;
33
.680 .'.
I
-(17,27 MM)--i
I'
i:-n'
_,_It.-1 1ll
-itT
O.50"REF
(1.27 MM)
llW-J
.020RE;T
TYP
TYP
3-141
L-
tt
tt
64 PIN QUIP
R6500/1 EB. R6500/1EAB
R6500 Microcomputer System
~'l'
R6500/1 EB and R6500/1 EAB
BAC,KPACK EMULATOR
Rockwell
INTRODUCTION
FEATURES
The.Rockwell R!l500/1 EB and .Fj6500/1 EAB Backpack E;mulator
is the PROM prototyping version of' the B-bil,' masRed-ROM
R6500(1 one:chip microcomplilter. Like the R6500/1, the ba.ckpack device is totally· upward/downward compatible, with all
meml)ers of the R6500/1family. It is designed to IlCcept standard 5~volt, 24-pin EPROMs or ROMs directly. in' a socket on
top of the Emulator. This. packaging concept a:llows ,a standard
EPROM to be easily removetl, reprogrammed; then reinserted
as often
desired.
• PROM version of the R6500/1
• ComPletelY pin compatible with R6500/1 single:chip
- microcomputers
• ~rofile approaches 4O-pin DIP of R6500/1
• Accepts 5-volt, 24~pin industry-standard EPROMs
-4K memories-2732, 2732A (3K bytes addreSsable)
-2K mert1liries~2716, 2516, 2316B
• Use as prototyping tool or for low volume production
• 3K bytes of memory capacity (1 K, 2K, 4K memories)
.• 64 x B static RAM
.
as
The backpack devices have: toe same pinouts as·the.maskedROM R6500/1 microcomputer. These 40 pins are fUnbtionally
and operationally identical. to the pins on the R6500/1,With
soma minor differences (described herein). T~;R6500/1 Microcomputer Data Sheet (Rockwell Document No. 29()OOD51)
'includes a description of the' interface signals' and their functions. Whereas the maSked-ROM R6500/1 provides 2K bytes
.of read-only memory, the R6500/1EB will ad~ress 3K bytes of
external program memory. This extra memory accommodates
program patches, test programs or optional programs during
breadboard and prototype development states.
ORDERING INFORMATION
Separate power pin for RAM
SoftWare ~ompatibU.ity with theR6!)OO family
32 bi:.aJrectiorial TTL compatible VO lines (4 ports)
1 bi-directional TTL compatible counter VO line
1~-bit programmable counter/latch wR.h four modes (interval
timer, pulse generator, event counter, pulse width
measurement)
• 5 interrupts (reset, non-maskable, two external edge sensitive, counter)
• . Crystal or external time base
• Single +5V power supply ,
•
•
•
•
•
BACKPACK EMULATOR
Pan
Number
Memory
capacity
Compatible., •
Temperature
Range and Speed
Meino.rles
R6500J1E81
2K x 8
2716, 2516
23168
OOC to 70°C
1 MHz
R650011E83
3K x 8
2732
O°C to 70 D C
1 MHz
R6500J1 EA83
3K x 8
2732A
(250 ns)
O°C to 70°C
2 MHz
SUPPORT PRODUCTS
Pan
Number
S65-101
M65-040
M65-081
M65-082
DeScription
SYSTEM 65 Microcomputer Development System
PROM Programmer Module
l-MHz R6500J1 Personality Module
2-MHz R6500Jl Personality Module
R6500/1 EB-R6500/1 EAB Backpack Emulator
Document No. 29000060
3-142
Data Sheet Order No. 060
Rev. 2, March 1984
R6S00/tEIi
and R6S00l1EAB
.
..
'.
:
'
,.,
,':"
'
CONFIGUFIATIO~S
,
' . '
110 PORT PULLUPS"
\
,The ernulator· devices have illternalllO port pullup resisto~,
The Backpack Emulator is avail abU:!, in three different versions,
.. to accommOdate various 24cpin' 2K'and 4K~memories and
spe~ds. All three versions provide 64 bytes of RAM arid 110, as
well as 24 Signals to support the external memory "bai::kpack"
socket: The 24 backpack signals diffilr somewhat between
versions (due to memory. pin diffe~ences) but always cohsistof
the address bus (t2~lines), the data b,us (8 lines) and the OE, CE,
Vcc,and Vss signals (onaline each), See the Interface Diagram.
TEST MODE t)ELETED
The test mode of the R6500/1 is not available on the Backpack
.
Emulator.
PROD,U(.rr~UPPPFlT
The~ackpilck Emulator is juSt one of the prOducts thaI Rockwell
MiCr~rnputer
;~Ith
l:.1li
The SYSTEM 65
Development System
R6500/1 Personality Module su'p'pOrlsboth hardware and'soft- .'
ware development. Complete in-circuitljser emulation with the,
R6500f1Personality MoQulealiows total sys1",mtestand evalu8-'
tion. With the optlofj~PR
:D
INSTRUCTION CONTROL LINES,
n
In n'
~
IN'l'ERNAL DATA BUS:- DATA {C2 TIME) ~
.
n n n,
n
I,
INTERNAL DATA BUS - REGISTERIPORT CONTROL (C1 TIME)
rr-- r- r - r - ~ r- r -
r--
~
r--
(1
:=,,,
,-
!!l
....m
.
I,
'up,
~. '~
t,h
R~' ~'
f'DitA
J
~
I
.•
,~,~""" ~ ,~,~
Rtgi!,"
Ooocode
~
,o
~
,
o
::r'
I , . el''''
"0
p""s
......
I\)
I:'
,
I
I .0 I I 0Po., 11,;'0
~
Register
~
f-
!
r""-
Fla~
Communl""""n
c8\!2 CLOCK PULSES AFTER OSCILLATOR STABILIZATION.
>8\!2 CLOCK PULSES.
Figure 3-2.
This instruction· is the same operation and format as the BBS
instruction except that a branch takes place if the bit tested
RAM RETENTION MODE
Data Retention Timing
One-Chip Microcomputers
R650Q/11 and R6500/12
3.5 CLOCK OSCfLLATOR
Three customer seleCtable mask options are available for
controlling the device timing. It can be ordered with crystal
or RC oscillator, a divide by 2 or divide by 4 countdown network and for clock master mode or clock slave mode
operation.
a
For 2 MHz internal operations the divide by two option must
be specified.
A reference frequency can be generated with the on-chip
,oscillator using either an external crystal or an external resistor
depending on the mask option selected. The oscillator reference frequency paSses through an internal countdown network (divide by 2 or divide by 4 option) to:obtain the internal
operating frequency (see Figure 3-3a and 3-3b). The external
crystal generated reference frequency is a preferred method
since the resistor method can have tolerances approaching
internal timing can also be controlled by driving the XTLI pin
with an external frequency source. Rgure 3-30 shows typical
connections. If ~TLO is left floating, tile external sOurce is
divided by the internal countdown ne!wor/(. However, if XTLO
is tied to Vss , "the internal countdown network is bypassed
causing the chip to operate at the. frequency of the external
source.
The oper!\tion described above asswned a CLOCK MASTER
MODE maSk option. In this mode a frequence source (crystal,
RC network or externaL source) must be applied to the XTLI
and XTLO pins. !/l2 is a buffered output signal which closely
approximates the internal timing. When a common external
source is used to drive multiple devices the .intemal timing
between devices as well as their Ii2 outputs will be skewed
in time. If skewing represents a system problem it can be
avoided by'the Master/Slave connection and options shown
in Figure 3-4.
50%.
Note:
When operating at a 1 MHz internal frequency place
. a 15-22pf capacitor between XTLO and 9round.
XT.LI
R = 2.4K
tINT
. '' .R6500/11
cE
,
for 2 MHz
..
XTLO
a
fEXT
=1 MHz
= 2X flNT
One device is operated in the CLOCK MASTER MODE and
a second in the CLOCK SLAVE MODE. Mask options in the
SLAVE unit convert the ~2 signal into a clock input pin which
is tightly coupled to the internal timing generator. As a result
the intemal timing of the MASTER and SLAVE units are synchronized with minimum skew. If \he ~2 signal·lo the SLAVE
unit is inverted, the MASTER and SLAVE UNITS WILL
OPERATE OUT OF PHASE. This approach allows the
devices to share external' inemoryusingcycle stealing
techniques.
.
two
a. Resistor Input
2-6 MHz c:::::J,'
IiS00l11 OR /12
Li
'f
.. 2MHz
R65OO/11 INT
XTLO
fEXT
XTLI
= 2X or 4X ~NT
c:::n
b. Crystal Input
MASTER·
.2
XTLO
Vee
2-4 MHz
, ...
3OO: LI
NC' XTLO
fExt
= 2X or 4X. flNT
L__ __.J OUT OF PHASE
6500/11 OR 112
f.INT .. 2 MHz
R65OO/11
.
INVERTER USED
" - --1 WHEN SLAVE IS
:
I TO,OPERATE
~"
'.
(OUTPUl C!:a<:K)
WITH MASTER
XTLI
SLAVE
112
(INPUT CLOCK)
XTLO
VCF
1-2 Mtk
~300.;LI
flNT :;
1 or 2 MHz
R6500/11
XTLO
Vss ".
.
c. Clock Inputs
Figure 3-3. Clock Oscillator Input Options
. Figure 3-4 ... Mast.rlSlave Connections
:,
3
One-Chip Microcomputers
R6500/11 and R6500/12
3.7 INTERRUPT FLAG AEGISTER(IFR)
AND INTERRUPT ENABLE
REGISTER (IER)
3.6 MODE CONTROL REGISTER (MCR)
The Mode COntrol Register contains control bits for the multifunctionl/Oports and mode select bits for Counter A and
Counter B. Its setting, along wfth the setting of "the Serial
Communications Control Register (SCCR); determines the
basic configuration of the device in any application. Initializing this register is one of the first' actions of any software
program. The Mode Control Register bit assignment is shown
in Figure 3-5.
MeR
An IRQ interrupt request can be initiated by any or all of eight
possible sources. These sources are all capable of being
enabled or disabled by the use of the appropriate interrupt
enabled bits in the Interrupt Enable Register (IER). Multiple
simultaneous interrupts will cause the IRQ interrupt request
to remain active until all interrupting conditions have been
serviced and cleared.
The Interrupt Flag Regit;ter contains the information that
indicates which'I/O or counter needs attention. The contents
of the Interrupt Flag Register may be examined at any time
by reading at address: 0011. Edge detect IFR bits may ,be
cleared by executing a RMB instruction at address location
0010. The RMB X, (0010) instruction reads FF, modifies bit
X to a "0", and writes the modified value at address location
0011. In this way IFR bits set to a "1" after the read cycle of
a Read-Modify-Write instruction (such as RMB) are protected
from being cleared. A logic "1" iS'ignored when writing to
edge detect IFR bits.
Addr 0014
Counter S'
I I
Mode 58.t
Bue Mode select
0 - 0 Interval Timer
0-
1 Pulse Ganeration
' , _ 0 Event Counte'r •
11 Pulse Width Meas.
0 - 0 Interval Timer
o-
1 Asymmetric Pulse Generation
, _
0 Event COunter
1 _'_ 1 Rett'1....ab.. Interval Timer
Pon B Latch
(1 - Enabled)
Port OT,I-II_
(0= Tri St~ Hf~~ Im~nce M~e)
Each IFR bit has a corresponding pit in the Interrupt Enable
Register which can be set to a "1" by writing a "1" in the
respective bit position at location 0012. Individual IER bits
may be cleared by writing a "0" inthe respective bit pOSition,
or by RES. If set to a "1", ,~n IRQ will be generated when the
corresponding IFR bit becomes true. The Interrupt Flag Register and Interrupt Enable Register bit assignments are shown
in Figure 3-6 and the functions of each bit are explained in
Table 3-1.
0 - ' XNormld
1 _'- 0 Abbr. Bua
, _
1 Mux'd Bus
Figure
3~5.
Mode Control Register
The use of Counter A Mode Select is shown in Section 6.1.
The use of Counter B Mode Select is shown in Section 6.2.
The use of Port B Latch Enable is shown in Section 4.4.
The use of Port 0 in Tri-State Enable is shown in Section
4.6.
The use of Bus Mode Select is shown in Section 4.5 and 4.6.
3-156
One-Chip Microcomputers
R6500/11 and R6500/12
Addr 0012
tER
tFR
Addr 0011
PAO Positive
Edge Detect
PAl Positive
Edge· Detect
PA2 Negative
Edge Detect
PA3 Negative
Edge Detect
Counter A
Undefflow Flag
cou",.,a
UnclerflowFlag
Receiver
Flag
XMTR
Flag
Figure 3-6.
Interrupt Enable and Flag Registers
Table 3-1
BIT
CODE
Interrupt Flag Register Bit Codes
FUNCTION
IFR 0:
PAD Positive Edge Detect Flag-Set to a "1" when a posilive going edge is detected on PAO.
Cleared byRMB 0 (0010) instruction or by RES.
IFR 1:
PAl Positive Edge Detect Flag-Set to a 1 when a positive going edge is detected on PAl.
Cleared by RMB 1 (0010) instruction or by RES.
IFR 2:
PA2 Negative Edge Detect Flag-Set to.a 1 When a negative going edge is detected onPA2.
Cleared byRMB 2 (0010) instruction or by RES.
IFR 3:
PA3 Negative Edge Detect Flag-Set to 1 wi:len a negative going edge is detected on PA3.
Cleared by. RMB 3 (0010) instruction or by RES.
IFR 4:
Counter A Underflow Flag-Set to a 1 when Counter A underflow occurs. Cleared by reading
the Lower Counter A at location 0018, bywliting to address loeation 001A, or by RES.
IFR 5:
Counter B Underflow Flag-Set to a 1 when Counter B underflow oCcurs. Cleared by reading
the Lower Counter B at location 001 C, by writing to address locatilln 00IE, or byRES;
IFR 6:
Receiv!9f Interrupt Flag-Set to a 1 when any of the. Serial Communication Status Register bits
othrough 3 is 'sei to a 1. CI!9ared when the R!9ceiver Status bits (SCSR 0-3) are cleared or by
RES.
IFR 7:
Transmitter Interrupt Flag-Set to a 1 when SCSR 6 is set toa 1 while SCSR 5 is a 0 Or SCSR
7 is set to a. 1. Cleared when the Transmitter Status bits (SCSR 6 & 7) are Glear~ or by RES.
3-157
One-Chip Microcomputers
R6500/11 and R6500/12
zero. This bit is cleared to logic 0 when the resultant 8 bits
of a data moilement or calculation operation are not all zero.
The R6500 instruct,ion set contains no instruction to specifically set or clear, the Zero Bit. The Zero Bit is, however,
affected by the following instructions; ADC, AND, ASl, BIT,
CMP, CPX, CPY, DEC, DEX, DEY, EOR, INC, INX, INY,
LOA, LOX, LOY, LSR, ORA, PlA, PLP, ROl, ROR, RTI,
, SBC, TAX,TAY,TXA, TSX, and TYA.
3.8 PROCE:SSOR STATUS REGISTER
The a·bit Processor Status Register, shown in Figure 3-7,
contains seven status flags. Some of these flags ate con- '
trolled by the user program; others may be controlled both
by the user's program and the CPU. The R6502 instruction
set contains a number of conditional branch, instructions
which ate designed to allow testing of these flags. Each of
the eight processor status flags is described in the following ,
sections.
3.B.3 Interrupt Disable Bit (I)
The Carry Bit (C) can be considered as the ninth bit of an
arithmetic operation. It is set to logic 1 if a carry "from the
eighth bit has occurred or cleared to logic 0 if no' carry
occurred as the result of arithmetic operations.
The Interrupt Disable Bit (I) is used to control the servicing
of an interrupt request (IRQ). If the I Bit is reset to logic 0,
the IRQ signal will be serviced. If the bit is set to logic 1, the
IRQ signal will be ignored. The CPU will set the Interrupt
Disable Bit to logic 1 if a RESET (RES), IRQ, or Non-Maskable Interrupt{NMI) signal is detected.
The'Carry Bit may be set or cleared under program control
by useef the Set Carry (SEC) or Clear Carry (ClC) instruction, respectively. Other operations whiC!1 affect the Carry Bit
are ADC, ASl, CMP, CPX, CPY, l$R, PlP, ROl, ROR, RTI,
and sec.
The I bit is cleared by the Clear Interrupt Mask Instruction
(Cll) and is set by the Set Interrupt Mask Insiruction (SEI).
This bit is set by the BRK Instruction. The Return from Interrupt (RTI), and Pull Processor Status (PlP) instructions will
also affect the I bit.
3.8.1 Carry Bit (C)
3.8.2 Zero Bit (Z)
The Zero Bit (Z) is set to logic 1 by, the CPU during any data
movement or calculation which sets all 8 bits of the result to
I I II
N
v
BID
II I 1 J
z
C
L=
CARRY (C) 0)
1
= Carry Set
o
=Carry Clear
ZERO (Z)0)
1 ='Zero Result
o :: Non~zero Rt:sult
INTERRUPT DISABLE (I) ~
1
o
=IRQ Interrupt Oi_led
=IRQ Interrupt Enabled
DECIMAL MODE (D)C!)
1
o
=Decimal Mode
= Binary Mode
BREAK COMMAND (8)C!)
, ' .. Break Command
o
=- Non Break Command
OVERFLOW (O)C!)
1 :: OVerflow set
o Overflow Clear
=
NEClATIVE (N) 0)
NOTES
Q) Not initialized by RES
1.:: Negative Value
0= Postive Value
. ® Set to L~ic 1 by RES
Figure 3·7.
Processor Status Register
3-158
On&oChip Microcomputers
R8500/11 ~nd,R6500/12
,This indicator only has meaning when signed arithmetic (sign
and seven magnitude bits) is performed. When theADC or
""SBC instruction is perfdrr:ned, the Overflow Bit is set to logic
1 if the polatity of the sign bit (bit 7) is changed because the
result exceeds +127 or -128; otherwise the bit is,cleared
to logic O. The V bit.may also be cleared by the programmer
using a Clear Overflow (ClV) instruction.
3.8.4 Decimal Mode Bit (D)
The Decimal Mode Bit (D), is used to control ,the ~rithmetic
mode of the CPU. When this bit is set to logic 1" the adder
operates as a decimal adder. When this bit is cleared to logic
0, the adder operates as a straight binary adder. The adder
mode is controlled only by the prc1grammer. The Set Deoimal
Mode {SED) instruction will set the D bit; the Clear Decimal
Mode (ClD) instruction will clear it. The PlP and RTI instructions also effect the Decimal Mode Bit.
The Overflow Bit may also be used with the BIT instruction.
The BIT instruction which may be used to sample interface
devices, alkiws the overflow flag to reflectthe condition of bit.
6 in the sampled field. During a BIT instruction the OVEllrflow.
Bit is set equal to the, content of the bit 6
the d~ta tested
with BIT,instructlon. WhMused in this mode, the overflOw
has nothingto do with signed arithmetic, but is just anoth~r
sense bit for the microprocessor. Instructions which affeCt the'
V fllig ~re ADC, BIT, C?lV, PlP, RTI and sse.
on
CAlfrlON
The Decimal Mode Bit Will either set or clear in an
unpredictable manner upon power application. This bit
rn,ust be initiillized to;the desired state by the tlser program or etron~us results ~ay occur.
3.S.7 Negative Bit (N)
3.8.5 Break Bit (B)
The Negative Bit (N) is used to indicate that the sign bit (bit
7), in theresulting value of a data movement or data arithmetic operation, is set to logic 1. If the sign bit is set to logic
1, the resulting value of' the data movement cit arithmetic '
operation is negative; if the sign bit is cleared, the result of
the data movement or arithmetic operation.is positive. There,
are no instructions that set or clear the Negative Bit since the
Negative Bit represents' only the status' of a result. The
instructions that effect the state of the Negative Bitare:' ADC,
AND, ASl, BIT, CMP, CPX, CPY, DEC, DEX, DEY, EOR,
INC,INX, JNY, lDA, lOX"LDY, LSR, ORA, pLA,PlP: ROl,
ROR, RTI, SBC, TAX, TAY,TSX, TXA, and TYA~
.
Tpe Break Bit (B) is used t~ determine the condition which
Qaused the IRQ service routine to be entered. If the IRQ service routine was entered because the CPU execUted a BRK
command, the Break Bit will be set to logic 1. If the IRQ rou~
tinljl,Wlis entere.d as the result of,an IRQ signal being generated, the B bit will be cleared to logic O. There are no
instructions which can set or clear this bit.
'3.8.6 Overflow Bit (V)
The Overflow Bit (V) is used to indicate that the result of a
signed, binary addition, or subtraction, operation is a value
that cannot be contained in seven bits (-128"" n "" 127).
3-159
3
R650011 t and. R6500/12
One-Chip Microcomputers
SECTION 4
PARALLEL INPUT/OUTPUT PORTS
The R6500/11 has 32 vq lines groupedJnto four 8-bit ports
(PA, PB, P¢,and PD). Ports A throughC may be used either
. for input or output individually or in groups of anY combinatiQn. port D maybe used as all inputs or all o~tputs.
Port D may only be all inputs or all outputs. All inputs is
selected by setting bit S of the Mode Control ReQister (MCRS)
to a "0".
.
.
The status of the input lines can be ihterrogated at any. time
by reading the I/O port addresses. Note that this will return
the actual status of .the input lines, not the data written into
the I/O port registers,
The R6500/12, a 64 pin QUIP device, has three additional
. ports: PE, PF and PG. PEis outputs only; PF andPG are
bidirectional.
Multifunction VO's sUch as Port A and Port C are protected
from normal port I/O instructions when they are programmed
to Perform a multiplexed function.
Internal pull-up resistors (FETs wilh'an impedance range of
3K ..;;' Rpu..;; 12K ohm) m~y be preJVidedon all port pins
except ~ort D and E as a mask option.
Read/Modify/Write' instructions Can be used to modify the
operation of PA, PB, PC, & PD and also ports PF and PG
of the R6500/12. During the Read cycle of a Read/Modify/
Write instruction the" Port VO register is read. For an other
read instructions the port input lines are read. Read/Modifyl
Write instructions are: ASL, DEC, -INC, LSR, RMB, ROL,
ROR, and 5MB.
The direction of the I/O lines are controlled by four 8-bit port
registers located in page zero. This arrangement provides
quick programming access using simple two-byte zero page
address instructions. There are no .direction registers associated with the I/O ports, which simplifies VO handling. The
VO addresses are shown in Table 4-1. Section E.6 shows
the I/O Port Timing.
Outputs for Ports A thru D and Ports E thru G of the R6500/
12 are controlled by writing the. desired VO line output states
into the corresponding I/O port register bit positions. A logic
1 will force a high (>2.4V) output while a logic 0 will force
a low «0.4V) output.
Table 4-1.
110 Port Addresses
Port
Address
A
0000
0001
0002
0003
0004
0005
0006
B
C
0
E
F
G
4.2 OUTPUTS
Port D all outputs is selected by setting MCRS to a "1".
Port E is always all outputs,
4.3 PORT A (PA)
Port A can be programmed via the Mode Control Register
(MCR) and the Serial Communications Control Register
(SCCR) as a standard parallel 8-bit, bit independent, I/O port
or as serial channel VO lines, counter I/O lines, or an input
data strobe for the Port B input latch option. Table 4-2 tabulates the control and usage of Port A.
4.1 INPUTS
In addition to their normal I/O functions, PAO and PAl can
detect positive going edges, and PA2 and PA3 can detect
negative going edges. A proper transition on these pins will
set a corresponding status bit in the IFR and generate an
interrupt request if the respective Interrupt Enable Bit is set.
The maximum rale at which an edge can be detected is onehalf the 02 clock rate. Edge detection timing is shown in Section E.S.
Inputs for Ports A, B, and C and also Ports F and G of the
R6500/12 are enabled by loading logic 1 into all I/O port register bil positions that are to correspond to I/O input lines. A
low «O.8V) input signal will cause a logic 0 to be read when
a read instruction is issued to the port register. A high (>2.0V)
input will cause a logic 1 to be read. An RES signal forces
all I/O port registers to logic 1 thus initially treating all I/O
lines as inputs.
3-160
R6500/11 and R6500/12
One-Chip Microcomputers
Table 4-2.
Port A Control & Usage
PAa I/O
~
MCR4
PORT B LATCH MODE
a
MCR4
SIGNAL
PAO (2)
=
1
SIGNAL
NAME
TYPE
NAME
TYPE
PAa
110
PORT B
LATCH STROBE
INPUT (1)
PA1-PA3110
PA1 (2)
SIGNAL
PA2 (3)
NAME
TYPE
PA3 (3)
PA1
PA2
PA3
I/O
I/O
liD
PA4 I/O
PA4
COUNTER A I/O
MCRO = 1
MCRI = a
SCCR7 = a
RCVR SIR MODE = a
(4)
MCRa,;, 0
MCR1 = a
SCCR? = a
RCVR SIR MODE = a
(4) (5)
SIGNAL
SCCR? = a
SCCR6 = a
MCRI = 1
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
NAME
PA4
I/O
CNTA
OUTPUT
CNTA
I
. TYPE
I
INPUT (1)
SERIAL I/O SHIFT REGISTER CLOCK
SCCR?
SCCRS
=1
=1
RCVR SIR MODE
(4)
SIGNAL
I
I
NAME
XMTR CLOCK
PAS
1
SIGNAL
TYPE
NAME
OUTPUT
RCVR CLOCK
PAS 110
MCR3
MCR2
=
J
I
TYPE
INPUT(1)
COUNTER B I/O
=a
=a
MCR3 ~ a
MCR2 = 1
SIGNAL
MCR3
MCR2
SIGNAL
=
=
1
X
SIGNAL
NAME
TYPE
NAME
TYPE
NAME
I
TYPE
PAS
I/O
CNTB
OUTPUT
CNTB
1
INPUT (1)
SERIAL I/O
XMTR OUTPUT
PA6110
SCCR?
PA6
=a
SCCR?
SIGNAL
=
1
SIGNAL
NAME
TYPE
NAME
TYPE
PA6
I/O
XMTR
OUTPUT
SERIAL I/O
RCVRINPUT
PA?IIO
SCCRS
PA7
=0
SCCR6 = 1
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
PAl
I/O
RCVR
INPUT (1)
3-161
Noles:
(1) Hardware Buffer Float
(2) Pos~ive Edge Detect
(3) Negative Edge Detect
(4) RCVR SIR Mode = 1 when
SCCRS • SCCR5 • SCCR4 = 1
(5) For the following mode combinations PA4 is available as an input
only pin:
SCCRl·SCCR60SCCR5.MCR1
+ SCCR7.SCCR60SCCR40MCRI
+ SCCR?'SCCR60SCCRS
+ SCCR?'$CCRSoSCCR40
One-Chip Microcomputers
R6500/11 and. R6500/12
4.4 PORT S (PS)
4.5 PORT C (PC)
Port B can be programmed as an 8 bit, bit independent 1/0
port. It has a latched input capability which may be enabled
or disabled via the Mode Control Register (MCR). Table
4-3 tabulates the control and usage of Port B. An Input Data
Strobe signal must be provided thru PAD when Port B is programmed to be used with latched input option. Input data
latch timing for Port B is shown in Section E.5.
Port C can be programmed as an 1/0 port and in conjunction
with Port D, as an abbreviated bus, or as a multiplexed bus.
When used in the abbreviated or multiplexed bus modes,
PCO-PC7 function as AO-A3, A12, R/W, A13, and EMS,
respectively, as shown in Table 4-4. EMS (External Memory
Select) is asserted (low) whenever the internal processor
accesses memory area between 0100 and 3FFF. (See
Memory Map, Appendix B). The leading edge of EMS may
be used to strobe the eight address lines multiplexed on Port
D in the Multiplexed Bus Mode. See Appendix E.3 through
E.5 for Port C timing.
Table 4-3,
Port B Control & Usage
Latch
Mode
1/0 Mode
MCR4 = 1
MCR4 = 0
(2)
Signal
Signal
4.6 PORT 0 (PO)
Pin
Name
Name
Type (1)
Name
Type
PBO
PSI
PB2
PB3
PB4
PB5
PB6
PB7
PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7
110
PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
1/0
110
110
110
110
110
110
Port D can be programmed as an 1/0 Port, an 8-bit tri-state
data bus, or as a multiplexed bus. Mode selection for Port
D is made by the Mode Control Register (MCR). The Port D
output drivers can be selected as tri-state drivers by setting
bit 5 olthe MCR to 0 (zero). Table 4-5 shows the necessary
settings for the MCR to achieve the various modes for Port
D. When Port D is se.lected to operate in the Abbreviated
Mode PDO-PD7 serves as data register bits DO-D7. When
Port 0 is selected to operate in the" Multiplexed Mode data
bits DO through 07 are time multiplexed with address bits A4
through All, respectively. Refer to the Memory Maps
(Appendix C) for Abbreviated and Multiplexed memory
assignments. See Appendix E.3 through E.5 for Port D timing.
(1) Resistive pull-up, active buffer pull down
(2) Input data is stored in port B latch by PAO pulse
4.7 PORT E, PORT FANO PORT G (PE,
PF & PG) R6500/12 ONLY
Port E only operates in the Output mode. It provides a Darlington output that can source current at the high (1) level.
Port F and Port G operate identically and can be programmed as .bidirectional VO ports. They have standard
output capability. See Appendix E.5 for Port E, F & Port G
timing.
3-162
R6500/11 andR6500/12
One-Chip·Microcomputers
Table 4·4.
Port C Control and Usage
1/0 Mode
=
Signal
PCO
PCI
PC2
PC3
PC4
PC5
PC6
PC7
Multiplexed
Mode
=1
=0
1
MCR7
MCR6 = 1
MCR7
MCR6
MCR7
0
MCR6 = X
Pin
Name
Abbreviated
Mode
=
Signal
Name
Type
(1)
PCO
PCI
PC2
PC3
PC4
PC5
PC6
PC7
I/O
I/O
1/0
1/0
I/O
1/0
1/0
1/0
Signal
Name
Type
(2)
Name
Type
(2)
AO
AI
A2
A3
AI2
RW
AI3
EMS
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
AO
AI
A2
A3
AI2
RW
AI3
EMS
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
(I) Resistive Pull·Up, Active Buffer Pull·Down
(2) Active Buffer Pull-Up and Pull-Down
Table 4·5.
Port 0 Control and Usage
Abbreviated
Mode
1/0 Modes
Pin
Name
PD~
PDI
PD2
PD3
PD4
PD5
PD6
PD7
MCR7 = 0
MCR6·= X
MCRS = 0
MCR7 = 0
MCR6 = X
MCRS = 1
Signal
Signal
Multiplexed Mode
MCR7 = 1
MCR6 = 0
MCRS = 1
'.
':
Signal
MCR7 = 1
MCRS = 1
MCRS = 1
Signal
Signal
Phase I
Phase 2
Name
Type (1)
Name
Type (2)
Name
Type (3)
Name
Type (2)
Name
Type (3)
PDO
PDI
PD2
PD3
PD4
PD5
PD6
PD7
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
PD~
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
DATAO
DATAl
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A4
AS
A6
A7
AS
A9
AIO
AI1
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
DATAO
DATAl
DATA2
DATA3
DATA4
DATA5
DATA6
DATAl
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(1) Tri-State Buffer
(2) Tri-State Buffer
(3) Tri·State Buffer
PDI
PD2
PD3
PD4
PD5
PD6
PDl
in High Impedance Mode
in Active Mode
in Active Mode Only During the Phase 2 Portion of a Write Cycle
3-163
One-Chip Microcomputers
R6500111 and R6500/12
SECTION 5
SERIAL INPUT/OUTPUT CHANNEL
ASVNCHRONOUS MOOE WITHOUT PARITY
The device provides a full duplex Serial 110 channel with programmable bit rates and operating modes. The serial 110
functions are controlled by the Serial Communication Control
Register (SCCR). The SCCR ,bit assignment is shown in
Figure 5-1. The serial bit rate is determined by Counter A
for all modes except the Receiver Shift Register (RCVR
SIR) mode for which an external shift clock must be provided.
The maximum data rate using the internal clock is 62.5K bits
per second (@ ¢2 = 1 MHz). The transmitter (XMTR) and
receiver (RCVR) can be independently programmed to
operate in different modes and can be independently enabled or disabled.
8-BIT DATA
$-8IT DATA
6-81T DATA
S-SIT DATA
o P~rily Disable
1
1
o
o
IPA~ITY I
IPA~ITY I
2 STOP
2 STOP
SHIFT REGISTER MODE 8-SIT OAT A
M.,
I Parily Enable
0 - 8 Bils/Char
1 - 7 Bits/Char
0-6 Bils/Char
1 _ 5 Bils/Char
I
WORO .... +1
SHIFT'REGISTER CLOCK (PA4)
o XMTR "
RCVR ASYN Mode
1 XMTR ASVN, RCVR SIR
X XMTR SIR, RCVR ASYN
Figure 5-2.
Transmitted Data Modes
In the SIR mode, eight data bits are always shifted out. Bitsl
character and parity control bits are ignored. The serial data
is shifted out via the SO output (PA6) and the shift clock is
available at the CA (PA4) pin. When the transmitter underruns in the SIR mode the SO output and shift clock are held
in a high state.
o RCVR Disable
1 RCVR Enable
o XMTR Disable
1 XMTR Enable
Figure 5-1.
iPA~ITY I ST~P I
8·BIT OATA
SCCR
o
o
2 STOP
Serial Communication Control Register
Except for the Receiver Shift Register Mode (RCVR SIR), all
XMTR and RCVR bit rates will occur at one sixteenth of the
Counter A interval timer rate. Counter A is forced into an
interval timer mode whenever the serial 110 is enabled in a
mode requiring an internal clock.
The XMTR Interrupt Flag bit (IFR?) is controlled by Serial
Communication Status Register bits SCSR5, SCSR6 and
SCSR?
Whenever Counter A is required as a timing source it must
be loaded with the hexadecimal code that seleds the data
rate for the serial I/O Port. Refer to Counter A (paragraph
6.1) for a table of hexadecimal values to represent the desired
data rate.
5.2 RECEIVER OPERATION (RCVR)
IFR?
=
SCSR6 (SCSR5 + SCSR?)
The receiver and its selected control and status functions are
enabled when SCCR-6 is set to a "1." In the ASYN mode,
data format must have a start bit, appropriate number of data
bits, a parity bit (if enabled) and one stop bit. Refer to paragraph 5.1 for a diagram of bit allocations. The receiver bit
period is divided into 8 SUb-intervals for internal synchronization. The receiver bit stream is synchronized by the start
bit and a strobe signal is generated at the approximate center
of each incoming bit. Refer to Figure 5-3 for ASYN Receive
Data Timing. The character assembly process does not start
if the start bit signal is less than one-naif the bit time after a
low level is detected on the Receive Data Input. Framing
error, over-run, and parity error conditions or a RCVR Data
Register Full will set the appropriate status bits, and any of
the above conditions will cause an Interrupt Request if the
Receiver Interrupt Enable bit is set to logic 1.
5.1 TRANSMITTER OPERATION (XTMR)
The XTMR operation and the transmitter related controll
status functions are enabled by bit? of the Serial Communications Control Register (SCCR). The transmitter, when in
the Asynchronous (ASYN) mode, automatically adds a start
bit, one or two stop bits, and, when enabled, a parity bit to
the transmitted data. A word of transmitted data (in asynchronous parity mode) can have 5, 6, ?, or 8 bits of data.
The nine data modes are in Figure 5-2. When parity is disabled, the 5, 6, ? or 8 bits of data are terminated with two
stop bits.
3-164
One-Chip Nicrocomputers
R6500/11 andR6500/12
Serlll
1
Input - ,
StartSN
LSB
::....._-'-----'I
I
received data has a parity error. This bit is cleared
by reading the Receiver Data Register or by RES.
SCSR 3: Framing Error-Set to a logic 1 when the received
data contains' a zero bit-after the last data or parity
bit in the stop bit slot. Cleared by reading the
Receiver Data Register or by RES. (ASYN Mode
only),
SCSR 4: Wake-Up-Set to a logic 1 by writing a "1" in bit
4.of address: 0016. The Wake-Up bit is cleared by
RES or when the receiver detects a string of ten
consecutive 1'so When the Wake-Up bit is set
SCSRO through SCSR3 are inhibited.
I
Stop BH Stap Bit '
• SerIollnput 0011 SlllItecIln
Figure 5-3. ASYN Receive Data Timing
In the SIR mode, an external shift clock must be provided at
CA (PM) pin along with 8 bits of serial data (lSB first) at the
SI input (PA7). The maximum data rate usinQ an external
shift clock is one-eighth the internal clock rate. Refer to
Figure 5-4 for SIR Mode Timing.
:::;;~~I 1
1
SCSR 5: End of Transmission-Set to a logic 1 by writing
a "1" in bit position 5 of address: 0016. The End
of Transmission bit is cleared by RES or upon
writing a new data word into the Transmitter Data
Register. When the End-of-Transmission bit is true
the Transmitter Register Empty bit is disabled until
a, Transmitter Under-Run occurs.
::'"---r---,----,,.---,-
SCSR 6: Transmitter Data Register Empty-Set to a logic
1 when the contents of the Transmitter Data Register, is transferred to the Transmitter Shift Register. Cleared upon writing new data into the
Transmtt Data Register. This bit is initialized to a
logic 1 by RES.
SCSR 7: Transmitter Um;Jer-Run-Set to a logic 1 when the
last data bit is transmitted if the transmitter is in a
SIR Mode or when the last stop bit is transmitted
if the XMTR is in the ASYN Mode while the Transmitter Data' Register Empty Bit is set. Cleared by
a transfer of .new data into the Tfansmitter Shift
Register, or by RES.
Data In
Shlft~~
External
Clock
Serial
Output
Shift
I
1
: ..._ - - , - _ - - , - _ - - , _ - - , _
.L...-_-'-_--'_ _"-
___
Data Out
,CIOCk~~
• Serial Input Data Shifted In
.. Serial Output Data Mak.. Transition
Figure 5-4. SIR Mode Timing
A RCVR interrupt (IFR6) is generated whenever any of
SCSRO-3 are true.
SCSRI '7, \
e
I~
\ 4 \ 3\
2\
1 '\
0
l
5.3 SERIAL COMMUNICATION STATUS
REGISTER (SCSR)
\Addr 0016
RCVROota
Reg Full
RCVR Ow......Run
The Serial Communication Status Register (SCSR) holds
information on various communication error conditions, status
of the transmitter and receiver data registers, a transmitter
end-of-transmission condition, and a receiver idle line condition (Wake-Up Feature). The SCSR bit assignment is shown
i'n Figure 5-5. Bit assignments and functions of the SCSR are
as follows:
'
Parity Error
Frame Error
Waka-Up
End of T ... n....I••lon
XMTR Data Reg Empty
SCSRO: Receiver Data Register Full -Set to a logic 1 when
a character is transferred from the Receiver Shift
Register to the Receiver Data Register. This bit is
cleared by reading the ReceiVer Data Register, or
by RES arid is disabled if SCCR6 = O. The SCSR
, 0 btt will not be set to a logic'1 if the received data
contains an error condition, instead, a corresponding error bit will be set to a logic 1.
XMTR Under-Run
Figure 5-5.
SCSR Bit Allocation
5.4 WAKE-UP FEATURE
In a multi-distributed microprocessor or microcomputer
applications, a destination address is usu'l.lIy included at the
beginning of the message. The Wake-Up Feature allows
non-selected CPU's to, ignore the remainder of the message
until the beginning of the next message by setting the WakeUp btt. As long as the Wake-Up flag is true, the Receiver
Data Register Fu!~ Flag, remaIns false. the Wake-Up btt is
automatically cleared when the receiver detects a string of
eleven consecutive 1's which indicates an idle transmit line.
When the next byte is received, the Receiver Data Register
Full Flag signals the CPU to wake-up and read the reqeived
data.
SCSR 1: Over-Run Error-Set to a logic 1 when a new character is transferred from the Receiver Shift Register, with the last character stiU in the Receiver
Data Register. This bit is cleared by reading'the
Receiver Data Register, or by RES.
SCSR 2: Parity Error-Set to logic 1 when the RCVR is in
the ASYN Mode, Parity Enable bit is set, and the
3-165
3
One-Chip Microcomputers
R6500/11 and R6500112
SECTION 6
COUNTER/TIMERS
The device contains two 1.6-bit counters (Counter A and
Counter B) and three 16-bit latches associated with the
counters. Counter A has one 16-bit latch and Counter B has
two 16-bit latches. Each counter can be independently programmed to operate in one of four modes:
Upper Latch A before the contents of the 16-bit latch are
transferred to Counter A. Counter A is set to the latch value
whenever Counter A underflows. When Counter A decrements from 0000 the next counter value will be the latch
value. not FFFF, and the Counter A Underflow Flag (IFR 4)
will be set to "1". This bit may be cleared by reading the
Lower Counter A at location 0018,· by writing to address
location 001 A, or by RES.
. Counter B
Counter A
• Retriggerable Interval Counter
• Asymmetrical Pulse
Generation
• Interval Timer
• Event Counter
• Pulse width
measurement
• Pulse Generation
• Interval Timer
• Event Counter
Counter A operates inany of four modes. These modes are
selected by the Counter A Mode Control bits in the Control
Register.
Operating modes of Counter A and Counter B are controlled
by the Mode Control Register. All counting begins at the
initialization value and decrements. When modes are selected
requiring a counter input/output line, PA4 is automatically
selected for Counter A and PA5 is automatically selected for
Counter B (see Table 4.2).
a
1. When the Counter is decremented from 0000, the next
Counter value is the Latch value (not FFFF).
2. When a write operation is performed to the Load Upper
Latch and Transfer Latch to Counter address 001 A,
the Counter is loaded with the Latch value. Note that
the contents of the Accumulator are loaded into the
Upper Latch before the Latch value is transferred to
the Counter.
The Counter value is decrem'ented by one count at the ~2
clock rate. The 16-bit Counter can hold from·l to 65535
counts. The Counter Timer capacity ;s therefore 1",s to 65.535
ms at the 1 MHz ~2 clock rate or 0.5 "'s to 32.767 ms at the
2 MHz ~2 clock rate. Time intervals greater than the maximum Counter val.ue can be easily measured by counting
IRQ interrupt requests in the counter IRQ interrupt routine.
I
COUNTER UNDERFL.OW
COUNTER INTERRUPT ENABLED
I~ET ANY TIME BEFORE
COUNTER UNDERFLOW FLAG
Figure 6-1.
COUNTER UNDERFLOW
1
0
1
In the Interval Timer mode the Counter is initialized to the
Latch value by either of two conditions:
.,
I (UL. LL)
0
1
Mode
Interval Timer
Pulse Generation
Event Counter
Pulse Width Measurement
6.1.1 Interval Timer
Counter A can be started at any time by writing to address:
001 A. The contents of the accumulator will be copied into the
I
0
The Cou nter is set to the Interval Timer Mode (00) when a
RES signal is generated.
The 16-bit latch contains the counter initialization value, and
can be loaded at any time by executing a write to the Upper
Latch Aat location 0019 and the Lower Latch A at location
0018. In either case, the contents of the accumulator are
copied into the applicable latch register.
I
0
The Interval Timer, Pulse Generation, and Pulse Width Measurement Modes are ~2 clock counter modes. The Event
Counter Mode counts the occurrences of an external event
on the CNTR line.
Counter A consists of
16-bit counter and a 16-bit latch
organized as follows: Lower CounterA (LCA), Upper Counter
A (UCA), Lower Latch A (LLA), and Upper Latch A (ULA).
The counter contains the count of either ~2 clock pulses or
external events, depending on the counter mode selected.
The contents of Counter A may be read any time by executing a read at location 0019 for the Upper Counter A and
at location 001A or location 0018 for the Lower Counter A.
Aread at location 0018 also clears the Counter A Underflow
Flag (IFR4).
--'-_~-'-_ _-'-_=--...JI,---",(UL. LL)
MCRO
(bit 0)
1
6.1 COUNTER A
COUNTER
MCR1
(bit 1)
.'1
I
I
1,---:------
When Counter A decrements from 0000, the Counter A
Underflow (IFR4) is set to logic 1. If the Counter A Interrupt
Enable Bit (IER4) is also set, an IRQ interrupt request will be
generated. The Counter A Underflow bit in the Interrupt Flag
Register can be examined in the IRQ interrupt routine to
determine that the IRQ was generated by the Counter A
Underflow.
I
Interval Timer Timing Diagram
3-166
One-Chip Microcomputers
R6500/11 and R6500/12
While the timer Is operating in the Interval TImer Mode, PA4
operates as a PA I/O bit.
The Counter A underflow flag will be set only when the count
in the timer reaches zero. Upon reaching zero the timer will
be loaded with the latch value and continue counting down
as long as the CA pin is held low. After the counter is stopped
by a high level on CA, the count will hold as long as CA
remains high. Any further low levels on CA will again cause
the counter to count down from its present value. Th& state
of the CA line can be determined by testing the state of PA4.
A timing diagram of the Interval Timer Mode is shown in
Figure 6-L
6.1.2 Pulse Generation Mode
In the 'Pulse Generation mode, the CA line operates as a
Counter Output. The line toggles from low to high or from
high to low whenever a Counter A Underflow occurs, or a
write is performed to address 001A.
A timing diagram for the Pulse Width Measurement Mode is
shown in Figure 6.3.
The normal output waveform is a symmetrical square-wave.
The CA output is initialized high when entering the mode and
transitions low when wr~ing to 001 A.
--i
r-
TpDSU
II
--'1
cNT,:;------\\..2,_ov_ _ _ _ _ _ _ _
Asymmetric waveforms can be generated 'if the value of the
latch is changed after each counter underflow.
COUNT
A one-shot waveform can be generated by changing from
Pulse Generation to Interval Timer mode after only one
occurrence of the output toggle condition.
No>
Figure 6-3.
N-2
I
N·3
Pulse Width Measurement
6.1.3 Event Counter MOde
In this mode the CA is used as an Event Input line, and the
Counter will decrement with eaoh rising edge detected on
this line. The maximum rate at which this edge can be
detected is one-half the ¢2 clock rate,
6.1.5 Serial 1/0 Data Rate Generation
Counter A also provides clock timing for the Serial I/O which
establishes the data rate for the Serial lIO' port. When the
Serial 110 is enabled, Counter A is forced to operate at the
internal clock rate. Counter A is not required for the RCVR
SIR mode. The Counter I/O (PA4) may al56 be required to
support the Serial I/O (see Table 4-2).
The Counter can count up to 65,535 occurrences before
underflowing: As in the other modes, the Counter A Underflow bit (IER4) is set to logic 1 if the underflow occurs.
Figure 6.2 is a timing diagram of the Event Counter Mode.
Table 6-1 identifies the values to be loaded in Counter A for
cl,ock rate of 1 MHz
selecting standard data rates with a
and 2 MHz. Although Table 6-1 identifies only the more
common'data rates,any data rate from 1 to 62.5K bps can
be selected by using the formula:
P2
N
=
¢2
16 x bps
-1
where
N
Figure 6-2.
Event Counter Mode
6.1.4 Pulse Width Measurement Mode
decimal value to be loaded into Counier A using
its hexadeCimal equivalent.
the clock frequency (1 MHz or 2 MHz)
the desired data rate.
NOTE
This,mode allows the accurate measurement of a lOW pulse
duration on the CAline. The Counter decrements by one
count at the ¢2 clock rate as long as the CA line is held in
the low state. The Counter is stopped when CA is in the high
state.
In Table 6-1 you will notice that the standard data rate
and the ,actual' data rate may be slightly different.
Transmitter and receiver ,errors of 1.5% or less are
acceptable. A revised clock rate is included In Table
6-1 for those baud rates which fall outside this limit.
3-167
R6500/11 and R6500/12
Table 6-1.
Standard
Baud
Rata
..
50
75
110
150
300
600
1200
2400
3600
4800
7200
9600
One-Chip Microcomputers
6.2.1 Retriggerable Interval Timer Mode
Counter A Values for Baud Rate Selection
Hexadecimal
,V.lue
1 MHz 2 MHz
04E1
0340
0237
01Ao
OOCF
0067 .
0033
0019
0010
OOOC
0008
0006
09C3
0682
046F
0340
01AO
OOCF
0067
0033
0021
0019
0010
OOOC
Actual
Beud
Rate
At
1 MHz
2 MHz
50,00
75.03
110.04
149.88
300.48
600.96
1201.92
2403.85
3676.47
4807.69
6944.44
8928.57
50,00
74.99
110.04
150.06
299.76
600.96
1201.92
2403.85
3676.47
4807.69
7352.94
9615.38
When operating in the Retriggerable Interval Timer mode,
Counter B is initialized to the latch value by writing to address
001 E, by a Counter B underflow, or whenever a positive edge
occurs on the CB pin (PA5). The Counter B interrupt flag will
be set if the counter underflows before a positive edge occurs
on the CB line. Figure 6·4 illusttates the operation.
Clock Rate
Needed
To Get
Standard
iBaud Rate
1 MHz 2 MHz
1 ,0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
0.9792
1.0000
1.0368
1.0752
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
1 .9584
2.0000
1.9584
2.0000
LATCH VALUE
IOOOO~~~------~---}-----~----~--------1
COUNTER
RESET BY
U_N_D_E_R_FL_O_W_S_-,r--14/ SOFTWARE
COUNTER B
I
!
FLAG
6.2 COUNTER B
Figure 6~4.
Counter B consists ola 16-bit counter and tWo 16-bit latches
organized as follows: Lower Counter B (LCB), Upper Counter
B (UCB), Lower Latch B (LLB), Upper Latch B (ULB), Lower
Latch C (LLC), and Upper Latch C (ULC).Latch Cis used
only in theasymm!ltrical pulse generation mode. The counter
contains the count of either ¢2 cloc;k pulses or external.
events depending on the counter mode. selected. The contents of Counter B may be read any time by executing a read
at location 0010 for the Upper Counter B and at location
001 E or 001 C for the Lower Counter B. A read at location
001C also clears the Counter B UnderflOW Flag.
Counter B Retriggerable Interval Timer Mode
6.2.2 AsymmetricliIl Pulse Ge",eration. Mode
Counter Bhas a special Asymmetrical Pulse Generation
Mode whereby a pulse train with programmable pulse width
and period can be generated without the processor interven·
tion once the latch values.are initialized.
In this mode, the 16-bit Latch B is initialized with. a value
which corresponds to the duration betWeen pulses (referred
to as 0 in the following descriptions). The 16-bit Latch C is
initialized with a value which corresponds to the desired
pulse width (referred to as P in the following descriptions).
The initialization sequence for Latch Band C and the starting
of a counting sequence are as follows:
Latch B contains the counter initialization value, and can be
loaded at any time by executing a write to the Upper Latch
B at location 0010 and the Lower Latch B at location 001 C.
In each case, the contents of the accumulator are copied into
the applicable latch register.
1. The lower 8 bits of P are loaded into LLB by writing to
address 001 C, and the upper 8 bits of P are loaded
into ULB and the full 16 bits are transferred to Latch
C by writing to address location 0010. At this point
both Latch B and Latch C contain the value of P.
Counter B can be initialized at any time i::ly writing to address:
001 E. The contents of the accumulator is copied into the
Upper Latch B before the value in the 16-bit Latch B is transferred to Counter B. Counter B will also be set to the latch
value and the Counter B Underflow Flag bit (IFR5) will be set
to a "1" whenever Counter B underflows by decrementing
from 0000.
2. The lower 8 bits of 0 are loaded into LLB by writing to
address 001 C, and the upper 8 bits of 0 are loaded
into ULB by writing to address location 001 E. Writing
to address location 001 E also causes the contents of
the 16-bit Latch B to be downloaded into the Counter
B and causes the CB output to go low as shown in
Figure 6·5.
IFR 5 may be cleared by reading the Lower Counter B at
location 001 C, by writing to address location 001 E, or by
RES.
3. When the Counter B underflow occurs the contents of
Counter B operates in the same manner as Counter A in the
Interval Timer and Event Counter modes. The Pulse Width
Measurement Mode is replaced by the Retriggerable Interval
Timer mode and the Pulse Generation mode is replaced by
the Asymmetrical Pulse Generation Mode.
the Latch C is loaded into the Counter B, and the CB
output toggles to a high level and stays high until
another underflow occurs. Latch B is then down-loaded
and the CB output toggles to a low level repeating the
whole process.
3-168
One-Chip Microcomputers
R6500/11 and R6500112
SECTION 7
POWER ON/INITIALIZATION CONSIDERATIONS
7.1 POWER·ON TIMING
7.3 RESET (RES) CONDITIONING
After application of Vee and VRR power to the R6500/1'l, RES
must be held low for at least eight ~2 clock cycles after Vee
reaches operating range and the internal oscillator has stabilized. This stabilization time is dependent upon the input
Vee voltage and performance of the internal OSCillator. The
clock can be monitored at ¢2 (pin 3}. Figure 7-1 illustrates
the power turn-on waveforms. Clock stabilization time is typically 20 ms.
.
When RES is driven from low to high the R6500/11 is put in
a reset state causing the registers and I/O ports to be configured as shown in Table 7-1.
+5_______
Vee
Table 7-1.
7
Registers
Processor Status
Mode Control (MCR)
Int. Enable (IER)
Int. Flag (IFR)
Sar. Com. Control (SCCR)
Sar. Com. Status (SCSR)
II
o--<:?~:~ ~"N" ~nC~~~Kn~TABILIZATION TIME
XTLO~ uu u
U U
RES Initialization of I/O Ports and Registers
uLruum.n.nnIl
6
5
4
3
- - - - 0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
I)
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
0
0
0
0
0
- -
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Ports
'2
/--:--
-I'
8 '2CI,.OCKSI
CYCLES MIN
r-
PA
PB
PC
PO
'
Figure 7-1. Power Turn-on Timing Detail
7.2 POWER·ON RESET
1
n
23
r
7_4 INITIALIZATION
Any initialization process for ,the R6500l11. should include a
RES, as indicated in the Preceeding paragraphs. After stabilization of the internal clock (if a power on situation) an
initialization subroutine should be executed to perform it 2 of the Processor Status Register-and initiate a reset vector fetch at
address FFFC and FFFD to begin user.im:lgram execution.
All of the I/O ports (PA, PB, PC, PO) will be forced to the
high (logic 1) state. All bits of the Control Register will
cleared to logic 0 causing the Interval Timers counter mode
(mode 00) to be selected and causing all interrupt eriabled
bits to be reset.
CB
OUTP!JT
Latch
Latch
Latch
Latch
1. The Stack Pointer should be set
2. Clear or Set Decimal Mode
3. Set or Clear Carry Flag
4. Set up Mode Controls as required
5. Clear Interrupts
nL--__
4
A typical initialization subroutine could be as follows:
I--D-Ipl-
LOX
TXS
CLD
SEC
1&3. Counter B __ Late!! B (D)
2&4. Counter B __Latch C (P)
Figure 6-5. Counter B Pulse Generation
CLI
3-169
Loae!' stack pointer starting address into X
Register
..
Transfer X Register value to Stack Pointer
Clear Decimal Mode
Set Carry Flag
Set:up Mode Control and
special function
registers as required
Clear Interrupts
II
86500/11 and R6500/12
One-Chip Microcomputers
APPENDIX A
ENHANCED R65021NSTRUCTION SET
This appendix contains a summary of the R6502 instruction
set. For detailed information, consult the R6502 Microcomputer System Programming Manual, Document 29650 N30.
The four instructions notated with a * are added instructions
to.enhance th¢ standard 6502 instruction set.
A.1 INSTRUCTION SET IN ALPHABETIC
SEQUENCE
ADC·
AND
ASL
Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)
*BBR
*8BS
BCC
BCS
BEQ
BIT
BMI
BNE
BPl
BRK
BVC
BVS
Branch on Bit Reset Relative
Branch on Bit Set Relative
Branch on Carry Clear
Branch on Garry Set
Branch on. Result lero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set
ClC
CLO
CLI
ClV
.CMP
CPX
CPY
Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow Flag
Compare Memory and Accumulator
Compare MemOJY and Index X
Compare Memory and Index Y
DEC
DEX
DEY
Decrement Memory by One
Decrement Index X by One
Decrement Ind€!x Y by One
EOR
"Exclusive-Or" Memory with
Accumulator
INC.
INX
INY
Increment Memory by One
Increment Index X by One
InCrement Index Y by One
JMP
JSR
Jump to New Location
Jump to New location Saving Return
Address
LDA
LOX
lOY
lSR
Load Accumulator with Memory
Load Index X with Memory
load Index Y with Memory
Shift One Bit Right (Memoryor
Accumulator)
NOP
No Operation
ORA
"OR" Memory with Accumulator
PHA
PHP
PLA
PlP
Push Accumulator on Stack
Push Processor Status 011 Stack
Pull Accumulator from Stack
Pull Processor Status from Stack
*RMB
ROl
Reset Memory Bit
Rotate One Bit left (Memory or
Accumulator)
Rotate One Bit Right (Memory or
Accumulator)
Return from Interrupt
Return from Subroutine
ROR
RTI
RTS
SBC
SEC
SED
SEI
*SMB
SM
STX
STY
TAX
TAY
TSX
TXA
TXS
TYA
3-170
Subiract Memory from Accumulator with
Borrow'
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Accumulator to Index X
Accumulator to Index Y
Stack Pointer tv Index X
Index Kto Accumulator
Index X to Stack Register
Index Y to Accumulator
lJ
A.2 INSTRUCTION SET SUMMARY TABLE
en
en
R6500/11 ,INSTRUCTION SET
INSTRUCTIONS
PROCESSOR STATUS
CODES
76543210
MNEMONIC
ADC
B D I Z C
OPERAnOtl
A·M-C--A
(4)(1)
AND
ASl
A M--A
(1)
C- cz::::==!iJ --0
BBR!#(D-7)]. Branch on M.=O (5)12)
.BBsr#(O-7)1 Branch on M.""
(5)12)
Bce
Branch on C = 0 (2)
BGS
BEQ
BIT
8MI
BNE
BPL
BRK
Branch on C= 1
BranchonZ=l
'AI\M
Branch on N = 1
Branctl on Z",O
Branch on N = 0
Branch-onV""
etC
o--c
CLD
ell
O--D
0--1
elV
o-v
eMP
CPX
CPY
DEC
OEX
DEY
A
X
Y
M
IINY
JSR
......
LOA
M--oA (II
LOX
LOY
LSR
M---X
M-oY
0-
NOP
No Operation
'ORA
AVM--A (1)
C
091 2 12 100
A--Ms 5 - 1--5
PHP
PLA
P.....Ms S - 1--5
5·1--5 Ms-A
PlP
S~I-S
~
Rtmlnt -
ATS
SBC
AIm SubA- M -C-A
SEC
SED
SEI
l--C'
1--0
l-T
TAX
TAY
A-X
A--V
S-X
TXA
X...... A
TXS
X-S
TVA
V-A
B858
3D
4
3
2" 1E
7
3
3
Z C
j
N
Z
Z C
Q.
~
~~I ~~I !~1 ~~"I~~t ~~I :~l~~
m
M.
M~'
(1)
~
....
••• Z
N
.
·3
3
3
4
• 0
.' 0
• 0
4, I
C8EB
• 0
N
N
N
N
N
N
N
N
N
N
21 D11 51 2 I 051 4 I 2 1DD 1 4 I 3 10914 13
50FE
61 21.5' I5121 55F6
59 I 4 13
6C
~I~I!H'I'IEA ,
0848
28
A' 6 2 B,
,
0'
6
2
11
5
2
15
4
2
10
Z
B61 41,2
5 TTITT I 1:
B442BC4
56625E7
2" 2A
66
4
E5
40
60
3B
2
8E438632
aC43"8432
F878
Z
Z
Z C
3
4 r 3 1 19 I 4 I 3
II!
AA
AS
BA
I
page
3. Carry not := Borrow
4. If in decimal mode Z flag is invalid
accumulator must be checked on zero result.
5. Effects 8-bit data field of the specified zero page address.
r
I
I I
1
1"
Z
Z C
Z C
(Restored)
4
,
N •••••
N
N
12 J,l E'I 61 21 "I 5I2IF51 4I2IFO I I IF91 4I
2
2
z •
IRestored)
111111 111~:I:ld~~
2
N •••••
071171 27}37 1471 571 67 1771 •
3
N V
3
!.'!61 21·'1 612\ :1 : I: 190 I 51 31 ' .t 5I 3
96
2,
9A 2. ,
I .. 2 ,
SA
NOTES
1. Add 1 to N if page boUndary is crossed
2. Add 1 10 N jf branch occurs 10 same "page
Add 2 10 N if branch occurs 10 dtlf8rent
3
8014131 ~13121
(5)
2
5
C
C
C
I 5 13
68
2E6E 66 26 5 2 SA 2
E912121EO 3
1
~ I ~ 1~
OOl61210Ei713
451312
....
m
N •
N V
39
·1·
Cl1 61
~I~ I:
Ms-P
(5)
ATI
T5X
2
6
30
3 E6
4C 36 33.
AOI TI!~ 4 "
4E 46
3
A222AE
A022AC
(1)
(1)
PHA
Y-M
4
16
BOFO
00 12 /2
CSE4
C4
C6
C9I'ITO
CE
401212140EE
r:r::=:J1l -
STY
35
(2)
(2)
Jump to New loe
Jump Sub
X-M
2
10
E022EC
C02-2CC
Co>
STx
5
00 I 7 /1
(1)
A'r/M-oA
M·l-M
x· t--X
Y-l·---Y
5MB(#(O-7)! l-h\.
STA
A-M
31
90
(2)
(21
X l--X
EOR
ROl
ROR
2-
(2)
Y I-V
RMB(#(O-7JJ O-M.,
6
2C1413124!.312
M'(1)
M
M
l __ M
INC
INX
JM.P
21
OA 1211
~ I~ I~
......-
.!...
65
2922204325
OE 6 3 06
(2)
(2J
Break
&anch On V =0
BVe
BVS
6' 161 2!7' 1512!75141217o 1413179
69,2!2! 6°141 31
~
....
1+ IBTT,!"7 t:
07
E7
:
,. ,. . ,
Z (3)
N •
M.
X
Y
A
M
Ms
M..
M7
Index X
Index Y
Accumulator
A
Memory per effective address
Memory per stack pointer
Selecter zero page memory bit
Memory Bil 7
...
II
V
#
j
o
:r
-a'
:F7 1
5:
N
N
N
LEGEND
,o
C:5"
• Z
Memory Bit 6
o
Add
= Subtract
o
And
= Or
Exclusive Or
Number of cycl8s
= Number of Bytes
=
8
o
~c
Ii
til
One-Chip, Microcomputers
R6500/11 and R6500/12
A.3 INSTRUCTION CODE MATRIX
0
BRK
0
LSD
o
~
o
2
3
a
6
7
8
ORA
ZP
2 3
ASL
ZP
2 5
RMBO
ZP
PHP
Implied
1 3
ORA
IMM
BPL
ORA
Relative (INO), Y
2 2-2 5-
ORA
ZP, X
2 4
ASL
ZP, X
2 6
RMBI
ZP ,
CLC
Implied
1 2
ORA
ABS,Y
3 4-
AND
ZP
2 3
ROL
Zp
2 5
RMB2
ZP
AND
ZP, X
RMB3
ZP
2 4
ROL
ZP, X
2 6
RTI
EOR
Implied (INO,X)
1 6
2 6
EOR
ZP
2 3
LSR
ZP
2 5
RMB4
ZP
BVC
EOR
Relative (IND);Y
eOR
ZP,X
2 4
LSR
ZP, X
2 6
RTS
AOC
Implied (INO,X)
1 6
2 6
AOC
ZP
2 3
BVS
ADC
Relative (INO, Y)
2-2
2 5-
3
JSR
AND
Absolute (INO,X)
3 6
2 6
2
BIT
ZP
2 3
2-'
2--
2
2 6
C
D
e
lOY
IMM
2 2
2 6
lOX
IMM
2 2
BCS
lOA
Relative (INO), Y
2 2--
2 5-
CPY
IMM
CMP
(INO!X)
2 2
26
CPX
IMM
SBC
(INO, X)
2 6
3
AND
IMM
2
2
RMBS
ZP
2 5
Cli
Implied
1 2
EOR
ABS,Y
3 4-
ROR
ZP
2 5
RMB6
ZP
2 5
PLA
Implied
1 4
AOC
Zp, X
2 4
ROR
ZP, X
2 6
RMB7
ZP
2 5
SEI
Implied
1 2
STY
ZP
2 3
STA
ZP
2 3
STX
ZP
5MBO
ZP
2 3
2 5
DEY
Implied
1 2
STY
ZP, X
STX
ZP, Y
2 4
5MB1
ZP
2 4
STA
Zp, X
2 4
LOY
ZP
2 3
LOA
ZP
LOX
ZP
5MB2
ZP
2 3
2 3
2 5
lOY
ZP, X
2 4
LOA
ZP, X
2 4
LOX
ZP, Y
5MB3
ZP
2 4
2
CPY
ZP
2 3
CMP
ZP
2 3
DEC
ZP
2 5
CMP
Zp,X
DEC
ZP,X
2 4
2 6
SBC
ZP
2 3
SBC
Zp,X
2 4
CPX
·zp
2 3
2
PLP
Implied
1 4
EOR
IMM
BEQ
sec
Relative (INO), Y
2-2
2 5-
a
5
2
. PHA
Implied
1 3
BNE
CMP
Relative (INO),Y
2 2-2 5-
2 2
F
LOA
(INO, X)
5
2
2 2
AND
ABS,Y
3 4'
5-
BCC
STA
Relative (INO, Y)
2 2'2 6
2 5
SEC
Implied
1 2
2 5-
STA
(INO,X)
B
4
BMI
AND
Relative (INO, Y)
2
A
A
5
BRK
ORA
Implied (INO, X)
1 7
2 6
4
2 5
2
5
2 5
TYA
Implied
1 2
2
2
AOC
IMM
2
2
Implied
1 7
B
-OPCode
-Addressing Mode
-,-Instruction Bytes; Machine Cycles
BIT
ABS
3 4
ROL
Accum
1 2
JMP
ABS
3 3
LSR
Accum
1 2
JMP
Indirect
3 5
ROR
Accum
1 .2
F
BBRO
ZP
3 5--
AND
ABS
3 4
ROL
ABS
3 6
AND
ABS,X
3 4-
ROL
ABS,X
37
BBR3
ZP
3 5--
EOR
ABS
3 4
LSR
ABS
3. 6
BBR4
ZP
3 5--
EOR
ABS,X
3 4'
LSR
ABS, X
3 7
BBRS
ZP
3 5--
AOC
ABS
4
ROR
ASS
3 6
3 5"
3
STY
ABS
3 4
STA
ABS
3 4
BBR2
ZP
3
5'-
BBR6
ZP
3
4
6
BBR7
ZP
3 5"
STX
ABS
BBSO
ZP
3 4
3 5-'
STA
ABS, X
3 5
TXS
Implied
1 2
a
BBRI
ZP
3 5--
AOC
ROR
ABS, X ABS, X
43
3 7
TXA
Implied
1 2
3 5
E
ASL
ABS
3 6
ORA
ASL
ABS, X ABS, X
3 43 .7
AOC
ABS,Y
3 4'
STA
ABS,Y
0
ORA
ABS
3 4
C
ASL
Accum
1 2
BBS1
ZP
3 5-'
9
TAY
Implied
1 2
TAX
Implied
12
LOY
ABS
3 4
LOA
ABS
3 4
lOX.
ABS
BBS2
ZP
2 2
3 4
3
CLV
Implied
1 2
lOA
ABS,Y
3 4-
TSX
Implied
1 2
lOY
ABS,X
LOA
ABS,X
3 4-
LOX
ABS,Y
3 4-
BBS3
ZP
3 5--
B
3 4-
5MB4
ZP
2 5
INY
Implied
1 2
eMP
IMM
OEX
Implied
1 2
CPY
ABS
CMP
ABS
DEC
ABS
C
3 4
3 4
36
BBS4
ZP
3 5'-
5MBS
ZP
2 5
CLD
Implied
1 2
CMP
ABS, Y
BBSS
ZP
5--
o
INC
ZP
2 5
5MB6
ZP
INX
Implied
1 2
BBSS
ZP
3 5--
E
INC
ZP, X
2 6
5MB7
ZP
2 5
SED
Implied
1 2
BBS7
ZP
5-'
F
7
8
5
2
5
LOA
IMM
2 2
CMP
DEC
ABS, X ABS, X
3 7
3 4'
3 4SBC
IMM
2 2
NOP
Implied
1 2
CPX
ABS
SBC
ABS
INC
ABS
3 4
3 4
3 6
I
SBC
ABS,Y
sec
INC
ABS, X ABS,)(
3 4'
3 7
3 4-
A
B
C
o
E
A
5--
3
I
3
F
-Add 1 to N if page boundaryjs cros.sed.
-, Add 1 to N if branch occurs to same page;
add 2 to N if branch occurs to different page,
3-172
One-Chip Microcomputers
R6500/11 and R6500112
APPENDIX B
KEY REGISTER SUMMARY
P
7
I
7
I
7
I
,.
I ACCUMULATOR
A
l NI v \ J"\
INDEX REGISTER Y
0\' \ z\ e\
INDEX REGISTER X
,
7
pel
I7
I7
INlvl I. 10 1' IzIC
'CH
SP
,,~
CARRY Ie)
PROGRAM COUNTER
pc
1
o
STACKP.OINl'ER
CD
= Carry Set
= Carry Clear
ZERO (ZIG)
PROCESSOR STATUS REG
P
1 =Zera Result
o = Non·Zero Result
INTEARUPT DISABLE
CPU Registers
(110
1 -:: IRQ Intetrupt Disabled
-0 :: iAQ Interrupt Enabled
aECIMAL MODE (0) (!)
1 -:-; Decimal Mode
0,:::; Binary Mode
BREAK COMMAND (B) (j)
, == Break Command
o
= Non Break Command
OVERFLOW (0)(1)
MeR
1 :;;: OVerflow Set
O=O."erf,ow Clear
Addr 0014
NEGATIVE (N)
NOTES
Counter B
0-
I I
Uocs. Select
Bus Mode Select
1 Nol initialized by Ri'r
(!) Set to Logic 1 by lin;
0 Interval Timer
0-
1 Pulle Generation
1-
0 Event Counler
1_
1 Pulse Wldttl Meas.
1
D
CD
= Negative Value
== Post/ve Value
Pl'OC888Or Stetus Register
0 - 0 Interval ilmer
·0 1 AsymmIKric Pulse Generation
1_
0 Event Counter
1_
1 Relriggerable Inte..... al Timer
PortBLatch
(~ '" Enable)
Pon 0 Tn-State
(0 '" Tri-State High Impedance Mode)
'FR
Addr 0012
'ER
O-XNormal
11_
AddrD011
0 Abbr. Bus
1 Mux"d Bus
PAO Positive
Edge Detect
PAt Positive
Edge De*>
PA2 Neg.live
Edge Detect
PA3 NegeUve
Edge Detecl
Mode Control Register
Counter A
U_rftowFllg
Counter
u_ _B Flog
RCVR
Flog
XMTR
Fllg-
Interrupt Ensble snd Fisg Registers
Add,0015
seCR
O-odd Parity
l_Even Parity
o Parity DI..bIe
o
o
1
1 Parity Enoblo
0 -8 aHI/Cha,
1 _7 alts/Char
0-6 aHI/Char
1
1_5BII8IChar
0 - 0 XMTR & RCVR ASYN _
0 - 1 XM'I'fI ASYN, RCVR SiR
l - X XMTR SIR, RCVR ASYN
W.ke-tJp
End of Tr.nsmll.lon
oRCVR DIablo
1 RCVRenobie
XMTR 0... Reg Empty
OXMTRDloobIe
KIlT" Under-Run
1 XMTR Enable
Serial Cqmmunlcstlons Control Register
Serlsl Communlcstlons Status Register
3-173
II
R6500/11 andR6500/12
One-Chip Microcomputers
APPENDIX C
ADDRESS ASSIGfJMENTS/MEMORV
MAPS/PIN FUNCTIONS
C.1 I/O AND INTERNAL REGISTER ADDRESSES
ADDRESS
REAO
(HEX)
WRITE
--
--
.OO1F
1E
10
1C
Lower Counter B
Upper Counter B
Lower Countflr B, CLR Flag
1B
1A
19
18
Lower Counter A
Upper Counter A
Lower Counter A, CLR Flag
Upper Latch A, Cntr A--Latch A, CLR Flag
Upper Latch A
Lower Latch A
17
16
15
14
Serial R~eiver Data Register
Serial Comm;Status Register
Serial Comm. control Register
Mode Control Register
Serial Transmitter Data Register
Serial Cornrn.. Status RE;lg. Bits 4 & 5 only
SeriaIComr(l. Control Regist!"
Mode .Control RegiSter
13
12
11
0010
OF
.OE
00
OC
OB
OA
09
08
07
06
05
04
03
02
01
0000
Upper Latch B, Cntr B--Latch B, CLR Flag
Upper Latch B, Latch C<-Latch B
Lower Latch B.
--
--
--Clear Int Aag (Bits 0--3 only,
--
Interrupt Enable Register
Interrupt Flag Register
Read FF
Inierrupt Enable Register
----
--
---
----
----
---
--
--
-.-
--
PortG*
Port F*
Port E*
PortG*
Port F*
Portp·
Port D
porte
PortB
PortA
PortO
PortC
PortS
PortA
NOTE: *R6500/12Q Only
3-174
Wr~e
O's only)
R6500t11 and R6500/12
One-Chip Microcomputers
C.2 ABBREVIATED MODE
MEMORY MAP
FFFE
FFFC
FFFA
C.3 MULTIPLEXED MODE
. MEMORY MAP
FFFE
IRQ lIactor
RESVactor
NMI Vector
IRQ Vector
RESVeclor
NMIVeclor
FFFC
FFFA
ROM (3K)
ROM (3K)
F400
F400
,
Reserved
Reserved
00lF
00lF
I
I
""r3FFF
UI!:!
l:.-'
"'~
I
Inlernal Ram (192)
Reserved
0000
1/0 " Registers
T3FFF
lUI!:!
:IE-'
I
I
I
I
I
I
I
I
External Memory
(16384 - 256)
Mux'd Addr Mode
w~
0010
OOOF
I
-L-OOFF
0040
/
Internal
Reglslers
I
Peripheral Devices
(64)
Abb, Addr Mode
00lF
I
I
/
Internal Ram (192)
I
0040
Reserved
I
Reserved
I
1/0 Ports E, F, G
(R6500/12Q Only)
I
001F
0000
Internal
Registers
I
-t-OOFF
Reserved
0007
110 Ports E, F, G 0006
(R6500/12Q Only)
0004
0003
110 Ports A, e, C, 0
0000
I
I
I/O Pons A, 8, C, 0
110 " Reglslers
4
5
B
7
1/0 PORT
FUNCTION
ABBREVIATED PORT
FUNCTION
MULTfPLEXED PORT
FUNCTION
PCO
PC1
PC2
PC3
AO
Al
A2
A3
AO
A1
A2
A3
PC4
PCS
PCB
PC7
A12
A12
9
10
11
RJW
R!W
A13
EMS
A13
EMS
19
18
17
16
POO
P01
P02
P03
00
01
02
03
A4/DO
15
14
13
12
P04
POS
POB
P07
D4
05
06
07
A8/.D4
A9/0S
A101D6
A11/D7
8
3-175
0004
0003
0000
C.4 MULTIPLE FUNCTION PIN ASSIGNMENTS-PORT C AND PORT D
PIN
NUMBER
0010
oooF
0007
0006
A5/D1
A6i02
A7/D3
II
R6500/11 and R6500/12
One-Chip Microcomputers
APPENDIX D
ELECTRICAL SPECIFICATIONS
·NOTE: Stresses above those listed may cause permanent dam·
age to the device. This is a stress rating only and functional oper·
ation of the device at these or any other conditions above those
indicated in other sections of this document is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
MAXIMUM RATINGS·
Parameter
Supply Voltage
Symbol
Value
Unit
vee & VRR
-0.3 to +7.0
Vdc
VIN
-0.3 to +7.0
Vdc
Input Voltage
Operating Temperature
Commercial
Storage Temperature
T
°C
o to +70
TSTG
-55 to +150
°C
DC CHARACTERISTICS
(Vee - 5V ±5%, VSS = 0, TA - 0 to 70°C)
Parameter
Symbol
Min.
Typ.
Max;
Unit
Power Dissipation (Outputs High)
Commerclal@ 25°C
Po
-
1200
mW
RAM Standby Voltage (Retention Mode)
VRR
3.0
-
Vee
Vdc
RAM Standby Current (Retention Mode)
Commercial @ 25°C
IRR
-
4
-
Input High Voltage
VIH
+2.0
Input High Voltage (XTLI and \&2 in Slave Option)
VIH
+4.0
Input Low Voltage
VIL
-0.3
Input Leakage Current (RES, NMI)
= 0 to 5.0 Vdc
liN
Input Low Current PA. PB, PC. PO, PF*, and PG*
(VIL = 0.4 Vdc)
IlL
Output High Voltage (Except XTLO)
(ILOAD = .100 ,.Ad c)
VOH
Output Low Voltage
(I LOAD = 1.6 mAdc)
VOL
Darlington Current Drive, PE'
(Vo
1.5Vdc)
10H
Input Capacitance
(Vin -0, TA = 25°C, f = 1.0 MHz)
PA, PB, PC, PO, PF', and PG'
XTLI,XTLO
Cin
-
mAde
Vee
Vdc
Vcc
Vdc
+0.8
Vdc
±10.0
,.Adc
-1.6
mAdc
-
Vee
Vdc
-
+0.4
Vde
Yin
=
+2.4
-1.0
mAde
-
-
10
50
3.0
6.0
11.5
KO
-
±10
"Adc
10
pF
RL
lOUT
-
COUT
-
3-176
-
-
Output Leakage Current
Tri·State I/Os while in High Impedance State
Note: Negative sign indicates outward current flow, positive indicates inward flow.
-
pF
I/O Port Pull·Up Resistance
PAD-PA7, PBO-PB7, PCD-PC7, PFO-PF7 & PGD-PG7
Output Capacitance
Tri-State I/Os while in High Impedance State
VIN = OV, TA = 25°C, f - 25°C, f = 1.0 MHz
-1.0
*R6500/12Q only.
One-Chip Microcomputers
R6500/11 .and R6500/12
APPENDIX E
TIMING REQUIREMENTS AND CHARACTERISTICS
E.2 CLOCK TIMING
E.1 GENERAL NOTES
SYMBOL
2. A valid Vee - RES sequence is required before proper
operation is achieved.
PARAMETER
MAX
MIN
MAX
10,..s
500
lO,..s
Tcyc
Cycle Time
1000
3. All timing reference levels are O.BV and 2.0V, unless
otherwise specified.
T pWX1
XTLI Input Clock
Pulse Width
XTLO = VSS
± 25
4. All time units are nanoseconds, unless otherwise specified.
TpW02
5. All capacitive loading is 130pf maximum, except as noted
below:
PA,PB
PC (1/0 Modes Only)
PC (ABB and Mux Mode)
PC6, PC7 (Full Address Mode)
SOpf maximum
SOpf maximum
130pf maximum
130pf maximum
Output Clock Pulse
Width at Minimum
Tcyc
T R, TF
Output Clock Rise,
Fall Time
T IR •
Input Clock Rise,
Fall Time
TIF
Tcyc
1.SV
XTLI
(XTLO
=
Vss)
T pw "
•
_ _ T.
3-177
TpW02
2 MHz
1 MHz
MIN
500
TpWX1
-
250
-
± 10
TpWX1
Tpwx,
TpWX1
± 20
± 25
-
25
-
15
-
10
-
10
One-Chip Microcomputers
R6500111 and R6500/12
E.3 ABBREVIATED MODE TIMING-PC AND PO
.
.
-~
1 MCR 8 -·0
- MCR 7 -- 1)
SYMB(lL
PARAMETER
(MCR 5
2 MHz
1 MHz
MIN
MAX
MIN
200
-
-
35
T pcAs
(PC5) R/W Setup Time
T pc. .
(PCO-PC4. PCS) Address Setup TIme
-
~PBSU
(PO) Data Setup Time
50
TpBHR "
(PO) Data Read Hold TIme
1.0
TPBHW
(PO) Data Write Hold Time
30
-
225
-
MAX
140
140
-
10
-
30
130
TpBDO
(PO) Data Output Delay
-
175
-
TPCHA
(PCo-PC4. PCS) Address Hold Time
30
-
30
TPCHR
(PC5) R/W Hold TIme
30
TpCHV
(PC7) EMS Hold Time
10
-
10
-
.T ~CVD(lI
(PC7) Address to EMS Delay Time
30
220
30
130
Tpclip
(PC7) EMS Stabilization Time
30
-
30
-
r----.-
30
NOTE 1: Values assume PCO-PC4. PCS and PC7 have the same capacitive load.
E.3.1 Abbreviated Mode Timing Diagram
WRITE
READr-______________,1
_TPCHR
RIW
1_-'----1
TPCRS
_TPCHV
TPCVD
TPBDD
TPBSU
PDO-PD7
TPBHR
3-178
TPBHW
R650()111 and R6500112
One-Chip Microcomputers
E.4 MULTIPLEXED MODE TIMING":""PC AND PO
(MCR 5
= 1, MCR 6 =
1 MCR 7 = 1)
2 MHz
1 MHz
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
140
T pCRS
(PCS) R/W Setup Time
-
225
TpCAS
(PCo-PC4, PCS) Address Setup Time
-
200
-
T PBAS
(PO) Address Setup Time
-
220
-
120
TpBSU
(PO) Data Setup Time
50
35
-
T pBHR
(PO) Data Read Hold Time
10
-
~O
-
Tp'BHW
(PO) Data Write Hold Time
30
-
30
-
T pSOD
(PO) Data Output Delay
-
175
-
140
T PCHA
(PCO·PC4, PCS) Address Hold Time
30
-
30
-
TpBHA
(PO) Address Hold Time
40
100
40
80
T PCHR
(PCS) R/W Hold Time
30
-
30
-
TpCHV
(PC7) EMS Hold Time
10
-
10
-
Tpcvo w
(PC7) Address to EMS Delay Time
30
200
30
150
Tpcvp
(PC7) EMS Stabilization Time
30
-
30
-
140
NOTE 1: Values assume PDO-PD? and PC? have the same capactive load.
E.4.1 Multiplex Mode Timing Diagram
READ
WRITE
~-----,--""""""\
_TPCHR
R/W
(PCS)
.
TPCRS
_TPCHV
EMS
(PC7)
TPCVP
TPCHA
PCO..,PC4,
PC6
TPCAS
PDOPD7
TPBAS
-
_TPBHA
TPCVD
--
~
TPBHR
TPBHW
One-Chip Microcomputers
R6500/11 and R6500/12
E.S ItO, EDGE DETECT, COUNTERS, AND SERIAL ItO TIMING
2 MHz
1 MHz
PARAMETER
SYMBOL
MIN
MAX
MIN
500
1000
175
-
MAX
Internal Wrtte to Peripheral Data Valid
TpDW (1)
TCMOS/1)
T pDOW
PA, PB, PC, PE, PF, PG, TTL
PA, PB, PC, PE, PF, PG,CMOS
PO
-
-
-
500
1000
150
Peripheral Data Setup Time
Tposu
TPDSU
PA, PB,PC, PF, PG
PO
-
200
50
-
200
50
75
10
-
75
10
Tcyc
-
Tcyc
-
Tcyc
-
Tcyc
-
-
Peripheral Data Hold Time
TpHR
T""A
Tepw
PA, PB, PC, PF, PG
PO
PAO-PA3 Edge Detect Pulse Width
Counters A and B
Tcpw
Teo(1)
PA4, PAS Input Pulse Width
PA4, PAS Output Delay
-
500
-
500
Port B latch Mode
T peLw
TPlSU
TpBL.H
PAD Strobe Pulse Width
PB Data Setup Time
PB Data Hold Time
Tcyc
175
30
-
Tcyc
150
30
-
Serial 1/0
TpOW (l)
TeMes (1)
Tcpw
TpOW(l)
TCMOS(ll
PA6
PA6
P A4
PA4
PA4
XMTR
XMTR
RCVR
XMTR
XMTR
TTL
CMOS
SIR Clock Width
4 Tcyc
Clock-SIR Mode (TTL)
Clock-SIR Mode (CMOS) -
-
500
1000
500
1000
4 Tcyc
-
NOTE 1: Maximum Load CapacItance: 50pF PassIve Pull·Up Required
3·180
500
1000
-
500
1000
R6500/11 and R6500/12
One-Chip Microcomputers
E.S.1 I/O, Edge Detect, Counter, and Serial I/O Timing
,
If-
..
TcyC
~
~
1.SV\
I
PAO-PA7
PBO-PB7
PCO-PC7
PDO-PD7
PFO-PF7
PGO-PG7
TPDSU
'"
I"'"
>t
.1
T~
"
EDGE DETECTS
(PAO-PA3)
K
).
TEPW
CNTR
PA4, PAS
1.SVJ
"\UV
1.SV}
"'"
TCPW
TCD
CNTR
(PA4, PAS)
~
TCPW
2.4V
O.4V
TpDDW
PDO- PD7
X
I
PAO-PA7
PCO-PC7
PBO:"'PB7
PEO-PE1
PFO-PF7
PGO-PG7
TCMOS
' TPDW
VDD-30%
2.4V
I
1
O.4V
PB----~~--~ ~------------------------------------~
(LATCH MODE)
1.SV
1.SV
;',\
PAOSTROBE
I. . . ~-----"T
..- TPLSU . . .
f-,
3-,181
"'~I
PBLW - - - - - - - - - - - -....
_
TpBLH
. R65/11 EB .R65/11 EAB
R6500 Microcomputer System
'1'
R65/11EB AND R65/11EAB
BACKPACK EMULATORS
Rockwell
INTRODUCTION
FEATURES
The.. Rockwell R65/11 EB and R65/11 EAB Backpack Emulator
is the· PROM prototyping version of· the a-bit, masked-ROM
R6500/11 one-chip microcomputer. Like the R6500/11, the
backpack device is totally upward/downward compatible with all
members of the R6500/11 family. It is designed to accept standard 5-volt, 24-pin EPROMs or ROMs directly, in a socket on
top of the Emulator. This packaging concept allows a standard
EPROM to be easily removed, re-programmed, then reinserted
as often as desired.
• PROM version of the R6500/11
• Completely pin compatible with R6500/11 single-chip micro.computers
• Profile approaches 4O-pin DIP of R6500/11
• Accepts 5 volt, 24-pin indusiry-standard EPROMs
-4K memories-2732, 2732A (4K bytes addressable)
• Use as prototyping tool or for low volume production
• 4Kbytes of memory capacity
• 192
a static RAM
• Separate power pin for 32 bytes of RAM
• Software compatibilityw~h the R6S0() family
• 32 bi-directional TTL compatible 110 lines (4 ports)
• Two 16 b~ programmable counter/iatches with six modes
(interval timer, pulse generator; event counter, pulse width
measurement~ asymmetrical pulse generator, and retrigger.
able interval timer)
• .10 interrupts (reset, non-maskable, four external edge sensitive, 2 counters, serial data received, serial data transmitted) ..
• Crystal or external time base
• Single +5V power supply
x
The backpack deVices have the same pinouts as the maskedROM R6500/11 microcomputer. These 40 pins arefunctianally
and operationally identical to the pins on the R6500/t1. The
R6500/11 Microcomputer Product Description (Rockwell Documen.! No. 29651 N23,Order No. 2119) includes a description of
the interface signals and their functions. Whereas the maskedROM R6500/11 proVides 3K bytes of read-only memory, the
R65/11EB will address4K bytes of external program memory.
This extra memory accommodates program patChes, test programs or optional programs during breadboard and prototype
.
development states.
ORDERING INFORMATION
Backpack Emulator
Part
Number
Memory
Capacity
Compatible
Memories
Temperature
Range and Speed
R65/11EB
4K x
a
2732
O°C to 700C
1MHz
R65/11EAB
4K x
a
2732A
O°Cto 70°C
2 MHz
Support Products
Part
Number
S65-101
Description
SYSTEM 65 Microcomputer
Development System
PROM Programmer Module
M65-040
M65-131
1-MHz R6500111 Personality Module
M65-132
2-MHz R6500/11 Personality Module
RDC-1001
ROC-101
ROckwell Design Center
1 MHz R6500/11 P Personality Module (ROC)
ROC-102
2 MHz R6500111 AP Personality Module (ROC)
Document No. 29001013
R65/11EB Backpack Emulator
3-182
Data Sheet Order No. 0113
February 1983
Backpack Emulators
R65/11EB. R65/11EAB
CONFIGURATIONS
PRODUCT SUPPORT
The Backpack Emulator is available in two different versions,
to accommodate 1 MHz and 2 MHz speeds. Both versions
provide 192 bytes of RAM and VO, as well as 24 signals to
support the external memory "backpack" socket.
The Backpack Emulator is just one of the products that Rockwell offers to facilitate system and program development
for the R6500/11.
The SYSTEM 65 Microcomputer Development 'System with
R6500/11 Personality Module supports both hardware and
software development. Complete in-circuit user emulation
with the R6500/11 Personality Module allows total system
test and evaluation. With the optional PROM Programmer,
SYSTEM 65 can also be used to program EPROMs for the
development activity. When PROM programs have been finalized, the PROM device can be sent to Rockwell for masking
into the 3K ROM of the R6500/11,
The emulator will relocate the EPROM address space to
FXXX (see Memory Map). EPROM addresses FFA through
FFF must contain the interrupt vectors.
EXTERNAL FREQUENCY REFERENCE
The external frequency reference may be a crystal or a
clock-the RC option of the R6500/11 is not available in the
emulator device. The R65/11 EB and R65/11 EAB divide the
input clock by two regardless of the source.
In addition to support products, Rockwell offers regularlyscheduled designer courses at regional centers.
I/O PORT PULLUPS
The devices have internal VO port pullup resistors on ports
A, B, & C. Port D has push-pull drivers.
XTLI
XTLO
vce,VRR, VSS
[::J
L-_64_R_AX_M_8_~1 I
vee,vss
PORTe
I
00-07
1--.;;...8·---1'.....
PROM/
ROM
CONTROL
REGISTER
40 R8500/11
eOMP.t.TIBLE PINS
24 PROM/ROM
PINS
R65/11 EB Interface Diagram
3-183
II
Backpack Emulators
R65/11EB. R65/11EAB
XTLO
XTLI
BACKPACK MEMORY SIGNAL
DESCRIPTION
Vss
_2
V RR
PCl
PC2
PC3
PBO
PBl
PB2
PB3
PB4
PC4
PBS
PC5
PB6
PCO
Signal
Name
Data Bus Lines. All instruction and data
transfers take place on the data bus lines.
The buffers driving the data bus lines have
full three-state capability. Each data bus
pin is connected-to an input and an output
buffer, w~h the output buffer remaining in
the floallng condilion.
.PA3
PA4
PAS
AO-A7
A8,A9
Al0
All
lS-8S,
23S,24S
19S
21S
Address Bus Unes. The address bus lines
are bulfered by pustVpull type drivers that
can drive one standard TTL load.
PA6
CE
18S
Chip Enable. CE is active when the address
is 8000-FFFF. This line can drive one TTL
load.
OE
20S
Memory Enable Line. This signal provides
the oulput enable for the memory 10 place
information on the data bus lines. This
signal is driven by an inverted
signal
from the CPU. II can drive 1 TTL load.
PB7
PC7
PD7
PAO
PAl
PA2
PD3
PD2
pA7
PDl
Description
9S-11S,
135-17S
PC6
PDe
PD5
PD4
Pin No.
00-07
PD~
NMI
RES
Vee
Pin Configuration
RiW
Vee
24S
Main Power Supply +5V. This pin is tied
diiectly to pin 21 (Vcel.
Vss
12S
Signal and Power Ground (zero voRs). This
pin is lied directly to pin 40 (V ssl.
I/O AND INTERNAL REGISTER ADDRESSES
Address
(Hex)
IE
10
lC
Lower Counter B
Upper Counler B
Lower Counter B, CLR Flag
lB
lA
19
18
Lower Counler A
Upper Counter A
Lower Counter A, CLR Flag
17
16
15
14
13
12
11
0010
-Upper Latch B, Cntr B<--Latch B, CLR Flag
Upper Latch B, Latch C<--Latch B
Lower Latch B
--
-Serial
Serial
Serial
Mode
Upper Latch A, Cntr A-Latch A, CLR Flag
Upper Latch A
Lower Latch A
Receiver Data Register
Comm. Status Register
Comm. Control Register
Control Register
. Serial
Serial
Serial
Mode
Transmitter Data Register
Comm. Status Reg. Bits 4 & 5 only
Comm. Control Register
Control Register
---
--
Interrupt Enable. Register
Interrupl Enable Register
Interrupl Flag Register
Read FF
Clear Inl Flag (Bits 0-3 only, Write O's only)
--
04 thru OF
03
02
01
0000
Write
Read
--
001F
--
Port 0
PortC
PortB
PortA
Port 0
PortC
Port B
PortA
3-184
Backpack Emulators
R65/11 EB. R65/t1 EAB
READ TIMING CHARACTERISTICS
1 MHz
SIgIIIII
OE
and
CE
Symbol
CPU
CPU
setup time from
Address setup time from
TAOS
TACC
Data set up time
Tosu
50
Data hold time-Read
THR
10
Address hold time
THA
30
T HOE
30
1.0
and
CE
hold time
Cycle Time
Max.
-
TOES
Memory read access time
OE
2 MHz
Min.
Tcyc
Min.
-
225
225
700
-
35
10
30
30
0.5
10.0
Max.
Unit
140
ns
140
ns
315
ns
-
ns
ns
ns
ns
10.0
p,S
r-------------------------------------------------------------------------,
READ TIMING WAVEFORMS
ADDRESS FROM
CPU
DATAFROM--~----4_----4_--~
MEMORY
~~--~,
ABBREVIATED MODE
MEMORY MAP
FFFC
IRQ VECTOR
RES VECTOR
FFFA
NMI VECTOR
"FE
MULTIPLEXED MODE
MEMORY MAP
FOOO
IRQ VECTOR
RES VECTOR
NMIVECTOR
....
ROM (3K)
'4GO
FFFE
'FFC
FF.A
EXTENDED ROM (1 K)'
FOOO
_(OK)
ExteNDED ROM (1K)'
001.
T
3FF'
L
l
,,/
PERIPHERAL DEVICES
(84)
ABBR ADOR MODE
s!!
wi\!
/
OOFF
RESERVED
001F
0000
110 & REGISTERS
/
l
.'
.'
//
INTERNAL RAM (192)
0040
001'
/
RESERVED
•l
-
RESERVED
INTERNAL
REGISTERS
0010
GOOF
RESERVED
110 PORTS E, F, G
(A8iOIII12Q ONLV)
INTERNAL
REGISTERS
T3FFF
0007
EXl'ERI!AoL MEMORY
(111384-258)
MUX'D ADDR MODE
s!!
wi\!
....t...
0006
OOCM
IlTERNAL RAM (192)
001.
0000
0000
'NOT AVAILABLE FDA MASKED ROM _ , .
3-185
I/O PORTS E. F, C
(RI5OOI12QONLV)
0040
000'
110 PORTS A, B, C, D
0010
RESERVEO
GOFF
RESERVED
UO • REGISTERS
•
-
000'
0007
0006
110 PORTS A, B, C, D
0000
II
R65/11EB. R65/11EAB
Backpack Emulators
ELECTRICAL CHARACTERISTICS
(Vee
=
5.0 ± 5%, Vss
= O,T A = 25'C)
Characteristic
Input High Threshold
00-07
SymbOl
Vo~age
Vss
Input Low Threshold Voltage
00-07
V ILT
Three-State (Off State) Input Current
(V = 0.4 to 2.4V, Vee = 5.25V)
00-07
I TSI
Output High Vo~age
(I LOAO = 100p. Ade, Vee
DO-07, AP-A11 , OE, CE
V OH
Output Low Vo~age
(I LOAD = 1.6 mAde, Vee
00-07, AO-A1l, OE, CE
= 4.75V)
Typ
Min
V 1HT
Max
-
+ 2.0
-
-
-
Vss
Unit
Vdc
+
0.8
Vdc
p.A
Vss
+
-
-
2.4
10
:!:
-
Vdc
VOL
= 4.75V)
-
-
-
0.80
Power Dissipation (less EPROM)
Po
Capacitance
(V in = 0, TA = 25°C, f = 1 MHz)
00-07 (High Impedance State)
Input Capacitance
C
Cin
-
VO Port Pull-up Resistance
RL
3.0
Vss
+
0.4
1.20
Vdc
W
pF
Cout
-
10
10
6.0
11.5
21
I
II
!
20
1---------2.020MAXI--------_1
. 1-
O.OSO!:.02
~
I
RIW
PAO
PAl
PA'
PA'
PA'
PA'
~
~
~
~
~
-~-+ I
-~---
.050 FIEF
(1.27MM)
TVP
. 1- =l "I
.92'
"
I
(23.495MM)
(19;:~MI
TIT~'
(5.08 MM)
-±..-
I
Ii.
I
I
Ii.
I
1 .. 1
~11
I
~
I
I
~
I
64 PIN QUIP
Figure 2-1. Mechanical Outline & Pin Out Configuration
3-188
~
__ t
.020REFJ
TVP
R6511 Q Microprocessor and· R6500/13 Microcomputer
SECTION '2
R6511 Q AND R65001131NTERFACE RE·QUIREMENTS
Table 2-1. A6500/13 Pin Descriptions
Pin No.
~ptlon
This section describes the interface requirements for the
R6511Q and R6500/13. Figure a-1 and 2-2 show the Interface Diagram and the pin out configuration for both devices.
Table 2-1-describes the function of each pin.,Figure 3-1 h./ls
a detailed block diagram of the R6500/13 ports which illus..
trates the internal function of the device.
Signal Name
21
43
V..
44
XTLI
42
XTLO
41
RES
6
XTLO
XTU
PAo.PA7 (PAD, PA1,
PA2, PA3:
EDGE DETECTS:)
45
Pao.PI? (LATCHED INPUTS)
os (PAD)
(DATA STROBE)"
23
PCO-PC7J(A13,.A14
(Fulraddre.. mode)'
PDo-P071
(DATAIADOR BUS (M-Alt))
SYNC
PAO-PA7
PBO-PB7
PCO-PC7
POO;PD7
CA(P")'
CI(PAS)"
39-32
31·24
54-61
62-64,
1,5
~~~;)~
·MULTlPL~XEO FU~TIONS PINS (Softw.... Satectable)
Figure 2-2. Interface Diagram
AOoA12, A15
20·7
DBO-DB7
53-46
SYNC
22
40
3-189
Mainpowe.. supply +5V
Separate· power pin for RAM.
In the event that Vee power
is off, this power retains RAM .
d.ata;
Signal and power ground (oii)
Crystal or clock input for in·
ternal clock oscillator. AI
allows input of X1 clock sig·
nal WXTLO is connectedt
Vss, or X2 or X4 clock if XTLO
is floated.
Crystal output from internal
clockosqillator.
The Reset input is used to .'
initialiZE! the device. This signal must nOitransition from
low to high for at least eight
cycles after Vee re~es o~
erating range and the inter·
nal oscillator has stabilized.
Clock signal output at internal frequency:
.A negative going edge on the
Non·Maskable Int\lrrupt signal requests. that a nonmaskable interrupt. be generated with the CPU.
Four a·bit ports used for
either input/output. Each line
of Ports A, B and C consists
of an active transistor to V
and an optional passive puRup to Vee. In the abbreviated
or multiplexed modes of operation Port C has an actiye
pull·up transistor. Port D
funqljons as either. an a·bit
input or a·bit output port. It
has active pull·up and pulldown transistors.
FOUrteen address iines used
to address a complete
65K external address space.
Note: A13 & A14 are SourCed
through PC6 & PC7 when in
the Full Address Mode.
Eight' bidirilctiorilll data bus
Hnes used to transmit data to
and irom extemalmemory.
SYNC is a positive going signal for the full cloCk cycle
whenever the CPU is performing an OP CODe fetch.
Controls the direction of. data
transfer between the CPU
and the extemal 65K address SP"Ctl. The signal is
high when reading lind low
when writing.
s.
II
R6511Q Microprocessor and R6500/13 Microcomputer
SECTION 3
SYSTEM ARCHITECTURE
This secti!)n' provides a fun~ional description of the R6500/
13. Functionally the R6500/13 consists of a CPU, both RAM
and, optional ROM memories, four 8-bit parallel I/O ports,. a
serial 1/0 port, dual counter/latch circuits, a mode control register, and a.n interrupt flag/Emable dual register circuit. A block
diagram ~f,the system i~ shown in Figure 3-1.
location is stored (or "pushed") onto the stack. Each time
data are to be pushed onto the stack, the Stack Pointer is
placed on the'Address Bus, data are written irito the memory
locaiion addressed by the Stack Pointer, and' the Stack
Pointer is decremented by 1. Each time data are read (or
"pulled") from the stack, the Stack Pointer is incremented by
1. The Stack Pointer is then placed on the Address Bus and
data are read from the memory location addressed by the
Pointer.
NOTE
Throughout this document, unless specified otherwise,
all memory or register address localions are specified
in hexadecimal notation.
The stack is located on zero page, I.e" memory locations
00FF-0040, After reset, which leaves the Stack Pointer
indeterminate, normal usage calls for its initialization at OOFF,
3.1 CPU LQ(lIC
3.1.4 Arithmetic And Logic Unit (ALU)
The R6500/13 internal CPU is a standard 6502 configuration
with ari 8-bit Accumulator register, two 8-bit Index Registers
(X and V); an8-bit Stack Pointer register, an ALU, a 16-bit
Progratn COunter, and standard instruction register/decode
and internal timing control logic.
All arithmetic and logic operations take place in the AlU,
including incrementing and decrementing internal registers
(except the Program Counter), The ALU cannot store data
for more than one cycle, If data are placed on the inputs to
the ALU at the beginning of a cycle, the result is always gated
into one of the storage registers or to external memory during
the next cycle.
3.1.1 Accumulator
The accumulator is a general purpose 8-bit register that
stores the results almost arithmetic and logic operations, In
addition, the accumulator usually contains one of the two
data words used in these'operations,
Each bit of the ALU has'two inputs, These inputs can be tied
to various internal buses or to a logic zero; the ALU then
generates the function (AND, OR, SUM, and so on) using
the data on the two inputs,
3.1.2 Index Registers
3.1.5 Program Counter
There are two a-bit index registers. X and y, Each index register can be used as a base to modify the address data program counter and thus obtain a new address-the sum of
the program counter contents and the index register contents,
The 16-bit Program Counter provides the addresses that are
used to step' the processor through sequential instructions
in a program, Each time the processor fetches an instruction
from program memory, the lower (least significant) byte of
the Program Counter (PCl) is placed on the low-order bits
of the Address Bus and the higher (most significant) byte of
the Program Counter (PCH) is placed on the high-order a
bits of the Address Bus, The Counter. is incremented each
time an instruction or data is fetched from program memory,
When executing an instruction which specifies indirect
addressing, the CPU fetches the op code and the address
and modifies the address from memory by adding the index
register to it prior to loading or storing the value of memory,
Indexing greatly simplifies many types of programs, especially those using data 'tables,
3.1.6 Instruction Register and Instruction Decode
Instructions are fetched from ROM or RAM and gated onto
the Internal Data Bus. These instructions are latched into the
Instruction Register, then decoded along with timing and
interrupt signals to generate control signals for the various
registers.
3.1.3 Stack Pointer
The Stack Pointer is an 8-bit register. It is automatically
incremented and decremented under control of the micro·
processor to perform stack manipulation in response to either
user instructions, an internal IRQ interrupt, or the external
interrupt line NI)IIL The Stack Pointer must be initialized by
the, user program,
3.1.7 Timing Control
The Timing Control Logic keeps track of the specific instruction cycle being executed, This logic is set to TO each time
an instruction fetch is executed and is ,advanced at the
beginning of each Phase One clock pulse for as many cycles
as are required to complete the instruction, Each data transfer
which takes place between the registers is caused by
decoding the contents of both the instruction register and
timing control unit.
The stack allows simple implementation of multiple level
interrupts, subroutine nesting and simplification of many types
of data manipulation. The JSR, BRK, RTI and RTS instruc·
tions use the stack and Stack Pointer.
The stack can be envisioned as a deck of cards which may
be accessed only from the top. The address of a memory
3-190
:::u
CJ)
........en
"s::
C:i"
a
'0
a
(')
CD
(I)
...~
I»
::l
Q.
:::u
~
o
~
w
s::
~
(;'
~
a
(')
o
3
-
'0
c
.!!!
AI)..A12.AI5
~
0G-01
~
ij
""'-""
PSO-:PB7
t
C8[PA5)
Figure 3-1.
t
c.."p,u)
l
so (Pol&)
t
$lIPAn'
Detailed Block Diagram
II
NMi
R6511Q Microprocessor and R6500/13 Microcomputer
3.1.8 Interrupt Logic
3.3 READ-ONL Y-MEMORY (ROM)
Interrupt logic controls the sequencing of three interrupts;
RES, NMI and IRQ. IRQ is generated by anyone of eight
conditions: 2 Counter Overt.lows, 2 Positive Edge Detects,
2 Negative Edge Detects, and 2 Serial Port Conditions.
The optional ROM consists of 256 bytes mask programmable
memory with an .address space from 7FOO to 7FFF. ROM
locations FFFA to FFFF are assigned for interrupt vectors.
The reset vector can be optionally at 7FFE or FFFC.
The R6511 Q has no ROM and its Reset vector is at FFFC.
3.2 NEW INSTRUCTIONS
3.4 RANDOM ACCESS MEMORY (RAM)
In addition to the standard R6502 instruction set, four new
bit manipulation instructions have been added to the R6500/
13. The added instructions and their format are explained in
the following paragraphs. Refer to Appendix A for the Op
Code mnemonic addressing matrix fOr these add.ed instructions. The four·added instructions do not impact the CPU
processor status register.
The RAM consists of 192 bytes of read/write memory with
an aSSigned page zero address of 0040 through OOFF. The
R6500/13 provides a separate power pin (V RR ) which may be
used for standby power for 32 bytes located at 0040-005F.
In the event of the loss of Vee power, the lowest 32 bytes of
RAM data will be retained if standby power is supplied to the
V RR pin. If the RAM data retention is not required then VRR
must be connected to Vee. During operation VRR must be at
the Vee level.
3.2.1 set Memory Bit (SMB m,Addr.)
This instruction sets to "1" one of the 8-bit data field specified
by the zero page address (memory or I/O port). The first byte
of the instruction specifies the 5MB operation and one of eight
bits to be set. The second byte of the instruction deSignates
.
address (0-255) of the byte to be operated upon.
For the .RAM to retain data upon loss of Vee, VRR must be
supplied within operating range and RES must be driven low
at least eight 1'l2 clock pulses before Vec falls out of operating
range. RES must.then beheld low while Vee is out of operating range and until"at least eight 1'l2 clock cycles after Vee
is again wi~hin operating range and the internal 1'l2 oscillator
is stabilized. VRR must remain within Vee operating range
during normal operation. When Vee is out of operating range,
VRR must remain within the VRR retention range in order to
retain data. Figure 3.2 shows typical waveforms.
3.2.2 Reset Memory Bit (RMB m, Addr.)
This instruction is the same operation and. format as 5MB
instruction except a reset to "0" of the bit results.
3.2.3 Branch On Bit Set Relative (BBS m, Addr,
DESn
RAM OPERATING MODE
This instruction tests one of eight bits deSignated by a 3-bit
immediate field within the first byte of the instruction. The
second byte is used to deSignate the address of the byte to
be tested within the zero page address range (memory or
I/O ports). The third byte of the instruction is used to specify
the 8-bit relative address to which the instruction branches
if the bit tested is a "1". If the bit tested is not set, the next
sequential instruction is executed.
I
RAM RETENTION MODE
I
I
::!1@' .: .t~-':~
I----®
~@
~
~ I-TRL
1 INITIAL APPLICATION OF Ycc AND VRR •
@
2 LOSS. OF Yee • RAM ON STANDBY POWER.
3 REAPPLICATION OF Yee.
4 >8 112 CLOCK PULSES AFTER OSCILLATOR STABILIZATION.
5 >8 112 CLOCK PULSES.
3.2.4 Branch On Bit Reset Relative (BBR m,
Addr,DESn
This instruction is the same operation and format as the BBS
instruction except that a branch takes place if the bit tested
is a "0".
Figure 3-2.
3-192
Data Retention Timing
Fl6511 Q, Microproc~:ssor andR65()()/13 Microcomputer
3.5 C~OCK iOSCILLA'rOR
is tied to V•• , the internaLcountdown network is bypassed
causing the chip to operate at the frequency of the external
source.
The R6511Q h~s been configured for a ayStalosCillator, a
divide by 2 countdown network, and for Master' Mode
Operation.
Three customer 'selectable mask options are available ,for'
controlling the R6500(13 timing. The R6500/13 can be ordered
with a crystal or RC, oscillator, a divide by 2 or divide by 4
countdown mitwor\{ and for clock master mode or clOck
, slave mode operation."
'
For 2MHz interval operation the divide-by-2 options must be
,
specified.
'
Theorxntlon,escribed above assumed a CLOCK MASTER
MODE mask option. In this mode a frequence source (crystal,'
RC network, or external source) must be applied tathe XTLI
and XTLO pins.
Note:
When operating at a 1 MHz internal frequency place a
15-22 pt capacitor between XTLO, ,and GiliD.
~ is a buffered output signal.Whichclosety approximates the
internal timing. When a common external source ill used to
drive, multiple devices the intemalliming between devices ~
well as their
outputs wm be skeWed in time. If skewing represents a system problem it can be avoided by the
Master/Slave connection and options shown in Figure 3-4.
A reference frequency can be generated with the on-chip
oscillator using either an external crystal or an external resistor
depending on the mask option selected. The oscillator reference fi'equency passes through an internal countdown network (divide by 2 or divide by 4 option) to obtain the internal
operating frequency (see Figures 3'-38 and 3-3b). The external
crystal generated reference frequency is a preferred method
since theresis/or method can have tolerances approaching
_2
One R6500/13 is operated in the CLOCK MASTER MODE
and a second in the CLOCK SLAVE MODE. Mask options
in the SLAVE unit convert to ;2 signal Into a clock input pin
which is tightly coupled to th~ internal timing generator. As
a result the fnternaltiming of the MASTER and SLAVE units
are synchronized with minimum skew. Ifthe"p2 signal to the
SLAVE unit is inverted, the MASTER and SLAVE UNITS
WilL OPERATE OUT OF PHASE. This approach alloWs the
two devices to share eldamal memory using pycle stealing
techniques.
.
,
50%.
Internal timing can also be controlled by driving the XTLI pin
with an external frequency source. Figure 3-Sc shows typical
connections. If XTlO is left floating, the externalsol,Jrce is
divided by the intern~1 countdown network.' However, if XTlO
R
~
~~/13
2.4K
~O
'INT'"
1 MHz
(USE.;. 4)
'EXT
=4
R6SOO/13
MHz
XTLI
A. RESISTOR INPUT
MASTER
. . -' :' l;'""" . . ·., ...
XTlO
B.
'EXT
=
'2 (OUTPUT CLOCk)
XTlO
2X or 4X 'INT
6500/13
CRYSTAL INPUT
Vee
XTLI
30011
r-- --~ INVERTER OSED
I
I WHEN SI,AVE IS.
:
: TO OPERA1"E
L__ ---' OUT OF PHASE
WITH MASTER
SLAVE
(INPUT CLOCK)
2-4 MHz
XTll
R6500/13 'INT
NC
XTlO
'EXT
=
XTLO
:;;2 MHz
= 2X or 4X 'INT
Figure 3-4. Mester/slave ConnectIons
300 II
1-2 MHz
'Xl-4~XTll
R6500/13
XTlO
'INT
= 1 or 2 MHz
'EXT
= 'INT
Vss ~
C.ClOCKINPUTS
Figure 3-3. Clock Oscillator Input Options
3-193
R6511Q Microprocessor and R6500/13 Microcomputer
"
,
3.7 INTERRUPT FLAGREGISTER'(IFR)
AND INTERRUPT ENABLE
REGISTER (IER) ,
3.6 MODE ,CONTROL REGISJER (MCR)
The Mode Control Register contains control bits for the mul- '
tifunction 1/0 ports and mode select bits for Counter A and
Counter B. Its setting, along with the setting of the Serial
Communioations Control Register (SCCR), determines the
basic ccnfiguration of the R6500/13 in any application, Ini~'
tializing this register is one of the first actions of any software
program. The Mode Control Register bit assignment is shown
in Figure 3-5.
MCR
An IRQ interrupt request can be initiated by any o(all of eight
possible sources. These sources are all Capable of being
enabled or disabled by the use ()f the appropriate interrupt
enabled bits in, the Interrupt Enable Register (It;:R). MultiplEi
simultaneous interrupts causethe IRQ interrupt request to
remain active until all interrupting conditions have been
serviced and cleared.
The Interrupt Flag Register contains the information that
indicates which I/O or ccunter needs attention. The contents
of the ,Interrupt Flag ,Register maybe examined at any time
by reading at addre$s: 001,1, Edge detect ,IFR bits may be
cleared by execl!ting a RMB instrlJction at address location
0010. The RMB X, (0010) instruction read$ FF, modifies bit
X to a "0", .and writes the modified value at address location
0011 .. In this way IFR bits. set to a "1" after the r.ead cycle of
a Read-Modify-Write instruction (such as RMB) are protected
from being cleared. A logic "1" is ignored when writing to
edge detect IFR bits,
Add,0014
I, I
Count., B
.Mode JI.I~~
0-,-
0 Interval Timer
_
0 - 1 puree Generation
1-'' - ' 0 Event COI,Int,r
,,1-,_1 Pulse Width M,I,.
0 - 0 Intarval Time,
o- 1 Asymmetr1c Puis. Generation
"t, --i- a,Event Counter
.
Bus MOlle ,$eloct
1_
1 Retrlggerabla Int_rvell Timer
Port B Latch
(1
=Enabled)
Port D 1<1-S\8I. _
(0= Tr'~ ~t~'t. High Impedance Mode)
0 - 0 Full
Each IFR bit has a corresponding bit. in the Interrupt Enable
Regi$ter which can be set to a"1" by writing a "1" .in the
respective bit position at location 0012. Individual IER bits
may be cleared by writing a "ri in the respective bit pOSition,
or. by RES. If set to a "1", an IRQ will be generated when the
corresponding IFR bit becomes true. The'lnterrupt Flag Register and Interrupt Enable Register pit assignments are shown
in Figure 3·6 and the functions of each bit are explained in
Table 3·1,
Adi:f~e~s
O~'Normal
'-'-0 Abbr. Sus
1 - 1 Mux'd. Sus
Figure 3-5. Motle COntrol Register
The use of Counter A Mode Select is shown in Section 6.1,
The use of Counter B Mode Select is shoWn in Section 6.2.
The use of Port B Latc,ht;:nable is shown in Section 4,4,
The use of Port D in Tri-State Enable is shown in Section
4.6.
The
u~:of
Bus Mode Select is shown in Section 4.5 and 4.6.
3-194
R6511Q Microprocessor and.R6500l13 Microcompute,·
AcId. 0012
IER
IFA
AcId•. 001.1
~~~~~~~~~~~~~
PAOP.ItIW·
lEdge Detect
PA1 Po.I!l".
Edge
o.t.Ct
PAZ Negllll".
Edge Detect
PM NegIIIIve
.
lEdge Detect
, CoIIIlllrA
CoII _·"U_owFl
_
..
U~ .....
. R_lver
XMTR
Fl811
Flog
Figure 3·6. Interrupt Enable and Flag Registers
Table 3-1. Interrupt Flag Register Bit Cod..
Bh
Code
,Function
IFRO:
PAD Positive Edge Detect Flag-Set to a "1" when a positive going edge is detected on PAO.
Cleared by RMB 0 (0010) instruction or by RES.
IFR 1:
.PA1 Positive Edge Detect f=lag-Set to Ii 1 when a positive gOing edge is detected on lOA1.
Cleared by RMB 1 (0010) Instruction or byRES.
f
IFR2:
PA2 Negative Edge Detect Flag-Set to a 1 wilen a negative going edge is detected on PA2.
Cleared by RMB 2 (0010). instruction Or by RES.
IFR3:
PA3 Negative
08tect Flag-Set tolwhen a negative going edge is detected on PA3.
Cleared by RMB 3 (0010) instruction or by RES.
IFR4:
Counter A Underflow' Flag-Set to al when Counter A undeinow ~urs. ClelVed by reading
the Lower Counter A et location 0018. by writing'to address location 001A. or by RES.
IFR5:
Counter B Underf!owFlag-Setto a 1 when .Counter B underflow ~urs. Cleared~reading
the Lower Counter B at location 001 C. by writing to address location 001 E. or by RES.
lFR6:
ReCeiver'lnterruPtFJag-Set to a 1 when any the Serial Communication Status Register bits
othrough 3 is set to a 1. Cleared when the Receiver Status bits (SCSR 0-3) are c;leared or by
RES .
IFR 7:
.'transmitter Interrupt Flag-Set to 8 1 whefl SCSR 6 is set toa 1 while SCSR 5 is a 0 or SCSR
7 is set to a 1. Cleared when the Transmittar Status bits (SCSR 6 & 7) are cleared or by RES.
edge
of
3-195
R6511 QMicroprocessor and R6500/13 Microcomputer'
zero. This bit is cleared to logic 0 when the resultant 8 bits
of a data movement orcalculation operation are not all zero.
The R6S00 instruction set contains no instruction to specifically set or clear the Zero Bit. The Zero Bit is, however,
'affected by the following instructions; ADC, AND, ASL, BIT,
CMP •. CPX, CPY, DE;C, DEX, DEY, EOR, INC, INX, INY,
LOA, LOX, LOY, LSR, ORA, PLA, PLP, ROL, ROR, RTI,
SBC, TAX, TAY, TXA, TSX, and TYA.
3.8 PROCESSOR STATUS REGISTER
The B-bit Processor Status Register, shown in Figure 3-7,
contains seven status flags. Some of these ilags are
controlled by the user program; others may be controlled both
by the user's program and the CPU. The R6502 instruction set
contains a number of conditional branch instructions which are
designed to allow testing of these flags. Each Of the eight processor status flags is described in the following sections. . .
3.8.3
Interr~pt
Disable Bit (I)
The Carry Bit (C) can be considered as the ninth bit of an
arithmetic operation. It is set to logic 1 if a carry from the
eighth bit has occurred or cleared to logic 0 if no carry
. occurred as the result of arithmetic operations.
The Interrupt Disable Bit (I) is used to control the servicing
of an interrupt request (IRQ). If the I Bit is reset to logic 0,
the .IRQ signal will be serviced. If the bit is setto logic 1, the
IRQ signal will be ignored. The CPU will sei tlie Interrupt
Disable· Bit to logic 1 if a RESET (RES), IRQ, or Non·Mask·
.
able Interrupt (NMI) signal is detected.
The Carry Bit may be set or cleared under program control
by use of the Set Carry (SEC) or Clear Carry (CLC) instruc·
tion, respectively. Other operations which affect the Carry Bit
ate ADe, ASL, CMP, CPX, CPY, LSR, PLP ,ROL, ROR, RTI,
and SBC.
.
The I bit is cleared by the Clear Interrupt Mask Instruction
(CLI) and is set by the Set Interrupt Mask Instruction (SEI).
This bit is set by the BRK Instruction. The Return from Interrupt (RTI) and Pull Processor Status (PLP) instructions will
also affect tile I bit.
3.8.1 Carry Bit(C)
i
3.8.2 Zero Bit (Z)
The Zero Bit (Z) is set to logic 1 by the .cPU during any data
movement or calculation which sets al.1 8 bils of the result to
CARRY (CIQ)
1
= Carry Set
= Carry Clear
L-_ _ _ ZERO(ZIQ)
o
1 =-Zero Result
o :: Non-Zero Res.un
1-_-;-_ _ _ INTERRUPT I)ISABLE (110
1
o
L-_~_ _ _ _ _
= IRQ InterruPt Disabled
=I~Q Interrupt Enabled
OECIMAL MODE (DIQ)
1
o
=Declmal'Mode
= Bina.ry MOcte
L-_ _ _ _ _ _ _ _ _ BRE.AK COMMAND (BIQ)
1 _ Break Command
o
-=
1 = 'Overflow Set
=
o Overflow Clear
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ NEGATIVE(NIQ) .
o
"NOTES
=
1
Negative Value
0= Postive Va1ue
Not initialized by RES
® Set to Logic 1 by RES
Figure 3-7.
Processor Status Register
3-196
"
Non Break Command
L-_ _-,-_ _ _ _ _ _ _ _ _ _ OVERFLOW(01Q)
R6511Q MicroprocessorandR6500/13 Microcomputer
Tl:lis indicator only has meaning when signed arithmetic (sign
and seven magnitude bits) is performed. When the ADC or
SBC instructionisperformed,~he Overflow Bit is set to logic
1 ,if the polarity of the sign bit (bit 1) is changed because the
result exceedS +127 or -128; otherwise the bit is cleared
to k;gic O. The V bit may also be cleared by the programmer
using a Clear Overflow (CLV) instruction.
3.8.4 Decimal Mode Bit (D)
The Decimal Mode Bit (0) is used to control the arithmetic '
mode of the CPU. When this bit is sel logic 1, the adder
operates as a decimal adder. When this bit is ,cleared to logic
0, the adder operates as a straight binary adder. The adder
mode is controlled only by the programmer. The Set Decimal
Mode (SISD) instruction will set the 0 bit; the Clear Decimal
Mode (CLD) instruction olears it. The PLP and RTI instructions also affect the Decimal Mode Bit.
to
The Overflow Bit may also be used with the BIT instruction.
The BIT instruction-which may be used to sampie interface
devices--:allOws the overflow flag to'refl9qt the condition'of
bit Sin the sampled field. During a BIT instruction, the OVerflOw Bit is set equal to the content of tne bit 6 on the data
tested with BIT' instruction. when used in this mode, the
overflOw has nothing to do, with signed arithmet~, but is just
anO,her sense bit for the microprocessor. Instructions affecting
the V flag are ADC, BIT, CLV, PLP, RTI and SBC.
CAUTION
The Decimal Mode"Bit will ,either set orcl9iir ,in an
unpredictable maimer upon power,application. This bit
\T.\\:Jst be initialized to the, desired state by the user
gram or erroneous results may occur.
pro-
3.8.7 Negative Bit (N)
3.8.!i.Break Bit (8)
The, Neg,aiive Bit (N) is us~d to indicate that the sign bit (bit
7) in ihe resulting value of a data movement or data arithmetiC operation is set to logic 1. If the sign bit is set to logic
1, the resulting value of the daia movement or arithmetic
operation is negative; if the sign bit is cleared, the Jl!sult of
the data movement or arithmetic operation is positive. There
are no instructions that set or clear the Negative Bit since the
Negative Bit represents only the status of a result. The
instructions that effeCt the state of the Negative Bit are: ADC,
AND, ASL, BIT, CMP, CPX, CPY, DEC, DEX, DE)" EOR,
INC, INX, INY, LOA, LOX, LOY, LSR, ORA, PLA, PLP, ROL,
ROR, RTI, SBC, TAX, TAY, TSX, TXA, and TVA.
The Break ait (B) is, used to determine the condition which
caused theJRQ service routine tobe entered. If tneIRQ'service routine was entered because the CPU executed a SRK
command, the Break Bit will be setto logic 1. If the IRQ routine was entered as the result of an IRQ signal being generated, the B bit will be cleared to logic O. There are no
instructions which can set or clear this bit.
3.8.6 Overflow Bit (V)
The, Overflow ,Bit (V) is used to indicate thatthe result of a
signed, binary addition, or subtraction, operation is a value
that cannot be contained in seven bits (-128 "" n "" 127).
3-197
0'
',-'
R6511 Q Microprocessor and R6500113 Microcomputer
SECTION 4
PARALLEL INPUT/OUTPUT PORTS
& BUS MODES
The devices have 32 I/OUnes group~ into Jour 8-bit ports
(PA, PB,PC, !lnd PO). Ports A through C may be used either
for input or output individually or in groups of any combination.
Port,O may be used as a" inputs or
outputs.
Port 0 may only be a" inputs or all outputs. A" inputs is
selected by setting bit 5 of the Mode Control Register (MCR5)
to a "0".
a"
The status of the input lines can be interrogated at any time
by reading the I/O port addresses. Note that this will return
the actual status of the input lines, not the data written into
the I/O port registers.
'
Multifunction I/O's such aii! Port A and Port Care protectec!
from noril1lil port I/O instructions when they are programmed
to perform a multiplexed function.
Read/Modify/Write instructions can be used to modify the
operation of PA, PB, PC, & PD. During the Read cycle of a
Read/Modify/Write instruction the Port I/O register is read.
For all 'other read instruction!? the port input ,lines are read.
Read!Modify/Write instructions are: ASl, DEC, INC, LSR,
RMB; ROL, ROR, and 9MB.
Internal pull-up resistors (FET's with an impedance range of
3K E; RL ,;;; ,12K ohm) are provid8ci on all port pins except
Port D. A mask option to delete the internal pull-ups in 8;bit
port groups is available: "
The direction of the 32 I/O lines are contrOlled by four 8-bit
port registers located in page zero., This arrangement provides quick programming access using simple two-byte zero
page ac:jdress instructions. There are no direction registers
associated with the'I/O ports, thus simplifYing I/O handling.
The 'I/O addresses are shown iii Table 4-1. Appendix E.6
shows the I/O Port TIming.
4.2 OUTPUTS
Outputs for Ports A thru 0 are controlled by writing the
desired I/O line output states into the corresponding I/O port
register bit positions. A logic ~ wi" force a high (>2.4V)
output while a logic 0 will force a low «O.4V) output.
Port 0 all outputs is selected by setting MCR5 to a "1".
Table 4-1.
110 Port Addresses
Port
Address
A
B
C
D
0000
0001
0002
0003
4.3 Port A (PA)
Port A can be programmed via the Mode Control Register
(MCR) and the Serial Communications Control Register
(SCCR) as a standard parallel 8-bit, bit independent, I/O port
or as serial channel I/O lines, counter I/O lines, or an input
data strobe for the Port B input latch option. Table 4-2 tabulates the control alid usage of Port A.
4.1 INPUTS
In addition to their normal I/O functions, PAC and PA1 can
detect positive going edges and PA2 and PA3 can detect
negative going edges. A proper transition on these pins will
set a corresponding status bit in the IFR and generate an
interrupt request if the respective Interrupt Enable Bit is set.
The maximum rate at which an edge can be detected is onehalf the
clock rate. Edge detection timing is shown in Appendix E.5.
Inputs for Ports A, B, and C are enabled by loading logic 1
into all I/O port register bit positions that are to correspond
to I/O input lines. A low «0.8V) input signal will cause a logic
to be read when a read instruction is issued to the port
register. A high (>2.0V) input wi" cause a logic 1 to be read.
An RES signal forces all I/O port registers to logic 1 thus
initially treating a" I/O lines as inputs.
o
P2
3-198
R6511Q Microprocessor and R650011.3 Microcomputer
Table 4·2
PAO flO
Port A Control & Usage
PORT B LATCH MODE
"
=0
MCR4
MCR4
SIGNAL
PAO (2)
PIN 39
=
1
SIGNAL
NAME
TYPE
PAO
1/0
'.
NAME
TYPE
PORT .B
LATCH STROBE
INPUT (1)
PA1-PA31/0
PA1 (2)
PIN 38
PA2 (3)
PIN 37
PA3 (3)
PIN 36
SIGNAL
NAME
TYPE
PA1
PA2
PA3
1/0
I/O
1/0
II
PA4110
PA4
PIN 35
MCRO = 0
MCR1 = 0
SCCR7 = 0
RCVR SIR MODE
COUNTER A 1/0
MCRO = 1
MCR1 = 0
SCCR7 = 0
RCVR SIR MODE = 0
(4)
=0
(4) (5)
SIGNAL
SCCR7 = 0
SCCR6 = 0
MCR1 = 1
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
NAME
'j
PA4
1/0
CNTA
OUTPUT
CNTA
I
TYPE
INPUT (1)
SERIAL 1/0 SHIFT REGISTER CLOCK
seCR7
SCCR.5
=
=
1
1
RCVR SIR MODE
(4)
SIGNAL
I
I
NAME
XMTR CLOCK
NAME
OUTPUT
RCVR CLOCK
•
MCR3 = 0
MCR2= 0
MCR3
MCR2
SIGNAL
NAME
PA5
I
SCCR7
PAS
PIN 33
MCR3 = 1
MCR2 =X
SIGNAL
SIGNAL
NAME
TYPE
NAME
1/0
CNTB
OUTPUT
CNTB
SERIAL I/O
XMTR OUTPUT
=0
SCCR7
SIGNAL
=1
SIGNAL
TYPE
NAME
TYPE
·PA6
I/O
XMTR
OUTPUT
SERIAL I/O
RCVRINPUT
PA71/0
SCCR6
=0
SCCR6
SIGNAL
=1
SIGNAL
NAME
TYPE
NAME
TYPE
PA7
I/O
RCVR
INPUT (1)
3-199
TYPE
INPUT (1)
COUNTER B 1/0
=0
=1
NAME
PA7
PIN 32
I
I
TYPE
PA61/0
1
SIGNAL
TYPE
PA51/0
PAS
PIN 34
=
(1)
(2)
(3)
(4)
I
I
TYPE
INPUT(1)·
Hardware Buffer Float
Positive Edge Detect
Negative Edge Detect
RCVR SIR Mode = 1 when seCR6
' SCCR5 ' SCCR4 = 1
(5) For tlie following mode combin!ltions PA4 is available as an input
only pin:
SCCR7 oSCCRSoSCCR5oMCR1
+ seCR7·seCRSo7SCCR4oMCR1
+ SCCR7·SeCRS·SCCR5
+ SCCR7·SCCR5C·SCCR4.
R6511Q Microprocessor andR6500113 Microcomputer
bit 5 olthe MCR to 1 (one). Table 4-5 shows the necessary
settings for' the MCR to achieve the variOus modes for Port
D. Wilen· Port' 0 is selected to operate in the Abbreviated
Mode POO-PD? seivesas data register bits· DO-D? When
Port D is selected to rovide A 13 and A 14: The remaining ports p~rform the
normal I/O function.
Signal
Type
(1)
I/O
I/O
I/O
1/0
I/O
I/O
I/O
lio
Name
PBD
PBl
PB2
PB3
PB4
PB5
PBS
PB7
Type
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT'
In the I/O Bus'Mode all ports serve as 1/0. The address and
data bus are still functional but without A13 and A14. Since
the internal RAM and registers are inthe OOXX location, A 15
can be used for chip se.lect and AO-AI2 used fOr selecting
8K of external memc;>ry; Thus, the device can be used to
emulate the R6500/11 in the Normal Bus Mode.
(1) Resistive Pull-Up, Active ,Buffer Pull-Down
(2) Input data is stored in Port B latch by PAD Pulse
In the Abbreviated Bus Mode, the address and data lines can
be used as in the 110 Bus Mode to emulate the R6500/11.
POrtC arid .Port 0 are automatically transformed iritoan
abbreviated address bus and control signals (Port C) and a
bidirectional data bus (Port D). 64 Peripheral addresses can
be selected. In general usage, these 64 addresses would be
distributed to several external I/O deviCes such as R6522
and R6520, etc., each of which may contain more than one
unique address.
4.5 PORT C (PC)
Port C can be programmed as an I/O port, as part of the full
address bus, and, il1 conjunction with Port D,as an abbreviated bus, or as a multiplexed bus. When operating in the
Full Address Mode PC6 and PC? serve as A 13 and A 14. with
PCO-PCS operating as normal I/O pins. When used in the
abbreviated or multiplexed bus modes, PCO-PC? function as
AO-A3, A12, R/W, A13, and EMS, respectively, as shown in
Table 4-4. EMS (External Memory Select) is asserted (low)
whenever the internal processor .accesses memory area
between 0100 and3FFF. (See Memory Map, Appendix B).
The leading ·edge of EMS may be used to strobe the eight
address lines multiplexed on Port D in the Multiplexed Bus
Mode. See Appendices E.3 through E.5 for Port C timing.
In the Multiplexed Bus Mode, the operation is- similar to the
Abbrevialec;j Mode except that a fu1l16i< of external addresses
are provided. Po,rt C prOVides the lower addresses and control signals. Port.D multiplexes functions. During the first half
of the cycle it contains the remaining necessary 8 address
bits for 16K; during the second half of the cycle' it contains
a bidirectional data bus. The address b~s appearing on Port
D must be latched into an external holding register. The
leading edge of EMS, whicn' iridicates that the bus function
is active, may be used for this purPose.
4.6 PORT 0 (PO)
Figures 4-1 a thru 4-1 d .show the pOSl>ible configurations of the
four bus modes: Figure 4-2 shows a memory map of the port
as a function of the Bus Mode and further. shows which
addresses are .activeor inactive on each of the .three possible
buses.
Port 0 can bl' programmed as an I/O Port, an 8-bit tri-state
data bus, or as a multiplexed bus. Mode selection for Port
D is made by the. Mode Gontrol Register (MCR). The Port D
output driverS can be selected as tri-state drivers by setting
3-200
R6511Q Microprocessor and R6500/13 Microcoinpute,r
Table 4·4.
Port C Control & Usage
Full Address
Mode
MCR7
MCR6
=0
MCR7
MeR6
=0
Signal
Pin
#
54
55
56
57
58
59
60
61
Pin
Naine
Abbreviated
Mode
110 Mode
=0
MCR7
MCR6
=1
Signal
Name
Type
Name
PCO
PCl
PC2
PC3
PC4
PC5
A13
A14
I/ON
I/O (1)
VO (1)
I/O (1)
110 (1)
110(1)
OUTPUT (2)
OUTPUT (2)
PCO
PCl
PC2
PC3
PC4
PC5
PC6
PC7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
pea
PC4
PC5
PC6
PC7
=1
MeRl:= 1
MCR6" 1
=0
Signal
Type
(1)
PCO
PCl
PC2
Multiplexed
Mode
Signal
Type
Type
Name
(2)
Nam.
(2)
AO
Al
A2
A3
A12
RW
A13
EMS
OUTPUT
OUTPUT
OUTPUT
OUTP.UT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
AO
Al
A2
A3
A12
RW
A13
EMS
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
bUTPUT
OUTPUT
(1) Resistive Pull·Up. Active Buffer Pull·Down
(2) Active Buffer Pull·Up and Pull·Down
Table 4·5.
Port D Control & Usage
Abbreviated
Mode
110 Modes
=
MCR7
0
MCR6 = X
MCR5 = 0
MeR7
MCR6
MCR5
Signal
Pin
#
Pin
Name
62
63
64
1
2
3
4
5
POD
POl
PD2
PD3
P04
P05
P06
P07
(1) Tri·State Buffer
(2) Tri·State Buffer
(3) Tri·State Buffer
Name
PD~
PD1
PD2
PD3
PD4
P05
P06
POI'
Type
(1)
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
MCR7
1
MeR6 = 0
MCR5
1
MCR7
MCR6
MCR5
.Signal
Signal
Type
Name
POD
POl
PD2
PD3
PD4
P05
P06
P07
Multiplexed Mode
=
=
=0
=X
=1
(2)
Name
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
·OUTPUT
DATAO
DATAl
DATA2
DATA3
DATA4
OATA5
OATA6
DATA7
Signal
.2 High
Nama
'10
AS
I/O
I/O
I/O
I/O
I/b
I/O
A6
A7
A8
in High Impedance Mode
in Active Mode
in Active Mode only during the phase 2 portion of a Write Cycle
3·201
Signal
.2 Low
Type
(3)
I/O
A4
A9
Al0
All
=1
=1
=1
Type (2)
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
Name
DATAO
DATAl
DATA2
DATA3
DATM
OATA5
OATA6
DATA7
Type (3)
110
I/O
I/O
I/O
I/O
I/O
I/O
·110
II
R6511Q Microprocessor and R6500113 Microcomputer
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Figure 4-1.
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SYNC
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OF EXTERNAL
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j,
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~DB7
~
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Y.
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A. FULL ADDRESS MODE
Y"
0'100-,,,,
[=~"J
.........
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D. MULTIPl.EXED BUS MODE
Bus Mode Configurations
3-202
EXTEFINALI/OOR
MEMORY
ACTJYEFROII
[=1
(:"e:::
T
)
R6511 QMicroprocessor andR6500/13 Microcoin,puter
ABBREVIATED
MODE
MULTIPLEXED
MODE
NORMAL
MODE
FULL ADDRESS
MODE
-"'T"""--------, FFFF
8000
7FFF
INTERNAL BOOT
STRAP ROM
(R6500/13 ONLY
7FOO
7EFF
4000
3FFF
EMS VALID
(WHEN ABBR OR
MUX MODE
SELECTED)
1FFF
0100
OOFF
RAM AND
INTERNAL
REGISTERS
0010
OOOF
0003
110 PORTS
til
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3-203
aI
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0
INACTIVE
BE
II
R6511Q Microprocessor andR6500/13 Microcomputer
SECTION 5
SERIAL INPUT/OUTPUT CHANNEL
ASYNCHRONOUS MODE WITHOUT PARITY
The device provides a full duplex Serial I/O channel with programmable bit rates and operating modes. The. serial I/O
functions are controlled by the Serial Communication Control
Register (SCCR). The SCCR bit assignment.is shown in
Figure 5-1. The serial bit rate is determined by Counter A for
all modes except the Receiver Shift Register (RCVR SIR)
mode for which an external shift clock must be provided. The
maximum data rate ljsing the internal clock is 62.5K bits per
second (at ¢2 = 1 MHZ). The transmitter (XMTR) and receiver
(RCVR) can be independently programmed to operate in
different modes and can be independently enabled or
disabled;
!
8·BIT DATA
~~Tlll
____________________~~L-~'S~TO~P~
28TOP
6"eITOATA
5-IITOATA
1-8TOP
71 61
5 I
4 I
31 J 10
2
1
a-alT DATA
IPA~ITY I
foatTDATA
i ~-odd
Parity
.'. ,I-Even Parity
o P1Irlty Disable
1 Parity Enable
0
B Bits/Char
1
Bits/Char
1
Blta/Char
1
1 - 5 Bits/Char
o XMTR .. RCVR ASYN Mode
1 XMTR ASYN, RCVfl. SIR
X XMTR SIR, RClJR ASYN
1
o RCVR Disable
1 RCVR Enable
o XMTR Disable
1 XMTR Enable
Figure 5-1.
2 STOP
I Addr 0015
5--81T DATA
SHIFT REGISTER MODE 8·BIT DATA
I_____WD_R_D"_+,-'
M.'--'-'-_________-:-:WOfl,..D_·____.,-'__~-...
_7
0 00-6
00
I
ASYNCHRONOUS MODE WITH PARITY
7.BIT DATA
SCCRI
2 STOP
SHIFT l'IEGISTER CLOCK (PA4)
I
Figure 5·2.
SIO' Data Modes
In the SIR mode, eight data bits are always shifted out. Bits/
character and parity control bits are ignored. The serial data
is shifted out via the SO output (PA6) and the shift clock is
available at the CA (PA4) pin. When the transmitter underruns in the SIR mode the SO output and shift clock are held
in a high state.
..
Serial Communication Control Register
The XMTR Interrupt Flag bit (IFR7) is, controlled by Serial
Communication Status Register bits SCSR5, SCSR6 and
SCSR7.
Except for the Receiver Shift Register Mode (RCVR SIR), all
XMTR and RCVR bit rates will occur at one sixteenth of the
Counter A interval timer rate. Counter A is forced into an
interval timer mode whenever the serial I/O is enabled in a
mode requiring an internal clock.
IFR7 = SCSR6 (SCSR5
Whenever Counter A is required as a timing source it must
be loaded with the hexadecimal code that selects the data
rate for the serial I/O Port. Refer to Counter A (paragraph
6.1) for a table of hexadecimal· values to represent the desired
data rate.
+ SCSR7)
5.2 RECEIVER OPERATION (RCVR)
The receiver and its selected control and status functions are
enabled when SCCR-6 is set to a "1." In the ASYN mode,
data format must have a start bit, the appropriate number of
data bits, a parity bit (if enabled), and one stop bit. Refer to
paragraph 5.1 for a diagram of bit all()cations. The receiver
bit period is divided into 8 sub-intervals for internal synchronization. The receiver bit stream is synchronized by the start
bit and a l'trobe signal is generated at the approximate center
of each incoming bit. Refer to Figure 5-3 for ASYN Receive
Data Timing. The character assembly process does not start
if the start bit signal is less than one-half the bit time after a
low level is detected on the Receive· Data Input. Framing
error, over-run, and parity error conditions or a RCVR Data
Register Full will set the appropriate status bits. Any of the
above conditions will cause an Interrupt Request if the
Receiver Interrupt Enable bit is set to logic 1.
5.1 TRANSMITTER OPERATION (XTMR)
The XTMR operation and the transmitter related control/
status functions are enabled by bit 7 of the Serial Communications Control Register (SCCR). The transmitter, when in
the Asynchronous (ASYN) mode, automatically adds a start
bit, one or two stop bits, and, when enabled, a parity bit to
the transmitted data. A word of transmitted data (in asynchronous parity mode) can have 5, 6, 7, or 8 bits of data.
The nine data modes are shown in Figure 5-2. When parity is
disabled, the 5, 6, 7 or 8 bits of data are terminated with two
stop bits.
3-204
R6511 Q Microprocessor and R6500/13 Microcomputer
-
I nput --,
::
'=s::..-:rt-::a::-II.L...:LS-=a-'--· .....- -......-
I
I
received data has a parity error. This bit is cleared
'by reading the Receiver Data Register or by RES.
I
.....SIOp all SlOp Btl
SCSR 3: Framing Error-Set to a logic 1 when the received
data contains a zero bit after the last data or parity
bit in the stop bit slot. Cleared by reading the
Receiver Data Register or by RES (ASYN Mode
only).
SCSR 4: Wake-Up-Setto a logic 1 by writing a "1" in bit
4 of address: 0016. The Wake,Up bit is cleared by
RES or when the receiver detects a string of ten
consecutive l's. When the Wake-Up bit is set
SCSRO through SCSR3 are inhibited.
• Serlol Inpul 00.. Shifted In
Figure 5-3.
ASYN Receive Data Timing
In the SIR mode, an external shift clock must be provided ai
CA (PA4) pin along with 8 bits of serial data (LSB first) at the
SI input(PA7). The maximum data rate using an external
shift clock is one-eighth the internal clock rate. Refer to
Figure 54 for SIR Mode Timing.
SCSR 5: End of Transmission-Set to a logic 1 by writing
a "1" in bit poSition 5 01 address: 0016. The End
of Transmission bit is cleared by RES or upon
writing a new data word into the Transmitter Data
Register. When the End-aI-Transmission bit is true
the Transmitter Register Empty bit is disabled until
a Transmitter Under-Run occurs.
I :. . __. . .
Input
_..J...-'----'_ _.....
Data In
External
"""'L.J7"1.JL-~
Shift
Clock
Serial
Oulput
Shift
I
I
SCSR 6: Transmitter Data Register Empty-Set to a logic
1 when the contents 01 the Transmitter Data Register are transferred to the Transmitter Shift RegiSter. Cleared upon writing new data into the
Transmit Data Register. This bit is initialized to a
logic 1 by RES.
SCSR 7: Transmitter Under-Run-Set to a logic 1 when the
last data bit is transmitted if the transmitter is in a
SIR Mode or when the last stop bit is transmitted
if the XMTR is in the ASYN Mode while the Transmitter Data Register Empty Bit is set. Cleared by
a transfer of new data into the Transmitter Shift
Register or by RES.
: ~--.--"'T'"---,--T"""
__-'-__......_-'-__.....
Data Out
CIOCk~~
• Sarial Input Data Shifted In
.
.. Serial Output Data Makes Transition
Figure 5-4.
SIR Mode Timing
A RCVR interrupt (IFR6) is generated whenever any of
SCSRO-3 are true.
SCSR
5.3 SERIAL COMMUNICATION STATUS
REGISTER (SCSR)
The Serial Communication Status Register (SCSR) holds
information on various communication error conditions, status
of the transmitter and receiver data registers, a transmitter
end-of-transmission condition, and a receiver idle line condition (Wake-Up Feature). The SCSR bit assignment is shown
in Figure 5-5. Bit assignments and functions of the SCSR are
as follows:
Frame Error
Wak'Hlp
End 'of TransmisSion
Xt,lTR Data Ileg Empty
SCSR 0: Receiver Data Register Full-Set to a logic 1 when
a character is transferred from the Receiver Shift
Register to the Receiver Data Register. This bit .is
cleared by reading the Receiver Data Register, or
. by RES and is disabled if SCCR 6 ~ O. The SCS R
o bit will not be set to a logic f if the received data
contains an error condition; instead, a corresponding error bit will be set to a logic 1.
XMrR Under-Run
Figure 5-5.
SCSR Bit Allocations
5.4 WAKE-UP FEATURE
In a multi-distributed microprocessor or microcomputer applications, a destination address is usually included at the
beginning of the message. The Wake-Up Feature al.lows
non-selected CPU's to ignore the remainder oi the message
until the beginning of the next message by setting the WakeUp bit. As long as the Wake-Up flag is true, the Receiver
Data Register Full Flag remains false. The Wake-Up bit is
automatically cleared when the" receiver detects a string .of
11 consecutive 1's which indicates an idle transmit line.
When the next byte is received, the Receiver Data Register
Full Flag signals the CPU to wake-upend read the received
data.
.
SCSR 1: Over-Run Error-Set to a logic 1 when a new character is transferred from the Receiver Shift Register with the last character still in the Receiver
Data Register. This. bit is cleared by reading the
Receiver Data Register or by RES.
SCSR 2: Parity Error-Set to logic 1 when the RCVR is in
the ASYN Mode, Parity Enable bit is set, and the
3-205
R6511 Q Microprocessor and R6500113 Microcomputer
SECTION 6
COUNTER/TIMERS
Upper Latch A before the contents of the 16-bit latch are
transferred to Counter A. Counter A is set to the latch value
whenever Counter A underflows, When Counter A decrementsfrom 0000 the next counter value will be the latch
value-not FFFF-and the Counter A Underflow Flag (IFR
4) will be set to "1". Ttlisbit may be cleared by reading the
Lower Counter A at location 0018, by writing to address location Op1A,or by RES.
'
The device contains two 16-bit;counters (Counter A and
Couhter 8) and three l6-bit la~ches associated with the
.counters. Counter A has one 1'6-bitlatch and Counter B has
two 16-bit latches. Each counter can be independenlly pro.
grammed to operate in one of f0l!nnOdes:
Counter A
Counter B
• Retriggerable Interval Counter
• Asymmetrical Pulse
.
Generation
• Interv'al Timer
• Event Counter
• . Pulse width
measurement
• Pulse Generation
• Interval Timer
• 'Event Counter
Counter A oper~tes in any of four modes. These modes are
selected by the Counter A MOde Control bits in the Control
Register,
Operating modes of Counter A and Counter 8 are controlled
by the Mode Control Register. All counting begins' at the
initializatiohvaluearid decrements. When modes are selected
requiring a counter inpuVoutput line, PA4 is automatically
selected for CounterA ~nd PAS is automatically selected for
'
Counter 8 (see Table 4.2).
Counter A consists Of a,16-bit counter and a 1p-bit latch
organized as follows: Lower Counter A (LCA) , Upper Counter
A (UCA), Lower Latch A (LLA), and Upper Latch A (ULA).
The counter contains the count of either ~2 clOCk pulses or
external events, depending on the counter mode selected.
The contents of Counter A may be read any time by executing a read at' loc~tion 0019 for the Upper Counter A and
at location 001A or location 0018 for the Lower Counter A.
A read at location 0018 also clears the Counter A Underflow
Flag (lFR4).
0
0
1
1
0
1
0
1
Mode
Interval Timer
Pulse Generalion
Event Counter
PulSe Width Measurement
The Counter is set to the Interval Timer Mode (00) when a
RES signal is generated.
6.1.1 Interval Timer
In
the Interval' Timer mode the Counter is initialized to the
Latch value by either of two condili.ons:
1; When the Counter is decremented from 0000, the next
Counter Value is the Latch value (not FFFF).
The H)-bit latch contains the counter initia!ization value and
can be loaded at any time by executing a write to the Upper
Latch A at location 0019 and the Lower Latch A at location
0018. In either case, the contents of the accumulator are
copied into the applicable I,atch register.
2, When a write. operation is performed to the Load Upper
Latch and Transfer Latch to Counter address 001A,
the Counter is loaded with the Latch value. Note that
the contents of the Accumulator are loaded into the
Upper Latch before the Latch value is transferred to
the Counter,
Counter A can be started at any time by writing to address:
001 A. The contents of the accumulator will be copied into the
The Counter value is' decremented by one count 'at the 02
clock rate. The 16~bit Counter can hold fromlto 65535
counts, The Counter Timer capacity is therefore l/Ls 10 65,535
ms althe 1 MHz ~2 clock rate or. 0;5,.,.s to 32.767ms at the
2 MHz 1'\2 clock rate, Time intervals greater than the max·
imum Counter value can be easily measured by counting
IRQ interrupt requests in the counter IRQ interrupt routine.
I
: COUNTER UNDERFLOW
I 1
".1-.;.'_'..J..f..:(",UL"..;L:;;;L,;I,.J1,-,'(",uL;o.'",LL:....1"-,1_
COUNTER'--'-----'_-'---'-_'-,_ '
I
COUNTER"INTERRUPT ENABLED rl-....;,.------,--71-----~
'
.
SET ANY TIME SEFORE
COUNTER UNDERFLOW
COUNT.ER UNDERFLOW FLAQ
\
Ir--":I------
Figure 6·1.
MCRO
(bit 0)
The Interval Timer, Pulse Generation,and Pulse Width Measurement Modes are ~2 clock counter modes. The Event
Counter Mode counts the occurrences of an external event
on the CNTR line,
6.1 COUNTER ,A .
",
MCRl
(bit lJ
When Counler A decrements from 0000, the Counter A
Underflow (IFR4) is set to logic t. If the 'Counter A Interrupt
Enable Bit (IER4) is' also sel, an IRQ interrupt request will be
generated. The Counter A Underflow bit in the Interrupt Flag
Register can be examined in the IRQ interrupt routine to
determine that the IRQ was generated by the Counter A
Underflow.
Interval Timer Timing Diagram
3·206
R6511 Q Microprocessor and R6500/13 Microcomputer
The Counter A underflow flag will be set only when the count
in the timer reaches zero. Upon reaching zero the timer will
be loaded with the latch value and continue counting down
as long as the CA pin is held low. After the counter is stopped
by a high level on CA, the count will hold as long as CA
remains high. Any further low levels on CA will again cause
the counter to count down from its present value. The state
of the CA line can be determined by testing the state of PA4.
While the timer is operating in the Interval Timer Mode, PA4
operates as a PA I/O bit.
A timing diagram of the Interval Timer Mode is shown in
Figure 6-1.
6.1.2 Pulse Generation Mode
In the Pulse Generation mode, the CA line operates as a
Gounter Output. The line toggles from low to high or from
high to low whenever a Counter A Underflow occurs or a
write is performed to address 001A.
A timing diagram for the Pulse Width Measurement Mode is
shown in Figure 6.3.
The normal output waveform is a symmetrical square-wave.
The CA output is initialized high when entering the mode and
transitions low when writing to 001A.
--1 I-- T
II
PDSU
cN.,;-----\"'2.0.:..v_ _ _ _ _ _ _ _-'1
Asymmetric waveforms can be generated if the value of the
latch is changed after each counter underflow.
COUNT
A one-shot waveform can be generated by changing from
Pulse Generation to Interval Timer mode after only one
occurrence of the output toggle condition.
N-'
Figure 6·3.
I
N-2
I
N·3
Putse Width Measurement
6.1.3 Event Counter Mode
In this mode the CA is used as an Event Input line, and the
Coumer will decrement with each rising edge detected on
this line. The maximum rate at which this edge can be
detected is one-half the ~2 clock rate.
6.1.5 Serial 1/0 Data Rate Generation
Counter A also provides clock timing for the Serial 1/0 which
establishes the data rate for the Serial 1/0 port. When the
Serial 1/0 is enabled, Counter A is forced to operate at the
internal clock rate. Counter A is not required for the RCVR
SIR mode. The Counter I/O (PA4) may also be required to
support the Serial 1/0 (see Table 4-2).
The Counter can count up to 65,535 occurrences before
underflowing. As in the other modes, the Counter A Underflow bit (IER4) is set to logic 1 if the underflow occurs.
Figure 6.2 is a timing diagram of the Event Counter Mode.
,2
CNTR
--jr
PDSUf--
,
I
I
I
I
I
I
Table 6·1 identifies the values to be loaded in Counter A for
selecting standard data rates with a ~2 clock rate of 1 MHz
and 2 MHz. Although Table 6-1 identifies only the more
common data rates, any data rate from 1to 62.5K bps can
be selected by using the formula:
~~
I
I
r- Tpw-jIIr-- Tpw--jI II
I
I
COUNT
N·'
I
N =
N·2
-1
16 x bps
where
N
Figure 6·2.
_.c:~2=---_
Event Counter Mode
~2
bps
6.1.4 Pulse Width Measurement Mode
decimal value to be loaded into Counter A using
its hexadecimal equivalent.
the clock frequency (1 MHz or 2 MHz)
the desired data rate.
NOTE
This mode allows the accurate measurement of a low pulse
duration on the CA line. The Counter decrements by one
count at the ~2 clock rate as long as the CA line is held in
the low state. The Counter is stopped when CA is in the high
state.
In Table 6-1 you will notice that the standard data rate
and the actual data rate may be slightly different.
Transmitter a'nd receiver errors of 1 .5% or less are
acceptable. A revised clock rate is included in Table
6-1 for those baud rates which fall outside this limit.
3-207
R6511 Q Microprocessor and R6500/13 Microcomputer
Table 6·1.
Standard
Baud
Rate
50
75
110
150
300
600
1200
2400
3600
4800
7200
9600
Counter A Values for Baud Rate Selection
Hexadecimal
Value
1 MHz 2 MHz
O4E1
0340
0237
01AO
OOCF
0067
0033
0019
0010
OOOC
0008
0006
09C3
0682
046F
0340
01AO
OOCF
0067
0033
0021
0019
0010
OOOC
Actual
Baud
Rate At
1 MHz
2 MHz
50.00
75.03
110.04
149.88
300.48
600.96
1201.92
2403.85
3676.47
4807.69
6944.44
8928.57
50.00
74.99
110.04
150.06
299.76
600.96
1201.92
2403.85
3676.47
4807.69
7352.94
9615.38
6.2.1 Retriggerable Interval Timer Mode
Clock Rate
Needed
To Get
Standard
Baud Rate
When operating in the Retriggerable Interval Timer mode,
Counter B is initialized to the latch value by writing to address
001 E, by a Counter B underflow, or whenever a positive edge
occurs on the CB pin (PA5). The Counter B interrupt flag will
be set if the counter underflows before a positive edge occurs
on the CB line. Figure 6-4 illustrates the operation.
1 MHz 2 MHz
1.0000
1.0000
1.0000
1.0000
1 .0000
1.0000
1.0000
1.0000
0.9792
1.0000
1.0368
1.0752
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
1.9584
2.0000
1.9584
2.0000
CB Line
4 / Reset by Software
--IIlL.._____
Counter B _ _ _ _ _ _
Flag
6.2 COUNTER B
Figure 6-4.
Counter B consists of a 16-bit counter and two 16-bit latches
organized as follows: Lower Counter B (LCB), Upper Counter
B (UCB), Lower Latch B (LLB), Upper Latch B (ULB), Lower
Latch C (LLC), and Upper Latch C (ULC). Latch C is used
only in the asymmetrical pulse generation mode. The counter
contains the count of either ~2 clock pulses or external
events depending on the counter mode selected. The con·
tents of Counter B may be read any time by executing a Read
at location 0010 for the Upper Counter B and at location
001 E or 001 C for the Lower Counter B. A Read at location
001 C also clears the Counter B Underflow Flag.
Counter B. Retrlggerable Interval Timer Mode
6.2.2 Asymmetrical Pulse Generation Mode
Counter B has a special Asymmetrical Pulse Generation
Mode whereby a pulse train with programmable pulse width
and period can be generated without the processor interven·
tion once the latch values are initializ,ed.
In this mode, the 16-bit Latch B is initialized with a value
which corresponds to the duration between pulses (referred
to as 0 in the following descriptions). The 16-bij Latch C is
initialized with a value corresponding to the desired pulse
width (referred to as P in the following descriptions). The
initialization sequence for Latch Band C and the starting of
a counting sequence are as follows:
Latch B contains the counter initialization value and can be
loaded at any time by executing a Write to the Upper Latch
B at location 0010 and the Lower Latch B at location 001 C.
In each case, the contents of the accumulator are copied into
the applicable latch register.
1. The lower 8 bits of P are loaded into LLB by writing to
address 001C; the upper 8'bits of P are loaded into
ULB and the full 16 bits are transferred to Latch C by
writing to address location 001 D. At this point both
Latch B and Latch C contain the value of P.
Counter B can be initialized at any time by writing to address:
001E. The contents of the accumulator is copied into the
Upper Latch B before the value in the 16-bit Latch B is trans·
ferred to Counter B. Counter B will also be set to the latch
value and the Counter B Underflow Flag bit (IFR5) will be set
to a "1" whenever Counter B underflows by decrementing
from 0000.
2. The lower 8 bits of 0 are loaded into LLB by writing to
address 001 C; the upper 8 bits of 0 are loaded into
ULB by writing to address location 001 E. Writing to
address location 001 E also causes the contents of the
16-bit Latch S to be downloaded into the Counter B
and the CB output to go low as shown in Figure 6-5.
IFR 5 may be cleared by reading the Lower Counter B at
location 00lC, by writing to address location 001E, or by
RES.
3. When Counter B underflow occurs the contents of the
Latch C are loaded into the Counter B and the CB output toggles to a high level, staying high until another
underflow occurs. Latch B is then down-loaded and the
CS output toggles to a low level repeating the whole
process.
Counter B operates in the same manner as Counter A in the
Interval Timer and Event Counter modes. The Pulse Width
Measurement Mode is replaced by the Retriggerable Interval
Timer mode and the Pulse Generation mode is replaced by
the Asymmetrical Pulse Generation Mode. Mode Control
Register bits MCR2 and MCR3 select the four Counter B
modes in a similar manner and coding as MCRO and MCRl
select the modes of Counter A.
3-208
R6511 Q Microprocessor and R6500/13 Microcomputer
SECTION 7
POWER ON/INITIALIZATION CONSIDERATIONS
7.3 RESET (RES) CONDITIONING
7.1 POWER ON TIMING
After application of Vee and VRR power to the device, RES
must be held low for at least eight
clock cycles after Vee
reaches operating range and the internal OSCillator has stabilized. This stabilization time is dependent upon the input
Vee voltage and performance of the internal oscillator. The
clock can be monitored at
(pin 3). Figure 7-1 illustrates
the power turn-on waveforms. Clock stabilization time is typically 20 ms.
When RES il;> driven from low to high the device is put in a
reset state causing the registers and I/O ports to be configured as shown in Table 7-1.
p2
Table 7-1. RES Initialization of 110 Ports and Registers
p2
Bit No.
REGISTERS
Processor Status
Mode Control (MCR)
Inl. Enable (IER)
Inl. Flag (IFR)
Ser. Com. Control (SCCR)
Ser. Com. Status (SCSR)
+5·----------------< ....- - - - -
Vcco~
...
'-...POWERON
XTLO~1lJU1flJ1J1JUl
STABILIZATION
PORTS
PA Latch
PB Latch
PC Latch
PD Latch
'2~JUlJlJ1J1fl.nJ1
I~CLO~
RES
CYCLES M I N ' r -
Figure 7-1.
7
6
5
- - 0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
4
3
2
1
0
-
-
-
0
0
0
0
1
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
All RAM and other CPU registers will initialize in a random,
non-repeatable data pattern.
Power Turn-On Timing Detail
7.2 POWER-ON RESET
When RES goes from low to high, the device sets the Interrupt Mask Bit-bit 2 of the Processor Status Registerand initiates a reset vector fetch at address FFFC and FFFD
(or optionally 7FFE and 7FFF) to begin user program execution. All of the I/O ports (PA, PB, PC, PD) will be forced
to the high (logic 1) state. All bits of the Control Register will
be cleared to logic 0 causing the Interval Timers counter
mode (mode 00) to be selected and all interrupt enabled bits
to be reset.
7.4 INITIALIZATION
Any initialization process for the device should include a
RES, as indicated in the preceeding paragraphs. After stabilization of" the internal clock (if a power on situation) an
initialization subroutine should be executed to perform (as a
minimum) the following functions:
1. The Stack Pointer should be set
2. Clear or Set Decimal Mode
3. Set or Clear Carry Flag
4. Set up Mode Controls as required
5. Clear Interrupts
CB
OUTPUT
2
A typical initialization subroutine could be as follows:
4
3
LDX
I--D-lpl-1&3. COUNTER B
LATCH B (D)
2&4. COUNTER B
LATCH C (P)
Figure 6-5.
TXS
CLD
SEC
CLI
Counter B Pulse Generation
3-209
Load stack pointer starting address into
X Register
Transfer X Register value to Stack Pointer
Clear Decimal Mode
Set Carry Flag
Set-up Mode Control and
special function registers
and clear RAM as required
Clear Interrupts
II
R6511Q Microprocessor andR6500/13 Microcomputer
APPENDIX A
ENHANCED R6502 INSTRUCTION SET
This appendix contains a summary of the Enhanced R6502
instruction set. For detailed information, consult the R6502
Microcomputer System Programming Manual, Document
29650 N30. The four instructions notated with a • are added
instructions to enhance the standard 6502 instruction set.
A.1 INSTRUCTION SETIN ALPHABETIC
SEQUENCE
MNEMONIC
ADC
AND
ASL
*BBR
*BBS
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRK
BVC
BVS
INstRUCTION
MNEMONIC
Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)
Branch on Bit Reset Relative
Branch on Bit Set Relative
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set
CLC
CLD
CLI
CLV
CMP
CPX
CPY
Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear .overflow Flag
Compare Memory and Accumulator
Compare Memory and Index X
Compare Memory and Index Y
DEC
DEX
DEY
Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One
EOR
"Exclusive-Or" Memory with
Accumulator
INC
INX
INY
Increment Memory by One
Increment Index X by One
Increment Index Yby One
JMP
JSR
Jump to New Location
Jump to New Location Saving Return
Address
Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One BitRight (Memory or
Accumuliltor)
NOP
No Operation
ORA
"OR" Memory with Accumulator
PHA
PHP
PLA
PLP
Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack
*RMB
ROL
Reset Memory Bit
Rotate One Bit Left (Memory or
Accumulator)
Rotate One Bit Right (Memory or
Accumulator)
Return from Interrupt
Return from Subroutine
ROR
RTI
RTS
SsC
SEC
SED
SEI
'SMB
STA
STX
STY
TAX
TAY
TSX
TXA
TXS
TYA
3-210
INSTRUCTION
LDA
LOX
LOY
LSR
Subtract Memory from Accumulator with
Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Accumulator to Index X
Accumulator to Index Y
Stack Pointer to Index X
Index X to Accumulator
Index X to Stack Register
Index Y to Accumulator
A.2 R6511Q AND R6500/13 INSTRUCTION SET SUMMARY TABLE
::D
0)
PROCESSOR STATUS
CODES
ADDRESSING MODES
OPERATION
MNEMONIC
ADC
AND
ASL
BBRI'I"-711
BBS/'10-7ll
BCC
BCS
BEQ
BIT
BMI
BNE
BPl
BRK
Bve
BVS
CLC
CLO
CLI
CLV
eMP
CPX
CPY
DEC
OEX
DEY
EOR
~
INC
INX
INY
A
MMEDlATEIASSOLUTEIZEROPAGEI ACCUM.
~M ~e---.A
(4)\1)
(1)
c~~
Branchon~"'O [5)(2)
A M----A
.....
BranchonC,,1
(2)
BranchonZ=l
(2)
IZ.PAGE,
xl
1
ABS,X
ABS,Y
BranchonV=O
BranchonV 1
9F
AF
BF
CF
OF
EF
FI'=
•
Z C
Z
Z C
M,Me • • • •
30 12 12
DO
10
1a
oa
5B
BB
X M
E022EC43E4
C022CC43C4
CE63C6
Y ·M
M 1-M
CA
88
(1)
49121214D.
E6
X·l-X
No Operation
AVM--A (1)
J\.-.-.Ms 5 1-5
P--Ms 5 1--5
S· 1----5 Ms-A
S -1---05 Ms----P
O-Mn (S)
~
~
Rtrn Inl (See Fig. 1)
Atrn Sub (See Fig. 2)
A M c-.A (1)
l-C
1-0
1-T
1 ~M" (5)
A_M
X---+M
Y_M
121'
2 ,_
4513 12
EE
M-l-M
411 61 2 151 15121 ~ I: 1~ I~~ I·; I3 I59 I 4
13
EB 121'
2 1
AD
Asl3
AE 4 '3 AS
21AC43A4
1 1
4E f 6 3 f 46
All 6 I 2 I Bl I 5 I 2 I B5! 4 I 2 I BO I 4 I 3 I B9
BE
B414121BC14
2
2
2
5 12 14A I 2 11
0912
2 I 00 I 4 I 3
f
05
o '
56625E7
EA 12
f
01
f
6 t 21 11 t 5- I 2 I 151 4 I 2 110 I 4 I 3 I 19 I 4 13
C=;.
z C
1
I 3 I2
~
3:
Z
Z
Z
N
, z
N '
4
4,
N
J
Z '
'
(Restored)
1
071171271371471"571671771·
., ~~ I: I; I !: I ~ I~ I~: I ~ I ~
E912121EOl4131
E5~312
: I: Ii
3B
Fa
7a
I2
A-Y
IA_X
s-x
X_A
x-s
V-A
NOTES
1. Add 1 to N if page boundary is crossed
2. Add 1 to N if branch occurs tQ same page
Add 2 to N if branch occurs to different page
3. CallY not = Borrow
4. If in decimal mode Z flag is invalid
accumulator must be checked on zero result.
5. Effects 8-bit data field of the specified zero page address.
;:1 :I~I;~I~I;
Ell 61 21 Fll 51
2I
F51
4I
2
I FD I 4 I
3
z C
Z C
N
N
(Restored)
I
F9
I 4 13
,
Z (3)
N V
,
1 '
,1
811 61 21 91
BOl4131
B513·12
8
E438
632
8C438432
I 6- t
2
I
951 4
I"
2
I
901 51 3
Ie, I
,a71971 A71 B7 IC71 071 E7 IF7
5 f 3
961412
941 41 2
AB
AA
BA
8A
2 1
121'
2
2
9A 21'
98
2
a
n
0
4al33 11
oa
6B
2a
iUI
....
-
z
IN
N
B61 4 I 2 I
0-
C)
C)
Z
Z
Z
I,
6C I 5 13 I
AD"
20 64 ..31
3
Z
Z
N '
C8
:::s
z
I~
I I I
S»
z C
Z C
Z C
N
4C I 31 3
A9
A2
0
, 0
, 0
N
N
N
N
D6-16121DE1713
1--X
Y 1-Y
"..
18
.
CD
, 0
C,I 61 2 I 011 5 I 2 1051 4 I 2 I DO I 4 I 3 109 I 4 13
3:
C=;.
(I)
1(1)
'
o '
C9121~·ICOI413IC5
A Mill
z .
, ,
~ I~ I~
(2)
(2)
"...
0
•
00 I 7 11
O-v
AVM-A
B D I Z C
NV
N
N
OFI'FI2FI3F I'FI5FI6F 17FI' ,
Fa 12 12
O-C
0-0
0-1
X
76543210
IRELATIVE
8F
8r-eak(See FIg. 1)
O~.~-C
TXA
TXS
TYA
(IND),Y
2C14{31241312
lSA
TSX
I
(2)
(2)
12}
N('p
ORA
PHA
PHP
PLA
PLP
RMB[#{O-7)j
TAX
TAY
(IND,X)
90
BO
AAM
Branch on N=l
Branch on Z = 0
Branch on N=O
JSA
LOA
LOX
LOY
RDl
ROA
Rli
AT5
SBC
SEC
SED
SEI
5MB{#(D-7)J
STA
STX
STY
I
IM~LlED
Branch on M. .. 1 (5)(2J
Branch on C = 0
(2)
Y-l--+Y
Jump to New Lac
Jump Sub (See F'9. 2)
M~A
(1)
M--X (1)
M--Y (1)
JMP
I
OP I n I. lOP I • I .1 Op I • ,. lap' • I .1 Op I • I. lopi • I • lop\ • I. 101'1 • I. lop I. I. lop I·. I.'OP I • I.
'70
61
71
751 4
69
'9
601413165
35
3D
39
204325
29
3'
2'
OA 1 2 I 1
OE 6 3 06
'E 17
'6
........
UI
1
z '
N '
M,
LEGEND
X
Y
A
M
M,
M,
M,
Index X
Index Y
Memory BitS
Add
Subtract
And
Accumulator
A
Memory per effective address
Me'1lOry per stac:-k pointer
Selecter' zero page memory bi1
Memo2
\
EDGE.DETECTS
(PAO-PA1)
1.5V
1.5V
J
...
PAO-PA!{
PBO-PB7
pCO-PC7
l~
TcvC
.1'"
TpDSU
>t'.
.
I
---
'---'
TpHR
K
)
TEPW
CNTR
PA2
~ 1.5V
. 1.5V
-;f
1.5V }
...
TCpw
TCD
CNTR
PA2
Tcpw
2.4V
O.4V
T pDDW
PBO-PB7
>t
I
TCMOS
PAO-PA7
PBO-PB7
PCO-PC6
TPDW
2.4V
.. I
VDD-30
I
O.4V
3-250
Fl~5/41 EB .R65/41 EAB
R6500 Microcomputer Sy!Sfem
'1'
R65/41EB AND "R65/41EAB
BACKPACK EMULATORS
Rockwell
II
FEATURES
INTRODUCtiON
T.he Roc~n R65141 EI;l and R65/41 EA~ e!.ackflack Emulator
is the PROM prototypil1g version 'of the. ~8~bit."masked~ROM
R6500141 one-chip microcomputer. Uke' the R6500/41,"the
backpack d9\iice is totally upward/downward compatible with all
members of the R6500141 family. It is designed to aCcept stan~
dard 5-volt, 24-pin EPROMs or ROMs directly, in a socket on
top of the Emulator. This packaging' concept allows a standard
EPROM to be easily removed, re-programmed, then reinserted
as often as desired.
". PROMYe~sioJ1 of the R6500/4.1
..'
• All Host bus'featl.Jres of R6500/41
,"
..
• Completely pin compatible With R6500/4t single-ehip micro. '.
computers
' "
• Profile approaches 40-pin DIP ofR6500/41
• Acaepts5 volt, 24-pin industry-standard EPROMs
-4K memories-'--2732, 2732A
• U~ as prototyping tool or for low volume production
• 4K bytes of memQrycapacity
• 64 x 8 static RAM
• Software compatibility with the R6500 family
• 23 bi-directional TTL compatible VO lines
• 16 bit· programmable counter/latch with four modes (interval timer, pulse generator, evel'lt counter, pulSE! width
measurement)
.7 interrupts (reset, two external edge sensitive, counter
underflow, Host data received, Output data register full; Input
data register empty).
Ttre backpack devices have the same pinouts as the maskedROM R6500/41 microcomputer. These 40 pins are f!lnction~lIy
and operationally identical to the pins on the R6500/41. The
R6500/41 Microcomputer Product Description (Rockwell Document No. 29651N38, Order No. 2135) includes a description of
the interface'signlils and their functions, Whereas the maskedROM R6500/41 providetF1.5K bytes of read-only memory; the
R65141 Ee will address '4,oKbyles of extemal program memory.
This extra memory accommodates program patches, test programs or optional programs du~ing breadboard and prototype
development states.
',
.. "
. ,
• .External time base
• Single +5V power 'supply
ORDERING INFORMATION
"Backpack EllIulator
Pa~t
Ml!!11ory
Number
Capacity
R65141EB
4K x 8
R65141EAB
4K x
iI
,CbmPetibJe" I"
"'8I1Ioti88 '.
2732
"~I
Number
~5·040
M65-131
M65-132
RDC-1001
ROC-131
RDC-132
O"C 1070'C
1MHz
2732A
....
O"C to 70"C
.....2 MHz· ,.
Support Products
','
.
Part
565-101
t8inperatu~
[:.1
Range ant!.~~ ,.
I
.
."
o.sCrlpt!~
$yS:reM~65.Microqomputer
Development System:'
PROM Programmer 'Module
1.-f).4Hz R13.500141 persQnalityModule
2,MHzR6500/41 Personality Module,
"Rocl\We,1I Oevelopmel)l Center
.
1 MHz 1'l6500/41 Personality Set(RDC)
2 MHz R6500141 Personality Set (ROC)
R~5/41 EB-R65/41 EAB 'Bl!okpack Emulator
Document No. 29001014
No. 0114
February 1,983
Data Sheet Order
3-251
Backpack Emulators
R65/41EB. R65/41EAB
CONFIGURATIONS
PRODUCT SUPPORT
The Backpack Emulator is available in two different versions,
to accommodate 1 MHz. lind 2 MHz speeds. Both versions
as well as 24 signals to
provide 192 bytes of RAM and
support the external memory "backpack" socket.
The Backpack Emulator is just one of the products that Rockwell offers to facilitate system lind program develOpment
for the R6500/41.
.
.
va,
The SYSTEM 65 Microcomputer Development System with
R6500/41 Personality Module supports bOth hardware and
software development. Complete in-cir(:uit user emulation
with the R6500/41 Personality Module allows total system
test and evaluat.ion. With the optional PROM Programmer,
SYST,EM 65 can also be used to program EPROMs for the
development activity. When PROM programs have been finalized, the PROM device can be sent to ROCkwell for masking
into the 1.5K ROM of the R6500/41.
"
External 4K memories with addresses of 000 to FFF, are
upward translated to addresses FOO() toFFFF when assembled to form the Backpack Emulator.
EXTERNAL FREQUENCY REFERENCE
The external frequency reference is an outpultiming signal
~2. This is an internally synchronized 1 x clock output suitable for external memory or peripheral interfacing.
In addition to support products, Rockwell offers regularlyschedul9d designer courses at regional centers.
1/0 PORT PULLUPS
The emulator devices haVe internal VO port pullup reSistors
on ports A and C. Port B has tri-state drivers.
CLKIN
CLOCK
OSCILLATOR
INTERRUPT
LOGIC
PROM/
ROM
40 R6500/41
24 PROM/ROM
PINS
COMPATIBLE PINS
R65/41EB Interface Diagram
3-252
Backpac'k,Ernulators
R85/4,1 EB. R65/41 EAB
,
CS,
BACKPACK MEMORY SIGNAL
Vee ,
, ClKIN
E (RO)
RiN (Wi!i)
DESCRiPTION
'RES
RS(A(i) ,
HD2
PB7
PB6
PBS
PB4
H03
PB3
HD4
HD5
PB2
PBl
H07
PBO
PA7
Pet
PAS
HOO
HOl
Hoe
pcO
Signal"
Name
DO-D7
PA4
PC4
PA2
PAl
AO-Ae
Al0,
All
PA3
PeS
Pee
~
Description
Datil Bus Wnes, All', instrUctiQnand data
transfers take
on thl1 data bus lines.
The buffers driving tl18 data bus lines have
full three-state capability. Each'data bus
'pin is coimected to
input and an output
buffer; with the output buffer. remaining in
the floating condition.
place
an
PA6
PC2
Pe3
Pin No.
9S~11 S,
13S-17S
CE
OE
lS-8S,
22S,,23S
19S,21S
. ISS
20S
PAO
V's
Address Bus Unes. The address bus lines
are ·bl.lflered by push/pull type drivers that
can drive one standard TTL load.
q/:1ip Enable.
Memory Enable Una. this Signal provides
the output enable' for the memory to place
information on the data bus lines. This
signal is driven by the
signal from the
CPU and then Inverted to 'form OE. This
signal is driven by the inverted address line
All. The OE signal will be low for
addresses greater than OFFF.
Riiii
Pin Configuration
(1) PIN 21 Is Vee for R65/41EB or All for R65/41EB
V~e·
245
Main Power SupplY +5V. This pin is tied
directly to pin 40 (V eel.
Vss
12S
Signal and Power Ground (zero volts). This
pin is tied directly to pin 21 (V sSl.
:
.. '
,110 AND lNTERNAL Rt:GIST&R ADDRESSES
Reed
Address
: 16
lA
19
18
"
17
16
15
14
13
12
11
10
03thru OF
02
01
0000
Write
--
,,'d01F
IE
10
lC
-:-
,1-,-"
Input
--
"
... ,
Datil~giste~(IOR)
',;.L~
0lllPUt Data Regls!&!,
--
"
"
Lower Counter
' Lower Counte~ & ,Clellr Fla~ (IFRS)
Upper Counter
--Mode Control Register
. ,",
~-
---
Mode ,Control Register
--,
--
InlElirl.lpt ~nable Register
Inierrupt Flag RegiSter
Read "FF;'
Interrupt Enable' !;Iegister
-~,
Clear Int Aa~ Bit
--
PortC
PoriB
PortA
~i
(OoR)':
"
.
t~IL
Lower Latch
Upper Latch/Transfar Latch to Counter & Clear FIIIQ (IFRS)
Upper Latch
.
"':' ,'
"" ,
~-
..
,H~st. Status Flag Register,
Host StatusFIaQ f!i,gister
--
,
PortC
PortB
PortA
"
II
~5i41EB.
R65/41EAB
Backpack Emulators
READ TIMIN~ CHARACTERISTICS
'tMHz
..
Signal
Symbol'
OE and CEsetup time from CPU
Addre'sssetupllme from CPU
Memory read access time
2 MHz
Min.
Mall'.
Min.
Max.
Unit
TOES
-
225
'. TAOS
-
225
-.
-
700
140
140
315
ns
ns
ns
sel
Data
up time
Data hold tirne-'-Read
T ACC
THR
AddreSs hold time
OE and CE hold time
'CycIeTIms'
T HA
30
T HOE
30
1.0
Tcyc
-
-
50
10
Tosu
30
-
ns
ns
ns
ns.
0.5
10.0
/Ls
35
10
30
10.0
.
READTIMIN'G. WAVEFORMS
ABBREVIATEQ BUS
MODE MEMORY MAP
Fl'FE
IRQ VECTOR
FFFC
RlSVECTOR
I
I\IlJLTIPLEXED BUS
MODE MEMORY MAP
, F
EllS
(~VE
~M1.IK
1
001 F
INTERNAL
REGISTERS
PUaPHeRAL
DE~E .
1
ROM (2.5K)*
,
MEMORY
-
, "HOI.,,""" for malked ROM A6500/41.
4CJlI6.121 BYTES
-
I
a,e
BUS
INTERNAL RAM
(84 BmES)
,
INTERNAL
I/O oNtD ~EGlSTEAS
·NoIavallable for ma8Ud ROM R65OOI41. '
3·254
T
I--~---i"'.
MULT1PLEXED
DATA AND ADDRESS
UNASSIGNeD
INTERNAL
IJO PORTS A,
INTERNAL
REGISTERS
EXTERNAL
1I
INTERNAL RAM
(84 BYTES)
110 AND REGISTERS
T
0010 EMS (ACTIVE LOW)
ADDRESSES
UNASSIGNED
EXTENDED
OFFF
ZONE FOR 18
INTERNAL
RoM1.SK
FJ..
EXTENOED
,
LOW)
IHOVECTOA
RES VECTOR
FFFB
ROM,....)·
T
FFE
FFFC
INTERNAL
110 POAfS A.. B,C
*A8500/42 ONLY
I
R65i41 EB. R&5/41 EAB
Backpack Emulators
ELECTRICAL CHARACTERISTICS
(Vee - 50 + 5% , Vss - 0, T A- 25°C)
--
CharacteriStic
Symbol
Input High Threshold Voltage
00-07
V IHT
Input !,ow Threshold Voltage
00-07
V ILT
Three-Stala (Off Stala) Input Current
(V = 0.4 to 2.4V, Vcc = 5.25V)
00-07
I TSI
Output High Voltage
(IWAD = 1001£ Ade, Vce
00-07, AO-All, OE, CE
VOH
= 4.75V)
MIl:!
Typ
Max
Unit
Vss + 2.0
-
Vde
-
-
Vss + 0.8
Vde
-
-
± 10
Vss + 2.4
-
-
-
-
Vss + 0.4
0.50
!LA
Output Low Voltage
(ILOAD = 1.6 mAde, Vcc = 4.75V)
00-07, AO-All, (5E, ~
VOL
Power Dissipation (less EPROM)
Po
Capacitance
(V in = 0, TA = 25'C, f = 1 MHz)
00-07 (High Impedance Stala)
Input Capacitance
C
Cout
Cln --
-
-
10
10
VO Port Pull-up Resistance
RL
3.0
6.0
11.5
-
Vde
W
pF
21
[]
20
1---------:2.020MA.--------I
. I-j----1.220MA.
t
I
----I
O.oSO •. Q20
:~~Jt=1
~'"-I
-~iJO'050 =.015 BOTH ENDS -{~
-
Vde
I....
o.tOO:t.OtOTVP
-:t. .003
1.';VP
,REF
4D-Pln Backpack Package
3-255
-
O.D40"':.::TYP
0.115
MAX
0.1:25
MIN
kohm
R6541 Q • R6500/43
R6500 Microcomputer System
'1'
Rockwell
R6541Q AND R6500/43
INTELLIGENT PERIPHERAL CONTROLLERS
SECTION 1
INTRODUCTION
1.1 FEATURES OF THE R6541Q &
R6500/43
• Directly compatible with 6500, 6800, 8080, and Z80 bus
families
• Asynchronous Host interface that allows independent clock
operation
• Unmultiplexed Address and Data buses for 4K of Peripheral I/O expansion
• 68% of the instructions are executed in less than 2J.1.s @
2 MHz
• NMOS-3 silicon gate, depletion load technology
• Single +5V power supply
• Input, Output and Status Registers for CPU/Host data
transfer
• Status register for CPU/Host data transfer operations
• Interrupt or polled data interchange with Host
• 64-pin QUIP
• Enhanced 6502 CPU
• Four new bit manipulation instructions
• Set Memory Bit (SMB)
• Reset Memory Bit (RMB)
• Branch on Bit Set (BBS)
• Branch on Bit Reset (BBR)
• Decimal and binary arithmetic modes
•
•
•
•
NOTE
This document describes both the R6541 Q and
R6500/43. In the text, the terms IPC or device will be
used when describing both parts. See Section 1.3 for
a description of the options available for the R6500/13
and the fixed features of the R6541 Q.
• 13 addressing modes
• True indexing
256-byte mask-programmable ROM'
64-byte static RAM
23 TTL-compatible I/O lines
A 16-bit programmable counter/timer, with latch
• Pulse width measurement
1.2 SUMMARY
The Rockwell R6541Q and R6500/43 One-Chip Intelligent
Peripheral Controllers (IPC) are general purpose, programmable interface I/O devices designed for use with a variety
of 8-bit and 16-bit microprocessor systems. They have an
enhanced R6502 CPU, an optional 256 by 8-bit ROM, 64 by
8-bit RAM, three I/O ports with multiplexed special functions,
a multi-function timer, and a full 4K address and data buses
all contained within a 64-pin Quad-in-line package.
• Pulse generation
• Interval timer
• Event counter
• Eight interrupts
• Two edge-sensitive lines; one positive, one negative
•
•
•
•
•
•
In both versions, special interface registers allow these IPC
devices to function as peripheral controllers for the 6500,
6800, Z80, 8080, and other 8-bit or 16-bit host microcomputer systems.
Reset
Counter Underflow
Host data received
Output Data Register full
Input Data Register empty
Non-maskable
The innovative architecture and the demonstrated high performance of the R6502 CPU, as well as instruction simplicity,
results in system cost-effectiveness and a wide range of
computational power. These features make the device a
leading candidate for IPC computer applications.
• Multiplexed bus expandable to 4K bytes of external rnemory
'R6541Q has no ROM.
Document No. 29651 N39
Product Description Order No. 2136
3-256
Rev. 1, August 1983
Intelligent Peripheral Controllers
R6541 Qand R6600/43
• Without ROM
• Reset Vector at FFFC
• No internal pull-up resistors on any Port (PA or PC)
Rockwell supports development of the R6541.Q and R6500/43
with the System 65 Microcomputer Development System and
the R6500r Family of Personality Modules~ Complete .
in-circuit emulation with the R6500r Family of Personality
Modules allows total system test and evaluation.
elK CIRCUIT
This product description assumes that the re.ader is familiar
with the R6502 CPU hardware and programming capabilities.
A detailed description of the R6502 CPU hardware is included
in the R6500 Microcomputer System Hardware Manual
(Document Order Number 201). A descrptlon of the instruction capabilities of the R6502 CPU is contained in the R6500
Microcomputer System Programming Manual (Document
Order Number 202).
EDGE DETECT
PAo.PA7
(PAo-PEC)
INT LOQIC
(PA1~NeD)
(PA2-cNTR)
6502 CPU
PBOo-PB1
co
RS(AO)
efFio)
W(WR)
(00"""D7,
84 BYTES RAM
peG-pce
(AD, A1, A2, A3,
258 BYTES ROM
1.3 CUSTOMER OPTIONS
CONTROL REG
The R6500/43 microcomputer is available with the following
customer specified mask options.
•
•
•
•
Option
Option
Option
Option
EMS, R/W, INT)'
HBG-HB?
INPUT DATA
"EG
II
OUTPUT DATA
"EG
1 with or without a 256 byte ROM
2 Reset Vector at FFFC or OFFC
3 Port A with or without internal pull-up resistors
4 Port C with or without internal pull-up resistors
A()"A11, A15
DBo-OB7
......... SYNC
All options should be specified on an R6500/43 order form.
'MULTIFUNCTION PINS
The R6541 Q has no customer specified mask options. It has
the following characteristics.
Figure 2·1. Interface Diagram
1.50
...••
..••
r-
(3.S1 MM)
-. £-[
.
A'41
--I
1m
Niii
$VN..\<
RJW
CLKJ!i
cs
,
~(~:
I
1.628
RS(AOI
Hao
Ha1
(41.35 MM)
Ha.
H"
HB4
Ha.
H"
I
prs
I
HB'r
PCS
PC.
PC.
pC2
1_.1.
PC1
pc.
VA~~~
________~__
.020RE~
TV.
Figure 2-2. R6541 Q & R6500/43 Pin Out Designation (64 PIN QUIP)
64 PIN QUIP
Figure 2·3.· R6541Q & R6500/43 Dimensional Outline
3-257
Intelligent Peripheral Controllers
R6541Q and R6500/43
SECTION 2
R6500/41 INTERFACE REQUIREMENTS
devic.es. Figure 2;3 shows the mechanical dimensions cif the
devices. Secticm 5 describes the Host computer interface
protocol .and timing requirements.
'
This section describes the interface requirements for the Intelligent Peripheral Controller. Figure 2-1 is the Interface Diagram for the devices. Figure 2-2 shows the pin out configuration and Table 2-1 describes the function of each pin ofthe
Table 2·1. Pin Description
SIGN~l
. PIN NO.
NAME R6541Q & R6500/43
ClKIN
DESCRIPTION
11
Symmetrical square wave
100 KHz to 2 MHZ,TTl compatible input.
24
Output timing signal-This is
an internally synchronized
1 x clock output suitable for
'external memory or peripheraJ interfacing.
57
The reset input is used to initialize the device. Section 7
describes the process and
conditions of the RES procedure.
VCC
64
Power supply input (+5V)
VSS
32
Signal and power ground
(OV).
.
12
Chip select pin for host interface.
15
Register select input pin used
by the Host processor to indicate that information being
written into the IPC is a data
or command byte or to indicate that information being
read from the IPC is a status
or data byte.
RS (AO)
HBo-HB7
PAo-PA7
13
Host timing control signal for
data register write and read.
14
Host timing control signal for
data register write and read.
16-23
Data bus between Host and
IPC data input and output
registers.
8
A negative going edge on the
Non-Maskable Interrupt signal requests that a nonmaskable interrupt be generated with the CPU.
33-40
8 bit I/O port uSed for either
input or output. EaCh line
consists of an active transistor to Vss and an optional
passive pull-up to Vee. The
two lower bits PAO and PA1
also serve as edge detect inputs. PAZ is time shared with
the 16 bit Counter Input or
output pin, CNTR, and is
mode selected.
PIN NO_
SIGNAL NAME R6541Q& R6500/43
49-56
8 bit VO port uljed for either
input or output. Each line
conSists of an active transistor to Vss and an active pullup to Vee. This port.becoines
a tri-state data bus, 00-07,
in tlie Abbreviated or Multi~
plexedBus Mode. 00'07 are
muttiplexed with address lines
A4-A11. in the Multiplexed
Bus Mode. ',.
PCo-PCS
31-25
7 bit VO port
for either
input or output. Each line
consists of an active transistor to Vss and an optional
passive pull-up to Vee. The
pins PCO· to PC5 are multiplexed. with address and
control signals for use in
abbreviated and multiplex
modes. PC6 is multiplexed
with INT and is program selectable. In these two modes
PCo-pe5 have active pullups.
AO-A11, A15
7-1
63-58
Thirteen' address lines used
to address a complete 8K
external address space.
DBO-DB7
41-48
Eight bidirectional data bus
lines used to transmit data to
and from external memory.
SYNC
R/W
3-258
DESCRIPTION
PBO-PB7.
used
9
SYNC is a' positive going signal for the full clock cycle
whenever the CPU is performing an OP CODE fetch.
10
Controls the direction of data
transfer between the CPU
and the external 65K address space. The signal is
high when reading and low
when writing.
Intelligent· Peripheral Controllers
R6541 Qand R6500/43
SECTION 3
SYSTEM ARCHITECTURE
data are to be pushed onto the stack, the Stack Pointer is
placed on the Address Bus, data are written into the memory
location addressed by the Stack Pointer, and the Stack
POinter is decremented by 1, Each time data are read (or
"pulled") from the stack, the Stack Pointer is incremented by
1. The Stack Pointer is then placed on the Address Bus, and
data are read from the memory location addressed by the
This section provides a functional description of the IPC dev.ice. Functionally, the device consists of a CPU, RAM and
optional ROM memories, three parallel I/O ports(actually 23
I/O lines), counter/latch circuit, a mode control register, and
an interrupt flag/enable dual register circllit. Ablock diagram
of the system is shown in Figure 3-1.
NOTE
Pointer.
Throughout this document, unless specified otherwise,
all memory or register address locations are specified
in hexadecimal notation.
The stack is locatee! on zero page, i.e., memory locations
007F-0040. Normal usage calls for the initialization of the.
Stack Pointer at 007F.
~nd
3.1 CPU LOGIC
3.1.4 Arithmetic
The intemal CPU of the device is an enhanced R6502 configuration with an 8-bit Accumulator register, two 8-bit Index
Registers (X and Y);an 8-bit Stack Pointer register, an ALU,
a 16-bit Program Counter, and standard instruction register/
decode and internal timing control logic.
All arithmetic and logic operations take place in the ALU, including incrementing and decrementing internal registers
(except the Program Counter). The ALU cannot store data
for more than one cycle. If data are placed on the inputs to
the ALU at the beginning of a cycle, the result is always gated
into one of the storage registers or to external memory during
the next cycle..
3.1.1 Accumulator
The accumulator is a general purpose S-bit register that"
stores the results of most arithmetic and logic operations. In
addition, the accumul.ator usually contains one of the two
data words used in these operations.
Logic Unit (ALU)
Each bit of the ALU has two inputs. These inputs can be tied
to various internal buses or to a logic zero; the ALU then
generates the function (AND, OR, SUM, and so on) using
the data on the two inputs.
3;1.2 Index Registers
3.1.5
~
ClKIN
-+
INPUT
DATA
REGISTER
PORTC
:: :[
Co)
INTERUPT
ENABLE
REGISTER
16 BIT
COUNTERI
LATCH
INTERUPT
FLAG
REGISTER
MODE
CONTROL
REGISTER
III:
I-
Z
J
64 x 8
RAM
~ ~
~
256 x 8
ROM
r---
mil
11
_U
::::J
DATA
PORTA
PORT B
1:llt
PCo-PC6
(AO-A3, EMS, R/W, INT)'
I
U
INTERNAL DATA BUS
INT
~
en
~
,---J
P2 .-RES
JJ
o
~
SYNC . - -
--+
hl
Q.
U'I
CPU,4iOST
STATUS
REGISTER
RNi . NMI
r+
I
:J
6502 CPU
WITH BIT MANIPULATION
INSTRUCTION ADDED
I ~;",;;:
OUTPUT
DATA
REGISTER
"
I:\)
I
L------....JS1~
HBO-HB7~
N
".-u/HOST
CONTROL
lOGIC
PAD-PA7
PAD-POS EDGE)'
( PAl-NEG EDGE
PA2-CNTR
ft
PBG-PB7
( 00-07) ,
A4-Al1
'MULTIPLEXED SIGNALS
tt l"rI/O
DBII-DB7
AII-A11, A15
Sec
CD
:J
"'0
CD
~
-6"
::r
CD
iil
oo
:J
~
Figure 3-1.
R654tQ &
R6500/43 Block Diagram
2CD
U;
Intelligent Peripheral Controllers.
R6541 Q and;R6500/43
3.4 RANDOM ACCESS MEMORV (RAM).
3.1.8 Interrupt Logic
The RAM'consists of 64 bytes of readlwrite memory,with an
. assigned page zero address of 0040 through 007F.
Interrupt. logic controls ille sequencing of three interrupts:
RES, NMI, and IRO. IRO is gen~rated by anyone of four
conditions: Counter Overflow, Positive Edge Detect, Negative Edge Detect, and Input Data Register Full.
3.5 SVSTEM CLQCK
The device functions wilh an external clock. II is fully aaynchronou.s in. reference 10 Ihe Host computer liming. The device clock frequency equals the external clock frequency. It
is also made available for any external device synchronization al pin ¢2.
3.2 NEW INSTRUCTIONS
In addition to the standard 6502 instruction set, four instructions have been added to. the devices to simplify operations
that previously required a read/modify/write operation. In order for these instructions to be equally applicable to any I/O
ports, with or without mixed input and output functions, the
1/0 ports have been ,designed to read the contents of Ihe
specified port dala regisler during Ihe Read cycle of the readl
modifylwrite operation, rather than I/O pins as in normal readcycles. The added instructions and their format are explained
in the following subparagraphs:- Refer to Appendix A for the
Op Code mnemonic addressing matrix for theSe added
instructions.
3.6 MODE CONTROL REGISTER (MCR)
The MO,de ConlrolRegisler contains conlrol bits for the mullifunction I/O-ports and mode select bits for the Counter, the
6500 or 8080 Bus Select, and the Interrupl (INn. Its setting
determines the.basic configuration of Ihe device in anyapplicalion. Initializing this register is one of Ihe firsl actions Of
any software program. The Mode .Control Register bil assignment is shown in Figure 3-2.
3.2.1 Set Memory Bit (SMB m, Addr.)
The use of Counler A Mode Select is shown 'in Section 6.
This instruction sets to "1" one of the a-bit data field specified
by the zero page address (memory or 1/0 port). The first byte
Of the instruclion specifies Ihe 5MB operation and 1 of a bits
to be set. The second byte of the inslruction designates address (OQ-FF) of the byte or I/O port to be operated upon.
The use of the 6500/8080 Host Bus Select is shown in Section 6.
The use of Interrupt $eleot is shown in Section 4.5.
3.2.2 Reset Memory Bit (RMB in, Addr.)
The use of Bus Mode Select is shown in Sections 4A and
4.5.
This instruction is the same operation and format as 5MB
instruction except a reset to "0" of the bit results.
'
'.
3.2_3 BranCh on Bit Set Relative (BBS m, Addr,
DEST)
This. instruction tests one of a bits design~ted ,by a three bit
immediate field within the firSt byte of the inStruction. The
second byte is uSed to designate the address of the byte to
be tested wilhin the zero page address. range (memory or
1/0 ports). The third byte of Ih~ instruction is \Jsed to specify
the a bit relative address to which the instruction branches
if the bit tested is a "1". If the bit tested is not set, the next
sequential instruction is executed.
IICR
COUNTEll
SELECT MODE
3.2.4 Branch On Bit Reset Relative (BBR m,
Addr, DEST)
,.
BUS MODE'
SELECT
READ~ONL V-MEMORV
•.
NOT USED
This instruotion is the same operation and format as the BBS
instruction e~cept that a branch takes place if the bit tested
is a "(y',
3.3
"COR 0014
1
sELECT
BUS
o = B5CIOi88OO BUS '
1=Z8C!I8080BUS
~
o
INTERVAL l1MER
1 PULSE GENl;RATOR
o
EVENT COUNTER
1 PULSE ",lint
MEASUREMENT
INTS!LECT
0=_
1 = INT
(ROM)
The optional ROM consists of 256 bytes mask programmable
memory with an·addressspace from OPOC 10 OFFF. ROM
locations FFFAthrough FFFF are assigned for interrupt vectors. The Reset vector can be optionally al OFFC or FFFC.
o
D' PO.tt B ~'LL .NPUTS
1 PORT B ALL OUTPUTS
t . 0 ABBREVIATEg suS 1II0DE
1 . 1 MULTIPLEXEII'IUS'MODE
Q
Flgu~ 3-2. Mode Cont~ol Register Bit Allocations
The R6541 0 has no ROM and its reset veCtor is at FFFC.
3-261
II
Intelligent Peripheral Controllers
R6541 Q and R6500/43
3.7 INTERRUPT FLAG REGISTER (lFR)
AND INTERRUPT ENABLE
REGISTER (IER)
ADDR 0012
An IRQ interrupt request can be initiated by any or all of four
possible sources. These sources are all capable of being
enabled or disabled by the use of the appropriate interrupt
enabled bits in the Interrupt Enable Register (IER). Multiple
simultaneous interrupts will cause the IRQ interrupt request
to remain active until all interrupting conditions have been
serviced and cleared.
.
ADDR 0011
PAD POSITIVE
EDGE DETECT
INTERRUPT ENABLE
PAl NEGATIVE
EDGE DETECT
INTERRUPT ENABLE
The Interrupt Flag,Register contains the information that indicates which I/O' or counter needs attention. The contents
oUhe Interrupt Flag Register may be examined at any time
by reading at address: 0011. Edge .detect IFR· bits may l:)e
cleared by executing a RMB instruction at address location
0010. Tile RMB X, (0010) instruction reads FF, modifies bit
X to a "0"; and writes the modified value at address location
0011. In this way IFR bits set to a "1" after the read cycle of
a Read-Modify-Write instruction (such as RMB) are Protected
from being cleared.IFR bits 6 and 7 are indeterminate on a
Read.
INTERNAL INTERRUPT
RE9UEST. IRQ ENABLE
EXTERNAL INTERRUPTS REQUEST 1,
INT-l ENABLE
EXTERNAL INTERRUPT REQUEST 2,
INT-2 ENABLE
COUNTER UNDERFLOW
INTERRUPT ENABLE
Figure 3-3.
Table 3-1.
Interrupt Enable Signals
Control Signal
Description
IER 0
Positive Edge Detect, Interrupt Enablewhen this bit is true, a positive going signal on PAO will generate an IRQ and set
the corresponding flag bit.
IER 1
Negative Edge Detect Interrupt Enablewhen this bit is set to a "1" a negative
going signal on pA1 will generate an IRQ'
and set the corresponding flag bit.
IER2
3.7.1 External interrupts (I NT)
An external interruptlNT 10 the Host computer may be selected in two modes. (See Section 5 for information on the
Host/Device interface).
Input Data Register Full Interrupt Enable-settingthis bit to a "1" allows an
IRQ to be generated each time the Host
fills the lOR setting the IDFR bit.
IER3
Output Data Register Full Interrupt Enable-when this bit is an interrupt request
to the Host is generated each time the
ODRF flag is set to a "1". (See External
Interrupts, Paragraph 3.7.1). Reading the
ODR clears INT-1 and ODRF flags.
IER4
Input Data Register Empty Interrupt Enable-when this is set to a "1" an interrupt is generated to th,e Host each time
the lOR is read by the CPU. The interrupt
occurs when the I'oRF flag is cleared.
INT-2 is cleared when the Host reads the
status flag register. (See External Interrupts, Paragraph 3.7.1).
IERS
El:Ich iFR bjt has a corre~ponding bi,t in the Interrupt Enable
Regist~r whic;h can be set to a "1" by writing a "1" in the respective bit position at location 0012. IndividuallER bits may
be cleared by writing a "0" in the respective bit position, or
by RES. If set to,~,"1",;an IRQ will be generated when the
corresponding IFR bit becomes true. The Interrupt Flag Register and InterrupfEnable Register bit aSSignments are shown
in Figure 3-3 and the functions of each bit are explained in
Table 3-1.
interrupt Enable and Flat Registers
OUTPUT DATA REGISTER (ODR) FULL
When IER 3 of the Interrupt Enable Register is set to a "1",
the device will assert the INT (PC6) line each time it loads
the ODR. The ODRF flag of the Status Flag Register and the
IFR 3 of the IFR will be set to a "1" indicating the ODR is full:
TheODRF and IFR 3 flags are cleared and INT is negated
when the Host processor reads the ODR.
INPUT DATA REGISTER (lOR) EMPTY
When IER 4 of the Interrupt Enable Register is set to a "1",
the device will assert the INT (PC6) line each time it reads
the lOR. The IDRF flag olthe Host Status Flag Register will
be cleared and the IFR 4 flag of the IFR will be set to a "1"
indicating the lOR has just been read by the device. The IFR
4 flag is cleared and INT is negated when the Host processor
reads the Host Status Flag Register. RES clears the IDR and
sets the IFR4 flag to'indicate the register is empty.
Counter Interrupt Enable-if enabled; an
IRQ is generated whenever the Counter
overflows.
3-262
I ntelUgent Peripheral Controllers
R6541 Q and R6500!43
3.8 PROCESSOR STATUS REGISTER
zero. This bit is cleared to logic 0 when the resultant 8 bits
of a data movement or calculation operation are nat all zero.
The R6502 instruction set contains no instruction to specifically set or clear the Zero Bit. The Zero Bit is, however, affected by the following instructions; ADC, AND, ASL, BIT,
CMP, CPX, CPY, DEC, DEX, DEY, EOR, INC, INX, INY,
LDA, LOX,LOY, LSR, ORA, PLA, PLP, ROL, ROR, RTI,
SBC, TAX, TAY, TXA, TSX, and TYA.
The:8-bit Processor Status. Register, shown in Figure 3-4,
contains seven status flags. Some of these flags are controlled by the user program; others may be controlled both
by the user's program and t.he CPU. The R6502 instruction
set contains a number of conditional branch Jnstructions
which are designed to allow testing of these flags. Each of
the eight processor status flags is described in the following
sections.
3.8.3 Interrupt Disable Bit (I)
3.8.1 Carry Bit (e)
The Interrupt Disable Bii(l) is used to control the servicing
of an Interrupt request (IRQ). If the I Bit is reset to logic 0,
the IRQ signal will be serviced. If the bit is set to logic 1, the
IRQ sign~1 will b~ ignored. The CPU will set the Interrupt
Disable B~ logiC 1 if a RESET (RES) or Non-Maskable
Interrupt (NMI) signal is detected.
The Carry Bit (C) can be considered as the ninth bit of an
arithmetic operation. It is set to logic 1 if a carry from the
eighth bit has occurred or cleared to logic 0 if no carry occurred as the result of arithmetic operations.
The Carry Bit may be set or cleared under program control
by use of the Set Carry (SEC) or Clear Carry (CLC) instruc·
tion,respectively. Other operations which affect the Carry Bit
are AOC, ASL, CMP, CPX, CPY,LSR, PLP, ROL, ROR, RTI,
and SBC.
The I bit is cleared by the Clear Interrupt Mask Instruction
(CU) ~nd is set by the Set Interrupt Mask Instruction (SEI).
ThiS bit may also be set by the BRK Instruction. The Return
from Interrupt (RTI) and Pull Processor Status (PLP) instructions will also affect the I bit.
3.8.2 Zero Bit (Z)
The Zero Bit (Z) is set to logic 1 by the CPU during any data
movement or calculation which sets all B bits of the result to
7
6
4
5
3
o
2
CARRY (C) (1)
1 = Carry Set
o = Carry Clear
'------Zero (2) (1)
1 = Zero Result
0= Non-Zero Result
'------INTERRUPT DISABLE (I) (2)
1 = IRQ Interrupt DIsabled
IRQ Interrupt Enabled
o=
' - - - - - - - - - DECIMAL MODE (D) (1)
1
= Del:imal Mode
o = Binary Mode
BREAK COMMAND (B) (1)
1 = Breek Command
o = Non-Break Command
1--_ _ _ _ _ _ _ _ _ _ _ _
OVERFLOW (0) (1)
1 = Overflow Set
Overflow Clear
o=
N O T E S ' - - - - - - - - - - - - - - - N E G A T I V E (N) (1)
(1) Not initialized by RES
(2) Set to Logil: 1 by RES
Figure 3-4.
1 = Negative Value
0 = Positive Value
Processor Status Register
3-263
II
Intelligent Peripheral Controllers
R6541 Q andR6500/43
3.8.4 Decimal Mode Bit (D)
This indicator only has meaning when signed arithmetic (sign
and seven magnitude bits) is performed. When the ADC or
SBC instruction is performed, the Overflow Bit is set to logic
1 if the polarity of the sign bit (bit 7) is changed because the
result exceeds + 127 or -128; otherwise the bit is cleared
to logic 0. The V bit may also be cleared by the programmer
using a Clear Overflow (CLV) instruction.
The Decimal Mode Bit (D), is used to control the arithmetic
mode of the CPU. When this bit is set to logic 1, the adder
operates as a decimal adder. When th.is bit is cleared to logic
0, the adder operates as a straight binary adder. The adder
mode is controlled only by the programmer. The Set Decimal
Mode (SED) instruction will set the D bit; the Clear Decimal
Mode (CLD) instruction will clear it. The PLP and RTI instruc·
tions also effect the Decimal Mode Bit.
The OverflOW Bit may also be used with the BIT instruction.
The BIT instruction which may be used to sample interface
devices, allows the overflow flag to reflect the condition of bit
6 in the sampled field. During a BIT instruction the Overflow
Bit is set equal to the content of the bit 6 on the data tested
with BIT instrction. When used in this mode, the overflow has
nothing to do with signed arithmetic, but is just another sense
bit for the microprocessor. Instructions which affect the V flag
are ADC, BIT, CLV, PLP, RTI and SBC.
CAUTION
The Decimal Mode Bit will either set or clear in an unpredictable manner upon power application to the device. This bit must be initialized to the desired state by
the user program or erroneous results may occur.
3.8.5 Break Bit (B)
3.8.7 Negative Bit (N)
The Break Bit (B) is used to determine the conditi~hich
caused the IRQ service routine to be entered. If the IRQ service routine was entered because the CPU executed a BRK
command, the Break Bit will be set to logic 1. If the IRQ rou·
tine was entered as the result of an IRQ signal being generated, the B bit will be cleared to logic 0. There are no instructions which can set or clear this bit.
The Negative Bit (N) is used to indicate that the sign bit (bit
7), in the resulting value of a data movement or data arithmetic operation, is set to logic 1. If the sign bit is set to logic
1, the resulting value of the data movement or arithmetic
operation is negative; if the sign bit is cleared, the result of
the data movement or arithmetic operation is positive. There
are no instructions that set or clear the Negative Bit Since the
Negative Bit represents only the status of a result. The instructions that effect the state of the Negative Bit are: ADC,
AND, ASL, BIT, CMP, CPX, CPY, DEC, DEX, DEY, EOR,
INC, INX, INY, LDA, LDX, LDY, LSR, ORA, PLA, PLP, ROL,
ROR, RTI, SBC, TAX, TAY, TSX, TXA, and TYA.
3.8.6 Overflow Bit
(V)
The Overflow Bit (V) is used to indicate that the result of a
signed, binary addition, or subtraction, operation is a value
that cannot be contained in seven bits (-128 "" n '" 127).
3-264
Intelligent Peripheral Controllers
R8541 Qand R8500/43
SECTION 4
PARALLEL INPUT/OUTPUT PORTS
(>2.0V) input will cause a logic 1 to be read. An FlES Signal
forces all I/O port registers to logic 1 thus Initially treating all
I/O lines as Inputs.
INPUT/OUTPUT PORTS
The IPC device provides three ports (PA, PB, and PC). The
15 lines of PA and PC are completely bidirectional, that is,
there is no line grouping or port association restrictions.
The eight lines of Port B may be programmed as all inputs
or all outputs. Port PC, however, may be multiplexed under
program control with seven other signals. Six of these signals
form an address and control bus for extended addressing.
The seventh signal is multiplexed with an external interrupt
output, INT. All eight Port B lines are tri-state to permit their
use as a data bus during extended addressing modes.
Port B may be all inputs or all outputs. All inputs is selected
by setting bits MCR6 and MCR7 of the Mode Control Reg·
Ister to a "0".
The status of the Input lines can be interrogated at any time
by reading the I/O port addresses. Note that this will return
the actual status of the Input lines,not the data written into
the I/O port registers.
Internal pull-up resistors (FET's with an impedance range of
3K,.,; Rpu .. 12K ohm) may be provided on ports PA and/or
PC. The R6541Q does not have these resistors.
Read/ModlfylWrlte Instructions can be used to modify the operatlon' of PA, PB, pc, and also PF, & PG of an emulated
R6500/42. During the Read cycle of a ReadlModifylWrile
instruction the Port 110 register is read. For all other read instructions the port input lines are read. ReadlModifylWrite instructions are: ASL, BBS, BBR, DEC, INC, LSR, RMB, ROL, ROR,
and 5MB.
The direction of the I/O lines are controlled by S-bit port registers located in page zero. This arrangement provides quick
programming access using simple two-byte zero page address instructions. There are no direction registers associated with the I/O ports, which simplifies VO handling. The
VO addresses are shown in Table 4-1. If a part is being
used to emulate a R6500/42 the ports must be provided in
external circuitry and addressed through locations' 00040006:
4.2 OUTPUTS
Outputs for Ports A thru C, and emulated Ports E thru G of
the R6500l42, are controlled by writing the desired I/O line
output states into the corresponding I/O port register bit positions. A logic 1 will force a high (>2.4V) output while a logic
o will force a low «0.4V) output. Port B also requires that
MCR6 be set to a "1" and MCR7 be set to a "0".
Tabl. 4-1. 110 Port Addre....
PORT
ADDRESS
A
B
C
E
F
G
0000
0001
0002
0004
0005
0006
}R6500/42 only
4.3 PORT A (PA) .
Port A can be programmed via the Mode Control Register
(MCR) as a standard parallel 8-bit, bit independent, I/O port,
or a counter I/O line. Table 4-2 tabulates the control and
usage of Port A.
In addition to their normal I/O functions, PAO can detect positive going edges, and PA1 can detect negative going edges.
An edge ~ransition on these pirlS will set a corresponding
status bit in the IFR and generate an interrupt request if the
respective Interrupt Enable Bit is set. The maximum rate at
which an edge can be detected is one-half the _2 clock rate.
Edge detection timing is shown in Section E.5.
4.1 INPUTS
Inputs for Ports A and C, and also Ports F and G if emulating
the R6500/42, are enabled by loading logic 1 Into all I/O port
register bit positions that are to correspond to I/O input lines.
A low «O.SV) input signal will cause a logiC 0 to be read
when a read instruction is issued to the port register. A high
Tabl. 4-2. Port A Control • U.ag.
PA()'PAll/0
PA21/0
MCRD
MCR1
SIGNAL
PA2COUNTER
=D
=D
MCRD
MCR1
SIGNAL
=1
=0
SIGNAL
PA3-PA71/0
MCRD = X
MCR1 = 1
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
NAMS
TYPE
NAME
TYPE
NAME
TYPE
PAO(I)
PAl (2)
I/O
I/O
PA2
1/0
CNTR
OUTPUT
CNTR
INPUT (3)
PA3-PA7
I/O
(1) POSITIVE EDGE DETECT
(2) NEGATIVE EDGE DETECT (3) HARDWARE BUFFER FLOAT
3-265
II
Intelligent Peripheral Controllers
R6541Q and R6500/43
4.4 PORT B (PB)
4.5 PORT C (PC)
Port B can be programmed as an 1/0 Port, an 8-bit tri-state
data bus, or as a multiplexed bus. Mode selection for Port
B is made by the Mode Control Register (MCR). The Port B
output drivers can be selected as tri-state output drivers by
setting bit 7 of the MCR to 0 (zero) and bit 6 of the MCR to
1. An all inputs condition is created by setting both MCR6
and MCR7 to 0 (zero). Table 4-3 shows the necessary settings for the MCR to achieve the various modes for Port B.
When Port B is selected to operate in the Abbreviated Mode
PBO-PB7 serves as data register bits 00-07. When Port B
is selected to operate in the Multiplexed Mode data bits DO
through 07 are time multiplexed with address bits A4 through
A 11, respectively. Refer to the Memory Maps (Appendix B)
for Abbreviated and Multiplexed memory assignments. See
Appendix E.3 through E.S for Port B timing.
Port C can be programmed as an 1/0 port and in conjunction
with Port B, as an abbreviated bus, or as a multiplexed bus.
When used in the abbreviated or multiplexed bus modes,
PCO-PCS function as AO-A3, RIW, and EMS, respectively,
as shown in Table 4-4. EMS (External Memory Select) is
asserted (low) whenever the internal processor accesses
memory area between 0080 and OFFF. (See Memory Map,
Appendix C). The leading edge of EMS may be used to
strobe the eight address lines multiplexed on Port B in the
Multiplexed Bus Mode. See Appendix E.3 through E.S for
Port C timing.
Table 4-3.
Port B Control & Usage
I/O MODES
R6541Q &
R6500/43
ABBREVIATED
MODE
MULTIPLEXED MODE
MeR7 = 1
MeR6 = 1
MeR7 = 0
MeR6 = 0
MeR7 = 0
MeR6 = 1
MeR7 = 1
MeR6 = 0
SIGNAL
SIGNAL
SIGNAL
PHASE 1
PHASE 2
SIGNAL
SIGNAL
PIN #
NAME
TYPE
(1)
NAME
TYPE
(2)
NAME
TYPE
(3)
NAME
TYPE (2)
NAME
TYPE (3)
49
50
51
52
53
54
55
56
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
DO
01
02
03
04
05
06
07
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A4
A5
A6
A7
A8
A9
Al0
All
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
DO
01
02
03
04
05
06
07
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(1) TRI-STATE BUFFER IS IN HIGH IMPEDANCE MODE (2) TRI-STATE BUFFER IS IN ACTIVE MODE
(3) TRI-STATE BUFFER IS IN ACTIVE MODE ONLY DURING THE PHASE 2 PORTION OF A WRITE CYCLE
Table 4-4.
Port C Control & Usage
ABBREVIATED
MODE
I/O MODE
R6541Q &
R6500/43
MeR7
MeR6
=0
=x
MeR7
MeR6
NAME
31
30
29
28
27
26
25
PCO
PCl
PC2
PC3
PC4
PC5
PC6'
=1
=0
MeR7
MeR6
SIGNAL
SIGNAL
PIN #
MULTIPLEXED
MODE
TYPE
(1)
NAME
AD
Al
A2
A3
EMS
I/O
I/O
I/O
I/O
I/O
I/O
R/W
iNT'
110
(1) RESISTIVE PULL-UP, ACTIVE BUFFER PULL-DOWN
(2) ACTIVE BUFFER PULL-UP AND PULL-DOWN
1
1
SIGNAL
TYPE
(2)
NAME
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
• PC6 if MCR5 = 0; INT if MCR5
3-266
=
=
AO
Al
A2
A3
EMS
R/W
INT"
=
1
TYPE
(2)
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
IntelligentPeripheralControUers
R6541Q and R6500/43
4.7 BUS MODES
A special attribute of Port B and Port C is their capability to
be configured via the Mode Control Register (see Section
3.6) into four different modes.
In the Multiplexed Bus Mode, the operation is similar to the
Abbreviated Mode except that a full4K of external addresses
are provided. Port C provides the lower addresses and control signals. Port B multiplexes functions. During the first half
of the cycle it contains the remaining necessary 8 address
bits for 4K; during the second half of the cycle it contains a
bidirectional data bus. The address bits appearing on Port
B must be latched. into an external holding register. The leading edge of EMS, which indicates that the bus function is
active, may be used for this purpose.
In the Port B All Inputs and Port B All Outputs modes the
separate address and data bus are used. The difference lies
in the direction of Port B-all inputs or all outputs. The receiving ports perform the normal I/O function. A 15 is usually
used as a chip select for external memory.
In the Abbreviated Bus Mode, the address and data lines can
be used as above to emulate the R6500/41. Port B and Port
C are automatically transformed into an abbreviated address
bus and control signals (Port C) and a bidirectional data bus
(Port B). 16 Peripheral addresses can be selected. In general
usage, these 16 addresses would be distributed to several
external I/O devices such as R6522 and R6520, etc., each
of which may contain more than one unique address.
Figures 4-1a thru 4-1.d show the PossiblecpnfiQur.ations of
the four bus modes. Appendix C1 shows a memory map of
the port as a function of the Bus Mode and further shows
which addresses are active or inactive on each of the three
possible buses.
3-267
3
Intelligent Peripheral Controllers
R6541Q and'R6500/43
PORTB
ALL OUTPUTS
i!lUSMODE
ABBREVIATED
BUS MODE
CLKIN --+
8 BITS
~
RES -+
8,BITS
AO(RS)--+
RIW(RD} __
.
PORTB
7 BITS
PORTC
v
.A
+-
8 BITS
~
INT#
DATA BUS PORT B)
~
R!W(RD)4
AG-A3(PORT C)
Vss
HBGHB7
~SYNC
i+-NMi
R/W(PORT C)
Vee--li
112
,2
--+
8 BITS
-..;..
INT#
16
PERIPHERAL
ADDRESSES
##
-
EMS (PORT C)*
Cs-lo
cs-+
-+
Vss -+
A.
v
E (WR)---.
V ee
PORTA
8 BITS
AO(RS)-+
v
E(WR)~
HBGtlB7
PORTA
'A
,
CLK~
IN
RES ____
~ Sy'NC
I+-
NMI
",AG-A11
12 BITS
A15 v
R/W
DB1-DB7 ,..
4K
EXTERNAL
MEMORY
@FXXX
12 BITS
A15 ..
~
DB1-DB7
8 BITS
8 BITS
r
Figure 4-18.
"
Figure 4-1c.
PORTB
ALL INPUTS
BUS MODE
MULTIPLEXED
BUS MODE
CLKIN --+
8 BITS
RES --+
.
8 BITS
AO(RS)~
PORTA
PORT B
7 BITS ) PORT C
v
E(WR)4
8 BITS
PORT A
v
"
~-;"t"'"'~
LATCH
CS---.
,.. 112
Vee~
......
EMS'
(PORT C)
(PORT C)
.2
HBG-(8 BITt
HB7...:!....
v
INT#..-
r-+SYNC
I+-NMi
AG-A3 PORT C)
r:-.
~NMI
SYNC
~AG-A11 ..
12 BITS
A15 r
RIW
jlB1-DB7
12 BITS
A15
R/w
4K
EXTERNAL
MEMORY
@FXXX
,'"
ADB1-DB7..
8 BITS
8 BITS
v
Figure 4-1b.
Figure 4-1d.
# OPTIONAL pes
##NOT AVAILABLE WITH BOOTSTRAP ROM OPTION
• EMS VALID @ 0100 THRU OFFF
3-268
UPT04K
EXTERNAL
MEMORY
AND/OR
PERIPHERALS
##
@OXXX
A4-A11
RJW
Vss
Vss .......
A
AO(RS)---.
RJW(RD)--+
E(WR)~
CS .......
Vee .......
HBG-( 8 BITS
HB7 ~
-v
INT# . . -
A
CLKIN--+
RES--+
A
RiW(RD)-+
4K
EXTERNAL
MEMORY
@FXXX
RiW
.
4K
EXTERNAL
MEMORY
@FXXX
,/
Intelligent Peripheral' Controllers
R6541 Q arid 'R6S00/43
SECTIONS
,HOST INTERFACE BUS
Two way data transfers are performed between the IPC and
the Host microprocessor by means of the Output Data Register and the Input Data Register. The Host can also write a
command to the lOR and read from the Host Status Flag
Register. Figure 5-1 shows the Host addressing matrix. A
hardware interrupt procedure a~d a software polling procedure is avail,able to control data traffic between the CPU and
Host.
RS (A.)
READ
1
HOST
STATUS FLAG
COMMAND
INPUT
0
DATA REG
OUTPUT
DATA REG
INPUT
Figure 5-1.
host write data exchange. The device can write to the Fl flag
at anytime.
"
The ODRF (Output Data Register Full) flag is set each time
the device writes to the Output Data Register. The setting of
the ODRF sets the device Interrupt Status Register IFRS flag.
An Output Interrupt (INT) may be generated undE!r program
cO,ntrol by setting IER3 in the in, terru, pt e,' nable" re,,9i5,',t,e,' r',T, he,
ODRF flag is reset only by a h&rdware reset or by the host
performing a read on the output data register. TheODRF flag
is reset following the conclusion of any host 0UtpUt data register read. The resetting of the ODRF causes the reset of the
IFR3 flag and thus the rE!set oltheextemai interrupt (INT).
WRITE
The IDRF (Input Data Register Full) flag is set following the
conclusion of any host write data exchange. The setting of
the IDRF causes IFR2 of the device status registerto be set.
An internal interrupt may be generated under program control by setting IER2 in the Inrerrupt Enable Register. The setting of IDRF also causes IFR4 to be reset. The IDRF resets
during device read of the input data register. IFR2, sets and
IFR4 resets following the reset of IDRF. IFR4 may,generate
an external output interrupt(INT, input buff,erempty), under
program control by setting IER4'inthe interrupt'enable
register.
Host Addressing Matrix
5.1 DATA REGISTERS
The device has an 8-bit Input Data Register (lOR) and, an
8-bit Output Data Register (ODR). The IDR serves as a temporary storage for commands and data from the Host to the
device. When transferring data from the Host to the device,
the following conditions are in effect:
The Host Status Flag, Register is cleared, PY t~e RES input.
• CS is asserted
• RS (AO) indicates command input or data input.
• The contents of the host data bus (HBO-HB7) are copied
into the lOR when the appropriate Host bus write signals
are asserted.
. HOST STATUS FLAG REGISTER
INPUT DATA
REGISTER
FULL FLAG
The ODR serves as a temporary storage for data from the
device to the Host. When the Host is reading da.ta from the
device, the following conditions are in effect:
OUTPUT DATA
REGISTER
FULL FLAG
• CS is asserted
• RS (AO) input selects ODR or HSFR
• The contents of ODR or the Flag Register arE! placed on
the host data bus (HBO-HB7) when, the appropriate Host
read signals are asserted.
PURPO~E
GENERAL
FLAGS STATUS REGISTER
5.2 HOST STATUS FLAG REGISTER
Figure 5-2.
A Host Status Flag Register facilitates a software protocol
that permits independent and uninterrupted floW Of dala
asynchronously between the host computer and the device.
COPIES R$ON
WRITE FROM HOST
Host Status Flag Register Bit Allocation,
5.3 HOST COMPUTER INTERFACE
,The deviCe will work with a variety of Host Computers. The
'HOST interface consists of a chip s~lect, one address line,
2 control lines and an 8 ,\:lit three state data bus. Internal logic
of the device, controlled by MCR4, configures, the addrE!ss
and two control lines to either a 8500 or 8080 operational
methodology. The interface is completely asynchronous and,
will work with a Host Computer up to a 5 MHz bus transfer
rate. The device clock input frequency need riot be the same
as the Host's. A mode control register is set. to match the
interface to that of the Host device as follows:
The Host Status Flag Register contains 8 flag bits that'can
be read at anytime by either the Host or the device. See Figure 5-2. General purpose flags F2 through F6 are serviced
by the device, in either read or write modes ahd, monitored
by the Host (Read Only).
Flag Fl can be read at anytime by either the host or the, device. The Fl flag copies th,e AO (RS) input sigriai during any
3-259'
3
Intelligent Peripheral Controllers
R6541 Q andR6500/43
MCR4 = 0
,
When MCR4 is set to a logic zero, the IPC is
configured to operate on a 6502/6800 type host
bus. In this mode, the E input is connected to
the host transfer strobe (VMA or /d2 for 6800,
fJ2 for 6500) and the R/W input is connected to
the ho~ microprocessor RJW output line. Figure 5-3 and Table 5-1, together, specify the relevant timing for read and write cycles on this
type of host bus.
. MCR4· =',1
When MCR4 is set to a logic one, the IPC is
configured for operation on an 8080/Z80. type
bus: In this mode, the AD input is used as a
read strobe and the WR input is connected to
the write strobe of the host microprocessor bus.
Figure 5-4 and Table 5-2 show the relevant tim~
ing characteristics for this mode,o/.operation.
Table S~2. H~t Interface
Timing CharacteristiCS BSEL = 1 (8080)
,TableS-1. HQat Interface
Timing Cflll,aeterlstics BSEL = 0 (6500)
,
CHARACTERISTICS
1 AN~2MHZ "
SYMBOL
MIN
CHARACTERISTICS
1AND2MH
MAX
SYMBOL
MIN
MAX
CS! R/W, RS Setup Time
Ie.
10
-
CS, AO Setup Time
Ie.
10
-
'AC99~S
to.
-
90'
Data'Access Time on Read
to.
-
90'
10
-
Data Hold Time
10
-
-
'.
Time
Data Hold Time
tOHR
'C9ntrol Hold Time
tHe
10
-
Control Hold Time
Write Oaia Setup Time
twDS
75
-
Write Data Setup Time
Write Data Hold Time'
t,,~w ',.
10
-
Write Data Hold Time
tWR
75
-
Write Strobe Width
WI'i!e ~roke, Y,Vidt~.
",
,.,
tDHR
"
READ
WRITE
Figure S·3. Timing Diagram-Host Interface (MCR4 = 0) (6500 Version)
WRrr.
-=
TCS~
RS
'
~
~ 1~THC
WPffi
... -
Tes _
1+~&,/!I///~
THC
Figure 5-4.
~~
I
!,.;:THC
,
TWA
-------
RD
H...HB7
10
75
tOHW
10
tWR
75
'NOTE:
90 ns when loading = 130 pf + 1 TTL LOAD and
7~ ns when Iqading, = 90 pI + 1 TTL LOAD.
'NOTE:
90 nswhen 10adi[1g' = 130 pI + 1 TTL LOAD and
75 ns, when loading =; 90 pI +1 TTL LOAD.
Ci
tHe
tWDS
TWDs]l1-•
~
Timing Diagram-Host interface (MCR4 = 1) (8080 Version)
3-270
~
Intelligent Peripheral Controllers
R6541Qand R6500/43
SECTION 6
COUNTER/TIMERS
The device contains a 16-bit counter and a 16-bit latch associated with it. The counter can be independently programmed to operate in one of four modes:
The Counter operates in any of four modes. These modes
are selected by the Counter Mode Control bits in the Control
Register.
Counter
•
•
•
•
Pulse width measurement
Pulse Generation
Interval Timer
Event Counter
Operating modes of the Counter are controlled by the Mode
Control Register. All counting begins at the initialization value
and decrements. When modes are selected requiring a
counter input/output line, PA2is selected for Counter I/O.
MCRI
(bit 1)
MCI'IO
(bit 0)
0
0
1
1
0
1
0
1
Mode
Interval Timer
Pulse Generation
Event Counter
Pulse Width Measurement
The Interval Timer, Pulse Generation, and Pulse Width Measurement Modes Clre ¢2 clock counter modes. The Event
Counter Mode counts the occurrences of an extemal event
on the CNTR line (PA2).
The Counter is set to the Interval Timer Mode (00) when a
RES signal is generated.
6.1 COUNTER
6.1_1 Interval Timer Mode
The Counter conSists of a 16-bit counter and a 16-bit latch
organized as follows: Lower Counter (LC), Upper Counter
(UC), Lower Latch (LL), and Upper Latch (UL). The counter
contains the count of either ~2 clock pulses or external
events, depending on the counter mode selected. The contents of the Counter may be read any time by executing a
read at location 0018 for the Upper Counter and at location
001 A or location 0019 for the Lower Counter. A read at location 0019 also clears the Counter Underflow Flag (IFR5).
In the Interval Timer mode the Counter is initialized to the
Latch value by either of two conditions:
1. When the Counter is decremented from 0000, the next
Counter value is the Latch value (not FFFF).
2. When a write operation is.performed to the Load Upper
Latch and Transfer Latch to Counter address 0019, the
Counter is loaded with the Latch value. Note that the
contents of the Accumulator are loaded into the Upper
Latch before the Latch value is transferred to the
Counter.
The 16-bit latch contains the counter initialization value, and
can be loaded at any time by executing a write to the Upper
Latch at location 0018 and the Lower Latch at location 001A.
In either case, the contents of the accumulator are copied
into the applicable latch register.
The Counter value is decremented by one count at the 132
clock rate. The 16-bit Counter can hold from 1 to 65535
counts. The Counter Timer capacity is therefore 1MS to 65.535
ms at the 1 MHz ¢2 clock rate or a.5MS to 32.767 ms at the
2 MHz ¢2 clock rate. Time intervals greater than the maximum Counter value can be easily measured by counting IRQ
interrupt requests in the counter IRQ interrupt routine.
The Counter can be started at any time by writing to address
0019. The contents of the accumulator will be copied into the
Upper Latch before the contents of the 16·bit latch are transferred to the Counter. The counter is set to the latch value
whenever the Counter underflows, When the Counter decrements from 0000 the next counter value will be the latch
value, not FFFF, and the Counter Underflow Flag (IFR 5) will
be set to "1 ". This bit may be cleared by reading the Lower
Counter at location 0019, by writing to address location 0019,
or by RES.
When the Cbunter decrements from 0000, the Counter Underflow (IFR5) is set to logic 1.lf the Counter Interrupt Enable
Bit (IER5) is also set, an IRQ interrupt request will be generated. The Counter Underflow bit in the Interrupt Flag Register can be examined in the IRQ interrupt routine to determine that the IRQ was generated by the Counter Underflow.
3-271
Intelligent Peripheral Controllers
R6541Q and R6500/43
6.1.4 Pulse Width Measurement Mode
While the timer is operating in the Interval Timer Mode, PA2
operates as a PA I/O.
This mode allows the accurate measurement of a low pulse
duration on the PA2 line. The Counter decrements by one
count at the ¢2 clock rate as long as the PA2 line is held in
the low state. The Counter is stopped when PA2 is in the
high state.
A timing diagram of the Interval Timer Mode is shown in Fig·
ure6·1.
The Counter underflow flag will be set only when the count
in the timer reaches zero. Upon reaching zero the timer will
be loaded with the latch value and continue counting down
as long as the PA2 pin is held low. After the counter is
stopped by a high level on PA2, the count will hold as long
as PA2 remains high. Any further low levels on PA2 will again
cause the counter to count down from its present value. The
state of the PA2 line can be determined by testing the state
of PA2.
C~~R ~~ ~~ ~~_C_O~~N_TE_~~IU~~:~:r~~~o_W~I(~UL~'L~4~.'~IL
__
__
__
COUNTER INTERRUPT ENABLED
I
'BCOUNTER
ET ANY UNDERFLOWI
TIME .EFOREr--~_______
I
I
COUNTER UNDERFLOW FLAG
Figure 6·1.
Interval Timer Timing Diagram
----------------~/~---------
6.1.2 Pulse Generation Mode
In the Pulse Generation mode, the PA2 line operates as a
Counter Output. The line toggles from low to high or from
high to low whenever a Counter Underflow occurs, or a write
is performed to address 0019.
COUNT
The normal output waveform is a symmetrical square·wave.
The PA2 output is initialized high when entering the mode
and transitions low when writing to 0019.
Asymmetric waveforms can be generated if the value of the
latch is changed after each counter underflow.
A one-shot waveform can be generated by changing from
Pulse Generation to Interval Timer mode after only one occurrence of the output toggle condition.
6.1.3 Event Counter Mode
In this mode PA2 is used as an Event Input line, and the
Counter will decrement with each rising edge detected on
this line. The maximum rate at which this edge can be defected is one-half the ~2 clock rate.
The Counter can count up to 65,535 occurrences before underflowing. As in the other modes, the Counter Underflow bit
(IER5) is set to logic 1 if the underflow occurs.
Figure 6.2 is a timing diagram of the Event Counter Mode.
Figure 6·2.
Event Counter Mode
3-272
In~elligent~.rlpheral ~9ontroUers
R6541 Q and R6500/43
S,ECTIQN .7
POWER ON/INITIALIZATION' CONSIDERATIONS
7.1 POWER ON TIMING
7.3· RESET (RES) CONDITIONS
After application of VCC power to the device, RES must be
held low for at least eight stable~2 clock cycles after Vee
reaches operating range.
When RES is dr.lven from low to high the device is put in a
reset staie causing the registers and I/O ports to be set as
shown in Table 7-1.
\_.-
Table 7·1. ... ........... 01110 ........ _
Figure 7-1 illustrates the power turn-on waveforms. External
clock stabilization time is typically 20ms.
7
REGISTERS
Processor Status
Mode Control (MCR)
Int. Enable (IER)
Int. Flag (IFR)
Host Status Flag
Input Data
Output Data
II
r-
PORTS
PA Latch
PB Latch
PC Latch
e
RD ________________________
6
5
4
:i
- - - - -
2
1
0
-
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
All RAM and other CPU registers will initialize in a random, nonrepeatable data pattern.
.
Figure 7-1. Power TurnoOn Timing Oetall
7.4 INITIALIZATION
Any initialization process for the device should include a RES
as indicated in the preceding paragraphs. After stabilization
of the external clock (if a power on situation) an initi.a1ization
routine should be executed·to perform (as a minimum) the
.
following functions:
7.2 POWER-ON RESET
The occurrence of RES going from low to high will cause the
device to set the Interrupt Mask Bit-bit 2 of the Processor
Status Register-and initiate a reset vector fetch at address
FFFC and FFFD to begin user program execution. All of the
I/O ports will be initialized to the high (logic 1) state. All bits
of the Control Register will be cleared causing the Interval
Timer counter mode to be selected· and causing all interrupt
enabled bits to be resat.
1.
2.
3.
4.
5.
The Stack Pointer should be set
Clear or Set Decimal Mode
Set or Clear Carry Flag .'
Set up Mode Controls and Counter as required
Clear Interrupts.
A typical initialization routine could be as follows:
LOX
TXS
CLD
SEC
CLI
3-273
Load· stack pointer starting address into
X Register
Transfer X Register value to Stack Pointer
Clear Decimal Mode
Set Carry Flag
Set-up Mode Control,
Counter, special function
registers and Clear RAM as required
CIE~ar Interrupts
0
Intelligent Peripheral Controllers
R6541Qand R6500/43
APPENDIX A
EXPANDED R6502 INSTRUCTION SET
The four instructions notated with a ' are added instructions
for the IPC devices which are not part of the standard 6502
instruction ·set.
.
This appendix contains a summary of the R6502 instruction
set. For detailed information, consult the R6502 Microcomputer System Programming Manual, Document 29650 N30.
A,1 INSTRUCTION SET IN ALPHABETIC
SEQUENCE
MNEMONIC
ADC
AND
ASL
'BBR
'B,BS
BCC
BCS
BEQ
BIT
BMi
BNE
BPL
BRK
BVC
BVS
INSTRUCTION
Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)
MNEMONIC
LDA
LDX
LDY
LSR
Branch on Bit Reset Relative
Branch on Bit Set Relative
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on OverflOW Clear
Branch on Overflow Set
CLC
CLD
CLI
CLV
CMP
CPX
CPY
Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable
Clear Overflow Flag
Compare Memory and
Compare Memory an(l
Compare Memory and
DEC
DEX
DEY
Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One
EOR
"Exclusive-Or" Memory with
Accumulator
INC
INX
INY
Increment Memory by One
Increment Index X by On'e
Increment Index Y by One
JMP
JSR
Jump to New Location
Jump to New Location Saving Return
Address
NOP
No Operation
ORA
"OR" Memory with Accumulator
PHA
PHP
PLA
PLP
Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack
'RMB
ROL
Reset Memory Bit
Rotate One Bit Left (Memory or
Accumulator)
Rotate One Bit Right (Memory or
Accumulator)
Retum from Interrupt
Retum from Subroutine
Bit
ROR
Accumulator
Index X
Index Y
RTI
RTS
SBC
SEC
SED
SEI
'SMB
STA
STX
STY
TAX
TAY
TSX
TXA
TXS
TYA
3-274
INSTRUCTION
Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or
Accumulator)
Subtract Memory from Accumulator with
Borrow
Set Carry Flag
Set DeCimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Accumulator to Index X
Accumulator to Index Y
Stack POinter to Index X
Index X to Accumulator
Index X to Stack Register
Index Y to Accumulator
l:I
A.2 R650011-11 INSTAUCTIONSET SUMMARY TABLE
IIMMEDlATEI~LUTEjZE"O_~,,-Ej ACCUM.I'MPUED
0' I n I
ADC
AND
ASL
~
A+M+C-->A (4){1f
AM---A
(1l
C-
rr::=:::IJ <-jj
BBR{#(S-nJ Branch on M.=0
(5)
BBS(#{O-7)] Branch on M&o:o I
(5)
BCC
BCS
BEQ
BIT
BMI
BNE
BPl
BRK
Bve
BVS
Branch on C~'0
Branch on C""" 1
Branch on Z=l
A M
Branch on N== 1
Branch on Z=1iI
Branch on N =0
Break
Branch on V==0'
Branch on V= 1
ClC
CLD
eLi
O-C
0-0
0-1
CLV
CMP
CPX
CPY
O-.v
A-tA
X-M
Y-M
DEC
OEX
M-l_M
INC
INX
M+l ...... M
X+I-X
y+t-.... Y
lSR
NOP
RTS
SEC
seD
SEt
.A I 2 I'
2C)4)3) 241312
:~I
!;l !~l ~~ 16~1 ~I ~~ I;~
••
;: I~ I~o
00 I 7 11
M---ooA (I)
M-X (1)
M-Y (1)
O-~-C
All
,
N
N
N
N
D61612IDEI7('
09
2
2 00
•
3
051312
I 5 I 2 I as 4 2 BD
4
99 1 4
31 BE
-4
3
3
I .1
E~ 121' 1.,16121" 151.1:
5E
.
4
2
.0
4
Z
Z
Z C
N
0
3119 I 4 13
4B
N ••••• Z
28
~
Int
2E 6
6E 6
26
68
2
6A +
2H
1
(Restored)
2
2 ED 4
l--T
N
(Restored)
N V
3B121'
2 1
Fa
78
2
1
TSX
g....,.X
TXA
X-A
1
BA12
8A 2 •
V_A
SA
98
4
85
4
-B.
~f+ I TT 1·
8.161219.1612195) 4121901513) <,15)3
A-Y
x-s
B
94) 41 2
84
BC '.
Z C
Z C
N
(5)
BD
BE
I '
E.I 6121 F.I 5 I 2 I F51 41 2) fD I 4) 3 I fSI 4,1 3
3
ESIT
071 .71 27 I 37 1471 57 I 67177
4. I I I I I I I I I ~~I :I~g~1 ~I ~
58
ES
~w
z
N
IN
B61 4 I 2 I
o
ac
08
68
Rtrn
-RIm Sub
A-M-c---.A (-I)
, ...... C
1--0
N
N
N
N
B4
4A I 2
XI
en
6G 15 13
All '61.2 I ••
AS
A6
No Operation'
a.
Z C
Z C
Z C
Z
Z
Z
Z
Z
Z
Z
N
~ I~ I~
46
o '
N
~1~~1~1~1591413
4.'1012151) 512155
F6
A4
I»
:3
, 0
491212140
EE
A9
AZ
..
'
CA
BB
4C 3
28 6
AD 4
AE 4
AC 4
4E 6
, Z
o '
CE
Jump to New loc
Jump Sub
~
.....
o
(II
M,Ms'
(2)
(2.
m
Z C
Z
Z C
30
DO
I ...... Mb
A......M
X...... tv!
V-M
A--X
TXS
1
N V
N
N
9.
a.
f.
5MB(#(S-7)]
STA
STX
STY
TAX
TAY
TVA
(7 6 5 4 3 2"-t 8
7INV.SDllC
~: I:
3D
70 4
'E 7
315235
'6
(2)
(2)
(2)
AVM--A
A--Ms 5-1-5
P-Ms -8-1-S
ptA
8+1 ___ 8 Ms--t-A
PlP
8+1 __ 5 Ms-P
RMB{#IJI-7)) O-M. (5)
sec
.06
71 1_512 >175 I 4
(2)
(2)
(2)
ORA
PHA
PHP
:~
ATI
BIT ADDRESSING (OP BY BIT #)
Cl) 61,21 OJ 1-512 I OS) 4 I 2 I DO »4 I 3 109 I 4 13
AV~A
lOY
I'ABS,Y IRELATIVEIINDIRECTlz.•AGE,Y
E022EC
crlTD
C.022CC
EOR
JSR
3
(IND;cX) I (IND),Y IZ.•AGE,xl ABS,X
B.
2)
69121216,0'1413165
29222D4:J25
eE: 6
I
n I # 10. I n I .1 OP I n 1# 10'1 n I • 10. I n I # 10. I n I. 10. I n I • 10. I n 1# 10. I n I # I 0' I n I # I 0.1 nl # I •
18 I 2 11
X-I_X
Y-I-V
LOA
LOX
# I 0' I
DB
58
B8
OEY
INY
JMP
* I 0. I nJ
PROCESSOR STATUS
CODes
ADDRESSINQ MODES
-
OPERATION
MNEMONIC
Q)
AA
A8
7
..,-, -:...
Z (3)
,
7
rrT7
'
ii
:F7 1
N
2
2
Z
::r
Z
Z
Dl
N
N
N '
.z
N '
,_ Z
NOTES
LEGEND
1. Add 1 to N if page boundary Is crossed
2. Add 1 to N If branch occurs 10 same page
Add 2 10 N Wt.-anch occurs 10 different page
3. CMy not = Borrow
4. If In decimal mode Z ftag is invalid
accumulator must be checked on zero result.
5. Effects a-bit data field of the specified zero: page address.
M.
X
Y
A
M
Memory 8ii 8
= Add
= SUbtract
A
=
V
M,
Milo
M,
Index X
Index Y
Accumulator .'
= Memoryp....ffoctive IIddress
Memory per stBck pOinter
Selecter zero page memOry bit
= Memory Bit 7
=
II
'of
m
I>
i
ca·CD
a
And
Or
Exclusive Or
Number of cycles
Number of Byles
CD
(")
o
a
o
i...
en
R6541 Q and R6500/43
Intelligent Peripheral Controllers
A.3 INSTRUCTION CODe MATRIX
7
8
9
A
ORA
ZP
2 3
ASL
ZP
RMBO
ZP
ORA
IMM
2 5
2 5
PHP
Implied
1 3
ASL
Accum
1 2
BPL
ORA
Relative (IND), Y
2 2"'
2 5'
ORA
ZP,X
2 4
ASL
ZP,X
2 6
RMBl
ZP
2 5
CLC
Implied
1 2
ORA
ABS, Y
3 4'
AND
ZP
2 3
ROL
ZP
2 5
RMB2
ZP
2 5
PLP
Implied
1 4
AND
IMM
2 2
8M1
AND
Relative (lND, y)
2 2"
2 5'
AND
ZP,X
2 4
ROL
Zp,X
2 6
RMB3
ZP
SEC
Implied
1 2
AND
ABS, Y
3 4'
RTI
EOR
Implied (IND, X)
1 6
2 6
EOR
ZP
LSR
ZP
RMB4
2 3
2 5
ZP
2 5
PHA
Implied
1 3
EOR
IMM
2 2
BVC
EOR
Relative (IN D), Y
2 2"
2 5'
EOR
ZP,X
2 4
LSR
ZP,X
2 6
RMB5
ZP
2 5
CLI
Implied
1 2
EOR
ABS,Y
3 4'
ACC
ZP
2 3
ROR
ZP
2 5
RMB6
PLA
Implied
1 4
ADC
IMM
2 2
ADC
ZP, X
2 4
ROR
ZP,X
2 6
RMB7
ZP
2 5
SEI
Implied
1 2
ADC
ABS, Y
3 4'
STA
ZP
2 3
STX
ZP
2 3
5MBO
ZP
2 5
DEY
Implied
1 2
3
2
o
JSR
AND
3 6
4
5
4
BIT
2 . Absolute (IND, X)
3
ZP
2 3
2 6
RTS
ADC
Implied (IND,X)
1 6
2 6
'.
BVS
ADC
Relative (IND, y)
2 2"
2 5'
A
STY
C
D
E
5
2
ROL
Accum
1 2
JMP
ABS
1 2
3 3
TYA
Implied
1 2
STA
ABS,Y
3 5
TXS
Implied
1 2
LDY
ZP
2 3
LOA
ZP
2 3
LDX
ZP
2 3
5MB2
ZP
2 5
TAY
Implied
1 2
LDA
IMM
2 2
TAX
Implied
1 2
LDY
ZP,X
2 4
LDA
ZP, X
2 4
LDX
ZP, Y
2 4
5MB3
ZP
2 5
CLV
Implied
1 2
LDA
ABS, Y
3 4'
TSX
Implied
1 2
CPY
ZP
2 3
'CMP
ZP
2 3
DEC
ZP
2 5
5MB4
ZP
2 5
INY
Implied
1 2
CMP
IMM
2 2
DEX
Implied
1 2
CMP
ZP,X
2 4
DEC
ZP,X
2 6
5MB5
ZP
2 5
CLD
Implied
1 2
CMP
ABS,Y
3 4'
SBC
ZP
2 3
INC
ZP
5MB6
ZP
2 5
INX
Implied
1 2
sac
2 2
5MB7
ZP
2 5
SED
Implied
1 2
ABS, Y
3 4'
7
8
9
LDA
Relative (IND), Y
2 2"
2 5'
CPV
IMM
2 2
CMP
(IND,X)
2 6
BNE
CMP
Relative (IND), Y
2 2"' .2 5'
CPX
IMM
2 2
sac
CPX
ZP
2 3
(IND, X)
2 6
sac
BEQ
Relative (IND);Y
2 2"
2 5'
o
ZP,X
2 4
3
2
4
2 5
INC
Zp,X
2 6
o
o
BRK
Implied
1 7
IMM
F
BBRO
ZP
AND
ABS
3 4
EOR
ABS
3 4
3 5
ADC
ABS
3 4
BBRl
ZP
3 5"
BBR2
ZP
3 6
3 5"
LSR
ABS
3 6
ROR
ABS
3 6'
ZP
3 5"
BBR4
ZP
3 5"
BBR6
ZP
BBR7
ZP
STA
ABS
STX
ABS
BBSO '
3 4
3 4
3 5"
CPY
ABS
3 4
BBSl
ZP
3 5
3 5"
CPX
ABS
3 4
sac
SBC
ABS
3 4
A
B
C
o
ZP
BBS3
ZP
BBS4
ZP
BBSS
ZP
A
B
C
o
3 5"
INC
ABS
BBSS
ZP
3 6
3 5"
E
9
3 5"
3 5"
sac
8
3 5"
DEC
ABS
INC
ABS, X ABS,X
3 4'
3 7
7
BBS2
3 6
CMP
DEC
ABS, X ABS,X
4'
.3
7
3
NOP
Implied
1 2
ZP
STA
ABS,X
CMP
ABS
3 4
6
3 5"
STY
ABS
LDY
LOA
LDX
ABS, X ABS,X ABS,Y
3 4'
3 4'
3 4'
4
3/5··
3 4
LDX
ABS
3 4
3
BBR5
ZP
3 5"
1 2
LDA
ABS
3 4
2
BBR3
TXA
Implied
LDY
ABS
3 4
o
3 5"
ROL
ABS
ADC
ROR
ABS, X ABS,X
3 7
3 4'
5MBl
ZP
2 5
LOX
IMM
2 2
JMp·
Indirect
ROR
Accum
1 2
STX
ZP, Y
2 4
LOA
(IND;X)
2 6
E
ASL
ABS
3 6
EOR
LSR
ABS, X ABS, X
3 4'
3 7
STA
Zp,X
2 4
LDY
IMM
2 2
BIT
ABS
3 4
LSR
Accum
ZP,X
2 4
STY
o
ORA
ABS
3 4
AND
ROL
ABS, X ABS, X
3 4'
3 7
BCC
STA
Relative (IND, y)
2 2"
2 6
sac
F
ZP
C
ORA
ASL
ABS, X ABS,X
3 7
3 4'
ZP
2 3
acs
B
2 5
2 2
STA
(IND,X)
2 6
8
9
B
6
BRK
ORA
Implied (IND,X)
1 7
2 6
BBS7
ZP
E
F
3 5"
F
'Add 1 to N if page boundary is crossed.
"Add 1 to N if branch occurs to same page;
add 2 to N if branch occurs to different page.
-OP Code
-Addressing Mode
-Instruction Bytes; Machine Cycles
3-276
R6541 Q and R6500/43
Intelligent Peripheral Controllers
APPENDIX B
KEY REGISTER SUMMARY
CPU Registers
,.
I
PCH
I7
A
I7
I7
Y
I7
PCl
Processor Status Register
•I
7
•I
•I
•I
•I
•
la I" I' Iz 10 I
I7
SP
IHlvl
ACCUMULATOR
A
INDEX REGISTeR Y
Y
l H1 v1 1 a1"1'1 z1 cJ
L:
INDEX REGISTER X
PROGRAM COUNTER
PC
STACK POINTER
CARRY (C) (')
, • Corry Sot
0= c8nyCl..r
.... (:Q(')
1 = Zero ....ult
o = Non-Zero ......It
S
INTERRUPT DISABLE (I) (2)
PROCESSOR STATUS
REG
P
1 = IRQ Interrupt DiUlJled
o = IRQ Interrupt Enabled
II
DECIMAL MDDE(D} (')
1 = Decimal Mode
o = Binary Mode
BREAK COMMAND (B) (1)
Mode Control Register
1
= BfHk Command
Q =
Non-Break Command
OVERFLOW (0) (1)
MCR
ADDROO14
1 = Overflow Set
0= OVerftow Clear
I
NEGATIVE (N) (1)
NOTES
(1) Not InitialIZed ~ RES
1 "" Negative Valul
o = Po.Illve Value
(2) Set to Logic 1 by RES
COIJNn"
SELECTMOOE
,L,
o
NOT USED
o
BUS SELECT
0 INTERVAL TIMER
1 PULSE GENERATOR
o
EVENT COUNTER
1 PULSE WIDTH MEASUREMENT
Interrupt Enable and Flag Registers
o = 8500/8800 BUS
1 = Z8O/8OIO BUS
lR'f SEL£CT
'E"
Q=Pe&
1 =lNi"
PORT B ~a.L INPuTS·
PORT 8 ALL OUTPUTS
ABSAEV1ATED BUS MODE
ItIULTlPl..EXED BOS MODE
Host Status Flag Register
PAD POSmYE
EDGE DETECT
HSFR
INTERRUPT ENABLE
ADDROO1E
PAl NEGATIVE
EDUEDETECT
INTERRUPT ENABLE
INTERNAL INTERRUPT
REQUEST;1IiQ ENAaLE
EXTERNAL INTERRUPTS REQUEST "
INT-' ENABLE
INPUT DATA REGISTER
FULL FLAG
EXTERNAL ~flRUPT REQuPT 2,
INT-2 'ENABLE
COUNTER UNDERFLOW
INTERRUPT ENABLE
OUTPUT DATA REGISTER
FUUFLAG
COPIE$ RS ON
WAITE 'FROM HOST
Host Addressing Matrix
RS(Aol
READ
1
HOST
STATUS FLAG
COMMAND
INPUT
0
DATA REG
OUTPUT
DATA-REG
INPUT
WRIT!;
GENERAL PURPOSE
FLAGS STATUS REGISTER
3-2n
::D
APPENDIX C
C.1 MEMORY MAPS AND ADDRESS AND PIN ASSIGNMENTS
Q)
...o~
I»
:J
Q.
::D
Q)
PORT B ALL INPUTS
6
PORT B ALL OUTPUTS
FFFE
'IRO VECTOR
FFFC
RES VECTOR
FFFA
ABBREVIATED BUS MODE
FFFE
FFFA
NMIVECTOR
4K USER
PROGRAM
MULTIPLEXEO BUS MODE
IROVECTOR
FFFE
IROVECTOR
FFFE
RES VECTOR
FFFC:
RES VECTOR
FFFC (OP RESeT VECTOR)
NMI VECTOR
FFFA
NMIVECTOR
FFFA
4K USER
PROGRAM
4KUSER
PR6GRAM,
FOOO
FOOO
FOOOI
,
"
IROVeCTOR
NMI VECTOR
FFF!
IROVECTOR
I
FFF' ;
RES VECTOR
1
FFF,
NMIVECTOR
I
UI
,
R65416R&5OOI43
(W/O BOOT STRAP ROM)
R6S00f43
(WfBOOT STRAP ROM)
,
~
4K
USER
PROGRAM
4K
USER PROGRAM
FOOOI
FOOO
INTERNAL REGISTERS
READ
RESERVED
RESERVED
I
NOT AVAILABLE
I
~
RESERVED
,
TOFFF
TOFFFI
o
o
~
PERIPHERAL
ADDRESSES
(16)
en
I
::;
w
RESERVED
RESET VECTOR
OFFB
BOOT STRAP
ROM (256)
1/0 &, REGISTERS
0000I
,
INTERNAL
RAM (64)
INTERNAL
RAM {54}
0040
004> I
RESERVED
VO & REGISTERS
I
I
I
I
I
I
HB~~atus Register
HBS Status Register
Input Host Bus Buffer
Output Host Bus Buffer
Lower Counter A
Lower Counter A#
Upper Counter A
Lower Latch A
Upper Latch A" #
Upper Latch A
--
---
-Mode Control Reg.
Mode COntrol Reg.
Interrupt Enable Reg.
Inter~pt Flag Reg.
Interrupt Enable Reg.
Read FF
Clr Interrupt Flag Reg.
ADDRESS
001F
OOtE
001D
001C
001B
001A
0019
0018
0017
0016
0015
0014
0013
oot2
0011
OOto
ooor
NOT AVAILABLE
RESER\iED
,
001
001F
0000
I
I
008> I
007F
0100
007F
va & REGISTERS
I
I
EXTERNAL
MEMORY
4056-128
OFOO
RESERVED
,
001F
I
NOT
AVAILABLE
0040>
001F
0000
OFFC
INTERNAL RAM (64)
RESERVED
VO & REGISTERS
0000
I
1010>,
EXTERNAL MEMORY
4096-128
007F
0040
001F
~
w
INTERNAL RAM (64)
INTERNAL RAM (64)
0040
<"
>
)
10100
oo7F
007F
:J
I
,
OFFI
1000
WRITE
VO & REGISTERS
I
0001 I
110 PORT C
0003
0002
VO PORTB
VO PORTA
0000
>-AND START COUNTER
If CLEAR FLAG
I!.
CO
CD
:J
-
,"0
CD
I~
CD
'"'2!.
f;l
-'"'
::::J
2-
CD
'"'
U)
Intelligent Peripheral Controllers
R6541 Q and R6500/43
C.2 1/0 AND INTERNAL REGISTER ADDRESSES
ADDRESS
READ
WRITE
--
001F
IE
1D
lC
--
Host Status F:ag Register
Host Status Flag Register
--
-Input Data Register (lOR)
Output Data Register (ODR)
--
--
lB
lA
19
18
Lower Counter
Lower Counter & Clear Flag (IFRS)
Upper Counter
Lower Latch
Upper Latch/Transfer Latch to Counter & Clear Flag (IFR5)
Upper Latch
----
----
17
16
IS
14
Mode Control Register
13
12
11
10
Interrupt Enable Register
Interrupt Flag Register
Read "FF"
Mode Control Register
--
-Interrupt Enable Register
-Clear Int Flag Bit
OF
OE
aD
OC
--
DB
OA
09
08
-----
---
----
--
----
----
07
06
05
04
--
--
--
----
--
--
--
03
02
01
00
PortC
Port B
PortA
PortC
Port B
Port A
C.3 MULTIPLE FUNCTION PIN ASSIGNMENTS
PIN NUMBER
R6500/43
R6541Q
1/0
FUNCTION
ABBREVIATED PORT
FUNCTION
MULTIPLEXED PORT
FUNCTION
31
30
29
28
PCO
PCl
PC2
PC3
AD
AI
A2
A3
AD
A1
A2
A3
27
26
25
PC4
PC5
PC6/1NT
R/W
R/W
EMS
PC6/1NT
EMS
PC6/1NT
49
50
51
52
PBO
PB1
PB2
PB3
DO
D1
D2
D3
A4/DO
A5/D1
A6/D2
A7/D3
53
54
55
56
PB4
PB5
PB6
PB7
D4
D5
06
D7
A8fD4
A9/D5
A1D/D6
A11ID7
3-279
II
Intelligent Peripheral Controllers
R6541 Q and R6500/43
APPENDIX D
ELECTRICAL SPECIFICATIONS
Maximum Ratings
RATING
SYMBOL
VALUE
UNIT
Svpply VoHage
Vee
Input Vonage
V'n
T
-0.3 to +7.0
-0.3 to +7.0
Vdc
Vdc
Operating Temperature Range,
Commercial
Storage Temperature Range
o to
+70
'C
'C
-65 to +150
TSt$!
This device contains circuitry to protect the inputs against damage due to high static voltages, however, it is advised that normal precautions
be taken to avoid application of any voltage higher than maximum rated voltages to this circuit.
D,C. Characteriatics (Vee
= 5V ±
5% V••
= 0)
CHARACTERISTIC
Power Dissipation (Outputs High)
SYMBOL
Po
Commercial O'C to + 70'C
MIN
TYP
MAX
-
500
-
-
Vee
Vdc
+0.8
Vdc
+10.0
!£Adc
-1.6
mAde
mW
Input High Voltage (Normal Operating Levels)
V'H
+2.0
Input Low Voltage (Normal Operating Levels)
VIL
-0.3
Input Leakage Current
I'N
-10.0
V'n
= 0 to 5.25 Vdc
Input Low Current
(V"
UNITS
-1.0
I"
= 0.4 Vdc)
Output High Voltage
(Vee = min, I",•• = -100 !£Adc)
Output High Voltage
(Vee = min)
VOH
+2.4
-
Vee
Vdc
VC;:MOS
Vee -30%
-
Vee
Vdc
-
-
+0.4
Vdc
Output Low Voltage
(Vee = min, I"". = 1.6 mAde)
VOL
Output High Current (Sourcing)
(VOH = 2.4 Vdc)
10H
-100
-
-
!£Adc
Output Low Current (Sinking)
(VOL = 0.4 Vdc)
10L
1.6
-
-
mAde
Darlington Current Drive, PE'
(VOH = 1.5Vde)
10H
-1.0
-
-
mAde
Output Low Current, PE'
(VOL = 0.4 Vde)
10L
1.6
-
-
mAde
C in
-
-
10
pF
COUT
-
-
10
pF
RL
3.0
6.0
11.5
KG
Input Capacitance'
(V'n - 0, TA = 25'C, f
PA, PB, PC, PF', PG'
Output Capacitance
(V'n - 0, TA = 25'C, f
I/O Port Resistance
PAO-PA7, PCP-PC6
PFO-PF7, PGO-PG7
=
1.0 MHz)
=
1.0 MHz)
NOTE: Negative sign indicates outward current flow, positive indicates inward flow. Vee = 5V ± 5% 'R6500/42 only
3-280
R6541Q and R6500/43
Intelligent Peripheral Controllers
APPENDIX E
TIMING REQUIREMENTS AND CHARACTERISTICS
E.1 GENERAL NOTES
1. Vee
5V ±5·o,
o·c
:S
TA
E.2 CLOCK TIMING
:S
70·C
1 MHz
2. A valid Vee - RES sequence is required before proper
operation Is achieved.
Symbol
Parameter
2 MHz
Min
Max
Min
Max
Teye
Cycle Time
1000
10,.s
500
101'8
3. All timing reference levels are 0.8V and 2.0V, unless otherwise specified.
TPWfO
ClKIN Input Clock
Pulse Width
475
-
240
-
4. All time units are nanoseconds, unless otherwise specified.
TpW02
Output Clock
Pulse Width at
Minimum T eye
Tpw\kl
Tpw;o
TpwlIO
TpwlIO
T R, TF
Output Clock
Rise, Fall Time
-
25
TIR, TIF
Input Clock Rise,
Fall TIme
-
10
5. All capacitive loading is 130 pF maximum, except as noted
below:
PA, PB
- 50 pF maximum
PB, PC (1/0 Modes Only)
- 50 pF maximum
PB, PC (ABB and Mux Mode) - 130 pF maximum
+25
Tcvc
ClKIN~ 1.5V
TIR
=fr--=
_
'---------
.. ---
Tpw.o
-
3-281
- TF
+20
-
15
10
II
R6541 Q and R6500/43
Intelligent Peripheral Controllers
E.3 ABBREVIATED MODE TIMING-PB AND PC
(MeR 5 = 1, MeR 6 = 0, MeR 7 = 1)
1 MHz
2 MHz
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
T PCRS
(PC5) R/w Selup Time
-
225
-
140
T pCAS
(PCO-PC3) Address Selup Time
-
225
-
140
TpBSU
(PB) Data Setup Time
50
T PBHR
(PB) Data Read Hold Time
10
T pBHW
(PB) Data Write Hold Time
30
-
30
-
T pBDD
(PB) Data Output Delay
-
175
-
150
T pCHA
(PCO-PC3) Address Hold Time
30
30
-
T pCHA
(PC5) R/W Hold Time
30
-
30
-
T pCHV
(PC4) EMS Hold Time
10
-
(PC4) EMS Stabilization Time
30
-
10
T pcvp
T Esu
Eii.1§ Setup Time
-
350
NOTE 1: Values assume PCD-PC5 have
E.3~ 1
t~
-
-
-
35
10
30
-
-
210
same capacitive load.
Abbreviated Mode Timing Diagram
WRITE
READ
4 - - TPCHR
Riw
(pes)
I_-'---~
TPCRS
_ _ _ TPCHV
TPCVP
TPBDD
TP8SU
PBO-PB7
TPBHR
3-2B2
TPB"lW
Intelligent Peripheral· Controllers
R6541Q and R6500/43
E.4 MULTIPLEXED MODE TIMING-PB AND PC
(MeR 5
= 1, MeR 6 = 1, MeR 7 = 1)
2 MHz
1 MHz
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
T PCRS
(PC5) R/W Setup Time
-
225
-
140
T pCAS
(PCO-PC3) Address Setup Time
225
-
140
T PBAS
(PB) Address Setup Time
-
225
-
140
T pBSU
(PS) Data Setup Time
50
35
-
T PBHR
(PS) Data Read Hold Time
10
-
10
-
Tl>BHw
(PS) Data Write Hold Time
30
-
30
-
T pBDO
(PS) Data Output Delay
-
175
-
150
T PCHA
(PCO-PC3) Address Hold Time
30
-
30
T PSHA
(PS) Address Hold Time
T pCHR
(PC5) R/W Hold Time
0
100
30
-
-
0
80
30
-
-
(PC4) EMS Hold Time
10
-
10
(PC4) Address to EMS Delay Time
30
-
30
Tpcvp
(PC4) EMS Stabilization Time
30
-
30
-
Tesu
EMS Setup Time
-
350
-
210
T PCHV
T pCVD
,,,
NOTE 1: Values assume
peo-pes
have the same capacitive load.
E.4.1 Multiplex Mode Timing Diagram
READ
WRITE
r-------------~
~TPCHR
RW
(pes)
1 _ - - -__ 1 TPCRS
_TPCHV
EMS
(PC4)
~--tESU------TPCVP
TPCHA _______
PCO-PC3
TPCAS
--..
_ _ TPBHA
PBO-PB7
I
TPBAS
TPBHR
.....--TPC"D
3-283
TPBHW
Intelligent Peripheral· Controllers
R6541 Q and R6500/43
E.5 1/0, EDGE DETECT AND COUNTER TIMING
1 MHz
PARAMETER
SYMBOL
MIN
2 MHz
MAX
MIN
MAX
Internal Write to Peripheral Data Valid
T pDW(1J
TCMoslH
TpODW
-
PA, PC TTL
PA, PC CMOS
PB
-
500
1000
-
lis
-
500
1000
150
-
200
50
-
-
75
10
-
"Tcyc
-
Peripheral Data Setup Time
TpDSU
Tposu
200
50
PA,PC
PB
-'-
Peripherar Data Hold Time
T pHR
T","
TEPW
75
10
PA,PC
PB
-
T~yc
PAQ-PA1Edge Deisel Pulse Width
-
Counter
Tcpw
Teof1l
PA2 Input purse Width
PA2 Output Delay
~
Tcyc
-
-".
Teye
500.·.
500
....,."..
NOTE 1: MaXImum Load CapaCl'D
I~---~wv-----·I
V1H
V1L
_tAVax-j
Q (DATA OUT)
-~~~~~~~~;_~~~~r-----_;~~~;_------VOH
PREVIOUS DATA VALID
=1
READ CYCLE TIMING 2 .
ADDRESS
INPUTS
-
DATA VALID
VOL
tAVEL
ADDRESS VALID
,
tELEH
V1H
V1L
E(CHIP ENABLE)
-
teLQV
I--tELQX ---l
HIZ
Q(DATAOUT)
Vee SUPPLY Icc
CURRENT Isa
DATA VALID
_____-=-=_ ~u_Jf
G (CHIP SELECT)
(SHOWN ACTIVE LOW)
lfr-
tQLQV-
-
teHciz \ HIZ
VOH
VOL
ItattOz 1_
tpo
TYPICAL CHARACTERISTICS
SUPPLY CURRENT VS AMBIENT TEMPERATURE
SUPPLY CURRENT VS SUPPLY VOLTAGE
0
70r--r--,---.-,---.---,.--.
l
40 -55'
E
3 0"::::'
0
10
-
°eo
"
~ 30~~--~~~~~~~,
~.
~'"
J
1.
"I''''Vc~+125'
Slandby TYPical
,; 5,OV
30
o
ao
eo
90
-+
120
,,",~I
ACCESS TIME
VS
AMBIENT TEMPERATURE
700
1 SO'
1A-Ambient Temperature-OC
Vee-Volts
SOO
11
~400
300
,;125'C
200
100
-55'
0 ~-
~
~~p ..........Vee = 5,OV
,......-
-60.3.0
0"
3.0
60
2 TIL LOAOS
CL = 100 pF
90" 120" 150'
TA-Ambient Temperature-OC
4-5 .
II
32K (4K x 8) Static ROM
R2332A and R2332B
PACKAGE DIMENSIONS
24-PIN PLASTIC DIP
24-PIN CERAMIC DIP
0070 0 .120
0:020 0.070
0.530
1i9i"i~t--~~O.'~5O~---j~FIi9IFi1f-L-
.
'---- ~
0.090
0.050
0:020
,
. '~'14r
r . 1~t~O'700~
,-~
,--- 0.450---1
~f::::
- -0.150
r
.
.~
M~
0.015
0.008
0:040
0.125
4-6
1~·160
-u- 0.023
0.032 REF
0.015
o:OsO
ii.6oO
R2364A
Memory Products
'1'
R2364A
64K (8K x 8) STATIC R()M
Rockwell
DESCRIPTION
The R2364A2, R2364A25 and R2364A3 are 65,536-bitstatic
Read-Only Memories (ROMs), organized as 8,192 eigh\-bit ,bytes,
that offer m8J!:imum access times of 200, 250 and 300 nanoseconds, resPectively. These ROMs are in industry-standard
24-pin, dual in-line packages, 'and ate available in ceramic or
low-co,st plastic;, These fully-static 64K-bit ROMs are compatible
with aU eight-bitN-channel microproceS$Ors, including the R6500
family of microprocessors.
.
QO
AO
A1
A2
A3
A4
AS
AS
A7
All three R2364A ROMs operate totally asynchronously, and
require no cloCk input. These devices provide tr;i-state output
·buffeni for memory expansion: ·The R2364A ROMs offer TTL
inp.lrt and output levels with a minimum noise immunity of 0.4
volts.
The mask-programmable chip enable input (EtE) may be programmed to function as a chip select witho.ut power down
standby mode or as a chip enable with power down standby
mode. The active level of the enable input is also programmable.
III
II:
~
IL
:;)
ID
S
~
0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
FEATURES
• 8,192 x 8 organization
,
.• Access time: 200 ns, 250 ns, ancl300 ns (max.)
A8 A9 A10 A11 A12
• Low power dissipation: 125 mWactive, 37.5 mW standby
R2364A Block Diagram
• Drives two TTL loads and 100 pI
• Single +5V ± 10"io power$Upply
• Totally static operation, nO Input clock required
• Completely TTL compatible
• Mask-programmable chip enaple
• Tri-stale output$, fOr mem!)rY expansion
A7
AS
AS
A4
A3
A2
A1
AO
QO
Q1
Q2
ORDERI~G INFORMATION
Pan Number: R2364A-- - - • --
[Package:
.C = Ceramic
'p = Plastic
re~perature Range:
No letter = DOC to 'I- 700c
E = -4OOC to +85°C
Power Down Standby Mode:
, S = Yes
No tetter .. No
GND
L-----,.,...Access Time (Max):
Note: Submit ROM codes using the'
. 2';' 200 ns'
RoCkwell ROM Code Order Form, '25 = 250 ns
Order No. 2137.
vee
A8
A9
A12
E'€·
A10
A11
Qi
Q6
Q5
Q4
Q3
·Mask-programl!ililil, option
3 = 300 ns
R2364A Pin Configuratl0l'!
No_
, ,DOcument No. 29000063
4-7
Data Sheet Order
063
Rev_ 3, March 1984
II
64K (8K x 8) Static ROM
R2364A
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Supply Voltage
Value
Vcc
-0.5 to +7.0
Vdc
Input Voltage
Y'N
-0.5 to +7.0
Vdc
Output Voltage
Vour
-0.5 to +7.0
Temperature Under Bias
Commercial
Industrial
TA
Storage Tern perature
TSTG
Power Dissipation
P
Vdc
°C
-10 to +80
-50 to +95
-6510 +150
°C
1.0
W
DC CHARACTERISTICS
= S.OV ± 10%, T A = OOG to 70oG(unless otherwise
Vcc
Symbol
-NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to thEl devic:e., This is
a stress rating only and. functional operation of the device at
these or any other conditions above; those incj(cated in. the
operational sections of this specification is hot implied. Exposure to absolute maximum rating conditions for extended periods
.'
may affect device reliability.
Unit
Parameter
specified)
Units
Vcc
V
V cc = 4.SV, 10H ,,; -400 /LA
V
V cc
10L= 3.3 mA
2.0
Vcc
.'
= 4.SV,
Input High Voltage
VIL
Input Low Voltage
-0.5
0.8
V
10
/LA
Vcc
= S.5V,
OV '" V
±10
'. /LA'
Output High Voltage
VOL
Output Low Voltage
V ,H
Typ
Test Conditions
Max
2.4
VOH
Min
0.4
'll
Input Load Current
ILO
Output Leakage Current
.
V
'n '" S.SV
Vcc ,,; S.SV, Chip Deselected,
Vour = +O.4V to V cc
= 5.5V
Icc
Power Supply Current, Active
25
55
rnA
IS8
Power Supply Current, Standily'
7.5
16
rnA
C,
Input Capacitance 2
7
pF
V cc = 5.0V, chip deselected, pin
under lest at OV, T A = 25°C
Co
Oulput Capacitance2
10
pF
f = 1 MHz
Vcc
Notes:
1. Applies only to chip enable with power down standby mode.
2. This parameter is periodically sampled and is not 100% tested.
AC CHARACTERISTICS
vcc =
S.OV ± 10%, T A = OOG to 70°C (unless otherwise specified)
R2364A2
Symbol
Parameter
Min.
Max.
R2364A25
Min.
Max.
R2364A3
Min.
Max.
Unit
tAVAX
Address Valid to Address Don't Care
200
250
300
tELEH
Chip Enable Low to Chip Enable High2
200
250
300
t AVQV
Address Valid to OUlput Valid (tACel (Access)
200
250
300
ns
teLQV
Chip Enable Low to Output Valid (Access)2
200
250
300
ns
t AVQX
Address Valid to Output (t OH) Invalid
10
10
10
teLQX
Chip Enable Low to Output (tco) Invalid
10
10
10
teHQZ
Chip Enable High to Output High Z (t OF )
10
t pu
Chip Selection to Power Up Time2
t pD
Chip Deselection to Power Down Time 2
t AveL
Address Valid to Chip Enable Low
a
tGLOX
Chip Select Low to Output Invalid'
10
90'
10
90'
10
90'
ns
tGHQZ
Chip Select High to Output High Z
10
70'
10
70'
10
70'
ns
70'
10
70'
lOa'
ns
ns
ns
70'
a
a
0
10
ns
lOa'
a
ns
lOa'
a
ns
ns
Notes:
1. Test Conditions:
Output Load: 2 TIL Loads and 100 pF: Input Transition Time: 20 ns: Timing Reference Levels: Input: 1.5V, Output: 0.8V, 2.0V.
2. Mask-programmed for chip enable with power down standby mode.
3. Mask-programmed for chip enable without power down standby mode.
4. Add 20 ns for extended temperature devices (-40°C to +85°C).
4-8
ns
,
64K (8K x 8) Static ROM
R2364A
TIMING" DIAGRAMS
READ CYCLE TIMING 1
ADDRESS
INPIITS
IE HELD LOW)
V1H
tA_vAX
___
~"~.
IAVQv
READ CYCLE TIMING 2
PRE\IIOUS DATA VALID"
=I
ADDRESS
INPIITS
~--"'--- V1L
bJADDRE:S VAUD
-1A_-j
(DATA OIlT)"
Q
---------.l
~"_'_"_ _ _ _ _" _"__
""
.
------D-AT-A-VA-U-P----VOH
~ ------...:;.;.;.;.;~~~---"--
VOL
I-tAVEL
~DDRESS
VALID
IeLEH
-
tGLQX
--
--:--I
IeLQV
-!eLQx--1"
~HOZIIeHQZ " -
TYPICAL CHARACTERISTICS
SUPPLY CURRENT VS AMBIENT TEMPERATURE
SUPPLY CURRENT V$SUPPLY VOLTAGE
7Or--r-r--r-r--r-r--,
70
60
50
0
- .
-55'
-
::.....,..
20
SI
0
0
-60
-30'
~
~al
1 .f' __+'~5'
incuw TVDical
0
30'
60
.
.-1~---
Vee ~ 5.0V
'0 -~~ ;:;-
1-
TA yS"C
O~~~~~~~~~~~.
3.5 4.0
90' 120" 1.50"
TA-Ambient Temperat,ure-oC
4.5
5.0
5.5
6.0
Vee-Volts
ACCESS TIME VS AMBIENT TEMPERATURE
700
600
500
,...;'25"C
200
100
o
-55'
~.,
.......-
~
30
V
60"
Vee
~
l
5.0V
2 TTL LOADS
CL = 100 pF
90' 120" 'SO'
TA -Ambient Tamperature-°C
4·9
6.5
7.0
64K (8K x 8) Static ROM
R2364A
PACKAGE DIMENSIONS
24-PIN PLASTIC DIP
24-PIN CERAMIC DIP
~~f~~~~~~~~~~]J
I
1.190
0.530
t---' o:4sO - - - j
~ :.~~:
O.+-L-
1.2601
1.230
0.050
0.020
0.530
J-- 0:4s0----1
M~~'--.
-~.~.---'-'{S~u1---::-C0.0"-15h\
~~'IFIf'il~f:::: . ~
- - .---c-.
I
0.090
----r0.150
0.085 -lilt.
-I 1-0.110
0.040 -11-- 0 . 023 0.032 REF 0.090
0.015
0.125
4-10
O.OOS+-
U
11---0.700~
D.600
R2364B
Memory Products
'1'
R2364B
64K (8K x 8) STATIC ROM
Rockwell
DESCRIPTION
E/E
The R2364B2, R2364B25 and R2364B3 are 65,536-bit static
Read-Only Memories (ROMs), organized as 8,192 eight-bit bytes,
that.offer maximum access times of 200, 250 and 300 nanoseconds, respectively. These ROMs are in industry-standard
28-pin, dual in-line packages, and are available in ceramic or
low-cost plastic. These fully-static 64K-bit ROMs are compatible
with all eight-bit N-channel microprocessors, including the R6500
family ofmicroproc:essors.
G/G/N
Sl/S1IN
S2iS2tN
QO
Ql
Q2
Q3
Q4
QS
Q6
Q7
AO
At
A2
A3
A4
AS
A6
A7
All three R2364B ROMs operate totally asynchronously, and
require no clock input. Three mask-programmable chip select
inputs ailow up to eight 64K ROMs to be OR-tied without external
decoding. These devices provide tri-state output buffers for
memory expansion. The R2364B ROMs offer TTL input and
output levels with a mihimum noise immunity of 0.4 volts.
The mask-programmable chip enable input (EtE) may be programmed to function as a chip select without pOwer down
standby mode or as a chip enable with power down standby
mode. The active level of the enable input is also programmable.
AS A9 Al0 A11 A12
FEATURES
•
•
•
•
•
•
•
•
•
•.
8,192 x 8 organization
Access time: 200 ns, 250 ns and 300 ns (max.)
Low power dissipation: 125 mW active, 37.5 mW standby
Drives two TTL loads and. 100 pF
Single + 5V ± 10% power supply
Totally static operation, no input clock required
Completely TTL compatible
Three tri-state mask-programmable chip select inputs
Mask-programmable chip enable
Tri-state outputs for memory expansion
R2364B Block Diagram
ORDERING INFORMAtiON
Part Number: R2364B ____ _
[
28
VCC
27
A7
26
S2/S2/N*
Sl/S1/N"
A6
4
25
A8
A5
5
24
A9
A4
6
23
All
A3
7
22
G/G/N"
Package:
C = Ceramic
P = Plastic
A2
8
21
Al0
Al
9
20
ell"
AO
10
19
Q7
Temperature Range:
No letter = O°C to + 70°C
E= -4.oo C to +85~C
QO
11
18
Q6
Ql
12
17
Q5
Q2
13
16
Q4
GND
14
15
Q3
Power Down Standby Mode
S = Yes
No letter = No
Note: Submit ROM codes using
Rockwell ROM Code Order
Form, Order No. 2137
NC
A12
•
"Mask·programmable option.
N = No effect on selection/enable logic, however, voltage other
than logic levels shall not be applied.
Access Time (Max}:
2 = 2.0.0 ns
25 = 25.0 ns
3 = 3.0.0 ns
R2364B Pin Configuration
Document No. 29000D62
4-11
Data Sheet Order No. 062
Rev. 3, March 1984
II
64K (SK x 8) Static ROM
R23648
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Value
Supply Voltage
Vcc
-0.5 to +7.0
Vdc
Input Voltage
V'N
-0.5 to +7.0
Vdc
Output Voltage
VOUT
-0.5 to +7.0
Temperature Under Bias
Commercial
Industrial
TA
Storage Temperature
T STG
Power Dissipation
P
'NOTE: Stresses above those listed under "Absolute Maximum·
Ratings" may cause permanent damage to the device.· This is
a stress rating only and functional .operation of the device at
these or any other conditions above those ·indicated in the
operational sections of this specification is' not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
.
Unit
Vdc
°C
-10to +80
-50 to +95
-65 to +150
°C
W
1.0
DC CHARACTERISTICS
vcc =
5.0V ± 1O~/o, T A = O°C to 70°C (unless othelWise specified)
Symbol
Parameter
Min
Typ
Max
Units
Vcc
V
Vcc
0.4
V
Vcc
10L
,.,.A
Vcc
= 5.5V,
OV '" V in
,.,.A
Vcc = 5.5V, chip deselected,
VOUT = +0.4V to Vcc
Vcc
Output High Voltage
VOL
Output low Voltage
V'H
Input High Voltage
2.0
Vcc
V
V'L
Input low Voltage
-0.5
0.8
V
10
±10
2.4
Test Conditions
= 4.5V,
= 4.5V,
VOH
10H
= -400,.,.A
= 3.3 mA
III
Input load Current
ILO
Output leakage Current
Icc
Power Supply Current, Active
25
55
mA
ISB
Power Supply Current, Standby'
7.5
16
mA
C,
Input Capacitance'
7
pF
V cc = 5.0V, chip deselected, pin
under test at OV, T A = 25°C
Co
Output Capacitance'
10
pF
f
=
'"
5.5V
= 5.5V
1 MHz
Notes:
1. Applies only to chip enable with power down standby mode.
2. This parameter is periodically sampled and is not 100% tested.
AC CHARACTERISTICS
Vee
= 5.0V
± 10%, T A
= O°C to 70°C
(unless othelWise specified)
R2364B2
Symbol
Parameter
Min.
Max.
R2364B25
Min.
Max.
R2364B3
Min.
Max.
Unit
tAvAX
Address Valid to Address Don't Care
200
250
300
tElEH
Chip Enable low to Chip Enable High'
200
250
300
tAvav
Address Valid to Output Valid (tAcd (Access)
200
250
300
ns
tElQV
Chip Enable low to Output Valid (Access)'
200
250
300
ns
t AVQX
Address Valid to Output (t OH) Invalid
10
10
10
ns
tELQX
Chip Enable low to Output (tco) Invalid
10
10
10
ns
10
10
ns
ns
tEHQZ
Chip Enable High to Output High Z (to F)
tpu
Chip Selection to Power Up Time'
tpo
Chip Deselection to Power Down Time'
tAVEL
Address Valid to Chip Enable Low
0
~LOV
Chip Select low to Output Valid'
10
90'
10
90'
10
90'
ns
tGHQZ
Chip Select High to Output High Z
10
70'
10
70'
10
70'
ns
70'
10
ns
4·12
70'
a
a
ns
lOa'
lOa'
100'
Notes:
1. Test Conditions:
Output Load: 2 TTL Loads and 100 pF; Input Transition Time:
20 ns; Timing Reference Levels: Input: 1.5V; Output: 0.8V, 2.0V.
2. Mask programmed for chip enable with power down standby mode.
3. Mask programmed for chip enable without power down standby mode.
70'
a
0
ns
ns
0
4. Add 20 ns for extended temperature devices (- 40°C to + 85°C).
5. 8 may be delayed up to tAVOV - tGLOV after the falling edge of E
without impact on t AVOV . Data is availa~e at the Q outpi,l!s after a
delay of tGLOV from the falling edge of G, provided that E has been
low (V,J and addresses have been...valid...!or at least tAVOV - tGLOV .
6. tGHOZ and IEHOZ are specified from G or E, whichever occurs first.
. 64K(8K x 8) Static ROM
·R2364B.
TIMING DIAGRAMS
=I
READ CYCLE TIMING 2
~~~~=:t:========~A~D~DRE~S~S~'l~A~L~ID?:======== V~,H
ADDRESS
~~.~
1---------
fel,EH
...,----"';"--1
17-'---- \I'H
E (CHIP ENABLE)
1-----,. tELQV
----'
tEHQZ
feLQX~
Q (DATA OUT)
I-
-----+-- HI Z:....--~~~~t==JD~A~T~A~V~A~L~IDc:=i=:J
V,L.
HIZ- VOH
VOL
Vee SUPPLY Icc- - - - - - -...;. - - - I r - - - - - - t - - - - - - - - - t - - - " " I I
CURRENT Isa -------~
~~
WS1$z
(CHIP SELECTS)
(SHOWN ACTIVE LOW)
TYPICAL CHARACTERISTICS
SUPPLY CURRI;NT VS
AMBIENT TEMPERATURE
SUPPLY CURRENT VS
SUPPLY VOLTAGE
70r-...,..--r-...,..--,.-...,..-.,---,
0
6O~-r--t--+--+--t--+-~
5Or--r--r--r--T--T--T--'
50
~ ,40~-r--t--+--+--t--+-~
-55'
~
~al
,J 1 _L:: -e~ ~
+125'
0
St.ndbv Tyoic.,
-50' -30"
0'
30'
60"
v
5.0V
90"
120" 150'
-1-
ACC,ESS TIME VS
AMBIENT TEMPERATURE
700
03.5 4.0
TA-Ambient Temperatur_oC
"
+ 125'C
>1'
200
1~ V
I
-55' .~
0 ~-
·60
-30"
5.0
5.5
6.0
Vee-Volts
500
100
4.5
0"
Vee
~
~
5.0V
2 TTL LOADS
CL
30
60"
90
~
100 pF
120
150'
TA-'-Ambient Temperatur"-;-'°C
4-13
6.5
7,0
64K (8K x 8) Static ROM
R2364B
PACKAGE DIMENSIONS
28-PIN PLASTIC DIP
28-PIN CERAMIC DIP
[~[~~[]1
(1.420)
f 4 - - - - (1.380) - - _ . ,
I
(.550)
(.530)
~':';':;:':';"~TT"TT"T""""""'.....,.,..J~
(.160)
(.115)
(.080)
1·-·
.... ---:::::
1-..l-(·'40-, ~iTl
r-:=+-(.oos),... ~~_, :::::-1 ~::
~~c:J
I (.110) . I--- (.590) ---l
~(.155) (.065)
(.065)
(.125) (.015)
4-14
(.015)
(.090)
(.125) (.020)
Fl23C64
MemoryProcJucts
'1'
R23C64
64K (8K, x 8) CMOS STATIC ROM
Rockwell
PRELIMINARY
DESCRIPTION
The Rockwell R23C64 is an 8K x 8 (65,536 bits) CMOS static
read-only-memory (ROM) housed in a 28-pin JEDEC standard
(B version) package. It is fabricated in CMOS technology to
achieve high performance with extremely low power dissipation.
This device is available with maximum access times of 150, 250,
or 300 nanoseconds, optional extended temperature range, and
packaged in ceramic. or low-cost plas~ic.
85,536 BIT
-.
The R23C64 is controlled via .the chip enable (E) and the mask
programmable chip selects (GRilN, S1/SlIN, S2IS2IN). The
addresses are latched on the falling edge of E, allowing the
R23C64 to operate on multiplexed busses as well as nonmultiplexed buses. The chip selects control the output buffers,
however, these buffers do not become active until valid data is
present from the in~ernal. data latches. This prevents ~urious,
invalid outputs th.at increase power dissipation. When E is high,
the output buffers are in the high impedance state and the
address and chip select pins are ignored. E may also be held
low indefinitely, keeping the address latched and the output buffers under chip select control.
DATA LATCHES
GIG
S1/81
S2/82
. FEATURES
• 8,192 x 8 organization
• JEDEC approved pinout
• Extremely low power
-Active 10 mW (max.)
-Active (quiescent) 50 p.W
-Standby 50 p.W (max.)
• Fast access times: 150 ns, 250 ns and 300 ns (max.)
• Mask programmable chip selects
• Latched addresses and (optionaQ latched chip selects
• Drive two TTL loads and 130 pF
• Single 5V ± 10% power supply
• Pin compatible with Rockwell R2364B NMOS ROMs and
R87C64 and R2764 EPROMs
QO-Q7
Fl23C64 Block Diagram
NC
A12
Part Number: R23C64 ___ _
~ LTemperature Range:
NO leller = OOeto +70oe
E = -40oe to +85°e
Note: Submit ROM
codes using Rockwell
ROM Code Order Form,
Order No. 2137.
vee
27
S2IS2JN·
S1/81/N·
26
A6
25
A8
AS
5
24
A9
A4
8
23
A11
A3
7
22
GlGIN·
A2
8
21
Al0
Al
9
20
Ii
AO
10
Q7
co
11
12
13
14
19
18
17
Q5
Ql
Q2
GND
Package:
e = Ceramic
P = Plastic
28
2
3
4
A7
ORDERING INFORMATION
~
MEMORY
ARRAY
Ao-,,'2
Q6
16
Q4
15
Q3
"Mask-programmable option.
N a No effect on selection logic, however, voltage greater
than logic' level shall not be applied.
Access Time (Max):
15=150ns
25 = 250 ns
3=300ns
R23C64 Pin Configuration
Document No. 29000M05
4-15
Data Sheet Order No. MM05
Rev. 1, March 1984
R23C64
64K (8K x 8) CMOS Static ROM
ABSOLUTE MAXIMUM RATINGS·,
Parameter
Symbol
V,/llue
Supply Vottage
Vee
-0.3 to +7.0
Vde
Input Voltage
Y,N
-0.3 to Vee +'0.3'
'Vdc :
-0.3 to Vee + 0.3
Output Voltage
V OUT
Temperature Under Bias
Commercial
Industrial
TA
Storage Temperature
T STG
Power Dissipation
P
Vdc
·C
-10to +80
-50 to +95
-55
to
+150
1:0
DC CHARACTERISTICS
7o'e
Vcc = 5.DV ±10%, TA = O:'Cto
Symbol
'NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent'damage to the: device,This is
a stress rating only and functiona:j operation of the device at
these or any other conditions ,above .those indicated'in the
operational sections of this specification is not implied. Expo"
sure to absolute maximum rating conditionS forextellded periods
may ~ffect device reliability.
Unit
Output High VoHage
VOL
Output Low Vottage
W
(unless otherWise specified)
Parameter
V OH
·C
Min
Typ
2.4
Max
Units
Test Conditions '
Vee
V
Vee
0.4
V
Vee
V
= 4.5V,
= 4.5V,
10H
IOL
= -200 p.A +130 pF
= 3.2 mA+ 130 pF
V ,H
Input High Vottage
2.0
Vee
V'L
,Input Low Vottage
-0.3
0.8
V
III
,Input Load .current
±1
p.A
Vee = 5.5V, OV .. V IN .. 5.5V·
Output Leakage Current
±10
p.A
Vee = 5.5V: chip deselected,
VOUT = +O.4V to Vee
2
1
mA
mA
T ELOV = 150 ns'.V ee
T ELQV = 300 ns', Vee
10
p.A
E = Vee -0.5V; all other pins aetive
V cc = 5.0V, chip deselected, pin u~der
test at OV, T A = 25'C, f = 1 MHz
, I LO
lee
' Power Supply Current:
Activ~
ISB
Power Supply Current. Standby
C,
Input Capacitance (all but
(E)
Co
Output Capacitance 3
E)
Notes:
1. TELEH = 150 ns, all pins aclive,no loads, 1 p.see cyele time (TELEL
2. T ELEH = 300 ns, all pins active, no loads, 2 p.sec cycle time (T ELEL
3. This parameter is periodically sampled and is not 100% tested.
5
10
pF
pF
10
pF
= 1 p.s).
= 2 p.s).
4-16
= 5.5V
= 5.5V
..
R23C64
64K (SK x 8) CMOS Static ROM
AC CHARACTERISTICS
Vee
=
50V
-+
10% TJi
=
O°C to 70°C (unless otherwise specified)
R23C64-15
Symbol
Parameter
Min
R23C64-25
Min
Max
R23C64-3
Max
Min
Max
Unit
tElEl
Cycle Time
220
365
465
ns
tELEH
Chip Enable Low to Chip Enable High
150
250
300
ns
tEHEL
Chip Enable High to Chip Enable Low
60
100
150
tElQV
Chip Enable Low to Output Valid (Access)
t AvEL
Address Setup Time
0
0
0
ns
tELA><
Address Hold Time
50
65
ao
ns
tGVQV
Chip Select Valid to Output Valid
100
150
tEHQZ4
Chip Enable High to Output High Z
la XQZ4
Chip Selects Invalid to Output High Z
t F, tR
Rise and Fall Times'"
50
10
ns
250
150
10
50
300
ns
50
10
50
10
ns
50
ns
15
10
ns
20
i
ns
Notes:
1. Test Conditons: Output Load: 2 TTL Loads and 100 pF; Input Transition Time: 20 ns; Timing Reference Levels: Input: 1.5V; Output: o.av, 2.0V.
2. Rise and Fall times stated are required for these high performance parameters only and may be relaxed to 100 ns for slower operation,
e.g., 100 kHz operation.
3. G may be delayed up. to tAVQV-...!!llQV after the f~ing edge of E without impact on tAVQv, Data is available at the Q outputs after a delay of
tGlQV from the falling edge of G,-pro~ded that E has been low (VIU and addresses have been valid for at least tAVQV-tGLQV'
4. t EHQZ , tGHQZ are specified from G or E whichever occurs first.
TIMING DIAGRAM
...
READ CYCLE TIMING
telEL
-. ~
--. ~
ADDRESSES
nun·
CJJJlJlJIJII
...
tElEH
VEL - - .
~teHEL~
..tYW!l'l
DRESSES
UUU'
l"- VAlID......:J!
tELAX
GtS1tS2
CHIP SELECTS
CHIP SELECTS
VALID
lX,
~tGVQV--':
HI-Z
Q (DATA OUT )
-...
~
.
teLQV
4-17
UATA
VALID
--iJto
HI-Z
~~EHQZ
I GXQZ
II
64K (8K x 8) CMOS Static ROM
R23C64
PACKAGE DIMENSIONS
:i8-PIN PLASTIC DIP
28-PIN CERAMIC DIP
[~[~J~]l
(1.420)
1 - - - - - (1.380)
---I
I
(.550)
(.530)
~~~~~"TTTT...,..I~
-r·'-.-.-._
_ _ _ _ _--1l---i
(.115)
(.080)
~~
(1.470)
(1.440)
--i
(.160)
(.140)l--(.610)
1,--(·590)
~~8{: 1l; jfiEjt~~"~ ~,~::
~#I'---'-I---J'
1
(.055)
(.010)
(.110).
~(.155)
I--- (.590) --I
(.065)
(.065)
(.125) (.015)
4-18
(.015)
(.090)
(.125) (.020)
"
(.015)
(.008)
R23128
Memory Products
'1'
R23128
128K (16K x 8) STATIC ROM
Rockwell
DESCRIPTION
G/G/N
S1/S1/N------------,
E---------~----_.
The R23128-25 and R23128-3 are 131 ,072-bit static Read-Only
Memories (ROMs), organized as 16,384 eight-bit bytes, that
offer maximum access times of 250 and 300 nanoseconds,
respectively. These ROMs are in industry-standard 28-pin, dual
in-line packages, and are available in ceramic or low-cost plastic.
These fully-static 128K-bit ROMs are compatible with all Nchannel microprocessors.
The R23128 ROMs operate totally asynchronously, and require
no clock input. Three mask-programmable chip select inputs
allow up to eight 128K ROMs to be OR-tied without external
decoding. These devices provide tri-state output buffers for
memory expansion. The R23128 ROMs offer TIL input and
output levels with a minimum noise immunity of 0.4 volts.
AO
The chip enable input (E) functions as a chip enable with power
down standby mode. When this line is high the chip is disabled
and enters a low power standby state.
A6
A1
A2
A3
A4
A5
A7
00
01
a:
w
cO~
u"'
w"-
02
03
131,072 BIT
ROM
CELL ARRAY
CO
~O~
a:
04
05
06
07
AS
FEATURES
• 16,384 x 8 organization bytes
• Access time: 250 ns and 300 ns (max.)
• Low typical power dissipation is 100 mW active, 20 mW
standby
• Drives two TIL loads and 100 pF
• Single +5V:!: 10% power supply
• Totally static operation, no input clock required
• Completely TIL compatible
• Three mask-programmable chip select inputs
• Tri-state outputs for memory expansion
R23128 Block Diagram
NC
A12
A7
ORDERING INFORMATION
Part Number: R23128= __
L
PaCkage:
~
C = Ceramic
P = Plastic
Temperature Range:
No letter = O'C to + 70'C
E = -40'C to +85'C
Note: Submit ROM
codes using Rockwell
ROM Code Order Form,
Order No. 2137
vce
SlJii/N'
A13
A6
A5
A4
AS
A3
A2
GlG/N'
AI
E
AO
00
07
01
05
02
Q4
GND
03
AS
All
AIO
06
• Mask-programmable option.
N = nD effect on selection/enable logic. however, voltBlle
greater than logic levels shall nol be applied.
' - - - Access Time (Max):
25 = 250 ns
3=300ns
R23128 Pin Configuration
Document No. 29000M03
Data Sheet Order No. MM03
4-19
Rev. 2, March 1984
II
128K (16K x 8) Static ROM
R23128
ABSOLUTE MAXIMUM RATINGS·
Parameter
Symbol
Value
Unit
Supply Vollage
Vee
-0.510 +7.0
Vdc
Inpul Vottage
V in
-0.510 +7.0
Vdc
Vout
-0.510 +7.0
Output
Vo~age
Temperalure under Bias
Commercial
Industrial
TA
Storage Temperature
TSTG
Power Dissipalion
Po
'NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect device reliability.
Vdc
~C
-1010 +80
-5010 +95
-6510 +150 'C
1.0
W
DC CHARACTERISTICS
vcc = 50V -+
Symbol
10% T A
= O'C to 70'C (unless otherwise specified)
Parameter
Typ
Min
VOH
Outpul HIGH Voltage
VOL
Output LOW Voltage
V IH
Input HIGH Voltage
2.0
V IL
Inpul LOW Voltage
-0.5
III
2.4
Max
Test Conditions
Units
Vee
V
Vcc = 4.5V, 10H = -400/LA
0.4
V
Vee = 4.5V, 10L = 3.3 mA
Vcc
V
0.8
V
Input Load Cun:ent
10
/LA
V cc = 5.5V, OV '"
ILO
Outpul Leakage Current
:!::10
/LA
V cc = 5.5V, chip deselected
YOU! = +O.4VIOVcc
Icc
Power Supply Current, Aclive
55
mA
Vee = 5.5V
ISB
Power Supply Current, Standby
16
mA
7
pF
10
pF
CI
Input Capacitance'
Co
Outpul Capacilance'
20
7.5
Yin '"
5.5V
V cc = 5.0V, chip deselected, pin
under lest al OV, T A = 25'C
f = 1 MHz
Note:
1. This parameter is periodically sampled and is not 100% tested.
AC CHARACTERISTICS
vcc = 5.0V :!:: 10%, T A = O'C to 70'C (unless otherwise specified)
R2312&-25
Symbol
Parameter
Min
R2312&-3
Max
Min
Max
Units
ns
IAVAX
Address Valid 10 Address Don'l Care
250
300
leLEH
Chip Enable Low to Chip Enable High
250
300
IAVOV
Address Valid to Output Valid (tAce> (Access)
250
300
ns
lewv
Chip Enable Low to Output Valid (Access)
250
300
ns
IAvoX
Address Valid 10 Output (tOH) Invalid
10
10
ns
lewx
Chip Enable Low to Output (teo) Invalid
10
10
ns
10
t EHOZ
Chip Enable High to Output High Z (t oF)
Ipu
Chip Selection to Power Up Time
70
10
ns
70
100
100
ns
ns
0
0
ns
tpo
Chip Deselection to Power Down Time
I AveL
Address Valid to Chip Enable Low
tGLOV
Chip Select Low to Output Valid
10
90'
10
90'
ns
tGHOZ
Chip Select High to Output High Z
10
70'
10
70'
ns
Notes:
1. Test Conditions:
Output load: 2 TTL loads and 100 pF
Inpul transilion lime: 20 ns
Timing ref~rence levels: Input: 1.5V; Output: 0.8V, 2.0V
2. Add 20 ns for extended lemperature devices (- 40'C to + 85 D C).
ns
0
0
be delayed up to tAVOV-tGLOV after the falling edge of E
without impact on IAVOV' Dala is avail~le at Ihe Q oute,ulS aiter a
delay of tGLOV from the falling edge of G, provided that E has been
low (VIL) and addresses have been ..".alid ~or at leasl IAVOV-tGLOV'
4. tGHOZ and IEHOZ are specified from G or E, whichever occurs first.
3.
G may
4-20
.
128K(16K)( 8) S~atiC ~M
R23128
AM~DDRESS
TIMING DIAGR{'
READ CYCLE
TIMING 1
(E HELD LOW)
INPUTS
~~,,--
_ _ _{--'-'- , - . - - - - I AVAX
--~";":""~-"-'~'1,--_--,--_ V'H
....
'
:""
):
:,
V'L
I AVQV - - - I
2-L ,IAVQX ----j
DATA VALID
VOL
-=~~~~~~~~~==~~~~==========~~~~~========VOH
Q (DATA OUT) _
PREVIOUS DATA VALID
ADDRESS
INPUTS
1r-.,-,--- V'H
E (CHI~ ENABLE)
, V'L
READ CYCLE
TIMING 2
IEHQZI_
z.
Q (DATA OUT)
VOH
VOL
Vee SUPPLY Icc
CURRENT IS9
------------~J---~~
GtS1
~
CHIP SELECTS
(SHOWN ACTIVE LOW)
(ACTIVE)-"--..,..._...J·
TYPICAL CHARACTERISTICS
SUPPLY CURRENT VS AMBIENT TEMPERATURE
Sl.!PPLY CURRENT VS SUPPLY VoLTAGE
70..--r-r-"""T-:-,---r--r---.
7O'
O~-+--+--+--+-~--~~
60
Or--+--+--+-+-~--~-;
~
40
I
Jl
30
o
0
""
'~
40
I
Jl
-w '
YPical +-~
.I j"::r--
I --..
__-+-~
_~1,25'
0
o -=t-Standby Typica;'--- ~'.,.=~5.0V
E60' - 30'
0'
30'
0
"
- - .......... Active Ii .
60'
90'
120'
-- '. J
10
ACCESS TIME VS AMBIENT TEMPERATURE
150'
700r--r--~"""T--,....--r---r--'
. 'Ii:,:
TA-Amblent Temperature-OC
600~-+--~-+--+-~---+-~
~
g4OO~-+--~-+--+--'-I---+-~.
$-
300~-+--~-+--+-~---+-~
-60' -30'
0'
30'
60'
BO' 120' 150'
TA-AmbJent TemperBlUre;"'OC
4-21
'J><;\ive~staOclbY TYpiC~:::
o
~$
--r
4.0 4.5
5,0
5.5
Vcc-VolI8
t',=(5'C
6.0
6i5
.7.0
"
.3
R23128
128K (16K x 8) Static ROM
PACKAGE DIMENSIONS
28-PfN PLASTIC DIP
28-PiN CERAMIC DIP
[]J~~]j
, (1.420)
t - - - - - - (UIQ)
---"I
I
(.550)
(.530)
L.,:,-,.,-T1'TT'I'TTTTr.,..,......,'TTTT'I~~
1--1"---
(.115)
('0:0)
(1.410)
---I ~
(.1<10)1--(.610)
~LJ
~('008) ~~I-t~-A~~~:~ =
~
(.012)
1(.110)
~(.590)--l
(.090) •
(.155) (.065)
(.i25) (.015)
(.065)
(.065)
,
4-22
_
(.023) .032 REF (.110)
(.150) (.060)
(.015)
(.125) (.020)
(.090)
R27064P
'MemOty, Producfs
'1'
R27C64P
64~ (8K x 8) CMOS ONE- TIME PROM
Rockwell
PRELIMINARY
FEATURES
DESCRIPTION'
• 8,192 x 8 organization
• JEDEC approved pin-out
The Rdckwell.R27C64P is an 8Kx 8 (65,536 bits) one·iime programmable read-only·memory (PROM). It is manufacturedusihg
CMOS technology for low power dissipation in .both active.and
standby operating modes. Access timeS 01250ns and350'rls
is performa~ce. compatible with most 8·bit .and 16·bit
microprocessors.
. . ..'
• Low Power
-Active 80 mW (max.)
-Standby 525 p.W (max.)
• Access times: 250 ns and 350 ns (max.)
• Single 5V power supply
• Static operation, no clocks required
• One·time programmable
• TTL compatible inputs and tri·state outputs during both read
and program mode
Initially, all b.its. are in the."1."statE!:.Data is p.rog. r.am.'.me.d. bY.'.
app'!ying 21" to Vpp a TTL low to E, and a 50 m~ low pulse
on P while the desired data is stable on DqO·DQ7 lines and
the address is stable on AO·A 12 lines.
The R27C64F'is ideal lorlow:cost permanent me~ory:ikpPlica.
tions (program and/or data) in prGduction rUns requiring fast programming turn-around either at the factory, distributor/dealer or
user's facility.
• Pin compatible with INTEL 2764A EPROM, Rockwell
R87C64 EPROM and R23C64 and R2364B ROMs.
ORDERING INFORMATION
VPP
VCC
Ad'
P
Part Number; R27C64P __
..-..-
L
A7
ACClISsTlme:
25
250 ns
. 35 .. 350 ns
A6
=
=
A~
A4
26
2.5
24
23
NC
AS
AfI·
An
G
A3
A2
A1
AO
MEMORY
ARRAY
.. DQO
D01
002
GND
E
19
18
007
17
DQ5
16
15
DOli
D03
DQS
R27C64P Pin Configuration'..
AO-A12
ADDRESSES
E
CHIP ENABLE
G
OUTPUT ENABLE
DOO-DQ7
P
DATA INPUT/Qufp\JT
.•.... PROGRAM ENABLE
..
'
R27C64P Pin Na",es
R27C64P. Block Diagram
Data Sheet Order No.MM18
March 1984
Document No. 29000M18
4·23
4
64K (8K x 8) CMOS OTP PROM
ABSOLUTE. MAXIMUM RATINGS·
Symbol
\"arameter
Supply Voltage
Vee
Input VQltage; . ,1)1-'
All, except Vpp during
Programming
VPII during Progrll,mmiog,'
,ViN
Output Voltage
- 0.3
Value
Unit
!O + 1.0.
Vdc
Vdc
-0.3 to Vcc +0.3
-0.3 to +22.0
VO(lT
-0.3 to Vcc +0.3
Temperalure under Bias
TA
_10 to +80
StorageTiimllerature "
TSTG
-40 t'o'125
ppwer Dissipation,: @ 25°C
P
:
...
Vdc~
°C
.,
°C
W
1.0
"
:~",
IiS~~nderAB~OLlrrE MAX-
°NOTE: Stresses above those
IMlJM RATINGS may cause peiltlanerit damage to the~~eVfee.
This is lI,stref!ls rating only and h!nCti~Il'~1 oPeration oft!i,~devi~
'at the'sl'tor ariyot;'er conditions IlbOve tl:!qSe indicated in the
operational sections of this speeifi9atlon 'is not ilTlplied. Exposure,
to absolute m~imum rating condiiions for extended period!! may
'. affecfdeilicereliilbility;
"
'
•
'.
OPERATrNGCONDITIONS
'j;, .
.
<
~
_ •
Pilramete~
c
,
\
,Rod Mode
"
Program Mode
5V ±5%
Vee Supply Voitage
5V ±5%
i:!1V ±·O.SV
'?~'·,~~~MTI~9~I1ARACTERI~!I~~"DURJ.NG
Vcc~c,.5:~V± 5%" TA = O~C
"
Parameter'
,'r'
SymbOl
7'"
Vo~
Ouipul High Voltage
. VOL
Output Low: Voltage
V'H
Inllut High Voltage
READ
to ]O<'?C' (untessOttlf!\Wise specified)
c
~
. ,"
Typ_
Min.
-
2.4
2.0:
.,.,
",
Max.
Teat Conditions
Unit
IOH = -400 p.A
V '
0,45
V
Vcc+ 0.3
V
10l" 2;t'mA
.. ,
",
,-
O.B
V
100
p.A
15
mA
E=G=V,l
Vp,. Current.
100
p.A
Vpp
liN
Input Leakage Current
±10
p.A
V 'N :" OV to Vee
±10
p.A
VOUT .. OV to Vee
7
pF
. 10
pF
VC;C' = 5.0V. chip deselected, pin under lest
at OV, TA = 25~C
f = 1 MHz
V'l
InputLOIN Voltage
lee1
Vce Standby Current
ICC2
Vcc Active Current
Ipp
10
Output Leakage Current
C,
InputCapacitance2
Co
Output Capaditance2
-0:1
,
E = Vcc/.G = V'l' Y'N = OV or Vee
""._,
Notes:
1. Applies only to chip enable with power down standby mode.
2. This parameter Is periodically sampled and is not 100% tested.
~IVCc max.
".
DC OPERATING CHARACTERISTICS DURING PROGRAMMI:NG
Vee
= 5.0V
Symbol
±5%, TA
= '20°C to 30°C, Vpp = 21.0V
Parameter
Min.
Input High Volta!;!e
2.0
V,l
Input Low. Voltage
-0.1
Icc
Vcc Active Current
V,"
Ip~
liN
..
, Vpp ACiive, ,currf""t
±O.5V
Typ.
Max.
Unit
Vee +0.3
V
0.8
,
hiputLeakaile Current
..
},'"
4-24
·v
0.5
mA
30
mA
: 10
p.A
Teat Conditions
'.
E= P=
V,l• G = V,H
V,N = OV to Vee
~~~~P
MetnoIy-.Producte
'1'
R27C64P,
64K (SK x 8) CMOS ONE..TIMEPflOi\ll'
Rockwell
'"i!
(",
PRELIMINARY
FEATURES
DESCRIPTION
• ,8,192 x 8 qrganizatlon
The Rockwell, R27C64P,isan 8K,x 8 (65,536 b"-,> qi1e-time p,.q;.
grammable read-only.m&mory (PROM). It ismanufaCtUradusing
CMOS technology tor low P,Ower QISSipation in "'~. activE! 8I)d
standby operating modes.·AcceSs tim~6f 250nfl and 350;~s
is performance compatible with most 8'bit anc!: 16-bil
microProcesSors.
:
"
, ,,' ',' . :.
• JEDEC approved pin-pul
• Low Power
-Active 80 mW (max.)
'-Standby 525 p.W (max.)
• Access times: 250 ns and 350 ns (max.)
prog~m,'~~,
InitiallY,: aU tilts are, in the ",1," stat!!.,'oat!!, is
by,' '
appJyin!;l21Yto Vpp a TTL: low to E, anda501Yl'l,lqw pulse
on P whilettie desired -data is stable on Dq()..oQ7 (ines and
the address is,stable on A()..A12 lines.
'
• Single 5V power supply
• Static operation, no clocks required
• One-time programmable
• TTL compatible inputs and tri~state outputs during both read
.
and program mode
.
~The;~7C64Pis ideal foHow.:cost ~rm~"'~ntm~fuo~"il~Plica
tions (pri:l9ra'm and/or erSt&) in ~ctionrti,nli requirfnll faSt programming tUm-around,eiUter aUhefactory, distributoridealer or '
user's facility.
"
• Pin compatible .with INTEL 2764A EPROM, Rockwell
R87C64 EPROM and R23C64 and R2364BROMs.
ORDERING INFORMATION'
-Li
vpp
Pan Numb8r: R27C64P':.~
,
Ad
A7
AS'
AccMaTlme:
25 .;. 250 na
35=,3$0 na
AS .
A4
~
~J'
A2
Al
AO
MEMOR~
.,ARRAY
vee
,p
NC
Aa ",
At
:Ali
G
Al0
t,
D07
. ,,"
DQO
~,
DOt
D05
D02
DO.
"'GND
003
1U7C84J1i Pin Configuration',.
AO-A12
ADDRESSES
E
ClitlPENABlE
,G
OUTPOT ENABLE
"PROGRAM E~BlE
R27C64P,BIOC,k Diagram
", "
Data Sheet Order No.MM18
Document No. 29000.,18
March ,1984
4-23
4
'
64.K (8Kx 8) CMOS OTP PROM
ABSOLUTE MAXIMUM RATINGS"
~:arameter
Symbol
V(X;
Supply voltage
Value
Vdc
Vdc
"
InputVoltagai';'" ",:
,,vIN
All, except Vpp dlldng
Programming
Vpp aU,ring Progr!lmmiog"
-0.3 to Vee +0.3
":0.3 to +22.0
Output Voltage
VOUT
-0.3 to V(X; +0.3
Temperatllre under Bias
T,(
-10 to +80
°C
Storage 'Temperature,'
T8TG
-40'10125
°d
Powe~ Dissipation, @ 25°C
P
,!
-
"
,
Pa..ameter
Read Mode
5V ±5%
Vdc'
1.(1.
.'
Vcjc Supply Voltage
thosenSt~ underABSOLlJiE~~·
°NOTE: Stresses above
IMUM RATINGS may cause permanent damage to th~deviee.
This is ~.~Iress rating only and functi\;;' OV to Vee
10
Output
Lea~age
±10
,.A'
VOUT
CI
Inputtall8Citanee2
pF
Co
OutPut Capacitance2
Vqc = 5.0V, chip deselected, pin under test
atOV, TA = 25~C
f = 1 MHz
Current
7
pF,
' 10
"
"
"
,
Notes:
1. Applies only to ehip enable with power down standby mode.
2. This parameter is periodically sampled and ,is not 100% tested.
E
= Vee,G = VIL'
"IN
= OV or Vee
= OV to Vee
'"
DC OPERATING CHARACTERISTICS DURING PROGRAM,.,.NG
Vee ~ 5.0V ±5%,TA =; 200 C to
Symbol
VIH
300 C, V pp
= 21.0V±O.5V
Parameter
Min.
Input High Voltage
2.0
-0.1
Typ.
Max.
Unl!
Vee +0.3
''V
:0.8
.V
VIL
Input Low Voltage
Icc
Vee Active Current
0.5
mA
Ipp
, V pp ACtiVE! -Curr~nt
30
,rnA
'10
' ,',,.A
liN
Input Lea~ge Current
,
..
.
"
'f·
4-24
' Test 'Conditions
..
,
"
E = j5 = VIL• G = VIH
YIN
= OV to Vee
-
64K (8K x 8) CMOS OTP PROM
R27C64P
AC CHARACTERISTICS DURING READ
Vce = 5.0V ± 5%, TA = ooe to 70 e (unless otherwise specified)
0
R27C64p·25
Symbol'
Parameter
Min.
R27C64p·35
Max.
Min.
Unit
Address to Data Valid
250
350
ns
tELOV
Chip Enable to Data Valid
250
350
ns
G = V,l
tGlQV'
Output Enable to Data Valid
10
120
ns
E ~ V'l
0
ioo
10
tGHQ:f
Output Enable to High Impedance
0
t AXQX
Address to Output Hold
0
tEHQZ
Chip Enable t6 High Impedance
0
100
90
Typ.
Test Conditions(')
Max.
t Avav
typo
0
90
0
100
E ~ G ~ V'l
ns
E '" V'l
ns
E = G ~ V'l
ns
G ~ V'l
Notes:
1. G may be delayed up 10 tAVQ\I'"tG.L9V after the fallil!,g edge of E without impact on IAVQV ' Data is available at the DQ outputs after a delay
of tGlQV from the falling edge of G, .£rovi£ed that E has been low (V,C> and addresses have been valid for at least tAVOV-tGlQV'
2. tGHQZ and tEHQZ are specified from G or E, whichever occurs first.
3. Test Conditions:
Output load: 1 TIL gate and Cl = 100 pF
Input Rise and Fall Times: :s 20 ns
Input Pulse levels: O.45V to 2.4V
Timing Measurement Reference Level: Inputs 1V and 2V
Outputs O.BV and 2V
READ TIMING DIAGRAM
ADDRESSES
VALID
ADDRESSES
E (CHIP ENABLE)
i----IeLQV---"'i
G (OUTPUT ENABLE)
HIGHZ
OUTPUT
-------+-------+-++-t-
. '+S .
~
45
PROGRAM TIMING DIAGRAM
_ _ _ _-I_--PROGRAM
VERIFY
ADDRESSES
VALID
HI-Z
Vpp
~LQV
~ (OUTPUT ENABLE)
4-38
,,-..
..
p,s
120
ns
1PO
I)s
" 55
50
-
(DATA)
OUTPUT
p,s
"
Notes:
Test Conditions:
Output Load: 1 TTL gate and C L = 100 pF
Input Rise and Fall Time$: :s 20 ns
Input Pulse Levels: O.45V to 2.4V
Timing Measurement Reference Level: Inputs 1V and 2V
O\l.tputs O;!3V and 2V
ADDRESSES
p,s
p,s
0
1 - - - - - PROGRAM
Units
ms
64K (8K x 8) CMOS UV EP.ROM
R87C64..·'
OPERATING MODES
Program Mode
The Rockwell R87C64 has five modes of operation (see table 1).
The R87C64 is hi the program mode when V pp is at 21V with
E input at VIL. The data to be programmed is applied to the data
.Read Mode
output pins. When the address controls and data are stable, a
50 msec program pulse is applied to the P input.
The read mOde is governed by Iwocontrol pins, Eand G. In order
to obtain data at the outputs, both E andG must be V IL. E is
the power controlanc;l shc;>uld be used for device selection. G
is the output c~ntrol and should be usEid to gate data to the output pins. Valid daia will appear on the output pins after TAVQV,
T ELQV ar T GLQV times, depending on whicl1 is limiting.
Program Verify Mode
A program verify should be performEid on the programmed bits
to determine that they were correctly programmed. The verify
may be performed with V pp at.21V. Data should be verified to
tGLQV after the falling edge of G.
Standby MOd.e
Program Inhibit Mode
The standby mode of the R87C64 reduces power diSSipation.
The R87C64 is plac6d in the standby mode by making E = V1 H.
This is iodeperidentof G and automatically puts the outputs in
their high impedance (High-Z). state.
Table 1.
Pin
E
(20)
The progr/1.m inhibit mode allows programming several R87C64
EPROMs simultaneously with different data for each by usi~
E to control which devices respond to the program pulse on.-,-"-P~,
-===
Mode Selection
P
G
(22)
(27)
Vpp
(1)
Vee
(28)
OQO-OQ7
(11-13, 15-19)
Mode
Read
V1L
V 1H
No Effect
+5
Q OUT
V1H
V1L
No Effect
+5
Standby
+5
+5
High·Z
Program
V1L
No Effect
V1L
+21
+5
Din
Program verify
V 1L
V1L
V 1H
+21
+5
Q OUT
Program inhibit
V1H
No Effect
No Effect
No Effect
+21
+5
High-Z
No Effect
VIH
+21
+5
High·Z
Program inhibit
Note: No Effect = No effect on selection/enable logic, however, no voltage other than logic levelS shall be applied.
ERASURE PROCEDURE
The integrated dose for erasure should be a minimum of
15 W-sec/cm2. The erasure time with this dosage is 20 minutes
using an ultraviolet lamp with a 12000 uW/cm2 power rating.
Initially, and after each erasure by ultraviqlet light, all bits of the
R87C64 are in the "1" state. In Program Mode, "O"s are selectively programmEid into the desired bit locations. The only way
to change a "0" to a "I" is by ultra-viol!!t light erasure.
Caution
The erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms .
Sunlight and certain types of fluorescent lamps have
wavelengths in the 3000-4000 Angstroms range.
.The recomm!!nded erasure procedure for the R87C64 is
exposure to ultra-violet light which has a wavelength of
2537 Angstroms.
4-3~
II
64K (SKx S) CMOS U~ EPROM
RS7ca4
PACKAGE DIMENSIONS,
MILLIMETERS
DIM
2IJ..PIN CERDIP
A
B
I::::::::::::::II
C
D
F
G
,J
" J
K
L
M
N
NOTE: EITHER ROUND OR SQUARE UV WINDOW.
4-40
MIN
36.32
12.95
3.68
MAX
37.34
13.46
4.19
0.41
0.51
1.27
1.52
2.54BSC
0.20,
0.30
0.20
0.30
3.18
.4.19
16.13
17:41
15.24
15.75
0.89
1.14
INCHES
MAX,
MIN
1.430
1.470
0.~,10
0·145
0.Q16'
0.050
0.100
0.008
0.008
0.125
0.635
Q.600
0.035
0.530
.Q.165
0.020
0.060
esc
,0.012
0.012
0.165 '
0.685
0.620
0.045
R5213/2816
Memory Products
'1'
Rockwell
R5213/2816
16K (2K x 8) ELECTRICALLY ERASABLE ROM
PRELIMINARY
FEATURES
ROW DECODERS
• 2K x 8, 2048 x 8 organization
• Single 5V ± 10% supply
• TTL or high voltage byte erase/byte write
• 9 ms o'r 1 ms byte erase/byte write
• 10,000 erase/write cycles per byte
• Chip clear
• Access time: 350 ns (max.)
• Infinite number of read cycles
• JEDEC Approved pinout
• Pin and 2816A EEPROMs compatible with Seeq 5213,
Intel 2816
COLUMN DECODERS
,MEMORY
ARRAY
Ao-A3
ORDERING INFORMATION
Part Number:
R5213
L
G
E
PaCkage:
CERDIP
Access Time:
25 = 250 ns
35 = 350 ns
R5213 Block Diagram
' - - - - - Model
No Letter = 9 ms Byte Write/Erase
H = 1 ms, Byte Write/Erase
vee
A8
A9
A7
A6
AS
A4
A3
A2
A1
AO
DOO
DESCRIPTION
The Rockwell R5213/2816 is a 2K x 8 (16,384 bits), 5Velectrically ~rasable Read-Only Memory (EEROM). DatI'!. is electrically written either by a TTL pulse Or a voltage between 15V
and 22V on the Write Enable pin. Once written-thiS requires
dess than 10 milliseconds-there is no limit to the number of
read cycles. A byte erase as well as a chip clear mode is available. Each byte may be erased and written 10,000 times. The
erasure time, in either a byte erase or chip clear mode, is less
'than 10 millisecOnds.
W
G
A10
E
007
DQ6
DOS
DQ4
D01
D02
GND
003
R5213 Pin Configuration
The R5213 is ideal for appli~tions requiring a nonvolatile
' d erase capab'lity
These Jea.
tem wn'et an
I
memory w ith In-sys
tures make possible dynamic reconfiguration, i.e., operating
software is altered in real time. Possible applications are instrument/machine self calibration, programmable character generators, table look-up updates over telephone lines, and cOl1troliing
automotive fueVair ratio. Designing the ,R5213 into 8- and 16-bit
microprocessor systems is also simplified since the typical
access time is less than 250 ns, allowing zero wait state
operation.
'
AD-A1D
DOcument No. 29000M01
4-41
ADDRESSES
E
CHIP ENABLE
G
OUTPUT ENABLE
W (VPP)
WRITE ENABLE
oaO-DQ7
DATA INPUT (WRITE OR ERASE)
DATA OUTPUT (READ)
Data Sheet Order NO.,MM01
Rev. 2, March 1984
16K (2K x 8) EEROM
R5213/2816
'NOTE: Stresses above those .listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
.those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS·
Symbol
Value
Supply Voltage
Parameter
Vee
-0.5 to +7.0
Vde
Input Vo~age
V'N
-0.5 to +7.0
Vde
VOUT
-0.5 to +7.0
Vdc
Temperature Under Bias
TA
-10to +80
'0.
Storage Temperature
T STG
-65 to +100
'0.
W Level During Wr~ingJ
Erasing
Vw '
-0.5 to +22.0
. Output VoHage
W Max. Duration at .22V
During W/E Inhibit
tw
24
Unit
OPERATING CONDITIONS
Vde
Hrs
Parameter
All Modes
Vee Supply Voltage
5V ± 10%
Temperature Range
o to 70'0.
DC CHARACTERISTICS
Vee
= 5.0V +-
Symbol
10% T A = 0'0 to 70'C (unless otherwise specified)
P.rlUlleter
Min.
Typ.(')
Max.
Unit
'nIat COndltlons(1)
I'N
Input Leakage Current
10
/LA
V'N = Vee Max.
10
Output Leakage Current
10
/LA
VOUT = Vee Max.
Iw
.Wrfte Enable Leakage
Read Mode
1.0
1.5
mA
W=V'H
-1.0
mA
W=V'l
W/E Mode-High Voltage
1.5
mA
W/E Inhibit Mode:-Highl,bRage
1.5
mA
-1.0
mA
W/E Mode-TTL
1.5
mA
lee1
Vee Standby Current
15
30
mA
W = 22V, E
W = 22V, E
W =V'L
W =22V
E =V'H
lee2
Vee Active Current
50
80
mA
E=
V,dDC)
Input Low Voltage (DC)
-0.1
O.B
V
V,dAC)
Input Low Voltage (AC)
-0.4
V'H
Input High Voltage
2.0
Vee + 1
V
Vw
W Read Voltage
2.0
Vee + 1
V
O.B
V
Chip Clear Mode-TTL
Chip Clear Mode-High Voltage
W Wr~e/Erase Voltage
-TTL Mode
-0.1
-High Voltage Mode
15
Val
Output Low Voltage
VOH
Output High Voltage
2.4
VG
G Chip Clear Voltage
14
C'N
Input Capacitance
C OUT
Output Capaeitance(3)
V
21
5
= V'l
= V ,H
~ = V'L
Time = 10 ns
22
V
0.45
V
IOl = 2.1 mA
V
IOH = -400 /LA
22
V
I G = IO ILA
10
pF
Vee = 5.0V, chip deselected, pin
under test at OV, T A = 25'C, I =
1 MHz
10
pF
, Cvec
Vee Capacitance (3)
500
pF
G= E =
Cvw
Vw Capacitance(3)
10
pF
G =
V'H
E = V'H
Notes:
1. Test Conditions: Output Load: 1 TTL gate and C L ;= 100 pF; Input Rise and Fall Times: .. 20 ns; Input Pulse Levels: 0.4SV to 2.4V; Timing
Measurement Reference Leyel: Inputs: IV and 2V, Outputs: O.BV and 2V
2. Typical values are lor T A = 25'C and Vee = S.OV.
3. This parameter is periodically sampled and is not 100% tested.
4-42
16K (2K x 8) EEROM
R5213/2816
AC CHARACTERISTICS DURING READ
',-
R5213-35(4)
R5213-25(4)
Min.
Typ.
Max.
tAVQV
Address to Data Valid
10
200
250
teLQv
Chip Enable to Data Valid
10
200
250
tGLQV
Output Enable to Data· Valid
10
50
90
10'
teHQz. tGHQz(2)
Output Enable to High Impedance
0
50
70
,0
tAXQX(3)
Output Hold from Address, Chip Enable,
or Output E~able. whichever Tr!lnS,~lon
Occurred First
0
Symbol
Parameter
Min.
Typ.
Max.
Tast Condltlons(l)
300
350
300
350
50
100
E =<3 "V1L
G = V 1L
E ';" V 1L
E = V 1L
E =<3 =V 1L
80
50
0
"
Notes:
1. Test Cond~ons: Output Load: 1 TTL gate and CL • 100 pF; Input Rise and Fall Times: ,,;20 ns; Input Pulse Levels: O.45V to-2.4V; Timing
~easurement Reference Level: Inputs: 1V and 2V, Outputs: 'l:8V and 2V
2. G may be delayed up to tAVQv-t(ij,pV after the falli~g adge of E without impact on tAVQV' Data is available at the DQ outputs after a delay
of tGLQV from the falling edge of G, provided that E has been low (V1J and addresses have been valid for at least tAVQV-tGLQV'
3. tEHQZ, tOHQZ is specilied Irom G or E whichever occurs lirst.
4. All timing units in nanoseconds (ns).
r------~-----,II
READ TIMING DIAGRAM
~ ..
I"-
ADDRESSES
J(
ADDRESSES
VALID
\I
~
tELQV
~/
\.
_
I - tOLQV OUTPUT
\.\\~
•
~VQv
4-43
t EHQZ, _
tOHQZ
IIIII}
HIGHZ
•
/
VALID OUTPUT
tAXQX-
\\
II
-
HIGHZ
16K (2K x 8)EEROM
R5213/2816
AC CHARACTERISTICS DURING WRITE/ERASE
Symbol
....
Parameter
0(1)
Mln.(')
Maximum. ~ndurance
Typ.
Units
Max.
10.000
cycles/byte
Address to W Set,Up Time
150
ns
E to W Set-Up Time
150
ns
Data to W Set-Up Time
0
ns
Write Enable Pulse Width
R5213
R5213H
9
tWHEH(2)
Write Recovery Time
50
tGHWL.
G Write/Erase
0
ns
tWHGX
G Write/Erase Hold Time
0
ns
tpF(3)
Vw Fall Time
5
ns.
t AvwL
t ELwL
,
tOVWL
tWHDX
10
Set-Up Time
ms
ms
70
20
1
ns
Notes:
1. Maximum endurance, 0, is the number of write and erase cycles/byte.
2. tWHEH (min) ~ 50 ns when in the High Voltage W/E Mode only. When in the TTL W/E Mode, tWHEH (min) ~ 700 ns.
3. t PF applies only when in the High Voltage W/E Mode.
4. Test Conditions: Output Load: 1 TTL gate and C L ~ 100 pF; Input Rise and Fall Times: '" 20 ns; Input Pulse Leve.ls: 0.45V to 2.4V; Timing
Measurement Reference Leliel: Inputs; 1V and 2V, Outputs: O.BV and 2V
BYTE ERASE OR BYTE WRITE TIMING DIAGRAM
~
ADDRESSES
~leLWL
--
~-
-
-
-
-
I
'!:;r- I\
I
tpF
\ -
IWHEH_
!
w
\
•
DQG-DQ7
(WRITE)
C
ADDRESSES VALID
t AVWL
V
I WHAX
..IDVW~~I - IWLwH- - I-'tWHDX "
HIGHZ
DATA VALID
V IH
DQG-DQ7
HIGHZ
(ERASE)
G
j7
\.
I
I - - tWHGX
-tGHWL-
NO EFFECT
--
rl
.~NO EFFECT
.
4-44
R5213/2816
16K (2Kx8)EEROM
CHIP ERASE TIMING
ADDRESSES
~
)(
NO. EFFECT
\ I.
E
/
t ELWL
twHEH
:.:j
G
V'H
Vi
tWLwH
II
V'H
V'H
DQQ-DQ7
HIGHZ
I DVWL
I WHDX
4-45
16K (2K x8) EEROM
R5213/2616
DEVICE OPERATION
A characteristic of all EEROMs is t~at the total number of write
and erase cycles is not unlimited. The R5213 has been designed
for applications requiring up to 10,000 write and erase cycles
per byte. The write and erase cyCling characteristic is completely byte independent. Adjacent bytes are not affected during
write/erase cycling.
The Rockwell R5213/2816 has six modes of operation (see
Table 1) and except for the chip clear mode it requires only TTL
.
inputs to operate these modes.
To write a particular location of the R5213, that byte must first
be erased. A memory location is erased by enabling the R5213
wnh Chip Enable at a TTL low, bringing Write Enable to a TTL
low while Output Enable is a TTL high, and TTL highs (logical
1'5) are being presented to all the I/O lines. The erase operation
requires 9 ms. A write operation is the same as an erase except
true data is presented to the I/O lines.
After the device is written, data is read by applying a TTL high
to W, enabling the chip, and enabling the outputs. Data is available t Evav time after Chip Enable is applied or t Avav time from
the addresses. System power may be reduced by placing the
R5213 into a standby mode. RaiSing Chip Enable to a TTL high
will reduce the active power by over 60%.
The R5213 is compatible to prior generation EEROMs which
required a high voltage Vppforwriting and erasing. In the R5213
there is an internal dual level detection circuit which allows either
a TTL low or 21 V V pp to be applied to W to execute an erase
or write operation. The R5213 specifies no restriction on the
rising edge of Vpp.
COMPATIBILITY
The R5213/2816 is 100% compatible with the Seeq 5213 and
the Intel 2816A and, except for the VG (G Chip Erase Voltage),
is also 100% baCkward compatible to the Intel 2816 which
requires high voltage for byte erase/write.
For certain applications, the user may wish to erase the entire
memory. A chip clear is performed in the same manner as a
byte erase except that Output Enable is between 14V and 22V.
All 2K bytes are erased in less than 10 ms;
Table 1. Mode Selection (Vee = 5V :t 10%)
Table 1.
~
Mode
Mode Selection
-
w (Vpp)
E
G
(18)
(20)
(21)
DQO-DQ7
(9-11, 13-17)
Read(1)
V ,L
V ,L
V ,H
DouT
Standby(1)
V ,H
No Effect
V ,H
High Z
Byte Erase (2)
V ,L
V ,H
V ,L
Byte Write(2)
V ,L
V ,H
V ,L
Chip Clear(2)
V ,L
VG
V ,L
Write/Erase Inhibit
V ,H
No Effect
No Effect
= V ,H
D'N
D'N
D'N
= V ,H
High Z
Note:
1. y!'may be from V ,H to 6V in the read and standby mode.
2. W may be at V ,L (TTL W/E Mode) or from 15V to 22V (High Voltage W/E Mode) in the byte erase, byte write, or chip clear mode.
3. No Effect = No effect on selection/enable logic, however, no voltage greater than logic levels shall be applied.
4-46
16K (2K x 8)EEROM
R5213/2816
POWER UP/DOWN CONSIDERATIONS
Care must be taken to prevent an unintentional write (or erase)
cycle during power-up or power-down. These cycles can be
prevented by applying a signal level of V ,H to W (pin 21) whenever Vee is greater than 2.75 volts. When Vee is 2.75 volts or
less, the device cannot perform a write (or erase) cycle.
the R5213 Vee. When this Vee is outside the normal operating
range (4.5 to 5.5 volts), the system power status signal (shown
in Figure 1) should be low. Under these conditions, the open
collector NAND. gate and the 470 ohm resistor protect against
an unintentional write (or erase).
Figure 1 shows a suggested circuit which can be used for powerup or power-down conditions. The power supply used for the
470 ohm pull-up resistor should be the same supply used for
Vee
7403
W
470 OHM
(±5%)
124
Vee
~
21
Vi
POWER
STATUS
Figure 1.
R5213
Typical Power Monitor Circuit
4-47
16K (2K x 8) EEROM
R5213/2816
PACKAGE DIMENSIONS
24-PIN CERDIP
T
i
0.557 ± 0.042
L,-,rTT"TT"ITT'rM'"lT"rT'I"T'T"T'T"""'''''' (14.15
I
1.07)
I
1.260:t 0025
(3200 ± 064)
Ti~~lnT
004:1::00:01
(1 01 :!: 0 50)
.----j
0100:1:0.010
(254 ± 025)
t-
L
~
0160% 002
a.StO:!: 0.01
(4.06:t 050) I~ (15.49:% 025)::::J
I..Y.
~r0.018:1:0002
(045
0.055
:t:
(1.39
± O,2n)
:t
0125 MIN
(3.17)
0 OS)
0.008
DIMENSIONS IN INCHES AND (MILLIMETERS)
4-48
~
... ~,
0660:1:004
(16.76 :t 1 01)
~
R52B33
Memory Products
'1'
Rockwell
64K (8K
X
R52B33
8) ELECTRICALLY ERASABLE ROM
FEATURES
•
•
•
..
The R52B33 is ideal for appHcations requiring a, nonvolatile
memory.wtth in-system write and erase capabiltty. Tl;tese features make possible dynamic reconfiguration, I.e., operating
software is altered in real time. Possible applications are instrument/machine self calibration, pl"()grammaple character generators, table look-up updates over telephone 'lines, and controlling
autol'11oiive fuel/air ratio.
Input latches
8192 x 8 organization
Single 5V ± 10% sl;lpply
TTL byte erase/byte write
• 9 ms byteeraselbyte write
• 10,000 erase/write cycles per byte
II
• Chip clear
• Fast access times: 200 ns, 250 ns,300 ns
and 350 ns (max.),
• Infinite number of read cycles
• JEDEC approved pinout
• Pin compatible With Seeq 52833 EEPROM
AD-A12 0+----\
MEMORY
ARRAY
ORDERING INFORMATION
Part Number:
Fl52B33
--
LPa~~;;p
Access Time:
2=2OOns
25 = 250 ns
3 = '300 ns
35 = 350 ns
'DQO-D07
L-~-Model
No Letter
H
R52B33 Block Diagra~
= 9 rns Byte WritelErase
= 1 rns Byte Write/Erase
CC
A12
A7
A6
AS
A4
A3
DESCRIPTION
The Rockwell R52B33 is a 64K (8192 x 8 bits) 5 volt electrically
erasable read-only-memory (EEROM). The device operate on
5 volt,Jrl,. levels in the read, write and erase modes.. The
R52B33also has a chip clear mode in which the entire memory
is erased in a single IilraS(lcycle: The device performs chip clear
with a TTL.h!9h level signal applied, to G and a TTL low level
applied to CC. The erasure time for both chip clear and byte
erasure is under 10 ms.
A2
A1
AO
DOO
001.
002
GND
Data, addresses, E, CC, and G are latched on the leading edge
of iN. The system controller needs only to maintain the Vii signal
during the erase/write cycle after the latches are activated.
Once written, which requires under 10 ms, there is no limtt to'
the nur'nbefof times that the data.may be read. Each byte may
be erased and written at least 10,000 times.
2
3
4
5·
8
7
I
9
10
11
12.
13
14 .
21
27
28
25
24
23
22
21
20
19
16
15
vee
W
NC
AI
A9
A11
G
A10
E
007
DOS
D05
DQ4
D03
R52B33 Pin Configuration
Document No. 29000M15
4-49
Data Sheet Order No. MM15
Rev. 1, March 1984
64K (8K x 8) EEROM
R52B33
AO-AI2
OPERATING CONDITIONS
ADDRESSES
E
CHIP ENABLE
Parameter
All Modes
G
OUTPUT ENABLE
Vcc Supply Voltage
5V ± .10%
W
WRITE ENABLE
Temperature Range
o to 70°C
DOO-D07
DATA INPUT (WRITE OR ERASE)
DATA OUTPUT (READ)
CC
CHIP CLEAR
N/C
NO CONNECT
R52B33 Pin Names
ABSOLUTE MAXIMUM RATINGS·
Parameter
Symbol
Value
Supply Voltage
Vcc
-0.5 to +7.0
Vdc
Input Vonage
VIN
-0.5 to.+ 7.0
Vdc
Output Voltage
VOUT
-0.5 to +7.0
Vdc
Temperature Under Bias
TA
-10to+80
°C
Storage Temperature
T STG
-65 to +100
°C
'NOTE: Stresses above those listed may cause permanent
damage to the device. Thill is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Unit
DC CHA.RACTERISTICS
Vcc
= 5.0V ::±:
10%, TA
Symbol
= O°C to 70°C (unless otherwise specified)
Parameter
Min.
Typ.(2)
Max.
Test Condltlons (1 )
Unit
=
liN
Input Leakage Current
±10
p,A
VIN
10
Output Leakage Current
±10
p,A
VOUT
IWE
Write Enable Leakage
Read Moce
10
p,A
10
p,A
W= VIH
W = VIL
W/E Mode
10
p,A
W
= VIL
18
40
mA
E
60
110
mA
E
= V'H
= G = VIL
O.B
V
Chip Erase Moce
ICCl
Vcc Standby Current
ICC2
Vcc Active Current
V,dDC)
Input Low Vonage (DC)
-0.1
V,dAC)
Input Low Voltage (AC)
-0,4
VIH
Input High Voltage
Vw
WRead Voltage
W Write/Erase Vonage
VOL
Output Low Voltage
V OH
Output Hig h Voltage
CIN
Input Capacitance
COUT
Output Capacitance (3 )
CVcc
Vcc Capacitance (3 )
CVw
Vw
V
Vee + 1
V
2.0
Vee + 1
V
-0.1
0.8
V·
0,45
V
10L
V
10H
2.4
5
Max.
Time = 10 ns
2.0
Capacitance (3 )
Vcc Max.
= Vcc
= 2.1 mA
= -400,.,.A
Vcc = 5.0V. chip deselected. pin
under test at OV, T A = 25°C, I =
1 MHz
10
pF
10
pF
500
pF
G = E = VIH
10
pF
G = E = VIH
Notes:
1. Test Conditions: Output Load: 1 TTL gate and C L = 100 pF: Input Rise and Fall Times:'" 20 ns; Input Pulse Levels: 0.45Vto 2,4V; Timing
Measurement Relerence Level: Inputs: 1V and 2V. Outputs: O.BV and 2V
2. Typical values are lor T A = 25°C and nominal supply voltages
3. This parameter is periodically sam pled and is not 100% tested.
4-50
R52B33
64K (8K x 8) EEROM
AC CHARACTERISTICS DURING READ
Symbol
Parameter
RS2B33-20
R52B33-25
RS2B33-30
Min.
Min.
Min.
Max.
Max.
R52B33-35
Max.
Min.
Max.
Unit Test Condltions(1)
t AVO "
tELQV
Address to Data Valid
200
250
300
350
ns
E
Chip Enable to Data Valid
200
250
300
350
ns
(!
tGLQV(2)
Output Enable to Data Valid
tEHOZ.
tGHQZ(3)
Output 'Enable to High Impedance
t AXQX
Output Hold from Address. Chip Enable.
or Output Enable. whichever Trans~ion
Occurred First
= G = V'L
= V,L
10
80
10
90
10
100
10
100
ns
E
= V,L
0
60
0
70
0
80
0
80
ns
E
= V'L
0
ns
E = G = V'L
0
0
0
Notes:
1. Test Conditons: Output Load: 1 TTL gate and CL = 100 pF; Input Rise and Fail times: :s20 ns; Input Pulse Levels: 0.45V to 2.4V; Timing
Measurement Reference Level: Inputs: 1V and 2V. Outputs: 0.8Vand 2V
2. G may be delayed up to IAVQv-tG.l.9V after the falling edge of E without impact on tAVQV ' Data is available at the DO outputs after a delay
oflQLov from the lalllng edgj! ~ G •.,provided that E has been low (V,J and addresses have been valid for at least tAVOV-tGLOV'
3. tEHOZ• IGHQZ Is specified from G or E whichever occurs first.
READ tiMING DIAGRAM
ADDRESS ES
~
f-
~K
ADDRESSES
VALID
\I
~
/
teLQV
~/
teHQZ
-~HQZ-
I - tGLOV -
I I I I iJ
\\\\\,
HIGH Z
OUTPUT
•
.
t AVQV
4-51
VALID OUTPUT
tAXQX-
\\
II
I-
...
HIGHZ
II
64K (8K x 8) EEROM
R52B33
AC CHARACTERISTICS DURING WRITE/ERASE
R52B33-35
Min.
Parameter
Symbol
0(1)
Maximum Endurance
tAVWl
E, G or Address Setup to W
tOVWl
Data Setup to W
tWLDx'2)
W to E, G, Address or Data Change
tWlWH
Write Enable, W, Pulse Width
R52833
Max.
50
ns
0
ns
50
ns
10
1
W to Mode Change (Write Recovery Time)
Unit
cycleslby1e
9
R52833H
tWR(3)
Typ.
10,000
50
70
ms
20
ms
ns
Notes:
1. Maximum endurance, Q, is the number of write and erase cycles/by1e. The endurance 0.1 the R52833 is guaranteed to be at least 10,000
cycleslby1e.
2. After tWlDX hold tim~from W, the inputs E, G, Address and Data are latched and are "No Effect" until tWR' Write Recovery Time, after
the trailing edge of W.
3. The Write Recovery Time, tWR, is the time after the trailing edge of Wthat the latches are open and able to accept the next mode set·up
conditions. Reference Table 1 (page 6) lor mode control conditions.
BYTE ERASE OR BYTE WRITE TIMING
I
K
NO EFFECT
I
f\
/
NO EFFECT
~(
ADDRESSES
VALID
I
I
I
I
I
I
I
I
I
I
V
~~
tAVWl;--
I
NO EFFECT
I
I
I
I
t WlwH
I
1
I
1\
"L
IWLox
tOVWlr. DOD-DQ7
(WRITE)
OQD-DQ7
(ERASE)
fllGHZ
)
HIGHZ
VALID
K
I-tWR-J
1
NO EFFECT
I
\
I
1
1
NO EFFECT
I
I
I
1
1
1
""1.----- BYTE ERASEIWRITE PERIOD -----rl!-START OF NEXT MODE
4-52
RS2B33, '
CHIP. ERASE TIMING
I
, -_ _~_ _ _ _ _...-_.:....~_ _...-_ _~i.::
NO EFFECT
NO'EFFECT
! - - - - - - IWLWH
-----!
II
I
I
I
I,
I
I
iii
I
IWR~
OQG-OQ7
.1
HIGHZ
f
1--~""'-'"----cHIP ERASE .P/aRIOO "":-----.,.....--'--'-~
.. I........
· START OF NEXT MOP•
. 1;.
.
i\,.
4.53
'.
".' . ~
64K (8K x 8) E'EROM
R52B33.
DEVICE OPERATION
The Rockwell R52B33 has six modes of operation (see Table
1). The control signals that determine these modes are TTL
compatible.
tOVWL' All of these cpntrol inputs together ,with the address and
data lines are latched on the 1~lIing edge Olw' After tWLOX they
may be removed and the next Condition established while the
byte is being erased or written. This effectively increases the
write speed. After t wLWH , W may be returned to the TTL high
level and the next operation begun tWR after the rising edge of
the pulse.
The chip clear and byte erase time is 10 ms.
READ
A read is accomplished by presenting the address of the desired
byte to the Column and Row Address inputs with AQ as the LSB.
Once the address is stable, Eis brought low in order to enable
the chip f!iN must be at a TTL high during the entire read cycle).
The output drivers are made active by bringing IT to aTTL low.
Data is valid t ELOV after E or IaLOv after G is low. The latches
are transparent in the read mode.
CHIP CLEAR
The chip clear is performed by taking CC and E to a TTL Ic;>w
level and IT to a TTL high voltage level. The order in which the
controls are set does not matter, only that they are stable lor
!AVWL before W goes low. The I/O and the address inputs are
No Effect. After the control and data inputs are stable, take
W low. This latches all control and data inputs and, after tWLOX
all inputs with the exception pi IN become No Effect. IN must
be maintained at a low level for·the duration 01 the chip clear
cycle and then return it to a high level. Another mode of operation may be started tWR after W is stable. The memory has,
now been returned to its clear state and contains all 1's.
.
STANDBY
The, power dissipation of the chip may be reduced by1aking E'
,to a TTL high between operations. This lowers Po by over 60%.
BYTE ERASE/BYTE WRITE
POWER UP/DOWN CONSIDERATIONS
,Each byte of the memory may'be individually erased or written
with TTL level pulses. The two operations have the same timing
and specificaticnssiriCt!;' the byte erase is performed by Writing
all highs (HEX FF) to the selected byte. This restores the byte
to its clear state of logical one., The byte erase is' performed by
presenting the device with E ata logical low and G·at a logical
high after the address is stable., These, controls must be, stable
for t AVWL before Wis..taken .active. The data must be stable for
Table 1.
~
Mode
Internal circuitry on alt,devices g\Jard agaios.t ,ir]advertent programm'ing pi bits during times when Vee is below the normal
operating voltage. The device outputs will remain in high impedance and the writ~/erase circuitry disabled as long as W is kept
at,VIL.Normal opetation, as outlined in Table 1, can begin only
after W has been taken to V IH.
Mode Selection (Vee
E
cc
(20)
(1)
=5V ± 10%)
G
(22)
W
(27)
DQO-DQ7
(11-13, 15-19)
Read!i)
VIL
VIH
VIL
VIH
DouT
Standby(1)
VIH
No Effect
No Effect
No Effect
HighZ
VIL
VIH
VIH
VIL
VIL
ViH
VIH
VIL
DIN
Byte Erase
ByteWrHe
-
DIN
~
V IH
Chip Clear
VIL
VIL
VIH
VIL
DIN ~ 'VIH
Write/Erase Inhibit
VIH
No Effect
No Effect
No Effect
High Z
Note:
1. IN may be from VIH to 6V in the read and standby mode.
2. No Effect ~ No effect on selection/enable logic, however, no voltage greater than logic levels shall be applied.
4-54
A52B33,
64K (8K x 8) EE,ROM
MICROPROCESSOR INTERFACE CIRCUIT EXAMPLE FOR BYTE WRITE/ERASE:
A D D R E S S . - - - - - - - - - - - - ' - - - - - - - - - - - - - - " J Ao-A12
BUS
~---_------------_dG
SYSTEM RESET
),>------jr---,------+<'I'
MEMORY RESET >,>-,-------'->----4~--;-''"l.....-'
MEMORY WRllE>
)O-+-+-----'--'----L
EEROM
R52B33
CHIP SELECT >>_-------------------~E
DATA BUS
¢===================~ DQO·DQ7
NOTE:,
ALL SIGNALS MUST SATISFY THE RELATIONSHIPS INDICATED
BY THE TIMING DIAGRAMS SHOWN ON PAGES 3, 4 AND 5.
EEROMSELECT IS DERIVED FROM THE CHIP SELECT
SIGNALS OF ALL DEVICES FOR WHICH THIS CIRCUIT GATES
W. THIS MAY ENTAIL A SIMPLE OR FUNCTION. IN CASE OF A
SINGLEEEROM, ,THE TWO SIGNALS WOULD BE, COMMON.
TYPICAL EEROM WRITE/ERASE ROUTINE
WAIT SUBROUTINE
ISSUE
MEMORY READ
COMMAND'"
TOt:EROM
INITIALIZE
COUNT
EXECUTE
WAIT
SUBROUTINE
DECREMENT
COUNT
ISSUE
, MEMORY WRITE
,
COMMAND
TOEEROM
4·55
II
R52B33
64K (8K x 8) EEROM
PACKAGE DIMENSIONS
MILLIMETERS
28-PIN CERDIP
I::::::::::::::II
-Ir-D
K
MAX
MIN
MAX
A
36.32
1.430
1.470
B
12.95
37.34
13.46
0.510
0.530
C
3.68
0.41
4.19
0.51
0.145
0.Q16
0.165
0.020
1.27
1.52
2.54 Bse
0.050
F
J
--jGr-
MIN
D
~mXl~mM~ilf::~.~·
~
.. .=n
I - L---I
4-56
INCHES
DIM
G
J
J
K
0.20
0.20
L
3.18
16.13
M
15.24
N
0.89
0.30
0.30
4.19
17.41
15.75
1.14
0.060
0.100Bse
0.008
0.012
0.008
0.012
0.125
0.165
0.635
0.685
0.620
0.600
0.035
0.045
R2816A and R5516A
Memory Products
'1'
Rockwell
R2816A and R5516A
16K (2K x 8) LATCHED EEPROM WITH TIMER
ORDERING INFORMATION
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Part Number: R2816A __ _
R5516A __ _
High endurance erase/write cycles
- 1,000,000 cycles per byte (R5516A)
- 10,000 cycles per byte (R2816A and R2816AH)
5 volt-only operation
On-chip latches for direct microprocessor bus interface
On-Chip timer for self-completed byte erase and write
Fast byte write cycle
- 2 ms write (R2816AH)
- 10 ms write (R2816A and R5516A)
Fast access time: 250 ns, 300 ns, 350 ns (max.)
TTL voltage level controlled modes
- Byte read
-Byte write with automatic byte erase
- Read/write inhibit
Optional high voltage controlled modes
- Byte erase
- Byte write
- 9 ms chip clear
Power up/down protection circuitry
Low power operation
- 110 rnA (max.) active current
- 40 rnA (max.) standby current
JEDEC approved 24-pin byte-wide pinout
Direct replacement for 2K x 8 EEPROMs
- 21V 2816
-5V 2816A and 5516A
AO-A3
Access Time
25 = 250 ns
L
3=300ns
35 = 350 ns
Byte Write time
H - 2 ms (R2816AH only)
No letter = 10 ms
"--------_-----l
DESCRIPTION
The Rockwell R2816A and R5516A are 16K (2K x 8) electrically
erasable programmable read-only memory (EEPROM) devices
with on-<:hip latches and write timer. EEPROMs allow non-volatile
storage of data when power is off and in-circuit reading and
writing of data when power is on.
The R2816A and R5516A both operate with TTL level signals
and a 5-volt power supply. The endurance, the numbero! times
that a byte may be written to a particular location, is 1 million
for the R5516A and 10 thousand for the R2816A. Once written,
there is no limit to the number of times that the data may be read.
Both EEPROMs have an internal timer that automatically times
out the write time. The on-chip timer, along with the latching of
address and data lines, allows the EEPROM to complete write
operation independently of the MPU. After executirig a write
COLUMN
ADDRESS
DECODE
COLUMN
ADDRESS
LATCHES
ROW
ADDRESS
DECODE
A4-A10
MEMORY
ARRAY
r-_.......::t:.....:L:,;A;.:,T.:,CH:; ENABLE
Vi
E
,..---'-----.
TIMER
CONTROL
LOGIC
R2816A and R5516A Block Diagram
Data Sheet Order No. MM17
March 1984
Document No. 29000M17
4-57
II
l
•
16K (2K
R2816A and R5516A
instruction to the EEPROM, the MPU is thus free to continue
other computational tasks without delay or interruption required
by earlier generation EEPROMs. The write operation is completed automatically, taking only 10 ms for the R2816A and
R5516A, or only 2 ms for the faster R2816AH. A separate erase
cycle is not required and the Write Enable
pulse width
requirement is only 150 ns (max.).
A7
rJi)
The R2816A EEPROM is the cost-effective choice for applications requiring infrequent updating of non-volatile data, i.e., no
more than 10,000 updateslbyte. The R5516A is ideal for designs
employing frequent update of data.
x 8) EEPROM
24
VCC
A6
2
23
A8
AS
3
22
A9
A4
4
21
Vi
G
A3
5
20
A2
6
19
A10
A1
7
18
E
AO
8
17
DQ7
DQO
9
16
DQ6
ADDRESS
DQ1
10
15
DQ5
CHIP ENABLE
DQ2
11
14
DQ4
G
OUTPUT ENABLE
GND
12
13
DQ3
W
WRITE ENABLE
AO-A10
E
000-007
DATA INPUT (WRITE OR ERASE)
DATA OUTPUT (READ)
R2816A and R5516A Pin Names
R2816A and R5516A Pin Configuration
ABSOLUTE MAXIMUM RATINGS·
Parameter
Symbol
Supply Voltage
Value
Unit
Vee
V IN
-0.5 to +7.0
Vdc
Input Voltage
-0.5 to +7.0
Vdc
Output "oltage
VOUT
-0.5 to + 7.0
Vdc
Temperature Under Bias
T STG
-10 to +80
·C
Storage Temperature
TSTG
-65 to + 100
·C
W Level in Optional
High Voltage Byte Erasel
Write and Chip Clear Modes
Vw
-0.5 to +22.5
Vdc
W or G Max. Duration at 22V
tw,tG
24
Hrs
G Level in Optional
HV Chip Clear Mode
VG
-0.5 to 22.5
°NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in the other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
OPERATING CONDITIONS
Vdc
Parameter
All Modes
Vcc Supply Voltage
SV ±10%
Temperature Range
o to 70·C
DC CHARACTERISTICS
(Vee =5.0V ±10%, TA = OOC to 70°C (unless otherwise noted)
Symbol
Parameter
Teat Condltlonsl
Unit
10
,.A
V IN = S.5V
Output Leakage Current
10
Write Enable Leakage Current
10
p.A
p.A
W
Input Leakage Current
lOUT
Iw
Min.
Typ.2
Max.
liN
IG
Output Enable Leakage Current
ICCI
Vcc Standby Current
18
40
"A
mA
Icc2
Vee Active Current
60
110
mA
V IL
Input Low Voltage
-0.1
0.8
V
V IH
Input High Voltage
2.0
Vw
W Input High Voltage in Optional
HV Byte Erase/Write and HV Chip
Clear Modes
12
22
V
VG
G Input High Voltage in
Optional HV Chip Clear Mode
12
22
V
VOL
V OH
Output Low Voltage
0.45
V
Output High Voltage
10
+1
Vec.
2.4
C IN
Input Capacitance3
7
pF
C OUT
Output CapacitanceS
10
pF
4-58
G
E
All 110 lines open, other inputs
= S.SV
E = G = VIL
All 110 lines open, other inputs
= 5.5V
V
V
Notes:
1. Test Conditions: Output Load: 1 TTL gate and C L = 100 pF; Input Rise
and Fall Times: ,,20 ns; Input Pulse Levels: O.45V to 2.4V; Timing
Measurement Reference Level: Inputs: IV and 2V, Outputs: 0.8V and 2V
= S.SV
= Vw
= VG
= VIH , G = VIL
VOUT
= 2.1 mA
= - 400 p.A
Vcc = 5.0 V, chip deselected, pin
under test at OV, TA = 25·C, f = 1 MHz
IOL
IOH
2. Typical values are for TA = 25·C and Vee = 5.0V.
3. This parameter is periodically sampled and is not 100% tested.
16K (2K x 8) EEPROM
R2816Aand R5516A
Applying a TTL low to the VIi input of the selected EEPROM (E
low) with the outputs disabled (G high) initiates the bl!,e wr~
cycle. The address is latched on the falling edge of W (or E,
whichever occurs later) and the data is latched on the rising edge
of VIi (or E, whichever occurs first). The EEPROM uses ihe
internal timer to automatically complete the byte erase and write
operation without intervention from the MPU.
EEPROM OPERATION
The Rockwell R2816A and R5516A EEPROMs have four modes
of TTL level controlled operation (Table 1) and three optional
high voltage level controlled modes (Table 2). The standby, byte
read, byte Write,and write/read inhibit modes are controlled by
TTL levels on the Chip Enable (e), Output Enable (G) and Write
Enable
inputs. These modes support operations in costsensitive designs whiml minimal supporting circuitry is required.
rN>
WRITE OR READ INHIBIT
the optional high voltage controlled modes allow R2816A1
R5516A operation in circuits designed for earlier generation
EEPROMs. A high volta,ge (12-22V) on VIi supports separate
byte erase and byte write operations required by prior EEPROM
designs. The chip clear mode requires high voltage inputs on
two control pins
andG).
Applying a TTL low to E with both G and VIi held at TTL high
enables the EEPROM but inhibits both reading from, and writing
to, the device.
rN
OPTIONAL HIGH VOLTAGE
CONTROLLED MODES
TTL LEVEL CONTROLLED MODES
HV BYTE ERASE OR BYTE WRITE
BYTE READ
The high voltage byte erase or write mode operates the same
as the TTL level controlled byte write mode with the following
exceptions:
The byte read mode drives the data line outputs (000-007) with
the contents of the EEPROM byte located by input address lines
AO-A10. Read access time is 250 ns or less (R2816A-25/
R5516A-25).
1. The. active W voltage level is 12-22V rather than TTL low.
2. A separate byte erase cycle must be performed with all data
bits set to 1 (data lines are TTL high) prior to the byte write
cycle.
A byte is read by stabilizing address lines AO-A10, applying a
TTL low to E to enable the device, and applying TTL low to G
to enable the data output drivers. Output data is valid on
DOD-DO? after tAvov, tELOV, or tOLDV time, whichever is
limiting. VIi is held at TTL high throughout the cycle.
HV CHIP CLEAR
The chip clear mode erases all data in the R2816A1R5516A to
the 1 state (TTL high) in 10 ms.
STANDBY
The standby mode reduces R2816A1R5516A power dissipation
by over 60% (maximum ICC drops from 110 mA to 40 mAl.
When the device is !lnabled, raiSing Wand G to a high voltage
level (12-22V) initiates the chip clear mode, Dropping W below
the high voltage minimum level terminates the mode. The data
lines must be held at TTL high.
A TTL high on E places the R2816A1R5516A in the standby mode
regardless of the G or VIi input levels. The data output lines are
in a high impedance state in this mode.
BYTE WRITE
POWER UP/DOWN WRITE PROTECTION
The TTL controlled byte write cycle performs both a byte erase
(all bits are written to the 1 state) and a byte write (all bits are
written to the input data line states) in the same write cycle. A
separate, preceding byte erase cycle is not required.
Table 1.
Internal Circuitry protects the R2816A1R5516A against a false
write during vee power application or removal. This Circuitry
prevents writing under any of the following conditions:
1. vee is less than 3V.
2. A negative transition on
between 3V and 5V.
TTL Modes Selection
VIi
does not occur when
vee
is
Control Pins
Chip
Select
Output
Enable
Write
Enable
Mode
tE)
CGI
(W)
I/O Data
Lines
(DQO-DQ7)
Byte Read
Standby
Byte Write
Write/Read Inhibit
VIL
VIH
VIL
VIL
Vil
No Effect
VIH
VIH
V IH
No Effect
VIL
VIH
DOUT
High Z
DIN
High Z
Table 2.
Optional High Voltage (HV) Modes Selection
Control Pins
Chip
Select
Note: No Effect = No effect on logic selection, however, no voltage
level other than TIL levels shall be applied.
4-59
Output
Enable
Write
Enable
Mode
(El
(Gl
(W)
I/O Data
Lines
(DQO-DQ71
HV Byte Erase
HV Byte Write
HV Chip Clear
Vil
VIL
Vil
V IH
V IH
VG
Vw
Vw
Vw
VIH
DIN
VIH
II
R2816A and R5516A
16K (2K
x 8) EEPROM
AC CHARACTERISTICS
= OOC to 70°C (unless otherwise specified)
Vee =5.0V ±10%. TA
BYTE READ
Limits (ns)
R55l6A-25
R2816A-25
Parameter
Min.
tAvAX
Read Cycle Time
250
tELOV
Chip Enable (E) Access Time (tc .)
250
tAVOV
Address Access Time (tACe!
250
tGLOV
Output Enable (G) Access Time (toEl
tEHOZ
E to Outputi.n High Z
tGHOZ
tAXOX
t pu
E Low to Power-Up Time
tpo
EHigh to Power Down Time
Symbol
R55l6A-3
R28l6A.-3
Max.
Min.
R2816A-35
Max.
300
....
90
Min.
Max.
Units
ns
350
300
350
ns
300
.350
ns
100
100
ns
10
100
ns
10
100
ns
10
100
10
100
G to Output in High Z (t OF)
10
100
Output Hold Irom Address Change (toH)
50
50
10
100
50
ns
0
0
0
ns
50
50
50
ns
Notes:
1. Test Conditions: Output Load: 1 TTL gate and CL = 100 pF; Input Rise and Fall Times: ,,;20 ns;lnpurPulse Levels: 0.45V to 2.4V;
Timing Measurement Reference Level: Inputs: 1V and 2V. Outputs: O.SV and 2V.
2. G low may be delayed up to t.GLO V a!!,er tl!.e falling edge of E without impact on tAVOV '
3. t.Hoz. and tGHOZ are specified from G or E high whichever occurs first.
BYTE READ WAVEFORMS
~------------tAVAX--~----------~
AO-Al0
(ADDRESS)
ADDRESS VALID
ADDRESS VALID
V1H
W--~---+-----------+---------+-------------r----~~------+-----DQO - DQ7
(DATA OUT)
HIGH Z
----+-----++-E-+f_
DATA VALID
~
~-----r~~.~
~
HIGHZ
~-------------------------------------tll:-l-----
4-61
II
R2S16A and R5516A
16K (2Kx 8) EEPROM
HIGH VOLTAGE BYTE ERASE/WRITE TIMING
Symbol
Parameter
Min.
Typ.
Max.
Unit
Address Valid to W HV Setup Time (tAs)
150
ns
tELWV
E Low to W HV Setup Time (lcs) .
150
ns
~HWV ..
G High to W HV Setup Time
0
ns
tovwv
Data Valid to W HV Setup Time (toS> .
0
ns
twvwx
W HV Pulse Width
9
tWF
W Fall Time
5
I's
IWHGX
G Hold Time
0
ns .
tAVWV.
10
70
Test Conditions
W
~
6V
W
~
6V
ms
tWHOX.
Data. Hold Time (tOH )
50
ns
I.
W
~
6V·
tWHEH
W Recovery :rime (tWA)
50
ns
I
W
~
6V
twHAX
Address Hold Time
50
ns
W
~
6V
HIGH VOLTAGE BYTE ERASE/WRITE WAVEFORMS
AO-Al0
(ADDRESS)
ADDRESS VALID
E
twvwx
Vw
W
V'H
000-007
(DATA IN)
000-007 .
(DATA OUT) ,
HIGH Z
DATA VALID
HIGH Z
V'H
HIGH Z
HIGH Z
4-62
R2816A and R5516A
16K (2Kx 8) EEPROM
HIGH VOLTAGE CHIP CLEAR TIMING
Symbol
Min.
Parameter
Typ.
Max.
Unit
Test Con'dltlons
tELWV
E Low 10 W HV Setup Time ('cs)
IGVWV
G HV to
tOHWV
Iwvwx
W HV Pulse Widlh
9
tWF
W Fall TIme
5
JIB
W
tWHGX
G Hold Time
10
ns
W
t WHOX
Data Hold Time (IoH)
50
ns
W = 6V
tWHEH
W Recovery Time (tWA)
SO
ns
W = 6V
10
ns
Vii HV Selup Time
10
ns
Dala High 10 W HV SetupTime (los)
0
ns
10
70
ms
= 6V
= 6V. G
= 12V
r---------B
HIGH VOLTAGE CHIP CLEAR WAVEFORMS
I+-----twvwx ' - - - - - I
Vw
DQO-DQ7
(DATA IN)
•
4-63
R2816A and
R~516A
16K (2K x 8) EEPROM
.
PACKAGE DIMENSIONS
24-PIN CERDIP
T
0.557
~
0.042
"'r:I"n"I'T"I'Tn"tTtTtT1:l"t:l"t:M::rII
I
I
1260 ±0.025
(32 00 ± 064)
L 0610~
~
0.160:t 0.02
001
(406:t 0.50) I~ (15.49!t; 0 25) ~
II .-=1=
.....~,
Timmn~t
I..t! M~!~
0.04
;!;
0.02
-j
0 100 :!:.0010
(1.01
:t
0.50)
(254
:i;
t-
025)
0.01' ± 0.002
(0.46:!: 0.05)
0.055 :t Q.OOB
".39 :!: 0.20)
DIMENSIONS IN INCHES AND (MllUMETERS)
4-64
(3.17)
0660
:!:
0 04
(16.76::t 1.01)
R2000
Memory Products
'1'
Rockwell
R2000
64x 8 NON-VOLATILE RAM
Product Preview
DESCRIPTION
FEATURES
The Rockwell R2000 Non-Volatile Random Access Memory
(NVRAM) is a conventional 64 x 8 static random access
memory (RAM) overlaid bit-for-bit with a 64 x 8 non-voltatile
electrically eraseable programmable read only memory
(EEPROM). The NVRAM combines the fast access read/write
functions of static RAM with the permanent storage capability
of EEPROM. STORE and RECALL commands, implemented
addresses to provide maximum user flexibility, initiate RAM to
EEPROM and EEPROM to RAM data transfers. In response to
the STORE command, the contents of the RAM are written into
the EEPROM within 12 ms. In response to the RECALL command, the contents of the EEPROM are transferred to the..RAM
within 7.S p.s. These commands require no additional control
lines or external circuitry to support bus operation during power
loss, thus greatly simplifying R2000 system deSign-in.
• Byte-wide 64 x 8 organization
• Single SV power supply
• Low power dissipation
- 50 mA active current
- 10.mA STORE current
- 25 mA standby current
• 10-Year data retention for each STORE
• Minimum 10,000 non-volatile STORE cycle endurance
• Microprocessor and microcontroller bus compatible
• Fillestrappable, directly compatible, bus interface configurations:
- A6500, R65COO, 6800 non-multiplexed bus
- Z80 non-multiplexed bus
- A65COO/21 , 6801 multiplexed bus
- A6500/11, R6S00/41 multiplexed bus
- 8051 multiplexed bus
as
Three inputs can be variously strapped to cause the R2000's
byte-wide parallel bus interface to operate in one of five different
bus configurations. This enables the R2000 to operate with. most
industry standard microprocessors and single-chip microcomputers with extended buses.
• Software control of non-volatile functions
- Storage protection
- STORE and RECALL operation
- No additional control lines
- Only a single external capacitor required
• Fast static RAM access time:
- 125 os (max.) for non-multiplexed bus
- 250 ns (max.) for multiplexed bus
R2000 applications include (1) saving of critical system data upon
power failure, (2) permanent storage of instrument/machine selfrecalibration ortransmittedparameters, (3) password storage,
(4) replacement of DIP switches used for system configuration,
and (S)automotive applications ranging from entry-codes to
engine performance adjustments.
• Reliable Ncchannel floating 9a,te technology
• TIL compatible
• Self-timed STORE with power-down .retention pin
BC2
BC1
A5(NC)
A4(NC)
A3(NC)
A2(NC)
A1(NC)
AG(NC)
DO(AO/DO)
D1(A1ID1)
vcc
VRR
'2(WR)
NC(AS/ALE)
E
MPX
RiW (RD)
07
06
D2(A2/D2)
D5(A5/D5)
D4(A4/D4)
GND
D3(A3/D3)
R2000 Pin Configuration
Document No. 29000M16
4-65
Product Preview Order No. MM16
March 1984
II
64 x 8 NVRAM
R2000
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
.,.,.
Value
• NOTE: Stresses above those Iist8d may cause permanent
damage to the device. This is a stress radng only and functiona'
operation of the device at these or any other condiiions above
those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximllm rating conditions
for extended periods may affect device reliability.
Unit
Supply Voltage
V cc ,,,,,
-0.3 to,<'12.0
Vdc
Input Voltage
VIN
-0.3 to +12.0
Vdc
Output Voltage
VOUT
-0.3 to +7.0
Vdc
Temperature Under Bias
TA
-10to+80
·C
Storage Temperature
T STG
-65 to +100
,~C
OPERATING CONDITIONS
~
All Modes
Paramater
Vee Supply Voltage
"
"
"SV"±S%
o to 7(j·C
Temperature Range
DC CHARACTERISTICS
tYee
=S.(lV ±5%, T... =",(lec to 70°C; unl$sS' otherwise specified)
Symbol
" ,Parameter
liN
Input Leakage Current
Typ.~
Min.
'Unlt
Max.
10
"A-
1'est Conditions 1
Vec = 5:25V
VIN = GND to ,S'25V
lOUT
Output Leakage CUrrani
10
p.A
VOUT = GND to Vcc Max,
IAA
VAA Store C~rrent '
10
rnA
V AA = Vee +OV. -O.2SV.
Vee= QV
lec1
Vee Standby Currant
2S
rnA
E
Icc2
Vec Active Current
SO
rnA
E = Vil • Vee = S.25V
VRR
VAA Supply Voltage
Vil
Input Low Voltage
VIH
Input High Voliage
VOL
Output Low Voltage
VOH
Output High Voltage
C IN
Input Capacitance
COUT
Output Capacitance3
"
4.0 '
"
5.25
V
-0'.3
0.8
V
2..0
Vcc + 1
V
0.4
V
= VIH • Vcc
= S;2SV
STORE Cycle. Vee = OV
IOl = 3.2 rnA
V
IOH = -0.3 rnA
S
pF
Vee = 5.0V. chip deselected. pin under test atOV.
150
pF
TA = 25·C. f = 1 MHz
2,4
Notes:
1. Test Conditions: Output Load: 1 TTL gate and Cl = 100 pF; Input Rise and Fall Times: s20 ns; Input Pulse Levels: O.45V to 2.4V;
Timing Measurement Reference Level: Inputs: 1V and 2V. Outputs: 0.8V and 2V.
2. Typical values are for TA = 25°C and Vcc = 5.0V.
3. This parameter is periodically sampled and is not 100% tested.
4. All units are direct current (DC) except capacitance.
4-66
R2000
64
SIGNAL DESCRIPTION
AO-AS "':'Address Lines. Th~ six addre~s inPuts select memory
x 8 NVRAM
FUNCTIONAL DESCRIPTION
The major functions in the R2oo0 NVRAM are(l) the volatile
staticR)l,M with its associated address decodll, sense and read
circuitry, write control circuitry" and input' receivers/output
drivers; (2) the non-volatile EEPROM With its associated STORE
and RECAL,Lcontrol circuit, and high voltage generator; and
(3) th~ bus interface configuration logic. A block diagram of the
R2OQO NVRA.Mis. shown In' Figure 1.
locations in RAM and initiale ,the STORE and RECALL .commands.ln a non-multiplexed bus configuration, these IInes.are
assigned to the AO-A5 pins. In a multipl~x~d bus configuration,
some, or all, of the address. inputs are s.h.ared willi th~ 00-05
data lines.
"
.
DO-D7--Data Lines. When E is LOW, the ejght bidirectional,
three-state, data lines transfer data from the R2000 RAM to the
data bus durjng a read operation, or from the data bus to the
R2000 during a write operation. When E is HIGH, the data lines
are in high impedance state. Iii a mulii'plexed bus configuration, some of the data, lines double as address lines:
vcc.
VRR
GND
a
64 )( B
EEROM
BCl
E-Chlp Enable. E LOW input enables. RAM read and write
operation, as well as STORE and RECALL initiation. When
E is HIGH, the R2oo0 is disabfed and operates in a low-power
standby mode. In the standby mode the R2000 consumes almost
50% less power than in the active mode. The data output lines
are in a high impedance state during standby mode.
BC2
MPX
,2
E
(RD)
RiW(WR)
(AS/ALE)
112(WR)-Clock/(Wrlte). This pin acts as eitherthe Clock (02)
or Write Enable (WR) input depending on bus interface
configuration. When configured for an 6500/6800 bus, 02 clocks
data in or out of the R2000 depending on'the level of RiW.
Whim configured for an Z80/8051 bus, WR. LOW (and ~O
HIGH) enables data to be written from the data lines into the
R2oo0.
AO-AS
64 )( B
STATIC RAM
RiW (BD)-ReadlWrlte (Read). This input pin serveS as either
DO-D7
Read/Write (RiW)orRead Enable (ROYdepending upon the bus
interlace configuration. When cpnfigured for an 6500/6800 bus,
RiW HIGH enables data to read from R2oo0 RAM to the data
lines, whereas RiW LOW ~nables data to be written from the
(iata IInesintq;the R2000. Whencbnfigured for an zaO/8051 bus,
RO LOW (and WR HI~H) enables data to be written from
the R2000 RAM to the data bus.
..
. (oo/AS-
OS/AS) 00"'07
be
'----.."......
Figure 1.
.
,~"
R200b' Block Dlagra~
.'
RAIlI
NC(AS1ALE)-No Connect (Address Strobe/Address Latch
Enable). This pin is used only with a multiplexed bus. A HIGH
on this pin-AS for an R6500/" bus, or ALE for the 8051 busindicates
that a valid address
exists on the data/address
lines.
.
• •
1
The 64 bytes of volatile RAM are located at addresses 0 to 3F
(hexadecimal)
decodec;lf{omaddress lines AQ...A5. L6pations
and 1 in RAM are not acC$ssible since addresses' and 1 corresp9nd to the STORE 8J1.d RECALL commands, respectively.
llle reroaining bytes are available for general read~rite access.
Table'1 .sumlT)arizes th~ memory map and.the command
operations',
as
o
and
,..PX.....:Multiplex. The MPX; BC1
BC2 inputs determine the
bus interface configuration. MPX HIGHseiects a multiplexed
bu~, whereas MPX LOW, selects a non-multiplexed bus.
<
.'1
o
,"
•
During normal operation, the RAM operates at bus spe~ withou.l
. affecting ~e ~qJ)tents q!:!.he EEPROM. AAMaccesses ar~ controUedby. E, 02(WR), R/w(RO), and (AS/ALEjillputS depending
on the str.apped bus configuration ..
BC1, BC2-BusConfiguration land 2, The BC1 and BC2
inputs, in conjunction with:the lVIPX input, determine the'bus
interface configuration. Table 2.defines the specific bus selected
by strapping each of theselhree inputs to' either. Vee or GNO.
EEPROM
VRR-ST()RE Power Supply. This power down retention pin
is normally connected to an external 470 p,F capacitor. The
capacitor' retains enough power·to write the data from RAM into
EEPROM when STORE is commanded upon loss of Vee.'
The 64 bytes of non-volatile EEPROM shadow the static RAM
cell.for-cell. Shadowing means that the RAM array is overlaid
bit-fot-bit. with the .EEPROM array. The .EEPROM operates in
parallel with the.. static RAM during a STORE or RECALL thus
providing immlidiate storage and retrieval. The first two bytes
ar~ not used because the corresponding addresses are used
for the STORE" and RECALL commands.
Vce-Power. +5 Vdc.
GND-Ground. Ground.
4-67
64 x 8 NVRAM
R2000
STORE SECURITY KEY
VRR CONNECTION,
The STORE and RECALL circuit controls the transfer of data
betWeen the RAM and the EEPROM. When a STORE command
is received, i.e., address 0 is written with the value 85 (heXadecimal) on the data lines, data is copied fromi'lAM to the
EEPROM. The 85 value, called the STORE security key, is
saved in an internal register during the STORE process. Once
initiated, the STORE process completes under internal control
and cannot be interrupted by an external signal. Access to the
RAM from the data bus is inhibited during this time ,(indeterminate data will be output to the data bus if a read is attempted)
and is re-enabled at the completion of the STORE. After STORE
is complete-less than 12 ms after receipt of the STORE
command-the 8S value is erased to prevent an inadvertent
STORE from occurring due to an unintentional generation of
address O. Internal R2000 circuitry also prevents alteration of
EEPROM contents during Vee and VRR decay following power
loss, and during Vee and VRR rise after power application.
rheVRR pin is normally connected to an external 470 ,I'F (min.),
1SVcapacitor. The capacitor, charged through internal circuitry
to a value of Vee - 0.2SV, contains enough energy to complete
a STORE operation upon loss of Vee. An internal current
limiting switch prevents a large inrush current to the capacitor
upon power turn~on. An internal power switch connected to Vee
opens during a STORE operation and when Vee drops below
VR R to inhibit current 'drain from the capacitor into the Vee
power grid.
If the Vee power grid has enough stored energy to support
R2000 operation for at least 12 ms after the processor detects
power loss and initiates a STORE, the VRR pin can be connected to Vee rather than the capacitor.
SYSTEM CONNECTION
Figure 2 shows a typical system connection using an R6S02.
CPU, 4K x asta.tic RAM, system decode logic, on an R2000
NVRAM.
When a RECALL command is received, i.e., any data is written
to address 1, dat,a in the EEPROM is copied to the RAM. The
RECALL time takes less than 7.S its.
Table 1.
R2000 NVRAMMemory Map
Readl
Write
Value
00
Write
85
Read
~
Write
Any
Read
02-3F
AO-A1l
00-07
00-07
Data
Address
(Hex.)
01
AO-A1S
-
Function
STORE RAM to EEPROM. The RAM
byte at this location is not accessible.
The 85 data value is required to
initiate the STORE sequence.
RtW
RtW
112
112/E
4K x 8
STATIC
RAM
CS
, No'operation.
RECALL RAM from EEPROM. RAM
data at this location is not accessible.
OTHER
SYSTEM
CHIP
SELECTS
R6S02
CPU
No operation
Write
Any
Write data to RAM locations 02-3F.
Read
Any
Read data from RAM locations 02-3F.
AO-AS
STORE AND RECALL EXECUTION
64 x 8
Read and write instructions can be executed in the application
program to STORE and RECALL data either during nOrmal
operation or upon detection of power loss or turn-on. If performed
as a part of normal operation, the STORE and RECALL instructions can be executed either periodically or upon demand. If
performed as a part of power on/off processing, the STORE
instruction Should be executed as part of the pOwer loss detect
interrupt handling routine, and the RECALL instruction executed
as part of the power turn-on proceSSing.
00-07
NVRAM
R/W
112
+ 5V------iV"'c"lcl
.:----il 1-1_-..:.V""RR"I.
-¥
Figure 2.
4-68
470pF 15V
Typical.System Interface
II
64
.R2000
Table 2.
BUS CONFIGURATIONS
x 8 NVRAM
Bus Configuration Strapping
Pin cOnnect.lons
Strapping MPX, BC1, BC2 hiputs high (Vee or low (GND) configures the R2000 bus interface to operate with one of five different busses as specified in Table 2. Figure 3 shows the five
possible configurations.
MPX
BC2
LOW
LOW: LOW
BC1
R6500,R65COO, 6800 Non-multiplexed
Bus Interface
LOW
LOW
HIGH
zao Non-multiplexed
HIGH
LOW
LOW
R65COO/2l ,
HIGH
HIGH
LOW
R6500/l1, R6500/41 Multiplexed
HIGH
LOW
HIGH'
B08!i/B051 Multiplexed
6801 Multiplexed
Note: Low = GND, High = Vee
112
NC
E
MPX (GNO)
RJW
07
06
05
04
03
GND
NC
NC
NC
NC
NC
NC
AO/OO
Al/D1
A2/02
GNO
AS
NC
E
MPX (GND)
RD
0.7
DO
DB
01
02
GND
05
04
03
BC2 (GNO)
BC1 (VCC)
VCC
'VRR
BC2(VCC)
001 (GNP)
AS
A4
VCC
VRR
.2
VRR
WR
AS
A4
A3
A2
A1
AO
Z80
Non-multiplexed Bus Interface
R6S00, R6SCOO,6B00
Non-multiplexed BuS Interface
BC2 (GNO)
BC1 (GNO)
112
AS
E
A3
E
MPX (VCC)
A2
MPX(VCC)
RJW
A1
AO
07
06.
A6/~
A4104
A~/03
R6SCOO/21, 6801
Multiplexed Bus Interface
II
vcc
BC2 (GJIU»
BC1 (VCC)
VCC
VRR
BC2 (GND)
BC1 (GNO)
AS
A4
A3
A2
A1
AO
00
01
02
RJW
.
D7
06
05
04
DO
D1
02
GNO
03
R6S00/11. and A6500/4l
MUlltjllexed Bus Interface
Figure 3. Five Possible Strapping Configurations
4-69
NC
NC
Nt
NC
NC
NC
AO/Do
A1/0l
A2/D2
GNO
VCC
VRR
WR
AL-
E
MPX (VCC)
R6
07
06
AS/OS
A4/04
A3/03
.8085/6051
Multiplexed Bus Interface
R2000
64 x 8 NVRAM
PACKAGE DIMENSIONS
24-PIN CERI;lIP
I
.
.•
.'.
..
~
0.557 ±0.042
1
(.,f4.1 5 .' 1.07)
~
.
lJF
~ ....~
1.250':1:0.025
==1
. .'
(32.00
:1:0:34)'
' '"
0.160
to,02
t
T
~l::,~h~.,..
'
.......
,"'n'
0.055 :I: 0,00,
(1.39 :I: 0,'0)
0,018 U 00'
(0.45 :1:0:05)
DIMENSIONS IN INCHES AND (MILLlMETiRS)
)
,
. -.~ ..
4-70
g~
-1
_
I
I
0,660 to 04
1(16,78 :1:1:01)1
0.010 to.OO'
(0.'5 '0,05)
EPROM PINOUTS GUIDE
,......----------------lnleI27256·------------------....,
,......-------------lnleI27128------------------.
, . . . . . . - - - - - - - - - - - · I n l e l 2764 - - - - - - - ' - - - - - - . ,
. . . - - - - - - - - T . I . 2564 - - - - - - - - - ,
...-----Molorola 88764 - - - - - - - .
VPP
vee
VPP
vPP
vPP 1
r--Inlel 2732---,
28 vee
vce
27 CS2
A12
A12
PGM PGM
CSI 2
A12
T..I ·2532
N.C.
A13
26 VCC
A7 1
24 vec
3
23 A8
25
4
A6 2
22 A9
24
5
AS 3
A4 4
All
A1223 A12
All
All
6
21 VPP
7
A3 5.
20 E/PGM GNPP ENP
E/POM G
G
8
A2 6
Al0
Al0
19 Al0
Al021 Al0
Al0
AI 7
E
9
All.20 All
18 All
E
E
10
AO - 8
19
17 DQ7
DQO 9
16 DQ6
18
11
001 10
17
15 DQ5
12
16
13
002 11
14 004
14
15
GND 12
13 DQ3
VPP = 21V
Rockwell ROM Pinouls (VPP z Chip Selecl in ROMS)
VPP = 25V
I I
2732A
2764
27128*
27256*
2732
2532
2564
68764
2332A-2532
R23328- 2732
2364A ----+- 88764
R23648 --2764
R23128-27128
R23C64A~68764
R23C648-2764
R87C32~2732A
NOTE: Pins Without Their Function Designaled Are Ihe Same as Ihe Corresponding Pin on Ihe 2532
*12V for Inlelligenl Programming
4-71
vcc
A14
A13
All
G
Al0
E
"',j
',.C
SECTION 5
INTELLIGENT DISPLAY CONTROLLERS
Page
Product Family Overview ............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5~2
10937 Alphanumeric Display Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-3
10938 and 10939 Dot Matrix Display Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
10939, 10942 and 10943 Dot Matrix Display Controller ........................... 5-20
10941 and 10939 Alphanumeric and Bargraph Display Controller ... . . . . . . . . . . . . . . . 5-32
10951 Bargraph and Numeric Display Controller ................................ 5-41
5-1
INTELLIGENT DISPLAY CONTROLLERS
Cut Costs 30ct/digit, Replace Up To 11 TTL Devices,
I.nterface With Any Host JlC
Rockwell display controllers drastically cut the cost and
complexity of designing vacuum fluorescent (VF) displays
into systems, can actually save up to 30 cents per digit.
One 10937 can replace up to eleven TTL devices and can
interface .withany host microcomputer. VF Display
manufacturers Futaba, NEC. and Noritake have all specified
thEise controllers.
The HJ937is a single,chip alphanumeric display controller
which directly drives 14 to 18 segment VF displays o/up to
16 characters. It includes brightness and refresh controls
and logic, its. own RAM buffer, PLA segment decoder, and
output driver.
The 10951 single-chip display controller is similar to the
10937 except the PLA segment decoder has been
reprogrammed to drive a bar graph display and numerics.
If neither the 10937 nor the 10951 PLA segment codes
satisfy the user's requirements, a custom code may be
specified for the single-chip display controller.
The 10938 segment decoder/driver and the 10939 digit
controller/driver operate as a set to drive dot matrix
displays. A single set controls 5 x 7 dot matrix displays 0/
up to 20 characters or cascaded to control up to
80 characters. Operating at 50V, the sets can drive VF
displays and, with external drivers, LED, CCD, gas
discharge and incandescent displays.
The 10941 can team with the 10939 to drive
alphanumeric 14-18 segment VF displays of 20 to
40 characters and bar graphs. The 10942 and 10943 can
team with the 10939 to drive 40 to 80 character 5 x 12 dot
matrix displays.
The Rockwell display controllers are finding wide
application in printers, photo copiers, typewriters, FAX
machines and in various automotive and white goods uses.
If the user has special requirements, a custom code may be
specified for the segment decoder/driver device which can
be packaged in a 40, 28, or 24 pin DIP according to the
device type selected.
A new single-chip controller is under development which
will be similar to the 10937/10951 devices except the user
will have some control over the number of display outputs
allocated as strobes or segments, the PLA will be. doubled
in size to allow 128 characters and the PLA may be
bypassed to allow direct control of segments.
VACUUM FLUORESCENT CONTROLLER APPLICATIONS
Multi-Chip Display
Controller
Single Chip
Display Type
•
•
•
•
•
•
8 Char. 14-18 Seg.
10 Char. 14-18 Seg.
16 Char. 14-18 Seg.
20 Char. 14-18 Seg.
32 Char. 14-18 Seg.
40 Char. 14-18 Seg.
•
•
•
•
20
32
40
40
Char.
Char.
Char.
Char.
5
5
5
5
x
x
x
x
Anode Driver
Type
(See Part No.)
Display
Controller
(See Part No.)
1 (10937)
1 (10937)
1 (10937)
1 (10941)"
1 (10941)"
1 (10941)"
1 (10938)
1 (10938)
1 (10938)
1 EA (10942)
(10943)
1 (10938)
1 EA (10942)
(10943)
7 MTX
7 MTX
7 MTX
12 MTX
• 80 Char. 5 x 7 MTX
• 80 Char. 5 x 12 MTX
• Numeric + Bar Graph
Grid Driver
(10939)
1 (10951)
" Also Controls Bar Graph Displays
5-2
1
2
2
1
2
2
2
4
4
10937
'1'
10937
ALPHANUMERICDISPLAV CONTROLLER
Rockwell
PRELIMINARY
DESCRIPTION
FEATURES
The 10937 Alphanumeric Display Controller, one of the Rockwell Intelligent Display Controller products, is a MOS/L-SI
general purpose display controller designed to interface to segmented displays (gas discharge, vacuum fluorescent, or LED).
• 16 ~haracter display driver with decimal point and comma tail
The 10937 will drive displays with up to 16 characters w~h .14
or 16 segments plus a decimal point and comma tail. Segment
decoding within the device provides for the ASCII character set
(upper case only). No external drive Circuitry is required for displays that operate on 10 ma of drive current up to 40 volts. A
16 x 64-bit segment decoder provides internal ASCII character
set decoding for the display.
• TTL compatible
• Direct digit drive of 10 mafor 30, 35, and 40 volt displays
• 14 or 16 segment drivers
• Average data rate: ,66 KHz
.
• Single character burst rate: 500 KHz
• Supports gas-discharge, vacuum fluoresCent, or I.,ED displays
• 64 x 16-bit PL-A provides segment decoding for ASCII character set (all caps Only) ,
• Serial data input for 8-bit display and control data words.
• 40-Piri DIP
ORDERING INFORMATION
Part
Number
Package
Type
Drive
Voltage
10937P-30
10937P-35
10937P-40
10937PE-30
10937PE-35
10937PE-40
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
30V
35V
40V
30V
35V
40V
Temperature
Range
O'C
O°C
O°C
-40°C
-40°C
-40°C
to
to
to
to
to
to
+ 70°C.
+ 70'C·
+70°C
+ 85°C
+ 85°C
+ 85'C
SGA
SGB
DISPLAY
DATA
BUFFER
TIMING
SGC
SEGMENT
OECODER
SGD
SGE
SGF
AND
CONTROL
S.GG
DECIMAL PT,
COMMA TAil
SGJ
POR
vss
SGK
SOL
VDD
A
SGP,
DIGIT DRIVERS
PNT
TAIL
10937 Block Diagram
Document No. 29000085
5-3
Data Sheet Order No. 085
Rev. 3, January 1983
10937
. Alphanumeric
Displ~y
.
~
Controller
; ".j
,INTERFACE DESCRIPTION
Signal Name ' PI" No.
1
VSS
ADt6-ADl
VDD
2·17
18
19
20
A
POR
DATA
SCLI<
SGA-5GP
TAIL
PNT
21
22.
23-38'
39
40
-,Functlol1
Power and signal ground
"Digns 16 through 1" driver'outputs
DC power. connection
A ,clock used only for device testing
Power-on reset input
Serial data input
Serial data cl9ck input
Segments A through P driver outputs
COmma tail driver output .
Decimal point driver output
Suppiy Vottage
Power Dissipation
Input Voltage
soo
S9N
SGM
SGL
SGK
SGJ
SGI
SGH
SOO
SGF
SGE
SOD
SGC
SGB
SGA
SCLK
DATA
AD7
ADS
AD5
SymbOl
Voo
'Po
V ,N
Output Voltage
Operating Temperature
Commercial
Industrial
StQrage Temperature
.'SGp
ADe
AD4
,AD3
AD2
ADI
VDD
A
PaR "
SPECIFICATIONS
Maximum Ratings'
Parameter
PNT
TAIL
VSS
AD16
"AbI5
AD14
AD13
AD12
AD11
AD10
AO!I
10937 Pin FUl1Qtlons
VOUT
Typ
Max
Unit
+0.3
", 40'
Min
-20
V
mW
:"'0.3
-,20":,
V
+0.3
-40'
V
'Tc
T,
0
''-,40
TST~
-55
Input CapacHance
100
+70
+!15
+125'
"C'
"C
"C
5
pI
~O
pI
C 'N
Output Capacitance'
COUT
10937 Pin Configuration
This device contains citcuitry toproteiit:thfi, inputs ,'against
damage due to high static voltages, however, it is advised
that normal, precautions, be taken ,to avo id application of any
vol\age higher than maximumTated to this circuit.
All vOttages are specified relative to V 55.
D.C. Characteristics
Limits (VSS
= 0)
Limits (Vss
= +5V)
' Max.
Parameter
Min.
Typ.
Max.
Min.
Typ.
Supply Voitage(V oo)
Input DATA, SCLI<,
Logic "1"
Logic "0"
-16.5
-15.0
-13.5
-11.5
-10.0
-1.0
v oo
+0.3
-4.2
+4.0
Voo
+5.3
+0.8
InputPOH
Logic "1"
Logic "0"
-3.0
Votl
+0.3
-10.0
+2.0
Voo
+5.3
+5.0
Output Digit and
Segment Strobes
Driver On
Commercial
Industrial
Driver Off 10931-30
Driver Off 10937-35
Driver Off 10937-40
Output Leakage
Input Leakage
-1.5
-1.7
-30
:
Condltlol1s
+3.5
+3.3
-25
"
-35
-30
-40
10
10
-35
10
." 10
.'
Unit
V
-8.5
V
V
} At lOrnA
} Actual value
determined by
external. circuit
. } Per driver at
driver off
V
V
V
V
V
,.A
,.A
NOTES: All outputs require Pulidown Resistors.
A.C. Characteristics
Characteristic
Symbol
Internal Clock (1 Bit Time)
Commercial
Industrial
Tcyc
~In
Typ
Max
Unit
10.0
10.0
20.0
22.2
,.s
,.s
ns
20.0
P.s
"
6.67
5.88
Segment or Digit Strobe Output
Tout
200
SCLI< Clock
On lime
Off lime
T on
TOfl
1.0
1.0
Data Input Sample Time
Before SCLK Clock Off
After SCLK Clock Off
TOOfl
Taofl
200
100
,.s
ns
ns
Alphanumeric Display Controller
10937
SCLK and Serial Data Timing
SCLK
DATA INPUT
"DATA must be stable during this time.
SCLK and Serial Data (Control Word) Examples
MSB
SCLK
DATA
DATA
DATA
+5Vn.n n
OV
-.J
LJ
LJ
TIME - - - - - .
n
LJ
I
L..J
0
~
LOAD DUTY CYCLE = 11
t23
~
LOAD BUFFER POINTER = 11
0 0 t23
~
LOAD DIGIT COUNTER = 15
~
l21
21
[%:1 ~ !%;j [%:1 [%:1 !%1
[2]
~
~
~
~
0
1·
0
~ ~ [%:1 f%1 ~
NOTE: Crosshatch
Data Word LSB/MSB Timing
END OF
DATA WORD
NEXT
DATA WORD
~
usa
LSB
MIN 40 ",SEC
Power-On Reset Voltage Umits
POR
-13.5V _ _ _ _
VOLTAGE
5-5
.
= don't care
10937
Alphanumeric Display Controller
FUNCTIONAL DESCRIPTION
Load Digit Counter
The 10937 is a general purpose display controller for multi:
plexed, segmented displays with up to 16 character positions
and 14 or 16 segments, plus decimal point arid comma tail. No
external drive circuitry is needed for displays requiring up to 10
ma of drive current up to 40 volts. All timing signals required to
control the display are generated in the 10937 device without
any refresh input from the host processor.
The LOAD DIGIT COUNTER code is normally used only during
initialization routines to define the number of character positions
to be controlled. This code maximiZes the duty cycle for any
display. If 16 characters are to be controlled, enter a value of
o (zero). Otherwise, enter the value desired.
Input data is loaded into the Display Data Buffer via the Serial
Data Input (Data) channel. Internal timing and control blocks
synchronize the segment and digit output signals to provide the
proper timing for the, muniplexing operation. A 16 x 64-bit PLA
is provided for segment decoding for the full ASCII character set
(upper case only).
The LOAD DUTY CYCLE code is used to turn the display on
and off, to adjust display brightness, or to modify display timing
for gas discharge displays. As shown in the block diagram, the
time slot for each character is 32 clock cycles. The Segment
and Digit Drivers for each character are on for a maximum of
31 cycles with a 1 cycle inter-digit off-time. The LOAD DUTY
CYCLE code contains a 5-bit numeric field which modifies the
on-time for segment Driver Outputs from 0 to 31 cycles. A duty
cycle of 0 puts both the segment and digit drivers into the off
state.
Load Duty Cycle
Input data is loaded into the 10937 ADC as a series of 8-bit
words with the most significant bit (MSB), bit 7, first. If bit 7 of
any word loaded is a logical 1 (this bit is referred to as the control
bit C), the loaded wQrd is a control data word. If the C bit bf any
word is a logical 0, the loaded word is a display data word. Thj3
following paragraphs describe the format and functi\lns of these
control and display data words.
INPUT DISPLAY DATA WORDS.
Display data words are loaded as B-bit ASCII format codes. The
64 codes available (with the C-bit set to 0 to indicate a display
data word) are shown in Table 2 with their corresponding ASCII
characters.
INPUT CONTROL DATA WORDS
WheM the C-Bit (bit 7) of the 8-bit input word is a logical 1, I;)its
5 and 6 are decoded into one of four control commands while
data associated with the command are extracted from bits 0-4
'(see Table 1). There are three control codes which -perforrn the
following display functions:
Sixteen display data words musfbe entered to completely load
the Display Data Buffer. The Buffer Pointer is automatically
.incremented before each data word is stored in the Display
Buffer except for decimal point and comma words. These do not
cause the Buffer Pointer to increment and thus are always
associated with the previous character entered. To select the
next character position to be loaded out of the normal sequence,
use the LOAD BUFFER POINTER command before entering
the display data word. It is not necessary to use the LOAD
. BUFFER POINTER command to cycle back to position 1 when
less than 16 character· positions are being used (DIGIT
COUNTER = 0).
• Load the Display Data Buffer pointer,
• Load the Digit Counter,
• Load the Duty Cycle register.
A fourth control code is defined but is not intended as a user
function (see note associated with Table 1). Table 1 lists the
control codes and their functions.
Load Buffer Pointer
The LOAD BUFFER POINTER code allows the Display Data
Buffer pointer to be set to any digit position so that individual
characters may be modified. The LOAD BUFFER PTR is loaded
with a decimal equivalent value 2 less than the desired value
(i.e., to point to character 6 of the display, a value of 4 is
entered).
Table 1. Control Data Words
8-Bit Control Word
C-Bit (Bit 7)
7-Bit Code (Bits 6-0)
1
1
1
010NNNN(1)
100NNNN(1)
11NNNNN(2)
1
OONNNNN(3)
Function
LOAD BUFFER POINTER (Position of character to be changed)
LOAD DIGIT COUNTER (Number of characters to be output)
LOAD DUTY CYCLE (On/off and brightness control)
TEST MODE ONLY (Not a user functiOn)
Notes: 1. NNNN is a 4-bit binary value representing the
digit number to be loaded
2. NNNNN is a 5-bit binary value representing the
number of clock cycles each digit is on.
3. This code is a device test function only. If executed it will lock the device in the test mode
which can be removed only by performing a
power-on reset.
5-6
10937
Alphanumeric Display Controller
11<114""0_ _ _ _ _ _ _ _ _ _
1~~~Ync;:isLE -----------'-""--'--~
..I
: 31 BIT TIMES
G~~~~~=_--------------'----------'----~r-I~--'---------
AD1
A~
-v
AD3
;1____~!l~________________________________________~r1~____
~I
AD4
~I~I
ADS
AD6
AD9
AD10
AD11
AD12
AD13
AD14
AD16
SGX
________~!I~__________________________________________~~
-r1~1~--------~r!~----------~--~----~~~----~-----------r1~1----------__~rI~~----------------------~--------------
AD6
AD7
AD15
~L1_B_IT~n-M-E-----~---------------'-----~r-l~------I I
,-,~______~--~----------~----~~----------~rI~~-----
-T1~1----------------~rJ~-----------------------------------~I~1----------------~rI~------------------~-----------
~1~1--------------------~rr~--------------------------~-
-T1-r1----------~----~---------4r1~----~~------------------~-----
~I~1------------~--__----~rI~------~------------~
~I~1--------------~----------~rlL--------------~-----
-TI~I------------------------------~rr~--------------------r1-1~------------------------------~--~rI~------_____________
-rl~1----------------------------------~rrL-------~-----
..I I.
31 BIT TIMES
-vG~
, II ' - - - - - - - - - 'n ' - - - - - - - - - - - - - - - - - '! L r l' - - - - - - , - - 1 . ., 1.1 BITnME
NOTE:
I 'I
Timing shown Is for 16 characters with a duty cycle of 31
Figure 1. Display Scan Timing Diagram (Duty Cycle)
Table 2. Character Assignments for, Display Data Words
DATA WORD
CHARACTER
DATA WORD
CHARACTER
OXOOOOOO
OXOOOO01
OX000010
OXOOO011
OX000100
OXOO0101
OXOO0110
OXOO0111
UX001OO0
OX001001
OX001010
OX001011
OX0011oo
OX001101
OX001110
OX001111
@
OX01oo00
OX01OOO1
OX01OO10
OX01oo11
OX010100
OX010101
OX010110
OX010111
OX011Ooo
OX011OO1
OX011010
OX011011
OX011100
OX011101
OX011110
OX011111
P
A
B
C
D
E
F
G
H
I
J
K
L
M
N
0
DATAWORO
Q
R
S
T
U
V
W
X
y
Z
[
/
1
1\
-
"
OX1000OO
' OX10OOO1
OX100010
. OX1OOO11
. (}X100100
OX100101
OX1oo110
OX100111
OX101oo0
OX101oo1
OX101010
OX101011
,OX1011QO
OX101101
OX101110
OX101111
5·7
CHARACTER
!
"
#
$
0/0
&
(
)
+
\
DATA WORD
CHARACTER
OX110ooo
OX11 0001
OX110010
OX110011
OX1101OO
OX110101
OX110110
OX110111
OX1110OO
OX111001
OX111010
OX111011
OX1111oo
OX111101
OX111110·
OX111111
0
1
2
3
4
5
6
7
8
9
:
;
<
=
>
?
Alphanumeric Display Controller
10937
POWER-ON F1ESET (POR)
SEGMENT DRIVERS. (SGA-SGP)
The Power-On Fleset (POR) initializes the internal circuits of the
10937 ADC when power (V DD) is applied, The forlowing conditions are established after a Power-O,n Reset:
Sixteen. 0.6) Segment Drivers' are provided (SGA-SGP), plus
the decimal point (PNT) and comma tail (TAIL). The segment
outputs. are internally deCOded from the 8-bit characters in the
Display Data Buffer by means of a 64 x 16-bit PLA. The Segment Driver Allocations are shown in Figure 2. Data codes and
their corresponding segment patterns are shown in Figure 3.
Timing characteristics for the segment outputs are shown in
Figure 1. See POR for the Power-On Reset state of these
drivers:
a. The Digit Drivers (AD1-AD16).are in the off state (floating);
b.. The Segment Drivers (SGA-SGP) are.in the off state
(floating). This includes PNT and TaiL
c. The cycle on-time for the LOAD DUTY CYCLE is set toO
.
~~
d. The LOAD DIGIT COUNTE.R is set to 16 (a bit code value
of 0).
e. The LOAD BUFFER POINTER is set to 15 to allow the first
character to be entered into position 1.
NOTE
For 14-segment displays, SGA is used for the top segment and SGF is used for the bottom segment. SGB and
SGEcan be floated.
DIGIT DRIVERS (AD1-AD16)
TYPICAL SYSTeM HOOK-UP
The sixte.en Digit Drivers (AD1-AD16) are used to select each
olthe display digits sequentially during a refresh scan. Display
segments will be illuminated when both the Digit Drivers and
Segmentorivers for a particular character are energized simultaneously.The timing characteristics of both the digtts and segments are shown in Figure 10 See POR for the POwer-On Reset
state of these drivers.
a
Figure 4shbws the 10937 driven by Host System as it would
be connected to a V-F display. EK is determined by the V-F
display specifications and RC is selected to provide proper
biasing currentforzeners. Pull down resistors RA and RG are
determined by the interconnection capacitance between the
10937 and the display.
SGA
SGH
SGB
.'~ GI ~GJ I
I~
. -.. -,
sao·'·
SGGI
'.' ."
.
. SGC
SGK
~.,/,
. . .•. . ,.."
· . I·SGD
/~~'"
$GF
SGe
•
.J
Figure .~. Segment Driver Alloc.ations
5-8
PNT
TAIL
A.lphanumeric Display Controner
10937
~
LSD
000
001
010
OXOOO
OX010
OX001
IlX011
-- 1 \- - 1 1- - \
I-1-1 I I 1
-- - - - 1
- -1 1 1 1
\1
\
1
- I- I- -
--
I- I.
I I- -I
OX1OO
\1
1\
OX101
/
SPACE
-
\/
OX111
-- -1
II I-- I
\ 1/\ 1- -1
1
\1
1
OX110,·
-
--
\
/
--I
--I
1
\
I
--
--
I II
\1/
- -I
-
1
/1\ I-- I I I- -I I \ /---- --I
I 1 -I- -I- / 1- - I
1
1
-1-1 1 --I /
-- I \ - -1 1-
1
1
011
--
100
101
III
I I 1- --1\/\
I-
I- --
110
111
I-
I
-I -
--
I
\
1
1
II
\
-
DECIMAL
POINT
-1-1
-
\
+
--I
I
I -I -
TAIL
--
1
\1 - - -- -I I I- -I - I II - I
--I - -\\
/
\1
\
\
I--I -I \1 1/ 1\ I- \\
\
\
I
1
\
1
\
--
I
\
I I
DECIMAL
POINT
I
/
/
I-- \ I--I II \1 - -
/
\
~-
--
I
I
--
NOTES: 1. Indicates characters that will not look the same as shown on a 14 segment display.
2. The LSD corresponds to the three least significant bits (Q..2) and the MSD corresponds to the next three bits
(3-5) in Table 2.
Figure 3. Display Segment Driver Character Patterns
5·9
- 1
I
11)937
Alphanumeric Display Controller
+5
Vss
DATA
10M'
10937
15V
CLOCK
+5
'----+---'-1 Voo
Rc
A
ADX
. TYPICAL
ANODE
(SEGMENT)
TYPICAL
GRID
(DIGIT)
1---'lN.-------+--------- V·F
DISPLAY
-V D1SP
Figure 4. Typical System Schematic
5·10
HOST
SYSTEM
. 1,0938.10939
'1'
10938 AND 10939
DOT MATRIX DISPLAY CONTROLLER,
Rockwell
DESCRIPTION'
FEATURES
The Rockwell 10938 and 10939 Dot Matrix Display Controller
is a two-<:hip MOs/LSI general purpose display controller syStem
designed to interface to dot matrix displays (gas discharge,
vacuum-fluorescent or LED).
• 20-<:haracter display driver cascadable to 80 or more
characters
• Standard 5 x 7 character font. Custom. fonts available by
speCial order
• Separate cursor driver output
• Direct drive capability for- vacuum-fluorescent displays
.; 96 x 35 PLA provides segment decoding for full 96-<:haracter
ASCII set
• Serial or parallel data input for 8-bit display and control
characters
• Brightness, refresh rllte, and display mode cOntrols
The-two-<:hip set will drive displays with up to 35 anodes (dots)
and up to 20 grids (characters) plus a cursor. The chips can be
cascaded to drive larger'displays of 80 characters or more with
any number of segments. An internal PLA-type segment decoder
provides character decoding and dot pattern generation for the
full 96-<:haracter ASCII set.
ORDERING INFORMATION
Part
Number
1093BP
1093BPE
10939P
10939PE
• 40-pin DIP
Package
Type
Temperature
Range
PlastiC
Plastic
Plastic
Plastic
O"Cto
-40°C to
O°Cto
-40"C to
I
+70"C
+B5'C
+70°C
+85°C
»CHARACTER 5 )( 7 DOT MATftlX"OISPI,.AY
SG01-SQU
CURSOR
STRDO-ST
",.
10939
10938
~
I
ANODE DRIVERS AND LATCHES
t
IN~~~~ON
LEVEL
t
..
DET
I6x3!iPlA
"--I
t
L
I
t
L
GRlDDAlY!RS
I
8-BlT SHIFT
REGISTER
CONTROL
LOGIC
r
SHIFT: CLOCK
I
-,
-
I""-"--
.....
:ill x •
~
t
I
HOST
Block Diagram of 10938 and 10939
Document No. 29000096
5-11
Data Sheet Order No. 096
Rev. 1, November 1982
10938 & 10939
Dot Matrix Display Controller
INTERFACE DE.SCRIPTION
10938 Pin Functions
Signal Naine
Vss .'
SG01-SG35
SCLK-DIS
DATA-LOAD
Voo
VGG "
Pln·No.
10939 Pin F~rictions
:;.
'Function
Power and signal ground
2
3-25,27:311 Segmeni driver outputs
' Serial data shift
39
Serial da,ta output/laich control
40
DC Power
I
Pull down driver vo~a!le
26
DATA-LOAD'
SCLK-DIS
SGOI
SG02
SG03
SG04
SG05
SG06
SG07
SGOI
SG09
SGl0
SGll
SG12
Voo
Vss
SG35
SG34
SG33
::~
SG30
SG29
SG28
SG27
SG26
SG25
SG24
SG23
SG22
SG21
SG20
SG19
SG18
Pin No.
Vss
Voo
CLOCK
CURSOR
MASTER
SIP
SOP
00:07
LO
POR
SCLK-DIS
DATA-LOAD
STROO-STRI9,
36
37
38
14
39
Pin Configuration
1
40
15-34
35
DATA-LOAD
MASTER
CLOCK'
, Voo
'Vss
VG•
STROO
STRCI1
STR02
D4
D5
STR03
06
D7
CURSOl'!
STR19
STR18
STR17
STR16
STR15
STR14
STR05
STR04
STR06
STR07
STR08
STR09
STR10
STR11
STR12
STR13
10939
SPECIFICATIONS
Pin Configuration
,
Parameters
Notes
!
Operating Temperature
Commercial
Industrial
Storage Temperature
Symbol'
"
Min
Typ
Max
Unit
I
Tc
Ti
Operating Vo~age
Operating Display VoHage
5
4
FU!1ctlon
Power and signal 'ground
DC Power
Synchronization Clock
Cursor drive output
Master/Slave Mode control
Sync Input
Sync Output
Serial or parallel dat!! input
Input data Strobe
Power-on reset
Serial data shift clock
Serial data output/latch control
Anode Drive Outputs
Pull down, driver voltage
SClK:DIS
SOP'
SIP
POR
LD
DO
Dl
D2
03
SG13
SG14
SG15
SG16
SG17
Maximum Ratings
3
2
6-13 '
VGG
VGo
10938
, Signal Name
0
-40
-55
1
Voo
-22
1
VGG
-50
Power Dissipation (tOtal)
1'000 = 0 rnA per driver
I'oao = 2 rnA per driver
2
Power Dissipation
:i
NOTES: 1. DeSignates characteristics for both 10938 and 10939.
2. , DeSignates characteristics lor 10938.
3., Designates characteristics lor 10939.
5-12
+70
+85
+125
-20
°C
°C
°C
-18
Vo~s
-30
Volts
PDO
POL
40
200
100
750
rnW
rnW
PO
200
400
mW
Dot Matrix DispfayController
10938 &10939
D.C_ CharacteristiCs
Notes
Parameters
InputDG-D7, LD, SIP
Logic "1"
Logic "0"
3
Input POR
Logic "1"
Logic "0"
3
Symbol
Min",
V,iI'
Vll
-1:2
"
Output SOP
Logic/11"
Logic "(1'
3
Output Digits, Cursor, and SegmentS
Logic !'1" (I,,,,,. = 10 mAl
Logic "(1' (I,,,,,. = 0 mAl
1
Typ
Vee
,
V 1HPO
V II•PO
-3.0
VOHSY
VOLSY
-1.2
V,,"
VOL
-1.5 '
Voo
Voo
'Max
Unit
+0.3
-4:2
V
V
+0:3
-10.0
V
V
+0.3
-4.2
V
V
.95 Voo
V
V
\,
Voo
NOTES: 1. Designates characteristics for both 10938 and 10939.
2. Designates characteristics for 10938,
3. Designates characteristics Illr 10939.
A.C_ Characteristics
Parameter
CLOCK Cycle Time
Commercial
'Industrial
Display Outputs
(STROO-STR19 and CURSOR)
Symbol
Typ
Min
Max
Unit
20.0
22.2
p.s
T...
6.66
5.88
T_
7.5'
1.54-
Tston
Serial Date (DO)
Set-upTime
Hold Time
Serial Clock to LD Time
LD to Serial Clock'
/.loS
p.s
,
SERIAL INTERFACE TIMING
Serial Clock (01)
On Time
()ff Time
Cycle Time
/.loS
iscon
20.0
0.4
' p.,
T.-
OA
p.S
Tsccyc
1.0
fLS,
Tsset~p
400
ns
Tshold
400
ns
,}"SI
600
ns
T,s
400
ns
TphOld
0
200
ns
ns
T1don
250
ns
40:0
44.5
p.S
...
PARALLEL INTERFACE TIMING
Parallel Data (00-07)
Set-upTime
Hold Time
Data Load (lD)
On Time
Off Time
Commercial
Industrial
CyCle Time
Commercial
Industrial
• 40 pt. maximum load capacitance:
I
TPSetup
Tldeff
/.loS
T'dCYC
60.0
66.7
P.s
I
p's
,
Dot Matrix Display Controller
10938 & 10939
SERIAL INTERFACE TIMING WAVEFORr.,S
r--- T"""---I
~TKon~ Tseoff-.J
~;ERIALCLOCK) ~
1
i-I--"'I~,,---_--:-_. . .' -__
I
I-T,,-j
I
,-T
....-'O_I." __ ...._
I
LD
DO
(DATA)
PARALLELINTERFACE TIMING WAVEFORMS
-"---I.,
__ Tid'" _ _....1
~I________. . .r---
1·-__
..
TId",, _ _
~I-=.,:::T'do::."~.~I_.
LD
____~I
D~D7
~
-t-L-d. r)
5-14
(
·1
___ -.J
Dot Matrix Display Controller
10938& 10939
FUNCTIONAL DESCRIPTION
Load Buffer Pointer
Once the display buffer has been loaded from the host processOr, the 10938/10939 system generates all timing signals
required to control the display.
The Load Buffer Pointer code sets the Display Data. Buffer
pointer: The lower 5 bijs of the code are loadedinto the buffer
pointer (see Table 2).
Table 2 Load Buffer POinter Codes
Input data is loaded into the Display Data Buffer via the Serial.
or Parallel Data Input channel on the 10939. Internal timing
and control logic synchronize the digit output signals with the
Serial Data and Load signals· to the 10938 to provide the
proper timing for the multiplexing operation. A 96 x35 bit
PLA is provided for decoding the full 96 character ASCii set.
Input data is loaded into the 10939 as a series of 8'bit words.
If the Serial Mode is selected, Input Data lines D2-D7 should
be tied down to Voo externally. Raising anyone of these lines
to the V ss level automatically shifts the 10939 into the Parallel
Mode. Input data may be Control or Display data. The following paragraphs describe the format and fUnctions of these
control and display data words.
'
CONTROL DATA WORDS
Control data words are distinguished from Display Data words
by the fact that they must be preceded by a Control Prefix
word (00000001 or 01 16), Control words and their functions
are defi ned in Table 1.
Table 1. Control· Word Assignments
Hex Value
00
01
02
03
04
05
06
07
08
09
OA
DB
O.C
00
OE
OF
to-3F
40-7F
80-9F
AO-BF
CO-DF
EO-FF
Function
Not used
Load 01 into Data Buffer
Not used
Not used
Not used
Set digit time to 16 cycles per grid
Set digit time, to 3Zcycles per grid
Set digit time to 64cYc:les per grid
Enable Normal Oispll!-y Mode (MSB in data words
is ignored)
Enable Blank Mode (data words with MSB =' 1
will be blanked)
Enable Inverse Mode (data words with MSB = 1
will be "inversed')
Not used
Not used
Not used
Start Display Refresh Cycle (useoniy once after
reset)
Not used
Not used
Load Duty Cycle Register with lower 6 bits (0-63) .
Load Oigit Counter (80=32, 81 = 1, 82=2,eto.)
N()t used
'
L~ad Buffer Pointer Register with lower 5 bits
Not Used
Code
Value
PoInter
Value
CO
Cl
C2
C3
C4
C5
C6
C7
C8
Cg
CA
CB
CC
CD
CE
CF
DO
01
D2
03
D4
05
06
07
08
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
D9
DA
DB
DC
DO
DE
OF
15
16
17
18
19
lA
lB
lC
10
IE
IF
Character
POSitIon
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NOT
USED
31
NOTE: DO NOT USE CHARACTER POSITIONS 20-31:
LO~d
Digit Counter
The Load Digit Counter defines .the number of character
positions (grids) to be controll!'ld. This code is normally used
only during initialization rO\.ltines, but it may also be\.lsed in
conjunction with the LOad Duty Cycle control code to extend
the range of brightness control (see Table 3).
Load Duty Cycle
The Load Duty Cycle code isused to turn the displayon and
off, to adjust display brightness, or to modify display timing.
The time slot foreabh character is 16, 32, or 64 cycles as
selected by the. Load .Digit Time codes (see Table 3). The
segment and digit drivers for each character are on for a .
maximum of 13, 29, or61 cycles with a 3.0 cycle inter-digit
off-time. The lower 6 bits of the Load Duty Cycle cOde are
loaded into the. Duty Cycle Register. Resultant duty cycles
are shown in Table 4.
5-15
Dot Matrix Display Controller
10938& 10939
Table 3. Load Digit Counter Codes
Code
Table 4. Duty Cycle Control Codes
Digit
Counter Value
No. of Grids
Controlled
Code
00
01
02
03
04
05
06
07
08
09
OA
08
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
18
1C
10
IE
IF
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
40
41
42
43
44
45
46
47
48
49
4A
48
4C
4D
4E
4F
50
51
52
80
81
82
83
84
85
86
87
88
89
8A
88
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
98
9C
9D
9E
9F
58
5C
5D
5E
5F
60
7C
7D
7E
7F
Load Digit Time
The Load Digit Time codes set the total time for each character during the refresh cycle.'Three values can be set using
the three codes shown in Table 1. The default value set at
power-on is 64 cycles per grid. For displays with 40 or more
characters, or under conditions where the display can be
subjected to quick movements during viewing (e.g. portable
or vehicle-mounted applications), it may be necessary to
increase the refresh rate by selecting 16 or 32 cycles per grid
with the appropriate control code.
Digit Time=16
on
orr
1
2
3
4
5
6
7
8
9
10
11
12
13
13
13
13
16
16
16
15
14
13
12
11
10
9
8
7
6
5
4
3
3
3
3
"
"
"
"
"
"
"
"
"
"
"
"
Digit Time=32
On
Off
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
25
26
27
28
29 .
29
29
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
32
32
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
7
6
5
4
3
3
3
"
"
Digit Time=64
On
Off
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
64
64
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
25
26
27
28
29
30
31
32
39
38
37
36
. 35
34
33
32
58
59
60
61
6
5
4
3
,
In the Blank mode, any character with the MSB="I" will be
blanked. In the Inverse mode, it will be displayed with all segment driver outputs inverted. On video displays, this is referred
to as "Inverse Video" format These controls allow individual
characters or groups of characters to be' blinked or blanked
by simply changing the mode without changing the data in
the Display Buffer.
Enable Display Mode
Start Refresh
Each ASCII character is represented by the lower . seven bits
of the a·bit value loaded into the 10939. The eighth (most
significant) bit is ignored in Normal display mode. If. either
Blank or Inverse mode is selected, however, a "0" in this bit
selects Normal display mode, while a "1" selectseither.Blank
or Inverse mode, depending on which mode is enabled.
Three control codes are provided (see Table 1) to enable
blank mode, enable inverse mode, or enable normal mode.
At power on, the 10939 is held in an internal Halt mode. The
normal display refresh sequence starts upon receipt of a
Start Refresh control code. This is particularly useful for synchronizing systems using more than one 10939. Only the
Master 10939 in a multi-chip system will recognize the Start
Refresh code. The Master starts the Slave(s) at the appropriate time, using the SYNCO signal.
5-16
Dot Matrix Display Controller
10938 &10939
INPUT DISPLAVDATAWORDS
~
Display data· words are loaded as 8-bit codes. The eighth
(most significant) bit specifies normal (0) or blank/inverse (1)
display mode, depending on the blank/inverse mode. selection. (see Control data words 0.9 and o.A in Table 1). Figure
1 shows the· ASCII codes for the segment patterns for a bargraph display.
2
3
:
0
....
.
4
e,.'
... .
..
.
.'
~:
: :
Twenty display data words must be entered to completely
load the Di::;play Data Buffer. The Buffer Pointer automatically increments after each data word is stored in the buffer.
To select the next character pOSition to be loaded out of
sequence., use the Load Buffer· Pointer Command. The Buffer
Pointer will automatically reset to character position 0. when
its value is equal to the Digit Counter programmed value.
2
.....
....
4
The Power-On Reset (PaR) initializes the internal circuits of
the 10.939. This is normally accomplished when power (V DO)
,is applied. The following conditions are established by appli. cation of paR:
"
...
.. .. .
:
..
; .....
....
:
..
8
1:1
:
..
0.".·
NOTE,S:
1. When the paR signal is removed, SCLK-DIS is set to the
' .
high impedance state.
2. During the initial rise time of VDD at power turn-on, the
magnitude of VGG should not exceed the magnitude of
V DD ·
.. .:
.. ..
7
A
:
:
.. ...
- ..
S
9
.-
.i •••
5
a. The Grid Drivers (STRo.o.-STR19) on the 10.939 are in the
off state.
,b. The Anode Drivers (SGo.1-SG35) on the 10.938 are in the
off slate.
c. The Duty Cycle is set to o..
d. The Digit Counter is set to 32.
e. The Buffer Pointer is set to o..
f. The Digit time is sel to.64.,
g. The Normal display mode is set.
h. DATA-LOAD is set to high impedance state:
i. SCLK-DIS is set to VOL to disable the segment drivers in
the. 10.938.
j. S()P is set to VOL to disable the sync pulse.
..
7
6
..
3
POWER-ON RESET
:
5
. ....
.. ... -
.....
.
i.
.. .. :
..
...
:
:
B
..
.. ,
,.
..
:
.
"
• e ....
C
DIGIT DRIVERS (STROO-STR19) PLUS. CURSOR
The 20.. Digit Drivers select each of the display character
positions sequentially during a refresh scan: Display segments will be illuminated when both the ,Digit Drivers and
Segment Drivers ·for a particular character are energized
simultaneously. The Cursor segment is generat!ld by the
.10.939, but its timing characteristics are identical to the 16
',segments generated by the 10.938.
"
0
...
...
: :
"
.
.
E
:
F
SEGMENT DRIVERS (SG01-SG35)
....
e .....
Sixteen Segment Drivers are provided .in the 10.938. The
output states for each ASCII character pattern and each bar·
graph pattern are internally, decoded from the 8-bit characters received from the 10.939 by means of a 96 x 1. 6-bitPLA.
Data codes and the corresponding of the ASCII patterns are
shown in Figure 1. Data codes and the corresponding bargraph patterns are shown in Figure 2.
.
The four least significant bits of the seven bit ASCII' code are
shown in hex notation down the left side olthe table. The
three mpst significant bits are shown across the top of the
table.
Figure 1. Dot Matrix Patterns
5-17
Dot Matrix Display Controller
10938 & ,1 0939
N·
1
2
3
4
5
6
7
4
1
2
3
SOOl
SG06
- SG11
SG16
S021
S026
S031
- -SOj)2
S007
SG12
S017
SG22
S027
S032
SG03
8008
SG13
S018
SG23
SG2a
SG33
SG04
SG09
SG14
.. SG19
- SG24
SG29
SG34
TYPICAL SYSTEM HOOKUPS
5
Figure- 3 shows a 10938 and a 10939 in a parallel interface
with the host system driving a 20 character display. Figure
4 shows a 10938 and a 10939 in a serial interface with the
host system driving a 20 character display. Figure 5 'Shows
a 10938 and two 10939's interfaced parallel with the host
system driving a 40 character display.
SGOS
SG10
SG15
SG20
SG25
SG30
SG35
Figure 2. 5 x 7 Dot Matrix Assignments
FILAMENT 1
20 CI:IARACTER. VACUUM TUBE
FLUORESCENT DISPLAY
FILAMENT 2
CURSOR
STROO-STR19
SG01~SG35
10938
.':.:.
v,.
-15V
v,.
soP
V"
+5V
V"
SIP
V"
-4SV
V",
10939
MASTER
DATA-LOAD
'., .~.
CLOCK
-,5V (v.,)
N.C.
SCLK·DtS
Figure 3. Typical Display System with Parallel Interface to Host System
FILAMENT 1
20 CHARACTER VACUUM TUBEFLUORESCENT DISPLAY
FILAMENT 2
CURSOR
STR1IO-STR19
SGD1-SG35
10938
V,.
-1SV
V"
+5V
V"
v"
-45V
v,.
SOP
SIP
10939
MASTER
DATA.LOAD
SCLK·DtS
Figure 4. Typical DIBplay System with Serial Interface to Host System
5-18
CLOCK
-15V IVo,)
N.C.
-1SV(Vool
D9t .Matrix D.i$play Controller
10938 & 10939
.
. . . . - - FlLA,,!,NT I
40 CHARACTEFt VAtUUM TUBE
"..
FLUOReSceNT DISPLAY
:--------- FII.AMENT ,2
,
SG01-SG35
,
$TRQO..STR19
Voe _
-15V_
SOP
SIP
10939 (MASTER)
MASTER
CLOCK
SIP
SOP
SCLK-DIS
LD
00-07
POR
MASTER I--+$V(V.,)
I-- -15V (V,.)
CLOCK
DATA-LOAD
I
.
VPD,
V" - + 5 V V"
V" - 4 5 V - V"
10938
'
STROII-STRI9
If
I
10939 (SLAVE)
LD
00-07
l
HOST
SYSTEM
Figure 5_ Typical Display System with Parallel Interface to Host and Two
5-19
10939 Dsvlces
POR
10939 · 10942·· 10943
'1'
10939, 10942, & 10943
DOT MATRIX DISPLAY CONTROLLER
Rockwell
DESCRIPTION
FEATURES
The Rockwell 10939, 10942, and 10943 Dot Matrix Display
COntroller is a three-chip MOS/LSI general purpose display controller system designed to interface to dot matrix displays (gas
discharge, vacuum-fluorescent or LED).
• 20-character display driver cascadable to 80 characters
• Standard 5 x 12 character font. Custom fonts available by
special order
• Separate cursor driver output
• Direct drive capability for vacuum-fluorescent displays
• Two 96 x 23 PLA's provide segment decoding for full 96character ASCII set
• Serial or parallel data input for 8-bit display and control
characters
• Brightness, refresh rate, <'Ind display mode controls
• 10939 provided in 40-pin 01 P
• 10942 and 10943 provided in 28-pin DIP
The three-chip set will drive displays with up to 46 anodes (dots)
and up to 20 grids (characters) plus a cursor. The chips can be
cascaded to drive larger displays of up to 80 characters with
any number of segments. An internal PLA-type segment decoder
provides character decoding and dot pattern generation for the
full 96-character ASCII set.
ORDERING INFORMATION
Part
Number
Package
Type
10939P
10939PE
10942P
10942PE
10943P
1D943PE
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
l
Temperature
Range
O°C to
-40"C to
O°C to
-4DoC to
DOC to
-4DoC to
+70°C
+85°C
+ 70°C
+85°C
+ 7DoC
+85°C
~
2o-CHAAACTER 5)( 12 DOT MATRIX DISPLAY
~SG01-SG23
109H
I
ANODE DRIVERS AND LATCHES
•
INVERSION
LOGIC
t
I
I '''''PLA I
t
L...f
{ ' 5G01-SG23
I
10943
I
ANODE DRIVERS AND lATCHES}--
•
§
§}
DETECT
DETECT
L ~~I~SION J
t
I
9Sx23PLA
t
8·81T SHIFT REGISTER
8-61T SHIFT REGISTER
'''39
101
RAM
CONTROL
LOGIC
~
I
~
~
CURSOR
GRID
DRIVERS
/
STRQO-STR19
I
'---
I
HOST
I
Block Diagram of 10939, 10942, 10943
Document No. 29000099
5-20
Data Sheet Order No. 099
March 1983
Dotft18trix
10939; 10942,.& 10943
DispJayOon~rolier'
INTERFACE DESCRIPTION
10939 Pin Functions
10942 and 10943 Pin Functions
Signal Name
Voo
Vss
SG01-SG23
VGf?,
SCLK-DIS
DATA· LOAD
Pin No.
1
2. , '.
3-1719-26
18
27
28
Function
Signal Name
DCPoW!!r
.' POWlIr and signal ground
$8gm!!nl (Aood!!) driwr outputs
Pull down driwr voltaQ!!
&lIal data shift
&rim data output/lalch control
PlnNo.
36
37
38
Vss
VOD
CLOCK
CURSOR
MASTER
SIP
14
39
3
2
6-13
5
SOP
DO~D7
LD
POR
SCLK-DIS.
DATA-LOAD
STRO(j-STR19
VaG
4
1
40
15-34
35
Function
Pow!!r and signal groun~
DC Pow!!r
SynchroniZation Clock
Cursor driw oulput
Maat!lr/SlaV!! Mode control
Sync Input
Sync Output
serial or parallel data input
Input data strobe
POWlIr-on reset
&rial dala sllilt clock
&rial data outpUl/lmch C(lIltrol
Anod!! Drive Outputs
Pull down drillllr voltaQ!!
Voo
Vss
SG23
S022
SG21
SG20
S019
S018
SOH
SG16
S015
S014
SClKDiS
SOP
SIP
POfI
LD
DO
SG06
DATA-LOAD
MASTER
C!-OCK
Voo
Vss
VaG
01
D2
03
VaG
SG09
. ~013
SG12
STROD
STROt
$TRo2
STR03
STR04
STIiI05
STAGG
STRD7
STROS
STR09
STRtD
D4
OJ;
sG10
OS
07
CURSOR
STRt9
STR18
STR17
STR16
STRtS
S011
, 10942 and 10943
. j:»Jn ,COnfigurations
Stftl1
STRt2
StRl~
5TR14
10939 Pin Configurations
SPECIFICATIONS'
,
Maximum Ratings
Parametllra
Symbol
Min
apllrating j!!mpllr8tiill!
Commercial
Industrim
Storage Temperature
TA
Ts
-55
Opllrating Vollag!!
Voo
-22
Opllralillg Display Vollage
VGG
-50
'typ
0
-40
6-21
-20
Max
'.'
Unit
OC
+70
+85
+125
·0
·0
-18
VolIS
-30
Volts
10939, 10942, & 10943
Dot Matrix Display Controller
D.C. Characteristics (Voo = -18 to -22 Vdc, Vss = 0 Vdc, unless otherwise noted.)
Parameter
Symbol
Min
1 0942 & 10943
Output segments
Logic "1" (I LOAO =.2 mAl
Logic "0" (lLOAO = a mAl
Typ
Max
VOH
VOL
-1.5
VGG
10939
Input DO-D7. LD. SIP
Logic "1"
Logic "0"
V,H
V,L
-1.2
Voo
+0.3
-4.2
V
V
Input POR
Logic "1"
Logic "0"
V ,HPO
V ,LPO
-3.0
VOO
+0.3
-10.0
V
V
Output SOP
Logic'''l''
Logic "0"
VOHSY
V OLSY
-1.2
Voo
+0.3
-4.2
V
V
Output Dig~s, CurSor
Logic "1" (I'oad = 10 mAl
Logic "0" (I'oad = a mAl
VOH
VOL
-1.5
VGG
.
0.95V GG
0.96VGG
Units
V
V
V
V
Note: TA = ()"C to + 70'C (commercial) or -4()"C to +85'C (industrial). unless otherwise noted.
Operating Currents
Parameters
•
.'
Maximum
Industrial
TA
40°C
Voo
-22Vdc
Commercial
TA
DOC
Voo
-22Vdc
=
=
==
Typical
Units
= 25'C
= -2DVdc
TA
Voo
10942 & 10943
100
I GG (1)
155(3)
4.5
11.2
85.7
9.0
82.6
2.2
5.6
77.8
mA
mA
mA
13.6
1.0
84.6
10.9
0.8
71.7
6.0
0.5
76.5
mA
mA
mA
9.1
1.0
80.1
7.3
0.8
78.1
4.0
0.5
74.5
mA
mA
mA
3.6
10939 (master)
100
I GG (2)
155 (3)
10939 (slave)
100
100(2)
Iss(3)
Notes:
1. The 10942 and 10943 each have 35 inlernal driver outputs. 23 of which are brought out. IGG is proportional to I~e number of drivers'
on. The values given are for all"35 drivers on. Divide IGG shown by 35 to determine IGG for one driver.
2. The 10939 will never have more than two drivers on at anyone time; one grid driver and the cursor. The values shown are for two
drivers on with 100% duty cycle.
.
.
,.'
3. Iss = 100 + IGG + laVA (lOVA = 35xILOAO)
Example: For 10939 and 10943 (TA = -40'C and Voo = -22V):
Iss = 4.5 + 11.2 + (35 x 2.0) = 85.7mA.
5-22
10939, 10942, & 10943
Dot Matrix Display Controller
A.C. Characteristics
Paramtltllr
Min
Symbol
CLOCK Cycle Time
Commercial
Industrial
Teyc
Display Outputs
(STRoo·STR19 and CURSOR)
T."'ff
6.66
5.88
Max'
Typ
20.0
22.2
p.s
p's
7.5"
1.54"
p's
T ston
Data Load (LO)
On Time
Off Time
Commercial
Industrial
Cycle Time
Commercial
Industrial
T 1don
Unit
P.s
1.0
P.s
40.0
44.5
P.s
60.0
66.7
p'S
Tldoff
p.S
T ldeyc
SERIAL INTERFACE TIMING
Serial Clock (01)
On Time
Off Time
Cycle Time
p.S
1.0
1.0
2.0
T scon
Tscoff
T sccyc
,.8P.s
20.0
p.s
Serial Data (DO)
Set-upTIme
Hold Time
Tssetup
TShOld
400
Serial Clock to LO Time
TSI
1.0
P.s
LD to Serial Clock
Tis
1.0
p.S
T psetup
0
200
ns
ns
PARALLEL INTERFACE TIMING
Parallel Data (00-07)
Set-upTime
Hold TIme
ns
ns
400
TPhoid
'40 pI. maximum load capacitance.
SERIAL INTERFACE TIMING WAVEFORMS
j - T_o-----t
I-T_-I-T_-I
~~RIAL CLOCK) ~
i-I----,~--~_~'---
I
J.TIO~
T_----t.1
L..o....-_ _ _ _ _
LD
DO
(DATA)
PARALLEL INTERFACE TIMING WAVEFORMS
1....- - -----1./
TIdcyC
LD
DO-D7
5-23
..-J
Dot Matrix Display Controller
10939,10942,& 10943
FUNCTIONAL DESCRIPTION
Load Buffer POinter
Once the display buffer has been loaded from the host processor, the.1093~, 10942, a,nd 10943 system generates all
timing signals required to control the display.
The Load Buffer Pointer code sets the Display Data Buffer
pointer. The lower 5 bits of the code are loaded into the buffer
pointer (see Table 2).
Input data is loaded into the Display Data Buffer via the Serial
or Parallel Data Input channel on the 10939. Internal timing and
control logic synchronize the digit output signals with the Serial
Data and Loa<;t signals to the 10942/10943 to provide the proper
timing for the multiplexing operation. Two 92 x 23 bit PLA's,
one in the 10942 and the other in the 10943, decode.the full 96character ASCII set:
Input data is loaded into the 10939 as a series of S-bit words.
If the Serial Mode is selected, Input Data lines 02-07 should be
tied down to V OD externally. Raising anyone of these lines to
the V55 level automatically shifts the 10939 into the Parallel
. Mode. Input data may be Control or Display data. The following
paragraphs describe the format and: functions of these control
and display data words.
CONTROL DATA WORD.S
Control data words are distinguished from Display Data words
by the. fact that they must be preceded by a Control Prefix word
(0000 0001 or 01 16). Conttol words and their functions are
defined in Table 1.
Table 1.
HexV.lue
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10·3F
40-7F
80-9F
AD-BF
CO'DF
EO-FF
Control Word Asslgnm.nls
FunctIon
Not used
Load 01 into Data Buffer
Not used
Not used
Not used
Load Digit Time to 16 cycles per grid
Load Digit Time to 32. cycles per grid
Load Digit Time to 64 cycles per grid
Enable Normal. Display Mode. (MSB in data words is
ignored)
Ena.ble Blank Mode (data words with .MSB 'C 1 will
be blanked)
Enable ·Inverse Mode (data words w~h MSB = 1 will
be "inversed")
Not used
Not used
Not used
Start Display Refresh Cycle (use only once after
reset)
Not used
Not used
Load Duty Cycle Register
Load Digit Counter (80=32, 81 =1, 82=2, etc.)
Not used
Load Buffer Pointer Register w~h lower 5 bijs
Not used
Table 2.
Load Buffer PoInter Codes
Code
Value
POinter
Value
CO
Cl
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
01
02
03
D4
05
D6
07
08
09
DA
DB
DC
DO
DE
OF
00
01
02
03
04
OS
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
lA
lB
lC
lD
IE
IF
Character
Position
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
·28
29
30
31
NOT
USED
Note: Do not use character posHions 20-31.
Load Digit Counter
The Load Digit Counter defines the number of character posilions (grids) to be controlled. This code is normally used only
during initialization routines, but it may also be used in conjunction with the. Load. Duty Cycle control code to extend the
range of brightness control (see Table 3).
Load Duty Cycle
The Load Duty Cycle code is used to turn the display on and
off, to adjust display brightness, or to modify display timing. The
time slot for each character Is 16, 32, or 64 cycles as selected
by the LOad Digit Time codes (see Table 1). The segment and
digit drivers for ea.ch character are on fOr a maximum of 13, 29,
.or 61 cycles with a 3:0 cycle inter-digit off-time. The lower 6 bits
of the Load Duty Cycle code are loaded into the Duty Cycle
Register. Resultant duty cycles are shown in Table 4.
5-24
Dot Matrix Display Controller
'0.939, 10942,& 10943
Table 3. Load Digit Counter.Codes
Code
Digit
Counter YeJue
80
81
82
83
84
85
86
87
88
89
8A
88
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
98
ge
90
9E
9F
00
01
02
03
04
05
06
07
08
09
OA
08
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
lA
18
lC
10
IE
IF
Table 4. Duty Cycle .ControlCodes
No. of Grid.
Controlled
Code
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 .
22
23
24
25
26
27
28
29
30
31
DlgltTlme=16
40
41
On
Off
On
Off
-
16
18
16
15
14
13
12
-
32
32
32
31
30
-
64
64
1
2
3
4
5
6
7
8
9
10
11
12
13
13
13
13
43
44
45
·48
47
48
49
4A
4B
4C
40
4E
4F
50
51
52
·
5B
5C
50
5E
SF
60
..
···
···
··
11
10
9
8
7
6
5
4
3
3
3
3
·
·"
"
·"
"
"
»
..
7C
7D
7E
Load Digit Time
The Load Digit Time codes. set the total time for each character
during the refresh cycle. Three values can be set using the three
codes shown in Table 1. The default value set at poweroOn is
64 cycles per grid. For displays with 40 or more characters, or
under conditions where the 9isplay can be subjected to quick
movements during viewing (e.g. portable or vehicle-mounted
applications), it may be necessary to increase the refresh rate
by selecting 16 or 32 cycles per grid with the appropriate control
code.
.
7F
DIgit Tlme=84 .
Off
-
42
Digit Tlme=32
On
·
"
»
·
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
18
17
25
26
27
28
29
29
29
"
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
7
6
5
4
3
3
3
·
··
··
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
25
26
27
28
29
30
31
32
64
63
62
61
1
...
60
59
58
57
56
55
54
53 '
52
51
50
49
48
47
39
38
37
36
35
34
33
32
'.
"
"
··
"
··
·
58
59
60
61
6
5
4
3
In the Blank mode, any character with the MSB="I" will be
blanked. In the Inverse. mode, it will be displayed with ali segment driver outputs inverted. On video displays, this is referred
to as "Inverse Video" format. These 'controls allow individual
qharacters or groups of character.!'to beblinked or blanked ~y
simply changing the mode without changing the data in the Dis'play Buffer;
Enable Display Mode
Start Refresh
Each ASCII character is represented by the 10V(8r seven bits of
the a·bit value loaded into the 10939. The 'eighth (most signifi·
cant) bit is used to turn the cursor on .in Normal display mod~,
If either Blank or Inverse mode is selected, hOwever, ~ "0" in
this bit selects Normal display mode, while a "I" selects either
Blank or Inverse mode, depending on which mode is enabled.
Three control codes are provided (see Table 1) to enable blank
mode, enable inverse mode; or enable normal mode.
'At power on, the 10939 is held in an internal Halt mode. The
normal display refresh sequence' Starts upon receipt of a Start
Refresh control code. This is particularly useful for synchronizing systems using more than one 10939. Only the Master
10939 is a multi-chip system will recognize the Start Retresh
code. The Master starts the Slave(s) at the appropriate time,
usil)g the SYNCO signal.
5-25
.
II
Dot Matrix Display Controller
10939, 10942, & 10943
INPUT DISPLAY DATA WORDS
POWER-ON RESET
DisJ'lay data words are loaded as S-bit codes. The eighth (most
significant) bit (bit 7) is a dual purpose ,bit. This bit specifies
normal (0) or blank/inverse (1) display mode, depending on the
blank/inverse mode selection (see control data words 09 and
OA in Table 1). Bit 7 also controls the cursor: output from the
10939; on (1) or off (0). Note, however, that this bit always controls the cursor no matter what display mode is selected.
The Power-On Reset (PaR) initializes the internal circuits of the
10939. This' is normally accomplished when power (Voo) is
applied. The following conditions are established by application
of paR:
a. The Grid Drivers (STROO-STR19) on the 10939 are in the off
state.
b. The Anode Drivers, SG01-SG23 on the 10942 and SG01SG23 on the 10943, are in the off state.
c. The DUly Cycle is set to O.
d. The Digit Counter is set to 32.
e. The Buffer Pointer is set to O.
f. The Digit time is set to 64.
g. The Nonnal display mode is set.
h. DATA-LOAD is set to high impedance state.
SCLK-DIS is set to, VOL to disable the segment drivers in the
10942 and 10943.
j. SOP is set to VOL to disable the sync pulse.
Twenty di,splay data words must be entered to completely load
the Display Data Buffer. The Buffer Pointer automatically increments after each data word is stored in the buffer. To select the
next character pos~ion to be loaded out' of sequence, use the
Load Buffer Pointer command. The Buffer Pointer will automatically reset to chanl.cter position 0 when its value is equal
to the Digit Counter programmed value.
DIGIT DRIVERS (STROO-STR1~) PLUS CURSOR
The 20 Digit Drivers sel,ect each of the display character positions sequentially during a refresh scan. Display segments will
be illuminated when both the Digit Dri,Vers and Segment Drivers
for a particular character are energized simultaneously. The
Cursor segment is generated by the 10939, but its timing characteristics are identical to the 46 segment outputs generated by
the 10942 and the 10943.
NOTES:
1. When the paR signal is removed, SCLK-DIS is set to the
high impedance state.
2. During the in~ial rise time of Voo at power turn-on,the magnitude of VGG should not exceed the magnitude olV oo.
SEGMENT DRIVERS (SG01-SG23)
46 Segment Drivers are provided by the 10942 and the 10943.
The o.utput states for each ASCII character pattern are internally
decoded from the 8-bit characters received from the 10939 by
means of two 96 x 23-bit PLA's, one in the 10942 and the other
in the 10943. Data codes and the corresponding ASCII patterns
are shown in Figure 1.
R~
SEGM.ENTS
DRIVEN BY
10942
1
2
3
4
5
SEGM.ENTS
DRIVEN BY
10943
6
7
8
9
10
11
12
1
2
3
4
5
~G01
~G02
SG06
SG11
S016
S021
SG03
SG08
SG13
SG16
SG19
X
SG07
SG12
SG17
5022
SG04
SG09
X
X
SG20
X
SG03
SG08
S013
SG18
5023
SODS
5010
X
X
SG21
X
.SG04
SG09
SG14
5019
5001
SG06
SG11
SG14
SG17
SG22
X
SGDS
5010
SG15
S020
S002
SG07
SG12
SG15
SG18
SG23
X
TIE THESE F,IVE TOGETHER!l J
Note:
1. DRIVEN BY CURSOR LINE OF 10939.
Figure 2.
5 x 12 Dot Matrix Assignments
5-26
Dot Matrix Display ~ontroller
10939, 10942, & 10943
~o 000
0001
0010
0011
I
•
X010
0100
0101
0110
.•• -=.'.-.
0111
~~
•
~~
II '.
""
f-,.
L
II II
X011
1111
~
••
.~
I
J•
·
•
•
•
• ·
•
. • •r - ·••
• •
..,.
'~" •
~
X100
'"
1111
II •
~
X101
'"
•
X110
X111
II
..
:I •
~
•• ..
•.. ..
••.. ..
.'
FFFI
•
••
·
..
••
..
••
•
.. .. • ••- ''""
~.
~
~
f-,.
.
I""
III
Dot Matrix Patterns
5-27
-
. I
..
~
Figure 1.
I ••
..
..
l"-
•
~
•
[I
•
•..
•I
10939~ 10942, & 10943
I~
1000
Dot Matrix Display Controller
1001 . 1010
•
X010
•
• f.-
..
""~
•
.:
,
X100
X101
X110
r
.
1100 ..
1101
•• ..
N
'"
"" ""
.~
••
-
•
r
•
•
••
""
•
•
f'-
~
•••
•
•
""
~
r
X111
••••
~
•
1111
•
r-
••
1110
• J •••
I Ie
\+
X011·
'.
1011
••
-~
Figure 1. Dot Matrix Patterns (Cont.)
.'.~"
I
10939, 10942,& 10943
Dot Matrix Display Controller
TYPICAL SYSTEM HOOKUPS
Figure 3 shows a 10939, 10942, and a 10943 in a parallel interface with the host system driving a 20-character display. Figure
4 shows a 10939, 10942, and a 10943 in a serial interface with
the host system driving a 20-character display. Figure 5 shows
two 10939's, a 10942, and a 10943 interfaced parallel with the
host system driving a 40-character display.
7
FILAMENT 1
20-CHARACTER 5 x 12 DOT MATRIX VACUUM 'FLUORESCENT DISPLAY
FILAMENT 2
/ SG01-SG23
I
SG01-SG23
I
15V
Voo
Vss
Voo
Vss
V..
-45V
v••
10943
10942
DATA-LOAD
!sCLK-DI
V..
Vss
Voo
SOP
MASTER
P
r-
CLOCK
r-
SIP
10939
-15V (Yoo)
N.C.
CURSOR
STROO-STRlI
LD
DO-D7
i
POR
I
i
HOST SYSTEM
Figure 3.
Typical Display System with Parallel Interface to Host System
5-29
10939, 10942, & 10943
r
/
I
Dot Matrix Display Controller
2CJ.CHARACTER 5
F1LAMENT 1
x12 VACUUM FLUORESCENT DISPLAY
FILAMENT 2
"' SG01-SG23
1
SG01-$G23
I
v••
v..
vo•
-15V
v••
vss
v..
-45
"
10943
10942
DATA~LOAD
eLK-DI
v..
v,.
v••
SOP
,SIP
10939
-j5V (V..) - 02-07
P
MASTER
1-7-
CLOCK
r- N•C.
.,.15V (V•• )
CURSOR
STIIOG-STR19
LD
DO
01
POR
I
t t
LATCH SERIAL
CLOCK
,
Figure 4.
DATA:
HOSTSVSTEM
Typical Display System with Serial Interface to Host System
5-30
' , '
,
10939, 10942, & 10943
Dot Matrix Display Controller
r
~
:':"
FtLAMma
'
,0
1SGm~G23
1SG01..s023
v,,
-1SV
V..
Vos
-45V
V..
1094:;!
-
V..
+6V
,....
Voo
DATA-LOAD
SCLK-DIS
DATA-LOAD
SIP
MA$TER
10139 (MASTER)
CURSOR
DO-D7
SCLK-DIS
DATA-LOAD
SIP
SOP
POR
I
I
I
SCLK-DIS
STRDD-STR19
LD
SOP
I---
+SV(Vss)- MA.....
-'.V(Vool
10131 (SLAVE)
I--f-
'CURSOR
-
SfflOO.STR1.
LD
CURSOR
/
DO-D7
POR
"
sTRllC>$TR'.
/
I
Figure 5.
MOs.-SYSTEM
I
Typical Display System with' Parallel Interface to Host and Two 10939 Devices
5-31
)
~1:~ENT1.,
4O-CHARACTER 5 )( 12 DOT MATRIX VACUUM FLUORESCENT DISPLAY
"':'
10941.10939
'1'
10941 AND 10939
ALPHANUMERIC AND BARGRAPH
DISPLAY CONTROLLER
Rockwell
DESCRIPTION
FEATURES
The Rockwell 10939 and 10941 Alphanumeric and Bargraph
Display Controller is a twci-chip MOS/LSI general purpose display controller system designed to interface with bargraph and
segmented displays (gas.discharge, vacuum-fluorescent or LED).
• 20-character display driver cascadable to 80 or more
characters
• Direct drive capability for vacuum-fluorescent displays
• 96 x 16 PLA provides segment decoding for ASCII characters (all caps only) and bargraph patterns
• Serial or parallel data input for 8-bit display and control
characters
• Brightness, refresh rate, and display mode controls
• Separate cursor driver output
• 10939 comes in 40-pin DIP
• 10941 comes in 24-pin DIP
The two-chip set will drive up to 20 segments and up to 20 grids
(characters) plus a cursor. The chips can be cascaded to drive
larger displays of 80 characters or more. Segment decoding for
ASCII characters or the bargraph patterns is accomplished
throug h an internal PLA.
ORDERING INFORMATrON
Part
N.umber
10941P
10941PE
10939P
10939PE
Package
Type
Temperature
Range
Plastic
Plastic
Plastic
Plastic
O'C to
-40'C to
O'C to
-40'C to
I
+70'C
+8S'C
+70'C
+8S'C
2O-CHAAACTEA 16-SEGMENT ALPHANUMERIC OR BARGRAPH DISPLAY
SG01·SG16
STRoo.STR19
CURSOR
10939
10941
~
GRID DRIVERS
SEGMENT DRIVERS AND LArCHES
~
f
I
INVERSION
LOGIC
I
91)( 1SPLA
J
f
L-.f
t
f
.---
LEVEL
DET
I
&oBIT SHIFT
REGISTER
.,-
CONTROL
~
20" 8
RAM
LOGIC
'----
SHIFT CLOCK
t
I
HOST
Block Diagram of 10941 and 10939
Document NO. 29000097
5-32
Data Sheet Order No. 097
November 1982
10941 & 10939
Alphanumeric and Bargraph Display Controller
INTERFACE DESCRIPTION
10941 Pin Functions
Pin No.
Signal Name
Vss
SG01·SG16
SCLK-DIS
DATA-LOAD
Voo
Voo
10939 Pin Functions
Function
Signal Name
Power and signal ground
2
6-15, 17-22 Segment driver outputs
Serial data shift
23
24
Serial data output/latch control
1
DC Power
Pull down driver voltage
16
Voo
Vss
NOT USED
NOT USED
NOT USED
SG16
SG15
SG14
SG13
SG12
SG11
SG10
Pin No.
36
37
38
14
39
3
2
6-13
5
4
1
40
15-34
35
Vss
Voo
CLOCK
CURSOR
MASTER
SIP
SOP
00-07
LD
POR
SCLK-DIS
DATA-LOAD
STROO-STR19
VGG
DATA-LOAD
SCLK-DIS
SGOl
SG02
SG03
SG04
SGOS
SG06
VGG
SG07
SGOB
'-L:.::...._ _ _--->--' SG09
Function
Power and signal ground
DC Power
Synchronization Clock
Cursor drive output
Master/Slave Mode control
Sync Input
Sync Output
Serial or parallel data input
Input data strobe
Power-on reset.
Serial data shift clock
Serial data output/latch control
Anode Drive Outputs
Pull down driver voltage
SCLK-DIS
SOP
SIP
POR
LD
DO
01
02
03
04
05
06
07
CURSOR
STR19
STRIB
STR17
STR16
STR15
STR14
10941 Pin Configuration
DATA-LOAD
MASTER
CLOCK
Vee
Vss
VGG
STROO
STROl
STR02
STR03
STR04
STR05
STR06
S'TR07
STR08
STR09
STR10
STRll
STR12
STR13
10939 Pin Configuration
SPECIFICATIONS
Maximum Ratings
Parameters
Operating Temperature
Commercial
Industrial
Storage Temperature
Notes
Symbol
Min
Tc
Ti
0
-40
-55
Operating Voltage
1
VOD
-22
Operating Display Voltage
1
Voo
-50
Power Dissipation (total)
I'o'd = 0 mA per driver
2
Iload = 2 mA per driver
Power Dissipation
Typ
Max
Unit
1
+70
+85
+125
-20
'C
'C
'C
-18
Volts
-30
Volts
PDO
PDL
40
200
100
750
mW
mW
PO
200
400
mW
3
NOTES: 1. Designates characteristics for both 10941 and 10939.
2. Designates characteristics for 10941.
3. Designates characteristics for 10939.
5-33
10941 &10939
Alphanumeric and Bargraph Display Controller
D.C. Characteristics
Parameter
Notes
Input 00'07, LO, SIP
Logic "1"
logic "(y'
3
Input POR
Logic "1"
Logic "(y'
3
Output SOP
logic "1"
LogiQ "(y'
3
Output Digits, Cursor, and Segments
LogiC 'I" (I,oad '" 10 rnA)
logic "(Y' (1,0.. '= 0 mAl
1
Typ
Max
Symbol
Min
V'H
V'L
-1.2
Voo
+0.3
-4.2
V
V
V 1HPO
-3.0
Voo
+0.3
-10.0
V
V
. -1.2
Voo
+0.3
-4.2
V
V
-1;5
V••
.95 VG.
V
V
VILPO
VOHSY
VOLSY
VOH
VOL
Unit
NOTES: 1. Designates characteristics for both 10941 and f 0939.
2. Designates characteristics for 10941.
3. Designates characteristics for 10939.
A.C. Characteristics
Parameter
Symbol
CLOCK Cycle .Time
Commercial
Industrilll
T,,,",
Display Outputs
(STROO-STRI9 and CURSOR)
Tstoff
Tston
Min
6.66
5.88
Typ·
Max
Unit
20.0
22.2
/LS
/LS
7.5'
1.54'
/LS
/LS
20.0
/LS
/LS
SERIAL INTERFACE TIMING
Serial Clock (01
On Time
Off Time
Cycle Time
f
0.4
0.4
1.0
Tscon
TSCoff
TSCCYC
iJ.S
Serial Data (DO)
Set-up Time
Hold Time
Tst10ld
400
400
ns
ns
&erial Clock to LD Time
T"
600
ns
LD to Serial Clock
T,.
400
ns
Tpsetup
0
200
ns
ns
·250
ns
40.0
44.5
/LS
/LS
60.0
66.7
iJ.S
Tssetul)
PARALLEL INTERFACE TIMING
Parallel Data (00-07).
Set-upTime
Hold lime
Data Load (LD)
On lime
Off Time
Commercial
Industrial
Cycle lime
Commercial
TphOld
Tldon
TldOff
TldCYC
Ind~strial
• 40 pl. maximum load capacitance.
5-34
/Ls
1
10941 & 10939
Alphanumeric and Bargraph Display Controller
SERIAL INTERFACE TIMING WAVEFORMS
~ERIAL
r--- Tsceys '---f
1.- -+-- SCoff-+l
Tscon
CLOCK)
-.J
T
I
~I----,\
' -__
~
I-T's~
l-Ts,+T,don..J..-T,doff---....,.~1
LD
_________-+!_-'I
Ts!lIetup
L.. .I_____
--.r-
TShOld
DO
(DATA)
1:1
PARALLEL INTERFACE TIMING WAVEFORMS
...1.1-----T,dCyC----~·1
I-T'don ....;....I..·-_T,doff - -......-t.
1_ _
LD
I
00-07
5-35
I
10941 & 10939
Alphanumeric and Bargraph Display Controller
FUNCTIONAL DESCRIPTION
Load Buffer Pointer
Once the display buffer has been loaded from the host processor, the 10941/10939 system generates all timing signals
required to control the display.
The Load Buffer Pointer code sets the Display Data Buffer
pointer. The lower 5 bits of the code are loaded into the buffer
pointer (see Table 2).
Input data is loaded into the Display Data Buffer via the Serial
or Parallel Data Input channel on the 10939. Internal timing
and control logic synchronize the digit output signals with the
Serial Data and Load signals to the 10941 to provide the
proper timing for the multiplexing operation. A 96 x 35 bit
PLA is provided for decoding the full 96. character ASCII set.
Table 2 Load Buffer Pointer Codes
Control data words are distinguished from Display Data words
by the fact that they must be preceded by a Control Prefix
word (0000 0001 or 01,.). Control words and their functions
are defined in Table 1.
Control Word Assignments
Function
00
Not used
Load 01 into Data Buffer
Not used
Not used
Not used
Set digit time to 16 cycles per grid
Set digit time to 32 cycles per grid
Set digit time to 64 cycles per 9rid
Enable Normal Display Mode (MSB In data words
is ignored)
Enable Blank Mode (data words with MSB ~ 1
will be blanked)
Enable Inverse Mode (data words with MSB ~ 1
will be "inversed")
Not used
Not used
Not used
Start Display Refresh Cycle (use only once aiter
reset)
Not used
Not used
Load Duty Cycle Register with lower 6 bits (.0-63)
Load Digit Counter (80=32, 81 =1,82=2, etc.)
Not used
Load Buffer Pointer Register with lower 5 bits
Not used
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10·3F
40-7F
80'9F
AQ'SF
CO·DF
EO·FF
Character
Position
CO
C1
C2
00
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
D1
D2
D3
04
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
CONTROL DATA WORDS
Table 1.
POinter
Value
C3
Input data is loaded into the 10939 as a series of 8-bit words.
If the Serial Mode is selected, Input Data lines 02-07 should
be tied down to Voo externally. Raising anyone of theSe lines
to the V ss level automatically shifts the 10939 into the Parallel
Mode. Input data may be Control or Display data. The following paragraphs describe the format and functions of these
control and display data words.
Hex Value
Code
Value
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
lA
lB
lC
10
IE
IF
NOT
USED
NOTE: DO NOT USE CHARACTE8 POSITIONS 20-31.
Load Digit Counter
The Load Digit Counter defines the number of character
positions (grids) to be controlled. This code is normally used
only during initialization routines, but it may also be used in
conjunction with the Load Duty Cycle control code to extend
the range of brightness control (see Table 3).
Load Duty Cycle
The Load Duty Cycle code is used to turn the display on and
off, to adjust display brightness, or to modify display timing.
The time slot for each character is 16, 32, or 64 cycles as
selected by the Load Digit Time codes (see Table 3). The
segment and digit drivers for each character are on for a
maximum of 13, 29, or 61 cycles with a 3.0 cycle inter-digit
off-time. The lower 6 bits of the Load Duty Cycle code are
loaded into the Duty Cycle Register. Resultant duty cycles
are shown in Table 4.
5-36
10941 &10939
Alphanumeric and Bargraph Display °Controlter
Table 3. Load DIgit Counter Codes
Table 4. Duty Cycle Control Codes
Digit
Counter Value
No. of Grids
Controlled
Code
81
82
83
00
01
02
03
4li
41
42
84
04
85
86
87
05
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Code
80
86
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9E
9F
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
43
44
45
46
47
46
49
4A'
4B
4C
40
4E
4F
50
51
52
58
5C
50
5E
5F
60
7C
70
7E
7F
Load Digit Time
The Load Digit Time codes set the total time for each ,char·
acter during the refresh cycle. Three values can be set using
the three codes shown in Table 1. The default value set at
power-on is 64 cycles per grid. For displays with 40 or more
characters, or under conditions where the display can be
subj\!cted to quick movements during viewing (e.g. portable
or vehicle;mounted applications), it may be necessary to
increase the refresh rate by selecting 16 or 32 cycles per grid
with the appropriate control code.
DlgH Tlme=16
on
on
-
11
12
13
13
13
13
"
16
16
16
15
14
13
12
11
10
9
8
7
6
5
4
3
3
3
3
"
"
"
"
1
2
3
4
5
6
7
8
9
10
"
"
"
n
"
"
"
DIgit Tlme=32
on
Off
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
32
32
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
25
26
27
28
29
29
29
"
DigH Tlme=64
On
on
-
64
64
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
63
62
61
60
59
58
57
56
55
54
7
6
5
4
,3
3
3
"
25
26
27
28
29,
30
31
32
39
38
37
36
35
58
59
60
61
6
5
4
3
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
..
53
52
51
50
49
48
47
34
33
32
In the Blank mode, any character with the MSB="1" will be
blanked. In the Inverse mode, it will be displayed with all segment drver outputs inverted•. On vigeo displays, this is referr,ed
to as "Inverse Video" format. These controls allow individual
characters or groups of characters 10 be blinked or blanked
by simply changing the mode without changing the data in
the Display Buffer.'
Enab,le Display Mode
Start Refresh
Each ASCII character is represented by the lower seven bits
of the B-bit value loaded into the 10939. The eighth (most
significant) bit is ignored in Normal display mode. If either
Blank or Inverse mode is selected, however, a "0" in this bit
selects Normal display mode, while a "1" selects either Blank
or Inverse mode, depending on which mode is enabled.
Three control codes are provided (see Table 1) to enable
blank mode, enable inverse mode, or enable normal mode.
At power on, the 10939 is held in an internal Halt mode. The
normal display refresh sequence' starts upon receipt of a
Start Refresh control, code" This is particularly ,\lseful for sYI)chronizing systems using more'than one 10939. Only the
Master 10939 in a multi-chip system will recognize the Start
Rekesh code. The Master 'starts the Slave(s) at the appropriate time, using the SYNCO signal.
5-37
10941 & 10939
Alphanumeric and Bargraph Display Controller
INPUT DISPLAY DATA WORDS
~
'"
Display data words are loaded· as 8-bit cqdes. The eighth
(most significant) bit specifies normal (0) or blank/inverse (1)
display mode, depending on the blank/inverse mode selection (see Control data words 09 and OA in Table 1). Figure
1 shows the ASCII codes for the segment patterns for a bargraph display.
'"
,
Twenty display data words must be entered to completely
load the Display Data Buffer. The Buffer Pointer automatically increments after each data word is stored in the buffer.
To selecUhe next character position to be loaded out of
sequence; use the Load Buffer Pointer command. The Buffer
Pointer will automatically reset to character position 0 when
its value is equal to the Digit Counter programmed value.
'"
POWER-ONAESET
-
-
II
\1/
I--
a. The Grid Drivers (STROO-STRI9) on the 10939 are in the
off state.
b" The Segment Drivers (SG01-SGI6) on the 10941 are in
the off state.
c. The Duty Cycle is set to O.
d. The Digit Counter is set to 32.
e. The B~ffer Pointer is set to 0.'
f. The Digit time is set to 64.
g. The Normal display mode is set.
h. DATA-LOAD is set to high impedance state.
i. SCLK-DIS is set to VOL to disable the segment drivers in
the 10941.
j. SOP is set to VOL to disable the sync pulse.
-
II I
I
-I-I -1- --I /
--
'"'
II
-I-I
POINT
TAil
--
no
I I I---
-7
L_
I
--
I- - \
DECIMAL
I=~I
'~m
1
m
--
I I I
I I-\
'-
,
\1
,
I I \1
I \1 I
I--I -\
I - I
I I
/
I
1\ I I /
I-
I \1 1/
I
I - I
1\
I I
I
I--I I--I II \1 --
Figure 1. 10941 14-Segment Display Patterns
Input Code
Segment Patterns (1 =On)
7 6 5 4 3 2 1 0 ABC 0 E F G H I J K L M N 0 P
NOTES: .
1. When the paR signal is removed, SCLK-DIS is set to the
high impedance state.
2. During the initial rise time of V DD at power turn-on, the
. magnitude of VGG should not exceed the magnitude of
V DD•
DIGIT DRIVERS (STROO-STR19) PLUS CURSOR
The 20 Digit Drivers select each of the display character
positions sequentially during a refresh scan. Display segments will be. illuminated when both the Digit Drivers and
Segment Drivers for a particular character are energized
simultaneously. The Cursor segment is generated by the
10939, but its timing characteristics are identical to the 16
segments generated by the 10941 .
.
SEGMENT DRIVERS (SG01-SG16)
Sixteen Segment Drivers are provided in the 10941. The
output states for each ASCII character pattern and each bargraph pattern are internally decoded from the 8-bit characters received from the 10939 by means of a 96 x 16-bit PLA.
Data codes and the corresponding of the ASCII patterns are
shown in Figure 1. Data codes and the corresponding bargraph patterns are shown in Figure 2.
0
0
O.
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0 0 1 0
0 0 1 1
o ·0 1 1
0 1 0 0
0 1 0 0
0 1 0 1
0 1 0 1
0 1 1 0
0 1 1 0
0 1 1 1
0 1 1 1
0
1
0
1
0
1
0
1
0
1
1 0
1 0
1 0
1 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
1 1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 1
1 1
1 1
1 1
1 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 1
1
1
1
1
1
1
1 1
1 1
1 1
1 1
1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 1
1 1 1
1 1 1 1 1
1 1 1 1 1 1
1 1 1 1'1 1
1 1 1 1 1 1
1 1 1 1 1 1
Figure 2. 10941 Bargraph PLA Codes
5-38
,
I- 1 I-- I
I
I \ -- I IIII
I \
I- -I I
I I I-- I
\
I I
-,
1\/1 I I
I-- - - II
I
--I - - I- - I I I--I
DECIMAL
71-- I
I
J_
I- I
I
--
11\
I II
, --
-- -
""
'"
'"
'"
II- - I I- - I \1
I I
1\
-
I--I I--I
--I I I
I
I
\
/
--
The Power-On Reset (PaR) initializes the internal circuits of
the 10939. This is normally accomplished when power (V DD)
is applied. The following conditions are established by application of paR:
'"
\ IL_1 I- -I I I I I
\1
""
."
'"
/ I II I-- I
Sl'ACE
~
no
'"
1
1 1
1 1 1
10941 & 10939
Alphanumeric and Bargraph Display Controller
TYPICAL SYSTEM HOOKUPS
Figure 3 shows a 10941 and a 10939 in a parallel interface
with the host system driving a 20 character display. Figure
4 shows a 10941 and a 10939 in a serial interface with the
host system driving a 20 character display. Figure 5 shows
a 10941 and two 10939's interfaced parallel with the host
system driving a 40 character display.
FILAMENT 1
20 CHARACTER VACUUM TUBE
FLUORESCENT DISPLAY
FILAMENT 2
CURSOR
STRoo-STR19
SG01-SG16
10941
V"
-15V
V"
SOP
V"
+5V
V"
SIP
V"
-45V
Voo
10939
MASTER
DATA-LOAD
-15V (Voo)
CLOCK
N.C.
SCLK-OIS
Figure 3. Typical Display System with Parallel Interface to Host System
r-____.{------------------------~::::::~~::~~------------------------r.---ALAMENTI
20 CHARACTER VACUUM TUBE
FLUORESCENT DISPLAY
. FILAMENT 2
CURSOR
STROO-STR19
SG01-SGI6
10941
V"
-15V
V"
SOP
V"
+5V
V"
SIP
V",
-45V
Voo
10939
MASTER
DATA-LOAD
SCLK-DJS
Figure 4. Typical Display System with Serial Interface to Host System
5-39
CLOCK
-15V (Voo)
N.C.
-15V
(Vool
Alphanumeric and Bargraph Display Controller
10941 & 10939
,...
/
_ F l l AMENT 1
40 CHARACTER VACUUM Tuee
FLUORESCENT DISPLAY
SG01·$G16
I
Y"
I--
_ F I LAMENT 2
STROO-STR19
STROo-STR19
-15V- Y"
SOP
SIP
Y" I-- +5Y V"
Y" I-- -45Y- Y"
10941
SIP
SOP
MASTER ........,. -15Y (V,,)
CLOCK
10939 (MASTeR)
OATAlOAO
SClKOIS
I
lO
00-07
POR
J
If
MASTER
CLOCK
10939 (SLAVe)
lO
00-07
J
HOST
SYSTEM
Figure 5. Typical Display System with Parallel Interface to Host and Two 10939 Devices
5-40
POR
r-
10951
'1'
10951
BARGRAPH & NUMERIC
DISPLAY CONTROLLER
Rockwell
Preliminary
DESCRIPTION
FEATURES
The Rockwell 10951 Bargraph & Numeric Display Controller
(referred to as the 10951) is a LSI general purpose display controller designed to interface to segmented displays (gas discharge, vacuum fluorescent, or LED).
• 16 segment drivers plus decimal point and comma tail drivers
The 10951 will drive 16-segment bargraph or seven-segment
plus comma and decimal numeric displays w~h up to 16 display
positions. The controller accepts command and data input words
on a clocked serial input line. Commands control the on/off duty
cycle, starting character position and number of characters to
display. Encoded data words display bargraph position (single
segment or increasing bar length), numbers, comma, decimal
and selected upper and lower case letters. No external drive
circuitry is required for displays that operate on lOrna of drive
current up to 40 volts. A 64 x 16-bit segment decoder provides
internal ASCII character set decoding for the display.
•
•
•
•
•
• 16 digit drivers
• Average data rate: 66 kHz
• Single character burst rate: 500 kHz
-Comma and decimal
-Eight upper and lower case seven-segment characters
• Command functions
-On/off duty cycle
-Character position
-Number of characters
ORDERING INFORMATION
Pari
Number
Package
Type
Drive
Voltage
Temperature
Range
10951P-50
10951PE-50
Plastic
Plastic
50V
50V
DOC to +7D'C
-40°C to +85'C
TTL compatible
Direct digit drive of 10 rna for 30,35, and 40 volt displays
Supports gas-discharge, vacuum ftuorescent, or LED displays
Serial data input for a-bit display and control data words
64 x 16-bit PLA provides data decoding driving
-Any 1 of 16 bargraph segments
-1 to 16 bargraph segments
- Ten seven-segment numeric characters (0-9)
• 4O-Pin DIP
SGA
SGB
SGC
SGD
SGG
SGH
SEGMENT
DRIVERS
SGK
SGl
SGM
SGN
SGO
SGP
TAil
10951 Block Diagram
Document No. 29000094
5-41
Data Sheet Order No. 094
March 1983
10951
Bargraph & Numeric Display Controller
INTERFACE DESCRIPTION
'PNT
VSS
10951, Pin Functions
Signal Name
VSS
AD16-ADl
VDD
A
POR
DATA
SCU<
SGA·SGP
TAIL
PNT
Pin No.
Function
1
2-17
18
19
20
21
22
23-38
39
40
Power and signal ground
Digits 16 through 1 driver outputs
DC Power connection
A clock used only for device testing
PoweroOn reset input
Serial data input
Serial data clock input
Segments A through P dril(er outputs
Comma tail driver output
Decimal point drivar output
AD16
TAIL
AD1S
sGP
AD14
SOD
AD13
SON
AD12
S,OM
AD11
SGL
AD10
SOK
AD9
SGJ
AD8
SOl
AD7
AD6
SGH
SQO
ADS
SGF
SPECIFICATIONS
AD4
SOE
AD3
$GO
Maximum Ratings
AD2
SGC
'ADl
SGS
VDD
SGA
Parameter
Symbol
Min
Supply Vo~age
'Voo
Po
+0.3
Power Dissipation
Input Voltage
40'
V'N
VOUT
Output Vo~age
Typ
Max
Unit
-20
V
mW
+0,3
100
-20
+0.3
-40
V
Tc
T,
+70 '
'C
-40
+85
'C
Storage Temperature
TSTG
-55
Input Capacitance
C'N
COUT
+125
,5
'C
pI
10
pI
Output Capacitance
0
POR
V
Operating Temperature
CommerCial
Industrial
SCLK
A
DATA
10951 Pin, Conftgur!dlon
This·llevice ;'!ontains Circuitry to Pro.tect the inputs against
, damage due' to high static voltages, however, it is/(ldvised
thai normal precautions be lakento avoidapplicalion of any
voltage, higher than maximum rated to this circuit
All voltages are specified'nelative toVss.
DC Characteristics
LImHs (VSS
=0)
Limits (Vss
=
+5V)
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Supply Voltage (V 00)
Input DATA, SCU<,
Logic "1"
Logic "0"
-16,5
-15,0
-13.5
-11.5
-10.0
-8.5
-1.0
Voo
+0.3
-4.2
+4.0
'Voo
+5,3
+0.8
Input POR
Logic "1"
Logic "(Y'
-3.0
Voo
+0.3
-10.0
+2,0
Voo
+5.3
-5.0
Output Digit and
Segment Strobes
Driver On
Commercial
Industriel
Driver Oft 10951-50
-1.5
-1.7
-50
+3.5
+3.3
10
10
10
10
Output Leakage
Input Leakage
-45
CondHlona
Unit
V
V
V
} AtlOmA
} Actual value
determined by
external circuit
} Per driver at
driver off
V
V
V
p.A
p.A
NOTES: All outputs require Pulldown Resistors.
AC Characteristics
Cl1aracteristlc
Symbol
Min
Typ
Max
UnH
6.1)7
5.88
10.0
10.0
20.0
22.2
p's
p.s
Internal Clock (1 Bit Time)
Commercial
Industrial
Tcyc
Segment or Digit Strobe Output
SCLK Clock
On Time
Off Time
Tout
200
Ton
T~ff
1.0
1.0
Data Input Sample Time
Belore SCLK Clock Off
After SCLK Clock Off
Tbott
Taoff
200
100
5-42
ns
20.0
p's
p.S
ns
ns
10951
Bargraph & Numeric Display Controller
SCLK and Serial Data Timing
SCLK
DATA-INPUT
*DATA must be stable during thlstlrne.
SCLK and Serial Data (Control Word) Examples
+5V
SCLK
TIME
MSB
ovDSlJl.JU
DATA
~ ~ ~ t;/;1 ~ ~ t;/;1 ~ ~
DATA
21
~
t%1 t%1
I:/jf
t%1 t%1
t23
,
'
LOAD DUTY CYCLE = 11
~
LOAD BUFFER POINTER = 11
LOAD DIGIT COUNTER = 15
DATA
N<>TE: Crosshstch= don't care
Data Word LSB/MSB Timing
..
END OF
DATA WORD
NEXT
DATA WORD
Lsa
..
LSB
seLK
MIN 4O,.SEC
Power-On Reset Voltage Limits
Vso
r-----r------,---,
POR
VOLTAGE
- - - - - - - - 7 - - - - - TIME
NOTE: Vss referenced to OV
l----. 100~s ----i
MIN
5-43
Bargraph & Numeric Display Controller
10951
FUNCTIONAL DESCRIPTION
Load Buffer POinter
The 10951 receives commands and data on a serial input
line clocked externally by a separate clock. input line. The
controller decodes the commands from control data words,
decod.es the data words in accordance with an internal 64 x 16bit programmable logic array (PLA) and turns on and off segment and digit output drivers. The segment output patterns
are controlled by the decoded data words while the digit
output and segment output timing are controlled by the
decoded control words. All timing signals required to control
the display are generated in the 10951 device without any
refresh input from the host processor.
The LOAD BUFFER PO.INTER code allows the Display Data
Buffer painter to be set to any digit position so that indiVidual
characters may .be modified. The LOAD BUFFER PTR is
loaded with a decimal equivalent value 2 less than the desired
value (i.e., to point to character 6 of the display, a value of
4 is entered).
Load Digit Counter
The LOAD DIGIT COUNTER code is normally used only
during initialization ,routines to define the number of character
positions to be controlled. This. code maximizes the duty
cycle for any display. If 16 characters are to be controlled,
enter a value of 0 (zero). Otherwise, enter the value desired.
Input data is loaded into the Display Data Buffer via the Serial
Data Input (Dat(l) channel. Internal timing and control blocks
synchronize the segment and digit output signals to provide
the proper timing for the mu~iplexing operation. The 16 x 64
PLA decodes 8-bit data words to drive the 16 segment,
comma and decimal point drivers. The decoded data words
will drive 16 segments to display bargraph patterns (single
segment and' mUltiple segment for Increasing, length displays) or . seven-segment patterns to display numbers,
selected upper and lower case letters, comm(l and decimal
point.'
Load Duty Cycle
The LOAD DUTY CYCLE code is used 10 turn the display on
and off, to adjust display brightness,. or to modify display
timing for gas discharge displays. As shown in the. block diagram, the time slot for each character is 32 clock cycles. The
Segment and Digit Drivers for each character are on for a
maximum of 31 cycles with il 1 cycle inter-digit oft-time. The
LOAD DUTY CYCLE code contains a 5-bit numeric field
which'moqifies the on-time for segment Driver Outputs from
o to 31 cycles: A duty cycle 01...0 puts both the segment and
digit drivers into the off state. Figure 1 shows the timing char(lcteristics for the segment outputs.
Input etats is loaded into the,.10951 as a series of 8-bit words
with the most significant bit (MSt;3), bit 7. ',Wbit 7 of an¥ word
loaded is. a I09ic(l1 1 (this'bit Is referred to as the control bit
C), the loaded word is a control data word. If the C bit of any
word Is a 10gicalO, the loaded word isa display data word.
The following paragraphs describe the format and functions
of these control and display data words.
POWER-ON RESET (POR)
The Power-On Reset (POR) initializes the internal Circuits of
the 10951 when power (V OD) is applied. The following conditions are established after a Power-On Reset:
INPUT CONTROL DATA WORDS
When the C-Bit (bit 7) of the 8-bit input word is a logical 1,
bits 5 and 6 are decoded into one of four control co.mmands
while data associated with the command are extracted from
bits 0-4. There are three control codes which perform the
following display functions:
a. The Digit Drivers (AD1-ADI6) are in the off state
(floating).
b. The Segment Drivers (SGA-SGP) are in the off state
(floating). This includes PNT and TAIL.
c. The cycle on-time for the LOAD DUTY CYCLE is set
to 0 cycles.
d. The LOAD DIGIT COUNTER is set to 16 (a bit code
value of 0):
e. The LOAD BUFFER POINTERis set to 15 to allow the
first character 10 be entered into position 1.
.• 'Load the Display Data Buffer pointer,
• Load the Digit Counter,
• Load the Duty Cycle register.
A fourth control code is defined but is ncit intended as a user
function (see note associated with Table 1). Table.l lists the
control codes and their functions.
Table 1. Control Data Words
8"Bit Control Word
C-Bit
7-Bit Code
1
010NNNNI1I
100NNNN11)
1
1
1
l1NNNNNI2)
OONNNNNI3)
Function
LOAD BUFFER POINTER (Position of character to be changed)
LOAD DIGIT COUNTER (Number of characters to be output)
LOAD DUTY CYCLE (On/off and brightness control)
TEST MODE ONLY (Not a user function)
3. This code is a device test function only. II exe-
NOTE: 1. NNNN is a4,bit binary value representing the digit
number to be loaded
2. NNNNN is a 5-bit binary value representing the
number of clock cycles each digit is on.
cuted it will lock the device in the test mode which
can be removed only by performing a power-on
reset.
5-44
10951
Bargraph & Numeric Display Controller
~14~i
ADI
AD2
AOO
AD4
ADS
AD6
AD7
AD6
AD9
A010
ADll
AD12
AD13
AD14
AD15
AD16
_________________
l~~~~~~LE
______________________~~1
: 31 BIT TIMES
G~~~~==~________~____~______________________~r-l~
-v ~ 1 BIT TIME
I I
r-o~
.
____________________________________________~~r_I~____~__
~1~1----~rt~----------------------------------------~rI~---~1~1~______~rI~____________________________________~----~
~1~1~--------~rI~--------------------------------------------
~I~1------------~rI~-------------------------------------
_1~1--------------~rI~----------------------~---------
_:~I~I----------------~r-I~-------------------------------I I
~~------------------------~r-1~--------------------------------------~1-1~----------------------~rI~------------------------------
-L1~1------------------------~rI~------------------------
~1~1--------------------------~rI~----------------------
~I~1----------------------------~rI~-----------------
~1~1--------------------------------~rI'-----------------
-rl~1----------------------------------~rI~-------------~I I~
-vG~
I /1 L..-__________----'11L..-____________________________rt....rl'-----------31 BIT TIMES
SGX
_______________
no....____________
I
~11.l BIT TIME
I II
NOTE:
Tlmlng shown Is for 16 characters with. duty cycle of 31
Figure 1. Display Scan Timing Diagram (Duty Cycle)
5-45
10951
Bargraph & Numeric Display Controller
INPUT DISPLAY DATA WORDS
Drivers and Segment Drivers for a particular character are
energized simultaneously. The timingcharacteristi~s of both
the. digits and segments are shown in Rgure 1. See POR for
the Power-0n Reset state of these drivers.
Display <;lata words are loaded as a-bit format codes. There
are 64 codes available (with the C-bit set to 0 to indicate a
display data word).
Sixteen display data words must be entered to completely
load the Display Data Buffer. The Buffer Pointer is automatically incremented bEtfore each data word is stored in the
Display Buffer except for decimal point and comma words.
The decimal point and comma words do not cause the Buffer
Pointer to increment and t!"ius are always associated with the
previous character entered; To select· the next character
position to be loaded out of the normal sequence, use the
LOAD BUFFER POINTER command before entering the display data word. It is not necessary to use the LOAD BUFFER
POINTER command to cycle back to position 1 when less
than 16 character positions are being used (DIGIT COUNTER
SEGMENT DRIVERS (SGA-SGP)
Sixteen (16) Segment Drivers are provided (SGA-SGP), plus
the decimal point (PNT) and comma tail (TAil). The segment, PNT and TAIL outputs are internally decoded from the
a-bit characters in the Display Data Buffer by means of a 64
x 16-bit PLA. The allocations for the 16-segment bargraph
display and the seven-segment alphanumeric character plus
comma and decimal point are shown in Figure 2. The input
codes associated with seven-segment alphanumeric, comma
and decimal point display are shown in Figure 3. The complete set of S-bit codes for the bargraph and alphanumeric
display is shown in Table 2. Note that only segment drivers
SGA-SGG are used to drive the seven-segment characters.
Segment drivers SGH-SGP may be used for other purposes
as decoded in accordance with Table 2. Timing characteristics for the segment oLitputs are shown in Figure 1. See
POR for the Power-0n Reset state of these drivers.
;>! 0).
DIGIT DRIVERS (AD1-AD16)
The sixteen Digit Drivers (AD1-AD16) are used to select
each of the display digits sequentially during a refresh scan.
Display segments will be illuminated when both the Digit
SGPSGO-SGNSGMSGLSGKSGJ - : SGI
SGH - SGGSGFSGESGDSGCSGB--
--
INPUT
CODE
(BITS 2-0)
SGA
OX1P1
OX110
000
I-I
1_'
I-I
I- I
I-I
I_I
I ,
001
I
I
I ,
_I
I
I
II
1=1
-I
1=
, I
I I
1
I
I I
I
I
1-
SGG
010
SGC
SGE
SGD
.PNT
' TAIL
011
7-SEGMENT
ALPHANUMERIC
100
I
I-
I
I
1
-'
-,
I
,
I-
,
1-
Figure 2. Segment Allocation
101
110
111
I
I
I-
I-
I ,
-,,
-,,
,-
•
OX111
,
-
_I
I- I
I~
1 I
1-
I
,1:-
I
Figure 3. 7-Segment Patterns
5-46
-,
-,
OX100
SGB
SGF
SGA-16-SEGMENT
BARGRAPH
INPUT CODE (BITS 7-3)
Bargraph & Numeric Display Co ntroller
10951
Table 2. 10951 Data Code.
'.
Input
Ccide
7 6 5 4 3 2 1 0
0 X 0 0, 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
,0
0
0
,0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o 0
o 0
o 0
o 0
0 0
0 0
0 0
'0 1
0 1
o 1
0 1
0 1
o 1
0 1
0 1
0 X o
0 X 0
0 X 0
0 X 0
0 X 0
0 X 0
0 X 0
0 X 0
0 X 0
0 X 0
0 X 0
0 X 0
a X 0
0 X 0
0 X 0
0 X 1
0
0
0
1
I
1
I
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
I
0
1
0
I
0
1
0
1
'1
0
I 0 1
1 1 0
1 1 I
Segment Driver Output P_rns (1
Function
Segment ,A On
Segment BOn
Segment C On
Segment D On .
Segment E On
segment F On
Segment G On
Segment H On
Segment I On
SegmentJ On
Segment K On
Segment L On
Segment M On
Segment N On
Segment 0 On
Segment POn
,.
1
1
1
1
1
1
1
1
1
1
1
1
0 0 0
0 0 0
0 0 I
0 0 I
0 I 0
0 I 0
0 I I
0 1 I
1 0 0
1 0 0
1 0 I
1 0 I
I I 0
1 1 0
I I I
I 1 1
Number 0
Number 1
Number 2
Number 3
Number 4
Number 5
Number 6
Number 7
Number B
Number 9
Letter P
LetterL
Comma
Blank
Decimal
Blank
1
0 X
0 0 0 0
0 0 0 1
0 o I 0
.,
1
I
I
I
I
I
I
0 X
0 X
I
0 X
1
0 X
1
0 X
I
I
0 X
0 X 1 1
0 X 1 I
0 X 1 1
0 X 1 I
0 X
0 X
0 X
0 X
0 X
I
1
1
I
,
I
1
I
1
I
,
0 0 I
0 I 0
0 I 0
0 I I
0 1 1
I 0 O·
1 0 0
I 0 1
1 0 I
1 1 0
I 1 0
1 1 I
1 1 I
I
0
I
0
I
0
I
0
I
0
I
0
I
I
0
I
0
1
0
1
0
I
0
1
0
1
Number 0
Number 1
Number 2
Number 3
Number 4
Number 5
Number 6
Number 7
NumberB
Numb8r9
Letter A
Letter ~
LetterC
Letterd
LetterE
Letter F
TAIL
1
0 X 1 0
0 X 1 0
0 X 1 0
0 X I 0
0 X I 0
0 X I 0
0 X 1 0
a X 1 0
0 X 1 0
0 X 1 0
0 X ,1 0
0 X 1 0
0 X 1 0
0 X 1 0
0 X I 0
0 X 1 o
0
PNT
1
0 0 0 I
0 0 1 0
0 0 I 1
0 1 0 0
0 1 0 I
0 1 I 0
0 1 1 1
1 0 0 0
1 a 0 1
1 0 1 0
I 0 I I
I I 0 0
1 1 0 I
I I I 0
I I I I
0
I
800 'SGP
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
0 0 0 0
~
SGA SGB SGC SGD SGE SGF SGG SGH SGI SGJ $OK SGL SGM $ON
Segment A On
Segments MB On
Segment A-C On
Segment A-D On
Segment A-E On
Segment A-F On
Segment A-G On
Segment A-H On
Segment A-IOn
Segment A-OJ On
Segment A-K On
Segment A-L On
Segment A-M On
Segment A-N On
Segment A-Q On
Segment A-P On
I
I
1
1
I
I
I
I
I
I
I
I
I
I
I
I
=On)
1
1
1
1
1
1
1
1
1
I
1
1
1
1
1
1
1
1
I
I
I
I
I
I
I
1
I
I
1
1
1
1
1
1
1
1
1
1
1
I
I
I
I
I
1
I
I
I
I
I
I
1
1
1
1
1
1
I
I
I
I
I
I
1
1
1
1
1
1
I
I
I
I
I
1
I
I
1
I
I
1
1
1
I
I
I
I
I
I
1
1
I
1
1
I
,
1
I
1
1
,
I
1
1
,
1
I
1
I
I
1
I
1
1
1
I
I
1
1
I
1
I
1
I
1
I
I
I
I
I
1
I
I
1
1
1
1
1
I
I
I
I
1
1
I
1
I
1
1
I
1
I
I
1
I
I
I
1
1
1
1
1
1
I
I
I
I
I
I
I
I
I
1
I
1
I
I
1
1
I
1
1
1
I
1
I
1
1
I
1
1
1
I
I
I
1
1
1
I
1
1
I
I
1
I
I
I
1
I
I
I
1
I
I
I
I
I
I
1
1
I
I
I
1
1
I
I
I
I
1
1
1
I
I
1
I
1
1
I
I
1
I
I
1
I
1
1
1
1
1
1
1
I
1
I
I
,
1
1
i'
1
1
l'
1
I
I
'1
1
I
I
I
I
1
1
1
1
1
1
1
I
1
I
I
NOTES:
Sets comma and decimal outputs for 'last character entened.
•• Sets decimal output for last character entened:
5-47
1
1
I
I
I
I
I
I
1
1
I
1
1
1
I
I
I
I
,
I
1
1
1
I
I
1
I
1
I
I
I
1
1
I
1
1
I
I
I
I
1
1
I
I
1
I
I
I
I
1
I
"
l~
1
1
'I
1
1
I
,1
1
I
1
1
1
1
1
I
I
I
I
I
B argraph
Codes
I'
I
I
I
,
1
1
I
I
1
1
I
1
1
1
1
1
1
1
I
1
1
1
1
1
1
1
1
1
1
1
I
1
1
I
1
I
1
1
,..
l'
AIphanumerlc
and
Special
Codes
1
I
I
,.JL
Bargraph .& Numeric Display Controller
10951
TYPICAL SYSTEM HOOK-UP
current for zeners. Pull down resistors RA and RG are determined by the interconnection capacitance between the 10951
and the display.
Figure 4 shows the 10951 driven by a Host System as it would
be connected io a V-F display. EK is determined by the V-F .display specifications and Rc is selected to provide proper biasing
+5
v••
DATA
10~f
10951
15V
'-----4--.-.4 VDD
Rc
CLOCK
+5
ADX
A
TYPICAL
ANODE
(SEGMENT)
TYPICAL
GRID
(DIGIT)
I-_Mr--+-+-------~V-F DISPLAY
-Y D1SP
Figure 4. Typical System Schematic
5-48
HOST
SYSTEM
SECTION"6
MICROCOMPUTER DEVELOPMENT SYSTEMS
Page'
Product Family Overview ..... : ........................... :.................
6-2
Rockwell Design Center (ROC)
RDC-1001 and RDC-1002 ROC System ....................................... 6-3
RDC-1 XX and RDC-3XX ROC R6500/* Personality Set. . . . . . . . . . . . . . . . . . . . . . . . . ..
6-9
RDC-502 and RDC-504 R6502-R65C02 Personality Set .................. , ....... 6-13
RDC-2000 R6500 Cross Assembler for Intel Development System .................. 6-17
System 65 Development System (Optional Modules)
.
'
M65-1XX and M65-2XX System 65 R6500/* Personality Set ....... , ...... ; ........ 6-19
M65-001, M65-Q02, and M65-Q03 User 65 Module ..............•................ 6-23
M65-031 andM65-032 16K Static RAM Module .' ........................... , .... 6-28
M65-040 PRo.M
Pr~gramr'ner ModUle ...................... '.f
... : .............
6-31
M65~045PROM/ROM..Module ~ ................., .............................. 6~39
M65-060 ,Extender Card .................... "'. :" ..... 0'., , .. ; .• ; .. ',,' .•... , .6-:43
M~5-07'{ Design protot~ping
Module ........ , ............ : ........ ;.: '.'. '. ...... 6.-44
M6S-660 Macro Assembler and Linking Loader ..• , ...• , ......... ,., , ........ , .. 6-46
S()ftware Prep.rationSystem '
SPS-200. Soft,ware, Preparation System' Peripheral Connector Module ...... ,,' ......... '648 '
6-1,
MICROCOMPUTER DEVELOPMENT SYSTEMS
Low Cost, Flexible Systems Work With Multiple p,Cs
To support product development, Rockwell offers a range
of microcomputer development systems, each extremely
economical when compared on a cost/performance basiS
with competitive deyelopment systems.
,"
'.
Rockwell A.IM 6!imicrocomPuter desCrtbedJn
Section 7 functions as an extremely low cost, expandable,
development system when used, with the Rockwell Software
Preparation System kit. The Rockwell Design Center (ROC)
is an excellent, low cost, disk based development system,
allowing concurrent development of up to four target R6500
and R6500/" systems.
The ROC is an easy to lise, powerful development system
for multi-chip and one-chip R6500 systems. A full line of
support modules, macro assembler, link editor and high
level PU6!i. language are also available. R6500" personality
modules, 'additional RAM and a PROM programmer help
add versatility.
The ROC supports the growing trend to using single-chip
microcomputers as slaves with multi-or single-chip
'microprocessor systems. The advantages of' slaves include
both cOst and technical ~vings, such ,as eliminating some
. complex timing relationships. With the ROC, up to four
different microprocessor personality niodules can be
performing in-circuit-emulation under control of the system.
The ROC mainframe is constructed modularly, using the
proven "RM Eurocard deSign, so it can be expanded readily,
as needed. The terminal unit includes CRT, disk drives, and
keyboard. Up to 1.28 Mbytes can be addressed on the two
96 TPI, double sided, double denSity, 5 Y4-inch disk drives.
The ROC allows designers to economically and efficiently
develop multiple 'microcomputer systems, regardless of the
microcomputer device involved. Personality sets and target
RAM modules are available for all R6500 and R6500/"
,configurations.
nia
Rockwell Design Center Development System
6-2
RDC-1001/2
Microcomputer Development Systems
'1'
Rockwell
RDC-1001/2
ROCKWELL OESIGNCENTER (ROC)
INTRODUCTION
For users who already have an Intel ISIS II with mass storage
program management, an R6500 cross-assembler is available.
This. allows the RDC to fUnction as a satellite, providing a powerful debug system. The ROC is also capable of receiving files
trom the Rockwell SYSTEM 65 Microcompllter.
The Rockwell Design Center (RDC) is a development system
vertically integrated to support the entireR6500family of microprocessors and microcomputers. The RDC allows emulation,
development, and software debugging of up to four separate
microprocessors and microcomputers concurrently, even if the
four devices are different members of the R6500 family. The
RDC is a disk-based system wijh two 96 TPl, double-sided,
double-density 5V4-inch floppy disk drives that provide a storage
capacity of up to 1.3M bytes of data (formatted).
When used with the R65001* Microcomputer or R6502-R65C02
Microprocessor Personality Sets, the ROC is a powerful emulation system for the complete family of Rockwell R6500/' onechip microcomputers or NMOS R6502 and CMOS R65C02
families of microprocessors. The multiple target bus structure
of the ROC allows the user to emulate four devices concurrently,
and at different speeds.
A unique bus structure provides a separate system bus and four
target busses which can operate at different speeds (up to 4
MHz). Construction of the RDC is modular based on the proven
RM 65 design using both single- and double-sized Eurocards
and highly reliable DIN 41612 pin and socket connectors. The
double Eurocards allow use of both the system bus and a target
bus which can operate at different speeds.
Featuring Softkey function keys, the RDC eliminates the need
for an operator to learn extra key strokes and command structures. A command line of operating modes is displayed across
the bottom of the CRT screen so that the user need only push
the corresponding function key to command the RDC to enter
the mode of operation desired.
FEATURES
Rockwell Design Center. System
Hardware
Functional
• Modular construction based on proven RM 65 archijecture
• Self-contained, disk-based operating system
• Softkey function access to menu-driven operational modes
•
•
•
•
Highly reliable, standard DIN 41612 pin and socket connectors
Non-glar(:! 12-inch CRT, green phosphor
Detachable full ASCII. intelligent keyboard
Dual 96 TPI, double-sided, double-density 5V4-inch floppy
disk drives
• Text Editor
• R6500 Macro Assembler/linking Leader
• SYSGEN configurable to user environment
• Automatic power-up initialization of system and configurations
• Separate system and target memory map
• 4 target simultaneous emulation
• Real-time in-circuit emulation, up to 4 MHz
• Five hardware breakpoints per target, 32-bits wide with' 'don't
care".. bits
• Separate ~system bus and· four independent target busses
•. Two serial ports...:...one for RDC terminal interface-one for
host system download
• Two parallel ports-one for RDC terminal interface-one for
external printer
•
•
•
•
64K byte RAM system memory
Internal self-test panel for system troubleshooting
Three separaie CPUs for keyboard, CRT, and system control
DeSigned for built-in PROM programmer option
• . Inside or outside window breakpoint with 1 byte resolution
• COl1figurable as a satellite for an Intel ISIS II host system
or .RoCkwell SYSTEM 65
• Self-test software
Data Sheet Order No. RDC04
Document No. 29655N04
Rev .. 2, December 1983
6-3
Rockwell Design Center
RDC-1001/2
PRODUCT OVERVIEW
FUNCTIONAL DESCRIPT.ION
The ROC consists of three assemblies; the mainframe, a CRT
terminal wtth floppy disk drives and a full ASCII keyboard. The
mainframe contains the following components:
•
•
•
•
•
•
Major Components and Interfaces
The block diagram shows the archttecture of the ROC system
and identifies the relationship between the system bus and the
target busses. Although the block diagram shows only one
Target Interface, it represents thearchttecture of each 'of the
four target busses. The terminal keyboard interfaces with the
ROC system through one of the RS-232C ports (J3 connected
to the ACIA module). The CRT interfaces with the ROC system
through a parallel port (J3 connected to the MPI module). The
disk drives intE1rface to the ROC system through a separate port
(J2 ,connected to the FOC module). All other control functions
of the ROC system interface directly through the ROC system
bus. Note that the Personality Set PMC module interfaces the
ROC system bus to the target bus.
The system bus and target/user busses
Power supply and system cooling fans
Two 32K Oynamic RAM modules for system memory
Single Board Computer (SSC) module
Floppy Oisk Controller (FOC) module
Asynchronous Communications Interface Adapter (ACIA)
module with 2 channels for keyboard interface and user
'
RS-232C
• Multi-Iunction Peripheral Interlape (MPI) module with two
ports for interface to the CRT terminal and to a printer
• 24-pin and 28-pin PROM sockets for optional PROM Programmer module
a
Bus Structure
The terminal assembly consists Of non-glare 12-inch, green
phosphor CRT, a video display controller module, and two, 5%inch floppy disk drives. The keyboard is intelligent for full ASCII
operation.
OPTIONAL ~6500I. or R6502·A65C02
PERSONALITY SET
r--- --- ---- -,
I
I
I
I L--_---' '"---,.------l
L ______ _
The ROC system operates through a multiple bus structure-a
system bus and four target busses. The system bus contains
21 card slots to accommodate single Eurocard modules or
,------,
II
EXTERNAL
II
I PRINTER
I
L_,_...J
I
I PARALLEL
I
KEYBOARD
32K
RAM
MODULE
J1
TWO
5Y4~
FLOPPY
DISK'
DRiVeS
CRT/FDe
RD,C !ERMINAL
PROM
SOCKETS (2)
ROC MAINFRAME
ROC System Block Diagram
6-4
Rockwell Desigh Center
RDC-100.1/2
double Eurocard modules. Double Eurocard mod\Jles plugged
into the system bus are. common to the system bus and the
target bus. Double Eurocard modules (such . as the R6500/*
Personality Set PMC module) are used for microcomputer
emulation support. Single Eurocard module connectors on the
system bus are used to interface with RDC microcomputer
system modules such as the 32K RAM(2), SSC, FDC, ACIA,
and MPI.
intended for plugging in a target (emulation) RAM module(8K
x 8 or 64K x 8 depending upon the microcomputer to be
emulated). These three target busses are color coded (blue.
[ed, and yellow) on the RDC card cage for easy identification
of the division of the target b~s segments. The fourth target bus
consists of nine .Euroconnectors, four of which wHI accept double
Eurocard modules and five of which will accept single Eurocard
modules .
The four target busses are segmented so that four separate
emulations can be controlled by the systernconcurrently. t.hree
of the target busses have four card slots ·each. Three of these
slots will accept double Eurocard modules, and the fourth will
accept a single Eurocard module. The double card slots are
intended for a Personality Module Controller (PMC) module and
future growth up to two Analyzer modules. The single card slot is
A typical single target emulation configuration will consist of an
R6500,. or R6502-R65C02 Personality Set (comprising a PMC
module, Personc;liityPod, and Emulator Interface) and a target
RAM module, as a minimum. Since up to fourfuliy configured
emulation system.S can be supported concurrently, the RDC
could be configured with any combination of four R6500/"
R6502-R65C02Personality Sets, and four target RAM modUles
in addition . to the RDC system control modules.
..
or
POWER SUPPLY - - -
- " ' - - - - TARGET BUSSES
_ _ _-
SYSTEM BUS
J4
PRINTER
PORT
_ - - - CARD CAGE
J3
PROM PROGRAMMER
SOCKETS
VlDEO·KEYSOARD
PORT
Jl
POWER SWITCH
RS232C
PORT
ROC MAINFRAME FRONT VIEW
RPC MAINFRAME BACK VIEW
TARGET
BUSSES
SYSTEM
BUS
ROC CHASSIS CARD CAGE
ROC Inter(lal Layout and Card Cage Bus Structure
6-5
RDC-100112
Rockwell Design Center
Operating Modes
The'ROC bootstrap ROM is initiated whenever the system is
pOwered-up. The' bootstrap program then loads the SYSGEN
data ilnd system pr()gram from the system disk drive. When the
bootstrap is completed the CRT displays aSoftkey menu for the
function keys on the keyboard. It is this menu that prompts thE!
user to select the mode of operation required. The Softkey
prompts displayed at this time are:
Each Softkey prompt, when selected by the function key, invokes
new set of Softkey prompts which further define the tasks to
be performed by the mode. As an example, if the LOCAL prompt
is selected, a new Softkey prompt menu displays:
a
UTILITY,
DEBUG
HELP
If UTILITY is selected from this prompt, a new menu displays:
SATELLITE
LOCAL
HEOLP
SYSGEN
DISK
These Softkey prompts reprllsent the primary modes of ope,iltion for the ROC system. When the function key corresponding
to the CRT prompt location is pressed, one of the following
modes is selected: .
COpy
-This mode allows the user to modify the diskette". stored system parameters on either a permanent
(until another power-up condition) or a. temporary
basis.
HELP
-This mode dis.playsinformation which briefly
describes the oPerational mode options available
in SATELLItE, LOCAL and, SYSGEN modes. AU
Softkey menus include a HELP which is always
loclltedonthe CRT screen directly over the far
right hand function key on the keyboard.
Mode
Ll
HELP
BACKUP
FORMAT
DIR
INIT
HELP
This hierarchy continues until all parameters of the tasks of the
mode selected have been established. At any time during the
mode selection process the user has the option of calling back
the previous set Of Softkey menu prompts by simply pushing the
- (minus) key.
-This mode provides the menus available to the
user from within the ROC without requiring host
resources.
SYSGEN
EXEC
Selecting DISK invokes a new menu which asks:
SATELLITE-This mode provides the menus available f()r inter'
facing the ROC as a satellite to the host system
(InteIISIS"II)
LOCAL
FILE
The illustration shows the depth to which the command line
prompts guide the user through selecting the desired mode of
operation.
Command Line Prompts
SATELlITE_ DOWNLOAD (ISIS II or SYSTEM 65 PROTOCOL) • HELP
L_ L L L ,= ..eo=,. . "'''
LOCAL _ _ UTILITY· DEBUG' HELP
L- "'~" ."~, • ~~~~. ~, • ~ •
~
"~'nm'
","m~,",'~~·",,,
NORMAL • STEP • DEBUGGER • HELP
.
. '
NORMAL • STEP • HELP
.
.
BP#1 • BP#2<' BP#3' BP#4 • BP#5 • CLEARALL • HELP
DISPLAY' CHANGE' LOAD' SAVE' HELP .
DUMp·, MODIFY' TEXT. DISASN • SAVE· VERIFY' LOAD. HELP
DISK' FILE. EXEC. HELP
L'
LI
I. .
. TEXT EDITOR' MACRO ASSEMBLER 'PROM PROGRAMMER· USER FILES
LIST' DELETE. RECOVER. RENAME' DIRECTORY. HELP
COpy. BACKUP' FORMAT' DIRECTORY. INIT • HELP
.
~
SYSGEN
KEEP. HOST. PRINTER' TARGETS' BEEPER' DISPLAY' HELP
L-.. CURRENT· TARGET 0 • TARGET 1 • TARGET 2 • TARGET 3 • HELP
• PARITY' HI BAUD. LOW BAUD' WORD LEN. STOP BITS' HELP'
SAVE SYSGEN ON DISKETTE
HELP
MODE COMMAND LIST EXPLANATIONS
..'
Command Line Hierarchy (Typical)
6-6
ROC.. 1001/2-
Rockwell Design Center
INTERFACE
Interface between the ROC system control modules and the port
connectors on the back panel are made through ribbon :cables.
The ribbon cables are permanently attached to thE! port connectors. The terminal interfaces to the ROC system through tWo
cables with mating cOnnectors
each end that are keyed" for
proper installation. The ROC Cable 'Interface figure shOws how
these cables are routed in the system. The Self-Test Panel
interface ribbon cable is attached to the test panel and has a
connector on the other end that mates ,to the SBC mpdule VO
connector. The optional PROM programmer module conne.cts
, to the two PROM sockets through a single ribbon cable.
on
RDC MAINFRAME
PROM
NOTE:
SOCKETS
CD Ribbon cables are physically attached to RDC ~alnframe
connectors Jl through J4 and ha"e connectors on the
other end that inate to the modulea.
ROC Mainframe Internal/External Ribbon Cable Connections
SPECIFICATIONS
ROC Terminal
Parameter
RDC Mainframe
CRT/FDD
Keyboard
3in. (1.62 cm)
20 in. (50.80 cm)
8 in. (20.32 cm)
Dimensions
Height
Width
Depth
11 in. (27.94 em)
20 in. (50.80 em)
18 in. (45.72 em)
14 in. (35.56 em)
20 in. (50.80 cm)
16 in. (40.64 cm)
Weight
40 Ibs. (18 Kg)
42 Ibs. (19 Kg)
Electrical
AC Input Voltage
AC Frequency
Fuse Requirement
Environmental
Temperature
With/Disk Media
Humidity
105 to 125 (RDC-l001)
210 to 250 (RDC-l002)
47 to 63 Hz
3 A slo-blo (ROC-tOOt)
1.5 A slo-blo(ROC-l002)
105 to 125 (ROC-l00l)
210 to 250 (FlOC-l002)
47 to 63 Hz
3 A slo-blo (ROC-l 001)
1.5 A slo-blo (ROC-l002)
59°F to 104°F (15°C to 40°C) operating
-4°F to 140°F (- 20°C to 80°C) shipping
-4°F to 122°F (-20°C to 50°C) storage
20% to 80% non-condensing operating"
1% to 95% non-condensing shipping
1% to 115% non-condensing storage
NOTE: "Disk media maximum wet bulb temperature 84.9°F (29.4°C)
6-7
6 Ibs. (2.7 Kg)
RDC-1001/2
Rockwell Design Center
ORDERING INFORMATION
Part Number
ROC-I 001
ROC-I 002
RDC-IOIO
ROC-I 011
RDC-IOI2
ROC-I 030
RDC-2000
Order Number(2 )
RDC06
RDCII
RDCI2
RMOS
RMIO
RMIS
RM24
RMII
Description
ROC System (100 Vac)(')
ROC System (220 Vac)(')
32K System RAM Module
8K Target RAM Module
64K Target RAM Module
PROM Programmer Module
R6S00 Cross Assembler for Intel ISIS II
PERSONALITY SETS
Personality Sets are available for the ROC that allow emulation,' development, and software'debugging of the complete
family of R6500/' Microcomputers and R6502-R65C02
Microprocessors, The microcomputers and microprocessors
supported by these Personality Sets are:
,
•
•
•
•
Document Title
ROC R6S00'· Personality Set Data Sheet
ROC R6502-R6SC02 Personality Set
Data Sheet
ROC PROM Programmer Data Sheet
ACIA Module Data Sheet
SBC Module Data Sheet
FDC Module Data Sheet
MPI Moduie Data Sheet
32K Dynamic RAM Module Data Sheet
R6500/11P
R6500/12P
R6541Q
R65Cltl2
• R6504
• R6512
•
•
•
•
•
•
R6500/13P
R6500/41P
R6501Q
R65C112
R6505
R6513
•
•
•
•
•
•
R6500/42P
R6500/43P
R6502
R6506
R6514
R6500/1P
•
•
•
•
•
R6511Q
R65C02
R6503
R650?
R6515
For complete information on ordering any particular
Personality Set or groups of Personality Sets, refer to the
ROC R6500/· Personality Set Data Sheet, Order Number
ROC06, or ROC R6502-R65C02 Personality Set Data Sheet,
Order Number ROCII,
Notes:
(I) Both system configurations are shipped with the following
components:
• ROC Mainframe
• ROC Terminal with 12" CRT and Dual SV4" Floppy Disk
Drives and detached Keyboard
• Six System Control modules-ACIA, FDC, sec, MPI,
and two 32K DRAM
• All Required Interface Cables
• Software Package (Utilities, Text Editor, Macro
Assembler)
• Documentation Package
(2) Documents provide further information about the ROC system,
6-8
ROC-tXX. ROC-3XX
Microcomputer Development Systems
'1'
RDC-1XX AND RDC-3XX
ROCKWELL DESIGN CENTER
R6500/* PERSONALITY SET
Rockwell
INTRODUCTION
FEATURES
The ROC, R65001* Personality Set is a ROckwell Oe!lign Center
(ROC) option that allows ,the ROC user to develop, di:lbug and
verify programs intended 'for use by any R6500 one-chip microcomputer system. The R65001* offers ti1e user a high performance development system specifically, designed for emulation
of a microcomputer system. This ROC option supports in-circuit
emulation for the entire R6500 family of one-chip microcomputers.
•
•
•
•
•
•
•
The basic R6500/* Personality Set includes a Personality Module
Controller (PMC), two Personality Emulator Pod Modules, a
Device Adapter, an In-Circuit EmulatiOn Probe assembly, an
interconnect cable set, and the required software and support
documentation.
•
•
•
•
, •
The R6500/* Personality Set provides the ROC with a dual CPU
,capability. This added feature permits the ROC CPU to maintain
control, even while the R65001* is executing a program, thus
providing the user with complete control over the development
process.
Disk based macro assembler and debug monitor
Provides8K RAM in system (optional)
Supports 65K address range in target environment
Five hardWare breakpoints with SYNC outputs
User defined external break signal
Single step through interrupts
Supports four simuttaneous target developments
No zero page address confiicts
Power down capability
RAM write protection
User or system supplied power and clock
Real-time in-circuit emulation
• Menu-driven Softkey command selection
The R6500/* Personality Set can be expanded to include four
separate emulation systems which can be run concurrently on
th8
ROC.'
,
ROC R6500/* Pereonallty Set
Document No. 29655N06
a:.9
Data Sheet Order No. RDC06
December 1982
RDC-1'ix .RDC-3XX
RDC R6500/* Personality Set
USED
FdR TRACE
·A
LONG 60 PIN
RIBBON CABLE'
EMULATION POD
BOARD 1
PMCBOARD
J1
EMULATION POD
BOARD 2
I
ROC MAINFRAME
OPTIONAL
':;ONNECTOR FOR
.E, F ANI)'G
PORTS
J2
USED FOR TRACE
System 'Interconnection
RUN MODE/CONTROLLED ,EXECUTION
COMMAND SUMMARY
CONTROLLED EXECUTION MODE COMMANDS
The RS500/' Personality Selis designed to allow the.RS~OO(~ "
to .execute independent of the RDC,' Thus, wt.1.ile ~R6500/"""
is executing code, the ROC CPU is still in operation,'1'his allows
certain functions to be performed by the RDC CPU,without dis:·
turbing the execution of the RS500/',
RUN MODE COMMANDS
The RS500/" debug monitor allows. certain'comma,pds to be
performed while the RS50D(' is in ,ttie Run t)'lode5The Run
Mode commands are highligtlled as follqWs: ..
.
~: .~:, ". ,if "
"
,
The Controlled Execution Mode commands are divided into five
groups, as follows:
.. '\.
Description
.' COMMANDS TO DISPLAY MEMORY OR REGISTERS
Display or alter sixteen selacted mamory locations
Disglay or alter next sixteen memory locations
DiSplay or a~ar previous. sixtaen memory locations
Gxamine/modify RAM aoo 1/0 one byte at a time
,qump memory in H~.X and ASCII format
Invoka disassemblar
Display ora~er 'register contents
COMMANDS TO. SET PROGRAM BREAKPOINTS
,
Set or reset SoftWare braakpoint addresses
.Enable or disablesinlile step mode
Set or ,mocjify h~rdware breakpoint
O,escriptlon
RUN MODE COMMANDS
Issue Reset
•
Examine or Modify Hardware Breakpoint
Exit Run Mode
Return to ROC Operating System
Select a New PMC Module
Enable/Disable the System Pointer
Halt/Resume Run
6-10
ROC R65001* Personality8et
RDC-1XX.RDC-3XX
CONFIGURATIONS
". . DescriptIOn
The,;:ROC Personality Sets for the R6500/* Microcomputers,
shQwn i.n the chart below, include one Personality ModuleCQIltroller (Plylc), two Personality EmulatQr .Pod MOdules. a Device
Adapter,,~n In-Circuit Eml!lation Probe assembly. aninterconnect cable. set, and the required software and support documernation. The ROC Personality Sets are available either bundled
with an BK Target RAM (the 100 series part numbers inlhetable
pelow) or unbundled without the BK Target RAM (the 300 series
part numbers below), ..
.COMMANDS TO TRACE PROGRAM FLOW
Toggle instruction trace on .or off
Toggle register printout on or off
Show register form for printout
~how last nine instruction addresses
DISK FUNCTIONS
Special disk functions
Display disk directory
Delete Iile
MISCELLANEOUS COMMANDS
Wr~e protect memory blocks
Load object code
Start exeCution of user's program
.
Dump ii1emory
Issue RESET
verify object code against memory
Retum control to RDC Operating System
Initialize the current board
Enable/disable·printer
Allow single step through'interrupts
RS500/* Personality. Sets
Part Number
ROC-l01-or -301
RDC-IO;! or -302
RDC-l11 or -311
RDC-112 or -312
RDC-12! .or -321
RDC-I22 or -32;2
ROC-131 or -331
RDC-I32 or -332
RDC-141 or -341
RDC-I42 or -342
RDC-151 or -351
RDC-152 or -352
RDC-161 or -361
ROC-162 or -362
6-11
Description
. R6500/11 P Personal~ Set, I MHz
R6500/11AP Personai~ Set, 2 MHz
R65001120 Personality Set, 1 MHz
R6500/12AO Personal~ Set, 2 MHz
R65001130 Personality Set, 1 MHz
R6500l13AO Persc:inal~ Set, 2 MHz
R6500/41 P Personality Set, 1 MHz
.. f!.6500/41AP Personal~ Set, 2 MHz
R6500/420 Personal~ Set, 1 MHz
R6500/42AO Personality Set, 2 MHz
R6500/430 Personal.~ Set, 1 MHz
R6500l43AO Personal~ Set, 2 MHz
R6500/1 P Personal~y Set, 1 MHz
R6500/1AP Personal~ Set, 2 MHz
ROC-1XX • ROC-3XX
ROC R6500/* Personality Set
DEVICE ADAPTERS
IN-CIRCUIT EMULATION PROBES
The Adapter/Emulator Devices are used to reconfigure ROC1XX PersOnality Sets for use with other R6500/* Microcomputers. They replace the Adapter/Emulator Devices in the Personality Emulator Pod Module and contain the desired emulator
device.
The In-Circuit Emulation Probe assemblies used to reconfigure
the RDC-1XX Personality Sets for use with other R6S00/*
Microcomputers are shown in the chart below.
Part Numbe..
Description
Part Number
Description
RDC-200
40-Pin Probe and cable for R6500/11 P.'
Prerequisite, RDC-211 or -212
RDC-211
Adapter/Emulator Device
(R6511Q) for R6500/11/12/13, 1 MHz
RDC-201
RDC-212
"Adapter/Emulator Device
.(R6S11 AQ) for R6500/11/12/1 3, 2 MH;
64-Pin Probe and cables for R6500112Q.
Prerequisite, RDC-211 or -212
RDC-202
RDC-221
Adapter/Emulator Device
(R6541AQ) for R6500/41/42I43, 1 MHz
64-Pin Probe and caples for R6500/13O.
Prerequisite, RDC:21'1 or -212
RDC-203
RDC-222
Adapter/Emulator Device
(R6541AQ) for R6500/41/42/43, 2 MHz
40-Pin Probe and cable for R6500/41 P.
Prerequisite, RDC-221 or -222
RDC-204
RDC-231
Adapter/Emulator Device
•(R6500/1 EC) for R650011, 1 MHz
RDC-205
64-Pin Probe and cables for R6500/42Q.
Prerequisite, RDC-221 or -222
64-Pin Probe and cables for R6500/43O .
Prere<;luisite, RDC-221 or -222
RDC~232
Adapter/Emulator Device
(R6500/1EAC) for R.6600/1, 2 MHz
RDC-206
6-12
40-Pin Probe and cable for R650011 P.
Prerequis~e, RDC:231 or -232
~DC-50X
'Mierol'nmputer Development Systems
'1'
Rockwell
RDC-502 AND RDC-504
.ROCKWELL DESIGN CENTER
,R6502..R65C02' PERSONALITY SET
.
,
;INTRODUCTION
FEATURES
The ROC R6502-R65C02 Personality Set i~ a Rockwell Design
Center (ROC) o~ion~hat allows the ROC user tei develop, debug
and verify programs intended for use by any R6500 one-chip
microprocessGl' ¥tem. The R6502-R65C02 offers the user a
;high performance development syStem specifically designed for
emulation of.a microproc~r ~m. This ROC option supports
in-circuit emulation for the entire R6500 and R65COO family of
one-chip microprocessors.
• Disk based macro ,assembler and debug monitor
The basic R6502-R65C.02 Personality Set includes a Personality
Module Controller (PMC), two Personality Emulator Pod ModuleS;
five emulator devices (R6502, R6512, R65C02, R65C102, and
R65C112), two prototype-ta-pod interface,cables, an ROC interconnect cable set, and the. required $oftware and support
'
'documentation.
The R6502-R65C02 Personality Set provides the ROC with a, dual
OPU 'capability. This added feature permits the ROC CPU to
maintain control, even while the microprocessor is executing a
,program, thus providing the 'user with complete cont,rol over the
development process.
'
•
•
•
•
Provides 8K or 64K RAM in system (optional)
Supports 65K address range in target environment
Five hardware breakpoints with SYNC outputs
User defined external break signal
• ~ingle step through interrupts
• SuPport.s four simultaneous target developments
• No zero page addre,ss conflicts
•
•
•
•
•
Power down capability
RAM write, protection
User or systern supplied p~r and clock
Real-time in-circuit emulation
Menu-driven Softkey command selection
,The R6502-R65C02 Personality Set can I:/e expanded to include
. lour SePlirate emuilltioll systems which can b.e ;run concurrently
'on the ROC.
•
'
'
•• 1
ROC R6502-R65C02 Personality Set
Data Sheet Order No. RDC11
, December 1983
Document No. 29655N11
6-13
ROC R6502-R65C02 Personality Set
ROC-SOX
40 PIN RIBBON
LONG 60 PIN
RIBBON CABL~
r-----
CABLi~"
___
,,~,,2
_
-'-"~.,
rr::"iI=:--''--n CONNECT'"
TO 40 PIN
DEVICE'"
CO"NNECTOR
'-'-_ _~ ON
PROTOTYPE
I
I
OR
CONNEct
TO 28 PIN
DeVICE
CONNECTOR
'--............. ON'
"
I
I
I
I
I
I
I
I
I
I
!~T~~~_~
PMC BOARD
J6
J1
J5
28 "PIN
RIBBoJ.!
CABLE"
EMULATION POD
BOARQ 2
",,:':"
ROC MAINFRAME
System Interconnection
RUN MODE/CONTROLLED EXECUTION
COMMAND SUMMARY
"
CONTROLLED EXECUTION MODE COMMANDS
The Controlled Execution Mode commands are divided into five
groups, as follows:
The R6502-R65C02 Personality Set is designed to allow R650X,
R651X or R65XXX devices to execute independent of the ROp.
Thus, while the emulator is executing code, the ROC CPU is
still in operation. This allows certain functions to be"performed
by the ROC CPU without disturbing the execution of the emulator
device.
"
Description
COMMANDS TO DISPLAY MEMORY OR REGISTERS
Display or alter sixteen selected memory locations
Display or alter n,elCt sixteen memory locations
Display or alter previous :sixteen memory locations
Examine/modify RAM and 'I/O one byte at a time
"Dump memory in Hex and ASCII format
Invoke disassembler "" "
Display or alter register contents
RUN MODE COMMANDS
The R6502-R65C02 debug monitor allows" certain commands
to be performed while the emulator is inthe Run mode;:The Run
Mode commands are highlighted" as fonows:
"0/
TO
COMMAr:mS
SET PFIOGRAM BREAKPOINTS
Set or reset software breakpoint addresses
Enable or disable single step" mode
Set or "modify hardware breakpoint
Description
RUN MODE COMMANDS
Issue Reset
Examine or Modify Hardware Breakpoint
Exit Run Mode
Return to RDC Operating System
Select a New PMC Module
Enable/Disable the System Pointer
Halt/Resume Run
6-14
RDC R6S02-R6SC02 Personality· Set
RDC-SOX
CONFIGURATIONS
Description
The ROC Personality Sets for the R6502-R65C02 Microprocessors, shown In the chart below,lncludes one Personality
Module Controller (PMC), two Personality Emulator Pod
Modules, one Emulator Device set, an interconnect cable set,
and the required software and support documentation.
COMMANDS TO TRACE PROGRAM FLOW
Toggle instruction trace on or off
Toggle register printout on or off
Show register form for printout
Show last nine instruction addresses
DISK FUNCTIONS
Special disk functions
Display disk directory
Delete file
R6502~R65C02
MISCELLANEOUS COMMANDS
Wrne protect memory blocks
Load object code
Start execution of user's program
Issue RESET
Verify object code against memory
Return control to ROC Operating System
Initialize the current board
Enable/disable printer
Allow single step through interrupts
PMCTO EPM2
INTERCONNECT
CABLE
(SO PIN)
Personality Sets and Memory
Part Number
Description
RDC-502
RDC-504
R6502-R65C02 Personality Set, 1-2 MHz
R6502-R65C02 Personality Set, 4 MHz
ROC-lOll
RDC-l012
8K RAM Target Memory, 1-2 MHz only
64K RAM Target Memory, 1-4 MHz
EPM1 TO EPM2
60-PIN
INTERCONNECT
CABLE
PMCTO EPM1
INTERCONNECT
CABLE
(60 PIN)
211-PIN .
PROTOTYPE-TO-POD
INTERFACE CABLE
Typical R6502-R65C02 Personality Set Hardware Components
6-15
ROC-SOX
ROC .R6502-R6SC02 Personality Set
R6502-R65C02 Personality Set Component List
QUANTITY
ITEM'
DESCRIPTION
1
PMC Module
Controller module that plugs into the RDC Mainframe,
1
Emulator Pod
Module Assembly
Pod that contains EPM-l and EPM-2, a shorf ribbon cable, a six-wire power cable,
and the R6502 Emulator Device.
1
Emulator Package
Package contains the R65l2, R65C02, R65Cl02 and R65Cl12 Emulator devices
and 5 jumper headers for the 28-pin processors.
2
PMC to Pod
Interface Ribbon Cables
(Long Length)
One cable with 60-pin connector on each end with one cable with a 50-pin
connector on each end.
2
Prototype-to-POd
Interface Cables
(Medium Length)
One of two possible configurations:
a. One ribbon cable with 40-pin connectors on each end. Used for emulating, the
R6502, R65l2, R65C02, R65Cl02 or R65Cl12.
b. One cable with a 28-pin connector on each end. Used for emulating the R6503,
R6504, R6S0S, R6506, R6S0?, R65l3, R6514 or R6515.
6-16
··flDC-2000
Microcomputer Development Systems
'1'
Rockwell
RDC-2000
R6S00 CROSS ASSEMBLER
FOR INTEL DEVELOPMENT SYSTEM
CROSS ASSEMBLY
FEATURES
The R6500 Cross Assembler provides the user with the capability of developing assembly language programs on the Intel
Development System and downloading these. programs to !h~
Rockwell Design Center (ROC) for debugging and in-circuit
operation.
• Intel Development System Host
• SuppOrts Rockwell's 8-bitCPU devices:
-R6500 NMOS microprocessor family
-R6500r NMOS microcomputer fa~ily
-R65COO CMOS microprocessor family
• Symbolic notation-operands and l.abels
• Interactive assembler operation
• Operator selected object code output devices
-Display/printer
-Printer
-Floppy Disk
-DownlOad to ROC
• Operator selected assembly/error listing output
-Display/Printer
-Printer
-Floppy Disk
• Assembler directives
• Symbolic cross-reference
• Communications support-downloading of object code
The process of translating microprocessor instructions for a.
computer program written in symbolic .form 10 executable
machine instructions is called art assembly, and the computer
program that performs this translation is called an assembler.
Assemblers that run on a host computer different from the target
computer that the generated machine code is to operate in are
called cross assemblers. One assembly language statement
usually translates. into a single processor instruction.' ,Each
statement consists of a label (if required), a mnemonic operation
code, an operand (if required), an arithmetic operator (if. required)
and an optional comment. Constants comprising one or more
bytes of memory are generated from data statements while one
or more bytes of memory are assigned to variables. This cross
assembler is a symbolic assembler that allows the programmer
to represent memory locations and numeric values with names
or symbols.
PRODUCT OVE.RVIEW
The R6500 Cross Assembler for the Intel Development System
allows users who have acCess to such a system and are accustomed to its text editor (ISIS CREDIT) to enter and .edit source
code, assemble the program and save both the source and
object code on floppy disk. The object code can then be loaded
into a Rockwell Design Center (ROC) for program debugging
and in-circuit validation using an R6500, R6500/' or R65COO
Personality Set. Up to four personality sets can be installed in
one ROC Main Frame to maximize the utility of one Intel Development System and ROC. The object code can also be programmed into PROM/ROM for execution by an R6500 NMOS
or R65COO CMOS microprocessor or masked in R6500r NMOS
one-chip microcomputer ROM for execution.
The disk-base.d R6500 cross assembler is a two-pass symbolic
assembler which produces absolute 6500 object code. It performs symbol (1-6 characters) definition, syntax checking,
assembly/symbol table listings and cross reference generation
for effective program development. Assembler operation is
automatic once started.
ORDERING INFORMATION
Part No.
RDC-20.00
Order No.
RDC02
Description
R6500 Cross Assembler for Intel Development
System Disk (8" ISIS II compatible disk)
Description
R6S00 Cross Assembler for Intel Development
System User's Manual (included with RDC-2000)
SYSTEM REQUIREMENTS
The Intel Development System must provide 64K bytes of
memory and the Dual-Density Drive option to sUPport the R6500
Cross Assembler. 32K bytes are then available for application
source code. The other 32K bytes contain the ISIS system (14K)
and the cross aSsembler (18K).
The assembler outputs to the console the pass it is currently
performing and a dot for every 16 lines of source code assembled. Thisenables viewing of the assembly process and observation of detected errors. List (.LST), object (.OBJ), and symbol
(.SYM) files are automatically generated with the source. name
assigned as the header and the particular extension added.
Data Sheet Order No. RDC09
March 1983
Document No. 29655N09
6-17
R6500. Cross Assembler for Intel Development System
RDC-2000
Assembler Directives
ASSIImbly Llstln, Control
.TTL
Title
. PAGE
pag~"
.LlNE
Page Length
,WIDTH.
'Line Lengtll .
SkiP'
;SKJP
'~.,
Source File Control
.END
End of Assembly
.MOD
Assembly Type
.
Data Storage .
. BYTE
.wORD
.DBYTE
,SBYTE
Initialize bylememdiy localion
Generate 1s·bit. address
.
Generate 16-bit data word
Initialize AC~IIS!rin!l .
Equate
Assign value t6 symbol
Error Codes
P• .a2··
Paaa 1
'.
'"
1 OPERAND VALUE IS INVALID OR GT HEXFFF.F
2 OPEMND VALUE IS GREATER THAN HEX FFFF
3 INCoRRECT ADDRESSING MODE
4 SYMBOL NOT PREVIOUSLY DEFINED
, ."
S NO O~E;RAND.
6 ASCII STRING NOT PROPERLY ENCLOSED
7 MISSING .END STATEMENT
8 UNDEFINED ASSEMBLER DIRECTIVE
9 IMPROPER EQUATE FORMAT
10 UNRE;COGNIZABLE ASTERISK DEFINITION
11 INDIRECT ADDRESSING OFF OF ZERO PAGE
12 INCORRE:CT FORM OF INDIRECTADDRESSIN
<
6-18, ,-
Operation
Addition
Subtraction
High-Byte Selection
Low-Byte Selection
M65-1XX. M65,;.2XX
"
"
• 'I, '
~.
,
Microcomputer Development Systems
'1'
Rockwell
M65-1X)( AND M65-2XX
SYSTEM 65
R6500/*PERSONALITY SET
.INTRODUCTION
FEATURES
The RockWell R65OO1* Personality Set is a System 65 Devel'opment System option that allows the System 65 user to develop,
debug and verify special programs intended for use by any
R6500 one-chip microcomputer system. The R6500r offers the
user a high performance development system specifically
designed for emulation of a microcomputer system. This System
65 option supports in-circuit emulation for the entire R6500
family of one-chip microcomputers.
•
•
•
•
•
•
•
•
•
•
•
•
The basic R6500I* Personality Set includes a Personality Module
Controller (PMC), two Personality Emulator Pod Modules, a
Device Adapter, an In-Circuit Emulation Probe assembly, an
interconnect cable set, and the required software and support
documentation.
Disk based macro asse~bler and debug monitor
Provides 8K RAM in system
Supports 65K address range in target environment
Two hardware breakpoints with SYNC outputs
"User defined external break signal
Single step through interrupts
Supports four simultaneous tar!:let developments
No zero page address conflicts
Power down capability
RAM write protection
User or system supplied power and clOck
Real-time in-circuit emulation
RUN MODE/CONTROLLED" EXECUTION
MODE COMMANDS
.
The R65001* Personal~y Set provides the System 65 with a dual
CPU capability. This added feature perm~s the System 65 CPU
to maintain control, even while the R65001* is executing a program, thus providing the user w~h complete control over the
development process.
The R6500r Personality Sel' is designed to allow the R6500/*
to execute Independent of the System' 65. Thus, while the
R6500/* is executing c,ode, the System 65 CPU is still in operation. This allOws certain functions to be performed by
the System 65 CPU withC1ut disturbillg the execution of the
R6500/*. Tables 1 and 2 list the commands for the Run Mode
and Controlled Execution Mode respectively. The R6500/,* debug
"monitor allows certain CommandS. to be. performed while the
. R6500/' is in the Run mode.
The R6500/* Personality Set can be expanded to include four
: separate emulation systems which can be run concurrently on
"the System 65 Development System.
. System 65 R6500/* Personality Set
Data Sheet Order No. 2132
Rev. 1, June 1983
Document No. 29651N35
6-19
M65.. 1xx. M65.. 2XX
System 65 R6500/* Personality Set
Table 1. ,Run Mode Commands
Command
I
C
0
ESC
F
•
$
Table 2.
R6500r Personal1ty41110<1ule S~s
DescilpttOn
.'
Issue reset
Examine or modify hardware breakpoint
Exit run lJ1O(je
Return to· System 65 monttor
Select a new PMC board
Give board number/emulator model
Enable/disable the system pointer
Halt/resume run
Part Number
"
DeScription
Commands to Display Memory or Registers
M
Display sixteen ~ected memory locations
Display next sixteen memory locations
Display preYious sixteen memory locations
Examine/modify RAM and UO one byte at a time
U
'Dump memory in,Hex and ASCII fonnat
Ir11l0ke disassembler
R
Display register contents
Commands to Alter Memory or RIgIs!ers
/
Atter memory locatioh,
ARer, progr!m'J counter
AHer accumulator'
A
X
ARer X register
Y
Alter Y register
P
Alter processor status
S
ARer stack pointer
,';,
"',
" ). (
Adapter/Emulator Devices 11> .
Part Number
Description
Adapter/Emulator De.vice
(R65110) for R65OOI11/12/13, 1 MHz
M65·211
',·M65-212
Adlipter/Erriulator Device
(R6511AO) for R6500/11/12/13, 2MHz
M65-221
Adapter/Emulator Device
(R65410) for R6500/41/42/43, fMHz
M65-222
Adapter/Emulator Device
(R6541AO) for R6500!41/42/43, 2 MHz
M65-231
Adapter/Emulator Device
(R6500!1 EC) for R6500/1, 1 MHz
M65:232,
Adapter/Emulator Device
(R6500/1EAC) for R6500/1,.2 MHz
~
,Commands to Set Program, Breakpoints
B
' Set or reset software breakpoint addresses
.4
Enable or di!l8ble single step mode
?
Show all software breakpoint adr;lresses
#
Clear all software breakpoints
C
Set or modify hardware breakpoint
I
I
Commands tO,Trace Program FI_
Z
Toggle instruction trace on or off
V
Toggle register prin,tout onor off
J
Show register fonn for printout
Show lasi nine instruction addresses
H
Note:
t. Used to reconfigure M65-1XX Personality Sets for use wtth
other R6500/' Microcomputers, Replaces Adapter/Emulator
Device in Personality Emulator Pod Module.
Disk Functions
Special disk ,fu~ions
1
2
Display disk directory
'"
3
Delete file
Miscellaneous Commands
W
Write project memory blocks
L
Load object code
Start execution of user's program
G
D
Dump memory .
'
I
Issue RESET
K
Verify object Codea9~nst mel1"~
o
Retum control to SVstem65 , ,
7
Relnitialize ~0I1 MoQ~or ,eitherlrom
System 65 or R65oo/'i Monitor '
8
Reenter R65OO!1 ,Monitor from System 65
'E
Enter the Text Editor
T
Reenter the Text Editor
N
Invoke the Assembler
F
Select a new PMC bOard
o
Initialize the Current board
S
E'nable/dlsable printer
Give board number/emulator model
ESC
Stop on·going process
-+
Allow single step through Interrupts
D;;terlptlon'
R6500/11P perSj)'l'jality Set'~'~H;t
R6500/11 AP 'Persd/lality Set, ,2 MHz
R6500/120PerljOrialily Set,1 ,.MHz',
R65oo!12AO pe;sonality Set; 2 MHz
R6500/130 Personality Set, 1 MHz
R6500/13AO Personality Set, 2 MHz
R6500/41 P Personality Set, 1 M\",z
R6500!41AP Personality,set, 2'MMz
R6500/420 Personality Set, 1 MHz
R6500/42AO PersOnality Set, 2'MHz
R6500/430 Persomility Set, l' MHz '
R6500/43AO Personality Set, 2 MHz
R6500/1,p PerllOnalily Set, 1 MHz
R6500/1AP Personality Set, 2 MHz
M65-101
M65-102
M65-111
M65·112
M65-121
M65·122
.M65-131
M65·132
M65-141
M65·142
M65-151
M65'152
M65-161
M65-162'
Controlled Execution Mode Commands
Command
:'
In-Circuit Emulation Probes 11>
PBrt Numbef
Description
M65-2oo
40 Pin Probe and cable for
'R6500/11 P. Prerequisite, M65-211 or 212
M65·201
64 Pin Probe and cables for
R6500/120. Prerequisite, M65-211 or 212
M65-202
M Pin, Probe and oables for
M65-2,03
4Q Pin Probe and cable for
M65-204
e 64 Pin Probe and cables for
:.""'.
M65'205
64 Pin Pro~ and cables for
R6500/13G!.:Prerequisite, M65·211 or 212
,R6500/41 P..J'terequisite, M65-221 or 222
R65OO/42Q. Prerequisite, M65·221 or 222
R6500t430. PrereqUisite, M65·221 or 222
M65-206
)
40 Pin '.Probe and cable for
R6500/1 P. Prerequisite, M65·231 or 232
Note:
1. Used to reconfigure M65·1XX Personality Sets for use with
,other R6500!' Microcomputers.
M65-1 XX. M65-2XX
System 65 R6500/* Personality Set
NOT USED
LONG 50 PIN
RIBBON CABLE
MEDIUM LENGTH
60 PIN RIBBON
J7
CABLE
J8rr-+~~~----------~
~ I
,
EMULATION POD
BOARD 1
SWIRE
POWER
CABLE
PMCBOARD
EMULATION POD
BOARD 2
J4
~
J2
NOT USED
SYSTEM 8S
_____________________________________s_y_s_w_m
__ln_t_e_re_o_n_n_ec_t_io_n________________________________
INTERCONNECT
CABLE SET
PERSONALITY MODULE
CONTROLLER
PERSONALITY
EMULATOR POD
MODULE NO.1
DEVICE
ADAPTER
PERSONALITY
EMULATOR POD
MODULE NO.2
IN-CIRCUIT
EMULATION
PROBE ASSEMBLY
Basic R6500'* Personality Set
6-21
PERSONALITY
EMULATOR POD
BOARD HOUSING.
ONE INCLUDED
WITH EACH SET
~ II[!lII
System 65 R6500/* -Personal ity Set
M65-1XX. M65-2XX
ADDITIONAL PROBES AND ADAPTERS
SELECTION GUIDE
If you already have a System 65 Personalny Set for a member
of the R6500/* family ypu need not purehase a complete new
set to support another member of the family. The following
matrix shows the minimum probes and adapters that need/o
be purchased to reconfigure your seUor another R6500/* device.
Select the device now being supported in the FROM row, find
the device you wish to support in the TO column. The PIN's in
the intersection will reconfigure your Personality Set.
~~00~/'l0~Y
:ro,
211
or·212
M65-202
MSf>202
M65-202
M65-202
MS5-203
M6f>203
M6f>221
RS500I130'
MSf>221
or 222
M65-221
M65-203
or 222
or-222
_203
M65-203
M65-2Q3
M6f>221
or 222
M65-221
ar222
M65-221
ar·222
MIl!>204
R65OO141P
R65OO14,20
RS5OOI430
or 222
111165-221
M6f>204
M65-204
!,lII5-221
'01'-222
M65-204
M6f>204
M65-204
MS5-221 . !,lIIf>22)
or 222
or 222
M65-221
or-222
or-222
!,lII5-206
M6f>206
M65-206
M6f>205
MS5-231
M6S.231
or 232
M65-231
M65-231
MS5-231
or 232
or-232
or·232
or-232
or-232
M65-2D6-
M6f>2D6
M65-2D6
M65-2D6
MS5-2D6
M64-2D6
R65OOI1P
6·22
M65-206
!,lII5-206
M6f>221
M65-231
M65-0~11, -002, -003
Microcomputer DeVelopment Systems
'1'
Rockwell
M65-P01,-002,-003
USER 65 MODULES
OVERVIEW
The U,SER 65 Module permits users developing R65OO-based
products to extend the full power of System 65 Development
System into their equipment for in-circuit emulation. Available
in both 1- and 2-MHz versions (M65-001 and 002), USER 65
supports all ten R6500 CPU's. M65-003 configuration is without
the controller.
USER 65 consists of two modules-':;a Host Module and a Buffer
Module-and two interconnE1i;t cables. The USER 65 Host
Module replaces the CPU Module in the System 65 chassis; it
performs all CPU Module functions, plus several external functions. The USER
Buffer Module extends the System 65 bus
lines (address, data, and control) to the user equipment.
as
FUNCTIONAL DESCRiPTION
USER 65 HOST MODULE
M65-001 USER ,65 Mpdule
The USER 65 Host Module shown in blOOk diagram 'replaces
the CPU Module in the System 65 chassis. It is capable of performing all functions of the CPU Module, plus external address
selection, automatic power up, and external clOCk selection. The
Host Module interface signals are listed in Table 1.,
The Host Module has automatic power-up c,ircuit consisting of
an NE555 timer (Z3) and associated discrete capacitors and
reSistors. This circuit will generate a 100 msec reset pulse fol'
lowing power-up.
The heart of the Host Module is the R6502 (Z11) microprocessor. It controls all functions of the System 65 and the user's
external equipment. Crystal Y1 (1 or 2 MHz) 'generates the
internal clock for the R6502 CPU. Switch S3 is used to select
either the internal generated clock or an externally provided
'
clock input.
The Host Module alsO contains the RS-232C and TTY baud rate
generator circu~ry. Crystal Y2 (1.8432 MHz) and baud Jate gen-,
erator MC14411 (Z13) generate a baud rate clock. The Clock
rate is muHiplied by 16 (x 16) to provide a selectable output
baud rate from 110 to 9600. Switch S4 and the SN74152 (Z12)
select the baud rate. This output is then provided to the System
65 b!l$ to be used by the Monitor Module.
The internaVexternal address selection is based on a decode of
A15-A12, using an SN74159N (Z1) decoder. This device has
sixteen active low outputs. Each output represents a 4K address
space and is selected by Switches S1 and S2. The outputs are
ORed together and in~ted by SN7406 (Z2). This eliablesignal
is then gated with R!W Signal to form a READ signal and a
WRITE signal, Which are used in the USER 65 Buffer Module.
The address lines and control lines 1111, fil2, DMA, and SYNC are
buffered with !.C.'s 8T97 (Z8-Z10, ZS).The data lines are
inverted and byffered withJ.C.8T26 (Z6, Z7). All of these lines
are brought to the System 65 bus and are also taken outto the
USER 65 Buffer Module through'series terminators (A1-A4).
The Controllin'es S.O., ROY, RES, NMI, IRQ are brought to the
System 65 bus'and are also brought from the USER 65 Host
Module, then bUffered with open collector buffer's SN7407(Z15).
These inputs come only from the user's equipment; the RESET
switch on the front panel will not reset the external eqUipment.
USER 65 Host Module Functional Block Diagram
Document No. 29650N43
6-23
Product Description Ord~ No. 220
Rev. 2, August 1983
6
M65-001, -002, -003
USER 65 Modules
System 65 bus line DMA is used to control the address and data
bus lines. This line is pulled up internally with a 3K resistor. By
pulling DMA low, the address, data and R/W lines are set to the
float state, allowing an external board to control them for DMA
operations. The DMA line does not stop the CPU-this must be
done by controlling the RDY line as outlined in the R6500
Microprocessor Data Sheet Order No. D39.
BUS LINES TO/FROM' U$ER--EOIJIPMENT
I~
USER 55 BUFFER MODULE
~
l~
;::
c
~
0
~
~
~.
~
~
~
i
;;.
0
~
~
~
i
III
18
~
:;
0
~
~
USER 65 Buffer Module Func.tlonal Block Diagram
USER 55 CABLES
The cable assembly supplied with the USER 65 option provides
the signal paths between the USER 65 Host and Bulfer Modules, and between the Buffer Mcidule and the user's equipment.
Since the USER 65 option is designed to emulate all versions
of the R6500 Family of CPU's, both a 4O-pin cable and two 28pin types of cables are provided.
INSTALLATION
USER 65 Host Board to Buffer
Board Interface Signals
USER 65 HOST MODULE
CONNECTOR J2
Install the USER 65 Host Module in the System 65 as follows:
SIGNAL
PIN
~
~
USER 65 BUS LINES
Two othersigna!s, READ and WRITE, are buffered by 25. The
READ signal is generated by the Host Module and is high when
the R/W line is high and an external address is active. The
WRITE Signal, also generated by the Host Module, is high when
R/W line is low and an external address is active. These two
lines control the data bus buffers 27 and 28.
CONNECTOR Jl
~
~
I~
The £)1 and 02 clocks are buffered by 8T97 (25). To use an
externalqlock, jumper N must be installed. To use ,fIl , jumper
M must !)einstalled. The DBE signal is provided for use during
emulation Of the R6512 CPu,. This line has aninternalpullup
res.istor of 3K. When brought 10Wit.wili disable the. data bus
drivers.
SIIONAL
c
Ii
The address lines, SYNC and R/W lines are buffered with I.C.'s
8T97 (ZI-23). The control lines RDY, RES, NMI, IRQ, and S.O.
are buffered with open collector I.C.'s SN7407 (24). The data
lines are inverted and buffered with I.C.'s 8T26A (27 and Z8).
They have series terminators of 150 ohms (29).
PIN
~
i;;.
~
The USER 65 Buffer Module receives the address, data and
control lines from the USER 65 Host Module, buffers thesesignals and intetfaces them to .the user's equipment.
Table 1.
I~
I~;::
1. Turn System 65 power off.
1
AD
1
EXT. CLOCK
3
A1
3
¢2
5
A2
5
¢.1
7
A3
7
GATED READ
9
A4
9
GATED WRITE
11
A5
11
13
A6
13
D6
15
A7
15
D5
17
AS
17
54
53
19
A9
19
A1D
21
-D2
Di'
23
All
23
25
A12
25
DO
27
A13
27
+5V
29
A\.4
29
+5V
31
A15
31
+5V
33
SYNC
33
+5V
35
R/W
35
+5V
37
RDY
37
+5V
39
RESET
39
+5V
41
NM1
iRO
45
SO
Never install or remove modules with System 65 power
on-it may cause damage to the module and/or to the
system.
D7
21
43
CAUTION
2. Remove the top cover of the System 65.
3. Remove the CPU Module.
4. Set switches Sl, S2, S3 and S4 on the USER 65 Host
Module per Table 2. The switch positions are shown in Figure 1.
5. Plug the USER 65 Host Module into anyc::onvenient slot in
the System 65 chasis.
6. Route the cables from the Buffer Module through the back
panel of System 65, through the slot provided.
7. Connect the 40- and 50-pin cables from the Buffer Module
to the top of the Host Module (the connectors are keyed with
arrows).
Note: Even-numbered pins are connected to Ground.
6-24
M~5';Q~1,
-0,02, -,003
Sf-UD RATE SELECT SWITCH
Figure 1. US,ER 65 ,Host and BuffefModules
Table 2.' USER 65 Host Module Swit"hes
8. Set switches S1, and 52 on the RAM Module per Tables 3
and 410 ~nable/disable and, toseled'the address range of
;
the internal System 65 RAM:
FUNCTION
SWITCH
ADDRESS SELECT
S1/S2
Th~e
'NotE
switches determine whether address 'selection is
internal or e'xternal" for: each 4.K~ byte po'rtion:' of mem.-
If external RAM adddresses are ,selected on the USER 65
and the same adqresses are seJe~ted and enabled on the,
System 65 inte[nai ,RA"",' board{s), t~e internal RAM will
override ,and prev~i1t pr9per opera\ion of the external
RAM.
'
,
ory space. External memory is selecteq when ~he switch
is ON, internal "memory is selected w~en the switch is
OFF.
S1 Switch
Addr8S$R.nge
1
2
3
4
5
6
8
$0000. $OFFF
$1OO0·$1FFF
$2000· $2FFF
$3000 - $3FfF
'$4000 -$4FFF
$5000 - $5FFF
$6009 - $6FFF
$7000'- $7FFF
S2Switch
Add.... R.~g&
7
1
2
,3
4,
5
"
s.
Table 3.
6
7
8
_Def. .,_,i. .,ri ,":-~i. .,on_. .,. . .". .,,-'..,-,-,'-"---'-'
- -=----,.,
Switch S1/S2-4 Position
,
RA"'1 Ena"le(Disa!>I",St..,
Up
RAM ,Di~bll!d:.!Deselei:ted.
Down
RAM En$bled ISelected),
Table 4.
SWitch S3 S\li~s eithertt\.'·SySTEM, 65 ,clock (INn
o. an 'external, user-supplied clock (EXT>. if an exter~ai supplie(l cloc~ is used" the f~"q';"ncy, must be
1 or 2 MHt + 1% if operation, of the S¥STEM ,65
mini-floppy ,disks is required. It, must' al)lll~"'s ,be •
TTL level, sq'uare wave~ clocldhp~ti
'
-2
Up
Up
$0000 - $11'1" F
Down
Up
Up
, $20oo,:,;i3F'ff'
Up,
Down
'Up
Down
Down
Up
Up
Up
Down
$8000 - $9FFF
Down
Up
Down
$AOOO - $BFFF .
Up
i,'
Thi~' switch determines the baud rate for either the
RS-232C or TTY ports. Switch settings "re:
(S4) POSITION,
0
1
2
3
4
5
6
7
SAUD RATE
"
$4006 - $~F FF
"
siI~OO-'$7;FFF
Up
Down
'Cown
$COop.- $01"1"1"
J,to
150
300
Down
Down
Down
$EOOO - $fFFF
6QO
Note;, "Up" is toward the top edge of the mOdule
"
1200
2400
4800
9600
6-25
,
8K Address Range Selected
BAUD RATE:SELECT
, S4
,"
RAM Address Range Select'
SWitch Settings
'
-3
",
n
U
-
Switch S1/S2 ,Positi""
-1
CLock SELECT
S3
RAM Module Enable/Disable
r--_ _ _ _--,-___
SW_,_'it...,Chr-,
,$ll900 ~ $8F F F
$9000 - $9FFF
$AQOO.$AFFF
$BOOO"$BFFF
,$COOO - $CF FF
"$0000; $DFFF
$EOoo -$EF FF
' $FOOO- $FFFF
:'
I~~nthe top cover.
USER 65 Modules
US~~,,65 BU,FFE,R ,M()D~!:!
' ,'"
.':;:::'"
,
,,~:~~~
Since'\he'Buffer:Modu\e,isdesigned to suppOffallCPU's in the
R6500 family, spec~Cj~~~~~:or~r:the strapping requirements.,Jump$r 1Q98ti6ns.are;.l\o~l;l,inFig!Jre 1.
,
"
"",
"
>,,'"
..
;~':, ",Buffer
EqUi"",,"t. ' 'Module
"epu' ," 'Socket'
,
The Buffer Module halO t\\i0 rriCldes for th~,RlWr,\jio~.For 40-pin
CPU emulation (I'I65q2and R65t2), theF¥JwUne Is, cOnnected
,to the user's eqlliprAent aii is;' Since the 28~in CPU's do not
provide all the ~~!I'l$S lin~ to the user'si:!q!lipi'l'leht, address
conflicts canoccurduring"System 6t;; Monitor 'execution. A gated
R/W Ijne is,provided to prevent theSe conflicts;,fhis line is normally high, arid goes low only when an external.add{ess is pre.sent and R/W is low.
:,,:"
Table 5 . .!J~ER 65 ,Buffer "',~dule
Connection Requireme~s "
" 'dableTo
User E~uipri1ent
,
10','
R~~
.,' ,
,
!
;:\
J3
R
,M
N*
,p •
PSOO·D605.(1)t
i
' CPU
Pin
,'"
'
4
28
27
26
1
2
3
28
27
26
1
2
3
4
28
27
26
1
2
3
4
28
3
27
26
1
2
3
28
27
34
37
26
1
3
4
28
27
26
1
3
28
27
26
1
2
4
Fm
28
912 (IN)
27
Switch 53 on the
USER 65 Host Mb~ule must be positioned to the EXT position
when the exte'nded clock or frequency reference is used.
6-26
M65-001, -002, -003
USER 65 Modules
SPECIFICATIONS
TYPICAL APPLICATION
A typical application for the USER 65 module is illustrated. The
user's system may include any combination of ROM's, PROM's,
RAM's, I/O devices, and a 40- or 28-pin CPU socket. For
emulation purposes, the USER 65 module is installed in the
CPU socket instead of a CPU. The user must provide page
O($OOOO-$OOFF) and page 1($01 00-$01 FF) either internally or
externally for use by the System 65 Monitor. For system development purposes, the user's ROM may be emulated with one
or more RAM modules provided in the System 65 chasis. This
permits easy manipulation, debugging, and reassembly of the
user's program during the development phase. For editing and
assembling of the source program, the user may use the System
65 RAM or may provide his own RAM modules 'externally.
Parameter
USER'S SYSTEM
SYSTEM 65
USER 65
BUFFER MODULE
USER 65 Module Hook-up
6-27
'.
1.MHz or 2 MHz
0° to 70°C
'+.5 Vdc ± 5% @ LSA
Host Module Specifications
MOdule Dimensions.
Edge Contacts:
Edge Contact Signals:
9,75 in. wide x 7.50 in. high
86 pins on 0.156 in. centers
System 65 compatible
Buffer Module Specifications
Module Dimensions:
Cable Lengths:
To System 65
To User Equipment
The USER 65 module may be used w~h the System 65 Monitor
enabled or disabled. With System 65 Monitor enabled, the full
resources of the System 65 Monitor are available for program
checkout and debugging. In this mode the System 65 uses
addresses $COOO-$FFFF; these addresses cannot be used by
the programmer.
Value
Common Specifications
Operating Frequency.
Operating Temperature.
Power Requirements
4.125 in. wide x 7.375 in. high
60 in.
12 in.
M65-031_ M65~032
Microcomputer Development Systems
'1'
Rockwell
M65-031 AND M65-032 .
16K STATIC RAM MODULES
OVERVIEW
FUNCTIONAL DESCRIPTION
.The 16K Static RAM Mpdule contains 16K (16,384) bytes of
Random Access Memory (RAM), implemented wnh 32 R2114
1024 x 4 Static RAM devices and is available in either 1 MHz
(M65-03t) or 2 MHz (M65-032) version. Also included are
address decoding and 'selection, write protection and data buflering circuitry.'
The edge connec,tor pin assignments for the, RAM Module are
compatible with the Motherboard pin assignments given in Section 4 of the System 65 User's Manual (Document No. 29650
N35; Order No. 206).
The RAM Module's 16K !:lytes of read/write memory are provided by 32 R2114 1024 x 4-bit, Static RAM devices.
The module's 16K bytes of RAM memory are segmented itlto
two independent 8K-byte sections. Each 8K section is controlled
by' an enable/disable swnch and three address range select
switches, located at the top 01 the Module. Each 8K section Can
be independently write-'Protected ~ia special lines.
Address Buffers Z47, Z46 and Z33' and Data Buffers Z32 and
Z45 present a single TTL load to the Motherboard edge COnnector. The data signals are inverted to make them compatible
with the system 65 Data Bus (00-07).'
,
The StatiC RAM, Module is directly compatible with the Rockwell
System 65 Microcomputer Development, System, and can be
used to increase the system's read/write memory capacity from
16K bytes to 48K bytes, wnhout hardviare modifiCation. The
module'may also be installed ,in user-designed equipment, via
the Auxiliary Card Cage.
Module switches Sl and S2 provide independent8K RAM section enable/disable and address selection. Sl-4 and 82-4 permit
each ElK section 01, RAM to be enabled or disabled. Sl-1, -2
and -3 and ,82-1 , -2, and -3 select the base, address to which
the. respective 8K sections will respond. these-switch settings
are compared to upper address bits A13, A14 and Al5 in,
Address Comparator devices Z10 and Z21, The Comparator
outputs enable or disable 1-01-8 Decoder devices Z9 and Z20
to provide the input chip select signals to the two 8K RAM
sections.
FEATURES
• System 65 compatible
• Available in 1 MHz (450 ns access) and 2 MHz (250 ns
access) verSions
• 16K bytes 01 Random Access Memory, with two independent
.
8K sections
•
•
•
•
Write protection is controlled, by seven Write Protect lines, WP1WP7, one line for each 8K section 01 memory (the lowest section, addresses $0000-$1 FFF, may not be write protected; note
that Z48-2 is tied to ground to permanently enable writing to this
section). A low voltage on WP1-WP7 enables writing into the
associated 8K section.
Separate write protect capability lor each 8K section
Static-no clocks or strobes required
9.75 in x 6.00 in . .module
Single +5V supply
When the Address Comparator enables the RAM Device Select
Decoders, Address Select switches S1-1 through Sl-3 and
82-1 through S2-3 are used by Z35 and Z36 to select one 01 .
the seven Write Protect lines. The selected line controls the
RAM Write Control signals, Z34-6 and Z34-8.
DocumentNo.~ON46
6-28
Product Description Order No. 214
Rev; 1, August 1983
M65-03,1 and. M65-032
16K'Static RAM. Modules
,.,
ADDRESS $ELECT
AND ENABLE/DISABLE
SWITCHES
,8K RAM
-?
r=::>
S1/S2
~----8K RAM
,
V
WP1-WP7
~=:J
---
1(;,
CHIP
SELECT
LOGIC
~
I.
V
R/W/02
I.
DATA
BUFFER
CONTROL
BUFFER
,
V
DO-D7
.~
R/W
ADDRESS
BUFFER
"
AO-A15
.
02
SYSTEM 65 BUS LINES
II
RAM Module Functional Block Diagram
INSTALLATION
Use the following procedure to install 16K Static RAM Modules
in the System 65 or, wfth appropriate changes, in an Auxiliary
Card Cage.
the System 65 Monitor Board, and must not be enabled
in RAM Modules.
4. Insert the RAM Module(s) into any vacant sIOI(S) in the
System 65 chassis.
5. Install System 65 top cover.
6. Tum system 65 power on.
1. Tum System 65 power off.
CAlTTlON
Never install or remove modules wfth System 65 power
on-It may cause damage to the module and/or to the
System.
Table 1. RAM Enable/Disable Switch Settings
Switch Sl/52-4 Position
2. Remove the top cover of the System 65.
3. The RAM Module has two banks of swftches-S1 and 52one bank for each 8K section of RAM. Using Tables 1 and
2, select the enable/disable and address range characteristics for each 8K section.
Up (Off)
Down (On)
NOTES
For proper System 65 operation ...
a. Page 0 (address range $OOOO-$OOFF) and Page 1($0100$01 FF) must be provided in RAM-either internal RAM
or external RAM as interfaced by USER 65 or its
equivalent.
b.RAM addresses in the range $COOO-$FFFF are used by
6-29
RAM Emible/Dlsable State
RAM Disabled (Deselected)
RAM Enabled, (Selected)
16K'Static RAM. Modules
M6501o031 andM6So032
"
Table 2.
RAM Address Range Select Switch Settings
SWl;ch Sl/S~ Pp~lon
-1
Up
Down
Up,
Down
Up
Down
Up
DoWn
;-2
-3
Up
Up
Up
Up
DoWn
Down
Down
Down
Up,
Up
DOwn
DO\yn
Up
Llp
Down
Down
SPEC.IFICATIONS
8K Address
Range s.kIcted
Memory Si:ze:
Word Length:
Interflce:
Max. Access Time:
$OooO-$IFFF
$2000-$3FFF
$400()~$5FFF
Module Components:' .
$6000-$7FFF
$8000-$9FFF
$AOOO-$BFFF
$CQOO-$DFFF
$Eo()O-$FFFF
Module Dimensions:
Edge Connector:
Operating Temperature: '
Power Requirements:
16K bytes
8 bits
,
System 65 compatible
450 ns (PIN Ma5-031)
250 ns (PIN M65-032)
32 R2114 Static 1024 x 4-bit RAM
devices
9.75 Ih. wide x 6.00 in. high
86 pins on 0.156-in. centers
OOC to +70'C
+5 Vdc ±5"1o @ 3.0 limps ,(typical)
Note: "Up", Is toward the top ,edge ,of the Module.
LOGICLEVELS
T i. ='O°C to + 70°C, Vee = +5V ±5%
Characteristic
Inputs (DO-D7), AO"AI5, WP1:\NP7, 13'2,
Input Low, \bRags
"
InPut Higl1'Wllage
,~.
OutPYtS (DO-57).
Outpt!! Low, \bRage
Output H;gti \bltage
SymbOl
Min
Max
Unit
CondHlon
V ,L
V ,H
0.8
Vee
V
2.0
Y
I,L = 400 !La
I'H =40~a
2.4
0.5
Vee
V
V
IOL= 4sma
IOH = 10ma
RfW'
VOL
VOH
"
6-30
MG5-Q~P
Microcomputer Development Systems
'1'
Rockwell
M65-040
PROM PROGRAMMER MODULE
OVERVIEW
The PROM Programmer Module consists of two R6520 Peripheral Interface Adapters (PIAs), data buffers, address decoders,
26V power supply, level shifters and power-up circuitry.
The M65-Q40 PROM Programmer ModUle provides System 65
users with a means to program, verify, read and check Programmable Read Only Memory (PROM) d,evices, and supports
2704,2708,2716,2516,2532, and 2758 devices. The PROM
Programmer Module connects directly to the PROM Socket on
the front panel of the System 65.chassis, via supplied cable.
The power-up circuitry (Z9) generates an automatic reset during
power-up. A reset signal may also.come from the Reset line of
the System 65 Bus.
.
'The PROM Programmer Module contains data bus buffers, Z12
and Z13, to provide a logical inversion and a single TTL load to
the System 65 bus signals", The two R6520 PIAs, Z5 and Z8,
are used to store the address, data and control information for
the PROM device, The address, Read/Write (RlW), and 132 signals"are buffered and decoded by Zl 0, Zll, Z14, Z15 and Z16,
PIA No, 1 is addressed at locations $C018-$COl B, PIA No.2
is addressed at locations $COl C-$.COl F,
The Module is supplied with a mini-floppy diskette which holds
a set of software routines that allow the user to check a PROM
for Rroper initialization, program the PROM from System 65
memory, verify the PROM with System 65 memory, and read
the contents of the PROM into memory. Utility functions to load,
verify and dump memory are also supplied.
FEATURES
The PROM device receives address linesAO-A9 and data lines
DO-D7 directly from the PIA devices. The program lines (see
Table 1, PROM socket pin nos, 18, 19 and 20) are level-shifted
to provide either OV, +5V, +12V, +25Vor +26V to the PROM
cjevice, Qepenping on,the device type, The 26-volt power is generated.lom the +5-volt power through a DC-DC converter, Z6,
and an adjustable volta9E1r regulator, Zl. Relays XRl through
XR4 are used to, switch the power lines· (see Table 1, PROM
socket pin nos, 21 and 23) to +5V, +12V an(j -5V to the PROM
device, depending on the device type. The -5V power is generated from the -12V power line through a voltage regulator,
Q9.
• System 65 development system compatible
• Supports programming of 2704, 2708, 2516, 2532, 2716
(Intel and Texas Instruments) and 2758 PROM devices.
• Comes with software on mini-fl.~Ppy diskette
FUNCTIONAL DESCRIPTION
The edge' connector pin assignments for the PROM Programmer Module are identical to the Motherboard pin assignments given in Section 4 of the System 65 User's Mallual
(Document No. 29650N35).
Table 1 summarizes the PROM Socket interface, and applies
to both the PROM socket located on. the PROM Programmer
Module and the PROM socket located on the System 65 front
panel.
"
Table 1.
PROM
, Sock.t
Pin
Number
20
vee
16
17
18
,.
2.
21
22
Document No. 2965ON42
6-31
0704
23
16
M65-040 PROM PrOgramming .Module
PROM O..,ice Type!
A7
A6
AS
A'
A3
A2
Al
AO
DO
01
D2
GND
03
04
OS
DS
D7
'GM
VOO
Cs/wE
VBB
GNO
A8
10
1.1
12
13
10
System 65 PROM Socket Interface Summllry
In'"
2708
A7
A6
..5
A4
A3
A2
Al
Ad
00
01
02
GNO
03
DO
OS
06
07
PGM
VOO
CSJWE
V88
AS
A8
vee
Intlll
2758
A7
A6
A6
A'
A3
A2
Al
AO
00
Dl
D2
GNO
D3
04
DS
OS
07
In",
2710
GND
A7
A6
AS
..4
A3
.,2
Al
AO
DO
Dl
D2
GND
03
D4
OS
D6
D7
CE/PGM
Al.
OE
OE
A.
A8
VPP
A9
A8
, vGC
vee
Ce/PGM
vpp
t.l.
2716
A7
A6
A5
A'
A3
A2
Al
AO
01
Q2
03
VSS
0'
QS
06
07
as
CS/PGM
VDD
Al0
VB8
A.
A8
VCCI.~EI
TJ.
2516
T.'.
2S:I2
C:onnector
J1
Pin
.
Numbet
,
.,7
A6
A5
A4
A3
A2
Al
AO
01
02
03
VSS
00
OS
06
07
Q8
A7
A6
A6
A4
A3
.A2
Al
AO
Ql
02
17
lS
23
2.
26
2'
22
20
OJ
18
Cs
PD/PGM
'VPP
VPP
A9
A8
VC'~
VSS
Q'
OS
06
Q7
08
PO/PGM All
AlO
Al0
A9
As
vee
21
,.
10
8.
8
2
13
11
9
Product Descripfion Order No. 213
Rev. 3, August 1983
6
.
if'
i~" ~~
-.. 0)
(ft'.
I-
i/
0·,
>
--~-
"-,'
~
"tI
~
s:
."g
,
c8...
3
3
....
Notli:AII examples were prepared·
-using SYSTEM.'65 Operating
.:.System Version 3
CD
.. :;.~
.
s:
o
Q.
C
PROM'Programmer Func.ional BlockOiiigram
CD
.PROM Programmer
M65-040
Mod~le
CAUTION
MODULE INSTALLATION
Incorrect PROM installatio~ may cause. PROM damage
and/or may blow Fuses F1 and F2 on the PROM F'ro~
.grammer Module.
Install the PROM Programmer Module as follows:
1. T~rn System 65 off.
CAUTION
3. Insert the PROM into the socket, then push up and in on the
socket lever to apply pressure to the pins.
Never install or remove modules with System 65 power
on-it may cause damage to the module and/or tottle
System.
To remove the PROM devic~, grasp the PROM device at each
~nd, then push the socket lever away from. the System 65 .front
panel to release pin pressure.
.
2. Remove. the top cover of the System 65.
3. Insert the PROM Programmer Module into any vacant slot
in the System 65 chassis.
4. Connect one end of the supplied cable to the connector on
top of the PROM Programmer Module and the other end to
the connector mounted on the inside front panel of System
65. Observe the correct polarity of the plugs and sockets;
i.e., align the arrows marked on the plugs and sockets.
5. Install the top cover of the System 65.
6. Set the System 65 RUN/STEP Switch to RUN.
PROM INSERTION/REMOVAL ON PROM
PROGRAMMER MODULE
To insert the PROM device, position the PROM device in front
of the socket, being careful to observe the Pin 1 location.
CAUTION
Incorrect PROM installation may cause PROM damage
. and/or may' blow Fuses F1 and F2 on the PROM Programmer Module.
NOTE
With the PROM· properly oriented, gently start all pins evenly
into the socket pin guides. Then press firmly and evenly on the
device (avoiding contact with the light window) until the device
is .securely seated.
The. PROM programmer will not operate properly if the
RUN/STEP Switch is in the STEP position.
7. Turn System '65 power on.
B. The PROM Programmer Module has an .automatic reset feature. The standard power-up message should appear on the
system terminal device' at power-on. A manually-initialed
re~t may. however, be perfOrmed whenever'required.
To remove the PROM device, exert an even, upward force on
both.. ~ides of the device While. co.unteracting with a les.ser, evenly
applied do.wnward force: This will pr~vent the PROM device
from poPping out one Side and .bendlllg or breaking pins still
engaged at the pther erid of the socket.
PROM DEVICE.INSERTIQN/REMOVAL
OPERATION
.CAlJTIOr..
The PROM Programmersoftware allows checking, reading, ver~
ifyingand programming 27Q4, a70E!, 275B. 2516, 2532 or 2716
type devices. The data/instructiOn.s a~ copied to/from the System
65 RAM .memory in the address range specified by the user.
The user can then transfer this . information to/from the diskette
(or otl]er VO device} using System 65 software routines.
The Prom device is frajJile" and. dropping, twisting or
uneven pressure may break". Never'press down.on the
wii'ictow. area of the chip.: '.
.
The PROM device may be fnsertedintoSystem 65 frant panel
socket or into the socket located on the PROM Programmer
Modu~.•
LOADING THE PROM PROGRAMMER ROUTINES
CAUTION
There is one PROM prograll)mer object file supplied on the
PROM Programmer diskette, PROM'n, where "n" is the program r,elease revision letti:lr. File PROM*n occupies from $0200
to $OFFF. User programs can be loaded starting at!~1000. To
load the PROM~n program, use·.the System 65l.Qad Command
L. Then enter the file nOFFSET"'000e IN=F
DONE
FILE"'PROM"'F
DISK"':!.
<5>
PROM PROGRAMMER FOR 1 MHZ S....STEM 11 ......... ''' ... ''',
ENTER PROM COMMAND. VERIF..., ,
PROl'l,~
ENTER: 21'841 2788. .Q:7M.
-27:16
vu.,.2SU. 2S32 .
.
TMS 271.6,
-N,
PROf't?
~:"''''''''~!:t';
...
271:6'
!
'.
.......
,::~:E~ ==~ =~~~~.~~;r=:'~~~~o;l=~i~'(l)
':
,'':'
-.,...~~
-v
:
'\
.
".' '~',
VERIFV
, 'ERRoR LIST,:"
,..;:,'
;<:'15>
~
~ ~~,,~~,:I.''!f,s~~''~Y~~
~TEJit "~~ :z'1aa. ~.,a7s,6,,~~, 2Sl~,>
;~7if ~
I
I,)
11
,";1 :,
-N
:
I,
OUT~
" ::,
,~~=~I~T~
E>,.
"=-....
1.'"
ENTER LAST ADDRE;SS
-'l7FF
I
,I.
.
'i
=CE"TYPE-~~
" ,:-,.!!~.....;..:~..tt~t,,:i;!:
'1481
i7FF.
ce
ca
ce'
I
RAtt"i",;
4t
1.S
DONE
.r
ENTER'PIP" ~~, YaIUFV(Y).~(P),REfII)(~n,OR ct£CK(C~
~ ~li':YE~IFV(F).~OfIt)(L~.OU~,~,O).f'IEP:I F~LL.
ERROR LIST
~:'R'II\$T .~.,
'I
P~RAI1(,'p). READ(~).'OR ~CK(cf "
,., ',
:,1
~,.:~.,~: ~~~y~F:).'!~~.(L).-·I~(~),~',!f~ Fl~~")~:IN~(I,(j,
Verify FUnCtiol:l~ample.with':ErTors,
5·u.sl'~i"
~ NOT INiTlf\l.lllEl>
CllNTI_y pressing theR'kEiVdnre$jilonse toJhe
ENTER con:!.mand m~ssage:
'
,;'"
~.
~IFY[NG
DON£
...............................................
DEVICE TYPE.
27...
';,;1".', '
,~i,:-"'.....~....'....~,:~',·::,
,:..
\," "" ':"
"" ':
,
,ENTER ,PROtt .~'~ YER;lEV(Y).PROQ"(P).R;Ef.MR)~OR CHE~(C).
.
~ ~ ~,; ~,IFY(F),. LORD(~.). ~(D)~'1'IEt'I ~~LL
"PrOgram. ~unctiori Example
" ,
~" .F
: After the first andl~ add~s~es are. entered,pOwer will,Poe
applied to 1~ PROM lind the'~tentscopie!l in~;~l1e specifi~ ..
. RAM k>cations. whiitpcompi&ied, the messkg.e DONE will be!
, printed and the next operation requested. '
"
" ,
,,'I
PROM Programmer Module
M65-040
LOAD MEMORY WITH OFFSET FUNCTION
(THE L COMMAND)
The PROM Programmer READ function reads progrs,m data
into€)ystem 65 RAM memory from PROM. After reading is complete, save, the PROM data on diskette (or other media) using
the System 65 Monilor D Command after exiting the PROM
Prografllmer functions, Alternatively, use the PROM Programmer D command to dump the' data with optional offset
before.lhe PROM Programmer functipns are exited. The amount
tope stor~d or loaded at one time is limited only by the RAM
locations available.
~~
The Load Memory wilh Offset Function (L),copies dJtafrom an
input object code file into memory addresses offset by an
entered amount from the addresses on the input file. The entered
offset value is additive with carry from bit 15 ignored, e.g.:
PROGRAMMER FOR 1 MHZ SYsTEM (VE'R E)
ENTER 2784.2798, 2:7!5E'$, 2716._2~1.6, 253:0::
-271.6
'ms
2716 PROM?
-N
Input File
Address
Offset
Value
Address in
Memory
$1QOO
$1000
$7000
$EOOO
0
$2000
$AOOO
$2000
$1000
$:3000
$1000
. $1000
...........................................................
DEVICE TYPEK:
271.6
PfI!OM ,PROGRAMMER fOR 1 MHZ SYSTEM (VER: E)
E'JTE~
ENTER 2704,2708,2758,271.6 •. 251.6,253:2
=2716
'-'
<~)
PROM COMMND: VERIFY';:V), PROI3R:FlM'(P). REFlD(R), OR CHECK(C)
OR: ~\"QRY COf'II'IflND: If'ERIFY(F), LOFlO(1.)i D~MP~,LOf'D(L)~ DUMPC:'I». MEM FILL.(M')~'lNYERT',P.
.....:................................................
cL
LOFID'
OF~SET~Draee
'
DE..,.lCE TIt'PE-
2716
."'........................ .....................
,
,
~
ENTE';r"p~OM COMMAND: ..vtRIFY" PR'OGRAM< p,)" READ:
OR I'tEI1ORY COMMAND: YERIFY(F), LOAD(U'DUMP(D)' MEM FILUM), INVERT< 1>
Re8d
:;
IN-F
;-'.
Fl,Lt;"'AIMBAS
DISK:2 r
.........!f' ............"'lI'............... "'...............
OEVI£E TYPE-
... "' ..................."'......... "'... ,.............. ...,
271.6
Function'Example
, , '
ENTER PiO!OM COMMAND: VERIF"I"(;",'), PRO'GRAM(P), REI!KHR)'; OR, CfiECK(C)
, o'R- MEMQRY, COMMflND: VERIFY(F), LOF\t)(U~ PUMP(D),;~M' FILL(m~'~INI,!ERT( I )
CHECK FUNCTION (THE C COMMAND)
Load lIiIemory with Offset Function Example
The Check Function (C) is used to check that. the PROM is
initialized. It is entered by preSSing the C key in response to the
ENTER command message.
VERIFY MEMORY WITH OFFSET FUNCTION
(THE F COMMAND)
The Verify Memory with Offsel Function (F) compares the contents of an object code file with the contents of memory at
addresses in memory offset by an entered amount from the
addresses on the reference obje~tcodefile;The, entered offset
is additive iii ttie same manner as the Load with Offset function·
The contents of both memory (ME:M) and reference file (FILE)
i3.re displayed/printed along with the address (ADDR) if any differences ,in value are detected.
After the first and last addresses are entered, power is applied
, to the device and all specified locations are checked for $FF.
Themessage PROM NOT INITIALIZED will be printed if all
locations do, not contain $FF. The message DONE will be printed
when the Check Function is complete.
<5>
PROM PROGRAMMER FOR 1. MHZ SYSTEM (VER E)
ENTER 2704, 2708. 2758. 271.6. 251.6. 25:12
""27115
TM5 2716 PROM?
=N
<5>
PROM PROGRAMMER FOR 1. MHZ S'r'STEM
t<>t< ...,,,,,,,,,*... ,,,,,,,,,,,,,,,,,,
DEVICE T'TPE'"
-N
271.6
...................."'''',.. .........'''..................
... ...lttltt.Itt.................. "'****** ... ...
ENTER' PROM COMMAND: VERIF:"I"(\I), PROGRRM(P)/READIt ........................ ,.; ... ,;..."' .."' ......... . , ;
DE ..... ICE T'r'PE=
2716
DEVICE TYPE=
2716
**...................,.."'........................*"'*
**"'*......... Itt.......Itt*... Itt ... "'Itt.,"...
E~TER
PROM COMMAND: VERIFY, PROGRAM (P), REFlD,L.OAD(L.),'I)lJMP(O).MEM FILL(M) • .JNYERT
Output File
Address (FROM =)
Offset
'Value
Address in
Memory
$1000
$4000
$1000
$AOOO
0
$0000
$8000
$1000
$1000
$1000
$9000
$6000
-"
MEI1 FILL-sa
FROtt-:LiMe
TO-llFF
...........................................
DEVJCE TYPE.
'2~1'1,
.................*..................
",
Memory Fill Ft,lnctlon t:xample
PROf1 P~GR~R FOR 1. MHZ SYSTE~. ._ ~OQRFltUP). REfID(R), OR OECI«C)
OR I'tEMORY COMI1AN'>: VERIFY,(F),. LGfIIIE>(L.), DUI1P(O), I1EI'I FILL.(M~.lNYERT(l)
-0
DUI1P
OFFSEr-oeee OUT-F
FRO"'-4IJBe TO-47FF
F1LE"!,,PRMOUT
Enter the bit pattern to be exclusively or'ed with memory, A "1"
in a bit pOSition williriliert the bit value while a "0" will leave the
bit value unchanged. Enter."FF" to invert all bit values and "00"
to invert noI1eof the bit values. Terminate the entry Yiith' a carriage retu" rn. The last two digits entered will be accepted. Ente.ro'"
'
the starting and ending addresses as'described for the MEM
FILL funetion.
.
' .
DI5f(-2
...............................
J1ORE?N
DEYl CE TYPE2716
ENTER' PROM CDl'U1AND:
OR I1EI1ORY CCII1t1AND:
i
YERIFY(Y)~ PROGRFII'I(P), READeR), OR CHECI(:(C)
''YERlf''(F)~ LOAI>~~)~"OOrIP~,I).1£M FILLCPt>. INVERT(])
:
Dump Ml.nory ~,ith Offset Functic:'~ ~xample
(~>
'
.
'
'
PROM PROGRAMMER FOR i" MH2: SYSTEM (YER E)
ENTER 2784. 2718. 21''S8. 212.S. 2'51.6. 233:2
MEMORY FIl.L FUN(rrION (THE M COMMAND)
-2716
TK5 2716 PROI"P.
'8M
the Memory Fill,,'Function (M)allows a user ~Iected. range of
RAM to be initialiZed, to an entered bit pattern. TI:Ie ,desired
PROM object code Cantlien be loaded. All unloaded memory
in the PROM address range Yiill remain ',initialized with the previously filled Pit pattern~ This allows PROM codes over Ii total
PROM address range to be easily verifific:l without in~alid data
r;!rrors being indicated due to random bit patterns in unused
addresses.
.
.',
I
'
.
......*:***-..................... ...
~
r
DE.VIC~
'fYPE-
2116
g=
............................................"r~.
~.~~ERME=·
.~
"
~ =~~~~~~: =~~~;.~~~:~M~l~~~~~i~y&;RT( I)
'
INVERt 81:TSooFF
To-13FF
FttQM-:Leee
...........................................
DEYlCE"'TYPE~716
..........................................."''''.
Enter the bit pattern,to be loaded in hexadecimal in response
to the MEM FILL= prompt. The last two digits entered will be
ac;cepted. Ter"linatethe entry with a carriage return. ThEin enter,
the starting and ending addresses in hexadecimal of the RAM.
to be filled. Terminate entries with a carrillge retum. The .last
four digits entered will be accepted.
ENTER PROl'I c~; YERIFY(Y). PR.OGRAM(P). READ~R). OR CHECK(C) ",'
, DR
~~ CQfIII'IAHI);
YERIFY(F~~LOAl> :developmenl
of custom circuits for installation in either Rockwell's System 65
Microco,mputer Development System or in user-designed eqUipment, via the Auxiliary Card Cage.
Thepil')assignments.for the Design Pr9tOtyping Module's 86pin edge connecior are Id8J1tical to the Motherboard pin allsignments given in Section 4 of the System 65. User's Manual. (Doc'
.
ument No. 2965dN35; Order No. 206).
This Module is a System 6p,compatible printed circuit module
w~h no mounted components, but w~h pre routed power bus and
power return lines. Spaced beside the power lines are platedthrough holes thatfpermit wire-wrap sockets to be installed.
Additional holes, at the top edge of the module, permit a variety
of wire-wrap flat ribbon cable connectors to be installed.
M65-071 Design Prototyping Module
Product Description Order No. 215
Docu.menfil4o.29650N45
6-44
Rev_ 2, August 1983
M65-071
Design Prototyping Module
INSTALLATION
SPECIFICATIONS
Install a Design Prototyping Module in the System 65 or, with
appropriate changes, in an Auxiliary Card Cage as follows:
Value
Parameter
Component Mounting Area
Number of Component Rows
Number of Hole Rows
Vertical Hole Spacing
Horizontal Hole Spacing
1. Turn System 65 power off.
CAUTION
Never install or remove modules with System 65 power
on-it may cause damage to the module and/or to the
System.
Flat Ribbon Connector Mounting
Area
Number of Pins
Per Connector
2. Remove the top cover of the System 65.
3. Insert the Design Prototyping Module into any vacant slot in
the System 65 chassis.
CAUTION
Installation of improperly-operating circuits may cause
malfunction and/or damage to the System 65.
4. Install the top cover of the System 65.
5. Turn System 65 power on.
6-45
14
35
46 holes' on 0.1-in. centers
35 holes on either 0.3-in.
or O.Hn. centers
170
Module Dimensions
7.50 in. high x 9.75 in. wide
x 0.062 in. thick
Edge Connector
86 pins on 0.156-in. centers
M65-660
Microcomputer Development Systems
'1'
Rockwell
M65-660
SYSTEM 65 MACRO ASSEMBLER
& LINKING LOADER
DESCRIPTION
MACROA~SEMBLER
The System 65 Macro Assembler and Linking loader is a diskbased computer program that generates computer program
absolute machine code or relocatable object code and links
relocatable object code into absolute machine code. The
assembler/loader operates on the System 65 Development
System and generates code for execution by any central processing unit (CPU) in the Rockwell R6500 NMOS microprocessor, R6500/* NMOS one-chip microcomputer and R65COO
CMOS microprocessor device families.
• Supports three CPU families
-R6500 NMOS microprocessor
-R6500/* NMOS microcomputer
-R65COO CMOS microprocessor
• Flexible object code generation
-Absolute code (executable)
-Relocatable code (linkable)
MACRO ASSEMBLER
The macro assembler translates CPU instructions and data
statements written in symbolic form (the source program), into'
absolute or relocatable code. Instructions, consisting of a label
(if included), a mnemonic operation code, an operand (if required)
and an arithmetic operator (if included), are assembled one-ata-time into one- to three-byte machine instructions (with absolute or relocatable address information). Constants comprising
one or more bytes of memory are generated from data statements while one or more bytes of memory are assigned to variables. The macro capability allows sequences of instructions to
be pre-defined for in-line code inclusion by specifying only the
macro name. Conditional assembly allows portions of instruction sequences or macros to be included in (or excluded from)
in-line code. The combination of the macro and conditional
assembly capability speeds program development by eliminating duplicate coding efforts for similar processing tasks and
increases program flexibility and reliability by allowing one source
program to generate different computer programs based on
specified control parameters.
LINKING LOADER
The linking loader combines independently assembled modules
of absolute and/or relocatable object code into a single executable object file. This allows a large program to be developed in
manageable size modules by separate software designers and
integrated by the linking process. This also allows program
changes to be made to one module without affecting any of the
other modules-a key requirement in many program validation
and certification procedures.
FEATURES
• Macro definition includes
-Multiple parameters
-Other macros
-CPU instructions
-Assembler directives
• Macro call includes
-Macro name
-Argument list
• Condition assembly
-IF condition
-ELSE complementary condition
-12 conditional operators
• Symbol cross reference table
-Lists defined and used symbols
-Listed.in alphanumeric order
LINKING LOADER FEATURES
•
•
•
•
Resolves inter-module symbol linkage
ASSigns absolute addresses
Generates absolute executable code
Produces reports
-Load map of module locations
-Symbolic debug table
-Symbol table
• Interactive or command file setup
ORDERING INFORMATION
Part No.
M6S-660-3
Order No.
Small programs can still be assembled into absolute executable
code without using the linking loader, however, to simplify
development.
249
Description
Macro Assembler and Linking Loader'"
Description
Macro Assembler and Linking Loader User's
Manual'2l
Notes:
1. Requires System 65 OS 3.1 ROMs
2. Included with M6S-660-3.
The assemblerlloader operates in conjunction with the ROMresident System 65 Debug Monitor/Text Editor (OS 3.1).
Document No. 29650N64
6-46
Data Sheet Order. No. 253
Rev. 1, March 1983
Macro Assembler & Linking Loader
M&5-66D-3
Assembler Directives
Asae",bIy LiSting Control
.TTL
option Control
Title
.OPT
.SBTTLSubt~Ie
;PAGPage
.SKI
Skip
.ERR
Error
Source File Control
.END
End of Assembly
.FILE
Next File
.INCl
Include
Data Storage
.BYTE
.WORD
.DBYTE
.sBYTE
.
In~iali~e byte memory location
Generate 16-bit address
Genarate 16-bit data word
Initiali~e ASCII string
Equate
Assign value to symbol
.RAD
Conditional
.IF
.ELSE
.EIF
Cond~ion
Complementary condition
End of conditional
Macro
.MACRO.
:ENDM
.MEXIT
.NARG
Define Macro
End of macro defin~ion
End of macro expansion
Number of passed arguments
Option
L1ST/NOLIST
GENINOGEN
ERRINOERR
SYM/NOSYM
CREF/NOCREF
Assembly listing
Object code listing
Errof!l!lneration.· ,
Symbol generation
Cross reference generation
ABS
Absolute object code
REL
Relocatable object code
MEM
Absolute object code to
memory
Table of contents
TOCINOTOC
OBJ/NOOBJ
Object code generation
MDINOMD
Macro definition
ME/NOME
Macro expansion
CCiNOCC
Conditional list
PLEN·
Page length
LLEN
Una length
FF/NOFF
Form feed
CLS'
Clear definitions
.Radix 2, 8, 10, or. 16
Relocation/Linking
.DEF
Intemal definition
.REF
Extemal reference
.ZRE F
Zero page reference
.PSECT
Program section
.IDE NT
Module identification
Linking Loader Directives
ERR
OBJ
MAP
CALS'
Svt,1,
DEBUG
Errors dllalination
Object code genaration
Load map genara1\On
Symbol table locatiOn
G.iobalsymbol table
. Debug symbol table
ORG
ORDER
DEF
LOAD
END'
6-47
()rigin
Section order
Symbol defin~ion··
.Load code specification
Command file end '
SPS·200
Microcomputer Development Systems
'1'
Rockwell
SPS·200
SOFTWARE PREPARATION SYSTEM (SPS)
PERIPHERAL CONNECTOR MODULE
INTRODUCTION
VIA (Z22). The parallel interface connector is compatible with
many of the RM 65 modules, e,g., single' B()ard Computer
(SaC) and Multi-function Peripheral Interface (MPI), and with the
AIM 65/40 ""icrocomputer connector, e.g., User Parallel 1/0,
Display Interface and Printer Interface.
The optional SPS Peripheral Connector Module (PCM) (Part
No. SPS-200), which conneClts directly to the AIM 65 Microcomputer Master Module,connector, provides the Software Preparation System (SPS) with a complete set of external 110 interfaces.
These 110 interfaces support external printers, serial devices,
audio cassette 20 mA current loop and parallel 110 devices such
as the RM 65 board family.
FEATURES
• 34-pin connector for Centronics compatible printer support
• RS-232 connector for serial. interface support
The external printer interface routes and buffers (TTL levels) the
printer signals to a Centronics compatible 34-pin c~nnector for
printer support.
• Molex connectOr for 20 mA eurrent loop support
• 3.5 mm mini-phone jack connectors for audio cassette
support
The RS·232 interface operates at the ± 5V level. No handshak:
ing signals are provided, but .selectable handshake signals have
been wired for static levels. Feed throughs are provided to cut
and jumper these signals. Data Set/Data Terminal operation is
l!elected using a jumper pair.
• 2,5 mm sub-min i-phone jack connectors for remote tape
control
• 40-pin parallel 1/0 connector, compatible with .the RM 65
module family
,
.. The 20mA current loop interface routes four 20mA current loop
signals from the AIM 65 Master Module connector (J1) to a
dedicated Molex connector to provide current loop 1/0 support.
REFERENCE DOCUMENTS
The following documents contain information regarding set-up
and operation of SPS-200.
'
,
The audio cassette recorder interface signals are routed to two
mini-phone (3.5 mm), jacks for audio cassette support. The
remote control lines are controled by reed relays and routed to
.
two sub-min i-phone (2.5 mm) jacks.
The parallel 110 connector interface supports the 40·pin signals
routed to the interface by the AIM 65 Master Module User
Order No.
Title
2167
R6500Software Preparation System (SPS)
User's Manual
AIM 65 MicrocOmputer User's Guide
209
SPS-200 Peripheral Connector Module
Document No. 29001034
6·48
Data Sheet Order No. 0134
February 1984
Peripheral Connecto.rModule
SPS·200
EXTERNAL PAINTER INTERFACE'
RS-2321.NTERFACE. .
SPS ",odule Printer COnnector
Signal
Pin
1
2
3
4
5
8
7
8
9
10
11
12
~
Ground
Data 1
Ground
Data 2
Ground
Data 3
Ground
Data 4
Ground
Data 5
Ground'
13
14
15
16
17
18
19
20
21
22
23 to 34
'.,
RS<232 COnnector Pin Assignments
Signal
Pin
Input/Output
Signal
Pin Mnemonl.c
Data 6
Ground
Daia 7
Ground
Data 8
Ground
1
2
3
5
GNO
Tl)
M
CTS
DSR
GND
OCO
.,6
m<
Ground
Not Used
Ground
Not Used
8
9-25
" Signal Naltle
Data Set
Date. Term
Chassis Ground
Transmit Daia
I
0
Receive Data
0
I
Clear 10 Send'.
+5V Always +5V Always
Data Set Ready'
+5VAlways +5VAlways
Signal Ground
Data Carrier Detected' +5V Always .+5VAlways
Not Used
'This can be cut for a No Connect option
@~................................
............... ~
25
14.
. /
r-G:======~:\"":"l
33
'
Interface Module Connector
.........
......
... ..
'
,
CABLE
CONNECTOR
(AMP) 206771-1
(OR EQUIVALENT)
REAR .PANEL
CONNECTOR
(3M) 3483-tOOj)
13
TOP VIEW
PINS 18& 38 ARE NOT CONNECTED
FiS.2.32 Cormeetor Pin Locations
,MATES TO
EXTERNAL
PRINTER
PIN 1
34 WIRE
SOCKET RIBBON, CABLE
RECEPTACLE
3M "0. 3414.6000
OR EQUIVALENT
eFEET
I-
36
CENTRONics
TYPE PLUG
3M NO. 33$&,1001
OR EQUIVALENT
./.
20 rnA CURRENT LOOP INTERFACE
20 mA Current Loop Conneetol' Pin ASsignments
Printer Interface Cable (User Supplied)
Pin
1
2
3
4
Centronlce Type COnnector Pin Assignment·
Pin
,Slgmil
.Pln
J-1
J-2
J-3
J-4
J-5
J-6
J-7
~
J-8
J-9
J-1.0
J-l1 to -17
.J-19to -29
J-30 to-35
J-1S and,J-36.
Data 1
. Data 2
Data 3
. Data 4
Data 5
DalliS
'PRINTER
....... ","," ......
',
36
'Sigrial
Data 7·
DataS
Signal. Mnemonic
TrY KYBD
. TrY !wer supply is sufficient.
NMOS Interface (Input Voltage
Svmbol
= +S.OV. TA = 25°C)
Min
Parameter
.
Max
Unit
V IH
Input High Voltage
2.4
5.0
V il
Input low Voltage
-0.3
+0.4
V
IIH
Input High 'Current
(V IH = 2.4V)
-100
-300
IJ.A
III
Input Low Current
-1.0
-1.6
mA
V OH
Output High Voltage
(llOAO .;;-J,OO A)
Output low Voltage
(lLOAD .;;-3 mAl
Output High Current (Sourcing)
(V OH ~2.4V)
(V OH ;'1.5V. VIA PBO·PB7 onlv)
2.4
5.0
V
-
0.4
V
-100
-1.0
-
1.6
-
VOL
IOH
IOl
TTL
OCnL
V
(V l l = O.4A)
Output low Current (Sinking)
(VOL';; O.4V)
-Industry standard LS nL.
-Industry standard Open Collector LS nL.
'"
p.A
mA
rnA
.,
3STTL
TPnL
-Industry standard Tri-State LS TTL.
-Industry standard Totem Pole LS TTL.
II
AIM 65 Microcomputer
PORTA
(10 LINES)
PORT B
(10 LINES)
~IONCONNECTOR
U.SER-DEDICATED
R6522 VIA
...J
oQ:
READIWRITE
MEMORY (RAM)
(1K OR 4K)
I<====================~~oo
...«
~
lZ"
~
o
o
«
PROM/RAM
EXPANSION SOCKETS
.
(UP TO 12K)
I
~
K:=::>t.:;:'"
~
en
>
en
ADVANCED
INTERACTIVE
MONITOR
(8K)
54·KEY
TERMINAL STYLE
KEYBOARD
AIM 65 Microcomputer Block Diagram
7-8
A65;.100, -400
AIM 65 Microcomputer'
MONITOR COMMANt)S
TEXT EDITOR COMMANDS
R - Read lines into text buffer
I
- Insert line into text buffer
K - Delete current line of text
(SPACE)-'-Display current line of text
L ~ List lines of text to peripheral I/O device
U - Mpve up one lirl!'l
D - Move down one line
T - Go to top line of text
8 - Go to bottom line of text
F - Find character string
C - Change character string
Q - Quit Text Editor, return to MOnitor
Major Function Entry
(RESET 8utton)-Enter and Initialize Monitor
ESC - Reenter Monitor
.
E - Enter and Initialize Text Editor
T - Reenter Text Editor
N - Jump to DOOO
5 - Jump to 8000
6 - Jump to 8003
Instruction Entry and DisassembJy
K
-
Enter mnemonic instruction entry mode
Disassemble memory
AIM 65 Memory Map
FFF F
Display/Alter Registers and Memory
- Atter Program Counter to (address)
A - Alter Accumulator to (byte)
X - Alter X Regi~er tq (byte)
Y - Atter Y Register to (byte)
P - Alter Processor Status to (byte)
S - Alter Stack Pointer to (bYte) ,
'R -"-'-Display all registers
M - Display four memory locations, starting at (address)
(SPACE) - Display next four memory locations
I - Alter current memory location
~
EOOO
DFF F
OPTIONAL
ASSEMBLER
DOO0
CFF F
~~~~!':
OPTIONA
PL/6S--
OPTIONAL
Pascal··
BOO0
AFF F
AIM 65
ON.BOARD I/O
AOOO
9FF F
-
Clear all breakpoints .'
:4 . - ..Toggle breakpoint enable orv'off
8 - Set one to four. breakpoint addresses
?, .....: ,Display. breakpoint addre,sses
ON-BOARD
.-
RESERVED
COOO OPTIONAL
BFF F BASIC*·
Manipulate Breakpoints
#
AIM6S
DEBUG MONITOR
TEXT EDITOR ROM.
.,
:.,
RESE,RVED*
8000
7FF F
, I
OPTION,AL
USER AVAILABLE
p .•~al,*·
,OFF-BOARD
4000
ContrOllnstructlonlTrace
3FF F
, G - ExecUt'e user's program
Z --t Toggle instruction trace rnode, pn!off.
V"""Toggle register trace mode on/off
. H -'-',TraceProgram Counter history ,
.',"
"
1000
..( ?,'
"
.'
:.
FF F
USE R AVAILABLE
4A0
49 F·
Control Peripheral Devices
,L - Lo8ct object cqde into memory from peripheral I/O device
D - Dump object code to peripheral 1/0 device
1 - Toggle Tape 1 controlorv'off
2 - toggle Tape.2 control on/off
,3 - Verify tape checksum
CTRL PRINT - Toggle Printer orv'off
LF-Une Fe~d
PRINT - Print Display contents
"
unR AVAILABLE'*
200
IF F
6502 STAO~ AND
AI1YI6~,lI~~TEM
100
"
1:' F
,"";
0
, P~GE
"
,
;"
0'"
;,',
,,:'-,
.. :' .'
','
~iJSER AVAiLABL~ M~NIT~R/E~ml~IS ~,~
IF
USED,
'~USE,I\ AV AlL,NJLEI F OfITIOII!AL LANCU,AGEI,'NOT ~$ED;
.LMiGUACE
~
O:DEO-D6
Call User-Defined Functions
0·A4
F1 - Call User Function 1
F2 ;.... Call User Function 2
F3 - Call User Functjon 3
PL/611
Pasca.
Monit;or /Editor
7-9
0,04
,"06-B4.FC'FF
DF·FF
P~E2-4.
~'t
NOl'.USED
2Iio.211
i~';;~A
'200'.\1';
201).!2'FF
NtlTUSED
II
A6S-0500
,
"
AIM 65 Microcomputer Family
'1'
Rockwell
A65-0500
AIM 65 MICROCOMPUTER SYSTEM
DESCRIPTION
FEATURES
The AI~ 65 "500" Series Microcomputer Sysblm off~rs the POP:
ular AIM '65 Microcomputer,power supply, iritereonnectwiring,
switches, and attractive injection molded enclosure-all fully
connected, assembled, and relldyfor operation. Four models,
pre-configured with varying, combinations of ROM-based languages, support many different educational, scientific, or industrial IIPplications. The stylistic, low' profile, compact enclosure
with fine textured, nonreflective brown finish, complements
classroom. industrial. office or labo!atory envltonments.
.• R6502 CPU-based 'single board computer
• 20-character16~sllgment display
• 20-column thermal prinblr
• Full-size 54-key terminal-style keyboard
• ROM-resident Debug Monitor/TeXl Editor
• Parallel application connection
.• Expansion bus connection
• Includes power supply, switches and wi~ng.
• Sturdy aluminum base
• Low-profile injection moldedABS top,cover
I
An models include a full-size terminal-style keyboard and 20-
c~racier alphanumeriq display for interl3Cftve operator com-
.>-.
va
"
"
• Enclosed, plug-in memory cartridge" o.ptiol} ' for desk-top
expansion
rI"luriicati,ons'and a 2Cl-column printer for I)ardcopy records of
comp~dl"Elsults of, programs and/or data. Serial interlace
and control lines are provided for audio cassette storage of pro,grams and qata files. The microcor'nPlJter memory features 4K
byUls 01 RAM .and 8K bytes of ROM-resident interactive debug
monitor andleXl editor· in-additionto the available languages.
Most import,nt may be the flexibility afforded by the user:.
PQrt that interfaces·to application sensors, actuadedicated
tors or peripherals. Built-in
features include two 8-bit parallel
handshake and one se'rial bidirectional data ports. Two 16-bit
timer/controllers are available for time measurement or event
counting. Finally. the microcomputer bus is accessible at a connector for external expansion with the AIM 65 memory cartridge
system (A6S-905-XX), AIM 65 PROM programmer (A65-901)
or a selectio!,!of RM6S modules such as floppy disk OJ CRT
controllers.
• RM 65 peripheral, input/output and memery module expansion inblrface'
• Fully assembled.
test~ and warranted.,
ORDERING INFORMATION
va
Part No.
Description
A65-D5DD
AIM 65 MicroComputer System with 4K RAM and
12K PROM/ROM capacity
AIM 65 Microcomputer System with 4K RAIIII. 8K
BASIC Interpreter ROMs. and 4t$ PROM/ROM
capacity
,
AIM 65 MicroComputer System with 4KRAM. 8K·
BASIC Interpreter ROMs lind 4KAssemtilerROM
AIM 65 Microcomputer System w~h4K RAM, 8K
FORTH ROMs and 4K PROM'ROM capacity
A65-D515
A65-o52D
A65-o55D
Order No.
209
2D9L
217
20.0.
20.1
202
221
233
265
283
Deecription
AIM 65 Microcomputer User's Guide (1)
AIM 65 Morihor Usting(1)
AIM 65 Reference Card(1)
R650D, Programming Reference Card (1 )
R650D Hardware Manual (1)
R65DD Programming Manl/Ill (1)
,
AIM 65 BASIC Language Reference Ma,nual (2)
AIM 65 BASIC, Reference Card(2)
AIM 65 FORTH User's Manual(3)
AIM 65 FORTH Reference Card(3)
.
Notes:
1. fncluded with all models.
2. Included with A65-o515 and A65-D520.
3. Included with A65-o55D.
.AIM 65 Microcomputer System
,Document No_ 29001026
7-10
Data Sheet Oreler No_ 0126
April 1983
A6S-MOO
AIM 65 Microcomputer System
SPECIFICATIONS
""
Characteristics
-'"
Values
""
"I
Dimensions
Width
Depth
Height
13.0 in. (330 mm)
15.5 in. (395 mm)
3.9 in. (100 mm)
Weight
11 lb. (5 kg)
""
Environment
Operating Temperature
Storage Temperature
Relative Humidity
Power
Input vo~age
Fuse
Power cord
Power supply output
Interface Connector (2)
Jl (Application) and
J3 (Expansion)
"
(
O· to 500C
o· to 700C
0% to 85% (wtthout condensation)
;',
115 Vac ± 10%,47-63 Hz(1)
115 Vac, lA
6 ft., 3-conductor cord (125 VAC, 13A rating) wnh molded vinyl grounding
plug (NEMA 5-15P) Class B
5 VDC (3.0A max.)
24 VDC (0.5 ave., 2.5A peak)
44-pin edge connector (0.156 if!. ceniers)
Mates wtth Viking 2VH2211 AND5 or equivalent
Notes:
1. Power supply transformer input connections can be changed for 230 Vac ± 10% input vo~age.
2. Refer to Data Sheet Order No. 079 for AS5-100, -400 for addttional sPecifications.
7-11
AS5-002 • AG,5-00S
AIM 65 Microcomputer Family
'1'
Rockwell
A65-002~
A65-006
AIM 65 MICROCOMPUTER ENCLOSURE
PRODUCT·.OVERVIEW
FEATURES
The AIM 65 Microcomp\ller Enclosure is an attractive, professional housi"9 f.or the Rockwell AIM 65 Microcomputer. Featuring low-profile stylistic 'deSign, .fine-textured, non-reflectiVe
finish and na:ndsome brown color, the enclosure makes the AIM
65 Microcomputer a pleasing addition to the office, labora,tory.
classroom and light industrjalenvirQnment. The 13 x 15.. 5 x'
3.9 inches enclosure occupies minimal desk-top. space,
• Attractive, low-profile styling
• Compact and Portable
• Sturdy alUminum base with integral accessory mounting
brackets
• Durable injection-ll1olded ABS top cover
· -'-Acc;ess holes to Application and EXP!lnsion connectors
-.External RESET push-button switch
,:'
- PllIggl1.ble access holes to STEP/RUN and TTY/KB S\(iIitches'
-Clear plastic printer paper tear bar
The enclosure consists of a sturdy alurninum base and a.durable
injection-molded top cover. The base includes mounting provisions for the power supply, line cord, power switch and cireuit
breaker. The cover is UL approved flame,retardant A,?S material with metal threaded insel'ts for firm attachrnenuo the base.
• All necessary accessories
;,..Rocker'style power on/off switch. .
~Fuse holder
~Line.Cord
Offeree! with or without an internal, power supply, ihe enclosure
come~ with a rocker~type power on/off switch, a. pushbutton
reset. switch, a 6-foot, 115 Vac .line cord with 3-prong plug, a
fUSE!. hQlderandfuse, and internal wiring for easy assembly to
the AIM 65 Microcomputer.
'
-'-AU'assembly hardware,'included
• . OptiOnal+5V +24V internal power supply operates from 115/
230Vac @50/60 Hz
The filtered powersupply provides +5V (regulated) at 3A and
+24V (regulated) at .5A (average)/2.5A (peak). Prewired DC
power lines terminated with lugs connect directly to the AIM 65
Microcomputer power terminal strip. The AIM 65 Microcomputer
system passes the FCC Class B radio frequency interference
requirements for personal computers when used with the A65006 Enclosure and power supply.
An external paper holder and paper feed guide allows easy
printer paper replacement without top coverremoval. A clear
plastic tear bar with a straight knife edge is permanently attached
to the lOP cover f.or convenient paper tear-off. Rear openings
permit access to. the application and expansion Gonnectors. A
remote Reset switch installed on the top cover is pre-wired to
slip-on terminals to mate with external Reset switch posts on
the AIM 65 Master Module. Removeable plugs allow access to
the RUN/STEP and TTY/KB switches on the AIM 65 Master
Module.
Document No. 29000080
7-12
Data Sheet Order No. 080
Rev_ 1, March 1983
A65-002 and A65-006
AIM 65 Microcomputer Enclosure
ORDERING INFORMATION
Part No.
A65-002
A65-006
Description
AIM 65 Enclosure (without Power Supply)
AIM 65 Enclosure and Power Supply
SPECIFICATIONS
Characteristic
Dimensions
Depth
Width
Height
Weight
without Power Supply
with Power Supply
Shipping Weight
without Power Supply
with Power Supply
Construction
Base Material
Mounting Brackets
Cover
Material
Forming
Color
Finish
Accessories
Fuse
Power On/Off Switch
Reset Switch
Value
12.9 in (328mm)
15.5 in (394 mm)
3/a.9 in ( 99 mm)
5 lb. 0 oz. (2.24 kg)
9 Ib.6 oz. (4.20 kg)
Characteristic
Accessories (cont.)
Power Cord
Type
Plug
Length
Rating
Power Supply
AC Input
6 lb. 8 oz. (2.9 kg)
10 lb. 14 oz. (4.87 kg)
DC Output 1
Voltage
Sheet Aluminum with
Chem-film finish
Integral
Current
Overvottage Protection
Flame-retardant ABS plastic
Injection Molded
Dark Brown
Non-Reflective,
fine textured
115 Vac@ IN
230 Vac @ O.5A
Rocker-style
Square Push-button
3-wire/18-gauge
US 3-prong (NEMA 5-15P)
6 feet
125V/13A
115/230 Vac ± 10%,
47-63 Hz
(Derate output current
10% for 50 Hz operation)
Adjustable +5Vdc±5%
(regulated)
3.0A
6.2±0.4Vdc
DC Output 2
Voltage
Current
Adjustable+24Vdc (regulated)
0.54 (average)/2.5A (peak)
Short Circuit Protection
Automatic current limiVfoldback
Temperature Rating
UI,. Recognized
7-13
Value
0° to 50°C full rated output
(Derated linearly) to 40%@70°C
o
A65-003
AIM 65 Microcomputer Family
'1'
Rockwell
A6S-003 '
AIM 65 SERVICE TEST 80ARD
DESCRIPTION
FEATURES
The AIM 65 Service Test Board, in conjunction with the AIM 65
Microcomputer and AIM 65 Debug Monitor ROMs, performs E!
complete funCtional test of the microcomputer. This test board
provides a convenient way to test the AIM 65 microcomputer
eHher after repair or during periqdic inspection andpreve\ltative
maintenance. The module connects directly to. the AIM 65
Microcomputer Application. and Expansion connectors. Power
is supplied from the AIM 65 Microcomputer eliminating additional power eonnectIQn requir~ments.
•
•
•
•
•
Performs complete functional test
No external equipment required
Provides hardcopy test results
ROM-based 4K-byte test program for immediate qperation
Performs five tests upon command
-ALL TESTS
-SINGLE TEST
-CONTINUOUS TEST
-R6532 RAM TEST
-2114 RAM TEST
• Tests nine separate functions i!l ALL TEST l'11oc/e or upon
SINGLE TEST command
-Chip select logic
-ROM checksum
- R6532 and 2114 RAM
-User R6522'YIA'·
The ROM-based test program can be initiated immediately after
micl'Qcornputer powerWrn-on.Menu type. command Pr'Qtnpts
simplify test selection. Five. separate commands allQW test leVel
selection appropriate to the test Qbjective. ALL TESTS selection
perfOrms nine separate tests consecutively to check all microcomputer circuits as Well as the application and expansiol'linter~
faces. Once initiated •. qperation Js automatic with oPerator
response required only to t}tpe keys to test the keybOard and
to advance testing after priht(jlradjustment. SING!-E TESTr;node
allows a specific test tqbe performed-this is especially useful
when testing a particular device or circuit. CONTINUOUS TEST
performs a repetitive test of the microcomputer wHhout oPerator
intervention-thus supporting burn-in operation and test after
component replacement. R6532 and 2114 RAM can be selectively checked with the R6532 RAM and 2114 RAM tests,
respectively.
.
•
•
Test commands and· results are displayed and printed. The
printout provides hardcopy test results for easy inclusion in
equipment maintenance records. Adjustment of potentiometers
controlling printer speed, printer dot intensHy and audio tape
circuit gain enables proper and consistent settings. An LED provides visual indication of proper audio circuit gain adjustment.
Mechanical adjustment of printer gear alignment is also
supported.
•
•
•
-System R6522 VIA.
-Display
-Printer
-Switch
-Keyboard
Isolates most failures to component level
Supports calibration of variable adjustments
-Audio tape circuit gain
-Printer speed
-Print intensity
-Printer dot alignment
Audio tape circuit gain adjustment LED indicator
Easy installation-connects directly to AIM 65 Application
and Expansion connectors
No external power required
ORDERING INFORMATION
Part No.
A65-003
Order No.
2117
Document No. 29001024
7-14
Description
AIM 65 Service Test Board
Description
AIM 65 Salf-Test Module User's Manual
(Included with A65-OO3)
Data Sheet Order No. 0124
April 1983
AIM 65 Service Test Board
',:'!Il
ASS,003 AIM
ssserVlj:e Test Module
7-15
II
A65~Q04·Q3
AIM 65 Microcomputer
'1'
Rockwell
FS:n;,y
A65-004-03
AIM 65 POWER SUPPLVAND CABLE
DESCRIPTION
• D4al AC1~put voltage'
':":110 or 115
@47cp3 Hz
-215 or 230 Vac@ 4Hl3l;iz
The AIM 65 Power Supply and Cable is a·compact ope~ frame
DC power supply with output Cable for connection to an AIM 65
Microcomputer. The pO,wer' supply. fits compactly. inside ttle
AIM.65 Enclosure (A65-002) to provide ,a complete table top
microcomputef,systEii)'J. The' +5V/3A ()utput provides PIsn!yof
power for full on-board PROM/ROM arid RAM expanSion. The
+24V/j';5A output supplies POWerfortheAIMS5 microcomputer
printer.
o~the
vao
indui)erini~k'
Slip-onterminals
AC'
,strip. simplify conne(jtion to"a""ide range. of input ,power: 1101l15121,s/230 Vac'
at 47-63 H;z. fThe 3-wire. DCoutput.cable, factory connected to
the power supplyoutpl1t terminals,can bEl readily connected to
theAIrv'! 6:;;. inpllt'pOwer termiAals.··
,"
,
,
.
or
• Two DC output vOlta$eS
- +5V for AIM 65 Microcomputer logic
""'" + 24V for AliI,4SSlll/icrooomputeriprintEir
• Slip-oninput' (;Qnl1ectlRn .....•,. . . '.
.Compact size:.,....fits,in:'AIMB5:SI1!.7iosur.e
"
....... '.
• Meets FCOGlassBAFlreQuirements for personal cQmputers
wh!3n cc).mectecrtot~ AIM 6& Mjcrpcomputer
.
Both outputs areCUfrent limited to preVent d~mage to the, power'
supply if. the outpulsareoverloa,dedor accidentli"Y shorted
together. Full power is provided from o~ to 50°C.
AS5,-OO4-03 F'ower Supply
Document No. 29.001 D25
7-16
Data Sheet Order No. D125
April 1983
AIM 65 Power Supply and Cable
A65-004-03
SPECIFICATIONS
Parameter
AC Input
Value
Parameter
115/230 Vac ± 10%, 47-63 Hz
(Derate output current 10% for 50
Hz operation)
Dimensions
A
B
DC Output 1
Voltage
Current
Overvoltage Protection
Adjustable +5 Vdc ± 5% (regulated)
3.0A
6.2 ± 0.4 Vdc
DC Output 2
Voltage
Current
C
D
E
F
G
H
I
Adjustable +24Vdc (regulated)
0.5A (average)/2.5A (peak)
J
Short Circuit Protection
Automatic current limiUfoldback
Temperature Rating
O'C to 50"C full rated output (Derated
linearly to 40% @ 70"C)
K
L
Output Cable
Length
Type
Load Termination
Routed Outputs
Value
6.31 in. (160.3 mm)
4.50 in. (114.3 mm)
3.78 in. (96.0 mm)
1.62 in. (41.3 mm)
0.45 in; (11.4 mm)
1.10 in. (27.9 mm)
2.12 in. (53.8 mm)
0.95 in. (24.1 mm)
1.24 in. (31.5 mm)
3.62 in. (91.9 mm)
1.20 in. (30:5 mm)
8-32 THD (3)
10 in. (254.0 mm)
3-wire jacketed with internal balun
Spade lugs
+5V, +24V and COM
DC OUTPUT TERMINAL'
AC INPUT TERMINAL
+24+5 COM
DOODDD
'I-
A
-'------+i-I
'SHOWN WITHOUT DC OUTPUT CABLE ATTACHED
7-17
II
A65-010
AIM 65 Microcomputer Family
'1'
Rockwell
A65-010
AIM 65 ASSEMBLER ROM
FEATURES
ASSEMBLY LANGUAGE
•
•
•
•
An assembler translates microprocessor instructions and data
statements written in symbolic form (the source program) into
machine executable code (the object program). The AIM 65
Assembler translates one instruction, consisting of a label (if
required), a mnemonic operation code, an Qperand (if required)
and arithmetic operator (if required) into a machine instruction
consisting of from .one to three bytes of memory. Constants
comprising one or more bytes of memory are generated from
data statements while one or more bytes of memory are assigned
to variables. The assembler operates in two passes. Pass 1
checks for syntax errors and assigns values to symbols in a
symbol table. Pass 2 generates the actual. machine code and
outputs the assembly listing which lists the source code and the
corresponding machine code.
~
•
•
The source code is usually entered using the AIM 65 Text Editpr
then assembled to generate the machine code for program
execution and debugging. Program changes to the source program can easily be edited then .the program reassembled to
generate the new machine code thus eliminating the need for
the programmer to code and recode the program in machine
code-a time consuming and laborious process.
•
•
•
PRODUCT OVERVIEW
AIM 65 Microcomputer host
6502 machine code generation
ROM-resident for immediate operation
Symbolic linkage-operands and labels
·Interactive assembler operation setup
Operator selected input device
-Memory (text buffer)
-Audio tape
-TTY
- User defined
Operator selected object code output device
-Memory (RAM)
-Audio tape
-TTY
- Display/printer
-Printer
-User-defined
Operator selected assembly/error listing output device
-Display/printer
-Printer
-User-defined
Assembler directives
AIM 65 DOS 1.0 compatible
MEMORY MAP
The AIM 65 Assembler is a 4K-by.te ROM-residenl,two-pass
symbolic assembler that plugs into socket Z24 on the AIM 65
Microcomputer Master Module and operates in conjunction with
the AIM 65 Debug Monitor/Text Editor ROMs. The assembler
translates computer program instructions written in standard
assembly language for the 6502 microprocessor into machine
code that will operate in any 6502 or 65XX CPU. Operating
options are selected interactively by the operator upon assembly
command. These options specify source cod.e device, object
code device, symbol table location, full assembly or errors. only
output listing and output listing device. Memory to memory
assembly is supported for rapid program generation. Compatibility with the 'RM 65 Floppy Disc Controller (FDC) module
(RM65-5101NE) and AIM 65 DOS 1.0 ROM (A65-090) allows
source code to be input from one or more files on floppy disk
and object code to be output to a floppy disk file to assemble
very large programs and to permanently save source and object
code.
Address (Hex)
$DOOO-$DFFF
SO-SAC
Contents
Assembler Program
Assembler Variables
ORDERING ·INFORMATION
Part No.
A65-0W
Order No.
209
Document No. 29001012
7-18
Description
AIM 65 Assembler ROM
Description
AIM 65 User's Guide
(includes AIM 65 Assembler
User's Instructions)
Data Sheet Order No. 0112
April 1983
AsS-Ota
AIM 65 Assembler ROM
R6502.CPU INSTRUCTIONS
I_Ion
......onlc
Mnemonic
Add Memory to Accumulator ~ith Carry
. ,AND Memory Wfth1\CCumulator
.,
. Shift Left One Bft (Momory or Accumulator).
ADC
AND
ASl
ace
acs
BNE
BPl
BRK
BVC
BVS
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in MeI'T'lCH'y with Accumulator
Branch on Result Minus
Branch on Result Not Zero.
Branch on Result ptus
Foroe Bleak
Branch on 9verftow.Glaar
Branch on 0118"- Set
ClC
ClD
Cli
ClV
CMP
CPX
CPV
Clear Carry Reg
Clear Decimal Mode
Clear InterruPl OIsabie
Clear 0118"- Rag
COfnpare Memory and
COfnpare Memory and
Compare Memory and
DEC
DEX
DEY
Decrement Memory by One
Decrement Index X by One
Decrement Inde. Y by One
EOR
Excluslve-OR Memory with Accumulator
INC
INX
INY
I..,remont Memory by One
Increment Index X by One
Increment Index Y by One
JMP
JSR
Jump to New location
Jump to New location Saving Retum
BEQ
BIT
8M1
Inetructlon
Load Accumulator with Memory
LoadlndOt,Xwith Mem~
Load Index YwHh Memory
Shift Right Ona BH (Memory or Accumulator)
LOA
lDX
LOY
LSR
NOP
NoOpor~
ORA
OR Memory with Accumulator
PHA
Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
PHP
PLA
Bit
PlP
Pull Processor. Statu~, ~m St~k
ROl
ROR
RTI
RTS
Rotate One Bit Left (Memory Of Accumulator)
Rotate One BK Right (Memory or Accumulator)
Return from Interrupt
Return from Subroutine
SBC
Subtract Memory from Accumulator with Borrow
Sot Carry Reg
Set Decimal Mode
Set Interrupt Disable Status
Store Accumulator In ~mory
SEC
AccumulalOf
Index X
Index Y
SED
SEI
STA
STl(
STY
"
Stole Index X In Memory
Store Index Y in Mambry
TAX
TAY
TSX
Transfer Accumulator to Index X
Transfer Accumulator to Inde~ Y
Transfer Stack ,Pointer to Index X
TXA
Transfer Index, X to Accumulator '
TXS.
TVA
Transfer Index X to Stack Pointer
Transfer Index Y to Accumulator
~~ss
AIM 65 ASSEMBLER DIRECTIVES
Command
Function
=
Equate
Byte conStant
Word constant
Double-byte constant
Page heading
Skip li/le
.',
.BYTE
.WORD
.DBYTE
.PAG
,SKIP
Command
.OPT
LISINOL
GEN/NOG
ERR/NOE
.,FILE
,END
7-19
Function
Usting' control option
Assembly listing generation
Object code question
Error listing generation
Source Code file linkage
'Last statement/lirst source code Hie linkage
II
A65-020
AIM 65 Microcomputer Family
'1'
Rockwell
A65-020
AIM 65 BASIC INTERPRETER ROMS
BASIC LANGUAGE
installed in the RM 65 SBC module. In this configuration, all RM
65 input/output operations must be user-provided and can be
tested using the AIM 65 Microcomputer prior to being installed
in the RM 65 environment.
BASIC is a simple but powerful computer program language.
Originally developed at Da.rtmouth University, BASIC has gained
universal acceptance and is commonly used world-wide in
schools, industry, and science.
LANGUAGE FEATURES
The heart of BASIC is a set of easily learned English words
which are used as commands. Complex and powerful statements can be constructed by adding operands and operators
to the commands. Equations involving complex formulas and
multiple variables can easily be solved. Interhal floating
point arithmetic handles a wide range of numeric values
(2.93873588E -39 to 1. 70141183E+38) and provides nine-digit
accuracy to most calculations. In addition to addition, subtrae;tion, multiplication and division, a full set of transcendentalfunctions support trigonometric, exponential, square, square root,
polynomial and logarithmic operations.
•
•
•
•
•
•
•
•
•
•
PRODUCT OVERVIEW
The AIM 65 BASIC Interpreter, consisting of input formatter,
lister, floating point functions, interpreter and input/output functions, is contained in two 4K-byte ROMs that plug into sockets
Z25 and Z26 on the AIM 65 Microcomputer Master Module. AIM
65 BASIC operates in one of two modes, development and runtime. In the development mode, BASIC statements are entered
and executed as either direct or indirect commands. Direct commands are executed upon entry to provide immediate results,
however, the statements are not stored for subsequent execution. Indirect commands are entered along with an associated
line number and are executed upon RUN command entry. The
AIM 65 microcomputer peripherals, i.e., the keyboard, 20-character single line display and 20 column printer, are used in the
development mode to enter statements, to list entered indirect
statements and to display/print execution results. The AIM 65
Debug Monitor/Text Editor ROMs must be resident in both the
run-time and the development mode.
BASIC is easy to learn
Microsoft BASIC is universally accepted
BASIC is widely used
Supports simple and complex statements
Floating point arithmetic functions
-Add, subtract, multiply, divide
- Trigonometric (sine, cosine, tangent, arctangent)
-Exponential, square, square root
-Natural logarithm
String variables and arrays
Integer variables
Subroutfne calls
Conditional expressions
User function
INTERPRETER FEATURES
•
•
•
•
AIM 65 Microcomputer host
ROM resident for immediate operation
Operates in development and run-time modes
Fast execution (reference Microsoft 6502 BASIC
interpretation)
• Develops programs for execution in AIM 65 Microcomputer
with AIM 65 BASIC installed or in RM 65 Single Board Computer (SBC) module based system with RM 65 Run-Time
BASIC installed
• Executes application program from RAM or PROM
In the run-time mode, BASIC begins execution of the application
program (i.e., previously entered indirect statements) without
entering the BASIC command level. A short user-provided driver
program initiali~es BASIC upon entry from the AIM 65 Monitor
command level via key depression or execution command (or
upon power turn-on or RESET if the RESET vector points to the
application program).
ORDERING INFORMATION
Description
Part No.
A65-020
RM65-0122
AIM 65 BASIC ROMs
RM 65 Run-Time BASIC ROM
Order No.
221
233
810
The AIM 65 BASIC Interpreter ROMs, when installed in the AIM
65 Microcomputer, support development and checkout of an
application program written in BASIC that is to be installed in
an RM 65 Single Board Computer (SBC) module for run-time
operation. The developed program, located in PROM or loaded
from mass storage, will run with RM 65 Run-Time BASIC ROM
Description
AIM 65 BASIC Language Reference Manual'"
AIM 65 BASIC Reference Card'"
RM 65 Run-Time BASIC User's Manual'"
Notes:
1. Included with A65-020.
2. Included with RM65-0122.
Document No. 29001004
Data Sheet Order No. 0104
April 1983
7-20
A65-020
AIM 658ASIC InterpretefROMs
PROM PROGRAMMING
MEMORY MAP
Add.....
,Hex) .
$BOOO~CFFF
$2()()-$20F
$0.$06
!he.;application program' is eaSi!yprogtainm~(tinta aPR6~'j~{
oPeration .in an OEM or end-user environmEmtusing the ~,~.~5
Microctimput~r .!:Onnected to eit~r an .RM.~ PROM". ~ro
grammer module. (RM65-2901 E) or
AIM 65 PROM Programmer and CO-eO Modul8 (A~-901).
'Conl8nts
AIM 65 BASIC
AIM jl5 BASIC
AIM
BASIC
65
Program
an
Variables
Variables
BASIC STATEMENT~
progr&m $tatemenls
Commends
String Functions
DEFFN
CLEAR'
CONT
.FRE
LIST
LOAD
NEW
PEEK
POKE
RUN
ASC'
CHR$
DIM
END
FOR
GOSUB
OOTO
IF ... GOTO
IF ... THEN
LET
SAVE
.NEXT
ON ... GOSUB
ON ..• GOTO
REM
RESTORE
RETURN
STOP
USR
WAIT
Input/Output
DATA
GET
INPUT
READ
PRINT,
.SPC
TAB
, POS
lB";T$
'·Ll:N
MID$
RIGHTS
STR$
VAL
ArithmetIC Functlcins
ABS
ATN'
COS
EXP
INT
LOG
RND
SIN
SGN
$OR'
TAN
·Unks.lo uSer-provided fuOCliQll....
, ' .
' I
)"'j
A65-024
AIM 65 Microcomputer
'1'
Rockwell
A65-024
AIM 65 BASIC COMPILER
LANGUAGE FEATURES
BASIC LANGUAGE
BASIC is a simple but powerful computer program language.
Originally developed at Dartmouth University, BASIC has gained
universal acceptance and is commonly used world-wide in
schools, industry, and science.
•
•
•
•
•
The heart of BASIC is a set of easily learned English words
which are used as commands. Complex and powerful statements can be constructed by adding operands and operators
to the commands. Equations involving complex formulas and
multiple variabJes can easily be solved. Internal floating
point arithmetic handles a wide. range of numeric values
(2. 93873588E -39 to 1. 70141183E't38) and provides nine-digft
accuracy to rnost calculations. In addition to addition,' subtraction,
multiplication' and division, Ii full set of transcendental functions
support trigonometric, exponential, square, square root, polynomial and logarithmic operations,
•
•
•
.•
BASIC is easy to learn
Microsoft BASIC is universally accepted
BASIC is widely used
Supports simple and complex statements
Floating point arithmetic functions
-Add, subtract, multiply, divide
.-Trigonometric (Sine, cosine, tangent,arctangent)
'-Exponential, square, square root
-Natural logarithm
String variables and arrays
Integer variables
Subroutine calls
Conditional expreSsions
• User function
PRODUCT OVERVIEW
COMPILER FEATURES
The AIM 65 BASIC Compiler, consisting of the BASIC compiler
and BASIC run-time library, is contained on an AIM 65 diskette.
The BASIC Compiler, in conjunction with the BASIC run-time
library, compiles a program wrttten in the BASIC language into
a 6500 assembly language source file and an optimized runtime library file. The BASIC source code file is made up of
indirect BASIC commands and statements. The two output files,
assembly source file .and optimized run-time file, are then
assembled using the AIM 65 Assembler to create a BASIC
object code file for execution.
• Aim 65 Microcomputer host
• Generates standalone object code
• Compiles to 6500 assembly language easing optimization
• Fast execution
• Develops programs for execution in AIM 65 Microcomputer
without AIM 65 BASIC installed or in RM 65 Single Board
Computer (SBC) module based system without RM 65 RunTime BASIC installed
• Executes application program from RAM or PROM
The AIM 65 Text Editor can be used to create and edit the
application program source code. The AIM 65 peripherals, i.e.,
keyboard, 20-character single-line display and 20-column printer,
are used to enter and list BASIC statements and to display/print
execution results.
ORDERING INFORMATION
Part No.
Description
A65-024
AIM 65 BASIC Compiler
Order No.
The disk-based compiler operates on the AIM 65 Microcomputer in conjunction with the RM65 Floppy Disk Controller (FDC)
module and the AIM 65 DOS 1.0. The AIM 65 Assembler (Part
No. A65-010) is required to support the BASIC Compiler on the
AIM 65 Microcomputer.
2159
233
Description
AIM 65 BASIC COmpiler User's Manual(1)
AIM 65 BASIC Reference Card(1)
Note:
1. Included with A65-024.
Document No. 29001010
7-22
Data Sheet Order No. 0110
August 1983
A6S·d24
,MEMORY
AIM 65 BASIC Complier
MA~
PROM. PA6GRAM'MIN~: .:);"; ,:;,:)\,~~]i"j/,
-.
Co~,
Addre.s (Hex)
$1000-$$000
$O-$FF
"
The application program is easily PIC~ramlTled' into a' PROM fOr
operation In an OEM or end-useit.nVlronm,..rli' usin,g ,tt!~:~!M:65
MiQl'CIqolTlPl:!ter connected to alther,.··an, .,l;IM !s,p.. PRPM-P~,;grammer"module (AMElS-29011!), Qf an':JldM,EI5' PAOM' Pre)grammer and CO~EP Module (A85-9P1)i
. 0.-r¥I;, .,
"':'"
,-
AIM 65 BASIC Obmpl18r
",
AIM:$,.~ASIC
V.labla.
BASIC STATEMENTS
Progrsm Statemsnts
DEF FN
DIM
END
FOR
GOSUB
GOTO
IF ... GOTO
IF." THEN
LET
NEXT
ON .. ,GOSUB
ON ... GOTO
REM
RESTORE
RETURIIl '
STOP
String Function.
PEEK
: POKE
ASC
~HR$
Input/Oulput
DATA
GET
'INPUT
READ
PRINT
SPC
TAB
LEFT$
LEN
, MID$
RIGHT$
_STR$
VAL
, Arlthmttlc Functions
ABS
ATN*
COS
EXP'
INT
LOG.
pas
U~R-
RNo
WAIT
SIN
SGN
'$OR
'-, TAN
'Woks to user-provided functiorl.
,
7-23
~:
11
A6S-030
AIM 65 Microcomputer Family
'1'
Rockwell
A65-03D
AIM 65 PL/65 COMPILER ROMS
PL/65 LANGUAGE
FEATURES
PU65 is a high level language developed for the R6500 family
of microprocessors. Resembling PUI and Algol in general form,
PU65 combines high level language attributes with the power
and flexibility of assembly language for efficient generation of
time-critical and system implementation software. High .Ievel
constructs speed program development and eliminate machine
coding errors by the use of compiler generated algorithms. All
language features are aimed at improving the productivity of the
'systems programmer by simplifying the writing of computer programs normally written in assembly language.
•
•
•
•
•
•
•
AIM 65 Microcomputer host and target
ROM resident for immediate operation
Resembles PUI and Algol
Increases program productivity and efficiency
Improves program reliability
Reduces programming errors
Drops down to assembly language by block or single instruc, tion for optimal code efficiency
• Includes control structures for conditional branching and iterative looping
• Supports structured programming and se,lf,documentation
• Encourages modular program design
• Compatible with RM 65 FDC mOdule and AIM 65 DOS 1.0.
PRODUCT OVERVIEW
The AIM 65 PU65 Compiler is contained in two 4K-byte ROMs
that plug into sockets 225 and 226, on the AIM ,65 Microcomputer Master Module, The compiler operates in conjunction with
the AIM 65 Debug Monitor/Text Editor ROMs. Source code
written in PU65 is compiled into assembly language instructions
rather than 6502 CPU machine code to allow program enhancement at the assembly level, if needed, and to avoid symbol
manipulation in the compiler. Drop down capability allows
assembly language to be incorporated in-line in the source
code, however. The generated assembly language may then be
assembled on the AIM 65 Microcomputer using the AIM 65
Assembler ROM.
MEMORY MAP
Address (Hex)
$BOOO-$CFFF
$0200-$049F
$0-$4
Compatibility with the RM 65 Floppy Disk Controller (FDC)
module and AIM 65 DOS 1,0 firmware allows efficient mass
storage and file handling of source code written in PU65, the
PU65 compiler generated assembly language and the assembled machine code-especially for large programs. The compiler inputs source code from the AIM 65 Text Editor, audio tape,
TTY or user-defined devices and outputs assembly code to display/printer, memory, audio tape, TTY or user defined devices.
The floppy disk interface is implemented through the user-defined
functions via DOS 1 ,0 firmware.
Contents
PU65 Compiler Program
PU65 Compiler Variables (Compilation Only)
PU65 Compiler Variables (Compilation and
Runtime)
ORDERING INFORMATION
Part No.
A65-030
A65-010
Order No.
257
PU65 compilers have also been implemented on the AIM
65/40 Microcomputer and the System 65 Development system
to allow programs written in PU65 to be transported between
these systems, AIM 65 and AIM 65/40 PU65 is a subset of the
System 65 PU65,
Description
AIM 65 PU65 Compiler ROMs
AIM 65 Assembler ROM'"
Description
AIM 65 PU65 Compiler User's Manual" 1
NOTES:
1, Included with A65-030.
2. User's instructions included in AIM 65 User's Guide
(Order No. 209).
Document No. 29001N09
7-24
Data Sheet Order No. 0109
March 1983
AIM 65 PU65 Compiler ROMs
A65-030
PU65 LANGUAGE STATEMENTS
Speclflc,atlon
ENTRY
EXrr
TFILE
DFILE
Imperative
BlOck
BEGIN
DO
END
SHIFT
ROTATE
ASSEMBLY CODE
INC
INCW
DEC
OECW
STACK
UNSTACK
Declaration
Cond"lonal Execution
IF-THEN-ELSE
DECLARE
DEFINE
DATA
Branching
GOTO
CALL
RETURN
RTI
BREAK
HALT
Assignment
Looping
Direct Single Byte Move
Indirect Single Byte Move
Direct Multiple Byte Move
FOR-TO-BY
WHILE
Miscellaneous
Comment
Tab
IJ
7-25
A65-040
AIM 65 Microcomputer Family
'1'
Rockwell
A65-040
AIM 65 MATH PACKAGE ROM
FLOATING POINT ARITHMETIC
FEATURES
Floating point arithmetic is often desired to perform mathematical operations in calculation intensive applications such as scientific computation,. industrial data acquisition and reduction,
process control, and laboratory measurements. In the AIM 65
Math Package, a number is represented in floating point form
as an unsigned exponent, a normalized mantissa and an arithmetic sign. The magnitude of the number is equal to two raised
to the exponent power times the fractional mantissa, where the
exponent may range from -127 to + 127. The mantissa is a 32bit number normalized such that the most significant bit (MSB)
is always equal to "1". Operating on floating point numbers
alleviates programming difficulty and additiOnal development
time usually associated with fixed point scaling and minimizes
uncertainties when performing calculations involving both very
large and very small numbers. Numbers in magnitude from
2.93873588E-39 to 1.70141183E+38 can be handled in the
AIM 65 Math Package. In addition, nine digit accuracy is provided in most calculations.
• Floating point arithmetic
-Addition and subtraction
-Multiplication and division
• Integer arithmetic
-Multiplication
-Division
• Comparison «, =, »
• Trigonometric
-Sine and cosine
-Tangent and arctangent
• Conversion
-Degrees to radians
-Radians to degrees
• Polynomials
-Consecutive power
-Odd power
• Logarithmic
-Natural log
-Common log
• Square root, power, exponential
• Absolute value, integer and floating point sign, greatest integer
• 6502 CPU machine instruction linkage
• Host computer independent
• AIM 65 FORTH and RM 65 Run-time FORTH compatible
PRODUCT OVERVIEW
The AIM 65 Math Package contains a full complement of floating
point arithmetic, conversion, trigonometric, utility and other transcendental functions as user callable subroutines in a 4K-byte
ROM. Programmed in 6502 machine language for fast execution, these functions support calculation intensive applications.
These functions are host computer independent and may be
installed in any 6502 CPU based microcomputer supporting the
memory map requirements. The math package is located at
$DOOO-$DFFF to allow direct installation in an AIM 65 Microcomputer, an RM 65 Single Board Computer (SBC) module or
in an RM 65 PROM/ROM module.
• 4K-by1e ROM based
• Nine digit accuracy
• Wide range (2.93873588E-39 to 1.70141183E+38)
ORDERING INFORMATION
Part No.
In addition to the machine language interface, direct linkage to
AIM 65 FORTH and RM 65 Run-Time FORTH provides floating
point processing in the FORTH language. When installed in an
AIM 65 Microcomputer with AIM 65 FORTH also installed, the
floating point words can be automatically linked to the FORTH
vocabulary during FORTH initialization. Application programs
written in FORTH can thus be both developed and executed on
the AIM 65 Microcomputer. For OEM or end user installation in
an RM 65 system with user-provided input'output functions,
such programs can be developed on an AIM 65 Microcomputer
then transferred to an RM 65 SBC based system with RM 65
Run-Time FORTH installed for execution in the RM 65
environment.
A65-040
A65-050
RM65-0152
Description
AIM 65 Math Package ROM
AIM 65 FORTH ROMs
RM 65 Run-Time FORTH ROMs
Order No.
2118
265
812
Description
AIM 65 Math Package User's Manual'"
AIM 65 FORTH User's Manual'"
RM 65 Run-Time FORTH User's Manual'"
Notes:
1. Included with A6S·040.
2. Included with A65-050.
3. Included with RM65-0152.
Document No. 29001006
7-26
Data Sheet Order No. 0106
March 1983
A65-040
AIM 65 Math Package ROM
MEMORY MAP
Address (Hex)
$DOOO-$DFFF
$AB-$C4
$25C-$27E
Contents'
AIM 65 Math Package Program
AIM 65 Math Package Variables
AIM 65 Math Package Variables
MATH PACKAGE FUNCTIONS
Assembly
Language
Label
INIT
FADDT
FAOO
FSUBT
FSUB
FMULTI
FMULT
FDIVT
FDIV
FORTH
Word
F+
F-
P
F/
Function
Initialize
Floating
Floating
Floating
Math, Package
Point Add
Point Add (Memory)
Point Subtract
Floating
Floating
Floating
Floating
Point
POint
Point
Point
Subtract (Memory)
Multiply
Multiply (Memory)
Divide
Floating Point Divide (Memory)
Integer Multiply
IMULT
IDIVID
FTOD
Integer Divide
Convert Floating Point to Integer
DTOF
NEGFAC
Convert Integer to Floating Point
Negate Roating Point Number
ABS
FABS
INT
SGN
SIGN
FCOMP
INT
SQR
FPWRT
EXP
LOG10
LOG
SGN
FSIGN
FCOMP
SQR
t
EXP
LOG
LN
Absolute Value of Floating Point
Number
Truncate Floating Point Number
Sign of FAC to FAC
Sign ,of FAC to ARG
Compare Floating Point Number
Square Root·
Assembly
Language
Label
FORTH
Word
Function
SIN
SIN
COS
TAN
COS
TAN
Sine
Cosine
Tangent
ARCTAN
DEGRE
RADS
ARCTAN
DEGREES
RADIANS
POLYODD
Arc Tangent
Convert Radians to Degrees
Convert Degrees to Radians
Odd Exponent Polynomial
POLY
M>F
Consecutive Exponent Polynomial
Move Number from Memory to FAC
F>M
Move Number from FAC to Memory
POLYX
POLY
MOVFM
MOVMF
MOVFA
MOVAF
CONUPK
FIN
FOUT
MINLN
DECLN
Raise to a Power
Exponential
Common Log
Natural Log
7-27
M>A
S>A
S>F
Move Number from ARG to FAC
Move Number from FAC to ARG
Move Number from Memory to ARG
Move Number from Stack to ARG
Move Number from Stack to FAC
F>S
Move Number from F~Cto Stack
FIN
Convert ASCII to Floating Point
FOUT
Convert Floating Point to ASCII
MIN-WIDTH
FOUT Minimum Field Width Variable
DEC-LENGTH FOUl No. of Places to the Right of the
Decimal Point Variable
A65-050
AIM 65 Microcomputer Family
'1'
Rockwell
A65-050
AIM 65 FORTH ROMS
FORTH LANGUAGE
PRODUCT OVERVIEW
FORTH isa unique programming language well suited to a
variety of applications. Because it was originally developed for
real-time control applications, FORTH is ideal for machine and
process control, energy managements, data acquisition, automatic testing, robotics and other applications where assembly
language was previously the only possible language choice.
AIM 65 FORTH, consisting of primitives, interpreter, macro
assembler and input/output functions, is contained in two 4Kbyte ROMs that plug into the AIM 65 Microcomputer Master
Module sockets Z25 and Z26. FORTH functions are linked
to AIM 65 Debug Monitor and Text Editor ROMs providing
access to the AIM 65 peripherals (keyboard, single-line display
and 20 column printer) as well as user-defined inpuVoutput
functions. >Both i'nteractive and batch modes of operation are
supported. Interactive operation interprets FO RTH words upon
entry for immediate execution and debugging or for compilation.
In the batch mode, FORTH words can be entered into the Text
Buffer then input to FORTH for interpretation. The batch mode
allows an application program to be easily edited using Text
Editor commands. Application programs written in FORTH can
thus be developed, as well as executed for checkout or pro.
ductionoperation, on the AIM 65 Microcomputer.
FO RTH actually provides the best of two worlds. It has the
looping and branching constructs of high-level languages
(DO ... LOOP, BEGIN ... END, IF ... THEN and IF ... ELSE
· .. THEN) and the code efficiency of machine and assembly
languages. And programmers will be pleased to know that
FORTH allows you to specify addresses, operands and data in
hexadecimal, octal, binary or any other number base from two
to 4O-a distinct advantage over languages like BASIC, where
all information must be in decimal.
In most time-critical applications, at least part of the program
must be written in assembly language. FORTH has a built in
6502 macro assembler, and lets you drop into assembly language at almost any point in your program, without perarate
assembly and load steps or awkward machine level linkage.
FORTH programs typically run up to ten times faster than other
interpretive languages, and can even approach the speed of
machine language programs for some applications.
AIM 65 FORTH ROMs, when installed in an AIM 65 Microcomputer, can also be used to develop and checkout an application
program written in FORTH that is to be installed in an RM 65
Single Board Computer (SBC) module for runtime operation.
The developed program will run with RM 65 Run-Time FORTH
ROMs installed in the RM 65 SBC module. In this configuration,
all RM 65 input/output operations must be user-provided and
can be tested using the AIM 65 Microcomputer as the host computer prior to being installed in the RM 65 environment.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ORDERING INFORMATION
AIM 65 Microcomputer host and target
ROM resident for immediate operation
Application oriented
Extensible language
Over 200 pre-defined functions
Interactive compilation
Reverse polish notation
Compact memory usage
Fast execution
Easy debugging
Stack implementation
16-bit words
Built-in structured macro assembler
Shortens software development time
Part No.
A65-050
A65-040
RM65-0152
Description
AIM 65 FORTH ROMs
AIM 65 Math Package ROM
RM 65 Run-Time FORTH ROM
Order No.
265
283
2118
812
Description
AIM 65 FORTH User's Manual'"
AIM 65 FORTH Reference Card'" "
AIM 65 Math Package User's Manual'"
RM 65 Run-Time FORTH User's Manual'"
NOTES:
1. Included with A65-050.
2. Included with A65-040.
3. Included with RM65-0152.
Document No. 29000087
7-28
Data Sheet Order No. 087
Rev. 1, March 1983
AIM 65 FORTH ROMs
A6S·0S0
DEVELOPING FORTH PROGRAMS
FORTH is built on subroutine-like functions, called '.;iNords>'
These words are linked together to form a "dictionary," which
is t/:le central core of the language. Writing a program in
FORTH consists of using several predefined words to define
each new word. Once the new word has been added to the
system dictionary, it becomes as much a part of the language
as any other word .~hat hlili been previously defined. In this
way new features and extensions can be added by simply
defining one or more new words. Adding new features to
conventional languages like BASIC or Pascal requires the
language system to be completely reassembled or
recompiled.
FORTH is a stack-oriented language, and is programmed in
Reverse Polish Notation (RPM), the notation that is used in
Hewlett-Packard scientificcaklulators. Using a data stack is
an extremely efficient way of passing variables back and
forth between operations. A clata stack eliminates the need
to tie up memory locations with variable tables, and allows
you to use only as much'memory as you need.
FORTH programs are developed using "top-down/bottomup" techniques. That is, the programmer begins by defining
the program in very general terms, then systematically breaks
these definiflOns down into more and more detailed submodules. When the lowest levels of sub-modules have been
defined, he starts coding, iM FORTH, at those levels, working
back up toward the top althe program, in pyramid fashion:
Each sub-module is a stand-alone component of the program, anq can be completely debugged without having the
complete program in the' system. This type of software
development is difficult,if not impossible, to do with mQst
other high-level languages.
FORTH WORDS
STACK MANIPULATION
DUP
2DUP
DROP
2DROP
SWAP
OVER
ROT
- DUP
>R
R>
R
PICK
SP@
RP@
BOUNDS
.S
Duplicate top of stack.
Duplicate top two stack nems.
Delete top of stack.
Delete top two stack nems.
Exchange top ·twostack nems.
Copy second item to top.
Rotate third item on top.
Duplicate only if non-zero
Move top nem to return stack.
Retrieve Hem from return stack.
Copy top of return "Slack onto stack.
Copy the nth item to top.
Return address of stack posHion
Return address of return stack pointer.
Convert" address count" to "endaddress start-address."
Print contents of Slack.
DEFINING WORDS
:
VARIABLE
CONSTANT
CODE
;CODE
USER
Begin colon definition of .
End colon definnion.
Create a variable wnh innial
value n; returns address whan
executed.
Create a constant wtth value
n; returns, valua, when executed.
Begin defiMnion o.t assembly-language
primitive operetlon .
Used to create a new. defining word,
with executipn-time "code routine" for
this data type in assembly.
Used to create a new defining word,
wtth execution-time: routine for this
data type in higher-level FORTH.
Create a user variable.
FLOATING POINT FUt,tCTIONS
AIM 65 FORTH COAtains both a single- (16-bit) and double(32-bit) preCision integer arithmetic capability. In AIM 65
applications where floating point arithmetic is desired, the
AIM 65 Math Package may be used in conjunction .with the
FORTH ROMs. These floatirigpolnt functions may be called
USing FOFiTH words included iM. the math package ROM.
When this ROM, is install.ed in socket Z24 on the .AIM 65
Microcomputer•. the floating. point. math words can be automatically linked to the FORTH dictionary during FORTH
initialization. The AIM 65 Math Package ROM can alSO be
installed in either an RM 65 sec or PROM/ROM module.
MEMORY
@
C@
CI
?
+1
CMOVE
FILL
ERASE
BLANKS
TOGGLE
MEMORY MAP
Fetch value addressed by top of stack.
Store. nl at address n2.
Fetc!) one byte only.
.Store 'one byte only.
Print contents of adc;lress.
Add second number on stack to
contents of addr:ess on ,top.
Moven3bytes starting at address n1 to
area startirig at address n2.
Put byte n3 into n2 bytes starting at
address nl"
Fill n2 bytes In memory with teroes,
beginning at address nl.
Fill n2 bytes in mel)1ory with blanks,
beginning at address nl.
Mask memory wnh bit pattern.
NUMERIC REPRESENTATION
Address (Hex)
$DOOO-$DFFF
$BOdo-$CFFF
$28O-$2FF
$25C-$27F
$2QO-$257
$AB-$C4
$10-$AA
Content.
Math Package Program
FORTH Program
Terminal Input Buffer
Math Package Variables
FORTH User Variables
Math Package Variables
FORTH Variables
DECIMAL
HEX
BASE
DIGIT
o
1
2
3
Set decimal base.
Set hexadecimal base.
Set number base.
Convert ASCII to binary.
The number zero.
The number one.
The number two.
The number three.
I
A65.050
AIM 65 FORTH ROMs
FORTH WORDS (CONT'D)
ARITHMETIC AND LOGICAL
CONTROL STRUCTURES
+
DO •.. LOOP
DO •.. ' +LOOP
D+
I
MOD
IMOD
·/MOD
·1
U·
UI
M"
MI
MlMOD
MAX
MIN
+ '-
0+ABS
DABS
NEGATE
DNEGATE
S- >0
1+
2t
1-
2AND
OR
XOR
Add.
Add doubl!!-precision numbers.
Subtract (nl - n2)
Multiply:
Divide (nl/n2).
Modulo (i.e., remainder from division).
Divide, giving remainder and quotienl.
Multiply, then divide (nl·n2/n3), with
double intermediate.
Like ./MOD, but give 'quotient only,
Unsigned multiply leaving double
jlroduct.
Unsigned divide.
Signed multiplication leaving double
product.
Signed remainder and quotient from
double dividend.'
Unsigned divide leaving double quoti!!nt
and remainder from double dividend
and single divisor.
Maximum.
Minimum.
Set sign.
Set sign of double-precision number.
Absolute value.
Absolute value of double-precision
nun1ber: '
.
I
LEAVE
BEGIN ... UNTIL
BEGIN ... WHILE
... REPEAT
BEGIN ... AGAIN
IF ... THEN
IF ... ELSE .' .• THEN
If top 01 slack true, execute ELSE
END
END IF
clause THEN continue; otherwise
e,xacutefollowing clause, THEN
continue.
Alias for UNTIL.
Alias for THEN.
COMPILER·TEXT INTER!,RETER
[COMPILE]
COMPILE
Change sign.
change sign of double-precision
, number:
Sign extend to double-precision
number.
Increment value on top of stack by I.
Increment value on top of stack by 2.
Decremerit value on top of stack by I.
Decrament value on top of stack by 2.
Logical AND (bitwise).
Logical OR (bitwise)
Logical exclusive OR (bitwise).
LITERAL
DLiTERAL
EXECUTE
[
]
CREATE
FORGET
HERE
0<
O~
U<
NOT
ALLOT
True if nl less than n2.
True if nl greater than n2.
True if top two numbers are equal.
'True if top number negative.
True If top number zero.
True if ul less than u2.
Same as O~.
TASK
- FIND
DP
<•.
C,
MISCELLANEOUS AND SYSTEM
«comment»
CFA
NFA
PFA
LFA
LIMIT
QUIT
ForCe compiiaiionoflMMEDIATE word.
Compile following into
dictionary .
Compile a number into a literal.,
,
Compile a double-precision number into
a literal.
Execute the definition on top of stack.
Suspend compilation, enter execution.
Resume compilation.
DICTIONARY CONTROL
COMPARISON OPERATORS
<
>
Set up loop, given index rang!!.
Like DO ... LOOP, but adds stack
value to index.
Place current index value on stack.
Terminate loop at next LOOP or
+ LOOP.
Loop back to BEGIN until true at
ONTll.
Loop while true at WHILE, REPEAT
loops unconditionally to BEGIN,
Unconditional loop.
If top of slack true, execute following
clause THEN continue; otherwise
continue ,at THEN.
PAD
IMMEDIATE
INTERPRET
Begin comment (terminate by right
parentheses on same line).
Alter PFA to CFA.
A~er PFA to NFA.
A~er NFA to PFA.
Alter PFA to LFA.
Top of memory.
Clear return stack and return to
terminal.
LATEST
LIT
CLiT
LITERAL
SMUDGE
STATE
7·30
Create a dictionary header.
FORGET all definitions from
on.
RetUrns address of next unused byte in
the dictionary.
Leave a gap of n bytes in the
dictionary.
A dictionary marker.
Find the address of in the
dictionary .
Search dictionary for .
User vari,able containing the dictionary
pointer.
Store byte into dictionary.
Compile a number into the dictionary.
Pointer to temporary buff!!r.
Force execution when compiling.
The Text Interpreter executes or
compiles.
Leave name field address (NFA) of top
word in CURRENT.
Place 16-bit literal on the stack.
Place byte literal on the stack.
Compile a 16-bit literal.
Toggle, name SMUDGE bit.
U$9r variable containing compilation
state.
AIM 65 FORTH ROMs
FORTH WORDS (CONT' D)
OUTPUT FORMATTING (CONT'D)
Convert next dlgft of double-precision
, ',number and add character to output
string,
Convert all significant dlgfts of doublaprecision number to output string.
Insert sign of n into output string.
Terminate output string (ready for
USER VARIABLES
MONITOR
#S
User variable for ABORT.
User variable for BlBUF.
USer variable 'for BlSCR.
User, varlabk! for c/L
User variable for EMIT.
User variable for FIRST.
User variable for KEY.
User variable for LIMIT.
UABORT
US/BUF
Us/SCR
Uc/L
UEMIT
UFIRST
UKEY
ULIMIT
SIGN
#>
TYPE).'
HOLD
HDL
-TRAILING
.L1NE
COUNT
a CASSmE I/O
COLD
MON
?TTY
CHAIN
CLOSE
?IN
?OUT
GET •
PUT
READ
WRITE
SOURCE
FINIS
form.
AIM 65 FORTH cold start.
ex~ to AIM 65 MonRor.
SW~h; true = TTY; false = KB
Chain tape file.
Close tape file.
Set to active input device (AID).
Set to active output device (AOD).
Input a character from the AID.
Output a character to the AOD.
Input n2 characters from AID to
address nl.
Output n2 char8.cters to AOD at
address nl'.
Compile from the AID.
Terminate complete from SOURCE.
DUMP
TYPE
?TERMINAL
KEY
EMIT
EXPECT
WORD
D.
D.R
DPL
VOCABULARIES
CONTEXT
Returns address of pointer to
CONTEXT vocabulary.
CURRENT
Returns address of pointer to
CURRENT vocabulary.
FORTH
Main FORTH vocabulary.
ASSEMBLER
Assembler voc/l.bulary.
DEFINITIONS
Set CURRENT vocabulary to
CONTEXT..
VOCABULARY Create new VOcabulary.
VLlST
Print nalTMils of all words in CONTEXT
vodabulary .
VOC-L1NK
Most recently d!1fined vocabulary.
Output CR to printer only.
Carriage return.
Type one space.
Type n spaces.
Outpui a CTRL B.
Print text string (terminated by ").
'Dump n2 words starting at address.
Type string ,of nl characters starting at
address n2.
.
True if terminal break request present.
Read key, put ASCII value on stack.
Output ASCII value from' stack.
"Read nl characters from input to
address n2.
Reile! one Wllrd from input stream, until
\
VIRTUAL STORAGE
LOAD
BLOCK
BlBUF
BlSCR
BLK
SCR
delim~er.
IN
BAUD
BL
c/L
TIS
QUERY
10.
HANG
User variable contained wfthin TIB.
Set BAUD rate.
Output a SPACE character.
Number of char8.cterslline.
Pointer to terminal input bu",r start
address.
Input text from terminal.
Print "'l\1arne> from name # field
address (nfa).
Wail for keystroke.
UPDATE
FLUSH
EMPTY-BUFFERS
+BUF
BUFFER
RW
USE
PREV
FIRST
OFFSET
OUTPUT FORMATTING
NUMBER
<#
Print number on top .of !IItack.
Prinl number nl right Justified n2
places.
Print double-precision number n2 n2.
Printdouble-precisloil number n2 n1
right jUstified' n3 places.
Number of digits to the right of decimal
point.
.F!
INPUT-OUTPUT
oCR
CR
SPACE
SPACES
CLRLINE
Insert ASCII character Into output
string.
Hold pointer, user variable.
Suppress trailing blanks.
Display line of text from maas storagll.
Change length of byte string to type
Convert string at address to doubleprecision number.
Start output string.
-->
;S
7-,31
Load mass storage screen (compile or
execute).
Read mass storage block to memory
address.
System constant lIivinQ maas storage
block size In bytes.
Number of bioCksieditillg screen.
System variable,containing current
block number.
System variable containing current
screen number.
Mark last buffer accessed as updated.
Write all updated buffers to mass
storage.,:,
Erase all buffers.
looremellt buffer address.
"Fetch next (TIemory buffer.
User' ",ad write 'linkage.
Vari~ble containing address of next
puffer.
Variable containing address of latest
buffer.
Leaves address of first block buffer.
User variable block offset to mass
storage.
Interpret next screen. "
Stop interpretation.
A65-050
AIM 65 FORTH ROMs
FORTH WORDS (CONT'D)
PRIMITIVES
OBRANCH
BRANCH
ENCLOSE
Ro
SO
RP!
SP!
NEXT
SECURITY
Run-time conditional branch.
Run-time unconditional branch.
Text scanning primitive used by WORD.
location of Return Stack.
location of Parameter Stack.
Initialize Return Stack.
Initialize Parameter Stack.
The FORTH virtual machine.
'CSP
?COMP
?CSP
?ERROR
?EXEC
?PAIRS
?STACK
ABORT
ERROR
MESSAGE
WARNING
FENCE
WIDTH
Store stack position in check stack
pointer.
Error if not compiling.
Check stack position.
.Output error message.
Not executing error.
Conditional not paired error.
Stack out of bounds error.
Errc;>r; operation terminates.
Execute error notification and restart
system.
Displays message.
Pointer to message routine.
Prevents forgetting below this point.
Controls significant characters of
.
MATH PACKAGE FORTH WORDS (A6~-040)*
FLOATING POINT ARITHMETIC
USER VARIABLE
F+
F-
MIN-WIDTH
p
FI
Adds two floating point i1umbers.
Subtracts one floating point number
from another floating point number.
Multiplies two floating point numbers.
Divides one floating point number by
another floating point number.
DEC-LENGTH
. Specifies the minimum field width to be
.output.
Specifies the number of places to the
right of the decimal point to be
output.
ASCIl/FLOATING POINT CONVERSIONS
UTILITY, SIGN AND COMPARISONS
FABS
INT
SGN
FSIGN
FCOMP
FIN
Takes the absolute value of a floating
point number:
Truncates a floating point number to an
integer.
Converts the sign of a floating point
number to a floating point number.
Gets a value corresponding to the sign
of a floating point number.
Compares the value of a compacted
number in memory to a floating point
number.
FOllT
FORMAT CONVERSION AND DATA MOVING
M>F
F>M
M>A
POLYNOMIAL
POLY
POLYODD
Converts a number in memory from
ASCII to floating point format.
Converts a number from floating point
to ASCII.
S>A
Evaluates a polynomial with
consecutive exponents.
Evaluates a polynomial with odd
exponents.
S>F
F>S
Unpacks the compacted number in
memory to floating point.
Packs the floating point number to
compacted format and stores the
result i'n memory.
Unpacks the floating point number in
memory.
Converts an integer to floating point
format.
Converts an integer to floating point
format.
Converts a number from floating point
to an integer.
EXPONENTIAL AND LOGARITHMIC
SQR
>
EXP
LOG
LN
TRIGONOMETRIC AND UNITS CONVERSION
Takes the square root of a floating point
number.
Raises one floating point number to the
power of another floating point
number.
Raises the transcendental number e to
the power of a floating point number.
Computes the logarithm to the base 10
(I.e., common log) of a floating point
number.
Computes the logarithm to the base e
(I.e., natural log) of a floating point
number.
SIN
COS
TAN
ARCTAN
DEGREES
RADIANS
'Requires AIM 65 FORTH or RM 65 FORTH be resident.
7-32
Calculates the sine of a floating point
number (in radians).
Calculates the cosine of a floating point
number (in radians).
Calculates the tangent of a floating
point number (In radians).
CalCUlates the arc tangent of a floating
point number.
Converts a floating point number from
radians to degrees.
Converts a floating point number from
degrees to radians.
A65·052
AIM 65 Microcomputer Family
'1'
Rockwell
A65-052
AIM 65 FORTH TARGET COMPILER
FORTH LANGUAGE
FEATURES
FORTH is a unique programming language well suited to a
variety of applications. Originally developed for real-time control
applications, FORTH has features that make it ideal for machine
and process control, energy management, data acquisition,
automatic testing, robotics and other input/output intensive
applications where assembly language was previously considered to be the only possible language choice.
• Fully compatible with FORTH programs developed with AIM
65 or AIM 65/40 FORTH Interpreter ROMs
• Disk-based compiler operation with vocabulary overlays for
-Text Editing
-Disk InterfaCing
-Serial Input/Output
-Compiling
-Special Utilities
FORTH actually provides the best of two worlds. It has the
looping and branching constructs of high-level languages (DO
... LOOP, BEGIN ... END, IF ... THEN and IF ... ELSE
... THEN) and the code efficiency of machine and assembly
languages. FORTH allows programmers to specify addresses,
operands and data in hexadecimal, octal, binary or any other
number base from two to 4O-a distinct advantage over languages like BASIC, where all information must be in decimal.
• Easy compiler operation
-Load screen direction
-Compile tracing (mapping)
-Compiles to RAM and/or disk
• Includes 6502 Macro Assembler with
-Forward references
-Symbolic labels
-Relative branches
FORTH TARGET COMPILER
• Efficient object code generation
- ROMabie object code
-Standalone operation
-Minimum runtime. nucleus
-Optimized FORTH compiled vocabulary
The FORTH Target Compiler generates object code from
application programs written in FORTH. The object code is a
compiled composite of the user's application vocabulary. and
those portions 01 the Target Compiler nucleus necessary to support the application vocabulary. The disk-based FORTH Target
Compiler operates on the AIM 65 Microcomputer in conjunction
with.the AIM 65 FORTH Interpreter ROMs, the AM 65 Floppy
Disk Controller (FDC) module and the AIM 65 DOS 1.0 firmware.
-AIM 65 autostart capability
-User-specified origin
• Flexible target computer installation
-System independent (runs on any 6502 CPU-based system
with minimal runtime memory map requirements)
The compiled object code, located at a user-specified origin with
optional auto-start vectors, will execute in any 6502 CPU-based
microcomputer system supporting the runtime nucleus memory
map requirements. Application programs can also be developed
to run on AIM 65 or RM 65 SBC module-based systems with
supporting RM 65 memory and input/output modules, e.g.,
Analog Input/Output, IEEE-488 Interface, and Multi-function
Peripheral Interface Linkage to RM 65 Floppy Disk Controller,
CRT Controller, and IEEE-488 module as well as the AIM 65
Math Package; firmwlj.re can also be .included for expanded
application systems.
ORDERING INFORMATION
Part No.
AIM
AIM
AIM
AIM
65-052
65-050
65-090
65-040
Order No.
2105
265
2116
Description
AIM
AIM
AIM
AIM
65 FORTH Target Compiler
65 FORTH Interpreter ROMs")
65 DOS 1.0 ROM","
65/40 Math Package ROM(6)
Description
AIM 65 and AIM 65/40 FORTH Target
Compiler User's Manual(3)
AIM 65 FORTH User's Manual")
AIM 65 Math Package User's Manual'"
Notes:
(1) Required for FORTH Target Compiler operation.
(2) Requires RM65-5101NE FOC module.
(3) Included with A65-052.
(4) Included with A65-050.
(5) Included with A65-040.
(6) Optional.
Document No. 29001011
7-33
Data Sheet Order No. 0111
March 1983
II
.
AIM 65 FORTH Target Compiler
A65-052
DEVELOPING FORTH PROGRAMS
FORTH TARGET COMPILER OPERATION
FORTH is built on subroutine-like functions,. called "words."
These words are linked together to form a "dictionary," which
is the central core of the lallguage. Writing a progr?m in FORrH
consists of using the dictionary words to define each new word.
Once the new word has been defined it is added to the system
dictionary and it becomes as much a part of the language as
any other word that has been previously defined. In this way
new features and extensions can be added py simply defining
one or more new words.
.
The disk-based, two-pass, FORTH Target Compiler compiles object code in one of twO. modes: BIG.COMPILE pr
QUICKCOMPILE. The QUICK:COMPILE mode compiles the
entire object code directly to RAM then saves the compile~ code
on disk. The BIG.COMPILE mode compiles to 1K-byte buffer
areas in RAM. When the buffer is f~lI, the buffer contents
are transferred to disk then compilation continues. The
BIG.COMPILE mode optimizes object code RAM requirements
although it compiles slower than the QUICKCOMPILE mode.
FORTH is a stack-oriented language, and is programmed in
Reverse Polish Notation (RPN), the notation that is used in
Hewlett-Packard scientific calculators. A data stack is an
extremely efficient way of passing variables back and forth
between operations and eliminates the need to"lie up memory
locations with variable tables.
Operation of the compiler is directed by one or more LOAQ
SCREENS. This technique provides the user with complete
control of compiler vi3riables, origin statements, cold start vectors and utility routines. The LOAD-SCREEN(s) then specify
which user screens to compile and in what order.
FLOATING POINT OPERATION
FORTH programs are developed using "top-downlbottom-up"
techniques. That is, the programmer begins by defining the program in very general terms, then systematically breaks these
definitions down into more and more detailed submodules. When
the lowest levels of sub-modules have been defined, FORTH
coding begins at those .levels, working back up toward the top
of the program, in pyramid fashion. Each sub-module is a stand,
alone component of the program, and can be debugged without
having the complete program in the system. The interactive
nature of FORTH supports this time efficient development
technique.
The FORTH Target Compiler provides both single-precision
(16-bit) and double-precision (32-bit) single integer arithmetic
functions. If floating point arithmetic is desired, code words can
easily be defined within. the application program to link to external
floating point subroutines. The' AIM 65 Math. Package ROM,
located at address $8000"$8FFF, can be installed in the application system. Alternatively, user-defined floating point' functions may be linked to or even provided within the code
definitions.
SYSTEM REQUIREMENTS
In most time-critical applications, at least part of the program
must be written in assembly languages. FORTH has a built-in
6502 macro assembler, and allows assembly language coding
at almost any point in your program, without separate assembly
and load steps or special machine level linkage. FORTH programs typically run up to ten times faster than other interpretive
languages, and can even approach the speed of machine language programs for some applications.
The AIM 65'FORTH Target Compiler operates in an AIM 65
Microcomputer in conjunction with an RM 65 32K Dynamic RAM
module and an RM 65 FDC module with an AIM 65 DOS 1.0
ROM installed on the FDC module. The following table lists two
configurations of AIM 65/40 and RM 65 hardware and firmware
which may be' used. Other configurations can be easily composed depending on the user's development and application
requirements.
The applicatiqn program is developed, debugged and integrated
with the user interface using the ROM-based FORTH Interpreter. After program validation, the application is compiled into
stand-alone object code with only required portions of the Target
Nucleus. The compiled byte count will generally be less than
the separate application/interpreter byte count.
Host Computer
Required
Peripherals
Firmware
f
RM65-7104E RM 65 Adapter/Buffer for AIM 65, or
RM65-7116E RM 65 Cable Adapter/Buffer for AIM 65
RM65-7004E RM 65 4-Slot Card Cage
RM65-3132E RM 65 32K Dynamic RAM Module
RM65-51 01 NE RM 65 Floppy Disk Controller (FDC) Module (without ROM)
A65-090 AIM 65 DOS 1.0 ROM
A65-050 AIM 65 FORTH ROMs
A65-040 AIM 65 Math Package ROM
Note:
~ Required in addition to host computer.
1. Included in host computer.
2. Remote to AIM 65 enclosure.
X
7-34
A65-450
AIM 65 Microcomputer
with 4K RAM
and FORTH ROMs
A65-550
AIM 65 Microcomputer
System with 4K RAM
and FORTH ROMs
X
X
X
X
X
X
(1)
Optional
X(2)
X
X
X
(1)
Optional
AIM6S FORTH Target Compiler
A6S-0S2
FORTH WORDS (Continued)
STRING ORIENTED COMMANDS
EDITOR VOCABULARY OVERLAY
o
Finds the text, deletes it and shows the line.
F
Finds the text, positions the cursor at the end
of the text string and shows the line.
BUFFERS
INSERT-BUF
An aD-byte buffer beginning at PAD
F1ND,BUF
An
a~-byte
buffer beginning at PAD
+ aD.
+
Inserts the contents of INSERT-BUF into line.
160.
MATCH
Searches. the memory space beginning at
ADDR2 for CNT2 for a match of the data
beginning at ADDRI for CNTI. If no match is
found, sets f",,1 and ADDR3=ADDRI +
CNTI. If a match is found, sets f =0 and
ADDR3 =address of the next byte after the
matching string.
(F)
Locates the text in the buffer.
#LAG
Returns the address of the character following
the cursor and then counts to the line end.
#LEAD
Returns the address of the character
preceding the cursor and the count to the
beginning of the line.
LINE ORIENTED COMMAN.DS:
K
Swaps the contents of the INSERT-BUF and
FIND-BUF.
LINE
On current screen, returns the RAM address
of the beginning of the line#.
M
Replaces INSERT-BUF and line# in block#
with current referenced line.
NEW
'Beginning at line#, clears each line and
allows a NEW line to be typed in. Input is
terminated by a null line entry (CR CR).
Clears remaining lines on the current screen.
P
Copies text into the INSERT-BUF and the
current line until the delimiter (CR) is
encountered.
TILL
SCREEN COMMANDS
Beginning at the current cursor address,
deletes text unTILL the end of the matching
text string is encountered. The text is held in
FIND-BUF.
T
Mov~s cursor to beginning of line# in current
screen. Shows the line.
U
Copies text into the INSERT-BUF and the line
on the current screen under the cursor.
x
Copies the current line into INSERT-BUF.
Then deletes the line and scrolls the screen
up. The last line becomes a blank.
>L1NE#
Returns the current cursor line #.
(DELETE)
Referring to the current cursor position,
deletes n preceding characters and calls
UPDATE.
(HOLD)
Copies the referenced line number into
INSERT-BUF and UPDATE.
B
Moves to last btock.
L
Lists current screen.
N
Moves to next block.
TOP
Moves cursor to the top line of the text.
WIPE
Clears the entire screen.
MISCELLANEOUS COMMANDS
BUF-MOVE
Move non-nUll contents of pAD to ADDR.
E
Erases the string in front of the cursor for a
length equal to the string in FIND-BUFF.
R
Replaces string identified by FIND-BUFF with
TEXT.
S
Beginning at current screen and continuing
through screen #n, searches for a string
match to TEXT and displays matches.
CURSOR COMMANDS
R#
Retums the cursor position (n).
(KILL)
Blanks line# and UPDATE.
#LOCATE
Returns byte posijion of cursor and line
number.
(PUT)
Replaces the current line with contents of
INSERT-BUF.
»
Adds n to cursor posijion and displays line.
TEXT
Takes text from input stream until DL.IMiter
character is encountered (65 characters
maximum). Moves text to PAD and fills to 6&
characters wijh blanks ($20).
USE
Displays CHAR as the cursor.
WHERE
Displays where an error in LOADing occurred.
Also shows context and c.urrent.
?
Prints the current line with the cursor at
current cursor position and the line number at
the end of the line.
1LINE
Searches the current line after cursor position
for a match to contents 01 FIND-BUF.
Repositions cursor to it il a match is found and
sets f=l. II no match is found, sets 1=0 and
positions the cursor to the next line.
7-35
A65-052
AIM 65 FORTH Target Compiler
FORTH WORDS
GENERAL PURPOSE VOCABULARY
The following FORTH words are provided in addition to those
provided in the A65-050 FORTH Interpreter ROMs (refer to Data
Sheet Order No. 087).
ABORT"
Prints TEXT if a run-time error occurs.
ASCII
During compile time. places a CLiT and the
literal value of CHAR in the dictionary. In
immediate mode, returns the ASCII value on
the stack.
YIN?
Asks the question YES? or NO?, depending
on f, = 1 or O. Returns f, as true or false
depending on input match to f,.
2ROT
Rotates double-precision numbers d" d" d,.
2"
Returns d, = d, " d,.
Combines low byte of I and high byte of h to
form n.
20VER
Double-precision OVER.
COMPILING
Activates the Compiler Vocabulary Overlay.
2SWAP
Double-precision'SWAP.
DISKING
Activates the Disk Vocabulary Overlay.
EDITOR
Activates the Editor Overlay.
EXTERNAL
Execution only. NFA of next word to be
defined.
FALSE
Returns a false flag.
H.
Prints n as an unsigned hexadecimal value.
HI
Returns the high byte of n.
IFEND
Marks a place.
IFTRUE
Compiles the following input if f=l. otherwise
skips.
INTERNAL
Returns the NFA of the latest word defined.
LO
Returns the low byte of n.
LOADER
COMBINE
Execution only. Creates a constant NAME with
value, n.
-TEXT
Compares strings at APDRl and ADDR2 for n
bytes. Returns f=l if same.
?DEF
IF NAME is defined, returns f=l.
?RANGE
Returns f=l if n2ESTINATION
Defines the target buffer' block numblir.
;CODE
identical to CODE but also sete,a pointer for
LOCATE.
'
RAM.LO }
RAM.HI
'
Identifies nUcleus RAM bpundarles. E;xte~cjs
from RAM.LO for USER,S,IZE bytes.
LOCATE
Informs the.compiler where
CODE Is Iqpated.
USER.SIZE
Number of bytes reserved beginning at
RAM.LO. RAM between RAM.LO +'
USER.SIZE I!nd RAM.HI ,is Used for wor:!<
buffers (PAD, etc.) when ,ROMABLE flag Is
set.
'
CONTROL WORDS
OLiTERAL
'ASCII
ORIGIN
FAST.COMPILE
',. Compiler's target dictionary.
' Target space will be RAM only, based on
~INDOW.LO and WINOoW.HI.
BIG.COMpILE
Target spacemavbe' )lirtual
disk.
6LEAR.TARGET
FiIIs,the target
d~ta space on
areawlthz~ros.· "
D6~'s>
Compiles a double number in line.
compilesQ,LlT of foilowing
AScI! character.
Immediate ,Word to',separate into TARGET·l\iUCLE.uS and larget
Complier.
..,'
the ellecution time
REVEAL
~imll~r to ,SMUDGE.
HIDE
Sets the SMUDGE bit on the. last tarqet word.
ASS-OSO
AIM 65 Microcomputer Family
'1'
Rockwell
A6S-060
AIM 65 INSTANT PASCAL ROMS
PASCAL LANGUAGE
FEATURES
Pascal. is a powerful high-level computer programming language originally designed for educational purposes. Developed
by Niklaus Wirth of the ETH Technical Institute of Zurich in 1971,
Pascal has gained acceptance worldwide as the standard language to teach computer programming. The rich variety of
Pascal language features allows a wide range of data structures
to be specified and complex algorithms to be implemented. Programming in Pascal USing structured progr.amming techniques
produces programs that are easy to write, understand and maintain. The widespread teaching of the language coupled with the
increased productivity of the programmer and the improved
reliability of compiler generated code is causing Pascal to be
increasingly adopted in industrial and scientific applications as
well as in the classroom.
•
•
•
•
•
•
AIM 65 Microcomputer host and target
Substantial subset of Standard Pascal (Jensen and Wirth)
ROM resident for immediate operation
Direct control of memory mapped I/O
Machine language interface linkage
Source code editor
-Position text pointer
- Find character string
-List, delete, insert statement
- View statement
• Flexible program control
-Check syntax for coding errors without executing program
-Execute one statement to allow examination and
modification of data
-Execute entire program
• Source level debugging facilities
-Breakpoint
-Assignment trace lists va.lues as they are changed
- Statement trace lists statements as they are executed
PRODUCT OVERVIEW
AIM 65 Instant Pascal™ is a unique implementation of the
Pascal language which combines the immediacy of ROM-based
software, interactive source code entry and debug facilities, onboard AIM 65 printer and display peripherals and low-cost
expansion memory, to provide a complete Pascal education,
development and application system. The language is a major
subset of Standard Pascal (defined by K. Jensen and N. Wirth
in their book, .. Pascal User Manual and Report") incorporating
all of the simple and structured statements, and the most widely
used simple and structured data types. Extensions to the language permit direct control in Pascal of the AIM 65 Microcomputer memory-mapped I/O and allow interfacing to machinelanguage programs developed with the AIM 65 Assembler.
• Device Source VO
-Input source code from specified device
-Output source code to specified device
MEMORY MAP
Address .(Hex)
$BOOO-$BFFF
$4000~$7FFF
$FC3-$FFF
$ED2-$FC2
$300 up
$FC-$FF
$06-$B4
Instant Pascal incorporates facilities to write and debug programs entirely at the source language level. These facilities
include source-level editor, breakpoint, and trace-plus immediate source statement execution for examination and modification of data. Source statements are translated immediately
upon entry into an intermediate language which is interpretively
.
executed.
Contents
Pascal Program
Pascal Program
Translator input area (default value)
Translator output area (default value)
Execution stack (default value)
Pascal Variables
Pascal Variables
ORDERING INFORMATION
The 20K-byte AIM 65 Instant Pascal software comes in a fiveROM set. One ROM plugs into AIM 65 Master Module socket
Z24 while the other four ROMs plug into an RM 65 16K-byte
PROM/ROM (RM65-3216E) module.
Part No.
A65-060
Description
AIM 65 Instant Pascal ROMs
Order No.
279
TMlnstant Pascal is a trademark of Melvin E. Conway.
Description
AIM 65 Instant Pascal User's Manual"
Note:
"Included with A65-060.
Document No. 29001007
7-38
Data Sheet Order No. 0107
MarCh 1983
65..060,·
AIM 65 Instant Pascal· ROMs
STANT PASCAL EXTENSIONS TO STANDARD PASCAL
Variables, .both simple and structured, maY,be given absolute memory addresses. This permits Pasqal programming of memorymapped ,I/O and linkage to machine-language subroutines.
The OTHERWISE: default clause is implemented in the CASE statement., Identifiers may have any length; the, entire identifier is
significant.
,
,
Data of type STRING may have lengths which vary dynamically up to the declared maXimumleng~h. The type ~:SmING[C] is
implemented as S:ARRAy[O' .. C] OF CHAR, where S[O] is the value of the dynamic length. (C is a constant',less than'256.)
The predefined procedure BREAK causes interruption of program execution, if it is enabled.
.
The predefined procedure SUBR(ENTRANCE) calls the machine-language subroutine whose entrance address is the declared
address of the absolute variable ENTRANCE. TlJe variant SUBR(ENTRANCE, DATA) places the a~dress of the Pascal variable DATA
in page 0 before giving control to the subroutine.
.
The Predefined functions FUNC(ENTRANCE) and FUNC(ENTRANCE, DATA) are the same as SUBR; in addition they retum a CHARtype value which the subroutine leaves in A.
TANDARD PASCAL FEATURES NOT IMPLEMENTED IN INSTANT PASCAL
Files and their associated predefined procedures and variables (GET, PUT, RESET, REWRITE, EOLN, EOF) are not implemented.
The predefined procedures READ, READLN, WRITE, WRITELN are implemented to interface with all character-serial devices available to the AIM 65 Monitor, including user-defined devices. The following types may be read and written: char, integer,real, Boolean
(Y or N on input), variable-length string.
Set expressions are not implemented. One-byte sets (with up to eight elements) and the relational operator IN are implemented; these
permit Pascal-level testing of VO device status.
Records are implemented, but record variants are not.
Dynamic storage allocation and the pointer type are not implemented.
-The directive FORWARD is not implemented.
-The constant definition identifier=identifier; is not implemented.
-Ambiguity between field and variable names at the same block level is not supported. Other Pascal visibility rules are fully supported:
-Packing of data is not done below the byte level. The word-symbol PACKED is acceptedbutignored, and the predefined procedures
PACK and UNPACK are not implemented.
-Procedural and functional parameters to procedures and functions are not implemented.
-GOTO may not jump outside its own block.
-'-The 60-character input line of the AIM 65 limits the length of cerlain constructs, in particular simple statements, .procedure/function::
lists, which may not be extended during input from one line to the next.
.
headings, and enumerated
type
AIM 65 Instant Pascal ROM
A65-060
MEMORY EXPANSION
CONSIDERATIONS"
OPERATION OF INSTANT PASCAL
All operations in the Instant Pascal system are controlled by'
ase! of single-letter commands. The system generally performs one of the following six major operations.
About 1.,5 bYtes per character of source code is required t
store an application program written in Pascal in memory du
to the translation process. For, minimum applications requirin
less than 3.2K bytes of on'board user RAM, the PROM/RO
module can be connected to the AIM 65 Expansion ,Con
, nector using an RM ,65 Single Card Adapter. For large
applications, connection of an RM 65 multi-slot Card cag
through an RM 65 A(japter/Buffer module is recor:nmended
One or' more RM 65 RAM modules can then' be added a
required. Up to 15.2K bytesof contiguous RAM can be ded
icated to the application program.
1. Source input from keyboard or input device.
2. Source output to printer or output device.
3. Program editing: pos~ioning the text unit pointer or deleting
text units. '
4. Syntax checking a program. This operation is called
aujomatically at the first call to execute a program after
any change. Ilmay also be called explicitly.
S. ExeclJting a program.
6. Executing a single statement entered by the user.
All commands are preceded by the Instant Pascal prompt
"+ <." The numeric parameter n in some of the commands
has either a decimal value or one of the following two default
values: "." =forever; CR= 1.
INSTANT PASCAL OPERATION COMMANDS
Text Unit Pointer Movement
+
Position to lop text unit.
+
+/n
Position to bottom text unit.
Position up n text units.
+/n
+string
Position down n text units.
Find the line containing the argument string.
Source Text Editing
+/n
Delete n text units.
+<1>
+< >space
Insert one line of source.
List current text unit.
+
View a neighborhood of five text units centered at the current,one.
Device Source I/O "
+IN=device
+/nOUT=device
Read lines of source until emptY line.
List n text units to the specified device.
Toggles
+
+
+
Toggle statement trace.
Toggle assignment trace.
Toggle enabling of the BREAK procedure.
Program Control
+
+
+<,>
+statement
Check program syntax.
Execute program. Starts at beginning of program unless a break is in progress. Break-in-progress status
may be cancelled with the C command or by changing the program.
Execute and trace until the start of the next statement and return with break-in-progress status set.
Immediately execute the statement. Identifier visibility is defined by the position of the text unit pointer in
the program.
Miscellaneous
+
+
+
+
, Redefine page width. The default value of 20 may be changed if a terminal is attached to the AIM 65.
Initiali;ze to empty program.
Report number of free memory bytes.
Cold start.
7-40
A6S-090
AIM 65 Microcomputer Family
'1'
Rockwell
OISK OPERATING SYSTEM
FEATURES
A disk operating system (OOS) provides a standard interface
between the user and one or more floppy disk drives, floPJjy disk
contrQl (FOC) hardware and executive-level software. The DOS,
imil1emented in software, allows program and data files to be
opened, closed, read and written under operator or program
control. In lin interactive environment, commancls .are usually
initiated by the operator from the keyboard in response to userfriendly prompts di~played by the system.
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PRODUCT OVERVIEW
The AIM 65 Disk Operating system Version 1.0 (DOS 1.0) provides·disk and file management funCtions for the AIM 65 Microcomputer in conjunction. with an RM 65 Floppy Disk Controlier
(FDC) module. With this configuration, mass stOrage files can
be easily manipulated when connected to one to four 5V4" or 8"
floppy disk drives: DOS 1.0 functions, contained On a 4K-byte
ROM that plugs in!o the FDC mQdule, are available immediately
upon computer POWlilr turn-on witho/Jtwaiting for separate loading
of a disk-based DOS into RAM.
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DOS 1.0 functions are operator commandable through interactive AIM 65 Debug Monitor/Text Editor operation as well as
language (assembler; compiler arid/or interpreter). operation.
Text and program source code may be written to, and read from,
disk with the Editor Ust and8ead commands, respectively.
Binary data and program object ~e may be written to, and
loaded from, disk. using the Debl./g Monitor Dump and Load
commands, ~espectively. Files containing source and Object
code for application programs written in AIM.aS Assembler,
BASIC, FORTH, pLj65 and Instant Pascal languages are there- ,
fore supported. In addition, utility functionsfolT11at l!; disk, list the
contents of the disk directory, delete a file, recover a file and
backl,lp a disk upon command. The OOS fun¢tions l11aYal$6 be
called under program control by the application,prOg.raminto
order to read and write data files.
.
AIM 65 Microcomputer compatible
ROM resident for immediate operatlo,n .
. _
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Installs on-board AM 65 Floppy Disk Controller (FOC) module
Provides mass storage of programs and data
Compatible with AIM 65 high level language and Assembler
ROMs
Disk oriented commands (format, list, backup)
File oriented commands (list, delete, recover)
Input/Output commands
--, Read and write text and object code
-Automatic file open and close
User-alterable variables
-'- Utility function and error hal)dling ve~ors (before and after
DOS functions)
.
-Input/output vectors
- VO buffer Vectors
Extensive error detection and 'reporting
MEMORY MAP
Address (Hex)
$8FOO-$8FFF
$8OPO-$8EFF
$8Oo-$7FF
$500-$563
$4Ao-$4FA
$D7-$DE
Contenta
RM 65 FOC MOdule I/O
DOS 1.0 Program ,
OOS 1,c I/O Buffer (default Ioc;ation)
OOS1..0 Variables
.
.
DOS 1.. 0 Variables
DOS 1.0 Variables
ORDERING INFORMATION -.
'. DillCrlptlbn
Disk read. or write errors, both at the OOS and FDC hardware
level, are reported upon dl'tection. User-alterable variables alloW
changing of default valueS to application unique values.
oos 1.0 ROM
A65-090
AIM-~5
RM6s-s101NE '
.....
RM:as FDCMOdu18 (wHhout ROM
. coptainingimmitlve subroutines''')
802:
RM (55 'FOC MOdule User's Man,!al'"
'. D,eerlptlon
DiskS formatted by AIM 65 DOS 1.0 are compatible with AIM
65/40 DOS 1,0 and AIM 65/40 BDOS 1.0. Files written by any
of these DOS programs may therefore be read by either
microcomputer.
Notes:
1. Describes u.ser:s Instructions for AiM 65 OOS 1.0. Included
with A65~ ,and RM65'Sl 01 NI:;,
2. The OOS-1.0 aOM includes primillvesubroutines in addition
to DOS fu.nctiOr:lS.
Document No_ 29001015
7-41
.
Data Sheet Order. No. 0115
March 1983
II
A65-901
AIM 65 Microcomputer Family .
'1'
Rockwell
,~,
, .. '.. . . . . A65-901
.
.
....
AIM 65 PROM 'PROGRAMMER AND"
'., .
CO-ED MODULE .
., .
FEATURES
PRODUCT OVERVIEW
The A65-90i PROM Progra~me~ and CO-ED Module is one of
the hardware options available for the AIM 65 MicrOcomputer
!amily:
.
• F1llJgs directly .onto the AIM 65 Expansion Conne.ctor
• Programs 1he following 5 volt PROMs. (or equivalents):
~.rntel 2758, 2716. and· 2732
~ TI TMS 2508, 2516 and 2532
•. Provides programming fUACtions to check, program, verify
and read ,PROM "
• Includes utility functiOns to load,verify,"dump,fm' ahd invert
memory
. . .i. . . •
• Incorporates objecfcode editor (CO~~D) functions to control
program pointers; search.fQrope~ands, jun;tpslbranc~ and
stri.ngs; and to modify instruCtiOlls wi~hautorn.atic address
, .! "
'
adjustment
• 1K bytes of Static RAM are incll!d~d to alloW single-pass programming of a 4K-byte PROM when used with a 4K RAM
version of AIM 6 5 , '
• L:er-oinsertiori force (ZIF) socket for PROM being'programmed
• Ori'board DCIDC Conl/elter allows 5V~only operation
• .Fully assembled, tested and warranted
.The A65-901 PROM Programmer and COcED Module programs
1K-, 2K-, and 4K-byte PROMs that can be Installed in the AIM
65 microcomputer or in a. RM 65 16K PRPM/ROM Mc:>(!ule. The
Pi={OM Programmer provides check, program, verify and read
functions.
.
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'. The utility ~f the Module isenh!!nced through the iricllJdiad Object
Code Editor (CO-ED). CO-ED allows you to ec;lit.gbjectcode in
much the same way as youean edilllourcElcQdetorthe AIM
~5 ~~~mbl~r, using AIM 65's Te~ Edi~pr, 'With CO-ED,pll:!CheS
can bemacle directly i(1your progra'rn wili:lout h!lving to go
through theilme-consuming process of ~e-assernbling.
,~
:
TheA6s-~01PROM Programmer and CO-ED Module alSo sup-
+
ports data load, verify and dump with offset functions. And the
Module plugs directly into the AIM 65 Expansion Connector.
;:'.'
A65-901 PROM Programmer and CO-ED Module
Document No. RMA65N17
7-42
Data Sheet Order No. RM17
Rev. 1, August 1983
AIM 65 PROM Programmer and CO-ED Module
A65-901
FUNCTIONAL DESCRIPTION
During PROM read operations, the PIA sets the address lines
to the PROM. The tri-state Data Buffer drives the PROM data
onto the AIM 65 Expansion Connector data lines. The Data Latch
is disabled at this time.
The R6520 Peripheral Interface Adapter (PIA) is the primary
interface device between the AIM 65 Expansion Connector and
the 24-pin Zero Insertion Force .PROM socket and control
circuits. During PROM programming, PROM address, PROM
data and programming control signals are transmitted to the PIA
on the AIM 65 Expansion Connector data lines. During PROM
check, verify and read operations, only PROM address and
control signals are issued to the PIA from the AIM 65.
The Power Switches drive +5V or +26V onto three PROM
socket programming lines depending on the PROM type
selected.
The 4K R2332 ROM contains the PROM Programmer and
CO-ED firmware.
Four PIA 110 Lines carry the most significant address signals
to the PROM. Eight other PIA 1/0 lines multiplex the PROM data
and least significant address Signals. One output line controls
the Tri-State Data Latch. Five other PIA 1/0 Lines control the
Power Switches.
1K bytes of on-board RAM are provided for use by the PROM
Programmer and CO-ED software. The RAM is mapped from
$1 OOO-$13FF to provide contiguous addressing from the top of
a 4K RAM AIM 65.
During PROM programming, PROM data is transferred to the
tri-state Data Latch, which drives the latched data to the PROM.
The PROM address is then sent to the PROM on the eight
multiplexed data/address lines and the four dedicated address
lines. The Power Switches are then turned on to apply the proper
voltage levels for the required time duration to transfer the 8-bits
of data into one PROM location. The process is repeated until
the specified PROM address range is fully programmed. The
tri-state Data Buffer is disabled during programming. .
The Address Decode circuitry generates individual chip select
signals to the RAM, ROM, PIA and the Data Buffer.
The PROM Programmer and CO-ED Module may be powered
from the AIM 65 or from an external + 5V power supply. A DCIDC
Voltage Converter generates + 30V from + 5V. The + 30V is
regulated to + 26V for on-board use. The + 30V may be
connected to an external pOwer supply to minimize current drain
on the +5V supply.
CONNECT TO AIM.&5
EXPANSION CONNECTOR
-
2
1
2
~
10
4
AODRESS
DECODE
2..<-
4K
R2332
ROM
1
J~
DATA
BUFFE:R
(TRI-STATEI
8
D
1
1
2
1
5
3
CHIP SELECT
8
CLOCK AND
CONTROL
ADDRESS
16
4
8
8
R6520
PIA
DATA
-I~:~~~AH)
8
4
DATA
10
1
r,.....
POWER
SWITCHES
1.,;:.
lK
2114
RAM
1 L
, ... - ..
+5V
A
B)
.....
I
I OC/OC
+5V TO +30V ~r1 +26V
~
VOLTAGE
I CONVERTER
I
'.
A
+5V
.~
GND
I
b
C
GND
REGULATOR
)
D
+30,V
A65-90l PROM Programmer and CO-ED Module Block Diagram
7-43
24.PIN
PROM
ZIF
SOCKET
5
L.!.,<...
GND
8
3
AIM 65 PROM Programmer and CO-ED Module
A6·5-901
AIM 65 Expansion Connector Pin Assignments
Top
~Component
Sidel
Bottom (Solder Side)
..
Signal
Inputl
Signal Name
Mnemonic
SYNC
ROY
<1>1
IRQ
S.O.
"Sync
0
"Ready
I
"Phas'e 1 Clock
"'nterrupt Request
"'Set Overflow
NMi
*Non-Ma~kapte
·RES
07
06
05
D.
03
02
01
DO
Interrupt
Reset
Data Bit 7
Data Bit 6
. qata Bi~ 5
O<;lta Bi,t.4
Data-Bit 3
Data ,Bi',t 2
Data Bit 1
Data Bit 0
*-12 Vdc
"+12Vdc
Chip SelectS
Chip S~recJ 9
·Chip Select A
+5 Vdc
Ground
·12V
+12V
csa
CS9
(:SA
+5V
GND
Output
0
,
Pin
Pin
1
2
3
A
B
C
0
E
F
H
J
K
L
M
N
P
R
S
T
•
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
5
6
7
8
9
10
11
12
13
"
15
16
17
18
19
20
21
22
0
0
0
U
V
Signal
Mnemonic
AO
A1
A2
A3
A4
A5
AS
A7
A8
A9
A10
A11
A12
A13
A14
A15
SYS <1>2
SYS R/W
w
AiW
X
Y
TEST
Z
RAM
iP2
R/W
Signal Name
Addre~s
,lnputJ
Output
Bit 0
Address Bit 1
Address Bit 2
Address
Address
Address
Address
Bit
Bit
Bit
Bit
3
4
5
6
Address Bit 7
Address Bit 8
Address B'it 9
Address Bit 10
Address Bit 11
Addres's Bit 12
Address Bit 13
Address Bi~ 14
Address Bit 15
System Phase 2 Clock
System Read/Write
Read/Write "Not"
Test
Phase 2 Clock "Not"
RAM Read/Write
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0
0
0
·0
0
0
NOTE:
.
.., '" N6t used on this module
PROM Programmer Commarid$
Category
Command
Function
ENTRY/EXIT
F1
F2
ESC
ENTER PROM PROGRAMMER
RE-ENTER PROM PROGRAMMER
ESCAPE TO MONITOR
BASE ADDRESS
8
0
PROM BASE ADDR,ESS
RAM BASE ADDRESS
PROM
C
P
V
R
CHECK PROM
PROGRAM PROM
VERIFY PROM
READ PROM
L
T
0
M
I
LOAD MEMORY
VERIFY MEMOAY
DUMP MEMORY
FILL MEMORY
INVERT MEMORY
1
2
T'OGGLE RECORDER CONTROL LINE 1 ON/OFF
TOGGLE RECORDER CONTROL LINE 2 ON/OFF
MEMORY
.:'
RECORDER CONTROL
CO-ED Commands
Category
Command
Function
ENTRY/EXIT
F3
/
ESC
ENTER CO-ED
EXIT CO-ED
ESCAPE TO MONITOR
POINTER CONTROL
W
T
B
U
0
G
X
LOCATE PROGRAM
MOV E TO TOP OF PROGRAM
MOVE TO BOTTOM OF PROGRAM
MOVE UP ONE ,INSTRUCTION
MOVE DOWN ONE INSTRUCTION
GO TO ADDRESS
EXCHANGE POlf'l~ER~
SEARCH
F
J
S
FIN'D AN OPERAND
FIND JUMPS AND BRANCHES
FIND A STRING
I
A
C
M
R
INSERT AN INSTRUCTION
STRIKEOUT AN,INSTRUCTION
ADJUST INSTRUCTION BLOCK
CHANGE INSTRUCTION
MOVE INSTRUCTION/DATA BLOCK
RELOGATE
K
FILL MEMORY
DISASSEMBLE MEMORY
PROGRAM MODIFICATION
$
UTILITY
,
'7-44
~65-901
AIM 65 PROM Programmer and CO-ED Module
SPECIFICATIONS
Value
Parameter
Dimensions
Width
Length
Height
4.4. in. (111 mm)
6.3 in. (160 mm)
0.75 in. (19 mm)
Weight
5.3 ox. (150 g)
Environment
Operating Temperature
Storage Temperature
Relative Humidity
O·C to 70°C;.
·40·C to 85·C
0% to 850/0 (without condensation)
Power Requirements
With DC/DC Converter
+5V ±5%,1.1A(5.5 W) -Maximum
+5V ±5%, 0.75 A (3.75 W)- Maximum
+ 30V ± 5%, 0.04A (1.2 W) - Maximum
Without DC/DC Converter
Memory Map
User RAM
I/O
ROM
$1000 - $13FF
$8800 - $8FFF
$9000 - $9FFF
7·45 .
'1'
Rockwell
A65-905
AIM 65 MElVIORY CARTRIDGE
.PR()DUCT OVERVIEW
FEATURES
The A65·~05 Memory Cartridge is one of the hardWare options
'
,available for the AIM 65 Microcomputer fill)1ily.
., Preconfigured Memory Cartridges
-AIM 65 high level'languages and support firmware
-Up to 16K bytes additiQn~
(volatile or non-volatile)
-Up to 32K byte additional PROM/ROM
-Combination RAM and PROM/ROM
RAM
Many applicatiol"!s of AIM (l5 microcOrTfputers, particularly in test
equipment, Instrumentation, monitors, analyzers or controllers,
require that the resident application sqftware or fixed parametric
data be changed periodioally. This may oCcur because the item
under test or being controlled has been changed, or parameter
values have been revised: For OEM' installations, the change
,may be required to customize the system for different customers.
•
•
•
,.
PermanEint Buffer Module installation
Convenient Memory Cartridge plug-in installation '
,Use with any AiM ,65 500 series Desktop Microcomputer
Compatible Vfith A65-0OS enclosure and power supply,
• Cartridges are fully assembled"test~d ,and warranted
The AIM . 65 Memory Cartridge system 'is an eConor;!1ical and
com;enientrriethod for ellpanding the memory of an AIM 65
microcomputer. The cartridges are designed for use with the
Rockwellpackageq 500 Series of desktop microcomputers, but
may also be used with any AIM,65 board·levelmicrocomputer.
A Buffer Module connects to the AIM 65 Master Module, buffers
the expansion bus signals, and provides a covered host recep·
tacle for a Memory Cartridge. In addition to expanded RAM and
provisions for user application PROM firmware, a variety of pre·
configured AIM 65 high level languages, assembler and math
package routines are available in plug· in Memory Cartridge
form, These language cartridges permit the user to program
different applications in different languages. Unpopulated RAM
and PROM/ROM cartridges are also available for complete user
fleXibility.
ORDERING INFORMATION
1'.65-905-00
1'.65-905-01
A65-905-o2
1'.65-905-03
A65-905-o4
A65-90S-05
AS5-905-OS
1'.65-905-07
'1'.65-905-08
1'.65-905-09
The Buffer Module fits under the AIM 6,5 Master Module and
fastens securely to the Rockwell AIM 65 Enclosure. Rugged
injection molded plastic covers for both the Buffer Module and
the Memory Cartridge complement the AIM 65 Enclosure in
color, texturE! and sturdiness. A Memory Cartridge plugs verti·
cally into the Buffer Module immediately behind the microcom·
puter enclosure to require a minimum of area in desktop
applications. A recessed label area on the Memory Cartridge
cover allows configuration information to be neatly added in an
area visible to the operator. Address decoding required by the
different cartridges is accomplished automatically without user
intervention.
Buffer Module
BASIC Interpreter, Assembler, BK CMOS RAM
& 4K User PROM Socket
PlI6S Compiler, Assembler, 8K CMOS RAM &
4K User PROM Socket
FORTH, Math Package, 8K CMOS RAM & 4K
User PROM Socket
Instant PASCAL & 6K CMOS RAM
32K PROM'ROM (1)
16K CMOS RAM
16K CMOS RAM (unpopulated)
8K CMOS RAM & 16K PROM'ROM (1)
16K Battery Backed CMOS RAM
.A 16K Battery Backed CMOS RAM Cartridge retains program
and data in memory when the AIM 65 Microcomputer power is
turned off. Critical information can thus be preserved during AC
power transients or outages and during normal turn-off cycles.
AIM 65 Desktop Microcomputer with Memory Cartridge
Document No. 29000D98
7-46
Data Sheet Order No. DSE
Rev. 2, August 19~
AIM 65 Memory Cartridge
A65-905
FUNCTIONAL DESCRIPTION
decoder and drive the appropriate decoder output to the low
state. The eight decoder outputs form the eight active low chip
select signals for the cartridge.
BUFFER MODULE
The Buffer Module interfaces the AIM 65 Expansion Connector
to a Memory Cartridge as illustrated. Non-inverting circuits
buffer the data and. address lines. Data direction is controlled
by the BR.iW signal. During a write operation, data from the AIM
65 Master Module is directed towards the cartridge. During a
read operation, data from the cartridge is directed towards the
AIM 65 Master Module. The RAM R/W signal is routed through
the Buffer Module to the cartridge interface to control the Memory
Cartridge device read/write operation.
PROM timing is controlled by a delay Circuit implemented with
a mono-stable multivibrator. This circuit delays the turn-on of
the address deCOde .PROM to prevent bus contentions at the
beginning of each cycle.
Power for the Buffer Module is derived from the AIM 65 power
supply through the Expansion Connector. Power for the cartridge is routed through the Buffer Module.
MEMORY CARTRIDGE
Address decoding is accomplished by a factory programmed
256 x4 PROM which drives a 3-to-8 decoder. An interlock
signal (PE) ensures the PROM is enabled only when a cartridge
is installed. Three address straps within the cartridge (51, 52,
and 53) identify the cartridge type installed by selecting the
appropriate address decoding section in the PROM. The five
most significant buffered address lines address one of the 32
bytes within the selected section. A valid address for the installed
cartridge results in a low level signal on the most significant
PROM output pin. This signal in turn enables both the 3-to-8
decoder and the data transceiver. The remaining three PROM
outputs (01, 02, and 03) provide the selection input to the
The Memory Cartridge has eight 24-pin sockets which can
accept'2K RAMs, 4K PROMs or 4K ROMs. In models -01,
-02, -03, -05, and -08, sockets are available for user supplied
PROMs. In model -07, sockets are provided for user supplied
RAMs.
Variations in socket functions are accomplished by routing
selected signals through factory installed jumpers. The eight
sockets are arranged into three groups as illustrated in the block
diagram. All sockets in each group are configured to accept the
same memory device type.
-.ICTSTO
AIUII
CONNECTS
TO
MEMORY
CARTRIDGE
EXPANStON
CONNECTOR
BUFFER MODULE
-
,-----
J1
DATA
(DO-D7)
DATA
TRANs"
la
CEIVERS
OIRECTlON
iRRI'
la
'----
J.
rBUFFERED DATA
(800-801)
~
,
,---
I"
ADORe8S
I"
ADDRESS
BUFFER
(AOoA1S)
L"
BUffERED ADDRESS
(BAG-8AI5)
'--ENABLE
lr--C4~ H-
t- , - ,
... ,.
L
~....
~
'---,
ENABLE
DISABLE
ADORESS STRAPS
(81·83)
INTERLOCK
(PEl
-DELAY
CIRCUIT
1
-
+,.,
+5V
ONO
RAM Rm
-
'--
Buffer Module Block Diagram
7-47
RAM RNi
AIM 65 Memory Cartridge
A65-905
INSTALLATION
2. There is no on/off switch for the battery. Remove the battery
to prevent draining the battery when the cartridge is not
powered.
BUFFER MODULE
1. Before installing the Buffer Module, turn off power to the AIM
65 Microcomputer.
3. The battery will last six months ih battery back-up mode.
Therefore, replace the battery after six months of use. The
replacement battery should be either a Gl:: or Sanyo CR2032.
2. Align the Buffer Module Connector J1 pin 1 with the AIM 65
ExpanSion Connector J3 pin 1.
4. A potentiometer in the cartridge sets the voltage threshold
level at which the cartridge switches from Vcc mode to battery back-up mode. The factory set levels areapproxirnately
+4.5 Vdc for battery back-up and +4.7 Vdc for Vee power.
Adjust this potentiometer while monitoring the voltage on pin
4 of Z9 to raise or lower these levels. When pin 4 goes high
(about +5 Vdc), the cartridge is in battery back-up.
3. Carefully slide the Buffer Module under the AIM 65 Master
Module, . plugging the Buffer Module onto the Expansion
Connector. Press in firmly on the end of the module assembly
until all pins are securely seated.
4. If. your AIM 65 Microcomputer is installed in an AIM 65
Enclosure, fasten the Buffer Module Assembly bottom plate
to the base plate of the enclosureLJsing the screws p~ovided
with the Buffer Module.
MEMORY CARTRIDGE
1. Before installing or removing a Memory Cartridge, turn,·off
power to the AIM 65 Microcomputer.
2. To install the cartriqge, align the cartriqge wtth the label side
towards the microcomputer and plug the cartridge, into tne
Buffer Module receptacle (the cartridge is keyed to prevent
improper insertion). Press down firmly on the top of th~ cartridge until all pins are securely seated.
MEMORY CARTRIDGE BATTERY INSTALLATION
(A65-905-090nly)
1. The battery is NOT factory installed. Install the battery by
sliding it into the holder pi us side (+ ) up.
CONNECTS TO
BUFFER
MQbULE
.,
MEMORY CARTRIDGe
-0-1rO'-;
1- -O-z~--[J~
- ~
BUFFERED OATA
(fiDO-BD7)
I
'
I
I SOCKET GROUP A
L _________
SUFFERED ADDRESS
(BAD-BAtO)
II
I
I I SOCKET
I
I I GROUP B
I
JI _ _ _ ..J
I -' - - - - - - - - - - - - - - -:
iOODD!
I
I
SOCKET GROUP C
L _______________ I
CHIP
PINS 24
r------,---t~--- SOCKET GROUPS A. B, & C
SREeTS
IC$1·Cs8)
INTERLOCK
(PEl
AODFIESS STRA~S
(51·53)
+5.
BATTERY BACKUP
CIRCUITS
(A6S.90S-09)
RAM RIW
I-+-'--";~
8M2
L-_ _
~ ~~ _-_-_~ _:_~_:_,:_:_:_~_:_:_: _:
PINS 21
_____
I
_______________________
Memory Cartridge Block Diagram
7-48
ASS-90S
AIM 65 Memory Cartridge
Memory Cartridge Memory Map
Cartridge Model (A6S-90S-XX)
Block
Starting Address
0000
-01
-02
-03
(1 )
-04
-05
8K RAM
8K RAM
6K RAM
4K PROM
4K PROM
4K PROM
PASCAL
BASIC
PL65
FORTH
PASCAL
0000
Assembler
Assembler
Math Pack
EOOO
AIM 65
MonRor
AIM 65
Monitor
AIM 65
Monitor
1000
-06
-07
-08
-09
16K RAM
8K RAM
16K Battery
Backed
RAM
AIM 65 Master Module RAM
8K RAM
32K PROM
16K RAM
2000
3000
4000
16K PROM
5000
6000
7000
8000
9000
AOOO
BOOO
AIM 65 Master Module I/O
COOO } (2)
FOOO
AIM 65
Monitor
AIM 65
Monitor
AIM6S
Monitor
AIM 65
MonRor
AIM 65
Monitor
Notes:
(1) Master Module only.
(2) These blocks are addressed on the AIM 65 Master Module in addition to the cartridges. Components must be removed from AIM 65 Master
Module sockets Z24, Z25, and Z26 prior to installing the memory cartridge model -01, -02, or -03. Component must be removed from AIM 65
Master Module socket Z26 prior to installing cartridge module -04.
Memory Cartridge Component Summary
Cartridge Model No. (A6S-90S-XX)
Socket
-01
-02
-03
-04
-05
-06
-07
-08
-09
BASIC
PLI65
FORTH
PASCAL
PROM/ROM
RAM
User
RAM
RAM and
PROM/ROM
Battery
Backed
RAM
Zl
RAM
RAM
RAM
RAM
PROM
RAM
RAM
RAM
RAM
Z2
RAM
RAM
RAM
RAM
PROM
RAM
RAM
RAM
RAM
Z3
RAM
RAM
RAM
RAM
PROM
RAM
RAM
RAM
RAM
Z4
RAM
RAM
RAM
R32P2-11
ROM
PROM
RAM
RAM
RAM
RAM
Z5
(1 )
PROM
(1)
PROM
(1 )
PROM
R32P3-11
ROM
PROM
RAM
RAM
PROM
RAM
Z6
R3226-11
ROM
R3299-11
ROM
R32Jl-ll
ROM
R32P4-11
ROM
PROM
RAM
RAM
PROM
RAM
Z7
R3225-11
ROM
R3298-21
ROM
R32J2-11
ROM
R32P5-11
ROM
PROM
RAM
RAM
PROM
RAM
Z8
R3224-11
ROM
R3224-11
ROM
R32L3-11
ROM
R32P6-11
ROM
PROM
RAM
RAM
PROM
RAM
Function
Notes:
1. All PROM is user provided TI2532 or equivalent.
2. All RAM is Toshiba TC5516Ap, Toshiba TC5516APL or Suwa Seikosha SRM2018C.
7-49
II
AIM 65 Memory Cartridge
A6S-90S
Buffer Module to AIM 65 Expansion Connector Pin Assignments
Top (Component Side)
Pin
Signal
Mnemonic
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SYNC
ROY
)61
IRQ
S.O.
NMI
RES
07
06
05
04
03
02
01
DO
-12V
+12V
eS8
eS9
CSA
+5V
GND
Signal Name
'SYNC
'Ready
'Phase 1 Clock
'Interrupt Request
'Set Overflow
'Non-Maskable Interrupt
'Reset
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
,
-12 Vdc
'+12 Vdc
'Chip Select II
'Chip Select 9
'Chip Select A
+5 Vdc
Ground
Bottom (SolderSide)
Input!
Output..
Pin
A
B
C
0
E
F
H
J
I/O
I/O
K
VO
I/O
I/O
1/0
1/0
I/O
.'
L
M
N
P
R
S
T
U
V
W
X
Y
Z
Signal
Mnemonic
AO
A1
A2
A3
M
A5
A6
A7
A8
A9
AtO
A11
A12
A13
A14
A15
SYS ¢2
SYS R/W
R/W
TEST
¢2
RAM R/W
Signal Name
Address Bit 0
Address Bit 1
Address Bit 2
Address Bit 3
Address Bit 4
Address Bit 5
Address Bit 6
Address Bit 7
Address Bit 8
Address Bit 9
Address Bit 10
Address Bit 11
Address Bit 12
Address Bit 13
Address Bit 14
Address Bit 15
System Phase 2 Clock
'System Read/Write
Read/Write "Not"
'Test
Phase 2 Clock "Not"
RAM Read/Write
Inputl
Output"
I
I
I
Note:
• = Not used on this module.
,. ; With respect to the Buffer Module.
I
Memory Cartridge to Buffer Module Connector Pin Assignments
Rear
Front (Label Side)
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
Signal
Mnemonic
BA3
BA1
BA7
BM
BAt5
BA14
BA12
BA9
BA11
BOt
BD3
BD5
SO?
CS2
CS4
eS6
esa
RAM R/W
S2
+5V
GND
Signal Name
Address
Add ress
Add ress
Address
Bit 3
Bit 1
Bit 7
Bit 4
AQdr~s Bit 15
Address Bit 14
Address Bit 12
Address Bit 9
Address Bit 11
Data Bit 1
Data Bit 3
Data Bit 5
Data Bit?
Chip Select 2
Chip Select4
Chip Select 6
Chip Select 8
RAM Read/Write
Address Strap 2
Not Used
+5 Vdc
Ground
Inputl
Output"
Pin
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I
I
I
I
I
1
3
5
7
9
11
13
15
17
19
21
23
25
2?
29
31
33
35
37
39
41
43
0
Note:
"With respect to Memory Cartridge.
7-50
Signal
Mnemonic
BA2
BAO
BA6
BA5
PE
BA13
BA8
BA10
BOO
BD2
BD4
BD6
CS1
eS3
CS5
eS7
S3 .
S1
+5V
GND.
Signal Name
Address Bit 2
Address Bit 0
Address Bit 6
Address Bit 5
Not Used
PROM Enable
Address Bit 13
Address Bit 8
Address Bit 10
Data Bit 0
Data Bit 2
Data Bit 4
Data Bit 6
Chip Select 1
Chip Select 3
Chip Select 5
Chip Select 7
Address Strap 3
Address Strap 1
Not Used
+5 Vdc
Ground
Inputl
Output..
I
I
I
I
0
I
I
I
I/O
I/O
VO
I/O
I
I
I
I
0
0
A6S-90S
AIM 6S Memory Cartridge
SPECIFICATIONS
Value
Parameter
Dimensions
Width
Length
Height
Memory Cartridge
Buffer Module
5.25 in. (133 mm)
4.85 in. (123 mm)
0.88 in. (22 mm)
4.75 in. (121 mm)
4.69 in. (119 mm)
1.48 in. (38 mm)
Power
-01, -02, -03
-04
-05
-06, -07, -09
-08
Environment
Operating Temperature
Storage Temperature
Relative Humidity
+5V ± 5%
550 ma-Typical
550 ma-Typical
870 ma-Typical
380 ma-Typical
620 mac-Typical
O"C t050'C
-40'C to 85°C (except A65-905-09)
-20"C to 50"C (A65-905-09)*
0% to 85% (w~hout condensation)
Interface Connections
AIM 65 Expansion Connector
+5V± 5%
250 ma-Typical
O'C to 70"C
-40'C to 85'C
0% to 65% (w~hout condensation)
44 pin-edge receptacle
(0.156 in. centers)
Buffer Module to Cartridge
44 pin-edge connector
(0.100 in. centers)
44 pin-edge receptacle
(0.100 in. centers)
Note: * -40"C to 85'C if the battery is not present.
II
7-51
SECTION 8
~IM 65/40 MICROCOMPUTER FAMILY
P,ge
Prbduc~ Family Overview ", :.. ' , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,-,
8-2
A65/40-8X15 Series 8000 Microcomputer System " " " " , ' , " " " ' , ' , " " " " , ' 8-3
A65/40-2000, A6S/40-3000, A65/40-4000 and A65/40-5000 AIM 65140 Microcomputer, , 8-10
A65/40-1000 Single Board Computer, , , , , , , , , , , , , , ......... , , . , .......... , .... 8-22
A65/40-0004 Power Supply and Cable " ........... , .... , " " " " " " " ' , ..... 8-30
A65/40-0200 and A6s/40-0210 Standard and Extended Keyboards , ............ ,'"
8-32
A65/40-0400 40-Character Display , ; . , .. : . , .... , ... " .. , , . , , : . . . . . . . . . . . . . . . . . 8-36
A65/40-0600 Graphics Printer, , . , . , , , , . , , , , , .............. , , , . , ... , ......•... 8-43
A65/40-0800 Video Display Controller Module ............ , ...... , .. , " " ' . " ' " 8-49
A65/40-7010 Assembler ROM ............ , ................................... 8-56
A65/40-7012 Macro Assembler and Linking. Loader .............................. 8-58
A65/40-7020 BASIC Interpreter ROMs ......................................... 8-59
A65140-7024 BASIC Compiler .. , ...... , ......................... ~ ............ a-S1
A65/40-7040 Math Package ROM ............................................ 8-63
A65/40·7050 FORTH ROMs ......•............................•.............. 8-65
A65/40-7052 FORTH 'f;a:rget Compiler ...•....................... ; ............. 8-70
A6S/4(),;7090
.. .
mSkOpe;~ting System Version
.
'
"
'
1.0 (DOS 1.0)
ROM .... :; ............
A65/~7092 Bootstrap Disk Operating System Version'1.0 Upgrade Kit.
8·1
"
8·75
, •...... 8-76
AIM 65/40 MICROCOMPUTER FAMILY·
Modular Microcomputer Family With Wide OEM, Control Capabilities
The AIM 65/40 modular microcomputer system allows
functional steps up from the AIM 65 microcomputer in hard
working blue collar applications,at very competitive prices.
It als,o offers an extremely wide range of languages,
controller options and an operating system for even greater
application fJexibility.
The four 'basic mOdules of an AIM 65/40 include an
R6502 based single board computer, an intelligent printer
with 40 column alphanumerics and graphics capabilnies, a
40-character intelligent alphanumeric VF display, and a fuU
ASCII keyboard. It may be purchased as a complete set for
end users or as separate modules for OEM' users. The
printer and display modules' may be mounted remotely from
the single bOl!ord computer.
Language ROMs include BASIC interpreter and compiler,
FORTH firrT)ware and compiler. An assembler ROM, debug
monitor,and text editor ROMs, math package ROM 'add to
the versatifity. There are even disk operating systems.
A video controller module can be pre-configured onto the
AIM 65/40 or can be used stand alone with other
microprocessor based systems. It gives the AIM 65/40 the
ability to command screen formatting, text handling and
screen editing, plus full'graphics,'drawing and data display
functions. When pre-configured, the AIM 66/40 comes with
an extended keyboard that inclildescursor movement
,~ontrols and ,a numeric keypad,;:'
'
. For ,desk ,tpp use, th~ ,AIM 65/40 comes i,n an attra~lve
enclosure; IncCluding power supply and anexpansioncat'd
cage which,can accept anyRf¥I 65 ,EurqPard module., With
Its built-In features and expansion capabilitiea, the desk top
AIM, 65140 can be any type ofrnicrocomputer system you
might need, .
,'
.
.'.
..\
In the' blue coilar family, ttle AIM 65/40 microcomputer
provides more"power, greater fll!~ibility,'for more
applications.
AIM 65140 MICROCOMPUTER
. BOARD-LEVEL VERSION
AIM 65140 MICROCOMPUTER
PACKAGED VERSION
8-2
,A65140~8X15
i"
~ .'
AIM
'1'
Rockwell
'
",
"
• i 24 lines
is automatically selected. A 40 x ?4 formaiis alllO available arid
other fOrmats are user programmable. Eight pages of text are
available In thE!. 60 x 24, form/it with aUtomatic page s~ing for
other formats. A 4K-byte character generator ROM contains bit
patterns for 256 different characters in a 7 x 10 dot matrix field.
Standard characte.rs Include upper- and lower-case alphabetics,
numerals (Including subscripts and superscripts), math and
G.reek symbQls, common European letters, and semlgraphlc
.characters.
.
The full graphics mode incorporates bit mapping of 260 x 224
ll'Je1s, which is cm the sec module and toutes
the si~als to the··Printer conn~or on the back panel:
'40-CharaclerDlsplay (ModeI8-8415 and-8s15) .
The 40-Character DisplayirlclLides a vacuum fluprescent display and Ii deqiqat!ild mict~prOCel!SOr-Mse(l controller. The
vacuum fluorescent display isa Single sealed. unit containing 40
;separately controllable digits. Each digit is composed of a 16. 'segrrenUorit which illuminates a fijI' set of upPer case alpha. biltics, numerics, and special characters. In the semi-graphics
the 1~ segments foreach-digiillt"e individuaHycontroiled.
Jrjadditkln,.each dig~ includ~s ~paraie decimal point When
energized, the digits form .. blight, . crisp characters in a bluegreen color.'
.
""ode,
When the BASIC ROMs arEl installed, the microcomPUter auto~
matically Initializes to the BASIC cOl1')mand level unless overridden by an .application program auto-start 59Q4ence. E~y
entry to the Debug Monitor Bnd Text Editor cpmrriand levels
allow machine level debugging, assembler selection and text
entry/editing.
a
Debug MonitorfText EditQr ROMs
The Debug Monitor/Text Editor irlcludes a wide selection of
.furlctions to simplify computer program entry and checkout. Text
can be easily entered, edited, saved and retriev!!d Using .either
line- or screen-oriented commands in the Text Editor. A char~
acter cursor can be positioned'ieft, right, up, or. down to aid. character insertion, addition, and deletion. Automatic and selective
character string change capability makes block changes as
desired. Multiple text buffers can easily be l1')alntained for sep!
arate program ~nd:data files.
.E)rtended Keyboard
The ExtEmded Keyboard contains a 57-key full-size terminal
style alphanumeric keyboard with locking SHIFT key, a 15-key
nUmeric and c.urspr control keyboar(i, !!ight fUrlction keys, and
separate RESET and ATTN keys.
. ' .'
.SOFTWARE DESCRIPTION
Stan<:iard ROM-based software in. ttl!! S!!ries 8000 Microcompuler System provides either immediate development capability
in eASIC and R6500 ass!!mbly language or automatIC application program startup in a run-time environment. Program!initiation can be performed ..eitti~r in a PROM/ROM-based
application:program or in RAM'~fter an automatically iniliilted
load of.the .application 'prograll]'from floppy disk: The FK>Ms
inl1falled in~ach Series 8000siSie/J'ls are:
.
• AIM
65140 Vb ROM
• AIM' 65/40 Bootstrap Disk
(BOOS to) .
it! .•. . . .
6~;~iirig
.
'
,
The De/JUg Monitor coRtrols .program execution in single step
and run modes' and allows COtwimient exam.ination andalterin~
of··rhemory .an.d 'regiS\ers.Single step mode disassembles
. instructions and traces register contents upon command for
detail examination of program operation. Symbol level dEl!bug.~
ging reduces dePendencie 0r:l absolute addresses and~implifies
program checkout. Commandstrin'g capabil.ity allows 9OI1)mand
sequerlcesto be chained an~ eaSily repeated.
, $ASICROMs
.
The 8K Microsoft-developed BASIC Interpretet imple~l1ts
industry sta.~dard high levellimguage which issimplebilt Pow~
a.h
System Version 1.0
erlul ..andiscommonlyused: in ,industry, science
• AIM. 6514() Debug Monitor/Tela Editor
• AIM 65140eASIC Interpreter
• AIM 65140~sembler
and~hools;
m"":'!'.'
BASIC operates in one of two modes, development.al'ld rUn"
.•
time. In the development mOde,BASICstatements are ~htereq'
and executed aseith!!r director indirect commands. Direct com~ .
mands aree.xecuted uppnentrY. to provide .immediatetesL!I~·i
'. ....
however, the statements are not stored for subsequent execution. Indirect commands are . en!ered along'liith an aSliQCiated
lin!! number and are executed."upon RUN command.$ntry or
applicationprogran:J auto-start i.Oitialization. Indirept sta~rnen~$
cianaiso .bElloadEld intO,:'the Text Editor for Mtry into BASIC tCi
simplify prograrit· editing. The. ~icrocompUter peripheral/!, i.e.,
keyboard, 4O':¢haracter single 'line display/Vidl'l0 displ~ a~d
Printer, are used in·the,~eveIOPliRent mode to enter statements;
I!> list entered indirect $tatemenls and to display/print exiicutlon
results.
I/~ ROM
The I/O ROM includes preprogr&mme(l auto-start initialization,
interrLipt, inputloUtpulandlJtllitY functions' which support userdefined prq~rams as weUas Se~l~ .8000 standardfirmwarieand
optionalfirr:i\ware/software: Aut~~~t~~ initialization.jumps tp pre.ctetermin8d·..,pROMlROM addre~I$S':during RESET proce!lsing.
The application program Can a5l!!'l/rlEl direct control. l'!f the system
for continue,d oPeration; or it canjust.·initialize requited fundians,
then retumcontrol back to the 1/0 ~OM for continued aut()"start
of oth~r function/!. VOdrivers directly suppOrt inte.lligent di$play
and printer peripherals. Other driliilis support the RS-232CI
20MA interfaces and the audio,',casSette ports, and contro.! the
on-board speakers.
.
Assembler ROM
The assembler translate.s computer program:Im;;lructiol;lswritten
in R6500 ~mbly 11!n.(Juag& for the 6502 microprocessor into
machine cO(je that will operate. t\ithe~ in tht;lSeries.8000Micro;.
computer System or in any65XX CPU-based microcomputer.
Operating ~ptions are selected interactively by the:operator
BOOS 1.0
The BOOS '1.0 ROM provides disk 'and file management' functionsas well as automatic IOadi~90f a bootstrap loadet· from
8-7
A65/40-8x15
AIM 65/40 Series 8000 Microcomputer System
SOFTWARE OPTIONS
upon assembly command. These options specify source code
device, object code device, symbol lable location, full assembly
or errors only output listihg. and output listing device. A repeat
Command irivokes the assembly according to previously commanded options for rapid setup during program debugging;
editing and reassembly. Memory to memory assembly is supported to speed program generation.
..
Pari No.
Description
Disk-Based!"
A65/40-7012
A65-4O/7024
A65/ 40-7052 .
ROM-Based
A65/ 40-7040
A65/40-7050
AIM 65/40 Macro Asse;nbler ~nd Linking LOader
AIM 65/40 BASIC Compiler
AIM 65/40 FORTH Compiler
AIM 65/40 Math Package .ROM
AIM 65/40 FORTHR9Ms
Note: Provided a 51/4-inch double-deJ'isily floppy' disk' compatible
with AIM 65/40 BOOS 1.0.
MEMOR,YMAP
BANKO
FFFF
FFFF
FOOO
AIM 65/40
I/O ROM (1)
EOOO
AIM 65/40
BOOS 1.0 ROM.
0000
ON,BOARD
PROM/ROM
DEDICATED
TO BANKo
.AIM 65140
BASIC. ROMs
COOO
COOII
DEBUG~ONITO~
8000
I
I
ON-BOARD
RAM
DEDICATED TO
BANK 0
OR
COMMON TO
,BOTH BANKS
7000
ON-BOARD
48K RAM
5000
....
'.,'.'
I
AIM 65140
ASSEMi31.EFi RO~(2)
8000
6000
--,-'
I
& TEXT EDITOR.ROMs (2)
AOOO
9000
1-"":'
I
AIM 65/40'
BoOO
.
I/O ROft/! CO,,",MON TO
, BOTH BANKS
FOOD
I
I
I
I
4000
3000
2000
1000
1000
ON-BOARD
!'lAM
C()MM()NTO
BOTH BANKS
OPTIONAL LANGUAGe
AND RM 65 MODULE.FIRMWARE VARIABLES (3)
,-.- iiOi MONiTO"RVARiAetES-- - __ ~CPU STACK ... -
- - - - PAGE ZEROoA'i'A -
I
--.l
I
--
o
I
Banking Memory Map .
Software Memory Map
Notes: (1) AIM 65/40 System Pli'ripheral I/O addresses are assigned
to FF80~FFDF.
'
(2) User available'during application 'program operation,
(3) User available if the optional language and the RM 65
expansion module ROMs are not used.
8-8
,'"
AIM ~/40 Series, 8000 Microeomputer'System
405140-8 x 15
SPECIFICATIONS
parameter
. Value
Pliramel8r
ElectriCal (cont,I
J3(Audio/20 mA
Current Loop)
Dlmenelone
Main I:nclosure
Width
Length
Height
Keyboard Enclosure
Width
Length
Height
17.00 in. (43.2 em)
7.75 in. 09.7 em)
2.26 In. ( 5.8 ern)
J4 (C~rriPosite Video)
J5 (Floppy Disk Drive)
17.00 in. (43.2 em}
17.68 in. (44,9.cm)
6.00 In. (15.2 em)
J7 (t:'rlnter) .
Ac POWer C~nnecition
PoW~tConnector
Environment
Operating Temperature
With Printer
Withoul·.print,r
Storage Temperature
WHh Printer
WHhout Printer
Relative Humidity
Electrical
Interface Connectors
(Back Panel)
J1 (Parallel
ApplicatiOn)
J2 (Serial RS-232C
Application)
~i~t8dkn.clor
2D-pinmass
(3M#a421-7020 ecjill\l~~nt)
RCA
type: ....•. '., '.' .. . . . ','
(Alfl8d #llOBB Or ecjuivalent).
34-pinrn8SS' terminated connector
(3M#3414-6034 Or equhialenl)
36-pin mass I!'rminated cO~lllIcIor
~M#3368-1001 Or equivalent
eti<:
or
~
':,
.~'pr&,g' ~cess8dGrounding Plug
(NI:MA5-15p)'
.
,
',:
O'C to 50·C
O'C to 70"0
Power Cord
Type
0·Ot070'C
-25·C to 85"0
0% to 85% (wHho.ut condenl'8lion)
..
Detachable,3-Conductor
Length
6Eset .'
R8tlng
LjneE'1d
125 Vac.15A Service
Molded Vinyl Grounding Plug
(NEMA 5:15p)
.
Molded Vinyl Grounding Receptacle
Microcomputer End
AC Power Requirement
Input Voltage
Fu.sa
115 Vae :10%.47-63 Hz
. 230 Vac, 3A•. SIo-Blo
40-pin mass terminated' connector
(3M#3417-7040 or.equivalent)
25-pin Delta connector
3M#3482-1000 or equivalent)
r.I
1:1
A65/40-8515 Microcomputer Systc!m:""'Back Pa~1
8-9
",'"
A65/~0-2000, -3000, -4000, ;'5000
.,
. ~ .\
~.;
AIM 65/40 Microcomputer Family
'1'
Rockwell
A65/4o-2000, -3000, ':4000 and ·5000
. AIM 65/40 MICROCOMPUTER
'"
OVERVIEW
FEATURES
The AIM e5/40m~rocompUtllr integrates the AIM 65J40 . mod·
ularcompi)nerits-Single Board Computer (Sec), ~O·Chf1.racter
Displ~y .or VldeoDll!pllilY COI)~rc>I;ler (VDC)' module, G~phics
Printer, and a. Standard.or .e,xte~,ded Keyboard-;-Into a com·
plete self-contained system Inclodlng an applicatlon-oriented
VO ROM and a ROM resident operator-orlented Debug Monitor/
Text Editor. The display"and.prlnter modules are mounted onto
the SBC while. the keyboard Is detached-all peripherals are
bonnected through removable 40-conductor ribbon cable"$. The
peripherals ban easily be)'eiocaied'to other positions to satisfy
unique I~,tallation req~iremElritl!. .
• Single Board Computer with extensive memory and I/O
-6502 CPU
-131Kaddressing, in Two 65K-byte banks
-Up to 48K'bytes of on·board RAM, with write·protect
-Up to 32K'bytesof on·board PROM or ROM
-User·Prioritlzedlnterrupts, up to six levels
- User· Dedicated parallel I/O interface
- User· Dedicated 'RS'232C serial Interface
- Audio cassette/TTY (20 mA current) interface
. -RM 'S5bus expansion interface
In its inte.grated form, adesk·top Installation of theAIM:·65140
inicrCX;omputer sYlitern Clin perform a wide range Of. specialized
data acqulsltion,data·reductlon, cOntrol, and monitpr functiOns
In either OEM or end·user configurations. As a development
tool, the system can support software developed in either
assembly Or high level language. for operation In AIM 65/40 or
RM 65 b~d microcomputers at a fraction of the· cost of other
systems.
• Graphics Printer
- Text mode provides upper/lower case alphanumeiic:s. Math,
and Special Characters at 240 lines/minute
.
....,..Full graphicsrnode provid~S 280-dot resolution;'·'
-Quiet, reliable thermal operation
• 40-ChaFacter Display
-Full upper case alphanumeric and special characters
-Bright, criSp vacuum fluorescent display
-Display, edit, auto-scroll, and character blinking functions
• Full-Size Terminal·Style Standard Keyboard
-57 keys, including locking ALL CAPS key
-Eight user function keys, plus ATTN and RESET
e I/O ROM
-Auto·start initialization
....,..Interrupt·griven peripheral I/O handling
'-RAM vectdred VO with expansion hooks
-General purpose I/O and util~y subroutines
. .; ROM'Resident Interactive Debug Monitor
-Accepts instructions in mnemonic form
-Machine level debug functions
-Command file for automatic command execution
As an advanced generation of the popular AIM 65 microcom·
puter, the separate AIM 65140 assemblies provide Increased
processing throughput, Improved keyboard, display and printer
modules, and expanded application interfaces. The 6502 CPUbased AIM 65 Single Board Computer, with a full address complement of memory capacity on-board, extremely flexible VO,
and interrupt driven I/O handle.rs in firm",:,are, is the heart of the
AIM 65/40 microcomputer system. The AIM 65 Graphics Printer,.'
with its separate microc()mputer contro!ler, prints 40 columns'
of character~,.using atomplete SEit of upper and lOwer case
alphabetic, numeric, semi-gVaphi9, and special characters .in the
. text mode at 240 lines per miri\l1e, and.' alsO provides Ii full
. graphics mode of 280"dotsby rifo~S. Tna AIM65/4,O-Character
Display, with its ciwllmicrop~oc~sSor-based coptroller, feilures
an easy-to-readfluorescent display., and providesa.'fuIl complement of .lIlphanumer~ and spepialcharacters asw,ell as internal
editing; s<;rolling, arid blinking funotions. The terminal"style,AIM
65 Standafd Keyboarq:,contains a:full'5i~ main keyboClrd plus
a separate row o,f eight dedicated function keys and Isolated
RESET and ATTN k e y s . '
• RQM-Resident Text EdRor
-Line and screel) oriented CQmmands
. -Read, list, insert, delete functions
-CursOr C9lltrOI functions
~ AutomatIC: and manual. block change fl,lnctions
e.Extensive DOcumentation
-Comprehensive user's manual
-I/O ROM and Monitor/Editor assembly listings
~. -Programming and hardware manual
-Summary booklet and wall schematic
The system comes with a.4K-byte I/O ROM and an 8K·byte
interactive debug .monitor alid,!eJl,t. edjtot:,o.p~ional assembler
and common high level language eompilersiinterpreters improve
programmer productivity, increase program reliability, and simplify program maintenance. ROM-based firmware includes a
disk operating system, symbolic assembler, universally accepted
BASIC interpreter, and a highly efficient FORTH system with
resident compiler, interpreter, and macro assembler. Optional
disk-based software includes a macro assembler, BASIC compiler and FORTH target compiler.
Document No. 29000078
8-10
Data Sheet Order No. 078
Rev. 1, July 1983
A6514o-iQOO, -3000,··'-4000 $nd -5000
AIM.65/40MlcroeORlPuter
FUNCTIONALDESCRfPTION
SINGLE BOARDC?OMPUTER (SBC) MODULE
The A65/40-1 OOOSBC Module con\ains an R6502 CPl), a 1
MHz clock circuit,en·board device decoders, interrupt request
priority circuit,reset conditioning, and both PROM/ROM and
RAM memory. On-board sockets accept up to 65K 'bytes of
'read-onlyand read/write memory. Up to 32K.bytes oIP.ROM/
ROM and up to 48K bytes of RAM may be inst~lIed~ All on-board·
memory may be enabled i.n4K-byte blocks,yielding an optimal
mix of on-boardloff-board memory and I/O to bE! addressed. The
RAM may also be .write-protectE!d in BK-byle'segme.nts. Dual
bank addressing allows .anadditional 56K bytes of memory or
VO 10 be accessed off-board.
.
The SSC module is connected by removable cables to the 40Character Display and the Graphics Printer over identical Centronics type parallel handshaking interfaces.· The SSC is also
connected to the Standard Keyboard through a removable interface cable. These peripheral. ports may be also used as general
purpose bi-directional data ports with parallel, serial, interrupt,
and timer capabil~ies controlled by user programming of two onboard R6522 Versatile Interface. Adapter (VIA) devices.
A65/~5000 AIM 65/40 Microcomputer
ORDERING INFORMATION
Microcomputers
Part No.
A65/40·2000
A65/40·3000
A65/40·4000
A65/40·5000
Description
A separate user-dedicated R6522 VIA interfaces with the Paraile I I/O Connector. The high current drive capacity of the VIA's
eight "S"port lines can directly drive many industry-standard
devices, such as solid state relays. The RS~232C connector
proVides an interface that al.lows the sse to function as a data
set or data terminal. Ar:1 Auoio/TTY Connector interfaces to one
or two' audio cassette recorders and to a 20 rnA current loop.
serial·interface.
AIM 65140 SBC w~h 32K FlAM. MonHor
ROMs, Extended Keyboard. and VDC
Module
AIM 65/40 SBC with 32K RAM, Monitor
ROMs, Extended KeybOard. VDC Module &
. Graphics Printer
AIM 65/40 SSC wnh 32K RAM Monnor ROMs,
Stendard Ke¥board and 4Q Char. Display
AIM 6&/40 with 32K RAM MOn~or ROMs,
Stsndard Keyboard,40 Char. Display and
. Graphics Printer
An Expansion Connector extends the system bus to Rockwell
RM 65 bus compatible memory, I/O, or peripheral controller
modules. Up to six levels of.interrupt priority may be assigned
to on, board and off'board~dfjherals.
Firmware Options .
Part No.
A65/40·7010
A65/ 40·7020
A65/4O·704O
A65/40·7050
A65/40·7090
A65/40-7092
STANDARD KEYBOARD
Description
AIM 65/40 AssemqlerROM
AIM 65/40 BASIC Interpreter ROMs
AIM 65/40 Math Package FlOM
AIM 65/40 FORTH ROMs
AIM 65/40 Disk Operatifl9 System Version 1.,0
(DOS 1.0) ROM
AIM 65/40 Bootstrap Disk Operating System
Version 1.0 (BOOS LO) ROM
The
.. A6. 5'./. .4. 0-0.. 2.00S.'.tan.
d. K.e. y. bo
...... ard
is.1I fUI.I.'• ize contact
termin.a.1single
style
alphanumeric
keyl;loardd.ar.
containing
66 momentary
pole single throw (SPST) keys and one locking SPST key. The
keyboar'dhas a complementof63 momentaryconiact keys in
an 8 x 9 matrix with nine po$itionsu~sed. An ALL CAPS
locking key is also in this matrix. Nine strobe and eight return
lines are used to deterr:nine which key is pressed. Three
momentary contact keys..,..RESET, ATTN. lIm;JPAPER FEED
are outside of the keyboard matrix: These keysw~ches have
dedicated returns.
S.
Software Options (5'14" Disks)
Part NO;
A65/40,7012
A65/40-7024
A65/41F7052
Description
EXTENDED KEYBOAR[)
AIM 65/40 Macro Assembler and Unking
Loader(1)
.
AIM 65/40 BASIC Complier Disk(2)
AIM 65/40 FORTH Target Compiler l ')
The A65/40-0210 Extended Keyboard has the. added features
of an industry standard numeric keyboard and cursor. control
keys.
Notes:
1. Requires RM 65 FDC Module (RM65-5101E) and A65/40-7092
BobS 1.0 ROM.
2. Requires RM 65 FDC Module (RM65-5t01E) and e.ither
. A65/40·7090 DOS 1.0 or A65/40-7092 BOOS 1.0 ROM,
8-11
8
A65/4G-aOOO,-3000, -4000 and -5000
PARALLEL I/O
Rs.232C
. AIM 65/40 Microcomputer
AUDIO/TTY
EXpA,NStoN
r-__~____-t~O:N:~:C~ro==R~~::i'){CO=N:N~'~Cro==R:~:'~)________-[CO:N=N:E=cro==R~(n~)____~__~CO:N:N:E:cro~R~~:4~)__~~~__~-,
A65140-1ooo
sac MODULE
PRINTER
CONNEcroR (J5)
'-r--""""
A65/40-0600
GRAPHICS
PRINTER
A~/40-0200
STANDARD KEYBOARD
OR A65{40-0210
EXTENDED KEYBOARD
A65/40-04oo
4O-CHAR. DISPLAY
OR A65/40-0800
VIDEO DISPLAY
CONTROLLER
MODULI!:
AIM 65/40 System Block Diagram
8-12
A65/4~2000, -3000r~4000 and -5000
!
AIM: 65t40tMi<:rocompuwr
GRAPHICS PRINTER
1/0 ROM
The A65/4D-D6DD Graphics Printer inclu{ll!~ a dot matrix thermal
printer mechanism, ~. microcomputer cOiitroller, thermal head
drivers, and motor/strobe timing circuitry.
.
The
ROM includes preprogrammed auto-start in"ltialization,
interrupt, input/output and utility functions which support userdefined programs as well .as AIM 65140. optional firmware/Software, Autq-start. initializatiOn Jumps to; predetermined PROM!
ROM aeldresses during RSSET processing. The application pre)gram can· assume direct eontrol of the. system for continued
operation, or it can. just initiaUze required functions, then return
Cqfltrol back to the
ROM for cQhtinued. auto-start of other
functions .. '
. .
".
The printer mechaniSl)1 includes a thermal head, platen,motor
drive linkage, and associated wiring. There are 40 thenna\ elements on the thennal head, each of which spans Seven' dot
fields; each eleiTIent. is a disCrete point whiCb rides against heat
sensitive paper. Control logic tur.n$~.ihe t\1ermal he8d drivers
to heat the sensitized paper when Ii Qat is to be, printed. During
a print cycle, the thermal head moVes horizontally acroSs' the
paper; when an entire row of dots has been printed; the prin.ter
motor advances the platen by one horizontal row of dots.
The printer controller includes an R6504 CPU, 4K'bYte ROM,
RAM, I/O, timer, clock, and reset circuitry. The ROM contains
both the CPU instructions and the ind.ividual ch.l!racterbit patterns. ThE! control,ler perfonns printepliptor and thermal head
timing and control functiOns to' enable ~he printer 10 operate
independently fr().m the sac module.
Data and control commands are transmjtted to the printer over
the Centronics type parallel handshake interface; An internal
buffer accepts up to 80 bytes for printing. The controller automatically prints the first 40. 7 x 8 dot-matrilC characters in the text
mode or after receiving a
of 280. dots in the graphics mode.
The paper can also ~e advanced with a'pape" feed command,
or manually using the paper feed SWitCh.
row
va
Va
I/O dri;,ers directly support AIM 65/40.. intelligent display and
. printer" peripherals. Other drivers support the RS-232C/TTY
. interfac~, the audio cassette ports 'gnel·'control the on-board
"
speaker.
DEBUG MONITORJrEXT EDITOR
The Debug Monitor/Text Editor includeS awlde selectiOn of functions to simplify computerpr6gram entry·and checkout. fe~ can
.be easily entered, edited, saved, and retrieved using either line
or screen oriented commandJl in the reX(Editor. A character
cursor can be positioned left,. right,up, or down to aid character
insertion, addition, and deletiOn. Automatic and selective character string change capability makes block· changes as desired.
Multiple text buffers can easily be maiillilined for separate program .and data files.
The Debug Monitor controls program exeCution in single' step
and run mOdes and 'allows Convenient examination arid' altl'lrinQ
of memory andregisters.$ingle steP.operation allows instruction and register trace for detail examinatiQn of executed. instructions. Syri1bollevel debugging reduces dependence on absolute
',.",
addresses and simplifies program checkout.
4C).CHARACTER DISPLAY
\ , '
",
The A65/4D-D400 4O-Character Display.contains a vacuum fluorescent display/a microprocessor-based controller, a 2K~byte
character fQl'lt/program ROM, character.and Segment driVers,
and a DC/DC power converter. The vacllum fluorescent display
is a single 'sealed unit containing 4D'separately coritroll~ble
digits. Eaehdigit is composed of .a 16-~!!~rnent font which a!lows
a full set of upper case .alphabetlcs, n~ffi~r.ics, and special characters to be displayecj.ln the semi-grapnics mode, the 16 segments of each digit are individuallycontr9l1ed.ln addition, each
digit includes a separate decimal point. When energized, the
digits form bright, crisp characters in a,blu,e-green color.
VIDEO DISPLAY CONTROLLER (VDC) MODULE
The A65/4D-D8DD Video Display Controller (VDC) modUle interfaces the AIM 65140. microcomputer. to either a CRT monitor or
TV receiver. The module connects to the AIM 65/40. sac module
display connector (J5) and interlaCes'to the display through
either the composite video output or· the separate' HSYNC,
VSYNC, and VIDEO output. TTL COmpatible signals. With its
integral microcomputer controller; bjJiIt-in commands provide
selectable and programmable screen formatting, flexible text
handling and editing, and full graphics drawing and data display
functions. In the text mode, preprogrammed fonnats of 80. chal"
acters x 24 lines or 40 characters x 24 lines are selectable.
ather formats are user programmable. The full graphics r'liode
incorporates bit mapping of 280. x 224 pixels, which is compat~
ible with the Graphics.Printer.
'8-13
A65/4o-2000, ..aooo, ~4000 and -5000
": AIM $5/40; Microcomputer
'LoadlDump Memory
DeBUG MONITORCOMNJANDS
Monitor Control Commands
l'
'Enter,andoinitialize,!I.1onijpr (C~ld Reset)
EnletMonMor (Warm,Reset)
Non~Maskable Inten;u,p,t '
escape to MO/1~Or Gomm'and Level
Initialize TeXt Buffer and E:nte(reXt Editor
E
'I " '
, Recover Text Bulfer ~rid, Eriier TeXt Editor
Reenter TSxt Editdr '
T
F1 - F8
Enter FunctiOn 1 - Function B
Repeat t.ast Command
+
ElieCufe 'Command String
&
, TQQgleMemory Bank,
Oirect':Periphe,ral,CO!lirol
CTRlZ
,
CTRlZCTRlZ
SBC'Module RAM Self Test
CTRlC
Clear Display And Home Cursor
CTRlN
Home Qwsor
D
CTRl RESET
RESET
ATTN
ESC
F
Peripheral Control
OTRlP
'PRINT
6
1
2
3
a
i>
F1 (or CTRl Q) , Home Cursor on Line
F2 (or orRl R)
Clear Line to Right
F3(o~ CTRl S)
Toggle Insert Mod", O,nlOf.!
F4 (or CTRl 1)
Deleje Character Und,er Cursor,
F5 (or CrRL U). ' Move C~rsor ,Left (Left Arrow)
1"6 (or CTRl V) Mqve Cursor Right (Right Arrow)
F7 (or CTRl wj Move Line/Cursor Down (Down Arr<;Jw)
Move linefcursor Up (Up Arrow) ,',' '
F8 (or CTRl X)
CTRlA
Add (Insert) a Line
'
CTRlB'
BreaK a Line
ClRlD
,Delete !l line
S
X
:Y'
Di~Ja¥ ~egi~t~r C~nte';ts
Oi!iplaYlA~er Accumulator
, 6is/Jlay/Ah~r: Prdeessor Status
'DiSpiay/Mer$i'acK Pointer
""', "bisplay/Alter'X Register
':;, 'DisP'aYrAl(eI"'YHegiSler:,;
DisP!itY/Alter',PTogram Caunter,"
..
~':'
TEXT EOITOR,COMMANDS
DisplaylAlter Memory
'"
M
,SPACE
/'
II",..
Toggle Auto-Print On/9ff
Prini DisPlaY cpntents
Toggle'ReCj;lrder 1 Control On/Off
Toggle ReCOi"tler 2 Control On/Oil
WrijY Tapti Checksum
Screen Orlentec:t:Commands
Di1ilPlaylAlte~ RegistElrs""
R,
A'
Load'Memory
Dump Memory
Verify Memory
Editor Control Cqmmands
,
DisPlay Selected Memory Contents, ,
QisplaYHigher Memory locations
Display .Lower'MeIT\Ory Locations
Mer Current Memory Contents
S
Q
ESC
+
Enter Screen Edit Mode
Quit Editor and Enter Monitor ,
Return to Editor Command Level
Repeat Last Command
Clear Display and Home Cursor
Home Cursor
EnterlDisassemble Instructions,
CTRlC
CTRlN
I
Lin!! Orient~' Com,nands
K
Enter Mnemonic Instruction
Disassemble Memory
Enter Symbolic Address
l
R
I
Execution/Trace
G
.z
J
H
V
a
Execute Program
Toggle Instruction Trace
Display Register Heading
Display Jump and Branch History
Toggle Symbol Table On/Off
.1(
(SPACE)
?
G
U
D,
Breakpoint Manipulation
?
#
4
B
J
B
Display Breakpoints
Clear Breakpoints
Toggle Breakpoint Enable OnlOff
Set Breakpoint
F7(or qRlW)
FB (or CTRl X)
8-14
List Multiple Lines
Muniple Liil~s
rnsert One Line
Overlay Current Line
Delete Multiple Lines
Djsplay Current line'
Display Current and Last Line Addresses
GO to Line NumberGo up Multiple Lines
Go down Multiple Lines
Go to Top Line
Go to Bottom I,.ine
, Go Down One Lin!;)
Go Up One Lin~
Fiehd
A65/4G-2000, -3000, .. 4000 and -5000
FFFFr-----~~~~~~-----,
AIM 65/40
AIM 65/40
110 ROM(l}
FOO0
F~~_ _ _ _I/_O_R_O_M_(l_}_ _ _ _~
BASIC
coo0
J
0000
I-
9000
I-
8000
8000
f-~
7000
7000 I-
AIM 65/40
ASSEMBLER ROM
f-
6000
5000
~.
PROMIROM
EXPANSION
(28K)
USER AVAILABLE
f-
4000
3000
3000
800 a
-
RAM
EXPANSION
(32K)
USER AVAILABLE
0 __
~
800
OPTIONAL LANGUAGES (3)
RM 65 RAM (3) -
o ~. o r-- 20
o~ 10
-
MOiiiTORRAM(2} -
-
6502 SrAcK- -
-
o '-- -PAGE ZERO DATA
16K
-~
400a
1000
50
PROM/ROM
DEDICATED TO
BANK 0 OR
CQMMONTO
BOTH BANKS
(20K)
16K
2000
2000
RAM
COMMON TO
BOTH BANKS
(4K)
-t
cooa
5000
4000
60o
12K
BOoo
AOOO
60 00
1
FOoo
OPTIONAL AIM 65/40
HIGH LEVEL LAN1GUAGE ROMo(3}
BASIC
FORTH
C000r-_ _ _ _~_ _ _ _ _~
FORTH
AOO 0
9000
4K
EOOOr-_ _ _B_DO_S_'_.OrR_O_M_(_4)_ _ _
AIM65/40
DEBUG/MONITOR
& TEXT EDITOR ROMs (2)
BOO0
I/O ROM(l}
-1
BOOS 1.0 ROM (4)
OPT'ONAL AIM 65/40
HIGH LEVEL LANGUAGE ROMs (3)
0000
-.-
FFFF
AIM 65/40
AiM 65{40
EO00
ON-BOARD·
PROMIROM & RAM
RUN-TIME MODE
DEVELOPMENT MODE
FFF F
AIM 65/40 Microcomputer
RAM
(16K)
---
12K
-~
1
1
4K
-Notes
(1) AIM t\S/40 System pedpheral 110 addresses are assigned ,to
FFSO-FFDF
(2) User available during application program operatIon If the debug
and text editor functions are not used
(3) User available If the optional language and the AM 65 expansion
module ROMs are not used
(4) Requires AM65-S101E Floppy Disk Controller (FOC) module
(S) 56K bytes oj RAM (0 - $DFFF) IS available for disk-based
assembler:compllers and user programs. I/O ROM and BOOS 1,0
ROM require 8K bytes (SEOOO-$FFFF)
AIM 65/40
sec
Memory Map
8-15
RAM
DEDICATED TO
BANK 0 OR
COMMON TO
BOTH BANKS
(44K)
ROM & I/O
COMMON TO
BOTH BANKS
(4K)
AIM 65/40 Microcomputer
A65/4o-.2000, -3000, -4000 and -5000
sec
Pin
Slgnlll
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
CB2
CBl
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PBO
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO
CA2
CA1
Module Connector J1 (Parallel Application) Pin Assignments
I/O
'.
Type
va
va
Va
va
va
va
va
va
va,
va
va
I/O
VO
va
VO
Va
VO
va
Va
;
I
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
Note: 'Pins 2 and 40·can be optiorillily jumperedto +5V{maximum
Pin
I
1
3
5
7
9
11
13
15
17
19
21
23
25
Signal
I/O
GND
AD
CTS
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
I
VO.
Type
'Power
RS-232C
RS'232C
Power
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
24
~ND
'
"
NCf+5V"
Power
Power
Power
Power
Power
Power
Power
Power
POWer
Power
Power
Power
Power
.Power
Power
Power
Power
Power
Power
Power
curre~t through each pin should not exeeed200 rnA),
sec Module Connector J3
(Audio/TTY) Pin Assignments
Signal
I/O
Type
Pin
Signlll
a
RS-232C
RS-232C
RS-232C
RS-232C
1
3
5
7
9
11
13
15
17
19
TTY RTS
TrYTD
. TrY RD
TrY RTN
AUDIO OUT
AUDIO IN
CTRL2 RTN·
CTRL2
CTRL 1 RTN
CTRL1
va
..
GND
GND
GND
TO
RTS
DSR
DCD
NC
NC
NC
NC
NC
DTR
NC
NC
va
va
va
Type
NC/+5V"
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
26
28
30
32
34
36
38
40
sec Module Connector J2
(Serial Application) Pin Assignment
Pi"
Slgnlll
2
4
6
8
10
12
14
16 ..
18
20
22
RS-232C
NC
8-16
Type
Pin
I
TTY
O· TrY
I
Power
I
TTL
TTL
Relay
I
Relay
Relay
Relay
I
2
4
6
8
10
12
14
16
18
20
I/O
TTY
a
a
a
Slgnlll
Type
GND
Power
Power
GND
GND
Power
GND
Power
GND
Power
Power
GND
GND ". Power
GND
Power
GND
Power
GND
Power
A65f4o..2000, 4000, .. 4000 and .5000
-"
SBC Module Connectot
, , 65 BU$)PII'I AsSignments
,. J4 {RM
: ...
," "Signal
Pin, ,Mnemorllc
Wil
(
, Xa:
18,1
2a
,
3~
4a
5a
Sa
78
+5V,
GND
'BADRI
GND ,:
'BA1S1,
ErAl1/
BA1~
BAsi
~ND ,
9a: BA5/ '
lOa: BASI
lla B'A2! '
12a BAO!
13a GND
148 BSO
15a' BRDY,
16a
17& +12V/+V
,
18a GND"
ea"
,
19a BDMT/
20a
21a BRiWI
22a
23a GND
24a BIROI
258 B¢2/
26a B_2
27a BD71
26a ,GND
29a BD4I
30a BD2I
31a BOll
328 +5V
Va +5V
Za
"
",
",
Bottom (Solder Side)
Signal
Mnemonic
.,,-
Signal~ame
l/Ci
TYpe
-
Not Connected
+'5 Vdc Line (See Nott;)
Ground
Buffered ~ank Address,
Ground
Buffered Address B~ 13
Buffered Addre$S Bit 11
'Buffere'd Addre$ Elit 10
Buffered Address Bit B
Ground
Buffered ~dress Bit 5
Buffered Address B~ 3
Buffered Address Bit 2
Buffered Address B~ 0
Ground
Buffered Set Overflow
Buffered Ready
'User Spare 1
'+12 Vdc/+V
Ground Line
"Buffered DMA Terminate
"User Spare 3
Buffered Read/Write "Not"
"System Spare
Ground
Buffered Interrupt Request
Buffered Phase 2 "Not" Clock
Buffered Phase 2 Clock
Buffered Data Bit 7
Ground
Buffered· Data Bit 4
Buffered Data BH 2
Buffered Data Bit 1
+5Vdc'
•
+5 Vdc (See Note)
Not Conr:1ected
, Nola: 'Not used on ,the SBC, Signal name
TC!P
0
,
0'
0
0
0
0
0
0
0
I
I
Power
Power
3STTL
Power
3STTL
3STTL
3STTL
3STTL
Power
3STTL
3STTL
3STTL
3STTL
Power
OCt.TL
OCTtL
Power
0
I
0
0
VO
1/0
I/O
110
3STTL
Power
OCTTL
3STTL
3STTL
3STTL
Power
3STTL
3STTL
3STTL
Power
Power,
-
Pin
Wc
Xc
lc
2c
30
40
SC
+5V
+5V
BAl51
BAl4/
BAl21
GND
BA9/
BA71
BASI
BA4/
GND
BA1/
B¢1
BSYNC
BDR01/
GND
-12V/-V
Sc
7c
6c
9c
10c
llc
12c
130
140
15e
16c
17c
16c BFLTI. ,
190
20c GND
21e BDR02/
22c BR/IN
230 BACTI
240 BNMV
25c GND
2Sc BRES!
27c BD61
26c BD51
29c BD3/
30c GND
31e 'BDOI
32c GND
Yc +5V
epo
ZC
r~ftectsRM 65 Bus reserved function.
'I"
'8-17
(~omp~nent $Ide)
Sili!nal"Nlime
Not Connected
+5 Vdc(See Note)
+5 VClb
Buffered Address B~ 15
Suffered Address B~ 14
,Buffered Ad~ress B~ 12"
Ground;'
'
Buffered Address Bit 9
Buffer~~ Address Bit 7
Buffered Address Bit 6
Buffered Ad\lress Bit 4
,
Ground
Buffered Address Bit 1
Buffered Phase 1 Clock
Buffered Sync
'Buffered DMA Request 1
, Ground
-12 Vdc/-V
'l,JserSpare 2
euffered Bus Float
,"Buffered External Phase 0 Clock
Ground'
'Buffered DMA Request 2
Buffered Rsad/Write
Buffered Bus Active
Buffered Non·Maskable Interrupt
Ground
Buffered Reset
Buffered Data Bit S
Buffered Data Bit 5
Buffered Data Bit 3
Ground,
Buffered bata Bit
Ground
-+;5 Vdc (See Note)
Not Connected
ci
:
I/O
Typa
-
0
0
0
0
0
0
0
0
0
Power
Power
3STTL
3STTL
~STTL
3STTL
3STTL
3STTL
3STTL
3STTt::
POWer
3STTL
TPTTL
3STTL
Power
I
OCTTL
Power
0
I
I
0
VO
VO
I/O
VO
3S TTL,
OC,TTL
OCTTL
Power
OCTTL
3STTL
3STTL
3STTL
POwer
3STTL
PoWer'
Power
-
AIM 65/40 Microcomputer
A65/4G-2000; -3000,,..4J000 and -5000
sec
Module Connector J5
116522
PIn.
. 1 (1)
3
5
7.
9
11
13
16
17
19
21
23
25
27
29
31
33
35
37
39
Notes:
Signal
+5V
NC
NC
NC
NC
NC
NC
PAPER FEED (2)
RES '
Printer
1/0
0
0
PB1
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO
liO
CA2
I/O
110
I/O
110
I/.O
110
I/O
I/O
I/O
!llgnal
,
+5V
NC
NC
NC
NC
NC
NC
f&ER FEED (2)
RES
STROBE
Data 7
Data 6
DataS
Data 4
Data 3
Data 2
Data 1
Data 0
NC
Pin
Signal
1 (1)
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
+5V
NC
NC
NC
NC
NC
NC
PAPER FEED (2)
I
1/0
'Type
Pin
0
Power
2,
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40 (1)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+5V
Type
Pin
Signal
Type
Power
2
4'
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GNp
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+5V
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
-
0
0
0
0
0
0
0
0
-0
0
TTL
TTL
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
I
NMOS
(t) Maximum +5V current through J5 shQuld not exceed 200 mA per pin.
(2) Connected 10 J7-39 through jumper W3.
sec
Pin Assignments
'.
ACK
-
Signal
GND
GND
GND
GND
GND
GND
GND
~ND
Type
,
Printer
1/0
+5V
NC
NC
NC
NC
NC
NC
PAPER FEED (2)
RES
REs
flO
VO
VO
VO
35
PBO
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO
37
39
CB2
VO
I/O
VO
110
I/O
1/0
1/0
Signal
.'
-
-
-
0
0
0
0
0
0
TTL
TTL
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
I
NMOS
0
0
0
0
S'i'Rc5BE
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
NC
ACK
0
(1) Maximum +5V current through J6 should not exceed 200 mA per pin.
(2) Connected to J7 -39 through jumper W3,
8-18
-
"',
Po:-ver
Power
Power
PoV{er
POWer
power
Power
Power
Pows,
power'
Power
Power
Pqwer
Power
Power
Power
Power.
Power
Power.
Power
Module Connector J6 (Display) Pin Assignments
R6522
Notes:
(Print~)
"
.
!
A65/4Qo.2000,-3000, -4000 and -5000
AIM 65/40 Microcomputer
SBC Module Connector J7 (Keyboard) Pin Assignments
R8522
Keyboard
Pin
Signal
1/0
1 (2)
3 (3)
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39 (4j
CB2
CBl
PB7
PB6
PB5
PB4
PB3
PB2
PBl
PBO
PA7
PA6
PA5
PA4
PA3
PA2
PAl
PAO
CA2
CAl
I/O
I/O
Notes:
(1)
(2)
(3)
(4)
110
I/O
I/O
I/O
110
I/O
1/0
I/O
I/O
I/O
I/O
1/0
110
I/O
1/0
1/0
I/O
I
Signal
RES
A'iTN
MSB7
MSB6
MSB5
MSB4
MSB3
MSB2
MSBI
MSBO
MRT7
MRT6
MRT5
MRT4
MRT3
MRT2
MRTI
MRTO
MSB8
PAPER FEED
I/O
Type
Pin
Signel
Type
I
I
TTL
TTL
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
2 (1)
4
6
NC/+5V
GND
GND
GND
GND
GND
GND
GND
GND
GND,
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC/+5V
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
0
0
0
0
0
0
0
0
I
I
I
I
I
I
I
I
I
I
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40 (1)
Pins 2 and 40 ean be optionally jumpered to +5V (maXimum current through each pin should not exceed 200 mAl.
Pin lean be optionally jumpered to the RESET circuit or to CB2.
Pin 3 ean be optionally jumpered to the NMI circuit or to CB1.
Pin 39 can be optionally jumpered as PAPER FEED or to CA1,
.NMOS INTERFACE (Input Voltage
Symbol
=+S.OV, TA =
25°C)
Min
Max
V IH
Input 'High Voltage
2.4
5.0
V
VIL
Input Lolv Voltage
-0.3
+0.4
V
IIH
Input High Current
(VIH ; 2.4V)
-100
-300
f'A
IlL
Input Low Current
(V IL ; 0.4A)
-1.0
-1.6
mA
VOH
Output High Voltage
(lLOAO ,,", -100A)
2.4
5.0
VOL
Output Low Voltage
(I LOAO "" -3 mAl
-
0.4
10H
IOL
TTL
DC TTL -
Paramater
V
V
.
Output High Curren! (Sourcing)
(VOH ;;. 2.4V)
(VOH ;;. 1.5V. VIA PBD-PB7 only)
Output Low Current (Sinking)
(VOL"" O.4V)
Industry standard LS TTL
Industry standard Open Collector LS TTL,
Unit
3S TTL TP TTL -
8-19
-100
-1.0
-
-
f'A
mA
1.6
-
mA
Industry standard Tri-stilte LS TTL.
I ndustry standard Totem Pole LS TTL.
AIM 65/40 MicrocomplJter
A65/40-2000, -3000, -4000 and -5000
SPECIFICATIONS
Parameter
Value
<
Dimensions
Width
Length{')
Height (2 )
11.85 in. (301 mm)
19.75 in. (502 mm)
4.6 in. (117 mm)
Shipping
Size
Weight
12.5 in. (320 mm) x 16.5 in. (420 mm) x 15 in. (385 mm)
13.3 lb .. (6 kg)
Weight
With Printer
without Printer
4 lb. 4 oz. (1.5.8 kg)
3 lb. 4 oz. (1.21 kg)
Environment
Operating Temperature
With Printer
Without Printer
Storage Temperature
With Printer
Without Printer
Relative Humidity
Power Requirements
With Printer
Without Printer
Interface Connector
Jl (Parallel Application)
O°C to 50°C
O°C to 700C
O°C to 70'C
-25'C to 85'C
0% to 85% (without condensation)
+5V ±5% reglJlated @ 2.6A(typ); 3.4A (max.); 3.4A(peak)13)
+24V (+3.6V, -2.6V) unregulated@ 2.5A (typ); 4.0A(max.); 6.3A (peak)(4)
+5V ±5% regulated @ 1.8A (typ); 2.4A (max); 2.4A (pSllk)131
40-pin edge connector (0.100 in. centers). Pre-drilled holes for installation of
40-pin 3M #3432-1002, or equivalent, mass terminated connector.
J2 (Serial Application)
26-pin edge connector (0.100 in. centers). Pre-drilled holes for installation of
25-pin AMP #206584-1, or equivalent, mass terminated connector.
J3 (Audio/TTY)
20-pin edge connector (0.100 in. centers). Pre-drilled holes for installation of
20-pin 3M #3492-1002, or equivalent, mass terminated connector.
J4 (RM 65 Expansion)
72-pin edge connector (0.100 in. centers). Pre-drilled holes for installation of
a 64-pin DIN 41612 Euroconnector or 72-pin TI H42-51-11-36, or equivalent,
connector to directly mate to one Rockwell RM 65 module.
J7 (Keyboard)
40-pin 3M #3495-1002, or equivalent. Mates
equivalent, ribbon cable connector.
J5 (Printer) and
J6 (Keyboard)
40-pin 3M #3495-2002, or equivalent. Mates with 3M #3418-0000T, or
equivalent, ribbon cable connector.
w~h
3M #3418-0000T, or
Notes:
1. Specified for 2 in. separation between keyboard and sse modules. The length may be reduced if keyboard and sse modules are overlapped/
canted or may be extended by installation of a longer interface cable. A cable up to four ·feet in length may be installed.
2. Specified for the printer mounted to the SBe module on 1 in. standoffs. The printer may be mounted up to 2.5 in. above the sse module using
the installed 3 in. cable or may be installed )0 operate with a cable up to four feet in length.
3. Power requirements are specified for 8 PROM/ROM devices (32K bytes) 0.6A (typical) and 1.2A (maximum) total, and for 16 RAM devices
(32K bytes) with 0.9A (typical) and 1.7A (maximum) total, installed.
•
4. +24V peak current specified as worst case with printer duty cycle of 75%. For most cases, a +24V 4A p6wer supply is sufficient.
8-20
I
A65/4~2000, -3000, ~4000, -5000
REFEREN,CEDOCUMENTS
AIM 65/40 Micrcu~c)rnputer
,
The following product literature is available for furtherpr~duct
tnfonT\ati~.
.
.
.
"
..
Order Munfile,r
074
076
075
086
077
0123
0128
0120
0118
0130
0122
0119
01'16
0129
..
,
'
Document Title
.:;
,
"
A65140-0200, A65140-0210 Standard
and Extended Keyboard Data Sheet
A65140-0400 40-Character Display Oat,a
Sheet
' :, ~
A65140,o600 Graphic Printer Data
Sheet
A65140'0800 Video Display Cbntrolier
MOdule Data Sheet
A65140-1000 Single Board,Qomputer
Module Data Sheet
A65140-7010 Assembler ROM
A65140-7012 Macro Assembler and
Linking Loader
Ai55140-7020 BASIC Interpreter ROMs
A65I40-7024 BASIC Compiler "
A65140-7040 Math Package ROMs
A6S140-70S0 FORTH ROMs
A65140-70S2, FORTH Target Compiler
A6SI40-7090 Disk Operating System
Version 1.0 ROM
A65140,7092 Bootstrap Disk Operating
SY,stem Version 1,0 RO~,
',.;
,
,
'
nil
':u
···.t.
8-21
A65/40~100.0
AIM 65/4{) Microcomputer Family
'1'
Rockwell
A65/40-1000
AIM 65/40 SINGLE BOARD COMPUTE.R
OVERVIEW
FEATURES
The A65/40-1000 §ingle Board Computer (SBC) is one of the
hardware options available for· the AIM 65/40. Microcomputer
family.
• Popular arid Powerful 6502 CPU
• . Extensive On-Board Memory
-Up to 48K bytes of RAM, with write-protect
-up to 32K bytes of PROM or ROM
• Extended and Flexible Addressing
-131 K addressing, in two 65K-byte banks
-Dedicated or shared bank addressing
-On.board/off-board. memory .select
• User'Prioritized InterruptSr-Up to six levels
~ Installed I/O Driver BOM
-Interrupt driven AIM 65/40 pefipherall/O handlers
- User program auto-start initialization .•
~Utility subroutines:and user I/O. driver linkage
• Two System Display/Printer Connectors
-Centronics type parallel handshake
-AIM 65/40 4O-character display compatible
-'AIM 65/40 graphics printer compatible
• Full-Size Keyboard Interface
-General purpose parallel interface
-AIM 65/40 keyboard compatible
• Parallel Application Interface
-R6522 Versatile Interface Adapter (VIA)
- Two 8-bit parallel bidirectional data ports
- Two 2-bit handshake control ports
- Two programmable 16-bit counter/timers
-8-bit serial interface
• RS-2.32C serial Application Interface
-R6551 Asynchronous Communications Interface Adapter
(ACIA) with programmable data rate to 19,200'baud
-Configurable as data set or data terminal
• 20 mA Current Loop Serial Interface
• Interface to Low Cost Audio Cassette Recorders
- Remote on/off control through on-board relays
-AIM 65 format compatible
The SBC is an extremely flexible and adaptable microcomputer .
on a single board. Memory sockets accept up to 65K bytes of
read-only and read/write memory on the board. Three installed
peripheral ribbon cable connectors,. as well as three user dedicated application ~dge con nectors, provide extensive and versatile parallel and serial interfaces for use in industrial, scientific
and educational installations. The RM 65 Bus compatible expansion connedotallows additional memory, liD, peripheral controller and application modules to be easily connected.
Up to 321<; bytes of PROM/RQM and up to 48K. bytes of RAM
mi:lY be installed on-board. All oo-board memoryrnay .be enabled in 4K-byte blocks, yielding.an optimi:ll mix of on-board/offboard memory and I/O to be addressed. The RAM may also be
writi!·protected in 81<;-byte segments. Dual bank addressing
allows an additional56K bytes of memory or 110 to be accessed
off-board.
The display and printer interfaces connect through interface
cables to the A65/40-0400 40-Character Display and the
A65/40-0600 Graphics Printer over identical Centronics type
parallel handshaking interfaces. The keyboard interface connects to the A65/40-D200 Standard Keyboard through an intet~
face cable. These peripheral ports may be. used as general
purpose bidirectional dala porfs with paraliel, serial, interrupt
and timer capabilities controlled by user programming of two on. board R6522 Versatile Interface Adapter (VIA) devices.
In addition, a separate· user-dedicated R6522 VIA interfaces
with the Parallel Application connector. The high current drive
capacitY of the VIA's eight "B" port lines can directly drive many
industry-standard devices, such as solid state relays. The
RS·232C Connector provides an interface that allows the SBC
to function asa data set .or data terminal. An Audio/TTY.Connector can be used to attach one or two audio cassette recorders,
for program or data storage, and a 20 mA current loop
teletypewriter.
• On-Board Piezo-Electric Speaker
- Programmable tone and duration
Tile AB5/40-1 000 SBC comes with a 4K-byte I/O ROM installed.
Preprogrammed auto-start initialization, interrupt, input/output
and utility functions support user-defined programs as well as
AIM 65/40 optional firmware/software. Auto-start initialization
jumps 10 predetermined PROM/ROM addresses during RESET
processing. The application program can assume direct control
of the SBC for continued operation, or it canjust initialize required
functions, then return control back to the I/O ROM for Continued
auto-start of other functions. I/O drivers directly support AIM
65/40 intelligent display and printer peripherals.
Document No. 29000077
• +5VOperation
8-22
Data Sheet Order No. 077
Rev. 1, August 1983
A65/40~1000
',,,
,
SingleBoajjtCotnpuler
,
Cont~'CitciJri~y
·FUNCTIONAL DESCRIPTION . .
CENl'.RAL PROCE;SSING
ANI).CQt1ITROL
".'. "
",
·The A65/40-1000,SBC containsa c~ntral processing l!nit (C",U),
. decoders; read/write memory, read-only memory, peripheral
interface devices, application interface circuits, expansion' bus
drillers :!lnd suppart circuitry-al~ connected together by an
internal system bus.
1/0 HARDWARE .
The.R6502 CPU, with its advanced pipeline architecture a.nd 13
... addressing modes .for .fast execUtion and memoryeffidierw;y,
performs·the centralprocessing.,A1 MHz system operatingfrlilquerey is derived from. a' clock circuit employing a16 MHz reference orystal.
'"
'.
' 0 "
..
Two system R6.522 VIA devices supp(lrt three peripheral partS..;..;
displaY, printer and keybOard. Common 110 data IiAes and Separate.Controllhles are routed from the System VIA to the DljlPlay
and Printer Connectors. B.oih common or .unique data:~n easilY
be transfElrredthroU{jh thE!" System VIA to .the ilitElrfElCilhg perlPh~
erats,since the handshaking control lines are sepEirately' han~
died. The System VIA also controls data transferrec;l to an"cffrOm
audio cassettE! recorders as well
on-bOard relaysto.remotely
turn the recorl:!ers on and off. Each VIA provides two 16-bit
timer/count$rsanl:! an 8-bit seriSlshift register.
.
The BESET conditioning circuit. shapes the. RESET signal
received.from the on-bOard RESET SWitch or the KeybOard ConnectQrand generates tl)e system reset (i'iEs)for the CPU, onbOard 1I0dllvices,.the off-bOard peripherals.andthe expansion
bus. It also generates the RES .signal at power turn-on.
~';
~dit¥ess
The RAM Retreshand Timing
cOntrols
arid data timlnt:(for RAM memory a(;eess, and provides !rans~·
parent refreshing of' the dynamic HAM devices. -\i'(tite :p~tect
switches allow the RAM to be selected for read~nlf·acCess,
with inl:lependent protectian of8K byte sections (eJlcept for the
lowesl8K whiCh contains page 0 and page 1)~ An attempted
write .into any protected RAM location will generate a write prOtect interrupt request (IFIO).
..
as
.
The. Single Step Cirouit, enabled under software cOntrol, allows
CPU monitored single .instroction execution through user pro~
grams located beloW $AOOO. When enablel:!, a Non-Maskable
Interrupt (NiJI) is generated upon execution Of each instruction
.to allow an interrupt subroutine toperformdebugfunclions, such
"as disassembly of the instruction display of register Contents.
A separate R6522 VIA interfaces with the Keyboard ConneCtor
and the an-bOard speaker amplifier, Nine keybOard strobe lines
are output from the keybO!lrd VIA'to the keybOard and another'
eight retum liries are'input. The eight return linesarealsoor'ed
together and connected to the VIA to cau~· a keybOard ·IRO
when a key is depressed:
.
The Interrupt Request Priority circuitry prioritizes indivjdual
interrupt requests (lRO) from six sources-the System R6522
VIA, the Keyboard R6522 VIA, the Application R6522 VIA, .the
i~PP"t:atiOn R.6551 ACIA, the RM 65 Bus, and the on-board RAM
,~riteProteci circuitry-lnto a ~yStem IRQ. Each
can be.
'assignel:! any priority relative to the others by wiring the Interrupt
.flequest PriOrity Header. The Irjterropt RequEist Priority Mask
:~hibits gener!ltion of the SystemiRQ" to the CPU for individual
.interrupt,requests assigned bl!la~. a software selected priority
",level..
The third R6522 VIA is dedicated to user functions. All 16 data
and 4 control lines are routed directly to the Parallel Application
Connector. The Application VIA provides two 8-bit bidirectional
data ports with handshake control and aUowsthe data direction:
of each port bitta be individually asSigned. One oft~data lines
may be configured as a ~rialline to ari a.,.bit M,iftregisterwith'
thre~ input and four output modes. Two indepen~nt 16~bit··
timer/Counters in:the R6522 with 'four modes it. Timer 1 and,
three modes In Timer 2 support numerous intern.aI a~d eX\!ilmal
timing' and clock fonctiQntt TwO. data portsassoc~~ with the l
.timers. allow v!ilrio+-!~ input/outpUt functions to be ~r~!lrammed' .'
such as rectangular wave form generation and sai11P1ing.:
:{
and
iRa
·The On-board Device Decoder IIElnerates device select signals
tor all on-bOard RAM, ROM or VQac~ss. The PROM/ROM and
·ijAM select swit~s allow .independent on-bOard/off~bOard
Selectiot)6f. ~~h «-byte block.
..
.
.
"
e.dser.ia.I.... ..
In
ad•.dilion.is t.o.prOVided
'. \118. para.
interface.·s;
use..r20.
d.e.m~
d.·. iea
•. ·.·.·i:rorm~.
interfaCe
inlie.,.
bOth
RS-232Ca and
Art·
R6551 Asynchronous. C6r1'1!11unication Interface Adapter (ACIA)
deviCe'cOl1n~to AS·232C and 20 mA current IQbp intEirfll98 ...
circuits. On-bO~ jumpers cOnfigure the R6551 ACI~ to operate"
as e~l)e"r a da~a ~t or a data ~$rmin,al. The Re!i!?~.ACIA, with ..
its inr$rnal data rate generator;.may,be programrr!i:KftoO/1$:of, "
the
~a(es (from50to 19,2Dqbaud). Additional~j;iram controlohYord ler'lgtH (5; 6, 7 or 8 "bits), nlimber of sto,,'\)its (1; 1112 "
Or 2)
parity (odd, even or none) is also provided.
... .
"
·Programmab1e.Baflk·. Ad"ressing creates two 65K-byt~' banks,
.~r an effectiVe addressing range of 131K.bytes wit/1 the RM 65
..•~us Ex~nsion C~nector. The~PR.!'Ir 4~ bytes containing the ...
ROM, and the·~ower .4K byl~s' containing the R6502 stack .
MM, are a:tNays.corrimen. totJoth'Bank
and . Bank ·"1. An
#pditional 20/( bYtes of PROM/~9Mr:nay be asSigned common .
to both banks, or dedicated to BankO, on 4K-bytebOundaries
.\iVith the, Baqk Selection jumpers. The remaining PROM/ROM
· and RAM is dedicate~ to Bank O.
:VO
,6
o
anI:!
"
The RS-232Clriterface ci.rcuit converts the TTL lelle(signalsto .
RS-~2Cvoltage levels and routes the signals to the RS-232C
Conn~or. The TlY Interface cir(:uit converts TTLI.li/VEilsifjnals
to 20· inA curfEjnt ·signals arid routes the signals to the Audio!
TTY Connecto~. The TTY .receive data and transmit data lines
operate in parJ!lllel with the RS-232Clines.
(~EMORY
'"
,
\,'
Eight 24-pin P.Ro~ROM socketS allow installation of up to 32K
up the
bytes of PROM'ROM. PROM/ROM.si~ jumpers
Soc/m the·f5 volt supply. The +12V and,-:-.12V are used
.bythe RS-2329 IntElrfaceCirduit,.while, +12Vimq -5Vare,
required by the dynamic RAMs.
to
.
NMOS Interface (Input Voltage :::: +5 OV TA
Symbol
V IH
' VIL
ILH
.. ,
'~'
Ill'
,"
V OH
"{
YOl,
'"
'IOH
10L
'··Notes: .TTL
OC'TTL
:;".
--.
= 25°C)
Min
P,arameter
Unit
Max
5~0
.2.4
..,0.3
-100
InpUt HighVoltage
Input\-QW Voltage
Input High Current
(VIH =2AV) ,
Input Low..Current
(V ll "; O.4A)
Output High Voftage
(I LOAD"; :-'100 A)
Output Low Voltage
(I LOAD ";'·:.~3 rnA) •
OUtpllf High Current (Sourcing)
(VOH ~2.4Vl
(VOH ;;'1.51{, VIA FaG-PB7 only)
Output Low Current (Sinking)
(VOL"; 0.4V)
"
V
V
+0.4
-300
-1.0
-'1:6
2.4
5,0
-
0.4
'. rnA'
V
V
,
-
-100
-1.0
1.6
-
Industry standard LS. TTL.
Industry· stahdilrd Open Collector LS TTL.
'.
p.A
rnA.
rnA
"
3STTl
Industry standard 'Tri-State LS TTL.
TPTTL -: Industry standard'Totem Pole LS TTL.•
..
.'
8-24
,
,
.,
.,,!
~~,
A65/~1000
Single Board Computer
FPPF r",--'_D_EV_E_"CIt'M_.;.,E;.,NT_M
...O_D_E_ _..,
F~~
A'Me&'OO
I/OAOMII'
______ __________
E~'~
~
________
~
____
~
~
__
~
RU~.TIME MODI:
FFFFr---------------.
AIM 81/40
I/OROM"')
.~~-------------------;
DOOiI
•
High LIVII L.n u.... ROM. (31
. BASIC
FORTH
~~~--------~--------~
A'MH'4q
c~~---------L--------_;
~~-----------------;
~
JIDOO
JIDOO
8000
8000
7000
7000
8000
.~
'2K
0000
_0
3O~
3000
2000
2~
,~o
'000
...
RAM
AAM
USER
AV~ILABLE
EXPANSION
(32K)
18.
i
4000
,
RAM
1000
Option,l LlngUJIII" (31
200
1~
_
Rr;i"i;AAM
I~
t---
DEDICATED TO
BANK OOR
COMMON TO
BOTH BANKS
I44KI
12.
l-
500
200
BOTHBANK8
8000
600
'00
II,ROM/ROM
DIDICATED TO
BANK'OOR
CDMMONTO
'8'
'f8KI
100
500
14KI'
1
cooo
5000
USER AVAILABLE
a
ROM '110
COMMON TO
BOTH BANKS
120K'
FORTH
8000
o.bull/Manitor
&: Text Editor ROM, (2)
f
PROM/ROM
EXPANSION
I"KI
Optiontll AIM 815/40
ROMs (3)
BAilie
'/0 AOM III
FO~
.ooo~-------~--------_;
OptIDNI AIM U/40
High LI"i Lin
-r'l
FFFF
--- --
=
,'.
~Av!!!!!!!.~_
6602 Stack
0 ...· .....____.;.P.;;;...;,.z;,;;.;.;;
••;.;;Oota;;,;·,;;,.'.,..'_ _ _-oJ
"..-1
N......: (1) AIM 85/40 Syatem pa/'lpho..1I/O oddre.... oro ...
to FF80 ~ FFDF.
(2) u_ ..aPlble d~rina oppllc,tllOO'l progr.m. ope,don ~ tho debug and, text adltor !uncll";' "'" not uald.
(3) u_ ..iMobl. H tho q>llonai ianguoge and 'I!" RM 65 uponolon modulo ROM. are not iJ .....
1
J
4'
RAM
COMMON TO'
BOTHBANK$
14K' •
·
,
.
II
Connector J1 (Parallel Application) Pin ASSignments
Pin·.
Signal
I/O
Type
Pin
. SJrlnal
Type
1
3
5
7
9
11
13
15
CB2
CBl
PB7
PBS
PBS
PB4
PB3
PB2
PBl
PBO
PA7
PAS
PAS
PA4
PA3
PA2
PAl
PAO
CA2
va
NMOS
NMOS
NMOS
NMOS
NMOS
. NMOS,
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMds
NMOS'
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
2
4
6
8
10
12
14
16
18
20
22
24
28
28
30
32
34
38
38
40
NC/+5V·
. GND
GND
GND
GND
GND
GND
aND
GND
GND
GND
GND
GND
GND
GND
GND
Power
POwer
Power"
POwer
Power
PoWer
PO\Ver
Pciwer
Power
PoWer
Power
POwer'
Power
PoWer
Power
Power
.Pow8r
Power
Power
Power
"
17
19
21
23
25
27
29
31
33
35
37
39
,.
CAl
.
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
vo
VO
I
~ND
GND
GND
NC/+5V"
Note: ·Plns 2 and 40 can be optionally jumpered to +5V (maximum current through each pin shpuld not exceed 200 mAl.
8-25
,
.
A65/40-1000
Single Board Computer
Connector J2 (Serial Application) Pin Assignments
Pin
Signel
1
3
5
7
GND
9
11
13
15
17
19
21
23
25
Rl5
CTS
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
.Pln
1/0
Type
I
I/O
Power
RS-232C
RS-232C
Power
2
4
6
B
10
12
14
16
18
20
22
24
26
Connector J3 (AudlorrTY) PIn Assignments
Signal
1/0
Type
TO
RTS
DSR
DCD
NC
NC
NC
NC
NC
DTR
NC
NC
NC
a
RS-232C
RS-232C
RS-232C
RS-232C
I/O
I/O
1/0
1/0
Pin
1
3
5
7
9
11
13
15
17
19
RS-232C
Signal
1/0
Type
Pin
Signal
Type
I
TTY
TTY
TTY
Power
TTL
TTL
Relay
Relay
Relay
Relay
2
4
6
8
10
·12
14
16
18
20
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
TTY RTS
TTYTD
TTY RD
TTY RTN
AUDIO OUT
AUDIO IN
CTRL2 RTN
CTRL2
CTRL 1 RTN
CTRLl
a
I
a
a
I
a
Connector J4 (RM 65 Bus) Pin Assignments
Bo~m
Pin
·Slgnal
Mnemonic
Wa
Xa +5V
la GND
2a
BADRI
3a
GND
4a
BA13/
Sa BA111
6a
BA1O/
7a
BA81
8a GND
9a
BA5/
10a BA3I
11a BA2/
12a
BAO/
13a GND
14a . BSO
1Sa
BRDY
16a
17a
+12 V/+V.
18a GND
19a BDMTI
20a
21a
Bp.tWI
22a
23a GND
24a
BIRO!
25a B%2/
26a Bjt2
27a
BCm
28a
GND
29a BD4/
30a BD2/
31a
BD1/
32a
+SV
Va
za
+SV
Top (Component Side)
(Solder Side)
Signel Neme
Not Connected
+5 Vdc Line (See Note)
Ground
Buffered Bank Address
Ground
Buffered Address ·Bit 13
Buffered Address Bit 11
Buffered Address Bit 10
Buffered Address Bit B
Ground
Buffered Address Bit S
Buffered Address Bit 3
Buffered Address Bit 2
Buffered Address Bit 0
Ground
Buffered Set Overflow
Buffered Ready
*User Spare 1
I/O
Type
0
0
0
a
0
a
0
0
a
I
I
Power
Power
3STTL
Power
3STTL
3STTL
3STTL
3STTL
Power
3STTL
3STTL
3STTL
3STTL
Power
OCTTL
OC TTL
*+12 Vdc/+V
Ground Une
*Buffered DMA Terminate
* User Spare 3
Buffered'Reacl/Write "Not"
*System Spare
Ground
Buffered· Int~rrupt Request
Buffered Phase 2 "Not" Clock
Buffered Phase 2 Clock
Buffered Data Bit 7
Ground
Buffered Data Bit 4
Buffered Data Bit 2
Buffered Data Bit 1
+S Vde
+S Vdc(See Note)
Not Connected
Power
0
I
0
a
I/O
I/O
1/0
1/0
3S TTL
Power
OCTTL
3STTL
3STTL
3STTL
Power
3STTL
3STTL
3sTTL
Power
Power
-
Pin
Wc
Xc
1c
2c
3c
40
Sc
6e
7c
Be
ge
lOe
Signal
Mnemonic
+5V
+SV
BA1S1
BAl4/
BA12/
GND
BA9/
BA71
BA61
BA4/
GND
BA1/
Brl1
BSYNC
BDR011
GND
11c
12e
13c
140
1Se
16c --12 V/-V
17e
1Be BFLTI
1ge Bf/O
20e GND
21e BDR02/
22c BRlW
23c BACTI
240 BNMII
25c GND
26c BRESI
27e BD6I
2Bc BD5/
2ge BD3I
30e GND
31e BDO/
32e GND
Ye +5V
Zc
Note: *Not used on the SBC. Signal name reflects RM 65 Bus reserved function.
8-26
..
Signal Name
Not Connected
+5 Vdc (See Note)
+S Vdc
Buffered Address Bit 15
Buffered Address Bit 14
Buffered Address Bit 12
Ground
Buffered Address Bit 9
Buffered Address Bit 7
Buffered Address Bit 6
Buffe red Address Bit 4
Ground
Buffered Address Bin
Buffered Phase 1 Clock
Buffered sync
*Buffered DMA Request 1
Ground
* -12 Vde/-V
*User Spare 2
Buffered Bus Float
*Buffered External Phase a Clock
Ground
*Buffered DMA Request 2
Buffered Read/Write
Buffered Bus Active
Buffered Non-Maskable Interrupt
Ground
Buffered ·Reset
Buffered Data B~ 6."
Buffered Data Bit S
Buffered Data Bit 3
Ground
Buffered Data Bit 0
Ground
+S Vdc (See Note)
Not Connected
I/O
Type
-
a
0
0
0
0
0
0
0
a
Power
Power
3STTL
3STTL
3STTL
3S TTL
3STTL
3STTL
3STTL
3STTL
Power
3S TTL
TPTTL
3S TTL
Power
I
OCTTL
Power
0
I
I
0
I/O
I/O
I/O
VO
3STTL
OCTTL
OC TTL
Power
OCTTL
3STTL
3STTL
3STTL
Power
3STTL
Power
Power
-
A65/40-1000
Single BoardCom'puter
Connector J5 (Printer) Pin Assignments
R6522
~
Pin
1(1)
Signal
35
+5V
NC
NC
NC
NC
NC
NC
PAPERFEED (2)
RES
PBl
PA7
PA6
PAS
PA4
PA3
PA2
PAl
PAD
37
39
CA2
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
Printer
1/0
0
0
VO
1/0
VO
1/0
VO
VO
1/0
VO
1/0
VO
,,,.
Signal
+5V
NC
NC
NC
NC
NC
NC
PAPERFEED (2)
RES
STROBE
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
NC
110
Typa
Pin
0
Power
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40(1)
-
-
0
0
TTL
TTL
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
I
NMOS
0
0
0
0
0
0
0
0
-
ACK
Notes: (1) Maximum +5V current through J5 should not exceed 200 mA per pin.
Signal
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+5V
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
(2) Connected to J7-39 through jumper W3.
Connector J6 (Display) Pin Assignments
Display
R6522
Pin
1 (1)
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Signal
+5V
NC
NC
NC
NC
NC
NC
PAPERFEED (2)
RES
PBO
PA7
PA6
PAS
PA4
PA3
PA2
PAl
PAD
CB2
1/0
I/O
Signal
1/0
§'fROBE
110
Data 7
Data 1$.
Data 5
Data 4
Data 3
Data'2
Data 1
Data 0
NC
ACK
1/0
I/O
I/O
vq
VO
VO
VO
1/0
Type
Power
+5V
NC
NC
NC
NC
NC
NC
PAPERFEED (2)
RES
-
-,--
0
0
0
0
TTL
TTL
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
I
NMos
0
0
0
0
0
0
0
-
Noles: (1) Maximum +5V current through J6 should not.exceed 200 mA per pin,
8-27
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+5V
(2) C'onnected to J7-39 through jumper, W3.
Type
,
Power
Power
Power
Power
Power
Power'
'Power
Power
Power
Power
Power
Power
P'lwer
Power
Power
Power
Power
Power
Power
Power
A65/40-1ooa
Single Board"Computer
Connector J7 (Keyboard) Pin Assignments
R6522
Pin
Signal
1.(2)
3 (3)
5
CB2
CBl
.PB7
PB6
PBS
PB4
PB3
PB2
PBl
PBO
PA7
PA6
..PAS
PA4
PA3
PA2
PAl
PAO
CA2
CAl
7
9
11
13.
15.
17
19
21
23
25
27{ ,
29
31
.33
35
37
39.
Nates: (1)
I(2)
(3)
(4)
Signal,"
I/O
I/O
I/O
I/O
1/0·
I/O.
I/O
I/O
I/O
1/0
1/0
1/0
1/0
I/O
I/O
I/O
I/O
1/0.
1/0
1/0
I
'.
I/O
'i
RES
AffN
MSB7
MSB6
MSB5
MSB4
MSB3
MSB2
MSBl
MSBO
MRT?
MRTS
MRT5
MRT4
MRT3
MRT2
MRTl
MRTO
MSB8
. PAPERFEED
......
....
Keyboard
I
0
0
0
0
0
.
0
0
0
I
I
I
I
I
I
I
I
I
I
Type
TTL
TTL
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
Pin
2(1)
4
6
8
10
12
14
16·
18
20
22
24
25
28
30
32
34
3S:
38
40(1)
Signal
NC/+5V
GND
GND
GND
GND
GND
GND
. .GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC/+SV
Type
pOwer
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Pow.er
Power
Power
Power
Power
Power
Powe(
Power
Power
PillS 2 andAO'Can beoPtioneJlyjumpereC! ta+.5V(maximum curren.t thraugh each pin shauld QOI exceed 200 mAi.
Pin 1 can be aplionallyjump9Fl1dta the RESET circuit ar to' 062.
Pi~.392n be aptionallY jumpered to' the NMI ..circuit or ta'CBI.Pin 39 can be aptian ally jumpered as PAPERFEED ar to' CAL
SPECIFICATIONS
Parameter
Dimensions
Width
Length
• Height
Weight
".
1.0 lb. (373 g)
O°C to' 70°C
-25°C to' +85°C
:
. '.. 0% to' 85% (w~t)aut cendpard-Ievel products, .or to other
computers.
The A65/40-0210 Extended Keyboard has all of. the abovefeatures, plus an industry standard numeric keybo!ird and cursor
control key
A65/40-0200 Standard Keyboard
Document No. 29000074
8-32
Data Sheet Order No. 074
Rev. 1, August 1983
AIM 65/40 Standard and Extended Keyboards
A65j40-0200, -0210
an image of the entire keyboard matrix. Three momentary contact keys-RESET, ATTN, and PAPER FEED are outside of the
keyboard matrix.
FUNCTIONAL DESCRIPTION
The AIM 65/40 Keyboard assembly. is a terminal-style alphanumeric keyboard which interfaces to a host computer through
a parallel interface. The keyboard contains 66 momentary contact single pole single throw (SPST) keys and one locking SPST
key.
All keyboard strobe and return lines are brought out to a 4O-pin
keyboard interface connector, which allows direct connection to
an AIM 65/40 SBC or any RM 65 modules with the parallel
peripheral connector.
The keyboard has a complement of 63 momentary contact keys
in an 8 x 9 matrix; with nine positions unused. An ALL CAPS
locking key is also in this matrix. To decode keys within the
matrix, the AIM 65/40 software places a logic 0 on one of the
nine strobe lines of the matrix. By reading the eight return lines,
any keyes) down on that strobe row can be distinguished.
Repeating this process for each of the nine strobe rows gives
KEYBOARD
INTERFACE
CONNECTOR
(J11
RESET AND
RETURN
-
ATTN
KEY
RESET
KEY
I
The added keys on the Extended Keyboard control 15 additional
momentary contact SPST switches, which are included in the
8 x 9 switch matrix. The 11 numeric and decimal switches are
connected in parallel with their counterparts on the main keyboard. The four cursor control switches are added positions in
the matrix which are not included in the Standard Keyboard.
,---
MAIN KEYBOARD KEYS (571
PAPER FEED
I
I
FUNCTION KEYS
I
,
I
I
L_~_..J
OTHERS
U
t
NUMERIC
KEYBOARD
lsI
II
15
II
II
II
II
ATTENTION
AND RETURN
U
PAPER FEED
AND RETURN
MATRIX STROBES (9)
KEYBOARD SWITCH
MATRIX
MATRIX RETURNS (Sl
-
* EXTENDED KEYBOARD ONLY
Keyboard Functional Block Diagram
Connector P1 (System Interface) Pin ASSignments
Pin
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12 '
10
8
6
4
2
Signal
Signal
Pin
~
39
37
35
33
31
29
27
25
23
21
19
ATTI'J
MSB7
MSB6
MSB5
MSB4
MSB3
MSB2
MSBI
MSBO
MRT7
MRT6
MRT5
MRT4
MRT3
MRT2
MRTI
MRTO
MSBB
PAPER F~~15
17
15
13
11
9
7
5
3
1
\
NC
GND (1)
GND (1)
GND (1)
GND (1)
GND(I)
GND (1)
GND (1)
GND (1)
GND (1)
GND (1)
GND(I)
GND(I)
GND (1)
GND (1)
GND (1)
~RET
ATTN RET
PAPER FEED RET
NC
Notes:
(1) Odd-numbered pins 9 through 37 are connected together on the keyboard and should be connected to GND on the interfacing equipment.
(2) The pin number assignments are reversed' from the AIM 65/40 SBC, to provide a one-to-one Signal routing through a 4O-conductor ribbon
cable.
8-33
AIM 65/40 Standard and Extended Keyboards
A65/4O-0200, -0210
fIIRT7
~
~5
'"
h
Io1Rrs
MRlo
flll
'"
~~
kJ
MRI4
MRll
'"
'"
'"
(LERlS
(RIGHT)
5
r~
1-;:;-
...'"
r~
~
~
r-:;-
~
[~
-r-;-
[t
rt
n-
It It
~
(t
r.
f~
1-:--
(7-
t
...L
G
.~
t
.
[-:-
r-:-
...L
.~
"
".
MS81
'"
,.,
,.
'il' -
r-:-
r.-'-
PRI_T
r:-
1-:--
Jt rt
;
<
[-:- r-:- r-:- ft rt (.:
r-:- r-:- [-:- rt It [-:...L
...L
...L
-'-
-'-
...L
---Jr·
.......
[ , _.......
f ._.......[ ._.......[_,____C"'-:____['-..;____[-,
Standard
.m
5!
f~
~
,~
~i&:
f~~s
,.,
~"
!
"
-'-
~,
MOTES:
1. LEGENDS IN PARENTHESES
DO MOT APPUR OM KEYCAPS
2. NU.8EtS III PAR[NTHESES
REfER TO PIN NU.IERS ON
CONNfCTOI J1
M~lI
'"
..J....
,w
.n,
..,
'"
"',..
,.,
'"
.
,
'"
'm
"""
'"
..L
M~TO
•
ltr;~-~-~--------~-----~--~--1---+---+-~~~~-~~
Non:S:
1. LEGENDS IN PARENTHEsES
00 lOT APPEAR ON IEYCAPS
2. "UMaUs IN PARENTHESES
R£FER TO PlN NU.IERS ON
CONNECTOR Jl
Extended
Keyboard SChematic
SPECIFICATIONS
Parameter
Dimensions
Width
Length
Height
Weight
Value
..
Standard
Extended
11.85 in. (301 mm)
5.25 in. (133 mm)
1.25 in. ( 32 mm)
15.35 in. (390 mm)
5.25 in. (133 mm)
1.25 in. ( 32 tnm)
1 lb. 12 oz.
1 lb. 8 oz.
Environment
Operating Temperature
Storage Temperature
Relative Humidity
Interface Connector
O'C to 50'C
-40'C to 55'C
0% to 95% (wtthout condensation)
40-pin 3M #3495-1002, or equivalent, receptacle. Mates wtth 3M
#3418-0000T, or equivalent ribbon cable connector.
8-34
A65/40-020(), -021.0
TOLERANCES
.XX-t.GS
.XXX-:t.010
.XX - ±.03
.XXX-±.010
AIM 65/40 Standard and Extended Keyboards
Standard
Extended
Keyboard Dimensions
"".:
8-35
,
A65/40-0400
.
AIM 65/40 MIcrocomputer Family
'1'
Rockwell
A65/40-0400
AIM 65/40 40-CHARACTER DISPLAY
OVERVIEW
FEATURES
The A65/40~0400 4O-Character Display is one ofjhe hardware
options available for the AIM 65/40 Microcomputer family.
• Intelligent controller
-Independent open~tion
-Centronics type handshake interface
-Separate character font/program ROM
• 40-character display
-VaCuum fluorescent
-Easy-lo-read 16-segment digits
-Clear,' bril1ht blue-green color
-Fast response
-Long life
The 40-Character Alphanumeric Display is a free-standing
subassembly consisting of a vacuum fluorescent display and a
microprocessor based controller. With its integral controller,
operation is completely automatic-including display refresh.
Connecting to a host computer over parallel interface with Centronics-compatible protocol, comman,d and.data'.are transferred
in a handshaking manner.
.
The sealed vacuum fluorescent display includes 40 bright, crisp,
16,segment digits. The blue,greencharactersare easily readable ,in almost any working environment-from offiee to factorY.
• 196 charaqlers
-Upper case alphabetics with lower case notation
-Numbers
-Math symbols
-Special characters
• Variable display parameters
-Auto-scroll rate
-Character blinking
-Character blink rate
-Cursor blink rate
• Internal editing functions
-80-eharacter line buffer
-Insert/delete character
-Right/left cursor control
- Transmit edited line to host
• Display self-test
• +5V operation
Firmware functions in the cOntroller augmeQt basic, c01'J'1munication and display updating with a variety of editing functions
and display enhanceml;!nts to increase its usability. The "full 40characters, coupled with programmable eye-catching techniques, such as variable rate character blinking and auto-scrolling,
allow meaningful and important messages to be displayed,
detected and understood-in factory, office, laboratory and
classroom applications.
Installation in a wide variety of racks, cabinets, enclosures, and
front panels is easy due to its straightforward construction and
standard interface. the display can be connected directly to the
Rockwell A65140-1 000 Single Board Computer (SBC), to Rockwell RM 65-1000E SBC module or RM65-5222E GPIO and
Timer module, or other compatible equipment, through an interconnecting cable.
A65/40-0400 40·Character Display
Document No_ 29000076
8-36
Data Sheet Order No_ 076
Rev_ 1, August 1983
4O-Character Display
A65/40..0400
FUNCTIONAL DESCRIPTION
The 4O-Character Display contains a vacuum fluorescent display, a microprocessor based controller, clock, a 2K-byte character fontJprogram ROM, character and segment drivers, and
a DC/DC power converter.
to provide a custom character set. The controller performs all
communications interfacing, display refreshing, and control
functions-enabling the display to operate independently from
the host computer.
The vacuum fluorescent display is a single sealed unit containing 40 separately controUable digits. Each digit is composed
of a 16-segment font which allows a full Set of upper case alphabeties, numerics, and special characters to be displayed. In the
semi-graphics mode, the 16 segments of each digit are individually controlled. In addition, each digit includes a separate decimal point. When energized,· the digits form blue-g'reen color
characters. The unit comes with a smoked, neUiral filter lens
cover the display, but other custom lens filters can be used to
change the display color to meet unique installation requirements.
All data and control commands are transmitted to the display
over the Centronics-type parallel handshake interface, An internal
buffer allows up to 80 characters to be received by the display;
the display scrolls after the 40th character is received. There
are character editing commands such as insert and delete, as
well as transmit buffer, which sends an edited line back to the
host computer. There are .al50 display enhancement features
such as auto-scroll which allows the display buffer to be continuously circulated, at a selected rate, and blinking characters.
The two-post terminal block provides +5V for the controller and
for the on-board DC/DC Converter, which generates the additional voltages required by the fluorescent display. The +5V
can, alternatively, be routed through the interface connector.
The display controller includes an R6504 CPU, RAM, VO, timer,
clock and reset circuitry. The 2K byte ROM contains both the
CPU controller instructions and the individual character segment
patterns. This ROM can be replaced by another PROM or ROM
.
Hex
Code
Control
Character
00
01
02
03
04
05
06
07
08
CTRL@
CTRLA
CTRLB
CTRLC
CTRLD
CTRl E
CTRL F
09
OA
OB
OC
00
OE
OF
.
Display Control Commands
Description
Clear Line
Clear to End of Line
Clear Line
Clear to End of Line
Clear Une
Clear to End of line
CT~G
.
CTRLH
CTRLI
CTFlLJ
CTRLK
CTRLL.
CTRLM
CTRLN
CTRLO
Backspace (---)
HoriZontal Tab (~)
Warm Reset
Warm Reset
Warm Reset
(Home on line)
(Home on Line)
Carriage Return (Home on Line)
,
Hex
Code
Control
Character
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
CTRLP
CTRLQ
CTRL R
CTRLS
CTRL T
CTRl U
CTRL V
CTRLW
CTRLX
CTRLY
CTRLZ
cTRL [
CTRL\
CTRL)
CTRLA
CTRL -
'Characters with no Indicated functiori are acknowledged, but do not otherwise affect display operation.
8-31
Description
Pass Through Next Character
··
··
Toggle Insert Character Mode
Delete One Character
Display Cursor
Blank Cursor
Warm Reset
Cold Reset
Escape Command (eSC)
··
··
A65/4~0400
4O-Character Disp.lay
40 CHARACTER
FLUORESCENT DISPLAY
DISPLAY
INTERFACE
CONNECTOR
DATA(S)
~
it
11,
DISPLAY CONTROLLER
ACK
REs
SEGMENT
DRIVERS
,l~"~--~~~
STROB,E
BU~Y
CHARACTE.R
DRiVERS
.....
-
~ __________________________J
,
POWER
CONNECTOR
(TB1)
G:: I: I
.,. .,. . .-"'!'--_. . .
~
-
DC/DC
POWER
CONVERTER
4O-Character Display Block Diagram
8-38
CHARACTER
FONTI
I
PROGRAM·
"
ROM'
4O-Character Display
A65/40-0400
Display Escape Commands
Hex Code
Character Sequence
lB 41
lB 45.
lB 47
lB 49
lB 54
lB 58 4C
lB 3D
lB57
lB 58
ESC A
ESCExyz
ESCG
ESC I
ESCT
ESC X L
ESC ~ x Y
ESCW
ESC X
Function
Auto-Scroll Display
Set Environment (1)
Enter Graphics Mode
Select/Deselect Display (toggle)
Perform' Self-Test
Tr,msmit Line
Pos~ion Cursor (2)
Set Window Pos.ion
Transmit Display Une
Notes:
(1) Set Environment Sequence:
Hex Code
41
42
43
52
53
Function
Character Sequence
XX
yy ZZ
YY ZZ
XX
XX
A (Attribute)
B (On) (Off)
C (On) (Off)
R (Rate)
S (Character)
Set
Set
Set
Set
Set
Bit-7 Attributes
Blinking Character Rate
Blinking Cursor Rate
Auto-Scroll Rate
the Cursor Character
(2) The Pos~ion Cursor sequence requires two add~ional characters. The firs! (y) is ignored. The second (x) becomes the new cursor position.
Connector J1 (Interface) Pin Assignments
Pin
Signal
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
+5V'
NC
NC
NC
NC
NC
BUSY
NC
RES
STROBE
DATA 7
DATA 6
DATA 5
DATA 4
DATA 3
DATA 2
DATA 1
DATA 0
NC
ACK
1/0
Type
Pin
Signal
Power
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Gt:JD
GND
GND
NC
NC
+5V'
-
TTL
-
I
I
I
I
I
I
I
I
I
I
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
-
0
NMOS
Note: • +5V on pins 1 and40 can be disconnected by a jumper.
8-39
Type
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
-
Power
40-Character Display
A65/40-0400
Data Transfer Timing Characteristics
Symbol .
Min
Parameter
Data Set-Up Time
Data Hold Time
Strobe Pulse Width Time
Processing Time
Acknowle~ge Width
Strobe-to:!Iusy .Time
Acknowledge:tO.Busy Time
Tosu
TOH
Ts
Tp
TA
TSB
TAB
0
25
50
-
Typ
Max
-
--
500
5
-
14
25
20
40
Note: to tf = 10 to 30 ns
OATA=X·
~
TO.SU
TOH
\
iL-J
TS
Tp
,
~
BUSY
I·
Data Transfer·Wa'\(eforms
8-40
-
"
Unit
I1-S
I1-S
ns
I1-S
I1-S
ns
ns
A65/4()'0400 ,.
SPECIFICATJQNS'
".,
V.f~
. Para/netel'
Dlmenillona
Width
Height"
Depth"
11.85 In. (301 mm)
3.Sin, (91 mm)
1.5 In. (38 111m)
Weight
8 O~.
Digit Dlnienstons .
Height'
'
Width,
"
....
,
"
','
...
" 0.24 in. (Smni)
. O. t~ in. (3 m~)
Power, Requl~ents
,.,'
"
:,'
..
'.,
'
+5'''!:5%fiegutated, o.aA(typical), 1,.OA (max.)
..
~nvlroninent
,,~.
Operating Temperature
Storage Temperature '
Relative, Humid\ly
.
,
,,:'
,'"
.
..,'
O"Ctd500c
-55"C to +iIo"c '
0% to 95~1o. (without cohdensatioo)
Interfm COnnectOr
~pin 3M #3495-1002,orequivalent,connector. Mate~ wk~ 3M
#3418;OOOOT,0r.iJquivalent, ribbcio cable QOnneclo(; .
Power Connector
Two-post terminal block
'"
."
Note: "Dimensions do not include mountl"\) bracketS.
"
..
,
,
...
NMOS Interface (Input yoltag.
sYmbol
VIH ',
V il
I,IH
III
VOH
VOL
10H
IOl
=, +S.OY, TA= ~C)
PIII'~r
Input High \A;iltage
Input Low Voliage
. Input )-llgh'Current
(VIH ""2.4V)
.. Input, Low Current
(Vll ",' 0.4A)
' Output High VQltage
. (I LOAD .E;,-I00A)
.Output L,ow VoHag$
, (ILOAD ","-3mA)
OUtpuf\rligh yUrre;,! (SOurcing) ,;'
(VOH" 2,4V)
Ol,Jlput Low Current (Sinking)
(VOL E; O:4V)
,
Min
Max:
2."
-0.3
-100
5.0: "
+.0.4
-300:
V
V
p.A
.,.1'.0
-1 •.6,:
rnA
5.Q
V'
0.4
V
!
2.4
Unit
p.A.
'-100
1.,6
,.
'/ .
mA
m
A65140-0400
40-Character Display
o
6
c
9
,,-,/--,
8
7
I
\
I
, "\i'
"-'1'/
~,-;,
,
" '
,..:.':~~,
, ,
it
I
":"-
"
IL'~"'" "
I
, l' ,
I
-\
I
I~_I
:"T'I
I·
I
1/ I \
:"~;,!-,
L:~
I
I,"
\
__\I
,,
I"
\.
"
"
'-"--' 'Z--'~'
't"
"\'. - --'
1\ I
,
"I
I
I',
E
:Sf2:
izls:
, , ,
Eel Gel 1\[/' ee,
, "'11
L" '" \ , I" J'\ , '/1
~_.J
__ l-.'
I~I'
It" ,
,\,
I~I
I
[iSI
1\:"-'/--'
l
I,
:-'\: :
't--';-'
,
1'1
I
'-",-'
:/j--';--: ,'~',"
,1 _'_J'
I \
I
,
-
-
,
I
I_ ... \I~
\
I
I(_..:.a'
I
IH
II,._'....J
,
{\ill {\!~1 I\t/l
Irc-,~,
1'1 I
ti~,
", J , L__"~
_
--"'--,
L___
L:~
,
"
"
\
I
'1
I
",,,,,:'
-'-;;'
I ',I
6 :,,-,:~-:
I "
I '. I
'!._I_~I
I'\:,/I,:
"-t- "
I
8
... I_~\l
, 'I' , ' / . \ I
I'
' / '.
I~_o...,).
4
l
,
I
',--'-i '''-Il'
"-l-I'
I,--",--,
'/' '''L-''
, , CO'Ge!
"
''-~.
, '" I~~;.
, '" !~!J
--,1
1\
J, "
I \ I,'
"-'-',
'--":...
\
3·
I
I~-.:.al
,..;.
I I
I
I
~tJ~l ,:\,7:
'-;,~,'
,'-'-i£.--'
, ,
o
'-\j-''-i
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'-,-.-/1
I
~\I __ '
1\ "
-:,'_a',,-,
,--1':-'
,:- '
'_I_J 1I
'"
"1,.-
'~1-;'
I'
"
:'L-:,~~-:
,, ,, ,,
'-,'""71
,'
,--",-,
~(~:-y
"
I /
_ _ oJ
'.
I,"
•
",
r
~i)~1
'~I-"
'\1/'
'\
,
I
\
,.
I /'
,-",,"-,
, "' .
, ',\', 1/1\1
I_,I~I
I
'"
,
I~'~I
't._'_oJ l
,-":-,
I\t/'I
",
~I~
, , ,, , ,
'S'?'
'S2'
,:t-:\:
, , "h,'\-:,
' , ;\J/'l
, ,,
,,-:,:-,'
-,',:-'
"
·t_ ...J t---'
'
" :-j:,-,
--,-,, '\-'/1-1/' " ,
,
,,",,(-;,
_'.....
L:~,~,:
, ,,,,
"
, )~-:
,-'...)1 :L.:~
(1\'/ CO
\
f
~L-"
\ /1
,,-,- ;,
I
I,-t'l
,_,I~'
r
I
"'
1'1'\
,I
,t:"'_J'
'
'
~L-"
\ ,'1
_ , __ I
I
'1\
,,' I \
I
I
'!._'_J'
~,-;,
,
"'::,:L
I
11\
I', \
I
I
,".-,':"
\.,',
,'-:::J~'
" '
It_'_J ' ~"
Character Display
8-42
I
'\/-1'
, , '
:":7:
_'_
t
,~_
-
I
'"-,\ ,II,
' , , , UI'-' ,'-"~~:
,--:,H
, ,
~-~, "~, '"_~I, ,rt, ,
I
I
\
,
"7,-,7: ,,-,r--:,:--:
, , -:,'~:
/,
,
/L
,
,
_~I
"
\
I,' I
, "
~~I
l"
'\' " ":...::\~:
, '" ,
''-'--'
I
'/1
:tJ--':--:
1\ t
,
,
I~I
,,'
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I
A651011,070$)O
AIM 6$140 Microcomputer Family
A65/40-0600
,AIM 6~/40 GRAPHICS PRINTER
'OVERVIEW
,
;
'.
111e A65140-0600Graphlcs Printer is one of the hardware options
troller performs printer motor and thermal head timing and control functions, tqenable the printer to operl/.teindependenlly
from the host computer. Further, the controller handles the communications interface, and processes the commands arid data
to be printed.
'
,available for the AIM 65/40 Microcomputer Family.
,ThjI Grapl1l9s PrJ!)ter is a microprocesser-controlled dot matrix
thermal printer, wtth a 41< byte character font/program ROM,
:and a paper fgedswltch. In the test mode, up to 40 characters
can be printed using 7 x 8 dot matrix characters. In the graphics
mode, all 280 horizOntal dot posiiions on a row. are individually
controlled, and any number of rows may be printed.
'
Data and control commands are transmitted to the printer over
the Centronics i¥pe parallel handshake. injerface. An Internal
buffer accepts ~ to 80 characters fOr printing. The controller
automatically prints the first 40 characters In the text mode or
after receiving each row 01 280 dots In the'graphlcs mode. The
paper can alse be advanced with a paper feed command, or
manually, using the paper feed switch.
The printer mechanism includes a thermal head, platen, motor,
drive linkage and asscc18ted wiring. There sre 40 thermal elements on the thermal head, each of which spans seven dot
fields. Each element is a discrete point which rides against he,at
sensitive paper. During a print cycle, the thermal head moves
horizontally across the paper. Control logic turns on the thermal
head drivers to hElat the sensitized paper when a dot is to be
printed: Wi'l!In an entire, row of dots has been printed, the printer
mO,tor adyances the ptaten by ,one horizontal row of dots.
The printer. controller inciudes.an R6504 CPU, RAM, VO, timer,
Clock al1d reset circuitry. The 4K byte ROM contains both the
CPU inStructions and the individual char~er bit patterns. The
'RQMis, sccketed, anci Can be replaced by a user-supplied
"PROM or
ROM, ,to provide
a cu,stom
character set.
The con"
",
..
i
ASS/40-0S00 Graphics Printer
A three-post terminal biock connects to +5V, +24V and GND.
The +5V supplies the control circuitry ,while the +24V powers
the motor and thermal head drivers. On-board potentiometers
allow motor speed and dot print Intensity to be manually adjusted.
FEATURES
• ,Intelligent controller
-Independent operation
-User command flexibility
-Centronics type handstlake Interface
-Separate character font/program ROM
• 4O-column text/semi-graphics
-256 character set
.- Upper and lOWer case alphabetlcs
-~umbers including superscripts and subscripts
-Math symbols
-European and Greek characters
. • Full graphics capability
-280 dot x n
-Individual dot control
-Print complex wave forms and digitized photographs
• Fasl-240 lines per minLile
• Quiet, thermal operation
• User alterable dot liming
• Printer self-lest
• Requires only +5V and +24V
DO,cument No. 2900007$
8-43
Data ShHt Order No. 075
Rev. 1, August 1983
I
AIM 65140 Graphics Printer
A65/40-0600
Printer Control Commands
Hex
Code
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
Character
CTRL@
CTRLA
CTRLB
CTRLC
CTRLD
CTRLE
CTRL F
CTRLG
CTRL H
CTRLI
CTRLJ
CTRLK
CTRLL
CTRLM
CTRLN
CTRLO
Hex
Code
Description
10
11
12
13
14
15
16
17
18
19
IA
IB
IC
10
IE
IF
*
Clear Une
Clear to End of Une
Clear Une
Clear to End of Line
Clear Line
Clear to End of Line
*
Backspace (<-)
Horizontal Tab (~)
Line Feed (,f)
Line Feed (t)
Form Feed
(Home on Line)
(Home on Line)
Carriage Return (Home on Line)
Desc~lptlon .'
Character
CTRL P
CTRLQ
CTRLR
CTRLS
CTRL T
CTRL U
CTRLV
CTRLW
CTRLX
CTRL Y
CTRLZ
CTRL!
CTRLi
CTRL]
CTRLfI
CTRL-
,
...
Pass Through Next Chara~ter
*
*
Toggle Inl>ert C.haracter Mode
Delete One Character
*
*
Turn CUrsor On
Turn Cursor Off
Cold Reset
Warm Reset
Escape Command (ESC)
Print Buffer Without Clear
Print Display Image (Window)
Paper Feed
*
Note: 'These characters are acknowledged, but do not otherwise affect printer operation.
Printer Escape Commands
Hex Code
IB 3D
IB 45
IB 47
IB 53
IB 54
Character Sequence
Function
ESC = Y x
ESC E x
ESC G
ESC S
ESCT
Posttion Cursor (1)
Set Environment (2)
Enter Graphics Mode
Transmit Character Definition
Perform Self-Test
Notes:
(I) The Position Cursor sequence requires two additional characters. The first (y) is ignored. The second (x) becomes the new cursor position.
(2) Set Environment Sequence:
Hex Code
41
47
50
54
XX
XX
XX
XX
Character Sequence
Function
Set Bit 7 Attributes
Set Gap Between Pages
Set Page Length
Set Dol Print Time
A (Attribute)
G (Length)
P (Length)
T(Time)
8-44
. ,;,i
AIM: 65/40 Graphic;s Printer
Data Transfer riming
Symbol
....
TD~u
Parameter
Min
Data Set-up Time"
Data Hold Time
Strobe Pulse Width Time
Processing Time (non-printing)
processing Time (printing)
Ackr]owiedge Pulse Wi,dth Time
Strtibe-to-Busy Time.
Acknowledge-Io-Bu$Y Time
To~
1s
Tp
"Tp
TA
Ts B,
TA.B
'0
25
50
0.13
0.25
-
Typ
--
0.15
5
14
20
..
MIil(
-
-
12
0.5
-
25
40
Note: t~ If = .10 to 30 ns
DATA
~
~ j.:=
T"",
.1.
,
~,--------1::1---------
TOM::.j
II
~
BUSY
Data Transfer
Wav~form8 "
'8-45
Unit
/LS
/LS
ns
ms
S
/LS
ns
ns
.'
AIM 65/40 GraphiCs Printer
A65/40-0600
SPECIFICATIONS
...
...
Parameter
Value
Dimensions.
Width
Length
Height
7.6 in. (193 mm)
6.3 in. (160 mm)
3.0 in. (77 mm)
Weight
1.0 lb. (0.45 kg)
Environment
Operating Temperature
Storage Temperature
Relative Humidity
.,
O'C to 50'C
0' to 70'C
, 0% to .85% (wnhout condensation)
Power Requirements
+5V ±5% Regulated, 0.3A (typical); O.4A (max.); 0.4 (peak)
+24V (+3.6V, -2.6V) Unregulated, 2,5A (typical); 4.0A (max,); 6.3* (peak)
I nterface Connector
40-pin 3M#3495-1002, or equillalent, receptacle: Mates w~h 3M
#3418-0000., or equivalent,.. ribbon cable connector.
Power ·Connector
3-post terminal bloi:k
Note: *+24V peak current specified as worst case with printer duty cycle of 75%. For most'cases, a +24V 4A power supply is sufficient.
"
,
Connector J4 (System Interface) Pin Assignments
Pin
1*
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Signal
I/O
+5V
NC
NC
NC
NC
NC
BUSY
PAPER FEED
RES
STROBE
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
NC
ACK
Type
Pin
Signal
Power
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40*
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
-
-
-
-
TTL
TTL
TTL
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
0
NMOS
Note: *Power 6n pin 1 and 40 can be diSConnected from this .connec.tor with on-board jumpers,
8-46
+5V
Type
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
AIM 65/40 Graphics Printer
A65/40"0600
NMOS Interface (Input Voltage
Symbol
V ,H
V ,L
I'H
I,L
V OH
VOL
IDH
IOL
= +5.0V, TA = 25·C)
Parameter
Input High Voltage
Input Low Voltage
Input High Current
(V,H = 2.4V)
Input Low Current
(V'L = O.4A)
Output High Voltage
(lLOAO"" -l00A)
Output Low Voltage
(I LOAD "" -3 rnA)
Output High Current (Sourcing)
(VOH '" 2.4V)
Output Low Current (Sinking)
(VOL"" 0.4V)
Min
Max
Unit
2.4
-0.3
-100
5.0
+0.4
-300
V
V
I"A
-1.0
-1.6
rnA
2.4
5.0
V
-
0.4
V
-100
-
I"A
1.6
-
rnA
F.:OM=C2RE
TEST COJNT=00
o
1
~
~
....
...,.
, lEi:2: c'
g)
[;
,'.
i
2
::
~J
4
(~
.,
A
F G!
5
6
":'
8
9
A
B
C
" #
r:: ..
"t
?'!
::.
S
S
$
(; ,;.:
5 6
:: 4
....
r)
2
~-.
D
-
E F G H
F
'1;:
J K L ttt N 0
L
[
h
k
f1l
=c'
t u
'.'
'..}
~-,.f
)
e
"
::::::.
,''-'.
}J.
'il"
Z
iT
~
'T'
-)-
#
:f
'"
Ii
n
:!i
·3
·3
.§
t-·
.:.:
S.:.
~;'
oj
§
±
,t
+-.
't
"1
-'
B
.-.'
+
J
.~.
(
:. s
~
-'
:J
.....
~
If
':!!"
::: s
7
"
•.••
-
7.;:,
+
'~
,-
IT'
"\:,
F,
F>M
Move Number from Memory to ARG
Move Number from Stack to ARG
Move Number from Stack to FAC
Move Number from FAC to Stack'
FOUT Minimum Field Width Variable
FOUT No. of Places to the Right of the Decimal Point Variable
FABS
INT
Absolute Value of Floating Point Number
Truncate Floating Point NUmber
SGN
SIGN
SGN
FSIGN
Sign of FAC to FAC
Sign of FAC to ARG
FIN
FOUT
FCOMP
SQR
FPWRT
EXP
FCOMP
Compare Floating Point Number
SQR
Square Root
Raise to a Power
MINLN
DECLN
MIN-WIDTH
DEC-LENGTH
LOG
LN'
Move Number from FAC to Memory
M>A
ABS
INT
EXP
,Consecutive Exponent Polynomial
Move Number from Memory to FAC
Move Number from ARG to FAC
'Move Number fromFACtoARG
S>A
S>F
F>S
FIN
FOUT
LOG10
LOG
Function
MOVAF
CONUPK
Negate Floating Point Number
t
Sine
,Cosine
Tangent
-
Exponential
Common Log
Natural Log
a-64
Convert ASCII to Floating Point
Convert Floating Point to ASCII
A65/40:-7Q50
AIM 65140 Microcomputer Family
'1'
Rockwell
A65/40·7050·
. AIM 65/40 FORTH ROMS
FORTH LANGUAGE.
PRODUCT OVERVIEW
FORTH is a unique ,programming language well suited to a
variety of applications. Because it was originally developed for
real-time control applications, FORTH is ideal for machine and
process control, energy'managements, data acquisition, automatic testing, robotics and other applications where aSsembly
language was previously the only possible language choice.
The AIM 65/4.0 FORTH system, consisting of primitives,
interpreter, macro assembler and input/output functions, is contained, in two 4K-byte ROMs. These ROMs Plug into, sockets
Z70 and Z11 on .the AIM 65/40 Microcomputer Single Board
Computer (SBC) module. Linkage 10 the AIM 65/40 VO ROM
interfaCes FORTH to the AIM 65/40 peripherals (keyboard,
single-line display/video display controller and graphics printer)
and io user~defined functions. Interface with the AIM 65140
Debug Monitor and Text Editor ROMs supports machine level
debugging and editing of application programs written in FORTH.
Both interactive and batch modes of operation are supported.
Interaction operation allows FORTH words to be compiled and/
or executed as they are entered for immediate debugging and
operation. In the batch mode, FORTH words can be entered
into the Text Buffer then input to FORTH to. be compiled and/or
executed. Batc!1 mode allows an application program to be
easily edited using Text Editor line~and screen-orlented
commands.
.
FORTH actually provides the best of two worlds. It has the
looping and branching constructs of high-level languages
(DO ... LOOP, BEGIN ... END, IF ... THEN and IF ... ELSE
· .. THEN) and the code efficiency of machine and asSembly
languages. And programmers will be pleased to know that
FORTH allows you to specify addresses, operands and data in
hexadecimal, octai, binaiyor any other number base from two
to A(}-a distinct advantage over languages like BASIC, where
ali information must ,be in decimal.
In most time"Critical applications, at least part of the program
must be written in assembly language. FORTH has a built in
6502 macro assembler, and lets you drop into assembly languagea! almost any point in your program, without pera,rate
assembly arid load steps or awkWard machine level linkage.
FORTH programs typically run up ,to ten times faster than other
interpretive languages, and can even approach the speed of
machine language programs for some applications.
The AiM 65140 FORTH ROMs cari also be installed in an RM
65 Single Board Computer (SBC) module based. system
for either development or runtime operation. This is especially
attractive in OEM or end-user applications requiring a compact
RM 65 modular computer assembly. The RM 65 .
VO ROM, when also instal/ed In this configuration, supports
FORTH input/output operatlcn with AIM 65/40 periph~rals cCnnected ,to RM 65 input/oUtput modules. Vectored inpuVoutput
functions support user-defined interface functions, as well, In an
RM 65 installation. '
.
FEATURES
•
••
•
•
•
•
•
•
•
.•
•
•
•
•
•
AIM 65140 Microcomputer host and target
RM 65 SB,C module based system compatible
ROM resident for Immediate operation
Application oriented
Extensible language:
Over 20.0 pre-defined functions
Interactive compilation
Reverse polish notalion
Compact' memory uSl\ge
Fast execution '
Easy debugging
Stack implementation
16-bit words
Built-in structured macro ,assembler
Shortens software development time
ORDERING INFORMATION
Part No.
A65/4O-7050
A65/4.o·7.040
Deacrlptlon
AIM 65/4.0 FORTH ROMs
AIM 65/40 Math 'Package ROM
Order No.
21.03
2104
2113
Deacrlptlon
AIM 65140 FORTH User's Manual"'
AIM 65140 FORTH Reference Card"'
AIM 6S'40 Math Package User's Manual'"
NOTES:
1. Included with A65140-7.oS.o.
2. Included with A65140-7.o4O.
Document NO•. 29001D22
8-65
Data Sheet Order No. 0122
March 1983
A6~!40;'7050
AIM 65/40 FORTH ROMs
DEVELOPING FORTH PROGRAMS
FORTH WORDS
FORTH is built on subro,utine-like functions, called "words."
These words arl! linked together to form a, ','dibtionary," which
,is the central core of the language. Writing. a program in
'FORTH consists of using several predefined words to define
each new word. Once the new word has been added to the
system dictionary, it becomes as much a part of the language
as any other word that has been previously defined. In this
way new features and extensions can be added by simply
defining one or, more new words. Adding new features to
conventional languages like BASIC or Pascal requires the
language system, to be completely reassembled or
recompiled.
.
STACK MANIPULATION
a
FOATH is stack-oriented language, and is programmed in
RellersePolisll Notation (RPM), the notation that is used in
Hewlett-Packard scientific c,alculators: Using a data stack is
an extremely efficient way' of passingvariables back ,and
for'thbetWeen operations. A data stack' eliminates the neE!d
to tie up memory lOcations with variable tables, and allows
you to use only as much memory as you ne~d.
,S
:
VARIABLE
CONSTANT
CODE
a
;CODE
Begin oolon definition of ,.
End colon definition.
Create 'a varillble with in~ial
value n; retums address When
exabuted. "
Create conS\ant with value
n; returns value, when executed.
Begin definition of assembly-language
primitiv,,<>~ration ,
Used to create a new defining word,
with execution-time "code routine" for
this data type in assembly.'
UI!8!1 to create a new defining word,
with execution-time routine for this
data type in higher-level FORTH.
Create a user variable.
a
MEr,10RY
A,IM 65/40 FORTH contains both a single- (16:bit) and double(32~bit) precision integer arithmetic capability. In AIM 65/40
or RM65 applications where floating point a,rithmetic is
desired, the AIM 65/40,Math Package may be used in conjunction with the FORTH ROMs. These floating point functions may be called using FORTH words included in the math
package ROM. When this ROM is installed in so,cket Z63 Oil
the AIM 65/40 SBe Module, the floating point math words
can be automatically linked to, the FORTH dictionary during
FORTH il1itialization. The AIM 65/40 Math Package can also
be installed in either an RM 65 SBe module based system
for operation in the RM!i5 environment.
@
C@
CI
?
+1
CMOVE
FILL
ERASE
BLANKS
TOGGLE
MEMORY MAP , .
Fetch value addressed by top of stack.
Store nl at address n2. '
Fetch one byte only.
Store one byte only.
'Print contents of address.
Add SeCond numb's! on iliack to
contents of address on top.,
Move n3 bytes, starting at address nl to
,area starting at address n2,
Put byte 'n3irito n2 bytes starting at
address nl,
Fill n2 bytes in me,!T1oryw~h zeroes,
beginning at address nl.
Fill n2 bytes in memory with blanks,
beginning at address nl.
Mask memory with bifpattern.
NUMERIC REPRESENTATION
"
$COOO-$DFFF
$8000-$BFFF
$780·$7FF
$760-$77F
$700-$75F
$AB-$C4
$10-$A8
"
DEFINING, WORDS
FORTffprogramsare developed using "top-dowriibOttomup" techniques. That is, the programmer begins by defining "
the program in V$ry gene(al terms, t~Einsysiematit:allybreaks
these definitions down into more and more detailed submodules. VVhen the lowest levels of SUb-modules have been
defined, he'startst:odlng~ in F'ORTH,atthose levels,working
backup toward the top of the program, inpyramicj fashion.
Each sub-module is
stand-alone component of the pro- '
gram, and can be completely debugged without having the
complete program in the system. This' type of software
development is difficult, if not impossible, to do with most
other high-level languages.
Address (Hex)
~
Duplicate top of $lack.
, ,
Dupllcat~ top tv.iost~·~e'rT\s:{:~i'
Delete top of stac~;'
,,'
Deletetqp,twostack ~.ms.
Exohange top two stabk'items.
Copy second, item to top.
Rotate third item on top.
Duplicate only if non-zero
Move top item tP fet~tn.stack,
Retrieve item from return stack.
Copy top of returfl stapk onto stack.
Copy the nth item'to top,
Return address Of stack position
ReturnaddreS$qlreturn stack pointer. '
Convert "address' count" '10 "endaddress start-add~~$."
'
Print contents 01 stack,
DUP
2DUP
DROP
2DROP
SWAP
OVER
ROT
- DUP
>R
R>
R
PICK
SP@
RP@'
BOUNDS'
DECIMAL
HEX
BASE
DIGIT
Contsnts
FORTH Program
Math Package Program
Terminal Input Buffer
User Variable!!
FORTH User Variables
M,ath Pack,age Variables
FORTH Variables
o
1
2
3
4
a-S6
Set decimal ba~.
Set hexadecimal base.
Set number base.
Convert ASCII to binary.
The number zero.
The number one,
The number two.
The number three."
The number four. "
AIM 65/40 FQRTH ROMs
A65140-7050
FORTH WORDS (CONT'D)
CONTROL STRUCTURES
ARfTHMETIC AND LOGICAL
+
D+
1
MOD
IMOD
·/MOD
~I
U·
U/
M'
MI
MlMOD
MAX
MIN
+D+ ABS
DABS
NEGATE
DNEGATE
S- >D
1+
2+
1 -
2AND
OR
XOR
DO ... LOOP
DO: .. +LOOP
Add.
Add deuble-precision numbers.
Subtract (nl .- n2)
Multiply.
Divide (n1/n2).
Medulo (i.e., remainder from division).
Divide, giving remainder and quotient.
Multiply,then divide (nl·n2ln3), with
deubleintermediate.
like ·/MOD, but give quotient enly.
Unsigned multiply leaving double
product.
. Unsigned divide.
Signedmultiplicatien leaving deuble
product.
Signed remainder and quotient lrom
double dividend.
Unsigned divide leaving double quotient
and remainder lrom double dividend
and singl!, divisor.
Maximum.
Minimum.
Set sign. •
Set sign el double-precision number.
Absolute value.
Absolute value'll deuble-precision
number.
Change sign.
Change. sign 01 double-precisien
number..
Sign extend te double-precision
number.
lncreme(lt'value en tep ef stack by 1.
Increment value en tep 01 stack by 2.
Decrement value on tep of stack by 1.
Decrement value en top 01 stack by 2.
Logical ANa (bitwise).
Logical OR (bitwise)
Logical exclusive OR (bitwise).
Silt up loep, given inde.x range.
Like 00 ... LOOP, but adds stack
vahle III index.
'
I
Placs.current index value en stack.
LEAVE
T!lrini;,ate loep at next LOOP er
+LOOP.
BEGIN ... UNTIL
Loop SaCk to BEGIN until true at
UNTIL:
BEGIN ... WHILE
.loop while true at WHILE, REPEAT
. .. REPEAT'
'. kiops unConditionally to BEGIN.
BEGIN ... AGAIN
Unconditienal loop.
IF ... THEN
.;",' .. If top'of!ft.ack true, execute,folloy.ring
clause THEN continue; otherwise
coritinue 'at THEN.
IF ..• ELSE ... THeN
II top 01 staCk true, execute ELSE
clauSe TttEN centinue; et~rwi~ .
execute following clause, THEN
continue.•
END
Alias·for UNTIL.
ENDIF
Alias for THEN.
COMPILER-TEXT INTERPRETE.R;
[COMPILE]
COMPILE
LITERAL
DLiTERAL
EXECUTE
[
]
DICTIONARY CONTROL
CREATE
FORGET
HERE
ALLOT
COMPARISON OPERATORS
<
>
0<
0=
U<
NOT
TASK
True if nl less than n2.
True if nl greater than n2.
True II top twe numbers are equal.
True if tep number negative.
True H top number zero.
True if u1 less than u2.
Same a130=.
- FIND
DP
C,
PAD
IMMEDIATE
INTERPRET
MISCEI,.LANEOUS AND SYSTEM
«cemment>)
CFA
NFA
PFA
LFA
LIMIT
QUIT
Ferce compilatien ef IMMEDIATE werd.
. Cempilefellewing into
dictienary.
Cempile a number inte a literal.
Cempilea double-precisien nUl'!\ber inte
a literal.
.\
Execute the definitien en tep ef stack.
Suspend compilatien, enter execution.
Resume compilatien.
Begin comment (terminate by right
parentheses on saml! line).
Alter PFA to CF:A,
Alter PFA te NFA.
A~er NFA te PFA.
Alter RFA toLFA.
Top ef memery.
Clear return stack and return te
terminal.
LATEST
LIT
CLiT
LITERAL
SMUDGE
STATE
8-67
Create. a. c;lictienary header.
FORqET all definitiens from
. 'on..
' . '
Returns address ef next unused bYte in
the. dictionary.
Leave a ~ap of il bytes in the
dictionary .
A dictiQnary marker.
Find the address el in the
dictlQna,ry •
Search dictionary fer .
User variable containif'!g the dictionary
pointer.
Store, byte into dictienary.
Cemplle a number into the dictionary.
Peinter. to. ~mporary buffer.
. Force execution when cempiling.
The "Fext lilIerpreter executes or .
compiles.
Lellve name field address (NFA) ef top
word in CURRENT.
PIBCII 16-bit literal on the stack.
Place byte literal en the stack.
Compile a 16-bit literal.
Toggle name SMUDGE bit.
User variable containing compilation
state.
AIM 65/40 FORTH ROMs
A65/40·'7050
FORTH WORD$(CONT'D)
OUTPUT FORMATTING (CONT'D)
USERVARIABLES
U?IN
U?OUT
U?TERMINAL
U-CR
UABORT
UB/BUF
UB/SCR
UC/L
UCLOSE
UCR
UEMIT ,
UFIRST" ,
UKEY
ULIMIT
User variable for ?IN.
Usar variable for ?Ol,lT.
Usar variable for ?TERMINAL.
Usar variable for oCR
.
Usar vari8b1e for ABORT.
Usar vaiiaIJle for B/BUF,
U$l!trvariablefor B/SCR.
Usar variable for C/L.
Usar V/lfiabl$ for CLOSE.
Usar variable for CR. •
Usar variable for, EMIT:
\Jaer variable iOrFIRsT.
UI!8( v:a'tlable forKEY,
User Variable for.LI~IT.
MONITOR
&CASSETTE
I/O
,;"
"
'-COLD
MON
CLOSE
?IN,
?OUT
GET
PUT
READ
WRITE
SOUFICE
FINIS
AIM 66/40 FORTH (lold start.
Exit to AIM 65/40 Monitor.
, 'ClOse tape file,.
set to active inpl.ll device (AID),
set to activ~ Q""putdel(ice (AOO).
Inp,ut a character f19m the AID.
Output a characier to the ADD,
Input n2 characters from AID iO:
address nl.
Outputn2' characters to AOD at
address nl,
Compile from tl;le ,AID,
Termlnate'complete from SbU,RCE,
INPUT-OUTPUT
oCR
CR
SPACE
SPACES
CLRLlNE
DUMP
TYPE
?TERMINAL
KEY
EMIT
EXPECT
WORD
IN
BAUD
Bl
C/L
TIB
QUERY
10:
HANG
Output CR to printer only.
Carriage return,
Type one space,
Type n spaces.
Output a CTRL B.
Print textstring,(terminated by").
Dump n2 words starting at address. ,
, . Type $tringof nl characters starting at
address n2.
True if terminal break request present.
Read key,put ASCII value on stack.
O~tput ,ASCII value from stack.
Read nl characters from input to
address n2.
Read one word from input stream, until
: dellinlter,
'
Usar virlable contained within TIB.
set BAUD rate. (See Note 1-)
OUtput a SPACE character.
Number of characters/ilne.
Pointer to terminal input buffer start
,address,
,
Input ield from terminal.
'Print from name # field
address (nfa),
Wait for keystroke,
<#
#S
SIGN
#>
HOLD
HDL
- TRAILING
.L1NE
'
COUNT
.R
0,
D,R
DPl
Convert string at address to doubleprecision number.
Start output string.
Convert next digit of double-precision
number and add character to output
string,
'
Convert all significant digits of doublepreciSion number to output string,
Insert sign of n into output string.
Terminate output string (ready for
TYPE).
Insert ASC,II character into output
string.
Hold pointer, user variable,
Suppress trailing blanks,
Qisplay line of text frOm mass storage,
Change length of byte string to type
form.
'
''Print number on top of stack.
Print number nl right justified n2
places,
Print double-precision number n2 n2.
Print double-precision number n2 nl
right justified n3places.
Number of digits to the right of decimal
, point:
VOCABULARIES
Returns address of pointer to
CONTElq· voeabulary.
Returns,address of pointer to
CURRENT
,CURRENT vOcabulary,
Main, FORTH vocabulary,
FORTH
Assembler vocabulary.
ASSEMBLER
Set CURRENT vocabulary to
DEFINITIONS
CONTEXT.
VOCABULARY Create new vocabu'lary.
Print names of all words in CONTEXT
VLIST
vocabulary.
Most recently defined vocabulary.
VOC-LINK
CONTEXT
VIRTUAL STORAGE
LOAD
BLOCK
B/BUF
B/SCR
BlK
SCR
UPDATE
FLUSH
EMPTY-BUFFERS
+BUF
BUFFER
RW
USE
PREV
OUTPUT FORMATTING
NUMBER
#
FIRST
OFFSET
-->
;S
load mass storage scraen (compile or
execute).
'
Read mass storage block to memory
address.,
System COnstant giving mass storage
block size In bytes,
Number of blocks/editing screen,
System variable containing current
block number,
System variable containing current
screen number,
Marklast buffer accessed as updated~
Write all, updated buffers to mass
storage.
EraSe all buffers.
Increment buffer address,
Fetch next memory buffer.
User read write linkage,
Variable comaining address of next
buffer:
Variable containing address of latest
buffer.
.
Leaves address of first block buffer,
User variable block offsat to mass
storage.
Interpret next screen.
Stop interpretation.
A65/40-7050
AIM 65/40 FORTH ROMs
FORTH WORDS (CONT'D)
PRIMITIVES
OBRANCH
BRANCH
ENCLOSE
RO
SO
RP!
SP!
NEXT
SECURITY
Run-time conditional branch.
Run-time unconditional branch.
Text scanning primitive used by WORD.
Location of Return Stack.
Location of Parameter Stack.
Initialize Return Stack.
Initialize Parameter Stack.
The FORTH virtual machine.
!CSP
?COMP
?CSP
?ERROR
?EXEC
?PAIRS
?STACK
ABORT
ERROR
MESSAGE
WARNING
FENCE
WIDTH
Store stack position in check stack
pointer.
Error if not compiling.
Check stack position.
Output error message.
Not executing error.
Conditional not paired error.
Stack out of bounds error.
Error; operation terminates.
Execute error notification and restart
system.
Displays message.
Pointer to message routine.
Prevents forgetting below this point.
Controls significant characters of
.
MATH PACKAGE FORTH WORDS (A65/40-7040)*
FLOATING POINT ARITHMETIC
F+
FF"
F/
USER VARIABLE
MIN-WIDTH
Adds two floating point numbers.
Subtracts one floating point number
from another floating point number.
Multiplies two floating point numbers.
Divides one floating point number by
another floating point number.
DEC-LENGTH
Specifies the minimum field width to be
output.
Specifies the number of places to the
right of the decimal point to be
output.
ASCII/FLOATING POINT CONVERSIONS
UTILITY, SIGN AND COMPARISONS
FABS
INT
SGN
FStGN
FCOMP
FIN
Takes the abSolute value of a floating
point number.
Truncates a floating point number to an
integer.
Converts the sign of a floating point
number to a floating point number.
Gets a value corresponding to the sign
of a floating point number.
Compares the value of a compacted
number in memory to a floating point
number.
FOUT
FORMAT CONVERSION AND DATA MOVING
M>F
F>M
M>A
POLYNOMIAL
POLY
POLYODD
Converts a number in memory from
ASCII to floating point format.
Converts a number from floating point
to ASCII.
S>A
Evaluates a polynomial with
consecutive exponents.
Evaluates a polynomial wtth odd
exponents.
S>F
F>S
Unpacks the compacted number in
memory to floating point.
Packs the floating point number to
compacted format and stores the
result in memory.
Unpacks the floating point number in
memory.
Converts an integer to floating point
format.
Converts an integer to floating point
format.
Converts a number from floating point
to an integer.
EXPONENTIAL AND LOGARITHMIC
SQR
>
EXP
LOG
LN
TRIGONOMETRIC AND UNITS CONVERSION
Takes the square root Of a floating point
..
number.
Raises on~ floating point number to the
power of another floating point
number.
Raises the transcendental number e to
the power of a floating point number.
Computes the logarithm to the base 10
(i.e., common log) of a ftoating point
number.
Computes the logarithm to the base e
(i.e., natural log) of a floating point
number.
SIN
COS
TAN
ARCTAN
DEGREES
RADIANS
'Requires AIM 65/40 FORTH ROMs be resident.
8-69
Calculates th& sine of a floating point
number (in radians).
Calculates the cosine of a floating point
number (in radians).
Calculates the tangent of a floating
point number (in radians).
Calculates the arc tangent of a floating
point number.
Converts a floating point number from
radians to degrees.
Converts a floating point number from
degrees to radians.
A65/4O,-7952
AIM 65140 Microcomputer Family
'1'
Rockwell
A65/40-7052
AIM 65/40 FORTH TARGET COMPILER
FORTH LANGUAGE
FEATURES
FORTH is a unique programming ,language well suited to a
variety Of applications. Originally developed for real-time control
applications, FORTH has feature,s that make ~ ideal for machine
and process control, energy management, data acquisition,
automatic testing, robotics and other input/output intensive
applications where assembly language was previously considered to be the only possible language choice.
• Fully compatible with FORTH, programs developed with AIM
65 or AIM 65140 FORTH Interpreter ROMS
• Disk-based compiler operation with vocabulary overlays for
-Text Editing
-Disk Interfacing
-Serial Input/Output
-Compiling
-Special Utilities
FORTH actually provides the best of two worlds. It has the
looping and branching cOnstructs of high-level languages (00
... LOOP, BEGIN ... END, IF ... THEN and IF ... ELSE
•.. THEN) and the code efficiency of machine and assembly
languages. FORTH allows programmers to specify cWdresses,
operands and data in hexadecimal, oCtal, binary or any other
number base from two to 4O-a Qistinct advantage over languages like BASIC, where all information must be in Qecimal.
• Easy compiler operation
-Load screen direction
-Compile traGing (mapping)
-Compiles to!'lA\'t1 andlor dis/<
• IncIL:lQes 6502 Macro Assembler with
-Forward references'
-Symbolic labels
-Relative branches
• Efficient object code generation
-ROMable object code
-Standalone oPeration"
-Minimum runtime nucleus
-Optimized FORTH compiled vocabulary
-User-specified origin
FORTH TARGET COMPILER
The FORTH Target Compiler generates object code from application programs written in FORTH. The object code is a compiled
composite of the user's application vocabulary and those portions
of the Target Compiler nucleus necessary to support the application vocabulary. The disk-based FORTH Target Compiler
operates on the AIM 65/40 Microcomputer in conjunction with
the AIM 65140 FORTH Interpreter ROMs, the RM 65 Floppy
Disk Controller (FDC) module and the AIM 65/40 BDOS 1.0
Upgrade Kit.
• Flexible target computer installation
-System indepenQent (runs on any 6502 CPU-based system
with minimal runtime memory map requirements) or
-AIM 6514O''Or RM65110 ROM autostart capability
ORDERING INFORMATION
Part No.
AIM
AIM
AIM
AIM
The compiled object codE!' located at a user-specified origin with
optional auto-start vectors, will execute in any 6502 CPU-based
microcomputer system supporting the runtime nucleus memory
map requirements, Application programs can also be Qeveloped
to run on AIM 65140 or RM 65 sec module-based systems with
supporting RM 65 memory ,and input/output modules,e.g.,
Analog Input/Output, IEEE:488 Interface, and Multi-function
Peripheral Interface. Linkage to RM 65 Floppy Disk Controller,
CRT Controller, and JEEE-488 module, as well as the AIM 65/
40 110 and Math Package, firmware can also be included for
expanded application systems.
Deacrlptlon
AIM 65/40 FORTH Target Compiler
AIM 65/40 FORTH Interpreter ROMs")
AIM 65/40, BOOS 1,,0 Upgrade Kit","
AIM 65/40 Math Package AOM'"
65140-7052
65140-7050
65/40-7092
65/40-7040
' 08i1crfptlon
OrdarNo.
2105
2103
2113
"
AIM6S and AIM 65140 FqRTH Target
' Compiler Users Manual'"
'AIM 65/40 FO~H Users Manual")
AIMa5/40 ~att1,Packlige Users Manual'"
Notes:
Required for FORTH Target Compi~r operation.
Requires RM65-5101NE 'FOC module.
Included wtth A6514O-7052.
Includedwnh A6514O-70S0.
(5) Included wnh A65I4O-7040.
(6) OPtional
(1)
(2)
(3)
(4)
Document No_ 29001019
8-70
Data Sheet Order No. 0119
Rev. 1, January 1984
A6S/40-7052
AIM 65/40 FORTH Target Compiler
DEVELOPING FORTH PROGRAMS
FORTH is built on subroutine-like functions, called "words."
These words are linked together to form a "dictionary," which
is the central core of the language. Writing a program in FORTH
consists of using the dictionarY words to define each new word.
Once the new word has been defined it is added to the system
dictionary and it becomes as much a part of the language as
any other word that has been previously defined. In this way
new features and extensions can be added by simply defining
.
one or more new words.
Nucleus. The ,compiled byte count will generally be less than
the separate application/interpreter byte count.
FORTH TARGET COMPILER OPERATION
The disk-based, two-pass, FORTH Target COmpiler compiles
object code in one of two modes: BIG.COMPILE or QUICK.
COMPILE. The QUICK.COMPILE mode compiles the entire
object code directly to RAM then saves the compiled code on
disk. The BIG.COt\4PILE mode compiles to 1K-byte buffer areas
in RAM. When the buffer is full, the buffer contents are transferred to disk then compilation continues. The BIG.COMPILE
mode optimizes object code RAM requirements although it compiles slower than the QUICK.COMPILE mode.
FORTH is a stack-oriented language, and is programmed in
Reverse· Polis11 Notation (RPN), the notation that is used in
Hewlett-Packard scientific calculators. A data stack is an
extremely efficient. way of passing variables back and forth
between operations and eliminates the need to tie up memory
locations with variable tables.
Operation of the compiler is directed by one or more LOAD
SCREENS. This technique provides the user with complete
control of compiler variables, origin statements, cold start vectors and utility. routines. The LOAD-SCREEN(s) then specify
which user screens to compile and in what order.
FORTH programs are developed using "top-down/botlom-up"
techniques. That is, the programmer begins by defining the program in very general terms, then systematically breaks these
definitions down into more and more detailed sub-modules.
When the lowest levels of sub-modules have been defined,
FORTH coding begins with those levels, working back up toward
the top of the program, in pyramid fashion. Each sub-module
is a stand-alone component of the program, and can be
debugged without having thecolnpleteprogram in the system.
The interactive nature of FORTH supports this time efficient
development technique.
FLOATING POINT OPERATION
The FORTH Target Compiler provides both single-precision
(16-bit) and double-precision (32-bit) single integer arithmetic
functions. If floating point arithmetic is desired, code words can
easily be defined within the application program to link to extemal
floating point subroutines. The AIM 65/40 Math Package ROM,
located at address $8000-$8FFF can be installed in the application system. Alternatively, user-defined floating point functions may be linked to or even provided within the code
definitions.
In most time-critical applications, at least part of the program
must be written in assembly languages. FORTH has a built-in
6502 macro assembler, and allows assembly language coding
at almost any point in your program, without separate assembly
and load steps or special machine level linkage. FORTH programs typically run up to ten times faster than other interpretive
languages, and can even approach the speed of machine language programs for some applications;
SYSTEM REQUIREMENTS
The AIM 65/40 FORTH Target Compiler operates in an AIM
65/40 Microcomputer with 32K bytes RAM in conjunction with
an RM 65 FDC module with an AIM 65/40 DOS 1.0 or BOOS
1.0 ROM Installed on the FOC module. The following table lists
two configurations of AIM 65/40 and RM 65 hardware and firmware which may be used. Other configurations can be easily
composed depending on the user's development and application requirements.
The application program is developed, debugged and integrated
with the user interface using the ROM-based FORTH Interpreter. After program validation, the application is compiled into
stand-alone object code with only required portions olthe Target
F,lequll8Cl
Perlpherala!
Firmware
RM65-7141E
Host Computer
AIM 65!40-2OOO (AIM 65!4O SBC Modu1!l with
32K RAM, Monitor ROMS, Extendild
Keyboard, and VDC Module)
FiM 65 Cable AOapler &. Buffer
Module lor AIM 65/40 .
X
RM65-7004E
RM 65 4-Slol Card Cage
RM65-5101NE RM 65 Floppy Disk Controller (FOC)
Module (Without ROM)
AIM 65140 OOS 1.0 ROM, or
A65/ 40-7090
AIM 65/40 BOOS 1.0 Upgrade Kit
A65/ 40-7092
A65-40-704O
AIM 65140 Math Package ROM
A6514O-7050
AIM 65140 FORTH ROMs
Floppy Disk Drives (2)
A65/40-1315 (AIM 65140
Mlcrocomputar System
-Strlee 1000)
X
X
X
X
X
X
X
optional
X
optional
X
X
CRT Monitor
Notes: X = Required in addition to host microcomputer.
8-71
-
X
X
X
D
"
AiM 65/40 FORTH Target'Compiter
FORTH WORDS
GENERAL PURPOSE VOCABULARY
The following FORTH words are provided in addition.to t/Jose
provided in the A65/40-1050 FORTH Interpreter ROMs (refer
to Data Sheet No. 0122).
ABORT'
Prints TEXT il a run-time error Occurs,
20VER
ASCII
During compile time; places aCLlTand
theliterahalue 01 CHAR iQthe dictionary,
Inimmedi~te mode. retums the ~SCII
value on the stac~.
2swAp
COMBINE
.Combines I~ byte 01 I and' high byte 01 h
to form n.··
-TEXT
Compares strings at ADDR1,'ahd ADDR2
lor Ii bytes. Returns ''''1 if same.
..
COMPILING
Activates the Compiler Vocabulary Overlay.
?OEF
IF NAME
?RANGE
Returns f;1 if n2L1NE#
Returns the current cursor IIne#.
MISCELLANEOUS COMMANPS
(DELETE)
Referring to the current cursor posftion,
deletes n preceding characters and calls
UPDATE.
BUF-MOVE
Mova non-nUll contents of PAD to ADDR.
E
Erases the string, in front of the cursor for a
length equal to the string in FIND-BUFF.
Copie5the referenced line number into
INSERT-BUF and UPDATE.
R
(KILL)
Blanks line# and UPDATE.
S
(PUT)
Replaces the current line wfth contents of
INSERT-BU/!.
?
Prints the currerit line wfth the cursor at
current cursor position and the line number
at the end of the line.
CURSOR COMMANDS
R#
Returns the cursor position (n).
Searches the current line after cursor
posftion for a match to contents of FINDBUF. Reposftions cursor to ft If a match is
foUnd and sets f= 1. If no match is found,
sets 1=0 and positions the cursor to the
next line.
.
#LOCATE
Returns byte positiOri of cursor and line
number.
»
Adds n to cursor posKion and displays the
line.
x
(HOLD)
1LINE
Replaces string identified by FIND-BUFF
with~XT.
8-73
Beginning at currenl screen and continuing
through screen #n. saarChes for a ·&Iring
match io TEXT and displays match
occurrences.
A65140,7052
1.
AIM 65/40 FORTH Target Complier
I'
FORTH WORDS (Continued)
Takes text from InpUt straam until DUMI.ter
charaqtElr Is ancount,rad (66 characters
maiclrrtum). MoVes, !ext to,PAQ. and fills to ....
~ characterS wfth blanks ( $ 2 0 ) . '
ORIGIN
C9mpller's target dlctiqnary.
FAST.COMPILE
Target space will be RAM only, based on
WINDOW,LO and WINDOW.HI.
USE
Displays CHAR a8 theeursor,
BIG. COMPILE
Target space maybe virtual data space on
disk.
.
WHERE
DiapiaysWhere en arror In LOADing
occurred. AISd IIhows context and currant,
CLEAR.TARGET
Fills the target area with zaros.
TEXT
READY
.TARO.ET COMPILER VOCABULARY
OVERLAY
START
. Defines names (n the object code.
LOCALS
Deflneawords al"i:ornpjle time only.
MAGICS
Immediate words,
,
< '
'~,
LABEL
For U$8 in assembJylanguaga to provide
flexibility and allow code sharing.
VARIABLE
II ROMAEiLE Is true, VARIABLE becomes
a USER vlrrabl$, otherwise variable Is
Identical to ROM~~d FORTH.
BYTES
Sets BSidebytas In RAM araa (like
ALLOT).
RAM
Equivalent to ROM command HERE.
Returns currant RAM addrass.
BCC, BCS, BNE,
BEQ, BPL, BMI,
BVC, BVS,
Relative branch opcodes for assem.bly
operation.
I
sWitcb
state to OFF,
;,,\,".
"
Prints or dI8pl*ys.the~ame and CFA of
eaCh WQRD "t"""
wtlen 'Orested.
,.
"~"Ins the compU~tlon, Everything.
Generates an. efluate type statement.
Changes switch alate to QN.
~ :i',.
.
DEFINING ·WORDS
SWITCHES .. FLAG WQ~DS(d~I". IICfIVe du~lng compile)
. Changes
."
following this command will be Interprated
or compiled .In the simulated target
m.~hine enVir:,"
Suppresses most non-fatal error
messages.
Automatic forward referance for undefined
words.
Values must be praceded by a. valid
decimal cha~er to be a valid number.
MAGIC WORDS
Generates read-only code.
DLITERAL
Compiles a double number In line.
ASCn
Complies CLIT of following ASCII
character.
DOES>
Immediate word to separate into TARGET NUCLEUS and
Target Compiler.
;CODE
Identical to CODE but also sets a pointer
for LOCATE.
LOCATE
Inform.s the compiler where the execution
time CODE Is located.
Forces rorward'referaF\C8 of, the, name
Immediately follciwing.
Name field length (headerlesscode).
Changes the vlliue 01 FORTH user
constants.
~flnes the Tatget addrass space
.boundaries.
Defines the target buffer block number.
REVEAL
ld8ntlftes nucleus RAM boundaries.
Extends from RAM.LO for J.)SER.SIZE
bytes.
HIDE
Number of bytes reserved begiMing at
RAM ..LO.. RAM between RAM.LO + .
USER.SIZE andRAM.Hlls used for wotk
buffers (PAD, e!c~) when ROMABLE flag Is
set.
.
8-74
SI~lIa; to$MUQGE.
Sets the !!MUDGE bit on the last target
·.word.
A65/40·7090
if
(
AIM 65140 M/f'.,mf'.,nmnut••,
'1'
A65/40-709,O, "
','
AI,M 85/40 DISKOPERATING,:S'l$TENf:
VERSION t.O (DOS 1.0) ROM "::i(,,
Rockwell
DISK OPERATING SYSTEM
FEATURES
A disk operating system (DOS) provides a stand,ard Interfaoe
between the useI' and oneormo!'B ftoppydisk drives, floppy disl<
control (f.PC) hardware and ~x8cutive, level software. The DOS,
implemented in software, allows program and data files to be
opened, closed, read and written underoperalor or program
control. In an Interactive eiWironment, commands are usually
Initiated by the operator from the keyboard in response to user
friendly prompts displayed by the system.
• AIM 65/40 Microcomputer compatible
• ROM resident for Immediate operation
• Installs on-board RM 65 Floppy Disk Con~roller (FDC) modLll!a
.' Prollides mass storage of programs and data "
,'
• Compatible with AIM 65 high level language, and Assembler
ROMs
.
"
• Disk oriented commands (format, list"backup)
• File oriented commands (list, delete, recover)
• Input/Output commands
-Read and write text and pbject code
-Automlitlc file open and close '
• User-alterable variables
-Utility furlction and error handling vectors (before and after
DOS functions)
,-Error handling vectors (before and after DOS functions)
-Ihput/output vectors
'
,
• Extens,ive error, detection and reporting
PRODUCT OVERVIEW
The AIM 65/40 Disk Operating System VersIOn 1.0 (DOS 1.0)
provides disk and file management fuilctions for the AIM
65/40 Microcomputer In conjunction with an RM 65 Floppy Disk
Controller (FDC) module. With this configurlll!gn, mass storage
files can be easily ,manipulated wtiencohnected, to one to four
5W' or 8" floppy disk drives. ,DOS 1.0 functions, contained on
a 4K-byle ROM that' plups into the FDC module,
available
Immediately upon computer power lum-on Without waiting for
separate loading of a disk-based DOS into RAM.
'
are
MEMORY MAP
",
Add ...... (Htx)
DOS. 1.0 functions are operator commandable through interaCtive AIM 6514Q Debug Monitor/Text Editor operation as well
as language (assembler, compiler and/or Interpreter) operation.
Text and program s6,urce cai;!e may be written to, and read from,
disk with the Editor, List al'l,d Read commands, resPectively.
'Binary data an~pi'ogramobject code may be written to, and
loaded from, disk using the, Debug Monitor Dump and Load
commands, respectively. FIles containing sourcellnd object
code for application programs written in AIM 65/40 Assembler,
BASIC, and FORTH languages are therefore supported. In
addition, utllily functions format a disk, list the contents of the
disk directory, delete a fRe, recover a file and backup Ii diSk ,upOn
command. The DOS functiOns may also, be called under program control by theappliclition program ,Into order to read ,and
write data flies.
' '
,.
"
$8FOO·$8FFF
$8oob'$SEFF
$SEOO-$3FFF
$500-$563'
$4AO-$4FA
$D7·$DE
Contelllt
RM 65 FDC Module I/O
DOS 1.0 Program
DOS 1.0 VO Buffer (defau~ location)
DOS 1.0 Variables
DOS ,1.0 Variables
DOS 1.0 Variables
ORD~RING INFORMATION
P.rt No.
A65/40-7090
RM85·5101NE
,"
Disk read Qr write errors,' both at the DOS and FDC hardware
, 'Jevel,' are reported upon,dJlteCtlon.·User-alterable variables allow
changing ofdelBult values to aJ)J'Jlication unique values.
OnlerNo.
802
DellCrtptlon
AIM 65140 DOS 1.0 ROM '
RM8S FOC Module (without ROM
pontainl!ig primitive $ubioutines'2I) ,
DellCrlpllon
RM65 FOe Mod!J1e User's Manual'l)
NOTES:
1. Describes user's instructions for AIM 65140 DOS 1.0.
Included with A65I40-7090 arid RM65-5101NE.
2. The DOS 1.0 ROM Includes "primitive subroutines In addition
to OOS functions.
'Oisks formatte~1lY AIM 65/40 DOS 1.0 are compatible with AIM
'65 DOS 1.0 and AIM 65/40 BOOS 1.0. FiJes written by any of
'these DOS prpgrams may therefore' be read by either
microcomPliter. '
Q4Jcument No; 29001 D16
8-75
Data Sheet Order No.D116
March 1983
A65/40-7092
AIM 65140 Microcomputer Family
'1'
Rockwell
A65/40-7092
AIM 65140 BOOTSTRAP DISK OPERATING
SYSTEM VERSION, 1.0 UPGRADE KIT
DISK OPERATING SYSTEM
FEATURES
A disk pperating system (DOS) provides a standard interface
between the user and one or more floppy disk drives, floppy disk
control (FOC) hardware and executive level software, The ~OS,
implemented in software, allows program and data filEl'S to be
opened, closed, read and written under operator or program
controL In an interactive environment, commands are usually
initiated by the operator from thi! keyboard in response to user
friendly prompts displayed by the system.
•
•
•
•
•
PRODUCT OVERVIEW
• Input/Output commands
-Read and write text and object code
-Automatic file open and close
AIM 65/40 Microcomputer compatible
ROM resident for immediate operation
Installs on-board RM 65 Floppy Disk Controller (FOG) module
Provides mass stor'!ge of programs and data
COmpatible with AIM 65 high level language and Assembler
ROMs
• Disk oriented commands (format, list, backup)
• File oriElnted commands (list, delete, recover)
The AIM 65/40 Bootstrap Disk Operating System Version 1.0
(BOOS 1.0) provides disk and file management functions for the
AIM 65/40 Microcomputer in conjunction with an RM 65 Floppy
Disk Controller (FOC) module. With this configuration, mass
storage files can be easily manipulated when connected to one
to four 51f4" or It floppy disk drives. BOOS 1.0 functions" contained on a 4K-byte ROM that plugs into the FO.C module, are
available immediately upon computer power turn-on without
waiting for separate loading of a disk-based DOS into RAM.
• User-alterable 'variables
-Utility function and error handling vectors (before and after
DOS functions)
-Input/output vectors
-I/O buffer vectors
• Extensive error detection and reporting
MEMORY MAP
The AIM 65/40 BOOS 1.0 provides a bootstrap and autostart
capability in addition to the same functions as AIM 65/40 DOS
1.0 (A65/40-7090). It is also located higher in memory than AIM
65/40 OOS 1.0 to a/locateRAM at $8XXX to disk-resident
system or application software. If neither AIM 65/40 Debug
Monitor nor BASIC Interpreter ROMs are installed, a bootstrap
function can be read from the disk and executed to load and
autostart an application program. The BASIC or Debug Monitor
command level will be entered if the AIM 65/40 BASIC or Debug
Monitor ROMs are installed (BASIC overrides the Debug Monitor) unless overridden by an application autostart via the AIM
65/40 VO ROM. AIM 65 BOOS 1.0 does not contain DMA routines, however, indirect vectors are provided for user addition.
Address (Hex)
$EOOO-$EFFF
TOP OF RAM
$500'$563
$4AO-$4FA
$D7·$DE
Contents
DOS
DOS
DOS
DOS
DOS
1.0 Program
1.0 I/O Buffer
1.0 Variables
1.0 Variables
1.0 Variables
ORDERING INFORMATION
Part No.
Disks formatted by AIM 65/40 BOOS 1.0 are compatible with
AIM 65 DOS 1.0 and AIM 65/40 DOS 1.0. Files written by any
of these DOS programs may therefore .be read by either
microcomputer.
A65/40· 7092
RM65-5101NE
Description
AIM 65/40 BOOS 1.0 Upgrade Kit
RM 65 FDC Module (without ROM containing
primitive subroutines")
Order No,
The upgra,de kit includes:
2152
288
280
262
For installatiol! on RM 65 FOe Module
AIM 65/40 BOOS 1.0 ROM
FOC Module addressing PLA (495R23-003)
Description
AIM
AIM
AIM
AIM
65/40 BOOS. 1.0 User's Manual")
65 Monitor/Editor Program Listing
65/40 System User's Manual
65/40 I/O ROM Program Listing
Notes:
I, BOOS 1.0 ROM in upgrade kit includes primitive subroutines
in addition to DOS functions.
2. Included with A65/40-7092
For installation on the AIM()5/40 sse Module
AIM 65/40 I/O ROM Vl.l (R32T3-14)
AIM 65/40 Monitor/Editor ROMs Vl.l
(R32U5-13 and R32U6-13)
Oocument No. 29001029
8-76
Data Sheet Order No. 0129
Rev. 1, January 1984
SECTION 9
RM65 MICROCOMPUTER·MODULE FAMILY
page
Product Family Overview ................................................. .
9-2
RM65-1000E Single Soard Computer (SBC) Module ........................... .
9-3
RM65-0110 110 ROM ..................................................... .
9-7
RM65-0122 Run-Time BASIC INTERPRETER ROM .................... ; ....... .
9-8
RM6S-0152 Run-Time FORTH ROM ........................................ . 9-10
RM65-2901E PROM Programmer Module ................. : ...... ',' .......... .
9~J5
RM65-3108E 8KStatic RAM Module ........................................ .
9~21
RM65-3132E 32KDynamic RAM Module .................................... . 9-25
RM65-3216E 16K PROM/ROM Module ....... , ............................. .
9-29
RM65-3264NE Univeral Memory Module ....................•.............. ,.. . 9"33
RM65-5101EFloppy DiskControHer(FDC) ..Module." .. , ........................ .
9~37
RM65~5102E CRTCdntroller (CRTe) Module .. : " ' c '
9::43,
•••••••.• , •••••.•••••••••.••
RM65-5104E Direct Memory Access Controller Mo(:lu\e .... ; ., .................. . 9-49
RM65·5222E General Purpose InputiOutput(GPIO) and,Timer Module .... , ....... . 9-54
RM65.5223E Multi-Function Peripheral Interface(MPI)Module ..... "....... ' ....•...
RM65-5302E and RM65-5303E Analog Input MPdule ahd
Analog, InputiOutputModule .......' .. ,. ,.,::. >.c... ;,....•..........
,
.
9-58
, ........ . , 9-63
RM65-5451 E Asynchronous Communications IQterface Apl;lpter(AC,IA) MOdule ..•...
9-69
RM65-1004E and Rfvl65-7004NE4-Slot Piggy,ba,ckModule Stack,and Motherboard ...
9-73
Rfvl65-700BE and RM65-7008NEB-Slot ,CardClilge,andMotherboard;., ... , ..
9-78
RM65-70'16E
andRM65~70t6NE
16-SlotCard qage
andMo~herMard
•.. : ........• 9"83,
RM6S-7101E SingleCardAdapter Module for AIM 65 ...... ',' ..•. , ...... , .... ; ... : 9-88
RM6~;'7102EI,EEE-4B8 Bus Inter~ace Module ........................ ; .•........ 9-94
RM65-7104E AdlilPter/Buffer Module for AIM~5 ...... ' •.. : .... : ............: : .. . 9-99
RM65-7H6E RM65 Cable Driver Adapter/Buffer Module forAIM65 ........ : ...... ·9-105
RM65,-7141E AdaptElI" Cable and Buffer Moddle for AIM 65f40 ......... '" ........ 9-111 .
RM65-7201E Design Prototyping Module ..•..• ~ .~ .............................. 9-116
RM65-7211E Extender Module .. , ........... ; ......,: ............ : ........... 9-120
9·1
m
RM 65 MICROCOMPUTER MODULE FAMILY
Standard Boards Cut Design Costs, Offer Flexibility
RM 65 microcomputer modules offer a Simple solution io
designing hard working blue collar microcomputer systems.
You start with an R6502 based single board Eurocard-sized
computer. Then you add functions, exactly as required, with
additional Eurocards. Program your system in either FORTH
or BASIC, control essentially any peripherals the system
may need. There's no more optimum way to quickly and
economically put together prototype and small to medium
run systems.
The RM 65 family includes a single board computer,
memory, general purpose 110, intelligent peripheral
controllers and accessory modules, Silicon software
supports the family with BASIC, FORTH and peripheral
drivers. Plus, the family includes card cages, buffers,
adapters, cabling, extender module, everything needed
for complete system implementation.
The RM 65 microcomputer modules are all Eurocard
sized, 100 mm x 160 mm. Memory modules include 8K
static RAM, 32K dynamic RAM, 16K PROM/ROM and a
PROM programmer. ROMs include 110, BASIC and FORTH.
There is an IEEE-488 module, general purpose 110 and
timer module, ACIA module, and a multifunction peripheral
controller module.
An analog input/output module allows an RM 65 system
to interface with thermocouples, strain gages, pressure
sensors and similar analog devices. Floppy disk and CRT
controller modules allow RM 65 systems to drive displays
and removable,memory. A direct memory access controller
allows RM 65 systems to have high data transfer rates
'
,
when needed,
Since the I'IM,65 blue collar family is designed around the
R6500family, systems can be readily redesigned into
R6500 devices as volume or application warrant;,RM 65 lets
you design custom systems with stand;;trd boards, buying
only What you need, when you 'need it.
9-2
RM65-tOOOE
"1
'1'
", • .
.'
.
RM65-1000E
.
RM65 SINGLEBC)ARD COMPUTeR"
(sec) MODULE'
Rockwell
MleROCOMPUT~R
RM 65
'h'
MODULES
FEATURES
The RM65-1000E Single Board Com~;rte~ Module iso~e ofthe
tuwlware options available for theRM 65 MiC/bcomputerModule
. UJl;Ilily.
.•
.
".
• Compact sizec:-a/;loul 4">< 6W(1 OQ mm x 160 ~m)
• Pin and:socket bus connection
10 On-board R6502 CPU
• 2K 01'2114 Static RAM .:
• Two sockets for up to 16K PROM/ROM
• . ~PPOrts the follO,Wlng PROM/ROM 0requivalents.
'"TI TMS 2516, TMS 2532 and Motorola. MCM 68764 PROMs
-Rockwell R2316, R2332, or R2364 ROMs
Interface
• R6522 Versatilelntenace Adapter (VIA) and
• FUlly Buffered Address, Daia,ar;dConfrol lines for RM65
Bus"
. " . ' . '.
'.
RM 65 Microcomputer Modules are designe,d for OEM and end
user microcomputer applications reql,liring state-of-the-art per~rmance, compact size,. mo,d.l,llar ,design af1d, low cost. Software
fpr RM .65 sys~ems can be devel9ped in R6500 Assembly LangUl!!ge, PLl65, BASIC and FORTH. Both BASIC ~nd FORTH are
available in ROM and can be incorporated into the user's $ystel;ll.
va
RM 65 Microcomputer Modules use a motherboard inte~nnect
concept and accept any.card in l1-0Y slot. Ttle 64-!ine BM 65 Bus
offers memory addressing up te> 128K.by!es, high immunity to
electrical noise and includes growth provisions for user functions,., A selection of card cagesprovide!l pack!lging flexibility.
RM 65 products may also be lIsed with Rockwell ,AIM 65 and
AIfy1a5l40'Microcomputers .fOl'praduqt ~velopmsnt and for a
broad variety of portable or desk-fop microcomputer applications.
• SeParate switches allow RAM.
PROMIROM, and. VIA to be
individually d~icated to one or two 65.K bYte mel1)!lFY banks
• Jumpers allow selection the following.
-2K, 4K or 8K PROM/ROMs
-'-RAM, PROM/ROM and 1/0 starting address to 4K byte
,
,
,
boundary
of
-On~board or EXternal bank addresslnQsource
PRODUCT OVERVIEW
-Programmable DMA Terminate
-On-board or external clock Source
The RM65;1000E S'ingle Board qonip~er (SBC) Module allows
userst!! design their products into compact modular stacks. The
SBCmodule plugs into a single slot in an RM 65 card cage/
motherboard, and controls other memory and
modules. The
heart of t1i9 SBC module is an R6502 CPU, which is capable"
of addressing 65k bytes of memory. In addition, the SBC module
contains bank address logic which allows addressing of"one or
two 65K byte memory banks. SoCkets on the module accept up
to 16K. bytes ofPROM/ROti/l. 2K bytes of static RAM are also
provided.
• .+5V operation
• Fully asse(Tlbled,.tested'and warranted
va
An R6522 Versatile Interface Adapter (VIA) provides two 8-bit
parallel VO data lines, two 2-bit eontrollines, two counter-timers
and an 8-bit shift register. On-board switches assign mel)1ory
sections to 4K byte blocks. All address, data and control Ihies
are buffered.
ORDERING INFORMATION
DeScription
Part'No;
RM65-1000E
Single Board Computer (SBC) Modul!!,
Description
Order No.
809
RM65-1000E Single Board Computer (SaC) Module
Single Board Computer (~BC) Module User's
Manual (included wtth RM65-1000E)
Document No. RMA65N10
Data
9-3
sheet Order No_
RM10
Rev. 2,May 1983
Single Board Computer (SBC) Module
RM65-1000E
FUNCTIONAL DESCRIPTION
or ROM is specified by the Base Address selection jumpers ahd
the PROM/ROM type jumpers.
.
The Clock Circuit uses a crystal-controlled oScillator to provide
a stable 1-MHz clock reference. A jumper se.lects between the
internal clock reference or an external clock (to 1 MHz) as the
source for the R6502 and the derived' system clock.
The 2K RAM section uses four 1K x 4 RAM devices to provide
on-board read/write memory.
The Reset Control circuit conditions the Reset signal to drive
the R6502 Reset line. A reset can be generated by either the
on-board reset pushbutton or an external switch. This circuitry
also generates a reset automatically, upon power-up.
The R6522 Versatile Interface Adapter (VIA) provides inputoutput capability to the SBC Module. The VIA provides two 8bit I/O porls each with two. control line.s. Both ports and control
lines are brought out to a connector for user applications.
The R6502 Central Processing Unit (CPU) is the heart of the
SSC Module and any interfacing Modules connected to the RM
65 Sus. The R6502 controls all program execution by means
of the address, data, control, and timing lines. All internal R6502
operations are synchronized to the cloC~ source.
The SBC Module can control up to 15 additional support modules by means of the RM 65 Bus. There are three groups of
signals on the RM 65 Bus: data, address, and control.
The Data Transceivers invert and transfer eight bits of parallel
data between the SBC Module and the RM 65 bus. The direction
of the transceiverS is controlled by the read/write signal from the
R6502. The transceivers are disabled when the on-board PROM/
ROM, RAM; or VIA is addressed or when the Bus Floalsignal
from the RM 65 Bus is active.
The Bank Select Control circuit detects when the SBC Module's
assigned memory bank is addressed, by comparing the Bank
Address signal to the Bank Select Enable and Bank Select
switches. The Bank Select Enable Sw~ches allow all on-board
PROM/ROM, RAM, ~ VIA'to be independently assigned'common
to boih Bank 0 (lower 65K) and Bank 1 (upper 65K) or dedicated
to either Sank 0 or. Bank 1, depending on the Bank Select
swttches. A jumper allows the Bank Address signal to be driven
by the on-board R6522 VIA or from another module.
The Address Buffers invert and transfer 16 parallel address bits
from the SBC Module to the RM 65 bus;
The Control Buffers buffer all control and clock signals between
the SBC Module and the RM 65 bus. The Non-Maskable Interrupt, Interrupt Request, Set OverflOW, External Clock (¢O), Ready
and Bus Float input lines are buffered coming from the RM 65
bus into the SBC Module. The DMA Terminate, Reset and
Phase 1 Clock (~1) output lines are always driven from the SBC
Module onto the RM 65 Bus. The other six output lines for Read/
Write, Phase 2 Clock, sync, and Bank Address are also buffered, but are tri-stated (disabled) when the Bus Float signal is
active.
The Base Address Decoder uses the six most-significant address
bits and the Base Address Jumpers to generate chip selects for
the on-board PROM/ROM, RAM, and VIA. The RAM. and VIA
can be independently mapped into any 4K block of the selected
65K bank. The PROM/ROMs may be mapped into any 4K or
8K block of the selected bank:
The 16K PROM/ROM section has two sockets which can accept
2K, 4K or 8K PROM/ROM devices. The size and type of PROM
RM 65 SBCModuie Block Diagram
9-4
:,.,'""
.'
RM65;.100G&i" ',',';
.,,:
.,',. " .
.8
Hti.
Sin9Ie~a~dComputer (S8crModul8
,. "":'."',11'\'
RM ,65 Bus Pin Assignments
Top (Component Side)
Bottom (Solder Side)
.. ;''','Slgn8/
'Mnem,onic
Pin
1a
2a, "
,,'GND
BADRI
GND
'BA13/
38 '"
4a
, Sa
iSA111
8a"
7a
Ila
, BA101
l BA8I
GND
BASI
9a
BA3/
lOa: '
lla'
BA2/
12a,
13a
SAOI
. GND
141
BSO "
BRo.y'
15a
16a
1,7a
+12V/+V'
GNo.
BDMTI
lBa
19a
20a
21a
22a
23a
,24a
25a
BRIWI
I
GND
BIRO!,
'" Bjil2f .
2Ba
892
27a
BD7/
GND
BDM
BD2f
2Ba
29a
30a
31a
BD11
32/!
+:5V
Sign!!1
Mnemonic
Pin
Signal Name
Ground
Buffered Bank Address
Ground
B~tfered~press'l;lit 13
Buffered Address Bit 1.1
Buffered Address Bit 10
B,uft8red AddreSs Bit B
GrOUnd
Eluffered Address Bit 5
Buf.fered Address Bit 3
Buffered Address Bit 2 '
Buffered AddreSs Bit a
Ground
,',
.Bl1f~ed ,~10verflow
Buffered Ready
.' USer Spare 1 '
'+12Vdc/+V
Ground line
Buffered DMA Terminate
. ,
'User Spare 3
BUffered Read/Wr~e "Not"
'System Spare
Ground
~uffered Interrupt Request
Buffered Phase 2 "Not" ClOck
Buffered PhaSe 2 Clock' '
Buffered DataBi! 7
.
Ground
Buffered 'Data Bit 4
Buffered Data Bit 2
Buffered Data Bit 1
+5Vdc
Ie
' +5V
BA1S!
BA14/
2c
3e
40
~~12f
5e
6e
7e
, Be
9c
10e
" 11c '
l2c
lab
14c
15c
·lSe,
17e
1Bc
19c
20e
21e
22e
i
23c
"
24c
25e
2Se
27e
2Bc
2ge
30e
31e
32e
GND
~A91
",BA7/
BASI
BA4/ '
GND
BA11
B~l, ,
BSYNC
BDR011
GND
,-12V/-V
BFLTI
B;<>
GND
BORQ2f
BRliN'
BAG1"1
I'INMII
GND
BRES!
BD6I
BD51
Bo.3/
GNo.
~DOI
GND,
Note:
:*Notused O(l this rnod~le .
.
"
r----j
r--=~4
6.~ IN.
ri
WLJIDTH
'.'
.' ",
.:
:~::RBOARD
I/AND-ftECEPTACLE
-1
"
1:
II
,I
--u
~ EUR~ONMECTOR
EXTENSION'·
RM 65SBC f\tQI:I~laOlmenslonal Outline ,
Signal ,Name
+5 Vdo
BUllE/red Address Bit 15
BuU$red Address Bit 14
Buffered Address Bit 12
Ground "
Buffered Address Bit 9
Buffeied Adc,iresS, eit 7
Buflered Address Sit 6 '
Buffered Address Bit 4
Ground
Buffered AR
R>
R
PICK
SP@
RP@
BOUNDS
.S
VARIABLE
CONSTANT
;CODE
FLOATING
POINT FUNCTIONS
,
,
:
USER
MEMORY
@
I
C@
C!
?
+1
CMOVE
FILL
ERASE
BLANKS
MEMORYM~P
TOGGLE
"
Address (Hex)
Begin colon definHion of .
End colon definHion.
Create a variable wlth inftial
value n; returns address when
executed.
Create a constant wHh value
n; ~turns value when executed.
Begin definftion of assemblY-lariguage
primitive operation .
Used to create a new defining word,
wHh execution-time "code. routine" for
. this dllta type in assembly: .
Used 10. create a new defining word,
wHh exeCution-time routine for this
data type in high8r-level FoRTH.
C"rElate a oser variable. .
'
The RM 65 Run.-TIme FORTH ROM contains both a single(16-bit) and double- (32:bit) precision integer arithmetic
capability. In AM 65 applications where floating point arithmeticis desired, thj!·AIM $5 Math Package ROM may be
used in {)onjunction with ttierun-time FORTH ROM. The
application program: can beaeveloped on an AIM 65 Mlcrororl'iput$rwith.'bO!h AIM 65 FORTH and AIM 65 Math Package
ROMs installed. A""ath paci
FORTH progralTisare develciped using "top-downJbottomup" techniques. That is, the programmer begins by defining
the program in very !J8neral·terms, then systematically breaks
these definitions' down into more' and more detailed sub~odules. When the' lowest levels of sub-modules have been
defined, he starts coding, in FORTH.. at those levels, working
back uP toward the tqp of the pro.gram, in pyramid fashion.
·Each sub-module is a stan.d-alone, component of the program, and can be completely debugged without having the
.
complete program in the system.
.
•
Description
Math Package Program
FORTH Program
UO Vectors
Terminal Input Buffer
Math Package Variables
FORTH User Variables
Math Package Variables
FORTH Variables
Fetch value address8d by t~p of Si~k.
Store'n1 at addrfjssn2.
Fetch one byte only.
.$ore one byte only.
P.iint contents of address.
Add .second number 'on stack to
contents of address on top.
Move n3 bytes starting at address nl to
area starting at address n2.
Put byte n3 into n2 bytes starilng at ,
address nl.
·FIII 02 bytes in memory wtth zeroes,
beginning at address nl.
Fill n2 bytes in Memory wfth blanks, .
beginning at address n1.
Mask memory wfth bit pattern.
NUMERIC REPRESENTATION
DECIMAL
HEX
BASE
DIGIT
o
1
2
3
9-11
Set decimal base.
Set hexadecimal base.
silt number base.
Convert ASCII to binary.
.The number zero.
.
The number one.
The number two.
The number three.
RM 65 Run-Time FORTH: ROM
RMSS;'0152
FORTH WORDS (CONT'D)
ARITHMETIC AND LOGICAL
+
0+
I
MOD
jMOD
-/MOD
./
U·
U/
M"
M!
MlMOD
MAX
MIN
+D+ ABS
DABS
NEGATE
DNEGATE
S- >D
1 +
2+
1 2AND
.OR
XOR
';' ,
CONTROL STRUCTURES
Add.
Add doub.le-precillion numbers.
$u!1\ract.(r:11 - n2)
Multiply. ~
Divide (nl/n2). .
Modulo (i.e., remainder from divi~ion).
Divide; giving rem"in~r and quotient.
Multiply, tben divide (nl-02/n3), with
double interme(jiate.
Uke -/MOD, 'but give quotient only.
Unsigned multiply leaving double
prod(Jcj.
, Unsigned divide.
Signed multiplication leaving double
product,
Signed remainder and quotient from
double'divipend.
Unsigred divide I~aving double quotient
. and remainder from double dividend
and single divisor.
Maximum.
Minimum.
. set sign.
Set sign 6f double-precision number.
AbsOlute value:
At)sOhlte val.ue of double-precision
number.
Change sign.
Change, sign of double-precision
number.
Sign extend to double-precision
number.
Increment value on top of stack by 1.
Increment value on top of stack. by 2.
Decrement value on top of stack by 1.
Decrement. value on top of stack by 2.
Logical AND (bitWise).
LOgical OR (bitwise)
Logical exclusive OR (bitwise).
I
LEAVE
BEGIN .. , UNTIL
BEGIN ... WHILE
•... REPEAT .
BEGIN .. , AGAIN
IF,., THEN
IF ... ELSE ... THEN
END
ENDIF
COMPILER-TEXT INTERf>RETER.
[COMPILE)
COMPILE
LITERAL
DLiTERAL
EXECUTE
[
I
CREATE
FORGET
HERE
COMPARI$ON OPERATOI\S
>
0<
0= .
U<
NOT
TASK
True n n1 less than n2.
True if n1 greater than n2.
True if top two numbers are equal.
True if top number negative.
True if .top number:zero.
. True if u1· less than u2.
Same as'O=,
- FIND.
DP
C,
PAD
IMMEDIATE
INTERPRET
MISCELLANEOUS AND SYSTEM .
«comment»
CFA
NFA
PFA
lFA
LIMIT
QUIT
Force co~pilationof IMMEDIATE wotd,
"Complillfollowing into
• diction.lll)'.
. .
. .
Compile a number iOto a literal •.
Compile a double-precision number into
.
a literal.
ExecUte the definition on top ot stack.
'Suspend'compilation, ente/execution.
Resume compilation.
DICTIONARY CONTROL
ALLOT
<
Set up lOop. giVen index range;
Li~ DO ... LOOP: but add~stack ~
value to index.
. .
Place' currentlndex ValUe on stack.
Terminate loopat next LOO'P or
+ LOOP,
Loop back to BEGIN until true at
UNTIL
Loop while true at WHILE, REPEAT
~ps unconditiQnally to BEGIN,
Uncondiiional loop.
If top of stack true, execute following
clause THEN continue; otherwise
continue at T H E N . .
If top ol'staektrue, execute ELSE
clause THEN continue;' otherwise
execute fciliowing clauae, THEN
continue.
.
.
Alias for UNTIL.
Alias for THEN.
DO .... LQOP
Do, .. +LOOP
, Begin comment (terminate by right
parentheses on same line).
Alter PFAto CFA.
Aller PFA to NFA.
A~erNFA to PFA.
Alter PFA to LFA.
Top of memol)'..
Clear return stack and return to
terminal. .
LATEST
LIT
CLIT
LITERAL
SMUDGE
STATE
9-12
Create a dictional)' header.
FORGET all definKions from
on.
Fieturns address of next unuSed b~e in
the dictionary.
Leave a gap
n b~es in the
, dictional)'.
A dictional)' marker.
Find tl:1e address of in the
dictional)'.
Search Cllctlonary for .
User variable containing the dictional)'
pointer.
Siora. byte into dictionarY.
ComPile a number into the dictional)'.
Painter to tempora\1 buffer. '
Force execution wi'Kin Compiling.
The Text Interpreter executes or
compiles.
leaVe name field address (N FA) of top
word In CURRENT.
Place l6-blt IIterara" the stack.
Place byte .1.lteral on the stack.
Compile a l6-bit literal.
Toggle name SMUOGE bit.
User variable containing compilation
state.
of
'RM65-0'152
RM 65 Run-Time FORTH ROM
FORTH WORDS (CONT'D)
USER VAFlIABLES (See Note 1)
U?TERMINAL
UABORT
UBiBUF
UBiSCR
Uc/L
UEMIT
UFIRST
UKEY
ULiMIT
User variable
Note 2.)
Uservariable
User variable
USer variable
User variable
User variable
User variable
User variable
User variable
OUTPUT FORMATTING (CONT'D)
for ?TERMINAL. (See
#
for ABORT.
for BlBUF.
for BlSCR.
for c/L.
for EMIT.
for FIRST.
for KEY.
for LIMIT.
#S
SIGN
#>
HOLD
HDL
- TRAILING
.LINE
COUNT
MONrrOR It CASSETTE I/O (See Note 1)
COLD
MON
CHAIN
CLOSE
?IN
?OUT
GET
PUT
READ
WRITE
SOURCE
FINIS
AIM 65 FORTH cold start.
(See Note 2.)
Exft to AIM 65 Monftor. (See Note 2.)
Chain tape file.
Close tape flle.
Set to active input device (AID).
Set to active output device (AOD).
Input a character from the AID.
output a character to the AOD.
Input n2 ctiaracters from AID to
ad,dress n1.
Output n2 characters to AOD at
address n1.
Compile from the AID.
Terminate complete from SOURCe.
.R
D.
D.R
DPL
VOCABULARIE&
CONTEXT
Returns address 01 pointer to
CONTEXT vocabulary.
CURRENT
Returns address of pointar to
CURRENT vocabulary.
FORTH
Main FORTH vocabulary.
ASSEMBLER
Assembler vocabulary.
DEFINITIONS
Set CURRENT vocabulary to
CONTEXT.
VOCABULARY Create new vocabulary.
VLIST
Print names of all words in CONTEXT
vocabulary .
VOC·L1NK
Most recently defined vocabulary.
INPUT-OUTPUT (See Note 1).
OCR
CR
SPACE
SPACES
CLRLINE
DUMP
TYPE
?TERMINAL
KEY
EMIT
EXPECT
WORD
IN
BAUD
BL
c/L
TIB
QUERY
10.
HANG
, OutP\l1 CR to printer only.
Carriage return.
Type one space.
Type n spaces.
. ', Output a CTRL B.
Print text string (terminated by ").
Dump n2words starting at address.
,Type string of nl characters starting at
address n2.
'
True if terminal break request present.
Read key, put ASCII value on stack.
Output ASCII value from stack.
Read nl characters lrom Input to
address n2.
Read one word from input stream,llntll
dellmfter.
User variable contalnadwithin TIB.
Set BAUD rate.
Output a SPACE character.
Number of charactsralline.
Polnter,lO terminal input buffer start
address.. , '
Input text from terminal.
Print from name # field
address (nfa).
Wait lor keystroke.
VIRTUAL STORAGE
LOAD
BLOCK
BlBUF
BlSCR
BLK
SCR
UPDATE
FLUSH
EMPTY·BUFFERS
+BUF
BUFFER
RW
USE
OUTPUT FORMATTING (See Note 1)
NUMBER
<'I
Convert next digit of double-precision
number and add character to output
string.
Convert all significant digits of doublepreciSion number to output string.
Insert sign of n into output string.
Terminate output string (ready for
TYPE).
Insert ASCII character into output
string.
Hold pointer, user variable.
Suppress trailing blanks.
Display line of text from mass storage .
Change length of byte string to type
form.
Print number on top of stack.
Print humber nl right justified n2
places.
Print double·preelsion numb8r n2 n2.
Print double· precision number n2 nl
right justified n3 places.
Number of digfts to the right of decimal
point.
PREV
Convert string at address 10 double·
precision number.
Start output string.
FIRST
OFFSET
NOTES: 1. Requires user·provided YO lunction.
2. Requires AIM 65 Monitor ROM be Installed.
..>
;S
9·13
Load mass storage screen (compile or
axaoute):
Read mass storage block to memory
address.
System constant giving mass storage
block size In bytes.
Number of blocks/editing screen.
Sy$iem variable containing currerit
block number.
Systell) variable containing cunrent
, screen number.
Mark last buffer accessed as updated.
Write ,~II updated buffers to mass
storage.
Erase all buffers.
Increment, f:)uffer addre~,.
Fetch liext memory buffer.
User (ead write linkage.
Variable containing address of next
buffer.
Vari,able containing address of latest
buffer.
Laaves address of first block buffer.
User variable block offsst to mass
storage.
Interpret next screen .
Stop Interpretation.
a
RM 65 Run-Time FORTH ROM
RM65,.0152
FORTH WORDS (CONT'O)
SECURITY
PRIMITIVES
OBRANCH
BRANCH'
ENCLOSE
RO
SO
RPI
SPI
NEXT
ICSP
Run-time conditional branch.
Run-time unconditional branch.
. Text sCanning primitive used by WORD.
Location of Return Stack.
Location of Parameter Stack.
Initialize RIllum Stack.
Initialize Parameter Stack.
Th8 FORTH virtual machine.
?COMP
?CSP
?ERROR
?EXEC
?PAIRS
?STACK
ABORT
ERROR
MESSAGE
WARNING
FENCE
WIDTH
Store stack position in check stack
poiriter.
Error if not compiling.
Check stack position.
Oulput error message.
Not execuling error.
Conditional not paired error.
Siack oul of bounds error.
Error; operation terminates.
.
Execule error notification and restart
system.
Displays message.
Pointer to message routine.
Prevents forgetting below this point.
Controls significant characters of
.
MATH PACKAGE: FORTH WORDS (A65-040)*
USER VARIABLE
FLOATING POINT ARITHMETIC
F+
Fp
FI
Adds two floating point numbers.
Subtracts one floating point number
from another floating point number.
Multiplies two floating point numbers.
Divides one floating point number by
another floating point number.
MIN-WIDTH
DEC-LENGTH
Specifies the minimum field width to be
oulpul.
Specifies the number of places to the
right of the decimal point to be
output. .
ASCII/FLOA'rING POINT .CONvERSIONS
UTILITY, SIGN AND COMPARISQNS
FABS
INT
SGN
FSIGN
FCOMP
FIN
Takes the absolule value of a floating
point number.
Truncates a floating point number to an
integer.
Converts the sign of a floating point
number to a floating point number.
Gets a value corresponding to the sign
of a floating point number.
.
Compares the value of a compacted
number in memory to a floating point
number.
FOUT
FORMAT CONVERSION AND DATA MOVING
M>F
F>M
M>A
POLYNOMIAL
POLY
POLYODD
Converts a number in memory from
ASCI! to floating point format.
Converts a number from floating point
to ASCI!.
S>A
Evaluates a polynomial' with
c.onsecutive exponents.
Evaluates a polynomial with odd
. eXPOnents.
S>F
F>S
:1
Unpacks the compacted number in
memory to floating point.
Packs theJloating point number to
compacted fOrmat and stores the
result in memory.
Unpacks the floating point number in
memory.
Converts an integer to floating poinl
format.
.
Converts an integer to floating point
format.
Converts a number from floating point
'to an integer.
. EXPONENTIAL AND LOGARITHMIC
$OR
>
EXP
LOG
LN
TRIGONOMETRIC AND UNITS CONVERSION
Takes the square root of a floating point
number.
Raises one Iloating point number to the
powllr of· another floating point
number.
Raises the transcendental number e to
the power of a floating point number.·
com pules the. logarithm to the base 10
(i.e .• common log) of a floating point
number.
Com pules the logarithm to the base e
(i.e., natural log) of a floating point
number.
SIN
COS
TAN
ARCTAN
DEGREES
RADIANS
'Requires AIM 65 FORTH or RM 65 Run-lime FORTH be resident.
9-14
Calc.ulates the sine of a floating point
number (in radians).
Calculates the cosine of a floating point
n\lmber (in radians).
Calculates the tangent of a floating
point number (in radians).
Calculates the arc tangent of a floating
point number.
Converts a floating point number from
radians to degrees.
Converts a floating point number from
degrees to ,radians.
RM65-290tE
RM65 MicrocompUter Family
'1'
Rockwell
RM65-2901E
RM 65 PROM PROGRAMMER MODULE
RM 65 MICROCOMPUTER MODULES
FEATURES
RM65 Microcomputer Module products are designed for OEM
and end usermicrocomputerapplications requiring state-of-the-·
art performance, .compact 'size; modUlar design· and low cOst.
Software for RM 65 systems can be developed in R6500
ASSembly Language, PLl65, BASIC, and FORTH. Both BASIC
and FORTH are available in ROM and can be incorporated into
the user's system.
• RM 65 bus compatible'
• Compact size RM 65 module-about 100 mm
(4 in. x 6'14 in.)
x 160 rnm
• Separate PROM socket module with
-28-pinZero h111ElrtionForce(ZIF) socket
-MolJnting holes forenclosuteor panel.installation
-Connecting 24-inch cable to RM 65 module
RM 65: Module prdducts use a motherboard interconnect ooncept in Which any card can be inserted in any s16t. The 64"line
RM 65 Bus offers memory addressirigtJp to 12SK bytes, provides high immunity to eleGtrical noise and includes growth provisions for user functions. A selection of card cages allows
packaging flexibility. RM 65 products may also be used with
Rockwell AIM 65 and AIM 65/40 Microcomputers for product
development and for a broad Variety of portable or desktop
microcomputer applications.
• Programs 1K-byte'to SK-byte UV EPROMs
; -1 K-byte: 2508, 2758
-2K-byte: 2516, 2716
-4K-byte:2532, 2732, 2732A
-SK-byte: 2564, 2764, 68764
.' Erases and programs 2K'byte EEROMs
-2K-byte: R5213f2S16, 5213,2816, 48016
• On-board SK-byte ROM contains programming functiOns
compatible with both
-AIM 65 Microcomputer Monitor
-AIM 65140 MicrocompUter VO and Monitor
PRODUCT OVERVIEW
TheRM 65· PROM Programmer module in conjunction with an
AIM 65 or AIM 65140 MiCrocomputer; programs industry standard 1K-, 2K-, 4K- and 8K~byteEPROMs (u~ra-violet light erasable prograriJmable read-only memories) and 2K-byte EEROMs
(electricatly erasable p(ogrammable read-only memories). The
module consists of apRM 65 modUle and a PROM socket
module connected together by a 24-inch ribooncable; A 2S-plh
Zero Insertion Force (ZIF) socket mounted on the PROM socket
module'allow$ installationofa 28-pin or 24·pin PROM. The
PROM socket module may be installed in various desk-top
endosure or front panel arrangements' for development, .enduser or OEM installation.
• Easy-to-use interactive commands
-:-PROM interface'(check, program, read, verify)
'"'-- RAM preparation (fill and invert) ' .
.
'-:':Ulility functions (command aM. PROM type menu, PROM
type selection, toggle verify mode, etc.)
• Verify during
after programming
• +5V only operatio,n (on-board·DCfDC corJVerter)
• Fully.assembled and tested with one year warranty
or
RM65-2901E PROM Programmer Module
Document No, RMA65N28
9-15
Data Sheet Order No. RM28
March 1983
RM6S-2901E
PROM programmer Module
An 8K-byte ROM containing the. PROMPrdgrammer comput~r
program instructions is installed onlh6 module. One-ha.l! 01 the
ROM contains programming functions" memory .mapped at
$7100-$7FFF, . which operate in conjunctionwith theA-1M 65
Monitor firmware. The other half olthe ROM is memerymapped
at $Dl OO-$DFFF and contains programmingfunctiori$'compiitible with the AIM 65/40 VO and Monitor ROMs. A jumper selects
which 4K-bytes (upper or lower), or if the entire 8K-bytes, of the
ROM secket are to be addressed.
ORDERING INFORMATION
Part No.
RM65·2901E
Description
PROM. Pro.@rammer Modul.e
Ord&r No,
820
Description
PROM Programmar Module lJser's Manual'
Note:
'Included with RM65-2901 E.
The R6522 VIA transfers 8-bit data between the RM65data
buS and the PROMdata lines and controls programming voltage
levels. During PROM programming, the VIA transfers data from
the Data Transceivers. for writing into the PROM and :during.a
PROM read, verify or check function, the VIA reads data from
the PROM. During PROM programming, the VIA issues control
signals to the Power Multiplexer, the Misplaced PROM Detector,
and the Vpp Rise/Fall Time Controller.
FUNCTIONAL DESCRIPTION
RM 65 Module
The Data Transceiversinvelt a.nd transfer 8·bitsefparallel data
between the PROM Programmer moqule and the RM 65 data
bus when enabled by the Chip SelectD'ecoder. The read/write
line from the RM 65 bus determines the direction of data flow.
During a write operatiol'1,data is transferred,from the bus to the.
module; during a read. operation, data is transferred from Ihe
module to the RM .65 bus.
The Programmable voltage Regulator,consisting of. the 8-bit
DAC, aVpp Rise/FaliTime Controller, a DC/PC Converter. and
an Analog Buffer, generates the VPp programming voltage. The
DAC'outPuts a voltage proportiohal toVpp for the selected
PROM type as oontro.lied by 8-bit data received from the RM 65
data bus. The DAC, output voltage is amplified to the fun Vpp
level; mixed with the rise or fall time. control signal,' clamped to
minimum,Vpp leve.l, and output totne Analog Buffer. The .+5
to +3~V DC/DC Converter provides the high v9ltage used in
the second stage of amplification. The Analog EMfer amplifies
the Vpp current for use by the Power Multiplexer.
The Gontrol Signal.Buffers inverland transferthephase2, read/
write., bank address and resel signi,lIs' from the RM 65 bus to
the' module, The bus active signal is. also driven to the RM 65
bus when data is being transferred between the RM 65 .bl:ls and
th.emodule.
.
Address Signal Buffers invert and transfer signals from 13
address lines from the RM 65 bus to the module ..
The Power Multiplexer selects the proper voltage level to output
to the PROM during a programming or read operation as controlled by signals from the VIA and Octal Latch A The output
voltage is selected from TTL high, TTL low, Vcc and the Vpp
output from the Analog Buffer. The correct voltage is selected
by VIA output control lines.
Thli1 Chip Select Decoder, in conjunction with Base Address
Select, Bank Select and Bank Select Enable switches and the
ROM Range Select jumper decodes the address from the .RM
65 I;lus and generates enable signals to other major on-.board
circuits. When the address matches the
Sase Address
switch positions, one of two OclalLatches, the on,boardR6522
Versatile Interface Adapter (VIA), the Digital·to-Analog Converter (DAC) and/or the Data Bus Transfers are enabled. When
the address matches the ROM Base Address switch positions
and ROM Range Selection jumper position, the on-board program ROM is enabled along with the Data Bus Transceivers.
va
The Mispla.ced PROM Detector determines if a 24:pin PROM
has been offset by o.ne or two pin positions when installed in
the 28-pin ZIF socket on the PROM module. The detecteQstate
is input to the VIA and sampled by the programming iirmware
to prevent application of programming voltage to a misplaced
PROM.
Bank ~Iect .andBank SefectEnable swit~hes assign the module
to one Of two 65K-bytemempry banks. The J;!ank Select Enable
switch assigns. the module)o.be active in col')1mqn memory
(botn Bank' 0 and 1) orin the bank se.lectedby t~eBank Select
switch'(either BankO or 1).
.
.
The two Octal Latches. A and B, transfer addresses from the
Address Buffers to the. PROM during PROM access operations.
The levels of three programming voltages output by the Power
Multiplexer to the PROM are also .controlled by Octall.,atch A.
PROM Socket Module and· Interface Cable
There are . eight Base AddreSS switc hes; fours""itches assign
the on-board ROM base address to a 4K'byte boundary and five
assign)he I/O. base .a.ddress to a page (256 bytes) within the
ROM base address.
A 28-pin
3~inch
Zero Insertion Force (ZIF). socket. is mounted. on a
x 3-inch PROM socket module and connected to the RM
65 module by a 24-inch ribbon cable. The socket ri1o~ul~has
mounting holes and may be installed in any orientation. The 28pin' ZIF socket allows installation of 24-pin PROMs as well as
28-pin PROMs.
The ROM Range Select jUmper indic~tes that no.ROM, a4Kbyte ROM .or an 8K-byte ROM, is installed on;board.
9-16
I
PROM .ProgrammetM()dule
PROM PROGRAM COMMANDS
PROM PROGRAMMER FUNCTIONS
Furictlon
C!lnlmand
Computer program routines to operatlHhe PROM Programmer
.module are provided in an SK-byte ROM installed on the'RM 65
,module. One of the twover~ions 01 the resid",nl firmware is
. jumper selectable upon installation to operate with either the
AIM 65 or the AIM 65/40 VO and Monitor finnware. Easy-to-use
. interactive commands perform PROM interface functions (check,
program, read and verify), RAM preparation functions (fill and
invert) and utility functions (e.g., command and PROM type
menus, toggle verification mode, and change PROM type).
Many Monitor commands are directly linked to the PROM Programmer command level for ease of operation.
Checlf
BANK
ADDRESS
BANK
SELECT
CONTROL
10
ADDRESS
8K Static RAM Module Block Diagram
9-22
RAM
SECTIONS
8K Static RAM Module
RM65-.3108E
RM 65 Bus Pin Assignments
Bottom (Solder Side)
Pin
la
2a
3a
4a
5a
6a
7a
8a
9a
lOa
1.1 a
12a
13a
14a
15a
16a
17a
lBa
19a
20a
21a
22a
23a
24a
25a
26a
27a
28a
29a
30a
31a
32a
Signal
Mnemonic
GND
BADRI
GND
BAl3/
BAll/
BA10/
BA8I
GND
BA5J
BA3!
.BA2I
BAO!
GND
BSO
BRDY
+12V/+V
GND
BDMT/
BRiWi
GND
BIROI
B~21
1¥2
BD7/
GND
BD4I
BD2I
BDI/
+5V
Top (Component Side)
Input!
Output
Signal Name
Ground
Buffered Bank Address
Ground
Buffered Address Bit 13
Buffered Address Bit 11
Buffered Address Bit 10
Buffered Address Bit B
Ground
Buffered Address Bit 5
Buffered Address Bit 3
Buffered Address Bit 2
Buffered Address Bit 0
Ground
'Buifered Set Overflow
'Buffered Ready
'User-Spare 1
'+12 VdC/+V
Ground Une
'Buffered DMA Terminate
• User Spare 3
Buffered Read/Write "Not"
'System Spare
Ground
'Buffered Interrupt Request
Buffered Phase 2 "Not" Clock
"Buffered Phase 2 Clock
Buffered Data Bit 7
Ground
Buffered Data Bit 4
Buffered Data Bit 2
Buffered Data Bit 1
+5 Vdc
Signal
Mnemonic
Pin
le
2e
3c
40
5e
6c
7e
Be
9c
I
I
I
I
I
I
I
I
I
+5V
BAl5J
BAl41
BAl21
GND
BA9/
BA7/
BA6I
BA4I
GND
BAI/
B;l
BSYNC
BDRal/
GND
-12V/-V
lOe'
I
I
VO
VO
VO
VO
lIe
12e
13c
140
15c
16c
17e
lBe
1ge
20c
21c
22e
23c
240
25c
26c
27c
2Be
2ge
30e
31e
32e
BFLT/
B;O
GND
BDRQ2I
BRlW
BACT/
BNMV
GND
BRES!
BD6I
BD5J
BD3I
GND
BOO/
GND
Signal Name
+5 Vde
Buffered Address Bit 15
Buffered Address 'Bit 14
Buffered Address Bit 12
Ground
Buffered Address Bit 9
Buffered Address Bit 7
Buffered Address Bli 6·
Buffered Address Bit 4
Ground
Buffered Address Bit 1
• Buffered Phase 1 Clock
'Buffered Sync
'Buffered DMA Request 1
Ground
'-12 Vdc/-V
• User Spare 2
'Buffered Bus Float
• Buffered External Phase 0 Clock
'Ground
• Buffered DMA Request 2
Buffered Read/Write
Buffered Bus Active
'Buffered Non-Meskable Interrupt
Ground
"Buffered Reset
Buffered Data Bit 6
Buffered Data Bit 5
Buffered Data Bit 3
Ground
Bu!f8red Data Bit 0
Ground
Note:
'Not used on this module.
r--r;~~~M)
r
---j
r-------------LENGTH~
;>
:~~~~~BOARD
I/ANDRECEPTACLE
EUROCARD CONNECTOR
--f,
"
::
WLIDTH
iI:l
COMPONENT AREA
Lr--_\.-
HEIGHT
a
t
,I
li
~
______________________
II
~T",--~
~ ~EURDCONNECTOR
EXTENSION
Module Dimensions
9-23
Input!
Output
I
I
I
I
I
I
I
I
I
0
VO
VO
VO
VO
RMS5-310SE
SK Static RAM Module
SPECIFICATIONS
Parameter
Value
Dimensions (See Notes)
Width
Length
Height
3.9 in. (100 mm)
6.3in. (160 mm)
0.56 in. (14 mm)
Weight
5.3 oz. (145 g)
Environment
Operating Temperature
Storage Temperature
Relative. Humidity
O'C to 70'C
-40'C to +85'C
0% to 85% (Without condensation)
Power Requirements
+5 Vdc ±5% @ 1.0A (S.OW)-Typical
1.9A (9.5W)-Maximum
Access Time
450ns-Maximum
RM 65 Bus Interface
64-pin plug (0.100 in. centers) per DIN 41612 (Row b not installed)
Notes:
1. Height includes the maximum values for component height above the board surface (0.4 in. for populated modules), printed circuit board
thickness (0.062 in.), and pin extension through the bottom of the module (0.1 in.).
2. Length does not include the added extension due to the module ejector.
3. DimensionS conform to DIN 41612.
9-24
RM6$-3132E
RM 65 Microcomputer Family
'1'
Rockwell
RM65-3132E
RM 65 32K DYNAMIC RAM MODULE
RM 65 MICROCOMPUTER MODULES
FEATURES
The RM65-3132E 32K Dynamic RAM Module is one of the hardware options available for the RM 65 Microcomputer. Module
Family.
• Compact size-about 4" x.6Va" (100 mm x 160 mm)
• Pin and socket bus connection
• RM 65 bus compatible
• Buffered data,' address, and control lines
• internal Refresh controller is completely transparent to the
RM 65 bus
RM 65 Microcomputer Module products are designed for OEM
and end user microcomputer applications requiring state-of-theart performance, compact size, modular design and low cost.
Software for RM 65 systems can be developed in R6500
Assembly Language, PU65, BASIC and FORTH. Both BASIC
and FORTH are available in ROM and can be incorporated into
the user's system.
• On-board sw~ch allows write protection
• Base Address Header allows each 4K memory section to be
assigned to any 4K block as a selected bank
• Bank select switches allow the entire board to be mapped
into either or both 65K banks
RM 65 module products use a motherboard interconnect concept and accept any card in any slot. The 64~line liM 65 Bus
offers memory addressing up to 128K bytes, high immunity to
electrical noise and includes growth provisions for user functions. A selection of card cages provides packaging flexibility.
RM 65 products may also be used with ROCkwell AIM 65 and
AIM 65/40 Microcomputer's for product developmeni and for a
broad variety of portable or desktop microGomputer applications.
• On-board DC-DC converter for -5 volt power supply
• Requires +5 and +12 volt power from the RM 65 bus
• Fully assembled, tested, and warranted.
ORDERING INFORMATION
Part No.
RM65-3132E
RM65-3132NE
,:
PRODUCT OVERVIEW
The 32K Dynamic RAM module provides 32K bytes of read/
write memory using 16 16K bit x 1 dynamic RAM (DRAM)
devices. Two bank select switches allow .the board to be dedicated to either one of two 65K Banks, or to be asSigned cO(Tlmon
to both banks. A 24-pin DIP header allows each of the eight 4K
sections to be independently mapped into any 4K block of the
selected 65K bank. The independent addressing of bl.ocks provide flexibil~y with system memory maps. An on-board switch
allows the entire board to be write-protected.
Order No.
808
Description
32K Dynamic RAM Module
32K Dynamic RAM Module (without RAM
devices installed)
Description
32K Dynamic RAM Module User's Manual
(included with RM65-3132E and
RM65-3132NE)
All refreshing of the dynamic RAM Chips is automatic and completely transparent to the RM 65 Bus, thus providing low pOwer
performance at no loss of bus speed.
RM6S-3132E 32K Dynamic RAM Module
Document No. RMA65N11
9-25
Data Sheet Order No. RM11
, Rev. 2, June 1983
RM65-3132E
32K Dynamic RAM Module
FUNCTIONAL DESCRIPTION
The Data Transceivers invert and transfer 8.bit parallel data
between the selected DRAMs to the RM 65 bus. During a read
operation, data from the DRAMs are latched and driven by the
transceivers onto the RM 155 bus. During a write operation, data
from the RM 65 bus drives the DRAMs. The transceivers are
disabled when the module is not addressed.
abled. The Base Address Encoder produces a 3 bit code for. ihe
enabled line and an additional signalf(jt'any line active (Board
select) . .The 3 bit code from the enc6cte'r becomes the:3 MSB
address bits for the Memory Address Multiplexer. The Board
Select line and a valid Bank Select signal are used to enable
the Memory Controller and Data Transceivers, as well.as create
a Data Bus Active Signal.
.
The Address Buffers invert and transfer 16·bit parallel address
lines from the RM 65 bus into the DRAM Module.
The Write Control logic uses the Write Protect switch and the
Read/Write Hneto e'nable writing into. the DRAMs .. If the Write
Protect SWitch is off, the Read/Write signal is transferred directly
to the Memory Controller. If the Write Protect switch is on, the
Memory Controller forces a read operation so that the contents'
of ihe DRAMs will not be altered.
The Bank Select Control circuit detects when the DRAM module's
assigned memory bank is addressed by comparing the bank
address signal from the RM 65 bus to the Bank SeleCt and Bank
Select Enable sw~ches. The Bank Select Enable switch allows
the board to reside in common memory (both Bank 0 and Bank
1) or only in the Bank set by the Bank Select swijch (either Bank
or Bank 1).
The Timing Control generates all the clocks required by the
Memory. Controller, . Memory Address Multiplexer, and the
Refresh Clock. The Refresh Clock generates a refresh cycle for
every seven RM 65 clock cycles.
o
The Control Buffers buffer the control and timing signals used
.
from the RM 65 bus,
l'he Memory Controller uses the clocks derived in the timing
control to sequence the signals to the DRAM devices. During
normal read or write cycles, the Memory Controller allows Row
Address, then Column Address' information to be applied to the
addressed DRAMs and generates the read/write signal. When
a refresh is required, 'the timing is controlled so that the refresh
is transparent to the RM 65 bus.
The DRAMdevic:es require 3 voltages. Two of these (+5 and
+ 12 volts) are available di~ectly froin the RM 65 bus,l'he third
voltage ( -5 volts) is generated on board with a DC/DC converter.
The Address Decoder uses the. four MSB address lines to
decode and enable one of .16 lines, each of which correspond
to 4K blocks. The Base Addre~s Selection Jumpers are placed
in a 28 pin socket which consists of16 lines from the Address
Decoder, four lines· from +5 volts, and 8 lines to the. Base
Address Encoder. The Base Address Selection is made by con·
necting each of the eight encoder inputs to anyone of the 16
decoder outputs or to +5 volts. This allows each 4K block to be
addressed anywhere in the selected.65K memory bank qr dis·
The Memory Address Multiplexer and Refresh Counter multi·
plexes Row, Columh, or Refresh Addresses onto the DRAM
address lines in response to the Memory Controller. There is
also a Refresh Counter which is incremented by the Refresh
Clock.
AM 65
BUS CONNECTOR
,
8
DATA
BUS ACTIVE
ADDRESS
DYNAMIC
RAM
DEVICES
(16)
CONTROL
AND TIMING
BANK ADDRESS
POWER
32K Dynamic RAM MOdule Block Diagram
9·26
RM65-3132E
32K Dynamic RAM Module
RM
65 Bus Pin Assignments
Bottom (Solder Side)
Signal
Mnemonic
Pin
la
2a
3a
4a
5a
Sa
7a
8a
9a
lOa
lla
12a
13a
14a
15a
lSa
17a
18a
19a
20a
21a
22a
23a
24a
25a
2Sa
27a
28a
29a
30a
31a
32a
GND
BADRI
GND
BA13!
BAll!
BA10!
BAS!
GND
BA5!
BA3!
BA2/
BAO!
GND
BSO
BRDY
+12V!+V
GND
BDMT!
BRlWi
GND
BIRO!
B~21
9112
BD7!
G!,;D
BD4I
BD2/
BD1!
+5V
Top (Component Side)
Signal Name
Signal
Mnemonic
Pin
Ground
Buffered Bank Address
Ground
Buffered Address Bit 13
Buffered Address Bit 11
Buffered Address Bit 10
Buffered Address Bit B
Ground
Buffered Address Bit 5
Buffered Address Bit 3
Buffered Address Bit 2
Buffered Address Bit 0
Ground
'Buffered Set Overflow
'Buffered Ready
'User Spare 1
+12 Vdc/+V
Ground Une
'Buffered DMA Terminate
'User Spare 3
Buffered Read!Write "Not"
'System Spare
Ground
'Buffered Interrupt Request
Buffered Phase 2 "Not" Clock
'Buffered Phase 2 Clock
Buffered Data Bit 7
Ground
Buffered Data Bit 4
Buffered Data Bit 2
Buffered Data Bit 1
+5 Vdc
lc
2c
3c
4c
5c
Sc
7c
Bc
9c
10c
llc
12c
13c
14c
15c
16c
Hc
18c
19c
20c
21c
22c
23c
24c
25c
26C
27c
28c
29c
30C
31c
32c
+5V
BA151
BA14!
BA121
GND
BA9!
BA7!
BAS!
BA4I
GND
BAli
B~l
BSYNC
BDRQ1!
GND
-12V!-V
BFLT!
B¢O
GND
BDRQ2I
BRlW
BACT!
BNMV
GND
BRES!
BD6!
BD5!
BD3/
GND
BDO!
GND
Signal Name
+5 Vdc
Buffered Address Bit 15
Buffered Address Bit 14
Buffered Address Bit 12
Ground
Buffered Address Bit 9
Buffered Address Bit 7
Buffered Address Bit S
Buffered Address Bit 4
Ground
Buffered Address Bit 1
'Buffered Phase 1 Clock
'Buffered Sync
'Buffered DMA Request 1
Ground
'-12 Vdc/-V
'User Spare 2
'Buffered Bus Float
'Buffered External Phase 0 Clock
Ground
'Buffered DMA Request 2
Buffered Read/Write
Buffered Bus Active
'Buffered Non-Maskable Interrupt
Ground
'Buffered Reset
Buffered Data Bit 6
Buffered Data Bit 5
Buffered Data Bit 3
Ground
Buffered Data Bit 0
Ground
Note:
'Not used on this module.
r--~;~~':nM)
r
----j
t--LENGTHi
t~
~~~NE~BOARD
llANoRECEPTACLE
EUROCARD CONNECTOR
--:.
COMPONENT AREA
"'I
L~ ___~_
'I
!l
WLIDTH
HEIGHT
II
L-________________________
II
~~;I--~
~ ~EUROCONNECTOR
EXTENSION
Module Dimensions
9-27
+
,
RM6~·3132E
32K Dynamic RAM Module
SPECI.FICATIONS
Dimen!Sions (1,2,3)
Wid1h'
Length
Height
3.9 in. (100 mm)
6.3 in. (160 mm)
0.?6 in. (1.4 mm)
Weight
4.5 oz. (140 g)
Environment
Operating Temperature'"
Storage Temperature
.Relative Humidity
O'Cto 70'C
-40°C to +85°C
0% to 85% (wHhOut condensation)
Power ReqUirements
+5 Vdc ±5'10 1:4 A.(7.0W)-Maximum
+12 Vdc±5% 1070 mA (2.1W)-Maximum
RM 65 Bus Interface
64-pin plug (0.100 in.' centers) per DIN 41612 (Row b not installed)
' .. '.'
Notes:
1. Height includes the maximum values 'for component height above the board surface (0.4 in. for populated modules), printed circuit board
thickness (0.062 in.), and pin eXtension Ihrough the bottom of Ina module (0. I in.).
.
2. Length does not include exienslons beyond the edge of the module due to connectors or the module ejector.
3. Dimensions confonl) toDl(!Ij 41612. '.
."
.
9-28
AM65-3216E
RM 65 Microcomputer Family
'1'
Rockwell
RM65-3216E
RM 65 16K PROM/ROM MODULE
RM 65 MICROCOMPUTER MODUL,ES
FEATURES
The RM65-3216E 16K PROM/ROM MOdule is one of the hardware options available for the RM 65 Microcomputer MOdule
family.
• Compact size-about 4" x 6%" (100 mm x 160mm)
•
•
•
•
RM 65 Microcomputer Module products are designed for OEM
and end user microcomputer applications requiring state-of-theart performance, compact size, modular design and low cost.
Software for RM 65 systems can be developed in R6500
Assembly Language, PLJ65, BASIC and FORTH. Both BASIC
and FORTH are available in ROM and can be incorporated into
the user's system.
Pin and socket bus connection
RM 65 Bus compatible
Buffered address, data and control lines
Supports the following PRQMs/ROMs pr equivalents:
Intel 2716 or 2732 PROMs
TI TMS 2516 or 2532 PROMs
Rockwell R2316, R2332 or R2364 ROMs
• Low-power PROM operation selectable by individual socket
jumpers
• Jumpers allow selection of 2K, 4K or 8K byte devices
• Starting address selectable for each of four 4K memory
blocks
• Separate switch allows 8K to be dedicated to one or two
memory bank operation
RM 65 module products use a motherboard interconnect concept and accept any card in any slot. The 64-line RM 65 Bus
offers memory addressing up to 128K bytes, high immunity to
electrical noise and includes growth provisions for user functions. A selection of card cages provides packaging flexibility.
RM'65 products may also be used with Rockwell AIM 65 and
AIM 65/40 Microcomputers for product development and for a
broad variety of portable or desktop microcomputer applications.
• +5V operation
• Fully assembled, tested and warranted
PRODUCT OVERVIEW
The RM 65 16K PROM/ROM MOdule has eight, 24-pin sockets
to accept up to 16K bytes of either programmable read-only
memory (PROM) or masked read-only mer.nory (ROM) devices.
On-board jumpers permit selection of 2K, 4K or 8K byte PROM!
ROM devices. Switches allow setting of the starting address for
independent 4K byte blocks of memory. All 16K bytes can be
assigned to two memory banks, or 8K ,can be assigned to
common memory while the other 8K can be dedicated to one
or two 65K memory banks. Low power operation is jumper
selectable for PROMs that have this option.
ORD~RING
part No.
RM65-3216c"
Ordar No.
806
INFORMATION
Oeacrlptlon
16K PROM/ROM Module
Oeacrlptlon
16K PROM/ROM Module User's Manual
(Included with RM65-3216E)"
RM65-3216E 16K PROM/ROM Module
Document No. RMA65N02
9-29
Data Sheet Order No. RM02
Rev. 2, June 1983
RM65-3216E
16K PROM/ROM Module
FUNCTIONAL DESCRIPTION
The PROM/ROM module has eight 24-pin sockets which Cali
accept up to 16K of either 2K, 4K, or 8K PROM or ROM.
Four Base Address Decoders allow. 4K PROM/ROM sections
to be independently addressed oflahy 4K boundarywittiir1the
sele~te(t bank. When an address fallswithihany section (per
the Base Address switches), an enable:signal'is sent to the Chip
Select DeCOder.
.
'
The Data Buffers invert and transfer 8-bits of para lIel data from
the selected PROM/ROM devices to the RM 65 Bus during read
operations...
The Chip Select Decoder uses outpLits from the Bank Select
Control circuit, ,the Base Address Decoders, and the PROM/
ROM size jumpers as well as'the address lines to generate chip
selects to the· PROM/ROM· devices. The PROM/ROM type
jumpers route the chip select lines to the correct pins on the
PROM/ROM sockets.
The Control Buffers invert and transfer phase 2 clo<;k, and read!
write control signals from the RM 65 Bus onto the PROM/ROM
module,. and drive.tne bus active signal onto the.AM 65 Bus.
The Bank Select control circuit detects when the PROM/HOM
module's assigned memory bank is addressed, by comparing
the bank address signal from the RM 65 Bus to the Bank Select
and Bank Select .Enable switChes. The Bank Select Enable
switch allows 8K of the F:'ROM/ROM to be common memory
(addressable in both Bank 0 and Sank 1) while the remaining
8K is assigned either to Bank 0 or Bank 1, as determined by the
Bank Select switch,
The Data Buffer Control circuit enables the Data Buffers during
a read operation when an address corresponding to a selected
base address is decoded and the selected PROM/ROM memory
bank is addressed.
RM66
BUS CONNECTOR
r--
8
/8
DATA
CLOCK AND
CONTROL
DATA
SUFFERS
2
CCNTROl
BUFFERS
BUS
ACTIVE
BANK
ADDRESS
BANK
SELECT
CONTROL
I
;J
r
DATA
BUFFER
CONTROL
-"
/6
. fj4
I+:"-
BANK
SELECT
SWITCH
j4-
BANK
SELECT
ENA8LE
SWITCH
8
8AS.E
; ADDRESS
SWITCHES
LI6
ADDRESS
f
ADDRESS
BUFFERS
2
,,('
PROM/ROM
SIZ.E ,
[JUMPERS
'--
.,
,;
L16
I
t--
I
16K PROM/ROM Module Block Diagram
CHIP
SELECT
DECODER
PROM/ROM
TYPE
JUMPERS
16
SOCKETS
FOR 16K OF
PROM/ROM
BASE
ADDRESS
DECODERS
.L11
/
RM65-3216E
16K PROM/ROM Module
RM 65 Bus Pin Assignments
Bottom (Solder Side)
Signal
Mnemonic
GND
BADR/
GND
BAI31
BAlli
BAlOl
BA6/
GND
BASI
BA3I
BA2I
BAOI
GND
BSO
BRDY
+12V/+V
GND
BDMTI
BR/WI
GND
BIRQ/
BJ12/
B~2
BD71
GND
BD41
BD2/
BOIl
Signal Name
Ground
Buffered Bank Address
Ground
Buffered Address Bit 13
Buffered Address Bit 11
Buffered Address Btt 10
Buffered Address Bit 8
Ground
Buffered Address Bft 5
Buffered Address Bit 3
Buffered Address Bit 2
Buffered Address Bit 0
Ground
"Buffered Set Overflow
"Buffered Ready
"User Spare 1
"+12 VdC/+V
Ground Line
"Buffered DMA Terminate
"User Spare 3
"Buffered Read/Write "Not"
"System Spare
Ground
"Buffered Interrupt Request
"Buffered Phase 2 "Nor· Clock
"Buffered Phase 2 Clock
Buffered Data Bit 7
Ground
Buffered Data Bit 4
Buffered Data Bit 2
Buffered Data Bit 1
Not Connected (See Note)
Top (Component Side)
Input!
Output
I
I
I
I
I
I
I
I
I
I
0
0
0
0
Pin
. Pin
la
2a
3a
4a
Sa
6a
7a
8a
9a
IDa
l1a
12a
13a
14a
15a
16a
17a
18a
19a
20a
21a
22a
23a
24a
25a
26a
27a
28a
29a
30a
31a
Za
10
20
3c
40
50
60
7c
8c
9c
100
110
12c
13c
140
150
16c
17c
180
190
20c
210
220
23c
240
250
26c
270
28c
29c
30c
31c
Zc
Signal
Mnllmonlc
+5V
BAI5!
BA141
BAI2/
GND
BA91
BA71
BA61
BA4I
GND
BAIl
B~I
BSYNC
BDROll
GND
-12V/-V
BFLTI
BIlo
GND
BDR02/
BR/W.
BACTI
BNMV
GND
BRES!
BD6I
BD51
BD3I
GND
BDOI
Signal Name
+5 Vdo
Buffered Address .Bit 15
Buffered Address Bit 14
Buffered Address Bit 12
Ground
Buffered Address Bit 9
Buffered Address Bit 7
Buffered Address Bit 6
Buffered Address Bit 4
Ground
Buffered Address Bit 1
".Buffered Phase 1 Clock
"Buffered Syno
"Buffered DMA Request 1
Ground
"-12 VdC/-V
"User Spare 2
"Buffered Bus Float
"Buffered External Phase 0 Clock
Ground
"Buffered DMA Request 2
Buffered Read/Wrne
Buffered Bus Active
"Buffered Non-Maskable Interrupt
Ground
"Buffered Reset
Buffered Data Bit 6
Buffered Data Bit 5
Buffered Data Bit 3
Ground
Buffered Data Bit 0
Not Connected (See Note)
Input!
Output
I
I
I
I
I
I
I
I
I
0
0
0
0
0
Note:
"Not used on the 16K PROM/ROM module.
SPECIFICATIONS
Parameter
Value
Dimensions (1, 2, 3)
Width
Length
Height
3.9 in. (100 mm)
6.3 in. (160 mm)
0.56 in. (14 mm)
Weight
5.0 oz. (140 g)
Environment
Operating Temperature
Storage Temperature
Relative Humidity
O°C to 70°C
- 40°C to + 85°C
0% to 85% (wfthout condensation)
Power Requirements
wlo PROM/ROM Devices
+5 Vdc ±S% 0.17A (0.85W)-Typioal
0.27A (1.35W)-Maximum
AocessTime
450 nanoseconds (max)
RM 65 Bus Interface
Edge Connector Version
Eurocard Version
72-pin edge connector (0.1 00 in. centers)
64-pin plug (0.100 in. centers) per DIN 41612 (Row b not installed)
,
Notes:
1. Height includes the maximum values for component height above the board surface (0.4 in. for populated modules), printed circuit board
thickness (0.062 in.), and pin extension through the bollomof the module (0.1 in.).
2. Length does not include the added extension due to the module ejector.
3. Dimensions conform to DIN 41612.
9-31
RM6So3216E
16K PROM/ROM Module
r
.
.
'.'
.'
'.
=11'". .
b= .
6:SIN.
0
'.
.
.
(.1.7. 2.M.M
......'......
." .' ..
..
.
..
MATING'
'.
.
'.
AND RECEPTACLE
.......... MOT. HERBOAR.O.
LENGT~·4./
•
.
.
EUROCARD CONNECTOR
--{1
.'
"
.:,;'
II
.
"
"
Lr-_~_~_
.-
HEIGHT
WLIDTH;:
,I
II
.
COMPONENT AREA
-~,
--1·I--EUROCONNECTOR
EXTENSION
Module Dimensions
9·32
'
AM65-3264NE
RM 65 Microcomputer Family'
RM65-3264NE
UNIVERSAL MEMORY MODULE
RM 65 MICROCOMPUTER MODULES
FEATURES
The RM65-3264NE Universal Memory Module (16K':'128K) is
one of the hardware options available for the RM 65 Microcom,
puter Module Family. '
• In the high speed mode, supports Rockwell Design Center
4 MHz RAM operations
'AM 65 Microcomputer Modules are designed for OEM and end
user microcomputer applications when state-of-the-art performance, compact size, modular design, and low cost are required.
Software for RM 65 systems can be developed in R6500
Assembly Language, PU65, BASIC, and FORTH. Both BASIC
and FORTH are available in ROM and can be incorporated into
'
the user's system.
• On-board header and shunt configure the module into a 2K
to 128K memory space
• Each half (four device sockets) independently configurable in
the universal memory mode
• In the universal memory mode, supports 2K. 4K, 8K, and 16K
byte-wide memory devices
• On-board memory bank select switches assign each half of
the module to either one or both of two 64K memory banks
• On-board ROM select switclies serve as wrne-protect swnches
for each half of the memory in universal memory mode
RM 65 Modules plug into a motherboard designed to accept any
card in any slot. The 54-UneRM 65 Bus accommodates memory
addressing up to 12&1< Pytes, provides high immunity to electrical noise, and include!! growth proviSions for user functions.
A selection of card cages permit packaging flexibility. RM 65
products may also be used wnh Rockwell AIM 65 or AIM 65140
Microcomputers for product development and for portable or
'
desktop microcomputer applications.
• 'Rockwell RM 65 Bus compaiible
• Compact size-l00 mm x 167 mm (approximately
'
~3~J
, '
4 in.
,
x
• Operates from a single +5V power source
• Fully assembled (except for user-supplied memory devices),
tested and warranted
• Supports 16K of2K devices, 32K of 4K devices, 64K of 8K
devices, and 128K of 16K devices in universal memory mode
:. Supports 64K()f SK devices in high speed mode (refer to
Devices Supported ,for part numbers)
OVERVIEW
Two major capabilities are provided in the, Universal Memory
Module: the flexibility of using 2K, 41<, 8K,or 16K memory
devices ,on the module, and use of the memory in eilher~ hig~
speed mode or a universal memocymode. Typical,data.transfer
rates are up to 4 MHz (to support the Rockwell Design Center
(ROC) System) ,in the high speed mode'and 1- to 2~MHz in the
universal memory mode. Rates, are dependent both on memo!y
devices used and systlilm configurat, ion. Memory devices that
can be'used with thl:! module are RA~'s,'ROM's, EPRQM's, and
Ei::PROM's.
ORDERING INFORMATION
Pllrt
No.
RM65-3264NE
RM!i5-3264NE Universal Memory Module'
Document No. AMA65N32
"'Universal MemOry Module
Data Sheet Order No.8M32
August 1983
9-33
9
,','
RM65~3264NE
Universal Memory Module
FUNCTIONAL DESCRIPTION
Device Select A consists of jumpers. E~, E4, and E7 through
El0 determine the particular type.mem6ry device (2K, 4K, BK,
or 16K) installed in the Memory A sogkets. Similarly, DeviCe
Select B jumpers E5, E6, and E11 'tfiroughE14 determine
memory device types in Memory S:
Data Bus Transceivers buffer and invert data· signals ·BDOI
through BD71. Data signals from the RM 65 Bus pass through
the bidirectional transceivers into the module dWing ;l. write
operation and out from the module through the transceivers to
the RM 65 Bus during a read operation. Data in is inverted for
use in the module, and data out (from the module) is inverted
for use on the RM 65 Bus. Transfers occur when any of the chipselect signals and the 02 clock pulse are in the active states
concurrently. Direction of data flow either into or out of the
.
module is controlled by the Rfiiij signal state.
Memory A Decoder is a programmable array logic (PAL) device
internally configured to decode a combination of input signals
and generate one output (chip-select) signal. Memory Decoders.
A.and B are:.u5ed onlywhEIO the module is'being operated in
.the universal memory mode. Both decoders operate in the
same manner, but only one is used at a time: Thus,when
Memory Ais addressed, Memory Decoder A is used, and
Memory Decoder B when Memory Bis addressed.
Address and Control Buffer. logic consists of inverters that buffer
address signals BAOI through BA13/ and the read/write signal
BRIW/. These signals are converted to posjtive signals BAO
through BA13 and BRlW for use within the module.
Bank Address· Select logic is controlled by the state of the
BADRI signal, which functions as a seventeenth address bit. The
state of the SADRI sign;l.1 indicates Which. of the two 65K memory
banks is addressed. In the high .speed memory mode, the
module cM be configured to operate in either one ,Qr both 65K
memory banks. In the universaJ mElIliory mode, each half of the
hoth. 65K memory
memory is configurable to either one
.
. . . , .. ,
.'
banks.
DEVICES SUPPORTED
In the universal memory mode, the following is a partial list of
devices supported:
or
ROM-Rockwell
.2712B
. EPF!OM~lritel
In the high speed mode,: the following
supported:'
Memory A consists of 2K •. 4K, 8K, or 16K memory devices
installed in the four sockets :assigned' as Memory A Memory B
;llso consistl! '01 memory devices located in, four sockets designated as. M!'!rT1ory B. Thus, the capacity of Memory A or
Memory B is dependent on the capat:ityof the memory devices
installed in each socket. Each of ihe two groups offour sockets
can be configured with jumpers to accept one of the four types
(2K, 4K, 8K, or 16K) of memory devices. Each memory device
in the memory sockets in Memory A or Memory B must have
the same capacity.
.is ~ partial list of devices
64K of the following 8K d!!vices:
R2364A, . R2364B
68A764
68766
2764
5564
6264
8464
9-34
ROM-Rockwell
Ii'PROI\t'1-Motorola
EPROM-Motorola
EPROM-Intel
RAM-Toshiba
RAM-Hitachi
RAM-Fujitsu
RM65.. 3264NE
Universal Memqry Module
RM 65 Bus Pin Assignments
Bottom (Solder Side)
Signal
Mnemonic
Pin
la
2a
3a
4a
5a
6a
7a
8a
9a
lOa
lla
12a
13a
14a
15a
16a
17a
18a
19a
20a
21a
22a
23a
24a
25a
26a
27a
268
29a
30a
31a
32a
Top (Component Side)
Signal Name
GNO
BADRI
GNO
BA13/
BAII/
BA10/
BA8!
GND
BAS/
BA3/
BA2/
BAO/
GNO
BSO
BROV
Pin
Ie,
2e
3e
4C
5e
6c
7e
Ground
Buffered Bank Address
Ground
Buffered Address Bit 13
Buffered Address Bit 11
Buffered Address Bit 10
BUffered Address Bit 8
Ground
Buffered Address Bit 5
Buffered Address Bit 3
Buffered Address Bit 2
Buffered Address 'Bit 0
Ground
'Buffered Set Overflow
'Buffered Ready
'User Spare, 1
'+12 Vdc/+V
GroundUne
'Buffered OMA Terminate
• User Spare 3
Buffered Read/Write "Not"
'System Spare
Ground
'Buffered Interrupt Request
Buffered Phase 2 UNot" Clock, '
Buffered Phase 2 Clock
Buffered Oata Bit?
Ground
Buffered OijlaBit 4
Buffered Oata Bit 2
Buffered Data Bit 1
+5 Vdc
+12V/+V
GNO
BOMT/
BA/Wi
GNO
BIRQf
B¢2I
B%2
B07/
GNO
B041
B021
BOI/
+5V
Signal
Mnemonic
-t,5V
BAI5/
BA14!
BAI21
GNO
BA9/
BA7/
BASI
BA4I
GNO
BAI/
B¢1
BSVNC
BDRQ1/
GNO
Be
9c,
IOc
l1c
12e
136
14c
15c
16c
17c
18c
190
20c
21c
22c
230
24c
25c
26c
27c
28c
290
30c
3te
32c
~1,2V/-V
BFLT/
B¢O
GNO
BORQ2I
BRlW
BACT!
BNMI/
GNO
BRES!
BD6/
B05/
B031
GNO
BOO/
GNO
Signal Name
+5 Vdc
Buffered Address Bit 15
Buffered Address Bit 14
Buffered Address Bit 12
Ground
Buffered Address Bit 9
Buffered Address Bit 7
Buffered Address Bit 6
Buffered Address Bit.4
Ground
Buffered Address Bit 1
'Buffered Phase 1 Clock
'Buffered SynC
'Buffered DMA Request 1
Ground
'-12 Vdc/-V
• User Spare 2
*Bu,ffered Bu~ :Float
'Buffered External Phase 0 Clock
Ground
'Buffered'DMA Request 2
'Buffered Read/Write
Buffered Bus Active
'Buffered Non-Maskable Interrupt
Ground
'Buffered Reset
Buffered Data Bit 6
Buffered DalaBit 5
Buffered Data Bit 3
Ground
Buffered Oata Bit 0
Ground
Note: • Not used on this module
p,
r-
,
BO_ITO
BP7/
8
I
I
BACl!
e.'21
B~TO
8K
8
~
,.
ADDRESS
AND
P.•
,.
CONTROL
SR!W/
MODULE
ACTIVE
.-~
BA131 8A14/ 8A15{
8A13/
8
MEMORY
DATA BUS
TRANSCEIVERS
ADDRESS
HEADER
MEMORY A
DECODER
8
HtG~
"SPEED
OPTION
SHUNT
I
•
8
8
,r
t I
H
DEVICE
SELECT A
~
BUFFER
~
UNIVERSAL
MEMORY
OPTION
SHUNT
BADRI
A
BANK
ADDRESS
SELECT
-
~
~
~
MEMORY 8
oeC:ODER
.}.-
4
~
Universal Memory Module Block Diagram
9-35
~
•
H
MEMORY
•
I
DEVICE
SELECT B
J
Universal Memory Module
RM65-3264NE
SPECIFICATIONS
Parameter·
Value
Dimenslons(1,2,3)
Width
Length
Height
100 min (3,94 in.)
160 mm (6.3 in.)
14 mm (0.56 in.)
Weight
156 9 (5.5 oz.)
Environment
Operating Temperature
Storage Temperature
Relative Humidity
O°C to 70'C
- 40°C to 85°C
0% to 85% (without conden~tion)
Power Requirements
5.0V (420 mao typical, 640 mao maximum with no memory devices installed)
Connector
RM 65 Bus Connector Pl
64-pin plug (0.100 in. centers) per DIN 41612 (Row b not installed)-mates
with Burndy P196B32ROOAOOL-9 or equivalent.
Notes:
1. Height includes the maximum values for component height above the beard surface (0.4 in. for pbpulated modules), printed circuit board
thickness (0.062 in.), and pin extimsion through the bottom of the module (0.1 in.).
2. Length does not include the added extension due to the module ejector.
3. Dimensions conforin to DIN 41'612.
~
' ' ' .••
. ,(6.6
IN..) ~
,"
rl?
WL
.
.
LENGTH
~,
MA'
••
MOTHER,E!OARO,
AND RECEPTACLE
~-r/
. Ii
II
II
.1
II
..........
EUROCONNECTOR
EXTENSION
~
I__
Module Dimensions
L
HEIGHT
r
EUROCARD CONNECTOR
COMPONENT AREA
o::--~- -_
~
RM65-5101E
RM 65 Microcomputer Family
'1'
Rockwell
RM65-5101E
RM 65 FLOPPY DISK CONTROLLER
(FDC) MODULE
RM .65 MICROCOMPUTER MODULES
FEATURES
The RM65-51 01 E Floppy Disk Controller Module is one of the
hardware options available for the RM 65 Microcomputer Module
family.
•
•
•
•
•
RM 65 Microcomputer Module products are designed for OEM
and end user microcomputer applications requiring state-of-theart performance, compact size, modular design and low cost.
Software for RM 65 systems can be developed in R6500
Assembly Language, PLl65, BASIC and FORTH. Both BASIC
and FORTH are available in ROM and can be incorporated into
the user's system.
Compact size-about 4" x 6%" (100 mmx 160 mm)
Pin and SOCket bus connection
RM 65 Bus compatible
Buffered address, data and control lines
Supports single or double sided, standard or mini-floppy disk
drives
• Controls up to four disk drives
• Interfaces directly to Shugart SA-850 or SA-450 disk drives,
with user options for other popular floppy disk drives
• Supports single~density IBM 3740 (FM) or double-density
IBM System 34 (MFM) formats
RM 65 modules use a motherboard interconnect concept and
accept any card in any slot. The 64-line RM 65 Bus offers
memory addressing up to 128K bytes, high immunity to electrical noise and includes growth provisions for user functions.
A selection of card cages provides packaging flexibility. RM 65
products may also be used wijh Rockwell AIM 65 and AIM
65/40 Microcomputers for product development and for a broad
variety of portable or desktop microcomputer applications.
•
•
•
•
PRODUCT OVERVIEW
The RM 65 Floppy Disk Controller (FDC) Module controls up to
four standard (8") or mini- (5%") floppy disk drives, singllj or
double sided, soft sectored with either single density (FM) or
double densijy (MFM) formal. Software control of media density
allows single or double density disks to be used in any connected drives.
OMA data transfer capability
Supports interrupt-driven or polled operation
Bipolar PROM Base Address decoding
Switches or jumpers for
-Bank Selection to one or two banks
-Double or Single sided operation
-Select or deselect ROM .
-Module disable
• On-board header configures I/O for 8" or 5v." drive interface
• Fully assembled, tested and wa.rranted
ORDERING INFORMATION
Two DIP headers configure. the FOC. to interface with eijher
standard or mini-floppy disk drives. An on-board jumper selects
single or double sided drives and a switch disables on-board
ROM. The FOC c:tirectly interfaces to most popula.rdrives with
only switch and/or header changes. Bank Select and Bank
Select Enable switches allow the F.DC module to be dedicated
to one.ol two 65K memory banks or assigned common to both
banks. The FDC module 1/0 can be assigned to any page (256
bytes) using a standard PROM if the ROM is deselected.
Part No,
RM6S-S101E
RM6S-S1 01 NE
ASS-090
A65/40-7090
Order No,
802
Description
Floppy Disk Controller (FDC) Module with
on-board ROM'
Floppy Disk Controller (FOC) Module
without on-board ROM
AIM 6S DOS 1.0 ROM"
AIM 6S/4O DOS 1.0 ROM"
Dascrlptlon
FOC Module User's Manual (included With
RM6S-S101E, RM6S-5101NE, A6S.Q90 and
A65/40.7090)
'ROM contains FOC module primitive subroutines only.
,. ROM contains FOC module primitive subroutines and operator
selectable file management functions integrated with host computer VO functions.
RM65-5101E Floppy Disk Controller (FDC) Module
Document No. RMA65N15
9·37
Data Sheet Order No, RM15
Rev_ 2, June 1983
RM65-5101E
Floppy Disk Controller (FOC) Module
sity, soft sector formats. The FOe features powerful commands,
including single or multiple record f!!ad/write with selectable
record lengths. Write precompensatjon circuitry ensures reliable
data recovery in double density formats. The Precompepsatibn .
jumper selects precompensation on all~racks, only on tracks 44 .
and greater, or no precompensation at all.
FUNCTIONAL DESCRIPTION
The Data Transceivers invert and transfer 8'bits of parallelqati\
between the FDC module and the.AM 65 bus, based on control
signals from the Base Address Decoder and the Controi Buffers.
The read/write control line determines the direction, whi.le the
bus active enables the Data Transceivers.
.
The Drive Configuration header selects the VOcorinector and
FDC circuitry for either 5W' mini-floppy or 8" standard floppy
disk formats. The 50-pin flO receptacle connects the FDC module
to a mass terminated cable connected to the installed disk
drives. A 34-pin cable and mating connector can be used .10
connect the 5%" mini-floppy drives while a 50-pin cable and
mating connector is needed to connect to the 8" floppy drives.
The
Address Buffers invert and transfer 12 of the 16 parallel
address lines from the RM 65 bus to the Base Address Decoder,
the Program ROM and the Floppy Disk Controller (FDC) device.
The Control Buffers invert and transfer phase 2 clock, reset, and
read/write control signals from the RM 65 bus onto the module.
The Bank Select Control circ;uit detects when the module'S
assigned memory bank is addressed by comparing the bank
address signal from the RM 65 bus to the Bank Select and Bank
Select Enable switches. The Bank Select Enable switch assigns
the module to be active 1n common memory (both Bank 0 and
Bank 1) or only in the Bank set by the Bank Select switch (either
Bank 0 or Bank 1).
The Drive Status Buffer allows detection of the Drive Configuration header and Single/Double Sided Drive jumper positions,
as well as selected dens tty and side information.
The Drive Control Register provides control of the side and drive
selection, motor on, head load, double density, and interrupt
disable. The Active Side 0 Level jumper allows the use of various drives without modification.
The Interrupt and DMA Control circuit enables operation in
either an interrupt driven mode or .under DMA control. Both
Interrupt generation and DMA requests can be disabled under
program control. The DMA request is jumper selectable for
either of two DMA request lines connected to the RM 65 bus.
The Ready State Gen~rator provides wait states as required by
the FDC device.
The Program ROM contains primitive subroutines to support
operations with up to four disk drives (single or double side,
single or double density), including:
The Base Address Decoder, wah the Base Address Select
PROM, the Bank Select Control circuit, the ROM Disable switch,
and the phase 2 and read/write signals control device selection
on the module. The Base Address Select PROM compares the
eight most significant address lines to the programmed
addresses to generate device select signals to the Program
ROM and the I/O devices. The ROM Disable swftch assigns the
module to be active either in a 256 byte page (disabled) or in
a 4K byte block (enabled). A separate Module Disable switch
allows the entire module to be disabled.
Format a Disk
Read or Write a Sector
Seek or Verify Seek of
a Track
Restore the Head
Read or Write Multiple
Sectors
Read or Write a Track
Turn Motors On or Off
Select or De-select any Drive
A user-provided program may call these subroutines to build an
application dependent file-handling system.
When the ROM is disabled, only the I/O devices are active, in
the 256 byte page that matches all eight Base Address Select
bits. For the flO devices, the three least significant address
lines, along with the. phase 2 clock and read/write control signals, drive register select lines to the FDC device, and· device
select lines to the Drive Status Buffer and Drive Control Register.
OPTIONAL DISK OPERATING SYSTEM
(DOS) FIRMWARE
Two optional ROMs are available that integrate the FDC primitive subroutines with operator selectable file management functions for operation on the AIM .65 and AIM 65/40 microcomputers.
Either of these ROMs may be installed into the PROM/ROM
socket on the FDC module to provide a firmware based Disk
.
Operating System (DOS).
When the ROM is enabled, the module is active in the 4K byte
block that matches the four most significant Base Address
select bits. The program ROM is selected except when the
address matches the four least significant Base Address Select
bits, in which case the I/O device select lines are selected.
This version 1.0 ROM-based system offers the same convenience as the other AIM 65 and AIM 65/40 firmware in that it
is immediately available fot use through the'Debug Monitor/Text
Editor upon power turn-on. Mass storage operation may, therefore, proceed without waiting for loading of the DOS into RAM.
The Controller Clock derives a reference frequency for the FDC
device from a crystal controlled oscillator. The frequency is 1
MHz or 2 MHz, depending on the Drive Configuration Header
position.
Text and program source code may be written to, and read from,
disk with the E:ditor LIST (L) and READ (R) commands, respectively. Similarly, binary data and program object code may be
written to, and loaded from, disk using the Monitor DUMP (D)
and LOAD (L) commands, respectively. AIM 65 and AIM 65/40
The FDC device, in conjunction with the Data Separator and
Precompensation Circuitry, interfaces the RM 65 bus to the
Floppy Disk medium. The. circuitry supports 5%" or 8", single
or double sided disk drives, with choice of single or double den-
9-38
,~.
RM650.6101,~
F'oppy Disk Controller (FD~) "O«:Iule
. ~',,'"
Assembler. and PU65 files, both sour~e and object code, are
therefore supported. AIM 6.5 and AIM 65140 ~ASIC programs
may also be saved on, and loac;l~ from disk.
.
the disk fOrrJ:\at' function initializeS a disk depending upon size,
. density and drive number. 5W' and 8' disks are initialized to 35
and' 77 tracks, respectively; however thE/se values are 'useralterable.
.
.
.
The primary DOS commands are:
Format a Disk
Ust the Directory
List a File
The
contents of a file may' be listed to another peripherali
including a file on another disk drive to allowcopying.of a file.
All the active files on a disk may be copied to another disk using
the backup function.
' .
Delete a File Name
Recover a File Name
Backup a Disk
Files are created automatically llpon writing a file to disk. A file
name (up to 10 characters in length) and the disk drive number
(from 1 to 8) are ope'rator entere,d i(l response to system prompts.
(Double-sided drives are treated ,as .twoseparate sides.)
'~'
.'
A file may be deleted (ff active) to prevent itirorn being accessed
or recovered ,(if· deleted) to allow it to be accessed.
I/O
CONNECTC!A
~DRE.
GOrlNS
ISTANDARD
FLOPPYI
TIMING
AND
CONTROL
......
34 PINS
IMIN'I·
ADI;JREII
FLOPPYI
iNTERRUPT
RIADY
READY
....ATE
,Gl.NERAtOR
Floppy Disk Controller Module Block Diagram
. 9-39
RM65-5101E
Floppy Disk Controller (FOC) Module
RM 65 Bus Pin Assignments
Bottoin (Solder Side)
Pin
la
2a
3a
4a
Sa
6a
7a
8a
9a
lOa
l1a
12a
13a
14a
lSa
16a
17a
18a
19a
20a
21a
22a
23a
24a
25a
26a
27a
28a
29a
30a
31a
32a
Signal
Mnemonic
GND
BADA/
GND
BAI31
BAil!
BA101
BABI
GND
BASI
BA31
BA2/
BAOI
GNO
BSO
BRDY
+12V/+V
GND
BDMTI
BA/Wi
GNO
BIROI
ap'2!
~2
B071
GNO
B041
BD2/
BOil
+5V
Note:
• Not used on this module.
Top (Component Side)
Signal Name
Ground
Buffered Bank Address
Ground
Buffered Address Bit 13
Buffered Address Bit 11
Buffered Address Bit 10
Buffered Address Bit 8
Ground
Boffered Address Bit 5
Buffered Address Bit 3
Buffered Address Bit 2
Buffered Address Bit 0
Ground
'Buffered Set Overflow
Buffered Ready
'User Spare 1
+12 Vde
Ground Une
'Buffered OMA Terminate
• User Spare 3
Buffered Read/Write ':Not"
'System Spare
Ground
Buffered Interrupt Request
Buffered Phase 2 "Not" Clock
'Buffered Phase 2 Clock
Buffered Data Bit 7
Ground
Buffered Data Bit 4
Buffered Data Bit 2
Buffered Data Bit 1
+5 Vde
Pin
.
Ie
2e
3c
4c
50
6e
7e
8c
ge
10e
lie
12e
13e
14c
15c
16c
17e
18c
1ge
20e
21e
22c
,23c
24c
25c
260
27e
28c
2ge
30e
31c
32e
Signal
Mnemonic
+5V
BAI5!
BAI4/
BAI2/
GND
BA91
BA71
BA61
BA4/
GND
BAil
B~1
BSYNC
BOROll
GNO
-12V/-V
BFLTI
B~O
GNO
,BOR02/
BA/W'
BACTI
BNMV
GNO
BRESI
BDSI
BD51
B031
GND
BDOI
GND
Signal Name
+5 Vde
Buffered Address Bit 15
Buffered Address Bit 14
Buffered Address Bit 12
Ground
Buffered Address Bit 9
Buffered Address Bit 7
Buffered Address Bit 6
Buffeted Address Bit 4
Ground
Buffered Address Bit 1
'Buffered Phase 1 Clock
'Buffered Sync
Buffered DMA Request 1
Ground
'-12 Vde/-V
'User Spare 2
'Buffered Bus Float
'Buffered External Phase 0 Clock
Ground
Buffered OMA Request 2
• Buffered Read/Write '
Buffered Bus Active
'Buffered,Non-Maskable Interrupt
Ground
Buffered Reset
Buffered Data Bit 6
Buffered Data Bit 5
Buffered Data Bit 3
Ground
Buffered Data Bit 0
Ground
RM6S-S101E
Floppy Disk Controller (FDClModule
I/O Connector Pin Assignments
Mini-Floppy Disk brive
Interface Cable Connector (2)
Standard Floppy Disk Drive
Interface Cable Connector
FDC Module
I/O Connector
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Pin
Signal Name
Pin
2
4
6
8
10
12
14
Track> 43 (Remex & ·MFE or equivalents)
N.C.
N.C.
Track> 43 (Caldisk or equivalents)
N.C.
N.C.
2nd Side Select
N.C.
Head Load
Index
Drive Ready
N.C.
Drive Select #1
Drive sell #2
Drive Sel
#3
Drive Select #4
Direction In
Step Pulse
Write Data
Write Gate
Track Zero
Write Protected
Read Data
N.C.
N.C.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Signal Name
N.C.
N.C.
Drive Select #4
Index
Drive Select #1
Drive Select #2
Drive Select #3
MolorOn
Direction In
step Pulse
Write Data
Write Gate
Track Zero
Write Protected
Read Data
2nd Side Select
N.C.
Notes:
1. All odd numbered pins are GND.
2. Pin 1 of the 34-pin mini-floppy disk drive interface cable connector should be keyed to pin 17 of the FDC module I/O connector.
6.BIN.
(172 MM)
MATING
MOTHERBOARD
AND RECEPTACLE
LENGTH
WIDTH
LL----~--L
~~
EUROCONNECTOR
EXTENSION
EUROCARD CONNECTOR
COMPONENT AREA
~----~ ------,
Floppy Disk Controller Module Dimensions
9-41
RM65-5101E
Floppy Disk Controller (FDC) Module
SPECIFICATIONS
Parameter
Value
Dimensions (1, 2, 3)
Width
Length
Height
3.9 in. (100 mm)
6.3 in. (160 mm)
0.56 in. (14 mm)
Weight
5.2 oz. (145 g)
Environment
Operating Temperature
Storage Temperature
Relative Humidity
Power Requirements
Interfaces
RM 65 Buslnterface
VO Connector
O'C to 70'C
-4O'C to +8S'C
0% to 85% (Without condensation)
+5 Vdc ± S% @ 600 mA-Typical
900 rnA-Maximum
+12 Vdc ±S%@60mA:-Typical
190 mA~Maximum
•
64-pin plug (0.100 in. centers) per DIN 41612 (Row b not installed)
SO-pin mass terminated connector (0.100 in. centers)
Mates with I&B/Ansley Part No. 609-5001 M or equivalent
Notes:
1. Height includes the maximum values for component height above the board surface (0.4 in. for
thickness (0.062 in.), and pin extension through the. bottom of the module (0.1 in.).
2, Length does not include the added extension due to the module ejector.
3. Dimensions conform to DIN 41612.
9-42
populat~d
.,
modules), printed circuit board
RM65-5102E
RM 65 Microcomp;"'erFamily
RM65·5102E
RM65 CRT CONTROLLER (CRTC) MODULE
RM 65 MICROCOMPUTER MODULES
FEATURES
The RM65-5102E CRT Controller Module is one of the hardware options available for the RM 65 Microcomputer Module
family.
• Compact size-about 4" x 6%" (100 mm x 160 mm)
• RM 65 bus compatible
• 4K Byte character generator ROM with:
-Upper and lower case alphabetics
-Special characters
-Numbers including subscripts and supersCripts
-Math symbols
-Semi-graphics
RM 65 Microcomputer Module products are designed for OEM
and end user microcomputer applications requiring state-of-theart performance, compact size, modular design and low cost.
Software for RM 65 systems can be developed in R6500
Assembly Language, PLl65, BASIC and FORTH. Both BASIC
and FORTH are available in ROM and can be incorporated into
the user's system.
• On-board ROM firmware supports:
-Scrolling
-Screen editing
-Full cursor movement control
-Full screen standard or inverse video
-Predefined formats for
80 column by 25 row (50/60 Hz)
72 column by 22 row,(50/SO Hz)
40 column by 25 row (60 Hz)
40 column by 16 row (60 Hz)
-Selectable format from 1 to 80 columns by 1 to 25 rows
-NTSC (60 Hz, 525 lines per frame) and European (50 Hz,
625 lines per frame) raster format
-CRT display driver for AIM 65
RM 65 modules use a motherboard interconnect concept and
accept any card in any slot. The 64-line RM 65 Bus offers
memory addressing up to 1281< bytes, high immunity to electrical noise and includes growth provisions for user functions.
A selection of card cages provides packaging flexibility. RM 65
products may also be used with Rockwell AIM 65 and AIM 65/
40 Microcomputers for product development and for a broad
variety of portable or desktop microcomputer applications.
PRODUCT OVERVIEW
The CRT Controller (CRTC) Module interfaces the RM 65 to a
CRt monitor or television receiver. The CRTC module outputs
HSYNC, VSYNC, and raw video signals for direct connection
to CRT Monitor, and composite video fol connectibn to a CRT
monitor or to a TV receiver through an RF modulator. A socketed on-board ROM generates 5 x 7 characters with two descenders in a 7 x 10 dot matrix field to, provide upper and lower
case alphanumerics and special symbols. The 2K bytes of onboard display RAM are memory-mapped.
• Single 5 volt operation
• Fully as~mbled, tested and warranted
a
A 2K-byte program ROM provides firmware to configure the
display format for 80 columns by 25 rows or 40 columns by 16
rows, scan rate of 50 or 60 Hz, and a CRT display driver for
AIM 65. There are alSO cursor control, screen editing, and utility
'ro(Jtines.
ORDERING INFORMATION
Part No.
RM65-5102E
Description
CRT Controlier (CRTC) Module
Order No.
814
Description
CRT Controller (CRTC) Module User's
Manual (included wtth RM65-5102E)
RM65-5102E CRT Controller (CRTC) Module
Document No. RMA65N14
Data Sheet Order No. RM14
9-43
Rev. 1,
June 1983
CRT Control.ler (CRTC) Module
RM65-5102E
FU'NCTIONAL DESCRIPTION
The Data Transceivers invert and transfer 8 bits of parallel data
between the CRTC Module and the RM 65 bus, based oncontrol signals from the Base Address DeCOder and the Control
Buffers, The read/write control line determines the direction,
while the bus active enables the Data Transceivers.
so the display can be updated by a.:block memory move or
under DMA control. The Refresh RAM Multiple)Cerand RAM
Transceiver allow the RM 65 bus and the .CRTC deVice 10 both
access the Refresh RAM, with the RM65 bus having priority
when any conflict occurs.
The Address Buffers invert and transfer the 16-bit parallel
address lines from the RM 65 bus to the Base Address Decoders,
the R2316 ROM, the CRT Controller (CRTC) device, and to the
.
Refresh RAM device.
The Display Enable Status Buffer allows the RM 65 bus to monitor the active display times, so that display memory transfers
can be made with no visible distortion.
The Character Generator ROM holds the fonls for the character
set. These fonts are stored' as 256 characters, eaCh with 10
seven-bit rows. The four CRTC device row address lines and
the eighl Character Latch bits, which hold the character being
refreshed, create an address for the character generator ROM.
The output data of the ROM, which is seven parallel bits, represents the display pattern. The Shift Register takes this data
and forms the serial video data. The Video Summer combines
and buffers the .serialvideo data with CRTe device timing signals to form a composite video output and a separate video,
horizontal sync, and vertical sync.
The Control Buffers invert and transfe~ the phase 2 clock and
read/write control signals from the RM 65' bus onto the module.
The Bank Select Control circuit detects when the module's
assigned memory bank is addressed, by comparing the bank
address Signal from the RM 65 bus to the Bank Select and Bank
Select Enable switches. The Bank Select Enable switch allows
the board to reside in common memory (both Bank 0 and Bank
1) or only in the Bank set by the Bank Select switch (either Bank
OorBank 1).
The Program ROM contains the firmware for an intelligent CRT
driver, in addition 10 utilities to aid in custom CRT display
application software. There are six predefined screen/ormats,
including 25 lines of 80 characters (50 or 60 Hz), 22 lines of 72
characters (50 or 60 Hz), 25 lines of 40.qharacters (50 Hz), and
16 lines of 40 characters (60 Hz). For other formats, any dimensions from 1 to 25 . lines of from 1 10 80 characters can be
defined (50 or 60 Hz). Full screen inverse video and 256 display
characters allow flexible display capabilities.
The Base Address Decoder, with the Base Address Select
switches, the Bank Select Control circuit, the ROM Disable
Switch and the read/write and phase 2 clock signals, generates
device selects for the on-board ROM, RAM, and VO (CRTC
device and Display Enable Status Buffer). The Base Address
Select switches allow the module to be selected to any 4K block.
Within the selected 4K block, the RAM is aSSigned to the lower
8 pages (2K bytes), and the I/O to the first 256 byte page of the
upper 2K bytes. When the ROM is disabled, only the RAM and
VO can be selected and the module is assigned 9 pages (2304
bytes) in memory. When the ROM is enabled, the module is
assigned the full 4K bytes, with 7 pages for ROM, in addition
to the RAM and I/O,
The intelligent display driver controls all screen updating and
cursor movement for the selected screen format. The cursor can
be on, off, or blinking with movements including liP, down, left,
right, home, and carriage return, as well as to any row and
column poSition. There. are many commands to facilitate screen
editing, such as:
.
.
The Controller Clock uses a crystal-controlled oscil'lator to derive
a 6 MHz or 12 MHz reference for the shift regisier dot clock
depending on the Dot Clock Select jumper position. With the 6
MHz clock, up to 40 characters per line can be displayed on any
monitor or standard television using .an RF modulator. Up to 80
characters per line can be achieved with the 12 MHz clock and
a high bandwidth monitor. Thl:j dOt clock is divided by seven to
provide a Characte(Clock for the CRTC device and a load character signal for the shift register.
Insert character or line
Delete character. or line
Clear 10 end of line
Clear to end of screen
Clear line or screen
Set or Clear special'character mode
The firmware utilities are useful for special applications. There
is also a display driver which replaces the AIM 65 on-board display wilh a CRT monitor and an AIM 65 Assembler listing reformatter which takes advantage of the longer display lines.
The Refresh RAM provides 2K bytes of display memory, for
screen densities of up to 25 lines with as many as 80 characters
each:The RAM is directly mapped into the RM 65 memory map,
9-44
RM~5102E
CRT Controller (CRTC)Module
RM 6SCRTC Control Commands
HeX
\18x
Code
.00
01
02
03
04
05
06
07
08
09
OA
08
OC
00
OE
OF
De8crlptlon
Character
.CTRL@
CTRLA
CTRLB
CTRLC
CTRLD
CTRLE
CTRlF
CTRLG
CTRLH
CTRLI
CTRLJ
CTRLK
CTRLL
CTRLM
CTRLN
CTRLO
Code
,
Clear Une
Clear to End of Une
Clear Screen
Clear to End of Screen
Clear Screen
Clear to End of Screen
.
Backspace~)
Horizontal Tab (-l
Line Feed (t)
Vertical Tab ( ~
Form Feed (Clear Screen)
Carriag.e Return (Home on Line)
Home on Screen
Home on Screen
t
.
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
Deacrlptlon
Character
CTRLP
CTRlQ
CTRLR
CTAlS
CTALT
CTRl U
CTRLV
CTRlW
CTRlX
CTRL Y
CTRLZ
CTRl[
CTRL\
CTRL]
CTRll\
CTRL_
Pass Through Next Character
,
,
Toggle Insert Character Mode
Delale One Character
Insert One Line
.Delete One Une
Display Cursor
Blank Cursor
Relink AIM 65 Display
.
Escape Character {ESC) (1)
Blinking Cursor
Enter Normal Characters
Perform Self Test
Reverse Video
'These characters halle no ellec!.
(1) There are two escape sequences as follows:
Hex Code
qharacter Sequence
Functlcin
lB 3D YY XX
ESC = Y x
'Move the cursor to the row y and column x position. with row y between top ($00) and bottom
($19). and column x between leftmost ($00) and rightmost ($4F),
lB 47
ESC G
Enter Graphics Character Mode
~ATA
IUS ACTIVE
ADDRESS
TIMINO"
AND
CONTROL
RAWVIDEi)
HSYNC
lANK
ADD"ESS
V SYNC
COMPOSITE
VIDEO
CRT Controller Module Block Diagram
CRT Controller (CRTC)MOduJe'
RM6S..S102E'
RM
65 Bus Pin Assignments
. "
BottOm (Solder Side) .
Pin
til
2a
3a'
4a
Sa
6a
7a
8/1
9a
10a
11a
12a
13a
14a
15a
16a
17a
18a
19a
20a
21a
,22a
23a
24a
25a
26a
27;1.
28a
29a
30a
31a
32a
Signal"
Mnemqnll?
GND
BADRI
rGND
BA13/
BA11!
BA10!
BAS/""
GND
BA5/
BA3I
BA2/
BAOI
GND
SSb
BRDY
+12V/+V
GND
BDMTI
BR/Wt
GND
BIRat
Bjil21
,~2
B07l
GND
BD41
BD2I
BD1!
+5V
......
,,:,',
Sig'n'.IName
",
,
Top (Corliponent Side)
"
Pin
,. ":,
Ground
Buffered Bank Address
t .~
' Ground
Buffered AddreSs Bit 13
Buffered Add~ss Bit 11
Buffered Address Bit 10
BLffered Address Bit 8
. Groupd
Buffered Address Bit 5
Buffered Address Bit 3
Buffered Address Bit 2
Buffered Addre'ss Bit 0
Ground
'Suffered SeIOverftow
'Buffered Ready
'USer 'Spare 1
'+12 Vdc/+V
Ground Une
'Buffered DMA Terminate
'User Spare 3
'Buffered Read/Write "Not"
'System Spare
Ground
'Buffered InterruPtR,equest'
Suffered Phase 2 "Not" C.lock
Buffered ·Phase 2 Clock
BUffered Data Bit 7
Ground
Buffered Data Bit 4
Buffered Data Bit 2
Buffered Data Bit 1
,
+5 Vde
le,
2e
3c
4c
5e
6c
7e
6e
ge
10c
11e
12e
13c'
14c
15c
16c
17c
16c
19c
20c
21e
22c
2Sc
24c
".
,
,
:"~5i:.
",.
26c
27c
28C
2ge
30c
31e
' 32e
Note:
• Not used on this module,
, ;Slgnal
MnemoniC
+5V
BAl5i
BAl41:
' 'BAl21
GND
BA9!,
BA?!
BA6/'
BA4I'
GND'
BA1!
..
;
~
Signallllame
;, ;
"
e¢'I'
BSYNC
BDR01!,
GND
-12v/-V
BFLT!
a,Jo
GND
BOR021
Ii!RliN
,BACT!
BNMV
GNO
BRES!
.,
BD6/
BDSt
B031
GND
aDO!
GND
:
'"
~1 "
..
'EURocARD CONNECTOR
Module Dimensions
9-46'
"
+5Vde
Buffered Address B~ 15
Buffered Address Bit 14
Buffered Address Bit 12
Ground
'Suffered Address Bit 9
,"
Buffered Address Bit 7
Buffered AddresS Bit 6
"Buffered Address Bit 4
Ground
' Buffered Address Bit 1
; 'Buffered PM.,1 Clock
'BufferedSynd "
'Suffered OMA Request 1
Ground
'-12 Vde(;:Y
..
'User Spare 2
• BU\4lred Bus Float
"BUffered 'Exi6rnal Phase 0 Clock
, ,,~i'Qjjnd. .
~.h/
'Buffered DMA Request 2
B~ Re8d!Wr~e ,
SUffered Bus Active
'Bl,!!fered Non-Maskable Interrupt
Ground
&Jffered Reset;
Buffered Data .Blt 6
Buffered Data Bit 5
Buffered Data Bit 3
Ground
Buffered Data Bit 0
Ground
RM65-5102E
CRT Controller (CRlC) Module
Character Set
1
2
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II
RM65..5102E
CRT Controller (CRTC) Module
'.,
SPECIFICATIONS
Value
Parameter
Dimensions (1, 2, 3)
3.9 In. (100 mm)
6.:3'ln. (160 mm)
0.56 In: (14 mm)
Width
Length
Height
Environment
Operating Temperature
Storage Temperature
Relative Humidity
Power Requirements
Interface
RM 65 Bus Interface
O'C t070'C
-40'C to +85"0
0% to 85% (without condensation)
.
'
'
"
+5 VcIC :1:5%,0.94 A (4,7 W)-Typical
1.30 A (6.8 W)-Maxlmum
64-pln plug (0.100 In, centers) per DIN 41612 (Row b not Installed)
va Connector
Composite Video
Mlnl-coax connector (50 ohm SMC type)
Mates to Sealeetro Part No. 050-024-0000-220 or equivalent
Raw Video and Sync
6-plnconnector
Mates to.AMP No. 87159-6 or equivalent
Notes:
1.. HelghtlncJudes the maximum values for component height above the board surface (0.4 In. for populated modules), printed. circuit board
thickness (0.062 In.), and'pin extensiOn through the bOttom oftherrl9dule (0.1 In.).
2. Length does not Include the added extension due to the module ejector.
. 3. Dimensions conform to DIN 41612.
9-48
RM65-5104E
RM 65 Microcomputer Family
'1'
Rockwell
RM65·5104E
RM 65 DIRECT MEMORY ACCESS
CONTROLLER MODULE
FEATURES
AM 65 MICROCOMPUTER MODULES
• Rockwell RM 65 Bus compatible
• Compact size-100 mm x 160 mm (approximately 4 in. x
,
6.25 in.)
The RM65-5104E Direct Memory Access Controller (DMAC)
Module. is one of the hardware options available for the RM 65
Microcomputer Module family.
.
• EXePutes memory~to-memory, 1I0-~1I0, memory-to-I/O, and
1I0-to-memory transfers
• DMA data transfers can be either within the same bank or
beween banks
• Memory address counters can either be incremented or
decremented
RM 65 Microcomputer Modules products are designed forOEIv'
and end user microcomputer applications when state-of-the~art
performance, compact size, modular design, and low cost are
requirlld. Software for RM 65 systems can be developed 'in
R6500 Assembly Language, PLJ65, BASIC, and Forth .. ~th
BASIC and .Forth are available in ROM and can be incorporated
into the user's system.
• Interleaved, cycle steal, and burst modes
• Processor-hold and processor-run operations
• Two DMA request channels
• DMA interrupt selectable either to the Non-Maskable Interrupt
or the Interrupt Request (BIRQ) line
RM 65. modules use a motherboard interconnect concept in
which any card can be inserted. into any slot. The 64-line RM
65 Bus permits memory addressing up to 128K bytes, provides
high immunity to electrical nOi!!9, and contains growth provisions for us.er functions. A selection of card cages allow!! packaging flexibility. RM65.products may also be used with RockWell
AIM 65 and AIM 65/40 Microcomputers for productdevelopment
and for a broad variety of portable or desk-top microcomputer
applications.
• 500K bytes per second maximum transfer rate
• DMA termination signal to abort any DMA transfer operation
in progress
.. Supports RM 65 FDC a-inch double-density operation
• Progra.mmable. Byte Counter for up to 65K_byte transfers
• Bank switches to assign 110' addreSses to either one or two
65K memory'banks
.110 Base Address switch selectable to a page boundary
PRODUCT OVERVIEW
The RM65-5104E DMAC Module performs high speed data
transfers between. memory andior 110 devices connected to the
RM 65 ~us, The data transfer rate When controlied,by the DMAC
Module hardware is typi9ally four times faster than the data
transfer r!lte achieved by CPU software. Thus by using the
DMAC Module, substantial time is saved when transferring large
blocks of data.
...
,
• Operates from a single +5V power source
• Fully assembled and tested with a one-year warranty
ORDERING INFORMATION
Description
After aOMA tranSfEir is initiatedby the CPU module, the DMAC
Module takes control of the.AM 65 Bus and independently completes the data transfers. Operation .of, the DMACModule can
beconirolled by an AIM 65, an AIM 65/40 SBC Module, or any
other CPU module connected to the RM 65 Bus. During the
DMA data transfers, the RM 65 SBC, AIM 65, or AIM 65/40 can
continue operations on its internal buses.
The DMAC Module is especially effective in the rapkl transfer
of data between either 5Y4-inch or a-inch floppy disks controlled
by either the FDC Module (RM65-5101E) or the RM 65 IEEE488 Module (RM65-7102E) and other memory or 110 modules
connected to the RM 65 Bus.
RM65-5104E Dlract Memory Access
Controller (DMAC) Module
DcicumentNo. RMA65N26
9-49
Data Sheet Order No. RM26
Rev. 1, June 1983
RM65-5104E
Direct Memory Access Controller (DMAC) Module
FUNCTIONAL DESCRIPTION
·
Addresses on the RM 65 Bus are compared with the address
set by the module Base Address switches. If the Bank ~Iect
Enable switch is set, the bank-address signal (BADR/) is compared with the signal from the Bank Select switch. When the
BADRI and address signal states on the bUS' match the signal
states generated by the Base Address and Bank Selectswltches,
the Microcode Generator, Chip Select, and Data ,Buffer, circuit!;
are enabled.
"
,
.'"
,
During DMA cycles, the DMAC Modu~is controlled by the State
Control ,Circuitry. When the DMAC Module is idle, module
operation starts or concludes in ,the Initialize Arid Condude
state. In the Read state, the source address from the Source
Address Generator is placed on the RM 65 address lines. Data
on the RM 65 data lines is then trarisferred from the SO\lrce
device' and ,saved in a temporary storage register, During the
Write state, the' destination address from the Destiriation Address
Geoerator is placed on the RM 65 address lines. Data in the
:Temporary Data Register is then placed on the RM 65 daia lines
and transferred to the destination device.
When the module circuits are enabled, the four least sil/nificant
address signals and the read/write signal (R/W-) generate chipselect and microcode signals. The chip-select signals enable
devices withintne DMAC Module enilei-, to accept or to out~ut
data. The microcode Signals control which registers iue active
in the DMA SoUrce Address, Destination Address, and Byte
Count Generators.
After the Write state, the byte count and mode qf operation
'aff~t the state which the DMAC Module next enters. If the byte
count is ze,ro, DMAC Module operation switches t6 the Initialize
And Conclude slate and control of both the RM 65 Bus and the
system returns to the processor. I! the bytec6uni is not zeJO,
then the' mode, of operation affects the next DMA state, When
the 'byte count is not zero and the data transfer is between two
memory devices, operation of the DMAC Module switches to
the Read state.
After the generators are enabled and selected, data can be
transferred between the module and the RM 65 Bus. Before the
start of a DMA operation, these generators must be initialized.
The Source Address Generator iind the Destination, Ad<;lress
Generator, r~spectively, mUl;! be load,ed to specify the starting
address of the Source and the destinatio'ri address during DMA
data transfers. Control registers must be loaded to specify if the
address is to bE! incremented or decremented after 'each 'liyte.
The Byte Count Generator must be ioi'\ded.to specify the number
of bytes of data to be transferred. A control byte in the Byte
Count Generator indicates whether the contents, of the register
are to be incremented, or, decremented. Typically, t,he Byte
Count Generator is set up to count down because the DMA
transfer stops when the byte count becomes zero. '
When the data transfer involves' 110 devices, DMAC Module
operation switches toa Read state if the DMA request signal
(or signals during ,I/O-to-I/O transfers) is present: 'ff the DMA
request signal is not present and the module is in the burst
mOde, the mode 01 operation sY{itches. to' a Hold state and
remains in the state until the DMA reciuest'signal is present.
Module operation then switches to a Read state. If the DMAC
Module is operating in an interleal(ed mode, the operation is
switched to the Initialize And Conclude state and control returns
to the processor. The module takes control again as soon as
sync and DMA request signals are present.
Contents of the Command Register specify the parameters the
DMAC Module is to use and start the DMA cycle. After the Command Regi,ster has been loaded, the DMAC Module waits for
two signals before beginning a DMA cycle. If the DMAC Module
is to transfer data to or from ao 110 device, a DMA~uest signal
must be received from the 110 device. For 1I0-to:1/0 transfers,
a DMA request must be received froin each 110 device. For
memory-to-memory transfers, the DMA request is generate<;l by
the DMAC Module. The second sigi\al required for DMA transfers is the sync signal, When the sync Signal goes high, the
DMAC Module forces the ready signal low (if the processor-stop
mode is enabled),'floats(effectively'i:!isconni:K;ts) the RM 65 Bus
from the microprocessor, and switches module operation to the
Read state.
"
'
At the endofaDMA cycle, after the byte count has been
redUced to zero and DMAC Module controi has sWitched to the
Initialize And Concluqe state, system control returns to ,the
microprocessor. The ready signal is disabled. The DMAC Module
Command Register is cleared and the' transfer-completeflag is
written into the Status Register. If the interrupt mask bit is not
set, either an interrupt request or a nonmaskable interrupt signal
is generated.
DMAC Module operating modes are controlled by bits in the
DMAC Module Command Register. Modes available are Halt,
Interrupt Mask, Burst, and:lnterleaved.
9-50
Direct ,.moryAccess. Controller (DMAC)· Module
RM65BUS
CONNECTOR
DATA
PHASE 2
(TIMING)
PHASE 1
ADDRESS
ADDRESS
CONTROL
DMA
REQUEST,
DMA
TERMIPfATE
INTERRUPT
RM65-5104E DMAC Module Block Diagram
9"51
RM65-5104E,
Direct Memory Access Controller (DMAC) Module
RM 65 Bus Pin Assignments
Top (Component Side)
Bottom (Solder Side)
Pin
la
2a
3a
4a
Sa
6a
7a
Sa
9a
lOa
l1a
12a
13a
14a
15a
16a
17a
18a
19a
20a
21a
22a
23a
24a
25a
26a
27a
28a
29a
30a
31a
32a
Signal
Mnemonic
GNO
BAO.R/
GNO
BAI3l
Signal Name
Grcund
Buffered Bank Address
Grcund
Buffered Address B~ 13
BA111
Buffered Address Bit 11
BA101
Buffered Address Bit 10
Buffered Address Bit 8
BA8/
GNO
Grcund
BAS/
Buffered Address Bit 5
Buffered Address Bit 3
BA3l.
BA2I
Buffered Address Bit 2
Buffered
Address' Bit 0
BAOI
Ground
GND
BSO
"Buffered Set Overflow
BRDY
Buffered Ready
"User Spare 1
+t2V/+V "+12 VdCt+Y
Ground;,
GNO
BOMTI
BufferedDMA Terminate
"User Spare 3
Buffered Read/Wr~e"Nbt"
BR/WI
' "System Silare
GNO
Ground
B.IRQ/
Buffered Interrupt Request
5;21
Buffered Phase 2 "Not" Clock
Buffered phase 2 Clock
8912
B071
Buffered Data Bit 7
GNO
Ground
BD4/
Buffered Data Bit 4
B021
Buffered Data Bit 2
Buffered Data Bit 1
BDll
+5V
+5 Vde
Pin
1/0
Ie
2e
3c
40
VO
VO
VO
VO
VO
50
et:
7e
8e
9c
lOe
lie
12e
13c
140
150
VO
VO
1/0
VO
0
let:
Signal
Mnemonic
+5V
BAI5/
BAI4/
BAI21
GND
BA91
' BA71
BASI
BA4/,
GND
BAtI
B;1
BSYNC
BDROli
GND
-12V/-V
17e
lBe
19c
20e
21e,
226
23e
240
250
2Be
27(';
2Be
29c
30e
31e
320
I
VO
0
a
va
VO
1/0
VO
I/O
Note:
"Not used on this module.
9-52
Bf'l:TI
B_O
GND
BDR021
BR/W
BAC!I
BNMI/
,GND
BRES!
BDSI
BD5/
BD3I
GND
BDO!
GND
Signal Name
+5Vdc
Buffered Address Bit 15
Buffered Address Bit 14
Buffered· Address Bit 12
Ground
B\lffered Address Bit 9
BOttered Address Bit 7
B·uffered Address Bit 6
Buffered Address B~ 4
Ground
Buffered Address Bit 1
'Buffered Phase 1 Clock
Buffered Sync
Buffered DMA Request 1
Grcund
>-12 Vdc/-V
~ \,Iser Spare 2
Buffered Bus Aoa!
"Buffered Extemal PhaS!'l 0 Clock
Grcund
Buffered DMA Request 2
Buffered Read/Write
B.uffered Bus Active
Buffered Non-Maskable Interrupt
Grcund
,. Buffered Reset
Buffered Dilla Bit 6
Buffered Data Bit 5
Buffered Data Bit 3
Grcund
Buffered Data Bit 0
Grcund
I/O
VO
1/0
VO
VO
VO
VO
VO
VO
I
VO
I
0
I
VO
0
0
I
VO
VO
I/O
VO
Direc~Memory Access Controller (DMAC) Module
SPECIFICATIONS
Parameter
Value
Dlmenslona(1:, "2,3)
Width
'
Length
Height
.100mm (3.9 in.)
1.64 mm,(6.4 in.)
14mm (0.56 in.)
137 9 (4.8 oz.)
'Weight
Environment
b·Oto 7O"C
Operating Temperature
Storage Temperature
Relative Hum[dity
-40"C to. +85·C
OO,b to 85%, wfthout condens,atlon
+5 Vdc ±5%,'at 1.2A (6.0W)-Typical
t.9A (9.5W)-:-M~imum
54-pin 'plug (0.100 in. centers) per OIN.41612 (a and b .wHh c not ,installed}
RM 85 ,Bua InterfaCe
N o t e s : ' "
1. Height Includes the maximum values for component height above the board surface (0.4 in.), printed circuit board thiqkness (0:062' in.), and
.
"
pin extension through the bottom of the modl!1e (0.1 in.).
2. Length does not include extensions beyond the edge of the module due to connectors or the module ejector.
3. Connector confOrms to DIN 41612.
r-
r
L"
WIDTH
:~:~
~
r-LENGTH~
I~
t'
::;SOARD
,I/ANDRECEPTACLE
'EUROCARD CONNECTOR
-fI
-1;
COMPONENT AREA,
Hr- ~
:1
JHT
I~
j.
£:;I
--'\-
'.'
.~.,.
----~
~ ~EUROCONNECTOR
EXTENSION
RM65-510<1E DMAC MoCtUIEI DImElm~ions
i--------'----"-~-~D
9-53
R~65-5222E
RM 65 Microcomputer Family
'1'
Rockwell
RM65-5222E
RM 65 GENERAL PURPOSE INPUT/OUTPUT
(GPIO) & TIME.R MODULE
RM 65 MICROCOMPUTER MODULES
ORDERING INFORMATION
The RM65-5222E GPIO & Timer Module is one of the hardware
options available, for the AM 65 Microcomputer Module family.'
Part No,
Description
General PurPose Input/Output (GPIO) and
Timer Module
.
RM65-5:;!22E '
RM 65 Microcomputer Module products are designed for OEM
and.,end user microcomputer applic;!tions requiring state-ol-theart performance, compact size, modular design and low· cost.
Software for RM 65 systerns' can be developed in R6500
Assembly Laqguage, PU65, BASIC ancj FORTH, Both BASIC .
and FORTH are available in ROM and can be incorporated into
the user's system.
Order No.
Description
801' "
,
RM 65 modules use a motherboard interconnect.concept and
accept any card in any slot. The 64-line RM 65 Bus offers
memory addressing up to 128K. bytes, high immunity to electrical noise and includes growth provisions lor uSer1unctibns.
A seleCtion ol,card cages provides packE!ging Ilexibility. RM 65
products may also be used wtth Rockwell AIM 65 E!nd AIM
65/40 Microcomputers for product development and lor a broad
variety of portable or desk-top microcomputer applications.
, 'General PurPoSe Input/Output (GPIO) and.
Timer Module i,Jsefs Manual (i~cluded w~h
RM6S-S222E)
FEATURES
•
•
•
•
.•
Compact size-about 4" x 6%" (100 mm x 160 mm)
Pfniliid socket bus connector
RM 65 Bus compatible
Fully buffered address, data and control bus interlace lines
Fully buflered data and control I/O lines
~,'Four 8-bit parallel bidirectional data ports'
;;' Four 2-bi! con~rol ports
• Four programmable 16-bit counter/timers
• TwO 8-bit shift registers lor synchronous serial communications
• Manually or software-controlled data line direction
• Jumper-selectable control line direction
• Bank select switches assign I/O addresses to one or two 65K
banks
• I/O' base address switch selectable to a page boundary
PRODUCT OVERVIEW
The RM65-5222E General Purpose InpUVOutput (GPIO) & Timer
Module provides a parallel I/O interlace to the RM 65 Bus. Two
R6522 Versatile Interface Adapter (VIA) devices provide four Bbit bidirectional data ports and four 2·bit control ports; 40 VO
lines in all. Two multi-mode l6-bit timer/counters extend the
versatility 01 the module. All I/O lines are TTL buffered.
The GPIO & Timer Module I/O can be assigned either to one
01 two 65K byte memory banks or common to both banks. Eight
switches allow I/O addresses to be set to any page (256 bytes).
Eight switches (two per I/O port) manually set the I/O tretnsceiver data direction or allow software control using the associated port control lines. Twelve jumpers specify the direction
01 the control lines.
• Four I/O connectors
• +5V operation
• Fully assembled, tested and warranted
RM65-5222E General Purpose Input/Output (GPIO) & Timer Module
Document No_ RMA65N12
9-54
Data Sheet Order No_ RM12
Rev_ 2, June 1983
RM65..;6222E
GPIO I. Timer MOdule
FUNCTIONAL DESCRIPTION
The Bank .Control circuit detects .when the GPIO & Timer
Module's assigned memory bank 1$ addressed by comparing
the bank addfeSs signal from the RM 65 Bus,to the Bank Select.
Enable and ,Bank ~)ect switches. Tile. Sank Select Enable
switch allows the module to ~ assigned common to either both
banks, or to Bank 0 (lower 65K) or Bank 1 (upper 65K) depending
on the Bank Select switch. ' .
The heart of the GPIO & Timer mod\ille is two R6522 Versatile
Interface Adapter (VIA) devices. Each VIA provides two B-bit
bidirectional input/ou!lM. ports, four VO controll,il:tes, two fully
programmable i6-blt timer/counters and an B-bit shift register
for serial InterfacE!. There is also control of Interrupt generation
from independent I/O conditions.
The two B-bit input/output peripheral ports are fully bidirectional.
Date direction registers allow each peripheral pin to independently act as either an input or an output. The four' control lines
can also be used for VO or' can provide handshaking for the
associated data ports. Each control input can be programmed
to interrupt the microprocessor on detection of a rising or falling
edge.
The Control BUfiers drive read/write, phase 2 clock, and reset
signals
the RM 65 Bus'to the GPIO.& Timer Module. The
interrupt request and bus~aOtivesignals ~ driven from the
GPIO & Timer Module.
.
frOm
The Base Address Decoders use the eight most significant
address lines to aSsiQ:llthe .32 110 addresses to a page (256
bytes) boundary; W~nan address is within range of the Base
Address switChes and the.Bank Control is enabled, a chip select
is generated to one of the R6522 devices.
Twelve Control Direction Jumpers allow the three bidirectional
control lines (CAi, OBi, and CB2) on each R6522 to be configured for either inpuler output mode.
The two i6-bit countet/timers are capable of many complex
timing and counting functIOns. One timer provides four modes
of operation: free running, with pulsed or toggl'ild output, oneshot interval timer with a low-level output pn a peripheral port
line, or one-shot interval timer with a toggle output on a peripheral port line. The three modes of the second i6-blt timer provide a one-shot interval timer, a count of external pulses, or a
clock for serial shift register. The shift register can shift in, or
shift out, data at the system clock rate, the timer clock rate, or
an external clock rate. Both timers and the shift register can be
programmed to interrupt the microprocessor upon time-out or
"
shift completion.
Four VO Direction Switc~s provide direction control to each of
the Port VO transceivers.. Four Programmed/Manual Select
switches allow the direction control to be established from the
Direction Control switches in the Manual mode or from a R6522
control line in the Programm~d mode.
The lIO Transceivers bWfer each of four a-bit VO ports. The
direction is determined by the Direction Control logic. There are
also eight buffers provided for the control lines (2 per VO port),
six of which can be configured for input or output as determined
by the Handshake Direction'Buffers.
The Data Transceivers inllert and buffer B-bitl! ,of parallel data
between the RM 65. Bus and the two R6522 VIA devices. The,
Data Transceivers are enabled when a valid address is present
at the Base Address Decoders. During a read operation, data
is transferred from the addressed R6522 to the RM 65 Bus.
During a write operation, data is transferred from the RM 65
Bus to the addressed R6522.
All VO data and control Signals are brought out to four connectors that will each accept a 20-pin mass terrninated~ribbon cable
(cable and mass terminated connectors
riot supplied with
the GPIO & Timer Module). Each connector is dedicated to one
pori with a data, 2 control and 10 grqund lines.
are
The Address Buffers invert the five least significant address bits
used to select the R6522 devices and registers.
OM ..
BUS CONNECTOR
r"'"
DAT A
•
s~
.-- ~
MDAT
A
TRANSCEIVERS
BUS
ACTIV E
PQRT 1
t--2
rf1
ADDRESS
•
ADDRESS
BUFF6:RS
•
'BAlE
~~E.ESS ~
ADDRESS
DECOot\!RS
.'TCHES
~
BANK'ADDRESS
BANK
SELECT
CONTROL
J
H
T
CONTROL
ANO
~
3
TIMING
CONTROL
I-- t -
I/O
t
,
I+-
I/O
t-
oJRECTION
CONTROL
LOGIC
BANK SELECT
SWITCH
•
•
2
2
1
BANK ENABLE
SWITCH
CONTROL
BUFFERS
~
f
CONTROL
DIRECTION
JUMPERS
."22
-
NO.2
'-
GPIO & Timer Module Block Diagram
9-55
I.
DATA
CONTROL
r_,
~.
2A
~
DATA
2
CONTROL
1/0
•
TRANSCEIVER
2
PORT 2
PORT 1B
2
2
VIA
3
•
I--
I/O
j-
~
CONTROL
BUFF15RS
DATA
J
DIRECTION
PROGRAMMED
/MANUAL
SWITCHES
INTERRUP
2
11O
TRANsceiVER
PORTt A
SWITCHES
l-
N.
•
I.
"'22
VIA
NO.1
PORT 2
DATA
J
CONTAOL
GPIO & Timer Module
RM65-5222E
RM 65 Bus Pin Assignments
Bottom (Solder Side)
Pin
1a
2a
Sa
4a
5a
Sa
7a
8a
9a
lOa
l1a
12a
13a
14a
15a
ISa
17a
18a
19a
20a
21a
22a
23a
24a
25a
2Sa
27a
28a
29a
30a
31a
32a
Signal
Mnemonic
Top (Component Side)
c
Pin
Signal Name
GND
BADRI
GND
BAI3/
BAW
ElA10!
BAa!
GND
BA5!.
BA3I
BA2I
BAO!
GND
BSO
BRDY
Ground
Buffered Bank Address
Ground
Buffered Address Bit13
Buffered Address Bit 11
Buffered Address Bit 10
Buffered Address.Bi! 8
Ground
'Buffered Addresl; Bit 5
Buffered Address Bit 3
Buffered Address Bit 2
Buffered Address Bit 0
Ground
'Buffered Set Overflow
'Buffered Ready
• User Spare 1 .
+12V1+V
'+12 Vdo/+V
GND
BDMTI
Ground Une
·Buffered DMA Terminate
'User Spate 3
Buffered Read/Write "Not"
·System Spare
Ground'
Bu'fferedlnterrupt Request
·BufferedPhSse 2 "Not" Clock
Buffered Phase 2 Clock
Buffered Data Bit 7
Ground
Buffered Data Bit 4
Buffered Data Bit 2
Buffered Data Bit 1
+5 Vdc
BR/W!
GND
BIRO!
BI'l21
9%2
BD7!
GND
BD4I
BD2I
BDI!
+5V
10
20
30
40
50
So
7c
Be
90
10c
110
120
130
140
..
150
160
17c
160
190
200
21c
22c
230
240
250
260
27c
28c
290
30c
31c
32c
Signal
Mnemonic
Signal Name
+5 Vdo
+5V
BA15!
BA141
BAI2I
GND
BA9!
BA7!
BASI
BA4I
GND
BAI!
B~1
BSYNC
BDR01!
GND
-12V!-V
BFLT!
B~O
'GND
BDR021
BRlW
BACT!
BNMV
GND
BRES!
BD6!
BD5I
BD3!
GND
BOO!
GND
Buffered Address Bit 15
Buffered Address Bit 14
Buffered Address Bit 12
Ground
Buffered Address Bit 9
·Buffered Address Bit 7
'Buffered Address Bit S
Buffered Address Bit 4
Ground
Buffered Address Bit 1
'Buffered Phase 1 Clock
'Buffered Sync
·Buffered DMA Request I
Ground
·-12 Vdo!-V
'User Spare 2
·Buffered Bus Float
·Buffered External Phase 0 Clock
Ground
·Buffered DMA Request 2
'Buffered Read/Write
Eluffered Bus Active
'Buffered Non-Maskable Interrupt
Ground
Buffered Reset
Buffered Data Bit S
Buffered Data Bit 5
Buffered Data Bit 3
Ground
Buffered Data Bit 0
Ground
Note:
'Not used on this module.
I/O Connector Pin Assignments
Pin
Signal
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
1
3
5
7
9
11
13
15
17
19
Notes:
1. Similar for ports 1B, 2A and 2B
2. Even Pins 2-20 are ground
9-56
1A
1A
1A
1A
1A
1A
1A
1A
1A
1Ii.
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data S
Data 7
Control CA 1
Control CA2
RM6S-S222E
GPIO & Timer Module
SPECIFICATIONS
Parameter
Value
Dimensions (1; 2, 3)
Width
Length
Height
3.9 in. (100 mm)
6:3 in. (160 mm)
0.56 in. (14 mm)
Weight
5.0 oz. (140 g)
Environment
Operating Temperature
Storage Temperature
Relative Humidity
O·C to 70"C
-40"C to +65°C
0% to 85% (without condensation)
Power Requirements
+5 Vdc ±5% 0.52 A (2.6 W)-Maximum
+5 Vdc ±5%0.94 A (4.70 WI-Maximum
Interface
RM 65 Bus Interface
64-pin plug (0.100 in. centers) per DIN 41612 (Row b not installed)
VO Interface
VO Connectors (4)
20-pin vertical mass tennination plug (0.3 in. pins on 0.100 in. centers)
Notes:
1. Height includes the maximum values for component height above the board surface (0..4 in. for populated modules), printed circuit board
thickness (0.062 in.), and pin extension through the bottom of the module (0.1 in.).
2. Length does not include extensions beyond the edge of the module due to connectors or the module ejector.
3. Dimensions conform to DIN 41612.
r--f'~;':.;MI----j ~~~~NE';.BOARO
r
L
WIDTH
1
J-LENGTH
t~
D0
DO
IjANDRECEPTACLE
EUROCARD CONNECTOR
-11
LO~O~E: ~~
'Iii
I
_
HEIGHT
_~.-...:.I!-.EUROCDNNECTOR
EXTENSION
RM65-5222E Module Dimensions
II
RM 65
'1'
Rockwell
Ri\465,,5223E
M;Crocomputer~a;'ilY
RM65-5223E
RM 65 MULTI~FUNCTION
PERIPHERAL INTERFACE MODULE
FEATUR,ES
RM 65 MICROCOMPUTER MODULES
• Compact size-about 4" x S%" (100 mmx 160 mm)
.• "Pin and socket bus,connection
THeRM65-1;i223E Multi-Function Interface (MPI) Module is one
of the hardware options available for the RM 65 MicrocompUter
Module f a m i l y . '
.
• RM 65 Bus compatible
.'TwQ R6522 Versatila.lnterface Adapter (VIA) devices
RM 65 Microcomputer Modules products are designed for OEM
and end user microcomputer applications requiring state-of-theart performance, compact size, modular design and row cost.
,Software for RM 65 systems can be developed in R6500
Assembly Language, PLl65, BASIC and FORTH. Both BASIC
and FORTH are available in ROM and'can be incorporated into
·the 'user's system.
"
,
• Four fully buffered 8-bit parallel data ports
• Four fully buffered 2-bit control ports
'
• Four programmable 16-bit counter/timers
• Two serial input/output ports
• Multiple interrupt conditions
.• Full buffeiing on all I/O data and control line~
• SoftWare-c6ntrolied data line direction
"
• Jumper-selectable contr~lline dirE!<;tk>n
'. Data port buffering can be removed
,
• A,II I/O lines are"availiible on twQ ,4O-pin I/Q c,onn!lcJors
• VO connectors are compatible w~h, both the AIM 65/40 and
RM.65 SBC module parallel I/O connectors and AIM 65/40
intelligent .peripherals
• One connector is fully compatible with the AIM 65/40 standard or extended keyboard
RM 65 modules use a motherboard interconnec{concept and
accept any ,card in any slotTIJe 64-line RM 65 Bus,offers
'memory addressing up to 128K bytes, high, immunity to electrical noise and includes growth provisions for u$er functions.
A selection of card cages provides packaging flexibilHy,. RM 65
products may also be used with Rockwell AIM"65 and AIM
65/40 Microcomputers for product development and for a broad
'variety of portable or desk-top microcomputer applications.
PRODUCT OVERVIEW
The RM65-5223E RM 65 Multi-function Interface (MPI) Module
provides a parallel I/O interface to the RM 65 Bus. Two R6522
Versatije Interface Adapter (VIA) devices provide four 8-bit
bidirectional data ports and four2-bit control ports; 40 VO lines
in all. Two multi-mode 1,6-bit timer/counters .extend the versatilHy of the module. All i/o lines are TTL buffered and available
connectors compatible wtth the AIM 65/40
on two 40 pin
SBC and RM 65' SBC Parallel, Application connectors. Data
buffer direction is under direct software control. Twelve jumpers
specify the direction of the control lines, while an addition,al 6
jumpers control the optional features,
• ,Bank swHches assign VO addresses to one or two 65K banks
• I/O base address switch selectable to a page boundary
• +5V operation
• Fully assembled, tested and warranted'
va
ORDERING INFORMATION
Part No.
RM65-5223E
The MPI Module VO can be assigned either to one of two 65K
byte memory banks or common to both banks. Eight swHches
allow I/O addresses to be set to any page (256 bytes).
Order No.
817
Description
Multi·funCtion· &ipherallnterface (MPI)
Module
.
'
Description
Multi·function Peripheral Interface Module
(MPI) Module User's Manual (included with
RM65-$'Fj~~'~_~' .
"?~
.
:'l!de
tyibdule
straight in until it touc~s:the mating mothetooard .rec~t'I..,.;:;,,,
Remove power from the' PMS \tIotherbOarif before
. remOVing a Qiodllie. .
.
.
.', ,~an'facturer"":'ETRllnc
~, .ModeI760~99XW-182.:11,1W
,"."'
.~'
•
t
,)ile
I
Remove a modl,lle from the PMS'a:sto'l6ws;:~:
1he cooliri!j, f!IDpqwer leads to the /'ecjuiredpowersLipJ;ilY;
:
'
mOd~1e
c. En!!ure that the
'connect()r is positioned properly
against the mating receptacle.
.
. "
,
"
,""
d .. Press in firmly on the ex~sededgeof the modl,lle until it is. '
..
.
firmly:se-ated.
,
" ..
,
.
I.
a.,l,ifl uPPfl thE! rry~du.re ej~tOrtab,iflnstan~;01h9lWise grasp'
theexpo!l8~~geo~'themOdUIe and pull,to rel$8~ the
modl,lle riomtlJ~ 1!1~~g9recept~.I~.
'
USVeiO,'S0I60 Hz, 6 watts
2500 RPM::'SO CFM
1Q02.,
b. Pull the mOdulemra.igll!~~~ulJtllitis,free
guides.'
~ ~I 760-9$XW-181-11220"
220 Vac,501$O Hz, 6 watts
I
2500 RPM, aoCFM
; 1002.
.
i
TRequires plug-in power cord, 3Q" long-Model 760-9601-6.
~-75
from the card slot
,
· 4-SJot, Piggyback ModOle,Stack and Motherboard
RM65-7004E. RM65-7004NE
4-CONNECTOR MOTHEfU:,OARD
ASSEMBLY
',',
The RM65-7004NE 4-slot motherboard can
.
.,
follows:
b6
assembled as
b. Solder the recepta91e pin connections to the' back of the
PCB.
a. Install up to four module connectors (receptacles) from!he
front of the PCB. Be sure to observe correct conneclor orientation. The following connectors or their' equivalent, may
be used:
c. Install the mini-terminal striptQ the power supply connection
holes from the back of the PCB.
Part No.
.
d. Solder the mini-terminal strip leads to the 'front of the PCB.'
Manufacturer
P196B32ROOKOOK9
Burndy Co~ration
Norwalk, CT 06856
968-6033-0531 -.3
Winchester Electronics
Oakville, CT 06779
00-8257-096-649-124
Eico Corporation
Huntington, Ph. 16652
'!NSTALL MODULES FROM
THIS END
0.'
-,IZO
r--t.3_MM_I.......
I----....;.-~;:OMMI,..·- - - - - 1
BOTTOM VIEW
"~'
LEFT SIDE ViEW"
~Slot
END VIEW
Piggyback Module Stack and Motherboard
9-76
-
FtM6~io04E. RM65-1004NE
"1.,
4-SlotPiggyb~kModule Stack and MotherboEird
'
~PECIFICATIONS
.....
,
Parameter.
.. ,'
'.J
~
RM6S,7004E 4rSlot PIIiS Dimensions
Width
Len9th
Height
",
:
,
Value
'.,
"
4.96 in. (126 mm)
8.00 in. (203 mm)
3.89 in. (99 mm)
,
Weight
"
',,'
13 oz. (370 g)
Module Separation
Slot 1: Centerline to Inside Top Cover
other Slots: Centerline to CenterUne
. ',C', .
'.'
i
.
0.85 in. (22
mm)
a.6. in, (15ml11j'
RM8S,7004NE Motherboard Dimensions
Width
.. '
.
.
.
3.938 in. (100 mm)
2.562 in. (65.1 mm)
0.062 in. (1.6 mm)
Length
Height
Hole Size
Uncoded
0.037 in•. (0.940 mm) dia.
. 0.044 in. (1.12 mm) dia.
0.128 in. (3.25 mm) dia.
A
B
BRES·
GND
+v
GND
+5
GND
·v
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3.662
(92.0 MM!
RM65-:7004N1; 4·Slot Motherboard (Rear
r ..,. "..'t
View)
.' '.219
~15.6MMI
"
.'
"
RM6S..
RM 65 Microcomputer
'1'
Rockwell
RM65-7008E AND RM65-7008NE
RM65 8-SLOT CARD CAGE
AND MOTHERBOARD
RM 65 MI.CROCOMPUTER MODULES
FEATURES
The RM65-7008E 8-Slot Card Cage .and RM65-7008NE 8-Slot
Motherboard is one of the hardware options available for the
RM 65 Microcomputer Module family.
.
• 8-slot card cage with integral module guides
• Rugged, but lightweight construction.
... Accepts axial module cooling fan
• Screw-down terminals for connecting external power (+5V,
+12V/+V, -12V/-V, GND)
RM 65 Microcomputer Module products are designed for OEM
and end user microcomputer applications requiring state-of-theart performance, compact size, modular design and low cost.
Software for RM 65 systems can be developed in R6500
Assembly Language, PLl65, BASIC and FORTH. Both BASIC
and FORTH are available in ROM and can be incorporated into
the user's system.
• Predrilled holes for various mounting configurations
• Assembled, tested and warranted
• Removable jumpers on motherboard support ±12V as well
as ±V.
ORDERING INFORMATION
RM 65 modules use a motherboard interconnect concept and
accept any card in any slot. The 64-line RM 65 Bus. offers
memory addressing up to 128K bytes, high immunity to electrical noise and includes growth provisions for user functions.
A set of card cages allows a broad variety of packaging options.
RM 65 products may also be used with ROckwell AIM 65 and
AIM 65/40 Microcomputers for product development -and desktop
microcomputer applications.
RM65-700BE
RM65~700aNE
8-Slol Card Cage
a-siot Motherboard
PRODUCT OVERVIEW
The RM65-7006E 8-slot Card Cage consists of an 8-slot RM 65
Bus compatible motherboard ih a card cage. Memory, I/O or
special functions maybe added to the AIM 65 Microcomputer
by use of the 8-slot card cage. When connected to the AIM 65
Master Module through the Buffer/Adapter Module, the card
cage may be mounted over, under, or behind the AIM 65 Master
Module in a variety of orientatiorls to meet unique application
requirements. The form factor 'of the 8-slot card cage allows low
profile placement in a table top or terminal style enclosure.
The RM65-7008NE 8-Slot Motherboard is a printed circuit board
(PCB) less eight connectors, three filter capacitors, two miniterminal strips and eight mounting blocks used to ·fasten the
PCB to the card cage. Connectors, mini-terminal strips, filter
capacitors and custom mounting blocks as needed can easily
be added to meet unique installation requirements.
RM65-7008E 8-510t Card Cage
Document No. RMA65N09
9-78
Data Sheet Order No. RM09
Rev. 3, June 1983
.S-Slot Card Cage and Motherboard
RM65-700SE. RM65-700SNE
RM 65 Bus Pin Assignments
Bottom (Solder Side)
Pin
la
2a
3a
4a
5a
6a
7a
8a
9a
lOa
lla
12a
13a
14a
15a
16a
17a
18a
19a
20a
21a
22a
23a
24a
25a
26a
27a
28a
29a
30a
31a
32a
Signal
Mnemonic
Signal Name
GND
BADRI
GND
BA13!
BAll!
BAlO!
BA6!
GND
BAS!
BAS!
BA2J
BAO!
GND
BSO
BRDY
+ 12V!+V
GND
BDMT!
BRm!
GND
BIRO!
B.0'2!
B.0'2
BD7!
GND
BD4!
BD2!
BD1!
+5V
Top (Component Side)
Pin
Ground
BufferE!d Bank Address
Ground
Buffered Address Bit 13
Buffered Address Bit 11
Buffered Address Bit 10
Buffered Address Bit 8
Ground
Buffered Address Bit 5
Buffered AddreSS Bit S
Buffered Address Bit 2
Buffered Address Bit 0
Ground
Buffered Set Overflow
Buffered Ready
User Spare 1
+12 Vde!+V
Ground Line
Buffered DMA Terminate
User Spare 3
Buffered ReadIWrite "Not"
System Spare
Ground
Buffered I nterrupt Request
Buffered Phase 2 "Not" Clock
Buffered Phase 2 Clock
Buffered Data Bit 7
Ground
Buffered Data Bit 4
Buffered Data Bit 2
Buffered Data Bit 1
+5 Vdc
le
2c
3e
4e
5c
6e
7c
8e
9c
lOe
llc
12c
lSc
14c
15c
16c
17e
18c
19c
20c
21c
22c
23c
24c
25c
26c
27c
28c
29c
SOc
31c
32c
MOTHERBOARD CONNECTION AND
MODULE INSTALLATION
Signal
Mnemonic
+5V
BA15!
BA14!
BA12!
GND
BAS!
BA7!
BA6!
BA4!
GND
BA1!
B.0'l
BSYNC
BDR01!
GND
-12V!-V
BFLT!
B.0'O
GND
BDR02!
BRNi
BACT!
BNMI!
GND
BRES!
BD6!
BD5!
BD3!
GND
BDO!
GND
Signal Name
+5 Vde
Buffered Address Bit 15
Buffered Address Bit 14
Buffered Address Bit 12
. Ground
Buffered Address Bit 9
Buffered Address Bit 7
Buffered Address Bit 6
Buffered Address Bit 4
Ground
Buffered Address Bit 1
Buffered Phase 1 Clock
Buffered Sync
Buffered DMA Request 1
Ground
-12 Vdc!-V
User Spare 2
Buffered Bus Float
Buffered External Phase 0 Clock
Ground
Buffered DMA Request 2
Buffered ReadIWrite
Buffered Bus Active
Buffered Non-Maskable Interrupt
Ground
Buffered Reset
Buffered Data Bit .6
Buffered Data Bit 5
Buffered Data Bit 3
Ground
Buffered Data Bit 0
Ground
NOTES
If both +12V and +V (e.g., +15V) are required, remove
the soldered jumper corresponding to pin17a between
receptacle 6 and 7 on the soldered side of the rnotherboard. Connect + 12Vto TBl if six or less modules require
+12V, or to TB2 if more than six modules require +12V.
Connect + V to the other termiHal strip.
Connect power to TBl and/or TB2. The power lines should be
long enoughJo allow the card cage to be oriented and positioned as required,
WARNING
The external power supplies must be turned off before
connecting to TBl or TB2.
If the jumper has been removed and only one voltage is
required (i.e., + 12V or + V), connect the power lead to
both TBl and TB2.
a, Connect +5V from an external power supply to either terminal marked "+5", "+5" is connected to all +5V pins on
all module receptacles.
d. Connect GND from the +12V/+V power supply to either "G"
terminal.
e. Connect -12V/-V from an external power supply to the terminal marked" - V". "- V" is connected to Pin 16c on each
module receptacle.
b, Connect GND from the power supply to either terminal marked
"G", Both of these terminals are connected to all GND pins
on all module receptacles,
NOTES
c, Connect.+ 12V/+ V from an external power supply to the terminal marked "+V". "+V" is connected to Pin 17a on each
module receptacle.
If both -12V and -V (e.g., -15V) are required, remove
the soldered jumper corresponding' to pin 16c between
9-79
8-Slot Card Cage aod Motherboard
flM65-700$E. RM65:-7008NE
receptacle 6 and 7 on the soldered side of the ,motherboard, Connect -12V to TBl if six or I~ssmodul.es require
-12V or to TB2 if more than.s.ix modules require -12V.
Connect -V to the other terminal strip.
CAUTION
ff ± l2V and ± V have beenconn~ted to different terminal
strips (TB1 or TB2). ensure that any modules requiring
±12Vor.±V lire ,installed in the slots corresponding to the
proper voltage.
If the Jumper has been removed and only one voltage is
required (i.e .• -12Vor -V) connect the power lead to
.
both TBl and TB2.
b. Inserrihe module into the card guide and slide the module
straight in until it touches the mating mothEirboard receptacle.
f. Connect GND from the -12V/~V power supplyto either "G"
terminal.
.
NOTE
The card sldlguides may be snug on tlie inserted module.
Install the card cage in ttle desired position. Mounting holes are
provided to allow attac~r'nent at 'the top or bottom of the card
cage.
c.
Ensur~
thaUhe module connector is positoned properly
against lhe mating receptacle.
CAUTION
Akeyis installed in each edge connector receptacle
between pin 5 and piri 6. Forcing an edge connector
module without a corresponding slot in the plug may
damage the receptacle and/or the module.
CAlITiON
Adequate cooling must be provided to keep'the temperature of the installed modules within specified operating
..
limits.
d. Pre.ss in firmly on the exposed edge of the module until it is
firmly seated.
Install a module in the card cage as follows:
Remove a module Iromthecard cage as follows:
.CAUtION
CAUTION
Power must be tumed off to the card cage motherboard
before installing a module.
Remove power from the card cage motherboard before
removing a module.
a. Position the module. component side facing TB1 end. in front
of the desired card slot.
a. Lift up on the module ejector tab. if installed; otherwise grasp
the exposed edge of the module and pull. to release the
module from the mating receptacle.
Card slot No. 1 (slot closest to TB1) has 0.85 inch of component clearance whereas the other fifteen slots are 0.6 inch
centers. If a module is higher than 0.4 inch above the surface
of the module. install it in card slot No.1.
b. Pull the module straight back until it is free from the card slot
guides.
SPECIFICATIONS
Pararneter
Value
8-Slot Card CIIge Dlrnensions
Width
Length
Height
Module Separation
Slot 1: Centerline to Inside Top Cover
Other Slots: Centerline to Centerline
4.96 in. (126 mm)
8.00 in. (203 mm)
6.40 In. (162.6 mm)
0.85 in. (22 mm)
0.6 in. (15 mrn)
Weight
1 lb. '6 oz. (624 g)
8-Slot Motherboard Dirnenslons
Width
Length
Height
3.938 in. (100 mm)
5.725 in. (145 mm)
0.062 in. (1.6 mm)
Hole Size
Uncoded
A
0.037 in. (0.940 mm) dia
0.044 in. (1.12 mm) dia
0.128 in. (3.25 mm) dia
B
9-80
S-Slot Card Cage and Mbtherboard
RM65-7008Ee RM65-700SNE
7.25 REF
(184.2 MMI
6.50
(165.1 MM)
(()\
.75
(19.1 MI\iI)-
:---
/Q'
V
I
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I
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-
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10000000000000000°,.00000000000 00000000 A
-+
'-
I
I
-
-----+
~i~~4
2.800
171.1 MMI
1.600
400
,(10.2 MMI
j--"t-
140.6 MMI
.500
112.7 MMI
.
JoooooooooooooooooooooooooooooooooooolC
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~~-------------~:BMMI--------------~~
RM65-700SNE S-Slot Motherboard (Rear View)
9-82
MMI
RM~7016
RM 65 Microcompur.r Family
'l~
Rockwell
RM65-7016E ANO RM65...7016NE
RM 65 1s...SLOT CARD CAGE
AND MOTHERBOARD
RM 65 MICROCOMPUTER MODULES
FEATURES
The RM65-7016E 16-Slot Card Cage and RM65-7016NE Moth~
erboard are one of the hardware options available for the RM
65 MicrocompUter Module family.
• 16-slot card cage with integral module guides
• Rugged, yet lightweight construction '
• Screw-down ierminals for oonnecting external power (.+5V,
+12V/+V, -12V/-V, GND)
RM 65 Microcomputer Modules products are designed for OEM
and end user microcomputer applications -requiring state-of-theart performance, compact size" modular desi!!n and low cost.
Software for RM 65 systems can be developed in R6500
Assembly Language, PlI65, BASIC and FORTH. Both BASIC
and FORTH are available in ROM and can be incorporated into
the user's system.
• Predrilled holes for various mounting configurations
• Assembled, tested and warranted
• Removable jumPers on motherboard support ± 12V as well
as ± V.
ORDERING INFORMATION
_RM 65 modules 'use a motherboard interconnect concept and
-accept any card in any slot. The 54-line RM 65 Bus offers
memory addressing up to 128~ bytes, high immunity to electrical noise and includes growth provisions for user functions.
A set of card cages .allows a broad variety of packaging options. ,
RM 65 products may also be uSed with Rockwell AIM65 and
AIM 65/40 Microcomputers for product development and desktop
microcomputer applications.
Description
Part No.
RM65-7016E
RM65-7016NE
16-Slot Card Cage
16-Slot Motherboard
PRODUCT OVERVIEW
The RM65-7016E 16-slotcard cage consists 6f a 16-slot RM 65
Bus compatible motherboard in a card cage. Memory, I/O or
special functions may be added to the AIM 65 Microcomputer
by use of t~ 16-slot card cage. When connected to the AIM 65
Master Module through the Adapter/Buffer, the card cage may
be mounted over, under, or behind the AIM 65 Master Module
in a variety of orientations to meet unique applic;ationrequirements. The form factor of the 16-slot card cage allows low profile
placement in a table top or terminal style enclosure.
The AM65-7016NE 16,Slot Motherboard is a printed circuit
board (PCB) less 16 connectors, two mini-terminal strips, three
fiHer capacitors and 16 mounting blocks used to fasten the PCB
to the RM65-t016E card cage. Connectors, mini,terminal strips,
filter capacitors, and custom mounting blocks as' needed can
easily be added to meet unique Installation requirements.
FlM65-7016E 16-SIot Card
Document No. RMA65N18
9-83
cage
Data Sheet Order No. RM18
Rev. 2, June 1983
RM65~7016E • RM65-7016NE
16-Slot Card Cage and Motherboard
RM 65 Bus Pin Assignments
, ,
Bottom (Soider Side)
Pin
"
la
;!a
3a .
4a
Sa
6a
7a
8a
9a
lOa
lla
12a
13a
14a
15a
16a
17a '
18<1
19a
20a
21a
22a
.23a
24a
25a
26a
27a
2Ba
29a
30a
31a
32a
Signal'
Mnemonic
GND
BADRI
GND
BAI3/
BAil!
BAIOI
BASI
GND
BAS/,
BA31
BA2/
SAOI
GND
SSO
BRDY
+12V/+V
GND
BDMTI
BRiWI
GNO'
BIRQI
~2/
B~2
BD71
GND
BD41
BD2/
BOil
+5V
Top (Component Side)
Signal Name
Signal
Mnemonic
Pin
I'e
2e
3e
4c
5e
6e
7e
Be
90
10e
lie
12e
13c
14c
15e
ISc
17c
1&
Ground
Buffered Bank Address
Ground.
Buffered Address Bit 13
Buffered Address Bit 11
Bulfered Address Bit 10
Buffered Address Bit S '
Ground
Buffered Address Bit 5
Bulfered Address Bit 3
Buffered Address Bit 2
Buffered Address Bit 0
Ground
Buffered 'Set Overflow
Buffered Ready
User Spare I
+12Vde/+V
'Ground UOO
Buffered DMA Terminate
User Spare 3
,
'Buffered Read/Write "Not"
System Spal'Ei'
Ground
Buffered Interrupt'Request
Bulfered Pl)ase 2 .. N~t" Clock
BUffered Phase 2 Clock
' Buffere,d Data Bit 7
Ground
Buffered Data Bit 4
Buffered Data Bit 2
Buffered Data Bit 1
+5 Vdc
.'
+5V
BAI5/
BA14/
B.o\I2/
GND
BA91
BA71
BASI
BA41
,GND
BAil
B¢I
BSYNC
BDRall
GND
-12vr~V
tge
20c
21c
22c.
230
24c
250
2Sc
27c
26c
290
30c
31c
32c
BFLTf
B;o
GND
BDRQ21
BRiW
BACTI
BNMII
GND
BRESI
BDSI
BD51
BD31
GND
BDOI
GND
,
,
Signal iII,ame ..
+5 Vde
BuffE\red Addre$S Bit 15
Buffered Address Bit 14
Buffered Address Bit 12
Ground
Buffered Address Bit 9
Buffered Address Bit 7 .
Buffered Address Sit S
Bulfered Address Bit 4
Ground
Buffered Address Bit 1
Buffered Phase 1 Clock
Buffered Syno.
BuffE\red DMA RequeSt I
Ground
-12 Vdc/-V
User Spare 2
. BiJffered Sus Float
Buffered External Phase 0 Clock
Ground
Buffered DMA Request 2
' l3uffer¢ Read/Wtite '-Bulfered Bus Active
Buffered Non;Maskable Interrupt
Ground
Buffered ReSet
Bllffered Dafa Bit 6
Buffered Data Bit 5
Buffered Data Bit 3
Ground
Buffered Data Bit 0
Ground
"
NOTES
MOTHEReaARDCONN'ECTION AND
MODULE INSTALLATION
'.
1. If both +12Varid +V(e.g" +15V) are required,remove
the soldered jumpercerresponding to pin 17a between
receptacle 3 and 4 on'the soldered side of the motherboard. Connect +12V to TBl ifthree or less modules require + 12V, or to TB2 if more than three modules
require +12V, Connect + V to the ether terminal strip.
Cenneclpqwer'tqTBl and/erTB2, Thl'!. pewer I,ines shduld be
leng enough to aUpw thl'! card cage to be' oriented and posirequired:
'
.
tiened
as
WARNING ..
The external power supplies must be turned .off befere
connecting to TB1 or TB2,
2. If the jumper has been removed and only one veltage
is required (Le., +12V or -tV), connect the pewer lead
te beth TB 1 and TB2, .
a, Cennect +5V frem an external pewer supply to either terminal marked "+5". "+5" is connected to all +5V pins on
all module receptaclEls.
d: Connect GND frem the +12V/+V power supply to either "G"
terminal'.
e, Conneot -12V/-V from an external power supply to the terminal marked "-V". "-V" is connected to Pin 160 on each
module receptacle.
b. Connect GND from the power supply to either terminal marked
"G". Both of these terminals are conneoted to all GND pins
on all module receptacles,
NOTES
c. Connect + 12V/ + V from an external power supply te the te,rminal marked "+V", "+V" is connected to Pin 17a on each
module receptacle.
1, If both -12V and - V (e,g" -15V) are required, remove
the soldered jumper corresponding to pin 16c between
9-84
RM65-7016E •.RM65-7016NE
receptacle 3 and 4 on the soldered side of the motherboard. Connect -12V to Ta1 if three or less modules require -12Vor to Ta2 if more than three modules
require -12V. Connect - V to the other terminal strip.
CAUTION
If ± 12V and ± V have been connected to different terminal
strips (Tal or Ta2), ensure that any modules requiring
± 12V or ± V are installed in the slots corresponding to the
proper voltage.
2. If the .jumper has been removed and only one voltage
is requi~ad (i.e., -12V or -V) connect the power leaet
to both Ta1 and Ta2.
b. Insert the module into .thecard guide and slide the module
straight in until. it touches the mating motherboard receptacle.
f. Connect GND from the -12vt- V power supply to either "G"
terminal.
.
NOTE
The card slot guides may be I$nllg on the inserted module.
Install the card cage in the desired position. MOUnting holes are
provided to allow attachment at the top or bottom of the card
cage.
c. Ensure'that the module. connector is positioned properly
against th~ mating. receptacle.
CAUTION
A key is installed in each edge connector receptacle
between pin 5 and pin 6. Forcing an edge connector
module without a corresponding slot in the plug may
damage the. receptacle and/or the module:
CAUTION
Ensure that neither the left nor right side of the card cage
is blocked such that the flow of forced cooling air is
impeded.
d.Press in firmly on the exposed edge of the module until it is
firmly seated.
Install a module in the card cage as follows:
Remove a module from' the card cage iilS follows:
CAUTION
CAUTION
Ensure that power is turned off to the card cage motherboard before installing a module.
Remove power frO.rn the card cage motherboard before
removing a module.
a. Positiontha module, component side facing Ta1 end, in front
of the desirea C!ilrd slot.
a. Lift up on the module ejector tab, if installed; otherwise grasp
the exposed edge of the module and pull, to release the
module from the miilting receptacle.
Card slot No. 1. (slot closest to Ta1) ha~ 0.&5 inch of component clearl;lnce whereas the other.s~n slots are 0.6 inch
centers. If a rTlottule Is higher than 0.4 inch.abdve the surface
'of the mOdule, install it in card slot No.1.
SPECIFICATIONS
.,
Characta~istlc
I
b. Pull the module, straight bac~ until it is free from the card slot
guides.
ValUe
..
RM65-7016E Card Cage Dimensions
Width
Length
HeIght
4.96 in. (126 mm)
8.00 in. (203 mm)
11.20 in. (285mm)
Weight
2 lb. 10 oz.,(l.20kg)
Module Separation:
Slot 1 : Centerline to Inside Top Cover
Other Slots: Centerline to Centerline
0.B5 in. (22 mm)
0.6 in. (15 mm)
RM65-7016NE M!)therboard Dlmenslc)ns
Width
Length
Height
Hole Size
Uneoded
A
B
3.938 in. (100 mm)
1.0.525 in. (267 mm)
0.062 in. (1.6 mm)
.
'
0.037 in. (0:940mmldia.
0.0# in. (1.12 mm) dia.
0.1211 in. (3.25rnm)dia.
\
''''
16-510t Card Cage and Motherboard
AM6s.;;7016E • AM65-1016NE
1'04_ _ _--'_ _ 7.211 ReF
1184.2MMI
1-------~;:.1 M M I - - - - - -ool
INSTALL MODULES FROM
. THIS END
3.i58 REF
4PLACES
.18aDIA
197.8~r.\l
. lUMMI
o
1.108
128.1MMI
~·~--,------,------~----~--~o
TOPV(EW
'.88
~.".
I128MMI..
.
{-----~:3.2MMI----~---i
,
.85
121.6MMI
0.2
15MMI
,...- -...,
~ TB1 ..J
0.8
I1UMMI
TVP7PLACES
11.20
1285MMI
LEFT SIDE VIEW
END VIEW
16-810t Card Cage and Motherboard
9-86
16-810. Card Cage and ",otherboard
RMes.7016E. R.M65-7016NE
16-CONNECTOR MOTHERBOARD
ASSEMBLY
b. Solder the receptacle pin eonneOtioris to the baclf.of the
PCB.
The RM65·7016NE 16·slot motherboard can be assembled as'
follows:
a. The fonowing connectors or their equivalent, may be used:
d. Solder the capacitor leads to the back oHhe -PCI:I'
Manufactu.....
Bumdy Corporation
Norwalk, CT 06856 "
Winchester Eiectronlcs
OalR~~~~~~=~~~~~!,:!e~~~=~~.~~~~~N~X~
1 OOOO,!OOOOOOOOOOOOOOOOOOOOOOOOOO ooo~o
c
000000000000000000000000000000000000 A
...
-
-
I
. . . . --~---+
I oooooooo,oo~ooo 00000000000000 000 00000
C
i 000000000000000000000000000000000000 A
I
.
l
'
c. Install three 100 ufd, 25 VDC¢'8paclforsf"om +5V toGNQ,.
+V to GND, and -V to GND,.ftom the frortt'ofthe PCB:.8&:
sure to observe correct polarity.
..
.
Install up to 16 module connectors (receptacles) from the front
of the PCB. Be sure to observe correct connector orientation.
Pari No.
" . , :.
.
'
00000000 000000000000 000000 00000
.I.
000001·.
10000000000,00000000000000000000000000 A
-"'''noo 000 OOOOOOOO.()OO 00'0 00000
~
....... 1'\0000000000 A
8.800
10.521
'28... MM,
16-SlotMotherboard (Rear View)
9·87
RM65-7101E
RM65 Microcomputer Family
'1'
Rockwell
RM65-7101E
RM .65 SINGLE CARD ADAPTER FOR AIM 65
RM 65 MICROCOMPUTER MODULES
FEATURES
The RM65-7101 E Single Card Adapter for the AIM 65 Microcomputer is one of the hardware options available for the RM
65 Microcomputer Module family.
.'
•
•
•
•
•
RM 65 Microcomputer Module products are designed for OEM
and end user microcomputer applications requiring state-of-theart performance, compact size,modular design and. low cost.
Software for RM 65 systems can be developed in R6500
Assembly Language, PL/65, BASIC and FORTH. Both BASIC
and FORTH are available in ROM and can be incorporated into
the user's system.
RM 65 module products use a motherboard interconnect concept and accept any card in any slot. The 64-line RM 65 Bus
offers memory addreSSing up to 12l1K bytes, high immun~ to
electrical noise and includes growth provisions for user fUnctions. A selection of'card cages prpliides packaging flexibility.
RM 65 products may'also be used with Rockwell AIM 65 and
AIM 65140 MicroComputers for product development and for a
broad variety 01 portable or desktop microcomputer applications.
ORDERING INFORMATION
Part No.
RM65-7101E
Drives one RM 65 Bus..compatible module ..
Provision for power· and ground routing
Extends address, data and control lines
Pin .and socket bus connector
Fully assembled, tested and warranted
PRODUCT OVERVIEW
The RM65-7101 E Single-Card Adapter allows one RM 65 Bus
compatible module to be connected to the AIM 65 Master
Module, through the AIM 65 Expansion connector. The Adapter
routes the AIM 65 address, data and control lines from the AIM
65 Expansion connector pin aSSignments to the RM 65 Bus pin
assignments. Drive circuitry is included on the address and data
lines.
RM65-7101E Single Card Adapter for AIM 65
Document No. RMA65N03
Data Sheet Order No. RM03
Rev. 2, June 1983
RM65~7101E
Single Card, Adapt~r 'for AIM 65
FUNCTIONAL DESCRIPTION
EXTERNAL +5VPOWER SOURCE CONNECTION
The Single Card Adapter interfaces AIIVI 65 Expansion Connector signals to an attached RM 65 Bus receptacll;!, De,ta and
address 'lines are buffered, whereas control iinel\are directly
wired. All signals are routed from the AIM 65 ExPansion Connector posHions to corresponding RM 65 Bus receptacle pin
positions. Ground is cOnnected to the interspersed RM 65 Bus
GND pins.
a. Install Jumper·AlB in the B position.
b. Connect the +5V lead from the external power supply to the
+5V connection on TB1.
c. Connect the ground lead from the external +5V power supply
to either of the two GND connections on TB1.
The Data Transceivers invert arid drive B-bits 01 parallel data
between the AIM 65 Expansion Connector and the RM65 Bus
interface. During a write operation, data received from the AIM
65 Expansion Connector are driven into the interlacing RM 65
module. During a read operation, data read from the RM 65
module are' transmitted into the AIM 65. When, the RM 65
module is not addressed, the transceivers are,disabled.
±12V/±V POWER CONNECTION
Connection points are proVided on TBl for ± 12 Vdc, or other
voltages, as required by the mating RM 65 module.
a. Connect the +12V/+V lead from the external power supply
to the TB1 connection marked +15V or +V. This terminal
is connected to connector Jl pin 17a.
The Address Buffers invert and buffer 16 parallel address bits
from the AIM 65 to the connected RM65 module.' The bank
address line is held high to address.Bank 0 (lower 65K) in the
interfacing RM 65 module.
b. Connect the -12V/- V lead from the external power supply
to the TBl connection marked -15V or -V. This terminal
is connected to connector J1 pin 16c.
Eleven control and timing signals are directly connected between
the AIM 65 Expansion Connector and the RM 65 module., The
read/write, phase 2 clock, phase 1 clock, sync and reset AIM
65 output lines are routed directly to the RM 65 receptacle. The
ready, interrupt request,set overflow and non-maskable interrupt lines from the RM 65 receptacle are connected straight
through to the AIM 65,Expansion Connector interface.
INSTALLATION
Before installing the module, inspect for damage and grease,
dirt, liquid or other foreign material tllat will affect performance.
CAUTION
A terminal block allows external +5V, + 12V/ + V, and -1'2V/- V
power supplies to be connected as required. An on-board jumper
allows the +5V for the RM 65 module to originate from the AIM
65 Expansion 'Connector or from the external +5V Power supply.
Prior to module installation, turn off power to the AIM 65
and, if applicable. the optional external +5Vand/or ±12V/
±V power supply input to the Mapter.
a. Align pin 1 of J3 on theSCA wjth pin 1 onhe Expansion
Connector on the AIM 65 Maste'r Module (component side,
POWER CONNECTION
•
u~.
+5 VOLT POWER CONNECTION,
b. Carefully insert the Adapter into the Expansion Connector.
The +5 volt>( +5V) required for the Single Card Adapter cari be
provided from the AIM 65 microcomputer through the AIM 65
Expansion Connector or directly from an external power sIJPply
through a connection to the 'on-board terminl!il board (TB1).
,Jumper AlB routes the +5V power from the selected ~urce.
c. Press in firmly until all'pins are securely seated.
d. Install the RM 65 module into the J1 connector on the
Adapter using installation procedures i:tescribed in Ihe dOCumentation fo,r,the particular m,O,d"UI,e. Ensure, t, hatBank Se, lect
switches on Ihe add-on module are positioned to Bank Select
or Bank Select Disable, as appropriate. ,
CAUTION
o
Turn off the external power supply ,before connecting
'
power leads to the Single Card Adapter.
,
"'/:
"
l
'
e. Turn on power to the AIM 65 and, if applicable, turn on
'
extemal +5 Vde and/or ±12V/;tVto the seA mOdule.
AIM 65 +5V POWER SOURCE CONNECTION
a. Install Jumper AlB. i(l the A posHion.
REMOVAL
b. Disconnect the +5V lead of the external power supply from
the +5V connection on TB1.
a.Turn off power to the AIM 65 lind if applicable,
±12V/±V power supplies.
WARNING
to the external
b. Pull the Adapter straight bac~ while moVing'Jt slightly from
side to Side to disconnect it from the AIM 65 Expansion
Connector.
If the mating RM 65 module draws over O.5A, the extemal
connection to +5V must be used, or the AIM 65 Master
Module may be damaged.
'
9-89
9'
Single Card Adapter for AIM 65
RM65-7101E
c
CONNECT To
RM 65 BUS
RECEPTACLE
CONNECT TO J',tM 65
EXPANSION CONNECTOR.
-
J3
, DATA
r
•
~
'
TIMING
AND
CONTROL
I
'
,I
BUS ACTIVE
I
'7
TIMING
AND
CONTROL
4
I
-I
ADI)RESS
BUFFERS
I
16. '
ADDRESS
I
BANK ADDREs'C;;
I
I
GND
.,v
DATA
TRANSCEIVEI;tS'
DATA
1~
ADDRess
J1
r-'-
~--,
A
,
.
GND'
,v
B'
"
.....
I
.'v
+12V/+V
I
OND
'V
OND
i
I
-
12V/-V
Single Card Adapter BloekDiagram
RM 65 Bus Pin Assignments
Bottom'(Solder Side)
Pin
la
2a
3a
4a
Sa
6a
7a
8a
9a
lOa
lla
12a
13a
14a
15a
16a
17a
18a
19a
20a
21a
22a
23a
24a
25a
26a
27a
28a
29a
30a
31a
32a
Signal
Mnemonic
GND
BADRI
GND
BAl3/
BAlli
BAlOl
Signal Name
Ground
Buffered Bank Address
Groand
Buffered Address Bit 13
Buffered ,Address Bit 11
Buffered Address Bit 10
Buffered Address Bit 8
BA,BI
GND
Ground
Buffered Address Bit 5
BASI
Buffered 'Address Bit 3
BA3I
Buffered Address Bit 2
BA2/
Buffered Address Bit 0
a'AOI
GND
Ground
Buffered Set Overflow
BSO
BRoy
Buffered Ready
'User Spare 1
+12VI'tV
+12 VdC/+V
GNo
Ground Una
BoMTI
'Buffered DMA Terminate
.
'l,Jser Spare 3
.. B,uffered Read/Write "Not"
'System Spare
GNo
Ground
Buffered Interrupt Request
BIROI
Buffered Phase 2 "Not" Clock,
B;2/
Buffered Phase 2 Clock
.
B;2
B071
Buffered Data Bit 7
Ground
GNo
Buffered Data Bit 4
BD4/
Buffered Data Bit 2
Bo2/
BOll
B~ffered Data Bit I
+SV
+5 Vdc
Top (Component Side)
1/0
Pin
o
Ie
2e
3e
o
o
o
o
4c
5e
6c
7e
8e
.0
ge
10e
o
o
o
l1e
Signal
Mnemonic
+5V
+5 We,
BA1SI
BA141
BAl2/
GNo
BA91
BA71
BA6I
BA4/
GNo
BAli
Buffered
Buffered
Buffered
Grourid
Buffered
Buffered
Buffered
Buffered
Ground'
Buffered
Buffered
Buffered
'Buffered
Ground
12e
B~l
13c
14c
15c
BSYNC
BoROII
GNo
-12V/-V
16e
17e
o
18c
BFLTI
1ge
20e
21e
22e
GNo
BDRQ2/
I
23c
24c
VO
25e
26e
27e
o
o
1/0
28c
29c
30e
VO
31e
VO
32c
Note:
'Not used on this module.
9-90
990
BA/W
BACTI
BNMII
GNo
BRES!
BD6I
BoSi
BD3I
GND
BoOI
GNo
Signal Name
1/0
Address Bit 15
Address Bit 14
Address Bit 12
o
o
o
Address'Bit
Address Bit
Address Bit
Addniss Bit
9
7
6
4
Address Bit 1
Phase I Clock
Sync
oMA Request I
o
o
o
o
o
o
o
-12 VdC/-V
'User Spare 2
'Buffered Bus Float
'Buffered Extemal Phase 0 Clock
Ground
'Buffered DMA Request 2
Buffered Read/Write
Buffered Bus Active
Buffered Non-MaSkable Interrupt
Ground
Buffered Reset
Buffered Data Bit 6
Buffered Data Bit 5
Buffered Data Bit 3
Ground
Buffered Data Bit 0
Ground,
o
I
I
o
1/0
1/0
VO
lio
"M65';' 7101 E
Single Card Adapter for AIM 65
"
SINGLE CARD ADAPTER SCHEMATIC
J§
CE!!!!
fUM
15
14
13
IZ
/I
10
9
B
JI
7 fSV
Ri!3 a,K}C7
A.JI.'LJ1A_.E~lJ
1-
44PI/.I
:"
~ "c
oo
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I~
87 Ie
8IJ II
rI
W:
€/.IG 19
f,:V
/jD~-
29a.
BDSBXBD713/1Cr-
ZBe
at
Z7d'
C3c
~~~
fO
AD
- I
II
9
t::SV6B ,qo_
~ ~LII~I~ _ _ _~+-+-~~~-- -+-+--~8~~;;~~~'/LZ-----~B~fi~/_-~;;;
C
RZ
13 c/lt:
o
113
dl
1113
E
F
H
J
//4
//5
IS
4
17
~
ZII3
//&;
1i7
lUI ZZK x 7
+SY
1- - - - - - - - . : l
I
1
I
k
L
M
N
p
li!
Ille
;!/I 1113
1911"
1113
I~ e/l3
rL
,_~ I/li?
oS 1-!211~~~_ _ _ _ _ _ __l----+_--1~7~i?/I4
T
BRZ8R:3BI'MDRSBRd'r
8/17-
1111
,L 16
-+
7
l-f
U3"
I YZ I({,
ZYZ
r3 Iv3
~-"R."'~5"--------~----~---'Z'_I//I1
,-L 16
B¢Z-
"p.
74t.:010
Ie
8//"·.i.e
[YlI(J-
.,,,
Sa
CY3 5
5'1911O//I.?-
I Vi! Ill>
BRI3'
.."
IY$ 14
ZY~3
IYI 18
X~, Y4,Yt!,
/C/~Za.
01./ lLS. COAlN€CTtJlI SHIILL BErKO TO ,cS"Y.
9-91
®
fi5'v
17d.
-
m
Single Card Adapter for AIM 65
RM65-7101E
AIM 65 Expansion Connector Pin Assignments
,
Top (component Side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Signal
Mnemonic
SYNC
RDY
~1
IRQ
S.O.
WI
RES
D7
DS
D5
D4
D3
D2
Dl
DO
-12V
+12V
em!
~
C§A,
+5V
GND
Signal Name
Sync
Ready
Phase 1 Clock
,Interrupt Request
Set Overflow
Non-Maskable Interrupt
Reset
Data Bit 7
Data BitS
Data B~'5
Data Bit 4
Data Bit 3 '
Data Bit 2
Data Bit 1
DataElit 0
'-12Vdc
'+12 Vdc
'Chip Select 8,
'Chip Select 9
Chip Select A
+5 Vdc
Ground
B!)ttom (Solder Side)
'Illput!
Output
Pin
I
0
I
0
0
0
I
,VO
A,
B
C
D
,E
AO
Al
A2
A3
F
,H
A5
A6"
A7
A8
A9
Al0
All
A12
A13
A14
A15
A4
J
K
L
M
N'
P
R
S
'T
U
V
VO
VO
vb
1/0
I/O
VO
I/O
.
Signal
Mnemonic
SYS~2
S~R/W
Vj
Fl/W
*TEST
X
,~
'Y
,Z
I
'RAM
R/W
Signal Name
Address Bit 0
Address Bit 1
Address Bit 2
Address, Bit 3
AddreSS Bit 4
Address Bit 5
Address Bit. 6
Address Bit 7
Aqdress Brt 8
Address Bit 9
Address Bit 10
Address Bit 11
Address Bit 12,
Address Bit 13
Address Bit14
Address Bit 15
System Phase 2 Clock
System Read/Write,
ReadlWrite "Not"
Test
Phase 2 Clock "Not"
flAM Read/Write
Note:
'Not used on this module,
MATES WITH
RM6S
MODULE
EDGE
L'\'
T
HEIGHT
Module Dimensions
9-92
EUROCARD
RECEPTACLE
COMPONENT
AREA
---~--
L...d:!:========r
Input!
Output
I
Single Card Ad~pter for AIM 65
RM65-7101E'
SPECIFICATIONS
Pl!"ameter
Value
Dimensions (1', 2; 3)
Width
Length
Height
Weight
4.4 in..(111 mm)
3.7 in. (93 mm)
0.56 in, (14 mm)
3.00z. (90 g)
Environment
Operating Temperature
Storage Temperature
Relative Humidity
Power
O"Cto 70"C
-4O"C to +85'C
0% to 85% (without condensation)
+5V ± 5% 110 mA (0.55W)-Typical
200 mA (1.00WI-Maximum
Interface
AIM 65 Expansion Connector
RM65 Bus
22144-edge receptacle (0.156 in. centers)
64-pin receptacle (0.1·00 centers) per DIN 41612 (Row b is not installed)
Notes:
1. Height includes the maximum values for.component height above the board surface (0.4 in. for populated modules), printed circuit board
thickness (0.062 in.), and pin extension through the bottom of the module (0.1 in.),
2. Length does not include extensions beyond the' edge of the module due to connectors.
3. Dimensions conform to DIN 41612.
9·93
"
AM65~71.02E
RM 65 MlcroCqmputer F.""iy
'1'
Rockwell
'"
RM65·7102E, .
RM 65 IEEE·488 BUS INTERFACE MODULE
'RM 65 MICROCOMPUTER MODULES
ORDERING INFORMATION
The RMes·7102E IEEE·48 Bus Interface MOdule Is one of the
hardware options available for the RM 85 MlcroCcimputer Module
Part No.
faml~.
RM65,7102E
RM 65 MICrocomputer Module products are designed lor OEM '
and en~ user mlc~9IT1puterappllc:~lons req!.lirjngst~ts.:of.the· '
art ~rformance, compact size, modular, design and low cost.
Software for RM 65 systema can be:, developed, in 865QO
Assembly Language, ,PLJ85, BASIC and·FORTH. SoU'! BASIC
.ana FORTH are available In FlOM and oan be inoorporated Into
the, user's s y s t e m . . ,
RM 65 modules use a motherboard Interconnect concept and
accept any card In any slot. The 64-l!neRM 85 BUI! offers
memory addre,sslng up to 1,28K .bytes, high Imm~nlty to,electrical noise: and Includes groWth provisions for user funotions.
A seleCtion of ca~ cages provides packaging flexibility. RM 65
produCts may also be used with Rockwell' AIM 65 and AIM
65/40 Microcomputers lor product develoPlTlent and lor a broad
variety ClI POrtSble or desktop microcomputer applications.
Order No.
PRODUCT OVERVIEW
The RM 65 IEEE-488 Bus Interface Module connects an AIM
65, AIM 65/40 or RM 65 SBC based system to the IEEE-488
General PurpOse Interface Bus (GPIB). Complete controller,
talker and listener functions, as defined in the IEEE-488, 1978
Stand~, are implemented. The module also supports extended
addressing and multiple bus controllers. On-board ROM firmware implements all 12 functions specified by the interface standard. Features not defined in the standard, but also supported,
include manue:! talk or listen disable, dual primary addressing,
and an external, trigger line., Switches select the Device Talk/
Listen Address, Enable Dual Primary Addressing Mode, Disable
Talk, Disable Listen, and System Controller mode. The bus
interface transceivers meet the electrical speCifications of the
IEEE·488 interface standard. An 8-inch ribbon cable mates the
IEEE-488 module to the IEEE·488 bus with a standard 24-pin
connector.
815
DelCrlptlon
IEEE·488 8us Interface Module, ..
DlICrlptlon
IEEE-488 Bus Interface Module User's Manual
(Included with RM85-7102E)
FEATURES
• Compact size-ab9ut 4" x 6W' (100 mmx 160 mm)
• Pin and SO¢ketbus connecflon"
..
• RM 85 ,Bus compatible' .
,
• 'Bufferedaddres$, data and coritrol lines'
• Listen, talk, ,and controller functions
• IEEE·488., 1978 ~dard fully Implemented
• Uses TI 9914 GPIBAdapter device,
• ,On-board ROM contains bus protOCOl and utility firmware
• Swkches for
-DeVice Talk/Listen Address
-Disable Talk
-Disable Listen
-Enable Dual Primary Addressing mode
-System Controller
-Base Address to page boundary lor VO
-Bank Selection to one or both 65K banks
• Jumper for ROM enable/disable
• LEOs show current address register contents
• Supports DMA data transfers
• +5V operation
• Fully assembled, tested and warranted
RM65-7102E IEEE·488 BUs Interface Module
Document No. RMA65N13
9-94
Data Sheet Order No. RM13
Rev. 2, June 1983
RM65-7102E
IEEE-488 .Bu$ Interface Module
FUNCTIONAL DESCRIPTION
The Address Buffers invert and transfer the 16-bit parallel
address lines from the RM 65 bus to the Base Address Decoders,
to the R2332 ROM and to the GPIB Adapter.
The TMS 9914 GPIB Adapter device provides hardware.cOntrol
of the IEEE-488 bus interface, using firmware subroutines provided In ROM. All bus interface lines are buffered by the GPIB
Data and Control Transceivers, to conform to the electrical
specifications of the IEEE-488 Standard. These lines are brought
out through a cable to a standard IEEE-488 connector. An
additional connector provides an external trigger output not
defined by the IEEE-488 Standard.
The Control Buffers invert and transfer phase 2 clock, reset, and
read/write control signals from the RM 65 bus onto the module.
The Interrupt request is buffered and driven onto the RM 65 bus.
The System Controller Select circuit allows manual selection
of System Controller capabilities in multiple controller configurations.
The Bank Select Control circuit detects when the module's
assigned memory bank is addressed by comparing the bank
address Signal/rom the RM 65 bus to the Bank Select and Bank
Select Enable swHches. The Bank Select Enable switch allows
the board to reside In common memory (both Bank 0 and Bank
1) or only in the Bank set by the Bank Select switch (either Bank
OorBank1).
The GPIB Sense Buffer allows the GPIB Sense Switches to be
read for Device Talk/Listen Address, Talk or Listen Disable, and
Dual Primary Address Mode selection. The. GPIB Status latch
latches the positions of the GPIB Sense Switches and displays
them on the GPIB Status Indicators. This allows a visual verification of the. Device Talk/Listen Address and Operating modes.
The Data Transceivers Invert and transfer 8-bits of parallel data
between the IEEE-488 Bus Interface Module and the RM 65
bus, based on data· direction signals from the Base Address
Decoder.
ON·BOARD PROGRAM ROM FIRMWARE
The DMA Control circuit allows DMA requests from the TI9914
GPIB Adapter device to be driven on the RM 65 bus or disabled
under program control. This line is jumper selectable for either
of two DMA request lines on the RM 65 bus.
The Program ROM firmware completeiy supports all 12 Bus
functions described In the IEEE-488, 1978 Standard, as well as
features of the TMS 9914 GPIB Adapter device not defined in
the Siandard. These utility functions make both the Bus protocol
and the GPIB Adapter device transparent to the programmer.
ThE! firmware, organized as subroutines, is linked to the user
program through a jump table. Many of these routines are interrupt-driven, to minimize the processor time In servicing the
module. User-alterable vectors and parameters are located in
RAM, to allow custom applications. Output data or commands
for the Bus are handled as tables, easing the set:up·and transfer
of information. Extensive error checking by the utility subroutines allow resident or user-provided error handling routines to
ens·ure proper Operation of the module, the.IEEE-488 Bus and
status of data transfer. Two self-test routines verify proper
module operation.
The Base Address Decoder compares the eight most signifiqant
address lines to the eight Base Address switches. The ROM
Disable jumper allows the module to be active in a 4K block
when enabled or active in a page (256 locations) when disabled.
When an address for the selected bank matches the four most
significant switches and the ROM is enabled, the Data Transceivers are enabled and the bus active signal is generated.
When this address also matches· the four least significant
switches the GPIB Adapter and I/O are selected. When there
is no match on the four least significant switches, the ROM is
selected. When the GPIB Adapter and I/O are selected, the four
least significant address lines, phase 2 clocks, and read/write
control lines are used to derive register selects for the GPIB
Adapter, device selects for the GPIB Status Latch, GPIB Sense
Buffers, System Controller Select, and DMA Control Circuits.
The read/write control lines also determine the direction for the
Data Transceivers.
The firmware is compatible with the inpuVoutput functions in the
AIM 65 Debug Monitor and the AIM 65/40 VO ROM.
9-95
RM65-7102E
IEEE-488 Bus Interface Module
DATA
HANDSHAKE
AND
CONTROL
IEEE-488
BUS
CONfIIEC;TOR
TIMING
AND
CONTROL
BANK
ADDRESS
OMA R'eQUEST
IEEE-488 Bus Interface Module Block Diagram
IEEE-488 Bus Interface Module
RM65-7102E
IEEE-488 Bus Interface connector Pin Assignments
Pin
Signal
Mnemonic
1
2
3
4
5
6
7
8
9
10
11
12
0101
0102
0103
0104
EOI
DAV
NRFD
NOAC
IFC
SRQ
ATN
SHIELD
Input!
Output
Signal Name
Pin
1/0
1/0
1/0
Data Inpul/Output 1
Data Inpul/Output 2
Data Inpul/Output 3
Oatalnpul/Output 4
End or Identify
Data Available
Not Ready for Oata
Not Data Accepted
Interface Clear
Service Request
Attention
Ground
Signal
Mnemonic
13
14
15
16
17
18
19
20
21
22
23
24
VO
VO
1/0
VO
VO
VO
VO
1/0
NlA
Input!
Output
Signal Name
Data Inpul/Output
Data Inpul/Output
Data Inpul/Output
Data Input/Output
Remote Enable
Ground
Ground
Ground
Ground
Ground
Ground
Logic Ground
0105
0106
0107
0108
REN
GND
GNO
GND
GND
GND
GND
GND
5
6
7
8
VO
VO
VO
1/0
110
N/A
N/A
N!A
N/A
N/A
N/A
N/A
External Trigger Pin Assignments
Pin
Signal Mnemonic
1
2
TRIG
GND
Input!Output
Signal Name
0
Trigger Out
Ground
RM 65 Bus Pin Assignments
Top (Component Side)
Bottom (Solder Side)
Pin
la
2a
3a
4a
5a
6a
7a
8a
9a
lOa
l1a
12a
13a
14a
15a
16a
17a
18a
19a
20a
21a
22a
23a
24a
25a
26a
27a
28a
29a
30a
31a
32a
Signal
Mnemonic
GND
BADFI/
GND
BA131
BA11/
BAIOI
BASI
GNO
BASI
BA3I
BA2/
BAD!
GNO
BSO
BROY
+12V/+V
GND
BDMT!
BFl/WI
GNO
BIRQf
B~2/
B~2
B071
GNO
B041
B02/
BOIl
+SV
Signal Name
Ground
Buffered Bank Address
Ground
Buffered Address Bit 13
Buffered Address Bit 11
Buffered Address Bit 10
Buffered Address Bit 8
Ground
Buffered Address Bit 5
Buffered Address Bit 3
Buffered Address Bit 2
Buffered Address Bit 0
Ground
'Buffered Set Overflow
'Buffered Ready
'User Spare 1
'+12 Vde/+V
Ground Line
'Buffered DMA Terminate
'User Spare 3
Buffered ReadlWrite "Not"
'System Spare
Ground
Buffered Interrupt Request
Buffered Phase 2 "Not" Clock
Buffered Phase 2 Clock
Butfered Data Bit 7
Ground
Buffered Data Bit 4
Buffered Oata Bit 2
Buffered Data Bit 1
+5 Vdc
Pin
Ie
2c
3c
4c
5c
6c
7c
8c
9c
IDe
llc
12c
13c
14c
ISc
16e
17c
18c
19c
20e
21e
22e
23e
24c
25e
26c
27c
28c
29c
30e
31c
32e
Note:
'Not used on this module.
9-97
Signal
Mnemonic
+5V
BA1SI
BA141
BAI2/
GNO
BA91
BA71
BA61
BA4/
GNO
BAIl
Bpll
BSYNC
BORQ1!
GND
-12V/-V
BFLT!
B~O
GNO
BORQ2/
BFI/"W
BACTI
BNMII
GNO
BRES!
BD61
B051
B031
GNO
BOOI
GND
Signal Name
+5 Vdc
Buffered Address Bit 15
Buffered Address Bit 14
Buffered Address Bit 12
Ground
Buffered Address Bit 9
Buffered Address Bit 7
Buffered Address Bit 6
Buffered Address Bit 4
Ground
Buffered Address Bit 1
'Buffered Phase 1 Clock
'Buffered Sync
Buffered DMA Request 1
Ground
'-12 Vde/-V
'User Spare 2
'Buffered Bus Float
'Buffered External Phase 0 Clock
Ground
BUffered DMA Request 2
Buffered Read/Write
Buffered Bus Active
'Buffered Non-Maskable Interrupt
Ground
Buffered Reset
Buffered Data Bit 6
Buffered Data Bit 5
Buffered Data Bit 3
Ground
Buffe red Data Bit 0
Ground
RM65-7102E
IEEE-488 Bus Interface Mddule
:
SPECIFICATIONS
Parameter
Value
.'
Dimensions (1. 2. 3)
Width"
.
3.9 in. (100 mm)
6.3 in. (160 mm)
0.56 in. (14 mm)
Length
Height
Weight
5.0 oz. (140 g)
En1(ironment
Operati~g Temperatu~
O°Cto nfC
-4O"C to +85°C
0% to 85% (without condensation)
Storage Temperature
Relative Humidity
+5 Vdc ± 5% @ 0:65A (3.25W)-Typical
1.0A (5:25W)-Maximum
PoWer Requirements
Interface
RM 65 Bus Interface
64-pin plug (0.100 in. centers) per DIN 41612 (Row b not installed)
. Module
VO Interface
Cable Receptacle
Trigger Connector
26-pin mass· terminated (0.100 in; centers)
Two vertical wire wrap pins (0.3·in. high on 0.200 in. centers)
IEEE-488 Bus Interface Cable
IEEE-488 Bus Connector:
:
Mpdule Connector
Cable Lengih
Type
Number of Conductors
Wire Size
24-pin mass terminated (2.16 mm centers) with metric thread lock
screws (AmphenoI57·or equivalent)
26-pin mass terminated (0.100 in. centers)
.8 inches
Flat ribbon
24
#28AWG
Notes:
1. Height includes the maximum values for component height abQve the board surface (004 in. for populated modules). printed circuit board
thickness (0.062 in.). and pin extension through the bottom of the module (0.1 in.).
2. length does not include the added extension due· to the module ejector.
3. Dimensions co~form tei DIN 41612.
'"
MATING
MOTHERBOARD
B.BIN.
1172MM)
r
F ' ' ' ' ' " = 1 1 , , / A N DRECEPTACLE
i
____
EUROCARD CONNECTOR
I
-
::
L-~ ___~
i
B.O\:DTH
@~
_ V
~
~"~g,, " :...- = ..
RIBBON CABLE
!i""r-
T---tJ
IEEE-48B
BUS CONNECTOR
II ---t f---~~~~~~~~ECTOR
Module Dimensions
9-911
~
RM65-7104E
RM 65 Microcomputer Family
'1'
RM65-7104E
RM 65 ADAPTER/BUFFER FOR AIM 65
Rockwell
RM 65 MICROCOMPUTER MODULES
FEATURES
RM 65 Microcomputer Module products are designed for OEM
and end user microcomputer applications requiring state-of-theart performance, compact size, modular design and low cost.
Software for RM 65 systems can be developed in R6500
Assembly Language, PLl65, BASIC and FORTH. Both BASIC
and FORTH are available in ROM and can be incorporated into
the user's system.
• RM 65 Bus Compatible
• Buffered address data and control lines
• Drives up to 15 modules
• Fully assembled, tested and warranted
PRODUCT OVERVIEW
RM 65 Module products use a motherboard interconnect concept and accept any card in any slot. The 64-line RM 65 Bus
offers memory addressing up to 128K bytes, high immunity to
electrical noise and includes growth provisions for user functions. A selection of card cages provides packaging flexibility.
RM 65 products may also be used with Rockwell's AIM 65
Microcomputer for product development and for a broad variety
of portable or desktop microcomputer applications.
The RM65-7104E Adapter/Buffer extends the AIM 65 Expansion Bus from the AIM 65 Expansion Connector to an RM 65
Bus motherboard that is situated up to 16 inches away. Included
circuitry permits the Adapter/Buffer to drive up to 15 RM 65 Buscompatible modules. (The similar Cable Driver Adapter/Buffer,
Part Number RM65-7116, provides the same drive capability for
applications in which the motherboard is up to six feet from the
Expansion Connector.)
ORDERING INFORMATION
Part No.
RM65-7104E
The Adapter/Buffer consists of an adapter module, a buffer
module and two 16-inch interconnect cables, Both cables are
flexible, so the motherboard may be installed in a wide variety
of locations and orientations relative to the AIM 65.
Description
Adapter Buffer for AIM 65
RM65-7104E Adapter/Buffer for AIM 65
Document No. RMA65N04
Data Sheet Order No. RM04
Rev. 2, May 1983
9-99
RM65 Adapter/Buffer t(n AIM 65
RM65-7104E
FUNCTIONAL DESCRIPTION
Jumper E2 selects the source·fOr the DMA Terminatelin~
(BDMTI)-elther the buffer modul9 o~ an e.xterrial ~odule: Ii\i~
the buffer mOdule Is ihe source (posltionA).;the Jj~A terminate
line is held high (inactive). For an extemal Source (plOsition W,
the DMA termina.te line is not used py the b!;Jffer mod!1Je, and
.
must be contrOlled by another module on the bus.
The Adapter/Buffer consists of two modll1esand two intercon-.
nect cables. The Adapter module connects 10 the AIM 65'
Expansion90nnector .and the. Buffer module cdnrle.c~i;to an. RM
65 Bus motherboard receptaCle.
.
The Adapter module transfers data,address and control lines
from AIM 65 Expansion Connector to the Interconnect cables.
Ttje eight data and 16 address lines are routed directly, without
buffering. The read/write,clock, sync and resetj~IM 65 output
control lines are also routed directly through the Adapter. The
ready, set overflow, interrupt request and non-maskable intertfle. module.
rupt AIM 65 input lines are ~uffered
INSTALLATION/REMOVAL
Installing
on
, Two 16~inch 40 conductor flat ribbon cables cpnnect the Adapter
mOdule to the Buffe'r module. The cables are mass terminated
at each end, and are permanently attached to the interfacing
module.
a. Before installing the Adapter/Buffer, turn off power to the AIM
65 and the' interlacing RM 65 Bus motherboard.
b. Configure Jumpers E1 andE2, per the Functional Destription.
c. Align the Adapter module connector J3 pin 1 with the AIM
. 65 ExpansiQn Connector J3 pint.
.
d, Pluglhe Adapter moJ/NI14J DTNElfllM6" &l'i'CIFKLJ
@PINJ
(e,".
.I'lI;Y~e,lc.~
~.mtt:I~hJlANIJ""'1.I4
INI 1I..t.t'I'MIU£CITJIP&Nllt.l.III'IE'D7D1n'
@JIIiIV,s 1a,~'5"<,..IIk.Q.,~/I.,Z/k:.2,J~.rn.NtJ,JI)~."i!.,
3NJtUN'1'1ED'('IIIWD..
All.
EnN 1I_¥If PNiS (2
GND.
T/~'~
"
nI'!t' "0)
SlI.fl.l. 44
". ;llt CIIAfCIrtJ/f3 ME • /O.t.$:1 ZO,., " , I ' .
9-109
Cable Driver Adapter/Buffer, for AIM6S
RM65-711.6E
SPECIFICATIONS
-.
Parameter
Value
Dimensions (1; 2. 3)
Cable Driver Adapter Module
Width
Length
Height
Buffer Module
Width
Length
Height
Weight
4.4 in. (111 mm)
5 In. (127 mm)
0.56 In. (14 mm)
3.9 in. (100 mm)
6.3 in. (160 mm)
0.56 in. (14 mm)
1.0 Ib (450 g)
Power
Cable Driver Adapter Module
Buffer Module
",
"
+5V:t 5% 30 mA (0.15W)-Typical
275 mA (O.25W)......:Maxirnum
+5V ± 5% 190 mA (0.95W)-Typical
330 mA (1.7W)-Maximum
Environment
Operating Temperature
Storage Temperature
Relative HumiditY
O°C to 700C
-40°C to +85°C
0% to 85% (without condensation)
Propagation Jlme'
50 ns..;."Maximum
Interfaces
Interfl\ce Connectors
AIM 65 Expan~ion Connector
22144...,..,edge receptacle (0.156 in., centers)
RM 65 Bus
Interface Cables
Number of Cables
Cable Length
Type
Number of conductors per cable
Wire Size
64-pin plug (0.1.00 in. centers) per DIN 41612 (Row b is not installed)
Two
6 teet
-;Flatribbon
40
#28AWG
Notes:
1. Height includes the maximum values for component height above the board surface (0.4 in. for pOpulated modules), printed circuit board
thickness (0.062 in.), and pin extension through the bottom of the module (0.1 in.).
'
2. Length does not include extensions beyond the edge of the module due to connectors or the module ejector.
3. Dimensions conform to DIN 41612;
9-110
RM6,5~7141.1E
RM'65 MIcrocomputer
RM6S..7t41E
RM 65 ADAPTER CABLE AND'
BUFFER MODULE FOR AIM 65/40
RMes MICROCOMPUTER MODULES.
PRODUCT OVERVIEW
AM 65 Microcomputer Module products are designed for OEM
. and end user microcomputer applications requiring state-of-I/)earlPEJrformance, cOmpact size, modular. design and low cost.
SClnWilre for RM 65 Systems can be developed in R6500
Assembly Language, PLl65, BASIC and FORTH. Both. BASIC
and.i=ORTH are available in ROM and can be incorporated into
the users syStem;
The RM65-7141 E Adapter ClI.ble and Buffer MOdule extends the
AIM 65/40: Expansion Bus from the AIM 65/40. Expansion Connector to RM 65 Bus motherboard that Is situated up to two
meters (79 inches) away. Ol)-board circuitry permits the buffer
module to drive up to 15 RM65B~-:coinpatlble modules.
The Adapter Cable' and Buffer Module consists of a buff8r
module anda 2-rneter interconnect cable.1:hEi'cable isfllaxible,
sO the motherboard may be Installed In a wide variety of locations and orientations relative to the AIM 65/40 SBC module.
RM 65 MOdulI! products use a motherboard interConnect concept and accepts any card in any slot. The 64-line RM 65 Bus
offers memory addressing up to 128K bytes, high immunity to
electrical noise and includes growth provisions for. user functions. A selection of cardcagell provides packaging fleXibility.
RM 65 products may also be used with Rockwell' AIM 65 and
AIM 65/40 Microcomputllrs for product development and for a
broad variety of portable or desktop microcomputer applications.
FEATURES
• .RM 65 Bus cOmpatible
• Buff~ addresS; data and'contro'lines
• Drives up to 15 modulell
• Long cable for distances up to 2 meters
• Edg~ connector andEliioeEii-d versiOns
• F~lIy asse,!,bled. tesfed.. a~d warranted
ORDERING INFORMATION
, Deacrlptlon
. Adapter Cable ahd Buffet Module for AIM 65140
RM65-7141E Adapter Cable and Buffer Module for AIM 65/40
Document No.RMA65N25
9-.111
Data Sheet Order No. RM25
Rev. 1, May 1983
RM65-7141E
Adapter Cable and Buffer Module for AIM 65/4.0
FUNCTIONAL DESCRIPTION
The RM65-7141E Adapter Cable and Buffer Module consists'of
one module and one interconnect;caple. The cable COrm6!;ts to
the AIM 65/40 SBC module Expanskin connector and the modure
connects to an AM 65 Bus motherboard recept!aCle.
the AIM 65/40 SSC module is th~source (position AMhe.,DfI11A
terminate line (BDMT/) from the AIM 65/.40 SB.C module'is"p.ut
on the RM 65 Bus. For an external sourcEI' (posiliori B), the OMA
terminate line is not used by the buffer modiile, and must be
controlled by another module on the bus. .
The two meter 64-conductor flat ribbon cable connects the AIM
65/40 SBC module to the buffer module. The cable is mass terminated at each end. One end of the cable connects to the SBC
mOdule Expansion connector (Euro connector) and the other
end connects to the buffer module.
INSTALLATION/REMOVAL
Installing the Adapter Cable and Buffer Module
Before installing the 'module, inspect for damage anll'grease.
dirt, liquid or other foreign materials that will'affect performance.
The module buffers and routes all interface'Signals between the
.
interconnect cable and the' AM 65 Bus connector. "
a. Betore installing the AIM 65/40 Ad'apter Cable and Buffer
Module, turn off power to the AIM 65/40 SSG. module and
the interfacing. AM 65 Bus motherboard.
.
b. Configure Jumpers E1 and E2, per the FUnctional Description.
c. Connect the cable Euro receptacle connector onto the AIM
65/40 SBC modUle Expansion .connector (Euro connector).
d. Connect the other cable connector onto buffer module connector P2.
'''.'
e. Install connector P1 ofthe buffer module into the'desired. slot
or the mating RM 65' Busmotherboilrd.
The Data Transceivers (Z6) invert and drive a-bits of parallel
data. During a writ~ operatiOn, data received from the cable are
driven onto the RM 65 Bus. During; a read operation, data
received from the RM 65 Bus are driven onto the cable. The
b~S active signal (BACT/) enables the Transceivers. When the
bus noat signal (BFLT/ps active, the Transceivers are disableq~
The Address Buffers (Z1 and Z3) inver:! and transfer 16 parqllel
address lines from the. interconnect cables to the RM 65 Bus.
When the bus float signal (BFLT/l is active, the Buffers are
disabled.
CAUTION
RM 65 Bus connectors are keyed to prevent
improper module connection. If the module d061i not
insert into the receptacle with 'moderate pressure
applied, check the orientation and connector alignment of the module. Forcing the module improperly
into the receptacle may damage the. receptacle andl
or the module.
Jumper E1 selects the' source for the. bank addresS line
(BADR/)-either the AIM' 65/40 SBC module or another contrOlling mOdule on the RM 65 Bus. When the AIM 65/40 SBC
module is the source (position A)" . the bank address line
(BADRI) is sourced by the AIM 65/40 sac module; thiS line is
disabled when the bus float line (BFLT/) is active. For an external
source (position B), the bank address line is not used by the
buffer module, and must be controlled by another module on
the RM 65 Bus.
f. Apply power to the AIM 65/40 SBC module and to the mating
RM65 Bus motherboard. (Power to the AM 65 motherboard
is not supplied by the Adapter Cable and Buffer Module.)
The read/write (BRlW and BRIW/), clock (B02, SO:?! and B01),
BSYNC and reset (BRESI) lines 'from the cable to the bus are
buffered by the Control Buffers (Z5). All of these lines, except
BRES! and B01 are disabled when the bus float line (BFLT/) is
active. The ready (BRDy), set overflow (BSO), interrupt request
(BIRQ/) and non-maskable interrupt(BNMV) lines from the bus
to the interconnect cable are also buffered by the Control Buffers.
Removing the Adapter Cable and Buffer Module
a. Turn off power to the AIM 65/40 SBC module and to the RM
65 Bus motherbOard.
b. Pull the buffer module straight back until it is free from the
RM 65 Bus receptacle and card cage slot guides.
c. Disconnect the cable connector from the AIM 65/40 SBC
module, ExpanSion connector.
Jumper E2 selects the source for the DMA T~~minate line
(BDMT/)-either the buffer module or an external module. When
9-112
RM65-71.41E
.AdapterC.ble and Buffer Module for· AIM 65140
Pin
la
2a
3a
4a
Sa
6a
7a.
8a
9a
jOa
11a
Signal
Mnemonk:
GNO
BADRI
GNp
BA13!
BA11/
BA101
BAB/
GNO
BASI
BA3/
BA2/
l~a
BAOI
138
14a
lSa'
168
17a
18a
19a
20a
21a
22a
23a
24a
25a
26a
27a
28a
29a
30a
31a
32a
GND
eso
BRDY
+12V/+V
GND
BOMTI
BRlWI
GNO
BIRQ/
802/
802
B071
GND
BD4I
BD2/
B011
+5V
BM 65 Bus Pin Assignments
.,
.
Bottom (Solder Side)
Signal Name :
,.
Ground
Buffered Bank Address'
Ground
BlJffered Address Bit 13
Buffered Address Bit 11
Buffered Address Bit 10
Buffered Address Bit 8
Ground
Buifered Address Bit S
Buffered Address Bit 3
Buffered Address Bit 2
Buffered Address Bit 0
Ground
,Buffered Set Overflow
Buffered Ready
"User Spare 1
"+12 Vdc/+V
Ground Une
Buffered DMA Terminate
"User Spare 3
Buffered Read/Write "Not"
'System Spare
GroUnd
Buffered Interrupt Request
Buffered Phase 2 "Not" Clock
Buffered Phase 2 Clock
Buffered Data Bit 7
Ground
Buffered Data' Bit 4
Buffered Data Bit 2
BUffered Data Bit 1
+SVdc
;'1/0
O.
0
0
0
0
0
0
0
0
I
I
Type
Pin
Power
3STTL
Power
3STTL
3S TTL
3STTL
.3STTL
Power
3STTL
3STTL
3SnL
3STTL
Power
OCTTL
OCTTL
1c
2c
4c
. SC
6c
7c
8c
9c
10c
11c
12c
13c
14c
lSc
16c
17c
18c
19c
20c
21c
22c
23c
24c
25c
26c
27c
;28c
29c
30c
31c
32c
Power
0
I
0
0
VO
110
VO
lio
+5V
BA15/
BA141
BA12/
GNO
BAS!
BA71
BAGI
BA4/
GNO
BA11
B01
. BSYNC
BORQ11
GNO
3c
0
3STTL
Power
OCTTL
3STTL
3STTL
3STTL
Power
3STTL
3STTL
3STTL
Power
Top (COmponent Side)
Signal
Mnemonic
-12V/-V
BFLTI
BOO
GNO
BORQ2/
BRlW
BACTI
BNMV
GNO
BRESI
B06/
B05/
B03!
GNO
BOOI
GNO
Signal Name
I/O
+5 Vdc
Buffered Address Bit 15
Buffered Address Bit 14
Buffered Address Bit 12
Ground
Buffered. Address Bit 9
Buffered Address Bit 7
Buffered Address Bit 6
Buffered Address Bit 4
Ground
Buffered Address Bit1
Buffered Phase 1 CloCk
Buffered Sync
'Buffered OMA Request 1
Ground
"-12 VdC/-V
• User Spare 2
Buffered Bus Float
"Buffered Externa.1 Phase 0 Clock
Ground
'Buffered OMA Request 2
Buffered Read/Write
Buffered Bus Active
Buffered Noo-Maskable Interrupt
Ground
Buffered Reset
Buffered Data Bit 6
Buffered Data Bit S
Buffered Data Bit 3
Ground
Buffered Data Bit 0
Ground
0
0
0
0
0
0
0
0
0
Power
I
0
I
I
0
VO
VO
VO
VO
CON NECTTO
RM. 65 BUS
RECEPrACLE
,
-
CONNECTOR r--
8
'i--
DATA
8
DATA
TRANSCEIVERS
BUS ACTIVE
bATA
BUS FLOAT
r-
ADDRESS
CLOCK
AND
CONTROL
I
I.....
Jl
16
ADDRESS
Bt,lFFERS
.--
'+-
+5V
16
ADDRESS
B
I
.,
~ .~~b::'
~7
F
f-~
f--
,
F4
~
J2
CONTROL
BUFFERS
7
r---;.o:f.
P2.
B'~O
RM65".7141E Adapter Cable and Buffer Module BlOCk Diagram
9·113
BANK ADDRESS
CLOCK
} AND
CONTROL
/4
~
OCTTL
Power
Notes:
'Not used on this module. Signal nam!! reflects: RM 65 Bus reser.ved function.
CONNECT TO
AIM 65/40
SBC MODULE
2 MCABLE
EXPANSION ~,_ _ _ _" -
Type
Power
3STTL
3S.TTL
3STTL
3STTL
3STTL
3STTL
3STTL
3STTL
Power
3STTL
TPTTL
3STTL
OMA TERMINA.TE
3STTL
OCTTL
OCTTL
Power
OCTTL
3STTL
3STTL
3STTL
Power
3STTL
Power
Adapter Cable and Buffer Module for AIM 65/40
RM65-7141E
..
I
II
!~
-
'I
-
j_~H
h ~~
H!HW
iW
~HU~~!
'I ~'t~~ ~il~~
H
~~
iU!
~U ~
f-
.
~
~e
191
~l
-
~
5
~
-!
Uli liii
I
9-114
~
fli\ft6S-7141 E
Adapter Cable and Buffer Module for AIM 65/40
SPECIFICATIONS
Characteristic
Value
Dimension (See Notes)
Width
Length
Height (see Note t)
"
100 111m (3.9 in.)
160 mm (6.3 in.)
14 mm (0.56 in.)
.,
.-
Weight
1.0 lb. (140 g)
P_er (Supplied from RM 65 Bus)
+5V ± 5% 170 mA (0.85 W)-Typical
. 270 mA (1.35 W)-Maximum
Environment
Operating Temperature
Storage Te.mperature
Relative Humidity
.'
O"q to 70°C
-40°C to 85°C
0% to 85% (without condensation)
Propagation Time (m~imum)
35 ns Address Bus
70 ns Data Bus (ref BACT/)
Interface Connectors
AIM 65/40 Expansion Connector
54-pin DIN'connector (0.100 in. centers) per DIN 41612 (males with j:lurndy .
RP196B32POA02K!i or -equivalent)
. '-'
RM 65 Bus
64-pin plug (0.100 in. centers) per DIN 41612 (Row b is not inl;ltalled)
Interface Cables
Number of Cables
Cable Length
Type
Number of conductors per cable
WireSi.ze
Connectors (Part Number)
One
2 m (78 in.)
Flat ribbon
64
#28AWG
Jl Winphester 965-6053-0.5.31-12 or equivalent
J2 Winchester 645-6053-4/12-12'
T & B Ansley 609-641-2
Cannon 006D64R3.BAL or equivalent
Notes:
.'
.
1. The height includes the maximum values lor component height above the board surface (O.4in. for populated modl.lles), prir)ted circuit board
thickness (0.062 in.), and pin extension through the bottom of the module (0.1 in.). Allow an additional 19 nim (0.75 in.) for the connector on
the bottom of the module and cable bend.
2. The length does not include extensions beyond the edge of the module due to connectors or the module ejector.
.....
3_ The dimensions conform to DIN 41612.
" .
.-
172 MM
IN.)
~I
LENGTH
Jl
·1
I
I
1
'1
I
.1
EUROCAF\D
VERSION
I
I
.
S
. ' "C;o,MPONENT ARE~;
~UAOCONN~CTOR
....
'&-,
CA8LE1rr-P---------L~~~:...-- ~
Module Oimensions
9-115
RM65-7201E
RM 65 Microcomputer Family
'1'
Rockwell
RM65-7201E
RM 65 DESIGN PROTOTYPINGMODULE
RM 65 MICROCOMPUTER MODULES
FEATURES
The RM()5-7201E Design Prototyping Module is one of the
hin plug (0.100 In. centers) per DIN 41612 (Row b Is not Installed)
"
,
Number of Component Hole Columns:
Number of Componell\ Hole Rows:
Number of +5V power strips:
Number of lealated power strips:
Number of ground strips:
Vertical hOle spacing:
Horizontal hole spacing:
r
,
i.9in. (100 mm)
6.3 in. (160 mm)
0.56 in. (14 mm)
"
36
36
6
4
..•.
\
9
'
'
0.100 in.
0.100 in.
Notes:
1. Height Includes the maximum values f~r component height above the board surface (0.4 in. for populated modules). printed circuit
thlcmess (0:062 in.), and pin extension through the bottom of the module (0.1 in.).
2. Length does not include the added eXlensioos due to the module ejector.
3. Dimensions conform to DIN 41612.
~~:'~~Ml~ ~~~~NE~BOARD
r ,.
t--LENGTH4
llANoRECEPTACLE
-n
'/
EURQ~ARD Cp,NNECTOR
-II
LO~O~E:~~_
Ii
t
WLIDTH
::
HEIGHT
,I
..-
II
T- --~
L---'------------l~
. "
!--eUROCONNECTOR
EXTENSION
Module Dimensions
". ,
'I"
,~
;
9-119
board
RM66-7211E
RM 65 Microcomputer Family
'1'
RM65-7211E
RM 65.EXTENDER MODULE
Rockwell
!=1M 65 MICROCOMPUTER MODULES
FEATURES
The RM65-7211 E Extender Module is one of the hardware
options available for the RM 65 Microcomputer Module family.
• Extends all RM 65 Bus Lines
• Terminals for GND and +5V
• Assembled, tested arid warranied
RM 65 Microcomputer Module products are designed for OEM
and end user microcomputer applications requiring state-of-theart performance, compact size, modular design.and low cost.
Software for RM 65 systems can tie developed in R6500
Assembly Language, Pll6S, B,4,SIC and FORTH ... Both BASIC
and FORTH ani available in ROM and can be incorporated into
the user's system.
RM 65 module. products use a motherboard interconnect concept .arrd accept any card in any slot. The 64-line RM65Bus
offers memory addres.sing up to 128K bytes,high immun~y to
electrical noise and includes growth provisions for user func~
tions. A selection of card cages provides packaging flexibility.
RM 65 products may also be used with Rockwell AIM 65 and
AIM 65/40 Microcomputers for product deVelopment and for a
broad variety of portable or desktop microcomputer.applications.
PRODUCT OVERVIEW
The RM 65 Extender Module physicaily extends ~ !TIOdule that
is electrically cor:mec;teq to. WI RM 65 motherboard. ·This simplifies signal tracing and troubleshooting by providing access to
the module outside of its card cage or enclosure.
The RM 65 Extende( Mod'ule consists ofa series of bus lines
connecting the RM· 65 connector plug on one end, to an RM 65.
compatible connector receptacle on the other end. The lines are
connected pin-far-pin between the pJug and receptacle.
ORDERING INFORMATION
Part No.
RM65·7211E
Description
Extender Module
RM65-7211E Extender Module
Document No. RMA65N07
Data Sheet Order No. RM07
Rev. 2, June 1983
.'
..
. RM65-7211 E .
Extender Module
'\"",
.
.
RM 65 Bus Pin Assignments
Bottom (Solder S~e)
Pin
'.
1a
~a
3a
4a
58
6a
7a
sa
.'
,
9a
lOa
11a
12a
138
14a
15a
16a
17a
18a
19a
20a
21a
22a
23a
248
25a
26a
27a
28a
29a
30a
3ta
32a
I:
Top (Compone,!1 Side)
~Ignal
I;lg~!
Signal Name
Mnemonic.
··.GND
BADfV
GNP
~131
BA11!
BA101
BASI
GND
BASI
BA3i
BA2/
BAOI
GND
BSO
BRDY
+12V/+V
GNQ
BDM1-1
BRiwl
GND
BIRQ/
;
B071
GND
BD4I
BD2I
BOll
.+5V
Pin
G(OUnd
Buffered Bank Address
Ground
Buffered Address Bit 13
Buffered Address Bit 11
Buffered Address Bit 10
Buffered Address Bit B
Ground
Buffiired AddressE1it 5
Buffered Address Bil 3
Buffered AddresS Bij 2
Buffered Address Bit 0
.
Ground
Buffered Set Overflow
Buffered Ready
User Spare 1
+12 VdC/+V
Ground Une
Buffered DMA Terminate
User Spare' 3
Buffered ReadlWr~e "Nor'
System Spare
Ground
Buffered Interrupt Request
Buffel'!ld Phase 2 "No.1" Clook
,auffered Phase 2 Clock
.Buffered Data Bit 7
Ground
Buffered Data Bit.4
Buffered Data Bit 2
Buffered Data Bit 1 .
+5 Vde
Mnemonic
1e
2e
30
.,4e
50
60
7c .'
Be
ge
10e
110
120
130
140
150
16c
170
1Be
1ge
20c
210
220
23e
240
250
26c
270
2Be
29c
30c
31e
32c
+5V
BA151
BA141
BA121
GND
BA91
BA71
BASI
BA4I
GND
BAll
B~1
BSYNC
BDRQ11
GND
-12V/-V
BFLTI
~O
GND
BDRQ2I
BfVW
BAcTI
BNMV
GND
BRES!
eD6I
BD5I
BD3/
GND
BOO!
GND
Signal Name
+5 Vdo
Buffered Address Bit 15
Buffered Address Bit 14
Buffered Address Bit 12
Ground·
Buffered Address Bit 9
Buffered Address Bit 7
Buffered Address Bit 6
Buffered Addre!;ls Bit 4
Ground
Buffered Address Bit 1
Buffered Phase 1 Clock
Buffered Syno
BL\ffered DMA Request 1
Ground
-12 VdC/-V
User Spare 2
Buffered Bus Float
Buffered External Phase 0 Clock
Ground
Buffered DMA Request 2
Buffered Read/Write
Buffered Bus Activl;O
Buffered Non-Maskable Interrupt
Ground
Buffered Reset
Butfered Data B~ 6
Buffered Data B~ 5
Butfered Data B~ 3
Ground
Buffered bata Bit 0
Ground
INSTALLATION
Before Installing the module, Inspect for damage and grease.
dirti liquid or other foreign materials that will affect perfonmance.
c. Insert the .Extender Module In a vacant card slot In the card
cage and connect it to the motherboard,
a. Turn power off to the RM 65 bus.
d. Connect the module to be extended to Jl of the Extender
Module.
CAUTION
CAUTION
Never install orrernove modules with power 'On-it may
cause damage to the host system or the modules Qeing
.cOnnected or disconnected.
b, Remove' mollule
(if present).
. Be sure the extended module is properly supported to
prevent damage to the module and/or the Extender
Module.
to bE\exte.nded fI'om the RM6s card cage
.
.
e. Apply power to .the RM 65 bus.
9-121
Extender· Module
RM65-7211E
SPECIFICATIONS
Parameter
Value
'",
,-
Dimensions (1, 2, 3)
Width
Length
Height
3.9 in. (100 mm)
7.4 in. (187 mm)
0.56 in. (14 mm)
Weight
3.2 oz. (90 g)
Interface Connectors
RMes Bus
64-pin plug (0.100 in.
RM 65 Module
64,pin plug
'
..
..
. co'
cen;~':') per DIN 41612 (Row b is not used)
(o.Hio in. centers) per DIN 41612 (Row b is not u~)
Notes:
1. Height includes the maximum values for component height above the board surface (0.4 in. for populated modules), printed circuit board
thickness (0.0i'l2 in.). and pin extension through the bottom of the modlile (0.1 in.).
2. Length does not include the added extension due to the module ejector.
3. Dimensions conform \0 DIN 41612.
.
MATING
MOTHERBOARO
r
,_
~
LENGTH4
,
IA,"'K'n~"
r---r,
L
HEIGHT
i
VVL'O'"
~
________________________
r-
.11
~~
-u"
~ !--EUROCONNECTOR
eXTENSION
Module Dimensions
9-122
Cb
SECTION 10
INTEGRAL MODEMS
Page
Product Family Overview ....... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
'10-2
High Speed
R96FAX 9600 BPS Facsimile Modem . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10-3
R96DP 9600 BPS Data Pump Modem ......•.................................. 10-13
R96FT 9600 BPS Fast Train Modem ...........................'. . . . . . . . . . . . . . 10-26
V96PJ1 9600 BPS Modem ,................................................ 10-28
R48DP 4800 BPS Data Pump Modem ........................................ 10-36
V27PI1 4800 BPS Modem .................................................. 10-49
Low to Medium Speed
R1212 1200 BPS Full Duplex Modem ....................................... , 10-56
R2424 2400 BPS Full Duplex Modem ........................................ 10-70
R24DC2400 BPS Direct Connect Modem .................................... 10-84
R24LL 2400 BPS Leased Line Modem ....................................... 10-92
R24 2400 BPS Integral Modem ............................................ 10-t01
MOdem Interfacing Products
R24MEB Modem Evaluation Board ......................................... 10-109
RDM Rockwell Data Access Arrangement Module ............................ 10-111
10-1
INTEGRAL MODEMS
Highest Quality, Performance at Competitive Cost
Rockwell International's high-speed integral modem
subsystems offer better performance and greater reliability
than any others. They're also more cost effective and are
optimized tei match more applications than others. That's
why Rockwell produces more high-speed integral modem
subsystems than any other company.
The chances are, if you're using a high-speed box
modem, a Rockwell subsystem is in it. Practically every
facsimile machine uses our modems. Rockwell is, by far,
the leading supplier to Japanese facsimile machine
manufacturers. With 99.6% of our subsystems accepted by
incoming inspection, we have documented an MTBF of
200,000 hours, or about 23 years between service calls.
As for performance, our modems don't lose a bit in a
million, even over long distance lines of the commercial
telephone network. Much of this is because of our signal
proceSSing capabilities, equalization and diagnostics.
Built-in diagnostics, such as eyepatternand mean
squared error, allow thorough modem testing. Several
stages of equalization permit accurate transmission over
even unconditioned lines. In fact, adaptive equalization,
which compensates for phase shifts and frequency delays,
was originated in modem technology under a basic patent
owned by Rockwell.
Much of modem technology came from Rockwell
International. Our first modems date back to vacuum tube
versions in 1955. We made the first LSI integral modems in
19.6.9. Today, we cover all speeds from 1~00-to 9600 bps,
with a 14,400 bps model to be announced.
Our newest third-generation LSI family members are
designed to be addressed as microcomputer peripherals,
thus simplifying design and reducing costs of the host
equipment. They're on interchangeable cards, small
Eurocard sized, so you can switch communication speeds
.' without expen'sive design changes.
And, they're optimized for specific applications-for box
modems and statistical multiplexers, for facsimile
equipment, for use in multi-point system terminllls,· etc.
They're also low in price and readily available. Being the
largest manufacturer lets us pass our advantages onto dur
customers. We offer the .best cost/performance modem
subsystems, with the highest reliability. There's no one else
close.
Rockwell Integral Modem Subsystems Lead The Industry
1973
1983
Size
MTBF (Thousand Hours)
50
ACCEPTANCE(%)
95
CARD SIZE (Sq. In.)
112
100
200
99.5
99.7
54
10
10-2
R9.6FAX
•
I
"
"
Integral Modems
R96FAx
$600 BPS FACSIMILE MODEM
PRELIMINARY
INTRODUCTION
FEATURES
the RockwellR96FAX is a synchronous serial 9600 bps modem
designed for operation over either dedicated unconditioned lines
or over the general switched telephone network.
• Ultimate User Compatibility: .
.
- CCITT V.29, V.27 ter, T.30, V.21 Channel 2, T.4, T.3
• Group III ~nd Group II Facsimile
• Half-Duplex (2-Wire)
• Programmable Tone Generation and Detection
• Dynamic Range -43 dBm to 0 dBm
• Diagnostic Capability
• Equalization:
- Automatic Adaptive
- Compromise Cable (Selectable)
- Compromise Link Amplitude (Selectable)
. .
• DTE Interface:
- Microprocessor Bus
- CCITT V.24 (RS-232-C Compatible)
• Small Size - 100 mm x 65 mm (3.94 x 2.56 inches)
• Low Power Consumption (2 Watts, Typical)
• Transmit Output Level (+ 5.5 dBm ± 0.5 dB)
• JTL anE! CMOS Compatiple
The modem satisfies telecommunications requirements specified
in CCITT Recommendations V.29 and V.27 ter, and of Recommendations T.30, T.4 and T.3.
The R96FAX is specifically optimized for use in Group III
Facsimile machines with the added capability of Group II
compatibility. The small size and low power consumption of the
modem offer the user flexibility in creating a 9600 bps modem
design customized for specific packaging and functional
requirements.
The modem is capable of operating at 9600,
and 300 bps.
noo, 4800, 2400,
R96FAX Modem
Document No._ 29200N06
10-3
Data Sheet Order No. MD06
Rev. 1 November 1983
9600 bps Facsimile Modem
is di~ided into three bits (tribits)fQr,ping' a,n8.point structure.
At 4800 bps, the data stream is divided into. two bits (dibjts)
forming a 4-point structure.
TECHNICAL SPECIFICATIONS
ThE! following are the technical specificati0'1sfor the R96.FAX
modem.
TRANSMITTER TONAL SIGN~LING ANO CARRIER
FREQUENCIES
At 1600 baud, the 4800 bps data stream is en<::oded into triblts
per CCITI V.27 ter.
The transmitter tonal signaling and carrier frequencies are given
in the following tables:
T. 30 Tonal Signaling Frequencies
At 1200 baud, the 2400 bps data stream is encoded intO dibits
per CCITT V,27ter.
i!!p~clflcatlon
EQUALIZERS
(Hz :l: O.S Hz)
Frequency Type
Calling Tone. (CNG)
Answer rone (CEO)
Group II Identification (CI2)
Group Ii Command (GC2)
Group II Confirmation (CFR2. MCF2)
Line Conditioning Signal (LCS).
End of Message (EOM)
Procedure Interrupt (PIS)
The R96FAX provides equalization functions which can be used
to improve performance when operating over poor linjls.
1100
2100
1850
2100
1650
1100
1100
462
Cable Equalizers - Selectable compromise cable equalizers
are provided to optimize performance over different lengths of
non·loaded cable of 0,4 mm diameier.
.
Link Amplitude Equalizer - The selectable compromise
amplitude equalizer may be inserted into the transmit.and/or
receive paths uoder control of the t(ansmit amplitude equalizer
enable and the rec.eive amplitudjl equaliZer enable bits in. the
interface memory. The amplitude select bit controls which of two
amplitude equ'alizers is selected ..
Carrier Frequencies
Specification
(Hz :l: O.S Hz)
Frequency Type
T . 3 Carrier (Group II)
V.27lerCarrier
V.29 Carrier
2100
1800
1700
Automatic Adaptive Equalizer - An automatic adaptive
equalizer is provided in the. receiver circuit for V.27 and V.29
configurations. The equalizer can be configured as either a T
or a T/2 equalizer,
TONE GENERATION
Under control of the host processor; the R96FAX can generate
voice band tones up to 4800 Hz with a resolution of 0.15 Hz and
an accuracy of 0.01%. Tones over 3000 Hz are attenuated.
TRANSMITTED DATA SPECTRUM
If neither the link amplitude nor cable equalizer is enabled, the
transmitter spectrum is shaped by the following raised cosine
filter functions:
1. 1200 Baud. Square root of 90 percent
, 2, 1600 Baucj. Square root of 50 percent
3, 2400 Baud: Square root of 20 percent
The out-of-band. transmitter 'power limitations meet those
specified by Part 68 of the FCC's Rules, and typically exceed
the requirements of foreign telephone regulatory bodies,
TONE DETECTION
In the 300 bps FSK receive configuration; the presence of tones
at preset frequencies is indicated by bits iA the,inter!ace memory
of the R96FAX. The frequenciEis and responses may be altered
by the user via microprocessor control,.
SIGNALING AND
DATA~AT'ES"
The signaling and d.ata rates fortheR96FAX aredefined'inthe
table below:
"
s·Igna r10910ata Rat es
Parameter
'
'.
SCRAMBLER/DESCRAMBLER
,,'
The R96FAX incorporates a self-synchronizing scramblerl .
descrambler. This facility is in accordance with either V.27 ter
or V.29.depending on the selected configuration.
SpePlflcation
(:I: 0;01%)
Signaling Rate:
Data Rate:
2400 B"ud
9600 bps.
7200 bps,
4800 bps
Signaling Rate:
Data Rate:
1600 Baud
4800 bps
Signaling Rate:
Data Rate:
'1200 Baud "
2400 bps
,
RECI;IVEDSIGNAL
FREQUENCY TOLERANCE
The receiver circuit of the R96FAX can adapt to received
frequency error of up to ±' 1.0 Hz with less than a 0.2 dB degradationin SER performance. Group Ii carrier recovery capture range
is 2100 ± 30 Hz,
RECEIVE LEVEL
DATA ENCODING
The receiver circuit of theR96FAX satisfies all specified performance requirements for received line signal levels from OdBm to
-43dBm. The received line signal level is measured at the
receiver analog input (RXA).
At 2400 baud, the data stream is encoded per CCITI V,29. At
9600 bps, the data stream is divided in groups of four-bits (quadbits) forming a 16-point structure. At 7200 bps, the data stream
10-4
9600 bps Facsimile Modem
R96FAX
2. Received Line Signal Detector (RLSD). RLSD is clamped off
(squelChed) during the time when RTS is on.
3. Extended Squelch. Optionally, RLSD remains clamped off for
130 ms after the ol'Ho-off transition of RTS.
RECEIVE TIMING
In the receive state, the R96FAX provides a Data Crock (DCLK)
output in the form of a square wave. The low to high transitions
of this output coinCide with ihe center of received data bits. The
timing recovery circuit is capable of tracking a ± 0.01 % frequency error in the associated transmit timing sour,ce.
RESPONSE TIMES OF CLEAR-TO-SEND (CTS)
The time between the off-to-on transition of RTS and the off-toon transition of CTSis dictated by the length of the training
sequence. Response time is 253 ms for V.29, 708 ms for V.27
ter at 4800 bps, and 943 ms for V.27 ter at 2400 bps.
TRANSMIT LEVEL
The transmitter output level is fixed at + 5.5 dBm ± 0.5 dB. When
driving a 600 ohm load the TXA output requir~s a 600 ohm series
resistor to provide - 0.5 dBm ± 0.5 dB to the load.
The time between the on-to-off transition of RTS and the on-tooff transition 'of CTS in the data state is a maximum of 2 baud
times for all configurations.
TRANSMIT TIMING
In the transmit state, the R96FAX provides a Data Clock (I)CLK)
output with the following characteristics:
1. Frequency. Selected data rate of 9600, 7200, 4800, 2400,
or 300 Hz (± 0.01 %). In Group II, DCLK tracks an external
10368 Hz clock.
2. Duty Cycle. 50 ± 1 %
RECEIVED. LINE SIGNAL DETECTOR (RLSD)
For either '11.27 ter or '11.29, RLSD turns on at the end of the training sequence. If training is notdetected at the receiver, the RLSD
off-to-on response time is 15 ± 10 ms. The RLSD on-to-off
response time .for V.27 is 19 ± 5 ms and for V.29 is 30 ± 9 ms.
Response.times are measured with a signal at least 3 dB above
the actual RLSD on threshold or at least 5 dB below the actual
RLSD off threshold.
Transmit Data (TXD) must be stable during the 1 microsecond
periods immediately preceding and following the rising edge of
DCLK.
TURN-ON SEQUENCE
The RLSD on-te-off response time ensures that all valid data bits
have appeared on RXD.
A total of ten selectable turn-on sequences can be generated
by the R96FAX, as defined in the following table:·
Turn-On Sequences
NO.
1
2
3
V.29
9600 bps
7200 bps
4800 bps
4
5
6
7
8
9
10
V.27 ter
RTS-CTS
Time (ms)
4800 bps2
2400 bps2
253
253
2.53
708
943
4800 bps2
2400 bps2
458
458
458
913
1148
9600 bps
7200 bps
4800 bps
Two thre!lhold options are provided:
1. Greater than -43 dBm (RLSD on)
Less than -48dBm (RLSD off)
2. Greater.than -47dBm (RLSD on)
Less than -52 dBm (RLSD off)
Comments
NOTE
Performance may be at a reduc.ed level when the received
signal is less than -43 dBm.
Preceded
By Echo
Suppressor
Disable
Tone
A minimumhysleresis action of 2 dB exists between the actual
off-to-on and on-to-off transition levels. The threshold levels and
hysteresis action are measured with an unmodulated carrier
signal applied to the receiver's audio input (RXA),
NOTES
1. Turn-on sequences six through ten can be generated for
lines with protection against talker echo.
2. V.27 ter long training sequence only.
MODES OF OPERATION
TURN-OFF SEQUENCE
The R9,6FAX is capable of being operated in either a serial or
.
a parallel mode of operation.
For V.27 ter, the turn-off sequence consists of approximately
10 ms of remaining data and scrambl!ld ones at 1200 baud or
approximately 7 ms of data and scrambled ones at 1600 baud
followed by a 20 ms period of no transmitted energy. For V.29,
the turn-off sequence consists of approximately 5 ms of remaining data and scrambled 1's followed by a 20 ms period of no
transmitted energy.
SERIAL MODE
The serial mode uses standard V.24 (RS-232-C compatible)
signals to transfer channel data. An optional USRT device
(shown in the R96FAX Interface Diagram) illustrates this
capability.
CLAMPING
PARALLEL MODE
The following clamps are provicled with the R96FAX:
1. Received Data (RXD). RXD is clampecl to a constant mark
(1) whenever RLSD is off.
The R96FAX has the capability of transferring channel data eight
bits al a time via the microprocessor bus.
10-5
m
I
R96FAX
9600 bps Facsimile Modem
.-,....,.
r1
1
RTS
I::::
USRT
(OPTIONAL)
I
I
I
I
I
CTS
TXD
I ..'"
i
DCLK
i
XCLK
L-.
RLSD
r
.. ,,..
RXD
..
'"'
,.;.
R96FAX
MODEM
I
i.>
+12V
+5V
I'
GND
POWER
SUPPLY
~12V
READ
....
DATA BUS (8)
ADDRESS BUS (4)
t
..
TXA
Di
RSi
LINE
RXA
I
INTERFACE
CS (2)
"
, DECODER......
, '-;"': CSi
POR .. .,...,~
,IRQ;:::
J
fy
EYE
PATTERN
GENERATOR
EYESYNC
EYECLK
,_ J
WRITE
fh'
J
EYEX
I
J
q~O~E:
CABS1"
~
!
I
I
L .... _ .....
HOST
PROCESSOR
(OTE)
CABS2
...-
=1
TELEPHONE
LINE
AUXIN'
+5-'VY..J
'.
R96FAX Functional Interconnect Diagram
R96FAX Hardware Supervisory Circuits (Cont )
MODE SELECTION
Name
Selection of either the serial Or parallel mode of operation is by
means of a control bit. To enable the parallel mode, the control
bit must be set to a 1. The modem automatically defaults to the
serial mode at power-on. In either mode the R96FAX is configured by the host processor via the microprocessor bus.
D7
D6
D5
D4
D3
D2
D1
DO
INTERFACE CRITERIA
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins in a
40-pin ribbon connector. Software circuits are assigned to
specific bits in a 32-byte interface memory.
RS3
RS2
RSI
RSO
-CSO
CSI
READ
WRITE
IRQ
HARDWARE SUPERVISORY CIRCUITS
Signal names and descriptions of the hardware supervisory
circuits, including the microprocessor interface, are listed in
the R96FAX Hardware Supervisory Circuits table, The microprocessor interface is designed to be 'directly compatible with
an 8080 microprocessor. With the addition of a few external logic
gates, it can be made compatible with 6500, 6800, or 68000
microprocessors.
1/0
,Pin No.
DCLK
XCLK
RTS
CTS
TXD
RXD
RLSD
I
I
I
I
CABS1
CABS2
I/O
14,39
3,4
26
37
36
,Description
110
110
1/0
110
110
110
110
110
9
31
15
28
23
29
I
I
I
I
30
8
27
10
I
I
I
I
6
18
1
2
32
Chip Select for Bank 0
Chip Select for Bank 1
Read Enable
Write Enable
Interrupt Request
13
22
19
17
20
21
16
Data Clock
External Clock for Group II
Request-to-Send
Clear-to-Send
Transmitter Data
Receiver Data
Received Line Signal Detector
0
7
5
Data Bus (8 Bits)
Register Select (4 Bits)
0
I
I
0
I
0
0
D. CABLE EQUALIZER:
Description
A. OVERHEAD:
GND
+5 volls
+ 12 volts
-12 volts
POR
Pin No.
C. V.24 INTERFACE:
R96FAX Hardware SupervisorY Circuits
Name
1/0
B. MICROPROCESSOR INTERFACE:
Ground
+ 5 volt supply
+ 12 volt supply
-12 volt supply
Power-an-reset "
I
I
33
34
Cable Select 1
Cable Select 2
38
Transmitter Analog Output
Receiver Analog Input
Auxiliary Analog Input
E. ANALOG SIGNALS:
TXA
RXA
AUXIN
10-6
0
I.
40
I
35
R96FAX
9600 bps Facsimile Modem
R96FAX Interface Memory
(HEX)
Reg No.
Bank
F
E
0
0
0
0
0
0
0
0
0
0
0
0
Symbol
Min
CSi, RSi setul!..!!!!!e prior
to Read or Write
TCS
Data 'Access time after Read
TDA
Data hold time after Reile!
TDH
10
CSi, RSi hold time altef.
Read or Write
Max
Units
30
-
'NS
-
140
NS
50
NS
-
NS
TCH
10
Write data setup time
TWOS
75
Write data hold time
TWDH
10
-
NS
TWR
75
-
NS
Write strobe pulse width
9
8
7
6
5
4
3
0
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Critical Timing Requirements
Characteristic
C
B
A
ci
0
0
Microprocessor Interface Timing Diagram
0
,
F
E
0
C
B
A
9
8
7
6
5
4
3
2
1
0
DeScription
Diagnostic Control
Handshake Status
Do Not Use
Do Not Use
Do Not Use
Do Not Use
Do Not Use
Do Not Use
Do Not Use
Do Not Use
Option
Configuration
Diagnostic Data Real
Diagnostic Data Real
Diagnostic Imaginary
Diagnostic Imaginary
Transfer Register
MSB's; FREOM
LSB's;' FREOL
MSB's
LSB's; Data
'Diagnostic control
Handshake Status
RAM Write Control
Gil AGe Slew'Rate Select
Tone Detect Indicator
Do Not Use
Do Not Use
Do Not Use
Receiver Status
Do Not Use
Receiver Statlls
Receiver Status
Diagnostic Data Re,al MSB's
Diagnostic Data Real LSB's
Diagnostic Imaginary MSB's
DiagnoStic linaginary LSB's' ,.
NS
SOFTWARE SUPERVISORY CIRCUITS
The operation of the R96FAX is affected bya number of software control inputs. These inputs are written into registers within
the modem via a microprocessor bus under external control.
Modem operation is monitored by various software flags that are
read from modem registers using the same microprocessor bus.
The functions of all modem 1/0 registers are listed in the R96FAX
Interface Memory table and are defined as follows:
Cable Equalizer Selection
CABS 2
CABS 1
Length of 0.4mm Diameter Cable,
0
0
1
1
0
1
0
1
0.0
1.8 km
3.6 km
7.2 km
INTERFACE MEMORY
CONFIGURATION REGISTER
The R96FAX has two banks of 16 registers to which anexternal (host) microprocessor has access. Although these registers
are within the modem, they may be addressed as part of the
host processor's memory space. The host may read data out
of or write data into these registers. These registers are referred
to as interface memory. SeeR96FAX Interface Memory table.
Registers in bank 0 update at the modem sample rate (9600 bps).
Registers in bank 1 update at the selected bauq rate.
The host processor configures ,the R96FAX by writing a control
byte Into the configuration register (0:4) in its interface memory
space as shown in the following table:
the
When information in these registers is being discussed,
format
Y:Z:Q is used. The bankis specified by yeO or 1), the register
by Z(D-F), and the bit by 0(D-7. 0 .. LSB). A bit is considered to
be "on" when set to a 1.
10-7
lID"I'
R96FAX
9600 bps Facsimile Modem
Receiver· data is preserited to the RXD output at a rate of
10368 samples per second. The user should strobe the data
on the rising edge of the data clock (DCLK). A logical 1 level
(high voltage) represents white. A logical 0 level (low voltage)
represents black.
Definition of Configuration Terms:
TNXMT.
G2.
FSK.
V29.
V27.
DR3.
DR2.
DRt.
Tone Transmit
Group" Facsimile
300 bps FSK/Tone Detection
V.29 Configuration
V.27 Configuration
Selects 9600 bpslV.29
Selects 7200 bpslV.29,
Selects 4800 bpslV.27
Selects 4800 bpslV.29,
Selects 2400 bpslV.27.
5. Tone Transmit. In this configuration, activating signal RTS
causes the modem to transmit a tone at a single frequency
specified by trye user; Two registers in the host inierface
memory spac\3 contain the frequency code. The most significant bits are specified in the FREOM register (0:3). The ~st
significant bits are specified in the FREOL register (0:2). The
least signilicant bit represents 0.146484 Hz ± 0.01 %. The
frequency generated is: I = 0.146484 (256 FREOM +
FREOL) Hz ±0.01%.
Control words for the five configurations are given in hexadecimal format in' the following table:
Hexadecimal frequency numbers (FREOM, FREOL) for commonly generated tones are shown in the following chart:
Configuration Control Words
No.
1
Config~ration
Configuration Word (HEX)
V.299600
V.297200
V.294800
14
12
11
V.274800
V.272400
OA
3
FSK
20
4
Group II
40
5
Tone Transmit
80
2
Commonly Generated Tones
Frequency
FREQM
FREQL
462 Hz
.1100 Hz
1650 Hz
185Q.·Hz
2100 Hz
OC
lD
2C
31
52
09
38
55
00
55
00
OPTION REGISTER
Definition of Configurations:
The host processor conveys option information to the R96FAX
by writing a control byte into the Option Register (0:5) in its
memory space as shown in the table below:
1. V.29. When any of the V.29 configurations. has been
selected, the modem operates as specified in CCID Recommendation V.29.
2. V.27. When any of the V.27 configurations has been
selected, the modem operates as specified in CCITT Recommendation V.27 ter.
3. FSK. . The modem operates as a. CCITT T.30 compatible
300 bps FSK modem having characteristics of the CCITT
V.21 channel 2 modulation system.
Definition of Option Terms:
RTS.
TOIS.
EDIS.
SQEXT.
T2.
LRTH.
4. Group II. The modem operates as a CCID T.3 compatible
AM modem. This permits transmission to and reception from
Group" fac.simile apparatus. A carrierjrequency of 2100 Hz
is used. A white signal is transmitted as maximum carrier.
A black signal is transmitted as no carrier. The phase of the
carrier representing white is reversed after each transition
through black.
Request-to-Send
Training Disable
Echo Protector Disable
Squelch Extend
T/2 Equalizer
Lower Receive Threshold
Definition of Options:
1. Request-to-Send. The R96FAX operates in the receive state
until RTS (0:517) is turned.con. At that time the modem
switches to the transmit state and remains there until RTS
is turned off, and the turn-olfsequence has been completed.
When in the receive state, the R96FAX recovers the carrier
of the remote transmitting modem to perform a coherent
demodulation of the incoming signal. This allows a baseband
of 3400 Hz to be recovered. The recovered baseband signal
is made available on the microprocessor bus as diagnostic
data.
2. Training Disable. When the TDIS bit (0:5:6) is on in the
receive state, this bit prevents the modem from entering the
training ph;:tse. When turneaon prior to RTS going on, this
bit prevents the generation of a training sequence at the start
of transmission.
The baseband signal is converted to black or white by comparing the received signal level with a preset threshold
number. This number may be changed by the user.
10·8
9600 bps Facsimile ·Modem
R96FAX
STATUS BITS
3. Echo Protector Disable. If the EDIS bit (0:5:3) is on, an
unmodulated carrier is transmitted for 185 to 200 ms followed
by 20 to 25 ms of no transmitted energy at the beginning of
the training sequence. This option is available in both the V.27
and V.29 configurations although it is not specified in the
celn V.29 Recommendation.
The status bits are defined in the following table: .'
status Bits
Name
1.0. No.
Description
DAO
O:E:O
Data Available (Zero) goes. on when the
R96FAX writes data il)to registered 0:0. It is
reset when the hO$! processor reads or writes
register 0:0. DAO is used in the parallel' mooe
and also for diagnostic data retrieval.
lAO
0:E:7
Interrupt Active (Zero) is on when bank 0 is
causing IROP to be active.
FED
1:5:6
Fa$! Energy Detect, when off, indicates energy
on the receiver Input. Not used for Group II.
P2DET
1:4:2
When off, P2DET indicates a P2 sequence has
been detected. Sets to 1 at start of PN
,sequence.
PNDET
1:7:6
When off, PNDET indicates a PN ~quence .
has been detected. Sets to 1 at ·end of PN
sequence.
CDET
1:7:0
When off, CDET indicates that energy is being
detected' and a training sequence is not
present. :Goes off at start of data state.
OA1
I:E:O
Data Availabie (One)' goes on when the
R96FAx wrttesdata into regi$!er 1:0. It is reset
when the host processor reads or writes
register 1:0.
Interrupt Active (One) is on, when bank 1 is
causing IRO to be active. '
.'
4. Squelch Extend. When ali, the SQEXT bit (0:5:2) inhibits
reception of signals for 130 ms after RTS is turned off.
5. T/2Equalizer. If the T/2 equalizer bit (0:5:1) is off, an adaptive equalizer with one tap per baud is used. If the Ti2 bit
is on, an adaptive equaHzer with two taps per baud is used.
6. Lower Receive Threshold. When on, the LRTH bit (0:5:0)
lowers the receiver turn-on threshold from -43 dBm to
-47 dBm.
DISCRETE CONTROL BITS
The discrete control bits are defined i'n the following table:
Discrete Control Bits
Nam~
I.D, No.
Description
IAl
1:E:7
PDM
Il:F:7
When on, 'PDM places tlie R96FAX in the
parallel nl9de and inhibits bank 0 diagnostics.
F3
1:8:7
SETUP
0:E:3
When on, SETUP causes, Ihe R96FAX to
reconfigure to the control. word in the .configuratio.~,registerandto assume .the options
s'peci,fi!!d for equalizer (0:5:1) and threshold
(0:5:0). Resets automatically. Note: Bit 0:4:0
t~rough 0:4:4 should only change state while
RIS is off to prevent 'errors in transmission. '
F2
1:B:6
Ft
1:8:5
i
lEO
RAMW
J3L
0:£::2
',I:D:O
I:D:4
DIAONOSTIC CAPABILITIES
When on, Interrupt Enable (Zero), causes the
IRO output to be low when the DAO bit
(0:£:0) is on.
The R96FAX provides the user with access to much of the data
stored in the modem's memories. This data is a useful tool in
performing certain diagnostic functions.
RAMW; when on, causes the 16-bit word' in
locations 1:0' and 1: 1 to be written' into RAM
at the location sp~ified in the diagnostic control register (1 :F).
HARDWARE DIAGNOSTIC CIRCUITS
J!!panese 3 ,link, when on, selects this
standard for link amplitude equalizer; when 9ft
selects U.S. survey long. .
.
RLE
I:D:5
Receiver link equalizer, when on, enables the
link amplitude equalizer in the receiver.
TLE
I:D:6
Transmitter link equalizer, when on, enables
the li,nk amplitude equaJize~ in the transmitter.
G2FGC
1:0;0
G2FGC, when on, selects a fast AGC rate in
Group II.
lEI
I:E;2
' When on, Interrupt Enable (One) causes the
IRO output to be low when the DAI bit
(1 :E:O) is on.
When on, these bitS indicate reception of their
respective tonal frequencies if the I'i!i6FAX is'
configured in FSK. Default frequencills are:
F3 =,462 Hz, F2 = 1100 Hz, and Fl =
2100Hz,.
'
Signal names and descriptions of the hardware diagnostic
circuits are given in the table below:
Hardware Diagnostic Circuits
Name,
EYEX
EYEY
EYECLK
EYESYNC
10-9
1/0
Pin No.
0
0
0
0
24
25
11
12'
Description
Eye Pattern
Eye Pattern
Eye Pattern
Eye Pattern
Signal
Data - X Axis
Data - Y Axis
Clock
Synchronizing
R96FAX
9600 bps Facsimile Modem
Eye Pattern Generation - The four hardware diagnostic circuits.
allow the user to generate and display an eye pattern: Circuits
EYEX and EYEY serially present eye pattern data for the horizontal and vertical display inputs respectively. The a-bit data words
are shifted out most significant bit first, clocked by the rising
edge of the EYECLK output. The EYESYNC output is provided
for word synchronization. The falling edge of EYESYNC may
be used to transfer the a-bit word from the shift register to a
holding register. Digital" to analog conversion can then be performed for driving the X and Y inputs of an oscilloscope.
RAM Access Codes (Write)
SOFTWARE DIAGNOSTIC CIRCUITS
Two diagnostic control registe~s are provided in the interface
memory to allow user access to various RAM locations within
the modem. The access code stored in bank 0 (O:F) selects the
source of data for the real and imaginary diagnostic data
registers in bank 0 (0:0 through 0:3). Similarly the access code
stored in bank 1 (1 :F) selects the source of data for registers
1:0 through 1:3. Bank 1 also provides the user with the ability
to store the contents of registers 1:0 and 1: 1 in the RAM location specifi.ed in register 1:F:Writing is performed by turning on
control bit RAMW (1 :13:0). Reading is performed by handshaking with the appropriate Data Available status bit. The eight most
significant bits of real and imaginary data from bank 1 are alsO
presented serially on EYEX and EYEY respectively.
Bank
Function
Access
Data
Type
1
Gil Black/White Threshold
Fl AID
Fl Bl1
Fl B12
Fl ADO
Fl BOI
Fl B02
F2 AID
F2 Bll
F2 B12
F2 ADO
F2 BOI
F2 B02
1"3 Al0
F3 Bl1
F3 B12
F3 ADO
F3 BOI
F3 B02
Fl A20
Fl B21
F2 A20
F2 B21
F3 A20
F3 B21
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
B7
B8
B9
BA
BB
BC
Imaginary
Imaginary
Imaginary
Ima9inary
Imaginary
Imaginary
Imaginary
Imaginary
Imaginary
Imaginary
Imaginary
Imaginary
Imaginary
Imaginary
Imaginary
Imaginary
Imaginary
Imaginary
Imaginary
Real
Real
Real
Real
Real
Real
POWER·ON INITIALIZATION
When power is applied to the R96FAX. a period of 100 to 300 ms
is required for initialization. The power-on-reset signal (POR)
remains low during the initialization period. After the low to high
transition of POR, the modem is ready to be configured.
RAM ACCESS CODES (READ)
The RAM Access Codes defined in the table below allow the
host processor to read diagnostic information within the R96FAX.
At POR time the modem defaults to the following configuration:
V.29/9600 bps, T/2 equalizer, serial mode, training enabled, echo
protector disable tone, no extended squelch, higher receive
threshold, interrupts disabled, no link equalizer, RAM access
codes 00.
RAM Access Codes (Read)
Bank
0
1
Function
Received Signal Samples
Demodulator Output
Low Pass Filter Output
One Baud Energy
AGC Gain Word - MSB's
AGC Gain Word - LSB's
Equalizer Input
Equalizer Tap Coefficients
Unrotated Equalizer Output
Rotated Equalizer Output
(Received Point-Eye Pattern)
Decision Points (Ideal)
Error Vector
Rotation Angle
Frequency Correction - MSB's
Frequency Correction - LSB's
Group II Base Band Signal
Group II Threshold
EQM
Access
Data Type
40
42
54
01
01
Real
Complex
Complex
Imaginary
Real
Imaginary
40
01-20
22
22
Complex
Complex
Complex
Complex
62
63
00
28
28
4B
2A
2B
Complex
Complex
Imaginary
Real
Imaginary
Real
Imaginary
Real
04
POR can also be used to initialize the users's host processor.
It may be connected to a user supplied power-on-reset signal
in a wire-or configuration.
PERFORMANCE
Whether functioning as a V.27 ter or V.29 type modem, the
R96FAX provides the user with unexcelled high performance.
Bit Error Rates - The Bit Error Rate (BER) performance of the
modem is specified for a test configuration conforming to that
specified in CCITT Recommendation V.S6, except with regard
to the placement of the filter used to bandlimit the white noise
source. Bit error rates are measured ata received line signal
level of -40 dBm as illustrated.
Phase Jitter -At 2400 bps, the modem exhibits a bit error rate
of 10-6 or less with a signal-to-noise ratio of 12.5 dB in the
presence of 15° peak-to-peak phase jitter at 150 Hz or with a
signal-to-noise ratio of 15 dB in the presence of 30° peak-topeak phase jitter at 120 Hz (scrambler inserted).
RAM ACCESS CODES (WRITE)
At 4800 bps (V.27 ter), the modem exhibits a bit error rate of
10-6 or less with a signal-to-noise ratio of 19 dB in the presence
of 15° peak-to-peak phase jitter at 60 Hz.
The RAM access codes defined in the following table allow the
host processor to write parameter information into the R96FAX.
10-10
R96FAX
9600 bps Facsimile Modem
INTERFACE CIRCUIT CHARACTERISTICS
At 9600 bps, the. modem exhibits a bit error. rate of 10-6 or less
with a signal-to-noise ratio of 23 dB in the presence of 10° peakto-peak phase jitter at 60 Hz. The modem exhibits a bit error
rate of 10-5 or less with a signal-to-noise ratio of 23 dB in the
presenoe of 60° peak-to-peak phase jitter at 30 Hz.
DIGITAL INTERFACE CIRCUITS
4800 BPS V.27 TER
2400 BPS V.27 TER
\ 0 0 BPS V.29
300
BP~~~O BPS\,.29
Digital Input Characteristics
9600 BPS V.29
10- 3
1\
Input Logic State
Allowed Input Voltage Levels
Low
High
O.OV to +0.8V at-0.01 mA
+2.0V to +5.0V at +0.1 mA
Notes
1. The digital inputs are directly TTUCMOS compatible. The
capacitive loading on each input is 25 pF (maximum).
2. Positive current is defined as current into the node.
Digital Output Characteristics
10-'
.S!
~
0
~
Input Logic State
Allowed Input Voltage Levels
Low
High
O.OV to +O.4V at + 1.6 mA
+ 2.4V to + 5.0V at -40 pA
Notes
1. The digital outputs are directly CMOS and TTL compatible.
2. Positive current is defined as current into the node.
-
iii
10- 5
ANALOG INTERFACE CIRCUITS
10
,
6
0
2
,
4
6
8 10 12 14 16 18
SIGNAL TO NOISE RATIO (dB)
20
Transmitter Output - The transmitter output is a low
impedance operational amplifier output. To match to 6000, an
external series resistor is required.
22 24
Receiver Input ohm±5%.
Typical Bit Error Rate Performance
NOISE
SOURCE
GR1381
50 KHZ BW
MODEM
TRANSMITTER
ENGINEERING
MODEM
CONSOLE
LINE
SIMULATOR
IMPAIRMENT
SOURCE
BRADLEY 2A
The receiver input impedance is 63.4 K
ATTENUATOR 1---'-----.
HP 3500
LEVEL
METER
HP 3552A
ATTENUATOR
HP 3500
MODEM
RECEIVER
NOTE
Signal and noise are measured with 3 KHz flat weighting.
BER Performance Test Sel-up
10-11
ENGINEERING
MODEM
CONSOLE
9600 bps Facsimile Modem
R96FAX
F3. ==1l
rrl
- I4
Auxiliary Analog Inpu~ - The auxiliary analog input (AUXIN)
allows access to the transmitter for the purpose of interfacing
with user provided equipment. Because this is a sampled data
input signals above 4800 Hz will cause afiasing errors. The input
impedance is 1K ohm and the gain to transmitter output is OdB.
I
1.
39 ....................................... 1
===========,
40 ........................................ 2
937
3.675
.
.~
I~IAHOLE
'[i:______ __
2.76
I
.265
I
.4~; ~
= = = = = ,
Header Pin Assignment
~~
PLCS
I
I
!
I
.407
-£40
PIN RIGHT
ANGLE HEADER
Printed Circuit Board Dimensions
R96FAX SPECIFICATIONS
Power
Voltage
Tolerance
Current (Typical)
Current (Max)
+5 Vdc
+ 12 Vdc
±5%
±5%
-12 Vdc
±5~/o
300 rnA
SmA
30 mA
<500
<10
ecified by Part ,68 of the FCC's Rules, and typically exceed
the require':'!ents of foreign teleph~e rfJgulatory'bodies.
1800
1700
TONE GENERATION
Under control of the host processor, the R9SDP can generate
voice band tones up to 48(10 Hz witl) a reSolution of 0.15 Hz and
an accuracy of 0.01%. Tones over 3000 Hz are attenuated.
SIGNALING AND DATA RATES
SCRA,MBLERIDESCRAMJ!I"f!~
The signaling and ,data rates for the R96DP are defined in the
'
,
table below:
The R96DP incorporates a self-synchronizing scramblerl
descrambler. This facility is in accordance with either V.27bisJter
or V,29 depending on the selected configuration.
Signaling/Data Rates"
"
Parameter
Specification
RECEIVED SIGNAL
FREQUENCY TOLERANCE
(±'O.O1%)
"
Signaling Rate:
Data Rate:
2400 Baud
9eOO bps,
,
7260 bp~,
) Tl)e receiver circuit of the R96DP can adapt to received
frequency error of up to ± 10Hz with less than 0.2 dB degradation in BER performance.
4800 bps
Signaling Rate:
Data Rate:
,1600 Baud
4800 bps
Signaling Rate:
Data Rate:
1200 Baud
2400 bps
RECEIVE LEVEL
The receiver circuit of the modem satisfies all specified performance requirements for received line signal levels from 0 dBm
to -:43dBm. Tt\e. received line signal level is measured at the
receiver analog input (RXA).
DATA ENCODING
At 2400 baud, the data stream is encod911 per CCIlT V.29. At
9600 bps, the data stream is divided in groups of four-bits (quadbits) forming a 16-point structure. At 7200 bps, the data stream
is divided into three bits (tribits) forming an 8-pointstructure.
At 4800 bps, the data stream is divided into two bils (dilli!s) ,
forming a 4-point structure.
, RECEIVE TIMING
(he R96DP provides a data derived Receive Data Clock
(RDCLK) output in the form of a squarewave. The low to high
transitions of t~is output coincide with the centers of received
data bits: The timing recovery circuit is capable of trac~ing a
,,± 0'.01 Ofo, frequency error in the aSSOCiated transmit timing
source .. "
At 1600 baud, the 4800 bps data stream is e,ncoded into tribits
per CCITI V.27 bislter.
TRANSMIT LEVEL
At ,1200 baud, the 2400 bps data stream is encoded into dibits
per CCITI V.27bis/ter.
'
'
The transmitter output level is accurate to ± 1.0 dB and is programmable from - 1.0 dBm to -15.0 dBm in 2 dB steps.
EQUALIZERS
The R96DP provides equalization function~Jhat improve performance when operating over low quality lines.
TRANSMIT TIMING
Cable Equalizers - Selectable compromise cable equalizers
in the receiverand transmitter are provided to optimize performance over dlff~rent lengths ,of non-loaded cable of 0.4 mm
c;liameter. . - '
,
The R96DP provides a Transmit Data Clock (TDCLK) output with
the following characteristics:
1; Fre,quency. Selected,data rate of 9600,7200, 4800. or
2400 Hz (±0.01%).
2. Duty Cycle. 50% ± 1%
10-14
R96DP
9600 bps Data Pump Modem
Inpllt data presented on TXD is sampled by the R96DP at the
low to high transition of TDCLK. Data on TXD must be stable
for at least one microsecond prior to the rising edge of TDCLK
and remain stable for at ,least one microsecond after the rising
edge of TDCLK.
The time between the on-to-off transition of RTSand the on-tooff transition of CTS in the data state is a maximum of 2 baud
times for all configurations.
RECEIVED LINE SIGNAL DETECTOR (RLSD)
TURN·ON SEQUENCE
For either V.27 bis/ter or V.29, RLSD turns on at the end of the
training sequence. If training is not detected at the receiver, the
RLSD off-to-on response time is 15 ± 10 ms. The RLSD
on-to-off response'time for V.27 is 10 ±5 ms and for V.29 is
30 ± 9 ms. Response times are measured with a signal at least
3 dB above the actual RLSD on threshold or at least 5 dB ,below
the actual RLSD off threshold.
A total of 14 selectable turn-on sequences can be generated
as defined in the following table:
The RLSD on-to-off response time ensures that all valid data
bits have appeared on RXD.
EXTERNAL TRANSMIT CLOCK
The transmitter data clock (TDCLK) can be phase locked to a
signal on input XTCLK. This input signal mu'st equal the desired
data rate to ± 0.01 % with a duty cycle of 50% ± 20%.
Turn·On Sequences
No.
V.29
V.27 bis/ter
CTS
Response Time
(milliseconds)
1 9600 bps
2 7200 bps
3 4800 bps
4800 bps long
4
2400 bps long
5
4800 bps snort
6
2400 bps short
7
253
253
253
708
943
50
67
8 9600 bps
9 7200 bps
10 4800 bps
4800 bps long
11
2400 bps long
12
4800 bps short
13
14
2400 bps short
458
458
458
913
1148
255
Comments
Preceded by
Echo Suppressor
Disable Tone
for lines using
echo suppressors'
. 272
• For short echo protect tone, subtract 155 ms from values of
CTS response time.
Four threshold options are provided:
1, Greater than - 43 dBm (RLSD on)
Less than -48 dBm (RLSD oft)
2. Greater than -' 33 dBm (RLSD on)
Less than - 38 dBm (RLSD off)
3, Greater than - 26 dBm (RLSD on)
Less than - 31 dBm (RLSD off)
4, Greater than -16 dBm (RLSD on)
Less than - 21 dBm (RLSD off)
NOTE
Performance may be at a reduced level when the received
signal is less than - 43 dBm.
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-to-off transition I~vels. The threshold levels and
hysteresis action are measured with an unmodulated carrier
signal applied to the receiver's audio input (RXA) .
MODES OF OPERATION
The R96DP is capable of being operated in either a serial or
a parallel mode of operation.
TURN·OFF SEQUENCE
For V.27 ter, the turn-off sequence consists of approximately
10 ms of remaining data and scrambled ones at 1200 baud or
approximately 7 ms of data and scrambled ones at 1600 baud
followed by a 20 ms period of no transmitted energy. For V.29,
the turn-off sequence consists of approximately 5 ms of remaining data and scrambled 1 's followed by a 20 ms period of no
transmitted' energy,
CLAMPING
Received Data (RXD) is clamped to a cOnstant mark (one)
whenever the Received Line Signal Detector (RLSD) is off.
SERIAL MODE
The serial mode uses standard V,24 (RS-232-C compatible)
signals to transfer channel data. An optional USRT device
(shown in the Functional Interconnect Diagram) illustrates this
capability,
PARALLEL MODE
The R96DP has the capability of transferring channel data up
to eight bits at a time via the microprocessor bus.
RESPONSE TIMES OF CLEAR·TO·SEND (CTS)
MODE SELECTION
The time between the off-to-on transition of Request-To-Send
(RTS) and the off-to-on transition of CTS is dictated by the length
of the training sequence and the echo suppressor disable tone,
if used, ,These times are listed in the Tllrn-On Sequences table.
If training is not enabled RTS/CTS delay is less than 1 ms.
Selection of either the serial or parallel mode of operation is by
means of a control bit. To enable the parallel mode, the control
bit must be set to a 1. The modem automatically defaults to the
serial mode at power-on. In either mode the R96DP is configured
by the host processor via the microprocessor bus.
,iIi]'
, '
I
R96DP
9600 bps Qata Pump
r-
<.
<1r
1.
I
l
i,
,.
!
"
FiTS
,.,
,CTS
.r.
.. . .
Q'
"ScOPE'
~
TXD
TDCLK
EVEX
iitSl)
"...r..'
r.
~
RXD
.r-
RDCLK
J
,
1---~~l,
I
',~,
~
+5V
HOST
PROCESSOR
(DTE)
"
DATA BUS (8)
t
TXA
Di
RSI '
•
. '.
INTERFACE 4 - -
RXA
'r--~
(
+5
",
POR,' .....
'IRQ·
;=;')
"
-.}
LINE
.
DECODER r,...CS (3)'", -" CSI
('"'-~
.'
"""-'"'
ADDReSS BUS (4)
"I
POWER"
SUPPLY
GND
-12V
READ
r-
"
+12V
MODEM
"',
WRITE
k
",
EVE
~TTEF!N
ENERATOR
EVESVNC
EVECLK
TBCLK';::::
RsCLK,.,
:.I
"
tv
xt '
""'xtCLK
I;
.,
;.
'L,...
~
,.USRT
(OPTIONAL),"'
,I
1
1
1
-
-a-'
I'
I
Modem.,
".,;'
AUXIN
.:':.
,Y
,
TELEPHbNE
LINE
'.
"
'-.;'
!
I"';'
~ .,.
A96DP Functional Interconnect Diagram,
tNT£RFACE CRITERIA
R98DP Hardware Supervisory Circuits (Cont.)
Name
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins in a
64-pin DIN connector. Software circuitl1 are assigned to specific
bits in a 48-byte interface memory.
HARDWARE SUPERVISORY CIRCUITS
Signal names and descriptions of the hardware superviSOry
circuits, including the microprcicessor interface, are !i$ted in
the R96DP Hardware SuperVisory Circuits table .. The microproces~r interface is design$d to be direetlycompatible with
an 8080 microprocessor. With the addition of a few extemallogic
gates, it can be made compatible with 6500, 6800, or 68000
microprocessors.
110
Pin No.
POR
I/O
I/O
I/O
4A
DO
1/0
5C
,CSO
CSI
CS2
READ
WRITE
IRQ
Description
'C}
2C
I/O
I/O
2A
3A
4C
1/0
"
1A
110
I
I
I
I
I
I
I
I
I
0
Description
RDCLK
TDCLK
XTCLK
RTS
CTS
TXD
RXD,
RLSO
Analog Ground
I
31C,~C
3C,8C,5A,10A
Digital Ground
I
I. 19C,23C,2BC,30C + 5 volt supply
+ 12 volt supply
I
1SA
_12 volt supply,
I
12A
Power-on-reset
13C
110
1o,16
a
0
I
I
0
I
0
'0
Data Bus (8 Bits)
6C }
6A
7C
7A
Register Select (4 Bits)
10C
9C
9A
12C
l1A
l1C
Chip Select for Bank 0
Chip Select for Bank 1,
Chip Select for Bank 2
Read Enable
Write Enable
Interrupt Request
C. V.24 I!IITERFACE:
A. OVERHEAD:
AGND
DGND
+51101ts
+'12 volts
-12 volts
Pin No.
07
06
05
04
03
02
01
RS3
RS2
RS1
RSO
R98DP Hardware Supervisory' Circuits
'Name
I/O
B. MICROPROCESSOR INTERFACE:
21A
23A
22A
25A
25C
24C
22C
24A
"
Receive Data Clock
Transmit Data Clock
External Transmit Clock
Request-to-Send
Clear-to-Send
Transmitter ,Data
ReGeiver Data
ReCeived Line Sigrial Detector'
.,
R9eDP
9600 bps Data Pump Mfdem
R96DP tlardware Supervisory Circuits (Cont..)
DellCriptlon
1.110 I Pin No.
registers are collectively referred'to as interface memory.,See
R96DP Interface Memory table; Access to the three banks of
registers (bank 0; bank 1 and bank. 2) is enabled by the Chip.
Select signals CSO, CSI and CS2 respectively. Four Register
.Select signals (RSO, RS1, RS2, and RS3 are provided to address
an individual register within an enabled bank. Registers in bank 1
operate at the sample rate of 9600 samples per .second,
Registers in banks 0 and 2 operate at the selected baud rate.
Name
.
D. AN.CllIJ'RY CIRCUITS:
RBCll<
TBell<
IgI
E. ANALOG SIGNALS:
TXA
RXA
AUXIN
I: I
Receiver Baud Clock
Transmitter Baud Clock
26A
27C
31A
32A
30A
I
Transmitter Analog 'Output
Receiver Analog Input·
Auxiliary Analog Input
R96DP Interface MemorY
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Mlcroprocel\SOrlnterface Timing Diagram
Critical Timing- Requirements
Sym~1 . Min
., Characteristic
Max
Units
CSi, RSi "etueJ!.!!!.e priqf,
to "ead or Wrile
TCS
IlseC
TDh.
.30
',' ' -
-
Data access time after Read
140
nsec
TDH
10
50
. (lsec
TC,",
10
-
Write data setup time
TWOS
·75
Writedata'hold time
TWDH
10
TWR
75
!
Data hold time after ,Read
..CSi, .FiSi hold time after
Rea!! or Write'
.Write strobe pulse width
..
.-
nsec
nsec
nsec
7
6
5
4
3
2
1
C
B
A
9
8
7
6
5
4
3
2.
1
0
F
E
0
C
B
A
2
6
5
4
2
1:>0 NOI Use
0
2
2
2
2
2
g.8
7
2
3
2
1
2
0
2
10-17
8
0
2
TheR96DP has three banks of 16 input/output (110) registers
.to which an external (host) microprtieessor has acCess. Although
these 110 registers are within the modem, they may bead!lressed
as part of the host processor's. memory space. These. lib
0
F
E
2
INTERFACE. MEMORY
Do Not Use
Tranl;lmitter Hal1dshake .
Do Not Use
Do Not Use
Do NOt Use
Do Not Use
DO NOt Use
Do Not Use
Transmitter Option
Transmitter Configuration
Equalizer
Loop/level
FREOM
FREOl
Do I\IOt Use
Tr!losmitter Dal!,
C
B
A
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
i
DellCriptlon
F
E
O·
2
2
2
nsec..
(HEX)
Reg No.
.'
Receiver Sample Handshakit
Do Not Use
Do Not Use
Aeceiver Baud Status
()o Not Use
Receiver Sample Status 2
Receiver Sample Status 1
ReceiVer Option
RecelverConflgliration
Diagnostic COnlrol XS
Diagnostic Control YS
. Diagnostic Data XSM
Diag!lqstic Data XSl.
Diagnos~c !;lata YSM
DiagnostiC Data YSl;
Receiver Data
Do Not \J~
Receiver Baud Handshake
Do NOt Use
Do Not Use
Do Not Us!,
. Do.Not Use
Do Not Use
Do Not
Do Not Use
Do Not Use
Diagnostic Control XB
Diagnostic Conlrol YB
Diagnostic Data XBM
Diagnostic Data XBl'
Diagnostlo Data'YBM
Diagnostic.pata, YBl
Use
,.t",
.R96OP'
9600 bps Data .Pump Modem
D~finitionof
WHen information in theSe IIO,registers,isbeing discussed, the,
format Y:Z:Q isils$q,The bank iSsp8cified byY(002),,thfJ register
,b¥ ~O-Fji~ndthe bit by 0(0-7, 0 .. LSBj., A bitis'GOnsidered. to
be',''on'' when sSt to a1. '
.., .
I.V,29, .\Nhen any of the V,~9 cor1figunitibn~
tieen
selected, the modem operates as specified in ccln recom.
"
mendation V:29.'
'Ilave
2, V.27. When, any Of the V.27 configurationshavebeEIO
selected, the m\>dem, operates as specified (n
recp,mmendalion V,27.
$OFTWARE SUPERVISORY CIRCUI:r~
,:','"
, '.
.',
e
•
'.J,..
~'"
:
.;-,', j
cciu
: ':
The operation of t/'le R96DP is affected by a number of softWare
" control inputs. These inputs are writtenintOregisters within the
. mOdem via a microprocessor bus under external control,.B.its
designated bY.anX are "DolI'tCarlil" 'inP4ts that can be set to
eith~1 or O. MOdem,operatlon'is nionitorEld by vaf.ioUj!software
flags that are read frOm modem regisffiJrilusing tile same
micrQprQC$$SOrbus/Bitsdesignated by
X are "undefil1ed"
'.outputs that rnay!le eitI1er 1 or 0, The functio(lsof all modern
I/O r89istersarellstedin tbeR96.DP Interlaee MElmpry table and
are defined as folloWs: " ' ,
'
"
TRAN~M'TTER OPTION
The host:p[ocessb~ 90n\l~Ys OptiOn'ii1fOrmationto t~ transmit;
ter. by writing a control;byie"jnto the. Option Registef.{O:7) in its,
interface memory spa~:as shown in the table below:'
.
The host processor confi~ur.El~the R96DP transmitter by writing
,8,l:;ontrol bytelnf9the transrliittercQl1fi!lur~Jipn register (9:6) in
i~ r~terfaCeJ1,e!110ry space,~ sho~n' in the follOwing table:
I
.• '
Di1ini~on
RTS:
. ITD/S:
SOlS:
MHLD:
EDIS:
TPOM:
XCEN:
SEDT:
" Definition of Transmitter C,onflguration Terms:
TQneTransmit,,;,
'
Tran$mitt~r ,Lql1g Training Sequence
Transmitter, Y'.29, Configuration
Tran$rnitterOata Rate 3 (Select$ 9600 bpsN.29)
TranSmitter DataRate2(S~lects 7200 I:>psN,29.
and Seleots 4800 bpSN.27)
Transmitter Data Rate t (Selects 4800 bpsN.29,
and Selectlil 24()()~p~.27) ,
.I
V,29 9sdo
V,29 720(f
V,294800
14
12
11
2
V.27.~BOO Long
22
21
02
\(.212400 Long
V,27 4,SQO,Short .
IV:2'I 2409, ~!lr1
3
Tone -Transn\ij
Scrambler Disable
Mark Hold
Echo ..Protector Disable
Transmitter Parallel Data Mode
External Clock Enable
Short I:cllo Protection Disable Tone'
2. Transmitter Train(ng Disable.,. When theTTD1S bit'(0:7:6) is
on, t/'le tranSmitter does npl generate a trainhig sequence
at fh~start oftransmission.
3. Scrambler Disable. When the SDIS bit «():7:5) is on, ,the,
transmitter scrambler circuit il! removed froni the data path.
Conflgutatlon BYtes (HEX)
1
. Request-to-Send
'TransmitterTrainingbisabl~
1;, Request:to-Send. T"e.R~~DP ~~ginS a tr~nsmif$equence
when the RTS bit (0:7:7) is tumed on and contlnueatransmitc
ling until RTS j~ turned off and the turn-off sequence has bElen
completed. This input bit parallels the operation olthe hardware RTS control"input:
Conflguratlori Controf Bytes
Configura,lon
I
of, Tr.rismi~.'()Ptipn ~':'~rm$:
Definition of Transmitter OptiollS:
Control bytes for the ttiree CO~figurailons are given in hexadecil\ial format in the fOllowing table:
.
, No.
1
I
In this config!Jration,activating $ignal RTS
causes tile modem'to transmit a tone at. a singl~ frequency
specifi!'l~. Py,the user. nyc> regist!!!:s inlhe host interface
memorY spa~ contain tile frequency code. The most significant bits are specified iii theFREQM '89istet (0:3): The l!'Iast
significant.bits are specified inthe FREQUegister (0:2). T"e
leaslsign\!icanl bit represents 0.146484 HZ±O.01%.
'
TR~~SMltTER CONF.tGU~ATION REGISTER
TDR1.
,
3. Tone.Transmit
an
TNXMT.
TLTS.
TV29.
TDR3.
TDR2,
Tf.8nsmttter ConfigurationsI':
, 4.'MarIU:/olli. " When theMHLQbit (1):7:4)i$on, the ;ransmit~
ter input data stream is forced to ,all marks (l's).
"
5. EchQ Protector Disable. When the EDIS,bil (0:7:3) is on, an
unmodulated carrier is transmitted .for 185 ms (oPtionally
30 ms)followed by 20: ms ¢ no transmitted energy at tile $Iart
of ttan$mission. Note that thiseplion is available in both V.27"
and V,29cOIifigurationsalthough,it isoot specified in the
cOin \1.29 recommendation.
01
80
10-18
9600· bps Data p~rnp Modem
R96DP
Link Delay Equalizer Selection
6. Transmitter Parallel Data Mode. WhentheTPDM bit (0.7:2)
is on, the tr.ansmitter accepts data for transmission from the
data input register rather than the serial hardwlire !lata input.
LOEN
D3L
1
1
7. External Clock Enable.
When the XCEN bit (0:7:1) is on, the
transmitter timing is established by the external clock supplied at the hardware input XTCLK (pin 22A).
8. Sholt ~ho Protector Disable Tone. When the SEDT bit (0:7:0).
is on, the echo protector disable tone is 30 ms long rather
than 185 ms.
Curve Matched
·X
0
1
(l'
No Equalizer
U,S'. Survey Long
Japanese 3-Link:
LOOP/LEVEL
The host processor conveys lobpback selection and transmittElf output level to the modem by wrhirig a control byte !ntothe
loopllevel register (9:4) in the interface memory space as shown
in the following table: .
EQUALIZER
The hostprocessor conveys equalizer selection information to
the modem by writing a control bytEi into the equalizer register
(0:5) in the interface memory space as shown in the following:
Definition of Loop/Level Terms:
Loca.1 Analog Loopbac::k (CCITT loop 3) Activate
Remote Analog LQopback(CCITT loop 4) Activate
L4HG:
Loop 4 High Gain
TL3-TL 1: Transmitter Level (Selects bits 3, 2, and 1)
L2ACT:
Remote Digital Loopback(CCITT loop 2) Activate
L3ACT:
L4ACT:
Definition of Equalizer Terms:·
CABS1,2:
LAEN:
LDEN:
A3L:
D3L:
Cable Equalizer (Selects bits.l or 2)
Link Amplitu(le Equalizer Enable
Link Delay Equalizer Enable
Amplitude 3-Link ·Select
Delay 3-Link Select
Definition .of Loop/Level Control:·
1. Local AnaJogLoopback Activate. When t~e L3ACT bit (0:4:7)
is on, the transmitter analog output is coupled to the receiver
analog input through anattenuator.inaccordance with CCITT
recommendatiqn .v.54 loop 3.
Definition of Equalizer Parameters:
:2. Remote Analog~oopback Activate. When the L4ACT bit
1. Cable Equalizer. The· cable equalizer select bits simultaneously control amplitude and delay compromise equillizers
in both the transmit and receive paths. The following table
gives the possible bit combinations.
,.<
(0:4:6),ls on,the receiver analog'input is connected to the
tJ;ansmilter analog output through a variable gain amplifier.
3. Loop 4High Gain: WhEIIltheL4HGbit (Q:4;S) ison,t~e loop
4 variable gain amplifier tssetior + 16 dB·. When L4HG is
off, the gain IsO dB.
.
),
Cable (0.4 mm diameter) Equalizer Selection
CABS2
CABSl
0
0
1
0
1
0
1
1
.,.
4. Remote Digital Loopback Activate. When the L2ACT bit
(0:4:1) is on, the receiver digital output ~ connected to the
transmitter digital input in accordance witl1 CCITT recommen. dation V.54 lqop 2.
'
Cable 1,e"gth
0,0
1.8 kin
,.
3.6 kiTt
7.2 km
2. Link Equtllizer. The link equalizer· enable and select bits
control separate amplitude and delay compromise equalizers
in the receive path. The following tables give the possible bit
..
. .. .
. .
combinations.
I'
Link Amplitude Equalizer Selection
A3L
Cllrve Matched
0
1
1
X
No Equalizer
U:S, Survey Long
Japanese 3-Link
il
1
-
Transmitter Level Selection
TL3
TL2
TLl
0
.0
0
0
LAEN
.
5. Transmitter Level Select 3, 2 and 1. Transmitter iUlalogout-,
. put level is determined by bits TL3,TL2, and TL1 as shown'
in the following table:
..
0
0
1
0
1
0
0
1·
·:1
1
1
1
1
1
0
'f
0
1
0
1
-,
Trlln.ltter Analog OlltPllt
- . O.S ClBm,±O.S dB·.
- 2.5 dBm :to.s dB- 4.S dBm ±O.SdB
- 6.S dBm :i:O.5dB
_ 8.S dBm ±O,S dB
-10.5 dBm ±Q:5 dB
-12.S dBm ±O.S dB
·-14.S dBm ±O:S dB
·EIICh step is a 2 dB change *0.2 dB
10-19
R96DP,
9600 bps Data Pump Modem
TRANSMITTER DATA
Definition of Transmitter Handshake 'Terms:
The host processor conveys ,output data to the transmitter in
parallel mode by' w~iling a data byte to the transmitter Data
Register (O:O)intheinterface memorY space. The dala must be
divided on ililagral baud bOl,!ndries as shown in the following
table:
TlA:
TSB:
TIE:
TBA:
Definition of Transmitter Handshake S~uelices:
Transml"er Data Register (0:0)
Configuration Bit 7 IBit 6
V.29 9600 bp~
51 Bli ,4,IBII 3,IBII 21 BII '1 BII 0
1
Baud 1
I
)(
V.29 7200 bps
Bau~
V.29 4800 bps
:3
V.274800 bps
X
V.2724OO bps
BaUd 3
NOTE: Dala
BIt
Transmilt~
';,1: "
Baud 0
Baud 2, I
Baud 1
I
Baud 1
I
'Baud 1
Baud 0
Baud 2
1. Transmitter Buffer Available.
The TBA bit goes off ,when the
host processor writes data 10 transmitter data register (0:0).
When the transmitter empties register 0:0 the TBA bit is on.
BaudO",
Baud 1
I
Transmitter;lnterruptActi,ve
Transmitter Setup !;Iii'
"
Transmitter'lnterrupt Enable
Transmitter Buffer Available
I
2. Transmitter Interrupt Enable. When the host processor writes
a ,1 in Ihe TIE, bit, the 'IRQ line of the hardware interface
Baud 0
is dri,ven low when TBA is on.
Baud 0
3. Transmitter Interrupt Active.
Status bit TIA is on whenever
the transmitter is driving IRQ low.
Bil 0 First.
When the host processo~ changes the
transmitter configuration register, thehost must write a 1 in
the TSB, bit. Bit TSBgoes 10 O'When the change becomes
efte,ctive.
'
4. Transmitter Setup Bit.
FREQM/FREQL
The host pr0ce$s6r conveys tone generation data to the transmitterby writing a 1,s.:bit data word to the FREQM/FREQl registerS
(0:3 and 0:2) in llie interface memory space as shown in.the
'
' '
,
following tables:,
RECEIVER CONFIGURATlON i
The hosl processor cOnfigures the receiver by writing a control
byte into the receiver configuration register (1 :6) in the interface
memory space as shown in' the follOWing tabl.e: '
Receiver Configuration Register (1:6)
The frequency number (N) determines the frequency (F)
follows: F=0.1464,84N Hz ±0'.01%
'
as
Definition of Receiver
COmmonly Generated Tones
FREQM
FREQL
462 Hz
1100Hz
1650 Hz
1850 Hz
2100 Hz
oc
52
10
2C
31
38
Terms:
Receiver long Training Sequence
RV29: ·Receiver V.29 Configuration
RDR3: Re(;~iver Dala Rate ~ (Selects 9600 bpsN.29)
RDR2: Receiver Data Rate 2 (Selects 7200 bpsN.29 and
Selects 4800 bpsN.27)
RDR1: Receiver Data Rate 1 (Selects 4800 bpsN.29 and
Selects 2400 bpsN.27)
Hexadecimal frequency numbers (FREQM, FREQl) for cOmmonly generated tones are given in the following table:
Frequertcy
Configura~lon
RLTS:
55
00
Conlrol words for, the two receiver configurations are,given in
hexadecimal format ,in Ihefollowing table;
55
00
"
TRANSMITTER HANDSHAKE,
Receiver Configuration Control
The host prqcessor performs a handshake sequence with the
transmitter by controlling and testing bits in the transmitter handshake t~ister (O:E) in the interface memory space as shown
in the folJowing table:
10-20
No.
COnfiguration
Configuration Word (HEX)
1
V.29 9600
V.~ 7200
V.294800
14
12
11
2
V.214600 Long
V:27 2400 Long
V.27 4600 Short
V.272400 Short
22
21
02
01
.' 960~tbps,Data Pump NI~~11'I
6. TI2 Equalizer Select. When t~ bit (1:7:1) is on;. anadapo'
tive equalizer with two taps per baud is used. Wh~n 12 is off
the equalizer has one tap ~r baud.
12
eflnltlon of Recelv,r Configurations:
.. V.29. When ariy' Of the V.29 configurations has been
lIelected,the transml~er operates as specified in CCITT
rec:drhmerldation V.29.
7. ReceiVer Tralnlng Disable. When the ATDIS bit (1 :'7:() is on,
the receiver is prevented from recognizing a training
sequence.
. . V.27. When ~y of the V.'l1configurations has been selected, .
the transmitter' operates' as specified in CCITT recommendation V.Zl.
RECEIVER SAMPI.,E ,liANDSIiAKE
The host proceSsor performs a handshake sequence with the
receiver sample. rate device by controlling and testing bits in the
recei)ler sample handshake register(tE) in the interfaCe memory
space' as shown in the following table.:.
.
hetiOSt procesSor-conveys option information to the transmiter by writing a control byte into the option register (1:7) in its
Interface memory space.as shown in the ,following table:
'I
'
.'
.
'
Receiver Samille Han~Shake.Regl~r (1:E)
Bit 7
RTH2
Definition of ReceiVer Option Terms:
Receiver Energy Detector Threshold (Bits 2 and 1)
Descrambler Disable.
RPDM:Receiver Parallel Data Mode
SWRT:'
Sample Wr.ite
BWRT:
aaud Write
T2:
TI2 Equalizer $el~
RTDIS:
Receiver Training Disable
RTH2, 1:
DDIS:
Definition of Receiver Slimple
Hand~hake
Terms:
RSIA: Receil(er Sample,lnterrupt Active
RSSB: Receiver Sample ~up· Bit
RSIE,Receiver SliIrJlple .Interrupt Entlble
f\SDA: ~eceiver SamplE! Data~ilable.
Definition of Receiver Sample Handshake Sequence:
Sample Data Avai/fJble., .. The RSDA bit goes on
when th lt rece.iver writes data into the receiver data register
(1:0). The bit goes off when the host processor reads data
froin register 1:0.
1. Receiver
Definition of Receiver Options:
1. Receiver Energy Detector Thteshold (Bits 2 and 1). The
r~eiVl!lr energy detector threshold is set by bi,~ATH? .and
ATH1 according to the foflowingtabll!:
2. Receiver Sample Interrupt ~nable.
When the host processOr
writes a 1. in the RS.IEbit, .th!i. iRQ,lin!:! of the hardware imerface is driven lowwi)~rl. RSoA is
Receiver Energy Detect. Thresholds
RTH2
RTfI1
0
0
.1
1
1
0
0
RLSD On
>
>
>
>
-43 ilBm
-$3 dBm
-26dBm
-16 dBrn
on." .
RLSD.Off .
< -48dBm
< -38·dBrn
.
Active. Status bit RSIA Is on
whenever the Receiver Sample ratE! device isdriVlng IRQ low.
3. ReceiVl!lr Sample Interrupt
<-319~m.
4. Receiver SatuP. elt. When the host processor changeS. the
.' receiver configLiratiQrlQrbits 6 or 7 inloe option ~ister.the
. hQSt mUStwrUe a 1 in the RSB bit.Bil RSe goes to Owhen
the changes become effective.
< -21dEim
2. Descrsmbler Disablf. . When the D[)IS ;bit(1:7:.5)isp~)he
ree;eiver descrambler circuit is remOved from the data. path.
RECEIVER BAUD HANDSHAKE
perf~~S
3. Receiver Parallel Data Mode.
When the RPDM bit (1 :7:4) is
on, the receiv$r supplies data to the receiver data register (to)
in parallel with the hardware serial data output.
.'i[I'
'
.The host processor
a htmdshake sequence with the
receiver baud:.,.a·.!e deVice l:!Y .controllin\land te$li.~9 bits.inth~
receiver baud handshake register (2:E) in the interlace memory
'1' :
space as shown in the following table:
'
•...
4. SamPle Write. When the SWAT bit (1:7:3) is on, the 16-bit
Word in registers 1:1 and 1:0 is written in the RAM location
specified by the contents of register 1:4.
'
.
Receiver Baud Handshake Reglstitr (2:E)
5. Ba~d write. Wh~n the BWAT bit (1:7:2).is on, the 16-bit wofd
in locations 2:1 and 2:0 is written in the RAM locati.on specified
by the contents of register 2:4.
.
10-21
.
R96DP
9600 bps Data Pump M·Qdern
Definition of Receiver Baud Handshake Terms:
RECEIVER BAUD STATUS
RBIA: Receiver Baud Interrupt ACtive
RBIE: Receiver Baud Interrupt Enable"
RBDA: Receiver Baud Data Available
The host processor has access to status bits that renect Qpera-,
tiol),of the receiver baud rate device. These bits can be tested
by the host by reading the receiver baud status word (I:B) In
the interface memory space as shown In the following table:
Receiver Baud Status Register (I:B)
Definition of Receiver Baud Handshake Sequence:
1. Receiver Baud Data Available. The RBDA bit goes on when
the receiver writes data into regist!!f (2:0). The. bit goes off
when the host proceSsor .reads data from register 2:0.
2. Receiver Baud InterrLipt En~ble. When the host processor.
writes a 1 in the RBIE bit, the IRQ line of the hardware interface is driven low when RBDA is on.
Definition of Receiver Baud Status Terms:
PNDET: Period N Detector
CDET: Carrier Detector
3. Receiver Baud Interrupt' Active. Status bit RBIA is .on
whEmever the receiver baud rate device is driving IRQ low.
Definition of Receiver Baud Status Conditions:
1. Period N Detector. When the PNDET bit(I:B:6). is off, it indicates a PN sequence hall been detected. This bit sets to a
1 at t,he eM of thePN. sequence.
RECEIVER SAMPLE STATUS
2. Carrier Detector. Whe!1 the CPET bit (1 :B:O) is off, it indicates'
that passband energy Is being detected and that a training
sequence Is not in process. It goes off at sta,rt Ilf data state
and goes to a 1 at end of receJved signal,
The host processor has access to various status bits that reflect
operation of the receiver sample:'rate deVice; These bits can be
tested by the host by reading the receiversarnple status 'word
(1:8 and 1:9) in the interface mEimory space as shown in the
follOWing tables:
RECEIVER DATA '
Receiver Sample Status Register 1 (1:8)
The host processor accepts input data from the receiver· in
parallel mode by reading a byte from the receiver data register
(2:0) in the interface memory space. The data is divided on integral baud boundries identical to the transmitter data register with
bit 0 received first. Note that the receiver data register is used
for diagnostic data in the serial mode.
Receiver Sample Status Register 2 (1:9)
DIAG~OSTICCA!=IABILITIES
TheR96DP provides the user with access to much of the data
stored in the modem's memories. This data is a useful tool in
performing certain diagnostic functions.
Definitio'n of Re~iver Sample Status Te.rms:
P2DET: Period Two Detector
FED:
Fast Energy Detector
HARDWARE DIAGNOSTIC CIRCUITS
Signal names and descriptions of the hardware diagnostic
circuits are given in the following table;'
DefinitiOn of Recelve.r Sample Status Condit.ions:
Hardware Diagnostic Circuits
1. Period Two Detector. When the P2DET bit (1:8:2) is off, it indicates that a P2 sequence has been detected. This bit sets
to a 1 at the start of the receive data state.
Name
EYEX
EYEY
EYECLK
EYESYNC
2.. Fast Energy Detector. 'When the FED bit (1 :9:6) is off, it indi"Cates that energy above the receiver threshold is present in
the' passband .. ,
10-22
1/0
Pin No.
0
0
0
0
15C
14A
14C
13A
.Descrlptlon
Eye Pattern
Eye Pattern
Eye Pattern
Eye Pattern
Signal
Data - X Axis
Data - Y Axis
Clock
Synchronizing
. . R96DP
9600 bpsPEJta Pymp. Mod.m
.'
EYE! Pattern Generation ..:iTh~ four hardwarediagnostii: circuits
allow the user to generate and display an eye pattern. Circuits
EYE>< and EYEY serially present eye Pattern data for the horizontar and vertical display inputs .respectively~ The. 8-bit data words
are shifted out most significant bit firSt, Clocked ·by therj~ing
edge of the EYECLK output. The EYE$YNC outputisprovided
for:word synchronization. The falling edge of EYESYNC may
be used to transfer the 8-bit word from the shi·ft register to ·a
" holding register. Digital 10. a~log cql;lversion can then be Performed for driving the X and Y inpUts of an oscilloscope. .
RAM Access Codes
'.
1
2
SOFTWARE· DIAGNOSTIC CIRCUITS.
Each receiver device (sample rate aqd baud rate) contains six
registers in the inferface memory space dedicated to reading
• and writing modem RAM locations from the host processor bus.
Four of these registers are organized into 2-byte data words and
the ·remaining two registers form 1-byte control registers that hold
RAM access codes. Data is read from RAM into the data
registers. Data is written into RAM from the data registers. The
RAM location involved in· the data tral!sferis specified by the
RAM access cod.e stored in the associated diagnostic control
register. The diagnostic registers are related as shown in the
following table:
.
Software Diagnostic
Device
Control.
Regl"er
Write Bit
Sample
Sample
Baud
Baud
XS (1:5)
Yg (1:4)
XB'(2:5)
VB (2:4)
None
SWRT (1 :7:3)
None
BWRT (1 :7:2)
. XSM(1:3)
VSM(1:1)
>CBM. (2:3)
YBM (2:1)
..
ECjualizer Input
Equalizer Tap Coefficients
Un rotated eq~alizer Output
Rotated Equalizer Output:
(Received POints)
... Decision Points (Idea! Data Points)
Rotation Angle
Frequel)cy Correction ("'!$B's)
Frequency Correction (LSB's)
EQM
POWER~ON
Reat·
Imas·
Access
Acc'eSs
.. CO
C2
42
04
54
81
-
CO,
81.Ao
E1
A2
E2
E3
04
01
40,
01-20
61
.-
22
62
63
00
-
2A
,AA:
2B
~
-
INITIALIZATIQN
When power \sappliedlQtheR96DP, aperioqof 100 to 300 ms
is. required for initialization. The power-on-resetsignal (POR)
remains low during the initialization penod. After the low to hi.gh
transition of POR; the modem Is ready to Qperate. At P()R tim~
the. modem defaults to thl! fallowing configuration: V.29,
9600 bps, T/2, long $choprotect disable ton\,/, serial data mode,
internal ClOCk; 'cable select 1.8 Km. amplitupe arid dela~
equalizers enabled and Japanese 3 link curves selected,
·tran!lmitter:out~\jt leve,lsettQ-0.5 ·dBm ±o.S dB, interrupts
disabled,and .receilierthreshold set to - 43' QBm.
Data Word'
(LSB)
XSl
VSl
XBl
VBl
" Received Signal Samples
t;>embdulator Output
Low Pass Filt~r. Output
One Baud Energy
AGC Gain W6rd- MSB's
AG}: Gain Word -"- lSB's
!:tror
Registers
Data Word
(MSB)
Furictlon
Bank
(1:2)
(1:0)·
(2:2)
(2:0)
'POR can also.be used to initialize the users's host prooe$sor.'
II 'may be connected to a tlser supplied power-On~reset signal
*In parallel mode, register 1:0 is used for receive data ·and
not diagnostic data.
in a Wlre-orconfiQuratipn. '"
.......
.
PEfl,FQRMANCE
,S
Data transfer reQlllaied by the appropriate data avjlilable bit. .
Reading always takes place at t~Ei designated r~te, .and data
left .in the data registers is overwritten each cycle. When the
aSsociated Write bit I~set. a write cycle is performed.each t1me
the. associated data available bit Is off.
.
WhethedlJnctioning.'as aV.27 bistter9/" V.29 type modem, .the
'R96DP provides the user with unexcelled ~igh performance.
Bit Error Ratee .... The Sit Error Rate (SER) performance of the
modem isspeeified for a test configuration conformJ?g to that
.specified in CCITT recommendad.on V,56, except With regard
to t~e Placement of the filt~lJsE!d t:>andlimit, th~. w"lls noise
souiPe. Blle,rrocrate.saremeilsurec ala feceiv",cnYne signal
level 01.40 clBm aSillustrated.
",~
.
to
,The eight bits of registers 2:3 and 2:1 are continuously presente9
serially on· hardware In.terface 'lines EYEX.: and .EYEV' :
'respectively.··"·'"
'Phase Jitter '--Ai 2400 bps, the modern exhibitS a bit error rate
of 10"8 or less with a slgnal-to-~qise ralio, of 12..5 dB in the,
. pre$ence of 15° peak.to-peak phase jitter at 150Hz Of '.With a
signal-Io-noise ratio Of 15 dB In t.he presence of 300 peak-to-peak
phase jitter at 120. Hz\(scramtller inserted).
'
.' R.AM.ACCESS CODES
The following table lists access codes for frequently used RAM
'. data:
10-23
iDJ.".
.... ,
'.
R96DP
9600 bps Data Pump Modem.
At 9600 bps. the modem exhibits a bit error rate of 10-6 or less
with a signal-to-noise ratio of 23 dB in the presence of 10° peakto-Pfilakphase jitter at 60 Hz. The modem exhibits a bit error
rate of 10-5 or less with a signal-to-noise ratio of 23 dB in the
presence of 60° peak-to-peak phase jitter at 30 Hz.
At 4800 bps (V.27 bis/ter). the modern exhibits a bit error rate
of .10-6 or less with a signal-to-noise ratio of 19 dB. in the
pr¢sence of 15° peak-to-peak phase jitter at 60 Hz.
4800 BPS
V, 27
AND
7200 BPS 9600 BPS
V.29
/ V.29
2400 BPS ~OBPS
V.29
V.27
10- 3
\
1\
\
V
V
INTERFACE CIRCUIT CHARACTERISTICS
V
DIGITAL INTERFACE CIRCUITS
Digital Input Characteristics
Input Logic State
Allowed Input Voltage Levels
O.OV to + O.BV at· - 2.5 pA
+ 2.0V to + 5.0V at + 2.5 pA
Low
High
Notes
1. Thedigital inputs are directly TTLlCMOScompatible. The
capacitive loading on each input is 25 pF (maximum).
2. Positive current is defined as current into the nqde.
Digital Output Chanu:teristics
Output Logic State
'
,
Output Voltage Level
+O.4Vat +·1.6 mA
+2.4Vat -100 pA
Low
Hi9h
Notes
1. The digital outputs are directly TTL/CMOS compatible.
Capacitive drive capability is 25. pF.
2. Positive current is defined as current into the node.
\
\
10 '
6
8
10
12
14
16
18
20
22
24
26
28
30
SIGNAL'TO-NOISE RATIO dB
Typical Bit Error Rate Performance
MODEM
TRANSMITTER
-
LINE
SIMULATOR
~
NOISE
SOURCE
GRl3S1
50KHZ BW
-
ATTENUATOR
HP 3500
IMPAIRMENT
SOURCE
BF;lADLEY 2A
-
ATTENUATOR
f--:-HP 3500
L
~7
LEVEL
METER
HP 3552A
MODEM
RECEIVER
I
I
ENGINEERING
MODEM
CONSOLE
-
NOTE
Signal and noise are measured with 3 kHz flat weighting.
BER Performance Test Set-up
10-24
ENGINEERING
MODEM
CONSOLE
A96DP
9600 bps Data Pump Modem
ANALOG INTERFACE CIRCUITS
TransmHterOutput Level - Tile transmitter output level is
adjustable in 2 dB steps from - 0.5 dBm to - 14.5 dBm accurate
to ± 0.5 dB. This level is measured at TXAinto a 600 ohm
impedance.
Receiver Input ohm ±5%.
The receiver input impedance is 63.4K
Auxiliary Transmitter Input - The auxiliary transmitter input
(AUXIN) allows access to the transmitter for the purpose of
interfacing with user provided equipment. Because this is a
sampled data input, signals above 4800 Hz will cause aliasing
errors. The input impedance is 1K ohm and the gain to transmit·
ter output is OdB.
R960P SPECIFICATIONS
Power Req!lirements
Voltage
ToleranCe
Current (Max)
+5 Vdc
+ 12 Vdc
-12 Vdc
±5%
±5%
±5%
<700 mA
<20 rnA
<80 mA
Note: All voltages must have ripple :s 0.1 volts peak-to-peak.
Environmental
Parameter
Temperature:
OperatingStorage-
Relative Humidity:
Specification
O°C to +60 o C (32 to 140°F)
".40 o C to +90 o C (-40 to 176°F)
Stored in heat sealed antistatic bag
and shipping container
Up to 90% noncondensing, or a wet
bulb temperature up to 35°C,
which!Wer is less.
Mechanical Information
Parameter
Board Structure:
Dimensions:
Weight:
Specification
Single PC board with single right
angle header with 64 pins, DIN 41612
or equivalent mating connector.
Width-3.94 in. (100 mm)
Length-4.70 in. (120 mm)
Height-0.55 in. (1.40 em)
Less than .22 lbs. (.08 kg)
10-25
R96FT
Integral Modems
'1'
Rockwell
R96FT··
9600 BPS FAST TRAIN MODEM
PRELIMINARY
INTRODUCTION
FEATURES
The R96 Fast Train (FT) is a synchronous, serial 9600{7200/
4800/2400 bps modem suitable for operation over dedicated unconditioned lines. It satisfies the telecommunications requirements specified in CCITT Recommendations V.29 and V.27
bis/teT.
• Configurations
-CCITT V.29, V.27 bis/ter
• Fast Training Sequence <30 msecl9600 bps, <2q msec/
4800 bps
.
Ideal for Multipoint Applications
Plug Compatible with Rockwell R96DP, R48DP Modems
Secondary Channel (Optional) 110, 75 bps
Dynamic Range: -43 dam 10.0 dBm
Equalization
-Automatic Adaptive
-Compromise Cable (Selectable) .
-Compromise Link Amplitude.(Selectable)
• DTE Interface: Two Alternate Ports
-Microprocessor Bus
-CCITT V.24 (RS-232-C Compatible)
•
•
•
•
•
The R96FT is specifically optimized for use in a multipoint
environment requiring a fast training sequence of less than 30
msec at 9600 bps and less than 20 msec at 4800 bps. The optional secondary channel, small size {100mm by 160mm), and
low power consumption (4 watts typical) offer the user flexibility in creating a 9600 bps modem. customized for specific
packaging and functional requirements.
Data can be transferred to and from the modem either serially
over theCCITT V.24 interface or in parallel. over the microprocessor bus interface.
The R96FT is a member of Rockwell's family of plug compatible 9600/4800 bps modems.
• Diagnostics
-Provides Telephone Line QualHy Monitoring Statistics
• Programmable Transmit Output Level
Product availability is winter, 1984.
• Loopbacks
-Local Analog
-Remote Analog (Locally Activated)
-Remote Digital (Locally Activated)
• Small Size-100mm x 160mm (3.94" x 6.30")
• Power Consu'!lption-5 Watts Typical
• TTL and CMOS Compatible
R96FT Modem
Document No. 29220N45
10-26
Product Summary Order No. 645
Rev. 2, March 1984
R96FT
9600 BPS Fast Train Modem
r-----I
I
I
I
I
I
I
I
I
L_--
r- -
..i....
"I
..
1,
I
"';:SCOPE"
....
C'i'§
txo
ALSD
'"'-
RXD
RDCLl(
.....
TSCLK
....
RBCLK
,_J
R9SFT
MODEM
+1,2
... +5
.
P
•. TXOUT
POWER
SUPPLY
POR
i"'"
IROP
I'"
.A
.. y
1
LINE
INTERFACE
-
}
TE~EPHONE
LINE
~AUi-
20K
;;
~THRESH10r2
I
I
1\
:\
+5V
I
9
C.
\ I
I
20K
>--~>--,---.. THRESH1 Dr 2
+5V~f20K
10
10K
NOISE
SOURCE
GR1381
50 KHZ BW
I
ENGINEERING
MODEM
CONSOLE
I---
12
14
16
18
20
22
24
SIGNAL TO NOISE RATIO
Typical Bit Error Rate Performance
Suggested Interface Circuits for Controlling
THRESH1 and THRESH2 Input Lines
MODEM
TRANSMITTER
\
\
\
~12Y
LINE
SIMULATOR
I---
IMPAIRMENT
SOURCE
BRADLEY ~A
-
ATTENUATOR
HP 3500
I---
ATTENUATOR
HP 3500
-
~
NOTE
THE V,56B CONFIGURATION INCLUDESA PERFECTO,3 TO 3,4 KHz FILTER
ON THE NOISE SOURCE, TO ACHIEVE THE SAME EFFECT IN THIS
CONFIGURATION. THE LEVEL METER USES lSKHz FLATWEIGHTING AND
6,85 dB IS ADDED TO THE MEASURED SIN RATIO,
BER Performance Test Set-up
10·32
L
i--L...-
LEVEL
METER
HP 3555B
MODEM
RECEIVER
1
ENGINEERING
MODEM
CONSOLE
V96P/1
connection is made. It is. possible to 'set up the receiver
without a training sequence, but it is a manual mode requiring
considerable user effort. In a training mode, an internal gen. erated pattem is transmitted to the receiver to facilitate synchronization. During the training mode, the data input line to
the receiver is ignored and the output line does not reflect
the state of the data input
In the data mode of operation, information on the data input
is strobed by the transmitter signal element clock and transmitted to the receiver. The receiver demodulates and decodes
the passband signal and outputs the recovered data on the
output where it is then ready to, be strobed by the receiver
signal element clock.
Request To Send-Ready For Sending
To initiate transmitter operation in the data or training mode,
the Request to Send input is brought high. If a training mode
is not initiated, the Ready for Sending indicator goes high
within one baud interval and data transmission commences.
The mode of the receiver is indicated by the data channel
received line signal detector (0109). For data mode, 0109
is high and the receiver training mode indicator is low.
If the receiver enters the training mode, the receiver training
mode indicator goes high until the training mode is completed. When training is completed the receiver training mode
indicator goes low and, if sufficient signal energy is present
on the input line, 0109 goes high, enabling the data mode.
Training Mode-Dial and Point-To-Point
For dial and point-to-point configurations, the V96P/t receiver
training is automatically initiated whenever a training sequence
is detected in the received line signal. The training sequence
consists of two phases: Phase 1 causes the training detector
to turn on and also makes a course adjustment of the carrier
frequency variable, which compensates for any frequency
translation due to the channel; Phase 2 is used to converge
the adaptive equalizer, which is part of the V96P/l structure.
A short scrambler synchronization sequence follows Phase
2 and is used to generate the success indicator. In order for
training to be successful, the incoming training sequence
must have been generated by a Similarly configured transmitter using a compatible training sequence.
At the receiver, detection of a trainiflg sequence requires that
there be sufficient signal energy and that the receiver's carrier frequency variable be within 30 Hz of nominal.
High Speed 9600 BPS Modem
The resync configurations are used for reacquiring synchronization in turnaround operation without having to go through
the normal long training sequence. The resync training
sequences are relatively short and are used for recovering
carrier phase, symbol timing and achieving equalizer convergence without resetting carrier frequency and equalizer
taps.
Training Mode-Multipoint
In the V96P/l modem, two multipoint configurations are provided for 4-wire circuits conforming to Ml020 which permit
short training sequences. In these configurations, the first
train signal must be high to process the short training
sequences; otherwise the receiver will ignore the training
sequence and enter directly into the data mode. The receiver
will enter into the training mode if the first train signal is high
and there is sufficient signal energy.
For 4-wire circuits which are worse than
2-wire circuits, a long training sequence
rather than the multipoint configuration.
sequences require that the receiver be in
point-to-point configuration.
Ml020 and for
should be. used
These training
the proper diaV
Training Mode-Manual
The V96P/l modem .includes two manual configurations in
which the remote modem need not transmit a special training
sequence to the local receiver. In these configurations, the
equalizer tap coefficients for the local receiver must be initialized from an external source. The tap coefficients may be
initialized by controlling three input terms-ICR, ICI and
ICLCP-in synchronization with the Baud Rate Clock.
In order to operate the modem in the manual configurations,
both the transmitter and receiver must be set according to
the code Shown in Table 1 Modem Configuration. Manual
cbnfiguration code octal 30. has a longer synchronizing
sequence than configuration code octal 32, but both synchrClnizing sequences conform to the CCITT Recommendation V.27. However, neither sequence is of sufficient
duration to aid in training the receiver.
Receiver Operation During Loss of Line Signal
When there is no line signal present, all receiver update
relating to the equalizer, carrier frequency variable and baud
timing are inhibited and the current values of the equalizer
taps and the carrier frequency variable are retained.
Training Resync (V.27 bis/ter Turnaround)
In a 2-wire half-duplex data communication system, data can
be transmitted in only one direction at any given instant.
Therefore, the modems at the local and remote sites are
required to. interchange their roles as the receiver and the
transmitter, respectively. This turnaround operation requires
constant resynchronization to meet CCITT Recommendations for V.27 biS/ter.
DATA QUALITY
The receiver generates an Eye Quality Monitor (EQM) signal
that can be used to determine the equivalent Gaussian signal
to noiSe ratio of the overall system within approximately ±
V~6P/1
High Speed 9600 BPS Modem
ADDITIONAL CAPABILITIES
2 db. Eye quality is determined by calculating the difference
~tween, the received signal point after equalization and the
transmitted or expected sign,al point. The, receiver output
DE02P is a filtered version of this error signal. It is a serial
word clocked by the system bit clock (345.6 kHz or 230.4
kHz, depending on baud rate). Outpu!signal DOGTP is a
gating signal which delineates the eight MSB's of DE02P.
The use and interpretation of these binary signals are quite
complex and are dependent on the application and the signal
structure. The user can derive a meaningful interpretation of
the EOM readings by monitoring, them while' testing, the
mqdem against his perform,mce criteria.
The V96P/1, provides many additional capabilities. germane
to data communication system design and implementation.
Capabilities such as local Ioopback, tone generation and
detection, external clOCk facilities, and 300 bps FSK operation are briefly described in the following paragraphs.
Local Loopback Capa~ility
A localloopback option is available for all half duplex and full
duplex modem configurations. The Local Loopback Command (ILS) connects the transmitter's output through a buffer
amplifier to the receiver input, thereby allowing a check of
lhe local modem. The ILB command squelches the input to
the receiver and loops the analog signal from the transmitter
to ,the receiver input.
Visuaj D'isplay of Eye Pattern
A visual indication of the modem's perfOrmance can' be
obtained by displaying the received baseband signal struc:
ture after equalization. This is done by converting the eight
MSB's of the real and imaginary equalized signal points
available on DRERP and DIERP to analog voltages which
are then used to drive the horizontal arid vertical sw~eps of
an OSCillOSCOpe. The resultant display will be' a syn1metrical
dot pattern of 16 points, 8 points, or 4 points which is a lime
representation of the received ba~band Signal. Any uncompensated distortion over the transmission path will eause
each dot in the pattern to enlarge or othe'iwise shOw disto'r~
tion.A typical visual eye pattern of a 4"point display is shOwn
in the following diagram.
An internal pattern generator is also incorporated in the
modem which can be used when no modem te,st set is
available.
Tone Generation And Detection
The transmitter can be used to transmit single frequency
tones for disabling echo suppressors or for system Signaling.
Tones that can be transmitted (selected through software
control) are: 1100 Hz; 1300 Hz, 1650 Hz; 1850 Hz, 2025 Hz,
and 2100 Hz. Other tones are also possible and the carrier
frequency can be altered by selection of values for a binary
bit stream.
External Data Clock
DISPERSION
The data input to' the transmitter can be clocked from an
external Source when the external clock is used as a reference input to the data clock's phase locked loop. By applying
an external clock the reference iriput will cause the transmitter data clock to track the frequency and phase of the reference. The frequency of the reference clock must be within
100 ppm of nominal in ,order for the receiver's baud timing
to properly track that of the transmitter. The reference clock
can be equal to the nominal data clock frequency or be a
subharmonic of it as long as the frequency tolerance is
adhered to.
DUE TO.GAIN
ERRORS
DISPERSION DUE
TO PHASE ERRORS
OrsPERSION A-AOUND
PROPER POSITION DUE
TO COMBINATION OF
RANDOM NOISE, PHASE
CIRCLE REPRESENTS
PROPER POSITION OF
HIGH QUALITY SIGNAL
ERROR, AND/OR GAIN
ERROR
'
Typical Eye Pattern
300 bps FSK Modem Operation
A CCITT T.30 compatible 300 bps FSK modem having characteristics of the CCITT V.21 channel 2 modulation system
can also be configured. The FSK modem is capable of generating the 1100, 1300, 1650 and 1856Hz tones.
Success Indicator
A second data quality indicator is provided for in all configurations except the 1200 baud non-V.27 modes. This signal
provides a rough indication that the training has been successful and that data will be properly received. This "suc. cess" output (DSUCP) will go high during the last one to
twenty milliseconds of receiver training, provided training has
been successful. During the data mode (DRTMP low and
0109 high), DSUCP will go high whenever 15 consecutive
data marks or spaces are decoded at the receiver data
output.
10-34
V9SPI1
. High· Speed. 9600 BPS Modem
SPECIFICATIONS
V96Pj1 Specifications
DC Voltages
Vol~
+ 5voH
+12 voH
-12 voR
Toiera...
Current (Typical)
Currant (Max)
±5%
±S%
13S ma
40ma
17S·ma
<2ooma
< 70ma
<23Oma
±5°/o
NOTE: All voltages must have ripple ..0.1 voHs peak-to-peak.
Environment
Temperature:
Relative Humidity:
.
Ppereiing! ~C to +6O"C (32 to 140'F)
Storage: -4O'C to +8O'C (-40 to 176'F)
(Stored in heat sealed antistatic: bag and shipping container)
Up to 90% noncondensing, or a wet bulb temperature up to 35'C, whichever is less.
.Mechanical
Dimensions:
Single PC board wHh edge connector
100 pin, edge connector, two sided, wHh 0.1 in (2.54 cm) centers. Recommended Viking3VHSOIIJNDS or equivalent m!lting connector.
Width-9.1e8 in (23.338 cm) . Depth-6.288 in (lS.972 cm)
Weight:
Less thl\n 0.45 Ibs (0.20 kg)
Board Structure:
Mating Connector:
1Cl-35
I
Jet
R48DP
Integral Modems
'1'
Rockwell
R48DP
4800 BPS DATA PUMP MODEM
PRELIMINARY
INTRODUCTION
FEATUR.ES
The Rockwell R48DPis a synchronous serial 4800 bps modem
designed for full-duplex operation ovar either four-wire dedicated
unconditioned lines or half-duplex operation over the general
switched telephone network.
.
..
• User CompatibilitY:
-""' CCITT V.27 blsJter
• Full-Duplex (4-Wlre)
• l:181f-Duplex
• Programmable Tone Generation
• Dynamic Range -43 dBm to 0 dBm
• DiagnoStic Capability
• Equalization:
- Automatic Adaptive
- Compromise Cable (Selectable)
- Compromise Link (Selectable)
• DTE Interface:
- Microprocessor Bus
- CCITT V.24 (R8-232-C Compatible)
• Loopbacks (V.54 Loop 2. 3 and 4)
- Local Analog
- Remote Analog (Locally Activated)
- Remote Digital (Locally Activated)
• Small Size - 100 mm x 120mm (4.0 x 4.8 Inches)
• Low Power Consumption (3 watts,typical)
• Programmable Transmit Output Level
• TTL and CMOS Compatible
The modem satisfies tel!lcommunications req",lrements specified
in CCITT Recommendations V.27 bisJter.
The small size and low power consumption of the modem offer
the user flexibility In creating a 4800 bps modem design
customized for specific packaging and functional requirements.
The modem is capable of operating at 4800 and 2400 bps.
A48DP Modem
Document No. 29200N08
10-36
Data Sheet Order No. MD08
March 1984
4800 bps Data Pump MC)de.m
R48DP.'
TECHNICAL SPECIFICATIONS
Automatic Adaptive Equalize' - An .automatlc ·adaptlve
equalizer Is provided in the receiver circuit The'equallz8r can
be configured as either a T or a T/2 equalizer.
The following are the technical specifications for the R48DP
modem.
TRANSMITTER CARRIER FREQUENCIES
.
~
TRANSMITTED DATA SPECTRUM
Thlt transmitter carrier frequencies are given in the following
table:
If the cable equalizer Is not enabled, the transmitter speCtrum
Is shaped by the following raised cOSin~ filter funCtloris:
1. 1200 Baud. Square rool'(lf 90 percent'
2. 1600 Baud. Square root of 50 percent
The out-of-band transmitter power limltatlonsmeet those
specified by Part 68 of the FCC's Rules, and typl~ally exceed
the requirements of foreign telephone regulatory bOdies. ,
Transmitter Carrier Frequencies
Sptclflcatlon
(~
Frequency Type
V.27 bislter Carrier
:to.S H,z)
1800
TONE GENERATION
SCRAMBLERIDESCRAMBLER
Under control of the host prOcessor, the R48DP can generate
voice band tones up to 4800 Hz with a resolution of 0.15 H:z and
an accuracy of 0.01% ..Tones over 3000 H:z are attenuated.
The R4eDP incorporates a self-synchronizlng scramblerl
descrambler. This facility is in accordance with V.27. bisiter.
SIGNALING AND DATA RATES
RECEIVED SIGNAL
FREQUENCY TOLERANCE
The signaling and data rates fQr the R48DP are defined in the
table below:
The receiver. circuit of the R48DP can adapt..to received
frequency errQf of up to :t 10Hz with less than 0.2 dB degradation In BER performance.
Slgnallng/Data Rates
Speclflcatlon
(:t 0.01%)
Parameter
Signaling Rate:
Data Rate:
1600 Baud
4800 bps
Signaling Rate:
Data Rate:
1200 Baud
. 2400 bps'
RECEIVE LEVEL
The receiver circuit of the modem satisfies all specified performance requirements for received line slgnill'leveis from 0 dBm
to -43 dBm.· The received line signal level is measured at the
receiver analOg input (RXA);
.
"
DATA ENCODING
RECEIVE TIMING
,
.
At 1600 baud, .the 4800 bps data~ream is encoded into triblts
per CCITI V.27 bisller.
.
"
The R48DP provides a data derived Receive Data Clock
(RDCll<) output in the form of a squarewave. The low to high
.transitions of tHis output .coincide with the.Center$ of received
data bits.. The timing recovery circuit is capable of tracking a
± 0.01 % frequency error in the associated transmit timing
source.
At 1200 baud, t!1e 2400 bps data stream is encoded into dibits
perCCITI V.27 bisller.
;
EQUALIZERS
The R48DP provides equalization functions that improve performance when operating over low quality Um"s.
TRANSMIT LEV/SL
The transmitter output level is accurate to
±1.0 dB and is pro-
Cable Equalizers - Selectable compromise cable equalizers
In the receiver and transmitter are provided to optimize performance over different .Jengths of non-loaded cable of 0.4 mm
diameter.
_ _.m..
Link EqualizerS - Selectable compromise link equalizers in the
receiver optiinize performance over channels exhibiting severe
amplitude and delay distOrtiOn. Two standards are provided: U.S.
survey long and Japanese 3-link.
The R48DP provides a Transmit Data Clock (TDClK) output with
.
the following characteristics:
1. Frequency. SeleCted data rate of 4800 or 2400 Hz ( :t 0.01 %).
2. Duty Cycle. 50% :t1%
-1.0dBmto -15.0'.m.,,0_.
TRANSMIT TIMING
10:.37
m
~
4800 bps Data Pump Modem
R48DP
Input data presented on TXDis sampled by the R48DP at the
low to high transition of TDCLK. Data on TXD must be stable
for at least one microsecond prior to the rising edge. of TDCLK
and remain stable for at least one microsecond after the riSing
edge of TDCLK.
RECEIVED LINE SIGNAL DETECTOR (RLSD)
For V.27 bis/ter, RLSD turns on at the end of the training
sequence. If training is not detected at the receiver, the RLSD
off-to-on response time is 15 ± 10 ms. The RLSD on-to-off
response time for V.27 is 10 ±5 ms. Response times are
measured with a signal at least 3 dB above the actual RLSD
on threshold or at least 5 dB below the actual RLSD off threshold.
EXTERNAL TRANSMIT CLOCK
The transmitter data clock (TDCLK) can be phase locked to a
signal on input XTCLK. This input signal must equal the desired
data rate to ±0.010f0with a duty cycle of 50"10 ±200f0.
The RLSD on-to-off response time ensures that all valid data
bits have appeared on RXD.
TURN-ON SEQUENCE
Four threshold options are provided:
1. Greater than - 43 dBm (RLSD on)
Less thim - 48 dBm (RLSD off)
2. Greater than - 33 dBm (RLSD on)
Less than - 38 dBm (RLSD off)
3. Greater than - 26 dBm (RLSD on)
Less than - 31 dBm (RLSD off)
4. Greater than -16 dBm (RLSD on)
Less than - 21 dBm (RI,.SD off)
A total of8 selectable turn-on sequences can be generated as
defined in·the following table:
Turn-On Sequences
CTS
Response Time
(milliseconds)
No.
V.27 bis/ler
1
2
3
4
4800 bps long
2400 bps long
4.800. bps short
2400 bps short
708
943
50
67
5
6
7
8
4800 bps long
2400 bps long
4800 bps short
2400 bps short
913
1148
255
272
Comments
NOTE
Performance may be at a reduced level when the received
signal is less tha" - 43 dBm.
.
...
Preceded by
Echo Suppressor
Disable Tone
fo(lines using
echo supressors'
A minimum hysteresis action of 2 dB exists between the actual.
off-to-on and on-to-off transition levels. The threshold levels and
hysteresis action are measured with an un modulated carrier
signal applied to the receiver's audio input (RXA) .
• For short echo protect tone. subtract 155 ms from values of
CTS response time.
MODES OF OPERATION
TURN-OFF SEQUENCE
The R48DP is capable of being operated in either a serial or
a parallel mode of operation.
For V.27 ter, the turn-off sequence consists of approximately
10 ms of remaining data and scrambled ones at .1200 baud or
approximately 7 ms of data and scrambled ones at 1600 baud
followed by a 20 ms period of no transmitted energy.
SERIAL MODE
The serial mode uses standard V.24 (RS-232-C compatible)
signals to transfer channel data. An optional USRT device
(shown in the Functional Interconnect Diagram) illustrates this
capability.
CLAMPING
Received Data (RXD) is clamped to a constant mark (one)
whenever the Received Line Signal Detector (RLSD) is off.
PARALLEL MODE
RESPONSE TIMES OF CLEAR-TO-SEND (CTS)
The R48DP has the capability of transferring channel data up
to eight bits at a time via the microprocessor bus.
The time between the off-to-on transition of Request-To·Send
(RTS) and the off-to·on transition of CTS is dictated by the length
of the training sequence and the echo suppressor disable tone,
if used. These times are listed in the Turn·On Sequences table.
If training is not enabled RTS/CTSdelay is less. than 1 ms.
MODE SELECTION
Selection of either the serial or parallel mode of operation is by
means of a control bit. To enable the parallel mode, the control
bit must be set to a 1. The modem automatically defaults to the
serial mode at power-on. In either mode the R48DP is configured
by the host processor via the microprocessor bus.
The time between the on-to-off transition of RTS and the on-tooff transition of CTS in the data state is a maximum of 2 baud
times for all configurations.
10-38
4800 bps DataPum.pMod.em
RTS
USRT
(OPTIONAL)
o ::
xt ty
I;::
CTS
, - TXD
-~------...;IR1Q~-OU~~~____________J
A
.A
INTERFACE . . - -
TELEPHONE
LINE
CSi
POR
.+5
-....}
AUXIN
-
1
R48DP Functional Interconnect Diagram
INTERFACE CRITERIA
R48DP Hardware Supervisory Circuits (Cont.)
Name
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins in a
64-pin DIN connector. Software circuits are assigned to specific
bits in a 48-byte int~rface memory.
07
Signal names and descriptions of the hardware supervisory
circuits, including the microprocessor interface, are listed in
the R48DP Hardware Supervisory Circuits table. The microprocessor intertace:is designed to be directly compatible with
an 8080 microprocessor. With the addition .of a few external logic
gates, it can be. made compatible with 6500, 6800, or 68000
microprocessors.
R48DP Hardware Supervisory Circuits
1/0
Pin No.
I
I.
I
I
I
I/O
31C,32C
3C,8C,51\,10A
19C,23C.26C.30C
15A,
12A
13C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1C
1A
2C
2A
3A
4C
4A
5C
RS3
RS2
RS1
RSO
I
I
I
I
6C
6A
7C
7A
CSO
CS1
CS2
READ
WRITE
IRQ
I
I
I
I
I
10C
9C
9A
12C
l1A
l1C
Chip ~Iect for Bank 0
Chip select for Bank 1
Chip Selep! ·Ior Bank 2
Read Enable
Write Enable
Interrupt Request
2lA
2M
22A
25A
250
24C
22C
24A
Receive Data Clock
Transmit Data Clock
External Transmit Clock
Request-to;Send
Clear-to·Send
Transmitter Dala
Receiver Data,
Received Line Signal Detector
0
Data Bus (8 BiIS)
"
Register Select'(4 Bits)
C. V.24 INTERFACE:
Deacrlptlon
RDCLK
TOCLK
XTCLK
RTS
CTS
TXD
RXO
RLSO
A. OVERHEAD:
AGND
OGNO
+5 volts
+ 12 volts
-12 volts
POR
Description
05
04
03
02
01
DO
06
HARDWARE SUPERVISORY CIRCUITS
Name
1/01 PinNa.
B. MICROPROCESSOR II'fTERFACE:
Analog Ground
Digital Ground
+ 5 volt supply
+ 12 volt supply ,
-12 volt supply
Power-on-resel
10-39
0
0
I
I
0
I
0
0
,
4800 bps Data Pump Modem
R48DP
R48DP Hardware Supervisory Circuits (Cont.)
Name
I 110 I Pin No. I
D. ANCILLARY CIRCUITS:
RBClK
TBClK
IgI
,26A
27C
E. ANALOG SIGNALS:
'TXA
RXA
AUXIN
I: I
31A
32A
30A
I
registers are collectively referred to as interface memory. See
R48DP Interface Memory table. Access to the three bank;s of
Description
registers (bank 0, bank 1 and bank 2) is enabled by the Chip
Select signals CSO, CS1 and CS2 respectively. Four Register
Select signals (RSC, RS1, RS2, and RS3 are provided to address
an individual register within an enabled bank. Registers in bank 1
operate at the sample rate of 9600 samples per second.
Registers in banks 0 and 2 operate at the selected baud rate.
Receiver Baud Clock
Transmitter Baud Clock
I
Transmitter Analog Output
Receiver Analog Input
Auxiliary Analog Input
R48DP Interface Memory
Bank
Oi
(i ., 0-')---___<(1
Microprocessor Interface Timing Diagram
Critical Timing RequirementS
Characteristic
Symbol
Min
CSi, RSi setuE!:J!!!!e prior
to Read or Write
TeS
Data access time after Read
TDA
Data hold time after Read'
TDH
10
CSi, RSi hold time after
Read or Write
Max
Units
30
-
nsec
-
140
nsec
50
nsec
TCH
10
-
nsec
Write data setup time
TWOS
75
nsec
Write data hold time
TWDH
10
-
TWR
75
-
nsec
Write strobe pulse width
C
0
0
0
0
0
0
0
0
0
0
0
A
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
F
E
0
C
B
A
9
8
7
6
5
4
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
nsee
INTERFACE MEMORY
The R48DP has three banks of 16 input/output (110) registers
to which an external (host) microprocessor has access. Although
these 110 registers are within the modem, they may be addressed
as part of the host processor's memory space. These 110
10-40
F
E
0
0
0
0
q
(i .,
(HEX)
Reg No.
0
B
2
-1
0'
F
E
0
C
B
A
9
8
7
6
5
4
3
2
1
0
DeSCription
Do Not Use
Transmitter Handshake,
Do Not Use
Do Not Use
Do Not Use
Do Not Use
Do Not USe
Do Not Use
Transmitter Option
Transmitter Configuration
Equalizer
loop/Level
FREQM
FREQl
Do Not Use
Transmitter Data
Do Not Use
Receiver Sample Handshake
Do Not Use
Do Not Use
Receiver Blwd Status
Do Not Use
Receiver Sample Status 2
Receiver Sample Status 1
Receiver Option
Receiver Configuration
Diagnostic Control XS
Diagnostic Control YS
Diagnostic Data XSM
Diagnostic Data XSl
Diagnostic Data YSM
Diagnostic Data YSl;
Receiver Data
Do Not Use
Receiver Baud Handshake
Do Not Use
Do Not Use
Do Not Use
Do Not Use
Do Not Use
Do, Not Use
Do Not Use
Do Not Use
Diagnostic Control XB
Diagnostic Control YB
Diagnostic Dilla XBM
Diagnostic Data XBl
Diagnostic Data yBM
Diagnostic Data yel
R48DP
4800. bps Data Pump Modem
When information in these lID registers is being discussed, the
format Y:Z:Q is used. The bank is specified by Y(0-2), the register
by Z(O-F), and the bit by 0(0-7, 0 = LSB). A bit is considered to
be "on" when set to a 1.
Definition of Transmitter Configurations:
1. V.27. When any of the V.27 configurations have been
selected, the modem operates as specified in CCITI recommendation V.27.
2. Tone Transmit.
In this configuration, activating Signal RTS
causes the modem to transmit a tone at a single frequency
specified by the user. Two registers in the. host interface
. memory space contain the frequency code. The most significant bits are specified in the FREQM register (0:3). The least
significant bits are specified in the FREQl register (0:2). The
least significant bit represents 0.146484 Hz ± 0.01 Dib.
SOFTWARE SUPERVISORY CIRCUITS
The operation of the R48DP is affected by a number of software
control inputs. These inputs are written into registers within the
modem via a microprocessor bus under external control. Bits
designated by an X are "Don't Care" inputs that can be set to
either 1 or O. Modem operation is monitored by various software
flags that are read from modem registers using the same
microprocessor bus. Bits designated by an X are "undefined"
outputs that may be either 1 or O. The functions of all modem
I/O registers' are listed in the R48DP Interface Memory table arid
are defined as follows:
TRANSMITTER OPTION
The host processor conveys option information to the transmitter by writing a control byte into the Option Register (0:7) in its
interface memory space as shown in the table below:
TRANSMITTER CONFIGURATION REGISTER
The host processor configures the R48DP transmitter by writing
a control byte into the transmitter configuration register (0:6) in
its interface memory space as shown in the following table:
Definition of Transmitter Option Terms:
RTS:
ITDIS:
SOlS:
MHLD:
EDIS:
TPDM:
XCEN:
SEDT:
Definition of Transmitter Configuration Terms:
TNXMT:
TLTS:
TDR2:
TOR 1:
Tone Transmit
Transmitter long Training Sequence
Transmitter Data Rate 2
Selects 4800 bpsN.27)
Transmitter Data Rate 1
Selects 2400 bpsN .27)
Definition of Transmitter Options:
1. Request-ta-Send. The R48DP begins a transmit sequence
when the RTS bit (0:7:7)isturned on arid coritinues transmitting until RTS is turned off and the turn-off sequence has been
completed. This input bit parallels the operation of the hardware RTS control input.
2. Transmitter Training Disable. When the TIDIS bit (0:7:6) is
on, the transmitter does not generate a training sequence
at the start of transmission.
Control bytes for the three configurations are given in hexadecimal format In the following table:
3. Scrambler Disable. When the SDIS.bi~ (0:7:5) is on, the
transmitter scrambler circuit is removed from the data path.
Configuration Control Bytes
No.
1
2
Configuration
Configuration Bytes (HEX)
4800
2400
4800
2400
22
21
02
01
V.27
V.27
V.27
V.27
Long
Long
Short
Short
Tone Transmit
RequesHo-Send
Transmitter Training Disable
Scrambler Disable
Mark Hold
Echo Protector Disable
Transmitter Parallel Data Mode
External Clock Enable
Short Echo Protection Disable Tone
4. Mark Hold. When the MHLD bit (0:7:4) is on, the transmitter input data stream is forced to all marks (1 's).
1mI
5. Echo Protector Disable. When.the EDIS bit (0:7:3) is on, an.
unmodulated carrier. is transmitted for 18.5 ms (optionally
30 ms) followed by 20 ms of no tran~mitted energy at the start
of transmission.
80
10-41
4800 bps Data Pump Modem
R48DP
link Delay Equalizer Selection
6. Transmitter Parallel Data Mode. When theTPDM bit (0:7:2)
is on, the transmitter accepts data for traJ1smission from the
data input register rather than the serial hardware data input.
lDEN
D3l
Curve .Matched
0
X
1
1
0
1
No Equalizer
U.S. Survey long
Japanese 3-Link
7. External Clock Enlble. When the XCEN bit (0:7:1) is on, the
transmitter timing is established by the external clock supplied at the hardware input XTClK (pin 22A).
LOOP/LEVEL
8. Short Echo Protector Disable Tone. When the SEDT bit
(0:7:0) is on, the echo protector disable tone is 30 ms long
rather than 185 ms.
The host processor conveys loopback selection and Iran.smitter output level.to. the modem by writing a c,ontrol. byte intolhe
loopllevel register (0:4) in the interface memory space as Shown
in the following table:
EQUALIZER
The host processor conveys equalizer selection information to
the modem by writing a control byte into the equaUzer register
(0:5) in the interface memory space as shown in the following:
Definition of Loop/Level Terms:
L3ACT:
L4ACT:
L4HG:
TL3-TL1:
L2ACT:
Definition of Equalizer Terms:
CABS1,2:
LAEN:
LOEN:
A3L:
03L:
Definition of Loop/Level ContrOl:
Cable Equalizer (Selects bits 1 or 2)
link Amplitude Equalizer Enable
link Delay Equalizer Enable
Amplitude 3-link Select
Delay 3-link Select
When the l3ACT bit (0:4:7)
is on, the transmitter analog output is coupled to the receiver
analog ii'lput through an attenuatorin accordance with CCITT
recommendation V.54 loop 3.
1. Local Analog Loopback Activate.
2. Remote Analog Loopback Activate. When the l4ACT bit
(0:4:6) is on, the receiver analog input is connected to the
transmitter analog output through a variable gain amplifier.
Definition of Equalizer Parameters:
1. Cable Equalizer. The cable equalizer select bits simultaneously control amplitude and delay compromise equalizers
in both the transmit and receive paths. The following table
gives the possible bit combinations.
3. Loop 4 High Gain . . When the l4HG bit (0:4:5) is on, the loop
4 variable gain amplifier is set for + 16 dB. When l4HG is
off, the gain is 0 dB.
4. Remote Digital Loopback Activate. When the l2ACT bit
(0:4:1) is on, the receiver digital output is connected to the
transmitter digital input in accordance with CCITT recommendation V.54 loop 2.
Cable (0.4 mm diameter) Equalizer Selection
CABS2
CABS1
Cable Length
0
0
0
1
1
1
0
0.0
1.8 km
3.6 km
7.2 km
1
5. Transmitter Level Select 3,2 and 1. Transmitter analog output level is determined by bits Tl3, Tl2, and Tl1 as shown
in the following table:
Transmitter Level Selection
2. Link Equalizer. The .link equalizer enable and select bits
control separate amplitude and delay compromise equalizers
in the receive path. The following tables give the possible bit
combinations.
link Amplitude Equalizer Selection
LAEN
A3l
Curve Matched
0
1
1
X
No Equalizer
U.S. Survey Long
Japanese 3-Link
0
1
local Analog loopback (CCITT loop 3) Activate
Remote Analog loopback (CCITT.loop 4) Activate
loop 4 High Gain
Transmitter level.(Selects bits 3, .2, and 1) .
Remote Digital loopback(cCITT loop 2) Activate
Tl3
Tl2
Tl1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
1
1
0
1
0
1
0
1
Transmitter Analog Output
- 0.5
- 2.5
- 4.5
- 6.5
- 8.5
-10.5
-12.5
-14.5
"Each step is a 2 dB change ± 0.2 dB
10-42
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
± 0.5 dB"
±0.5dB
± 0.5 dB
± 0.5 dB
± 0.5 dB
± 0.5 dB
± 0.5 dB
± 0.5 dB
4800 bps Data Pump Modem
R48DP
TRANSMITTER DATA
Definition of Transmitter Handshake Terms:
The host processor conveys output data to the transmitter in
parallel mode by writing a data byte to the transmitter Data
Register (0:0) in the interface memory space. The data must be
divided on integral baud boundries as shown in the following
table:
TIA:
TSB:
TIE:
TBA:
Transmitter Data Register (0:0)
V.27 2400 bps
Baud 3
Baud 2
I
Baud 1
I
1. Transmitter Buffer Available. The TBA bit goes off when th e
h~t processor writes data to transmitter data register (0:0)
When the transmitter empties register 0:0 the TBA bit is on
Baud 0
2. Transmitter Interrupt Enable. When the host processor writes
a 1 in the TIE bit, the IRQ line of the hardware interface
is driven low when TBA'is on.
NOTE: Data Transmitted Bit 0 First.
FREQM/FREQL
3. Transmitter Interrupt Activ~ Status bit TIA is on wheneve
the transmitter is driving IRQ low.
The host processor conveys tone generation data to the transmitter by writing a 16-bit data word to the FREQM/FREQl registers
(0:3 and 0:2) in the interface memory space as shown in the
following tables:
4. Transmitter Setup Bit. When the host processor changes the
transmitter configuration register, the host must write a 1 i n
the TSB bit. Bit TSB goes to 0 when the change becomes
effective.
'
FREQM Register
Bit 7
215
I Bit 6 I BitS
I 214 I 213
Blt4
212
Interrupt Active
Setup Bit
Interrupt Enable
Buffer Available
Definition of Transmitter Handshake Sequences:
I
Configuration Bit 71Blt 6 BI151 Bit 41 BI131 BI121 Bit 1 Bit 0
V.2748OO bps
X
Baud 1
Baud 0
I
Transmitter
Transmitter
Transmitter
Transmitter
I Bit 3 I Bit 2 I Bit 1 I Bit 0
211 I 210 I 29 I 28
I
FREQL Register
Bit 7
27
I Bit6 I Bit 5
I
26
I
25
Bit 4
24
I Bit 3 I Bit 2 I Bit 1 I Bit 0
I 23 I 22 I 21 I 20
RECEIVER CONFIGURATION
The host processor configures the receiver by writing a contro
byte into the receiver configuration register (1 :6) in the interface
memory space as shown in the following table:
..
The frequency number (N) determines the frequency (Flas
follows: F=0.146484N Hz ±0.01%
Receiver Configuration Register (1 :6)
HexadeCimal frequency numbers (FREQM, FREQl) for commonly generated tones are given in the following table:
I Bil71 Bit 6 I BitS I Bit 4 I Bil31 Bi121 Bit 1 rBilO
I X I X I RLTS I X I X I X I RDR21 RDR1
Commonly Generated Tones
Frequency
FREQM
FREQL
482 Hz
1100 Hz
1650 Hz
1850 Hz
2100 Hz
oC
10
2C
31
38
52
55
00
55
00
Definition of Receiver Configuration Terms:
RLTS:
ROR2:
ROR1.
TRANSMITTER HANDSHAKE
Receiver long Training Sequence
Receiver Data Rate 2
Sele~ts 4800 bpsN.27)
Receiver Data Rate 1
Selects 2400 bpsN.27)
Control words,for receiver configuration are given in hexadecimal
format iri the following table:
'
The host processor performs a handshake sequence with the
transmitter by controlling and testing bits in the transmitter handshake register (O:E) in the interface memory space as shown
in the following table:
Receiver Configuration Control
No.
1
Transmitter Handshake Register (O:E)
10-43
Configuration
V.274800
V.27 2400
V.27 4800
V.27 2400
Long
Long
Short
Short
Configuration Word (HEX)
22
21
02
01
4800 bps Data Pump Modem
R48DP
6. TI2 Equalizer Select. When the T2 bit (1 :7:1) is on, an adaptive equalizer with two taps per baud is used. When T2 is off
the equalizer has one tapper baud.
Definition of Receiver Configurations:
When any of the V.27 configurations has been selected, the
transmitter operates as specified in CCITT. recommendation
V.27.
7. Receiver Training Disable.
RECEIVER OPTION
RECEIVER SAMPLE HANDSHAKE
The host proces.sor conveys option information to the transmitter by writing a control byte into the option register (1 :7) in its
interface memory space. as shown in the following table:
The host processor performs a handshake sequence with the
receiver sample rate device by controlling and testing bits in the
receiver sample handshake register (tE) in the interface memory
space as shown in the following table:
When the RTDIS bit (1:7:0) is on,
the receiver is prevented from recognizing a training
sequence.
Receiver Sample Handshake Register (1:E)
Definition of Receiver Option Terms:
RTH2, 1:
DDIS:
RPDM:
SWRT:
BWRT:
T2:
RTDIS:
Definition of Receiver Sample Handshake Terms:
Receiver Energy Detector Threshold (Bits 2 and 1)
Descrambler Disable
Receiver Parallel Data Mode
Sample Write
Baud Write
T12 Equalizer Select
Receiver Training Disable
RSIA:
RSSB:
RSIE:
RSDA:
1. Receiver Sample Data Available. The RSDA bit goes on
when the receiver writes data into the receiver data register
(1:0). The bit goes off when the host processor reads data
from register 1:0.
1. Receiver Energy Detector Threshold (Bits 2 and 1). The
receiver energy detector threshold is set by bits RTH2 and
RTHI according to the following table:
2. Receiver Sample Interrupt Enable. When the host processor
writes a 1 in the RSIE bit, the IRQ line of the hardware interface is driven low when RSDA is on.
Receiver Energy Detect Thresholds
RTHI
0
0
0
1
1
Q
1
1
RLSD On
>
>
>
>
-43 dBm
-33 dBm
-26 dBm
-16dBm
3. Receiver Sample Interrupt Active.
Status bit RSIA is on
whenever the Receiver Sample rate device is driving IRQ low.
RLSD Off
<
<
<
<
-48
-38
-31
-21
Interrupt Active
Setup Bit
Interrupt Enable
Data Available
Definition of Receiver Sample Handshake Sequence:
Definition of Receiver Options:
RTH2
Receiver Sample
Receiver Sample
Receiver Sample
Receiver Sample
dBm
dBm
dBm
dBm
4. Receiver Setup Bit. When the host processor changes the
receiver configuration or bits 6 or 7 in the option register, the
host must write a 1 in the RSB bit. Bit RSB goes to 0 when
the changes become effective.
2. Descrambler Disable. When the DDIS bit (1:7:5) is on, the
receiver descrambler circuit is removed from the data path.
RECEIVER BAUD HANDSHAKE
3. Receiver Parallel Oata Mode.
When the RPDM bit (1 :7:4) is
on, the receiver supplies data tothe receiver data register (1 :0)
in parallel with the hardware serial data output.
The host processor performs a handshake sequence with the
receiver baud rate device by contrOlling and testing bits in the
receiver baud handshake register(2:E) in the interface memory
space as shown in the following table:
4. Sample Write. When the SWRT bit (1:7:3) is on, the 16-bit
word .in registers 1:1 and 1:0 is written in the RAM location
specified by the oontents of register 1:4.
Receiver Bal,ld Handshake Register (2:E)
5. Baud Write. WhE!f! the BWRT bit (1 :7:2) is on, the 16-bit word
in locations 2:1 an4;2:0 is written in the RAM location specified
by the contents of register 2:4.
10-44
R48DP
4800 bps Data Pump Modem
Definition of Receiver Baud Handshake Terms:
RECEIVER BAUD STATUS
RBIA: Receiver Baud Interrupt Active
RBIE: Receiver Baud Interrupt Enable
RBDA: Receiver Baud Data Available
The host processor has access to status bits that reflect operation of the receiver baud rate device. These bits can be tested
by the host by reading the receiver baud status word (1 :B) in
the interface memory space as shown In the following table:
Definition of Receiver Baud Handshake Sequence:
Receiver Baud Status Register (1 :B)
1. Receiver Baud Date Avelfable. The RBDA bit goes on when
the receiver writes data into regi$ler (2:0). The bit goes off
when the host processor reads data from register 2:0.
2. Receiver Baud Interrupt Enable. When the host processor
writes a 1 in the RBIE bit, the IRQ line of the hardware interface is driven low when RBDA is on.
Definition of Receiver Baud Status Terms:
PNDET: Period N Detector
CDET: " Carrier Detector
3. Receiver Baud Interrupt Active. Status bit RBIA is on
whenever the receiver baud rate device is driving IRQ low.
Definition of Receiver Baud Status Conditions:
RECEIVER SAMPLE STATUS
1.
The host processor has access to various status bits that reflect
operation of the receiver sample rete device. 1hesebits can be
tested by the host by reading the receiver sample status word
(1:8 and 1:9) in the interface memory space as shown in the
following tables:
Period N Detector.
When the PNDET bit (1 :B:6) is off, it indio'
cates a PN sequence has been detected. This bit sets to a
1 at the end of the Pt'I sequence.
2. Carrier Qetector. When the CDET bit (1 :8:0) is off, it indicates
that pasilband energy is being detected anct that a training
sequence is not in process. It goes off at start of data state
and goes to a 1 at end of received signal.
Receiver Sample Status Register 1 (1:8)'
RECEIVER DATA
The host processor acceptS input data from the receiver in
parallel mode by reading a byte from the receiver data register
(2:0) in the interface memory space. The data is divided on integral baud boundries identical to the transmitter data register with
bit 0 received first. Note that the receiver data r$gist", is used
for 'diagnostic data in the serial mode.
Receiver Sample Status Register 2 (1:9)
DIAGNOSTIC CAPABILITIES
The R48DP ptovides the user withactess to much of the data
stored in the moclem's memories. This data is a useful tool in
performing certain diagnostic functions.
Definition of Receiver Sample, Status Terms:
P2DET: Period Two Detector
FED:
Fast Energy Detector
HARDWARE DIAGNOSTIC CIRCUITS
Signal names and descriptions of the hardware diagnostic
'
circuits are given in the followin,g table:
Def.inition'of Receiver S.mple Status Conditions:
Hardware Diagnostic Circuits
1. PerIod Two Detector.
When the P2DET bit (1:8:2)is off, it indicates that a P2 sequence has been detected. This bit sets
,to a 1 at ihe start of the 'receive data state.
',
Nama
EYEX
EY.EY
EYECLK
EYESYNC
2. Fast Energy Deteptor. When the fE.D bit (1:9:6) is off, it lridi. cates thatenergy abOve the receiver threshold is present in
the passband.
'
10-45
110
0
0
0
0
Pin No.
1SC
14A
14C
13A
"
Oel!Crlptlon
E)'II Pattern
- Eye Pattam
Eye Pattem
Eye Pattam
Signal"
Data - X Axis
Data - Y Axis
Clock
Synchronizing
4800 bps Data Pump Modem
R48DP
RAM ACCESS CODES
Eye Pattern Generation - The four h!lrdware diagnostic circuits
allow the uSer to generate and display an eye pattern. Circuits
EYE)(ane;! EYEY serially presenteyepattern.data for the horizontill anc;l vertical display inputs respectively. The 8'bil data words
are shifted out most significant bit first; clocked by the rising
edge of the EYECLK output. The'EYESYNC output is provided
for word synchronization. The falling edge of EYESYNC may
be used to transfer the 8-bit word from thil' shift register to a
hOlding· register. Digital to analog conversion can then be performed fOr driving Ihe X and Y inputs of an oscilloscope.
The following table lists access codes for frlilquently us.ed RAM
data:
' "
.
RAM Access Codes
Bank
1
2
SOFTWARE DIAGNOSTIC CIRCUITS
Each receiver device (sample rate and baud rate) contains six
registers in the interface memory space dedicated to reading
and writing modem RAM locatiOns from the host processor bus.
Four oflhese registers are organized i!'jIO 2-byte data worc;ls .and
the remaining two registers form 1"b~e control registers thatl)old
RAM acce$S codes. Data is read from RAM. into the data
registers. Data is written into RAM from the data registers. The
RAJvt lo.c;atioo involved in .the data transfer is specif,ied by the
R4M access code stored in the associ/lted diagn~lic c.ontrol
register. The diagnoStic registers are relat~ ~ shown in the
following table:'
.
Function
Received Signal Samples
Demodulator Output .
low Pass Filter Outpul
Average Energy
AGC Gain Word - MSB's
AGC Gain Word- LSB's
Equalizer Input
Equalizer Tap Coefficients
Umotated Equalizer Output
Rotated Equalizer Output
(Received Points) .
Decision Points (Ideal Data P!lints)
Error
Rotation Angle.
Frequency C.orr<;!ction (MSB's)
Frequency Correction (LSB's)
EOM
Real
Access
CO
C2
04·
81
Imag.
Access
,42
54
5C
-
-
01
CO
81-AO
El
40
01-20
61
A2
E2
E3
22
62
63
00
-
AA
A1
-
2A
-
POWER.-ON INITIALIZATION·
W.llen power:lsapplied to the R48DP, a period of 100 to 300 ms
is" required for iiliti.alization. the power-on-reset Signal (POR)
remains low during the initialization period. After the low to high
transition of POR, the modem is ready to operate. At POR time
the modem defaults to the following configuration: V.27,
4800 bps, Tl2, long echo protect disable tone, serial data mode,
internal clock, cable select 1.8 Km, amplitude and delay
equalizers enabled and Japanese 3-link curves selected,
transmitter output level'set to- 0.5 dam ± 0.5 dB, interrupts
disabled, and receiver threshold set to -43 dBm.
Software Diagnostic Registers
Control
Device
Register
Write Bit
Sample
Sample
Baud
Baud
XS (1:5)
YS (1:4)
XB.(2:5)
VB (2:4)
None
SWRT (1 :7:3)
None
BWRT (1 :7:2)
Data Word
(MSB)
Data word
(LSB)
XSM
YSM
XBM
YBM
XSl (1:2)
YSl (1:0)'
'XBl(2:2)
YBl (2:0)
(1:3)
(1:1)
(2:3),
(2,1)
"In parallel mode, regIster 1:0 is used for receive data and
POR can also.be used to initialize the users's host,processor~
It may be connected to a user supplied power-on-reset signal
in a wire-or configuration.
not diagnostic data.
PERFORMANCE
Data transfer is regulated by the appropriate data available bit.
Reading always takes place at the designated rate, and data
left in the data registers is overwritten each cycle. When the
associated write bilis set; a wri.te cycle is performed each time
the associated data available bit is off.
Functioning asa V.27 bis/ter type modem, the R48DP provides
the user with unexcelled high performance.
ait error Rates - The Bit Error Rate (BER) performance of the
modem is specified for a test configuration coniorming to that
specified in cCln recommendatioQ V.56, except with regard
to the placement of the filter used to bandliii'lit the while noise
source. Bit error rates are measured af a received line signal
level of -20 dBm as illustrated.
The eight bits of registers 2:3 and 2:1. are continuQusly presented
. serially on hardware interface lines EYEX and EYEY
respectively.
.
10-46
4800 bps Data Pump Modem
R48DP
Phase Jitter -At 2400 bps, the modem exhibits abi! .errorrate
of 1Q-6 or less with a signal-to-noise nitio of 12.5 dB in the
presence of 15°peak-to-~ak phase jitter at 150 Hz or with
signal-to-noisEi ratio of 15 dB in the presence of 30" peak-to-peak
phase jitter at 120 Hz (scrambler inserted).
4800 BPS
V. 27
a
2400 BPS
V.27
\
At 4800 bps
fY.'Zl
bislter), the modem exhibits a bit error rate
of 10-6 or less with a signal-to-noise ratio of 19 dB in the
presence of 150 peak-Io-peak phase jitter at 60 Hz.
INTERFACE CIRCUIT CHARACTERISTICS
DIGITAL INTERFACE CIRCUITS
10 •
Digital Input Characteristics
Input Logic State
AI/owed Input Voltage Levels
O.OV to +O.8V at ~2.5 pA
+2.0V to +5.0V at +2.5 pA
Low
High
Notes
1. The digital inputs are directly nUCMOS compatible. The
capacitive loading on each input ill .25 pF (maximum).
2. Positive current is defined as current into the node.
Digital Output Characteristics
10 '
,
6
8
10 12
14
16
18
20
22
24
26
28
30
Output Logic State
Output Voltage Level
Low
High
+O.4Vat +1.6 rnA
+ 2.4V .at -100 pA
Notes
1. The digital outputs are directly nUCMOS compatible.
Capacitive drive capability is 25 pF.
2. Positive Cllrrsnt is defined as current into the node.
SIGNAL-TO-NOISE RATIO dB
Typical Bit Error Rate Performance
NOISE
SOURCE
GR1381
50 KHZ BW
MODEM
TRANSMITTER
-
LINE
SIMULATOR
-
IMPAIRMENT
SOURCE
BRADLEY 2A
r---
ATTENUATOR
HP 3500
-
ATTENUATOR
HP 3500
-
-
1--'--
MODEM
RECEIVER
1
I
ENGINEERING
MODEM
CONSOLE
L
LEVEL
METER
HP 3552A
NOTE
Signal and noise are measured with 3 kHz flat weighting.
BER Performance Test Set-up
10-47
ENGINEERING
MODEM
CONSOLE
R48DP
4800 bps Data Pump Modem
ANALOG INTERFACE .CIRCUITS
Transmitter. Output Level - The ..transmitter outpu.! level is
adjustable in 2 dB steps from - 0.5 dBm to - 14.5 dBm'accurate
to 0.5 dB. This level is measured at TXA into a 600 ohm
impedance.
±
Receiver Input ohm ±5%.
The receiver input impedance is 63.4K
Auxiliary Transmitter Input - The auxiliary transmitter input
(AUXIN) allows aooess to the transmitter for the purpose of
interfacing with user provided equipment. Beoause this is a
sampled data input, signals above 4800 Hz will cause aliasing
errors. The input impedance is 1K ohm and the gain to transmitter output is OdB.'
R48DP SPECIFICATIONS
Power Requirements
Voltage
+5Vdc
+.12 Vdc
-12 Vdc ..
loleranee
Current (Max)
±5%
±5%
±5%
<700 mA
<20 mA
<80 mA
Note: All volta!}es mu.sl have ripple sO.1 vOlts peak-to-peak.
Environmental
Parameter
Temperature:
OperatingSiorage-
Relative Humidity:
Specification
O°C to + 60°C (32 to 140°F)
- 40°C to + 90°C (- 40 to 176°F)
Stored in heat sealed antistatic bag
and shipping container
Up to 90% noncondenslng. or a wet
bulb temperature up to 35°C.
whichever is less.
Mechanical Information
Parameter
Board. Structure:
Dimensions:
Weight:
Specification
Single PC board with single right
angle header with 64 pins. DIN 41612
or equivalent mating connector.
Width-3.94 in. (100 mm)
Length-4.70 in. (120 mm)
Height-0.55 in. (1.40 em)
LeSs than .22 Ibs. (.08 kg)
10-48
V27P/1
Integral Modems
'1'
Rockwell
V27P/1
HIGH SPEED 4800 BPS MODEM
INTRODUCTION
FEATURES
The Rockwell V27P/1 is a versatile, high performance, 4800 bps
modem on a single printed circuit board. Being CCITT V.27
compatible, the V27P/1 (with minimal interface circuitry) can
operate on dedicated 2-wire or 4-wire half-duplex or 4-wire fullduplex lines. The V27P/1 can also operate in half-duplex on the
general switched network.
•
•
•
•
•
Measuring approximately 9.2 inches (23.3 cm) by 6.3 inches
(16.0 cm), the V27P/1 is the smallest full-feature 4800 bps
modem that approaches data communication theoretical performance limits.
Single printed circuit card
480012400 bps modes
Full-duplex or half-duplex
Dedicated or general switched network lines operation
Ultimate user flexibility:
-CCITT V.27 ter, V.27 bis compatible
-Also 300 bps binary signalling per CCITT T.30
TTL compatibility
Automatic adaptive equalizer
Analog loopback test circuitry
0 to -45 dBm dynamic AGC
LSI signal processing
High reliability
• Low power consumption:
- Typically 3.5 watts
• Automatic training sequence for receiver
•
•
•
•
•
•
The V27P/1 meets the tolerances specified in the CCITT V.27
bis (alternate A), V.27 ter and FSK T.30 specifications. In addition,
the V27P/1 can be configured to be functionally compatible with
those enhanced specifications available in the Rockwell V27P
and M48P modem series.
Document No. 29220N31
10-49
Data Sheet Order No. 631
March 1983
High Speed 4800 BPS Modem
V27P/1
FUNCTIONAL SPECIFICATIONS
":(
TRANSMIT CONTROLS
XMIT
HIGH SPEED DATA INPUT _ _ _ _ _~
LINE
SIGNA.'L
FSK.DATA IN~UT
------------1
FSKDATA OUTPUT
------------1
LOOPBACK
EYE QUALITY _ - - - - - - - ,
RECEIVER
DEVlCE
Rev ,
HIGH SPEED
(jATAOIJTPUT
LINE
SIGNAL
+-''--_ _ _....;._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - '
RECEIVE CONTROLS _ _
V27P/1 Functional Block Diagram
Transmit Carrier and Signalling Frequencies
Carrier Frequency Codex
Compatible QAM:
Carrier Frequency V.2-7:
Echo Suppression Frequencies:
Signalling Frequencies of 1'.30:
tion: At.1200 baud the spectrum is shaped by approximately
a square rool'of 90 percent raised cosine filter function.
1706.667 H:?: ± 0.01 %
1800 Hz ± 0.01"1;'
2100 Hz ±0.01 %
2025 Hz :!: 0.01%
1850 Hz :!: 0.01%
1650 Hz :!: 0.01%
1300 Hz:!: 0.01%
1100 Hz :!: 0.01%
. ·'The 1600 anr;l1200 baud 'configurations require a usable
bandwidth from 950 Hz to 2650 Hz and 1150 Hz to 2450 Hz
respectively.
Data Encoding
At 1600 baud the data stream is divided ,into, groups of three
bits (tribits)~ The data. rate of 4800 bps may use either an 8point QAM structure or 8-phase structure. Encoding of the
., tribits in. tAe 8"phase structure are per CCln Recommendation V.27 ter.
Received Signal Frequency Tolerance
The receiver can receive. freqllency errors of up to ± 10
Hz with less than a 0.2 dB degradation ill Bit Error Rate
.
.
performance.
At 1.200 baUd the data stream is divided into groups of two
bits (dibitS). The data rate of 2400 bps uses a 4-phase data
. structure. Encodh1g of the dibits may be per the fallback rate
. of COm Recommendation V.27 bis and ter (same as V.26A)
or V26B depending on the selected configuration.
Data Signalling and Modulation Rate
At 1600 baud:
Signalling RateData. RateAt 1200 baud:
Signalling RateData Rate-
1600 baud :!: 0.01 %
4800 bps ± 0.01 %
Turn-on, Turn-off Sequences
1200 baud±: 0.01 %
2400 bps:!: 0.01 %
The V27P/1 turn-on sequences are compatible with cCln
Recommendations V.21 bis (allernate i). V.27. and Rockwell
M48P modem specifications.
At 1600 baud the transmitted spectrum is shaped by approximately a square root 01 50 percent raised cosine filter func-
The turn-off sequences for all V.27 modes (except the 1600
baud rate manual V.27 mode) consists.of 5 to 10 millisec-
Transmitted Data Spectrum
10-50
High Speed 4800 BPS Modem
V27P/1
onds of remaining data followed by continuous scrambled 1's
followed by no transmission energy. The period of no transmission energy is provided by turning off the transmitteJ key
signal for a recommended duration of 20 milliseconds.
shown where P1 and P2 are the most significant octal dig~ and P3 through P5
establish the least significant octal digit
shown in the chart.
The turn-off sequences for all non-V.27 modes consists of
4 to 7 milliseconds of remaining data followed by a period of
no transmission energy.
IRC (1 P-5P):
Receiver Configuration Inputs 1 through 5.
These five bits establish the octal code
shown where P1 and P2 are the most significant octal digit and P3 through P5
establish the least significant octal digit
shown in the chart.
IRSS (1 P-2P),
ITSS (1 P-2P):
Receiver Signal Structure and Transmitter
Signal Structure. Where P1 and P2 establish an octal code of 0, 1, 2, or 3. They
define the signal structures as follows:
1 selects a point QAM
3 selects DPSK as:
a-phase at 1600 baud
4-phase at 1200 baud
Ready For Sending Response Times
The Ready For Sending response time to a Request To Send
is determined by the configuration selected and its corresponding training time. In Table 1 the Training Times are
shown in milliseconds. Note, however, that the 1600 baud
manual cCln configurations actually specify the synchronizing sequence timing per CCID V.27 rather than the training
time. Also note the following abbreviations.
ITC (1 P-5P):
Transmitter Configuration Inputs 1 through
5. These five bits establish the octal code
V27P/1 Configurations
No.
Configuration
Transmitter
ITC (1P-5P)
(Octal Code)
Receiver
IRC (1P-SP)
(Octal Code)
22
22
36
20
20
32
22
36
22
20
32
30
Signal
Structure
IRSS (1 P-2P)
ITSS (1 P-2P)
(Octal Code)
Data
Rate
(bps)
Training
Time
(msec)
Carrier
Frequency
(hz)
1,3
1,3
1,3
1,3
1,3
3
4800
4800
4800
4800
4800
4800
NOTE
NOTE
NOTE
NOTE
NOTE
1800
1800
1800
1800
1800
1800
1800
1.
2.
3.
4.
5.
6.
1600
1600
1600
1600
1600
1600
7.
1600 Baud Manual cCln
30
30
3
4800
1600 Baud V27 DIALJP-P
1600 Baud V27 DIALJP-P E P
1600 Baud V27 DIALJP-P - T/2
1800 Baud V27 DIALJP-P - T/2 EP
1600 Baud V27 Mullipoint - T/2
1600 Baud V27 Resync (use with
configuration 8)
1600 Baud V27 Resync EP (use
with configuration 9)
1600 Baud V27 Resync - T/2 (use
with configuration 10)
1600 Baud V27 Resync - T/2 EP
(use with configuration 11)
1200 Baud DIAL
1200 Baud pop
1200 Baud V27 DlALJ P- P
1200 Baud V27 DIAl1P-P EP
1200 Baud V27 Mullipoint
1200 Baud V?7 ReSync (use with
configuration 19)
1200 Baud V27 Resync EP (use
with configuration 20)
23
27
23
27
21
21
23
23
33
33
27
25
3
3
3
3
3
3
4800
4800
4800
4800
4800
4800
181
181
221
141
141
20 (Sync
Sequence)
50 (Sync
Sequence)
708
923
708
923
50
50
25
25
3
4800
265
1800
21
35
3
4800
50
1800
25
35
3
4800
265
1800
14
10
13
17
11
11
10
10
11
11
15
13
3
3
3
3
3
3
2400
2400
2400
2400
2400
2400
170
117
943
1158
66
66
1800
1800
1800
1800
1800
1800
15
13
3
2400
281
1800
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
Note:
Baud
Baud
Baud
Baud
Baud
Baud
DIAL, cCln DIAL
DIAL - T/2
DIAL Slow
pop
pop - T/2
Manual cCln
Carrier frequency is 1706 2/3 Hz when IRSS (1 P-2P) is a 1 (S-point).
Carrier frequency is 1800 Hz when IRSS (1 P-2P) is a 3 (8-phase DPSK).
10-51
1800
High Speed 4800 BPS Modem
V27P/1
Received Line Signal Detector (0109)
+,V
A.
The tiine response cif the Received Line Signal detector circuit (D109) is a function of the length of the received turn-on
sequence. Circuit 0109 turns 'on after synchronizing is completed and prior to user data appearing on the received
output line. 0109 turns on for approximately 2 milliseconds
after the echo protect tone disappears in the V27EP configurations (No.9, II, 14, 16, 20 and 23 of the V27P/l Configuration, Chart).
1----- - ----,
15.
I
'0'
I
V27./1
I
I
I
1
1
I
I
I
I
I
I
THAESH1
I
orTHRESH2
For non-CCITI configurations (No. I, 2 and 3 in the table on
pa~El 3), 010,9 m()mentarily goes on at the beginning of the
synchronizinp sequence.
I
I
-'2V
I
L _______ -1I
When no synchronizing signal iI!, .detected at the receiver,
0109 turns onin5 to15 millisEjConds for an applied signal
greater than 3 dB above the turn an threshold. If training is
not enabled at the receiver, 0109 turns on in 5 to 15
milliseconds.
+'V
B.
20•
......-.J\.J'''' __
~
THRESH1 or 2
Three threshold options are provided: ,
c.
1) Greater than -43 dBm:
Less than -48 dBm:
0109 ON
0109 OFF
2) Greater than -26 dBm:
Less than - 31 dBm:
0109 ON
0109 OFF
[;]1---1
3) Greater than -16 dBrn:
Less than -21 dBm:
0109 ON
0109 OFF
+'V~,
>0"
,
The three threshold options are controlled by the condition
of the THRESHI and THRESH2 control lines as indicated
below.
dB LEVEL
-43dBmON
-26 dBm ON
-16 dBm ON
THRESHI
THRESH2
Open Circuit
Open Circuit
o to -0.5V
Open Circuit
Oto -0.5V
Open Circuit
+5V
roo
20K
>,,---0._ _
THRESH1 or 2
-12V
Suggested Interface Circuits for Controlling
THRESH1 and THRESH2 Input Lines
Data Scrambler Selection
When the received signal drops 5 dB below the 0109 turn
off threshold, 0109 will turn off in 5 to 15 rnilliseconds. The
condition of 0109 between the selected turn on and turn off
thresholds is notspecified except that a hysteresis action of
greater than 2 dB exists between the off-to-on and on-to-off
transition levels.
'
The V27P/l makes available to the user one CCITI V.29
compatible scrambler, five di,fferent period 127 scramblers
(and descrarnblers), and a no scramble option. These scramblers provide data transmitted by the V27P/l with the degree
of randomness necessary to ensure the continued convergence of all adaptive processes at the receiver. The seven
possible. scrambler configurations that are user software
selectable are:
Recommended circuits to control THRESH 1 and THRESH2
input interface lines are shown in diagrams (A, B and C).
The V27P/l is thoroughly tested to guarantee Bit Error Rate
(BER) performance under test conditions equivalent to ccm
Recommendation V.26. The test set-up used by Rockwell is
shown in the BER Performance Test Set-up diagram.
• Period 127 cryptographic
• Period 127 synchronizing
• CCITI period 127 self synchronizing
CCITI Recommendation V.27)
• Period 8,388,607 self synchronizing
CCITI Recommendation V.29)
• Period 127 self synchronizing with 8-bit
• CCITI period 127 self synchronizing
CCITI Recommendations V.27 bis and
• No scrambler
The resuHs of these BER perforrnance tests are shown in the
Typical Bit Error Rate Performance diagram.
All scramblers can' be used wllh, all modem configurations
listed in the table on page 3.
Bit Error Rates
10-52
(compatible with
(compatible with
protection
(compatible with
ter)
High Speed 480,!~BPS Modem
V27P/1
MODEM
TRANSMITTER
-
LINE
SIMULATOR
I
f----
NOISE
SOURCE
GRl381
50 KHZ BW
I--
ATTENUATOR
HP 3500
IMPAIRMENT
SOURCE
BRADLEY 2A
f---
ATTENUATOR
HP 3500
'-
L
-,,"-
LEVEL
METER
HP 3555B
MODEM
RECEIVER
I
NOTE
THE V.56B CONFIGURATION INCLUDESAPERFECTO.3TO 3.4 KHz FILTER
ON THE NOISE SOURCE. TO ACHIEVE THE SAME EFFECT IN THIS
CONFIGURATION. THE LEVEL METER USES 15 KHz FLAT WEIGHTING AND
S.B5 dB IS ADDED TO THE MEASURED SIN RATIO.
ENGINEERING
MODEM
CONSOLE
ENGINEERING
MODEM
CONSOLE
BER Performance Test Set-up
.
.
I
without a training sequence, but it isa manual mode requiring
considerable user effort. In a train ing mode, an internally
generated pattern is transmitted to the receiver to facilitate
synchronization. During the training mode, the data input line
to the receiver is ignored and the output line does not reflect
the state of the data input.
"
I
I
\
\
In the data mode of operation, information on the data input
is strobed· by the transmitter signal elelnent clock and transmitted to the !'8ceiver. The receiver demOdulates and decodes
the passband signal and outputs the recovered'data on the
output where it is then ready to be strObed by the receiver
signal element clock .
\
.,
Request To Send-Ready For Sending
,
. II .
, ,
"
~8
To initiate transmitter operation in the data or training mode,
the Request to Send input is brollght high. If a training mode
is not initiated the Ready for Sending indicator goes high
within one baud interval and data transmission commences.
20
The mode of the receiver is indicated by the data channel
received line signal detector (0109). For data mode, D109
is hig" and the receiver training mode indicator is low;
Typical Bit Error Rate Performance
MODES OF OPERATION
If the receiver enters the training mode, the receiver training
mode inc;licatar goes high until the training mode is completed. When training is completed the receiver training mode
indicator goes low and, if sufficient signal energy is present
on the input line, 0109 goes high, enabling the data mode.
The V27P/1 has two modes of operation; a training mode
and a data mode. In order for the receiver to correctly decode
the transmitted data the V27P/1 must detect the' presence
of a line signal, adjust the AGe, detect the presence of a
training sequence, recover the baud timing of the transmitter,
phase and frequency lock to the carrier associated with the
received Signal, and adapt the equalizer to the amplitude and
delay characteristics of the channel. This learning process
is accomplished most efficiently when the transmitter initiates
a training sequence whenever a new transmitter-receiver
connection is made. It is possible to set up the receiver
Training Mode-Dial and Point·To-Point
For dial and point-tc-point configuratIOns, the V27P/1 receiver
training is automatically initiated whenever a training sequence
is detected in the received line signal. The training sequence
consists of two phases: Phase 1 causes the training detector
to turn on and alsc makes a course adjustment of the carrier
10-53
mII
High Speed. 4800 BPS Modem
V27P/1
frequency variable which compensates for any frequency
translation due to the channel; Phase 2 is used to converge
the adaptive equalizer which is part of the V27P/1 structure.
the code shown in Table 1. Manual configuration code octal
30 has a longer synchronizing sequence than configuration
code octal 32, but both synchronizing sequences conform
to the CCITT Recommendation V.27. However, neither sequence is of sufficient duration to aid in training the receiver.
A short scrambler synchronization sequence follows Phase
2 and is used to generate the success indicator. In order for
training to be successful, the incoming training sequence
must have been generated by a similarly configured transmitter using a compatible training sequence.
Receiver Operation During Loss of .Line Signal
When there is no line signal present, all receiver update
relating to the equalizer, carrier frequency variable and baud
timing are inhibited and the current values of the equalizer
taps and the carrier frequency variable are retained.
At .the receiver, detection of a training sequence requires that
there be sufficient signal energy and that the receiver's carrier frequency variable be within 30 Hz of nominal.
Training Resync (V_27 bls/ter Turnaround)
DATA QUALITY
In a 2-wire half duplex data communication system, data can
be transmitted in only one direction at any given instant
Therefore, the modems at the local and remote sites are
required to interchange their roles as the receiver and the
transmitter respectively. This turnaround operation requires
constant resynchronization to meet CCITT Recommendations for V.27 bis/ter.
The receiver generates an Eye Quality Monitor (EQM) signal
tharcan be used to determine the equivalent Gaussian signal
to noise ratio of the overall system within approximately ±
2 db. Eye quality is determined by calculating the difference
between the received signal point after equalization and the
transmitted or expected signal point. The receiver output
DEQ2P is a filtered version of this error signal. It is a serial
word clocked by the system bitc.lock (345.6 KHz or 230.4
KHz, depending on baud rate). Output signal DQGTP is a
gating signal which delineates the eight MS8's of DEQ2P.
The use and interpretation of these binary Signals are qUite
complex and are dependent on the application and the signal
structure. The user can derive a meaningful interpretation of
the EQM readings by monitoring them while testing the
modem against his performance criteria.
The resync configurations are used for reacquiring synchronization in turnarOl,lnd operation without having to go through
the normal long training sequence . .The resync training
sequences are relatively short and are used for recovering
carrier phase, symbol timing and achieving equalizer convergence without resetting carrier. frequency and. equalizer
taps.
Training Mode-Multipoint
Visual Display of Eye Pattern
In the V27P/1 modem, two multipoint configurations are provided for 4-wire circuits conforming to M1020 which permit
short training sequences. In these configurations, the first
train signal must be high to process the short training
sequences; otherwise the receiver will ignore the training
sequence and enter directly into the data mode, The receiver
will enter into the training mode if the first train signal is high
and there is sufficient signal energy.
A visual indication of the modem's performance can be
obtained by displaying the received baseband signal structure after equalization. This is done by oonverting the eight
MSB's of the. real and imaginary equalized signal points
available on DRERP and DIERP to analog voltages which
are then used to drive the horizontal and vertical sweeps of
an oscilloscope. The resultant display will be a symmetrical
dot pattern of 16 points, 8 points, or 4 pOints which is a time
representation of the received baseband signal. Any uncompensated distortion over the transmission path will cause
each dot in the pattern to enlarge or otherwise show distortion. A typical visual eye pattern of a 4 point display is shown
in the following diagram.
For 4-wire circuits which are worse than M1020 and for
2-wire cirCUits, along training sequence should be used
rather than the multipoint configuration. These training
sequences require that the receiver be in tt)e proper dial!
point-to-point configuration.
Training Mode"";Manual
The V27P/1 modem includes two manual configurations in
which the remote modem need not transmit a special training
sequence to the local receiver. In these configurations, the
equalizer tap coefficients for the local receiver must be initializedfrom an external source. The tap coefficients may be
initialized by controlling three inputterms-ICR, ICI aild
ICLCP-in synchronization with the Baud Rate Clock.
DISPERSION DUE
TO PHASE ERRORS
DISPERSION AROUND
PROPER POSITION DUE
T.0 COMBINATION OF
RANDOM NOISE, PHASE
ERROR, AND/OR GAIN
ERROR
CIRCLE REPRESENTS
PROPER POSITION OF
HIGH QUALITY SIGNAL
In order to operate the modem in the manual configurations,
both the transmitter and receiver must be set according to
Typical Eye Pattern
10-54
V27P/1
High Speed 4800 BPS Modem
.
"
.,.
,"
Success Indicator
Tone Generation And Oetecticm
A second data quality indicator is provided for in all configurations except the 1200 baud non-V.27 modes. This signal
provides a rough indication that the training has been SI,lCcessful and that data will be properly received. This "success" output (DSUCP) will go high during the last one to
twenty milliseconds of receiver training, provided training has
been successful. During the data mode (DRTMP low and
0109 high), DSUCP will go high whenever 15 consecutive
da~ marks or spaces are decoded at the rec;eiver data
output.
The transmitter can be used\o:transmit single frequern:;y
tones for disabling echo suppressors' or for system signalin'g.
Tone that can be transmitted{sele,Cted throughsottwarE\co~
trol) are: 1100 Hz, 1300 Hz, t6?0 Hz, 1850 HZ,2025 Hz, and
2100 Hz. Other tones are alSO possible. The carrier frequency can be altered by selection of values for a binary bit
stream.
External Data Clock
The data input to ,the transmitter can be clocked from an
eXternal source when the external clock is usee as iI. referenqe inp,ut to the data clock's phase locked l(lop. By applying
an' external clock the reference input will cause the transmitter data clock to track the freqUency and phase of the refe
erence. The frequency of the reference clock must be within
100 ppm of nominal il] ,order for the receiver's baud timing
to properly track that of the transmitter. The reference clock
can be equal to the nominal data clock frequency or be a
subharmonic of it as long as the frequency tolerance is
adhered to.
ADDITIONAL CAPABILITIES
The V27P/l provides many additional capabilities germane
to data communication system design and implementation.
Capabilities such as local loopback, tone generation and
detection, external clock facilities, and 300 bps FSK operation are briefly described in the following paragraphs.
300 bps FSK Modem Operation
Local Loopback Capability
A CCITI T.30 compatible 300 bps FSK modem having characteristics of theCCITI V.21 channel 2 modulation system
, can also be configured. The FSK modem. is capable of generating the 1100, 1300, ·1650 and 1850 Hz tones;
A localloopback option is available for all half duplex, and full
duplex modem configurations. Th,e Local Loopba<;k Command (ILB) connects the transmitter's outp~ through a buffer
amplifier to the receiver input, thereby allowing a check of
the local modem. The ILB col1)mand squelches the input to
the receiver and loops the analog signal from the transmitter
to the receiver inpUt.
An internal pattern gerierator is also inc;:orpor;!.ted in the
modem which can be used' when no modem' test set is
available.
SPECIFICATIONS
V27P/1 ,Specifications
DC Voltage.
Voltage
+ S volt
+12 vott
-12vott
Toleranee
Current (Typical)
Curren. (Max)
1.3Sfna
40ma
17Sma
<200 ma
< 70ma
<230 ma
,
±5'1'0
±S%
±S%
Note: All voltages must have ripple ..0.1 voltspeak-to-Peak,
,
EnYI~nll\8l\t '
Temperature:
..
Relative Humidity:
OPera\ing:~q:!O+~C (32 to ,140'FJ
Storage: , ~49'Glo +!ltt',c .<"-40 to 176'F) ,
(Stored In ,heat sealedlll1~static bag and shipping container)
•Up to 90% nonCj)ndimsing,
a .wet bulb temperature up to 3S'C, whichi~ less.
..
or
ever
Mtic,hanl~ .
Board Structure;
Mating Conn8ctor:
Dimensions:
Weight:
Single PC board with edge CQnnector
10Qt:iin;ildge CQnn8Ctor, two sided, with.0.1 In (2.54 em) cenlers. Raeoritmeni!ed Viking 3VHSO/IJND5 or equivalent mating connector.
Width":':9.188in (23.338 em) Depth-6,288 in (15.972 em)
Less than 0,45 Ibs (0.20 kg)
10-55
R1212
Integral Modems
'1'
Rockwell
R1212
1200 BPS FULL-DUPLEX MODEM
PRELIMINARY
INTRODUCTION
FEATURES
The RockWell R12121s a high performance fUlI-duplex 1200 bps
modem: Using state-of-the-art VLSI and signal processing
technology, theR1212 provides the user with enhanced performance and reliabilitY on a-single printed circuit board of less than
'
22 square-inches':""overall size.
•
•
•
•
•
The R1212 modem is ideal for data transmission over the 2-wire
dial-up telephone network. The direct-connect, auto dial/answer
features are-speCifically designed for remote and central ,Site
computer applications. The bus int4il$ce allows e~y integration into a personal computer, box modem, microcomputer,
terminal or any other communications prQduct that demands the
utmost in reliability and performance.
-"
-
•
•
•
The added test features, such as local analog loopback, remote
digitalloopback,anda self"test function, offer the userflexibility in crelilting a 1200 bps modem design clJstomizedfor specific
packaging and functional requirements.
•
•
•
•
•
•
Being CCITT V.22 A, B compatible, as well as Bell 212A and
103 compatible, this modem fits any application for full-duplex
1200 bps (synchronous and asynchronous) and 0, to 300 bps
asynchronous data transmission over the general switched
telephone network.
CCITTV.22 A, B Compatible
Bell 212A and 103 Compatible
Synchronous: 1200 bps, 600 bps ±0.01 %
Asynchronous: 1200 bps, 600 bps + 1%, - 2.5%, 0-300 bps
-Character length 8, 9, 10, or 11 bits"
DTE Interface
'
-Functionally: Microprocessor Bus (Control) and RS-232-C
Interface (Data/Control)
-Electrically: TTL Compatible
Operation: 2-~ire full-duplex
Adaptive and Fixed ,Compromize Equalization
Test Configurations: '
-Local AnalOj;l" Loopback
-Remote Digital l.oQpback
-Self Test'
Auto/Manual ~nswer'
Auto/Manual Dial:
-Tone Qr' Pulse Dial,
Power Consumption: 3 Wa~ Typical
Power Requirements: +5 Vdc, ± 12 Vdc
Plug-compatible member of new ROckwell modem line
Two Versions: R1212DC (Direct Connect) with FCC approved
OM Part 68 Interface and R1212M (Module) without OM
R1212 Full-OuplexModem
Document No. 29200N10
10·56
Data Sheet Order No. MD10
Rev. 1 January 1984
R1212
12QO bps Full-Duplex Modem
TECHNICAL SPECIFICATIONS
below the level of the main channel power, and again the
overall power transmitted to the line should remain constant
whether or not a guard tone is enabled. The device
acComplishes this by reducing the main channel transmit path
gain by .97d6 and 1.76d6 for the cases of the 1800 Hz and
553.846 Hz guard tones respectively.
3. DTMF Tones: The R1212 is capable Of generating dual tone
multi-frequency tones. When theiransmlsslon of DTMF tones
are required, the CRO and DTMF bits must be set to a 1.
(see Interface Memory). When In this mode, the allecilic
DTMF tones generated are decided by loading transmit
register with the appropriate digit as shown in the fOllowing
table:
Interface Memory Slgna,l
The following are the technical specifications for the R1212
modem.
TRANSMITTER CARRIER AND SIGNALING
FREQUENCIES
The transmitter carrier and signaling frequencies are given in
the following .table:
Transmitter Carrier and Signaling
Frequenclea Specifications
Frequency
V.22 low channel. Originate Mode
V.22 high chennel. Answer Mode
Bell 212A high channel Answer Mode
Elell 212A low channel Originate Mode
Bell 1031113 Originating Mark
Bell 103/113 Originating Space
Bell 103/113 Answer Mark
Bell 1031113 Answer Space
SpecHlcatlon
(Hz :1:0.01%)
1200
2400
2400
1200
1270
1070
2225
2025
BCD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TONE GENERATION
The specifications for tone generation are as follows:
1. Anlwer Backton.l: The R1212 is capable of generating
e¢ho disabling tones both of the CCITT and Bell versl~ns,
as follows:
a. CCITT: 2100 Hz :1:15 Hz.
b. Bell: 2225 Hz :I: 10 Hz.
2. Guard Tones: If
is low, an 1800 Hz guard tone frequency
Is selected; If GTS if high, a 553.846 Hz tone is employed.
In accordance with the CCITT V.22 Recommendation, the
level of transmitted power for the 1800 Hz guard lone should
be 6 :I: 1dB below the level of the data pow.r III the main
channel. The total power Is transmitted to the line should be
the same whether or not a guard tone Is enabled •. I.f a 553.846
Hz guard is us.d, Its transmitted power should b.3 :I: 1dB
ens
Operatlnl Mod.
V.22'
(Alternative A)
Mode I
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Dill Dlglta
0
1
2
3
4
5
6
7
8
9
*
Spare (8)
Spere (C)
Spare (0)
/I
Spare (F)
The R1212 can detect tones in the 340 to 645 Hz band.
SIGNALING AND DATA RATES
The signaling and data rates for the R1212 are defined In the
table below:
Signaling and Data Rate.
811111111ng Rate (SIUd)
Dati Rite
1200 bps :1:0.01% Synchronous
600
600 bps :I: 0.01 % Synchronous
Mode iii
600
600
1200 bpe :l:0.01OM1 SynChronous
600 bps :l:0.01%-Synchronous
Modell
600
1200 bpe Asynchronous
(Alternative Bl
Model
8, 9, 10, or 11 Bits Per Character
600 bps Asynchronous
6, 9, 10, or 11 Bits Per Chllracter
MOde Iv
Be1l212A
Palra
1336
1209
1336
1477
1209
1336
1477
1209
1338
1477
1209
1833
1833
1833
1477
1833
TONE DETECTION
600
Mode iii
Tona
941
697
697
697
770
770
770
852
852
852
941
697
770
852
941
941
600
1200 bps :1:0.01%
SyhchronouslAsychronou8
o to 300 ·Bps Asynchr~)AOU8
o to 300
10-57
R1212
1200 bps Full-Duplex Modem
Transmit Level
OAT A ENCODING
Configuration Word
The specifications for data encoding are as follows:
1. 1200 bps (V. 22 and Bell 212A). The transmitted data is divided
into groups of two consecutive bits (dibits) forming a four-point
signal structure.
2. 600 bps (V. 22). Each bit is encoded as a phase change
relative to the phase preceding signal elements.
EQUALIZERS
o dbm
1
-2 dbm
010
-4 dbm
o1
-6 dbm
1
100
-8 dbm
o1
-10 dbm
1 1 0
-12 dbm
1 1 1
-14 dbm
1
The R1212 provides equalization functions which can be used
to improve performance when operating over poor lines.
Transmit Level
0
o0
o0
PERMISSIVE/PROGRAMMABLE CONFIGURATIONS
Automatic Adaptive Equalizer-An automatic adaptive
equalizer is provided in the receiver circuit for V.22 and Bell 212A
configurations.
The R1212M transmit level is set to 0 dBm to allow a DAA to
be used. The DAA would then determine the permissive or programmable configuration.
Fixed Compromise Equalizer-Compromise equalizers are provided in the transmitter and receiver.
The R1212DC transmit level is strapped in the permissive mode
so that the maximum output level is - 9.5 dBm ± 0.5 dBm.
TRANSMITTED DATA SPECTRUM
TRANSMIT TIMING
After making allowance for the nominal SPElcified compromise
equalizer characteristic, the transmitted line signal has a frequency spectrum shaped by the square root of a 75 percent
raised cosine filter. Similarly, the group delay of the transmitter
output is within ± 100 microseconds over the frequency range
800 to 1600 Hz (low channel) and 2000 to 2800 Hz (high
channel).
The R1212 provides a Transmit Data Clock (TDClK) output with
the following characteristics:
1. Frequency. Selected data rate of 1200 or 600 Hz (±0.01%).
2. Duty Cycle. 50 ± 1%.
Transmit Data (TXO) must be stable during the one microsecond
periods immediately preceding and following the rising edge of
TDClK.
SCRAMBLER/DESCRAMBLER
CLAMPING
The R 1212 incorporates a self-synchronizing scramblerl
descrambler. In accordance with the CCITI V.22 and the Bell
212A recommendations.
The following clamp is provided with the R1212:
1. Receive Data (RXD). RXD is clamped to a constant mark (1)
whenever RLSD is off.
RECEIVED SIGNAL FREQUENCY TOLERANCE
RECEIVED LINE SIGNAL DETECTOR
The receiver circuit of the R1212 can adapt to received frequency
errors of up to ± 7 Hz with less than a 0.2 dBm degradation in
BER performance.
The high and low channel thresholds are greater than - 45 dBm
(ALSO on) and less than - 48 dBm (RlSD off) for V.22 and Bell
212A configurations.
DATA SET READY
RECEIVE LEVEL
The on condition of the R1212 output Data Set Ready (DSA)
indicates that the modem Is in the data transfer state. The off
condition of OSA is an indication that the DTE is to disregard
all signals appearing on the interchange circuits-except the calling indicator and the test signal. DSR will switch to the off state
when in test state. The on condition of DSR indicates the
following:
The receiver circuit of the R1212 satisfies all specified performance requirements for the received line signals from - 12 dBm
to - 45 dBm. The received line signal is measured at the receiver
analog input RXA.
RECEIVE TIMING
The R1212 provides a Receive Data Clock (RDClK) output in
the form of a (50 ± 1% duty cycle) squarewave. The low to high
transitions of this output coincide with the center of received data
bits. The timing recovery circuit is capable of tracking a ± 0.01 %
frequency error in the associated transmit timing source.
1. The modem is not in the talk state, i.e., an associated
telephone handset is not in control of the line.
2. The modem is not in the process of automatically establishing
a call via pulse or DTMF dialing.
3. The modem is generating an answer tone or detecting answer
tone.
4. After ring indicate goes on, DSA waits at least two seconds
before turning on to allow the bell equipment to be engaged.
TRANSMIT LEVEL
The R1212M output control circuitry contains a variable gain
buffer which reduces the modem output level. The R1212M can
be strapped via the host interface memory to accomplish this.
DSR will go off 50 msec after OTR goes off or 50 msec plus a
maximum of 4 sec when SSO is enabled.
10-58
1200.bps Full-Duplex Modem
.
r------,
I~
I
I
I
I
I
I
I
I
I
;
.CTS
TXD
......
USART
(OPTIONAL)
.A,..,
lDC,"K
l~
XTCLK
(".
RLSD
I
I
RXD
RDCLK
I
'TBCLK
I
L_-_. J~,,_J
-
.~~
.,.,
~
,..
,..
MODEM
RBCLK
+5V
READ
.....
DATA .BUS (8)
,
I
CS (2)
RS(O:3)
-,,--
RXA
LINE
INTERFACE
'-'
DECODERI'
(
POR
(",~
IRQ
+5
TXA
0(0:7)
ADDRESS BUS (4)
AAA
POWER
SUPPLY
GND
-12V
WRITE
HOST
PROCESSOR
(OTE)
+l1V
~}
.--
TELEPHONE
LINE
"0
/'1)
I
..
R1212 Functional Interconnect Diagram
DATA TERMINAL READY
CONTROL SELECTION
An on condition of OTR prepares the modem to be ~onnected
to the communications channel, and maintains the connection
established by the OTE (maryual answering) or internal
(automatic answering) means. The off condition places the
modem in the disconnect state.
SelectiOn of either the s!"rial or parallel control is by means of
bits ([0,1):0:7). To enab.le the parallel control, the bits must be
setto a one. In Elithermode;the R1212 is configured by the host
processor via the microprocessor bus.
INTERFACE CRITERIA
The modem interface ,comprises both hardware and softWare
circuits. Hardware circuits ~re assigned to spElcific pins. in,a
64-pin DIN connector. Software circuits arEl ~!ligned to specific
bits in a 32-byte intElrface memory.
MODES OF OPERATION
The R1212 is capable of being operated in either a serial or a
parallel mode of operation,
HARDWARE SUPERVISORY CIRCUITS
Signal names and descriptions of the hardware sUJJ8rvisory
circuits, includIng the microproce$SOr interface. are. given in the
following table. The microprocessorinterface.was designE!dto
be compatible with an .8080,6500, 6800, and ()8000
microprocessor.
SERIAL MODE
ThElserial mode uses standard V.24 (RS-232-C compatible)
signals to transfElr channel data. An optional USART device
(shown in the diagram above) illustrates this capability.
10-59
1200 bps Full-Duplex Modem
R1212
R1212 Harcjware Supervisory Circuits
Name
Type
Pin No.
WRITE
Deecrlptlon
CSI
(I = 0,1)
A.OVERHEAD
DGNO
G
AGND
+5 VDC
G
P
+12 VOC
.=,.gVDC
POR
P
P
OC
5A, lOA,
3C,8C
31C,32C
19C, 23C,
26C,30C
15A
12A
13C
t
Digital Ground
Analog Ground
+ 5 Volt Supply
+ 12 Volt Supply
-12 Voll Supply
Ij'o~r-on-Reset
B. MICROPROCESSOR INTERFACE
07
06
05,
04
03
02
01
DO
RS3
AS2
RSl
RSO
CSO
CS1
READ
WRITE
IRQ
B
B
B
B
B
B
B
B
I
I
I
I
I
I
I
I
OC
1A
2C
'C
2A
3A
4C
4A
5C
6C}
6A
7C
7A
10C
9C
12C
11A
llC
Data Bus (B-Blts)
READ
. Aeglster Select (4-Bits)
01
(i
Chip Select for Bank 0
Chip Select for Bank 1
Read Enable
Write E:nabfe
Interrupt Request
=,0 _7)-----'0
Microprocessor Intertace Timing Diagram
C. V.24 INTERFACE
XTCLK
TDCLK
RDCLK
CTS
TXD
RXD
RLSD
DTR
DSR
RI
I
0
0
0
I
22A
23A
21A
25C
240
22C
24A
21C
20A
18A
External Transmit Clock
Transmit Data Clock
Receive Data Clock
Clear-to-Send
Transmit Data
Receive Data
Received Line Signal Detector
Data Terminal Ready
Data Set Ready
Alng Indicator In
Critical Timing Requirements
Symbol
Min
CSi, RSI setup time prior
to Read or Write
TCS
30
Data Access time aiter Read
TDA
D. ANALOG SIGNALS (R1212M ONLY)
Data hold time aiter Read
TDH
RXA
TXA
CSi, RSI hold time aiter
Read or Write
0
0
I
0
0
I
0
32A
31A
Characteriatlc
Receive Analog
Transmit Analog
E. SIGNALS TO OM (R2424M ONLY)
RD
RCCT
CCT
OH
I
0
I
0
27A·
28A
29C
29A
Ring Detect
Request Coupler Cut Through
Coupler Cut Through
Off-Hook Relay Control
TBCLK
RBCLK
TLK
·ORG
B
I
0
OC
P
G
0
0
II
27C
26A
28C
16C
Transmit Baud ClOck
Aecelve Baud Clock
Talk TLK
Data
Originate ORG
Answer
=
=
BidirectiOnal
Input
Output
Open Collector
Power
Ground
10-60
Units
NS
140
NS
50
NS
TCH
10
NS
Write data setup time
TWOS
75
NS
Write dats hold time
TWOH
10
NS
TWR
75
NS
Write strobe pulse width
F. ANCILLARY FUNCTIONS
10
Max
R1212
1200 bps .Full-DuplexModem
INTERFACE MEMORY
When information in these registers is being discuSsed, the
format Y:Z:Q isu~d. The bank is specified by Y (0 or 1), the
LSB). A bit is
register by Z (O-F), and the bit by Q (0-7, 0
considered to be 'on' when set toa one.
The R1212 has two banks of 16 registers to which an external
(host) microprocessor has access. Altho'ugh these registers are
within the modem, they may be addressed as part of the host
processor's memory space. The host may read data otltof or
write data into theSe registers. These registers, as shown in the
following table, are referedto as int~rface memory.
=
.
.
R1212 Interface Memory
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Flag No.
(HEx)
0
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F
DeScription
....nk
Do Not Use
00 Not Use'
Diagnostic Data Real LSB's
Diagnostic Data Real MSB's
Diagnostic Data Imaginary LSB's
Diagnostic Data Imaginary MSB's
Do Not Use
Do Not Use
Receiver Status
Receiver Status
Configuration
Configuration
Configuration
Configuration
' Handshake Stiltus
Diagnostic Control Register
1
.1.
·1
1
1
1
1
1
1
1
1
1
1
1
·1
1
Reg No.
(HEX)
0
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F
. Description
Dial Digit Registar
Do Not Use
Dlagnostlc'Data Real LSB's
Diagnostic Data Real MSB's
Dlagnosiic Data Imaginary LSB's
Diagnostic Data Imaginary MSB's
Do Not Use
Do Not Use
Transmitter Status
Configuration
Configuration
Configuration
Configuration
Configuration
Hand$hake Status
Diagnostic Control Register
The interface memory bits are defined in the following table:
Interface Memory Definitions
Name
Definition
"'emorY
Location
Description
When on,' Me causes the modem to automatically answer whan a ringing' Signal
is present on the line.
ME
Auto Answer Enlll1le
AL
Analog Loopback
(O,1):B:0
When on, AL places the modem in analog loopback. (See Software Diagnostic
Circuits).
BUS
Bus Selee,t
(0,1):0:7
.. When on, BUS places the modem,in the parallel control mode;When off, the
modem Is configured tor the serial control mode. Bus can be In either state to
cOnfigura the modem.
CHAR
Character Length select
CRQ
Call Request
(0,1):0:6
When on, CRQ pisces the transmitter In auto dial snd the receiver In tone ,
det~ mode. The data placed In the dial digit \lufferls then treated 8$ digllS to
be dialect Aftar the laSt digit has been dialed; .FF (Hex) should be loaded Into
, the buffer· to, tell:the modem to go to the data stata. CRQlrfthe tran$mltter
(Benk 1) Wheritarned off causes the modem to go on-hook. Therefora, It should
be 0",· tor theduratlCln of the cell and not turned off, until It III. desired to go onhook. ORQ'ln the racelver (Bank 0) must be turned off immediately after
ringback is detected to put the modem In the data mode, otherwise 1\0
ansWetb~k tone'win be detected.
CTS
Clear-ta-Send
1:8:6.
When on,CTS indicates to Ihe terminal equipment that the modem will transmit
. any data which are present at .TXO.
DATA
Talk/Data
1:0:5·
1:0:4
(O,1):C:(3,4)
These bits'select either 8,9,10, or 11 bit characters, (See Character Length
table).
When on, DATA places the modem in data alate and when off in the talk state.
:',
10-61
R1,212'
1200 bps Full-Duplex Modem
Interface Memory Definitions (Continued)
DefinItion
Memory
LocatIon
DDEI
Dial Digit Empty Interrupt
I:E:2
When on, DDEI ca4ses an interrupt to occur when tlie dial digit register (1 :0)
is empty (DDRE=I).
DDRE
Dial Digit Register Empty
I:E:O
When on, DDRE indicates that the dial digit register is empty and can be
loaded with new digits to be dialed. After the register is loaded, DDRE goes
off.
DL
Digita' Loopback (Manual)
«(?,1i:A:5
When on, DL manually places the modem In digital loopback. (See Software
Dia~nostfc Circuits).
DLO
Data Line OCcupied
1:8:7
When on, DLO Indicates that the modem is In auto dial, i.e., CRQ is on and
the modem is off-hook ready to dial.
DSR
Data Set ReaciY
1:8:5
When on, DSR indicates that.the modem hanshake has begun and that the
data state will follow. DSR alone should not be used to indicate that the
communication channel has been completely established. DSR in conjunction
with CTS and RLSD will determine this. DSR will be off In all test states
(except optl~mally for analog loopbllck) and when the channel is being used
for voice communication (talk).
DSRA
Data Set Ready rn Analog
Loopback
1';'C:7
DTMF
Touch Tones!
Pulse Dialing
1 :B:l
When on, DTMF tells the modem to auto dial using tones. When off the
modem should dial using pulses.
DTR
Data Terminal Ready
1:0:3
DTR must be on before the modem will enter the data state, either manually
or automatically. DTR must also be on in order for the modem to automatically
answer an incoining call.
ENSI
Enable New Status
Interrupt
(0,1):E:6
When on, ENSI causes an interrupt to occur when the status bits in registers
(0:[8, 9J) and (1 :8) are updated. (NEWS = 1)
ERDL
Enable Response to
Remote Digital Loopback
(0,1):A:7
When on,ERDL enables the modem to respond to another modem's remote
digital loopback request, thus going into loopback.
GTE
Guard Tone Enable
I:B:4
When on, GTE causes the specified guard tone to be transmitted (CCITT
Configurations only).
GTS
Guard Tone Select
I:B:3
When off, GTS selects the 1800 Hz tone and when on the 550 Hz tone.
IRQ
Interrupt Request
LCD
Enable Loss of Carrier
Disconnect
MODE
Mode Select
NEWC
New Configuration
(O,I):E:3
When on, NEWC tells the modem that a new configuration has been written
into the configuration registers. The modem will then read the configuration
registers Md then reset NEWC. NEWC must be set after a new configuration,
has been written into the following registers: (O:[A-OJ) and (1: [9-0)). The
remaining, registers do not require the use of NE;WC to tell the modem that
new data was written into them.
New Status
(0,1):E:5
When on, NEWS tells the user that there has been a change of status in the
status registers.
Name
"
(O,I):E:7
0:0:2
(0,1):A:(0-3)
DescriptIon
,When on, DSRA causes DSR to be on during analog loopback.
When on, IRQ indicates that an interrupt has been generated.
When on, LCD causes the modem to terminate a call when a loss of received
carrier energy is detected after approximately 350 msec.
These bits select the compatibility at which the modem is to operate. (See
Mode Select table).
,
NEWS
10-62
1200 bps Full-Duplex Modem
R1.212
Interface Memory Definitions (Continued)
Name
Definition
ORG
Originate/Answer
ADL
Initiate Remote Digital
Loopback
ROLl
Memory
Location
1:9:5
Daacrljrtlon
When on, OAG tells the modem that it is originating a call and when low
answering a cal\. This is only valid in manual originate/answer and analog
loopback.
(0,1)::A:6
When on, RDL causes the modem to initiate a request for the remote modem
to go into digital loop back.
Remote Digital Loopback
Indicator
0:8:1
When on, ROLl indicates that the modem has received an RDL request and is
in remote digital loopback.
RI
Ring Indicator
1:8:4
When on, RI indicates that a ringing signal is being detected.
RLSD
Received Line Signal
Detector
0:8:0
When on, RLSD indicates that the carrier has successfully been received.
RLSD will not respond to the 550,1800,2100, or 2225 Hz tones.
RSD
Enable Receive Space
Disconnect
0:0:1
When on, RSD causes the modem· to go on-hook after receiving approximately
1.6 seconds of continuous spaces.
SPEED
Speed Indication
SSD
Enable Send Space .
Disconnect
ST
Self Test
3DB
3 dB Loss to Receive
Signal
1 :B:2
When on, 3DB attenuates the received signal adB. This is only used if the
R1212M will see OdBm or greater line signal at the receiver input. Insertion of
the adB loss will then prevent saturation. This .bit is not needed with the
R1212DC.
TONE
Tone Detect
0:8:7
TONE follows the energy detected in the 340 to 64S Hz frequency band. The
user must determine which tone is present on the line by determining the duty
cycle. TONE is active only when CRQ in SankO is on.
TXCLK
Transmit Clock Select
0:9:(4,5)
1:0:0
(0,1):A:4
I:C:(5,6)
00 - 300 bps
01 - 600 bps
10 - 1200 bps
When on, SSD causes the modem to transmit approximately 4 seconds of
spaces before disconnecting; when DTR Is turned off.
When on, ST activates self test. ST must be turned off to end the test. (See
Software Diagnostic Circuits).
TXCLK allows the user to designate the origin of the transmitter data clock.
(See Transmit Clock table).
SOFTWARE SUPERVISORY CIRCUITS
Mode
Configuration
The operation ofthe R1212 is affected by a number of software
control inputs. ;These inputs are written into registers withi.n the
modem via a microprocessor bus under external control. Modem
operation is monitored by various software flags that are re.ad
from modem registers using the same microprocessor bus.
Be1l212A
Bell 212A
Bell 212A
V.22A
V.22B
V.22A
V.22B
The transmit and receive registers contain many bits which perform identical functions and are located in the same memory
location only In different banks. Care must be taken to set theSe
bits according to the desired function.
ConflgurllIlon Word
1200 ·Sync.
1200 Async.
300 Async.
1200 Sync.
1200 Async.
600 Sync.
600 Async.
0
0
0
1
1
1
1
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
Character Length
ConfiguratIon
CONFIGURATION REGISTER
8 bits
9 bits
10 bits
11 bits
The host processor configures the R1212 by writing a control
word into the configuration registers In Its interface memory
space as shown in the following tables:
10-63
Configuration. Word
0
0 1
1 0
1 1
9
1200 bps FullaDuplex Modem
R1212
AUTO DIAL SEQUENCE
Transmit Clock
Configuration
Configuration Word
Internal
Not Used
External
Slave
0 0
0 1
1 0
The following flow chart defines the auto dial sequence via the
microprocessor interface memory.
1 1
Receiver Interface Memory Bank 0 ("CSO)
Bit
5
6
7
2
3
4
1
0
ROll
RLSD
Register
0
1
2
Diagnostic Data Real Low
3
Diagnostic Data Aeal High
4
Diagnostic Data Imaginary Low
5
Diagnostic Data Imaginary High
6
7
8
TONE
9
Speed
A
ERDL RDL
DL
ST
Mode
AL
B
CHAR
C
0
BUS
CRO
E
IRO
ENSI NEWS
F
Auto Dial Sequence Flow Diagram
RSD
LCD
Note: The modem timing for the auto dialer accounts for interdigit delay for pulses and tones.
NEWC
Diagnostic Control Register
DIAGNOSTIC CAPABILITIES
The R 1212 provides the user with access to much of the data
stored in the modems memories. This data is a useful tool in
performing certain diagnostic functions.
Transmitter Interface Memory Bank 1 (CSi)
Bit
7
5
6
3
4
2
1
0
RAM ACCESS CODES
Register
0
The RAM access codes defined in the table below allow the host
processor to read diagnostic data from the modem receiver. The
access codes should be loaded into the diagnostic control
register (O:F). The appropriate diagnostic data will then be
available in the diagnostic data registers (0:[2-5]).
Dial Digit Register
1
2
Diagnostic Data Real Low
3
Diagnostic Data Real High
4
Diagnostic Data Imaginary Low
5
Diagnostic Data Imaginary High
RAM Access Codes Bank 0
Function
6
Scrambled Data (Imag. Reg.)
Self Test Error Counter (Real Reg.)
Equalizer Tap Coefficients
Phase Error (Real Reg.)
Rotated Equalizer Output
(Received Point Eye Pattern)
Rotated Angle (Imag. Aeg.)
Low Pass Filter Output
Input Signal to Equalizer Tap CoeffiCients
Decision Points (Ideal)
Rotated Error
Equalizer Output
Demodulator Output
7
8
DLO
crs
9
A
DSR
ERDL
B
RDL
DL
TX LEVEL
C
DSRA
0
BUS
CRO
E
IRO
ENSI NEWS
F
AI
ORG
TXCLK
DATA
ST
GTE
Mode
GTS
3DB
OTMF
AL
CHAR
AAE
OTR
NEWC DOE I
SSD
DDRE
Diagnostic Controi Register
10-64
Acee.88 Data Typa
00
00
01-09
DC
00
OE
40
41-49
40
4E
4F
52
Real
Real
Complex
Real
Complex
Real
Complex
Complex
Complex
Complex
Complex
Complex
1200 bps Full-Duplex Modem
R1212
TEST
the OL bits ([O,1):A:5). OL should be set during the data
mode. OSR and eTS will be off. The local modem can then
be tested from the far-end by using the terminal equipment
at the far-end to transmit a test pattern and examine the
looped data. At the far·end modem, all interface circuits
behave normally as in the data mode. At the conclusion of
the test, DL must be turned off. The local modem will then
return to the normal data mode with control reverting the
OTE's OTR.
2. Local Analog Loopback (V. 54 Loop 3). The R1212 is capable
of entering into a local analog loopback (V.54 Loop 3). In this
loop, the transmitter's analog output is coupled to the
receiver's analog input at a point neer the modem's telephone
line interface. An attenuator is introduced into the loop such
that the signal level coupled into the receive path is approximately -16 dBm attenuation.
3. Remote Digital Loopback (V.54 Loop 2) (BeI/212A and eCIIT
V.22 bis and V.22). The R1212 is capable of entering into a
remote digital loopback. Remote digital loopback may be
locally entered by the interface memory. Remote digital loopback cannot be performed simultaneously with local analog
loopback.
The specifications for R1212 tests are defined as follows:
Self tests can be initiated by setting bits ([0,1): A: 4) to a 1. It
is possible to perform the tests with or without the OTE connected to the modem. During any self test TXO and RTS are
ignored. Note that self tests do not test asynchronous-tosynchronous converter circuits in either the transmitter or
receiver.
Error detection is accomplished by monitoring a counter in the
RAM. If the counter increments during the self test, an error was
made. The counter contents are available in the diagnostic
registers when the RAM access code 00 is loaded in the
diagnostic control register (0: F).
Self test end-to-end-Upon activation of self-test an internally
generated data pattern of alternate binary ones and zeros
(reversals) at the selected bit rate are applied to the scrambler.
An error detector, capable of identifying errors in a stream of
reversals are connected to the output of the descrambler.
Self test with loop 3-Loop 3 is applied to the modem as
defined in recommendation V.54. Self-test is activated and DeE
operation is as in the end-to-end test. In this test OTR is ignored.
POWER-ON INITIALIZATION .
Self test with loop 2-The modem is conditioned to instigate
a loop 2 at the remote modem as specified in recommendation
V.54. Self-test is activated and DeE operation is as in the endto-end test.
When power is applied to the R1212, a period of 100 to 300 ms
is required for initialization. The power-on-reset (POR) signal
remains low during the initialization period. After the low to high
transition of POR, the modem is ready to be configured.
Loopbacks-Remote digital loopback, digital loopback, and
local analog loopback can be initiated via the interface memory,
as follOWS:
The modem automatically defaults to Bell 212A 1200 bps,
answer state using serial start-stop data, 10 bits per character.
POR can also be used to initialize the user's host processor.
It may be connected to a user supplied power-on-reset signal
in a wire-or configuration.
1. Digital Loopback. The R1212 can be manually conditioned
to loop the received data back to the transmitter by setting
MODEM
TRANSMITTER
r--
LINE
SIMULATOR
r--
NOISE
SOURCE
GR1381
50 KHZ BW
r--
ATTENUATOR
HP 350D
IMPAIRMENT
SOURCE
BRADLEY 2A
t--
ATTENUATOR
HP 350D
t-"'--
L
r--
LEVEL
METER
HP 3552A
1--'--
MODEM
RECEIVER
I
I
ENGINEERING
MODEM
CONSOLE
ENGINEERING
MODEM
CONSOLE
NOTE
Signal and noise are measured with 3 kHz flat weighting.
BER Performance Test Set-up
1()"65
1200 bps Full-Duplex Modem
R1212
Connection to the telephone line interface pins of the R1212DC
to the network are made via the RJ11, as shown in the table
below:
PERFORMANCE
Whether functioning as a V.22, or Bell 212ktype modem, and
regardless of simulated line condition or introduced line impairment, the R1212 provides unexcelled high performance to the
user.
R1212DC Network Interface
BIT ERROR RATES
The Bit Error Rate (BER) performance of the R1212 is specified
for a test configuration conforming to that specified in CCITT
Recommendation V.56, except with regard to the placement of
the filter used to bandlimit the white noise source. Bit error rates
are measured at a received line signal level of -43-dBm,
Connection Type
Telco
Mnemonic
Function
VSOC
RJ11
1
2
3
R
Jack
4
T
Ring-one side of
telephone nne
Tip-one side of
telephone line
S
6
INTERFACE CIRCUIT CHARACTERISTICS
RING INDICATOR
DIGITAL INTERFACE CIRCUITS
The R1212 provides a ring indicator (FiT) output; itl! low state
indicates the presence of a ring signal. on the line. The low
condition appears approximately coincident with the on segment
of the ring cycle (during rings) on the communication channel.
(The ring signal cycle is typically two seconds on, four seconds
off.) The high condition of the indicator output is maintained
during the off segment of the ring cycle (between rings) ami at
all other times wben ringing is being received. The operation
of FiT is not disabled by an off condition on Data Terminal Ready.
Digital Input Characteristics
Input Logic State
Allowecllnput Voltage Levels
Low
High
O.OV to + O.BV at - 2.5 p.A
+2.0V to +5.0V at +2.5 p.A
Notes:
1. The digital inputs are directly TTUCMOS compatible. The
capactive loading on each input is-25 pF(maximum).
2. Positive currentis defined as current into the node.
Ri will respond to ring signals in the frequency range of 15.3 Hz
Digital Output Characteristics
to 68 Hz with volta911 amplitude levels of 40 to 150 Vrms (applied
across_Tip and Ring),with the response times given in the following table:
Output Logic State
Low
High
Allowed Output Voltage Levels
RI Response Time
+0.4Vat + 1.6 mA
+ 2.4V at -100 p.A
Notes:
1. The digital outputs are directly TTUCMOS compatible.
The capactive loading on each output is 50 pF (maximum).
2. Positive current is defined as current into the node.
RI Transition
Response Time
Off-Io-On
On-to-Off
125 ms 10 400 ms
75 ms 10 250 ms
This off-to-on (on-to-off) response time is defined as the time
interval between the sudden connection (removal) of the ring
signal across Tip and Ring and the subsequent on (off) transition Ri.
OH (OFF-HOOK)
The R1212M provides an output OH (Off-Hook) which indicates
the state of the OH relay. A low condition on OH implies the OH
relay is closed and the modem is connected to the telephone
line. A high condition on OH implies the OH relay is open (i.e.,
the modem is on-hOOk). The delay between the low-ta-high or
high-to-Iow transition of OH and the subsequent close-to-open
or open-to-close transition of the OH relay is B ms maximum.
ANALOG INTERFACE CIRCUITS
TRANSMISSION LINE INTERFACE
The R1212DC interface to the telephone line is the Tip and Ring
leads. Lightning induced surge voltages and other hazardous
voltages which may appear on the telephone line are limited to
approximately 7V peak between the secondary leads of the line
coupling transformer.
The DAA (R1212DC only) is bi-directional as required by 2-wire
full-duplex circuits.
10-66
1200 bps Full-Duplex Modftm
R1212
When the programmable connection arrangement is used, the
maxi,mum output transmit signal level allowed to appear across
the Tip and Ring (again, terminated with aOOohms) is set by
a resistor installed by the telephone company in their wall Jack
at the customer location; The resistor (which is of)e of thirteen
possible values) interacts with the .modem through modem leads
PR and PC to program the maximum output level, in one dB
steps between -12 dBm and 0 dBm. (The resistor is selected
by the telephone company jack installer after he.has measured
the line loss from the customer'focation to the local telephone
company centra~ office).
RD Indicates to the R1212M by an on (low) condition that a
ringing signal is present. The RD signal should not respond to
momentary bursts of ringing less than 125 ms in duration, or
to less than 40V rms, 15 to 68 Hz appearing across TIp and Ring
with respect to ground.
RCCT
RCCT is used to request that a data transmission path through
the OM be connected to the telephone line. When RCCT goes
off (low), the cut-through buffers are disabled and CCT should
go off (high) within 1 msec. RCCT should be off during dialing
but on for tone address signaling.
INSTALLATION
IMPORTANT ,NOTICE. TO
CCT
An on (low) signal to the CCT lead indicates to the R1212M that
the data transmission path through the OM is connected.
1. All direct connections to the telephone lines shall be made
through standard plugs and telephone company provided
jacks."
.
2. It is prohibited to connect the modem to pay telephones or
party ·lines.
3. You are required to notify the local tel~phone company prior
to the connectl"n al1d upon final disconnection of the mOdem.
You must supply to the telephone company the make, model
nump.er,. FCC 'regilitratri:m num~er, ringer equivalence and
particular line to which the connection is to be made. If the
proper jacks ;ire not avajlable, you must order the type of
jacks to be used from the telephone company.
4. You should disconnect the modem from the telephone line
if it appears to be malfunctioning. Reconnect it only when
it can be determined that the telephone line is the source of
trouble .. If the modem needs repair; return it to RoCkwell International. This applieS 10 'equipment both in and out of warranty. Do not attempt to rePair the unit as this will. Violate FCC
ru~
.,
AUDIO INTERFACE INPUT IMPEDANCE
The specifications for the audio interface input impedance are
given in the following table:
Audio Interface Input Impedance
Measurement
On/Olf Hook
On-Hook (DC)
The DC resistance between Tip and
Ring, and between either Tip or Ring
and signal ground is greater than
10 megohms for DC voltages up to
100 volts.
On-Hook (AC)
The 'on-hook AC impedance measured
between Tip and Ring is less than
4OKohms (15.3 Hz minimum).
Off-Hook (DC)
Less than 200 ohms.
Off-Hook (AC)
600 ohms nominal when measured'
between Tip and Ring.
USER
The modem contains protective circuitry registered with the
Federal Communications Commission (FCC) Part68 to allow
dlriJ!:t connection to the switched telephone network. To comply with the FCC is required:
5: The. modem contains protective circuitry to prevent harmful
voltages-from being transmitted to the telephone network.
If however such harmful VOltages do occur, then the telephone
company shall:
.
• Promptly notify you of the discontinuance.
• Afford you the opportunity to correct the situation which
caused the discontinuance.
The FCC requires that the following label be prominently
displayed on an outside surface of the OEM's end product.
• Unit contains Registered Protective Circuitry which
complies with Part as of FCC Rules.
• FCC Registration Number: Applied For
TRANSMITTER OUTPUT
Basic telephone company requirement is that .the sigrial level
received at the relevant local central office not exceed - 12 dBm.
Several different "connection arrangements" have been
established (as documented in Part 68) to accomplish this goal.
When the permissive connection arrangement is used, the
transmit output signal level appearing across i"ipand Ring (with
a 600 ohm resistiVe load across Tip and Ring) will not exceed
- 9 dBm. The output level is set at a fixed -10 dBm (nominal).
The permissive wall jacks used .for data connections are the
same jacks used for standard voice installations. The permissive
connection arrangement allows greater mobility for user
equipment.
1m'I "
• Ringer Equivalence: 0.5
Size of the label should.be such that all the required information is legible without m a g n i f i c a t i o n . , ,
10-67
R12t2
1200 bps Full-Duplex Modem
GENERAL SPECIFICATIONS
The gener!!1 specifications for the R1212 are,glven 111 the fOllowIng ,tables:
,
Power Requlrementl
",
Voltage·
Tolefllnoe
Curfllnt (Max)
<1500 ma
+6 Vdc
:t6%
+ 12 Vdc
:1;5%
< lOrna
:1;5% '
-12 Vdc
< SOma
·AII voltages must have ripple ,,0.1 volt. peak-te-peak.
Environmental
perameter
Temperature:
Operal[ng "
Storage·
Relallve Humidity:
Altitude:
"
Speol'loatlon
O·C to,-+: SO·C (32 to 140· F),
- 4O·CHo ,+ 80·C (- 40 III 17S·F)
Up 10 90% noncondenslng. or ,a weI
bulb temperalure up to 35·C!
whichever.is less.
- 20b to + '10,000 feel
·PCB's are stored In heal sealed antistatic bags and shipping
cllntainers,
,
Mech~nlc.1
Soarll StruCture:
Malitig CO,nriEictor:
PCB Dimensions:
DC Version
M Version
Weight:
Single PC board with rlghl angie
male DIN, cllimsclor." '"
Female S roW 84 pin Euroeonnector
(OIN),wllh roWs A and C popiJlliled:
Recommended mating connector: '
Winchester 96S-6048-0531-1, or
equivalent.
W!dth 3.94 in. (100 mm) x Length
4.725 in. (120 mm) x Height 0.75
in. (19 mm)
Width 3.94 In. (100' mm, x Length
3.35 In. (85 mm) x Height 0.40 in.
(10 mm)
Less than 0;45 Ibs. (0.20 kg.)
IO-S8
R1212
.156 t·003
IT,
~ ~
I
~1~~:6i;
:rr
MALE 64·PIN .
DIN CONNECTOR
1200 bps Full-Duplex Modem
:15& ±i•. OOS
DIAMETER
PLACES
MAtE 64,PIN,
OINOONNEC1'OR
'~
' '
R1212DC
R1212M
1l~1
~
'"
I ~ 2.725 ~I 'I- .483
~3.346~
Printed Circuit Board Dimensions
10-69
Inches
MM
. 11~
.156
.483
2.725
3.346
3.700
3.937
4.100
4.725
3
4
12
69
85
. 94
100
104
120
R2424
Integral Modems
'1'
Rockwell
R2424
2400 BPS FULL-DUPLEX MODEM
PRELIMINARY
INTRODUcTION
FEATURES
The Rockwell R2424 is a high performance full-duplex 2400 bps
modem ..Using state-of-the-art VLSI and signal processing
technOlogy, the R2424 provides the user with enhanced perform-.
ance and reliability oli asinllie printed circuit bQard of less than
22 square-inches-overall size.
•
•
•
•
The R2424 modem is ideal for data transmission over the 2-wlre
dial-up telephone network. The direct-connect, auto dial/answer
features are specifically designed for remote and cel'1tral site.
compuier applications. The bus interface allows easy integration into a personal computer. box modem, microcomputer, t~r~
mina.lor anyol,/ler communicati~:nls product that demanlls the
u1most in reliability and performance.
.
•
•
•
•
The added test feaiures, such as local analog loopback, remote
digitalloopback, and a self-test function, offer the user flexibility in qreating a 2400 bps modem de~ign customized for specific
packaging and functional requirements.
•
•
Being CCITT V.22 bis, V.22 A, B compatible, as well as Be1l212A
and 103 compatible. this modem fits most applications for fullduplex 2400 and 1200 bps fallback (synchronous and asynchronous) and 0 to 300 bps asynchronous data transmission over
the general switched telephone network .
•
•
•
•
CCrTT V.22 bis. V.22 A, B Compatible
Bell 212A and 103 Compatible
Synchronous: 2400 bps, 1200 bps. 600 bps ± G.Ol %
Asynchronous: 2400 bps, 12GO bps, 600 bps + 1%. -2.5%,
0-300 bps
"":Charac:ter length 8, 9, 10, or 11 bits
DTE Interface
-Functionally: Microprocessor Bus (ControQ and RS-232-C
.Interface (DatalControQ
-Electrically: TTL Compatible
Operation: 2-wire full-duplex
Adaptive and Fixed Compromize Equalization
Tes! Configurations:
-Local Analog L(iopback
-Remote Digital Loopback
-Self Test
Auto/Manual Answer.
Auto/Manual Dial:
-Tone or Pulse Dial
Power Consumption: 3 Watts Typical
Power Requirements: + 5 Vdc. ± 12 Vdc
Plug-compatible member of new Rockwell modem line
Two Versions: R2424DC (Direct Connect) with FCC approved
OM Part 68 Interface and R2424M (Module) without OM
. <"
R2424 Full-Duplex Modem
Document No_ 29200N11
10-70
Data Sheet Order No_ MD11
Rev. 1 January 1984
R2424
2400 bps Full-Duplex Modem
TECHNICAL SPECIFICATIONS
dation, the level of transmitted power for the 1800 Hz guard
tone should be 6 ± 1 dB below the level of the data power
in the main channel. The total power transmitted to the line
should be the same whether or not a guard tone is enabled.
If a 553.846 Hz guard tone is used, its transmitted power
should be 3 ± 1 dB below the level of the main channel power,
and again the overall power transmitted to the line should
remain constant whether or not a guard tone is enabled. The
device accomplishes this by reducing the main channel
transmit path gain by .97 dB and 1.76 dB for the cases of
the 1800 Hz and 553.846 Hz guard tones respectively.
3. DTMF Tones: The R2424 is capable of generating dual tone
multi-frequency tones. When the transmission of DTMF tones
are required, the CRQand DTMF bits must be set to a 1 (see
Interface Memory). When in this mode, the specific DTMF
tones generated are decided by loading transmit register with
the appropriate digit as shown in the following table:
fhe following are the technical specifications for the R2424
modem.
TRANSMITTER CARRIER AND SIGNALING
FREQUENCIES
The transmitter carrier and signaling frequencies are given in
the following table:
Transmitter Carrier and Signaling
Frequencies Specifications
Frequency
Specification
(Hz ±O.OI%)
V.22 bis low channel, Originate Mode
V.22 low channel, Originate Mode
V.22 bis high channel, Answer Mode
V.22 high channel, Answer Mode
Bell 212A high channel Answer Mode
Bell 212A low channel Originate Mode
Bell 103/113 Originating Mark
Bell 103/113 Originating Space
Bell 103/113 Answer Mark
Bell 103/113 Answer Space
1200
1200
2400
2400
2400
1200
1270
1070
2225
2025
Interface Memory Signals
Dial
Digits
BCD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TONE GENERATION
The specifications for tone generation areas follows:
1. Answer Backtones: The R2424 is capable of generating
echo disabling tones both of the CCITT and Bell versions,
as follows:
a. CCITT: 2100 Hz ± 15 Hz.
b. Bell: 2225 Hz ± 10 Hz.
2. Guard Tones.: If GTS is low, an 1800 Hz guard tone frequency is selected; if GTS if high, a 553.846 Hz tone is
employed. In accordance with the CCITT V.22 Recommen-
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
*
Spare (B)
Spare (C)
Spare (D)
#
Spare (F)
Tone Pairs
941
697
697
697
770
770
770
852
852
852
941
697
770
852
941
941
Signaling and Data Rates
Operating Mode
Signaling Rate (Baud)
Data Rate
V.22 bis:
600
Synch.ronous/Asynchronous
2400 bps ± 0.01 %
V.22 bis:
600
Synchronous/Asynchronous
1200 bps ±0.01%
V.22:
(Alternative A)
Mode i
600
1200 bps ±0.01% Synchronous
600
600 bps ± 0.01 % Synchronous
600
600
1200 bps ±0.01% Synchronous
600 bps ± 0.01 % Synchronous
Mode iii
(Alternative B)
Mode i
Mode iii
Mode ii
1200 bps Asynchronous
B, 9, 10, or 11 Bits Per Character
Mode iv
600 bps Asynchronous
B, 9, la, or 11 Bits Per Character
Bell 212A:
600
1200 bps ±0.01%
Synchronous/Asynchronous
o to 300 bps Asynchronous
Oto 300
10-71
1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1633
1633
1633
1477
1633
R2424
2400 bps Full-Duplex Modem
TONE DETECTION
RECEIVE LEVEL
The R2424 can detect tones in the 340 to 645 Hz band.
SIGNALING AND DATA RATES
The receiver circuit of the R2424 satisfies all specified performance requirements for the received line signals from - 12 dBm
to - 45 dBm. The received line signal is measured at the receiver
analog input RXA.
The signaling and data rates for the R2424 are defined in the
table below:
RECEIVE TIMING
The R2424 provides a Receive Data Clock (RDCLK) output in
the form of a (50 ± 1% duty cycle) squarewave. The low to high
transitions of this output coincide with the center of received data
bits. The timing recovery circuit is capable of tracking a ± 0.Q1 %
frequency error in the associated transmit timing source.
DATA ENCODING
The specifications for data encoding are as follows:
1. 2400 bps (V.22 bis). The transmitted data is divided into
groups of four consecutive bits (quad bits) forming a 16-point
signal structure.
2. 1200 bps (V. 22 and 8eI/212A). The transmitted data is divided
into groups of two consecutive bits (dibits) forming a four-point
signal structure.
3. 600 bps (V. 22). Each bit is encoded as a phase change
relative to the phase preceding signal elements.
TRANSMIT LEVEL
The R2424M output control circuitry contains a variable gain
buffer which reduces the modem output level. The R2424M can
be strapped via the host interface memory to accomplish this.
Transmit Level
EQUALIZERS
Configuration Word
The R2424 provides equalization functions which can be used
to improve performance when operating over poor lines.
o0
o0
o1
o1
Automatic Adaptive Equalizer-An automatic adaptive
equalizer is provided in the receiver circuit for V.22 bis, V.22
and Bell 212A configurations.
Fixed Compromise Equalizer-Compromise equalizers are provided in the transmitter and receiver.
TRANSMITTED DATA SPECTRUM
Transmit Level
0
o dbm
1
-2 dbm
0
-4 dbm
1
-6 dbm
100
-8 dbm
1 0 1
-10 dbm
1 1 0
-12 dbm
1 1 1
-14 dbm
1. V.22 bis. The transmitted line signals (excluding the
characteristics of the fixed comromise equalizer) have a frequency amplitude spectrum shaped by the square root of
75 percent raised cosine filter. The group delay of the
transmitter output is within ± 100 microseconds over the
frequency ranges 900 to 1500 Hz (low channel) and 2100 to
2700 Hz (hgh channel).
2. V.22. After making allowance for the nominal specified compromise equalizer characteristic, the transmitted line signal
has a frequency spectrum shaped by the square root of a
75 percent raised cosine filter. Similarly, the group delay of
the transmitter output is within ± 100 microseconds over the
frequency range 800 to 1600 Hz (low channel) and 2000 to
2800 Hz (high channel).
PERMISSIVE/PROGRAMMABLE CONFIGURATIONS
The R2424M transmit level is set to 0 dBm to allow a DAA to
be used. The DAA would then determine the permissive or programmable configuration.
The R2424DC transmit level is strapped in the permissive mode
so that the maximum output level is - 9.5 dBm ± 0.5 dBm.
TRANSMIT TIMING
The R2424 provides a Transmit Data Clock (TDCLK) output with
the following characteristics:
1. Frequency. Selected data rate of 2400, 1200 or 600 Hz
(±0.01%).
2. Duty Cycle. 50 ± 1%.
SCRAMBLER/DESCRAMBLER
The R2424 incorporates a self-synchronizing scrambler!
descrambler. In accordance with the CCITT V.22 bis, V.22 and
the Bell 212A recommendations.
Transmit Data (TXD) must be stable during the one microsecond
periods immediately preceding and following the rising edge of
TDCLK.
RECEIVED SIGNAL FREQUENCY TOLERANCE
CLAMPING
The receiver circuit of the R2424 can adapt to received frequency
errors of up to ± 7 Hz with less than a 0.2 dBm degradation in
BER performance.
The following clamp is provided with the R2424:
1. Receive Data (RXD). RXD is clamped to a constant mark (1)
whenever RLSD is off.
10-72
2400 bps Full-Duplex Modem
R2424
,
-
r
I
I
I
1
1
I
I
I
I
r-
CTS'
TXD
...........
TDCLK
Y
XTCLK
USART
(OPTIONAL)
I
h.
RLSD
I
RXD
RDCLK
r
I
l~'
TBCLK
I
-
j
L---..
~
.r'1
-
,..
MODEM
RBCLK
+5V
-12Y
READ
....
DATA BUS (8)
I
CS (2)
DECODERr
POR
?~oL
rea
:::.. ...
+5
A
y
A
TXA
0(0:7)
ADDRESS BUS (4)
t
POWER
SUPPLY
GND
WRITE
HOST
PROCESSOR
(DTE)
+12V
RS(0:3)
"
RXA
LINE
~}
INTERFACE ~
TELEPHONE
LINE
,.,)
,-,)
I
R2424 Functional Interconnect Diagram
RECEIVED LINE SIGNAL DETECTOR
established by the OTE (manual answering) or internal
(automatic answering) means. The off condition places the
modem in the disconnect state.
The high and low channel thresholds are greater than - 45 dBm
(RLSO on) and less than -48 dBm (RLSOoff) for V.22 bis, V.22
and Bell 212A configurations.
DATA SET
MODES OF OPERATION
~EADY
The R2424 is capable of being operated in either a serial or a
parallel mode of operation.
The on condition of the R2424 output Data Set Ready (OSR)
indicates that the modem is in the data transfer state. The off
condition of OSR is an indication that the DTE is to disregard
all signals appearing on the interchange circuits-except the calling indicator and the test signal. OSR will switch to the off state
when in test state. The on condition of DSR.indicates the
following:
SERIAL MODE
The serial mode uses standard V.24 (RS-232-C compatible)
signals to transfer channel data .. An optional USART device
(shown in the diagram above) illustrates this capability.
1. The modem is not in the talk state, i.e., an associated
telephone handset is not in control of the line.
2. The modem is not in the process of automatically establishing
a call via pulse or OTMF dialing.
3. The modem is generating an answer tone or d~tecting answer
tone.
4. After ring indicate goes on, OSR waits at least two seconds
before turning on to allow the bell equipment to be engaged.
CONTROL SELECTION
Selection of either the serial or parallel control is py means of
bits ([0;1j:D:7). To ena.ble the parallelcontrol, the bits must be
set to a one. In either 111000e, theH2424 is configured by the host
.
processor via the. mic;:roprocessor bus.
DSR will go off 50 msec after DTR goes off or 50 msec plus a
maximum of 4 sec when SSO is enabled.
INTERFACE CRITERIA
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins in a
64-pinDIN connector. Software circuits areassigned to specific
bits in a 32-byte interface memory.
OAT A TERMINAL READY
An on condition of OTR prepares the modem to be connected
to the communications channel, and maintains the connection
10-73
R2424
2400 bps Full-Duplex Modem
R2424 Hardware Supervisory Circuits
Name
HARDWARE SUPERVISORY CIRCUITS
Description
Pin No.
Type
Signal names and descriptions of the hardware supervisory
circuits, including the microprocessor interface, are given in the
following table. The microprocessor interface was designed
to be compatible with an 8080, 6500, 6800, and 68000
microprocessor.
A.OVERHEAD
DGND
G
AGND
+5 VDC
G
P
+12 VDC
-12 VDC
POR
P
P
OC
5A, lOA,
3C,8C
31C.32C
19C, 23C,
26C,30C
15A
12A
13C
Digital Ground
Analog Ground
+ 5 Volt Supply
+ 12 Volt Supply
- 12 Volt Supply
Power-On-Reset
WRITE
B. MICROPROCESSOR INTERFACE
B
B
B
B
B
B
B
B
I
I
I
I
I
I
I
I
OC
D7
D6
D5
D4
D3
D2
Dl
DO
RS3
RS2
RSI
RSO
CSO
CSI
READ
WRITE
IRQ
CSi
(i = 0.1)
lC
lA
2C
2A
3A
4C
4A
5C
6C
6A
7C
7A
10C
9C
12C
llA
l1C
Chip Select for Bank 0
Chip Select for Bank 1
Read Enable
Write Enable
Interrupt Request
22A
23A
21A
25C
24C
22C
24A
21C
20A
18A
External Transmit Clock
Transmit Data Clock
Receive Data Clock
Clear-to-Send
Transmit Data
Receive Data
Received Line Signal Detector
Data Terminal Ready
Data Set Ready
Ring Indicator In
I}
Data Bus (8-Bits)
Register Select (4-Bit5)
READ
C. V.24 INTERFACE
XTCLK
TDCLK
RDCLK
CTS
TXD
RXD
RLSD
DTR
DSR
Ai
I
0
0
0
I
0
0
I
0
0
Di
(i = 0 - 7 ) - -.......\.1
Microprocessor Interface Timing Diagram
Critical Timing Requirements
D. ANALOG SIGNALS (R2424M ONLY)
RXA
TXA
I
0
32A
31A
Characteristic
Symbol
Min
CSi, RSi setu~e prior
to Read or Write
TCS
30
-
NS
Ring Detect
Request Coupler Cut Through
Coupler Cut Through
Off-Hook Relay Control
Data Access time after Read
TDA
-
140
NS
Data hold time after Read
TDH
10
50
NS
TCH
10
Transmit Baud Clock
Receive Baud Clock
Talk TLK
Data
Originate ORG
Answer
TWDS
75
-
NS
Write data setup time
Write data hold time
TWDH
10
-
NS
TWR
75
-
NS
Receive Analog
Transmit Analog
E. SIGNALS TO DAA (R2424M ONLY)
RD
RCCT
CCT
OH
I
0
I
0
27A
28A
29C
29A
CSi, RSi hold time after
Read or Write
F. ANCILLARY FUNCTIONS
TBCLK
RBCLK
TLK
ORG
B
I
0
OC
P
G
0
0
I
I
27C
26A
28C
leC
=
Write strobe pulse width
=
Bidirectional
Input
Output
Open Coliector
Power
Ground
10-74
Max
Units
NS
2400~psFull-Dul)lex Modem
R2424
INTERFACE MEMORY
The R2424 has two banks of 16 registers to which an external
(host) microprocessor has access. Although these registers are
within the modem, thllY may be addressed as part of the host
processor's memory space. The host may read data out of or
write data into these registers. These registers, as shown in the
following table, .are referl!d to as interface memory.
When inforniation in these registers is.being discussed, the
format Y;Z;Q is. used. The bank is specified by Y (0 or I), the
tegister by Z (O-F), al'!d the bit by Q (0-7,0, = LSB). A bit is
considered to be 'on' when set to a one.
R2424 Interface Memory
Re,g No.
Bank
(HEX)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
Reg No.
Description
Bank
..
1
.1
1
1·
1
1
1
1
1
1
1
1
1
.1
1
1
Do Not Use
Do Not Use
Diagnostic: Qata Real LSEI's
Diagnostic Data Real M.SB's
Diagnostic Data Imaginary LSB's
Diagnostic Data lniaginary MSB's
00 Not Use
Do Not Use
Receiver Stalus
Receiver Status
Configuration
Configuration,
Configuration
Configuratfon
Handsnake Status
Diagnostic Control Register
5
6
7
8
9
A
B
G
0
E
F
(HEX)
DeSCrij)tlon
0
1
2
3
4
Dial Digit Register
Do Not Use
Diagnostic Data Real LSB's
Diagnostic Data Real MSB's
Diagnostic Data Imaginary LSB's
Diagnoslic Data Imaginary MSB'.s
Do Not Use
Do Nol Use
Transmitter Status
Configuration
Configuration
Configuration
Configuration
Configuration
Handshake Status
Diagnostic Control Regisler
5
6
7
8
9
A
B
C
0
E
F
..
.
The interface memory bits are defined in· the following table:
Interface Memory Definitions
,MemO.-y
Name
Definition
<-
Location
Des~riptlon
1:0:4
When on, AAE causes tlie modem 10 automatically answer when a ringing signal
is present on the line.
AAE
Auto Answer Enable
AL
Analog Loopback
(O,I):B:O
When on, AL places Ihe modem in analog loopback. (See Software DiagnostiC
Circili\S.)
BUS
Bus. Select
(0,1):0:7
When on, BUS places the modem in Ihe parallel control mode. When .off, the
modem is configured for the serial conlrol mode. BUS can be in eilher slaleto
configure, the modem.
CHAR
Character Length Select
CRO
Call Request
(0,1):0:6
Wben on, CRO places the transmitter in auto dial and the receiver in tone
detect mode. The data pieced in tne. dial digit buffer is then trealed as digits to
be dialecj. f\ftl!f the last digit has been dialed, FF (Hex) should be loaded into
Ihe buffer to tellihe modem to go 10 the data state, CRO in Ihe Iransmitter
(Bank 1) when tLirned off causes tile modem to go on-Itook. TherefQre, it should
be on for theauration of the call and not turned off until it is desired to go on·
hook. CRO in the 'receiver (Blink 0) must be turned off immediately after
ringb~k is detected to put the modem in the data mode, otherwise no
answerback tone will be dejected.
CTS
Clear·ta-Send
1:8:6
When on, CTS indicates to the terminal equipment that the modem will transmit
any data which are present at TXD.
DATA
Talk/Data
1 :.0:5
When on, DATA places the modem in data state and when off in the talk state.
DDEI
Dial Digit Empty Interrupt
1:E:2
When on, DD~I.c;auses an interrupt to occur when the dial digit register (1 :O).is
empty (DDRE = 1).
DDRE
Dial Digit Register Empty
I:E':O
When on, DDRE indicates that the dial digit register is empty and can be loaded
with new digits to be dialed. After the register is loaded, DDRE goes off.
(0,1):C:(3,4)
These bi\S selecteither 8, 9" 10, or 11 bit characters. (See Charl~cter Length
table.)
10·75
2400 bps Full-Duplex Modem
R2424
Interface Mamory Deflnltlonl (Continued)
Definition
Memory
Location
DL
Digital Loopback (Manual)
(0,1):A:5
When on, DL manually places the modem in digital loopback. (See Software
Diagnostic Circuits.)
DLO
Data Line Occupied
1 :8:7
When on, DLO Indicates that the modem is in auto dial, I.e., eRO Is on and
the modem is off-hoQk. ready to dial.
DSR
Data Se.t Ready
DSRA
Data Set Ready In Analog
Loopback
1:C:7
When on, DSRA causes DSR to be on during analog loopback.
DTMF
Touch Tones!
Pulse Dialing
1:8: 1
When on, DTMF tells the modem to auto dial using tones. When off the
modem should dial using pulses.
DTR
Data Terminal Ready
1:0:3
DTR mu'st be on before the modem will enter the data state, either manually
or automaticl!IIy. DTR must also be on in order for the modem to automatically
answer,n in«oming call.
'
ENSI
Enable New Status
Interrupt
(0,1):E:6
.
,
'When on, ENSI causes an interrupt to occ'ur when the. status bits in registers
(0:[8, 9)) and (1:$j are updated. (NEWS = 1)
ERDL
Enable Response to
Remote Digital Loopback
(0,1):A:7
When OIl. EROL enables the modem to respond to another m~dem's remote
digital loopback request, thus gOing into loopback.
GTE
Guard Tone Enable
1:8:4
When on, GTE .causes the specified guard tone to be .transmitted (CCITT
Configurations only).
GTS
Guard Tone Select
1:8:3
When off, GTS selects the 1800 Hz tone and when on the 550 Hz tone.
IRO
Interrupt Request
LCD
Enable Loss of Carrier
Disconnect
MODE
Mode Select
NEWC
New Configuration
(0,1):E:3
When on, NEWC tells the modem that a new configuration has been written
into the cpnfiguration registers. The modem will then read the configuration
'registers and then reset NEWC. NEWC must be set atter a new configuration
has been written into the following registers: (O:[A-D)) and (1 :[9-0)). The
remaining registers do not require the use of NEWC to tell the modem that
new data was ~ritten into them.
NEWS
New Status
(O,l):E:5
When on, NEWS tells the user that there has been a change of status in the
status registers.
ORG
Originate/Answer
RDL
Initiate Remote Digital
Loopback
Name
. 1 :8:5
Description
When on, DSR indicates that the modem hanshake has begun and that the
data state will follow. DSR alone should not be used to indicate that the
commu.nicatlon channel has been completely established. DSR in conjunction
with CTS and RLSD will determine this. DSR will be off in all test states
(except optionally for analog loopback) and when the channel is being used
for voice communication (talk).
"
" '
\
(0,1):E:7
0:0:2
(0,1): M(0-3j
1 :9:5
(0,1)::A:6
""
,
When on, IRO indicates that an interrupt 'has been generated.
When on, LCD causes the modem to terminate a call when a loss of received
carrier energy is detected after approximately 350 msec.
These bits select the Qompatibility at which the modem is to operate. (See
Mode Select table).
When on, ORG tells the modem that it is originating a call and when low
answering a call. This is only valid in manual originate/answer and analog
loopback.
When on, RDL causes the modem to initiate a request for the remote modem
to go into digital loopback.
10.76
2400 bps Full .. Ouplex Modem
R2424
Interface Memory Definitions (Continued)
Name
Oellnltlon
Memory
Location
aescrlptlon
ROLl
Remote Digital Loopback
Indicator
0:8:1
When on, ROll indicates that the modem has received an flDL request and is
In remote digital loopback.
RI
Ring Indicator
1:8:4
When on, RI Indicates that a ringing signal is being detected.
RLSD
Received Line Signal
Deleclor
0:8:0
When on, RLSD indicates Ihat the carrier has successfully been reCeived.
RLSD will not respond 10 the 550, 1800;2100, or 2225 Hz lones.
RSD
Ef).able Receive Space
Disconnect
0.:0:1
When on, RSD causes the modem to go on·hook afler receiving approximately
1.6 seconds of continuous spaces.
SPEED
Speed Indication
SSD
Enable Send Space
Disconnect
ST
Self Test
30B
'3 dB Loss to Receive
Signal
1 :B:2
When on, 30B attenuates the received signal 3dB. This is only used if the
R2424M will see adBmor greater line signal at the receiver input. Insertion of
the 3dB loss will thim prevent saturation. This bit is not needed with the
R2424DC.
TONE
Tone Detect
0.:8:7
TONE follows the energy detected in the: 340. to 645 Hz frequency band. The
user must determine which tone is present on the line by determiniJig the dutY
cycle. TONE is active only when CRQin Bank a is on.
TXCLK
Transmit Clock Select
0:9:(4,5)
1 :0:0.
(o.,I):A:4
1 :C:(5,6)
0.0 = 30.0. bps
01 =60.0. bps
10. = 120.0. bps
11 = 240.0. bps
When on, SSD causes the mOdem to transmit approximately 4 seconds of
spaces before disconnecting, when DTR is turned (Iff.
When on, ST activates 'self test. ST must oe turned
Software Diagnostic Circuits.)
off to end the test. (See.
TXCLK allows the user to designate the origin of thoHransmitter (jata clock.
(See Transmit Clock table.)
SOFTWARE SUPERVISORYCIRCI:'IT~
.,
Configuration '.
The operation of the R2424 is affected by a number of software
control inputs. These inputs are written into registers within the
modem via a micropro~ssor bus under external control. Modem
operation is monitored by various software flags that are read
from modem registers usin~ the same microprocessor bus.
Bell 212A
Bell 212A
B.eU 212A
V.22A
V.22B
. V.22A
V.22B
V..22 bis
V.22 bis
V.22 bis
V.22 bis,
The transmit and receive registers. contain many bits which per·
form identical fUnctions and are located in the same memory
locatiOn only in different banks. Care must be taken to set these
bits according to the. desired function•.
Mode
Configuration Word
0
0
0
1
1
1
1
1
1
1
1
120.0. Sync.
120.0. Async.
30.0. Async.
120aSync,
120.0 Async.
600 Sync .
60.0 Async.
2400 Sync:
240.0. Async.
120.0. Sync.
120.0. Async.
0. 1
a 1
1 a
0. a
0."0.
0 1
a 1
1 a
1 a
1 1
1 1
a
1
a
0
1
a
1
a
1
0
1
Character Length
CONFIGURATION REGISTER
Configuration
The host processor configures the R2424by writing a control
word into the configuration' registers in its interface memory
space as shown in the following tables:
8
9
10.
11
10·77
bits
bits
bits
bits
Configuration Word
a a
0 1
1 a
1 1
R2424
2400 bps Full-Duplex Modem
AUTO DIAL SEQUENCE
Transmit Clock
Configuration Word
Configuratl~n
0
0
Internal
NolUsed
External
Slave
The following flow chart defines the auto dial sequence via the
microprocessor interface memory.
0
1
0
1
1
1
Receiver Interface Memory Bank 0 (CSO)
Bit
!i
6
7
4
1
2
3
0
','
Fieglster
0
1
Low
Diagnostic Data Real
,,2
Diagnostic Data Real !"I\gll
3
4
DiagnosticDatalmaginary Low
5
Diagnostic Data Imaginary High
6
7
TONE
8
A
ERDL ADL
I
ST
DL
RDLI
",
,
Speed
9
RLSD
I
Mode
AL
B
,,'
C
CHAR
"
D
BUS
CRQ
E
tRQ
ENSI NEWS
Auto Dial Sequence Flow Diagram
RSD
LCD
Note: The modem timing for the auto dialer accounts for interdigit delay for pulses and tones.
,
NEWC "
Diagnostic Control Register
F
DIAGNOSTIC CAPABILITIES
The R2424 provides the user with access to much a! the data
stored in the modems memories. This data is a useful tool in
performing certain diagnostic functions.
Transmitter Interface Memory Bank 1 (CSI)
Bit
7
6
4
5
2
3
1
0
RAM ACC~SS CODES
Register
The RAM access codes defined in the table below allow the host
processor to read diagnostic data from the modem receiver. The
access codes !;hould be, loaded into the diagnostic control
register (O:F). The appropriate diagnostic data will then be
available in the diagnostic data registers (0:[2:5]).
Dial Digit Register
0
1
2
Diagnostic pata Real Low
3
Diagnostic Data Reai High
4
Diagnostic Data Imaginary Low
5
Diagnostic Data Imaginary High
RAM Access Codes 'Bank 0
Function
6
Scrambled Data (Imag. Reg,)
Self Test Error Counter (Real Reg.)
Equalizer Tap Coefficients
Phase Error (Real Reg.)
Rotated Equalizer Output '
(Received Point Eye Pattern)
Rotated Angle (I mag. Reg.)
Low Pass Filter Output
Input Signal to Equalizer Tap Coefficients
Decision Points (Ideal)
Rotated Error
Equalizer Output
Demodulator Output
7
8
OLO
CTS
A
DSR
ERDL
B
RDL
DL
TX LEVEL
C
DSRA
0
BUS
CRQ
E
IRQ
ENSI NEWS
F
RI
ORG
9
TXCLK
DATA
ST
GTE
Mode
GTS
3DB
DTMF
AL
CHAR
AAE
DTR
NEWC ODE I
SSD
DDRE
Diagnostic Control Register
10-78
Access Data Type
00
00
01-09
OC
OD
Real
Real
Complex
Real
Complex
OE
40
41-49
4D
4E
4F
Real
Complex
Complex
Complex
Complex
Complex
Complex
52
2400 bps Full-Duplex Modem
R2424
the OL bits ([O,I]:A:5). OL should be set during the data
mode. OSR and eTS will be off. The local modem can then
be tested from the far-end by using the terminal equipment
at the far-end to transmit a test pattern and examine the
looped data. At the far-end modem, all interface circuits
behave normally as in the data mode. At the conclusion of
the test, OL must be turned off. The local modem will then
return to the normal data mode with control reverting the
OTE's OTR.
2. Local Analog Loopback (V. 54 Loop 3). The R2424 is capable
of entering into a local analog loopback (V.54 Loop 3). In this
loop, the transmitter's analog output is coupled to the
receiver's analog input at a point near the modem's telephone
line interface. An attenuator is introduced into the loop such
that the signal level coupled into the receive path is approximately - 16 dBm attenuation.
3. Remote Digital Loopback (V. 54 Loop 2) (Bel/ 212A and CCITT
V.22 bis and V.22). The R2424 is capable of entering into a
remote digital loopback. Remote digital loopback may be
locally entered by the interface memory. Remote digital loopback cannot be performed simultaneously with local analog
loopback.
TEST
The specifications for R2424 tests are defined as follows:
Self tests can be initiated by setting bits ([O,1]:A:4) to a 1. It
is possible to perform the tests with or without the OTE connected to the modem. During any self test TXO and RTS are
ignored. Note that self tests do not test asynchronous-tosynchronous converter circuits in either the transmitter or
receiver.
Error detection is accomplished by monitoring a counter in the
RAM. If the counter increments during the self test, an error was
made. The counter contents are available in the diagnostic
registers when the RAM access code 00 is loaded in the
diagnostic control register (0: F).
Self test end-to-end-Upon activation of self-test an internally
generated data pattern of alternate binary ones and zeros
(reversals) at the selected bit rate are applied to the scrambler.
An error detector, capable of identifying errors in a stream of
reversals are connected to the output of the descrambler.
Self test with loop 3-Loop 3 is applied to the modem as
defined in recommendation V.54. Self-test is activated and DeE
operation is as in the end-to-end test. In·this test OTR is ignored.
POWER-ON INITIALIZATION
Self test with loop 2-The modem is conditioned to instigate
a loop 2 at the remote modem as specified in recommendation
V.54. Self-test Is activated and DeE operation is as in the endto-end test.
When power is applied to the R2424, a period of 100 to 300 ms
is required for initialization. The power-on-reset (POR) signal
remains low during the initialization period. After the low to high
transition of POR, the modem is ready to be configured.
Loopbacks-Remote digital loopback, digital loopback, and
local analog loopback can be initiated via the interface memory,
as follows:
The modem automatically defaults to V.22 bis 2400 bps, answer
state using serial start-stop data, 10 bits per character.
POR can also be used to initialize the user's host processor.
It may be connected to a user supplied power-on-reset signal
in a wire-or configuration.
1. Digital Loopback. The R2424 can be manually conditioned
to loop the received data back to the transmitter by setting
NOISE
SOURCE
GR1381
50 KHZ BW
MODEM
TRANSMITTER
~
LINE
SIMULATOR
I--
I--- ATTENUATOR
HP 350D
IMPAIRMENT
ATTENUATOR
I--I-SOURCE
HP 350D
BRADLEY 2A
LEVEL
METER
HP 3552A
1---
MODEM
RECEIVER
1
I
ENGINEERING
MODEM
CONSOLE
L
r-
NOTE
Signal and noise are measured with 3 kHz flat weighting.
BER Performance Test Set-up
10-79
ENGINEER!NG
MODEM
CONSOLE
2400 bps Full-Duplex Modem
R2424
PERFORMANCE
Connection to the telephone line interface pins of the R2424DC
to the network are made via the RJll, as shown in the table
below:
Whether functioning as a V.22 bis, V.22, or Bell 212A type
modem, and regardless of .simulated line condition or introduced
line impairment, the R2424 provides unexcelled high performance to the user.
R2424DC Network Interface
Connection Type
BIT ERROR RATES
The Bit Error Rate (BER) performance of the R2424 is specified
for a test configuration conforming to that specified in CCITT
Recommendation V.56, except with regard to the placement of
the filter used to bandlimit the white noise source. Bit error rates
are measured at a received line signal level of - 43 dBm.
Telco
Mnemonic
Function
Ring-one side of
telephone. line
Tip-one side of
telephone line
1
2
VSOC
RJ11
3
R
Jack
4
T
5
6
RING INDICATOR
The R2424 provides a ring indicator(Ri) output; its low state
indicates the presence of a ring signal on the line. The low
condition appears approximately coinCident with the on segment
of the ring cycle (during rings) on the communication channel.
(The ring signal cycle is typically two seconds on, f9ur seconds
off.) The high condition of the indicator output is maintained
during the off segment of the ring cycle (between rings) and at
ali other times when ringing is being received, The operation
of Ai is not disabled by an off condition on Data Terminal Ready.
INTERFACE CIRCUIT CHARACTERISTICS
DIGITAL INTERFACE CIRCUITS
Digital Input Characteristics
Input Logic State
Allowed Input Voltage Levels
Low
High
O.OV to + O.BV at - 2.5 p.A
+ 2.0V to +5.0V at + 2.5 p.A
Notes:
1. The digital inputs are directly TTL/CMOS compatible. The
capactive loading on each input is 25 pF (maximum).
2. Positive current is defined as current into the node.
Ai will
respond to ring signals in the frequency range of 15.3 Hz
to 68 Hz with vollage amplitude levels of 40 to 150 Vrms (applied
across Tip and Ring), with the response times given in the following table:
RI Response Time
Digital Output Characteristics
Output Logic State
Low
High
Allowed Output Voltage Levels
+O.4Vat +1.6mA
+2.4Vat -100 ~A
Notes:
1. The digital outputs are directly TTL/CMOS compatible.
The capactive loading on each output is 50 pF (maximum).
2. Positive current is defined as current into the node.
RI Transition
Response Time
Off-to-On
On-to-Off
125 ms to 400 ms
75 ms to 250 ms
This off-to-on (on-to-off) response time is defined as the time
interval between the sudden connection (removal) of the ring
signal across Tip and Ring and the subsequent on (off) transition Ai.
OH (OFF-HOOK)
ANALOG INTERFACE CIRCUITS
The R2424M provides an output OH (Off-Hook) which indicates
the state of the OH relay. A low condition on OH implies the OH
relay is closed and the modem is connected to the telephone
line. A high condition on OH implies the OH relay is open (i.e.,
the modem is on-hook). The delay between the low-to-high or
high-to-Iow transition of OH and the subsequent close-to-open
or open-to-close transition of the OH relay is 8 ms maximum.
TRANSMISSION LINE INTERFACE
The R2424DC interface to the telephone line is the Tip and Ring
leads. Lightning induced surge voltages and other hazardous
voltages which may appear on the telephone line are limited to
approximately 7V peak between the secondary leads of the line
coupling transformer.
The DAA (R2424DC only) is bi-directional as required by 2-wire
full-duplex circuits.
10-80
R2424
2400 bps Full-Duplex Modem
When the programmable connection arrangement is used, the
maximum output transmit signal level allowed to appear across
the Tip and Ring (again, terminated with 600 ohms) is set by
a resistor installed by the telephone company in their wall jack
at the customer location. The resistor (which is one of thirteen
possible values) interacts with the modem through modem leads
PR and PC to program the maximum output level, in one dB
steps between - 12 dBm and 0 dBm. (The resistor is selected
by the telephone company jack installer after he has measured
the line loss from the customer location to the local telephone
company central office).
RD
RD indicates to the R2424M by an on (low) condition that a
ringing signal is present. The RD signal should not respond to
momentary bursts of ringing less than 125 ms in duration, or
to less than 40V rms, 15to 68 Hz appearing across Tip and Ring
with respect to ground.
RCCT
RCCT is used to request that a data transmission path through
the DAA be connected to the telephone line. When RCCT goes
off (low), the cut-through buffers are disabled and CCT should
go off (high) within 1 msec. RCCT should be off during dialing
but on for tone address signaling.
INSTALLATION
CCT
IMPORTANT NOTICE TO USER
An on (low) signal to the CCT lead indicates to the R2424M that
the data transmission path through the DAA is connected.
The modem contains protective circuitry registered with the
Federal Communications Commission (FCC) Part 68 to allow
direct connection to the switched telephone network. To comply with the FCC regulations the following is required:
AUDIO INTERFACE INPUT IMPEDANCE
1. All direct connections to the telephone lines shall be made
through standard plugs and telephone company provided
jacks.
2. It is prohibited to connect the. modem to pay telephones or
party lines.
3. You are required. to notify the local telephone company prior
to the connection and upon final disconnection of the modem.
You must supply to the telephone company the make, model
number, FCC registration number, ringer equivalence and
particular line to which the connection is to be made. If the
proper jacks are not available, you must order the type of
jacks to be used from the telephone company.
4. You should disconnect the modem from the telephol)e line
if it appears to be malfunctioning. Reconnect it only when
it can be determined that the telephone line is the source of
trouble. If the modem needs repair, return it to Rockwell International. This applies to equipment both in and out of warranty. Do not attempt to repair the unit as this will violate FCC
rules.
5. The modem contains protective circuitry to prevent harmful
voltages from being transmitted to the telephone network.
If however such harmful voltages do occur, then the telephone
company shall:
• Promptly notify you of the discontinuance.
• Afford you the opportunity to correct the situation which
caused the discontinuance.
The FCC requires that the following label be prominently
displayed on an outside surface of the OEM's end product.
• Unit contains Registered Protective Circuitry which
complies with Part 68 of FCC Rules.
• FCC Registration Number: Applied For
• Ringer Equivalence: 0.5
Size of the label should be such that all the required information is legible without magnification.
The specifications for the audio Interface input impedance are
given in the following table:
Audio Interface Input Impedance
Measurement
On/Off Hook
On-Hook (DC)
The DC resistance between Tip and
Ring, and between either Tip or Ring
and signal ground is graater than
10 megohms for DC voltages up to
100 volts.
On-Hook (AC)
The on-hook AC impedance measured
between Tip and Ring is less than
40K ohms (15.3 Hz minimum).
Off-Hook (DC)
Less than 200 ohms.
Off-Hook (AC)
600 ohms nominal when measured
between Tip and Ring.
TRANSMITTER OUTPUT
Basic telephone company requirement is that the signal level
received at the relevant local central office not exceed -12 dBm.
Several different "connection arrangements" have been
established (as doCumented in Part 68) to accomplish this goal.
When the permissive connection arrangement is used, the
transmit output signal level appearing across Tip and Ring (with
a 600 ohm resistive load across Tip and Ring) will not exceed
- 9 dBm. The output level is set at a fixed -10 dBm (nominal).
The permissive wall jacks used for data connections are the
same jacks used for standard voice installations. The permissive
connection arrangement allows greater mobility for user
equipment.
10-81
R2424
2400 bps Full-Duplex Modem
GENERAL SPECIFICATIONS
Power Requirements
Voltage"
Tolerance
Current (Max)
+5 Vdc
+ 12 Vdc
-12 Vdc
±5%
±5%
±5%
<500 ma
< 10 ma
< 50 ma
"All voltages must have ripple :5 0.1 volts peak-to-peak.
Environmental
Parameter
Temperature:
Operating
Storage"
Relative Humidity:
Altitude:
Specification
O°C to + BOaC (32 to 140°F)
- 40°C to + BOaC (- 40 to 176°F)
Up to 90% noncondensing, or a wet
bulb temperature up.to 35°C,
whichever is less.
- 200 to + 10,000 feet
"PCB's are stored in heat sealed antistatic bags and shipping
containers.
Mechanical
Board Structure:
Mating Connector:
PCB Dimensions:
DC Version
M Version
Weight:
Single PC board with right angle
male DIN connector.
Female 3 row 64 pin Euroconnector
(DIN) with rows A and C populated.
Recommended mating conne.ctor:
Winchester 96S-6043-0531-\ or
equivalent.
Width 3.94 in. (100
4.725 in. (120 mm)
in. (19 mm)
Width 3.94 in. (100
3.35 in. (85 mm) x
(10 mm)
Less than 0.45 Ibs.
mm) x Length
x Height 0.75
mm) x Length
Height 0.40 in.
(0.20 kg.)
10-82
R2424·
2400 bps Full-Duplex Modem
R2424DC
Inches
.119
.156
.483
.2.725
3.346
3.700
3.937
4.100
4.725
Printed Circuit Board Dimensions
10-83
MM
3
4
12
69·
85
94
100
104
120
R24DC
Integral Modems
'1'
Rockwell
R24DC
2400 BPS DIRECT CONNECT MODEM
INTRODUCTION
FEATURES
The ROCkwell R24DC is a high performance synchronous serial
2400 pps DPSK modem. El\tensively utilizing MaS/LSI technol· .
ogy wi,th registered protective circuitry, the R24DC is ideally
suitable for direct .connection to the domestic switched network
ortwo-wire private "nes:Performance and versatility are enhanced
while. cost and size are reduced by .the .on·board Rockwell
PPS-4/1 One Chip Microcomputer
• High Performance; Low Cost
• LSI High Density; Low Power
• Microcomputer Controlled Line ConnectlDisconnect Sequence;
Low Component Count
• Bell 2{)1 C, cCln V.26 bis Compatible
• Half Duplex (2·Wire) Operating Mode
• 2400 BPS Data Rate
• Auto or Manual Answer
• Auto or Manual Dial Through (Pulse Dialing)
• Automatic Answer Back Tone Generation upon Auto Answer
• Direct Connect to Switched Network
• Programmable or Permissive Connection Arrangement
• Local Analog Loopback Test Mode
• Compromise !Oqualizer (Strap Selectable)
• Scrambler/Descrambler Facility (Selectable)
• Line Current Sensing (Selectable)
• DTE'lnterfac;e LSnUCMOS Compatible Levels. RS"232·C
Functions
• External Transmit Data Clock Tracking
• Power Requirements, ± 12V, +5V
• Typical Power Consumption 3 Watts
• Diagnostic Outputs Available for Eye Pattern and Data Quality
Monitor
• 15 Second Abort Timer (Selectable)
Having Bell201C and cCln V.26 bis compatibility, the R24DC
offers the user a high performance 2400 bps modem that is FCC
registered for direct connection to the dial·up network. Nq
re-registration of OEM equipment is required when the simple
installation instructions, supplied with the R24DC, are followed.
OEM's can easily incorporate this single (6" x 8") card into their
Computer terminals, communication networks, PABX equipment,
data concentrators, stand·alone box modems or almost any
application where reliable data communicaiion is required.
R24DC Modem
Document No. 29200N02
10·84
Data Sheet Order No. MD02
Rev. 1, August 1983
R24DC
2400 bps Direct Connect Modem
FUNCTIONAL SPECIFICATIONS
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DECISION
DEVice
MOS/LSI
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DIAGNOSTICS
A
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Reves
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DCP
P.
PPS4/1
MICRO·
R
PROCESSOR
DEVICE
lA7552.
DTE INTERFACE CONNECTOR
R24DC Functional Block Diagram
Transmitter Carrier Frequency -
1800 Hz ± 0.01 %
Echo Suppression and Answering Tone Frequencies 2100 Hz ±0.01 olo or 2025 Hz ±0.01%.
Received Signal Frequency Tolerance - The receiver can
adapt to received frequency errors up to ± 10Hz with less than
a 0.5 dB degradation in bit error rate.
Data Signaling and Modulation Rate - The normal signaling
rate is 1200 baud ±0.01%, and a data rate of 2400 bps ±0.01%.
The fallback signaling rate is 1200 baud ± 0.01 %, and a data
rate of 1200 bps ± 0.01 %.
Transmitted Data Spectrum - The transmitted spectrum's
bandwidth extends from 800 Hz to 2800 Hz. Phase distortion
characteristics are within the limits specified in CCITT Recom·
mendation V.26 bis. The out of band signal power limitations
meet those specified by Part 68 or Tariff 261 of the FCC's regula·
tions, and typically exceed the requirements of international
regulatory bodies as well.
VLrV V\ATV-V
Reference
Line Signal
Diagram (V.26 A&B)
At 1200 bps, differential2·phase modulation is employed. Each
bit to be transmitted is encoded as a phase change relative to
the phase of the immediately preceding signal element. The
enCOding is in accordance withCCITT RecommendationV.26
bis as shown in the following chart.
Data Encoding (DPSK) - At 2400 bps, differential 4·phase
modulation is employed. The data stream to. be transrt:litted is
1200 BPS
2400 BPS
BIT
PHASE CHANGE
PHASE CHANGE
DIBIT
V.26A
00
01
11
10
00
+900
+180 0
+270°
V.26B/Bell 201
0
1
.>
+45 0
+135 0
+225°
+315°
+90 0
+270 0
Turn On Sequences - A total of six selectable turn on
sequences can be generated by the transmitter of the R24DC,
as shown in the following chart.
10·85
R24DC
2400 bps Direct Connect Modem
TYPE OF
LINE
SIGNAL
SEGMENT 1
TURN-ON
SEQUENCE
NUMBER
CONTINUOUS
UNSCRAMBLED
ONES
1
2
3
4
90 ms
8.33 ms
148.3ms
8.33 ms
220 ms '
8.33 ms
5
6
SEGMENT 2
TOTAL OF
SEGMENTS
1,2
CONTINUOUS
SCRAMBLED1
ONES
NOMINAL
TOTAL
TURN ON
SEQUENCE
TIME2
Oms
81'.67 ms
Oms
140 ms
Oms
211.7ms
90 ms
90 ms
148.3 ms
'148.3 ms
220 ms
·220 ms
COMMENTS
V.26, V.26 bis
(scrambler inserted)
Bell 201C
('scrambler inserted)
V.26 bis
(scrambler inserted)
As is evident from the above for those turn-on sequences for which the scrambler is inserted, the transmitted line signal corresponds to a
continuous "'one", unscrambled, for 8.33 ms·ten baud (symbol) inteNals for the remainder of the tu-rn-on sequence.
Turn Off Sequence - When the R24DC transmitter has been
sending data and Request-to-Send is turned off, any remaining
data bit information is transmitted within 6 milliseconds.
1. Received Data. The Received Data output is clamped to
a mark when Carrier Detect is off. This action prevents
disturbances on the line from getting through the receiver
circuit to the data output.
2. Carrier Detect Clamp. The Carrier Detect output is clamped
off (squelched) during the time when Request-to-Send is on.
An. option extends this clamp for 148 ms beyond transitioning
off; thus providing echo protection.
CLEAR-TOoSEND
RESPONSE TIMES1
OFF-TO-ON
ON-TO-OFF
COMMENTS
90 ms
90 ms
148.3 ms
148.3 ms
220 ms
220 ms
Oms
Oms
Oms
Oms
Oms
Oms
V.26 bis
V.26 bis w/scrambler
Bell 201C
Bell 201 C w/scrambler
V.26 bis
V.26 bis w/scrambler
1
2
3
4
5
6
3. Receive Clock Clamp. The Receive Clock output is clamped
off when Carrier Detect is off. This action prevents any disturbances from propagating through the receiver circuit to the
receive clock output.
Equalizer - The R24DC contains a fixed compromise delay
equalizer, which can be used to improve performance over the
domestic switched network. The equalizer may optionally be
pOSitioned in the receiver, or removed entirely, by means of a
jumper plug. The equalizer has a nominally flat 0.0 dB amplitude
response.
The tolerance on 9ach Off-to-On and On-to-Off response time is
(+3.4, -0.1) ms.
Test Pattern Generation - The scramblerldescrambler function can be used to implement a 127-bit test pattern feature. For
example, a constant mark input could be scrambled and transmitted as a pseudo-random signal to be descrambled at the
receiver back to the constant mark. A transmission error would
be represented as a space for the duration of an incorrect bit.
Scrambler/Descrambler - The R24DC incorporates a selfsynchronizing scrambler/descrambler. This feature is enabled
by a discrete digital input.
Carrier Detection - The receivE!r circuit of the R24DC contains
a received line signal detector which indicates the presence of
energy at the receiver input above a certain threshold for a mini.
mum amount of time.
Receive Level -43 dBm .
. Carrier Detect Thresholds
Received Level
Carrier Detect
Greater than -43 dBm
Less than -48 dBm
Off (Line signal not present)
Carrier Detect Response Time
Response Time
Of1-to-On
On-to-Oft'
14:l:.1 ms
8±3 ms
The R24DC receives line signals from 0 to
Transmit Timing - The R24DC generates a Transmit Clock
having the following characteristics: Frequency - 2400 Hz
±0.01% (1200 Hz ±0.Q1% in fallback mode), duty cycle - 50
± 1%; The R24DC is also optionally capable of tracking an
External Transmit Clock supplied by the user. Both have similar
characteristics.
On (Line signal present)
Carrier Detect Transition
by the transmission of a continuous "one", scrambled,
Clamping - The following clamps are provided:
Respom.e Times of Clear-to-Send, -The Clear-to-Send
response times are determined by the selected configuration
of the R24DC and its associated turn-on sequence, as shown
in the following chart.
TURN-ON
. SEQUENCE
NUMBER
followe~
Receive Timirig- The modem provides a data derived Receive
Clock outputin the form of a nominal squarewave (50 ± 1% duty
cycle). The modem timing recovery function is capable of tracking a ± 0.01 % frequency error in the associated transmit timing
source.
10-86
R24DC
2400 bps Direct Connect Modem
Transmit Level - The R24DC transmitted output line signal
level may be regulated in either the permissive or programmable
modes. In the permissive mode, the transmitted line signal level
is -9 dBm maximum. In the programmable mode, the transmitted
line signal level is set by an external resistor installed by the
telephone company in the wall jack. U~ing this method, the transmitted line signal level can be controlled in increments of 1 dBm
from 0.0 to -12 dBm, depending on the value of resistance
installed.
Data Structure
INPUT
DATA
-SIGNALLING
RATE
SELECTOR
IP1-16)
Answering Tone Generation - When in the automatic answering mode, the R24DC generates a selectable answerillg tone
of 2100 Hz ± 0.01 % or 2025 Hz ± 0.01 %. It is also capable of
optionally providing this tone when in the manual answer mode.
V.26 AlB
(Pl-141
DATA STRUCTURE
Low
Low
2400 bps Alternate A
Low
High
2400 bps V.26 Alternate B
(Bell 201Cl
High
Low or High
1200 bps
Abort Timer - The R24DC contains a 15 ± 1 second abort timer,
which may be enabled via the Abort Enable input.
Answering Tone Frequency
INPUT
SELECT 1
(P1-341
ANSWERING TONE
FREQUENCY
High
Low
2100 Hz
2025 Hz
Line Current Interrupt Disconnect - The R24DC contains a
475 ± 125 ms line current interrupt abort timer, which may be
enabled via the LCIS Enable input.
The digital interchange circuits provide control, status indicators,
data clocks and data interface. Traditional RS232-type control
functions and additional signals allow the user to access the
inherent flexibility and monitoring capabilities of the R24DC.
Satellite Option and DSR Selection
Satellite
Option
DSR (P1-30)
During Analog
Loopback
AL-DSR Enable
Yes
No
Yes
No
OFF (High)
ON (Low)
ON Low)
OFF (High)
High
Low
Wired to Analog Loopback
Wired to Analog Loopback 1.
Carrier Detect Squelch
(Pl-12)
INPUTS
ANALOG
LOOPBACK
(Pl-33)
SELECT 2
(Pl·3S)
REQUEST·
TO-SEND
(PH1)
Low
Low or High
Low or High
No Squelch
High
Low or High
Low
Squelch
High
High
Low->High
Extended Squelch 2
High
Low
Low->High
No Extanded Squelch
1. Inverse of Signal applied to Analog Loopback Input.
Baud Clocks - Symbol or baud timing is available for both the
transmitter and receiver functions. These signals have characteristics similar to the data clocks except that their frequency is
equal to the signalling rate of 1200 Hz ±O.Ol%.
Analog Loopback - The R24DC can be locally commanded
into local analog looPback (CCITT Loop 3) via digital input Analog
Loopback, when in the wait mode.
SQUELCH STATUS 1
"Squelch" means that Carrier Detect is clamped off (high) regardless_of the level of received line ,ignal. When "extended ,quelch"
is enabled, squelch occurs both during the time when Requestto-Send is on (low) and for 148.3 ms (+3.4, -0.1 ms) following
the On-to-Off transition of Reque.t-to-Send.
Selection Of Clear-To-Send Response Times
INPUTS
TURN-ON
SEQUENCE
SELECT 1
IPl-34)
1
2
3
4
High
High
Low
Low
High
High
5
6
CLEAR,TO-SEND
RESPONSE TIME1
(ms)
SCRAMBLER
ENABLE
IP1-1S)
Low
High
Low
High
Low
High
SELECT 2
(Pl-35)
OFF-TO-ON
ON-TO-OFF
Low
Low
Low or High
Low or High
High
High
90
90
148.3
148;3
220
220
0
0
0
0
0
The tolerance on each Off-to-On and On-to-Off response i. 1-3.4, -0.1 msl.
10-87
a
2400 bps Direct Connect Modem
R24DC
± 1.5
OPERATING MODES
be on. Then DP (normally off) is pulsed at a rate of 9.5
pulses per second.
Line connect and disconnect sequences are controlled automatically by the R:240C which is at all times in one of the following
modes:
The pulsefequirement is a uniform train with break intervals at
58% to 64%.
The interdigit time (i.e., the time between the end of the last pulse
of a given digit and the beginning of the first pulse of a subsequent digit) should be between 700 ms and 3 seconds.
Wait Mode - This is a hot-standby mode. The R240C enters
this mode upon a power-up, Reset, or whenever an operational
mode is exited. The following diagrams illustrate the sequence
of events for the Wait mode.
C.O.P.il:! turned off after the called modem anl:!wers. Signal
sequence for this mode is shown in the following diagram.
INITIALIZE
OH· HIGH
DATA SST REAOV" HIGH
SOUELCH = ACTIVATED
RESET ABORT TIMER
Automatic Call Mode Sequence
Manual Answer Mode - This mode provides the capability of
manually answering calls with a telephone set. Signal sequence
for this mode is shown in the following diagram.
:::v
DATASET
-----~~----~-.~
ON
ON
TERMINAL
READY
VI==-l
ANSWElUNG
TONE
GENERATION
UF ENABLED
Manual Originate Mode - This mode provides the capability
of manual call origination. Calls may be originated in the usual
manner by a telephone set. Signal sequence for this mode is
shown in the following diagram.
REAOY
IiIV ABT
ENABLEJ
Manual Answer Mode Sequence
Automatic Answer Mode - This mode provides the capability
of automatically answering calls. Signal sequence for this mode
is shown in the following diagram.
~'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~
/
""I
TERMINAL
IlEAOV
--=--.,
~
OFF·HOOk
ANSWERING
ro:.
~~~~RATION
GENERATION _ _ _...:;._ _ _ _-'~\---_:_----_';_\-, __
----:::-;-----"""'''''''1;;:'1
ON
L~~s
IF ABT ENABL.E
(
TONE
~:!~:n
p-
ON
-
Analog Loopback Mode - This mode provides the capability
of diagnosing a problem in the communications link. In this
mode, the transmitter's analog output is connected to the
receiver's analog input through an attenuator.
~::~INAL
---,=------'1
I
\ (
V
"~.-----;;;;-';-----\r-\-\--{-(
Wait Mode Flow Diagram
~
M
LOW
------..,,"",
"'t
(oFF HOOK
i
I
0.,.
'. -4 t-- \
--4 f-- 0''.
SETREADV----------iLf'(l------!
Manual Originate Mode Sequence
\
~ ..........
J
~~
r+-:J
______-""=___~_'
'MOOEM
Automatic Cal.1 Mode - This mode provides the capability
of automatically originating calls by using the pulse dialing
technique.
ON HOOK·
\_
,~
HANosnl----------
ts·
=<
::
The R240C allows the user to auto dial by controlling inputs
OTR, C.O.P. and DP. To originate a call, OTR and C.O.P. must
275 ms if satellite option is selected
65 rns if satellite option is not selected
AutomatiC Answer Mode Sequence
10-88
R24DC
2400 bps Direct Connect Modem
INTERFACE CRITERIA
Analog Interface Circuits - The analog interface circuits
defined in the following charts provide power and switched network connections and a means for the user to mon~or the incoming line signals.
The R24DC interface signals are classified as digital interchange
signals and analog signals. These signals interface to the user
through the board edge connector.
Analog Interface Circuits
Digital Interchange Circuits - The characteristics of the
R24DC digital inputs and outputs are given in the following
charts.
TERM
PIN
NUMBER
DESCRIPTION
Digital Input Characteristics
I nput Logic Stata
Allowed Input Voltage Lavels
Low
High
O.OV to 0.8V sinking <10 j).A
+4.0V (VSS - lV) to +5.0V (VSS)
sourcing <10 uA
The digital inputs are directly CMOS compatible. The
capacitive loading on each input is 25 pF (maximum).
+12V
P140
-12V
P1-38
-12V Power Supply
+5V
Pl-l
+5V Power Supply
COMMON
Pl·2,
P14
Ground (signal and power return)
Receiver
Analog
Pl-32
Low impedance output of R24DC
receive filter. Gain from Tip and
Ring to Receiver Analog is nOm·
. inally 12.7 dB
Digital Output Characteristics
Ouput Logic Stata
Low
High
+12V Power Supply
TELEPHONE INTERFACE
LEADS
Allowed Output Voltage Levels
O.OV to O.4V sinking 0.36 mA
4.0V (VSS - W) to 5.0V (VSS)
sourcing 100 j).A
The digital outputs are directly CMOS or 10wllower Schottky
TTL compatible.
TIP
RING
P2-9
P2-10
PR
PC
P2-2
P2·4
for programmable mode
MI
MIC
P2-3
P2·1
Leads routed to contact on exclusion key of associated telephone
Telephone Line Leads
Leads to external wall jack resistor
set
DIGITAL OUTPUT CHARACTERISTICS
(EXCEPTIONS)
The exceptions to the above are outputs OH, RI, SH and A. Outputs OH, RI and SH have the following characteristics:
R24DC
Output Logic Stata
Allowed Output Voltage Levels
Low
High
O.OV to 0.4V sinking 0.36 mA
2.4V to 5.0V (VSS) sourcing 100 p.A
RECEIVED ANALOG
DIAL PULSE
COP
CF
DB
cc
SB
DO
Output A, useful in the generation of eye pattern and diagnostic
information, switches from +5.0V to -12.0V.
CE
DATA SIGNALLING
Audio Interface Input Impedance
Paramater
CA
CH
BA
oA
Specification
On-Hook DC
DC resistance between Tip and Ring, and
between either Tip or Ring and signal
ground is gr.ater than 10 megohms for
DC voltages up to 100 volts.
On-Hook AC
On-hook AC impedance measured
between Tip and Ring is less than 40 K
ohms (15.3 Hz minimum)
Off·Hook DC
Less than 200 ohms
Off·Hook AC
600 ohms nominal when measured
between Tip and Ring
Longitudinal
Balance
Meets requirements of FCC Rules,
Part 68
I~~~~CTS
CARRIER OET
TX DATA ClK
DSR
RX DATA
RX DATA CLK
SH
RI*
OH
CD
~~~~~
RTS
RATE SET
TX DATA
EXT TX CLOCK
OTR
ABT
ENABLE
SCRAMBLER
ENABLE
ABORT
ENABLE
LCSI
ENABLE
TELEPHONE
INTERFACE LEADS
)
CONFIGURATION
CONTROLS MAY
BE STRAPPED HIGH
OR lOW AS DESI RED
NOTES
.. REQUIRED IF AUTO ANSWER IS IMPLEMENTED.
•• AUTOMATIC CALLING CAPABILITY CAN BE EASILV IMPLEMENTED WITHIN THE DTE.
FCC Registration Number: AMQ9SQ-6BB13·DM-R
Ringer Equivalence: 0.9B
Typical R24DC to OEM Interconnections
for Half-Duplex Applications
10-89
R24DC
2400 bps Direct Connect Modem
r
r--
"
T
~
~
M.
ill I
"
I
I
T
r--~
13,
M.C
PR
PC
~
M'C
M.
~
'--
(111
I
I
<:::::::::> TO DTE
I
-
I
L
MINIATURE
PLUG
I
R24DC
12,1
12' I
ST=ARD
--,
-
14'
RJ36X
JACK
~
~.
-
~}
R
NOT USED
I
NEtWORK
EX
r-~~-4~R~M______roTN
2
•
4
T
"M.C
..
CORD
•
J
I
5
•
+':+-+-H-H----l--7
•
~--JI~,-+--~~
EX
.l
-I-
L---+-----'''''-I~*---'---+_ORN
;:~N~I::R·~M=ER:----""'"
TO NETWORK
.
MI
(HI-%)
TELEPHONE HANOSET
'----t---.:I'
TYPE RTC
OPTIONED FOR DATA SET
M'C
CONTROL OF THE LINE
NOTES
1.
2.
3.
4.
MI AND MIC ARE REQUIRED ONLY If HANDSET IS EMPLOYED.
PR AND PC ARE REQUIRED FOR PROGRAMMABLE MODE ONLY.
STANDARD TELEPHONE
PROVIDED JACK RJ16X. RJ45S,OR RJ41S.
RJ36X OR CONNECTING alaCK IS REQUIRED ONLY IF TElEPHONE HANDSET IS EMPLOYED, WHEN THE A24DC IS IN THIS
PERMISSIVE MODE, THE RJA2X ADAPTER AND RJ11C JACK MAY BE EMPLOYED WITH THE ASSOCIATED TELEPHONE SET.
co,.
Typical R24DC to Network Interconnection
Telephone Line and OEM Connections -- Connection of the
.R24DC telephone interface pins to the network is made via
standard jacks and plugs. A typical installation, including an
optional telephone set, is illustrated.
Timing Jitter -- The maximum steady slale timing jitter of
Received Clock with respect to Transmil Clock is less than 10%
pop for an input signal-Io-noise ratio of 12 dB.
Bit Error Rate -- The following graph represents typical R24DC
performance.
Telephone Set - If il is desirable to have manual call origination or alternate voice capability, an exclusion key telephone set
(configured as Modem Controls the Line) may be ordered from
your local telephone company.
Mounting and Signal Routing -- The R24DC may be physically
incorporated into your OEM end product by using either the four
corner (0.156 inch) diameter mounting holes or by using board
guides. The electrical interface is via edge connector(s).
Interface Mating Connectors
Typel
PI (DTEI Connector
P2 (Telephone Linel
Connector
Type:
40 pin
0.100 in. spacing
20 pins per side
10 pin
0.100 in. spacing
20 pins per side
Winchester:
T&B Ansley:
Spectra-Strip:
5340-0
60940l5M
8074005-001
53-10-0
609-1015M
80"} -, 005-00 1
Manufacturer
1\ .
,
i
I
.\_
""~4-:.-"~~7--:-.---!.--,J'.~'''''-'~'--::I3c'-:',.~"
SIGNAL TO NOISE RATIO (DB)
1. 1200 BPS, BACK·TQ·BACK, SCRAMBLER, NO EQUALIZER
2. 2400 BPS, V .2eA OR B, BACK·TO.BACK, SCRAMBLER.
PERFORMANCE DATA
NO EQUALIZER
3. 2400 BPS, V .26ADR B, 15°.150 !oIZPHASE JITTER, NO
SCRNt/lBLER, NO EQUALIZER
The R24DC is a high performance synchronous 2400 bps DPSK
modem, utilizing a coherent demodulation technique to achieve
reliable operation over the switched network or uncondiiioned
lines.
4. 2400 Sho. ~ .26A OR B. 30°.120 HZ PHASE JITTER, NO
SCRAMBLER, NO EQUALIZER
5. 2400 BPS. V .26A OR B. 3002 UNCONDITIONED LINE.
NO SCRAMBLER, EQUALIZER
Typical Bit Rate Performance
10-90
2400 bps Direct Connect Modem
R240C
,
'
<,
modem
Phase error and eye pattern canbElexiremely useflii lot
acceptance testing, product evaluation, and obServation ofline
signal quality under actual operation.
.
Phase Error - Phase error can be measured by using the
modem's output signals PE, SYC, and A. With an external test
circuit, a numerical value can be derived to indicate the quality
of received data. This numerical value can be directly correlated
to bit error rate performance. The required test cireuit can. be
implemented with discrete circuitry or in software within a
microcomputer.
Eye Pattern - By using the mod.ems digital output signals
RCVDS, SYC, and A along with an added test circuit, the user
can generate an oscilloscope quadrature eye pattern. This pat- .
tern displays the received signal as a group of dots in the base·
band signal plane; hence, it is a graphic representation of
.~
modem performance.
POWER REQUIREMENTS.
.':'
Ripple
Maximum
Cu.rant
100 in\{ pop
. 50 inV p-p
50 mV p-p
1l0mA
70mA
140mA
Voltage
+5VDC±5%
+12 VDC±5%
-1~yDC±5%
ENVIRONMENTAL SPECIFICATIONS
Operating Temperature: OOC to 60·C
Storage Temperature: -40°C to + 90·C
Relative Humidity: to 95% (non-condensing)
Altitude: -200 to 10,000 feet (-61 meters to 3,049 meters)
Burn-In: 96 hours at700C
CIRCLE REPRESENTS
PROPER POSITION OF
HIGH QUALITY SIGNAL
DISPERSION AROUND
PROPIOR·PDSllIQN DUE
TO COMBINAtiON OF
RANDOM NCISE;:""HASE
ERROR.AND/OR GAIN
ERROR.
MAXIMUM DIMENSIONS
Width: 4.988 in. (12.669 cm)
Length: 7,900 in; (20.066cm)
Height: 0.50C) in.'{1.270 cm)
Typical Eye Pattern: 4 Phalle-2400 BPS-1200 Bau~ (V26A)
1,.,.
10·9:1
R24LL
Integral Modems
'1'
Rockwell
R24LL
2400 BPS MODEM
INTRODUCTION
FEATURES
The Rockwell R24LL is a high-performance serial synchronous
2400 bps DPSK modem. By utilizing state-of-the-arfMOS/LSI
technolog}';theR24LL provides the user with enhanced performance and reliability in a small package. Implemented on Ii
single printed circuit board, the R24LL is less . than 26,square
inches.
.' Hi!;lh Performance-Low Cost
• LSI High Density-Low Power
• Bell 201B/C, CCITT V.26 AlB Compatibility and V.26 bis
AlB Compatibility
• DTE Interface LSTTL/CMOS Compatibility
• ExternalTransmit Data Clock Tracking
• Diagnostic Outputs Available for Eye Pattern Generation and
.
Data Quality'Monitoring
TheR24LLoperates in either the fUll-duplex (4,wire telephone
connection) or half-duplex (2-wire ,telephone connection) mode.
The R;14LL is designed for easy integration into a user's system, .
e.g., a Simple box or rack-mount modem,statistical multiplexor,
error controller, terminal, PBX, or any other communiciltions
product thilt requires the. utmost in reliability and performance
tor diltil transmission over. voice-grilde telephone lines: ;
• Fixed Compromise Equalizer (Strap Selectable)
• 2400/1200 bps Modes
., Transmitter-Differ~ntial Phase Modulation
.•. Receiver-Coherent Phase Detection
• Operating Modes:
:""Hilif-Duplex (2-wire)
......,Full-Duplex (4-wire)
• OutstahdingPerforri-iance Overtlnconditioned Lines
• V.27 Scrambler/Descrambler Compatibility
• Answer-Bilck Tone Generation
• Cleilr-to-Send Delay Options
• NSYNC Option for Rapid Resynchronization in Multi-Point
Applications
• Small Size-Less than 26 sq. in.
• Typical Power Consumption-3 watts
• Power Requirements, +5 Vdc and :t 12 Vdc
The R24LL is ideal (or data transmission i1Pplications over either
.2,wire or 4-wlre leased (dedicated) telephone lines orthedial.up telephone network, Bell 201 B/C, CCITT V ..26.A/Band V.26
bis AlB compatible, the R24LL modem offers the user flexibility
in creating a 2400 bps modem design customized for specific
packaging and functional requirements,
Document No. 29200N05
Data Sheet Order No_ MOOS
1();'92
Rev. 1, March 1983
R24LL
2400 BPS Modem
RECIN
EQIN
CARRIER
DETECT
CIRCUITRY
REF
RECEIVER
DEVICE.
SAMPLE
AND
HOLD/DAC·
MOS/LSI
TRANSMITTER
·osc
T1
DIVIDER
REC
OSC.
DIVIDER
(11043)
DECISION
DEVICE
REF
TRANSMIT
DAC
TRANSMITTER
. DEVICE
MOS/LSI
(11044)
MOSiLSI
(11042)
DIGITAL
INTERCHANGE
CIRCUITS
DIAGNOSTICS
A
SYC
RCVDS
PE
R24LL Functional .BlockDJagram
FUNCTIONAL SPECIFICATIONS
Data Encoding (I!IPSKj~At 2400 bps, differential' 4-phase
modulation is employed. The .data stream to be transmitted
divides Into pairs of consecutive bits (dibiis ). Each dibjt is encoded
, as a phase change relative to ,the phase of the immediately preceaing signal element. Two alternative ~rrangements of. coding
are possible (In aooordance with cCln RecommelJdations V.26
and V.26 bis) as shown In the following chart.
Transmitter Carrier Frequency-1800 Hi ± 0.01%
. .. Echo Suppression ,and Answerlng Tone Frequencles-2100
Hz ± 0.01% or 2025 Hz ±0~01%
Received Signal Frequency Tolerance-The receiver can
adaplto received frequency errors up to ± 10Hz with less than
a 0.5 dB degradation in bit error rate.
Data Signaling and. Modulation Rata':'"""The normal signaling
rate is 1200 baud :1:. 0.01% and a data rate of 2400 bps ±
0001%. The fallback signaling rate is 1200.baud ± 0.01% and.
a data rate of 1200 bps ± 0.01%.
Data Encoding .
2400 BPS
Transmitted 'Data Spectrum-The transmitted spectrum's
bandwidth extends from 800 Hz to 2800 Hz. Phase'distortion
characteristics fall within the limit.s specified in cCln Recom-.
mendation V:26 bis. Theout-of-band-signal power limitations
meet those specified by Part 68 of. Tariff 261 of the FCC's regulations and typically exceed the requirements of international
regulatory bodies as well.
Phe"Cheng.
Dlblf
V.26A
00
0"
+90'
+t80"
+270"
01
11
10
10-93
. V;288/BeII ~1
:t45'
+135'
+225'
+315'
R24LL
2400 BPS Modem
Turn Off Sequence-When the transmitter has been sending
data and. "Request-to-Send" is turned off, any remaining data
bit information transmits within 6 milliseconds.
V\TVV\J\T. ..-U
1'1
+45'
ALTERNATIVE B
f\
+135"
~
f\
+225"
I
Response Times of Clear-to-Send-The selected configura.' tion of the R24LL and its associated turn-on sequence determine the Clear-to-Send response times, as shown in the following
chart.
+315"
,
f\, f\ if\ [\
\TVV\JW V\J
Scrambler/Descrambler-The R24LL incorporates a selfsynchronizing scrambler/descrambler enabled by a discrete digital input.
Reference Line Signal Diagram (V.26 A&B)
Carrier Detection-The R24LL contains a received line signal
detector. This detector indicates the presence of energy at the
receiver Input above a certain threshold for a minimum amount
of time.
.
At 1200 bps, differential2-phase modulation is employed. Each
bit to be transmitted is encoded as a phase change relative to
the phase of the immediately preceding signal elennent. The
encoding is in accordance with CCITT Recommendation V.26
bis as shown in the following chart.
Bit
Carrier Detect Thresholds
Data Encoding
Received Level
1200 BPS
Greater than-43 dBm
Less than -48 dBm
Phase Change
Carrier Detect
On (line signal present)
Of! (line signal. not present)
a
1
Carrier Detect Response Time
Carrier Detect Transition
Response Time
Oll-Io-On
On·to-Of!
14± 1 ms
8 ± 3 ms
Turn On Sequerices-The transmitter of the R24LL can generate a total of 13 Selectable twn-on sequences, as shown in
the following chart.
Turn-On Sequences
Type of
Line Signal
Segment 1
Segment 2
Total of
Segments 1, 2
Turn-On
Sequence
Number
Continuous
Unscrambled
Ones
Continuous
Scrambled'
Ones
Nominal Total
Turn On Sequence
Time 2
Oms
6.67 ms
8.33 ms
30 ms
8.33ms
90 ms
8.33 ms
148.3 ms
8.33 ms
220 ms
8.33 ms
800 ms
8.33 ms
Oms
Oms
Oms
Oms
21.67 ms
Oms
81.67 ms
Oms
140 ms
Oms
211.7ms
Oms
791.7 ms
1
2
3
4
5
6
7
8
9
10
11
12
13
Oms
6.67 ms
8.33 ms
30 ms
30 ms
90 ms
90 ms
148.3 ms
148.3 ms
220 ms
220 ms
800 ms
800 ms
Comments
V.26
(scrambler inserted)
V.26, V.26 bis
(scrambler inserted)
(scrambler inserted)
V.26 bis
(scrambler inserted)
V.26 bis
(scrambler inserted)
Notes:
1. See paragraph titled Scrambler/Descrambler for a description of scrambler/descrambler facility.
2. For those turn-on sequences in which the scrambler is inserted, the transmitted line Signal corresponds to a continuous "one" ,unscrambled,
for 8.33 ms·ten baud (symbol) intervals, followed by the transmission of a continuous "one", scrambled, for the remainder of the turn·on
sequence.
10-94
2400 BPS Modem
R24LL
Clear-To-Selld Response Times
Turn-On
Sequence
Number
Clear-To-Send
Response Times'
Off-to-On
Equalizer-:-The R24LL contains a fixed' compromise delay
equalizer which improves performance over the domestic
switched network. The equalizer may optionally be positioned
in the receiver or removed. entirely by means· of a jumper plug.
It has a nominally flat 0.0 dB amplitude response.
Comments
On-to-Off
1
Oms
Oms
2
6.67 ms
Oms
switched carrier
4-Wire (BELL 201)
3
8.33 ms
O.ms
switched carrier
4-wire
4
30 ms
Oms
CCITT 4-wire
5
30 ms
Oms
CCITT 4-wire with
scrambler
6
90 ms
Oms
CCITT 2-wire
7
90 ms
Oms
CCITT 2-wire with
scrambler
8
143.3 ms
Oms
switched' carrier
2-wire
9
143.3.ms
Oms
switched carrier
2-wire with
scrambler
10
220 ms
Oms
CCITT 2-wire
echo protection
11
220 ms
Oms
switched 2-wire
echo protection with
scrambler
12
800ms
Oms
CCITT 2-wire auto
call
13
800 ms
Oms
CCITT 2-wire auto
call with scrambler
Test Pattern Generation-Thescrambler/descrambler function can be used to implement a 127 -bit test pattern feature. For
example, a constant mark input could be scrambled and transmitted as a pseudo-random signal to be descrambled at the
receiver back to the constant mark. A transmission error would
be represented as a space for the duration of an incorrect bit.
Receive Level-The R24LL receives line signals from 0 to -43
dBm.
TransmitTiming-The R24LL generates a Transmit Clock with
the following characteristics: Frequency--'2400 Hz ±0.01 %
(1200 Hz ± 0.01% in fall back mode), duty cycle-50 ± 1%.
The R24LL can also optionally track an External Transmit Clock
supplied by the user. Both have similar characteristics.
Receive Timing-The R24LL provides a data derived Receive
Clock output in the form ofa nominal squarewave(50 ± 1%
duty cycle). The timing recovery function can track a ± 0.01 %
frequency error in the associated transmit timing source.
Secondary Channel-The R24LL provides the user sufficient
flexibility to add an external secondary channel if desired. (A
secondary channel is a data transmission channel having a
lower signalling rate and occupying a different portion of the telephone line bandwidth than the primary channel. The primary
and secondary channels share the same transmission facility,
the telephone line.) Additional receive filtering to allow simultaneous operation of the secondary channel must be provided
external to the R24LL.
Note:
• The tolerance on 'each' Off-to-On and On-to-Off response
time is (+.9, -.1) ms.
Trallsmit Level-The transmitted output line signal.l.evel of the.
modem is -1.0 dBm ± 1.0 dBm when the transmitter output is
terminated with a 600 ohm resistor in series. This applies to all
possible transmitted data patterns both at 2400 bps and 1200
bps, as well as to answering tone generation.
Clamping Options-The following clamps are provided with
the R24LL:.
1. Received Data. The Received Data output is clamped to a
mark when Carrier Detect is off. This action prevents disturbances on the line from getting through the receiver circuit
to the data output.
Answering Tone Generation-The R24LL can generate an
answering tone al2100 Hz ± 0.01 % or. 2025 Hz ± 0.01 %
(selectable) for 3.4 ± 0.2 seconds under the control of an input
logic signal (CAUTO). The R24LL also provides a digital output
(TONA) indicating the conclusion of answering tone generation.
2. Carrier Detect Clamp. The Carrier Detect output is clamped
off (squelched) when Request-to-Send is on. An oPtion
extends this clamp for 148 milliseconds beyond transitioningoff, thus providing echo protection.
New Sync-Pulsing the New Sync (NSYNC) digital input forces
Carrier Detect Off and causes the R24LL to resynchronize rapidly on sequences of incoming messages. This feature is necessary in some polling applications because the receiver
maintains the timing information of the previous message for
some time after it has ended-this may interfere with resynchronization on receipt of the next message from a different
remote transmitter.
3. Receive Clock Clamp. The Receive Clock output is clamped
off when Carrier Detect is off. This action prevents any disturbances from propagating through the receiver cirCuit to the
receive clock output,
10-95
II!]I
R24LL
2400 BPS Modem
Fast Energy Detector-A received line signal detector, the fast
energy detector's output (RLSD) has the same threshold and
hysteresis characteristics as the Carrier Detect. For RLSD the
maximum turn-on time is 1.6 ms and the maximum turn-off time
is 6.6 ms (both times for Equalizer not inserted). Furthermore,
the RLSD output will respond to transient line conditions (no
momentary dropout or momentary-on glitch protection).
CP15, RW/4W, TH09, FSYC, TC09, and PBS. If answerback
or echo suppression tone generation capability is required, the
input CAUTO (which should be strapped low if not used) and
the output TONA are available. Implementation of the New Sync
function requires any new sync pulses to be inputted to NSYNC.
The outputs SYC, RCVDS, DCP, A, and PE can be used to generate eye pattern and phase error diagnostic information.
Baud Clocks-Symbol or baud timing is available for both the
transmitter and receiver functions. These signals have characteristics similar to the .data clocks' except that their frequency
is equal to the signalling rate (1 :200 Hz ± 0.01 %). Transitions
on Transmitter Baud Clock and Receiver Baud Clock coincide
with Off-to-On transitions of Transmit Clock and Receive Clock,
respectively. For 2400 bps operation both baud clocks are low
for the first data bit in a baud and high for the second data bit.
Analog interface connections. The GAIN-G1-G2 jumper (for
threshold set selection) should be in the proper location as
described in the table at the top of page 9. Note that input
impedance at REC IN is a resistive 15.BK ohms. If a 600 ohrn
receiver input impedance is desired, an external resistor to
signal ground must be added. Take care when routing to REC
IN (for low. level receive signal) from any telephone interface
circuitry. Also note that it is possible to insert the equalizer into
the receiver or not to insert it by use of the jumper on the board.
Implementation of a local analog loopback scheme could be
achieved in many ways. If the line interface connection as
shown in the diagram below is employed, the user can create
a local analog loopback simply by deactivating squelch. To isolate the telephone line during this loopback (no transmitted
line signal), additional circuitry must be added.
Analog Loopback-The R24LL provides the flexibility to implement a variety of analog loopback schemes using a minimum
amount of external circuitry.
Eye Pattern/Data Quality Detector-The R24LL outputs digital signals (RCVDS, SYC, A) which the user can decode to
generate a quadrature eye pattern. The eye pattern is a visual
(oscilloscope) display showing the received signal as groupings
of dots in the baseband signal plane. It is useful as an incoming
modem test and product evaluation tool and as an indication of
a line condition in actual operation (useful for some network
control applications).
Full-Duplex-In a full-duplex application, the user needs both
transmit and receive capabilities simultaneously. A 4-wire line
connection is required.
The only differences with half-duplex are that REC IN is no
longer connected to T1 (the transmitter and receiver have independent transmission paths) and the squelch function would be
deactivated (except during New Sync) by use of the input T2W/
4W.
The modem also outputs digital signals (PE, SYC, A) which the
user can decode to generate a data signal quality detector. This
indicates if a reasonable probability of errors is received on the
data channel.
Digital interface connection is the same as for the half -duplex.
CONFIGURATIONS
Analog interface connections. With the exception of the 4-wire
line interface, analog interface connections are the same as
half-duplex. Implementation of a variety of local or remote analog
or digital loopback schemes requires the addition of a minimal
amount of external circuitry.
The R24LL modem provides the user with a wide range of
modem functional configurations. Some of the possibilities are
described below.
Half-Duplex (2-Wire)-ln a half-duplex application, the user
needs both transmit and receive capabilities (although not
simultaneously) on a 2-wire connection.
If a hybrid (4-wire -- 2-wire) transformer is not employed as a
line interface device, REC IN would be strapped to T1 through
an extemal resistor, the user perhaps selecting this resistor to
produce a specific output impedance or to compensate for
losses in any line interface circuitry.
RECEIVER
Digital interface connections. In a typical application, the user
controls basic modem operation through the digital Signals T103,
T105, T106, T114, T104, T115, T109, and perhaps RBCK,
T113, or TBC. (T113 is used if transmit timing is to be locked
to the customer's clock; TBC may be employed to minimize certain timing delays and is useful in some multiplexing operations).
A number of digital inputs can either be fixed (tied directly and
permanently to the +5V supply [high] or to signal ground or the
-12V supply [low] in accordance with the specific requirements)
or, if the user desires programmable flexibility, these signals can
be interfaced with his equipment. Signals of this type include
T111, V26A, 1, SBGR, K, Y, TC06, BOOMS, E, T2W/4W, CP04,
n
RECIN
TRANSMITTER
R
."tv
EXTERNAL
REGISTER
TO LINE INTERFACE
CIRCUITRY
R24LL Half-Duplex Mode
10-96
Tl
,.
R24LL
2400 BPS Modem
INTERFACE CRITERIA
The R,24LL interlace signals' are classified as digital interchange
signals and analog signals. The signals interface to the modem
user through the board edge cOnnector.
Digital Interchange Circuits-The characteristics of the R24LL
digital inputs and outputs are given in the following charts:
Digital Input Characteristics
Inj)~t Logic State
Low
The digital inputs are directly CMOS compatible. The capacitive
loading on eaCh input is 25 pF (maximum).
Digital Output Characteristics
Output Logic Stale
Pl-A21
R2W/4W
P1-A22
Receiver Baud Clock
(RBCK)
Pl-A23
PBS
Pl-A24
TH09
Pl-A25
Transmitted Date
(Tl03)
Clear-to-Send or
Ready-for-Sending
(TID6)
Data Signalling Rate
Selector (Tl11)
P1-A29
ADowed Input Voltage Levels
-12V (Voo) to 0.8V sinking <10 p,A
+4.0V (V ss - W) to +5.0V (V ss) sourcing
<10 p,A
High
DCP
Receive Clock
(TllS)
Allowed Output Voltage Levels
E
Low
O.OV to 0.4V (-0.4V to +0.4V for RLSD)
sinking 0.36 mA
+4.0V (V S8 - 1V) to +5.0V (V sS> sourcing
100 p,A
High
T2W/4W
Y
The digital outputs are directfy CMOS or low-power Schottky TTL
compatible.
Transmitter Baud
Clock (TBC)
A
Pl-A30
Input determining whether transmitted data rate is 2400 bps or
1200 bps.
Pl-A33 Output providing received signal
element timing Information.
Pl-B6} Inputs affecting Clear-to-Send rePl-B7
sponse time and Tl09 Squelch.
Pl-B8
Input affecting Ready-for-Sendlng
response time and answering tone
frequency.
Pl-Bl0 Output b8.ud clock (1200 Hz).
Pl-Bll
Pl-BI5
Pin
Number
TONA
Pl-AS
800MS
Pl-A6
TCOS
PI-A7
K
Pl-A8
X
CAUTO
Pl-A9
Pl-A10
New Sync (NSYNC)
CLAMP
Fast Energy
Detector (RLSD)
Fast Sync (RSYC)
Pl-A13
Pl-A15
Pl-A17
S8GR
P1-A18
Pl-A19
THRH
Pl-BI8
V26A1B
Pl-BI9
CP15
Pl-B20
RCVDS
SYC
PE
TC09
Pl-B21}
Pl-B22
Pl-B23
Pl-B24
CP04
Extemal Transmit
Clock (T113)
Pl-B25
Pl-B29
Request-ta-Send
(Tl05)
Received Date
(Tl04)
Transmit Clock
(T114)
P1-B30
Description
Output indicating completion of
answering tone.
Input affecting Clear-to-8end response time.
Input affecting Clear-to-Send response time.
Input affeeting Ready-for-Sending
response time.
Input affecting T109 Squelch.
Input initiation transmission of answering tone.
Input affecting Tl09 Squelch.
Input forcing squeIch of T109
Input generating Tl09.
Input determining whether fast
sync feature (fast resynchronization upon recovery-of received line
signal following momentary drop. out) is enabled.
Input determining whether the
modulo 8 pattern guard will be Incorporated Into the scrambler
facility.
carrier Detect
(Tl09)
Pl-B31
Pl-B33
Pl-B24
Note:
The following PI connector pin locations should be left open and unconnected:
A4, All, A12, A14, A16, A20, A35, Bl, B12, B13, B14, B17; B32, and B35.
10-97
Input determining Tl09 On-to-Off
response time.
Input affecting state of THRH
output.
InpUt for digital data to' be
transmitted.
Output indicating readiness to accept data for transmission.
Pl-A32
Digital Interchange Circuits
Term
Digital output enabling user to
generate eye pattern and phase
error diagnostic information.
Input affectihg state of THRH
output.
For 2400 ,bps operation.
Digital output enabling user to
generate eye pattern and phase
error diagnostic information.
Input determining whether scrambler is to be inserted.
Output used in conjunction with
carrier detect circuitry to implement Tl09 threshold set select
function.
Input selecting dlbitencoding at
2400 bps operation as per V.26
Alternate A or V.26 Alternate B.
Input selecting optional clamping
of Receive Clock (TllS).
Digital outputs enabling user to
generate eye pattern and phase
error diagnostic information.
Input determining Tl09 Off-to-On
response time.
Input determining Tl04 damping,
Input providing modem with transmitted signal element timing
Inlofmation.
Input to transmitter.
Digital 'data output from' modem
receiver.
Output providing user with transmitted signal element timing
infonnation.
Output indicating presence of signal energy on receiver line.
R24LL
2400 BPS Modem
Tone Generation
Data Structure
Inputs
Input
Data Signalling
Rate Selector
(P1-A32j
Data Structure
V26 AlB
(P1-B19)
Low
Low
Low
High
High
Don't
Care
2400 bps Atternate A
2400 bps V.26 Alternate B
(Bell 201C)
1200 bps
Outputs
CAUTO
(P1-A10)
Y
(Pl-B8)
TONA
(P1-A5)
Transmitted Signal
Low
High
High
High
Don't Care
High
Low
Don't Care
High
High
High
Low
Normal Operation
2100 Hz .Answering Tone
2025 Hz Answering Tone
Norm!!1 Operation
Selection of Clear-To-Send Response Times
Clear-Ta-Send
Response Times
(ms)
Inputs
Turn-On
Sequence
1
2
3
4
5
5
6
6
7
8
9
9
9
10
10
10
11
12
Y
(p1-a8)
Low
High
High
High
High
High
High
High
Low
Low
High
High
High
High
High
High
High
High
800MS
(Pl-A6)
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
Low
Low
TC08
(Pl-A7)
T2W/4W
(Pl-B7)
Don't Care
High
Low
Don't Care
High
High
High
High
Don't Care
Don't Care
Low
Don't Care
Low
Low
Don't Care
Low
Don't Care
Don't Care
High
High
High
High
Low
High
Low
High
Low
Don't Care
Don't Care
Low
Low
Don't Care
Low
Low
Don't Care
Don't Care
K
(Pl-A8)
Don't Care
Low
Low
Low
Don't Care
High
Don't Care
High
Don't Care
Don't Care
High
Don't Care
Don't Care
High
Don't Care
Don't Care
Don't Care
Don't Care
I
(P1-B15)
Low
Low
Low
High
Low
Low
High
High
Low
High
Low
Low
Low
High
High
High
Low
High
E
(Pl-B6)
Don't
Don't
Don't
Don't
Low
Don't
Low
Don't
Don't
Oon't
Don't
High
Don't
Don't
- High
Don't
Don't
Don't
Care
Care
Care
Care
Care
Care·
Care
Care
Care
Care
Care
Care
Care
Care
Off-ta-On
On-ta-Off
6.67
' 8.33
30
30
90
90
90
90
148.3
148.3
220
220
220
220
220
220
220
800
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note: The'tolerance on eachOIl-to-On and On-to-Oll response time is (+0.9, -0.1 ms).
Carrier Detect Squelch
Inputs
X
(Pl-A9)
T2W/4W
(Pl-B7)
E
(Pl-S6)
Tl05
(P1-B30)
Don't Care
Oon't Care
Low
High
High
High
Don't Care
High
Low
Low
Low
Low
Don't Care
Don't Care
Don't Care
Don't Care
High
Low
Don't Care
Don't Care
Don't Care
High
High-->Low
Hig~Low
NSYNC
(P1-A13)
Squelch Status
Low
High
High
High
High
High
Squelch
No Squelch
No Squelch
Squelch
Extended Squelch
No Extended Squelch
Notes:
"Squelch" means that Carrier Detect (TlOg) is clamped off regardless of the level of received line signal. During squelch, CLAMP
(T-13) is a low impedance to ground. For normal operation (no squelch) CLAMP (T-13) is in a high impedance ("open drain")
state.
When "extended squelch" is enabled, squelch occurs both when Request-to-Send (Tl0S) is On (High) and for 148.3 ms (+0.9,
-0.1 ms) following the On-to-Off (High to Low) transition of Tl 05.
10-98
R24LL,
2400 BPS
Carrier Detect Threshold Sel~tlon
Gain
Strap "
THRH
High Impedanca
High Impedanee
Low impedanCe
to ground
The receiver and iransmitter line interfaces are' single-ended,
(non·transformer coupled) signals ' w.ith the following charac·
teristics:
Selilctecl
Th....hbld Set'
131
-43 ciBm,-48 dBm
..,33 dBm, -38 dam
-26 dBm,-31 dElm
132'
131 or q2
Transmitter Voice FrequenCy
2., Maximum Output Level: ..0.0 dBm as measured-per the fol·
low.ing 'diagram using, a, true' RMS
meter.
'
'"
,:
THRH Operation
"
Input
TH09
Low
High
Low
High
Output T1
1. ,Output Impedance: ImpedanCE! of Op-Amp
Gain must be shorted to eithar G10r G2.
;
MOdem "
THRH
R2w/4W
H)gh ImPedance ",.
Low
Low
High
High
I
I
I
High Impedance
High Impedance
Low Impedance
THRH.is ari open-driiindnV$f representirig either a low imped'
anca to ground «5OQ ohms) or a V$ry' high impedance state.
,
>---'r-__T"'1'Ir-,6QO-.J'w+'V.~1".-.~~~~E AMS
600 + .1%
I
'Scrainbler/D.scnimbler "
," Input
i
(P1-St5)
High
oOn'l cafe
Low
High
High
Low
S.crambler/DellCrambler '
Configuration
SaGA
(P1-At9)
NQ Scrambler
Scrambler V.27bls, ler
(modylO 8pallern guard)
(no modulo 8 pattern guard)
. ReceIVer Voice' FrequenCy Input REC ,IN
1. Input ImpedanCE!:. 1.5:6K
ohms ± '1% resist~ve
.,
,..~.
Analog Interface Clrcults-Theanillog il"ltE!rf~e, circuits of the
R24LL defined in the following chart provide the power, the
switched network connections; and a means for the user· to
monitot the incoming line signals.
'
The output level at the R24LL line interface is,less,!han -60,
dBm in theJrequency ban,dbf 1 Hz to 1? Hz 'lVhen tbe}T1odem
is not IranSQ'litting, AperiQ,(I, of ,1 00 millisecol1(1s is reqljired for:
the line interfaces to sta:bllze fOllowing power~!n-on; , I:
,loW impedance VoiCe f~quencyoutpiJt 1'.1
satisfie~ appli6atlons
interfacing with lossy triinsform&rs or hybrids, .The characteristics T1 output~: ,
"',
Analoglntertac:. ClrcuHs
"
T"",
Pin
Number
of
DellCrlptlon
+12V'
-12V
+5V
COMMON
P1-B5,89
,~ :
1>1"A1
P1~A2, 52
P1-A3, ~1,a3
T1
P1-A34
",
+12V PowerSupply.
'-12V Powat !)Uppjy'· .
+5V, powar Supply
Ground (signal, :iIIIJd pOwer
return)
T1 lathe low Impedance
transml1llir analog O\JIpUt~ln,a
signal). The' T1, ,allows the
ullllr the flexibility neeiled to ,
c\jStOmize his output impedance' (to compe~ta for
transforl'ller losses, for in-
a. Output Impedance: Essentially zero ohms y/hen loadep to
grovnd with, greater', than, 400"olir'ns
(resistiv~). This, ill a di,rectqutput from an
oPerational amplifier'.
b. Minimurrl Lqad: ';,; 400 \l,hrn$' (reSistive) as measured Qatween
T1and s,ignal ground.
PEAFPR"'~NCE.D~TA " • ,'"
TheR24LLisa high pertOrmancesyi1cl1ronous 2400,bps;[)PSK
mOdElrit,lt ~iliZesa,coh.erent(lel'liOdulation tecl1nique·to achieve
reliable operatTon over the sWitchednelwOrk or unConditioned
lines.'
,
~).
SE;CONDARY IN
P1-S4
RECIN
P1-836
,
2. Maximum Input Level: ..0.0 dBm
SecOndary channel Input
from the DiE.
RecelV$ fittar input. Input
impedance is a resistiV$ 15.8
K ohms ± 1%.
Timing, Jitter"'"the maximum steady state timin!i' iitt~r 'of
ReCeiVed Clock with respect to TFan$rnitClock is less than to%
pop foranh,pUt)signal~to-noi,se' ratio of 12 dB.
Audio Interface-The aUdio jlJ~rfaceiriCludes the R24LL's
interface with the transmission' network,
BH E,rrorflate-The fbll6\ving graph representstypicaiR24LL
perfOrmance.
'
10-99
2400 BPS Modem
R24LL
DISPERSION
d
r-@-- r2,_
10-4
~
/@
-T
I
'"
t--
~;U
Oi==:>-
,\
\\
::
\\
1\ \ ® ~V
-- -
v
COMMUNICATION
CHANNEL
Figure 2.
Receiver Interconnection
MODEM OPERATION HALF OR FULL-DUPLEX
DTE - Data Terminal Equipment
The modem modules provide the user with all the necessary interfaces connections to implement almost any loopback scheme
desired. With a minimum amount of external circuitry, loopback
testing can be controlled via a communications adapter/software
approach or manually. For local analog, remote analog and
remote digitalloopback, the V.27 scrambler within the modem
can be used to generate a 127-bit word.
Figure 3 indicates the module interconnections necessary for
half-duplex operation. For full-duplex operation, the transmitter/
receiver interconnections are Similar to the half-duplex case with
the exception that "REC IN" is not connected to T2 or T1. In
full-duplex operations, the transmission and receiver paths are
independent.
10-104
R24
2400 bps Integral Modem
INTERFACE DESCRIPTION
TRANSMITTER ANALOG CONTROLS
STANDARD DIGITAL INTERCHANGE
(CCITT V.24 EIA RS232C MeSul.lntarf!sa
Input
Input
DACOUT
Term
Equivalent) Equivalent
Term
Modu'8lnterface
Output
Description
TI03
BA
T·9
T104
TI05
BB
CA
T-8
TI06
CB
TI09
CF
RI-4
TIll
CH
T-12.
R2-9
Data Signalling Rate Selector
Selects 2400 bps or 1200 bps
Mode
TI13
DA
T-7
External Transmit Clock
(Transmitted Signal Element
Timing)
TI14
DB
T-IO
Transmit Clock (Transmitted
Signal Element Timing)
TI15
DO
R2-6
Receive Clock (Receive Signal
Element Timing)
Output
T-22
TFIL
T-23
TIN
-ldBm
-3dBm
-5dBm
-7dBm
-9dBm
-lldBm
-13dBm
-15dBm
T-31
Input to Low Pass Filter. DAC OUT is
Normally Connected to TFI L Unless
Additional Filtering oran Equalizer is to be
Inserted.
Transmitted Data
R2·5
Received Data
T-6
Request to Send
Ready for Sending
(Clear to Send)
R2-22
Data Channel Received Line
Signal Detector (Carrier Detect)
Description
Output of Digital to Analog Converter
These NineSignals Implement the
T-39
T-38
T-37
T-36
T-35
T-34
T-33
T-32
i~:~~~~~I';.' ~~:J'~~~~v~~ ~t\~~~%O[,j One of
Strapped to TIN to Set the Desired Output
Level.
RECEIVER DIGITAL CONTROLS
Modulelntarface
ANALOG LINE INTERFACES
Module Interface
Term
input
RECIN
RI-12
OutPut
TI
T-I
T2
T·2
Description
Analog Line Signal Input (Receive Filter
Input)
Low ImpedanceTransmitterOutput
Standard Transmitter Output 600 ohms
Impedance
COMMON MODEM DIGITAL CONTROLS
T-16
R2-13
V26A
NSYNC
CLAMP
Inpui
Output
RBCK
RI-I
R2-25
RLSD
THRH
R2W/4W
TH09
R2-24
RI-3
R2-8
R2-18
RI-2 } Control Signals to Geoerate Carrier Detect
R2-23 (TI09) and Implemenl TI09 Threshold Set
TC09
R2-15
Determines Carrier Detect (TI09) Off-to-On
PBS
R2-16
Determines Carrier Detect (TI09) On-to-Off
Response
CP04
R2-17
Clamps Received Data (TI04) to a mark
or space when Carrier Detect (T109) is Off
CP15
R2-19
Optional Clamping of Received Clock (T115)
FSYC
R2-20
Fast Sync Optional Fast Resynchronization
Procedure
Description
Receiver Baud Clock
Select Function
Response
Description
Term
SSGR
Term
SelectsV.26A orV.26B Dibit Encoding
{J2\5
2}
T-17
{
Controls for Scramble Operation
RECEIVER DIGITAL DIAGNOSTICS
R2-14
T-14
R2-11
R2-10
Controls T109 to Force Rapid
Resynchronization of the Receiver
T-13
I mplements Squelch for Carrier Detect
(TI09)
Term
R2-1
R2-2
R2-4
R2-3
R2-7
SYC
RCVDS
DCP
A
PE
Digital Outputs which EnableUserto
Generate Eye Pattern and Phase Error
Information
TRANSMITTER DIGITAL CONTROLS
Term
CAUTO
TONA
¥wodUle Interface
"put
Output
T-3
TBC
Description
T-5
AnswerTone
Indicates Completion of Transmission
of Answer Tone
T-4
Transmitter Baud Clock
Z
T-28
Input Forcing Transmit Clock (TI14) to
Phase and Frequency Lock to External
Transmit Clock (T113)
T2W/4W
T-II
T-24
T-25
T-26
T-27
T-29
T-30
Inputs Affecting Ready lor Sending
X
K
Y
TC06
800MS
E
RECEIVER ANALOG CONTROLS
Initiat~s
Response Times, AnswerTone Frequency
and Carrier Detect (TI09) Squelch
Tarm
RECOUT
RI-7
Receive FilterOuput
EO IN
EO OUT
RI-8
RI-6
RI-5
R2-21
Equalizer Input
Equalizer Output
RLSDIN
AGCIN
AGCOUT
GAIN
GI
G2
RI-II
RI-9
IANALOG
R2-27
10-105
R2-26
.
Carrier Detect Circuitry Input
Automatic Gain Control Circuitry Input
Automatic Gain Control Circuitry Output
R1-10} Optional Carrier Detect (T109) Threshold
Selection Controls
Sample and Hold Circuitry Input
R24
2400 bps Integral Modem
MODEM PERFORI\IIANCE
The R24 is a high performance synchronous 2400 bps DPSK
modem, utilizing a coherent demodulation technique to achieve
reliable operation oVer the switched network or unconditioned
lines. This section contains a quantitative discussion of the R24's
typical performance under varying test conditions.
DISPERSION
DUE TO GAIN
ERRORS
DISPERSION DUE
TO PHASE ERRORS
Timing Jitter - The maximum steady state timing jitter of
"receive clock" with respect to "transmit clock" is less than 10%
pop for an input signal-to-noise ratio of 12 dB.
Bit Error Rate performance:
DISPERSION AROUND
PROPER POSITION DUE
TO CQMBJNA TlON OF
RANDOM NOISE, PHASE
ERROR, AND/OR GAIN
ERROR.
CIRCLE REPRESENTS
PROPER POSITION OF
HIGH QUALITY SIGNAL
The following graph represents typical R24
Typical Eye Pattern: 4 Phase-2400 bps-1200 Baud (V26A)
Phase error and eye pattern can be extremely useful for modem
acceptance testing, product evaluation, and observation of line
signal quality under actual operation.
ELECTRICAL CHARACTERISTICS
POWER REQUIREMENTS
Voltage
Ripple
Maximum
Current
T
+5 Vdc±5%
+12 Vdc±5%
·12 Vdc ±5%
100 mV p.p
50 mV p~p
50 mV p.p
38mA
16mA
48mA
Rl
+12 Vdc ±5%
-12 Vdc±5%
50 mV p.p
50 mV p.p
23 mA
16mA
R2
+5 Vdc±5%
+12 Vdc ±5%
~12 Vdc ±5%
100 mV p.p
50 mV p~p
50 mV p~p
64mA
25mA
78 mA
Module
SIGNAL TO NOISE RATIO
Maximum total power consumption approximately 3 watts.
Typical total power consumption approximately 2 watts.
~DB)
1 1200 BPS, BACK.TO.8ACK, SCRAMBLER. NO EOUAlIZER
2 2400 6PS, V.~A OR B. BACK·TO-BAcK. SCRAMBLER. NO EQUALIZER
3 2400 BPS, V.26A OF! B, 1&0·150 HZ PHASe: JITtER, NO SCRAMeLER, NO EaUALIZER
4 2400 BPS, V.26A OR B, 30°·120 HZ Pl-IASE' JITTER, NO SCRAMBLER, NO EQUALIZER
5 2400 PBS, V.2tlA OR e, 3002 UNCONDITIONED LINE, NO SCRAMBLER, EOUALIZER
DIGITAL INTERFACE
The R24 provides LS TTL or CMOS compatible logic levels that
are functionally equivalent to EIA RS232/449 and CCITT V.24.
Phase Error - Phase error can be measured by using the
modem's output signals PE, SYC, and A. With an external test
circuit, a numerical value can be derived to indicate the quality
of received data. This nUmerical value can be directly correlated
to bit error rate performance. The required test circuit can be
implemented with discrete circuitry or in software within a
microcomputer.
Input
logic
Allowed Input Voltage levels
Low
High
·12.0V to +0.8V Sinking <10 jJ.A
+4.0V to +5.0V Sourcing <10 jJ.A
Digital inputs are directly CMOS compatible. Interfacing with
standard TTL or low-power Schottky TTL requires an external
pull-up resistor.
Output
logic
Eye Pattern - By using the modem:> digital output signals
RCVDC, SYC, and A along with an added test circuit, the user
can generate an oscilloscope quadrature eye pattern. This pattern
displays the received signal as a group of dots in the baseband
signal plane; hence, it is a graphic representation of modem
performance.
Low
High
Allowed Output Voltage Levels
O.OV to + 0.4V Sinking 0.36 mA
+ 4.0V to + 5.0V Sourcing 100"A
Digital outputs are directly CMOS or low-power Schottky TTL
compatible.
10-106
2~OO blls Integral M~dem
R24
TRANSMISSION LINE INTERFACE
c
The R24 provides an analog interface that must generally be
transformer coupled to ensure normal telephone line isolation.
Through appropriate selection of transformers and other interface circuitry, the R24 can be configured to operate on leased
or dial-up telephone lines, or on other special private networks.
For the dial-up interface, Rockwell offers an FCC registered
module that allows direct connection to this network. For the
leased line interface, only transformers with characteristics
similar to those utilized on the R24 modem eVi;l.luation board are
required for this connection.
-'2V/181
(17) SeGR
+12V(19)
(l6)V26A
(18)1 .
.325
(8.26)
.. COM (201
(14) NSYNC
"5V (21)
(13) CLAMP
!;JAC
(12)T111
(lHT2W/4W
~Mr!~~l
X (24)
(10jT114
K f2f!1
( 9}Tl03
I 8) n05
. TCDS (27)
Y (26)
. Z ,Z8j
BOOMS/291
( 7.)T113
( 6)
nos
E (3D)
TIN (31)
(, SITONA
L_
,-
( 4)TBC
( 31CAUTO
-lSdBm (32)
-,\T1
.100
(2.54)
TYP.
-13dBm (33)
-11dSm(34)
-9dBm (361
·7dBm (36)
.~-5dBm (37)
-3dBm (38)
I 2}T2
·1dBm'la91
The receiver and transmitter' line intertaqes are single-ended
(non-transformer cOllpled)signalsc;with the following
characteristics:
.
fI
(8.26)
i
\025 (.64) SQ. PIN
39 PLACES
Transmitter Module Package
Transmitter Output (Normal)
--'-
-r-I~----------'-~---------'~ .325
Output Impedance: 600 ohms ± 2%
Maximum outP.ot level: $0.0. dBm
I
1.025
(26.04)
I
Transmitter Output (Alternate) Low Impedance:
.~2~)
G2( 9)
GAIN (10)
.. G1 (11)
REC IN (12)
~
(8)EQIN
(7)REC OUT
t61 EQOUT
(5) RLSO IN
Output Impedance: 0 ohms (op amp output)
.
Maximum output level $ +6.0 dB
L_
1.900
!~:+~~
I
~ \m~~~
Note: This output for transformer loss compensation.
.100
(2.54)
,
TYP.
"
·J2V(13)
+-12V(14)
COM (15)
Receiver Input:
Input Impedance: 15.8K ohms ±1%
Maximum Input Level: 0.0 dBm
. \025 (.64) SQ. PIN
15 PLACES
Recelver-"- A1 Module Package
MECHANICAL SPECIFICATIONS
11
.soo
Af~~ iIi!
120.32)
L_
I
.300 MAX.
.
(COLE.TS)!: _ _ _ -
o!i;
~I
.062
-
. .
1-----
"I
2.400
I
-I
2.75 ± .03
.344 ± .005
---l!-
(20) FSYC
(19) CP15
j 181 TH09
(17jCP04
116) PBS
(15) TC09
1
AGC OUT (26)
IANALOG (27)
,
.325
(8.26)
'1·
(14) SaGR
(13) V26A
2.500
~II~=-r
P.080
10
0
± -.007
MAX.
(LEAO PROTECTION)
t"\")sYC
'5V (28)
COM (29)
. 12v(30)
·12V (31)
.100
(2,64)
TYP.
\025 (.64) SO. PIN
31 PLACES
Receiver -
R2 Module Package
NOTES: 1) Dimensions in inches (millimeters).
2) Component side shown
NOTE: This cross-section is common to all modules.
10-107
2400 bps Integral Modem
R24
R24 MODEM EVALUATION BOARD
PRINTED CIRCUIT BOARD MOUNTING
OPTIONS FOR THE R24 MODULES
To facilitate evaluation and design-in of the R24 modem·for new
and existing equipment designs, an 1'124 Modem Evaluation
Board (R24MEB) is available. The R24MEB can be easily combined with terminal systems for real-time performance
evaluation.
Three methods of mounting are commonly used. Each configuration has certain distinct advantages.
Mounting
Method
Type of Connection
or Connector Used
Standard Flush
PCB Component
Mount
Wave Soldered Into Standard
PCB Eyelets
Above Board
Low Profile'
Socket
Connectors (SAE Series
PCB Plug-in'
Sockets (Bullets)
3000 or Methode Series 1000)
These Sockets are Wave
Soldered Into Standard
PCB Eyelets
Connectors '(AMP Miniature
Spring Sockets.)
Pin Sockets are Individually
Soldered Ihto PCB Eyelets
Basic
Advantage
RECEIVER
Lowest Height
Profile
Plug-in Capabilityat Low
Cost
Lowest Profile for Plug-in
Capability
ENVIRONMENTAL SPECIFICATIONS:
Operating temperature: O°C to 60°C
Storage temperature: -40°C to + 80°C
Relative humidity: to 95% (non-condensing)
Altitude: -200 to 10,000 feet (-6.1 meters to:3,049 meters)
Burn-In: 96 hours at 70°C
The Modem Evaluation Board is equipped with a standard 31
pin edge connector, control switches, output level jumper, and
interface transformers. These features allow full control of the
interface circuitry. In addition, this unit can be used directly in
a U.S. leased line configuration. The R24MEB is recommended
for all first-time users to assist in their evaluation. Complete
documentation is supplied with each initial R24MEB.
Ordering Information
When ordering, specify products as follows:
R24 - Set of 3 modules (T, R1, R2)
R24MEB - Modem Evaluation Board
10-108
Integral Modems
R24MEB
MODEM EVALUATION BOARD
. INTRODUCTION
FEATURES
To aid the llser In the design phase of leased line modems,
Rockwell has made available ·the R24 Modem Evaluation Board
(MEB). The R24MEB is a convenient cost effective means for
evaluation and design-in of the R24 2400 bps Integral Modem.
• Convenient evaluation method of R24 Integral Modem
modules
• Exercises all R?4 Integral Modem features
• Easily integrated into a prorotype system
• Cost effective for low-volume applications
• Will serve as. incoming test vehicle
• Standard board edge connector
• Pin receptacles for easy mountingfinterfacing R24 modules
(R, R2, T)
• Complete option select switches
• Transmitter output level strap selectable
• Backed by complete customer support documentation package
The Modem Evaluation Board is equipped with pin receptacles
for mounting and interfacing the three R24 receiver and transmitter modules (R1, R2 and T). In addition to all interconnections
being etched on the back of the board, the R24MEB also provides telephone coupling transformers, transient protection circuits, DIP switches (for option selection and gain control) and
a DIP socket for jumper selection of the transmitter output level. .
A 31-pin edge connector (with Industry standard 0.125 inch contact centers) provides pin-infpin-out, as well as power connections
for analog and digital interface signals.
These features allow full control of the modem interface circuitry.
Also, the complete R24 modem can be used directly in a U.S.
leased line configuration. "The R24MEB is recommended for all
first-time users to assist in their evaluation. Complete documentation is supplied with each initial R24MEB.
R24MEB Modem
Document No. 29220N14
Evaluati~n
10-109
Board
Product Summary No. 614
Rev. 1, August 1983
R24MEB
Modem Evaluation Board
TRANSMIT
LEVEL
CONTROL
NETWORK
R2
IMpEDANCE
COUPLING
RESISTOR
INPUTIOUTPUT CONNECTOR (PI)
INPUT
POWER
ANALOG
RECEIVER
INPUT
~
DIGITAL
INTERFACE
ANALOG
TRANSililiTTER
OUTPUT
R24MEB Functional Diagram
ORDERING INFORMATION
BOARD DIMENSIONS
When ordering, specify products as follows:
Width: 5.875 in. (14.923 em)
Depth: 6.813 in. (17.305 cm)
R24MEB - Modem Evaluation Board
R24 - Set of 3 modules (T, Rl, R2)
10-110
RDAA
Integral Modems
RDAA
ROCK\rVELL DATA ACCESS
ARRANGEMENT MODULE
PRELIMINARY
SECTION 1 -
INTRODUCTION
FEATURES
This document is an aide to customers installing, operating and
troubleshooting the Rockwell Data Access Arrangement (RDAA)
Module designed and manufactured by Rockwell International.
• Pre-registered (under FCC Rules, Part 68) for direct connection to dial telephone network
• Integral Data Access Arrangement (DAA)
• Automatic dialing-pulse or tone
• Establishes data transmission path
• Automatic answering function
• Surge and hazardous voltage protection
• Switch hook status indication
THE RDAA MODULE
The RDAA Module enables the modem user to make direct connections of their modems to the domestic switched telephone
network. The RDAA is completely registered with the Federal
Communications Commission under Rules Part 68. Therefore,
no user re-registration of OEM data communication equipment
is necessary when used with the RDAA. This means a definite
cost-savings for the OEM equipment designer.
• Ringing indication
• Automatic line signal output limiting
• Programmable or Permissive (strap selectable) connection
arrangements
• Small size (approximately 3.95" by 3.94") (100 mm. by
100 mm.)
In addition to establishing your desired data transmission path,
the RDAA also features an automatic answering function, line
surge and hazardous voltage protection, switch hook status
indication, ringing indication and automatic signal level control.
Automatic dialing can be performed by pulsing the OH relay or
by transmitting tone pairs.
RDAA Module
Document No. 29220N49
10-111
Product Description Order No. 649
August 1983
RDAA
Rockwell Data Access Arrangement Module
----------------------------------------------
When the Permissive connection arrangement is employed, the
maximum signal output level across T and R is fixed at -9 dBm.
The Permissive jacks (RJ11 C) used for ·Iine connections are the
same jacks used for standard voice installations. Therefore, this
arrangement provides for greater mobility of user equipment.
The RDAA is easily incorporated into the users end product by
either using the provided mounting holes, andlor using the cardguides without card-edge connector. The small size of the RDAA
makes it ideal for piggyback type mounting.
The Rockwell RDAA printed circuit board is 3.94 inches (100
mm.) in width and 3.94 inches (100 mm.) in depth.
RDAA DIMENSIONS
SELECTABLE CONFIGURATIONS
The dimensions for the RDAA Module are given in Figure 2.
As a prerequisite, telephone companies require that the signal
level received at their local central office not exceed-12 dBm.
Several different connection arrangements have been established (as documented in the FCC Rules, Part 68) to meet this
requirement.
MATING CONNECTORS
The mating connectors of the RDAA are as follows:
1. Two row (14 pins) ribbon type connectors .1" spacing between
pins.
By jumper selection (Figure 1) the RDAA can be configured to
operate in either the Programmable (PG) or Permissive (PM)
connection arrangement. This is accomplished by placing the
jumper in either the W2 or Wl locations for the desired mode.
Wl jumper in, W2 jumper out for the permissive mode. W2
jumper in, Wl jumper out for the programmable mode.
'OJ: . .
3.94
3.94~
3.70-~~--11
rr: i~'~'- .~---l
3.275
I
I
I
I
3.94 3.275
I
1
II"~~~~,,
000000[J
e ____~·~O~o~o~o~o~o~o~__________~~~
Figure 1.
I
~ _~~
RDAA Module Jumper Selection Location
Figure 2.
When using the Programmable connection arrangement, the
maximum signal level allowed to be transmitted across T and
R is set by a resistor installed by the telephone company in their
wall jack (RJ45S or RJ41 S) at the customer location. The resistor
interacts with the RDAA throug h the leads PR and PC to program the maximum output level in one dB steps between -12
dBm and 0 dBm. Sel.ection of the resistor from thirteen possible
values is based on loop loss measurements performed by the
telephone jack installer. The Programmable' arrangement provides for the transmission of the maximum allowable amount of
power. Therefore, this arrangement offers optimum performance over long loops.
10-112
Iggggggg I
RDAA Module Dimensions
RDAA
Rockwell Data Access Arrangement Module
SECTION 2 -
INTERFACE DESCRIPTION
INTERFACE CIRCUIT DESCRIPTION
The following paragraphs describe in detail the ROM interface
circuits shown in the block diagram (Figure 3) and the interface
circuits listing (Table 2-1).
PR>------------------------------------------------------,
PC>-------~----------------------------------------_,
TXA
t-+----....;....-------+- RXA
t-------------------------~----_+------------~r_---
L-==::.J---------------
-12V)--
CCTI
+5V}---
MI>---------~~_1:>-----~------------------------------------+
SH
MIC )>----------""'..."'......-,...
Figure 3.
RDAA Functional Block Diagram
Table 2·1.
RDAA Interface Circuits
Signal Direction To:
Lead Designation
User
RDAA
Both
R, T
MI, MIC
PR, PC
+5V, +12V, -12V
RDI
Transmission leads for data signals.
Leads to telephone set switch hook.
Leads to.programming resistor.
X
Signal ground required.
Ringing signlj.l present indication.
To request data transmiSsion palh cut through.
To control Off-Hook relay.
Status of telephone set switch hook.
Transmission palh cut through indication.
Lead to modem putput.
Lead to modem input.
DC power required.
X
SG
RCCT
OH
SH
CCTI
TXA
RXA
Function
X
X
X
X
X
X
X
X
X
X
10-113
RDAA
RockWell Data Access Arrangement Module
SG
NOTE
WARNING. If OH is asserted to a logic high before the
incoming call ring signal is completed, the OH reed relay
switch contacts may suffer degradation.
The SG (Signal Ground) is the common reference for all modem
interface signals.
RDI
RDI (Ring Detect) indicates to the user by an ON (Low) condition that a ringing signal is present. The RDI signal will not
respond to momentary bursts of ringing less than 125 ms in duration, or to less than 40V rms, 15 to 68 H;Z appearing across Tip
and Ring with respect to ground. RDI is also used to disable
the transmission path. The electrical characteristics of the RDI
signal are shown in Table 2-2.
SH
An ON (High) signal on the SH lead indicaies to the user that
the associated telephone (if used) is in the talk mode i.e., a contact closure exists between MI and MIC. The characteristics of
the SH signal are shown in Table 2-2.
CCTI
Table 2-2. Output Signals RDI
SH and CCT/ Characteristics
Output
Logic State
LOW
HIGH
CCTI is the Coupler Cut Through. An ON (Low) signal to the
CCT/iead indicates to the user that the data transmission path
through the RDAA is connected. The ON (Low) state does not
indicate the status of the telephone line or connection. The
characteristics of the CCTI signal are shown in Table 2-2.
Output Levels
0.0 to 0.4V while sinking < 1.6 rna
2,4 to 5.0V while sourcing < 40 p.A
TXA
TXA (fransmit Arialog) is t~e lead from modem transmitter output. This lead should be tied to GND when the modem is in the
receive only mode.
RCCT,'
RCCT (Request Coupler Cut-Through) is used to request that
a data transmission path through the RDAA be;, connected to
the telephone line. When RCCT goes OFi= (Low), the cut-through
buffers are disabled and CeT will go OFF (High) within 1 millisecond. RCCT must be OFF (Low) during dial pulSing but ON (High)
for tone address signaling. The electrical characteristics of the
RCCT signal are shown in Table 2-3.
RXA
RXA (Receive Analog) is the lead to modem receiver input. This
lead may be left open when the modem is in the transmit-only
mode.
POWER REQUIREMENTS
The following power must be provided at the RDAA interface.
Table 2-3. Input Signals RCCT and OH Characteristics
Input
Logic State
OFF or LOW
ON or HIGH
A. + 12 VDC ± 5% @ 15 rna with a maximum ripple of 50 mv
Input Levels
peak-to-peak
0.0 to O.BV, load current'" 0.36 rna
RCCT = 2.0 to 5.0V, load current '" 20 p'a
OH = 2.0V, load current'" 100 p'a
5.0V, load current'" 250 p.a
B. +5 VDC ±5% @ 20 rna with a maximum ripple of 100 mv
peak-to-peak
C. -12 VDC ± 5% @'15 rna with a maximum ripple of 50 mv
peak-to-peak.
OH
OH controls the OFF-HOOK relay. Applying an ON (High) signal
to OH closes the OH relay and establishes a DC path between
T and R. Maximum delay between the ON signal to OH and the
close of the OH relay is 10 ms. When originating a call, an ON
(High) signal is used to request dial tone. After detecting dial
tone, OH can be pulsed to generate the dial pulses corresponding to the number of the called station (see Section 4.2).
On incoming calls, anON (High) signal to the OH lead initiates
the answering sequence (see Section 4.1). The characteristics
of the OH signal is shown in Table 2-3.
HAZARDOUS VOLTAGE PROTECTION
Lightning induced surge voltages and other hazardous voltages
are limited to 10.0 volts peak between the secondary leads of
the coupling transformer T1. The isolation between the relay
contacts and coils provides the protection of the telephone line
from hazardous voltages appearing on any control lead.
10-114
RockW~1I Data Ac~ess Arrangel1lent Module
RDAA'i
RING DETECTOR AND TIMER
The output control cirCljitry cOl)tains a variable gain buffer which
reduces the RDAA output 'to the maximum allowed level across
T and R. When theRDAA isjumperedto operate in the Programmable mode, the resistor in the telephone company wall
jac\< sets the output level to one of thirte!'ln possible values. If
the RDAA is jumpered to operl!le in the, Permissive mode', tl)en
an internal resistor will set the output to a fixed value. The rela~
tionship between the RDAA input amplitud",' (in dBm) across
TXA and GND and the nom,inal ROM output level across T and
'
R is given below:
When the Ring D",tector detects the presence of a ringing signal
ranging from 15.3 to 68 Hz with voltage levels of,4O to 150 VRMS
across, Tip and Ring (T and R) leads, after a delay 01,,125 ms
10500 ms, it will send an RDI (Ring Detect) signal to the user's
data terminal equipment. (DTE). If the DTE is conditioned for
answering, the DTE; will return an ON signal on OH and, RCCT.
The OH signal closes the OH relay and.starts a timer. Thetimer
is used to provl'de a quiet interval of more than two seconds
between the closing of OH relay'and the connection of data
transmission path. This allows the telephone company to prop-:
erly engage their billing equipment. After this delay the CCTI
interface lead goes ON (Low) and data transmission maybegin.
A. For Programmable mode: output level across T and R '"
(input amplitude at TXA - 7 dB + (Programmed level set by
wall jack resistor).
RDI will go OFF (High) in less than 400 MSEC after the ringing
signal is stopped. The ring detector is disabled when OH is ON
(High) or SH is ON (High).
B. For Permissive mode: output level across T and R '" (input
, amplitude at TXA) - 16 dB.
SIGNAL LEVEL LIMITER AND GAIN
CONTROL CIRCUITRY
IMPEDANCE SPECIFICATIONS
On-Hook DC:
The DC resistance between T ,and H,
and between either T or R and signal
ground are greater than 10 megohms
for DC voltages up to 100 volts.
On-HookAC:
The on-hook AC impedance
measured between T and R is less
than 40K ohms (15.3 Hz minimum).
NOTE
Off-Hook DC:
Less than 100 ohms.
The off-hook relay is not affected by the IimHing function,
therefore, so triggering the limiting function need not resuR
in call termination.
Off-Hook AC:
600 ohms nominal when measured
between T and R.
TXA and GND:
2 ~gohmS typical (operational
amplifier voltage follower input .'
impedance).
RXA and GND:
75 ohms typical (operatIOnal amplifier
voltage follower oUtput impedance).
The limiter monitors the signal level applied to the RDAA input
lead TXA and is unaffected by the level of receive signal. When
the applied sigl)al amplitude becomes greater than + 7 dBm for
a period of 1.:310 3 seconds;'the transmission path is disconnected via the transmit and receive buffers, and the output signal
CCTI will go OFF (High).
RedUCing the input signal amplitude to less than + 7 dBm will
reset the ,1i.mHer in tess than 4 rnilliseconds, restore the c;lata'
, transmission path, and cause the signalCCT to go ON (tow,:
In order not to activate ihe limiter during normal operation; care
must be taken to ensure that the maximum signal amplitude into
the RDAA input TXA never exceeds + 6 dBm. If the modem
:output has a tolerance of ± 1 dB, then it is recommended to set
the modemoutpLit to +5 dBm (± 1 dB), so that the maximum
'
signal amplitude Into TXA is 6 dBm.
IN,SERTION LOSS
There is no insertion 'loss for the RDAA, The' RQAJ1.<;ontains a
receive buffer which compensates for transformer insertion loss.
For this reason, additional receive !:lolfering is not necessary.
10-115
RDAA
Rockwell Data.Access Arrangement Module
;.
SECTIO~
3."""" INSTALLATION/CHECKOUT
TELEPHONE SET AND JACK'
ORDERING,INFORMATION
.
RDAA CON,NECTION TO TELEPHONE LINE
, .
.
If it is desirable to have manual call origination. or alternate voice
capability, an exclusion key telephone set rTJay be ordered from
a loealtelephone company. The telephone line may be transferred to the telephone set by lifting both the·.handset and the
excluSion .key, if. the telephone is configured as Data Set Control$. Line. This operation is for manual origination or alternate
voice transfer (refer to paragfaph 4.4 for· manual origination procedure). A call may be terminated by replacing the handset in
its cradle and taking OH low if OH is not already low.
Connection of the telephone line interface pins of the RDAA to
theneiwork shall be made via ..standard jacks and plugs as
shown in Figure 4: Cable color codes are also shown in Rgure
4. 'A number ofteil'lphoneline 66rdl'l1ariufactuiers produce the
standard plugs and cables (Meyer Wire Co., Hamden, CT; Virginia Plastics, Roanoke, VA, etc.)
,
-
~
.,;'
l ' '.
BtACK
.' r- ,.
~J4~ \
JACK
;.•
---~..,
MI .' R
T
'T
MIC
.
~
MI
A
YELLOW
-1'
:t~F~~"LT~T.iT~T~T-!TJ
r-
AEO
GREEN
- --
I ~ 2 3 4 _6 ,
I·JA.bK.; "~1IX
L _____
_
" 'J'
'.
r""" -
,
~
PLUG
""'.
PC
PlDAAPFIOGRAII .. ABI..E
MOllE
5
""'='"
·S'rANQARD
8-POSITION
STANDARD
4
\
.'T1
"MININTU'RE [-1I
C",,"l.E
BLACK
A1
SHOWN ON
'IGURE 3·2.
....
PA
'-sTA'NdAAo
,PlUQ
Mit
SUCH AS
RJ16X
MIC
SILVER
-~
MI
GREE~
YELLOW
usoc
m_' {
A '
., ."owN·
.'~.,
"
MI
AED
R'
"
TO RDAA
.DA.
MIC
TO MINIATURE 6 POSITION JACK
~
1
2
3
4
'Ii ._
STANDARD
CABLE
ROM
1'1'
~RMI'IIYI
""""
I
'r"
l'
1
1
ADAPTER
. RJA2X
1
1
FlJ4;S IS Pt UNIVERSAL JACK WHICH
1
CAN BE UTILIZED WITH EITHER
THE'PROGRAMMABLE MODE OR
f"IXED-LOSS LOOP IFLLI MODE
2
3
•
J{
Figure 4.
2
3
.
I
., 1~
r-----,
6 POSITION
MINIATURE PLUG
MINIATURE PLUG
Standard Jacks, Plugs and Cable Color Codes
10-116
1
r----:l
l.JJJJJ.:TJ
RJ41S
JACK
I
lTl!ttT~TJ
'POSITION
Rockwc!1I Data Access A~rangement Module
RDAA
,The ringer of the telephone set may be disconnected by the
telephone company to prevent the bell from ringing.
When ordering this telephone, specify the USOC number RTC
and the following options:
The telephone company provides an exclusion key telephone
under the Universal Service Order Code (USOC) RTC. This telephone set has the following customer options:
A. A2 - Data set controls line
B. B3 - A,ural monitoring not provided
or
B4 - Aural monitoring provided
A. A1 - Telephone set controls line
C. B3 - Aural monitoring not provided
C. C5 - Touch tone dial telephone (503C)
or
C6 - Rotary dial telephone (2503C)
D. B4 - Aural monitoring provided (See. Note 1)
D. DB - Voice mode indication only
B. A2 - Data set controls line
E. C5 - Touch tone dial
Another telephone set provided by the telephone company is
the Model 502 with exclusion key. To order this telephone set,
specify the following:
F. C6 - Rotary dial
G. 07 - Switch hook indication
H. DB - Voice mode indication only (See Note 2)
A. Modem 502 with exclusion key
B. Data set controls line
NOTES
A summary of the information for ordering telephone and jacks
is given in Table 3-1. Examples of typical installation are given
in Figure 3-2.
1. The aural monitoring feature allows the telephone
handset to be used for listening to line signalswithout
interfering with data transmission.
.
2. In this option the make contact of the exclusion key and
a make contact on the switchhook are connected in
series and to the mode indication leads MI and MIC of
the data jack. Therefore, the SH signal of the ROM
goes ON only when the exclusion key Is. lifted.
Table 3-1.
Output
Configuration
Optional
Telephone Sat
Programmable
With
Telephone Set
Without
Telephone Set
Permissive
With
Telephone Set
Without
TeleptiorieSet
I
Telephones and Jacks Ord~rlng Information
FCC
Reg. No.
Ringer
Equivalent '
AMQ9SQ
67943
DP-E
AMQ9SQ
67943
DP-E
AMQ9SQ
67943
DP-E
AMQ9SQ
67943
DP-E
.8B
'RJ36X and
2.3RJ45S
.8B
2.3RJ45S
.8B
'RJ36X and RJ16X
'or
4RJA2X and RJ11C
RJ11C
.8B
Telephone Jack
USOCNo.
Telephone Set
USOCNo.
RTC or 502
with excl.usion key
N.A.
RTC or 502
with eXclusion key
N.A, ~
Notes:
1. ,RJ36X iSJ;IF] 8 position miniature jack,into which,the telephone plugs. Rathe( t~!Ion using an RJ36X jack, the tEllephone company may use a
' connecting block to connect the telephone set and data jack to the telephone line.
"
'
,
'2. RJ41 S is a uniVersal data jack. It may be used for either Programmable or Fixed-Loss Loop mode. The 'RJ45S jack is preferred, because it
costs l e s s . '
3. For multiple connections, the RJ45M jack should be ordered. The letter M indicates multiple single line jack for up to 8 lines. Specify the number
Of lines required when ordering.
4., RJA2X is the adapter shown in Figure 3-1. The use of the RJ36X and RJ16X jacks is recommended.
•
10-117
iII
"',
RDAA
Rockwell Data Access Arrangement Module
TOOTE
OH RCCT RD! SH CCT!
TX
OUTPUT
R
R
T
T
,..---..,.1--1
TOOTE
MODEM
RDAA
MIC'
MI
RXA
MIC
RX
INPUT
STANDARD
MINIATURE
PLUG
~RO
1
2
EX
I
•5
J
J
3
7
8
}TONETWOR K
JJ
J"~
I
a
:
NETWORK
,
Sit
'~EX
EX
+
1,
''- BRIDGING
TRANSFORMER
RTe"
"
OPTIONED FOR OATA SET
CONTROL OF THE LINE
'NOTES:
1.
2.
3.
••
MI AND MIC ARE REQUIRED ONLY IF HANDSET IS USED.
PR AND PC ARE REQUIRED FOR PROGRAMMABLE MODE ONLY.
STANDARD TELEPHONE CO. PROVIDED JACK RJ1ax, RJ45S OR RJ.1S.
RJ36X OR CONNECTING BLOCK REQUIRED ONLY IFTELEPH9NE HANDSET IS USED. WHEN THE RDAA
IS IN THE PERMISSIVE MODE, THE RJA2X ADAPTER AND RJ11C OF FIGURE 4 MAY BE USED WITH THE
ASSOCIATED TELEPHONE SET.
FigureS.
IS
Transmit and Receive (Half Duplex) and (Full Duplex)
MOD,EM INTERFACE
There are 4 possible two-wire" modes of operation configurations: receive-only, transmit-only, and receive and transmit (half
duplex) and full-duplex (using two different frequencies simultaneously) as described below: .
"
C. For the transmit-only configuration,the RDAA lead RXA is
left open rather than connected to the modem receiver as
shown in Figure 5.
A. For the half-duplex and full~duplexconfigurations, the interface connection circuitry could be as shown in Figure 5.
For a A-wire full-dup/exconfiguration, 2 RDAAmodules .arid 2
.telephone lines are" required. The connection circuitry cons,ists
of one 2-wire receive"only conneCtion, and one 2-wire transmit~
only connection.
"
B. For the receive-only configuration, ,the connection circuitry is
the same as that shown in Figure 5, exCept that the RDAA
input lead TXA is grounded rather than connected to the
modem transmitter output.
"
10-118
RDAA
Rockwell Data Access Arrangement Module
MODULE MOUNTING AND SECURING
Care must be taken in routing the telephone interface pins to
the telephone jack. The FCC (Rules, Part 68) requires that the
telephone interface leads shall'be separated from the leads or
metallic paths connecting to power connections.
The RDM may be physically incorporated into the OEM's end
product by using the four corner (0.156 inch diameter) mounting
holes and self-locking plastic standoffs, or by bolting the RDM
module to a rigid structure. The RDM module may also be
mounted using card guides without card edge connector.
NOTE
Power connections are those connections between commercial power and any transformer, power supply rectifier,
converter, or other circuitry associated with the RDM,
The connection of the interface pins (including the ± 12V
and +5V) shown in Figure 2 are not power connections.
A number of manufacturers such as Richlock Corporation, Chicago, IL., produce plastic standoffs (Part Number CBS-3N).
ELECTRICAL INTERFACE
Electrical connection to the RDM module is made through
ribbon type connectors. The connector(s) interface pins (Figure
2) are contained on the component side of the board. There are
two test points brought out to the interface connector of the
board. Therefore care must be taken to prevent shorting test
points with any of the other interface signals.
The telephone interface leads shall not be routed in the same
cable (or use the same connector) as leads or metallic paths
connecting to commercial power.
FCC (Rules, Part 68) also requires that the telephone leads T
and R be separated from metallic paths to leads connecting to
non-registered equipment, when specification details provided
to FCC do not show that the interface voltages are less than
non-hazardous voltage source limits in Part 68. T and R shall
not be routed in the same cable (or use adjacent pins on the
same connector) as metallic paths to leads which are not considered non-hazardous. All DTE interface connector signals
shown in Table 3-2 have been established as non-hazardous.
The RDAA telephone line interface connector pins are physically
separated from the RDAA DTE interface connector pins, as
shown in Figure 2 and described in Table 3-2.
Therefore, in routing the telephone interface leads from the
RDM PI connector to the telephone jack, the following precautions must be strictly adhered to. The telephone jack interface routing path should be as direct as possible. Any cable
used in establishing this path should contain no signal leads
other than possibly the (previously established as non-hazardous) DTE interface signals shown in Table 3-2. Any connector used in establishing this path should contain no
commercial power source signal leads, and adjacent pins to the
T and R (np and Ring) pins in any such connector should not
be utilized by any signals other than possibly those shown in
Table 3-2. Also the DTE interface routing path should be made
as short as possible.
Table 3-2. RDAA Telephone and
Modem Interface
Type
Interface
Circuli
DTE
Interface
Connections
RDAA
Connectors/
Pin No.
Interface
Circuli/Signal
P2-1
P2-2
P2-3
P2-4
P2-5
P2-6
P2-7
P2-8
P2-9
P2-10
CCTI
P2-11
P2-12
P2-13
P2-14
Telephone
Line
Interface
Connections
PI-4
PI-3
PH
PI-2
Pl-(5-8) & (11-12)
PI-9,10
PH3,14
RXA
TXA
OH
RCCT
RDI
-12V
SH
GND
TP2 EXCESSIVE
POWER DETECT
+12V
+5V
N/U
TPI BILLING
DELAY TIME
INSTALLATION PROCEDURE
A. Check the telephone line interface cable(s) plug(s) and jack(s)
(Figure 4). If the USOC RJ41 S jack is used for the Programmable mode, ensure that the jumper W2 is installed and WI
jumper is removed for the programmable mode of operation.
B. Make sure the telephone company installer has measured
the loop loss correctly and has selected the proper programming resistor in the RJ45S or RJ41S jack.
PC
PR
MIC
MI
(Not Used)
R
T
NOTE
You have the right to know the method used by the
installer for measuring loop loss and selecting the programming resistor.
10,-119
RDAA
Rockwell Data Access Arrangement Module
C. Check the. power supplies to see if they meet the proper
requirements specified in paragraph 2.2.
A. All direct connections to the telephone lines shall be made
through standard plugs and jacks as specified in Figure 4
and Table 3-1.
D. Insert the telephone cable plug into the jack, and make the
DTE interface connection. Then switch on the power suppliE.:s.
B. It is prohibited to connect the RDAA to pay telephones or
party lines.
OPERATIONAL CHECKOUT PROCEDURE
C. You are required to notify the local telephone company of
the connection or disconnection of the RDAA, the make, the
modem number, the FCC registration number, the ringer
equivalence number (refer to Table 3-1) and the particular
line to which the connection is made. If the proper jacks are
not available, you must order the type of jacks to be used
from the telephone company. (Refer to Table 3-1 for the
proper jacks and telephones,)
The following procedures check out the RDAA in association
with a modem, a data terminal, a telephone set and an automatic dialer. The telephone set is required only in the manual
origination mode (refer to paragraph 4.4) or if alternate voiGe
communication is desired. The automatic dialer is required only
in the automatiC dial mode (refer to paragraph 4.3).
D. You should disconnect the RDAA from the telephone line if
it appears to be malfunctioning. If the RDAA needs repair,
return it to Rockwell International. This applies to equipment
both in and out of warranty. Do not attempt to repair the unit
as this will violate the FCC rules.
AUTOMATIC ANSWER MODE
A. Set the modem transmitted output level to +5 dBm.
B. Call the local modem from a remote station.
C. Follow the instructions given in Figure 6.
E. The RDM contains protective circuitry to prevent harmful
voltages being transmitted to the telephone network. If however, such harmful voltages do occur, then the telephone
company has the right to temporarily discontinue your service. In this case, the telephone company shall:
D. Transmit data from the local terminal to the remote terminal
and monitor the CCT I signal. It should stay low.
E. Terminate the call sequence and verify the received data.
AUTOMATIC ORIGINATE MODE
1. Promptly notify you of the discontinuance.
A Set the modem transmitted output level to +5 dBm.
2. Afford you the opportunity to correct the situation that
caused the discontinuance.
B. Follow the procedure of Figure 8 for touch tone origination
or Figure 7 for pulse dial origination.
3. Inform you of your right to bring a complaint to the FCC
concerning the discontinuance.
C. Transmit data from the local terminal and monitor the CCTI
signal. It should stay low.
F. The telephone company also has the right to make changes
in their facilities and services which may affect the operation
of your equipment. However, you shall be given notice in
writing by the telephone company adequate to allow you to
maintain uninterrupted service.
D. Terminate the call sequence and verify the received data.
MANUAL OPERATION MODE
A Set the modem transmitted output level to +5 dBm.
G. Labeling Requirements:
B. Follow the instructions given in paragraph 4.4.
C. Transmit data from the local terminal. CCT should stay low.
1. The FCC requires that the following label be prominently
displayed on an outside surface of the OEM's end product:
D. Terminate the call sequence and verify the received data.
Unit contains Registered Protective Circuitry
which complies with Part 68 FCC Rules
SPECIAL INSTRUCTIONS TO USER
FCC Registration Number:
Your Rockwell Data Access Arrangement has been registered
with the Federal Communications Commission (FCC). To comply
with the FCC regulations you are requested to observe the
following:
Ringer Equivalence: .8B
2. The size of the label shou Id be such that all the required
information is legible without magnification.
10-120
RDAA
Rockwell Data Access Arrangement Module
SECTION 4 -
OPERATING INSTRUCTIONS
--
AUTOMATIC ANSWER
Thecoimection of the data transmission path for automatic
a.,swer is as described in paragraph 2.4.. To disconnect the datE!
transmission path, just turn off OH and/or DA, as shown in
Figure 6.
I
+
ROlON
I
.,'
ceT/· ON
I
.
I
RCCT·OFflI
DETECT DIAL TONE 1
IDLE
r--
r--
I
I
CCT/· OFF3
'DH " RCCT • ON
I
2-SECOND MINIMUM DELAY'
I
R
ceT/· ON
D·
I
A!II$WER TONE
A
I
I
R
OH PULSE$ FOR NO.
0
I
RCCT .ON·
T
I
E
A
0
I
E
!!ETECT ANI!WER TO!!!§4
I
I
OATA TRANSMISSION
I
OM II· RCCT ·.-OFF
'OH" RCCT· OFF
I
CCT/· OFF
----
t
I
CCT/· OFF
~
-
IDLE
-DA MAY BE ON
P~R"~ANENTLY
0
CCT/. ON3
A
T
DATA TRANSMISSION
A
......--
OH" RCCT· ON
,
-----
+
IDLE
NOTES:
1. DIAL TONE DETECTION IS NOT PROVIDED WITMINTHE RDAA.
ALTERNATIVELY, DTE MAY START FROU..IDLE, TURN ON OH,
THEN TIME FOR 3 SECONDS TO ENSURE DIAL TONE PRESENT
AND PULSE OM FOR NUMBER.
2. DA MUST BE OFF DURING DIAL PULSI.NG. DA MAY BE ON AT
ALL OTHER TIMES.
3. THE DA TO CCT RESPONSE nME IS· LESS THAN 1 MS.
4. ANSWER TONE DETECTION CIRCUITRY IS NOT PROVIDED
WITHIN THE RDAA.
FOR AUTOMATIC ANSWER.
Figure 6. Automatic Answering Sequence
AUTOMATIC DIAL
Figure 7.
DIAL PULSE ORIGINATION
The DTE must provide the logic to turn ON the OH and DA
leads, detect dial ione (or time for 3 seconds to ensure dial tone
pre!!!!nt), then turn OFF the DA lead and generate the dial
pulses corresponding to the called number (Figur~·7). The
2·second delay period between OH and DA going ON and the
response of CCT going ON will not be invoked in the origination
mode. The DTE should monitor for call progress indication (dial
tone, busy tone, answer tone, and call i~terCept).
Dial Pulse Origination Sequenc~
face with Voiceband Ancillary and Data Equipment"
(PUB 47001).
The following is an example for pulse dialing the digit #2 through
.the OH lead.
Requirements for proper call establishment exist on the p\:llse
repetition rate (8 to 11 pulses per second), oft. duty cycle
(Ell! percen! nominal),. Interdigital delay1iming. (600 rns to
2 seconds) and chatter and spurious rnakes. and breaks. The
RDM oft-hook felay /s a Reed relay designed to loriglife. Bell
System requirements for pulse and touch-tone dialing are
described in their Commimications reference "Electrical
Characteristics'of Bell System Network Facilities at the Inter-
+SVIMAKE
.....
OV/BREAK
ON.HOOK
I~
10-121
-~
OFF-HOOK
INTERDIGITAl,.
1DOIM--l-100rM
INTERVAL
iOOmlT02SEC
RI)AA
"Rockwell Data Access, Arrangement Module
Ben System requir~ments exist on minimum and maximum tone
pair transmit power for proper carr address signaling. When the
RDAA is in the programmable mode, the gain of the RDAA
transmit leg is set by a programming resistor i,n the telephone
jack (over thirteen possible values). This makes establishment
01 the tone pair signal level to.be input to the RDAA (at TXA)
Which meets the 'Bell System requirements difficult. It is therefore necessary to operate the RDAA in the Permissive mode for
touch-tone origination. In this event the proper input power level
(per frequency pair) to the RDAA (at TXA) would be + 15 dBM
(nominal) .. This .Ievel is well above the RDAA automatic
limiter threshold. But the RDAAlimiter activates (cuts off transmission. path) . only if threshold power level is continuously
exceeded for about one secorid minimum, and quickly resets
itself if the power leVEl!. drops below threshQld"I.fthe)one pair
duration time is restricted to significantly under one second (the
minimUm duration requirement is only 50 milliseconds) and the
minimum interdigital time requirement (45 milliseconds) is
observed, the limiter will no! be activated. These requirements
are easily met if the tone pair generation is under logic contro\.
If the generation.is controlled via,keyboard input, the limiter will
be activated if a key is depressed and held for, more than a
second, but will recover during. the inter.val between key closures. However, the possibility exists that transients occurring
at limiter activation and resetting, may endanger proper call
origination.
'
,
The OH lead can be pulSEid directly via microProoessor port, Or
a commerCially available "binary to dial pulse" LSI device'such
as the Rockwen CRC 8000, the, ,General Instrument AY-5-9151
series, or the Motorola MC ,14~8. These devices can accept
4-bit, binary digital inputs, buffer these digits, and output- the OH
dial pulses \lpon command. ',·Also available from numerous
semiconductor manufacturers '(National, Mostek, General
Instrument, Motorola, etc.) are LSI, devices ca~ble of inteffacing directly to a key board and producing suitable dial pulses.
TOUCH~TONE
ORIGINATION
, The user's tenninal must provide the logic to turn ON the OH
and RCCT signals, detect the dial tone (or time for 3 seconds
to ensure diaJ loile present) and trarismitthe tone~address
signals via the TXA lead (FiguEes). The 2-second delay period
between,OWand RCCTgoing ON aricfCCTI going ON is not
invoked'in the origination mode,. The DTE shouldmdnitor for
call progress indications (dianohe, DUSY tone, answer tone, and
call interqept).
It should be noted that tone adc;tress signaling method is significantly more complicated in terms of hardware requirements
" ,han simple pulse dialing.:The necessarY tone pair generators
must be added by the user. A number ofsemiconduct-or manufacturers produce monolithic· LSI tone generators .(AMI, Mostek;
Motorola, 'Natiomll, General' Instrument; Intersil, etd.). These
tone pair generators are deSigned t6 interface witli keyboards
or digital ports and may require varying degrees of additional
low pass filtering to reduce harmonic distortion. Touch-tone
dialing is significantly faster than'pulse dialing; but it may not be
available in some locations.
.
',.,'
AUTOMATIC CALLING UNIT
Automatic dialing capapilitymay also be added toa data transmission system simply by purchasing or leasing a separate box
termed an "Automatic Calling Unit" (ACU). Such units are available from a variety of manufacturers. ACU's are available utilizing pulse or tone dialing. Connections of ACU to the data
transmission system may be different for different ACUs. The
standard protocol involved in interfacing between the user's
data terminal equipment and an ACU is documented inCCITT
Recommendation V.25 and also in EIA Standard RS-366.
"lnterfC!ce Between Data Terminal Equipment and AutomatiC
Calling Equipment for Data Communication." It should be reemphasized that a separate ACUil3 not necessarily required for
automatic dial capability. The RDAA .and some external hardware and/or software (as previously described) can suffice.
IDLE
t
,..--
,..--
·OH.DA.ON
I
CCT·DN
I
....DETE.CT DIAL TONE
I
TRANSMIT TONE
ADDResS SIGNALS
R
0
·"DETECT ANSWER TONE
0
T
DATA TRANSMISSION
A
I
A
I
E
MANUAL ORIGINATION
,
For manual origination ·a telephcirie set with an e~clusion key
must be ordered from the local telephone company (refer to
TapIe3-1). After Ii,ting both the handset and the exclusion key,
a call may be originated or anSWered in the same manner as
normaltelephone .service. When the handset and the exclusion
key are lifted (MI is shorted to MIC), the signal SH is turned ON.
If the user's data terminal !sready, it may respond with OH and
RCCT. The RDAA wili then turn ON the GCTI signal. When
answer tone is.heard, the operatpr replaces the handset in its
cradle. the SH Signal will go Low and the data transmission path
is connected. When data transmission is completed, the terminal
turns OFF the OH signal and returns to the idle state.
·OH Be DA-OFF
I
CCl"·05-F
+
"'"--
"--
IDLE
·DA MAY BE PERMANENTLY ON.
"ALTERNATIVELY. USER MAY TIME FOR 3 SECONDS TO
ENSURE DIAL TONE PRESENT.
·-·ANSWER TONE DETECTION CIRCUITRY IS NOT PROVIDED
WITHIN THE RDAA.
Figure 8_
Touch-Tone Origination Sequence
10-122
RDAA
Rockwell Data Access Arrangement Module
SECTION 5 -
FAULT ISOLATION
CUSTOMER REPAIR LIMITATIONS
FAULT ISOLATION
Under the FCC Rules, no customer is authorized to repair an
ROM module. In the event of an ROM malfunction, return the
faulty ROM to Rockwell International. It is recommended that
the following fauH isolation instructions provided in this section
be performed prior to returning a suspected ROM module. A
periodic check of the DC power supplies is also recommended.
The fauH isolation flow chart (Figure 9) has been prepared specifically as an aid to the user for locating possible network and!
or ROM module malfunctions.
Figure 9.
RDAA Fault Isolation Flow Chart
10-123
".
~,
.
SECTION 11
T·1 AND T·1/CEPT PULSE CODE
MODULATION PROTOCOL DEVICES
Page
ProduCt Family OVerview. . . . . . . . . . .. . . . . . . . . . . . . ... . . . . . . . . . . • . . . . . . . . . . . . .11-2
RB040 Tri-Port Memory ..............................................'. . . . ..
11-3
ROOSD T-1 Serial Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
11-9
RBOSD T-1 Serial Receiver ................................................. 11-17
RB07D T-1/CEPT Pulse Code Modulation Transceiver ........................... 11-23
11·1
T-1 AND T-1/CEPT PCM
(PULSE CODE MODULATION) PROTOCOL DEVICES
Meet AT&T and CCITT Standards
Rockwell International is the first company producing LSI
devices for supporting the commercial digital switched
network. The 24 or 32 digitiZe(! channels meet AT&T and
CCITT standards.
'
.
This means it is now possible to design T·lICEPT
systems using LSI instead of discrete devices. This results
in a much lower parts count, lower power requirements,
smaller size and significant cost reductions. It also means
an increase in reliability.
Using our LSI devices, the 24 or 32 channels of 64K bps
information ·and Signaling are multiplexed over a single pair
of wires. All data are transmitted serially, along with framing
bits, at 1.544 to 2.048M bps. At the receiving end frame,
superframe, and channel synchronization is accomplished,
with signaling information outputted and the 24 or 32
channels: uniquely identifiable~
Transmjssiqn in digital format instead of analog has
inherent ability to perfectly regenerate the signal even after
noise in the phone network. The TTL compatible devices
operate from a single 5V power supply.
For specialized memory for digital PBX and other
telecommunication applications, tri·port memory devices
are also .available. These allow random read and sequential
read simultaneously, and, allOw addressing sequentially
or randomly. They support eitl1er time or space division
switching as well as elastic storage applications when
transmission and write speeds differ.
Rockwell LSI Devices Provlde• Parts Count Redu.ctlon
• Cabling Reduction
• Cost Reduction
• Increased Reliability
• Increased Performance
11·2
R$040
T-1 PCM Devices
T-1
R8D40
TRI-PORT MEMORY
OVERVIEW
FEATURES
The Tri-Port Memory circuit is designed to function as an
assemblY point and temporary storage area for a-bit T-1 data.
I! provides 64 8-bit locations of on-chip random access memory
whichcari Cbe accessed via external addresses pr internal
sequential addressing.
•
•
•
•
•
•
•
•
•
TRI-PORT MEMORY OPERATION
The Tri-Port Memory device accepts 8-bit parallel input data on
lines A through H, This data is stored in an internal memory location that is selected by either random address lines R01 through
R32 or by the device's Sequential Address Counter. Write Select
signal WSEl determ.ines the source of tile address; in the logic
O.state, WSEl selects the random address, in the logic 1 state,
WSEl selects the internal sequential address.
'The state of Write Enable signal WE determines whether or not
the data on lines A through H will be written into memory. Data
will'only be written into memory whenWE goes low (to a logic
o state) and the address inputs have stabilized.
64 x B·bit static memory
Single + 5V supply .
Two totally independent read ports
Multiple Read access .time < 430 ns (worst case)
Selectable random- or sequential-address Write operation
On-chip sequential address counter
.
Tri-state drivers, for chip-selectable bus operation
40-pin plastic dual in-line package
LSTTL Schottky-compatible (12KO pullup, to drive CMOS)
APPLICATIONS
Time-division Multiplex (TOM) digital switching data and control
stores
• TOM sequential machines
• Elastic stores
• Hardware/Software control interfaces
• 110 Buffers
The ,on-chip, six-bit Sequential Address Cou(lter is a binary
counter that increments on each pos.itive transition of Sequential Clock (SCll<). When the Counter attain~ binary 111111, ~he
nextposifive transition on SCLK will clear it to binary 000000.
The Counter will also be cleared unconditionally if Reset signal
RST has been set to logic 0 when the positilie transition of SClK
occurs.
The Sequential Read Enable signai, SRE, enables sequentially. addressed read operations. If SRE is logic 0, the sequential
El,ccessed .data outputs (SA through SH) will become valid within
430 ns after the next positive transition on SCLK. If SRE is logic
1, and 350 ns have elapsed since the positive transition of SClK,
the sequential accessed d.ata outputs will become valid BO ns
after the negative transition of SRE. The sequential read data
will cease.to be valid lOOns after the negativ.e transition of SRE
or 20 ns after the next positive transition of SClK, becoming
valid with the content of the next sequential location within
430 ns of that SClK transition.
R04
ROB
1'116
R32
1'102
1'101
RST
SCLK
N.C,
WE
voo
RH
RG' .
aND
RF
RE
RO'
RC
RB
RA
RRE
A
N.C,'
SH
sa
SF
SE
so
se
SB
SA
SRE
B
e
0
a
H
F
The Random Read Enable signal, RRE, enables' randomaccessed' read operations. If RRE is logic 0, tna random
accessed data outputs (RA through RH) will become valid within
380 ns after the random address lines have stabilized. If RRE
is logic 1, and 300 ns have elapsed since the random address
lines have stabilized, the random accessed data outputs will
"NOTE: PIN 34 HAS AN OUTPUT SIGNAL APPLICABLE ONLY
TO 'ROCKWEL:L TESTING, MAKE NO CONNECTION TO THIS
PIN.
Pin Configuration
Document No. R8040D
11·3
Data Sheet Order No. 306
Rev. 3, August 1983
III
R8040
T-1 Tri-Port Memory
:'
'~."
~..:.
",i{':
In the case of a same location read~e cycle, thiii'~eq
andlor ralldomdata outputs will cease,;ti;!~ valid after a , .
transition of WE, and will become valid wit\il theQ'ewly-V/ri
c.ontent!;, within 34d ns of that transition. Conttcl! Qf \h,is "ara,meter
minimizes external circuitry required ~dl-'resolu1i,ol! of read"write
contention.""
become valid 80 ns after the negative transition of RRE. The
random accessed data outputs will cease to be valid 100 ns'after
a paSitive transition of RRE or 29 ns after the;random address,
input lines change, I:!ecoming vali9, wittl,. the contents of the
newly-addressed location within 380 ~'after ttle random address
inputs have stabilized.
RECOMMENDED OPERATING CONDITIONS
Minimum Setup/Hold Times
Setup
Signel
SCLK
Meau,eto "
ns
,.
.f'·
We,
R01·R32
A,·H
..
'JiiST
wq
280
250
150
180
wef
';SCLK l
"
,
Meas",eto
'"
300
Wfl
WEl
"
WSEL
',;
H"",,·
0
0
WEt
WE t
""\
,!:
;
Minimum Pulse, W,idt" .,
WE (=01
..
SCLK
170 n.
220n.
"
SEQUENTIAL COUNTER RESET SETUP AND HOLD TIMING
~RE;~T
-
-
f1~~rTIAL
-:-
-'1Xl
I--
,XX)(-~,:- -~~,HOLD >
SETUP> 180NS---1
,,'"
~'-
'_..JlI
________
0
,'
READ OUTPUTS AT SAME LOCATiON AS WRITE
(ALL OTHER INPUTS STABLE)
L" /
~ (TSLI~ 340
NS MAX
-I'
'IXI\-- --- ~ ---- --XX)!(
OATA
OUTPUTS
NOTE,
RANDOM WRITE ALWAYS, AFFECTS, RANDOM READ OUTPUTS;
SEQUENTIAL WRITE ALWAYS AFFECTSSEQUI;NTlAL READ .oUTPUTS.
EITHER WRITE lOO.Y: AFFECT THE O~POSITE READ OUTPUT. IF, AND ONLY
IF, THE RANDOM A,ODRESS AND,SEQUENTIAL A'DDRESS ARE EQUAL.
11-4
.Q.
0
SCLK t
Signal
,
'\..',
Hio
wet
, Minimum pulse.widi.ltI
"
n.'
NEW DATA __
..
,
T-1 Tri-Port Memory
R8040
WRITE SETUP AND HOLD TIMING
SCLK
IiFWSEL=1)
4: .,"'" ,="'~.'"'" ''''"'-xmzzmmz.
--ll---I
SETUP> 300 NS
WRITE
SELECT
(WSEL)
~~l~S~~=OI
-:-)(XX
I..
______
HOLD> 0 '
i)O(X------:-.~----
I
--i I-~)<)()(~~~IL-----------~------------------------~~~I~~-~--------------------_'_-__-___f--------11--I
HOLD> 0
SETUP > 250 NS-----I
HOLD> 0
SETUP > 280 NS
-------xxx
WRITE DATA
(A.H)
I
I f-- ~l~~PNS ~
----~WIDTH
~
RANDOM READ (RRE
,
= 0, WE
X__________________
I·
= a,WE
~~~~rTlAL ~.'
.,' .
--
I
f---
_{r-----
> 170NS---l
X
.
(TRA) 380 NS MAX.
-~-----""'I
~~~.SHOLD ---j
-XXX
xxx--
= 1)
'.
~f-"'.--------
\ \ \_ _ _ _ _ _\ \
ITSAl430 NS 'Y'AX. '
'.
(ADDRESS STABLE, WE
j
~
,.~.
---XXX
, SEOUENTIAL
OUTPUT DATA
(SA.SHI
READ PORT ENABLE/DISABLE
r
~--------------------------------------~I~---------
>8<*--------
SEQUENTIAL READ (SRE
xxx-
= 1)
RANDOM
ADDRESS
(R01·R32) _____~I~
RANDOM
OUTPUT DATA
(RA·RH)
HOLD
>100 NS
20NS'
MIN. HOLD
-II
--1
L-I.
xxx--
~1)
READ ENABLE
(RRE OR SREI
m
11·5
T-1 Tri-Port· Memory
R8040
Propagation Delays
Symbol
Min
Max
Units
'
tRA
Sequential Read Access Time
380
430
100
Read Port Enable
tPE
Same-Location' Read After Write
tSL
0
0
0
0
0
ns
Read Port Disable Ito HI-Z)
tSA
tpD
Parameter
Random Read Access
T~me
~
80
340
ns
ns
ns
ns
A -WRITE DATA·
B
e
o
•
G
R32 RANOOM ADDRESS INPUTS
1 OF 64
READ
R16
R08
R04
R02
ROI
RANDOM
ADDRESS
DECODER
RANDOM
READ PORT
WRITE
mEL
WRITE
ADDRESS
DECODER
ADDRESS
SELECTOR
"0"'" RANDOM
SEQUENTIAL
ADDRESS COUNTER
SEQUENTIAL
R'EAO PORT
S32
S16
t
1 OF 64
M8~::~:t4=~::::::~
5041-
selK
)-=:::...
____---J[) elK
R
M2r_------~r_------i
Ml
READ
SeQUENTIAL
ADDRESS
DECODER
r---~
~+5
...L) GNO
":' S"RE
0
Tri-Port Memory Block Diagram
11-6
T-1 Tri-Port Memory.
MAXIMUM RATINGS·
. Parameter
Symbol
VaIn
UnIt
Voo
+4.7510 +5.25
V
Supply Voltage
Operating Tetnperatura
Top
Storage "temperatufl'
TSTG
o to
+70
'C
-5510 +150
'C
·NOTE:Str~_ ~bove those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions. above
those.indicated ill other sections of this document is not Implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
ELECTFlICAL CHARACTERISTICS
(Voo
= +5V
±5%. Vss =
ov. TA =
Parameter
25°C)
Symbol·
Input logic "1" Voltage
VIH
Input Logic "0" Voltage
Vil
Min
Max
UnIt
0.8
V
2.0
V
Input Logic "1" Voltage
VOL
Output Logic "0" Voltage
VOL
V
Output Source Current
10H
-100
Output Sirik Current
IOl
400
Input Capacitance
CI
5
Output· Capacitance
Co
25
pF
Power Dissipation '(at 25'C)
Poss
300
rriw
2.4.
0.4
V
"A
"A
PF
111
.11-7
T.. 1 Trl·Port M.mory
R8040
PACKAGE DIMENSIONS
f
.550
":53ii
~~~~~~~~~
I
.160
MAXI
--:140
• -1
2.02
151.3 MMI
J~cll==1
I
M' ;=F'''~' "'~: ~ li::
085
06!>
.060 .
ToO
NOTE:· Pin No.1-is in lower left corner when
svmbolizatio~
is in nOrmal"orientation
11-8
R8050
T·1PCM Devices
',,;
A8050
T·1 SEAIALTAANSMITTER
DESCRIPTION
The Rockwell T-l Serial Transmitter formats data to be
serially transmitted according to T-l 92 or T-l 03specifications, inserting framing and signalling bits along with 24
channels of 8-bit. channel data. The T-l Serial Transmitter
also provides for alarm reporting via the Bit 2 inhibit method
or, with minimal external logic, via the multiframe alignment
signal (Fs) modification method.
INH
TEST
BI13
FASYNC
(lHCLK
S81T
eCis
SSTB
Figure 1 is a functional block diagram olthe T-ol ,',Serial Transmitter. The Mod 193 counter is driven by the clock at 1.S44
MHz and is either synchronized to the driving system by input
signal SYNCIN or provides synchronization via output signal
SYl\iOUT. Input Signal FRSYNGappliessynchronization to
a Mod,12 counter, which identifies the frame of th El 12-frame
multiframe ,being procesi;ed. '.
"
B70PTN
BIT5
WlPLAA
BIT1
UNPLAB
B!T~
OND,
BIT7
,BINOUT
Voo
SYNOUT
CLOCK
lOOP
ALARM
SYNCIN
BIT8
BCH
ACH
Pin Configuration
FEATURES
,
The input data register latches data during each bit period,
when the 8th bit of a channel sample is being transmitted.
The data selector outputs the proper sequence of bits, as
controlled bya bit count and frame count.
• Single SV supply, low power Schottky TTL compatible.
• Accepts 8 bits of parallel data as input.
• Generates output as 193 bit serial data stream iii T-1, 02,
03 or 04 Mode 3 data format.
• Provides a channel and frame timing signal.
• Provides alternate control for alarm reporting and signalling.
• Provides automatic bit insertion for all-zero channel
samples.
The zero channel monitor function t~uses Bit 8 or Bit 7 to
be transmitted' as a "one" if the channel data, sample is all
"zeros." Inputll'lHprovides a means to inhibit the zero
chaHnel mon(torfunclion. Input B70PTN controls the particularS, 'Of the insertion method.
T·1 TRANSa/lITTEF-lINPUiS
Two type'S of transmit formats are provided, a binary output
and a paired unipolar output. The unipolar. pair provides a
means to externally create a single bipolar output with minimallogic.
Any input"" O.SV = logic 0, low. Any input;;. i.ov = logic
1, high. The transition from a low level to. a high level is cal,led
a rising edge, while the converse is defined as a falling edge.
FRSVNC
r----~----'!__----!__-7L,CHC~~F
,svtlCIN >--i~--'~;':;-::::;;;;'
CLOCK
>---i---t.::::'::=J
r-'-+-+-I-"--+lf+1----+-~SYNOUT
!-----!--~ SSTO
Bill
lIlT 2
BIT 3 ,
, BIT.
BITS
, BIT.
BIT 1
r--""""L~
UNPLRA
AlARM
UNPl.R8
ACH
OCH
eels >-=:::::::;:=~
~~~~.~OITr~~
Flgllre 1.
Document No. R8050D
81NOOt
0IT8
____
~
__
~~~aI
T-1 Serial Transmitter
.11-9
Data Sh,et Order No. 307
Rev. 3, August. 1983
T -1 Serial Transmitter
R8050
FRSYNC: Frame Synchronization
BCH: "B" Channel Highway Signalling
Frame sync allows external synchronization of the transmitter's internal frame counter. When FRSYNC becomes
high, the frame counter is directly set to frame 1, the first of
the twelve frames. If FRSYNC is held high and does not
return to zero before a rising edge of CLOCK, the subsequent states of BINOUT, UNPLRA and UNPLRB are high,
high and low, respectively, regardless of the states of any
other inputs. The latter mechanism is useful for device and/
or board testing only and will cause bit errors and/or bipolar
violations if used during field operations. See Figures 6 and 7.
BCH allows the user to transmit one bit of signalling per
channel as Bit 8 of each channel data sample in Frame 12
only. BCH is clocked into the input register by the fal~ngedge
of CHCLKF. Refer to Table 1 and Figure 4.
5-BIT: Multlframe Signalling Bit
SBIT, in conjunction with CCIS, provides an alternate way
to control the multilrame signalling bit (Fs) transmission. The
S-Bit input is transmitted as the multiframe signalling bit (Fs)
if CCIS is held high. Refer to Table 2.
SYNCIN: Synchronization Input
ALARM: Local Alarm
SYNC IN allows external synchronization of the internal
Modulo 193 bit/channel counter. When SYNCIN becomes
high, the Modulo 193 counter is directly set to the state corresponding to the output of the framing (FT or Fs) bit. The
first bit of channel one will be output on BINOUT (and
UNPLRA or UNPLRB) as a result of the first rising edge of
CLOCK following the return of SYNC IN to logic O. See Figures 5 and 7.
Used for reporting alarm conditions. If the ALARM signal is
high, Bit 2 (the most-significant bit) of every channel data
sample of every frame is transmitting as a zero. This is commonly called remote alarm Signalling. ALARM is clocked into
the input register at the falling edge of CHCLKF. Refer to
Table 1 and Figure 4.
LOOP: Loop Strap
TEST: Rockwell Device Test Input
Provided to aid testing of user applications. When enabled
to a high level, LOOP forces the unipolar outputs to transmit
alternating ones and zeros, regardless of input conditions,
while BINOUT continues to provide normal data outputs.
Refer to Figure 3.
Used only for Rockwell device testing. Keep this input
grounded.
CLOCK: T-1 Clock
Maximum frequency = 1.6 MHz
Minimum pulse width = 275 ns
The T-1 bit period is bounded by the rising edges of this
input.
CCIS: Common Channel Interoffice Signalling Strap
Provides optional control for replacing the automatiC Fs pattern with a 4-kilobit common channel signalling path. When
CCIS is high, the SBIT input replaces the Fs pattern and the
insertion of ACH and BCH is suspended. The CCIS input
may also be used to provide the alternate method of alarm
reporting. See Figure 4.
INH: Inhibit Zero Channel Monitor
If INH is high, the zero channel monitor function is disabled,
and Bits 7 and 8 are transmitted per corresponding inputs
received. See Table 1.
B70PTN: Bit 7 Option
Provides Bit 7 as an alternate bit position for "one" stuffing,
as programmed by the zero channel monitor function. Refer
to Table 1.
For channels in signalling frames (6 or 12) in which the first
six data bits and the signalling highway are all "zero," BIT
7 will be forced to one if INH is low. For any frame except
a signalling frame Bit 8 or Bit 7 as selected by B70PTN will
be transmitted as a "one" if the channel input data is "zero"
and INH is low.
VSS, VOD: Ground and Power
Voo = +5 ±O.25 Vdc
Vss = Ground, 0 Vdc
BITS 1-8: Parallel Channel Data Inputs
Bit 1, the sign bit, will be serially transmitted first, followed
by Bits 2 through 8. The falling edge of CHCLKF indicates
input channel data has been clocked into the input register
and always occurs during the transmission of the final bit (Bit
8) of each channel data sample.
T-1 Transmitter Outputs
Low power TIL Schottky compatible. "1" '" 2.4 Vdc, "0" ,,;
0.4 Vdc, CM05-12Kfl pullup to Voo required.
SSTB: 4 kHz Signalling Channel Strobe
ACH: "A" Channel Highway Signalling
SSTB is the least-significant bit of the frame counter. Unless
it is directly set by FRSYNC, SSTS will go high as each
framing bit (FT) is serially transmitted, and will return low as
each multiframe alignment signal (Fs) is transmitted. Refer
to Figure 2.
ACH allows the user to transmit one bit of signalling per
channel as Bit 8 of each channel data sample in Frame 6
only. ACH is clocked into the input register by the falling edge
of CHCLKF. Refer to Table 1 and Figure 4.
11-10
R80S0
T·1 Serial Transmitter
SYNOUT: Channel Sync Output
BINOUT is synchronously transmitted as a high level if
FRSYNC remains high during the rising edge of CLOCK.
Refer to Figures 6 and 7.
SYNOUT provides a means to synchronj~ to the internal bit
counter (Mod 193). SYNOUT is high for one bit tiine,begin,
ning just prior to the first data bit of a frame being seriillly
transmitted. Refer to Figure 8. SYNOUT is the only output
determined by the falling edge of CLOCK.
UNPLRA, UNPLRB: T,1 serial Data Unipolar Outputs
Two paired unipolar outputs are provided for the purpose of
creating a single serial data output transmission in bipolar
format. The unipolar output register toggles for each "one"
bit to be serially transmitted. UNPLRA and UNPLRB are
transmitted as complements for "One" data b~s and as low
levels for "zero" data bits. See Figure 3.
CHCLKF: Channel Clock False
The falling edge of CHCLKF, occurring as Bit 8 of any
channel is being serially transmitted, indicates input data has
been clocked into the input register. With the exception of an
extra bit period extending the low level duration at frame bit
time, CHCLKF is a divide,by,eight of CLOCK. Refer to Figure
The input signal LOOP, if high, forces the unipolar outputs
to toggle every bit time, regardless of input data.
2.
BINOUT: Serial Data Output, Binary Fonnatted
FRSYNC perturbs the current bits being transmitted by
UNPLRA and UNPLRB. 11 FRSYNC remains high during the
rising edge of CLOCK, UNPLRA will be transmitted as a high
level and UNPLRB will be low. Refer to Figures 6 and 7.
BINOUT is the binary formatted serial conversion of the par,
allel input data. The programmed format of BINOUT follows
Tables 1 and 2.
Table 1. Serial Channel Sample Output Data Truth Table
Inputs X
....z
::t
II:
c(
.J
c(
IL
:r
~
0
....
II)
.... '".... t::'"
~
= don't care
......
iii
iii
II)
iii
In
'"
....
....
CD
III
iii
~
Iii
I:
;t;
0
c(
:r
Blnout
Serial Output
Current
Frame
Number
III
t,lotes
Channel
Bit Position
0
1
2
3
4
5
6
7
8
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X'
0
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
1
0
X
X
P
Q
R
S
T
U
V
X
A
X
6
P
Q
A
S
T
U
V
A
f
0
X
X
P
Q
R
S
T
U
V
X
X
8
12
P
Q
R
'S
T
U
V
B
2
0
X
X
P
Q
R
S
T
U
V
W
X
X
Y
P
Q
R
S
T
U
V
W
2.3
0
1
X
0
0
0
0
0
0
0
X
A
X
6
0
0
0
0
0
0
0
A
0
1
X
0
0
0
0
0
0
0
X
X
B
12
0
0
0
0
0
0
0
B
0
1
X
0
0
0
0
0
0
0
W
X
X
Y
0
0
0
0
0
0
0
W
0
0
X
0
0
0
0
0
0
0
X
0
X
6,
0
0
0
0
0
0
1
0
0
0
X
0
0
0
0
0
0
0
X
X
0
12
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
X
X
Y
0
0
0
0
0
0
1
0
3
0
0
0
0
0
0
0
0
0
0
0
X
X
Y
0
0
0
0
0
0
0
1
3
NOTES: (1) ALARM = 1 has the same effect as BIT 2 = 0
(2) P, Q. R, S, T, U and V may m"t simultaneously be zero, unles A, B or W is 1
(3) Y is any frame f 6 and 112 with eels = 0, or alilrames with eels = 1
, 1,11
1
3
R80S0
T-1 Serial Transmitter
Table 2. Framing Bit (FT & Fsl Output Data
Frame
Number
Processed
Bit
1
FT
2
Fs
3
FT
4
Fs
Bino!.',
,
eels
.
~
eels = 1
0
1
1
0
SBIT
0
0
0
SBIT
5
FT
1
1
6
Fs
1
SBIT
7
FT
0
0
8
Fs
1
SBIT
9
FT
1
1
10
Fs
1
SBIT
11
FT
0
12
Fs
a (NOTE 1)
0
SBIT
Notes: (1) Alternate remote alarm reporting may be accomplished by holding SBIT and eels both high just prior
to initiation of Frame 12.
(2) Fr bit insertion· is automatic and no optional control is provided.
.
r
CLOCK
(1.544 MHz)
BINOUT= ~--~~F~~~~~~~~~~~~~~~~~~"~"~\,r~V-~",~",~~~X
BIT NO.
8
_
CHCLKF
~SAMPLE CH.
... CH. 24
-l
1
OR
f -.
I. - - - - - - -
lr7j--------------"'>::L
n---------,,'Yr:SAMPLE CH. 2
FT
CHANNEL 1
•
~
I of
..j
J
CHANNEL 2
(horizontal scale change)
FRAME NUMBER
FT = 1
See Fig. 7
SSTB
SYNOUT
FRSYNC'
~
_____________________________
SYNCIW
'POSSIBLE POSITIONS TO RE·INFORCE INTERNAL SYNCHRONIZATION.
Figure 2. Transmitter Input-Output Signal Relationships
11-12
~~
_ _ _ _ __
R8050
T -1 Serial Transmitter
CLOCK
LOOP
BINOUT
UNPLRA
UNPLRB
Figure 3. Transmitter Binary, Unipolar Outputs
\'----1 \ 1 \
CLOCK
;~;~~
c _ _ _ _ _ _ _ _ _ _ ,_ _ _ _ _ _ _ _ _ _
ALARM
X
::~~~:
~7~PTN
_
xt
6th
t,.
I
X
~
~~_
'" _ _
_ __ _
I
X
7th
x
8th
For1st
x
---1-1t& t: _________________ _
Figure 4 (a). Channel Input Timing
CLOCK
LOOP
~ZXX
~XXZ
\
Figure 4 (b). LOOP Input Timing
CLOCK
.-l
\~----,{
\
BINOUT
CCIS
/
xf= '. fit-----------1\\\\\\\\
SSTB
SBIT
~
-- -- c -- - - , --
X
CH 24, BIT 7
X
CH 24, BIT 8
X
/'-+*~--------"'1-h\(SEE
Fs
x
c - - - --
CH 1, BIT 1
x
NOTE)
NOTE: CCIS WAVEFORM SHOWN FOR ALTERNATE ALARM REPORTING METHOD. CCIS SHOULD BE
ACTIVE JUST PRIOR TO FRAME 12. UNDER THESE CONDITIONS, SBIT HIGH WOULD REPORT
THE REMOTE ALARM.
' - - - - - - - - - - - - - '
Figure 4 (e). Control Input Timing
11-13
m
.
R80S0
T-1 Serial Transmitter
\~~/
,.Jrr;
CLOCK
0
X
SYNCIN
BINOUT
X
ANY BIT
CH 1, BIT 1
x
CH 1, BIT 2
x
Figure 5, SYNCIN Timing Relationship
~
CLOCK
\
j
;;F= ·"~t-·"
FRSYNC
\
\
/
I
III
SSTB
\s:s:
XXX
III
IZI
\\\
XXX
III
XXX
s:s:~
III
XXX
BINOUT
XXX
UNPLRA
UNPLRB
Figure 6. Non-return-to-zero FRSYNC Timing
CLOCK
FRSYNC
(Return to zero)
SYNCIN
DATA
IN
BINOUT
(1 PULSE PER 2316 CLOCKS)
__---..un
..
~~~~N~!:T~
SYNOUT
111111--------------------.. .
may change
I
CH 23
FRAME 12
CHANNEL 1 FRAME 1
78a8FH1828384Hs86
l1li/
SSTB
CHCLKF
(1 PULSE PER 193 CLOCKS, MAX)
'*'\\
!I///
!///III
Figure 7. Transmitter External Synchronization (Return-to-zero FRSYNC)
11-14
..
R8050
T·1 Serial Transmitter
Table 3. Input Timing
Min
Buffered Data Setup Time
Buffered Data Hold Time
Control Input Setup Time
Control Input Hold Time
Asynchronous Control Input Setup Time
Asynchronous Control Input Hold Time
SYNCIN Setup Time
SYNC IN Hold Time
SYNCIN Pulse Width
Frame Sync Setup Time (Return to Zero)
Frame Sync Hold Time (Return to Zero)
Frame Sync Pulse Width
Frame Sync Setup Time (Non-Return to Zero)
Frame Sync Hold Time (Non-Return to Zero)
t,s
t'H
t"
t'H
t,s
t'H
t"
t'H
tss
tSH
tss
tSH
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
450
a
400
20
350
20
200
20
100
250
20
200
525
20
Table 4. Output Propagation Delay, Worst Case
(Measured from Rising Edge of Clock Unless Stated Otherwise)
Output
SSTB
SYNOUT
Ref from Falling
Edge of Clock
CHCLKF
BINOUT
UNPLRA
UNPLRB
Max Delay
Unit
500
500
ns
ns
500
500
500
500
ns
ns
ns
ns
MAXIMUM RATINGS·
Symbol
Value
Unit
Supply Voltage
Parameter
Voo
+4.75 to +5.25
Vdc
Operating Temperature
Top
o to 70
·C
Storage Temperature
TSTG
-55 to + 150
·C
• NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in other sections of this document is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Voo = 5.0 ±5%)
Symbol
Min
Max
Unit
Logical "1" Input Voltage
VOH
2.0
Voo + 0.3
V
Logicical "0" Input Voltage
Vil
-0.3
0.8
V
Logicical "1" Output Voltage
VOH
2.4
-
V
Logic "0" Output Voltage
VOL
-
0.4
V
Output Source Current
10H
-100
~
Output Sink Current
IOl
400
-
Capacitance Load (any output)
C
25
pF
Input Capacitance (any input)
CIN
Parameter
-
Clock Frequency
Power Dissipation
Po
11-15
~
5
pF
1.6
MHz
250
mW
m
R8050'
T-1 Serial Transmitter
PACKAGE DIMENSIONS
I
ill!!)
(.530)
~"T'TTTT'T"M"T"T'"I"'TTT'T'T'TT'T"I'Trr'~
(J!Q)
----1"I"i,
ITJ-
~~~t~
(.150) (.060)
(.125) (.020)
11·16
R8060-R8060A
T-1 PCM Devices
'1'
Rockwell
R8060and R8060A
T-1 SERIAL RECEIVER
DESCRIPTION
The Rockwell T-1 Receiver processes serial unipolar data of a
T-1,D2 or T-1,D3 line from which data and a 1.544 MHz clock
have been extracted.
Frame synchronization is accomplished by locating the frame
bit (FT) alternating every 386 bits. Loss of frame sync is indicated
if a frame bit error occurs within two to four F·Bit frames since
the previous frame bit error.
Remote alarm reporting is detected by monitoring the second
received bit of every channel sample of every frame. An alarm
is indicated if 255 consecutive Bit 2 zeros are received.
Channel data bits are output by an eight·bit parallel register. The
rising edge of the signal called channel clock (CHClK) indicates
the extraction of new output channel data.
SIGFR
SBCLK
WIHBT
B2ALRM
TOATA
COB8
TESTI
COB7
FRALRM
COB6
CHCLK
COB5
CDe4
COB3
MAxCN"T
C"HSYN"C
}""'"""
DATA
BITS
CDB2
COBI
CDINH
SYNCEN
MR
A loss of carrier is indicated if 31 consecutive bit times yield
"zeros" at the input. Carrier loss is reset and frame sync search
begins when a "one" reappears at the TDATA input.
Signaling bits, which occur 193 bit positions after a framing bit,
are monitored to detect signaling frames. The signaling frame
output, SIGFR, identifies the present frame as a signaling frame,
and the S·Bit output at that time identifies which signaling frame
is being processed.
TCLK
VOO (+5)
GND
CALRM
SBIT
TESTa
SBALRM
Pin Configuration
ORDERING INFORMATION
The T·1 Serial Receiver is available in two versions. With the
standard commercial version, R8060, data will be stable within
900 ns after the bit clock. With the selected version, R8060A,
data will be available within 600 ns after the bit clock.
Several signals developed from a MOD 386 counter are provided
to aid in the external processing and storage of channel data.
Signals are provided to increment counters, synchronize
counters, strobe data into memories, etc.
VOO
>--C:>
\ISS
>---e::>- (OND)
CDINH
+511
P2
P12
~p:; : l)
4
,
16
32
,
64
1
±
CHANNH
~~~A
)-..!pl:"_ _ _ _ _ _-1...L..J~~lt-''_,
The Rockwell T·1 Receiver chip operates on a single 5 volt supply
and directly interfaces to the low power TTL Schottky logic family.
The Receiver is packaged in a 28 pin dual in·line (DIP).
TeSTO
Timing relationships are given in figures 3 through 5.
FEATURES
o
Synchronizes serial T·1,D2 orT·1,D3signals in less than 5 ms.
o
Extracts 8·bit parallel channel data
CALRM
m.
SYNCEN~~P1t·
===~f=%~~~~~~_"'
• Provides timing signals to capture and synchronize channel
and frame information
o
Monitors and detects
-
TESTl~
CHSYNC
MA)(CNT
SBClK
S'"T
;rcrn;
(LEAVe OPEN)
S8ALRM
L----=======-B---1'ALRM
• Single 5V supply
• lSTTL Schottky compatible
Document No. R8060D
..
c::;::====~!
Errors in signaling bit pattern
loss of frame sync
loss of carrier
Remote alarm reporting
CHell(
WIHBT
Figure 1.
11·17
R8060
Blo~k Diagram
Data Sheet Order No. 308
Rev. 3, August 1983
~
II.1II
T-1 Serial Receiver
R8060 • R8060A
T-1 RECEIVER INPUTS
COB (1-8): CHANNEL DATA BIT 1 THROUGH 8
Any input ::s;0.8V = LOGIC 0, LOW, ZERO. Any input ;;,:2.0V =
LOGIC 1, HIGH, ONE. A transition from a low level to a high
level is called a rising edge, while the converse is true for the
falling edge.
Bit 1 is the sign bit, Bit 2 is the most significant bit and Em 8
is the least significant bit. If CDINH is low, new parallel channel
data becomes valid within 200 ns after the rising edge of CHCLK
and remains valid until the next rising edge of CHCLK. If CDINH
is high, channel data Bits 1 through 7 are forced to a high level.
Bit 8, the least significant bit, is not controlled by CDINH. Channel data Bits 1 through 7 are enabled or disabled within 300 ns
(R8060) or 150 ns (R8060A) by CDINH. Refer to Figures 3
through 5.
TDATA: UNIPOLAR T-1-D2, T-1-D3 SERIAL DATA INPUT
Unipolar T-l Data is clocked in on the falling edge of TCLK.
Thereafter, TDATA is processed on the rising edge of TCLK.
TDATA must be stable 100 ns before and remain stable 100 ns
after the falling edge of TCLK.
CHCLK -
CHANNEL CLOCK
Typical clock frequency is 1.544 MHz. Maximum clock frequency
is 1.85 MHz. The T-1 bit period is bounded by the rising edges
of TCLK.
The rising edge of CHCLK indicates a change of parallel output
channel data. CHCLK is four TCLKS high then four TCLKS low
except for when an "F" or "S" bit is received. Then CHCLK
stretches to five TCLKS high and four TCLKS low. Refer to
Figures 3 and 4.
SYNCEN: FRAME SYNCHRONIZATION ENABLE
CHSYNC: CHANNEL SYNC
Provides a means to disable the automatic resync search initiated by a FRAME ALARM condition. If the SYNCEN Signal is
low, with synchronization function is inhibited and remains inhibited until SYNCEN transitions high. SYNCEN must be stable
200 ns before the rising edge of FRALRM, in order to inhibit the
synchronization function.
Channel Sync occurs one time in a 24 channel period, making
it suitable for synchronizing external counters to the T-1 Frame
rate. CHSYNC goes low one TCLK period before the tailing edge
of CHCLK at channel 24 date sample time. CHSYNC returns
high 1 TCLK period after the next riSing edge ofCHCLK. Refer
to Figures 3 through 5.
MR: MASTER RESET
TESTO: ROCKWELL DEVICE TEST OUTPUT
Master Reset, when low performs an initialization clear of the
T-l Receiver; SBALRM and CALRM are reset to low levels while
FRALRM, CHCLK, WIHBT and CHSYNC are set to high levels.
Frame synchronization search begins on the rising edge of MR
provided that SYNCEN signal has been high for 200 ns.
Minimum pulse width is one T-l clock period.
Designed to aid in Rockwell device testing. No connection
required for normal operation.
TCLK: T-1 CLOCK
WIHBT: WRITE INHIBIT
WIHBT covers the parallel channel data transition period. WIHBT
is suitable for clocking or strobing channel data into external
memories. WIHBT is high for two TCLK periods, beginning one
TCLK period before the rising edge of CHCLK. Refer to Figures
3 and 4.
CDINH: CHANNEL DATA INHIBIT
Provides a means to disable channel data bit outputs. When at
a high level, CDINH forces channel data Bits 1 through 7 high.
Bit 8, the least significant channel data bit, is not controlled by
CDINH.
MAXCNT: MAXIMUM COUNT OF 386 MODULUS
TESTI: ROCKWELL DEVICE TEST INPUT
MAXCNT is low for one TCLK period, marking the completion
of a two-frame period corresponding to the expected receipt of
an F-bit at the TDATA input. Refer to Figures 4 and 5.
Used only for Rockwell device testing, no connection to TESTI
is required for normal operation.
SBCLK: S-BIT CLOCK
SBCLK will be high during the S-Bit frame and low during the
F-bit frame. The transitions will occur within 300 ns after the rising edge of TCLK as channel 24 data is being transferred to the
parallel channel outputs. Refer to Figures 3 through 5.
VSS, VDD: GROUND AND POWER
=
+ 5.0 ± 0.25 VDC
VDD
VSS = Ground, 0 VDC
S-BIT: SIGNALING BIT OUTPUT
T-1 RECEIVER OUTPUTS
The S-Bit output monitors the previous S-Bit received which
occurred two frames before the receipt of the current S-Bit. An
S-Bit output transition occurs one TCLK period after the rising
edge of SBCLK.
Low Power TTL Schottky - compatible
"1" ;;,: 2.4 Vdc; "0" ::s; 0.4 Vdc
CMOS - 12 K Opullup to VDD required.
11-18
T"1 SetialReceiver
R8060 • R8060A
During a signaling frame (SIGFR is low), frame 6 or "A" highway
signaling is identified by S-Bit output being low. If S-Bit is high
during a signaling frame, frame 12 or "B" highway signaling
is identified. Refer to Figures 3 through 5.
FRALRM is set high and, frame sync search begins when the
first TDATA high level is received.
FRALRM: FRAME ERROR ALARM
SIGFR: SIGNALING FRAME
FRALRM detects an out-of-frame condition. FRALRM goes high
if:
SIGFR identifies frame 6 or 12 when low. If the sequenpe (If five
consecutive received 5-Bits is eitherOll1X or lXOOI (left to right,
as received), SIGFR shall go low after the rising edge, but at
least 375 ns before the falling edge of WIHBT corresponding
to channell data sample time. SIGFR returns high one frame
later (193 bits). Refer to Figures 3'through 5.
A) The framing synchronization function is in progress.
B) Within 250 ns after the falling edge af,MR.
C) An F-Bit is received which is not the inverse of the last
F-Bit and the same condition also occurred two or three
or four F-Bil frames earlier.
D) Within 250 ns after the falling edge of CALRM, (CALRM
being reset by high level TDATA bit).
SBALRM: S-BIT ALARM
FRALRM goes low upon completion of the synchronization function or within 250 ns after the riSing edge of CALRM. (Carrier
loss condition during frame synchronization function).
SBALRM goes high if the sequence of the five S-Bits received
contains four consecutive ones (01111), and remains high until
three consecutive "zero" bits are preceded and followed by a
"one" S-Bit (10001). The actual transition of SBALRM output
occurs after the rising edge, but at least 375 ns before the failing edge of WIHBT corresponding to channel 1 'data sample
time.
OUTPUT CLOCK SIGNALS DURING FRAME
SYNCHRONIZATION FUNCTION
Following the Declaration of Frame Sync loss (FRALRM goes
high), output signals will continue normally for a two-frame period
with.the exception of CHSVNC, which has the above mentioned
second frame sync pulse inhibited. Following the two-frame
period CHCLK, CHSVNC, and WIHBT are held high until frame
sync has been located, as indicatEld.by the falling edge of
FRALRM. With typical data patterns, frame synchronization
takes less than five milliseconds. See Figure 2.
B2ALRM: BIT 2 ALARM
B2ALRM goes high, detecting a remote alarm condition, if 255
consecutive channel data sample~ are received with Bit 2 low ..
B2ALRM returns low upon the receipt of any channel sample
with Bit 2 high.
CALRM: CARRIER LOSS ALARM
A carrier loss is detected and CALRM is set high if 31. consecutive low level TDATA bits are received. CALRM is reset low,
/FRAMESVNC
FRALRM-----Jr------~------------~----------~--------T~I_______________
II-.......- - - 2 FRAME PERIOD------i-.-tl
-------,L-.Jr-----
CHSVNC~r_"._j,...i--.-{flf-
CHCLK~~
WIHBT
Figure 2.
Signat Retationship During Frame Alarm and Search for Resynchronization
11-19
T -1 Serial Receiver
R8060 • R8060A
. . 0 4 - - - F BIT FRAME
~
'NP,~~~::~ I '
___
CH24
.J'~
I
S BIT FRAME' ----....
CH1
_ _---..,
I
I H 32 H • I 412 I' IB~T I
t
A~
±
_ _ _- . .
I .. 1 1f·1 • I 4 I 2I'
32
I H 32
t
CLOCKED DATA I' I t I" 132 1'.1 • I 4 I 2 I, IB~T I ± 1"1 32 1'.1 • I 4 I 2 I' I t 1"1
TCLK (1.54 MHZ)
'------'I
CHClK
WIHBT
SBCLK
________________~x~~---------------
SBIT
X...___CH_2_4_0_UT_P_U_T_D_AT_A__--'~
v-::::;-
CHANNEL DATA~
PARALLEL OUT ~L---,-C_H_2l_D:...U_T_PU_T_D_A_T_A_--.J
.Figure 3.
Signal Relationships at Beginning of FS Frame (S-BIT)
_ _ _ _ _ S BIT FRAME
FBITFRAME~
CH'
CH24
INPg~~::~ I'
I
CLOCKED DATA I'
,,-------''''-----..
t
1.. 132 1f.l· 14 I 2 1'IB~TI
I ± 1.. 1
32
++, H • I 4I 2r, I
t
1.. 132
1,.1 • I 4 12 I' IB~TI ± 16413.1'.1 • I 4 I 2I, I ± 164 1
CHCLK
WIHBT
'-------'I
SBIT
NO CHANGE
u
~~~:~~iLD;J:~'___C_H_23_0_U_T_PU_T_D_A_T_A_
Figure 4.
__.JX'____C_H_2_4_0_UT_P_U_T_D_AT_A___~
Signal Relationship at Beginning of FT Frame (F-BIT)
11-20
T-1 Serial Receiver
R8060· R8060A
FRAME SYNCHRONIZATION
BIT IF BIT) PATTERN
SIGNALING SYNCHRONIZATION
BIT (SBIT)'PATTERN
SBCLK
mIT~~
____________________- - J
(OUTPUT)
SIGFR-----------,L.j
MAXCNT
---..,Ur-----,Ur----,u
u
u
FRAME = 24 TIME SLOTS = 193 BITS = 125ILS
TIME SLOT = 5.181LS ONE BIT = 648 NS
MULTIFRAME = 12 FRAMES = 1.5 MS.
F BIT (F T ) FRAME ALIGNMENT SIGNAL
(ODD·NUMBERED FRAMES)
S BIT (FS) MULTI FRAME AI,.IGNMENT SIGNAL
(EVEI,II·NUMBERED FRAMES)
FRAME
FIRST BIT
FRAME
FIRST BIT
1
3
5
7
1
2
4
o
o
6
8
10
12
1
1
1
9
11
o
1
o
1
o
Figure 5.
Table 1. Output Propagation Delay
Worst Case, From Rising Edge to TCLK
OUTPUT
o
Multiframe Signal RelationShips
I
MAX DELAY (NS)
1.550)
1.5301
CHCLK
CHSYNC
WIHBT
MAXCNT
SBCLK
SBIT
SIGFR
SBALRM
B2ALRM
CALRM
FRALRM
COB (1-8)
300
300
300
300
300
400
475
475
450
300
900 (RS060)
600 (RS060A)
400
LM-n-rTTnTT'rTTTTTTTT'TTTTTTTT"'c..l
Packaging Diagram
11-21
OJ
R8060' • R8060A
T-1 Serial Receiver
MAXIMUM RATINGS·
Symbol
Value
Unit
Supply Voltage
Parameter
Voo
+4.75 to +5.25
V
Operating Temperature Ra,rige
Top
Storage Temperature Range
TSTG
o to
+70
-55 to + 150
·C
·C
"NOTE: Stresses above those listed:may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device, reliability.
ELECTRICAL CHARACTERISTICS
(Voo
=
+5V ±5%, T... = 25°C)
Paramater
"
Min
Max
Input Logic "'1" Voltage
VJH
2.0
Voo +0.3
V
Input Logic "0" Voltage
VJL
-0.3
0.8
V
Symbol
Output Logic '''1'' Voltage
VOH '
Output Logic "0" Voltage
VOL
Output Source Current
lOti
-100
Output Sink Current
10L
400
Clock Frequency
TCLK
Input Capacitance
2.4
Unit
V
0.4
V
,.A
,.A
1.85
MHz
pf
CJ
5
Output Capacitance
Co
25
pF
Power Dissipation
PDS~
550
mW
"
11-22
R8070
T·1ICEPT PCM Devices
R8070
T-1/CEPT PCM TRANSCEIVER
PRELIMINARY
INTRODUCTION
• Operates with EXTENDED FRAMING, CLEAR CHANNEL
andlor CEPT formats
• Uses a clock of 1.544 (T-l), 1.576 (112 T-tC), or 2.048 (CEPT)
MHz depending on operation mode
• Supports multiplex/demultiplex T-1C, mode 1 (synchronous)
operation
• Formats data to be serially transmitted/received according to
CCITT and AT&T specifications
• Mode Selectabie - provides 17 different data format and zero
suppression mode combinations
• Selectable serial or parallel digital data interface
• Provides status and alarm information to peripheral equipments for control and status reporting
• Allows external synchronization of the transmitter's internal
circuitry
• Generates signals for external processing of data
• Interfaces between multiplexed· digital signals and the PCM
highway
The R8070 T·l/CEPT Transceiver is a new generation PCM
(Pulse Code Modulation) protocol device designed and manufactured by AQCkwelllnternational. The new device utilizes CMOS
technology providing a higher level of component integration
than its predecessors; low power dissipation and many features
and capabilities. The device is designed to meet AT&T and
CCITT specifications, including EXTENDED FRAME and CLEAR
CHANNEL and/or CEPT applications using T·l, T·1C or CEPT
specifications.
Product availability of R8070 T-lICEPT PCM Transceiver is
Winter, 1984.
APPLICATIONS
• Channel Banks - add signalling and framing information to
the multiplexed 24-volce channels
• CPI and .DMI - provides bidirectional data communication
between systems
• PBX - interfaces between transmission medium and trunk
side of PBX
• Time and Space Division Switching - provides interface
between PCM highway and dedicated time slot interchange
circuitry
• Can be used in virtually any vOice/data system designed to
AT&T or CCITT specifjcations for primary rate interface
CUSTOMER BENEFITS
R8070 T·1/CEPT PCM Transceiver
Use of the R8070 will:
• Reduce board layout area
• Save power - CMOS low power dissipation
• Provide higher design reliability - replaces 100 MSI with one
chip
•. Provide cost reduction
• Meet AT&T and CCITT specifications in a single device
• Provide ease of signal processing on a digital data
FEATURES
• PCM format transceiver (transmitter and receiver in one Chip)
• CMOS technology design
• 5-volt single supply voltage
• 54-pin QUIP package
• Meets CCITT G.732, G.733 and G.703 (applicable parts)
specifications; and AT&T advisories
Document No. 29300N11
11-23
Product Summary Order No. 311
March,
1984
T-1/CEPT PCM Transceiver
R8070
SELECTABLE R8070 MODES
'"
DESCRIPTION
MNEMONIC
T·1
,
193 bitslfraine, no,signalling
4 frames per super frame
Zero suppression - BSZS, B7 stuffing, or transllarent
193 bits/frame, with signalling
12 frames per super frame
Zero suppression - BeZS, B7 stuffing, or transparent
193 bits/frame, extended frame, with signalling
24 frames per super frame
Zero suppression - BeZS, B7 stuffing, or transparent
193 bitslframe, extended frame, no signalling
24 frames per super frame
Zero suppression .:... eeZS or transparent
197 bitslframe, 'II! synchronous T·1C, no signalling
4 frames per super frante
Zero suppression, (None) transparent
193N
1935
193E
193F
197N
197 bits/frame, 'I. syt1chronous n·c, with !!ignalling
12 frames per super frame
Zero suppressio,"" (None) transparent
1975
CEPT
256 bits/frame, with signalling
2 frames per super frame
Zero suppression - HDB3 or trimsparent
256 bits/frame, with signalling
16 frames per super frame
Zero suppression - HDB3 or transparent
256N
256S
Legend:
Zero Suppression Key
BeZS = Bipolar e Zero Substitution
B7 = Bit 7
HDB3 = High Density Bipolar 3 Zero Max
11-24
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