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Motorola's Microcomputer Families

I

Reliability

I

Data Sheets

I

Mechanical Data

I

Technical Training

I

Memory Products

I

Logic and Special Function Products

I

Development Systems and
Board-Level Products

II.

MOTOROLA
MICROCOMPUTERS
Prepared by
Technical Information Center

This book is intended to provide the design engineer with the technical data
needed to completely and successfully design a microcomputer based
system. The data sheets for Motorola's microcomputer and peripheral components are included.
The information in this book has been carefully checked; no responsibility,
however, is assumed for inaccuracies. Furthermore, this information does
not convey to the purchaser of microelectronic devices any license under
the patent rights of the manufacturer.
Additional information about memory products, technical training, and
system development products is also provided. For further marketing and
applications information, please contact:

Motorola Inc.
MOS Integrated Circuits Group
Microprocessor Division
Austin, Texas
(512)928-6800

Printed in U.S.A.

Series C
Second Printing
©MOTOROLA INC., 1984
Previous Edition © 1981
"All Rights Reserved"

Product Preview data sheets herein contain information on a product under
development. Motorola reserves the right to change or discontinue these
products without notice.
Advance Information data sheets herein contain information on new products. Specifications and information are subject to change without
notice.

EXORciser and EXORmacs are registered

trad~rnarks

of Motorola Inc.

BASIC-M, EXORbug, EXORbus, EXORdisk, EXORset, EXORterm, HDS-200,
1I0module, LlLbug, MDOX, MICRObug, Micromodule, PRObug, RMS09,
RMS68K, SUPERbug, UNICORN, UNIDOS, VERSAbug, VERSAbus,
VERSAdos, VERSAmodule, VMC 68/2, VMEbus, VMEmodule~ and VME/10
are trademarks of Motorola Inc.
DEC and VAX are trademarks of Digital Equipment Corporation
LARK is a trademark of Control Data Corporation
Sentry is a registered trademark of Fairchild
Silent 700 Cassette is a trademark of Texas Instruments Incorporated
UNIX is a trademark of Bell Labs

ii

TABLE OF CONTENTS
Page No.

Title

Chapter 1 - Motorola's Microprocessor and Microcomputer Families
Introduction ...........................................................................................
Single-Chip Microcomputers (MCUs) - The M3870, M6801,
M6804, and M6805 Families.........................................................
CMOS M6805 Components ..................................................................
M6804 Family Spectrum .......................................................................
CMOS M6805 and CMOS M6804 Spectrum ......................................
M6805FamilySpectrum .......................................................................
M6801 Family Spectrum........................................ ...............................

1-3
1-6
1-9
1-10
1-11
1-12

Chapter 2 - Reliability
Reliability and Quality Monitor Report ...............................................

2-3

1-3

Chapter 3 - Data Sheets
(See Master Index for sequence)
Chapter 4 - Mechanical Data
Introduction ...........................................................................................
Package Dimensions ............................................................................

4-3
4-3

Chapter 5 - Technical Training
Introduction ...........................................................................................
Course Offerings...................................................................................

5-3
5-3

Chapter 6 - Memory Products
Selection Guide.....................................................................................

6-2

Chapter 7 - Logic and Special Function Products
MC144110/1............................................ ................................................
MC145000/1............................................ ................................................
MC145040/1............................................................................................
MC145157/8............................................ ................................................
High-Speed CMOS Selector Guide .....................................................:

7-3
7-4
7-5
7-6
7-7

Chapter 8 - Development Systems and Board·Level Products
Development Systems...........................................................................
Reference Guide: Selection by MPU/MCU Supported.......................
Microcomputer Boards ..................................... :...................................

8-3
8-15
8-19

iii

iv

MASTER INDEX
This index includes all devices in Motorola 8-bit
Microcomputer and Microprocessor/Peripheral
product line. Devices with MPU in the page
number column are fully characterized in the
separate Microprocessor Data Book.
Device No.
MC1372
MC2670
MC2671
MC2672
MC2673
MC2674
MC2675
MC3440A
MC3441A
MC3443A
MC3446A
MC3447
MC3448A
MC3870
MC6800
MC6801
MC6801U4
MC6802
MC6802NS
MC6803
MC6803E
MC6803U4
MC6804J2
MC6804P2
MC68HC04P2
MC68HC04P3
MC6805K2
MC6805K3
MC6805P2
MC6805P4
MC6805P6

Description
Page No.
Color Television Modulator .................. .
3-3
Display Character and Graphics Generator ..... . MPU
Programmable Keyboard and Communications
Controller ............................... . MPU
Programmable Video Timing Controller ........ . MPU
Video Attributes Controller .................. . MPU
Advanced Video Display Controller ............ . MPU
Color/Monochrome Attributes Controller ....... . MPU
3-11
Quad Interface Bus Transceiver .............. .
Quad Interface Bus Transceiver .............. .
3-11
Quad I nterface Bus Transceiver .............. .
3-11
3-15
Quad Bidirectional Bus Transceiver ........... .
Octal Bidirectional Instrumentation Bus (GPIB)
Transceiver .............................. .
3-18
Quad Bidirectional Instrumentation Bus (GPIB)
Transceiver .............................. .
3-24
8-Bit Single-Chip Microcontroller ............. .
3-29
8-Bit Microprocessor Unit. ................... . MPU
8-Bit Microcomputer Unit .................... .
3-52
8-Bit Microcomputer Unit .................... .
3-91
8-Bit Microprocessor with Clock and
Optional RAM ............................ . MPU
8-Bit Microprocessor with Clock and
Optional RAM ............................ . MPU
8-Bit Microprocessor Unit. ................... .
3-52
8-Bit Microprocessor ........................ . MPU
8-Bit Microprocessor Unit .................... .
3-91
8-Bit Microcomputer ........................ . 3-133
8-Bit Microcomputer ........................ . 3-179
8-Bit HCMOS Microcomputer Unit ............. . 3-225
8-Bit HCMOS Microcomputer Unit ............. . 3-225
8-Bit Microcomputer Unit with Serial Peripheral
Interface and Two Timers .................. . 3-227
8-Bit Microcomputer Unit with A/D Converter,
Serial Peripheral Interface, and Two Timers ... . 3-227
8-Bit HMOS 1 K Microcomputer ............... . 3-231
8-Bit HMOS 2K Microcomputer ............... . 3-253
8-Bit Microcomputer ........................ . 3-276

v

Device No.
M C68(7)05 R/U
Series
MC6805R2
MC6805R3
MC6805S2
MC6805T2
MC6805U2
MC6805U3
MC68HC05C4
MC6808
MC6809
MC6809E
MC68HC09E
MCM6810
MC68HC11A4
MC6821
MC6822
MC6829
MCM68HC34
MC6835
MCM6836E16
MCM6836R16
MC6839
MC6840
MC6844
MC6845
MC6846
MC6847
MC6847Y
MC6850
MC68HC51
MC6852
MC68HC53
MC6854
MC6859
MC68HC68A1
MC68HC68R1
MC68HC68R2
MC68HC68T1
MC6875
MC6875A
MC6880A/MC8T26A

Description
8-Bit Microcomputers .......................
8-Bit Microcomputer ........................
8-Bit Microcomputer ........................
8-Bit Microcomputer with A/D Converter, Serial
Peripheral Interface, and Three Timers .......
8-Bit HMOS 2K Microcomputer with PLL .......
8-Bit Microcomputer ........................
8-Bit Microcomputer ........................
8-Bit HCMOS Microcomputer .................
8-Bit Microprocessor with Clock and

Page No.
.
.
.

3-298
3-298
3-298

.
.
.
.
.

3-390
3-481
3-298
3-298
3-508

No RAM ................................ .

MPU
MPU
MPU
MPU
MPU
3-599
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU

8-Bit Microprocessing Unit ................... .
8-Bit Microprocessor Unit .................... .
8-Bit HCMOS Microprocessing Unit ........... .
128 x 8-Bit Static Random Access Memory ..... .
8-Bit Microcomputer ........................ .
Peripheral Interface Adapter ................. .
Industrial Interface Adapter .................. .
Memory Management Unit ................... .
Dual-Port Memory Unit ...................... .
Mask Programmed CRTC Controller ........... .
128K Combination ROM/EEPROM Memory ..... .
128K Combination ROM/EEPROM Memory ..... .
Floating-Point ROM ......................... .
Programmable Timer ........................ .
Direct Memory Access Controller ............. .
CRT Controller (CRTC) ...................... .
ROM-I/O-Timer ............................. .
Video Display Generator ..................... .
Video Display Generator ..................... .
Asynchronous Communications Interface
Adapter ................................. .
Asynchronous Communications Interface
Adapter ................................. .
Synchronous Serial Data Adapter ............. .
Asynchronous Communication Interface Adapter
Advanced Data-Link Controller ............... .
Data Security Device ........................ .
Serial 1O-Bit A/D Converter ................... .
8-Bit Serial Static RAM ...................... .
8-Bit Serial Static RAM ....................... .
Real-Time Clock plus RAM and Power
Sense/Control ........................... .
Two-Phase Clock Generator .................. .
Two-Phase Clock Generator .................. .
Quad Bus Transceiver ....................... .

vi

MPU
MPU
MPU
MPU
MPU
MPU
3-623
3-624
3-624
3-627
3-637
3-637
3-650

Device No.

Description

MC6882A, B/MC3482A, B Octal Buffer/Latch. . . . . . . . . . . . . . . . . . . . . . . . . ..
MC6883/SN74LS783
Synchronous Address Multiplier. . . . . . . . . . . . . ..
MC6885/MC8T95
Hex Address Buffer. . . . . . . . . . . . . . . . . . . . . . . . ..
MC6886/MC8T96
Hex Address Buffer. . . . . . . . . . . . . . . . . . . . . . . . ..
MC6887/MC8T97
Hex Address Buffer. . . . . . . . . . . . . . . . . . . . . . . . ..
MC6888/MC8T98
Hex Address Buffer. . . . . . . . . . . . . . . . . . . . . . . . ..
MC6889/MC8T28
Quad Bus Transceiver. . . . . . . . . . . . . . . . . . . . . . ..
8-Bit MPU D/A Converter. . . . . . . . . . . . . . . . . . . . . .
MC6890
MC68120
Intelligent Peripheral Interface ................
MC68121
Intelligent Peripheral Interface ................
MC68701
EPROM Microcomputer. . . . . . . . . . . . . . . . . . . . ..
MC68701 U4
8-Bit EPROM Microcomputer. . . . . . . . . . . . . . . . ..
MC68705P3
8-Bit EPROM Microcomputer. . . . . . . . . . . . . . . . ..
MC68705P5
8-Bit EPROM Microcomputer. . . . . . . . . . . . . . . . ..
MC68705R3
8-Bit EPROM Microcomputer. . . . . . . . . . . . . . . . ..
MC68705R5
8-Bit EPROM Microcomputer. . . . . . . . . . . . . . . . ..
MC68705U3
8-Bit EPROM Microcomputer. . . . . . . . . . . . . . . . ..
MC68705U5
8-Bit EPROM Microcomputer. . . . . . . . . . . . . . . . ..
MC146805E2
8-Bit CMOS Microprocessor. . . . . . . . . . . . . . . . . ..
MC146805E3
8-Bit CMOS Microprocessor. . . . . . . . . . . . . . . . . . .
MC146805F2
8-Bit CMOS Microcomputer. . . . . . . . . . . . . . . . . ..
MC146805G2
8-Bit CMOS Microcomputer. . . . . . . . . . . . . . . . . ..
MC146805H2
8-Bit CMOS Microcomputer. . . . . . . . . . . . . . . . . ..
MC146818
CMOS Real-Time Clock plus RAM. . . . . . . . . . . . ..
MC146823
CMOS Parallel Interface . . . . . . . . . . . . . . . . . . . . ..
MC1468705F2
8-Bit CMOS Microcomputer with EPROM. . . . . . ..
MC1468705G2
8-Bit CMOS Microcomputer with EPROM. . . . . . ..
TCA5600
Universal Microprocessor Power Supply
Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TCF5600
Universal Microprocessor Power Supply
Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

vii

Page No.
3-655
3-660
3-685
3-685
3-685
3-685
3-690
3-695
3-702
3-702
3-746
3-786
3-827
3-851
3-298
3-298
3-298
3-298
3-876
MPU
3-910
3-935
3-962
3-994
3-1016
3-1031
3-1033
3-1059
3-1059

Motorola's Microcomputer Families

1-1

I

I

1-2

MOTOROLA'S
MICROPROCESSOR AND MICROCOMPUTER FAMILIES
Serving as the "heart" of every microcomputer system is a microprocessor. Motorola
manufactures the industry's most complete selection of solid-state microcomputer components to provide the performance you need and the design flexibility you want.
The family concept has been extremely popular in the microprocessor industry. Motorola
pioneered this family concept with the introduction of the M6800 Family in 1974. Since
then the MPU/MCU Family has evolved in several directions, as shown in Figure 1-1, in
order to fill expanding use concepts. In addition, the basic M6800 Family has been enhanced. A large number of .peripheral devices have been developed to support the expanding family of microprocessors and microcomputers.

SINGLE-CHIP MICROCOMPUTERS (MCUs)
THE M3870 AND THE M6801 - M6804 - M6805 FAMILIES
Take a basic MPU; add an on-chip clock oscillator and timer, put in enough Read-Only
Memory (ROM) to handle the program routines for dedicated application, and enough
Read/Write (RAM) Memory capacity to handle the associated data manipulations; cap it
off with sufficient input/output capability to interface with a number of parallel and serial
oriented peripherals and you have a single-chip microcomputer.
The single-chip system doesn't necessarily have all the flexibility of a mUlti-chip system,
but with adequate capacity to handle a specific requirement, it can save both component
cost and equipment manufacturing cost. Motorola offers single-chip microcomputers across
a broad spectrum of processor performance and system functionality. Motorola's first high
volume production single-chip MCU is the second source of the popular 3870. The M6801
Family includes the high performance single-chip MCU, plus EPROM and ROM-less versions. The rapidly expanding M6805 Family includes a number of memory and package
sizes with various special I/O functions, in both HMOS and CMOS. The M6804 Family
now provides the 8-bit processing capabilities that compete in the 4-bit price arena!

PERFORMANCE - Processor performance, or program efficiency, for the application
is an important single-chip MCU selection criteria. The M6801 Family is the throughput
leader with 16-bit data operations, binary mulitply, and an average of only 3.7 cycles per
instruction. Bit modify and test instructions and powerful indexing modes put the M6805
Family in second place on the performance scale. The MC3870 also offers a very successful 8-bit architecture. The MC6804 Family offers the proven capability of the M6800based instruction set.

1-3

I

-6.0
5.0
4.0
3.0 --.

~- - -

-- -

"'

,..
(

~ 2.5~

~

~

0
u.

1.5

~

12l

a:
w
a..

~

y~lrov

/

~ 2.0
a:

--- ....

) ..........

'" -L.-/(

,,..- -"
)
~'---/
.........

--

.......
68HC11. )

--./

1.0

'"

0.75

---

0.5
0.4

1976

1977

1978

1979

1980

1981

INTRODUCTION YEAR

FIGURE 1-1. GENEALOGY OF THE COHESIVE
M6800 MICROPROCESSOR/MICROCOMPUTER FAMILY

1982

1983

.......

---

0.6

1975

./

1984

)
./

TECHNOLOGY -

The very high production volumes of high-density NMOS (HMOS)
permit low cost single-chip solutions. CMOS, as a relatively new microcomputer technology,
offers very low power consumption and wide power supply tolerance at performance levels
similar to HMOS. The M6801 Family, M6805 Family, and MC3870 are produced in HMOS
while the M6805 Family makes CMOS benefits available. The M6805 Family is the first
microcomputer that allows you to look at the technology trade-offs independent of the
architectural and supplier choices. The new M6804 Family is available in both the HMOS
and CMOS technology.

SINGLE-CHIP MICROCOMPUTERS, SELECTOR GUIDE
BY TECHNOLOGY
HMOS/NMOS .............. PAGE

HMOS/NMOS .............. PAGE

MC6804J2 ..................... 3-133
MC6804P2 ..................... 3-179
MC6805K2 ..................... 3-227
MC6805K3 ..................... 3-227
MC6805P2 ..................... 3-231
MC6805P4 ..................... 3-253
M C6805P6 ..................... 3-276
MC6805R2 ..................... 3-298
MC6805R3 ..................... 3-298
MC6805S2 ..................... 3-390
M C6805T2 ..................... 3-481
MC6805U2 ..................... 3-298
MC6805U3 ..................... 3-298
MC68705P3 ................... 3-827
MC68705P5 ................... 3-851
MC68705R3 .................. 3-298
MC68705R5 .................. 3-298
MC68705U3 .................. 3-298
MC68705U5 .................. 3-298

MC6801 ........................... 3-52
MC6801 U4 ....................... 3-91
MC6803 ........................... 3-52
MC68120/121 ................ 3-702
MC68701 ....................... 3-746
MC68701 U4 .................. 3-786
MC3870 ........................... 3-29

CMOS
MC68HC04P2 ............... 3-225
MC68HC04P3 ............... 3-225
MC68HC05C4 ............... 3-508
MC146805E2 ................. 3-876
MC146805F2 ................. 3-91 0
MC146805G2 ................ 3-935
M C 146805 H 2 ................ 3-962
MC1468705F2 ............. 3-1031
MC1468705G2 ............ 3-1033
MC68HC11A4 ............... 3-599

ROM SIZE -

The mask ROM capacities of the present single-chip MCUs range from
1K byte for the M6805 and M6804 Families, up to 4K bytes on the M6801 Family version.
However, the M6801 and M6805 Families may in the future be implemented with as much
as 64K bytes of on-chip ROM without any architectural changes. In selecting the ROM
size, the ROM usage efficiency of the instruction set should be considered, along with the
application to be programmed. The architecture of the MC3870 class offers short one- and
two-byte instructions. The M6801 and M6805 Families use many multi-function instructions
such as bit manipulation, memory modification, indexing, and multiply to do the function
of two or more instructions in traditional MCUs.

NON-MASK-ROM VERSIONS - EPROM versions and/or ROM-less versions of practically all single-chip MCUs are offered. They serve for limited to high volume applications,
prototype debugging, and field trials. EPROM versions are available in the M6805 and
M6801 Families. ROM-less versions are offered in the M6801 and M6805 Families.
1-5

I

I

RAM SIZE - On-chip RAM sizes range from 32 bytes in the M6804 Family to 192 bytes
in the M6801 Family. Between these present limits are the M6805 Family versions of 96,
112, and 176 bytes. Architectures such as the M6801 and M6805 Families which permit
multi-level subroutines plus ROM and RAM data tables allow you to trade-off ROM and
RAM utilization. ROM usage can be minimized with subroutines and look-up tables, while
RAM use can be optimized with ROM tables and fewer subroutines.
DIGITAL I/O - Single-chip MCUs are available in 40-pin dual-in-line packages as well
as the smaller (and lower cost) 28-pin packages. All these MCU families include 40-pin
versions, while the M6805 Family has 28-pin members. Five to seven pins serve power
and control functions permitting up to 23 1/0 pins in a 28-pin package and up to 34 1/0
pins in 40-pin versions (including interrupts, timers, and special 1/0 functions). All of the
MCUs offer essentially any mix of inputs and outputs. Higher output drive current is available
in the M6805 Family.
EXPANSION BUS - The ROM-less versions include a bus to access off-chip program
memory and additional 1/0. However, the M6801 Family single-chip MCUs also include
three bus structure modes for off-chip expansion. The three bus modes permit the number
of bus pins to be otimized for the amount of address space needed off-chip.
INTERRUPTS -

When an application program must synchronize with two or more
external events, interrupt hardware in some form is usually necessary. The M6801 and
M6805 Families include fully automatic interrupts (registers are saved) with programmable
vectors for both external pins and internal timers. The MC3870 interrupt scheme requires
more program overhead.

TIMERS - On-chip timers are the most frequently used special 1/0 function. Timers may
generate interrupts to a program at a periodic rate, measure external values, count external
events, and generate measured output values. The M6801 Family includes a 16-bit timer
that may be used to perform three of the above functions simultaneously. The M6805
Family timer consists of a programmable 8-bit counter and a selectable 7-bit prescaler.
The MC3870 timer is 8 bits with a decimal prescaler.

SPECIAL FUNCTIONS -

Various members of the MCU families include additional
1/0 functions. For example, the MC6801 Family includes a full 8-bit UART with baud rate
generator on-chip. A 4-channel 8-bit AID converter is included on a few M6805 Family
versions. The digital portion of an RF frequency synthesizer is added to an M6805 Family
member.

DEVELOPMENT SUPPORT - All three families are fully supported on the EXORciser
development system. Included are assemblers, keyboard debugging including breakpoints,
user system emulation, and stand-alone emulation. The M6801 Family has the added
benefit of various high level languages and compatibility with MC6800 programs.

THE CMOS M6805 COMPONENTS
Motorola offers an 8-bit CMOS processor in the MC146805E2. The CMOS portion of
the M6805 Family of 8-bit microprocessors, peripherals, and single-chip microcomputers
combines the low power characteristic of CMOS, with the application flexibility of the
M6800 Family.
1-6

The M6805 Family has evolved from the M6800 Family. The M6805 Family includes similar
programmable bidirectional I/O, flexible memory organization, many memory reference
instructions, interrupts, and multi-level subroutine nesting. ROM use efficiency, bit manipulation instructions, and improved table look-up indexing are M6805 Family enhancements
of the M6800 heritage.
The benefits of CMOS are added to Motorola's microprocessor repertoire. low operating
power and even lower standby power consumption permit battery operation, cut cooling
costs, and reduce power supply expense. The wider operating voltage range of CMOS
offers higher noise immunity and easier switching to standby power. Static CMOS parts
permit true standby operation plus power optimization with lower frequencies and voltages.

PROGRAMMING - The enhanced M6800 architectural features make the M6800 Family
easy to program. The stack pOinter permits up to 32 subroutine levels. Three ROM-efficient
indexed addressing modes allow for look-up tables anywhere in memory. Any I/O pin or
RAM bit may be modified with a single instruction. A branch may be taken depending upon
the bit state of any I/O pin or RAM bit with only a single instruction. RAM, ROM, and I/O
registers are all accessed with the same powerful memory addressing instructions. An
efficient instruction set permits programs to be written faster, more easily optimized, and,
therefore, more reliable.
INTERRUPTS - Real-time applications require sensing, measuring, and controlling
system events. Five vectored interrupts, which stack the program registers, are included
in M6805 Family processors to implement these applications. For time dependent tasks,
a programmable 8-bit counter generates an interrupt when zero is reached. The timer
includes a program-selectable 7-bit prescaler and a software selectable input. The timer
input may be an external signal for pulse width measurement, or the on-chip oscillator. An
external interrupt pin is also provided. Software techniques for external eventsynchronization are not needed.
MOTEL - The MOTEL concept (for MOtorola and InTEL bus compatibility) allows both
types of processors to be interchanged on a bus without changing the design of the
peripheral/memory system. The MOTEL circuit automatically detects which type of processor is connected, and interprets the bus control signals appropriately. The MCM65516
2K CMOS ROM, MC146818 Real-Time Clock plus RAM, and MC146823 Parallel Interface
incorporate the MOTEL concept to provide a high degree of system flexibility.
SINGLE-CHIP CMOS MICROCOMPUTERS - Dedicated single-chip MCUs are also
included in the M6805 Family. The MC146805F2 has 1K byte of on-chip ROM, while the
MC146805G2 has a 2K ROM. The MC146805G2 also includes 112 RAM bytes, 32inputl
output lines, programmable timer, external and timer interrupts, and high current output
pins. The 1K MC146805F2 has the same interrupt features but fewer I/O lines, 28 pins,
and less RAM, 64 bytes. The MC146805E2 microprocessor serves as the ROM-less
prototyping part for both single-chip MCUs. The MC68HC05C4 has 32 I/O lines and 176
bytes of RAM. The MC68HC11A4 has AlD,512 bytes of EEPROM, 256 bytes of RAM
and 40 I/O lines. The MC68HC04P2 has 32 bytes of RAM and 20 I/O lines.

PERIPHERALS - Two types of CMOS peripherals are being added to Motorola's CMOS
family. Parallel bus-oriented peripherals support microprocessors such as the MC146805E2,
1-7

I

I

while single-chip microcomputers are supported by port-oriented 1/0, usually using serial
data transfer. The MC146823 Parallel Interface offers three 8-bit ports (24 lines) of digital
interfacing, including port latch control signals, to multiplexed-bus microprocessors such
as the MC146805E2. The MC146818 Real-Time.Clock plus RAM relieves the processor
of maintaining the time and date, generates timed interrupts, and includes 50 bytes of
CMOS RAM. Program memory is provided by the completely bus compatible MC65516
2K CMOS ROM. Other support circuits include LCD drivers (MC145000, MC145001,
MC144115, and MC144117), LED drivers (MC14499 and MC144100), DIA converters
(MC144110 and MC144111), AlDsubsystem (MC14443 and MC14447), latches (MC14099,
MC14597, MC14598, and MC14599), remote 1/0 (MC14469) and frequency synthesizers
(MC14156 and MC145144).

POWER SAVINGS - Energy efficiency is, of course, the chief CMOS attraction. CMOS
MPUs are seriously considered anywhere a battery is used, whether it be the primary or
a back-up power source. The operating current can be orders-of-magnitude lower. Standby
modes can have power usages order-of-magnitude lower yet. Since the M6805 Family is
static in design, low-speed operating current is extremely low.

STATIC DESIGN - The clock of a static CMOS microprocessor may be at any frequency
below the specified maximum. CMOS users frequently lower the frequency, to conserve
power, approaching the point where the processor is fully loaded during the worst-case
program cycle. A static MPU allows operation at 1 kHz or 10kHz· in applications where
battery drain is critical, and the workload light. A static processor can also be stopped
during any cycle without losing any volatile information, which assures extremely low
standby current.

PROGRAM CONTROL OF POWER -

Typical CMOS microprocessor applications
require considerable attention to minimizing power consumption. The M6805 and M6804
Families of CMOS processors include program control of power usage, as well as the
traditional external power optimizing tools. The program may initiate either of two standby
modes, called Stop and Wait, which halt program execution. The external or timer interrupts
automatically turn the processor back on to allow execution to resume. Why not save
power when the program has no work to do? The program can be restarted when there
is work that needs doing. Battery drain is the average of operating and standby current
for the average work duty cycle.

LOW POWER DISSIPATION - A major side benefit of low power usage is that the
heat dissipated is also low. The costs of cooling equipment is not needed. Fan noise in
an office environment, as well as fan unreliability, need not be endured. Systems may be
enclosed in smaller housings. Air tight systems need not have special heat conducting
mechanisms.
WIDER VOLTAGE RANGE - The initial CMOS MPU products are characterized to
operate from 3.0 to 6.0 voltages. The voltage range is being extended to higher voltages
in upcoming versions. The wider voltage range permits lower cost power regulation, easier
switching to back-up sources,and lower cost batteries. The higher voltage parts add noise
immunity to the wide voltage range benefits.

1-8

SINGLE-CHIP MICROCOMPUTER FAMILIES FEATURES
SPECTRUMS
The following illustrations (Figures 1-2 through 1-5) represent the microcomputer families
and their features.

6804
CORE

FIGURE 1-2. M6804 FAMILY SPECTRUM
1-9

I

I

LEGEND
SPI = SERIAL PERIPHERAL
INTERFACE
SCI = SERIAL COMMUNICATION
INTERFACE
COP=COMPUTER OPERATING
PROPERLY

FIGURE 1·3. CMOS M680S AND CMOS M6804 SPECTRUM

1-10

I

LEGEND
B= BYTE
CHAN = CHANNEL
COP = COMPUTER OPERATING
PROPERLY
1/0 = INPUT OUTPUT
OSC SYN = OSCILLATOR
SYNTHESIZER
PLL = PHASE LOCK LOOP
SCI = SERIAL COMMUNICATION
INTERFACE
SPI = SERIAL PERIPHERAL
INTERFACE
8-BIT THP = 8-BIT TIMER HARDWARE
PRESCALER

FIGURE 1·4. M6805 FAMILY SPECTRUM

1-11

I

F

U
T
U
R

E

LEGEND
B=BYTES
STBY = STANDBY
CH =CHANNEL
SPI = SERIAL PERIPHERAL
INTERFACE
SCI = SERIAL COMMUNICATION
INTERFACE
COP = COMPUTER OPERATING
PROPERLY

FIGURE 1·5. M6801 FAMILY SPECTRUM

1-12

Reliability

2-1

I

RELIABILITY AND QUALITY
MONITOR REPORT
OCTOBER 1983

I
Introduction
Motorola conducts extensive reliability tests to qualify devices, to evaluate process and material
changes and to accumulate generic performance data. The results of these tests provide the basis
for production decisions and the generation of reliability reports for customer use. The following
report provides an overview of reliability testing on Motorola's MOS Microprocessor Components
conducted during 1982. Included in the report are summary results of dynamic life testing and thermal
performance testing for plastic and ceramic packaged devices, and moisture performance testing
for plastic parts. Results of the tests are detailed below.

Dynamic Life
Dynamic life, or high temperature operating life, is performed to accelerate failures resulting
from thermally activated defects. Failure mechanisms detected during life test include die related
defects which occur during wafer processing and both die and package related defects which occur
during assembly.
Stress is generated through the application of a 5 volt dynamic bias and an ambient temperature
of 125°C. A dynamic bias is considered more effective than static bias for LSI Microprocessor devices
because a large percentage of the chip can be continuously exercised. During life test, devices are
exercised using a common mid-range frequency clock signal which is typically 500KHz or 1MHz.
Devices are electrically tested after 1~'504, and 1008 hours using computer controlled testers
which employ functional patterns under w st-case supply and clock conditions. Pass/fail criteria are
established for each circuit type based on nctionality and data sheet limits for AC and DC parameters. Devices which fail to meet a test criterion are segregated by failure mode and data logged,
and failure analysis is performed, when appropriate, to establish associated failure mechanisms.
Life test failure rates are calculated using the Chi-Square distribution and a 90% confidence level
(see Appendix A). This 90% confidence level is more stringent than the 60% level used in the 1981
report. The accompanying increase in failure rates for individual device types is a result of tightening
the confidence level and does not indicate a reduction in the reliability of the devices. Tables 1 and
2 summarize the 1982 dynamic life test data for MOS Microprocessors.

Test results contained herein are for information only. This report does not alter
Motorola's standard warranty or product specifications.

2-2

TABLE 1.
SUMMARY OF DYNAMIC LIFE TEST RESULTS

70°C
Device
Type

Technology
NMOS

MC6800
MC681 0
MC6821
MC6822
MC6840
MC6844
MC6845
MC68652
MC68653
MC68661

TOTAL

HMOS

MC6801
MC6805P2
MC6805R2
MC6805U2
MC6809
MC68000
MC68008
MC68230
MC68451
MC68705P3

TOTAL

CMOS

MC141200
MC146805E2
MC146805G2
MC146818

TOTAL
GRAND TOTAL

* 90%

Test
Devices

125°C
Device Hours

Equivalent
Device Hours

Failures

Failure
Rate*
FITs

45
90
448
83
45
45
346
45
134
45

45,360
89,040
451,584
83,664
45,360
45,360
346,752
45,360
135,072
45,360

2.2 x 106
4.6x10 6
24.1 x 106
4.9 x 106
2.5 x 106
2.7 x 106
19.5 x 106
1.9 x 106
5.3 x 106
2.5 x 106

1,326

1,332,912

70.2 x 106

4

110

704
224
171
86
225
262
168
126
88
268

702,672
212,352
170,520
80,808
225,960
262,080
169,344
120,456
88,704
265,248

106
106
106
106
106
106
106
106
106
106

3
0
1
0
1

2

250
240
370
770
580
350
340
960
480
340

2,322

2,298,144

105.1 x 106

12

170

135
89
178
89

135,576
83,352
171,192
88,872

14.1 x 106
8.8x10 6
17.2 x 106
7.4 x 106

i

0
3
0

270
260
390
310

491

478,992

47.5 x 106

4

170

4,139

4,110,048

222.8 x 106

20

120

Confidence Level

2-3

27.1
9.7
10.1
3.0
6.3
15.0
6.8
7.0
4.8
15.3

x
x
x
x
x
x
x
x
x
x

0

2
0
0
0
0
2
0
0
0

2
0
3
0

1050
1150
100
470
920
860
270
1200
440
920

I

TABLE 2.
MICROPROCESSOR FAMILY DYNAMIC LIFE TEST RESULTS

Total
Devices

125°C
Device Hours

70°C
Equivalent
Device Hours

Failures

Failure Rate
FITs

*

WAFER PROCESS TECHNOLOGY

I

NMOS

1,326

1,332,912

HMOS

2,322

2,298,144

CMOS

491

478,992

x 106
105.1 x 106
47.5 x 106
70.2

4

110

12

170

4

170

PACKAGING SYSTEM TECHNOLOGY
Ceramic

1,875

1,858,176

Plastic

2,264

2,251,872

TOTAL

4,139

4,110,048

* 90% Confidence

x 106
118.5 x 106
222.8 x 106
104.3

12

170

8

110

20

120

Level

SUMMARY:
The overall life test results for 1982 show a very significant improvement over our 1981 data base
(Reliability Report 8238). For 1982 we tightened our confidence level from 60% to 90%. The failure
rate for 1982 was 120 FITs at a 90% confidence level as compared with 250 FITs at 90% confidence
level for 1981. The major effect of tightening the confidence level from 60% to 90% is to increase
the predicted failure rate of individual devices with limited device hours. For example, the predicted
failure rate for the MC6800 using 60% confidence is 420 FITs. The predicted failure rate for this
same device using the 90% confidence is 1050 FITs, or more than double. This makes a statistically
significant comparison of the individual device failure rates very difficult. It is more beneficial to
examine the failure rate of the process technologies (NMOS, HMOS, CMOS) or the packaging
technologies (plastic and ceramic) in which there are a considerable number of device hours which
reduce the impact of the confidence level change. Even with the statistical tightening for 1982, the
process and package technologies have achieved a reliability improvement as measured by dynamic
life test when compared with the 1981 data base.

Plastic Package Environmental Performance
The use of plastic encapsulation for packaging of integrated circuits has met with widespread
customer acceptance throughout the semiconductor industry because it is lighter, less expensive,
and more resistant to physical damage than ceramic packaging. However, there are several reliability
concerns in plastic packages: contamination, moisture resistance, wirebond integrity, and thermal
performance. Dynamic life test results show no significant difference between plastic and ceramic
device performance; this demonstrates that Motorola's careful selection of materials and rigid control
of processes has eliminated any plastic-related performance degradation. The following section
addresses the other reliability concerns of plastic parts: corrosion, wirebond integrity, and thermal
performance.

2-4

Moisture Related Performance
In plastic integrated circuits, moisture present in the package can cause an increase in the corrosion
rate of the die metallization, if ionic contaminants are present, resulting in failures when the device
is in use. Moisture may reach the interconnect metallization along the leadframe-molding compound
interface or through the bulk of the plastic. The combination of moisture, ionic contaminants carried
in with the moisture or present in the plastic, and an electric field creates an electrolytic cell which
becomes a corrosion site.
To help prevent corrosion problems, Motorola uses a molding compound which forms a compressive bond around the leadframe which, when cured, produces a tight seal to minimize microgaps.
Tighter control of contamination sources throughout the manufacturing process, improvements in
passivation and improved metallization techniques have resulted in lower defect density and more
complete passivation coverage, keeping moisture from penetrating to the die surface.
Two accelerated tests are used by Motorola to assess the level of performance achieved by the
combined application of these corrosion-prevention measures: Autoclave and Temperature Humidity
Bias (T.H.B.). 1982 moisture performance test results are detailed below.

Autoclave
Autoclave testing uses a combination of temperature, humidity, and pressure to accelerate moisture
ingress along the leadframe-molding compound interface path. The absence of a bias keeps device
power dissipation from acting as a moisture barrier, increasing the probability that moisture will reach
the die if a part is defective.
Autoclave test conditions include 121°e, 100% relative humidity and 15 psig. Each test sample
is selected from a separate assembly lot and subjected to a minimum of 96 hours of stress; complete
parametric and functional tests are performed on all devices at each read pOint. In addition, some
devices are stressed for an additional 48 hours. All electrical failures are included in the data base,
not only those associated with corrosion on the die. Autoclave test results for ~ 982 are summarized
in Table 3.

TABLE 3.
AUTOCLAVE TEST RESULTS
121°C
100% R.H.
15 psig

48

96

144

Failures/Sample "

6/3083

1/3076

2/1399

Percent Defective

0.19

0.03

0.14

Cumulative Percent Defective

0.19

0.22

Hours

I

0.36

Temperature Humidity Bias
Temperature Humidity Bias (T.H.B.) testing is used to evaluate the moisture resistance of plastic
devices by employing the severe conditions of 85°e, 85% relative humidity, and 5 volts to accelerate
corrosion of the metallization. The biasing circuits used in TH.B. testing create static electric fields
between adjacent pins and metallization stripes, maximizing the effect of electrolytic cells while
minimizing the power dissipation. A typical TH.B. biasing scheme would include: all I/O or output
pins either open or with resistive terminations; enable pins are disabled; and all other pins have
alternate VDD and VSS on adjacent pins. As with autoclave, the expected failure mode is corrosion
of the die metallization.

2-5

I

Each TH.B. sample is sourced from a separate assembly lot and tested fora period of 1008
hours. Complete parametric and functional test programs are typically performed at the 168. 504,
and 1008 hour read points using computer controlled testers. The pass/fail criteria used for life test
are also employed with T.H.B. samples. A worst-case analysis is presented since all electrical failures
are considered instead of only those associated with corrosion mechanisms. Results for 1982 are
summarized in Table 4.

I

TABLE 4.
TEMPERATURE HUMIDITY BIAS TEST RESULTS
85°C
85% R.H.
5.0 VOLTS

Hours

168

504

1008

2/1456

4/1796

5/1781

Percent Defective

0.14

0.22

0.28

Cumulative Percent Defective

0.14

0.36

0.64

Failures/Sample

A Weibull plot (Figure 1) shows the continued improvement in T.H.B. performance as measured
in 1979, 1980, 1981 and 1982.

50.0

..,.1"...... -1"'"

10.0
5.0
1979

Q)

.2
'u..ro

1.0

E
Q)

0,5

(.)

CD

a..

l---'--

----- -

~-~

0.1
0.05

0.01

...--

,.",,-

-----

~

-

1980

........

..........

-

1981

-"""""- -"""
_

....

--

..
"".."

""..--

~-

-

-

.,....

.".,.

.".,.-

.".,.
~

.,....

.".,.

... ""- ... ~

---

100II

~
~

~

1982

I

I

168

336

504

1008
Test Time in Hours

10 K

FIGURE 1. WEIBULL PLOT OF TEMPERATURE HUMIDITY BIAS TEST RESULTS

2-6

Thermal Cycling Performance
Thermal cycling accelerates the stressing effects of thermal expan~ion mismatch between the
various components of the plastic and ceramic packaging systems through rapid successive eX
cursions to high and low temperature extremes. Temperature cycle and thermal shock are two tests
which are used to determine the effects of these stresses on package integrity, especially wire bond
and die bond integrity. These types of failure modes follow the classical wearout mechanism pattern
(Le. an increasing failure rate with increased cycles of exposure.)
m

Temperature Cycle
The integrity of wire bonds and die bonds in plastic packages can be accurately evaluated through
temperature cycle testing. Military Standard 8838, Method 1010.4, Condition C is employed to
permit easy comparison of results with other industry sources.
Devices are inserted into the cycling system and held at - 65°C for at least ten minutes. Following
the cold dwell, devices are heated to 150°C during a transition time of five minutes maximum, after
which devices dwell at 150°C for a minimum of ten minutes. They are then cooled during a similar
transition period to - 65°C after which the cycle is repeated. The system employs a circulating air
environment to assure rapid stabilization at the specified temperature, The dwell at each extreme,
plus the two transition times, constitutes one test cycle (approximately 30 minutes).
Electrical measurements and high temperature continuity tests are typically performed after 100,
500 and 1000 cycles. The predominant failure mechanism in the ceramic packaged product is wire
bond breakage above the ball near the die where the heat and stress of the bonding process reduce
the strength of the wire. The predominant temperature cycle activated failure mechanisms in plastic
encapsulated circuits are die lift and die crazing/cracking due to inadequate die wetting/curing and
mold compound stresses on the die, respectively. Results of the test are shown in Table 5.

TABLE S.
TEMPERATURE CYCLE TEST RESULTS
- 6SoC to + 1S0°C
AIR TO AIR
Cycles

Failures/Sample

100

SOO

1000

7/3103

5/3081

8/3050

Percent Defective

0.23

0.16

0,26

Cumulative Percent Defective

0.23

0.39

0.65

Thermal Shock
Thermal shock is an environmental test performed in accordance with Military Standard 8838,
Method 1011.3, Condition C. The objective of this test is the same as that for temperature cycle
- to emphasize differences in expansion coefficients for components of the packaging system.
However, thermal shock provides a more severe stress than temperature cycle in that the devices
are exposed to a more sudden change in temperature due to the higher thermal conductivity and
heat capacity of the liquid ambient
Devices are placed in a fluorocarbon bath cooled to - 65°C. After being held in the cold chamber
for at least five minutes, the sample is transferred in less than ten seconds to an adjacent chamber
filled with fluorocarbon at 150°C and held for an equivalent time. The dwell time at each endpoint,
plus the total transition time, constitutes one test cycle (approximately ten minutes). Thermal shock
endpoint electrical measurements and high temperature continuity tests are typically performed
at 100, 500, and 1000 cycles. Results of thermal shock tests performed in 1982 are shown in
Table 6.

2-7

I

TABLE 6.
THERMAL SHOCK TESTS RESULTS
- 65°C TO + 150°C
LIQUID TO LIQUID
Cycles

I

100

500

1000

Failures/Sample

1/941

1/967

9/955

Percent Defective

0.11

0.10

0.94

Cumulative Percent Defective

0.11

0.21

1.15

Conclusions
Reliability testing performed by Motorola MaS Microprocessor Division during 1982 has produced
excellent results. The specific test results included in this report are representative of Motorola MaS
Microprocessor components expected field performance. Failure rate estimates have been based
on the outcome of tests and data analyses which are widely accepted. Life test failure rates on both
ceramic and plastic packaged devices are significantly reduced over those reported previously.
Moisture resistance testing indicates extremely high performance of Motorola MaS Microprocessor
plastic encapsulated circuits. Thermal integrity testing shows that there are few failures, which
typically occur only after extensive exposure to temperature extremes greater than those seen in
field applications. The level of performance predicted by these test results is among the best available
in the industry and far exceeds the requirements of most applications. Comparison to previous
reports (Reliability Report 8238) verifies a history of continuous improvement which has made
Motorola MaS Microprocessor components the optimum choice for reliable performance.
Copies of this and other reliability reports may be obtained from your local Motorola representative.
For additional information contact Microprocessor Reliability Engineering 512-928-6640 or write to:
MOS Microprocessor Reliability Engineering
Motorola Incorporated
3501 Ed Bluestein Blvd.
Austin, Texas 78721

2-8

APPENDIX A.
QUALITY AND RELIABILITY SYSTEM
A complete Reliability and Quality Assurance system is in place to monitor and control the performance of Motorola's MOS Microprocessor Components. Incoming Quality Control inspects starting
wafers, masks, chemicals, package piece parts and molding compounds. Process Engineering and
In-Process Quality Control perform step-by-step monitoring of the wafer process to check oxidation,
diffusion, photolithography, ion implantation, polysilicon deposition, metallization, passivation, and
other process operations. Final visual, class probe, and capacitance-voltage plots complete the wafer
area inspections. Environmental monitors are also performed for air cleanliness, water quality, temperature and humidity.
In the assembly area, In-Process Quality Control performs monitors on eqUipment performance
and gate inspections at the major process steps on all lots. The Outgoing Quality Control group
continues this philosophy in the final test area by performing electrical and visual-mechanical gates
on every lot. The electrical inspection, which consists of AC, DC and functional tests, is performed
to a 0.1 % (maximum) Acceptable Quality Level (AQL) sampling plan. The visual/mechanical inspection is also performed to a 0.1 % AQL sampling plan. Any lot which fails either of these gates
is returned to production for 100% rescreen. A Quality Engineering organization exists to approve
final test programs and support the Outgoing Quality Control organization. Test programs are tailored
to assure all required specifications are met or the devices are rejected.
The Reliability Engineering organization is responsible for performing qualifications of new deSigns
and process changes prior to introduction. In addition, Reliability Engineering establishes and maintains monitor programs to assure processes stay in control once they are qualified. Results from
these programs provide rapid feedback to correct problems as they occur.
Supporting these efforts is the Metrology Laboratory which includes both a Standards and a
Calibration Laboratory to provide National Bureau of Standards traceability to all production
measurements.
Also offering required support are a Chemical Laboratory with such equipment as a gas chromatograph/mass spectrograph and X-ray fluorescent systems for detailed incoming chemical analyses; a Surface Analysis Laboratory whose equipment includes a Scanning Electron Microscope
(S.E.M.) and a Scanning Auger Microprobe (S.A.M.); and a Product Analysis Laborabory for detailed
analyses of failure modes and mechanisms for Microprocessor devices.

2-9

I

III

I

MOS Reliability & Quality Assurance Operations

I

I

I

1

Microprocessor
Division
R&QA
Reliability Engineering
QA Engineering
QC Gate
Lot Processing
Burn-In

Memory
Operation
R&QA
Reliability Engineering
QA Engineering
QC Gate
Lot Processing
Burn-In

I

Logic and Special Functions
Operation
R&QA

I

Reliability Engineering
QA Engineering
QC Gate
Lot Processing
Environmental Laboratory

r;.>
.;...&.

o

I

R&QA
Technical
Services

I

I

R&QA
Business
Services

Wafer
Operation
R&QA

I

I

Product Analysis
Laboratory
Technical Writing
Statistical Training
Assembly R&QA
Engineering
Data Base Computer
System

Specifications
Metrology Laboratory
Warehouse Final
Inspection
Customer Notification
Returned Material

Wafer In Process QA
Wafer R&QA Engineering
Analytical Services

FIGURE A. RELIABILITY AND QUALITY ASSURANCE ORGANIZATION

APPENDIX B.
PACKAGING SYSTEMS
Motorola Microprocessor devices are produced in plastic, CERDIP and sidebraze packages. The
ceramic package types are hermetically sealed to protect the integrated circuit from environmental
factors and permit operation over extreme temperature ranges. Although plastic devices are not
hermetic, modern epoxies exhibit extremely high moisture resistance, and long lifetimes may therefore be expected from these devices in typical environments.

Plastic
In recent years, plastic encapsulated devices have gained widespread acceptance throughout the
electronics industry. Improvements in materials and process controls have resulted in significant
improvements in reliability performance. In addition, plastic packages have the advantage of low
cost and physical strength. Through careful selection of molding compound, leadframe material, and
assembly methods, Motorola produces plastiC packaged ICs with reliability suitable for nearly all
applications.
Encapsulated integrated circuits incorporate the simplest processing and package construction
of the various systems available. The die is attached to a leadframe, wire bonded and encapsulated
using an epoxy novolac molding compound. The die may be attached to the leadframe by epoxy
or by any of a variety of eutectic forming metal preforms. Wire bonding may be thermocompression
or thermosonic, but the wire is always gold. This system has evolved from early industry experiments
with aluminum ultrasonic wire bonding which experienced high rates of opens and intermittents. The
encapsulant is the most critical component of the system since it controls contamination, moisture
resistance, and stress effects. Epoxy novolacs have become the industry standard molding compound since they combine excellent characteristics in all these areas.
The plastiC package is, by far, the most resistant to physical damage since the die is completely
encapsulated and cavity hermeticity is not a concern. Since the package is light in weight and the
plastiC is less brittle than ceramic, chipping and cosmetic damage are not problems. The leadframe
and plating are equivalent to CERDIp, and modern epoxies pose no danger from contamination.
In comparing plastic to ceramic packages, there are two characteristics to be considered: moisture
resistance and thermal characteristics. Microprocessor plastic products perform very well on moisture
resistance related tests. This is due to advances in molding compounds, and the characteristic low
voltages and moderate power dissipation of Microprocessor products. In most instances, plastic
devices will provide excellent performance, essentially equivalent to hermetic performance. Thermal
resistance has been improved dramatically through the introduction of copper leadframes and heatspreaders. During 1982 and 1983, a large number of Microprocessor devices will be converted from
Alloy 42 to copper leadframes to take advantage of the better thermal conductivity of copper. This
results in lower junction temperatures, and subsequent improvements in electrical characteristics
and reliability performance.
Another approach to lower thermal resistance for devices with high power dissipation is plastiC
assembly using a heatspreader. The heatspreader is an anodized aluminum piece part that sits
below the plane of the leadframe. During the encapsulation process, the heatspreader is surrounded
by plastiC and becomes part of the package structure. Heatspreaders, when used in combination
with Alloy 42 leadframes, yield a thermal resistance roughly equivalent to a copper leadframe plastiC
device, or to a ceramic device. Devices which contain a heatspreader employ the suffix "G" to
designate this package type. The MC6801 Microprocessor Family has been offered in this package,
and the 64-pin MC68000 16-bit Microprocessor is being offered in a heatspreader package.

2-11

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The sidebraze, or solder seal, package is composed of three layers of alumina which are screened
with refractory metal such as tungsten or moly manganese and fired together to form the package
body with a cavity for the die. The refractory metal is then plated and Alloy 42 leadframes are brazed
to the bottom, sides or top of the package, depending on the vendor. The advantage of the sidebraze
version is accurate lead alignment without the need for forming. The final piece part operation is
plating which may be gold, or tin with a selective gold plate in the cavity. Although epoxy die bonding
is feasible in this package - due to the higher sealing temperature, most manufacturers, including
Motorola, employ a eutectic bond. Both aluminum ultrasonic wire bonding and gold thermocompression bonding are used.

2-13

I

I

Some tradeoffs exist in the performance characteristics of the two hermetic packages as they are
offered by Motorola. Both typically are ceramic, hermetic, employ a eutectic die bond, use ultrasonic
aluminum wire bonding, and have tin plating. The thermal resistance of the packages is very similar,
with the sidebraze having a slight advantage. Both packages perform well on the standard thermal
and mechanical environmental tests, but each is susceptible to handling damage. Loose shipping
rail packaging or high velocity impacts during testing can chip the sidebraze package and sever the
interlayer metallization. This type of handling will not affect the 1O-mil-thick leadframe of the CERDIP
package, but hermeticity failures can occur. The CERDIP package is slightly thicker and heavier, but
no conductive surfaces are exposed so the shorting potential in dense packaging is reduced. Extensive testing of 24, 28. and 40 lead CERDIP and sidebraze devices has indicated no significant
differences in reliability.
Some Microprocessor devices are now being offered in Leadless Chip Carriers (LCC). The primary
advantage of LCCs is increased device density at the board or substrate level. Motorola currently
uses a 40-pin LCC that is essentially identical to the sidebraze dual-in-line in construction characteristics and assembly methods. Some MC68000 16-bit family devices will be offered in higher
terminal count LCCs, up to 68 terminals. Future plans include LeCs with single layer construction
and other package types offering higher packing density at the system level.

2-14

APPENDIX C.
FAILURE RATE CALCULATIONS
Environmental tests are designed to measure device resistance to unusual and severe stress, not
expected under normal operating conditions. Device performance under these conditions is expressed as a percent of devices defective and compared to previous results. Life tests, on the other
hand, accelerate the use conditions of the device with temperature and voltage in a manner which
is more quantitatively correlatable to system operation. Life test failure rates are expressed as failures
per unit time and are calculated using established principles of probability and statistics.
The principles of reliability engineering have indicated that failure rates for semiconductor devices
will take the form of the "bathtub" curve (Figure C1).

2

o

1~________~~_____3_______

)

t~ I

FIGURE C1. DEVICE FAILURE RATE AS A FUNCTION OF TIME.

The following three regions are represented in the curve:
1 Infant Mortality - a region of high but rapidly declining failure rates, usually associated with
manufacturing defects.
<

2. Random Failures - a region of low, random failures caused by more subtle defects. This
area of the curve represents the useful part of device life.
3. Wearout - a region of rapidly rising failure rates related to device wearout. Most semiconductors will not reach this stage before they are replaced because of changes in technology.
Techniques for calculating life test failure rates assume that the devices being tested have passed
infant mortality and entered the stable random failure portion of the life curve. Failures which occur
in this area are few and are known to approximate specific probability distributions. These probability
distributions are used to calculate sample failure rates which can be projected to the population in
general through the application of confidence limits. Techniques used to calculate life test failure
rates for microprocessors are discussed below.
A failure rate for any sample of life tested devices can be determined by dividing the number of
failures by the number of device hours. However, this rate will apply to that sample only. If you are
interested in projecting from the sample to the populations in general, you must establish confidence
limits. The application of confidence limits is a statement of how "confident" you are that the sample
failure rate approximates that for the population in general. To obtain rates with different confidence
levels it is necessary to make use of specific probability distributions which take the same form as
the actual failure distribution.

2-15

I

It has been determined that failures in semiconductors that have entered the middle portion of the
bathtub curve will approximate a Poisson distribution; this distribution applies when one has a large
sample with an extremely small number of events of interest, such as device failures. Given a
Poisson. failure process, a Chi-Square distribution can be used to establish confidence limits for
failure rates. Reliability Engineering has determined that the following general formula, which utilizes
values from a Chi-Square table, can be used to calculate failure rates for semiconductors:

A

I

=

1 x 105
MTTF'

=

X2 (a, d.f.)
2t

(1 )

where:
A = Failure Rate, %/1000 Hours
MTTF = Mean Time To Failure (Hours)
x2 = Chi-Square Function
100 - Confidence Limit
a =
100

d.f. = Degrees of Freedom = 2r + 2
r = Number of Failures
t = Device Hours
To calculate the failure rate, first determine the level of confidence you require and calculate
degrees of freedom. Select the Chi-Square value from a Chi-Square distribution table with the
appropriate degrees of freedom and confidence level. Divide that value by twice the actual device
hours, at the temperature of interest.
The above formula applies for calculating a device failure rate, provided that the test is conducted
at system temperature. However, since we are unable to observe long-term effects which develop
over time, the test is accelerated through the application of a high temperature. In order to calculate
a failure rate at the ambient temperature of a system, a factor must be supplied to compensate for
the acceleration. The factor (Fa) which equates test temperature with rated temperature is derived
from the Arrhenius relationship:
Fa = exp ((elk) . (J..
Tr

-

J..))

Tt

(2)

where:
Fa = Acceleration Factor
Activation Energy, eV
k = Soltzman's constant, 8.62 x 10 -5 eV;oK
Tr = Junction Temperature, OK at the Rated Ambient of 70°C
Tt = Junction Temperature, OK at the Life Test Ambient of 125°C

e=

Motorola uses 70°C for the system temperature (To) to more closely approximate the actual temperature of the device during system operation and to supply a degree of conservatism to the failure
rate calculation.

2-16

Motorola uses an activation energy (8) value of 1.0 electron-volt. A 1.0 eV was selected as an
average value because a variety of different failure mechanisms exist for microprocessor and other
VLSI devices, with activation energies ranging from 0.40 eV for oxide related failures to 1.0 eV or
greater for contamination and metal related failures, Tr and Tt of the equation are the average
junction temperatures present at the rated and test ambients, Motorola uses junction, rather than
ambient temperature, because they produce acceleration factors that are more conservative and
representative of actual conditions. These temperatures are calculated as follows:

TJ = T A

+ Po 6JA
0

(3)

where:
TJ = Junction Temperature, °C
TA = Ambient Temperature, °C
Po = Average Power Dissipation, Watts
6JA = Thermal Resistance - Junction to Ambient, °C Per Watt
Once this step has been completed, the acceleration factor can be calculated and applied as a
multiplier to the number of device test hours under accelerated test conditions to determine the
equivalent number of hours at rated operating conditions. To determine the failure rate at the operating
temperature, use equation (1) substituting the equivalent device hours at rated temperature for t in
the equation ..
Formula 1 provides a failure rate expressed in percent per thousand hours. This number, stated
as a percentage per each thousand hours of operation, is one way Motorola Reliability Engineering
expresses failure rates for Microprocessors, One other way of expressing failure rates is Failures
In Time (FITs) which refers to failed units per 109 device hours (1 FIT = t.. x 104),
Mean Time To Failure (MTTF) is another parameter frequently used to express failure rates. MTTF
is the average time to a failure of a non-repairable item such as a semiconductor and is expressed
as the reCiprocal of the failure rate:
MTTF =

2-17

!

t..

(4)

I

APPENDIX D.
ELECTRICAL TESTING AND FAILURE CHARACTERISTICS

I

The electrical measurements performed on reliability test samples were obtained using computer
controlled testers and programs employing exhaustive functional routines under worst-case supply
and clock conditions. Devices which do not meet a test criterion, including those failing for parametric
reasons, are first segregated into "bin outs" defined by the test program. A data log is obtained from
which each failing device is then assigned to one of six failure mode categories. An analysis to
determine specific failure mechanisms is performed when the level or pattern of failure indicates
that it is appropriate. T.H.B. rejects are routinely decapsulated and inspected for corrosion of the
metallization.
The electrical test programs are typically constructed in the following manner:
1.
2.
3.
4.
5.

"Opens" test
"Shorts" test
Input Leakage
Functionality using nominal supply and input voltage levels and low frequency clock conditions
Functionality to data sheet parametric limits using worst-case combinations of VDO level and
clock frequency
6. Three-state leakage
7. Output buffer current drive capability
8. Power dissipation test
Failure modes categorized according to these tests do not always indicate a specific problem
and individual test programs may deviate from the sequence shown above as required for complete
testing of the specific device type. Microprocessors and other LSI logic circuits do not readily lend
themselves to the identification of failure modes since their complexity creates an astronomical
number of possible combination, some of which are very subtle. Attempts to categorize these
modes by the test sequence invariably result in groupings which are not mutually exclusive or
related to physical mechanisms.
The distribution of failure modes and mechanisms observed during life testing appears to be
the result of random manufacturing anomalies and does not, therefore, indicate trends correlatable
to specific process or design deficiencies. These results are consistent with careful attention to
process controls and reflect Motorola's high priority for quality and reliability.

TABLE 01.
FAILURE MODE CLASSIFICATION

A.

OPENS - No electrical connection between an external terminal and corresponding die
circuitry (possible intermitent). MOS inputs are normally high impedance parts and opens are
detected by forward-biasing the substrate diode.

B.

SHORTS - An unintended resistive path of relatively low value between one terminal and
any other terminal.

C.

FUNCTIONAL - A failure of one or more output terminals to respond with a correct logical
state under nominal supply, clock, and VIH/VIL levels; a violation of the internal Boolean
relationship defined by the circuit design.

D.

INPUT LEAKAGE - A current of either polarity which exceeds data sheet limits for input
terminals. Large values of leakage are classified as shorts.

E.

THREE-STATE LEAKAGE - A current of either polarity which exceeds data sheet limits for
I/O terminals when under three-stated conditions. This parameter is also timing dependent
and, when catastrophic, is classified as a functional failure mode.

F.

PARAMETRIC - A broad classification of non-catastrophic failure modes which excludes
leakages but includes:

1. Failure to respond at one or more output terminals with a correct logical state under worstcase supply, clock, and VIH/VIL conditions; usually the result of excessive propagation
delays, improper VOH/VOL levels, or a dynamic logic state which should be static, etc.
Must be 100% functional under nominal conditions and may be associated with leakage
currents not previously detected.
2. Excessive power dissipation. For CMOS Microprocessors, leakage currents can be a significant contributing factor for this failure mode. Device is 100% functional.
3. Incorrect output analog voltage or current level not resulting in a functional failure.

2-19

I

APPENDIX E.
MICROPROCESSOR AVERAGE JUNCTION TEMPERATURES
AND GATE COUNTS
Average Junction
Temperature @TA = 70°C
MOS

Technology
NMOS

I

HMOS

CMOS

NOTES:

Device
Type

Ceramic

Plastic
A42
Cu

83
91
83
79
85
89
89
83
81
83
89
85
86

92
116
92
92
103
105
109
94
92
91
101
98
106

81
88
90
91
84
85
84
91
86
88

85
99

102

91

MC6801
MC6805P2
MC6805R2/U2
MC6809/E
MC6829
MC68000
MC68008
MC68120
MC68451
MC68705P3
MC68705R3

95
88
82
92
92
97
107
96

96*
106
108
117
117
95*

97
95
87
96
96

MC141000
MC141200
MC146805E2
MC146805F2
MC146805G2
MC146823

71
71
71
71
71
71

MC6800
MC6802/08
MC6810
MC6821
MC6844
MC6845
MC6846
MC6847
MC6850
MC6852
MC6854
MC68488
MC68652
MC68653
MC68661
MC68701

88
89

*

Plastic package with molded-in heatspreader.
A42 Plastic package with Alloy 42 leadframe.
Cu Plastic package with copper leadframe.

2-20

72
72
72
72
72
72

Equivalent
Number of
Gates
1,367
3,633
1,083
450
1,000
750
3,755
833
580
907
1,400
893
6,442
3,200
4,200
11,267
8,533
4,833
6,430
3,000
3,293
12,667
12,667
9,644
12,233
8,833
14,433
2,425
2,425
4,333
5,633
5,800
867

APPENDIX F.
RELIABILITY AND QUALITY MONITOR PROGRAM
The Motorola MOS Microprocessor Reliability and Quality Monitor Program is designed to generate
an ongoing data base of reliability and quality performance for various categories of Microprocessor
products. The primary purpose of the program is to identify negative trends in the data so that
immediate corrective action can be taken. The program also allows Motorola to develop a large data
base of reliability and quality results that can be reported quarterly to customers.
For the reliability monitor tests, each quarter sample group is pulled from major categories of
product representing a matrix of processing and packaging technologies (see Sample Group chart).
Product mix, sample availability and equipment capacity may cause the specific sample group pulled
for a given quarter to vary from the chart shown. Each sample group has a specific set of reliability
tests associated with it that are appropriate for that product type based on our history for that
classification. At the end of each quarter, results are reported for all sample groups that have
completed testing.
The quality results that are reported are the electrical and visual/mechanical AOQ (Average
OutgOing Quality, given in parts per million defective) for the Microprocessor Division. This data
represents the summary of results from the QC gate operation performed on every lot during the
quarter. Electrical AOQ represents any AC, DC, or functional failure at any temperature (each lot
is typically gated at two temperatures: hot and either room or cold). Visual/mechanical AOQ represents failures such as bent leads, incorrect marking, marking permanency problems, and cracked
packages. The AOQ reported is the product of the process average (ratio of defective devices to
largest sample size) and the lot acceptance rate.
Following are brief descriptions of the various reliability tests included in this program:

High Temperature Operating Life
High temperature operating life (H,T.O.L.) testing is performed to accelerate failure mechanisms
which are thermally activated through the application of extreme temperatures and the use of dynamic
operating conditions. The temperature and voltage conditions used in the stress are typically 125°C
with a bias level at the maximum data sheet specification limit of 5.5 volts. All devices used in HTOL
test are sampled directly after final electrical test with no prior burn-in or other pre-screening. Testing
is performed per Mil Std 883B, Method 1005, with all stressing dynamic and minimum test duration
1008 hours. Some sample groups will be extended beyond 1008 hours, some run at temperatures
higher than 125°C, and some at voltages higher than maximum rated voltage to look for the effects
of these variations.
Device equivalent hours assume the Arrhenius relationship using an activation energy of 1.0 eV
to extrapolate from the device junction temperature at 125°C to the junction temperature at 70°C.
Failure rates given in FITs are derived using the Chi-Square distribution to a 90% confidence limit.
A FIT is 1 failure per 109 device hours or 0.0001 %/1 000 Hours.

Temperature Humidity Bias
Temperature Humidity Bias (T.H.B.) is an environmental test performed at a temperature of 85°C
and a relative humidity of 85%. The test is designed to measure the moisture resistance of plastiC
encapsulated circuits. A nominal voltage of 5 volts static bias is applied to the device to create the
electrolytic cells necessary to accelerate corrosion of the metallization. Testing is performed per
JEDEC Standard 22, Method A 101. Most groups are tested to 100 hours with some groups extended
beyond to look for longer term effects.

2-21

I

Autoclave
Autoclave, like T.H.B., is an environmental test which measures device resistance to moisture
penetration along the leadframe-plastic interface. Conditions employed during the test include 121°C,
100% relative humidity, and 15 psig. Corrosion of the die is the expected failure mechanism. Autoclave
is a highly accelerated and destructive test performed per JEDEC Standard 22, method A 102. Testing
is routinely performed for 144 hours.

Temperature Cycle

I

Temperature cycle testing accelerates the effects of thermal expansion mismatch among the
different components within a specific packaging system. This test is typically performed per Mil
Std 8838, Method 1010, Condition C ( -- 65°C to + 150°C), or JEDEC Standard 22, Method A 104,
Condition 8 (-40°C to + 125°C). During temperature cycle testing, devices are inserted into a
cycling system and held at the cold dwell temperature for at least ten minutes. Following this cold
dwell, the devices are heated to the hot dwell where they remain for another ten minute minimum
time period. The system employs a circulating air environment to assure rapid stabilization at the
specified temperature. The .owe II at each extreme, plus the two transition times of five minutes each
(one up to the hot dwell temperature, another down to the cold dwell temperature), constitute one
cycle. Test duration is for 1000 cycles with some tests extended to look for longer term effects.

Thermal Shock
The objective of thermal shock testing is the same as that for temperature cycle testing - to
emphasize differences in expansion coefficients for components of the packaging systems. However,
thermal shock· provides additional stress in that the device is exposed to a sudden change in
temperature due to the transfer time of ten seconds maximum as well as the increased thermal
conductivity of a liquid ambient. This test is performed per Mil Std 8838, Method 1011, Condition
C (- 65°Cto + 150°C). Devices are placed in a fluorocarbon bath and cooled to - 65°C. After being
held in the cold chamber for five minutes minimum, the devices are transferred to an adjacent
chamber filled with fluorocarbon at + 150°C for an equivalent time. Two five-minute dwells plus two
ten-second transitions constitute one cycle. Test duration is normally for 1000 cycles with some tests
being extended to look for longer term effects.

Data Retention
Data retention testing or high temperature storage is performed to measure the stability of programmed EPROM and EEPROM devices during storage at elevated temperatures with no electrical
stress applied. The devices are exposed to an ambient environment of 150°C per Mil Std 8838,
Method 1008, Condition C. An acceleration of charge loss from the storage cell is the expected
result. All groups are typically tested to 1008 hours.

2-22

RELIABILITY AND QUALITY MONITOR PROGRAM
SAMPLE GROUPS

Category
Name

Typical
Product
Types

Minimum Number of
Sample Groups/Qtr

NMOS
Plastic

6800 Family
3870, 6800, 6810
6821, 6845, Custom

8

HMOS
Plastic

6801 Family
6805 Family
6809 Family

4

CMOS
Plastic

CMOS Family
146805E2
14680SG2

4

68000
Family
Plastic
(HMOS)

68000

CERDIP
(NMOS or
HMOS)

6800 Family
3870,6800,6810,
6821, 6845', 6801,
6805, 6809

Side
Braze

6800 Family
3870, 6800, 6810
6821, 6845, 6810,
6805, 6809

Leadless
Chip
Carrier

146805E2
146805G2
CMOS Family

68000
Family
Ceramic
(HMOS)

68000

EPROM MCU
(NMOS. HMOS
or CMOS)

68701
68705
1468705G2

2

2

Test Performed
No. Samples

(Typ.)

HTOL
THB
Autoclave
TCITS

45
34
22
38

Pes
Pes
Pes
Pes

HTOL
THB
Autoclave
TCITS

45
34
22
38

Pes
Pes
Pes
Pes

HTOL
THB
Autoclave
TCITS

45
34
22
38

Pes
Pes
Pes
Pes

HTOL
THB
Autoclave
TCITS

45
36
38
38

Pes
Pes
Pes
Pes

HTOL
TCITS

45 Pes
38 Pes

TCITS

52 Pes

HTOL
TCITS

30 Pes
38 Pes

HTOL

45 Pes

HTOL
TCfTS
Data
Retention

45 Pes
38 Pes

2

3

2

2

2-23

45 Pes

I

APPENDIX G.
QUAUTYPERFORMANCE

II

The chart below gives the goals and actuals for the Microprocessor Division Electrical and Visual/
Mechanical AOa (Average Outgoing auality, given in parts per million defective). This data represents
the summary of results from the ac gate operations performed on every lot. Electrical AOa represents any AC, DC, or functional failure at any temperature (each lot is typically gated at two
temperatures: hot, and either room or cold). Visual/Mechanical AOa represents failures such as bent
leads, incorrect marking, marking permanency problems, and cracked packages. The AOa reported
is the product of the process average (ratio of defective devices to largest sample size) and the lot
acceptance rate.
AVERAGE OUTGOING QUALITY

Goal

Electrical
AOQ (PPM)
Actual
(-)
(-)

4000
2000
1725

Visual/Mechanical
AOQ (PPM)
Actual
(-)
(-)

Total 1979
Total 1980
Total 1981

3000
2500
1500

1st atr 1982
2nd atr 1982
3rd atr 1982
4th atr 1982

1200
1000
800
600

1045
868
492
636

1408
1934
1062
651

1st atr 1983
2nd atr 1983
3rd atr 1983
4th atr 1983

500
450
400
350

326
341
313

405
267
251

1st Half 1984
2nd Half 1984

275
275

1st Half 1985
2nd Half 1985

175
125

1986

100

2-24

4500
2500
1920

Data Sheets

3-1

I

I

3-2

®

MC1372

MOTOROLA

COLOR TV
VIDEO
MODULATOR CIRCUIT

COLOR TV VIDEO MODULATOR

SILICON MONOLITHIC
INTEGRATED CIRCUIT

· .. an integrated circuit used to generate an R F TV signal from
baseband color·difference and luminance signals.
The MC1372 contains a chroma subcarrier oscillator, a lead and
lag network, a quasi·quadrature suppressed carrier DSB chroma
modulator, an RF oscillator and modulator, and an LSTTL com·
patible clock driver with adjustable duty cycle.
The MC1372 is a companion part to the MC6847 Video Display
Generator, providing and accepting the correct dc interconnection
levels. This device may also be used as a general·purpose modulator
with a variety of video signal generating devices such as video games,
test equipment, video tape recorders, etc.
•

Single 5.0 Vdc Supply Operation for NMOS
and TTL Compatibility

•

Minimal External Components

, , _ PSUFFIX
PLASTIC PACKAGE
CASE 646-05

Pin ConnecHons

•

Compatible with MC6847 Video Display Generator

•

Sound Carrier Addition Capability

•

Modulates Channel 3 or 4 Carrier with Encoded Video Signal

•

Low Power Dissipation

Clock
Output
Oscillator
Input

Duty Cycle
Adj

•

Linear Chroma Modulators for High Versatility

•

Composite Video Signal Generation Capability

•

Ground-Referenced Video Prevents Overmodulation

VCC
Color B
Input
Color Ref
Input

Chrominance
Input
Luminance
Input

Color A
Input

Chroma
Modulator
Output

FIGURE 1 - BLOCK DIAGRAM

Color B

Luminance
Input

Input

VCC

RF
Modulator
Output

11

Oscillator

Chrom inance

Input

Input
Chrominance

Oscillator

....--..., • ..---t----+--Vl0
O.l/.1 F

V5

3-5

V6

V7

V9

..
FIGURE 4 -

(")
~

Oscillator

Clock

Luma

Chrominance

R F Modulator

RF

Adjust

Input

Driver

Input

Input
10

Output
12 (

Tank

11
VCC

s:

SCHEMATIC DIAGRAM

Duty Cycle

1·

2

9Q

139

W
.....

914

N

o-__~~------~------------.---------~--~~-------.--+--.--__-+------~~----~--------__-+----~~~~~--,
R5
4.7 k

~II

04
20 k
R8

~ R'K
20 k

I

500

~05
R9

11 k

01

R2
25k

~~

~R12

02
.;r

R7
3.6k

Dl

Rl0

R25 :> R26:>

U'l

R27

a:

4

~--~~.---~------~~~~--------~--------~-+--~--~----~~----~--------~----------~--~~--

VJ

__-+-OGround
1-

0>
R50

c

R31

R28
'V

~ if2fR':' I I Jo ~~

8 Chroma

~Modulator

-1

C4

R51~

C2

r~
C'

;:PM

ow

TM

Output

032

It

Q~t

R39

o~

1 k

036

034

R33

R34

R35

R48
3.4 k

033
R38

R52

R44

3.4 k

I

R37

:L'
Color B
Input

fR45

R46

Color Reference

Input

R47

Color A
Input

MC1372

OPERATIONAL DESCRIPTION
Pin 1 - Clock Output
Provides a rectangular ptilse output waveform with
frequency equal to the chrominance subcarrier oscillator.
This output is capable of driving one LS-TTL load.
Pin 2 - Oscillator Input
Color subcarrier oscillator feedback input. Signal from
the clock output is externally phase shifted and ac coupled to this pin.
Pin 3 - Duty Cycle Adjust
A dc voltage applied to this pin adjusts the duty cycle
of the clock output signal. If the pin is left unconnected,
the duty cycle is approximately 50%.

Pin 11 - VCC
Positive supply voltage
Pin 12 - R F Modulator Output
Common collector of output modulator stage. Output
impedance and stage gain may be selected by choice of
resistor connected between this pin and dc supply.
Pins 13 and 14 - RF Tank
A tuned circuit connected between these pins determines the R F oscillator frequency. The tuned circuit must
provide a low dc resistance shunt. Applying a dc offset
voltage between these pins results in baseband composite
video at the R F Modulator Output.
MC1372 CIRCUIT DESCRIPTION

Pin 4 - Ground
The chrominance oscillator and clock driver consist of
emitter follower 04 and inverting amplifier 05. Signal
presented at clock driver output pin 1 is coupled to
osci:lator input pin 2 through an external RC and crystal
network, which provides 180 0 phase shift at the resonant
frequency. The duty cycle of the output waveform is
determined by the dc component at pin 1 internally
coupled through R12 to the base of 04. As pin 1 dc
voltage increases, a smaller portion of the sinusoidal
feedback signal at pin 2 exceeds the 04 base voltage of
two times VBE required for conduction. As the dc level
is reduced, device 04 and thus 05 is turned on for a
longer percentage of the cycle. Transistors OQ, Ql,
02 and diode Dl provide the biasing network which
determines the dc operating level of the oscillator. The
transistor 02 and resistors R5, R6, and R 7 form a voltage
reference of four times VBE at the collector of 02. The
dc voltage at pin 1 is determined by the values of R4,
R8, and R12 and the applied duty cycle adjust voltage
at pin 3. Since these resistors are nominally equal, the
voltage at pin 1 will always approximate the dc voltage
at pin 3.
The oscillator signal at pin 1 is internally coupled to
active filter 044. This filter reduces the frequency content
above 4 MHz. The output of the filter at the emitter of
044 is ac coupled through C3 to the input of the lead/lag
network. R32 and Cl provide approximately 50 0 of phase
lag, while C2 and R29 provide approximately 50 0 of
phase lead. These two quasi-quadrature waveforms are
used to switch chroma modulators B and A, respectively.
The transistors 022 through 025 and 032-033 form
a doubly balanced modulator. The input signal applied
at pin 5 is compared to the color dc reference voltage
applied at pin 6 in differential amplifier 032-033. The
source current provided by transistor 034 is partitioned
in transistors 032 and 033 according to the differential
input signal. The bases of transistors 023 and 024 are
connected to the dc reference voltage at the emitter of
030. The bases of transistors 022 and 025 are connected

Pin 5 - Color B Input
Dc coupled input to Chroma Modulator B, whose
phase leads modulator A by approximately 1000. The
modulator output amplitude and polarity correspond to
the voltage difference between this pin and the Color
Reference Voltage at Pin 6.
Pin 6 - Color Reference Input
The dc voltage applied to this Pin establishes the
reference voltage to which Color A and Color B inputs
are compared.
Pin 7 - Color A Input
Dc coupled input to Chroma Modulator A. whose
phase lags modulator B by approximately 1000. The
modulator output amplitude and polarity correspond to
the voltage difference between this pin and the Color
Reference Voltage at Pin 6.
Pin 8 - Chroma Modulator Output
Low impedance (emitter follower) output which
provides the vectorial sum of chroma modulators A
and B.
Pin 9 - Luminance Input
Input to R F modulator. This pin accepts a dc coupled
lum inance and sync signal. The ampl itude of the R F signal
output increases with positive voltage applied to the pin,
and ground potential results in zero output (i.e., 100%
modulation). A signal with positive-going sync should
be used.
Pin 10 - Chrominance Input
Input to the R F modulator. Th is pin accepts ac coupled
chrominance provided by the Chroma Modulator Output
(pin 8). The signal is reduced by an internal resistor divider
before being appl ied to the R F modulator_ The resistor
divider consists of a 300 ohm series resistor and a 500
ohm shunt resistor. Additional gain reduction may be
obtained by the addition of external series resistance
to pin 10.

3-7

I

MC1372

associated equipment. The duty cycle may be adjusted
by varying the dc voltage applied to pin 3. This adjust·
ment may be made with the use of a potentiometer
(10 kst) between supply and ground. With no connection
to pin 3, the duty cycle is approximately 50%.

to the phase delayed oscillator signal at the emitter of
buffer transistor 021. The differential signal currents
provided by 032 and 033 are switched in transistors
Q22 through 025 and the resultant signal voltage is
developed across R49. This signal has the phase and
frequency of the oscillator signal at the emitter of 021.
The amplitude is proportional to the differential input
signal applied between pins 5 and 6. Transistors 026
through 029 and 038-039 form chroma modulator B.
This modulator develops a signal voltage which is propor·
tional to the differential voltage appl ied between pins
7 and 6. The phase and frequency of the output is equal

Chroma Modulator
The chrominance oscillator is internally phase shifted
and applied to chroma modulators A and B. No external
lead/lag networks are necessary. The phase relationship
between the modulators is approximately 100 0 , which
was chosen to provide the best rendition of colol's using
equal amplitude color·difference signals. The voltage
applied to pin 5,6, or 7 must always be within the Input
Common Mode Voltage Range. Since the amplitude of

to the phase advanced chroma oscillator at the emitter
of buffer transistor 020. Both chroma modulators A and

I

B share the same output resistor, R49, so the output
signal presented at the emitter of 042 (pin 8) is the
algebraic sum of modulators A and B.
The

chrominance output is proportional to the voltage difference between pins 5 and 6 or 7 and 6, it is desirable
to select the Color Reference Voltage applied to pin 6 to
be midway between V5 max and V5 m in (which should

RF oscillator consists of differential amplifier

018 and 019 cross-coupled through emitter followers
016 and 017. The oscillator will operate at the parallel

be V7 max and V7 m in). The Chroma B Modulator will be
defined as a (B·Y) modulator if a burst flag signal is
applied to the Color B Input (pin 5) at the appropriate
time. This voltage should be negative with respect to the
Color Reference Voltage, and typically has an amplitude
equal to 1/2[V6-V5m i n J. Since the phase of burst is
always defined as -(B-Y), the Chroma A Modulator
approximates an (R,Y) modulator; however, the phase
is offset by 10 0 from the nominal 90 0 , to provide the
1000 phase shift as discussed previously.

resonant frequency of the network connected between
pins 13 and 14. The oscillator output is used to switch
the doubly balanced RF modulator, 09 through 015.
Transistors 07 and 08 provide level shifting and a high
input impedance to the luminance input pin 9. The
bases of transistors 09 and 010 are both biased through
resistors R 17 and R 18, respectively, to the same dc
reference voltage at 06 emitter. The base voltage at 010
may only be offset in a negative direction by luminance
signal current source 08. This design insures that overmodulation due to the luminance signal will never occur.
Thechrominance signal developed at pin 8 is externally

R F Modulator and Oscillator
The coil and capacitor connected between pins 13 and
14 should be selected to have a parallel resonance at the
carrier frequency of the desired TV channel. The values
of 56 pF and 0.1 )1H shown in Figure 5 were chosen
for a Channel 4 carrier frequency of 67.25 MHz. For
Channel 3 operation, the resonant frequency should
be 61.25 MHz (C = 75 pF, L = 0.1 )1H). Resistors R4 and

ac coupled to pin 10 where it is reduced by resistor
dividers R20 and R17, and added to the luminance
signal in 09. The resultant differential composite video
currents are switched at the appropriate R F frequency
in 012 through 015. The output signal current is presented

R5 are chosen to provide an adequate amplitude of
switching voltage, whereas R6 is used to lower the maximum dc level of switching voltage below VCC, thus
preventing saturation within the IC.
Composite Luminance and Sync should be de coupled
to Luminance Input, pin 9. This signal must be within
the Luma Input Dynamic Range to insure linearity.
Since an increase in dc voltage applied to pin 9 results
in an increase in R F output, the input signal should
have positive-going sync to generate an NTSC compatible
signal. As long as the input signal is positive, overmodulation is prevented by the integrated circuit.
Chrominance information should be ac coupled to
Chrominance Input, pin 10. This pin is internally connected to a resistor divider consisting of a series 300
ohms and a shunt 500 ohms resistor. The input impedance
is thus 800 ohms, and a coupling capacitor should be
appropriately chosen.

at pin 12.
Transistors 036, 041 and resistors R44, R47 provide
a highly stable voltage reference for biasing current sources
043,034,035, and 011.

MC1372 APPLICATION INFORMATION
Chrominance Oscillator
The oscillator is used as a clock signal for driving
associated external circuitry, in addition to providing a
switching signal for the chroma modulators. The IC uses
an external crystal in a Colpitts configuration, as shown
in Figure 5. Resistor R 1 provides current limiting to
reduce the signal swing. Capacitor C2 is adjusted for
the exact frequency desired (3.579545 MHz).
In some applications, the duty cycle of the clock signal
at pin 1 must be modified to overcome gate delays in

3-8

MC1372

FIGURE 5 - TYPICAL APPLICATION CIRCUIT

r---------------------------~e_--------e_--------e_~

+5Vdc

C5

0001

In

RF
Output

I
C3

R2

01

750

tage at pin 12 is high enough to prevent the output
devices from reaching saturation (approximately 4.5 V
with components in Figure 5). The peak current out of
pin 12 is typically 2 mAo Hence, a load resistance of up

The Luminance to Chrominance ratio (L:C) may be
modified with the addition of an external resistor in series
with pin 10 (as shown in Figure 5). The unmodified L:C
(Ao) is determined by the ratio of the respective Conver·
sion Gain for equal amplitude signals (typically, 0.883 =
-1.6 dB). The modified L:C will be governed by the
equation Ao(l + R ext /800) for equal amplitude input
signals.

to 250 ohms may be safely used with a 5 \, supply.
Composite Video Signal Generation
The R F modu lator may be easi Iy used as a composite
video generator by replacing the R F oscillator tank
circuit with a diode as shown in Figure 3. This results in
the output modulator being biased so the summation of
luminance and chrominance appears unswitched at
pin 12. The polarity of the output waveform is controlled by the direction of the diode. Inverted video:
Anode to pin 14, cathode to pin 13. Non·inverted
video: Anode to pin 13, cathode to pin 14. Note that the
supply resistor must always be connected to the anode
of the diode.
The amplitude of signal may be increased by increasing
the load resistor on pin 12 and returning it to a higher
supply voltage. Any voltage up to the Absolute Maximum

The internal chrominance modulators are not inter·
nally connected to the RF modulator; therefore, the user
has the option of connecting an externally generated
chrominance signal to the RF modulator. In addition,
the RF modulator is wideband, and a 4.5 MHz FM audio
signal may be added to the chrominance input at pin 10.
This may be accomplished by selecting an appropriate series
input resistor to provide the correct Lumi nance :Sound
ratio.
The modulated RF signal is presented as a current
at R F Modulator Output, pin 12. Since this pin represents
a current source, any load impedance may be selected for
matching purposes and gain selection, as long as the vol-

Rating may be used.

3-9

MC1372

RECOMMENDED CHROMA-LUMA SIGNALS

I

Applications with MC6847 Video Display Generator
The MC1372 may be easily interfaced to the MC6847
as shownin Figure 5. The dc levels generated and required
by the VDG are compatible with the MC1372, so that
pins 1, 5, 6, 7, and 9 may be directly coupled to the
appropriate MC6847 pi ns. Both integrated circuits as
well as any associated NMOS MPU may be driven from
a common 5 Vdc supply.

Pin ;t9
Luminance
Input
(Vdc)
Sync

Recommended Chroma-Luma Signals
A chroma modulation angle of 1000 was chosen to
faciltate a desirable selection of colors with a minimum
number of input signal levels. The following table demonstrates applicable signal levels for a variety of colors.

3-10

~7

Pin #6

Pin #5

Color A
(Vdc)

Color Ref.
(Vdc)

Color B
(Vdc)

Pin

1.0

1.5

1.5

1.5

Blanking

0.75

1.5

1.5

1.5

Burst

0.75

1.5

1.5

1.25

Black

0.70

1.5

1.5

1.5

Green

0.50

1.0

1.5

1.0

Yellow

0.38

1.5

1.5

1.0

Blue

0.62

1.5

1.5

2.0

Red

0.62

2.0

1.5

1.5

Cyan

0.50

1.0

1.5

1.5

Magenta

0.50

2.0

1.5

2.0

Orange

0.50

2.0

1.5

1.0

Buff

0.38

1.5

1.5

1.5

®

MC3440A
MC3441A
MC3443A

MOTOROLA

QUAD INTERFACE

QUAD GENERAL-PURPOSE INTERFACE
BUS (GPIB) TRANSCEIVERS

BUS TRANSCEIVERS
SI LICON MONOLITHIC
INTEGRATED CIRCUITS

The MC3440A, MC3441 A, MC3443A are quad bus transceivers
intended for usage in instruments and programmable calculators
equipped for interconnection into complete measurement systems.
These transceivers allow the bidirectional flow of digital data and

P SUFFIX

PLASTIC PACKAGE
CASE 648-05

commands between the various instruments. Each of the transceiver
versions provides four open-collector drivers and four receivers
featuring input hysteresis.
The MC3440A version consists of three drivers controlled by
a common Enable input and a single driver without an Enable input.
Terminations are provided in the device.
The MC3441A differs in that all four drivers are controlled by

Output and
Term ination
Gnd
Bus A
Receiver
Output A

the common Enable input. Again, the terminations are provided.
The MC3443A is identical to the MC3441A except that the terminations have been omitted. As such it is pin compatible, and
functionally equivalent to the SN75138. It does offer the advantage
of receiver input hysteresis.
•

Receiver Input Hysteresis Provides Excellent Noise Rejection

•

Open-Collector Driver Outputs Permit Wire-OR Connection

•

Tailored to Meet the Standards Set by the IEEE and IEC
Committees on Instrument Interface (488-1978)

•

Terminations provided (except MC3443A version)

•

Provides Electrical Compatibility with General-Purpose
I nterface Bus

Input Voltage
Oliver Output Current

Operating Ambient Temperature Range

Enable E
Driver
Input 0
Receiver
Output 0

Output and
Termination

Unit

7.0

Vdc

VI

5.5

Vdc

IOID}

150

mA

830
6.7

o to

Vee

Gnd

Value

T stg

e

Bus 0

VCC

TA

Storage Temperature Range

e

Driver
Input B

Bus B

Symbol

Po

Power DiSSipation (Package Limitation)
Derate above 25°C

Receiver
Output
Driver
Input

Receiver
Output B

MAXIMUM RATINGS ITA = 25°C unless otherwise noted}
Rating

e

Driver
Input A

Bus A

Power Supply Voltage

Vee
Bus

mW
mW/oC

00

-65 to +150

°c

Receiver
Output A
Driver

Input A
Driver
Input B
Receiver
Output B

Bus B

Bus

e

Receiver
Output

e

Driver
Input C

Enable E
Driver
Input D

Receiver
Output 0

°c
Bus 0

TYPICAL APPLICATION - GPIB MEASUREMENT SYSTEM
Output Gnd
Bus A

Instrument
A
(with GPIB)

Receiver
Output A
Programmable
Calculator
(with GPIB)

- T - = Bus
Termination
16 Lines Total

3-11

Bus

e

Receiver
Output

e

Driver
Input A

Driver
Input

Driver
Input B

Enable E

Receiver
Output B

Instrument
B
(with GPIB)

Vce

e

Driver
Input D
Receiver
Output 0

I

MC3440A, MC3441A, MC3443A

ELECTRICAL CHARACTERISTICS

(Unless otherwise noted, 4.5
TA = 250 C, VCC = 5.0 V)

v.;; VCC';; 5.5 V and 0';; TA';; 70 0 C, typical values are at

Characteristic

Symbol

Min

Input Voltage - High Logic State

VIH(D)

2.0

-

-

V

Input Voltage - Low Logic State

VIL(D)

-

-

0.8

V

lnpu! C-urrent
High Logic State
(VIH = 2.4 V)

IIHID)

-

-

40

iJ A

IILID)

-

-

-1.6
-0.25

mA

VIK(O)

-

-

-1.5

V

VOH(D)

2.5

-

-

V

Typ

Max

Unit

DRIVER PORTION

Input Current - Low Logic State
(VIL

= 0.4

V. Vce

= 5.0

V. TA

MC3443A
MC3440A,3441A

= 25 0 C)

I nput Clamp Voltage
(lIK=-12mA)
Output Voltage - High Logic State (1)
(VIH(E)
2.4 V or VIL(D)
0.8 V)

=

(MC3440A, 3441 A only)

=

Output Voltage - Low Logic State

(VIH(D)
(VIH(D)

I

= 2.0 v. VIL(E) = 0.8 v.

=

2.0

V, VIL(E)

=

0.8

V

VOL(D)

IOL(D)

v. IOL(D)

=
=

-

-

-

-

0.5
0.80

IOH(DI

-

-

250

iJ A

48 mAl
100 mAl

Output Leakage Current - MC3443A Only
(VIH(EI = 2.0 V Or VIL(D) = 0.8 \/1
RECEIVER PORTION

-

400

580

-

mV

VILH(RJ

0.8

0.98

-

V

Input Threshold Voltage - High to Low Output Logic State

VIHL(RI

-

1.56

2.0

V

(VCC = 5.0 V, TA = 25 0 C)
Output Voltage - High Logic State

VOH(R)

2.4

-

-

V

VOL(RI

-

-

0.5

V

IOS(RI

-20

-

-55

mA

2.50

-

-1.5
3.70

0.7

-

-

-1.3

-

-

-

2.5
-3.2
+0.04

Input HysteresIs
Input Threshold Voltage - Low to High Output Logic State
(VCC = 5.0 V, TA = 25 0 CI

(VIL(RI = 0.8 V. IOH(R) = -400"AI
Output Voltage - Low Logic State
(VIH(RI

=

2.0

v.

IOL(RI = 16 mAl

Output Short·Ctrcuit Current
(VIL(R) = 0.8 V) (Only one output may be shorted at a tIme)
BUS TERMINATION PORTION (Does not apply to MC3443A)
Bus Voltage (VIL(D) = 0.8 V)
(lBUS = -12 mAl
(No Load)

VBUS

Bus Current

IBUS

(VIL(O) = 0.8
(VIL(O) = 0.8
(VIL(O) = 0.8
(VCC = 0,0';;

V, VBUS;;' 5.0 V)
V. VBUS';; 5.5 V)
V, VBUS = 0.5 V)
VBUS';; 2.75 V)

V

mA

(MC3440A, 3441 A only)

TOTAL DEVICE POWER CONSUMPTION
Power Supply Current
(VIH(D)

= 2.4

V. VIL(E)

=0

VI

SWITCHING CHARACTERISTICS

(VCC = 5.0 V. TA

= 250 CI

Characteristic
DRIVER PORTION
Propagation Delay Time from Driver Input to Low Logic State Bus Output

tPHL(DI

-

13

30

-

13

25

Propagation Delay Time from Driver I nput to High Logic State Bus Output

tPLH(01

-

17

30

-

17

25

ns

Propagation Delay Time from Enable Input to Low Logic State Bus Output

tPHL(E)

25

40

-

25

32

ns

Propagation Delay Time from Enal!JJll nput to High Logic State Bus Output

tPLH(EI

-

25

40

-

25

32

ns

RECEIVER PORTION
Propagation Delay Time from Bus I nput to High Logic State Receiver Output
Propagation Delay Time from Bus Input to Low Logic State Receiver Output
(1) 12 k resistor from the bus terminal to VCC required on the MC3443A version.

3-12

ns

MC3440A, MC3441 A, MC3443A

FIGURE 1 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
RECEIVER INPUT (BUS) TO OUTPUT
To Scope
(Output) +5.0 V
Input

50%

To Scope
(Input)

OV

VOH
Output

---3(

t PLH (R)

1.5 V

15 pF

VOL--------'------------------J

or equiv

Input

Pulse

I

FIGURE 2 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
DRIVER AND COMMON ENABLE INPUTS TO OUTPUT (BUS)

OV
To Scope
(Input)

3.0 V

tv

VOH
Output
VOL

50%

50%

Pulse

OV

Input
VOH
Output
VOL

p,v

FIGURE 3 - TYPICAL RECEIVER HYSTERESIS
CHARACTER ISTICS
50
f------- -

~
~
~

40

I
Vee = 5.0 V
TA = 25 0 C

--+----+----+----+-----+----1

f..----+---+-----+-----H---+----I---+--+----i

30 I----+--+_---+----+-t--+_---+-±--t----j
2.0 I----+--+_---j---t-"/'---+----t--t---t----j

f:::J

o

~ 1.0~·-~--+_---j---~-_+---t-_t_--t-----j
~--r--.-

OL-_-L____L -__- L_ _ _L -__- L_ _ _L -_ _- L_ _~

o

1.0

0.5

VI. INPUT VOLTAGE (VOLTS)

3-13

1.5

2.0

1.5 V

C'

MC3440A, MC3441A, MC3443A

GENERAL PURPOSE INTERFACE BUS APPLICATION
INSTRUMENT B

INSTRUMENT A

-----

MC3441A

l

--

I
I

:
r
I

0102

0102

I

0103

0103

I

REN

~

I

0104

(Always
Enabled)

I

0106 )

-,

0105

I

I

0107 )

0106

I

0108

SRO

)

"-

I
I

(Always
Enabled)

I
I

I
MC3441 A

1
I

REN

I

EOI

IFC

,-I

E

~

EOI

,)

(Always

I

I
I
I
I
I
I

Instruments

)

To
Lo gic (Typical)

I

Enabled)
(Always
(Always

Enabled)

Enabled)
SRQ)

,

ATN

OAV)

IFC

NRFO

NRFO

NOAC

NOAC

MC3440A

I

I

0108

OAV

ATN )

I
I
~

'-

I

I

)

44-

0107

'-

I

MC3440A

)

'-

I

I

MC3440A

I

1
I
I
~

I

I

I

I

I
I

0104

I

MC3441A

-

I

01051

I

----

I

0101

I
I

I

1-

0101

I

I

--

J-I

MC3440A

2j

I
I

4-2+I
I

I

MC3440A

I
----

--- -- ~

~

16 Lines
Total

I
L

I
-- --

GPIB SIGNALS
8 Line Data Bus:

0101 -

0108

5 General Interrupt Transfer Control Bus:
REN - Remote Enable
SRO --' Service Request
EOI - End or Identify
ATN - Attention
I FC - I nterface Clear

3-14

3 Data Byte Transfer Control Bus
OAV - Data Valid
N R F 0 - Not Ready for Data
NOAC - Not Data Accepted
16 Total Signal Lines

®

MC3446A

MOTOROLA

QUAD GENERAL-PURPOSE INTERFACE
BUS (GPIB) TRANSCEIVER

QUAD INTERFACE
BUS TRANSCEIVER

The MC3446A is a quad bus transceiver intended for usage in
instruments and programmable calculators equipped for interconnec-

SILICON MONOLITHiC
INTEGRATED CIRCUIT

tion into complete measurement systems. This transceiver allows the
bidirectional flow of digital data and commands between the various
instruments. The transceiver provides four open-collector drivers and
four receivers featuring hysteresis.
•

Tailored to Meet the IEEE Standard 488-1978 (Digital Interface
for Programmable Instrumentation) and the Proposed IEC
Standard on Instrument Interface

•

Provides Electrical Compatibility with General-Purpose Interface
Bus (GPIB)

•

MaS Compatible with High Impedance Inputs

•

Driver Output Guaranteed Off During Power Up/Power Down

•

Low Power - Average Power Supply Current ~ 12 mA

•

Terminations Provided

I
P SUFFIX
PLASTIC PACKAGE

CASE 648-05

l

PIN CONNECTIONS
TYPICAL MEASUREMENT SYSTEM APPLICATION
Receiver

....

VCC

Output A
Receiver
Output D

Bus A

- - -,
Instrument

I

A
(with GPIB)

I

I

w

Enable
ABC

~

Driver
Input B

~-.

Instrument
B
(with GPIB)

Driver
Input A

J

Program ma ble
Calculator
(with GPIB)

I

Input D
Enable D
Driver
Input C

Bus B

I

Receiver
Output B

Bus C

.....

~

----

•
- T - == Bus Termination

3-15

Driver

u>

Gnd

16 L inas Total

Bus D

Receiver
Output C

MC3446A
MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)

Rating

Symbol

Value

VCC

7.0

Vdc

VI

5.5

Vdc
mA

Power Supply Voltage
Input Voltage

Unit

Driver Output Current

10(0)

150

Junction Temperature

TJ

150

°c

Operating Ambient Temperature Range

TA

o to +70

°c

T stg

-65 to +150

°c

Storage Temperature Range

ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, 4.5 V ~ VCC ~ 5.5 V and 0 ~ T A ~ 70 0 C, typical values are at T A = 25 0 C, VCC = 5.0 V)
Character istic

Symbol

Min

Typ

Max

Unit

DRIVER PORTION

I

Input Voltage - High Logic State

VIH(D~

-

-

V

Input Voltage - Low Logic State

VIL~D)

-

-

0.8

V

Input Current - High LOijic State
(VIH = 2.4 V)

IIH(D)

-

5.0

40

",A

Input Current - Low Logic State

IIL(D)

-

-0.2

-0.25

mA

Input Clamp Voltage
(lIK=-12mA)

VIK(D)

-

-

Output Voltage - High Logic State (1)

VOH(D)

2.5

VOL(D)
IIB(D)

2.0

(VIL = 0.4 V, VCC = 5.{)V, TA = 250 C)
-1.5

V

3.3

3.7

V

-

-

0.5

-

-

1.0

mA

(VIH(S) = 2.4.Vor VIH(D) = 2.0 V)
Output Voltage - Low Logic State
(VIL(S) = 0.8 V, VIL(D) = 0.8 V, IOL(D) ~ 48 mAl
Input Breakdown Current
(VI(D) = 5.5 V)
RECEIVER PORTION
-

400

625

-

mV

Input Threshold Voltage - Low to High Output Logic State

VILH(R)

-

1.66

2.0

V

Input Threshold Voltage - High to Low Output Logic State

VIHL(R)

0.8

1.03

V

Output Voltage - High Logic State

VOH(R)

2.4

-

-

Output Voltage - Low Logic State
(VIL(R) = 0.8 V, IOL(R) = 8.0 mAl

VOL(R)

-

-

0.5

V

Output Short·Circuit Current
(V I H (R) = 2.0 V) (Only one output may be shorted at a time)

IOS(R)

4.0

-

14

mA

3.3

3.7
-1.5

Input Hysteresis

V

(VIH(R) = 2.0 V,IOH(R) = -400 ",A)

BUS LOAD CHARACTERISTICS
Bus Voltage

(VIH(E) = 2.4 V)
(IBUS = -12 mAl

V(BUS)

2.5

Bus Current

(VIH(O)= 2.4 V, VBUS;,<5.0 V)
(VIH(D) = 2.4 V, VBUS = 0.5 V)
(VBUS ~ 5.5 V)

I(BUS)

0.7
-1.3

(VCC

= 0,0

V
mA

-3.2
2.5

V ~ VBUS ~ 2.75 V)

0.04

TOTAL DEVICE POWE R CONSUMPTION
Power Supply Current
(All Drivers OFF)
(All Drivers ON)

SWITCHING CHARACTERISTICS

(VCC = 5.0 V, TA = 25 0 C)

Characteristic
DRIVER PORTION
Propagation Delay Time from Driver Input to Low Logic State Bus Output

tPHL(D)

-

-

50

ns

Propagation Delay Time from Driver Input to High Logic State Bus Output

tPLH(D)

-

-

40

ns

Propagation Delay Time from Enable Input to Low Logic State Bus Output

tPHL(E)

-

50

ns

Propagation Delay Time from Enable Input to High Logic State Bus Output

tPLH(E)

50

ns

RECEIVER PORTION
Propagation Delay Time from Bus Input to High Logic State Receiver Output
Propagation Delay Time from Bus Input to Low Logic State Receiver Output

3-16

_.
-

MC3446A

FIGURE 1 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
RECEIVER INPUT (BUS) TO OUTPUT
To Scope
(Output)
Input

+5.0 V

To Scope

ov

(Input)

Output

2.4 V
Input

Pulse

I

FIGURE 2 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
DRIVER AND COMMON ENABLE INPUTS TO OUTPUT (BUS)

To Scope

.5.0 V

(Input)

r-

VOH-~-lI

Pulse

F

Output

50PF

1

Input

1.5 V

VOL----·

* Includes Probe and Jig Capacitance

FIGURE 4 - TYPICAL BUS LOAD LINE

FIGURE 3 - TYPICAL RECEIVER HYSTERESIS
CHARACTER ISTICS
5.0

~

60

I
1 - - - 1 - Vee = 5.0 V -+--+---+--t---+-----i
TA = 25 0 e

4.0

1-1--r--i-~==+=::;jjjH==+==:::j

;;:

~ 3.0

z
1---.

::>

>

::>

2.0 ~-_+--~-+_-H--+_-_+--+_-__l

~

::>

~

J

20

I

.§
>--

2:

~
>--

I

4.0

10

~-_+--f-----1I--_+_+_-_+--+_-_+-___1

~~

20

f
I
I
I
I

-4.0
-6.0
-8.0
10
12

OL-__-L____L -__J -__~~--~--~~--~--~

o

0.5

1.0

1.5

14
-4.0

20

J

Non-Shaded Area

-

eonf~r~~ ~~ ~~~raph

_

Standard 488-1978

_

I I

3-17

I

I

J
-2.0

2.0
VBUS. BUS VOLTAGE (VOLTS)

Vi. INPUT VOLTAGE !VOL TS)

~~

I

4.0

6.0

®

MC3447

MOTOROLA

BIDIRECTIONAL INSTRUMENTATION
BUS (GPIB) TRANSCEIVER
This bidirectional bus transceiver is intended as t~e interface
between TTL or MOS logic and the IEEE Standard Instrumentation
Bus (488-1978, often referred to as GPIB). The required bus termination is internally provided.

OCTAL BIDIRECTIONAL
BUS TRANSCEIVER
WITH
TERMINATION NETWORKS
SILICON MONOLITHIC
INTEGRATED CIRCUIT

Low power consumption has been achieved by trading a minimum
of speed for low current drain on non-critical channels. A fast

I

channel is provided for critical ATN and EOI paths.
Each driver/receiver pair forms the complete interface between
the bus and an instrument. Either the driver or the receiver of each
channel is enabled by a Send/Receive input with the disabled output
of the pair forced to a high impedance state. The receivers have
input hysteresis to improve noise margin, and their input loading

L SUFFIX
CERAMIC PACKAGE
CASE 623-05

follows the bus standard specifications.
Low Power - Average Power Supply Current

•
•
•
•
•
•
•
•
•

Eight Driver/Receiver Pairs
Three-State Outputs
High Impedance Inputs
Receiver Hysteresis - 600 mV (Typ)
Fast Propagation Times - 15-20 ns (Typ)
TTL Compatible Receiver Outputs
Single +5 Volt Supply
Open Collector Driver Output with Terminations
Power Up/Power Down Protection (No Invalid
I nformation Transmitted to Bus)

•
•

No Bus Loading When Power is Removed From Device
Required Termi nation Characteristics Provided

MAXIMUM RATINGS (T A

P3 SUFFIX

= 30

•

mA Listening
75 mA Talking

PLASTIC PACKAGE
CASIi 724-02

PIN ASSIGNMENTS

= 25°C unless otherwise noted)

Rating
Power Supply Voltage

Symbol

Value

VCC

7.0

Vdc

VI

5.5

Vdc

Input Voltage

Unit

Driver Output Current

10(0)

150

rnA

Junction Temperature

TJ

150

Operating Ambient Temperature Range

TA

o to +70

T stg

-65 to +150

°c
°c
°c

Storage Temperature Range

-

llnstrument

A

I

(With GPIS)

I

- --

TYPICAL MEASUREM ENT
SYSTEM APPLICATI ON

--~~

/

~
'",
.. mm.," :
,
Calcu lator
I

Instrument
S
(With GPIB)

I

------16 Lines Total

Vee

(With GPIS)

--F-O Bus

- Indicates

~us

~

Gnd

~ Termin.tions

MC3447
E lECTR ICAl CHARACTER ISTICS
(Unless otherwise noted 4 50 V<, VCC <,550 V and 0 <, T A <, 70 0 C· typical values are at T A = 25°C VCC = 5 0 V)
Characteristic - Note 2

Symbol

Min

Typ

Max

(Bus Pin Open)(VI(S/R) = 0.8 V)
(I(Bus) = -12 rnA)

V(Bus)
VIC(Bus)

2.5

-

3.7
-1.5

Bus Current
(5.0 V <, V (Bus) <, 5.5 V)
(V(Bus) = 0.5 V)
(VCC = 0 V, 0 V <, V(Bus) <, 2.75 V)

I(Bus)
-

Bus Voltage

Unit
V

-

rnA
0.7
-1.3

Receiver Input Hysteresis

-

-

-

2.5
-3.2
+0.04

400

600

-

-

1.6
10

mV

(VI(SIR) = 0.8 V)
Receiver Input Threshold

V
Low to High
High to Low

(VI(S/R) = 0.8 V)
Receiver Output Voltage - High Logic State

VILH(R)
VIHL(R)

0.8

VOH(RI

2.4

2.0
-

-

-

V

-

0.5

V

-20

mA

(VI(S/R) = 0.8 V, 10H(R) = -200 !lA, V(Bus) = 2.0 V)
Receiver Output Voltage - Low Logic State

VOL(R)

-

(VI(S/R) = 0.8 V, 10L(R) = 4.0 mA,(V(Bus) = 0.8 V
Receiver Output Short Circuit Current
(V I(SIR) = 0.8 V, V (Bus) = 2.0 V)

10S(R)

-4.0

-

Driver Input Voltage - High Logic State

VIH(D)

2.0

-

-

V

-

0.8

V

(VI(SIR) = 2.0 V)
Driver Input Voltage - Low Logic State

VIL(D)

-

(VI(S/R) = 2.0 V)
Driver Input Current - Data Pins

!lA

(VI(S/R) = 2.0 V)
(0.5 <, VI(D) <, 2.7 V)
(VI(D) = 5.5 V)

II(D)
IIB(D)

-100

-

..

-

II(S/RI
IIB(SIR)

-250

-

20
100

VIC(D)

-

-

-1.5

VOH(D)

2.5

-

-

V
V

40
200

I nput Current - SendlReceive

!lA

(0.5 <, VI(S/R) <, 2.7 V)
(Vl(sfRl = 5.5 V)
Driver Input Clamp Voltage

-

V

(VilS/R) = 2.0 V, IIC(D) = -18 mAl
Driver Output Voltage - High Logic State
(VIS/R) = 2.0 V, VIH(D) = 2.0 V)
Driver Output Voltage - Low Logic State (Note 1 )

VOL(DI

-

-

0.5

ICCL
ICCH

-

30
75

45
95

7.0
16

15
30

28
15

50
30

17
12

30
22

(VI(S/R) = 2.0 V, VILlD) =0.8 V, 10L(D) = 48 mAl
Power Supply Current
(Listening Mode - All Receivers On)
(Talking Mode - All Drivers On)

SWITCHING CHARACTERISTICS

(VCC

mA

= 5.0

V TA =

25 0 C

-

unless otherwise noted)

Propagation Delay of Driver
(Output Low to High)
(Output High to Low)

tPLH(D)
tpHL(D)

-

Propagation Delay of Receiver (Channels 0 to 5, 7)
(Output Low to High)
(Output High to Low)

tPLH(R)
tpHL(R)

-

Propagation Delay of Receiver (Channel 6, Note 3)
(Output Low to High)
(Output High to Low)

tPLH(R)
tPHL(R)

-

NOTES:

ns
-

ns

-

ns

-

1. The IEEE 488·1978 Bus Standard changes VOLlD) from 0.4 to 0.5 V maximum to permit the use of Schottky technology.
2. Specified test conditions for V /(S/R) are 0.8 V (Low) and 2.0 V (High). Where VI (SIR) is specified as a test condition, V I (SIR)
uses the opposite logic levels.
3. In order to meet the IEEE 488·1978 standard for total system delay on the ATN and EOI channels, a fast receiver has been
provided on Channel 6 (pins 9 and 16).

I

MC3447

SWITCHING CHARACTERISTICS (continued) (V cc = 50 V T A = 25 0 C unless otherwise noted)
Symbol

Min

Typ

Max

Propagation Delay Time - Send/Receiver to Data
Logic High to Third State
Third State to Logic High
Logic Low to Third State
Third State to Logic Low

tpHZ(R)
tpZH(R)
tpLZ(R)
tpZL(R)

-

15
15
15
10

30
30
25
25

Propagation Delay Time - Send/Receiver to Bus
Logic Low to Third State
Third State to Logic Low

tPLZ(O)
tpZL(D)

13
30

25
50

Characteristic

Unit
ns

--

ns

-

PROPAGATION DELAY TEST CIRCUITS AND WAVEFORMS
FIGURE 1 - BUS INPUT TO DATA OUTPUT (RECEIVER)

(Output)

r---------""'\

I

Input

To Scope

+ 5.0 V

3.0 V

\

1.5V

To Scope

~~L~R~

1 k

(!nput)

Output

lN916
or Equiv.
tTLH"tTHL'

5.0ns(10 90)

Duty Cycle .- 50%
Send/
Rec

Pulse

Generator

'I ncludes Jig
and Probe CapacItance

FIGURE 2 - DATA INPUT TO BUS OUTPUT (DRIVER)
3.0 V

To Scope
(Input)

To Scope
(Output) 3.0 V
Send/

Driver Input

or Enable

1.5 V

51
Bus

Pulse

Output
f=1.0MHz
-Includes Jig

tTLH = tTHL <;; 5.0 ns (10-90)

Clnd Probe Capdcitance

Duty Cycle = 50%

FIGURE 3 - SEND/RECEIVE INPUT TO BUS OUTPUT (DRIVER)
To Scope
(Output)

Pulse
51

'en"
-

Input
Output
Low to Open

3.0 V

f=1.0MHz

C L = 30 pF (Includes Jig and

tTLH = tTHL = <;; 5.0 ns (10-90)

Probe Capacitance

Duty Cycle = 50%

3-20

MC3447
FIGURE 4 - SEND/RECEIVE INPUT TO DATA OUTPUT (RECEIVER)
~------_·----3.0

V

Input

5.0 V

OV

To Scope
(Output)

1.2 k
Output

zl

High to Open
Output

600

Low to Open

2.0 V
51

Pulse

CL

~

15 pF (Includes Jig

f~1.0MHz

and Probe Capac itance)

tTLH ~ tTHL ~ .;; 5.0 ns (10-90)
Duty Cycle

FIGURE 5 - TYPICAL RECEIVER HYSTERESIS
CHARACTERISTICS
6.0

4.0 - f - TA = 25 0 C -+--+---+--+-+---+------1
;:j'

.5

~

'"

;

f-

3.0

~ -2.0

1----+--+----+---+----+---+--+------1--~_I

~

Cl

>

~

I

2.0

Cl

2.0

/~

-4.0

..---

I
,/'"

~ -8.0

~ 1.01----+--+----+--+__---+--+-+--+----1

-10

o

__

~_~

__

~_~

__

1.0

0.5

~_~_~

1.5

I

-14
-4.0

2.0

VI, INPUT VOLTAGE (VOLTS)

VBUS, BUS VOLTAGE (VOLTS)

FIGURE 7 - SUGGESTED PRINTED CIRCUIT BOARD LAYOUT USING MC3447s AND MC68488
10

MC68488

0

o

0
0
0
0
0
0
0
0

2 MC3447s

T~~s/f"v~,
T
~
'::-fi~
:~~,~~:

0

I

0

:

0-,' !
0

'!

0
0

4

0

5

0

SIR (5)

0
0
DAV

0-----/,---D

0--

0

0 - - D I 08

/

0

o--~~~

/

OS/R(1-4)-0---------0

::~j ~/I ~_S/_:_(6_)
---o---o~-~~~
W I
-o:-_S/_R_(7_)

DAC
RFD 0 - - - - - - - - '

:

SRQ~

0

REN

0

iFC

Gnd

Gnd

Gnd

~--~
Jumper or second

level metal

3-21

Gnd

-I--I--I---

r----I

4.0

2.0

-2.0

I

I

4881978
V CC = 5.0 V

-12
o~_~

---I

f...--

Non·Shaded Area
Conforms to
Paragraph 3·5.3 of
IEEE Standard

~ -6.0 I---

1----+~~-_t--_+--+__---+--+_+____+-___1

I

I

4.0

~ 5.0 V

VCC

50%

FIGURE 6 - TYPICAL BUS LOAD LINE

5.0 ,-----,----.-----,----.-----,---,--------,-----,

~

~

6.0

MC3447

FIGURE 8 - SIMPLE SYSTEM CONFIGURATION
<5 V

090

T/R 1

,...-------...,

I

I

I
I

OAV

2 MC3447s

00
Data

T/R 2
097

I
I
I

OAV

07

R/W

R/W

RS0

A0

MC6802

i""B0

0101

MC6800
RS2

MPU

Address

192

I

A15
0105

194

0107

196

IRQ

IRQ

NOAC

OAC

C/l

:l

[0

EOI

EOI

IFC

IFC

CO

"~

roCO
-

w

'"

~
>

2.0

>o

:::>

~ 1.0

~:~;~~;~etdo Area

~

Paragraph 3·5.3 of - i - - IEEE Standard
-~
488·1978
-f-Vee = 5.0 V

-8.0
-10

0.5

1.0

1.5

2.0

VI, INPUT VOLTAGE (VOLTS)

J

~ -6.0

-12

o
o

-14
-4.0

I
-2.0

2.0
VBUS, BUS VOLTAGE (VO LTS)

3-27

[

i--""""

/f..--::::

~ -4.0

o

5

...."....

~ -2.0

3.0

I
, -~ ~

I

:::r:

o

_

~

I
4.0

6.0

MC3448A

FIGURE 8 - SIMPLE SYSTEM CONFIGURATION
+5 V

DB¢

T/R 1

D¢
Data

T/R 2

I

EOI

EOI

SRQ

SRQ

DB7

07

R/W

R/W

RS¢

A.0

RS2

MC6802
OR
MC6800
MPU

Address

c

I

REN

REN

'" c

" <0
co:2

A15
IFC

IFC

1--------1
I

IRQ

ATN



t

Internal  clock

2tO

2tO

WRITE

tw

Internal WRITE Clock period

4t
6t

4t
6t

1/0

1000

0

1200

Notes

Short Cycle
Long Cycle
ns

50 pF plus
one TTL load

Output delay from internal WRITE clock

0

tsllO

Input setup time to internal WRITE clock

1000

tl/O-s

Output valid to STROBE delay

3t
-1000

3t
+250

3t
-1200

3t
+300

ns

1/01oad=
50 pF + 1 TTL load

tsL

STROBE low time

8t
-250

12t
+250

8t
-300

12t
+300

ns

STROBE load =
50 pF + 3 TTL loads

tRH

RESET hold time, low

6t
+ 750

6t
+1000

ns

power
supply
rise
time +0.1

power
supply
rise
time +0.15

ms

6t
+750

6t
+1000

ns

To trigger
interrupt

2t

2t

ns

To trigger timer

tdllO

STROBE

--

RESET

--

tRPOC RESET hold time, low for power clear

EXT INT

Unit

tEH

EXT INT hold time in active and inactive state

3-30

1200

ns

MC3870

DC CHARACTERISTICS (I/O Power Dissipation <
- 100 mW) INote 2)
Symbol
VCC

Ot070+C
Min
Max

Parameter
Power Supply Voltage

4.5

5.5

-40 to +85°C
Min
Max
4.75

5.25

Unit

Conditions

V

VIHEX

External Clock Input High Level

2A

VCC

2A

VCC

V

VILEX

External Clock Input Low Level

-0.3

0.6

-0.3

0.6

V

IIHEX

External Clock Input High Current

-

100

-

130

p.A VIHEX=2.40

IILEX

External Clock Input Low Current

-

-100

-

-130

p.A VILEX=O.60

2.0

VCC
13.2

2.2

Standard Pullup

2.2

VCC
13.2

V

2.0

V

Open Drain (1)

V

VIHI/O

Input High Level, I/O Pins

VIHR

Input High Level, RESET

2.0

VCC

2.2

VCC

VIHEI

Input High Level, EXT INT

2.0

VCC

2.2

VCC

-03

0.8
-1.6

-0.3
-

-1.9

mA VIN=OAV

+10
-5

-

+18
-8

p.A

VIL

Input Low Level

IlL

Input Low Current, All Pins with Standard Pullup Resistor

-

IL

Input Leakage Current, Open Drain Pins,
and Inputs with No Pullup Resistor

-

10H
10HDD
10HS

-

Output High Current Pins with Standard Pullup Resistor
Output High Current Direct Drive Pins

-100

-

-90

-

-1.5

-

-1.3
-

-

-

-300

STROBE Output High Current

-

0.7

-8.5

-11

-

-270

-

V

(1)
VIN= 13.2 V
VIN=0.2V

p.A VOH=2A V
mA

VOH=1.5V
VOH=0.7V

p.A VOH=2AV

Output Low Current

1.8

-

1.65

-

mA VOL =OA V

10LS

STROBE Output Low Current

5.0

-

4.5

-

mA VOL=OAV

ICC

Power Supply Current

-

85

-

110

mA Outputs Open

PD

Power Dissipation

-

400

-

525

mW Outputs Open

10L

1. RESET and EXT INT have internal Schmitt triggers giving minimum 0.2 V hysteresis.
2. Power dissipation for I/O pins is calculated bv EIVCC - VIL) (iIILI) = EIVCC - VOH)(IIOHIl = EIVOL)(lOL)

TIMER AC CHARACTERISTICS
Definitions:
Error = Indicated time value - actual time value
tpsc = t x Prescale Value
Interval Timer Mode:
Single interval error, free running INote 3) .
Cumulative interval error free running INote 3) .
Error between two Timer reads INote 2)
Start Timer to stop Timer error INotes 1,4)
Start Timer to read Timer error INotes 1,2).
Start Timer to interrupt request error INotes 1,3) ..
Load Timer to Stop Timer error INote 1)
Load Timer to read Timer error I Notes 1 , 2) .
Load Timer to interrupt request error INotes 1,3) .....

..................... ±6t
.. ... 0
± Itpsc+ tto - Itpsc + t to - Itpsc + 7t to -8t
+ t to - Itpcs + 2t ± to- Itpsc+8t to - 9t

Pulse Width Measurement Mode:
Measurement accuracy INote 4)
Minimum pulse Width of EXT INT pin.

+ t to - Itpsc + 2t

Event Counter Mode:
Minimum active time of EXT INT pin.
Minimum inactive time of EXT INT pin ..

. ....... 2t
....2t

NOTES:
1. All times which entail loading, starting, or stopping the Timer are referenced from the end of the last machine cycle of the OUT or OUTS
instruction.
2. All times which entail reading the Timer are referenced from the end of the last machine cycle of the IN or INS instruction.
3. All times which entail the generation of an interrupt request are referenced from the start of the machine cycle in which the appropriate interrupt request latch is set. Additional time may elapse if the interrupt request occurs during a privileged or multicycle instruction.
4. Error may be cumulative if operation is repetitively performed.

3-31

I

MC3870

FIGURE 2 - STROBE SOURCE CAPABILITY
(TYPCIAL AT VCC=5 V, TA=25°C)

FIGURE 3 - STROBE SINK CAPABILITY
(TYPICAL AT VCC=5 V, TA=25°C)

-15
+ 100

""'E

i

""'E

I

a

1",00II",,"
~~

1"""1 .....

u

...... """"

a:

~

........ -

-10

-5

I

f'

...........

r---

----.,

~

--- .....

~

,~

.... """"

OUTPUT VOLT AGE

["""II~

OUTPUT VOLTAGE

FIGURE 4 -

STANDARD 1/0 PORT SOURCE CAPABILITY
(TYPICAL AT VCC=5 V, TA=25°C)

FIGURE 5 -

DIRECT DRIVE 1/0 PORT SOURCE CAPABILITY
(TYPICAL AT VCC=5 V, TA=25°C)

-1.5

-10

""'~-1.0

""'E

~

I
>-

1"'1""

I'

>-

'-

i

.... ""

.....
u

a~ -5

""",-

r- .... -..,

...........

u

I'

~

a:

"

~-O.5
en

-- ...

=>
o

"""

en

~

~

~

~

.... 1iIIo.,

I'

,

OUTPUT VOLTAGE

OUTPUT VOLT AGE

FIGURE 6 - 1/0 PORT SINK CAPABILITY
(TYPICAL AT VCC=5 V, TA=25°C)

FIGURE 7 -

MAXIMUM OPERATING TEMPERATURE
vs 1/0 POWER DISSIPATION

100
+60
+ 50

.... ~

50

>-

Pl48ric ....

z

i+

30
~

~+20

,,-

en

+ 10

.. -.

-III- ::-

""'E1+40
1..00 ....

.... ~-

-

CERA.MiC
I

I
I

1",00II1'"

,tI'

...
......

100

200· 300

400

500

600

,~

Po I/O - mW
OUTPUT VOLT AGE

3-32

""'"

"'1"-

1000

MC3870

FIGURE 8 -

MC3870 IDD vs TEMPERATURE (VCC=5 V)

90
80

70
« 60
E
I

IiIIo..

, '" , '"
.....

[""110"""

I"Iio..

.....,,~

Il1o..

.....

f"""IIi"""

~50

,

""""'

40

r--..
r--..
r--..

[""110""",

......

~

1""0"""
,....""",

30

..... """,
~

r"'"

20
-40

-20

+20 +40 +60 +60 +100
TEMPERATURE TA - 0 C

FIGURE 9 -

ac TIMING DIAGRAM

External Clock

I nternal

If>

Clock

-----

I/O Port Output

j

JE""=-f
__
{~
~

- 40
the timer interrupt request latch will be set every 4000 cp clock
periods. For a 2 MHz cp clock (4 MHz time-base frequency)
this will produce 2 millisecond intervals.
The range of possible intervals is from 2 to 51,200 cp clock
periods (1 JLs to 25.6 ms for a 2 MHz clock). However, approximately 50 cp periods is a practical minimum because the
time between setting the interrupt request latch and the execution of the first instruction of the interrupt service routine
is at least 29 cp periods (the response time is dependent upon
how many privileged instructions are encountered when the
request occurs); 29 is based on the timer interrupt occuring
at the beginning of a non-privileged short instruction. To
establish time intervals greater than 51,200 cp clock periods is
a simple matter of using the timer interrupt service routine to
count the number of interrupts, saving the result in one or
more of the scratchpad registers until the desired interval is
achieved. With this technique virtually any time interval, or
several time intervals, may be generated.
The Timer may be read at any time and in any mode using
an input instruction (IN 7 or INS 71 and may take place "on
the fly" without interfering with normal timer operation.
Also, the Timer may be stopped at any time by clearing bit 3
of the ICP. The Timer will hold its current contents in-

Pulse Width Measurement Mode - When ICP bit 4 is set
(logic 1) and at least one prescale bit is set, the Timer
operates in the Pulse Width Measurement Mode. This mode
is used for accurately measuring the duration of a pulse applied to the EXT INT pin. The Timer is stopped and the
prescaler is reset whenever EXT INT is at its inactive level.
The active level of EXT INT is defined by ICP bit 2; if cleared,
EXT INT is active low; if set, EXT INT is active high. If ICP bit
3 is set, the prescaler and Timer will start counting when EXT
INT transitions to the active level. When EXT INT returns to
the inactive level the Timer then stops, the prescaler resets,
and if ICP bit 0 is set an external interrupt request latch is set.
(Unlike timer interrupts, external interrupts are not latched if
the ICP Interrupt Enable bit is not set)

o

As in the Interval Timer Mode, the Timer may be read at
any time, may be stopped at any time by clearing ICP bit 3,
the prescaler and ICP bit 1 function as previously described,
and the Timer still functions as an 8-bit binary down counter
with the timer interrupt request latch being set on the
Timer's transition from H '01' to H 'N'. Note that the EXT
INT pin has nothing to do with loading the Timer; its action is
that of automatically starting and stopping the Timer and of
generating external interrupts. Pulse widths longer than the
prescale value times the modulo-N value are easily measured
by using the timer interrupt service routine to store the
number of timer interrupts in one or more scratchpad
registers.
As for accuracy, the actual pulse duration is typically
slightly longer than the measured value because the status of
the prescaler is not readable and is reset when the Timer is
stopped. Thus, for maximum accuracy, it is advisable to use
a small division setting for the prescaler.
Event Counter Mode - When ICP bit 4 is cleared and all
prescale bits (ICP bits 5, 6, and 7) are cleared, the Timer
operates in the Event Counter Mode. This mode is used for
counting pulses applied to the EXT INT pin. If ICP bit 3 is set,
the Timer will decrement on each transition from the inactive
level to the active level of the EXT INT pin. The prescaler is
not used in this mode; but as in the other two timer modes,

3·41

I

MC3870

the Timer may be read at any time, may be stopped at any
time by clearing ICP bit 3, ICP bit 1 functions previously
described, and the timer interrupt request latch is set on the
Timer's transition from H '01' to H 'N'.
Normally ICP bit 0 should be kept cleared in the Event
Counter Mode; otherwise, external interrupts will be
generated on the transition from the inactive level to the active level of the EXT INT pin.
For the Event Counter Mode, the minimum pulse width required on EXT INT is 2 cf> clock periods and the minimum inactive time is 2 cf> clock periods; therefore, the maximum
repetition rate is 500 kHz.

I

address for a timer interrupt is H '020'. The vector address
for external interrupts is H '~AO'. After the vector address is
passed to the Program Counter, the CPU section sends an
acknowledge signal to the appropriate interrupt request latch
which clears that latch. The execution of the interrupt service routine will then commence. The return address of the
original program is automatically saved in the Stack Register,

P.
The Interrupt Control Bit of W (Status Register) is
automatically reset when an interrupt request is acknowledged. It is then the programmer's responsibility to determine
when ICB will again be set (by executing an EI instruction).
This action prevents an interrupt service routine from being
interrupted unless the programmer so desires.

External Interrupts - When the timer is in the Interval
Timer Mode the EXT INT pin is available for non-timer
related interrupts. If ICP bit 0 is set, an external interrupt request latch is set when there is a transition from the inactive
level to the active level of EXT INT. (EXT INT is an edgetriggered input.) The interrupt request is latched until either
acknowledged by the CPU section or until ICP bit 0 is cleared
(unlike timer interrupt requests which remain latched even
when ICP bit 1 is cleared). External interrupts are handled in
the same fashion when the Timer is in the Pulse Width
Measurement Mode or in the Event Counter Mode, except
that only in the Pulse Width Measurement Mode the external
interrupt request latch is set on the trailing edge of EXT INT;
that is, on the transition from the active level to the inactive
level.

Figure 17 details the interrupt sequence which occurs
whether the interrupt request is from an external source via
EXT INT or from the MC3870's internal timer. Events are
labeled with the letters A through G and are described
below.
Event A - An interrupt request must satisfy a hold time
requirement as specified in the AC Characteristics in order to
guarantee that it is valid on the rising edge of the WRITE
clock.
Event B - Event B represents the instruction being executed when the interrupt occurs. The last cycle of B is normally the instruction fetch for the next cycle. However, if B is
not a privileged instruction and the CPU's Interrupt Control
Bit is set, then the last cycle becomes a "freeze" cycle rather
than a fetch. At the end of the freeze cycle the interrupt request latches are inhibited from altering the interrupt daisychain so that sufficient time will be allowed for the daisychain to settle. (If B is a privileged instruction, the instruction
fetch is not replaced by a freeze cycle; instead, the fetch is
performed and the next instruction is executed. Although
unlikely to be encountered, a series of privileged instructions
will be sequentially executed without interrupt. One more instruction, called a 'protected' instruction, will always be executed after the last privileged instruction. The last cycle of
the protected instruction then performs the freeze.)
The dashed lines on EXT INT illustrate the last opportunity
for EXT INT to cause the last cycle of a non-protected instruction to become a freeze cycle.

INTERRUPT HANDLING

When either a timer or an external interrupt request is
communicated to the CPU section of the MC3870, it will be
- acknowledged and processed at the completion of the first
non-privileged instruction if the Interrupt Control Bit of the
Status Register is set. If the Interrupt Control Bit is not set,
the interrupt request will continue until either the Interrupt
Control Bit is set and the CPU section acknowledges the interrupt or until the interrupt request is cleared as previously
described.
If there is both a timer interrupt request and an external interrupt request when the CPU section starts to process the
requests, the timer interrupt is handled first.
When an interrupt is allowed the CPU section will request
that the interrupting element pass its interrupt vector address to the Program Counter via the data bus. The vector
FIGURE 17 -

INTERRUPT SEQUENCE

Freeze Cycle

~-B

--:-,-

(Internal)

3-42

C+OTETF--t-G

MC3870

The freeze cycle is a short cycle (4 cp clock periods) in all
cases except where B is the Decrement Scratchpad instruction, in which case the freeze cycle is a long cycle (6 cp clock
periods).
INT REO goes low on the next negative edge of WRITE if
both PRIIN is low and the appropriate interrupt enable bit of
the Interrupt Control Port is set. Both INT REO and WRITE
are internal signals.

rupt response time is 3 long cycles plus 2 short cycles plus
one WRITE clock pulse width plus a setup time of EXT INT
prior to the leading edge of the WRITE pulse - a total of 27
cp clock periods plus the setup time. At a 2 MHz cp this is
14.25 p.s. Although the maximum could theoretically be infinite, a practical maximum is 35 P.s (based on the interrupt
request occurring near the beginning of a PI and LR K, P sequence).

Event C - A NO-OP long cycle to allow time for the internal priority chain to settle.

POWER-ON RESET

Event D - The Program Counter (PO) is pushed to the
stack register (P) in order to save the return address. The interrupt circuitry places the lower 8 bits of the interrupt vector
address onto the data bus. This is always a long cycle.
Event E - A long cycle in which the interrupt circuitry
places the upper 8 bits of the interrupt vector address onto
the data bus.
Event F - A short cycle in which the interrupting interrupt
request latch is cleared. Also, the CPU's Interrupt Control Bit
is cleared, thus disabling interrupts until an EI instruction is
performed. The fetch of the next instruction from the interrupt address.
Event G - Begin execution of the first instruction of the
interrupt service routine.
SUMMARY OF INTERRUPT SEQUENCE

For the MC3870 the interrupt response time is defined as
the time elapsed between the occurrence of EXT INT going
active (or the Timer transitioning to H 'N') and the beginning
of execution of the first instruction of the interrupt service
routine. The interrupt response time is a variable dependent
upon what the microprocessor is doing when the interrupt
request occurs. As shown in Figure 17, the minimum interFIGURE 18 -

The intent of the Power-On Reset circuitry on the MC3870
is to automatically reset the device following a typical powerup situation, thus saving external reset circuitry in many applications. This circuitry is not guaranteed to sense a "Brown
Out" (low voltage) condition nor is it guaranteed to operate
under all possible power-on situations.
Three conditions are required before the MC3870 will leave
the reset state and begin operation. Refer to Figure 18 as an
aid to the following descriptions. The On-Chip V CC detector
senses a minimum value of V CC before it will allow the
MC3870 to operate. The threshold of this detector is set by
analog circuitry because a stable voltage reference is not
available with n-channel MOS processing. Processing variations will cause this threshold to vary from a low of 3.0 volts
to a high of 4.3 volts with 3.5 volts being typical.
The MC3870 uses a substrate bias as a technique to provide improved performances versus power consumption
relative to conventional grounded substrate approaches.
This bias generator may start operating as low as
V CC = 3 volts on some devices while others may require
V CC = 4 volts in order to get adequate substrate bias. Until
the substrate reaches the proper bias,the MC3870 will not
be released from the reset state. The final condition required
is that the clocks of the MC3870 must be functioning.
Typically the clocks will start to function at VCC equal to 3 to
3.5 volts but since the part is tested at 4.5 volts, Motorola
can not guarantee any operation below 4.5 volts. The output
of the delay circuit in Figure 18 will stay low until the clocks

POWER ON RESET BLOCK DIAGRAM

To Internal
3870 Logic
Reset State = 1

I

MC3870

start to function. If the input to the delay circuit is high,
typically after 100 cycles of the WRITE clock (800 cycles of
the external clock) the output of the delay circuit will go high
allowing the MC3870 to begin execution.

I

into vibrational motion. This time is baSically dependent on
the frequency (mass) of the crystal. 4 MHz crystals typically
require about 2-3 ms to start while 1 MHz crystals require
60-70 ms to start oscillating. Of course, this time may vary
greatly from crystal to crystal and is also a function of the
power supply rise time characteristic, however, the highfrequency crystals start faster and are definitely recommended (i.e., 3-4 MHz).
The condition of the port pins during the power-in-clear
sequence is often asked. The port pins or the STROBE line
cannot be specified until V CC reaches 4.5 V and the MC3870
enters the RES ET state. Before this, the port pins may stay
at VSS, may track VCC as it rises, or they may track VCC
part way up then return to VSS (ports 4 and 5 will go to VCC
once the clocks are running and the MC3870 has sufficient
V CC to properly operate the internal control logiC and I/O
ports).

If VCC falls to ground for at least a few hundred
nanoseconds the output of the delay circuit will go low immediately and the MC3870 will reset.
The internal logic may detect a valid Vce, bias and clocks
at VCC=3.5 volts and allow the MC3870 to start executing
after the time delay. With a slowly rising power supply, the
part may start running before V CC is above 4.5 volts which is
below the guaranteed voltage range. When power-on-clear
is required with a slowly rising power supply, an external
capacitor must be used on the RESET pin to hold it below
0.8 volts until VCCis stable above 4.5 volts. (Note: The option to disconnect the internal pullup resistor on RESET is
available which allows the use of a larger external pullup
resistor and a small capacitor on RES ET.)
In many applications it is desirable if the unit does an
automatic power-on-clear, but not mandatory. The unit will
have a RESET push button and if the unit does not power-up
correctly or malfunctions because of some disturbance on
the VCCline, the operator will simply press RESET and
restore normal operation. It is for these applications that the
internal power-on-clear circuitry was designed.
In some applications it is required that the microcomputer
continue to run properly without operator intervention after
brown-outs, power line disturbances, electrical noise, computer malfunction due to a programming bug, or any other
disturbance except a catastrophic failure of some component.
One concept used to keep computers running is that of
the "WATCHDOG TIMER". The computer is programmed
to periodically reset the watchdog timer during the normal
execution of its program (this is easily done in the MC3870 as
its normal application is in some control function which is
typically periodic). As long as the computer continues to execute its program the watchdog timer is continually reset
and never times out. Should the computer stop executing its
program for whatever reason, the watchdog timer will time
out producing a RESET pulse to the CPU re-starting execution. This is a very positive way to assure that the computer
is doing its job, i.e., executing the program. It is important
that the software driving the watchdog timer test as many
functional blocks (timer, ALU, scratchpad RAM, and ports)
of the MC3870 as possible before resetting the watchdog
timer. This is because operation of the MC3870, with an out
of specification power supply, may allow some of the functions to operate correctly while other functions are not
operable.
Motorola can guarantee correct operation of the MC3870
only while the VCC voltage remains within its specified
limits. If proper operation of the MC3870 must be
guaranteed after a disturbance on the V CC line, then an external circuit must be used to monitor the VCC line and produce RESET to the MC3870 whenever VCC is out of the
specified limits.
A related characteristic to power-on-clear is the startup
time of the basic timing element. The LC and RC oscillators
begin to function almost immediately once Vce is high
enough to allow the on-board oscillator to operate
(VCC=3.5 V). Operation with a crystal is partly mechanical
and some start time is required to get the mass of the crystal

EXTERNAL RESET

When RESET is taken low, the content of the Program
Counter is pushed to the Stack Register and then the Program Counter and the ICB bit of the W Status Register are
cleared. The original Stack Register content is lost. Ports 4,
5, 6, and 7 are loaded with H '00'. The contents of all other
registers and ports are unchanged or undefined. When
RESET is taken high, the first program instruction is fetched
from ROM location H '000'. When an external reset of the
MC3870 occurs, PO is pushed into P and the old contents of
P are lost. It must be noted that an external reset is recognized at the start of a machine cycle and not necessarily at
the end of an instruction. Thus, if the MC3870 is executing a
multi-cycle instruction, that instruction is not completed and
the contents of P upon reset may not necessarily be the address of the instruction that would have been executed next.
It may, for example, point to an immediate operand if the
reset occurred during the second cycle of an LI or CI instruction. Additionally, several instructions (JMP, PI, PI, LR, PO,
Q) as well as the interrupt acknowledge sequence modify PO
in parts. That is, they alter PO by first loading one part then
the other and the entire operation takes more than one cycle.
Should reset occur during this modification process the
value pushed into P will be part of the old PO (the as yet unmodified part) and part of the new PO (already modified
part). Thus, care should be taken (perhaps by external
gating) to insure that reset does not occur at an undesirable
time if any significance is tei be given to the contents of P
after a reset occurs.
VCC DECOUPLING
The MC3870 family devices have dynamic circuitry internally which requires a good high frequency decoupling
capacitor to surpress noise on the VCC line. A 0.01 /tF or
0.1 /tF ceramic capacitor should be placed between V CC and
ground, located physically close to the MC3870 device. This
will reduce noise generated by the MC3870 to about
70-100 mV on the VCC line.
TEST LOGIC

SpeCial test logic is implemented to allow access to the internal main data bus for test purposes.
In normal operation, the TEST pin is unconnected or is
connected to GND. When TEST is placed at a TTL level
(2.0 V to 2.6 V) port 4 becomes an output of the internal data

3-44

MC3870

+ 5 V, bit 7 of the Accumulator is set to a logic "1"; but, if
EXT INT is at GND, then Accumulator bit 7 is reset to logic
"0".

bus. The data appearing on the port 4 pins is logically true
whereas input data forced on port 5 must be logically false.
When TEST is placed at a high level (6.0 V to 7.0 V), the
ports act as above and additionally the 2K x 8 program ROM
is prevented from driving the data bus. In this mode,
operands and instructions may be forced externally through
port 5 instead of being accessed from the program ROM.
When TEST is in either the TTL state or the high state,
STROBE ceases its normal function and becomes a machine
cycle clock (identical to the F8 multi-chip system WRITE
clock except inverted).
Timing complexities render the capabilities associated with
the TEST pin impractical for use in a user's application, but
these capabilities are thoroughly sufficient to provide a rapid
method for thoroughly testing the MC3870.

In the MC3870 (F8 COMPATIBLE) INSTRUCTION SET
summary, the number of cycles shown are "nominal"
machine cycles. A nominal machine cycle is defined as 4 cJ>
clock periods, thus, requiring 2 P.s for a 2 MHz cJ> clock frequency (4 MHz external time-base frequency).
Also, the summary uses an older nomenclature for register
names. The translation is as follows:
PCO= PO
PCl = P
DCO= DC

Program Counter
Stack Register
Data Counter

DCl = DCl Auxiliary Data Counter
The nomenclature is used in order to be consistent with the
assembly language mnemonics.
For the MC3870, execution of an INS or OUTS instruction
requires 2 machine cycles for ports 0 and 1, whereas ports 4
and 5 require 4 machine cycles.

SUPPLEMENTARY NOTES
The Interrupt Control Bit of the W Status Register is
automatically reset when an interrupt request is acknowledged. It is then the programmer's responsibility to determine when ICB will again be set (by execution an EI instruction). This action prevents an interrupt service routine from
being interrupted unless the programmer so desires.
When reading the Interrupt Control Port (port 6), bit 7 of
the Accumulator is loaded with the actual logic level being
applied to the EXT INT pin, regardless of the status of !CP
bit 2 (the EXT INT Active Level bit). This is, if EXT INT is at

INSTRUCTION EXECUTION
This section details the timing and execution of the
MC3870 instruction set. Refer to Figure 19 for a MC3870 Programming Model.

3-45

I

iii
FIGURE 19 -

3:

nw
.....

MC3870 PROGRAMMING MODEL
_----{IADC

EI

CO

.-------------4>~ILNK

01

o

OUTS 7
Timer

w
4

3

2

,

INS' 7

Ports

0

LlSL
OUTS 6
Int Cntl
INS' 6t

I

LISU
Scratchpad
Registers

o

OUTS 0,1,4,5
I/O

o

Aux Oata

3

Counter

Ports

INS' 0,1,4,5

AS'

NS

2

XS

3
4

ASO

LR

ROM
MEM
2048 x 8

(,.)

Ports

I.

LR

~

'~O]

I I.

0>
I . T ..

lOS'

SL4

SRI
SR4

ROM
Mem

AM'
AMD

2048 x 8

NM
OM

XM

3F
Counter
Int. Vector

Hex

77
Octal

LM
(DCI

Reset Transfers PO to P and

From

then clears PO, ICB Bit of W

Timer

and Ports 4,5,6, and 7 .

• These instructions set status.
t

H '000'

Extern~1 Interrupt

RESET

t The value of the external interrupt input is loaded to Bit 7 of the accumulator (with Bits 0 through 6 loaded with zeros)
when the instruction 'I NS 6' is executed. This instruction also sets status.

ttPO, P, DC, and DCl are 12-bit registers
NOTE: The Instructions PI and PK are shown in two sequential parts. (PI', PI2 and PK', PK2).

MC3870

MC3870 INSTRUCTION SET
ACCUMULATOR GROUP INSTRUCTIONS
Operation
Add Carry

Mnemonic
Op Code

Operand

LNK

Machine
Code

Function

Bytes
1

AI

A-IAI+CRY
A-IAI+H',,'

19

Add Immediate

24il

2

And Immediate

NI

A-IAIAH',,'

21il

A-H'OO'

70

H',,' + IAI+ 1

25"
18

Clear

CLR

Compare Immediate

CI
COM

Complement
Exclusive or Immediate
Increment

A-IAI+H'FF'
A-IAI+H',,'

XI
INC

Load Immediate

(2 MHz
o
FIGURE 12 -

EXPANDED NON-MULTIPLEXED CONFIGURATION

-

Vee
XTAL1

~

Vee

Vee
I
XTAL1

~ EXTAL2

Standby---.
RESEt~
NM'I~

MC6801

Port 3
Port4

iOS

8

7

(00-07)
(AO-A7)
lOS
.. R/Vii
E

87

R/W
E

IRQj~

Port 3
8 Data Lines
RlVii

Port 1
8110 Lines
Port 2
51/0
Lines
Serial 110
16-Bit Timer

lOS
Port 4
To 8
":"

VSS

Port 1 .....
81/0 ....
Port 2 ..L
51/0
....SCI
Timer

.....

.

....
-,.-

~

VSS

RAM

PIA
----~

ACIA

o
w

MC6801·MC6803

Expanded-Multiplexed Modes (0, 1, 2, 3, 6)
A 64K byte memory space is provided in the expandedmultiplexed modes. In each of the expanded-multiplexed
modes port 3 functions as a time multiplexed address/data
bus with address valid on the negative edge of address
strobe (AS), and data valid while E is high. In modes 0 to 3,
port 4 provides address lines A8 to A 15. In mode 6, however,
port 4 initially is configured at RESET as an input data port.
The port 4 data direction register can then be changed to
provide any combination of address lines, A8 to A 15. Stated
alternatively, any subset of A8 to A 15 can be provided while
retaining the remaining port 4 lines as input data lines. Internal pullup resistors pull the port 4 lines high until software
configures the port.
In mode 0, the reset vector is external for the first two E
cycles after the positive edge of RES ET, and internal thereafter. In addition, the internal and external data buses are
connected so there must be no memory map overlap in order
to avoid potential bus conflicts. Mode 0 is used primarily to
verify the ROM pattern and monitor the internal data bus
with the automated test equipment.
Only the MC6801 can operate in each of the expandedmultiplexed modes. The MC6803 operates only in modes 2
and 3.
Figure 13 depicts a typical configuration for the expandedmultiplexed modes. Address strobe can be used to control a

TABLE 3 -

Mode*

P22
PC2

P2l
PCl

P20
PCO

7

H

H

6

H

H

5

H

L

4

H

L

3

L

H

2

L

1
0

PROGRAMMING THE MODE
The operating mode is determined at RESET by the levels
asserted on P22, P21, and P20. These levels are latched into
PC2, PC1, and PCO of the program control register on the
positive edge of RESET. The operating mode may be read
from the port 2 data register as shown below, and programming levels and timing must be met as shown in Figure 15. A
brief outline of the operating modes is shown in Table 3.

PORT 2 DATA REGISTER
765

I PC2 I PCl I PCO I P24

P23

I P22 I P21

P20

MODE SELECTION SUMMARY
Bus
Mode

I

I
I

I
MUXI5,6)

Single Chip

I
I
Ill)

I

MUXI5,6)

Non-Multiplexed/ Partial Decode

L

I
1(2 )

I

E

E

E

I
MUX(4)

Single-Chip Test

H

H

L

E

I

E

MUX(4)

Multiplexed/ RAM

L

L

H

I

I

MUX(4)

Multiplexed/ RAM and ROM

L

L

L

I

I

E
1(3 )

MUX(4)

Multiplexed Test

ROM

RAM

H

I

L

I

H

$0003

Circuitry to provide the programming levels is dependent
primarily on the normal system usage of the three pins. If
configured as outputs, the circuit shown in Figure 16 may be
used; otherwise, three-state buffers can be used to provide
isolation while programming the mode.

Interrupt
Vectors

Legend:
--r=-Tnterna I
E - External
MUX - Multiplexed
NMUX - Non-Multiplexed
L - Logic Zero
H - Logic One

* The

transparent D-type latch to capture addresses AO-A7, as
shown in Figure 14. This allows port 3 to function as a data
bus when E is high.

Operating
Mode
Multiplexed/ Partial Decode

Multiplexed/No RAM or ROM

NOTES:
i1TTnternal RAM is addressed at $XX80.
(2) Internal ROM is disabled.
(3) RESET vector is external for two cycles after RESET goes high.
(4) Addresses associated with ports 3 and 4 are considered external in modes 0,
1,2, and 3.
(5) Addresses associated with port 3 are considered external in modes 5 and 6.
(6) Port 4 default is user data input; address output is optional by writing to port 4
data direction register.

MC6803 operates only in modes 2 and 3.

3-61

I

MC6801·MC6803

FIGURE 13 -

EXPANDED MULTIPLEXED CONFIGURATION
VCC

Port 1
ai/O Lines • • •~
Port 2
5 110 Lines
Serial 110
16-Bit Timer

I

Port 4
a Lines
Address Bus
VSS

VCC
I

6~
VCC Sta ndby~
~
SE1-----..
NMi--.

XTAL1
Port 3
EXTAL2

IRoi~

Port 1
a 1/0
Port 2
51/0
SCI
Timer

.....

...

a

a

Data Bus
(00-07)

~
Latch

Port4

MC6801
MC6803

R/W

Address Bus
(AO-A15)

16

'" Rlw

E

--..

-'"

r

...

...

,.
~
VSS

l

Il

ROM

RAM

Il

PIA

1

NOTE: To avoid data bus (port 3) contention in the expanded multiplexed modes, memory devices should be enabled only during E high time.

GNO

.,.

FIGURE 14 - TYPICAL LATCH ARRANGEMENT

AS

I

.,.

G
01

Port 3
Addressl Data

,

I

OC
°1

74LS373
(Typical)

Address: AO-A7

...

.,.
Oa

08

Data: 00-07

3-62

MC6801·MC6803

FIGURE 15 - MODE PROGRAMMING TIMING
See Figure 16
for Diode Arrangement
,, __ - - GVMPDD
(P2(), P21,

Mode Inputs
(P20, P21, P22)

~"
~
____ ....... "
--.-

"21

MPL
Mode Latch

T

RESET

Level

MODE PROGRAMMING (Refer to Figure 15)
Symbol

Min

Max

Unit

Mode Programming Input Voltage Low*

VMPL

-

1.8

V

Mode Programming Input Voltage High

VMPH

4.0

-

Mode Programming Diode Differential (If Diodes are Used)

VMPDD

0.6

-

V

RESET Low Pulse Width

PWRSTL

3.0

-

E Cycles

Mode Programming Setup Time

tMPS

2.0

-

E Cycles

Mode Programming Hold Time
RESET Rise Time~ 1 ,.s
RESET Rise Time< 1 ,.s

tMPH

0
100

-

ns

Characteristic

V

FIGURE 16 - TYPICAL MODE PROGRAMMING CIRCUIT
VCC

1
>

4
).
~ ).
R2 : >RH > Rl· ~
~
>
~>

~>

Rl:~
6

RESET
P20

RESET
8

~

9

P2 1

10

P2 2

Mode
Control
Switches

0'

0

P20 (PCO)
P21 (PC1)
P22 (PC2)

MCSSOl
MC6803

0

NOTES:
1. Mode 7 as shown
_L...
2. R2-C = Reset time constant
3. R1 = 10 k (typical)
4 0 = 1N914, 1N4001 (typical)
5. Diode Vf should not exceed VMPDD min.

MEMORY MAPS

each operating mode is shown in Figure 17. The first 32 locations of each map are reserved for the internal register area,
as shown in Table 4, with exceptions as indicated.

The M6801 Family can provide up to 64K byte address
space depending on the operating mode. A memory map for

3-63

I

MC6801·MC6803

FIGURE 17 -

Multiplexed-Test Mode -

MC6801
Mode

MC6801/03 MEMORY MAPS (Sheet 1 of 3)

o

MC6801
Mode
Multiplexedl RAM and ROM

$0CXXl(1 )

Internal Registers
$001 F

1

.$0CXXl ( 1)

,7'7TT777'?'7T.77I

IL"'-'-LL~.L.LJ,-'I

Internal Registers
External Memory Space
External Memory Space
Internal RAM

I

Internal RAM

External Memory Space

External Memory Space

$F8oo
Internal ROM

Internal ROM
$FFEF fL.L.o'-"'-.<..L.<~'-'1<
$FFFO
External Interrupt Vectors

Internal Interrupt Vectors(2)

NOTES:
1) Excludes the following addresses which may be
used externally: $04, $05, $06, $07, and $OF.
2) Addresses $FFFE and $FFFF are considered
external if accessed within two cycles after a
positive edge of RESET and internal at all other
times.

b777777?'7T.'7! ,

NOTES:
1) Excludes the following addresses which may be
used externally: $04, $05, $06, $07, and $OF.
2) Internal ROM addresses $FFFO to $FFFF are not
usable.

3) After two MPU cycles, there must be no overlapping of internal and external memory spaces
to avoid driving the data bus with more than one
device.
4) This mode is the only mode which may be used
to examine the interrupt vectors in internal ROM
using an external RESET vector.

3-64

3:

oen
FIGURE 17 -

CO

MC6801/03 MEMORY MAPS (Sheet 2 of 3)

o....

3l::

MC6801
MC6803
Mode

MC6801
MC6803
Mode

2

3

MC6801
Mode

Multiplexed/No RAM or ROM

4

$0000(1)

IJ}};

»;))""

$001 F IU u U u U / 1

rTTTTTT7777771 "

$0000
$001F

Internal Registers

Internal Registers
$001F

!{{{{{{

$0080

w,§/:VffA~

$OOFF

l/ u

~)

Internal Registers

«({(I<
External Memory Space
Internal RAM

/C// u u

1.(
Unusable (1 )(4)

External Memory Space

w

0>
0'1

External Memory Space

::::~t=jJ

$FFFO
External Interrupt Vectors

NOTES:
1) Excludes the following addresses which may be
used externally: $04, $05, $06, $07, and $OF.

$FFFF

I

External Interrupt Vectors

L . . .- - - - - - '

NOTES:
1) Excludes the following addresses which may be
used externally: $04, $05, $06, $07, and $OF.

$XX80
$XXFF

~)

Internal RAM
Internal Interrupt Vectors

NOTES:
1) The internal ROM is disabled.
2) Mode 4 may be changed to Mode 5 without having to assert RESET by writing a one into the
PCO bit of the port 2 data register.
3) Addresses A8 to A 15 are treated as "don't cares"
to decode internal RAM.
4) Internal RAM will appear at $XX80 to $XXFF.

III

CO

o

W

Single-Chip Test

Multiplexed/ RAM
$OOOO( 1)

oen

iii
FIGURE 17 -

MC6801
Mode

s::
oen
CD

MC6801/03 MEMORY MAPS (Sheet 3 of 3)

5

MC6801
Mode

o
...A.

6

MC6801
Mode

7

Multiplexedl Partial Decode
}

$OOlF

Internal Registers

$OOOOI1I~1

l'' ' "'

$OOFF
$0100

External RAM
Memory Space

$OOFF

$OOFF

Il

Unusable

$FSOO

$OOSO
Internal RAM

w

m

$001 F

External Memory Space

$0080

$01 FF

0>

Single Chip
$0000

Internal Registers

$001 F

$0080

External Memory Space

V7777)77777/1j
$FSOO 1;;;;;n;;nJ

$FSOO

V7777/~777/7»1}

Internal ROM
Internal ROM

Internal ROM
$FFFF

vcucuuuo

Internal Interrupt Vectors

$FFFF

((cuuU/UQ

Internal Interrupt Vectors

NOTES:
1) Excludes the following addresses which may not
be used externally: $04, $06, and $OF (no 10SI.

NOTES:
1) Excludes the following addresses which may be
used externally: $04, $06, and $OF.

2) This mode may be entered without going
through RESET by using mode 4 and subsequently writing a one into the PCO bit of the port
2 data register.

21 Address lines AS-A 15 will not contain addresses
until the data direction register for port 4 has
been written with ones in the appropriate bits.
These address lines will assert ones until made
outputs by writing the data direction register.

31 Address lines AO to A7 will not contain addresses
until the data direction register for port 4 has
been written with ones in the appropriate bits.
These address lines will assert ones until made
outputs by writing the data direction register.

CD

o

W

Non-Multiplexed/Partial Decode
$0000(1)

i:

ocn

$FFFF v/////h'////A

Internal Interrupt Vectors

MC6801·MC6803

MC6801/03 INTERRUPTS

between them to prevent supplying power to Vee during
powerdown operation. Vee standby should be tied to
ground in mode 3.

The M6801 Family supports two types of interrupt requests: maskable and non-maskable. A non-maskable interrupt (NMI) is always recognized and acted upon at the completion of the current instruction. Maskable interrupts are
controlled by the condition code register I bit and by individual enable bits. The I bit controls all maskable interrupts. Of the maskable interrupts, there are two types: IRQ1
and IRQ2. The programmable timer and serial communications interface use an internal I RQ2 interrupt line, as shown
in Figure 1. External devices (and IS3) use TRCfi. An IRQ1 interrupt is serviced before IRQ2 if both are pending.
All IRQ2 interrupts use hardware prioritized vectors. The
single sel interrupt and three timer interrupts are serviced in
a prioritized order and each is vectored to a separate location. All interrupt vector locations are shown in Table 5.
The interrupt flowchart is depicted in Figure 18 and is
common to every interrupt excluding reset. During interrupt
servicing the program counter, index register, A accumulator, B accumulator, and condition code register are pushed
to the stack. The I bit is set to inhibit maskable interrupts and
a vector is fetched corresponding to the current highest
priority interrupt. The vector is transferred to the program
counter and instruction execution is resumed. Interrupt and
RESET timing are illustrated in Figures 19 and 20.

TABLE 4 -

INTERNAL REGISTER AREA
Register

FUNCTIONAL PIN DESCRIPTIONS

Address

00

Port
Port
Port
Port

1 Data
2 Data
1 Data
2 Data

Direction Register* * *
Direction Register* * *
Register
Register

01
02
03

Port
Port
Port
Port

3
4
3
4

Direction Register* * *
Direction Register* * *
Register
Register

04*
05* *
06*
07* *

Data
Data
Data
Data

Timer Control and Status Register
Counter (High By tel
Counter (Low By tel
Output Compare Register (High By tel

08
09
OA
OB

Output Compare Register (Low By tel
Input Capture Register (High By tel
Input Capture Register (Low By tel
Port 3 Control and Status Register

OC
00
OE
OF*

Rate and Mode Control Register
T ransmitl Receive Control and Status Register
Receive Data Register
Transmit Data Register

10
11
12
13

RAM Control Register
Reserved

Vee AND Vss
Vee and VSS provide power to a large portion of the
MCU. The power supply should provide + 5 volts (± 5%) to
Vee, and VSS should be tied to ground. Total power
dissipation (including Vee standby), will not exceed Po
milliwatts.

14
15-1 F

* External addresses in modes 0, 1, 2, 3, 5, and 6; cannot be accessed in mode 5 (no 10SI.
* * External addresses in modes 0, 1, 2, and 3.
* * * 1 = Output, 0= Input.

TABLE 5 -

Vee STANDBY
Vee standby provides power to the standby portion ($80
through $BF) of the RAM and the STBY PWR and RAME
bits of the RAM control register. Voltage requirements depend on whether the device is in a powerup or powerdown
state. In the powerup state, the power supply should provide
+ 5 volts (± 5%) and must reach VS B volts before RES ET
reaches 4.0 volts. During powerdown, Vee standby must remain above VSBB (min) to sustain the standby RAM and
STBY PWR bit. While in powerdown operation, the standby
current will not exceed ISBB.
It is typical to power both Vee and Vee standby from the
same source during normal operation. A diode must be used

MCU INTERRUPT VECTOR LOCATIONS

MSB

LSB

Interrupt

FFFE

FFFF

RESET

FFFC

FFFD

NMI

FFFA

FFFB

Software Interrupt (SWII

FFF8

FFF9

IR01 (or IS31

FFF6

FFF7

ICF (Input Capturel*

FFF4

FFF5

OCF (Output Capturel *

FFF2

FFF3

TOF (Timer Overflowl *

FFFO

FFF1

SCI (RDRF+ ORFE+ TDREI*

--

* IR02 Interrupt

3-67

I

..
FIGURE 18 -

s:

o

INTERRUPT FLOWCHART

en

Q)

o

""""

i:
oen
Q)

o
w

(JJ

m
ex>

SCI = TIE-TDRE+ RIE-(RDRF+ ORFE)
Condition Code Register

I Non-Maskable Interrupt

NMI

FFFC: FFFD

SWI

FFFA:FFFB

Software Interrupt

IRQl

FFF8:FFF9

Maskable Interrupt Request 1

ICF

FFF6: FFF7

Input Capture Interrupt

OCF

FFF4: FFF5

Output Compare Interrupt

TOF

FFF2:FFF3

Timer Overflow Interrupt

SCI

FFFO: FFFl

SCI Interrupt (TDRE + RDRF + ORFE)

A

3:
FIGURE 19 -

o
0)

INTERRUPT SEQUENCE

CO

o

I Cycle
Last Instructioni

#1

#3

#2

#4

I

#5

I

#7

#6

#8

#9

I

#10

I

~

#11

~

#12

o

0)

CO

o

Internal
Address Bus

IRQ1

W
~ ~tPcs

\.

NMI or IRQ2

~

!+-tpcs

Internal
Data Bus

~_

PC 0- 7

Op Code Op Code

w

PC8-15

X 0-7

X 8-15

ACCA

ACCB

CCR

\

Internal R/W

Irrelevant
Data

Vector
MSB

Vector
LSB

First Ins!. of
Interrupt Routine

/

0>

<0
FIGURE 20 -

RESET TIMING

&\\\\\\\\\\\\\~ ~\\\\\\\\\\\\\\ ~
Vcc
RESET

Internal
Address Bus
Internal Riw
Internal
Data Bus

5.25 V
4

7f~

I I

75 V

1

tRC

--------II I

i

I

I

nnsu

~

I I

~ i:= tpcs

.

~ 4.0V

~

~ i:=,pcs

08\~F-'_- - _

\\\\\\\\\\\\\\S\\s4
(SSS\S\\\\\S\\SS\\S\\S\\\\ \ S~
II-"_"!\"_-J',--_I\.-_-J't._--"'--_J'-_...J'_-...J '-:":-:-='
~ ~
~ FFFE

------

S\\\\\\\SS\\S\\SSS ts\\\\\\\\\\\\\\\\\\\\\\\\\V

-------------~~

&\\\\\\\\S\\\\\\\~ iK\\\\S\\\\\ \\\\\\\\\\\\\\\\\ssxj

~
PC 8-15 PC 0-7

~NotValid

First
Instruction

..

MC6801·MC6803

XTALl AND EXTAL2

I

SCl and SC2 In Single-Chip Mode
In single-chip mode, SCl and SC2 are configured as an
input and output, respectively, and both function as port 3
control lines. SCl functions as IS3 and can be used to indicate that port 3 input data is ready or output data has been
accepted. Three options associated with IS3 are controlled
by port 3 control and status register and are discussed in the
PORT 3 (P30-P37). If unused, IS3 can remain unconnected.
SC2 is configured as OS3 and can be used to strobe output data or acknowledge input data. It is controlled by output strobe select (OSS) in the port 3 control and status
register. The strobe is generated by a read (OSS = Q) or write
(OSS = 1) to the port 3 data register. OS3 timing is shown in
Figure 4.

These two input pins interface either a crystal or TTL compatible clock to the MCU internal clock generator. Divide-byfour circuitry is included which allows use of the inexpensive
3.58 MHz or 4.4336 MHz Color Burst TV crystals. A 20 pF
capacitor should be tied from each crystal pin to ground to
ensure reliable startup and operation. Alternatively, EXT AL2
may be driven by an external TTL compatible clock at 4fo
with a duty cycle of 50% (± 5%) with XT AL 1 connected to
ground.
The internal oscillator is designed to interface with an ATcut quartz crystal resonator operated in parallel resonance
mode in the frequency range specified for fXTAL. The
crystal should be mounted as close as possible to the input
pins to minimize output distortion and startup stabilization
time. * The MCU is compatible with most commercially
available crystals. Nominal crystal parameters are shown in
Figure 21.

SCl and SC2 In Expanded Non-Multiplexed Mode
In the expanded non-multiplexed mode, both SCl and
SC2 are configured as outputs. SCl functions as input/ output select (lOS) and is asserted only when $0100 through
SOl FF is sensed on the internal address bus.
SC2 is configured as read/write and is used to control the
direction of data bus transfers. An MPU read is enabled
when read/write and E are high.

RESET
This input is used to reset the internal state of the device
and provide an orderly startup procedure. During powerup,
RESET must be held below 0.8 volts: (1) at least tRC after
V CC reaches 4.75 volts in order to provide sufficient time for
the clock generator to stabilize, and (2) until V CC standby
reaches 4.75 volts. RESET must be held low at least three E
cycles if asserted during powerup operation.

SCl and SC2 In Expanded-Multiplexed Mode
In the expanded-multiplexed mode, both SCl and SC2 are
configured as outputs. SCl functions as address strobe and
can be used to demultiplex the eight least-significant addresses and the data bus. A latch controlled by address
strobe captures address on the negative edge, as shown in
Figure 14.
SC2 is configured as read/write and is used to control the
direction of data bus transfers. An MPU read is enabled
when read/write and E are high.

E (ENABLE)
This is an output clock used rrimarily for bus synchronization. It is TTL compatible and is the slightly skewed divideby-four result of the device input clock frequency. It will
drive one Schottky TTL load and 90 pF, and all data given in
cycles is referenced to this clock unless otherwise noted.

PORT 1 (P1O-P17l
Port 1 is a mode independent 8-bit I/O port with each line
an input or output as defined by the port 1 data direction
register. The TTL compatible three-state output buffers can
drive one Schottky TTL load and 30 pF, Darlington transistors, or CMOS devices using external pullup resistors. It is
configured as a data input port by RESET. Unused lines can
remain unconnected.

NON-MASKABLE INTERRUPT (NMI)
An NMI negative edge requests an MCU interrupt sequence, but the current instruction will be completed before
it responds to the request. The MCU will then begin an interrupt sequence. Finally, a vector is fetched from SFFFC and
SFFFD, transferred to the program counter and instruction
execution is resumed. NMI typically requires a 3.3 kO
(nominal) resistor to VCe. There is no internal NMI pullup
resistor. NMI must be held low for at least one E cycle to be
recognized under all conditions.

PORT 2 (P20-P24)

MASKABLE INTERRUPT REQUEST 1 (IRQ1)

PORT 2 DATA REGISTER

TROT is a level-sensitive input which can be used to request an interrupt sequence. The M PU will complete the current instruction before it responds to the request. If the interrupt mask bit (I bit) in the condition code register is clear, the
MCU will begin an interrupt sequence. A vector is fetched
from $FFF8 and SFFF9, transferred to the program counter,
and instruction execution is resumed.
TROT typically requires an external 3.3 kO (nominal)
resistor to VCC for wire-OR applications. TR01 has no internal pullup resistor.

7

6

543

I PC21 PCl I PCO I P24 I P23 I P22

P2l

I P20 I $0003

Port 2 is a mode-independent, 5-bit, mUlti-purpose I/O
port. The voltage levels present on P20, P21, and P22 on the
rising edge of RESET determine the operating mode of the
MCU. The entire port is then configured as a data input port.
The port 2 lines can be selectively configured as data output
lines by setting the appropriate bits in the port 2 data direction register. The port 2 data register is used to move data
through the port. However, if P21 is configured as an output, it will be tied to the timer output compare function and
cannot be used to provide output from the port 2 data
register.

STROBE CONTROL 1 AND 2 (SCl AND SC2)
The function of SCl and SC2 depends on the operating
mode. SCl is configured as an output in all modes except
single-chip mode, whereas SC2 is always an output. SCl
and SC2 can drive one Schottky load and 90 pF.

* Devices made with masks subsequent to M5G, M8D, and T5P incorporate an advanced clock with improved startup characteristics.

3-70

MC6801·MC6803

FIGURE 21 -

M6801 FAMILY OSCILLATOR CHARACTERISTICS

(a) Nominal Recommended Crystal Parameters

Nominal Crystal Parameters*

RS
Co
Cl
Q

* NOTE'

3.58 MHz

4.00 MHz

5.0 MHz

6.0 MHz

8.0 MHz

60 {}
3.5 pF
0.015 pF
>40 K

50 {}
6.5 pF
0.025 pF
>30 K

30-50 {}
4-6 pF
0.01-0.02 pF
>20 K

30-50 {}
4-6 pF
0.01-002 pF
>20 K

20-40 {}
4-6 pF
0.01-002 pF
>20 K

These are representative AT-cut crystal parameters only. Crystals of other types of cut may also
be used.

MC6801

----------~ID~(-----------

Cl

RS

2

CL = 20 pF (typicall
Equivalent Circuit
NOTE

TTL-compatible oscillators may be
obtained from'
Motorola Component Products
Attn: Data Clock Sales
2553 N. Edgington St.
Franklin Park, IL 60131
Tel: 312-451-1000
Telex: 433-0067

(b) Oscillator Stabilization Time (tRC)

~--------------~J~'-------------------------------VCC

4.75V

3-71

I

MC6801·MC6803

Port 2 can also be used to provide an interface for the
serial communications interface and the timer input edge
function. These configurations are described in PROGRAMMABLE TIMER and SERIAL COMMUNICATIONS INTERFACE (SCI).
The port 2 high-impedance TTL-compatible output buffers
are capable of driving one Schottky TTL load and 30 pF, or
CMOS devices using external pullup resistors.

Port 3 In Expanded Non-Multiplexed Mode
Port 3 is configured as a bidirectional data bus (07-00) in
the expanded non-multiplexed mode. The direction of data
transfers is controlled by read/write (SC2). Data is clocked
by E (enable).
Port 3 In Expanded-Multiplexed Mode
Port 3 is configured as a time multiplexed address (AO-A7)
and data bus 107-DOl in the expanded-multiplexed modes,
where address strobe (AS) can be used to demultiplex the
two buses. Port 3 is held in a high-impedance state between
valid address and data to prevent bus conflicts.

PORT 3 (P30-P37)
Port 3 can be configured as an I/O port, a bidirectional
8-bit data bus, or a multiplexed address/data bus depending
on the operating mode. The TTL-compatible highimpedance output buffers can drive one Schottky TTL load
and 90 pF. Unused lines can remain unconnected.

I

PORT 4 (P40-P47)
Port 4 is configured as an 8-bit I/O port, as address outputs, or as data inputs depending on the operating mode.
Port 4 can drive one Schottky TTL load and 90 pF and is the
only port with internal pullup resistors. Unused lines can remain unconnected.

Port 3 In Single-Chip Mode
Port 3 is an 8-bit I/O port in the single-chip mode, with
each line configured by the port 3 data direction register.
There are also two lines, IS3 and OS3, which can be used to
control port 3 data transfers.
Three port 3 options are controlled by the port 3 control
and status register and are available only in single-chip
mode: (1) port 3 input data can be latched using IS3 as a
control signal, (2) OS3 can be generated by either an MPU
read or write to the port 3 data register, and (3) an TR01 interrupt can be enabled by an TS3 negative edge. Port 3 latch
timing is shown in Figure 5.

Port 4 In Single-Chip Mode
In single-chip mode, port 4 functions as an 8-bit I/O port
with each line configured by the port 4 data direction
register. Internal pullup resistors allow the port to directly
interface with CMOS at 5 volt levels. External pullup resistors
to more than 5 volts, however, cannot be used.
Port 4 In Expanded Non-Multiplexed Mode
Port 4 is configured from reset as an 8-bit input port,
where the port 4 data direction register can be written to provide any or all of eight address lines, AO to A7. Internal
pullup resistors pull the lines high until the port 4 data direction register is configured.

PORT 3 CONTROL AND STATUS REGISTER

$OOOF

Bit 0-2

Not used.

Bit 3

LATCH ENABLE. This bit controls the
input latch for port 3. If set, input data
is latched by an IS3 negative edge. The
latch is transparent after a read of the
port 3 data register. LATCH ENAB LE
is cleared during reset.
OSS (Output Strobe Select). This bit
determines whether OS3 will be
generated by a read or write of the port
3 data register. When clear, the strobe
is generated by a read; when set, it is
generated by a write. OSS is cleared
during reset.

Bit 4

Bit 5
Bit 6

Bit 7

Port 4 In Expanded-Multiplexed Mode
In all expanded-multiplexed modes except mode 6, port 4
functions as half of the address bus and provides A8 to A 15.
In mode 6, the port is configured from reset as an 8-bit
parallel input port, where the port 4 data direction register
can be written to provide any or all of upper address lines AS
to A15. Internal pullup resistors pull the lines high until the
port 4 data direction register is configured, where bit 0 controls AS.

RESIDENT MEMORY
The MC6801 provides 2048 bytes of on-chip ROM and 12S
bytes of on-chip RAM.
One half of the RAM is powered through the VCC standby
pin and is maintainable during VCC powerdown. This standby portion of the RAM consists of 64 bytes located from $SO
through $BF.
Power must be supplied to Vee standby if the internal
RAM is to be used regardless of whether standby power
operation is anticipated.
The RAM is controlled by the RAM control register.

Not used.
IS3 IRQl ENABLE. When set, an IRQl
interrupt will be enabled whenever IS3
FLAG is set; when clear, the interrupt
is inhibited. This bit is cleared during
reset.
IS3 FLAG. This read-only status bit is
set by an IS3 negative edge. It is
cleared by a read of the port 3 control
and status register (with IS3 FLAG set)
followed by a read or write to the port
3 data register or during reset.

RAM CONTROL REGISTER ($14)
The RAM control register includes two bits which can be
used to control RAM accesses and determine the adequacy
of the standby power source during powerdown operation.
It is intended that RAME be cleared and STBY PWR be set
as part of a powerdown procedure.

3-72

MC6801·MC6803

standby RAM is not valid. This bit can
be set only by software and is not affected during reset.

RAM CONTROL REGISTER
7

6

4

PROGRAMMABLE TIMER
Bit 0-5
Bit 6 RAME

Bit 7 STBY PWR

Not used.
RAM Enable. This read/write bit can
be used to remove the entire RAM
from the internal memory map. RAME
is set (enabled) during reset provided
standby power is available on the positive edge of RESET. If RAME is clear,
any access to a RAM address is external. If RAME is set and not in mode 3,
the RAM is included in the internal
map.
Standby Power. This bit is a
read/write status bit which, when
once set, remains set as long as VCC
standby remains above VSBB (minimum). As long as this bit is set following a period of standby operation, the
standby power supply has adequately
preserved the data in the standby
RAM. If this bit is cleared during a
p'eriod of standby operation, it indicates that VCC standby had fallen to a
level sufficiently below VSBB (minimum) to suspect that data in the
FIGURE 22 -

The programmable timer can be used to perform input
waveform measurements while independently generating an
output waveform. Pulse widths can vary from several microseconds to many seconds. A block diagram of the timer is
shown in Figure 22.
COUNTER ($09:0A)
The key timer element is a 16-bit free-running counter
which is incremented by E (enable). It is cleared during reset
and is read-only with one exception: a write to the counter
($09) will preset it to $FFF8. This feature, intended for
testing, can disturb serial operations because the counter
provides the SCI internal bit rate clock. TOF is set whenever
the counter contains all ones.
OUTPUT COMPARE REGISTER ($OB:OC)
The output compare register is a 16-bit read/write register
used to control an output waveform or provide an arbitrary
timeout flag. It is compared with the freecrunning counter on
each E cycle. When a match occurs, OCF is set and OLVL is
clocked to an output level register. If port 2, bit 1, is configured as an output, OLVL will appear at P21 and the output
compare register and OLVL can then be changed for the next

BLOCK DIAGRAM OF PROGRAMMABLE TIMER

Output
Level
Register
Bit 1
Port 2
DDR

Output Compare Pulse

oJ

Output
Level
Bit 1
Port 2

3-73

Input
Edge
Bit 0
Port 2

I

MC6801·MC6803

compare. The function is inhibited for one cycle after a write
to its high byte ($OB) to ensure a valid compare. The output
compare register is set to $FFFF at RESET.

Bit 5 TOF

Timer Overflow Flag. TOF is set when
the counter contains all ones. It is
cleared by reading the TCSR (with
TOF set) then reading the counter high
byte ($09), or during reset.

Bit 6 OCF

Output Compare Flag. OCF is set
when the output compare register
matches the free-running counter. It is
cleared by reading the TCSR (with
OCF set) and then writing to the output compare register ($OB or $OC), or
during reset.
Input Capture Flag. ICF is set to indicate a proper level transition; it is
cleared by reading the TCSR (with ICF
set) and then the input capture register
high byte ($00), or during reset.

INPUT CAPTURE REGISTER ($OD:OE)

The input capture register is a 16-bit read-only register
used to store the free-running counter when a "proper" input transition occurs as defined by IEDG. Port 2, bit 0 should
be configured as an input, but the edge detect circuit always
senses P20 even when configured as an output. An input
capture can occur independently of ICF: the register always
contains the most current value. Counter transfer is inhibited, however, between accesses of a double byte MPU
read. The input pulse width must be at least two E cycles to
ensure an input capture under all conditions.

I

Bit 7 ICF

TIMER CONTROL AND STATUS REGISTER ($08)

The timer control and status register (TCSR) is an 8-bit
register of which all bits are readable, while only bits 0-4 can
be written. The three most-significant bits provide the timer
status and indicate if:

SERIAL COMMUNICATIONS INTERFACE (SCI)
A full-duplex asynchronous serial communications interface (SCI) is provided with two data formats and a variety of
rates. The SCI transmitter and receiver are functionally independent, but use the same data format and bit rate. Serial
data formats include standard mark/space (NRZ) and Biphase and both provide one start bit, eight data bits, and one
stop bit. "Baud" and "bit rate" are used synonymously in
the following description.

• a proper level transition has been detected,
• a match has occurred between the free-running
counter and the output compare register, and
• the free-running counter has overflowed.
Each of the three events can generate an IR02 interrupt
and is controlled by an individual enable bit in the TCSR.
TIMER CONTROL AND STATUS REGISTER (TCSR)
7

6

5

4

3

2

1

WAKE-UP FEATURE

0

In a typical serial loop mUlti-processor configuration, the
software protocol will usually identify the addressee(s) at the
beginning of the message. In order to permit uninterested
MPU's to ignore the remainder of the message, a wake-up
feature is included whereby all further SCI receiver flag (and
interrupt) processing can be inhibited until its data line goes
idle. An SCI receiver is re-enabled by an idle string of ten
consecutive ones or during reset. Software must provide for
the required idle string between consecutive messages and
prevent it within messages.

ICF I OCF I TOF I EICI I EOCII ETOIIIEDG IOLVLI $0008

Bit 0 OLVL

Bit 1 EIDG

Bit 2 ETOI

Bit 3 EOCI

Bit4 EICI

Output Level. OLVL is clocked to the
output level register by a successful
output compare and will appear at P21
if bit 1 of the port 2 data direction
register is set. It is cleared during reset.
Input Edge. IEDG is cleared during
reset and controls which level transition will trigger a counter transfer to
the input capture register:
IEDG = 0 Transfer on a negative-edge
IEDG = 1 Transfer on a positive-edge.
Enable Timer Overflow Interrupt.
When set, an IR02 interrupt is enabled
for a timer overflow; when clear, the
interrupt is inhibited. It is cleared during reset.
Enable Output Compare Interrupt.
When set, an IR02 interrupt is enabled
for an output compare; when clear,
the interrupt is inhibited. It is cleared
during reset.
Enable Input Capture Interrupt. When
set, an IR02 interrupt is enabled for an
input capture; when clear, the interrupt is inhibited. It is cleared during
reset.

PROGRAMMABLE OPTIONS

The following features of the SCI are programmable:
• format: standard mark/space (NRZ) or Bi-phase
• clock: external or internal bit rate clock
• Baud: one of four per E clock frequency, or external
clock ( x 8 desired baud)
• wake-up feature: enabled or disabled
• interrupt requests: enabled individually for transmitter
and receiver
• clock output: internal bit rate clock enabled or disabled
to P22
SERIAL COMMUNICATIONS REGISTERS

The serial communications interface
dressable registers as depicted in Figure
by the rate and mode control register
receive control and status register. Data

3-74

includes four ad23. It is controlled
and the transmit!
is transmitted and

MC6801-MC6803

received utilizing a write-only transmit register and a readonly receive register. The shift registers are not accessible to
software.

time and rates for three selected MCU
frequencies.
Bit 3:Bit 2

CC1: CCO Clock Control and Format
Select. These two bits control the format and select the serial clock source.
If CCl is set, the DDR value for P22 is
forced to the complement of CCO and
cannot be altered until CCl is cleared.
If CCl is cleared after having been set,
its DDR value is unchanged. Table 7
defines the formats, clock source, and
use of P22.

Rate and Mode Control Registers (RMCR) ($10)

The rate and mode control register controls the SCI bit
rate, format, clock source, and under certain conditions, the
configuration of P22. The register consists of four write-only
bits which are cleared during reset. The two least-significant
bits control the bit rate of the internal clock and the remaining two bits control the format and clock source.
RATE AND MODE CONTROL REGISTER (RMCR)
7

I

X

4

6

I

Bit l:Bit 0

X

I

X

3

2

1

If both CCl and CCO are set, an external TTL-compatible
clock must be connected to P22 at eight times (8X) the
desired bit rate, but not greater than E, with a duty cycle of
50% (± 10%). If CCl :CCO= 10, the internal bit rate clock is
provided at P22 regardless of the values for TE or RE.

0

I X I CCl I cco I SSl I sso I

$0010

SSl:SS0 Speed Select. These two
bits select the baud rate when using
the internal clock. Four rates may be
selected which are a function of the
MCU input frequency. Table 6 lists bit

NOTE: The source of SCI internal bit rate clock is the timer
free-running counter. An MPU write to the counter
can disturb serial operations.

FIGURE 23 - SCI REGISTERS

Bit 7

Rate and Mode Control Register
CCl

I

Bit 0

I Icco I Isso I
SSl

$10

Transmit/Receive Control and Status Register

RDRF IORFE ITDREI RIE I

RE

I I I
TIE

TE

wu

I

$11

Receive Data Register
$12

Port 2

INot Addressable)
Receive Shift Register

10

Transmit Shift Register
12

$13

Transmit Data Register

3-75

I

MC6801·MC6803

Transmit/ Receive Control And Status Register
(TRCSR) ($11)

RDRF and/or ORFE is set; when clear,
the interrupt is inhibited. RIE is cleared
during reset.

The transmit! receive control and status register controls
the transmitter, receiver, wake-up feature, and two individual interru~ts and monitors the status of serial operations. All eight bits are readable while bits 0 to 4 are also
writable. The register is initialized to $20 by RESET.

Bit 5 TDRE

Transmit Data Register Empty. TDRE
is set when the transmit data register is
transferred to the output serial shift
register or during reset. It is cleared by
reading the TRCSR (with TDRE set)
and then writing to the transmit data
register. Additional data will be
transmitted only if TDRE has been
cleared.

Bit 6 ORFE

Overrun Framing Error. If set, OR FE indicates either an overrun or framing error. An overrun is a new byte ready to
transfer to the receiver data register
with RDRF still set. A receiver framing
error has occurred when the byte
boundaries of the bit stream are not
synchronized to the bit counter. An
overrun can be distinguished from a
framing error by the state of RDRF: if
RDRF is set, then an overrun has occurred; otherwise a framing error has
been detected. Data is not transferred
to the receive data register in an overrun condition. Unframed data causing
a framing error is transferred to the
receive data register. However, subsequent data transfer is blocked until the
framing error flag is cleared. * ORFE is
cleared by reading the TRCS R (with
ORFE set) then the receive data
register, or during reset.

Bit 7 RDRF

Receive Data Register Full. RDRF is
set when the input serial shift register
is transferred to the receive data
register. It is cleared by reading the
TRCSR (with RDRF set), and then the
receive data register, or during reset.

TRANSMIT/RECEIVE CONTROL AND STATUS
REGISTER (TRCSR)
76543210
IRDRFIORFEITDREI RIE I RE I TIE

I

I TE IWU I $0011

Bit 0 WU

"Wake-up" on Idle Line. When set,
WU enables the wake-up function; it is
cleared by ten consecutive ones or
during reset. WU will not set if the line
is idle.

Bit 1 TE

Transmit Enable. When set, P24 DDR
bit is set, cannot be changed, and will
remain set if TE is subsequently
cleared. When TE is changed from
clear to set, the transmitter is con=
nected to P24 and a preamble of nine
consecutive ones is transmitted. TE is
cleared during reset.

Bit 2 TIE

Transmit Interrupt Enable. When set,
an IRQ2 interrupt is enabled when
TDRE is set; when clear, the interrupt
is inhibited. TE is cleared during reset.

Bit 3 RE

Receive Enable. When set, the P23
DDR bit is cleared, cannot be changed, and will remain clear if RE is subsequently cleared. While RE is set, the
SCI receiver is enabled. RE is cleared
during reset.

Bit 4 RIE

Receiver Interrupt Enable. When set,
an IRQ2 interrupt is enabled when
TABLE 6 - SCI BIT TIMES AND RATES
4fo SS1:SS0
E
0
0
+16
1
+
128
0
1
+ 1024
0
1
1
+4096
* External (P22)

2.4576 MHz
614.4 kHz
26 !Ls/38,400 Baud
208,",s/4,800 Baud
1.67 ms/600 Baud
6.67 ms/150 Baud
13.0,",s176,800 Baud

4.0 MHz
1.0 MHz
16 ,",s/62,500 Baud
128 ,",sI7812.5 Baud
1.024 ms/976.6 Baud
4.096 ms/244.1 Baud
8.0 ,",sl 125,000 Baud

4.9152 MHz
1.2288 MHz
13.0 ,",s176,800 Baud
104.2 ,",s/9,600 Baud
833.3 ,",sl 1,200 Baud
3.33 ms/300 Baud
6.5 ,",s/153,600 Baud

* Using maximum clock rate
TABLE 7 - SCI FORMAT AND CLOCK SOURCE CONTROL
CC1:CCO
00
01
10
11

Clock
Source
Bi-Phase Internal
NRZ
Internal
NRZ
Internal
NRZ
External
Format

Port 2
Bit 2
Not Used
Not Used
Output
Input

* Devices made with mask number M5G, M8D, and T5P do not transfer unframed data to the receive data register.

3-76

MC6801·MC6803

executable instruction is sufficient to identify the instruction
and the addressing mode. The hexadecimal equivalents of
the binary codes, which result from the translation of the 82
instructions in all valid modes of addressing, are shown in
Table 8. There are 220 valid machine codes, 34 unassigned
codes, and 2 codes reserved for test purposes

SERIAL OPERATIONS

The SCI is initialized by writing control bytes first to the
rate and mode control register and then to the transmit!
receive control and status register. When TE is set, the output of the transmit serial shift register is connected to P24
and serial output is initiated by transmitting a 9-bit preamble
of ones.
At this point one of two situations exist: 1) if the transmit
data register is empty (TDRE= 1), a continuous string of
ones will be sent indicating an idle line, or 2) if a byte has
been written to the transmit-data register (TDRE=O), it will
be transferred to the output serial shift register (synchronized with the bit rate clock), TDRE will be set, and transmission will begin.
The start bit (0), eight data bits (beginning with bit 0) and a
stop bit (1), will be transmitted. If TDRE is still set when the
next byte transfer should occur, ones will be sent until more
data is provided. In Bi-phase format, the output toggles at
the start of each bit and at half-bit time when a one is sent.
Receive operation is controlled by RE which configures P23
as an input and enables the receiver. SCI data formats are illustrated in Figure 24.

PROGRAMMING MODEL

A programming model for the MC6801/03 is shown in
Figure 10. Accumulator A can be concatenated with accumulator B and jointly referred to as accumulator D where
A is the most-significant byte. Any operation which modifies
the double accumulator will also modify accumulator A
and/or B. Other registers are defined as follows:
Program Counter - The program counter is a 16-bit
register which always points to the next instruction.
Stack Pointer - The stack pointer is a 16-bit register
which contains the address of the next available location in a
pushdown/ pullup (LI Fa) queue. The stack resides in random access memory at a location defined by the programmer.
Index Register - The index register is a 16-bit register
which can be used to store data or provide an address for the
indexed mode of addressing.

INSTRUCTION SET

Accumulators - The MPU contains two 8-bit accumulators, A and B, which are used to store operands and results
from the arithmetic logic unit (ALU). They can also be concatenated and referred to as the D (double) accumulator.

The MC6801/03 is upward source and object code compatible with the MC6800. Execution times of key instructions
have been reduced and several new instructions have been
added, including a hardware multiply. A list of new operations added to the MC6800 instruction set is shown in Table

Condition Code Registers - The condition code register
indicates the results of an instruction and inciudes the
following five condition bits: negative IN), zero (Z), overflow
(V), carry/borrow from MSB (C), and half carry from bit 3
(H). These bits are testable by the conditional branch instructions. Bit 4 is the interrupt mask (I bit) and inhibits all
maskable interrupts when set. The two unused bits, B6 and
B7, are read as ones.

1.

In addition, two new special opcodes, 4E and 5E, are provided for test purposes. These opcodes force the program
counter to increment like a 16-bit counter, causing address
lines used in the expanded modes to increment until the
device is reset. These opcodes have no mnemonics.
The coding of the first (or only) byte corresponding to an

FIGURE 24 -

SCI DATA FORMATS

Output

Clock

NRZ
Format

I,

Bi-Phase
Format
Idle Start

Bit

Bit

o

Data: 01001101 ($40)

3-77

4

7

Stop

I

MC6801·MC6803

eliminating the additional memory access. In most applications, the 256-byte area is reserved for frequently referenced
data.
Extended Addressing - The second and third bytes of the
instruction contain the absolute address of the operand.
These are three byte instructions.
Indexed Addressing - The unsigned offset contained in
the second byte of the instruction is added with carry to the
index register and used to reference memory without changing the index register. These are two byte instructions.
Inherent Addressing - The operand(s) are registers and
no memory reference is required. These are single byte instructions.
Relative Addressing - Relative addressing is used only for
branch instructions. If the branch condition is true, the program counter is overwritten with the sum of a signed single
byte displacement in the second byte of the instruction and
the current program counter. This provides a branch range
of -126 to 129 bytes from the first byte of the instruction.
These are two byte instructions.

ADDRESSING MODES
Six addressing modes can be used to reference memory.
A summary of addressing modes for all instructions is present in Tables 9 through 12, where execution times are provided in E cycles. Instruction execution times are summarized in Table 13. With an input frequency of 4 MHz, E
cycles are equivalent to microseconds. A cycle-byccycle
description of bus activity for each instruction is provided in
Table 14 and a description of selected instructions is shown
in Figure 25.
Immediate Addressing - The operand or "immediate
byte(s)" is contained in the following byte(s) of the instruction where the number of bytes mat:::hes the size of the
register. These are two or three byte instructions.
Direct Addressing - The least-significant byte of the
operand address is contained in the second byte of the instruction and the most-significant byte is assumed to be $00.
Direct addressing allows the user to access $00 through $FF
using two byte instructions and execution time is reduced by

OP

MNEM

MODE

-

,

00
01

NOP

02

INHER

2

1

~

TABLE 8 - CPU INSTRUCTION MAP
OP

MNEM

MODE

34

INHER

-

,

3
3

1
1

OP

MNEM

MODE

-

68

ASL
ROL

INDXD

5

35

DES
TXS

36

PSHA

3

1

59
5A

DEC

1

#

OP

MNEM

MODE

-

9C
9D

CPX
JSR

DIR

5

6

2
2

5

2

9E
9F

LDS
STS

5

2

SU8A

5

2

AO
A1

CMPA

3

2

A2

S8CA

37

PSH8

3

1

58

04
05
06

LSRD

3

1

36

PULX

1

ASLD
TAP

3

1

39

RTS

5
5

1

6C
6D

INC
TST

1

3A

A8X

3

1

6E

JMP

07

TPA

2
2

3B

RTI

10

5F

CLR

INDXD

08
09

INX

3

1
1

1

3C

PSHX

4

1

70

NEG

EXTND

3D
3E
3F

MUL
WAI

10

71

SW!

9
12

1
1

73

COM

5

40
41

NEGA

2

1
1

74

03

OA
OB
OC

DEX
CLV
SEV

3
2

1
1

2

1

CLC

2

1

OD

SEC

2

1

OE
OF

CLI

2

42

SEI

2

1
1

43

COMA

2

10
11

SBA

2

1

44

LSRA

CBA

2

1

45

12

45
47

13
14

48
49

15
15

TAB

2

1

4A

17

TBA

2

1

4B

18
19

LSR

5

3

ROR

5

3

1

77

ASR

5

3

2

1

78

ASL

5

3

75

79

ROL

5

3

RORA

2

1

7A

DEC

5

3

ASRA
ASLA

2
2

1
1

7B
7C

ROLA
DECA

2

1

7D

INC
TST

2

1

7E
7F

JMP

,

CLR

EXTND

3
5

SUBA

IMMED

2

2

4D
4E

TSTA

4F

CLRA

2

1C

50

NEGB

2

10

51

85

BITA

1E
1F

52

85
87

2

1

IA
IB

ABA

INHER

2

1

2
2

1
1

6

3

5

3
3

CMPA

2

2

82

SBCA

2

1

83

3

1

84

SUBD
ANDA

2
4
2

2

lOAA

2
2

2
2
2
2

T

53

COMB

2

1

3

2

54

LSRB

2

1

88

EORA

2

3
3

2

55

ADCA

2

2

56

RORB

2

1

89
8A

BLS

3

ASRB

3

2
2

57

BCC

56

ASLB

2
2

1
1

25

BCS

3

2

2

BNE
BEG

3
3

2
2

59
5A

ROLB

25
27

DECB

2

28

BVC

3

2

INCB

29
2A

BVS

3

2

5D

TSTB

BPL

3

2

T

2B

BMI

3

2

5E
5F

2C
2D

BGE

22
23
24

2E
2F
30
31
32
33

BRA

REL

3
3

2
2

60
61

3

2

62

REL
INHER

3
3

2
1

63

64

t

3
4

1

65

1

4

1

66
67

BLT
BGT
BLE

1SX
INS
PULA
PULB

NOTES:

CLRB
NEG

COM
LSR
ROR
ASR

INHER
INDXD

1

INDXD

ORAA

2

2

IMMED

2
4

3

BSR

REL

5

2

LDS

IMMED

3

3

90

SUBA

DIR

8B

ADDA

BC

CPX

1

8D

1

8E
8F

2

1

2

1

5B
5C

2

1

6

2

6
6

3

80
81

BRN
BHI

20
21

3

75

INCA

INHER

2
3

72

4C
DAA

5
5

2
2

3

2

2

91

CMPA

3

2

92

SBCA

2

93

SUBD
ANDA

3
5

94

2

3

2

95

BITA

3

2

96

LDAA

3

2

97

STAA

3

EORA
ADCA

3
3

2
2
2

DRAA
ADDA

3

2

3

2

6

2

98
99
9A

6

2

9B

A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B5
B7
B8
B9
BA
BB
BC
BD
BE
BF
CO
C1
C2
C3
C4
C5
C6
r:7
C8
C9
CA
CB
CC
CD
CE
CF

1. Addressing Modes
INHER '" Inherent
INOXO "" Indexed
IMMEO "" Immediate
REL"" Relative
EXTNO""Extended OIR""Oirect
2. Unassigned opcodes are indicated by "e" and should not be executed.
3. Codes marked by "T" force the PC to function as a 16-bit counter

3-78

-

#

3
3

2
2

S8C8

3

2

ADDD
ANDB

5

2

D4

2

D5

BITB

3

2

2
2

D5
D7

LDAB

3

2

STAB

3

2

3
3

2

3
3
4

2
2
2

4

2

#

OP

MNEM

MODE

DO
D1

SUBB
CMP8

DIR

5

2
2

4

2

D2

DIR

4

2

D3

INDXD

4

2

4
4

~

SUBD
ANDA

5
4

2

DB

EORB

BITA

4

2

ADCB

LDAA
STAA

4
4

2
2

D9
DA
DB

3

ORAB
ADDB
LDD

2

2

EORA

4

2

ADCA

4

2

DC
DD

ORAA
ADDA

4

2

DE

STD
LDX

4

2

DF

STX

DIR

4

2

CPX

5

2

SUBB

INDXD

4

2

4

2

6

2

EO
E1

4

2

5

2

E2

SBCB

4

2

5
4

2
3

E3
E4

ADDD
AN DB

5
4

2
2

3
3

E5
E5

BITB
lOAB

4

SBCA

4
4

4

2
2

SUBD
ANDA

5
4

3

E7

STAB

4

2

3

E8

EORB

4

2

BITA

4

3

ADCB

4

LDAA

4

3

E9
EA

ORAB

4

2

STAA

4

3

EB

ADDB

4

2

EORA

4

3

EC

LDD

5

2

ADCA
ORAA

4
4

3
3

ED
EE

STD
LDX

5
5

2
2

5
4

3

4

3

JSR
lOS
STS
SU8A

INDXD
EXTND

CMPA

CMPB

ADDA

4

3

EF

STX

INDXD

CPX

5

3

5

3
3

FO
F1

SUBB
CMPB

EXTND

JSR

2

2

SBCB

4

3

EXTND

5
5

F2

STS

3

F3

ADDD

6

3

SUBB
CMPB

IMMED

2

2

F4

ANDB

2

2

F5

3

2
4

2
3

F6
F7

BITB
LDAB
STAB

4
4
4
4

3
3

LDS

SBCB
ADDD

F8

3

AN DB

2

2

EORB

4

3

BITB

2

2

F9

ADCB

LDAB

/

2

FA

DRAB

4
4

3

FB

ADDB

4

3

3

EORB
ADCB

2

2

FC

LDD

5

3

2

2

FD

STD

5

3

DRAB

2

FE

3

2

LDX
STX

5

ADDB

2
2

5

3

LDD

3

3

FF

EXTND

* UNDEFINED OP
LDX

IMMED

3

3

CODE

MC6801·MC6803

TABLE 9 -

INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS
Condition Codes
Immed

Pointer Operations

# Op -

MNEM Op -

Compare Index Register

CPX

Decrement Index Register

DEX

3 9C

8C 4

Index

Direct

5

Extnd

# Op

# Op 2 AC 6

Inherent

-

# Op

2 BC 6

Boolean/
Arithmetic Operation

-

#

3

1 X-1 ..... X

X-M:M+l

3
09

Decrement Stack Pointer

DES

34

3

1 SP-1-SP

Increment Index Register

INX

08

3

1 X+1-X

Increment Stack Pointer

INS

31

3

1 lSP+1 ..... SP

Load Index Register

LOX

CE 3

3 DE 4

2 EE 5

2

5

3

M ..... XH,IM+lI-XL

Load Stack Pointer

LDS

8E

3 9E

4

2 AE 5

2 BE 5

3

M

Store Index Register

STX

DF 4

2 EF 5

2

FF

5

3

XH-M,XL ..... IM+ 11

Store Stack Painter

STS

9F

2 AF 5

2 BF b

3

SPH ..... M,SPL -IM+11

Index Reg -

3

4

FE

TXS

35

3

1 X-1-SP

TSX

30

3

1 SP+ 1-X

Add

ABX

3A 3

1 B+X-X

Push Data

PSHX

3C 4

1 XL - MSp,SP-1 - SP
XH ..... MSP,SP-1 ..... SP

Pull Data

PULX

38

Stack Pointer

5

1 SP+ 1 SP+ 1 -

4

3

2

1

0

H

I

N

Z

V

C

· ·· 1 11 ·1 ·1
·1 · ··
·· ·· ·tt · ··
1
· ·· ·1_ ··
· · · ···
· ·· ·· ·
···
R

SPH,IM+lI ..... SPL

StacK Pntr ..... Index Register

5

R
R

SP,MSp ..... XH
SP,MSp ..... XL

R

TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 1 of 2)
Condition Codes
Accumulator and
Memory Operations

Immed
MNEM Op

-

Direct

# Op -

Index

# Op -

Extend

# Op -

Inher

# Op -

Add Accumulators

ABA

1B

Add B to X

ABX

3A 3

Add with Carry

ADCA 89

2

ADCB C9 2

2

2 99

3

2

Boolean
Expression

#

A+M+C ..... A

2

B9 4

3

2

F9

4

3

B+M+C ..... B

2 BB 4

3

A+M ..... A

2 9B

3

2 AB 4

E9

Add

ADDA 8B

ADDB CB 2

2 DB 3

2 EB 4

2 FB 4

3

B+M-A

Add Double

ADDD C3 4

3 D3 5

2

2

F3

6

3

D+M:M+1 ..... D

And

ANDA 84

2 94

2 A4 4

2

B4 4

3

A.M-A

E4

4

2

F4

4

3

B.M ..... B

68

6

2

78

6

3

2

ANDB C4 2
Shift Left, Arithmetic

2

ASL

6

ASLA

48

2

1

ASLB

58

2

1

05

3

1

ASRA

47

2

1

ASRB

57

2

1

Shift Left Double

ASLD

Shift Right, Arithmetic

ASR

Bit Test

3

2 D4 3

E3

67

BITA 85
BITB

Compare Accumulators

CBA

Clear

CLR

2

C5 2

2 95

3

2 D5 3

6

2

77

6

3

2

2

F5

3

B·M

4

4

11
6F

6

2 7F

6

5F

CLRB

l's Complement

2

1 00"'" A

2

1 00 ..... B

2

2 91

3

2 A1

CMPB C1

2

2 D1

3

2 E1

4

2

F1

4

3

B-M

63

6

2

73

6

3

M

COM

4

--0

bO

43

2

1 A"'" A

53

2

1 B-B

R
R

··

t t t t
t

· ·· 1t 1t t
·· 1 1
··
·· 1 1

M

COMB

1 ~11

··
·
··

A-M

3

COMA

3-79

C

1 A-B

CMPA 81

2 B1

0

V

oo ..... M
4F

4

2

3

CLRA
Compare

b7

A.M

E5

--

qllil IIII-~

2 B5 4

1

Z

t

bO

2 A5 4

2

N

1
1

@]-jb711111111

3

3

I

1

4

2

4

H

·t ·· · ·

1 A+ B ..... A
1 oo:B+ X ..... X

2 A9 4

2 D9 3

5

·

R

t t

R

R

S

R

R

R

S

R

R

R

S

R

R

1 1

1 1

t t t t
Itt R S
t t R S
t t R S

I

MC6801·MC6803

TABLE 10 -

ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 2 of 2)
Condition Codes

Accumulator and
Memory Operations

Immed
MNEM Op

DeCimal Adjust, A

DAA

Decrement

DEC

Exclusive OR
Increment

-

Direct

Index

# Op -

# Op -

Extend

Inher

# Op -

# Op -

2 7A

3

19
6A 6

6

4A

2

1 B-1-B

EORA 88

2

2 98

E:ORB C8

2

2 D8 3

3

2 A8 4

2 B8 4

3

A$M-A

2

B$M-B

INC

E8

4

2

F8

4

3

6C

6

2 7C

6

3

Push Data
Pull Data

Rotate Right

Subtract Accumulator
Subtract with Carry
Store Accumulators

M-A

2

F6

4

3

M-B

3 DC 4

2 EC 5

2 FC

5

3

M:M+1-D

68

2 78

6

3

CC 3

E6

4
6

48

2

1

58

2

1

05

3

2

LSRA

44

2

1

LSRB

54

2

1

LSRD

04

3

1

MUL

3D 10

1 AxB-D

40

2

1 oo-A-A

NEGB

50

2

1 00- B-B

NOP

01

2

1 PC+ 1 - PC

64

NEG

60

6

6

2

74

2 70

6

6

b7

2 BA 4

3

A+M-A

2 FA 4

3

B+M-B
36

3

37

3

1 B-

PULA

32

4

1 Stack -

33

4

1 Stack- B

ROLA

49

2

1

ROLB

59

2

1

RORA

46

2

1

RORB

56

2

1

SBA

10

2

1 A-B-A

ROR

66

6

2

76

6

A

3

3

@].-111111111-§
b7

b7

A-M-C-A

2

2

2 A2 4

2 82 4

3

2

2 D2 3

2

E2

4

2

F2

4

3

B-M-C-B

STAA

97

3

2

A7 4

2

B7 4

3

A-M

STAB

D7 3

2

E7

2

F7

4

3

B-M

STD

DD 4

2 ED 5

2 FD 5

3

D-M:M+1

3

2 AO 4

2 BO 4

3

A-M-A

2 DO 3

2 EO 4

2

FO 4

3

B-M-B

3 93

2 A3 6

2 B3 6

3

Subtract Double

SUBD 83

2

SUBB CO 2
4

2 90

5

4

D-M:M+1-D

TAB

16

2

1 A-B

TBA

17

2

1 B-A

TST

6D 6

2 7D 6

M-oo

3

TSTA

4D

2

1 A-oo

TSTB

5D 2

1 B-oo

The condition code register notes are listed after Table 12.

3-80

bO

@-IIIIIIIII-@]

S8CB C2

3

R
R

R

Stack

SBCA 82

92

· ·· tt tt tt t
· ·· tt tt tt
· · tt tt
·t t t
·
· ·· tt tt tt ·
· ·· tt tt ·
·· tt tt t ·t
· · tt tt tt tt
t t t t
· ··· tt tt tt
·· ·· tt tt tt
t
· ·tt ·tt tt tt
··t t t t
· · ·l l · ·
· · ·t t ·
· · ·· ··· · ···
· · ·t ·t ·t ·t
·· · tt tt tt tt
t t t t
·· tt tt tt tt
·· tt tt tt tt
· · tt tt t ·t
· tt tt ·
t t t ·t
· tt tt tt tt
t t
· · tt tt ··
·· tt tt
R

1 A-Stack

PSHB

6

bO

oo-M-M

3

2 AA 4

6

0

R

2 EA 4

69

V C

R

2 9A 3

2 79

-0

bO

o -IIIIIIIII-~

2 DA 3

SUBA 80

T est, Zero or Minus

b7

2

ROL

1

Z

R

3

PSHA

2

N

R

@] ~ 11111111

DRAB CA 2

DRAA 8A

3

I

R

LSLB
LSR

4

H

R

LSLA

Subtract

Transfer Accumulator

1 B+1-B

2

2

PULB
Rotate Left

2

2 D6 3

LDAB C6

3

NEGA

Inclusive OR

5C
3

2 96

LSLD

No Operation

1 A+1-A

2 B6 4

2

LSL

2

5

R

M+ 1-M
4C

2 A6 4

LDAA 86
LDD

2's Complement (NegateJ

M-1-M
5A 2

Logical Shift, Left

Multiply

1 Adj binary sum to BCD

DECB

Load Double

Shift Right, Logical

2

DECA

INCB

I

#

1 A-1-A

INCA
Load Accumulators

Boolean
Expression

bO

R
R

R

R
R
R

R

R

R

R

R

MC6801·MC6803

TABLE 11 - JUMP AND BRANCH INSTRUCTIONS
Condition Code Reg.
Operations

Direct
Relative
Index
Extend
Inherent
# Op # Op - # Op - # Op - #
MNEM Op

-

Branch Always

BRA

Branch Never
Branch If Carry Clear
Branch If Carry Set

BCS

Branch If ~ Zero

BEG

Branch If ;;,:Zero

BGE

2C

> Zero

BGT

2E

Branch if

543210
H I N Z V C

Branch Test

20

3

None

BRN

21

3

BCC

24

3

2

25

3

2

C~1

27

3

2

Z~1

3

2

None
C~O

NEDV~O

Z+INEDVI~O
C+Z~O

Branch If Higher

BHI

22

Branch If Higher or Same

BHS

24

3

2

C~O

Branch If ",Zero

BLE

2F

3

2

Z+(NEDVI~1

Branch If Carry Set

BLO

25

3

2

C~1

Branch If Lower Or Same

BLS

23

3

2

C+Z~1

Branch If 

.::

.t::

'i

2
3

••
•
••
•••
•3

C

III

•••
•2
3
2

••
••
•
•••
•••
•
•••
•
•••
•

!as

III

!

'6
III

as

E
.§

IE:

INX
JMP
JSR
LOA
LDD
LOS
LOX
LSL
LSLD
LSR
LSRD
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI

3
3
3
3
3
3

•

3
3
3
3
3
3
3
3
3
6
3
3

2
2
2
2
2

•2
•2
2
3
3

••3

3-82

•
••
2
3
3
3

•
•••
•
••
2
••
••
••
•••
2
•
••
••
••2
••
••
•
••
•
•
4

"0

III

III

C

III

III

"0

ti

"0
C

0

w

.::

••
5

•3

•3

6
4
5
5
5
6

6

!

3
4
4
4

!

)(

)(

"0

4

5
5
5
6

•••
•••
•3
•••
•••
••
•3
•
••3

•6
•
•6
•
•
••
•6
6
••
•
•
••
4

•
•
•
•
•••
•
•••
•
••

4
4
4

5
5
5

5
5
5

3
5

4

4

•••
••
••
•
•

4

4

6

•

••
•
•6
••
•

6

6

4

6
6

4

4

6

••
•
••
•••
6

!

.t::

.::
3

••
•••
•2
3
2
3
10
2
2

•
3

4
4

III

.~
as

'ii

IE:

••
••
••
•••
••
••
••
••

5
2
2
10
5
2

•2
2
2

••
••
••
12
2
2
2
2
2
3
3
9

•

MC6801·MC6803

SUMMARY OF CYCLE-BY-CYCLE OPERATION
Table 14 provides a detailed description of the information
present on the address bus, data bus, and the read/write
(R/W) line during each cycle of each instruction.
The information is useful in comparing actual with expected results during debug of both software and hardware
as the program is executed. The information is categorized in
groups according to addressing mode and number of cycles

TABLE 14 Address Mode and
Instructions

per instruction. In general. instructions with the same addressing mode and number of cycles execute in the same
manner. Exceptions are indicated in the table.
Note that during MPU reads of internal locations, the
resultant value will not appear on the external data bus except in mode O. "High order" byte refers to the mostsignificant byte of a 16-bit value.

CYCLE-BY-CYCLE OPERATION (Sheet 1 of 5)

R/W
Address Bus

Data Bus

Line

IMMEDIATE
2

1
2

Opcode Address
Opcode Address+ 1

1
1

Opcode
Operand Data

LDS
LDX
LDD

3

1
2

Opcode Address
Opcode Address+ 1
Opcode Address + 2

1
1
1

Opcode
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

CPX
SUBD
ADDD

4

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address Bus FFFF

1
1
1
1

Upcode
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Address of Operand

1
1
1

Opcode
Address of Operand
Operand Data

Opcode Address
Opcode Address + 1
Destination Address

1
1

0

Opcode
Destination Address
Data from Accumulator

Opcode Address
Opcode Address+ 1
Address of Operand
Operand Address + 1

1
1
1
1

Opcode
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Opcode Address
Opcode Address+ 1
Address of Operand
Address of Operand + 1

1
1

0
0

Opcode
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)

Opcode Address
Opcode Address+ 1
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1

Opcode
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address+ 1
Subroutine Address
Stack Pointer
Stack Pointer-l

1
1
1

Opcode
Irrelevant Data
First Subroutine Opcode
Return Address (Low Order Byte)
Return Address (High Order Byte)

ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB

3
1
2

3
4

DIRECT
ADC
ADD
AND
BIT
CMP
STA

EOR
LDA
ORA
SBC
SUB

3

1
2

3

3

1
2

3
LDS
LDX
LDD

4

1
2

3
4

STS
STX
STD

4

1
2

3
4

CPX
SUBD
ADDD

5

1
2

3
4

5
JSR

5

1
2

3
4

5

0
0

I

MC6801·MC6803

TABLE 14 Address Mode and
Instructions

CYCLE-BY-CYCLE OPERATION (Sheet 2 of 5)
R/W
Line

Address Bus

Data Bus

EXTENDED

3

JMP

1
2

3
ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB

STA

4

1
2

3
4
4

1
2

3
4

I

LDS
LDX
LDD

5

1
2

3
4

5
5

STS
STX
STD

1
2

3
4

5
ASL
ASR
CLR
COM
DEC
INC
CPX
SUBD
ADDD

LSR
NEG
ROL
ROR
TST*

6

1
2

3
4

5
6
6

1
2

3
4

5
6
JSR

6

1
2

3
4

5
6

Opcode Address
Opcode Address + 1
Opcode Address + 2

1
1
1

Opcode
Jump Address (High Order Byte)
Jump Address (Low Order Byte)

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand

1
1
1
1

Opcode
Address of Operand
Address of Operand (Low Order Byte)
Operand Data

Opcode Address
Opcode Address + 1
Opcode Address + 2
Operand Destination Address

1
1
1

0

Opcode
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand
Address of Operand + 1

1
1
1
1
1

Opcode
Address
Address
Operand
Operand

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand
Address of Operand + 1

1
1
1

Opco<;le
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

0
0
1
1
1
1
1

of Operand (High Order Byte)
of Operand (Low Order Byte)
Data (High Order Byte)
Data (Low Order Byte)

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand
Address Bus FFFF
Address of Operand

0

Opcode
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data

Opcode Address
Opcode Address+ 1
Opcode Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1
1

Opcode
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Opcode Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer-l

1
1
1
1

Opcode
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

0
0

* TST does not perform the write cycle during the sixth cycle The sixth cycle is another address bus= $FFFF

3-84

MC6801·MC6803

TABLE 14 -

R/W

Address Mode and
Instructions

3

,
,
2

3
ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB

STA

4

2

3
4
4

,
2

3

,

4

5

LDS
LDX
LDD

2

3
4

,

5
5

STS
STX
STD

2

3
4

,

5
ASL
ASR
CLR
COM
DEC
INC
CPX
SUBD
ADDD

LSR
NEG
ROL
ROR
TST*

6

2

3
4

5
6
6

,

2

3
4

5
6
JSR

Line

Address Bus

INDEXED
JMP

CYCLE-BY-CYCLE OPERATION (Sheet 3 of 5)

6

,

2

3
4

5
6

Opcode Address
Opcode Address+'
Address Bus FFFF

,,
,,,
,,
,,
,,,
,,
,
1

Opcode Address
Opcode Address + ,
Address Bus FFFF
Index Register Plus Offset
Opcode Address
Opcode Address + ,
Address Bus FFFF
Index Register Plus Offset

Opcode Address
Opcode Address+ ,
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset+ ,
Opcode Address
Opcode Address + ,
Address Bus FFFF
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset
Opcode Address
Opcode Address + ,
Address Bus FFFF
Index Register+ Offset
Index Register+ Offset+'
Address Bus FFFF
Opcode Address
Opcode Address + ,
Address Bus FFFF
Index Register+ Offset
Stack Pointer
Stack Pointer-'

Opcode
Offset
Low Byte of Restart Vector

1

Opcode
Offset
Low Byte of Restart Vector
Operand Data

1

Opcode
Offset
Low Byte of Restart Vector
Operand Data

0

Opcode Address
Opcode Address + ,
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + ,

Data Bus

Opcode
Offset
Low Byte of Restart Vector
Operand Data I High Order Byte)
Operand Data ILow Order Byte)

0
0

Opcode
Offset
Low Byte of RestartVector
Operand Data IHigh Order Byte)
Operand Data (Low Order Byte)

0

Opcode
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data

,,,
,,
,,
,,
,
,,
,,

0
0

Opcode
Offset
Low Byte of Restart Vector
Operand Data IHigh Order Byte)
Operand Data ILow Order Byte)
Low Byte of Restart Vector
Opcode
Offset
Low Byte of Restart Vector
First Subroutine Opcode
Return Address (Low Order Byte)
Return Address IHigh Order Byte)

* TST does not perform the write cycle during the sixth cycle The sixth cycle is another address bus= $FFFF

3-85

I

MC6801·MC6803

TABLE 14 Address Mode and
Instructions

CYCLE-BY-CYCLE OPERATION (Sheet 4 of 5)

R/W
Line

Address Bus

Data Bus

INHERENT
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM

I

2

1
2

Opcode Address
Opcode Address + 1

1
1

Opcode
Opcode of Next Instruction

ABX

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Irrelevant Data
Low Byte of Restart Vector

ASLD
LSRD

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Irrelevant Data
Low Byte of Restart Vector

DES
INS

3

1
2
3

Opcode Address
Opcode Address + 1
Previous Stack Pointer Contents

1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data

INX
DEX

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1

Opcode
Opcode of Next Instruction
Low Byte of Restart Vector

1
2
3

Opcode Address
Opcode Address + 1
Stack Pointer

0

Opcode
Opcode of Next Instruction
Accumulator Data

1
2
3

Opcode Address
Opcode Address + 1
Stack Pointer

1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data

1

2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Opcode of Next Instruction
Low Byte of Restart Vector

PSHA
PSHB

DAA
DEC'
INC
LSR
NEG
Nap
ROL
ROR
SBA

SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST

3

TSX

3

TXS

3

1

1
1

PULA
PULB

4

1
2
3
4

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1

1
1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data
Operand Data from Stack

PSHX

4

1
2
3
4

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer-l

1
1

0
0

Opcode
Irrelevant Data
Index Register (Low Order Byte)
Index Register (High Order Byte)

PULX

5

1
2
3
4
5

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1
Stack Pointer+2

1
1
1
1
1

Opcode
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)

RTS

5

1
2
3
4
5

Opcode Address
Opcode Address + 1
S tack Poi nter
Stack Pointer + 1
Stack POlnter+2

1
1
1
1
1

Opcode
Irrelevant Data
Irrelevant Data
Address of Next Instruction (High Order Byte)
Address of Next Instruction (Low Order Byte)

WAI

9

1
2
3
4
5
6
7

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer-l
Stack Pointer-2
Stack Pointel - 3
S tack Pointer - 4
Stack Pointer-5
S tack Pointer - 6

1
1

Opcode
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condition Code Register

8
9

0
0
0
0
0
0
0

3-86

MC6801·MC6803

TABLE 14 Address Mode and
Instructions

CYCLE-BY-CYCLE OPERATION (Sheet 5 of 5)
R/W
Line

Address Bus

Data Bus

INHERENT
10

MUL

1
2
3
4
5

6
7

8
9
10

10

RTI

1
2
3
4
5

6
7

8
9
10

SWI

12

1
2
3
4
5
6
7

8
9
10
11
12

Opcode Address
Opcode Address+ 1
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart

Opcode Address
Opcode Address+ 1
Stack Pointer
Stack Pointer+ 1
Stack Pointer+2
Stack Pointer+ 3
Stack Pointer+4
Stack Pointer+5
Stack Pointer+6
Stack Pointer+ 7

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Irrelevant Data
Contents of Condition Code Register from Stack
Contents of Accumulator B from Stack
Contents of Accumulator A from Stack
Index Register from Stack (High Order Byte)
Index Register from Stack (Low Order Byte)
Next Instruction Address from Stack (High Order Byte)
Next Instruction Address from Stack (Low Order Byte)

Opcode Address
Opcode Address+ 1
Stack Pointer
Stack Pointer-1
Stack Pointer - 2
Stack Pointer- 3
Stack Pointer-4
Stack Pointer - 5
Stack Pointer-6
Stack Pointer- 7
Vector Address FFFA (Hex)
Vector Address FFFB (Hex)

1
1
0
0
0
0
0
0
1
1
1

Opcode
I rrelevant Data
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condition Code Register
Irrelevant Data
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)

0

Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector

RELATIVE
BCC
BCS
BEQ
BGE
BGT
BSR

BHT BNE BLO
BLE BPL BHS
BLS BRA BRN
BLT BVC
BMI BVS

3

1
2
3

Opcode Address
Opcode Address + 1
Address Buss FFFF

1
1
1

Opcode
Branch Offset
Low Byte of Restart Vector

6

1
2
3
4
5
6

Opcode Address
Opcode Address + 1
Address Bus FFFF
Subroutine Starting Address
S tack Pointer
Stack Pointer-1

1
1
1
1
0
0

Opcode
Branch Offset
Low Byte of Restart Vector
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

3-87

I

•

3:
oen
CO

o

FIGURE 25 - SPECIAL OPERATIONS

~

JSR, Jump to Subroutine
~

Direct

{

$9D=JSR

I

Next Main Instr.

RTN

Main Program
~

{

~

S"~

WAI, Wait for Interrupt

o-'::=:~

$AD=JSR
K=Offset

SP

Next Main Instr.

RTN

RTNL

RTI Return from Interrupt

(..)

eX>
ex>

'

Main Program

!

~

EXTND

$BD=JSR

AcmltrA

SP-3

Index Register (XH)

SP-2

Index Register (XL)

10

SP-l

RTNH

SP

RTNL

10

SP

-

~

-

Stack

Condition Code

SP+ 1

AcmltrB

Next Main Ins!.

SP+4

Index Register (XH)

SP+5

Index Register (XL)

SP+6

RTNH

SP+7

RTNL

~

¢~

Next Main Instr

Subroutine
[

W

SP-4

AcmltrA

± K=Offset

RTS, Return from Subroutine

CO

AcmltrB

SP+3

$8D=BSR

RTN I

Condition Code

SL=Subr.Addr.

Main Program
~

SP-6
SP-5

SP+2

BSR, Branch To Subroutine

~

~

SH = Subr. Addr.

RTN

Stack

SP-7

K = Direct Address

INDXD

SP

SWI, Software Interrupt
Main Program

i:
oen

$39=RTS

I

SP-l

RTNH

SP

RTNL

Stack

SP~

~

~

SP-2~

~

¢

Stack

SP+ 1

RTNH

SP+2

RTNL

Legend:
RTN = Address of next instruction in Main Program to be executed upon return from subroutine
RTNH = Most significant byte of Return Address
RTNL = Least significant byte of Return Address
- = Stack Pointer After Execution
K = 8-bit Unsigned Value

Ef

JMP, Jump

!

Main Program

PC

INDXD

X+K

~extln~

E~"~

$7E=JMP
KH = Next Address
KL = Next Address

{
K

I

Next Instruction

o

MC6801·MC6803

APPENDIX
CUSTOM MC6801 ORDERING INFORMATION
A.O CUSTOM MC6801 ORDERING INFORMATION
The custom MC6801 specifications may be transmitted to
Motorola in any of the following media:
1) PROM(s)
2) MDOS diskette
The specification should be formatted and packed, as indicated in the appropriate paragraph below, and mailed
prepaid and insured with a cover letter (see Figure A-2) to:

data), may be submitted for pattern generation. The
MC2708s must be clearly marked to indicate which PROM
corresponds to which address space ($F800-$FFFF). See
Figure A-1 for recommended marking procedure.
After the PROM(s) are marked, they should be placed in
conductive IC carriers and securely packed. Do not use
styrofoam.
FIGURE A-l

~

Motorola Inc.
M PU Marketing L 10
3501 Ed Bluestein Blvd.
Austin, Texas 78721

6d

~

6d

xxx = Customer ID

A copy of the cover letter should also be mailed separately.

A.1 PROMs
MCM2708 and MCM2716 type PROMs, programmed with
the custom program (positive logic sense for address and

A.2 DISKETTE (MOOS)
The start/end location should be written on the labe\.
EXORciser format.

FIGURE A-2
CUSTOMERNAME ___________________________________________________________________________
ADDRESS ________________________________________________________________________________
CITY _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ STATE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ZIP _ _ _ _ _ _ _ __
PHONE (_ _ )_____________________________________________________ EXTENSION _ _ _ _ _ _ __
CONTACT MS/MR ___________________________________________________________________________
CUSTOMERPART# _________________________________________________________________________
TEMPERATURE RANGE
00° to 70°C
o -40 to 85°C
o -40 to 105°C

PACKAGE TYPE
o Ceramic
o Plastic

MARKING
o Standard
PATTERN MEDIA
o Special
02708 PROM
02716 PROM
o Diskette (MDOS)
(Note 1) _____________________________________________________________________________
NOTE: (1) Other Media Require Prior Factory Approval
SIGNATURE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
TITLE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

3-89

I

MC6801·MC6803

, . . . . - - - MC6801 L1 -

LlLBug TM Monitor - - -......

An MC6801 may be purchased without specifying the ROM
pattern. This standard part is labeled as MC6801 L1 and
contains a 2K monitor in the ROM. The monitor, LlLbug,
may be used to evaluate and debug a program under
development. Details and a source listing are specified in
the" LI Lbug Manual."

II

IMPORTANT NOTICE
Devices made with mask #T5P may generate multiple framing error
flags in response to unframed data. These devices will eventually synchronize correctly after a framing error, but valid, framed data following
an unframed data byte may generate false framing error flags.

®

MC6801U4
MC6803U4

MOTOROLA

Advance Information
HMOS
(HIGH-DENSITY N-CHANNEL, SILICON-GATEI

MICROCOMPUTER/MICROPROCESSOR (MCU/MPU)
The MC6801U4 is an 8-bit single-chip microcomputer unit (MCU)
which enhances the capabilities of the MC6801 and significantly
enhances the capabilities of the M6800 Family of parts. It includes an
MC6801 microprocessor unit (MPU) with direct object-code compatibility and upward object-code compatibility with the MC6800. Execution times of key instructions have been improved over the MC6800
and the new instructions found on the MC6801 are included. The MCU
can function as a monolithic microcomputer or can be expanded to a
64K byte address space. It is TTL compatible and requires one + 5-volt
power supply. On-chip resources include 4096 bytes of ROM, 192 bytes
of RAM, a serial communications interface (SCIl, parallel I/O, and a
16-bit six-function programmable timer. The MC6803U4 can be considered an MC6801 U4 operating in modes 2 or 3; i.e., those that do not
use internal ROM.

MICROCOMPUTER/
MICROPROCESSOR

.MMii'l

~iW\l
'"

4

>

>

4>

R2 : > R1 4 R1 4> R14>
> 4> ~ > ~>

MC6801U4
MC6803U4

6

RESET '"

8

P20

9

P2 1

10

P22

NOTES:
1. Mode 7 as shown
2. R2.C= Reset time constant
3. R1 = 10 k (typical)
4. D= 1N914, 1N4001 (typical)
5. Diode Vf should not exceed V MPDD min.

D

P20 (PCo)
P21 (PC1l
P22 (PC2)

I

Mode
Control
Switches

;>

D'

RESET

D'"

_I.-

FIGURE 16 -

MC6801U4/MC6803U4 MEMORY MAPS (Sheet 1 of 4)

Multiplexed Test Mode
$0000(1)
Internal Registers
$OOlF

MC6801U4
Mode

External Memory Space

o

Internal RAM

External Memory Space

$BFFO
$BFFF
$FOOO

~~~~t>
J::

External Interrupt Vectors(2)
External Memory Space

Internal ROM

NOTES:
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07, and
$OF.
2) The interrupt vectors are at $BFFO-$BFFF.
3) There must be no overlapping of internal and
external memory spaces to avoid driving the
data bus with more than one device.

3-103

4) This mode is the only mode which may be
used to examine the entire ROM using an external RESET vector.
5) Modes 5-7 can be irreversibly entered from
mode 0 by writing to the PCO-PC2 bits of the
port 2 data register.

Me6801 U4, MC6803U4

FIGURE 16 -

MC6801U4/MC6803U4 MEMORY MAPS (Sheet 2 of 4)

MC6801U4
Mode

MC6801U4
MC6803U4
Mode

1
Multiplexed/RAM

Multiplexed/RAM & ROM

I

2

Internal Registers

I nternal Aeglsters

External Memory Space

External Memory Space

Internal RAM

Internal RAM

External Memory Space
External Memory Space

Internal ROM
SFFEF ~~~~
SFFFO
SFFFF

External Interrupt Vectors

NOTES:
1) Excludes the following addresses which may
be used externally: $05 and $07.
2) Internal AOM addresses $FFFO to $FFFF are
not usable.
3) Address lines AB-A 15 will not contain addresses until the data direction register for
port 4 has been written with "1s" in the appropriate bits. These address lines will assert
"1s" until made outputs by writing the data
direction register.

3-104

External Interrupt Vectors

NOTE:
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07, and
$OF.

MC6801U4, MC6803U4

FIGURE 16 -

MC6801U4/MC6803U4 MEMORY MAPS (Sheet 3 of 4)

MC6801U4
MC68D3U4
Mode

3

MC6801U4
Mode

Multiplexed/ RAM

5

Non-Multiplexed/ Partial Decode
$0000(1)

$0000(1 ) r - - - - - , . . .

~~ Internal Registers

S001 F""~'-4<.LLj'-L.<.~'-"

$OlFFT :~: '~:,

External Memory Space

;;;.
Internal Registers( 1, 2)

:::o Internal Registers
$001 F ""~.L.LL.
~

g

SCI = TIE·TOAE + AIE·IADAF + OAFEI
ICI = IICF1.EICIlI + IICF2.EICI21
OCI = IOCFloEOCll I + IOCF2o EOCI21 + IOCF3o EOCI31

Vecto,-PC

Mode 0

Modes 1-3, !>-7

NMI

BFFC-BFFD

FFFC-FFFD

SWI

BFFA-BFFB

FFFA-FFFB

Software Interrupt

101

BFFS-BFF9

FFFS-FFF9

Maskable Interrupt Request 1

ICF

BFF6-BFF7

FFF6-FFF7

Input Capture Interrupt

OCF

Non·Maskable Interrupt

BFF4-BFF5

FFF4-FFF5

Output Compare Interrupt

TOF

BFF2-BFF3

FFF2-FFF3

Timer Overflow Interrupt

SCI

BFFQ-SFFI

FFFO-FFFI

SCI Interrupt

s:

FIGURE 18 -

Last Instruction

~

n
en

INTERRUPT SEQUENCE

00
0
...a

Cycle
#1

#2

I

#4

#3

I

#5

#7

#6

#9

#8

I

#10

#11

C
~

#12

s:

n
en

Internal
Address Bus

IRQ1

NMI or IRQ2

00
0
W

c~

~ i+-tpcs l
\

~~tPcs

Internal
Data Bus _ _ _ _ _ _ ~_
Op Code Op Code

....'t>
0

PC 0-7

PC8-15

X

X07

8~

15

ACCA

\

Internal R/IN

Irrelevant
Data

CCR

ACCB

Vector
MSB

Vector
LSB

First Ins!. of
Interrupt Routine

/

CO

FIGURE 19 -

Vcc

&\\\.\~\\~ ~'\&~~W\~\

~475V
I~

525 V

RESET

InternaBI
Address us

Internal R/IN
Internal
Data Bus

II

RESET TIMING

~,'

tRC

r-----=::;J

~ ~4.0V

I.'I--_ _ _ _ _ _

I

f"'v'i~-r11l---JU
__
ttpes

tpcs

08

s\\\\\\\\\\\\\\\\'!
f\\\\S\\\\\\\\\\\\\\\\\\\\\\~
IL-~~_"-_.J\..._--J'.'--_~_.J'\..._ _ ,"_ _ _ .,"=,=~,::"::,:~
~ ~
~ FFFE

------

&\\'L\\\%\S\\\~ ts\\\\\\\\\\\\\S\\\S\\S\\\\V

'40 K

>30 K

>20 K

*NOTE These are representative AT-cut crystal parameters only Crystals of other
types of cut may also be used

MC6801U4

----------~ID~I---------L1

C1

RS

co

CL = 20 pF (tYPical)

Equivalent Circuit
NOTE
TTL-compatible oscillators may be
obtained from:
Motorola Component Products
Attn: Crystal Clock Oscillators
2553 N. Edgington St
Franklin Park, IL 60131
Tel: 312-451-1000
Telex: 433-0067

(b) Oscillator Stabilization Time (tRC)

~4-.7-5-V----------~J~'--------------------------------

VCC

I

1~.r------tRC------)~
Oscillator
Stabilization
Time, tRC

3-111

I

MC6801 U4, MC6803U4

PORT 3 CONTROL AND STATUS REGISTER

SC2 is configured as read/write and is used to control the
direction of data bus transfers. An MPU read is enabled
when read/write and E are high.
P10-P17 (PORT 1)
Port 1 is a mode independent 8-bit I/O and timer port.
Each line can be configured as either an input or output as
defined by the port 1 data direction register. Port 1 bits 0, 1,
and 2 (P10, P11, and P12) can also be used to exercise one
input edge function and two output compare functions of
the timer. The TTL compatible three-state buffers can drive
one Schottky TTL load and 30 pF, Darlington transistors, or
CMOS devices using external pullup resistors. It is configured as a data input port during RESET. Unused pins can
remain unconnected.

I

P20-P24 (PORT 2)
Port 2 is a mode-independent, 5-bit, multipurpose I/O
port. The voltage levels present on P20, P21, and P22 on the
rising edge of RESET determine the operating mode of the
MCU. The entire port is then configured as a data input port.
The port 2 lines can be selectively configured as data output
lines by setting the appropriate bits in the port 2 data direction register. The port 2· data register is used to move data
through the port. However, if P21 is configured as an output, it is tied to the timer output compare 1 function and cannot be used to provide output from the port 2 data register
unless output enable 1 (OEll is cleared in timer control
register 1.
Port 2 can also be used to provide an interface for the
serial communications interface and the timer input edge
function. These configurations are described in SERIAL
COMMUNICATIONS INTERFACE and PROGRAMMABLE
TIMER,
The port 2 three-state TTL-compatible output buffers are
capable of driving one Schottky TTL load and 30 pF, or
CMOS devices using external pullup resistors.
PORT 2 DATA REGISTER
7

IPC2

6
PCl

PCO

4

3

P24

P23

o
P22

P2l

P20

$03

P30-P37 (PORT 3)
Port 3 can be configured as an I/O port, a bidirectional
8-bit data bus, or a multiplexed address/data bus depending
on the operating mode. The TTL compatible three-state output buffers can drive one Schottky TTL load and 90 pF.
Unused lines can remain unconnected.
PORT 31N SINGLE-CHIP MODE - Port 3 is an 8-bit I/O
port in the single-chip mode with each line configured by the
port 3 data direction register. There are also two lines, IS3
and OS3, which can be used to control port 3 data transfers.
Three port 3 options are controlled by the port 3 control
and status register and are available only in single-chip
mode: 1) port 3 input data can be latched using IS3 as a control signal, 2) OS3 can be generated by either an MPU read
or write to the port 3 data register, and 3) an )RQ1 interrupt
can be enabled by an IS3 negative edge. Port 3 latch timing
is shown in Figure 4.

o

654
IS3
Flag

I

1iRO'i
IS3 1 X loss 1Latch
. Enable

X

X

X

$OF

Bits 0-2 Not used.
Bit 3

Latch Enable - This bit cC"~trols the input latch for
port 3. If set, input data is latched by an IS3
negative edge. The latch is transparent after a read
of the port 3 data register. Latch enable is cleared
during reset.

Bit 4

OSS (Output Strobe Select) - This bit determines
whether OS3 will be generated by a read or write of
the port 3 data register. When clear, the strobe is
generated by a read; when set, it is generated by a
write. OSS is cleared during reset.

Bit 5

Not used.

Bit 6

IS3 IRQ1 Enable - When set, an TR"Ql interrupt
will be enabled whenever the IS3 flag is set; when
clear, the interrupt is inhibited. This bit is cleared
during reset.

Bit 7

IS3 Flag - This read-only status bit is set by an IS3
negative edge. It is cleared by a read of the port 3
data register or during reset.

PORT 3 IN EXPANDED NON-MULTIPLEXED MODE
Port 3 is configured as a bidirectional data bus (07-00) in the
expanded non-multiplexed mode. The direction of data
transfers is controlled by read/write (SC2). Data is clocked
by E (enable).
PORT 31N EXPANDED MULTIPLEXED MODE - Port 3 is
configured as a time multiplexed address (A7-AOl and data
bus (07-DOl in the expanded multiplexed mode where address strobe (AS) can be used to demultiplex the two buses.
Port 3 is held in a high-impedance state between valid address and data to prevent bus conflicts.
P40-P47 (PORT 4)
Port 4 is configured as an 8-bit I/O port, as address outputs, or as data inputs depending on the operating mode.
Port 4 can drive one Schottky TTL load and 90 pF, and is the
only port with internal pull up resistors. Unused lines can remain unconnected.
PORT 4 IN SINGLE-CHIP MODE - In single-chip mode,
port 4 functions as an 8-bit I/O port with each line configured by the port 4 data direction register. Internal pullup
resistors allow the port to directly interface with CMOS at
5-volt levels. External pull up resistors to more than 5 volts,
however, cannot be used.
PORT 4 IN EXPANDED NON-MULTIPLEXED MODE
Port 4 is configured from reset as a,i 8-bit input port where
the port 4 data direction register can be written to provide
any or all of eight address lines AO to A7. Internal pull up
resistors pull the lines high until the port 4 data direction
register is configured.

3-112

MC6801U4, MC6803U4

PORT 41N EXPANDED MULTIPLEXED MODE - In all expanded multiplexed modes except modes 1 and 6, port 4
functions as half of the address bus and provides A8 to A 15.
In modes 1 and 6, the port is configured from reset as an
8-bit parallel input port where the port 4 data direction
register can be written to provide any or all of upper address
lines A8 to A 15. Internal pullup resistors pull the lines high
until the port 4 data direction register is configured where bit
o controls A8.

RESIDENT MEMORY
The MC6801 U4 provides 4096 bytes of on-chip ROM and
192 bytes of on-chip RAM.
Thirty-two bytes of the RAM are powered through the
V CC standby pin and are maintainable during V CC power
down. This standby portion of the RAM consists of 32 bytes
located from $40 through $5F in all modes except mode 3
which is $0040 through $005F.
Power must be supplied to VCC standby if the internal
RAM is to be used regardless of whether standby power
operation is anticipated.
The RAM is controlled by the RAM control register.
RAM CONTROL REGISTER ($14)
The RAM control register includes two bits which can be
used to control RAM accesses and determine the adequacy
of the standby power source during power-down operation.
It is intended that RAME be cleared and STBY PWR be set
as part of a power-down procedure.
RAM CONTROL REGISTER

6

OUTPUT COMPARE
($1C:1D)

REGISTERS

($OB:OCI.

($1A:1B),

The three output compare registers are 16-bit read/write
registers, each used to control an output waveform or provide an arbitrary time-out flag. They are compared with the
free-running counter during the negative half of each E cycle. When a match occurs, the corresponding output compare flag (OCF) is set and the corresponding output level
(OLVL) is clocked to an output level register. If both the corresponding output enable bit and data direction register bit
are set, the value represented in the output level register will
appear on the corresponding port pin. The appropriate OL VL
bit can then be changed for the next compare.
The function is inhibited for one cycle after a write to its
high byte ($OB, $1 A, or $1 C) to ensure a valid compare after
a double byte write. Writes can be made to either byte of the
output compare register without affecting the other byte.
The OLVL value will be clocked out independently of
whether the OCF had previously been cleared. The output
compare registers are set to $FFFF during reset.

o

4

x

which is incremented by E (enable). It is cleared during reset
and is read-only with one exception: in mode 0 a write to the
counter ($09) will configure it to $FFF8. This feature, intended for testing, can disturb serial operations because the
counter provides the SCI internal bit rate clock. The TOF is
set whenever the counter contains all ones. If ETOI is set, an
interrupt will occur when the TOF is set. The counter may
also be read as $15 and $16 to avoid inadvertently clearing
the TOF.

x

x

x

x

$14

Bits 0-5 Not used.
Bit 6

RAM Enable - This read/write bit can be used to
remove the entire RAM from the internal memory
map. RAME is set (enabled) during reset provided
standby power is available on the positive edge of
RESET. If RAME is clear, any access to a RAM address is external. If RAME is set, the RAM is included in the internal map.

Bit 7

Standby Power - This bit is a read/write status bit
which when cleared indicates that VCC standby
has decreased sufficiently below VSBB (minimum)
to make data in the standby RAM suspect. It can
be set only by software and is not affected during
reset.

INPUT CAPTURE REGISTERS ($OD:OE), ($1E:1F)
The two input capture registers are 16-bit read-only
registers used to store the free-running counter when a
"proper" input transition occurs as defined by the corresponding input edge bit (IEOG1 or IEOG2). The input pin's
data direction register Should be configured as an input, but
the edge detect circuit always senses P10 and P20 even
when configured as an output. The counter value will be
latched into the input capture registers on the second
negative edge of the E clock following the transition.
An input capture can occur independently of ICF; the
register always contains the most current value. Counter
transfer is inhibited, however, between accesses of a double
byte MPU read. The input pulse width must be at least two E
cycles to ensure an input capture under all conditions.

TIMER CONTROL AND STATUS REGISTERS

PROGRAMMABLE TIMER

Four registers are used to provide the MC6801 U4/
MC6803U4 with control and status information about the
three output compare functions, the timer overflow function, and the two input edge functions of the timer. They
are:
Timer Control and Status Register (TCSR)
Timer Control Register 1 (TCRll
Timer Control Register 2 (TCR2)
Timer Status Register (TSR)

The programmable timer can be used to perform
measurements on two separate input waveforms while independently generating three output waveforms. Pulse
widths can vary from several microseconds to many
seconds. A block diagram of the timer is shown in Figure 21.
COUNTER ($09:0Al, ($15, $16)
The key timer element is a 16-bit free-running counter

3-113

I

..
FIGURE 21 -

3:
(")

BLOCK DIAGRAM OF PROGRAMMABLE TIMER

i"RTI2

MC6801U4/MC6803U4 Internal Bus
~

~r

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0$lC:1D
Output Compare
Register 3

I

I

V$lA:1B
Output Compare
Register 2

V$OB:OC
Output Compare
Register 1

I

II

Free-Running
16-Bil Counter

II

II
I

V
Output Compares
!Three)

~

II

Overflow
Detect

I

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L2

Cla,)

....L

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Edge Detects
ITwo)

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I /~

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IICFl I OCF11 TOF I EIClllEOIClll ETOlllEDGl OLVL11

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I ICF2 I ICF1 I OCF31 OCF2 I OCF1 I TOF I

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I OE3 I OE2 I OEl IIEDG211EDGl

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1

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I EICI2 I EICl11 EOCI3I EOC\21 EOCll

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~

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r'--->

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Output Level
P21

I

I

Output Level
Register 2

~p.

i 0."" ~."
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P11

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'----

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Pl0

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Output Level I
Register 1
I

ETOI I TEST ICLOCKI

Input Edge
P20
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----. D

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3:
n
en
CO

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r-------. D

TCR21$18)

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o

o

f

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Port Control
Circuitry

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TCRl 1$17)

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Input Capture
Register 2

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TCSR 1$08)

$OD:OE
Input Capture
Register 1

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Output Level
Register 3

I

I

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MC6801 U4, MC6803U4

TIMER CONTROL AND STATUS REGISTER (TCSR)
($08) - The timer control and status register is an 8-bit
register of which all bits are readable, while only bits 0-4 can
be written. All the bits in this register are also accessible
through the two timer control registers and the timer status
register. The three most significant bits provide the timer
status and indicate if:
1. a proper level transition has been detected at P20,
2. a match has occurred between the free-running
counter and output compare register 1, or
3. the free-running counter has overflowed.

Bit 7

TIMER CONTROL REGISTER 1 (TCR1) ($17) - Timer
control register 1 is an 8-bit readlwrite register which contains the control bits for interfacing the output compare and
input capture registers to the corresponding 1/0 pins.

Each of the three events can generate an I R02 interrupt
and is controlled by an individual enable bit in the TCSR.

TIMER CONTROL REGISTER 1

7

TIMER CONTROL AND STATUS REGISTER

76543210

Output Levell - OLVL 1 is clocked to output level
register 1 by a successful output compare and will
appear at P21 if bit 1 of the port 2 data direction
register is set and the OE1 control bit in timer control register 1 is set. OLVL 1 and output level
register 1 are cleared during reset. Refer to TIMER
CONTROL REGISTER 1 (TCR1) ($171.

Bit 1

Input Edge 1 - IEDG1 is cleared during reset and
controls which level transition on P20 will trigger a
counter transfer to input capture register 1:
IEDG 1 = a transfer on a negative-edge
IEDG1 = 1 transfer on a positive-edge
Refer to TIMER CONTROL REGISTER 1 (TCR1)

Output Levell - OLVL 1 is clocked to output level
register 1 by a successful output compare and will
appear at P21 if bit 1 of the port 2 data direction
register is set and the OE1 control bit is set. OLVL 1
and output level register 1 are cleared during reset.
Refer to TIMER CONTROL AND STATUS
REGISTER (TCSR) ($081.

Bit 1

Output Level 2 - OLVL2 is clocked to output level
register 2 by a successful output compare and will
appear at P11 if bit 1 of port 1 data direction register
is set and the OE2 control bit is set. OL VL2 and output level register 2 are cleared during reset.

Bit 2

Output Level 3 - OLVL3 is clocked to output level
register 3 by a successful output compare and will
appear at P12 if bit 2 of port 1 data direction register
is set and the OE3 control bit is set. OL VL3 and output level register 3 are cleared during reset.

Bit 3

Input Edge 1 - IEDG1 is cleared during reset and
controls which level transition on P20 will trigger a
counter transfer to input capture register 1.
I EDG 1 = a transfer on a negative-edge
IEDG1 = 1 transfer on a positive-edge
Refer to TIMER CONTROL AND STATUS
REGISTER (TCSR) ($08).

Bit 4

Input Edge 2 - IEDG2 is cleared during reset and
controls which level transition on P10 will trigger a
counter transfer to input capture register 2.
IEDG2= transfer on a negative-edge
IEDG2= 1 transfer on a positive-edge

($17).

Bit 2

Enable Timer Overflow Interrupt - When set, an
IR02 interrupt will be generated when the timer
overflow flag is set; when clear, the interrupt is inhibited. ETOI is cleared during reset. Refer to
TIMER CONTROL REGISTER 2 (TCR2) ($18).

Bit 3

Enable Output Compare Interrupt 1 - When set,
an IR02 interrupt will be generated when output
compare flag 1 is set; when clear, the interrupt is inhibited. EOCI1 is cleared during reset. Refer to
TIMER CONTROL REGISTER 2 (TCR2) ($181.

Bit 4

Enable Input Capture Interrupt 1 - When set, an
IR02 interrupt will be generated when input capture flag 1 is set; when clear, the interrupt is inhibited. EICI1 is cleared during reset. Refer to
TIMER CONTROL REGISTER 2 (TCR2) ($18).

Bit 5

Timer Overflow Flag - The TOF is set when the
counter contains all ones ($FFFFI. It is cleared by
reading the TCSR or the TSR (with TOF set) and
the counter high byte ($09), or during reset. Refer
to TIMER STATUS REGISTER (TSR) ($19).

Bit 6

Output Compare Flag 1 - OCF1 is set when output
compare register 1 matches the free-running
counter. OCF1 is cleared by reading the TCSR or
the TSR (with OCF1 set) and then writing to output
compare register 1 ($OB or SOC), or during reset.
Refer to TIMER STATUS REGISTER (TSR) ($191.

$17

a

Bit

a

543210

!OE3 ! OE2 ! OEl !IEDG2!IEDG1!OLVL310LVL2IoLVL1!

IICFl I OCFl I TOF I EICll I EOCll I ETOIIIEDG110LVLli $00

Bit

Input Capture Flag - ICF1 is set to indicate that a
proper level transition has occurred; it is cleared by
reading the TCSR or the TSR (with ICF1 set) and
the input capture register 1 high byte ($OD), or during reset. Refer to TIMER STATUS REGISTER
(TSR) ($19).

a

Bit 5

Output Enable 1 - OE1 is set during reset and
enables the contents of output level register 1 to be
connected to P21 when bit 1 of port 2 data direction register is set.
OE1 = a port 2 bit 1 data register output
OE1 = 1 output level register 1

Bit 6

Output Enable 2 - OE2 is cleared during reset and
enables the contents of output level register 2 to be
connected to P11 when bit 1 of port 1 data direction register is set.
oE2 = a port 1 bit 1 data register output
OE2= 1 output level register 2

3-115

I

MC6801 U4, MC6803U4

Bit 7

Output Enable 3 - OE3 is cleared during reset and
enables the contents of output level register 3 to be
connected to P12 when bit 2 of port 1 data direction register is set
OE3= 0 port 1 bit 2 data register output
OE3= 1 output level register 3

TIMER CONTROL REGISTER 2 (TCR2) ($18) - Timer
control register 2 is an 8-bit read/write register (except bits 0
and 1) which enable the interrupts associated with the freerunning counter, the output compare registers, and the input
capture registers. In test mode 0, two more bits (clock and
test) are available for checking the timer.

Bit 0

CLOCK - The CLOCK control bit selects which
half of the 16-bit free-running counter (MSB or
LSB) should be clocked with E. The CLOCK bit is a
read/write bit only in mode 0 and is set during
reset.
CLOCK = 0 - Only the eight most significant bits
of the free-running counter run with TEST = O.
CLOCK = 1 - Only the eight least significant bits
of the free-running counter run when
TEST=O.

Bit 1

TEST - the TEST control bit enables the timer test
mode. TEST is a read/write bit in mode 0 and is set
during reset.
TEST = 0 - Timer test mode enabled:
a) The timer LSB latch is transparent which
allows the LS B to be read independently
of the MSB.
b) Either the MSB or the LSB of the timer is
clocked by E, as defined by the CLOCK
bit.
TEST= 1 - Timer test mode disabled.

TIMER CONTROL REGISTER 2
(Non-Test Modes)

I

7

6

5

4

3

2

$.18

IEICI2 I EICI1 I EOCI31 EOCI21 EOCI1 I ETOI

Bits 0-1 Read-Only Bits - When read, these bits return a
value of 1. Refer to TIMER CONTROL REGISTER 2
(Test Mode).
Bit 2

Enable Timer Overflow Interrupt - When set, an
IR02 interrupt will be generated when the timer
overflow flag is set; when clear, the interrupt is inhibited. ETOI is cleared during reset. Refer to
TIMER CONTROL AND STATUS REGISTER
(TCSR) ($08).

Bit 3

Enable Output Compare Interrupt 1 - When set,
an IR02 interrupt will be generated when the output compare flag 1 is set; when clear, the interrupt
is inhibited. EOCll is cleared during reset. Refer to
TIMER CONTROL AND STATUS REGISTER
(TCSR) ($08).

Bit 4

Enable Output Compare Interrupt 2 - When set,
an I R02 interrupt will be generated when the output compare flag 2 is set; when clear, the interrupt
is inhibited. EOCI2 is cleared during reset.

Bit 5

Enable Output Compare Interrupt 3 - When set,
an IR02 interrupt will be generated when the output compare flag 3 is set; when clear, the interrupt
is inhibited. EOCI3 is cleared during reset.
Enable Input Capture Interrupt 1 - When set, an
I R02 interrupt will be generated when the input
capture flag 1 is set; when clear, the interrupt is inhibited. EICll is cleared during reset. Refer to
TIMER CONTROL AND STATUS REGISTER
(TCSR) ($08).

Bit 6

Bit 7

Enable Input Capture Interrupt 2 - When set, an
IR02 interrupt will be generated when the input
capture flag 2 is set; when clear, the interrupt is inhibited. EICI2 is cleared during reset.

Bits 2-7 See TIMER CONTROL REGISTER 2 (Non-Test
Modes). (These bits function the same as in the
non-test modes.)
TIMER STATUS REGISTER (TSR) ($19) - The timer
status register is an 8-bit read-only register which contains
the flags associated with the free-running counter, the output compare registers, and the input capture registers.
TIMER STATUS REGISTER

754

I

6
EICll

I

5

4

3

EOCI31 EOCI21 EOCI1

I

2
ETOI

I

1

I

TOF

$19

Bit 2

Timer Overflow Flag - The TOF is set when the
counter contains all ones ($FFFF). It is cleared by
reading the TSR or the TCSR (with TOF set) and
then the counter high byte ($09), or during reset.
Refer to TIMER CONTROL AND STATUS
REGISTER (TCSR) ($08).

Bit 3

Output Compare Flag 1 - OCFl is set when output
compare register 1 matches the free-running
counter. OCFl is cleared by reading the TSR or the
TCSR (with OCFl set) and then writing to output
compare register 1 ($OB or SOC), or during reset.
Refer to TIMER CONTROL AND STATUS
REGISTER (TCSR) ($08).

Bit 4

Output Compare Flag 2 - OCF2 is set when output
compare register 2 matches the free-running
counter. OCF2 is cleared by reading the TSR (with
OCF2 set) and then writing to output compare
register 2 ($lA or $1 B), or during reset.

Bit 5

Output Compare Flag 3 - OCF3 is set when output
compare register 3 matches the free-running
counter. OCF3 is cleared by reading the TSR (with
OCF3 set) and then writing to output compare
register 3 ($lC or $10), or during reset.

Bit 6

Input Capture Flag 1 - ICFl is set to indicate that a
proper level transition has occurred; it is cleared by
reading the TSR or the TCSR (with ICFl set) and
the input capture register 1 high byte ($OD), or during reset. Refer to TIMER CONTROL AND
STATUS REGISTER (TCSR) ($08).

TIMER CONTROL REGISTER 2
(Test Mode)

7

I

Bits 0-1 Not used.

The timer test bits (test and clock) allow the free-running
counter to be tested as two separate 8-bit counters to speed
testing.

IEICI2

3

IICF2 I ICFl I OCF31 OCF21 OCF1

0

TEST CLOCK I $18

3-116

MC6801 U4, MC6803U4

Bit 7

the required idle string between consecutive messages and
prevent it within messages.

Input Capture Flag 2 - ICF2 is set to indicate that a
proper level transition has occurred; it is cleared by
reading the TSR (with ICF2 set) and the input capture register 2 high byte ($1E), or during reset.

PROGRAMMABLE OPTIONS
The following features of the SCI are programmable:

SERIAL COMMUNICATIONS INTERFACE

• Format: standard mark/space (NRZ) or bi-phase

A full-duplex asynchronous serial communications interface (SCI) is provided with two data formats and a variety of
rates. The SCI transmitter and receiver are functionally independent but use the same data format and bit rate. Serial
data formats include standard mark/space (NRZ) and biphase and both provide one start bit, eight data bits, and one
stop bit. "Baud" and "bit rate" are used synonymously in
the following description.

• Clock: external or internal bit rate clock
• Baud: one of eight per E clock frequency or external
clock ( x 8 desired baud)
• Wake-Up Feature: enabled or disabled
• Interrupt Requests: enabled individually for transmitter
and receiver
• Clock Output: internal bit rate clock enabled or disabled
to P22

WAKE-UP FEATURE
In a typical serial loop multiprocessor configuration, the
software protocol will usually identify the addressee(s) at the
beginning of the message. In order to permit uninterested
MPUs to ignore the remainder of the message, wake-up
feature is included whereby all further SCI receiver flag (and
interrupt) processing can be inhibited until its data line goes
idle. An SCI receiver is re-enabled by an idle string of ten
consecutive ones or during reset. Software must provide for

SERIAL COMMUNICATIONS REGISTERS
The serial communications interface includes four addressable registers as depicted in Figure 22. It is controlled
by the rate and mode control register and the
transmit/receive control and status register. Data is transmitted and received utilizing a write-only transmit register and a
read-only receive register. The shift registers are not accessible to softwarE}.

FIGURE 22 - SCI REGISTERS
Bit 7

I

ESE

I

Rate and Mode Control Register

Sit 0

I I I I I

I

CCl

CCO

SSl

SSO $10

Transmit/Receive Control and Status Register

RDRF IORFE

fDREI RIE I

RE

I TIE

TE I WU

1$11

Receive Data Register
$12
~--~--~--~--~--~--~--~--~

Port 2

(Not Addressable)
Receive Shift Register

10

Transmit Shift Register
12

$13
Transmit Data Register

3-117

MC6801 U4, MC6803U4

for P22 is forced to the complement of CCO and
cannot be altered until CC1 is cleared. If CC1 is
cleared after having been set, its DDR value is
unchanged. Table 7 defines the formats, clock
source, and use of P22.

RATE AND MODE CONTROL REGISTER (RMCR) ($10)
- The rate and mode control register controls the SCI bit
rate, format, clock source, and under certain conditions, the
configuration of P22. The register consists of five write-only
bits which are cleared during reset. The two least significant
bits in conjunction with bit 7 control the bit rate of the internal clock and the remaining two bits control the format and
clock source.

Bits 4-6

Not used.

Bit 7

EBE Enhanced Baud Enable - EBE selects the
standard MC6801 baud rates when clear and the
additional baud rates when set (Table 6). This
bit is cleared by reset and is a write-only control
bit.
EBE=O standard MC6801 baud rates
EBE= 1 additional baud rates

RATE AND MODE CONTROL REGISTER
643

x
Bit 1: Bit

II

a

X

I

X

I

CCl

2

I

1

CCO

I

0

SSl

I

SSO

I

$10

If both CC1 and CCO are set, an external TTL-compatible
clock must be connected to P22 at eight times (8 x) the
desired bit rate, but not greater than E, with a duty cycle of
50% (± 10%). If CC1 :CCO= 10, the internal bit rate clock is
provided at P22 regardless of the values for TE or RE.

SS1 :SSO Speed Select - These two bits select
the baud when using the internal clock. Eight
rates may be selected (in conjunction with bit 7)
which are a function of the MCU input frequency. Table 6 lists bit time and rates for three
selected MCU frequencies.

NOTE
The source of SCI internal bit rate clock is the timer
free-running counter. An MPU write to the counter in
mode a can disturb serial operations.

Bit 3:Bit 2 CC1:CCO Clock Control and Format Select These two bits control the format and select the
serial clock source. If CC1 is set. the DDR value

TABLE 6 -

EBE

SSl:SS0
E

SCI BIT TIMES AND RATES

2.4576 MHz

4.0 MHz

4.9152 MHz

614.4 kHz
Baud
Time

1.0 MHz
Baud
Time

1.2288 MHz
Time
Baud

4fo -

0

0

0

+16

38400.0

261's

62500.0

16.01's

768000

·13.0I'SI

0

0

1

+ 128

4800.0

208.3I's

7812.5

128.01's

9600.0

104.2I's

0

1

0

+ 1024

600.0

1.67 ms

976.6

1.024 ms

1200.0

833.31's

0

1

1

+4096

150.0

6.67 ms

244.1

4.096 ms

300.0

3.33 ms

1

0

0

+54

9600.0

104.2I's

15625.0

54l's

19200.0

52.01's

1

0

1

+256

2400.0

416.61's

3906.3

2561's

4800.0

208.31's

1

1

0

+512

1200.0

833.31's

1953.1

5121's

2400.0

416.61's

1

1

1

+2048

300.0

3.33 ms

488.3

2.05 ms

600.0

1.67 ms

76800.0

13.01's

125000.0

8.01's

153600.0

6.51's

External (P22) *

* USing maximum clock rate

TABLE 7 -

SCI FORMAT AND CLOCK SOURCE CONTROL

CC1:CCO

Format

Clock
Source

Port 2
Bit 2

00

Bi-Phase

Internal

Not Used

01

NRZ

Internal

Not Used

10

NRZ

Internal

Output

11

NRZ

External

Input

3-118

MC6S01 U4, MC6S03U4

TRANSMIT/RECEIVE CONTROL AND STATUS
REGISTER (TRCSR) ($11) - The transmit/receive control
and status register controls the transmitter, receiver, wakeup feature, and two individual interrupts, and monitors the
status of serial operations. All eight bits are readable while
bits 0 to 4 are also writable. The register is initialized to $20
by RESET.

Bit 6

Overrun Framing Error - If set, ORFE indicates
either an overrun or framing error. An overrun is a
new byte ready to transfer to the receiver data
register with RDRF still set. A receiver framing error
has occurred when the byte boundaries of the bit
stream are not synchronized to the bit counter. An
overrun can be distinguished from a framing error
by the state of RDRF: if RDRF is set, then an overrun has occurred; otherwise, a framing error has
been detected. Data is not transferred to the
receive data register in an overrun condition. Unframed data causing a framing error is transferred
to the receive data register. However, subsequent
data transfer is blocked until the framing error flag
is cleared. ORFE is cleared by reading the TRCSR
(with ORFE set) then the receive data register, or
during reset.

Bit 7

Receive Data Register Full - RORF is set when the
input serial shift register is transferred to the receive
data register, or during reset.

TRANSMIT/RECEIVE CONTROL AND STATUS REGISTER

7

6

5

IRORF I ORFE I TORE

432

1

0

I RIE I RE I TIE I TE I wu I $11

Bit 0

"Wake-Up" on Idle Line - When set, WU enables
the wake-up function; it is cleared by ten consecutive ones or during reset. WU will not be set if
the line is idle. Refer to WAKE-UP FEATURE.

Bit 1

Transmit Enable - When set, P24 DDR bit is set,
cannot be changed, and will remain set if TE is
subsequently cleared. When TE is changed from
clear to set, the transmitter is connected to P24 and
a preamble of nine consecutive ones is transmitted.
TE is cleared during reset.

Bit 2

Transmit Interrupt Enable - When set, an IR02 is
set; when clear, the interrupt is inhibited. TE is
cleared during reset.

Bit 3

Receive Enable - When set, the P23 DDR bit is
cleared, cannot be changed, and will remain clear if
RE is subsequently cleared. While RE is set, the SCI
receiver is enabled. RE is cleared during reset.

Bit 4

Receiver Interrupt Enable - When set, an IR02 interrupt is enabled when RDRF and/or ORFE is set;
when clear, the interrupt is inhibited. RIE is cleared
during reset.

Bit 5

Transmit Data Register Empty - TDRE is set when
the transmit data register is transferred to the output serial shift register or during reset. It is cleared
by reading the TRCSR (with TDRE set) and then
writing to the transmit data register. Additional
data will be transmitted only if TDRE has been
cleared.

SERIAL OPERATIONS
The SCI is initialized by writing control bytes first to the
rate and mode control register and then to the
transmit/receive control and status register. When TE is set,
the output of the transmit serial shift register is connected to
P24 and serial output is initiated by transmitting a 9-bit
preamble of ones.
At this point, one of two situations exists: 1) if the transmit
data register is empty (TDRE= 1), a continuous string of
ones will be sent indicating an idle line; or 2) if a byte has
been written to the transmit data register (TORE=O), it will
be transferred to the output serial shift register (synchronized with the bit rate clock), TORE will be set, and transmission will begin.
The start bit (0), eight data bits (beginning with bit 0), and
a stop bit (1) will be transmitted. If TD RE is still set when the
next byte transfer occurs, ones will be sent until more data is
provided. In bi-phase format, the output toggles at the start
of each bit and at half-bit time when a one is sent. Receive
operation is controlled by RE which configures P23 as an input and enables the receiver. SCI data formats are illustrated
in Figure 23.

FIGURE 23 -

SCI DATA FORMATS

Output
Clock

NRZ
Format

I

I,

Bi-Phase
I'ormat
Bit

Idle Start

0

Data 01001101 ($40)

3-119

Bit

4

6

7

Stop

I

MC6801U4, MC6803U4

INSTRUCTION SET

to increment like a 16-bit counter causing address lines used
in the expanded modes to increment until the device is reset.
These opcodes have no mnemonics.
The coding of the first (or only) byte corresponding to an
executable instruction is sufficient to identify the instruction
and the addressing mode. The hexadecimal equivalents of
the binary codes, which result from the translation of the 82
instructions in all valid modes of addressing, are shown in
Table 8. There are 220 valid machine codes, 34 unassigned
codes, and 2 codes reserved for test purposes.

The MC6801U4/MC6803U4 is directly source compatible
with the MC6801 and upward source and object code compatible with the MC6800. Execution times of key instructions
have been reduced and· several instructions have been
added, including a hardware multiply. A list of new operations added to the MC6800 instruction set is shown in
Table 1.
In addition, two special opcodes, 4E and 5E, are provided
for test purposes. These opcodes force the program counter

TABLE 8 - CPU INSTRUCTION MAP
OP

I

06
07
08

09
OA
OB
OC
00
OE
OF

10
11
12
13
14
15
16
17
18
19
1A
1B
1C

33

OP

MNEM

MODE

-

#

OP

MNEM

MODE

2
2
2

6
6

3
3

ROR
ASR
ASL
ROL
DEC

6
6

5
6
6

3
3
3
3
3

INC
TST
JMP
CLR
SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDAA

6
6
3
6
2
2
2
4
2
2
2

3
3
3
3
2
2
2
3
2
2
2

2
2
2
2
2
2
2
2
2
2

C8
C9
CA
CB
CC
CD
CE
CF

DO
D1
D2
03
D4
D5
06
D7
D8
09
DA
DB
DC
DD
DE
OF
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF

SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDAB
STAB
EORB
ADCB
DRAB
ADDB
LDD
STD
LDX
STX
SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDAB
STAB
EORB
ADCB
DRAB
ADDB
LDD
STD
LDX
STX
SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDAB
STAB
EORB
ADCB
DRAB
ADDB
LDD
STD
LDX
STX

DIR

COM
LSR

5
5
4
4
4
4
4
6
4
4
4
4
4
4
4
4
6
6
5
5
4
4
4
6
4
4
4
4
4
4
4
4
6
6
5
5
2
2
2
4
2
2

2
2
2
2

2
2
2
2
3

CPX
JSR
LDS
STS
SUBA
CMPA
SBCA
SUBD
ANDA
81TA
LDAA
STAA
EORA
ADCA
ORAA
ADDA
CPX
JSR
LDS
STS
SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDAA
STAA
EORA
ADCA
ORAA
ADDA
CPX
JSR
LOS
STS
SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDAB

DIR

6
6
3
6
6

9C
9D
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
CO
C1
C2
C3
C4
C5
C6

-

#

OP

MNEM

MODE

-

#

OP

MNEM

MODE

34
1

ASL
ROL
DEC

3
3
2
2
3
3
2
2
2
2
2
2
2
2

1
1
1
1
1
1
1
1
1
1
1
1
1
1

35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47

9
12
2

1
1
1
1
1
1
1
1
1
1
1
1
1

INDXD

2

3
3
3
3
5
5
3
10
4

68

INHER

DES
TXS
PSHA
PSHB
PULX
RTS
ABX
RTI
PSHX
MUL
WAI
SWI
NEGA

INHER

NOP

2
2

1
1

LSRD
ASLD
TAP
TPA
INX
DEX
CLV
SEV
CLC
SEC
Cli
SEI
SBA
CBA

48
TAB
TBA

2
2

1
1

DAA

INHER

2

1

ABA

INHER

2

1

49
4A
4B
4C
4D
4E
4F

50

10
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32

#

6
6
6

MODE

00
01
02
03
04
05

-

MNEM

BRA
BRN
BHI
BLS
BCC
BCS
BNE
BED
BVC
BVS
BPL
BMI
BGE
BLT
BGT
BLE
TSX
INS
PULA
PULB

REL

,

REL
INHER

t

3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4

2
2
2
2
2

2
2
2
2
2
2
2
2
2
2
2
1
1
1
1

51
52
53
54
55

56
57

56
59
5A
5B
5C
50
5E
5F

60
61
62
63

10

COMA
LSRA
RORA
ASRA
ASLA
ROLA
DECA

2
2
2
2
2

1
1
1
1
1

INCA
TSTA
T
CLRA
NEGB

2
2

1

2

1
1

COMB
LSRB

2
2

1
1

RORB
ASRB
ASLB
ROLB
DECB

2
2
2
2
2

1
1
1
1
1

2
2

1
1

2
6

1
2

6
6

2
2

INCB
TSTB
T
CLRB
NEG

64

COM
LSR

65
66
67

ROR
ASR

2

It'
INHER
INDXD

1

INDXD

6
6

2
2

69
6A
6B
6C
6D
6E
6F
70
71

INC
TST
JMP
CLR
NEG

1

INDXD
EXTND

72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
B1
82
83

84
85
B6
87

88
89
8A
8B
8C
8D
8E
8F

90
91
92
93
94
95
96
97
98
99
9A
9B

EORA
ADCA
DRAA
ADDA
CPX
BSR
LDS
SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDAA
STAA
EORA
ADCA
DRAA
ADDA

EXTND
IMMED

~

IMMED
REL
IMMED
DIR

2
2
2
2
4
6
3

2
2
2
2
3
2
3

3
3
3
5
3
3
3
3
3
3
3
3

2
2

NOTES:
1. Addressing Modes
INHER-Inherent INOXO-Indexed
IMMEO_lmmediate
REL-Relative
EXTNO-Extended OIR-Oirect
2. Unassigned opcodes are indicated by "e" and should not be executed.
3. Codes marked by "1" force the PC to function as a 16-bit counter.

3-120

~

DIR
INDXD

"

I.INDXD
EXTND

EXTND
IMMED

2
2
2

2

2

2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
3
2
2
2

2
2
2
2
3

2
2
2
2
3

C7
EORB
ADCB
DRAB
ADDB
LDD

DIR
INOXD

,
INDXD
EXTND

EXTND

3
3
3
5
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
6
4
4
4
4
4
4
4
4
5
5
5
5
4
4
4
6
4
4
4
4
4
4
4
4
5
5
5
5

* UNDEFINED OP CODE
LDX

IMMED

3

3

#
2
2
2
2

2
2
2
2
2
2
2

2
2
2
2
2
2
2
2
2
2
2
2

2
2

2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3

MC6801 U4, MC6803U4

instruction where the number of bytes matches the size of
the register. These are two or three byte instructions.

PROGRAMMING MODEL
A programming model for the Me6801U4/Me6803U4 is
shown in Figure 8. Accumulator A can be concatenated with
accumulator B and jointly referred to as accumulator D
where A is the most significant byte. Any operation which
modities the double accumulator will also modify accumulators A and/or B. Other registers are defined as
follows:

DIRECT ADDRESSING - The least significant byte of the
operand address is contained in the second byte of the instruction and the most significant byte is assumed to be $00.
Direct addressing allows the user to access $00 through $FF
using two byte instructions and execution time is reduced by
eliminating the additional memory access. In most applications, the 256-byte area is reserved for frequently referenced
data.

PROGRAM COUNTER - The program counter is a 16-bit
register which always points to the next instruction.

EXTENDED ADDRESSING - The second and third bytes
of the instruction contain the absolute address of the
operand. These are three byte instructions.

STACK POINTER - The stack pointer is a 16-bit register
which contains the address of the next available location in a
pushdown/pullup (LIFO) queue. The stack resides in
random-access memory at a location defined by the programmer.

INDEXED ADDRESSING - The unsigned offset contained in the second byte of the instruction is added with
carry to the index register and is used to reference memory
without changing the index register. These are two byte instructions.

INDEX REGISTER - The index register is a 16-bit register
which can be used to store data or provide an address for the
indexed mode of addressing.

INHERENT ADDRESSING - The operand(s) is a register
and no memory reference is required. These are Single byte
instructions.

ACCUMULATORS - The MPU contains two 8-bit accumulators, A and B, which are used to store operands and
results from the arithmetic logic unit (ALU)' They can also be
concatenated and referred to as the D (double) accumulator.

RELATIVE ADDRESSING - Relative addreSSing is used
only for branch instructions. If the branch condition is true,
the program counter is overwritten with the sum of a signed
single byte displacement in the second byte of the instruction and the current program counter. This provides a
branch range of - 126 to + 129 bytes from the first byte of
the instruction. These are two byte instructions.

CONDITION CODE REGISTER - The condition code
register indicates the results of an instruction and includes
the following five condition bits: negative (N), zero (Z),
overflow (V), carry/borrow from MSB (e), and half carry
from bit 3 (Hl. These bits are testable by the conditional
branch instructions. Bit 4 is the interrupt mask (I bit) and inhibits all maskable interrupts when set. The two unused bits,
B6 and B7, are read as ones.

SUMMARY OF CYCLE-BY-CYCLE OPERATION
Table 14 provides a detailed description of the information
present on the address bus, data bus, and the read/write
(R/W) line during each cycle of each instruction.
The information is useful in comparing actual with expected results during debug of both software and hardware
as the program is executed. The information is categorized in
groups according to addressing mode and number of cycles
per instruction. In general, instructions with the same addressing mode and number of cycles execute in the same
manner. Exceptions are indicated in the table.
Note that during MPU reads of internal locations, the
resultant value will not appear on the external data bus except in mode O. "High order" byte refers to the most significant byte of a 16-bit value.

ADDRESSING MODES

Six addreSSing modes can be used to reference memory.
A summary of addressing modes for all instructions is
presented in Tables 9, 10, 11, and 12 where execution times
are provided in E cycles. Instruction execution times are
summarized in Table 13. With an input frequency of 4 MHz,
one E cycle is equivalent to one microsecond. A cycle-bycycle description of bus activity for each instruction is provided in Table 14 and descriptions of selected instructions
are shown in Figure 24.
IMMEDIATE ADDRESSING - The operand or "immediate byte(s)" is contained in the following byte(s) of the

3-121

I

Me6801 U4, MC6803U4

TABLE 9 - INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS
Condition Codes
Immed
Pointer Operations

I

# Op -

MNEM Op -

Index

Direct

# Op 2 AC 6

Extnd

Inherent

# Op

# Op 2 BC 6

Booleanl
Arithmetic Operation

-

#

1 X-1-X

Compare Index Register

CPX

Decrement Index Register

DEX

09

3

Decrement Stack Pointer

DES

34

3

1 SP-1-SP

Increment Index Register

INX

08

3

1 X+1-X

Increment Stack Pointer

INS

31

3

1 1 SP+1-SP

Load Index Register

LDX

CE 3

3 DE 4

Load Stack Pointer

LDS

8E

3 9E

Store Index Register
Store Stack Pointer
Index Reg -

TXS

Stack Pointer

8C 4

3 9C

5

4

2 EE 5
2 AE 5

STX

DF 4

STS

9F

3

4

3

X-M:M+1

3

M-XH,IM+11-XI

3

M-SPH,IM+li-SPL

2 EF 5

3

XH-M,XL -IM+li

2 AF 5

2 BF 5

3

SPH-M,SPL -IM+li
3
3

3

2

I

N

Z

1 0
V C

·· ·· ·I II ·I ·I
·· ·· · · ·· ··
··· ··· III ·III · ···
· ·· I 1 ··
··· ··· ·· ··· ··· ··
······
······
R

1 SP+1-X

Stack Pntr-Index Register

TSX

30

ABX

3A 3

1 B+X-X

Push Data

PSHX

3C 4

1 XL -MSp,SP-1-SP
XH - MSp,SP-1 - SP

Pull Data

PULX

38

5

1 SP+ l-SP,MSP-XH
SP+ l-SP,MSP-XL

R
R

1 X-1-SP

Add

TABLE 10 -

4

H

J

2 FE 5
2 BE 5
2 FF 5

35

5

R

ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 1 of 2)
Condition Codes

Accumulator and
Memory Operations

Immed

-

Index

Direct

Extend

Inher

Add Accumulators

ABA

# Op 1B 2

Add B to X

ABX

3A 3

MNEM Op

# Op -

# Op -

# Op -

ADCB C9

2
2

2 99 3
2 D9 3

2 A9 4
2 E9 4

2

Add

ADDA 8B

2

2 9B 3

2 AB 4

ADDB CB 2

2 DB 3

Add Double

ADDD C3 4

3 D3 5

And

ANDA 84

2

ANDB C4 2

Add with Carry

Shift Left, Arithmetic

Shift Left Double
Shift Right, Arithmetic

Bit Test

ADCA 89

4

3

B+M+C-B

2 BB 4

3

A+M-A

2 EB 4

2 FB 4

3

B+M-A

2 E3 6

2 F3 6

3

D+ M:M+ 1-D

2 94 3

2 A4 4

2 B4 4

3

A·M-A

2 D4 3

2 E4 4

2 F4 4

3

B·M-B

68

2 78 6

3

A+M+C-A

48

2

1

ASLB

58

2

1

05

3

1

ASLD
67

ASR

6

2 77 6

3

ASRA

47

2

1

ASRB

57

2

1

2

85

BITB

C5 2

2 95 3
2 D5 3

b7

b7

2 B5 4

3

A.M

F5

4

3

B·M

6F

2 7F 6

3

2

2

1 A-B

CLRA

4F

2

1 OO-A

CLRB

5F

2

1 OO-B

CLR

CMPA 81

2

2 91

3

2 A1

CMPB C1

2

2 D1

3

COM

6

OO-M

A-M

4

2 B1

2 E1

4

2 F1

4

3

B- M

63

6

2

73

6

3

M-M

4

3

COMA

43

2

1 A-A

COMB

53

2

1 B-B

3-122

3

2

1

I

N

Z

V C

0

· ··· · · ·
···
1
·· ··
·· ··
··· ··
·· ·· I I I I
·· ·· 1I 1I I I
l l
··· ·· I 1 1 ·1
·· ··
·· ·· I l t t
11 t
·· · lt ll
I 1 I I

R

-

-0

bO

q" iT IIII-@]

2 A5 4
2 E5 4

4

H

R

@l-111111111

11

CBA

Clear

1's Complement

3

F9

6

5

I

1 A+B-A
1 OO:B+X-X

2 B9 4

ASL

Compare Accumulators

Compare

#

ASLA

BITA

Boolean
Expression

bO

R

R

R

S

R

R

R

S

R

R

R

S

R

R

1 1 J J
R

S

R

S

R

S

MC6S01 U4, MC6S03U4

TABLE 10 -

ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 2 of 2)
Condition Codes

Accumulator and
Memory Operations

Immed

MNEM Op

Decimal Adjust, A

DAA

Decrement

DEC

Exclusive OR

Increment

-

Direct

# Op -

Index

# Op 6A

6

Extend

Inher

# Op -

# Op -

#

19

1

2 7A

3

6

4A

2

1

DECB

5A

2

1

2

98

3

2

A8 4

2

B8

4

3

AEI1M-A

EORB C8

2

2

08

3

2

E8

4

2

F8

4

3

BEI1M-B

6C

6

2

7C

6

3

INC

4

2

B6

4

3

M-A

LDAB C6

2

2

06

3

2

E6

4

2

F6

4

3

M-B

3 DC 4

2

EC

5

2

FC

5

3

M:M+1-D

68

6

2

78

6

3

CC 3

LSLA

48

2

1

LSLB

58

2

1

LSLD

05

3

2

LSR

64

6

2

74

6

2

1

2

1

LSRD

04

3

1

MUL

3D 10

i

40

1 oo-A-A

70

6

50

2

1 00- B - B

2

1

Subtract with Carry

Store Accumulators

2 AA 4

2 BA 4

3

A+M-A

2 DA 3

2 EA 4

2 FA 4

3

B+M-B

PSHA

36

Subtract Double
Transfer Accumulator

1

A - Stack

37

3

1

B-

PULA

32

4

1

Stack-A

33

4

1

Stack-B

49

2

1

59

2

1

ROL

69

6

2

79

6

ROR

66

6

2

76

6

~-jIIIIIIII-{9
b7

@J--IIIIIIIII-@]

46

2

1

RORB

56

2

1

b7

SBA

10

2

1

A--B-A

SBCA 82

2

2

92

3

2 A2

4

2

B2

4

3

SBCB C2

2

2

02

3

2

E2

4

2

F2

4

3

B-M-C-B

STAA

97

3

2 A7

4

2

B7

4

3

A-M

STAB

07

3

2

E7

4

2 F7

4

3

B-M

DO 4

2 ED

5

2

FD

5

3

D-M.M+1

90

A-M-C-A

SUBA 80

2

2

3

2 AO 4

2 BO 4

3

A-M-A

SUBB CO

2

2 DO 3

2 EO 4

2

4

3

B-M-B

SUBD 83

4

3

2 A3 6

2 B3 6

3

93

5

D-MM+1-D
16

2

1

A-B

17

2

1

B-A

TSTA

40

2

1

A-oo

TSTB

50

2

1

B - 00

TST

60

6

2 70 6

The condition code register notes are listed after Table 12

3-123

bO

3

TAB

M-oo

3

R

R

Stack

RORA

FO

R

R

3

TBA
Test, Zero or Minus

3

PSHB

STD
Subtract

PC+ 1-PC

3

ROLB

Subtract Accumulator

2

01
2 9A

··· · tt tt tt ·
t t t
··· ··· tt tt ·
·· ·· tt tt tt ··
· · tt tt t ·
·· ··· tt tt ·
· ·· tt tt lt lt
· ·· tt tt tt tt
· ·· tt tt tt
· ·· tt tt tt
· · ·t ·t ·t tl
· · tt tt tt tl
· · ·f ·f · ·
·· t t ·
· ·· ·· · · ·
···· ·
R

AxB-D

NOP
2

bO

oo-M-M

3

ROLA

Rotate Right

b7

NEGB

ORAA 8A

-0

o-IIIIIIIII-~

44

2

C

R

54

6

0

V

R

~-111111111
b7
bO

LSRB

60

1

Z

R

LSRA

NEG

2

N

R

3

PULB
Rotate Left

B+1-B

A6

ORAB CA 2

Pull Data

1

2

NEGA

Push Data

2

3

LSL

Inclusive OR

5C
96

3

I

R

A+1-A

2

LDD

No Operation

1

2

Load Double

2' s Complement (Negate)

2

4

H

R

M+1-M
4C

LDAA 86

Logical Shift, Left

Multiply

B-1-B

2

INCB

Shift Right, Logical

A-1-A

EORA 88

5

t t t t

AdJ binary sum to BCD
M-1-M

DECA

INCA

Load Accumulators

2

Boolean
Expression

bO

· · tt tl ·tl tt
l t t l
·· · tt tt tt tt
·l t t t
t t t t
· · tt tt tt ll
·· tt tt
·· ·· tl tt t ·t
t t t l
R
R

R

·
·

·

t l t t
t l R
t l R

l l
l t
l l

R

R

R

R

R

R

I

MC6801 U4, MC6803U4

TABLE 11 - JUMP AND BRANCH INSTRUCTIONS
Condition Code Reg.
Operations
Branch Always

I

Direct
Relative
Index
Inherent
Extend
# Op MNEM Op # Op # Op
# Op
#
BRA

20

3

5

-

-

Branch Test

2

None

B ranch Never

BRN

21

3

2

None

Branch If Carry Clear

BCC

24

3

2

C=O

Branch If Carry Set

BCS

25

3

2

C=1

Branch If= Zero

BEQ

27

3

2

Z=1

Branch If

~Zero

BGE

2C

3

2

NED V=O

Branch If

> Zero

BGT

2E

3

2

Z+(N ED V)=O
C+Z=O

Branch If Higher

BHI

22

3

2

Branch If Higher or Same

BHS

24

3

2

C=O

Branch If ""Zero

BLE

2F

3

2

Z+(NEDV)=l

Branch If Carry Set

BLO

25

3

2

C=1

Branch If Lower Or Same

BLS

23

3

2

C+Z=1

< Zero

BLT

20 3

2

NED V= 1

Branch If Minus

BMI

2B

3

2

N=1

Branch If Not Equal Zero

BNE

26

3

2

Z=O

Branch If Overflow Clear

BVC

28

3

2

V=O

Branch If Overflow Set

BVS

29

3

2

V=1
N=O

Branch If

Branch If Plus

BPL

2A 3

2

Branch To Subroutine

BSR

80 6

2

Jump

JMP

Jump To Subroutine

JSR

6E
90 5

2

3

AD 6

2 7E

3

3

2 BO 6

3

H

4
I

1

3

2

N

Z V

0
C

· ·· ·· ·· ·· ··
··· ··· ··· ··· ··· ···
··· ··· ··· ··· ··· ···
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ·
··· ·· ··· ··· ··· ···
··· ··· ··· ··· ··· ···
· · ·· ·· ·· ··
·· · ·· ·· ·· ··
·· · ··· ··· ··· ···

See Special Operations· Figure 24 •

No Operation

NOP

01

Return From Interrupt

RTI

3B 10

1

Return From Subroutine

RTS

39

5

1

Software Interrupt

SWI

3F 12

1

Wait For Interrupt

WAI

3E

1

2

1

9

1 1 1 1 1 1

See Special Operations· Figure 24 •

S

TABLE 12 - CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS
Condition Code Register
Operations

Inherent
MNEM Op

5

-

#

Boolean Operation

Clear Carry

ClC

OC

2

1

Clear Interrupt Mask

CLI

OE

2

1

O-C
0-1

Clear Overflow

ClV

OA

2

1

O-V

Set Carry

SEC

00

2

1

1-C

Set Interrupt Mask

SEI

OF

2

1

1-1

SEV

OB

2

1

1-V

CCR

TAP

06

2

1

A-CCR

Accumulator A

TPA

07

2

1

CCR-A

Set Overflow
Accumulator A CCR -

LEGEND
Op Operation Code (Hexadecimal!
- Number of MPU Cycles
MSp Contents of memory location pointed to by Stack Pointer
# Number of Program Bytes
+ Arithmetic Plus
- Arithmetic Minus
• Boolean AND
X Arithmetic Multiply
+ Boolean Inclusive OR
61 Boolean Exclusive OR
M Complement of M
Transfer Into
o Bit=Zero
00 Byte=Zero

3-124

CONDITION CODE SYMBOLS
H Half-carry from bit 3
I Interrupt mask
N Negative (sign bitl
Z Zero (by tel
V Overflow, 2's complement
C Carry/Borrow from MSB
R Reset Always
S Set Always
t Affected
• Not Affected

H

··
···
·t
·

4
I

3

2

1

0

N

Z

V

C
R

· ·· ·· ·· ·
·· ·· ·· · ·
· ·· ·· · ··
·····
R

R

S

S

S

t

t

t

t

t

MC6801 U4, MC6803U4

TABLE 13 - INSTRUCTION EXECUTION TIMES IN E CYCLES
ADDRESSING MODE

ADDRESSING MODE

!III
"6
II>

E

ABA
ABX
ADC
ADD
ADDD
AND
ASL
ASLD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BHS
BIT
BLE
BLO
BLS
BLT
BMI
BNE
BPL
BRA
BAN
BSR
BVC
BVS
CBA
CLC
CLI
CLR
CLV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOR
INC
INS

~

II>

ti

~

c:

~

~
II)

C
II>
~

a:

.E

0

w

~

.=

.=

•
•

•
•3

•
•

••

2
3

2
2
4
2

•••
•
•
•
••
•
•2

•
••

f

3
5
3

•
•
•
••
•
•
•
••
3
•
•
•

4
4
6
4
6

•6
••
•
•
•
••
4

~

4
4
6
4
6

•
6

••
••
•
•
•
4

~

•
•

••
2
3
2

••
••
••
••

!III

II>

~III

"6
II)

E
.§

a;

•
••

INX
JMP
JSR
LDA
LDD
LDS
LDX
LSL
LSLD
LSR
LSRD
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RT!
RTS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
T'PA
TST
TSX
TXS
WAI

••
•
••
•
3
3
3

3
3
3
3

•3
3
3
3
3
3
3

3
3
6
3
3

6

2

•
•••
•
4

2

•
•

3

•5
•
••
•3
•
•

•
4
6
6

6

•
4
6
6

•6
•
•

•6
•
•

•

•

4
6

4
6

2
2
2
2
2

•2
•
2
2
3
3

••
3

3-125

•
••
2
3
3
3

•
•
••

••
•
••
••
2

•
•
••
•
•••
•
•
•
•
2

2
4

•
•
•
•
••
••
•

~

II>

ti
f

~

c:

!I(

~

II>
I(

II>

~

0

w

.=

•

•

•

•
5
3
4
4
4

••

3
6
4
5
5
5
6

•

•
•
•
•
•3
•
•
••
•
•
•••
3
•
••
3

••
•4
••
•4

4
4
4
3
5

5
5
5
4
6

••
•
•
•
•
•
•
•

6

•
•6
•
4

••

••6
6

3
6
4
5
5
5
6

•6
•

•
6

•
•••
•

~

3

•
•
•
•

••

2
3
2
3
10
2
2

•3

6
6

4
4
5
2
2
10
5
2

•
•
•
••
4

•

4
5
5
5
4
6

•••
••

•
•
•

•
•
•

6

II)

.~

.=

4

••
•
•
•
6

C
II>
~

•2
2
2

•
•
•
•
•
•
12
2
2
2
2
2
3
3
9

•
••
••

••
•
•
•
•
•

•

I

MC6801 U4, MC6803U4

TABLE 14 -

Address Mode and
Instructions

CYCLE-BY-CYCLE OPERATION (Sheet 1 of 5)

R/W
Address Bus

Data Bus

Line

IMMEDIATE

2

1
2

Opcade Address
Opcade Address + 1

1
1

Opcade
Operand Data

LDS
LDX
LDD

3

1
2

Opcade Address
Opcade Address + 1
Opcade Address + 2

1
1
1

Opcade
Operand Data I High Order Bytei
Operand Data (Low Order Bytei

CPX
SUBD
ADDD

4

Opcade Address
Opcade Address + 1
Opcade Address + 2
Address Bus FFFF

1
1
1
1

Upcade
Operand Data (High Order Bytei
Operand Data (Low Order Bytei
Low Byte of Restart Vector

Opcade Address
Opcode Address + 1
Address of Operand

1
1
1

Opcode
Address of Operand
Operand Data

Opcade Address
Opcode Address + 1
Destination Address

1
1

0

Opcode
Destination Address
Data from Accumulator

Opcade Address
Opcode Address + 1
Address of Operand
Operand Address + 1

1
1
1
1

Opcode
Address of Operand
Operand Data (High Order By tel
Operand Data (Low Order Bytei

Opcode Address
Opcode Address + 1
Address of Operand
Address of Operand + 1

I
1

0
0

Opcode
Address of Operand
Register Data I High Order By tel
Register Data I Low Order By tel

Opcode Address
Opcode Address + 1
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1

Opcode
Address of Operand
Operand Data IHlgh Order By tel
Operand Data ILow Order By tel
Low Byte of Restart Vector

Opcode Address
Opcade Address + 1
Subroutine Address
S tack Pointer
S tack POinter - 1

1
1
1

Opcode
Irrelevant Data
First Subroutine Opcode
Return Address I Low Order By tel
Return Address I High Order By tel

ADC
ADD
AND
BIT
CMP

I

EOR
LDA
ORA
SBC
SUB

3
1
2

3
4

DIRECT

ADC
ADD
AND
BIT
CMP
STA

EOR
LDA
ORA
SBC
SUB

3

1
2

3

3

1

2
3
LDS
LDX
LDD

4

1
2

3
4

STS
STX
STD

4

1
2

3
4

CPX
SUBD
ADDD

5

1
2

3
4

5
JSR

5

1

2
3
4

5

0
0

3-126

MC6S01 U4, MC6S03U4

TABLE 14 -

CYCLE-BY-CYCLE OPERATION (Sheet 2 of 5)

R/W

Address Mode and
Instructions

Address Bus

Line

Data Bus

EXTENDED

JMP

3

1
2

3
ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB

STA

4

1
2

3
4
4

1
2

3
4

5

LDS
LDX
LDD

1
2

3
4

5
STS
STX
STD

5

1
2

3
4

5
ASL
ASR
CLR
COM
DEC
INC
CPX
SUBD
ADDD

LSR
NEG
ROL
ROR
TST*

6

1
2

3
4

5
6
6

1
2

3
4

5
6
JSR

6

1
2

3
4

5
6

Opcode Address
Opcode Address+ 1
Opcode Address + 2

1
1
1

Opcode
Jump Address (High Order Bytei
Jump Address (Low Order Bytei

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand

1
1
1
1

Opcode
Address of Operand
Address of Operand (Low Order Bytei
Operand Data

Opcode Address
Opcode Address + 1
Opcode Address + 2
Operand Destination Address

1
1
1
0

Opcode
Destination Address (High Order Bytei
Destination Address (Low Order Bytei
Data from Accumulator

Opcode Address
Opcode Address+ 1
Opcode Address + 2
Address of Operand
Address of Operand+ 1

1
1
1
1
1

Opcode
Address of Operand (High Order Bytei
Address of Operand (Low Order Bytei
Operand Data (High Order Bytei
Operand Data (Low Order Bytei

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand
Address of Operand + 1

1
1
1
0
0

Opcode
Address
Address
Operand
Operand

Opcode Address
Opcode Address + 1
pcode Address + 2
Address of Operand
Address Bus FFFF
Address of Operand

1
1
1
1
1
0

Opcode
Address of Operand (High Order Bytei
Address of Operand (Low Order Bytei
Current Operand Data
Low Byte of Restart Vector
New Operand Data

Opcode Address
Opcode Address + 1
Opcode Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1
1

Opcode
Operand Address (High Order Bytei
Operand Address (Low Order Bytei
Operand Data (High Order Bytei
Operand Data (Low Order Bytei
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Opcode Address + 2
Subroutine Starting Address
Stack Pointer
S tack POinter - 1

1
1
1
1
0
0

Opcode
Address of Subroutine (High Order Bytei
Address of Subroutine (Low Order Bytei
Opcode of Next Instruction
Return Address (Low Order Bytei
Return Address (High Order Bytei

o

*TST does not perform the write cycle during the Sixth cycle The Sixth cycle

3-127

IS

of Operand (High Order Bytei
of Operand (Low Order Bytei
Data (High Order Bytei
Data (Low Order Bytei

another address bus= $FFFF

11

Me6801 U4, MC6803U4

TABLE 14 Address Mode and
Instructions

CYCLE-BY-CYCLE OPERATION (Sheet 3 of 51

R/W
Address Bus

Line

Data Bus

INDEXED

3

JMP

1

2

3
ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB

4

3
4
4

STA

1

2

1

2

3
4

I

LDS
LDX
LDD

5

STS
STX
STD

5

ASL
ASR
CLR
COM
DEC
INC

1

2
3
4
5
1

2
3
4
5
LSR
NEG
ROL
ROR
TST*

6

1

2
3
4
5
6

CPX
SUBD
ADDD

6

JSR

6

1

2
3
4
5
6
1

2
3
4
5
6

Opcode Address
Opcode Address+ 1
Address Bus FFFF

1
1
1

Opcode
Offset
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset

1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset

1
1
1

0

Opcode
Offset
Low Byte of Restart Vector
Operand Data

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data I High Order Bytei
Operand Data I Low Order Bytei

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data IHigh Order Bytei
Operand Data ILow Order Bytei

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset

0
0
1
1
1
1
1

0

Opcode
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register+ Offset
Index Register+ Offset + 1
Address Bus FFFF

1
1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data IHigh Order Bytei
Operand Data ILow Order Bytei
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register+ Offset
Stack Pointer
Stack Pointer-l

1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
First Subroutine Opcode
Return Address ILow Order Bytei
Return Address I High Order Bytei

0
0

*TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus= $FFFF.

3-128

MC6801 U4, MC6803U4

TABLE 14 Address Mode and
Instructions

CYCLE-BY-CYCLE OPERATION (Sheet 4 of 5)

R/W
Address Bus

Line

Data Bus

INHERENT
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM

DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA

2

1
2

Opcode Address
Opcode Address+ 1

1
1

Opcode
Opcode of Next Instruction

ABX

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Irrelevant Data
Low Byte of Restart Vector

ASLD
LSRD

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Irrelevant Data
Low Byte of Restart Vector

DES
INS

3

1
2
3

Opcode Address
Opcode Address + 1
Previous Stack Pointer Contents

1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data

INX
DEX

3

1
2
3

Opcode Address
Opcode Address+ 1
Address Bus FFFF

1
1
1

Opcode
Opcode of Next Instruction
Low Byte of Rest
~

EXTND

I

'

Main Program

IT

$BD~

I

RTNL

RTI Return from Interrupt

Cf

Main Program

PC

e>-:::~rn

JSR

~

,"""","m,,,m
RTI
$3B~

Ie>
c)

I

JSR

Subr. Addr

Next Main Inst

RTN

BSR, Branch To Subroutine

~

Main Program
~

$8D~

¢~

8SR

± K~ Offset
RTN

I Next Main Instr

RTS, Return from Subroutine

~

$39~RTS

SP-l
SP

Subroutine

I

SP-2

I

Stack

E

RTNH

SP- 5

Acmltr B

SP-4

AcmltrA

SP-3

Index Register (XH)

C

Condition Code

SP-2

Index Register (XL)

SP-l

RTNH

SP

RTNL

~

Stack

SP
Condition Code

~

LV

SP~

Stack

SP+ 1

RTNH

SP + 2

RTNL

INDXD

SP+ 2

AcmltrB

SP+3

AcmltrA

SP+4

Index Register (XH)

SP+5

Index Register (XL)

SP+6

RTNH

SP+7

RTNL

~

JMP, Jump

RTNL

~

-+

~

I

Main Program

PC

,~

$7E~JMP

'"," "W",,;OO

Legend
RTN ~ Address of next instruction in Main Program to be executed upon return from subroutine
RTNH ~ Most significant byte of Return Address
RTNL ~ Least significant byte of Return Address
- ~ Stack Pointer After Execution
K ~ 8-bit Unsigned Value

III

"""'"'

.~
3:
en
CO
o

SP-7
SP-6

SP+ 1

SH ~ Subr. Addr.
SL~

Stack

KH ~ Next Address

{

KL ~ Next Address

K

I

Next Instruction

o

W

~

MC6801U4, MC6803U4

APPENDIX
CUSTOM MC6801U4 ORDERING INFORMATION

($FOOO-$FFFF). See Figure A-1 for recommended marking
procedure.
FIGURE A-l

~
~

A.1 CUSTOM MC6801U4 ORDERING INFORMATION
The custom MC6801 U4 specifications may be transmitted
to Motorola in any of the following media:
1) EPROMs
2) MDOS diskette
The specification should be formatted and packed, as irldicated in the appropriate paragraph below, and mailed
prepaid and insured with a cover letter (see Figure A-2) to:

I

Motorola Inc.
3501 Ed Bluestein Blvd.
Austin, Texas 78721
Mail Drop L-13

~
~

xxx = Customer ID

After the EPROMs are marked, they sould be placed in a
conductive IC carrier and securely packed. Do not use
styrofoam.

A.3 DISKETTE (MOOS)
The startl end location should be written on the label using
EXORciser format.

A copy of the cover letter should also be mailed separate-

r----MC6801U4Ll UNICORN Monitor----...

ly.

An MC6801 U4 may be purchased without specifying the ROM pattern. This standard part is labeled as
MC6801U4L 1 and contains a 2K monitor (UNICORN)
in the ROM. This monitor may be used to evaluate and
debug a program under development. Details and a
source listing are specified in the UNICORN Monitor
Reference Manual M68UNICORN(Dl).

A.2 EPROMs
MCM2708 and MCM2716 type EPROMs, programmed
with the custom program (positive logic sense for address
and data), may be submitted for pattern generation. Both
the MCM2708s and MCM2716s must be clearly marked to indicate which PROM corresponds to which address space
EXORciser is a registered trademark of Motorola Inc.
UNICORN is a trademark of Motorola Inc.

FIGURE A-2
Customer Name _____________________________________________________________________________________
Address __________________________________________________________________________________________
State ___________________________________________________ City _____________________ Zip _ _ _ _ __
Phone I _ _ I _____________________________________________________ Extenslon _______________________
Contact Ms/Mr _____________________________________________________________________________________
Customer Part # ________________________________________________________________________________

Package Type
o Ceramic
o Plastic
Marking
o Standard
Special

o

Pattern Medid
o 2708 EPROM
o 2716 EPROM
o Diskette IMOOS)

o

OTHERISeeNote) __________________________________________________________________________

NOTE: Other media require prior factory approval
Signature ____________________________________________________________________________________
Title ___________________________________________________________________________________

3-132

®

MOTOROLA

Advance Information

I
MC6804J2
8-BIT MICROCOMPUTER

This document contains information on a new product Specifications and information herein
are subject to change without notice

3-133

MC6804J2

TABLE OF CONTENTS
Paragraph
Number

Page
Number

Title
Section 1
Introduction

I

1.1
1.2

General ...
Features.

3-139
3-139

2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5

Section 2
Functional Pin Description, Memory, CPU, And Registers
Functional Pin Description.
. ................
VCC and VSS·
...
IRQ.
XTAL and EXTAL.
. .....
TIMER. . .
. .....
RESET.
. . . . . . . . .. ..........
MDS.
.........
Input/Output Lines (PA4-PA7, PBO-PB7) .
...
Memory.
Central Processing Unit.
.. ....
Registers ......... .
.
......
Accumulator (A).
. ................
Indirect Registers (X, Y) ..
......
Program Counter ....
Flags (C, Z).
· .....
Stack.
. ......... .
· .....

3-142
3-142
3-142
3-142
3-142
3-142
3-143
3-143
3-143
3-143
3-145
3-145
3-145
3-145
3-146
3-146

Section 3
Timer

3.1
3.2
3.2.1
3.2.2
3.2.3

Introduction ..
Timer Registers.
Timer Count Register (TCR).
Timer Status/ Control Register (TSCR) ..
Timer Prescaler Register ............. .

......
· .....
· .....
· ....

4.1
4.1.1
4.1.2
4.1.3

Section 4
Interrupt, Self-Test, Reset, And Internal Clock Generator
Interrupt.
Edge-Sensitive Option ..
Level-Sensitive Option.
Power Up and Timing.

3-151
...... 3-151
3-151
3-151

3-134

3-147
3-149
3-149
3-149
3-150

MC6804J2

TABLE OF CONTENTS
( Continued)
Paragraph
Number

4.2
4.3
4.4

Title

Self-Test...
Reset ...
Internal Clock Generator Options ..

Page
Number

3-153
3-153
3-153

Section 5
Input/ Output Ports

5.1
5.2
5.2.1
5.2.2

Input/Output ...
Registers ....
Port Data Registers.
Port Data Direction Registers.

3-158
3-160
3-160
3-160

Section 6
Software And Instruction Set

6.1
Software ....
6.1.1
Bit Manipulation.
6.1.2
Addressing Modes.
6.1.2.1
Immediate ...
Direct.
6.1.2.2
Short Direct ..
6.1.2.3
Extended
6.1.2.4
Relative ...
6.1.2.5
6.1.2.6
Bit Set/ Clear ...
6.1.2.7
Bit Test And Branch ...
Register-Indirect ..
6.1.2.8
6.1.2.9
Inherent ..
Instruction Set ..
6.2
6.2.1
Register/ Memory Instructions.
Read- M odify-Write Instructions.
6.2.2
6.2.3
Branch Instructions ..
Bit Manipulation Instructions ..
6.2.4
Control Instructions.
6.2.5
Alphabetical Listing ...
6.2.6
6.2.7
Opcode Map Summary.
6.3
Implied Instructions ..

3-161
3-161
3-162
3-162
3-162
3-162
3-162
3-162
3-162
3-163
3-163
3-163
3-163
3-163
3-163
3-163
3-163
3-167
3-167
3-167
3-167

Section 7
Electrical Specifications

7.1
7.2
7.3

3-172
3-172
3-172

Introduction ...
Maximum Ratings.
Thermal Characteristics ...

3·135

I

MC6804J2

TABLE OF CONTENTS
( Continued)
Paragraph
Number

7.4
7.5
7.6
7.7

Title

Power Considerations ..
Electrical Characteristics ..
Switching Characteristics.
Port DC Electrical Characteristics.

Page
Number

3-173
3-173
3-173
3-174

Section 8
Ordering Information

I

8.1
8.1.1
8.1.2
8.2
8.3
8.4

Introduction.
EPROMs.
MDOS Disk File.
Verification Media.
ROM Verification Units (RVUs).
Flexible Disks ...

3-175
3-175
3-175
3-175
3-176
3-176

Section 9
Mechanical Data

9.1

3-178

Pin Assignment.

3-136

MC6804J2

LIST OF ILLUSTRATIONS
Figure
Number

Title

Page
Number

1-1

MC6804J2 MCU Block Diagram ..

3-141

2-1
2-2

MC6804J2 MCU Address Map.
Programming Model.

3-144
3-145

3-1

Timer Block Diagram.

3-148

4-1
4-2
4-3

3-152
3-154
3-155
3-155
3-156

4-7

Reset and Interrupt Processing Flowchart.
Self-Test Circuit.
Power-Up Reset Delay Circuit.
Clock Generator Options.
Crystal Motional Arm Parameters and Suggested PC Board Layout.
Typical Frequency Selection for Resistor-Capacitor Oscillator Option
(CL=17 pF).
Clock Generator Timing Diagram ..

5-1
5-2

Typical I/O Port Circuitry.
Typical Port Connections.

3-158
3-159

6-1

Bit Manipulation Example.

3-161

7-1
7-2
7-3

LSTTL Equivalent Test Load (Port B).
CMOS Equivalent Test Load (Ports A and B)
LSTTL Equivalent Test Load (Port A and TIMER)

3-172
3-172
3-172

8-1

Ordering Form.

3-177

4-4
4-5
4-6

3-137

3-156
3-157

I

MC6804J2

LIST OF TABLES
Table
Number

I

Title

Page
Number

3-1

Prescaler Coding Table.

3-147

6-1
6-2
6-3
6-4
6-5
6-6
6-7

Register / M emory Instructions.
Read-Modify-Write Iristructions.
Branch Instructions.
Bit Manipulation Instructions.
Control Instructions.
Instruction Set.
MC6804J2 Microcomputer Instruction Set Opcode Map

3-164
3-165
3-166
3-166
3-168
3-169
3-170

3-138

MC6804J2

SECTION 1
INTRODUCTION
1.1 GENERAL
The MC6804J2 microcomputer unit (MCU) is a member of the M6804 Family of very low-cost
single-chip microcomputers. This 8-bit microcomputer contains a CPU, on-chip CLOCK, ROM,
RAM, I/O, and TIMER. It is designed for the user who needs an economical microcomputer with
the proven capabilities of the M6800-based instruction set.

1.2 FEATURES
The following are some of the hardware and software features of the MC6804J2 MCU.

HARDVVAREFEATURES
•
•
•
•
•
•

5-Volt Single Supply
32 Bytes of RAM
Memory Mapped I/O
1008 Bytes of Program ROM
64 Bytes of Data ROM
12 Bidirectional I/O Lines (Eight Lines with High Current Sink Capability)

• On-Chip Clock Generator
• Self-Test Mode
•
•
•
•
•

Master Reset
Complete Development System Support on EXORciser
Software Programmable 8-Bit Timer Control Register and Timer Prescaler (7 Bits, 2n)
Timer Pin is Programmable as Input or Output
On-Chip Circuit for ROM Verify

SOFTVVARE FEATURES
• Similar to M6805 HMOS Family
• Byte Efficient Instruction Set
• Easy to Program
• True Bit Manipulation
• Bit Test and Branch Instruction

3·139

I

MC6804J2

SOFTWARE FEATURES (Continued)
•
•
•
•
•
•
•
•

Separate Flags for Interrupt and Normal Processing
Versatile Indirect Registers
Conditional Branches
Single Instruction Memory Examine/Change
True LIFO Stack Eliminates Stack Pointer
Nine Powerful Addressing Modes
Any Bit in Data Space Memory May be Tested
Any Bit in Data Space Memory Capable of Being Written to May be Set or Cleared

USER SELECTABLE OPTIONS

I

• 12 Bidirectional I/O Lines with LSTTL,LSTTLICMOS, or Open-Drain Interface
• Crystal or Low-Cost ReSistor-Capacitor Oscillator
• Mask Selectable Edge- or Level-Sensitive Interrupt Pin

3-140

i:

o
en
CO

o

~

c..

N

TIMER

Accumulator

Cf>
-"'"
~

-"'"

PAA

P~rt

PA5

l'IO PA6
Ines
PA7

3

Port

R:9

H
u

Dlr
D,"
Reg

1008 x 8
User Program ROM
304x8
Sel(Test ROM

Indirect
Register
(Notel
Indirect
Register
(Notel

AI
X

y

Stack
12
Program
Counter
High PCH,

18

CPU
Control

CPU

~

~

Dlr
Reg.

D'"
8

P
art
RB
eg

~PBC

PBl
PB2
PB3

AlU

Program
Counter
low PCl

NOTE 8-Bit indirect registers X and Y, although shown as part of the CPU, are actually located in the 32 x 8 RAM at locations $80
and $81

Figure 1-1. MC6804J2 MCU Block Diagram

Port
B

PB4 1/0
PB5 lines
PB6
PB7

MC6804J2

SECTION 2
FUNCTIONAL PIN DESCRIPTION, MEMORY, CPU, AND REGISTERS
This section provides a description of the functional pins, memory spaces, the central processing
unit (CPU), and the various registers and flags.
2.1 FUNCTIONAL PIN DESCRIPTION
2.1.1 VCC and VSS
Power is supplied to the MCU using these two pins. VCC is power and VSS is the ground
connection.

I

2.1.2 IRQ
This pin provides the capability for asynchronously applying an external interrupt to the MCU. Refer
to 4.1 INTERRUPT for additional information.
2.1.3 XTAL and EXTAL
These pins provide connections to the on-chip clock oscillator circuit. A crystal, a resistor and
capacitor, or an external signal, depending on the user selectable manufacturing mask option, can
be connected to these pins to provide a system clock source with various stability/ cost tradeoffs.
Lead lengths and stray capacitance on these two pins should be minimized. Refer to 4.4 INTERNAL
CLOCK GENERATOR OPTIONS for recommendations concerning these inputs.
2.1.4 TIMER
In the input mode, the timer pin is connected to the prescaler input and serves as the timer clock. In
the output mode, the timer pin signals that a time out of the timer has occurred. Refer to SECTION
3 TIMER for additional information.
2.1.5 RESET
The RESET pin is used to restart the processor of the MC6804J2 to the beginning of a program.
This pin, together with the MDS pin, is also used to select the operating mode of the MC6804J2. If
the MDS pin is at zero volts, the normal mode is selected and the program counter is loaded with
the user restart vector. However, if the MDS pin is at + 5 volts, then pins PA6 and PA7 are decoded
to allow selection of the operating mode. Refer to 4.3 RESET for additional information.

3·142

MC6804J2

2.1.6 MDS
The MDS (mode select) pin is used to place the MCU into special operating modes. If MDS is held
at + 5 volts at the exit of the reset state, the decoded state of PA6 and PA7 is latched to determine
the operating mode (single-chip, self-test, or ROM verify). However, if MDS is held at zero volts
at the exit of the reset state, the single-chip operating mode is automatically selected (regardless of
PA6 and PA7 state).
For those users familiar with the MC6801 microcomputer, mode selection is similar but much less
complex in the MC6804J2. No special external diodes, switches, transistors, etc. are required in the
MC6804J2.
2.1.7 Input/Output Lines (PA4-PA7, PBO-PB7)
These 12 lines are arranged into one 4-bit port (A) and one 8-bit port (8). All lines are programmable
as either inputs or outputs under software control of the data direction registers. Refer to SECTION
5 INPUT/OUTPUT PORTS for additional information.
2.2 MEMORY
The MCU operates in three different memory spaces: program space, data space, and stack space.
A representation of these memory spaces is shown in Figure 2-1. The program space (Figure 2-1 a)
contains all of the instruotions that are to be executed, as well as the data required for the immediate addressing mode instructions, and the self-test and user vectors. The data space (Figure
2-1 b) contains all of the RAM locations, plus I/O locations and some ROM used for storage of
tables and constants. The stack space (Figure 2-1 c) contains RAM which is used for stacking
subroutine and interrupt return addresses.
The MCU is capable of addreSSing 4096 bytes of program space memory with its program counter
and 256 bytes of data space memory with its instructions. The data space memory contains three
bytes for port data registers, three bytes for port data direction registers, one byte for timer
status/control, 64 bytes ROM, 32 bytes RAM (which includes two bytes for X and Y indirect
registers), two bytes for timer prescaler and count registers, and one byte for the accumulator. The
program space section includes 304 bytes of self-test ROM, 1000 bytes program ROM, and eight
bytes of vectors for self-test and user programs.
2.3 CENTRAL PROCESSING UNIT
The CPU of the M6804 Family is implemented independently from the I/O or memory configuration.
Consequently, it can be treated as an independent central processor communicating with I/O and
memory via internal addresses, data, and control buses.

3-143

I

MC6804J2

(al Program Space Memory Map

(bl Data Space Memory Map

$000

Port A Data Reg iste

Reserved (All Ones)

1· 0 1 0 I 0 I 0

Port B Data Register

$ADF
$AEO

1

I1 I 1 I1 I0 I0 I0 I0

Self-Test ROM

Not Used

I0 I0 I0 I0

PortA DDR

$COF
$Cl0

Port B Data Direction Register
1

Program ROM

I 1I 1 I 1I0 I0 I0 I0

$00
$01
$02
$03
$04
$05
$06
$07

Not Used
$FF7

I

Self- Test IRQ Vector

$FF8-$FF9

Self-Test Restart Vector

$FFA-$FFB

User IRQ Vector

$FFC-$FFD

User Restart Vector

$FFE-$FFF

Timer Status Control Register

$08
$09
$OA

Future Expansion
$1 F
$20
User Data Space ROM
$5F
$60

(cl Stack Space Memory Map

Future Expansion

Levell

Indirect Register X

Level 2

Indirect Register Y

Level 3

$7F
$80
$81
$82

Level 4
Data Space RAM

$9F
$AO
Future Expansion
$FC
Prescale~

$FD

Timer Count Register

$FE

Accumulator

$FF

Figure 2-1. MC6804J2 MCU Address Map

3·144

Register

MC6804J2

2.4 REGISTERS
The M6804 Family CPU has four registers and two flags available to the programmer. They are
shown in Figure 2-2 and are explained in the following paragraphs.

0
Accumulator

A

These Are
Registers
In Data
Space RAM

0

I

X

Indirect
Register X

0

I

y

0

8 7

11
PCH

Indirect
Register Y

I

PCl

Normal Flags

Interrupt Flags

•

W

..

rn

Program
Counter

Figure 2-2. Programming Model

2.4.1 Accumulator (A)
The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical
operations, and data manipulations. The accumulator is implemented as the highest RAM location
($FF) in data space and thus implies that several instructions exist which are not explicitly implemented. Refer to 6.3 IMPLIED INSTRUCTIONS for additional information.
2.4.2 Indirect Registers (X, V)
These two indirect registers are used to maintain pointers to other memory locations in data space.
They are used in the register-indirect addressing mode, and can be accessed with the direct, indirect, short direct, or bit set/ clear addressing modes. These registers are implemented as two of
the 32 RAM locations ($80, $81) and as such generate implied instructions and may be manipulated
in a manner similar to any RAM memory location in data space. Refer to 6.3 IMPLIED INSTRUCTIONS for additional information.
2.4.3 Program Counter (PC)
The program counter is a 12-bit register that contains the address of the next ROM word to be used
(may be opcode, operand, or address of operand). The 12-bit program counter is contained in PCl
(low byte) and PCH (high nibble).

3-145

I

MC6804J2

2.4.4 Flags (C, Z)

The carry (C) bit is set on a carry or a borrow out of the ALU. It is cleared if the result of an
arithmetic operation does not result in a carry or a borrow. The (C) bit is also set to the value of the
bit tested in a bit test instruction, and participates in the rotate left instruction.
The zero (Z) bit is set if the result of the last arithmetic or logical operation was equal to zero, otherwise it is cleared.

I

There are two sets of these flags, one set is for interrupt processing, the other for all other routines.
When an interrupt occurs, a context switch is made from the program flags to the interrupt flags
(interrupt model. An RTI forces the context switch back to the program flags (program mode).
While in either mode, only the flags for that mode are available. Further, the interrupt flags will not
be cleared upon entering the interrupt mode. Instead, the flags will be as they were at the exit of the
last interrupt mode. Both sets of flags are cleared by reset.
2.4.5 Stack

There is a true LIFO stack incorporated in the MC6804J2 which eliminates the need for a stack
pointer. Stack space is implemented in separate RAM (12-bits wide) shown in Figure 2-1 c.
Whenever a subroutine call (or interrupt) occurs, the contents of the PC are shifted into the top
register of the stack. At the same time (same cycle), the top register is shifted to the next level
deeper. This happens to all registers with the bottom register falling out the bottom of the stack.
Whenever a subroutine or interrupt return occurs, the top register is shifted into the PC and all
lower registers are shifted up one level higher. The stack RAM is four levels deep. If the stack is
pulled more than four times without any pushes, the address that was stored in the bottom level will
be shifted into the PC.

MC6804J2

SECTION 3
TIMER
3.1 INTRODUCTION
A block diagram of the MC6804J2 timer circuitry is shown in Figure 3-1. The timer logic in the MCU
is comprised of a simple 8-bit counter (timer count register, TCR) with a 7-bit prescaler, and a timer
status/ control register nSCR). The timer count register, which may be loaded under program control, is decremented towards zero by a clock input (prescaler output). The prescaler is used to extend the maximum interval of the overall timer. The prescaler tap is selected by bits 0-2 (PSO-PS2)
of the timer status/ control register. Bits PSO-PS2 control the actual division of the prescaler within
the range of divide-by-l (20 ) to divide-by-128 (27). The timer count register nCR) and prescaler are
decremented on rising clock edges. The coding of the TCSR PSO-PS2 bits produce a division in the
prescaler as shown in Table 3-1.

Table 3-1. Prescaler Coding Table
PS2
0
0
0
0

PSl
0
0
1
1

PSO
0
1

0
1

PS2

Divide By

1
1
1
1

1
2
4
8

Divide By

PSl
0
0

PSO
0

1
1

0

64

1

128

1

16
32

The TIMER pin may be programmed as either an input or an output depending on the status of
TOUT nSCR bit 5), Refer to Figure 3-1. In the input mode, TOUT is a logic zero and the TIMER pin
is connected directly to the prescaler input. Therefore, the timer prescaler is clocked by the signal
applied from the TIMER pin. The prescaler then divides its clock input by a varue determined by the
coding of the TSCR bits PSO-PS2 as shown in Table 3-1. The divided prescaler output then clocks
the 8-bit timer count register (TCR). When the TCR is decremented to zero, it sets the TMZ bit in
the timer status/ control register (TSCR). The TMZ bit can be tested under program control to perform a timer function whenever it goes high. The frequency of the external clock applied to the
TIMER pin must be less than tbyte (fosc/48)'
In the output mode, TOUT is a logic one and the TIMER pin is connected to the DOUT latch.
Therefore, the timer prescaler is clocked by the internal sync pulse (divide-by-48 of the internal
oscillator). Operation is similar to that described above for the input mode. However, in the output
mode, the low-to-high TMZ bit transition is used to latch the DOUT bit of the TSCR and provide it
as output for the TIMER pin.
NOTE
TMZ is normally set to logic one when the timer times out (TC R decrements to $00);
however, it may be set by a write of $00 to the TCR or by a write to bit 7 of the TSCR.

3-147

I

•

3:

oen

Q)
Q
~

c..

N

Microcomputer Internal Bus
Sync

bO

Prescaler

TIMER
Pin

Select
1--_ _ _ _-II'-of-8
Initialize

Timer Count Register
(TCR)

Timer Status/ Control
Register (TSCR)
TMZ

3

4>

....I.

~

ex>

TIMER Pin Status
TOUT

0

Prescaler
Clock

TIMER
Pin

TIMER Pin
Sync

Input Mode
Output Mode

Figure 3-1. Timer Block Diagram

MC6804J2

During reset, the timer count register and prescaler are set to $FF, while the timer status/ control
register is cleared to $00 and the DOUT LATCH (TIMER pin is in the high-impedance input mode) is
forced to a logic high. The prescaler and timer count register are implemented in data space RAM
locations ($FD, $FE); therefore, they are both readable and writeable. A write to either will
predominate over the TCR decrement-to-$OO function; i.e., if a write and a TCR decrement-to-$OO
occur simultaneously, the write will take precedence, and the TMZ bit is not set until the next timer
time out.

3.2 TIMER REGISTERS
3.2.1 Timer Count Register (TCR)

o
LSBI

IMSB
TCR addr = $FE

The timer count register indicates the state of the internal 8-bit counter.
3.2.2 Timer Status/ Control Register (TSCR)
7

6

TMZ

INot Usedl

4
TOUT

I DOUT

PSI

PS2

PSl

PSO

TSCR Address= $09

b7, TMZ

Low-to-high transition indicates the timer count register has decremented to zero
since the timer status/ control register was last read. Cleared by a read of TSCR
register if TMZ was read as a logic one.

b6

Not used.

b5, TOUT

When low, this bit selects the input mode for the timer. When high, the output
mode is selected.

b4, DOUT

Data sent to the timer output pin when TMZ is set high (output mode only).

b3, PSI

Used to initialize the prescaler and inhibit its counting while PSI = O. The initialized
value is set to $FF. The timer count register will also be inhibited (contents unchanged). When PSI = 1 the prescaler begins to count downward.

bO, b1, b2
PSO-PS1

These bits are used to select the prescaler divide-by ratio; therefore, effecting
the clock input frequency to the timer count register.

3-149

II

MC6804J2

3.2.3 Timer Prescaler Register

Lssl

IMSS

TPR Address = $FD

The timer prescaler register indicates the state of the internal 7-bit prescaler. This 7-bit prescaler
divide ratio is normally determined by bits PSO-PS2 of the timer status/ control register (see Table
3-1),

I

3-150

MC6804J2

SECTION 4
INTERRUPT, SELF-TEST, RESET, AND INTERNAL CLOCK GENERATOR
4.1 INTERRUPT

The MC6804J2 can be interrupted by applying a logic low signal to the IRQ pin; however, a mask
option selected at the time of manufacture determines whether the negative-going edge or the
actual low level is sensed to indicate an interrupt.
4.1.1 Edge-Sensitive Option

When the IRQ pin is pulled low, the internal interrupt request latch is set. Prior to each instruction
fetch, the interrupt request latch is tested and, if its output is low, an interrupt sequence is initiated
at the end of the current instruction (provided the interrupt mask is cleared!. Figure 4-1 contains a
flowchart which illustrates both the reset and interrupt sequence. The interrupt sequence consists
of one cycle during which: the interrupt request latch is cleared, the interrupt mode flags are
selected, the PC is saved on the stack, the interrupt mask is set, and the IRQ vector (single chip
mode= $FFC/$FFD, self-test mode= $FF8/$FF9) is loaded into the PC. Internal processing of the
interrupt continues until an RTI (return from interrupt) instruction is processed. During the RTI instruction, the interrupt mask is cleared and the program mode flags are selected. The next instruction of the program is then fetched and executed. Once the interrupt was initially detected and the
interrupt sequence started, the interrupt request latch is cleared so that the next (second) interrupt
may be detected even while the previous (first) one is being serviced. However, even though the
second interrupt sets the interrupt request latch during processing of the first interrupt, the second
interrupt sequence will not be initiated until completion of the interrupt service routine for the first
interrupt. Completion of an interrupt service routine is always accomplished using an RTI instruction to return to the main program. The interrupt mask (which is not directly available to the programmer) is cleared during the last cycle of the RTI instruction.
4.1.2 Level-Sensitive Option

The actual operation of the level-sensitive and edge-sensitive options are similar except that the
level-sensitive option does not have an interrupt request latch. With no interrupt request latch, the
logic level of the IRQ pin is checked for detection of the interrupt. Also, in the interrupt sequence,
there is no need to clear the interrupt request latch. These differences are illustrated in the flowchart
of Figure 4-1.
4.1.3 Power Up and Timing

During the power-up sequence the interrupt mask is set to preclude any false or "ghost" interrupts
from occurring. To clear the interrupt mask, the programmer should write a JSR (instead of a ..!MP)
instruction to an initialization routine as the first instruction in a program. The initialization routine

3-151

I

MC6804J2

Load Program
Counter from
Reset Vector
a-OORs
1 -Interrupt Mask
a-Interrupt Request
Latch (Edge
Sensitive Optionl
$FF-TCR
$OO-TSCR
$FF - Prescaler

Load PC
From IRQ
Vector
($FFC/$FFD)

Select
Program
Mode
Flags

II

Stack
Program
Counter
(PC)

Put $FFE
on
Address
Bus

Select
Interrupt
Mode
Flags

y

Pin
Low

y

N

Clear
Interrupt
Request
Latch

Check
Interrupt
Request
Latch
Output

N

Figure 4-1. Reset and Interrupt Processing Flowchart

3-152

MC6804J2

should end with an RTI (instead of RTSl. Maximum interrupt response time is six machine (tbyte)
cycles (see 4.4 INTERNAL CLOCK GENERATOR OPTIONS). This includes five machine cycles for
the longest instruction, plus one machine cycle for stacking the PC and switching flags. Minimum
response time is one machine cycle for stacking PC and switching flags (see 2.4.4 Flags (C, Z)).
4.2 SELF-TEST

The MC6804J2 MCU has a unique internal ROM-based off-line·self-test capability using signature
analysis techniques. A test program stored in the on-chip ROM is initiated by configuring pins PA6
and PA7 during reset. The test results are sampled on a cycle-by-cycle basis by a 16-bit on-chip
signature analysis register configured as a linear feedback shift register (LFS R) using the standard
CCITT CRC16 polynomial. A schematic diagram of the self-test connections is shown in Figure
4-2. To perform a test of the MCU, connect it as shown in Figure 4-2a and monitor the LEOs for a
1100 ($OC) pattern.
A special ROM self-test utilizing the signature analysis circuitry is also included. To initiate a test of
the ROM, connect the circuit as shown in Figure 4-2b. This mode also uses the on-chip signature
analysis register to verify the contents of the custom ROM by monitoring an internal bus. The
"Good" LED indicates that all ROM words have been read and that the result was the correct
signature.
The on-chip self-test and the ROM test are the basis of Motorola's production testing for the
MC6804J2. These tests have been fault graded using statistical methods (refer to "The M6804 BuiltIn Self-Test", Proceedings of 1983 International Test Conference, pp. 295-300, Oct. 1983) and have
been found to provide high fault coverage using automatic test equipment (ATE) or the circuit of
Figure 4-2.
4.3 RESET

The MCU can be reset in two ways: by initial power up (see Figure 4-1) and by the external reset input (RESET). During power up, a delay of tRHL is needed before allowing the RESET input to go
high. This time delay allows the internal clock generator to stabilize. Connecting a capacitor and
resistor to the RESET input, as shown in Figure 4-3, typically provides sufficient delay.
4.4 INTERNAL CLOCK GENERATOR OPTIONS

The internal clock generator circuit is designed to require a minimum of external components. A
crystal, a resistor-capacitor, or an external signal may be used to generate a system clock with
various stability/ cost tradeoffs. A manufacturing mask option is required to select either the crystal
oscillator or the RC oscillator circuit. The different clock generator option connection methods are
shown in Figure 4-4, crystal specifications and suggested PC board layouts are given in Figure 4-5,
resistor-capacitor selection graph is given in Figure 4-6, and a timing diagram is illustrated in Figure
4-7. The crystal oscillator startup time is a function of many variables: crystal parameters (especially
RS), oscillator load capacitance (CLl, IC parameters, ambient temperature, and supply voltage. To
ensure rapid oscillator startup, neither the crystal characteristics nor the load capacitance should
exceed recommendations.
The oscillator output frequency is internally divided by four to produce the internal  1 and 2
clocks. The 1 clock is 9ivided by twelve to produce a machine byte (cycle) clock. A byte cycle is
the smallest unit needed to execute any operation (i.e., increment the program counter). An instruction may need two, four, or five byte cycles to execute.

3-153

I

MC6804J2

+5V

MC6804J2
PA7~1~9~________~

0
L..-_ _ _ _2--t

+5V

PA6 18
PA5 17
PA4 16

RETI

330

, XT AL
r -__......._ _ _5
330

11

I

PB7 15
1
PB6 1-0-=-4+41>+-1----'
PB5 1-'1..::.3~+-+--.

PB41-'1.::.2~+4Ih

330

iR0

2
330

*Used with crystal option only.

. (a) Functional Test

10

+5V

MC6804J2

4.7 k

PA7
PA6
PA5
PA4
r - - _......_ _~5

J

19

18
17
16

XT AL

0*
..._---'4~ EXT AL

J

+5V _ _ _....,6::-i MDS

7 TIMER

PB7
PB6
PB5
PB4 t-:-::.-----4-_+_.
PB3
PB2 1 - - - - - . " _ _.....
PBl
PBO
SN74LS74

*Used with crystal option only.

(b) Simple ROM Verify Test

Figure 4-2. Self-Test Circuit

3-154

MC6804J2

+5V
4.7k

.I 10 l'F
Part Of
MC6804J2
MCU

Figure 4-3. Power-Up Reset Delay Circuit

I
r-::::L
-

CL2

CJ

XTAL

4

EXTAL

MC6804J2
MCU
(Crystal Mask
Optioni

+5V
NC
External
Clock
Input

4

EXTAL
XTAL

4.7 k

MC6804J2
MCU
(Crystal Mask
Optioni

EXTAL
MC6804J2
MCU
XTAL
(Resistor·Capacitor Mask
Optioni

External Clock

External Resistor·Capac;tor

Figure 4-4. Clock Generator Options

3-155

MC6804J2

ctJla)

Crystal Parameters

EXTAL4

C,

XTAL5

Crystal Parameters
AT - Cut Parallel Resonance Crystal
CO= 7 pF Maximum
Freq. =" MHz
RS = 50 Ohms Maximum

I

Piezoelectric ceramic resonators which
have the equivalent specifications may be
used instead of crystal oscillators. Follow
ceramic resonator manufacturer's suggestions for CO, C" and RS values.

Ib)

Ic)

NOTE: Keep crystal leads and circuit
connections as short as possible.

Figure 4-5. Crystal Motional Arm Parameters and Suggested PC Board Layout

N

'2.:1

i

10.0

~ 11.0

is 9.0
~ B.O
cr
Q

I-

7.0

~ 6.0

C3

:g 5.0
~

4.0
3.0
~ 2.0
8::
..: 1.0
..:

~

x

10

12

14

16

18

RESISTANCE (RLI IN kO

Figure 4-6. Typical Frequency Selection For Resistor-Capacitor
Oscillator Option (CL = 17 pF)

3-156

MC6804J2

(a) Oscillator - 1-2 Timing

OSC

(b) 1 - Sync Timing
1

r---l1_ _ _ _ _ _ _ _ _ _.
, .L

SYNC --l

Figure 4-7. Clock Generator Timing Diagram

3-157

I

MC6804J2

SECTION 5
INPUT/OUTPUT PORTS
5.1 INPUT/OUTPUT

I

There are 12 input! output pins. All pins (port A and B) are programmable as either inputs or outputs
under software control of the corresponding data direction register (DDRl. The port I/O programming is accomplished by writing the corresponding bit in the port DDR to a logic one for output or a
logic zero for input. On reset, all the DDRs are initialized to a logic zero state to put the ports in the
input mode. The port output registers are not initialized on reset but should be initialized before
changing the DDR bits to avoid undefined levels. When programmed as outputs, the latched output data is readable as input data, regardless of the logic levels at the output pin due to output
loading; see Figure 5-1. All input/ output pins are LSTTL compatible as both inputs and outputs. In
addition, both ports may have one of two mask options: 1) internal pullup resistor for CMOS output
compatibility, or 2) open drain output. The address map in Figure 2-1 gives the address of data
registers and DDRs. The register configuration is discussed under the registers paragraph below
and Figure 5-2 provides some examples of port connections.

Data
Direction Register
Bit

Latched
Output
Data
Bit

Data
Direction
Register
Bit

1
1
0

Output
Data
Bit

Output
State

0
1

0
1

X

Hi-Z

Input
To

MCU
0
1
Pin

Figure 5-1. Typical I/O Port Circuitry

3·158

MC6804J2

PA7

PB7
PB6

PA6
13

PA5
SN74LS04
or
MC14069
(Typical!

PA4

12

PB5
PB4
PB3
PB2

LSTTL Driving Port A Directly

PB1
PBO

CMOS or LSTTL Driving Port B Directly

I

(a) Input Mode

+ V
PA7

(CMOS Loadsi

PA6
PA5
PA4

(1 LSTTL Loadl

Port A, bit 7 programmed as output, driving
CMOS loads and bit 4 driving one LSTTL
load directly (using CMOS output optioni.

PB7

15

PB6

14

PB5

13

PB4

12

PB3

11

PB2

10

PB1

9

~

PBO

",,,,

~'"

~

Port B, bit 0, and bit 1 programmed as output,
driving LEOs directly.

(b) Output Mode

Figure 5-2. Typical Port Connections

3-159

MC6804J2

The latched output data bit (see Figure 5-1) may always be written. Therefore, any write to a port
writes to all of its data bits even though the port DDR is set to input. This may be used to initialize
the data registers and avoid undefined outputs; however, care must be exercised when using readmodify-write instructions since the data read corresponds to the pin level if the DDR is an input (0)
and corresponds to the latched output data when the DDR is an output (1). The 12 bidirectional
lines may be configured by port to be LSTTL (standard configuration), LSTTL/CMOS (mask option), or open drain (mask option). Port B outputs are LED compatible.
NOTE
The mask option only allows changes by port. For example, if the customer wishes PA7
to be open drain, then PA4-PA7 must all be open drain.
5.2 REGISTERS

I

The registers described below are implemented as RAM locations and thus may be read or written.
5.2.1 Port Data Register

o
LSBI

IMSB
Port A Address = $00
Port B Address= $01

The source of data read from the port data register will be the port I/O pin or previously latched output data depending upon the contents of the corresponding data direction register (DDR). The
destination of data written to the port data register will be an output data latch. If the corresponding
data direction register (DDR) for the port I/O pin is programmed as an output, the data will then appear on the port pin.
5.2.2 Port Data Direction Register
LSBI

/MSB
Port A Address = $04
Port B Address= $05

The port DDRs configure the port pins as either inputs or outputs. Each port pin can be programmed individually to act as an input or an output. A zero in the pins corresponding bit position
will program that pin as an input while a one in the pins corresponding bit position will program that
pin as an output.

3-160

MC6804J2

SECTION 6
S,OFTWARE AND INSTRUCTION SET
6.1 SOFTWARE
6.1.1 Bit Manipulation

The MC6804J2 MCU has the ability to set or clear any register or single random access memory
(RAM) writable bit with a single instruction (BSET, BCLR)' Any bit in data space, including ROM,
can be tested, using the BRSET and BRCLR instructions, and the program may branch as a result
of its state. The carry bit is set to the value of the bit referenced by BRSET or BRCLR.A,rotate instruction may then be used to accumulate serial input data in a RAM location or register. The
capability to work with any bit in RAM, ROM, or I/O allows the user to have individual flags in RAM
or to handle I/O bits as control lines.
The coding example in Figure 6-1 illustrates the usefulness of the bit manipulation and test instructions. Assume that the MCU is to communicate with an external serial device. The external device
has a data ready signal, a data output line, and a clock line (to clock data one bit at a time, MSB
first, out of the device). The MCU waits until the data is ready, clocks the external device, picks up
the data in the carry flag (C bit), clears the clock line, and finally accumulates the data bit in the
accumulator.

MCU
Ready
Senal
Device

Clock

SELF

BRSET

6,PORTA,SELF

CONT

BSET
BRCLR
BCLR
ROLA

5,PORTA
4,PORTA,CONT
5,PORTA

r-6P

0

5R
T

Data

4A

I--

Figure 6-1. Bit Manipulation Example

3·161

I

MC6804J2

6.1.2 Addressing Modes

The MC6804J2 MCU has nine addressing modes which are explained briefly in the following
paragraphs. The MC6804J2 deals with objects in three different address spaces: program space,
data space, and stack space. Program space contains the instructions which are to be executed,
plus the data for immediate mode instructions. Data space contains all of the RAM locations, X
and Y registers, accumulator, timer, I/O locations, and some ROM (for storage of tables and constants). Stack space contains RAM for use in stacking the return addresses for subroutines and
interrupts.
The term "Effective Address" (EA) is used in describing the address modes. EA is defined as the address from which the argument for an instruction is fetched or stored.

I

6.1.2.1 IMMEDIATE. In the immediate addressing mode, the operand is located in program ROM
and is. contained in a byte following the opcode. The immediate addressing mode is used to access
constants which do not change during program execution (e.g., a constant used to initialize a loop
counter) .
6.1.2.2 DIRECT. In the direct addressing mode, the effective address of the argument is contained
in a single byte following the opcode byte. Direct addressing allows the user to directly address the
256 bytes in data space memory with a single two-byte instruction.
6.1.2.3 SHORT DIRECT. The MCU also has four locations in data space RAM ($80, $81, $82, $83)
which may be used in a short-direct addressing mode. In this mode the lower two bits of the opcode
determine the data space. RAM location, and the instruction is only one byte. Short direct addressing is a subset of the direct addressing mode. (The X and Y registers are at locations $80 or $81
respectively.)
6.1.2.4 EXTENDED. In the extended addressing mode, the effective address is obtained by concatenating the four least significant bits of the opcode with the byte following the opcode (12-bit
address). Instructions using the extended addressing mode (JMP, JSR) are capable of branching
anywhere in program space. An extended addressing mode instruction is two bytes long.
6.1.2.5 RELATIVE. The relative addressing mode is only used in conditional branch instructions. In
relative addressing, the address is formed by adding the sign extended lower five bits of the opcode
(the offset) to the program counter if and only if the condition is true. Otherwise, control proceeds
to the next instruction. The span of relative addressing is from - 15 to + 16 from the opcode address. The programmer need not worry about calculating the correct offset when using the
Motorola assembler since it calculates the proper offset and checks to see if it is within the span of
the branch.
6.1.2.6 BIT SET/CLEAR. In the bit set/ clear addressing mode, the bit to be set or cleared is part of
the opcode, and the byte following the opcode specifies the direct address of the byte in which the
specified bit is to be set or cleared. Thus, any bit in the 256 locations of data space memory, which
can be written to, can be set or cleared.

3-162

MC6804J2

6.1.2.7 BIT TEST AND BRANCH. The bit test and branch addressing mode is a combination of
direct addressing and relative addressing. The bit which is to be tested is included in theopcode,
and the data space address of the byte to be tested is in the single byte immediately following the
opcode byte. The third byte is sign extended to twelve bits and becomes the offset added to the
program counter if the condition is true. The single three-byte instruction allows the program to
branch based on the condition of any bit in data space memory. The span of branching is from
-125 to + 130 from the opcode address. The state of the tested bit is also transferred to the carry
flag.
6.1.2.8 REGISTER-INDIRECT. In the register-indirect addressing mode, the operand is at the address (in data space) pointed to by the contents of one of the indirect registers (X or Yl. The particular X or Y register is selected by bit 4 of the opcode. Bit 4 of the opcode is then deGoded into an
address which selects the desired X or Y register ($80 or $81l. A register-indirect instruction is one
byte long.
6.1.2.9 INHERENT. In the inherent addressing mode, all the information necessary to execute the
instruction is contained in the opc0de. These instructions are one byte long.
6.2 INSTRUCTION SET

The MC6804J2 MCU has a set of 42 basic instructions, which when combined with nine addressing
modes produce 242 usable opcodes. They can be divided into five different types: register/memory,
read-modify-write, branch, bit manipulation, and control. The following paragraphs briefly explain
each type. All the instructions within a given type are presented in individual tables.
6.2.1 Register/ Memory Instructions

Most of these instructions use two operands. One operand is the accumulator and the other
operand is obtained from memory using one of the addressing modes. The jump unconditional
(JMP) and jump to subroutine (JSR) instructions have no register operands. Refer to Table 6-1.
6.2.2 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify or test its contents, and write the
modified value back to memory or to the register. There are ten instructions which utilize readmodify-write cycles. All INC and DEC forms along with all bit manipulation instructions use this
method. Refer to Table 6-2.
6.2.3 Branch Instructions

The branch instructions cause a branch from the program when a certain condition is met. Refer to
Table 6-3.
6.2.4 Bit Manipulation Instructions

These instructions are used on any bit in data space memory. One group either sets or clears. The
other group performs the bit test branch operations. Refer .to Table 6-4.

3-163

I

iii
3:

()
CJ)

Table 6-1. Register/Memory Instructions

CO

Addressing Modes
Indirect

Function
Load A from Memory

CfJ
.....

0)
~

Mnem

I

Opcode
XP I YP

LOA I EO

FO

I

Immediate

I I

Direct

I I I

Ea

Load XP from Memory

I LDXI

BO

Load YP from Memory

I LDYI

BO
BC-BF

Fl

I E2

F2

EA

FA

Subtract from A

SUB I E3

F3

EB

FB

Arithmetic Compare
with Memory

CMP I E4

F4

EC

FC

I F5

ED

FD

AND Memory to A

AND

Jump to Subroutine

JSR

Jump Unconditional

JMP

Clear A

CLRA

Clear XP

CLRX

FB

Clear YP

CLRY

FB

Complement A

COMA
MVI

Rotate A Left and Carry

I ROLA

Arithmetic Left Shift of A IASLA

Short-Direct

I I I

I I

#
#
#
#
#
ISpecial
Cycles Opcode Bytes Cycles Opcode Bytes Cycles Notes

F9

STA I El
ADD

Move Immediate Value
to Memory

I I I

AC-AF

Store A in Memory

E5

I

#
#
Cycles Opcode Bytes

Fa

Add to A

I

Extended

Inherent

I I

#
#
#
#
#
Bytes Cycles Opcode Bytes Cycles Opcode Bytes

a (TAR)
9ITAR)

I

FB

I

I

-

-

B4

3

4

-

-

-

-

B5

FA

2

I -

Bol3141BO

1

SPECIAL NOTES
1. In Short-Direct addressing, the LOA mnemonic represents opcode AC, AD, AE, and AF. This is equivalent to RAM locations $80 (AC), $81 (AD), $82 (AE), and $83 (AF)

2. In Short-Direct addressing, the STA mnemonic represents opcode BC, BD, BE, and BF. This is equivalent to RAM locations $80 (BC), $81 (BD), $82 IBE), and $83 (BF).
3. In Extended addressing, the four LSBs of the opcode (Mnemonic JSR and JMP) are formed by the four MSBs of the target address.
4. In Immediate addressing, the LDXI and LOY I are mnemonics which are recognized as follows:
LDXI = MVI $OO,data
LOY I = MVI $81 ,data
Where data is a one-byte hexadecimal number.
5. In both Immediate and Direct addressing, the MVI instruction has the same opcode (801.

o
~
c..
I\)

3:

oen

Q)

o

~

c..
N

Table 6-2. Read-Modify-Write Instructions
Addressing Modes
Direct

Indirect
Opcode
Function

Cf
~

en
(11

Increment Memory Location
Increment A
Increment XP
Increment YP
Decrement Memory Location
Decrement A
Decrement XP
Decrement YP

Mnem
INC
INCA
INCX
INCY
DEC
DECA
DECX
DECY

X
E6

E7

Y
F6

Bytes

Cycles
4

1

Opcode
FE
FE

4

F7

~--.-

FF
FF

#
Bytes
2

2

Short-Direct

#
Cycles
4
4

2
2

- - - -

Opcode
AS-AB

Bytes
1

Cycles
4

AS
A9
8S-B8

4
4

BS
B9

4

Special
Notes
1.3

2.4

4

~

SPECIAL NOTES
1. In Short-Direct addressing. the INC mnemonic represents opcode A8. A9. AA. and AB. These are equivalent to RAM locations $80 (AS). $81 (A9). $S2 (AA).
and $83 (AB)'
2. In Short-Direct addressing. the DEC mnemonic represents opcode B8. B9. BA. and BB. These are equivalent to RAM locations $80 IB8). $81 IB9). $S2ISA),
and $83 ISS),
3. In Indirect addressing. the INC'mnemonic represents opcode E6 or F6. and causes the location pointed to by X (E6 opcode) or Y (F6 opcode) to be incremented.
4. In Indirect addressing. the INC mnemonic represents opcode E7 or F7. and causes the location pointed to by X {E7 opcodel or Y (F7 opcode) to be incremented.

III

MC6804J2

Table 6-3. Branch Instructions
Relative Addressing Mode
Function

Mnem

Branch if Carry Clear
Branch if Higher or Same

#

#

Opcode

Bytes

Cycles

Special
Notes

BCC

4O-5F

1

2

1

(BHS)

40-5F

1

2

1,2

Branch if Carry Set

BCS

6O-7F

1

2

1

(BlO)

6O-7F

1

2

1,3

Branch if Not Equal

BNE

00-1F

1

2

1

Branch if Equal

SEQ

20-3F

1

2

1

Branch if lower

SPECIAL NOTES

I

1. Each mnemonic of the Branch Instructions covers a range of 32 opcodes; e.g., BCC ranges from 40 through 5F. The
actual memory location (target address) to whic" the branch is made is formed by adding the sign extended lower five
bits of the opcode to the contents of the program counter.
2. The BHS instruction (shown in parentheses) is identical to the BCC instruction. The C bit IS clear if the register was higher
or the same as the location in the memory to which it was compared.
3. The BlO instruction (shown in parentheses) is identical to the BCS instruction. The C bit is set if the register was lower
than the location in memory to which it was compared.

Table 6-4. Bit Manipulation Instructions
Addressing Modes
Bit Test and Branch

Bit Set/Clear
Function

Mnem

#

#

Opcode

Bytes

Cycles

Opcode

#

#

Bytes

Cycles

Special
Note

Branch IFF Bit n is set

BRSET n (n=O

.7)

-

-

-

C8+ n

3

5

1

Branch IFF Bit n is clear

BRClR n (n=O

. . . 7)

-

-

-

CO+ n

3

5

1

Set Bit n

BSET n (n=O.

.7)

D8+ n

2

4

-

-

1

Clear Bit n

BClR n (n=O

.. 71

DO+ n

2

4

-

-

-

1

SPECIAL NOTE
The opcode is formed by adding the bit number (0-71 to the basic opcode. For example: to clear bit six uSing the BSET6
instruction the opcode becomes DE (08+61; BClR5 becomes (CO+51; etc

3-166

MC6804J2

6.2.5 Control Instructions
The control instructions control the MCU operations during program execution. Refer to Table 6-5.
6.2.6 Alphabetical Listing
The complete instruction set is given in alphabetical order in Table 6-6. There are certain
mnemonics recognized by the Motorola assembler and converted to other instructions. The fact
that all registers and accumulator are in RAM allows many implied instructions to exist. The implied
instructions recognized by the Motorola assembler are identified in Table 6-6.
6.2.7 Opcode Map Summary
Table 6-7 contains an opcode map for the instructions used on the MCU.
6.3 IMPLIED INSTRUCTIONS
Since the accumulator and all other registers are located in RAM many implied instructions exist.
The assembler-recognized implied instructions are given in Table 6-6. Some examples not recognized by the assembler are shown below.

BCLR,7 $FF
BSET,7 $FF
BRCLR,7 $FF
BRSET,7 $FF
BRCLR,7 $80
BRSET,7 $80
BRCLR,7 $81
BRSET,7 $81

Ensures accumulator is plus
Ensures accumulator is minus
Branch iff accumulator is plus
Branch iff accumulator is minus
Branch iff X is plus (BXPU
Branch iff X is minus (BXMI)
Branch iff Y is plus (BYPU
Branch iff Y is minus (BYMI)

3-167

I

..
3:

o

en
CD

o

~

Co.
N

Table 6-5. Control Instructions
Addressing Modes
Inherent

Short-Direct

Relative

#

#
Mnem

Opcode

Bytes

Cycles

~

Transfer A to X
Transfer A to Y

TAX
TAY

BC

1
1

4
4

C»
00

Transfer X to A

TXA

AC

4

Transfer Y to A

TYA

AD

4

Return from Subroutine
Return from Interrupt

RTS

B3

RTI
NOP

B2

Function
~

No-Qperation

BD

Opcode

Bytes

Cycles

SPECIAL NOTE
. The NOP instruction is equivalent to a branch if equal (BEQ) to the location designated by PC + 1.

2

Opcode

Bytes

Cycles

Special
Notes

3:
0
0)

Table 6-6. Instruction Set

CO
0

Mnemonic

Inherent

Immediate

ADD

X

AND

X

ASLA

Direct

I

Bit/Set
Clear

Bit- TestBranch

Aegister
Indirect

X

Extended

Aelative

X

f\

X

f\

Assembler converts this to "BCC"

BLO

Assembler converts this to "BCS"

BASET
X

BSET

1

1

1

1

Assembler converts this to "SUB $FF"

CLAA

c.c

f\

X

BACLA

(J)

f\

X

BNE

Assembler converts this to "MVI $80,#0"

CLAY

Assembler converts this to "MVI $81,#0"
X

X

1
f\

CLAX

.....t.

I

l

X

I

BHS

I COMA

f\

X

BEQ

ICMP

I

I

X

BCC
BCS

.

I

Assembler converts this to "ADD $FF"

BCLA

(..)

I

Flags

Addressing Modes
Short
Direct

I
I
i

f\

T

f\
f\

I

I DECA

X
I
Assembler converts this to "DEC $FF"

f\

DECX

Assembler converts this to "DEC $80"

f\

DECY

Assembler converts this to "DEC $81"

f\

I DEC

X

INC

Assembler converts this to "INC $FF"

INCX

Assembler converts this to "INC $80"

INCY

Assembler converts this to "INC $81"

I

f\
f\

f\

INCA

JMP

f\

f\
f\
f\

I

X

JSA

X
X

LDA

I

f\

LDXI

Assembler converts this to "MVI $80,DATA"

LDYI

Assembler converts this to "MVI $81,DATA"

MVI
Assembler converts this to "BEQ I PCI

NOP

+

1"

AOLA

f\
f\

ATI

1
I

f\
f\

I

f\

RTS

X

STA
SUB

X

TAX
TAY
TXA
TYA
Flag Symbols Z ~ Zero, C ~ Carry Borrow

X

f\

X

f\

Assembler converts this to "5TA $80"
Assembler converts lhis to "5T A $81"
Assembler converts this to "LDA $80"
Assembler converts this to" LDA $81"
f\ ~ Test and Set If True, Cleared OtherWise, • = Not Affected

..

~

c..
N

MC6804J2

Table 6-7. MC6804J2 Microcomputer Instruction Set Opcode Map
Branch Instructions

~
Low

I

1

2

3

4

5

6

7

0000

0001

0010

0011

0100

0101

0110

0111

2
1

BNE
REL

2

1
2

2
0010

I

0011

BNE

REL

REL

REL

1

REL

B,
'·','011

BNE

e
1100

D
1101

REL

BNE

1

REL

2
1

REL

F

REL

1
2

BNE
REL

1

REL

2

BNE
1

1

1

REL

REL

1

1
2

REL

REL

REL

1

REL

1

REL

1

REL

1

Inherent
Short Direct
Bit Test and Branch
Immediate
Direct
Extended
Relative
Bit Set/Clear
Register Indirect

#

REL

1

2

Bee
REL

REL

REL

Bee

1

REL

2

Bee
Bee
REL

Bee
REL

2

Bee

REL

REL

1

Bes
1

2

Bes

1

REL 1

2

2

Bes

1

REL

REL

Bes
REL

Bes

1

REL

2

1

Bes
REL

1

REL

2

Bes

Bes
REL

1

1

REL

Bes
REL

1

REL

2

Bes
REL

REL

,Bes

2

2

1

REL

Bes

1
2

1

Bee
REL

1
2

Bes

1

2

REL

Bes
REL

Bes
REL

1

1
2

2

1

2

REL

Bes
REL

1

Bee
REL

1
2

1

2

Bee

1

2

Bee

REL

REL

Bes
REL

1

2

Bee
REL

Indicates Instruction Reserved for Future Use
Indicates Illegal Instruction

3-170

1

Bes

2

Bee

1

2

2

Bee

REL

Bes
REL

1

2

2
REL

1
2

Bes
REL

Bee

Bee

REL

2

Bee

1

Abbreviations for Address Modes
INH
SoD
B-T-B
IMM
DIR
EXT
REL
BSe
R-IND

1

Bes
REL

REL

Bes

Bes

2

Bee

1
2

BEQ

REL

1

2
REL

Bee

1
2

2

1
2

REL

Bes
REL

2
REL

Bes

1

Bes

1

Bee
REL

1
2

BEQ

1

2

BEQ

REL

BEQ

REL

REL

2

Bes

2

Bee

REL

2

Bee

1

Bes

Bes
REL

1

2
REL

1

2

BEQ

1

2

BEQ

1
2

BNE
REL

REL

BEQ

REL

1

1
2

2

Bee
REL

1

2

BEQ

1
2

BEQ

1

2

BNE

2

BNE
1

REL

REL

REL

REL

2

Bee

1

2

SEQ

REL

1
2

REL

1
2

BEQ

1

2

BNE

1

2

BNE

REL

REL

REL

BEQ

1

Bes
REL

1
2

Bee

Bee

1

2

BEQ

1

2

BEQ

REL

REL

2

Bee

1

2

BEQ

1

2
REL

1
2

1
2

2
1111

REL

BNE
REL

2
1110

BNE

2

BNE

1

2

2

1

E

REL

REL

BEQ

REL

1

2

BEQ

1

2

1
2

2

2

REL

BNE
REL

1

1

2

2

A

2

REL

BEQ

Bee

1

2

Bes

1
2

Bee
REL

1

2

REL

2

Bee

1

2
REL

1

2

BEQ

1

BNE

BNE
1

REL

1

REL

REL

REL

1

2

BEQ

1

2

BEQ

REL

BEQ

1
2

Bee

1

2

BEQ

1

2
REL

1

2

2

BNE
, 2

1010

REL

BNE
REL

2

1001

1

REL

REL

2

Bee
REL

1
2

BEQ

1

2

BEQ

1

2

2

BNE

9

REL

BNE
REL

1

8
1000

1

REL

BEQ

REL

2

Bee

1

2

BEQ

1
2

BEQ

1
2

2

1

7

REL

BNE

2
0111

1

REL

REL

1
2

BEQ

1
2

2

BNE

6

REL

BNE

BNE

1

1

REL

2

BEQ

1
2

BEQ

1
2

2

2
0110

REL

BNE

BNE

1
2

5
0101

1

REL

1
2

2

1
2

REL

BNE
REL

BNE

4
0100

1

2

BEQ

1
2

2

2

3

REL

BNE
REL

1

1
2

BNE

1
0001

2

2

BNE

0
0000

0

Bes
REL

1

REL

MC6804J2

8

Register/Memory, Control, and
Read/Modify/Write Instructions
A
9
1001

1000

4

JSRn
2

EXT

2

*

MVI

EXT

IMM

3

JSRn

*

JMPn

4

*

EXT

3

JSRn

*

JMPn
EXT

4

RTI

EXT

2

JSRn

*

JMPn
EXT

JSRn
2

2

EXT

2

4

*

JSRn
4

INH

INH

*

3

*

4

4

JSRn
2

2

EXT

2

4

4

4

JSRn

JSRn
4

4

JSRn
2

2

EXT

2

EXT

2

4

4

4

JSRn
2

3

STA
SoD

1

SoD

3

2

2

BRSETO
6-T-6

2

BRSET1
6-T-6

2

STA

ADD

ADD
R-IND

1

SUB

R-IND

CMP

AND

INC

INC

R-IND

1

2

2

BRSET5
6-T-6

2

BRSET6
6-T-6

2

R-IND

1

0111

4

8

LDA
IMM

2

DIR

1000

DIR

1001

DIR

1010

DIR

1011

DIR

1100

DIR

1101

DIR

1110

DIR

1111

4

#
4

4

BSET2
6se

9

STA
2

ADD
2

ADD
IMM

2

A

4

BSET3
6se

SUB

SUB
IMM

2

B

4

BSET4
6se

2

BSET5
6se

2

CMP

CMP
IMM

C

4

4

AND

AND
IMM

4

2

D

4

BSET6
6se

#

INC
2

4
2

0110

7

DEC

R-IND

LDA

BSET1
6se

4

BRSET7
8-T-8

6

R-IND

1

DEC
4

4

BRSET4
6-T-6

0101

4

4

BRSET3
6-T-6

5

R-IND

1
4

4

4
2

0100

4
R-IND

4

BRSET2
6-T-6

4
R-IND

1

AND

2

0011

4
R-IND

1

BSETO
6se

0010

3

R-IND

1

CMP
1

1

2

R-IND

1

SUB
1

BCLR7
6se

0001

4

4

BCLR6
6se

1

R-IND

1

4

4

BCLR5
6se

0000

4
R-IND

4

BCLR4
6se

4

5

4

LDA
1

SoD

1

2

BRCLR7
6-T-6

5

STA
SD

4

EXT

3

4

1

JMPn
EXT

SoD

2

4

5

1

LDA
EXT

3

STA

4

JMPn

4

BRCLR6
6-T-6

5
SoD

4
SoD

1

3

STA
1

LDA
EXT

4

JRSn
2

4
SoD

4

JMPn

SoD

1

LDA
1

3

BCLR3
6se

4

5

DEC
SD

4

EXT

4

JSRn
2

1

JMPn
EXT

SoD

1

4

2

R-IND

1

STA
1

4

4

BRCLR5
6-T-6

5

DEC
SoD

1

INC
EXT

2

3

4

4

JMPn
EXT

2

SoD

BCLR2
6se

Low

0

LDA

R-IND

4

4

BRCLR4
6-T-6

5

1

INC
EXT

2

3

DEC

4

4

SD

4
SoD

1

JMPn
EXT

2

1

INC
EXT

4

4

DEC
SoD

1

JMPn

4

BRCLR3
6-T-6

5

4

INC
EXT

4

JSRn
2

3

JMPn
EXT

*

EXT

2

2

LDA
1

~
I

1111

4

4

BCLR1
6se

4

5

JMPn
EXT

3

*

EXT

2

JSRn
2

3

BCLRO
6se

4

BRCLR2
6T-6

1110

4

4

5

4

4

3

ROLA
1

JMPn
EXT

2

2

5

4

*
EXT

4

JSRn

BRCLR1
6-T-6

5

1

JMPn

3

COMA

EXT

4

4
2

INH

1

JMPn
EXT

2

5

RTS

EXT

2

4

4

INH

1
2

4

2

BRCLRO
6-T-6

5

2

4

2

3

Register / Memory and
Read/ Modify/Write
F
E

1101

4

5

4

4
2

2

1100

5

4

JMPn
EXT

B
1011

1010

4

2

Bit Manipulation
Instructions
D
C

E

4

BSET7
sse

#

F

DEC
2

LEGEND

...--+------------~ Opcode in Hexadecimal
1111
Cycles - - - - - + 4

-------if----.

M nemonie
Bytes-----..

Opcode in Binary

LDA

' - - - - - - - - - - - A d d r e s s Mode

3-171

I

MC6804J2

SECTION 7
ELECTRICAL SPECIFICATIONS
7.1 INTRODUCTION

This section contains the electrical specifications and associated timing for the MC6804J2.
7.2 MAXIMUM RATINGS
Symbol

Value

Unit

VCC

-0.3 to + 7.0

V

Input Voltage

Vin

-0.3 to ( 7.0

Operating Temperature Range IComm.)

TA

o to 70

V
DC

Rating
Supply Voltage

I

Operating Temperature Range lind.)
Storage Temperature Range
Junction Temperature Range
Plastic
Ceramic
Cerdip

TA

-40 to 85

DC

Tstg

- 55 to 150

DC

TJ

150
175
175

DC/W

This device contains circuitry to protect
the inputs against damage due to high
static voltages of electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high impedance circuit. For proper
operation it is recommended that Vin and
V out be constrained to the range
V SS:s IVin or Vout):S V CC- Reliability of
operation is enhanced if unused inputs
except EXT AL are connected to an appropriate logic voltage level le.g., either
VSS or VCC)·

7.3 THERMAL CHARACTERISTICS
Characteristic

Symbol

Value

Unit

liJA

TBO
TBO
TBO

DC/W

Thermal Resistance
Plastic
Ceramic
Cerdip

VCC=52V
Test
Point

Test
Point

MM06150
or Equiv.

TestPoint~

40 pF
ITotal)

Figure 7-1. LSTIL Equivalent
Test Load (Port B)

130

pF ITotal)

Figure 7-2. CMOS Equivalent
Test Load (Ports A and B)

3-172

30 pF
ITotal)

46 kG

10 kG
MM07000
or Equiv.

Figure 7-3. LSTTL Equivalent
Test Load (Port A and TIMER)

MC6804J2

7.4 POWER CONSIDERATIONS

The average chip-junction temperature, T J, in °C can be obtained from:
(1)
TJ=TA+(PO-OJA)
Where:
TA = Ambient Temperature, °C
OJA = Package Thermal Resistance, Junction-to-Ambient, °c/W
PO= PINT+ PPORT
PINT= ICC x VCC, Watts - Chip Internal Power
PPORT = Port Power Dissipation, Watts - User Determined
For most applications PPORT~ PINT and can be neglected. PPORT may become significant if
the device is configured to drive Darlington bases or sink LED loads.
An approximate relationship between Po and T J (if PPORT is neglec.ted) is:
PO=K+(TJ+273°C)
(2)
Solving equations 1 and 2 for K gives:
K=PO-(TA+273°C)+OJA-P 0 2
(3)
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by
measuring Po (at equilibrium) for a known T A- Using this value of K the values of Po and TJ can be
obtained by solving equations (1) and (2) iteratively for any value of T A-

7;5 ELECTRICAL CHARACTERISTICS (VCC= +5.0 Vdc±0.5 Vdc, VSS=O Vdc, TA=O°C to
70°C, unless otherwise noted)
Characteristic

Max

Symbol

Min

Typ

Internal Power Dissipation- No Port Loading

PINT

150

Input High Voltage

VIH

2.0

Input Low Voltage

VIL

-0.3

Input Capacitance

Cin

-

10

-

pF

Input Current (IRQ, RESET)

lin

-

2

20

p.A

-

Unit

-

mW

VCC
0.8

V

V

7.6 SWITCHING CHARACTERISTICS (VCC= +5.0Vdc±0.5Vdc, VSS=GNO, TA=O°C to
70°C, unless otherwise noted)
Characteristic
Oscillator Frequency
Bit Time
Byte Cycle Time
IRQ and TIMER Pulse Width

Symbol
fOSC

Min
4.0

Typ

tbit

0.364

tbyte

4.36

Unit
MHz

-

1.0

p's

-

12.0

p's

tWL,tWH 2xtbyte

-

-

2xtbyte
100

-

-

-

-

RESET Pulse Width

tRWL

RESET Delay Time (External Capacitance= 1.0 p.F)

tRHL

3-173

Max
11.0

-

ms

I

MC6804J2

7.7 PORT DC ELECTRICAL CHARACTERISTICS (Vee= +5.0 Vdc±0.5 Vdc, VSS= GND,
TA =

ooe

to 70 0 e, unless otherwise noted)
Symbol

Characteristic

Min

Typ

Max

Unit

Timer and Port A (Standard)
Output Low Voltage, ILoad=O.4 rnA

VOL

-

-

0.5

V

Output High Voltage, I Load = - 50 p.A
Input High Voltage

VOH

2.3

-

-

V

VIH

2.0

-

V

Input Low Voltage

VIL

-0.3

-

Vee
0.8

Hi-Z State Input eurrent

ITSI

-

4

40

p.A

V

Port A (Open Drain)

I

Output Low Voltage, ILoad=O.4 rnA

VOL

-

-

0.5

V

Input High Voltage

VIH

2.0

VIL

-0.3

Vee
0.8

V

Input Low Voltage

-

Hi-Z State Input eurrent

ITSI

-

4

p.A

4

40
40

-

Open Drain Leakage (Vout= Vee)

ILOD

V
p.A

Port A (CMOS Drive)
Output Low Voltage, ILoad=O.4 mA (Sink)

VOL

-

0.5

V

Output High Voltage, ILoad= -10 p.A

VOH

-

-

V

Output High Voltage, ILoad= -100 p.A

VOH

Vee- 1.C
2.3

-

-

V

Input High Voltage, ILoad= -300 p.A Max

VIH

2.0

-

Input Low Voltage, ILoad= -300 p.A Max
Hi-Z State Input eurrent (Vin=O.4 V to Vee)

VIL

-0.3

-

Vee
0.8

V
V

ITSI

-

-

-300

p.A

VOL
VOL

-

-

0.5

V

Output Low Voltage, ILoad= 10 mA (Sink)

-

-

1.5

V

Output High Voltage, ILoad= -100 p.A

VOH

2.3

-

-

V

Input High Voltage

VIH

2.0

-

V

Input Low Voltage

VIL

-0.3

-

Vee
0.8

Hi-Z State Input eurrent

ITSI

-

8

80

p.A

Output Low Voltage, ILoad= 1.0 mA

VOL

-

-

0.5

V

Output Low Voltage, ILoad= 10 mA (Sink)

VOL

-

1.5

V

Input High Voltage

VIH
VIL

Vee
0.8

V

Input Low Voltage

-

Hi-Z State Input eurrent

ITSI

-

8

80

p.A

8

80

p.A

0.5

V

1.5

V

-

V
V

Port B (Standard)
Output Low Voltage, I Load = 1.0 mA

V

Port B (Open Drain)

Open Drain Leakage (V out = Vee)

ILOD

2.0
-0.3

V

Port B (CMOS Drive)
Output Low Voltage, ILoad= 1.0 mA

VOL

-

Output High Voltage, ILoad= 10 mA (Sink)

VOL

-

Output High Voltage, ILoad= -10 p.A

VOH

Output High Voltage, ILoad= -50p.A

VOH

Vee- 1.C
2.3

-

Input High Voltage, ILoad= - 300 p.A Max

VIH

2.0

-

Vce

Input Low Voltage, ILoad= -300 p.A Max

VIL

-0.3

-

0.8

V

Hi-Z State Input Current (Vin = 0.4 V to Vee)

ITSI

-

-300

p.A

3-174

-

V

MC6804J2

SECTION 8
ORDERING INFORMATION
8.1 INTRODUCTION
The following information is required when ordering a custom M CU. The information may be
transmitted to Motorola in the following media:
EPROM(s), MCM2716 or MCM2532
MOOS, disk file
To initiate a ROM pattern for theMCU, it is necessary to first contact your local field service office,
local sales person, or your local Motorola representative.
8.1.1 EPROMs
An MCM2716 or MCM2532 type EPROM, programmed with the customer program (positive logic
sence for address and data), may be submitted for pattern generation. Since all program and data
space information will fit on one MCM2716 or MCM2532 EPROM, the EPROM must be programmed as follows in order to emulate the MC6804J2 MCU. For an MCM2716, start the data
space ROM at EPROM address $020 and start program space ROM at EPROM address $410 and
continue to memory space $7FF. Memory spaces $7F8 through $7FB are reserved for Motorola selftest vectors. For an MCM2532, the memory map shown in Figure 2-1 can be used. All unused
bytes, including the user's space, must be set to zero. For shipment to Motorola, the EPROMs
should be placed in a conductive IC carrier and packed securely. 00 not use styrofoam.
8.1.2 MOOS Disk File
An MOOS disk, programmed with the customer program (positive logic sense for address and
data), may be submitted for pattern generation. When using the MOOS disk, include the entire
memory image of both data and program space. All unused bytes, including the user's space, must
be set to zero.
8.2 VERIFICATION MEDIA
All original pattern media (EPROMs or floppy disk) are filed for contractual purposes and are not
returned. A computer listing of the ROM code will be generated and returned along with a listing
verification form. The listing should be thoroughly checked and the verification form completed,
signed, and returned to Motorola. The signed verification form constitutes the contractural agreement for creation of the customer mask. If desired, Motorola will program a blank MCM2716,
MCM2532, or MOOS disk (supplied by the customer) from the data file used to create the custom
mask to aid in the verification process.

3-175

II

MC6804J2

8.3 ROM VERIFICATION UNITS (RVUs)

Ten MCUs containing the customer's ROM pattern will be sent for program verification. These units
will have been made using the custom mask but are for the purpose of ROM verification only. For
expediency they are usually unmarked, packaged in ceramic, and tested only at room temperature
and five volts. These RVUs are included in the mask charge and are not production parts. These
RVUs are not backed nor guaranteed by Motorola Quality Assurance.
8.4 FLEXIBLE DISKS

I

The disk media submitted must be single-sided, single density, 8-inch, MDOS compatible floppies.
The customer must clearly label the disk with the ROM pattern file name. The minimum MDOS
system files as well as the absolute binary object file (filename. LO type of file) from the M6804 cross
assembler must be on the disk. An object file made from a memory dump; using the ROLLOUT
command is also admissable. Consider submitting a source listing as well as: filename, . LX
(EXORciser loadable format). This file will of course be kept confidential and is used 1) to speed up
the process in house if any problems arise, and 2) to speed up our customer to factory interface if a
user finds any software errors and needs assistance quickly from the factory representative.
MOOS is Motorola's Disk Operating System available on development systems such as EXORciser,
EXORset, etc.

3-176

MC6804J2

OPTION LIST

Select the options for the MCU from the following list. A manufacturing mask will be generated
from this information. Select one in each section.
Internal Oscillator Input
Crystal
Resistor-Capacitor
Interrupt Trigger
o Edge-Sensitive
o Level- and Edge-Sensitive
Output Drive (Select one Option per Port)
LSTTL
CMOS/LSTTL
Open Drain
Port A
o
0
Port B
o
0

o
o

o
o

Customer Name__________________________________________________________
________________________________________________________________

Addres~s

City._____________________________ State~_______________ Zip------------Phone (
Extension __________________________
Contact Msi M [____________________________________________________
Customer Part Numbe[____________________________________________________
Pattern Media

o
o
oo

MCM2532 EPROM
MCM2716 EPROM
M DOS Disk File
________________________________________
(Note)~

Note: Other Media require prior factory approval.
Signature____________________________________________________________
Title _______________________________________________________________

Figure 8.1 Ordering Form

3-177

I

MC6804J2

SECTION 9
MECHANICAL DATA
This section contains the pin assignment and package dimension diagrams for the MC6804J2
microcomputer.

9.1 PIN ASSIGNMENT
Vss

RESET
PA7
PA6

I

XTAL
MDS
TIMER
PBO

3·178

®

ItIIOTOROLA

Advance Information

I
MC6804P2
8-BIT MICROCOMPUTER

This document contains information on a new product. Specifications and Information herein
are subject to cha'nge without notice

3-179

MC6804P2

TABLE OF CONTENTS
Paragraph
Number

1.1
1.2

I

Title
Section 1
Introduction
General ....................... .
Features ............................... .
Section 2
Functional Pin Description, Memory, CPU, And Registers
Functional Pin Description .............. .

Page
Number

3-185
3-185

2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5

VCC and VSS···················.
IRQ........... ......................
. ................... .
XTAL and EXTAL..........
. ........... .
TIMER ................................. .
RESET .................. .
MOS ...................... .
Input/Output Lines (PAO-PA7, PBO-PB7, PCO-PC3).
Memory.. . . .. . . .. .. . .. .. ... .
. ........... .
Central Processing Unit .................. .
Registers .................... : ...... .
Accumulator (A). . . . . .. . ......... .
Indirect Registers (X, Y) .......... .
Program Counter .................. .
Flags (C, Z) ....................... .
Stack .............. .

3-188
3-188
3-188
3-188
3-188
3-188
3-189
3-1.89
3-189
3-189
3-191
3-191
3-191
3-191
3-192
3-192

3.1
3.2
3.2.1
3.2.2
3.2.3

Section 3
Timer
Introduction ................... .
Timer Registers. . . . . . . . . . . . . . . . . . . . . . . .
. ........... .
Timer Count Register (TCR) ............... .
Timer Status/Control Register (TSCR).
. ............. .
. ..................... .
Timer Prescaler Register.

3-193
3-195
3-195
3-195
3-196

4.1
4.1.1
4.1.2
4.1.3

Section 4
Interrupt, Self-Test, Reset, And Internal Clock Generator
Interrupt. . . . . . . . . . . . . . . .
. ........... .
Edge-Sensitive Option.
. .................................... .
Level-Sensitive Option. . . . . . . . . . . . . . . . . . . . .
. ........... .
Power Up and Timing .......................................... .

3-197
3-197
3-197
3-197

3-180

MC6804P2

TABLE OF CONTENTS

(Continued)
Paragraph
Number

4.2
4.3
4.4

Page
Number

Title

Self-Test ..... .
Reset ..
Internal Clock Generator Options ...

3-199
3-199
3-199

Section 5
Input/ Output Ports

5.1
5.2
5.2.1
5.2.2

I nput/ Output ..
Registers.
Port Data Registers. . ....... .
Port Data Direction Registers ..

3-204
3-206
3-206
3-206

Section 6
Software And Instruction Set

6.1
6.1.1
6.1.2
6.1.2.1
6.1.2.2
6.1.2.3
6.1.2.4
6.1.2.5
6.1.2.6
6.1.2.7
6.1.2.8
6.1.2.9
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.3

Software .....
Bit Manipulation ..
Addressing Modes.
Immediate.
Direct.
Short Direct ..... .
Extended
Relative ..
Bit Set/Clear ..
Bit Test And Branch ..
Register-Indirect.
Inherent.
Instruction Set.
Register/ Memory Instructions ..
Read-Modify-Write Instructions.
B ranch Instructions.
Bit Manipulation Instructions.
Control Instructions ..
Alphabetical Listing.
Opcode Map Summary.
Implied Instructions ...

. ..

3-207
3-207
3-208
3-208
3-208
3-208
3-208
3-208
3-208
3-209
3-209
3-209
3-209
3-209
3-209
3-209
3-209
3-213
3-213
3-213
3-213

Section 7
Electrical Specifications

7.1
7.2
7.3

Introduction.
Maximum Ratings ..
Thermal Characteristics.

3-218
3-218
3-218

3-181

I

MC6804P2

TABLE OF CONTENTS
(Continued)
Paragraph
Number

7.4

7.5
7.6

7.7

Title

Power Considerations ................. .
Electrical Characteristics ... .
Switching Characteristics ... .
Port DC Electrical Characteristics ......... .

Page
Number

3-219
3-219
3-219
3-220

Section 8
Ordering Information

I

8.1
8.1.1

8.1..2
8.2

8.3
8.4

Introduction ..
EPROMs ............ .
MDOS Disk File .................... .
Verification Media .......... .
ROM Verification Units (RVUs) .. .
Flexible Disks ....................... .

3-221
3-221
3-221
3-221
3-222
3-222

Section 9
Mechanical Data

9.1

3-224

Pin Assignment ...

3-182

MC6804P2

LIST OF ILLUSTRATIONS
Figure
Number

Title

Page
Number

1-1

MC6804P2 MCU Block Diagram.

3-187

2-1
2-2

MC6804P2 MCU Address Map.
Programming Model ....

3-190
3-191

3-1

Timer Block Diagram ...

3-194

4-1
4-2
4-3
4-4
4-5
4-6

3-198
3-200
3-201
3-201
3-202

4-7

Reset and Interrupt Processing Flowchart ... .
Self-Test Circuit. ..................... .
Power-Up Reset Delay Circuit .... .
Clock Generator Options ....
Crystal Motional Arm Parameters and Suggested PC Board Layout .....
Typical Frequency Selection for Resistor-Capacitor Oscillator Option
(CL=17 pF)............ ....
. ........ .
Clock Generator Timing Diagram ..

5-1
5-2

Typical 1/0 Port Circuitry ..
Typical Port Connections.

3-204
3-205

6-1

Bit Manipulation Example.

3-207

7-1
7-2
7-3

LSTTL Equivalent Test Load (Port B). . ........ .
CMOS Equivalent Test Load (Ports A, B, C).
LSTTL Equivalent Test Load (Ports A, C, and TIMER), ....

3-218
3-218
3-218

8-1

Ordering Form ..

3-223

3-183

3-202
3-203

I

MC6804P2

LIST OF TABLES
Table
Number

Title

Page
Number

3-1

Prescaler Coding Table ...... .

3-193

6-1
6-2
6-3
6-4
6-5
6-6
6-7

Register I M emory Instructions.
Read-Modify-Write Instructions ......... .
B ranch Instructions ...... .
Bit Manipulation Instructions ...
Control Instructions.
Instruction Set .....
MC6804P2 Microcomputer Instruction Set Opcode Map.

3-210
3-211
3-212
3-212
3-214
3-215
3-216

II

3-184

MC6804P2

SECTION 1
INTRODUCTION
1.1 GENERAL

The MC6804P2 microcomputer unit (MCU) is a member of the M6804 Family of very low-cost
single-chip microcomputers. This 8-bit microcomputer contains a CPU, on-chip CLOCK, ROM,
RAM, 1/0, and TIMER. It is designed for the user who needs an economical microcomputer with
the proven capabilities of the M6800-based instruction set.
1.2 FEATURES

The following are some of the hardware and software features of the MC6804P2 MCU.
HARDWARE FEATURES

• 5-Volt Single Supply
• Pin Compatible with the MC6805P2 and MC68705P3
•
•
•
•
•
•

32 Bytes of RAM
Memory Mapped 1/0
1024 Bytes of Program ROM
64 Bytes of Data ROM
20 Bidirectional 1/0 Lines (Eight Lines with High Current Sink Capability)
On-Chip Clock Generator

•
•
•
•
•
•

Self-Test Mode
Master Reset
Complete Development System Support on EXORciser
Software Programmable 8-Bit Timer Control Register and Timer Prescaler (7 Bits, 2n)
Timer Pin is Programmable as Input or Output
On-Chip Circuit for ROM Verify

SOFTWARE FEATURES

•
•
•
•
•

Similar to M6805 HMOS Family
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instruction

3-185

I

MC6804P2

SOFTWARE FEATURES (Continued)

•
•
•
•
•
•
•
•

Separate Flags for Interrupt and Normal Processing
Versatile Indirect Registers
Conditional Branches
Single Instruction Memory Examine/Change
True LIFO Stack Eliminates Stack Pointer
Nine Powerful Addressing Modes
Any Bit in Data Space Memory May be Tested
Any Bit in Data Space Memory Capable of Being Written to May be Set or Cleared

USER SELECTABLE OPTIONS

I

• 20 Bidirectional I/O Lines with LSTTL, LSTTLICMOS, or Open-Drain Interface
• Crystal or Low-Cost Resistor-Capacitor Oscillator
• Mask Selectable Edge- or Level-Sensitive Interrupt Pin

3-186

MC6804P2

TIMER

PBO
PBl
PB2 Port
PB3
B
PB4 I/O
PB5 Lines
PB6
PBl

Accumulator
A

Port
A
I/O
lines

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PAl

8
Port
A
Reg.

Data
Dir
Reg.

Indirect
Register
INotel

X

Indirect
Register
INotel

y

CPU

Stack
12

4
1024x 8
User Program ROM
288x8
Self-Test ROM

pco

Program
Counter
High PCH
Program
Counter
low PCl

AlU

Port
PC1
C
PC2 I/O
PC3 Lines

NOTE' 8- Bit indirect registers X and Y, although shown as part of the CPU, are actually located in the 32 x 8 RAM at locations $80
and $81.

Figure 1-1. MC6804P2 MCU Block Diagram

3-187

I

MC6804P2

SECTION 2
FUNCTIONAL PIN DESCRIPTION, MEMORY, CPU, AND REGISTERS
This section provides a description of the functional pins, memory spaces, the central processing
unit (CPU), and the various registers and flags.
2.1 FUNCTIONAL PIN DESCRIPTION
2.1.1 VCC and VSS

Power is supplied to the MCU using these two pins. VCC is power and VSS is the ground
connection.

I

2.1.2 IRQ

This pin provides the capability for asynchronously applying an external interrupt to the M CU. Refer
to 4.1 INTERRUPT for additional information.
2.1.3 XTAL and EXTAL

These pins provide connections to the on-chip clock oscillator circuit. A crystal, a resistor and
capacitor, or an external signal, depending on the user selectable manufacturing mask option, can
be connected to these pins to provide a system clock source with various stability/ cost tradeoffs.
Lead lengths and stray capacitance on these two pins should be minimized. Refer to 4.4 INTERNAL
CLOCK GENERATOR OPTIONS for recommendations concerning these inputs.
2.1.4 TIMER

In the input mode, the timer pin is connected to the prescaler input and serves as the timer clock. In
the output mode, the timer pin signals that a time out of the timer has occurred. Refer to SECTION
3 TIMER for additional information.
2.1.5 RESET

The RESET pin is used to restart the processor of the MC6804P2 to the beginning of a program.
This pin, together with the MDS pin, is also used to select the operating mode of the MC6804P2. If
the MDS pin is at zero volts, the normal mode is selected and the program counter is loaded with
the user restart vector. However, if the MDS pin is at + 5 volts, then pins PA6 and PA7 are decoded
to allow selection of the operating mode. Refer to 4.3 RESET for additional information.

3·188

MC6804P2

2.1.6 MDS

The MDS (mode select) pin is used to place the MCU into special operating modes. If MDS is held
at + 5 volts at the exit of the reset state, the decoded state of PA6 and PA7 is latched to determine
the operating mode (single-chip, self-test, or ROM verify). However, if MDS is held at zero volts
at the exit of the reset state, the single-chip operating mode is automatically selected (regardless of
PA6 and PA7 statel.
For those users familiar with the MC6801 microcomputer, mode selection is similar but much less
complex in the MC6804P2. No special external diodes, switches, transistors, etc. are required in the
MC6804P2.
2.1.7 Input/Output Lines (PAO-PA7, PBO-PB7, PCO-PC31

These 20 lines are arranged into two 8-bit ports (A and B) and one 4-bit port (Cl. All lines are programr:nable as either inputs or outputs under software control of the data direction registers. Refer
to SECTION 5 INPUT/OUTPUT PORTS for additional information.
2.2 MEMORY

The MCU operates in three different memory spaces: program space, data space, and stack space.
A representation of these memory spaces is shown in Figure 2-1. The program space (Figure 2-1 a)
contains all of the instructions that are to be executed, as well as the data required for the immediate addressing mode instructions, and the self-test and user vectors. The data space (Figure
2-1b) contains all of the RAM locations, plus I/O locations and some ROM used for storage of
tables and constants. The stack space (Figure 2-1cl contains RAM which is used for stacking
subroutine and interrupt return addresses.
The MCU is capable of addressing 4096 bytes of program space memory with its progLm counter
and 256 bytes of data space memory with its instructions. The data space memory coItains three
bytes for port data registers, three bytes for port data direction registers, one byte for timer
status/control, 64 bytes ROM, 32 bytes RAM (which includes two bytes for X and Y indirect
registers), two bytes for timer prescaler and count registers, and one byte for the accumulator. The
program space section including 288 bytes of self-test ROM, 1016 bytes program ROM, and eight
bytes of vectors for self-test and user programs.
2.3 CENTRAL PROCESSING UNIT

The CPU of the M6804 Family is implemented independently from the I/O or memory configuration.
Consequently, it can be treated as an independent central processor communicating with I/O and
memory via internal addresses, data, and control buses.

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I

MC6804P2

(a) Program Space Memory Map

(b) Data Space Memory Map

$000
Reserved (All Ones)
$ADF
$AEO
Self-Test ROM

Port A Data Register

$00

Port B Data Register

$01

1 11/ 1 11 1 Port C Data Reg.

$02

Not Used

$03

$BFF

Port A Data Oirection Register

$04

$ COO

Port B Data Direction Register

$05

11 1 I 1 1 1J

Program ROM

Port C DDR

$06
$07

Not Used
$FF7

I

$08

Self-Test IRO Vector

$FF8-$FF9

Self- Test Restart Vector

$FFA-$FFB

User IRO Vector

$FFC-$FFD

User Restart Vector

$FFE-$FFF

Timer Status Control Register

$09
$OA

Future Expansion

$1 F
$20
User Data Space ROM

$5F
$60
Future Expansion

Ie) Stack Space Memory Map
Levell

Indirect Register X

Level 2

Indirect Register Y

Level 3

$7F
$80

$81
$82

Level 4
Data Space RAM
$9F
$AO
Future Expansion

Prescaler Register

$FC
$FD

Timer Count Register

$FE

Accumulator

$FF

Figure 2-1. MC6804P2 MCU Address Map

3·190

MC6804P2

2.4 REGISTERS

The M6804 Family CPU has four registers and two flags available to the programmer. They are
shown in Figure 2-2 and are explained in the following paragraphs.

0

I

A

These Are
Registers
In Data
Space RAM

I

7

Accumulator

0

r-- - - - - - - - - - - - - - - . . ,

X

.

I

Indirect
Register X

0
Indirect

I Register Y

Y

0

8 7

11
PCH

I

PCL

Normal Flags

)I

Interrupt Flags
)I-

Program
Counter

rn
m

Figure 2-2. Programming Model

2.4.1 Accumulator (A)

The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical
operations, and data manipulations. The accumulator is implemented as the highest RAM location
($FF) in data space and thus implies that several instructions exist which are not explicitly implemented. Refer to 6.3 IMPLIED INSTRUCTIONS for additional information.
2.4.2 Indirect Registers (X, Y)

These two indirect registers are used to maintain pointers to other memory locations in data space.
They are used in the register-indirect addressing mode, and can be accessed with the direct, indirect, short direct, or bit set/ clear addressing modes. These registers are implemented as two of
the 32 RAM locations ($80, $81) and as such generate implied instructions and may be manipulated
in a manner similar to any RAM memory location in data space. Refer to 6.3 IMPLIED INSTRUCTIONS for additional information.
2.4.3 Program Counter (PC)

The program counter is a 12-bit register that contains the address of the next ROM word to be used
(may be opcode, operand, or address of operand), The 12-bit program counter is contained in PCl
(low byte) and PCH (high nibble!.

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I

MC6804P2

2.4.4 Flags (e, Z)

The carry (C) bit is set on a carry or a borrow out of the ALU. It is cleared if the result of an
arithmetic operation does not result in a carry or a borrow. The (C) bit is also set to the value of the
bit tested in a bit test instruction, and participates in the rotate left instruction.
The zero (Z) bit is set if the result of the last arithmetic or logical operation was equal to zero, otherwise it is cleared.

I

There are two sets of these flags, one set is for interrupt processing, the other for all other routines.
When an interrupt occurs, a context switch is made from the program flags to the interrupt flags
(interrupt mode). An RTI forces the context switch back to the program flags (program mode).
While in either mode, only the flags for that mode are available. Further, the interrupt flags will not
be cleared upon entering the interrupt mode. Instead, the flags will be as they were at the exit of the
last interrupt mode. Both sets of flags are cleared by reset.
2.4.5 Stack

There is a true LIFO stack incorporated in the MC6804P2 which eliminates the need for a stack
pointer. Stack space is implemented in separate RAM (12-bits wide) shown in Figure 2-1c.
Whenever a subroutine call (or interrupt) occurs, the contents of the PC are shifted into the top
register of the stack. At the same time (same cycle), the top register is shifted to the next level
deeper. This happens to all registers with the bottom register falling out the bottom of the stack.
Whenever a subroutine or interrupt return occurs, the top register is shifted into the PC and all
lower registers are shifted up one level higher. The stack RAM is four levels deep. If the stack is
pulled more than four times without any pushes, the address that was stored in the bottom level will
be shifted into the PC.

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MC6804P2

SECTION 3
TIMER
3.1 INTRODUCTION

A block diagram of the MC6804P2 timer circuitry is shown in Figure 3-1. The timer logic in the MCU
is comprised of a simple 8-bit counter (timer count register, TCR) with a 7-bit prescaler, and a timer
status/ control register (TSCR). The timer count register, which may be loaded under program control, is decremented towards zero by a clock input (prescaler outputl. The prescaler is used to extend the maximum interval of the overall timer. The prescaler tap is selected by bits 0-2 (PSO-PS2)
of the timer status/ control register. Bits PSO-PS2 control the actual division of the prescaler within
the range of divide-by-1 (20) to divide-by-128 (27) . The timer count register (TCR) and prescaler are
decremented on rising clock edges. The coding of the TCSR PSO-PS2 bits produce a division in the
prescaler as shown in Table 3-1.

Table 3-1. Prescaler Coding Table
PS2

PS1

PSO

Divide By

PS2

PS1

PSO

Divide By

0
0
0
0

0
0

0

0

16
32

0

1
1
1
1

0
0

1
1

1
2
4
8

1
1

0

64

1

128

1
1

1

The TIMER pin may be programmed as either an input or an output depending on the status of
TOUT (TSCR bit 5). Refer to Figure 3-1. In the input mode, TOUT is a logic zero and the TIMER pin
is connected directly to the prescaler input. Therefore, the timer prescaler is clocked by the signal
applied from the TIMER pin. The prescaler then divides its clock input by a value determined by the
coding of the TSCR bits PSO-PS2 as shown in Table 3-1. The divided prescaler output then clocks
the 8-bit timer count register (TCRl. When the TCR is decremented to zero, it sets the TMZ bit in
the timer status/control register (TSCRl. The TMZ bit can be tested under program control to perform a timer function whenever it goes high. The frequency of the external clock applied to the
TIMER pin must be less than tbyte (fosc/48l.
In the output mode, TOUT is a logic one and the TIMER pin is connected to the DOUT latch.
Therefore, the timer prescaler is clocked by the internal sync pulse (divide-by-48 of the internal
oscillator). Operation is similar to that described above for the input mode. However, in the output
mode, the low-to-high TMZ bit transition is used to latch the DOUT bit of the TSCR and provide it
as output for the TIMER pin.
NOTE
TMZ is normally set to logic one when the timer times out (TCR decrements to $00);
however, it may be set by a write of $00 to the TCR or by a write to bit 7 of the TSCR.

3-193

I

•

!:

oen
CO

o,c:.
""D

N

Microcomputer Internal Bus
Sync

Prescaler

TIMER
Pin

~_ _ _ _-II

Initialize

bO
Select
1-01-8

Timer Count Register
(TCR)

Timer Status/Control
Register (TSCR)
TMZ

~
~

<0
.,J:I..

TIMER Pin Status

TOUT
0
1

Prescaler
Clock

TIMER
Pin

TIMER Pin
Sync

Input Mode
Output Mode

Figure 3-1. Timer Block Diagram

MC6804P2

During reset, the timer count register and prescaler are set to $FF, while the timer status/ control
register is cleared to $00 and the DOUT LATCH (TIM ER pin is in the high-impedance input mode) is
forced to a logic high. The prescaler and timer count register are implemented in data space RAM
locations ($FD, $FE); therefore, they are both readable and writeable. A write to either will
predominate over the TCR decremenHo-$OO function; i.e., if a write and a TCR decrement-to-$OO
occur simultaneously, the write will take precedence, and the TMZ bit is not set until the next timer
time out.

3.2 TIMER REGISTERS
3.2.1 Timer Count Register (TCR)

I

IMSB
TCR Address = $FE

The timer count register indicates the state of the internal 8-bit counter.
3.2.2 Timer Status/ Control Register (TSCR)
6

TMZ

5

INot Used I TOUT

4

I DOUT

PSI

PS2

PSl

pso

TSCR Address= $09

b7,TMZ

Low-to-high transition indicates the timer count register has decremented to zero
since the timer status/control register was last read. Cleared by a read of TSCR
register if TMZ was read as a logic one.

b6

Not used.

b5, TOUT

When low, this bit selects the input mode for the timer. When high, the output
mode is selected.

b4, DOUT

Data sent to the timer output pin when TMZ is set high (output mode only).

b3, PSI

Used to initialize the prescaler and inhibit its counting while PSI = O. The initialized
value is set to $FF. The timer count register will also be inhibited kontents unchanged), When PSI = 1 the prescaler begins to count downward.

bO, b1, b2
PSO-PS1

These bits are used to select the prescaler divide-by ratio; therefore, effecting
the clock input frequency to the timer count register.

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MC6804P2

3.2.3 Timer Prescaler Register

o
\MSB

LSB\
TPR Address= $FD

The timer prescaler register indicates the state of the internal 7-bit prescaler. This 7-bit prescaler
divide ratio is normally determined by bits PSO-PS2 of the timer status/ control register (see Table
3-1) .

I

3·196

MC6804P2

SECTION 4
INTERRUPT, SELF-TEST, RESET, AND INTERNAL CLOCK GENERATOR
4.1 INTERRUPT

The MC6S04P2 can be interrupted by applying a logic low signal to the IRQ pin; however, a mask
option selected at the time of manufacture determines whether the negative-going edge or the
actual low level is sensed to indicate an interrupt.
4.1.1 Edge-Sensitive Option

When the IRQ pin is pulled low, the internal interrupt request latch is set. Prior to each instruction
fetch, the interrupt request latch is tested and, if its output is low, an interrupt sequence is initiated
at the end of the current instruction (provided the interrupt mask is cleared). Figure 4-1 contains a
flowchart which illustrates both the reset and interrupt sequence. The interrupt sequence consists
of one cycle during which: the interrupt request latch is cleared, the interrupt mode flags are
selected, the PC is saved on the stack, the interrupt mask is set, and the IRQ vector (single chip
mode= $FFC/$FFD, self-test mode= $FFS/$FF9) is loaded into the PC. Internal processing of the
interrupt continues until an RTI (return from interrupt) instruction is processed. During the RTI instruction, the interrupt mask is cleared and the program mode flags are selected.The next instruction of the program is then fetched and executed. Once the interrupt was initially detected and the
interrupt sequence started, the interrupt request latch is cleared so that the next (second) interrupt
may be detected even while the previous (first) one is being serviced. However, even though the
second interrupt sets the interrupt request latch during processing of the first interrupt, the second
interrupt sequence will not be initiated until completion of the interrupt service routine for the first
interrupt. Completion of an interrupt service routine is always accomplished using an RTI instruction to return to the main program. The interrupt mask (which is not directly available to the programmer) is cleared during the last cycle of the RTI instruction.
4.1.2 Level-Sensitive Option

The actual operation of the level-sensitive and edge-sensitive options are similar except that the
level-sensitive option does not have an interrupt request latch. With no interrupt request latch, the
logic level of the IRQ pin is checked for detection of the interrupt. Also, in the interrupt sequence,
there is no need to clear the interrupt request latch. These differences are illustrated in the flowchart
of Figure 4-1.
4.1.3 Power Up and Timing

During the power-up sequence the interrupt mask is set to preclude any false or "ghost" interrupts
from occurring. To clear the interrupt mask, the programmer should write a J S R (instead of a J M P)
instruction to an initialization routine as the first instruction in a program. The initialization routine

3·197

I

MC6804P2

Load Program
Counter from
Reset Vector
O-OORs
1 -Interrupt Mask
0-1 nterrupt Request
Latch (Edge
Sensitive Option)
$FF-TCR
$OO-TSCR
$FF - Prescaler

Load PC
From IRQ
Vector
($FFC/$FFO)

Select
Program
Mode
Flags

I

Stack
Program
Counter
(PC)

Put $FFE
on
Address
Bus

Select
Interrupt
Mode
Flags

y

Pin
Low

N

Clear
Interrupt
Request
Latch

Check
Interrupt
Request
Latch

N

Figure 4-1. Reset and Interrupt Processing Flowchart

3-198

MC6804P2

should end with an RTI (instead of RTS)' Maximum interrupt response time is six machine (tbyte)
cycles (see 4.4 INTERNAL CLOCK GENERATOR OPTIONS), This includes five machine cycles for
the longest instruction, plus one machine cycle for stacking the PC and switching flags. Minimum
response time is one machine cycle for stacking PC and switching flags (see 2.4.4 Flags (C, Z)).
4.2 SELF-TEST
The MC6804P2 MCU has a unique internal ROM-based off-line self-test capability using signature
analysis techniques. A test program stored in the on-chip ROM is initiated by configuring pins PA6
and PA7 during reset. The test results are sampled on a cycle-by-cycle basis by a 16-bit on-chip
signature analysis register configured as a linear feedback shift register (LFS R) using the standard
CCITT CRC16 polynomial. A schematic diagram of the self-test connections is shown in Figure
4-2. To perform a test of the MCU, connect it as shown in Figure 4-2a and monitor the LEDs for a
00100 ($04) pattern.
A special ROM self-test utilizing the signature analysis circuitry is also included. To initiate a test of
the ROM, connect the circuit as shown in Figure 4-2b. This mode also uses the on-chip signature
analysis register to verify the contents of the custom ROM by monitoring an internal bus. The
"Good" LED indicates that all ROM words have been read and that the result was the correct
signature.
The on-chip self-test and the ROM test are the basis of Motorola's production testing for the
MC6804P2. These tests have been fault graded using statistical methods (refer to "The M6804
Built-In Self-Test", Proceedings of 1983 International Test Conference, pp. 295-300, Oct. 1983) and
have been found to provide high fault coverage using automatic test equipment (ATE) or the circuit
of Figure 4-2.
4.3 RESET

The MCU can be reset in two ways: by initial power up (see Figure 4-1) and by the external reset input (RESET), During power up, a delay of tRHL is needed before allowing the RESET input to go
high. This time delay allows the internal clock generator to stabilize. Connecting a capacitor and
resistor to the RESET input, as shown in Figure 4-3, typically provides sufficient delay.
4.4 INTERNAL CLOCK GENERATOR OPTIONS

The internal clock generator circuit is designed to require a minimum of external components. A
crystal, a resistor-capacitor, or an external signal may be used to generate a system clock with
various stability/ cost tradeoffs. A manufacturing mask option is required to select either the crystal
oscillator or the RC oscillator circuit. The different clock generator option connection methods are
shown in Figure 4-4, crystal specifications and suggested PC board layouts are given in Figure 4-5,
resistor-capacitor selection graph is given in Figure 4-6, and a timing diagram is illustrated in Figure
4-7. The crystal oscillator startup time is a function of many variables: crystal parameters (especially
RS), oscillator load capacitance (CU, IC parameters, ambient temperature, and supply voltage. To
ensure rapid oscillator startup, neither the crystal characteristics nor the load capacitance should
exceed recommendations.
The oscillator output frequency is internally divided by four to produce the internal 4>1 and 4>2
clocks. The 4>1 clock is divided by twelve to produce a machine byte (cycle) clock. A byte cycle is
the smallest unit needed to execute any operation (i.e., increment the program counter)' An instruction may need two, four, or five byte cycles to execute.

3-199

I

MC6804P2

SN74LS125A

3

+5V

+5V
8
'--_ _ _-=2"'"1

. . . - - _......_ _""'5

REET

330

XI AL
330

I

PB7
PB6
PB5
PB4
PB3 ~~I----4
PB2 ........--4--+..
PB 1 r..:.::.~I----+-+-.
PBO ,"",",--4--+-+-~
IRQ

330

330

330

*Used with crystal option only.

(a) Functional Test

+5V

MC6804P2

5 XTAL

~
+5V

0*
4 EXTAL

J

6 MDS
~ TIMER
9 PCO

10

~~i

11 PC3

4.7 k

PA7 27
PA6 26
PA5 25
PA4 24
PA3 23
PA2 22
PAl 21
PAO 20

PB7
PB6
PB5
PB4
PB3
PB2
13
PBl
12
PBO'

SN74LS74

*Used with crystal option only.

(b) Simple ROM Verify Test

Figure 4-2. Self-Test Circuit

3-200

MC6804P2

+5V
4.7k

10JLF

I
Part Of
MC6804P2
MCU

Figure 4-3. Power-Up Reset Delay Circuit

I
-L-:L
-

CL2

o

XTAL

4

EXTAL

MC6804P2
MCU
(Crystal Mask
Option)

+5V

NC
External
Clock
Input

EXTAL

4 EXTAL
XTAL

MC6804P2
MCU

MC6804P2
MCU
(Crystal Mask
Option)

XTAL
(Resistor-Capacitor Mask
Option)

External Clock

External Resistor-Capacitor

Figure 4-4. Clock Generator Options

3-201

MC6804P2

(a)

Crystal Parameters

EXTAL 4

C1

~~
. ~E----J..

XTAL5

Crystal Parameters
AT - Cut Parallel Resonance Crystal
CO= 7 pF Maximum
Freq = 11 MHz
RS = 50 Ohms Maximum
Piezoelectric ceramic resonators which
have the equivalent specifications may be
used instead of crystal oscillators. Follow
ceramic resonator manufacturer's suggestions for CO, C1, and RS values

(b)

(c)

I
NOTE: Keep crystal leads and circuit
connections as short as possible

Figure 4-5. Crystal Motional Arm Parameters and Suggested PC Board Layout

N

12.0

~ 11.0
>'-'

10.0

~a:

8.0

~

0

~

;

~
~

co:

~

x

~

co:

9.0
7.0
6.0
5.0

4.0
3.0
2.0
1.0
10

12

14

16

18

RESISTANCE (RU IN kG

Figure 4-6. Typical Frequency Selection For Resistor-Capacitor
Oscillator Option (CL = 17 pF)

3-202

MC6804P2

(a) Oscillator - <1>1-<1>2 Timing

OSC

(b) <1>1 - Sync Timing

<1>1

SYNC

--..Jr-JIi-....-_ _ _ _ _ _ _ _----',I IL
Figure 4-7. Clock Generator Timing Diagram

3-203

II

MC6804P2

SECTION 5
INPUT/OUTPUT PORTS
5.1 INPUT/OUTPUT

I

There are 20 input/output pins. All pins (port A, S, and C) are programmable as either inputs or outputs under software control of the corresponding data direction register (DDRl. The port 1/0 programming is accomplished by writing the corresponding bit in the port DDR to a logic one for output or a logic zero for input. On reset, all the DDRs are initialized to a logic zero state to put the
ports in the input mode. The port output registers are not initialized on reset but should be initialized
before changing the DDR bits to avoid undefined levels. When programmed as outputs, the latched
output data is readable as input data, regardless of the logic levels at the output pin due to output
loading; see Figure 5-1. All inputloutput pins are LSTTL compatible as both inputs and outputs. In
addition, all three ports may have one of two mask options: 1) internal pullup resistor for CMOS
output compatibility, or 2) open drain output. The address map in Figure 2-1 gives the address of
data registers and DDRs. The register configuration is discussed under the registers paragraph
below and Figure 5-2 provides some examples of port connections.

Data
Direction Register t -......- - - - - - - - . - - - - - - ,
Bit

Latched
Output
Data
Bit

Data
Direction
Register
Bit
1
1

0

Output
Data
Bit

Output
State

Input
To
MCU

0

0

0

1
X

1
Hi-Z

1
Pin

Figure 5-1. Typical I/O Port Circuitry

3-204

s:

oen

Q)

o

MC14069

SN74LS04
(Typical!

19

PB7

PA6

18

PB6

PC3

17

PB5

PC2

16

PB4

PCl

15

PB3

~PA5
24
PA4
23
22

~

PA7

PA3
PA2

SN74LS04
or
MC14069
(Typical)

"tJ

I\)

PCO

PB2

(Typical!

PAl

PB1

CMOS and LSTTL. Driving Port C Directly

PAO

PBO

LSTTL Driving Port A Directly

CMOS or LSTTL Driving Port B Directly

(a) Input Mode
(.,.)

N
o

(J1

+v
PA7

PB7

19

PB6

18

PB5

17

22

PB4
PB3

16
15

PAl

21

PAO

20

PB2
PBl

14
13

PBO

12

PA6

26

PA5

25

PA4

24

PA3

23

PA2

~

(1 LSTTL Load!

Port A, bit 7 programmed as output, driving
CMOS loads and bit 4 driving one LSTTL
load directly (using CMOS output option!.

«

~

(CMOS Loads!

+V

t
~.....,..""

",""""

10
PC3~

~

PC2

PCl
PCO

9.
R
_
_

_

CMOS
Inverter
MC14049iMC14069
(TYPical)

-..Port C open drain option, with bits 0-3 programmed as output, driving CMOS load via
wired-ORed configuration.

Port B, bit 0, and bit 1 programmed as output,
driving LEDs directly.

(b) Output Mode

Figure 5-2. Typical Port Connections

•

MC6804P2

The latched output data bit (see Figure 5-1) may always be written. Therefore, any write to a port
writes to all of its data bits even though the port DDR is set to input. This may be used to initialize
the data registers and avoid undefined outputs; however, care must be exercised when using readmodify-write instructions since the data read corresponds to the pin level if the DDR is an input (0)
and corresponds to the latched output data when the DDR is an output (1). The 20 bidirectional
lines may be configured by port to be LSTTL (standard configuration), LSTTLICMOS (mask option), or open drain (mask option). Port B outputs are LED compatible.
NOTE
The mask option only allows changes by port. For example, if the customer wishes PA7
to be open drain, then PAO-PA7 must all be open drain.
5.2 REGISTERS

I

The registers described below are implemented as RAM locations and thus may be read or written.
5.2.1 Port Data Register
LSB/
Port A Address= $00
Port B Address= $01
Port C Address= $02 (Bits 0-3)

The source of data read from the port data register will be the port I/O pin or previously latched output data depending upon the contents of the corresponding data direction register (DDR). The
destination of data written to the port data register will be an output data latch. If the corresponding
data direction register (DDR) for the port I/O pin is programmed as an output, the data will then appear on the port pin.
5.2.2 Port Data Direction Register
/MSB
Port A Add ress = $04
Port B Address = $05
Port C Address = $06 (Bits 0-3)

The port DDRs configure the port pins as either inputs or outputs. Each port pin can be programmed individually to act as an input or an output. A zero in the pins corresponding bit position
will program that pin as an input while a one in the pins corresponding bit position will program that
pin as an output.

3-206

MC6804P2

SECTION 6
SOFTWARE AND INSTRUCTION SET
6.1 SOFTWARE
6.1.1 Bit Manipulation

The MC6804P2 MCU has the ability to set or clear any register or single random access memory
(RAM) writable bit with a single instruction (BSET, BClR)' Any bit in data space, including ROM,
can- be tested, using the BRSET and BRClR instructions, and the program may branch as a result
of its state_ The carry bit is set to the value of the bit referenced by BRSET or BRCLR. A rotate instruction may then be used to accumulate serial input data in a RAM location or register. -The
capability to work with any bit in RAM, ROM, or I/O allows the user to have individual flags in RAM
or to handle I/O bits as control lines_
The coding example in Figure 6-1 illustrates the usefulness of the bit manipulation and test instructions_ Assume that the MCU is to communicate with an external serial device. The external device
has a data ready signal, a data output line, and a clock line (to clock data one bit at a time, MS B
first, out of the device). The MCU waits until the data is ready, clocks the external device, picks up
the data in the carry flag (C bit), clears the clock line, and finally accumulates the data bit in the
accumulator.

SELF

MCU
Ready
Serial
Device

_Clock
Data ..

BRSET

2,PORTA,SELF

BSET
BRCLR
BCLR
ROLA

I, PORTA
O,PORTA,CONT
I,PORTA

r-2p
0

1 R
T

OA

CONT

-

Figure 6-1. Bit Manipulation Example

3-207

I

MC6804P2

6.1.2 Addressing Modes
The MC6804P2 MCU has nine addressing modes which are explained briefly in the following
paragraphs. The MC6804P2 deals with objects in three different address spaces: program space,
data space, and stack space. Program space contains the instructions which are to be executed,
plus the data for immediate mode instructions. Data space contains all of the RAM locations, X
and Y registers, accumulator, timer, I/O locations, and some ROM (for storage of tables and constants). Stack space contains RAM for use in stacking the return addresses for subroutines and
interrupts.
The term" Effective Address" (EA) is used in describing the address modes. EA is defined as the address from which the argument for an instruction is fetched or stored.

I

6.1.2.1 IMMEDIATE. In the immediate addressing mode, the operand is located in program ROM
and is contained in a byte following the opcode. The immediate addressing mode is used to access
constants which do not change during program execution (e. g., a constant used to initialize a loop
counter).
6.1.2.2 DIRECT. In the direct addressing mode, the effective address of the argument is contained
in a single byte following the opcode byte. Direct addressing allows the user to directly address the
256 bytes in data space memory with a single two-byte instruction.
6.1.2.3 SHORT DIRECT. The MCU also has four locations in data space RAM ($80, $81, $82, $83)
which may be used in a short-direct addressing mode. In this mode the lower two bits of the opcode
determines the data space RAM location, and the instruction is only one byte. Short direct addressing is a subset of the direct addressing mode. (The X and Y registers are at locations $80 and $81
respectivel y. )
6.1.2.4 EXTENDED. In the extended addressing mode, the effective address is obtained by concatenating the four least significant bits of the opcode with the byte following the opcode (12-bit
address). Instructions using the extended addressing mode (JMP, JSR) are capable of branching
anywhere in program space. An extended addressing mode instruction is two bytes long.
6.1.2.5 RELATIVE. The relative addressing mode is only used in conditional branch instructions. In
relative addressing, the address is formed by adding the sign extended lower five bits of the opcode
(the offset) to the program counter if and only if the condition is true. Otherwise, control proceeds
to the next instruction. The span of. relative addressing is from -15 to + 16 from the opcode address. The programmer need not worry about calculating the correct offset when using the
Motorola assembler since it calculates the proper offset and checks to see if it is within the span of
the branch.
6.1.2.6 BIT SET/CLEAR. In the bit set/ clear addressing mode, the bit to be set or cleared is part of
the opcode, and the byte following the opcode specifies the direct address of the byte in which the
specified bit is to be set or cleared. Thus, any bit in the 256 locations of data space memory, which
can be written to, can be set or cleared.

3-208

MC6804P2

6.1.2.7 BIT TEST AND BRANCH. The bit test and branch addressing mode is a combination of
direct addressing and relative addressing. The bit which is to be tested is included in the opcode,
and the data space address of the byte to be tested is in the single byte immediately following the
opcode byte. The third byte is sign extended to twelve bits and becomes the offset added to the
program counter if the condition is true. The single three-byte instruction allows the program to
branch based on the condition of any bit in data space memory. The span of branching is from
-125 to + 130 from the opcode address. The state of the tested bit is also transferred to the carry
flag.
6.1.2.8 REGISTER-INDIRECT. In the register-indirect addressing mode, the operand is at the address (in data space) pointed to by the contents of one of the indirect registers (X or Yl. The particular X or Y register is selected by bit 4 of the opcode. Bit 4 of the opcode is then decoded into an
address which selects the desired X or Y register ($80 or $81 l. A register-indirect instruction is one
byte1long.
6.1.2.9 INHERENT. In the inherent addressing mode, all the information necessary to execute the
instruction is contained in the opcode. These instructions are one byte long.
6.2 INSTRUCTION SET

The MC6804P2 MCU has a set of 42 basic instructions, which when combined with nine addressing
modes produce 242 usable opcodes. They can be divided into five different types: register! memory,
read-modify-write, branch, bit manipulation, and control. The following paragraphs briefly explain
each type. All the instructions within a given type are presented in individual tables.
6.2.1 Register/Memory Instructions

Most of these instructions use two operands. One operand is the accumulator and the other
operand is obtained from memory using one of the addressing modes. The jump unconditional
(JMP) and jump to subroutine (JSR) instructions have no register operands. Refer to Table 6-1.
6.2.2 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify or test its contents, and write the
modified value back to memory or to the register. There are ten instructions which utilize readmodify-write cycles. All INC and DEC forms along with all bit manipulation instructions use this
method. Refer to Table 6-2.
6.2.3 Branch Instructions

The branch instructions cause a branch from the program when a certain condition is met. Refer to
Table 6-3.
6.2.4 Bit Manipulation Instructions

These instructions are used on any bit in data space memory. One group either sets or clears. The
other group performs the bit test branch operations. Refer to Table 6-4.

3-209

I

iii
3:

(')

..
CJ)

Table 6-1. Register/Memory Instructions

CO

o

Addressing Modes
Indirect

Function
Load A from Memory

Mnem
LOA

Load XP from Memory

f LDXI

Load YP from Memory

1 LDYI

1- XOpcode
I Y
t EO

FO

Immediate

I I I
#

Bytes

Direct

I I I

#

#

#

#

I

I I I
#

Cycles Opcode. Bytes

#

I I I
#

Cycles Opcode Bytes

I\)

Short-Direct

#

Cycles Opcode Bytes

Cycles Opcode Bytes

E8

F8

AC-AF

F9

BC-BF

I I
#

Cycles Opcode Bytes

#

Cycles

ISpecial
Notes

BO
BO

Store A in Memory

STA J El

Fl

Add to A

ADD 1 E2

F2

EA

FA

Subtract from A

SUB 1 E3

F3

EB

FB

Arithmetic Compare
with Memory

CMP 1 E4

F4

EC

FC

F5

ED

FD

I I

AND Memory to A

AND

N

Jump to Subroutine

JSR

o

Jump Unconditional

JMP

Clear A

CLRA

FB

Clear XP

CLRX

FB

Clear YP

CLRY

FB

Complement A

COMA

U)

Inherent

I I

#

"'D

Extended

E5

8 (TAR)

~

Move Immediate Value
to MemQry

MVI

Rotate A Left and Carry

1ROLA

Arithmetic Left Shift of A IASLA

9 (TAR)

I

BO

I

I

3

I

I

4

I

I

-

-

B4

3

4

-

-

-

-

B5

FA

2

-

BO

SPECIAL NOTES
Short-Direct addressing, the LDA mnemonic represents opcode AC, AD, AE, and AF. This is equivalent to RAM locations $80 (AC), $81 (AD), $82 (AE), and $83 (AF)
Short-Direct addressing, the STA mnemonic represents opcode BC, BD, BE, and BF. This is equivalent to RAM locations $80 (Be), $81 (BO), $82 (BE), and $83 (BFI.
Extended addressing, the four LSBs of the opcode (Mnemonic JSR and JMP) are formed by the four MSBs of the target address.
Immediate addressing, the LDXI and LOYI are mnemonics which are recognized as follows
LOXI = MVI $80,data
LOYI = MVI $Sl,data
Where data is a one-byte hexadecimal number.
5. In both Immediate and Direct addressing, the MVI instruction has the same opcode (SOl.

In
'2. In
3. In
4. In

s:

oen
CO

o

~

"tJ

N

Table 6-2. Read-Modify-Write Instructions
Addressing Modes
Direct

Indirect
Opcode
Function
Increment Memory location

w

N

~
~

Increment A
Increment X
Increment Y
Decrement Memory location
Decrement A
Decrement X
Decrement Y

Mnem
INC
INCA
INCX
INCY

X
E6

DEC
DECA
DECX
DECY

E7

Short-Direct

#
Y
F6

Bytes
1

Cycles

4

Opcode
FE
FE

FF

F7

FF

Bytes

Cycles

2

4
4

2

4
4

#
Opcode
AS-AB

Bytes
1

AS
A9
BS-BB
BS
B9

1

4

Special
Notes
1,3

4
4
4

2,4

Cycles

4
4

SPECIAL NOTES
1. In Short-Direct addressing, the INC mnemonic represents opcode AS, A9, AA, and AB. These are equivalent to RAM locations $80 (A8), $81
and $83 (AB)'
2. In Short-Direct addressing, the DEC mnemonic represents opcode B8, B9, BA, and BB These are equivalent to RAM locations $80 (B8), $81
and $83 (BB)
3. In Indirect addressing, the INC mnemonic represents opcode E6 or F6, and causes the location pointed to by X (E6 opcode) or Y (F6 opcode)
4. In Indirect addressing, the INC mnemonic represents opcode E7 or F7, and causes the location pointed to by X (E7 opcodel or Y (F7 opcode)

(A9), $82 (AA),
(B9), $82 (BA),
to be incremented.
to be incremented .

MC6804P2

Table 6-3. Branch Instructions
Relative Addressing Mode
Function

#

#

Mnem

Opcode

Bytes

Cycles

Branch if Carry Clear
Branch if Higher or Same

Special
Notes

BCC

40-5F

1

2

1

(BHS)

40-5F

1

2

1,2

Branch if Carry Set

BCS

60-7F

1

2

1

(BLO)

60-7F

1

2

1,3

Branch if Not Equal

BNE

OO-lF

1

2

1

Branch if Equal

BEQ

20-3F

1

2

1

Branch if Lower

SPECIAL NOTES

I

1. Each mnemonic of the Branch Instructions covers a range of 32 opcodes; e.g., BCC ranges from 40 through 5F. The
actual memory location (target address) to which the branch is made is formed by adding the sign extended lower five
bits of the opcode to the contents of the program counter
2. The BHS instruction (shown in parentheses) is identical to the BCC instruction. The C bit is clear if the register was higher
or the same as the location in the memory to which it was compared.
3. The BLO instruction (shown in parentheses) is identical to the BCS instruction. The C bit is set if the register was lower
than the location in memory to which it was compared.

Table 6-4. Bit Manipulation Instructions
Addressing Modes
Bit Set/Clear
Function

Mnem

Bit Test and Branch

#

#

#

#

Opcode

Bytes

Cycles

Opcode

Bytes

Cycles

Special
Note
1

Branch I FF Bit n is set

BRSET n (n=O ..

7)

-

-

-

C8+ n

3

5

Branch IFF Bit n is clear

BRCLR n (n=O .. .. 7)

-

-

-

CO+n

3

5

1

Set Bit n

BSET n (n=O .

08+ n

2

4

-

-

-

1

Clear Bit n

BCLR n (n=O.

00+ n

2

4

-

-

-

1

.. 7)
7)

SPECIAL NOTE
1. The opcode is formed by adding the bit number (0-7) to the basic opcode. For example: to clear bit six using the BSET6
instruction the opcode becomes OE 1D8 + 6); BCLR5 becomes (CO + 5); etc.

3-212

MC6804P2

6.2.5 Control Instructions
The control instructions control the MCU operations during program execution. Refer to Table 6-5.
6.2.6 Alphabetical Listing
The complete instruction set is given in alphabetical order in Table 6-6. There are certain
mnemonics recognized by the Motorola assembler and converted to other instructions. The fact
that all registers and accumulator are in RAM allows many implied instructions to exist. The implied
instructions recognized by the Motorola assembler are identified in Table 6-6.
6.2.7 Opcode Map Summary
Table 6-7 contains an opcode map for the instructions used on the MCU.
6.3 IMPLIED INSTRUCTIONS
Since the accumulator and all other registers are located in RAM many implied instructions exist.
The assembler-recognized implied instructions are given in Table 6-6. Some examples not recognized by the assembler are shown below.

BCLR,7 $FF
BSET,7 $FF
BRCLR,7 $FF
BRSET,7 $FF
BRCLR,7 $80
BRSET,7 $80
BRCLR,7 $81
BRSET,7 $81

Ensures accumulator is plus
Ensures accumulator is minus
Branch iff accumulator is plus
Branch iff accumulator is minus
Branch iff X is plus (BXPU
Branch iff X is minus (BXMI)
Branch iff Y is plus (BYPU
Branch iff Y is minus (BYMI)

3-213

I

MC6804P2

Table 6-5. Control Instructions
Addressing Modes
Inherent

#

#

Opcode

Bytes

Cycles

Opcode

Relative
#
Bytes

-

-

-

B3

1

2

B2

1

2

-

-

-

-

-

Short-Direct
Function

Mnem

Opcode

#

#

Bytes

Cycles

Transfer A to X

TAX

BC

1

4

Transfer A to Y

TAY

BD

1

4

Transfer X to A

TXA

AC

1

4

Transfer Y to A

TYA

AD

1

4

Return from Subroutine
Return from Interrupt

RTS
RTI

-

N 0-0 peration

NOP

-

-

-

-

-

SPECIAL NOTE

II

. The NOP instruction is equivalent to a branch if equal (B EQ) to the location designated by PC + 1.

3-214

#
Cycles

Special
Notes

-

-

-

-

-

-

-

1

3:

0

en

Table 6-6. Instruction Set

Q)

0
Addressing Modes

I

Bit-Test
Branch

Bit Set
Clear

Immediate

Direct

X

X

X

AND

X

X

X

ASLA

X

BCLR

I

~

I
X
X

1

CLRA

X
Assembler converts this to "SUB $FF"

CLRX

Assembler converts this to "MVI $80,#0"

CLRY

Assembler converts this to "MVI $81,#0"

I

X

X
X
X
I
I
Assembler converts this to "DEC $FF"

DECX

Assembler converts this to "DEC $80"

DECY

Assembler converts this to "DEC $81"

INC

X

INCA

Assembler converts this to ' INC $FF"

INCX
INCY
JMP

Assembler converts this to ' INC $80"

X

.

I
I

II

II

I

II

X

II

1

II
II

X

II
II
II

I
I

II
II

J

II

1

1

I

I

I

I

I

I

I

II

II
II

X

X

II
II
II
II

Assembler converts this to ' INC $81"
X

JSR

X
X

LOA
LDXI

X

X

X

Assembler converts this to ' MVI $80,DATA"

LDYI
X

MVI

T

T

II

Assembler converts this to "MVI $81,DATA"
X
Assembler converts this to' BEQ (PC)

NOP

+

1"

X

II
II

.

X
X
X

STA
SUB

I

X

I DEC
IDECA

ROLA
RTI
RTS

I

C
II

II

X

BRSET
BSET

I COMA

I

I

X

BRCLR

ICMP

Z
II

Assembler converts this to "BCC"
Assembler converts this to "BCS"

BHS
BLO
BNE

N

Relative

1

BCS
BEQ

(,.)

Extended

I

Assembler converts this to "ADD $FF"

BCC

01

Register
Indirect

ADD

Mnemonic

Inherent

Short
Direct

Flags

X

TAX
TAY
TXA
TYA
Flag Symbols: Z=Zero, C= Carry/Borrow,

X

X
Assembler converts this to" ST A $80"
Assembler converts this to "ST A $81"
Assembler converts this to" LDA $80"
Assembler converts this to "LDA $81"
/\= Test and Set if True, Cleared Otherwise,

-=

X

II

X

II

Not Affected

~

"tJ

N

MC6804P2

Table 6-7 .. MC6804P2 Microcomputer

Branch Instructions
Low
~
I

1

2

3

4

5

6

7

()()()()

0001

0010

0011

0100

0101

0110

0111

2

2

BNE

0
()()()()

0

1

2

2

1

0010

I

1

REL

1

REL

2

1

REL

1

REL

e
1100

2

1

BNE

1101

1

REL

1

1

REL

1

REL

1

BNE
REL

1

REL

REL

REL

REL

1

REL

1

1

REL

1

Bee
REL

1

1

REL

1

REL

1

1

REL

BEQ

Bee
REL

1

REL

1

Inherent
Short Direct
Bit Test and Branch
Immediate
Direct
Extended
Relative
Bit Set/Clear
Register Indirect

#

Indicates Instruction Reserved for Future Use
Indicates Illegal Instruction

3-216

REL

1

1

1

REL

2

Bes
REL

1

REL

2

Bes
REL

REL

Bes

2

Abbreviations for Address Modes
INH
S-D
B-T-B
IMM
DIR
EXT
REL
Bse
R-IND

1

Bee
REL

1

2

Bes

2

REL

Bes
REL

2

1

1

2

Bes
REL

REL

Bes
RE

1

Bee

2

1
2

2

2

Bee

REL

1

Bee

2
REL

1

Bes

Bes
REL

2

REL

2

2

1

1

Bes
REL

REL

Bes
REL

2

1

Bee

BEQ

REL

Bee
REL

2

BEQ

1

Bes

2

Bee
REL

2

Bee
REL

2

BEQ

REL '1

2

2

REL

Bes

1

2

Bee

2

BEQ

1

2

BEQ

REL

1

2

BEQ

2

Bee

1
2

Bes
REL

REL

Bes
REL

Bes
REL

1

1

2

1

Bee
REL

2

1

2

BEQ

1

2

1

REL

2

2

REL

Bes

Bes
REL

1

1

2

1

Bee
REL

Bee
REL

1

2

BEQ

1

2

2

BNE

F

REL

BNE

1
2

1

1

REL

Bes
REL

2

2

Bee
REL

1

Bee
REL

1

2

Bes
REL

1

REL

Bes
REL

2

2

2

1

2
REL

1

2

2

BNE
2

1111

REL

BNE

2
1110

1
2

BNE

E

1
2

BNE
REL

2

REL

REL

1

1

Bee

Bee
REL

BEQ

BEQ
REL

1
2

1

1

1

1

2

Bes

2

2

2

BEQ

2

BNE
REL

2

D

REL

2

REL

REL

2
REL

REL

Bes

Bes
REL

1

1

2

1

Bee
REL

REL

2

1

Bee

BEQ

REL

REL

Bes

Bes

2

1

1

Bee
REL

2

BEQ

1

1

1

2

2

2

1

BEQ
REL

REL

Bee
REL

2

1
2

BEQ

REL

REL

Bes
REL

Bes

Bee

2

BEQ
REL

1

Bee
REL

1

1

2

2

2

1

BEQ

1

BEQ
REL

BNE

BNE

B

1

REL

Bes
REL

Bes
REL

Bee

2

2

2

2

2

REL

1

Bee
REL

1

2

BEQ
REL

1

BNE
1

1

BNE
REL

2

1011

1
2

BNE

REL

BEQ

1

1

2

2

2

2

Bes
REL

Bee
REL

Bee
REL

1

2

BEQ

2

BNE
REL

1

A

REL

REL

1

BEQ

1

2

BEQ

1

2

1

BNE
1

9

REL

2

2

1010

1

BNE
REL

2

1001

2

2

REL

1

BNE

BNE

8

REL

BEQ

1

2

2

BEQ

2

Bee
REL

Bee
RE~

1

2

1

2

BEQ

1

2
REL

1

2

1

BNE
2

1000

REL

BNE
REL

2

0111

1

REL

BEQ

2

Bee
REL

1

2

BEQ

1

2

2

BNE

7

REL

BNE
REL

1

6
0110

1

REL

2

BEQ

1

2

BEQ

1

2

2

1

5

REL

BNE

2
0101

1

BNE

4

2

2

BNE

REL

1

BNE

2
0100

REL

2

2
0011

1

BNE

3

2

2

BEQ

1

BNE
REL

2

2

REL

1

BNE

1
0001

2

BNE
REL

Bes
REL

1

REL

MC6804P2

Instruction Set Opcode Map

8

Register/Memory, Control, and
Read/ Modify /Write Instructions
9
A

1000

1001

4

JSRn
2

EXT

2

4

*

MVI

EXT

4

*

JSRn
2

JSRn
2

EXT

2

EXT

2

EXT

2

4

*

4

*

INH

3

INH

3

1

4

JSRn
2

4

*

4

JSRn
2

5

JMPn
EXT

4

2

*
4

JMPn
EXT

2

EXT

2

4

JMPn

4

JSRn
2

4

JMPn
EXT

2

JSRn

JMPn
EXT

2

EXT

2

EXT

2

4

4

JSRn
2

4

JMPn

4

4

JRSn

JMPn
EXT

4

2

2

STA
S-D

1

JMPn
EXT

1

3

8-T-8

LOA

8-T-8

8
DIR

1000

DIR

1001

DIR

1010

DIR

1011

DIR

1100

DIR

1101

DIR

1110

DIR

1111

STA
2

9

4

ADD
2

A

ADD
IMM

2

IMM

2

4

SUB

8se

SUB

B

4

BSET4
2

8se

CMP
2

CMP
IMM

4

BSET5
2

8se

C

4

AND
2

0

AND
IMM

2

4

BSET6
2

#

8se

INC
2

4

3

2

#

BSET3

BRSET7
S-D

1

0111

4
IMM

4

5

STA
S-D

8se

2

BRSET6
S-D

1

4

LOA
EXT

5

4

4

8-T-8

7

R-IND

1

LOA

4

4

3

6

DEC

R-IND

2

BSET2

BRSET5
S-D

1

LOA
EXT

4

JSRn

STA

4

8-T-8

0110

4

4

3

5

4
S-D

1

8-T-8

1

DEC

8se

2

BRSET4
S-D

1

LOA
EXT

4

2

STA

4

JMPn

3

R-IND

INC

4

5

4

S-D

1

8-T-8

BRSET3
S-D

1

LOA
EXT

4

JSRn
2

DEC
S-D

1

3

0101

4

1

BSET1
2
4

5

5

R-IND

4
R-IND

4
8se

1

INC

BSETO
2

BRSET2
S-D

1

INC
EXT

8-T-8

5

4

AND

4

3

DEC
S-D

1

4

8-T-8

BRSET1
S-D

4

INC
EXT

4

2

DEC
1

8se

0100

4
R-IND

1

BCLR7

4
R-IND

1

AND

4

4

3

5

4
SD

1

8se

2

BRSETO
S-D

1

INC
EXT

4

4

DEC
S-D

1

4

4

JSRn
2

5

4

INC
EXT

8-T-8

3

CMP

4

4

0011

4
R-IND

1

BCLR6
2

BRCLR7

*

EXT

4

JSRn
2

8-T-8

3

0010

3

R-IND

1

CMP
4

8se

4

BRCLR6

*

EXT

SUB

R-IND

1

BCLR5
2

2

R-IND

1

SUB
4

8se

0001

4

1

BCLR4
2

4
8-T-8

5

JMPn

8se

1

R-IND

ADD

R-IND

1

BCLR3
2

BRCLR5

STA
1

4

4

4
8-T-8

5

ROLA

EXT

8se

0000

4
R-IND

ADD

BCLR2

0

R-IND

1

STA
1

4

2

BRCLR4

4

*

--

8-T-8

LOA

R-IND

4
8se

4

5

1

JMPn

4

3

COMA

EXT

4

JSRn
2

INH

4

JMPn

8T-8

BRCLR3

1

4

JSRn
2

3

LOA

Low
~
I

1111

4

1

BCLR1
4

5

RTS

EXT

8se

2

BRCLR2
INH

1
2

JMPn
EXT

BCLRO
4

8-T-8

5

RTI

*
EXT

1110

4

2

BRCLR1

2

4

2

8-T-8

3

JMPn
EXT

4

3

*

EXT

4

2

1101

5

JMPn

Register / Memory and
Read/ Modify/Write
E
F

4

BRCLRO
IMM

3

4

JSRn
2

2

1100

5

4

JMPn
EXT

B
1011

1010

4

2

Bit Manipulation
Instructions
C
0

E

4

BSET7
2

8se

#

DEC
2

F

LEGEND

F 1--+-------------:7 Opcode in Hexadecimal
1111
Cycles

-----+ 4

Mnemonic -------1f--~ LOA
Bytes ------c~

Opcode in Binary

' - - - - - - - - - - - Address Mode

3-217

I

MC6804P2

SECTION 7
ELECTRICAL SPECIFICATIONS
7.1 INTRODUCTION
This section contains the electrical specifications and associated timing for the MC6804P2.
7.2 MAXIMUM RATINGS
Rating

I

Symbol

Value

Unit

Supply Voltage

Vee

- 0.3 to + 7.0

V

Input Voltage

Vin

-0.3 to +7.0

Operating Temperature Range IComm )

TA

o to 70

V
DC

Operating Temperature Range lind.)
Storage Temperature Range
Junction Temperature Range
Plastic
Ceramic
Cerdip

TA

-40 to 85

°C

Tstg

- 55 to 150

"C

TJ

150
175
175

DC/W

This device contains circuitry to protect
the inputs against damage due to high
static voltages of electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high Impedance circuit For proper
operation it is recommended that Vm and
V out be constrained to the range
VSS:sIV m or Vout):SVCc. Reliability of
operation is enhanced if unused inputs
except EXT AL are connected to an appropriate logic voltage level le.g., either
VSS or VCC)

7.3 THERMAL CHARACTERISTICS
Characteristic

Symbol

Value

Unit

OJA

70
50
60

DC/W

Thermal Resistance
PlastiC
Ceramic
Cerdip

Test
Point
40 pF
1T0tal)

MMD6150
or Equiv

23 k!J

VCC=52V
4 k!J
MMD7000
or Equiv

Figure 7-1. LSTTL Equivalent
Test Load (Port B)

VCC=52V
Test
Point

MMD6150
or Equiv.

TestPoint~

130 pF ITotal)

Figure 7-2. CMOS Equivalent
Test Load (Ports A, B, C)

3·218

30 pF
1T0tail

46 k!J

10 k!J
MMD7000
or Equiv

Figure 7-3. LSTTL Equivalent
Test Load (Ports A, C,
and TiMER)

MC6804P2

7.4 POWER CONSIDERATIONS

The average chip-junction temperature, T J, in °c can be obtained from:
(1)
Tj=TA+(PD-8jA)
Where:
T A = Ambient Temperature, °c
8JA= Package Thermal Resistance, Junction-to-Ambient, °C/W
PD= PINT+ PPORT
PINT= ICC x VCe, Watts - Chip Internal Power
PPORT= Port Power Dissipation, Watts - User Determined
For most applications PPORT~ PINT and can be neglected. PPORT may become significant if
the device is configured to drive Darlington bases or sink LED loads.
An approximate relationship between PD and T J (if PPORT is neglected) is:
PD=K+(TJ+273°C)
(2)
Solving equations 1 and 2 for K gives:
(3)
K = PD-(T A + 273°C) + 8JA - PD 2
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by
measuring PD (at equilibrium) for a known T A- Using this value of K the values of PD and T j can be
obtained by solving equations (n and (2) iteratively for any value of T A-

7.5 ELECTRICAL CHARACTERISTICS (VCC= +5.0 Vdc±0.5 Vdc, VSS=O Vdc, TA=O°C to
70°C, unless otherwise noted)
Symbol

Characteristic

Min

Internal Power Dissipation ~ No Port Loading

PINT

Input High Voltage

VIH

20

Input Low Voltage

VIL

-0.3

Input Capacitance

Cin

Input Current (IRQ, RESET)

lin

~

~

~

Typ

Max

Unit

150

-

mW

VCC
0.8

V

~

~

10
2

~

20

V
pF
JlA

7.6 SWITCHING CHARACTERISTICS (VCC= + 5.0 Vdc± 0.5 Vdc, VSS = GND, T A = O°C to
70°C, unless otherwise noted)
Characteristic

IOSC

Min
4.0

tblt

0.364

tbyte

4.36

Symbol

Oscillator Frequency
Bit Time
Byte Cycle Time
IRQ and TIMER Pulse Width

tWL,tWH 2xtbyte

RESET Pulse Width

tRWL

RESET Delay Time (External Capacitance= 10 JlF)

tRHL

3-219

2xtbyte
100

Typ
~

~

.-

-

Max
11.0

Unit
MHz

10

Jls

12.0

Jls

~

~

~

~

~

~

ms

I

MC6804P2

7.7 PORT DC ELECTRICAL CHARACTERISTICS (Vee= +5.0 Vdc±0.5 Vdc, VSS=GND,
T A = ooe to 70 0 e, unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

-

-

0.5
-

V

-

Vee

V

-

0.8
40

/LA
V

Ports A and C (Standard)
Output Low Voltage, ILoad=OA mA

VOL

Output High Voltage, ILoad = - 50 /LA

VOH

Input High Voltage

VIH

Input Low Voltage

VIL

Hi-Z State Input Current

Irs I

2.3
2.0
-0.3

V
V

-

4

-

-

0.5

-

Vee

V

-

V

4
4

0.8
40
40

/LA

V

Ports A and C (Open Drain)

I

Output Low Voltage, ILoad=OA mA

VOL

Input High Voltage

VIH

Input Low Voltage

VIL

2.0
-0.3

Hi-Z State Input Current

ITSI

-

Open Drain Leakage IV out = Vee)

ILOD

-

/LA

Ports A and C (CMOS Drive)
Output Low Voltage, ILoad=OA mA ISink)

VOL

-

0.5

Output High Voltage, ILoad= -10 /LA

VOH

Vee- 1.O

-

-

V

Output High Voltage, ILoad= -100 /LA

VOH

-

-

V

Input High Voltage, ILoad= -300 /LA Max

VIH

-

Vee

V

Input Low Voltage, ILoad= -300 /LA Max

VIL

2.3
2.0
-03

-

Hi-Z State Input Current 1Vin=OA V to Vee)

Irsl

-

-

0.8
-300

/LA

Output Low Voltage, ILoad= 1.0 mA

VOL

-

-

VOL

-

-

0.5
1.5

V

Output Low Voltage, ILoad= 10 mA ISink)
Output High Voltage, ILoad= -100 /LA

VOH

-

-

V

Input High Voltage

VIH

-

Vee

V

Input Low Voltage

VIL

-

Hi-Z State Input Current

Irsl

-

8

0.8
80

/LA

Output Low Voltage, ILoad= 1.0 mA

VOL

-

-

VOL

-

-

0.5
1.5

V

Output Low Voltage, ILoad= 10 mA ISink)
Input High Voltage

VIH

-

Vee

V

-

0.8
80
80

/LA

-

V

Port B (Standard)

2.3
2.0
-0.3

V

V

Port B (Open Drain)

2.0
-03

Input Low Voltage

VIL

Hi-Z State Input Current

Irsl

-

ILOD

-

8
8

Output Low Voltage, ILoad = 1.0 mA

VOL

-

-

Output High Voltage, ILoad= 10 mA ISink)

VOL

-

-

Output High Voltage, ILoad= -10 /LA

VOH

Vee- 1.O

Output High Voltage, ILoad= -50 /LA

VOH

Input High Voltage, ILoad= -300 /LA Max

VIH

2.3
2.0

Input Low Voltage, ILoad= -300 /J.A Max

VIL

Hi-Z State Input eurrentlVin=OA V to Vee)

Irsl

Open Drain Leakage IVout=Vee)

V
V
/LA

Port B (CMOS Drive)

3-220

-

0.5
1.5

V
V

-

V

-

V

-

Vee

V

-0.3

-

-

-

0.8
-300

/LA

V

MC6804P2

SECTION 8
ORDERING INFORMATION
8.1 INTRODUCTION

The following information is required when ordering a custom MCU. The information may be
transmitted to Motorola in the following media:
EPROM(s), MCM2716 or MCM2532
MOOS, disk file
To initiate a ROM pattern for the MCU, it is necessary to first contact your local field service office,
local sales person, or your local Motorola representative.
8.1.1 EPROMs

An MCM2716 or MCM2532 type EPROM, programmed with the customer program (positive logic
sense for address and data), may be submitted for pattern generation. Since all program and data
space information will fit on one MCM2716 or MCM2532 EPROM, the EPROM must be programmed as follows in order to emulate the MC6804P2 MCU. For an MCM2716, start the data
space ROM at EPROM address $020 and start program space ROM at EPROM address $400 and
continue tO I memory space $7FF. Memory space $7F8 through $7FB are reserved for Motorola selftest vectors. For an MCM2532, the memory map shown in Figure :2-1 can be used. All unused
bytes, including the user's space, must be set to zero. For shipment to Motorola, the EPROMs
should be placed in a conductive IC carrier and packed securely. 00 not use styrofoam.
8.1.2 MOOS Disk File

An MOOS disk, programmed with the customer program (positive logic sense for address and
data), may be submitted for pattern generation. When using the MOOS disk, include the entire
memory image of both data and program space. All unused bytes, including the user's space, must
be set to zero.
8.2 VERIFICATION MEDIA

All original pattern media (EPROMs or floppy disk) are filed for contractual purposes and are not
returned. A computer listing of the ROM code will be generated and returned along with a listing
verification form. The listing should be thoroughly checked and the verification form completed,
signed, and returned to Motorola. The signed verification form cons;itutes the contractural agreement for creation of the customer mask. If desired, Motorola will program a blank MCM2716,
MCM2532, or MOOS disk (supplied by the customer) from the data file used to create the custom
mask to aid in the verification process.

3-221

I

MC6804P2

8.3 ROM VERIFICATION UNITS (RVUs)

Ten MCUs containing the customer's ROM pattern will be sent for program verification. These units
will have been made using the custom mask but are for the purpose of ROM verification only. For
expediency they are usually unmarked, packaged in ceramic, and tested only at room temperature
and five volts. These RVUs are included in the mask charge and are not production parts. These
RVUs are not backed nor guaranteed by Motorola Quality Assurance.
8.4 FLEXIBLE DISKS

II

The disk media submitted must be single-sided, single density, 8-inch, M DOS compatible floppies.
The customer must clearly label the disk with the ROM pattern file name. The minimum MDOS
system files as well as the absolute binary object file (filename. LO type of file) from the M6805 cross
assembler must be on the disk. An object file made from a memory dump; using the ROLLOUT
command is also admissable. Consider submitting a source listing as well as: filename, . LX
(EXORciser loadable format), This file will of course be kept confidential and is used 1) to speed up
the process in house if any problems arise, and 2) to speed up our customer to factory interface if a
user finds any software errors and needs assistance quickly from the factory representative.
MDOS is Motorola's Disk Operating System available on development systems such as EXORciser,
EXORset, etc.

3-222

MC6804P2

OPTION LIST
Select the options for the MCU from the following list. A manufacturing mask will be generated
from this information. Select one in each section.
Internal Oscillator Input
Crystal
Resistor-Capacitor
Interrupt Trigger
o Edge-Sensitive
o Level- and Edge-Sensitive
Output Drive (Select one Option per Port)
LSTTL
CMOS/LSTTL
Open Drain
Port A
0
Port B
0
o
Port C
0
o
o

o
o

o

o
o

Customer Name__________________________________________________________
Address __________________________________________------________________
City __________________________ State _____________ Zip ________
Phone (
Extension ____________________
Contact Ms/Mr _______________________________________________
Customer Part Number __________________________________________________
Pattern Media
MCM2532 EPROM
MCM2716 EPROM
o MDOS Disk File
(Note), _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

o
o
o

Note: Other Media require prior factory approval.
S ignature _________________________________________________________
Title ________________________________________________________________
Figure 8.1 Ordering Form

I

MC6804P2

SECTION 9
MECHANICAL DATA
This section contains the pin assignment and package dimension diagrams for the MC6804P2
microcomputer.

9.1 PIN ASSIGNMENT

RESET

VSS

II

IRQ

2

VCC

3

PA7
PA6

EXTAL

4

PA5

XTAL

5

PA4

MDS

6

PA3

TIMER

7

PA2

PCO

8

PCl

9

PC2

10

19

PC3

11

18

PB6

PBO

12

17

PB5

PAO
PB7

PBl

13

16

PB4

PB2

14

15

PB3

3-224

®

MC68HC04P2
MC68HC04P3

MOTOROI.A

Product Preview
HCMOS
(HIGH-DENSITY CMOS
SILICON-GATE)

8-BIT HCMOS MICROCOMPUTER UNITS
The MC68HC04P2 and MC68HC04P3 HCMOS microcomputer units
(MCUs) are members of the M68HC04 Family of very low-cost singlechip microcomputers. These 8-bit microcomputers contain a CPU, onchip CLOCK, ROM, RAM, I/O, and TIMER. They are designed for the
user who needs an economical microcomputer with the proven
capabilities of the M6800-based instruction set. The following are some
of the hardware and software highlights of the MC68HC04P2 and
M C68H C04P3 microcomputers.

8-81T HCMOS
MICROCOMPUTERS

I

HARDWARE FEATURES

• Low Power HCMOS
• Power Saving Stop and Wait Modes
• 8-Bit Architecture
• MC68HC04P2 and MC68HC04P3 are Pin Compatible With the
MC6804P2
• RAM: MC68HC04P2 - 32 Bytes
MC68HC04P3 - 128 Bytes

PLASTIC PACKAGE
CASE 710

• Memory Mapped I/O
• User ROM: MC68HC04P2 - 1024 Bytes
MC68HC04P3 - 2048 Bytes

Z SUFFIX
CHIP CARRIER
CASE 761

• 72 Bytes of ROM for Look-Up Tables
• 20 TTL/CMOS Compatible Bidirectional I/O Lines (Eight Lines are
LED Compatible)
•
•
•
•
•

On-Chip Clock Generator
Self-Check Mode
Master Reset
Complete Development System Support on EXORciser
Software Programmable Timer Prescaler'

PIN ASSIGNMENT

• 5 Volt Single Supply
RESET

VSS

SOFTWARE FEATURES

• Similar to M6800 Family
• Byte Efficient Instruction Set
•
•
•
•
•
•
•
•
•

Easy to Program
True Bit Manipulation
Bit Test and Branch Instruction
Versatile Interrupt Handling
Versatile Indirect Registers
Conditional Branches
Single Instruction Memory Examine/Change
Timer Pin is Software Programmable as Clock Input or Timer Input
10 Powerful Addressing Modes

USER SELECTABLE OPTIONS

•
•
•
•

20 Bidirectional I/O Lines with TTL or TTL/CMOS Interface Option
Crystal or Low-Cost Resistor Oscillator Option
Vectored Interrupts: Timer, Software, and External
Mask Selectable Edge- or Level-Sensitive Interrupt Pin

This document contams information on a product under development. Motorola reserves the
right to change or discontinue this product without notice.

3-225

IRQ

27

PA7

VCC

26

PA6

25

PA5

XTAL

24

PA4

MDS

23

PA3

TIMER

22

PA2

PCO

21

PAl

EXTAL

4

20

PAO

10

19

PB7

PC3

11

18

PB6

PBO

12

17

PB5

PBl

13

16

PB4

PB2

14

15

PB3

PCl
PC2

MC68HC04P2, MC68HC04P3

BLOCK DIAGRAM

TIMER

CPU
Control

AlU

*User ROM area: MC68HC04P2=1024x8 - MC68HC04P3=2048x8
* * RAM area: MC68HC04P2= 32 x 8 - MC68HC04P3= 128 x 8

PROGRAMMING MODEL

I Accumulator

A
These are
Registers
~n Data
Space RAM

7

I

f
I

11

0
YP

PCl

Normal Flags

Interrupt Flags

I Indirect
Register Y

0

8

PCH

llndirect
Register X

XP

7

I Program

~

---..rn

3-226

Counter

Data
Dlr
Reg.

Port
B
Reg

PBO
PBl
PB2 Port
PB3
B
PB4 I/O
PB5 Lines
PB6
PB7

Data
Dir
Reg

Port
C
Reg

PCO Port
PCl
C
PC2 I/O
PC3 lines

®

MC680SK2
MC680SK3

MOTOROLA
Product Preview

HMOS
(HIGH DENSITY
N-CHANNEL, SILICON-GATE
DEPLETION LOAD)

8-BIT MICROCOMPUTER UNITS WITH
SERIAL PERIPHERAL INTERFACE AND TWO TIMERS

8--SIT
MICROCOMPUTERS

The MC6805K2/MC6805K3 microcomputer units are members of the
M6805 Family of low-cost single-chip microcomputers. These 8-bit
microcomputers contain a CPU, on-chip clock, ROM, EEPROM, RAM,
I/O, two timers, one programmable prescaler, and a serial peripheral interface. These units are designed for the user who needs an economical
microcomputer with the proven capabilities of the M6800-based instruction set
HARDWARE FEATURES

L SUFFIX

• 32 Bidirectional TTL I/O Lines
Eight CMOS I/O Compatible
Eight LED liO Compatible
Eight Open Drain (Software Control)
• User ROM:

CASE 715

MC6805K2 - 2K Bytes
MC6805K3 - 3.6K Bytes

~
~

• 96 Bytes of User RAM, 16 Bytes on Standby via VSTBY Pin
•

128 Bytes of User EEPROM with Write/Erase Latches

•
•
•
•

Self-Check Mode
Serial Peripheral Interface
Zero-Crossing Detect/ Interrupt
Two Cascadable 8-Bit Timers with 7-Bit Software Programmable
Prescaler, Data Modulus Latch, and Capture Latch

~
"

PSUFFIX

PLASTIC PACKAGE
CASE 711

'

'

'I

I,

' '

SSUFFIX

CERPID PACKAGE
CASE 734

• Auxiliary Counter with "WatChdog" Reset Feature
• 5-Volt Single Supply

PIN ASSIGNMENT

• Two External Interrupts
SOFTWARE FEATURES

• 10 Powerful Addressing Modes
• Byte EffiCient Instruction Set with True Bit Manipulation, Bit Test,
and Branch Instructions
• Single Instruction Memory Examine/Change
• Powerful Indexed Addressing for Tables

VSS

PA7

RESET

PA6

INTl

PA5

VCC

PA4

XTAL

PA3

EXTAl

PA2

VSTBY
Vpp

PAl

• User Callable Self-Check Subroutines

PCO

PB7

• Complete Development System Support on EXORciser, EXORset,
and HDS-200

PCl

PB6

PC2

PB5

PC3

PB4

PC4

PB3

PC5

PB2

PC6

PBl

• Full Set of Conditional Branches
• Memory Usable as Register / Flags

USER SELECTABLE OPTIONS

• Eight Bidirectional I/O Lrnes With TTL or TTL/CMOS Interface
Option
• Crystal or Low-Cost Resistor OSCillator Option

PC7

• Low Voltage Inhibit Option
• Vectored Interrupts: Tlmer/SPI, Software, and External
• Eight Byte Standby RAM Option

This document contains information on a product under development Motorola reserves the
right to change or discontinue this product without notice

3-227

PAO

PBO

TIMERA/PD7

PDO/SPISS

TCON1I1NT2/PD6

PD1/SPICl

TIMERB/PD5

PD2/SPID

TCON2/PD4

PD3/SPID

I

MC6805K2-MC6805K3

FIGURE 1 -

BLOCK DIAGRAM

f'...COl!)q-(I')N"-O

««««««««

Timer A
Control I Data

~~~~~~~~

XTAL
EXTAL

=1

Clock

IIII IIII

~:~

r+

Port A

Modulus
Latch

I

PB4
PB5
PB6
PB7

Timer B
Control I Data

--

co

15

~

co
a:
0
0

~

Program
Counter
Low

Accumulator
Index Register
Condition Code
Register

Timer A
Prescaler

Modulus
Latch

~

Capture
Latch

I

Program
Counter
High

Stack Pointer

PD7ITimer A
PD6/TCON1/1NT2
PD5/Timer B
PD4/TCON2

CPU
RESET

i'Nff
VCC
VSS

PCO
PCl
PC2
PC3
PC4
PC5
PC6
PC7

Control

~

ALU

-----

--

-

--

*
u

0

~

0

0

0
0

~

a:

0

1

u
a:
0

Data
Latch

I

SPI
Data/Clock

-

0

SPI
Control
RAM

Address
Latch

EEPROM
128x8

96 x 8

VSTBY

I-- Vpp

* User ROM
MC6805K2=2K Bytes
MC6805K3=3.6K Bytes
FIGURE 2 -

11

PROGRAMMING MODEL

A

Accumulator

x

Index Register

87
PCH

11
10101010\0\

PD3/SPID
PD2/SPID
PDl/SPICL
PDO/SPISS

I

Self
Check
ROM
24Bx8

User
ROM

I

I

DORA

PBO
PBl
PB2
PB3

H

Capture
Latch

Program Counter

PCL

o

54
SP

Stack Pointer

Condition Code Register
Carry/Borrow
Zero
Negative
Interrupt Mask
Half Carry

MC6805K2·MC6805K3

SIGNAL DESCRIPTION
The input and output signals for the MC6805K2 and
MC6805K3 microcomputer units (MCUs) are described in the
following paragraphs.
Vcc, VSS, AND VSTBY
Power is supplied to the MCUs using these pins. VCC provides the 5.0 volt ± 5% power supply connection, V S S is the
ground connection, and VSTBY is the standby RAM power
connection.
INT1
This pin provides the capability for asynchronously applying an external interrupt to the MCU. Zero-crossing detection capability is provided on this pin.
XTAL AND EXTAL
These pins provide control input for the on-chip clock
oscillator circuit. A crystal or a capacitor-resistor network,
depending on the user selectable manufacturing mask option, can be connected to these pins to provide a system
clock source with various stabilitylcost tradeoffs.
Vpp
This pin is used to supply programming voltage (21 volts)
to the EEPROM in the program mode. It should be connected to VCC during normal operation.
TIMER A/PD7 - TIMER B/PD5
These pins allow an external input to be used to decrement the internal timers.
RESET
This pin allows resetting of the MCU by an external
source.

3-229

INPUT /OUTPUT PORTS
(PAO-PA7, PBO-PB7, PCO-PC7, PDO-PD7)
Ports A, B, and C are programmable as either inputs or
outputs under software control of the data direction
registers. All ports are CMOS and TTL input compatible and
TTL output compatible.

MEMORY
As shown in Figure 3, the MC6805K2 and MC6805K3
microcomputers are capable of addressing 4096 bytes of
memory space with their program counters. The MCUs have
implemented 2048 bytes of ROM including eight interrupt
vectors, 248 bytes of self-check ROM, 96 bytes of user RAM,
128 bytes of EEPROM, and 17 bytes of port 1/0, control,
data, and status registers. The user ROM is split into two
areas. One area is the main memory (locations $700 to $EFF).
The last eight user ROM locations, $FF8 to $FFF, are for the
interrupt vectors.
The MCUs reserve the first 17 memory locations for 1/0
and hardware features. These locations are used for the
ports, the port data direction registers, the timers, the
miscellaneous register, the serial peripheral interface, and
the EEPROM program control. Of the 96 RAM bytes, 31
($061 through $07F) are shared with the stack area. The
stack must be used with care when data shares the stack
area. The lower sixteen bytes of RAM, between $20 and $2F,
are powered through the VSTBY pin.
The shared stack area is used during the processing of an
interrupt or subroutine calls, to save the contents of the CPU
state. Since the register contents are pushed onto the stack,
the stack pointer decrements during pushes. The low order
byte (PCL) of the program counter is stacked first; then the
high order four bits (PCH) are stacked. This ensures that the
program counter is loaded correctly during pulls from the
stack, since the stack pointer increments when it pulls data
from the stack. A subroutine call results in only the program
counter (PCL, PCH) contents being pushed onto the stack;
the remaining CPU registers are not pushed (see Figure 4).

I

MC6805K2·MC6805K3

FIGURE 3 -

MEMORY MAP

..

Hex
$000

Hex
$000

Port A Data

$080
EEPROM
128 Bytes

Port B Data
Port C Data

$100

Port D Data

Future
EEPROM

Port A DDR
$400

Port B DDR
Port C DDR

Future
ROM

Port D DDR
$700

II

Timer A Data
Timer A Control
Miscellaneous

Main
ROM
2048
Bytes

Program Control
Timer B Data
Timer B Control
SPI Data
SPI Control

$FOO

Prescaler Control

Self-Check ROM
248 Bytes

Future RAM
$FF8

Vectors 8 Bytes

RAM 96 Bytes

$FFF

FIGURE 4 -

INTERRUPT STACKING DIAGRAM

5
n-4

1 1

1

4

1

3

2

Condition
Code Register

o

Pull
n+ 1

n-3

Accumulator

n+2

n-2

Index Register

n+3

I

n+4

n-1

11 1 1

PCH*

PCl*

n+5

Push
* For subroutine calls, only PCl and PCH are stacked.

3-230

®

MC680SP2

MOTOROLA
Advance Information

HMOS
(HIGH DENSITY
N-CHANNEL. SILICON-GATE
DEPLETION LOAD)

8-BIT MICROCOMPUTER UNIT
The MC6805P2 Microcomputer Unit (MCU) is a member of the
M6805 Family of low-cost single-chip microcomputers. This 8-bit
microcomputer contains a CPU, on-chip CLOCK, ROM, RAM, I/O, and
TIMER. It is designed for the user who needs an economical microcomputer with the proven capabilities of the M68oo-based instruction set.
The following are some of the hardware and software highlights of the
MC6805P2 MCU.

8-BIT
MICROCOMPUTER

HARDWARE FEATURES

• 8-Bit Architecture

L SUFFIX

• 64 Bytes of RAM

CERAMIC PACKAGE
CASE 719

• Memory Mapped I/O
• 1100 Bytes of User ROM
• 20 TTLICMOS Compatible Bidirectional I/O Lines (8 Lines are
LED Compatible)
• On-Chip Clock Generator
• Self-Check Mode
• Zero Crossing Detection
• Master Reset
• Complete Development System Support on EXORciser
• 5 V Single Supply
SOFTWARE FEATURES

• Similar to M6800 Family
• Byte Efficient Instruction Set
• Easy to Program
• True Bit Manipulation
• Bit Test and Branch Instruction

PIN ASSIGNMENT

• Versatile Interrupt Handling
• Versatile Index Register

VSS

• Powerful Indexed Addressing for Tables
• Full Set of Conditional Branches

RESET

iNT

PA7

VCC

PA6

• Memory Usable as Register/Flags
• Single Instruction Memory Examine/Change
• 10 Powerful AddreSSing Modes
• All AddreSSing Modes Apply to ROM, RAM, and I/O
USER SELECTABLE OPTIONS

• Internal 8-Bit Timer with Selectable Clock Source (External Timer
Input or Internal Machine Clock)

EXTAL

PA5

XTAL

PM

NUM

PA3

TIMER

PA2

PCO

PAl

PCl

PAD

• Timer Prescaler Option (7 Bits, 2n)

PC2

PB7

• 8 Bidirectional I/O Lines with TTL or TTLI CMOS Interface Option

PC3

PB6

• Crystal or Low-Cost Resistor Oscillator Option

PBO

PB5

• Low Voltage Inhibit Option
• Vectored Interrupts: Timer, Software, and External

ThiS document contains information on a new product Specifications and Information here",
are subject to change Without notice

3-231

PBl

PB4

PB2

PB3

I

MC6805P2

FIGURE 1 -

MC6805P2 HMOS MICROCOMPUTER BLOCK DIAGRAM

TIMER

Data
Dir.
Reg.

Port
B
Reg.

PBO
PBl
PB2 Port
PB3
B
PB4 I/O
PB5 Lines
PB6
PB7

Data
Dir
Reg

Port
C
Reg

PCO Port
PCl
C
PC2 I/O
PC3 lines

Accumulator
8

I

PAO
PAl
Port PA2
A
PA3
I/O PA4
Lines PA5
PA6
PA7

8
Port
A
Reg.

Data
Dir.
Reg.

A

CPU
Control

Index
Register

X
Condition
Code
Register CC

CPU

Stack
Pointer

SP
Program
Counter
High PCH
1100 X 8
User ROM
116X8SelfCheck ROM

AlU

Program
Counter
low PCl

MAXIMUM RATINGS
Rating

Symbol

Value

Unit

Supply Voltage

VCC

-0.3 to + 7.0

V

Input Voltage (Except Pin 6)

Vin

-0.3 to + 7.0

Operating Temperature Range

TA
T stg

o to 70

V
DC

-55 to + 150

DC

Storage Temperature Range
Junction Temperature
Plastic
Ceramic

150
TJ

Cerdip

DC

175
175

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields, however, it IS advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this highImpedance circuit. For proper operation It IS
recommended that Vin and V out be constrained to the range VSS:s IV ,n or Vout)
:s V CC- Reliability of operation IS enhanced if
unused inputs are tied to an appropriate logic
voltage level (e.g., either VSS or VCC)

THERMAL CHARACTERISTICS
Characteristic

Symbol

Value

(jJA

50

Unit

Thermal Resistance

72

Plastic
Ceramic
Cerdip

DC/W

60

POWER CONSIDERATIONS
The average chip-junction temperature, Tj, in °C can be obtained from:
Tj=TA+(PDe(;ljA)
Where:

(1)

T A=Ambient Temperature, °C
(;l jA = Package Thermal Resistance, junction-to-Ambient, °C/W
PD= PINT+ PPORT
PINT= ICC x Vce Watts - Chip Internal Power
PPORT= Port Power Dissipation, Watts - User Determined
For most applications PPORT2 Signal. The maximum frequency of a Signal that can be recognized by the TIMER or INT pin
logic is dependent on the parameter labeled tWL, tWH. The
pin logic that recognizes the high (or low) state on the pin
must also recognize the low (or high) state on the pin in
order to "re-arm" the internal logic. Therefore, the period
can be calculated as follows: (assumes 50/50 duty cycle for a
given period)
tcyc x 2 + 250 ns = period =

TIMER BLOCK DIAGRAM

<1>2
(Internal)
Timer
TIMER
Input
Pin

r------l
I

I

L_____ J

Manufacturing
Mask
Options

Write

~

freq

The period is not simply tWL + tWH. This computation is
allowable, but it does reduce the maximum allowable frequency by defining an unnecessarily longer period (250 ns
twice).
When the r/>2 signal is used as the source, it can be gated
by an input applied to the TIMER input pin allowing the user
to easily perform pUlse-width measurements. (NOTE: For
ungated r/>2 clock inputs to the timer prescaler, the TIMER

Write

Read
Internal Data Bus

3-236

Read

MC6805P2

pin should be tied to VCC.) The source of the clock input is
one of the mask options that is specified before manufacture
of the MCU.
A prescaler option can be applied to the clock input that
extends the timing interval up to a maximum of 128 counts
before decrementing the counter. This prescaling mask option is also specified before manufacture.
The timer continues to count past zero, falling through to
$FF from zero and then continuing the count. Thus, the
counter can be read at any time by reading the timer data
register (TOR). This allows a program to determine the
length of time since a timer interrupt has occurred and not
disturb the counting process.
At power-up or reset, the prescaler and counter are initialized with all logical ones, the timer interrupt request bit
(bit 7) is cleared, and the timer interrupt mask bit (bit 6) is
set.

low voltage detect circuit; see Figure 10. The internal circuit
connected to the RESET pin consists of a Schmitt trigger
which senses the RESET line logic level. The Schmitt trigger
provides an internal reset voltage if it senses a logic "0" on
the RESET pin. During power-up, the Schmitt trigger
switches on (removes reset) when the RESET pin voltage
rises to VIRES +. When the RESET pin voltage falls to a
logical "0" for a period longer than one tcyc, the Schmitt
trigger switches off to provide an internal reset voltage. The
"switch off" voltage occurs at VIRES -. A typical reset
Schmitt trigger hysteresis curve is shown in Figure 11.
During power-up, a delay of tRHL is needed before allowing the RESET input to go high. This time allows the internal
clock generator to stabilize. Connecting a capacitor to the
RESET input, as shown in Figure 12, typically provides sufficient delay. See Figure 16 under Interrupts section for the
complete reset sequence.

SELF-CHECK
The self-check capability of the MC6805P2 MCU provides
an internal check to determine if the part is functional. Connect the MCU as shown in Figure 9 and monitor the output
of port C bit 3 for an oscillation of approximately 7 Hz. A
9-volt level on the TIMER input, pin 7, energizes the ROMbased self-check feature. The self-check program exercises
the RAM, ROM, TIMER, interrupts, and I/O ports.

RESETS
The MCU can be reset three ways: by initial power-up, by
the external reset input (RESET), and by an optional internal

FIGURE 9 -

INTERNAL CLOCK GENERATOR OPTIONS
The internal clock generator circuit is designed to require a
minimum of external components. A crystal, a resistor, a
jumper wire, or an external signal may be used to generate a
system clock with various stability/cost tradeoffs. A
manufacturing mask option is required to select either the
crystal oscillator or the RC oscillator circuit. The oscillator
frequency is internally divided by four to produce the internal
system clocks.
The different connection methods are shown in Figure 13.
The crystal specifications and suggested PC board layouts

SELF-CHECK CONNECTIONS

MC6805P2

INT

PA7 27
PA6 26

RESET

28

1

:::r:

RESET

1.0 pF

PA4 24
XTAL

*4
+10 V

10 k

PA5 25

PA3 23
PA2 22

EXTAL

7

TIMER

6

NUM

PAl

21

PAO

20

PB7

19

PB6

VCC

18

PB5

17

PB4

16
15

PCO

PB3

PCl

PB2

PC2

PBl

13

PC3

PBO

12

14

*This connection depends on the clock oscillator user selectable mask option.
Use crystal if crystal option is selected.

3-237

I

MC6805P2

are given in Figure 15. A resistor selection graph is given in
Figure 16.
The crystal oscillator startup time is a function of many
variables: crystal parameters (especially RS), oscillator load

FIGURE 10 -

capacitance, Ie parameters, ambient temperature, and supply voltage. To ensure rapid oscillator startup, neither the
crystal characteristics nor the load capacitance should exceed recommendations.

POWER AND RESET TIMING

5V
VCC

REm
Pin

II

Internal
Reset

FIGURE 11 - TYPICAL RESET SCHMITT
TRIGGER HYSTERESIS

FIGURE 12 -

Out
Of
Reset

POWER-UP RESET DELAY CIRCUIT

V CC -J\}V'v---i----,

=r::: 10

/l

F

Part Of
MC6805P2
MCU
In
Reset

I

I

I

0.8 V

2V

4V

I

FIGURE 13 -

CLOCK GENERATOR OPTIONS

XTAL

XTAL
(See Notel CJ
CL

4

=r:::

MC6805P2
MCU
EXTAL
(Crystal Mask
Option 1

4

EXTAL

MC6805P2
MCU
(Resistor Mask
Optionl

Approximately 25% to 50% Accuracy
Typical tcyc = 1.25 /ls
External Jumper

Crystal

+5V
_'''''~_ _

XTAL
External
Clock
Input

4

MC6805P2
EXTAL
MCU
(Crystal Mask
Option 1

(See Figure 151

4

No
Connection

XTAL
EXTAL

MC6805P2
MCU
(Resistor Mask
Option 1

Approximately 10% to 25% Accuracy
External Resistor
(Excludes Resistor Tolerencel

External Clock

NOTE: The recommended CL value with a 4.0 MHz crystal is 27 pF, maximum, including system distributed capacitance. There is an internal
capllcitance of approximately 25 pF on the XTAL pin. For crystal frequencies other than 4 MHz, the total capacitance on each pin
should be scaled as the inverse of the frequency ratio. For example, with a 2 M Hz crystal, use approximately 50 pF on EXT AL and
approximately 25 pF on XTAL. The exact value depends on the Motional-Arm parameters of the crystal used.

3-238

MC6805P2

FIGURE 14 - CRYSTAL MOTIONAL ARM PARAMETERS
AND SUGGESTED PC BOARD LAYOUT

FIGURE 15 - TYPICAL FREQUENCY SELECTION FOR
RESISTOR OSCILLATOR OPTION
8.0

la)
Crystal Parameters

7.0

C1

EXTAL~~XTAL
4

·~C~

AT - Cut Parallel Resonance Crystal
Co =7 pF Max.
Freq.=4.0MHz@CL=24pF
RS = 50 ohms Max.

5

~
~
>

0

c

f~
~0

6.0
VCC=5.25 V
TA=25°C

5.0
40
3.0
2.0

(3

1.0
0

0

10

20

30
40
50
Resistance (k!ll

60

70

80

(b)

INTERRUPTS

(e)

The MC6805P2 MCU can be interrupted three different
ways: through the external interrupt (lNT) input pin, the internal timer interrupt request, or the software interrupt instruction lSWI). When any interrupt occurs: processing is
suspended, the present CPU state is pushed onto the stack,
the interrupt bit (I) in the condition code register is set, the
address of the interrupt routine is obtained from the appropriate interrupt vector address, and the interrupt routine
is executed. Stacking the CPU registers, setting the I bit, and
vector fetching requires a total of 11 tcyc periods for completion.
A flowchart of the interrupt sequence is shown in
Figure 16. The interrupt service routine must end with a
return from interrupt (RTI) instruction which allows the MCU
to resume processing of the program prior to the interrupt
(by unstacking the previous CPU state). Unlike RESET,
hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the
current instruction execution is complete.
When the current instruction is complete, the processor
checks all pending hardware interrupts and if unmasked,
proceeds with interrupt processing; otherwise, the next instruction is fetChed and executed. Note that masked interrupts are latched for later interrupt service.
If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed as any other instruction.
The external interrupt is internally synchronized and then
latched on the falling edge of INT. A sinusoidal input signal
(fINT maximum) can be used to generate an external interrupt, as shown in Figure 17(a), for use as a zero-crossing
detector. This allows applications such as servicing time-ofday routines and engaging/disengaging ac power control
devices.
For digital applications, the INT pin can be driven by a
digital signal. The maximum frequency of a signal that can
be recognized by the TIMER or INT pin logic is dependent on
the parameter labeled tWL, tWH. The pin logic that
recognizes the high (or low) state on the pin must also

NOTE: Keep crystal leads and circuit
connections as short as possible.

3-239

I

MC6805P2

FIGURE 16 -

FiE'SET AND INTERRUPT PROCESSING FLOWCHART

1-1 (in CC)
07F- SP
O-DDRs
CLR iNi Logic
FF- Timer
7F-Prescaler
7F- TCR

I

Stack
PC. X. A. CC

Timer
Load PC From:
SWI: 7FC/7FD
INT
7FA /7FB
TIMER 7F8 I7F9

Put 7FE on
Address Bus

Fetch
Instruction

Load PC
from
7FE17FF

Execute All
Instruction
Cycles

FIGURE 17 - TYPICAL INTERRUPT CIRCUITS
(a) Zero-Crossing Interrupt

(b) Digital-Signal Interrupt

VCC
ac Input
(fINT Max.)
RSl mil
ac Input ~
lOV acp_p

(Current

~Limiting)

TTL

2

MC6805P2
MCU

R

0.1-1.0
I'F

3·240

4.7 k

Level
INT
Digital--.....--'~
Input

MC6805P2
MCU

MC6805P2

recognize the low (or high) state on the pin in order to "rearm" the internal logic. Therefore, the period can be
calculated as follows: (assumes 50/50 duty cycle for a given
period)

.

1

tcyc x 2 + 250 ns = penod = freq
The period is not simply tWL + tWH. This computation is
allowable, but it does reduce the maximum allowable frequency by defining an unnecessarily longer period (250 ns
twice). See Figure 17(b).
A software interrupt (SWI) is an executable instruction
which is executed regardless of the state of the I bit in the
condition code register. Note that if the I bit is zero SWI
executes after the other interrupts. SWls are usually used as
breakpoints for debugging or as system calls.

INPUT/OUTPUT
There are 20 input/output pins. The INT pin may also be
polled with branch instructions to provide an additional input
pin. All pins (port A, B, and C) are programmable as either
inputs or outputs under software control of the corresponding data direction register (DDR). The port I/O programming
is accomplished by writing the corresponding bit in the port
DDR to a logic "1" for output or a logic "0" for input. On
reset, all the DDRs are initialized to a logic "0" state to put
the ports in the.input mode. The port output registers are not
initialized on reset but may be written to before setting the
DDR bits to avoid undefined levels. When programmed as
outputs, the latched output data is readable as input data,

regardless of the logic levels at the output pin due to output
loading; see Figure 18. When port B is programmed for outputs, it is capable of sinking 10 mA and sourcing 1 mA on
each pin.
All input/output lines are TTL compatible as both inputs
and outputs. Ports Band C are CMOS compatible as inputs.
?ort A may be made CMOS compatible as outputs with a
mask option. The address map in Figure 5 gives the address
of data registers and DDRs. The register configuration is provided in Figure 19 and Figure 20 provides some examples of
port connections.
Caution
The corresponding DDRs for ports A, B, and Care
write-only registers (registers at $004, $005, and $006).
A read operation on these registers is undefined. Since
BSET and BCLR are read-modify-write functions, they
cannot be used to set or clear a DDR bit (all "unaffected" bits would be set). It is recommended that all
DDR bits in a port be written using a single-store instruction.

The latched output data bit (see Figure 18) may always be
written. Therefore, any write to a port writes all of its data
bits even though the port DDR is set to input. This may be
used to initialize the data registers and avoid undefined outputs; however, care must be exercised when using readmodify-write instructions since the data read corresponds to
the pin level if the DDR is an input ("0") and corresponds to
the latched output data when the DDR is an output ("1"),

FIGURE 18 - TYPICAL PORT 1/0 CIRCUITRY

Data
Direction Register
Bit*
 ORA

4

JMP
EXT
3

2
4

JSR

OIR

8 JSR
EXT
3

OIR

' LOX
3
EXT

LOX

2

, STX
OIR
2

'ofCy,"
M"""oo;'

IX2

3
6
3

CMP
IXI

;S

~

9

ORA

1

A

4

7

BSR
REL
2
, LOX
2
IMM

SBC

BIT

5

4

2

3

,f"

5 SBC

" CPX
3
IX2

BIT

2

8

3

5

CPX
OIR
2

" STA
EXT
3

ADD
IMM
2

6

4

L
4

CMP

Con

IX

5

6

CMP
OIR

4

2

1X2

STA
OIR
2

TXA
INH

Abbreviations for Add.... Modes
INH
IMM
DIR
EXT
REL
BSC
BTB
IX
IXl
IX2

INH

o

EX"

5

L

ASP
INH
1
2
NOP
1
INH

6

7

CLRX
INH

INC
6

7

4

CLRA
INH

6

7

4

AND
IMM

2 BI~MM
2
2 LOA
IMM

6

• SUB
2
-OIR

4

2

LSR
1

"

3BRSEJ~B 2 BSE~~c 2 BM~EL 2
7

b

1010

RTS

rSEl;B

10

NEG

4

1001

1~

1

6
2 ROR
DIR

4

BRSE
3
JiB

faa

NEG
1
INH

NEG
1
INH

A

DIR
B

4

BRCL
3
:1B . 2 BCL~~c -.2 BCSBf.L

B

1

O,~,

IMM

REI

4

-.2. BLSf!f.J.

10

::e

O~O

4

I
Reg~erl Memory

Control
INH
INH
9

6

BRSE
3
ltB

10

O~'

BRN
RE'

2

ItO
1011

NEG
2
-OIR

IX

O~

rJ"
b

RIIIId-Modjfy-Write
INH
XI

4

BRCL
3
:iB

BRSE
3
l:B

INH

Dilt

~

M6805 HMOS FAMILY OPCODE MAP

t>

3

STX
EXT

1

~

JSR

3
t>

IX2
LOX

3
3

STX

4

2

JMP

IXI

8 JSR
IXI
2
5

IX2

2
6

IX2

2

LOX
STX

B

JJMP
IX

1

JSA
1
4

LOX

IXI

1

IXI

5
1

IX

C

:

1100

0

I

1101

E

IX

1110

I

IX

F
1111

I

STX

LEGEND

r,

1 1; ;

SUI
IX

~

0"",. ;0

H~"";""I

Ope ode in Binary

(XX)() ~

' - - - - - - - - - - Address Mode

MC6805P2

ORDERING INFORMATION
The information required when ordering a custom MCU is
listed below. The ROM program may be transmitted to
Motorola on EPROM(s) or an MOOS disk file.
To initiate a ROM pattern for the MCU it is necessary to
first contact your local Motorola representative or Motorola
distributor.

puter listing of the ROM code will be generated and returned
along with a listing verification form. The listing should be
thoroughly checked and the verification form completed,
signed, and returned to Motorola. The Signed verification
form constitutes the contractual agreement for creation of
the customer mask. If desired, Motorola will program on
blank EPROM from the data file used to create the custom
mask and aid in the verification process.

EPROMs

The MC68705P3 EPROM MCU programmed with the
customer program may be used to submit the ROM pattern.
Note that while the MC6805P2 has 1.1K Bytes of ROM, the
MC68705P3 contains 1.8K of EPROM memory.
The MCM2716 or MCM2532 type EPROMs, programmed
with the customer program (positive logic sense for address
and datal. may be submitted for pattern generation. The
EPROM must be clearly marked to indicate which EPROM
corresponds to which address space. The recommended
marking procedure is illustrated below:

xxx

080

xxx =

Customer ID

After the EPROM(s) are marked, they should be placed in
conductive IC carriers and securely packed. 00 not use
styrofoam.
VERIFICATION MEDIA
All original pattern media (EPROMs or floppy disk) are
filed for contractual purposes and are not returned. A com-

ROM VERIFICATION UNITS (RVUs)
Ten MCUs containing the customer's ROM pattern will be
sent for program verification. These units will have been
made using the custom mask but are for the purpose of
ROM verification only. For expediency they are usually unmarked, packaged in ceramic, and tested only at room
temperature and 5 volts. These RVUs are included in the
mask charge and are not production parts. The RVUs are
thus not guaranteed by Motorola Quality Assurance and
should be discarded after verification is completed.
FLEXIBLE DISKS
The disk media submitted must be single-sided, singledensity, 8-inch, MOOS compatible floppies. The customer
must write the binary file name on the disk with a felt-tip
pen. The minimum MOOS system files as well as the absolute binary object file (filename LO type of file) from the
M6805 cross assembler must be on the disk. An object file
made from a memory dump using the ROLLOUT command
is also acceptable. Consider submitting a source listing as
well as the following files: filename, LX (EXORciser loadable
format) and filename, SA (ASCII Source Code). These files
will of course be kept confidential and are used 1) to speed
up the process in-house if any problems arise, and 2) to
speed up the user-to-factory interface if the user finds any
software errors and needs assistance quickly from Motorola
factory representatives.
MOOS is Motorola's Disk Operating system available on
development systems such as EXORciser, EXORset, etc.

GENERIC INFORMATION

Package Type

Internal Clock
Frequency (MHz)

Temperature
OQC to 70 Q

e

Generic Number

Ceramic
L Suffix

1.0
1.5
2.0

Plastic
P Suffix

1.0
1.5
2.0

OQC to 70QC
OQC to 70 QC

MC6805P2P
MC68A05P2P
MC68B05P2P

Cerdip
S Suffix

1.0
1.5
2.0

OQC to 70Qe
OQC to 70 QC
OQC to 70QC

MC6805P2S
MC68A05P2S
MC68B05P2S

OQC to 70QC
OQC to 70QC
OQC to 70 QC

3·251

MC6805P2L
MC68A05P2L
MC68B05P2L

I

MC6805P2

MC6805P2 MCU CUSTOM ORDERING INFORMATION

Date _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Customer PO Number _ _ _ _ _ _ _ _ _ __
Customer Company _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Motorola Part Numbers
MC _ _ _ _ _ _ __

Address

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SC _______- - - - - City _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ State _ _ _ _ _ _ _ _ _ _ _ _ _ Zip _ _ _ _ __
Country _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~

Phone _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Extension _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Cusl()mer Contact Person _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-,-_ _ _ _ _ _ _ __
Customer Part Number _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

I

OPTION LIST

Select the options for your MCU from the following list, A
manufacturing mask vyill be generated from this information,
Timer Clock Source
Internal 2 signal. The maximum frequency of a signal that can be recognized by the TIMER or INT pin
logic is dependent on the parameter labeled tWL, tWH. The
pin logic that recognizes the high (or low) state on the pin
must also recognize the low (or high) state on the pin in
order to "re-arm" the internal logic. Therefore, the period
can be calculated as follows: (assumes 50/50 duty cycle for a
given period)
tcyc x 2 + 250 ns = period = _1_
freq

FIGURE 8 - TIMER BLOCK DIAGRAM

2

Timer
Interrupt
Request

(Internal!

Timer
Interrupt
Mask

TIMER
Input

Pin
,-------')

:
:
:L______ !:
Manufacturing
Mask Options
Write

Read
Internal Data Bus

3-259

Write

Read

I

MC6805P4

FIGURE 9 - SELF-CHECK CONNECTIONS

iNT

W

MC6805P4

PA6 26

RESET

,a

28 RESET

.,

5

PA5 25
PA4 24

XTAL

PA3 23
PA2 22

4 MHz*

_

c::::::J
EXTAL

PAl 21
PAO 20

24pF~

+lOV
VCC

I

PA7' 27

10 kO -=7
3
6

TIMER
PB7

VCC

19

PB6 18
PB5 17

VSB

PB4

16

PCO

PB3

15

PCl

PB2 14

PC2

PBl

PC3

PBO 12

13

VSS
-= 1

* NOTE: For RC user selectable mask option, omit the crystal and the 24 pF capacitor and connect pins 4 and 5 together with a jumper or
resistor to

Vce.

The period is not simply tWL +tWH. This computation is
allowable, but it does reduce the maximum allowable frequency by defining an unnecessarily longer period (250 ns
twice).
When the 4>2 signal is used as the source, it can be gated
by an input applied to the TIM ER input pin allowing the user
to easily perform pulse-width measurements. (Note: for
ungated 4>2 clock inputs to the timer prescaler, the TIMER
pin should be tied to VCC.) The source of the clock input is
one of the mask options that is specified before manufacture
of the MCU.
A prescaler option, divide by 2n , can be applied to the
clock input that extends the timing interval up to a maximum
of 128 counts before decrementing the counter. This prescaling mask option is also specified before manufacture.
The timer continues to count past zero, falling through to
$FF from zero and then continuing the count. Thus, the
counter can be read at any time by reading the timer data
register (TOR). This allows a program to determine the
length of time since a timer interrupt has occurred and not
disturb the counting process.
At power-up or reset, the prescalerand counter are initialized with all logical ones, the timer interrupt request bit
(bit 7) is cleared, and the timer interrupt mask bit (bit 6) is
set.

of port C bit 3 for an oscillation of approximately 7 Hz. A
9-volt level on the TIMER input, pin 7, energizes the ROMbased self-check feature. The self-check program exercises
the RAM, ROM, TIMER, interrupts, and 1/0 ports.

RESETS
The MCU can be reset three ways: by initial power-up, by
the external reset input (R ES ET), and by an optional internal
low voltage detect circuit; see Figure 10. The internal circuit
connected to the RESET pin consists of a Schmitt trigger
which senses the R"E"SEi' line logic level. The Schmitt trigger
provides an internal reset voltage if it senses a logic "0" on
the RESET pin. During power-up, the Schmitt trigger
switches on (removes reset) when the RESET pin voltage
rises to VIRES+. When the RESET pin voltage falls to a
logical "0" for a period longer than one tcyc, the Schmitt
trigger switches off to provide an internal reset voltage. The
"switch off" voltage occurs at VIRES -. A typical reset
Schmitt trigger hysteresis curve is shown in Figure 11.
During power-up, a delay of tRHL is needed before allowing the RESET input to go high. This time allows the internal
clock generator to stabilize. Connecting a capacitor to the
RESET input, as shown in Figure 12, typically provides sufficient delay. See Figure 16 under the Interrupts section for
the complete reset sequence.

SELF-CHECK
The self-check capability of the MC6805P4 MCU provides
an internal check to determine if the part is functional. Connect the MCU as shown in Figure 9 and monitor the output

3-260

INTERNAL CLOCK GENERATOR OPTIONS
The internal clock generator circuit is designed to require a
minimum of external components. A crystal, a resistor, a

MC6805P4

jumper wire, or an external signal may be used to generate a
- system clock with various stability/cost tradeoffs. A
- manufacturing mask option is required to select either the
crystal oscillator or the RC oscillator circuit. The oscillator
frequency is internally divided by four to produce the internal
system clocks.
The different connection methods are shown in Figure 13.
The crystal specifications and suggested PC board layouts
FIGURE 10 -

are given in Figure 14. A resistor selection graph is given in
Figure 15.
The crystal oscillator startup time is a function of many
variables: crystal parameters (especially RS), oscillator load
capacitance, IC parameters, ambient temperature, and supply voltage. To ensure rapid oscillator startup, neither the
crystal characteristics nor the load capacitance should exceed recommendations.

POWER AND RESET TIMING

5V
VCC

ov

I

Internal
Reset
FIGURE 11 - TYPICAL RESET SCHMID
TRIGGER HYSTERESIS

FIGURE 12 -

Out
Of
Reset

POWER-UP RESET DELAY CIRCUIT

vCC

-J\)'V'v-~---,

=r: 10 I'F

Part Of
MC6805P4
MCU
In
Reset

I

I,

I
I

0.8 V

4V

2 V

FIGURE 13 -

CLOCK GENERATOR OPTIONS

XTAL

XTAL
(See Notel

c:J

MC6805P4
EXTAL
MCU
(Crystal Mask
Optlonl

EXTAL

MC6805P4
MCU
(Resistor Mask
OptIOn)

Approximately 25% to 50% Accuracy
Typical tcyc = 1.25 P.s
External Jumper

Crystal

+5V
- v , / v -__ XTAL

XTAL
External
Clock
Input

EXTAL

MC6805P4
MCU
(Crystal Mask
Option)

(See Figure 15)

4

No
Connection

EXTAL

MC6805P4
MCU
(Resistor Mask
Option)

Approximately 10% to 25% Accuracy
External Resistor
(Excludes Resistor Tolerance)

External Clock

NOTE: The recommended CL value with a 4.0 MHz crystal is 27 pF, maximum, including system distributed capacitance. There is an internal
capacitance of approximately 25 pF on the XT AL pin. For crystal frequencies other than 4 MHz, the total capacitance on each pin
should be scaled as the inverse of the frequency ratio. For example, with a 2 MHz crystal, use approximately 50 pF on EXT AL and
approximately 25 pF on XT AL. The exact value depends on the Motional-Arm parameters of the crystal used.

3-261

MC6805P4

FIGURE 14 - CRYSTAL MOTIONAL ARM PARAMETERS
AND SUGGESTED PC BOARD LAYOUT

FIGURE 15 - TYPICAL FREQUENCY SELECTION FOR
RESISTOR OSCILLATOR OPTION
8.0r-~-----------------------------------'

Crystal Parameters

EXTAL

(a)

C1

~~.

4·~~

AT - Cut Parallel Resonance Crystal
Co =7 pF Max.
Freq=4.0 MHz@CL=24pF
RS = 50 ohms Max.

7.0

~ 6 .0
Z
XTAL

5

i

Vee =525 V
TA=25°e

50

f 40
E

3.0

U 2.0

o

1.0
O~---L----~--~----~--~-----L----~---J

I

o

(b)

10

20

40
50
30
Resistance (kill

60

70

INTERRUPTS
The MC6805P4 MCU can be interrupted three different
ways: through the external interrupt (iNT) input pin, the internal timer interrupt request, or the software interrupt instruction (SWI). When any interrupt occurs: processing is
suspended, the present CPU state is pushed onto the stack,
the interrupt bit (I) in the condition code register is set, the
address of the interrupt routine is obtained from the appropriate interrupt vector address, and the interrupt routine
is executed. Stacking the CPU registers, setting the I bit. and
vector fetching ~oquire a total of 11 tcyc periods for completion.
A flowchart of the interrupt sequence is shown in
Figure 16. The interrupt service routine must end with a
return from interrupt (RTJ) instruction which allows the MCU
to resume processing of the program prior to the interrupt
(by unstacking the previous CPU state). Unlike RESET,
hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the
current instruction execution is complete.
When the current instruction is complete, the processor
checks all pending hardware interrupts and if unmasked,
proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Note that masked interrupts are latched for later interrupt service.
If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed as any other instruction.
The external interrupt is internally synchronized and then
latched on the falling edge of INT. A sinusoidal input Signal
(fINT maximum) can be used to generate an external interrupt, as shown in Figure 17(a), for use as a Zero-Crossing
Detector. This allows applications such as serviCing time-ofday routines and engaging/disengaging ac power control
devices.

(c)

NOTE: Keep crystal leads and circuit
connections as short as possible.

3-262

80

MC6805P4

FIGURE 16 -

RESET AND INTERRUPT PROCESSING FLOWCHART

1-1 Bit lin CCI
07F-SP
O-DDRs
CLR INT Logic
FF-Timer
7F-Prescaler
7F-TCR

Stack
PC, X, A, CC

Load PC From:
SWI 7FC17FD
INT: 7FA17FB
TIMER: 7F817F9

Put 7FE on
Address Bus

Fetch
Instruction

SWI

Load PC
from
7FE17FF

Execute All
Instruction
Cycles

FIGURE 17 -

TYPICAL INTERRUPT CIRCUITS
(b) Digital-Signal Interrupt

(a) Zero-Crossing Interrupt

VCC

I ac

TTL

(Current

)~Imltlngl

nPMutax.
(f INT
Rs1 MO
ac Inputs
10 Vac p-p

R

2

iNT

MC6805P4
MCU

0.1-1.0
I-'F

4.7 k

Level
2
Digital--_---..,
Input

lJ

3-263

iN'f

MC6805P4
MCU

I

MC6805P4

For digital applications, the iNT pin can be driven by a
digital signal. The maximum frequency of a signal that can
be recognized by the INT pin logic is dependent on the parameter labeled tWL, tWH. The pin logic that recognizes the
high (or low) state on the pin must also recognize the low (or
high) state on the pin in order to "re-arm" the internal logic.
Therefore, the period can be calculated as follows: (assumes
50/50 duty cycle for a given period)
1
tcyc x 2 + 250 ns = period = freq

I

outputs, the latched output data is readable as input data,
regardless of the logic levels at the output pin due to output
loading; see Figure 18. When Port B is programmed for outputs, it is capable of sinking 10 mA and sourcing 1 mA on
each pin.
All input/output lines are TTL compatible as both inputs
and outputs. Ports Band C are CMOS compatible as inputs.
Port A may be made CMOS compatible as outputs with a
mask option. The address map in Figure 5 gives the address
of data registers and DDRs. The register configuration is provided in Figure 19 and Figure 20 provides some examples of
port connections.

The period is not simply tWL + tWH. This computation is
allowable, but it does reduce the maximum allowable frequency by defining an unnecessarily longer period (250 ns
twice). See Figure 17(b).
A software interrupt (SWI) is an executable instruction
which is executed regardless of the state of the I bit in the
condition code register. Note that if the I bit is zero SWI
executes after the other interrupts. SWls are usually used as
breakpoints for debugging or as system calls.

Caution
The corresponding DDRs for ports A, B, and Care
write-only registers (registers at $004, $005, and $006).
A read operation on these registers is undefined. Since
BS nand BCLR are read-modify-write functions, they
cannot be used to set or clear a DDR bit (all "unaffected" bits would be set). It is recommended that all
DDR bits in a port be written using a single-store
instruction.

INPUT/OUTPUT
There are 20 input/output pins. The INT pin may also be
polled with branch instructions to provide an additional input
pin. All pins (Ports A, B, and C) are programmable as either
inputs or outputs under software control of the corresponding data direction register (DDR). The port I/O programming
is accomplished by writing the corresponding bit in the port
DDR to a logic "1" for output or a logic "0" for input. On
reset, all the DDRs are initialized to a logic "0" state to put
the ports in the input mode. The port output registers are not
initialized on reset but may be written to before setting the
DDR bits to avoid undefined levels. When programmed as

The latched output data bit (see Figure 18) may always be
written. Therefore, any write to a port writes all of its data
bits even though the port DDR is set to input. This may be
used to initialize the data registers and avoid undefined outputs; however, care must be exercised when using readmodify-write instructions since the data read corresponds to
the pin level if the DDR is an input (0} and corresponds to the
latched output data when the DDR is an output (1).

FIGURE 18 - TYPICAL PORT 1/0 CIRCUITRY

Data
Direction Register
Bit*
(f)

c

~~
2c

-

~
c

0

u

Latched
Output
Data
Bit

*DDR is a write-only register and reads as ali "1s"
* * Ports A (with CMOS drive disabled), B, and C are three-state ports.
Port A has optional internal pullup devices to provide CMOS drive
capability. See Electrical Characteristics tables
for complete information.

3-264

Data
Direction
Register
Bit
1
1
0

Output
Data
Bit
0
1
X

Output
State
0
1

Hi-Z* *

Input
To
MCU
0
1

Pin

MC6805P4

FIGURE 19 -

MCU REGISTER CONFIGURATION

PORT DATA REGISTER

PORT OAT A DIRECTION REGISTER (DDR)
0

(1) Write Only; reads as all "1s"
(2) 1 = Output; 0= Input. Cleared to 0 by reset.
(3) Port A Addr = $004
Port B Addr= $005
Port C Addr= $006 (Bits 0-3)

Port .A Addr = $000
Port B Addr= $001
Port C Addr= $002 IBits 0-31

TIMER CONTROL REGISTER (TCR)
1
4
2
6
3
5

I I I I I
1

1

1

1

1

0

TIMER DATA REGISTER (TDR)
0

1$009

LSB

MSB

1$008

TCR7 - Timer Interrupt Status Request Bit: Set when
TDR goes to zero; must be cleared by software.
Cleared to 0 by reset.
TCR6 Bit 6- Timer Interrupt Mask Bit: 1 = timer interrupt masked (disabled!. Set to 1 by reset.
TCR Bits 5,4,3,2, 1,0 read as "1s" - unused bits.

FIGURE 201a) -

I

TYPICAL OUTPUT MODE PORT CONNECTIONS

(CMOS Loads)

PA7

27

PA6

26

PB7

19

PA5

25

PB6

18

PA4

24

PA3

23

PA2

22

PAl

21

PAO

20

---

11 TTL Loadl

1.6mA

PB5

17

PB4

16

PB3

15

--.Ib
1.0mA

PB2

14

PBl

13

PBO

12

Port A, bit 7 and bit 4 programmed as output.
Bit 7 driving CMOS loads and bit 4 driving one
TTL load directly using CMOS output option.

-

Port B, bit 5 programmed as output. driving
Darlington-base directly.

+ V

+V
PB7

19

PB6

18

PB5

17

PB4

16

PC3

11

PB3

15

PC2

10

PB2

14

PB1

13

PBO

12

10mA
4-

\\

\\

PCl

9

PCO

8

CMOS
Inverters
MC140491 MC14069
(Typical)

~10mA

Port C, bits 0,3 programmed as output, driving
CMOS loads, using external pull up resistors.

Port B, bit 0 and bit 1 programmed as output,
driving LEDs directly.

3·265

MC6805P4

FIGURE 20(b) - TYPICAL INPUT MODE PORT CONNECTIONS

PB7

PA7

PB6

PA6
25
MC74LS04
(Typical)

PA5

MC74LS04
or
MC14069
(Typical)

17

PB5

16

PB4

15

PB3

24

PA4

23

PA3

22

PA2

14

PAl

13

PB2
PBl

PAO

12

PBO

TTL Driving Port A Directly

I

CMOS or TTL Driving Port B Directly

PC3

MC14069
(Typical)

PC2
PCl
PCO

MC74LS04
(Typical)

CMOS and TTL Driving Port C Directly

BIT MANIPULATION
The MC6805P4 MCU has the ability to set or clear any
single random access memory or input/output bit (except
the data direction register; see Caution under Input/Output
section) with a single instruction (BSET, BCLR). Any bit in
page zero including ROM, except the DDRs, can be tested,
using the BRSET and BRCLR instructions, and the program
branches as a result of its state. The carry bit equals the
value of the bit referenced by BRSET or BRCLR. A Rotate
instruction may then be used to accumulate serial input data
in a RAM location or register. The capability to work with

any bit in RAM, ROM, or I/O allows the user to have individual flags in RAM or to handle I/O bits as control lines.
The coding example in Figure 21 illustrates the usefulness
of the bit manipulation and test instructions. Assume that
the MCU is to communicate with an external serial device.
The external device has a data ready signal, a data output
line, and clock line to clock data one bit at a time, LSB first,
out of the device. The MCU waits until the data is ready,
clocks the external device, picks up the data in the carry flag
(C bit), clears the clock line, and finally accumulates the data
bit in a RAM location.

FIGURE 21 - BIT MANIPULATION EXAMPLE

SELF

MCU
Ready ..
Serial
Device

__Clock

-

2,PORTA,SELF

BSET
BRCLR
BCLR
ROR

1,PORTA
O,PORTA,CONT
1,PORTA
RAMLOC

a
1 R
T

Data ..

BRSET

-2 P
OA

-

CONT

3-266

MC6805P4

ADDRESSING MODES
The MC6805P4 MCU has 10 addressing modes which are
explained briefly in the following paragraphs. For additional
details and graphical illustrations, refer to the M6805 Family
User's Manual.
The term "effective address" (EA) is used in describing the
address modes. EA is defined as the address from which the
argument for an instruction is fetched or stored.
IMMEDIATE

In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The immediate addressing mode is used to access constants which
do not change during program execution (e.g., a constant
used to initialize a loop counter).
DIRECT

In the direct addressing mode, the effective address of the
argument is contained in a single byte following the opcode
byte. Direct addressing allows the user to directly address
the lowest 256 bytes in memory with a single 2-byte instruction. This includes the on-chip RAM and I/O registers and
128 bytes of ROM. Direct addressing is an effective use of
both memory and time.
EXTENDED

In the extended addressing mode, the effective address of
the argument is contained in the two bytes following the opcode. Instructions using extended addressing are capable of
referencing arguments anywhere in memory with a single
3-byte instruction. When using the Motorola assembler, the
programmer need not specify whether an instruction uses
direct or extended addressing. The assembler automatically
selects the shortest form of the instruction.
RELATIVE

The relative addressing mode is only used in branch instructions. In relative addressing, the contents of 'the 8-bit
signed byte following the opcode (the offset) is added to the
PC if and only if the branch condition is true. Otherwise,
control proceeds to the next instruction. The span of relative
addressing is from -126 to + 129 from the opcode address.
The programmer need not worry about calculating the correct offset when using the Motorola assembler, since it
calculates the proper offset and checks to see if it is within
the span of the branch.
INDEXED, NO OFFSET

In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. Thus, this addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is often used to move a pointer through a
table or to hold the address of a frequently referenced RAM
or I/O location.
INDEXED, 8-BIT OFFSET

an n element table. With this 2-byte instruction, k would
typically be in X with the address of the beginning of the
table in the instruction. As such, tables may begin anywhere
within the first 256 addressable locations and could extend
as far as location 510 ($1 FE is the last location at which the
instruction may begin).
INDEX, 16-BIT OFFSET

In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit
index register and the two unsigned bytes following the opcode. This addressing mode can be used in a manner similar
to indexed, 8-bit offset, except that this 3-byte instruction
allows tables to be anywhere in memory. As with direct and
extended addressing, the Motorola assembler determines
the shortest form of indexed addressing.
BIT SET/CLEAR
In the bit set/ clear addressing mode, the bit to be set or
cleared is part of the opcode, and the byte following the opcode specifies the direct address of the byte in which the
specified bit is to be set or cleared. Thus, any read/write bit
in the first 256 locations of memory, including I/O, can be
selectively set or cleared with a single 2-byte instruction. See
Caution under the Input/Output section.
BIT TEST AND BRANCH

The bit test and branch addressing mode is a combination
of direct addressing and relative addressing. The bit and condition (set or clear) which is to be tested is included in the opcode, and the address of the byte to be tested is in the single
byte immediately following the opcode byte. The signed
relative 8-bit offset is in the third byte and is added to the
value of the PC if the branch condition is true. This single
3-byte instruction allows the program to branch based on the
condition of any readable bit in the first 256 locations of
memory. The span of branching is from -125 to + 130 from
the opcode address. The state of the tested bit is also
transferred to the carry bit of the condition code register.
See Caution under the Input/ Output section.
INHERENT

In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, as well as control instruction with no other
arguments, are included in this mode. These instructions are
one byte long.

INSTRUCTION SET
The MC6805P4 MCU has a set of 59 basic instructions,
which when combined with the 10 addressing modes produce 207 usable opcodes. They can be divided into five different types: register/memory, read-modify-write, branch,
bit manipulation, and control. The following paragraphs
briefly explain each type. All the instructions within a given
type are presented in individual tables.

In the indexed, 8-bit offset addressing mode, the effective
address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode.
This addressing mode is useful in selecting the kth element in

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One
operand is either the accumulator or the index register. The

3-267

I

MC6805P4

other operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to
subroutine (JSR) instructions have no register operands.
Refer to Table 1.

BIT MANtf'ULATION INSTRUCTIONS
These instructions are used on any bit in the first 256 bytes
of the memory (see Caution under Input/Output section).
One group either sets or clears. The other group performs
the bit test branch operations. Refer to Table 4.

READ-MODIFY-WRITE INSTRUCTIONS
These instructions read a memory location or a register,
modify or test its contents, and write the modified value
back to memory or to the register (see Caution under Input/Output section). The test for negative or zero (TST) instruction is included in the read-modify-write instructions
though it does not perform the write. Refer to Table 2.

I

CONTROL INSTRUCTIONS
The control instructions control the MCU operations during program execution. Refer to Table 5.

ALP't1ABETICAL LISTING
The complete instruction set is given in alphabetical order
in Table 7.

BRANCH INSTRUCTIONS

OPCOOE MAP SUMMARY

The branch instructions cause a branch from the program
when a certain condition is met. Refer to Table 3.

Table 7 is an opcode map for the instructions used on the
MCU.

3-268

MC6805P4

TABLE 1 -

REGISTER/MEMORY INSTRUCTIONS
AddressIOq Modes

Direct

Extended

Indexed
(No Offset)

Indexed
(8·8it Offset)

Indexed
(16·Bit Offset)

Op
Code 8ytes Cycles

Op
Code Bytes Cycles

Op
Code Bytes Cycles

Op
#
Code Bytes Cycles

OP
Code Bytes Cycles

Immediate

Function

Op
Mnemonic Code Bytes Cycles
LOA

A6

Load X from Memory

LOX

AE

Store A In Memory

STA

Load A from Memory

F6

1

BE

CE

FE

1

B7

C7

F7

86

2

C6

06

E6

EE

O~

E7

07

Store X In Memory

STX

BF

CF

FF

EF

OF

Add Memory to A

ADD

AB

BB

CB

FB

EB

DB

AOC

A9

B9

C9

F9

E9

09

SUB

AO

BO

CO

FO

EO

DO

Add Memory and
Carry to A

Subtract Memory
Subtract Memory from
A with Borrow

SBC

A2

B2

C2

F2

E2

02

AND Memory to A

AND

A4

B4

C4

F4

E4

04

OR Memory wIth A

ORA

AA

BA

CA

FA

EA

OA

Exclusive OR Memory
with A

EaR

A8

B8

CB

FB

EB

DB
01

Arithmetic Compare A
with Memory

CMP

At

B1

C1

F1

El

Arithmetic Compare X
with Memory

CPX

A3

B3

C3

F3

E3

03

Bit Test Memory with
A (LogIcal Compare)

BIT

A5

B5

C5

F5

E5

05

Jump Unconditional

JMP

BC

CC

FC

EC

DC

Jump to Subroutine

JSR

BO

CD

FO

ED

DO

Indexed
(No Offset)

Indexed
(8 Bit Offset)

II
II
Op
Code Bytes Cycles

/I
/I
Op
Code Bytes Cycles

TABLE 2 -

READ-MODIFY-WRITE INSTRUCTIONS
Addressing Modes

Inherent (A)

Function

II
Op
II
Mnemonic Code Bytes Cycles

Inherent (X)

Direct

Op
II
II
tI
II
Op
Code Bytes Cycles Code Bytes Cycles

Increment

INC

4C

1

4

5C

1

4

3C

2

6

7C

6

6C

Decrement

DEC

4A

1

4

5A

1

4

3A

2

6

7A

1

6

6A

2

7

Clear

CLR

4F

1

4

5F

1

4

3F

2

6

7F

1

6

6F

2

7

Complement

COM

43

1

4

53

1

4

33

2

6

73

1

6

63

2

7

Negate
(2'5 Complement)

NEG

40

1

4

50

1

6

70

1

6

60

2

7
7

1

2

7

30

2

Rotate Left Thru Carry

ROL

49

1

4

59

1

4

39

2

6

79

1

6

69

2

Rotate RIght Thru Carry

ROR

46

1

4

56

1

4

36

2

6

76

1

6

66

2

7

LogIcal ShIft Left

LSL

4B

1

4

5B

1

4

38

2

6

78

1

6

68

2

7

4

LogIcal ShIft RIght

LSR

44

1

4

54

1

4

34

2

6

74

1

6

64

2

7

ArithmetIC ShIft RIght

ASR

47

1

4

57

1

4

37

2

6

77

1

6

67

2

7

Test for Negative
or Zero

TST

40

1

4

50

1

4

3D

2

6

70

1

6

60

2

7

3-269

I

MC6805P4

TABLE 3 -

BRANCH INSTRUCTIONS
Relative Addressing Mode
Mnemonic

Op
Code

#

#

Bytes

Cycles

Branch Always

BRA

20

2

4

Branch Never

BRN

21

2

Branch IFF Higher

BHI

22

2

4
4

Branch IFF Lower or Same

BLS

23

2

4

BCC
IBHS)

24

2

4

24

2

4

BCS
IBLO)

25

2

4

25

2

4

Branch IFF Not Equal

BNE

26

2

Branch IFF Equal

BEQ

27

2

4
4

Function

Branch IFF Carry Clear
IBranch IFF Higher or Same)
Branch IFF Carry Set
IBranch IFF Lower)

I

Branch IFF Half Carry Clear

BHCC

28

2

4

Branch IFF Half Carry Set

BHCS

29

2

Branch IFF Plus
Branch IFF Minus

BPL

2A

2

4
4

BMI

2B

2

4

Branch IFF Interrupt Mask Bit is Clear

BMC

2C

2

Branch IFF Interrupt Mask Bit is Set

BMS

2D

2

Branch IFF Interrupt Line is Low

BIL

2E

2

4
4
4

Branch IFF Interrupt Line is High

BIH

2F

2

Branch to Subroutine

BSR

AD

2

TABLE 4 -

4
8

BIT MANIPULATION INSTRUCTIONS
Addressing Modes
Bit Setl Clear

Bit Test and Branch

#

#

Bytes

Cycles

3

10

3

10

-

-

-

-

-

-

Branch IFF Bit n is Set

BRSETnln=O

7)

-

-

-

Op
Code
2-n

Branch IFF Bit n is Clear

BRCLR n (n=O .7)
BSET n (n=O .. 7)
BCLR n (n= O. .7)

-

--

-

01 + 2-n

10+ 2-n

2

11 + 2-n

2

7
7

Mnemonic

Function

Set Bit n
Clear Bit n

TABLE 5 -

Op
Code

#

#

Bytes

Cycles

CONTROL INSTRUCTIONS
Inherent

Function

#

#

Mnemonic

Op
Code

Bytes

Cycles
2

Transfer A to X

TAX

97

1

Transfer X to A

TXA

9F

1

2

Set Carry Bit

SEC

99

1

2

Clear Carry Bit

CLC

98

1

2

Set Interrupt Mask Bit

SEI

9B

1

2

Clear Interrupt Mask Bit

CLI

9A

1

2

Software Interrupt

SWI

83

1

11

Return from Subroutine

RTS

81

1

6

Return from Interrupt

RTI

80

1

9

Reset Stack POI"ter

RSP

9C

1

2

No-Operation

NOP

90

1

2

3-270

MC6805P4

TABLE 6 - INSTRUCTION SET
Addressing Modes

Condition Code
Bit

Mnemonic Inherent Immediate

ADC
ADD
AND
ASL
ASR
BCC
BCLR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
BIL
BIT
BLO
BLS
BMC
BMI
BMS
BNE
BPL
BRA
BRN
BRCLR
BRSET
BSET
BSR
CLL
CLI
CLR
CMP
COM
CPX
DEC
EOR
INC
JMP
JSR
LOA
LOX
LSL
LSR
NEO
NOP
ORA
ROL
RSP

Direct

Bit
Indexed
Indexed Indexed Setl Test &
Extended Relative (No Offset) (B Bits) (16 Bits) Clear Branch
X
X
X
X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X
X

X
X
X
X
X
X
X
X

X

X

X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X

X

X
X
X
X
X
X
X
X

X

X

X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X

X

X

X

X

X

X

X
X

X

X

X
X
X
X
X
X
X
X
X
X
X

X
X

X
X
X
X
X
X
X

X

Condition Code Symbols:
H Half Carry (From Bit 3)
Interrupt Mask
N Negative (Sign Bit)
Z Zero

X
X

1\ 1\

1\

1\ 1\

•

1\ 1\

X

X

1\

1\

1\

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1\
1\

•
•
0

•
•
1\

1\ 1\

1

1\

1\

1\

1\

1\

1\ 1\

1\ 1\

X
X
X
X

C Carry/Borrow
II Test and Set if True, Cleared Otherwise
• Not Affected

3-271

1\

1

X

C

1\ 1\

1\ 1\

X

X

N Z

1\ 1\

X

X

I

•
•
••
••
••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
• •0 • •
• •0 •
••
••
••
••
••
••
••
••••
••••
••
••
••
•• 0
••
••••
••
••
••••
1\

1\ 1\

X

X

H

1\ 1\

/\

1\

1\

1\

•
•
•
•
•
•
•
1\

1\

1\

1\ 1\

1\

1\

1\

1\

1\

•
•
1\

•

I

MC6805P4

TABLE 6 -

INSTRUCTION SET (CONTINUED)

Addressing Modes

Condition Code

Bit
Indexed
Indexed Indexed Setl Test &
Extended Relative (No Offset) (8 Bits) (16 Bits) Clear Branch
Bit

Mnemonic Inherent Immediate
RTI

X

RTS

X
X

SBC
SEC

X

SEI

X

X

X

X

X

X

X

X

X

X

X

STX

X

X

X

X

X

X

X

X

X

X

X

SWI

X

TAX

X

TST

X

TXA

X

H

I N Z
? ? ? ?

C

•• • •
••
••••
• ••
••
••
••
• ••
•• • •
••
••••
1\ 1\

•
1\

1

STA
SUB

I

Direct

1\ 1\

1\ 1\

1\ 1\

1

X

X

Condition Code Symbols:
H Half Carry (From Bit 3)
I Interrupt Mask
N Negative (Sign Bit)
Z Zero

X

C Carry/Borrow
/\ Test and Set if True, Cleared Otherwise
• Not Affected
? Load CC Register From Stack

3·272

1\ 1\

?

1

•
•
•
•
•
•
•
1\

3:

(")

TABLE 7 -

0)

M6805 HMOS FAMILY OPCODE MAP

CO

Bit Manipulation
8TB
Bse

Low
~

ri1
1

0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
B
1000

9

1001

(..)

N
.......

(..)

It,O

1~'
lfoo
D
1101
E
1110

F

1111

~

10
:iBRSEJla
10
BRCLRO
BTB
3
10
BRSE
3
JiB
10

Branch
REL

~,
7

OO~O

4

LBSE1~c ~ BR~~L
7

2

IR

INH

OO~,
6

2

4

NE~'R

1

01~

Read/Modify/Write
IXl
INH
5
0101

NEG
INH

1

NEG
INH

NEG
2

1

NEG

IX

1

RTI

17

INH

6

1

2
2

4

6

4

2 COM
DIR

1

10
BRSET2
BTB
3
10
BRCLR2
3
BTB
10
BRSE
3
JiB
10

2 BLS
REL

7

4

4

2 BSE~~c

6

2 BCC
REL

2 LSR
DTR

1

7

4

2

3BRCL~T3B
10

7

BCL~~c

2 BCS
REI

7

4

COMA
INH

1

COMX
INH

1

LSRX
INH

LSR
2

6

4

4

7

2 BNEREI

2 ROR
DIR

RORA
1
INH

RORX
1
INH

2 ROR

7

4

6

4

4

7

2 BCL~~c

2 BEQ
-.lill

BSE~~c

4

BSE~~c

2

ASR
DIR

1

ASRA
INH

1

ASRX
INH

2

6

4

4

LSLA
1
INH

LSLX
1
INH

2
7

LSL

2 BHCC
REL

2

4

6

4

4

2

ROL
2
DIR

ROLA
INH
1

ROLX
1
INH

4

4

7

2 BSE~~c

6

4

2

7

BPL
2
REL

DEC
DIR
2

DECA
1
INH

DECX
1
INH

2

7

4

6

4

4

7

3BRCL~.,6B

2 BCL~~c

10
3BRSET7
BTB
10
BRCLR7
3
BTB

2

7

4

BCLR5
BSC

7

BHC~EL

BSET6
BSC

2

2

7

4

BCLR7
2
BSC

BMC
REL

4

BSET7
2
BSC

COM

IX

1

SWI
INH

LSR

IX

6

IX1

1

ROR

IX

6

ASR

IX1

1

IX

1
2

IX1

1

LSL

IXI

1

IX

6

DEC

IX1

1

2

DIR

6

BMS
REL
BIL

TST
2

DIR

DEC

IX

1

INCA
INH

1

INCX
INH

4

4

TSTA
1
INH

TSTX
1
INH

6

INC
2

IX1

7

1

INC

IX

6

TST
2

IX1

1

TST

IX

REL

4

CLR
2

DIR

CLRA
1
1NH

7

4

1

CLRX

\!'J~ ~2,-----__ ~

1

CLR

IX

- - -

-

-

Inherent
Immediate
Direct
Extended
Relative
Bit Setl Clear
Bit Test and Branch
Indexed (No Offset)
Indexed, 1 Byte (S-Bit) Offset
Indexed,2 Byte (l6-Bit) Offset

4

2

CPX
DIR

4

2

AND
DIR

4

2

BIT

DIR

4

LDA
2
DIR

2
2

EO~MM

2

EOR
DIR

IX2

6

STA
EXT

3

IX2

2
5

IX2

2
5

6

CPX
3
6

BIT IX2

6

3

IX2

3

IXI

IX2

EOR

IX2

IXI

BIT IXI

2

IXI

STA
2
5

IXI

EOR

" ADD
3
IX2
5
JMP
3
IX2

b

JSR

8

8

NOP
1
INH

BSR
2
REL

2

2

4

LDX
IMM
2

LDX
DIR
2
5
STX
DIR
2

2

4

JMP
DIR

3

JSR

8

JSR
3
EXT

9

, LDX
3
EXT

6

7

D1R

JMP
EXT

STX
EXT
3

3

IX2
LDX

3

2
5

IXI

, ADD
3
EXT

ADD
DIR

IX2

IXI

ADD

2
JMP
2

IX2

IX

4
0100

AND
1
1
1
5
1
1

BIT IX

O,~,

LDA

IX

6
0110

IX

7
0111

IX

B
1000

STA
EOR

9

IX

1001
A
1010

ADD

1

IX

B
1011

IXI

C
1100

IXI

/ JSR
1
IX

D
1101

4

IXI
STX

1

ADC

• ORA
1
IX
4

LDX

2
2

3
0011

CPX

, JMP
1
IX

JSR

2

STX
3

1

IXI

4

6

6

IX

1

4

2

5

IX

2
0010

4

' ORA
IXI
2

2

1

ADC
IX2

0001

SBC

4

LDA

3

ADC

IX

CMP

I

4

" ORA
IX2
3

ORA
DIR
2

6

rk

4

6

STA

IX

4

IXI

, ORA
EXT
3

4

3

2
5
2
5

1

4

AND
IX2

LDA

CMP
IXI

CPX

AND
3
6

SUB
4

SBC

6

EOR
EXT

2
5

SBC

IX1

ADC
EXT
3

3

TXA
1
1NH

CMP
3

SUB

3
5

2

ADD
IMM

6

2
5

~

1111
4

ADC
DIR
2

4

2

,X2

7

6

3
5

3 SUB

3

F

1110
5

4

ADC
IMM
2
2
ORA
IMM
2

IXI

j 1~

1
5
1

LDX
STX

IX

E
1110

IX

1111

F

LEGEND

Abbreviations for Address Modes
INH
IMM
DIR
EXT
REL
BSC
BTB
IX
IXl
IX2

SBC
2
DIR

4

2

6

CLR

CMP
DIR

SEC
1
INH
2
CLI
INH
1
2
SEI
INH
1
2
RSP
1
INH

REL
6

BIH
2

INC

2

2
ROL

SUB
3
EXT
5
CMP
EXT
3
5
SBC
EXT
3
5
CPX
EXT
3
5
AND
EXT
3
5
BIT
3
EXT
5
LDA
EXT
3

5 STA
2
DIR

TAX
INH
CLC
INH

IX

6

ROL

SUB
2
DIR

4

2

ASR

6

BMI
REL

2
4

7

DIR

1

LSL

7

2

IXI

7

2 BCL~~c

rSEJie
10
BRCLR4
3
BTB
10
BRSE
3
JiB
10
BRCLR5
BTB
3
10
BRSET6
BTB
3
10

1
6

4

7

11

6

COM
IXI

7

4

LSRA
INH

2

en

IX

E

1101
6

5

2

!Xl

0

C
1100

4
4

CMP
IMM

SBC
IMM
2
2
CPX
IMM
2
2
AND
IMM
2
2
2 BIT
IMM
2
LDA
IMM
2

2 BHIREL

7

2 BCL~1c

B

SUB
IMM

1X2

EX

DIR
1011

2

RTS
INH

4

2 BSE~1c

2

IX1

IMM
A
1010
2

9

BRN
REL

2

3BRCL~T1B

2

01~1
6

4

BCLRO
BSC

7

2

IX

01~0

7

4

o

Register/ Memory

Control
INH
INH
9
8
1000
1001

1:' 1;;

# of eyol..
Moomooio
Bytes

4

~

1

SUI

IX

O,ood. '0 H"'''C;m.'
Opcode in Binary

WUU --' - - - - - - - - - - Address Mode

"'U
~

MC6805P4

ORDERING INFORMATION
The information required when ordering a custom MCU is
listed below. The ROM program may be transmitted to
Motorola on EPROM(s) or an MOOS disk file.
To initiate a ROM pattern for the MCU, it is necessary to
first contact your local Motorola representative or Motorola
distributor.

signed, and returned to Motorola. The signed verification
form constitutes the contractual agreement for creation of
the customer mask. If desired, Motorola will program on
blank EPROM from the data file used to create the custom
mask and aid in the verification process.

EPROMs

ROM VERIFICATION UNITS (RVUs)
Ten MCUs containing the customer's ROM pattern will be
sent for program verification. These units will have been
made using the custom mask but are for the' purpose of
ROM verification only. For expediency they are usually unmarked, packaged in ceramic, and tested only at room
temperature and 5 volts. These RVUs are included in the
mask charge and are not production parts. The RVUs are
thus not guaranteed by Motorola Quality Assurance, and
should be discarded after verification is completed.

The MCM2716 or MCM2532 type EPROMs, programmed
with the customer program (positive logic sense for address
and data), may be submitted for pattern generation. The
EPROM must be clearly marked to indicate which EPROM
corresponds to which address space. The recommended
marking procedure is illustrated below:

xxx

I

FLEXIBLE DISKS

The disk media submitted must be single-sided, singledensity, 8-inch, MOOS compatible floppies. The customer
must write the binary file name and company name on the
disk with a felt-tip pen. The minimum MOOS system files, as
well as the absolute binary object file (filename LO type of
file) from the M6805 cross assembler, must be on the disk.
An object file made from a memory dump using the
ROLLOUT command is also acceptable. Consider submitting
a source listing as well as the following files: filename, LX
(EXORciser loadable format) and filename, SA (ASCII
Source Code). These files will of course be kept confidential
and are used 1) to speed up the process in-house if any problems arise, and 2) to speed up the user-to-factory interface if
the user finds any software errors and needs assistance
quickly from Motorola factory representatives.
MOOS is Motorola's Disk Operating system available on
development of systems such as EXORciser, EXORset, etc.

080

xxx = Customer 10
After the EPROM(s) are marked, they should be placed in
conductive IC carriers and securely packed. Do not use
styrofoam.
VERIFICATION MEDIA

All original pattern media (EPROMs or floppy disk) are filed for contractual purposes and are not returned. A computer listing of the ROM code will be generated and returned
along with a listing verification form. The listing should be
thoroughly checked and the verification form completed,

GENERIC INFORMATION
Package Type

Frequency (MHz)

Temperature

Generic Number

Ceramic
L SuffiX

1.0

O°C to 70°C

MC6805P4L

Plastic
P SuffiX

1.0

O°C to 70 D C

MC6805P4P

Cerdlp
S SuffiX

1.0

O°C to 70°C

MC6805P4S

3·274

MC6805P4

MC6805P4 MCU CUSTOM ORDERING INFORMATION
Date _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Customer PO Number _ _ _ _ _ _ _ _ _ __
Customer Company _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Motoro!a Part Numbers

MC _ _ _ _ _ _ __
Address _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SC _ _ _ _ _ _ __
City,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ State _ _ _ _ _ _ _ _ _ _ _ _ Zip _ _ _ _ __
Country _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Phone _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Extension _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Customer Contact Person _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Customer Part Number _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

OPTION LIST
Select the options for your MCU from the following list. A
manufacturing mask will be generated from this information

Timer Clock Sc,urce
Internal 2 clock
o TIMER input pin

Internal Oscillator Input
Crystal
o Resistor

o

Timer Prescaler
o 20 (divided
21 (divided
22 (divided
o 23 (divided
o 24 (divided
o 25 (divided
o 26 (divided
27 (divided

o
o

o

by
by
by
by
by
by
by
by

o

11
21
41
81
161
321
641
1281

Low Voltage Inhibit
Disable
o Enable

o

Port A Output Drive
CMOS and TTL
TTL Only

o
o

Port B Output Drive

o TTL
o Open Drain

Standby RAM
08 Bytes
o 32 Bytes
64 Bytes
o 112 Bytes

o

Port C Output Drive
TTL
Open Drain

o
o

Pattern Media (All other media requires prior factory approval. I

o

o
o

EPROMS (MCM2716 or MCM25321

Floppy Disk
Other _ _ _ _ _ _ __

Clock Freq. _ _ _ _ _ _ _ _ _ _ _ __
Temp. Range _________________

0 0 to + 70 D C (Standardl

Marking Information (12 Characters Maximuml

Title _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Signature _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

3·275

I

®

MC680SP6

MOTOROLA
Advance Information

HMOS
(HIGH DENSITY
NCHANNEL. SILICON-GATE
DEPLETION LOAD)

8-BIT MICROCOMPUTER UNIT

I

The MC6805P6 Microcomputer Unit (MCU) is a member of the
M6805 Family of low-cost single-chip microcomputers. This 8-bit
microcomputer contains a CPU, on-chip CLOCK, ROM, RAM, 1/0, and
TIMER, It is designed for the user who needs an economical microcomputer with the proven capabilities of the M6800-based instruction set.
The following are some of the hardware and software highlights of the
MC6805P6 MCU.
HARDWARE FEATURES

• 8-Bit Architecture
• 64 Bytes of RAM
• Memory Mapped 1/0

8-BIT
MICROCOMPUTER

~SUFFIX

CERAMJC PACKAGE
CASE 719

• 1796 Bytes of User ROM
• 20 TTL/CMOS Compatible Bidirectional 1/0 Lines (8 Lines are
LED Compatible)
• On-Chip Clock Generator
• Self-Check Mode
• Zero CrOSSing Detection
• Master Reset
• Complete Development System Support on EXORciser

CASE 710

• 5 V Single Supply
SOFTWARE FEATURES

• Similar to M6800 Family
• Byte Efficient Instruction Set

S SUFFIX

• Easy to Program
• True Bit Manipulation
• Bit Test and Branch Instruction

CERDIP PACKAGE
CASE 733

• Versatile Interrupt Handling

PIN ASSIGNMENT

• Versatile Index Register

VSS

• Powerful Indexed AddreSSing for Tables
• Full Set of Conditional Branches
• Memory Usable as RegisterlFlags
• Single Instruction Memory ExaminelChange

INT

• 10 Powerful Addressing Modes
• All AddreSSing Modes Apply to ROM, RAM, and 1/0
USER SELECTABLE OPTIONS

• Internal 8-Bit Timer with Selectable Clock Source (External Timer
Input or Internal Machine Clock)
• Timer Prescaler Option (7 Bits, 2n)
• 8 Bidirectional 1/0 Lines with TTL or TTL/CMOS Interface Option
• Crystal or Low-Cost Resistor Oscillator Option

VCC

PA7
PA6

EXTAL

PA5

XTAL

PA4

NUM
TIMER

PA2

ThiS document contains Information on a new product. SpeCifications and information herein
are subject to change Without notice

3-276

PA3

pca

PAl

PCl

PAa

PC2

PB7
PB6
PB5

PC3
PBa

• Low Voltage Inhibit Option
• Vectored Interrupts: Timer, Software, and External
• Port B Open Drain Drive Option

RESET

PB1

PB4

PB2

PB3

MC6805P6

FIGURE 1 - MC6805P6 HMOS MICROCOMPUTER BLOCK DIAGRAM

TIMER

Data
Dir.
Reg

Port
B
Reg.

PBO
PBl
PB2 Port
PB3
B
PB4 1/0
PB5 Lines
PB6
PB7

Data
Dir.
Reg.

Port
C
Reg.

PCO Port
PCl
C
PC2 1/0
PC3 Lines

Accumulator
A

CPU
Control

Index
Register

PAO
PAl
Port PA2
A
PA3
1/0 PA4
Lines PA5
PA6
PA7

Port
A
Reg.

Data
Dir.
Reg.

X
Condition
Code
Register CC

CPU

Stack
Pointer

SP
Program
Counter
High PCH
1796 x 8
User ROM
116 X 8 SelfCheck ROM

AlU

Program
Counter
low PCl

MAXIMUM RATINGS
Rating

Symbol

Value

Unit

Supply Voltage

VCC
Yin
TA
Tstg

-0.3 to + 7.0
-0.3 to + 7.0

V

Input Voltage (Except Pin 61
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Plastic

V

01070

DC

-55 to + 150

DC

150
TJ .

Ceramic
Cerdip

DC

175
175

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields, however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit. For proper operation it is
recommended that Yin and V out be constrained to the range V SS oS (Vin or Voutl
oS V Cc. Reliability of operation is enhanced if
unused inputs are tied to an appropriate logic
voltage level (e.g., either VSS or VCCI.

THERMAL CHARACTERISTICS
Characteristic

Symbol

Value

Unit

°JA

72
50
60

DC/W

Thermal Resistance
Plastic
Ceramic
Cerdlp

POWER CONSIDERATIONS
The average chip-junction temperature, T j, in °c can be obtained from:
(1)

Tj=TA+(PDelljA)
Where:
T A = Ambient Temperature, °c
lIjA'" Package Thermal Resistance, junction-to-Ambient, °C/W
PD E PINT + PPORT
PINT'" ICC x VCe. Watts -

Chip Internal Power

PPORTE Port Power Dissipation, Watts -

User Determined

For most applications PPORT~PINT and can be neglected, PPORT may become significant if the device is configured to
drive Darlington bases or sink LED loads.
An approximate relationship between PD and T j (if PPORT is neglected) is:
PD = K -+- (T j -\: 273°C)

(2)

Solving equations 1 and 2 for K gives:
K= PDe(TA + 273°C) +lIjAePD 2

(3)

Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known T A. Using this value of K the values of PD and T j can be obtained by solving equations (1) and (2) iteratively for any
value of T A.

3-277

I

MC6805P6

ELECTRICAL CHARACTERISTICS (VCC= +5.25 Vdc ±5.0 Vdc, VSS=O Vdc, TA=O° to 70°C unless otherwise noted).
Characteristic
Input High Voltage
RESET (4.75,sVCC,s5.75)
(Vce<4.75)
INT (4.75,sVCC,s5.75)
(VCC<4.75)
All Other

Symbol

Min

VIH

4.0
VCC-0.5
4.0
VCC-0.5
2.0

Input High Voltage Timer
Timer Mode
Self-Check Mode

VIH

Input Low Voltage
INT
All Other

VIL

Typ
-

-

*
*

-

Max

Unit

Vce
VCC
VCC
VCC
VCC

V

10.0

VCC+l
15.0

V

VSS
VSS

*

1.5
0.8

V

-

4.0
2.0

V

2.0

fi'E'SEi

I

Hysteresis Voltage (See Figures 10, 11, and 12)
"Out of Reset"
"Into Reset"

INT Zero Crossing Input Voltage, Through a Capacitor
Internal Power Dissipation - No Port Loading VCC=5.75 V, TA=O°C
Input Capacitance
XTAL
All Other

2.1
0.8
2.0

-

4.0

PINT

-

400

690

Vac p-p
mW

Cin

-

25
10

-

pF

-

Low Voltage Recover
Low Voltage Inhibit

O°C to 70°C
- 40°C to 85°C

Input Current (External Capacitor Charging Current)
TIMER (Vin=O.4 V)
INT (Vin= 2.4 V to V CC)
EXT AL (Vin = 2.4 V to V CC, Crystal Option)
(Vin=O.4 V, Crystal Option)
RESET (Vin=0.8 V)

* Due

VIRES+
VIRES VINT

-

-

VLVR

-

-

4.75

V

VLVI

2.75
3.1

3.5
3.5

-

V

lin

-

-

-

20

-

-4.0

-

-

20
50
10
-1600
-40

/LA

to Internal biaSing, this Input (when unused) floats to approximately 2.0 Vdc.

PORT DC ELECTRICAL CHARACTERISTICS (VCC= +5.25 Vdc +05
Vdc, VSS=O Vdc, TA=Oo to 70°C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

Port A with CMOS Drive Enabled
Output Low Voltage, ILoad= 1.6 mA

VOL

-

-

0.4

V

Output High Voltage, ILoad= -100 /LA

VOH

2.4

-

Output High Voltage, ILoad = - 10 /LA

VOH

-

-

V

-

VCC
0.8

V

V

Input High Voltage, ILoad= -300 /LA (max.)

VIH

VCC-l
2.0

Input Low Voltage, ILoad= -500 /LA (max.)

VIL

VSS

Hi-Z State Input Current (Vin=2.0 V to VCC)

IIH

-

-300

/LA

IlL

-

-

-500

/LA

Output Low Voltage, ILoad = 3.2 mA

VOL

-

-

0.4

V

Output Low Voltage, ILoad= 10 rnA (sink)

VOL

-

-

1.0

V

Output High Voltage, ILoad= -200 /LA

VOH

2.4

-

Darlington Current Drive (Source), Vo = 1.5 V

IOH

-1.0

-

-10

mA

Input High Voltage

VIH

2.0

-

VIL

VSS

-

VCC
0.8

V

Input Low Voltage

-

2

10

/LA
V

Hi-Z State Input Current (Vin = 0.4 V)

V

Port B

Hi-Z State Input Current

ITSI
Port C and Port A with CMOS Drive Disabled

-

V

V

Output Low Voltage, ILoad= 1.6 mA

VOL

-

-

0.4

Output High Voltage, ILoad= -100 /LA

VOH

2.4

-

-

V

Input High Voltage

VIH

2.0

-

V

Input Low Voltage

VIL

VSS

-

VCC
0.8

Hi-Z State Input Current

ITSI

-

2

10

/LA

Output High Voltage

VOH

2.4

-

13.0

V

Hi-Z State Input Current

ITSI

-

2

20

/LA

V

Port B with Open-Drain Option

See MC68(7)05 Series Data Sheet for port I/V curves and Input protection schematiCs.

3-278

MC6805P6

SWITCHING CHARACTERISTICS (VCC= +5 25 Vdc ±O 5 Vdc VSS=O Vdc TA=O°C to 70°C unless otherwise noted)
Symbol
Min
Typ
Max
Characteristic
Oscillator Frequency
0.4
4.2
MC6805P6
0.4
6.0
MC68A05P6
losc
8.0
MC68B05P6
0.4
10
095
Cycle Time (4/fos c )
tcyc
INT and TIMER Pulse Width (See INTERRUPTS)
tWL,tWH
tcyc+ 25O
RESET Pulse Width
tRWL
tcyc+ 25O
RESET Delay Time (External Capacitance= 1.0 p.F)
100
tRHL
INT Zero Crossing Detection Input Frequency
0.03
1.0
liNT
External Clock Input Duty Cycle (EXT AU
50
60
40
FIGURE 2 - TIL EQUIVALENT TEST LOAD FIGURE 3 (PORT B)

MHz
p's
ns
ns
ms
kHz
%

CMOS EQUIVALENT TEST LOAD FIGURE 4 - TIL EQUIVALENT TEST LOAD
(PORT A)
(PORTS A AND C)

VCC=575 V

VCC=575V
Test
Point

Test
Point

MMD615Q
or Equiv.

TestPoint~

40 pF
(Totall

Unit

130 pF !Totall

125 kill MMD7000
or EqUiv.

30 pF
!Totall

SIGNAL DESCRIPTION

24kll

2.97 kll
MMD7000
or Equiv.

INPUT/OUTPUT LINES (PAO-PA7, PBO-PB7, PCO-PC3)

The input and output signals for the MCU are described in
the following paragraphs.
Vcc AND VSS
Power is supplied to the MCU using these two pins. VCC
is power and VSS is the ground connection.

iNT
This pin provides the capability for asynchronously applying an external interrupt to the MCU. Refer to Interrupts section for additional information.
XTAL AND EXTAL

These pins provide connections to the on-chip clock
oscillator circuit. A crystal, a resistor, or an external signal,
depending on the user selectable manufacturing mask option, can be connected to these pins to provide a system
clock source with various stability I cost tradeoffs. Lead
lengths and stray capacitance on these two pins should be
minimized. Refer to Internal Clock Generator Options section
for recommendations about these inputs.
TIMER

This pin allows an external input to be used to decrement
the internal timer circuitry. Refer to Timer section for additional information about the timer circuitry.

RESE'f
This pin allows resetting of the MCU at times other than
the automatic resetting capability already in the MCU. Refer
to Resets section for additional information.

These 20 lines are arranged into two 8-bit ports (A and B)
and one 4-bit port (Cl. All lines are programmable as either
inputs or outputs under software control of the data direction registers. Refer to Inputs/Outputs section for additional
information.

MEMORY
As shown in Figure 5, the MCU is capable of addressing
2048 bytes of memory and I/O registers with its program
counter. The MC6805P6 MCU has implemented 1984 of
these locations. This consists of: 1796 bytes of user ROM,
116 bytes of self-check ROM, 64 bytes of user RAM, 6 bytes
of port I/O, and 2 timer registers.
The stack area is used during the processing of interrupt
and subroutine calls to save the processor state. The register
contents are pushed onto the stack in the order shown in
Figure 6. Because the stack pointer decrements during
pushes, the low order byte (PCL) of the program counter is
stacked first; then the high order three bits (PCH) are
stacked. This ensures that the program counter is loaded
correctly, during pulls from the stack, since the stack pointer
increments during pulls. A subroutine call results in only the
program counter (PCl, PCH) contents being pushed onto
the stack. The remaining CPU registers are not pushed.

CENTRAL PROCESSING UNIT
The CPU of the M6805 Family is implemented independently from the I/O or memory configuration. Consequently, it can be treated as an independent central processor communicating with I/O and memory via internal address, data, and control buses.

REGISTERS
NUM

This pin is not for user application and must be connected
to VSS.

3-279

The M6805 Family CPU has five registers available to the
programmer. They are shown in Figure 7 and are explained in
the following paragraphs.

•

MC6805P6

FIGURE 5 - MCU ADDRESS MAP

o
000
Page Zero
Access with
Short
Instructions

127
128

Page Zero
User ROM
(128 Bytes)

255
256

7654321

$000

1/0 Ports
Timer
RAM
(128 Bytes)

0

PortA

1

Port B

2

$07F
$080

[

1 1 1 1

Not Used

$003

Port A DDR

$004*

Port B DDR
Not Used

I

~~~

Interrupt
Vectors

~

2041
2042
2043
2044
2045
2046
2047

Self Check
ROM
(116 Bytes)
Timer Interrupt

r------External Interrupt
r------SWI

1------Reset

$783
$784

$005*

IPort C DDR

$006*

7

Not Used

$007

8

Timer Data Reg

$008

9

Timer Control Reg

$009
$OOA

10
1923
1924

$002

3

6

Main User
ROM
(1668 Bytes)

$001
Port C

4

5

$100

I

$000

Not Used
(54 Bytes)

63
64

$03F
$040

RAM
164 Bytes)
$7F7
$7F8
$7F9
$7FA
$7FB
$7FC
$7FD
$7FE
$7FF

Stack
(31 Bytes
Maximum)

t

127

$07F

* Caution: Data direction registers (DDRs) are write-only; they read as $FF.

FIGURE 7 - PROGRAMMING MODEL

FIGURE 6 - INTERRUPT STACKING ORDER
6
n-4

11

5
1

4

I

3

2

Condition
Code Register

o

Pull

o

7

I

A _ _ _ _--', Accumulator
'--_ _ _ _ _

n+1

o
X
'--_________
--'1

n-3

Accumulator

n+2

n-2

Index Register

n+3

,'--_PCH
_ _'--_ _ _ _PCl
_ _ _ _ _--',

n+4

10

n -1

1 11 11
PCl*

I

PCH*

n+5

I

I

Index Register

o

8 7

10

I

Program Counter

o

5 4

0 , 0 0 , 0
SP_ _
L---L--'-_'----'--'-_'---_
111
__

--->I

Stack Pointer

Push
Condition Code Register
*For subroutine calls, only PCl and PCH are stacked.
Carry/Borrow
Zero

ACCUMULATOR (A)
The accumulator is a general purpose 8-bit register used to
hold operands and results of arithmetic calculations or data
manipulations.

' - - - - - Negative
~-----

Interrupt Mask

' - - - - - - - - Half Carry

3-280

MC6805P6

INDEX REGISTER (X)

ZERO (Z) - Used to indicate that the result of the last
arithmetic, logical, or data manipulation was zero.

The index register is an 8-bit register used for the indexed
addressing mode. It contains an 8-bit value that may be
added to an instruction value to create an effective address.
The index register can also be used for data manipulations
using the read-modify-write instructions. The index register
may also be used as a temporary storage area.

CARRY/BORROW (C) - Used to indicate that a carry or
borrow out of the arithmetic logic unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions plus Shifts and rotates.

TIMER

PROGRAM COUNTER (PC)
The program counter is an 11-bit register that contains the
address of the next instruction to be executed.
STACK POINTER (SP)
The stack pointer is an 11-bit register that contains the address of the next free location on the stack. Initially, the
stack pointer is set to location $07F and is decremented as
data is pushed onto the stack and incremented as data is
pulled from the stack. The six most significant bits of the
stack pointer are permanently configured to 000011. During
an MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set to location $07F. Subroutines and interrupts may be nested down to location $061 (31 bytes maximum) which allows the programmer to use up to 15 levels of
subroutine calls.
CONDITION CODE REGISTER (CC)
The condition code register is a 5-bit register in which four
bits are used to indicate the results of the instruction just executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each individual condition code register bit is explained in the following paragraphs.
HALF CARRY (H) - Set during ADD and ADC instructions to indicate that a carry occurred between bits 3 and 4.
INTERRUPT (I) - This bit is set to mask (disable) the
timer and external interrupt (lNT). If an interrupt occurs
while this bit is set, the interrupt is latched and is processed
as soon as the interrupt is cleared.
NEGATIVE (N) - Used to indicate that the result of the
last arithmetic, logical, or data manipulation was negative
(bit 7 in result equal to a logical one).

The MC6805P6 MCU timer circuitry is shown in Figure 8.
The 8-bit counter may be loaded under program control and
IS decremented toward zero by the clock input (prescaler
output). When the timer reaches zero, the timer interrupt request bit (bit 7) in the timer control register (TCR) is set. The
timer interrupt can be masked (disabled) by setting the timer
interrupt mask bit (bit 6) in the TCR. The interrupt bit (! bit) in
the condition code register also prevents a timer interrupt
from being processed. The MCU responds to this interrupt
by saving the present CPU state on the stack, fetching the
timer interrupt vector from locations $7F8 and S7F9, and executing the interrupt routine; see the Interrupts section. THE
TIMER INTERRUPT REOUEST BIT MUST BE CLEARED BY
SOFTWARE.
The clock input to the timer can be from an external
source (decrementing of timer counter occurs on a positive
transition of the external source) applied to the TIMER input
pin or it can be the internal 2 signal. The maximum frequency of a signal that can be recognized by the TIMER or INT pin
logic is dependent on the parameter labeled tWL, tWH. The
pin logic that recognizes the high (or low) state on the pin
must also recognize the low (or high) state on the pin in
order to "re-arm" the internal logic. Therefore, the period
can be calculated as follows: (assumes 50/50 duty cycle for a
given period)
tcyc x 2 + 250 ns = period =

The period is not simply tWL + tWH. This computation is
allowable, but it does reduce the maximum allowable frequency by defining an unnecessarily longer period (250 ns
twice).
When the 2 signal is used as the source, it can be gated
by an input applied to the TIMER input pin allowing the user
to easily perform pUlse-width measurements. (NOTE: For
ungated 2 clock inputs to the timer prescaler, the TIMER

FIGURE 8 - TIMER BLOCK DIAGRAM

rJ>2
(Internall

Timer
TIMER
Input
Pin

r------:
:
:

L _____ l

Manufacturing
Ma~k

Options

Write

~

freq

Read

Write
Internal Data Bus

3-281

Read

I

MC6805P6

pin should be tied to Vce) The source of the clock input is
one of the mask options that is specified before manufacture
of the MCU.
A prescaler option can be applied to the clock input that
extends the timing interval up to a maximum of 128 counts
before decrementing the counter. This prescaling mask option is also specified before manufacture.
The timer continues to count past zero, falling through to
$FF from zero and then continuing the count. Thus, the
counter can be read at any time by reading the timer data
register (TOR) This allows a program to determine the
length of time since a timer interrupt has occurred and not
disturb the counting process.
At power-up or reset, the prescaler and counter are Initialized with all logical ones, the timer interrupt request bit
(bit 7) is cleared, and the timer interrupt mask bit (bit 6) is
set.

I

low voltage detect circuit; see Figure 10. The internal circuit
connected to the RESET pin consists of a Schmitt trigger
which senses the RESET line logic level. The Schmitt trigger
provides an internal reset voltage if it senses a logic "0" on
the RESET pin. During power-up, the Schmitt trigger
switches on (removes reset) when the RESET pin voltage
rises to VIRES +. When the RESET pin voltage falls to a
logical "0" for a period longer than one tcyc, the Schmitt
trigger switches off to provide an internal reset voltage. The
"switch off" voltage occurs at VIRES _. A typical reset
Schmitt trigger hysteresis curve is shown in Figure 11.
During power-up, a delay of tRHL is needed before allowing the RESET input to go high. This time allows the internal
clock generator to stabilize. Connecting a capacitor to the
RESET input, as shown in Figure 12, typically provides sufficient delay. See Figure 16 under Interrupts section for the
complete reset sequence.

SELF-CHECK
INTERNAL CLOCK GENERATOR OPTIONS

The self-check capability of the MC6805P6 MCU provides
an internal check to determine if the part is functional. Connect the MCU as shown in Figure 9 and monitor the output
of port C bit 3 for an oscillation of approximately 7 Hz. A
9-volt level on the TIMER input, pin 7, energizes the ROMbased self-check feature. The self-check program exercises
the RAM, ROM, TIMER, interrupts, and I/O ports.

The internal clock generator circuit is designed to require a
minimum of external components. A crystal, a resistor, a
Jumper wire, or an external Signal may be used to generate a
system clock with various stability/cost tradeoffs. A
manufacturing mask option is required to select either the
crystal oscillator or the RC oscillator circuit. The oscillator
frequency IS internally divided by four to produce the internal
system clocks.
The different connection methods are shown in Figure 13.
The crystal specifications and suggested PC board layouts

RESETS
The MCU can be reset three ways: by initial power-up, by
the external reset input (RESET), and by an optional internal

FIGURE 9 -

SELF-CHECK CONNECTIONS

INT

MC6805P6

PA7 t-2_7_-+-_ _ _....
PA6 t-2_6_ _ _---.

28 RESET

1\0----.---------*
:c1.0'"

4

PA5 t-2_5_ _--,
PA4 24

XTAL

EXTAL

PA3 t-2_3_-+--i_+--'
PA2 t-2_2_-+--+--,
PA 1 t-2_1_-+--,
PAO 20

+ 10V

10 k

7

TIMER

6

NUM

---"''''\1-----;

PB7 19

Vec

PB6 1-1_8_-+--,
PB5 1-1;....7_-+--+--,
PB41-1..;.6_-+--+_+-...,
PB3 15

5100

~~~~~~~--~PCO

t-~5Jl0'v0"v_---+l~--_1 PC 1
t-~5Jl0V°"v_-+l~~-~PC2

PB2 1-1_4_ _--'

~....J\51,,0./'0\r_-+tI~~ PC3
Vcc= Pin 3

PBO 1-1_2_ _ _ _ _.....

PB 1 1-1_3_ _ _--1

VSS=Pinl

* This connection depends on the clock oscillator user selectable mask option.
Use crystal if crystal option is selected.

3-282

MC6805P6

capacitance, Ie parameters, ambient temperature, and supply voltage. To ensure rapid oscillator startup, neither the
crystal characteristics nor the load capacitance should exceed recommendations.

are given in Figure 14. A resistor selection graph is given in
Figure 15.
The crystal oscillator startup time is a function of many
variables: crystal parameters (especially RS), oscillator load

FIGURE 10 -

POWER AND RESET TIMING

5 V
VCC

RESET
Pin

II

Internal
Reset

FIGURE 11 - TYPICAL RESET SCHMITT
TRIGGER HYSTERESIS

FIGURE 12 -

Out
Of
Reset

POWER-UP RESET DELAY CIRCUIT

V CC -JVV'v----i---,

I

10 /LF

Part Of
MC6805P6
MCU
In
Reset

I

0.8 V

2V

4 V

FIGURE 13 -

CLOCK GENERATOR OPTIONS

XTAL

XTAL
(See Notel CJ
CL

::::::c

MC6805P6
EXTAL
MCU
(Crystal Mask
Optionl

EXTAL

Approximately 25% to 50% Accuracy
Typical tcyc= 1.25 /Ls
External Jumper

Crystal

+5V
_,,,,,,_ _ XTAL

XTAL
External
Clock
Input

MC6805P6
MCU
(Resistor Mask
Option I

EXTAL

MC6805P6
MCU
(Crystal Mask
Optionl

MC6805P6
(See Figure 151

EXTAL

No
Connection

MCU
(Resistor Mask
Optionl

Approximately 10% to 25% Accuracy
External Resistor
(Excludes Resistor Tolerencel

External Clock

NOTE: The recommended CL value with a 4.0 MHz crystal is 27 pF, maximum, including system distributed capacitance There is an internal
capAcitance of approximately 25 pF on the XTAL pin. For crystal frequencies other than 4 MHz, the total capacitance on each pin
should be scaled as the Inverse of the frequency ratio. For example, with a 2 MHz crystal, use approximately 50 pF on EXT AL and
approximately 25 pF on XT AL. The exact value depends on the Motional-Arm parameters of the crystal used

3-283

MC6805P6

FIGURE 15 - TYPICAL FREQUENCY SELECTION FOR
RESISTOR OSCILLATOR OPTION

FIGURE 14 - CYRSTAL MOTIONAL ARM PARAMETERS
AND SUGGESTED PC BOARD LAYOUT
8.0

(a)

Crystal Parameters

7.0

Cl

EXTAL~~XTAL
4

-~C~

AT - Cut Parallel Resonance Crystal
Co =7 pF Max.
Freq.=4.0 MHz @ CL =24 pF
RS = 50 ohms Max.

5

N
I

~
>-

6.0

u
c

5.0

f

40

gJ

~

3.0

'u 2.0

0

1.0
0

II

VCC=525V
T A =25°C

0

10

20

30
40
50
Resistance IkOl

60

70

80

(b)

INTERRUPTS

(c)

NOTE: Keep crystal leads and circuit

The MC6805P6 MCU can be interrupted three different
ways: through the external interrupt (INT) input pin, the internal timer interrupt request, or the software interrupt instruction (SWI). When any interrupt occurs: processing is
suspended, the present CPU state is pushed onto the stack,
the interrupt bit (I) in the condition code register is set, the
address of the interrupt routine is obtained from the appropriate interrupt vector address, and the interrupt routine
is executed. Stacking the CPU registers, setting the I bit, and
vector fetching requires a total of 11 tcyc periods for completion.
A flowchart of the interrupt sequence is shown in
Figure 16. The interrupt service routine must end with a
return from interrupt (RTI) instruction which allows the MCU
to resume processing of the program prior to the interrupt
(by unstacking the previous CPU state). Unlike RESET,
hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the
current instruction execution is complete.
When the current instruction is complete, the processor
checks all pending hardware interrupts and if unmasked,
proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Note that masked interrupts are latched for later interrupt service.
If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed as any other instruction.
The external interrupt is internally synchronized and then
latched on the falling edge of INT. A sinusoidal input Signal
(fINT maximum) can be used to generate an external interrupt, as shown in Figure 17(a), for use as a zero-crossing
detector. This allows applications such as serviCing time-ofday routines and engaging/ disengaging ac power control
devices.
For digital applications, the INT pin can be driven by a
digital Signal. The maximum frequency of a signal that can
be recognized by the TIMER or INT pin logic is dependent on
the parameter labeled tWL, tWH. The pin logic that
recognizes the high (or low) state on the pin must also
recognize the low (or high) state on the pin in order to "re-

connections as short as possible

3-284

MC6805P6

FIGURE 16 -

RESET AND INTERRUPT PROCESSING FLOWCHART

1-1 (in CC)
07F- SP
O-DDRs
CLR TNT Logic
FF- Timer
7F-Prescaler
7F- TCR

Stack
PC, X, A, CC

Timer
Load PC From
SWI
7FC/7FD
INT
7FA /7FB
TIMER. 7F8 /7F9

Put 7FE on
Addless Bus

Fetch
Instruction

Load PC
Irom
7FE17FF

N
Execute All
Instruction
Cycles

FIGURE 17 -

TYPICAL INTERRUPT CIRCUITS
(b) Digital-Signal Interrupt

(a) Zero-Crossing Interrupt

VCC
ac Input
(liNT Max.)
R,,;l mil
ac Input ~
lOV acp _p

(Current

~Limiting)

2

INT

MC6805P6
MCU

R
0.1-1.0

"F

TTL 4.7 k
Level
Digital---a...-;:;.j INT
Input

lJ

3-285

MC6805P6
MCU

I

MC6805P6

regardless of the logic levels at the output pin due to output
loading; see Figure 18. When port B is programmed for outputs, it is capable of sinking 10 mA and sourcing 1 mA on
each pin.
All input/output lines are TTL compatible as both inputs
and outputs. Ports Band C are CMOS compatible as inputs.
Port A may be made CMOS compatible as outputs with a
mask option. The address map in Figure 5 gives the address
of data registers and DDRs. The register configuration is provided in Figure 19 and Figure 20 provides some examples of
port connections.

arm" the Internal logic, Therefore,. the period can be
calculated as follows: (assumes 50/50 duty cycle for a given
period)

,

1

tcyc x 2 + 250 ns = period = freq
The period is not simply tWL + tWH, This computation is
allowable, but it does reduce the maximum allowable frequency by defining an unnecessarily longer period (250 ns
twice), See Figure 17(b),
A software interrupt (SWI) is an executable instruction
which is executed regardless of the state of the I bit in the
condition code register. Note that if the I bit is zero SWI executes after the other interrupts. SWls are usually used as
break-points for debugging or as system calls.

Caution
The corresponding DDRs for ports A, B, and Care
write-only registers (registers at $004, $005, and $006).
A read operation on these registers is undefined. Since
BSET and BCLR are read-modify-write functions, they
cannot be used to set or clear a DDR bit (all "unaffected" bits would be set). It is recommended that all
DDR bits in a port be written using a Single-store instruction.

INPUT /OUTPUT
There are 20 input/output pins. The INT pin may also be
polled with branch instructions to provide an additional input
pin. All pins (port A, B, and C) are programmable as either
inputs or outputs under software control of the corresponding data direction register (DDR). The port I/O programming
is accomplished by writing the corresponding bit in the port
DDR to a logic" 1" for output or a logic "0" for input. On
reset, all the DDRs are initialized to a logic "0" state to put
the ports in the input mode. The port output registers are not
initialized on reset but may be written to before setting the
DDR bits to avoid undefined levels. When programmed as
outputs, the latched output data is readable as input data,

I

The latched output data bit (see Figure 18) may always be
written. Therefore, any write to a port writes all of its data
bits even though the port DDR is set to input. This may be
used to initialize the data registers and avoid undefined outputs; however, care must be exercised when using readmodify-write instructions since the data read corresponds to
the pin level if the DDR is an input ("0") and corresponds to
the latched output data when the DDR is an output ("1").

FIGURE 18 - TYPICAL PORT I/O CIRCUITRY

Data
Direction Register
Bit*
(/)

c

co

.Q

OJ

OJ

c
~
()

-C
-

C
C

0

u

Latched
Output
Data
Bit

Data
Direction
Register
Bit
1
1
0

Output
Data
Bit
0
1
X

Output
State
0
1
Hi-Z* *

*DDR is a write-only register and reads as all "1s".
* * Port A (with CMOS drive disabled), B, and C are three state ports. Port A has optional internal pullup devices
to provide CMOS drive capability. See Electrical Characteristics table for complete information.

3-286

Input
To
MCU
0
1
Pin

MC6805P6

FIGURE 19 -

MCU REGISTER CONFIGURATION

PORT DATA REGISTER

PORT DATA DIRECTION REGISTER IDDRI

Port A Addr= $000
Port B Addr= $001
Port C Addr= $002 IBlts 0---31

III Write Only; reads as all "ls"
121 1 = Output; 0= Input. Cleared to 0 by reset.
131 Port A Addr = $004
Port B Addr = $005
Port C Addr= $006 IBits 0---31
TIMER DATA REGISTER lTORI

TIMER CONTROL REGISTER ITCRI
5

4

3

2

L--.....L-~I_l----Ll_l_lL....-l--L1_l----Ll_l--'---I1 $009

MSB

LSB

1$008

TCR7 - Timer Interrupt Status Bit: Set when TOR goes
to zero; must be cleared by software. Cleared to
o by reset.
TCR6 Bit 6- Timer Interrupt Mask BIt: 1 = timer interrupt masked (disabledl. Set to 1 by reset
TCR Bits 5, 4,3,2,1.0 read as "ls" - unused bits.

I

FIGURE 20(a) - TYPICAL OUTPUT MODE PORT CONNECTIONS

(CMOS Loads)

PA7

27

PA6

26

PB7

19

PA5

25

PB6

18

PA4

24

PA3

23

PA2

22

PAl

21

PAD

20

.-

(1 TTL Load)

1.6mA

PB5

17

PB4

16

PB3

15

PB2

14

PBl

13

PBO

12

Port A, bit 7 and bit 4 programmed as output
Bit 7 driving CMOS loads and bit 4 driving one
TTL load directly using CMOS output option

---. Ib
1.0mA
2N6386lTypicall

Port B, bit 5 programmed as output, driving
Darlington-base directly.

+ V
PB7

19

PB6

18

PB5

17

PB4

16

PB3

15

PB2

14

PBl

13

PBO

12

+ V

PC3

11

PC2

10

PCl

CMOS
Inverters
MC140491 MC14069
(Typicall

PCO
'-10mA

Port B, bit 0 and bit 1 programmed as output,
driving LEOs directly.

Port C, bits 0-3 programmed as output, driving
CMOS loads, using external pullup resistors.

3-287

MC6805P6

FIGURE 2O(b) -

TYPICAL INPUT MODE PORT CONNECTIONS

PB7

PA7
PA6
MC74LS04
(Typical)

.

25

PA5

24

PA4

23

PA3

22

PA2

MC74LS04
or
MC14069
(Typical)

.

PB6
17

PB5

16

PB4

15

PB3

14

PB2

PAl

PBl

PAO

PBO

TTL driving port A directly.

CMOS or TTL driving port B directly.

I

11

PC3

10

PC2
PCl

8

PCO

!Typical)
CMOS and TTL driving port C directly.

SOFTWARE
BIT MANIPULATION
The MC6805P6 MCU has the ability to set or clear any
single random access memory or inputloutput bit (except
the data direction register, see Caution under InputlOutput
section), with a single instruction (BSET, BCLR). Any bit in
page zero including ROM, except the DDRs, can be tested,
using the BRSET and BRCLR instructions, and the program
branches as a result of its state. The carry bit equals the
value of the bit referenced by BRSET or BRCLR. A rotate instruction may then be used to accumulate serial input data in
a RAM location or register. The capability to work with any

FIGURE 21 -

bit in RAM, ROM, or 1/0 allows the user to have individual
flags in RAM or to handle 1/0 bits as control lines.
The coding example in Figure 21 illustrates the usefulness
of the bit manipulation and test instructions. Assume that
the MCU is to communicate with an external serial device.
The external device has a data ready signal, a data output
line, and a clock line to clock data one bit at a time, LSB first,
out of the device. The MCU waits until the data is ready,
clocks the external device, picks up the data in the carry flag
(C bit), clears the clock line, and finally accumulates the data
bit in a RAM location.

BIT MANIPULATION EXAMPLE

SELF

MCU

Ready _
Serial
Device

-

BRSET

2,PORTA,SELF

BSET
BRCLR
BCLR
ROR

I ,PORTA
O,PORTA,CONT
I ,PORTA
RAMLOC

2 P

Clock
Data _

a
1 R
T
OA

CONT

-

3-288

MC6805P6

ADDRESSING MODES
The MC6805P6 MCU has 10 addressing modes which are
explained briefly in the following paragraphs. For additional
details and graphical illustrations, refer to the M6805 Family
User's Manual.
The term "effective address" (EA) is used in describing the
address modes. EA is defined as the address from which the
argument for an instruction is fetched or stored.
IMMEDIATE - In the immediate addressing mode, the
operand is contained in the byte immediately following the
opcode. The immediate addressing mode is used to access
constants which do not change during program execution
(e.g., a constant used to initialize a loop counterl.
DIRECT - In the direct addressing mode, the effective address of the argument is contained in a single byte following
the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single
2-byte instruction. This includes the on-chip RAM and I/O
registers and 128 bytes of ROM. Direct addressing is an effective use of both memory and time.
EXTENDED - In the extended addressing mode, the effective address of the argument is contained in the two bytes
following the opcode. Instructions using extended addressing are capable of referencing arguments anywhere in
memory with a single 3-byte instruction. When using the
Motorola assembler, the programmer need not specify
whether an instruction uses direct or extended addressing.
The assembler automatically selects the shortest form of the
instruction.
RELATIVE - The relative addressing mode is only used in
branch instructions. In relative addressing, the contents of
the 8-bit signed byte following the opcode (the offset) is added to the PC if and only if the branch condition is true. Otherwise, control proceeds to the next instruction. The span of
relative addressing is trom -126 to + 129 from the opcode
address. The programmer need not worry about calculating
the correct offset when using the Motorola assembler since
it calculates the proper offset and checks to see if it is within
the span of the branch.
INDEXED, NO OFFSET - In the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. Thus, this addressing mode
can access the first 256 memory locations. These instructions are only one byte long. This mode is often used to
move a pointer through a table or to hold the address of a
frequently referenced RAM or I/O location.
INDEXED, 8-BIT OFFSET - In the indexed, 8-bit offset
addressing mode, the effective address is the sum of the
contents of the unsigned 8-bit index register and the unsigned byte following the opcode. This addressing mode is
useful in selecting the kth element in an n element table.
With this 2-byte instruction, k would typically be in X with
the address of the beginning of the table in the instruction.
As such, tables may begin anywhere within the first 256 addressable locations and could extend as far as location 510
($1 FE is the last location at which the instruction may beginl.

3-289

INDEXED, 16-BIT OFFSET - In the indexed, 16-bit offset
addressing mode, the effective address is the sum of the
contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. This addressing mode
can be used in a manner similar to indexed, 8-bit offset, except that this 3-byte instruction allows tables to be anywhere
in memory. As with direct and extended addressing, the
Motorola assembler determines the shortest form of indexed
addressing.
BIT SET/CLEAR - In the bit set/clear addressing mode,
the bit to be set or cleared is part of the opcode, and the byte
following the opcode specifies the direct address of the byte
in which the specified bit is to be set or cleared. Thus, any
read/write bit in the first 256 locations of memory, including
I/O, can be selectively set or cleared with a single 2-byte instruction. See Caution under the Input/Output section.
BIT TEST AND BRANCH - The bit test and branch addressing mode is a combination of direct addressing and
relative addressing. The bit and condition (set or clearl which
is to be tested is included in the opcode, and the address of
the byte to be tested is in the single byte immediately fo~low­
ing the opcode byte. The signed relative 8-bit offset is in the
third byte and is added to the value of the PC if the branch
condition is true. This single 3-byte instruction allows the
program to branch based on the condition of any readable
bit in the first 256 locations of memory. The span of branching is from -125 to + 130 from the opcode address. The
state of the tested bit is also transferred to the carry bit of the
condition code register. See Caution under the Input/Output
section.
INHERENT - In the inherent addressing mode, all the information necessary to execute the instruction is contained
in the opcode. Operations speCifying only the index register
or accumulator, as well as control instruction with no other
arguments, are included in this mode. These instructions are
one byte long.
INSTRUCTION SET
The MC6805P6 MCU has a set of 59 basic instructions,
which when combined with the 10 addressing modes produce 207 usable opcodes. They can be divided into five different types: register/memory, read-modify-write, branch,
bit manipulation, and control. The following paragraphs
briefly explain each type. All the instructions within a given
type are presented in individual tables.
REGISTER/MEMORY INSTRUCTIONS - Most of these
instructions use two operands. One operand is either the accumulator or the index register. The other operand is obtained from memory using one of the addressing modes. The
jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operands. Refer to Table 1.
READ-MODIFY-WRITE INSTRUCTIONS - These instructions read a memory location or a register, modify or
test its contents, and write the modified value back to
memory or to the register (see Caution under Input/Output
section). The test for negative or zero (TST) instruction is included in read-modify-write instructions though it does not
perform the write. Refer to Table 2.

I

MC6805P6

BRANCH INSTRUCTIONS - The branch instructions
cause a branch from the program when a certain condition is
met. Refer to Table 3.

CONTROL INSTRUCTIONS - The control instructions
control the MCU operations during program execution.
Refer to Table 5.

BIT MANIPULA'JION INSTRUCTIONS - These instructions are used on any bit in the first 256 bytes of the memory
(see Caution under Input/Output section). One group either
sets or clears. The other group performs the bit test branch
operations. Refer to Table 4.

ALPHABETICAL LISTING - The complete instruction set
is given in alphabetical order in Table 6.
OPCODE MAP SUMMARY - Table 7 is an opcode map
for the instructions used on the M CU.

I

3-290

TABLE 1 -

s:

n

REGISTER/MEMORY INSTRUCTIONS

en

Addressing Modes
Direct

Extended

Op
#
#
Code Bytes Cycles

Op
#
#
Code Bytes Cycles

#
#
Op
Code Bytes Cycles

Immediate
Function

#
#
Op
Mnemonic Code 8ytes Cycles

Load A from Memory

LOA

A6

Load X from Memory

LOX

AE

Store A

In

Memory

STA

-

Store X

In

Memory

STX

--

2

CO

Indexed
lNo Offset)

2

B6

2

4

2

2

BE

2

--

-

B7

2

-

-

BF

AB

2

2

BB

F6

I

4

5

FE

I

6

F7

I

3

6

FF

3

5

FB

C6

3

5

4

CE

3

5

C7

3

2

5

CF

2

4

CB

Indexed
18-8it Offset)

Indexed
116-8it Offset)

Op
#
#
Code Bytes Cycles

#
#
OP
Code Bytes Cycles

E6

2

4

EE

5

E7

I

5

I

4

5

06

2

5

2

6

EF

2

EB

3

6

DE

3

6

07

3

7

6

OF

3

7

2

5

DB

3

6
6

Add Memory to A

ADD

Add Memory and
Carry to A

ADC

A9

2

2

B9

2

4

C9

3

5

F9

I

4

E9

09

3

SUB

AO

2

2

BO

2

4

CO

3

5

FO

I

4

EO

2
2

5

Subtract Memory

5

DO

3

6

Subtract Memory from
A with Borrow

SBC

A2

2

2

B2

2

4

C2

3

5

F2

I

4

E2

2

5

02

3

6

AND Memory to A

AND

A4

2

2

B4

2

4

C4

3

5

F4

I

4

E4

2

5

04

3

6

OR Memory with A

ORA

AA

2

2

BA

2

4

CA

3

5

FA

I

4

EA

2

5

DA

3

6

ExclUSive OR Memory
With A

EOR

A8

2

2

B8

2

4

C8

3

5

F8

I

4

E8

2

5

08

3

6

A"thmetlc Compare A
With Memory

CMP

Al

2

2

Bl

2

4

Cl

3

5

Fl

I

4

El

2

5

01

3

6

A"thmetlc Compare X
With Memory

CPX

A3

2

2

B3

2

4

C3

3

5

F3

I

4

E3

2

5

03

3

6

N

Bit Test Memory With
A lLoglcal Compare)

BIT

A5

2

2

B5

2

4

C5

3

5

F5

I

4

E5

2

5

05

3

6

-L

Jump Unconditional

JMP

-

-

-

BC

2

3

CC

3

4

FC

I

3

EC

2

4

DC

3

5

Jump to Subroutine

JSR

-

-

-

BD

2

7

CD

3

8

FO

I

7

ED

2

8

DO

3

9

VJ

<0

-

TABLE 2 -

READ-MODIFY-WRITE INSTRUCTIONS
Addressing Modes

Inherent lA)
Function

#
#
Op
Mnemonic Code Bytes Cycles

Inherent (X)

Indexed
(No Offset)

Direct

#
#
Op
#
#
Op
Code Bytes Cycles Code Bytes Cycles

Indexed
(8 Bit Offset)

#
Op
#
Code Bytes Cycles

#
#
Op
Code Bytes Cycles

Increment

INC

4C

I

4

5C

I

4

3C

2

6

7C

I

6

6C

2

7

Decrement

DEC

4A

I

4

5A

I

4

3A

2

6

7A

I

6

6A

2

7

Clear

CLR

4F

I

4

5F

I

4

3F

2

6

7F

I

6

6F

2

7

Complement

COM

43

I

4

53

I

4

33

2

6

73

I

6

63

2

7

Negate
(2's Complement)

NEG

40

I

4

30

2

6

70

1

6

60

2

7

Rotate Left Thru Carry

ROL

49

1

4

59

1

4

39

2

6

79

1

6

69

2

Rotate Right Thru Carry

ROR

46

I

4

56

1

4

36

2

6

76

I

6

66

2

7

Logical Shift Left

LSL

48

I

4

58

I

4

38

2

6

78

I

6

68

2

7

4

50

I

7

Logical Shift Right

LSR

44

54

I

4

34

2

6

74

64

2

7

47

4

57

I

4

37

2

6

77

1
1

6

ASR

1
1

4

Arithmetic Shift Right

6

67

2

7

Test for Negative
or Zero

TST

40

1

4

50

1

4

3D

2

6

70

1

6

60

2

7

..

o

CJ'I

."

en

I

MC6805P6

TABLE 3 -

BRANCH INSTRUCTIONS
Relative Addressing Mode
Mnemonic

Op
Code

#
Bytes

#
Cycles

Branch Always

BRA

20

2

4

Branch Never

BRN

21

2

4

Branch IFF Higher

BHI

22

2

4

Branch IFF Lower or Same

BLS

23

2

4

Branch IFF Carry Clear

BCC

24

2

4

(BHS)

24

2

4

BCS

25

2

4

(BlO)

25

2

4

BNE

26

2

4

Function

(BranchlFFHigher or Same)
Branch IFF Carry Set
(Branch IFF lower)
Branch IFF Not Equal
Branch IFF Equal

I

BEO

27

2

4

Branch IFF Half Carry Clear

BHCC

28

2

4

Branch IFF Half Carry Set

4

BHCS

29

2

BranchlFF Plus

BPl

2A

2

4

BranchlFF Minus

BMI

2B

2

4

Branch IFF Interupt Mask
Bit is Clear

BMC

2C

2

4

Branch IFF Interrupt Mask
Bit IS Set

BMS

20

2

4

Branch IFF Interrupt Line
is low

Bil

2E

2

4

Branch IFF Interrupt line
is High

BIH

2F

2

4

Branch to Subroutine

BSR

AD

2

8

TABLE 4 -

BIT MANIPULATION INSTRUCTIONS
Addressing Modes
Bit Set/Clear
Op
Code

Mnemonic

Function

#
Bytes

Bit Test and Branch

#
Cycles

Op
Code

#
Bytes

#

Cycles

Branch IFF Bit n is set

BRSET n (n = O.

7)

-

-

-

2-n

3

10

Branch IFF Bit n is clear

BRCLR n (n = 0

7)

-

-

-

01 + 2 - n

3

10

Set Bit n

BSET n (n = 0

7)

10+2.n

2

7

-

-

-

Clear bit n

BClR n (n = 0

7)

11 + 2 - n

2

7

-

-

-

TABLE 5 -

CONTROL INSTRUCTIONS
Inherent
#
#
Bytes
Cycles

Mnemonic

Op
Code

Transfer A to X

TAX

97

1

Transfer X to A

TXA

9F

1

2

Set Carry Bit

SEC

99

1

2

Clear Carry Bit

ClC

98

1

2

Set Interrupt Mask Bit

SEI

9B

1

2

Clear Interrupt Mask Bit

CLI

9A

1

2

Software Interrupt

SWI

83

1

11

Return from Subroutine

RTS

81

1

6

Return from Interrupt

RTI

80

1

9

Reset Stack POinter

RSP

2

NOP

9C
90

1

No-Operation

1

2

Function

3-292

2

MC6805P6

TABLE 6 -

INSTRUCTION SET

Addressing Modes

Mnemonic Inherent Immediate

Direct

Condition Code

Bit
Bit
Indexed
Indexed Indexed Set! TestS.
Extended Relative (No Offset) ·(B Bits) (16 Bits) Clear Branch

ADC

X

X

X

X

X

X

ADD

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

AND
ASl
ASR

X
X

BEG

X

BHCC

X

BHCS

X

BHI

X

BHS

X

BIH

X
X

BIL
X

BIT

X

X

X

BLO

X

BLS

X

BMC

X

BMI

X

BMS

X

BNE

X

BPL

X

BRA

X

BRN

X

X

X

X

BRSET

X

X

BSET
X

BSR
X

CLI

X

CLR

X

COM

X

DEC
INC

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X
X

X
X

EOR

X

X
X

X

CPX

X
X

X
X

CMP

X

X

X

JMP

X

X

X

X

X

X

X

X

X

X

X

LDX

X

X

X

X

X

X

X

X

X

X

LSR

X

X

X

X

NEG

X

X

X

X

NOP

X
X

ORA
ROL

X

RSP

X

X

X

X

Condition Code Symbols:
H Half Carry (From Bit 3)
Interrupt Mask
N Negative (Sign Bit)
Z Zero

X

X

X

X

/\ /\

•

/\ /\

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
/\

/\

•
•
0
•
•
/\
1

/\ /\

/\

/\ /\

/\ /\
/\ /\
/\

/\ /\

X

/\

/\

/\ /\

/\ /\

C Carry/ Borrow
II Test and Set if True, Cleared Otherwise
• Not Affected

3-293

/\

/\ /\

X

X

LSL

/\ /\

/\ /\

X

LDA

JSR

/\

/\

1

X

C

/\ /\

/\ /\

BRCLR

CLL

N Z

/\ /\

BClR
BCS

I

•
•
••
••
••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
• 0 •0 •
••
••
••
••
••
••
••
••••
••••
••
••
••0
••
••
••••
••
••
••••
/\

/\ /\

X

BCC

H

/\ /\

/\ /\

•
•
•
•
•
•
•
/\

/\
/\

•

•
/\

•

I

MC6805P6

TABLE 6 -

INSTRUCTION SET (CONTINUED)
Condition Code

Addressing Modes

Mnemonic Inherent Immediate
RTI

X

RTS

X
X

SBC
SEC

X

SEI

X

X

X

X

X

X

X

X

X

X

X

STX

X

X

X

X

X

X

X

X

X

X

X

SWI

X

TAX

X

TST

X

TXA

X

I N Z
? ? ? ?

H

C

•• • •
••""
••••
• ••
••""
••""
••
• •" •"
•• • •
••""
••••

•
"
•
•
•
•"
•
•
•

1

STA
SUB

I

Direct

Bit
Bit
Indexed Indexed Setl Test &
Indexed
Extended Relative (No Offset) (8 Bits) (16 Bits) Clear Branch

1

X

X

Condition Code Symbols:
H Half Carry (From Bit 3)
I Interrupt Mask
N Negative (Sign Bit)
Z Zero

X

C Carry/Borrow
1\ Test and Set if True, Cleared Otherwise
• Not Affected
? Load CC Register From Stack

3-294

?

1

3:

n

TABLE 7 Bit Manipulation
BTB
BSe

~

Low

~

13

1
0001

3

2
0010

3

0011
4
0100
5
0101
6
0110
7
0111
B
1000

(,.)

N

<0

(11

1~

9

1001

~

BRSE

JfR

10
BRCLRO
BTB
10
BRSET1
3
BTB
10
BRCLR1
3
BTB
10
BRSET2
3
BTB
10
BRCL
3
10
BRSE
3
10
BACL
3
10
13BRSET4
BTB
10
BACLR4
3
BTB

:ls
JJs

B
1011
C
1100

0

1101
E
1110

F

1111

?
7

~1
BSE~~e

ci,o
L BRAREL

,

4

BSE~le
BCL~1e
BSE~~e

7

BCL~~e

)

NEG
INH

L NEG

7

)
)

4

6

BLS
REI
BCC
REL

4

COMA
INH

7

COM X
INH

) COM
DIR

1

6

4

4

LSRA
1
INH

LSRX
1
INH

)

LS~TR

1

COM
1
6

)

:

2

IXl

I

LSR

IX

1

BSE1~e

2
4

BNEREL

~ BEG
-.Jill
4

2

BHCC

RFI

6

4

) ROA
DIR

1

4

AOAA
INH

1

SWI
INH

IX

)

ASAX
INH

)

ASA

7
?

LSL

6
2 ASA

4

6

4

4

LSL
2
DIR

LSLA
INH
1

LSLX
1
INH

DIR

1

4

ASRA
INH

1

4

4

2 BCL~~e

AOLA
1
INH

AOLX
1
It2
Clock
Ifosc+4)

fplN - Prescaler Input Frequency
fCIN - Counter Input Frequency

Timer

Timer Control Register Bits'
TIR - Timer Interrupt Request Status
TIM - Timer Interrupt Mask
TIN - Timer Input Select
TIE- Timer External Input Enable
PSC- Prescaler Clear
PS2, PS 1, PSO- Prescaler Select

Mask Option Register Bits
ClK - Clock Oscillator Type
TOPT - Timer Mask/Programmable Option
CLS - Timer Clock Source
P2, Pl ,PO- Prescaler Option

NOTE: The TOPT bit in the mask option register selects whether the timer is software programmable via the timer control register or
emulates the mask programmable parts via the MOR EPROM byte

Figure 5-3. MC68705R3/MC68705U3 Timer Block Diagram

..

iii
s:

n
0)

--CO
~

o

UI

lJ

c:
en
m
~
m

Timer Data Register ITORI
8- Bit Counter

en

Timer
Pin

Set
7-Blt Prescaler

c.u

ex>

Select

~_ _ _ _ _ _-----1ll-01-8

W
I\)

Timer Control Register ITCR)

Clear
Internal
2
Clock
Ifosc+41

fplN - Prescaler Input Frequency
fCIN - Counter Input Frequency

Timer Control Register Bits
TIR - Timer Interrupt Request Status
TIM - Timer Interrupt Mask
TIN - Timer Input Select
TIE - Timer External Input Enable
PS C - Prescaler Clear
PS2, PS 1, PSO - Prescaler Select

Mask Option Register Bits
ClK - Clock Oscillator Type
TOPT - Timer Mask/ Programmable Option
ClS - Timer Clock Source
(TIE) - (Timer External Input Enable)
SNM - Secure/Non-Secure Mode Option
P2, Pl, PO- Prescaler Option

NOTES: The TOPT bit in the mask option register selects whether the timer is software programmable via the timer control register or emulates
the mask programmable parts via the MaR PROM byte.
The TIE bit in the mask option register is not used if MaR TOPT = 1 I MC6805P2 emulation) It sets the intial value 01 TCR TIE if MaR
TOPT = 0

Figure 5-4. MC68705R5/MC68705U5 Timer Block Diagram

MC68(7)OSR/U SERIES

A prescaler option can be applied to the clock input that extends the timing interval up to a maximum of 128 counts before decrementing the counter. This prescaling TCR or MaR option selects
one of eight outputs on the 7-bit binary divider; one output bypasses prescaling. To avoid truncation errors, the prescaler is cleared when bit 3 (b3) of the TCR is written to a logic one; however,
TCR bit 3 always reads as a logic zero to ensure proper operation with read-modify-write instructions (bit set and clear for example).
At reset, the prescaler and counter are initialized to an all ones condition; the timer interupt request
bit (TCR, b7) is cleared and the timer interrupt request mask (TCR, b6) is set. TCR bits bO, b1, b2,
b4, and b5 are initialized by the corresponding mask option register (MaR) bits at reset. They are
then software selectable after reset (if the TOPT bit (b6) in the MORE is equal to zero).
Note that the timer block diagrams in Figures 5-3 and 5-4 reflect two separate timer control configurations: a) software controlled mode via the timer control register (TCR), and b) MaR controlled
mode to emulate a mask ROM version with the mask option register. In the software controlled
mode, all TCR bits are read/write, except bit b3 which is write-only (always reads as a logic zero). In
the MaR controlled mode, for all four devices, TCR bit b7 and b6 are read/write and bits b5, b4, b2,
b 1, and bO have no effect on a write (always read as logic ones). For the M C68705R3/ M C68705U3,
bit b3 is write-only (reads as logic zero), and for the MC68705R5/MC68705U5, bit b3 has no effect
on a write (reads as a logic one).
5.3.1 Software Controlled Mode

The TOPT (timer option) bit (b6) in the mask option register is EPROM programmed to a logic zero
to select the software controlled mode, which is described first. TCR bits b5, b4, b3, b2, b1, and bO
give the program direct control of the prescaler and input select options.
The timer prescaler input frequency (fPIN) can be configured for three different operating modes
plus a disable mode, depending upon the value written to TCR control bits b4 and b5 (TIE and TIN).
When the TIE and TIN bits are programmed to zero the timer input is from the internal clock (phase
two) and TIMER input pin is disabled. The internal clock mode can be used for periodic interrupt
generation as well as a reference for frequency and event measurement.
When TIE= 1 and TIN = 0, the internal clock and the TIMER input pin signals are ANDed to form the
timer input. This mode can be used to measure external pulse widths. The external pulse simply
gates in the internal clock for the duration of the pulse. The accuracy of the count in this mode is
plus or minus one count.
When TIE=O and TIN= 1, no prescaler input frequency is applied to the prescaler and the timer is
disabled.
When TIE and TIN are both programmed to a one, the timer is from the external clock. The external
clock can be used to count external events as well as provide an external frequency for generating
periodic interrupts.
Bits bO, b1, and b2 in the TCR are program controlled to choose the appropriate prescaler output.
The prescaling divides the prescaler input frequency by 1, 2, 4, etc. in binary multiplex to 128 producing counter input frequency to the counter. The processor cannot write into or read from the

3-329

I

MC68(7)OSR/U SERIES

prescaler; however, the prescaler is set to all ones by a write operation to TCR, b3 (when bit 3 of the
written data equals one), which allows for truncation-free counting.
5.3.2 MOR Controlled Mode

The MOR controlled mode of the timer is selected when the TOPT (timer option) bit (b6) in the
MOR is programmed to a logic one to emulate the MC6805R2 mask-programmable prescaler and
timer clock source. The timer circuits are the same as described above, however, the timer control
register (TCR) is configured differently, as discussed below.

I

The logic level for the functions of bits bO, b1, b2, and b5 in the TCR are all determined at the time
of EPROM programming. They are controlled by corresponding bits within the mask option register
(MOR, $F38l. The value programmed into MOR bits bO, b1, b2, and b5 controls the prescaler division and the timer clock selection. Bit b4 (TIE) is set to a logic one in the MOR controlled mode
(when read by software, these five TCR bits always read as logic ones). As in the software programmable configuration, the TIM (b6) and TIR (b7) bits of the TCR are controlled by the counter and
software as described above. Bit b3 of the TCR (in the MOR controlled mode) for the MC68705R31
MC68705U3 always reads as a logic zero and can be written to a logic one to clear the prescaler;
however, for the MC68705R51 MC68705U5 bit b3 is set to a logic one and when read by software
always reads as a logic one. The MOR controlled mode is designed to exactly emulate the
MC6805R2 which has only TIM, TIR, and PSC in the TCR and has the prescaler options defined as
manufacturing mask options.
5.3.3 Timer Control Register (TCR)

The configuration of the TCR is determined by the logic level of bit 6 (timer option, TOPT) in the
mask option register (MOR). Two configurations of the TCR are shown below, one for TOPT = 1
and the other for TOPT = O. TOPT = 1 configures the TCR to emulate the MC6805R2. When
TOPT=O, it provides software control of the TCR. When TOPT= 1, the prescaler "mask" options
are user programmable via the MOR. A description of each TCR bit is provided below (also see
Figures 5-3 and 5-4).
TCR with MOR TOPT = 1 (MC6805R2 Emulation)
b7

b6

b5

b4

b3

b2

b1

bO

Timer Control

TIR
TIM
! PSC* !
l !Register $009
*For the MC68705R3/MC68705U3 write only, reads as a zero-for the MC68705R5/MC68705U5
reads as a one and has no effect on the prescaler.
TCR with MOR TOPT = 0 (Software Programmable Timer)
b7

b6

b5

b4

b3

b2

b1
bO Timer Control
PS-1...,--pS-O---'!Register $009

r--- R-"'-T-I-M--r--- N--r-TI-E--r-I-PS-C-*'!-P-S-2--r--

TI
TI
*Write only, reads as a zero.
b7, TIR

Timer Interrupt Request - Used to initiate the timer interrupt or signal a timer data
register underflow when it is a logic one.
1 = Set when the timer data register changes to all zeros.
0= Cleared by external reset or under program control

3-330

MC68(7)OSR/U SERIES

b6, TIM

Timer Interrupt Mask - Used to inhibit the timer interrupt to the processor when it is a
logic one.
1 = Set by an external reset or under program control.
0= Cleared under program control.

b5, TIN

External or Internal - Selects the input clock source to be either the external TIMER (pin
8) or the internal phase two.
1 = Selects the external clock source.
0= Selects the internal phase two (fasc+4) clock source.

b4, TIE

External Enable - Used to enable the external TIMER (pin 8) or to enable the internal
clock (if TIN = OJ regardless of the external TIMER pin state (disables gated clock featurel.
When TaPT = 1, TIE is always a logic one.
1 = Enables external TIMER pin.
0= Disables external TIMER pin.
TIN-TIE MODES
TIN

o
o
1
1

TIE
0
1
0

CLOCK
Internal Clock (phase two)
Gated (AND) of External and Internal Clocks
No Clock
External Clock

b3, PSC Prescaler Clear - When TaPT = 0, this is a write-only bit. It reads as a logic zero so the
BSET and BCLR on the TCR function correctly. Writing a one into PSC generates a pulse
which clears the prescaler. When TaPT = 1, operation remains the same for the
MC68705R31 MC68705U3; however, for the MC68705R51 MC68705U5 this bit is always
read as a logic one and has no effect on the prescaler.
b2, PS2 Prescaler Select - These bits are decoded to select one of eight outputs on the timer preb1, PS1 scaler division resulting from decoding these bits.
bO, PSO
PS2

PS1

0
0
0
0
1
1
1
1

0
0
1
1
0
0

PSO Prescaler Division

0
1
0
1
0
1
0
1

1 (Bypass Prescaler)
2
4
8
16
32
64
128

NOTE
When changing the PS2-PSO bits in software, the PSC bit should be written to a one in
the same write cycle to clear the prescaler. Changing the PS bits without clearing the
prescaler may cause an extraneous toggle of the timer data register.

3-331

I

MC68(7)05R/U SERIES

SECTION 6
SELF-CHECK
The self-check capability of the MC6805R2, MC6805U2, MC6805R3, and MC6805U3 microcomputers provides an internal check to determine if the part is functional. Connect the MCU as shown
in Figure 6-1 and monitor the output of port C bit 3 for an oscillation of approximately 7 hertz. A
10-volt level (through a 10k resistor) on the timer input, pin 8, and pressing then releasing the
R"ESTI button, energizes the ROM-based self-check feature. The self-check program exercises the
RAM, ROM, TIMER, interrupts, and 1/0 ports, as well as the AID for the MC6805R2 and
MC6805R3.

I

Several of the self-check subroutines can be called by a user program with a JSR or 8SR instruction. They are the RAM, ROM, and four-channel AID tests. The timer routine may also be called if
the timer input is the internal phase two clock.
6.1 RAM SELF-CHECK SUBROUTINE

The RAM self-check is called at location $F6F for the MC6805R2/MC6805U2 and at location $F84
for the MC6805R31 MC6805U3. If any error is detected, it returns with the Z bit cleared; otherwise
the Z bit is set. The walking diagnostic pattern method is used.
The RAM test must be called with the stack pointer at $07F. When run, the test checks every RAM
cell except for $07F and $07E which are assumed to contain the return address.
The A and X registers and all RAM locations except $07F and $07E are modified.
6.2 ROM CHECKSUM SUBROUTINE

The ROM self-check is called at location $F8A for the MC6805R2/MC6805U2 and at location $F95
for the MC6805R3/MC6805U3. Ifany error is detected, it returns with the Z bit cleared; otherwise
Z = 1, X = 0 on return, and A is zero if the test passes. RAM locations $040 are overwritten.
6.3 ANALOG-TO-OIGITAL CONVERTER SELF-CHECK

The analog-to-digital self-check for the MC6805R2 is called at location $FA4 and for the MC6805R3
at $FAE. For both devices, it returns with the Z bit cleared if any error was found; otherwise the Z
bit is set.
The A and X register contents are lost. The X register must be set to four before the call. On return,
X = 8 and AI D channel 7 is selected. The AI D test uses the internal voltage references and confirms
port connections.

3-332

MC68(7)OSR/U SERIES

Il

--

RESET

1.

r

3

5

:r:

-

I~

-

A'"

LED..

*6

4~

=

~~n

EXTAL
XTAL

8

'ir"J.122VVV
... "y

PA5 ~

12...

PA4

PAl 34
33

PAO

32

PB7

31

PB6

11 PC2

PB5

~

12 PC3

PB4

~

PC4

PB3 28

~ PC5

PB2 27

15 PC6

PBl

~

16 PC7

PBO

F-

~

-

PD7

...!..§. PD6/11NT21

..L

36

PA2 35

10 PCl

.J.l

O.l I1 F

PA6

TIMER

9 PCO

~EDa....Lv)(.v~l~ n
LED .. 'l"'~12~"'''' v

...,

39

PA3

MHZ~ NUM (N/C)* *

10 k
LED ..... ~ ...

m

40

PA7

4 VCC

..L 1.01'F
-L't.

+5 .25V

+ 10V

1
VS·S
1.0 ...... 11FT 2 RESET

PD~

24

19 PD5

PD1 23

20 PD4

PD3 21

PD2 22

T

-L
* This connection depends on clock oscillator user selectable mask option. Use jumper if the RC mask option is selected.
* * For the MC6805R2/MC6805U2 pin 7 is not for user application and must be connected to VSS. For the MC6805R3/MC6805U3 pin T
is not connected.
LED Meanings
PCO

PCl

PC2

PC3 Remarks [1:LED ON; O:LED OFF)

1
0
1
0
1
0

0
1
0 Bad I/O
1
0
0 Bad Timer
1
0
0 Bad RAM
1
0
0 Bad ROM
0
Bad A/D
0
0
0
0
0 Bad I nterrupts or Request Flag
All Flashlnq
Good Device
Anything else bad Part Bad Port C, etc.

Figure 6-1. Self-Check Connections

3-333

I

MC68(7)OSR/U SERIES

6.4 TIMER SELF-CHECK SUBROUTINE

The timer self-check is called at location $FCF for the MC6805R21 MC6805U2 and at location $F6D
for the MC6805R3/MC6805U3. If any error was found, it returns with the Z bit cleared; otherwise
the Z bit is set.
In order to work correctly as a user subroutine, the internal phase two clock must be the clocking
source and interrupts must be disabled. Also, on exit, the clock is running and the interrupt mask is
not set so the caller must protect from interrupts if necessary.
The A and X register contents are lost. The timer self-check routine counts how many times the
clock counts in 128 cycles. The number of counts should be a power: of two since the prescaler is a
power of two. If not, the timer probably is not counting correctly. The routine also detects a timer
which is not running.

I

3-334

MC68(7)OSR/U SERIES

SECTION 7
RESET, CLOCK, AND INTERRUPT STRUCTURE
7.1 RESET

The MCU can be reset three ways: by initial powerup, by the external reset input (RESET) and by an
optional internal low-voltage detect circuit (not available on the MC68705U3 or MC68705R3 EPROM
versions). The RESET input consists mainly of a Schmitt trigger which senses the RESET line logic
level. A typical reset Schmitt trigger hysteresis curve is shown in Figure 7-1. The Schmitt trigger
provides an internal reset voltage if it senses a logical zero on the RESET pin.
Out
Of
Reset

I
In
Reset

I

I
I

I

08V

2V

4V

I

VIRES- VIRES+

Figure 7-1. Typical Reset Schmitt Trigger Hysteresis

7.1.1 Power-On Reset (PaR)

An internal reset is generated upon powerup that allows the internal clock generator to stabilize. A
delay of tRHL milliseconds is required before allowing the RESET input to go high. Refer to the
power and reset timing diagram of Figure 7-2. Connecting a capacitor to the RES ET input (as illustrated in Figure 7-3) typically provides sufficient delay. During powerup, the Schmitt trigger
switches on (removes reset) when RESET rises to VIRES +.

5V

vee

OV _ _ _ _ _ _...J

RESET
Pin

tRHL
Internal
Reset

Figure 7-2. Power and Reset Timing

3·335

MC68(7)05R/U SERIES

Pin 2
1 0 /t F . - -......--+--i

Typical

(Optionali
POR
Delay
Capacitor

* Disable LVI

I

1-0-LVR

Charging
Current
Source

Figure 7-3. RESET Configuration

7.1.2 External Reset Input

The MCU will be reset if a logical zero is applied to the RESET input for a period longer than one
machine cycle (tcyc). Under this type of reset, the Schmitt trigger switches off at VIRES - to provide an internal reset voltage.
7.1.3 Low-Voltage Inhibit (LVI)

The optional low-voltage detection circuit (not available on the MC68705R3, MC68705R5,
MC68705U3, and MC68705U5) causes a reset of the MCU if the power supply voltage falls below a
certain level (VLVI). The only requirement is that VCC remains at or below the VLVI threshold for
one tcyc minimum. In typical applications, the VCC bus filter capacitor will eliminate negative-going
voltage glitches of less than one tcyc. The output from the low-voltage detector is connected
directly to the internal reset circuitry. It also forces the RESET pin low via a strong discharge device
through a resistor. The internal reset will be removed once the power supply voltage rises above a
recovery level (VLVR), at which time a normal power-on-reset occurs.
7.2 INTERNAL CLOCK GENERATOR OPTIONS

The internal clock generator circuit is designed to require a minimum of external components. A
crystal, a resistor, a jumper wire, or an external signal may be used to generate a system clock with
various stability/ cost tradeoffs. The mask option register (EPROM) is programmed to select crystal
or resistor operation. The oscillator frequency is internally divided by four to produce the internal
system clocks. For MC6805R2, MC6805U2, MC6805R3, and MC6805U3 a manufacturing mask option is used to select crystal or resistor operation.
The different connection methods are shown in Figure 7-4. Crystal specifications and suggested PC
board layouts are given in Figure 7-5. A resistor selection graph is given in Figure 7-6.
The crystal oscillator start-up time is a function of many variables: crystal parameters (especially
RS), oscillator load capacitances, IC parameters, ambient temperature, and supply Voltage. To ensure rapid oscillator start up, neither the crystal characteristics nor the load capacitances should exceed recommendations.

3-336

MC68(7)OSR/U SERIES

I See

Note 2) c::J

XTAL

XTAL

MCU
EXT AL (Crystal Option,
See Note 1)

EXTAL

Crystal

Approximately 25% to 50% ACClJfilCY
Typical tcyc = 1.25 IlS
External Jumper

XTAL

Jl.JL

Exlernill
Clock
Input

EXT AL

MCU
(RC Option,
See Note 1)

MCU
(Crystal Option,
See Note 1)

VCC
--.,., " " ,_---' X TAL
R
(See Figure 7-5)
EXTAL
No
Connection

External Clock

MCU
(RC Option,
See Note 1)

Approximately 10% to 25% Accuracy
(Excludes Resistor Tolerancel
External Resistor

NOTES:
1. For the MC68705R3, MC68705U3, MC68705R5, and MC68705U5 MaR b7 = 0 for the crystal option and MaR b7 = 1 for the RC option. When the TIMER input pin is in the VIHTP range (in the bootstrap EPROM programming mode), the crystal option is forced.
When the TIMER input is at or below VCC, the clock generator option is determined by bit 7 of the Mask Option Register (CLK).
2. The recommended CL value with a 4.0 MHz crystal is 27 pF maximum, including system distributed capacitance. There is an internal capacitance of approximately 25 pF on the XT AL pin. For crystal frequencies other than 4 M Hz, the total capacitance on each
pin should be scaled as the inverse of the frequency ratio. For example, with a 2 MHz crystal, use approximately 50 pF on EXTAL
and approximately 25 pF on XTAL. The exact value depends on the Motional-Arm parameters of the crystal used.

Figure 7-4. Clock Generator Options

When utilizing the on-board oscillator, the MCU should remain in a reset condition (reset pin
voltage below VIRES +) until the oscillator has stabilized at its operating frequency. Several factors
are involved in calculating the external reset capacitor required to satisfy this condition: the
oscillator start-up voltage, the oscillator stabilization time, the minimum VIRES + , and the reset
charging current specification.
Once VCC minimum is reached, the external RESET capacitor will begin to charge at a rate dependent on the capacitor value. The charging current is supplied from V CC through a large resistor, so
it appears almost like a constant current source until the reset voltage rises above VIRES + .
Therefore, the RESET pin will charge at approximately:
(VIRES + )eCext= IRESetRHL
Assuming the external capacitor is initially discharged.

3-337

II

MC68(7)OSR/U SERIES

(a)

Cl

-t~0I
s

EXTAL

5

_

Co

XTAL

6

AT - Cut Parallel Resonance Crystal
Co = 7 pF Max
Freq.=4.0 MHz @ CL =24 pF
RS = 50 ohms Max.

Piezoelectric ceramic resonators which
have the equivalent specifications may be
used instead of crystal oscillators. Follow
ceramic resonator manufacturer's suggestions for CO, Cl, and RS values.

I

(b)
(c)

NOTE: Keep crystal leads and circuit connections as short as possible.

Figure 7-5. Crystal Motional-Arm Parameters
and Suggested PC Board Layout

8.0 . . . - - . - - - - - - - - - - - - - - - - - - - - - - ,
70

~
:2

6.0
VCC=525V
TA ~ 25°C

1.0
10

20

40
50
Resistance (km

30

60

70

Figure 7-6. Typical Frequency Selection for
Resistor (RC Oscillator Option)

80

MC68(7)OSR/U SERIES

7.3 INTERRUPTS

The microcomputers can be interrupted four different ways: through the external interrupt (I NT) input pin, the internal timer interrupt request, the external port D bit 6 (INT2) input pin, or the software interrupt instruction (SWI). When any interrupt occurs: the current instruction (including
SWI) is completed, processing is suspended, the present CPU state is pushed onto the stack, the
interrupt bit (I) in the condition code register is set, the address of the interrupt routine is obtained
from the appropriate interrupt vector address, and the interrupt routine is executed. Stacking the
CPU register, setting the I bit, and vector fetching require a total of 11 tcyc periods for completion.
A flowchart of the interrupt sequence is shown in Figure 7-7. The interrupt service routine must end
with a return from interrupt (RTI) instruction which allows the M CU to resume processing of the

I
1-1 (in CCI
07F-SP
O-DDRs
CLR INT Logic
FF-Timer
7F - Prescaler
7F-TCR
7F-MR

Load PC From:
SWI: FFC/FFD
INT: FFAI FFB
Timer or
INT2: FF81 FF9

M C68705R31 M C68705U3
MC68705R5/MC68705U5
Load Options From
MaR ($F381 Into
Control Logic

Figure 7-7. Reset and Interrupt Processing Flowchart

MC68(7)OSR/U SERIES

program prior to the interrupt (by unstacking the previous CPU state). Unlike RESET, hardware
interrupts do not cause the current instruction execution to be halted, but are considered pending
until the current instruction execution is complete,
When the current instruction is complete, the processor checks all pending hardware interrupts and
if unmasked, proceeds with interrupt processing; otherwise the next instruction is fetched and executed. Note that masked interrupts are latched for later interrupt service.
If both an external interrupt and a timer interrupt are pending at the end of an instruction execution,
the external interrupt is serviced first. The SWI is executed as any other instruction.

II

NOTE
The timer and INT2 interrupts share the same vector address. The interrupt routine must
determine the source by examining the interrupt request bits (TCR b7 and M R b7). Both
TCR b7 and MR b7 can only be written to zero by software.
The external interrupt, INT and INT2, are synchronized and then latched on the falling edge of the
input signal. The INT2 interrupt has an interrupt request bit (bit 7) and a mask bit (bit 6) located in
the miscellaneous register (MR). The INT2 interrupt is inhibited when the mask bit is set. The INT2
is always read as a digital input on port D. The INT2 and timer interrupt request bits, if set, cause the
MCU to process an interrupt when the condition code I bit is clear.
A sinusoidal input signal (fINT maximum) can be used to generate an external interrupt for use as a
zero-crossing detector. This allows applications such as servicing time-of-day routines and engaging/ disengaging ac power control devices. Off-chip full wave rectification provides an interrupt at
every zero crossing of the ac signal and thereby provides a 2f clock. See Figure 7-8.
A software interrupt (SWI) is an executable instruction which is executed regardless of the state of
the I bit in the condition code register. SWls are usually used as breakpoints for debugging or as
system calls.
(b) Digital-Signal Interrupt

(a) Zero-Crossing Interrupt

Vcc
ae
Input
(tiNT Max.)

(Current

TTL

~'mltln9)3 iNT

R~1M(}

aelnput
<2
0

C

3
5

3
5

3
5

3
5

3
5

3
5

Olf

3

4

6

STA
DIR
3
EOR
DIR
3
ADC
DIR
3
ORA
DIR
3
ADD
DIR
2
JMP
DIR
5

3
5

3
5

3
5

3
5

3
4
3
8

1101

4 6
SUB
EXT
4
CMP
EXT
4
SBC
EXT
4
CPX
EXT
4
AND
EXT
4
BIT
EXT
4
LOA
EXT
5

STA
EXT
4
EOR
EXT
4
ADC
EXT
4
ORA
EXT
4
ADD
EXT
3
JMP
EXT
6

BSR
JSR
JSR
REL 2
DIR 3
EXT
24
4
3 5
*STOP
LOX
LOX
LOX
1
INH
IMM
2
DIA
2
EXT
3
4 6
5
5
*WAIT 2 2 TXA 2
STX
STX
1
INH 1
INH
DIR 3
2
EXT
1

2

IX
F

1110

1111

4 4

5 5

SUB

SUB

3
6

IXl
4

5 5

CMP

CPX
IXl 1
4 4

5 5

IXl

1

5 5

4

4

BIT
5 5

LOA
3
7
STA
3
6

IXl

IXl 1
4 4

5 5

EOR
5 5

ADC
3
6

ADC
5 5

ORA
3
6

ORA
5 5

ADD
3
5

JMP
3

IXl 1
3 3
JMP

JSR
3
6

JSR
5 5

LOX

1

5 5

STX
IX2 2

0101

IX
4

0110

IX
3

0111

IX
3

1000

IX
3

1001

IX
3

1010

IX
2

1011

IX

1100

6

7

8
9

A

B

C

0
IX
3

dOl

IX
4

1110

IX

1111

LOX
IXl

6 6

STX

IX
3

JSR

LOX
IX2 2

3
7

5

5

IXl 1
44

IX2 2

4

JMP
IXl 1
6 7

IX2 2
7 8

9

0100

ADD

ADD
IX2 2
44

IX
3

3

ORA
IXl 1
44

IX2 2

0011

ADC
IXl 1
4 4

IX2 2

IX
3

2

EOR
IXl 1
44

IX2 2

0010

STA

STA

EOR
3
6

1

5 5

IX2 2

IX
3

1

LOA

LOA
IX2 2
6 6

0001

BIT
IXl 1
44

IX2 2

IX
3

AND

AND
IX2 2

BIT

0000

CPX

IX2 2
AND

0
IX
3

SBC
IXl 1
4 4

5 5

CPX
3
6

I Low
~

CMP

SBC
IX2 2

3
6

4

IXl 1
4 4

5 5

SBC
3
6

3
6

1

CMP
IX2 2

3
SUB

IX2 2

3
6

3

IXl
E

E

F

STX
IXl

1

LEGEND
+-+---------:':'Opcode In HexadeCimal

__

1111

Cycles, M6805 HMOS _ _ _.4-....:::o;~r---===:;*.:::::
Mnemonlc---+--l~

Bytes------'~_

Opcode in Binary

_t~~-~~~

Cycles, M146805 C M O S - - - - - - J

' - - - - - - - - - A d d r e s s Mode

I

MC68(7)OSR/U SERIES

SECTION 11
ELECTRICAL CHARACTERISTICS
11 1 MAXIMUM RATINGS
Rating

I

Symbol

Value

Unit

Supply Voltage

VCC

-0.3 to + 7.0

V

Input Voltage
MC6805R2, MC6805R3, MC6805U2,
and MC6805U3 (Except
TIMER in Self-Check Mode
and Open-Drain Inputs)
Self-Check Mode !TIMER Pin Only)

Yin
Yin

-0.3to+7.0
-0.3 to + 15.0

V
V

Vpp
Yin

- 0.3 to + 22.0
-0.3 to + 7.0

V
V

Yin
Yin

-0.3 to + 15.0
-0.3 to + 7.0

V
V

M C68705R31 M C68705U3
EPROM Programming Voltage
(Vpp Pin)
TIMER Pin - Normal Mode
TIMER Pin - Bootstrap
Programming Mode
All Others
Operating Temperature Range
MC6805R2, MC6805U2, MC6805R3,
MC6805U3, MC68705R3,
MC68705U3, MC68705R5,
MC68705U5
MC6805R2C, MC6805U2C,
MC6805R3C, MC6805U3C,
MC68705R3C, MC68705U3C,
MC68705R5C, MC68705U5C
MC6805R2V, MC6805U2V,
MC6805R3V, MC6805U3V
Storage Temperature Range
Junction Temperature
Plastic
Ceramic
Cerdip

TL to TH

TA

o to

DC

+ 70

-40 to 85

-40 to 105
Tst9

- 55 to + 150

DC

TJ

150
175
175

DC/W

11 2 THERMAL CHARACTERISTICS
Characteristic

Symbol

Value

Tflermal Resistance
Plastic (P Suffix) - MC6805R2, MC6805U2,
MC6805R3, MC6805U3
Ceramic - MC6805R2, MC6805U2, MC6805R3,
MC6805U3, MC68705R3, MC68705U3,
MC68705R5, MC68705U5

Unit

60

DC/W

OJA
50

Cerdip - MC6805R2, MC6805U2, MC6805R3
MC6805U3, MC68705R5, MC68705U5

60

3-364

These devices contain circuitry to
protect the inputs against damage
due to high static voltages or electrical fields; however, it is advised
that normal precautions be taken
to avoid application of any voltage
higher than maximum rated
voltages to this high-impedance
circuit. For proper operation it is
recommended that Yin and V out
be constrained to the range
VSS~(Vin and Vout)~VC(,
Reliabiity of operation is enhanced
if unused inputs except EXT AL are
tied to an appropriate logic voltage
level (e.g., either VSS or VCC).

MC68(7)OSR/U SERIES

11.3 POWER CONSIDERATIONS
The average chip-junction temperature, T J, in °c can be obtained from:
(1)
T J = T A + (PD-OJA)
Where:
T A == Ambient Temperature, °c
OJA1i= Package Thermal Resistance, Junction-to-Ambient, °C/W
PD==PINT+ PPORT
PINT== ICC x Vce Watts - Chip Internal Power
PPORT == Port Power Dissipation, Watts - User Determined
For most applications PPORT~ PINT and can be neglected. PPORT may become significant if
the device is configured to drive Darlington bases or sink LED loads.
An appropriate relationship between PD and TJ (if PPORT is neglected) is:
PD= K -;- (T J + 273°)
(2)
Solving equations 1 and 2 for K gives:
K=PD-(TA+273°C)+OJA-PD 2
(3)
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by
measuring PD (at equilibrium) for a known T A- Using this value of K the values of PD and T J can be
obtained by solving equations (1) and (2) iteratively for any value of T A-

VCC=575V
Test

MMD6150

P0o-In_t____-o.....
r E~q--+Ui..
V - - - . 1.45 kO

40 pF

T i

(10lall~

12 kO

TestPolnt~

130 pF !Total I

MMD7000
or Equlv

Figure 11-1. TTL Equivalent Test Load
(Port B)

Figure 11-2. CMOS Equivalent Test Load
(Port A)

Vcc= 575 V
Test
POint
Test
Point

30 pF
(Totall

Figure 11-3. TTL Equivalent Test Load
(Ports A and C)

~J

VCC=575V

3.34 kO

30 pF (Totall

Figure 11-4. Open-Drain Equivalent Test Load
(Port C)

3-365

I

MC68(7)OSR/U SERIES

11.4 MC6805R2 AND MC6805R3
11.4.1 Electrical Characteristics (VCC= +5.25 Vdc ±O.5 Vdc, VSS=O Vdc, TA=TL to TH
unless otherwise noted)
Characteristic
Input High Voltage
RESET 1475~VCC~5751
IVCC<4751
INT 1475~VCC~5751
IVCC<4751
All Other

Typ

Max

Unit

-

VIH

4.0
VCC-05
4.0

VCC
VCC
VCC
VCC
V'CC

V

VIH

Input Low Voltage
RESET
INT
All Other IExcept AID Inputsl

INT Zero Crossing Input Voltage, Through a Capacitor
TA = OoC
TA= -40 oe

I nput Capacitance
XTAL
All Other Except Analog Inputs ISee Notel

2.0
9.0

-

-

10.0

VIRES +
VIRES-

2.1
0.8

-

VI NT

2

PD

-

-

Low Voltage Recover

VLVR

-

Low Voltage Inhibit

VLVI

2.75

-

lin
IRES

-4.0

NOTE Port D Analog Inputs, when selected, Cin = 25 pF for the first 5 out of 30 cycles.
*Due to internal biasing this input Iwhen unusedl floats to approximately 2.0 V.

3-366

*
*

-

Cin

Input Current
TIMER IVin = OAI
INT IVin=2A V to Veci
EXTAL IVin=2A V to Vee Crystal Optionl
IVin = OA V Crystal Optionl
RESET IVin = 0.8 VI
I External Capacitor Charging Currentl

-

VSS
VSS
VSS

VIL

RESET Hysteresis Voltages ISee Figures 7·1, 7·2, and 7·31
"Out of Reset"
"Into Reset"
Power Dissipation - (No Port Loading, V CC = 5.75 V
for Steady-State Operationl

Min

VCC-05
2.0

Input High Voltage Timer
Timer Mode
Self·Check Mode

I

Symbol

*
-

-

-

VCC + 1.0
15.0
0.8
1.5
0.8

V

V

4.0
2.0

V

4

Vac p.p

520
580

740
800

mW

25
10

-

pF

-

-

4.75

V

3.75

4.70

V

-

20
50
10
-1600
-40

/l-A

20
-

-

MC68(7)OSR/U SERIES

MC6805R2 AND MC6805R3

11.4.2 Switching Characteristics (VCC= +5.25 Vdc ±0.5 Vdc, VSS=O Vdc, TA=TL to TH
Symbol

Min

Typ

Max

Unit

Oscillator Frequency

losc

0.4

-

4.2

MHz

Cycle Time (4/losc)

tcyc
tWL, tWH

0.95

-

10

t<;yc+ 250

-

-

1'5
n5

tRWL
liNT

tcyc + 250
0.03

-

-

-

1

kHz

-

40

50

60

-

-

-

100

%
ms

Characteristic

INT, INT2, and TIMER Pulse Width
RESET Pulse Width
INT Zero-Crossing Detection Input Frequency
External Clock Input Duty Cycle (EXTAU
Crystal Oscillator Start-Up Time*

n5

* See Figure 7-5 lor tYPical crystal parameters.

11.4.3 AID Converter Characteristics (VCC = + 5.25 Vdc ± 0.5 Vdc, VSS = 0 Vdc, TA = TL to TH
unless otherwise noted)
Min

Typ

Max

Unit

Resolution

B

B

B

Bits

Non-Linearity

-

-

-

-

± 1/2
± 1/2

LSB

Quantizing Error
Conversion Range

Comments
For VRH=40 to 5.0 V andVRL =0 V

LSB

-

VRH

V

VRH

-

-

VCC

V

AI D accuracy may decrease proportionately as

VRL

VSS

-

0.2

V

VRH is reduced below 4.0 V. The sum 01 VRH and

30

30

30

tcyc

VRL must not exceed VCe.
Includes sampling time

Conversion Time

VRL

Monotonicity
Zero Input Reading
Ratiometric Reading

Inherent (within total errori

00
FE

00
FF

01

hexadecimal

Vm=O

FF

hexadecimal

Yin = VRH

Sample Time

5

5

5

Sample/ Hold Capacitance, Input

-

-

25

tcyc
pF

VRL

-

VRH

V

Analog Input Voltage

3-367

Negative transients on any analog lines (Pins 19-24)
are not allowed at any time during conversion

I

MC68(7)OSR/U SERIES

MC6805R2 AND MC6805R3

11.4.4 Port Electrical Characteristics (VCC= +5.25 Vdc ±O.5 Vdc, VSS=O Vdc, TA=TL to TH
unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

Port A with CMOS Drive Enabled
Output Low Voltage ILoad= 1.6 mA

VOL

-

-

0.4

V

Output High Voltage ILoad= -100ItA

VOH

2.4

-

V

Output High Voltage ILoad- -10 itA

VOH

VCC-l

-

-

V

Input High Voltage ILoad- -300 itA (max)

VIH

2.0

-

V

Input Low Voltage ILoad= -500 itA (max)

VIL

VSS

-

Vr.r.
0.8

Hi-Z State Input Current (Vin = 2.0 V to V CC)

IIH

-

-300

itA

IlL

-

-500

itA

0.4

V

1.0

V

Hi-Z State Input Current (Vin = 0.4 V)

-

V

Port B

I

Output Low Voltage ILoad = 3.2 mA

VOL

-

Output Low Voltage ILoad= 10 mA (sink)

VOL

-

Output High Voltage I Load = - 200 itA

VOH

2.4

-

Darlington Current Drive (Source) VO= 1.5 V

IOH

-1.0

-

-10

mA

Input High Voltage

VIH

2.0

-

Input Low Voltage

VIL

VSS
-

-

VCC
0.8

V

<2

10

itA

Hi-Z State Input Current

ITSI

-

V
V

Port C and Port A with CMOS Device Disabled
Ouput Low Voltage ILoad= 1.6 mA

VOL

-

-

0.4

V

Output High Voltage ILoad= -100 itA

YOH

2.4

-

-

V

Input High Voltage

VIH

2.0

-

VIL

VSS

-

VCC
0.8

V

Input Low Voltage
Hi-Z State Input Current

ITS I

-

<2

10

itA

V

Port C (Open-Drain Option)
Input High Voltage

VIH

2.0

-

13.0

V

Input Low Voltage

VIL

VSS

-

0.8

V

Input Leakage Current (Vin = 13.0 V)

ILOD

-

<3

15

itA

Output Low Voltage ILoad= 1.6 mA

VOL

-

-

0.4

V

Port D (Digital Inputs Only)
Input High Voltage

VIH

2.0

-

VCC

V

Input Low Voltage

VIL

VSS

-

lin

-

<1

0.8
5

V
itA

Input Current

*

*PD4/VRL -PD5IVRH: The AID conversion resistor (15 kG typical) is connected internally between these two lines, impacting their
use as digital inputs in some applications.

3-368

MC68(7)OSR/U SERIES

11.5 MC6805U2 AND MC6805U3
11.5.1 Electrical Characteristics (VCC= +5.25 Vdc ±O.5 Vdc, VSS=O Vdc, TA=TL to TH
unless otherwise noted)
Characteristic
Input High Voltage
RESET (4.75:SVCC:s5.75)
(VCC<4.75)
INT (4.75:sVcc:s5.75)
(VCC<4.75)
All Other (Except Timer)
Input High Voltage Timer
Timer Mode
Self-Check Mode

Symbol

Min

VIH

4.0
VCc-OS
4.0
VCC-0.5
2.0

*
*-

2.0
9.0

10.0

VIL

VSS
VSS
VSS

-'"

VIRES+
VIRES-

2.1
O.B

-

VIH

Input Low Voltage
RESET
INT
All Other
RESET Hysteresis Voltages (See Figures 7-1, 7-2, and 7-3)
"Out of Reset"
"Into Reset"

Typ

Max

Unit

-

Vec
Vec
Vec
Vec
Vec

V

-

-

-

-

INT Zero Crossing Voltage, Through a Capacitor

VINT

2

-

Internal Power Dissipation (No Port Loading, V CC = 5.75 V
TA=O°C
for Steady-State Operation)
TA=-40°C

PINT

-

520
580

Cin

-

25
10

Input Capacitance
XTAL
All Other
Low Voltage Recover

VLVR

-

Low Voltage Inhibit

VLVI

2.75

Input Current
TIMER (Vin = 04 V)
INT (Vin= 24 V to VCC)
EXTAL (Vin=24 V to VCC Crystal Option I
_ _ (Vin=04 V Crystal Option)
RESET (Vin=O.B VI
(External Capacitor Charging Current)

-

3.75

VCC+l.0
15.0
O.B
1.5
O.B

V

4.0
2.0

V

4

Vac p-p

740
BOO

mW

-

pF

4.75

V

4.70

V

-

-

20

-

20

50

lin

-

-

IRES

-4.0

-

V

10
-1600
-40

p.A

*' Due to internal biasing, this input (when unused) floats to approximately 2.0 v.
11.5.2 Switching Characteristics (VCC= +5.25 Vdc ±O.5 Vdc, VSS=O Vdc, TA=TL to TH
unless otherwise noted)
Characteristic
Oscillator Frequency

Symbol

Min

Typ

Max

Unit

fosc

04

-

4.2

MHz
p's

tcyc

0.95

.-

lD

twL, twH

tcyc +250

--

-

ns

IiESTI Pulse Width

tRWL

t cyc +250

-

ns

REStT Delay Time (External Cap= 1 p.F)
iNT Zero Crossing Detection Input Frequency

tRHL

-

-

ms

flNT

0.03

-

1.0

kHz

-

40

50

60

%

-

-

-

100

ms

Cycle Time (4/fos c )
INT, INT2, and TIMER Pulse Width

External Clock Input Duty Cycle (EXTALi
Crystal Oscillator Start-Up Time*
* See Figure 7-5 for tYPical crystal parameters.

3-369

100

II

MC68(7)OSR/U SERIES

MC6805U2 AND MC6805U3
11.5.3 Port Electrical Characteristics (VCC= +5.25 Vdc ±O.5 Vdc, VSS=O Vdc, TA=TL to TH
unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

2A

-

OA

V

-

-

V

-

-

V

-

Vee
0.8

V

-300

I'A
I'A

Port A with CMOS drive enabled
Output Low Voltage ILoad = 1.6 mA

VOL

Output High Voltage ILoad= -100 p.A

VOH

I'A
High Voltage ILoad= -300 I'A (maxi
Low Voltage ILoad= -500 I'A (maxi

Vee- 1.O

Output High Voltage ILoad= -10

VOH

Input

VIH

2.0

VIL

VSS

-

IIH

-

IlL

-

-

-500

Input

Hi-Z State Input Current (Vin=2.0 V to Veel
Hi-Z State Input Current (Vin = OA VI

V

Port B

I

Output Low Voltage ILoad = 3.2 mA

VOL

-

-

OA

V

Output Low Voltage ILoad = 10 mA (sinkl

VOL

--

1.0

V

VOH

2A

IOH

-1.0

-

-10

-

Vc:c:

V

0.8

V

-

<2

10

I'A

OA
-

V

Output High Voltage ILoad= -200

I'A

-Darlington Current Drive (Sourcel VO= 1.5 V
Input High Voltage

VIH

2.0

Input Low Voltage

VIL

VSS

Hi-Z State Input Current

ITSI
Port C and Port A with CMOS drive disabled

--

VOL

-

-

VOH

2.4

-

Input High Voltage

VIH

2.0

-

Input Low Voltage

VIL

VSS

-

Output Low Voltage ILoad = 1.6 mA
Output High Voltage ILoad = -100

I'A

Hi-Z State Input Current

ITSI

-

-

V
mA

V
V

Vce
0.8

V

<2

10

I'A
V

Port C (Open-Drain Option)
Input High Voltage

VIH

2.0

-

130

Input Low Voltage

VIL

VSS

-

0.8

V

Input Leakage Current (Vin = 13.0 V)

ILOD

-

<3

15

I'A

Output Low Voltage ILoad= 1.6 mA

VOL

-

-

OA

V

Input High Voltage

VIH

2.0

-

Input Low Voltage

VIL

VSS

-

V

Input Current

lin

Vee
0.8
5

-

<1

V

I'A

MC68(7)OSR/U SERIES

11.6 MC68705R3 AND MC68705R5
11.6.1 Programming Operation Electrical Characteristics (Vee=5.25 Vdc ±0.5, VSS=O,
T A = 20° to 30 0 e unless otherwise noted)
Symbol

Min

Typ

Max

Unit

Programming Voltage

Characteristic

Vpp

20.0

21.0

22.0

V

Vpp Supply Current
Vpp = 5.25 V
Vpp=21.0 V

Ipp

-

-

8
30

rnA

-

Oscillator Frequency

fos c (p)
VIHTP

Bootstrap Programming Mode Voltage (TIMER Pin) @ IIHTP = 100 p.A Max

0.9

1.0

1.1

MHz

9.0

12.0

15.0

V

11.6.2 Electrical Characteristics (Vee= +5.25 Vdc ±0.5 Vdc, VSS=O Vdc, TA=O° to 70 0 e
unless otherwise noted)
Characteristic
Input High Voltage.
RE"STI (4.75:s;VCC:s;5.75)
(VCC<4.75)
INT
(4.75:s;VCC:s;5.75)
(VCC<475)
All Other
Input High Voltage (TIMER Pin)
Timer Mode
Bootstrap Programming Mode

Min

Typ

Max

Unit

VIH

4.0
VCC-05
4.0
VCC-05
2.0

-

VCC
VCC
VCC
VCC
VCC

V

VCC+ 1.0
15.0

V
V

0.8
1.5
0.8

V
V
V

4.0

Vac Pop

VIH

Input Low Voltage
RESET
INT
All Other

VIL

INT Zero-Crossing Input Voltage - Through a Capacitor

VINT

Internal Power Dissipation (No Port Loading, VCC=5.25 V TA=O°C
for Steady-State Operation)
TA= -40°C

PINT

Input Capacitance
EXTAL
All Other (See Notel

Cm

2.0
9.0
VSS
VSS
VSS
2.0

Programming Voltage (Vpp Pin)
Programming EPROM
Operating Mode
Input Current
TIMER (Vin = OA V)
iNi' (Vin=OA V)
EXTAL (V m =2A V to VCCI
(Vin=OA V)
RESET (Vin = 0.8 V)
(External Capacitor Changing Current)

12.0
-

**
-

V

740

-

580

ROO

-

25
10

-

pF
pF

4.0
20

V
V

22.0
5.75

V
V

20
50
10
-1600
-40

/LA

21
08

Vpp*

200
4.75

IRES

-

V

520

VIRES +
VIRES-

lin

-

**
**

-

-

RESET Hysteresis Voltage (See Figure 7-1)
Out of Reset Voltage
Into Reset Voltage

*

Symbol

--

210
VCC

-

-

-

20

-

-

--

-

-4.0

-

-

mW

*Vpp is pin 7 on the MC68705R3 and MC68705R5 and is connected to VCC in the normal operating mode. In the MC6805R2, pin 7 is
connected to VSS in the normal operating mode. The user must allow for this difference when emulating the rvlC6805R2 ROM-based
MCU.
* Due to internal biasing, this input (when not used) floats to approximately 2.0 V.

NOTE: Port D analog inputs, when selected, Cin = 25 pF for the first 5 out of 30 cycles.

3-371

•

MC68(7)05R/U SERIES

MC68705R3 AND MC68705R5
11.6.3 Switching Characteristics (Vee= +5.25 Vdc ±O.5 Vdc, VSS=O Vdc, TA=Oc to 70 ce
unless otherwise noted)
Characteristic
Oscillator Frequency
Normal
Instruction Cycle Time 14/10scl
INT, INT2, or Timer Pulse Width
RESET Pulse Width

I

Min

Typ

Max

Unit

lose

0.4

-

4.2

MHz

tcyc

0.950

-

10

tWL,tWH

t cyc + 250

-

-

fls
ns

Symbol

tRWL

tcyc + 250

RESET Delay Time IExternal Cap= 1.0 flF)

tRHL

-

INT Zero Crossing Detection Input Frequency

-

-

ns

100

-

ms
kHz

liNT

0.03

-

1.0

External Clock Duty Cycle IEXTAU

-

40

50

60

%

Crystal Oscillator Start-Up Time*

-

-

-

100

ms

* See Figure 7-5 lor typical crystal parameters.

11.6.4 AID Converter Characteristics (Vee= +5.25 V ±O.5 Vdc, VSS=O Vdc, TA=O° to 70 ce
unless otherwise noted)
Characteristic
Resolution
Non-Linearity
Quantitizing Error
Conversion Range

Min

Typ

Max

8
-

8

8

-

± 1/2
± 1/2
VRH

V

-

V
V

-

Unit
Bits
LSB

Comments
For VRH

=

4.0 to 5.0 V and VRL = 0 V

LSB

VRH

VRL
-

VRL

VSS

-

VCC
0.2

30

30

30

Ratiometric Reading

00
FE

FF

FF

hexadecimal

Sample Time
Sample/Hold Capacitance, Input

5

5

-

-

5
25

tcyc
pF

VRL

-

VRH

V

AI D accuracy may decrease proportionately as
V RH is reduced below 4.0 V. The sum 01 V RHand
VRL must not exceed VCC.

Conversion Time
Monotonicity
Zero Input Reading

Analog Input Voltage

tcyc
Inherent Iwithin total error)
01
hexadecimal
00

3-372

Includes sampling time
Vin=O
Vin=VRH

Negative transients on any analog lines Ipins 19-24)
are not allowed at any time during conversion.

MC68(7)OSR/U SERIES

MC68705R3 AND MC68705R5
11.6.5 Port Electrical Characteristics (Vee =

+ 5.25 Vdc ± 0.5 Vdc, VSS= 0 Vdc, T A =0° to 70 e
0

unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit
V

Port A
Output Low Voltage, ILoad= 1.6 mA

VOl

-

-

OA

Output High Voltage, 'Load = -100 p.A

VOH

2A

-

-

V

Output High Voltage, ILoad= -10 p.A

VOH

VCC-l0

-

-

V

Vce
0.8

V

Input High Voltage, ILoad= -300 p.A (Max)

VIH

2.0

-

Input Low Voltage, ILoad= -500 p.A (Maxi

VIL

VSS

-

Hi-Z State Input Current (V in = 20 V to Vcel
Hi-Z State Input Current (Vin - OA V)

IIH

-

-

-300

p.A

IlL

-

-

-500

p.A

V

Port B
Output Low Voltage, ILoad = 3.2 mA

VOL

-

-

0.4

V

Output Low Voltage, ILoad= 10 mA (Sink)

VOL

-

-

1.0

V

Output High Voltage, ILoad = - 200 p.A

VOH

2A

Darlington Current Drive (Source), VO= 1.5 V

IOH

-1.0

Input High Voltage

VIH

Input Low Voltage

VIL

HI-Z State Input Current

ITS I

-

V

.-

-10

mA

2.0

-

VSS

-

Vce
0.8

V

<2

10

p.A
V

-

--

V

Port C
Output Low Voltage, ILoad= 1.6 mA

VOL

-

-

0.4

Output High Voltage, ILoad= -100 p.A

VOH

2A

-

-

V

Input High Voltage

VIH

2.0

-

V

Input Low Voltage

VIL

VSS

-

Vce
0.8

HI-Z State Input Current

ITS I

-

<2

10

p.A

Input High Voltage

VIH

2.0

-

VIL

VSS

-

Vce
0.8

V

Input Low Voltage
Input Current

lin

<1

5

p.A

V

Port D (Input Only)

-

V

11.7 MC68705U3 AND MC68705U5
11.7.1 Programming Operation Electrical Characteristics (Vee=5.25 Vdc ±0.5, VSS=O Vdc,

TA = 20° to 30 0 e unless otherwise noted)
Symbol

Min

Typ

Max

Unit

Programming Voltage

Characteristic

VPP

200

21.0

22.0

V

Vpp Supply Current
Vpp= 5.25 V
Vpp=21.0V

Ipp

-

-

8
30

mA

1.1

MHz

-

Programming Oscillator Frequency

foscp

Og

1.0

Bootstrap Programming Mode Voltage (TIMER Pin)(@ '1HTP = 100 /lA Max)

VIHTP

9.0

12.0

3-373

150.

V

•

MC68(7)OSR/U SERIES

MC68705U3 AND MC68705U5
11.7.2 Electrical Characteristics (Vee =
unless otherwise noted)

+ 5.25 Vdc ± 0.5 Vdc, VSS = 0 Vdc, T A = 0° to 70 0 e

Characteristic
Input Hlgh'Voltage
RESET 14.99:sVCC:s5511
IVCC<4751
iNf
1499:sVCC:s5.51J
IVCC<4751
All Other
Input High Voltage !TIMER P,nl
Timer Mode
Bootstrap Programming Mode

II

Symbol

Min

Typ

Max

Unit

-

VIH

40
VCC-05
4.0
VCC-05
2.0

VCC
VCC
VCC
VCC
VCC

V

VIH

Input Low Voltage
RESET
INT
All Qther
Internal Power Dissipation (No Port Loading, VCC=5.25 V TA=O°C
for Steady-State Operation)
TA= -40°C
Input Capacitance
XTAL
All Other
INT Zero· Crossing Voltage, through a Capacitor
RESET Hysteresis Voltage (See Figure 7-1)
Out of Reset Voltage
Into Reset Voltage
Programming Voltage IVpp P,nl
Programming EPROM
Operating Mode
Input Current
TIMER 1Vin = 0.4 VI
INT
1Vin=0.4 "\,1)
EXTAl IVin=2.4 V to VCC Crystal Optionl
1Vin = 0.4 V Crystal Option)
RESET 1Vin = 0.8 VI
I External Capacitor Changing Currentl

2.0
90

-

**
**
-

-

V

VCC+l.0
15.0

12.0

-

VSS
VSS
VSS

**

PINT

-

520
580

740
800

mW

C,n

-

25
10

-

pF

-

-

VI NT

2.0

-

4.0

Vac p-p

VIRES +
VIRES-

2.1
0.8

-

4.0
2.0

V

-

Vpp*

20.0
4.75

22.0
5.75

V

VCC

VIL

lin
IRES

0.8
15
0.8

-

21.0

-

-

-

20

-

-

20
50
10
-1600
-40

-

-4.0

-

V

I'A

*Vpp is Pin 7 on the MC68705U3 and MC68705U5 and is connected to VCC in the Normal Operating Mode. In the MC6805U2. Pin 7 is
NUM and is connected to VSS in the Normal Operating Mode. The user must allow for this difference when emulating the
MC6805U2 ROM-based MCU.
* * Due to internal biasing, this input (when not used) floats to approximately 2.0 V.

11.7.3 Switching Characteristics (Vee =
unless otherwise noted)

+ 5.25 Vdc, ± 0,5 V, VSS = 0 Vdc, T A = 0° to 70 0 e
Symbol

Characteristic
Oscillator Frequency
Normal
Instruction Cycle Time 14/fosc)

iNT,

INT2, or Timer Pulse Width
RESET Pulse Width

Min

Typ

Max

Unit

fosc

0.4

-

4.2

MHz

tcyc
tWL,tWH

0.950

-

10

-

-

I's
ns

tRWL

tcyc+ 250
tcyc+ 250

-

-

ns

RESET Delay Time IExternal Cap= 10 I'FI

tRHL

100

-

-

ms

iNi

flNT

0.03

-

1.0

kHz

-

40

50

-

-

-

60
100

ms

Zero CrosSing Detection Input Frequency
External Clock Duty Cycle IEXTALI
Crystal Oscillator Start-Up Time*

* See Figure 7-5 for tYPical crystal parameters.

3-374

%

MC68(7)OSR/U SERIES

MC68705U3 AND MC68705U5

11.7.4 Port Electrical Characteristics (Vee= +5.25 Vdc ±O.5 Vdc, VSS=O Vdc, TA=O° to 70 0 e
unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

-

-

0.4

V

-

-

V

PortA
Output Low Voltage, ILoad = 1.6 rnA

VOL

Output High Voltage, ILoad = -100 p.A

VOH

Output High Voltage, ILoad= -10 p.A

VOH

2.4
VCC-l.0

-

-

V

Input High Voltage, ILoad= -300 p.A (Maxi

VIH

2.0

-

Input Low Voltage, ILoad= -500 p.A (Maxi

VIL

VSS

-

VCC
0.8

V

Hi-Z State Input Current (Vin=2.0 V to VCCI

IIH

-

-

-300

p.A

Hi-Z State Input Current (Vin = 0.4 VI

IlL

-

-

-500

p.A

V

Port B
Output Low Voltage, ILoad= 3.2 rnA

VOL

-

-

D.4

V

Output i_ow Voltage, ILoad= 10 rnA (Sinkl

VOL

-

-

1.0

V

Output High Voltage, ILoad = - 200 p.A

VOH

2.4

-

Darlington Current Drive (Sourcel, VO= 1.5 V

IOH

-1.0

-

-10

mA

Input High Voltage

VIH

2.0

-

Input Low Voltage

VIL

VSS

-

VCC
0.8

V

IT"I

-

<2

0

p.A

Hi-Z State Input Current

V

-

V

Port C
Output Low Voltage, ILoad= 1.6 rnA

VOL

-

-

0.4

V

Output High Voltage, ILoad= -100 p.A

VOH

2.4

-

-

V

Input High Voltage

VIH

2.0

-

Input Low Voltage

VIL

VSS

-

VCC
0.8

V

-

<2

10

p.A

VCC
0.8
5

V

Hi-Z State Input Current

ITSI

V

Port D (Input Only)
Input High Voltage

VIH

2.0

-

Input Low Voltage

VIL

VSS

-

Input Current

lin

-

<1

V
p.A

11.8 1/0 CHARACTERISTICS
Figures 11-5 through 11-15 illustrate I/O characteristic data for HMOS M6805 Family devices.
Simplified port logic diagrams are shown in Figures 11-16 and 11-17, typical input protection in
Figure 11-18, and an I/O characteristic measurement circuit in Figure 11-19. The I/O characteristic
curves and logic diagrams are intended to allow the system designer to interface the M6805 in a
variety of applications where non-TTL loading conditions exist.
A minimum specification curve (included with VOH vs 10H charts only) is provided as a guaranteed
limit of performance under the conditions shown. The expected minimum and maximum curves in
each figure represent the anticipated performance window under normal manufacturing and
operating conditions. A typical curve also is illustrated indicating. performance under nominal
conditions.
Figure 11-15 represents the variation of I DD with temperature and VDD for a typical M6805 Family
device. As shown, IDD varies directly with VDD and inversely with temperature.

3-375

I

MC68(7)OSR/U SERIES

.2121

(3.7SV -1 ~A)
f--

(2.4V.-lOO~A)

~
SPECI / /
/

-.3121

r

!

MIN

-.8121

"<

3

I

o

-1.3121

/

/

j

TYPICAL
2S·C.
S.2SV

EXPECTED
MIN
8S·C.
4.7SV

I

!

:

I

/

:

/

/EXPECTED
MAX
-40·C.
S.7SV

I

-1.8121

I

/

"

/

-- ---

.....

-

r:---~'.~

/

I
I

-2.3121

-2.8121
121.121121

l.-----1.--l _ _

1. 121121

2.121121

:3.121121
VOH

4.121121

5.00

6.00

(VOLTS)

Figure 11-5. Port A VOH vs IOH
(with CMOS Pull-ups)
12.121121

1121.121121

8.121121

/
/

<

3
...J
0

/

EXPECTED
MAX
S.7SV
-40°C.

/

... TYPICAL
S.2SV
2SoC •

I

e.11J12I

I

/
/

4.121121

/ ......

2.121121

(O.4V. 1.6mA)

12I.11J12I
121.121121

• 1121

.2121

.3121

VOL

.411J

1
Clock
4>2

EXTALI

PAO
PAl
PA2
PA3

P

0

PA4

R
T

PA5

A

0
0
R

Accumulator
Index Register
Condition Code
Register

PA6

Stack Pointer

PA7

Program
Counter
Low

A/O Converter

Program
Counter
High

ANO/POD

ALU

AN3/PD3

AN1/POl
AN2/P02

RESET
Control
INTl

VRL
VRH
'-4--+-4--+-4--+--~~

Port 0

I

I

L--_~_AX_~---I~ ~
PBO
SPISS

* Includes 8

PBl
SPICL

PB2
SPIO

PB3
SPIO

bytes for interrupt vectors.

Figure 1-1. Block Diagram

3~398

INT2/
AN4/
VSTBY

MC6805S2

1.1 HARDWARE FEATURES

The following are some of the hardware features of the M C6805S2 M CU.
• A/ D Converter
8-Bit Conversion, Monotonic
Four Multiplexed Analog Inputs
Ratiometric Conversion
• 21 TTL Including Eight TTL/CMOS Compatible I/O Lines
14 Bidirectional (Four Lines are LED Compatible)
7 Input-Only
• 1480 Bytes of User ROM
•
•
•
•
•
•
•
•

64 Bytes of RAM
Self-Check Mode
Serial Peripheral Interface (SPI)
Zero-Crossing Detect/Interrupt
One 8-Bit and One 16-Bit Timer
One 7-Bit and One 15-Bit Software Programmable Prescaler
Three Bidirectional I/O Lines with TTL or Open-Drain Interface (Software Programmable)
Auxiliary Counter with "Watchdog" Reset Feature

• 5-Volt Single Supply
1.2 SOFTWARE FEATURES

The following are some of the software features of the MC6805S2 MCU.
• 10 Powerful Addressing Modes
• Byte Efficient Instruction Set with True Bit Manipulation, Bit Test, and Branch Instructions
•
•
•
•
•
•

Single Instruction Memory Examine/ Change
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Register/Flags
User Callable Self-Check Subroutines
Complete Development System Support on EXORciser, EXORset, and HDS-200 Available
Now

1.3 USER SELECTABLE OPTIONS

The following are user selectable options of the MC6805S2 MCU.
• Eight Bidirectional I/O Lines with TTL or TTL/CMOS Interface Option
• Crystal or Low-Cost Resistor Oscillator Option
•
•
•
•

Low Voltage Inhibit Option
Vectored Interrupts: Timer/ SPI, Software, and External
16-Bytes Standby RAM Option
Fifth A/D Channel Option

EXORciser is a registered trademark of Motorola Inc.
EXORset and HDS-200 are trademarks of Motorola Inc.

3-399

I

MC6805S2

SECTION 2
SIGNAL DESCRIPTION, MEMORY, CPU, AND REGISTERS
This section provides a description of the signals, memory spaces, the central processing unit
(CPU), and the various registers.
2.1 SIGNAL DESCRIPTION

The following paragraphs provide a brief description of the signals and a reference (if applicable) to
other paragraphs that contain more detail about the function being performed.
2.1.1 VCC and VSS

I

Power is supplied to the MCU using these two pins. VCC is power and VSS is the ground
connection.
2.1.2 INT1 and INT2

These pins provide the capability for asynchronously applying an external interrupt to the MCU.
Refer to 5.4 INTERRUPTS for additional information.
2.1.3 XTAL and EXTAL

These pins provide control input for the on-chip clock oscillator circuit. A crystal, a resistor, or an
external signal, depending on the user selected manufacturing mask option, can be connected to
these pins to provide a system clock source with various stability/ cost tradeoffs. Lead length and
stray capacitance on these two pins should be minimized. Refer to 5.3 INTERNAL CLOCK
GENERATOR OPTIONS for recommendations about these inputs.
2.1.4 Timer A/ PCO and Timer B/ PC1

These pins allow an external input to be used to decrement the internal timer circuitry. Refer to
SECTION 3 TIMERS for additional information about the timer circuitry.
2.1.5 RESET

This pin allows resetting of the MCU at times other than the automatic resetting capability already in
the MCU. The MCU can be reset by pulling RESET low. Refer to 5.2 RESETS for additional information.

3-400

MC6805S2

2.1.6 Input/Output Lines (PAO-PA7, PBO-PB3, PCO-PC1, and PDO-PD6)
Ports A, B, and C are programmable as either inputs or outputs under software control of the data
direction registers (DORs). Port 0 has up to four analog inputs or five via mask option, plus two
voltage reference inputs when the analog-to-digital (A/D) converter is used (P05/VRH, P04/VRl,
and an INT2 input). If any analog input is used, then the voltage reference pins (P05/VRH,
P04/VRU must be used in the analog mode. Refer to 6.1 INPUT/OUTPUT, 6.6 ANALOG- TODIGITAL CONVERTER (A/D), and 5.4 INTERRUPTS for additional information. Port 0 can also be
used as a 7-bit digital input-only port.
2.2. MEMORY
As shown in Figure 2-1, the M CU is capable of addressing 4096 bytes of memory and I/O registers
with its program counter. The MC6805S2 MCU has implemented 1802 of these locations. This consists of: 1480 bytes of user ROM including eight interrupt vectors, 248 bytes of self-check ROM, 64
bytes of user RAM, seven bytes of port 1/0, five timer registers, two AID registers, a miscellaneous
register, and two serial peripheral interface (SPI) registers. The user ROM has been split into three
areas. The first area is memory locations $080 to $OFF, and allows the user to access these ROM
locations utilizing the direct and table look-up indexed addressing modes. The main user ROM area
is from $9CO to $EFF. The last eight user ROM locations at the top of memory are for the interrupt
vectors.
The MCU reserves the first 18 memory locations for I/O features, of which 17 have been implemented. These locations are used for the ports, the port OORs, the timers, the miscellaneous
register, the SPI, and the A/D. Of the 64 RAM bytes, 31 are shared with the stack area, from $061
through $07F. The stack must be used with care when data shares the stack area. The lower 16
bytes of RAM, between $40 and $4F, may be powered through the INT2/P06 pin via a user-defined
mask option. Selection of this option does not exclude any of the available functions of the
INT2/P06 input.
The shared stack area is used during the processing of an interrupt or subroutine calls to save the
contents of the CPU state. The register contents are pushed onto the stack in the order shown in
Figure 2-2. Since the stack pointer decrements during pushes, the low order byte (PCL) of the program counter is stacked first; then the high order four bits (PCH) are stacked. This ensures that the
program counter is loaded correctly during pulls from the stack, since the stack pointer increments
when it pulls data from the stack. A subroutine call results in only the program counter (PCl, PCH)
contents being pushed onto the stack; the remaining CPU registers are not pushed.
2.3 CENTRAL PROCESSING UNIT
The CPU of the M6805 Family is implemented independently from the I/O or memory configuration.
Consequently, it can be treated as an independent central processor communicating with I/O and
memory via internal address, data, and control buses.
2.4 REGISTERS
The M6805 Family CPU has five registers available to the programmer. They are shown in Figure 2-3
and are explained in the following paragraphs.

3-401

I

MC6805S2

7 6

$000

000

AID, Timer, SPI
(128 Bytes)

127
128

$OFF
$100

256

3840

Timer (A, BI,
SPI, iNi2

Port B

$001

Port C

$002

Port D

$003

*
*

Port C DDR

$006

Not Used

$007

Timer A

$008

Timer A Control
Register

$009

Miscellaneous
Register

$OOA

TimerB MSB

$008

AID

Timer B LSB

$OOC

Timer B Control
Register

$OOD

Cantrall Status

$OOE

Result

$OOF

$FF7
$FF8

SPI Data

$010
$011

(248 Bytes)

4088

$000

$004

AID

4087

~

- - - - -

-

$FF9
$FFA

SPI
Cant roll Status

I-

- - - - - -

$FFB
$FFC

Not Used (46 Bytes)

External (INT1)

Q)

>

~

I-

- - - - - -

$FFD
$FFE

RESET

4095

$FFF

fl-

* Data direction registers (DDRs) are write only; they read as $FF
* * Mask Option

Figure 2-1. Address Map

3..402

$012

$03F
$040
$04F
1-------$050
RAM
$061
Stack (31 Bytesl
$07F
(Standby RAMI**

SWI

~

0 Hex

$005

Main ROM
(1344 Bytes)
$EFF
$FOO

1

Port B DCR

$9BF
$9CO

3839

2

PortA DDR

I
2495
2496

3

PortA

*

Future ROM
(2240 Bytes)

en

4

$07F
$080

Page 0 ROM
(128 Bytes)

255

~

5

1/0, RAM

MC6805S2

7
n-4

6

5

11 1

4

I

3

2

1

Condition
Code Register

Pull

n+1

n-3

Accumulator

n+2

n-2

Index Register

n+3

I

n+4

n-1

111 1

PCH*

PCl*

n+5

Push
* For subroutine calis, only PCH and PCl are stacked

Figure 2-2. Interrupt Stacking Order

°
°
~llndex
°

----II

L..-_ _ _ _
A_ _ _ _

L..-_ _ _ _X
____

11

8 7

----o1

'--_P_C_H_---"'_ _ _ _ _P_C_l_ _ _

11

Accumulator

Register

Program Counter

54

IL.0---L,.I_0J...I0--,-1_0..1.1_0-,-1_1~1_1...11_ _ _
s_p_ - - - I Stack Pointer
Condition Code Register
Carry/Borrow
Zero
L.......---Negative
'------Interrupt Mask
' - - - - - - - H a l f Carry

Figure 2-3. Programming Model

2.4.1 Accumulator (A)
The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic
calculations or data manipulations.
2.4.2 Index Register (X)
The index register is an 8-bit register used for the indexed addressing mode. It contains an 8-bit
value that may be added to an instruction value to create an effective address. The index register
can also be used for data manipulations using the read-modify-write instructions and as a temporary
storage area.

3-403

I

MC6805S2

2.4.3 Program Counter (PC)
The program counter is a 12-bit register that contains the address of the next instruction to be
executed.
2.4.4 Stack Pointer (SP)
The stack pointer is a 12-bit register that contains the address of the next free location on the
stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to
location $07F. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. The seven most significant bits of the stack pointer are
permanently configured to 0000011. Subroutines and interrupts may be nested down to location
$061 (31 bytes maximum) which allows the programmer to use up to 15 levels of subroutine calls
(less if interrupts are allowedl.

II

2.4.5 Condition Code Register (CC)
The condition code register is a 5-bit register in which four bits are used to indicate the results of the
instruction just executed. These bits can be individually tested by a program and specific action
taken as a result of their state. Each bit is explained in the following paragraphs. For more information concerning the condition code register refer to the M6805 HMOSIM146805 CMOS Family
Users Manual.
2.4.5.1 HALF CARRY (H) - Set during ADD and ADC operations to indicate that a carry occurred
before bits 3 and 4.
2.4.5.2 INTERRUPT (I) - When set, this bit masks (disables) the timer (both A and B), external
(INT1 and INT2), and the serial peripheral interface interrupts. If an interrupt occurs while this bit is
set, the interrupt is latched and is processed as soon as the interrupt bit is cleared.
2.4.5.3 NEGATIVE (N) - When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was negative (bit 7 in the result is a logic onel.
2.4.5.4 ZERO (Z) - When set, this bit indicates that the result of the last arithmetic, logic, or data
manipulation was zero.
2.4.5.5 CARRY IBORROW (C) - When set, this bit indicates that a carry or borrow out of the
arithmetic logic unit (ALU) occurred during the last arithmetic operation. This bit is also affected
during bit test and branch instructions plus shifts and rotates.

3-404

MC6805S2

SECTION 3
TIMERS
The MC6805S2 has three timers and two programmable prescalers (see Figure 3-1) which are
described in this section.

Select

I
To MCU

To MCU
Select

TBCR4,5

~

I nternal Clock

Figure 3-1. Timer A and B Block Diagram

3-405

MC6805S2

3.1 TIMER A

I

Timer A is an 8-bit programmable down counter, which may be loaded under program control (see
Figures 3-2 and 3-31. Included in this timer is a modulus latch which allows the timer to be "auto
reloaded." Address $08 is the location of TIMER A's data register. Upon every clock input received,
timer A decrements toward $00. Upon reaching this value, bit 7 in the timer A control register
(T ACR located at $09) is set, signifying a timer interrupt has been generated. At the same time, the
timer is reloaded with the contents of the modulus latch. I n addition to setting the interrupt bit, the
transition to state $00 also generates an overflow condition which can be used to toggle bit 0 or bit 1
of port B directly, under the control of the miscellaneous register bit 3 (MR3), the serial peripheral
interface control register, and the port B data direction register. The bit selected depends upon the
state of bit 0 of the miscellaneous register. The timer interrupt may be masked by setting bit 6 of the
TACR. Of course, the I bit in the condition code register will also prevent a timer interrupt from being processed. The timer interrupt vector locations are $FF8 and $FF9. The timer interrupt request
bit MUST be cleared by software.

$008

--~---,..--------r---r-~~.......- - { ~~:~:~:r

Overflow ....

Figure 3-2. Timer A

I TACR7 I TACR6 I TACR5 I TACR4 I TACR3 I TACR2 I TACRl I TACRO I
T ACR7 = Timer A Interrupt Request Flag
TACR6= Timer A Interrupt Request Mask
TACR5= External/Internal
TACR4= External Enable
TACR3=Timer A Load Mode Control
TACR2}
TACRl Prescaler 1 Divide Ratio Select
TACRO
TACR5

TACR4

Prescaler 1 Clock

0
0
1
1

0
1

Internal Clock
AND of Internal Clock-PCa
Clock Disabled
pca Positive Transition

a

1

Figure 3-3. Timer A Control Register

3-406

MC6805S2

There are three ways of loading data from the modulus latch into timer A as described in the following paragraphs.
3.1.1 Direct Loading

When the MCU writes to the timer A data register, the data is latched by the modulus latch, and
forced into the timer. For this operation, TACR bit 3 must be clear.
3.1.2 Asynchronous External Event Loading

When T ACR bit 3 is a logic one, the contents of the modulus latch are transferred to the timer at the
rising edge of the INT2 interrupt request bit (MR7) gated with interrupt request mask bit (MR6).
NOTE

If this feature is used, then care must be taken in programming as it will start an interrupt
service routine if the I bit in condition code register (CC) is clear.
Loading $00 to timer A allows a countdown of 256 clocks before next $00 state is
reached.
3.1.3 Auto-Loading

Auto-loading of the modulus latch occurs whenever the timer reaches the $00 state. This mode is
independent of the status of bit 3 in TACR.
NOTE

Loading modes 1 and 2 are mutually exclusive, and auto-loading occurs in both modes 1
and 2.
Timer A may be read at any time without disturbing the countdown mechanism of the timer. At
reset, both the timer and modulus latch contents are set to $FF.
NOTE

Loading $01 to timer A should be avoided when operating with a divide-by-one prescaler.
Doing so will inhibit timer A auto-loading, interrupt generation, and port B toggle
mechanisms.
3.2 TIMER A CONTROL REGISTER

Timer A control register (T ACR) occupies memory location $09 (see Figure 3-4). Five bits are
allocated to timer A and three bits are used to control prescaler 1.

3-407

I

MC6805S2

Timer A

FF

CC

I

AA

T

I
I
I
1

1

1
RESET

Timer A
Overflow

U

I

I

I

I

I

I

1

I

:

In

I

I

1

I

____~~IL~~~~L
I
I
I

[TACR3]

1

I

n--,--_~__t--L
1

[MR7]-[MR6]

',1

1

INT2
Interrupt

I
I

CC-[OS]

MCU Write

@

Direct Load

®
©

Auto Load
Asynchronous External Event Load

AA-[oS]

F'IQure 3-4. Timer
.
A Operation

3·408

MC6805S2

TACR7

Timer A Interrupt Request Flag
Set at the transition of timer A to $00 state. Cleared by software or at reset.

TACR6

Timer A Interrupt Request Mask
Set at reset or under program control. When set, timer A interrupt requests to the processor are inhibited. Cleared under program control.

TACR5

External or Internal Bit
Set under program control. When set, selects the input clock source for prescaler 1 to be
the PCO input, otherwise the internal clock (fosc divided by four) is the input clock
source. Cleared at reset or under program control.

TACR4

External Enable Bit
Control bit used to enable the external timer pin (PCG).
TACR5

T ACR3

TACR4 Prescaler

o
o

o

1

o

1

1

1

1 Clock Source

Internal Clock
AND of In'ternal Clock and PCO*
Inputs Disabled
PCO* Low-to-High Transition

Timer A Load Mode Control
Set under program control. When set, allows asynchronous external event loading of
timer A (INT2 driven loading is enabled). Cleared under program control or at reset.
When clear, allows direct loading of timer A. Auto-loading takes place independent of
T ACR3 status. Cleared by reset or by program control.

TACR2} Prescaler 1 Division Ratio Control Bits
TACR1
Set or cleared under program control, also cleared at reset. When set, these bits select
TACRO one of the eight possible outputs on prescaler 1.
TACR2

TACR1

TACRO

Prescaler 1
Division Ratio

1
2

000
o
0
1
010
o
1
1

1

o

0

0
1

1

0

1

1

4

8
16
32
64
128

3.3 TIMER B

Timer B is a 16-bit timer which is accessed via two registers at SOB for the most-significant byte
(MSB) and SOC for the least-significant byte (LSB) (refer to Figure 3-5), Included within the MSB of
timer B is a "pipeline" latch, which allows a "snap shot" value of the entire 16 bits to be read.

* The status of pea depends upon

the data direction status of pea. If pea is an output, then the clock source is equal to the port data
register content, independent of the port electrical loading. If an input, then the clock source is the logic level of pea.

3-409

II

MC6805S2

Selected
{ Prescaler

v-------------./
MCU Write LSB SOC:
MCU Write MSB SOB:
MCU Read LSB SOC:

I

MCU Read MSB SOB:

MCU Data Bus

MCU-[Timer B LSB]
{ [Po Latch W]-[Tjmer B MSB]
MCU -

[P Latch W]

[Timer B LSBJ-MCU
{ [Timer B MSBJ - [P. Latch RJ
[Po Latch RJ-MCU

Figure 3-5. Timer B

Read/write operations to the LSB are direct. Reading the LSB can occur at any time without disturbing the count. At the time of the LSB read, the contents of the MSB are loaded into the pipeline
latch, so when the MPU reads the MSB, it actually reads the latch.
Writing to the LSB of timer B may occur at any time, and the contents are immediately entered into
the timer. At the same time the contents of the pipeline latch are forced into the MSB of the timer.
Hence, a 16-bit word may be placed into the entire timer data register during a LSB write operation.
In order to manipulate a 16-bit word in timer B during a read, it is recommended that a read of the
LSB be done first, then the MSB. A 16-bit write should be done in the opposite order. (First, write
the MSB and then the LSB.) After reset, timer B contains $FFFF.
Like timer A, timer B decrements toward zero upon every clock input received and during the transition to state $00 TBCR7 in the timer B control register is set (TBCR is located at $OD).
The timer interrupt can be masked by setting the timer interrupt mask bit (TBCR6) (Figure 3-6). The
I bit in the condition code register will also prevent a timer interrupt from being processed. The
M CU responds to a timer interrupt by saving the current M CU state in the stack, fetching the vector
from $FF8 and $FF9, and executing the interrupt routine. The timer interrupt routine bit MUST be
cleared by software.

I TBCR7 I TBCR6 I TBCR5 I TBCR4 I TCBR31
TBCR7 =
TBCR6=
TBCR5=
TBCR4=

TBCR2

I TBCRl I TBCRO I

Timer B Interrupt Request Flag
Timer B Interrupt Request Mask
External/Internal
External Enable

TBCR5

TBCR4

Prescaler 2 Clock

0
0

0

Internal
AND of Internal Clock-PCl
Clock Disabled
PCl Positive Transition

1
1

TBCR3}
TBCR2
.
TBCRl Prescaler 2 Divide Ratio Select
TBCRO

Figure 3-6. Timer B Control Register

3·410

·1

0
1

MC6805S2

The transition to $00 generates an overflow pulse which may be used to force a port B data register
toggle under the control of the miscellaneous register bit 3 (M R3), the S PI control register, and the
port B data direction register. (See 6.5 MISCELLANEOUS REGISTER and 4.3 SERIAL
PERIPHERAL INTERFACE CONTROL AND STATUS REGISTER.)
3.4 TIMER B CONTROL A STATUS REGISTER

Timer B control and status register (TBCR) occupies memory location $00 (see Figure 3-6). Four
bits are allocated to timer B and four bits are used to control prescaler 2.
TBCR7

Timer B Interrupt Request Flag
Set at the transition of timer B to $00. Cleared by software or at. reset.

TBCR6

Timer B Interrupt Request Mask
Set at reset or under program control. When set, inhibits timer B interrupt requests to the
processor. Cleared under program control.

TBCR5

External or Internal Bit
Set under program control. When set, selects the input clock source for prescaler 2 to be
the PC1 input, otherwise the internal clock (fosc divided by four) is the input clock
source. Cleared at reset or under program control.

TBCR4

External Enable Bit
Set under program control or at reset. When set, this bit enables the external timer pin
(PC1). Cleared under program control.
TBCR5

o
o
1
1

TBCR4 Prescaler 2 Clock Source
o Internal Clock
1
AND of Internal Clock and PC1 *
o Inputs Disabled
1
PC1 * Low-to-High Transition

Prescaler 2 Division Ratio Control Bits
TBCR3}
TBCR2 Set or cleared under program control. When set, these bits select one of the 16 possible
TBCR1
outputs on prescaler 2. All bits are cleared at reset.
TBCRO

* PCl

sta~us depends on the data direction status of PC1. If PCl is an output, then the clock source is equal to the port data register con·
tent, independent of the port electrical loading. If an input then the clock source is the logic level on PCl.

3·411

II

MC6805S2

TBCR3 TBCR2 TBCR1
000
000
001
001
010
010

o
o

I

TBCRO

o
1

o

8

o

16
32
64
128
256
512
1024
2048
4096
8192
16384
32768

1

o

1
1
1
1
1
1

o

1
1
0
0
1
1

4

1

1
1
1
1
100
100
0
0
1
1
1
1

Division Ratio
1
2

1

o
1
1

o
1

o
1

3.5 PRESCALER 1

Prescaler 1 is a 7-bit binary down counter whose value is selected by TACR2, TACR1, and TACRO.
The selected output is used as the clock input to either timer A or timer B, depending upon the
status of the prescaler cross-couple bit (M R1). The type of clock source to prescaler 1 may be
selected by TACR5 and TACR4 (see 3.1 TIMER A).
Prescaler 1 is set to $7F at reset or under program control when a one is written to prescaler 1 clear
bit (MR3).
NOTE
When changing outputs on the prescaler, a prescaler clear should be done first to avoid
truncation errors.
3.6 PRES CALER 2

Prescaler 2 is a 15-bit down counter whose value is selected by TBCR3, TBCR2, TBCR1, and
TBCRO. The selected output is used as the clock input to either timer A or timer B, depending upon
the status of MR1. The type of clock source to prescaler 2 can be selected by TBCR5 and TBCR4
(see 3.3 TIMER B).
Prescaler 2 is preset to $7FFF at reset, under program control when a logic one is written to
prescaler 2 clear bit (M R2).
NOTE
When changing outputs on the prescaler, a prescaler clear should be done first to avoid
truncation errors.

3.7 AUXILIARY COUNTER
The third timer register in the MC6805S2 is the auxiliary counter, or "watchdog" timer. It is a fixed
counter which is clocked by the internal clock (fosc divided by fourl. The total count period is 4095

3-412

MC6805S2

cycles. The MCU communicates with this counter via the miscellaneous register bits 5 and 4 (MR5,
MR4l. Upon overflow, the auxiliary counter control/status bit in the miscellaneous register (MR5) is
set. Countdown may be aborted at any time under program control, which also will reset the
counter to 4095. To do this, the MCU must write to MR5 the inverse of what is read from MR5.
At reset, the counter is preset to its maximum count of 4095, and MR5 is cleared. The value of the
counter is not accessible to the MCU; however, the possibility of detecting an underflow and
presetting it at any time under program control allows it to be used as a fixed rate polled timer in applications requiring lengthy time out periods.
When the auxiliary counter reset mask bit in the miscellaneous register (MR4) is clear and the MR5
is set as a result of counter time out, the reset pin is internally pulled to ground (VSSl. This feature
is useful in many applications, e. g., automotive, where the M CU operates in a noisy environment.
Due to high energy spikes on the power supply and I/O lines, the MCU may lose control of the program and execute through non-valid memory space. The "watchdog" timer will bring the MCU
back to reset. M R4 is automatically set at reset or under program control.
To return from a catastropic system runaway, the reset line is pulsed, which will restart the entire
program. This program should regularly preset the auxiliary counter at a rate higher than the
counter time out so as not to allow a forced reset. If program runaway does occur, it is likely that
regular presetting of the auxiliary counter will not take place, and an overflow will force the MCU to
regain control. (See Figure 3-7.)

3-413

I

MC6805S2

I
External Reset

[MR4J

I

L/vIRES+

I
I

~A

I

I

fl£D \

I

MCUWrite

®

Forced Reset"" I

I

I

I[MR5J=1~1

I

I

I

l/[MR5J=0
I

I

I

I

J
I

I

I

I

I

I

I

I

I

1-[MR5J

1--[MR4J

0-[MR4J

o
o
o

I

Time

I

I

Reset

[MR5J

~I

I

I
0-[MR5J

Counter Preset by Writing "1'
Overflow: MR5--1; No Forced Reset
Counter Reset by Writing "0"
Overflow M R5 --1 Forced Reset

Figure 3-7. Auxiliary Counter Operation

3-414

VIRES-:Ks+

L
Lr
I

I
0--[MR4J

MC680552

SECTION 4
SERIAL PERIPHERAL INTERFACE (SPI)
This section describes the operation of the serial peripheral interface (SPI) on the MC6805S2.

4.1 INTRODUCTION
The serial peripheral interface (SPI) on the MC6805S2 has several versatile operating modes. Arbitration on data and clock lines is provided. The SPI communicates with the MCU via data and
control registers located at memory addresses $10 and $11, respectively. Operation of the S PI occurs via port B (see Figure 4-1).
The SPI consists of:
a) an 8-bit shift register (MSB out first; MSB in first) which may also be used as an SPI data
register,
b) a divide-by-eight counter,
c) slave select/ arbitration logic,
d) an SPI control register, and
e) start and stop bit detection capability.
Unlike the 1/0 port operation, the SPI data and clock inputs are always taken from their respective
110 port pins, regardless of the status of the data direction register relative to that port. This makes
it easy to do data and clock arbitration.

Serial peripheral interface operation is enabled when the SPI enable bit (SPICR4) is set. When
enabled, the SPI is capable of operating in the following modes:
a) one wire - auto clocked (e.g., NRZ),
b) two wire - half duplex,
c) two wire - half duplex with clock arbitration,
d) three wire - half duplex with slave select/busy line,
e) three wire - full duplex,
f) three wire - full duplex with clock arbitration, and
g) four wire - full duplex with slave selectlbusy line.

4.2 SPI TERMINOLOGY
The following explanations are provided to facilitate user understanding of the various operating
modes of the serial peripheral interface (see Table 4- 1).

3-415

II

MC6805S2

I
Direction
Register
DDR 81
Clear

Data In
Strobe

MRO

Figure 4-1. Serial Peripheral Interface (SPI)

3-416

MC680552

Table 4-1. SPI Operation
DEFINTIONS
Transmitter - Data Master: DDRB2 or 3= 1
Receiver - Data Slave: DDRB2 or 3=0
Clock Master: DDRB1 = 1
Clock Slave: DDRB1 =0
Transaction Mode: SPICR4= 1
1) Active: SPICR7-IDDRBO-PBO+ DDRBO) if DDRB1 =0 (clock slave mode) or
SPICR7-IDDRBO-PBO+ DDRBO) if DDRB1 = 1 (clock master mode)
Clock pulses allowed, data shifted
2) Idle: SPICR7+ DDRBO-PBO if DDRB1 =0 (clock slave mode)
Clock pulses blocked, data output line in high-impedance state
Deselect Mode: SPICR4=0- No SPI Operations
SLAVE SELECT INPUT
Slave Select Input: SPISS - PBO
If DDRBO=O then no SPISS action on MCU
1) Master Mode SPISS=l DDRB1=1
SPISS 1 - 0: Switch to Slave Mode IDDRB1 1-0)
Set SPICR1 (Mode Fault Flag)
2) Slave Mode SPISS = 0
DDRB1 = 0
External clock is allowed to shift data in/out. If SPISS is pulled high, the external clock input pulses are
inhibited; no data shift; divide-by-eight counter cleared; SPID (PB2 or PB3) switched to highimpedance state
Used as Chip-Select Input
DATA ARBITRATION
Data master loses data mastership when data collision occurs during internal data strobe time
If SPID output port (PB2 or PB3) = 1 while actual pin level is pulled low externally - conflict detected at internal
data strobe time.
Then SPICR1 (mode fault flag) is set; .sPID output port DDR (B2 or B3) 1-0 (high-impedance state)
CLOCK ARBITRATION
MCU has clock mastership (DDRB1 = 1)
1) Via SPISS line (DDRBO=O). If SPISS is pulled low, then clock mastership lost; DDRB1 1-0 (highimpedance state); SPICR1 is set (mode fault flag).
2) Via clock line SPICl (DDRB1 = 1 and DCRB5=0)
Condition: SPICl must have open-drain output (DCRB5 = 0)
If clock line is held low externally then clock mastership is not lost; minimum tClH and tClK
times are guaranteed.
If SPICl goes low during idle mode then SPICR1 = 1 and clock line is switched low to inhibit
the system clock
MODE FAULT FLAG OPERATION (SPICR1)
Flag set when any of the following conditions occur.
Data arbitration occurs on SPID output.
Clock arbitration with SPISS during master to slave switching
Clock arbitration via clock line if SPICl 1 - 0 during idle.
START, STOP, AND CLOCK IDLE CONDITIONS
Clock Idle: The clock level just prior to the transition that causes data on the serial output data line to be changed is
defined as the S PI clock idle state.
SPICR5=0: SPICl Idle= low State
SPICR5= 1 SPICl Idle= High State
These definitions are necessary for determining start and stop conditions

NOTE
Clock idle state can only be defined if SPICR4=0 (Deselect Mode)
Start Condition: Any negative transition of the data input line (PB2 or PB3) during an SPICl idle state.
Stop Condition: Any positive transition of the data input line during an SPICl idle state

3-417

I

MC6805S2

4.2.1 Clock Mastership

The SPI clock source is always taken from port B 1. When the clock level on pin PB 1 is defined by
the MCU, it is said that the MCU has clock mastership. The principle condition for clock mastership
during an S PI operation is that port B1 must be initialized by its DDR bit so that the port is in the
output mode. When PB1 DDR is clear (i.e., configured as an input) during an SPI operation, and
external device provides the SPI clock on pin PB1. This is referred to as the "clock slave" mode.
4.2.2 Data Mastership

I

SPI data transactions (transmission/reception) can occur through port B2, port B3, or through both
of these ports as determined by the software. The MCU is said to have data mastership when the
data output on the selected data output port is defined by the processor. T·he main requirement for
data mastership during an SPI operation is that the selected SPI data output port, PB2 or PB3, be
initialized by its DDR bit to be in the output mode. Routing of output data to the proper port data
register is done by SPICR3. The MC6805S2 may be a "receiver" in any mode of operation.
4.2.3 SPI Transaction Mode

This is the mode where the S PI is allowed to operate (see Figure 4-2). Operation takes place via port
B lines. SPI transactions are enabled when the SPI control register bit 4 (SPICR4) is set.
4.2.4 SPI Deselect Mode

SPICR4 is clear in this mode. All SPI operations and actions relative to the SPI operation are
blocked in the SPI deselect mode. This mode is selected at reset.
4.2.5 SPI Active Mode

The SPI active mode is part of the transaction mode (Figure 4-3), In addition to the transaction
mode requirements, the two following requirements must be met for the MC6805S2 to operate in
the SPI active mode: 1) SPICR7 = 0, and SPISS (port Bo) = 0 if PB1 DDR = 0 (clock slave mode) and
2) SPICR7 = 0 and SPISS = 1 if PB1 DDR = 1 (clock master mode). In this mode, the SPI clock
pulses are allowed to shift serial information.
4.2.6 SPI Idle Mode

This is part of the transaction mode and is characterized additionally by 1) SPICR 7= 1 or 2) slave
select input (port Bo)= 1 if DDRB1 =0 (clock slave mode). In this mode all SPI clock pulses are
blocked and, if the MCU is in the clock slave mode, the serial data out line is forced to high impedance if slave select input PBO= 1. In this mode the MCU is processing serial data or is deselected
under external control.

3-418

MC6805S2

Deselect Mode
Active

(SPICR41

~
r-,

SPICl~ _
(SPICR7)

_________________~III
_

Internal Data

I~~r~~;

--LI,-I--Jlul_

IIIIII

___

I

SPISS

B-[SPICR71

I

I
8

I

Condition:

"" "
1

2

SPID Out

SPICl

(SPICR7)

Data Out
Strobe

Data In
Strobe

SPID Out

------

===>(1.-_____

Figure 4-2. SPI Operation (Example: Clock Slave Mode)

3-419

3

/I II
1

2

I

MC6805S2

SPiel

SPID Out

.~ I
E

Output Data
Strobe

~

-~~

Input Data
Strobe

SPID Input

==X_~X~----JX\------JX\--_

~

n

n

SPID Out

Output Data
Strobe

HI
-~~

Input Data
Strobe

SPID Input

n

n'---_

L
XXXXXXXXXXXXXXXXXXXXXX

~n

~ ~

I

n

o
II

LO

a:

u

c::

~

Valid Data

_---JX\------JX~__JX"""'___>C

-----,n
n n L
--.n
n
n n'---_
roXXXXXXXX>cxXXXXXXXXX
~ ~

Valid Data

Figure 4-3. SPI Clock (Active Transaction)
4.3 SPI CONTROL AND STATUS REGISTER

This register, illustrated in Figure 4-4, contains the status and control bits related to S PI operations.
SPICR7

SPI Interrupt Request Bit
This bit is cleared at reset or under program control. When the eighth SPI data input
strobe is detected from the SPI clock input this SPI interrupt request bit becomes set.
When set, it forces the SPI into the idle mode. It remains in the idle mode until it is serviced. Only if SPICR7 is not masked by SPICR6 i's the processor allowed to receive an interrupt request. The processor services this interrupt if the I bit is clear in the condition
code register. It does so by fetching the interrupt vector from addresses $FF8 and $FF9.
As long as SPICR7 is set the SPI remains in the idle mode during SPI transactions.
SPICR7 is also cleared at the zero to one transition of SPICR2 due to a "start bit" detection during the transaction mode.

SPICR6

SPI Interrupt Request Mask Bit
This bit is set at reset or under program control. When set, it inhibits interrupt requests
from SPICR7. This bit is cleared under program control, or at the zero to one transition of
SPICR2 due to a "start bit" detection during the transaction mode.

3-420

MC6805S2

Interrupt
Request
To CPU

From
PB1 Pin

Shift
To PB3
Data "Register

$10
LSB

MSB
SPI Data Register

To PB2
Data Register

From
PB3 Pin
From
PB2 Pin

Figure 4-4. SPI Control Register Operation
SPICR5

SPI Clock Sense Bit/ Bus-Busy Flag
This is a dual-function bit controlled by the status of SPICR4. The function of this bit is
the following:
SPICR4

o
1

Mode
SPI Deselect
SPI Transaction

SPICR5 Function
SPI Clock Sense Bit (Read/Write)
SPI Bus-Busy Flag (Read Only)

If the SPI is in the deselect mode (SPICR4=0), SPICR5 becomes a read/write bit that
controls the clock sense and SPICl idle level. When low, this bit causes SPI input data to
be latched into the SPI data register on the negative edge of the SPI clock and output
data to be changed on the positive edge of the SPI clock. This corresponds to a low
SPICl idle level. When high, input data is latched on the positive edge and output data
changed on the negative edge of the SPI clock. This corresponds to a high SPICl idle
level. Data in the S PI data register is shifted by one location to the left at the SPI clock
edge that latches SPI input data. This clock edge is referred to as the data input strobe.
During SPI operation (SPICR4= 1), SPICR5 becomes a rea.d-only bit that serves as a
"bus-busy" flag. This flag is set due to a start condition and cleared due to a stop condition or at reset. A received MCU or a clock slave can poll this flag to determine the appropriate time to "capture the bus" and become a transmitter or clock master. This flag
provides a "clean" hook-unhook mechanism to the serial bus to allow true multi-master
operation.
In a properly ordered system, only one MCU has data mastership between a given start
and stop condition. Outside this busy lone, the serial bus is considered free and is

3-421

I

MC680SS2

signalled to the MCUs via the bus-busy flag. In the case that more than one processor attempts to gain access to the bus during this free zone, a normal data arbitration will take
place. The MCUs with low priority can then get off the bus and remain as slaves until the
next free zone.
SPICR4

SPI Operation Enable Bit
This bit is cleared at reset or under program control. When set under program control, it
allows SPI operation and actions relative to it. When it is cleared, the divide-by-eight
counter is reset; the SPI data register is disabled from shifting; and data and clock arbitration logic, as well as the slave select input logic, actions are inhibited. logic status of this
bit determines which of the dual functions is performed by SPICR2 and SPICR5.

SPICR3

SPI Data Output Select Bit
This bit is cleared at reset or under program control. When set under program control,
this bit allows the output of the SPI data register to be loaded to the port B3 data register
at the appropriate SPI clock edge selected by SPICR5, during the active transaction
mode. When clear, the port B2 data register is loaded with the output of the S PI data
register at the appropriate S PI clock edge during the active transaction mode.

SPICR2

Port B1 Toggle Enable/Start Bit
This is a dual function bit controlled by the status of SPICR4. The function of this bit is
the following:

II

SPICR4

o
1

Mode
S PI Deselect
SPI Transaction

SPICR2 Function
Port B 1 Toggle Enable
Start Bit

During non-SPI operations (SPICR4=0), when set under program control, SPICR2
enables port B 1 data register toggle facility. Its prime use is in applications where continuous toggle operation may be required. This bit is cleared under program control or at
reset.
During SPI operation (SPICR4= 1), this bit is set by the negative transition of the data input of the SPI data shift register while the clock is in its idle level. The (SPICL) idle level is
defined as the high level of SPICl if SPICR5= 1 or the low level of SPICR5= O. Note that
SPICR5 must be defined during the SPI deselect mode (SPICR4=O).
At the protocol level, this means that a "start" condition may be defined as an exceptional change of state of data input while this condition does not occur or should not be
allowed to occur during the data transmission. "Start" condition information may be
used to distinguish address and data transmissions, as well as transmission resync after
transmission synchronization has been lost. This bit is cleared or set under program
control.
SPICR1

Mode Fault Flag
This bit is cleared at reset or under program control. It is set under. the following
conditions:

3-422

MC6805S2

1) When SPI data output arbitration occurs on the SPI data output port (PB3 or PB2)
selected by SPICR3, the SPI data output port DDR is cleared (switches to highimpedance state), MCU loses data mastership, and the mode fault flag is set.
2) When the MCU has clock mastership (i.e., port B 1 DDR = 1), slave select input PBO, if
used as such in the application, should stay high. If a low level is detected on this input, then the MCU loses clock mastership, switches to clock slave mode, the port B1
DDR is cleared, and the mode fault flag is set.
3) When the MCU operates in the master mode where clock arbitration is done via the
clock line, then the mode fault flag is set during the idle mode when a negative clock
edge is detected on the SPI clock input. Simultaneously the port B1 data register is
cleared.
This feature allows the MCU to detect that some other device has attempted to drive the
SPI clock input while the MCU was not ready to perform a serial transaction; or that MCU
has lost data mastership or clock mastership.
SPICRO

SPI Input Data Select Bit
This bit is cleared at reset or under program control. When set under program control, it
allows SPI data from port B3 to be latched into the SPI data register. When clear, SPI
data from port B2 is routed to the input of the S PI data register.

4.4 SPI DATA REGISTER
This register can be written into at any time. It can be read "on the fly" irrespective of serial operation without disturbing the data. Data is shifted left by one bit every time there is a data input strobe
while the LSB is loaded with data from port B2 or B3 according to the status of SPICRO.
The MSB is loaded to the data register of port B2 or B3 according to the status of SPICR3 every
time there is a data output strobe. Data input and output strobes are generated during the transitions of the SPI clock input to the MCU under the control of SPICR5. Data input and output strobes
are generated internally only during the active transaction time.
4.5 SPI DIVIDE-BY-EIGHT COUNTER
This counter is cleared during SPI deselect or idle modes. It counts at every data input strobe during
the SPI active transaction mode. At overflow, it sets SPICR7, which in turn puts the SPI in the idle
mode and blocks all data input and output strobes. This counter is also cleared when the slave
select input (PBG) is high while the MCU is operating the SPI with slave select in the slave mode, or
when a "start" condition is detected. Clearing of the counter by the "start" condition allows resynchronization of data transmission between MCUs.

3-423

I

MC6805S2

4.6 SPI OPERATION

The SPI may operate in a variety of ways depending on user application needs. The main modes are
described below; however, this list is neither exhaustive nor absolute. Software assisted protocols
may be defined to upgrade the hardware versatility and/ or system performance of the MC6805S2.
Some features common to all operating modes are outlined below.
1) The SPI data input and output paths may be individually routed under program control via
SPICR3 and SPICRO to or from either PB2 or PB3 (see Table 4-21. This gives rise to four
possible routings useful in half duplex and full duplex operations, as well as allowing bidirectional information to flow in daisy-chained systems.

I

2) When data input and output is done on the same pin (PB2 or PB3), i.e.,
SPICR3 e SPICRO= 0, then half duplex operation takes place. The unused port line (PB2 or
PB3) is free for any other use.
3) Data input is always relative to the port pin logic level regardless of the data direction
register status on that pin.
If SPICR3e SPICRO=O, then in case of data arbitration on the data output line, the data input to the SPI data register is always equal to the logic level imposed on the data input pin
by the device which wins the data arbitration.
Table 4-2. Port B Status During SPI Operation
Port
Name

Comments

Use

Input

Output

PBO

SPISS
Data

Yes
No

No
Yes

Used as slave select input
Used as "busy" signal or any digital output

PBl
PBl

SPICl
SPICl

Yes
No

No
Yes

Clock slave
Clock master

PB2
PB2
PB2

SPID
SPID
Data

Yes
No
Yes

No
Yes
Yes

SPI data input SPICRO=O
SPI data output SPICR3=O
Any digital signal S PI CR3 = 1

PB3
PB3
PB3

SPID
SPID
Data

Yes
No
Yes

No
Yes
Yes

SPI data input SPICRO = 1
SPI data output SPICR3= 1
Any digital signal SPICR3 = 0

pso

4) When full duplex operation is required, then SPICR3 e SPICRO= 1. In this mode, 16 bits of
information may be transferred with eight clock pulses between ,at least two devices with
transmit capability. In this mode both PB2 and PB3 are used for SPI data transfer.
Moreover, the same shift register is used for data out and data in. Thus, the byte transmitted is replaced by the byte received, removing the need for separate status bits for XMIT
EMPTY and REC FULL. A single status bit, SPICR7, is used to signify thatthe input/ output
operation is complete.
5) The SPI clock is always provided on port B1. In the clock slave mode, the port B1 DDR is
clear (i.e., input model. In the clock master mode, the port B1 DDR is set and hence the
MCU imposes the clock level on pin PB1 until there is clock arbitration on the clock line or
until the MCU loses clock mastership when the slave select input PBO goes low.

3-424

MC6805S2

6) Clock pulse generation in the case of clock mastership is accomplished via the data register
toggle facility provided on port B1. According to the status of M RO, the overflow pulse of
either timer A or B is used as a toggle clock source during the active transaction time.
Hence, the port B1 data register changes state every time there is a timer overflow. Clock
frequency generated by this method is therefore half the overflow frequency of the selected
timer. There is no fixed baud rate generation. The clock frequency is dependent on the
prescaler clock source option, prescaler divide ratio, and timer divide ratio as well as the port
C status in case of external clocking for the timer. Toggling of the port B1 data register is
automatically allowed during the active transaction mode.
7) For correct transfer of data between devices connected to the SPI, all devices must have
their output data strobe and input data strobe on the same clock. edges.
8) For proper transmission, the first clock edge during the active transaction mode must be the
output data strobe. When this occurs, the MSBs of the data registers of all transmitters are
copied on to the data output pins (e. g., this is valid for devices with such output capability)
and the MCU copies the MSB of its SPI on to the port B2 or B3 data register, according to
SPICR3 status.
On the opposite clock edge, all receivers internally generate the data input strobe and shift
by one location the contents of the SPI data register. Data for the receivers is assumed to be
stable on this clock edge. Hence, error-free master-slave type serial data transfer is accomplished. It is therefore important that before a serial data transf~r starts, the master
clock level has to be initialized under program control so as to create an output data strobe
on the initial SPI clock edge.
NOTE
If the initial clock edge is the input data strobe, the M S B of all receivers are lost,
and transmitted MCU data will have a framing error. However, if a peripheral
transmitter device (without the selective data output and input strobe feature) is
transmitting data to the M CU, then, the first clock edge should generate the data
input strobe for the MCU.

9) The data direction registers of port B are always accessible during SPI operation. This is also
true for data control registers of port B which control open-drain enables and the port B output toggle enables (oCR7 through DCR4). However, during SPI active transaction mode,
the following data registers are not write accessible under program control:
a) PB1 data register;
b) PB2 data register if SPICR 3= 0, and
c) PB3 data register if SPICR 3= 1.
This allows write instructions to port B lines not used for SPI operation during the active
transaction mode without affecting the contents of data registers used for SPI.
10) The toggle enable of the port B1 data register is asserted during the active transaction mode
by the SPI logic. This starts the generation of SPI clock pulses if the MCU has the clock
mastership. If the MCU is in the clock slave mode (ODR B1 = 0), then an external device
provides the clock pulses.

3-425

I

MC6805S2

11) Port B lines not used for SPI can be used for other digital functions, e.g.; a) in half-duplex or
one-wire operation the unselected SPI data port may be used as I/O, and b) port BO may
always be used as digital output in the modes where SPI operates without slave select
input.
4.7 START BIT OPERATION
In all operating modes of the SPI, it is implied that all data transmissions are sensitive to the clock
edges. Depending on the state of SPICR5, data changes either as the result of the rising or falling
edge of the clock SPICl.

II

The clock level prior to the transition that causes data on the serial data line to be changed is called
the "idle" level. It is assumed that data must be stable just prior to and during the idle level during
transmission.
Optional creation of an exception to this rule may be interpreted as additional information such as to
1) signal the beginning of a transmission; 2) to separate address and data fields and/ or 3) to synchronize transmitter and receivers.
Negative transition of data input while the clock line (SPICL) is in its "idle" level is being defined as
an exceptional condition on the MC6805S2 SPI. This condition causes SPICR2 and SPICR5 to be
set and is defined as the start condition.
The rising edge of SPICR2 causes the divide-by-eight counter, SPICR7 and SPICR6 to be cleared.
Refer to Figure 4-5 for clock idle level definition, to Figure 4-6 for the start bit definition, and to
Figure 4-7 for stop bit definition.

/f

SPICl
SPID (82 or 83)

L

l
----~lX),..--------:X~,.--------} (;~~~:d=~uring
OOk

IdI, L,,,I

•

.

_ •

Deselect
Mode: SPICR4=0)

Output

spiel

SPID (82 or 83)
Output

.....--"\--..II
----..-O\X,.--------"X,.--------I
•

-,)

•

•

•

Figure 4-5. SPI Clock Idle Level Definition

3-426

SPICR5= 1
(Defined During Deselect
Mode: SPICR4= 0)

MC6805S2

SPI Data In

tL______-JWd1~~
1 = Clock Idle level

o
SPICl
JfStart Bit Set

SPICR2

1'--;....------------ -----1

r

/Cleared via
Software

SPICR5=1
(Defined During Deselect
Mode: SPICR4=OI

L _ _ _ _ _ _ _ __

/BuS-Busy Flag Set
SPICR5

SPI Data In

0= Clock Idle level

I

o
,Start Bit Set
SPICR2

_ /Cleared via

~r~--------------~

SPICR5=0
(Defined During Deselect
Mode: SPICR4=OI

SO_ft_w_a_re____________

J(BUS-BUS Y Flag Set
SPICR5

~
Figure 4-6. SPI Start Bit Definition

SPIDatain

____

~

f
1 = Clock Idle level

•

SPICR5=1
(Defined During Deselect
Mode: SPICR4= 01

tBUS-BUSY Flag Cleared
SPICR5

SPIDatain

SPICl

SPICR5

T
f
L __ .--J -- IL___....
F--

____

-

-

__

O_=_C_I_OC_k_l_dl_e_l_evel

rBUS-BUSY Flag Cleared

Figure 4-7. SPI Stop Bit Definition

3-427

SPICR5=0
(Defined During Deselect
Mode: SPICR4=01

11

MC6805S2

4.8 ADDRESS AND DATA FIELD SEPARATION

In systems connected together on a serial bus without individual chip-selects for individual elements
connected to this bus, serial transmission must convey not only data but the address of the receiver
element to which data is sent. Since all transmissions are byte long, recognition of address from a
data pattern is not possible unless the address can be distinguished from data by a start bit. In many
standard accepted systems, an address field follows a start condition which is then followed by a
number of data fields depending on the transaction relative to that address.
Detection of this start condition sets SPICR2, hence at the end of an 8-bit transmission it is possible
to check if the received byte corresponds to address or data fields. It must be emphasized that a
start condition does not occur normally during the transmission but it is provoked by the transmitter, prior to address field transmission.

I

Secondly, zero-to-one transition of SPICR2 caused by the start condition causes the divide-by-eight
counter to be cleared, hence allows all receiver MCUs to be synched-up simultaneously.
The third important consideration is the rate of occupation of the MCU in serving the information
flow on the serial bus with respect to the background tasks.
In case of high-speed transmissions (up to lOOK Baud) and heavy information flow not related to a
given MCU on the serial data bus, it is possible, if no precaution is taken, that a non-selected
receiver MCU has to analyze every field; data or address, to check for a particular address field that
is of concern. This causes a very high interruption rate to service the SPI and leaves very little time
for background tasks. In order to mask an undesirable data field transmission, that requires interrupt driven analysis, SPICR6 may be set and SPICR2 can be cleared after analyzing an invalid address field. Then, the MCU becomes immune to all SPI interrupt requests due to subsequent data
fields. On the next start bit preceding a new message, SPICR2 is set which in turn causes SPICR7
and SPICR6 to be cleared. The MCU is then ready to service an incoming new address field via
interrupt.
Refer to Figure 4-8 which illustrates the time for SPI address and data field separation (reception).
4.9 DATA FIELD ONLY OPERATION

In applications where: 1) only data patterns are transmitted or 2) the effect of the rising edge of
SPICR2 having cleared SPICR6, SPICR7, and divide-by-eight counter needs to be inhibited, it is
sufficient to set SPICR2 under program control before transmission. SPICR7 and SPICR6 are not
cleared by the software controlled setting of SPICR2.

3-428

MC6805S2

(a) Address Recognized

t

+~Bit

t

Address Field

Dat;~~ 1 1111111 II

Data Field

III "III1

(SPICR5=O)*

Start Bit

t

SPICl

~ Data Field N

__ 111111111 __

~essField

n 11111""

__ U1lJUUL __ ~
8

SPICR2

J

8

____.J

IO--SPICR2

SPICR6

o
SPICR7

-~m1
MCU

mO~SPICR7

O--SPICR7

InterruPts~

MCU Interrupts
MCU Treats
And Accepts Address
SPICR2--0

~

MCU Interrupts

ffl__

~

MCU

+
t
+
la. . .-. .II. . .III
. . . . . .I1. . . .II_...&..L.II~III
...
. .II~11
. . . ___ 111111111 __

SPI Data

+

Address Field

Data Field

Data Field N

n

111111111

:=L

J_---+--'I

SPICR6

SPICR7

Start Bit

~ress 'Field

__ JlllIlJlIll __ ~

SPICl

SPICR2

InterruPts~

MCU Treats
New Address Field

MCU Treats
Data Field

(b) Address Not Recognized

~t

nI

---11 v////J/J//J//I2=~!I!l//IIZ~~7J
MCU Interrupts

~

~

MCU Does Not Interrupt

MCU Treats
and Does Not Accept Address
SPICR2--0
SPICR6--1

~

* As defined during SPI deselect mode (SPICR4= 0),

Figure 4-8. SPI Address and Data Field Separation (Reception)

3-429

IT

-.f I

MCU Interrupts
MCU Treats
New Address Field

I

MC6805S2

4.10 DATA ARBITRATION

Data arbitration occurs when two or more transmitters try to control a common data line. Refer to
Figure 4-9 for data arbitration timing.

(SPICR4)

SPICl

I nterna I Data In
Strobe

I

L

XXXXXlJ

n

L

(SP,CR5)=O*

----------------~--------~.

(SPICR7)

SPID Pin

SPID Out
Register( * * )

XXXXXl

'!lXlXIY

\

0

M1

\

/

)(

I

(SPICR1)

SPID Output
Buffer

YYXIYX

X

X
It(

r-

Hi Z
-

-I

Bus Contention

*As defined during SPI deselect mode (SPICR4=O),
* * SPIDout= PB2 if SPICR3-DDRB2= 1
SPIDout= PB3 if SPICR3-DDRB3= 1

Figure 4-9. SPI Data Arbitration Timing Diagram

The MCU handles the data arbitration in the following ways:
Starting Conditions
1) The MCU has data mastership, i.e., port B2 or B3 are used for SPI data transfer and
have their data direction registers in the output mode.

2) SPICR3 is preset properly to output the SPI data on the selected data output port (PB2
or PB3)
3) The S PI is in the active transaction mode.
Arbitration Criterion

The SPI data output line logic level on the pin is compared with contents of the data
register of that line during the data input strobe. If the data register content is one while
the SPI data output line logic level is zero then it is decided that an external device(s) is
(are) trying to control the data line.

3-430

MC6805S2

Action
When the arbitration criteria are met, the mode fault flag (SPICR1) is set, the MCU loses
data mastership and the SPI data output line DDR is cleared putting the line in the input
mode.
NOTE
Complementary type of arbitration (i. e., output data line equals one; port
data register equals zero) is not implemented and should not occur in the
system as this will cause excessive dissipation on the port and may result in a
catastrophic failure of the circuit.
4.11 CLOCK ARBITRATION
Clock arbitration is done in two ways: 1) via the slave select input line and 2) via the serial peripheral
interface clock line. Both types of arbitration may be used simultaneously in an application.
4.11.1 Clock Arbitration via Slave Select Input Line
During serial peripheral interface transactions, port BO serves as the slave select input if port BO is in
the input mode mDR BO=O).
When the MCU has clock mastership, PBO should remain high. When an external device requests
clock mastership this input is pulled low. The MCU loses clock mastership and switches to slave
type operation, the clock line data direction register bit is cleared, (DDR B 1 = 0), and the mode fault
flag is set.
This clock arbitration may happen during active or idle transaction modes (see 4.12 SLAVE SELECT
INPUT OPERATION).
4.11.2 Clock Arbitration via Serial Peripheral Interface Clock Line
This type of arbitration is enabled only when the MCU operates as clock master while the clock line
output buffer works in the open-drain mode IOCR B5= 0), Unlike the clock arbitration described
previously, the MCU does not lose clock mastership. The clock output data register status is
monitored under control of the clock arbitration flip-flop to guarantee minimum clock high and
clock low times on the clock line, in case two or more clock masters are trying to control the clock
line simultaneously. Each clock master may be assumed to be asynchronous with respect to the
other(s) and to run with different clock frequencies. When set, the clock arbitration flip-flop (CLAQ)
blocks the toggle enable of port B1 effectively inhibiting the port data register from changing state
by toggling during the toggle pulse. Refer to Figure 4-10 for timing.

3-431

I

MC6805S2

Condition: ISPICR4)=1:IDCRB5)=O
Normal Operation

"Open Drain SPICl"; IDDRB1=1I

Timer Overflow

SPICl Data
Register

J

\

II

SPICl Pin

IDDRB1)= 1

Internal Data
Strobe

ISPICR5)=1

ClAO

Timer Overflow

PBl Toggle
Clock

t::lK~~T
rL
ISPICR5) = 1*

----+--

-----++++4--..

/External Master
SPICl

\-------

SPICl Data
Register

ClAO
IArbitration)

J

_____

~

Wait

r-S:~~L-l

ISPICR1)

I
I

- - I_ _ _

ISPICR?)

~Idle----+*As defined during SPI deselect mode ISPICR4=O).

Figure 4-10. Clock Arbitration via Clock Line Timing

3-432

MC6805S2

CLAO status is modified under the following conditions:
a) CLAO is cleared when:
1) SPICR 4=0 or DDR B1 = 1
2) Toggle pulse is generated for port B 1.
b) CLAO is set when:
1) A negative edge is detected on the SPI clock input if the port B 1 data register is high.
Simultaneously, the port 81 data register is cleared. If this occurs in the idle mode, while
the MCU is not ready for serial transmission, the mode fault flag (SPICR 1) is set as well.
In this way, the MCU will keep the clock line low, effectively blocking all clock pulses on
the clock line, and detecting that the clock line was driven low during the idle mode. If
the MCU was set up as a transmitter, the clock edge occurring during the idle mode cannot generate an internal data output strobe. Hence, during subsequent serial transmission receivers it would "miss" the MSB of the data transmitted from the MCU. Protocols
can be set up to avoid, or recover from, this type of framing error.
2) If the S PI clock line is still low 2 % machine cycles after the port B 1 data register is set,
the CLAO set command will remain active, as long as the SPI clock line remains low. The
clock arbitration operation is explained in more detail in 4.13.3 Two-Wire Half Duplex
Mode with Clock Arbitration.
4.12 SLAVE SELECT INPUT OPERATION
Slave select information is supplied to the MCU via port BO by an external device. If port BO is in the
output mode then slave select actions are inhibited. If the slave select feature is not used in an application, port BO should be used in the output mode.
Slave select input generates various actions depending on whether the SPI is operating in the clock
master mode or clock slave mode. These are outlined in the following paragraphs.
4.12.1 Slave Select Input Actions During Master Mode
In this mode, the slave select input is monitored to assure that it stays false (high), If slave select
becomes true (low), the device immediately exits the master mode and becomes a slave (DDR
B 1 = Q). The significance of this is that a collision has occurred; that 'is, two devices have both
become or are willing to become masters. This is normally the result of a software error, although
some systems may allow the default master to "knock all other masters off the bus" if an erroneous
bus state is detected. This is a castastrophic event and it is the responsibility of the default master to
completely "clean up" the system. Moreover, the mode fault flag is set to signalto the MCU that
clock mastership is lost. These actions can take place during either active or idle transaction modes.
Refer to Figure 4-11.

3-433

I

MC6805S2

(SPICR4)

16

KXXXXXXXX

Timer Overflow

SPICl Data
Register

_---Hi-Z

SPICl (Pin)

1--1

1--1

1

1

.J

II

Intern,,1 Data In
Strobe
(SPICR5) = 1 *

[

________

I

1-1-1

L

External Source

_

_

(SPICR?) 0

~

n

n

......_ _ _ _ _ _ _... 1.._ _ _ _

II _ _ _
.JL..

n

II' - _

~

Idle

·111( -III(
SPISS 1

(DDRB11 1

(DDRBO)

Active Transaction
External Source Requests~
Clock Mastership
,

~~-

= 0 Input

--------------------------~~I---------Mastership lost ~I

(SPICR1) 0

-----------------Master----'l·~I...II(~---Slave--*As defined during SPI deselect mode (SPICR4=O)

Figure 4-11. Clock Arbitration via Slave Select Input -

Master Mode

4.12.2 Slave Select Input Actions During Slave Mode

The slave select (SS) input is generated by the current clock master (parallel port may be used) and
used to enable one of several possible slaves to accept and/ or return data. The S S signal must be
low prior to occurrence of serial clock pulses and must not become high until the eighth (last) serial
clock cycle. A high level on SS forces serial data output to the high-impedance state without affecting the data direction register status relative to the data outPLJt. Also, when SS is high the serial
clock input pulses (if any) are inhibited from generating internal data output arrd input strobe
pulses, and also the eight-bit counter is cleared.
The significance of this is that the slave select acts as a chip-enable line and the MCU receives
and/or is allowed to transmit back information only when SS is pulled low by the current clock
master. Individual lines must be used from the master for each slave select input. A single line is sufficient in the case of daisy chain or cascade connection of multiple slaves. Refer to Figure 4-12.

3-434

MC6805S2

(SPICR4)

~

71///J/J//IIJ!/J////}////////11J!///////11/I///J!I
SPI~~g~S~:~ l;///////II///IIIIIId01/IIJ/$//$uJ/;j/1m
----1 [II/11J//;fIlA:
Interna~t~:~:
n
n
IIh
OV:rif~:

SPICl (Pin)

_

(SPICR5) =0*

2

1

_ _ _ _ _ _ _ _..... L._ _ _ _...... '-_ _ _ _-.f

I

8

O-SPICR7

j

(SPICR7)

SPISS

W

\~

_____ru

SPID Out

===

DeSelect-Tldle ••*'I.-------Active--------'.~I.~---Idle

L

L
.I~

Active

*As defined during SPI deselect mode (SPICR4=0).

Figure 4-12. Clock Arbitration via Slave Select Input -

Slave Mode

4.13 SPI OPERATING MODES

A brief description of the serial peripheral interface (SPI) operating modes is contained in the following paragraphs.

A.13.1 One-Wire - Autoclocked Mode
In this mode, various circuits are connected to each other via a single wite one which data transfer
takes place. The clock is implicit during transmission and each circuit is its own clock master. The
MCU should be initialized as clock master and port B1 is not connected externally. In order to
achieve the precise timing required for this transmission it may be useful to start the active transaction mode with an interrupt. Hence, the data input/ output line can be connected on the M CU to the
INT2 line.
With the assistance of software to generate the start bit and stop bits, and swap the order of bits in
the data, NRZ-type serial transmission compatible with MC6801 can be achieved in this mode. (See
Figures 4-13 and 4-14.) Unused SPI data port B2 or B3 may be used as a normal input/ output. Port
BO may be used only as an output.

3-435

II

MC6805S2

Stop

Stop
Anywhere

SPID

I

I

In~~:m~me~~~~~____-A____-A____~~__~~__~~__~~____~-r~

'----.JIll

I

I
:

1

Timer Overflow

1

Internal Data In Strobe

1 SPICR5=O*

SPICl

SPICR7

I

I

~----------SPI
TABR2-0
Bit Clear SPID
load Baud Rate Timer
Set Clock level On SPICl * *
TACR3 -1

A c t i v e - - - - - - - - - - i.....
I .... SPlldle . .

•+

Enable Timer Bit Set SPID
Interrupt
At Timer
Interrupt

To Modulus latch
Inhibit Timer Interrupt
Enable SPI

*As defined during SPI deselect mode ISPICR4=Q).
* * Done Only Once Before First Transmission

Figure 4-13. SPI -

Stop
SPID

NRZ Operation (Transmit) Timing

Start

Stop

INT231"',____......____-A____.....___.....
Processed

~

____&....____&....____.....____.....____'"

I

Timer Overflow 1

I
Causes SPllnterruPt~:

Internal Data Strobe

8

SPICl

SPICR7

SPICR5=O*

I!J///!!~

t

I

* Done

SPlldle-

RECV Full

Start Timer= 2 x Baud Rate Disable Timer Interrupt
Set Clock level*
Enable SPI
Enable Timer Interrupt
* As defined during SPI
deselect mode ISPICR4=Ol.
*

-t

t""'..t - - - - - - - - - - S P I Active
MCU
SPICl ~---SPID

J----._ From Transmitted

Only Once Prior To First Reception

Figure 4-14. SPI NRZ Operation Timing (Receive)

3-436

MC6805S2

4.13.2 Two-Wire Half-Duplex Mode
In this mode, the data and clock lines are connected between various circuits in the system. Data
and clock mastership should be monitored via protocol included in the data patterns transmitted
between circuits. Moreover, data arbitration is possible on the MCU data line. Any transmitter can
"knock out" all others by transmitting all zeros.
4.13.3 Two-Wire Half-Duplex Mode with Clock Arbitration
In this mode, the MCU is assumed to operate as a clock master with an open-drain SPI clock output
buffer. Clock and data arbitration is accomplished as explained in 4.11 CLOCK ARBITRATION.
More than one clock master (and transmitter) is allowed at the same time in this mode.
An interesting protocol occurs when the clock lines of all masters operate with open-drain outputs.
If no master other than the MCU is operating on the clock line, then the clock arbitration flip-flop
(ClAQ) is never set and every toggle pulse creates an edge on the SPI clock line (SPiel). This is the
normal mode of operation.
However, if an external master pulls the SPI clock line low, the MCU sets ClAO to inhibit the next
timer overflow from generating a toggle pulse on the SPI clock port. The SPI clock port data
register is also cleared. At the next timer overflow, ClAO is reset and the SPI clock port is allowed
to toggle during future timer overflows. In the meantime, other master clock outputs may go high.
However, the SPI clock line is held low by the MCU until a low-to-high transition occurs on its
SPICl data register line. (In wire-or configuration, any master with a low output imposes a low
clock line on the total system.)
This mechanism guarantees that in case of clock arbitration (a process which is asynchronous to
the timer overflows) the SPI clock low time is not shorter than one toggle period. Hence, narrow
negative glitches are avoided on the clock line. Some devices in the system may be operated totally
under software control by using polling techniques. Polling is generally much slower than hardwired
logic. Potential appearance of narrow glitches could cause castastrophic system faults, as some
devices in the system might respond to them and some might not.
The clock arbitration flip-flop is also set when the SPICl data register toggles high while an external
master keeps the SPI clock line low after two and one-half machine cycles. ClAO remains set until
the SPICl line returns to a high state. At the next timer overflow, ClAO is reset. Future timer
overflows will be allowed to toggle the SPICl data register to the low state.
This mechanism guarantees that in case of a clock arbitration situation, the SPI clock high time is
not shorter than one toggle period. This avoids narrow positive glitches. The same comments are
applicable to positive glitches with regard to system performance.
In such a system, the longest clock low time is imposed by the clock master with the longest clock
low time. The shortest high time is determined by the device with the shortest high clock time.
4.13.4 Three-Wire Half-Duplex Mode with Slave Select Input
This mode is similar to the two-wire half-duplex mode except that the slave select input provides the
possibility of using the MCU as a peripheral circuit in a system (or in systems) where clock mastership may be passed through the slave select line.

3-437

I

MC6805S2

A typical method of doing this is to wire the slave select lines together. The current master puts its
slave select line (SPISS) in the output mode prior to a serial transmission and pulls the SPISS line
low signifying that the system is busy. In this way, the clock master will keep its mastership until the
end of the transmission. Software protocol can be arranged such that slaves do not request mastership until their SPISS lines go high. At the end of a transmission, the current master pulls the
SPISS line high and puts its SPISS port (PBG) in the input mode. A slave requesting clock mastership can now pull the SPISS line low, "knocking out" the current master. To avoid simultaneous
mastership requests, time multiplexed protocols may be required.
4.13.5 Three-Wire Full-Duplex Mode

II

In this mode, the MCU can operate as a transmitter and receiver at the same time. Bus oriented or
daisy chain type networks are feasible. Protocols included in the data stream are required to change
the clock masters, number of transmitters in the system, or the direction of information flow in
daisy chained systems with "collision." In this mode, it is possible for the MCU to shift out one byte
while receiving another. This removes the need for XMIT EMPTY or REC FULL status bits. Refer to
Figure 4-15.

Slave Select
Clock ---~'-+-------'''''''''''I-----......- + - - - -.....- t - - - Data

Example:

{

82= SPID In
83= SPID Out

{

82= SPID Out
83= SPID In

Information Flow

Figure 4-15. Daisy Chain/Cascade Organization

4.13.6 Three-Wire Full-Duplex Mode with Clock Arbitration

This mode is a mix of the three-wire full-duplex mode and the two-wire half-duplex mode with clock
arbitration, where the SPI clock line operates in a wire-or fashion in the system. Simultaneous
masters are allowed and clock arbitration is accomplished via the clock line.
4.13.7 Four-Wire Full-Duplex Mode with Slave-Select Input

This mode is similar to the three-wire full-duplex mode with regard to network and to the three-wire
half-duplex mode with slave-select input in respect to clock arbitration and slave selection. Refer to
Figure 4-16.

3-438

MC6805S2

* Half Duplex

MCUl

SPIDPB2/3
{ SPICLPBl

* Half

Duplex
{ SPID PB2/3
With Clock Arbitration
SPICLPBl

* Half

MCU2
V CC

Duplex
With Slave Select

* Full Duplex

* Full

Duplex
With Slave Select

MCU3

g

---' g

(!)

(/)

0....

0....

{

{

SPIDPB2/3
SPICLPBl
SPISSPBO
SPID InPB2/3
SPID OutPB3/2
SPICLPBl

SPID In:PB2/3
SPID OutPB3/2
SPICLPBl
{
SPISSPBO

CLUCL~
(!)

(J)

(!)

Figure 4-16. SPI Operation Bus Organization

3-439

I

MC6805S2

SECTION 5
SELF-CHECK, RESETS, CLOCK GENERATOR OPTIONS,
AND INTERRUPTS
This section describes the self-check capability, resets, clock generator options, and interrupts.
5.1 SELF-CHECK

I

The self-check capability of the MC6805S2 MCU provides an internal check to determine if the part
is functional. Connect the MCU as shown in Figure 5-1 and monitor the output of port C bit 0 for an
oscillation of approximately 7 Hz. A 9-volt level on PCO, pin 2, detected as the device under test
comes out of reset, energizes the ROM-based self-check feature. The self-check program exercises
the CPU, RAM, ROM, AID, timers, interrupts, 1/0 ports, and auxiliary counter.

28
+9V

27

VCC

26
25
24
23
22
AN2

21

AN1
20
ANO
PBO
PB1

10
11

RESET
PA7
PA6
PA5
PA4

19

R1 =6 kO
R2= 3 kO
R3= 200 0
R4=390 0
C1 =22 pF
C2= l/-tF
C3=0.1/-t F

PA3
18
PA2

12

17

13

16

14

15

PB2

PAl

PB3

PAO

* RC Oscillator Option Shown If QO-Q2 LEDs Blinking= Device Passes Test
Q3 Blinking = Watchdog Reset Problem

Figure 5-1. Self-Check Connections

3-440

MC6805S2

Several of the self-check subroutines can be called by a user program with a JSR or BSR instruction. They are the RAM, ROM, and 4-channel AID tests. The timer routine may also be called if the
timer input is the internal phase two clock.
5.1.1 RAM Self-Check Subroutine
The RAM self-check is called at location $F39 and returns with the Z bit clear if any error is detected;
otherwise, the Z bit is set. The walking diagnostic pattern method is used.
The RAM test must be called with the stack pointer at $07F. When run, the test checks every RAM
cell except for $07F and $07E which are assumed to contain the return address.
The A and X registers and all RAM locations except the top two are modified.
5.1.2 ROM Checksum Subroutine
The ROM self-check is called at location $F54 and returns with the Z bit cleared if any error was
found; otherwise Z = 1, X = 0 on return, and A = 0 if the test passed. RAM locations $040-$043 are
overwritten.
5.1.3 Analog-to-Digital Converter Self-Check
The AI D self-check is called at location $F6E and returns with the Z bit cleared if any error was
found; otherwise Z = 1.
The A and X register contents are lost. The X register must be set to four before the call. On return,
X = 8 and AI D channel7 is selected. The AI D test uses the internal voltage references and confirms
port connections.
5.1.4 Timer Self-Check Subroutine
The timer self-check is called at location $F99 and returns with the Z bit cleared if any error was
found; otherwise Z = 1 .
In order to work correctly as a user subroutine, the internal phase two clock must be the clock
source and interrupts must be disabled. Also, on exit, the clock is running and the interrupt mask is
not set so the caller must protect from interrupts if necessary.
The A and X register contents are lost. The timer self-check routine counts how many times the
clock counts in 128 cycles. The number of counts should be a power of two since the prescaler (1) is
a power of two. If not, the timer probably is not counting correctly. The routine also detects if timer
A is not running.

3-441

•

MC6805S2

5.2 RESETS
The MCU can be reset four ways: by initial power up, by the external reset input (RESET), by a
forced reset generated by a timeout of the MCUs auxiliary or "watchdog" counter, and by an optional internal low voltage detect circuit. The RESET input consists mainly of a Schmitt trigger
which senses the RESET line logic level. A typical reset Schmitt trigger hysteresis curve is shown in
Figure 5-2. The Schmitt trigger provides an internal reset voltage if it senses a logic zero on the
RESET pin. Refer to the reset circuit in Figure 5-3 and to Figure 5-9, under 5.4 INTERRUPTS, for
the complete reset sequence.

Out

I

Of
Reset

In
Reset

-+L _ _ __

'---1~~.--~-+-I........

0.8 V
VIRES-

4V

2V

VIRES +

Figure 5-2. Typical Reset Schmitt Trigger Hysteresis

vee

Vee

220 kn
Typ

23

RESET

lOon
Typ

I

1 JtF Typ.

* * Optional-l 00
Discharge
Device

Meu

Miscellaneous Register

Figure 5-3. Reset Circuit

3-442

**

ms Delay
Typical During Power Up

MC680552

5.2.1 Power-On Reset (PaR)

An internal reset is generated upon power up that allows the internal clock generator to stabilize. A
delay of tRHL milliseconds is required before allowing the RESET input to go high. Refer to the
power and reset timing diagram of Figure 5-4. Connecting a capacitor to the RESET input (as illustrated in Figure 5-5) typically provides sufficient delay. During power up, the Schmitt trigger
switches on (removes reset) when the RESET rises to VIRES +.

5V

Vcc
OV
RESET
Pin

II

Internal
Reset

Figure 5-4. Power and Reset Timing

1
--.

23
1.0 pF

Part Of
MC6805S2
MCU

Figure 5-5. Power-Up Reset Delay Circuit

5.2.2 External Reset Input

The MCU will be reset if a logic zero is applied to the RESET input for a period longer than one
machine cycle (tcyc). Under this type of reset, the Schmitt trigger switches off at VIRES - to provide an internal reset voltage.
5.2.3 Low Voltage Inhibit (LVI)

The optional low-voltage detection circuit causes a reset of the MCU if the power supply voltage
falls below a certain level (VLVI). The only requirement is that VCC remains at or below the VLVI
threshold for one tcyc minimum. In typical applications, the V CC bus filter capacitor will eliminate
negative-going voltage glitches of less than one tcyc. The output from the low-voltage detector is
connected directly to the internal reset circuitry. It also forces the RES ET pin low via a strong
discharge device through a resistor. The internal reset will be removed once the power supply
voltage rises above a recovery level (VLVR), at which time a normal power-on-reset occurs.

3-443

MC6805S2

5.2.4 Forced Reset

If the auxiliary counter reset mask bit in the miscellaneous counter (M R4) is clear and the auxiliary
counter status bit (MR5) is set, as a result of counter overflow, a switch to VSS is turned on, pulling
the RESET pin low. A consequent voltage drop below VIRES - on RESET causes an MCU reset,
which in turn sets MR4. Switching to VSS when the RESET pin is turned off allows voltage to rise
above VIRES +, after which the MCU reset is released.
RESET pin voltage variations occurring as a result of forced reset may be amplified externally in
order to provide a reset to other peripheral circuits in the system. The reset output from the MCU is
not TTL compatible.
5.2.5 Reset Initialization

I

The minimum low time for all four modes of reset is one tcyc + 250 nanoseconds (tcyc= oscillator
frequency divided by four). When reset is detected, the MCU initialization takes place. The following are the actions taken on the internal circuitry:
a) FF
b) FFFF
c) 7F
d)7FFF
e) 50
f) 50
g) 50
h)07

Timer A Modulus Latch and Timer A
Timer B
Prescaler 1
Prescaler 2
Timer A Control Register
Timer B Control Register
Miscellaneous Register
A/ D Status Control Register

i) 40
j)
k)
I)
m)

00
FC
FO
1

n) 7F
0) FFE

Serial Peripheral Interface
Control Register
Port A Data Direction Register"
Port C Data Direction Register"
Port B Data Control Register"
Interrupt (Mask Bit I in
Condition Code Register)
Stack Pointer
Program Counter

5.3 INTERNAL CLOCK GENERATOR OPTIONS
The internal clock generator circuit is designed to require a minimum of external components. A
crystal, a resistor, a jumper wire, or an external signal may be used to control the internal clock
generator with various stability/ cost tradeoffs. A manufacturing mask option is used to select the
crystal or resistor option. The oscillator frequency is internally divided by four to produce the internal systern clocks.
The different connection methods are shown in Figure 5-6. The crystal specifications and suggested
PC board layout are given in Figure 5-7. A resistor selection graph is shown in Figure 5-8.
The crystal oscillator start-up time is a function of many variables: crystal parameters (especially
RS), oscillator load capacitance, IC parameters, ambient temperatures, and supply oscillator startup. Neither the crystal characteristics nor the load capacitances should exceed recommendations.

* Reads

as $FF

3-444

MC6805S2

When utilizing the on-board oscillator, the MCU should remain in a reset condition (reset pin
voltage below VIRES +) until the oscillator has stabilized at its operating frequency. Several factors
are involved in calculating the external reset capacitor required to satisfy this condition: the
oscillator start-up voltage, the oscillator stabilization time, the minimum VIRES +, and the reset
charging current specification.
Once VCC minimum is reached, the external RESET capacitor will begin to charge at a rate dependent on the capacitor value. The charging current is supplied from V CC through a large resistor, so
it appears almost like a constant current source until the reset voltage rises above VI RES + .
Therefore, the RESET pin will charge at approximately:
(VIRES + )eCext= IRES-tRHL
Assuming the external capacitor is initially discharged.

_6-t XT AL
r -_ _ _ _......_ 2
MC6805S2
EXTAL

EXTAL

MCU
(Crystal Mask
Option)

CL

26

I

XTAL

_'''''~_ _ XTAL

MC6805S2
27

EXTAL

MC6805S2
MCU
(Resistor Mask
Option)

Approximately 25% to 50% Accuracy
Typical tcyc = 1.25 ,..s
External Jumper

Crystal

External
Clock
Input
(TTL Compatible,
Low Impedance
Source)

II

26 XTAL

MC6805S2
MCU
(Resistor Mask
EXT AL
Option)

MCU
Either Crystal
or RC Mask
Option

External Clock

Approximately 10% to 25% Accuracy
External Resistor
(Excludes Resistor Tolerance)

NOTE:
The recommended CL value with a 4.0 MHz crystal is 27 pF, maximum, including system distributed capacitance. For crystal frequencies other than 4 MHz, the total capacitance on each pin should be scaled as the inverse of the frequency ratio. For example, with
2 MHz crystal, use approximately 50 pF on EXT AL and approximately 50 pF on XT AL. The exact value depends on the Motional-Arm
parameters of the crystal used

Figure 5-6. Clock Generator Options

3-445

MC6805S2

EXTAL

XTAL

27

26

AT -

Cut Parallel Resonance Crystal
CO= 7 pF Max.
Freq. =4.0 MHz@CL = 24 pF
RS = 40 ohms Max
(e)

II
NOTE:

Keep crystal leads and circuit connections as short as possible.

Figure 5-7. Crystal Motional Arm Parameters and
Suggested PC Board Layout

8.0
7.0

±!
~

6.0

~

5.0

~

3.0

0

2.0

>

f

'0

~

4.0

1.0
0
0

10

20

30

40

50

60

70

80

Resistance (k{})

Figure 5-8. Typical Frequency Selection for Resistor Oscillator Option

3-446

MC6805S2

5.4 INTERRUPTS
The MC6805S2 MCU can be interrupted seven different ways: at reset, through the external interrupt (INT1) input pin, the internal timer (either A or B) interrupt request, the SPI interrupt request,
the external port D bit 6 (I NT2) input pin, and a software interrupt instruction (SWIl.
The reset interrupt has priority over all other interrupts and is not maskable. It is serviced immediately at its occurrence independent of the instruction being executed (see 5.2 RESETS), All other interrupts are maskable and do not cause the current instruction execution to be halted, but are considered pending until the current instruction execution is complete. Pending INT1, INT2, timer A,
timer B, or SPI interrupts are acknowledged by the MCU only if the I bit in the condition code
register is clear.
When any interrupt (except reset) is acknowledged, processing is suspended following completion
of the current instruction being executed, the present MCU state is pushed onto the stack, the
interrupt bit (I bit) in the condition code register is set, the address of the interrupt routine is obtained from the appropriate interrupt vector address, and the interrupt routine is executed. Stacking the
CPU registers, setting the I bit, and vector fetching requires a total of 11 tcyc periods for completion. Note that interrupts which are masked are latched internally for later interrupt service once the
mask bit(s) is (are) cleared. Refer to Figure 5-9 for a flowchart. The interrupt service routine must
end with a return from interrupt (RTI) instruction which allows the MCU to resume processing of
the program prior to the interrupt.
Table 5-1 provides a listing of the interrupts, their priority, and the address of the vector which contains the starting address of the appropriate interrupt service routine. This p,iority applies to those
interrupts pending when the CPU is ready to accept an interrupt. In addition, each of these interrupts, except INT1, have a separate mask bit which must also be cleared, in addition to the I bit, for
the MCU to acknowledge the interrupt. Specifically, the INT2, timer A, timer B, and SPI interrupts
each have their own independent mask bits contained in MR6, TACR6, TBCR6, and SPICR6,
respectively.
NOTE
The timer A, timer B, INT2, and SPI interrupts share the same vector address. The interrupt routine must determine the source of the interrupt by examining the interrupt request bits, namely TACR7, TBCR7, MR7, and SPICR7. These bits are not automatically
cleared following interrupt servicing and must be cleared via software. The INT1 interrupt
has its own unique vector address. Therefore, the INT1 interrupt request is cleared automatically when the INT1 vector is serviced.

Table 5-1. Interrupt Priorities
Interrupt
RESET
SWI
INTl
TIMER/INT2/SPI

Priority

1
2*

3
4

Vector Address
$FFE
$FFC
$FFA
$FF8

and
and
and
and

$FFF
$FFD
$FFB
$FF9

* Priority 2 applies when the I bit In the condition code register IS set
When 1=0, SWI has a priority of four (like any other instruction)
The priority of TNf1 thus becomes two and the T) M ER I INT21 S PI
becomes three

3-447

I

MC6805S2

I

1 -- !(in CCRI
07F--SP
40--SPICR
FFFF -- Timer B
7FFF -- Prescaler 2
FO--OCRB
50--TBCR
FC= OORC
O--OORA
CLR INT Logic
FF--Timer A
7F -- Prescaler 1
50--TACR
50--MR
07--ACSR

Clear
INTl
Request
Latch

Stack
PC, X, A, CC

Timer A, B,
INT2, SPI
Load PC From:
SWI: FFC/FFD
INT FFA/FFB
TIMER A, TIMER B,
SPI or INT2:
FF81 FF9

Load PC
from
FFE/FFF

Execute All
Instruction
Cycles

* MR7.MR6+ TACR7.TACR6+ TBCR7.TBCR6+ SPICR7.SPICR6
(INT21

(Timer AI

!Timer BI

(SPII

Figure 5-9. Reset and Interrupt Processing Flowchart

A software interrupt (SWI) is an executable instruction which is executed regardless of the state of
the I bit in the condition code register. SWls are usually used as breakpoints for debugging or as
system calls.
The external interrupts, INT1 and INT2, are latched and/or sensed on the falling edge of the input
signal. Timer A and B interrupt request bits are set when these timers make transition to $00 and
$0000, respectively.

3-448

MC6805S2

A sinusoidal input signal (fINT maximum) can be used to operate an external interrupt (INT1), as
shown in Figure 5-10, for use as a zero-crossing detector with hysteresis included. An interrupt request is generated for each negative-slope zero crossing of the ac signal. This allows applications
such as servicing time-of-day routines and engaging/ disengaging ac power control devices. Offchip full wave rectification provides an interrupt at every zero crOSSing of the ac signal and thereby
provides a 2f clock.

INT1--L-------------~~rn------------or.~_.

- 5° I

I

ZCD Interrupt. I
Detected Within I
InternallNTl

I

:

ThiS Window - ................_ _ _ _ _ _ _ _..l.LU.I

Figure 5-10. Interrupt Timing

For digital applications, INT1 can be driven directly by a digital signal. The maximum frequency of a
Signal that can be recognized by the timer and INT1 pin logic is dependent on the parameters
labeled tWL and tWH· The pin logic that recognizes the high (or low) state on the pin must also
recognize the low (or high) state on the pin, in order to re-arm the internal logic. Therefore, the
period can be calculated as follows: (assumes 50/50 duty cycle for a given period)
tcyc x 2 + 250 ns = period =f_1req
The period is not simply tWL, tWH. This computation is allowable, but it does reduce the maximum
allowable frequency by defining an unnecessarily longer period (250 ns twice). See Figure 5-11. For
the INT1 function, the maximum allowable frequency is also determined by the software response
of the INT1 service routine.
VCC

MC6805S2
MCU

4.7 k
TTL
Level ___.._-25-1
Digital
Input

TNT1

MC6805S2
MCU

lJ
(a) Zero-Crossing Interrupt

(b) Digital-Signal Interrupt

Figure 5-11. Typical Interrupt Circuits (lNT1)

3·449

MC6805S2

SECTION 6
INPUT/OUTPUT PORTS AND ANALOG-TO-DIGITAL CONVERTERS
This section describes the input! output pins, the port data registers, th!3 miscellaneous register,
and the analog-to-digital converter.
6.1 INPUT/OUTPUT

I

There are 14 input or input! output pins. The INT1 pin may also be polled with branch instructions to
provide an additional input pin. All pins on ports A, B, and C are programmable as either inputs or
outputs under software control of the corresponding data direction registers (DDRs). The port I/O
programming is accomplished by setting the corresponding bit in the port DDR to a logic one for
output or a logic zero for input. On reset all the DDRs are initialized to a logic zero state, placing the
ports in the input mode. The port output registers are not initialized on reset and should be
initialized by software before changing the DDRs from input to output. When programmed as outputs, all I/O pins read latched output data, regardless of the logic levels at the output pin due to
output loading; refer to Figure 6-1 and Table 6-1.
CAUTION
The port data registers are not initialized during reset. The contents of these registers
should be written to a known state for any port pins that are expected to become outputs. This will avoid any spurious transitions before initializing the corresponding DDR
bits to the output mode.
Data
Direction Register
Bit*

c:

Latched
Output
Data
BI1

~
o

U

Data
Direction
Register
Bit

Output
Data
Bit

Output
State

X

High-Z* *

Input
To

MCU

1

Pin

* DDR IS a write-only register and reads as all "1s".
* * Ports A (with CMOS drive disabled), B, and C are three-state
ports. Port A has optional internal pullup devices to provide CMOS
drive capability. See Electrical Characteristics tables for complete
information

Figure 6-1. Typical Port I/O Circuitry

3-450

MC6805S2

Table 6-1. DigitallnputlOutput Ports
Input
Name

Number

Input

Output

TTL

Port A

8

Yes

Yes

Port B
LED
Drive

4

Yes

Port C

21bl

Yes

Port D

71al

INT1

1

Output

Special

TTL

CMOS

*
* lal

* lal

Yes

*
*Ibl

Yes

* lal

*

Yes

No

*

Yes

No

Comment
a: If Pull-Up Option
a 10 mA Sink; Current Limited Source PB1PB3
can be programmed to open-drain configuration
via PB DCR
b' Hi-Z Input
a Hi-Z Input
b Shared with EXT Timer Inputs

a PD5 and PD4 Share a 15 kilohm resistor Itypl
Bill B IH Instruction

*

All input/output lines are TTL compatible as both inputs and outputs. Port A lines are CMOS compatible as outputs using a mask option. Ports B1, B2, and B3 can be software programmed to
operate as open-drain outputs. Port B, C, and D lines are CMOS compatible as inputs. When programmed as outputs, port B is capable of sinking 10 milliamperes and sourcing 1 milliampere on
each pin (TTL output state). Port D lines are input only; thus, there is no corresponding DDR.
Port D provides the multiplexed analog inputs, reference voltages, and INT2. All of these lines are
shared with the port D digital inputs. PDO-PD3 may always be used as digital inputs and may also be
used as analog inputs. The VRL and VRH lines (PD4 and PD5) are internally connected by the AID
resistor. Analog inputs may be prescaled to attain the VRL and VRH recommended input voltage
range.
Figure 6-2 provides some examples of port connections The address map in Figure 2-1 gives the
addresses of data registers and DDRs.

CAUTION
The corresponding DDRs for ports A, B, and C are write-only registers (locations $004,
$005, and $006). A read operation on these registers reads as all ones. Since BSET and
BCLR are read-modify-write functions, they cannot be used to set a DDR bit (all unaffected bits would be set). It is recommended that all DDR bits in a port be written using a
single-store instruction.
The latched output data bit may always be written. Therefore, any write to a port writes all of its
data bits even though the port DDR is set to input. This may be used to initialize the data registers
and avoid undefined outputs. However, care must be exercised when using read-modify-write instructions since the data read corresponds to the pin level if the DDR is an input (zero) and corresponds to the latched output data when the DDR is an output (one).

3-451

I

MC6805S2

(a) Output Modes

PA7

22

PA6

21

PA5

20

PA4

19

PA3

18

PA2

17

PAl

16

PAO

15

ICMOS Loads)

PB3

..16mA

11 TTL Load)
PBl

""f\r.......

'-"\J\j'\r.....

Port A. bit 7 programmed as output. driving CMOS
loads and bit 4 one TTL load d"ectly lusing CMOS
output option)

I

Port B. bit 3 programmed as output. driving Darlington-base directly

+ V

VCC

PB3
PB2

\\

PBl
PBO

2N6386
ITypical)

\\

PB3

14

PB2

13

PBl

12

PBO

11

CMOS
Inverter

MC140491 14069 !Typical)

~lOmA

Port B. bits 1-3. programmed as open-drain
outputs. driving CMOS loads using external
pull-up resistors

Port B. bit a and bit 1 programmed as output. driving
LEOs directly,

(b) Input Modes

PA7
PA6

MC74LS04 !TYPical)

MC74LS04 or M~C14069
!TYPical)
•
•
14
PB4

20

PA5

19

PA4

18

PA3

:

13

PB2

17

PA2

:

12

PBl

11

PBO

PAl
PAO

CMOS or TTL driVing Port B directly
TTL driving Port A d"ectly
ANO

POOl ANa

ANI

P01/ANl

AN2

P02/AN2
P03/AN3

OV

VRL
VRH

- - . r - ' - - _ - - - ' PC 1

PCO

P06/1NT2

Port 0 used as 4-channel AID Input

CMOS and TTL driving Port C directly

Figure 6-2. Typical Port Connections

3-452

MC6805S2

6.2 PORT B TOGGLE CAPABILITY

Port B 1 and BO data registers have toggle capability at the timer overflow times. Under the control
of the timer output cross-couple bit in the miscellaneous register, (M ROl, the overflow pulses from
timer A and timer B are directed to port B 1 and BO data registers. (See Figures 6-3 and 6-4.)
An incoming toggle pulse on port BO is allowed to toggle the data register if port B OCR bit 4
(DCR4) is cleared. At reset this bit is set. An incoming toggle pulse on port B1 is allowed to toggle
the port B 1 data register under the following conditions governed by control bits in S PI control
register and SPI clock arbitration flip-flop status.
PB1 toggle enable= (SPICR7-SPICR4-(PBO+ DDRBOl + SPICR2-SPICR4)-CLAO
where:
SPICR7= SPI interrupt request flag bit,
S PI CR4 = S PI transaction enable bit,
S PI CR2= port B 1 toggle enable bit, and
CLAO = clock arbitration flip-flop output.
When PB1 toggle enable is asserted, MCU write to PB1 data register is inhibited. When SPI is not
used, SPICR4 and CLAO are reset. Therefore, SPICR2 can directly control the port B 1 toggle
capability. (See 4.6 SERIAL PERIPHERAL INTERFACE OPERATION.)

Port B3

* Write Only Register
SPI
MSB

SPI
MSB

MCU~----------

__------------<

Figure 6-3. Port B Configuration (Sheet 1 of 2)

3-453

I

MC680SS2

* * Timer Overflow

Toggle* - - - - - - - - - - - - - 4 h
Enable
MCU

MCU

I

(SPICR1)

Timer Overflow

.JL...

MCU~------------------~~------~----_<

*Toggle Enable B1 = (SPICR7.SPICR4.(PBO+ DDRBO))·SPICR2·SPICR4)·CLAQ
or B Depends on (MROI
x Write Only Register

* * A,

Figure 6-3. Port B Configuration (Sheet 2 of 2)

3-454

MC6805S2

DCR7

DCR6

DCR5

DCR4

DDR3

DDR2

DDR1

DDRO

Data Direction
DCR7
DCR6
DCR5
DCR4
DDR3
DDR2
DDR1
DDRO

-

PB3
PB2
PB1
PBO
PB3
PB2
PB1
PBO

Output
Output
Output
Toggle
Output
Output
Output
Output

Buffer Open Drain Enable
Buffer Open Drain Enable
Buffer Open Drain Enable
Enable
Mode
Mode
Mode
Mode

* Write Only Register: All Bits Read as "1'

Figure 6-4. Port B Data Control Register

Port toggle capability allows action on port BO or B 1 or both as a result of timer overflows. This
speeds up timer overflow to port service, compared to the normal program controlled method, and
is very useful in critical real-time related applications.
Toggle capability on port B 1 is fundamental for S PI operation in the clock master mode, where the
clock pulses are generated by the MCU using this feature as controlled by one of the two available
timers.
A write to port BO or B1 data registers is inhibited while the individual port toggle enable is asserted.
This allows a write to other port B data registers without disturbing the toggle feature of the
selected port line.
6.3 PORT B DATA CONTROL REGISTER

The port B data control register consists of four status bits (oCR7 through OCR4) and four data
direction bits (oCR3 through OCRO). OCR7, OCR6, and OCR5 are respectively port B3, B2, and B1
open-drain output control bits. These bits are set at reset or under program control and cleared
under program control. When clear, the port output buffers operate in the open-drain mode, if the
port lines are in the output mode. When set, the port output buffers operate in the push-pull mode.
OCR4 is a toggle enable control bit for port BO. This bit is set at reset or under program control and
cleared under program control. When cleared, the timer overflow pulse causes the data register on
port BO to toggle.
When PBO toggle enable is asserted by clearing OCR4, MCU write to the PBO data register is
inhibited.
OCR3, OCR2, OCR 1, and OCRO are respectively the port B3, B2, B 1, and BO data direction
registers.
6.4 PORT A AND C DATA DIRECTION REGISTERS

Port A has an 8-bit and port C has a 2-bit wide data direction register. All bits are cleared at reset to
the input mode. These registers are write only; they read as $ FF.

3-455

I

MC6805S2

6.5 MISCELLANEOUS REGISTER

The miscellaneous register (shown below), at memory location $OA, contains control and status information related to INT2, auxiliary counter, prescaler 1 and 2, and timer overflow.

I

I

MR7

I

MR6

I

MR5

I

MR4

MR3

MR2

MRl

MRO

$OA

MR7

INT2 Interrupt Request Bit
This bit is set when a negative edge is detected on INT2 pin. If not masked by INT2 interrupt mask bit, (MR6) it causes an interrupt requestto the MCU. If the I bit in the condition
code register is clear, the MCU will acknowledge interrupt by executing the interrupt procedure. The interrupt vector is fetched from address $FF8 and $FF9. This bit is cleared
under program control or at reset.

MR6

INT2 Interrupt Request Mask
This bit is set at reset or under program control. When set, it inhibits the INT2 interrupt
request from being acknowledged by the MCU. MR6 is cleared under program control.

MR5

Auxiliary Counter Status/Preset Bit
This bit is set whenever the auxiliary counter overflows. If it is not masked by the auxiliary
counter reset mask MR4, it will drive a switch to VSS on the RESET pin causing an MCU
reset. This bit is cleared at reset or under program control. M R5 may be used as an
auxiliary counter preset bit. If MR5 is clear it is possible to preset the auxiliary counter by
writing a logic one to MR5. If MR5 is set (i.e., the auxiliary counter has already overflowed at least once) a logic zero written to M R5 clears the M R5 bit and presets the
auxiliary counter. MR5 is cleared at reset. Refer to Figure 3-7 for auxiliary counter timing
information.

MR4

Auxiliary Counter Reset Mask Bit
This bit is set at reset or under program control. When set, it inhibits activation of the
reset switch controlled by MR5 on the RESET pin. MR4 is cleared under program control.

MR3

Prescaler 1 Clear Bit
This bit is used to preset the contents of prescaler 1 to $7F. This bit reads as a zero. In
order to preset prescaler 1, a logic one must be written into M R3.

MR2

Prescaler 2 Clear Bit
This bit is used to preset the contents of prescaler 2 to $7FFF. This bit reads as a zero. In
order to preset prescaler 2, a logic one must be written into MR2.

3-456

MC6805S2

MR1

Prescaler Cross-Couple Bit
This bit controls the outputs of prescalers 1 and 2 and directs them to either timer A or
timer B clock inputs. This bit is cleared at reset or under program control and set under
program control. When MR1 is clear the output of prescaler 1 is used as a clock input of
timer A and the output of prescaler 2 is used as clock input for timer B. When MR1 is set,
outputs of the prescalers are cross-coupled. Thus, prescaler 1 feeds the timer B clock input and prescaler 2 feeds the timer A clock input.
To avoid truncation errors at the time of cross coupling, both prescalers may be preset by
writing a one to M R3 and M R2 simultaneously.

MRO

Port B Toggle Cross-Couple Bit
This bit controls the overflow pulses of timers A and B and directs them to either port B 1
or BO. This bit is cleared at reset or under program control and set under program control.
When MRO is clear, the overflow output pulse of timer A is used as a port 81 data register
toggle clock source. Similarly, the timer B overflow output pulse is directed to port BO
toggle clock input.
When MRO is set, timer A overflow output is directed to port BO and timer B output is
directed toward port B1.

6.6 ANALOG-TO-DIGITAL CONVERTER (AID)
The MC6805S2 microcomputers have an 8-bit analog-to-digital (AI D) converter implemented on
the chip using a successive approximation technique. Up to four external analog inputs, via port D,
are connected to the AI D through a multiplexer. Four internal analog channels may be selected for
calibration purposes (VRH-VRL, VRH-VRL/2, VRH-VRL/4, and VRL). The accuracy of these internal channels will not necessarily meet the accuracy specifications of the external channels.
A fifth external analog input (AN4) is available via mask option. When selected, it replaces the VRH
internal channel. Due to signal routing, the accuracy of this fifth channel may be slightly less than
ANO-AN3. The fifth AI D channel could be used to conveniently monitor the standby RAM supply
voltage, as an example.
The multiplexer selection is controlled by the AID control register (ACR) bits 0, 1, and 2.

3-457

I

MC6805S2

Whenever the ACR is written, the conversion in progress is aborted, the conversion complete flag
(ACR bit 7) is cleared, and the selected input is sampled for five machine cycles and held internally.
During these five cycles the analog input will appear approximately like a 25 picofarads (maximum)
capacitor charging through a 2.6 kilohm resistor, typical (see Figure 6-5).

Device ~2'6
k!1 (Typical)
Analog
Input

I

Channel
Select

I

_
-

25 pF (Max)

Virtual
Ground

Figure 6-5. Effective Analog Input Impedance
(During Sampling Only)

The converter operates continuously using 30 machine cycles to complete a conversion of the
sampled analog input. When the conversion is complete, the digitized sample of digital value is
placed in the AID result register (ARR), the conversion complete flag is set, the selected input is
sampled again, and a new conversion is started.
The AID is ratio metric. Two reference voltages (VRH and VRU are supplied to the converter via
port D pins. An input voltage equal to VRH converts to $FF (full scale) and an input voltage equal to
VRL converts to $00. An input voltage greater than VRH converts to $FF and no overflow indication
is provided. Similarly, an input voltage less than VRL. but greater than VSS converts to $00. Maximum and minimum ratings must not be exceeded. For ratiometric conversion, the source of each
analog input should use VRH as the supply voltage and be referenced to VRL. To maintain the full
accuracy on the AID, VRH should beequal to or less than VDD, VRL should be equal to or greater
than VSS but less than the maximum specification and (VRH-VRU should be equal to or greater
than 4 volts.
The AID has a built-in Y2 LSB offset intended to reduce the magnitude of the quantizing error to
± Y2 LSB, rather than + 0, -1 LSB with no offset. This implies that, ignoring errors, the transition
point from $00 to $01 occurs at Y2 LSB above VRL. Similarly, the transition from $FE to $FF occurs
1.5 LSB below VRH, ideally. Refer to Figures 6-6 and 6-7.

3-458

MC6805S2

Error Convention
±2LSB's

Converter·
Output
(Hexl

FF
FE
FD

FC

FB
FA
F9
FS

O.S
0.7

11

0.6
0.5
0.4
0.3
0.2
0.1
00
VRL

lx

2x

3x

4x

5x

6x

250x

x=2~*(VRH-VRLI=1

253x 254x

251 x 252x

255x

V RH

LSB

Figure 6-6. Ideal Converter Transfer Characteristic
Digital
Output

Digital
Output

FF

FF

)/
/
/
Offset Errors

/

I
I
I

Full Scale Error

I

I
I

(VRH -1 LSBI
Offset
(Positivel

Analog
Input

oo~______________~I____
I __•

~
Full
Scale
Error

Digital
Output

FF

Non-Linearity

oo~

______ __-+________
~

~~~

Analog
Input

Figure 6-7. Types of Conversion Errors

3-459

Analog
Input

MC6805S2

On release of reset the AI D control register (ACR) is cleared therefore after reset channel zero will
be selected and the conversion complete flag will be clear. Refer to Figure 6-8 and Table 6-2.

D/A
Control
Logic

15 k (Typ.)

PD5/VRH
PD4IVRL

Count

--+-e

PDO/ANO
PD1/AN1PD2/AN2 PD3/AN3 -

1-of-8
Select
Multiplexer

'------_...

TN'f2/PD61 AN4-

AID
Result

AID

Figure 6-8. AI D Block Diagram

Table 6-2. AI D Input Mux Selection
AI D Output (Hex)

AID Control Register
ACR2

ACR1

ACRO

Input Selected

0
0
0
ANO
1
0
0
AN1
0
1
0
AN2
1
0
1
AN3
0
0
1
VRH**
1
1
0
VRL *
1
1
0
VRH/4*
1
1
1
VRH/2*
* Internal (calibration) levels
* * AN4 may replace the VRH calibration channel

3-460

Min

Typ

FE* *
00
3F
7F

. FF* *
00
40
80

Max

FF*
01
41
81

*

if selected via mask option

MC6805S2

SECTION 7
SOFTWARE AND INSTRUCTION SET
This section describes the software and instruction set for the MC6805S2.
7.1 SOFTWARE

The following paragraphs describe the software available to the user.
7.1.1 Bit Manipulation

The MC6805S2 MCU has the ability to set or clear any single RAM or input/output bit (except the
data direction registers; see Caution under INPUT/OUTPUT) with a single instruction (BRSET,
BCLRl. Any bit in page zero, including ROM except the DDRs, can be tested using the BRSET and
BRCLR instructions and the program branches as a result of its state. The carry bit (C) equals the
value of the bit referenced by BRSET or BRCLR. The capability of working with any bit in RAM,
ROM, or I/O allows the user to have individual flags in RAM or to handle single I/O bits as control
lines.
The coding example in Figure 7-1 illustrates the usefulness of the bit manipulation and test instructions. Assume that the MCU is to communicate with an external serial device. The external device
has a data ready signal, a data output line, and a clock line to clock data one bit at a time, LS B first
out of the device. The MCU waits until the data is ready, clocks the external device, picks up the
data in the carry flag (C bit), clears the clock line, and finally accumulates the data bit in a RAM
location.

MCU

*
NEXT

*

WAIT FOR READY

BRSET

2,PORTA,

BSET
BRCLR
BCLR
ROR

1, PORTA
0, PORTA, NEXT
1, PORTA
RAMLOC

CLOCK NEXT BIT IN
PICKUP BIT IN C-BIT
RETURN CLOCK LINE HIGH
MOVE C-BIT INTO RAM

Ready
Serial
Device

Clock

Data

~

2P

0
1R
T

°A

~

Figure 7-1. Bit Manipulation Example

3-461

I

MC6805S2

7.1.2 Addressing Modes

The MC6805S2 MCU has ten addressing modes available for use by the programmer. They are explained briefly in the following paragraphs. For additional details and graphical illustrations, refer to
the M6805 HMOSIM146805 CMOS Family Users Manual.
The term "effective address" (EA) is used in describing the addressing modes. EA is defined as the
address from which the argument for an instruction is fetched or stored.
7.1.2.1 IMMEDIATE. In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The immediate addressing mode is used to access constants which
do not change during program execution (e.g., a constant used to initialize a loop counter),

I

7.1.2.2 DIRECT. In the direct addressing mode, the effective address of the argument is contained
in a single byte following the opcode byte. Direct addressing allows the user to directly address the
lowest 256 bytes in memory with a single two-byte instruction. This address area includes all onchip RAM and I/O registers and 128 bytes of ROM. Direct addressing is an effective use of both
memory and time.
7.1.2.3 EXTENDED. In the extended addressing mode, the effective address of the argument is
contained in the two bytes following the opcode. Instructions with extended addressing mode are
capable of referencing arguments anywhere in memory with a single three-byte instruction. When
using the Motorola assembler, the user need not specify whether an instruction uses direct or extended addressing. The assembler automatically selects the shortest form of the instruction.
7.1.2.4 RELATIVE. The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte following the opcode (the offset) is added to the PC
if, and only if, the branch condition is true. Otherwise, control proceeds to the next instruction. The
span of relative addressing is from - 126 to + 129 from the opcode address. The programmer need
not worry about calculating the correct offset if he uses the Motorola assembler, since it calculates
the proper offset and checks to see if it is within the span of the branch.
7.1.2.5 INDEXED, NO OFFSET. In the indexed, no offset addressing mode, the effective address
of the argument is contained in the 8-bit index register. Thus, this addressing mode can access the
first 256 memory locations. These instructions are only one byte long. This mode is often used to
move a pointer through a table or to hold the address of a frequently referenced RAM or I/O
location.
7.1.2.6 INDEXED, a-BIT OFFSET. In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following
the opcode. This addressing mode is useful in selecting the kth element in an n element table. With
this two-byte instruction, k would typically be in X with the address of the beginning of the table in
the instruction. As such, tables may begin anywhere within the first 256 addressable locations and
could extend as far as location 510 ($1 FE is the last location at which the instruction may begin).

3-462

MC6805S2

7.1.2.7 INDEXED, 16-BIT OFFSET. In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes
following the opcode. This addressing mode can be used in a manner similar to indexed, 8-bit offset
except that this three-byte instruction allows tables to be anywhere in memory. As with direct and
extended, the Motorola assembler determines the shortest from of indexed addressing.
7.1.2.8 BIT SET/CLEAR. In the bit set! clear addressing mode, the bit to be set or cleared is part of
the opcode, and the byte following the opcode specifies the direct address of the byte in which the
specified bit is to be set or cleared. Thus, any read/write bit in the first 256 locations of memory, including I/O, can be selectively set or cleared with a single two-byte instruction. See Caution under
6.1 INPUT/OUTPUT.
7.1.2.9 BIT TEST AND BRANCH. The bit test and branch addressing mode is a combination of
direct addressing and relative addressing. The bit which is to be tested and condition (set or clear) is
included in the opcode, and the address of the byte to be tested is in the single byte immediately
following the opcode byte. The signed relative 8-bit offset in the third byte is added to the PC if the
specified bit is set or cleared in the specified memory location. This single three-byte instruction
allows the program to branch based on the condition of any readable bit in the first 256 locations of
memory. The span of branching is from -125 to + 130 from the opcode address. The state of the
tested bit is also transferred to the carry bit of the condition code registers. See Caution under 6.1
IN PUT / OUTPUT.
7.1.2.10 INHERENT. In the inherent addressing mode, all the information necessary to execute the
instruction is contained in the opcode. Operations specifying only the index register or accumulator,
as well as control instruction with no other arguments, are included in this mode. These instructions
are one byte long.
7.2 INSTRUCTION SET
The MC6805S2 MCU has a set of 59 basic instructions, which when combined with the 10 addressing modes produce 207 usable opcodes. They can be divided into five different types: register/
memory, read-modify-write, branch, bit manipulation, and control. The following paragraphs
briefly explain each type. All the instruction within a given type are presented in individual tables.
7.2.1 Register/ Memory Instructions
Most of these instructions use two operands. One operand is either the accumulator or the index
register. The other is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump-to-subroutine (JSR) instructions have no register operand. Refer to
Table 7-1.

3-463

I

MC6805S2

Table 7-1. Register/Memory Instructions
Addressong Modes
Immediate
Function

/I
/I
Op
Mnemonic Code BVtes Cycles

Load A Irom Memory

LOA

A6

2

2

Load X from Memory

LOX

AE

2

2

Store A on Memory

STA

Store X on Memory

STX

Add Memory to A

ADD

Add Memory and
Carry to A

AOC

A9

Subtract Memory

SUB

AD

/I
Op
/I
Code Bytes Cycles

Indexed
(No Offset)

Op
/I
/I
Code Bytes Cycles

II
II
Op
Code Bytes Cycles

86

2

4

Indexed
(8·80t Offset)
/I
II
Op
Code Bytes Cycles

Indexed
(16· 80t Offset)
II
OP
Code Bytes

II

Cycles

C6

3

F6

1

4

~

06

3

6

BE

2

4

Cf

3

5

FE

1

4

EE

2

5

OF

3

6

B7

2

5

C7

3

6

F7

1

~

E7

2

6

07

3

7

8F

2

5

CF

3

6

FF

1

5

EF

2

6

OF

3

7

2

BB

2

4

CB

3

5

FB

1

4

EB

2

5

DB

3

6

2

2

B9

2

4

C9

3

5

F9

1

4

E9

2

5

D9

3

6

2

2

BO

2

4

CO

3

5

FO

1

4

EO

2

5

DO

3

6

-

AB

Extended

Dorect

2

5

E6

2

Subtract Memory from

I

A with Borrow

SBC

A2

2

2

82

2

4

C2

3

5

F2

1

4

E2

2

5

D2

3

6

AND Memory to A

AND

A4

2

2

84

2

4

C4

3

5

F4

1

4

E4

2

5

D4

3

6

OR Memory woth A

ORA

AA

2

2

BA

2

4

CA

3

5

FA

1

4

EA

2

5

DA

3

6

Exctusove OR Memory
woth A

EOR

A8

2

2

B8

2

4

C8

3

5

F8

1

4

E8

2

5

D8

3

6

Arothmetoc Compare A
wIth Memory

CMP

Al

2

2

81

2

4

Cl

3

5

Fl

1

4

El

2

5

Dl

3

6

Arithmetic Compare X
with Memory

CPX

A3

2

2

B3

2

4

C3

3

5

F3

1

4

E3

2

5

D3

3

6

Bot Test Memory woth
A ILogocal Compare}

BIT

A5

2

2

B5

2

4

C5

3

5

F5

1

4

E5

2

5

05

3

6

Jump Unconditional

JMP

BC

2

3

CC

3

4

FC

1

3

EC

2

4

DC

3

5

Jump to Subroutine

JSR

8D

2

7

CD

3

8

FD

1

7

ED

2

8

DO

3

9

3-464

MC6805S2

7.2.2 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify or test it contents, and write the
modified value back to memory or to the register; see Caution under 6.1 INPUT/OUTPUT. The test
for negative or zero (TST) instruction is included in the read-modify-write instruction though it does
not perform the write. Refer to Table 7-2.

Table 7-2. Read-Modify-Write Instructions
AddressIOg Modes
Inherent (A)
Function

I<
I<
Op
Mnemonic Code Bytes Cycles

Inherent (X)

Indexed
(No Offset)

Direct

I<
I<
I<
I<
Op
Op
Code Bytes Cycles Code Bytes Cycles

Increment

INC

4C

I

4

5C

1

4

3C

Decrement

DEC

4A

1

4

5A

1

4

3A

Clear

CLR

4F

1

4

5F

1

4

3F

Indexed
18 8,t Offset)

/I
/I
Op
Code Bytes Cycles

/I
/I
Op
Code Bytes Cycles

2
2
2
2

6

7C

1

6

6C

6

7A

1

6

6A

6

7F

1

6

6F

6

73

1

6

63

6

70

1

6

60

6

79

1

6

69

76

1

6

66

Complement

COM

43

1

4

53

1

4

33

Negate
12s Complemenll

NEG

40

1

4

50

1

4

30

Rotate Left Thru Carry

ROL

49

1

4

59

1

4

39

2
2

Rotate RIght Thru Carry

ROR

46

1

4

56

1

4

36

2

6
6

78

1

6

68

6

74

1

6

64

6

77

1

6

6

7D

1

6

LogIcal ShIft Lelt

LSL

48

1

4

58

1

4

38

LogIcal ShIft RIght

LSR

44

1

4

54

1

4

34

Arothmetlc ShIft R,ght

ASR

47

1

4

57

1

4

37

2
2
2

TST

4D

1

4

5D

1

4

3D

2

2
2
2
2

7
7
7
7

2
2

7
7

67

2
2
2
2

6D

2

7

7
7
7
7

Test for NegatIve
or Zero

3-465

I

MC6805S2

7.2.3 Branch Instructions
The branch instructions cause a branch from the program when a certain condition is met. Refer to
Table 7-3.

Table 7-3. Branch Instructions
Relative Addressing Mode

I

op
Function

Mnemonic

Code

#
Bytes

#
Cycles

Branch Always

BRA

20

2

4

Branch Never

BRN

21

2

4

Branch IFF Higher

BHI

22

2

4

Branch IFF Lower or Same

BLS

23

2

4

Branch IFF Carry Clear
(BranchlFFHlgher or Same)
Branch IFF Carry Set

BCC

24

2

4

(BHS)

24

2

4

BCS

25

2

4

(BLO)

25

2

4

Branch IFF Not Equal

BNE

26

2

4

Branch IFF Equal

BEG

27

2

4

Branch )FF Half Carry Clear

BHCC

28

2

4

Branch IFF Half Carry Set

(Branch IFF Lower)

BHCS

29

2

4

Branch IFF Plus

BPL

2A

2

4

BranchlFF Minus

BMI

2B

2

4

Branch IFF Interupt Mask
Bit IS Clear

BMC

2C

2

4

Branch IFF Interrupt Mask
Bit IS Set

BMS

2D

2

4

Branch IFF Interrupt Line
IS low

Bil

2E

2

4

Branch IFF Interrupt Line
IS High

BIH

2F

2

4

Branch to Subroutine

BSR

AD

2

8

3·466

MC6805S2

7.2.4 Bit Manipulation Instructions

The instructions are used on any bit in the first 256 bytes of memory; see Caution under 6.1 INPUT /
OUTPUT. One group either sets or clears. The other group performs the bit test and branch operations. Refer to Table 7-4.

Table 7-4. Bit Manipulation Instructions
Addressing Modes
Bit Set/Clear
Mnemonic

Function
Branch IFF Bit n
Branch IFF Bit n

op
Code

1/

Bytes

Cycles

Op
Code

11

t1

Bytes

Cycles

set

BRSET n (n ' 0

7\

-

-

2en

3

10

clear

BRCLR n (n = 0

7\

-

--

01 • 2 en

3

10

IS

IS

Bit Test and Branch

1/

Set Bit n

BSET n (n = 0

7\

10' 2 en

2

7

Clear bit n

BCLR n (n = 0

7)

11 ' 2 en

2

7

7.2.5 Control Instructions

The control instructions control the MCU operations during program execution. Refer to Table 7-5.

Table 7-5. Control Instructions
Inherent
Function

11

11

Mnemonic

Op
Code

Bytes

Cycles

Transfer A to X

TAX

97

1

2

Transfer X to A

TXA

9F

1

2

Set Carry Bit

SEC

99

1

2

Clear Carry Bit

CLC

98

1

2

Set Interrupt Mask Bit

SEI

98

1

Clear Interrupt Mask Bit

CLI

9A

1

2
2

Software Interrupt

SWI

83

1

11

Return from Subroutine

RTS

81

1

6

Return from Interrupt

RTI

80

1

9

Reset Stilck POinter

RSP

9C

1

2

No Operafion

NOP

9D

1

2

II

MC6805S2

7.2.6 Alphabetical Listing
The complete instruction set is given· ina alphabetical order in Table 7-6.
Table 7-6. Instruction Set (Sheet 1 of 2)
Addressing Modes

Condition Code

Bit
Bit
Indexed Indexed Indexed Set/ Test &
Mnemonic Inherent Immediate Direct Extended Relative (No Offset) (8 Bits) (16 Bits) Clear Branch H I
X
X
X
X
X
1\
X
ADC

II

ADD

X

X

X

X

X

X

AND

X

X

X

X

X

X

ASl

X

X

X

X

ASR

X

X

X

X

1\

X

BClR
BCS

X

BEQ

X

BHCC

X

BHCS

X

BHI

X

BHS

X

BIH

X
X

Bil
X

BIT

X

X

X

BlO

X

BlS

X

BMC

X

BMI

X

BMS

X

BNE

X

BPl

X

BRA

X

BRN

X

X

X

X

BRSET

X
X
X

BSR
Cll

X

CLI

X

ClR

X

COM

X

X
X

X

X

X

X

X

EOR

X
X

X

CPX
DEC

X
X

CMP

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

JSR

X

X

X

X

X

Z Zero
C Carry! Borrow

1\
•

3-468

1\

1\ 1\

1\

1\ 1\

1\

1\
1\

1\ 1\

1

1\ 1\

1\

1\ 1\
1\ 1\

Test and Set If True. Cleared Otherwise
Not Affected

1\

1\ 1\

1\ 1\

X

X

Condition Code Symbols
H Half Carry IFrom Bit 3)
I Interrupt Mask
N Negative ISlgn Bit)

1\ 1\

1

X

JMP

INC

1\

1\ 1\

BRClR
BSET

C

1\ 1\

1\ 1\

X

BCC

N Z

•
•
•• •
••
••
•• •• •
•• • • •
•• • • •
•• • • •
•• • • •
•• • • •
•• • • •
•• • • •
•• • • •
•• • • •
••
•
•• • • •
•• • • •
•••• •
•• • • •
•• • • •
•• • • •
•• • • •
•• • • •
•• • • •
••••
•• • •
•• • • •
•• • • •
• •0 • • 0
• •• •
•• 0 •
••
••
••
•• •
•• •
••
•
•• • • •
•• • • •

MC6805S2

Table 7-6. Instruction Set (Sheet 2 of 2)
Addressing Modes

Condition Code

Bit
Indexed Indexed Indexed Set! Test &
Extended Relative (No Offset) (8 Bits) (16 Bits) Clear Branch H
X
X
X
X
Bit

Mnemonic Inherent Immediate Direct
X
X
LOA
X

X

X

X

X

LSL

X

X

X

X

LSR

X

X

X

X

NEO

X

X

X

X

NOP

X
X

X

X

X

LOX

X

ORA
ROL

X

RSP

X

RTI

X

RTS

X

X

X

X

X

X

STA

X

STX

X
X

SEC

X

SEI

X

X

SUB
SWI

X

TAX

X

TST

X

TXA

X

Condition Code Symbols
H Half Carry (From Bit 31
I Interrupt Mask
N Negative (Sign Bit 1

X

Z
C

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Zero
Carry! Borrow

11
•

Test and Set If True, Cleared OtherWise
Not Affected

7.2.7 Opcode Map
Table 7-7 is an opcode map for the instruction used on the MCU,

3-469

Z

A A

A

A

A A

A

A A

)

C

•
•

A

A A

X

X

N

A A
A A

)

X

SBC

X

I

••
••
••0
••
••
••••
••
••
••••
)

)

•
•
•
A
)

•• •• •
••
• •, • • ,
• •• •
••
•
•• •
••
• ,•• •
•• •• •
••
•
•••••
1\ 1\

1\

1\ 1\

1\ 1\

1\ 1\

1\ 1\

1\

I

MC6805S2

Table 7-7. M6805 HMOS/M146805 CMOS Family Instruction Set Opcode Map

~
Low

Bit Manipulation
BTB
BSe
1
0

I

0000

0001

BRSETO
3

BTB

BRCLRO

0001

3

BTB

BRSETl
3

I

3

4

BRSET2
3

BTB

5

BRCLR2
3

BTB

6
0110

BRSET3
3

BTB

7
0111

BRCLR3
3

BTB

3

BTB

3

BTB

BRSET5
3

BTB

1011

BRCLR5
3

BTB

C
1100

BTB

1101

BRCLR6
3

BTB

E
1110

BRSET7
3

BTB

F
1111

BRCLR7
3

BTB

1

LSR
1

6 6
IXl

1

2

3

7

INH
X
IMM
DIR

Inherent
Accumulator
Index Register
Immediate
Direct

Bse

5

LSR
IXl

1

IX

1

1

X

2

3

7

ASR
A

2

1

1

X

2

3

7

X

2

LSL

5 4

2

1

3 4

ROL
DIR

1

5 4

DEC

1

3 4

DEC
DIR

1

3

7

X

2

1

1

3

7

X

2

3

7

IX

6 6

5

ASR
IXl

1

IX

6 6

5

LSL
IXl

1

IX

6 6

ROL

DEC
A

IXl

LSL

ROL
A

5

ROR

ASR

3 4
A

6 6

ROR

3 4

LSL
DIR

2

ROR
A

5 4

3 6
REL

5

ROL
IXl

1

IX

6 6

DEC

5

DEC
IXl

1

IX

3
REL

2

5 4
2

INC

REL

5 4

1

2

REL

3

2

INC
A

4 4

TST

5 4

3 4

INC
DIR

2

3 6

BMS

Bse

5 4

3 6

BMC

Bse

1

X

2

3 4

3

7

TST
DIR

1

TST
A

1

6 6

INC
IXl

1

IX

5 6

TST
X

5

INC

IXl

2

4

TST
1

IX

BIL

Bse

2

REL

5 4
2

5 4

3 6

BIH

Bse

EXT
REL
BSC
BTB

IX

6 6

LSR
X

5

COM

CLR
REL

2

DIR

3 7

3 4

CLR
1

CLR
A

1

6 6

CLR
X

2

Extended
Relative
Bit Set/Clear
Bit Test and Branch

IX
IXl
IX2

3-470

5

CLR
IXl

1

Abbreviations for Address Modes

A

IX

BMI

BCLR7
2

1

ROL

REL

5 4

7 7

10

7

ASR
DIR

2

BPL

BSET7
2

2

3

3 4

5 4

3 6

2

BCLR6
2

X

A

LSL

REL

5 4
Bse

7 7

10

1

ROR
DIR

3 6

2

BSET6
2

1

5 4

2

BHCS

Bse

5 7

10

D

2

[)IR

ASR

REL

2

BCLR5

BRSET6
3

2

5 4

5 7

10

IXl

COM

3 4

LSR

3 6

BHCC

Bse

5 7

10

B

7

COM
A

ROR

REL

5 4

BSET5
2

1

5 4

3 6

BEQ

Bse

5 7

10

A
1010

3

5

NEG

NEG

REL

2

BCLR4
2

DIR

2

BNE

BSET4
2

BRCLR4

9
1001

2

2

BCS
2

5 4

5 7

10

3

BCLR3

BRSET4

8
1000

REL

Bse

5 7

10

3 4

COM

LSR

2

BSET3
2

2

3 6

5 4

5 7

10

REL

5 4
Bse

5 7

10

COM

BCC

Bse

5 4

3 6

2

BCLR2
2

1

3

5 4

BSET2
2

X

NEG
A

REL

BLS

Bse

5 7

10
0101

2

1

0111

6 6

BHI
5 4

5 7

NEG
DIR

7

REL

2

BCLRl

BTB

2

0110

3

3

2

5 4
Bse

5 7

BRCLRl
10

0100

2

3 4

IX
7

BRN

Bse

BSETl

BTB

10

3
0011

2

5 7

10

2
0010

2

5 4

BCLRO

0101

0100

NEG

REL

Read/Modify/Write
IXl
X
6
5

5 4

3 6

BRA

Bse

5 7

10

1

0011

5 4

BSETO
2

A
4

DIR
3

0010

5 7

10

0
()()(J()

Branch
REL
2

Indexed (No Offset)
Indexed, 1 Byte (8-Bit) Offset
Indexed, 2 Byte (16-Bit) Offset
M146805 CMOS Family Only

IX

MC6805S2

Control
INH

IMM

DIR

8

9

A

B

C

D

1000

1001

1010

1011

1100

1101

9

9

2

INH

2

2

4

IMM

2

SUB

RTI
1
6

6

2

INH

2

RTS

2

4

IMM

2

2

4

2

11

10

2

2

4

CPX

INH

2

2

2

4

AND
2

2

2

4

BIT
2

2

2

4

2

LDA
2
2

IMM

2

2

2
2

2

2

2

INH

2

2

2

2

INH

2

2

2

2

2

2

4

IMM

2

INH

2

2

4
2

2

4

2

1

IMM

INH
2

1

2
6

8

INH

2

5

2

2

4

2
2

2

IMM

DIR

3

3

5

DIR

3

3

5

Dir

3

4

6

3

5
3

3

5
3

2

4

6

3

5
3

3

5

EXT

3

4

6

EXT

3

4

6

EXT

3

4

6

EXT

3

4

6

2

4

3

5

7

3

5

8

EXT

3

4

6

EXT

3

3

3

5

4

6

EXT

3

4

6

EXT

3

4

6

3

4

6

3

3

5

tXT

3

6

9

IX2

2

5

5

3

4

6

IX2

2

5

5

3

5

7

IX2

2

5

5

IXl

1

4

4

IXl

1

4

4

IXl

1

4

4

IX2

2

5

5
2

6

6

4

4

2

5

5

IX2

2

IXl

1

4

4

IXl

1

4

4
1

5

5
1

4

4

IX1

1

5

5
2

5

5

IX2

2

5

5

4

4

IXl

1

4

4

IX1

1

2

4

4

4

4

IX1

1

3

3

2

7

8

1

6

7

JSR
IX2

2

5

5

IXl

1

4

4

2

6

6

1

5

5

2

IX1

1

0111

3

8
IX

1000

3

9
IX

1001

3

A
IX

1010

3

B
IX

1011

2

C
IX

1100

5

D
IX

1101

3

E
IX

1110

4

STX

STX
IX2

7
IX

LDX
IX1

0110

4

JSR

LDX
IX2

6
IX

JMP
IXl

0101

3

ADD

JMP
IX2

5
IX

ORA

ADD

0100

3

ADC

ORA

IX2

4
IX

EOR

ADC

0011

3

STA
IX1

2
0010

3
IX

LDA
IXl

0001

3

BIT

EOR

IX2

3
IX

AND

STA
IX2

1

CPX
1

0000

3
IX

SBC

LDA
IX2

0
IX

CMP

IXl

Low
~
I

3

SUB

BIT

STX
3

4

AND

LDX

EXT

4

CPX

JSR

EXT

1111

SBC

JMP

EXT

3

5

ADD

STX
DIR

5

ORA

EXT

F

1110

CMP

ADC

LDX
DIR

2

EOR

JSR
DIR

5

STA

JMP

DIR

5
IX2

LDA

EXT

IX

E
SUB

AND

ADD
3

2

CPX

ORA

DIR

IX2

SBC

ADC

DIR

5

CMP

EOR

DIR

5

BIT

3

STX
INH

3

STA

DIR

5

TXA

6

LDA

LDX
2

4
EXT

AND

JSR

REL

2

1

3

7

LDX

INH

3

DIR

2

BSR

2

2

DIR

IX1

SUB

CPX

JMP

INH

*WAIT

5

3

NOP

*STOP

3

ADD

2

2
1

3

ORA

RSP
1

DIR

ADC

IMM

3

SBC

EOR

ADD

SEI
1

4

ORA

CLI
1

2
IMM

ADC

SEC
1

5

2

EOR

EXT

BIT

2

INH

6

CMP

STA

CLC
1

3

5

INH

2

5
3

LDA

TAX
1

3
DIR

BIT

IMM

4

SUB

AND

IMM

2

3

CPX

IMM

2

DIR

SBC

IMM

2

SWI

5

CMP

SBC
2

3

SUB

CMP

1

1

Register / Memory
EXT
1X2

INH

F
IX

1111

LEGEND

F +-i------------:::;?' Opcode in Hexadecimal
1111

Cycles, M6805 HMOS ---~
Mnemonic - - - - +....

Opcode in Binary

Bytes ---~~--I-~:..J,.-~~~:...J
Cycles, M146805 CMOS _ _ _ _ _ _J
, , - - - - - - - - - Address Mode

7-1117-12

3-471

II

MC6805S2

SECTION 8
ELECTRICAL SPECIFICATIONS
This section contains the electrical specifications for the MC6805S2.

8.1 MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage

I

PCOin
Self-Check Mode
All Other

Port A and C Source Current per Pin
(One at a Time)
Operating Temperature Range
MC6805S2
MC6805S2C
Storage Temperature Range
Junction Temperature
Plastic Package
Ceramic Package
Cerdip

Symbol

Value

Unit

VCC

-0.3 to + 7.0

V

Yin

-03 to + 15.0
-0.3 to + 7.0

V

lout

10

mA

TA

o to 70
-40 to 85

°c

Tstfi

-55 to + 150

TJ

150
175
175

°c

8.2 THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Plastic
Ceramic
Cerdip

Symbol

Value

Unit

8JA

70
60
60

°C/W

3-472

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electrical fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit. For proper operation it is
recommended that Yin and Vout be constrained to the range VSS:s;(Vin or
Vout:S; V Cc. Reliability of operation is
enhanced if unused inputs except EXT AL are
tied to an appropriate voltage level (e.g.,
either VSS or VCC!.

MC6805S2

8.3 POWER CONSIDERATIONS

The average chip-junction temperature, T J, in DC can be obtained from:
(1)
TJ=TA+(PDeOJA)
Where:
T A = Ambient Temperature, DC
OJA = Package Thermal Resistance, Junction-to-Ambient, °C/W
PD = PINT+ PPORT
PINT= ICC x VCe, Watts - Chip Internal Power
PPORT = Port Power Dissipation, Watts - User Determined
For most applications PPORTCOMP

PA2

PCOITIMER

PAl

PCl

PAO

PC2

PB7

fin

PB6

PBO

PB5

PBl

PB4

PB2

PB3

•

MC6805T2

FIGURE 1 -

PAO
Port PAl
PA2
A PA3
I/O PA4
Lines

Data
Dir.
Reg.

~!~

PA7

MC6805T2 HMOS MICROCOMPUTER BLOCK DIAGRAM

Accumulator

8
Index
Register

Port
C
Reg.

X

Condition
Code
Register CC

I

Data
Dir.
Reg.

CPU
Control

A

Port
PCO/TIMER C
PCl
I/O
PC2
Lines

CPU

Stack
Pointer

Port
B
I/O
Lines

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

Port
B
Reg.

Data
Dir.
Reg.

SP
Program
Counter
High PCH

Frequency
Input
fin

AlU

Phase
Comparator
COMP

Program
Counter
low PCl

Self-Check
ROM

MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

VCC

-0.3 to + 7.0

V

Input Voltage (Except Pin 6)

Vin

-0.3 to + 7.0

Operating Temperature Range

TA
Tstg

+ 70
-55 to + 150

°c

Symbol

Value

Unit

8JA

120
50

°C/W

Rating

Storage Temperature Range

o to

V
°c

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Plastic
Ceramic
Cerdip

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields, however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit. For proper operation it is
recommended that Vin and Vout be constrained to the range VSS:s;(Vin or V out )
:s; VCC. Reliability of operation is enhanced if
unused inputs are tied to an appropriate logic
voltage level (e.g., either VSS or VCC).

60

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °c can be obtained from:
(1)
TJ = T A (PD-OJA)
Where:
TA5!Ambient Temperature, °C
0JA'" Package Thermal Resistance, Junction-to-Ambient, °C/W
PD E PINT + PPORT
PINTEICCx VCC, Watts - Chip Internal Power
PPORT 5! Port Power Dissipation, Watts - User Determined
For most applications PPORT COMP
Normal Mode
Self-Check Mode

-

Input Low Voltage
RESET
INT
All Other Except fin

VIL

INT Zero-Crossing Input Voltage, through a Capacitor

VINT

Internal Power Dissipation - No Port Loading,
VCC=575V, TA=O°C
Input Capacitance
XTAL
All Others

V

-

0.8
1.5
0.8

-

4.0

Vacp - p

400

-

mW

25
10

-

pF

-

1.2

-

-

VSS
VSS
VSS
2.0

PINT
Cin

V

VCC+ 1
10.0

10.0

-

*

-

-

AC Coupled Input Voltage Swing on fin

VFIP

0.5

Input Current (VIH = VCC) on Pin 11 (fin)
Output Low Current (VOL = 10 V) on Pin 7 (c/>COMP)

IFH

-

-

40

Vac pop
p.A

ICML

-

-300

-

p.A

ICMH

-

200

-

p.A

IOFF

-

2

-

nA

VIRES+
VIRES-

2.1
0.8

4.0
2.0

V

Output High Current (VOH = VCC - 1 V) on Pin 7 (c/>COMPI
Leakage Current (Vin=VCC) on Pin 7 (c/>COMP)
RESET Hysteresis Voltage (See Figures 10 and 11)
"Out of Reset"
"Into Reset"
Input Current
TIMER (Vin=O.4
INT
(Vin=O.4
EXTAL (Vin=2A
(Vin=OA
RESET (Vin = 0.8

V)
V)
V to VCC)
V)
V) (External Capacitor Charging Current)

-

-

20
50
10
-1600
-40

VLVR

-

-

4.75

VLVI

2.75
3.1

3.5
3.5

lin

-

-

-

20

-

-

-

-

-4.0

Low Voltage Receiver
Low Voltage Inhibit

-

O°C to 70°C
- 40°C to 85°C

p.A

V
V

-

-

See MC68(7)05 Series Data Sheet for port I/V curves and Input protection schematiCs.

* Due to internal biasing, this INT input (when unused) floats to approximately 2.0 volts

SWITCHING CHARACTERISTICS (VCC= 5.25 Vdc -+0.5 Vdc, VSS = GND, T A = 0 to 70°C unless otherwise noted)
Characteristics

Oscillator Frequency
Cycle Time (4/fos c )
INT and TIMER Pulse Width (See TIMER and INTERRUPT Sections)
RESET Pulse Width
RES""ET Delay Time (External Capacitance-l.0 p.F)

Symbol

Min

Typ

Max

Unit

fosc

0.4

-

4.2

MHz
P.s
ns

0.95
tcyc
tWH,tWL t cyc + 250
tRWL t cyc + 250
tRHL

Input Frequency

-

-

10

-

-

-

-

ns

-

ms
MHz

100

1

-

16

Input Frequency Rise Time (fin - max)

tlNR

-

-

20

ns

Input Frequency Fall Time (fin = max)

tlNF

-

-

20

ns

fin

40

-

60

%

Injection Pulse Active Time

tERR

-

70

-

ns

TNT Zero-Crossing

liNT

0.03

-

1.0

kHz

-

40

50

60

%

Duty Cycle of fin
Detection Input Frequency

External Clock Input Duty Cycle (EXTAU

3-483

I

MC6805T2

PORT ELECTRICAL CHARACTERISTICS (VCC = + 525 Vdc +
- 05 Vdc VSS = GND TA = 0° to 70°C unless otherwise noted)
Typ
Max
Symbol
Min
Unit
Characteristic
Port A with CMOS Drive Enabled
0.4
V
Output Low Voltage, ILoad = 1.6 rnA
VOL
2.4
V
Output High Voltage, ILoad = - 100 p.A
VOH
V
Output High Voltage, ILoad = - 10 p.A
VCC+1
VOH
2.0
V
Input High Voltage, ILoad = - 300 p.A (max)
VIH
VCC
Input Low Voltage, ILoad= - 500 p.A (max)

VIL

VSS

Hi-Z State Input Current (Vin=2.0 V to VCC)
Hi-Z State Input Current (Vin=O.4 V)

IIH
IlL

-

-

0.8
-300

-

-

-500

VOL
VOL

-

-

0.4
1.0

2.4
-1.0

-

-

-

-10

2.0

-

VSS

-

VCC
0.8

rnA
V
V

-

2

10

p.A

-

-

2.4
2.0

-

0.4
-

V
V
V
V
p.A

V
p.A
p.A

Port B
Output Low Voltage, ILoad=3.2 rnA
Output Low Voltage, ILoad= 10 rnA (sink)
Output High Voltage, ILoad = - 200 p.A
Darlington Current Drive (Source), VO= 1.5 V

I

VOH
IOH
VIH
VIL
ITS I
Port C and Port A with CMOS Drive Disabled

Input High Voltage
Input Low Voltage
Hi-Z State Input Current
Output Low Voltage, I Load = 1.6 rnA
Output High Voltage, ILoad= -100 p.A
Input High Voltage
Input Low Voltage
Hi-Z State Input Current

FIGURE 2 - TIL EQUIVALENT TEST LOAD
(PORT B)

-

VOL
VOH
VIH
VIL

VSS

-

VCC
0.8

I1'SI

-

2

10

FIGURE 3 - CMOS EQUIVALENT TEST LOAD
(PORT A)

FIGURE 4 - TIL EQUIVALENT TEST LOAD
(PORTS A AND C)
VCC=5.75V

VCC=5.75V
Test
Point

Test
Point

V
V
V

MMD6150
or Equiv.

TestPoint~

40 pF
(Totall

I30PF (Totail

30 pF
(Totail

24 kG

2.97 kG
MMD7000
or Equiv.

C=40 pF (Totail

SIGNAL DESCRIPTION

XTAL AND EXTAL
These pins provide control input for the on-chip clock

The input and output signals for the MCU are described in
the following paragraphs.

VCC AND VSS
Power is supplied to the MCU using these two pins. VCC
is power and VSS is the ground connection.

oscillator circuit. A crystal or an external signal can be connected to these pins to provide input to the internal
oscillator. Lead length and stray capacitance on these two
pins should be minimized. Refer to INTERNAL
OSCILLATOR for recommendations about these pins.
fin
This pin provides the high frequency digital input to the
variable divider portion of the on-chip frequency synthesizer.
The reference frequency for the phase lock loop is divided
down from the crystal oscillator. Refer to the PHASE LOCK
LOOP for details on the frequency synthesizer features.

INT
This pin provides the capability for asynchronously applying an external interrupt to the MCU. Refer to INTERRUPTS
for additional information.

3-484

MC6805T2

mented 2698 of these memory locations. This consists of:
2508 bytes user ROM, 116 bytes self-check ROM, 64 bytes of
user RAM, six bytes of port I/O, two timer registers, and two
PLL registers. The user ROM is split into two areas. The first
area begins at memory location $080 and continues through
$7FF. The lower 128 bytes of this ROM area (part of page
zero) allows the user to access ROM locations utilizing the
direct and table look-up indexed adressing modes. The
second user ROM area begins at memory location $040 and
continues through $F83. The last eight user ROM locations,
at the top of memory, are for the interrupt vectors.
The MCU reserves the first 16 memory locations for I/O
features, of which 10 have been implemented. These locations are used for the ports, the port ODRs, the timer, and
the PLL registers.
Sixty-four bytes of user RAM are provided. Of the 64
bytes, 31 bytes are shared with the stack area. The stack
must be used with care when data shares the stack area.
The shared stack area is used during the processing of
interrupt and subroutine calls to save the processor state.
The register contents are pushed onto the stack in the order
shown in Figure 6. Since the stack pointer decrements during pushes, the low order byte (PCL) of the program counter
is stacked first; then the high order four bits (PCH) are
stacked. This ensures that the program counter is loaded
correctly following pulls from the stack, since the stack
pointer increments when it pulls data from the stack. A
subroutine call results in only the program counter (PCH,
PCl) contents being pushed onto the stack, the remaining
CPU registers are not pushed.

COMP
This three-state output is the result of comparing the internal reference frequency to the variable divider signal. Refer
to PHASE LOCK LOOP for details. In self-check, cf>COMP is
raised to '" 9 Volts.
RESET
A low voltage level on this Schmitt trigger input will reset
the MPU. Refer to RESETS for additional information.
NUM
This pin is not for user application and must be connected
to VSS.
INPUT/OUTPUT LINES (PAO-PA7, PBO-PB7, PCO-PC2)
These 19 lines are arranged into two 8-bit ports (A and B)
and one 3-bit port (C). All lines are programmable as either
inputs or outputs under software control of the data direction registers. Refer to INPUT/OUTPUTS for additional information. The PCO/TIMER pin also serves as an external input to the internal timer. Refer to the TIMER section for information on the timer modes.

MEMORY
The MCU memory is configured as shown in Figure 5. The
MCU is capable of addressing 4096 bytes of memory and I/O
registers with its program counter. The MCU has impleFIGURE 5 -

MC6805T2 MCU ADDRESS MAP

o
Page Zero {
Access with
Short
Instructions

127
128

255

I/O Ports, RAM,
PLL, Timer
(128 bytes)
Page Zero
User ROM
(128 bytes)

256
User ROM
(1792 bytes)

SOOO
S07F
I\S08O
SOFF
S100

\

S7FF
S800

2047

2048

Not Used
(1344 bytes)

SD3F
SD40

3391
3392
ROM
(580 bytes)
3971
3972

4087
4088

Self-Check
ROM
(116 bytes)

SF83
SF84

SFF7
SFF8

Interrupt Vectors (8 bytes)
4095

$FFF

0

PortA Data

1

Port B Data

2

1

1

1

1

1

sooo

1

Port C
Data

S002

3

NOT USED

$003

4

PortA DDR

$004*

Port BOOR

5
6

NOT USED

I

S005*
Port C
DDR*

SOO6*

7

NOT USED

S007

8

Timer Data Register

SOO8

9

Timer Control Register

S009

10

Variable Divider LSB

$OOA

11
12
63

,~

1

1

I

Variable Divider MSB

$008

NOT USED
(52 bytes)

SOOC

User RAM
(64 bytes)

$03F
S040

Stack
(31 bytes maximum)

..

* Caution: Data direction registers (DDRs) are write-only; they read as SFF

3-485

S001

S07F

I

MC6805T2

FIGURE 6 -

5
n -4

FIGURE 7 -

INTERRUPT STACKING ORDER

1 1
1

Pull

4

Condition
Code Register

I

n

0

+1

Accumulator

n +2

n -2

Index Register

n +3

I

n

+4

11

n

+5

1 1 1

1

I

PCH*

PCl*

L.__A_ _ _ I Accumulator
0
x
I Index Register
0
PCl
I Program Counter
54
0
SP
I Stack Pointer
.......J

n -3

n -1

PROGRAMMING MODEL

11

PCH

Push

Condition Code Register

* For subroutine calls, only PCH and PCl are stacked.
Carry/Borrow

I

L..-_ _ _

Zero
Negative

'-------Interrupt Mask
L--_ _ _ _ _ _ Half Carry

CONDITION CODE REGISTER (CC)

REGISTERS

The condition code register is a 5-bit register in which four
bits are used to indicate the results of the instruction just
executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each individual condition code register bit is explained in the following paragraphs.

The MCU has five registers available to the programmer.
They are shown in Figure 7 and are explained in the following
paragraphs.
ACCUMULATOR (A)
The accumulator is a general purpose 8-bit register used to
hold operands and results of arithmetic calculations or data
manipulations.
INDEX REGISTER (X)
The index register is an 8-bit register used for the indexed
addressing mode. It contains an 8-bit value that may be
added to an instruction value to create an effective address.
The index register can also be used for data manipulations
using the read/modify/write instructions. The index register
may also be used as a temporary storage area.

HALF CARRY (H) - Set during ADD and ADC instructions to indicate that a carry occurred between bits 3 and 4.
INTERRUPT (I) - This bit is set to mask (disable) the
timer and external interrupt (lNT). If an interrupt occurs
while this bit is set, the interrupt is latched and is processed
as soon as the interrupt bit is cleared.
NEGATIVE (N) - Used to indicate that the result of the
LAST arithmetic, logical, or data manipulation was negative
(bit 7 in result equal to a logic one).

PROGRAM COUNTER (PC)
The program counter is a 12-bit register that contains the
address of the NEXT instruction to be executed.
STACK POINTER (SP)
The stack pointer is a 12-bit register that contains the
address of the next free location on the stack. Initially, the
stack pointer is set to location $07F and is decremented as
data is being pushed onto the stack and incremented as data
is being pulled from the stack. The seven most-significant
bits of the stack pointer are permanently set to 0CXl0011. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $07F. Subroutines
and interrupts may be nested down to location $061 (31
bytes maximum) which allows the programmer to use up to
15 levels of subroutine calls. A subroutine call occupies two
RAM bytes on the stack, while an interrupt uses five RAM
bytes.

ZERO (Z) - Used to indicate that the result of the LAST
arithmetic, logical, or data manipulation was zero.
CARRY/BORROW (C) - Used to indicate that a carry or
borrow out of the arithmetic logic unit (ALU) occurred during the LAST arithmetic operation. This bit is also affected
during bit test and branch instructions plus shifts and
rotates.
TIMER
The MC6805T2 timer circuitry is shown in Figure 8. The
8-bit counter may be loaded under program control and is
decremented toward zero by the clock input (prescaler output). When the timer reaches zero the timer interrupt request

3·486

MC6805T2

FIGURE 8 - TIMER BLOCK DIAGRAM
2
(lnternall]3
r- : -.,
I

I

I

I

PCOITIMER
Pin

I

L __ J

TCR5

Timer
Interrupt
Mask

TCR4

r---,
I

I

I
I
I
I
L ___ J

Clock
Input

Manufacturing
Mask Option

Internal Data Bus

bit (bit 7) in the timer control register (TCR) is set. The timer
interrupt can be masked (disabled) by setting the timer interrupt mask bit (bit 6) in the TCR. The interrupt bit (I bit) in the
condition code register also prevents a timer interrupt from
being processed. The MCU responds to this interrupt by saving the present CPU state on the stack, fetching the timer
interrupt vector from locations $FF8 and $FF9 and executing
the interrupt routine; see INTERRUPTS. The timer interrupt
request bit (TeR7) must be cleared by software.
The clock input to the timer is established via bit 5 (TCR5)
in the timer control register. When this bit is set (external
mode), the timer clock source is the PCO/TIMER pin. In this
mode a mask option is used to select either the cp2 gated with
PCO/TIMER or the positive transition on PCO/TIMER as
timer clock source. This allows easily performed pulse width
or pulse count measurements. When TCR5 is low, logic
zero, the timer clock source is the internal cp2.
Bit 4 in the timer control register (TCR4) disables the timer
clock source when set to logic one.
The maximum frequency of a Signal that can be recognized by the PCO/TIMER pin logic is dependent on the
parameter labeled tWL, tWH. The pin logic that recognizes
the high (or low) state on the pin must also recognize the low
(or high) state on the pin in order to "re-arm" the internal
logic. Therefore, the period can be calculated as follows:
(assumes 50/50 duty cycle for a given period).
tcyc x 2 + 250 ns

= period = -1f
req

The period is not simply tWL + tWH. This computation is
allowable, but it does reduce the maximum allowable frequency by defining an unnecessarily long period (250
nanoseconds twice).
When the cp2 Signal is used as the source, it can be gated
by an input applied to the PCO/TIMER input pin allowing the
user to easily perform pUlse-width measurements. (Note: for
ungated cp2 clock inputs to the timer prescaler, the

3-487

PCO/TIMER pin should be tied to Vce) The source of the
clock input is one of the mask options that is specified before
manufacture of the MC6805T2.
A prescaler option, divide by 2n , can be applied to the
clock input that extends the timing interval up to a maximum
of 128 counts before decrementing the counter. This prescaling mask. option is also specified before manufacture.
The timer continues to count past zero, falling through to
$FF from zero, and then continuing to count. Thus, the
counter can be read at any time by reading the timer data
register (TDR). This allows a program to determine the
length of time since a timer interrupt has occurred, and not
disturb the counting process.
At power-up or reset, the prescaler and counter are initialized with all logic ones; the timer interrupt request bit
(TCR7) is cleared; the timer interrupt mask bit (TCR6) is set;
the external timer source bit (TCR5) is cleared and the timer
disable bit (TCR4) is cleared.

SELF-CHECK
The self-check capability of the MCU provides an internal
check to determine if the part is functional. Connect the
MCU as shown in Figure 9 and monitor the output of Port C
bit 3 for an oscillation of approximately 3 hertz. A 9-volt level
on the cpCOMP input, pin 7, energizes the ROM-based selfcheck feature. The self-check program exercises the RAM,
ROM, timer, interrupts, and I/O ports.

RESETS
The MCU is reset whenever the RESET input line senses a
logic zero. This can be accomplished in two different ways:
(1) during power-up when a capacitor is used to hold the
RESET pin low for a specified time (tRHL); and (2) any time
after power-up that the RESET line falls to a logic zero for a
period longer than one tcyc. See Figures 10 and 11.

I

MC6805T2

I

The internal circuit connected to the RESET pin consists
of a Schmitt trigger which senses the RESET line logic level.
The Schmitt trigger provides an internal reset voltage if it
senses a logic 0 on the RESET pin. During power-up, the
Schmitt trigger switches on (removes reset) when the
RESET pin voltage rises to VIRES+. When the RESET pin
voltage falls to a logic 0 for a period longer than one tcyc, the
Schmitt trigger switches off to provide an internal reset
voltage. The "switch off" voltage occurs at VIRES _. A
typical reset Schmitt trigger hysteresis curve is shown in
Figure 11 (b).
Upon power-up, a delay of tRHL is needed before allowing
the reset input to go high. This time allows the internal clock
generator to stabilize. Connecting a capacitor to the RESET
input, as shown in Figure 11 (a), will provide sufficient delay.
See Figure 15 under INTERRUPTS for the complete reset sequence.

If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI (software interrupt) instruction is executed as any other instruction and as such will take
precedence over hardware interrupts only if the I bit is set
(interrupts masked).
Table 1 shows the execution priority of the RESET, INT
and timer interrupts, and instructions (including the software
interrupt, SWI). Two conditions are shown, one with the I
bit set and the other with I bit clear; however, in either case
RESET has the highest priority of execution. If the I bit is set
as per Table 1(a), the second highest priority is assi~ned to
any instruction including SWI. This is illustrated in Figure 15
which shows that the INT or timer interrupts are not tested
when the I bit is set. If the I bit is cleared as per Table 1(b),
the priorities change in that the next instruction (including
SWI) is not fetched until after the INT and timer interrupts
have been tested (and serviced). Also, when the I bit is clear,
if both INT and timer interrupts are pending, the INT interrupt is always serviced before the timer interrupt.

INTERNAL OSCILLATOR
The internal oscillator circuit has been designed to require
a minimum of external components. The use of a crystal or
an external Signal may be used to drive the internal oscillator.
The different connection methods are shown in Figures 12
and 13. The crystal specifications and suggested PC board
layout are given in Figure 14.
The crystal oscillator startup time is a function of many
variables: crystal parameters (especially Rs), oscillator load
capacitances, IC parameters, ambient temperature, and supply voltage. To ensure rapid oscillator startup, neither the
crystal characteristics nor the load capacitance should
exceed recommendations:

The external interrupt is internally synchronized and will
set a latch on the falling edge of INT. A sinusoidal input
Signal (fINT maximum) can be used to generate an external
interrupt, as shown in Figure 16(a) for use as a zero-crossing
detector with hystersis included. This allows for applications
such as time-of-day routines and engaging/disengaging ac
power control devices. As shown in Figure 17(a), off-chip
clamping limits the ac input to the VINT specification while
still providing an interrupt at every zero crossing of the ac
Signal.
For digital applications, as shown in Figure 16(b), the INT
input can be driven directly by a digital signal. The maximum
frequency of a Signal that can be recognized by the INT pin
logic is dependent on the parameter labeled tWL, tWH. The
logic that recognizes the high (or low) state on the pin must
also recognize the low (or high) state on the pin in order to
"re-arm" the internal logic. Therefore, the period can be
calculated as follows: (assumes 50/50 duty cycle for a given
period).

INTERRUPTS
The MC6805T2 MCU can be interrupted three different
ways: through the external interrupt (INT) input pin, the
internal timer interrupt request. or the software interrupt
instruction (SWI). When any interrupt occurs, processing is
suspended, the present CPU state is pushed onto the stack,
the interrupt bit (I) in the condition code register is set, the
address of the interrupt routine is obtained from the appropriate interrupt vector address, and the interrupt routine is
executed. Stacking the CPU registers, setting the I bit, and
vector fetching requires a total of 11 tcyc periods for completion.
A flowchart of the interrupt sequence is shown in Figure
15. The interrupt service routine must end with a return from
interrupt instruction (RTI) which allows the MCU to resume
processing of the program prior to the interrupt (by unstacking the previous CPU state).
Unlike RESET, hardware interrupts do not cause execution of the current instruction to be halted. Hardware interrupts are considered pending until execution of the current
instruction is complete.
As shown in Figure 15, when execution of the current
instruction is complete, the processor checks all pending
hardware interrupts and if unmasked (I bit = 0), proceeds
with interrupt processing; otherwise, the next instruction is
fetched and executed. Masked interupts are latched internally for later interrupt service.

tcyc x 2 + 250 ns = period

1
freq

The period is not simply tWL + tWH. This computation is
allowable, but it does reduce the maximum allowable frequency by defining an unnecessarily longer period (250
nanoseconds twice). For the INT function, the maximum
allowable frequency is also determined by the software
response of the INT service routine.
A software interrupt (SWI) is an executable instruction
which is executed regardless ,of the state of the I bit in the
condition code register; however, if the I bit is clear, a software interrupt (or any other instruction) cannot be executed
until after the INT and timer interrupts have been serviced.
SWls are usually used as breakpoints for debugging or as
system calls.

3-488

MC6805T2

FIGURE 9 -

2
L-

SELF-CHECK CONNECTIONS

TfiIT

PA7
MC6805T2

I

.r-11

1,OIL F

PA5

RESET

t,eL1 4

PA4

EXTAL

~

I

PA3

0

PA2

_T

I

5

ICL2 ~

--

10 kO
+9V

VVv

..

vv

..

J1f

4700
.AA A

vv.

VCC=Pln3
Vss=Pinl

-

21
20

PAO

r---

PB7

r---

I

PB6
17
PB5
PB4

PCOITIMER

.Jjf 9

A

22

18

NUM

8

~

4700
.A

24

23

19

J1f

J \ AA

PAl

-

COMP

~
4700

XTAL

25

7

-VVv

6

vCC

PA6

28

27
26

PCl

1O
PC2
11

16

15
PS3 ~
14
PS2
13
PSl
12
PSO

fin

FIGURE 10 -

POWER AND RESET TIMING

5VV~S ____________~;f~-------~~------------------------~
RESET
Pin

tRHL
Internal
Reset

FIGURE 11 -

POWER-UP RESET DELAY CIRCUIT

(b) Typical Reset Schmitt Trigger Hysteresis

(a) Delay Circuit

Out
of Reset

In Reset '--_t-1____t
1 -........._ 1...-_ _ __
0,8 V

3·489

2V

4V

MC6805T2

FIGURE 12 -

FIGURE 13 -

CRYSTAL OSCILLATOR

External
Clock
Input

EXTAL
(See Note) c::J
XTAL

MC6805T2
MCU

EXTERNAL OSCILLATOR

EXTAL
MC6805T2
XTAL

MCU

External Clock

I

NOTE: The recommended value of both CL 1 and CL2 with a 4.0
megahertz crystal is 27 picofarads maximum, including
system distributed capacitance. For crystal frequencies
other than 4 megahertz, the total capacitance on each pin
should be scaled as the inverse of the frequency ratio. For
example, with a 2-megahertz crystal, use approximately 50
picofarads for both CL 1 and CL2. The exact value depends
on the motional-arm parameters of the crystal used.

FIGURE 14 - CRYSTAL MOTIONAL ARM PARAMETERS
AND SUGGESTED PC BOARD LAYOUT
(a) Recommended Crystal Motional-Arm Parameters

C1

XTAL

~~EXTAL

5-~~4
AT - Cut Parallel Resonance Crystal
CO=7 pF Max.
FREQ=4.0 MHz @ CLl and CL2=24 pF
RS = 50 ohms Max.

(b) Suggested PC Board Layouts

NOTE: Keep crystal leads and circuit
connections as short as possible.

3·490

MC6805T2

FIGURE 15 -

RESET AND INTERRUPT PROCESSING FLOWCHART

Clear

1-1 (in CC)
07F-SP
O-DDRs
CLR INT Logic
FF-Timer
7F - Prescaler
7F-TCR
3FFF - PLL VaL Div.

Clear
INT
Request
Latch

liNT

I

And
TCR7= 1

Put FFE on
Address Bus

N

Fetch
Instruction

Is

Load PC
from
FFEI FFF

N

Execute
Instruction

TABLE 1 - INTERRUPT/INSTRUCTION EXECUTION
PRIORITY AND VECTOR ADDRESS
(a) I Bit Set
Interrupt/ Instruction
RESET
SWI (or Other Instruction)

Priority

Vector
Address

1
2

$FFE-$FFF
$FFC-$FFD

NOTE: INT and Timer Interrupts are not tested when the I bit is set;
therefore, they are not shown
(b) I Bit Clear
Interrupt/ Instruction
RESET
INT
Timer
SWI (or Other Instruction)

Priority
1

2
3
4

Vector
Address
$FFE-$FFF
$FFA-$FFB
$FFB-$FF9
$FFC-$FFD

INPUT/OUTPUT
There are 19 input/output pins. (The INT pin may also be
polled with branch instructions to provide an additional input
pin.) All pins (Ports A, B, and C) are programmable as either
inputs or outputs under software control of the corresponding data direction registers (DDR). The port I/O programming is accomplished by writing the corresponding bit in the
port DDR to a logic 1 for output or a logic 0 for input. On
reset all DDRs are initialized to a logic 0 state to put the ports
in the input mode. The port output registers are not initialized on reset and should be initialized before changing the
DDR bits to avoid undefined levels. When programmed as
outputs, all I/O pins read the latched output data, regardless
of the logic levels at the output pin due to output loading;
see Figure 17. When Port B is programmed for outputs, it is
capable of sinking 10 milliamperes and sourcing one
milliampere on each pin.

MC6805T2

FIGURE 16 - TYPICAL INTERRUPT CIRCUITS
(a) Zero Crossing Interrupt

(b) Digital Signal Interrupt
VCC

AC
(Current
Input
Limiting)
(fINT Max.)
Rs 1 MO -'V'I/\.,....--.....AC Input ~
10 Vpp

4.7 k

.....- - (

MC6805T2
MCU

TTL
Level
2
Digital - -...- - \
Input

iNi

MC6805T2
MCU

lJ

I
FIGURE 17 - TYPICAL PORT 1/0 CIRCUITRY

Data
Direction Register
Bit*

Latched
Output
Data
Bit

To Timer
for PCOITIMER Pin
Data
Direction
Register
Bit
1
1
0

Output
Data
Bit
0
1

X

Output
State

Input
To
MCU

0
1
3-State* *

0
1
Pin

* DDR is a write-only register and reads as all 1s.
* * Ports A (with CMOS drive disabled), B, and C are three-state ports. Port A has optional internal pullup devices to provide CMOS drive
capability. See Electrical Characteristics tables for complete information.

3·492

MC6805T2

All input/output lines are TTL compatible as both inputs
and outputs. Ports Band C are CMOS compatible as inputs.
Port A may be made CMOS compatible as outputs with a
mask option. Figure 18 provides some examples of port connections. The address map in Figure 5 gives the address of
the data registers and DDRs. The register configuration is
shown in Table 2.

port writes all of its data bits even though the
port DDR is set to input. This may be used to initialize the data registers and avoid undefined
outputs; however, care must be exercised when
using read/modify/write instructions since the
data read corresponds to the pin level if the DDR
is an input (0) and corresponds to the latched
output data when the DD R is an output (1).

Caution
The corresponding DDRs for ports A. B, and
C are write-only registers (registers at $004,
$005, and $006). A read operation on these
registers is undefined. Since BSET and BCLR
are read/modify/write functions, they cannot
be used to set or clear a DDR bit (all "unaffected" bits would be set). It is recommended
that all DDR bits in a port be written uSing a
single-store instruction.
The latched output data bit (see Figure 17)
may always be written. Therefore, any write to a

TABLE 2 -

PHASE LOCK LOOP
The PLL section consists of: a 14-bit binary variable
divider, a fixed 10-stage divider, a digital phase and frequency comparator with a three-state output, and circuitry
to avoid "backlash" effects in phase lock conditions.
With a suitable high-frequency prescaler and an active
integrator the user can easily establish a frequency synthesizer system driving a voltage controlled oscillator, as
shown in Figure 19. The equations governing the PLL are
given in Figure 20.

MCU REGISTER CONFIGURATION

PORT DATA REGISTER

o

7
Port A Addr = $000
Port B Addr = $001
Port C Addr= $002

PORT DATA DIRECTION REGISTER (DDR)
(1) Write Only; reads as aills
(2) 1 = Output, 0= Input. Cleared to 0 by Reset
(3) Port A Addr = $004
Port B Addr= $005
Port C Addr = $006

TIMER DATA REGISTER (TOR)

$OOB
MSB

LSB

TIMER CONTROL REGISTER ITCR)

$009
TCR Bits 0, 1, 2, and 3 read as 1s (not used)
TCR4- Disable Timer: 1 = Timer Stopped. 0= Timer
Allowed to Count. Cleared to 0 by Reset.
TCR5- External Timer Source: 1 = External, 0= Internal
2. Cleared to 0 by Reset.
TCR6- Timer Interrupt Mask Bit: 1 = timer interrupt
masked (disabled!. Set to 1 by Reset.
TCR7 - Timer Interrupt Request Status Bit: Set when
TDR goes to zero, must be cleared by software.
Cleared to 0 by Reset.

3-493

6

4

I

MC6805T2

FIGURE 18 -

TYPICAL PORT CONNECTIONS
(a) Output Modes

I

PA7

27

PA6

26

PB7

19

PA5

25

PB6

18

PA4

24

PB5

17

PA3

23

PB4

16

PB3

15

PB2

14

PBl

13

PBO

12

PA2

22

PAl

21

PAO

20

(CMOS Loads)

.--

(1 TTL Load)

1.6mA

Port A, Bit 7 Programmed as Output, Driving
CMOS Loads and Bit 4 Driving one TTL Load
Directly (using CMOS output option).

t
-'Ib
1.0mA

2N8386 (Typical)

-=-

Port B, Bit 5 Programmed as Output. Driving
Darlington-Base Directly.

+V
PB7

19

PB6

18

PB5

17

PB4

16

PB3

15

PB2

14

PBl

13

PBO

12

+V

10 mA
(maxi
~

10= HFE-Ib

~~

PC2

10

PCl

9

CMOS
Inverters

MC14049/MC14069
(Typical)

PCO/TIMER
~10mA(max)

Port C, Bits 0-2 Programmed as Output, Driving CMOS Loads, Using External Pullup
Resistors.

Port B, Bit 0 and Bit 1 Programmed as Output, Driving LEOs Directly.

(b) Input Modes

PA7

PB7

PA6

PB6

PA5
SN74LS04
(Typical)

24

PA4

23

PA3

22

PA2

SN74LS04
or
MC14069
(Typical)

17

PB5

16

PB4

15

PB3

14

PB2

PAl

PBl

PAO

PBO

TTL Driving Port A Directly.

CMOS or TTL Driving Port B Directly.

MC14069

[TYP~ :~/TiMER

SN74L~
(Typical)

CMOS and TTL Driving Port C Directly.

3-494

MC6805T2

VARIABLE DIVIDER

divider if followed by a write operation to register $OOA. For
correct operation of the variable divider, the absolute value
of the four lower significant bits of the 14-bit binary code
(loaded into the 14-bit latch) must be less than or equal to
the absolute value of the upper 10 bits. Figure 22 shows a
typical manipulation of the 14-bit data to the registers.
The use of the 14-bit latch synchronizes the data transfer
between two asynchronous systems, namely, the CPU and
the variable divider.
At power-up reset both the variable divider and the contents of the PLL registers are set to logic 1s.
The variable frequency input pin, fin, is self biased requiring an ac coupled signal with a minimum swing of 0.5 V. The
input frequency range of fin allows the device, together with
a suitable prescaler, to cover a given frequency spectrum.
For example, with a-+-64 prescaler the entire television frequency spectrum can be covered.

The variable divider is a 14-bit binary down counter which
communicates with the CPU via two read/write registers
located at address $ooA, for the LS byte, and $OOB, for the
MS byte. The upper two bits in register $ooB, always read as
logic 1s. When the variable divider count has reached zero a
preset pulse, fVAR, is generated.
The fVAR signal is applied to the phase comparator circuit
together with the fREF signal. The phase/frequency difference, between the two signals, results in an error signal
output (tPCOMP, pin 7) which controls the VCO frequency.
In addition, the fVAR pulse is also used to reload the 14-bit
variable divider latch as shown in Figure 21.
Data transfers from registers $ooA and $OOB to the latch
occur outside the preset time and only during a write operation performed on register $OOA. For example; a 6-bit data
transfer to register $ooB is only transferred to the variable

FIGURE 19 -

I

PHASE lOCK lOOP AN AN RF FREQUENCY SYNTHESIZER

fVCO

q,COMP

¥Varicap

Ilnte~t;-;

I

,------ ----------

11

;

Band
Information

fin

-,
I
I
I
I
I
I

I
I

I
I
MC6805T2

I

------------~
4
Varicap is a trademark of TRW Semiconductor

FIGURE 20 -

PRINCIPAL Pll EQUATIONS

For a system in lock:
fVAR = fREF
fVAR=fin+N
fin=fVCO+P
FVCO=fREFxpxN

Example for determining minimum frequency step:
fCl =4.00 MHz= Crystal frequency
fCLl4= 1.00 MHz= Internal Oscillator frequency
R= 21°= Reference Divider ratio
P = 64 = Prescaler division ratio

Where: P = Prescaler division ratio
N = Variable Divider division ratio

fREF=

~
4x R

6
= 4x 10 =976.5 Hz
4x 1024

Minimum frequency step =
~fVCO

~=976.5x64=625 kHz

3-495

MC6805T2

FIGURE 21 -

MC6805T2 PLL BLOCK DIAGRAM

CPU Data Bus

READ PLLHI

1 4 - - - - - - - - - READ PLLLOW

WRITE PLLHI

1. .- - - - - , . . . - - - WRITE PLLLOW

I

14

Variable Divider

tl>COMP 0 ....- - - - - - 1

Comparator

i--'I Manufacturing
L _ ..J Mask Option
I

Reference
Divider
+32

25

+16

24

+8

23

+4

22

-+-2

21

fREF

=

fCL

4x (2 1, 22 , ... 2 10)

~
lout of 10 Mask Option

FIGURE 22 - TYPICAL FINE TUNE EXAMPLE
FTPLU

TTl

FTMIN

TT2

LDA
INCA
BNE
INC
INC

PLLLOW

TST
BNE
DEC
DEC

PLLLOW
TT2
PLLHI
PLLLOW

TTl
PLLHI
PLLLOW

3-496

check if LS byte = $FF (Reg $OOA)
if not increment only LS byte
increment MSB (Reg $OOB) before LSB

check if LS byte = $00
if not decrement only LS byte
decrement MSB before LSB

MC6805T2

REFERENCE DIVIDER
This 10-stage binary counter generates a reference frequency, fREF, which is compared to the output of the variable divider. The reference divider is mask programable,
thus, allowing the user a choice of reference frequency, see
Figure 21.

integrated, amplified, and the resultant dc voltage is applied
to the voltage controlled oscillator varicap.
In practice a linear characteristic around the steady-state
region can not be achieved due to internal propagation
delays. Thus, phase comparators exhibit non-linear
characteristics and for systems which lock in phase, this
results in a "backlash" effect - creating sidebands and FM
distortion. To avoid this effect a very short pulse is injected
periodically into the system. The loop, in turn, attempts to
cancel this interference and in doing so brings the phase
comparator to its linear zero, as shown in Figures 25 and 26.
A typical application, for a TV frequency synthesizer, is illustrated in Figure 27.

PHASE COMPARATOR
The phase comparator compares the frequency and phase
of fVAR and fREF, and according to their phase relationship
generates a three-level output (1, 0, Hi-Zl, COMP, as
shown in Figures 23 and 24. The output waveform is then

FIGURE 23 -

PHASE COMPARATOR STATE DIAGRAM

I
cl>COMP
Output

3-State
High-Impedance

o

FIGURE 24 -

PHASE COMPARATOR OUTPUT WAVEFORM

fVAR

fR EF --4---1

1cl>COMP Hi-Z

0-

..

Phaselead

.

..

Phaselag

3-497

..

Stable State

MC6805T2

FIGURE 25 -

PHASE COMPARATOR CHARACTERISTICS

Ideal

y /

/

/

/
----r-------,.+7f---4-----....----I.. wLLetREF
-211"

I
FIGURE 26 -

PHASE COMPARATOR WITH PULSE INJECTION

Ideal

/

/

y/
/

/
--.-------+---+-+-+----r---....

wLLetREF

Stable State: tE-tERR-O
No Backlash Zone

MC6805T2

FIGURE 27 -

A TYPICAL TV SYNTHESIZER APPLICATION
4 MHz

o

MCl4497
Remote
Control
Transmitter

Data
ClK
MC6805T2

000
000
KEYBOARD

Varicap

Display

Band

or

ITCMl44102-CMOS Memory
MCM2801 NMOS 16x 16
Non-Volatile

BIT MANIPULATION
The MCU has the ability to set or clear any single randomaccess memory or input! output bit (except the data direction
registers, see Caution under INPUT /OUTPIJT), with a single
instruction (BSET, BCLR). Any bit in page zero including
ROM, except the DDRs, can be tested, using the BRSET
and BRCLR instructions, and the program branches as a
result of its state. The carry bit equals the value of the bit
referenced by BRSET and BRCLR. A rotate instruction may
then be used to accumulate serial input data in a RAM location or register. The capability to work with any bit in RAM,

FIGURE 28 -

ROM, or 1/0 allows the user to have individual flags in RAM
or to handle I/O bits as control lines.
The coding example in Figure 28 illustrates the usefulness
of the bit manipulation and test instructions. Assume that
the MCU is to communicate with an external serial device.
The external device has a data ready signal, a data output
line, and a clock line to clock data one bit at a time, LS B first,
out of the device. The MCU waits until the data is ready,
clocks the external device, picks up the data in the carry flag
(C bit), clears the clock line and finally accumulates the data
bits in a RAM location.

BIT MANIPULATION EXAMPLE

SELF

MCU
Ready
Serial
Device

Clock

BRSET

2, PORT A, SELF

BSET
BRClR
BClR
ROR

1, PORTA
0, PORT A, CaNT
1, PORTA
RAM laC

r-2 P
a
1 R
T

CaNT

Data

---°A

3-499

II

MC6805T2

ADDRESSING MODES
The MC6805T2 has 10 addressing modes which are explained briefly in the following paragraphs. For additional
details and graphical illustrations, refer to the M6805 Family
Users Manual.
The term "effective address" (EA) is used in describing the
address modes. EA is defined as the address from which the
argument for an instruction is fetched or stored.
IMMEDIATE
In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The immediate addressing mode is used to access constants which
do not change during program execution (e.g., a constant
used to initialize a loop counter).

I

DIRECT
In the direct addressing mode, the effective address of the
argument is contained in a single byte following the opcode
byte. Direct addressing allows the user to directly address
the lowest 256 bytes in memory (page zero) with a single
2-byte instruction. The address area includes the on-chip
RAM and I/O registers and 128 bytes of ROM. Direct addressing is an effective use of both memory and time.
EXTENDED
In the extended addressing mode, the effective address of
the argument is contained in the two bytes following the
opcode. Instructions using extended addressing are capable
of referencing arguments anywhere in memory with a single
3-byte instruction. When using the Motol ola assembler, the
programmer need not specify whether an instruction uses
direct or extended addressing. The assembler automatically
selects the shortest form of the instruction.
RELATIVE
The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit
Signed byte following the opcode (the offset) is added to the
PC if and only if the branch condition is true; otherwise, control proceeds to the next instruction. The span of relative
addressing is from -126 to + 129 from the opcode address.
The programmer need not worry about calculating the correct offset when using the Motorola assembler, since it
calculates the proper offset and checks to see if it is within
the span of the branch.
INDEXED, NO OFFSET
In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. Thus, this addressing mode can access the first 256
memory locations (page zero). These instructions are only
one byte long. This mode is often used to move a pointer
through a table or to hold the address of a frequently
referenced RAM or I/O location.
INDEXED, 8-BIT OFFSET
In the indexed, 8-bit offset addressing mode the effective
address is the sum of the contents of the unsigned 8-bit

3-500

index register (X) and the unsigned byte following the opcode. This addressing mode is useful in selecting the kth element in an n element table. With this 2-byte instruction, k
would typically be in X with the address of the beginning of
the table in the instruction. As such, tables may begin
anywhere within the first 256 addressable locations and
could extend as far as location 510 ($lFE).
INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit
index register and the two unsigned bytes following the opcode. This addressing mode can be used in a manner similar
to indexed, 8-bit offset; except that this 3-byte instruction
allows tables to be anywhere in memory. As with direct and
extended, the Motorola assembler determines the shortest
form of indexed addressing.
BIT SET/CLEAR
In the bit set/clear addressing mode, the bit to be set or
cleared is part of the opcode, and the byte following the opcode specifies the page-zero address of the byte in which the
specified bit is to be set or cleared. Thus, any read/write bit
in the first 256 locations of memory, including I/O, can be
selectively set or cleared with a single 2-byte instruction. See
Caution under INPUT/OUTPUT.
BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination
of direct addressing and relative addressing. The bit, which
is to be tested, and condition (set or clear) is included in the
opcode and the address of the byte to be tested is in the
single byte immediately following the opcode byte. The signed relative 8-bit offset in the third byteis added to the value
of the PC if the branch condition is true. This single 3-byte
instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory.
The span of branching is from - 125 to + 130 from the opcode address. The state of the tested bit is also transferred to
the Carry bit of the Condition Code Register. See Caution
under INPUT/OUTPUT.
INHERENT
In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, as well as control instruction with no other arguments, are included in this mode. These instructions are one
byte long.

INSTRUCTION SET
The MCU has a set of 59 basic instructions, which when
combined with the 10 addressing modes produce 207 usable
opcodes. They can be divided into five different types:
register/memory, read/modify/write, branch, bit manipulation, and control. The following paragraphs briefly explain
each type. All the instructions within a given type are
presented in individual tables.

MC6805T2

REGISTER/ MEMORY INSTRUCTIONS

~

xxx

xxx

Most of these instructions use two operands. One
operand is either the accumulator or the index register. The
other operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to
subroutine IJ S R) instructions have no register operand
Refer to Table 3.

800

080

READ/ MODIFY /WRITE INSTRUCTIONS
These instructions read a memory location or a register,
modify or test its contents, and write the modified value
back to memory or to the register (see Caution under INPUT/OUTPUT). The test for negative or zero ITST) instruc
tions is included in the read/modify/write instructions
though it does not perform the write. Refer to Table 4.

XXX= Customer 10
After the EPROM Is) are marked they should be placed in
conductive IC carriers and securely packed. Do not use
styrofoam.
VERIFICATION MEDIA

BRANCH INSTRUCTIONS

All original pattern media (EPROMs or Floppy Disk) are
filed for contractual purposes and a~e not returned. A computer listing of the ROM code will be generated and returned
along with a listing verification form. The listing should be
thoroughly checked and the verification form completed,
signed, and returned to Motorola. The signed verification
form constitutes the contractual agreement for creation of
the customer mask. If desired, Motorola will program one
blank EPROM from the data file used to create the custom
mask to aid in the verification process

The branch instructions cause a branch from the program
when a certain condition is met. Refer to Table 5.
BIT MANIPULATION INSTRUCTIONS
These instructions are used on any bit in the first 256 bytes
of the memory (see Caution under INPUT/OUTPUT). One
group either sets or clears. The other group performs the bit
test branch operations. Refer to Table 6.
CONTROL INSTRUCTIONS

ROM VERIFICATION UNITS (RVUs)

The control instructions control the MCU operations during program execution. Refer to Table 7.

Ten MCUs containing the customer's ROM pattern will be
sent for program verification. These units will have been
made using the custom mask but are for the purpose of
ROM verification only. For expediency they are usually unmarked, packaged in ceramic, and tested only at room
temperature and 5 volts. These RVUs are included in the
mask charge and are not production parts. The RVUs thus
are not guaranteed by Motorola Quality Assurance, and
should be discarded after verification is completed.

ALPHABETICAL LISTING
The complete instruction set is given in alphabetical order
in Table 8.
OPCODE MAP SUMMARY
Table 9 is an opcode map for the instructions used on the
MCU.

FLEXIBLE DISKS
The disk media submitted must be single-sided, singledensity, 8-inch, M'DOS- compatible floppies. The customer
must write the binary file name and company name on the
disk with a felt-tip pen. The minimum MOOS system files as
well as the absolute binary object file (fiiename, . LO type of
file) from the M6805 cross assembler must be on the disk. An
object file made from a memory dump using the ROLLOUT
command is also acceptable. Consider submitting a source
listing as well as the following files: filename, . LX( EXORciser
loadable format) and filename, . SA IASCII Source Codel
These files will of course be kept confidential and are used 1)
to speed up the process in-house if any problems arise, and
2) to speed up the user-to-factory interface if the user finds
any software errors and needs assistance quickly from
Motorola factory representatives.
MOOS is Motorola's Disk Operating System available on
development systems such as EXORciser, EXORset, etc.

ORDERING INFORMATION
The information required when ordering a custom MCU is
listed below. The ROM program may be transmitted to
Motorola on EPROM(s) or on MOOS disk file.
To initiate a ROM pattern for the MCU it is necessary to
first contact your local Motorola representative or
distributor.
EPROMs - Two MCM2716 or one MCM2532 type
EPROM(s), programmed with the customer program
(positive logic sense for address and data), may be submitted for pattern generation. The EPROM(s) must be clearly
marked to indicate which EPROM(s) corresponds to which
address space. The recommended marking procedure for
two MCM2716 EPROMs is illustrated below.

3-501

I

..
TABLE 3 -

:s:
o

REGISTER/MEMORY INSTRUCTIONS

0)

Addressing Modes

Immediate

11
Op
Mnemonic Code Bytes

Function

w
cJ,

oI\)

LOA

A6

Load X from Memory

LOX

AE

2

Store A In Memory

STA

-

-

Store X

STX

-

-

In

Memory

11
Cycles

/I
Op
Code Bytes

2

2

Load A from Memory

Direct

Extended
/I

Cycles

Op
/I
Code Bytes

86

2

4

C6

3

2

BE

2

4

CE

3

-

B7

2

5

C7

3

BF

2

5

CF

00

Indexed
(No Offset)
/I

Cycles

/I
Op
Code Bytes

Indexed
(88it Offset)
Op
II
Code Bytes

II

Cycles

C
U1

Indexed
(16-Bit Offset)

II

Cycles

11
OP
Code Bytes

-I

II

N

Cycles

5

F6

1

4

E6

2

5

06

3

6

5

FE

1

4

EE

2

5

DE

3

6

6

F7

1

5

E7

2

6

07

3

7

3

6

FF

1

5

EF

2

6

OF

3

7

Add Memory to A

ADD

AB

2

2

BB

2

4

CB

3

5

FB

1

4

EB

2

5

DB

3

6

Add Memory and
Carry to A

AOC

A9

2

2

B9

2

4

C9

3

5

F9

1

4

E9

2

5

09

3

6

Subtract Memory

SUB

AO

2

2

BO

2

4

CO

3

5

FO

1

4

EO

2

5

DO

3

6

Subtract Memory from
A with Borrow

SBC

A2

2

2

B2

2

4

C2

3

5

F2

1

4

E2

2

5

02

3

6

I

AND Memory to A

AND

A4

2

2

B4

2

4

C4

3

5

F4

1

4

E4

2

5

04

3

6

OR Memory with A

ORA

AA

2

2

BA

2

4

CA

3

5

FA

1

4

EA

2

5

OA

3

6

ExclUSive OR Memory
with A

EOR

A8

2

2

B8

2

4

(8

3

5

F8

1

4

E8

2

5

08

3

6

A"thmetlc Compare A
with Memory

CMP

A1

2

2

B1

2

4

C1

3

5

F1

1

4

El

2

5

01

3

6

ArIthmetic Compare X
with Memory

CPX

A3

2

2

B3

2

4

(3

3

5

F3

1

4

E3

2

5

03

3

6

Bit Test Memory with
A (Logical Compare)

BIT

A5

2

2

B5

2

4

(5

3

5

F5

1

4

E5

2

5

05

3

6

Jump Unconditional

JMP

-

2

3

((

3

4

FC

1

3

EC

2

4

DC

3

5

JSR

-

-

BC

Jump to Subroutine

BO

2

7

(0

8

FO

1

7

ED

2

8

DO

3

9

TABLE 4 -

3

READ/MODIFY/WRITE/ INSTRUCTIONS
Addressing Modes

Inherent (A)
Function

/I
Op
Mnemonic Code Bytes

II

Cycles

Inherent (X)
Op
II
Code Bytes

Increment

INC

4C

1

4

5C

II
II
Op
Cycles Code Bytes

1

Indexed
(No Offset)

Direct
II

Cycles

/I
Op
Code Bytes

Indexed
(8 Bit Offset)

11
Cycles

II
Op
Code Bytes

2

II

Cycles

4

3C

2

6

7C

1

6

6C

Decrement

DEC

4A

1

4

5A

1

4

3A

2

6

7A

1

6

6A

2

7

Clear

CLR

4F

1

4

5F

1

4

3F

2

6

7F

1

6

6F

2

7

Complement

COM

43

1

4

53

1

4

33

2

6

73

1

6

63

2

7

Negate
(2·s Comptement)

NEG

40

1

4

50

1

4

30

2

6

70

1

6

60

2

7

Rotate Left Thru Carry

ROL

49

1

4

59

1

4

39

2

6

79

1

6

69

2

7

Rotate Right Thru Carry

ROR

46

1

4

56

1

4

36

2

6

76

1

6

66

2

7

Logical Shift Left

LSL

48

1

4

58

1

4

38

2

6

78

1

6

68

2

7

7

Logical Shift Right

LSR

44

1

4

54

1

4

34

2

6

74

1

6

64

2

7

A"thmellc Shift Right

ASR

47

1

4

57

1

4

37

2

6

77

1

6

67

2

7

Test for Negative
or Zero

TST

40

1

4

50

1

4

3~

2

6

70 L 1
6__
60
--_

-

-

---

2
7
-'---- .

MC6805T2

TABLE 5 -

BRANCH INSTRUCTIONS
Relative Addressing Mode
Mnemonic

Function

Op
Code

#
Bytes

#
Cycles

Branch Always

BRA

20

2

4

Branch Never

BRN

21

2

4

Branch IFF Higher

BHI

22

2

4

Branch IFFLower or Same

BLS

23

2

4

BCC

24

2

4

(BHSI

24

2

4

Branch IFF Carry Set

BCS

25

2

4

(Branch IFF Lowerl

(BLOI

25

2

4

BNE

26

2

4

Branch IFFCarry Clear
(BranchlFFHlgher or Samel

Branch IFF Not Equal

BEQ

27

2

4

Branch IFF Half Carry Clear

BHCC

28

2

4

Branch IFF Half Carry Set

BHCS

29

2

4

Branch IFF Plus

BPL

2A

2

4

Branch IFF Equal

Branch IFF Minus

BMI

2B

2

4

Branch IFF Interupt Mask
Bit IS Clear

BMC

2C

2

4

BranchlFFlnterrupt Mask
Bit IS Set

BMS

20

2

4

Bil

2E

2

4

Branch IFF Interrupt line
IS low
BranchlFFlnterrupt line
IS High

BIH

2F

2

4

Branch to Subroutine

BSR

AD

2

8

TABLE 6 -

II

BIT MANIPULATION INSTRUCTIONS
Addressing Modes
Bit Set/Clear

Mnemonic

Function
Branch IFF Bit n
Branch IFF Bit n

Op
Code

Bit Test and Branch
Op
Code

#
Cycles

set

BRSET n (n = 0

71

-

--

-

clear

BRClR n (n = 0

71

-

--

-

IS
IS

#
Bytes

2. n
01

+-

2. n

#
Bytes

3

10

3

10

Set Bit n

BSET n (n = 0

71

10 + 2. n

2

7

-

-

Clear bit n

BClR n (n = 0

71

11 + 2. n

2

7

-

-

TABLE 7 -

CONTROL INSTRUCTIONS

Mnemonic

Op
Code

Inherent
#
Bytes

#
Cycles

Transfer A to X

TAX

97

1

2

Transfer X to A

TXA

9F

1

2

Set Carry Bit

SEC

99

1

2

Clear Carry BI1

ClC

98

1

2

Function

Set Interrupt Mask BI1

SEI

9B

1

2

Clear Interrupt Mask BI1

CLI

9A

1

2
11

Software Interrupt

SWI

83

1

Return from Subroutine

RTS

81

1

6

Return from Interrupt

RTI

80

1

9

Reset Stack POinter

RSP

9C

1

2

No-Operation

NOP

90

1

2

3-503

#
Cycles

MC6805T2

TABLE 8 -

INSTRUCTION SET

Addressing Modes

Condition Code
Bit

Mnemonic Inherent Immediate

Direct

Bit
Indexed
Indexed Indexed Set! Test &
Extended Relative (No Offset) (8 Bits) (16 Bits) Clear Branch
X
X
X
X

ADC

X

X

ADD

X

X

X

X

X

X

AND

X

X

X

X

X

X

ASl

X

X

X

X

ASR

X

X

X

X

BCC

I

X

BEG

X

BHCC

X

BHCS

X

BHI

X

BHS

X

BIH

X

Bil

X
X

BIT

X

X

X

X

BlS

X

BMC

X

BMI

X

BMS

X

BNE

X

BPl

X

BRA

X

BRN

X

X

X

BRSET

X
X
X

BSR
Cll

X

CLI

X

ClR

X

COM

X

INC

X

X

X

X

X
X

EaR

X
X

X

CPX
DEC

X
X

CMP

X

X

X

X

JMP

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X
X
X

X

X

X

X

X

X

X

X

X

X

lOA

X

X

X

X

X

X

lOX

X

X

X

X

X

X

X

X

JSR

lSl

X

X
X

X

X

X

NEG

X

X

X

X

Nap

X

lSR

X

ORA
ROl

X

RSP

X

X

X

X

Condition Code Symbols:
H Half Carry (From Bit 3)
Interrupt Mask
N Negative (Sign Bit)
Z Zero

X

X

X

X

Z

C

/I

/I

/I
/I

/I

/I

/I

/I

/I

••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
• •0 • •
• •0 •1
••
••
••
/I

/I

/I

/I

••
••
••
••
••••
••••
••
••
•
••0
••
••••
••
••
••••
/I

/I

/I

/I

/I

/I

/I

/I

/I

/I

/I

/I

/I

•

/I
/I

X

C Carry/Borrow
II Test and Set if True, Cleared Otherwise
• Not Affected
o Cleared

3-504

/I
/I

/I

BRClR
BSET

•
•

/I

X

BlO

N

••
••
••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••

X

BCS

I

/I
/I

X

BClR

H

/I

/I

/I

/I

/I

/I

/I

•
/I

/I

•

•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
/I
/I

•
•
•
•
0

/I

1
/I

•
••
•
•
•
•
/I

/I
/I

•
•
•
/I

MC6805T2

TABLE 8 -

INSTRUCTION SET (Continued)

Addressing Modes

Mnemonic Inherent Immediate
RTI

X

RTS

X
X

SBC
SEC

X

SEI

X

Direct

X

Condition Code

Bit
Bit
Indexed
Indexed Indexed Set! Test &
Extended Relative (No Offset) (8 Bits) (16 Bits) Clear Branch

X

X

X

X

X

X

X

X

X

STX

X

X

X

X

X

X

X

X

X

X

X

SWI

X

TAX

X

TST

X

TXA

X

I

N

Z

)

)

)

)

••• •
••
••••
• ••
••
••
••
• ••
••••
/\

/\

C
)

•
/\
1

•
•
•
•
•
••
•
•••• •
1

STA
SUB

H

/\

/\

/\

/\

/\

/\

/\

/\

/\

1

X

Condition Code Symbols
H Half Carry (From Bit 31
Interrupt Mask
N Negative (Sign Bitl
Z Zero

X

X

C Carry/Borrow
1\ Test and Set If True, Cieared Otherwse
• Not Affected
7 Load CC Register From Stack
Set

3-505

II

iii
s:

(")

m

TABLE 9 -

00

o

M6805 HMOS FAMILY OPCODE MAP

CJ'I

Bit Manipulation
BTB
BSt

~

rlio

INH
4

J,1

0100

5

01~0

IX
7

INH
8

0111

1000

INH
9

IMM
A

DIR

1010

1011

B

rk

BASE
3
JfB

2

10

7

4

1

BACLAO
BTB
3

BCLAO
2
Bse

BRN
REL
2

10

7

4

4

2 BSE~1e

2

BASETl
BTB
3

2 BHIREI

SBC
IMM
2

SBC
OIR
2

10

7

4

6

4

4

11

2

4

BACLAl
BTB
3

BCLRl
Bse
2

BLS
REL
2

COM
OIR
2

COMA
1
INH

COM X
1
INH

SWI
1
INH

4

6

4

4

CPX
IMM
2
2
AND
IMM
2
2
BIT
IMM
2
LDA
IMM
2

0010

3
0011

4
0100

10

7

BASET2
BTB
3

2

10

5
0101

6
0110

7
0111

8
1000

9
1001

BSE~~e

BSET2
Bse

7

4

BAA
REL

2

6

4

2 NEG
D1R

1

BCC
REL

2

2

BCLR2
Bse

1

NEG

NEG
1X1

1

RTI
IX

6

COM
2

IXl

7

LSRX
INH

4

6

4

4

BSET3
2
Bse

INH

1

2
2

COM
1

IX

2

INri

6

LSR
2

IXl

LSR
1

BNE
REL
2

AOR
OIR
2

RORA
1
INH

RORX
1
INH

4

6

4

4

10

7

BRCLR3
BTB
3

2 BCL~~e

10

7

BRSET4
3
BTB

2

10

7

BRCLA4
BTB
3

2

BEQ
REL
4

BSE~1e

2
2

ASR
DIR

BHCC
REL

2

LSL

OIR

2

ASRA
INH

1

ROL

DIR

1

1

ASRX
INH

LSLA
INH

INH

1

ROLX
INH

10

7

4

6

4

4

DEC
OIR
2

DECA
1
INH

DECX
1
INH

7

4

1100

BSET6
2
Bse

BMC
REL
2

2

7

4

rC::~B

2 BCL~~e

6

D

2 BMS
REL
4

10

7

3BASET7
BTB

2

10

7

BRCLA7
BTB
3

BCLA7
Bse
2

BSET7
Bse

2

IX

ASR

IXl

1
6

IXl

1
6

2

LSL

IXl

ROR
IX

1

1

IX

ROL

IXl

7

DEC
2

LSL

CLC
INH

IX
2

ROL
1
6

IX

1

SEC
INH

2
DEC

IX 1

TAX
INH

2

6

2

CLI

IX

1

!NH

2
SEI
1

6

BIL

INC
TST

2

OIR
OIR

4

INCA
1
INH

INCX
1
INH

2

4

4

7

TSTA
1
INH

TSTX
1
INH

2

6

INC

IX 1

INC
1
6

TST
2

TST
1X1

INH

1

ASP
1
INH
2
NOP

IX
IX

1

INH

REL
-6

4

BIH

7

4

REL

2

CLR

OIR

4

4

CLRA
1
INH

CLRX
1
INH

7

2

2

6

CLR

IXl

CLR
1

IMM

2

ASR

BMI
REL

2
2

2

6

7

3BASET5
BTB

BCLA5
Bse

2
7

LSLX
1
4

ROLA
INH

ROR

7

4

4

6

BHCS
REL

1
4

6

4

BCLA4
Bse

2

7

SUB
IMM
CMP

BCS
REL

2

BASET6
BTB
3

1111

LSRA
INH

7

10

F

1

2

4

E

LSR
OTR

BASET3
BTB
3

10

2

7

10

2

1101

NEG
INH

BACLA2
BTB
3

7

1110

1

4

2 BSE~~c

C

:NH

IX

--

1100

2
2 EOR
IMM
2
ADC
IMM
2
2
ORA
IMM
2
2
ADD
IMM
2

2

SUB
OIR

TXA
1
INH

CMP
OIR
2

CMP
EXT
3
5
SBC
EXT
3
5
CPX
EXT
3

CPX
2

Inherent
Immediate
Direct
Extended
Relative
Bit Set/Clear
Bit Test and Branch
Indexed (No Offset)
Indexed, 1 Byte (S-Bit) Offset
Indexed, 2 Byte (16-Bitl Offset

OIR

AND
01"

4

BIT

OIR

2

3
5

BIT

EXT

3
5

LDA
OIR
2

LDA
EXT
3

5

6

STA
OIR

4

EOR
2

OIR

ADC
OIR

4

ORA
OIR
2
4

2

ADD
OIR

3

3

3

IX2

6

SBC
3

IX2

6

CPX
3

IX2
IX2

BIT

IX2

3

ADC
EXT

5 ADD
EXT
3

IX2
IX2

IXl

EOR
3

IX2

ADC
3

IX2

bORA
IX2
3
6

ADD
3

IX2

SUB
1

CMP
IXl
2
5
SBC
IXl
2

4

5

4

CPX

IXl

2

BIT

IXl
IXl

SBC
1

CPX
1

AND
1
4

BIT
1

IXl

2

LDA

JMP

IX

0001

IX

1
2
0010

I

3

IX

0011

IX

0100

IX

0101

4
5

1

6

IX

0110

IX

0111

IX

1000

IX

1001

5

STA

IXl

EOR

IXl

2
5

STA
1
4

EOR
1

7

i

I

8

4

ADC

IXl

2

IXl

2

ADC
1

• OAA

5 OAA

5 ADD
IXl
2

1

JMP

ADD
1
.j

IX2

2

IX2

" JSR
IXl
2

IXl

IX2

' LDX
IXl
2

9
A

IX

1010

IX

1011

IX

1100

4

4

3

rk

4

LDA

2

I

CMP

4

AND
2
5
2

IX

4

5

5

JMP
EXT
3

SUB

6

STA
3

6

, ORA
EXT
3

2

N

~

4

5

LDA

6

EOR
EXT

1111

5

AND
3

7

STA
EXT

4

JMP

1

B
C

8

JSR
2

OIR

4

2
5

3

CMP

3

1110

5

6

5

4

2

3
5

IX2

6

4

2

SUB
3

6

AND
EXT

E

IX
F

5

6

5

4

2

LDX
OIR

STX
OIR
2

JSR
EXT
3

"

,

"

3
6

LDX
EXT

STX
EXT
3

JSA

3

JSA
1

D

IX

1101

IX

1110

IX

1111

4

LDX

3
7

6

STX
3

IX2

STX
2

IXl

LDX
1
5

STX
1

E

F

LEGEND

Abbreviations for Address Modes
INH
IMM
DIR
EXT
REL
BSC
BTB
IX
IXl
IX2

SUB
EXT

5

7

BSA
REL
2
2
LDX
IMM
2

6

4

JMP
OIR
2
8

3

IXl

1101

5

4

2

1

10

B
1011

NEG

9

6

RTS

BACLA5
BTB
3

1010

7

4

1001

6

BPL
2
REL

A

0101

-I

Register / Memory
EXT
1X2
C
0

Control

Read/ Modify/Write
IXl
INH

7

2

0>

DIR

rk
10

0001

w
in
o

~1

Branch
REL

Mnemonic

3

# of Cycles (CMOSI

1

# of eyel" IHMOSI

4
..

F

1111

~.~~------------~7

SUB

1

1)1._

:::=1

Opcode in Hexadecimal

Opcode in Binary

Ul1JU~

' - - - - - - - - - - Address Mode

MC6805T2

MC6805T2 MCU CUSTOM ORDERING INFORMATION
Date _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Customer PO Number _ _ _ _ _ _ _ _ _ __
Motorola Part Numbers

Customer Company
Address

MC - - - - - - - - - - - - - - - - - - - - - - - - - · - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S C ______________

City _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ State _ _ _ _ _ _ _ _ _ _ _ _ _ Zip _ _ _ _ __
Country _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Phone _ _ _ _ _ _ _ _ _ _ _ __

Extension _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Customer Contact Person _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Customer Part Number _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
OPTION LIST
Select the options for your MCU from the following list A
manufacturing mask will be generated from this information
Timer Clock Source
Internal 2 clock (gated by PCOITIMER)
PCO/TIMER input pin (positive transition)

o
o

Timer Prescaler
o 20 (divide
o 21 (divide
o 22 (divide
o 23 (divide

by
by
by
by

Port A Output Drive
0 CMOS and TTL
0 TTL Only
o Open Drain

1)
2)
4)
8)

PLL Reference Divider
o 21 (divide by 2)
o 22 (divide by 4)
o 23 (divide by 8)
24 (divide by 16)
25 (divide by 32)

o
o

o
o
o
o

24 (divide by 16)
25 (divide by 32)
26 (divide by 64)
27 (divide by 128)

o
o
o
o
o

26 (divide by 64)
27 (divide by 128)
28 (divide by 256)
29 (divide by 512)
2 10 (divide by 1024)

Pattern Media (All other media requires prior factory approval

o

EPROMS (two MCM2716s or one MCM2532)

0 Floppy Disk

o

Other _ _ _ _ _ _ __

Clock Freq. _ _ _ _ _ _ _ _ _ _ _ __
Temp. Range _ _ _ _ _ _ _ _ _ _ _ __

o

0° to + 70 D C (Standard)

0

-40° to +85°C*

* Requires prior factory approval
Marking Information (12 Characters Maximum)
Title _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Signature _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

3-507

I

®

MOTOROLA

Advance Information

I
MC68HC05C4
8-BIT MICROCOMPUTER

This document contaIns InformatIon on a new product. SpecIfIcatIons and onformatlon hereon
are subject to change without notice

3-508

MC68HC05C4

TABLE OF CONTENTS
Paragraph
Number

Title

Page
Number

Section 1
Introduction

3-516
3-516

1.1
1.2

General ..
Features.

2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.6.1
2.1.6.2
2.1.6.3
2.1.7
2.1.8
2.1.9
2.1.10
2.2
2.2.1
2.2.2
22.3
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.5.1
2.4.5.2
2.4.5.3
2.4.5.4
2.4.5.5

Section 2
Functional Pin Description, Input/Output Programming,
Memory, CPU Registers, and Self-Check
Functional Pin Description.
VDD and VSS
IRQ (Maskable Interrupt Request).
RESET
......... .
TCAP
TCMP
OSC1, OSC2 .
Crystal.
RC ..................... .
External Clock .
PAO-PA7.
PBO-PB7.
PCO-PC7.
PDO-PD5, PD7 .
Input/Output Programming .... .
Parallel Ports
.......... .
Fixed Port.
Serial Ports (SCI and SPI)
Memory ............ .
CPU Registers
Accumulator (A) ..
Index Register (X) .
Program Counter (PC)
Stack Pointer (SP)
Condition Code Register (CC) ..
Half Carry Bit (H) .
Interrupt Mask Bit (I).
Negative (N) ...
Zero (Z) .
Carry/Borrow (C)

3-509

3-518
3-518
3-518
3-518
3-518
3-518
3-519
3-519
3-520
3-520
3-520
3-520
3-520
3-520
3-521
3-521
3-522
3-522
3-522
3-524
3-525
3-525
3-525

3-525
3-525
3-525
3-525
3-526
3-526
3-526

I

MC68HC05C4

TABLE OF CONTENTS
(Continued)
Paragraph
Number

2.5
2.6
2.7

Page
Number

Title

Self-Check
Timer Test Subroutine.
ROM Checksum Subroutine ...

.........

3-526
3-526
3-526

Section 3
Resets, Interrupts, and Low Power Modes

II

3.1
3.1.1
3.1.2
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.3
3.3.1
3.3.2

Resets.
RESET Pin.
Power-On Reset
Interrupts
Hardware Controtled Interrupt Sequence
Software Interrupt (SWI)
Externa I Interru pt
Timer Interrupt.
Serial Communications Interface (SCI) Interrupts
Serial Peripheral Interface (SPI) Interrupts
Low Power Modes
STOP Instruction
WAIT Instruction

3-528
3-528
3-528
3-528
3-531
3-531
3-531
3-535
3-535
3-535
3-536
3-536
3-536

Section 4
Programmable Timer

4.1
4.2
4.3
4.4
4.5
4.6

Introduction ..
Counter.
Output Compare Register
Input Capture Register.
Timer Control Register (TCR)
Timer Status Register (TSR)

3-537
3-543
3-543
3-544
3-545
3-546

Section 5
Serial Communications Interface (SCI)

5.1
5.1.1
5.1.2
5.1.3
5.2
5.3
5.4
5.5
5.6
5.7
5.7.1
5.7.2

Introduction ..
SCI Two-Wire System Features.
SCI Receiver Features
SCI Transmitter Features.
Data Format ..
Wake-Up Feature
ReceiveData In ...
Start Bit Detection Following a Framing Error ..
Transmit Data Out (TDO) .
Registers ..
Serial Commu nications Data Register (S C DA T) .
Serial Communications Control Register 1 (SCeR1)

3-510

3-547
3-547
3-547
3-547
3-548
3-548
3-548
3-549
3-551
3-551
3-551
3-551

MC68HC05C4

T AS LE OF CONTENTS
( Continued)
Paragraph
Number

5.7.3
5.7.4
5.7.5

6.1
6.1.1
6.1.2
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.3
6.4
6.4.1
6.4.2
6.4.3
6.5

Title

Serial Communications Control Register 2 (SCCR2)
Serial Communications Status Register (SCSR)
Baud Rate Register.
Section 6
Serial Peripheral Interface (SPI)
Introduction and Features
Introduction.
Features ..
Signal Description ..
Master Out Slave In (MOSI).
Master In Slave Out (MISO).
Slave Select (SS)
Serial Clock (SCK)
Functional Description
Registers.
Serial Peripheral Control Register (SPCR) .
Serial Peripheral Status Register (SPSR) .
Serial Peripheral Data I/O Register (SPDR) ..
Serial Peripheral Interface (SPI) System Considerations ...

Page
Number

3-553
3-555
3-556

3-559
3-559
3-559
3-559
3-559
3-562
3-562
3-563
3-563
3-565
3-565
3-566
3-569
3-569

Section 7
Effects of Stop and Wait Modes on The
Timer and Serial Systems

7.1
7.2
7.2.1
7.2.2
7.2.3
7.3

Introduction
Stop Mode ..
Timer During Stop Mode ..
SCI During Stop Mode.
SPI During Stop Mode.
Wait Mode ..

3-571
3-571
3-571
3-571
3-572
3-572

Section 8
Instruction Set and Addressing Modes

8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.2
8.2.1

Instruction Set.
Register/ Memory Instructions
Read-Modify-Write Instructions ..
Branch Instructions.
Bit Manipulation Instructions
Control Instructions
Alphabetic Listing ..
Opcode Map
Addressing Modes
Inherent

3-511

3-573
3-573
3-573
3-576
3-576
3-577
3-577
3-577
3-577
3-581

I

MC68HC05C4

TABLE OF CONTENTS

(Concluded)
Paragraph
Number

I

8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10

Title

Page
Number

3-581
3-581
3-581
3-581
3-581
3-582
3-582
3-582
3-582

Immediate
Direct
Extended
Indexed, No Offset
Indexed, 8-Bit Offset ...
Indexed, 16-Bit Offset.
Relative ...
Bit Set/Clear ..
Bit Test and Branch
Section 9
Electrical Specifications

9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10

Introduction.
Maximum Ratings.
Thermal Characteristics
Power Considerations ...
DC Electrical Characteristics (VDD = 5.0 Vdcl .
DC Electrical Characteristics (VDD = 3.3 Vdcl ..
Control Timing (VDD = 5.0 Vdc) ...
Control Timing (VDD = 3.3 Vdcl ..
Serial Peripheral Interface (SPI) Timing (VDD = 5.0 Vdcl
Serial Peripheral Interface (SPI) Timing (VDD=3.3Vdcl ....

3-584
3-584
3-584
3-585
3-585
3-586
3-587
3-588
3-589
3-590

Section 10
Ordering Information

10.1
10.1.1
10.1.2
10.2
10.3
10.4

Introduction .. .
EPROMs .......... .
MDOS Disk File ....... .
Verification Media ..
ROM Verification Units ...
Flexible Disks ...

3-595

3-595
3-595
3-596
3-596
3-596

Section 11
Mechanical Data

11.1

Pin Assignments ...

3-598

3-512

MC68HC05C4

LIST OF ILLUSTRATIONS
Figure
Number

Title

Page
Number

1-1

MC68HC05C4 Microcomputer Block Diagram

3-517

2-1
2-2
2-3
2-5
2-6
2-7

Oscillator Connections ..
Typical Frequency vs Resistance for RC Oscillator Option Only.
Typical Parallel Port I/O Circuitry ..
Address Map ..
Programming Model ..
Stacking Order ....
Self-Check Circuit Schematic Diagram

3-519
3-520
3-521
3-523
3-524
3-524
3-527

3-1
3-2
3-3
3-4

Power-On Reset and RESET.
Hardware Interrupt Flowchart ..
STOP/WAIT Flowcharts.
External Interrupt ........... .

3-529
3-532
3-533
3-534

4-1
4-2
4-3
4-4
4-5

Programmable Timer Block Diagram
Timer State Timing Diagram For Reset
Timer State Timing Diagram For Input Capture
Timer State Timing Diagram For Output Compare ...
Timer State Timing Diagram For Timer Overflow ..

3-538
3-539
3-540
3-541
3-542

5-1
5-2
5-3
5-4
5-5
5-6
5-7

Data Format ..................... .
Examples of Start Bit Sampling Technique.
Sampling Technique Used on All Bits ....
SCI Artificial Start Following a Framing Error .... .
SCI Start Bit Following a Break ............... .
Serial Communications Interface Block Diagram ............ .
Rate Generator Division ............... .

3-548
3-549
3-549
3-550
3-550
3-552
3-558

6-1
6-2
6-3
6-4

Master-Slave System Configuration ....... .
Data Clock Timing Diagram ...
Serial Peripheral Interface Block Diagram
Serial Peripheral Interface Master-Slave Interconnection ...

3-560
3-561
3-564
3-565

9-1
9-2

Equivalent Test Load ............. .
Typical Operating Current vs Internal Frequency ......... .

3-584
3-586

2-4

3-513

I

MC68HC05C4

LIST OF ILLUSTRATIONS
( Continued)
Figure
Number
9-3
9-4
9-5
10-1
10-2

Title
Stop Recovery Timing Diagram
Timer Relationships ..
Timing Diagrams.

Page
Number
3-587

3-588
3-591

EPROM Marking Example ... .
Ordering Form. . ............ .

I

3-514

3~595

3-597

MC68HC05C4

LIST OF TABLES
Table
Number

Title

Page
Number

2-1
2-2

I/O Pin Functions.
Self-Check Results .

3-522
3-527

3-1
3-2

Reset Action on Internal Circuit.
Vector Address for Interrupts and Reset ..

3-530
3-530

5-1
5-2

Prescaler Highest Baud Rate Frequency Output.
Transmit Baud Rate Output For a Given Prescaler Input.

3-558
3-558

8-1
8-2
8-3
8-4
8-5
8-6
8-7

Register/ Memory Instructions
Read-Modify-Write Instructions.
Branch Instructions.
Bit Manipulation Instructions.
Control Instructions
Instruction Set ..
MC68HC05C4 HCMOS Instruction Set Opcode Map ...

3-574
3-575
3-576
3-576
3-577
3-578
3-580

3-515

I

MC68HC05C4

SECTION 1
INTRODUCTION
1.1 GENERAL
The MC68HC05C4 HCMOS Microcomputer is a member of the M68HC05 Family of low-cost singlechip microcomputers. This 8-bit microcomputer contains an on-chip oscillator, CPU, RAM, ROM,
1/0, two serial interface sytems, and timer. The fully static design allows operation at frequencies
down to dc, further reducing its already low-power consumption.

1.2 FEATURES
The following are some of the hardware and software highlights of the MC68HC05C4.

I

HARDWARE FEATURES
• HCMOS Technology
• 8-Bit Architecture
• Power Saving Stop and Wait Modes
• Fully Static Operation
• 176 Bytes of On-Chip RAM
• 4160 Bytes of On-Chip ROM
• 24 Bidirectional 1/0 Lines
• 2.1 MHz Internal Operating Frequency at 5 Volts; 1.0 MHz at 3 Volts
• Internal 16-Bit Timer Similar to MC6801 Timer
• Serial Communications Interface System
• Serial Peripheral Interface System
• Self-Check Mode
• External, Timer, Serial Communications Interface, and Serial Peripheral Interface Interrupts
• Master Reset and Power-On Reset
• Single 3- to 6-Volt Supply
• On-Chip Oscillator with RC or Crystal Mask Options
• 40-Pin Dual-In-Line Package
• Chip Carrier Also Available
SOFTWARE FEATURES
• Similar to MC6800
• 8 x 8 Unsigned Multiply Instruction
• Efficient Use of Program Space
• Versatile Interrupt Handling

3-516

MC68HC05C4

SOFTWARE FEATURES (Continued)

• True Bit Manipulation
• Addressing Modes with Indexed Addressing for Tables
• Efficient Instruction Set
•
•
•
•

Memory Mapped I/O
Two Power-Saving Standby Modes
Upward Software Compatible with the M146805 CMOS Family
Complete Development System Support on EXORciser and HDS-200

TCMP

OSCl

I

OSC2

TCAP --37
~------------~ RESET
·~----------~~IRQ

Port
A
I/O
lines

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7

Accumulator
A

8
Port
A
Reg

Data
Dir
Reg

Index
Register

CPU
Control

X

Data
Dir
Reg

Port

C
Reg

Condition
Code
Register CC

PCO
PCl
Port
PC2
C
PC3
I/O
PC4
Lines
PC5
PC6 _
PC7

CPU

Port
B
I/O
lines

PBO
PBl
PB2
PB3 PB4
PB5
PB6
PB7

Stack
Pointer
Port
B
Reg

Data
Dir
Reg

Port 0
S

Program
Counter
High PCH
Program
Counter
low PCl

SCI
System
AlU

SPI
System
Baud Rate
Generator
Internal
Processor
Clock

240 x 8
Self-Check
ROM

Figure 1-1. MC68HC05C4 Microcomputer Block Diagram

3-517

PD7
RDI (POOl
TOO (POll
MISO (PD21
MOSI (PD31
SCK (PD41
55 (PD51

MC68HC05C4

SECTION 2
FUNCTIONAL PIN DESCRIPTION, INPUT/OUTPUT PROGRAMMING,
MEMORY, CPU REGISTERS, AND SELF-CHECK
This section provides a description of the functional pins, input/output programming, memory,
CPU registers, and self-check.
2.1 FUNCTIONAL PIN DESCRIPTION
2.1.1 VDD and VSS

Power is supplied to the MCU using these two pins. VDD is power and VSS is ground.

I

2.1.2 IRQ (Maskable Interrupt Request)

I RQ is a programmable option which provides two different choices of interrupt triggering sensitivity. These options are: 1) negative edge-sensitive triggering only, or 2) both negative edgesensitive and level-sensitive triggering. In the latter case, either type of input to the IRQ pin will produce the interrupt. The MCU completes the current instruction before it responds to the interrupt
request. When the IRQ pin goes low for at least on tILlH, a logic one is latched internally to Signify
an interrupt has been requested. When the MCU completes its current instruction, the interrupt
latch is tested. If the interrupt latch contains a logic one, and the interrupt mask bit (I bit) in the condition code register is clear, the MCU then begins the interrupt sequence.
If the option is selected to include level-sensitive triggering, then the I RQ input requires an external
resistor to VDD for "wire-OR" operation. See INTERRUPTS in Section 3 for more detail concerning
interrupts.
2.1.3 RESET

The RESET input is not required for startup but can be used to reset the MCU internal state and provide an orderly software startup procedure. Refer to RESETS in Section 3 for a detailed description.
2.1.4 TCAP

The TCAP input controls the input capture feature for the on-chip programmable timer system.
Refer to INPUT CAPTURE REGISTER in Section 4 for additional information.
2.1.5 TCMP

The TCMP pin (35) provides an output for the output compare feature of the on-chip timer system.
Refer to OUTPUT COMPARE REGISTER in Section 4 for additional information.

3-518

MC68HC05C4

2.1.6 OSC1, OSC2
The MC68HC05C4 can be configured to accept either a crystal input or an RC network to control
the internal oscillator. The internal clocks are derived by a divide-by-two of the internal oscillator frequency (foscl.
2.1.6.1 CRYSTAL. The circuit shown in Figure 2-1 (b) is recommended when using a crystal. The
internal oscillator is designed to interface with an AT-cut parallel resonant quartz crystal resonator
in the frequency range specified for fosc in 9.7 or 9.8 Control Timing. Use of an external CMOS
oscillator is recommended when crystals outside the specified ranges are to be used. The crystal
and components should be mounted as close as possible to the input pins to minimize output
distortion and startup stabilization time. Refer to 9.5 or 9.6 for VDD specifications.

2 MHz

4 MHz

400

75

[}

Co

5

7

Cl

0.008

0.012

COSCl

15-40

15-30

COSC2
Rp

15-30

RSMAX

Q

I

Units

15-25

pF
/L F
pF
pF

10

10

M[}

30

40

K

(a) Crystal Parameters

:cy

MC68HC05C4
OSCl

L

SC2

OSC2

RS

Cl

~

39

Rp

o

38

"J"

OSC1
~

Co

-3-8--------~IDI~

COSC2

_________3_9

(c) Equivalent Crystal Circuit

(b) Crystal Oscillator Connections

U neon nected

-<

L - -_ _ _

(d) RC Oscillator Connections

External Clock

(e) External Clock Source Connections

Figure 2-1. Oscillator Connections

3-519

MC68HC05C4

2.1.6.2 RC. If the RC oscillator option is selected, then a resistor is connected to the oscillator pins
as shown in Figure 2-1 (d). The relationship between Rand fosc is shown in Figure 2-2.

TBD

I

Figure 2-2. Typical Frequency vs Resistance For
RC Oscillator Option Only
2.1.6.3 EXTERNAL CLOCK. An external clock should be applied to the OSCl input with the OSC2
input not connected, as shown in Figure 2-1 (e). An external clock may be used with either the RC or
crystal oscillator option. The toxov or tlLCH specifications do not apply when using an external
clock input. The equivalent specification of the external clock source should be used in lieu of
toxov or tILCH·
2.1.7 PAO-PA7
These eight I/O lines comprise port A. The state of any pin is software programmable and all port A
lines are configured as input during power-on or reset. Refer to INPUT/OUTPUT PROGRAMMING
paragraph below for a detailed description of I/O programming.
2.1.8 PBO-PB7
These eight lines comprise port B. The state of any pin is software programmable and all port B lines
are configured as input during power-on or reset. Refer to INPUT/OUTPUT PROGRAMMING
paragraph below for a detailed description of I/O programming.
2.1.9 PCO-PC7
These eight lines comprise port C. The state of any pin is software programmable and all port Clines
are configured as input during power-on or reset. Refer to INPUT/OUTPUT PROGRAMMING
paragraph below for a detailed description of I/O programming.
2.1.10 PDO-PD5, PD7
These seven lines comprise port D, a fixed input port that is enabled during power-on. All enabled
special functions (SPI and SCI) affect the pins on this port. Four of these lines, PD2/MISO,
PD3/MOSI, PD4/SCK, and PD5/SS, are used in the serial peripheral interface (SPI) discussed in

3-520

MC68HC05C4

Section 6. Two of these lines, PDO/ RDI and PD1 /TDO, are used in the serial communications interface (SCI) discussed in Section 5. Refer to 2.2 INPUT/OUTPUT PROGRAMMING for a detailed
description of I/O programming.
2.2 INPUT/OUTPUT PROGRAMMING
2.2.1 Parallel Ports
Ports A, B, and C may be programmed as an input or an output under software control. The direction of the pins is determined by the state of the corresponding bit in the port data direction register
(DDRl. Each 8-bit port has an associated 8-bit data direction register. Any port A, port B, or port C
pin is configured as an output if its corresponding DDR bit is set to a logic one. A pin is configured
as an input if its corresponding DDR bit is cleared to a logic zero. At power-on or reset, all DDRs are
cleared, which configure all port A, B, and C pins as inputs. The data direction registers are capable
of being written to or read by the processor. Refer to Figure 2-3 and Table 2-1. During the programmed output state, a read of the data register actually reads the value of the output data latch and
not the I/O pin.

1/0
Pin

Internal
MC68HC05C4
Connections

(a)

4

Typical Port
Data Direction
Register

Typical Port
Register

Pin

P-7

P-6

P-5

P-4

P-3

P-2

P-1

(b)

Figure 2-3. Typical Parallel Port I/O Circuitry

3-521

P-O

I

MC68HC05C4

Table 2-1. I/O Pin Functions
1/0 Pin Function

R/W*
0
0

DDR
0

1

0

The state of the 1/0 pin is read

1

1

The 1/0 pin is in an output mode. The output data latch is read.

* R/W

1

The 1/0 pin is in input mode. Data is written into the output data latch.
Data is written into the output data latch and output to the 1/0 pin.

IS an Internal signal.

2.2.2 Fixed Port

I

Port D is a 7-bit fixed input port (PDO-PD5, PD7) that continually monitors the external pins
whenever the SPI or SCI systems are disabled. During power-on reset or external reset all seven bits
become valid input ports because all special function output drivers are disabled. For example, with
the serial communications interface (SCI) system enabled, (RE= TE= 1) PD~ and PDl inputs will
read zero. With the serial peripheral interface (SPI) system disabled (SPE=O) PD2 through PD5 will
read the state of the pin at the time of the read operation. No data register is associated with the
port when it is used as an input.
2.2.3 Serial Port (SCI and SPI)

The serial communications interface (SCI) and serial peripheral interface (SPI) use the port D pins
for their functions. The SCI function requires two of the pins (PDO-PD1) for its receive data input
(RD!) and transmit data output (TDO) respectively, whereas the SPI function requires four of the
pins (PD2-PD5) for its serial data input/output (MISO), serial data output/input (MOS!), system
clock (SCK), and slave select (SS) respectively. Refer to SECTION 5 SERIAL COMMUNICATIONS
INTERFACE and SECTION 6 SERIAL PERIPHERAL INTERFACE for a more detailed discussion.
2.3 MEMORY

As shown in Figure 2-4, the MCU is capable of addressing 8192 bytes of memory and I/O registers
with its program counter. The MC68HC05C4 MCU has implemented 4601 bytes of these locations.
The first 256 bytes of memory (page zero) include: 25 bytes of I/O features such as data ports, the
port DDRs, timer, serial peripheral interface (SPI), and serial communication interface (SCI); 48
bytes of user ROM, and 176 bytes of RAM. The next 4096 bytes complete the user ROM. The selfcheck ROM (224 bytes) and self-check vectors (16 bytes) are contained in memory locations $1 FOO
through $1 FEF. The 16 highest address bytes contain the user defined reset and the interrupt vectors. Seven bytes of the lowest 32 memory locations are unused and the 176 bytes of user RAM include up to 64 bytes for the stack. Since most programs use only a small part of the allocated stack
locations for interrupts and/ or subroutine stacking purposes, the unused bytes are usable for program data storage.

3-522

s:

0
$0000

0000

0000
Ports
7 Bytes

I/O
32 Bytes
$oolF
$0020
User
ROM
48 Bytes
$004F
$0050

0031
0032

Unused
3 Bytes

.\

\

0079
0080

i

\

S~,k

cJ,

0255
0256
User
ROM
4096 Bytes

I\)

c.v

$lOFF
$1100

\

\

Timer
10 Bytes

\
\

\

Unused
3584 Bytes

$1 FFF

$03

c.n

Port A Data Direction Register

$04

Port B Data Direction Register

$05

Port C Data D"irection Register

$06

Unused

$07
$08

Unused

$09

Serial Peripheral Control Register

I $OA

Serial Peripheral Status Register

I SOB

SOD

Serial Communications Control Register 1

$OE

\

I

I

$12
$13
I

I

$16

I $17
I

Alternate Counter Low Register

$lA

I

Unused

\

I

Unused

\
\

8191

Figure 2-4. Address Map

..

-

$lC

$1 E

Unused
-

$18

$10

Unused
L

$18
$19

Alternate Counter High Register

\

$14
$15

Output Compare Low Register
Counter High Register

\

$11

Timer Status Register

Counter Low Register

\

$OF

I $10

Output Compare High Register

\

256 Bytes

I

Timer Control Register

Input Capture Low Register

\

I SOC

Serial Communications Baud Rate Register

\

8175
8176

Unused

Input Capture High Register

\

1-------

User
Vectors
16 Bytes

Port D Fixed Input Register

0031
032

\
7935
7936

Self-Check
Vectors
$1 FEF
$1 FFO

0

Serial Communications Data Register

Unused
4 Bytes

\

Self Check

$lFDF
$1 FEO

$02

Serial Communications Status Register

\
4351
4352

$1 EFF
$1 FOO

$01

Serial Communications Control Register 2

\

:I:

Port B Data Register

Serial Peripheral Data 1/0 Register

\

64 Bytes

$ooFF
$0100

Serial
Communications
Interface
5 Bytes

en
Q)

Port C Data Register

\

$OOBF f - - - - - - 0191
0192
$OOCO

c.v

$00

Serial Peripheral
Interface
3 Bytes

\
RAM
176 Bytes

Port A Data Register

$1 F
i

0

0

~

MC68HC05C4

2.4 CPU REGISTERS

The MC68HC05C4 CPU contains five registers, as shown in the programming model of Figure 2-5.
The interrupt stacking order is shown in Figure 2-6.

0

7

I

I

A

Accumulator

Index Register

X

12
PC

I

Program Counter

12
7
101010101011111

0

I

SP

Stack Pointer

CC

~
I

N

Z

C

Condition Code Register
Carry/Borrow
Zero
Negative
Interrupt Mask
Half Carry

Figure 2-5. Programming Model

Stack

I ncreasing Memory
Addresses

1~
U

R
N

11111 1 Condition Code Register
Accumulator
Index Register

o I 0I 0 1

PCH
PCl

I

n

Decreasing Memory
Addresses

P

T

Unstack

NOTE: Since the Stack Pointer decrements during pushes, the PCl is
stacked first, followed by PCH, etc. Pulling from the stack is
in the reverse order.

Figure 2-6. Stacking Order

3-524

MC68HC05C4

2.4.1 Accumulator (A)

The accumulator is an 8-bit general purpose register used to hold operands, results of the arithmetic
calculations, and data manipulations.
2.4.2 Index Register (X)

The X register is an 8-bit register which is used during the indexed modes of addressing. It provides
an 8-bit value which is used to create an effective address. The index register is also used for data
manipulations with the read-modify-write type of instructions and as a temporary storage register
when not performing addressing operations.
2.4.3 Program Counter (PC)

The program counter is a 13-bit register that contains the address of the next instruction to be
executed by the processor.
2.4.4 Stack Pointer (SP)

The stack pointer is a 13-bit register containing the address of the next free locations on the pushdown/pop-up stack. When accessing memory, the seven most significant bits are permanently
configured to 0000011. These seven bits are appended to the six least significant register bits to produce an address within the range of $OOFF to $OOCO. The stack area of RAM is used to store the
return address on subroutine calls and the machine state during interrupts. During external or
power-on reset, and during a reset stack pointer (RSP) instruction, the stack pointer is set to its upper limit ($OOFF). Nested interrupt and/ or subroutines may use up to 64 (decimal) locations. When
the 64 locations are exceeded, the stack pointer wraps around and points to its upper limit ($OOFF),
thus, losing the previously stored information. A subroutine call occupies two RAM bytes on the
stack, while an interrupt uses five RAM bytes.
2.4.5 Condition Code Register (CC)

The condition code register is a 5-bit register which indicates the results of the instruction just
executed as well as the state of the processor. These bits can be individually tested by a program
and specified action taken as a result of their state. Each bit is explained in the following
paragraphs.
2.4.5.1 HALF CARRY BIT (H). The H bit is set to a one when a carry occurs between bits 3 and 4 of
the ALU during an ADD or ADC instruction. The H bit is useful in binary coded decimal
su brouti nes.
2.4.5.2 INTERRUPT MASK BIT (I). When the I bit is set, all interrupts are disabled. Clearing this bit
enables the interrupts. If an external interrupt occurs while the I bit is set, the interrupt is latched
and is processed after the I bit is next cleared; therefore, no interrupts are lost because of the I bit
being set. An internal interrupt can be lost if it is cleared while the I bit is set (refer to SECTION 4
PROGRAMMABLE TIMER, SECTION 5 SERIAL COMMUNICATIONS INTERFACE, and SECTION
6 SERIAL PERIPHERAL INTERFACE for more information).

3-525

II

MC68HC05C4

2.4.5.3 NEGATIVE (N). When set, this bit indicates that the result of the last arithmetic, logical, or
data manipulation is negative (bit 7 in the result is a logic one).
2.4.5.4 ZERO (Z). When set, this bit indicates that the result of the last arithmetic, logical, or data
manipulation is zero.
2.4.5.5 CARRY/BORROW (C). Indicates that a carry or borrow out of the arithmetic logic unit
(ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and
branch instructions, shifts, and rotates.
2.5 SELF-CHECK

I

The self-check capability of the MC68HC05C4 MCU provides an internal check to determine if the
device is functional. Self-check is performed using the circuit shown in the schematic diagram of
Figure 2-7. As shown in the diagram, port C pins PCO-PC3 are monitored (light emitting diodes are
shown but other devices could be used) for the self-check results. The self-check mode is entered
by applying a 9 Vdc input (through a 4.7 kilohm resistor) to the IRQ pin (2) and 5 Vdc input (through
a 4.7 kilohm resistor) to the TCAP pin (37) and then depressing the reset switch to execute a reset.
After reset, the following seven tests are performed automatically:
I/O - Functionally exercises ports A, B, andC
RAM - Counter test for each RAM byte
Timer - Tracks counter register and checks OCF flag
SCI - Transmission Test; checks for RDRF, TDRE, TC, and FE flags
ROM - Exclusive OR with odd ones parity result
SPI - Transmission test with check for SPIF, WCOl, and MODF flags
INTERRUPTS - Tests external, timer, SCI, and SPI interrupts.
Self-check results (using the LEDs as monitors) are shown in Table 2-2. The following subroutines
are available to user programs and do not require any external hardware.
2.6 TIMER TEST SUBROUTINE
This subroutine returns with the Z bit cleared if any error is detected; otherwise, the Z bit is set.
This subroutine is called at location $1 FOE. The output compare register is first set to the current
timer state. Because the timer is free running and has only a divide-by-four prescaler, each timer
count cannot be tested. The test reads the timer once every 10 counts (40 cycles) and checks for
correct counting. The test tracks the counter until the timer wraps around, triggering the output
compare-llag in the timer status register. RAM locations $0050 and $0051 are overwritten. Upon
return to the user's program, X=40. If the test passed, A=O.
2.7 ROM CHECKSUM SUBROUTINE
This subroutine returns with the Z bit cleared if any error is detected; otherwise, the Z bit is set.
This subroutine is called at location $1 F93 with RAM location $0053 equal to $01 and A= o. A short
routine is set up and executed in RAM to compute a checksum of the entire ROM pattern. Upon
return to the user's program, X=O. If the test passed, A=O. RAM locations $0050 through $0053
are overwritten.

3-526

MC68HC05C4

RESET
+9 V

4.7k~
10 k

1

10 k

y2N3904
3

-

+5V
10 k

RESET
IRQ
VDD

NC

OSCl

-=

37

40

+5V

39

TCAP

r--

5

-

6
7
8

-

~
10

11

PA7

D

PA6
PA5

TCMP
PA4

35

r-33

PD4/SCK
PA2

32

PD3/MOSI
PAl
PD2/MISO
PAO

-

14

10 k

~

15

-

16

----.lZ.
18
19

PBO

PCO

PBl

PCl

PB2

PC2

PB3

PC3

PB4

PC4

PB5

PC5

PB6

PC6

PB7

PC7

4.7 K

~

2N3904

10 k

30

I

..

~

28
27

~,

..

26
25
24

-23
22
21

VSS

.l.. 20
NOTE: The RC Oscillator Option may also be used in this circuit.

Figure 2-7. Self-Check Circuit Schematic Diagram

Table 2-2. Self-Check Results
PC3

PC2

PCl

pca

1

0

0

1

1

0

1

0

Bad RAM

1

0

1

1

Bad Timer

1

1

0

0

Bad SCI

1

1

0

1

Bad ROM

Remarks
Bad 1/0

1

1

1

0

Bad SPI

1

1

1

1

Bad Interrupts or IRQ Request

Flashing
Ail Others

o Indicates

Good Device
Bad Device, Bad Port C, etc

LED on; 1 Indicates LED

II

1M

29

PDO/RDI
13
r--

+5V

~

31

PD1ITDO
12

I~F

34

PD5/SS

PA3

(See Note)

36

PD7

4 MHz

I-

38

OSC2

:qF

I

10M
MC68HC05C4

~

:1'9-

IS

3-527

off

-=
4.7 k

~

+5V
4.7 k

.. 4.7 k

'!,...

4.7 k

MC68HC05C4

SECTION 3
RESETS, INTERRUPTS, AND LOW POWER MODES
3.1 RESETS

The MC68HC05C4 has two reset modes: an active low external reset pin (RESET) and a power-on
reset function; refer to Figure 3-1.
3.1.1 RESET Pin

I

The RESET input pin is used to reset the MCU to provide an orderly software startup procedure.
When using the external reset mode, the RESET pin must stay low for a minimum of one and one
half tcyc. The RESET pin contains an internal Schmitt Trigger as part of its input to improve noise
immunity.
3.1.2 Power-On Reset

The power-on reset occurs when a positive transition is detected on VDD. The power-on reset is
used strictly for power turn-on conditions and should not be used to detect any drops in the power
supply voltage. There is no provision for a power-down reset. The power-on circuitry provides for a
4064 tcyc delay from the time that the oscillator becomes active. If the external RESET pin is low at
the end of the 4064 tcyc time out, the processor remains in the reset condition until RESET goes
high.
Table 3-1 shows the actions of the two resets on internal circuits, but not necessarily in order of
occurrence (X indicates that the condition occurs for the particular reset).
3.2 INTERRUPTS

Systems often require that normal processing be interrupted so that some external event may be
serviced. The MC68HC05C4 may be interrupted by one of five different methods: either one of four
maskable hardware interrupts (IRQ, SPI, SCI, or Timer) and one non-maskable software interrupt
(SWI). Interrupts such as Timer, SPI, and SCI have several flags which will cause the interrupt.
Generally, interrupt flags are located in read-only status registers, whereas their equivalent enable
bits are located in associated control registers. The interrupt flags and enable bits are never contained in the same register. If the enable bit is a logic zero it blocks the interrupt from occurring but
does not inhibit the flag from being set. Reset clears all enable bits to preclude interrupts during the
reset procedure.
.
The general sequence for clearing an interrupt is a software sequence of first accessing the status
register while the interrupt flag is set, followed by a read or write of an associated register. When
any of these interrupts occur, and if the enable bit is a logic one, normal processing is suspended at
the end of the current instruction execution. Interrupts cause the processor registers to be saved on

3-528

i:

o

0)
Q)

::I:

(J1

I

I~---------------------------------------

VDD

%
I

I

~,..,..l.,v4Z--'-Z-r-rZZ-'-Zr-rO""""""Z"""""""jZ-r-7jj-r-j-r-7"jj-'-j-r-rjZ~j,...-rjZ--r-7jZ-r-j-r-70-r-Z"'-'jj-r-Z"""ZZ"--;Zr-r-jj""l'"'7Z"""'ZZ""'O-'-ZlIjZ-r-Z"07lZ--rjj17jj-'-ZIIZZ-r-Z'f//j
OSCl * *

I tOXOV I 4064
I
III(
"III(

I
I
I

I

I

I
I
-I

tcyc

iI

tcyc

IJ

Internal
Processor
Clock*

U>

cit

I\)

<0

Internal
Address
Bus*

Internal
Data
Bus*

~tRL-1

RESET

oo
o

1

***

¥

* Internal timing signal and bus information not available externally.
* * OSCl line is not meant to represent frequency. It is only used to represent time.
* * *The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence

Figure 3-1. Power-On Reset and RESET

~

MC68HC05C4

Table 3-1. Reset Action on Internal Circuit

Condition

I

RESET
Pin

Power-On
Reset

X
X
X
X

X
X
X
X

X
X
X
X
X*
X
X
X

X
X
X
X
X
X
X
X

X

X

X
X
X
X

X
X
X
X

Timer Prescaler reset to zero state
Timer counter configured to $FFFC
Timer output compare (TCMPI bit reset to zero
All timer interrupt enable bits cleared (lCIE, OCIE, and TOIEI to disable timer interrupts.
The OlVl timer bit is also cleared by reset.
All data direction registers cleared to zero (inputl
Configure stack pointer to $OOFF
Force internal address bus to restart vector 1$1 FFE-$l FFFI
Set I bit in condition code register to a logic one
Clear STOP latch
Clear external interrupt latch
Clear WAIT latch
Disable SCI Iserial control bits TE=O and RE=OI. Other SCI bits cleared by reset include: TIE, TCIE,
RIE, ILlE, RWU, SBK, RDRF, IDLE, OR, NF, and FE.
Disable SPI Iserial output enable control bit SPE = 01 Other SPI bits cleared by reset include SPIE,
MSTR, SPIF, WCOl, and MODF.
Set serial status bits TDRE and TC
Clear all serial interrupt enable bits ISPIE, TIE, and TCIEI
Place SPI system in slave mode IMSTR=OI
Clear SCI prescaler rate control bits SCPO-SCP1
*Indlcates that timeout stili occurs.

the stack (see Figure 2-6) and the interrupt mask (I bit) set to prevent additional interrupts. The
appropriate interrupt vector then points to the starting address of the interrupt service routine (refer
to Figure 2-4 for vector location). Upon completion of the interrupt service routine, the RTI instruction (which is normally a part of the service routine) causes the register contents to be recovered
from the stack followed by a return to normal processing. The stack order is shown in Figure 2-6.
NOTE
The interrupt mask bit (I bit) will be cleared if and only if the corresponding bit stored in
the stack is zero.

A discussion of interrupts, plus a table listing vector addresses for all interrupts including reset, in
the MC68HC05C4 is provided in Table 3-2.
Table 3-2. Vector Address for Interrupts and Reset

Register
N/A
N/A
N/A
Timer Status

SCI Status

SPI Status

Flag
Name

Interrupts

N/A
N/A
N/A
ICF
OCF
TOF
TDRE
TC
RDRF
IDLE
OR
SPIF
MODF

Reset
Software
External Interrupt
Input Capture
Output Compare
Timer Overflow
Transmit Buffer Empty
Transmit Complete
Receiver Buffer Full
Idle Line Detect
Overrun
Transfer Complete
Mode Fault

3-530

CPU
Interrupt

Vector
Address

RESET
SWI
IRQ
TIMER

$1 FFE-$l FFF
$1 FFC-$l FFD
$lFFA-$lFFB
$1 FFS-$l FF9

SCI

$1 FF6-$1 FF7

SPI

$1 FF4-$1 FF5

MC68HC05C4

3.2.1 Hardware Controlled Interrupt Sequence
The following three functions (RESET, STOP, and WAIT) are not in the strictest sense an interrupt;
however, they are acted upon in a similar manner. Flowcharts for hardware interrupts are shown in
Figure 3-2, and for STOP and WAIT are provided in Figure 3-3. A discussion is provided below.
(a) -

(b)
(c)

A low input on the RESET input pin causes the program to vector to its starting address
which is specified by the contents of memory locations $1 FFE and $1 FFF. The I bit in the
condition code register is also set. Much of the MCU is configured to a known state during this type of reset as previously described in RESETS paragraph 3.1.
STOP - The STOP instruction causes the oscillator to be turned off and the processor
to "sleep" until an external interrupt (IRQ) or reset occurs.
WAIT - The WAIT instruction causes all processor clocks to stop, but leaves the
Timer, SCI, and SPI clocks running. This "rest" state of the processor can be cleared by
reset, an external interrupt (rR"ll) , Timer interrupt, SPI interrupt, or SCI interrupt. There
are no special wait vectors for these individual interrupts.

3.2.2 Software Interrupt (SWI)
The software interrupt is an executable instruction. The action of the SWI instruction is similar to
the hardware interrupts. The SWI is executed regardless of the state of the interrupt mask (I bit) in
the condition code register. The interrupt service routine address is specified by the contents of
memory location $1 FFC and $1 FFD.
3.2.3 External Interrupt
If the interrupt mask (I bit) of the condition code register has been cleared and the external interrupt
pin (IRQ) has gone low, then the external interrupt is recognized. When the interrupt is recognized,
the current state of the CPU is pushed onto the stack and the I bit is set. This masks further interrupts until the present one is serviced. The interrupt service routine address is specified by the contents of memory location $1 FFA and $1 FFB. Either a level-sensitive and negative edge-sensitive
trigger, or a negative edge-sensitive only trigger are available as a mask option. Figure 3-4 shows
both a functional and mode timing diagram for the interrupt line. The timing diagram shows two different treatments of the interrupt line (I RQ) to the processor. The first method shows single pulses
on the interrupt line spaced far enough apart to be serviced. The minimum time between pulses is a
function of the number of cycles required to execute the interrupt service routine plus 21 cycles.
Once a pulse occurs, the next pulse should not occur until the MCU software has exited the routine
(an RTI occurs). The second configuration shows several interrupt lines "wire-ORed" to form the
interrupts at the processor. Thus, if after servicing one interrupt the interrupt line remains low, then
the next interrupt is recognized.
NOTE
The internal interrupt latch is cleared in the first part of the service routine; therefore, one
(and only one) external interrupt pulse could be latched during tl LI L and serviced as soon
as the I bit is cleared.

3-531

•

MC68HC05C4

From
RESET

y

Clear IRQ
Request
Latch

I

Load PC From:
IRQ: $lFFA-$lFFB
Timer: $lFF8-$lFF9
SCI: $1 FF6-$1 FF7
SPI: $1 FF4-$1 FF5

Complete
Interrupt
Routine
and Execute
RTI

Figure 3-2. Hardware Interrupt Flowchart

3-532

MC68HCOSC4

Stop

Wait

Stop Oscillator
And All Clocks

Oscillator Active
Timer, SCI, And SPI
Clocks Active
Processor Clocks Stopped

Clear I Bit

I
Yes

Turn On Oscillator

(1) Fetch Reset Vector or

(21 Service Interrupt
a. Stack
b. Set I Bit
c. Vector to Interrupt
Routine

(1) Fetch Reset Vector or
(2) Service Interrupt
a. Stack
b. Set I Bit
c. Vector to Interrupt
Routine

Figure 3-3. STOP/WAIT Flowcharts

3-533

MC68HC05C4

Level-Sensitive Trigger
Mask Option
VDD
D

External
Interrupt
Request

01------/

Interrupt Pin ------.....~--_<~/ C
I Bit(CCI

Power-On Reset
External Reset

I

External Interru pt
Being Serviced I Read of Vectorsl
(a) Interrupt Function Diagram

U

IRO~tILIH

I.

Edge-Sensitive Trigger Condition
The minimum pulse width (tILiHI is either
125 ns (VDD=5 VI or 250 ns (VDD=3 VI
The period tlLlL should not be less than
the number of tcyc cycles it takes to execute the interrupt service routine plus 21
teyc cycles.

tILlL-----~·~1

Level-Sensitive Trigger Condition
If after servicing an interrupt the IRO remains low, then the next interrupt is
recognized.

IRO:----r--==tILIH~
IROn

~

_ _~I

Normally
Used with
Wire-ORed
Connection

r

I R O - - ,I~__________________________~
IMCUI

(b) Interrupt Mode Diagram

Figure 3-4. External Interrupt

3-534

MC68HC05C4

3.2.4 Timer Interrupt

There are three different timer interrupt flags that will cause a timer interrupt whenever they are set
and enabled. These three interrupt flags are found in the three most significant bits of the timer
status register (TSR, location $13) and all three will vector to the same interrupt service routine
($1 FF8-$1 FF9).
All interrupt flags have corresponding enable bits (ICIE, OCIE, and TOlE) in the timer control
register nCR, location $12). Reset clears all enable bits, thus preventing an interrupt from occurring
during the reset time period. The actual processor interrupt is generated only if the I bit in the condition code register is also cleared. When the interrupt is recognized, the current machine state is
pushed onto the stack and I bit is set. This masks further interrupts until the present one is serviced.
The interrupt service routine address is specified by the contents of memory location $1 FF8 and
$1 FF9. The general sequence for clearing an interrupt is a software sequence of accessing the
status register while the flag is set, followed by a read or write of an associated register. Refer to
SECTION 4 PROGRAMMABLE TIMER for additional information about the timer circuitry.
3.2.5 Serial Communications Interface (SCI) Interrupts

An interrupt in the serial communications interface (SCI) occurs when one of the interrupt flag bits
in the serial communications status register is set, provided the I bit in the condition code register is
clear and the enable bit in the serial communications control register 2 (location $OF) is enabled.
When the interrupt is recognized, the current state of the machine is pushed onto the stack and the
I bit in the condition code register is set. This masks further interrupts until the present one is serviced. The SCI interrupt causes the program counter to vector to memory location $1 FF6 and $1 FF7
which contains the starting address of the interrupt service routine. Software in the serial interrupt
service routine must determine the priority and cause of the SCI interrupt by examining the interrupt
flags and the status bits located in the serial communications status register (location $10). The
general sequence for clearing an interrupt is a software sequence of accessing the serial communications status register while the flag is set followed by a read or write of an associated register.
Refer to SECTION 5 SERIAL COMMUNICATIONS INTERFACE for a description of the SCI system
and its interrupts.
3.2.6 Serial Peripheral Interface (SPI) Interrupts

An interrupt in the serial peripheral interface (SPI) occurs when one of the interrupt flag bits in the
serial peripheral status register (location SOB) is set, provided the I bit in the condition code register
is clear and the enable bit in the serial peripheral control register (location $OA) is enabled. When the
interrupt is recognized, the current state of the machine is pushed onto the stack and the I bit in the
condition code register is set. This masks further interrupts until the present one is serviced. The
SPI interrupt causes the program counter to vector to memory location $1 FF4 and $1 FF5 which
contains the starting address of the interrupt service routine. Software in the serial peripheral interrupt service routine must determine the priority and cause of the SPI interrupt by examining the
interrupt flag bits located in the SPI status register. The general sequence for clearing an interrupt is
a software sequence of accessing the status register while the flag is set, followed by a read or write
of an associated register. Refer to SECTION 6 SERIAL PERIPHERAL INTERFACE for a description
of the SPI system and its interrupts.

3-535

I

MC68HC05C4

3.3 LOW POWER MODES
3.3.1 STOP Instruction
The STOP instruction places the MC68HC05C4 in its lowest power consumption mode. In the
STOP mode the internal oscillator is turned off, causing all internal processing to be halted; refer to
Figure 3-3. During the STOP mode, the I bit in the condition code register is cleared to enable external interrupts. All other registers and memory remain unaltered and all input/ output lines remain unchanged. This continues until an external interrupt (IRQ) or reset is sensed at which time the internal oscillator is turned on. The external interrupt or reset causes the program counter to vector to
memory location $1 FFA and $1 FFB or $1 FFE and $1 FFF which contains the starting address of the
interrupt or reset service routine respectively.

I

3.3.2 WAIT Instruction
The WAIT instruction places the MC68HC05C4 in a low power consumption mode, but the WAIT
mode consumes somewhat more power than the STOP mode. In the WAIT mode, the internal
clock remains active, and all CPU processing is stopped; however, the programmable timer, serial
peripheral interface, and serial communications interface systems remain active. Refer to Figure
3-3. During the WAIT mode, the I bit in the condition code register is cleared to enable all interrupts.
All other registers and memory remain unaltered and all parallel input/output lines remain unchanged. This continues until any interrupt or reset is sensed. At this time the program counter vectors to the memory location ($1 FF4 through $1 FFF) which contains the starting address of the interrupt or reset service routine.

3-536

MC68HC05C4

SECTION 4
PROGRAMMABLE TIMER
4.1 INTRODUCTION

The programmable timer, which is preceded by a fixed divide-by-four prescaler, can be used for
many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from several microseconds to many seconds. A block diagram
of the timer is shown in Figure 4-1 and timing diagrams are shown in Figures 4-2 through 4-5.
Because the timer has a 16-bit architecture, each specific functional segment (capability) is
represented by two registers. These registers contain the high and low byte of that functional segment. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is
also accessed.
NOTE
The I bit in the condition code register should be set while manipulating both the high and
low byte register of a specific timer function to ensure that an interrupt does not occur.
This prevents interrupts from occurring between the time that the high and low bytes are
accessed.

The programmable timer capabilities are provided by using the following ten addressable 8-bit
registers (note the high and low represent the significance of the byte). A description of each
register is provided below.
Timer Control Register nCR) location $12,
Timer Status Register (TSR) location $13,
Input Capture High Register location $14,
Input Capture Low Register location $15,
Output Compare High Register location $16,
Output Compare Low Register location $17,
Counter High Register location $18,
Counter Low Register location $19,
Alternate Counter High Register location $lA, and
Alternate Counter Low Register location $1 B.

3-537

I

MC68HC05C4

1

l

MC68HC05C4 Internal Bus
Internal
Processor
Clock

@
Buffer

+4
High
Byte

Low
Byte
W

$16\
$17

I

V-Low
Byte

High
Byte

Output \
Compare
Register

~

16-Bit Free
Running
Counter
Counter
Alternate
Register

High
Byte

$18

Low
Byte
Input
Capture
Register

$19

\ $14
$15

$lA
$1 B

W

I

Output
Compare
Circuit

I

Overflow
Detect
Circuit

Edge
Detect
Circuit

r--QI--

D

Timer
Status
Reg.

I

+
ICF

OCF

TOF

I

Output
Level
Reg.

$13

ICIE I OCIE

TOlE IIEDG

Interrupt
Circuit

I

OLVL

C

RESET

I C~:;OI
$12

J

I

I

Timer

~CLK

Output ~dge
Input
Level
(TeMP (TCAP
Pin 35) Pin 37)

I

Figure 4-1. Programmable Timer Block Diagram

3-538

:s::

oen
CO

J:

o
o

(J1

o

~

Internal
Processor
Clock
(Internal
Resetl

TOO

_ _ _ _ _~I
I \

I

TOl

v.>

cJ,

v.>

Tl0

CO

I

I

I

I

'U.......II~I~I~.......I~I-+

.fl1lJi1J1
I

Internal
Timer
Clocks

IIIIII

I

n

I

_~I~n

Counter
(16-Bitl
RESET
(External
or End of PORI

n

n___

_______H I n n
n
n
fL
I

T11

n'---__

$F~FC

~----

I

-------r - -

$FFFD

K

!1/11/

NOTE: The Counter Register and Timer Control Register are the only ones affected by RESET.

Figure 4-2. Timer State Timing Diagram For Reset

$FFFE

X,,____
$FFFF

MC68HCOSC4

Internal
Processor
Clock
TOO

Internal
Timer
Clocks

TOl

Tl0

Tll

______ ______ ______ n
r
Jll-o-__n____n_____n
___n
n
__n__----tn___ n
rL
~n~

~n~

~_ _~n..._..

I

I

Counter - - : : : : : - \ /
(16-Bitl ~_ _ _ _ _
$F_F_E_C_ _ _J

Input
Edge

X~

(SeeNot~~'3

\ \

_ y

Input
Capture
Register

$m?

X

~~:~_ _$_F_F_ED_ _ _. - J

VlIVIIYJ7IV111

Internal
Capture
Latch

Input
Capture
Flag

~

$FFEE

X

'\._ _ _ _ _ _ _ __ _

$FFEF

i

:

rY" \'"--______
X
/

$FFED

NOTE: If the input edge occurs in the shaded area from one timer state TlO to the other timer state Tl0 the input capture flag is set during the next state Tll

Figure 4-3. Timer State Timing Diagram For Input Capture

3-540

MC68HC05C4

Internal
Processor
Clock
TOO

Internal
Timer
Clocks

TOl

Tl0

Tll

Counter
(16-Bitl

________~rl~______~n
~~
-,rl~________________~n

n

______________

-11~

________n

n

r
n

____~rl~______~n
n
rL
-:;;;:v
X~______~x_________~X
~_ _ _ _$_F_F_E_C_ _ _--J

$FFED

$FFEE

$FFEF

(Notell~

Compare
Register
Compare
Register
Latch

X

CPU Writes $FFED

(Note21~

Output Compare
Flag (OCFI and
TCMP (Pin 351

NOTES:

$FFED

\'-----

(Note31~

The CPU write to the compare register may take place at any time, but a compare only occurs at timer state TOl Thus, a 4cycle difference may exist between the write to the compare register and the actual compare.
2. Internal compare takes place during timer state T01.
3. OCF is set at the timer state Tll which follows the comparison match ($FFED in this examplel

Figure 4-4. Timer State Timing Diagram For Output Compare

3-541

I

MC68HC05C4

Internal
Processor
Clock

TOO

_____n_____n""""-_______n____

TOl

Jl~

Internal
Timer
Clocks

T11

I

Counter
(16-Bit)
Timer
Overflow
Flag (TOF)

r

-----.J

____n______n_______

n~

__

____n______n_____n____rL
--;;;;;;'V

X

~_ _ _ _$_F_F_FF_ _ ___'

X

X

_____
$O_O_OO_ _ _.-J '-_ _ _ _$_0_0_01_____

$0002

----~/

NOTE: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000) It is cleared by a read of the timer status register
during the internal processor clock high time followed by a read of the counter low register.

Figure 4-5. Timer State Diagram For Timer Overflow

3-542

MC68HCOSC4

4.2 COUNTER

The key element in the programmable timer is a 16-bit free running counter, or counter register,
preceded by a prescaler which divides the internal processor clock by four. The prescaler gives the
timer a resolution of 2.0 microseconds if the internal processor clock is 2.0 MHz. The counter is
clocked to increasing values during the low portion of the internal processor clock. Software can
read the counter at any time without affecting its value.
The double byte free running counter can be read from either of two locations $18-$19 (called
counter register at this location), or $lA-$l B (counter alternate register at this location). A read sequence containing only a read of the least significant byte of the free running counter ($19,$1 B) will
receive the count value at the time of the read. If a read of the free running counter or counter alternate register first addresses the most significant byte ($18,$lA) it causes the least significant byte
($19,$1 B) to be transferred to a buffer. This buffer value remains fixed after the first most significant
byte "read" even if the user reads the most significant byte several times. This buffer is accessed
when reading the free running counter or counter alternate register least significant byte ($19 or
$1 B), and thus completes a read sequence of the total counter valUe. Note that in reading either the
free running counter or counter alternate register, if the most significant byte is read, the least
significant byte must also be read in order to complete the sequence.
The free running counter is configured to $FFFC during reset and is always a read-only register.
During a power-on-reset (POR), the counter is also configured to $FFFC and begins running after
the oscillator startup delay. Because the free running counter is 16 bits preceded by a fixed divideby-four prescaler, the value in the free running counter repeats every 262,144 M PU internal processor clock cycles. When the counter rolls over from $FFFF to $0000, the timer overflow flag (TOF)
bit is set. An interrupt can also be enabled when counter rollover occurs by setting its interrupt
enable bit (TOlE).
4.3 OUTPUT COMPARE REGISTER

The output compare register is a 16-bit register, which is made up of two 8-bit registers at locations
$16 (most significant byte) and $17 (least significant byte). The output compare register can be used
for several purposes such as, controlling an output waveform or indicating when a period of time
has elapsed. The output compare register is unique in that all bits are readable and writable and are
not altered by the timer hardware. Reset does not affect the contents of this register and if the compare function is not utilized, the two bytes of the output compare register can be used as storage
locations.
The contents of the output compare register are compared with the contents of the free running
counter once during every four internal processor clocks. If a match is found, the corresponding
output compare flag (OCF) bit is set and the corresponding output level (OLVU bit is clocked (by
the output compare circuit pulse) to an output level register. The values in the output compare
register and the output level bit should be changed after each successful comparison in order to
control an output waveform or establish a new elapsed timeout. An interrupt can also accompany a
successful output compare provided the corresponding interrupt enable bit, OCI E, is set.
After a processor write cycle to the output compare register containing the most significant byte
($16), the output compare function is inhibited until the least significant byte ($17) is also written.
The user must write both bytes (locations) if the most significant byte is written first. A write made

3-543

II

MC68HC05C4

only to the least significant byte ($17) will not inhibit the compare function. The free running
counter is updated every four internal processor clock cycles due to the internal prescaler. The
minimum time required to update the output compare register is a function of the software program
rather than the internal hardware.
A processor write may be made to either byte of the output compare register without affecting the
other byte. The output level (OLVU bit is clocked to the output level register regardless of whether
the output compare flag (OCF) is set or clear.

I

Because neither the output compare flag (OCF bit) or output compare register is affected by reset,
care must be exercised when initializing the output compare function with software. The following
procedure is recommended:
(1) Write the high byte of the output compare register to inhibit further compares until the low
byte is written.
(2) Read the timer status register to arm the OCF if it is already set.
(3) Write the output compare register low byte to enable the output compare function with the
flag clear.
The advantage of this procedure is to prevent the OCF bit from being set between the time it is read
and the write to the output compare register. A software example is shown below.
B7
B6
BF

16
13
17

STA
LDA
STX

OCMPHI
TSTAT
OCMPLD

INHIBIT OUTPUT COMPARE
ARM OCF BIT IF SET
READY FOR NEXT COMPARE

4.4 INPUT CAPTURE REGISTER

The two 8-bit registers which make up the 16-bit input capture register are read-only and are used to
latch the value of the free running counter after a defined transition is sensed by the corresponding
input capture edge detector. The level transition which triggers the counter transfer is defined by
the corresponding input edge bit (IEDG). Reset does not affect the contents of the input capture
register.
The result obtained by an input capture will be one more than the value of the free running counter
on the rising edge of the internal processor clock preceding the external transition (refer to timing
diagram shown in Figure 4-3). This delay is required for internal synchronization. Resolution is affected by the prescaler allowing the timer to only increment every four internal processor clock
cycles.
The free running counter contents are transferred to the input capture register on each proper signal
transition regardless of whether the input capture flag (ICF) is set or clear. The input capture
register always contains the free running counter value which corresponds to the most recent input
capture.
After a read of the most significant byte of the input capture register ($14), counter transfer is inhibited until the least significant byte ($15) of the input capture register is also read. This
characteristic forces the minimum pulse period attainable to be determined by the time used in the
capture software routine and its interaction with the main program. The free running counter increments every four internal processor clock cycles due to the prescaler.

3-544

MC68HC05C4

A read of the least significant byte ($15) of the input capture register does not inhibit the free
running counter transfer. Again, minimum pulse periods are ones which allow software to read the
least significant byte ($15) and perform needed operations. There is no conflict between the read of
the input capture register and the free running counter transfer since they occur on opposite edges
of the internal processor clock.
4.5 TIMER CONTROL REGISTER (TCR)

The timer control register (TCR, location $12) is an 8-bit read/write register which contains five control bits. Three of these bits control interrupts associated with each of the three flag bits found in
the timer status register (discussed below). The other two bits control: 1) which edge is significant
to the input capture edge detector (i.e., negative or positive), and 2) the next value to be clocked to
the output level register in response to a successful output compare. The timer control register and
the free running counter are the only sections of the timer affected by reset. The TCMP pin is forced
low during external reset and stays low until a valid compare changes it to a high. The timer control
register is illustrated below followed by a definition of each bit.
4
ICIE

oelE

TOlE

IEDG

OLVL

I

$12

87,ICIE

If the input capture interrupt enable (ICIE) bit is set, a timer interrupt is enabled
when the ICF status flag (in the timer status register) is set. If the ICI E bit is
clear, the interrupt is inhibited. The ICIE bit is cleared by reset.

86, OCIE

If the output compare interrupt enable (OCIE) bit is set, a timer interrupt is
enabled whenever the OCF status flag is set. If the OCIE bit is clear, the interrupt is inhibited. The OCIE bit is cleared by reset.

85, TOlE

If the timer overflow interrupt enable (TOlE) bit is set, a timer interrupt is
enabled whenever the TOF status flag (in the timer status register) is set. If the
TOlE bit is clear, the interrupt is inhibited. The TOlE bit is cleared by reset.

81,IEDG

The value of the input edge (I EDG) bit determines which level transition on pin
37 will trigger a free running counter transfer to the input capture register.
Reset does not affect the IEDG bit.
0= negative edge
1 = positive edge

80, OLVL

The value of the output level (OLVU bit is clocked into the output level register
by the next successful output compare and will appear at pin 35. This bit and
the output level register are cleared by reset.
0= low output
1 = high output

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II

MC68HC05C4

4.6 TIMER STATUS REGISTER (TSR)
The timer status register (TS R) is an 8-bit register of which the three most significant bits contain
read-only status information. These three bits indicate the following:
1. A proper transition has taken place at pin 37 with an accompanying transfer of the free running counter contents to the input capture register,
2. A match has been found between the free running counter and the output compare register,
and
3. A free running counter transition from $FFFF to $0000 has been sensed (timer overflow).
The timer status register is illustrated below followed by a definition of each bit. Refer to timing
diagrams shown in Figures 4-2,4-3, and 4-4 for timing relationship to the timer status register bits.
4

I

ICF

OCF

TOF

o

o

$13

B7,ICF

The input capture flag (ICF) is set when a proper edge has been sensed by the
input capture edge detector. It is cleared by a processor access of the timer
status register (with ICF set) followed by accessing the low byte ($15) of the input capture register. Reset does not affect the input compare flag.

B6,OCF

The output compare flag (OCF) is set when the output compare register contents matches the contents of the free running counter. The OCF is cleared by
accessing the timer status register (with OCF set) and then accessing the low
byte ($17) of the output compare register. Reset does not affect the output
compare flag.

85, TOF

The timer overflow flag (TOF) bit is set by a transition of the free running
counter from $FFFF to $0000. It is cleared by accessing the timer status register
(with TOF set) followed by an access of the free running counter least significant byte ($19). Reset does not affect the TOF bit.

Accessing the timer status register satisfies the first condition required to clear any status bits which
happen to be set during the access. The only remaining step is to provide an access of the register
which is associated with the status bit. Typically, this presents no problem for the input capture and
output compare functions.
A problem can occur when using the timer overflow function and reading the free running counter
at random times to measure an elapsed time. Without incorporating the proper precautions into
software, the timer overflow flag could unintentionally be cleared if: 1) the timer status register is
read or written when TOF is set, and 2) the least significant byte of the free running counter is read
but not for the purpose of servicing the flag. The counter alternate register at address $lA and $1 B
contains the same value as the free running counter (at address $18 and $19); therefore, this alternate register can be read at any time without affecting the timer overflow flag in the timer status
register.
During STOP and WAIT instructions, the programmable timer functions as follows: during the wait
mode, the timer continues to operate normally and may generate an interrupt to trigger the CPU out
of the wait state; during the stop mode, the timer holds at its current state, retaining all data, and
resumes operation from this point when an external interrupt is received.

3-546

MC68HC05C4

SECTION 5
SERIAL COMMUNICATIONS INTERFACE (SCI)
5.1 INTRODUCTION

A full-duplex asynchronous serial communications interface (SCI) is provided with a standard NRZ
format and a variety of baud rates. The SCI transmitter and receiver are functionally independent,
but use the same data format and bit rate. The serial data format is standard mark/ space (N RZ)
which provide one start bit, eight or nine data bits, and one stop bit. "Baud" and "bit rate" are used
synonymously in the following description.
5.1.1 SCI Two Wire System Features

• Standard NRZ (mark/space) format.
• Advanced error detection method includes noise detection for noise duration of up to 1/16 bit
time.
• Full-duplex operation (simultaneous transmit and receive).
• Software programmable for one of 32 different baud rates.
• Software selectable world length (eight or nine bit words).
• Separate transmitter and receiver enable bits.
• SCI may be interrupt driven.
• Four separate enable bits available for interrupt control.
5.1.2 SCI Receiver Features

• Receiver wake-up function (idle or address bit).
• Idle line detect.
• Framing error detect.
• Noise detect.
• Overrun detect.
• Receiver data register full flag.
5.1.3 SCI Transmitter Features

• Transmit data register empty flag.
• Transmit complete flag.
• Break send.
Any SCI two-wire system requires receive data in (RDD and transmit data out (TDO)'

3-547

I

MC68HC05C4

5.2 DATA FORMAT
Receive data in (ROil or transmit data out (TOO) is the serial data which is presented between the
internal data bus and the output pin (TOO), and between the input pin (R Oil and the internal data
bus. Data format is as shown for the NRZ in Figure 5-1 and must meet the following criteria:
1. A high level indicates a logic one and a low level indicates a logic zero.
2. The idle line is in a high (logic one) state prior to transmission/ reception of a message.
3. A start bit (logic zero) is transmitted/ received indicating the start of a message.
4. The data is transmitted and received least-significant-bit first.
5. A stop bit (high in the tenth or eleventh bit position) indicates the byte is complete.
6. A break is defined as the transmission or reception of a low (logic zero) for some multiple of
the data format.

II

Control bit "M"
Selects 8 or 9 bit data

3

Idle Line

a

4

s

s
* Stop bit is always high

Figure 5-1. Data Format

5.3 WAKE-UP FEATURE
In a typical multiprocessor configuration, the software protocol will usually identify the addressee(s)
at the beginning of the message. In order to permit uninterested MPUs to ignore the remainder of
the message, a wake-up feature is included whereby all further SCI receiver flag (and interrupt) processing can be inhibited until its data line returns to the idle state. An SCI receiver is re-enabled by
an idle string of at least ten (or eleven) consecutive ones. Software for the transmitter must provide
for the required idle string between consecutive messages and prevent it from occurring within
messages.
The user is allowed a second method of providing the wake-up feature in lieu of the idle string
discussed above. This method allows the user to insert a logic one in the most significant bit of the
transmit data word which needs to be received by all "sleeping" processors.
5.4 RECEIVE DATA IN
Receive data in is the serial data which is presented from the input pin via the SCI to the internal
data bus. While waiting for a start bit, the receiver samples the input at a rate which is 16 times
higher than the set baud rate. This 16 times higher-than-baud rate is referred to as the RT rate in
Figures 5-2 and 5-3, and as the receiver clock in Figure 5-7. When the input (idle) line is detected
low, it is tested for three more sample times (referred to as the start edge verification samples in
Figure 5-2). If at least two of these three verification samples detect a logic low, a valid start bit is
assumed to have been detected (by a logic low following the three start qualifiers) as shown in
Figure 5-2; however, if in two or more of the verification samples a logic high is detected, the line is

3-548

MC68HCOSC4

Idle

Start

I

ROl1

0
0

Start
Oualifiers

Start Edge
Verification
Samples

Idle

Start

Noise

n

ROl2

Iidle

Noise

Start

U

ROl3

I

o

RT Clock Edges (for all three examples)

Figure 5-2. Examples of Start Bit Sampling Technique

Previous Bit

Samples

Present Bit

ROI
16

1

R
T

R
T

Next Bit

V

V

V

R
T

9
R
T

10
R
T

16

1

R

R

T

T

Figure 5-3. Sampling Technique Used on All Bits

assumed to be idle. (A noise flag is set if one of the three verification samples detects a logic high,
thus a valid start bit could be assumed and a noise flag still set.) The receiver clock generator is controlled by the baud rate register (see Figures 5-6 and 5-7); however, the serial communications interface is synchronized by the start bit (independent of the transmitter).
Once a valid start bit is detected, the start bit, each data bit, and the stop bit are sampled three
times at RT intervals of 8RT, 9RT, and 10RT (1 RT is the position where the bit is expected to start)
as shown in Figure 5-3. The value of the bit is determined by voting logic which takes the value of
the majority of samples (two or three out of three). A noise flag is set when all three samples on a
valid start bit or a data bit or the stop bit do not agree. (As discussed above, a noise flag is also set
when the start bit verification samples do not agree.)
5.5 START BIT DETECTION FOLLOWING A FRAMING ERROR

If there has been a framing error without detection of a break (10 zeros for 8-bit format or 11 zeros
for 9-bit format), the circuit continues to operate as if there actually were a stop bit and the start

3·549

MC68HC05C4

edge will be placed artificially. The last bit received in the data shift register is inverted to a logic
one, and the three logic one start qualifiers (shown in Figure 5-2) are forced into the sample shift
register during the interval when detection of a start bit is anticipated (see Figure 5-4); therefore the
start bit will be accepted no sooner than it is anticipated.
If the receiver detects that a break (R DR F = 1, FE = 1, receiver data register = $00) produced the
framing error, the start bit will not be artificially induced and the receiver must actually receive a
logic one bit before start. See Figure 5-5.

~Data~ Expected Stop --.j

I

Artificial Edge

--11
,

Receive~
Data In

I

Start Bit

I

ttt

r--Data~

~

Data
Samples

(a) Case 1, Receive Line Low During Artificial Edge

~Data
Receive

_I.
I

Dataln~

Expected Sto p

--1

U----I

/StartEdge
Start Bit

ttt

I
~Data--+-

'---'

Data
Samples

(b) Case 2, Receive Line High During Expected Start Edge

Figure 5-4. SCI Artificial Start Following A Framing Error

~Expected s t o j .

Detected as Valid
Start Edge

II

Receive ....-Break
Data In

ttt

~

•

Start Bit

r

L,;.-._----'

------------------------------~

ttt
T

ttt tttt t"'--"'
tt

T

Data Samples

~
Start
Start Edge
Qualifiers Verification
Samples

Figure 5-5. SCI Start Bit Following A Break

3·550

MC68HC05C4

5.6 TRANSMIT DATA OUT (TOO)

Transmit data out is the serial data which is presented from the internal data bus via the SCI and
then to the output pin. Data format is as discussed above and shown in Figure 5-1. The transmitter
generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal
to 1116 that of the receiver sample clock.
5.7 REGISTERS

There are five different registers used in the serial communications interface (SCI) and the internal
configuration of these registers is discussed in the following paragraphs. A block diagram of the
SCI system is shown in Figure 5-6.
5.7.1 Serial Communications Data Register (SCDAT)

Serial Communications Data Register

$11

The serial communications data register performs two functions in the serial communications interface; i.e. it acts as the receive data register when it is read and as the transmit data register when it
is written. Figure 5-6 shows this register as two separate registers, namely: the receive data register
(RDR) and the transmit data register (TOR), As shown in Figure 5-6, the TOR (transmit data
register) provides the parallel interface from the internal data bus to the transmit shift register and
the receive data register (R DR) provides the interface from the receive shift register to the internal
data bus.
When SCDAT is read, it becomes the receive data register and contains the last byte of data
received. The receive data register, represented above, is a read-only register containing the last
byte of data received from the shift register for the internal data bus. The RDR F bit (receive data
register full bit in the serial communications status register) is set to indicate that a byte has been
transferred from the input serial shift register to the serial communications data register. The
transfer is synchronized with the receiver bit rate clock (from the receive control) as shown in Figure
5-6. All data is received least-significant-bit first.
When SCDAT is written, it becomes the transmit data register and contains the next byte of data to
be transmitted. The transmit data register, also represented above, is a write-only register containing the next byte of data to be applied to the transmit shift register from the internal data bus. As
long as the transmitter is enabled, data stored in the serial communications data register is transferred to the transmit shift register (after the current byte in the shift register has been transmitted).
The transfer from the SCDAT to the transmit shift register is synchronized with the bit rate clock
(from the transmit control) as shown in Figure 5-6. All data is transmitted least-significant-bit first.
5.7.2 Serial Communications Control Register 1 (SCCR1)
R8

T8

M

I WAKE I

$OE

The serial communications control register 1 (SCCR 1) provides the control bits which: 1) determine
the word length (either 8 or 9 bits), and 2) selects the method used for the wake-up feature. Bits 6
and 7 provide a location for storing the ninth bit for longer bytes.

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I

MC68HC05C4

Internal Bus

I

Internal
Processor
Clock

$OD

$OE

NOTE: The Serial Communications Data Register (SCDATI is controlled by the internal R/W signal. It is the transmit data register when
written and receive data register when read.

Figure 5-6. Serial Communications Interface Block Diagram

3-552

MC68HC05C4

B7, R8

If the M bit is a one, then this bit provides a storage location for the ninth bit in
the receive data byte. Reset does not affect this bit.

B6, T8

If the M bit is a one, then this bit provides a storage location for the ninth bit in
the transmit data byte. Reset does not affect this bit.

B4, M

The option of the word length is selected by the configuration of this bit and is
shown below. Reset does not affect this bit.
0= 1 start bit, 8 data bits, 1 stop bit
1 = 1 start bit, 9 data bits, 1 stop bit

B3, WAKE

This bit allows the user to select the method for receiver "wake up". If the
WAKE bit is a logic zero, an idle line condition will "wake up" the receiver. If
the WAKE bit is set to a logic one, the system acknowledges an address bit
(most significant bit). The address bit is dependent on both the WAKE bit and
the M bit level (table shown below). (Additionally, the receiver does not use the
wake-up feature unless the RWU control bit in serial communications control
register 2 is set as discussed below.) Reset does not affect this bit.
Wake

M

Method of Receiver "Wake-Up"

o

X

Detection of an idle line allows the next data byte received
to cause the receive data register to fill and produce an
RDRF flag.
Detection of a received one in the eighth data bit allows an
RDRF flag and associated error flags.
Detection of a received one in the ninth data bit allows an
RDRF flag and associated error flags.

o

5.7.3 Serial Communications Control Register 2 (SCCR2)

I

7
TIE

I

6
TCIE

I

5
RIE

I

4
ILiE

I

3
TE

RE

RWU

SBK

$OF

The serial communications control register 2 (SCCR2) provides the control bits which: individually
enable/ disable the transmitter or receiver, enable the system interrupts, and provide the wake-up
enable bit and a "send break code" bit. Each of these bits is described below. (The individual flags
are discussed in the 5.7.4 Serial Communications Status Register.)
B7, TIE

When the transmit interrupt enable bit is set, the SCI interrupt occurs provided
TDRE is set (see Figure 5-6), When TIE is clear, the TDRE interrupt is disabled.
Reset clears the TIE bit.

B6, TCIE

When the transmission complete interrupt enable bit is set, the SCI interrupt
occurs provided TC is set (see Figure 5-6), When TCIE is clear, the TC interrupt
is disabled. Reset clears the TCIE bit.

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MC68HC05C4

B5, RIE

When the receive interrupt enable bit is set, the SCI interrupt occurs provided
OR is set or RDRF is set (see Figure 5-6), When RIE is clear, the OR and RDRF
interrupts are disabled. Reset clears the RIE bit.

B4,IUE

When the idle line interrupt enable bit is set, the SCI interrupt occurs provided
IDLE is set (see Figure 5-6). When ILiE is clear, the IDLE interrupt is disabled.
,Reset clears the ILiE bit.

B3, TE

When the transmit enable bit is set, the transmit shift register output is applied
to the TOO line. Depending on the state of control bit M in serial communications control register 1, a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones
is transmitted when software sets the TE bit from a cleared state. If a transmission is in. progress, and TE is written to a zero, then the transmitter will wait
until after' the present byte has been transmitted before placing the TOO pin in
the idle high-impedance state. If the TE bit has been written to a zero and then
set to a one before the current byte is transmitted, the transmitter will wait until
that byte is transmitted and will then initiate transmission of a new preamble,
After the preamble is transmitted, and provided the TORE bit is set (no new
data to transmit), the line remains idle (driven high while TE = 1); otherwise,
normal transmission occurs, This function allows the user to "neatly" terminate a transmission sequence. After loading the last byte in the serial communications data register and receiving the interrupt from TORE, indicating the
data has been transferred into the shift register, the user should clear TE. The
last byte will then be transmitted and the line will go idle (high impedance).
Reset clears the TE bit.

B2, RE

When the receive enable bit is set, the receiver is enabled. When RE is clear,
the receiver is disabled and all of the status bits associated with the receiver
(RDRF, IDLE, OR, NF, and FE) are inhibited. Reset clears the RE bit.

B1, RWU

When the receiver wake-up bit is set, it enables the "wake up" function. The
type of "wake up" mode for the receiver is determined by the WAK E bit
discussed above (in the SCCR1l. When the RWU bit is set, no status flags will
be set. Flags which were set previously will not be cleared when RWU is set. If
the WAKE bit is cleared, RWU is cleared after receiving 10 (M = 0) or 11 (M = 1)
consecutive ones, Under these conditions, RWU cannot be set if the line is
idle. If the WAKE bit is set, RWU is cleared after receiving an address bit. The
RDRF flag will then be set and the address byte will be stored in the receiver
data register. Reset clears the RWU bit.

BO, SBK

When the send break bit is set the transmitter sends zeros in some number
equal to a multiple of the data format bits. If the SBK bit is toggled set and
clear, the transmitter sends 10 (M = 0) or 11 (M = 1) zeros and then reverts to
idle or sending data. The actual number of zeros sent when SBK is toggled
depends on the data format set by the M bit in the serial communications control register 1; therefore, the break code will be synchronous with respect to
the data stream. At the completion of the break code, the transmitter sends at
least one high bit to guarantee recognition of a valid start bit. Reset clears the
SBK bit.

I

3·554

MC68HC05C4

5.7.4 Serial Communications Status Register (SCSR)

TDRE

TC

RDRF

IDLE

OR

NF

FE

$10

The serial communications status register (SCSR) provides inputs to the interrupt logic circuits for
generation of the SCI system interrupt. In addition, a noise flag bit and a framing error bit are also
contained in the SCSR.
87, TDRE

86, TC

The transmit data register empty bit is set to indicate that the contents of the
serial communications data register have been transferred to the transmit serial
shift register. If the TDR E bit is clear, it indicates that the transfer has not yet
occurred and a write to the serial communications data register will overwrite
the previous value. The TDRE bit is cleared by accessing the serial communications status register (with TDRE set), followed by writing to the serial communications data register. Data can not be transmitted unless the serial communications status register is accessed before writing to the serial communications data register to clear the TD RE flag bit. Reset sets the TD RE bit.
The transmit complete bit is set at the end of a data frame, preamble, or break
condition if:
1. TE = 1, TD RE = 1, and no pending data, preamble, or break is to be
transmitted; or
2. TE = 0, and the data, preamble, or break (in the transmit shift register)
has been transmitted.
The TC bit is a status flag which indicates that one of the above conditions has
occurred. The TC bit is cleared by accessing the serial communications status
register (with TC set), followed by writing to the serial communications data
register. It does not inhibit the transmitter function in any way. Reset sets the
TC bit.

85, RDRF

When the receive data register full bit is set, it indicates that the receiver serial
shift register is transferred to the serial communications data register. If multiple errors are detected in anyone received word, the N F, FE, and RDR F bits
will be affected as appropriate during the same clock cycle. The RDRF bit is
cleared when the serial communications status register is accessed (with RDR F
set) followed by a read of the serial communications data register. Reset clears
the RDRF bit.

84, IDLE

When the idle line detect bit is set, it indicates that a receiver idle line is
detected (receipt of a minimum number of ones to constitute the number of
bits in the byte format). The minimum number of ones needed will be 10
(M = 0) or 11 (M = 1). This allows a receiver that is not in the wake-up mode to
detect the end of a message, detect the preamble of a new message, or to
resynchronize with the transmitter. The IDLE bit is cleared by accessing the
serial communications status register (with IDLE set) followed by a read of the
serial communications data register. The IDLE bit will not be set again until

3·555

I

MC68HC05C4

after an RDRF has been. set; i.e., a new idle line occurs. The IDLE bit is not set
by an idle line when the receiver "wakes up" from the wake-up mode. Reset
clears the IDLE bit.
83, OR

When the overrun error bit is set, it indicates that the next byte is ready to be
transferred from the receive shift register to the serial commu nications data
register when it is already full (R D RF bit is set). Data transfer is then inhibited
until the RDRF bit is cleared. Data in the serial communications data register is
valid in this case, but additional data received during an overrun condition (including the byte causing the overrun) will be lost. The OR bit is cleared when
the serial communications status register is accessed (with OR set), followed
by a read of the serial communications data register. Reset clears the OR bit.

82, NF

The noise flag bit is set if there is noise on a "valid" start bit or if there is noise
on any of the data bits or if there is noise on the stop bit. It is not set by noise
on the idle line nor by invalid (false) start bits. If there is noise, the NF bit is not
set until the RDRF flag is set. Each data bit is sampled three times as described
above in RECEIVE DATA IN and shown in Figure 5-3. The NF bit represents the
status of the byte in the serial communications data register. For the byte being
received (shifted in) there will also be a "working" noise flag the value of which
will be transferred to the NF bit when the serial data is loaded into the serial
communications data register. The NF bit does not generate an interrupt
because the RDRF bit gets set with NF and can be used to generate the interrupt. The NF bit is cleared when the serial communications status register is accessed (with NF set), followed by a read of the serial communications data
register. Reset clears the NF bit.

81, FE

The framing error bit is set when the byte boundaries in the bit stream arenot
synchronized with the receiver bit counter (generated by a "lost" stop bit). The
byte is transferred to the serial communications data register and the RDRF bit
is set. The FE bit does not generate an interrupt because the RDRF bit is set at
the same time as FE and can be used to generate the interrupt. Note that if the
byte received causes a framing error and it will also cause an overrun if transferred to the serial communications data register, then the overrun bit will be set,
but not the framing error bit, and the byte will not be transferred to the serial
communications data register. The FE bit is cleared when the serial communications status register is accessed (with FE set) followed by a read of the
serial communications data register. Reset clears the FE bit.

I

5.7.5 Baud Rate Register
4
SCPl

SCPO

SCR2

SCRl

SCRO

SOD

The baud rate register provides the means for selecting different baud rates which may be used as
the rate control for the transmitter and receiver. The SCPO-SCP1 bits function as a prescaler for the

3-556

MC68HC05C4

SCRO-SCR2 bits. Together, these five bits provide multiple, baud rate combinations for a given
crystal frequency.
B5, SCP1
B4, SCPO

These two bits in the baud rate register are used as a prescaler to increase the
range of standard baud rates controlled by the SCRO-SCR2 bits. A table of the
prescaler internal processor clock division versus bit levels is provided below.
Reset clears SCP1-SCPO bits (divide-by-one).

SCP1
0
0
1
1
B2, SCR2
B1, SCR1
BO, SCRO

SCPO
0
1
0
1

Internal Processor
Clock Divide By
1
3
4
13

These three bits in the baud rate register are used to select the baud rates of
both the transmitter and receiver. A table of baud rates versus bit levels is
shown below. Reset does not affect the SCR2-SCRO bits.

SCR2 SCR1
0
0
0
0
0
1
1
0
0
1
1
0
1
1
1
1

Prescaler Output
Divide By

SCRO
0
1
0
1
0
1
0
1

1
2
4
8
16
32
64
128

The diagram of Figure 5-7 and Tables 5-1 and 5-2 illustrate the divided chain used to obtain the baud
rate clock (transmit clock). Note that there is a fixed rate divide-by-16 between the receive clock
(RT) and the transmit clock (Tx). The actual divider chain is controlled by the combined SCPO-SCP1
and SCRO-SCR2 bits in the baud rate register as illustrated. All divided frequencies shown in the
first table represent the final transmit clock (the actual baud rate) resulting from the internal processor clock division shown in the" divide-by" column only (prescaler division only). The second
table illustrates how the prescaler output can be further divided by action of the SCI select bits
(SCRO-SCR2). For example, assume that a 9600 Hz baud rate is required with a 2.4576 MHz external crystal. In this case the prescaler bits (SCPO-SCP1) could be configured as a divide-by-one or a
divide-by-four. If a divide-by-four prescaler is used, then the SCRO-SCR2 bits must be configured
as a divide-by-two. This results in a divide-by-128 of the internal processor clock to produce a 9600
Hz baud rate clock. Using the same crystal, the 9600 baud rate can be obtained with a prescaler
divide-by-one and the SCRO-SCR2 bits configured for a divide-by-eight.

NOTE
The crystal frequency is internally divided-by-two to generate the internal processor
clock.

3-557

11

MC68HC05C4

SCI
Transmit
Clock (Tx)

Oscillator
Frequency

SCPO-SCP1
Prescaler
Control

SCRO-SCR2
SCI Select
Rate Control

+N

+M

Receive
Clock (RT)

Figure 5-7. Rate Generator Division

I

Table 5-1. Prescaler Highest Baud Rate Frequency Output
SCP Bit
1
0
0
0
1
1

Clock*
Divided By
1
3
4
13

0
1
0
1

Crystal Frequency MHz
4.194304
131.072
43.691
32.768
10082

kHz
kHz
kHz
kHz

4.0
125.000
41.666
31.250
9600

2.4576
kHz
kHz
kHz
Hz

76.80
25.60
19.20
5.907

kHz
kHz
kHz
kHz

1.8432

2.0
62.50
20.833
15.625
4800

kHz
kHz
kHz
Hz

57.60
19.20
14.40
4430

kHz
kHz
kHz
Hz

*The clock in the "Clock Divided By" column is the internal processor clock.
NOTE' The divided frequencies shown in Table 5-1 represent baud rates which are the highest transmit baud rate (Tx) that can be obtained by a specific crystal frequency and only using the prescaler division. Lower baud rates may be obtained by providing a
further division using the SCI rate select bits as shown below for some representative prescaler outputs.

Table 5-2. Transmit Baud Rate Output For a Given Prescaler Output

2
0
0
0
0
1
1
1
1

SCR Bits
1
0
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Divide
By
1
2
4
8
16
32
64

128

Representative Highest Prescaler Baud Rate Output
131.072 kHz

32.768 kHz

76.80 kHz

19.20 kHz

9600 Hz

131.072
65.536
32.768
16.384
8.192
4096
2048
1.024

32.768
16.384
8.192
4096
2.048
1.024
512
256

76.80
38.40
19.20
9600
4800
2400
1200
600

19.20
9600
4800
2400
1200
600
300
150

9600
4800
2400
1200
600
300
150
75

kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz

kHz
kHz
kHz
kHz
kHz
kHz
Hz
Hz

kHz
kHz
kHz
Hz
Hz
Hz
Hz
Hz

kHz
Hz
Hz
Hz
Hz
Hz
Hz
Hz

Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz

NOTE' Table 5-2 illustrates how the SCI select bits can be used to prOVide lower transmitter baud rates by further diViding the prescaler
output frequency. The five examples are only representative samples. In all cases, the baud rates shown are transmit baud rates
(transmit clock) and the receiver clock is 16 times higher in frequency than the actual baud rate.

3-558

MC68HC05C4

SECTION 6
SERIAL PERIPHERAL INTERFACE (SPI)
6.1 INTRODUCTION AND FEATURES
6.1.1 Introduction
The serial peripheral interface (SPI) is an interface built into the MC68HC05C4 MCU which allows
several MC68HC05C4 MCUs, or MC68HC05C4 plus peripheral devices, to be interconnected within
a single "black box" or on the same printed circuit board. In a serial peripheral interface (SPI),
separate wires (signals) are required for data and clock. In the SPI format, the clock is not included
in the data stream and must be furnished as a separate signal. An SPI system may be configured in
one containing one master MCU and several slave MCUs, or in a system in which an MCU is
capable of being either a master or a slave.
Figure 6-1 illustrates two different system configurations. Figure 6-1a represents a system of five
different MCUs in which there are one master and four slaves (0, 1, 2, 3), In this system four basic
lines (signals) are required for the MOSI (master out slave in), MISO (master in slave out), SCK
(serial clock), and SS (slave select) lines. Figure 6-1 b represents a system of five MCUs in which
three can be master or slave and two are slave only.
6.1.2 Features
•
•
•
•
•
•
•
•
•

Full duplex, three-wire synchronous transfers
Master or slave operation
1.05 MHz (maximum) master bit frequency
2.1 MHz (maximum) slave bit frequency
Four programmable master bit rates
Programmable clock polarity and phase
End of transmission interrupt flag
Write collision flag protection
Master-Master mode fault protection capability

6.2 SIGNAL DESCRIPTION
The four basic signals (MOSI, MISO, SCK, and SS) discussed above are described in the following
paragraphs. Each signal function is described for both the master and slave mode.
6.2.1 Master Out Slave In (MOS!)
The MOSI pin is configured as a data output in a master (mode) device and as a data input in a slave
(mode) device. In this manner data is transferred serially from a master to a slave on this line; most

3-559

I

MC68HC05C4

MISO
MOSI
SCK

SS

M6805 HCMOS SlaveO

I

MISO SCK_
MOSI
SS

I---VDD

L-----

M6805 HCMOS
Master

I

p

0

0
R
T

2
3 f--

1

r

I II

I

I 1

l

MOSI
SS
MISO SCK

MOSI
SS
MISO
SCK

MOSI
SS
MISO
SCK

M6805 HCMOS SIave3

M6805 HCMOS Slave 1

M6805 HCMOS Slave 2

a. Single Master, Four Slaves

M6805 HCMOS 1
Master / Slave

l3i TI [
MISO
SCK

MISO SC~
MOSI SS

SS r----

M6805 HCMOS 0
Master/ Slave

~

5
0

p

0
R

1

...
T
I

I

I

I

~

I

I

I

MOSI SS
MISO SCK

M6805 HCMOS 4
Slave Only For 0

I T
I I

I

~

I

5

o1

I

Sync
Line

2
3
4 f----

T

r

I I T

MOSI SS
MISO SCK

M6805 HCMOS 3
Slave ForO-l·2

32 1 0 51

MOSI SS
MISO SCK

M6805 HCMOS 2
Master/ Slave

b. Three Master/Slave, Two Slaves

Figure 6-1. Master-Slave System Configuration

3-560

2 3

MC68HC05C4

significant bit first, least significant bit last. The timing diagrams of Figure 6-2 summarize the SPI
timing diagram shown in Section 9, and show the relationship between data and clock (SCKl. As
shown in Figure 6-2, four possible timing relationships may be chosen by using control bits CPOL
and CPHA. The master device always allows data to be applied on the MOSIline a half-cycle before
the clock edge (SCK) in order for the slave device to latch the data.
NOTE

Both the slave device(s) and a master device must be programmed to similar timing
modes for proper data transfer.
When the master device transmits data to a second (slave) device via the MOSI line, the slave
device responds by sending data to the master device via the MISO line. This implies full duplex
transmission with both data out and data in synchronized with the same clock signal (one which is
provided by the master device). Thus, the byte transmitted is replaced by the byte received and
eliminates the need for separate transmit-empty and receiver-full status bits. A single status bit
(SPIF) is used to signify that the I/O operation is complete.
Configuration of the MOSI pin is a function of the MSTR bit in the serial peripheral control register
(SPCR, location $OAl. When a device is operating as a master, the MOSI pin is an output because
the program in firmware sets the MSTR bit to a logic one.

~l~

____________________________________

~ISS

SCK
(CPOL=O, CPHA=O)

SCK
(CPOL=O, CPHA= 1)
SCK
(CPOL= 1, CPHA=O)

SCK
(CPOL=l,CPHA=1)
MISO/
MOSI

!iliA

LSB

MSB

internal strobe for data capture (all modes)

Figure 6-2. Data Clock Timing Diagram

3-561

vii

I

MC68HC05C4

6.2.2 Master In Slave Out (MISO)
The MISO pin is configured as an input in a master (mode) device and as an output in a slave
(mode) device. In this manner data is transferred serially from a slave to a master on this line; most
significant bit first, least significant bit last. The MISO pin of a slave device is placed in the highimpedance state if it is not selected by the master; i.e., its SS pin is a logic one. The timing diagram
of Figure 6-2 shows the relationship between data and clock (SCK). As shown in Figure 6-2, four
possible timing relationships may be chosen by using control bits CPOl and CPHA. The master
device always allows data to be applied on the MOSIline a half-cycle before the clock edge (SCK) in
order for the slave device to latch the data.

NOTE
The slave device(s) and a master device must be programmed to similar timing modes for
proper data transfer.

I

When the master device transmits data to a slave device via the MOSI line, the slave device
responds by sending data to the master device via the MISO line. This implies full duplex transmission with both data out and data in synchronized with the same clock signal (one which is provided
by the master device). Thus, the byte transmitted is replaced by the byte received and eliminates the
need for separate transmit-empty and receiver-full status bits. A single status bit (SPIF) in the serial
peripheral status register (SPSR, location SOB) is used to signify that the I/O operation is complete.
In the master device, the MSTR control bit in the serial peripheral control register (SPCR, location
$OA) is set to a logic one (by the program) to allow the master device to receive data on its MISO
pin. In the slave device, its MISO pin is enabled by the logic level of the SS pin; i.e., if SS = 1 then
the MISO pin is placed in the high-impedance state, whereas, if SS=O the MISO pin is an output
for the slave device.

6.2.3 Slave Select (55)
The slave select (SS) pin is a fixed input (PD5, pin 34), which receives an active low signal that is
generated by the master device to enable slave device(s) to accept data. To ensure that data will be
accepted by a slave device, the SS signal line must be a logic low prior to occurrence of SCK
(system clock) and must remain low until after the last (eighth) SCK cycle. Figure 6-2 illustrates the
relationship between SCK and the data for two different level combinations of CPHA, when SS is
pulled low. These are: 1) with CPHA = 1 or 0, the first bit of data is applied to the MISO line for
transfer, and 2) when CPHA = 0 the slave device is prevented from writing to its data register. Refer
to the WCOl status flag in the serial peripheral status register (location SOB) description for further
information on the effects that the SS input and CPHA control bit have on the I/O data register. A
high level SS signal forces the MISO (master in slave out) line to the high-impedance state. Also,
SCK and the MOSI (master out slave in) line are ignored by a slave device when its SS signal is
high.
When a device is a master, it constantly monitors its SS signal input for a logic low. The master
device will become a slave device any time its SS Signal input is detected low. This ensures that
there is only on,8 master controlling the SS line for a particular system. When the SS line is detected
low, it clears the MSTR control bit (serial peripheral control register, location $OA). Also, control bit
S PE in the serial peripheral control register is cleared which causes the serial peripheral interface
(SPI) to be disabled (port D SPI pins become inputs). The MODF flag bit in the serial peripheral
status register (location SOB) is also set to indicate to the master device that another device is attempting to become a master. Two devices attempting to be outputs are normally the result of a

3-562

MC68HC05C4

software error; however, a system could be configured which would contain a default master which
would automatically "take-over" and restart the system.
6.2.4 Serial Clock (SCK)

The serial clock is used to synchronize the movement of data both in and out of the device through
its MOSI and MISO pins. The master and slave devices are capable of exchanging a data byte of information during a sequence of eight clock pulses. Since the SCK is generated by the master
device, the SCK line becomes an input on all slave devices and synchronizes slave data transfer.
The type of clock and its relationship to data are controlled by the CPOL and CPHA bits in the serial
peripheral control register (iocation $OA) discussed below. Refer to Figure 6-2 for timing.
The master device generates the SCK through a circuit driven by the internal processor clock. Two
bits (SPRO and SPR1) in the serial peripheral control register (location $OA) of the master device
select the clock rate. The master device uses the SCK to latch incoming slave device data on the
MISO line and shifts out data to the slave device on the MOSI line. Both master and slave devices
must be operated in the same timing mode as controlled by the CPOL and CPHA bit in the serial
peripheral control register. In the slave device, SPRO, SPR1 have no effect on the operation of the
serial peripheral interface. Timing is shown in Figure 6-2.
6.3 FUNCTIONAL DESCRIPTION

A block diagram of the serial peripheral interface (SPI) is shown in Figure 6-3. In a master configuration, the master start logic receives an input from the CPU (in the form of a write to the SPI rate
generator) and originates the system clock (SCK) based on the internal processor clock. This clock
is also used internally to control the state controller as well as the 8-bit shift register. As a master
device, data is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin for application to the slave device(s). During a read cycle, data is applied serially from a slave device via the MISO pin to the 8-bit shift register. After the
8-bit shift register is loaded, its data is parallel transferred to the read buffer and then is made
available to the internal data bus during a CPU read cycle.
In a slave configuration, the slave start logic receives a logic low (from a master device) at the SS
pin and a system clock input (from the same master device) at the SCK pin. Thus, the slave is synchronized with the master. Data from the master is received serially at the siaveMOSI pin and loads
the 8-bit shift register. After the 8-bit shift register is loaded, its data is parallel transferred to the
read buffer and then is made available to the internal data bus during a CPU read cycle. During a
write cycle, data is parallel loaded into the 8-bit shift register from the internal data bus and then
shifted out serially to the MISO pin for application to the master device.
Figure 6-4 illustrates the MOSI, MISO, and SCK master-slave interconnections. Note that in Figure
6-4 the master SS pin is tied to a logic high and the slave SS pin is a logic low. Figure 6-1 provides a
larger system connection for these same pins. Note that in Figure 6-1, all SS pins are connected to a
port pin of a master/slave device. In this case any of the devices can be a slave.

3-563

I

•

3:

o0')

CO
~

oo
en
o

See Note
Internal
Processor
Clock

33

~

Internal
Data
Bus

34

U)

Ot

0>
~

SPCR

$OA '..--....----'

NOTE: The SS, SCK, MOSI, and MISO are external pins which provide the following functions·
a. MOSI- Provides serial output to slave unit(s) when device is configured as a master. Receives serial input from master unit
when device is configured as a slave unit.
b. MISO- Receives serial input from slave unit(s) when device is configured as a master. Provides serial output to master when
device is configured as a slave unit.
c. SCK - Provides system clock when device is configured as a master unit. Receives system clock when device is configured as
a slave unit.
d. SS
- Provides a logic low to select a slave device for a transfer with a master device.

Figure 6-3. Serial Peripheral Interface Block Diagram

MC68HC05C4

Master

Slave

I

I

I
MISOI

I MISO

8-Bit Shift Register

8-Bit Shift Register

I
I MOSI
I
I

I

I SCK

SCKI
I
SSI
OV - - - - ,

ISS
+5V

I

Figure 6-4. Serial Peripheral Interface Master-Slave Interconnection

6.4 REGISTERS

There are three registers in the serial parallel interface which provide control, status, and data
storage functions. These registers which include the serial peripheral control register (SPCR, location $OA), serial peripheral status register (SPSR, location SOB), and serial peripheral data I/O
register (SPDR, location SOC) are described below.
6.4.1 Serial Peripheral Control Register (SPCR)

I

7
SPIE

I

6
SPE

I

I

4
MSTR

I

3
CPOL

I

2
CPHA

SPR1

SPRO

$OA

The serial peripheral control register bits are defined as follows:
B7, SPIE

When the serial peripheral interrupt enable bit is high, it allows the occurrence
of a processor interrupt, and forces the proper vector to be loaded into the program counter if the serial peripheral status register flag bit (S PI F and/ or M ODF)
is set to a logic one. It does not inhibit the setting of a status bit. The S PI E bit is
cleared by reset.

B6, SPE

When the serial peripheral output enable control bit is set, all output drive is applied to the external pins and the system is enabled. When the S PE bit is set, it
enables the SPI system by connecting it to the external pins thus allowing it to
interface with the external SPI bus. The pins that are defined as output depend
on which mode (master or slave) the device is in. Because the SPE bit is cleared
by reset, the SPI system is not connected to the external pins upon reset.

B4, MSTR

The master bit determines whether the device is a master or a slave. If the
M STR bit is a logic zero it indicates a slave device and a logic one denotes a
master device. If the master mode is selected; the function of the SCK pin
changes from an input to an output and the function of the MISO and MOSI
pins are reversed. This allows the user to wire device pins MISO to MISO, and
MOSI to MOSI, and SCK to SCK without incident. The MSTR bit is cleared by
reset; therefore, the device is always placed in the slave mode during reset.

3-565

II

MC68HCOSC4

83, CPOl

The clock polarity bit controls the normal or steady state value of the clock
when data is not being transferred. The CPOl bit affects both the master and
slave modes. It must be used in conjunction with the clock phase control bit
(CPHA) to produce the wanted clock-data relationship between a master and a
slave device. When the CPOl bit is a logic zero, it produces a steady state low
value at the SCK pin of the master device. If the CPOl bit is a logic one, a high
value is produced at the SCK pin of the master device when data is not being
transferred. The CPOl bit is not affected by reset. Refer to Figure 6-2.

82, CPHA

The clock phase bit controls the relationship between the data on the M I SO
and MOSI pins and the clock produced or received at the SCK pin. This control
has effect in both the master and slave modes. It must be used in conjunction
with the clock polarity control bit (CPOl) to produce the wanted clock-data
relation. The CPHA bit in general selects the clock edge which captures data
and allows it to change states. It has its greatest impact on the first bit transmitted (M S 8) in that it does or does not allow a clock transition before the first
data capture edge. The CPHA bit is not affected by reset. Refer to Figure 6-2.

81, SPR1
80, SPRO

These two serial peripheral rate bits select one of four baud rates to be used as
SCK if the device is a master; however they have no effect in the slave mode.
The slave device is capable of shifting data in and out at a maximum rate which
is equal to the CPU clock. A rate table is given below for the generation of the
SCK from the master. The SPR1 and SPRO bits are not affected by reset.

I

SPR1

SPRO

Internal Processor
Clock Divide 8y

0
0
1
1

0
1
0
1

2
4
16
32

6.4.2 Serial Peripheral Status Register (SPSR)
7

I

SPIF

6

I

weal

o

4

I

I

MODF

I

SOB

The status flags which generate a serial peripheral interface (S PI) interrupt may be blocked by the
SPIE control bit in the serial peripheral control register. The WCOl bit does not cause an interrupt.
The serial peripheral status register bits are defined as follows:
87, SPIF

The serial peripheral data transfer flag bit notifies the user that a data transfer
between the device and an external device has been completed. With the completion of the data transfer, SPIF is set, and if SPIE is set, a serial peripheral
interrupt (SPI) is generated. During the clock cycle that SPIF is being set, a
copy of the received data byte in the shift register is moved to a buffer. When
the data register is read, it is the buffer that is read. During an overrun condition, when the master device has sent several bytes of data and the slave
device has not responded to the first SPIF, only the first byte sent is contained
in the receiver buffer and all other bytes are lost.

3·566

MC68HC05C4

The transfer of data is initiated by the master device writing its serial peripheral
data register.
Clearing the SPIF bit is accomplished by a software sequence of accessing the
serial peripheral status register while SPIF is set and followed by a write to or a
read of the serial peripheral data register. While S PI F is set, all writes to the
serial peripheral data register are inhibited until the serial peripheral status
register is read. This occurs in the master device. In the slave device, SPIF can
be cleared (using a similar sequence) during a second transmission; however, it
must be cleared before the second SPIF in order to prevent an overrun condition. The S PI F bit is cleared by reset.
B6, WCOl

The function of the write collision status bit is to notify the user that an attempt
was made to write the serial peripheral data register while a data transfer was
taking place with an external device. The transfer continues uninterrupted;
therefore, a write will be unsuccessful. A "read collision" will never occur since
the received data byte is placed in a buffer in which access is always synchronous with the MCU operation. If a "write collision" occurs, WCOl is set
but no SPI interrupt is generated. The WCOl bit is a status flag only.
Clearing the WeOl bit is accomplished by a software sequence of accessing
the serial peripheral status register while WeOl is set, followed by 1) a read of
the serial peripheral data register prior to the S PI F bit being set, or 2) a read or
write of the serial peripheral data register after the SPIF bit is set. A write to the
serial peripheral data register (SPDR) prior to the SPIF bit being set, will result
in generation of another WCOl status flag. Both the SPIF and WeOl bits will
be cleared in the same sequence. If a second transfer has started while trying to
clear (the previously set) SPIF and WeOl bits with a clearing sequence containing a write to the serial peripheral data register, only the SPIF bit will be
cleared.
A collision of a write to the serial peripheral data register while an external data
transfer is taking place can occur in both the master mode and the slave mode,
although with proper programming the master device should have sufficient information to preclude this collision.
Collision in the master device is defined as a write of the serial peripheral data
register while the internal rate clock (SCK) is in the process of transfer. The
signal on the SS pin is always high on the master device.
A collision in a slave device is defined in two separate modes. One problem
arises in a slave device when the CPHA control bit is a logic zero. When CPHA
is a logic zero, data is latched with the occurrence of the first clock transition.
The slave device does not have any way of knowing when that transition will
occur; therefore, the slave device collision occurs when it attempts to write the
serial peripheral data register after its SS pin has been pulled low. The SS pin
of the slave device freezes the data in its serial peripheral data register and does
not allow it to be altered if the CPHA bit is a logic zero. The master device must
raise the SS pin of the slave device high between each byte it transfers to the
slave device.

3-567

I

MC68HC05C4

The second collision mode is defined for the state of the CPHA control bit being a logic one. With the CPHA bit set, the slave device will be receiving a clock
(SCK) edge prior to the latch of the first data transfer. This first clock edge will
freeze the data in the slave device I/O register and allow the msb onto the external MISO pin of the slave device. The SS pin low state enables the slave
device but the drive onto the MISO pin does not take place until the first data
transfer clock edge. The WCOl bit will only be set if the I/O register is accessed while a transfer is taking place. By definition of the second collision mode, a
master device might hold a slave device SS pin low during a transfer of several
bytes of data without a problem.
A special case of WCOl occurs in the slave device. This happens when the
master device starts a transfer sequence (an edge or SCK for CPHA= 1; or an
active SS transition for CPHA=O) at the same time the slave device CPU is
writing to its serial peripheral interface data register. In this case it is assumed
that the data byte written (in the slave device serial peripheral interface) is lost
and the contents of the slave device read buffer becomes the byte that is
transferred. Because the master device receives back the last byte transmitted,
the master device can detect that a fatal WCOl occurred.

II

Since the slave device is operating asynchronously with the master device, the
WCOl bit may be used as an indicator of a collision occurrence. This helps
alleviate the user from a strict real-time programming effort. The WCOl bit is
cleared by reset.
B4, MODF

The function of the mode fault flag is defined for the master mode (device). If
the device is a slave device the MODF bit will be prevented from toggling from
a logic zero to a logic one; however, this does not prevent the device from being in the slave mode with the MODF bit set. The MODF bit is normally a logic
zero and is set only when the master device has its SS pin pulled low. Toggling
the MODF bit to a logic one affects the internal serial peripheral interface (SPI)
system in the following ways:
1. MODF is set and SPI interrupt is generated if SPIE= 1.
2. The SPE bit is forced to a logic zero. This blocks all output drive from
the device, disables the SPI system.
3. The MSTR bit is forced to a logic zero, thus forcing the device into the
slave mode.
Clearing the MODF is accomplished by a software sequence of accessing the
serial peripheral status register while MODF is set followed by a write to the
serial peripheral control register. Control bits SPE and MSTR may be restored
to their original set state during this clearing sequence or after the MODF bit
has been cleared. Hardware does not allow the user to set the SPE and MSTR
bit while MODF is a logic one unless it is during the proper clearing sequence.
The MODF flag bit indicates that there might have been a multi-master conflict
for system control and allows a proper exit from system operation to a reset or
default system state. The MODF bit is cleared by reset.

3.. 568

MC68HC05C4

6.4.3 Serial Peripheral Data 1/0 Register (SPDR)
Serial Peripheral Data 1/0 Register

SOC

The serial peripheral data 1/0 register is used to transmit and receive data on the serial bus. Only a
write to this register will initiate transmission I reception of another byte and this will only occur in
the master device. A slave device writing to its data 1/0 register will not initiate a transmission. At
the completion of transmitting a byte of data, the S PI F status bit is set in both the master and slave
devices. A write or read of the serial peripheral data I/O register, after accessing the serial peripheral
status register with SPIF set, will clear SPIF.
During the clock cycle that the SPIF bit is being set, a copy of the received data byte in the shift
register is being moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read. During an overrun condition, when the master device has sent several
bytes of data and the slave device has not internally responded to clear the first S PIF, only the first
byte is contained in the receive buffer of the slave device; all others are lost. The user may read the
buffer at any time. The first SPIF must be cleared by the time a second transfer of data from the
shift register to the read buffer is initiated or an overrun condition will exist.
A write to the serial peripheral data 110 register is not buffered and places data directly into the shift
register for transmission.
The ability to access the serial peripheral data 1/0 register is limited when a transmission is taking
place. It is important to read the discussion defining the WCOl and SPIF status bits to understand
the limits on using the serial peripheral data I/O register.
6.5 SERIAL PERIPHERAL INTERFACE (SPI) SYSTEM CONSIDERATIONS

There are two types of SPI systems; single master system and multi-master systems. Figure 6-1
illustrates both of these systems and a discussion of each is provided below.
Figure 6-1 a illustrates how a typical single master system may be configured, using an M6805
HCMOS family device as the master and four M6805 HCMOS family devices as slaves. As shown,
the MOSI, MISO, and SCK pins are all wired to equivalent pins on each of the five devices. The
master device generates the SCK clock, the slave devices all receive it. Since the M6805 HCMOS
master device is the bus master, it internally controls the function of its MOSI and MISO lines, thus
writing data to the slave devices on the MOSI and reading data from the slave devices on the MISO
lines. The master device selects the individual slave devices by using four pins of a parallel port to
control the four SS pins of the slave devices. A slave device is selected when the master device
pulls its SS pin low. The SS pins are pulled high during reset since the master device ports will be
forced to be inputs at that time, thus disabling the slave devices. Note that the slave devices do not
have to be enabled in a mutually exclusive fashion except to prevent bus contention on the MISO
line. For example, three slave devices, enabled for a transfer, are permissible if only one has the
capability of being read by the master. An example of this is a write to several display drivers to clear
a display with a single I/O operation. To ensure that proper data transmission is occurring between
the master device and a slave device, the master device may have the slave device respond with a
previously received data byte (this data byte could be inverted or at least be a byte that is different
from the last one sent by the master device). The master device will always receive the previous

3-569

I

MC68HC05C4

byte back from the slave device if all MISO and MOSI lines are connected and the slave has not
written its data I/O register. Other transmission security methods might be defined using ports for
handshake lines or data bytes with command fields.
A multi-master system may also be configured by the user. A system of this type is shown in Figure
6-1 b. An exchange of master control could be implemented using a handshake method through the
I/O ports or by an exchange of code messages through the serial peripheral interface system. The
major device control that plays a part in this system is the MSTR bit in the serial peripheral control
register and the MODF bit in the serial peripheral status register.

I

3-570

MC68HC05C4

SECTION 7
EFFECTS OF STOP AND WAIT MODES ON THE
TIMER AND SERIAL SYSTEMS
7.1 INTRODUCTION
The STOP and WAIT instructions have different effects on the programmable timer, serial communications interface (SCI), and serial peripheral interface (SPI) systems. These different effects
are discussed separately below.

7.2 STOP MODE
When the processor executes the STOP instruction, the internal oscillator is turned off. This halts
all internal CPU processing including the operation of the programmable timer, serial communications interface, and serial peripheral interface. The only way for the MCU to "wake up" from the
stop mode is by receipt of an external interrupt (logic low on IRQ pin) or by the detection of a reset
(logic low on RESET pin or a power-on reset). The effects of the stop mode on each of the MCU
systems (Timer, SCI, and SPI) are described separately.

7.2.1 Timer During Stop Mode
When the MCU enters the stop mode, the timer counter stops counting (the internal processor
clock is stopped) and remains at that particular count value until the stop mode is exited by an interrupt (if exited by reset the counter is forced to $FFFC). If the stop mode is exited by an external low
on the IRQ pin, then the counter resumes from its stopped value as if nothing had happened.
Another feature of the programmable timer, in the stop mode, is that if at least one valid input capture edge occurs at the TCAP pin, the input capture detect circuitry is armed. This action does not
set any timer flags or "wake up" the MCU, but when the MCU does "wake up" there will be an active input capture flag (and data) from that first valid edge which occurred during the stop mode. If
the stop mode is exited by an external reset (logic low on RESET pin), then no such input capture
flag or data action takes place even if there was a valid input capture edge (at the TCAP pin) during
the MCU stop mode.

7.2.2 SCI During Stop Mode
When the MCU enters the stop mode, the baud rate generator which drives the receiver and
transmitter is shut down. This essentially stops all SCI activity. The receiver is unable to receive and
transmitter is unable to transmit. If the STOP instruction is executed during a transmitter transfer,
that transfer is halted. When the stop mode is exited, that particular transmission resumes (if the
exit is the result of a low input to the IRQ pin). Since the previous transmission resumes after an IRQ
interrupt stop mode exit, the user should ensure that the SCI transmitter is in the idle state when the
STOP instruction is executed. If the receiver is receiving data when the STOP instruction is

3-571

I

MC68HC05C4

executed, received data sampling is stopped (baud rate generator stops) and the rest of the data is
lost. For the above reasons, all SCI transactions should be in the idle state when the STOP instruction is executed.

7.2.3 SPI During Stop Mode
When the MCU enters the stop mode, the baud rate generator which drives the SPI shuts down.
This essentially stops all master mode SPI operation, thus the master SPI is unable to transmit or
receive any data. If the STOP instruction is executed during an S PI transfer, that transfer is halted
until the MCU exits the stop mode (provided it is an exit resulting from a logic low on the IRQ pin). If
the stop mode is exited by a reset, then the appropriate controll status bits are cleared and the SPI is
disabled. If the device is in the slave mode when the STOP instruction is executed, the slave S PI will
still operate. It can still accept data and clock information in addition to transmitting its own data
back to a master device.

I

At the end of a possible transmission with a slave SPI in the stop mode, no flags are set until a logic
low IRQ input results in an MCU "wake up". Caution should be observed when operating the SPI
(as a slave) during the stop mode because none of the protection circuitry (write collision, mode
fault, etc.) is active.
It should also be noted that when the MCU enters the stop mode all enabled output drivers (TOO,
TCMP, MISO, MOSI, and SCK ports) remain active and any sourcing currents from these outputs
will be part of the total supply current required by the device.

7.3 WAIT MODE
When the MCU enters the wait mode, the CPU clock is halted. All CPU action is suspended;
however, the timer, SCI, and SPI systems remain active. In fact an interrupt from the timer, SCI, or
SPI (in addition to a logic Iowan the IRQ or RESET pins) causes the processor to exit the wait
mode. Since the three systems mentioned above operate as they do in the normal mode, only a
general discussion of the wait mode is provided below.
The wait mode power consumption depends on how many systems are active. The power consumption will be highest when all the systems (timer, TCMP, SCI, and SPI) are active. The power
consumption will be the least when the SCI and SPI systems are disabled (timer operation cannot
be disabled in the wait mode). If a non-reset exit from the wait mode is performed (i.e., timer
overflow interrupt exit), the state of the remaining systems will be unchanged. If a reset exit from
the wait mode is performed all the systems revert to the disabled reset state.

3-572

MC68HC05C4

SECTION 8
INSTRUCTION SET AND ADDRESSING MODES
8.1 INSTRUCTION SET
The MCU has a set of 62 basic instructions. They can be divided into five different types: register/
memory, read-modify-write, branch, bit manipulation, and control. The following paragraphs
briefly explain each type. All the instructions within a given type are presented in individual tables.
All of the instructions used in the M146805 CMOS Family are used in the MC68HC05C4 MCU, plus
an additional one; the multiply (MUll instruction. This instruction allows for unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high order product is
then stored in the index register and the low order product is stored in the accumulator. A detailed
definition of the MUL instruction is shown below.
Operation:
Description:

Condition
Codes:

X:A--X*A
Multiplies the eight bits in the index register by the eight bits in the accumulator
to obtain a 16-bit unsigned number in the concatenated accumulator and index
register.
H:
I:
N:
Z:

C:
Source
Form(s):

Cleared
Not affected
Not affected
Not affected
Cleared

MUL
Addressing Mode
Inherent

Cycles
11

Bytes
1

Opcode
$42

8.1.1 Register/Memory Instructions
Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the addressing modes. The
operand for the jump unconditional (JMP) and jump to subroutine (JSR) instructions is the program counter. Refer to Table 8-1.
8.1.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify or test its contents, and write the
modified value back to memory or to the register. The test for negative or zero (TST) instruction is
an exception to the read-modify-write sequence since it does not modify the value. Refer to Table
8-2.

3-573

•

•

s:

oen
CO

::t

oo
U1
o
~

Table 8-1. Register/Memory Instructions
Addressing Modes

Function

c...>

cJ,

.......

~

Mnem.

Op
Code

#
Bytes

#
Cycles

Op
Code

Indexed
(No Offset)

Extended

Direct

Immediate

#

#

Bytes

Cycles

Op
Code

#

#

Bytes

Cycles

Op
Code

#
Bytes

Indexed
(S-Bit Offset)

#
Cycles

Op
Code

,

,

Bytes

Cycles

Indexed
(1S-Bit Offset)

,

Op
Code

Bytes

#
Cycles

Load A from Memory

LDA

A6

2

2

B6

2

3

C6

3

4

F6

1

3

E6

2

4

D6

3

5

Load X from Memory

LDX

AE

2

2

BE

2

3

CE

3

4

FE

1

3

EE

2

4

DE

3

5

Store A

In

Memory

STA

-

-

-

B7

2

4

C7

3

5

F7

1

4

E7

2

5

D7

3

6

Store X

In

Memory

STX

-

-

-

BF

2

4

CF

3

5

FF

1

4

EF

2

5

DF

3

6

Add Memory to A
Add Memory and
Carry to A

ADD

AB

2

2

BB

2

3

CB

3

4

FB

1

3

EB

2

4

DB

3

5

ADC

A9

2

2

B9

2

3

C9

3

4

F9

1

3

E9

2

4

D9

3

5

Subtract Memory

SUB

AO

2

2

BO

2

3

CO

3

4

FO

1

3

EO

2

4

DO

3

5
5

Subtract Memory from
A with Borrow

SBC

A2

2

2

B2

2

3

C2

3

4

F2

1

3

E2

2

4

D2

3

AN D Memory to A

AND

A4

2

2

B4

2

3

C4

3

4

F4

1

3

E4

2

4

D4

3

5

OR Memory With A

ORA

AA

2

2

BA

2

3

CA

3

4

FA

1

3

EA

2

4

DA

3

5

Exclusive OR Memory
With A

EOR

A8

2

2

B8

2

3

C8

3

4

F8

1

3

E8

2

4

D8

3

5

CMP

A1

2

2

B1

2

3

C1

3

4

F1

1

3

E1

2

4

D1

3

5

CPX

A3

2

2

B3

2

3

C3

3

4

F3

1

3

E3

2

4

D3

3

5

BIT

Arithmetic Compare A
with Memory
Arithmetic Compare X
with Memory
Bit Test Memory with
A I Logical Compare)

A5

2

2

B5

2

3

C5

3

4

F5

1

3

E5

2

4

D5

3

5

Jump Unconditional

JMP

-

-

-

BC

2

2

CC

3

3

FC

1

2

EC

2

3

DC

4

Jump to Subroutine

JSR

-

-

-

BD

2

5

CD

3

6

FD

1

5

ED

2

6

DD

3
3

-

,7

.

s:

o
en
00

:::I

oo

(J1

o
~
Table 8-2. Read-Modify-Write Instructions
Addressing Modes
Inherent (X)

Inherent (A)

Function

Mnemonic

Op
Code

#
Bytes

#
Cycles

Indexed
(No Offset)

Direct

Op
Code

#
Bytes

#
Cycles

Op
Code

#
Bytes

#
Cycles

Indexed
(S-Bit Offset)

Op
Code

#
Bytes

#
Cycles

Op
Code

#
Bytes

#
Cycles

Increment

INC

4C

1

3

5C

1

3

3C

2

5

7C

1

5

6C

2

6

Decrement

DEC

4A

1

3

5A

1

3

3A

2

5

7A

1

5

6A

2

6

w
cJ,

Clear

CLR

4F

1

3

5F

1

3

3F

2

5

7F

1

5

6F

2

6

Complement

COM

43

1

3

53

1

3

33

2

5

73

1

5

63

2

6

........

Negate
12'5 Complement)

NEG

40

1

3

50

1

3

30

2

5

70

1

5

60

2

6

Rotate Left Thru Carry

ROL

49

1

3

59

1

3

39

2

5

79

1

5

69

2

6

Rotate Right Thru
Carry

ROR

46

1

3

56

1

3

36

2

5

76

1

5

66

2

6

Logical Shift Left

LSL

1

3

58

1

3

38

2

5

78

1

5

68

2

6

Logical Shift Right

LSR

48
44

1

3

54

1

3

34

2

5

74

1

5

2

6

Arithmetic Shift Right

ASR

47

1

3

57

1

3

37

2

5

77

1

5

64
67

2

6

TST

4D

1

3

50

1

3

3D

2

4

7D

1

4

6D

2

MUL

42

1

11-

(]I

Test for Negative
or Zero
Multiply
-

-

-

- -

- -

L

_____

~--

--

-

-

-

-

-

-

-

5

-

--

-

MC68HC05C4

8.1.3 Branch Instructions
Most branch instructions test the state of the condition code register and if certain criteria are met,
a branch is executed. This adds an offset between - 127 and + 128 to the current program counter.
Refer to Table 8-3.
Table 8-3. Branch Instructions
Relative Addressing Mode
Mnemonic

Op
Code

#

I

Bytes

Cycles

Branch Always

BRA

20

2

3

Branch Never

BRN

21

2

3

Branch IFF Higher

BHI

22

2

3

Branch IFF Lower or Same

BLS

23

2

3

Branch IFF Carry Clear

BCC

24

2

3

IBHS)

24

2

3

BCS

25

2

3

IBLO)

25

2

3

Branch IFF Not Equal

BNE

26

2

3

Branch I FF Equal

BEQ

27

2

3

Branch IFF Half Carry Clear

BHCC

28

2

3

Branch IFF Half Carry Set

Function

I

IBranch IFF Higher or Same)
Branch IFF Carry Set
IBranch IFF Lower)

BHCS

29

2

3

Branch IFF Plus

BPL

2A

2

Branch IFF Minus

BMI

2B

2

3
3

Branch IFF Interrupt Mask Bit is Clear

BMC

2C

2

3

Branch IFF Interrupt Mask Bit is Set

BMS

2D

2

BIL

2E

2

BIH

2F

2

3
3
3

BSR

AD

2

6

Branch IFF Interrupt Line is Low
Branch IFF Interrupt Line

IS

High

Branch to Subroutine

8.1.4 Bit Manipulation Instructions
The MCU is capable of setting or clearing any bit which resides in the first 256 bytes of the memory
space except for ROM, port D data location ($03), serial peripheral status register ($OB), serial communications status register ($10), timer status register ($13), and timer input capture register
($14-$15). All port registers, port DDRs, timer, two serial systems, on-chip RAM, and 48 bytes of
ROM reside in the first 256 bytes (page zero). An additional feature allows the software to test and
branch on the state of any bit within the first 256 locations. The bit set, bit clear, and bit test and
branch functions are all implemented with a single instruction. For the test and branch instructions,
the value of the bit tested is automatically placed in the carry bit of the condition code register.
Refer to Table 8-4.
Table 8-4. Bit Manipulation Instructions
Addressing Modes
Bit Set/ Clear
Mnemonic

Function
Branch I FF Bit n

IS

Set

BRSET n In=O

Branch IFF Bit n

IS

Clear

8RCLR n In=O

Op
Code

71
71

Bit Test and Branch

#

#

Bytes

Cycles

Op
Code

#

#

Bytes

Cycles
5

-

-

-

2-n

3

-

-

-

01 + 2-n

3

5

Set Bit n

BSETnln=O

7)

10 + 2-n

2

5

-

-

-

Clear Bit n

BCLRnln=O

7)

11 + 2-n

2

5

-

-

-

3-576

MC68HC05C4

8.1.5 Control Instructions

These instructions are register reference instructions and are used to control processor operation
during program execution. Refer to Table 8-5.
Table 8-5. Control Instructions
Inherent
Function

Mnemonic

Op

#

#

Code

Bytes

Cycles

Set Carry Bit

SEC
CLC

99
98

1

Clear Carry Bit
Set Interrupt Mask Bit

SEI

9B

1

Clear Interrupt Mask Bit

9A

1

Software Interrupt

CLI
SWI

2
2
2
2
2
2

83

1

10

Return from Subroutine

RTS

81

1

Return from Interrupt

RTI

80

1

6
9

Reset Stack Pointer

RSP

9C

1

NOP

9D

1

STOP
WAIT

8E

1
1

Transfer A to X

TAX

97

1

Transfer X to A

TXA

9F

1

No-Operation
Stop
Wait

8F

1

2
2
2
2

8.1.6 Alphabetical Listing

The complete instruction set is given in alphabetical order in Table 8-6.
8.1.7 Opcode Map

Table 8-7 is an opcode map for the instructions used on the MCU.
8.2 ADDRESSING MODES

The MCU uses ten different addressing modes to provide the programmer with an opportunity to
optimize the code to all situations. The various indexed addressing modes make it possible to locate
data tables, code conversion tables, and scaling tables anywhere in the memory space. Short
indexed accesses are single byte instructions, while the longest instructions (three bytes) permit accessing tables throughout memory. Short absolute (direct) and long absolute (extended) addressing are also included. One and two byte direct addressing instructions access all data bytes in most
applications. Extended addressing permits jump instructions to reach all memory. Table 8-7 shows
the addressing modes for each instruction, with the effects each instruction has on the condition
code register.
The term "effective address" (EA) is used in describing the various addressing modes, and is
defined as the byte address to or from which the argument for an instruction is fetched or stored.
The ten addressing modes of the processor are described below. Parentheses are used to indicate
"contents of" the location or register referred to; e.g., (PC) indicates the contents of the location
pointed to by the PC. An arrow indicates "is replaced by", and a colon indicates concatenation of
two bytes. For additional details and graphical illustrations, refer to the M6805 HMOSIM146805
CMOS Family Microcomputer! Microprocessor User's Manual.

3-577

II

•

!:
o
en
CD

%

o
o

o
en

Table 8-6. Instruction Set
Condition Codes

Addressing Modes
Mnemonic

~

Us
.......,
ex>

ADC
ADD
AND
ASL
ASR
BCC
BCLR
BCS
BEG
BHCC
BHCS
BHI
BHS
BIH
BIL
BIT
BLO
BLS
BMC
BMI
BMS
BNE
BPL
BRA
BRN
BRCLR
BRSET
BSET
BSR
CLC
Cli
CLR
CMP

Inherent

Immediate

Direct

Extended

X
X
X

X
X
X
X
X

X

X
X

Relative

X

X

Indexed
(No Offset)

Indexed
(8 Bits)

Indexed
(16 Bits)

X
X
X
X
X

X
X
X
X
X

X
X
X

Bit

Test & H

Clear

Branch

N Z C

A

A A A
/I.

/I.
•

X
X
X
X
X
X
X
X
X
X

X

X

X

A

X

X
X
X
X
X
X
X
X
X

••
J
•••
•••
•
••.- •A
•• •0
•
•
0 A •
A
i

o
X

I

j

I

X

X

,

I

X

X
X

••
••
••
•
••
•A

j

X
X

X
X
X

I

/I.

•

/I.
A
A
A A A
A A A

••
••
•••
•••

X

X

~

Bit

Set/

X
X

X
X

X

•

•

1

A

3:

o

0)

CO

:r::

o
C1I
o

o

~

w

cit

-..J
<0

COM
CPX
DEC
EOR
INC
JMP
JSR
LOA
LOX
LSL
LSR
MUL
NEG
NOP
ORA
ROL
ROR
RSP
RTI
RTS
SBC
SEC
SEI
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT

X
X
X
X
X

X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X

•
•
•
•
•

•
•
•
•
•

1\
1\
1\
1\
1\

•
•
•

•
•
•

1\
1\
1\

•

1\

1\
1\
1\
1\
1\

X

X
X
X
X
X
X
X

X

X
X
X

X
X
X

X

X

X

X

X

X

X

X

X

X

X
X

X
X

X
X

X
X

X
X

X

X

X
X
X

X

X

X
X
X
X
X
X
X

Condition Code Symbols:
H
Half Carry (From Bit 3)
Interrupt Mask
N
Negate (Sign Bit)
Z
Zero
C
Carry/Borrow

X

1\

•

•

•

•

•

?

?

•

X
X

Test and Set if True Cleared Otherwise
Not Affected
Load CC Register From Stack
Cleared
Set

•

••
•••••
• • • • ••
•
••o
••••
•••••
•
••
• • •7 • •
••••
•1 • • 1
•••
o • • •
••
1
• • -.-•
•• ••
•o •• •• •••
1\
1\
1\
1\
1\

1\
1\
0
1\

1\
1\
1\

1\
1\

0
X

1
1\

1\

II
1\

?

7

1\

1\

II

.1\11

1\
•. 1 1\
\1\

1\

•

1\

1\

III
3:

o

Q)

Table 8-7. MC68HC05C4 HCMOS Instruction Set Opcode Map
Bit Manipulation
8T8
85l

~i

rk

O,~,

BRCL
3

0010

3

0011

4

o~o
7
0111

1~
9

1001

0.

1~0

o

B
1011

~,

5

0100

2

ex>

..

ri,o

:l:

5
BRSE
J1B
i3
5

ircL:le
5
i.aBRSEJta
5
rCL::a
5
BRSE
i3
Jie
5
BRCLR5
3
BTB
_5

2 BCL~~c
5

2 8SE~~c
5
BCLR5
2
BSC
5

foe

,g,

5

i3BRCL:~B

5

F
1111

r£"

O~

5

5
BRSE
i3
JIB
5
BRCLR7
3
BTB

2 BCL~~c
5
2

8SE~~c

2

BHIREI
3
BLS
REL
3
BCC
REL
3
BCS
REL
3
BNEREL
3
BEO
Rll
3

BHC~ll

8CLR7
BSC

INH
8
1000

IX

O~O

O~,

Ol"

3
6
NEG
~ NEG
1
INH
IX1

5

1

NEG

IX

RTI

BHC~EL

3
2 BPL
REL
3
BMI
2
REL
3
2 BMC
REL
3
2

BM~EL

3
2

BIL

2

81H

1

IMM

OIR

9

A

B

1001

1

9
INH

1

RTS
INH

1.2.
2

2 ROR
OIR

1

5

2 ASR
DIR

1

5

2 LSL

DIR

1

5

2 ROL
DIR

1

5

2 DEC
DIR

1

3
RORA
INH
3
ASRA
INH
3
LSLA
INH
3
ROLA
INH
3
DECA
INH

3
COM X
1
INH
3
LSRX
1
INri

2
6

2 COM

IX1

1

COM

6

2

LSR

IXI

5

10

IX

SWI
1
INH

2

5

1

LSR
IX

2
2

1
1
1
1
1

3
RORX
INH
3
ASRX
INH
3
LSLX
INH
3
ROLX
INH
3
DECX
INH

6

2 ROR

IXl

5

1

ROR

6

2 ASR

IXI

1

6

2 LSL

IX1

1

IXI

2

IX1

IX
IX
5

1

ROL

6

DEC

2

5

LSL

6

2 ROL

IX

1

IX

3

DIR
4
TST
2
DIR

INCA
1
INH
3
TSTA
1
INH

INCX
INH
1

INC

2

2

CLR
DIR

1

CLRA
INH

2

INC

2

TST

3
1

CLRX
INH

IX1

5

1

INC
IX
4

5

3

TSTX
1
INH

3

5

6

IXl

TST
1

IX

5

6

2

CLR

IXl

1

CLR

IX

2
STOP
INH
1
2
WAIT
1
INH

A

X
IMM
DIR
EXT

REL
BSC
BTB
IX
IXl
IX2

Inherent
Accumulator
Index Register
Immediate
Direct
Extended
Relative
Bit Set/Clear
Bit Test and Branch
Indexed (No Offset)
Indexed, 1 Byte (S-Bit) Offset
Indexed, 2 Byte (l6-Bit) Offset

4

AND
EXT
EXT
4
LDA
EXT

IXI

2

CMP
IXI

4
4

2

SBC

IXI
IXI

2

BIT

3

LDA
3

IX2
5

2

IX2
5

2

IX2

AND

IXI
4

BIT IX
4

2

LDA

IXI
5

2
2 EOR
IMM
2
ADC
IMM
2
ORA'
2
IMM

ORA .j
DIR
2

ORA 4
3
EXT

ORA'
IX2
3

ORA 4
IXI
2

ADD 1
IMM
2

ADD j
DIR
2
2
JMP
DIR
2

ADD
EXT
3
3
JMP
EXT
3

ADD'
IX2
3
4
JMP
IX2
3

ADD •
IXI
2

JSR 5
DIR
2

JSR 6
EXT
3

JSR
3

LDX 3
DIR
2
4
STX
DIR
2

LDX 4
EXT
3

LOX 5
IX2
3

JSR 6
IXI
2
4
LOX
IXI
2

1

INH
2
RSP
1
INH
2
NOP
1
INH

6

BSR
2
REL
2
LDX
IMM
2

2
1

TXA
INH

-

4

7

IX2

2
2

STA
EOR

IXl
4

STX '
EXT

2

JMP
2

STX
3

IX2

0001

SBC 3
1
IX
CPX
1

IXI
IXI

j

IXI

2

STX '
IXI

~

IX
3

1

IX
3
BIT IX
3
LOA
1
IX

~

1

2

0010

3

.j

AND

0011

01~
5
0101

6

0110

4

STA
1
1

4

ADC

6

3

~

4

5

3

1:',
SUB 3
1
IX
3
CMP
I
IX

4

CPX

AND

4

BIT

2

STA 6
IX2
3
5
EOR
3
IX2
5
ADC
IX2
3

Abbreviation. for Addrea Modes
INH

CPX 5
3
IX2

4

STA '
EXT
3
4
EOR
EXT
3
4
ADC
EXT
3

1

3

SBC 5
IX2
3

SUB

4

SEI
5

SUB 5
3
IX?
5
CMP
IX2
3

STA
DIR
2
3
EOR
DIR
2
3
ADC
DIR
2

2

IX

SUB 4
EXT
4
CMP
EXT
4
SBC
EXT
4
CPX
EXT

2

SEC
1
INH
2
CLI
1
INH

5

DEC

1101

1

SUB 3
SUB 2
IMM .2
...DJR 3
2
3
CMP
CMP
IMM 2
DIR 3
2
3
SBC
SBC
IMM 2
DIR 3
2
3
CPX
CPX
IMM 2
DIR 3
2
3
AND
AND
IMM 2
DIR 3
2
J
BIT
BIT
IMM 2
DIR 3
2
3
LDA
LDA
IMM 2
DIR 3

TAX
1
INH
2
CLC
'NH

5

ASR

J:

oo
c.n
o

IX

IX'
E
1110

0

fro

1011

1010

MUL

INH
3
COMA
1
INH
3
LSRA
1
INH

5

REL
3
REL

INH

11
5
2 COM
DIR
5
2 LSR
DTR

Q)
Register /Memory
1X2
EX"

Control

6

3

5

2

3
NEG
1
INH

2 BRNREL
3

2 BSE~lc 2
5
2 BCL~1c 2
5
2 BSE~~c 2
5
2 BCL~~c 2
5
2 BSE~lc 2
5
2 BCL~~c 2.
5
2 BSE1~c 2.
5

2 BSE~~c

11~0

INH

Read/ Modify/Write
INH
IX'

3

5

2 BCL~~c
5

3BRSEJ~B

1

3

,5

OIR

~BRSEJ~ .2 BSE~c ~ BR~n .2 NEGOJR
5
BRCLRO
3
BTB
5
BRSE
3
JiB
5
BRCL
3
:T'B
5
BRSE
3
J1B

1

0001

(,.)

~

Branch
REL

IX
3
EOR
ADC

1
ORA
1

IX

8
1000

9

.j

IX

1001

j

A
1010

IX
ADD

7
0111

j

IX

8
1011

JMP 2
1
IX

C
1100

1

JSR
1

5

0

IX

1101

LOX 3
1
IX

E
1110

STX 4
1
IX

F
1111

I

I

LEGEND
::> Opcode in Hexadecimal

II(

Mnemonic
Bytes

~..
1

Cycles _ _ _ _ _ _..1

~

~.x.

l

~

Opcode in Binary

lLUJ ~

' - - - - - - - - - - Address Mode

MC68HC05C4

8.2.1 Inherent
I n inherent instructions, all the information necessary to execute the instruction is contained in the
opcode. Operations specifying only the index register or accumulator, and no other arguments, are
included in this mode.
8.2.2 Immediate
In immediate addressing, the operand is contained in the byte immediately following the opcode.
Immediate addressing is used to access constants which do not change during program execution
(e. g., a constant used to initialize a loop counter).
EA= PC+ 1; PC--PC+2
8.2.3 Direct
In the direct addressing mode, the effective address of the argument is contained in a single byte
following the opcode byte. Direct addressing allows the user to directly address the lowest 256
bytes in memory with a single two byte instruction. This includes all on-chip RAM and I/O registers,
and 128 bytes of on-chip ROM. Direct addressing is efficient in both memory and time.
EA = (PC + 1); PC.... PC + 2
Address Bus High---O; Address Bus Low---(PC+ 1)
8.2.4 Extended
I n the extended addressing mode, the effective address of the argument is contained in the two
bytes following the opcode. Instructions with extended addressing modes are capable of referencing arguments anywhere in memory with a single three-byte instruction. When using the Motorola
assembler, the user need not specify whether an instruction uses direct or extended addressing.
The assembler automatically selects the most efficient addressing mode.
EA= (PC+ 1):(PC+2); PC---PC+3
Address Bus High---(PC+ 1); Address Bus Low---(PC+2)
8.2.5 Indexed, No Offset
In the indexed, no offset addressing mode, the effective address of the argument is contained in the
8-bit index register. Thus, this addressing mode can access the first 256 memory locations. These
instructions are only one byte long. This mode is used to move a pointer through a table or to
address a frequently referenced RAM or I/O location.
EA= X; PC---PC+ 1
Address Bus High---O; Address Bus Low---X
8.2.6 Indexed, 8-Bit Offset
Here the EA is obtained by adding the contents of the byte following the opcode to that of the index
register; therefore, the operand is located anywhere within the lowest 511 memory locations. For
example, this mode of addressing is useful for selecting the mth element in a n element table. All instructions are two bytes. The content of the index register (X) is not changed. The content of

3-581

I

MC68HC05C4

(PC + 1) is an unsigned 8-bit integer. One byte offset indexing permits look-up tables to be easily accessed in either RAM or ROM.
EA = X + (PC + 1); PC-- PC + 2
Address Bus High ..... K; Address Bus Low ..... X + (PC+ 1)
where:
K = The carry from the addition of X + (PC + 1)

8.2.7 Indexed, 16-Bit Offset

I

In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the two unsigned bytes following the opcode. This addressing
mode can be used in a manner similar to indexed 8-bit offset except that this three byte instruction
allows tables to be anywhere in memory (e.g., jump tables in ROM). As with direct and extended,
the M6805 assembler determines the most efficient form of indexed offset; 8- or 16-bit. The content
of the index register is not changed.
EA=X+[(PC+1):(PC+2))l; PC--PC+3
Address Bus High ..... (PC + 1) + K;
Address Bus Low ..... X + (PC + 2)
where:
K = The carry from the addition of X + (PC + 2)

8.2.8 Relative
Relative addressing is only used in branch instructions. In relative addressing, the content of the
8-bit signed byte following the opcode (the offset) is added to the PC if and only if the branch condition is true. Otherwise, control proceeds to the next instruction. The span of relative ade'fressing is
limited to the range of - 126 to + 129 bytes from the branch instruction opcode location. The
Motorola assembler calculates the proper offset and checks to see if it is within the span of the
branch.
EA = PC + 2 + (PC + 1); PC-- EA if branch taken;
otherwise, EA = PC-- PC + 2

8.2.9 Bit Setl Clear
Direct addressing and bit addressing are combined in instructions which set and clear individual
memory and 1/0 bits. In the bit set and clear instructions, the byte is specified as a direct address in
the location following the opcode. The first 256 addressable locations are thus accessed. The bit to
be modified within that byte is specified in the first three bits of the opcode. The bit set and clear instructions occupy two bytes, one for the opcode (including the bit number) and the other to address the byte which contains the bit of interest.
EA= (PC+ 1); PC ..... PC+2
Address Bus High ..... O; Address Bus Low..... ( PC + 1)

8.2.10 Bit Test and Branch
Bit test and branch is a combination of direct addressing, bit set! clear addressing, and relative
addressing. The actual bit to be tested, within the byte, is specified within the low order nibble of
the opcode. The address of the data byte to be tested is located via a direct address in the location
following the opcode byte (EA 1). The signed relative 8-bit offset is in the third byte (EA2) and is

3-582

MC68HC05C4

added to the PC if the specified bit is set or cleared in the specified memory location. This single
three byte instruction allows the program to branch based on the condition of any bit in the first 256
locations of memory.
EA1 = (PC+ 1)
Address Bus High--O; Address Bus Low--(PC+ 1)
EA2= PC+3+ (PC+2); PC--EA2 if branch taken;
otherwise, PC-- PC + 3

II

3·583

MC68HC05C4

SECTION 9
ELECTRICAL SPECIFICATIONS
9.1 INTRODUCTION
This section contains the electrical specifications and associated timing information for the
MC68HC05C4.

9.2 MAXIMUM RATINGS (Voltages Referenced to VSS)
Ratings

Symbol

Value

VDD

-0.5 to + 1.0

V

Vin
I

VSS-0.5 to VDD+0.5

V

25

TA
Tstg

- 55 to + 125

mA
DC

-65 to + 150

DC

Supply Voltage
Input Voltage

I

Current Drain Per Pin Excluding VDD and VSS
Operating Temperature Range
Storage Temperature Range

Unit

9.3 THERMAL CHARACTERISTICS
Characteristics
Thermal Resistance
Ceramic
Plastic
Chip Carrier

VOO=4.5 V
Pins
PAO-PA1,
PBO-PB1,
PCO-PC1,
PD6
PD1-PD4

Rl
3.26 kG

R2
2.38 kG

C
50 pF

1.9 kG

226 kG

200 pF

Symbol

Value

Unit

(JJA

50
100
100

DC/W

This device contains circuitry to
protect the inputs against damage
due to high static voltages of electric fields; however, it is advised
that normal precautions be taken
to avoid application of any voltage
higher than maximum rated
voltages to this high impedance
circuit. For proper operation it is
recommended that Vin and V out
be constrained to the range VSS:s
(Vin or Voutl:S VDD· Reliability of
operation is enhanced if unused inputs except OSC2 are connected
to an appropriate logic voltage
level (e.g., either VSS or VDDl.

VDD
R2
(See Tablel
Test
Point C J - - - - -.....- - - - .

VOO=30V
Pins
PAO-PA1,
PBO-PB1,
PCO-PC1,
PD6
PD1-PD4

Rl
10.91 kG

R2
6.32 kG

C
50 pF

6 kG

6 kG

200 pF

Rl
(See Tablel

Figure 9-1. Equivalent Test Load

3-584

MC68HC05C4

9.4 POWER CONSIDERATIONS
The average chip-junction temperature, T J, in °c can be obtained from:
TJ=TA+(PDeOJA)
Where:
T A = Ambient Temperature, °c
OJA = Package Thermal Resistance, Junction-to-Ambient, °C/W
PD= PINT+ PliO
PINT = ICC x VCe. Watts - Chip Internal Power
PliO = Power Dissipation on Input and Output Pins - User Determined
For most applications PI/O< PINT and can be neglected.

(1)

An approximate relationship between PD and T J (if PliO is neglected) IS:
PD= K...;-. (TJ+273°C)
(2)
Solving equations 1 and 2 for K gives:
K=PD e (TA+273°C)+OJA e PD 2
(3)
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by
measuring PD (at equilibrium) for a known T A. Using this value of K the values of Po and T J can be
obtained by solving equations (1) and (2) iteratively for any value of T A.

9.5 DC ELECTRICAL CHARACTERISTICS (VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc,
T A = - 55°C to + 125°C unless otherwise noted)
Typ

Max

Unit

VOL
VOH

-

-

0.1

VOO-01

-

-

V
V

Output High Voltage
(ILoad=0.8 mAl PAO-PA7, PBO-PB7, PCO-PC7, TCMP
(ILoad=1.6 mAl P01-PD4

VOH
VOH

VOO-O.8
VOO-O.8

-

-

-

-

V
V

Output Low Voltage
(ILoad= 1.6 mAl PAO-PA7, PBO-PB7, PCO-PC7, P01-P04, TCMP

VOL

-

-

0.4

V

Input High Voltage
PAO-PA7, PBO-PB7, PCO-PC7, POO-P05, P07, TCAP, iRQ, RESET, OSC1

VIH

0. 7xV OO

-

VOO

V

Input Low Voltage
PAO-PA7, PBO-PB7, PCO-PC7, POO-P05, P07, TCAP, IRQ, RESET, OSC1

VIL

VSS

-

0.2x VOO

V

Total Supply Current (CL = 50 pF on Ports, no dc Loads, tcyc= 500 ns,
(VIL =0,2 V, VIH=VOO-O.2 VI
RUN
WAIT (See Notel
STOP (See Notel

100
100
100

-

5
1.5
1.0

TBO
TBO
TBO

mA
mA
p.A

I/O Ports Hi-Z Leakage Current
PAO-PA7, PBO-PB7, PCO-PC7, P01-P04

IlL

-

-

± 10

p.A

Input Current
RESET, IRQ, TCAP, OSC1, POO, P05, P07

lin

-

-

±1

p.A

Capacitance
Ports (as input or outputl
RESET, TR('i', TCAP, OSC1, POO-P05, PD7

Cout
Cin

-

-

-

-

12
8

pF
pF

Characteristic

Symbol

Output Voltage, ILoad $10.0 p.A

NOTE: Measured under the following conditions:
1. All ports are configured as input, VIL =0.2 V, VIH=VOO-O.2 V.
2 No load on TCMP, CL = 20 pF on OSC2.
3. OSC1 is a square wave with VIL =0.2 V, VIH=VOO-O.2 V
4. TE= RE= SPE=O

3-585

Min

-

I

MC68HC05C4

TBO

Figure 9-2. Typical Operating Current vs Internal Frequency

I

9.6 DC ELECTRICAL CHARACTERISTICS (VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc,
T A = - 55°C to 125°C unless otherwise noted)
Symbol

Min

Typ

Max

Unit

VOL
VOH

-

-

0.1

VOO-01

-

-

V
V

Output High Voltage
(ILoad=0.2 mAl PAO-PA7, PBO-PB7, PCO-PC7, TCMP
(ILoad=OA mAl P01-P04

VOH
VOH

VOO-03
VOO-03

-

-

-

-

V
V

Output Low Voltage
(ILoad=OA mAl PAO-PA7, PBO-PB7, PCO-PC7, P01-P04, TCMP

VOL

-

-

0.3

V

Input High Voltage
PAO-PA7, PBO-PB7, PCO-PC7, POO-P05, P07, TCAP,

Characteristic
Output Voltage, I Load oS 10.0 /lA

TAO,

RESET, OSC1

VIH

0. 7xV OO

-

VOO

V

Input Low Voltage
PAO-PA7, PBO-PB7, PCO-PC7, POO-P05, P07, TCAP, IRQ, RESET, OSC1

VIL

VSS

-

0.2x VOO

V

Total Supply Current (CL = 50 pF on Ports, no dc Loads, tcyc= 1000 ns,
(VIL = 0.2 V, VIH = VOO - 02 V)
RUN
WAIT (See Note)
STOP (See Note)

100
100
100

-

-

<4
<1.5
<30

TBO
TBO
TBO

mA
mA
/lA

-

1/0 Ports Hi-Z Leakage Current
IlL

-

<1

±10

/lA

Input Current
RESET, TAO, TCAP, OSC1, POO, P05, P07

lin

-

<1

±1

/lA

Capacitance
Ports (as input or output)
RESET, IRQ, TCAP, OSC1, POO-P05, P07

Cout
Cin

-

-

12

-

-

8

pF
pF

PAO-PA7, PBO-PB7, PCO-PC7, P01-P04

NOTE: Measured under the following conditions:
1 All ports are configured as input, VIL = 0.2 V, VIH = VOO - 02 V.
2. No load on TCMP, CL = 20 pF on OSC2.
3 OSC1 isa square wave with VIL=0.2V, VIH=VOO-0.2V.
4. TE= RE= SPE=O

3-586

MC68HC05C4

9.7 CONTROL TIMING (VDD = 5.0 Vdc

± 10%,

VSS = 0 Vdc, T A =

-

55 to

+ 125°C)

Symbol

Min

Frequency of Operation
Crystal Option
External Clock Option

fosc
fosc

dc

Internal Operating Frequency
Crystal (fosc -;- 2)
External Clock (fosc -;- 2)

fop
fop

dc

tcyc

480

Characteristic

Cycle Time (See Figure 3-1 )
Crystal Oscillator Startup Time (See Figure 3-1)

toxOV

Stop Recovery Startup Time (Crystal Oscillator) (See Figure 9-3)
RESET Pulse Width (See Figure 3-2)
Timer
Resolution* *
Input Capture Pulse Width (See Figure 9-4)
Input Capture Pulse Period (See Figure 9-4)
Interrupt Pulse Width Low (Edge-Triggered) (See Figure 3-4)

tlLCH

4.2
4.2

MHz
MHz

2.1
2.1

MHz
MHz

-

ns

-

100

ms

-

100

ms

1.5

-

tcyc

tRESL
tTH, tTL
tTLTL

4.0
125

-

tcyc
ns

tlLlL

OSC1 Pulse Width

-

Unit

tRL

tlLlH

Interrupt Pulse Period (See Figure 3-4)

-

Max

tOH, tOL

***
125
*
90

-

tcyc
ns
tCYC
ns

*The minimum period tlLlL should not be less than the number of cycle times it takes to execute the interrupt service routine plus
21 tcyc.
* * Since a 2-bit prescaler in the timer must count four internal cycles (t cyc ), this is the limiting minimum factor in determining the timer
resolution.
* * * The minimum period tTL TL should not be less than the number of cycle times it takes to execute the capture interrupt service
routine plus 24 tcyc.

ose1

1

~lllllllllli ~ 111111111/;
tRL

IR02
~----- tlLCH -----~~r-- 4064·t cyC

IR03

Internal
Clock
Internal

Add~~:

YXXXXIXX
RESET or Interrupt
Vector Fetch

NOTES:
1. Represents the internal gating of the OSCl pin
2. iRO pin edge-sensitive mask option.
3. IRO pin level and edge-sensitive mask option.
4. RESET vector address shown for timing example.

Figure 9-3. Stop Recovery Timing Diagram

3-587

I

MC68HC05C4

9.8 CONTROL TIMING (VOO = 3.0 Vdc

± 10%, VSS = 0 Vdc, T A = - 55 to + 125°C)
Symbol

Min

Max

Unit

Frequency of Operation
Crystal Option
External Clock Option

Characteristic

lose
fosc

dc

2.0
2.0

MHz
MHz

Internal Operating Frequency
Crystal (Iosc -:- 2)
External Clock (Iosc -:- 2)

fop
fop

-

dc

1.0
1.0

MHz
MHz

tcyc

1000

-

ns

tOXOV

100

ms

tilCH

-

100

ms

tRl

1.5

-

tcyc

tRESl
tTH, tTL
tTLTl

4.0
250

-

tcyc
ns

***
250

-

Cycle Time (See Figure 3-1)
Crystal Oscillator Startup Time (See Figure 3-1)
Stop Recovery Startup Time (Crystal Oscillator) (See Figure 9-3)
RESET Pulse Width- Excluding Power-Up (See Figure 3-1)
Timer
Resolution* *
Input Capture Pulse Width (See Figure 9-4)
Input Capture Pulse Period (See Figure 9-4)

I

Interrupt Pulse Width low (Edge-Triggered) (See Figure 3-4)

tlLlH

Interrupt Pulse Period (See Figure 3-4)

tlLll

OSCl Pulse Width

tOH, tOl

*
200

-

-

tcyc
ns

-

tcyc
ns

*The minimum period tlLll should not be less than the number of cycle times it takes to execute the interrupt service routine plus
21 tcyc.
* * Since a 2-bit prescaler in the timer must count lour internal cycles (t cyc ), this is the limiting minimum factor in determining the timer
resolution.
* * * The minimum period tTL Tl should not be less than the number of cycle times it takes to execute the capture interrupt service
routine plus 24 tcyc.

External
Signal
(TCAP
Pin 37)

Figure 9-4. Timer Relationships

3-588

MC68HC05C4

9.9 SERIAL PERIPHERAL INTERFACE (SPI) TIMING (Figure 9-5)

(VOO=5.0Vdc ±10%, VSS=OVdc, TA=-55to +125°)
Num.

1

2

3

4

5

6

Symbol

Min

Max

Unit

Operating Frequency
Master
Slave

fop(m)
fop(s)

de
de

105
2.1

MHz
MHz

Enable Lead Time
Master
Slave (CPHA=O)
Slave (CPHA= 1)

tlead(m)
tlead(SO)
tl ea d(Sl)

240
100

Enable Lag Time
Master
Slave (CPHA=Ol
Slave (CPHA= 1)

tlag(m)
tlag(SO)
tl ag (Sl)

0.0
125

-

Clock (SCK) High Time
Master
Slave

tw(SCKH)m
tw(SCKH)s

TBD
TBD

-

Clock (SCK) Low Time
Master
Slave

tw(SCKLlm
tw(SCKLls

TBD
TBD

-

Data Setup Time (Inputs)
Master
Slave

tsu(m)
tsu(s)

100
100

-

Data Hold Time (Inputs)
Master
Slave

th(m)
this)

100
100

-

ta

-

TBO

ns

tdis

-

TBD

ns

tv(B)m
tv(B)s

TBD

-

-

200

ns
ns

tv(A)

TBD

-

ns

Characteristic

7

Access Time
Slave

8

Disable Time (Hold Time to High-Impedance State)
Slave

9

Data Valid
Master (Before Capture Edge)
Slave (After Enable Edge) * *

*

*

-

-

-

-

-

-

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

10

Data Valid
Master (After Capture Edge)

11

Rise Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, MISO)
SPI Inputs (SCK, MOSI, MISO, 55)

trm
trs

-

100
2.0

p's

Fall Time (70% VDD to 20% VOO, CL = 200 pF)
SPI Outputs (SCK, MOSI, MISO)
SPI Inputs (SCK, MOSI, MISO, 55)

tfm
tfs

-

100
2.0

p'S

tho(m)
tho(s)

0
0

-

12

13

Output Data Hold (After Enable Edge)
Master
Slave

* Signal production depends on software.
* * Assumes 200 pF load on all SPI pins.

3-589

-

ns

ns

ns
ns

I

MC68HC05C4

9.10 SERIAL PERIPHERAL INTERFACE (SPI) TIMING (Figure 9-5)

(VDD=3.3 Vdc ±10%, VSS=O Vdc, TA= -55 to
Num.

Symbol

Min

Max

Unit

fop(m)
fop(s)

dc
dc

0.5
1.0

MHz
MHz

Enable Lead Time
Master
Slave (CPHA=O)
Slave (CPHA= 1)

tlead(m)
tlead(SO)
tl ea d(Sl)

500

*

-

200

-

ns
ns
ns

Enable Lag Time
Master
Slave (CPHA = 0)
Slave (CPHA= 1)

tlag(m)
tlag(SO)
tl ag (Sl)

*

-

0.0
250

-

ns
ns
ns

Clock (SCK) High Time
Master
Slave

tw(SCKH)m
tw(SCKH)s

TBD
TBD

-

P.s
ns

Clock (SCK) Low Time
Master
Slave

tw(SCKL)m
tw(SCKL)s

TBD
TBD

-

P.s
ns

Data Setup Time (Inputs)
Master
Slave

tsu(m)
tsu(s)

200
200

-

ns
ns

Data Hold Time (Inputs)
Master
Slave

th(m)
thIs)

200
200

-

ns
ns

Characteristic
Operating Frequency
Master
Slave

t

2

3

I

4

5

6

+ 125°C)

7

Access Time
Slave

8

Disable Time (Hold Time to High-Impedance State)
Slave

9

Data Valid
Master (Before Capture Edgel
Slave (After Enable Edge) * *

ta

-

TBD

ns

tdis

-

TBD

ns

tv(B)m
tv(B)s

TBD

400

ns
ns

tv(A)

TBD

-

ns

-

10

Data Valid
Master (After Capture Edge)

11

Rise Time (20% VDD to 70% VDD, CL =200 pF)
SPI Outputs (SCK, MOSI, MISO)
SPI Inputs (SCK, MOSI, MISO, SS)

trm
trs

-

200
2.0

ns
P.s

Fall Time (70% VDD to 20% VDD. CL ~200 pFI
SPI Outputs (SCK, MOSI, MISO)
SPI Inputs (SCK, MOSI, MISO, 55)

tfm
tfs

-

200
2.0

ns
P.s

tho(m)
tho(s)

0
0

-

-

ns
ns

12

13

Output Data Hold (After Enable Edge)
Master
Slave

* Signal production depends on software.
* * Assumes 200 pF load on all SPI pins.

3-590

MC68HC05C4

ss

Held High on Master

(Input)

SCK
(Output)

MISO
(Input)

MOSI
(Output)

(a) SPI Master Timing CPOL = 0, CPHA = 1

Held High on Master

SS
(Input)

SCK
(Output)

MISO
(Input)

MOSI
(Output)

(b) SPI Master Timing CPOL= 1, CPHA= 1
NOTE Measurement points are VOL, VOH, VIL, and VIH

Figure 9-5. Timing Diagrams

3-591

I

MC68HC05C4

Held High on Master

55
(Inputl

SCK
(Outputl

MISO
(Inputl

MOSI
(Outputl

I

Ie) SPI Master Timing CPOL=O, CPHA=O

ss

Held High on Master

(Inputl

SCK
(Output)

MISO
(Inputl

MOSI
(Output)

(d) SPI Master Timing CPOL= 1, CPHA=
NOTE Measurement points are VOL, VOH, VIL, and VIH.

Figure 9-5. Timing Diagrams (Continued)

3-592

MC68HC05C4

ss
(Inputl

SCK
(Inputl

-----~
MISO
(Outputl

MOSI
(Inputl ~..........."'"""~~

(el SPI Slave Timing CPOL=O, CPHA= 1

ss
(Inputl

SCK
(Input)

MISO
(Outputl

MOSI
(Inputl

(f) SPI Slave Timing CPOL= 1, CPHA= 1

NOTE: Measurement points are VOL, VOH, VIL, and VIH.

Figure 9-5. Timing Diagrams (Continued)

3-593

I

MC68HC05C4

ss
(Inputl

SCK
(Inputl

MISO
(Outputl

MOSI
(Inputl

(gl SPI Slave Timing CPOL=O, CPHA=O

I
ss
(Input)

SCK
(Inputl

MISO
(Outputl

MOSI
(Input)

(h) SPI Slave Timing CPOL= 1, CPHA=O

NOTE Measurement points are VOL, VOH, VIL, and VIH

Figure 9-5. Timing Diagrams (Continued)

3-594

MC68HC05C4

SECTION 10
ORDERING INFORMATION
10.1 INTRODUCTION

The following information is required when ordering a custom MCU. The information may be
transmitted to Motorola in the following media:
EPROM(s), MCM2716 or MCM2532
MDOS, disk file
To initiate a ROM pattern for the MCU, it is necessary to first contact your local field service office,
local salesperson, or your local Motorola representative.
10.1.1 EPROMs

The MCM2716 or MCM2532 type EPROMs, programmed with the customer program (positive logic
sense for address and data), may be submitted for pattern generation. The EPROMs must be clearly
marked to indicate which EPROM corresponds to which address space. Figure 10-1 illustrates the
markings for the three MCM2716 EPROMs required to emulate the MC68HC05C4 MCU.
After the EPROM(s) are marked, they should be placed in conductive IC carriers and securely
packed. Do not use styrofoam.

xxx

0020

0800

xxx =

1000

Customer 10

Figure 10-1. EPROM Marking Example
10.1.2 MOOS Disk File

An MDOS disk, programmed with the customer program (positive logic sense for address and
data), may be submitted for pattern generation. WHEN USING THE MOOS DISK, INCLUDE THE
ENTIRE MEMORY IMAGE OF BOTH DATA AND PROGRAM SPACE. All UNUSED BYTES, INCLUDING THE USER'S SPACE, MUST BE SET TO ZERO.

3-595

I

MC68HC05C4

10.2 VERIFICATION MEDIA

All original pattern media (EPROMs or floppy disk) are filed for contractual purposes and are not
returned. A computer listing of the ROM code will be generated and returned along with a listing
verification form. The listing should be thoroughly checked and the verification form completed,
signed, and returned to Motorola. The signed verification form constitutes the contractural agreement for creation of the customer mask. If desired, Motorola will program a blank MCM2716 or
MCM2532 EPROM (supplied by the customer) from the data file used to create the custom mask to
aid in the verification process.
10.3 ROM VERIFICATION UNITS

I

Ten MCUs containing the customer's ROM pattern will be sent for program verification. These units
will have been made using the custom mask but are for the purpose of ROM verification only. For
expediency they are usually unmarked, packaged in ceramic, and tested only at room temperature
(25°) and five volts. These RVUs are included in the mask charge and are not production parts.
These RVUs are not backed nor guaranteed by Motorola Quality Assurance.
10.4 FLEXIBLE DISKS

The disk media submitted must be single-sided, single density, 8-inch MDOS compatible floppies.
The customer must clearly label the disk with the ROM pattern file name and company name. The
floppies are not returned by Motorola as they are used for archival storage. The minimum MDOS
system files as well as the absolute binary object file (filename. LO type of file) from the M6805 cross
assembler must be on the disk. An object file made from a memory dump; using the ROLLOUT
command is also admissable. Consider submitting a source listing as well as: filename, . LX(EXORciser loadable format). This file will of course be kept confidential and is used 1) to speed up the process in house if any problems arise, and 2) to speed up our customer to factory interface if a user
finds any software errors and needs assistance quickly from the factory representative.
MDOS is Motorola's Disk Operating System available on development systems such as EXORciser,
EXORset, etc.

3-596

MC68HC05C4

OPTION LIST
Select the options for the MCU from the following list. A manufacturing mask will be generated
from this information. Select one in each section.
Internal Oscillator Input
Crystal
Resistor

o

o

Interrupt Trigger
Edge-Sensitive
Level- and Edge-Sensitive

o
o

Customer Name _________________________________________________________
Address _______________________________________________________________
City ________________________ State _______________________ Zip ______
Phone (_ _ l ___________Extension _____________________________
Contact Ms/Mr _________________________________________________________
Customer Part N umber __________________________________________________

Pattern Media
02532 EPROM
02716 EPROM
MDOS Disk File
(Notel _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____

o
o

Note: Other Media require prior factory approval.
S ignature ___________________________________________________________
Title ________________________________________________________________

Figure 10-2. Ordering Form

3-597

II

MC68HC05C4

SECTION 11
MECHANICAL DATA
This section contains the pin assignment and package dimension diagrams for the MC68HC05C4
microcomputer.
11.1 PIN ASSIGNMENT

VOO

I

IRQ

2

OSCl

NC

3

OSC2

PA7

4

TCAP

PA6

5

P07

PA5

6

TCMP

PA4

7

P05/SS

PA3

8

P04/SCK

PA2

9

PAl

10

P03/MOSI
31

P02/MISO

PAO

11

POl/TOO

PBO

12

POO/ROI

PBl

13

28

PCO

PB2

14

27

PCl

PB3

15

26

PC2

PB4

16

25

PC3

PB5

17

24

PC4

PB6

18

23

PC5

PB7

19

22

PC6

VSS

20

21

PC7

NOTE: Pin assignments are the same for both the dual in-line and chip carrier package.

3-598

®

MC68HCllA4

MOTOROLA

Product Preview
HCMOS
(HIGH-DENSITY HIGH-PERFORMANCE
SILICON GATE)

MC68HC11A4 8-BIT MICROCOMPUTER
The HCMOS MC68HC11A4 is an advanced microcomputer (MCU)
containing highly sophisticated on-chip peripheral functions. An improved instruction set provides additional capability while maintaining
compatibility with the other members of the M6801 Family. The fully
static design allows operation at frequencies down to dc, further reducing its already low power consumption. Features available in addition to
the normal M6801 features include:

M ICROCOM PUTER

I

• 4K Bytes of ROM
• 512 Bytes of EEPROM
• 256 Bytes of RAM (All Saved During Standby)
• Enhanced 16-Bit Timer System
Four Stage Programmable Prescaler
Three Input Capture Functions
Five Output Compare Functions
• An 8-Bit Pulse Accumulator Circuit
• An Enhanced Non-Return-To-Zero Serial Communications
Interface (SCI)

CERAMIC PACKAGE

Also Available In
52- Pin Quad Pack

• A New Serial Peripheral Interface
• Eight Channel 8-Bit AI D Converter
• A Real Time Interrupt Circuit
• A Computer Operating Properly (COP) Watchdog System

PIN ASSIGNMENT

+5V

I

0-

V DD

XTAL

" L - - - EXTAL

MODA/LIR

-

IRQ

MODBIVpp
STRB/R/W
STRA/AS

Port A

Port B

(3 in, 4 out, 1 1/0)

(8 Output)

Port C

Port E
(4 or 8 Input)

(8110)
Port D

,

(61/0)
VSS

.-L
This document contains Information on a product under development Motorola reserves the
right to change or discontinue this product without notice

3-599

MC68HC11A4

FIGURE 1 PA7

PAl

PA6

OC2

PA5

OC3

PA4

PortA I+--~ OC4

PA3

OC5

PA2

ICl

PA1

IC2

PAD

IC3

MC68HCllA4 BLOCK DIAGRAM

~tPulse Accumulator

-Q...-O

COP
ILlR)
MODA
Mode
Control

Timer
System

OCl

IVpp)
MODB
Periodic Interrupt

XTAL

I

Osc
Port B . .- - - - /

Clock
Logic

Address

CPU Core

Bus

Address!
Data

Interrupt
Logic

Serial
Peripheral
Interface

SPI

RAM

EEPROM

ROM

SCI

-0

~r

0

~

o§

C

ill

Serial
Communication
Interface

0>

co c

......
o 0:,

A-D Converter

z~

c

0

lin
VRL VRH

Vss

~
VDD

3-600

256

512

Bytes

Bytes

4K Bytes

EXTAL

MC68HC11A4

DESCRIPTION and INPUT/OUTPUT PORTS for additional
information regarding address strobe, read/write, port B,
and port C.

GENERAL DESCRIPTION
The MC6SHC11 A4 is a single-chip microcomputer that
utilizes HCMOS techniques to provide the low-power characteristics and high noise immunity of CMOS plus the highspeed operation of HMOS. On chip memory systems include
a 4K byte ROM, 512 bytes of electrically erasable programmable ROM (EEPROM), and 256 bytes of static RAM. The
MC6SHC11 A4 microcomputer also provides highly sophisticated, on-chip peripheral functions including: an S-channel
analog-to-digital converter, a serial communications interface (SCI) subsystem, and a serial peripheral interface (SPI)
subsystem.
New design techniques are used to provide a 2 MHz
nominal bus rate. The timer system is expanded to provide
three input capture lines, five output compare lines, and a
real time interrupt circuit. This gives the MC6SHC11A4 one
of the most comprehensive timer systems found on a singlechip microcomputer. Other features of the MC68HC11A4 include: a pulse aGcumulator which can be used to count external events (event counting mode) or measure an external
period (input gates accumulation of internal clock - E/64); a
computer operating properly (COP) watchdog system which
helps protect against software failures; a programmable
clock monitor system which causes generation of a system
reset in case the clock is lost or running too slow; and an illegal opcode detection circuit which provides an unmaskable
interrupt if an illegal opcode fetch is detected.

BOOTSTRAP MODE
The bootstrap mode is considered a special mode as
distinguished from the normal operating single-chip mode.
In the bootstrap mode, all vectors are fetched from the 128
byte on-chip boot loader ROM. This is a very versatile mode
since there are essentially no limitations on the special pur-'
pose program that is boot loaded into the internal RAM. The
boot loader is contained in 128 bytes of ROM which is
enabled as internal memory space at $BFSO-$BFFF. The boot
loader contains a small program which reads a 256 byte program into on-chip RAM ($OOOQ-$OOFFl. After the character
for address $OOFF is received, control is automatically passed
to that program at memory address $0000 and the MCU
operates in the single-chip mode.
In the bootstrap mode, the serial receive logic is initialized
by software in the boot loader ROM. This allows the program control of the serial communications interface (SCI)
baud and word format.
.
During initialization of the special bootstrap mode, a
special control bit is configured to permit access to a number
of special test control bits which allows for self testing of the
MCU in the bootstrap mode. Also, since the mode control
bits can be written to, the operating mode of the MCU may
be changed from the special bootstrap mode (which is a
Single-chip mode by default) to expanded multiplexed mode
under program control.

OPERATING MODES
TEST MODE
The test mode is considered a special mode as distinguished from the normal operating expanded multiplexed mode;
however, it is considered as operating in the expanded multiplexed mode since external memory may be addressed. The
reset vector is fetched from external memory space $BFFE$BFFF; therefore, program control may be vectored to an external test program.
The test mode is primarily intended as the main production
test mode at the time of manufacture; however, it may also
be used to program calibration or personality data into the internal EEPROM (electrically erasable programmable read
only memory) of the MC68HC11 A4. During initialization of
the test mode, a special control bit is configured to permit
access to a number of special test control bits. Also, since
the mode control bits can be written to in the test mode, the
operating mode of the MCU may be changed from the
special test mode (which is an expanded multiplexed mode
by default) to the single-chip mode under program control.

The MC68HC11A4 MCU uses two dedicated pins (MODA
and MODB) to select one of two basic operating modes or
one of two special operating modes. The basic operating
modes are single-chip (mode 0) and expanded multiplexed
(mode 1), and the special operating modes are bootstrap and
special test. The levels required on the MODA and MODB
pins for mode selection are discussed in FUNCTIONAL PIN
DESCRIPTION. The characteristics of the operating modes
are discussed below.
SINGLE-CHIP MODE (MODE 0)
In the single-chip mode the MCU functions as a selfcontained microcomputer and has no external address or
data bus. lri this mode the MCU provides maximum use of its
pins for on-chip peripheral functions, and all address and
data activity occurs within the MCU. As discussed in FUNCTIONAL PIN DESCRIPTION, when MODA = 0 and
MODB = VDD the single chip mode is selected during reset.
EXPANDED MULTIPLEXED MODE (MODE 1)
In this mode, two I/O ports plus two additional I/O lines
become address. data, and control (AS and R/VV) to allow
the MCU to address up to 64K bytes of address space High
order address bits are output on the port B pins. Low order
address bits and the data bus are time multiplexed on the
eight port C pins. Port D bit 6 becomes the address strobe
(AS) control output which is used in demultiplexing the low
order address from the data at port C. The R/W control pin
(port D, pin 7) is used to control the direction of data
transfers on the port C bus. Refer to FUNCTIONAL PIN

MEMORY
Composite memory maps for each MC68HC11 A4 mode of
operation are shown in Figure 2. These modes include
single-chip, expanded multiplexed, special boot, and special
test.
In the single-chip mode (mode 0) of Figure 2, the
MC68HC11 A4 does not generate external addresses. The actual internal memory locations are shown in the shaded areas
of Figure 2 and the contents of these shaded areas are

3-601

I

MC68HC11A4

FIGURE 2 - MC68HCllA4 MEMORY MAPS
$FFFF

~D
- 4K ROM

$Fooo
$Eooo

4K ROM
(May Be Disabled From Internal Map)

FOOO

$Dooo

$COOO

-

FFF

Boot ROM

~
$Booo

I

~ Interrupt

F~F ~ ~ I~':::D~O:

c:J

Interrupt
Vectors

[:]
BFCO
tlfSMOD=1)

7FF

$AOOO

B600

$9000

512 Byte EEPROM
(May Be Disabled From Internal Map)

$8000
$7000
EXT

EXT

$6000
$5000

64 Byte Register Block

~ (May Be Remapped To Any 4K Boundary)

$4000

~

$3000
$2000

For Expanded Modes
PORTC PORTCL DDRC PORTB
And PIOC Are EXT

$1000
OFF

$0000

256 Byte RAM
(May Be Remapped To Any 4K Boundary)

[:]
0000
Single
Chip
(Mode 0)

Expanded
Mux
(Mode 1)

Special
Boot

Special
Test

shown on the right side of the diagram. For example:
memory locations $0000 through $OOFF contain the 256
bytes allocated to RAM; memory locations $1000 through
$103F are allocated for a 64-byte register block; memory
locations $B6oo through $B7FF are allocated for a 512-byte
EEPROM (electrically eraseable programmable read only
memory); and memory locations $FOoo through $FFFF are
allocated for 4K bytes of ROM (memory locations $FFCO
through $FFFF are reserved for the interrupt and reset
vectors).
The expanded multiplexed mode (mode 1) memory locations shown in Figure 2 are basically the same as for the
single-chip mode; however, the memory locations between
the shaded areas (designated EXT) are for externally addressed memory and 1/0.
The special bootstrap mode memory locations are similar
to the single-chip memory locations except that a special

bootstrap program is addressed at memory locations $BF80
through $BFFF. The special bootstrap program controls the
process of boot loading a 256 byte program through a serial
port into internal RAM.
The special test mode memory locations are similar to the
expanded multiplex mode except the interrupt vectors are at
external memory locations.

CENTRAL PROCESSING UNIT
The central processing unit (CPU) of the MC68HC11A4 is
basically an extension of the MC6801 CPU. In addition to being able to execute all MC6800 and MC6801 instructions, the
MC68HC11A4 uses a 4-page opcode map to allow execution
of 91 new opcodes. As in the M C6801, the CPU of the
MC68HC11A4 is implemented independently from the 1/0,

3-602

MC68HC11A4

memory, or on-chip peripheral configurations. Consequently, this CPU can be treated as an independent processor
communicating with these internal subsystems when
operating in the single-chip mode. However, when the
MC68HCll A4 is operating in the extended multiplexed
mode, it is capable of addressing external memory and

FIGURE 3 -

peripherals in addition to communicating with the on-chip
subsystems.
The MC68HCllA4 CPU has seven registers available to
the programmers as shown in Figure 3. The interrupt stacking order is shown in Figure 4. The seven registers are
discussed below.

MC68HC11A4 PROGRAMMING MODEL

A

8-Bit Accumulators A and B

:1

D

x

Y

SP

Or 16-Bit Double Accumulator D

°1

Index Register X

°1

I ndex Register Y

°

Stack Pointer

°

Program Counter

1

PC

1

l

S

X H

I

N

Z

V

C

I

Condition Code Register

~

Carry/ Borrow from MSB
Overflow
Zero
Negative
I-Interrupt Mask
Half Carry (from Bit 3)
X-Interrupt Mask
Stop Disable

3-603

I

MC68HC11A4

FIGURE 4 -

INTERRUPT STACKING ORDER

PROGRAM COUNTER (PC)
The program counter is a 16-bit register that contains the
address of the next instruction to be executed.

Stack
SP

PCl

SP-l

PCH

SP-2

IYl

SP-3

IYH

SPA

IXl

SP-5

IXH

SP-6

ACCA

SP-7

ACCB

SP-8

CCR

-- SP Before Interrupt

CONDITION CODE REGISTER (CCR)
The condition code register is an 8-bit register in which
each bit signifies the results of the instruction Just executed.
These bits can be individually tested by a program and a
specific action can be taken as a result of the test. Each individual condition code register bit is explained below.
Carry/Borrow (C)

I

The C bit is set if there was a carry or borrow out of the
arithmetic logic unit (ALU) during the last arithmetic operation. The C bit is also affected during shift and rotate instructions.
Overflow (V)
The overflow bit is set if there was an arithmetic overflow
as a result of the operation; otherwise, the V bit is cleared
Zero (Z)

SP-9

--SP After Interrupt

The zero bit is set if the result of the last arithmetic, logic,
or data manipulation was zero; otherwise, the Z bit is
cleared.
Negative (N)

ACCUMULATOR A AND B

The negative bit is set if the result of the last arithmetic,
logic, or data manipulation was negative (b7 of result equal
to a logic one); otherwise, the N bit is cleared.

Accumulator A and accumulator B are general purpose
8-bit registers used to hold operands and results of arithmetic calculations or data manipulations. As in the MC6801,
these two accumulators can be concatenated into a single
double-byte accumulator called the D accumulator.

I Interrupt Mask (I)
The I interrupt mask bit is set either by hardware or program instruction to disable (mask) all maskable interrupt
sources (both external and internal).

INDEX REGISTER X (IX)
The 16-bit IX register is used during indexed modes of addressing. It provides a 16-bit indexing value which may be
added to an 8-bit offset provided in an instruction to create
an effective address. The IX register can also be. used as a
counter or as a temporary storage area.

Half Carry (H)
The half carry bit is set to a logic one when a carry occurs
between bits 3 and 4 of the arithmetic logic unit during an
ADD, ABA, or ADC instruction; otherwise, the H bit is
cleared.

INDEX REGISTER V (IV)
The 16-bit IY register is also used during indexed modes of
addressing similar to the IX register; however, most instructions using the IY register require an extra byte of machine
code and a cycle of execution time since they are two byte
opcodes. The IY register can also be used as a counter or as
a temporary storage in the same manner as the IX register.
STACK POINTER (SP)
The stack pointer (SP) is a 16-bit register that contains the
address of the next free location on the stack. The stack is
configured as a sequence of last-in-first-out read/write
registers which allow important data to be stored during interrupts and subroutine calls. Each time a new byte is added
to the stack (a push), the S P is decremented; whereas, each
time a byte is removed from the stack (a pull) the SP is incremented. The address contained in the SP also indicates
the location at which the accumulators (A and B), IX, and IV
can be stored during certain instructions.

X Interrupt Mask (X)
The X interrupt mask bit is set only by hardware (Reset or
XIRQ); and it is cleared only by program instruction (TAP or
RTI).
Stop Disable (S)
The stop disable bit is set to disable the STOP instruction,
and cleared to enable the STOP instruction. The S bit is program controlled. The STOP instruction is treated as no
operation (NOP) if the S bit is set.

FUNCTIONAL PIN DESCRIPTION
The below pin descriptions do not include the I/O ports.
They are discussed separately under INPUT/OUTPUT
PORTS.

3-604

MC68HC11A4

completes the current instruction. When an XIRQ interrupt is
recognized, on-chip hardware automatically sets the X bit.
The X bit can be cleared either as part of interrupt routine by
the TAP instruction (nested interrupt) or by the return from
interrupt instruction. The XIRQ pin requires an external
resistor to VDD.
The XIRQ input may also be used to return the MCU to
normal operation from the low-power stop mode by applying
a low level to the XIRQ pin. If the X bit in the condition code
register is cleared and the MCU is in the stop mode, a low fnput on the XIRQ brings the MCU out of the stop mode and
operation resumes with the stacking operation leading to
service of the XIRQ request. If the X bit is set and the MCU is
in the stop mode, a low input on the XIRQ brings the MCU
out of the stop mode and operation resumes with the program instruction following the STOP instruction.

VDD AND VSS
Power is supplied to the MC68HCll A4 using these two
pins. VDD is power input (+ 5 V) and VSS is the power
return path.
RESET
This active low bi-directional control pin is used as an input to initialize the MC68HCllA4 to a known start-up state,
and as an open-drain output to indicate an internal failure
has been detected in either the clock monitor or computer
operating properly (COP) circuit.
XTAL, EXTAL
These two inputs provide for an interface with either a
crystal input or a CMOS compatible clock to control the
MC68HCll A4 internal clock generator circuitry. The frequency applied to these pins should be four times the desired
internal clock rate since an internal divide-by-four circuit
determines the actual E-clock rate. When a crystal is used, a
25 picofarad capacitor should be connected between VSS
and each of these two pins (XTAL and EXTAU; however, if
a CMOS compatible external clock is used, the signal should
be connected to the EXT AL pin and the XT AL pin should be
left disconnected.

E
The E pin provides an output for the internally generated
E-clock which can be used as a timing reference. The frequency of the E output is actually one fourth that of the input
frequency at the XTAL and EXTAL pins. In general when the
E pin is low, an internal process is taking place and, when
high, data is being accessed. This output becomes inactive
during the power-saving wait mode if the MC68HCllA4 is
operating in the single-chip or bootstrap modes (see
MODA/UR, MODBIVpp description below).
IRQ
The IRQ pin provides a means for requesting asynchronous interrupts to the MC68HCllA4. The IRQ interrupt
input is program selectable with a choice of either negative
edge-sensitive or level-sensitive triggering. The IRQ interrupt
input is always configured to level-sensitive triggering during
reset. The IRQ pin requires an external resistor to VDD. The
MCU completes the current instruction before responding to
an interrupt request on the IRQ pin.
If IRQ is low and the interrupt mask bit (I bit) in the condition code register is clear, the MCU begins an interrupt sequence at the end of the current instruction.
XIRQ
The XIRQ pin provides a means for requesting asynchronous non-maskable interrupts to the MC68HCll A4,
after a power-on reset. During reset (including power-on
reset), the X bit in the condition code register is set and the
XIRQ interrupt is masked to preclude interrupts on this line
until MCU operation is stabilized. The X bit may then be
cleared by program control (using the transfer accumulator
A instruction, TAP); however, the X bit can only be set again
by reset or by recognition of a hardware XIRQ interrupt.
Once the X bit in the condition code register is cleared, an interrupt on the XIRQ pin will be serviced as soon as the MCU

MODA/UR, MODBIVpp
These pins have alternate functions, MODA and MODB
controlling one function, Vpp controlling an alternate function, and LTR used for an alternate function.
MODA, MODB
During reset these two pins are used to control the two
basic operating modes of the MC68HCll A4 plus two special
operating modes. The modes versus MODA and MODB inputs are shown in the table below.

MODS

MODA

VOO
VOO

0
1
0
1

#
#

Mode Selected
Single-Chip (Mode 0)
Expanded Multiplexed (Mode 11
Special Bootstrap
Special Test

1 = Logic High
0= Logic Low
# = 1.4 Times VOO (or Higher)

Vpp
In addition to the MODA function, the MODAIVpp pin is
also used to supply the programming voltage for programming the internal EEPROM. Changing the voltage applied to
this pin after reset has no affect on mode selection.
UR
In addition to the MODA function, the MODA/LIR pin
provides an output as an aid in debugging once reset is completed. The L1R pin goes to an active low during the first
E-clock cycle of each instruction and remains. low for the
duration of that cycle (opcode fetch). Some MC68HCllA4
opcodes are two consecutive bytes long including a page 2
(PG2), page 3 (PG3), or page 4 (PG4) prebyte. For these instructions L1R goes low for only the first (prebyte) opcode
byte fetch.
NOTE
The LTR output will not go low for at least two E-clock
cycles after reset because of the reset vector fetch.

3-605

I

MC68HC11A4

Each of the input capture pins provide for a transitional input which is used to latch a timer value into a 16-bit readonly register (input capture register). The value latched by an
input capture corresponds to the value of the free running
counter which is part of the timer system. External devices
provide the transitional inputs and internal decoders determine which input transition edge (rising, falling, or either) is
sensed.
Each of the output compare pins provide for an output
whenever a match is made between the value in the freerunning counter (in the timer system) and a value loaded into
the particular 16-bit output compare register. The outputs
can be used externally to indicate that a certain period of
time has elapsed.
When port A pin 7 (PA7) is configured as a pulse accumulator input (PAl), the'external input pulses are applied to a
pulse accumulator register within the MC68HC11 A4.
Each port A pin that is not used for its alternate timer function, as described above, may be used as a general purpose
input or output line.

VREFl, VREFH
These two pins provide the reference voltage for the
analog-to-digital converter.
R/W/STRB

I

This pin provides two different functions depending on the
operating mode. In single-chip mode the pin provides the
STRB (output strobe) function and in the expanded multiplexed mode it provides the R/W (read-write) function.
In the single-chip mode the STRB pin acts as a programmable strobe. This strobe can also be used to provide a data
acknowledge (handshake) to a parallel I/O device.
In the expanded multiplexed mode the R/W (read/write) is
used to control the direction of transfers on the external data
bus. A low level (write) on the R/W pin enables the data bus
output drivers to the external data bus. A high level (read) on
this pin forces the output drivers to a high-impedance state
and data is read from the external bus.
AS/STRA
This pin provides two different functions depending on the
operating mode. In single-chip mode, the pin provides the
STRA (input strobe) function and in the expanded multiplexed mode it provides the AS (address strobe) function.
In the single-chip mode, the STRA pin acts as a programmable input strobe. This input is also used with STRB and
port C for full handshake modes of parallel I/O.
In the expanded multiplexed mode the AS (address
strobe) output may be used to demultiplex the address and
data signals at port C.

Port B
In the single-chip mode, all of the port B pins are general
purpose output pins. During MCU read cycles the levels
sensed at the input side of the port B output drivers is read.
Port B may also be used in a simple strobed output mode
where the STRB (port D bit 7) pulses each time port B is
written.
Port C
In the single-chip mode, all port C pins are general purpose
input/output pins. Port C inputs can be latched by the STRA
input (at port D bit 6). Port C may also be used in full handshake modes of parallel I/O where the STRA input and
STRB output act as handshake control lines.

INPUT/OUTPUT PORTS
Therearefive8-bit ports on the MC68HCllA4 MCU. All of
these ports serve more than one purpose depending on the
mode configuration of the MCU. A summary of the pins versus function and mode is provided in Table 1 and discussed
in the following paragraphs. Because the port functions are
controlled by the particular mode selected, each port is
discussed for its function(s) during the mode of operation.

Port D
In the single-chip mode port D bits 0-5 may be used for
general 110 or with the serial communications interface (S CI)
and serial peripheral interface (SPI) subsystems. Bits 6 and 7
are used as handshake control signals for ports Band C.
Bit 0 is the receive data input (RxD) for the serial communication interface (SCI).
Bit 1 is the transmit data output (TxD) for the SCI.
Bits 2 through 5 are dedicated to the serial peripheral interface (SPI). Bit 2 is the master-in-slave-out (MISO) line; this
pin is an input when the SPI is configured as a master device
and an output when configured as a slave device. Bit 3 is the
master-out-slave-in (MOSI) line; this pin is an output when
the SPI is configured as a master device and an input when
configured as a slave device. Bit 4 is the serial clock (SCK)
and is an output when the SPI is configured as a master and
an input when configured as a slave device. Bit 5 is the slave
select (SS) input which receives an active low signal to
enable a slave device to accept SPI data.
Bit 6 (STRA) and 7 (STRB) are discussed in FUNCTIONAL
PIN DESCRIPTION.

SINGLE-CHIP MODE
In the single-chip mode the MC68HCll A4 functions as a
monolithic microcomputer without external address or data
buses. In this mode, four of these ports (A, B, C, D) are configured as parallel I/O data ports. Port E can be used for
general purpose static inputs and/ or analog-to-digital converter channel inputs.
Port A
In all operating modes (including the single-chip mode)
port A may be configured for: three input capture functions
(IC1, IC2, IC3), four output compare functions (OC2, OC3,
OC4, OC5), and a pulse accumulator input (PAl) or a fifth
output compare function (OC1).

3-606

MC68HC11A4

TABLE 1 -

PORT SIGNAL SUMMARY

Port-Bit

Single-Chip
Modes 0 and Bootstrap Mode

Expanded Multiplexed
Mode 1 and Special Test Mode

A-O
A-l
A-2
A-3
A-4
A-5
A-6
A-7

PAO/IC3
PA1/1C2
PA2/1Cl
PA3/0C5/and-or OCl
PA4/0C4/and-or OCl
PA5/0C3/and-or OCl
PA6/0C2/and-or OCl
PA7I PAil and-or Oel

PAO/IC3
PA1/1C2
PA2/1Cl
PA3/0C5/and-or OCl
PA4/0C4/and-or OCl
PA5/0C3/and-or OCl
PA6/0C2/and-or OCl
PA7/PAl/and-or OCl

B-O
B-1
B-2
B-3
B-4
B-5
B-6
B-7

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

A8
A9
AlO
A11
A12
A13
A14
A15

C-O
C-l
C-2
C-3
C-4
C-5
C-6
C-7

PCO
PCl
PC2
PC3
PC4
PC5
PC6
PC7

AO/DO

D-O
D-l
D-2
D-3
D-4
D-5
D-6
D-7

PDO/RxD
PD1ITxD
PD2/MISO
PD3/MOSI
PD41 SCK
PD5/SS
STRA
STRB

PDO/RxD
PD1ITxD
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
AS
R/W

E-O
E-l
E-2
E-3
E-4
E-5
E-6
E-7

PEOI ANO
PE1/ANl
PE21 AN2
PE31 AN3
PE41 AN4
PE51 AN5
PE61 AN6
PE71 AN7

PEOI ANO
PE1/ANl
PE21 AN2
PE31 AN3
PE41 AN4 ##
PE51 AN5 ##
PE61 AN6 ##
PE7/AN7##

Al/Dl

A2/D2
A3/D3
A4/D4
A5/D5
A6/D6
A7/D7

##
##
##
##

## - not bonded in 48-pin variations

Port E
In all operating modes (including the single-chip mode),
port E is used for general purpose static inputs andlor
analog-to-digital (AID) channel inputs. Port E should not be
read as static inputs while an AI D conversion is actually taking place.
NOTE
On 4B-pin packaged versions of the MC68HC11 A4, the
four most significant bits of port E are not connected
to pins.
EXPANDED MULTIPLEXED MODE
In the expanded multiplexed mode, the MC68HC11 A4 has
the capability of accessing a 64K byte address space. The

3-607

total address space includes the same on-chip memory address as for single-chip mode plus external peripheral
devices. In this mode ports B, C, and bits 6 and 7 of port D
are configured as a memory expansion bus.
Port A
In all operating modes (including the expanded multiplexed mode), port A may be configured for: three input
capture functions (IC1, IC2, IC3), four output compare functions (OC2, OC3, OC4, OC5), and a pulse accumulator input
(PAl) or a fifth output compare functon (OC1).
Each of the input capture pins provide for a transitional input which is used to latch a timer value into a 16-bit readonly register (input capture register). The value latched by an
input capture corresponds to the value of a free running

II

MC68HC11A4

counter which is part of the timer system. External devices
provide the transitional inputs and internal decoders determine which input transition edge (rising, falling, or either) is
sensed.
Each of the output compare pins provide for an output
whenever a match is made between the value in the free running counter (in the timer system) and a value loaded into
the particular 16-bit output compare register. The outputs
can be used externally to indicate that a certain period of
time has elapsed.
When port A pin 7 (PA7) is configured as a pulse accumulator input (PAl), the external input pulses are applied to a
pulse accumulator register within the MC68HC11A4.
Each port A pin that is not used for its alternate timer function as described above, may be used as a general purpose
input or output line.

I

Port B
In the expanded multiplexed mode, all of the port B pins
act as high order address output pins. During each MCU
cycle, bits 8 through 15 of the address are output on the
PBO-PB7 lines respectively.
Port C
In the expanded multiplexed mode, all port C pins are configured as multiplexed addressl data pins. During the address
portion of each MCU cycle, bits 0 through 7 of the address
are output on the PCO-Pel lines. During the data portion of
each MCU cycle (E high), bits 0 through 7 (DO-D7) are
bidirectional data pins controlled by the R/W signal.
Port D
In the expanded multiplexed mode port D bits 0-5 may be
used for general 110 or with the serial communications interface (SCI) and serial peripheral interface (SPI) subsystems.
Bits 6 and 7 act as expansion bus control lines AS and R/W
respectively.
Bit 0 is the receive data input (RxD) for the serial communications interface (SCI).
Bit 1 is the transmit data output (TxD) for the SCI.
Bits 2 through 5 are dedicated to the serial peripheral interface (SPI). Bit 2 is the master·in-slave-out (MISO) line; this
pin is an input when the SPI is configured as a master device
and an output when configured as a slave device. Bit 3 is the
master-out-slave-in (MOSI) line; this pin is an output when
the SPI is configured as a master device and an input when
configured as a slave device. Bit 4 is the serial clock (SCK)
and is an output when the SPI is configured as a master and
an input when configured as a slave device. Bit 5 is the slave
select (SS) input which receives an active low signal to
enable a slave device to accept SPI data.
Bit 6 (AS) and 7 (R/W) are discussed in FUNCTIONAL
PIN DESCRIPTION.
Port E
In all operating modes (including the expanded multiplexed mode), port E is used for general purpose static inputs andlor analog-to-digital (AID) channel inputs. Port E
should not be read as static inputs while an AID conversion
is actually taking place.

NOTE
On 4B-pin packaged versions of the MC68HC11A4, the
four most significant bits of port E are not connected
to external pins.
BOOTSTRAP MODE
In the bootstrap mode all 1/0 port pins function the same
as in the single-chip mode. Operational differences are
discussed in OPERATING MODES.
TEST MODE
In the test mode all 1/0 port pins function the same as in
the expanded multiplexed mode. Operational differences are
discussed in OPERATING MODES.

INTERRUPTS
The MC68HC11A4 MCU interrupts can be generated by
any of four different basic methods: (1) by presenting the appropriate external signal; (2) by enabling interrupts from the
programmable timer output compare or input capture, serial
communication interface, serial peripheral interface timer
overflow, pulse accumulator, or parallel 1/0; (3) by executing
a software interrupt (SWI) instruction; or (4) by detection of
an illegal opcode.
The program may also be interrupted by: (1) detection of a
timeout in the computer operating properly (COP) circuit. (2)
clock monitor detects loss of the E-clock or a low frequency
E-clock, or (3) by a reset. The above three methods of interrupting the program result in fetching a reset vector rather
than an interrupt vector; however, they do interrupt the
program.
When an external or internal (hardware) interrupt occurs,
the interrupt is not serviced until the current instruction being executed is completed. Until the current instruction is
complete,the interrupt is considered pending. After completion of current instruction execution, unmasked interrupts
may be serviced in accordance with an established fixed
hardware priority circuit; however, one I bit related interrupt
source may be elevated to the highest I bit priority position in
the circuit.
Seventeen hardware interrupts and one software interrupt
(excluding reset type interrupts) can be generated from all of
the possible sources. The interrupts can be divided into two
basic categories, maskable and non-maskable. In the
MC68HC11A4 fifteen of the interrupts can be masked using
the condition code register I bit. In addition to being
maskable by the I bit in the condition code register, all of the
on-chip interrupt sources are individually maskable by control bits. The software interrupt (SWI instruction) is a nonmaskable instruction rather than a maskable interrupt
source. The last interrupt (external input to the XIRO pin) is
considered as a non-maskable interrupt because once
enabled, it cannot be masked by software; however it is
masked during reset and upon receipt of an interrupt at the
XIRO pin. Table 2 provides a list of each interrupt, its vector
location in ROM, and the actual condition code register bit
that masks it. A discussion of the various interrupts is provided below.

3-608

MC68HC11A4

TABLE 2 -

INTERRUPT VECTOR ASSIGNMENTS

Vector
Address

FFCO, C1
I

I
FFD4,
FFD6,
FFD8,
FFDA,
FFDC,
FFDE,
FFEO,
FFE2,
FFE4,
FFE6,
FFE8,
FFEA,
FFEC,
FFEE,
FFFO,
FFF2,
FFF4,
FFF6,
FFF8,
FFFA,
FFFC,
FFFE,

D5
D7
D9
DB
DD
DF
E1
E3
E5
E7
E9
EB
ED
EF
F1
F3
F5
F7
F9
FB
FD
FF

Interrupt Source

Masked
By

Reserved

~

I
I
Reserved
SCI Serial System
SPI Serial Transfer Complete
Pulse Accumulator Input Edge
Pulse Accumulator Overflow
Timer Overflow
Timer Output Compare 5
Timer Output Compare 4
Timer Output Compare 3
Timer Output Compare 2
Timer Output Compare 1
Timer Input Capture 3
Timer Input Capture 2
Timer Input Capture 1
Real Time Interrupt
TRO (External Pin or Parallel 1/0)
XIRQ Pin (Pseudo Non-maskable Interrupt)
SWI
Illegal Op-Code Trap
COP Failure (Reset)
COP Clock Monitor Fail (Reset)
RESET

TIMER INTERRUPTS
The timer system provides nine of the fifteen interrupt
possibilities: five output compare interrupts, three input capture interrupts, and a timer overflow interrupt.
The timer contains five 16-bit output compare registers
which are program controlled and may be loaded with a
number between $OOOO-$FFFF. The value in each output
compare register is then compared to a 16-bit comparator,
which is loaded from the timer free running counter, during
each clock cycle. If a match is found between the 16-bit
comparator value and the output compare register value, the
corresponding output compare flag is set. When the output
compare flag is set, a corresponding output compare interrupt may be generated and/ or an external output may be
generated at the corresponding port A pints). Port A outputs
PA3 through PA7 are used as output pins for output compare functions OCl through OC5.
In addition to the five output compare interrupts, the timer
also provides for three input capture interrupts. The timer
contains three 16-bit latch registers which are used to latch
the value of the free running counter (in the timer) when an
input capture edge is applied to the corresponding PAO-PA2
pin. The value of the free running counter is latched into the
corresponding input capture register and an internal interrupt may be generated. The interrupt routine can then read
the storage register and determine the time at which the input capture was detected.
The timer may also provide an interrupt when the free running counter changes value from $FFFF to $0000 (overflow)

~

I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
X Bit
None
None
None
None
None

The 16-bit free running counter repeats this change once for
every 65,536 inputs from a prescaler circuit. The prescaler is
programmable for either divide-by-l, divide-by-4, divideby-B, or divide-by-16 of the MCU E-clock. Thus, the
prescaler extends the actual range of the free running
counter and the time between timer overflow interrupts from
2 16 to 2256 E-clock inputs to the prescaler.

REAL TIME INTERRUPTS
The real time interrupt is a maskable interrupt that occurs
periodically at a rate of EI213, E/214, E/2 15 , or E/216.

EXTERNAL INTERRUPTS
Two external interrupts are accessable using the IRQ and
the XIRQ pins. The IRQ interrupt is a maskable interrupt
while the XIRQ interrupt is considered a non-maskable interrupt; however, the XIRQ interrupt is masked during reset
and immediately following receipt of an XIRQ interrupt
signal. These interrupts are controlled by the I and X bits in
the condition code register as discussed in CENTRAL PROCESSING UNIT.

SOFlWARE INTERRUPT (SWI)
The software interrupt is executed the same as any other
instruction and will take precedence over interrupts only if
the other interrupts are masked (I and X bits in the condition
code register set). The SWI instruction is executed similar to
other maskable interrupts in that it sets the I bit, CPU
registers are stacked, etc.

I

MC68HC11A4

NOTE
The SWI instruction cannot be fetched as long as
another interrupt is pending execution. However,
once it is fetched no other interrupt can be honored
until the first instruction in the SWI service routine is
completed.
SERIAL PERIPHERAL INTERFACE (SPI) INTERRUPT
A serial peripheral interface (S PI) interrupt is generated
when a serial data transfer between the MC68HCll A4 and
an external device has been completed. This interrupt is
masked if the condition code register I bit is set.
SERIAL COMMUNICATIONS INTERFACE (SCI)
INTERRUPT

I

A serial communications interface (SCI) interrupt is
generated if anyone of the following occurs in the SCI:
1. Transmit data register is empty
2. Transmission of data is complete
3. Receive data register is full or an overflow occurred in
the receive data register
4. Idle line detected by receiver.
The SCI interrupt is masked if the condition code register I
bit is set.
PULSE ACCUMULATOR INTERRUPT
The pulse accumulator contains an 8-bit counter which is
program controlled to either count input pulses (event
counting) at PAl or to count internal E/64 clocks subject to
an enable signal at PAl (gated time accumulation). When
the counter has an overflow from $FF to $00 a pulse accumulator overflow interrupt is generated provided the I bit
in the condition code register is clear.
When the input to the pulse accumulator is a gate input at
PAl for counting internal E/64 clocks, the trailing edge of
the gate signal (end of counting cycle) can generate an interrupt. This pulse accumulator input edge interrupt is
generated provided the I bit in the condition code register is
clear. Refer to PULSE ACCUMULATOR for more
information.

POWER-ON RESET
The power-on reset occurs when a positive transition is
detected on VDD. The power-on reset is used strictly for
power turn-on conditions and should not be used to detect
any drops in power supply voltage. There is no provision for
power-down reset. If the external RESET pin is low at the
end of the power-on delay time, the processor remains in the
reset condition until RESET goes high.
COMPUTER OPERATING PROPERLY (COP) RESET
The MC68HCllA4 MCU contains a watchdog timer which
will time itself out if not reset within a specific time by a program reset sequence. If for any reason the COP watchdog
timer is allowed to timeout, it generates an MCU reset which
is functionally similar to pulling the RESET pin low.
A control bit, which is implemented in an EEPROM cell of
the system configuration register, is used to enable (or
disable) the COP reset function. When this bit is clear, the
COP reset function is disabled; if set, the COP reset is
enabled.
CLOCK MONITOR RESET
The MC68HCll A4 MCU contains a clock monitor circuit
which measures the E-clock input frequency. If the E clock
input rate is high enough, then the clock monitor does not
time out. However, if the E clock signal is lost, or its frequency falls below 200 kHz, then an MCU reset is generated
which is functionally similar to pulling the RESET pin low
A read-write control bit, which is implemented in the
system configuration options register, is used to enable (or
disable) the clock monitor reset. When this bit is clear, the
clock monitor reset function is disabled; when set, the clock
monitor reset is enabled.

STOP AND WAIT
The MC68HCll A4 MCU contains two programmable lowpower operating modes; stop and wait. In the wait mode,
the on-chip oscillator remains active together with other
functions discussed below. In the stop mode, all clocks including the crystal oscillator are stopped.

PARALLEL I/O INTERRUPT
The parallel
which uses the
pose of sharing
of the parallel
modes.

I/O subsystem can generate an interrupt
same vector as the IRQ interrupt. The purthe TAO vector is to allow external emulation
I/O subsystem in expanded multiplexed

RESETS
The MC68HCll A4 MCU has four possible types of reset:
an active low external reset pin (RESET), a power-on reset
function, a computer operating properly (COP) watchdog
timer reset, and a clock monitor reset.
RESET PIN
The RESET pin is used to reset the MCU to provide an
orderly software startup procedure. To request an external
reset, the RESET pin must be held low for eight Ecyc (two
Ecyc if internal resets are not used).

WAI (WAIT) INSTRUCTION
The WAI instruction places the MC68HCllA4 MCU in a
low power consumption (wait) mode. In the wait mode, the
internal clock remains active, and the MCU enters one of
four different variations of the wait mode. These variations,
which depend upon the I bit in the condition register and
whether or not the COP circuit is required in the system, include: (1) only the CPU turned off; (2) CPU and the E clock
output buffer turned off; (3) CPU and timer system turned
off; or (4) CPU, E output, and timer system all off.
During the wait mode, the CPU registers are stacked and
processing is suspended until a qualified interrupt is
detected. The actual qualified interrupt type is dependent
upon which of the wait mode variations is selected. The
qualified interrupt(s) required to bring the MCU out of the
wait mode for each of the wait mode variations is shown
below. In all cases, reset brings the MCU out of the wait
mode; however, as in all resets, the system is reset and the
start of MCU operation is determined by the reset vector.

3-610

MC68HC11A4

Wait Mode Variation

Qualified Interrupt

Only CPU Turned Off

IRQ, XIRQ, Any Internal
Interrupt

CPU and E Clock Output
Buffers Turned Off

IRQ, XIRQ, Any Internal
Interrupt

CPU and Timer System
Turned Off

IRQ, XIRQ

CPU, E Clock Output
Buffers, and Timer
System Turned Off

IRQ, XIRQ

3 Input Capture (three 16-bit registers)
4. Output Compare (five 16-bit registers)
5. Main Timer Control and Status Registers
PRESCALER AND FREE RUNNING COUNTER
The key element in the timer system is a 16-bit free running
counter with its associated programmable prescaler (divideby-l, 4, 8, or 16). The free running counter is clocked by the
output of the prescaler which is in turn clocked by the E
clock. The free running counter can be read by software at
any time without affecting its value since it is clocked and
read on opposite half cycles of the M PU E clock. The free
running counter is cleared to $0000 during reset and is a
read-only register (except in the test or bootstrap mode
where this feature is used in factory testing).
The 16-bit free running counter repeats every 65,536
counts (prescaler output) and when the count changes from
$FFFF to $0000 a timer overflow flag bit is set. Setting the
timer overflow flag bit also generates an internal interrupt if
the overflow interrupt enable bit is set.

STOP INSTRUCTION
The STOP instruction places the MC68HCllA4 MCU in its
lowest power consumption mode provided the S bit in the
condition code register is clear. In the stop mode all clocks
including the internal oscillator are stopped, causing all internal processing to be halted. To exit the stop mode and
resume normal processing, a low level must be applied to
one of the external interrupt pins (IRQ or XIRQ) or to the
RESET pin. If an external interrupt is used at the IRQ input, it
is only effective if the I bit in the condition code register is
clear. If an external interrupt is applied at the XI RQ input, the
MCU exits from the stop mode regardless of the state of the
X bit in condition code register; however, the actual recovery
sequence differs depending on the X bit. If the X bit is clear,
the MCU starts up with the stacking sequence leading to
normal service of the XIRQ request. If the X bit is set, then
processing will continue with the instruction immediately
following the STOP instruction and no XIRQ interrupt service routine is requested. As in the wait mode, a low input to
the RESET pin will always result in an exit from the stop
mode and the start of MCU operation is determined by the
reset vector.
Since the oscillator is stopped in the stop mode, a restart
delay may be required to allow for oscillator stabilization
when exiting from the stop mode. If the internal oscillator is
being used, this delay is required; however, if a stable external oscillator is being used, a control bit within the MCU may
be used (cleared) to bypass the delay. If the delay bypass
control bit is clear then the RESET pin would not normally be
used for exiting the stop mode. In this case, the reset sequence sets the delay control bit and the restart delay will be
imposed.

Input Capture Functions
There are three separate 16-bit read-only input capture
registers which are not affected by reset. Each of these
registers is used to latch the value of the free running
counter when a selected transition at an external pin is
detected. External devices provide the inputs on the PAOPA2 pins, and an interrupt can be generated when an input
capture edge is detected. The time of detection can be read
from the appropriate register as part of the interrupt routine.
Output Compare Functions
There are five separate 16-bit read/write output compare
registers which are initialized to $FFFF at reset. The value
written into the output compare register is compared to the
free running counter value during each MCU E clock cycle. If
a match is found between the two values, the particular output compare flag bit is set and an interrupt is generated provided that particular interrupt is enabled.
In addition to the interrupt, a specified action may be
initiated at a timer output pin(s). For OC1, the output action
to be taken, when a match is found, is controlled by a 5-bit
mask register and a 5-bit data register. The 5-bit mask
register specifies which timer port outputs are to be affected
and the 5-bit data register specifies the data to be placed on
the affected output pins. For OC2 through OC5, one specific
timer output is affected as controlled by four 2-bit fields in a
timer control register. Specific actions include: (1) timer
disconnect from output pin logic, (2) toggle output compare
line, (3) clear output compare line to zero, or (4) set output
compare line to one.

PROGRAMMABLE TIMER SYSTEM
The timer system in the MC68HCllA4 uses a "time-ofday" approach in that all timing functions are related to a
single 16-bit free running counter. The free running counter
is clocked by the output of a programmable prescaler (divideby-l, 4, 8, or 16) which is in turn clocked by the MCU E
clock. Functions available within the MC68HCllA4 timer include: three input capture functions and five output compare
functions.
The capabilities of the programmable timer are obtained
using the following registers:

PULSE ACCUMULATOR
The pulse accumulator is an 8-bit counter that can operate
in either of two modes depending on the state of a control
bit. These include the event counting mode or the gated time
accumulation mode.
The pulse accumulator control register contains four bits
which enable and configure the pulse accumulator system.
One bit enables the counter. One bit determines whether the

1. Prescaler (divide-by-l, 4, 8, or 16)
2. Free Running Counter (16-bit)

3-611

I

MC68HC11A4

PA7/ PAl pin will be an input or an output. A third bit
specifies the event counting mode or the gated time
accumulation mode, and the fourth bit determines which
edge of the PAl input is the active one. The 8-bit counter
counts from $00 to $FF and when it overflows from $FF to
$00 a flag bit is set. This results in a hardware interrupt provided the pulse accumulator overflow interrupt enable bit is
set.
In the event counting mode, the 8-bit counter is clocked to
increasing values by an external (PAl) pin input (PA7). In the
gated time accumulation mode, the 8-bit counter is clocked
to increasing values by the MCU E clock (divided-by-64) provided the proper gating signal is applied to an external (PAl)
pin input (PA7).

SERIAL COMMUNICATIONS INTERFACE (SCI)

I

The serial communications interface (SCI) allows the
MC68HCllA4 to be efficiently interfaced with peripheral
devices that require an asynchronous serial data format. The
SCI in the MC68HCllA4 is provided with a standard NRZ
format with a variety of baud rates. The baud rate is derived
from the crystal clock circuit and interface with peripheral
devices is accomplished uSing port D pins. PDO for receive
data (RxD) and PDl for transmit data (TxD).
BAUD RATE GENERATION

The actual baud rate generation circuit contains a programmable prescaler and divider which is clocked by the
MCU E clock. A programmable baud rate register is used to
provide the various divide ratios used in the baud rate
generator prescaler and divider. This scheme of baud rate
generation allows for selection of many different standard
baud rates, all of which are controlled by the crystal
oscillator.
DATA FORMAT
Receive data (RxD) in or transmit data (TxD) out is the
serial data which is presented between the input pin (PDO)
and the internal data bus, and between the internal data bus
and the output pin (PDll. The data format requires:

1. An idle line which is in the high state (logic one)prior to
transmission/ reception of a message.
2. A start bit (logic zero) which is transmitted/received
indicating the start of a message.
3. Data is transmitted and received least-significant bit
first.
4. A stop bit (logic one in the tenth or eleventh bit position) indicates the byte is complete.
5. A break is defined as the transmission or reception of a
logic zero for some multiple of the data format.
The data format word length may consist of either ten or
eleven bits. Selection of the word length is controlled by a
single bit in a control register within the SCI. If this control
bit is clear, the data contains a start bit, eight data bits, and a
stop bit. If this control bit is set, there is a start bit, nine data
bits, and a stop bit.

TRANSMIT OPERATION

The SCI transmitter includes a parallel data register and a
serial shift register. This is referred to as a double buffered
system in that besides the character being Shifted out serially, another character is already waiting to be loaded into the
serial shift register. The output of the transmit serial shiftregister is applied to the TxD output pin (PD1) as long as a
transmit enable bit is set.
RECEIVE OPERATION
Receive data in (RxD) is serial data which is presented to
the input pin (PDO). An advanced data recovery scheme is
used to distinguish valid data from noise in the serial data
stream. In this manner the data input can be selectively
sampled to detect receive data and then verify that the data
is valid. Data is received in a serial shift register and is
transferred to a parallel register as a complete byte. This is
referred to as a double buffered system in that besides the
character already in the parallel register, another is being
shifted in serially.
WAKE-UP FEATURE

The wake-up feature allows a receiver(s) to "sleep" until a
specific action takes place. In a typical multiprocessor configuration, the software protocol will usually identify the addressee(s) at the beginning of a message. This wake-up
feature allows uninterested M PUs to ignore incoming
messages. The MC68HCllA4 SCI permits this wake-up
feature by either of two methods: idle line wake-up or address mark wake-up.
In idle line wake-up, all receivers wake up whenever an idle
line is detected; however, if a receiver does not recognize its
address in the first frame of a message it may ignore the rest
of the message by invoking the wake-up feature. In this
wake-up method, transmitter software must provide for the
required idle string between consecutive messages and prevent it from occurring within messages.
In the address mark wake-up, all serial frames consist of
seven (or eight) inform·ation bits plus a most-significant bit
(MSB) which is used to indicate an address frame if the MSB
is a logiC one. The first frame of each message is an address
frame which wakes up all receivers in the system. All
receivers evaluate this marked address frame to determine
which receiver(s) the message is intended for. If a receiver
determines that a message is not intended for it. it invokes
the receiver wake-up function so that no additional program
overhead is required for the rest of the message.
INTERRUPT FLAGS

The serial communications interface (SCI) generates a
hardware interrupt (SCI interrupt) whenever anyone of
several flags is set and its corresponding interrupt enable bit
is also set. These flags which are discussed below include:
1. Transmit Data register empty
2. Transmission complete
3. Idle line detected
4. Receive data register full or overrun error detected.

3-6·12

MC68HC11A4

The transmit data register empty (TDRE) bit is set to indicate that the transmit parallel data register contents have
been transferred to the transmit serial shift register. If the
corresponding interrupt enable bit (transmit interrupt enable)
is set then an SCI interrupt is generated.
The transmission complete (TC) bit is set when the
transmitter no longer has any meaningful information to
transmit; i.e., no data in the serial shifter, no queued preamble, and no queued break. If the transmitter is enabled
when TC is set, the serial line will go idle (continuous mark).
The idle line detected (IDLE) bit is set whenever a receiver
detects a receiver idle line. This could indicate the end of a
message, the preamble of a new message, or resynchronization with the transmitter. If the corresponding interrupt
enable bit (idle line interrupt enable) is set then an SCI interrupt is generated
The receiver data register full (RDRF) bit is set whenever
the receiver serial shift register contents are transferred to
the serial communicatior:s data register. If the corresponding
interrupt enable bit (receive interrupt enable) is set then an
SCI interrupt is generated.
The overrun error bit is set to indicate that the next byte is
ready for transfer from the receive shift register to the receive
data register but that register is already full (RDRF bit set).
Data transfer is then inhibited until the OR (overrun) bit is
cleared. As with the RDRF bit, an SCI interrupt is generated
if the corresponding interrupt enable bit is set.

In this manner data is transferred serially from a master to a
slave on this line; most significant bit first, least significant
last.
MASTER IN SLAVE OUT (MISO)
The MISO pin is configured as an input in a master (mode)
device and as an output in a slave (mode) device. In this
manner data is transferred serially from a slave to a master on
this line; most significant bit first, least significant last.
SLAVE SELECT (SS)
The slave select (SS) is a fixed input which receives an active low signal that is generated by a master device to enable
slave devices to accept data.
SERIAL CLOCK (SCK)
The serial clock is used to synchronize the movement of
data both in and out of the device through its MOSI or MISO
pins. The master and slave devices can exchange a byte of
information during a sequence of eight clock pulses. The
SCK is generated by the controlling master device and
becomes an input on all slave devices to synchronize slave
data transfer.

ANALOG-TO-DIGITAL (AID) CONVERTER
The MC68HC11 A4 contains an 8-channel, multiplexed input, successive approximation analog-to-digital converter
with sample and hold. Two dedicated pins (VREFL, VREFH)
are provided for the reference supply voltage input. These
dedicated pins are used instead of the device power pins to
increase accuracy of the AI D conversion.
The 8-bit AID conversions of the MC68HC11A4 are
accurate to within ± one LSB (± '12 LSB quantizing error
and ± Y2 LSB non-linearity error). Each conversion is accomplished in 50 MCU E clock cycles or less. An internal
control bit allows selection of an internal conversion clock
oscillator which allows the AI D to be used with very low
MCU clock rates. A typical conversion cycle requires 25 to 50
microseconds to complete.

SERIAL PERIPHERAL INTERFACE
The serial peripheral interface (S PI) allows several
MC68HC11A4 MCUs, or MC68HC11A4 MCUs plus
peripheral devices, to be interconnected within a single
"black box", on the same printed circuit board. In a serial
peripheral interface, the MC68HC11 A4 provides such
features as:
•

Full Duplex, Two, Three, or Four Wire Synchronous
Transfers

• Master or Slave Operation
• Interface With Low Cost "Dumb" Peripherals
• Interface With Intelligent Peripherals on Masterl
Slave Basis

NOTE
In the 48-pin dual in-line package, four conversion
channels are not implemented. These include channels
four through seven.

• Four Programmable Master Bit Rates
• Programmable Clock Polarity and Phase
• End of Transmission Interrupt Flag
• Write Collision Error Detection
•

Master-Master Mode Fault Error Detection

ADDRESSING MODES

Four basic signal lines are associated with the S PI system.
These include a master-out-slave-in (MOSI) line; a master-inslave-out (MISO) line; a serial clock (SCK) line; and a slave
select (SS) line. Two master-slave system configurations are
shown in Figure 5 and the basic Signals (MOSI, MISO, SCK,
and SS) are described below.

Six addressing modes can be used to reference memory;
they include: immediate, direct, extended, indexed (with
either of two 16-bit index registers and an 8-bit offset),
inherent, and relative. Some instructions require an additional byte before the opcode to accommodate a mUlti-page
opcode map; this byte is called a prebyte.
The following paragraphs provide a description of each
addressing mode plus a discussion of the prebyte. In these
descriptions the term effective address is used to indicate the
address in memory from which the argument is fetched or
stored, or from which execution is to proceed.

MASTER OUT SLAVE IN (MOSI)
The MOSI pin is configured as a data output in a master
(mode) device and as a data input in a slave (mode) device.

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MC68HC11A4

FIGURE 5 . MASTER·SLAVE SYSTEM CONFIGURATION
(Sheet 1 of 2)

a. Single Master, Four Slaves

MC68HCll A4 Slave 0
SCK
MISO
MOSI
SS

MISO
MOSI
SCK

SS f - - VOO
MC68HCll A4 Master

I

0
p

0
R
T

1
2
3 f--

MOSI
MISO
SCK

II

~

MC68HCll A4 Slave 3

SS

MOSI
SS
MISO
SCK

Ir

MC68HCll A4 Slave 2

3-614

MOSI
MISO

SS
SCK

MC68HCll A4 Slave 1

MC68HC11A4

FIGURE 5 . MASTER·SLAVE SYSTEM CONFIGURATION
(Sheet 2 of 2)

b. Three Master/Slave, Two Slaves
MC68HCllA4
Master/ Slave

MOSI
MISO
MISO

SCK

SCK

MOSI

SS

SS 15

o12

3

VOO
Sync
Line

MC68HC11A4
Master/ Slave

P
0
R
T

5
0
1
2

U

~

I

3
4

r--

I II
MOSI

MISO SCK
MC68HC11A4
Slave Only For 0

T
1

SS

T

MOSI
MISO SCK
MC68HC11A4
Slave For 0·1·2

3·615

~

2

1

0

51

MOSI
MISO SCK

MC68HC11A4
Master/ Slave

SS

MC68HC11A4

IMMEDIATE ADDRESSING
In the immediate addressing mode, the actual argument is
contained in the byte(s) immediately following the instruction where the number of bytes matches the size of the
register. These are two, three, or four (if prebyte is required)
byte instructions.

II

DIRECT ADDRESSING
In the direct addressing mode, the least significant byte of
the operand address is contained in a single byte following
the opcode and the most significant byte is assumed to be
$00. Direct addressing allows the user to access addresses
$0000 through $OOFF using two byte instructions and execution time is reduced by eliminating the additional memory access. In most applications, this 256-byte area is reserved for
frequently referenced data. These are usually two or three (if
prebyte is required) byte instructions.
EXTENDED ADDRESSING
In the extended addreSSing mode, the second and third
bytes following the opcode contain the absolute address of
the operand. These are three or four (if prebyte is required)
byte instructions: one or two for the opcode and two for the
effective address.
INDEXED ADDRESSING
In the indexed addreSSing mode, one of the index registers
(X or Y) is used in calculating the effective address. In this
case the effective address is variable and depends on two
factors: (1) the current contents of the index register (X or Y)
being used, and (2) the 8-bit unsigned offset contained in the
instruction. This addressing mode allows referencing any
memory location in the 64K byte address space. These are
usually two or three (if prebyte is required) byte instructions,
the opcode plus the 8-bit offset.
INHERENT ADDRESSING
In the inherent addressing mode, all of the information to
execute the instruction is contained in the opcode. The

3-616

operands (if any) are registers and no memory reference is
required. These are usually one or two byte instructions.
RELATIVE ADDRESSING
The relative addressing mode is used for branch instructions. If the branch condition is true and contents of the 8-bit
signed byte following the opcode (the offset) is added to the
contents of the program counter to form the effective
branch address; otherwise, control proceeds to the next instruction. These are usually two byte instructions.
PREBYTE

In order to expand the number of instructions used in the
MC68HC11A4, a prebyte instruction has been added to certain instructions. The instructions affected are usually
associated with index register Y. The opcode instructions
which do not require a prebyte could be considred as page 1
of the overall opcode map. The remaining opcodes could be
considered as pages 2, 3, and 4 of the opcode map and
would require a prebyte; $18 for page 2, $lA for page 3, and
$CD for page 4. Refer to INSTRUCTION SUMMARY for
more detail.

INSTRUCTION SET
The central processing unit (CPU) in the MC68HC11A4 is
basically a proper extension of the MC6801 CPU. In addition
to its ability to execute all M6800 and M6801 instructions, the
MC68HC11A4 CPU has a paged operation code (opcode)
map with a total of 91 new opcodes. Major functional additions include a second 16-bit index register (Y register), two
types of 16-by-16 divide instructions, a STOP instruction,
and bit manipulation instructions.
Table 3 shows all MC68HC11 A4 instructions in all possible
addreSSing modes. For each instruction the operand construction is shown as well as the total number of machine
code bytes and execution time in CPU E-clock cycles. Notes
are provided at the end of Table 3 which explain the letters in
the Operand and Execution Time columns of some instructions.

MC68HC11A4

TABLE 3 -

MC68HC11A4 INSTRUCTIONS, ADDRESSING MODES, AND EXECUTION TIMES

Source Form(s)

Addressing
Mode
for
Operand

Machine Coding
( Hexadecimal)
Operand(s)

Opcode

Machine
Code
Bytes
(Total)

Execution
Time
(Cycles)

ABA

INH

1B

1

2

ABX

INH

3A

1

3

ABY
ADCA (apr)

ADCB (apr)

ADDA (apr)

ADDB (apr)

INH
A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

ADDD (apr)

ANDA (apr)

ANDB (apr)

IMM
DIR
EXT
IND, X
IND, Y
A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

ASL (apr)

EXT
IND, X
IND, Y

18

3A
Ii
dd
hh

18

89
99
B9
A9
A9

2

4

11

ff
ff

2
2
3
2
3

2
3
4
4
5

ii
dd
hh
if
ff

II

18

C9
09
F9
E9
E9

2
2
3
2
3

2
3
4
4
5

Ii
dd
hh
ff
if

II

18

8B
9B
BB
AB
AB

2
2
3
2
3

2
3
4
4
5

ii
dd
hh
if
if

II

18

CB
DB
FB
EB
EB

2
2
3
2
3

2
3
4
4
5

JJ

kk

dd
hh
if
II

3
2

18

C3
03
F3
E3
E3

2
3

4
5
6
6
7

II

2
2
3
2
3

L.
3
4
4
5

II

2
2
3
2
3

2
3
4
4
5

3
2
3

6
6
7

18

A4
A4

il
dd
hh
if
if

18

C4
04
F4
E4
E4

dd
hh
if
if

84
94
B4

78
68
18

ASLA

A

INH

68
48

ASLB

B

INH

58

ii

hh

II

if
II

ASLD

INH

05

ASR (apr)

EXT
IND, X
IND, Y

77

hh

67
67

if
if

18

II

II

3

1

2

1

2

1

3

3
2
3

6
6
7

ASRA

A

INH

47

1

2

ASRB

B

INH

57

1

2

BCC (rei)

REL

24

rr

BCLR (apr) (msk)

DIR
IND, X
IND, Y

15

dd
if
if

18

10
10

mm
mm
mm

2

3

3
3
4

6
7
8

BCS (rell

REL

25

rr

2

3

BEG (reI)

REL

27

rr

2

3

BGE (reI)

REL

2C

rr

2

3

BGT (rell

REL

2E

rr

2

3

3-617

I

MC68HC11A4

TABLE 3 -

MC68HC11A4 INSTRUCTIONS, ADDRESSING MODES, AND EXECUTION TIMES (CONTINUED)

Source Form(s)

Machine
Code
Bytes
(Total)

Machine Coding
( Hexadecimal)
Operand(s)

Opcode

Execution
Time
(Cycles)

BHI (reI)

REl

22

rr

2

3

BHS (reI)

REL

24

rr

2

3

A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

ii
dd
hh
ff
ff

II

18

85
95
B5
A5
A5

2
2
3
2
3

2
3
4
4
5

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

ii
dd
hh
ff
ff

II

18

C5
D5
F5
E5
E5

2
2
3
2
3

2
3
4
4
5

BITA (apr)

BITB (apr)

I

Addressing
Mode
for
Operand

BLE (reI)

REL

2F

rr

2

3

BlO (reI)

REL

25

rr

2

3

BLS (reI)

REl

23

rr

2

3

BlT (reI)

REL

2D

rr

2

3

BMI (reI)

REl

2B

rr

2

3

BNE (reI)

REL

26

rr

2

3

BPL (ref)

REL

2A

rr

2

3

BRA (ref)

REl

20

rr

2

3

BRN (reI)

REL

21

rr

2

3

BRCLR (apr)
(msk)
(rei)

DIR
IND, X
IND, Y

dd
ff
ff

mm
mm
mm

rr
rr
rr

4
4

18

13
1F
1F

5

6
7
8

BRSET (apr)
(msk)
(ref)

DIR
IND, X
IND, Y

18

12
1E
1E

dd
ff
ff

mm
mm
mm

rr
rr
rr

4
4
5

6
7
8

BSET (apr) (msk)

DIR
IND, X
IND, Y

dd
ff
ff

mm
mm
mm

3

6
7

18

14
1C
1C
8D

3
4

8

rr

2

6

BSR (ref)

REL

BVC (reI)

REl

28

rr

2

3

BVS (ref)

REL

29

rr

2

3

CBA

INH

11

1

2

ClC

INH

OC

1

2

CLI

INH

OE

1

2

CLR (apr)

EXT
IND, X
IND, Y

7F
6F
6F

3
2
3

6
6
7
2

18

hh
ff
ff

II

CLRA

A

INH

4F

1

CLRB

B

INH

5F

1

2

INH

OA

1

2

A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

18

81
91
B1
A1
A1

ii
dd
hh
ff
ff

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

II

18

C1
D1
F1
E1
E1

CLV
CMPA (apr)

CMPB (apr)

dd
hh
ff
ff

3-618

II

2
2
3
2
3

II

2
2
3
2
3

2

3
4
4

5
2
3
4
4

5

MC68HC11A4

TABLE 3 -

MC68HCllA4 INSTRUCTIONS. ADDRESSING MODES. AND EXECUTION TIMES (CONTINUED)

Source Form(s)

Addressing
Mode
for
Operand

COM (apr)

EXT
IND. X
IND. Y

Machine Coding
( Hexadecimal)
Operand(s)

Opcode

18

73
63
63

hh

II

If
If

Machine
Code
Bytes
(Total)
3
2
3

Execution
Time
(Cycles)
6
6
7

COMA

A

INH

43

1

2

COMB

B

INH

53

1

2

4
3
4
3
3

5
6
7
7
7

3
2
3
2
3

4
5
6
6
7

4
3
4
3
3

5
6
7
7
7

CPO (apr)

IMM
DIR
EXT
IND. X
IND. Y

CPX (apr)

CPY (apr)

1A
1A
1A
1A
CD

83
93
B3
A3
A3

IMM
DIR
EXT
IND. X
IND. Y

CD

8C
9C
BC
AC
AC

IMM
DIR
EXT
IND. X
IND. Y

18
18
18
1A
18

8C
9C
BC
AC
AC

18

DAA

INH

19

DEC (apr)

EXT
IND. X
IND. Y

7A
6A
6A

IJ

kk

dd
hh

)1

II
If
IJ

kk

dd
hh

)1

II
II
II

kk

dd
hh

II

II
II
hh

II

If
If

1

2

3
2
3

6
6
7
2

DECA

A

INH

4A

1

DECB

B

INH

5A

1

2

INH

34

1

3

DES
DEX

INH

DEY

INH

EORA (apr)

EORB (apr)

A
A
A
A
A

IMM
DIR
EXT
IND. X
IND. Y

B
B
B
B
B

IMM
DIR
EXT
IND. X
IND. Y

18

09

1

3

09

2

4

II

2
2
3
2
3

2
3
4
4
5

II

2
2
3
2
3

2
3
4
4
5

88

18

98
B8
A8
A8

18

C8
08
F8
E8
E8

ii
dd
hh

If
If
ii
dd
hh

If
If

FDIV

INH

03

1

41

IDIV

INH

02

1

41

INC (apr)

EXT
IND. X
IND. Y

7C
6C
6C

3
2
3

6
6
7
2

18

hh

II

If
If

INCA

A

INH

4C

1

INCB

B

INH

5C

1

2

INS

INH

31

1

INX

INH

3
3

INY

INH

JMP (apr)

EXT
IND. X
IND. Y

JSR (apr)

DIR
EXT
IND. X
IND. Y

08

1

18

08

2

4

3
2
3

3

18

7E
6E
6E

2

18

90
BD
AD
AD

5
6
6
7

hh

II

If
If
dd
hh

3-619

If
If

II

3
2
3

3
4

•

MC68HC11A4

TABLE 3 -

MC68HC11A4 INSTRUCTIONS, ADDRESSING MODES, AND EXECUTION TIMES (CONTINUED)

Source Form(s)
LDAA (opr)

LDAB (opr)

I

Addressing
Mode
for
Operand
A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

LDD (opr)

LOX (opr)

LOY (opr)

LSL (opr)

86
96

18

18

C6
06
F6
E6
E6

18

CC
DC
FC
EC
EC

18

8E
9E
BE
AE
AE

IMM
DIR
EXT
IND, X
IND, Y

CD

CE
DE
FE
EE
EE

IMM
DIR
EXT
IND, X
IND, Y

18
18
18
1A
18

CE
DE
FE
EE
EE

IMM
DIR
EXT
IND, X
IND, Y

EXT
IND, X
IND, Y

Operand(s)

Opcode

B6
A6
A6

IMM
DIR
EXT
IND, X
IND, Y

LOS (opr)

Machine Coding
( Hexadecimal)

78
68
18

68

LSLA

A

INH

LSLB

B

INH

48
58

LSLD

INH

05

LSR (opr)

EXT
IND, X
IND, Y

74
18

64
64

ii

dd
hh
If

II

2

3

4
4
5

3

ii

2
2

dd
hh
If
If

II

jj

Kk

3

2
3

dd

3

2

hh
If
If

II

jj

kk

3

2
3

dd

3

2
II

3

2

II

3

kk

3

hh
If
If

II

3

jJ

kk

jj

dd

2
2
3

dd
hh
If
If

II

hh
If
If

II

hh
If

II

3

2
3
4
4
5
3
4
5
5
6
3
4
5
5
6
3
4
5
5
6

3

4
5
6
6
6

3
2
3

6
6
7

4
3
4

3

II

Execution
Time
(Cycles)

2
2
2

ff

hh
If

Machine
Code
Bytes
(Total)

1

2

1

2

1

3

3
2
3

6
6
7

2

LSRA

A

INH

44

1

LSRB

B

INH

54

1

2

INH

04

1

3

MUL

INH

3D

1

10

NEG (opr)

EXT
IND, X
IND, Y

70
60
60

3

6
6
7

LSRD

18

hh
If
If

II

2
3

NEGA

A

INH

40

1

NEGB

B

INH

50

1

NOP
ORAA (opr)

ORAB (opr)

INH

01

A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

18

8A
9A
BA
AA
AA

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

18

CA
DA
FA
EA
EA

1

ii

2
2

dd
hh
If
If

II

2
3

ii

2
2

dd
hh
If
If

3-620

3

II

3

2
3

2
2
2
2
3
4
4
5

2
3
4
4
5

MC68HC11A4

TABLE 3 -

MC68HCllA4 INSTRUCTIONS, ADDRESSING MODES, AND EXECUTION TIMES (CONTINUED)
Addressing
Mode

Machine Coding
(Hexadecimal)

for
Source Form(s)

Operand

Operand(s)

Opcode

Machine
Code
Bytes
(Total)

Execution
Time
(Cycles)

PSHA

A

INH

36

1

3

PSHB

B

INH

37

1

3
4

PSHX

INH

PSHY

INH

18

3C

1

3C

2

5
4

PULA

A

INH

32

1

PULB

B

INH

33

1

4

PULX

INH

38

1

5

PULY

INH

2

6

ROL (apr)

EXT
IND, X
IND, Y

3
2
3

6
6
7

18

38

18

79
69
69

hh
If
II

II

ROLA

A

INH

49

1

2

ROLB

B

INH

59

1

2

3
2
3

6
6
7

46

1

2

ROR (apr)

EXT
IND, X
IND, Y

18

76
66
66

hh
If
If

II

RORA

A

INH

RORB

B

INH

56

1

2

INH

3B

1

12

RTS

INH

39

1

5

SBA

INH

10

1

2

A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

dd
hh
II
II

II

18

82
92
B2
A2
A2

2
2
3
2
3

2
3
4
4
5

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

dd
hh
II
If

II

18

C2
D2
F2
E2
E2

2
2
3
2
3

2
3
4
4
5

RTI

SBCA (apr)

SBCB (apr)

il

ii

SEC

INH

OD

1

2

SEI

INH

OF

1

2

SEV

INH

OB

1

2

A
A
A
A

DIR
EXT
IND, X
IND, Y

18

97
B7
A7
A7

dd
hh
If
If

2
3
2
3

3
4
4
5

B
B
B
B

DIR
EXT
IND, X
IND, Y

18

D7
F7
E7
E7

dd
hh
If
If

2
3
2
3

3
4
4
5

DD
FD

dd
hh
If
If

2
3
2
3

4
5
5
6

STAA (apr)

STAB (apr)

STD (apr)

DIR
EXT
IND, X
IND, Y

ED
18

ED

3-621

II

II

II

•

MC68HC11A4

TABLE 3 -

MC68HCllA4 INSTRUCTIONS, ADDRESSING MODES, AND EXECUTION TIMES (CONTINUED)

Source Form(s)

Addressing
Mode
for
Operand

Operand(s)

Opcode

STOP

INH

CF

STS (opr)

DIR
EXT
IND, X
IND, Y

18

9F
BF
AF
AF

dd
hh
ff
ff

DIR
EXT
IND, X
IND, Y

CD

DF
FF
EF
EF

dd
hh
ff
ff

DIR
EXT
IND, X
IND, Y

18
18
1A
18

DF
FF
EF
EF

dd
hh
ff
ff

18

80
90
BO
AO
AO

dd
hh
ff
ff

18

CO
DO
FO
EO
EO

II
dd
hh
ff
ff

18

83
93
B3
A3
A3

II
dd
hh
ff
ff

STX (opr)

STY (opr)

I

Machine Coding
(Hexadecimal)

SUBA (opr)

SUBB (opr)

A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

SUBD (opr)

IMM
DIR
EXT
IND, X
IND, Y

II

II

II

II

II

Machine
Code
Bytes
(Total)
1

2

2
2

4
5
5

3

6

2
3
2
3

4
5
5

3
4
3
3

5

3

2
2
3

2
3
2

2
II

3

2
3
kk

6
6
6
6
2
3
4
4
5
2
3
4
4
5

3
2
3

4
5
6
6
7

3

2
II

Execution
Time
(Cycles)

SWI

INH

3F

1

14

TAB

INH

16

1

2

TAP

INH

06

1

2

TBA

INH

17

1

2
*
2

TEST

INH

00

1

TPA

INH

07

1

TST (opr)

EXT
IND, X
IND, Y

7D
6D
6D

18

hh
ff
ff

II

3

2
3

6
6
7

TSTA

A

INH

4D

1

2

TSTB

B

INH

5D

1

2

TSX

INH

TSY

INH

TXS

INH

TYS

INH

WAI

INH

XGDX

INH

XGDY

INH

18
18

18

30

1

3

30

2

4

35

1

3

35

2

4

3E

2

14+n**

8F

1

3

8F

2

4

* -Infinity or until reset occurs.
* * -12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock cycles (n) until an interrupt is recognized. Finally
two additional cycles are used to fetch the appropriate interrupt vector.
dd = 8-bit direct address ($OOOO-$OOFF) (high byte assumed to be $00)
ff = 8-bit positive offset $00 (0) to $FF (255) (is added to index)
hh = high order byte of 16-bit extended address
ii = one byte of immediate data
jj = high order byte of 16-bit immediate data
kk = low order byte of 16-bit immediate data
II = low order byte of 16-bit extended address
mm = 1-byte bit mask (set bits to be affected)
rr = signed relative offset $80 (- 128) to $7F (+ 127) (offset relative to the address following
the machine code offset byte)

3-622

®

MC68HC68Al

MOTOROLA

Product Preview
HCMOS
(HIGH-DENSITY CMOS
SILICON-GATE)

SERIAL 10-BIT ANALOG-TO-DIGITAL CONVERTER
The MC68HC68Al is an HCMOS seriall0-bit analog-to-digital (AID)
converter. Interface to the AID converter is through a standard serial
peripheral interface (SPI) unit. This device can interface directly with
the MC68HC05D2 microcomputer without additional components.
The following is a summary of the features offered by the
MC68HC68A 1.

SERIAL 10-BIT
ANALOG-TO-DIGITAL
CONVERTER

I

• 10 Bits of Resolution
• Eight Bits of Accuracy
• Serial Peripheral Interface Capability
• Conversion Time 100 p,s Maximum
• Eight Analog Input Channels
• Common Mode VDD-VSS
• Continuous or Single-Channel Scan
• Sample and Hold Capability
• Schmitt Oscillator Clock Input

P SUFFIX
PLASTIC PACKAGE
CASE 648

GENERAL DESCRIPTION
The MC68HC68A 1 is an HCMOS lO-bit analog-to-digital converter.
Interface to the MC68HC68A 1 is through a standard serial peripheral interface (SPI)' Data is shifted in on the shift-data-in (SOl) pin and out on
the shift-data-out (SDOl pin synchronous with the second edge of the
shift-clock (SCK) pin following chip enable (CE) being activated. This
device is compatible with the MC68HC05D2 microcomputer and will interface directly without additional components.
The MC68HC68A 1 performs a lO-bit analog-to-digital conversion in a
maximum conversion time of 100 microseconds. Data out from the
device is transferred in two 8-bit bytes using the serial peripheral interface burst mode operation. The most significant 8-bit byte contains
data in valid bits which the controlling microcomputer can monitor to
insure correct data.
One of eight analog channels can be accessed through three of the
eight address bits. Additional address information can be used to
establish the systems operation to allow for system polling or interrupt
driven communications from the controlling microcomputer. The address register will allow direct access to any of the sixteen 8-bit on-chip
registers containing the eight channels of AID information.
The device is available in a 16-pin package and contains an on-chip
Schmitt oscillator clock input which can be directly driven by a system
clock or connected to an external capacitor to develop an independent
clock for the AID device.

This document contains information on a product under development. Motorola reserves the
right to change or discontinue this product without notice

3-623

PIN ASSIGNMENT
OS C [r;--\....I'"i6::J V 0 0

INT [ 2

15] A2

SOO [ 3

14] A3

5011 [ 4
SCK[5

13

P A4

12~iA5

P A6

CE [ 6

11

A1I7

10pA7

VSS [ 8

9

~ A8

®

MC68HC68Rl
MC68HC68R2

MOTOROLA
Advance Information

HCMOS
(HIGH-DENSITY CMOS SILICON-GATE)

8-BIT SERIAL STATIC RAMs

I

The MC68HC68Rl and MC68HC68R2 are serially organized 128-word
(MC68HC68Rl) or 256-word (MC68HC68R2) by 8-bit static random access memories (RAMs). These RAMs are intended for use in systems
where minimum package and interconnect size, low power, and
simplicity of use are desirable; for example, in systems utilizing synchronous serial 3-wire (clock, data in, data out) interfaces. Interface can
be made with the MC68HC05D2 without additional components, provided the MC68HC05D2 SPI control register bits CPHA and CPOL are
set.

8-BIT SERIAL STATIC RAMs

• Fully Static Operation
• Operating Voltage Range: 3 V to 5.5 V
•
•
•
•

Maximum Standby Current = 2 p,A
Directly Compatible with SPI Interface
Separate Data Input and Data Output Pins
Input Data and Clock Buffers Gated Off with Chip Enable

P SUFFIX
PLASTIC PACKAGE
CASE 626

• Protocol for Fast Sequential Multiple Byte Accesses
• Minimum Data Retention Voltage: 2 V
• Small 8-Lead Plastic Package

PIN ASSIGNMENT

S C K D 8 VDD
SS
2
7
SDI
See Note

VSS

3.

4

..

6

.5

SDO

CE

NOTE
Pin 3= N/C for MC68HC68Rl
Pin 3=A7 for MC68HC68R2

ThiS document contains InformAtion on ~ product under development Motorola reserves the
right to change or discontinue thIS product without notice

3-624

MC68HC68R1·MC68HC68R2

SIGNAL DESCRIPTION

VDD AND VSS
The VOO pin is the + 5 volt power supply and VSS is the
ground reference pin.

CHIP ENABLE AND SLAVE SELECT (CE AND SS)
A high level on the CE pin, coincident with a low level on
the SS pin, is required for the RAM serial interface logic to
become enabled. The device is held in the reset state if either
CE is low or SS is high.

ADDRESS LINE (A7) -

MC68HC68R2 ONLY

This address input is used in the 256-word RAM version to
select either of two 128-word memory areas. (Address bits
AO-A6, used to provide the address within the 128-word
memory area in both the MC68HC68R1 and MC68HC68R2
versions, are the seven least significant bits of the first serial
8-bit byte received at the SOl port at the start of a read or
write cycle. The most significant bit of this first byte is the
read/write mode bit.)

SERIAL CLOCK (SCK)
This clock input is used to synchronously latch data in and
shift data out of the RAM chip.
SERIAL DATA IN (SDI)
Serial data, present at this port, is latched into the RAM
chip by SCK if the chip is enabled and in a write cycle.

DATA FORMAT, TRANSFER, AND TIMING

SERIAL DATA OUT (SDO)

FORMAT

Serial data is shifted out of this port by SCK if the RAM
chip is enabled and in a read cycle.

Two type of 8-bit bytes are used when storing or retrieving
data in the RAM chip, as shown in Figure 1.

FIGURE 1 -

SERIAL DATA FORMAT

Addressl Control Byte
Bit:

7

4

I RI W I A6

A5

A4

A3

A2

A1

AO

AO-A6' The seven least significant RAM address bits, sufficient
to address 128 bytes.
R/W: Read or write data transfer control bit. R/W = 0 initiates
one or more memory read cycles; R/W = 1 initiates one
or more memory write cycles.

Data Byte
Bit·
D7
DO-D7

D6

D5

4

3

2

D4

D3

D2

8 bits of data

3-625

D1

DO

I

MC68HC68R1·MC68HC68R2

out the entire transfer, whether single or multiple, as shown
in Figure 2.

TRANSFER

Data transfers, occurring only while CE is high and SS is
low, are either single data byte or multiple data transfers.
Only only address byte is required for each type of transfer.
For mUltiple transfers, the RAM automatically increments
the address as long as it remains enabled. However, anytime
enabling signals CE and SS are removed, RAM is reset, and
when re-enabled, interprets the first word received as an address word. Therefore, RAM must remain enabled through-

FIGURE 2 -

TIMING
Address, control, or data bits are latched into RAM by the
rising edge of SCK during a write cycle During a read cycle,
the rising edge of SCK shifts out the data bits. Bit switching
occurs during the trailing edge of SCK and ensures that the
bit value is valid when the SCK rising edge occurs, as shown
in Figure 3.

SERIAL TRANSMISSION BYTE SEQUENCES
Single Byte Transfer

CE

I

Data

-.I
WlJ/~

Address Byte

Data Byte

\---V!I////II!J/!ff!////!h

Multiple Byte Transfer
CE

~

Data

R/W Address= Address Byte _ _ _ _ _ _.....J
R/W Address= Address Byte+ 1 - - - - - - - - - - - - - - '
R/W Address=Address Byte+in-l) -----------------------~

FIGURE 3 -

RAM TIMING DIAGRAM

SCK
-----'I

SOl

I

~ Bit Latch/Shift Clock

I

I

~--- A-O----J~~---------~
__

I

>+--

SDO

~~

Bit Switching Clock

_________

~~~

~

______D_7_____

3-626

®

MC68HC68Tl

MOTOROLA

Product Preview
HCMOS
(HIGH~DENSITY

REAL-TIME CLOCK
PLUS RAM AND POWER SENSE/CONTROL
The MC68HC68T1 HCMOS clock/RAM peripheral contains a realtime clock/calendar, a 32x8 static RAM, and a synchronous, serial,
three-wire interface for communication with a microcomputer. The
followinq summarizes the features of the MC68HC68T1.
•

Full Clock Features - Seconds, Minutes, Hours (AM/PM), Day-ofWeek, Date, Month, Year (0-99), Auto leap Year

•
•

32 Word by 8-Bit RAM
Minimum Operating Voltage 2.2 Volts

•

Burst Mode for Reading/Writing Successive Addresses
or RAM

•

Selectable Crystal or 50/60 Hz line Input

•
•

BCD Data Contained in Registers
Buffered Clock Output for Driving CPU Clock, Timer, Colon, or
LCD Backplane

In

CMOS

SILlCON~GATE)

REAL-TIME CLOCK
PLUS RAM AND
POWER SENSE/CONTROL

II

Clock

P SUFFIX

•

Power-On-Reset with First~Time-Up Flag

•

Freeze Circuit Eliminates Software Overhead During a Clock Read

•

Three Independent Interrupt Modes ~
Power~Down Sense

PLASTIC PACKAGE
CASE 648

Alarm, Periodic, or

•

CPU Reset Output ~ Provides Orderly Power Up/Down

•

Watch~Dog Circuit

•

Auto Switchable Clock

DESCRIPTION
The M C68H C68T 1 H CM 0 S clock/ RAM peripheral contains a real~
time clock/calendar, a 32x 8 static RAM, and a synchronous, serial,
three-wire interface for communication with a microcomputer.
Operating in a burst mode, successive clock or RAM locations can be
read or written using only a single starting address An on~chip
oscillator allows acceptance of a selectable crystal frequency or can be
programmed to accept a 50/60 hertz line input frequency.
Three pins give the MC68HC68T1 the capability for sensing
powerup/ powerdown conditions, a capability useful for battery~backup
systems. The 16~pin dual~in-line package has an interrupt output
capable of signalling the microcomputer of the occurrence of three
separately selectable conditions. An· alarm can be set for comparison
with the seconds, minutes, and hours registers. This alarm can be used
in conjunction with the power supply enable output to initiate a system
power-up sequence.
A software power-down sequence can be initiated by setting a bit in
the interrupt control register This applies a reset to the CPU, using the
CPU RESET output, sets the clock (ClK) and power supply enable
(PSE) output pins low, and disables the serial interface. This condition
is held until an edge is sensed on the varying power sense (VPS) input,
signalling system power coming on, or by activation of a previously
enabled interrupt
A watCh-dog circuit can be enabled that requires the microcomputer
to toggle the chip enable (CE) pin of the MC68HC68T1 approximately
every 8 microseconds, without performing a serial transfer. If this
condition is not sensed, the CPU RES ET line resets the CPU.
A block diagram of the MC68HC68T1 is shown in Figure 1.
This document contains information on a product under development Motorola reserves the
right to change or discontinue thiw product without notice

3-627

PIN ASSIGNMENT
ClK OUT

Ifi'i\....I""i6p

CPUR [ 2
INT I 3

VOO

15~ XTAl IN

14 ~ XT Al OUT

SCK

I

4

13

P ClK

SOl

I

5

12

P 50/60

SOO [ 6
CE

I

7

11 ~ VPS
10 P paR

p PSE

VSS 1L,.8_ _ _....
9

MOOE
Hz

•
FIGURE 1 - FUNCTIONAL BLOCK DIAGRAM

~

.....

XTAL
XTAL

Clock Mode
Clock Out

INT

I\)

ex>
VDD
C>--

VSS

C>--

SCK
SDO
SDI
CE
MODE
MODE

:I:
CO

50/60 Hz

c:»

CO

oen

CE

w

3!:

oen

Serial
Interface

MC68HC68T1

SIGNAL DESCRIPTION

CLOCK OUTPUT (CKL OUT)

This signal is the buffered clock output which can provide
one of fifteen selectable frequencies.
CPU RESET (CPUR)

This output can be used to drive the CPU reset pin to permit orderly powerup/ powerdown.
INTERRUPT (lNT)

The interrupt output is driven by a single NFET pulldown
transistor and can be activated by three selectable conditions.
SERIAL CLOCK (SCK)

The serial clock input is used to latch data into, and shift
data out of, the interface logic.
SERIAL DATA IN (SDI)

The serial data input, present at this port, is latched into
the interface logic, by SCK, if the logic is enabled.
SERIAL DATA OUT (SDO)

The serial data ouput, present at this port, is shifted out of
the interface logic, by SCK, if the logic is enabled.

LINE SENSE (50/60 Hz)

The line sense input can be used to drive two functions. If
the clock is selected for line operation, a Schmitt trigger input senses the 50/60 Hz input. If the power sense interrupt is
enabled, this input is used to sense when external power to
the system is turning off. If this pin is not used, it should be
connected to VDD.
CLOCK MODE SELECT (CLK MODE)

When tied to VDD, the clock mode select intput selects
the clock output for XT AL following a power-on reset. When
tied to VSS, the clock output is disabled following a powerreset.
CRYSTAL INPUT/OUTPUT (XTAL IN AND XTAL OUT)

For crystal operation, these two pins are connected to a
32768 hertz, 1.048576 megahertz, 2097152 megahertz, or
4.194304 megahertz crystal. If crystal operation is not required, connect XT AL IN to VDD or VSS and leave XT AL
OUT open. If an external clock is used, connect the external
clock to XT AL IN, and leave XT AL OUT open.
VDD AND VSS

Power is supplied to the MC68HC68T1 using these two
pins. VDD is the + 5 volts power input and VSS is the power
supply ground reference pin.

CHIP ENABLE (CE)

When high, the chip-enable input enables the interface
logic. Otherwise the logic is in a reset state. The watch-dog
circuit can be toggled at this pin.
POWER SUPPLY ENABLE (PSE)

The power supply enable output is used to control system
power and is enabled high on a varying power sense edge,
an Interrupt, or a power-on reset. PSE is set low by writing a
high into the power-down bit of the interrupt control
register.
POWER-ON RESET (POR)

This Schmitt trigger generates a power-on reset signal using an external RC network
VARYING POWER SENSE (VPS)

The varying power sense input is connected to system
power and detects a positive edge that indicates a switch
from battery-backup power to an external power source.
This action disables the CPUR output, enables the PSE output and switches to line from crystal operation, if the auto
switchable clock option in being used. If this pin is not used,
it should be connected to VDD.

CLOCK/RAM TRANSFER AND WORD FORMAT
The following paragraphs
transfer and word format.

describe

the

clock/ RAM

TRANSFER FORMAT

Data transfers, occurring only while CE is high are either
single data byte or multiple data byte transfers. Only one address byte is required for each type of transfer.
For mulitple transfers, the clock/ RAM automatically increments the address as long as it remains enabled. The
clock/ RAM must remain enabled between transmission of
address and data bytes or between successive data bytes in
the case of mulitple byte transfers. The serial control logiC in
the clock/ RAM is held reset when the clock/ RAM is not
enabled or the software powerdown is enabled (refer to
Figure 2).
SERIAL DATA FORMAT

The address, control, and status 8-bit byte formats, used
in the clock/ RAM registers, are shown in Figures 3 through 9.

3-629

I

MC68HC68T1

FIGURE 2 -

SERIAL TRANSMISSION BYTE SEQUENCES

Single Byte Transfer

Data

I I I I II

Data Byte

Address Byte

Multiple Byte Transfer

I

... -------'L

CE~
Data

I I I I II

R/W

Data Byte

Address Byte

Add"~

• Add"" BY"

R/W Address = Address Byte + 1

I: ·:

Data Byte

1

D_a_ta_B_y_te_--LI_I_I_I_I_I

1... _ _

1

t

~

R/WAddress = Address Byte + in-1) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---'

FIGURE 3 -

ADDRESS/CONTROL BYTE

o

4

I

Clock
A4
RAM _

A3

A2

A1

Read/Write:

Read or write data transfer control bit. R/W = 0 initiates one or more write cycles. R/W = 1 initiates
one or more read cycles.

Clock/RAM:

Clock or RAM select bit. If bit is set high, the
clock is selected. If bit is set low, the RAM is
selected.

AO-A4:

Selects desired address of RAM or specifies clock
register. If invalid address specified, it is ignored.

Test Mode:

If the address is set to 01010101, the test mode is
entered.

FIGURE 4 -

RAM DATA FORMAT

4

$OO-lF

AO

D7

D6

D5

D4

D3

3-630

D2

D1

o
o

MC68HC68T1

FIGURE 5 -

$00

$01

4

X

Tens of Seconds

7

4

5

112/24

Seconds Units

Tens of Minutes

X
7

$02

CLOCK DATA REGISTERS

7

I

X

Minutes Units

4

IAM/PMllo HR

I

Hours Units

4
$03

X

$04

X

X

X

X

10 Date

X

0
Day of Week

X

7
Date Units

4
$05

X

X

Tens

X

Month Units

II

4
$06

Tens of Years

Year Units

FIGURE 6 - ALARM DATA REGISTERS (WRITE ONLY)

$08

X

Alarm Seconds

$09

X

Alarm

$OA

X

X

Alarm Hours

FIGURE 7 6

Minutes

CLOCK CONTROL FORMAT

543

$10

Start/ Stop:

This bit high enables the clock counters. A low
resets all counter bits divider stage and inhibits
clock operation.

Line/XTAL:

This bit high, selects clock operation on the
50/60Hz input. If low, it enables crystal operation
If line operation is selected and the power sense
interrupt is enabled, operation is automatically
switched to crystal operation at power off. If a
rising edge is sensed on the VPS pin, line operation
is automatically selected. If necessary, the crystal
can then be tuned for battery-backup operation.

50/60 Hz:

This bit high, selects 50 Hz input; a low selects
60 Hz.

Clock Out:

These three bits specify one of seven output
frequencies:
0123-

Read/Reset:
XTAL Select

These pins select one of four possible crystal
frequencies as specified below
0- 4.194304 MHz
1 - 2.097152 MHz

2 - 1.048576 MHz
3 - 32768 Hz

3-631

Disable
1 Hz
2 Hz
50 Hz, 60 Hz,
or 64 Hz

4 XTAL
5 - XTAL %2
6 - XTAL %4
7 - XTAL %8

Ali register bits can be read, and are automatically
reset by POR except the clock out 2 bit If clock
mode input pin is low, clock out2 is reset on POR. If
ciock mode is high, ciock out 2 is set on POR, permitting the clock output pin to drive an MPU ciock
input.

MC68HC68T1

FIGURE 8 -

INTERRUPT CONTROL FORMAT

11

Watch Dog:

I

Power Down:

This bit high, initiates a power down. This applies a
CPU reset, sets the clock and PSE output pins low,
and disables the serial interface. Power down is
released if a previously enabled interrupt becomes
active or the VPS pin senses a rising edge,
signalling CPU power up.

Alarm:

This bit high enables comparator output to trigger
the interrupt circuit.

Power Sense'

This bit high enables sense circuits to detect main
power down via the 50/60 Hz input pin. This
activates a threshold detector centered at VDD.
Maximum time required to sense power down is 2.5
ms plus associated RC time constant of input
circuit. For this function, the crystal need not be
enabled, but proper selection/operation is required.
The circuit is automatically disabled after the
Interrupt.

FIGURE 9 -

x
$12

X

These four bits select periodic interrupt frequency Selectable options are listed below
0- Disable
1 - 2048 Hz XT AL Only
2 - 1024 Hz XTAL Only
3 - 512 Hz XTAL Only
4- 256 Hz XT AL Only
5 - 128 Hz XTAL Only
6 - 50 Hz, 60 Hz, or 64 Hz Line or XT AL
7 - 32 Hz XT AL Only
8 - 32 Hz XTAL Only
9 - 8 Hz XTAL Only
10 - 4 Hz XTAL Only
11 - 2 Hz
12 - 1 Hz
13 - Minute
14 - Hour
15 - Day

Read/ Reset:

All bits In the register can be read to as well as
being written to All bits are also rest by the
power-on-reset.

STATUS REGISTER (READ ONLY)

Test
Mode

Test Mode:

If clock/ RAM enters test mode, this bit goes
high. Test mode and this bit are reset by a POR
or a status register read.

First Time:

This bit high signifies that a POR has occurred.
This occurs if data in clock/ RAM is not correct
and should be initialized. This bit is reset by a
status register read.

Interrupt
True:

Periodic
Select:

This bit high enables walch-dog function. This
requires CPU to toggle chip enable input without a
serial transfer. Otherwise, the CPU RESET signal
resets CPU. Maximum time between toggling
depends on input clock selected, as listed below:
50 Hz
60 Hz
XT AL
Selected Clock
Maximum Time
10 ms
8.3 ms
7.8 ms

First
Time
Up

Int
True

Power
Sense
Int

Clk
Int

Power Sense:

Clock
Interrupt

Alarm
Interrupt:

This bit high signifies a valid power, clock or
alarm interrupt This bit is reset on a register
read

Reset:

3-632

Alarm
Int

This bit high indicates a power sense interrupt.
The MCU can now initiate a power down sequence. This bit is reset on a read.

This bit high indicates a clock-selected, interrupt.
This bit is reset on a read.

This bit set high indicates an alarm function interrupt. This bit is reset on a read
All register bits are reset by POR except the first
time up bit, which is set. The interrupt output is
reset on a register read.

MC68HC68T1

SYSTEMS CONFIGURATIONS
Examples of four system configurations (Figure 10 through 131 are shown in schematic diagrams

FIGURE 10 -

POWER ALWAYS ON SYSTEM

Bridge
AC Line

Regulator

S
:>

A

A

vv.

VOO
60/50HZ

?
>

.-l
I-

paR

IRQ

OJ

I

~

CE

::2'

SCK

RESET
""'-

PORT

U

VSS- CM

NOTE:

SCK

SOl

SOO

SOO

SOl

Clock circuit driven by line input frequency
circuit included to detect power failure

3-633

n-

CJ

VOS

u1 and t/>2 clock signals
required by the microprocessor, this clock generator is compatible
with 1.0, 1.5, and 2.0 MHz versions of the MC6800. Both the
oscillator and high capacitance driver elements are included along
with numerous other logic accessory functions for easy system
expansion.
Schottky technology is employed for high speed and PNP-buffered
inputs are employed for NMOS compatibility. A single +5 V power
supply, and a crystal or RC network for frequency determination
are required.

•

Typical MPU System with Bus Extenders
LSUFFIX
CERAMIC PACKAGE
CASE 620-02
GND +5 V

c:::J 4 x fo

MPU

T

PIN CONNECTIONS

ADDRESS
AND
CONTROL
BUS

DATA
BUS

X1

16

VCC

X2

i5

MPUq,1

Ext In

3

14

Reset Output

4 x fo

4

13

MPU q,2

2 x fo
Memory
Ready
Bus q,2

5

12

Power-On Reset

6

11

DMA/Ref Grant

7

10

DMA/Ref Req

Ground

B

9

Memory Clock

ORDERING INFORMATION
Device
I Temperature Range
Oto +700 C
MC6875L I
MC6875AL I
-55 to +125 0 C

3·637

I

Paek..e

I Ceramic

Dip

I Ceramic Dip

MC6875, MC6875A
ABSOLUTE MAXIMUM RATINGS (Unless otherwise noted TA
Rating

= 25 0 C.l

Symbol

Value

Unit

VCC

+7.0

Vdc

Input Voltage

VI

+5.5

Vdc

Operating Ambient Temperature Range
MC6875L
MC6875AL

TA

Storage Temperature Range

T stg

-65 to +150

°c

TJ

175

°c

Power Supply Voltage

Operating Junction Temperature

o to +70
·55 to +125

°c
NOTE:
Operation of the MC6875AL over the full military
temperature range (to maximum TA) will result in
excessive operating junction temperature.
The use of a clip on 16 pin heat sink similar to AAVID
Engineering, Inc., Model 5007 (RoCA = 18°CIW) is
recommended above TA = 95°C.

RECOMMENDED OPERATING CONDITIONS

Contact AAVID Engineering, Inc.
30 Cook Court
Laconia, New Hampshire 03246
Tel. (603) 524-4443

Rating
Power Supply VO,ltage
Operating Ambient Temperature Range

II

OPERATING DYNAMIC POWER SUPPLY CURRENT
Characteristic
Power Supply Currents
(VCC = 5.25 V, fosc = 8.0 MHz, VIL = 0 V, VIH = 3.0 V)
Normal Operation
(Memory Ready and DMA/Refresh Request Inputs at
High Logic State)
Memory Ready Stretch Operation
(Memory Ready Input at Low Logic State;
DMA/Refresh Request Input at High Logic State)
DMA/Refresh Request Stretch Operation
(Memory Ready Input at High Logic State;
DMA/Refresh Request Input at Low Logic State)

3·638

Symbol

Min

Typ

Max

Unit

ICCN

-

-

150

mA

ICCMR

-

-

135

mA

ICCDR

-

-

135

mA

MC6875, MC6875A

ELECTRICAL CHARACTERISTICS
(Unless otherwise noted specifications apply over recommended power supply and temperature ranges.
Typical values measured at Vee = 5.0 V and T A = 25 0 e.)
Characteristic
Output Voltage - High Logic State
MPU ¢1 and 1 AND <1>2 CHARACTERISTICS
Output Period (Figure 3)

I

Pulse Width (Figure 3)
(fo ~ 1.0 MHz)
(fo ~ 1.5 MHz)
(fo ~ 2.0 MHz)

tpWM

Total Up Time (Figure 3)
(fo ~ 1.0 MHz)
(fo ~ 1.5 MHz)
(fo ~ 2.0 MHz)

tUPM

ns

Delay Time Referenced to Output Complement (Figure 3)
Output High to Low State (Clock Overlap at 1.0 V)

tPLHM

0

-

-

ns

Delay Times Referenced to 2 x fo (Figure 4 MPU <1>2 only)
Output Low to High Logic State
Output High to Low Logic State

tPLHM2X
tpHLM2X

-

-

-

-

85
70

ns
ns

tTLHM
tTHLM

-

-

-

-

25
25

ns
ns

-

-

-

-

Transition Times (Figure 3)
Output Low to High Logic State
Output High to Low Logic State
BUS 2 CHARACTERISTICS
Pulse Width
(fo ~ 1.0
(fo ~ 1.5
(fa ~ 2.0

- Low Logic State (Figure 4)
MHz)
MHz)
MHz)

ns

tPWLB
430
280
210

Pulse Width - High Logic State
(fa ~ 1.0 MHz)
(fa ~ 1.5 MHz)
(fa ~ 2.0 MHz)

ns

tpWHB

Delay Times - (Referenced to MPU <1>1) (Figure 4)
Output Low to High Logic State
(fa ~ 1.0 MHz)
(fo ~ 1.5 MHz)
(fa ~ 2.0 MHz)
Output High to Low Logic State
(CL ~ 300 pF)
(CL ~ 100 pF)

450
295
235

-

-

-

-

480
320
240

-

-

-

-

25
20

-

+25
+40

ns
ns

-

ns

tPLHBMl
-

-

tPHLBMl

-

Delay Times (Referenced to MPU <1>2) (Figure 4)
Output Low to High Logic State
Output High to Low Logic State

tPLHBM2
tPHLBM2

-30
0

tTLHB
tTHLB

-

-

-

-

20
20

ns
ns

Symbol

Min

Typ

Max

Unit

Delay Times (Referenced to MPU 2) (Figure 4)
Output Low to High Logic State
Output High to Low Logic State

tPLHCM
tPHLCM

-50
0

Delay Times (Referenced to 2 x fo) (Figure 4)
Output Low to High Logic State
Output High to Low Logic State

tPLHC2X
tPHLC2X

-

tTLHC
tTHLC

-

Transition Times (Figure 4)
Output Low to High Logic State
Output High to Low Logic State

-

SWITCHING CHARACTERISTICS (continued)
Characteristic
MEMORY CLOCK CHARACTERISTICS

Transition Times (Figure 4)
Output Low to High State
Output High to Low State

3-640

-

-

-

-

+25
+40

ns
ns

65
85

ns
ns

25
25

ns
ns

MC6875, MC6875A

2 x fo CHARACTERISTICS
Delay Times (Referenced to 4 x fo) (Figure 4)
Output Low to High Logic State
Output High to Low Logic State

ns
ns

-

-

-

-

365
220

-

-

-

tTLH2X
tTHL2X

.-

-

25
25

ns
ns

Output Low to High Logic State
Output High to Low Logic State

tPLH4X
tPHL4X

-

-

-

-

50
30

ns
ns

Transition Time (Figure 4)
Output Low to High Logic State
Output High to Low Logic State

tTLH4X
tTHL4X

-

-

-

-

25
25

ns
ns

Set-Up Times (Figure 5)
Low Input Logic State
High Input Logic State

tSMRL
tSMRH

55
75

-

-

-

-

ns
ns

Hold Time (Figure 5)
Low Input Logic State

tHMRL

10

-

-

ns

Set-Up Times (Figure 6)
Low Input Logic State
High Input Logic State

tSDRL
tSDRH

65
75

-

-

-

-

ns
ns

Hold Time (Figure 6)
Low Input Logic State

tHDRL

10

-

-

ns

Delay Time Referenced to Memory Clock (Figure 6)
Output Low to High Logic State
Output High to Low Logic State

tPLHG
tPHLG

-15
-25

-

+25
+15

ns
ns

Transition Times (Figure 6)
Output Low to High Logic State
Output High to Low Logic State

tTLHG
tTHLG

-

-

-

-

25
25

ns
ns

tPLHR
tPHLR

-

-

-

-

1000
250

ns
ns

-

-

100
50

ns
ns

tPLH2X
tPHL2X

Delay Time (Referenced to MPU ct>1) (Figure 4)
Output High to Low Logic State
(fo ~ 1.0 MHz)
(fa = 1.5 MHz)

50
65

ns

tpHL2XMl

Transition Times (Figure 4)
Output Low to High Logic State
Output High to Low Logic State

-

4 x fo CHARACTERISTICS
Delay Times (Referenced to Ext. In) (Figure 4)

MEMORY READY CHARACTERISTICS

DMA/REFRESH REQUEST CHARACTERISTICS

DMA/REFRESH GRANT CHARACTERISTICS

RESET CHARACTERISTICS
Delay Time Referenced to Power-On Reset (Figure 7)
Output Low to High Logic State
Output High to Low Logic State
Transition Times (Figure 7)
Output Low to High Logic State
Output High to Low Logic State

tTLHR
tTHLR

-

DESCRIPTION OF PIN FUNCTIONS
•
•

2 x fa
OMA/AEF REO

- A free running oscillator at four times the MPU clock rate useful tor a system sync signal

•

BUS4>2

-

A free running oscillator at two times the MPU clock file
- An asynchronous Input used to freeze the MPU clocks in th~ 4>1 high, 4>2 low state tor

•

MEMORY CLOCK

-

•

POWER·ON RESET

•

RESET

•

X 1. X2

-

-

A synchronous output used to sVnchronlze the refresh or OMA operation to the MPU

MEMORY READY - An asynchronous input used to freeze the MPU clocks In the 4'1 low, 4>2 high state for slow
memory Interface

•

MPU 4>1
MPU4I2

- Capable of drilling the ¢/1 and 1i2 Inputs on two MC6800s

3-641

An output nomlnClolly

In

phase With MPU 412 which free runs dUfing a refresh request cycle

A Schmitt trigger mput which controls Reset. A capaCitor to ground IS required to set the
desired time constant. Internal 50 k resistor to Vee See General DeSign Suqgestlons for
Manual Reset Operation

dynamic memory refresh or cycle Ueal OMA (Direct Memory Access)

•

An output nominally In phase With MPU 1i2 haVing MC8T26A type drive capability

-

An output to the MPU and 1/0 dell Ices

-

PrOlllslon to attach a series resonant crystal or RC network

-

Allows driVing by an external TTL signal to synchrOnize the MPU to an external system

I

MC6875, MC6875A

FIGURE 1 - BLOCK DIAGRAM

X1

X2

In

I

BUS <1>2

Memory Ready 0-.:.(6_):-_+-_ _--1

(10)
DMA/Refresh 0-4---+--~
Request

Vcc
50 k

Reset (14)
Output 0 - + - - - - - - - - '

Pin 16 -- +5.0 Volts
Pin 8

-

Gnd

Power-On Reset

FIGURE 2 - TYPICAL HYSTERESIS CHARACTERISTIC
OF RESET FUNCTION

FIGURE 3 - TIMING DIAGRAM FOR
MPU 1>1 AND 1>2

5.0 ~-'--I-'--I-'----'-----'------'-----'~-'----'-------'

_ Vee

=

5.0

V-+-.-+--4--+--+---+---+---1

TA = 25 0 e

f--------

to

~----___<~

'" 3.01---+----+----/f----+--+--+4--4---+---+---j·

;

Cl

>

~

2.0I--__I------If-----IIf------I__

Cl

6 1.01---+----+----11----+---+---++--4---+---+---/
>
0L-_L-_L-_~_~_~_~_~_~-~-7

o

1.0

2.0

3.0

4.0

5.0

VOV

~

1.0 V

~

Clock Overlap
measurement point

VI. INPUT VOLTAGE (VOLTS), POWER-ON RESET PIN

3-642

MC6875, MC6875A

FIGURE 4 - TIMING DIAGRAM FOR NON·STRETCHED OPERATION
(Memory Ready and DMA/Refresh Request held high continuously)
Ext. In Input Voltage: 0 V to 3.0 V, f = 8.0 MHz, Duty Cycle = 50%, tTLHEX = tTHLEX = 5.0 n5

2.0 V

Ext. In

4 x fa

I

2 x fa

MPU <1>1

MPU <1>2

Bus <1>2
0.8 V

Memory Clock
0.8 V

OM AI Refresh

Grant

0.8 V

(Low)

3-643

0.8 V

MC6875, MC6875A

FIGURE 5 - TIMING DIAGRAM FOR MEMORY READY STRETCH OPERATION
(Minimum Stretch Shown)
Input Voltage: 3.0 to 0 V. tTHLMR = tTLHMR = 5.0 ns

Memory Ready

0.8 V

I

~

DMA/Refresh Request

DMA/Refresh Grant

(Low)

Irrelevant

MC6875, MC6875A

FIGURE 6 - TIMING DIAGRAM FOR DMA/REFRESH REQUEST STRETCH OPERATION
(Minimum Stretch Shown)
Input Voltage: 3.0 to 0 V, tTHLDR = tTLHDR = 5.0 ns

Memory Ready

~

Irrelevant

I
-+---- tpw DMA

1.5

=

fu ----.\-

DMA/Refresh Grant
0.8 V

0.8 V

3-645

MC6S75, MC6S75A

FIGURE 7 - POWER ON RESET
Input Voltage: 0 to 5.0 V. f = 100 kHz - Pulse Width = 1.0 ~5. tTLH

= tTHL = 25 ns

5.0 V ------+----+.~---------------___,.

Power·On Reset

OV - - - - - - '

I

0.8 V

0.8 V

3-646

MC6875, MC6875A

FIGURE 8 - LOAO CIRCUITS

For MPU (.1 and MPU 1.2

+5.0 V
RLL

RLL=18k

68

CL °
All diodes are 1 N916
or equivalent

MPU <1>1 CL

= 35

MPU <1>2 CL

= 70 pF,

pF, RD
RD

300 pF

I

All diodes are lN916
or equivalent

20 n
= 15 n

=

For 4 x fo, 2 x fo, Memory Clock and DMA/Refresh Grant

I

For Reset Output

+5.0 Volts

RLL

CL O
100 pF

I

240

RLL = 1_2 k

RLH
4.7 k
All diodes are lN916
or equ ivalent

All diodes are 1 N916
or equivalent

• Load capacitance includes fixture and probe capacitance

NOTE:
Operation of the MC6875AL over the full military temperature range (to maximum T A) will result in excessive
operating junction temperature_

Contact AAVID Engineering, Inc_
30 Cook Court

The use of a clip on 16 pin heat sink similar to AAVID
Engineering, Inc_, Model 5007 (ReCA = 18o C/W) is

Laconia, New Hampshire 03246
TeL (603) 524-4443

recommended above T A "" 95 0 C_

3-647

MC6875, MC6875A

APPLICATIONS I N FORMATION
FIGURE 9 - TYPICAL RC FREQUENCY versus VOLTAGE
+8.0

~ +6.0

'"z
~

+4.0

~

+2.0

~

v

... V

UJ

V

V

/
/
/""

fo = 1.0 MHz @Vee=5.0V

!--

TAI=25'~

!---

-

V
-2.0
4.5

I

5.0

5.5
6.0
Vee, SUPPLY VOLTAGE (VOLTS)

7.0

6.5

FIGURE 10 - TYPICAL RC FREQUENCY
versus TEMPERATURE
/

+1.0

/
/

~ +0.8

/

UJ

'"~
Z

+0.6

/

/

>-

/

'-" +04
~
.

/
./

~ +0.2

1
and <1>2 clocks to suppress overshoot and reflections.
The VCC pin (pin 16) of the MC6875 should be
bypassed to the ground pin (pin 8) at the package with a
0.1 /J.F capacitor. Because of the high peak currents
associated with driving highly capacitive loads, an adequately large ground strip to pin 8 should be used on the
MC6875. Grounds should be carefully routed to minimize
coupling of noise to the sensitive oscillator inputs. Unnec·
essary grounds or ground planes should be avoided near
pin 2 or the frequency determining components. These
components should be located as near as possible to the
respective pins of the MC6875. Stray capacitance near
pin 2 or the crystal, can affect the frequency. The can of
the crystal should not be grounded. The ground side
of the crystal or the C of the R-C oscillator should be connected as directly as possible to pin 8.
Unused inputs should be connected to VCC or ground.
Memory Ready, DMA/Refresh Request and Power-On
Reset should be connected to VCC when not used.
The External Input should be connected to ground
when not used.

I

Ext In

_

-

4 X fo = Crystal frequency

4 X fo =\ _ _
1 __
21rJLTCT

1 k 0'15 k

7

8 9 10

4 x fo, FREQUENCY (MHz)

3-648

• Required by some
Crystal manufacturers

2.5 JLH ,,;; LT ,,;; 22 JLH
75 pF ,,;; CT ,,;; 200 pF
RT = lkn

MC6S75, MC6S75A

TABLE 1 - OSCILLATOR COMPONENTS
TANK CIRCUIT
PARAMETERS

APPROXIMATE
CRYSTAL PARAMETERS

CTS KNIGHTS
400 REIMANN AVE.
SANDWICH, I L
60548
(815) 786-8411

McCOY ELECT. CO.
WATTS & CHESTNUTS STS.
MT. HOLL Y SPRING, PA
17065
(717)486-3411

LT
jLH

CT

RS
Ohms

Co

C1

pF

pF

mpF

fo
MHz

10

150

15-75

3-6

12

4.0

MP-04A
• 390 pF

113-31

4.7

82

8-45

4-7

23

8.0

MP'()80
• 47 pF

113-32

Inductors may be obtained from: Coileraft, Cary, IL 60013

FIGURE 13
RC OPERATION
(1)

. - - - - - - - j Xl
EXTERNAL INPUT
R

(1)

(2)

Xl

X2

I-=-

C

MC6875
X2
Ext In

MC6875
(3)

-=-

Ext In
51

External Pulse
Generator

To precisely time a crystal to desired frequency, a
variable trimmer capacitor in the range of 7 to 40 pF
would typically be used. Note it is not a recommended
practice to tune the crystal with a parallel load capacitance.
The table above shows typical values for CT and LT,
typical crystal characteristics, and manufacturers' part
numbers for 4.0 and 8.0 megahertz operation.
The MC6875 will function as an R-C oscillator when
connected as shown in Figure 13. The desired output
frequency (M¢1) is approximately:
Formula

320

4 x fo "'" C (R+ .27) + 23

TYCO CRYSTAL PRODUCTS
3940 W. MONTECITO
PHOENIX, AZ
85019
(602) 272-7945
150-3260
150-3270

(312) 639·2361

a solid VOL output level until VCC has reached 3.5 to
4.0 V, During this time transients may appear on the
clock outputs as the oscillator begins to start. This
happens at approximately VCC = 3 V. At some VCC level
above that, where Reset Output goes low, all the clock
outputs will begin functioning normally. This phenomenon of the start-up sequence should not cause any
problems except possibly in systems with battery back-up
memory. The transients on the clock lines during the
time the Reset Output is high impedance could initiate
the system in some unknown mode and possibly write
into the backup memory system. Therefore in battery
backup systems, more elaborate reset circuitry will
be required.
Please note that the Power-On Reset input pin of the
MC6875 is not suitable for use with a manual MPU reset
switch if the DMA/Ref Req or Memory Ready inputs are
going to be used. The power on reset circuitry is used to
initialize the internal control logic and whenever the
input is switched low, the MC6875 is irresponsive to
the DMA/Ref Req or Memory Ready inputs. This may
result in the loss of dynamic memory and/or possibly
a byte of slow static memory. The circuit of Figure 14
is recommended for applications which do not utilize the
DMA/Ref Req or Memory Ready inputs. The circuit of
Figure 15 is recommended for those applications that do.
FIGURE 14 - MANUAL RESET FOR APPLICATIONS NOT USING
DMA/REFRESH REQUEST OR MEMORY READY INPUTS
VCC

C in picofarads
R in K ohms
4 x fo in Megahertz

(See Figure 11)
It would be desirable to select a capacitor greater than
15 pF to minimize the effects of stray capacitance. It is
also desirable to keep the resistor in the 1 to 5 k n
range. There is a nominal 270 n resistor internally at
X 1 which is in series with the external R. By keeping
the external R as large as possible, the effects due to
process variations of the internal resistor on the frequency
will be reduced. There will, however, still be some
variation in frequency in a production lot both from
the resistance variations, external and internal, and
process variations of the input switching thresholds.
Therefore, in a production system, it is recommended
a potentiometer be placed in series with a fixed R
between X 1 and X2.
POWER-ON RESET
As the power to the MC6875 comes up, the Reset
Output will be in a high impedance state and will not give

3-649

C

12

4\
~

:e00

14

40

ID

U

0
0

00
ID

U

~

~

Manual Reset Switch

FIGURE 15 - MANUAL RESET FOR SYSTEMS USING
DYNAMIC RAM OR SLOW STATIC RAM IN CONJUNCTION
WITH MEMORY READY OR DMA/REFRESH REQUEST INPUTS
VCC
1/474LS08
47 k

o

Ii
<0
U

~

~

Manual Reset
.:LSWitCh

I

®

MCST26A
MC6880A

MOTOROLA

QUAD THREE-STATE BUS TRANSCEIVER

I

This quad three-state bus transceiver features both excellent MOS
or MPU compatibility, due to its high impedance PNP transistor
input, and high-speed operation made possible by the use of Schottky
diode clamping_ Both the -48 rnA driver and -20 rnA receiver outputs are short-circu it protected and employ three-state enabl ing inputs.
The device is useful as a bus extender in systems employing the
M6800 family or other comparable MPU devices. The maximum
input current of 200 IlA at any of the device input pins assures
proper operation despite the limited drive capability of the MPU
chip. The inputs are also protected with Schottky-barrier diode
clamps to suppress excessive undershoot voltages.
The MC8T26A is identical to the NE8T26A and it operates from
a single +5 V supply.
•

High Impedance Inputs

•

Single Power Supply

•

High Speed Schottky Technology

QUAD THREE-STATE
BUS TRANSCEIVER
MONOLITHIC SCHOTTKY
INTEGRATED CIRCUITS

,,LSUFFIX

CERAMIC PACKAGE
CASE 620-02

_

!
16

•

Three-State Drivers and Receivers

•

Compatible with M6800 Family Microprocessor

1

P SUFFIX
PLASTIC PACKAGE
CASE 648-05

PIN CONNECTIONS - MC8T26A

MICROPROCESSOR BUS EXTENDER APPLICATION

MC6880A

(Clock)

GND +5 V

~'1

<:>2
Receiver
Enable

VCC

Input

Receiver
Output
1

Driver
Enable
Input

2

Receiver
Output

4
Bus4
Driver
Input

4

AND

Receiver
Output

CONTROL

3

BUS
Driver
Input

Bus3

7

2
Gnd

ORDERING INFORMATION
Alternate

Temperature
Range

Package

MC6880AL

MC8T26AL

0 to +75°C

Ceramic DIP

MC6880AP

MC8T26AP 0 to +75 C

Device

3-650

Plastic DIP

MC8T26A, MC6880A

MAXIMUM RATINGS

(T A; 250 C unless otherwise noted.)
Symbol

Value

Unit

VCC

8.0

Vdc

Input Voltage

VI

5.5

Vdc

Junction Temperature
Ceramic Package
Plastic Package

TJ

Rating
Power Supply Voltage

°c
175
150

Operating Ambient Temperature Range

TA

o to +75

Storage Temperature Range

T stg

-65 to+150

ELECTRICAL CHARACTERISTICS

°c
vc

(4.75 V";; VCC';; 5.25 V and OOC.;; TA';; 75 0 C unless otherwise noted.)

Characteristic
I nput Current - low logic State
(Receiver Enable Input, Vll(RE); 0.4 V)
(Driver Enable Input, VILlDE) ; 0.4 V)
(Driver Input, Vll(D); 0.4 V)
(Sus (Receiver! Input, VILIS); 0.4 V)
Input Disabled Current - low logic State
(Driver Input, VILlD); 0.4 V)

Symbol

Min

Typ

Max

Unit

IILlRE)
Ill(DE)
IILlD)
II LIB)

-

-

-

-

-200
-200
-200

iJ A

-

-

-

-200

-

-

-25

!lA
iJ A

IILlD) DIS

Input Current·High logic State
(Receiver Enable Input, VIH(RE); 5.25 V)
(Driver Enable Input, VI H(DE)'; 5.25 V)
(Driver Input, VIH(D); 5.25 V)

IIH(RE)
IIH(DE)
IIH(D)
IIH(S)

(Receiver Input, VIH(S) = 5.25 V)
I nput Voltage - low logic State
(Receiver Enable Input)
(Driver Enable Input
(Driver Input)

V I LI RE)

(Receiver Input)
Input Voltage - High logic State
(Receiver Enable Input)
(Driver Enable Input)
(Driver Input)
(Receiver Input)

-

-

25
25
25

-

-

100

-

-

-

-

-

-

VILlDE)
VILlD)

-

-

-

-

0.85
0.85
0.85

VILIS)

-

-

0.85

VIH(RE)
VIH(DE)
VIH(D)

2.0
2.0
2.0

-

-

-

-

-

-

VIH(S)

2.0

-

-

V

V

Output Voltage - low logic State
(Bus Driver) Output, IOLlB) = 48 mAl
(Receiver Output, 10l(R) = 20 mAl
Output Voltage - High logic State
(Sus (Driver) Output, IOH(S) = -10 mAl
(Receiver Output, 10H(R) = -2.0 mAl

0.5
0.5

V

3.1
3.1

-

V

-

100
100

!lA

-100
-100

!lA

-1.0
-1.0
-1.0

V

VOlIB)
VOLlR)

-

-

-

-

VOH(S)
VOH(R)

2.4
2.4
3.5

(Receiver Output, IOH(R) ; -100 !lA, VCC = 5.0 V)

-

Output Disabled leakage Current - High logic State
(Bus Driver) Output, VOH (B) = 2.4 V)
(Receiver Output, VOH(R) = 2.4 V)

10HLlS)
10Hl(R)

-

-

-

-

Output Disabled leakage Current - low logic State
(Sus Output, VOLtS) ; 0.5 V)
(Receiver Output, VOLlR) = 0.5 V)

IOll(B)
10ll(R)

-

-

Input Clamp Voltage
(Driver Enable Input IID(DE) ; -12 mAl
(Receiver Enable Input IIC(RE) = +12 mAl
(Driver Input IICID); ·-12 mAl

VICIDE)
VIC(RE)
VIC(D)

-

-

-

-

-

-

Output Short·Circuit Current, VCC ; 5.25 V (1)
(Sus (Driver) Output)
(Receiver Output)

10S(S)
10S(R)

-50
-30

-

-150
-75

mA

-

ICC

-

-

87

mA

Power Supply Current
(VCC = 5.25 V)
(1) Only one output may be short·circuited at a time.

3-651

-

I

MC8T26A, MC6880A

SWITCHING CHARACTERISTICS

(Unless otherwise noted, specifications apply at T A = 25 0 e and Vee = 5.0 V)
Symbol

Figure

Min

Max

Unit

Propagation Delay Time from Receiver (Bus) I nput to
High Logic State Receiver Output

tPLH(R)

1

-

14

ns

Propagation Delay Time from Receiver (Bus) I nput to
Low Logic State Receiver Output

tPHL(R)

1

-

14

ns

Propagation Delay Time from Driver I nput to
High Logic State Driver (Bus) Output

tpLH(D)

2

-

14

ns

Propagation Delay Time from Driver I nput to
Low Logic State Driver (Bus) Output

tPHL(D)

2

-

14

ns

Propagation Delay Time from Receiver Enable Input to
High Impedance (Open) Logic State Receiver Output

tPLZ(RE)

3

-

15

ns

Propagation Delay Time from Receiver Enable Input to
Low Logic Level Receiver Output

tpZL(RE)

3

-

20

ns

Propagation Delay Time from Driver Enable Input to
High Impedance Logic State Driver (Bus) Output

tPLZ(DE)

4

-

20

ns

Propagation Delay Time from Driver Enable Input to
Low Logic State Driver (Bus) Output

tPZL(DE)

4

-

25

ns

Characteri stic

I

FIGURE 1 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY FROM
BUS (RECEIVER) INPUT TO RECEIVER OUTPUT, tPLH(R) AND tPHL(R)

tTLH';;; 5.0 ns

tTHL';;; 5.0 ns

Input

OV
Input Pulse Frequency = 10 MHz
Duty Cycle = 50%

tpHL(R)
VOH---"""""
Output

Vo L - - - - - - ' - - - - - - - - - - - '

To Scope
(Input)

2.6 V

To Scope
( Input)

Receiver

~
Input

92
Receiver
Input

1N916
or Equ iv.

Output

Driver
Input
Pulse

Generator

51

1.3 k
Driver
Enable
Input

3-652

30 pF

MC8T26A, MC6880A
FIGURE 2 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
DRIVER INPUT TO BUS (DRIVER) OUTPUT. tPLH(D) AND tPHL(D)

tTHL" 5.0 ns

2.6V----Input

OV----..I
Input Pulse Frequency
Duty Cycle

tpHL(D)

=

=

10 MHz
50%

VOH-----Output
VOL---------~---------J

2.6 V

2.6 V

To Scope
(Input)

To Scope
(Output)

Driver
Enable
Input

I

30

Driver

Driver
Input

(Bus)

1N916
or Equiv.

Output

Receiver
Output
51

300 pF

260

~
~
Input

FIGURE 3 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
RECEIVER ENABLE INPUT TO RECEIVER OUTPUT. tPLZ(RE) AND tpZL(RE)

tTHL';; 5.0 ns

.
r-

Input

tPZL(REl

"'3.5 V

------+------:_---------,.

VOL----~

To Scope
(Input)

Input Pulse Frequency = 5.0 MHz
Duty Cycle = 50%

1.5 V

Output

2.6 V
To Scope
(Outputl

Receiver ·Enable
Input

5.0 V

240

2.4 k

Receiver

Output

Pulse
Generator

51

5.0 k

.3-653

30 pF

1N916
or Equiv.

MC8T26A, MC6880A

FIGURE 4 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIMES FROM
DRIVER ENABLE INPUT TO DRIVER (BUS) OUTPUT, tPLZ(DE) AND tpZL(DE)

tTHL";;5.0ns

2.6 V
Input

-----t-,-~~,.-------1

o V ___

~_-"T I

Input Pulse Frequency = 5.0 MHz
Duty Cycle = 50%

"'3.5V---~

Output
VOL------~------------J

I

+2.6 V
To Scope
(Output)

Driver Enable
Input

5.0 V

70

2.4 k

Driver
Input

Driver (Bus)
Pulse

51

Generator

Output

Receiver
Output

1N916
5.0 k

~

300 pF

0:-

Equiv.

Enable
Input

FIGURE 5 - BIDIRECTIONAL BUS APPLICATIONS

Receiver
Outputs

Receiver
Outputs

Driver
Inputs

Driver
Inputs

To Other
Drivers/ Receivers

Driver
Enable

3-654

Receiver
Enable

®

MC3482A1MC6882A
MC3482BIMC6882B

MOTOROLA

OCTAL THREE-STATE BUFFER/LATCH
This series of devices combines four features usually found
desirable in bus-oriented systems: 1) High impedance logic inputs
insure that these devices do not seriously load the
bus; 2) Three-state logic configuration allows buffers not being
utilized to be effectively removed from the bus; 3) Schottky
technology allows for high-speed operation; 4) 48 mA drive
capability.
•

Inverting and Non-Inverting Options of Data

•

SN74S373 Function Pinouts

•

Eight Transparent Latches/Buffers in a Single Package

•

Full Parallel-Access for Loading and Reloading

•

Buffered Control Inputs

•

All Inputs Have Hysteresis to Improve Noise Rejection

OCTAL THREE-STATE
BUFFER/LATCH

LSUFFIX
CASE 732-03

•

High Speed - 8.0 ns (Typ)

•

Three-State Logic Configuration

•

Single +5 V Power Supply Requirement

•

Compatible with 74S Logic or M6800 Microprocessor Systems

•

High Impedance PNP Inputs Assure Minimal Loading of the Bus

INPUT EQUIVALENT
CIRCUIT

MICROPROCESSOR BUS EXTENDER APPLICATION

(Clock)
Gnd +5 V q,1 q,2

OUTPUT EQUIVALENT
CIRCUIT

Vee

ORDERING INFORMATION

3-655

I

MC6882A, MC6882B, MC3482A, MC3482B

MAXIMUM RATINGS (T A

= 2SoC unless otherwise noted)

Rating
Power Supply Voltage
Input Voltage
Operating Ambient Temperature Range
Storage Temperature Range
Operating Junction Temperature

Symbol

Value

Unit

VCC
VI
TA
T stg

8.0
5.5
o to +75
-65 to +150

Vdc
Vdc
uc
°c
°c

TJ
175

Ceramic Package

ELECTRICAL CHARACTERISTICS (Unless otherwise noted OOC';;;T A';;; 75°C and 4 75 V';;; VCC';;; S 25 V)
Character istic

II

Symbol

Min

Typ

Max

Unit

Input Voltage - High Logic State'
(VCC = 4.75 V, T A = 25°C)

VIH

2.0

-

-

V

Input Voltage - Low Logic State
(VCC = 4.75 V, T A = 25 0 C)

VIL

-

-

0.8

V

Input Current - High Logic State
(Vce = 5.25 V, VIH = 2.4 V)

IIH

-

-

40

IJ.A

IlL

-

-

-250

IJ.A

Output Voltage - High Logic State
(VCC = 4.75 V, 10H = -20 mAl

VOH

2.4

-

-

V

Output Voltage - Low Logic State
(lOL = 48 mAl

VOL

-

-

0.5

V

Output Current - High Impedance State
(VCC = 5.25 V, VOH = 2.4 V)
(VCC = 5.25 V, VOL = 0.5 V)

102
-

-

-

100
-100

Output Short-Circuit Current
(VCC = 5.25 V, Va = 0) (only one output can be shorted at a time)

lOS

-30

-80

-130

mA

Power Supply Current
(VCC = 5.25 V)

ICC

-

130
150

rnA

V IK

-

-1.2

V

Input Current - Low Logic State
(VCC = 5.25 V, VIL = 0.5 V, VIL(OE)

= 0.5 V)

MC3482A/MC6882A
MC34828/MC68828

Input Clamp Voltage
(VCC = 4.75 V, 11K = -12 rnA)

3-656

IJ.A

-

MC6882A, MC68828, MC3482A, MC34828

SWITCHING CHARACTERISTICS (V CC = 5.0 V, o°c.; T A'; +75°C, unless otherwise noted, typical
Characteristics

Symbol
Min

Propagation Delay Times
Data to Output
Low to High
CL=50pF
CL = 250 pF
CL=375pF
CL = 500 pF
High to Low
CL = 50 pF
CL=250pF
CL=375pF
CL = 500 pF
Propagation Delay Times
Latch Disable (Low to High)
to Output
Low to High
CL = 50 pF
High to Low
CL = 50 pF
Propagation Delay Times
(CL = 20 pF)
High Output Level to High Impedance
Low Output to High Impedance
High Impedance to High Output
High Impedance to Low Output

Typ

Max

Min

Unit

Typ

Max
ns

tPLH(DI
4.0

_.

~

10

9.0
12
14
16

16
20

4.0

9.0
12
14
16

16
20
22
24

24

10

8.0
15
18
21

16
22
25
28

4.0

-

8.0
15

-

17

14

18

16
22
24
27

~

22

~

tpHL(DI
4.0
~

-

16

I

ns

tpLH(LI
tpHL(LI

-

22

30

-

18

30

-

23

30

-

14

25
ns

tPHZ(QE)
tPLZ(QE)
tpZH(QE)
tpZL(QE)

-

-

-

15
27
16
20

8.0
20
9.0
13

-

@ T A = 25°C.1

MC3482BI
MC6882B

MC3482A1
MC6882A

Symbol

13
23
18
16

6.0
15
11
9.0

-

AC SETUP CHARACTERISTICS (V cc = 5.0 V, O°C .; T A'; +75°C, unless otherwise noted, typical
Characteristic

T A = 25°C.1

@

MC3482BI
MC6882B

MC3482A1
MC6882A

Unit

Min

Typ

Max

Min

Typ

Max

0

-

7.0

0

-

ns

-

8.0

-

-

ns

-

-

15

-

ns

Setup Time
(Data to Negative Going Latch Enablel

tsu(D)

10

Hold Time
(Data to Negative Going Latch Enablel

th(D)

10

Minimum Latch Enable Pulse Width
(High or Low)

tW(LI

-

~

15

MC6882A, MC6882B, MC3482A, MC3482B

PIN CONNECTIONS AND TRUTH TABLES

MC34828/MC68828

MC3482A/MC6882A

I

Output
Enable

Latch

Input

Output

Output
Enable

Latch

Input

Output

0

1

0

1

0

1

0

0

0

1

1

0

0

1

1

0

0

X

Qo

0

0

X

1

X

X

Z

1

X

X

3-658

1
Q

o

Z

MC6882A, MC6882B, MC3482A, MC3482B

FIGURE 2 - WAVEFORMS FOR PROPAGATION DELAY
TIMES DATA TO OUTPUT

FIGURE 1 - TEST CIRCUIT FOR SWITCHING CHARACTERISTICS

, - - - - -.......- - - - - - 3 V

To Scope
Output

To Scope (I nput)

Closed for
Input or

tPLZ(OE), tPZL(OE) only

Enable

+5 V
1 k
1 N3064

50

Output

MC3482A/MC6882A

or Equivalent

Output
1.0 k
CL Includes Probe and
Jig Capacitance

MC3482B/MC6882B _ _ _oJ

1

Closed for
tPHZ(OE),tPZH(OE) only

Input Pulse Conditions

tTHL'TLH<5ns
1.0 MHz

f

FIGURE 3 - WAVE FORMS FOR AC SETUP AND
LATCH DISABLE TO OUTPUT DELAY

Latch

Input
(Data) .;,...:o""",-,~",+,-~~

Output

_ _ _-oJ

FIGURE 4 - WAVEFORMS FOR PROPAGATION DELAY
TIMES - OUTPUT ENABLE TO OUTPUT

II

®

SN74LS783
MC6883

MOTOROLA
Advance Infor:rnation

SYNCHRONOUS
ADDRESS
MUL TIPLEXER

SYNCHRONOUS ADDRESS MULTIPLEXER
The SN74LS783/MC6883 brings together the MC6809E
(MPU), the MC6847 (Color Video Display Generator) and dynamic RAM to form a highly effective, compact and cost effective computer and display system.

LOW POWER SCHOTTKY

• MC6809E, MC6800, MC6801 E, MC68000 and MC6847 (VDG)
Compatible
• Transparent MPUIVDG/Refresh

I

• RAM size Static)

4K, 8K, 16K, 32K or 64K Bytes (Dynamic or

• Addressing Range -

96K Bytes

• Single Crystal Provides All Timing

l"~'"
~

40

• Register Programmable:
VDG Addressing Modes
VDG Offset (0 to 64K)
RAM Size
Page Switch
MPU Rate (Crystal 7 16 or 7 8)
MPU Rate (Address Dependent or Independent)

I

•

"

"~:;

1

NSUFFIX
PLASTIC PACKAGE
CASE 711

1

4~SUFFIX

CERAMIC PACKAGE
CASE 734

• System "Device Selects" Decoded 'On Chip'
• Timing is Optimized for Standard Dynamic RAMs

• + 5.0 V Only Operation
• Easy Synchronization of Multiple SAM Systems

PIN ASSIGNMENT

• DMA Mode

SYSTEM BLOCK DIAGRAM

TV Display Section
is Optional

Address

To
ROMs
and
I/O

AQ·A15

40
39

3

38

4

37

6

35 (RAS1)

36
7

34

8

33

9

32

10

31

11

30

12

29

13

28

14

27

15

26

16

25

DYNAMIC

17

24

RAM

18

23

19

22

20

21

Q~----I

MC6B09E

MPU

Data

1
2

4K, BK, 16K
32K or 64K
BYTES

This document contains information on a new product. Specifications and information herein
are subject to change without notice.

3-660

SN74LS783, MC6883
MAXIMUM RATINGS (TA

= 25°C unless otherwise noted.)

Symbol

Value

Unit

VCC

-0.5to +7.0

Vdc

Input Voltage (Except OSCln)

VI

-0.5 to 10

Vdc

Input Current (Except OSCln)

II

- 30 to + 5.0

mA

Vo

-0.5to +7.0

Vdc

Rating
Power Supply Voltage

Output Voltage
Operating Ambient Temperature Range

o to

- 65 to + 150

°c
°c

TA

Storage Temperature Range

Tstg

+ 70

Input Voltage OSCln

VIOSCln

-0.5 to VCC

Vdc

Input Current Oscln

II0sCIn

-0.5 to +5.0

mA

GUARANTEED OPERATING RANGES
Parameter

Symbol

Min

Typ

Max

VCC

4.75

5.0

5.25

V

Operating Ambient Temperature Range

TA

0

25

75

°c

Output Current High
RASO. RAS1. CAS. WE
All Other Outputs

10H

Output Current Low
RASO. RAS1. CAS. WE
VClk

10L

Supply Voltage

mA

-

-

-

-1.0
-0.2
mA

-

All Other Outputs

Unit

-

8.0
0.8
4.0

DC CHARACTERISTICS (Unless otherwise noted specifications apply over recommended power supply and
temperature ranges.)
Characteristic

Symbol

Min

Typ

Input Voltage -

High Logic State

VIH

2.0

-

V

Input Voltage -

Low Logic State

VIL

-

-

0.8

V

Input Clamp Voltage
(VCC = Min. lin = -18 mAl All Inputs Except OSCln

VIK

-

-

-1.5

V

Input Current - High Logic State at Max Input Voltage
(VCC = Max. Vin = 5.25 V) VClk Input
(VCC = Max. Vin = 5.25 V) DAO Input
(VCC = Max. Vin = 5.25 V OSCln = Gnd) OSCOut Input
(VCC = Max. Vin = 7.0 V) All Other Inputs Except OScin

II

-

-

-

-

200
100
250
100

-

-

20

-

-1.2
-60
-8
-.4

Input Current High Logic State
(VCC = Max. Vin = 2.7 V)
Input Current (VCC = Max.
(VCC = Max.
(VCC = Max.
(VCC = Max.

All Inputs Except VClk.
DAO OSCln. OSCOut

Max

fLA

-

fLA

IIH

Low Logic State
Vin = 0.4 V) DAO Input
Vin = 0.4 V) VClk Input
Vin = 0.4 V. OSCln = Gnd) OSCOut Input
Vin = 0.4 V) All Other Inputs Except OSCln

IlL

mA

-

Output Voltage - High Logic State
(VCC = Min. 10H = -1.0 mAl RASO. RAS1. CAS. WE
(VCC = Min. 10H = -0.2 mAl E. Q
(VCC = Min. 10H = - 0.2 mAl All Other Outputs

VOH(C)
VOH(E)
VOH

Output Voltage - Low Logic State
(VCC = Min. 10L = 8.0 mAl RASO. RAS1. CAS. WE
(VCC = Min. 10L = 4.0 mAl E. Q Outputs
(VCC = Min. IOL = 0.8 mAl VClk Output
(VCC = Min. 10L = 4.0 mAl All Other Outputs

VOL(C)
VOL(E)
VOL(V)
VOL

Units

- 30

-

-

-

-

V

-

-

-

-

-

-

-

-

-

-

0.5
0.5
0.6
0.5

3.0
VCC - 0.75
2.7

V

-

Power Supply Current

ICC

-

Output Short-Circuit Current

lOS

30

3-661

-

180

230

mA

-

225

mA

I

SN74LS783,MC6883
AC CHARACTERISTICS (4.75 V",;VCC",;5.25 V and 0",;TA",;70°C, unless otherwise noted).
Symbol

Characteristic

Propagation Delay Times
(See Circuit in Figure 9) Oscillator-In "'-- to Oscillator-Ou~ td(OL-OH)
Oscillator-In J to Oscillator-Oui"-- td(OH-OL)
(CL
(CL

= 195 pF) AO thru A15 to ZO, Z1, Z2 thru Z7
= 30 pF) AO thru A15, R/W to SO, S1, S3

(CL
(CL

= 95 pF) Oscillator-Out "'-- to RASO J
= 95 pF) Oscillator-Out "'-- to RASO "'= 95 pF) Oscillator-Out "-to RAS1 J
= 95 pF) Oscillator-Out "'--to RAS1 "'= 195 pF) Oscillator-Out " - to CAS J
= 195 pF) Oscillator-Out "'-- to CAS "'= 195 pF) Oscillator-Out " - to WE J
= 195 pF) Oscillator-Out "'-- to WE "'= 100 pF) Oscillator-Out "'-- to E J
= 100 pF) Oscillator-Out "'-- to E "'-= 100 pF) Oscillator-Out "'-- to 0 J
= 100 pF) Oscillator-Out "'-- to 0 "'= 30 pF) Oscillator-OutJ to VClk f
= 30 pF) Oscillator-Out J to VClk "'-

(CL
(CL
(CL
(CL
(CL
(CL

I

(CL
(CL
(CL
(CL
(CL
(CL

Setup Time for AO thru A15, R/W
Hold Time for AO thru A15, R/W

Rate
Rate

=

Rate
Rate

=

=

=

Max

Units
ns

-

3.0
20

-

28
18

td(OL-ROH)
td(OL-ROL)

-

20
18

td(OL-R1 H)
td(OL-R1L)

-

22
20

td (OL-CH)
td(OL-CL)

-

-

-

-

-

-

20
20

-

22
40

-

55
25

-

td(OL-OH)
td(OL-OL)

-

td(OH-VH)
td(OH-VL)

-

50
65

-

td(OL-AR)
td(OL-AC)

-

36
33

-

-

-

td(OL-EH)
td(OL-EL)

= 195 pF) Oscillator-Out " - to Row Address
= 195 pF) Oscillator-Out " - to Column Address
(CL = 15 pF) Oscillator-Out " - to DAO J Earliest!1)
(CL = 15 pF) Oscillator-Out " - to DAO J Latest(1)
(CL = 95 pF on RAS, CL = 195 pFon CAS) CAS "'-- to RASJ

Typ

td(A-Z)
td(A-S)

td(OL-WH)
td(OL-WL)

(CL
(CL

Min

-

-

55
25

-

-

-

td(OL-DH)
td(OL-DH)

-

-15
+15

td(CL-RH)

-

208

-

716
8

tsu(A)

-

28
28

-

ns

716
7 8

th(A)

-

30
30

-

ns

2.0

5.0

6.0

fLs

Width of HS Low 2

twL(HS)

-

Notes: 1. When using the SAM with an MC6847, the rising edge of DAO is confined within the range shown in the timing diagrams (unless the
synchronizing process is incomplete. I The synchronization process requires a maximum of 32 cycles of OSCOut for completion.
2. tWL(HSI wider than 6.0 fJ.S may yield more than 8 sequential refresh addresses.

FIGURE 1 -

PROPAGATION DELAY TIMES
VERSUS LOAD CAPACITANCE

40

g

30
td IOL·R1L1

~

;:::
>- 20

;j
0

z:

0

;:::

~

-

L~ p-r

~
10

'" td IOL·CLI

td (OL·ROLI

«
Q

--

~

~
50

100

200
300
CL, LOAD CAPACITANCE IpFI

3-662

400

500

SN74LS783, MC6883
PIN DESCRIPTION TABLE
~
~

0

Q.

gc:
0

0

"'C

c:

."

:::ell

(/)

.t;

ii:

"'C
c:(

c:

....:::I

c..

1-=

:::l
Q.

~

No.

VCC
Gnd

40
20

Apply + 5 volts ± 5%. SAM draws less than 230 mAo
Return Ground for + 5 volts.

A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
AO

36
37
38
39
1
2
3
4
24
23
22
21
19
18
17
16

Most Significant Bit.

R/W

15

MPU READ or WRITE. This signal comes directly from the MPU and is used to enable writing
to the SAM control register, dynamic RAM (via WE)' and to enable device select #0.
Apply 14.31818* MHz crystal and 2.5-30 pF trimmer to ground. See

Display Address DAO. The primary function of this pin is to input the least significant bit of a
16-bit video display address. The more significant 15-bits are outputs from an internal 15-bit
counter which is clocked by DAO. The secondary function of this pin is to indirectly input the
logic level of the VDG "FS" (field synchronization pulse) for vertical video address updating.
Horizontal Synchronization. The primary function of this pin is to detect the falling edge of
VDG "HS" pulse in order to initiate eight dynamic RAM refresh cycles. The secondary function
is to reset up to 4 least significant bits of the internal video address counter.
VDG Clock. The primary function of this pin is to output a 3.579545 MHz square wave** to the
VDG "Clk" pin. The secondary function resets the SAM when this VClk pin is pulled to logic
"0" level, acting as an input.

VClk

OS C Out
(/)

9

7

6

S2
S1

25
26

SO

27

E

14

ell

~Jj

(/)

(/)

c:

0

fr
:::I
0

Ul

~

c:(

:;..

cc:g
c:(

~"§

13
35
34
33
32
31
30
29
28

Most Significant Bit
First, the least significant address bits from the MPU or "VDG" are presented to ZO-Z5 (4K
x 1 RAMs) or ZO-Z6 (16K x 1 RAMs) or ZO-Z7 (64K x 1 RAMs). Next, the most significant
address bits from the MPU or "VDG" are presented to ZO -Z5 (4K x 1 RAMs) or ZO -Z6
(16K x 1 RAMs) or ZO -Z7 (64K x 1 RAMs). Note that for 4K x 1 and 16K x 1 RAMs, Z7 (Pin
35) is not needed for address information. Therefore, Pin 35 is used for a second row
address select which is labeled (RAS1).
Least Significant Bit.
Row Address Strobe One. This pulse strobes the least significant 6,7 or 8 address bits into
dynamic RAMs in Bank #1.
Row Address Strobe Zero. This pulse strobes the least significant 6,7 or 8 address bits into
dynamic RAMs in Bank #0.
Column Address Strobe. This pulse strobes the most significant 6,7 or 8 address bits into
dynamic RAMs.
Write Enable. When low, this pulse enables the MPU to write into dynamic RAM.

RAS1t

35

RASOt

12

CASt

11

WEt

10

c:(c

cc

0
0

Most Significant Bit (Device Select Bits). The binary value of S2, S1, SO selects one of eight
"chunks" of MPU address space (numbers 0 through 7). Varying in length, these "chunks"
provide efficient memory mapping for ROMs, RAMs, Input/Output devices, and MPU Vectors.
(Requires 74LS 138-type demultiplexer).
Least Significant Bit.

Q

~2

....:::I

Apply 1.5 kH resistor to 14.31818* MHz crystal and 33 pF capacitor to ground. See page 12.

Z7t
Z6t
Z5t
Z4t
Z3t
Z2t
Z1t
Zot

...

ii:

12.

E (Enable Clock) "E" and "Q" are 90 0 out of phase and are both used as MPU clocks for the
MC6809E. For the MC6800 and MC6801 E, only "E" is used. "E" is also used for many MC6800
peripheral chips.
Q (Quadrature Clock).

:::l.>o:
Q.

pa~ge

5
8

0

ell

Least Significant Bit.

DAO

c .... Hs
> ~

.-.......
...
>

MPU address bits AO-A15. These 16 signals come directly from the MPU and are used to
directly address up to 64K memory locations or to indirectly address up to 96K memory
locations. (See pages 17 and 18 for memory maps). Each input is approximately equivalent
to one low power Schottky load.

OS C ln

c:J"§
-

Function

Name

"14.31818 MHz is 4 times 3.579545 MHz television color subcarrier. Other frequencies may be used. (See page 12.)
""When VDG and SAM are not yet synchronized the "square wave" will stretch (see page 10.)
(= 60 MHz) resonances.

t Due to fast transitions, ferrite beads in series with these outputs may be necessary to avoid high frequency

3-663

II

•
FIGURE 2 -

en

z
.....
~

ren
.....

= SLOW

TIMING WAVEFORMS for MPU RATE

CD

jI)
i ...

ONE MACHINE CYCLE

..

i

~

n
CSCln

~

CHANGE FROM H TO l

WilL CHANGE FROM H TO l

~

CHANGE FROM L TO H

WILL CHANGE FROM l YO H

~

ANY CHANGE PERMlnED

E
(,)

OSCOut

Reference Points in Time_

-ll---ldIOl-EHI
~ I~:~(~l-Ql)

~h~::~)l-QH)
~

a,
0)
~

AO.A1S,R'W

.-

50,51,52

-"if

~: !=====::;:::::

tsulA16!

"".PQj
/VrH

-1··1

1

1

1

''''HI~·

~ld=-IO;H_=-VH=I_=+========~~~========================~====~~====~======t===~~~~~~~~~~illL=================t==i:~
(See-N~te 1.1
tdfOH-VlI

VALID VDG ADDRESS (RIDYI
(also, Z7ifin64K mode)

IdIOl-AR)_IWVOH F

_!L\b::::ldIOl-ACI
1"71
VOL

VAUD.I{DG A.DDRESS (COLUMN

~0{1
td{oL'ROH)~1

AASO

WE

_.

*

VOlfel

.

T

-i~

-.//.-tdfOL-Rll1

....... iJ.-

'\ VaHIC)
td(Cl.RH)

_

VAllO MPU ADDRESs (COLUMN)

VOL

''V'

r--

••

m __ ~

L/~.---

MPU ADORE S (ROW)

»-1 ~ ~~~~~~lHJ

RAS1 ••

l IdWl-AC)::J VOH

1
VALi~

IdIOl-ROU

~S

VOlfC)

---+1~td(Ql-CH)

VOLIC)

----"1 r::.~d(OL'WL)

VOHIC)

I'

-"1~td(OL-Cl)
VOlIC)

VOlIC)

"Timing points marked with """ are defined elsewhere (specifically. 8 cycles of "OSCOut" to the left or right_I
Note 1: The period of "VClk" is four times that of "OSCOul" unless the synchronization process is incomplete. Also.
VClk may rise within td(OH.VHI nanoseconds of TO. Tl. T2 ... or TF.

td(ol.WH)~i

t---

--Ss

~ ·4~
OH(C

o

z

......

.....
ro
......

FIGURE 3- TIMING WAVEFORMS for MPU RATE = FAST

00
jA)
,..

ONE MACHINE CYCLE

~

.,

n
Iw

G)

~

CHANGE fROM H TO L

WilL CHANGE FROM H TO l

~

CHANGE FROM l TO H

WILL CHANGE FROM L TO H

OSCln,

Osc Out

~

'--"""',-~s

~~--~~-----k~t-------~~~:------t~~-+-----4----~----~~----r-----t-----------~~--+-~.~
.~

~

c»

0)

c.n

:~

AO·A15,RW-·

DAO::~~~=:~~~~==~~J=~~~~~~~~~~~=1======9=======t=====~==~~~~~~~....~~~;;:::::::r::::::J::J

50,51,52::

:::

.-1/
• -11

i""::::ldIOH.VHI
VOH

VOL(V)

--I

~ldIOH.VLI

td(Ol·Acl
VOH

VALID MPU ADDRESS (ROW Note 1
(also,Z7 iiin 64K model

RAS1_.~

VOH

/
VOL

VALID MPU ADDRESS (COLUMN) Note 1

-1t:.ldIOL'RfHI

..fV°I~\~L'ROH)

-

-J.t::.

(4K & 16K m O d e S ) .

CAs _. . - •
W'E-'

.'

::4{

VALID MPU ADDRESS (COLUMN)

VOL

VOLlC)/....f'VOHICI
vOLlC)
j-

-",2). Thus,
when properly pOSitioned, VDG and MPU RAM accesses interleave without contention as shown below:

FIGURE 12 - MOTOROLA MPU WITH VDG TIMING
VDG Data
VDG Data
VDG Address
Window
VDG Address
Window
( ________ j . ~ ____ ~~~--------A---~~

'E' Clock:
(Approx. 1 MHz)

l

I

I

MPU Half

\.. ________ y-----.J~.... -------...(---.-Jy
MPU Address

MPU Data
Window

MPU Address

VDG Half

r

MPU Data
Window

This Interleaved Direct Memory Access (IDMA) is synchronized via the MC6883 by centering the VDG data
window half-way between MPU data windows. **
The result is a shared RAM system without MPUIVDG RAM access contention, with both MPU and VDG
running uninterrupted at normal operating speed, each transparent to the other.

RAM Refresh
Dynamic RAM refresh is accomplished by accessing eight*** sequential addresses every 64*** microseconds
until 128 consecutive addresses have been accessed. To avoid RAM access contention between REFRESH and
MPU, each of the 128 refresh accesses occupies the "VDG half" of the interleaved DMA (IDMA). Furthermore,
refresh accesses occur only during the television retrace period (at which time the VDG doesn't need to access
RAM).
In summary, the VDG, MPU and MC6883's Refresh Counter all transparently access the common dynamic
RAM without contention or interruption.

Why IDMA?
Use of the interleaved direct memory access results in fast modification to variable portions of display RAM,
by the MPU, without any distracting flashes on the screen (due to RAM access contention.) In addition, thE!
MPU is not slowed down nor stopped by the MC6883; thereby, assuring accurate software timing loops without
costly additional hardware timers. Furthermore, additional hardware and software to give "access permission"
to the MPU is eliminated since the MPU may access RAM at any time.
* Only 1 pin,

(DAO) out of 40 pins is dedicated to the video display.

** See VOG synchronization (p~e 10) for more detail.
*** When not using a MC6847, HS may be wired low for

continuous transparent refresh.

3·672

SN74LS783, MC6883
"Systems On Silicon" Concept
Total Timing
For most applications, the SAM can supply complete system timing from its on-chip precision 14.31818 MHz
oscillator. This includes buffered MPU clocks (E and O), VDG clock, color subcarrier (3.58 MHz)' row address
select (RAS)' column address select (CAS) and write enable (WE).
Total Address Decode
For most applications, the SAM plus a "1 of 8 decoder" chip completely decodes liD, ROM and RAM chip
selects without wasting memory address space and without needlessly chopping-up contiguous address space.
Chip selects are positioned in address space to allow three types of memory (RAM, local ROM and cartridge
ROM) independent room for growth. For example, RAM may grow from address $OOOO-up, cartridge ROM may
grow from address $FEFF-down and local ROM may grow from $FBFF-down. Alternately, if the application
requires minimum ROM and maximum contiguous RAM, a second choice of two memory maps places RAM
from $0000 to $FEFF. (See pages 17 and 18.)
In both memory maps all liD, MPU vectors, SAM control registers, and some reserved address spaces are
efficiently contained between addresses $FFOO and $FFFF.

How Much RAM7
Using nine SAM pins (ZO - Z7 and RASO) the following combinations require no additional address logic.
FIGURE 13 Address:
MSB

RAM CONFIGURATIONS

Chip Select:
LSB

Z5Z4Z3Z2Z1Z0 ..................................... RASO

l
t

Z5Z4Z3Z2Z1Z0 ..................................... RAS1 (=Z7) \- - - - - - One or two banks of 4K x 8 (like MCM4027's)
Z6Z5Z4Z3Z2Z1Z0 ..................................... RASO

Z6Z5Z4Z3Z2Z1Z0 ..................................... RAS1 (=Z7) \ - - - - - - One or two banks of 16K x 8 (like MCM4116's)
Z7Z6Z5Z4Z3Z2Z1Z0 ..................................... RASO - - - - - - - - - - - One bank of 64K x 8 (like MCM6665's)

PROGRAMMING GUIDE
SAM -

Programmability

The SAM contains a 16-bit control register which allows the MC6809E to program the SAM for the following
options:
VDG Addressing Mode .......... 3-bits
VDG Address Offset ............... 7-bits
32K Page Switch ..................... 1-bit
MPU Rate ................................ 2-bits
Memory Size .......................... 2-bits
Map Type ................................ 1-bit
Note that when the SAM is reset by first applying power or by manual hardware reset,t all control register
bits are cleared (to a logic "0").

VDG Addressing Mode
Three bits (V2, V1, VO) control the sequence of DISPLAY ADDRESSES generated by the SAM (which are used
to scan dynamic RAM for video information). For example, if you wish to display Dynamic RAM data as
INTERNAL ALPHANUMERICS VIDEO, you should program; the MC6847 for the INTERNAL ALPHANUMERICS
MODE and CLEAR BITS V2, V1 and VO in the SAM. The table on the following page summarizes the available
modes:
t See Figure 7 for manual reset circuit.

*Typically, part of a PIA (MC6821) at location $FF22 is used to control MC6847 modes. (See MC6847 Data Sheet.)

3-673

I

SN74LS783, MC6883

MC6847 Mode

G/A

GM2

GM1

Internal Alphanumerics

0

X

X

0

External Alphanumerics

0

X

X

,

X
X

0

0

OSemigraphics -

0

X

X

0

X

0

0

0

0

0
0

Mode Type

II

SAM Mode
GMt
EXTii

4

CSS

V2

V1

VO

0

0

0
0

Semigraphics -

6

0

X

X

1

X

0

Semigraphics -

8*

0

X

X

0

X

0

1

Semigraphics -

12*

0

X

X

0

X

1

0

Semigraphics -

24*

0

X

0

X

1

,

Full Graphics -

1C

0

0

0

0

0

1R

0

0

X

0

0

1

Full Graphics -

2C

0

1

,

0

X

0

1

0

X

0

0

,
,
,

X

Full Graphics -

,
,
,
,
,
,
,
,

X

0

0

X

1

X

X

X

X

X

Full Graphics -

2R

Full Graphics -

3C

Full Graphics -

3R

Full Graphics -

6C

Full Graph.ics -

6R

Direct Memory Accesst

0

,
,
,
,

0

,
,

X

X
X

,
,
,
,
,

1

0

,
,

0

1

0

,

0

,
,

0
0

,

0

*58,512, & 524 modes are not described in the MC6847 Data Sheet. See appendix "A".
tDMA is identical to 6R except as shown in Figure 5 on page 9.

VDG Address Offset
Seven bits (FS, F5, F4, F3, F2, F1 and FO) determine the Starting Address for the video display. The
"Starting Address" is defined as "the address corresponding to data displayed in the Upper Left corner of
the TV screen". The "Starting Address" is shown below in binary:

Note that the "Starting Address" may be placed anywhere within the 64K address space with a resolution of
V2K (the size of one alphanumeric page).
The FS-FO bits take effect during the TV vertical synchronization pulse (i.e., when FSfrom MCS847 is low).

Page Switch
One bit (P1) is used "in place of" A 15 from the MCS809E in order to refer access within $OOOO-$7FFF to one
of two 32K byte!pages of RAM. If the system does not use more than 32K bytes of RAM, P1 can be ignored. **
**When using 4K x 1 RAMS, two banks of eight IC's are allowed. This accounts for Addresses $0000-1 FFF. Also, this same RAM can be
addressed at $2000-$3FFF, $4000-$5FFF and $6000-$7FFF.

3-674

SN74LS783, MC6883
MPU Rate
Two bits (Rl, RO) control the clock rate to the MC6B09E MPU. The options are:
RATE (FREQUENCY OF "E" CLOCK)

R1

RO

0
0
1

0
1
X

0.9 MHz (Crystal Frequency 7 16) Slow
0.9/1.8 MHz (Address Dependent Rate)
1.8 MHz (Crystal Frequency 7 8) Fast
(Typical Crystal Frequency

=

14.31818 MHz)

In the "address dependent rate" mode, accesses to $0000-$7FFF and $FFOO-$FFl F are slowed to 0.9 MHz
(crystal frequency 7 16) and all other addresses are accessed at 1.8 MHz (crystal frequency -;. B.)
Note: "Slow" (0.9 MHz) operation can be accomplished using 1.0 MHz MC6B09E and MC6821 devices. For "Fast"
(l.B MHz) operation, 2.0 MHz MC6BB09E and MC68B21 devices must be used.

Memory Size
Two bits (Ml and MO) determine RAM memory size. The options are:
SIZE

I

M1 MO

One or two banks of 4K x 1 dynamic RAMs
One or two banks of 16K x 1 dynamic RAMs
One bank of 64K x 1 dynamic RAMs
Up to 64K static RAM*

0
0
1
1

0
1
0
1

*ReqUlres a latch for demultlplexmg the RAM address.

IMPORTANT!
Note: Be sure to program the SAM for the correct memory size before using RAM (i.e., for a subroutine
stack).

Map Type
One bit (TY) is used to select between two memory map configurations.
Refer to pages 17, lB and 19 for details. Early versions of the SAM did not allow the "Fast" MPU rate to be
used in conjunction with Map Type "TY = 1". Devices manufactured after January 1, 1983 allow both "Fast"
and "Slow" MPU rates to be used with Map Type "TY = 1." (Date of manufacture is marked on devices as
YYWW where YY is the year and WW is the week of manufacture.)

Writing To The SAM Control Register
Any bit in the control register (CR) may be set by writing to a specific unique address. Each bit has two unique
addresses ... writing to the even # address clears the bit and writing to the odd # address sets the bit. (Data
on the data bus is irrelevant in this procedure.) The specific addresses are tabulated on pages 17 and lB.
If desired, a short routine may be written to program the SAM CR "a word at a time". For example, the
following routine copies "B" bits from "A" register to SAM CR addresses beginning with address "X".
SAM1

46
24
30
A7
20

06
01
80
02

ROR
BCC
INX
STA
BRA

A
SAM2
(LEAX1.X)
O,X+
SAM3

SAM2

A7

81

STA

O,X++

SAM3

SA
26
39

F2

DEC
BNE
RTS

B
SAM1

7

6

S

4

3

2

o

C

C~I~----,-----,--~I-+D )

3·675

SN74LS783, MC6883

FIGURE 14 - MEMORY MAP (TYPE #0)
FINE

COURSE
MC6S09E
Address

__ S _
MC6S09E
Vectors,
Bits
5AM ;~
Control,
1/0

52,
51,50 MC6S09E'
Value Address

t

t

$FFFF

1'\$FFOO

(S

ROM1**
(5=2)

- - - - --<$AOOO

TFiQ

SWI2

I

,~~

I--

Reserved
for future
MPU
enhancements.

'--

Do not use!

164I(S
s·

~

I

ROMO**

(s= 1)

..---+-- - -- -k$SOOO
I
I
I
I
I

I
I
I

(S

RAM
(5=0 if R/W = 1)
(5=7 if R/IN = 0)
I
I

I
I
I

I~

16K

(S

(S

K$1000

: r

'-'v--'" ' - v - - "

Page 0

*Note:
M.S. == Most Significant
L.S. == Least Significant

(S

$0000

~
~"i

~

~
~
~
.. i

~

MPU
Rate

Pl

Page #1

Dynamic

r~FAST

rrA~.
FAST

o

0

t

Transparent
SLOW \ Refresh

Q

'}- MPU Addresses from $0000 to $ 7FFF
Apply to page #1 if P1 = '1
Address of "Upper-Left-Most
Display Element = $0000 + (V, K· Offset)

F5
F4

I

~

r64r~6K ~

I~OI

Memory
Size

RO

S~';,

F6

Display
Offset
(Binary)

F3

~DMA

.--G6R,G6C

~rT IGr,E'

F2
Fl

G1R
AI, AE, S4, S6

V2

~

+<$4000

fvde

TV

MO

I~

I

Page 1

SWI

II

- - - - -k$COOO

:-- -f

~
~

Definitions

ReSET
NM!

~

(5=3)

~--r

Label

~~---

II

ROM2**

I

t

VDG
Mode
(SAM)

1

1

o

0

1

1

o

0

VO
-~

FF6
FF5

-

FF4~

FF42
FF41
FF40

~

Reserved
Do not use!

Reserved for Futu re
Control Registers or Special 1/0

1/0 2

~
~I"~

F '22
F '21

110 1

1'1"0F'1F
FF03
FFO'
FFr

1I0O(Slow)

FFOO
**May also be RAM

s
== Csel t Bit .
(All bits are cleared when SAM is reset.)
C ==
ear BIt \
S = Device Select value = 4 x S2 + 2 x S1 + 1 x SO

l

3·676

SN74LS783, MC6883
FIGURE 15 -

MEMORY MAP (TYPE #1)
FINE

COURSE

MC6809E
Vectors,
SAM

MC6809E
__ 8 __ Address
Bits
,

52,
51, SO MC6809E
Value

~ ~~~~$FFFF

Address

110, Boot
ROM

Label

.

Definitions

/~,~---

Control,~t-'-

$FFOO

(S = 3

if
R/W =0)
(S

(S = 0

I

if
R/W =1)

Reserved
for future
MPU
enhancements.

~--- k$COOO

(S =2

***

if
R/W =0)

Do not use!

(S = 0

if
R/W = 1)
RAM

1 - - - - K$AOOO
(S = 1

if
R/W =0)
(S = 0

~

«
a:

if
R/W = 1)

1 - - - - K$8000

...J
...J

«

(S=O

if
R/W=1)
(S

(S=7

if
R/W=O)

(S-I;;I~---Ll,~-I

(S

*Note:
M.S. == Most Significant
L.S. == Least Significant

1/01

**Decode S2, S1, and SO with an open
collector SN74LS156 and 'wire-or' state 7
with state 2. (See Appendix B for
suggested decode circuit.)
***To avoid ROM enable during R/Iii = LOW,
the ROM at S = 2 must be gated with R/Iii.
(See Appendix B for suggested decode circuit.)

I/OO(Slow)

S == Set Bit ~
.
.)
't (All bits are cleared when SAM IS reset.
C == CI ear B I
S = Device Select value = 4 x S2 + 2 x S1 + 1 x SO

3-677

SN74LS783, MC6883
FIGURE 16 - MEMORY ALLOCATION TABLE
(Also, see the memory MAPs on pages 17 and 18.)
Type # 0:

(Primarily for ROM based systems)

Address Range
$FFF2 to FFFF
FFEO to FFF1
FFCO to FFDF
FF60 to FFBF
FF40 to FF5F
FF20 to FF3F
FFOO to FF1 F
COOO to FEFF
AOOO to BFFF

I

8000 to SFFF
0000 to 7FFF

5=4(52)+2
(51) +50
5 Value
2
2
7
7
6
5
4
3
2
1

o if RiVi = 1
7 if RiVi =0

Intended Use
MC680SE Vectors: Reset, NMI, SWI, IRQ, FIRQ, SWI2, SWI3.
Reserved for future MPU enhancements.
SAM Control Register: VO, - V2, FO - F6, P, RO, R1, MO, M1, TY.
Reserved for future control register enhancements.
1/02: Input/Output (PIAs, ACIAs, etc.) To subdivide, use AO - A4.
1/01: Input/Output (PIAs, ACIAs, etc.) To subdivide, use AO-A4.
1/00: Input/Output (PIAs, ACIAs, etc.) To subdivide, use AO-A4.
ROM2: 16K addresses. External cartridge ROM*.
ROM1: 8K addresses. Internal ROM*. Note that MC680SE vector addresses select this
ROM*.
ROMO: 8K addresses. Internal ROM*.
RAM: 32K addresses. RAM shared by MPU and VDG.

'Not restricted to ROM. For example, RAM or I/O may be used here.

Type # 1:

(Primarily for RAM based systems)

Address Range
$FFF2 to FFFF
FFEO to FFF1
FFCO to FFDF
FF60 to FFBF
FF40 to FF5F
FF20 to FF3F
FFOO to FF1 F
0000 to FEFF

5=4(52)+2
(51)+50
5 Value
2
2
7
7
6
5
4

o if Riw =

1

Intended Use
MC680SE Vectors: Reset, NMI, SWI, IRQ, FIRQ, SWI2, SWI3.
Reserved for future MPU enhancements.
SAM Control Register: VO - V2, FO - F6, P, RO, R1, MO, M1, TY.
Small ROM: Boot load program and initial MC680S vectors.
1/02: Input/Output (PIAs, ACIAs, etc.) To subdivide, use AO-A4.
1/01: Input/Output (PIAs, ACIAs, etc.) To subdivide, use AO - A4.
1/00: Input/Output (PIAs, ACIAs, etc.) To subdivide, use A2 - A4.
RAM: 64K( - 256) addresses, shared by MPU and VDG.
(If RiW = 0 then S = 3 for $COOO-$FEFF; S = 2 for $AOOO-$BFFF; S
$8000-$SFFF and S = 7 for $0000-$7FFF.)

3-678

=

1 for

SN74LS783, MC6883
APPENDIX A
VDG/SAM Video Display System Offers 3 New Modes
by
Paul Fletcher
There are three new modes created when the VDG
and SAM are used together in a video display system. These modes offer alphanumeric compatibility
with 8 color low-to-high resolution graphics,
64Hx64V, 64Hx96V, 641-ix192V. The new modes 58,
512, and S24 are created by placing the VDG in the
Alpha Internal mode and having the SAM in a 2K,
3K or 6K full color graphics mode. In all modes the
VDG's S/A and Inv. pins are connected to data bits
DD7 and DD6 to allow switching on the fly between
Alpha and 5emigraphics and between inverte.d
and non-inverted alpha. This method is used in
most VDG systems to obtain maximum flexibility.
The three modes divide the standard 8*12 dot box
used by the VDG for the standard alpha and semigraphics modes into eight 4*3 dot boxes for the 58
mode, twelve 4*2 dot boxes for the 512 mode, and
twenty-four 4*1 dot boxes for the 524 mode. Figure
17 shows the arrangement of these boxes. One byte
is needed to control two horizontally consecutive
boxes. It therefore takes four bytes for the 58, six
bytes for the S12, and 12 bytes for the S24 mode to
control the entire 8*12 dot box. These two horizontally consecutive boxes have four combinations of
luminance controlled by bits 80 - 83. For conven-

ience 82 should be made equal to 80 and 83 should
be made equal to 81. This eliminates a screen placement problem which wou Id cause other codes to
change patterns when moved vertically on the
screen. The illuminated boxes can be one of eight
colors which are controlled by 84 - 86 (see Figure
18). The bytes needed to control all the boxes in the
8*12 dot box must be spaced 32 address spaces
apart in the display RAM because of the addressing
scheme orginally used in the VDG and duplicated
by the SAM. This means to place an alphanumeric
character on the TV screen it requires 4, 6, or 12
bytes depending on the mode used. These bytes are
placed 32 memory locations apart in the display
RAM (see Figure 18). This multiple byte format allows the mixing of character rows of different characters in the same 8*12 dot box creating new characters and symbols. It also allows overlining and
underlining in eight colors by switching to semigraphics at the correct time.
These new modes optimize the memory versus
screen density tradeoffs for RF performance on
color TVs. This could make them the most versatile
of all the modes depending on the users creativity
and the software sophistication.

APPENDIX B
Memory Decode for "MAP TYPE

= 1"
MPU Vectors and
Boot Load ROM
128 X 8 (or 256 X 8)

EN
Vcc = 16
Gnd = 8

"7 (03a)
Ea
Ea

EN

+5.0
V

4

+5.0
"6 (02a) 5 V.
+5.0
"5 (Ola) 6 V
+5.0
V
4 (OOa)

1/0 2
1/0 1
1/0 0

SN74LS156

3 (03b)
52

F.om SAM \

Eb
Eb

'2 (02b)
T(Olb)

51
50

Al
13

AO

o(OOb)

12

NC

11
10

9

NC

+5.0 V
RAM READ

3-679

I

SN74LS783, MC6883

FIGURE 17 -

DISPLAY MODES

sa, S12, S24

BiWisible Dot Correlation

~8~1
Scan
Lines

S8

~~~ress Byte

1

•

S12

$XX20 ($01)
$XX40 ($01)

$01 is the
VDG "ASCII"
code for 'A'.

$XX60 ($01)

• Alphanumeric Compatible

~S---'I
Scan
Lines

• •

••
•
•••••
•
•
•
•

•

12

1

I

$XXOO ($01)

Left

1

Right ***
Red

$XXOO ($BF)

Blue

Off

$XX20 ($AA)

Off

Green

$XX40 ($85)

Red

12

1

Orange

Orange $XX60 ($FF)

Off

Off

$XX80 ($SO)

Yellow

Yellow

$XXAO ($9F)

• Options: One of S colors for
L or R or both. Off = Black

1

1~8-1

Blue
Black
Black

Scan f----+-----1
Lines

~

S24

Blue
Black
Black

• ••••
•
•
• •
•
• •
••
•
•
Black
Black

t----+----lj

Green

Green

$XXOO
$XX20
$XX40
$XX60
$XXSO

$XXAO ($1S)1
$XXCO ($1S)
VDG
$XXEO ($1S)
Code
$X100 ($1S)
for X
$X120 ($1S)
$X140 ($SO)
$X160 ($8F)

• Underline, Overline
• Mix Character Dot Rows

*** Characters will always

remain in standard VDG positions.

3-680

($AF)
($SO)
($SO)
VDG
($14) .-Code
($18)
for T

en
FIGURE 18 -

r-(1~*--1
Ll
L1

LO
LO

58
Ll

L1

w

m
00
--L

(rl

~

LO

LO

,

LX C2

Cl

CO

Color

B3.Bl

B2.BO

0

X

X

X

Black

0

0

1

0

0

0

Green

1

0

0

1

Yellow

t(a)**

1

0

1

0

Blue

I(b)

1

0

1

1

Red

1

1

0

0

Buff

l~c)

1

1

0

1

Cyan

J

Semi

0

I
I
I

1

Alpha

'--y--A
Extra

y

}

ASCII Code

(d)

1

0

1

1

Off

Off

Color

I
I
I

Off

Color

Off

I
I
I

I

Color

I

1

1

1

0

Magenta

1

1

1

1

Orange

32 Columns - - - - - - -

of 58 810ok.

+

','

1111
:

2 , 4 5

(a)l
(a)2
(a)3
(a)4
(a)5

1st row of 4 x
dot boxes

_.1
row.

I

(d)

(a)32
(b)l
(b)2
(b)3
(b)4
(b)5

=

3rd row of 4 x
dot boxes

+

16 Rows
of S8 Blocks

0020

~

One ROWOf+
8 x 12
TV Screen
Resolution
Semi = 64 x 64
32 Char. H. x 16 Rows V

$0000

~~

2nd row of 4 x 3
dot boxes

(b)32
(c)l
(c)2
(c)3
(c)4
(c)5

$0040

~~

4th row of 4 x
dot boxes

*

•

I!I

.-en
~

en Memory Map

Column

Alpha

~

4

BO

I~
i~I)li1 1111111111
..

z

58 DISPLAY FORMAT EXAMPLES

(c}32
(d)l
(d)2
(d)3
(d)4
(d)5

$0060

(d)32
$0080

--...

CD

~

3:
en

o

CD
CD
W

SN74LS783, MC6883

FIGURE 19 -

EXAMPLE of MC6809E, MC6883 and MC6847 COMPUTER

, ENDC

.---

-

,----

-

A15
A14
A13
A12

S

21

S

18

All

All

S
Ala

I

Ala

19

Ala

21
18
19

A9

22

22

A8

23

23

A7

1

1

A6

2

2

3

3

A5
A4

CSl

24

CSl

24

4

4

A3

CSO

22

CSO

22

5

5

6

6

35

7

7

A2
Al

RSl

AO

RSO
CS2

RiW

35

RS1

36

RSO

~iiOii
21

CS2

36

8

101
~-

8

E~ROM1

S~ROM2

21

BA

EXPANSION
CONNECTOR

BS
BUSY
LlC

21

21

ell
00

25

~

0

3:
3:

3:

3:

(')

E

0

'"j;

'"j;

TSC

25

00

0

3:
3:

n

(')

(')

(')
ell

21

0

3:
3:

3:
en
co

3:

3:

at

at

co

~

)0

00
)0

**

g;

~

)0

w
w

w

w

en

U1

FIRO
IRO

IRCA,B

38,37

IROA,B

38,37

HALT
NMI
RESET

34

34

+5V

20

20

24

24

GNO

1

1

12

12

~+12V

~-12V
07

07

26

07

26

07

17

07

17

06

27

27

16

16

05

28

28

15

15

D4

29

29

14

14

03

30

30

13

13

02

31

31

11

11

01

32

32

10

10

DO

DO

33

DO

33

DO

9

DO

9

OSPB
'---

~

I

PB~
7 6 5
4 3
2 1 0

171161151141131121111101

CB-

PAI

7

6

5

4

3

2

91 81 71 61 51 41

1
31

0
2

\

1

CA-

~
2 . 1

2

1

191181391401

64 KEY
KEYBOARD
CONNECTS
HERE

:-.J

PB~
4 3
2 1
7 6 5
0
171161151141131121111101

PA-

~
91 81

71

6\

5\ 41 31

if

~I
2

1

2

1

191181391401

MC6847 Mode Control & Mise 1/0 connects here. ]

3-682

SN74LS783, MC6883

4.7 k

~

.-----23
22
21
21

20

1S

19

19

1S

22

17

A12
All
Ala

23

16

1

15

2

14

3

13

4

12

5

11

6

10

7

9

8

S

E~ROMO

32

6
5
33
38
39

.'-'

24
12

07

37 A14

A13

38 A13

5~I/Ol

A12

39 A12

4" ~ilOo

1

All

2

Ala

3

A9

4

AS

24

A7

23

A6

22

A5

21

A4

19

A3

18

A2

17

Al

16

AO

-

15

RW

- 9
6 -

VCC

All

S2~

Al0

~ 3
26
2
S 1 - Al ,...

~
~

.'-'

~

I

~t

27
1
5 0 - AO co _
1

AS
A7

16

25
26

14

27

13

28

11

29

10

30

9

31

A5

Gnd

A4

n

Mp.;.

VCC ~ 16

CHB

Gnd~S

-EN -EN

f4

5 4

A3

=

A2

VI

Al

»

6 1.5 k

3:
3:

AO

50 PFt

en
CX)

R/VV

cb-

05COut

(')

=.T

5

fl

OSCin

14.31818
MHz

~9-35 pF

fjS9

LlC

3:

TSC

C

OAO

"'II
VClk

(')

en

14

~

Ms

1-

HS

FS

8

38
22

7

33 Clk

I:)

13

CO

UI

':

Gnd

07
06
05
04
03
02
01
DO

Q

100 k

1

Z7 Z6 Z5 Z4 Z3 Z2 ZI ZO
35 34 33 32 31 30 29 28

n

'-----

<
0

t ~rl

13* 10· 11*12* 6* 7* 5* 4·

t 5 V

.. \

A6 A5

A4

A3 A2 A1

AO

E2

2 07

3

2 06

5

Ei

I/)

7

2 05

Q7

15

Q6 14

4

13

Q5 14

7

14

~

I/)

11

Q4 14
03 14

Q 2

3 0

6

8 005 GM2

8

9

7 004 GMI

13

~

(;j

12

6 003 GMo

20

15

5 002 CSS

Gnd' 10

16

4 001

12

t

8

2 02

14

VCC~20

6

02 14

14 VCC

2 01

16

Gnd~10

4

Q1

17

2 DO

18

2

00 14

fl flf f1
VCC

VSS

VBB

18 0

~
4.7 k

~4XO.l ~F

+ 12

V

+5V

0

19

EXT

3 000

1 CLEAR

"~

5V

*This pin number on 8 different RAM chips is connected to this point.
**See text ... page 16

3·683

AG

~

2 03

VOO

007
2 006

f!

9

14

5

I/)

2 04

-(}---

AS

JA

17

r

,---E Inv

~
Clk

I

19

ie...,

bf-

15' 3'

RAS CAS WE

---= 2J
RAM's MCM4116B-20

en

11

T

-

(')

1

~F-l-'" 0 1~F-l-

CAS
RASO
WE
12 11 10

~

3:

,5V

-

r---<>

OAO
C)

E

-

--

~ROMO

--

_ _ _ __

I.--

tsu(D)_

th(D)

1.4V

tWiE)-..-I---',

lout

I

-1

FS -------~---.... ~~-·~1"72~;--- ..\

os - - - - - - - -

FIGURE 2 - BLOCK DIAGRAM
87654321
~

(

(

(

(

(

iii

al

rn

REFOUT

12

18

IReference

2.5 V

I

Source

~

4.900 kO

I

o

c

c

12

Double Buffered
Latches

A.Gnd

9

r.t
-=

~

~

t-

A. Gnd

13
Bipolar Offset
Current Sources.
Switches

2.450
kll

5.0 k
15

VEE

10VSpan
5.0 k

611
VEE
-5 V
to-15 V

620
Vee
5V

14

617
Analog
Ground

610
Digital
Ground

3-697

16
20 V Span

MC6890
TEST FIGURES
UNIPOLAR CONFIGURATIONS

BIPOLAR CONFIGURATIONS

FIGURE 3A

FIGURE 4A
R250n

19

19
Rl
loon

Rl
loon

MC6890
18

MC6890
18

+10 V Configuration
Latched Input Code: 11111111

-=-

-::±5.0 V Configuration
Latched Input Code: 10000000

FIGURE 3B

I

FIGURE 4B
R250n

19
Rl
lOOn

16

19
Rl
loon

MC6890

18

MC6890
18

+20 V Configuration
Latched Input Code: 11111111

-=-

±10 V Configuration
Latched Input Code: 10000000

FIGURE 3C

FIGURE 4C
R250n

19
Rl
lOOn

19
Rl
loon

MC6890

MC6890
18

18

-::-

-::-

+5.0 V Configuration
Latched Input Code: 11111111

FIGURE 5

±2.5 V Configuration
Latched Input Code: 10000000

TEST CONFIGURATION FOR DAC OUTPUT IMPEDANCE
19

Rl

MC6890

lOOn
18

Latched Input Code: 11111111
12 V
Rout

=.:llout

3·698

MC6890

TERMINOLOGY
Gain error is laser trimmed to less than ±1.0% with R1 =
100 n (Figure 3) and can be user trimmed to zero error with
R1 = 200 n pot.

Nonlinearity (Relative Accuracy) - Maximum output
deviation from ideal straight line connecting zero and fullscale readings, expressed as a fraction of LSB or percent
of full scale.

Bipolar Zero - USing the configuration shown in
Figure 6 with R 1 = 100 n, R2 = 50 n, with the MSB on and
all other bits off, the output voltage reading compared to
analog ground is expressed as a percentage of the fullscale range. Offset voltage of the output op amp must be
nulled. Bipolar Zero error is laser trimmed to less than
0.20% and can be user trimmed to zero with R2= 1
pot.

Differential Nonlinearity - Maximum deviation in the
readi ngs of a ny two adjacent input bit codes from the idea I
LSB step, expressed in fractions of LSB or percentage of
full scale. A differential nonlinearity value greater than
1 LSB may lead to non-monotonic operation.

oon

Monotonicity - For every increase in the input digital
word, the output current either remains the same or
increases. The MC6890 is guaranteed to be monotonic
over temperature.

Temperature Coefficients - (Unipolar zero, Bipolar
zero, Gain and Reference Output). The maximum deviation
of the particular parameter over the specified temperature
range, divided by the temperature range, expressed in
parts per million of Full Scale Range per degree C.

Settling Time - The elapsed time from the Enable
positive transition until the output has settled within an
error band about its final value.
The worst case switching condition occurs when all bits
are latched "on," which corresponds to a low-to-high
transition for all bits. This time is typically 200 ns for the
current output to settle to within ±1/2 LSB for 8 bit
accuracy. These times apply when the output swing is
limited to a small «0.5 V) swing and the external output
capacitance is under 10 pF.

Power Supply Rejection - The change in full scale
current caused by the specified change in VEE or VCC is
expressed in LSB's.
Reset Function - The MC6890 has a Reset pin (9)that
will force the DAC's registers, and therefore the DAC
output current, to zero. This input is active low and should
not occur simultaneously with an active Enable Signal
although no harm would result to the converter. The
power dissipation increases slightly during Reset low.
Reset Should not be allowed to become more negative
than ground.

Gain Error - The difference between the actual full
scale range and the ideal full scale range. Based on a 0 to
10 V output configuration, the ideal FSR is
9.961 V.

FIGURE 6 -

;~~ x

10 V =

MC6890 IN TYPICAL BIPOLAR ±2.5 V OPERATION

16
18

4.900 k.o.

Rl
0-200.0.
lout

19

VO±2.5 V

13

R2
0-100.0.

07

08

05

04

03

02

01

1

1

1

1

1

1

1

1

1
0
1
0
0

1
1
0
1
0
0

1
0
1
0
0

1
0
1
0
0

1
0

1
0
1
0
0

0
0
1
1
0

1
0
0
0

1

0
0

3·699

DO

Vo (Volts)
R2 =60.0.
R2 = 50.0.
+2.490
+2.480
+2.470
+2.460
+0.010
+0.000
-0.010
-0.020
-2.470
-2.480
-2.490
-2.500

I

MC6890

TYPICAL PERFORMANCE CURVES

FIGURE 7 - REFERENCE VOLTAGE versus
EXTERNAL LOAD CURRENT*

(!)

~>

- t--- r---- r----

2.500

~ 2.490

~

I

!
~

TA

1

25 0 c

r--"

2.480

2.470

>

2.460

\
o

5.0

10

15

25

20

35

30

IREF. REFERENCE OUTPUT CURRENT (rnA)

*External load current is in addition to Reference Input
Current (Pin 18) of Df A converter.

FIGURE 8 -

DIGITAL INPUT CHARACTERISTICS

1.0
VCC

, _I.---

=5.0 V

I
~

.3 -1.0

f--

l-

i
I-

-I-"

Data Inputs

-2.0 I - - -

l--- +--

TA

=25

0

Reset

-3.0

::::>

a..
z

~

t5

is

-4.0

1)

-5.0

VEnable

-6.0
-7.0
-0.2

V
-0.1

1.0

2.0

3.0

4.0

OIGITAL INPUT LOGIC LEVELS (VOLTS)

3·700

5.0

3:

oen

CO
CD

FIGURE 9 - TYPICAL APPLICATION OF THE MC6890 IN A MC6800 SERIES MPU SYSTEM

o
Analog Power
Supplies

Digital
Power Supply
Gnd

+5.0 V

Gnd +5.0 V -5 Vto-15 V

Optional VCC Kelvin Connection

of +5.0
V Analog
Supply
L _ _ _ _ in
_Absence
___
__
___
__ _

Digital
System
Ground

Kelvin Ground Connection

O.l/lF
O.l/lF
O.l/lF

-=10
VSS

120

*Note: Bypass
capacitor leads should
be short

111

Digital
Gnd

VCC
13

(,.)

.!..J

o

~

MC6800
MC68AOO
MC68BOO
MC6802
etc.

Reset

f--1

1000.(>

'-----r'

T

I

I

~ Vout

±5.0V
Memory

SN74LS 133

2
VMA

.I. 1 .O /l F
Address Bus

Data Bus

III

®

MC68120
MC68121

ItIIOTOROLA
Advance Information

HMOS
INTELLIGENT PERIPHERAL CONTROLLER

I

The MC68120/MC68121 Intelligent Peripheral Controller (lPCI is a
general purpose, mask programmable peripheral controller. The IPC
provides the interface between an M68000 or M6800 Family
microprocessor and the final peripheral devices through a system bus
and control lines. System bus data is transferred to and from the IPC via
dual-port RAM while the software utilizes the semaphore registers to
control RAM tasking or any other shared resource. Multiple operating
modes range from a single chip mode with 21 I/O lines and 2 control
lines to an expanded mode supporting an address space of 64K bytes.
The MC68120 has 2K bytes of on-chip ROM to make full use of all
operating modes. The MC68121 utilizes only the expanded address
modes, due to the absence of on-chip ROM.
A serial communications interface, 16-bit timer, dual-ported RAM
and semaphore registers are available for use by the IPC in all operating
modes.
• System Bus Compatible with the Asynchronous M68000 Family
• System Bus Compatible with the MC6809 and Other M6800 Family
Processors/ Peripherals
• Local Bus Allows Interface with all M6800 Peripherals
• MC6801 Source and Object Code Compatible
• Upward Compatible with MC6800 Source and Object Code
• 2048 Bytes of ROM (MC68120 Only)
• 128 Bytes of Dual-Ported RAM
• Multiple Operation Modes Ranging from Single Chip to Expanded,
with 64K Byte Address Space
• Six Shared Semaphore Registers
• 21 Parallel I/O Lines and 2 Handshake Lines (5 I/O Lines on
MC68121)
• Serial Communications Interface (SCI)
•
•
•
•
•
•

16-Bit Three-Function Timer
8-Bit CPU and Internal Bus
Halt/Bus Available Capability Control
8 x 8 Multiply Instruction
TTL Compatible Inputs and Outputs
External and Internal Interrupts

GENERIC INFORMATION
(TA=O°C to 70°C)
Package Type
Ceramic
L Suffix

Frequency (MHz)

Generic Number

1.0
1.0
1.25
1.25

MC68120Ll (Unicorn ROM)
MC68121 L
MC68120Ll-l (Unicorn ROM)
MC68121L-l

This document contains information on a new product. Specifications and information herein
are subject to change without notice.

3-702

(HIGH-DENSITY N-CHANNEL
SILICON-GATE)

INTELLIGENT PERIPHERAL
CONTROLLER

L SUFFIX
CERAMIC PACKAGE
CASE 740

PIN ASSIGNMENT
VSS
IRQl
HALTI
BA/NMI
E

P24
P23
P22

SR/W

P21

DTACK

P20

CS

SC2

SA7

SCl

SA6

P30

SA5

P31

SA4

P32

VCC

P33

SA3

P34

SA2

P35

SAl

P36

SAO

P37

SDO

P40

SDl

P41

SD2

P42

SD3

P43

SD4

P44

SD5

P45

SD6

23

P46

SD7

24

P47

MC68120, MC68121

MC68120/MC68121 INTELLIGENT PERIPHERAL CONTROLLER ~ N~:::n:J;:!;

BLOCK DIAGRAM

cs

(L (L (L (L (L

SR/W
DTACK

f->o<:----1-.

Test POint

MMD6150
or Equiv.

I~'c

MMD7000
or Equiv.

C=90 pF
=30 pF
R=37 kO
=24 kO

3·704

for
for
for
for

P30-P37,
P20-P24,
P40-P47,
P20-P24,

P40-P47,

SC~

SC2

RALT/&A,/1'lMT
SC1, SC2
HALT/BAINMI, P30-P37

MC68120, MC68121

DC SYSTEM BUS ELECTRICAL CHARACTERISTICS
(VCC=5.0 Vdc ±5%, VSS=O, TA=70°C unless otherwise noted) (Refer to Figure 3)
Symbol
Characteristic
CS, OTACK, SAO-SA7, SOO-S07, SR/W
VIH
CS, OTACK, SAO-SA7, SOO-S07, SR/W
Input Low Voltage
VIL
OT ACK, SOO-S07 VOH
Output High Voltage ((Load = - 400 p.A, V CC = min)
OT ACK, SOO-S07 VOL
Output Low Voltage ((Load = 5.3 mA, VCC= mini
Input High Voltage

Min

Typ

Max

Unit

VSS + 2.0
VSS-0.3

-

VSS+2.4

-

VCC
VSS+0.8
-

-

-

VSS+0.5

V
V
V
V

-

FIGURE 3 - TIMING TEST LOAD SDO-SD7, DTACK

vcc
RL: 750 0

...----.

Test POint o----~--...--

MMD6150
or Equlv

MMD7000

c= 130 pF

or Equlv

R =6 kO

PERIPHERAL PORT TIMING (Refer to Figures 4 through 7)
Symbol

Min

Max

Unit

Peripheral Data Setup Time

tposu

200

-

ns

Peripheral Data Hold Time

tPOH

200

-

ns

Delay Time, Enable Positive Transition to OS3 Negative Transition

tOS01

-

350

ns

Delay Time, Enable Positive Transition to OS3 Positive Transition

tOS02

-

350

ns

Delay Time, Enable Negative Transition to Peripheral Data Valid (Ports 2, 3, 4)

tpwo

-

350

ns

Delay Time, Enable Negative Transition to Peripheral CMOS Data Valid

tCMOS

-

2.0

p's

Input Strobe Pulse Width

tpWIS

200

-

ns

tlH

60

-

ns

tiS

20

tpWIC

2

-

Ecyc

Characteristics

Input Data Hold Time
Input Data Setup Time
Input Capture Pulse Width (Timer Function)

FIGURE 5 - DATA SETUP AND HOLD TIMES
(MPU WRITE LOCAL BUS)

FIGURE 4 - DATA SETUP AND HOLD TIMES
(MPU READ LOCAL BUS)

P20-P24
P40-P47
Inputs

All Data
Data Valid
Port Outputs _ _ _ _ _ _ _ _-1 1'0_ _ _ __

P30-P37
Inputs*

Notes:
1.10 k Pullup resistor required for Port 2 to reach. 0.7 VCC
2. Not applicable to P21
3. Port 4 cannot be pulled above V CC

*Port 3 Non-Latched Operation (LATCH ENABLE=O)

FIGURE 6 -

ns

PORT 3 OUTPUT STROBE TIMING
(SINGLE CHIP MODE)

FIGURE 7 - PORT 3 LATCH TIMING
(SINGLE CHIP MODE)

Address
Bus
P30-P37
Inputs

OS3

* Access matches Output Strobe Select (OSS = 0, a read;
OSS= 1, a write)
Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

3-705

II

MC68120, MC68121

LOCAL BUS TIMING (See Notes 1 and 2)
Ident.
Number

II

Symbol

Characteristics

MC681201

MC68120-11

MC68121
Min Max

MC68121-1
Min Max

Unit

1

Cycle Time

tcyc

1.0

2.0

0.8

2.0

2

Pulse Width, E Low

PWEL

430

1000

360

1000

/ls
ns

3

Pulse Width, E High

PWEH

450

1000

360

1000

ns

4

Clock Rise and Fall Time

tr,tf

-

25

-

25

ns

9

Non-Muxed Address Hold Time

tAH

20

-

20

-

ns

11

Address Delay From E Low

tAD

-

260

-

220

ns

17

Read Data Setup Time

tDSR

80

-

70

-

ns

18

Read Data Hold Time

tDHR

10

-

10

-

ns

19

Write Data Delay Time

tDDW

-

-

200

ns

21

Write Data Hold Time

tDHW

20

-

20

-

ns

23

Muxed Address Delay from AS

tADM

-

90

-

80

ns

25

Muxed Address Hold Time

tAHL

20

110

20

110

ns

26

Delay Time E to AS Rise

27

Pulse Width, AS High

80
170

28

Delay Time AS to E Rise

29

Usable Access Time (Note 4)

225

tASD

1()()

-

PWASH

220

-

tASED

1()()

-

tACC

570

-

Enable Rise Time Extended

tERE

-

Processor Control Setup Time

tpcs

Processor Control Hold Time

tPCH

FIGURE 8 -

LOCAL BUS TIMING

tERE

lOS,
R/W, Address
(Non-Muxed)

Read Data Muxed

Addr/Data
Muxed

~----~191~----~

Write Data Muxed

Addr/Data
Muxed

Address
Strobe (AS) _ _ _ _-"'rl
I+----~

NOTES
1. Voltage levels shown are VLSO.5 V, VH2:2.4 V, unless otherwise specified.
2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise specified.
3. Address valid on the occurrence of the latest of 11 or 23.
4. Usable access time is computed by: 1- (4+ 11 + 17).

3~706

-

ns
ns

80
435

-

80

-

80

ns

200

-

200

-

ns

20

40

20

40

ns

ns
ns

MC68120, MC68121

ASYNCHRONOUS SYSTEM BUS TIMING (Re er to ·Igures 9 10 11 an d 121
Symbol

Min

Typ

Max

Unit

Cycle Time

t c:yc

0.8

-

2.0

System Address Setup

tSAS

30

-

-

I's
ns

System Address Hold

tSAH

0

-

-

ns

Characterisic

System Data Delay Read
Semaphore
RAM
System Data Valid
System Data Hold Read
System Data Delay Write
Semaphore

tSDDR

0.3

-

0.3+ 1.5
tcyc *

tSDDR

-

315

-

I's
ns

tSDV

0

-

-

ns

tSDHR

0

-

100

ns

..

-

..

ns

tSDDW

-

-

60

ns

tSDHW

0

-

-

ns

tSDDW

RAM
System Data Hold Write
Data Acknowledge
Semaphore
RAM

tDAL

0.5

-

0.5+ 1.5
tcyc*

tDAL

-

315

-

-

I's
ns

Data Acknowledge High

tDAH

-

60

ns

Data Acknowledge Three-State

tDAT

-

-

90

ns

Data Acknowledge Low to CS High

tDCS

60

-

-

ns

* Actual value dependent upon clock period.
* * Data need not be valid on write to Semaphore Registers.

FIGURE 9 - ASYNCHRONOUS READ OF SEMAPHORE REGISTER

FIGURE 11 -

FIGURE 10 -

ASYNCHRONOUS WRITE OF SEMAPHORE REGISTER

FIGURE 12 -

ASYNCHRONOUS READ OF RAM

SR/W
SAO-SA7

ASYNCHRONOUS WRITE OF RAM

~""'~_ _ _ _ _ _ _ _ _J.I!T.L.JJ

SAO-SA7

SOO-S07 -----H-......- - - - - - - 1 HALT /EiA/i\JMI

signals. Figure 22 shows the appropriate timing diagram for
Halt/BA with the recommended circuit. The pull up resistor
shown in the circuit maintains a high logic level when HALT
is not active. During a positive half-cycle of E, pin 3 is an input sampled to determine if the Halt State is requested (active low). During the negative half cycle of E, the BA signal is
output through pin 3. After the request for Halt State signal
is detected and the processor completes its current instruction, the CPU is halted and the active low BA Signal is output
through pin 3 during the negative half cycle of E. The local
bus is then available for other devices to utilize until the Halt
State signal has returned to a high level, thus allowing the

IPC back on the local bus. During the Halt State, the R/Wis
high, and the address bus displays the address of the next instruction.
When Single instruction operation is desired, in program
debug for instance, it is advantageous to Single step through
instructions. After SA goes low, HALT must be brought
high for one E-cycle and returned low again to Single step
through instructions. Figure 22 illustrates the timing involved
while single stepping through a single byte, two bus cycle instruction, such as CLRA.
BA is not output in response to the Wait instruction. If interrupts are to be utilized in removing the processor from a

FIGURE 22 - HALT/SA TIMING DIAGRAM

In/Out

M I~______________~
R/W~
Add/Data

Add
- - - -.....f4-Fetch.
Note Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts. unless otherWise n01ed

3-716

MC68120, MC68121

Wait State while in the Halt/BA mode then, iR01 and IRQ2
are the only interrupts which may do so; therefore, their
masks must be cleared before entering the Wait State.

Expanded Non-Multiplexed Mode - In this mode, both
SCl and SC2 are configured as outputs. SCl functions as
Input/Output Select (lOS) and is asserted (active-low) only
when addresses $0100 through $01 FF are accessed. SC2 is
configured as Riw and is used to control the direction of
local data bus transfers. An MPU read is enabled when R/W
and E are high.

MASKABLE INTERRUPT REQUEST 1 -

IRQ1
This level-sensitive input can be used to request an interrupt sequence. The IPC will complete the current instruction
before it responds to the request. If the interrupt mask bit
{I-bit) in the Condition Code Register is clear, the IPC will
begin an interrupt sequence: a vector is fetched from $FFF8
and $FFF9, transferred to the Program Counter, and instruction execution is continued at the new location. This is explained in greater detail in the Interrupt Section.
IRQl typically requires an external resistor (3K to 10K
depending on external devices drive capability) to V CC for
wire-OR applications. IRQl has no internal pull up resistor.

Expanded Multiplexed Modes - In these modes, SCl is
configured as an input and SC2 is configured as an output.
In the expanded multiplexed modes, the IPC has the ability
to access a 64K byte address space. SCl f~nctions as an input, Address Strobe, which controls demultiplexing and
enabling of the eight least significant addresses and the data
buses.
By using a transparent latch such as an SN74LS373 or
MC6882, Address Strobe (AS) can also be used to demultiplex the two buses external to the IPC. (See Figure 23.)
SC2 provides the local Data Bus control signal called
Read/Write (R/W). SC2 is configured as R/W and is used to
control the direction of local data bus transfers. An MPU
read is enabled when R/W and E are high.

STROBE CONTROL 1 AND 2 -

SC1 and SC2
The functions of SCl and SC2 depend on the operating
mode. SCl is configured as an input in all modes except
the Expanded Non-Multiplexed Mode, whereas SC2 is always an output. SCl and SC2 can drive one Schottky load
and 90 pF.

SYSTEM BUS INTERFACE

Single Chip Modes - In these modes, SCl and SC2 are
configured as an input and output, respectively, and both
function as Port 3 control lines. SCl functions as an input
strobe {lS3) and can be used to indicate that Port 3 input
data is ready or output data has been accepted. Three options associated with IS3 are controlled by the Control and
Status Register for Port 3 and are discussed in the Port 3
description.
SC2 is configured as an output strobe (OS3) and can be
used to strobe output data or acknowledge input data for
Port 3. It is controlled by Output Strobe Select (OSS) in the
Port 3 Control and Status Register. The strobe is generated
by a read (OSS=O) or write (OSS= 1) to the Port 3 Data
Register. OS3 timing is shown in Figure 6.

FIGURE 23 GNO

Port 1 is a mode-independent 8-bit data port which permits the external system bus to access the dual-ported RAM
and semaphore registers either asynchronously or synchronously with respect to the E clock. In addition to the
eight data lines (SOO-S07), eight address (SAO-SA7) and
three control lines (SR/W, CS, OTACK) are used to access
the dual-ported RAM and semaphore registers.
Port 1 Data Lines (SDO-SD7) - These data lines are bidirectional data lines which allow data transfer between the
dual-ported RAM or the semaphore registers, and the
system bus. The data bus output drivers are three-state
devices which remain in the high-impedance state except

TYPICAL LATCH ARRANGEMENT

...

AS
,

Port 3
Address/ Data

I I

EN/G
01

OC

01

SN74S373
(Typical)

08

Address: AO-A7

08

Data: 00-07
~

~

3·717

I

MC68120, MC68121

during a read of the IPC dual-ported RAM or semaphore
registers by the system processor.

Inputs on P20, P21 and P22 determine the operating mode
which is latched into the Program Control Register on the
positive edge of RESET. The mode may be read from the
Port 2 Data Register (PC2 is latched from pin 45).
Port 2 also provides an interface for the Serial Communications Interface and Timer. 8it 1, if configured as an
output, is dedicated to the Timer Output Compare function
and cannot be used to provide output from the Port 2 Data
Register.

System Address Lines (SAO-SA7) - The address lines
together with the Chip Select signal allow any of the 128
bytes of RAM or six semaphore registers to be uniquely
selected from the system bus. The address lines must be
valid before the CS signal goes low for the asynchronous interface and valid before the E signal goes high for the synchronous interface. The system interface must be deselected
between reads or between writes for the asynchronous
operation.

I

PORT 3 - P30-P37
Port 3 can be configured as an 1/0 port, a bi-directional
8-bit data bus, or a multiplexed address/ data bus depending
upon the operating mode. The TTL compatible three-state
output buffers can drive one Schottky TTL load and 90 pF.

System Read/Write (SRiW) - This signal is generated by
the system bus to control the direction of data trans~ on
the data bus. With the IPC selected, a low on the SR/W line
enables the input buffers, and data is transferred from the
system processor to the IPC. When SR/W is high and the
chip is selected, the data output buffers are turned on and
data is transferred from the IPC to the system bus.

Single Chip Modes - In these modes, Port 3 is an 8-bit
I/O port where each line is configured by the Port 3 Data
Direction Register. Associated with Port 3 are two lines, IS3
and OS3, which can be used to control Port 3 data transfers.
Three Port 3 options, controlled by the Port 3 Control and
Status Register and available only in the Single Chip Modes
are: 1) Port 3 input data can be latched using 1S3 as a control
signal, 2) OS3 can be generated by either an IPC read or
write to the Port 3 Data Register, and 3) an iROT interrupt
can be enabled by an IS3 negative edge. Port 3 latch timing
is shown in Figure 7.

Chip Select (CS) - This signal is a TTL compatible input
signal, used to activate the system bus interface and allows
transfer of data between the IPC and the system processor
during synchronous or asynchronous accesses. CS provides
the synchronizing signal for the Semaphore registers during
access by the system bus.

PORT 3 CONTROL AND STATUS REGISTER

Data Transfer Acknowledge (DTACK) - This bidirectional
control line is used to determine synchronous or asynchronous system bus accesses and to provide the data
acknowledge signal for asynchronous data transfers.
As an input, it is sampled on the falling edge of CS by the
IPC to determine if the system bus is being accessed synchronously or asynchronously with respect to the E clock.
If DT ACK is low when sampled, the system bus is synchronous and data will be transferred during E high as shown
in Figure 13.
If t'5TAcr is high when sampled, the system bus is asynchronous. In this mode DT ACK becomes an output that is
asserted low when data is on the bus during a system read or
when a data transfer is completed during a system write.
Refer to Figures 9 through 12.
DT ACK requires an external pullup resistor when the
system bus is run asynchronously since it is then a bidirectional handshake line for information transfer on the system
data bus.

6543210
$OF

Bits 0-2 Not used.
Bit 3
LATCH ENABLE. This bit controls the input latch
for Port 3. If set, input data is latched by an IS3
negative edge. The latch is transparent after a read
of the Port 3 Data Register. LATCH ENABLE is
cleared by Reset.
Bit 4
OSS (Output Strobe Select). This bit determines
whether OS3 will be generated by a read or write of
the Port 3 Data Register. When clear, the strobe is
generated by a read; when set, it is generated by a
write. OSS is cleared by Reset.
Bit 5
Not used.
Bit 6
IS3-IR01 ENABLE. When set, an IROl interrupt
will be enabled whenever IS3 FLAG is set; when
clear, the interrupt is inhibited. This bit is cleared by
Reset.
Bit 7
183 FLAG. This read-only status bit is set by an IS3
negative edge. It is cleared by a read of the Port 3
Control and Status Register (with IS3 FLAG set)
followed by a read or write to the Port 3 Data
Register or by Reset.

PORT 2 - P20-P24
Port 2 is a mode independent 5-bit I/O port where each
line is configured by its Data Direction Register. During
reset, all lines are configured as inputs. The TTL compatible
three-state output buffers can drive one Schottky TTL load
and 30 pF, or CMOS devices using external pullup resistors.
P20, P21 and P22 must always be connected to provide the
operating mode.

Expanded Non-Multiplexed Mode - In this mode, Port 3
is configured as a bi-directional data bus (DO-D7). The direction of data transfers is controlled by R/IN (SC2!. Data
transfers are clocked by E (Enable!.

PORT 2 DATA REGISTER

I

7
PC2

I

6
PCl

5

I I
PCO

4

3

P241 P23

I

2
P22

I

1
P2l

I

0
P20

$03

3-718

MC68120, MC68121

pull up resistors to more than 5 volts, however, cannot be
used.

Expanded Multiplexed Modes - In these modes, Port 3 is
configured as a time-multiplexed address (AO-A?) and data
bus (00-07). Address Strobe (AS) must be input on SC1,
and can be used externally to de-multiplex the two buses.
Port 3 is held in a high-impedance state between valid address and data to prevent potential bus conflicts.

Expanded Non-Multiplexed Mode - In this mode, Port 4
is configured from reset as an 8-bit input port, where the
Data Direction Register can be written, to provide any or all
of address lines AO-A7. Internal pullup resistors are intended
to pull the lines high until the Data Direction Register is configured.,

PORT 4 - P40-P47
Port 4 is configured as 8-bit I/O port, as address outputs,
or as data inputs depending on the operating mode. Port 4
can drive one Schottky TTL load and 90 pF and is the only
port with internal pull up resistors.

Expanded Multiplexed Mode - In all these modes except
Mode 6, Port 4 functions as half of the address bus and provides A8 to A 15. In Mode 6, the port is configured from reset
as an 8-bit parallel input port; the Port 4 Data-Direction
Register must be written to provide any or all of address
lines, A8 to A 15. Internal pullup resistors are intended to pull
the lines high until the Data Direction Register is configured
(bit 0 controls A8, etc.).

Single Chip Modes - In these modes, Port 4 functions as
an 8-bit I/O port where each line is configured by the Port 4
Data Direction Register. Internal pullup resistors allow the
port to directly interface with CMOS at 5 volt levels. External

OPERATING MODES
Single Chip Modes (4, 7) - In Single Chip Mode, three of
the four IPC ports are configured as parallel input/output
data ports, as shown in Figure 25. The IPC functions as a
complete microcomputer in these two modes without external address or data buses. A maximum of 21 I/O lines and
two Port 3 control lines are provided.
In Single Chip Test Mode (4), the RAM responds to addresses $XX80 (X = don't care) through $XXFF and the ROM
is removed from the internal address map. A test program
must first be loaded into the RAM using Modes 0, 1, 2, or 6.
If the IPC is reset and then programmed into Mode 4, execution will begin at $XXFE:XXFF. Mode 5 can be irreversibly
entered from Mode 4 without going through reset by setting
bit 5 of the Port 2 Data Register. This mode is used primarily
to test Port 3 and 4 in the Single Chip and Non-Multiplexed
Modes.

The IPC provides eight different operating modes which
are selectable by hardware programming and referred to as
Modes 0 through 7. The operating mode controls the
memory map, configuration of Port 3, Port 4, SC1 and SC2
and the address location of the interrupt vectors.
FUNDAMENTAL MODES
The eight modes of the IPC can be grouped into three fundamental modes which refer to the type of bus it supports:
Single Chip, Expanded Non-Multiplexed, and Expanded
Multiplexed. Single Chip includes Modes 4 and 7, Expanded
Non-Multiplexed is Mode 5 and the remaining five are Expanded Multiplexed modes. A system utilizing three
MC68120's, one in each of the fundamental operating
modes, is shown in Figure 24. Table 6 summarizes the
characteristics of the operating modes.

TABLE 6 - SUMMARY OF IPe OPERATING MODES
Common to all Modes:
System Bus Interface
Reserved Register Area
6 Semaphore Registers
I/O Port 2
Programmable Timer
Serial Communications Interface
12B bytes of Dual Ported RAM
Single Chip Mode*
2048 Bytes of ROM !Internal)
Port 3 is a Parallel I/O Port with Two Control Lines
Port 4 is a Parallel I/O Port
SCl is Input Strobe 3 !lS3)
SC2 is Output Strobe 3 (OS3)
Expanded Non-Multiplexed Mode*
2048 Bytes of ROM !Internal)
256 Bytes of External Memory Space
Port 3 is an a-Bit Data Bus
Port 4 is an Address Bus
SC1 is Input/Output Select !lOS)
SC2 is Read/Write (RiW)

Expanded Multiplexed Modes
Four Memory Space Options (64K Address Space):
(1) MDOS Compatible
(2) No ROM
(3) External Vector Space
(4) ROM with Partial Address Bus*
External Memory Space Accessed Through:
Port 3 as a Multiplexed Address/Data Bus
Port 4 as an Address Bus (High)
SCl is Address Strobe Bus (AS) Input
SC2 is Read/Write (R/W)
Test Modes
Expanded Multiplexed Test Mode
May be Used to Test RAM and ROM*
Single Chip and Non-Multiplexed Test Mode*
May be Used to Test Ports 3 and 4 as I/O Ports

* MC68120 only

3·719

I

MC68120, MC68121

FIGURE 24 - IPC FUNDAMENTAL OPERATING MODES

68000
6809
6801
6802

6808
6803
6800

RAM

Single Chip Mode

ROM

I

SSDA
ADLC
CRTC

Expanded
Non-Multiplexed
Mode

System Bus

Expanded
Multiplexed
Mode

ROM

Local
Bus
RAM

PIA
ACIA
GPIA
PTM

SSDA
ADLC
CRTC

Expanded-Multiplexed Modes (0, 1,2, 3, 6) - In the Expanded Multiplexed Modes, the IPC has the ability to access
a 64K-byte memory space. Port 3 functions as a timemultiplexed address/ data bus with address valid on the
negative edge of Address Strobe (AS) and the data bus valid
while E is high. In Modes Dto 3, Port 4 provides address lines
AS-A 15. However, in Mode 6, Port 4 can provide any subset
of AS to A 15 while retaining the remainder as input lines.
Writing 1's to the desired bits in the Data Direction Register
(DDR) will output the corresponding address lines while the
remaining bits will remain inputs (as configured from reset or
from O's written to the DDR). Internal pullup resistors are
provided to pull Port 4 lines high until software configures
the port. Initialization of Port 4 in Mode six must be done to
obtain any upper address lines externally.

Expanded Non-Multiplexed Mode (5) - A modest amount
of external memory space is provided in the Expanded NonMultiplexed Mode while retaining significant on-chip
resources. Port 3 functions as an S-bit bi-directional data bus
and Port 4 is configured as an input data port. Any combination of AD to A7 may be provided while retaining the remainder as input data lines. Any combination of the eight
least-significant address lines may be obtained by writing to
the Port 4 Data Direction Register. Internal pullup resistors
are provided to pull Port 4 lines high until it is configured.
Figure 26 illustrates the external resources available in the
Expanded Non-Multiplexed Mode. The IPC interfaces directly with M6800 Family parts and can access 256 bytes of external address space at $100 through $1 FF. lOS provides an
address decode of external memory ($100-$1 FF) and may be
used as an address or chip select line.

3-720

MC68120, MC68121

FIGURE 25 -

SINGLE CHIP MODE

VCC

MC68120

RESET

HALT IBA/NMI
IR01

Port 3
8110 Lines

8 System
Address Lines
Port 1
8 System
Data Lines

iS3

System
Bus

SR/W

OS3

I

CS
Port 4
8110 Lines

DTACK
Port 2
5110 Lines
Serial 110,
16-Bit Timer

-

VSS

FIGURE 26 -

EXPANDED NON-MULTIPLEXED MODE

VCC

RESET

MC68120

HALT/BA/NMI
IR01

Port 3
8 Data Lines

8 System
Address Lines
Port 1
8 System
Data Lines

R/W

lOS

SRiw

CS
Port 4
8 Address Lines

DTACK
Port 2
5110 Lines
Serial 1/0,
16-Bit Timer

VSS

3-721

System
Bus

MC68120, MC68121

after the positive edge of RESET. In addition, the internal
and external data buses are connected together so there
must be no memory map overlap (to avoid potential bus conflicts). Mode 0 is used primarily to verify the ROM pattern
and monitor the internal data bus with automated test equipment.

Figure 27 depicts the external resources available in the
Expanded-Multiplexed Modes. Address Strobe can be used
to control a transparent D-type latch to capture addresses
AO-A7, as shown in Figure 23. This allows Port 3 to function
as a Data Bus when E is high.
In Mode 0, the reset vector is external at $BFFE and $BFFF
FIGURE 27 -

EXPANDED MULTIPLEXED MODE
VCC

HAL T lBAINMI

MC681201
MC68121

IRQl

Port 3

8 System
Address Lines

8 Lines Multiplexed

I

Add ressl Data

Port 1
8 System
Data Lines

R/W.----I
AS

------'l~

System
Bus

SR/W

Cs
Port 4
8 Address Lines

DTACK
Port 2
5110 Lines
Serial 110,
16-Bit Timer

VSS

MODE PROGRAMMING

configured as outputs, the circuit shown in Figure 29 may be
used; otherwise, the three-state buffers can be used to provide isolation while programming the mode.

The operating mode is programmed by the levels asserted
on P22, P21, and P20 during the positive edge of RESET.
These are latched into PC2, PC1, and PCO of the program
control register. The operating mode may be read from the
Port 2 Data Register and programming levels and timing
must be met as shown in Figure 28 and Table 7. Any mode
may be entered from either Mode 0 or Mode 4 without going
through reset by writing the appropriate bits to the port 2
data register. A brief outline of the operating modes is
shown in Table 8.
Circuitry to provide the programming levels is primarily
dependent on the normal system use of the three pins. If

FIGURE 28 -

MEMORY MAPS
The IPC provides up to 64K bytes of address space
depending upon the operating mode. A memory map for
each operating mode is shown in Figure 30. In Modes 1Rand
6R, the "R" means the ROM has been relocated by a mask
option. The first 32 locations of each map are reserved for
the IPe internal register area, as shown in Table 9, with exceptions as indicated.

MODE PROGRAMMING TIMING
See Figure 29
for Diode

tMPH
IP20, P21, P22)
Mode Inputs
(P20, P21, P22)

VMPH Min
RESET
VMPL Max

3-722

VMPL
Mode Latch Level

MC68120, MC68121

TABLE 7 -

MODE PROGRAMMING SPECIFICATIONS (See Figure 30)
Symbol

Min

Typ

Max

Mode Programming Input Voltage Low

VMPL

-

-

1.8

Mode Programming Input Voltage High

VMPH

4.0

-

-

Characteristic

Unit

V
V

Mode Programming Diode Differential (if Diodes are Used)

VMPDD

0.6

-

-

RESET Low Pulse Width

PWRSTL

3.0

-

-

E-Cycles

Mode Programming Setup Time

tMPS

2.0

-

-

E-Cycles

Mode Programming Hold Time
RESET Rise Time~ 1 p's
RESET Rise Time< 1 p's

tMPH

0
100

-

-

ns

-

-

TABLE 8 -

Mode

Pin 45
P22
PC2

Pin 44
P21
PC1

Pin 43
P20
PCO

MODE SELECTION SUMMARY

ROM

RAM

Interrupt
Vectors

Bus
Mode

Operating
Mode

Single Chip

7

H

H

H

I

I

I

6

H

H

L

I

I

I

I
MUX(5,6)

I
1(2)

I
1(1)

I

NMUX(5,6)

I

Multiplexed/ RAM(4)
Multiplexed/RAM(4)

5

H

L

H

4

H

L

L

V

Multiplexed/ Partial Decode(5)
Non-Multiplexed/ Partial Decode(5)

3

L

H

E

E

2

L

H
H

1(7)

I
MUX(4)

L

E

I

E

MUX(4)

1

L

L

H

I

I

Multiplexed/RAM and ROM(4)

L

L

L

I

I

E
E(3)

MUX(4)

0

MUX(4)

Multiplexed Test(4)

Legend:
I - Internal
E - External
MUX - Multiplexed
NMUX - Non-Multiplexed
L - Logic "0"
H - Logic "1"

Single Chip Test

-

Notes:
(1) Internal RAM is addressed at $XX80
(2) Internal ROM is disabled
(3) Interrupt vectors externally located at $BFFO-$BFFF
(4) Addresses associated with Ports 3 and 4 are considered external in Modes 0, 1, 2, and 3
(5) Addresses associated with Port 3 are considered external in Modes 5 and 6
(6) Port 4 default is user data input; address output is optional by writing to Port 4 Data Direction Register
(7) Internal RAM and registers located at $COXX (for use with MDOS)

FIGURE 29 -

TYPICAL MODE PROGRAMMING CIRCUIT

V C

R2

R1

R1

R1

MC68120/
MC68121

,--,

RESET ~::--_..............._-+-_-+-_+-___---,-48,,", RESET
P20

43 P20 (PCO)

I

P21
P22

44 P21 (PC1)
I

I

45 P22 (PC2)

L __ J

Optional
Three-State
Buffers
MC14066B

Notes:
1. Mode 7 as shown
2. R2-C = Reset time constant
3. R1 = 10 k (typical)
4. D= 1N914, 1N4001 (typical)

3·723

I

MC68120, MC68121

FIGURE 30 -

MC68120
Mode
Multiolexed Test Mode

IPC MEMORY MAPS

o

Internal Registers
S001 F
External Memory Space
S0080
Internal RAM
SOOFF

I

External Memory Space

SBFFO

External Interrupt Vectors l21

SBFFF

Notes:
1i Excludes the following addresses which may be
used externally: S04, S05, S06, S07 and SOF
21 The Interrupt vectors are externally located at
SBFFO-SBFFF.
31 There must be no overlapping of Internal and external memory spaces to avoid driving the data
bus with more than one device
41 This mode is the only mode which may be used
to examine the interrupt vectors in Internal ROM
using an external RESET vector.
51 MC68120 only

External Memory Space

SF800
Internal ROMI51

MC68120
Mode

1

Multiplexed/RAM and ROM

SOOOO p-,-r7""lr-Tn

Internal Registers l11
External Memory Space
Notes:
11 Excludes the following addresses which may be
used externally: S04, $05, S06, S07 and SOF.
21 Internal ROM addresses SFFFO to SFFFF are not
usable.

Internal RAM

External Memory Space

Internal ROM

SFFFF'--_ _ _v

External Interrupt Vectors l21

3-724

MC68120, MC68121

FIGURE 30 -

MC681201
MC68121
Mode

IPC MEMORY MAPS (CONTINUED)

2

MC681201
MC68121
Mode

3

Multlplexed/RAM, MDOS Compatible (1)
Multlplexedl RAM

$OOOO~---'"

Internal Registers l 1)
External Memory Space

External Memory Space
Internal RAM

Internal Registers (2 )
External Memory Space
External Memory Space
Internal RAM
External Memory Space
$FFFO .....----t<

External Interrupt Vectors
External Interrupt Vectors

$FFFF~---""J

Notes:
1) Relocating the internal registers and the internal
RAM to high memory allows processor to run
MDOS.
2) Excludes the following addresses which may be
used externally: $COO4, $C005, $COO6, $C007,
and $COOF

Notes·
1) Excludes the following addresses which may be
used externally: $04, $05, $06, $07, and $OF.

MC68120
Mode

MC68120
Mode

4

5

Non-Multiplexedl Partial Decode 121 (3)

Single Chip Test (2 )

$OOOOI11}

::~JII~:~'~~I ~~:""

$OOOO~} Internal Reg sters (5 )
i

$001 F

$OOFF
$0100

External Memory Space

I

$01 FF

Unusablel 1)(4)

$XX80131~..,....,;....,_"7"'I} Internal
$XXFF

m~)lnternaIROM

$FFFF~

RAMI41

Internal Interrupt Vectors

10<""110<",",, Veo,""

Notes·
11 Excludes the following addresses which may not
be used externally: $04, $06, and $OF (no lOS).
21 This mode may be entered without going
through Reset by using Mode 4 and subsequently writing a" 1" into bit 5 (PCOI of Port 2 Data Register.
31 Address lines AO to A7 will not contain addresses
until the Data Direction Register for Port 4 has
been written with "1's" in the appropriate bits.
These address lines will assert ''1's'' until made
outputs by writing the Data Direction Register.

Notes:
1) The internal ROM is disabled.
21 Mode 4 may be changed to Mode 5 without having to assert RESET by writing a "1" into bit 5(PCOI
of Port 2 Data Register.
3) Addresses A8 to A 15 are treated as "don't
cares" to decode internal RAM
4) Internal RAM will appear at $XX80 to $XXFF.
5) MPU Read of Port 3 Data Direction Register will
access Port 3 Data Register instead.

3-725

I

MC68120, MC68121

FIGURE 30 -

MC68120
Mode

IPC MEMORY MAPS (CONCLUDED)

6

Multlplexed/ Partial Decode
$0000
Internal Registersl11121
$oolF
External Memory Space
$0080

Notes·
11 Excludes the following addresses which may be
used externally: $04, $06, $OF.
21 Address lines A8-A 15 will not contain addresses
until the Data Direction Register for Port 4 has
been written with ''1's'' in the appropriate bits.
These address lines will assert "l's" until made
outputs by writing the Data Direction Register.

Internal RAM

II

External Memory Space

$F8oo
Internal ROM
Internal Interrupt Vectors

$FFFF

MC68120
Mode

7

Single Chip

$oooo~} Internal Reglsters111
$001 F ,nusable
$0080
}
$ooFF

Internal RAM
Notes
11 MPU reads of Port 3's Data Direction Register
will access Port 3's Data Register instead

Unusable

3-726

MC68120, MC68121

TABLE 9- INTERNAL REGISTER AREA
Address * * * *
( Hexadecimal)

Register
Reserved
Port 2 Data Direction Register* * *
Reserved
Port 2 Data Register
Port
Port
Port
Port

3
4
3
4

Data
Data
Data
Data

00
01
02
03

SCI Rate and Mode Control Register
T ransmitl Receive Control and Status Register
SCI Receive Data Register
SCI Transmit Data Register

04*
05* *
06*
07 * *

Direction Register* * *
Direction Register* * *
Register
Register

Timer Control and Status Register
Counter (High Byte)
Counter (Low Byte)
Output Compare Register (High Byte)

08
09
OA
OB

Output Compare Register (Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
Port 3 Control and Status Register

OC
OD
OE
OF*

Register

Function Control Register
Counter Alternate Address (High Byte)
Counter Alternate Address (Low Byte)
Semaphore 1
Semaphore 2
Semaphore 3
Semaphore 4
Semaphore 5
Semaphore 6
Reserved

Address * * * *
(Hexadecimal)
10
11
12
13
14
15
16
17
18
19
lA
lB
lC
lD-1F

* * * 1 = Output, 0 = Input
* * * * These addresses relocated at $COOO-$COl F in Mode 3.

* These external addresses in Modes 0, 1, 2, 3, 5, 6 cannot be accessed in Mode 5 (no lOS)
* * These are external addresses in Modes 0, 1, 2, 3

INTERRUPTS

The IPC supports two types of interrupt requests:
Maskable and Non-Maskable. A Non-Maskable Interrupt
(NMIl is always recognized and acted upon at the completion of the current instruction. Maskable interrupts are controlled by the Condition Code Register I-bit and by individual
enable bits. The I-bit controls all maskable interrupts. Of the
maskable interrupts, there are two types: TROT and IRQ2.
The Programmable Timer and Serial Communications Interface use an internal I RQ2 interrupt line, as' shown in the
block diagram of the IPC. External devices (and IS3) use
\Rill. An IRQ1 interrupt is serviced before an IRQ2 interrupt
if both are pending.
All IRQ2 interrupts use hardware prioritized vectors. The

TABLE 10 -

Single SCI interrupt and three timer interrupts are serviced in
a prioritized order where each is vectored to a separate location. All IPC vector locations are shown in Table 10, from
highest (top) to lowest (bottom) priority.
The interrupt flowchart is depicted in Figure 31. The Program Counter, Index Register, Accumulator A, Accumulator
B, and Condition Code Register are pushed to the stack. The
I-bit is set to inhibit maskable interrupts and a vector is
fetChed corresponding to the current highest priority interrupt. The vector is transferred to the Program Counter and
instruction execution is resumed. The general interrupt timing sequence is shown in Figure 32. The Interrupt HALT / BA
timing is illustrated in Figure 21 and 22.

MCU VECTOR LOCATIONS *

MSB

LSB

$FFFE

FFFF

RESET* *

Interrupt
NMI

FFFC

FFFD

FFFA

FFFB

Software Interrupt (SWI)

FFF8

FFF9

IRQl (or IS3)

FFF6

FFF7

ICF (Input Capture)

FFF4

FFF5

OCF (Output Compare)

FFF2

FFF3

TOF (Timer Overflow)

FFFO

FFF1

SCI (RDRF+ORFE+TDRE)

*These locations are relocated at $BFFO-$BFFF In Mode O.
* * Highest priority.

3-727

I

FIGURE 31 -

•

INTERRUPT FLOWCHART

3:

n

...

0)

CO

N

?
3:

n
0)

...
...
CO

N

U)

..:...

I\.)
0)

SCI = TIE-TORE + RIE-IRORF + ORFEI

Vector Mode 0

PC

Modes 1-7

NMI

BFFC-BFFD

FFFC-FFFD Non-Maskable Interrupt

SWI

BFFA-BFFB

FFFA-FFFB Software Interrupt

IRQ1

BFF8-BFF9

FFF8-FFF9 Maskable Interrupt Request 1

ICF

BFF6-BFF7

FFF6-FFF7 Input Capture Interrupt

OCF

BFF4-BFF5

FFF4-FFF5 Output Compare Interrupt

TOF

BFF2-BFF3

FFF2-FFF3 Timer Overflow Interrupt

SCI

BFFO-BFFl

FFFO-FFFl
A

SCI Interrupt ITORE + RORF + ORFEI

MC68120, MC68121

FIGURE 32 -

INTERRUPT SEQUENCE

Cycle
Last Instructlon...j

#1

#2

#3

#4

#5

#6

#1

#S

#9

#10

#11

#12

I

k-tpcs
\L~

NMI or IRQ2

___________________________________________________________

~ ~tPcs

First Inst. of
Interrupt Routine

Internal

-----,..r----,.,---""""'.r_--..,---""'"r_-"',---",----..r--~.r_--V_--V_--_V,..--_V--"r--"""'\.

Data B u s - - -..... '---Ao-p-c-od-eAo-p-c-od-eA -PC-O'-7/\..P-C-S-'1-5A -X-O-'7J

,--X-S-1-5A-A-C-CA--.J"--A-C-C-BJ'I"--C-C-R.J'\~I-rre-Ie-v-an-t" -_ _''-..,...-_,,-_ _r
Data

\~--------------------------~I

Internal R/W

PROGRAMMABLE TIMER
when clear, the interrupt is inhibited. It is
cleared by reset.

The Programmable Timer can be used to perform input
waveform measurements while independently generating an
output waveform. Pulse widths can vary from several
microseconds to many seconds. A block diagram of the
Timer is shown in Figure 33.

Bit 3 EOCI Enable Output Compare Interrupt. When set, an
IR02 interrupt is enabled for an output compare; when clear, the interrupt is inhibited. It is
cleared by reset.

TIMER CONTROL AND STATUS REGISTER ($08)

Bit 4 EICI

The Timer Control and Status Register (TCSR) is an 8-bit
register of which all bits are readable while bits 0-4 can be
written. The three most significant bits provide the timer
status and they indicate:

Enable Input Capture Interrupt. When set, an
IR02 interrupt is enabled for an input capture;
when clear, the interrupt is inhibited. It is
cleared by reset.

Bit 5 TOF

Timer Overflow Flag. TOF is set when the
counter contains all 1's. It is cleared by reading
the TCSR (with TOF set) followed by reading
the highest byte of the counter ($09), or by
reset. Reading the counter at $15 will not clear
TOF.

Bit 6 OCF

Output Compare Flag. OCF is set when the Output Compare Register matches the free-running
counter. It is cleared by reading the TCSR (with
OCF set) and then writing to the Output Compare Register ($OB or $OC), or by reset.
Input Capture Flag. ICF is set to indicate a proper level transition. It is cleared by reading the
TCSR (with ICF set) and then reading the Input
Capture Register High Byte ($OD), or by reset.

• a proper level transition has been detected, or
• a match has been found between the free-running
counter and the output compare register, or
• the free-running counter has overflowed.
Each of the three events can generate an I R02 interrupt
and is controlled by an individual enable bit in the TCSR.
TIMER CONTROL AND STATUS REGISTER
(TSCR)

6

5

4

3

2

1

0

Bit 7 ICF
Bit 0 OLVL Output level. OLVL is clocked to the output level
register by a successful output compare and will
appear at P21 if Bit 1 of the Port 2 Data Direction
Register is set. It is cleared by reset.
Bit 1 IEDG Input Edge. IEDG is cleared by reset and controls which level transition will trigger a counter
transfer to the Input Capture Register:

Bit 2 ETOI

IEDG = 0 Transfer on a negative edge
IEDG = 1 Transfer on a positive edge
Enable Timer Overflow Interrupt. When set, an
IR02 interrupt is enabled for a timer overflow;

COUNTER ($09:0A)
The key timer element is a 16-bit free-running counter
which is incremented by E (Enable!' It is cleared during reset
and is a read-only with one exception: a write to the counter
($09) will preset it to $FFF8. This feature, intended for
testing, can disturb serial operations because the counter
provides the SCI internal bit rate clock. TOF is set whenever
the counter contains all 1's. The counter may also be read at
location $15 and $16 to avoid the clearing of the TOF.

3-729

I

MC68120, MC68121

FIGURE 33 -

PROGRAMMABLE TIMER -

BLOCK DIAGRAM

MC68120/MC68121 Internal Bus

I
and
Status
Register
$08

Bit 1
Port 2

DDR

IR02
Output Compare Pulse

_ _ _ _I

Output Input
Level Edge
Bit 1
Bit 0
Port 2 Port 2

OUTPUT COMPARE REGISTER ($OB:OC)

INPUT CAPTURE REGISTER ($OD:OE)

The Output Compare Register is a 16-bit Read/Write
register used to control an output waveform or provide an arbitrary timeout flag. It is compared with the free-running
counter on each E-cycle. When a match is found, OCF is set
and OLVL is clocked to an output level register. If Port 2, bit
1 is configured as an output, OL VL will appear at P21. The
Output Compare Register and OL VL can then be changed
for the next compare. The compare function is inhibited for
one cycle after a write to the high byte of the counter ($OB)
to ensure a valid compare. The Output Compare Register is
set to $FFFF by reset.

The Input Capture Register is a 16-bit read-only register
used to store the free-running counter when a "proper" input transition occurs as defined by IEDG. Port 2, bit 0 should
be configured as an input, but the edge detect circuit always
senses P20, even when configured as an output. An input
capture can occur independently of ICF: the input capture
register always contains the most current value regardless of
whether ICF was previously set or not. Counter transfer is inhibited, however, between accesses of a double byte IPC
read. The input pulse width must be at least two E-cycles to
ensure an input capture under all conditions.

SERIAL COMMUNICATIONS INTERFACE (SCI)
A full-duplex asynchronous Serial Communications Interface (SCI) is provided with two data formats and a choice of
Baud rates. The SCI transmitter and receiver are functionally
independent, but use the same data format and bit rate.
Serial data formats include standard mark/space (NRZ) and
Bi-phase. Both formats provide one start bit, eight data bits,
and one stop bit. "Baud" and "bit rate" are used
synonymously in the following description.

beginning of the message. In order to allow uninterested
MPUs to ignore the remainder of the message, a wake-up
feature is included whereby all further SCI receiver flag (and
interrupt) processing can be inhibited until the data line goes
idle. An SCI receiver is re-enabled by an idle string of ten
consecutive 1's or by reset. Software must provide the required idle string between consecutive messages and prevent it within messages.

WAKE-UP FEATURE

PROGRAMMABLE OPTIONS

The following features of the SCI are programmable:
• format: standard mark/space (NRZ) or Bi-phase

In. a typical serial loop mUlti-processor configuration, the
software protocol will usually identify the addressee(s) at the

3·730

MC68120, MC68121

RATE AND MODE CONTROL REGISTER (RMCR)

• clock: external or internal clock source
• Baud rate: one of four per E-clock frequency, or oneeighth of the external clock input to P22
• wake-up features: enabled or disabled
• interrupt requests: enabled individually for transmitter
and receiver

7

x

6
X

I

5
X

I

4
X

321

SERIAL COMMUNICATIONS REGISTERS
The Serial Communications Interface includes four addressable registers as depicted in Figure 34. It is controlled
by the Rate and Mode Control Register and the
Transmit/Receive Control and Status Register. Data is
transmitted and received utilizing a write-only Transmit
Register and read-only Receive Register. The shift registers
are not accessible by software.

NOTE: The source of SCI internal baud rate clock is the
free-running counter of the timer. An IPC write to the
counter can disturb serial operations.

FIGURE 34 - SCI REGISTERS
Bit 7

Rate and Mode Control Register

I

I

0

I CC1 I CCO I SS1 I SSO I $10

Bit 1: BitO SSl:SS0 Speed Select. These two bits select
the Baud rate when using the internal clock.
Four rates may be selected which are a function
of the IPC input frequency (E). Table 11 lists bit
times and rates for three selected IPC frequencies.
Bit 3: Bit 2 CC1:CCO Clock Control and Format Select.
These two bits control the format and select the
serial clock source. If CC1 is set, the Data Direction Register (DDR) value for P22 is forced to
the complement of CCO and cannot be altered
until CCl is cleared. If Cel is cleared after having been set, its DDR value is unchanged. Table
12 defines the format, clock source, and use of
P22.
If both CCl and CCO are set, an external TTL compatible
clock must be connected to P22 at eight times (8X) the
desired Baud rate, but not greater than E, with a duty cycle
of 50% (± 10%). If CCl :CCO= 10, the internal Baud rate
clock is provided at P22 regardless of the values for TE or RE.

• clock output: internal bit rate clock enabled or disabled
to P22

Rate and Mode Control Register ($10) - The Rate and
Mode Control Register (RMCR) controls the SCI Baud rate,
format, clock source, and under certain conditions, the configuration of P22. The register consists of four write-only bits
which are cleared by reset. The two least significant bits control the Baud rate of the internal clock and the remaining two
bits control the format and clock source.

I

CCl

Bit 0

I I Issol
CCO

SSl

$10

Transmit/ Receive Control and Status Register

RDRF 'ORFE ITDRE' RfE'

RE

I

TIE

TE

I I
WU

$11

Receive Data Register
$12

Port 2

(Not Addressable)
Receive Shift Register

45

47

Transmit Data Register

3-731

11

MC68120, MC68121

TABLE 11 -

TABLE 12 -

I

SCI BIT TIMES AND RATES

SSl:SS0

E

614.4 kHz

1.0 MHz

1.2288 MHz

0 0

+16

26 /Ls/38,400 Baud

16 /Ls/62,500 Baud

13.0/LsI76,800 Baud

0 1

.;- 128

104.2 /Ls/9,600 Baud

.;- 1024

208 /Ls/4,800 Baud
1.67 ms/600 Baud

128 /LsI7812.5 Baud

1 0

1.024 ms/976.6 Baud

833.3 /Ls/ 1,200 Baud

1 1

+4096

6.67ms/150 Baud

4.096 ms/244.1 Baud

3.33 ms/300 Baud

SCI FORMAT AND CLOCK SOURCE CONTROL

CC1:CCO

Format

Clock
Source

Port 2
Bit 2

0 0

Bi-Phase

Internal

Not Used

0 1

NRZ

Internal

Not Used

1 0

NRZ

Internal

Output

1 1

NRZ

External

Input

Bit 6 ORFE

Transmit/ Receive Control and Status Register ($11) The Transmit/ Receive Control and Status Register (TRCSR)
controls the transmitter, receiver, wake-up features, and two
individual interrupts and monitors the status of serial operations. All eight bits are readable while only bits 0 to 4 are
writable. The register is initialized to $20 by reset.
TRANSMIT/RECEIVE CONTROL AND STATUS REGISTER
ITRCSR)
7

6

543

IRDRFIORFEITDREI RIE I

Bit 0 WU

Bit 1 TE

Bit 2 TIE

Bit 3 RE

Bit 4 RIE

Bit 5 TDRE

RE I TIE

Bit 7 RDRF

1
TE

WU

$11

"Wake-up" on Idle Line. When set, WU
enables the wake-up function; it is cleared by
ten consecutive 1's or by reset. WU will not set
if the line is idle.
Transmit Enable. When set, the P24 DDR bit is
set, cannot be changed, and will remain set if
TE is subsequently cleared. When TE is
changed from clear to set, the transmitter is
connected to P24 and a preamble of nine consecutive 1's is transmitted. TE is cleared by
reset.
Transmit Interrupt Enable. When set, an IR02
interrupt is enabled when TDRE is set; when
Clear, the interrupt is inhibited. TIE is cleared
by reset.
Receive Enable. When set, the P23 DDR bit is
cleared, cannot be changed, and will remain
clear if RE is subsequently cleared. While RE is
set, the SCI receiver is enabled. RE is cleared
by reset.
Receiver Interrupt Enable. When set, an IR02
interrupt is enabled when RDRF and/or OR FE
is set; when clear, the interrupt is inhibited.
RIE is cleared by reset.
Transmit Data Register Empty. TDRE is set
when the contents of the Transmit Data
Register is transferred to the output serial shift
register or by reset. It is cleared by reading the
TRCSR (with TDRE set) and then writing to
the Transmit Data Register. Additional data

3-732

will be transmitted only. if TDRE has been
cleared.
Overrun Framing Error. If set, ORFE indicates
either an overrun or framing error. An overrun
occurs when a new byte is ready to transfer to
the Receiver Data Register with RD'RF still set.
A receiver framing error has occurred when
the byte boundaries of the bit stream are not
synchronized to the bit counter. An overrun
can be distinguished from a framing error by
the value of RDRF: if RDRF is set, then an
overrun has occurred; otherwise,a framing error has been detected. Data is not transferred
to the Receive Data Register in an overrun
condition. ORFE is cleared by reading the
TRCSR (with ORFE set) then reading the
Receive Data Register, or by reset.
Receive Data Register Full. RDRF is set when
the contents of the input serial shift register is
transferred to the Receive Data Register. It is
cleared by reading the TRCSR (with RDRF
set), and then reading the Receive Data
Register, or by reset.

SERIAL OPERATIONS
The SCI is initialized by writing the control bytes first to
the Rate and Mode Control Register and then to the
Transmit/Receive Control and Status Register. When TE is
set, the output of the Transmit Shift Register is connected to
P24 and serial output is initiated by the transmission of a
9-bit preamble of 1's.
At this point one of two situations exist: 1) if the Transmit
Data Register is empty (TDRE= 1), a continuous string of 1's
will be sent indicating an idle line, or 2) if a byte has been
written to the Transmit Data Register (TDRE=O), the byte
will be transferred to the Transmit Shift Register (synchronized with the bit rate clock), TDRE will be set, and
transmission will begin.
The start bit (0), eight data bits (beginning with bit 0) and a
stop bit (1), will be transmitted. If TDRE is still set when the
next byte transfer should occur, 1's will be sent until more
data is provided. Receive operation is controlled by RE which
configures P23 as an input and enables the receiver. In Biphase format, the output toggles at the start of each bit and
at half time when a "1" is sent. SCI data formats are illustrated in Figure 35. In receiving Bi-phase, a "1" is input
when two transitions occur in less than 3/4 bit-time, and a
"0" is input when more than 3/4 bit-time passes after a transition on P23.

MC68120, MC68121

FIGURE 35 -

SCI DATA FORMATS

Output
Clock

NRZ
Format

Bi-Phase
Format

Idle Start

Bit
0

Bit

4

7

Stop

Data: 01001101 ($401

INSTRUCTION SET
The MC68120/MC68121 is upward source and object code
compatible with the MC6800 processor and directly compatible with the M6801 Family processors.

E-cycles. Instruction execution times are summarized in
Table 17. With an input frequency (EI of 1 MHz, E-cycles are
equivalent to microseconds. A cycle-by-cycle description of
bus activity for each instruction is provided in Table 18 and a
description of selected instructions is shown in Figure 38.

PROGRAMMING MODEL
A programming model for the MC68120/MC68121 is
shown in Figure 14. Accumulator A can be concatenated
with accumulator B and jOintly referred to as accumulator D
where A is the most significant byte. Any operation which
modifies th'e double accumulator will also modify accumulator A and/or B. Other registers are defined as
follows:

Immediate Addressing - The operand is contained in the
following byte(sl of the instruction where the number of
bytes matches the size of the register. These are two or three
byte instructions.
Direct Addressing - The least significant byte of the
operand address is contained in the second byte of the instruction and the most significant byte is assumed to be $00.
Direct addressing allows the user to access $00 through $FF
using two byte instructions and execution time is reduced by
eliminating the additional memory access (refer to Table 1I.
In most applications, this 256-byte area is reserved for frequently referenced data. Note that no direct addressing of
internal control registers is possible in Mode 3.

Program Counter - The program counter is a 16-bit
register which always points to the next instruction.
Stack Pointer - The Stack Pointer is a 16-bit register
which contains the address of the next available location in a
pushdown/pullup (L1FOI queue. The stack resides in random access memory at a location specified by the software.
Index Register - The Index Register is a 16-bit register
which can be used to store data or provide an address for the
indexed mode of addressing.

Extended Addressing - The second and third bytes of the
instruction contain the absolute address of the operand.
These are three byte instructions.

Accumulators - The IPC contains two 8-bit accumulators, A and B, which are used to store operands and
results from the arithmetic logic unit (ALUI. They can also be
concatenated and referred to as the D (doublel accumulator.
Condition Code Register - The Condition Code Register
indicates the results of an instruction and includes the
following five condition bits: Negative (NI, Zero (ZI,
Overflow (VI, Carry/Borrow from MSB (CI, and half carry
from bit 3 (HI. These bits are testable by the conditional
branch instructions. Bit 4 is the interrupt mask {I-bitl and inhibits all maskable interrupts when set. The two unused bits
b6 and b7, are read as ones.

Indexed Addressing - The unsigned offset contained in
the second byte of the instructions is added with carry to the
Index Register and used to reference memory without
changing the Index Register. These are two byte instructions.
Inherent Addressing - The operand(sl are registers and
no memory reference is required. These are single byte instructions.
Relative Addressing - Relative addressing is used only for
branch instructions. If the branch condition is true, the Program Counter is overwritten with the sum of a Signed single
byte displacement in the second byte of the instruction and
the current Program Counter. This provides a branch range
of -126 to 129 bytes from the first byte of the instruction.
These are two byte instructions.

ADDRESSING MODES
The MC68120/MC68121 provides six addressing modes
which can be used to reference memory. A summary of addressing modes for all instructions is presented in Tables 13,
14, 15 and 16 where execution times are provided in

3-733

I

MC68120, MC68121

TABLE 13 - INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS
Condition Codes
Immed
Pointer Operations

I

Mnemonic OF 8C 4

Direct

Index
Extend Inherent
# OP- # Op- # Op - # OP- #
3 9C 5

2 AC 6 2 BC 6

3

5 4 3 2 1 0
H I N Z V C

,

Booleanl
Arithmetic Operation
P< - M: M + 1

Compare Index Reg

CPX

Decrement Index Reg

DEX

09 3

Decrement Stack Pntr

DES

34 3

1 SP - 1 -SP

Increment Index Reg

INX

08 3

1 X + 1 --X

31 3

1 1 SP + 1 --SP

• • It t t
••• ••
••••••
• • · I. • •
••••••
••
•
••
•
••
•
••
•
••••••
•• • • • • •
• •• •• •• •• ••
••••••

1 X - 1 --X

Increment Stack Pntr

INS

Load Index Reg

LDX

CE 3

3 DE 4

2 EE 5 2 FE 5

3

M --XH, (M + 1) --XL

Load Stack Pntr

LDS

8E 3

3 9E 4

2 AE 5 2 BE 5

3

M -SPH, (M + 1) --SPL

Store Index Reg

STX

DF 4

2 EF 5

2 FF 5

3

XH --M, XL -(M + 1)

Store Stack Pntr

STS

9F 4

2 AF 5

2 BF 5

3

SPH --M, SPL -(M + 1)

Index Reg - Stack Pntr

TXS

35 3

1 X - 1 -SP

Stack Pntr - Index Reg
Add
Push Data

TSX
ABX
PSHX

30 3
3A 3
3C 4

Pull Data

PULX

38 5

1 SP + 1 --X
1 B + X--X
1 XL -- MSp, SP - 1 --SP
XH --MSR SP - 1 --SP
1 SP + 1 -SP, MSp -XH
SP + 1 --SP, MSp -XL

R

R
R

R

TABLE 14 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 1 of 2)
Accumulator and
Memory Operations
Add Acmltrs
Add B to X
Add with Carry
Add
Add Double
And
Shift Left,
Arithmetic
Shift Left Dbl
Shift Right,
Arithmetic
Bit Test
Compare Acmltrs
Clear

Compare
1 's Complement

Decimal Adj, A
Decrement

Exclusive OR

MNE
ABA
ABX
ADCA
ADCB
ADDA
ADDB
ADDD
ANDA
ANOB
ASL
ASLA
ASLB
ASLD
ASR
ASRA
ASRB
BITA
BITB
CBA
CLR
CLRA
CLRB
CMPA
CMPB
COM
COMA
COMB
DAA
DEC
DECA
DECB
EORA
EORB

Extend
Immed
Index
Direct
Inher
Op # Op - # Op - # Op - # Op
#
1B 2 1
3A 3 1
89 2 2 99 3 2 A9 4 2 B9 4 3
C9 2 2 09 3 2 E9 4 2 F9 4 3
8B 2 2 9B 3 2 AB 4 2 BB 4 3
CB 2 2 DB 3 2 EB 4 2 FB 4 3
C3 4 3 D3 5 2 E3 6 2 F3 6 3
84 2 2 94 3 2 A4 4 2 B4 4 3
C4 2 2 04 3 2 E4 4 2 F4 4 3
68 6 2 78 6 3
48 2 1
58 2 1
05 3 1
67 6 2 77 6 3
47 2 1
57 2 1
85 2 2 95 3 2 A5 4 2 B5 4 3
C5 2 2 D5 3 2 E5 4 2 F5 4 3
11 2 1
6F 6 2 7F 6 3
4F 2 1
5F 2 1
A1
2
B1
81 2 2 91 3 2
4
4 3
C1 2 2 D1 3 2 E1 4 2 F1 4 3
63 6 2 73 6 3
43 2 1
53 2 1
19 2 1
6A 6 2 7A 6 3
4A 2 1
5A 2 1
88 2 2 98 3 2 A8 4 2 B8 4 3
C8 2 2 D8 3 2 E8 4 2 F8 4 3

-

3-734

Boolean
Expression
A + B-A
OO:B + X-X
A+M+C-A
B+M+C-B
A +M-A
B + M--A
D + M:M + 1 -D
A·M-A
B· M-B

Condition Codes
H
N Z V C

t

t I t

• ••••
R
R

•
•

R
R

•
•I

I
A·M
B· M
A-B
OO-M
OO-A
OO-B
A-M
B -M
M-M
A-A
B-B
Adj binary sum to BCD
M-1-M
A-1-A
B-1 --B
A C±> M-A
B C±> M--B

I

I

R S
R S
R S

R R
R R
R R

I

I
I

R S
R S
R S

•

I

R
R

••
••

MC68120, MC68121

TABLE 14 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 2 of 2)
Accumulator and
Memory Operations
Increment

Load Acmltrs
Load Double
Logical Shift,
Left

Shift Right,
Logical

Multiply
2'5 Complement
(Negate)
No Operation
Inclusive OR
Push Data
Pull Data
Rotate Left

Rotate Right

Subtract Acmltr
Subtract with
Carry
Store Acmltrs

Subtract
Subtract Double
Transfer Acmltr
Test, Zero or
Minus

MNE
INC
INCA
INCB
LDAA
LDAB
LDD
LSL
LSLA
LSLB
LSLD
LSR
LSRA
LSRB
LSRD
MUL
NEG
NEGA
NEGB
NOP
ORAA
ORAB
PSHA
PSHB
PULA
PULB
ROL
ROLA
ROLB
ROR
RORA
RORB
SBA
SBCA
SBCB
STAA
STAB
STD
SUBA
SUBB
SUBD
TAB
TBA
TST
TSTA
TSTB

Extend
Immed
Direct
Index
Inher
# Op - # Op
Op # Op - # Op
#
6C 6 2 7C 6 3
4C 2 1
5C 2 1
86 2 2 96 3 2 A6 4 2 B6 4 3
C6 2 2 D6 3 2 E6 4 2 F6 4 3
CC 3 3 DC 4 2 EC 5 2 FC 5 3
68 6 2 78 6 3
48 2 1
58 2 1
05 3 1
64 6 2 74 6 3
44 2 1
54 2 1
04 3 1
3D 10 1
60 6 2 70 6 3
40 2 1
50 2 1
01 2 1
8A 2 2 9A 3 2 AA 4 2 BA 4 3
CA 2 2 DA 3 2 EA 4 2 FA 4 3
36 3 1
37 3 1
32 4 1
33 4 1
69 6 2 79 6 3
49 2 1
59 2 1
66 6 2 76 6 3
46 2 1
56 2 1
10 2 1
82 2 2 92 3 2 A2 4 2 B2 4 3
C2 2 2 D2 3 2 E2 4 2 F2 4 3
97 3 2 A7 4 2 B7 4 3
D7 3 2 E7 4 2 F7 4 3
DD 4 2 ED 5 2 FD 5 3
80 2 2 90 3 2 AO 4 2 BO 4 3
CO 2 2 DO 3 2 EO 4 2 FO 4 3
83 4 3 93 5 2 A3 6 2 B3 6 3
16 2 1
17 2 1
6D 6 2 7D 6 3
4D 2 1
5D 2 1

-

The Condition Code Register notes are listed after table 16.

3-735

-

Boolean
Expression
M+ 1-M
A + l-A
B + 1 -B
M --'-A
M -B
M:M + 1 -D

Condition Codes
H
N Z V C

\

I

I

I

I

I 1
R
R
R

I

•

•••
•

•

I

R
R
R
R

AXB-D
00 - M-M
00 - A-A
00 - B-B
PC + 1 -PC
A +M-A
B + M-B
A -Stack
B -Stack
Stack -A
Stack-B

!

•~ •I •I
I

I

I

I

I

I
I

R
R

••••

••• ••• ••
•
•I •I •I
I

I

I
I

•••
•••
I

I
\
I

I

R
R
R

•
•

I
A - B-A
A - M - C-A
B - M - C-B
A-M
B-M
D -M:M + 1
A-M -A
B - M-B
D - M:M + 1 -D
A-B
B-A
M - 00
A - 00
B - 00

I
I

•

I j

": I I
I I t

t

I

t

I
I I

R
R
R
R
R

•

•
R
R
R

I

MC68120, MC68121

TABLE 15 - JUMP AND BRANCH INSTRUCTIONS

Direct
Operations

Mnemonic

OP -

Index

Extnd

# Op- # OP 2

Condo Code Reg.
5 4 3 2 1 0

Inheren

# OP

-1$1

Branch Test

Branch Always

BRA

Branch Never

BRN

21 3

2

None

Branch If Carry Clear

BCC

24 3

2

C=O

20 3

Branch If Carry Set

BCS

25 3

2

C= 1

BEQ

27 3

2

Z=1

Branch If :::: Zero

BGE

2C 3

2

N<±lV=O

> Zero

BGT

2E 3

2

Z+(N<±lV)=O

Branch If Higher

BHI

22 3

2

C+Z=O

Branch If Higher or Same

BHS
BLE

24 3 2
2F 3 2

BLO
BLS

25 3 2
23 3 2

Z + (N<±lV) = 1
C=1
C+Z-1
N(i)V = 1

Branch If < Zero
Branch If Carry Set
Branch If Lower Or Same

C =0

< Zero

BLT

2D 3

2

Branch If Minus

BMI

2B 3

2

N - 1

Branch If Not Equal Zero

BNE

26 3

2

Z=O

Branch If Overflow Clear

BVC

28 3

2

V=O

Branch If Overflow Set

BVS

29 3

2

V=1

Branch If

Branch If Plus

BPL

2A 3

2

Branch To Subroutine

BSR

80 6

2

Jump

JMP

Jump To Subroutine

JSR

No Operation

2

N=O

AD 6 2 BD 6 3

NOP

01 2

1

Return From Interrupt

RTI

3B 0

Return From Subroutine

RTS

39 5

~ } Soo Spec'"~
1 Operations-

n2

Software Interrupt

SWI

3F

Wait For Interrupt

WAI

3E 9

1

I

N Z

V C

&

} See Special
Operations Figure 36

6E 3 2 7E 3 3
90 5

H

••••••
••••••
••••••
••••••
••••••
••••••
•••• ••
••••••
• • • • ••
••••••
•• •• ••
•
••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
• II• • • • •
••••••
• ••••
• •••••

None

Branch If = Zero
Branch If

I

OP - #

Relative

, , ,, ,
S

Figure 36

TABLE 16 - CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS
Condo Code Reg.
4 3 2 1 0

Inherent
Mnemonic OP -

5
#

Boolean Operation

Clear Carry

CLC

OC 2

1

o -C

Clear Interrupt Mask

CLI

OE 2

1

0-1

Clear Overflow

CLV

OA 2

1

o -V

Set Carry

SEC

00 2

1

1 -C

Set Interrupt Mask

SEI

OF 2

1

1-1

Set Overflow

SEV

OB 2

1

1 -V

Accumulator A -CCR

TAP

06 2

1

A -CCR

TPA

07 2

1

CCR -A

Operations

CCR -Accumulator A
LEGEND
OPOperation Code (Hexadecimal)
- Number of MPU Cycles
MSp Contents of memory location pointed to by Stack Pointer
Number of Program Bytes
Arithmetic Plus
Arithmetic Minus
Boolean AND
Arithmetic Multiply
Boolean Inclusive OR
Boolean Exclusive OR
iiii Complement of M
- Transfer Into
OBit = Zero
00 Byte = Zero

#
+
•
X
+
<±l

CONDITION CODE SYMBOLS
H
I
N
Z
V
C
R
S

I

•

3-736

Half-carry from bit 3
Interrupt mask
Negative (sign bit)
Zero (byte)
Overflow, 2's complement
Carry/Borrow from MSB
Reset Always
Set Always
Affected
Not Affected

H

I

N

Z

V

C

•••••
• ••••
•••• •
•••••
• ••••
•I •I •I •I I •I
••••••
R

R

R

S

S

S

MC68120, MC68121

TABLE 17 - INSTRUCTION EXECUTION TIMES IN E CYCLES
ADDRESSING MODE

ADDRESSING MODE

!«I
'6
G)

E

ABA
ABX
ADC
ADD
ADDD
AND
ASL
ASLD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BHS
BIT
BLE
BLO
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BSR
BYC
BYS
CBA
CLC
CLI
CLR
CLY
CMP
COM
CPX
DAA
DEC
DES
DEX
EOR
INC
INS

.
u

f

1:1
G)

1:1

c::

!I(

1:1
G)
I(

Gl
1:1

C
G)
~

.s;

.E

i5

w

.=

.=

•
•

••

••

••

2
3

2

2
4
2

3
3
5
3

•• ••
•• ••
•• •
•• •••
•
•2 ••3
• •
• ••
••• ••
•••
•
••
•
•••
••2 3
• •5
•• ••
•• •
•3
2
•• ••
4

4
4
6
4
6

•
••
••
•
••
6

4

6

•
4
6
6

•6
••
6
•
4

•

4
4
6
4
6

••
•2

6

3
2

•
••
••
••
•
••
•
4

6

•
4
6
6

•
••
•
6

4
6

••
•
•••
••

!
tel
'6

G)

...>

Gl

E

«I

a;
a:

•••
••
••
••

INX
JMP
JSR
LOA
LOO
LOS
LOX
LSL
LSLO
LSR
LSRO
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEY
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI

3
3
3
3
3
3
3

•3
3
3
3
3
3
3
3
3
6
3
3

2
2
2
2
2

•2

•2
2
3
3

••
3

•••
•••
•••
••
•••
•

3-737

U
f

1:1
Gl
1:1

c::

!I(

1:1
Gl
I(

Gl
1:1

.E

i5

w

.=

•
••2

••
5

•3

•

3
3
3

•••
•••
•2
••
••
•
••
••
2
•
••
•
•••
2
••
••
•
•••
•
4

3
4
4
4

•••
•••
•
•••
••
••
••
3

3

•••
3
4
4
4
3
5

•
•••
••
••
•

6
4
5
5
5
6

•6

•
•6
•4
•
••
•6
6
••
•4
•
••
4
5
5
5
4
6

•
•••
•6
••
•

3
6
4
5
5
5
6

•6
•
•6
•
••
••
6
6
•
••
••
•
4

4

4
5
5
5
4
6

•
•••
•6
••
•

..
c::

f

Gl

.s;

.=
3

••
••
••
2

Gl

.~

«I

a;
a:

••

3
2
3
10
2
2

I

•

3
4
4
5
2
2
10
5
2

•

•2
2
2

•
•••
••
12
2
2
2
2
2
3
3
9

•

MC68120, MC68121

FIGURE 36 - SPECIAL OPERATIONS
JSR, Jump to Subroutine
PC
Direct

1-------1

{

RTNL...:.=-'::':':~=--.J

-+- sp~~ r n S t a C k

PC
INDXD
f--~-----"--=-=-'--~

{

SP- 1

RTNH

SP

RTNL

RTNL.:.="'::'::::::':""::=_

PC
~----.:......c.------1

EXTND

~=-':=~=-l

{

RTNL.:.=-'::':':~=--.J

I

BSR, Branch tf) Subroutine
SP

Stack

-+ SP- 21r - - - - - - ,
SP- 1 _

SP L-_.:..:.R.:..:.TN,,-,L~--.J

RTN L-_ _ _ _-'

RTS, Return from Subroutine

q

Subroutine

PC

~1_.;.:$3~9_=__R__
TS____---l1

RTNH

~:rnStack
SP+l

RTNH

---. SP + 2

RTNL

SWI, Software Interrupt
Main Program

----.JI

R::I,-_ _
$3_F_-_S_W_1

q

WAI, Wait for Interrupt

RTI, Return from Interrupt
Interrupt Program
PC

I

$3B-RTI

I

q

SP

Stack

---'SP-7
SP-6

Condition Code

SP-5

Acmltr B

SP-4

Acmltr A

SP-3

Index Register IXHI

SP-2

Index Register IXU

SP- 1

RTNH

SP

RTNL

SP

Stack

SP
SP+ 1
SP+2

Condition Code
Acmltr B

SP+3

Acmltr A

SP+4

Index Register IXHI

SP+5

Index Register IXL

SP+6

RTNH

---. SP+7

RTNL

JMP, Jump
Main Program
$6E= JMP
INDXD {

PC

X+ K

I
rl

K= Offset
Extended

{PC~-----:-:-C----1

-N-e-xt-In~s--tru-c--'-tio-n-'

K I Next Instructlon

LegendRTN

= Address

of next instruction

In

Main Program to be executed upon return from subroutine

RTN H = Most significant byte of Return Address

... = Stack

pointer after execution

K = 8-bit unsigned value

RTNL = Least significant byte of Return Address

3·738

I

MC68120, MC68121

CYCLE-BY-CYCLE OPERATION SUMMARY
Note that during MPU reads of internal locations, the
resultant value will not appear on the external Data Bus except in Mode O. "High order" byte refers to the most significant byte of a 16-bit value.
The coding of the first (or only) byte corresponding to an
executable instruction is sufficient to identify the instruction
and the addressing mode. The hexadecimal equivalents of
the binary codes, which result from the translation of the 82
instructions in all valid modes of addressing, are shown in
Table 19. There are 220 valid machine codes, 34 unassigned
codes and 2 reserved for test purposes.

Table 18 provides a detailed description of the information
present on the Address Bus, Data Bus, and the R/W line
during cycle of each instructions.
The information is useful in comparing actual with expected results during debug of both software and hardware
as the program is executed. The information is categorized in
groups according to addressing mode and number of cycles
per instruction. In general, instructions with the same addressing mode and number of cycles execute in the same
manner. Exceptions are indicated in the table.

TABLE '8 -

Address Mode &
Instructions

Address Bus

IMMEDIATE
ADC EOR
ADD LDA
AND ORA
BIT SBC
CMP SUB

2

LDS
LDX
LDD

3

CPX
SUBD
ADDD

4

,
2

,
,
2

3

2

3
4

DIRECT
ADC EOR
ADD LDA
AND ORA
BIT SBC
CMP SUB

3

STA

3

,
2

3

,
,
2

3
LDS
LDX
LDD

4

STS
STX
STD

4

2

3

,

4

2

3
4

CPX
SUBD
ADDD

5

1
2

3
4

,
5

JSR

CYCLE BY CYCLE OPERATION (Sheet' of 5)

5

2

3
4
5

Op Code Address
Op Code Address + ,

Op Code Address
Op Code Address + ,
Op Code Address + 2
Op Code Address
Op Code Address + ,
Op Code Address + 2
Address Bus FFFF
Op Code Address
Op Code Address + ,
Address of Operand

Op Code Address
Op Code Address + ,
Destination Address
Op Code Address
Op Code Address + ,
Address of Operand
Operand Address + ,
Op Code Address
Op Code Address ... ,
Address of Operand
Address of Operand + 1
Op Code Address
Op Code Address + ,
Operand Address
Operand Address + ,
Address Bus FFFF
Op Code Address
Op Code Address + ,
Subroutine Address
Stack Pointer
Stack Pointer + ,

R/W
Line

,,

,,
,
,,
,,
,,
,
,,
,,
,,
,
,,
,,
,,
,

0

1

0
0

1

0
0

Data Bus

Op Code
Operand Data

Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code
Address of Operand
Operand Data

Op Code
Destination Address
Data from Accumulator
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)

-

3-739

Continued -

I

MC68120, MC68121

TABLE 18 -

CYCLE BY CYCLE OPERATION (Sheet 2 of 5)

Address Mode &
Instructions

R/W
Line

Data Bus

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)

3

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

4

Address of Operand

1

Op Code
Address of Operand
Address of Operand
(Low Order Byte)
Operand Data

1
2

Op Code Address
Op Code Address + 1

1
1

3

Op Code Address + 2

1

4

Operand Destination Address

0

1
2

Op Code Address
Op Code Address + 1

1
1

Address Bus

EXTENDED
JMP

3

1
2

3
ADC EOR
ADD LOA
AND ORA

4

BIT SBC
CMP SUB
STA

I

LOS
LOX

4

5

LOD

STS
STX

5

1
2

3

Op Code Address + 2

1

4
5

Address of Operand
Address of Operand + 1

1
1

1
2

Op Code Address
Op Code Address + 1

1
1

3

Op Code Address + 2

1

4
5

Address of Operand
Address of Operand + 1

0
0

1

2

Op Code Address
Op Code Address + 1

1
1

CLR ROL

3

Op Code Address + 2

1

COM ROR
DEC TST
INC

4
5

6

Address of Operand
Address Bus FFFF
Address of Operand

0

1
2

Op Code Address
Op Code Address + 1

1
1

3

Op code Address + 2

1

4
5

6

Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1

1
2

Op Code Address
Op Code Address + 1

1
1

STD

ASL LSR
ASR NEG

CPX
SUBD

6

6

ADDO

JSR

6

1
1

3

Op Code Address + 2

1

4
5

Subroutine Starting Address
Stack Pointer

0

6

Stack Pointer - 1

0

1

Op Code
Destination Address
(High Order Byte)
Destination Address
(Low Order Byte)
Data from Accumulator
Op Code
Address of Operand
(High Order Byte)
Address of Operand
(Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code
Address of Operand
(High Order Byte)
Address of Operand
(Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code
Address of Operand
(High Order Byte)
Address of Operand
(Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code
Operand Address
(High Order Byte)
Operand Address
(Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)
Op Code of Next Instruction
Return Address
(Low Order Byte)
Return Address
High Order Byte)

-

3-740

Continued -

MC68120, MC68121

TABLE 18 Address Mode &.
Instructions

CYCLE BY CYCLE OPERATION (Sheet 3 of 5)

Address Bus

R/W
Line

Data Bus

INDEXED
JMP

3

1

2

3
ADC EOR
ADD LDA
AND ORA
BIT SBC
CMP SUB

4

STA

4

1

2
3
4
1

2

3
4
LDS
LDX
LDD

5

STS
STX
STD

5

1

2

3
4
5
1
2

3
4
5

ASL LSR
ASR NEG
CLR ROL
COM ROR
DEC TST (1)
INC

6

CPX
SUBD
ADDD

6

JSR

6

1

2

3
4
5
6
1

2

3
4
5
6
1

2
3
4
5
6

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Offset
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset

1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset

1
1
1

0

Op Code
Offset
Low Byte of Restart Vector
Operand Data

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Op Code Address
Op Code Address + 1
Address- Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset

0
0
1
1
1
1
1

0

Op Code
Offset
Low Byte of Restart Vector
'Current Operand Data
Low Byte of Restart Vector
New Operand Data

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Index Register + Offset + 1
Address Bus FFFF

1
1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Stack Pointer
Stack Pointer - 1

1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)

0
0

-

3-741

Continued -

I

MC68120, MC68121

TABLE.18 -

CYCLE BY CYCLE OPERATION (Sheet 4 of 5)

Address Mode &
Instructions

Address Bus

R/W
Line

Data Bus

INHERENT

I

ABA DAA SEC
ASL DEC SEI
ASR INC SEV
CBA LSR TAB
CLC NEG TAP
CLI NOP TBA
CLR ROL TPA
CLV ROR TST
COM SBA

2

1
2

Op Code Address
Op Code Address + 1

1
1

Op Code
Op Code of Next Instruction

ABX

3

1
2
3

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Irrelevent Data
Low Byte of Restart Vector

ASLD
LSRD

3

1
2
3

Op Code Address
Op Code Address +1
Address Bus FFFF

1
1
1

Op Code
Irrelevant Data
Low Byte of Restart Vector

DES
INS

3

1
2
3

Op Code Address
Op Code Address +1
Previous Register Contents

1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data

INX
DEX

3

1
2
3

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Op Code of Next Instruction
Low Byte of Restart Vector

PSHA
PSHB

3

1
2
3

Op Code Address
Op Code Address +1
Stack Pointer

1
1

0

Op Code
Op Code of Next Instruction
Accumulator Data

TSX

3

1
2
3

Op Code Address
Op Code Address + 1
Stack Pointer

1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data

TXS

3

1
2

Op Code Address
Op Code Address +1
Address Bus FFFF

1
1
1

Op Code
Op Code of Next Instruction
Low Byte of Restart Vector

PULA
PULB

4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer +1

1
1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data
Operand Data from Stack

PSHX

4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer -1

1
1

0
0

Op Code
Irrelevant Data
Index Register (Low Order Byte)
Index Register (High Order Byte)

4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer +1
Stack Pointer +2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer +1

1
1
1
1
1
1
1
1
1

5

Stack Pointer +2

1

1
2

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer -1

0
0

Stack
Stack
Stack
Stack
Stack

0
0
0
0
0

3
1
2
3

4
1
2

3
4
PULX

5

1
2
3

4
RTS

WAI

5

9

5
1
2
3

3
4
5
6
7
8

9

Pointer
Pointer
Pointer
Pointer
Pointer

-2
-3
-4
-5
-6

1
1

Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)
Op Code
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(High Order Byte)
Address of Next Instruction
(Low Order Byte)
Op Code
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address
(High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
-

3-742

Continued -

MC68120, MC68121

TABLE 18 Address Mode &
Instructions

CYCLE BY CYCLE OPERATION (Sheet 5 of 5)

Address Bus

R/W
Line

Data Bus

INHERENT
10

MUL

10

Op Code Address
Op Code Address +1
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF

1
1
1
1
1
1
1
1
1
1

Op Code
Irrelevant Data
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart

1
2
3
4

Op Code Address
Op Code Address +1
Stack Pointer
Stack Pointer +1

1
1
1
1

5

Stack Pointer +2

1

6

Stack Pointer +3

1

Op Code
Irrelevant Data
Irrelevant Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (High Order Byte)
Next Instruction Address from
Stack (Low Order Byte)

1
2
3
4
5
6
7

8
9
10

RTI

12

SWI

7

Stack Pointer +4

1

8

Stack Pointer +5

1

9

Stack Pointer +6

1

10

Stack Pointer +7

1

1
2
3
4

Op Code Address
Op Code Address +1
Stack Pointer
Stack Pointer -1

1
1
0
0

5
6
7

10
11

Stack Pointer -2
Stack Pointer -3
Stack Pointer -4
Stack Pointer -5
Stack Pointer -6
Stack Pointer -7
Vector Address FFFA (Hex)

0
0
0
0
0
1
1

12

Vector Address FFFB (Hex)

1

8
9

Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector

Op Code
Irrelevant Data
Return Address (Low Order Byte)
Return Address
(High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)

RELATIVE
BCC
BCS
BEQ
BGE
BGT
BSR

BHT BNE BLO
BLE BPL BHS
BLS BRA BRN
BLT BVC
BMT BVS

3

1
2
3

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Branch Offset
Low Byte of Restart Vector

6

1
2
3
4
5
6

Op Code Address
Op Code Address +1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer -1

1
1
1
1
0
0

Op Code
Branch Offset
Low Byte of Restart Vector
Op Code of Next Instruction
Return Address (Low Order Byte)
ReturnAddress(High Order Byte)

3-743

I

MC68120, MC68121

OP
00

MNEM

MODE

-"

01
02
03

NOP

INHER

2

04

LSRD
ASLD
TAP
TPA
INX
DEX
CLV
SEV
CLC
SEC
Cli
SEI
SBA
CBA

Oh

06
07

DB
D9
OA
DB

DC

00

I

DE
OF
10
11
12
13
14
15
16
17
18
19
1A
18
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33

3
3
2
2
3
3
2
2
2
2
2
2
2
2

TAB
TBA

1

1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2

1
1

DAA

INHER

2

1

ABA

INHER

2

1

BRA
BRN
BHI
BLS
BCC
BCS
BNE
BEa
BVC
BVS
BPL
BMI
BGE
BLT
BGT
BLE
TSX
INS
PULA
PULB

REL

REL
INI:iER

~

INHFR

3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1

TABLE 19 - CPU INSTRUCTION MAP
OP
34
35
36
37
3B
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
SF
60
61
62
63
64
65
66
67

MNEM

MODE

DES
TXS
PSHA
PSHB
PULX
RTS
ABX
Rli
P$HX
MUL
WAI
SWI
NEGA

INHER

-"
3
3
3
3
5
5
3
10
4
10
9
12
2

1
1
1
1
1
1
1
1
1
1
1
1
1

COMA
LSRA

2
2

1
1

RORA
ASRA
ASLA'
ROLA
DECA

2
2
2
2
2

1
1
1
1
1

INCA
TSTA
T
CLRA
NEGB

2
2

1
I

2
2

I
1

COMB
LSRB

2

2

I
1

RORB
ASRB
ASLB
ROLB
DECB

2
2
2
2
2

1
I
1
1
I

INCB
TSTB
T
CLRB
NEG

2
2

I
1

2

I
2

COM
LSR
ROR
ASR

INHER
INDXD

6

1
6
6

2
2

6
INOXO 6

2
2

OP

MNEM

MODE

68
69
6A
6B
6C
6D
6E
6F
70
71

ASL
ROL
DEC

INDXD

-"
6
6
6

2
2
2

6
6
3
6
6

2
2
2
2
3

COM
LSR

6
6

3
3

ROR
ASR
ASL
ROL
DEC

6
6
6
6
6

3
3
3
3
3

INC
TST
JMP
CLR

6
6
3
6
2
2
2

3
3
3
3
2
2
2
3
2
2
2

INC
TST
JMP
CLR
NEG

1

INDXD
EXTND

72
73
74
75
76

77
7B
79
7A
7B
7C
7D
7E
7F
80
81
82
83
B4
B5
86
87
B8
89
8A
BB
BC
8D
BE
8F

90
91
92
93
~4

95
96
97
98
99
9A
9B

SUBA

CMPA
SBCA
SUBD
ANDA
BITA
LDAA
EORA
ADCA
DRAA
ADOA
CPX
BSR
LQS
SUBA
CMPA
SBCA
SUBD
ANDA
BI~A

LDAA
STAA
EORA
ADCA
DRAA
ADDA

EXTNO
tMMED

.

I
I
2
2
2

2
2
2
2

.

2
2
2
2
3
2
3

3
3
3
5
3
3
3
3
3
3
3
3

2
2
2
2
2
2
2
2
2
2
2
2

IMMEO
REL
6
IMMED 3
DIR

OIR

NOTES,
1, Addressing Mades
IMMED ... lmmediate
INHER _Inherent INDXD -Indexed
REL. Relative
EXTN D., Extended
DI R ., Direct
2, Unassigned opcodes are indicated by"'" and should not be executed,
3. Codes marked by "T" force the PC to function as a 16-bit counter.

3·744

OP

MNEM

MODE

9C
9D
9E
9F
40
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
BI
B2
B3
B4
B5
B6
B7
BB
B9
BA
BB
BC
BD
BE
BF
CO
CI
C2
C3
C.
(5

CPX
JSR
LDS
STS
SUBA
CMPA
SBCA
SUBD
ANd'A
BITA
LOAA
STAA
EORA
ADCA
DRAA
ADDA
CPX
JSR
LDS
STS
SUBA
CMPA
SBCA
SUBD

DIR

C6
C7
CB
C9
CA
CB
CC
(D
CE
CF

!

INDXD

INOXO
EXTND

ANDA

BITA
LDAA
STAA
EORA
ADCA
DRAA
ADDA
CPX
JSR
LDS
STS
SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDAB

5
5
4
4
4
4
4
6
4
4
4
4
4
4
4
4
6
6
5
5
4
4
4
6

·
··
4

4
4
4
4

,
EXTNO
IMMED

6
6
5
5
2
2
2

·
2
2

2

2

EORB
ADCB
DRAB
ADDB
LOD
LDX

-"

3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
3
2
2
2

3

2
2
2
2
3

3

3

2
2

2

IMMED

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

OP
DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
EO
EI
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
'3
F.
F5
F6
F7
FB
F9
FA
FB
FC
FD
FE
FF

MNEM

MODE -

SUBB
CMPB

DIR

slICB
ADDD
ANDB
BITB
LOAB
STAB
EORB
ADCB
DRAB
ADDB
LDD
STD
LDX
STX
SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDAB
STAB
EORB
ADCB
DRAB
ADDB
LDD
STD
LDX
STX
SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LOAB
STAB
EORB
ADeB
DRAB
AD DB
LDD
STD
LOX
STX

~
OIR
INDXO

3
3
3
5
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
6
4
4
4
4

··
·
4

~
INOXO
EXTND

5
5
5
5

··
··
·
4
6
4
4

4

4

EXTNO

'UNDEFINED OP (ODE

4
5
5
5
5

"

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3

3
3
:J
3
3
3
3
3
3
3

MC68120, MC68121

APPENDIX A
MC68120 CUSTOM ORDERING INFORMATION
MC2708s must be clearly marked to indicate which PROM
corresponds to which address space ($F800-$FBFF; $FCOO$FFFF). See Figure A-2 for recommended marking procedure.

A.O
Address $FFEF is Reserved for the Checksum value for the
ROM, to be generated at the factory.

A.1 CUSTOM MC68120 ORDERING INFORMATION
The custom M C68120 specifications may be transmitted to
Motorola in any of the following media:
A) EPROM(s)
B) MDOS diskette
The specification should be formatted and packaged, as
indicated in the appropriate paragraph below, and mailed
prepaid and insured with a cover letter (see Figure A-1) to:

FIGURE A-2

~
~

Motorola Inc.
MPU Marketing
3501 Ed Bluestein Blvd.
Austin, Texas 78721
A copy of the cover letter should also be mailed separately.

xxx = Customer

PrLl.
~
10

After the EPROM(s) are marked, they should be placed in
conductive IC carriers and securely packed. Do not use
styrofoam.

A.2 EPROMs
A.3 MOOS DISKETTE

MCM2708 and MCM2716 type EPROMs, programmed
with the custom program (positive logic notation for address
and data), may be submitted for pattern generation. The

The file name and start/ end location Should be written on
the label.

FIGURE A-l
CUSTOMERNAME _______________________________________________________
ADDRESS _____________________________________________________________
ST A TE _________________________ CITY ___________________ ZIP _________
PHONE __________________________ EXTENSION ______________________

CONTACT MS/MR
CUSTOMERPART# _________________________________________

PATTERN MEDIA
02708 EPROM
02716 EPROM
o Diskette (MOOS)

TEMPERATURE RANGE
00° to 70°C

MARKING
o Standard
o Special

PACKAGE TYPE
o Ceramic

(Note 1) __________________________________________________________
NOTE: (1) Other Media Require Prior Factory Approval
SIGNATURE _____________________________________________________
TITLE ____________________________________________________________

3-745

I

®

MOTOROLA

MC68701

Advance Information
MOS
(N-CHANNEL, SILICON-GATE,
DEPLETION LOAD)

MICROCOMPUTER WITH EPROM
MC68701 MICROCOMPUTER UNIT (MCU)

I

The MC68701 is an 8-bit single chip microcomputer unit (MCU) which
significantly enhances the capabilities of the M6800 family of parts. It
can be used in production systems to allow for easy firmware changes
with minimum delay or it can be used to emulate the MC6801 103 for
software development. It includes an upgraded M6800 microprocessor
unit (MPU) with upward source and object code compatibility. Execution times of key instructions have been improved and several new instructions have been added including an unsigned multiply. The MCU
can function as a monolithic microcomputer or can be expanded to a
64K byte address space. It is TTL compatible and requires one + 5 volt
power supply for nonprogramming operation. An additional Vpp power
supply is needed for EPROM programming. On-chip resources include
2048 bytes of EPROM, 128 bytes of RAM, Serial Communications Interface (SCI), parallel 1/0, and a three function Programmable Timer. A
summary of MCU features includes:
•
•
•
•
•
•
•
•
•
•
•
•

Enhanced MC6800 Instruction Set
8 x 8 Multiply In.struction
Serial Communications Interface (SCI)
Upward Source and Object Code Compatibility with the MC6800
16-Bit Three-Function Programmable Timer
Single-Chip or Expanded Operation to 64K Byte Address Space
Bus Compatibility with the M6800 Family
2048 Bytes of UV Erasable, User Programmable ROM (EPROM)
128 Bytes of RAM (64 Bytes Retainable on Powerdown)
29 Parallel 1/0 and Two Handshake Control Lines
Internal Clock Generator with Divide-by-Four Output
- 40 to 85°C Temperature Range

~

L SUFFIX

CERAMIC PACKAGE
CASE 715

PIN ASSIGNMENT

Vss
SCl

XTALl
EXTAL2
NMI

SC2
P30

4

IRQl

P31

RESETIVpp

P32

Vee

7

P33

P20

P34

P21

GENERIC INFORMATION

Package Type
Ceramic
L Suffix

Frequency (MHz)

Temperature

1.0
1.0
1.25
1.25
1.5
2.0

O°C to 70°C
-40°C to 85°C
O°C to 70°C
-40°C to 85°C
O°C to 70°C
O°C to 70°C

Generic Number
MC68701 L
MC68701CL
MC68701L-l
MC68701CL-l
MC68A701L
MC68B701 L

This document contains information on a new product. Specifications and information herein
are subject to change without notice

3·746

P35

P22

10

P23

11

31

P36
P37

P24

12

P40

Pl0

13

P41

Pll

14

P42

P12

15

P43

P13

16

P44

P14

17

P45

P15

18

P46

P16

19

P47

P17

20

Vee

Standby

MC68701

MC68701 MICROCOMPUTER BLOCK DIAGRAM

.......----4>-+-+-.. P20
.....+-_---+-+-.. P21

P30

P31
P32
P33
P34
P35

.....+--hr--+-.. P22
.....+-H-.--.P23

.....+-+-I-+~.. P24

P36

P37
SC2
SCl

I

P40

P41
P42
P43
P44

~----.Pl0

P45
P46
P47

.....------'~Pll

.....- - - - . P 1 2
.....- - - - . P 1 3
.....- - - - . P 1 4

.....- - - - . P 1 7

MAXIMUM RATINGS
Rating
Supply Voltage

Symbol

Value

Unit

VCC

-0.3 to + 7.0

V
V

Yin

-0.3 to + 7.0

Operating Temperature Range
MC68701
MC68701C

TA

TL to TH
o to 70
-40 to 85

°C

Storage Temperature Range

Tstg

o to 85

°C

Input Voltage

THERMAL CHARACTERISTICS
Characteristic

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation it is recommended that Yin and V out be constrained to the range VSS ~ (Yin or Vout) ~ VCe.
Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level
(e.g., either VSS or VCC).

Thermal Resistance
Ceramic Package

POWER CONSIDERATIONS
The average chip-junction temperature, T J, in °c can be obtained from:
TJ=TA+(PD e8JA)

(1)

Where:
T A = Ambient Temperature, °c
8JA = Package Thermal Resistance, Junction-to-Ambient, °C/W
PD= PINT+ PPORT
PINT= ICC x VCC, Watts - Chip Internal Power
PPORT= Port Power Dissipation, Watts - User Determined
For most applications PPORT0

01

'"

,

Port 3Data
Address/

74LS373
ITYPlcal)

) Add"" ADA,

-"

D8

08
--"

) 0",
--"
--'"

ODD,

I

MC68701

FIGURE 14 - MODE PROGRAMMING TIMING

See Figure 16

~ VMPDD

for Diode Arrangement

VMPH Min

Mode Inputs
(P20, P21, P22)

:?"p:;':':

(P20, P21, P22)
____ ...,"

mET

VMPL
Mode Latch
Leve)

VMPL Max

MODE PROGRAMMING (Refer to Figure 14)
Characteristic
Mode Programming Input Voltage Low
Mode Programming Input Voltage High
Mode Programming Diode Differential

I

Symbol

Min

Typ

VMPL
VMPH

-

-

4.0
0.6

VMPDD
PWRSTL
tMPS

RESET Low Pulse Width
Mode Programming Set-Up Time
Mode Programming Hold Time
RESET Rise Time~ 1 I's
RESET Rise Time< 1 I's

tMPH

Max
1.8

Unit

-

-

3.0
2.0

-

-

V
V
E-Cycles
E-Cycles

0
100

-

-

-

V

ns

FIGURE 15 - TYPICAL MODE PROGRAMMING CIRCUIT
VCC

o
r-t?~>

S <> 
"

D
6

RESETIVpp

Vpp~

"Program"

Notes:
1. Mode 0 as shown (switches closed).
2. R1 = 10k ohms (typical).
3. The RES ET time constant is equal to RC where R is the equivalent parallel resistance of R2 and the number of resistors (R 1)
placed in the circuit by closed mode control switches.
4. D= 1N914, 1N4001 (typical).
5. If V = VCC, then R2= 50 ohms (typical) to meet VIH for the RESETIVpp pin. V= VCC is also compatible with MC6801. The
RESET time constant in this case is approximately R2*C.
____
6. Switch S1 allows selection of normal (RESET) or programming (Vpp) as the input to the RESETIVpp pin. During switching, the input level is held at a value determined by a diode (0), resistor (R2) and input voltage (VI.
7. While S1 is in the "Program" position, RESET should not be asserted.
8. From powerup, RESET must be held low for at least tRC. The capacitor, C, is shown for conceptual purposes only and is
on the order of 1000 JLF for the circuit shown. Typically, a buffer with an RC input will be used to drive RESET, eliminating
. the need for the larger capacitor.
9. Diode Vf should not exceed VMPDD min.

3-756

3:

FIGURE 16 -

oen

MC68701 MEMORY MAPS

CO

MC68701
Mode

o

MC68701
Mode

lc'uuu,(U{'I(

External Memory Space

External Memory Space
S0080
Internal RAM

......

$BFFO
$9 FFF

I
f--.

~
----{(..J(

External Memory Space

Internal RAM

Internal RAM
SOOFF I/Z'l"J///U'l4'

External Memory Space

SF800

InnJuun;K'

Inn;»))));;(

Internal EPROM
SFFEF
Internal EPROM

$FFFF '21

I

External Interrupt Vectors
External Memory Space

SF800

Internal Registers
SOOl F

S0080 b77777777/7J::

SOOF F V///////J'/ /ry

External Memory Space

~

U'I

b>77>7)7J7}A

ICU(((((U('K

(,.)

2

Multiplexed/RAM

Internal Registers
S001 F ruuuuu't'

S0080 In))/Ju??>;/(

SOOFF

MC68701
Mode

SOOOO"'~rT'7'7>-.

$OOOO'''~~

i/)nn)>JJ}Jt,.

Internal Registers
S001 F

1

Multiplexed/RAM & EPROM

Multiplexed Test mode
SOOOO'1l

.....
o....

[///.(t'l'Zt:««V

Notes'
1) Excludes the following addresses which may
be used externally: $04, $05, S06, S07 and SOF
2) There must be no overlapping of internal and
external memory spaces to avoid driving the
data bus with more than one device,

SFFFO

I<'C(U

~U(u'1(

External Interrupt Vectors

SFFFF

Notes
1) Excludes the followmg addresses which may
be used externally S04. S05, S06, S07 and
SOF
21 Internal EPROM addresses $FFFO to $FFFF are
not usable

SFFFO
SFFFF

!

I> External Interrupt Vectors

Notes
1) Excludes the followmg addresses which may
be used externally $04. S05, S06, S07, and
SOF

3) This mode is used to program the onboard
EPROM.

II

•
FIGURE 16 -

3:

(")

MC68701 MEMORY MAPS (CONTINUED)

Q)

CO
~

MC68701
Mode

3

Multiplexed/No RAM or EPROM
$()()(X)(1 )" uun'"''''

MC68701
Mode

4

Single Chip Test

5

Non-Multiplexed/ Partial Decode
Internal Registers l5 )

Internal Registers

MC68701
Mode

SOOOO{ 1)rT77'"""TT7"77~~

~~ Internal Registers

S001 F""~:"':":''"4-''-<..L''''-~

;~:~:::, :::"y S, ~

SOl FF
Unusable{11(4)

External Memory Space

I

U)

Unusable

.!.J

0'1

to

Internal EPROM
SFFFO ~I- - - - - i
External Interrupt Vectors
SFFFFI

V

Notes:
1) Excludes the follOWing addresses which may be
used externally: $04, $05, S06, S07 and SOF

SXX80~ Internal
SXXFF

RAM
Internal Interrupt Vectors

1%///////////1) Internal Interrupt Vectors

Notes:

Notes

1) The internal EPROM is disabled.

1) Excludes the following addresses which may NOT
be used externally: $04, $06, and $OF (No lOS).

2) Mode 4 may be changed to Mode 5 without having to assert RESET by writing a "1" Into the
PCO bit of Port 2 Data Register
3) Addresses A8 to A 15 are treated as "don't
cares" to decode internal RAM
4) Internal RAM will appear at SXX80 to SXXFF
5) MCU read of the Port 3 Data Direction Register
will access the Port 3 Data Register.

2) This mode may be entered without going
through RESET by using Mode 4 and subsequently writing a "1" into the PCO bit of Port 2
Data Register.
3) Address lines AO to A 7 will not contain addresses
until the Data Direction Register for Port 4 has
been written with ''1's'' in the appropriate bits.
These address lines will assert ''1's'' until made
outputs by writing the Data Direction Register.

o
""'"

MC68701

FIGURE 16 -

MC68701
Mode

MC68701 MEMORY MAPS (CONCLUDED)

6

MC68701
Mode

7

~

Multiplexed/Partial Decode

SOOOO~

Internal Registers

Internal Registers( 1)

SOOl F "'-~0LLjr='0L.L0~

SOOl F jU":.LL..UL..40 k

>30 k

>20 k

>20 k

>20 k

Q

* Note:

These are representative AT-cut crystal parameters only Crystals of other types of
cuts may also be used

1.1
CL

= 20 pF

(tYPical)

Ll

NOTE
TTL-compatible oscillators may be
obtained from

C,

RS

3

Motorola Component Products
Attn: Data Clock Sales
2553 N. Edginton SI.
Franklin Park, IL 60131
Tel 312-451-1000
Telex: 433-0067

Co
Equivalent Circuit
(b) Oscillator Stabilization Time (tRC)

vcc

~~4-7-5-V----------~fJ?r--------------------------------

==---+--------:jl
f

-----------------+t----------~f
------=-....,
loIo(l'-----tRc

Oscillator
StabilizatIOn

Time. tRC

3·763

I

MC68701

SC1 And SC2 In Expanded Non-Multiplexed Mode
In the Expanded Non-Multiplexed Mode, both SCl and
SC2 are configured as outputs. SCl functions as Input/Output Select (lOS) and is asserted only when $0100 through
$01 FF is sensed on the internal address bus.
SC2 is configured as Read/Write and is used to control
the direction of data bus transfers. An MPU read is enabled
when Read/Write and E are high.

I

SC1 And SC21n Expanded Multiplexed Mode
In the Expanded Multiplexed Modes, both SCl and SC2
are configured as outputs. SCl functions as Address Strobe
and can be used to demultiplex the eight least significant addresses and the data bus. A latch controlled by Address
Strobe captures address on the negative edge, as shown in
Figure 15.
SC2 is configured as Read/Write and is used to control
the direction of data bus transfers. An MPU read is enabled
when Read/Write and E are high.
P10-P17 (PORT 1)
Port 1 is a mode independent 8-bit I/O port with each line
an input or output as defined by the Port 1 Data Direction
Register. The TTL compatible three-state output buffers can
drive one Schottky TTL load and 30 pF, Darlington transistors, or CMOS devices using external pullup resistors. It is
configured as a data input port by RESET. Unused lines can
remain unconnected.
P20-P24 (PORT 2)
Port 2 is a mode-independent, 5-bit. multipurpose I/O
port. The voltage levels present on P20, P21, and P22 on the
rising edge of RESET determine the operating mode of the
MCU. The entire port is then configured as a data input port.
The Port 2 lines can be selectively configured as data output
lines by setting the appropriate bits in the Port 2 Data Direction Register. The Port 2 Data Register is used to move data
through the port. However, if P2l is configured as an output, it will be tied to the timer Output Compare function and
cannot be used to provide output from the Port 2 Data
Register.
Port 2 can also be used to provide an interface for the
Serial Communications Interface and the timer Input Edge
function. These configurations are described in the appropriate SCI and Timer sections of this publication.
The Port 2 high-impedance, TTL compatible output buffers are capable of driving one Schottky TTL load and 30 pF
or CMOS devices using external pullup resistors.
PORT 2 DATA REGISTER

7

I

6

PC21 PCl

5

I I
PCO

4

3

2

P241 P231 P221 P21

o

I I
P20

$0003

P30-P37 (PORT 3)
Port 3 can be configured as an I/O port, a bidirectional
8-bit data bus, or a multiplexed address/ data bus depending
on the operating mode. The TTL compatible three-state output buffers can drive one Schottky TTL load and 90 pF.
Unused lines can remain unconnected.

Port 3 In Single-Chip Mode
Port 3 is an 8-bit I/O port in the Single-Chip Mode, with
each line configured by the Port 3 Data Direction Register.
There are also two lines, IS3 and OS3, which can be used to
control Port 3 data transfers.
Three Port 3 options are controlled by the Port 3 Control
and Status Register and are available only in Single-Chip
Mode: (1) Port 3 input data can be latched using IS3 as a
control signal, (2) OS3 can be generated by either an MPU
read or write to the Port 3 Data Register, and (3) an IRQl interrupt can be enabled by an IS3 negative edge. Port 3 latch
timing is shown in Figure 4.
PORT 3 CONTROL AND STATUS REGISTER

7

6

5

4

3

2

IS3
Flag

IS3
IRQl
Enable

X

OSS

Latch
Enable

X

Bit 0-2
Bit 3

Bit 4

Bit 5
Bit 6

Bit 7

o
X

X

$oooF

Not used.
LATCH ENABLE. This bit controls the
input latch for Port 3. If set. input data
is latched by an IS3 negative edge. The
latch is transparent after a read of Port
3 Data Register. LATCH ENABLE is
cleared during reset.
OSS (Output Strobe Selectl. This bit
determines whether OS3 will be
generated by a read or write of the Port
3 Data Register. When clear, the
strobe is generated by a read; when
set, it is generated by a write. OSS is
cleared during reset.
Not used.
IS3 IRQl ENABLE. When set, an IRQl
interrupt will be enabled whenever IS3
FLAG is set; when clear, the interrupt
is inhibited. This bit is cleared during
reset.
IS3 FLAG. This read-only status bit is
set by an IS3 negative edge. It is
cleared by a read of the Port 3 Control
and Status Register (with IS3 FLAG
set) followed by a read or write to the
Port 3 Data Register or during reset.

Port 3 In Expanded Non-Multiplexed Mode
Port 3 is configured as a bidirectional data bus (o7-DOl in
the Expanded Non-Multiplexed Mode. The direction of data
transfers is controlled by Read/Write (SC2l. Data is clocked
by E (Enablel.
Port 3 In Expanded Multiplexed Mode
Port 3 is configured as a time multiplexed address (AO-A7)
and data bus (07-DOl in the Expanded Multiplexed Modes
where Address Strobe (AS) can be used to demultiplex the
two buses. Port 3 is held in a high impedance state between
valid address and data to prevent potentional bus conflicts.

3-764

MC68701

MC68701 RAM/EPROM CONTROL REGISTER

P40-P47 (PORT 4)
Port 4 is configured as an 8-blt I/O port, as address outputs, or as data inputs depending on the operating mode.
Port 4 can drive one Schottky TTL load and 90 pF and is the
only port with internal pullup resistors. Unused lines can remain unconnected.

7

6

Bit 0
Port 4 In Single Chip Mode
In Single Chip Mode, Port 4 functions as an 8-bit I/O port
with each line configured by the Port 4 Data Direction
Register. Internal pullup resistors allow the port to directly interface with CMOS at 5 volt levels. External pullup resistors
to more than 5 volts, however, cannot be used.
Port 4 In Expanded Non-Multiplexed Mode
Port 4 is configured during reset as an 8-bit input port,
where the Port 4 Data Direction Register can be written to
provide any or all of eight address lines AO to A7. Internal
pullup resistors pull the lines high until the Port 4 Data Direction Register is configured.

x

x

1

0

PPC

I I
PLC

$14

PLC. Programming Latch Control.
This bit controls (a) a latch which captures the EPROM address to be programmed and (b) whether the PPC bit
can be cleared. The latch is triggered
by an MPU write to a location in the
EPROM. This bit is set during reset
and can be cleared only in Mode O. The
PLC bit is defined as follows:
PLC = 0 EPROM address latch
enabled; EPROM address is latched
during MPU writes to the EPROM.
PLC= 1 EPROM address latch is
transparent.

Bit 1

Port 4 In Expanded Multiplexed Mode
In all Expanded Multiplexed modes except Mode 6, Port 4
functions as half of the address bus and provides A8 to A 15.
In Mode 6, the port is configured during reset as an 8-bit
parallel input port, where the Port 4 Data Direction Register
can be written to provide any or all of upper address lines A8
to A 15. Internal pullup resistors pull the lines high until the
Port 4 Data Direction Register is configured, where bit 0 controls A8.

RESIDENT MEMORY
The MC68701 has 128 bytes of onboard RAM and 2048
bytes of on board UV erasable EPROM. This memory is controlled by four bits in the RAM/EPROM Control Register.
One half of the RAM is powered through the VCC standby
pin and is maintainable during VCC powerdown. This standby portion of the RAM consists of 64 bytes located from $80
through $BF.
Power must be supplied to VCC standby if the internal
RAM is to be used, regardless of whether standby power
operation is anticipated. In Mode 3, VCC standby should be
tied to ground.
The RAM is controlled by the RAM/ EPROM Control
Register.

Bit 2-5
Bit 6 RAME

Bit 7 STBY PWR

RAM/EPROM CONTROL REGISTER ($14)
The RAM/EPROM Control Register includes four bits:
STBY PWR, RAME, PPC, and PLC. Two of these bits,
STBY PWR and RAME, are used to control RAM access and
determine the adequacy of the standby power source during
power-down operation. It is intended that RAME be cleared
and STBY PWR be set as part of a power-down procedure.
RAME and STBY PWR are Read/Write bits.
The remaining two bits, PLC and PPC, control the operation of the EPROM. PLC and PPC are readable in all modes
but can be changed only in Mode O. The PLC bit can be written without restriction in Mode 0, but operation of the PPC
bit is controlled by the state of PLC.
Associated with the EPROM are an 8-bit data latch and a
16-bit address latch. The data latch is enabled at all times,
latching each data byte written to the EPROM. The address
latch is controlled by the PLC bit.
A description of the RAM/EPROM Control Register
follows.

4

x

PPC. Programming Power Control.
This bit gates power from the
RESETIVpp pin to the EPROM programming circuit. PPC is set during
reset and whenever the PLC bit is set.
It can be cleared only if (a) operating in
Mode 0, and (b) if PLC has been
previously cleared. The PPC bit is
defined as follows:
PPC = 0 EPROM programming
power (Vpp) applied.
PPC = 1 EPROM programming
power (Vpp) is not applied.
Unused.
RAM Enable. This Read/Write bit can
be used to remove the entire RAM
from the internal memory map. RAME
is set (enabled) during reset provided
standby power is available on the
positive edge of reset. If RAME is
clear, any access to a RAM address is
external. If RAME is set and not in
Mode 3, the RAM is included in the internal map.
Standby Power. This bit is a read/
write status bit which, when once set,
remains set as long as V CC standby remains above VSBB (minimum). As
long as this bit is set following a period
of standby operation, the standby
power supply has adequately preserved the data in the standby RAM. If this
bit is cleared during a period of standby operation, it indicates that VCC
standby had fallen to a level sufficiently below VSBB (minimum) to
suspect that data in the standby RAM
is not valid. This bit can be set only by
software and is not affected during
reset.

Note that if PPC and PLC are set, they cannot be
simultaneously cleared with a Single MPU write. The PLC bit
must be cleared prior to attempting to clear PPC. If both PPC
and PLC are clear, setting PLC will also set PPC. In addition,

3-765

I

MC68701

A routine which can be used to program the MC68701
EPROM is provided at the end of this publication. This nonreentrant routine requires four double byte variables named
IMBEQ, IMEND, PNTR, and WAIT to be initialized prior to
entry to the routine. These variables indicate (a) the first and
last memory locations which bound the data to be programmed into the EPROM, (b) the first EPROM location to be programmed, and (c) a number which is used to generate
the programming time delay. The last variable, WAIT, takes
into account the MCU input crystal (or TTL-compatible
clock) frequency to insure the programming time, t pp , is
met. WAIT is defined as the number of MPU E-cycles that
will occur in the real-time EPROM programming interval,
tpp. For example, if tpp = 50 milliseconds and the MC68701
is being driven with a 4.00 MHz TTL-compatible clock:
WAIT (MPU E-cycles) = .t pp * (MCU INPUT fREOf)4* 106
. = 50000(4* 106 )/4* 100
=50000

it is assumed that Vpp is applied to the RESET /Vpp pin
whenever PPC is clear. If this is not the case, the result is
undefined.

I

ERASING THE MC68701 EPROM
Ultraviolet erasure will clear all bits of the EPROM to the
"0" state. Note that this erased state differs from that of
some other widely used EPROMs (such as the MCM6870S)
where the erased state is a "1". The MC68701 EPROM is
programmed by erasing it to "O's" and entering "l's" into
the desired bit locations.
The MC68701 EPROM can be erased by exposure to high
intensity ultraviolet light with a wave length of 2537A for a
minimum of 30 minutes. The recommended integrated dose
(UV intensity X exposure time) is 15 Ws/cm. The lamps
should be used without shortwave filters and the MC68701
should be positioned about one inch away from the UV
tubes.
The MC68701 transparent lid should always be covered
after erasing. This protects both the EPROM and lightsensitive nodes from accidental exposure to ultraviolet light.
PROGRAMMING THE MC68701 EPROM
When the MC68701 is released from Reset in Mode 0, a
vector is fetched from location $BFFE:BFFF. This provides a
method for an external program to obtain control of the
microcomputer with access to every location in the EPROM.
To program the EPROM, it is necessary to operate the
MC68701 in Mode 0 under the control of a program resident
in external memory which can facilitate loading and programming of the EPROM. After the pattern has been loaded
into external memory, the EPROM can be programmed as
follows:
a. Apply programming power (Vpp) to the RESET /VPP
pin.
b. Clear the PLC control bit and set the PPC bit by
writing $FE to the RAM/EPROM Control Register.
c. Write data to the next EPROM location to be programmed. Triggered by an MPU write to the
EPROM, internal latChes capture both the EPROM
address and the data byte.
d. Clear the PPC bit for programming time, tpp, by
writing $FC to the RAM/EPROM Control Register
and waiting for time, tpp. This step gates the programming power (Vpp) from the RESET /VPP pin to
the EPROM which programs the location.
e. Repeat steps b through d for each byte to be programmed.
f.
Set the PLC and PPC bits by writing $FF to the
RAM/EPROM control register.
g. Remove the programming power (Vpp) from the
RESET /VPP pin. The EPROM can now be read and
verified.

NOTE
A monitor program called PRObug@ is available from
Motorola Microsystems. PRObug contains a user option for
programming the on-board MC68701 EPROM.

PROGRAMMABLE TIMER
The Programmable Timer can be used to perform input
waveform measurements while independently generating an
output waveform. Pulse widths can vary from several
microseconds to many seconds. A block diagram of the
Timer is shown in Figure 21.

COUNTER ($09:0A)
The key timer element is a 16-bit free-running counter
which is incremented by E (Enable). It is cleared during reset
and is read-only with one exception: a write to the counter
($09) will preset it to $FFFS. This feature, intended for
testing, can disturb serial operations because the counter
provides the SCI internal bit rate clock. TOF is set whenever
the counter contains all 1'so
OUTPUT COMPARE REGISTER ($OB:OC)
The Output Compare Register is a 16-bit Read/Write
register used to control an output waveform or provide an arbitrary timeout flag. It is compared with the free-running
counter on each E-cycle. When a match occurs, OCF is set
and OLVL is clocked to an output level register. If Port 2, bit
1, is configured as an output, OL VL will appear at P21 and
the Output Compare Register and OLVL can then be
changed for the next compare. The function is inhibited for
one cycle after a write to the high byte of the Compare
Register ($OB) to ensure a valid compare. The Output Compare Register is set to $FFFF during reset.
INPUT CAPTURE REGISTER ($OD:OE)
The Input Capture Register is a 16-bit read-only register
used to store the free-running counter when a "proper" input transition occurs as defined by IEDG. Port 2, bit 0 should
be configured as an input, but the edge detect circuit always

Because of the erased state of an EPROM byte is $00, it is
not necessary to program a location which is to contain $00.
Finally, it should be noted that the result of inadvertently
programming a location more than once is the logical OR of
the data patterns.

3-766

MC68701

FIGURE 21 -

BLOCK DIAGRAM OF PROGRAMMABLE TIMER

MC68701 Internal Bus
1RQ2

I

Timer
Control

And
Status
Register

$08

senses P20 even when configured as an output. An input
capture can occur independently of ICF: the register always
contains the most current value. Counter transfer is inhibited, however, between accesses of a double byte MPU
read. The input pulse width must be at least two E-cycles to
ensure an input capture under all conditions.

Input Edge. IEDG is cleared during
reset and controls which level transition will trigger a counter transfer to
the Input Capture Register:
I EDG = 0 Transfer on a negative-edge
IEDG = 1 Transfer on a positive-edge.
Enable Timer Overflow Interrupt.
When set. an IRQ2 interrupt is enabled
for a timer overflow; when clear, the
interrupt is inhibited. It is cleared during reset.
Enable Output Compare Interrupt.
When set. an IRQ2 interrupt is enabled
for an output compare; when clear,
the interrupt is i.,hibited. It is cleared
during reset.
Enable Input Capture Interrupt. When
set. an IR02 interrupt is enabled for an
input capture; when clear, the interrupt is inhibited. It is cleared during
reset.

Bit 3 EOCI

TIMER CONTROL AND STATUS REGISTER (TCSR)

6

5

4

3

2

o

Bit 4 EICI

3-767

Port 2

Bit 1 EIDG

• the free-running counter has overflowed.

7

Port 2

Output level. OLVL is clocked to the
output level register by a successful
output compare and will appear at P21
if Bit 1 of the Port 2 Data Direction
Register is set. It is cleared during
reset.

Bit 2 ETOI

Each of the three events can generate an IR02 interrupt
and is controlled by an individual enable bit in the TCS R.

Input
Edge
Bit 0

Bit 0 OLVL

TIMER CONTROL AND STATUS REGISTER ($08)
The Timer Control and Status Register (TCSR) is an 8-bit
register of which all bits are readable while bits 0-4 can be
written. The three most significant bits provide the timer
status and indicate if:
• a proper level transition has been detected,
• a match has occurred between the free-running
counter and the output compare register, and

Output
Level
Bit 1

MC68701

Bit 5 TOF

Timer Overflow Flag. TOF is set when
the counter contains all 1'so It is
cleared by reading the TCSR (with
TOF set) then reading the counter high
byte ($09), or by RESET.

Transmit/ Receive Control and Status Register. Data is
transmitted and received utilizing a write-only Transmit
Register and a read-only Receive Register. The shift registers
are not accessible to software.

Bit 6 OCF

Output Compare Flag. OCF is set
when the Output Compare Register
matches the free-running counter. It is
cleared by reading the TCSR (with
OCF set) and then writing to the Output Compare Register ($OB or SOC), or
by RESET.
Input Capture Flag. ICF is set to indicate a proper level transition; it is
cleared by reading the TCSR (with ICF
set) and then the Input Capture
Register High Byte ($OD), or by
RESET.

Rate and Mode Control Register (RMCR) ($10)

Bit 7 ICF

II

The Rate and Mode Control Register controls the SCI bit
rate, format. clock source, and under certain conditions, the
configuration of P22. The register consists of four write-only
bits which are cleared during reset. The two least significant
bits control the bit rate of the internal clock and the remaining two bits control the format and clock source.

RATE AND MODE CONTROL REGISTER (RMCR)

7

6

x

x

Bit l:Bit 0

SERIAL COMMUNICATIONS INTERFACE (SCI)
A full-duplex asynchronous Serial Communications Interface (SCI) is provided with two data formats and a variety of
rates. The SCI transmitter and receiver are functionally independent, but use the same data format and bit rate. Serial
data formats include standard mark/space (NRZ) and Biphase and both provide one start bit, eight data bits, and one
stop bit. "Baud" and "bit rate" are used synonymously in
the following description.

x

43210
CCl CCO SSl SSO

x

I

I I

I

I $0010

SSl :SSO Speed Select. These two
bits select the Baud rate when using
the internal clock. Four rates may be
selected which are a function of the
MCU input frequency. Table 6 lists bit
time and rates for three selected MCU
frequencies.

Bit 3:Bit 2

CCl :CCO Clock Control and Format
Select. These two bits control the format and select the serial clock source.
If CCl is set, the DDR value for P22 is
forced to the complement of CCO and
cannot be altered until CCl is cleared.
If CCl is cleared after having been set,
its DDR value is unchanged. Table 7
defines the formats, clock source, and
use of P22.
If both CCl and CCO are set. an external TTL compatible
clock must be connected to P22 at eight times (8X) the
desired bit rate, but not greater than E, with a duty cycle of
50% (± 10%). If CCl :CCO= 10, the internal bit rate clock is
provided at P22 regardless of the values for TE or RE.

WAKE-UP FEATURE
In a typical serial loop multi-processor configuration, the
software protocol will usually identify the addressee(s) at the
beginning of the message. In order to permit uninterested
MPU's to ignore the remainder of the message, a wake-up
feature is included whereby all further SCI receiver flag (and
interrupt) processing can be inhibited until the data line goes
idle. An SCI receiver is re-enabled by an idle string of ten
consecutive 1's or during reset. Software must provide for
the required idle string between consecutive messages and
prevent it within messages.

NOTE: The source of SCI internal bit rate clock is the timer
free running counter. An MPU write to the counter
can disturb serial operations.

PROGRAMMABLE OPTIONS
The following features of the SCI are programmable:
• format: standard mark/space (NRZ) or Bi-phase

Transmit/Receive Control And Status Register
(TRCSR) ($11)
The Transmit/ Receive Control and Status Register controls the transmitter, receiver, wake-up feature, and two individual interrupts and monitors the status of serial operations. All eight bits are readable while bits 0 to 4 are also
writable. The register is initialized to $20 by RESET.

• clock: external or internal bit rate clock
• Baud: one of 4 per E-clock frequency, or external clock (X8 desired baud)
• wake-up feature: enabled or disabled
• interrupt requests: enabled individually for transmitter and receiver
• clock output: internal bit rate clock enabled or disabled to P22

TRANSMIT/RECEIVE CONTROL AND STATUS
REGISTER (TRCSR)

SERIAL COMMUNICATIONS REGISTERS
The Serial Communications· Interface includes four addressable registers as depicted in Figure 22. It is controlled
by the Rate and Mode Control Register and the

7

6

543

IRDR90RF~TDRE IRIE I RE

3-768

o

2
TIE

I I I
TE

WU

$0011

MC68701

TABLE 6 4f _
o
SS1:SS0
E
+16
0
0
+ 128
1
0
1
+ 1024
0
+4096
1
1
External (P22)

SCI BIT TIMES AND RATES

2.4576 MHz

4.0 MHz

614.4 kHz

1.0 MHz

Baud
Baud
Baud
Baud
Up to 76,800 Baud

16 jls/62,5oo daud
128 jls!78123 Baud
1.024 ms/9,6.6 Baud
4.096 ms/244.1 Baud

26 jls/38,4oo
208 jls/4,8oo
1.67 ms/600
6.67 ms/150

TABLE 7 -

4.9152 MHz
1.2288 MHz
13.0 jls!76,8oo Baud
104.2 jls/9,6oo Baud
833.3 jls/1 ,200 Baud
3.33 ms/300 Baud
Up to 153,600 Baud

Up to 125,000 Baud

SCI FORMAT AND CLOCK SOURCE CONTROL
Format

Clock Source

Port 2, Bit 2

0

0

Bi-Phase

Internal

Not Used

0

1

NRZ

Internal

Not Used

1

0
1

NRZ

Internal

Output

NRZ

External

Input

CC1:CCO

1

FIGURE 22 Sit 7

11

SCI REGISTERS
Rate and Mode Control Register

Sit 0

I CCl I CCO 1 551 1SsolS10

I

Transmit/Receive Control and Status Register

RDRF 'ORFE 'TORE' RIE

I I
RE

TIE

TE

I I
wu

Sll

$12

Port 2

10

Transmit Shift Register

12

$13
Transmit Data Register

3·769

MC68701

BitOWU

Bit' TE

Bit 2 TIE

I

Bit 3 RE

Bit 4 RIE

Bit 5 TORE

Bit 6 ORFE

"Wake-up" on Idle Line. When set,
WU enables the wake-up function; it is
cleared by ten consecutive "s or during reset. WU will not set if the line is
idle.
Transmit Enable. When set, P24 DDR
bit is set, cannot be changed, and will
remain set if TE is subsequently
cleared. When TE is changed from
clear to set, the transmitter is connected to P24 and a preamble of nine
consecutive "s is transmitted. TE is
cleared during reset.
Transmit Interrupt Enable. When set,
an IR02 interrupt is enabled when
TORE is set; when clear, the interrupt
is inhibited. TE is cleared during reset.
Receive Enable. When set, the P23
DDR bit is cleared, cannot be changed, and will remain clear if RE is subsequently cleared. While RE is set, the
SCI receiver is enabled. RE is cleared
during reset.
Receiver Interrupt Enable. When set,
an IR02 interrupt is enabled when
RDRF and/or ORFE is set; when clear,
the interrupt is inhibited. RIE is cleared
during reset.
Transmit Data Register Empty. TORE
is set when the Transmit Data Register
is transferred to the output serial shift
register or during reset. It is cleared by
reading the TRCSR (with TORE set)
and then writing to the Transmit Data
Register. Additional data will be
transmitted only if TORE has been
cleared.
Overrun Framing Error. If set, ORFE indicates either an overrun or framing error. An overrun is a new byte ready to
transfer to the Receiver Data Register
with RDRF still set. A receiver framing
error has occurred when the byte
boundaries of the bit stream are not

synchronized to the bit counter. An
overrun can be distinguished from a
framing error by the state of RDRF: if
RDRF is set. then an overrun has occurred; otherwise a framing error has
been detected. Data is not transferred
to the Receive Data Register in an
overrun condition. Unframed data
causing a framed error is transferred to
the Receive Data Register. However,
subsequent data transfer is blocked
until the framing error flag is cleared.'
ORFE is cleared by reading the TRCSR
(with ORFE set) then the Receive Data
Register, or during reset.
Receive Data Register Full. RDRF is
set when the input serial shift register
is transferred to the Receive Data
Register. It is cleared by reading the
TRCSR (with RDRF set), and then the
Receive Data Register, or during reset.

Bit 7 RDRF

SERIAL OPERATIONS
The SCI is initialized by writing control bytes first to the
Rate and Mode Control Register and then to the
Transmit/Receive Control and Status Register. When TE is
set, the output of the transmit serial shift register is connected to P24 and serial output is initiated by transmitting to
9-bit preamble of "s.
At this point one of two situations exist: 1) if the Transmit
Data Register is empty (TOR E= '), a continuous string of 1's
will be sent indicating an idle line, or 2) if a byte has been
written to the Transmit-Data Register (TDRE=O), it will be
transferred to the output serial shift register (synchronized
with the bit rate clock), TORE will be set, and transmission
will begin.
The start bit (0), eight data bits (beginning with bit 0) and a
stop bit ('), will be transmitted .. If TORE is still set when the
next byte transfer should occur, "s will be sent until more
data is provided. In Bi-phase format, the output toggles at
the start of each bit and at half-bit time when a "'" is sent.
Receive operation is controlled by RE which configures P23
as an input and enables the receiver. SCI data formats are illustrated in Figure 23.

FIGURE 23 - SCI DATA FORMATS
Output
Clock

NRZ
Format

Bi-Phase
Format
Idle Start

Bit
0

Bit
3

4

5

6

7

Stop

Data: 01001101 ($4D)

* Devices made with mask numbers T7 A and CB4 do not transfer unframed data to the Receive Data Register.

3-770

MC68701

INSTRUCTION SET
The MC68701 is upward source and object code compatible with the MC6800. Execution times of key instructions
have been reduced and several new instructions have been
added, including a hardware mUltiply. A list of new operations added to the MC6800 instruction set is shown in
Table 1. In addition, two new special opcodes, 4E and 5E,
are provided for test purposes. These opcodes force the program counter to increment like a 16-bit counter, causing address lines used in the expanded modes to increment until
the device is reset. These opcodes have no mnemonics.
The coding of the first (or only) byte corresponding to an
executable instruction is sufficient to identify the instruction
and the addressing mode. The hexadecimal equivalents of
the binary codes, which result from the translation of the 82
instructions in all valid modes of addressing, are shown in
Table 8. There are 220 valid machine codes, 34 unassigned
codes, and 2 reserved for test purposes.
PROGRAMMING MODEL

A programming model for the MC68701 is shown in Figure
9. Accumulator A can be concatenated with accumulator B
and jointly referred to as accumulator D where A is the most
significant byte. Any operation which modifies the double
accumulator will also modify accumulator A and/ or B. Other
registers are defined as follows:
Program Counter - The program counter is a 16-bit
register which always points to the next instruction.
Stack Pointer - The stack pointer is a 16-bit register
which contains the address of the next available location in a
pushdown/pull up (LIFO) queue. The stack resides in random access memory at a location defined by the programmer.
Index Register - The Index Register is a 16-bit register
which can be used to store data or provide an address for the
indexed mode of addressing.
Accumulators The MCU contains two 8-bit accumulators, A and B, which are used to store operands and
results from the arithmetic logic unit (ALU). They can also be
concatenated and referred to as the D (double) accumulator.
Condition Code Registers - The condition code register
indicates the results of an instruction and includes the
Overflow (V), Carry/Borrow from MSB (C), and Half Carry
following five condition bits: Negative (N), Zero (Z),

from bit 3 (H). These bits are testable by the conditional
branch instructions. Bit 4 is the interrupt mask (I-bit) and inhibits all maskable interrupts when set. The two unused bits,
B6 and B7 are read as ones.
ADDRESSING MODES

The MC68701 provides six addressing modes which can be
used to reference memory A summary of addressing modes
for all instructions is presented in Tables 9,10, 11, and 12
where execution times are provided in E cycles. Instruction
execution times are summarized in Table 13. With an input
frequency of 4 MHz, E cycles are equivalent to microseconds. A cycle-by-cycle description of bus activity for
each instruction is provided in Table 14 and a description of
selected instructions is shown in Figure 24.
Immediate Addressing - The operand or "immediate
byte(s)" is contained in the following byte(s) of the instruction where the number of bytes matches the size of the
register. These are two or three byte instructions.
Direct AddreSSing - The least significant byte of the
operand address is contained in the second byte of the instruction and the most significant byte is assumed to be $00.
Dirflct addressing allows the user to access $00 through $FF
using two byte instructions and execution time is reduced by
eliminating the additional memory access. In most applications, the 256-byte area is reserved for frequently referenced
data.
Extended Addressing - The second and third bytes of the
instruction contain the absolute address of the operand.
These are three byte instrutions.
Indexed Addressing - The unsigned offset contained in
the second byte of the instruction is added with carry to the
Index Register and used to reference memory without
changing the Index Register. These are two byte instructions.
Inherent Addressing - The operand(s) are registers and
no memory reference is required. These are single byte ;nstructions.
Relative Addressing - Relative addreSSing is used only for
branch instructions. If the branr::h condition is true, the Program Counter is overwritten with the sum of a signed single
byte displacement in the second byte of the instruction and
the current Program Counter. This provides a branch range
of -126 to 129 bytes from the first byte of the instruction.
These are two byte instructions.

3-771

I

MC68701

TABLE 8 -

OP
00
01

MNEM
NOP

MODE
INHER

2

,
1

02

MNEM

MODE

34

INHER

35

DES
TXS

36

PSHA

-

,

MNEM

MODE

-

1
1

68

ASL

INDXD

6

2

69

ROL

6

3
.3

1

6A

DEC

6

1

6B
6C

INC

6

2

6

37

PSHB

LSRD

3

1

3B

5

05
06

ASLD
TAP

3
2

1
1

39
3A

PULX
RTS
ABX

1

07

TPA

2

1

3B

RTI

3
10

OB

INX
DEX
CLV

3
3
2

1

09

1
1

3C
3D
3E

MUL
WAI

1
1

40

OA

5

PSHX

TST
JMP

1

CLR

INDXD

3
6

4
10

1
1

70
71

NEG

EXTND

6

9
12

1
1

72

2

1

73
74

SEV

2

CLC
SEC

2
2

1

41

75

OE
OF

CLI
SEI

2
2

1

42

76

1

43

SBA

2

1

44

11

CBA

2

1

45

12
13

46
47

48

14
15
16
17

TAS
TBA

2

1

2

1

2

1

18
19

DAA

INHER

1A

COMA
LSRA
RORA
ASRA

1

6D
6E
6F

OB

10

SWI
NEGA

1
1

OC
aD

3F

,

OP

3
3

04

03

II

OP

CPU INSTRUCTION MAP

2

1

2

1

2
2

1
1

OP

MNEM

MODE

-

2
2

DO
D1

SUBB
CMPB

DIR

3

I

3

2
2

D2

SBCB

3

2

4

2
2

5

2

2

D3
D4

ADDD

4

ANDB

3

4

2

D5

BITB

3

2

4

2

LDAB

6
4
4

2

STAB

3
3

2

SUBD
ANDA
BITA

D6
D7

2
2

D8

EORB
AOCB

3
3

2
2

A6

LDAA

4

2

DRAB

3

STAA

4

ADDB

DC

LDD

3
4

2
2

4

2
2

DB

EORA
ADCA

4

2

4

2

4
4

2

DD
DE

STD

ORAA
ADDA

4

2

DIR

4

2

INDXD

4

2

MNEM

MODE

-

CPX

DIR

5

2

9C
9D

JSR

2

9E

LDS

9F

STS

DIR

AO

SUBA

INDXD

2

A1

2
2

A2

Cf..1PA
SBCA

3

A3
A4
A5

COM
LSR

6

3

6

3

A7
A8

ROR

6

3

A9
AA

77

ASR

6

78
79

ASL
ROL

6
6

7A

DEC

6

7B
7C

,

OP

~

5
4

AB
AC

2

DF

CPX

6

2

AD

JSR

6

2

EO
E1

SUBB
CMPS

AE
AF

LDS
STS

5
5
4

2
2

E2
E3
E4

SBCS
ADDD
ANDB

6
4

2

E5
E6
E7

SITB

4

LDAB

4

2
2

STAB

4

2

E8

EORS
ADCB
ORA8

4
4

2

E9
EA

4

2

ADD8
LOD

4

2
2

STD
LDX

5

2

5

2
2

INDXD

ASLA

2

INC

6

3

ROLA

2

1

7D

TST

6

3

BO
B1

SUBA
CMPA

4

3

2

1

7E

JMP

3

3

S2

SBCA

4

3

6

3
2

B3
B4

SUBD
ANDA

6
4

3
3

2

B5

BITA

3

86
B7

4
4

7F

CLR

4C

INCA

2

1

80

4D

TSTA

2

1

81

SUBA
CMPA

4E

T

82

S8CA

2

2

4F

CLRA

83

50

NEG8

SU8D
ANDA

4
2

3
2

EXTND
I

3

3

88

LDAA
STAA
EORA

3

E8
EC

10

51

85

BITA

2

2

4

3

ED

52

86

LDAA

2

2

89
8A

ADCA

1E
1F

DRAA

4

3

ADDA

4

3

2

2

SB
8C

EE
EF

CPX

2
2

8D

JSR

6
6

3
3

Fa

2
2

8E
8F

LDS

3

STS

5
5

3

CO
C1

SU88
CMP8

2

C2

SBC8
ADDD

2
2
4

AND8

18

A8A

INHER

2

1

1C

REL

2
2

1
1

84

53

COMB

2

1

87

54
55
56

LSRS

2

1

86
89

EORA
ADCA

ROR8

2

1

8A

DRAA

20

8RA

21

8RN

3

2
2

22

8HI

3

2

23
24

BLS

2

57

1

88

ADDA

58

ASR8
ASL8

2

2

2

1

BC

CPX

IMMED

2
4

3

25
26

8CS
BNE

3
3
3·

2
2

59
5A

ROLB
DEC8

2
2

1
1

8SR
LOS

REL
IMMED

6
3

2
3

27

8EO

3

58

2B

2
2

BD
BE
BF

90

SU8A

8CC

3

3

8VC

3

INC8

2

1

29

8VS

3

TSTB

2

1

8PL

3

2
2

5D

2A

5E

T

28

BMI

3

2

5F

CLR8

INHER

2

3

2

80

NEG

INDXD

6

3

2

61

3
3
3

2
1

3
4
4

1
1

66

ROR

1

67

ASR

2C

aGE

2D

BLT

2E
2F

8GT

31

8LE
TSX
INS

32

PULA

33

PUL8

30

It
REL
INHER

~

2

5C

62
63

84
65

1

INDXD

3

2

C3
C4

EXTND
IMMED

3

EXTND

S8C8

4
4

F3
F4

ADDD
AND8

6
4

3

2
2
2

F5
F6

81TB
LOA8

4
4

F7

STAB

4

3
3
3

EORB

4

3

2

2

F9

ADCB

4

3

2

2

FA

ORA8

4

3

F8

ADD8

4

3

FC

LDD

5

3

FD

STD
LDX
STX

5

3

FB

5

94

3

2
2

C7

2

SU8D
ANDA

C8

EORB

2

2

95

81TA

3

2

C9

ADC8

2

LDAA
STAA

3
3
3

2
2

CA
C8

2
2

FE
FF

2

CC
CD

DRAB
ADD8
LDD

2
2
2
3

3

3

3

ADCA
DRAA

98

ADDA

,

3
3
3

NOTES:
1. Addressing Modes
INHER_lnherent INDXD-Indexed
IMMED-Immediate
REL-Relative
EXTND-Extended DIR-Direct
2. Unassigned opcodes are indicated by "e" and should not be executed.
3. Codes marked by "T" force the PC to function as a 16-bit counter.

3·772

2
2
2

CE
CF

3

2

93

9A

3

BIT8

1

2
2

3
3

LDA8

2

6

5
4

3
2

2

EORA

2

SUB8
CMPB

3

97

2

F2

3

98
99

5

2
2

F1

CMPA

2
2

4

INDXD

S8CA

C5
C6

4

STX

91

6
6

6

DIR

2

4
4

92

96
COM
LSR

,

2

3
3

DECA

2
2

2

3
3

49

EXTND
IMMED

2

LDX
STX

4A
4B

1

D9
DA

,

LDX

It
IMMED

It
EXTND

5

3

5

3

* UNDEFINED OP CODE

MC68701

TABLE 9 -

INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS
Condition Codes
Direct

Immed
Pointer Operations

MNEM Op -

Compare Index Register

CPX

Decrement Index Register

DEX

BC 4

# Op 3 9C

5

Index

# Op 2 AC 6

Extend

Inherent

# Op -

# Op -

2 BC 6

3

#

Booleanl
Arithmetic Operation

1 SP-1-SP

Decrement Stack Pointer

DES

34

INX

08 3

1 X+l-X

Increment Stack Pointer

INS

31

1 1 SP+l-SP

Load Index Register

LOX

CE 3

3 DE 4

Load Stack Pointer

LOS

BE

3 9E

Store Index Register

3

2 EE 5
2 AE 5

2 FE 5
2 BE 5

3

M-XH,IM+l)-XL

3

M-SPH,IM+ll-SPL

STX

OF 4

2 EF 5

2 FF 5

3

XH-M,XL -IM+ll

Store Stack Pointer

STS

9F

4

2 AF 5

2 BF 5

3

Index Reg -

TXS

Stack Pointer

3

1 X-l-SP

3

1 SP+l-X

Stack Pntr -Index Register

TSX

30

Add

ABX

3A 3

PSHX

3C 4

1 XL -MSp,SP-l-SP
XH-MSp,SP-l-SP

38

1 SP+1-SP,MSP-XH

Push Data
Pull Data

PULX

5

1

0

Z

V

C

R
R

R

R

SPH-M,SPL -IM+ll
35

2

N

l

4

3

3

I

t t tt
t

1 X-1-X

Increment Index Register

3

4

H

·· ·· · · ·
··· ··· ··· ·· ··· ···
·· ·· ··
··· ··· · · · ···
·· ··· ··· ··· ··· ···
······

X- M:M+ 1

09 3

5

1 B+X-X

SP+ 1-SP,MSP-XL

TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 1 of 2)
Accumulator and
Memory Operations
Add Acmltrs
Add B to X
Add with Carry
Add
Add Double
And
Shift Left,
Arithmetic
Shift Left Obi
Shift Right,
Arithmetic
Bit Test
Compare Acmltrs
Clear

Compare
1's Complement

Decimal Adj. A
Decrement

Exclusive OR
Increment

Load Acmltrs
Load Double
Logical Shift,
Left

MNE
ABA
ABX
ADCA
ADCB
ADDA
ADDB
ADDD
ANDA
ANDB
ASL
ASLA
ASLB
ASLD
ASR
ASRA
ASRB
BITA
BITB
CBA
CLR
CLRA
CLRB
CMPA
CMPB
COM
COMA
COMB
DAA
DEC
DECA
DECB
EORA
EORB
INC
INCA
INCB
LDAA
LDAB
LDD
LSL
LSLA
LSLB
LSLD

Immed
Extend
Index
Direct
Inher
Boolean
Condition Codes
Op # Op Expression
# Op - # Op - # Op - #
N Z V C
H
1B 2 1 A + B-A
I ,
~
I
3A 3 1 OO:B + X--X
A+M+C--A
89 2 2 99 3 2 A9 4 2 B9 4 3
B+M+C-B
C9 2 2 09 3 2 E9 4 2 F9 4 3
A + M-A
8B 2 2 9B 3 2 AB 4 2 BB 4 3
B + M--A
CB 2 2 DB 3 2 EB 4 2 FB 4 3
D+M:M+1--D
C3 4 3 03 5 2 E3 6 2 F3 6 3
A· M--A
84 2 2 94 3 2 A4 4 2 B4 4 3
R
B . M --B
C4 2 2 04 3 2 E4 4 2 F4 4 3
R
68 6 2 78 6 3
48 2 1 g~lllllllr-o
b7
bO
58 2 1
05 3 1
67 6 2 77 6 3
47 2 1
b7
bO
57 2 1
85 2 2 95 3 2 A5 4 2 B5 4 3
A·M
R
C5 2 2 05 3 2 E5 4 2 F5 4 3
B'M
R
11 2 1 A-B
1
I •
6F 6 2 7F 6 3
OO-M
R S R R
4F 2 1 OO-A
R S R R
5F 2 1 00 --B
R S R R
A-M
81 2 2 91 3 2 A1 4 2 B1 4 3
C1 2 2 01 3 2 El 4 2 F1 4 3
B-M
M -M
63 6 2 73 6 3
R S
43 2 1 A-A
R S
53 2 1 B-B
R S
19 2 1 Adj binary sum to BCD.
j
6A 6 2 7A 6 3
M-1-M
4A 2 1 A - 1 -A
5A 2 1 B-1 --B
88 2 2 98 3 2 A8 4 2 B8 4 3
R
A <±> M --A
2
4
2
08
3
2
E8
2
F8
4
3
C8
B <±> M -B
I R
6C 6 2 7C 6 3
M+ 1-M
\
I
4C 2 1 A + 1 --A
I .1
5C 2 1 8 + 1 --8
86 2 2 96 3 2 A6 4 2 86 4 3
M --A
R
C6 2 2 06 3 2 E6 4 2 F6 4 3
M --B
R
CC 3 3 DC 4 2 EC 5 2 FC 5 3
M:M + 1 -0
R
68 6 2 78 6 3
48 2 1
g~llllllll_o
58 2 1
b7
DO
05 3 1

•

,

••••
••

...-

c:rntfuIHJ

••

•

••
••
•

•
•
••

•.

...-

3·773

•
••
•••
•

,

:

,,

••
•••
•
•
••
•

I

MC68701

TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 2 of 2)
Accumulator and
Memory Operations
Shift Right,
Logical

Multiply
2's Complement
(Negate)
No Operation
Inclusive OR
Push Data
Pull Data

I

Rotate Left

Rotate Right

Subtract Acmltr
Subtract with
Carry
Store Acmltrs

Subtract
Subtract Double
Transfer Acmltr
Test, Zero or
Minus

MNE
LSR
LSRA
LSRB
LSRD
MUL
NEG
NEGA
NEGB
NOP
ORAA
ORAB
PSHA
PSHB
PULA
PULB
ROL
ROLA
ROLB
ROR
RORA
RORB
SBA
SBCA
SBCB
8TAA
STAB
STD
SUBA
SLIBB
SUBD
TAB
TBA
TST
TSTA
TSTB

Immed
Direct
Extend
Index
Inher
# Op - # Op
# Op
Op # Op - #
64 6 2 74 6 3
44 2 1
54 2 1
04 3 1
3D 10 1
60 6 2 70 6 3
40 2 1
50 2 1
01 2 1
8A 2 2 9A 3 2 AA 4 2 BA 4 3
CA 2 2 DA 3 2 EA 4 2 FA 4 3
36 3 1
37 3 1
32 4 1
33 4 1
69 6 2 79 6 3
49 2 1
59 2 1
66 6 2 76 6 3
46 2 1
56 2 1
10 2 1
82 2 2 92 3 2 A2 4 2 B2 4 3
C2 2 2 D2 3 2 E2 4 2 F2 4 3
97 3 2 A7 4 2 B7 4 3
D7 3 2 E7 4 2 F7 4 3
DD 4 2 ED 5 2 FD 5 3
80 2 2 90 3 2 AO 4 2 BO 4 3
CO 2 2 DO 3 2 EO 4 2 FO 4 3
83 4 3 93 5 2 A3 6 2 B3 6 3
1
16 l
17 2 1
6D 6 2 7D 6 3
4D 2 1
5D 2 1

-

The condition code register notes are listed after Table 12.

3-774

Boolean
Expression

-

--

0-1111
II III-EJ
7
hO
~)

•I •I •I

AXB-D
00 - M-M
00 - A-A
00 - B-B
PC + 1 -PC
A + M-A
B + M-B
A -Stack
B -Stack
Stack -A
Stack -B

-

I I I
I I I

-

bO

D-IIIIIIII'-IJ
b7

•I •I • ••
I I
• • • ••
•• •• •• ••
•I •I •I •I
R
R

~1111111k--{fJ
b7

Condition Code.
H
N Z V C
R
R
R
R

I

I

I
I

\

I
I

I

I

bO

A- B-A
A-M-C-A
B - M - C-B
A-M
B-M
D -M:M + 1
A-M-A
B - M-B
D - M:M + 1 -D
A-B
B-A
M -00
A - 00
B - 00

I

I

••
•I

I

I

I

R
R
R
R
R

R
R
R

I I

••
R
R
R

MC68701

TABLE 11 - JUMP AND BRANCH INSTRUCTIONS
Condition Code Reg.
Direct
Operations

Relative

Index

-

Inherent

Extend

-

# Op

20

3

2

21

3

BCC

24

3

BCS

25

3

2

C=1

BEG

27

3

2

Z=1

BGE

2C

3

NEBV=O

BGT

2E

3

Z+INEBV)=O

MNEM Op

Branch Always

BRA

Branch Never

BRN

Branch If Carry Clear
Branch If Carry Set
Branch If = Zero
Branch If

2: Zero

Branch If > Zero

-

# Op

# Op -

# Op -

None
None

C=o

Branch If Higher

BHI

22

3

2

Branch If Higher or Same

BHS

24

3

2

C=O

:s Zero

BlE

2F

3

2

Z+INEBV)=1

C=1

Branch If

543210
H I N Z V C

Branch Test

#

C+Z=O

Branch If Carry Set

BlO

25

3

2

Branch If lower Or Same

BlS

23

3

2

Branch If < Zero

BlT

20 3

Branch If Minus

BMI

2B 3

Branch If Not Equal Zero

BNE

26

3

2

Z=O

Branch If Overflow Clear

BVC

28

3

2

V=o

Branch If Overflow Set

BVS

29

3

2

V=1
N=O

C+Z=1
NEB V= 1

I

N=1

Branch If Plus

BPl

2A 3

2

Branch To Subroutine

BSR

80 6

2

Jump To Subroutine

JSR

No Operation

NOP

01

Return From Interrupt

RTI

3B 10

Jump
JMP
6E 3 2 7E 3 3
f--'-_
_ _ _ _ _ _ ___+--+-+-+-+---+--+_j-'-~+_=_+_+_+4__+_j____lSee
Special Operations- Figure 24
90 5

2

AO 6

2 BD 6

... . . .
0

0

0

l

J

f-;-f-;-

:

3
2

1

J

l l

!

0
0
Return From
Subroutine
RTS
39 5
I-::--:--_
__
_ _ _ _ ___+--+-+-+-+---+--+_j-~~+_+__+_+__+__+____I
See Special Operations-Figure 241--+-+--+--11--+---1

Software Interrupt

SWI

3F 12

1

Wait For Interrupt

WAI

3E

1

TABLE 12 -

9

•

S

•

•

CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS
Condition Code Register

Operations

Inherent
MNEM Op

-

#

Boolean Operation

Clear Carry

CLC

OC

2

1

O-C

Clear Interrupt Mask

CLI

OE

2

1

0-1

Clear Overflow

ClV

OA

2

1

O-V

Set Carry

SEC

00

2

1

1-C

Set Interrupt Mask

SEI

OF

2

1

1-1

Set Overflow

SEV

OB

2

1

1-V

CCR

TAP

06

2

1

A-CCR

Accumulator A

TPA

07

2

1

CCR-A

Accumulator A CCR -

LEGEND
Op Operation Code (Hexadecimal)
- Number of MPU Cycles
MSp Contents of memory location pointed to by Stack Pointer
# Number of Program Bytes
+ Arithmetic Plus
- Arithmetic Minus
• Boolean AND
X Arithmetic Multiply
+ Boolean Inclusive OR
e Boolean Exclusive OR
M Complement of M
Transfer Into
o Bit=Zero
00 Byte= Zero

3-775

CONDITION CODE SYMBOLS
H Half-carry from bit 3
Interrupt mask
N Negative (sign bit)
Z Zero (byte)
V Overflow, 2's complement
C Carry/Borrow from MSB
R Reset Always
S Set Always
l Affected
• Not Affected

5

4

3

H

I

N

··
··
·

·
··

··
··
·

l

l

l

2
Z

1

0

V

C

··· ·· ··
· ·· ·
·
···· ·
······
R

S

R

R

S

S

l

l

l

MC68701

TABLE 13 -

INSTRUCTION EXECUTION TIMES IN E CYCLES

ADDRESSING MODE

ADDRESSING MODE

!III

'isQ)

E

I

ABA
ABX
AOC
ADD
AD DO
AND
ASL
ASLD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BHS
BIT
BLE
BLO
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BSR
BVC
BVS
CBA
CLC
CLI
CLR
CLV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOR
INC
INS

.

u
~

"tl
Q)

"tl

c

!)(

"tl

Q)
)(
Q)

E
~

Q)

.c

..

>

'is
Q)

III

E

a:

.§

C

••
•

••5

Q)

.§

C

w

.:

.:

"i

•
•

••
3

••

••

2
3

•••
••
•
•••

2
2
4
2

•••
•
•••
•••
2

3
5
3

•••
•
••
•••
•
••
3

4
4
6
4
6

•6
••
•••
••
4

6

2

•
••
••
•
•
4

2

3

•5
••
•
•3

••

•
4
6
6

•
6

•
•4
6

•

"tl

4
4
6
4
6

•6
•
••
••
••
••

•
•

••
2
3
2

•
••
••

•
4
6
6

•6
••
6
•
4

INX
JMP
JSR
LOA
LOO
LOS
LOX
LSL
LSLO
LSR
LSRD
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBO
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI

3
3
3
3
3
3
3

•

4

6

!III

3

3
3
3
3
3
3
3
3
6
3
3
2
2
2
2
2

•
2

•2
2
3
3

•
•3

3-776

2
3
3
3

••
•
•••
•
••
•
2

•
•

••
•
•
•••
••
••
••
••
•••
••
2

2
4

"tl
Q)

0
f

3
4
4
4

•
•

•••
•
•3
•••
••
•
••

"tl

Q)
)(
Q)

w

)(

.:

•3

•3

6
4
5

6
4
5
5
5
6

!

5

5
6

•
••
6

6

•4
•

••
•
••
6
6

•3
••
•3

•4
•
••4

4
4
4
3
5

5
5

••
••
••
••
•

"tl

c

5
4
6

•
•
•
•

•
6

•
•

•

"tl

•6
••
6
•
•••
•6
4

6

•••
4
•

••
4
5
5
5
4
6

••
•••
6
••
•

E
Q)
i
.c

Q)

.~
III

.:

"ii
a:

3

•
•
•
••
•

•

•
••
••

2
3
2
3
10
2
2

•3

4
4
5
2
2
10
5
2

•
2
2
2

••
•••
•

12
2
2
2
2
2
3
3
9

•

MC68701

SUMMARY OF CYCLE-BY-CYCLE OPERATION
Table 14 provides a detailed description of the information
present on the Address Bus, Data Bus, and the Read/Write
(R/W) line during each cycle of each instruction.
The information is useful in comparing actual with expected results during debug of both software and hardware
as the program is executed. The information is categorized in
groups according to addressing mode and number of cycles

TABLE 14 -

Address Mode and
Instructions

per instruction. In general, instructions with the same addressing mode and number of cycles execute in the same
manner. Exceptions are indicated in the table.
Note that during MPU reads of internal locations, the
resultant value will not appea, on the external Data Bus except in Mode O. "High order" byte refers to the most significant byte of a 16-bit value.

CYCLE-BY-CYCLE OPERATION (Sheet 1 of 5)

R/W
Address Bus

Data Bus

Line

IMMEDIATE

2

1
2

Opcode Address
Opcode Address + 1

1
1

Opcode
Operand Data

LOS
LOX
LDD

3

1
2

Opcode Address
Opcode Address + 1
Opcode Address + 2

1
1
1

Opcode
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

CPX
SUBD
ADDD

4

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address Bus FFFF

1
1
1
1

Opcode
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Address of Operand

1
1
1

Opcode
Address of Operand
Operand Data

Opcode Address
Opcode Address + 1
Destination Address

1
1

a

Opcode
Destination Address
Data from Accumulator

Opcode Address
Opcode Address + 1
Address of Operand
Operand Address + 1

1
1
1
1

Opcode
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Opcode Address
Opcode Address + 1
Address of Operand
Address of Operand + 1

1
1

a
a

Opcode
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)

Opcode Address
Opcode Address + 1
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1

Opcode
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Subroutine Address
Stack Pointer
Stack Pointer-l

1
1
1

Opcode
Irrelevant Data
First Subroutine Opcode
Return Address (Low Order Byte)
Return Address (High Order Byte)

ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

3
1
2

3
4

DIRECT

ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

3

1
2

3

STA

3

LOS
LOX
LDD

4

STS
STX
STD

4

CPX
SUBD
ADDO

5

JSR

5

1
2

3
1
2

3
4
1
2

3
4
1
2

3
4
5
1
2

3
4
5

a
a

3-777

I

MC68701

TABLE 14 -

CYCLE-BY-CYCLE OPERATION (Sheet 2 of 5)

R/W

Address Mode and
Instructions

Address Bus

Line

Data Bus

EXTENDED

3

JMP

1
2

3
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

STA

4

1
2

3
4
4

1
2

3
4

I

5

LOS
LOX
LDD

1
2

3

4
5
5

STS
STX
STD

1
2

3
4

5
LSR
NEG
ROL
ROR
TST*

ASL
ASR
CLR
COM
DEC
INC
CPX
SUBD
ADDD

6

1
2

3
4

5
6
6

1
2

3
4

5
6
JSR

6

1
2

3
4

5
6

* TST

Opcode Address
Opcode Address + 1
Opcode Address + 2

1
1
1

Opcode
Jump Address (High Order Byte)
Jump Address (Low Order Byte)

Opcode Address
Opcode Address + 1
Opcode Address+ 2
Address of Operand

1
1
1
1

Opcode
Address of Operand
Address of Operand (Low Order Byte)
Operand Data

Opcode Address
Opcode Address + 1
pc ode Add ress + 2
Operand Destination Address

1
1
1

0

Opcode
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand
Address of Operand + 1

1
1
1
1
1

Opcode
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Opcode Address
Opcode A.ddress + 1
Opcode Address + 2
Address of Operand
Address of Operand + 1

1
1
1

Opcode
Address
Address
Operand
Operand

o

0
0
1
1
1
1
1

of Operand (High Order Byte)
of Operand (Low Order Byte)
Data (High Order Byte)
Data (Low Order Byte)

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand
Address Bus FFFF
Address of Operand

0

Opcode
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data

Opcode Address
Opcode Address + 1
Opcode Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1
1

Opcode
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Opcode Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer-l

1
1
1
1

Opcode
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

0
0

does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus= $FFFF.

3·778

MC68701

TABLE 14 Address Mode· and
Instructions

CYCLE-BY-CYCLE OPERATION (Sheet 3 of 5)

R/W
Address Bus

Line

Data Bus

INDEXED

3

JMP

1

2

3
ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SSC
SUB

4

4
4

STA

1

2
3

1

2

3
4

5

LDS
LDX
LDD

1

2

3
4

5

5

STS
STX
STD

1

2
3
4

5
ASL
ASR
CLR
COM
DEC
INC
CPX
SUBD
ADDD

LSR
NEG
ROL
ROR
TST*

6

1

2

3
4

5
6
6

1

2
3
4

5
6
JSR

6

1

2

3
4

5
6

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Offset
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset

1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset

1
1
1

0

Opcode
Offset
Low Byte of Restart Vector
Operand Data

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data IHigh Order Byte)
Operand Data ILow Order Byte)

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data IHigh Order Byte)
Operand Data ILow Order Byte)

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset
Opcode Address
Opcode Address+ 1
Address Bus FFFF
Index Register+ Offset
Index Register + Offset + 1
Address Bus FFFF
Opcode Address
Opcode Address + 1
Address Bus FFFF
I ndex Register + Offset
Stack Pointer
Stack Pointer-l

0
0
1
1
1
1

1

0
1

1
1
1
1

1
1
1
1

0
0

Opcode
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Opcode
Offset
Low Byte of Restart Vector
Operand Data IHigh Order Byte)
Operand Data ILow Order Byte)
Low Byte of Restart Vector
Opcode
Offset
Low Byte of Restart Vector
First Subroutine Opcode
Return Address ILow Order Byte)
Return Address IHigh Order Byte)

*TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus= $FFFF.

3.. 779

I

MC68701

TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 4 of 5)
Address Mode and
Instructions

R/W
Line

Address Bus

Data Bus

INHERENT
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM

II

2

1
2

Opcode Address
Opcode Address + 1

1
1

Opcode
Opcode of Next Instruction

ABX

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Irrelevant Data
Low Byte of Restart Vector

ASLD
LSRD

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Irrelevant Data
Low Byte of Restart Vector

DES
INS

3

1
2
3

Opcode Address
Opcode Address + 1
Previous Stack Pointer Contents

1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data

INX
DEX

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Opcode of Next Instruction
Low Byte of Restart Vector

PSHA
PSHB

3

1
2
3

Opcode Address
Opcode Address + 1
Stack Pointer

1
1

0

Opcode
Opcode of Next Instruction
Accumulator Data

TSX

3

1
2
3

Opcode Address
Opcode Address + 1
Stack Pointer

1
1
1

Opcode
Opcode of Next .Instruction
Irrelevant Data

TXS

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Opcode of Next Instruction
Low Byte of Restart Vector

PULA
PULB

4

1
2
3
4

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1

1
1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data
Operand Data from Stack

PSHX

4

1
2
3
4

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer-l

1
1

0
0

Opcode
Irrelevant Data
Index Register (Low Order Byte)
Index Register (High Order Byte)

1
2
3
4
5
1
2
3
4
5

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1
Stack Pointer+ 2
Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer+ 2

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)

1
2
3
4
5
6

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer-l
Stack Pointer - 2
Stack Pointer- 3
Stack Pointer-4
Stack Pointer - 5
Stack Pointer-6

1
1

Opcode
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Cpndition Code Register

DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA

SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST

PlILX

5

RTS

5

WAI

9

7
8
9

0
0
0
0
0
0
0

3-780

Opcode
Irrelevant Data
Irrelevant Data
Address of Next Instruction (High Order Byte)
Address of Next Instruction (Low Order Byte)

MC68701

TABLE 14 Address Mode and
Instructions
INHERENT
MUL

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart

Opcode Address
Opcode Address+ 1
Stack Pointer
Stack Pointer+ 1
Stack Pointer+2
Stack Pointer+ 3
Stack Pointer+ 4
Stack Pointer+5
Stack Pointer+6
Stack Pointer+ 7

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Irrelevant Data
Contents of Condition Code Register from Stack
Contents of Accumulator B from Stack
Contents of Accumulator A from Stack
Index Register from Stack (High Order Byte)
Index Register from Stack (Low Order Byte)
Next Instruction Address from Stack (High Order Byte)
Next Instruction Address from Stack (Low Order Byte)

9
10
11
12

Opcode Address
Opcode Address+ 1
Stack Pointer
Stack Pointer-1
Stack Pointer- 2
Stack Pointer - 3
Stack Pointer- 4
Stack Pointer-5
Stack Pointer-6
Stack Pointer-7
Vector Address FFFA (Hex)
Vector Address FFFB (Hex)

1
1
0
0
0
0
0
0
0
1
1
1

Opcode
Irrelevant Data
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condition Code Register
Irrelevant Data
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)

3

1
2
3

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Branch Offset
Low Byte of Restart Vector

6

1
2
3
4
5
6

Op Code Address
Op Code Address +1
Address Bus FFFF
Subroutine Starting Address
Stack POinter
Stack POinter ~ 1

1
1
1
1

Op Code
Branch Offset
Low Byte of Restart Vector
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

1
2
3
4
5
6
7

10

1
2
3
4
5
6
7

8
9
10
12

1
2
3
4
5
6
7

8

RELATIVE
BCC BHT BNE BLO
BCS BLE BPL BHS
BEQ BLS BRA BRN
BGE BLT BVC
BGT BMT BVS
BSR

Data Bus

Opcode Address
Opcode Address + 1
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF

10

8

SWI

R/W
Line

Address Bus

9
10
RTI

CYCLE·BY·CYCLE OPERATION (Sheet 5 of 5)

3·781

a
a

Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector

I

..
3:

oen
FIGURE 24 -

CD

......

SPECIAL OPERATIONS

o

~

JSR, Jump to Subroutine

Direct

I

SWI, Software Interrupt

$9D= JSR

U)

..!..I

ex>

I\)

EXTND

K = Direct Address

~

k>~

$AD= JSR
K= Offset
Next Main Instr.

RTN

I

L--/

Next Main Instr.

RTN

~

{

I~~

$3F=SWI

RTN

Main Program

INDXD

SP

F

Main Program

~

Main Program

~

Stack

SP-2§8
SP-l
RTNH
SP

SP-3

Index Register (XH)
Index Register (XL)

$3E=WAI

SP-l

RTNH

SP

RTNL

2f

Stack

I

"'. ""om "om ,"'aw,' "" '",.;;;~;~"m

Ic::)

$BD=JSR

SP+l
SP+2

AcmltrB

SP+3

AcmltrA

SP+4

Index Register (XH)

SP+5

Index Register (XL)

SP+6

RTNH

SP+ 7

RTNL

2f

Main Program

¢~

$8D= BSR

± K=Offset

I Next Main Instr.

RTS, Return from Subroutine

~

$39=RTS

I

~

¢

Stack
--.

SP_2§8
SP-l
RTNH
SP

Subroutine

I

SP

SH = Subr. Addr.

BSR, Branch To Subroutine

RTN

AcmltrA

SP-2

Next Main Inst.

~

AcmltrB

SP-4

Main Program

SL= Subr. Addr.

RTN

Condition Code

SP-6
SP-5

RTNL

Main Program

~

WAI, Wait for Interrupt

Stack

SP-7

Stack

INDXD

I

PC~

X+ K

S
P
§8
SP+
1
RTNH

--.

SP+ 2

RTNL

Legend:
RTN = Address of next instruction in Main Program to be executed upon return from subroutine
RTNH = Most significant byte of Return Address
RTNL = Least significant byte of Return Address
- = Stack Pointer After Execution
K = 8-bit Unsigned Value

~

JMP, Jump

RTNL

I

Next Instruction

Condition Code

Main Program
$7E=JMP

E"~d~ f

KH = Next Address
KL = Next Address

K

I

Next Instruction

MC68701

EPROM PROGRAMMING ROUTINE

PAGE
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057
00058

001

EPROM

.SA:1

EPROM
NAM
OPT
TTL

*** ROUTINE TO PROGRAM THE MC68701 EPROM ***
EPROM
ZOl,LLEN=80
*** ROUTINE TO PROGRAM THE MC68701 EPROM **

*********************************************************

*

*
*

*
*
*
*
*
*
*
*
*
*
*
*
*

E PRO M -- A NON-REENTRANT ROUTINE
THE MC68701 EPROM.

JSR

EPROM

NOTES:
1.

THE ROUTINE EXPECTS FOUR DOUBLE BYTE VALUES
TO BE INITIALIZED PRIOR TO BEING CALLED.
THESE VALUES ARE:
IMBEG = A DOUBLE BYTE ADDRESS WHICH POINTS
TO THE FIRST BYTE TO BE PROGRAMMED
INTO THE EPROM.
IMEND

A DOUBLE BYTE ADDRESS WHICH POINTS
TO THE LAST BYTE TO BE PROGRAMED ININTO THE EPROM.

PNTR

= A DOUBLE BYTE ADDRESS WHICH POINTS
TO THE FIRST BYTE IN THE EPROM TO BE
PROGRAMMED.

WAIT

A DOUBLE BYTE COUNTER VALUE WHICH IS
A FUNCTION OF THE MCU INPUT FREQUENCY AND IS USED WITH THE OUTPUT COMPARE FUNCTION TO GENERATE A 50 MSEC
TIMEOUT. IT IS EQUIVALENT TO
4 * 10**6

50000 * (MCU INPUT FREQ)

VALUES FOR TYPICAL INPUT FREQS

*

**
*
*

I

CALLING CONVENTION:

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

PROGRAM

THE ROUTINE PROGRAMS THE MC68701 EPROM
STARTING AT ADDRESS "PNTR" FROM A
BLOCK OF MEMORY STARTING AT "IMBEG"
AND ENDING AT "IMEND".

*

*
*

TO

ARE:

WAIT

MCU INPUT FREQ

30615 ($7797)
50000 ($C350)
61375 ($EFBF)

2.45 MHZ
4.00 MHZ
4.91 MHZ

2.

IT IS ASSUMED THAT POWER (VPP) IS
TO THE RESET PIN FOR PROGRAMMING.

AVAILABLE

3.

THIS ROUTINE

CHECKING.

PERFORMS

NO

ERROR

Routine parameter initialization, such as stack pointer, etc., must be done prior to entry.
(Use of PRObug will ensure all needed initialization.)

3-783

MC68701

EPROM PROGRAMMING ROUTINE

PAGE

002

00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070A 0080

.SA:l

*
0008
0009
OOOB
0014

A
A
A
A

EPROM

EQU
EQU
EQU
EQU

L 0 CAL
ORG

0002
0002
0002
0002

A
A
A
A

ROUTINE TO PROGRAM THE MC68701 EPROM

***

E QUA T E S

TCSR
TIMER
OUTCMP
EPMCNT

*

***

IMBEG
IMEND
PNTR
WAIT

RMB
RMB
RMB

$08
$09
SOB
$14

TIMER CONTROL/STAT REGISTER
COUNTER REGISTER
OUTPUT COMPARE REGISTER
RAM/EPROM CONTROL REGISTER

VAR I ABL E S
$80
2
2
2
2

START OF MEMORY BLOCK
00072A 0082
LAST BYTE OF MEMORY BLOCK
00073A 0084
FIRST BYTE OF EPROM TO BE PGM'D
COUNTER VALUE
00074A 0086
RMB
00075
S TAR T S
HER E
00076
* EPROM
00077
00078A 3000
ORG
$3000
00079A 3000 DE 84
A EPROM LDX
PNTR
SAVE CALLING ARGUMENT
PSHX
RESTORE WHEN DONE
00080A 3002 3C
IMBEG
USE
STACK
0008lA 3003 DE 80
A
LDX
00082
EPR002 PSHX
SAVE POINTER ON STACK
00083A 3005 3C
00084A 3006 86 FE
A
LDAA
I/$FE
REMOVE VPP, SET LATCH
EPMCNT
PPC=l, PLC=O
00085A 3008 97 14
A
STAA
X
MOVE DATA MEMORY-TO-LATCH
00086A 300A A6 00
A
LDAA
PNTR
GET WHERE TO PUT IT
00087A 300C DE 84
A
LDX
00088A 300E A7 00
A
STAA
X
STASH AND LATCH
NEXT ADDR
INX
00089A 3010 08
STX
PNTR
ALL SET FOR NEXT
00090A 3011 DF 84
A
ENABLE EPROM POWER (VPP)
LDAA
I!$FC
0009lA 3013 86 FC
A
PPC=O, PLC=O
EPMCNT
STAA
00092A 3015 97 14
A
00093
* NOW WAIT FOR 50 MSEC TIMEOUT USING OUTPUT COMPARE.
00094
00095
GET CYCLE COUNTER
LDD
WAIT
00096A 3017 DC 86
A
BUMP CURRENT VALUE
ADDD
TIMER
00097A 3019 D3 09
A
CLR
TCSR
CLEAR OCF
00098A 30lB 7F 0008 A
00099A 30lE DD OB
A
STD
OUTCMP
SET OUTPUT COMPARE
A
OOlOOA 3020 86 40
LDAA
NOW WAIT FOR OCF
1/$40
00101
00102A 3022 95 08
A EPR004 BITA
TCSR
EPR004
NOT YET
00103A 3024 27 FC 3022
BEQ
SETUP FOR NEXT ONE
00104A 3026 38
PULX
NEXT
00105A 3027 08
INX
MAYBE
DONE
00106A 3028 9C 82
A
CPX
IMEND
NOT YET
00107A 302A 23 D9 3005
BLS
EPR002
REMOVE VPP, INHIBIT LATCH
00108A 302C 86 FF
A
LDAA
I/$FF
EPROM CAN NOW BE READ
00109A 302E 97 14
A
STAA
EPMCNT
RESTORE PNTR
OOllOA 3030 38
PULX
OOlllA 3031 DF 84
A
STX
PNTR
THAT'S ALL
00112A 3033 39
RTS
00113
END
TOTAL ERRORS 00000--00000

OOOllA 0080

II

EPROM

3-784

MC68701

IMPORTANT NOTICE
Devices made with mask numbers T7 A and CB4 may generate multiple framing
error flags in response to unframed data. These devices will eventually synchronize
correctly after a framing error; but valid, framed data following an unframed byte may
generate false framing error flags.

I

3-785

®

MC68701U4

MOTOROLA

Advance Information
HMOS
(HIGH-DENSITY N-CHANNEL, SILICON-GATE)

8-BIT EPROM MICROCOMPUTER/MICROPROCESSOR
(MCU/MPUl

II

The MC68701 U4 is an 8-bit single-chip EPROM microcomputer unit
(MCU) which enhances the capabilities of the MC6801 and significantly
enhances the capabilities of the M6800 Family of parts. It includes an
MC6801 microprocessor unit (MPUI with direct object-code compatibility and upward object-code compatibility with the MC6800. Execution times of key instructions have been improved over the MC6800
and the new instructions found on the MC6801 are included. The MCU
can function as a monolithic microcomputer or can be expanded to a
64K byte address space. It is TTL compatible and requires one + 5-volt
power supply for nonprogramming operation. An additional Vpp power
supply is needed for EPROM programming. On-chip resources include
4096 bytes of EPROM, 192 bytes of RAM, a serial communications interface (SCI), parallel I/O, and a 16-bit six-function programmable
timer.

a-BIT EPROM
MICROCOMPUTER/
MICROPROCESSOR

• Enhanced MC6800 Instruction Set
• Upward Source and Object Code Compatibility with the MC6800,
MC6801, and MC6801U4
• Bus Compatibility with the M6800 Family
• 8 x 8 Multiply Instruction
• Single-Chip or Expanded Operation to 64K Byte Address Space
• Internal Clock Generator with Divide-by-Four Output
• Serial Communications Interface (SCI)
• 16-Bit Six-Function Programmable Timer
•
•
•
•

PIN ASSIGNMENT

VSS
XTALl

39

Three Output Compare Functions
Two Input Capture Functions
Counter Alternate Address
4096 Bytes of User EPROM

• 192 Bytes of RAM
• 32 Bytes of RAM Retainable During Power Down
• 29 Parallel I/O and Two Handshake Control Lines

SCl
SC2

EXTAL2

N'Mi

P30

TRQl

P31

RESET/Vpp

P32

VCC

P33

P20

P34
P35

P21

• NMI Inhibited Until Stack Load
P22
P23

GENERIC INFORMATION
(T A = 0°

Package Type
Ceramic -

L Suffix

to 70°C)
Generic Number
MC68701U4L
MC68701 U4L-l

31

P36
P37

P24

P40

Pl0

P41

Pll

P42

P12

P43

P13

P44

P14

P45

P15

P46

P16

P47
VCC

Standby

This document contains information on a new product Specifications and information herein
are subject to change without notice

3:
(')

BLOCK DIAGRAM

G)

co
.....
o

Cl.
Cl.

~~
I~w
-'0

...
08

08

...

...

3·796

MC68701U4

Circuitry to provide the programming levels is dependent
primarily on the normal system usage of the three pins. If
configured as outputs, the circuit shown in Figure 15 may be
used; otherwise, three-state buffers can be used to provide
isolation while programming the mode.

PROGRAMMING THE MODE
The operating mode is determined at RESET by the levels
asserted on P22, P21, and P20. These levels are latched into
PC2, PC1, and PCO of the program control register on the
positive edge of RESET. The operating mode may be read
from the port 2 data register, as shown below, and programming levels and timing must be met as shown in Figure 14. A
brief outline of the operating modes is shown in Table 3.

MEMORY MAPS
The MC68701 U4 can provide up to 64K byte address space
depending on the operating mode. A memory map for each
operating mode is shown in Figure 16. The first 32 locations
of each map are reserved for the internal register area, as
shown in Table 4, with exceptions as indicated.

PORT 2 DATA REGISTER

6
IpC2 I PCl

PCO

o

4

3

P24

P23

P22

P21

$03

P201

FIGURE 14 - MODE PROGRAMMING TIMING
See Figure 15
for Diode Arrangement

(P20, P21, 1"22)

:?,p:;.:.::

mET - - -- .....

Mode Inputs
(P20, P21. P22)

r

VMPDD

VMPL
Mode Latch
Level

'"

MODE PROGRAMMING (Refer to Figure 14)
Symbol

Min

Max

Unit

Mode Programming Input Voltage Low

VMPL

-

1.8

V

Mode Programming Input Voltage High

VMPH

4.0

-

V

VMPDD

0.6

PWRSTL

3.0

E Cycles

Mode Programming Setup Time

tMPS

2.0

-

Mode Programming Hold Time
RESET Rise Time~ 1 p's
RESET Rise Time< 1 p's

tMPH

0
100

-

ns

-

Characteristic

Mode Programming Diode Differential

(If

Diodes are Used)

RESET Low Pulse Width

TABLE 3 - MODE SELECTION SUMMARY
P22
Mode
7

pe2
H

P21
PCl
H

6
5

H

H

L

I

H

L

H

I

P20
PCO
H

EPROM
I

RAM
I

Interrupt
Vectors
I

I
I

I
I

Bus
Mode
I
MUX(2,3)

Operating Mode
Single Chip
Multiplexed! Partial Decode

4

H

-

-

-

L

L
H

-

3

L
H

Non-Multiplexed! Partial Decode
U ndefined l4 )

E

I

E

MUXll,5)

Multiplexed! RAM

2

L

H

L

E

E

MUXll)

Multiplexed!RAM

1

L

L

H

E

0

L

L

L

I
I

I
I
I

E

MUXI2,3)
MUXll)

Multiplexed/RAM and EPROM
Multiplex ed Test! Programming

LEGEND
I - Internal
E - External
MUX - Multiplexed

NMUXI2,3)

NMUX - Non-Multiplexed
L - Logic "0"
H - Logic "1"

NOTES:
1. Addresses associated with ports 3 and 4 are considered external in modes 0, 2, and 3.
2. Addresses associated with port 3 are considered external in modes 1, 5, and 6.
3. Port 4 default is user data input; address output is optional by writing to port 4 data direction register
4. Mode 4 is a non-user mode and should not be used as an operating mode.
5. Mode 3 has the internal RAM and internal registers relocated at $DOOO-$DOFF.

3-797

V
E Cycles

II

MC68701U4

FIGURE 15 - TYPICAL MODE PROGRAMMING CIRCUIT
VCC

Rl
P20--~'-~-+--------------------------~

P20 (PCO)

P21 --~--__~------------------------~ P21 (PC1)
10
P22--~~~-e~------------------------~ P22 (PC2)
V

MC68701U4
Mode Control Switches

I

D

R2

D
"Normal"
Sl
RESETIVpp

Vpp~

"Program"

T

C

FIGURE 16 -

NOTES:
1. Mode a as shown (switches closed).
2. Rl = 10 kilohms (typical).
3. The RESET time constant is equal to RC where
R is the equivalent parallel resistance of R2 and
the number of resistors (R 1) placed in the circuit by closed mode control switches.
4. D= lN914, lN4001 (typical).
5. If V= VCC, then R2= 50 ohms (typical) to meet
VIH for the RESETIVpp pin. V=VCC is also
compatible with MC6801 U4. The RESET time
constant in this case is approximately R2 x C.
6. Switch Sl allows selection of normal (RESET)
or programming (Vpp) as the input to the
RESET IVpp pin. During switching, the input
level is held at a value determined by a diode
(D), resistor (R2) and input voltage (VI.
7. While Sl is in the "Program" position, RESET
should not be asserted.
8. From powerup, RESET must be held low for at
least tRe. The capacitor, C, is shown for conceptual purposes only and is on the order of
1000 /LF for the circuit shown. Typically, a buffer with an RC input will be used to drive
RESET, eliminating the need for the larger
capacitor.
9. Diode Vf should not exceed VMPDD min.

MEMORY MAPS (Sheet 1 of 3)

Multiplexed Test/ Program Mode
$0000(1)
$OOlF ~L....t:......:....:::....:~

Internal
Registers
External
Memory Space

MC68701 U4
Mode

o

Internal
RAM

External
Memory Space
External
$BFFO
$B FFF """"'-r-r-r-r-r-r,.-t,. Interrupt Vectors(2)
$ FOOO t-;.-,.....,.....,.....,.....,.....,.....,.-,I;::

External

NOTES:
1) Excludes the following addresses which may be
used externally: $04, $05, $06, $07, and $OF.
2) The interrupt vectors are at $BFFO-$BFFF.
3) There must be no overlapping of internal and
external memory spaces to avoid driving the
data bus with more than one device.

4) This mode
EPROM.
5) Modes 5-7
mode 0 by
port 2 data

3-798

is used to program the on-chip
can be irreversibly entered from
writing to the PCO-PC2 bits of the
register.

~

FIGURE 16 -

oen

MEMORY MAPS (Sheet 2 of 3)

CO

.....
o...&
C

MC68701 U4
Mode

MC68701U41
Mode

Multiplexed/RAM and EPROM

$001 F
$1XXlO111
$0040

~ 1'"' '"'
b));)))))

J'\

$OOFFnl

$0000(1)
$001 F

Memory Space
Internal

$0040

RAM

$OOFF r«/U(U(I(

j

External
Memory Space

Internal
RAM

$ 0 0 0 0 . a ) Internal
Registers( 1, 2)
$OOlF

External
Memory Space

..:...

1/// / / / / / /

$0000(1)

Internal
Registers
External
Memory Space

Registers
External

(0
(0

$Fooo

$0040 I) ) ) ( ) ) ) ) ) J<'

I

$OOFF

Internal

$FFEF~}
$FFFO
$FFFF

3

Multiplexed/ RAM

Multiplexed/ RAM

External
Memory Space

C".)

2

MC68701U4
Mode

EPROM
External
Interrupt Vectors

$FFFO
$FFFF

I

I~ External

L . ._ _ _ _•

$FFFO

Interrupt Vectors

$FFFF
NOTES:
1) Excludes the following addresses which may be
used externally: $05 and $07.
2) Internal EPROM addresses $FFFO to $FFFF are
not usable.
3) Address lines A8-A 15 will not contain addresses until the data direction register for port
4 has been written with "ls" in the appropriate
bits. These address lines will assert "ls" until
made outputs by writing the data direction
register.

NOTE:
1) Excludes the following addresses which may be
used externally $04, $05, $06, $07, and $OF.

V((((//((

$FOOO
Internal
EPROM

$FFFF

V///////OJ

Internal
Interrupt Vectors

NOTES:
1) Excludes the following addresses which may
not be used externally: $04, $06, and $OF (no
lOS).
2) Address lines AO to A7 will not contain addresses until the data direction register for port
4 has been written with "1 s" in the appropriate
bits. These address lines will assert "ls" until
made outputs by writing the data direction
register.

$FFFF

_rrnm"

$FOOO

EPROM
Internal
Interrupt Vectors
$FFFF

NOTES:
1) Excludes the following addresses which may be
used externally: $04, $06, $OF.
2) Address lines A8-A15 will not contain addresses until the data direction register for port
4 has been written with "1 s" in the appropriate
bits. These address lines will assert "ls" until
made outputs by writing the data direction
register.

Internal
RAM

7

MC68701U4

TABLE 4 - INTERNAL REGISTER AREA
Register
Port 1 Data Direction Register* * *
Port 2 Data Direction Register* * *
Port 1 Data Register
Port 2 Data Register
Port 3 Data Direction Register* * *
Port 4 Data Direction Register* * *
Port 3 Data Register
Port 4 Data Register
Timer Control and Status Register
Counter (High Byte)
Counter (Low Byte)
Output Compare Register (High Byte)
Output Compare Register (Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
Port 3 Control and Status Register
Rate and Mode Control Register
Transmit/Receive Control and Status Register
Receive Data Register
Transmit Data Register
RAM Control Register
Counter Alternate Address (High Byte)
Counter Alternate Address (Low Byte)
Timer Control Register 1
Timer Control Register 2
Timer Status Register
Output Compare Register 2 (High Byte)
Output Compare Register 2 (Low Byte)
Output Compare Register 3 (High Byte)
Output Compare Register 3 (Low Byte)
Input Capture Register 2 (High Byte)
Input Capture Register 2 (Low Byte)

MC68701U4 INTERRUPTS
The M6801 Family supports two types of interrupt requests: maskable and non-maskable. A non-maskable interrupt (NMI) is always recognized and acted upon at the completion of the current instruction. Maskable interrupts are
controlled by the condition code register I bit and by individual enable bits. The I bit controls all maskable interrupts. Of the maskable interrupts, there are two types: IRQ1
and IRQ2. The programmable timer and serial communications interface use an internal IRQ2 interrupt line, as shown
in the block diagram. External devices and IS3 use IRQ1. An
IRQ1 interrupt is serviced before IRQ2 if both are pending.

Address
00
01
02
03
04*
05* *
06*
07* *
08
09
OA
OB
OC
OD
OE
OF*
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F

NOTE
After reset, an NMI will not be serviced until the first
program load of the stack pointer. Any NMI generated
before this load will be remembered by the processor
and serviced subsequent to the stack pointer load.

All IRQ2 interrupts use hardware prioritIZed vectors. The
single SCI interrupt and three timer interrupts are serviced in
a prioritized order and each is vectored to a separate location. All interrupt vector locations are shown in Table 5. In
mode 0, reset and Interrupt vectors are defined as SBFFOSBFFF.
The interrupt flowchart is depicted in Figure 17 and is
common to every interrupt excluding reset. During interrupt
servicing, the program counter, index register, A accumulator, B accumulator, and condition co.de register are
pushed to the stack. The I bit is set to inhibit maskable interrupts and a vector is fetched corresponding to the current
highest priority interrupt. The vector is transferred to the
program counter and instruction execution is resumed. Interrupt and RESET timing are illustrated in Figures 18 and 19.

* External addresses in modes 0, 1, 2, 3, 5, and 6; cannot be
accessed in mode 5 (no lOS)
* * External addresses in modes 0, 2, and 3
* * * 1 = Output, 0= Input

TABLE 5 - MCU INTERRUPT VECTOR LOCATIONS
Mode 0

Modes 1-3, 5-7

MSB

LSB

MSB

LSB

BFFE

BFFF

FFFE

FFFF

RESET

BFFC

BFFD

FFFC

FFFD

Non-Maskable Interrupt* *

BFFA
BFF8

BFFB
BFF9

FFFA

FFFB
FFF9

Software Interrupt
Maskable Interrupt Request 1

FFF8

Interrupt

BFF6

BFF7

FFF6

FFF7

Input Capture Flag*

BFF4

BFF5

FFF4

FFF5

Output Compare Flag*

BFF2

BFF3

FFF2

FFF3

Timer Overflow Flag*

BFFO

BFF1

FFFO

FFF1

Serial Communications Interface*

* iRTI2 interrupt
* * NMI must be armed (by accessing stack pointer) before an
NMI is executed

3-801

I

..
s:

FIGURE 17 -

n
en

INTERRUPT FLOWCHART

00

......
o

...

C

~

WAI

w

60

o

I\)

SCI= TlE-TDRE + RIEo(RDRF + ORFE)
ICI = IICFl o EICllI + (lCF2o EIC)2)
OCI = IOCFloEOCll) + (OCF2oEOCI2) + (OCF3o EOCI3)

Vector-PC
Mode 0

Modes 1-3, 5-7

mJl

BFFC-BFFD

FFFC-FFFD

SWI

BFFA-BFFB

mm

FFFA-FFFB

Software Interrupt

BFF8-BFF9

FFF8-FFF9

Maskable Interrupt Request 1

ICF

BFF6-BFF7

FFF6-FFF7

Input Capture Interrupt

Non-Maskable Interrupt

OCF

BFF4-BFF5

FFF4-FFF5

Output Compare Interrupt

TOF

BFF2-BFF3

FFF2-FFF3

Timer Overflow Interrupt

SCI

BFFO-BFFI

FFFO-FFFI

SCI Interrupt

~

3:
FIGURE 18 -

Last Instruction

~

0
en

INTERRUPT SEQUENCE

00

-....

ICycie
#1

#2

#4

#3

#5

#8

#7

#6

#9

#11

#10

0

#12

~

C
----1
Interal
Address Bus

IRQl

L....J

L......J

I

I

L......J

L......J

L......J

L-..J

L...J

L-J

L-..J

L......J

L......J

L.....-I

L......J

L.....-J

L-.J

I Bit Set

~ ~tpcs

\

NMlorlRQ2

~ ~tPcs

Internal
Data Bus _ _ _ _ - - - - - - - - - - - Op Code Op Code
PC 0-7

PC8-15

X 0-7

X8-15

ACCA

ACCB

\

Internal R/W

Irrelevant
Data

CCR

Vector
MSB

Vector
LSB

First Inst. of
Interrupt Routine

/

(..)

00

0

(..)

FIGURE 19 -

VCC

" "~\\\\\\\
&\\\\'1\\\\\\~"t~\~\W"
/1-...
+

525V
4.75
V

I I

RESET TIMING

LJL.n

~
~
~~,pcs

i=
r'pcs
~
~40V

II

I I

'RC

,

os;,'\. _ __

RESET
Internal
Address Bus

S\\\\\\\\\\\\\\\\~ h\\\S\\\\\\\S\\\\\\\\\\\\\\~ II.-.--.J'o'--...J'''----..J''---_A-_~_.....A..._-A._-A_-'\._
FFFE

Internal R/W
Internal
Data Bus

FFFE

FFFE

FFFE

FFFF

New PC

FFFE

'40 K

>30 K

>20 K

These are representative AT-cut crystal parameters only. Crystals of other
types of cut may also be used.

MC68701U4

----------~ID~I---------L1

C1

RS

CO

CL = 20 pF (tYPical I

Equivalent Circuit
NOTE
TTL-compatible oscillators may be
obtained from
Motorola Component Products
Attn: Crystal Clock Oscillators
2553 N. Edgington St
Franklin Park, IL 60131
Tel: 312-451-1000
Telex: 433-0067

Ibl Oscillator Stabilization Time (tRCI

~4-.7-5-V------------~J~r--------------------------------

VCC

~------tRC------~

Oscillator
Stabilization
Time, tRC

3-805

I

MC68701U4

SC2 is configured as readlwrite and is used to control the
direction of data bus transfers. An MPU read is enabled
when readlwrite and E are high.
P10-P17 (PORT 1)
Port 1 is a mode independent 8-bit 1/0 and timer port.
Each line can be configured as either an input or output as
defined by the port 1 data direction register. Port 1 bits 0, 1,
and 2 (PlO, P11, and P12) can also be used to exercise one
input edge function and two output compare functions of
the timer. The TTL compatible three-state buffers can drive
one Schottky TTL load and 30 pF, Darlington transistors, or
CMOS devices using external pullup resistors. It is configured as a data input port during RESET. Unused pins can
remain unconnected.

I

P20-P24 (PORT 2)
Port 2 is a mode-independent, 5-bit, multipurpose 1/0
port. The voltage levels present on P20, P21, and P22 on the
rising edge of RESET determine the operating mode of the
MCU. The entire port is then configured as a data input port.
The port 2 lines can be selectively configured as data output
lines by setting the appropriate bits in the port 2 data direction register. The port 2 data register is used to move data
through the port. However, if P21 is configured as an output, it is tied to the timer output compare 1 function and cannot be used to provide output from the port 2 data register
unless output enable 1 (OE1) is cleared in timer control
register 1.
Port 2 can also be used to provide an interface for the
serial communications interface and the timer input edge
function. These configurations are described in SERIAL
COMMUNICATIONS INTERFACE and PROGRAMMABLE
TIMER.
The port 2 three-state TTL-compatible output buffers are
capable of driving one Schottky TTL load and 30 pF, or
CMOS devices using external pullup resistors.
PORT 2 DATA REGISTER

IPC2

PCl

PCO

P24

P23

P22

P2l

P20

PORT 3 CONTROL AND STATUS REGISTER

6

153 1153
1Flag IRQl

5

4

3

I X I ass 1Enable
Latch
.

0

X

X

X

$OF

Bits 0-2 Not used.
Bit 3
Latch Enable - This bit controls the input latch for
port 3. If set, input data is latched by an IS3
negative edge. The latch is transparent after a read
of the port 3 data register. Latch enable is cleared
during reset.
OSS (Output Strobe Select) - This bit determines
Bit 4
whether OS3 will be generated by a read or write of
the port 3 data register. When clear, the strobe is
generated by a read; when set, it is generated by a
write. OSS is cleared during reset.
Bit 5
Not used.
IS3 IRQ1 Enable - When set, an IRQ1 interrupt
Bit 6
will be enabled whenever the IS3 flag is set; when
clear, the interrupt is inhibited. This bit is cleared
during reset.
IS3 Flag - This read-only status bit is set by an IS3
Bit 7
negative edge. It is cleared by a read of the port 3
control and status register (with IS3 flag set)
followed by a read or write to the port 3 data
register or during reset.
PORT 3 IN EXPANDED NON-MULTIPLEXED MODE
Port 3 is configured as a bidirectional data bus (07-00) in the
expanded non-multiplexed mode. The direction of data
transfers is controlled by readlwrite (SC2). Data is clocked
by E (enable).
PORT 3 IN EXPANDED MULTIPLEXED MODE - Port 3 is
configured as a time multiplexed address (A7-AO) and data
bus (07-00) in the expanded multiplexed mode where address strobe (AS) can be used to demultiplex the two buses.
Port 3 is held in a high-impedance state between valid address and data to prevent bus conflicts.

$03

P30-P37 (PORT 3)
Port 3 can be configured as an 1/0 port, a bidirectional
8-bit data bus, or a multiplexed addressl data bus depending
on the operating mode. The TTL compatible three-state output buffers can drive one Schottky TTL load and 90 pF.
Unused lines can remain unconnected.
PORT 3 IN SINGLE-CHIP MODE - Port 3 is an 8-bit 1/0
port in the single-chip mode with each line configured by the
port 3 data direction register. There are also two lines, IS3
and OS3, which can be used to control port 3 data transfers.
Three port 3 options are controlled by the port 3 control
and status register and are available only in single-chip
mode: 1) port3 input data can be latched using IS3 (SC1) as
a control signal, 2) OS3 (SC2) can be generated by either an
MPU read or write to the port 3 data register, and 3) an IRQ1
interrupt can be enabled by an IS3 negative edge. Port 3
latch timing is shown in Figure 4.

P40-P47 (PORT 4)
Port 4 is configured as an 8-bit 110 port, as address outputs, or as data inputs depending on the operating mode.
Port 4 can drive one Schottky TTL load and 90 pF, and is the
only port with internal pullup resistors. Unused lines can remain unconnected.
PORT 4 IN SINGLE-CHIP MODE - In single-chip mode,
port 4 functions as an 8-bit 1/0 port with each line configured by the port 4 data direction register. Internal pullup
resistors allow the port to directly interface with CMOS at
5-volt levels. External pullup resistors to more than 5 volts,
however, cannot be used.
PORT 4 IN EXPANDED NON-MULTIPLEXED MODE
Port 4 is configured from reset as an 8-bit input port where
the port 4 data direction register can be. written to provide
any or all of eight address lines AD to A7. Internal pullup
resistors pull the lines high until the port 4 data direction
register is configured.

3-806

MC68701U4

Bit 1

PORT 41N EXPANDED MULTIPLEXED MODE - In all expanded multiplexed modes except modes 1 and 6, port 4
functions as half of the address bus and provides A8 to A 15.
In modes 1 and 6, the port is configured from reset as an
8-bit parallel input port where the port 4 data direction
register can be written to provide any or all of upper address
lines A8 to A 15. Internal pullup resistors pull the lines high
until the port 4 data direction register is configured where bit
o controls A8.

RESIDENT MEMORY

Bit 2-5
Bit 6

The MC68701 U4 has 192 bytes of on-chip RAM and 4096
bytes of on-chip UV erasable EPROM. This memory is controlled by four bits in the RAM/EPROM control register.
Thirty-two bytes of the RAM are powered through the
VCC standby pin and are maintainable during VCC powerdown. This standby portion of the RAM consists of 32 bytes
located from $40 through $5F.
Power must be supplied to VCC standby if the internal
RAM is to be used, regardless of whether standby power
operation is anticipated.
The RAM is controlled by the RAM/EPROM control
register.
RAM/EPROM CONTROL REGISTER ($14)
The RAM/ EPROM control register includes four bits:
STBY PWR, RAME, PLC, and PPC. Two of these bits,
STBY PWR and RAME, are used to control RAM access and
determine the adequacy of the standby power source during
power-down operation. It is intended that RAME be cleared
and STBY PWR be set as part of a power-down procedure.
RAME and STBY PWR are read/write bits.
The remaining two bits, PLC and PPC, control the operation of the EPROM. PLC and PPC are readable in all modes
but can be changed only in mode O. The PLC bit can be written without restriction in mode 0, but operation of the PPC
bit is controlled by the state of PLC.
Associated with the EPROM are an 8-bit data latch and a
16-bit address latch. The data latch is enabled at all times,
latching each data byte written to the EPROM. The address
latch is controlled by the PLC bit.
A description of the RAM/EPROM control register
follows.
RAM/EPROM CONTROL REGISTER
6

I~~~ IRAME I
Bit 0

5
X

4

I

X

3

I

X

0

I

X

I

PPC

I

PLC

$14

Programming Latch Control (PLC). This bit controls the latch which captures the EPROM address
to be programmed and whether the PCC bit can be
cleared. The latch is triggered by an M PU write to a
location in the EPROM. This bit is set during reset
and can be cleared only in mode O. The PLC bit is
defined as follows:
PLC = 0- EPROM address latch enabled; EPROM
address is latched during MPU writes to
the EPROM.
PLC = 1 - EPROM address latch is transparent.

Bit 7

Programming Power Control (PPC). This bit gates
power from the RESETIVpp pin to the EPROM
programming circuit. PPC is set during reset and
whenever the PLC bit is set. It can be cleared only if
operating in mode 0, and if PLC has been previously cleared. The PPC bit is defined as follows:
PPC = 0- EPROM programming power (Vpp)
applied.
PPC= 1- EPROM programming power (Vpp) is
not applied.
Unused.
RAM Enable (RAME). This read/write bit can be
used to remove the entire RAM from the internal
memory map. RAME is set (enabled) during reset
provided standby power is available on the positive
edge of reset. If RAME is clear, any access to a
RAM address is external. If RAME is set, the RAM
is included in the internal map.
Standby Power (STBY PWR). This bit is a
read/write status bit which when cleared indicates
that V CC standby has decreased sufficiently below
VSBB (minimum) to make data in the standby
RAM suspect. It can be set only by software and is
not affected during reset.

Note that if PPC and PLC are set, they cannot be
simultaneously cleared with a single MPU write. The PLC bit
must be cleared prior to attempting to clear PPC. If both PPC
and PLC are clear, setting PLC will also set PPC. In addition,
it is assumed that Vpp is applied to the RESET IVpp pin
whenever PCC is clear. If this is not the case, the result is
undefined.
ERASING THE MC68701 U4 EPROM
Ultraviolet erasure will clear all bits of the EPROM to the
zero state. The MC68701U4 EPROM is programmed by erasing it to zeros and entering ones into the desired bit locations.
The MC68701U4 EPROM can be erased by exposure to
high intensity ultraviolet light with a wave length of 2537
angstroms for a minimum of 30 minutes. The recommended
integrated dose (ultraviolet intensity times exposure time) is
15 watts/centimeter. The lamps should be used without
shortwave filters, the MC68701U4 should be positioned
about one inch away from the ultraviolet tubes, and the
transparent lid should not be covered.
The MC68701 U4 transparent lid should always be covered
after erasing. This protects both the EPROM and lightsensitive nodes from accidental exposure to ultraviolet light.
PROGRAMMING THE MC68701U4 EPROM
When the MC68701U4 is released from reset in mode 0, a
vector is fetched from location $BFFE:$BFFF. This provides
a method for an external program to obtain control of the
microcomputer with access to every location in the EPROM.
To program the EPROM, it is necessary to operate the
MC68701 U4 in mode 0 under the control of a program resident in external memory which can facilitate loading and programming of the EPROM. After the pattern has been loaded

3-807

I

MC68701U4

I

into external memory, the EPROM can be programmed as
follows:
a. Apply programming power (VPP) to the RESET/Vpp
pin.
b. Clear the PLC control bit and set the PPC bit by writing
$FE to the RAM/EPROM control register.
c. Write data to the next EPROM location to be programmed. Triggered by an MPU write to the EPROM, internal latches capture both the EPROM address and the
data byte.
d. Clear the PPC bit for programming time, t pp , by writing
$FC to the RAM/EPROM control register and waiting
for time, tpp. This step gates the programming power
(Vpp) from the RESETlVpp pin to the EPROM which
programs the location.
e. Repeat steps b through d for each byte to be programmed.
f. Set the PLC and PPC bits by writing $FF to the
RAM/EPROM control register.
g. Remove the programming power (Vpp) from the
RESET IVpp pin. The EPROM can now be read and
verified.
Because the erased state of an EPROM byte is $00, it is not
necessary to program a location which is to contain $00.
Finally, it should be noted that the result of inadvertently
programming a location more than once is the logical OR of
the data patterns.

OUTPUT COMPARE REGISTERS
($lC:lO)

($OB:OC),

($lA:1B),

The three output compare registers are 16-bit read/write
registers, each used to control an output waveform or provide an arbitrary time-out flag. They are compared with the
free-running counter during the negative half of each E cycle. When a match occurs, the corresponding output compare flag (OCF) is set and the corresponding output level
(OLVL) is clocked to an output level register. If both the corresponding output enable bit and data direction register bit
are set, the value represented in the output level register will
appear on the corresponding port pin. The appropriate OLVL
bit can then be changed for the next compare.
The function is inhibited for one cycle after a write to its
high byte ($OB, $1A, or $1 C) to ensure a valid compare after
a double byte write. Writes can be made to either byte of the
output compare register without affecting the other byte.
The OLVL value will be clocked out independently of
whether the OCF had previously been cleared. The output
compare registers are set to $FFFF during reset.
INPUT CAPTURE REGISTERS ($OD:OE), ($lE:1F)
The two input capture registers are 16-bit read-only
registers used to store the free-running counter when a
"proper" input transition occurs as defined by the corresponding input edge bit (IEDGl or IEDG2). The input pin's
data direction register should be configured as an input, but
the edge detect circuit always senses P10 and P20 even
when configured as an output. The counter value will be
latched into the input capture registers on the second
negative edge of the E clock following the transition.
An input capture can occur independently of ICF; the
register always contains the most current value. Counter
transfer is inhibited, however, between accesses of a double
byte MPU read. The input pulse width must be at least two E
cycles to ensure an input capture under all conditions.

PROGRAMMABLE TIMER
The programmable timer can be used to perform
measurements on two separate input waveforms while independentlY generating three output waveforms. Pulse
widths can vary from several microseconds to many
seconds. A block diagram of the timer is shown in Figure 21.
COLJNTER ($09:0A), ($15, $16)
The key timer element is a 16-bit free-running counter
which is incremented by E (enable). It is cleared during reset
and is read-only with one exception: in mode 0 a write to the
counter ($09) will preset it to $FFF8. This feature, intended
for testing, can disturb serial operations because the counter
provides the SCI internal bit rate clock. The TOF bit is set
whenever the counter contains all ones. If ETOI is set, an interrupt will occur when the TOF is set. The counter may also
be read at $15 and $16 to avoid inadvertently clearing the
TOF.

TIMER CONTROL AND STATUS REGISTERS
Four registers are used to provide the MC68701U4 with
control and status information about the three output compare functions, the timer overflow function, and the two input edge functions of the timer. They are:
Timer Control and Status Register (TCSR)
Timer Control Register 1 (TCR 1)
Timer Control Register 2 (TCR2)
Timer Status Register (TSR)

3·808

FIGURE 21 -

il'i02

3:
n
0)

BLOCK DIAGRAM OF PROGRAMMABLE TIMER
MC68701U4 Internal Bus

CO
.....
o

......

Port Control
CirCUitry

Input Edge
P20

w

P10

CO

Output Level
P21

eX>
o

Output Level
P11

Output Level
P12

C

~

MC68701U4

TIMER CONTROL AND STATUS REGISTER (TCSR)
($08) - The timer control and status register is an 8-bit
register of which all bits are readable, while only bits 0-4 can
be written. All the bits in this register are also accessible
through the two timer control registers and the timer status
register. The three most significant bits provide the timer
status and indicate if:

Bit 7

1. a proper level transition has been detected at P20,
2. a match has occurred between the free-running
counter and output compare register 1, or
3. the free-running counter has overflowed.
Each of the three events can generate an IR02 interrupt
and is controlled by an individual enable bit in the TCS R.

TIMER CONTROL REGISTER 1 (TCR1) ($17) - Timer
control register 1 is an 8-bit read/write register which contains the control bits for interfacing the output compare and
input capture registers to the corresponding I/O pins.

TIMER CONTROL REGISTER 1

7

TIMER CONTROL AND STATUS REGISTER

76543210

I

Input Capture Flag - ICFl is set to indicate that a
proper level transition has occurred; it is cleared by
reading the TCSR or the TSR (with ICFl set) and
the input capture register 1 high byte ($OD), or during reset. Refer to TIMER STATUS REGISTER
(TSR) ($19)

6

IOE3 I OE2

4

3

2

1

0

OEl IIEDG21IEDG110LVL3IoLVL210LVL11

$17

IleFl loeFl I TOF I Elell I EOeil I ETOIIIEDG110LVL11 $00

Bit 0

Output Levell - OL VL 1 is clocked to output level
register 1 by a successful output compare and will
appear at P21 if bit 1 of the port 2 data direction
register is set and the OEl control bit in timer control register 1 is set. OLVL 1 and output level
register 1 are cleared during reset. Refer to TIMER
CONTROL REGISTER 1 (TCR1) ($17).

Bit 1

Input Edge 1 - I EDG 1 is cleared during reset and
controls which level transition on P20 will trigger a
counter transfer to input capture register 1:
IEDG 1 = 0 transfer on a negative-edge
IEDGl = 1 transfer on a positive-edge
Refer to TIMER CONTROL REGISTER 1 (TCR1)
($17)

Bit 2

Bit 0

Output Levell - OLVL 1 is clocked to output level
register 1 by a successful output compare and will
appear at P21 if bit 1 of the port 2 data direction
register is set and the OEl control bit is set OLVL 1
and output level register 1 are cleared during reset.
Refer to TIMER CONTROL AND STATUS
REGISTER (TCSR) ($08).

Bit 1

Output Level 2 - OLVL2 is clocked to output level
register 2 by a successful output compare and will
appear at Pll if bit 1 of port 1 data direction register
is set and the OE2 control bit is set. OLVL2 and output level register 2 are cleared during reset.

Bit 2

Output Level 3 - OLVL3 is clocked to output level
register 3 by a successful output compare and will
appear at P12 if bit 2 of port 1 data direction register
is set and the OE3 control bit is set. OL VL3 and output level register 3 are cleared during reset.

Bit 3

Input Edge 1 - IEDGl is cleared during reset and
controls which level transition on P20 will trigger a
counter transfer to input capture register 1.
I EDG 1 = 0 transfer on a negative-edge
IEDGl = 1 transfer on a ppsitive-edge
Refer to TIMER CONTROL AND STATUS
REGISTER (TCSR) ($08).

Bit 4

Input Edge 2 - IEDG2 is cleared during reset and
controls which level transition on Pl0 will trigger a
counter transfer to input capture register 2.
IEDG2=0 transfer on a negative-edge
IEDG2 = 1 transfer on a positive-edge

Bit 5

Output Enable 1 - OEl is set during reset and
enables the contents of output level register 1 to be
connected to P21 when bit 1 of port 2 data direction register is set.
OEl = 0 port 2 bit 1 data register output
OEl = 1 output level register 1

Bit 6

Output Enable 2 - OE2 is cleared during reset and
enables the contents of output level register 2 to be
connected to Pll when bit 1 of port 1 data direction register is set.
OE2 = 0 port 1 bit 1 data register output
OE2= 1 output level register 2

Enable Timer Overflow Interrupt - When set, an
IR02 interrupt will be generated when the timer
overflow flag is set; when clear, the interrupt is Inhibited. ETOI is cleared during reset. Refer to
TIMER CONTROL REGISTER 2 (TCR2) ($18)

Bit 3

Enable Output Compare Interrupt 1
When set,
an IR02 interrupt will be generated when output
compare flag 1 is set; when clear, the interrupt is inhibited. EOCll is cleared during reset. Refer to
TIMER CONTROL REGISTER 2 (TCR2) ($18).

Bit 4

Enable Input Capture Interrupt 1 - When set, an
IR02 interrupt will be generated when input capture flag 1 is set; when clear, the interrupt IS inhibited. EICll is cleared during reset. Refer to
TIMER CONTROL REGISTER 2 (TCR2) ($18).

Bit 5

Timer Overflow Flag - The TOF is set when the
counter contains all ones ($FFF F). It is cleared by
reading the TCSR or the TSR (with TOF set) and
the counter high byte ($09), or during reset. Refer
to TIMER STATUS REGISTER (TSR) ($19)

Bit 6

Output Compare Flag 1 - OCFl is set when output
compare register 1 matches the free-running
counter. OCFl is cleared by reading the TCSR or
the TSR (with OCFl set) and then writing to output
compare register 1 ($OB or SOC), or during reset.
Refer to TIMER STATUS REGISTER (TSR) ($19)

3-810

MC68701U4

Bit 7

Output Enable 3 - OE3 is cleared during reset and
enables the contents of output level register 3 to be
connected to P12 when bit 2 of port 1 data direction register IS set
OE3 = 0 port 1 bit 2 data register output
OE3= 1 output level register 3

TIMER CONTROL REGISTER 2 (TCR21 ($181 - Timer
control register 2 is an 8-bit read/write register (except bits 0
and 1) which enable the interrupts associated with the freerunning counter, the output compare registers, and the input
capture registers. In test mode 0, two more bits (clock and
test) are available for checking the timer.

Bit 0

CLOCK - The CLOCK control bit selects which
half of the 16-bit free-running counter (MSB or
LSB) should be clocked with E. The CLOCK bit IS a
read/write bit only in mode 0 and is set dUring
reset.
CLOCK = 0 - Only the eight most significant bits
of the free-running counter run with TEST = O.
CLOCK = 1 - Only the eight least significant bits
of the free-running counter run when
TEST = O.

Bit 1

TEST - the TEST control bit enables the timer test
mode. TEST IS a read/write bit in mode 0 and is set
during reset
TEST = 0 - Timer test mode enabled
a) The timer LS B latch is transparent which
allows the LSB to be read independently
of the MSB.
b) Either the MSB or the LSB of the timer is
clocked by E, as defined by the CLOCK
bit.
TEST= 1 - Timer test mode disabled.

TIMER CONTROL REGISTER 2
(Non-Test Modes)

7

6

543

2

o

IEICI2 I EICI1 I EOCI31 EOCI21 EOCI1 I ETOI

$18

Bits 0-1

Read-Only Bits - When read, these bits return a
value of 1. Refer to TIMER CONTROL REGISTER 2
(Test Model.

Bit 2

Enable Timer Overflow Interrupt - When set, an
IR02 interrupt will be generated when the timer
overflow flag is set; when clear, the Interrupt is inhibited. ETOI is cleared during reset. Refer to
TIMER CONTROL AND STATUS REGISTER
(TCSRI ($081

Bit 3

Enable Output Compare Interrupt 1 - When set,
an I R02 interrupt will be generated when the output compare flag 1 is set; when clear, the interrupt
is inhibited. EOCll is cleared during reset. Refer to
TIMER CONTROL AND STATUS REGISTER
(TCSRI ($081.

Bit 4

Enable Output Compare Interrupt 2 - When set,
an IR02 interrupt will be generated when the output compare flag 2 is set; when clear, the interrupt
is inhibited. EOCI2 is cleared during reset

Bit 5

Enable Output Compare Interrupt 3 - When set,
an IR02 interrupt will be generated when the output compare flag 3 is set; when clear, the interrupt
is inhibited. EOCI3 IS cleared during reset.

Bit 6

Enable Input Capture Interrupt 1 - When set, an
IR02 interrupt will be generated when the input
capture flag 1 IS set; when clear, the interrupt is inhibited. EICll IS cleared during reset. Refer to
TIMER CONTROL AND STATUS REGISTER
(TCSRI ($081

Bit 7

Enable Input Capture Interrupt 2 - When set, an
IR02 interrupt will be generated when the input
capture flag 2 is set; when clear, the interrupt is inhibited. EICI2 is cleared during reset.

The timer test bits (test and clock) allow the free-running
counter to be tested as two separate 8-bit counters to speed
testing.

TIMER CONTROL REGISTER 2
(Test Mode)
76543210
IEICI2 I EICI1 I EOCI31 EOCI21 EOCI1 I ETOI I TEST I CLOCK

I

$18

Bits 2-7 See TIMER CONTROL REGISTER 2 (Non-Test
Modesl. !These bits function the same as In the
non-test modes.)
TIMER STATUS REGISTER (TSRI ($19) - The timer
status register is an 8-blt read-only register which contains
the flags associated with the free-running counter, the output compare registers, and the input capture registers
TIMER STATUS REGISTER
754
IICF2 IICF1

I OCF31

o

3

OCF21 OCF1

I TOF

$19

Bits 0-1 Not used.
Bit 2

Timer Overflow Flag - The TOF IS set when the
counter contains all ones ($FFFF). It IS cleared by
reading the TSR or the TCSR (with TOF set) and
then the counter high byte ($09), or dUring reset.
Refer to TIMER CONTROL AND STATUS
REGISTER (TCSRI ($08)
Output Compare Flag 1 - OCFl IS set when output
compare register 1 matches the free-running
counter. OCFl IS cleared by reading the TSR or the
TCSR (with OCFl set) and then writing to output
compare register 1 ($OB or $OC), or during reset.
Refer to TIMER CONTROL AND STATUS
REGISTER (TCSR) ($08)

Bit 4

Output Compare Flag 2 - OCF2 is set when output
compare register 2 matches the free-running
counter. OCF2 IS cleared by reading the TSR (with
OCF2 set) and then writing to output compare
register 2 ($lA or $lB), or during reset.

Bit 5

Output Compare Flag 3 - OCF3 is set when output
compare register 3 matches the free-running
counter. OCF3 is cleared by reading the TSR (with
OCF3 set) and then writing to output compare
register 3 ($lC or $10), or during reset.

Bit 6

Input Capture Flag 1 - ICFl IS set to indicate that a
proper level transition has occurred; it is cleared by
reading the TSR or the TCSR (with ICFl set) and
the input capture register 1 high byte ($00), or durIng reset. Refer to TIMER CONTROL AND
STATUS REGISTER (TCSR) ($08l.

II

MC68701U4

Bit 7

the required idle string between consecutive messages and
prevent it within messages.

Input Capture Flag 2 - ICF2 is set to indicate that a
proper level transition has occurred; it is cleared by
reading the TSR (with ICF2 set) and the input capture register 2 high byte ($lE), or during reset.

PROGRAMMABLE OPTIONS

The following features of the SCI are programmable:

SERIAL COMMUNICATIONS INTERFACE

• Format: standard mark/space (NRZ) or bi-phase

A full-duplex asynchronous serial communications interface (SCI) is provided with two data formats and a variety of
rates. The SCI transmitter and receiver are functionally independent but use the same data format and bit rate. Serial
data formats include standard mark/space (NRZ) and biphase and both provide one start bit, eight data bits, and one
stop bit. "Baud" and "bit rate" are used synonymously in
the following description.

• Clock: external or internal bit rate clock
• Baud: one of eight per E clock frequency or external
clock ( x 8 desired baud)
• Wake-Up Feature: enabled or disabled
• Interrupt Requests: enabled individually for transmitter
and receiver
• Clock Output: internal bit rate clock enabled or disabled
to P22

WAKE-UP FEATURE

I

SERIAL COMMUNICATIONS REGISTERS

In a typical serial loop mUltiprocessor configuration, the
software protocol will usually identify the addressee(s) at the
beginning of the message. In order to permit uninterested
MPUs to ignore the remainder of the message, wake-up
feature is included whereby all further SCI receiver flag (and
interrupt) processing can be inhibited until its data line goes
idle. An SCI receiver is re-enabled by an idle string of ten
consecutive ones or during reset. Software must provide for

The serial communications interface includes four addressable registers as depicted in Figure 22. It is controlled
by the rate and mode control register and the
transmit/receive control and status register. Data is transmitted and received utilizing a write-only transmit register and a
r8ad-only receive register. The shift registers are not accessible to software.

FIGURE 22 - SCI REGISTERS
Bit 7

I

I

EBE

Rate and Mode Control Register

Bit 0

I Icco I Isso I

I

CCl

SSl

$10

Transmit/Receive Control and Status Register

RDRF IORFE

ITDREI RIE I

RE

I

TIE

TE

I

WU

1$11

Receive Data Register
$12
~--~--~--~--~--~--~--~--~

Port 2

(Not Addressable)
Receive Shift Register

10

Transmit Shift Register
12

Transmit Data Register

3-812

MC68701U4

for P22 is forced to the complement of CCO and
cannot be altered until eCl is cleared. If CCl is
cleared after having been set, its DDR value is
unchanged. Table 7 defines the formats, clock
source, and use of P22.

RATE AND MODE CONTROL REGISTER (RMCR) ($10)
- The rate and mode control register controls the SCI bit
rate, format, clock source, and under certain conditions, the
configuration of P22. The register consists of five write-only
bits which are cleared during reset. The two least significant
bits in conjunction with bit 7 control the bit rate of the internal clock and the remaining two bits control the format and
clock source.

Bits 4-6

Not used.

Bit 7

EBE Enhanced Baud Enable - EBE selects the
standard MC6801 baud rates when clear and the
additional baud rates when set (Table 6). This
bit is cleared by reset and is a write-only control
bit.
EBE = 0 standard MC6801 baud rates
EB E = 1 additional baud rates

RATE AND MODE CONTROL REGISTER

6

I

EBE

x

4

x

x

3

2

1

0

I eel I ceo I 551 I 550 I $10

Bit 1: Bit 0

SS1 :SSO Speed Select - These two bits select
the baud when using the internal clock. Eight
rates may be selected (in conjunction with bit 7)
which are a function of the MCU input frequency. Table 6 lists bit time and rates for three
selected MCU frequencies.

Bit 3: Bit 2

CC1 :CCO Clock Control and Format Select These two bits control the format and select the
serial clock source. If CCl is set, the DDR value

TABLE 6 -

SS1:SS0
E

NOTE
The source of SCI internal bit rate clock is the timer
free-running counter. An MPU write to the counter in
mode 0 can disturb serial operations.

SCI BIT TIMES AND RATES

2.4576 MHz

4.0 MHz

4.9152 MHz

614.4 kHz
Baud
Time

1.0 MHz
Baud
Time

1.2288 MHz
Time
Baud

4fo EBE

If both CCl and CCO are set, an external TTL-compatible
clock must be connected to P22 at eight times (8 x) the
desired bit rate, but not greater than E, with a duty cycle of
50% (± 10%). If CC 1: CCO= 10, the internal bit rate clock is
provided at P22 regardless of the values for TE or R E.

0

0

0

+16

38400.0

261's

62500.0

16.01's

76800.0

13.0 1'S

0

0

1

+ 128

4800.0

208.31's

7812.5

128.01's

9600.0

104.2 I's

0

1

0

+ 1024

600.0

1.67 ms

976.6

1.024 ms

1200.0

833.31's

0

1

1

+4096

150.0

6.67 ms

244.1

4.096 ms

300.0

3.33 ms

1

0

0

+64

9600.0

104.2I's

15625.0

64l's

19200.0

52.01's

1

0

1

+256

2400.0

416.61's

3906.3

2561'S

4800.0

208.31's

1

1

0

+512

1200.0

833.31's

1953.1

5121's

2400.0

416.61's

1

1

1

+2048

300.0

3.33 ms

488.3

2.05 ms

600.0

01.67 ms

External (P22) *
maximum clock rate

76800.0

13.0 I'S

125000.0

8.01's

153600.0

6.51's

* USing

TABLE 7 -

SCI FORMAT AND CLOCK SOURCE CONTROL
Clock
Source

Port 2
Bit 2

Bi-Phase

Internal

Not Used

NRZ

Internal

Not Used

10

NRZ

Internal

Output

11

NRZ

External

Input

CC1:CCO

Format

00
01

3-813

I

MC68701U4

TRANSMIT/RECEIVE CONTROL AND STATUS
REGISTER (TRCSR) ($11) - The transmit/receive control
and status register controls the transmitter, receiver, wakeup feature, and two individual interrupts, and monitors the
status of serial operations. All eight bits are readable while
bits 0 to 4 are also writable. The register is initialized to $20
by RESET.

Bit 6

Overrun Framing Error - If set, ORFE indicates
either an overrun or framing error. An overrun is a
new byte ready to transfer to the receiver data
register with RORF still set. A receiver framing error
has occurred when the stop bit (1) is not found in
the tenth bit time. An overrun can be distinguished
from a framing error by the state of RORF: if RORF
is set, then an overrun has occurred; otherwise, a
framing error has been detected. Data is not
transferred to the receive data register in an overrun condition. Unframed data causing a framing error is transferred to the receive data register.
However, subsequent data transfer is blocked until
the framing error flag is cleared. ORFE is cleared by
reading the TRCSR (with ORFE set) then the
receive data register, or during reset.

Bit 7

Receive Data Register Full - RORF is set when the
input serial shift register is transferred to the receive
data register, or during reset.

TRANSMIT/RECEIVE CONTROL AND STATUS REGISTER

7

6

5

4

IRDRF IORFE ITDRE I RIE

I

3
I RE

2
I TIE

1

0

I TE I

wu

I $11

Bit 0

"Wake-Up" on Idle Line - When set, WU enables
the wake-up function; it is cleared by ten consecutive ones or during reset. WU will not be set if
the line is idle. Refer to WAKE-UP FEATURE.

Bit 1

Transmit Enable - When set, P24 OOR bit is set,
cannot be changed, and will remain set if TE is
subsequently cleared. When TE is changed from
clear to set, the transmitter is connected to P24 and
a preamble of nine consecutive ones is transmitted.
TE is cleared during reset.

Bit 2

Transmit Interrupt Enable - When set, an IR02 is
set; when clear, the interrupt is inhibited. TE is
clea'red during reset.

Bit 3

Receive Enable - When set, the P23 OOR bit is
cleared, cannot be changed, and will remain clear if
RE is subsequently cleared. While RE is set, the SCI
receiver is enabled. RE is cleared during reset.

Bit 4

Receiver Interrupt Enable - When set, an IR02 interrupt is enabled when RDRF and/or ORFE is set;
when clear, the interrupt is inhibited. RIE is cleared
during reset.

Bit 5

Transmit Data Register Empty - TORE is set when
the transmit data register is transferred to the output serial shift register or during reset. It is cleared
by reading the TRCSR (with TORE set) and then
writing to the transmit data register. Additional
data will be transmitted only if TORE has been
cleared.

SERIAL OPERATIONS
The SCI is initialized by writing control bytes first to the
rate and mode control register and then to the
transmit/receive control and status register. When TE is set,
the output of the transmit serial shift register is connected to
P24 and serial output is initiated by transmitting a 9-bit
preamble of ones.
At this point, one of two situations exists: 1) if the transmit
data register is empty (TORE= 1), a continuous string of
ones will be sent indicating an idle line; or 2) if a byte has
been written to the transmit data register (TOR E= 0), it will
be transferred to the output serial shift register (synchronized with the bit rate clock), TO RE will be set, and transmission will begin.
The start bit (0), eight data bits (beginning with bit 0), and
a stop bit (1) will be transmitted. If TORE is still set when the
next byte transfer occurs, ones will be sent until more data is
provided. In bi-phase format, the output toggles at the start
of each bit and at half-bit time when a one is sent. Receive
operation is controlled by RE which configures P23 as an input and enables the receiver. SCI data formats are illustrated
in Figure 23.

FIGURE 23 -

SCI DATA FORMATS

Output
Clock

o

Data

o

o

0

NRZ
Format

Bi-Phase

Format

Idle Start

Bit

0

Data 01001101 ($4D)

3·814

Bit

3

4

6

7

Stop

MC68701U4

to increment like a 16-bit counter causing address lines used
in the expanded modes to increment until the device is reset
These opcodes have no mnemonics.
The coding of the first (or only) byte corresponding to an
executable instruction is sufficient to identify the instruction
and the addressing mode. The hexadecimal equivalents of
the binary codes, which result from the translation of the 82
instructions in all valid modes of addressing, are shown in
Table 8. There are 220 valid machine codes, 34 unassigned
codes, and 2 codes reserved for test purposes.

INSTRUCTION SET
The MC68701 U4 is directly source compatible with the
MC6801 and upward source and object code· compatible
with the MC6800. Execution times of key instructions have
been reduced and several instructions have been added, including a hardware multiply. A list of new operations added
to the MC6800 instruction set is shown in Table 1.
In addition, two special opcodes, 4E and 5E, are provided
for test purposes. These opcodes force the program counter

TABLE 8 OP

MNEM

MODE

-

#

00
01

NOP

INHER

2

1

02
03

MODE

-

#

OP

MNEM

MODE

-

#

OP

MNEM

MODE

-

#

OP

MNEM

MODE

-

#

34

DES

INHER

3

1

68

ASL

INDXD

6

2

9C

CPX

DIR

5

2

3

1

69

ROL

6

2

9D

JSR

5

2

SUBB
CMPB

3
3

2

TXS

DO
D1

DIR

35
36
37

PSHA
PSHB

3
3

1
1

6A

DEC

6

2

9E
9F

LDS
STS

4
4

2
2

S8CB
ADDD
ANDB

2
2

4

D2
D3
D4

3
5

SUBA

3

2

A1

5

1

6B

3

PULX

3

1
1

38

ASLD

5

1

6D

TST

TAP

2

1

39
3A

RTS

06

ABX

3

1

JMP

07

TPA

2

1

3B

RTI

10
4

1

6E
6F

CLR

1

70

NEG

3

2

EXTND

6

3

ANDA

4

2

08

EORB

3

2

BITA
LDAA

4

6
6

3

1

77

ASR

6

3

AB

1

78
79

ASL
ROL

6

3

6

3

AC
AD

2

1

6

3

1

7A
7B

DEC

2
2

1

7C

INC

6

ROLA
DECA

2
2

1
1

7D
7E

TST
JMP

7F

CLR

EXTND

INCA
TSTA

2

1
1

SUBA
CMPA

IMMED

2

80
81
82

SBCA

OC
00

CLC
SEC

2
2

1
1

40
41

OE

CLI

2

1

42

OF

SEI

2

1

43

COMA

2

10
11
12
13
14
15
16
17
18
19
1A
1B
1C

SBA

2

1

44

LSRA

2

CBA

2

1

45
46

RORA

47

4B

ASRA
ASLA

1

49
4A

1

4B

2

STAB

ROR

1

INHER

2

2

76

2

ABA

2

3

6

3
3

SEV

3E
3F

MUL
WAI

OB

2

3

SUBD

D6
D7

LDAB

A3

6

3D

1

INHER

BITB

2

2

COM
LSR

1

2

DAA

D5

4

6

72

3C

3

CLV

4C

2

A2

CMPA
SBCA

4

2

INDXD

73
74
75

3

DEX

TBA

2
2

6

1
1

INX

09
OA

10
9
12
2

SWI
NEGA

1

71

~

2

BO

SUBA

EXTND

4

3

AN DB

6

3

3

B1
B2

CMPA
SBCA

4
4

3
3

BITB
LDAB

4
4

6
2

3
2

B3
B4

SUBD
ANDA

6
4

3

E5
E6
E7

2

3

STAB

4

2

3

E8

EORB

4

2

2

B5

BITA

4

3

ADCB

4

2

2

LDAA

4

3

E9
EA

2
2

DRAB

4

2

STAA

4

3

EB

ADDB

4

2

5

2

5

2

CLRA

2

1

83

SUBD

4

3

50

NEGB

2

1

84

ANDA

2

2

B8

EORA

4

3

EC

LDD

2

2

ADCA

4

3

ED

STD

2

2

B9
BA

ORAA

4

3

LDX

BB
BC

ADDA
CPX

4
6

3
3

EE
EF
FO

STX
SUBB

BD

JSR

6

3

F1

CMPB

3

2

54
55

2
2

COMB
LSRB

3

2

68

RORB

2

1

2

57

ASRB

2

1

8B

ADDA

BCC

3

2

68

ASLB

2

1

CPX

IMMED

25

BCS
BNE
BEQ

3

2

ROLB

2

1

BSR

3

REL
IMMED

3

2
2

59
5A

8C
8D

3

2

DIR

3
3
3
3
3
3
3
3
3
4
4

2

INS

t

30
31
32

33

PULA
PULB

2
2
2
2
2
2

DECB

2

1

8E

5B
5C
50

INCB
TSTB

2

1
1

90

5E
5F

CLRB

60
61

1
1

64

1
1

66
67

LOS

2
INHER
INDXD

COM
LSR

65
ROR
ASR

1

INDXD

INDXD
EXTND

2

2

5

2

5
4

3

4

2
3
3

BE
BF

5

3

F2

S8CB

4

STS

EXTND

5

IMMED

ADDD
AN DB

6

C1

CMPB

2
2

F3
F4

3

SUBB

3
2

6

CO

2

F5

BITB

4
4

3

3

3

C2

SBCB
ADDD

2
4

2

F6

LDAB

4

3

3

F7

STAB

4

3

3
3

2
2

ANDB
BITB

2
2

2

2

F8
F9

EORB
ADCB

4
4

3
3

FA

2

C3
C4
C5

LDS

3

92

SBCA

3

2

C6

LDAB

2

2

aRAB

4

3

2

1

93

2

C7

FB

ADDB

4

3

2

94

SUBD
ANDA

5

6

3

2

C8

EORB

2

2

FC

LDD

5

3

95

BITA

3

2

C9

ADCB

2

2

FD

STD

5

96

LDAA
STAA

3
3

2

CA

ORAB

2

2

FE

LDX

5

3

2

CB

ADDB

2

2

FF

STX

5

3

T
NEG

91

SUBA
CMPA

,

2

3
2

2
2
4

8F

62
63

ORAA

4

CMPB

1

3
3

REL
INHER

JSR

B6
B7

T

BLS

BLE
TSX

AE

4E
4F

23
24

It

6

3

2
2

BGT

2

2

2

2E
2F

2

4
4

ADCA

BLT

4

6
4

89
8A

20

DIR
INDXD

40

2

BPL

STX
SUBB
S8CB

2

BGE

OF

2

ADDD

2

BMI

2

E3
E4

EORA

2B

4
6

E2

88

2C

2

ADDA
CPX

2
2

2

1
1

BVC
BVS

4

1

53

28
29
2A

LDX

2

LDAA

26
27

DE

2

86
87

I

2

5

85

BRN
BHI

LDD
STD

4

EORA
ADCA
ORAA

5

52

22

2
2

4
4

3
4
4

INDXD

51

21

2

3

ADDB

2

LDS
STS

1E
1F
REL

3

aRAB

DB
DC
DD

4
4

AF

10

BRA

09
DA

ADCB

2
2
2
2

STAA

EO
E1

BITA

20

2

3

6

1

08

PSHX

2
2

1

~

DIR
INDXD

2

AO

A4
A5
A6
A7
A8
A9
AA

1

TAB

6C

INC

LSRD

05

04

CPU INSTRUCTION MAP

MNEM

OP

6
6

2

6
6

2
2

2

97
98
99
9A
9B

EORA

3
3

2
2

CC
CD

lOD

ADCA
ORAA
ADDA

3
3

2
2

CE
CF

LDX

NOTES:
1. Addressing Modes
INHER ... Inherent
INDXD ... Indexed
IMMED ... Immediate
EXTND ... Extended DIR ... Direct
REL ... Relative
2. Unassigned opcodes are indicated by "e" and should not be executed.
3. Codes marked by "1" force the PC to function as a 16-bit counter.

3-815

IMMED

3

3

3

3

EXTND

* UNDEFINED OP CODE

3

I

MC68701U4

DIRECT ADDRESSING - The least significant byte of the
operand address is contained in the second byte of the instruction and the most Significant byte is assumed to be $00.
Direct addressing allows the user to access $00 through $FF
using two byte instructions and execution time is reduced by
eliminating the additional memory access. In most applications, the 256-byte area is reserved for freqLlently referenced
data.

PROGRAMMING MODEL
A programming model for the MC68701 U4 is shown in
Figure 8. Accumulator A can be concatenated with accumulator B and jointly referred to as accumulator D where
A is the most significant byte. Any operation which modifies
the double accumulator will also modify accumulators A
and/or B. Other registers are defined as f.ollows:
PROGRAM COUNTER - The program counter is a 16-bit
'register which always points to the next instruction.

EXTENDED ADDRESSING - The second and third bytes
of the instruction contain the absolute address of the
operand. These are three byte instructions.

STACK POINTER - The stack pointer is a 16-bit register
which contains the address of the next available location in a
pushdown/pullup (LIFO) queue. The stack resides in
random-access memory at a location defined by the programmer.

I

INDEXED ADDRESSING - The unsigned offset contained in the second byte of the instruction is added with
carry to the index register and is used to reference memory
without changing the index register. These are two byte instructions.

INDEX REGISTER - The index register is a 16-bit register
which can be used to store data or provide an address for the
indexed mode of addressing.

INHERENT ADDRESSING - The operand(s) is a register
and no memory reference is required. These are single byte
instructions.

ACCUMULATORS - The MPU contains two 8-bit accumulators, A and B, which are used to store operands and
results from the arithmetic logic unit (ALU). They can also be
concatenated and referred to as the D (double) accumulator.

RELATIVE ADDRESSING - Relative addressing is used
only for branch instructions. If the branch condition is true,
the program counter is overwritten with the sum of a Signed
single byte displacement in the second byte of the instruction and the current program counter. This provides a
branch range of - 126 to + 129 bytes from the first byte of
the instruction. These are two byte instructions.

CONDITION CODE REGISTER - The condition code
register indicates the results of an instruction and includes
the following five condition bits: negative (N), zero (Z),
overflow (V), carry/borrow from MSB (e), and half carry
from bit 3 (H). These bits are testable by the conditional
branch instructions. Bit 4 is the interrupt mask (I bit) and inhibits all maskable interrupts when set. The two unused bits,
B6 and B7, are read as ones.

SUMMARY OF CYCLE-BY-CYCLE OPERATION
ADDRESSING MODES
Six addressing modes can be used to reference memory.
A summary of addressing modes for all instructions is
presented in Tables 9,10,11, and 12 where execution times
are provided in E cycles. Instruction execution times are
summarized in Table 13. With an input frequency of 4 MHz,
one E cycle is equivalent to one microsecond. A cycle-bycycle description of bus activity for each instruction is provided in Table 14 and descriptions of selected instructions
are shown in Figure 24.

Table 14 provides a detailed description of the information
present on the address bus, data bus, and the read/write
(R/W) line during each cycle of each instruction.
The information is useful in comparing actual with expected results during debug of both software and hardware
as the program is executed. The information is categorized in
groups according to addressing mode and number of cycles
per instruction. In general, instructions with the same addressing mode and number of cycles execute in the same
manner. Exceptions are indicated in the table.
Note that during MPU reads of internal locations, the
resultant value will not appear on the external data bus except in mode O. "High order" byte refers to the most significant byte of a 16-bit value. During unused bus cycles, the address bus is forced to $FFFF and R/W is high.

IMMEDIATE ADDRESSING - The operand or "immediate byte(s)" is contained in the following byte(s) of the
instruction where the number of bytes matches the size of
the register. These are two or three byte instructions.

3-816

MC68701U4

TABLE 9 -

INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS
Condition Codes
Immed

Pointer Operations

# Op -

MNEM Op -

Extend

Index

Direct

# Op 2 AC 6

Inherent

# Op

# Op 2 BC 6

Boolean/
Arithmetic Operation

-

#

3

1 X-1-X

CPX

Decrement Index Register

DEX

Decrement Stack Pointer

DES

34

3

1 SP-1-SP

Increment Index Register

INX

08

3

1 X+1-X

31

3

1 1 SP+1-SP

3 9C

5

3

X-M:M+1
09

Increment Stack Pointer

INS

Load Index Register

LOX

CE 3

3 DE 4

Load Stack POinter

LOS

8E

3 9E

Store Index Register
Store Stack Pointer

3

M -XH,IM+ ll-XL

4

2 FE 5
2 BE 5

3

M-SPH,IM+11-SPL

STX

OF 4

2 EF 5

2 FF 5

3

XH-M,XL -IM+lI

STS

9F

2 AF 5

2 BF 5

3

SPH-M,SPL -IM+lI

4

3

2

I

N

Z V C

1

0

·1 ·· ··
· · · ·1 ·· ·

2 EE 5
2 AE 5

3

4

H

1 1 1 1
1

Compare Index Register

8C 4

5

1 X-1-SP

Index Reg -

Stack POinter

TXS

35

3

Stack Pntr -

Index Register

TSX

30

3

I

SP+l-X

Add

ABX

3A 3

1

B+X-X

Push Data

PSHX

3C

4

1 XL XH -

Pull Data

PULX

38

5

1 SP+ l-SP,MSP-XH
SP+ l-SP,MSP-XL

MSp,SP-1 MSp,SP-l -

SP
SP

··

R

··
·· · ···
· · · ··
···
··
1
1

R

I

R

R

TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 1 of 2)
Condition Codes
Accumulator and
Memory Operations

Immed

-

Direct

Extend

Index

Inher

Add Accumulators

ABA

# Op 1B 2

Add B to X

ABX

3A 3

Add with Carry

MNEM Op

ADCA 89

2

ADCB C9 2

2

# Op -

# Op -

2 A9 4

3

B+M+C-B

2 AB 4

2 BB 4

3

A+M-A

2 FB 4
2 F3 6

3

B+M-A

3

D+M:M+1-D

ADDB CB 2

2 DB 3

2 EB 4

ADDD C3 4

3 03 5

2 E3 6

Shift Left Double
Shift Right, Arithmetic

Bit Test

2

1

0

N

Z

V

C

1 1 1 1

··

2

2 94 3

2 A4 4

A·M-A

R

2 E4 4

2 B4 4
2 F4 4

3

2 D4 3

3

B·M-B

R

68

2 78 6

3

ANDA 84
ASL

6

ASLA

48

2

1

ASLB

58

2

1

05

3

1

ASRA

47

2

1

ASRB

57

2

1

ASLD
ASR

BITA

Compare Accumulators

CBA

Clear

CLR

1's Complement

3

I

ANDB C4 2

BITB

Compare

A+M+C-A

2 B9 4
2 F9 4

Add Double

4

H

· ·· I I I· I
·

1 oo:B+X-X

3

5

1

1 A+B-A

2 E9 4

ADDA 8B

Shift Left, Arithmetic

#

2 99 3
2 09 3
2 9B 3

Add

And

# Op -

Boolean
Expression

67

2
C5 2
85

2 95 3
2 05 3

6

2 77 6

3

b7

b7

2 B5 4

3

A·M

F5

4

3

B·M

6F

2 7F 6

3

11
6

2

1 A-B
oo-M

CLRA

4F

2

1 oo-A

CLRB

5F

2

1 oo-B

CMPA 81

2

2 91

CMPB C1

2

2 01 3

COM

3

2 A1

4

2 E1 4
63 6

4

3

A-M

2 F1 4
2 73 6

3

B-M

3

M-M

2 B1

COMA

43

2

1 A-A

COMB

53

2

1 B-B

3·817

-0

bO

qilli IIII-@)

2 A5 4
2 E5 4

2

-

@]-illlllill

bO

··

·

·· ·
··· ··· 1t tt tt tt
·· ·· t t ·
t
···
I I

R

R

I I

I

R

S

R

R

R

S

R

R

R

S

R

R

·ttI
·· ·· 1t 1t t
· tt

· ·· t

t

I

t

R

S

R

S

R

S

I

MC68701U4

TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 2 of 2)
Condition Codes
Accumulator and
Memory Operations

MNEM Op -

Decimal Adjust, A

DAA

Decrement

DEC

Exclusive OR
Increment

Load Accumulators

I

Immed

Direct

Extend

Index

# Op -

Inher

# Op -

# Op -

# Op 19 2

6A 6

2 7A 6

3
4A 2

1 A-1--A
1 B-1--B

EORA 88

2

2 98 3

2 A8 4

2 B8 4

3

A6lM--A

EORB C8 2

2 D8 3

2 E8 4

2 F8 4

3

B6lM--B

3

M+1--M

INC

6C

6

2 7C

6

INCA

4C

2

1 A+1--A

INCB

5C

2

1

2 96 3

2 A6 4

2 B6 4

3

M--A

LDAB C6 2

2 D6 3

2 E6 4

2 F6 4

3

M--B

3 DC 4

2 EC 5

2 FC 5

3

M:M+1--D

6

2 78 6

3

CC 3

68

LSLA

48

2

1

LSLB

58 2

1

05

3

2

44

2

1

LSLD
LSR

64

6

2 74 6

Inclusive OR
Push Data
Pull Data
Rotate Left

Rotate Right

Subtract Accumulator
Subtract with Carry
Store Accumulators

Subtract
Subtract Double
Transfer Accumulator
Test, Zero or Minus

b7

b7

1

LSRD

04

1

MUL

3D 10

1 AxB-D

NEGA

40

2

1 00- A -- A

NEGB

50

2

1 OO-B--B

NOP

01

2

1 PC+ 1-- PC

ORAA 8A

60

6

2

70

6

2 9A 3

2 AA 4

2 BA 4

3

A+M--A

ORAB CA 2

2 DA 3

2 EA 4

2 FA 4

3

B+M--B

PSHA

36

3

PSHB

37

3

1 B -- Stack

PULA

32

4

1

Stack -- A

PULB

33

4

1

Stack -- B

ROLA

49

2

1

ROLB

59

2

1

69

6

66 6

ROR

2

2

79

76

6

6

@].-111111111-§
b7

1

2

1

SBA

10

2

1 A-B--A

2

2 D2 3

92

3

2

B2 4

3

2

4

2

F2

4

3

B-M-C--B

2 A7 4

2

B7 4

3

A--M

2

F7

4

3

B--M

2 FD 5

3

D--M:M+1

2 AO 4

2 BO 4

3

A-M--A

2

EO 4

2

FO

4

3

B- M--B

2 A3 6

2

B3 6

3

D-M:M+1--D

STAA

97

STAB

D7 3

2

STD

DO 4

2 ED 5

SUBA 80

2

2

90

3

3

SUBB CO 2

2 DO 3

SUBD 83

3

4

93

5

b7

2 A2 4
E2
E7

4

A-M-C--A

TAB

16

2

1 A--B

TBA

17

2

1

TST

60 6

2 7D

6

B--A
M-OO

3

TSTA

4D

2

1 A-OO

TSTB

50

2

1

The condition code register notes are listed after Table 12.

bO

@-IIIIIIII~@]

2

56

2

·· ·· tt tt tt t
t t t
··· ··· tt tt t ···
·· ·· tt tt t ··
t t t
··· ··· tt tt t ·
·· ·· tt tt
·· tt tt tt tt
t t t t
·· ··· t tt tt tt
·· ·· tt tt tt
· . ·t ·t tt
·
·· ·· tt tt tt tt
t t t t
·
··· ··· tt ·tt ·
·· ·· ·· ·· ·
·· ·· · ··
·· ·· tt tt tt tt
·· ·· tt tt tt tt
·· ·· tt tt tt tt
·· · tt tt tt tt
·· ·· tt tt t ·t
t t
··· ··· tt tt t ··t
·· ·· tt tt tt tt
·· ·· 1t tt ··
·· ·· tt tt
··t t
R
R
R

R

3
46

2

C

R

3

RORB

SBCB C2

bO

1 A -- Stack

RORA

SBCA 82

0

V

R

2

ROL

+-0

bO

OO-M--M

3

1

Z

R

-IIIIIIIII--@j

54 2

NEG

2

N

R

LSRB

3

3

I

R

@J+1lliTllll
o

4

H

R

3

LSRA

5

R

B+1--B

2

LDAA 86

LSL

No Operation

M-1--M

5A 2

Logical Shift, Left

2's Complement INegatel

1 Adj binary sum to BCD

DECA

LDD

Multiply

#

DECB

Load Double

Shift Right, Logical

Boolean
Expression

B-OO

bO

R
R

R

R
R
R

R

R

R

R

R

MC68701U4

TABLE 11 - JUMP AND BRANCH INSTRUCTIONS
Condition Code Reg.
Operations

Direct
Relative
Index
Extend
Inherent
MNEM Op
# Op - # Op - # Op - # Op - #

-

Branch Always

BRA

20

3

2

Branch Never

BRN

21

3

2

None

Branch II Carry Clear

BCC

24

3

2

C=o

None

Branch II Carry Set

BCS

25

3

2

C=l

Branch 11= Zero

BEQ

27

3

2

Z=l

B ranch II 2: Zero

BGE

2C

3

2

N e V=O

Branch II >Zero

BGT

2E

3

2

Z+INeV)=O

2

C+Z=o

Branch II Higher

BHI

22

3

Branch II Higher or Same

BHS

24

3

C=o

B ranch II :5 Zero

BlE

2F

3

Z+INeV)=l

Branch II Carry Set

BlO

25

3

2

C=l

Branch II lower Or Same

BlS

23

3

2

C+Z=l

2

Branch II 

E

IV

"ii

••
•
••
••
•
•

INX
JMP
JSR
LOA
LDD
LOS
LOX
LSL
LSLD
LSR
LSRD
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI

3
3
3
3
3
3
3

•3
3
3
3
3
3
3
3
3
6
3
3

•

•2
•2
2
3
3

••3

3-820

'tl
Q)

t;

f

'tl

c:

!)(

'tl
Q)
)(

Qj
~

.E

i5

w

.=

•
••

••

•3

•3

5

6

6

3
4
4
4

4

4

5
5
5
6

5
5
5
6

2
3
3
3

•
•••
••
•
••
•
2

•
•

••
•
•
••
•••
••
•
•••
••
••
•
2

2
4

••
••
••
•3
•••
•••
•••
3
••
•3
4
4
4

3
5

•
••
•••
•
••

•
••
•
•
••
•
••
•
••
•
6

6

4

6
6

4

4
5
5
5
4
6

•
•••
•
•
••
6

E
Q)

Q)

"0

•
••
•
••
••
••
6

6
4

6
6

•4

••

•

4
5
5
5
4
6

••
••
•6
•
••

.=

Q)

>

";;

IV

"ii

3

••
•
••
•

2
3
2
3
10
2
2

•

•
3

4
4

5
2
2
10
5
2

•2
2
2

••
••
••

12
2
2
2
2
2
3
3
9

•

MC68701U4

TABLE 14 -

Address Mode and
Instructions

R/W
Address Bus

IMMEDIATE
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

CYCLE-BY-CYCLE OPERATION (Sheet 1 of 5)

2

,
2

LDS
LOX
LDD

3

CPX
SUBD
ADDD

4

1
2

3
1
2

3
4

Data Bus

Line

Opcode Address
Opcode Address + ,

,,

Opcode
Operand Data

Opcode Address
Opcode Address+ 1
Opcode Address+2

1
1
1

Opcode
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Opcode Address
Opcode Address+ 1
Opcode Address+2
Address Bus FFFF

1
1

1
1

Opcode
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address+ 1
Address of Operand

1
1
1

Opcode
Address of Operand
Operand Data

Opcode Address
Opcode Address+ 1
Destination Address

1
1

0

Opcode
Destination Address
Data from Accumulator

Opcode Address
Opcode Address+ 1
Address of Operand
Operand Address + 1

1
1
1
1

Opcode
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Opcode Address
Opcode Address + 1
Address of Operand
Address of Operand + 1

1
1

0
0

Opcode
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)

Opcode Address
Opcode Address + 1
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1

Opcode
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Subroutine Address
Stack Pointer
Stack Pointer-l

1
1
1

Opcode
Irrelevant Data
First Subroutine Opcode
Return Address (Low Order Byte)
Return Address (High Order Byte)

DIRECT
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

3

1
2

3

STA

3

LDS
LDX
LDD

4

STS
STX
STD

4

CPX
SUBD
ADDD

5

JSR

5

1
2

3
1
2

3
4
1
2

3
4
1
2

3
4
5
1
2

3
4
5

0
0

3-821

•

MC68701U4

TABLE 14 -

CYCLE-BY-CYCLE OPERATION (Sheet 2 of 5)

R/W

Address Mode and
Instructions

Address Bus

Line

Data Bus

EXTENDED

3

JMP

1
2

3
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

4

4

STA

1
2

3
4
1
2

3
4

I

LOS
LOX
LOD

5

STS
STX
STD

5

ASL
ASR
CLR
COM
DEC
INC

1
2

3
4
5
1
2

3
4
5
LSR
NEG
ROL
ROR
TST*

6

1
2

3
4

5
6

CPX
SUBD
AODD

6

JSR

6

1
2

3
4
5
6
1
2

3
4

5
6

Opcode Address
Opcode Address+ 1
Opcode Address + 2

1
1
1

Opcode
Jump Address (High Order Byte)
Jump Address I Low Order Byte)

Opcode Address
Opcode Address+ 1
Opcode Address+ 2
Address of Operand

1
1
1
1

Opcode
Address of Operand
Address of Operand ILow Order Byte)
Operand Data

Opcode Address
Opcode Address + 1
Opcode Address + 2
Operand Destination Address

1
1
1

0

Opcode
Destination Address IHigh Order Byte)
Destination Address I Low Order Byte)
Data from Accumulator

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand
Address of Operand + 1

1
1
1
1
1

Opcode
Address
Address
Operand
Operand

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand
Address of Operand + 1

1
1
1

Opcode
Address of Operand IHigh Order Byte)
Address of Operand I Low Order Byte)
Operand Data I High Order Byte)
Operand Data ILow Order Byte)

0
0

of Operand IHigh Order Byte)
of Operand ILow Order Byte)
Data I High Order Byte)
Data ILow Order Byte)

Opcode Address
Opcode Address + 1.
Opcode Address + 2
Address of Operand
Address Bus FFFF
Address of Operand

0

Opcode
Address of Operand IHigh Order Byte)
Address of Operand I Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data

Opcode Address
Opcode Address + 1
Opcode Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1
1

Opcode
Operand Address IHigh Order Byte)
Operand Address I Low Order Byte)
Operand Data IHigh Order Byte)
Operand Data ILow Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Opcode Address + 2
Subroutine Starting Address
S tac~, Poi nter
S lock Pointer - 1

1
1
1
1

Opcode
Address of Subroutine IHigh Order Byte)
Address of Subroutine I Low Order Byte)
Opcode of Next Instruction
Return Address I Low Order Byte)
Return Address IHigh Order Byte)

1
1
1
1
1

0
0

* TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus= $FFFF.

3-822

MC68701U4

TABLE 14 -

CYCLE-BY-CYCLE OPERATION (Sheet 3 of 5)

R/W

Address Mode and
Instructions

Address Bus

Line

Data Bus

INDEXED

3

JMP

1

2
3
ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB

4

4

STA

1

2
3
4
1

2
3
4
LDS
LDX
LDD

5

STS
STX
STD

5

ASL
ASR
CLR
COM
DEC
INC
CPX
SUBD
ADDD

JSR

1

2
3
4
5
1

2
3
4
5
LSR
NEG
ROL
ROR
TS1*

6

1

2
3
4
5
6
6

1

2
3
4
5
6
6

1
2

3
4
5
6

Opcode Address
Opcode Address+ 1
Address Bus FFFF

1
1
1

Opcode
Offset
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset

1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data

Opcode Address
Opcode Address+ 1
Address Bus FFFF
Index Register Plus Offset

1
1
1

0

Opcode
Offset
Low Byte of Restart Vector
Operand Data

Opcode Address
Opcode Address+ 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data (High Order By tel
Operand Data (Low Order Byte)

Opcode Address
Opcode Address+ 1
Address Bus FFFF
Index Register Plus Offset
I ndex Register Plus Offset + 1

1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Opcode Address
Opcode Address+ 1
Address Bus FFFF
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset

0
0
1
1
1
1
1

0

Opcode
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data

Opcode Address
Opcode Address+ 1
Address Bus FFFF
Index Register+ Offset
I ndex Register + Offset + 1
Address Bus FFFF

1
1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address+ 1
Address Bus FFFF
Index Register+ Offset
Stack Pointer
Stack Pointer-l

1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
First Subroutine Opcode
Return Address (Low Order Byte)
Return Address (High Order Byte)

0
0

*TST does not perform the write cycle during the sixth cycle The sixth cycle is another address bus= $FFFF

3-823

I

MC68701U4

TABLE 14 Address Mode and
Instructions

CYCLE-BY-CYCLE OPERATION (Sheet 4 of 5)

R/W
Address Bus

Line

Data Bus

INHERENT
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM

I

DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA

2

1
2

Opcode Address
Opcode Address+ 1

1
1

Opcode
Opcode of Next Instruction

ABX

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Ir.relevant Data
Low Byte of Restart Vector

ASLD
LSRD

3

1
2
3

Opcode Address
Opcode Address+ 1
Address Bus FFFF

1
1
1

Opcode
Irrelevant Data
Low Byte of Restart Vector

DES
INS

3

1
2
3

Opcode Address
Opcode Address + 1
Previous Stack Pointer Contents

1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data

INX
DEX

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Opcode of Next Instruction
Low Byte of Restart Vector

PSHA
PSHB

3

1
2
3

Opcode Address
Opcode Address + 1
Stack Pointer

1
1

0

Opcode
Opcode of Next Instruction
Accumulator Data

TSX

3

1
2
3

Opcode Address
Opcode Address + 1
Stack Pointer

1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data

TXS

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Opcode of Next Instruction
Low Byte of Restart Vector

PULA
PULB

4

1
2
3
4

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1

1
1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data
Operand Data from Stack

PSHX

4

1
2
3
4

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer-1

1
1

0
0

Opcode
Irrelevant Data
Index Register (Low Order Byte)
Index Register (High Order Byte)

1
2
3
4
5
1
2
3
4
5

Opcode Address
Opcode Address+ 1
Stack Pointer
Stack Pointer+ 1
Stack Pointer + 2
Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1
Stack Pointer+ 2

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)
Opcode
Irrelevant Data
Irrelevant Data
Address of Next Instruction (High Order Byte)
Address of Next Instruction (Low Order Byte)

1
2
3
4
5
6
7

Opcode Address
Opcode Address+ 1
Stack Pointer
Stack Pointer-1
Stack Pointer- 2
Stack Pointer - 3
Stack Pointer-4
Stack Pointer- 5
Stack Pointer-6

1
1

Opcode
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condition Code Register

SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST

PULX

5

RTS

5

WAI

9

8
9

0
0
0
0
0
0
0

3-824

MC68701U4

TABLE 14 Address Mode and
Instructions

CYCLE-BY-CYCLE OPERATION (Sheet 5 of 5)

R/W
Line

Address Bus

Data Bus

INHERENT (Continued)
Opcode Address
Opcode Address + 1
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart

Opcode Address
Opcode Address+ 1
Stack Pointer
Stack Pointer+ 1
Stack Pointer+2
Stack Pointer+3
Stack Pointer+4
Stack Pointer+ 5
Stack Pointer+ 6
Stack Pointer+ 7

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Irrelevant Data
Contents of Condition Code Register from Stack
Contents of Accumulator B from Stack
Contents of Accumulator A from Stack
Index Register from Stack (High Order Byte)
Index Register from Stack (Low Order Byte)
Next Instruction Address from Stack (High Order Byte)
Next Instruction Address from Stack (Low Order Byte)

1
1
0

11
12

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer-1
Stack Pointer - 2
Stack Pointer- 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer-6
Stack Pointer - 7
Vector Address FFFA (Hex)
Vector Address FFFB (Hex)

0
0
0
0
1
1
1

Opcode
Irrelevant Data
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condition Code Register
Irrelevant Data
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)

3

1
2
3

Opcode Address
Opcode Address + 1
Address Buss FFFF

1
1
1

Opcode
Branch Offset
Low Byte of Restart Vector

6

1
2
3
4

Opcode Address
Opcode Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer-1

1
1
1
1

Opcode
Branch Offset
Low Byte of Restart Vector
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

10

MUL

1
2
3
4
5
6
7

8
9
10
10

RTI

1
2
3
4
5

6
7

8
9
10
SWI

12

1
2
3
4
5
6
7

8
9
10

0
0

Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector

RELATIVE
BCC
BCS
BEQ
BGE
BGT
BSR

BHT
BLE
BLS
BLT
BMI

BNE BLO
BPL BHS
BRA BRN
BVC
BVS

5
6

3-825

0
0

I

iii
s:

(')

en
CO

"

C

~

FIGURE 24 - SPECIAL OPERATIONS

C

~

JSR, Jump to Subroutine

SP

SWI, Software Interrupt

I¢~

Main Program

E.C

$90; JSR
Direct

{

RTN

INOXO

{

w

AcmltrA

SP-3

Index Register IXH)

e>-'SHffi
~

K; Offset
Next Main Instr.

Stack

SP-l

RTNH

SP

RTNL

WAI, Wait for Interrupt

(J)

EXTNO

I

$3E;WAI
RTN

~

RTNH

SP

RTNL
-

~

$3B; RTI

Stack

SP
SP+l

Condition Code
AcmltrB

SL; Subr. Addr

SP+3

AcmltrA

Next Main Inst

SP+4

Index Register (XH)

SP+5

Index Register (XL)

SP+6

RTNH

SP+ 7

RTNL

~

± K; Offset
Next Main Instr

Subroutine
[$39;1115

U

Stack

¢~ SP-2~

$80; BSR

RTN I

'"''''"'''''''''I¢

Index Register (XL)

SP+2

Main Program
~

Ie>

SP-2
SP-l

SH = Subr. Addr.

BSR, Branch To Subroutine

~

I

$BO; JSR

RTN

RTS, Return from Subroutine

Main Program

E£;

'

Main Program

~

AcmltrB

K; Direct Address

RTI Return from Interrupt

00
I\)

Condition Code

SP-5
SP-4

$AO;JSR

RTN

SP-7
SP-6

Next Main Instr.

Main Program

E.C

Stack

I

SP-l

RTNH

SP

RTNL

~

¢

Stack

SP~

-+

SP+ 1

RTNH

SP+2

RTNL

Legend:
RTN; Address of next instruction in Main Program to be executed upon return from subroutine
RTNH; Most significant byte of Return Address
RTNL; Least significant byte of Return Address
- ; Stack Pointer After Execution
K; 8-bit Unsigned Value

-+
JMP, Jump

INOXO

ES;

I

PC

X+ K [

Main Program
$7E;JMP
K H ; Next Address
KL; Next Address

'''e"ood {
Next Instruction

[
K [

Next Instruction

®

MC68705P3

MOTOROLA

Advance Inf'orIllation
8-BIT EPROM MICROCOMPUTER UNIT
The MC68705P3 Microcomputer Unit (MCU) is an EPROM member
of the M6805 Family of low-cost single-chip microcomputers. The user
programmable EPROM allows program changes and lower volume
applications in comparison to the factory mask programmable versions.
The EPROM versions also reduce the development costs and turnaround time for prototype evaluation of the mask ROM versions. This
8-bit microcomputer contains a CPU, on-chip CLOCK, EPROM,
bootstrap ROM, RAM, I/O, and a TIMER.
Because of these features, the MC68705P3 offers the user an
economical means of designing an M6805 Family MCU into his system,
either as a prototype evaluation, as a low-volume production run, or a
pilot production run.

HMOS
(HIGH-DENSITY, N-CHANNEL
DEPLETION LOAD,
5 V EPROM PROCESS)

8-BIT EPROM
MICROCOMPUTER

I

HARDWARE FEATURES:

•

8-Bit Architecture

•
•
•
•

112 bytes of RAM
Memory Mapped I/O
1804 Bytes of User EPROM
Internal 8-Bit Timer with 7-Bit Prescaler

S SUFFIX
CERDIP PACKAGE
ALSO AVAILABLE

• Programmable Prescaler
• Programmable Timer Input Modes

PIN ASSIGNMENT

• External Timer Interrupt
•

Vectored Interrupts -

•

Zero-Cross Detection on INT Input

External, Timer, and Software

•

20 TTL/CMOS Compatible Bidirectional I/O Lines (8 Lines are
LED Compatible)

•
•

On-Chip Generator
Master and Power-On Reset

•

Complete Development System Support on EXORciser

INT

PA7

Vec

PA6

EXTAL

PA5
PA4

•

Emulates the MC6805P2 and MC6805P4 (Except for VSB)

•

Bootstrap Program in ROM Simplifies EPROM Programming

SOFTWARE FEATURES:

•
•

RESET

VSS

PA3
TIMER

PA2

PCO

PAl

PCl

PAO

PC2

PB7

PBO

PB5

Similar to M6800 Family
Byte Efficient Instruction Set

PB6

•
•
•
•

Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handling

•
•

Versatile Index Register
Powerful Indexed Addressing for Tables

•
•
•

Full Set of Conditional Branches
Memory Usable as Registers/ Flags
Single Instruction Memory Examine/Change

•
•

10 Powerful Addressing Modes
All Addressing Modes Apply to EPROM, RAM, and I/O

PB4

PBl

PB3

GENERIC INFORMATION
(1= 1.0 MHz, T A = to 70°C)

a

Package Type

ThiS document contams Information on a new product Specifications and Information herein
are sublect to change Without notice

3-827

Generic Number

Ceramic
L Suffix

MC68705P3L

Cerdip
S Suffix

MC68705P3S

MC68705P3

BLOCK DIAGRAM
RESET

INT

Vpp

TIMER

Data
Dir
Reg

Port
B
Reg

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

Data
Dir
Reg

Port
C
Reg

PCO
PCl
PC2
PC3

Accumulator
A

CPU
Control

Index
Register

I

Port
A
1/0
Lines

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7

Port
A
Reg

X
Condition
Code
Register CC

Data
Dir
Reg

Stack
Pointer

115 X 8
Bootstrap ROM

8

Port
C
1/0
lines

CPU
SP

Program
Counter
High PCH

1804 X 8
EPROM

Port
B
1/0
lines

AlU

Program
Counter
low PCl

MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage
EPROM Programming Voltage (Vpp Pin)
TIMER Pin
Normal Mode
Bootstrap Programming Mode
All Others
Operating Temperature Range
Storage Temperature Range
Junction Temperature

Symbol

Value

Unit

VCC

-0.3 to + 7.0

V

Vpp

- 0.3 to + 22.0

V

Vin
Vin
Vin

-0.3 to + 7.0
-0.3 to + 15.0
-0.3 to + 7.0

V
V
V

TA
Tstg
TJ

-55 to + 150

o to

+ 70

+150

°c
°c
°c

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS oS (Vin or Vout) oS VCC
Reliability of operation is enhanced if unused Inputs are tied to an appropriate logic voltage level
(e.g., either VSS or VCC).

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Ceramic Package
POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °c can be obtained from:
(1)

T J = T A + (PD-8JA)
Where:
T A = Ambient Temperature, °c
8JA= Package Thermal Resistance, Junction-to-Ambient. °C/W
PD= PINT+ PPORT
PINT= ICC x VCC, Watts -

Chip Internal Power

PPORT= Port Power Dissipation, Watts -

User Determined

For most applications PPORT2 signal. The maximum frequency
of a signal that can be recognized by the TIMER pin logic is
dependent on the parameter labeled tWL, tWH· The pin
logic that recognizes the high state on the pin must also
recognize the low state on the pin in order to "re-arm" the
internal logic. Therefore, the period can be calculated as
follows: (assumes 50/50 duty cycle for a given period)

.
tcyc x 2 + 250 ns = period =

II

1
freq

The period is not simply tWL + tWH· This computation is
allowable, but it does reduce the maximum allowable frequency by defining an unnecessarily longer period (250 ns
twice).
When the cJ>2 signal is used as the source, it can be gated
by an input applied to the TIMER pin allowing the user to
easily perform pUlse-width measurements. (Note: When the
MaR TOPT bit is set and the CLS bit is clear, an ungated cJ>2
clock input is obtained by tying the TIMER pin to VCC.) The
source of the clock input is selected via the TCR or the MaR
as described later.
A prescaler option can be applied to the clock input that
extends the timing interval up to a maximum of 128 counts
before decrementing the counter. This prescaling option
selects one of eight outputs on the 7-bit binary divider; one
output bypasses prescaling. To avoid truncation errors, the
prescaler is cleared when bit b3 of the TCR is written to a
logic ''1'', when in the software controlled mode (TOPT = 0,
more on these modes in later paragraphs); however, TCR bit
b3 reads as a logic "0" when TOPT = 0 and as a "1" when
TOPT = 1 to ensure proper operation with read-modify-write
instructions (bit set and clear for example).
At Reset, the prescaler and counter are initialized to an all
"1s" condition; the Timer Interrupt Request bit (TCR, b7) is
cleared and the Timer Interrupt Request mask (TCR, b6) is
set. TCR bits bO, b1, b2, b4, and b5 are initialized by the corresponding Mask Option Register (MaR) bits at Reset. They
are then software selectable after Reset if TOPT = O.
Note that the timer block diagram in Figure 7 reflects two
separate timer control configurations: a) software controlled
mode via the Timer Control Register (TCR), and b) MaR
controlled mode to emulate a mask ROM version with the
Mask Option Register. In the software controlled mode, all
TCR bits are read/write, except bit b3 which is write-only
(always reads as a logic "0"). In the MaR controlled mode,
TCR bits b7 and b6 are read/write, the other six have no effect on a write and read as logic "1s". The two configurations provide the user with the capability to freely select
timer options as well as accurately emulate the MC6805P2
and MC6805P4 mask ROM version. In the following paragraphs refer to Figure 9 as well as the TIMER CONTROL
REGISTER and MASK OPTIONS sections.
The TOPT (Timer Option) bit (b6) in the Mask Option
Register is EPROM programmed to a logical "0" to select the
software controlled mode, which is described first. TCR bits
b5, b4, b3, b2, b1, and bO give the program direct control of
the prescaler and input selection options.
The Timer Prescaler input (fpIN) can be configured for
three different operating modes, plus a disable mode,
depending upon the value written to TCR control bits b4 and
b5 (TIE and TIN).
When the TIE and TIN bits are programmed to "0", the
timer input is from the internal clock (cJ>2) and TIMER input

pin is disabled. The internal clock mode can be used for
periodic interrupt generation as well as a reference for frequency and event measurement.
When TIE= 1 and TIN=O, the internal clock and the
TIMER input pin Signals are ANDed to form the timer input
fPIN. This mode can be used to measure external pulse
widths. The external pulse Simply gates in the internal clock
for the duration of the pulse. The accuracy of the count in
this mode is ± one count.
When TIE = 0 and TIN = 1, no fplN input is applied to the
prescaler and the timer is disabled.
When TIE and TIN are both programmed to a "1", the
timer is from the external clock. The external clock can be
used to count external events as well as provide an external
frequency for generating periodic interrupts.
Bits bO, b1, and b2 in the TCR are program controlled to
choose the appropriate prescaler output. The prescaling
divides the fplN frequency by 1,2,4, etc. in binary multiples
to 128 producing fCIN frequency to the counter. The processor cannot write into or read from the prescaler;
however, the prescaler is set to all "ls" by writing b3 of TCR
to a "1", which allows for truncation-free counting.
The MaR controlled mode of the timer is selected when
the TOPT (Timer Option) bit (b6) in the MaR is programmed
to a logical "1" to emulate the mask-programmable prescaler
of the MC6805P2 and MC6805P4. The timer circuits are the
same as described above; however, the Timer Control
Register (TCR) is configured differently, as discussed below.
The logical level for the functions of bits bO, b1, b2, and b5
in the TCR are all determined at the time of EPROM programming. They are controlled by corresponding bits within
the Mask Option Register (MaR, $784). The value programmed into MaR bits bO, b1, b2, and b5 controls the prescaler
diviSion and the timer clock selection. Bit b4 (TIE) and b3
(PSC) are set to a logical" 1" in the MaR controlled mode.
(When read by software, these six TCR bits always read as
logical "ls".) As in the software programmable configuration, the TIM (b6) and TIR (b7) bits of the TCR are controlled
by the counter and software as described above and in the
TIMER CONTROL REGISTER section. The MaR controlled
mode is designed to exactly emulate the MC6805P2 and
MC6805P4 which has only TIM and TIR in the TCR and have
the prescaler options defined as manufacturing mask
options.

RESETS
The MCU can be reset in two ways: by initial power-up
and by the external reset input (RESET). Upon power-up, a
delay of tRHL is needed before allowing the "RES'Efinput to
go high. This time allows the internal clock generator to
stabilize. Connecting a capacitor to the RESET input, as
shown in Figure 8, typically provides sufficient delay.

FIGURE 8 -

POWER-UP RESET DELAY CIRCUIT

I

Part of
MC68705P3
MCU

3-834

::c 1.0 ~F

MC68705P3

The internal circuit connected to the RES ET pin consists
of a Schmitt trigger which senses the RESET line logic level.
The Schmitt trigger provides an internal reset voltage when
it senses logical "0" on the RESET pin. During power-up,
the Schmitt trigger switches on (removes reset) when the
RESET pin voltage rises to VIRES +. When the RESET pin
voltage falls to a logical "0" for a period longer than one
t cyc , the Schmitt trigger switches off to provide an internal
reset voltage. The "switch off" voltage occurs at VIRES-.
A typical reset Schmitt trigger hysteresis curve is shown in
Figure 9. See Figure 13 under INTERRUPTS for the complete reset sequence.

Option Register (EPROM) is programmed to select crystal or
resistor operation. The oscillator frequency is internally
divided by four to produce the internal system clocks.
The different connection methods are shown in Figure 10.
FIGURE 9 - TYPICAL RESET SCHMITT
TRIGGER HYSTERESIS
Out
of Reset

INTERNAL CLOCK GENERATOR OPTIONS
The internal clock generator circuit is designed to require a
minimum of external components. A crystal, a resistor, a
jumper wire, or an external signal may be used to generate a
system clock with various stability/ cost tradeoffs. The Mask

In Reset

UI
0.8 V 2 V

4V

FIGURE 10 - CLOCK GENERATOR OPTIONS

5 XTAL

5 XTAL

CJ
4 EXTAl
Cl
(See Note 21

I

MC68705P3
MCU

4 EXTAL

(Crystal Option, MaR
b7=0, See Note 11

MC68705P3
MCU
(RC Option,
MaR b7=11

Crystal
Approximately 25% to 50% Accuracy
Typical tcyc= 1.25 p's
External Jumper

Vce

_""",-_~5 XT Al

~XTAl
External
Clock
Input

4 EXT AL

MC68705P3
MCU
(Crystal Option,
MaR b7=01

(See Figure 131 4 EXTAL
No
Connection

Me~~~5P3
(RC Option,
MaR b7= 11

Approximately 10% to 25% Accuracy
(Excludes Resistor Tolerancel
External Resistor

External Clock

NOTES:
1. When the TIMER input pin is in the VIHTP range (in the bootstrap EPROM programming model, the crystal option is forced. When the
TIMER input is at or below VCC, the clock generator option is determined by bit 7 of the Mask Option Register (ClKI.
2. The recommended Cl value with a 4.0 MHz crystal is 27 pF maximum, including system distributed capacitance. There is an internal
capacitance of approximately 25 pF on the XT AL pin. For crystal frequencies other than 4 MHz, the total capacitance on each pin should be
scaled as the inverse of the frequency ratio. For example, with a 2 M Hz crystal, use approximately 50 pF on EXTAL and approximately 25 pF
on XT Al. The exact value depends on the Motional-Arm parameters of the crystal used.

3-835

I

MC68705P3

Crystal specifications and suggested PC board layouts are
given in Figure 11. A resistor selection graph is given in
Figure 12.
FIGURE 11 - CRYSTAL MOTIONAL-ARM
PARAMETERS AND SUGGESTED PC BOARD LAYOUT

la)
Cl

EXTAL~~XTAL
4

~

5

FIGURE 12 - TYPICAL FREQUENCY SELECTION
FOR RESISTOR OSCILLATOR OPTION
8.0

!

r--__.------------------..

7.0
6.0

VCC=5.25V
TA=25°C

g 5.0

~
l4.0

~ 30
.~ 2.0

o

I

AT - Cut Parallel Resonance Crystal
Co =7 pF Max.
Freq. = 4.0 MHz @ CL = 27 pF
RS = 50 ohms Max.

1.0
10

20

50
40
Resistance I k{l)

30

60

70

80

Ib)

The crystal oscillator start-up time is a function of many
variables: crystal parameters (especially RS), oscillator load
capacitances, IC parameters, ambient temperature, and
supply voltage. To ensure rapid oscillator start-up neither the
crystal characteristics nor the load capacitances should exceed recommendations.
BOOTSTRAP ROM

The bootstrap ROM contains a factory program which
allows the MCU to fetch data from an external device and
transfer it into the MC68705P3 EPROM. The bootstrap program provides: timing of programming pulses, timing of Vpp
input, and verification after programming. See PROGRAMMING FIRMWARE section.

Ic)

NOTE: Keep crystal leads and circuit connections
as short as possible.

MASK OPTION REGISTER (MOR)
The Mask Option Register is an 8-bit user programmed
(EPROM) register in which six of the bits are used. Bits in
this register are used to select the type of system clock, the
timer option, the timer/prescaler clock source, and the
prescaler option. It is fully described in the MASK OPTIONS
section.
INTERRUPTS
The MC68705P3 MCU can be interrupted three different
ways: through the external interrupt (INT) input pin, the
internal timer interrupt request, or the software interrupt instruction (SWI). When any interrupt occurs: the current instruction (including SWI) is completed, processing is
suspended, the present CPU state is pushed onto the stack,
the interrupt bit (I) in the Condition Code Register is set, the
address of the interrupt routine is obtained from the appropriate interrupt vector address, and the interrupt routine is
executed. Stacking the CPU registers, setting the I-bit, and
vector fetching requires a total of 11 tcyc periods for completion. A flowchart of the interrupt sequence is shown in

3-836

MC68705P3

Figure 13. The interrupt service routine must end with a
return from interrupt (RTI) instruction which allows the CPU
to resume processing of the program prior to the interrupt
(by unstacking the previous CPU state). Unlike RESET,
hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the
current instruction execution is complete.
When the current instruction is complete, the processor
checks all pending hardware interrupts and, if unmasked,

FIGURE 13 -

proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Note that masked interrupts are latched for later interrupt service.
If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed as any other instruction.
The external interrupt is internally synchronized and then
latched on the falling edge of INT. A sinusoidal input signal

RESET AND INTERRUPT PROCESSING FLOWCHART

I
1-1 (in CC)
07F-SP
O-DDRs
CLR INT Logic
FF-Timer
7F - Prescaler

Stack
PC, X,A, CC

Timer
Load PC From:
SWI: 7FC/7FD
INT: 7FA 17FB
TIMER: 7F817F9

Put 7FE on
Address Bus

Fetch
Instruction

SWI

Load Options From
MaR ($784) Into
Control Logic

N
Execute All
Instruction
Cycles

Load PC
From
7FE17FF

3·837

MC68705P3

(tINT maximum) can be used to generate an external interrupt, as shown in Figure 14(a), for use as a Zero-Crossing
Detector (for negative transitions of AC sinusoid). This
allows applications such as servicing time-of-day routines
and engaging/disengaging AC power control devices. Offchip full-wave rectification provides an interrupt at every zero
crossing of the AC signal and thereby provides a 2f clock.

allowable frequeJl£Y is also determined by the software
response of the INT service routine.
A software interrupt (SWI) is an executable instruction
which is executed regardless of the state of the I-bit in the
Condition Code Register. SWls are usually used as breakpoints for debugging or as system calls.
INPUT/OUTPUT

For digital applications, the INT pin can be driven by a
digital signal. The maximum frequency of a signal that can
be recognized by the TIMER or TNT pin logic is dependent on
the parameter labeled tWL, tWH. The pin logic that
recognizes the high (or low) state on the pin must also
recognize the low (or high) state on the pin in order to "rearm" the internal logic. Therefore, the period can be
calculated as follows: (assumes 50/50 duty cycle for a given
period)

I

tcyc x 2 + 250 ns

There are 20 input/ output pins. The INT pin may be polled
with branch instructions to provide an additional input pin.
All pins on Ports A, B, and C are programmable as either inputs or outputs under software control of the corresponding
Data Direction Register (DDR). The port I/O programming is
accomplished by writing the corresponding bit in the port
DDR to a logic "1" for output or a logic "0" for input. On
Reset all the DDRs are initialized to a logic "0" state, placing
the ports in the input mode. The port output registers are not
initialized on Reset but may be written to before setting the
DDR bits to avoid undefined levels. When programmed as
outputs, the latched output data is readable as input data
regardless of the logic levels at the output pin due to output
loading; see Figure 15. When Port B is programmed for outputs, it is capable of sinking 10 mA and sourcing 1 mA on
each pin.

1
= period = TreQ

The period is not Simply tWL + tWH. This computation is
allowable, but it does reduce the maximum allowable frequency by defining an unnecessarily longer period (250 ns
twice). See Figure 14(b). For the INT function, the maximum

FIGURE 14 -

a -

TYPICAL INTERRUPT CIRCUITS

Zero-Crossing Interrupt

b -

Digital-Signal Interrupt
VCC

(Current
Limiting)

---'\II.I'v-Q-----f

Inapcut
(fINT Max)

R

TTL 4.7 k
Level
Digital ---4>----IINT
Input

MC68705P3
MCU

0.1-1.0

Rs M{J
ac Input~ 10 Vacp - p

/L

MC68705P3
MCU

F

FIGURE 15 - TYPICAL PORT 1/0 CIRCUITRY

Data
Direction Register
Bit*

Latched
Output
Data
Bit

Data
Direction
Register
Bit

Output
Data
Bit

Output
State

Input
To
MCU

x

High-Z* *

Pin

1
1

o

*DDR is write-only register and reads as all "ls".
* * Ports Band C are three-state ports. Port A has internal pullup
devices to provide CMOS drive capability. See Electrical
Characteristics tables for complete information

3·838

MC68705P3

All input/ output lines are TTL compatible as both inputs
and outputs. Port A lines are CMOS compatible as outputs
while port Band C lines are CMOS compatible as inputs. The
memory map in Figure 6 gives the address of data registers
and DDRs. The Register configuration is provided in Figure
16. Figure 17 provides some examples of port connections.

Caution
The corresponding DDRs for ports A, B, and Care
write-only registers (registers at $004, $005, and $006).
A read operation on these registers is undefined. Since
BSET and BClR are read-modify-write functions they

FIGURE 16 -

cannot be used to set or clear a single DDR bit (all
"unaffected" bits would be set). It is recommended
that all DDR bits in a port must be written using a
single-store instruction.
The latched output data bit (see Figure 15) may always be
written. Therefore, any write to a port writes all of its data
bits even though the port DDR is set to input. This may be
used to initialize the data registers and avoid undefined outputs; however, care must be exercised when using
read-modify-write instructions since the data read corresponds to the pin level if the DDR is an input ("0") and corresponds to the latched output data when the DDR is an output ("1").

MCU REGISTER CONFIGURATION

PORT DATA DIRECTION REGISTER (oDR)

PORT OAT A REGISTER

o

7

0

(11 Write Only; reads as all 1s
(21 1 = Output; 0= Input Cleared to 0 by Reset
(31 Port A Addr = $004
Port B Addr = $005
Port C Addr= $006

Port A Addr= $000
Port B Addr= $001
Port C Addr= $002 (Bits 0-3)

TIMER DATA REGISTER (TORI
LSB

MSB

$008

TIMER CONTROL REGISTER ITCRI

$009
See detail description in TIMER CONTROL REGISTER
section.

PROGRAMMING CONTROL REGISTER (PCRI

~

________________

~

__

I $OOB

~-L~

See detail description In ON-CHIP PROGRAMMING
HARDWARE section.

MASK OPTION REGISTER (MORI

o
$784
See detail description in MASK OPTIONS section.

3-839

I

MC68705P3

FIGURE 17 -

TYPICAL PORT CONNECTIONS
(a) Output Modes

I

PA7

27

PA6

26

PA5

25

PA4

24

PA3

23

PA2

22

PAl

21

PAO

20

ICMOS Loads)

--

11 TTL Load)

1.6 mA

PB7

19

PB6

18

PB5

17

PB4

16

PB3

15

PB2

14

PBl

13

PBO

12

.1 0 = HFEolb

____.Ib
10 mA
2N63861TYPICill)

-=

Port B, Bit 5 Programmed as Output, Driving
Darlington- Base Directly

Port A, Bit 7 Programmed as Output, Driving CMOS
Loads and Bit 4 Driving one TTL Load Directly luslng
CMOS output option)

+ V
+ V
PB7

19

PB6

18

PB5

17

PB4

16

PB3

15

PC3

11

PB2

14

PC2

10

PBl

13

PCl

9

PBO

12

4---10 mA

'"

CMOS
Inverters
MC"14049/MC14069
ITYPlca11

PCO

Port B, Bit 0 and Bit 1 Programmed as Output, Driving LEDs Directly

Port C, Bits 0-3 Programmed as Output, Driving
CMOS Loads. Using External Pullup Resistors

(b) Input Modes

MC74LS04
lTypicall

TTL Driving Port A Directly

PA7

PB7

PA6

PB6

25

PA5

24

PA4

23

PA3

22

PA2

MC74LS04
or
MC14069
lTypical)

17

PB5

16

PB4

15

PB3

14

PB2

PAl

PBl

PAO

PBO

CMOS or TTL Driving Port B Directly

MC14069
PC3
PC2
PCl
PCO

CMOS and TTL Driving Port C Directly.

3-840

MC68705P3

TIMER CONTROL REGISTER (TCR)

b4, TIE

External Enable- Used to enable the external
TIMER pin (7) or to enable the internal clock (if
TIN = Q) regardless of the external timer pin
state (disables gated clock feature). When
TOPT= 1, TIE is always a logical "1".

The configuration of the TCR is determined by the logic
level of bit 6 (Timer Option, TOPT) in the Mask Option
Register (MOR). Two configurations of the TCR are shown
below, one for TOPT = 1 and the other for TOPT = O.
TOPT = 1 configures the TCR to emulate the MC6805P2 or
MC6805P4. When TPOT = 0, it provides software control of
the TCR. When TOPT = 1, the prescaler "mask" options are
user programmable via the MOR. A description of each TCR
bit is provided below (also see Figure 8 and TIMER).

1 = Enables external timer pin.
0= Disables external timer pin.

TIN-TIE Modes
b7

b6

b5

b4

b3

b2

b1

bO

TIN

TIE

CLOCK

0

0

0

1

1
1

0
1

Internal Clock 1<1>2)
Gated lAND) of External and
Internal Clocks
No Clock
External Clock

Timer Control
Register $009
TCR with MaR TOPT=1 IMC6805P2/P4 Emulation)

b7

b6

b5

b4

b3

TIR

TIM

TIN

TIE

I I

I I I

PSC*

b2

b1

PS21 PS1

bO

Ipso I

Timer Control
Register $009

b3, PSC

Prescaler Clear- This is a write-only bit. It reads
as a logical "0" (when TOPT = 0) so the BSET
and BCLR on the TCR function correctly.
Writing a "1" into PSC generates a pulse which
clears the prescaler. (When TOPT = 1 this bit is
always read as a logica I "1" and has no effect on
the prescaler.)

b2, PS2
b1, PS1
bO, PSO

Prescaler Select- These bits are decoded to
select one of eight outputs on the timer
prescaler. The table below shows the prescaler
division resulting from decoding these bits.

TCR with MaR TOPT = 0 I Software Programmable Timer!

*

= write only, reads as a zero

b7, TIR

Timer Interrupt Request- Used to initiate the
timer interrupt or signal a timer Data Register
underflow when it is a logical" 1".
1 = Set when the Timer Data Register changes
to all zeros.
0= Cleared by external reset or under program
control.

PS2

PS1

0

0
0
1
1
0
0
1
1

0

b6, TIM

0
0
1
1
1
1

Timer Interrupt Mask-Used to inhibit the
timer interrupt, to the processor, when it is a
logical "1".
1 = Set by an external reset or under program
control.
0= Cleared under program control.

b5, TIN

External or Internal- Selects the input clock
source to be either the external TIMER pin (7)
or the internal t/>2.

PSO

0
1

0

Prescaler Division
1 I Bypass Prescaler)
2
4

1

8

0

16
32

1
0
1

64
128

Note
When changing the PS2-PSO bits in software, the
PSC bit should be written to a "1" in the same write
cycle to clear the prescaler. Changing the PS bits without clearing the prescaler may cause an extraneous
toggle of the Timer Data Register.

1 = Selects the external clock source
0= Selects the internal t/>2 (fOSC+4) clock
source

3-841

I

MC68705P3

Two examples for programming the MaR are discussed
below.

MASK OPTIONS
The MC68705P3 Mask Option Register is implemented in
EPROM. like all other EPROM bytes, the MaR contains all
zeros prior to programming.
When used to emulate the MC6805P2 or MC6805P4, five
of the eight MaR bits are used in conjunction with the
prescaler. Of the remaining, the b7 bit is used to select the
type of oscillator clock, and bits b3 and b4 are not used. Bits
bO, b1, and b2 determine the division of the Timer prescaler.
Bit b5 determines the Timer clock source. The value of the
TOPT bit (b6) is programmed to configure the TCR (a logic
"1" for MC6805P2/P4 emulation).
If the MaR Timer Option (TOPT) bit is a 0, bits b5, b4, b2,
b1, and bO set the initial value of their respective TCR bits
during reset. After initialization the TCR is software controllable.
A description of the MOR bits is as follows:

I

Example 1

To emulate an MC6805P2 to verfiy your program with an RC oscillator, and an event count
input for the timer with no prescaling, the MaR
would be set to "11111000". To write the MaR,
it is simply programmed as any other EPROM
byte.

Example 2

Suppose you wish to use the MC68705P3 programmable prescaler functions, and you wish
the initial condition of the prescaler to be divided by 64, with the input disabled and an internal
clock source. If the clock oscillator was to be in
the crystal mode, the MaR would be set to
"00001110" .

b2_..-_b_1 -,-_bO---, Mask Option
,-b_7-,-_b6_.-_b_5--,_b4_..-_b3---,r-

ON-CHIP PROGRAMMING HARDWARE
The Programming Control Register (PCR) at location $ooB
is an 8-bit register which utilizes the three lSBs (the five
MSBs are set to logic "ls"). This register provides the
necessary control bits to allow programming the MC68705P3
EPROM. The bootstrap program manipulates the PCR when
programming, so that users need not be concerned with the
PCR in most applications. A description of each bit follows.

1_C_LK--&.I_T_O_p....ITIL.-c_L_S....JIL.-_.J.I.:....
....
_..J...._P_2-J._P_l-L_P_0.....J1 Register $784

Clock Oscillator Type
l=RC
0= Crystal
Note

b7, ClK

VIHTP on the TIMER pin (7) forces the crystal mode.

b7
b6, TOPT

Timer Option
1 = MC6805P2/P4 type timer/prescaler. All bits,
except 6 and 7, of the Timer-Control
Register (TCR) are invisible to the user. Bits
5, 2, 1, and 0 of the Mask Option Register
determine the equivalent MC6805P2/P4
mask options.
0= All TCR bits are implemented as a Software
Programmable Timer. The state of MaR bits
5, 4, 2, 1, and 0 sets the initial values of their
respective TCR bits (TCR is then software
contolled after initialization).

b5, ClS

Timer/Prescaler Clock Source
1 = External TIMER pin.
0= Internal 2

b4

Not used if MaR TOPT= 1 (MC6805P2/P4
emulation). Sets initial value of TCR TIE if
MaR TOPT=O.

b3

Not used.

b2, P2
b1, P1
bO, PO

P.rescaler Option - the logical levels of these
bits, when decoded, select one of eight outputs
on the timer prescaler. The table below shows
the division resulting from decoding combinations of these three bits.
P2

Pl

PO

°
°°°1

°°1
1
°°

°1
°1
°1
°1

1
1
1

1
1

b6

b5

b4

b3

b2

b1

Program

bO

I

IVPONI PGE I PLE Control
L-_.L..-_.....L..._---.JL-_.L..-_....J_L.-_.J.___.1.._-..J_ Register $ooB

bO, PlE

Programming latch Enable- When cleared this
bit allows the address and data to be latched into the EPROM. When this bit is set, data can be
read from the EPROM.
1 = (set) read EPROM
0= (clear) latch address and data into
EPROM (read disabled)
PlE is set during a Reset, but may be cleared
any time. However, its effect on the EPROM is
inhibited if VPON is a logic "1".

bl, PGE

Program Enable- When cleared, PGE enables
programming of the EPROM. PGE can only be
cleared if PlE is cleared. PGE must be set when
changing the address and data; i.e., setting up
the byte to be programmed.
1 = (set) inhibit EPROM programming
0= (clear) enable EPROM programming (if
PLEislow)
PGE is set during a Reset; however, it has no
effect on EPROM circuits if VPON is a logic
"1".

b2, VPON

(Vpp ON) - VPON is a read-only bit and when at
a logic "0" it indicates that a "high voltage" is
present at the Vpp pin.
1 = no "high voltage" on Vpp pin
0= "high voltage" on Vpp pin
VPON being "1" "disconnects" PGE and PlE
from the rest of the chip, preventing accidental
clearing of these bits from effecting the normal
operating mode.

Prescaler Division
1 (Bypass Prescaler)
2
4

8
16

32
64
128

3-842

MC68705P3

2537 A. The recommended integrated dose (UV intensity x
exposure time) is 25 Ws/cm2 . The lamps should be used
without shortwave filters and the MC68705P3 should be
positioned about one inch from the UV tubes. Ultraviolet
erasure clears all bits of the MC68705P3 EPROM to the "0"
state. Data is then entered by programming "1s" into the
desired bit locations.

Note

VPON being "0" does not indicate that the Vpp
level is correct for programming. It is used as a
safety interlock for the user in the normal
operating mode.
The Programming Control Register functions are shown
below:

Caution
VPON PGE

PLE

0
1
0

0
0
1

0
0
0

1
0
1
0
1

1
0
0
1
1

0
1
1
1
1

Programming Conditions

Be sure that the EPROM window is shielded from light
except when erasing. This protects both the EPROM
and light-sensitive nodes.

Programming mode (program EPROM byte)
PGE and PLE disabled from system
Programming disabled (latch address and
data in EPROM)
PGE and PLE disabled from system
Invalid state; PGE=O iff PLE=O
Invalid state; PGE=O iff PLE=O
"High voltage" on VPP
PGE and PLE disabled from system
(Operating Mode)

PROGRAMMING FIRMWARE

The MC68705P3 has 115 bytes of mask ROM containing a
bootstrap program which can be used to program the
MC68705P3 EPROM. The vector at addresses $7F6 and $7F7
is used to start executing the program. This vector is fetched
when VIHTP is applied to pin 7 (TIMER pin) of the
MC68705P3 and the RESET pin is allowed to rise above
VIRES + . Figure 18 provides a schematic diagram of a circuit
and a summary of programming steps which can be used to
program the EPROM in the MC68705P3.

ERASING THE EPROM

The MC68705P3 EPROM can be erased by exposure to
high-intensity ultraviolet (UV) light with a wavelength of
FIGURE 18 -

PROGRAMMING CONNECTIONS SCHEMATIC DIAGRAM
Run
MC68705P3
VCC

VSS
INT

.I

24 21

VCC

VCC
EXTAL

17

D7

19

15

26

16 D6

22

14

25

15 D5

23

12 Q9

24

14 D4

PA3 23
PA2 22

13 03

PAl 21

10

PA6
PA5

0.1

XTAL

PA4

75 pF

+26 V

VPP
7 TIMER

12

PB7

010

407

MCl4040B
12-Bit
Counter

11 D2
206
01

4

9 00

19

3 05
5 04

MCM2716

6 03

(16K EPROM)

702

VCC

PB6 18

8 PCO
9

VDD

011

13 08

PAO 20

PBO

0.1

27

PA7

PB5 17

PCl

10 PC2

-""
1'-

1'-

~

~

PB4 16
PB3 15

11 PC3

COUNT

PB 1 PB2
13

as

14

~

.;:::

E

1N4748A

0,

lN4742A

510

VCC

~~

VCC=VOO= +5.0 V typical
VSS=O V
Vpp=+21 V ±1 V

D
Ql

~

>

~

Summary of Programming 5teps:
1. When plugging in the MC68705P3 or the MCM2716, be sure that 51 and 52 are closed and that VCC and + 26 V are not applied
2. To initiate programming, be sure Sl is closed; 52 IS closed; and VCC and + 26 V are applied. Then open S2, followed by 51
3. Before removing the MC68705P3, first close 52 and then close 51. Disconnect VCC and +26 V; then remove the MC68705P3

3-843

I

I

MC68705P3

PROGRAMMING STEPS
The MCM2716 UV EPROM must first be programmed with
an exact duplicate of the information that is to be transferred
to the MC68705P3. Non-EPROM addresses are ignored by
the bootstrap. Since the MC68705P3 and the MCM2716 are
to be inserted and removed from the circuit they should be
mounted in sockets. In addition, the precaution below must
be observed (refer to Figure 18):
Caution
Be sure S1 and S2 are closed and V CC and + 26 V are
not applied when inserting the MC68705P3 and
MCM2716 into their respective sockets. This ensures
that RESET is held low while inserting the devices.

I

When ready to program the MC68705P3 it is only
necessary to provide V CC and + 26 V, open switch S2 (to
apply Vpp and VIHTP), and then open Sl (to remove Reset).
Once the voltages are applied and both S2 and Sl are open,
the CLEAR output control line (PB4) goes high and then low,
then the 11-bit counter (MC14040B) is clocked by the PB3
output (COUNT). The counter selects the MCM2716 EPROM
byte which is to load the equivalent MC68705P3 EPROM
byte selected by the bootstrap program. Once the EPROM
location is loaded, COUNT clocks the counter to the next
EPROM location. This continues until the MC68705P3 is
completely programmed at which time the Programmed indicator LED is lit. The counter is cleared and the loop is
repeated to verify the programmed data. The Verified indicator LED lights if the programming is correct.
Once the MC68705P3 has been programmed and verified,
close switch S2 (to remove Vpp and VIHTP) and close
switch Sl (to Reset). Disconnect +26 V and VCC; then
remove the MC68705P3 from its socket.

MC6805P2 AND MC6805P4 EMULATION
The MC68705P3 emulates the MC6805P2 and MC6805P4
"exactly." MC6805P2/P4 mask features are implemented in
the Mask Option Register (MOR) EPROM byte on the
MC68705P3. There are a few minor exceptions to the exactness of emulation which are listed below:
1. The MC6805P2 "future ROM" area is implemented in
the MC68705P3 and these 704 bytes must be left unprogrammed to accurately simulate the MC6805P2/P4.
(The MC6805P2/P4 reads all "Os" from this area.)
2. The reserved ROM areas in the MC6805P2/P4 and
MC68705P3 have different data stored in them and this
data is subject to change without notice. The
FIGURE 19 -

MC6805P2 uses the reserved ROM for the self-check
feature and the MC68705P3 uses this area for the
bootstrap program.
3. The MC6805P2'reads all "ls" in its 48 byte "future
RAM" area. This RAM is not implemented in the
MC6805P2 mask ROM version, but is implemented in
the MC68705P3 and MC68705P4.
4. The Vpp line (pin 6) in the MC68705P3 must be tied to
VCC for normal operation. In the MC6805P2, pin 6 is
the NUM pin and is grounded in normal operation. The
MC6805P4 uses pin 6 for VSB which is normally tied to
VCe. as with the MC68705P3.
5. The LVI featl,Jre is not available in the MC68705P3.
Processing differences are not presently compatible
with proper design of this feature in the EPROM version.
6. The function in the Non-User Mode is not identical to
the MC6805P2/P4 version. Therefore, the MC68705P3
does not function in the MEX6805 Support System. In
normal operation, all pin functions are the same as on
the MC6805P2/P4 version, except for pin 6 as previously noted.
7. The MC6805P4 provides a standby RAM feature which
is not available on the MC68705P3.
The operation of all other circuitry has been exactly
duplicated or designed to function exactly the same in both
devices including Interrupts, Timer, Data Ports, and Data
Direction Registers (DDRs). A stated design goal has been to
provide the user with a safe inexpensive way to verify his
program and system design before committing to a factory
programmed ROM.
SOFTWARE
BIT MANIPULATION
The MC68705P3 MCU has the ability to set or clear any
single random-access memory or input/output bit (except
the Data Direction Register, see Caution under INPUT /OUTPUT paragraph), with a single instruction (BSET, BCLR).
Any bit in the page zero memory can be tested, using the
BRSET and BRCLR instructions and the program branches
as a result of its state. The Carry bit equals the value of the
bit referenced by BRSET and BRCLR. A Rotate instruction
may then be used to accumulate serial input data in a RAM
location or register. This capability to work with any bit in
RAM, ROM, or I/O allows the user to have individual flags in
RAM or to handle I/O bits as control lines. The coding example in Figure 19 illustrates the usefulness of the bit manipulation and test instructions. Assume that the MCU is to communicate with an external serial device. The external device

BIT MANIPULATION EXAMPLE

MCU

Serial
Device

SELF

READY ... t-2
P
Clock
,0

BRSET

2,PORTA,SELF

BSET
BRCLR
BCLR
ROR

1, PORTA
O,PORTA,CONT
1,PORTA
RAMLOC

R
T

Data ...

OA
""""-

CONT

3-844

MC68705P3

has a data ready signal, a data output line, and a clock line to
clock data one bit at a time, LSB first, out of the device. The
MCU waits until the data is ready, clocks the external device,
picks up the data in the Carry flag (C-bit), clears the clock
line, and finally accumulates the data bit in a RAM location.
ADDRESSING MODES
The MC68705P3 MCU has 10 addressing modes which are
explained briefly in the following paragraphs. For additional
details and graphical illustrations, refer to the M6805 Family
Users Manual.
The term "effective address" (EA) is used in describing the
addressing modes. EA is defined as the address from which
the argument for an instruction is fetched or stored.
IMMEDIATE - In the immediate addressing mode, the
operand is contained in the byte immediately following the
opcode. The immediate addressing mode is used to access
constants which do not change during program execution
(e.g., a constant used to initialize a loop counter).
DIRECT - In the direct addressing mode, the effective address of the argument is contained in a single byte following
the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single
2-byte instruction. This address area includes all on-chip
RAM, I/O registers, and 128 bytes of EPROM. Direct addressing is an effective use of both memory and time.
EXTENDED - In the extended addressing mode, the effective address of the argument is contained in the two bytes
following the opcode. Instructions using extended addressing are capable of referencing arguments anywhere in
memory with a single 3-byte instruction. When using the
Motorola assembler, the programmer need not specify
whether an instruction uses direct or extended addressing.
The assembler automatically selects the shortest form of the
instruction.
RELATIVE - The relative addressing mode is only used in
branch instructions. In relative addressing, the contents of
the 8-bit Signed byte following the opcode (the offset) is added to the PC, if and only if, the branch condition is true.
Otherwise, control proceeds to the next instruction. The
span of relative addressing is from -126 to + 129 from the
opcode address. The programmer need not worry about
calculating the correct offset when using the Motorola
assembler, since it calculates the proper offset and checks to
see if it is within the span of the branch.

INDEXED, NO OFFSET - In the indexed, no offset
addressing mode, the effective address of the argument is
contained in the 8-bit index register. Thus, this addressing
mode can access the first 256 memory locations. These instructions are only one byte long. This mode is often used to
move a pointer through a table or to hold the address of a
frequently referenced RAM or I/O location.
INDEXED, 8-BIT OFFSET - In the indexed, 8-bit offset
addressing mode, the effective address is the sum of the
contents of the unsigned 8-bit index register and unsigned
byte following the opcode. This addressing mode is useful in

selecting the kth element in an n element table. With this
2-byte instruction, k would typically be in X with the address
of the beginning of the table in the instruction. As such,
tables may begin anywhere within the first 256 addressable
locations and could extend as far as location 510 ($1 FE is the
last location at which the instruction may begin).
INDEXED, 16-BIT OFFSET - In the indexed, 16-bit offset
addressing mode, the effective address is the sum of the
contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address mode can
be used in a manner similar to indexed, 8-bit offset, except
that this 3-byte instruction allows tables to be anywhere in
memory. As with Direct and Extended addressing, the
Motorola assembler determines the shortest form of indexed
addressing.
BIT SET/CLEAR - In the bit set/clear addressing mode,
the bit to be set or cleared is part of the opcode and the byte
following the opcode specifies the direct address of the byte
in which the specified bit is to be set or cleared. Thus, any
read/write bit in the first 256 locations of memory, including
I/O, can be selectively set or cleared with a single 2-byte instruction. See Caution under the INPUT/OUTPUT
paragraph.
BIT TEST AND BRANCH - The bit test and branch
addressing mode is a combination of direct addressing and
relative addressing. The bit which is to be tested and the
condition (set or clear) is included in the opcode, and the
address of the byte to be tested is in the single byte immediately following the opcode byte. The Signed relative
8-bit offset is in the third byte and is added to the value of the
PC, if the branch condition is true. This single 3-byte instruction allows the program to branch based on the condition of
any readable bit in the first 256 locations of memory. The
span of branching is from -125 to + 130 from the opcode
address. The state of the tested bit is also transferred to the
Carry bit of the Condition Code Register. See Caution under
the INPUT/OUTPUT paragraph.
INHERENT - In the inherent addressing mode, all the information necessary to execute the instruction is contained
in the opcode. Operations specifying only the index register
br accumulator, as well as control instruction with no other
arguments, are included in this mode. These instructions are
one byte long.
INSTRUCTION SET
The MC68705P3 MPU has a set of 59 basic instructions,
which when combined with the 10 address modes produce
207 usable opcodes. They can be divided into five different
types: register/memory, read-modify-write, branch, bit
manipulation, and control. The following paragraphs briefly
explain each type. All the instructions within a given type are
presented in individual tables.
REGISTER/MEMORY INSTRUCTIONS - Most of these
instructions use two operands. One operand is either the accumulator or the index register. The other operand is obtained from memory using one of the addressing modes. The
jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operands. Refer to Table 1.

3-845

I

MC68705P3

CONTROL INSTRUCTIONS - The control instructions
control the MCU operations during program execution.
Refer to Table 5.

BRANCH INSTRUCTIONS - The branch instructions
cause a branch from the program when a certain condition is
met. Refer to Table 3.

ALPHABETICAL LISTING - The complete instruction set
is given in alphabetical order in Table 6.

BIT MANIPULATION INSTRUCTIONS - These instructions are used on any bit in the first 256 bytes of the memory

OPCODE MAP SUMMARY - Table 7 is an opcode map
for the instructions used on the MCU.

TABLE 1 -

I

(see Caution under INPUT/OUTPUT paragraph). One group
either sets or clears. The other group performs the bit and
test branch operations. Refer to Table 4.

READ-MODIFY-WRITE INSTRUCTIONS - These instructions read a memory location or a register, modify or
test its contents, and write the modified value back to
memory or to the register (see Caution under INPUT/OUTPUT paragraph), The test for negative or zero (TST) instruction is included in the read-modify-write instructions, though
it does not perform the write. Refer to Table 2.

REGISTER/MEMORY INSTRUCTIONS
Addressing Modes

Function

Op
Mnemonic Code Bytes Cycles

Load A from Memory

LDA

A6

Load X from Memory

LDX

AE

Store A

STA

In

Memory

2

2

Indexed
(16·Bit Offset)

Direct

Extended

Indexed
(No Offset)

Indexed
(8·8it Offset)

Op
Code Bytes Cycles

Op
Code Bytes Cycles

Op
Code Bytes Cycles

Op
Code Bytes Cycles

Immediate

B6

2

4

C6

1

F6

5

3

BE

CE

FE

B7

C7

F7

4

E6

5

OP
Code Bytes
D6

3

EE

DE

3

E7

D7

2

Store X In Memory

STX

BF

CF

FF

EF

DF

Add Memory to A

ADD

AB

BB

CB

FB

EB

DB

Add Memory and
Carry to A

ADC

A9

B9

C9

F9

E9

D9

SUB

AO

BO

CO

FO

EO

DO

Subtract Memory
Subtract Memory from
A with Borrow

A2

SBC

B2

E2

F2

C2

Cycles
6

D2

AND Memory to A

AND

A4

B4

C4

F4

E4

D4

OR Memory With A

ORA

AA

BA

CA

FA

EA

DA

ExclUSive OR Memory
With A

EOR

A8

88

C8

F8

E8

D8
Dl

ArithmetiC Compare A
With Memory

CMP

Al

Bl

Cl

Fl

El

CPX

A3

B3

C3

F3

E3

D3

BIT

A5

85

C5

F5

E5

D5

ArithmetiC Compare X

With Memory

Bit Test Memory With
A (Logical Compare)
Jump Unconditional

JMP

BC

CC

FC

EC

DC

Jump to Subroutine

JSR

BD

CD

FD

ED

DD

TABLE 2 -

READ-MODIFY-WRITE INSTRUCTION
Addressing Modes

Inherent (A)
Function

#
Op
#
Mnemonic Code Bytes Cycles

Inherent (X)

Indexed
(No Offset)

Direct

Op
#
#
#
#
Op
Code Bytes Cycles Code Bytes Cycles

Indexed
(8 Bit Offset)

#
#
Op
Code Bytes Cycles

Increment

INC

4C

1

4

5C

1

4

3C

Decremenl

DEC

4A

1

4

5A

1

4

3A

Clear

CLR

4F

1

4

5F

1

4

Complement

COM

43

1

4

53

1

4

Negate
(2·s Complement)

NEG

40

1

4

50

1

4

30

2

6

70

Rotate Left Thru Carry

ROL

49

1

4

59

1

4

39

2

6

79

Rotate Right Thru Carry

ROR

46

1

4

56

1

4

36

2

6

76

Logical Shift Left

LSL

48

1

4

58

1

4

38

2

6

78

Logical Shift Right

LSR

44

1

4

54

1

4

34

2

6

74

#
#
Op
Code Bytes Cycles

2

6

7C

1

6

6C

2

2

6

7A

1

6

6A

2

7

3F

2

6

7F

1

6

6F

2

7

33

2

6

73

1

6

63

2

7

1

6

60

2

7

1

6

69

2

7

1

6

66

2

7

1

6

68

2

7

1

6

64

2

7

2

7

2

7

ArithmetiC Shift Right

ASR

47

1

4

57

1

4

37

2

6

77

1

6

67

Test for Negative
or Zero

TST

4D

1

4

5D

1

4

3D

2

6

7D

1

6

6D

3-846

7

MC68705P3

TABLE 3 -

BRANCH INSTRUCTIONS
Relative Addressing Mode
Mnemonic

Op
Code

#
Bytes

#
Cycles

Branch Always

BRA

20

2

4

Branch Never

BRN

21

2

4

Branch IFF Higher

BHI

22

2

4

Branch IFF lower or Same

BlS

23

2

4
4

Function

BCC

24

2

(Branch IFF Higher or Same)

(BHS)

24

2

4

Branch IFF Carry Set

BCS
(BlO)

25

2

4

25

2

4

Branch IFF Not Equal

BNE

26

2

4

Branch IFF Equal

BEQ

27

2

4

Branch IFF Half Carry Clear

BHCC

28

2

4

Branch IFF Half Carry Set

BHCS

29

2

4

BPl

2A

2

4

Branch IFF Minus

BMI

2B

2

4

Branch IFF Interrupt Mask Bit is Clear

BMC

2C

2

4

Branch IFF Interrupt Mask Bit is Set

BMS

20

2

4

Branch I FF Carry Clear

(Branch IFF lower)

Branch IFF Plus

Branch IFF Interrupt Line is low

Bil

2E

2

4

Branch IFF Interrupt Line is High

BIH

2F

2

4

Branch to Subroutine

BSR

AD

2

8

TABLE 4 -

I

BIT MANIPULATION INSTRUCTIONS
Addressing Modes
Bit 5et/ Clear

Op
Code

Bit Test and Branch

Branch IFF Bit n is set BRSET n In

~

0 ... 71

Op
Code
2. n

Branch IFF Bit n is clear BRClR n In

~

0 .. 71

01 + 2. n

Function

Mnemonic

Bytes

Set Bit n

BSET n (n

~

0 ... 7)

10 + 2. n

Clear Bit n

BClR n In

~

0 .... 71

11 + 2. n

TABLE 5 -

Cycles

Bytes

10
10

CONTROL INSTRUCTIONS
Inherent

Function

Mnemonic

Op
Code

#

#

Bytes

Cycles

Transfer A to X

TAX

97

1

2

Transfer X to A

TXA

9F

1

2

Set Carry Bit

SEC

99

1

2

Clear Carry Bit

ClC

9B

1

2
2

Set Interrupt Mask Bit

SEI

9B

1

Clear Interrupt Mask Bit

CLI

9A

1

2

Software Interrupt

SWI

83

1

11

Return from Subroutine

RTS

81

1

6

Return from Interrupt

RTI

80

1

9

Reset Stack Pointer

RSP

9C

1

2

No-Operation

NOP

90

1

2

3-847

#
Cycles

MC68705P3

TABLE 6 -

INSTRUCTION SET

Addressing Modes

Mnemonic

Inherent Immediate

X
X
X

ADC
ADD
AND
ASl
ASR

X
X

Direct

Extended Relative

X
X
X
X
X

X
X
X

Condition Codes

Indexed
(No Offset)

Indexed
(8 Bits)

X
X
X
X
X

X
X
X
X
X

Bit
Indexed Set/
(16 Bits) Clear

X
X
X

X

BClR

X
X
X
X
X
X
X
X

BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
Bil

X

BIT

X

X

X

X

X

BlS
BMC
BMI
BMS
BNE
BPl
BRA
BRN

X
X

BRClR
BRSET

X

BSET

X

BSR
ClC

X

CLI

X

ClR

X

COM
CPX

N Z C

·
·
·· ·· ·
·· ·· · · ·
·· ·· ·· ·· ··
··· ··· ··· ··· ···
··· ··· ··· ··· ···
··· ··· ·· ·· ···
·· ·· ·· ·· ··
··· ··· ··· ··· ···
··· ··· ··· ··· ···
··· ··· ··· ··· ·
··· ·· ··· ··· ··
··· ··· ·
··
A
A
A
A
A

A
A
A
A
A

A
A

A
A

A
A

0

0

X

CMP

I

A A

X
X
X
X
X
X
X
X
X

BlO

H

A
A

X

BCC

I

Bit
Test &
Branch

X
X

X
X
X
X

X

X

X

X

X

X

Condition Code Symbols
H
Half Carry (From Bit 3)
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
Carry/Borrow
C
A
Test and Set if True, Cleared Otherwise
Not Affected
?
Load CC Register From Stack
1
Set
Clear

o

3·848

X
X
X
X

X

X

0
A
A
A

1
A A
A 1
A A

MC68705P3

TABLE 6 -

INSTRUCTION SET (CONTINUED)
Addressing Modes

Mnemonic
DEC

Inherent Immediate
X

INC

Extended Relative

Indexed
(No Offset)

Indexed
(8 Bits)

X

X

X

X

X
X

EOR

Direct

X

X

X

Indexed
(16 Bits)

X

X

X

X

X

X

X

X
X

X

JMP

Condition Codes

X

X

X

X

LDA

X

X

X

X

X

X

LDX

X

X

X

X

X

X

JSR

LSL

X

X

X

X

LSR

X

X

~

X

NEQ

X

X

X

X

NOP

X
X

X

X

X

ORA

X

ROL

X

RSP

X

RTI

X

RTS

X

X

SEI

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X
X

TAX

X

TST

X

TXA

X

N
Z
C
A

?

A

A

A

A

A

A

A

A

A

A

A

A

A

a

A

A

A

A

A

A

A

A

A

A

?

?

?

A

A

A

A

A

A

A

A

A

A

A

1

X

X

Condition Code Symbols

H

··· ··· ···
·· ·· ·· ·· ··
··· ··· ··
··· ··· · · ·
··· ··· · · ··
·· ·· · · ·
·· · ·· ·· ·
·· ·· ··
··· ·· ·· ·· ··
·· ·· · · ··
1

STX
SUB

H I N Z C

1

STA

SWI

Bit
Test &
Branch

?

X

SBC
SEC

X
X

Bit
Set/
Clear

Half Carry (From Bit 3)
Interrupt Mask
Negative (Sign Bit)
Zero
Carry I Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
Set
Clear

3-849

X

A

I

III
3:

n
TABLE 7 Branch

Bit Manipulation

~
o
0000

1
0001

2

0010

3

0011

4

0100

5

0101

6

0110

7

0111

8
1000

CN

m
o

9

1001

A

1010

B

1011

C

1100

D

1101

E

1110

F

1111

lITIl

BSC
1

o

0000
10
BRSETO
I3
BTB
10
BRCLRO
3
BTB

REL

4

17 BCLRO

BTB

14

2

1
1

2

Bse

u' t-

BTB

2

sse

IT

BCLR4
2
sse
2

17

BNE
REL

~

BEG
REI
BHCC
REL

1--

BHCS
2
REL
2

REl-_

14

10BRCLR7
3
BT8

I

17 BCLR7
2

8se

14
14
2

A

2

16

DIR

[4

1

16 -T4
2

~L

-~[4
LSLA
INH

BIH

1

~
LSLX
INH

CClM
LSR

COM

2

RTIINH

12

SWI
INH

IXI I ,
6

DIR

1

14

INH

1

INH

2

LSR

REL I 2 CLRDIR 11

I

1

TSTX
INH

CLR~NH I 1 CLR~NH

I2

I

Inherent
Immediate
Direct
Extended
Relative
Bit Set/ Clear
Bit Test and Branch
Indexed (No Offset)
Indexed. , Byte (8-Bit) Offset
Indexed. 2 Byte ('6-Bit) Offset

1111

1101

BI~MM

.

16 ASR
IX 1 I 1

~6
LSL
IX 1
ROL
IXI
DEC

ROL

6
1

1
IX 1

2

LSL

1

16

1

DEC

TAX
INH

r:

ac

INC

IXI I 1

TST

INC

I

2

TST

1

I

IX'

I,

CLR

INH

~~

SEI

2

SBC

IX2

1 2 SBC

IX1

I 1 SBC

!) ------,-

'--l

RESET

Set

Pin

eX>

7-BI1 Prescaler

(J1

""""-I
~----------------~I
Clear

Select
1-of-8

Timer Control Register ITCR)
TIR

Internal

cp2
Clock
(fosc+ 4 )

Timer

fplN - Prescaler Input Frequency
fCIN - Counter Input Frequency

Timer Control Register Bits
TIR - Timer Interrupt Request Status
TIM- Timer Interrupt Mask
TIN- Timer Input Select
TIE - Timer External Input Enable
PSC - Prescaler Clear
PS2, PS1, PSO- Prescaler Select

Mask Option Register Bits
ClK - Clock OSCillator Type
TOPT - Timer Mask/ Programmable Option
ClS- Timer Clock Source
ITIE) -ITimer External Input Enable)
SNM-Secure/Non-Secure Mode Option
P2, P1, PO- Prescaler Option

NOTES: The TOPT bit in the mask option register selects whether the timer is software programmable via the timer control register or emulates
the mask programmable parts via the MOR PROM byte.
The TIE bit in the mask option register is not used if MaR TOPT = 1 I MC6805P2 emulation!. It sets the intial value of TCR TIE if MaR
TOPT=O.

III

MC68705P5

The clock input to the timer can be from an external
source (decrementing the counter occurs on a positive transition of the external source) applied to the TIMER input pin,
or it can be the internal cJ>2 signal. The maximum frequency
of a signal that can be recognized by the TI M ER pin logic is
dependent on the parameter labeled tWL, tWH. The pin
logic that recognizes the high state on the pin must also
recognize the low state on the pin in order to "re-arm" the
internal logic. Therefore, the period can be calculated as
follows: (assumes 50/50 duty cycle for a given period)

.
tcyc x 2 + 250 ns = period =

I

1
freq

The period is not simply tWL + tWH. This computation is
allowable, but it does reduce the maximum allowable frequency by defining an unnecessarily longer period (250 ns
twice).
When the cJ>2 signal is used as the source, it can be gated
by an input applied to the TIMER pin allowing the user to
easily perform pUlse-width measurements. (Note: When the
MOR TOPT bit is set and the CLS bit is clear, an ungated cJ>2
clock input is obtained by tying the TIMER pin to VCC.) The
source of the clock input is selected via the TCR or the MOR
as described later.
A prescaler option can be applied to the clock input that
extends the timing interval up to a maximum of 128 counts
before decrementing the counter. This prescaling option
selects one of eight outputs on the 7-bit binary divider; one
output bypasses prescaling. To avoid truncation errors, the
prescaler is cleared when bit b3 of the TCR is written to a
logic "1", when in the software controlled mode (TOPT=O,
more on these modes in later paragraphs); however, TCR bit
b3 reads as a logic "0" when TOPT = 0 and as a "1" when
TOPT = 1 to ensure proper operation with read-modify-write
instructions (bit set and clear for example).
At Reset, the prescaler and counter are initialized to an all
"1s" condition; the Timer Interrupt Request bit (TCR, b7) is
cleared and the Timer Interrupt Request mask (TCR, b6) is
set. TCR bits bO, b1, b2, b4, and b5 are initialized by the corresponding Mask Option Register (MaR) bits at Reset. They
are then software selectable after Reset if TOPT = O.
Note that the timer block diagram in Figure 7 reflects two
separate timer control configurations: a) software controlled
mode via the Timer Control Register (TCR), and b) MOR
controlled mode to emulate a mask ROM version with the
Mask Option Register. In the software controlled mode, all
TCR bits are read/write, except bit b3 which is write-only
(always reads as a logic "0"). In the MOR controlled mode,
TCR bits b7 and b6 are read/write, the other six have no effect on a write and read as logic "1s". The two configurations provide the user with the capability to freely select
timer options as well as accurately emulate the MC6805P2
and MC6805P4 mask ROM version. In the following paragraphs refer to Figure 9 as well as the TIMER CONTROL
REGISTER and MASK OPTIONS sections.
The TOPT (Timer Option) bit (b6) in the Mask Option
Register is EPROM programmed to a logical "0" to select the
software controlled mode, which is described first. TCR bits
b5, b4, b3, b2, b1, and bO give the program direct control of
the prescaler and input selection options ..
The Timer Prescaler input (fpIN) can be configured for
three different operating modes, plus a disable mode,
depending upon the value written to TCR control bits b4 and
b5 (TIE and TIN).
When the TIE and TIN bits are programmed to "0", the
timer input is from the internal clock (cJ>2) and TIMER input

pin is disabled. The internal clock mode can be used for
periodic interrupt generation as well as a reference for frequency and event measurement.
When TIE = 1 and TIN = 0, the internal clock and the
TIMER input pin Signals are ANDed to form the timer input
fplN. This mode can be used to measure external pulse
widths. The external pulse simply gates in the internal clock
for the duration of the pulse. The accuracy of the count in
this mode is ± one count.
When TIE = 0 and TIN = 1, no fplN input is applied to the
prescaler and the timer is disabled.
When TIE and TIN are both programmed to a "1", the
timer is from the external clock. The external clock can be
used to count external events as well as provide an external
frequency for generating periodic interrupts.
Bits bO, b1, and b2 in the TCR are program controlled to
choose the appropriate prescaler output. The prescaling
divides the fPIN frequency by 1,2,4, etc. in binary multiples
to 128 producing fCIN frequency to the counter. The processor cannot write into or read from the prescaler;
however, the prescaler is set to all "1s" by writing b3 of TCR
to a "1", which allows for truncation-free counting.
The MOR controlled mode of the timer is selected when
the TOPT (Timer Option) bit (b6) in the MOR is programmed
to a logical "1" to emulate the mask-programmable prescaler
of the MC6805P2 and MC6805P4. The timer circuits are the
same as described above; however, the Timer Control
Register (TCR) is configured differently, as discussed below.
The logical level for the functions of bits bO, b1, b2, and b5
in the TCR are all determined at the time of EPROM programming. They are controlled by corresponding bits within
the Mask Option Register (MaR, $784). The value programmed into MaR bits bO, b1, b2, and b5 controls the prescaler
division and the timer clock selection. Bit b4 (TIE) and b3
(PSC) are set to a logical "1" in the MOR controlled mode.
(When read by software, these six TCR bits always read as
logical "1s".) As in the software programmable configuration, the TIM (b6) and TIR (b7) bits of the TCR are controlled
by the counter and software as described above and in
TIMER CONTROL REGISTER. The MOR controlled mode is
designed to exactly emulate the MC6805P2 and MC6805P4
which has only TIM and TIR in the TCR and have the
prescaler options defined as manufacturing mask options.

RESETS
The MCU can be reset in two ways: by initial power-up
and by the external reset input (REID). Upon power-up, a
delay of tRHL is needed before allowing the RESUinput to
go high. This time allows the internal clock generator to
stabilize. Connecting a capacitor to the RESET input. as
shown in Figure 8, typically provides sufficient delay.

FIGURE 8 -

POWER-UP RESET DELAY CIRCUIT

~
VCC--~~~~2~8--~

:r 1.0/,F

Part of

MC68705P5
MCU

3-858

MC68705P5

The internal circUit connected to the RESET pin consists
of a Schmitt trigger which senses the RESET line logic level
The Schmitt trigger provides an internal reset voltage when
it senses logical "0" on the RESET pin. During power-up,
the Schmitt trigger switches on (removes reset) when the
RESET pin voltage rises to VIRES +. When the RESET pin
voltage falls to a logical "0" for a period longer than one
t cyc , the Schmitt trigger switches off to provide an internal
reset voltage. The "switch off" voltage occurs at VIRES-.
A typical reset Schmitt trigger hysteresis curve IS shown in
Figure 9. See Figure 13 under INTERRUPTS for the complete reset sequence.

Option Register (EPROM) is programmed to select crystal or
resistor operation. The oscillator frequency is internally
divided by four to produce the internal system clocks.
The different connection methods are shown in Figure 10.
FIGURE 9 - TYPICAL RESET SCHMITT
TRIGGER HYSTERESIS
Out
of Reset

INTERNAL CLOCK GENERATOR OPTIONS
The internal clock generator cirCUit IS designed to require a
minimum of external components. A crystal, a resistor, a
Jumper wire, or an external signal may be used to generate a
system clock with various stability/ cost tradeoffs. The Mask

FIGURE 10 -

In Reset
0.8 V

4 EXTAl
CL
I See Note 21

.::c

4V

I

CLOCK GENERATOR OPTIONS

5 XTAl

5 XTAl

CJ

2V

MC68705P5
MCU

4 EXTAL

I Crystal Option, MOR
b7 = 0, See Note 11

MC68705P5
MCU
IRC Option,
MOR b7= 11

Crystal
Approximately 25% to 50% Accuracy
Typical tcyc = 1.25 IJ.s
External Jumper

~XTAl
External

Clock
Input

-=-

4 EXTAl

MC68705P5
MCU

ISee Fig. 12)
No
Connection

I Crystal Option,
MORb7=0I

4
EXTAl

MC68705P5
MCU
IRC Option,
MOR b7= 11

ApprOXimately 10% to 25% Accuracy
I Excludes Resistor Tolerance)
External Resistor

External Clock

NOTES
1 When the TIMER input pin is in the VIHTP range lin the bootstrap EPROM programming mode), the crystal optIOn is forced When the
TIMER input is at or below VCC, the clock generator option is determined by bit 7 of the Mask OptIOn Register lelK)
The recommended CL value with a 4.0 MHz crystal is 27 pF maximum, including system distributed capacitance. There IS an internal
capacitance of approximately 25 pF on the XTAL pin. For crystal frequencies other than 4 MHz, the total capacitance on each pin should be
scaled as the Inverse of the frequency ratio. For example, With a 2 MHz crystal, use approximately 50 pF on EXTAl and approximately 25 pF
on XT AL. The exact value depends on the Motional-Arm parameters of the crystal used

3-859

MC68705P5

Crystal specifications and suggested PC board layouts are
given in Figure 11. A resistor selection graph is given in
Figure 12.
FIGURE 11 - CRYSTAL MOTIONAL-ARM
PARAMETERS AND SUGGESTED PC BOARD LAYOUT

la)

4

I

8.0r-~~----------------------------------~

7.0

~2

6.0

VCC=525 V
TA=25°C

>-

C,

EXTAL

FIGURE 12 - TYPICAL FREQUENCY SELECTION
FOR RESISTOR OSCILLATOR OPTION

ct::r
AT - Cut Parallel Resonance Crystal
Co = 7 pF Max
Freq = 4.0 MHz @ CL = 27 pF
RS = 50 ohms Max

~ 50
XTAL

5

f

40

o 3.0

j§

~ 2.0

o

'.0

o

~

o

__ ____ __
~

10

~

20

~~

__-L____L -__

40
50
Resistance Iknl

30

~

____

60

~

70

__

~

80

Ib)

The crystal oscillator start-up time is a function of many
variables: crystal parameters (especially RS), oscillator load
capacitances, IC parameters, ambient temperature, and
supply voltage. To ensure rapid oscillator start-up neither the
crystal characteristics nor the load capacitances should exceed recommendations
BOOTSTRAP ROM
The bootstrap ROM contains a factory program which
allows the MCU to fetch data from an external device and
transfer it into the MC68705P5 EPROM. The bootstrap program provides: timing of programming pulses, timing of Vpp
input, and verification after programming. See PROGRAMMING FIRMWARE.
MASK OPTION REGISTER (MOR)
Ic)

NOTE' Keep crystal leads and circuit connections

The Mask Option Register is an 8-bit user programmed
(EPROM) register. Bits in this register are used to select the
type of system clock, the timer option, the timer/prescaler
clock source, the prescaler option, and the secure mode. It is
fully described in the MASK OPTIONS.
INTERRUPTS
The MC68705P5 MCU can be interrupted three different
ways: through the external interrupt liNT) input pin, the
internal timer interrupt request, or the software interrupt instruction (SWIl. When any interrupt occurs: the current instruction (including SWI) is completed, processing is
suspended, the present CPU state is pushed onto the stack,
the interrupt bit (I) in the Condition Code Register is set, the
address of the interrupt routine is obtained from the appropriate interrupt vector address, and the interrupt routine is
executed. Stacking the CPU registers, setting the I-bit, and
vector fetching requires a total of 11 tcyc periods for completion. A flowchart of the interrupt sequence is shown in

as short as possible

3-860

MC68705P5

proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Note that masked interrupts are latched for later interrupt service.
If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed as any other instruction.
The external interrupt is internally synchronized and then
latched on the falling edge of INT. A sinusoidal input Signal

Figure 13. The interrupt service routine must end with a
return from interrupt (RTI) instruction which allows the CPU
to resume processing of the program prior to the interrupt
(by unstacking the previous CPU state). Unlike RESET,
hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the
current instruction execution is complete.
When the current instruction is complete, the processor
checks all pending hardware interrupts and, if unmasked,

FIGURE 13 -

RESET AND INTERRUPT PROCESSING FLOWCHART

I
1--1 (in CC)
07F--SP
O--DDRs
CLR iNT Logic
FF--Timer
7F -- Prescaler

Put 7FE on
Address Bus

Clear
Stack
PC, X, A, CC

TCR6=O
And
TCR 7 = 1

y

Timer
Load PC From
SWI
7FC/7FD
INT
7FA /7FB
TIMER: 7F8!7F9

N

Fetch
Instruction

SWI

Load Options From
MOR ($784) Into
Control Logic

N
Execute All
Instruction
Cycles

Load PC
From
7FE!7FF

3-861

MC68705P5

(fINT maximum) can be used to generate an external interrupt, as shown in Figure 14(a), for use as a Zero-Crossing
Detector (for negative transitions of AC sinusoid). This
allows applications such as servicing time-of-day routines
and engaging/disengaging AC power control devices. Offchip full-wave rectification provides an interrupt at every zero
crossing of the AC signal and thereby provides a 2f clock.

allowable freque..!l9' is also determined by the software
response of the INT service routine.
A software interrupt (SWI) is an executable instruction
which is executed regardless of the state of the I-bit in the
Condition Code Register. SWls are usually used as breakpoints for debugging or as system calls.
INPUT/OUTPUT

For digital applications, the TNT pin can be driven by a
digital signal. The maximum frequency of a signal that can
be recognized by the TIMER or TNT pin logic is dependent on
the parameter labeled tWL, tWH. The pin logic that
recognizes the high (or low) state on the pin must also
recognize the low (or high) state on the pin in order to "rearm" the internal logic. Therefore, the period can be
calculated as follows: (assumes 50/50 duty cycle for a given
period)

I

tcyc x 2

1

+ 250 ns = period = Tr8Q

The period is not simply tWL + tWH This computation is
allowable, but it does reduce the maximum allowable frequency by defining an unnecessarily long period (250 ns
twice). See Figure 14(b). For the INT function, the maximum

There are 20 input/output pins The INT pin may be polled
with branch instructions to provide an additional input pin.
All pins on Ports A, B, and C are programmable as either inputs or outputs under software control of the corresponding
Data Direction Register (DDR). The port I/O programming is
accomplished by writing the corresponding bit in the port
DDR to a logic "1" for output or a logic "0" for input. On
Reset all the DDRs are initialized to a logic "0" state, placing
the ports in the input mode. The port output registers are not
initialized on Reset but may be written to before setting the
DDR bits to avoid undefined levels. When programmed as
outputs, the latched output data is readable as input data
regardless of the logic levels at the output pin due to output
loading; see Figure 15. When Port B is programmed for outputs, it is capable of sinking 10 mA and sourcing 1 mA on
each pin.

FIGURE 14 - TYPICAL INTERRUPT CIRCUITS
a - Zero-Crossing Interrupt

b - Digital-Signal Interrupt
VCC

(Current
Limiting)

TTL

--'\,/\/'v..--_Q
...-.. .

ac
Input
(fINT Max)

ac

--f
0.1 -10

4.7 k

Level
Digital --_-~ INT
Input

MC68705P5
MCU

MC68705P5
MCU

/IF

R,,;l M!2
10 Vp_p

Input~

FIGURE 15 - TYPICAL PORT liD CIRCUITRY
Data
Direction Register
Bit*
VJ

Latched
Output
Data
Bit

C

~.g
~

2c

-

0

~
c
0

u

Data
Direction
Register
Bit

Output
Data
Bit

Output
State

Input
To
MCU
0

High-Z* *

Pin

0
1
X

* DDR is write-only register and reads as all "1 s".
* * Ports Band C are three-state ports. Port A has internal pullup
devices to provide CMOS drive capability. See Electrical
Characteristics tables for complete information.

3-862

MC68705P5

All input/ output lines are TTL compatible as both inputs
and outputs. Port A lines are CMOS compatible as outputs
while port Band C lines are CMOS compatible as inputs. The
memory map in Figure 4 gives the address of data registers
and DDRs. The Register configuration is provided in Figure
16. Figure 17 provides some examples of port connections.

Caution
The corresponding DDRs for ports A, B, and Care
write-only registers (registers at $004, $005, and $006).
A read operation on these registers is undefined. Since
BSET and BCLR are read-modify-write functions they

FIGURE 16 -

cannot be used to set or clear a single DDR bit (all
"unaffected" bits would be set). It is recommended
that all DDR bits in a port must be written using a
single-store instruction.
The latched output data bit (see Figure 15) may always be
written. Therefore, any write to a port writes all of its data
bits even though the port DDR is set to input. This may be
used to initialize the data registers and avoid undefined outputs; however, care must be exercised when using
read-modify-wrlte Instructions since the data read corresponds to the pin level If the DDR is an Input ("0") and corresponds to the latched output data when the DDR IS an output ("1")

MCU REGISTER CONFIGURATION

PORT DATA REGISTER

PORT DATA DIRECTION REGISTER (DDR)

o
Port A Addr = $000
Port B Addr = $001
Port C Addr= $002 (Bits 0-3)

111 Write Only, reads as all 1s
(21 1 = Output; 0= Input Cleared to 0 by Reset
131 Port A Addr = $004
Port B Addr= $005
Port C Addr = $006
TIMER DATA REGISTER ITDR)

L-M_S_B____________________L_S_B~J

$~

TIMER CONTROL REGISTER ITCR)

$009
See detail description in TIMER CONTROL REGISTER.

PROGRAMMING CONTROL REGISTER IPCRI

o
~______________L-~~~I$OOB
See detail description in ON-CHIP PROGRAMMING HARDWARE.

MASK OPTION REGISTER IMORI

$784

See detail description in MASK OPTIONS.

3-863

II

MC68705P5

FIGURE 17 -

TYPICAL PORT CONNECTIONS

(a) Output Modes

I

PA7

27

PA6

26

PA5

25

PA4

24

ICMOS Loadsl

11 TTL Loadl
~

16 mA

PB7

19

PB6

18

PB5

17

PB4

16

PA3

23

PB3

15

PA2

22

PB2

14

PAl

21

PBl

13

PAO

20

PBO

12

+IO~ HFEolb
----.. Ib
10 mA
2N6386

-=

Port B, Bit 5 Programmed as Outpul, Driving
Darlington-Base Directly

Port A, Bit 7 Programmed as Outpu\, Driving CMOS
Loads and Bit 4 Driving one TTL Load Directly luslng
CMOS output optloni

+ V
+ V

PB7

19

PB6

18

PB5

17

PB4

16

PB3

15

PC3

11

PB2

14

PC2

10

PBl

13

PBO

12

~~

~~

CMOS
Inverters

MCi4049/MC14069
ITYPlcal1

PCl
PCO

~10mA

Port B, Bit 0 and Bit 1 Programmed as Output, Drlv
rng LED~ Directly

Port C, B'ls 0-3 Programmed as Output, Driving
CMOS Loads, USing External Pullup Resistors

(b) Input Modes

PB7

PA7

PB6

PA6

MC74LS04
ITYPlcali

25

PA5

24

PA4

23

PA3

22

TT L Driving Port A Directly

17
MC74LS04
or
MC14069
ITYPlcal1

PB5

16

PB4

15

PB3
PB2

PA2

14

PAl

13

PBl

PAO

12

PSO

CMOS or TTL Driving Port B Directly

MC14069
PC3
PC2
PCl
PCO

CMOS and TTL Driving Port C Directly

3-864

lTyplC~11

MC68705P5

TIMER CONTROL REGISTER (TCR)

b4, TIE

External Enable- Used to enable the external
TIMER pin 171 or to enable the internal clock lif
TI N = 01 regardless of the external timer pin
state Idisables gated clock featurel When
TOPT= 1, TIE is always a logical "1".

The configuration of the TCR is determined by the logic
level of bit 6 lTimer Option, TOPTI in the Mask. Option
Register I MORI. Two configurations of the TCR are shown
below, one for TOPT = 1 and the other for TOPT = O.
TOPT= 1 configures the TCR to emulate the MC6805P2 or
MC6805P4. When TPOT = 0, it provides software control of
the TCR. When TOPT= 1, the prescaler "mask" options are
user programmable via the MOR. A description of each TCR
bit is provided below lalso see Figure 7 and TIMERI.

1 = Enables external timer pin.
0= Disables external timer pin.

TIN-TIE Modes
b7

b6

b5

b4

b3

b2

bl

bO

TIN

TIE

0

0

0

1

1
1

0
1

Timer Control
Register $009

I TIR I TIM I

TCR with MOR TOPT = 1 I MC6805P21 P4 Emulation)

b7
TIR

b6

I

TIM

b5

b4

b3

I TIN

TIE

IPsc*1

b2

bl

PS21 PSl

bO
Control
Ipso I Timer
Register $009

b3, PSC

Prescaler Clear- This is a write-only bit. It reads
as a logical "0" Iwhen TOPT = 01 so the BSET
and BCLR on the TCR function correctly.
Writing a "1" into PSC generates a pulse which
clears the prescaler. IWhen TOPT = 1 this bit is
always read as a logical" 1" and has no effect on
the prescaler.1

b2, PS2
b1, PS1
bO, PSO

Prescaler Select- These bits are decoded to
select one of eight outputs on the timer
prescaler. The table below shows the prescaler
division resulting from decoding these bits.

TCR with MOR TOPT = 0 I Software Programmable Timer)
* = write only, reads as a zero

b7, TIR

Timer Interrupt Request- Used to initiate the
timer interrupt or signal a timer Data Register
underflow when it is a logical "1".
1 = Set when the Timer Data Register changes
to all zeros.
0= Cleared by external reset, power-on reset,
or under program control.

b6, TIM

Timer Interrupt Mask- Used to inhibit the
timer interrupt, to the processor, when it is a
logical "1".
1 = Set by an external reset, power-on reset, or
under program control.
0= Cleared under program control

b5, TIN

CLOCK
Internal Clock 1¢2)
Gated lAND) of External and
Internal Clocks
No Clock
External Clock

External or Internal- Selects the input clock
source to be either the external TI M ER pin 171
or the internal cj>2.

PS2

PSl

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

PSO

0
1

0
1
0
1
0
1

Prescaler Division
1 I Bypass Prescalerl
2
4
8
16
32
64
128

Note
When changing the PS2-PSO bits In software, the
PSC bit should be written to a "1" In the same write
cycle to clear the prescaler. Changing the PS bits without clearing the prescaler may cause an extraneous
toggle of the Timer Data Register

1 = Selects the external clock source levent
count model
0= Selects the internal cj>2 IfOSC+41 clock
source

3-865

I

MC68705P5

I

MASK OPTIONS

P2

P1

PO

The MC68705P5 Mask Option Register is implemented in
EPROM. Like all other EPROM bytes, the MaR contains all
zeros prior to programming.
When used to emulate the MC6805P2 or MC6805P4, five
of the eight MaR bits are used in conjunction with the
prescaler. Of the remaining, the b7 bit is used to select the
type of oscillator clock, b3 is the securel non-secure mode
option, and b4 is not used. Bits bO, b1, and b2 determine the
division of the Timer prescaler. Bit b5 determines the Timer
clock source. The value of the TOPT bit (b6) is programmed
to configure the TCR (a logic "1" for MC6805P2/P4 emulation).
If the MaR Timer Option (TOPT) bit is a 0, bits b5, b4, b2,
b1, and bO set the initial value of their respective TCR bits
during reset. After initialization the TCR is software controllable.
A description of the MaR bits is as follows:

°
°
°
°1

°
°1

°1
°1
°1
°1

Example 1

To emulate an MC6805P2 to 'verify your program with an RC oscillator, and an event count
input for the timer with no prescaling, the MaR
would be set to" 11111000'" To write the MaR,
it is simply programmed as any other EPROM
byte.

Example 2

Suppose you wish to use the MC68705P5 programmable prescaler functions, and you wish
the initial condition of the prescaler to be divided by 64, with the input disabled and an internal
clock source. If the clock oscillator was to be in
the crystal mode, the MaR would be set to
"00001110"

Clock Oscillator Type
1 = RC
0= Crystal
Note

VIHTP on the TIMER pin (7) forces the crystal mode.

b5, ClS

Timer Option
1 = MC6805P2/P4 type timer/prescaler All bits,
except 6 and 7, of the Timer-Control
Register (TCR) are invisible to the user. Bits
5, 2, 1, and 0 of the Mask Option Register
determine the equivalent MC6805P21 P4
mask options.
0= All TCR bits are Implemented as a Software
Programmable Timer. The state of MaR bits
5,4, 2, 1, and 0 sets the initial values of their
respective TCR bits nCR IS then software
con tolled after initialization).
Timer/Prescaler Clock Source
1 = External TIMER pin.
0= Internal 2

b4, (TIE)

Not used if MaR TOPT= 1 (MC6805P2/P4
emulation). Sets initial value of TCR TIE if
MaR TOPT=O.

b3, SNM

When this bit is set, i.e., programmed to a
"1", it is not possible to access the EPROM
contents of the MC68705P5 externally. For
further information see PROGRAMMING
FIRMWARE.

b2, P2
b1, P1
bO, PO

1

4

8
16
32
64
128

Two examples for programming the MaR are discussed
below.

LI_C_LK--LI_T_O_P~TIL-C_L_S--L._--LI_S_N_M_IL-p_2---L_P_1---L_p_0---li Register $784

b6, TOPT

°
°1

1
1
1

r-b_7~_b6_"""T""_b_5--"'r--b4_-r-_b_3"""T""_b_2--r_b_1--r_b_O--, Mask Option

b7, ClK

1

Prescaler Division
1 (Bypass Prescaler)
2

ON-CHIP PROGRAMMING HARDWARE
The Programming Control Register (PCR) at location $ooB
is an 8-bit register which utilizes the three lS Bs (the five
MSBs are set to logic "1s"). This register provides the
necessary control bits to allow programming the MC68705P5
EPROM. The bootstrap program manipulates the PCR when
programming, so that users need not be concerned with the
PCR in most applications. A descriptIOn of each bit follows.
b7

b6

b5

b4

b3

b2

b1

IVPONI

~GE

bO
I PLE

Program

I Register
Control
$ooB

L-_...1.-_--'-_ _L---_...1.-_--'-._---1._ _.1.._---l.

bO, PlE

Programming latch Enable- When cleared this
bit allows the address and data to be latched into the EPROM. When this bit is set, data can be
read from the EPROM.
1 = (set) read EPROM
0= (clear) latch address and data into
EPROM (read disabled)
PlE is set during a Reset, but may be cleared
any time. However, its effect on the EPROM is
inhibited if VPON is a logic" 1"

b1, PGE

Program Enable- When cleared, PGE enables
programming of the EPROM. PGE can only be
cleared if PlE is cleared. PGE must be set when
changing the address and data; i.e., setting up
the byte to be programmed.
1 = (set) inhibit EPROM programming
0= (clear) enable EPROM programming (if
PIE is low)

Prescaler Option - the logical levels of these
bits, when decoded, select one of eight outputs
on the timer prescaler. The table below shows
the division resulting from decoding combinations of these three bits.

3-866

MC68705P5

Iy. After programming, the only way to revert the non-secure
mode is by erasing the entire EPROM.

PGE is set during a Reset; however, it has no
effect on EPROM circuits if VPON is a logic
"1".
b2, VPON

PROGRAMMING STEPS

(Vpp ONI- VPON is a read-only bit and when at
a logic "0" it indicates that a "high voltage" is
present at the Vpp pin.
1 = no "high voltage" on Vpp pin
0= "high voltage" on Vpp pin
VPON being "1" "disconnects" PGE and PLE
from the rest of the chip, preventing accidental
clearing of these bits from effecting the normal
operating mode.

The MCM2716 UV EPROM must first be programmed with
an exact duplicate of the information that is to be transferred
to the MC68705P5. Non-EPROM addresses are ignored by
the bootstrap. Since the MC68705P5 and the MCM2716 are
to be inserted and removed from the circuit they should be
mounted in sockets. In addition, the precaution below must
be observed Irefer to Figure 18):
Caution

Be sure S1 and S2 are closed and VCC and + 26 V are
not applied when inserting the MC68705P5 and
MCM2716 into their respective sockets. This ensures
that RESET is held low while inserting the devices.

Note

VPON being "0" does not indicate that the Vpp
level is correct for programming. It is used as a
safety interlock for the user in the normal
operating mode.
The Programming Control Register functions are shown
below
VPON PGE

PLE

0
1
0

0
0
1

0
0
0

1
0
1
0
1

1
0
0
1
1

0
1
1
1
1

Programming Conditions
Programming mode (program EPROM by tel
PGE and PLE disabled from system
Programming disabled (latch address and
data in EPROMI
PGE and PLE disabled from system
Invalid state; PGE=O iff PLE=O
Invalid state; PGE=O Iff PLE=O
"High voltage" on Vpp
PGE and PLE disabled from system
(Operating Model

ERASING THE EPROM

The MC68705P5 EPROM can be erased by exposure to
high-intensity ultraviolet I UV) light with a wavelength of
2537 A The recommended Integrated dose (UV intensity x
exposure time) is a 25 Ws/ cm 2 The lamps should be used
without shortwave filters and the MC68705P5 should be
positioned about one inch from the UV tubes. Ultraviolet
erasure clears all bits of the MC68705P5 EPROM to the "0"
state. Data is then entered by programming "ls" into the
desired bit locations.
Caution

When ready to program the MC68705P5 it is only
necessary to provide V CC and + 26 V, open switch S2 I to
apply Vpp and VIHTPI, and then open Sl Ito remove Reset).
Once the voltages are applied and both S2 and S 1 are open,
the CLEAR output control line (PB4) goes high and then low,
then the l1-bit counter IMC14040B) is clocked by the PB3
output ICOUNT). The counter selects the MCM2716 EPROM
byte which is to load the equivalent MC68705P5 EPROM
byte selected by the bootstrap program. Once the EPROM
location is loaded, COUNT clocks the counter to the next
EPROM location. This continues until the MC68705P5 is
completely programmed at which time the Programmed indicator LED is lit. The counter is cleared and the loop is
repeated to verify the programmed data. The Verified indicator LED lights If the programming is correct.
Once the MC68705P5 has been programmed and verified,
close switch S2 Ito remove Vpp and VIHTP) and close
switch S1 Ito Reset). Disconnect +26 V and Vce then
remove the MC68705P5 from its socket.

Be sure that the EPROM window is shielded from light
except when erasing. This protects both the EPROM
and light-sensitive nodes.
PROGRAMMING FIRMWARE

The MC68705P5 has 115 bytes of mask ROM containing a
bootstrap program which can be used to program the
MC68705P5 EPROM. The vector at addresses $7F6 and $7F7
is used to start executing the program. This vector is fetched
when VIHTP is applied to pin 7 (TIMER pin) of the
MC68705P5 and the RESET pin is allowed to rise above
VIRES +. Figure 18 provides a schematic diagram of a circuit
and a summary of programming steps which can be used to
program the EPROM in the MC68705P5.
Note that the MC68705P5 will not execute the bootstrap
program when in the secure mode. Therefore, the on-chip
EPROM must be completely erased before programming. To
enter the secure mode, bit 3 of the mask option register must
be programmed to a logic one and memory locations $782
and $783 must be programmed with $20 and $FE respective-

3-867

MC6805P2 AND MC6805P4 EMULATION

The MC68705P5 emulates the MC6805P2 and MC6805P4
"exactly." MC6805P2/P4 mask features are implemented in
the Mask Option Register IMOR) EPROM byte on the
MC68705P5. There are a few minor exceptions to the exactness of emulation with are listed below:
1. The MC6805P2 "future ROM" area is implemented in
the MC68705P5 and these 704 bytes must be left unprogrammed to accurately simulate the MC6805P2/P4.
(The MC6805P2/P4 reads all "as" from this area.)
2. The reserved ROM areas in the MC6805P2/P4 and
MC68705P5 have different data stored in them and this
data is subject to change without notice. The
MC6805P2 uses the reserved ROM for the self-check
feature and the MC68705P5 uses this area for the
bootstrap program.
3. The MC6805P2 reads all "1s" in its 48 byte "future
RAM" area. This RAM is not implemented in the
MC6805P2 mask ROM version, but is implemented in
the MC68705P5 and MC68705P3.
4. The Vpp line Ipin 6) in the MC68705P5 must be tied to
VCC for normal operation. In the MC6805P2, pin 6 is
the NUM pin and is grounded in normal operation. The
MC6805P4 uses pin 6 for VSB which is normally tied to
VCe. a.s with the MC68705P5.
5. The function in the Non-User Mode is not identical to
the MC6805P2/P4 version. Therefore, the MC68705P5

I

MC68705P5

FIGURE 18 -

PROGRAMMING CONNECTIONS SCHEMATIC DIAGRAM
Run
MC68705P5
VCC

VSS
INT

.I.

24 21

VCC

VCC
EXTAL

PA7
PA6
PA5

0.1

XTAL

PA4

75 pF

+26 V

I

D7

19

15

26

16 D6

22

14

25

15

23

12

24

14

D4

13 D3

PA2 22

11 D2

PB7
PBO

D5

PA3 23

10

010
09

13 08

MC14040B
12-BI1
Counter

206
D1

:3 05

9 DO

19

Voo

011

407

PAO 20

TIMER

12

17

PAl 21

VPP

0.1

27

5 04
MCM2716

6 03

(16K EPROM)

702

VCC

PB6 18

PCO

PB5 17

PCl
10 PC2

r--

r--

-i



~

Summary of Programming Steps:
1. When plugging in the MC68705P5 or the MCM2716, be sure that Sl and S2 are closed and that VCC and +26 V are not applied.
2. To initiate programming, be sure S1 is closed; S2 is closed; and V CC and + 26 V are applied. Then open S2, followed by S 1.
3. Before removing the MC68705P5, first close S2 and then close Sl. Disconnect VCC and +26 V; then remove the MC68705P5.

FIGURE 19 -

BIT MANIPULATION EXAMPLE

-

MCU

READY

SELF

BRSET

2, PORTA, SELF

BSET
BRCLR
BCLR
ROR

1, PORTA
0, PORTA, CONT
1, PORTA
RAMLOC

2 P

Serial
Device

Clock

1

~
T

Data

OA

I--

CONT

3-868

I

MC68705P5

does not function in the MEX6805 Support System. In
normal operation, all pin functions are the same as on
the MC6805P2/P4 version, except for pin 6 as previously noted.
6. The MC6805P4 provides a standby RAM feature which
is not available on the MC68705P5.
The operation of all other circuitry has been exactly
duplicated or designed to function exactly the same in both
devices including Interrupts, Timer, Data Ports, and Data
Direction Registers (DDRs) A stated design goal has been to
provide the user with a safe inexpensive way to verify his
program and system design before committing to a factory
programmed ROM.
SOFTWARE
BIT MANIPULATION
The MC68705P5 MCU has the ability to set or clear any
single random-access memory or input/output bit (except
the Data Direction Register, see Caution under INPUT/OUTPUT), with a single instruction (BSET, BCLR). Any bit in the
page zero memory can be tested, using the BRSET and
BRCLR instructions and the program branches as a result of
its state. The Carry bit equals the value of the bit referenced
by BRSET and BRCLR. A Rotate instruction may then be
used to accumulate serial input data in a RAM location or
register. This capability to work with any bit in RAM, ROM,
or I/O allows the user to have individual flags in RAM or to
handle I/O bits as control lines. The coding example in
Figure 19 illustrates the usefulness of the bit manipulation
and test instructions. Assume that the MCU is to communicate with an external serial device. The external device has a
data ready signal, a data output line, and a clock line to clock
data one bit at a time, LSB first, out of the device. The MCU
waits until the data is ready, clocks the external device, picks
up the data in the Carry flag (C-bit), clears the clock line, and
finally accumulates the data bit in a RAM location.
ADDRESSING MODES
The MC68705P5 MCU has 10 addressing modes which are
explained briefly in the following paragraphs. For additional
details and graphical illustrations, refer to the M6805 Family
Users Manual.
The term "effective address" (EA) is used in describing the
addressing modes. EA is defined as the address from which
the argument for an instruction is fetched or stored.
IMMEDIATE - In the immediate addressing mode, the
operand is contained in the byte immediately following the
opcode. The immediate addressing mode is used to access
constants which do not change during program execution
(e.g., a constant used to initialize a loop counter).
DIRECT - In the direct addressing mode, the effective address of the argument is contained in a single byte following
the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single
2-byte instruction. This address area includes all on-chip
RAM, I/O registers, and 128 bytes of EPROM. Direct addressing is an effective use of both memory and time.
EXTENDED - In the extended addressing mode, the effective address of the argument is contained in the two bytes

following the opcode. Instructions using extended addressing are capable of referencing arguments anywhere in
memory with a single 3-byte instruction. When using the
Motorola assembler, the programmer need not specify
whether an instruction uses direct or extended addressing.
The assembler automatically selects the shortest form of the
instruction.
RELATIVE - The relative addressing mode is only used in
branch instructions. In relative addressing, the contents of
the 8-bit signed byte following the opcode (the offset) is added to the PC, if and only if, the branch condition is true.
Otherwise, control proceeds to the next instruction. The
span of relative addressing is from -126 to + 129 from the
opcode address. The programmer need not worry about
calculating the correct offset when using the Motorola
assembler, since it calculates the proper offset and checks to
see if it is within the span of the branch.

INDEXED, NO OFFSET - In the indexed, no offset
addreSSing mode, the effective address of the argument is
contained in the 8-bit index register. Thus, this addressing
mode can access the first 256 memory locations. These instructions are only one byte long. This mode is often used to
move a pointer through a table or to hold the address of a
frequently referenced RAM or I/O location.
INDEXED, 8-BIT OFFSET - In the indexed, 8-bit offset
addressing mode, the effective address is the sum of the
contents of the unsigned 8-bit index register and unsigned
byte following the opcode. This addressing mode is useful in
selecting the kth element in an n element table. With this
2-byte instruction, k would typically be in X with the address
of the beginning of the table in the instruction. As such,
tables may begin anywhere within the first 256 addressable
locations and could extend as far as location 510 ($1 FE is the
last location at which the instruction may begin).
INDEXED, 16-BIT OFFSET - In the indexed, 16-bit offset
addressing mode, the effective address is the sum of the
contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address mode can
be used in a manner similar to indexed, 8-bit offset, except
that this 3-byte instruction allows tables to be anywhere in
memory. As with Direct and Extended addressing, the
Motorola assembler determines the shortest form of indexed
addressing.
BIT SET/CLEAR - In the bit set/clear addressing mode,
the bit to be set or cleared is part of the opcode and the byte
following the opcode specifies the direct address of the byte
in which the specified bit is to be set or cleared. Thus, any
read/write bit in the first 256 locations of memory, including
1/0, can be selectively set or cleared with a single 2-byte instruction. See Caution under the INPUT/OUTPUT.

BIT TEST AND BRANCH - The bit test and branch
addreSSing mode is a combination of direct addressing and
relative addressing. The bit which is to be tested and the
condition (set or clear) is included in the opcode, and the

3-869

I

MC68705P5

address of the byte to be tested is in the single byte immediately following the opcode byte The signed relative
8-bit offset is in the third byte and is added to the value of the
PC, if the branch condition is true. This single 3-byte instruction allows the program to branch based on the condition of
any readable bit in the first 256 locations of memory. The
span of branching is from -125 to + 130 from the opcode
address. The state of the tested bit is also transferred to the
Carry bit of the Condition Code Register. See Caution under
INPUT /OUTPUT.
INHERENT - In the inherent addressing mode, all the information necessary to execute the instruction is contained
in the opcode. Operations specifying only the index register
or accumulator, as well as control instruction with no other
arguments, are included in this mode. These instructions are
one byte long.

I

INSTRUCTION SET
The MC68705P5 MPU has a set of 59 basic instructions,
which when combined with the 10 address modes produce
207 usable opcodes. They can be divided into five different
types: register/memory, read-modify-write, branch, bit
manipulation, and control. The following paragraphs briefly
explain each type. All the instructions within a given type are
presented in individual tables.
REGISTER/MEMORY INSTRUCTIONS - Most of these
instructions use two operands. One operand is either the accumulator or the index register. The other operand is obtained from memory using one of the addressing modes. The

jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operands. Refer to Table 1.
READ-MODIFY-WRITE INSTRUCTIONS - These instructions read a memory location or a register, modify or
test its contents, and write the modified value back to
memory or to the register (see Caution under INPUT/OUTPUT). The test for negative or zero (TST) instruction is included in the read-modify-write instructions, though it does
not perform the write. Refer to Table 2.
BRANCH INSTRUCTIONS - The branch instructions
cause a branch from the program when a certain condition is
met. Refer to Table 3.
BIT MANIPULATION INSTRUCTIONS - These instructions are used on any bit in the first 256 bytes of the memory
(see Caution under INPUT/OUTPUT). One group either sets
or clears. The other group performs the bit and test branch
operations. Refer to Table 4.
CONTROL INSTRUCTIONS - The control instructions
control the MCU operations during program execution.
Refer to Table 5.
ALPHABETICAL LISTING - The complete instruction set
is given in alphabetical order in Table 6.
OPCODE MAP SUMMARY - Table 7 is an opcode map
for the instructions used on the MCU.

3-870

MC68705P5

TABLE 1 -

REGISTER/MEMORY INSTRUCTIONS
Addressing Modes

Direct

Extended

Indexed
(No Offsetl

Op
Code Bytes Cycles

Op
Code Bytes Cycles

#
Op
Code Bytes Cycles

Immediate

Op
Mnemonic Code Bytes Cycles

Function

LOA

A6

Load X from Memory

LOX

AE

Store A In Memory

STA

Load A from Memory

Store X

In

10

A

STX

B6

4

2

C6

BE

CE

B7

C7

3

F6

5

I

FE

Indexed
(16·Bit Offset I

Op
Code Bytes Cycles

4

E6

4

EE

F7

2

5

E7

06

3

DE

3

6

07

BF

CF

FF

EF

OF

ADD

AB

BB

CB

FB

EB

DB

AOC

A9

B9

C9

F9

E9

09

SUB

AO

BO

CO

FO

EO

DO

Memory

Add Memory

2

Indexed
(8·Bit Offsetl
Op
#
Code Bytes Cycles

Add Memory and

Carry to A

Subtract Memury
Subtract Memory from

A with Borrow

SBC

B2

C2

F2

E2

02

AND Memory to A

AND

A4

B4

C4

F4

E4

04

OR Memory with A

ORA

AA

A2

BA

CA

FA

EA

OA

Exclusive OR Memory
with A

EOR

A8

B8

C8

F8

E8

08

CMP

Al

BI

CI

FI

EI

01

Arithmetic Compare X
with Memory

CPX

A3

B3

C3

F3

E3

03

Bit Test Memory with
A (Logical Compare)

BIT

A5

B5

C5

F5

E5

05

I

Arithmetic Compare A
with Memory

Jump Unconditional

JMP

BC

CC

FC

EC

DC

Jump to Subroutine

JSR

BO

CD

FD

ED

DO

TABLE 2 -

READ-MODIFY-WRITE INSTRUCTION
Addressing Modes

Inherent (A)
Op
Function

#

Mnemonic Code Bytes

#
Cycles

Inherent (X)

Indexed
(8 Bit Offset)

Indexed
(No Offset)

Direct

Op
#
#
#
#
Op
Code Bytes Cycles Code Bytes Cycles

#
#
Op
Code Bytes Cycles

#
#
Op
Code Bytes Cycles

Increment

INC

4C

1

4

5C

1

4

3C

2

6

7C

1

6

6C

2

Decremenl

DEC

4A

1

4

5A

1

4

3A

2

6

7A

1

6

6A

2

7

Clear

CLR

4F

1

4

5F

1

4

3F

2

6

7F

1

6

6F

2

7

Complement

COM

43

1

4

53

1

4

33

2

6

73

1

6

63

2

7

1

4

7

Negate
(2's Complement)

7

NEG

40

50

1

4

30

2

6

70

1

6

60

2

Rotate Left Thru Carry

ROL

49

1

4

59

1

4

39

2

6

79

1

6

69

2

Rotate Right Thru Carry

ROR

46

1

4

56

1

4

36

2

6

76

1

6

66

2

7

Logical Shift Left

LSL

48

1

4

58

1

4

38

2

6

78

1

6

68

2

7

7

Logical Shift Right

LSR

44

1

4

54

1

4

34

2

6

74

1

6

64

2

7

Arithmetic Shift Right

ASR

47

1

4

57

1

4

37

2

6

77

1

6

67

2

7

Test for Negative
or Zero

TST

4D

1

4

5D

1

4

3D

2

6

7D

1

6

6D

2

7

3-871

MC68705P5

TABLE 3 -

BRANCH INSTRUCTIONS
Relative Addressing Mode
Mnemonic

Op
Code

#
Bytes

Branch Always

BRA

20

2

4

Branch Never

BRN

21

2

4

Branch I FF Higher

BHI

22

2

4

Branch IFF lower or Same

BlS

23

2

4

BCC
(BHS)

24

2

4

24

2

4

BCS
(BlO)

25

2

4

25

2

4

Branch I FF Not Equal

BNE

26

2

4

Branch I FF Equal

BEQ

27

2

4

Branch IFF Half Carry Clear

BHCC

28

2

4

Branch IFF Half Carry Set

BHCS

29

2

4

Branch IFF Plus

BPl

2A

2

4

Branch I FF Minus

BMI

2B

2

4

Branch IFF Interrupt Mask Bit is Clear

BMC

2C

2

4

Branch IFF Interrupt Mask Bit is Set

BMS

20

2

4

Branch IFF Interrupt Line is low

Bil

2E

2

4

Branch IFF Interrupt Line is High

BIH

2F

4

Branch to Subroutine

BSR

AO

2
2

Function

Branch I FF Carry Clear
(Branch IFF Higher or Same)
Branch IFF Carry Set
(Branch IFF lower!

I

TABLE 4 -

#
Cycles

8

BIT MANIPULATION INSTRUCTIONS
Addressing Modes
Bit Setl Clear

Function

Op
Code

Mnemonic

Bytes

Bit Test and Branch
Cycles

Branch IFF Bit n is clear BRClR n (n
Set Bit n

BSET n (n

Clear Bit n

BClR n (n

Bytes

2. n
01 + 2. n

Branch IFF Bit n is set BRSET n (n - 0 .. 7)

= 0 ... 7)
= 0 .. 7)
= 0 .... 7)

Op
Code

10
10

10 + 2. n
11 + 2. n

TABLE 5 - CONTROL INSTRUCTIONS
Inherent
Mnemonic

Op
Code

#
Bytes

#
Cycles

Transfer A to X

TAX

97

1

2

Transfer X to A

TXA

9F

1

2

Set Carry Bit

SEC

1

2

Clear Carry Bit

ClC

99
98

1

Set Interrupt Mask Bit

SEI

9B

1

2
2

Clear Interrupt Mask Bit

CLI

9A

1

2

Software Interrupt

SWI

83

1

11

Return from Subroutine

RTS

81

1

6

Return from Interrupt

RTI

1

9

Reset Stack Pointer

RSP

1

2

No-Operation

Nap

80
9C
90

1

2

Function

3·872

Cycles

MC68705P5

TABLE 6 -

INSTRUCTION SET

Addressing Modes

Condition Codes
Bit

Mnemonic

Inherent Immediate

Direct

Extended Relative

Indexed
(No Offset)

Indexed
(8 Bits)

Indexed
(16 Bits)

X

X

X

ADC

X

X

X

ADD

X

X

X

X

X

X

AND

X

X

X

X

X

X

ASL

X

X

X

X

ASR

X

X

X

X

Setl
Clear

Bit
Test &
Branch

X
X

BHCS

X

BHI

X

BHS

X

BIH

X

BIL

X

BIT

X

X

X

X

BLO

X

BLS

X

BMC

X

BMI

X

BMS

X

BNE

X

BPL

X

BRA

X

BRN

X

X

X

X

BRSET

X

BSET

X

BSR

X
X

Cli

X

CLR

X

CMP
COM
CPX

A A A

A A

BRCLR

CLC

C

A A A

X

BEG

Z

··
··· ··· ·
··· ··· ··· ··· ···
··· ··· ··· ··· ···
··· ··· ··· ··· ···
·· ·· · · ··
··· ··· ··· ··· ···
··· ··· ··· ··· ···
·· ·· ·· ·· ··
··· ··· ··· ··· ·
·· ·· ·· ·· ··
··· ·· ·· ·· ··
··· ···
A A

X

BHCC

N

A A A

A A A

BCLR
BCS

I

A

X

BCC

H

A

A
A

0

0

X
X

X

X

X

X

X

X
X

Condition Code Symbols
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bill
Z
Zero
C
Carry/Borrow
A
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
1
Set
Clear

o

3-873

X

X

X

X

X

X

X

X

0

X

1

A A A

A A

X

1

A A A

I

MC68705P5

TABLE 6 -

INSTRUCTION SET (CONTINUED)
Addressing Modes

Condition Codes

I
I Mnemonic

DEC

Inherent Immediate
X

INC

X

X
X

Indexed
(16 Bits)

Indexed
(No Offset)

Indexed
(8 Bits)

X

X

X

X

X

X

X

X

X

X

X

JMP

X

X

X

X

X

X

X

X

X

X

X

LOX

X

X

X

X

X

X

X

X

X

X

LSR

X

X

X

X

NEG

X

X

X

X

NOP

X
X

X

X

X

X

ORA
ROL

X

RSP

X

RTI

X

RTS

X

SEC

X

SEI

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

TXA

X

?

?

?

A A A
e

X

X

?

1

1

X

TST

A A

A A A

X

TAX

A A

0 A A

X

X

A A

A A A

STX
SWI

A A

A A A

STA
SUB

·· ·· ··
·· ·· · · ··
·· ·· · · ··
·· ·· ·
·· ··
·· ·· · · ··
·· ·· · · ·
·· ·· · · ·
·· · · ·· ·
·· ·· ··
·· · · · ·
··· ··· ·· ·· ···
?

X

SBC

X

H I N Z C

A A

X

LSL

Bit
Test &
Branch

A A

X

LOA

JSR

I

Extended Relative

X
X

EOR

Direct

Bit
Setl
Clear

A A

A A

A A A

1

X

X

Condition Code Symbols
H
Half Carry (From Bit 3)
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
C
Carry 1Borrow
A
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
1
Set
o
Clear

3-874

X

A A

3:

(")

TABLE 7 Bit Manipulation
BTB
I
BSC

o

~
o

0000

I

Branch
REL

I
DIR

Read-Modify-Write
INH
IXl

INH

INH

3

4

5

6

7

8

9

0011

0100

0101

0110

0111

l00J

1001

SUB
2

3

3

BTB

8AClAl
TO
3
BTB

0011

4

10BASET2
3
BTB

5

10
BAClA2
3
BTB

6

10
BASET3
3
BTB

0100
0101
0110

esc

2

Rll

172 BClAlBSC 142

BlS
REL

2

r

[7 BSET2
2
BSC 2
17 BClA2 14
2

BSC

2

6

BCC
REL

esc

12
16

2

COM
DIR
lSR
DTR

X
14I COMAINH 141 COM INH

14

1

lSRA
INH

6

I ) COM
2

~17
lSAX
1

INH

IX 1

11

1"1

COM

lSR

2

IX 1

BNE
2
REL

lSR
1

ROR
2
DIR

I

RORA
1
INH

I

RORX
1
INH

2 ROR IX1 1,

ROR IX

I

_2~_IX~I~-+-

7 ASR

! 6 ASR

8

lSlX
INH

7

1

1000

9

1001

BTB

3

A

10
BRSET5

B

BAClA5
3
BTB
10
BASH6
3
BTB

1010

BTB

10

lOll

C

1100

E

F
1111

10
BRClR6
;J _ jlTB

l

10
13BASET7B
BT
10
BAClR7
3
BTB

2

~

2

BSC

2

[7 BClA5 14
2
BSC 2
[7 BSET6 14
2

l7
2

REL

BPl
REL

BClA6
BSC

[4
2

BSC

[4

ROl

2

OIR

16

DEC
2
DIR

1

AOlA

14

INH

14

1

ROlX
INH

14

DECA
I
DECX
I
INH
1
INH

2

IX:

11

SBC
SBC
IX2
EXT I 3

I

ROl
2

17

IXl

2

CPX
IMM 12

CPX

CPX
CPX
IX2
EXT I 3

DIR 13

I 2

lD~MM I 2

3

BIT

BIT
EXT 3
_5-_ _ T6

DIR

lDADIR 13

I 4

I 5

ROl

ADC
ADC
SEC
INH 12
DIR
IMM 12

DEC

CLI

,Xl

BMS
REL
Bil
BIH

2

I2

DIR I 1
TST

DIR

I 1 TSTAINH I

1

TSTX
INH

I2

INC

3

IX 1

I1

5 OAA
EXT

ADD
ADD
IMM 12
DIR

5 ADD
EXT

SEI
RSP
INH

TST

NOP
BSR
INH 12
REL
lOX
IMM

REL
REL I 2 ClR DIR

1, CLA~NH I 1 CLR~NH

I 2

(lR
IXl

I

ClR
1

Inherent
Immediate
Direct
Extended
Relative
Bit Setl Clear
Bit Test and Branch
Indexed INo Offsetl
Indexed, 1 Byte 18-Bitl Offset
Indexed, 2 Byte 116-Bit) Offset

AD~XT

ORA
ORA
DIR
INH 12
IMM 12

INC
IXll,

TST

lD~XT I 3

IXI I 1
5

AND,X2 I 2

CPX
IXI

IX2

0010

3

CPX

1
14

AND

AND
.

IX

[5

BIT

I'

IX

0011

IX

0100

5

BIT

BIT
2_--.lXl.ll
15
14

~

lDA IX2 12 LDA IX1 11

4

LOA IX

--'llQJ

6

0110

8
12

INH 12
INCX
INH I 1
INH I 2

I3
[6

1

2

1((X)

I

INCA

AN~XT

5

I

INC

OOJI

SBC

7

12

1

16

DEC

IX

CMP

SBC

0111

TXA
INH

T6
I

3 ADC ,X2

16

JM~XT I

I

18

19

[5
lOX
DIR 3
5 STX ]6

[6
LOX
EXT 3
-[7
STX

3

JSA
3
EXT

DIR

4

DIR

3

EXT

IX2
IX2

3 JMP

3

IX2

JSA

I 4

IXI

12

JMP
JSA

2

IX1

2

1011

IX

1100

IXI

I

IXI

j ,r., J ~
_

o

1

1

B

C

JSR

1

IX2

1010

IX
JMP

[5 LOX 14
LOX
IX2 2
6 STX IXI [51
STX

3

IX
ADD

IXI

18

A

OAA

ADD

2
14

IX2

1001

OAA

2

9

ADC

2 ADC IX1

15

ADD

3
15

2 JMPDIR

1

15

OAA

3

16

7

JSR

I 5

1101

E

LOX

1110
STX
IX

F
1111

LEGEND

Abbreviations for AddreBB Modes
INH
IMM
DIR
EXT
REL
BSC
BTB
IX
IXl
IX2

SBC
DIR 13

IX

I 6

I

~

I

lSl

BMI
REL

BMC
BSC I 2
RELI2

17 BSETl [4
2
BSC 2
17 BClA7 14
I
2

BHCS

2

17 BSH5 14

16

lSl

12

o

~

1---

6

17 BClA4 14

SBC
IMM 12

BI~MM

I

SUB

~T

AND
AND
IMM 12
DIH

ASRX
INH

1110

~

If,1

4

6
1
1

7

10BAClA4

SWI
INH

BCS
REL

[7 BSET3 14
2

INn

BHI

0111

1101

IX

IXI

11~0

CMP
CMP
CMP
CMP
CMP
IXI I I
IMM I 2
DIR 13
EXT I 3
IX2 I 2

RTS

BRN
REL

10BASETl [7 BSETl 14

0010

o

1X2
Igl

SUB

SUB
DIR

~

1

(J'I

11~-T

B

1011

T-----~

2

"'-J

EXT

DIR

IMM
A
1010

INH

2
0010

OOJI

00

o

Register / Memory

Control
IX

1

()()()1

=

VJ

en
CO
......

M6805 HMOS FAMILY OPCODE MAP

# of eye,,"

Mo,m,,"
Bytes

4

.. SUB

1

IX

Opcode in Hexadecimal
Opcade in Binary

UOOO --' - - - - - - - - - - Address Mode

III

U1
."
U1

®

MOTOROLA

MC14680SE2

Advance InforIllation

CMOS
(HIGH PERFORMANCE SILICON GATE)

8-BIT MICROPROCESSOR UNIT

8-BIT

The MC146805E2 Microprocessor Unit (MPU) belongs to the M6805
Family of Microcomputers. This 8-bit fully static and expandable
microprocessor contains a CPU, on-chip RAM, I/O, and TIMER. It is a
low-power, low-cost processor designed for low-end to mid-range applications in the consumer, automotive, industrial, and communications
markets where very low power consumption constitutes an important
factor. The following are the major features of the MC146805E2 MPU:

I

MICROPROCESSOR

S SUFFIX
CERDIP PACKAGE
CASE 734

HARDWARE FEATURES

L SUFFIX

• Typical Full Speed Operating Power of 35 mW @ 5 V
•

Typical WAIT Mode Power of 5 mW

•

Typical STOP Mode Power of 25 p.W

•

112 Bytes of On-Chip RAM

CERAMIC PACKAGE
CASE 715

P SUFFIX

•

16 Bidirectional I/O Lines

•

Internal 8-Bit Timer with Software Programmable 7-Bit Prescaler

•

External Timer Input

•

Full External and Timer Interrupts

•

Multiplexed Address/Data Bus

•

Master Reset and Power-On Reset

•

Capable of Addressing Up to BK Bytes of External Memory

•

Single 3- to 6-Volt Supply

•

On-Chip Oscillator

PLASTIC PACKAGE
CASE 711

Z SUFFIX
CHIP CARRIER
CASE 761

PIN ASSIGNMENT

• 40-Pin Dual-In-Line Package
•

Chip Carrier Also Available

RESET

SOFTWARE FEATURES
•
•

Similar to the MC6800
Efficient Use of Program Space

IRQ

(31

LI

(41
TIMER

OS

• Versatile Interrupt Handling

(61

•

True Bit Manipulation

(71

•

Addressing Modes with Indexed Addressing for Tables

•

Efficient Instruction Set

•

Memory Mapped I/O

(81
(91
(101

• Two Power Saving Standby Modes

PB5
PB6
PB7

GENERIC INFORMATION

BO
Package
Type

Frequency

(MHz)

Temperature

Generic Number

Ceramic
L Suffix
Cerdip
S Suffix
Plastic
P Suffix
Leadless Chip Carrier
Z Suffix

1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0

O°C to 70°C
- 40°C to 85°C
O°C to 70°C
-40°C to 85°C
O°C to 70°C
- 40°C to 85°C
O°C to 70°C
-40°C to 85°C

MC146805E2L
MCl46805E2CL
MC146805E2S
MC146805E2CS
MCl46805E2P
MCl46805E2CP
MCl46805E2Z
MC146805E2CZ

B1
B2
16 (171

B3

17 (181

B4

18 (191

B5

19 (201

B6

20 (211

B7

Pin numbers in parentheses represent equivalent Z
suffix chip carrier pins.
This document contains information on a new product Specifications and Information herein
are subject to change without notice

3-876

MC146805E2

MAXIMUM RATINGS Ivoltages referenced to VSSI
Ratings
Supply Voltage
All Input Voltages Except OSC1

Symbol

Value

Unit

VOO

-0.3 to +8.0

V

Vin

VSS-0.5 to VOO+0.5

V

I

10

mA

Current Drain Per Pin Excluding VOO and VSS

h

Operating Temperature Range
MC146805E2
MC146805E2C

to TH

o to 70

TA

°C

-40 to 85
Tstg

Storage Temperature Range

THERMAL CHARACTERISTICS
Characteristics

Symbol

Thermal Resistance
Plastic
Cerdip
Ceramic
Chip-Carrier

()JA

Value
100
60
50
TBO

Unit

°C/W

- 55 to + 150

°C

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance
circuit. For proper operation it is recommended that Vin and Vout be constrained to the
range VSSslVin or VoutlsVDO. Reliability
of operation is enhanced if unused inputs are
tied to an appropriate logic voltage level
le.g., either VSS or VOOI.

FIGURE 1 - MICROPROCESSOR BLOCK DIAGRAM

TIMER

PAD
PAl
PA2
Port
A
1/0
lines

PA3

Data
Dir
Reg

PA4

PA6

Index
Register

Bl

Mux
Bus
Drive

B2
B3
B4

PBO
Port
B
Reg

Data
Dir
Reg

Multiplexed
Addressl
Data
Bus

B5

CPU

B6

POinter SP

PBl

PB3

CPU
Control

A

Stack

PA7

PB2

8

Condition
Code
5 Register CC

PA5

Port
B
1/0
Lines

BO

Accumulator
Port
A
Reg

B7

Program
Counter
High PCH
Program
Counter
low PCl

ALU

A8
Address
Drive

A9
AlO

Address
Bus

All
15

PB4

A12

PB5
PB6
AS

PB7

112 x 8
RAM

3-877

Bus
Control

Address Strobe

DS

Data Strobe (<1>21

R/W

Read/Write

11

MC146805E2

DC ELECTRICAL CHARACTERISTICS @ 3.0 V (Voo = 3.0 Vdc, VSS = 0, T A = TL to TH, unless otherwise noted)
Characteristics
Output Voltage (lLoad:S 10.0 ",A)
Total Supply Current (CL = 50 pF - No dc Loads, tcyc= 5 "'s)
Run (VIL=0.2 V, VIH=VOO-0.2 V)

Min

Max

VOL
VOH

-

0.1

VOO-0.1

-

Unit
V

mA

See Note Below)

100

-

1.3

Wait (Test Conditions -

200

",A

Stop (Test Conditions -

See Note Below)

100

-

100

",A

100

Output High Voltage
(lLoad=0.25 mAl AB-A12, BO-B7, OS, AS, R/IN

VOH

2.7

-

V

VOH

2.7

-

V

Output Low Voltage
(ILoad= 0.25 mAl AB-A 12, BO-B7, PBO-PB7, OS, AS, R/W,PAO-PA7

VOL

-

0.3

V

Input High Voltage
PAO-PA7, PBO-PB7, BO-B7

(ILoad=0.1 rnA) PAO-PA7, PBO-PB7

I

Symbol

VIH

2.1

-

V

TIMER, IRQ, RESET

VIH

2.5

-

V

OSC1

VIH

2.1

-

V

VIL

-

0.5

V

Input Low Voltage (All Inputs)
Frequency of Operation
Crystal

fosc

-

1.0

MHz

External Clock

fosc

dc

1.0

MHz

lin

-

±1

",A

ITSL

-

±10

",A

Cin

-

B.O

pF

Cout

-

12.0

pF

Input Current
RESET, IRQ, TIMER, OSC1
Hi-Z Output Leakage
PAO-PA7, PBO-PB7, BO-B7
Capacitance
RESET, IRQ, TIMER
Capacitance
OS, AS, R/W, AB-A12, PAO-PA7, PBO-PB7, BO-B7

NOTE: Test conditions for Quiescent Current Values are:
Port A and B programmed as inputs.
VIL = 0.2 V for PAO-PA7, PBO-PB7, and BO-B7.
VIH=VOO-0.2 V for RESET, IRQ, and TIMER
OSC1 input is a squarewave from VSS + 0.2 V to VOO - 0.2 V.
OSC2 output load (including tester) is 35 pF maximum
Wait mode 100 is affected linearly by this capacitance.

3-878

MC146805E2

DC ELECTRICAL CHARACTERISTICS @ 5.0 V IVOO= 5.0 Vdc ± 10%, VSS =0, T A = h to TH, unless otherwise noted)
Characteristics
Output Voltage IILoadS10.0 /-IA)
Total Supply Current ICL = 130 pF - On Bus, CL = 50 pF - On Ports,
No dc Loads, tcyc = 1.0 /-Is, VIL = 0.2 V, VIH = VOO - 0.2 V)
Run

Symbol

Min

Max

VOL
VOH

-

0.1

VOO-0.1

-

Unit
V

100

-

10

mA

Wait ITest Conditions -

See Note Below)

100

-

1.5

mA

Stop ITest Conditions -

See Note Below)

100

-

200

/-I A

VOH

4.1

-

V

VOH

4.1

-

V

VOL

-

0.4

V

Output High Voltage
IILoad= 1.6 mAl A8-A12, BO-B7, OS, AS, R/W
IILoad-0.36 mAl PAO-PA7, PBO-PB7
Output Low Voltage
IILoad= 1.6 mAl AS-A12, BO-B7, PAO-PA7, PBO-PB7, OS, AS, Rlw
Input High Voltage
PAO-PA7, PBO-PB7, BO-B7

VIH

VOD-2.0

-

V

TIMER, IRQ, RESET

VIH

VOD-O.S

-

V

OSC1

VIH

VOD-1.5

-

V

VIL

-

O.S

V

-

5.0

MHz

Input Low Voltage IAII Inputs)
Frequency of Operation
Crystal

fosc

External Clock

fosc

dc

5.0

MHz

lin

-

±1

/-I A

ITSI

-

± 10

!LA

Cin

-

S.O

pF

Cout

-

12.0

pF

Input Current
RESET, IRQ, TIMER, OSC1
Hi-Z Output Leakage
PAO-PA7, PBO-PB7, BO-B7
Capacitance
RESET, IRQ, TIMER
Capacitance
OS, AS, R/W, AS-A12, PAO-PA7, PBO-PB7, BO-B7
NOTE Test conditions for Quiescent Current Values are
Port A and B programmed as Inputs
VIL = 0.2 V for PAO-PA7, PBO-PB7, and BO-B7
VIH=VOO-0.2 V for RESET, IRQ, and TIMER
OSC1 input is a squarewave from VSS + 02 V to VOO - 0.2 V
OSC2 output load lincluding tester) IS 35 pF rrlaximum
Wait mode 1100) IS affected linearly by thiS capaCItance

3-879

11

MC146805E2

TABLE 1 -

CONTROL TIMING (VSS=O, TA=TL to TH)
VOO=5.0 V ± 10%
fosc = 5.0 MHz

VOO=3.0 V
fosc= 1 MHz
Characteristics

Symbol

Min

Typ

Max

Min

Typ

Max

Unit

1/0 Port Timing - Input Setup Time (Figure 3)

tpVASL

500

-

-

250

-

-

ns

Input Hold Time (Figure 3)

tASLPX

100

-

-

100

-

-

ns

Output Delay Time (Figure 3)

tASLPV

-

-

0

-

-

0

ns

Interrupt Setup Time (Figure 6)

tlLASL

2

-

-

0.4

-

-

I'S

Crystal Oscillator Startup Time (Figure 5)

tOXOV

-

30

300

-

15

100

ms

Wait Recovery Startup Time (Figure 7)

WASH

-

-

10

-

-

Stop Recovery Startup Time (Crystal Oscillator! (Figure 8) tlLASH
Required Interrupt Release (Figure 6)
tDSLIH

-

30

300

-

-

-

5

0.5

-

1.5

-

-

J.ls

-

1.0

tcyc

1.0

-

Timer Pulse Width (Figure 7)

itS

15

100

ms

-

-

1.0

I's

0.5

-

-

tcyc

tRL

5.5

-

Timer Period (Figure 7)

tTLTL

1.0

-

Interrupt Pulse Width Low (Figure 16)

tlLlH

1.0

-

-

Interrupt Pulse Period (Figure 16)

lJLlL

~

-

~

-

1000

-

200

-

-

OSCl Pulse Width High

tOLOL
tOH

-

-

350

-

-

75

-

OSCl Pulse Width Low

tOL

350

-

-

75

-

-

tTH, tTL

Reset Pulse Width (Figure 5)

I

2

Oscillator Cycle Period (115 of t cyc )

tcyc
tcyc
ns
ns
ns

*The minimum period tl LI L should not be less than the number of tcyc cycles it takes to execute the interrupt service routine plus 20 tcyc
cycles.

FIGURE 2 -

EQUIVALENT TEST LOAOS

CMOS Equivalent

Test Point

1

r

C=50 pF, PAO-PA7, PBO-PB7
= 130 pF, A8-A12, BO-B7, OS, AS, R/IN
with VOD=5 V ± 10%

3-880

MC146805E2

FIGURE 3 - 1/0 PORT TIMING
(VLow=0.8 V, VHigh=VDD-2.0 V, VDD=5.0 ± 10%
TA=TL to TH, CL on Port=50 pF, fosc=5 MHz)
Address
Strobe

Port
Input - - - - - {

..,----tpVASL-----.,..----tASLPX

I

Port
Output

* The address strobe of the first cycle of the next instruction.

TABLE 2 - BUS TIMING ITA = TL to TH, VSS = 0 V) See Flgure4

Num

Characteristics

1

Cycle Time

2

Pulse Width, DS Low

3
4

Symbol

tcyc
PWEL
PWEH

Pulse Width, DS High

fosc= 1 MHz
VOO=3.0 V
50 pF Load

fosc =5MHz
VOO=5.0 V ± 10%,
1 TTL
and 130 pF Load

Min

Max

Min

Max

5000
2800
1800

de

1000
560
375

de

-

-

8

Clock Transition
RIW Hold

9
11
16

Non-Muxed Address Hold
RIW Delay from DS Fall
Non-Muxed Address Delay from AS Rise

17
18

MPU Read Data Setup
Read Data Hold

tDSR
tDHR

19
21

MPU Data Delay, Write
Write Data Hold

tDDW

-

0

-

800

-

55

-

23
24
25
26
27
28

Muxed Address Delay from AS Rise
Muxed Address Valid to AS Fall
Muxed Address Hold
Delay DS Fall to AS Rise
Pulse Width, AS Hiqh
Delay, AS Fall to DS Rise

tDHW
tRHD

0
600
250
800

250

0
55
60
160

120

t,tf
tRII',IH
tAH
tAD
tADH

tASL
tAHI
tASD
PWASH
tASED

3-881

100

-

Unit

ns
ns
ns

-

30

-

10

-

ns
ns __

800

-

100

-

0

500
200

200
0

-

115

800

0

160
120

-

10

-

750
-

850

-

800

-

-

0

175
160

-

ns

300
100

ns
ns

-

ns
ns

-

180
-

ns
ns
ns
ns
ns
ns
ns
ns

..
S

-n
~

FIGURE 4 -

MC146805E2 BUS TIMING

en

00

o

U1

m
N

AS

OS

w

R/W

6:>
ex>

'"
AB-A12

BO-B7

BO-B7
MPU Read

* VHigh=2.0 V,

VLow=05 V for VOO=3 V for outputs only.
VHigh= VOO- 2.0 V, VLow= O.B V for VOO= 5 V ± 10% for outputs only

s:
(")
...a

FIGURE 5 -

~

POWER-ON RESET AND RESET TIMING

en

00

o

U1

Voo/
OSCl ~7IIT!IT!IZ!/;~VI!JJ!IlJ/i//J1J1////7IlIZ!!I
RFSET~__
:;,;
flfl/J/I!L~!//Idl/IIIITffi'ZlJ/////II!ZZTIZZ/IIJZZlI/71 iIOl7II!IIll/
I 'oxov
- -'Rl-<'
_J/IZ!/lj
AS _ _ _

192"",c-~

~

------'1

Unmux
A8-A12
Address

BUS:::::::~'~--~--~--~~~;;~~-~~~~~(E~~JIX=======)c=======X=X~

Mux BO-B7
Address/Oata
Bus

RIW

~

FE

Z7IZVZ7IZ/

\

'C7

w

cD

CD

v,)'
Oscillator Waveform

Crystal Oscillator Connections

MC146805E2
10 MO

38~39

OSC2~n~

I

COSC2

I

OSCl

Crystal Parameters Representative Frequencies

RS max
CO
Cl
Q

COSCl
COSC2

5.0 MHz

4.0 MHz

1.0 MHz

500
8 pF
0.02 pF
50k
15-30 pF
15-25 pF

750
7 pF
0.012 pF
40 k
15-30 pF
15-25 pF

4000
5 pF
0.008 pF
30 k
15-40 pF
15-30 pF

COSCl
Crystal CircUit

~~~39

0~~1
0~C2

II

101

0~9Cl

m
N

•
FIGURE 6 -

s:

o....

~
~

IRQ AND TCR7 INTERRUPT TIMING

CO

o

f--- n -----!-- n + ,----+-- n + 2 ---+- n + 3 --+--n +4------1---n + 5--1---n + 6--+e- n t 7 --I-- n +8--+- n + 9 ~

U1

m
N

AS

OS
Unmux

Ad~~~~'~us

-----A

I"_H."

r'::~_, ~L

f\..Jv------J'

"'------A

I "

IRQ or TCR7

Mux BO·B7
Address/
Bus Data

R/W

=.J(~C-'-:)Lx..--.x:...JL£~:......J~.A~~.AJ.~~J'-"--~-"--...A~~~~~-~:'mrA\-I\....~:O;[i"""C~~r----.J'--.J~RTi..J
..
,,_. ,,-

-.J''-----I'-

r_~_

W---~

I

"'tDS llH - The interrupting deVice must release the IRQ line within

ttllS

\

'L

time to prevent subsequent recognition of the same Interrupt

(,.)

00

(X)
~

FIGURE 7 - TIMER INTERRUPT AFTER WAIT INSTRUCTION: TIMING

OS
Unmux

Ad~~~l~us-X-------J(~~---X~~~~~--------------~o-----~n-'----co-~--~~~----cp~----~~~---PF7~~~'~~----J~--­
Mux BO-B7
Address/Data
Bus
R/W

New PCrl

'1Tm771Tml

'"

'

\

I

New PCl 1st Op CodeRlnt ,
olltlne

3:
o
~

~

en
CO
o

U'I

m
N

FIGURE 8 -

05C2 *

11l/lfl///III7I1T!l7l1 ."

IRQ

\

INTERRUPT RECOVERY FROM STOP INSTRUCTION: TIMING

' - 11/21/11!l/Zl//!/;vJ;vu/llJITII!I///Jj~/l//II/TJ//////////d///I//JIIflJ/diJ/////flIJflflTl7//J
-l-tILASH-t--1920

tcyc~

~----------~--~\r---------------------------------------------

AS

w
eX>

DS

ex>

(J1

Unmux
A8-A12

Add"~B"'~
M
BO B7
Addr+ 1

Ad~r~ss/-Data

<

8E

=

)\\\\\\\\\\\\\\\';

Bus

A

,.

.r'-'!-

r-L-M

"

~

R/W

*:

Represents the internal gating of the OSCl input pin.
tcyc is one instruction cycle (for fose = 5 MHz. teye = 1 ,..5)

I!I

'-''-'

I4+-

MC146805E2

FUNCTIONAL PIN DESCRIPTION
VDD AND VSS
VDD and VSS provide power to the chip. VDD provides
power and VSS is ground.

lRQ (MASKABLE INTERRUPT REQUEST)

I

IRQ is both a level-sensitive and edge-sensitive input
which can be used to request an interrupt sequence. The
MPU completes the current instruction before it responds to
the request. If IRQ is low and the interrupt mask bit (I bit) in
the condition code register is clear, the MPU begins an interrupt sequence at the end of the current instruction. The interrupt circuit recognizes both a "wire ORed" level as well as
pulses on the IRQ line (see Interrupt section for more
details). TRC2 requires an external resistor to VDD for "wire
OR" operation.
RESET

The RESET input is not required for start-up but can be
used to reset the MPU internal state and provide an orderly
software start-up procedure. Refer to the Reset section for a
detailed description.

BO-B7 (ADDRESS/DATA BUS)

The 80-87 bidirectional lines constitute the lower order
addresses and data. These lines are multiplexed, with address present at address strobe time and data present at data
strobe time. When in the data mode, these lines are bidirectional, transferring data to and from memory and peripheral
devices as indicated by the R/W pin. As outputs in either the
data or address modes, these lines are capable of driving one
standard TTL load and 130 pF.
OSC1,OSC2
The MCl46805E2 provides for two types of oscillator inputs - crystal circuit or external clock. The two oscillator
pins are used to interface to a crystal circuit, as shown in
Figure 5. If an external clock is used, it must be connected to
OSC1. The input at these pins is divided by five to form the
cycle rate seen on the AS and DS pins. The frequency range
is specified by fos c . The OSCl to bus transitions relationships are provided in Figure 9 for system designs using
oscillators slower than 5 MHz.
CRYSTAL - The circuit shown in Figure 5 is recommended when using a crystal. The internal oscillator is designed to
interface with an AT-cut parallel resonant quartz crystal
resonator in the frequency range specified for fosc in the
electrical characteristics table. An external CMOS oscillator
is recommended when crystals outside the specified ranges
are to be used. The crystal and components should be
mounted as close as possible to the input pins to minimize
output distortion and start-up stabilization time.

TIMER
The TIMER input is used for clocking the on-chip timer.
Refer to Timer section for a detailed description.
AS (ADDRESS STROBE)

Address strobe (AS) is an output strobe used to indicate
the presence of an address on the 8-bit multiplexed bus. The
AS line is used to demultiplex the eight least significant address bits from the data bus. A latch controlled by address
strobe should capture addresses on the negative edge. This
output is capable of driving one standard TTL load and 130
pF and is available at fosc + 5 when the MPU is not in the
WAIT or STOP states.

EXTERNAL CLOCK - An external clock should be applied to the OSCl input with the OSC2 input not connected,
as shown in Figure 10.

LI (LOAD INSTRUCTION)

This output is used to indicate that a fetch of the next opcode is in progress. LI remains low during an external or
timer interrupt. The LI output is used only for certain debugging and test systems. For normal operations this pin is not
connected. The LI output is capable of driving two standard
LSTTL loads and 50 pF. This Signal overlaps data strobe.

DS (DATA STROBE)
This output is used to transfer data to or from a peripheral
or memory. DS occurs anytime the MPU does a data read or
write. DS also occurs when the MPU does a data transfer to
or from the MPU internal memory. Refer to Table 2 and
Figure 4 for timing characteristics. This output is capable of
driving one standard TTL load and 130 pF. DS is a continuous signal at fosc + 5 when the MPU is not in the WAIT
or STOP state. Some bus cycles are redundant reads of
opcode bytes.

PAO-PA7
These eight pins constitute input/ output port A. Each line
is individually programmed to be either an input or output
under software control via its data direction register as
shown in Figure 11(b). An I/O pin is programmed as an output when the corresponding DDR bit is set to a "1", and as
an input when it is set to a "0". In the output mode the bits
are latched and appear on the corresponding output pins. An
MPU read of the port bits programmed as outputs reflects
the last value written to that location. When programmed as
an input, the input data bit(s) are not latched. An MPU read
of the port bits programmed as inputs reflects the current
status of the corresponding input pins. The I/O port timing is
shown in Figure 3. See typical I/O port circuitry in Figure 11.
During a power-on reset or external reset, all lines are configured as inputs (zero in data direction register!. The output
port register is not initialized by reset. The TTL compatible
three-state output buffers are capable of driving one standard TTL load and 50 pF. The DDR is a read/write register.

R/W (READ/WRITE)
The R/W output is used to indicate the direction of data
transfer for both internal memory and I/O registers, and external peripheral devices and memories. This output is used
to indicate to a selected peripheral whether the MPU is going
to read or write data on the next data strobe (R/W
low = processor write; R/W high = processor read). The
R/W output is capable of driving one standard TTL load and
130 pF. The normal standby state is read (high).
AS-A12 (HIGH ORDER ADDRESS LINES)

The A8-A 12 output lines constitute the higher order nonmultiplexed addresses. Each output line is capable of driving
one standard TTL load and 130 pF.

3-886

MC146805E2

FIGURE 9 -

OSC1 TO BUS TRANSITIONS

OSC1

AS

DS

I

R/W

A8-A12

BO-B7
MPU Read

BO-B7
MPU Write

-----i

*Read data "latched" on DS fall

FIGURE 10 -

EXTERNAL CLOCK CONNECTION

OSC1 39
OSC2
No
Connection
(NC)

38
MC146805E2

PBO-PB7
These eight pins interface with input/output port B. Refer
to PAO-PA7 description for details of operation.

MEMORY ADDRESSING
The MC146805E2 is capable of addressing 8192 bytes of
memory and I/O registers. The address space is divided into
internal memory space and external memory space, as
shown in Figure 12.

The internal memory space is located within the first 128
bytes of memory (first half of page zero) and is comprised of
the I/O port locations, timer locations, and 112 bytes of
RAM. The MPU can read from or write to any of these locations. A program write to on-chip locations is repeated on
the external bus to permit off-chip memory to duplicate the
content of on-chip memory. Program reads to on-chip locations also appear on the external bus, but the MPU accepts
data only from the addressed on-chip location. Any read
data appearing on the input bus is ignored.
The stack pointer is used to address data stored on the
stack. Data is stored on the stack during interrupts and
subroutine calls. At power-up, the stack pointer is set to
$OO7F and it is decremented as data is pushed onto the
stack. When data is removed from the stack, the stack
pointer is incremented. A maximum of 64 bytes of RAM is
available for stack usage. Since most programs use only a
small part of the allotted stack locations for interrupts and/ or
subroutine stacking purposes, the unused bytes are usable
for program data storage.
All memory locations above location $OO7F are part of the
external memory map. In addition, ten locations in the I/O
portion of the lower 128 bytes of memory space, as shown in

3-887

MC146805E2

FIGURE 11 -

TYPICAL PORT liD CIRCUITRY

To
And
From

CPU

I

(b)

Data Direction
Register

$0004

PortA
Register

$0000

Pin

PA7

PA6

PA5

PA4

PA3

PAl

PAl

PAO

Data Direction
Register

$0005

Port B
Register

$0001

Pin

PB7

PB6

PB5

PB4

PB3

PB2

PBl

TABLE 3 - I/O PIN FUNCTIONS
R/W

0

DDR

0

0

1

1

0

1

1

I/O Pin Functions
The I/O pin is in input mode. Data is written
into the output data latch.
Data is written into the output data latch and
output to the I/O pin.
The state of the I/O pin is read.
The I/O pin is in an output mode. The output
data latch is read.

3·888

PBO

MC146805E2

Figure 12, are part of the external memory map. All of the external memory space is user definable except the highest 10
locations. Locations $1FF6 to $1FFF of the external address
space are reserved for interrupt and reset vectors (see
Figure 12),

INDEX REGISTER (X)

The X register is an 8-bit register which is used during the
indexed modes of addressing. It provides an 8-bit value
which is used to create an effective address. The index
register is also used for data manipulations with the readmodify-write type of instructions and as a temporary storage
register when not performing addressing operations.

REGISTERS
The MC146805E2 contains five registers as shown in the
programming model in Figure 13. The interrupt stacking
order is shown in Figure 14.
ACCUMULATOR (A)

PROGRAM COUNTER (PC)
The program counter is a 13-bit register that contains the
address of the next instruction to be executed by the
processor.

This accumulator is an 8-bit general purpose register used
to hold operands and results of arithmetic calculations and
data manipulations.

FIGURE 12 -

Aeo,,,
Via {
Page 0
Direct
Addressing

$0000

I/O Ports
Timer
RAM

127
128

I

MPU ADDRESS MAP

1
$OO7F

Port A Data Register

$0000

Port B Data Register

$0001

External Memory Space

$0002

External Memory Space

$0003

$0080

255
1-256

\

- - - --

- --

4

$OOFF
$0100

External
Memory
Space
(8064 Bytesl

Port A Data Direction Register

$0004

Port B Data Direction Register

$0005

External Memory Space

$0006

External Memory Space

$0007

Timer Data Register

$0008

Timer Control Register

$0009
~OOOA

10
External Memory
Space

15

$OOOF

16

$0010

63
64

RAM
(112 Bytesl

$OO3F

I-

/ 7 $0040
./

8182~

-

-

-

-

-

-

-

--

./

~I~ I~er~t.:.r0~W~t ~at=-On~ $lFF6-$lF~7
Timer Interrupt

~

Interrupt
Vectors
{

-

-

Ext;;:;;ailnt;ru; - SWI

-

~

-

-

-

-

/"

$lFF8-$lFF9

~ -

-

./

-

-

/

$lFFA-$lF~B

./
/"./ Stack (64 Bytes Maxi

I

$lFFC-$lFFD

8191L.-_ _ _ _ _ _ _ _ _ _ _---'

/"
$lFFE-$lFFF
127 V

3-889

"

./

f

$007F

MC146805E2

FIGURE 13 -

PROGRAMMING MODEL

0

7

I
I

A

12

I

Accumulator

I

Index Register

0

7

X

8 7

PCl

PCH

Program Counter

0

12

1010101010101

I

SP

Stack Pointer

CC

l§
1

I

FIGURE 14 -

N

Z

C

condit. ion Code Register
Carry/ Borrow
Zero
Negative
Interrupt Mask
Half Carry

STACKING ORDER
Stack

Increasing Memory
Addresses

1:

N

111111

Condition Code Register
Accumulator
Index Register

o I0

I0 I

PCH
PCl

Unstack

I1

Decreasing Memory
Addresses

T

NOTE: Since the stack pointer decrements during pushes, the PCl is
stacked first, followed by PCH, etc. Pulling from the stack is in
the reverse order.

STACK POINTER (SP)

The stack pointer is a 13-bit register containing the address of the next free location on the stack. When accessing
memory, the seven most significant bits are permanently set
to 0000001. They are appended to the six least significant
register bits to produce an address within the range of $OO7F
to $0040. The stack area of RAM is used to store the return
address on subroutine calls and the machine state during interrupts. During external or power-on reset, and during a
"reset stack pointer" instruction, the stack pointer is set to
its upper limit ($OO7F). Nested interrupts and/ or subroutines
may use up to 64 (decimal) locations, beyond which the
stack pointer "wraps around" and points to its upper limit,
thereby losing the previously stored information. A
subroutine call occupies two RAM bytes on the stack, while
an interrupt uses five bytes.

CONDITION CODE REGISTER (CC)

The condition code register is a 5-bit register in which each
bit is used to indicate the results of the instruction just executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each of the
five bits is explained below.
HALF CARRY BIT (H) - The H bit is set to a one when a

carry occurs between bits 3 and 4 of the ALU during an ADD
or ADC instruction. The H bit is useful in binary coded
decimal addition subroutines.
INTERRUPT MASK BIT (I) - When the I bit is set, both
the external interrupt and the timer interrupt are disabled.
Clearing this bit enables the above interrupts. If an interrupt
occurs while the I bit IS set, the interrupt is latched and will
be processed when the I bit is next cleared.
NEGATIVE BIT (N) - When set, this bit indicates that the
result of the last arithmetic, logical, or data manipulation was
negative (bit 7 in the result is a logical one).
ZERO BIT (Z) - When set, this bit indicates that the result
of the last arithmetic, logical, or data manipulation was zero.
CARRY BIT (C) - The C bit is set when a carry or a borrow out of the ALU occurs during an arithmetic instruction.
The C bit is also modified during bit test, shift, rotate, and
branch types of instruction.

RESETS
The MCl46805E2 has two reset modes: an active low external reset pin (RESET) and a power-on reset function; refer
to Figure 5.

MC146805E2

RESET (PIN #1)

TIMER INTERRUPT

The RESET input pin is used to reset the MPU and provide
an orderly software start-up procedure. When using the
external reset mode, the RESET pin must stay low for a minimum of one tRL. The RESET pin is provided with a Schmitt
trigger to improve its noise immunity capability.

If the timer mask bit (TCR6) is cleared, then each time the
timer decrements to zero (transitions from $01 to $00) an interrupt request is generated. The actual processor interrupt
is generated only if the interrupt mask bit of the condition
code register is also cleared. When the interrupt is recognized, the current state of the machine is pushed onto the
stack and the I bit in the condition code register is set. This
masks further interrupts until the present one is serviced.
The processor now vectors to the timer interrupt service
routine. The address for this service routine is specified by
the contents of $1 FF8 and $1 FF9 unless the processor is in a
WAIT mode, in which case users of mask versions BP4XXXX and AW9XXXX should refer to the appendix for additional information regarding exceptions to this function. The
contents of $1 FF6 and $1 FF7 specify the service routine.
Also, software must be used to clear the timer interrupt request bit (TCR7). At the end of the timer interrupt service
routine, the software normally executes an RTI instruction
which restores the machine state and starts executing the interrupted program.

POWER-ON RESET

The power-on reset occurs when a positive transition is
detected on VOO. The power-on reset is used strictly for
power turn-on conditions and should not be used to detect
any drops in the power supply voltage. There is no provision
for a power-down reset. The power-on circuitry provides for
a 1920 tcyc delay from the time of the first oscillator operation. If the external reset pin js low at the end of the 1920
tcyc time out, the processor remains in the reset condition.
Either of the two types of reset conditions causes the
following to occur:
- Timer control register interrupt request bit (bit 7) is
cleared to a "0".
- Timer control register interrupt mask bit (bit 6) is set to
a "1".
- All data direction register bits are cleared to a "0" (inputs).
- Stack pointer is set to $OO7F.
- The address bus is forced to the reset vector ($1FFE,
$1FFFl.
Condition code register interrupt mask bit (I) is set to a
"1".
STOP and WAIT latches are reset.
External interrupt latch is reset.
All other functions, such as other registers (including output ports), the timer, etc., are not cleared by the reset conditions.

INTERRUPTS
The MC146805E2 may be interrupted by one of three different methods: either one of two maskable hardware interrupts (external input or timer) or a non-maskable software interrupt (SWIl. Systems often require that normal processing
be interrupted so that some external event may be serviced.
Interrupts cause the processor registers to be saved on the
stack and the interrupt mask set to prevent additional interrupts. The RTI instruction causes the register contents to be
recovered from the stack and a return to normal processing.
The stacking order is shown in Figure 14.
Unlike RESET, hardware interrupts do not cause the current instruction excution to be halted, but are considered
pending until the current instruction execution is complete.
When the current instruction is complete, the processor
checks all pending hardware interrupts and if unmasked,
proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Note that masked interrupts are latched for later interrupt service.
If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed as any other instruction. Refer to Figure 15 for the interrupt and instruction
processing sequence.

EXTERNAL INTERRUPT
If the interrupt mask bit of the condition code register is
cleared and the external interrupt pin iRQ is "low," then the
external interrupt occurs. The action of the external interrupt
is identical to the timer interrupt with the exception that the
service routine address is specified by the contents of $1 FFA
and $1FFB. The interrupt logiC recognizes both a "wire
ORed" level and pulses on the external interrupt line. Figure
16 shows both a functional diagram and timing for the interrupt line. The timing diagram shows two different treatments
of the interrupt line (iRa) to the processor. The first configuration shows many interrupt lines "wire ORed" to form
the interrupts at the processor. Thus, if after servicing an interrupt the IRQ remains low, then the next interrupt is
recognized. The second method is single pulses on the interrupt line spaced far enough apart to be serviced. Users of
mask versions BP4XXXX and AW9XXXX should refer to the
appendix regarding exceptions to this function. The
minimum time between pulses is a function of the length of
the interrupt service routine. Once a pulse ocurs, the next
pulse should not occur until the MPU software has exited the
routine (an RTI occursl. This time (tILlLl is obtained by adding 20 instruction cycles (one cycle tcyc = 5/foscl to the
total number of cycles it takes to complete the service
routine including the RTI instruction; refer to Figure 6.
SOFTWARE INTERRUPT (SWI)

The software interrupt is an executable instruction. The
action of the SWI instruction is similar to the hardware interrupts. The SWI is executed regardless of the state of the interrupt mask in the condition code register. The service
routine address is specified by the contents of memory locations $1FFC and $1FFO. See Figure 15 for interrupt and instruction processing flowchart.
STOP
The STOP instruction places the MC146805E2 in a low
power consumption mode. In the STOP function the internal
oscillator is turned off, causing all internal proceSSing and
the timer to be halted; refer to Figure 17. The OS and AS
lines go to a low state and the R/W line goes to a high state.

3-891

II

MC146805E2

FIGURE 15 -

I

RESET AND INTERRUPT PROCESSING FLOWCHART

Stack
PC,X, A, CC

O-DDRs
CLR iRCi Logic
FF-Timer
7F-Prescaler
7F-TCR

Timer
Put 1FFE on
Address Bus

Load PC From:
SWI: 1FFCI1 FFD
iRO: 1FFA/ 1FFB
TIMER: lFF8/1FF9
Timer Wait: 1FF6/ 1FF7

Fetch
Instruction

SWI

Load PC
from
1FFE/ 1FFF

Execute All
Instruction
Cycles

3-892

MC146805E2

FIGURE 16 - EXTERNAL INTERRUPT
la) Interrupt Functional Diagram

VDD - - - D

External
Interrupt
Request

0..-.-----1

>-.............- - Q C

Interrupt Pin

a

I Bit (CCR)

Power-On Reset

I

External Reset
External Interrupt
Being Serviced

Ib) Interrupt Mode Diagram
(1)

----

}

•

IROn

Wire ORed Condition
If aft.er servicing an interrupt the iRQ remains low, then the next interrupt is
recognized.

rno(MPU)~L__________________________~

(2)

iRO~tlLIH

~

U

tILlL~~

3·893

Pulse Condition
The minimum pulse width (tILlH) is one
tcyc· The period tlUL should not be less
than the number of tcyc cycles it takes to
execute the interrupt service routine plus
20 tcyc cycles.

MC146805E2

The multiplexed addressl data bus goes to the data input
state (as shown in Figure 8). The high order address lines remain at the address of the next instruction. The MPU remains in the STOP mode until an external interrupt or reset
occurs.
During the STOP mode, timer control register (TCR) bits 6
and 7 are altered to remove any pending timer interrupt requests and to disable any further timer interrupts. External
interrupts are enabled in the condition code register. All
other registers and memory remain unaltered. All 1/0 lines
remain unchanged.
FIGURE 17 -

STOP FUNCTION FLOWCHART

which is allowed to count in a normal sequence. The R/W
line goes to a high state, the multiplexed addressl data bus
goes to the data input state, and the DS and AS lines go to
the low state (as shown in Figure 7). The high order address
lines remain at the address of the next instruction. The MPU
remains in this state until an external interrupt, timer interrupt, or a reset occurs.
During the WAIT mode, the I bit in the condition code
register is cleared to enable interrupts. All other registers,
memory, and 1/0 lines remain in their last,state. The timer
may be enabled to allow a periodic exit from the WAIT
mode. If an external and a timer interrupt occur at the same
time, the external interrupt is serviced first; then, if the timer
interrupt request is not cleared in the external interrupt
routine, the normal timer interrupt (not the timer WAIT interrupt) is serviced since the MPU is no longer in the WAIT
mode.

TIMER

I

The MPU timer contains a single 8-bit software programmable counter (timer data register) with 7-bit software
selectable prescaler. Figure 19 shows a block diagram of the
timer. The counter may be preset under program control and
decrements towards zero. When the counter decrements to
zero, the timer interrupt request bit, i.e., bit 7 of the timer
control register (TCR), is set. Then if the timer interrupt is
not masked, i.e., bit 6 of the TCR and the I bit in the condition code register are both cleared, the processor receives an
interrupt. After completion of the current instruction, the
processor proceeds to store the appropriate registers on the
stack, and then fetches the timer interrupt vector from locations $1 FF8 and $1 FF9 in order to begin servicing the interrupt. If the MPU is interrupted by the timer while in the
WAIT mode, the interrupt vector fetch would be from locations $1FF6 and $1FF7.
The counter continues to count after it reaches zero,
allowing the software to determine the number of internal or
external input clocks since the timer interrupt request bit was
set. The counter may be read at any time by the processor
without disturbing the count. The content of the counter
becomes stable prior to the read portion of a cycle and does
not change during the read. The timer interrupt request bit
remains set until cleared by the software. If a read occurs
before the timer interrupt is serviced, the interrupt is lost.
TCR7 may also be used as a scanned status bit in a noninterrupt mode of operation (TCR6 = 1).
The prescaler is a 7-bit divider which is used to extend the
maximum length of the timer. Bit 0, bit 1, and bit 2 of the
TCR are programmed to choose the appropriate prescaler
output which is used as the counter input. The processor
cannot write into or read from the prescaler; however, its
contents are cleared to all "Os" by the write operation into
TCR when bit 3 of the written data equals 1, which allows for
truncation-free counting.
The timer input can be configured for three different
operating modes, plus a disable mode, depending on the
value written to the TCR4, TCR5 control bits. Refer to the
Timer Control Register section.

Stop Oscillator
And All Clocks
TCR Bit 7-0
TCR Bit 6-1
Clear I Bit

Yes

WAIT
The WAIT instruction places the MC146805E2 in a low
power consumption mode, but the WAIT mode consumes
somewhat more power than the STOP mode; refer to Table
1. In the WAIT function, the internal clock is disabled from
all internal circuitry except the timer circuit; refer to Figure
18. Thus, all internal processing is halted except the timer

TIMER INPUT MODE 1
If TCR4 and TCR5 are both programmed to a "0", the input to the timer is from an internal clock and the external
TIMER input is disabled. The internal clock mode can be

3-894

MC146805E2

FIGURE 18 - WAIT FUNCTION FLOWCHART

Oscillator Active
Clear I Bit
Timer Clock Active
All Other Clocks
Stop

I

used for periodic interrupt generation, as well as a reference
in frequency and event measurement. The internal clock is
the instruction cycle clock and is coincident with address
strobe (AS) except during a WAIT instruction. During a
WAIT instruction the AS pin goes to a low state but the internal clock to the timer continues to run at its normal rate.

TIMER INPUT MODE 2
With TCR4= 1 and TCR5= 0, the internal clock and the
TIMER input pin are ANDed to form the timer input signal.
This mode can be used to measure external pulse widths.
The external timer input pulse simply turns on the internal
clock for the duration of the pulse. The resolution of the

count in this mode is ± 1 clock and therefore accuracy improves with longer input pulse widths.

TIMER INPUT MODE 3
If TCR4= 0 and TCR5 = 1, then all inputs to the timer are
disabled.
TIMER INPUT MODE 4
If TCR4= 1 and TCR5= 1, the internal clock input to the
timer is disabled and the TIMER input pin becomes the input
to the timer. The external TIMER pin can, in this mode, be
used to count external events as well as external frequencies
for generating periodic interrupts.
Figure 19 shows a block diagram of the timer subsystem.

3-895

MC146805E2

FIGURE 19 - TIMER BLOCK DIAGRAM

External
Input

Write

Cleared by
TCR3
'~

I

____________

~~~

Read

Interrupt

____________--J/

Software Functions
NOTES:
1. Prescaler and timer data register are clocked on the falling edge of the internal clock (AS) or external input.
2. Timer data register is written to during data strobe (oS) and counts down continuously.

TIMER CONTROL REGISTER (TCR)

TCR5 TCR4

o

~

76543210
ITCR71TCR61TCR51TCR41TCR31TCR21TCR11TCROI
All bits in this register except bit 3 are read/write bits.

TCR7 - Timer interrupt request bit: bit used to indicate
the timer interrupt when it is logic" 1".
1 - Set whenever the counter decrements to zero, or under program control.
o - Cleared on external reset, power-on reset, STOP instruction, or program control.

0
1

TCR2
0
0
0
0
1
1
1
1

o-

TCR5 - External or internal bit: selects the input clock
source to be either the external TIMER pin or the internal
clock (unaffected by RESET).
1 - Select external clock source.
Select internal clock source (AS).

o-

1 - Enable external TIMER pin.
Disable external TIMER pin.

1
1

Internal clock (AS) to timer
AND of internal clock (AS) and TIMER
pin to timer
Inputs to timer disabled
TIMER pin to timer

TCR2, TCR1, TCRO - Prescaler address bits: decoded to
select one of eight outputs of the prescaler (unaffected by
RESET),

1 - Set on external reset, power-on reset, STOP instruction, or program control.
Cleared under program control.

o-

1

TCR3 - Timer Prescaler Reset bit: writing a "1" to this bit
resets the prescaler to zero. A read of this location always
indicates a "0" (unaffected by RESET).

TCR6 - Timer interrupt mask bit: when this bit is a logic
"1" it inhibits the timer interrupt to the processor.

TCR4 - External enable bit: control bit used to enable the
external TIMER pin (unaffected by RESET).

o

Prescaler
TCRl
TCRO
0
0
1
0
1
0
1
1
0
0
1
0
1
0
1
1

Result
+1
+2
+4
+8
+16
+32
+64
+ 128

INSTRUCTION SET
The MPU has a set of 61 basic instructions. They can be
divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type. All the instructions within a given type are presented in individual
tables.

3-896

MC146805E2

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One
operand is either the accumulator or the index register. The
other operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to
subroutine (JSR) instructions have no register operand.
Refer to Table 4.
READ-MODIFY-WRITE INSTRUCTIONS
These instructions read a memory location or a register,
modify or test its contents, and write the modified value
back to memory or to the register. The test for negative or
zero (TST) instruction is an exception to the read-modi.fywrite sequence since it does not modify the value. Refer to
Table 5.
BRANCH INSTRUCTIONS

This set of instructions branches if a particular condition is
met, otherwise no operation is performed. Branch instructions are two byte instructions. Refer to Table 6.
BIT MANIPULATION INSTRUCTIONS
The MPU is capable of setting or clearing any bit which
resides in the first 256 bytes of the memory space, where all
port registers, port DDRs, timer, timer control, and on-chip
RAM reside. An additional feature allows the software to
test and branch on the state of any bit within these 256locations. The bit set, bit clear and bit test, and branch functions
are all implemented with a single instruction. For the test and
branch instructions, the value of the bit tested is also placed
in the carry bit of the condition code register. Refer to Table

7.
CONTROL INSTRUCTIONS

These instructions are register reference instructions and
are used to control processor operation during program execution. Refer to Table 8.
ALPHABETICAL LISTING

The complete instruction set is given in alphabetical order
in Table 9.
OPCODE MAP SUMMARY

Table 10 is an opcode map for the instructions used on the
MCU.

ADDRESSING MODES
The MPU uses ten different addressing modes to provide
the programmer with an opportunity to optimize the code to
all situations. The various indexed addressing modes make it
possible to locate data tables, code conversion tables, and
scaling tables anywhere in the memory space. Short indexed
accesses are single byte instructions, while the longest instructions (three bytes) permit accessing tables throughout
memory. Short and long absolute addressing is also included. Two byte direct addressing instructions access all data
bytes in most applications. Extended addressing permits
jump instructions to reach all memory. Table 9 shows the
addressing modes for each instruction, with the effects each
instruction has on the condition code register. An opcode
map is shown in Table 10.
The term "effective address" or EA is used in describing
the various addreSSing modes, and is defined as the address
to or from which the argument for an instruction is fetched

or stored. The ten addressing modes of the processor are
described below. Parentheses are used to indicate "contents
of," an arrow indicates "is replaced by," and a colon indicates concatenation of two bytes.
INHERENT
In inherent instructions all the information necessary to execute the instruction is contained in the opcode. Operations
specifying only the index register or accumulator, and no
other arguments, are included in this mode.
IMMEDIATE
In immediate addressing, the operand is contained in the
byte immediatley following the opcode. Immediate addressing is used to access constants which do not change during
program execution (e.g., a constant used to initialize a loop
counter).

EA=PC+1; PC--PC+2
DIRECT
In the direct addreSSing mode, the effective address of the
argument is contained in a Single byte following the opcode
byte. Direct addressing allows the user to directly address
the lowest 256 bytes in memory with a single two byte instruction. This includes all on-chip RAM and I/O registers
and up to 128 bytes of off-chip ROM. Direct addressing is efficient in both memory and speed.

EA= (PC + 1); PC-PC + 2
Address Bus High-a; Address Bus Low-(PC+ 1)
EXTENDED
In the extended addressing mode, the effective address of
the argument is contained in the two bytes following the opcode. Instructions with extended addressing modes are
capable of referencing arguments anywhere in memory with
a single three byte instruction. When using the Motorola
assembler, the user need not specify whether an instruction
uses direct or extended addressing. The assembler
automatically selects the most efficient addreSSing mode.
EA= (PC+ 1):(PC+2); PC-PC+3
Address Bus High-(PC + 1); Address Bus Low-(PC + 2)
INDEXED, NO OFFSET
In the indexed, no offset addreSSing mode, the effective
address of the argument is contained in the 8-bit index
register. Thus, this addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is used to move a pointer through a table or
to address a frequently referenced RAM or I/O location.

EA= X; PC-PC+ 1
Address Bus High-a, Address Bus Low-X
INDEXED, 8-BIT OFFSET
Here the EA is obtained by adding the contents of the byte
following the opcode to that of the index register; therefore,
the operand is located anywhere within the lowest 511
memory locations. For example, this mode of addressing is
useful for selecting the m-th element in an n element table.
All instructions are two bytes. The contents of the index
register (X) is not changed. The contents of (PC + 1) is an
unsigned 8-bit integer. One byte offset indexing permits
look-up tables to be easily accessed in either RAM or ROM.

EA= X+ (PC+ 1); PC-PC+2
Address Bus High -K; Address Bus Low-X + (PC + 1)
where: K = The carry from the addition of X + (PC + 1)

3-897

I

MC146805E2

INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode the effective
address is the sum of the contents of the unsiged 8-bit index
register and the two unsigned bytes following the opcode.
This addressing mode can be used in a manner similar to indexed 8-bit offset, except that this three byte instruction
allows tables to be anywhere in memory (e.g., jump tables in
ROM). As with direct and extended, the M6805 assembler
determines the most efficient form of indexed offset - 8 or
16 bit. The content of the index register is not changed.
EA=X+[(PC+ 1):(PC+2)]; PC--PC+3
Address Bus High--(PC + 1) + K
Address Bus Low- K + (PC + 2)
where: K = The carry from the addition of X + (PC + 2)
RELATIVE

I

Relative addressing is used only in branch instructions. In
relative addressing the content of the 8-bit signed byte
following the opcode (the offset) is added to the PC if and
only if the branch condition is true. Otherwise, control proceeds to the next instruction. The span of relative addressing
is limited to the range of - 126 to + 129 bytes from the
branch instruction opcode location. The Motorola assembler
calculates the proper offset and checks to see if it is within
the span of the branch.
EA= PC+2+ (PC+ 1); PC--EA if branch is taken;
otherwise, PC--PC + 2
BIT SET/CLEAR

Direct addressing and bit addressing are combined in instructions which set and clear individual memory and I/O
bits. In the bit set and clear instructions, the byte is specified
as a direct address in the location following the opcode. The
first 256 addressable locations are thus accessed. The bit to
be modified within that byte is specified with three bits of the

opcode. The bit set and clear instructions occupy two bytes,
one for the opcode (including the bit number! and the second to address the byte which contains the bit of interest.
EA=(PC+1); PC-PC+2
Address Bus High ~O; Address Bus Low -( PC + 1)
BIT TEST AND BRANCH

Bit test and branch is a combination of direct addressing,
bit addressing, and relative addressing. The bit address and
condition (set or clear) to be tested are part of the opcode.
The address of the byte to be tested is in the single byte immediately following the opcode byte (EA 1). The Signed
relative 8-bit offset is in the third byte (EA2) and is added to
the PC if the specified bit is set or clear in the specified
memory location. This single three byte instruction allows
the program to branch based on the condition of any bit in
the first 256 locations of memory.
EA1 = (PC+ 1)
Address Bus High-O; Address Bus Low-(PC+ 1)
EA2=PC+3+(PC+2); PC-EA2 if branch taken;
otherwise, PC- PC + 3

SYSTEM CONFIGURATION
Figures 20 through 25 show in general terms how the
MC146805E2 bus structure may be utilized. Specified interface details vary with the various peripheral and memory
devices employed.
Table 11 provides a detailed description of the information
present on the bus, read/write (R/W) pin and the load instruction (LI) pin during each cycle for each instruction.
This information is useful in comparing actual with expected results during debug of both software and hardware
as the control program is executed. The information is
categorized in groups according to addressing mode and
number of cycles per instruction.

3-898

TABLE 4 -

REGISTER/MEMORY INSTRUCTIONS
Addressing Modes

Immediate
Op
Code

I

I

Mnemonic

Bytes

Cycles

Load A from Memory

LDA

A6

2

Load X from Memory

LDX

AE

2

Store A in Memory

STA

-

Function

c:u

~

Direct

Indexed
(No Offset)

Extended

Op
Code

I

I

Bytes

Cycles

2

B6

2

2

BE

2

-

-

B7

2

I

Indexed
(8-Bit Offset)

I

Op
Code

I

I

Cycles

Bytes

Cycles

3

E6

2

4

D6

3

5

en

3

EE

2

4

DE

3

5

N

1

4

E7

2

5

D7

3

6

4

F6

1

4

FE

1

5

F7

3

C6

3

3

CE

3

4

C7

3

Store X in Memory

STX

-

-

-

BF

2

4

CF

3

5

FF

1

4

EF

2

5

DF

3

6

Add Memory to A
Add Memory and
Carry to A

ADD

AS

2

2

BB

2

3

CB

3

4

FB

1

3

EB

2

4

DB

3

5

ADC

A9

2

2

B9

2

3

C9

3

4

F9

1

3

E9

2

4

D9

3

5

Subtract Memory

SUB

AO

2

2

BO

2

3

CO

3

4

FO

1

3

EO

2

4

DO

3

5
5

Subtract Memory from
A with Borrow

SBC

A2

2

2

B2

2

3

C2

3

4

F2

1

3

E2

2

4

D2

3

AND Memory to A

AND

A4

2

2

B4

2

3

C4

3

4

F4

1

3

E4

2

4

D4

3

5

OR Memory with A

ORA

AA

2

2

BA

2

3

CA

3

4

FA

1

3

EA

2

4

DA

3

5

Exclusive OR Memory
with A

EOR

A8

2

2

B8

2

3

C8

3

4

F8

1

3

E8

2

4

D8

3

5

CMP

A1

2

2

B1

2

3

C1

3

4

F1

1

3

E1

2

4

D1

3

5

CPX

A3

2

2

B3

2

3

C3

3

4

F3

1

3

E3

2

4

D3

3

5

BIT

A5

2

2

B5

2

3

C5

3

4

F5

1

3

E5

2

4

D5

3

5

Jump Unconditio"al.

JMP

BC

2

2

3

3

FC

1

2

EC

2

3

DC

3

4

JSR

-

CC

Jump to Subroutine

-

-

-

BD

2

5

CD

3

6

FD

1

5

ED_ "---2_

DD

3

7

Arithmetic Compare A
with Memory
Arithmetic Compare X
with Memory
Bit Test Memory with
A (Logical Compare)

TABLE 5 -

6
- -

- -

READ-MODIFY-WRITE INSTRUCTIONS

---

Addressing Modes
Inherent (A)

Function

Mnemonic

Op
Code

Inherent (X)

I

#

Bytes

Cycles

Indexed
(No Offset)

Direct

Op
Code

I

#

Bytes

Cycles

Op
Code

~
G)

Bytes

I
Cycles

I
Cycles

I

Op
Code

I
Bytes

I
Bytes

...A

Indexed
(16-Bit Offset)

,

Op
Code

Op
Code

3C
n

#

#

Bytes

Cycles

Indexed
(8-Bit Offset)

Op
Code

I

I

Bytes

Cycles

Op
Code

I

I

Bytes

Cycles

Increment

INC

4C

1

3

5C

1

3

3C

2

5

7C

1

5

6C

2

6

Decrement

DEC

4A

1

3

5A

1

3

3A

2

5

7A

1

5

6A

2

6

Clear

CLR

4F

1

3

5F

1

3

3F

2

5

7F

1

5

6F

2

6

Complement

COM

43

1

3

53

1

3

33

2

5

73

1

5

63

2

6

Negate
(2's Complement)

NEG

40

1

3

50

1

3

30

2

5

70

1

5

60

2

6

Rotate Left Thru Carry

ROL

49

1

3

59

1

3

39

2

5

79

1

5

69

2

6

Rotate Right Thru
Carry

ROR

46

1

3

56

1

3

36

2

5

76

1

5

66

2

6

Logical Shift Left

LSL

1

3

3

38

2

5

78

1

5

6

1

3

1

3

34

2

5

74

1

5

68
64

2

LSR

58
54

1

Logical Shift Right

48
44

2

6

Arithmetic Shift Right

ASR

47

1

3

57

1

3

37

2

5

77

1

5

67

2

6

T est for Negative
or Zero

TST

4D

1

3

5D

1

3

3D

2

4

7D

1

4

6D

2

5

III

00

o

m

MC146805E2

TABLE 6 -

BRANCH INSTRUCTIONS
Relative Addressing Mode

Function

Mnemonic

#

#

Bytes

Cycles
3

Branch Always

BRA

20

2

Branch Never

BRN

21

2

3

Branch IFF Higher

BHI

22

2

3

Branch IFF Lower or Same

BLS

23

2

3

Branch IFF Carry Clear

BCC

24

2

3

IBHS)

24

2

3

IBranch IFF Higher or Samel
Branch IFF Carry Set

BCS

25

2

3

IBLO)

25

2

3

Branch IFF Not Equal

BNE

26

2

3

Branch IFF Equal

BEQ

27

2

3

Branch IFF Half Carry Clear

BHCC

28

2

3

Branch IFF Half Carry Set

BHCS

29

2

3

BPL

2A

2

3

Branch IFF Minus

BMI

2B

2

3

Branch IFF Interrupt Mask Bit is Clear

BMC

2C

2

3

Branch IFF Interrupt Mask Bit is Set

BMS

2D

2

3

Branch IFF Interrupt Line is Low

BIL

2E

2

3

Branch IFF Interrupt Line is High

BIH

2F

2

3

Branch to Subroutine

BSR

AD

2

6

IBranch IFF Lower)

I

Op
Code

Branch IFF Plus

TABLE 7 -

I'

BIT MANIPULATION INSTRUCTIONS
Addressing Modes
Bit Setl Clear

Function

Mnemonic

Op
Code

Branch IFF Bit n is Set

BRSET n In=O

7)

Branch IFF Bit n is Clear

BRCLRnln=O

7)

Bit Test and "Branch

#

#

Bytes

Cycles

Op
Code

#

#

Bytes

Cycles

-

-

-

2-n

3

5

-

-

-

01 + 2-n

3

5

Set Bit n

BSET n In=O. 7)

10+ 2-n

2

5

-

-

-

Clear Bit n

BCLR n In=O .. 7)

11 + 2-n

2

5

-

-

-

TABLE 8 -

CONTROL INSTRUCTIONS
Inherent

Function

Mnemonic

Op
Code

#

#

Bytes

Cycles

Transfer A to X

TAX

97

1

2

Transfer X to A

TXA

9F

1

2

Set Carry Bit

SEC

99

1

2

Clear Carry Bit

CLC

98

1

2

Set Interrupt Mask Bit

SEI

9B

1

2

Clear Interrupt Mask Bit

CLI

9A

1

2

Software Interrupt

SWI

83

1

10

Return from Subroutine

RTS

81

1

6

Return from Interrupt

RTI

80

1

9

Reset Stack Pointer

RSP

9C

1

2

No-Operation

NOP

9D

1

2

Stop

STOP

8E

1

2

Wait

WAIT

8F

1

2

3-900

MC146805E2

TABLE 9 -

INSTRUCTION SET

Addressing Modes
Mnemonic

Inherent

ADC
ADD
AND
ASL
ASA
BCC
BCLA
BCS
BEG
BHCC
BHCS
BHI
BHS
BIH
BIL
BIT
BLO
BLS
BMC
BMI
BMS
BNE
BPL
BAA
BAN
BACLA
BASET
BSET
BSA
CLC
CLI
CLA
CMP
COM
CPX
DEC
EOA
INC
JMP
JSA
LDA
LDX
LSL
LSA
NEG
NOP
OAA
AOL
AOA
ASP
ATI
ATS
SBC
SEC
SEI
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT

Immediate
X
X
X

X
X

Direct
X
X
X
X
X

Extended

Relative

Condition Codes

Indexed
(No Offset)

Indexed
(8 Bits)

Indexed
(16 Bits)

X
X
X
X
X

X
X
X
X
X

X
X
X

X
X
X

Bit

Setl
Clear

Bit
Test &
Branch

H I N Z C
A
1\

X
X
X
X
X
X
X
X
X
X
X

X

X

X

X

••
••
•••
••
•
••

X

X
X

X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X

X

X

X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X

X
X
X

X
X

X
X
X
X

X

H
I
N
Z
C

Half Carry (From Bit 31
Interrupt Mask
Negative (Sign Bitl
Zero
Carry / Borrow

X

X

X

X

X

X
X

X
X

X
X

X
X

X
X

X

X

A
•

1

Test and Set if True. Cleared Otherwise
Not Affected
Load CC Aegister From Stack
Cleared
Set

3-901

A

I

0

1

A
A
A
A
A
A

A
A
A
A
A
A

•
•0
•

•
A

1
A

A
A
A
0 A
A _A

A
A
A

•A •A •
•
A A
1\

X

Condition Code Symbols

A
1\

•A

A
A

A

X

X

•
•• •••
•• ••
••• •••
••
•A •A

A
A
A

X

X
X

A
A
A

••
•
• ••
• ••
•
•

X

X
X

X
X
X
X
X

A
1\

A
A
A

•0

i
X

A
1\

•
•
•
•
•

X
X

X

•

•
•
•

X
X
X
X
X
X
X
X
X

X
X
X

•
••
•
••
••

?

•••
1

•
•
••
•
••
?

A

•0
••
1
••
••
0 •
A
A
A

A

A

A

?

?

••
•A •A
• 1
•A ••
•A •
A

••
••
A

•
••
•
••
A

..
3:

n
...a

TABLE 10 - MC146806 CMOS INSTRUCTION SET OPCODE MAP

~

BitMa~lation

~
o
0000

1

0001

2
0010

3

REI

DIR

0001

2
0010

3
0011

o

,

5[

5[

3[

BRSETO
BSETO
BRA
BTB 2
BSC 2
AEL
5
BRCLR0 [ BCLRO 5[
BRN
3
BTB 2
BSC 2
AEL
5
BRSET,"T BSET1 [
BHI
3
BTB 2
BSC 2
AEL

I3

2

IX
7

INH
INH
IXI
456

0100

0101

0111

0110

NEG
NEG
NEG
INH I 1
INH
DIA I 1

NEG

IXI I 1

NEG

I

'1

7
0111

8

1000

9
1001
A
1010

B
1011

C

1100

o

1101

E

lIla

F
1111

INH

IMM

8
1000

9
1001

It,O .

RTI

LL

INH

2

COM
SWI
BCLRl 5[
BLS 31
COM 51 COMA 31 COMX 31
COM 6
IX I 1
INH
BSC 2
AEL 2
DIA I
INH 1
INH 2
IX 1 I 1

ROR
BSET3 51
BNE 31
ROR 51 RORA 31
RORX 31
ROR
2
BSC 2
AEL 2
DIA I
INH 1
INH 2
IX I I I

2

BCLR4
BSC

.

2

3[

BHCS
AEL

3]

31 --

3

BTB

2

I
5[
BCLR6
BSC

3[

BMS
2
AEL

2

.. --~TST A 3

TST

CLI

DIA

I

INH

SEI

~

INH

IMM
DIR
EXT
REL

BSC
BTB
IX
IX1
IX2

Inherent
Accumulator
Index Register
Immediate
Direct
Extended
Relative
Bit Setl Clear
Bit Test and Branch
Indexed (No Offset)
Indexed. 1 Byte (S-Bit) Offset
Indexed. 2 Byte (16-Bit) Offset

I

3

0
0000

I
0001

2
0010

CPX 31
CPX 41
CPX 51
CPX
CPX
CPX
IX
DIA 3
EXT 3
IX2 2
IXI I 1
IMM 12

0011

AND 31
AND 41
AND 51
AND
AND
AND
DIR 3
EXT 3
IX2 2
IXI I 1
IX
IMM 12

0100

d
~

I

STA

STA

3

4

5

.JllllL

6

0110

7

2
IXI I I
IX
I
1 2 EOR
I I EOR
IX1
IX
I
AOC
AOC
I 2
IXl I 1
IX

0111

ORA
ORA
ORA
ORA
ORA
ORA
IMM 12
DIA I 3
EXT I 3
IX2 I 2
IXl I 1
IX

A
1010

ADD
ADD
ADD
ADD
ADD
ADD
INH 12
IMM 12
DIA I 3
EXT I 3
IX21 2
IXl I 1
IX

1011

INH 12

I

JMP
JMP
JMP
JMP
JMP
DIA I 3
EXT I 3
IX2 I 2
IXI I I
IX

JSR
NOP
BSR
JSR
JSR
JSR
JSR
INH 12
AEL I 2
DIA I 3
EXT I 3
IX2 I 2
IXI I 1
IX

L
STOP
INH
CLR 51
WAIT 2
TXA
IX
1
INH 11
INH

T

LOX
LOX
LOX
LOX
LOX
IMM 12
DIA I 3
EXT I 3
IX2 I 2
IXI I I

LOX

8

1000

9

1001

B

C

1100

o

1101

E

IX

1110

STX
STX
STX
STX
DIA I 3
EXT I 3
IX2 I 2
IXI I 1
IX

F
1111

STX

Abbreviation. for Addr... Modes

A
X

~

I

SBC
SBC 31
SBC 41
SBC 51
SBC
SBC
IX
DIA 3
EXT 3
IX2 2
IXI I 1
IMM 12

RSP
INH

TST
TSTX
TST
INH I 2
IXI I I

BRSET751 BSET7 51
BIL
3
BTB 2
BSC 2
AE
5
BRCLR7 [ BCLR751 - BIH
CLR
CLRA 31
CLRX 3
CLR
3
BTB 2
BSC 2
AEL I 2
DIA 1,
INH 1
INH I 2
IXI I I

IX
1[,1

SUB
SUB 4[
SUB 5[
SUB 41
SUB 3
IMM 2
DIA 3
EXT 3
IX2 2
IXl 1
IX
21
31
41
~-n
CMP
CMP
IX
IMM 12 CMPDIA 13 CM~XT 3 CMP,X2 2 CMP,X1 I I

I

3

ROL 51 ROLA
ROLX
ROL
DIA I
INH I
INH I 2
51
3[
3
DEC
DEC
DEC
DECA
OECX
IXI I 1
IX
2
DIA I
INH 1
INH I 2
2

IXI

11~0

19l

TAX
INH

BRSET5
BSET5
. BPL.
13
BTB 2
'2
AEI.
5
5
BRCLR5 [· BCLR5 [
BMI
3
BTB 2
BSC 2
AEL
5
5
INC
INC
BRSET6
BSET6
BMC 3[
INC 51
INCA 31
INCX
IXI I 1
3
BTB 2
BSC 2
AEL 2
DIA 1
INH I 1
INH I 2

I
5[
BRCLR6

lfoo

STA 41
STA 51
STA
DIA 3
EXT 3
IX2
3T
4I
5
CLC
12 EO~MM 2 EORDIA 3 EOREXT I 3 EOR lx2
'NH
2 I
21
3T
4
5
SEC
AOC
AOC
ADC
AOC
IX2
INH 12
IMM 12
DIA I 3
EXT I 3

BRCLR35[ BCLR3 51
BEG 31
ASR 51 ASRA 31
ASRX 31
ASR
ASR
3
BTB 2
. BSC 2
REL 2
DIA I
INH I
INH 2
IX 1 I 1
5
BSET4 51--BHCC 3f
L~~5[ L~~~3f LSLX 3 I, LSL
BRSET4
LSL
IXI I 1
BTB 2
BSC 2
REL 2
DIA I
INH I
INH 2
I3
BRCLR4
3
BTB

EXT . _~

I

"IT:

I
'1- -sf·
IT; ~.

1~1
-:1
SUB

BIT
BIT 31
BIT 41
BIT
BIT 4
BIT
12
IMM 2
DIA 3
EXT 3
I
2
IXI I 1
.Jll
21
31
41
···51
LOA
LOA
LOA
LOA
LOA
LOA
2
IMM 2
DIA 3
EXT 3
IX22
IXI I I
IX

BRCLR2'[ BCLR251
BCS
3
BTB 2
BSC 2
AEL
BRSET3
13
BTB

'DIR

-r

I

10

LSR
BRSET25[ BSET2 51
BCC 31
LSR 51
LSRA 31
LSRX 31
LSR
3
BTB 2
BSC 2
AEL 2
DTR 1
INH 1
INH 2
IXI I 1

6

IX I 1

INH

RTS
INH

BRCLRl
3
BTB

0110

~

Bse

0000

4
0100
0101

I\)

BTB

CO

~ister/Mamory

Control

0011

5

~

Read-MOdify-Write

Branch

LEGEND
~.r-~I--------------~

Mnemonic
Bytes

~.
1

# of Cycles _ _ _ _ _ _--J

~

l

~

}~X

Opcode in Hexadecimal

Opcode in Binary

(XXX) ~

"

Address Mode

o
en

m
N

MC146805E2

FIGURE 20 -

CONNECTION TO CMOS PERIPHERALS

Chip
Enable

A8A12
MC146805E2
CMOS
Microprocessor

......- - _....

TYPical CMOS
Peripheral
(MC146818 etc.1
ADO-AD7

J-_---..:.A..:.:d:.::d::.:re::::s:.::.s--=S:..:.t:..::ro~b.:::.e_~~ AS
J-_ _--'D::,:a:!.:;t:o!.a-=S~tr-=o~b::::..e_ _~ DS
R IW J-_ _ _R!..!:e~a!-"d:.c./~W:..:.r~ite"--_~~ R/W
~____~ln~te~r_ru~p~t_ _ _~nR5

CKOUT (MC1468181
RESET·~------~--------~RESET

FIGURE 21 -

CONNECTION TO CMOS MULTIPLEXED MEMORIES

CMOS
Multiplexed
Memory
(MCM655161

MC146805E2
A8-A12

~-------BO-B7
Address Strobe

AS~------------~-----M

DS

Data Strobe

G

R/W

Read/Write

W

3-903

I

MC146805E2

FIGURE 22 -

CONNECTION TO M6800 PERIPHERALS

M6800
Peripherals

MC146805E2

I

DS~____~D~a~ta~S~tr~o~be~__~

RlIN ~____~R-,-,e::::ac:::d,-IW=..;ri-"'te'---__..-.t R(W
IRO

Interrupt

RESET

IRO
RESET

NOTE· In some cases, pullup resistors or other level
shifting techniques may be required on signals
going from NMOS to CMOS parts.

FIGURE 23 -

CONNECTION TO LATCHED NON-MULTIPLEXED CMOS ROM AND EPROM

BO-B7

Address/Data Bus

Data

00-07
CMOS
Non-Muxed
AO-A7 Memory

MC146805E2

A8-A12

A8

.......- - - - - - ,

R/Wt-------.....

Output
Enable

S

Chip
Enable

E

J

DSr---------~______

AS

3-904

MC146805E2

FIGURE 24 -

CONNECTION TO STATIC CMOS RAMS

CMOS
Static
RAMs

MC146805E2
CMOS
Microprocessor
DO-D7

AS~--"'-'

AS

AS-A12

A9

I
DS~------------~

R/W

FIGURE 25 - CONNECTION TO LATCHED NON-MULTIPLEXED CMOS RAM

Addressl Data Bus

Data

00-07

AO-A7

MC146805E2

CMOS
Non-Muxed
RAM

AS-A12

AS

S

DS

R/W

Chip
Enable

AS

3·905

E

MC146805E2

TABLE 11 Address Mode
Instructions

SUMMARY OF CYCLE-BY-CYCLE OPERATION
R/W
Pin

LI
Pin

Data Bus

Op Code Address
Op Code Address + 1
Op Code Address + 1

1
1
1

1
0
0

Op Code
Op Code Next Instruction
Op Code Next Instruction

1
2

Op Code Address
Op Code Address + 1

1
1

1
0

Op Code
Op Code Next Instruction

1
2
3
4
5

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
I Stack Pointer + 2
New Op Code Address

1
1
1
1
1
1

1
0
0
0
0
0

Op Code
Op Code Next Instruction
Irrelevant Data
Irrelevant Data
Irrelevant Data
New Op Code

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Vector Address 1FFC (Hex)
Vector Address 1FFD (Hex)
Interrupt Routine Starting Address

1
1
0
0
0
0
0
1
1
1

1
0
0
0
0
0
0
0
0
0

Op Code
Op Code Next Instruction
Return Address (LO Byte)
Return Address (HI Byte)
Contents of Index Register
Contents of Accumulator
Contents of CC Register
Address of Int. Routine (HI Byte)
Address of Int. Routine (LO Byte)
Interrupt Routine First Opcode

8
9

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer + 4
Stack Pointer + 5
New Op Code Address

1
1
1
1
1
1
1
1
1

1
0
0
0
0
0
0
0
0

Op Code
Op Code Next Instruction
Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data
New Op Code

2

1
2

Op Code Address
Op Code Address + 1

1
1

1
0

Op Code
Operand Data

5

1
2
3
4
5

Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand
Address of Operand

1
1
1
1
0

1
0
0
0
0

Op Code
Address of Operand
Operand Data
Operand Data
Manipulated Data

5

1
2
3
4
5

Op Code Address
Op Code Address + 1
Address of Operand
Op Code Address + 2
Op Code Address + 2

1
1
1
1
1

1
0
0
0
0

Op Code
Address of Operand
Operand Data
Branch Offset
Branch Offset

3

1
2
3

Op Code Address
Op Code Address + 1
Op Code Address + 1

1
1
1

1
0
0

Op Code
Branch Offset
Branch Offset

1
2
3
4
5

Op Code Address
Op Code Address + 1
Op Code Address + 1
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1

1
1
1
1
0
0

1
0
0
0
0
0

Op Code
Branch Offset
Branch Offset
First Subroutine Op Code
Return Address (LO Byte)
Return Address (HI Byte)

Cycles

Cycle #

LSR LSL
ASR NEG
CLR ROL
COM ROR
DEC INC TST

3

1
2
3

TAX CLC SEC
STOP CLI SEI
RSP WAIT NOP TXA

2

Address Bus

Inherent

RTS

6

6

I

1

SWI

10

2
3
4
5

6
7

8
9

10

RTI

9

1
2
3
4
5

6
7

Immediate
ADC EOR CPX
ADD LOA LOX
AND ORA BIT
SBC CMP SUB
Bit Set/Clear

. BSET n
BCLR n
Bit Test and Branch
BRSET n
BRCLR n
Relative
BCC BHI BNE BEQ
BCS BPL BHCC BLS
BIL BMC BRN BHCS
BIH BMI BMS BRA

BSR

6

6

3-906

MC146805E2

TABLE 11 Address Mode
Instructions

J

Cycles

SUMMARY OF CYCLE-BY-CYCLE OPERATION (CONTINUED)

Cycle #

Address Bus

LI

R/W
Pin

Pin

Data Bus

Direct

2

JMP
ADC
ADD
AND
SBC

EOR CPX
LDA LDX
ORA BIT
CMP SUB

3

Op Code Address
Op Code Address + 1

1
1

0

1
2

Op Code Address
Op Code Address + 1
Address of Operand

1
1
1

0
0

Op Code Address
Op Code Address + 1
Address of Operand
Op Code Address + 2

1
1
1
1

0
0
0

Op Code Address
Op Code Adrress + 1
Op Code Address + 1
Address of Operand

1
1
1

3

4

TST

1
2

3
4

STA
STX

4

1
2

3
4

LSL LSR DEC
ASR NEG INC
CLR ROL
COM ROR

·1
2

5

3
4
5
1
2

5

JSR

1

1
2

3
4
5

Op Code Address
Op Code Address + 1
Operand Address
Operand Address
Operand Address

0
1
1
1
1

0
1
1
1

1

1

1

0
0
0
1

0
0
0
0
1

Op Code Address
Op Code Address + 1
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1

0
0

0
0
0
0

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

0
0

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand

1
1
1
1

0
0
0

Op Code Address
Op Code Address + 1
Op Code Address + 2
Op Code Address + 2
Address of Operand

1
1
1
1

Op Code
Jump Address
Op Code
Address of Operand
Operand Data
Op Code
Address of Operand
Operand Data
Op Code Next Instruction
Op Code
Address of Operand
Address of Operand
Operand Data
Op Code
Address of Operand
Current Operand Data
Current Operand Data
New Operand Data
Op Code
Subroutine Address (LO Byte)
1st Subroutine Op Code
Return Address (LO Byte)
Return Address (HI Byte)

Extended

3

JMP

1
2

3
ADC BIT ORA
ADD CMP LDX
AND EOR SBC
CPX LDA SUB

4

1
2

3
4
1
2

STA
STX

5

3
4

5
1
2

6

JSR

0
1
1
1
1

1

1

1

0
0
0
0
1

Op Code
Jump Address (HI Byte)
Jump Address (LO Byte)
Op Code
Address Operand (HI Byte)
Address Operand (LO Byte)
Operand Data
Op Code
Address of Operand (HI Byte)
Address of Operand (LO Byte)
Address of Operand (LO Byte)
Operand Data
Op Code
Address of Subroutine (HI Byte)
Address of Subroutine (LO Byte)
1st Subroutine Op Code
Return Address (LO Byte)
Return Address (HI Byte)

3
4
5
6

Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack POinter
Stack Pointer - 1

0
0

0
0
0
0
0

1
2

Op Code Address
Op Code Address + 1

1
1

0

1
2

Op Code Address
Op Code Address + 1
Index Register

1
1
1

0
0

Op Code Address
Op Code Address + 1
Index Register
Op Code Address + 1

1
1
1
1

0
0
0

Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register

1
1
1
0

0
0
0

Op Code
Op Code Next Instruction
Op Code Next Instruction
Operand Data

Op Code Address
Op Code Address + 1
Index Register
Index Register
I ndex Register

1
1
1
1
0

1
0
0
0
0

Op Code
Op Code Next Instruction
Current Operand Data
Current Operand Data
New Operand Data

Op Code Address
Op Code Address + 1
I ndex Register
Stack POinter
Stack POinter - 1

1
1
1
0
0

1
0
0

Op Code
Op Code Next Instruction
1st Subroutine Op Code
Return Address (La Byte)
Return Address (HI Byte)

Indexed, No-Offset

JMP
ADC
ADD
AND
SBC

2
EOR CPX
LDA LOX
ORA BIT
CMP SUB

3

3

TST

4

STA
STX

4

1
2

3
4
1
2

3
4
1

LSL LSR DEC
ASR NEG INC
CLR ROL
COM ROR

5

JSR

5

2
3
4

5
1

2
3
4

5

3-907

1

1

1

1

0
0

Op Code
Op Code Next Instruction
Op Code
Op Code Next Instruction
Operand Data
Op Code
Op Code Next Instruction
Operand Data
Op Code Next Instruction

I

MC146805E2

TABLE 11 - SUMMARY OF CYCLE-BY-CYCLEOPERATION (CONTINUED)

Address Mode
Instructions
Indexed a-Bit Offset
JMP

I Cycles

3

Cycle #

1
2

3
ADC EOR CPX
ADD LOA LOX
AND ORA CMP
SUB BIT SBC

STA
STX

I

4

1
2

3
4
1
2

5

3
4

5
1
2
TST

5

3
4

5
LSL LSR
ASR NEG
CLR ROL
COM ROR
DEC INC

1
2

6

3
4

5
6
1
2

JSR

6

3
4

5
6

Address Bus

Op Code Address
Op Code Address
Op Code Address

R/W
Pin

LI

1
1
1

0
0

Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register + Offset

1
1
1
1

0
0
0

Op Code Address
Op Code Address + 1
Op Code Address + 1
Op Code Address + 1
Index Register + Offset

1
1
1
1

0

0
0
0
0

Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register + Offset
Op Code Address + 2

1
1
1
1
1

0
0
0
0

Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register + Offset
Index Register + Offset
Index Register + Offset

1
1
1
1
1

+1
+1

0
1
1
1
1

Data Bus

Pin
1

1

1

1

1

0
0
0
0
0
1

Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register + Offset
Stack Pointer
Stack Pointer - 1

0
0

0
0
0
0
0

Op
Op
Op
Op

1
1
1
1

0
0
0

Op Code Address
Op Code Address + 1
Op Code Address + 2
Op Code Address + 2
Index Register + Offset

1
1
1
1
1

0
0
0
0

Op Code Address
Op Code Address + 1
Op Code Address + 2
Op Code Address + 2
Op Code Address + 2
Index Register + Offset

1
1
1
1
1

Op Code
Offset
Offset
Op Code
Offset
Offset
Operand Data
Op Code
Offset
Offset
Offset
Operand Data
Op Code
Offset
Offset
Operand Data
Op Code Next Instruction
Op Code
Offset
Offset
Current Operand Data
Current Operand Data
New Operand Data
Op Code
Offset
Offset
1st Subroutine Op Code
Return Address LO Byte
Return Address HI Byte

Indexed, l6-Bit Offset
JMP

4

1
2

3
4

ADC CMP SUB
ADD EOR SBC
AND ORA
CPX LOA
BIT LOX

1
2

5

3
4

5
1
2

STA
STX

6

3
4

5
6
1
2

3
JSR

7

4

5
6
7

Code
Code
Code
Code

Address
Address
Address
Address

+1
+2
+2

Op Code Address
Op Code Address + 1
Op Code Address + 2
Op Code Address + 2
Index Register + Offset
Stack Pointer
Stack Pointer - 1

3-908

0
1
1
1
1
1

0
0

1

1

1

0
0
0
0
0
1

0
0
0
0
0
0

Op Code
Offset (HI Byte)
Offset (LO Byte)
Offset (LO Byte)
Op Code
Offset (H I Byte)
Offset (LO Byte)
Offset (La Byte)
Operand Data
Op Code
Offset (HI Byte)
Offset (LO Byte)
Offset (La Byte)
Offset (LO Byte)
Operand Data
Op Code
Offset (HI Byte)
Offset (LO Byte)
Offset (LO Byte)
1st Subroutine Op Code
Return Address (LO Byte)
Return Address (HO Byte)

MC146805E2

TABLE 11 -

Instructions

Cycles

SUMMARY OF CYCLE-BY-CYCLE OPERATION (CONTINUED)
RESET
Pin

R/W
Pin

LI
Pin

$lFFE

0

1

0

$lFFE

0

1

0

Irrelevant Data

1

$1 FFE

1

1

0

Irrelevant Data

2

$1 FFE

1

1

0

Irrelevant Data

3

$1 FFE

1

1

0

Vector High
Vector Low

Cycle #

Address Bus

Data Bus

Other Functions

Hardware RESET

Power on Reset

Instruction

IRO Interrupt
(Timer Vector $lFF8, $lFF9)

5

1922

Cycles

10

Irrelevant Data

4

$1 FFF

1

1

0

5

Reset Vector

1

1

0

Op Code

1

$1 FFE

1

1

0

Irrelevant Data

1919

$1 FFE

·• ··• ··• ••
·
·
1

1

0

Irrelevant Data

1920

$1 FFE

1

1

0

Vector High

1921

$1 FFF

1

1

0

Vector Low

1922

Reset Vector

1

1

0

Op Code

IRQ
Pin

R/W
Pin

LI
Pin

Lase Cycle of Previous
Instruction

0

X

0

X

1

Next Op Code Address

0

1

0

Irrelevant Data

2

Next Op Code Address

X

1

0

Irrelevant Data

3

SP

X

0

0

Return Address (LO Byte)

4

SP-1

0

0

Return Address (HI Byte)

5
6
7

SP-2

X
X

0

0

Contents Index Reg

X
X

0

0

Contents Accumulator

SP-4

0

0

Contents CC Register

8

$lFFA

X

1

0

Vector High

9

$1 FFB

X

1

0

Vector Low

10

IRO Vector

X

1

0

Int Routine First

·• ···
·

Cycles #

Address Bus

SP-3

Data Bus

APPENDIX
MC146805E2 INTERRUPT CLARIFICATION
Under certain circumstances, the MC146805E2 (BP4XXXX
and AW9XXXX) 8-bit Microprocessor Unit TAO interrupt
does not conform to the operation described in this
Advanced Information Sheet.

these require no action and the third has a recommended solution.
a. Those not using the WAIT mode neqd not take any
action.

1. The level sensitive IRQ mode, which is by far the most
frequently used, is FULLY OPERATIONAL: thus, most
MC146805E2 applications are unaffected. However,
the edge-triggered TRO interrupt mode MIGHT NOT BE
SERVICED under certain programming circumstances;
therefore, it is recommended that the edge-triggered
mode not be used.
2. An interrupt-vector address CAN BE improperly
generated in some circumstances. There is a possibility
that when an external interrupt (iRQ) and timer interrupt occur during the WAIT mode (following wait
instruction), address locations $1 FF2 and $1 FF3 are
selected instead of vector locations $1 FF6 and $1 FF7.
There are three specific examples listed below; two of

b. If the WAIT mode is used without external interrupt
(iRO pin held high), no precautions are required.
c. When IRQ can be active (low) during the WAIT
mode, the vector in locations $1 FF6 and $1 FF7 (the
WAIT mode timer interrupt vector) should be
duplicated in $1 FF2 and $1 FF3. In this way the circumstances that caused selection of the second
vector do not disturb normal program execution.
On future MC146805E2 parts, no special actions will be
necessary. If you have questions, contact your Motorola
distributor or Motorola sales office, or contact Motorola
Microprocessor Applications Engineering in Austin, Texas.

3-909

I

®

MOTOROLA

Advance Information

MC14680SF2
CMOS
(HIGH-PERFORMANCE SILICON-GATE)

a-BIT MICROCOMPUTER UNIT

I

The MC146805F2 Microcomputer Unit (MCU) belongs to the
M146805 Family of Microcomputers. This 8-bit MCU contains on-chip
oscillator, CPU, RAM, ROM, I/O, and TIMER. The fully static design
allows operation at frequencies down to dc, further reducing its already
low-power consumption. It is a low-power processor designed for lowend to mid-range applications in the consumer, automotive, industrial,
and communications markets where very low-power consumption constitutes an important factor.

HARDWARE FEATURES
• Typical Full Speed Operating Power of 10 mW at 5 V
• Typical WAIT Mode Power of 3 mW
• Typical STOP Mode Power of 25 ,."W
• 8-Bit Architecture
• Fully Static Operation
• Single 3- to 6-Volt Supply
• 1089 Bytes of On-Chip User ROM
• 64 Bytes of On-Chip RAM
• Memory Mapped I/O
• 16 Bidirectional I/O Lines
• 4 Input-Only Lines
• Internal 8-Bit Timer with Software Programmable 7-Bit Prescaler
• External Timer Input
• External and Timer Interrupts
• Self-Check Mode
• Master Reset and Power-On Reset
• On-Chip Oscillator
• 1 ,."s Cycle Time
• 28-Pin Dual-In-Line Package
• Chip Carrier Also Available
SOFTWARE FEATURES
• Similar to the MC6800
• Efficient Use of Program Space
• Versatile Interrupt Handling
• True Bit Manipulation
• Ten Addressing Modes with Indexed Addressing for Tables
• Efficient Instruction Set
• Memory Mapped I/O
• User Callable Self-Check Routines
• Two Power Saving Standby Modes
USER SELECTABLE OPTIONS
• Crystal or Low-Cost Resistor Oscillator Option
• Oscillator Internally Divided by 2 or 4
• Interrupts Edge Sensitive Only or Level and Edge Sensitive

8-BIT
MICROCOMPUTER

P SUFFIX
PLASTIC PACKAGE
CASE 710

L SUFFIX
CERAMIC PACKAGE
CASE 719

S SUFFIX
CERDIP PACKAGE
CASE 733

Z SUFFIX
CHIP CARRIER
CASE 761

PIN ASSIGNMENT
VDD
TIMER

PCO
PCl
PC2
PC3
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
Chip carrier pin assignments are shown on the next
page.

ThiS document contains Information on a new product Specifications and information herein
are subject to change without notice

MC146805F2

PIN ASSIGNMENT (CONTINUED)

*
u
z

:;;:
U
(J)
:::l
z
0

I~ I~

a:
0
0

>

:!ii
i=

0

U

0..

*
u
U
0..
Z

NC*

PC2

OSC2

PC3

PAO

PBO

PA1

PB1

PA2

PB2

PA3

PB3

NC*

NC*

PA4

NC*

NC*

NC*

NC*

NC*

*

LD

U

z ;;t=

co

r---

« «
0..
0..

(J)
(J)

>

r---

ro

0..

co
ro

0..

LD

'

cO
....L
~

2*

Internal
Address

Bus*

Internal
Data

Bus*

\

,

~tRL~

*

-/'

Internal timing signal not available externally.

o
en

."

Timer)
( Pin 27

FIGURE 5 -

RESET

CD

MC146805F2

FIGURE 6 -

OSC2** --------__~

STOP RECOVERY

~

~ ZIIIIIIIZZZ

IRQ
or
RESET

Kw-----_

tlLCH - - - - - - -......
I.If----1920t CyC

~

;ZZZ

-----3.~1

~~.-----------------------------------------------~~-------

I

* Internal timing Signals not available externally
**Represents the Internal gating of the OSC1 input pin

FUNCTIONAL PIN DESCRIPTION
VDD and VSS
Power is supplied to the MCU using these two pins. VDD
is power and VSS is ground.

OSC1,OSC2
The MCl46805F2 can be configured to accept either a
crystal input or an RC network. Additionally, the internal
clocks can be derived from either a divide-by-two or divideby-four of the external frequency (fosc). Both of these options are photomask selectable.

IRQ (MASKABLE INTERRUPT REQUEST)

TAO is photomask option selectable with the choice of interrupt sensitivity being both level and negative edge or
negative edge only. The MCU completes the current instruction before it responds to the request. If TROis low and the
interrupt mask bit (I bit) in the condition code register is
clear, the MCU begins an interrupt sequence at the end of
the current instruction.
If the photomask option is selected to include level sensitivity, then the IRQ input requires an external resistor to
VDD for "wire-OR" operation. See the Interrupt section for
more detail.
RESET

The RESET input is not required for start-up but can be
used to reset the MCU's internal state and provide an orderly software start-up procedure. Refer to the Resets section
for a detailed description.
TIMER
The TIMER input may be used as an external clock for the
on-chip timer. Refer to the Timer section for a detailed
description.

RC - If the RC oscillator option is selected, then a resistor
is connected to the oscillator pins as shown in Figure 7(b).
The relationship between Rand fosc is shown in Figure 8.
CRYSTAL - The circuit shown in Figure 7(a) is recommended when using a crystal. The internal oscillator is
designed to interface with an AT-cut parallel resonant quartz
crystal resonator in the frequency range specified for fosc in
the electical characteristics table. Using an external CMOS
oscillator is suggested when crystals outside the specified
ranges are to be used. The crystal and components should
be mounted as close as possible to the input pins to minimize
output distortion and start-up stabilization time. Crystal frequency limits are also affected by VDD. Refer to Table 1,
Control Timing Characteristics, for limits.
EXTERNAL CLOCK - An external clock should be applied to the OSCl input with the OSC2 input not connected,
as shown in Figure 7(e). An external clock should be used
with the crystal oscillator mask option only. toxOV or tlLCH
do not apply when using an external clock input.

NUM (NON-USER MODE)

PAO-PA7

This pin is intended for use in self-check only. User applications should leave this pin connected to ground through
a 10 kilohm resistor.

These eight 110 lines comprise Port A. The state of any pin
is software programmable. Refer to the Input/Output Programming section for a detailed description.

3.. 915

MC146805F2

FIGURE 7 -

OSCILLATOR CONNECTIONS

Crystal Parameters

Oscillator Waveform

1 MHz

4 MHz

Units

400

75

{}

Co

5

7

pF

C1

0.008

0.012

I'F

COSC1

15-40

15-30

pF

COSC2
Rp

15-30

1525

pF

10

10

M{}

30 k

40 k

RSMAX

Q

I

-

la) Crystal Oscillator Connections and Equivalent Crystal Circuit

MC146805F2
OSC1
4

OSC2
Rp

---~ID"""I
COSC1

Ib)

"J"

___

COSC2

RC Oscillator Connection

Ic) External Clock Source Connections

Unconnected

External Clock

3-916

4

MC146805F2

FIGURE 8 -

FREQUENCY vs RESISTANCE FOR

PBO-PB7
These eight lines comprise Port B. The state of any pin is
software programmable. Refer to the Input/Output Programming section for a detailed description.

RC OSCILLATOR OPTION ONLY

PCO-PC3

These four lines comprise Port C, a fixed input port. When
Port C is read, the four most-significant bits on the data bus
are "1s" . There is no data direction register associated with
Port C.

TBD

INPUT/OUTPUT PROGRAMMING

Any Port A or B pin may be software programmed as an
input or output by the state of the corresponding bit in the
port data direction register (DDRl. A pin is configured as an
output if its corresponding DDR bit is set to a logic "1". A
pin is configured as an input if its corresponding DDR bit is
cleared to a logic "0". At reset, all DDRs are cleared, which
configures all port pins as inputs. A port pin configured as an
output will output the data in the corresponding bit of its
port data latch. Refer to Figure 9 and Table 2.

R (kOl

FIGURE9 - TYPICAL PORT 1/0 CIRCUITRY
(a)

Interal
MC146805F2
Connections

(b)

4

6

Typical Port
Data Direction
Register

2

0

Typical Port
Register

Pin

P-7

P-5

P-6

TABLE 2 -

P-4

P-3

P-l

P-2

P-O

1/0 PIN FUNCTIONS

1/0 Pin Function

R/W
0
0

DDR
0
1

Data is written into the output data latch and output to the I/O pin

1

0

The state of the I/O pin

1

1

The I/O pin is in an output mode. The output data latch

The I/O pin is in input mode. Data is written into the output data latch
IS

read.

3-917

IS

read

I

MC146805F2

The RAM test must be called with the stack pointer at $7F
and the accumulator zeroed. When run, the test checks
every RAM cell except for $7F and $7E which are assumed to
contain the return address.
A and X are modified. All RAM locations except the top 2
are modified. (Enter at location $78B.)

SELF-CHECK
The MCl46805F2 self-check is performed using the circuit
in Figure 10. Self-check is initiated by tying NUM and TIMER
pins to a logic" 1" then executing a reset. After reset, the
following five tests are executed automatically:
1/0 - Functionally Exercise Ports A, B, C
RAM - Walking Bit Test
ROM - Exclusive OR with ODD "ls" Parity Result
Timer - Functionally Exercise Timer
Interrupts - Functionally Exercise External and Timer Interrupts
Self-check results are shown in Table 3. The following
subroutines are available to user programs and do not require any external hardware.

I

TABLE 3 -

ROM CHECKSUM SUBROUTINE

Returns with Z bit cleared if any error was found; otherwise Z = 1, X = 0 on return, and A is zero if the test passed.
RAM locations $40-$43 are overwritten. (Enter at location
$7A4.)

TIMER TEST SUBROUTINE

Return with Z bit cleared if any error was found; otherwise
Z= 1.
This routine runs a simple test on the timer. In order to
work correctly as a user subroutine, the internal clock must
be the clocking source and interrupts must be disabled.
Also, on exit, the clock will be running and the interrupt
mask will not be set, so the caller must protect himself from
interrupts if necessary.
A and X register contents are lost; this routine counts how
many times the clock counts in 128 cycles. The number of
counts should be a power of two since the prescaler is a
power of two. If not, the timer probably is not counting correctly. The routine also detects if the timer is running at all.
(Enter at location $7BE.)

SELF-CHECK RESULTS

PB3

PB2

PBl

PBO

1

0

1

1

Bad Timer

Remarks

1

1

0

0

Bad RAM

1

1

0

1

Bad ROM

1

1

1

0

Bad Interrupt or Request Flag

All Cycling

Good Part

All Others

Bad Part

RAM SELF-CHECK SUBROUTINE-

Returns with the Z bit clear if any error is detected; otherwise, the Z bit is set.

FIGURE 10 -

SELF-CHECK PINOUT CONFIGURATION

+5V +5V

..

10 k :

>

~
> .~

+5V +5V

1

6~1

P

2

L----1..
XTAL
XTA L

10 k

10 k

~

2
,.27
8
9

..2Q
~
12
13

GND~

VDDJj

RESET

-

IRQ

NUM

TIMER

27

PCO

~

1£ I--

OSCl

PCl

OSC2

PC2

PAO

PC3

PAl

MC146805F2

PBO

PA2

PBl

PA3

PB2

PA4

PB3

PA5

PB4

PA6

PB5

PA7

PB6

VSS

PB7

3-918

24
23

~
~ I-20
19
18
17
16
15

MC146805F2

MEMORY

The stack pointer is used to address data stored on the
stack. Data is stored on the stack during interrupts and
subroutine calls. At power-up, the stack pointer is set to $7F
and it is decremented as data is pushed on the stack. When
data is removed from the stack, the stack pointer is incremented. A maximum of 32 bytes of RAM are available for
stack usage. Since most programs use only a small part of
the allocated stack locations for interrupts and/ or subroutine
stacking purposes, the unused bytes are available for program data storage.

The MC146805F2 has a total address space of 2048 bytes
of memory and I/O registers. The address space is shown in
Figure 11.
The first 128 bytes of memory (first half of page zero) is
comprised of the I/O port locations, timer locations, and 64
bytes of RAM. The next 1079 bytes comprise the user ROM.
The 10 highest address bytes contain the reset and interrupt
vectors.

FIGURE 11 -

ADDRESS MAP

o

S()()()()

Access
Via
Page 0
Direct
Addressing

127
128

I/O Ports
Timer
RAM

S()()()()
$0001

I

1 1 1 1

S007F

1

Port A Data Register
Port B Data Register

,

S0080

255
256

1279
1280

2037
2038
User
Defined
Interrupt
Vectors

1

1188ytes
Self-Check ROM

* Reads of unused locations undefined

RESET

$0006

Unused*

$0007

Timer Data Register

$0008

Timer Control Register

$0009
$OOOA

54 Bytes
Unused*

S04FF
$0500

$003F
S0040

63
64
RAM
(64 Bytesl

S077F
$0780

--------- --- Timer Interrupt From Wait State Only
----------Timer Interrupt
---External Interrupt
---SWI
----

2047

$0005

Unused*

10

S04B6
$04B7

640 Bytes
Unused*
1919
1920

SOOO4

Port B Data Direction Register

1079 Bytes
User ROM

73 Bytes
Self-Check ROM

$0002
$0003

Port A Data Direction Register

4

SOOFF
SOl00

1206
1207

Port C

Unused *

$005F

95 f 96

/ 7 $0060

$07F5

/'

/'

$07F6 $07F7

/'
/
/'

$07F8 $07F9

./
/

$07FA $07FB

./ ./ Stack (32 Bytes Maxi

1

$07FC $07FD
$07FE $07FF
./
127

3-919

./
./

+

$007F

I

MC146805F2

REGISTERS

PROGRAM COUNTER (PC)

The program counter is an 11-bit register that contains the
address of the next instruction to be executed by the processor.

The MCl46805F2 contains five registers as shown in the
programming model (Figure 12l. The interrupt stacking order
is shown in Figure 13.

STACK POINTER (SP)
The stack pointer is an 11-bit register containing the address of the next free location on the stack. When accessing
memory, the six most-significant bits are appended to the
five least-significant register bits to produce an address
within the range of $7F to $60. The stack area of RAM is
used to store the return address on subroutine calls and the
machine state during interrupts. During external or power-on
reset, and during a "reset stack pointer" instruction, the
stack pointer is set to its upper limit ($7Fl. Nested interrupts
and/ or subroutines may use up to 32 (decimal) locations
beyond which the stack pointer "wraps around" and points
to its upper limit thereby lOSing the previously stored information. A subroutine call occupies two RAM bytes on the
stack, while an interrupt uses five bytes.

ACCUMULATOR (A)

This accumulator is an 8-bit general purpose register used
to hold operands and results of the arithmetic calculations
and data manipulations.
INDEX REGISTER (X)

I

The X register is an 8-bit register whiCh is used during the
indexed modes of addressing. It provides the 8-bit operand
which is used to create an effective address. The index
register is also used for data manipulations with the readmodify-write type of instructions and as a temporary storage
register when not performing addreSSing operations.

FIGURE 12 -

PROGRAMMING MODEL

7

10

I

PCH

0

I
7
I
87
I

0

X

0

1

0

Index Register

0

I
I

PCl

5
1

Accumulator

0

10

1

I
I

A

I 0 I

I

4

Program Counter

0

I

SP

~
I

N

Z

C

Stack Pointer

condit. ion Code Register
Carry/Borrow
Zero
Negative
Interrupt Mask
Half Carry

FIGURE 13 - STACKING ORDER
Stack

IncreaSing Memory
Addresses

j~

1

11 l' 1 Condition Code Register
Accumulator
Index Register

01 0

10 10 1 0 1
PCL

PCH

11

DecreaSing Memory
Addresses

T

Unstack
NOTE: Since the Stack Pointer decrements during pushes, the PCL is
stacked first, followed by PCH, etc. Pulling from the stack is in
the reverse order.

3-920

MC146805F2

CONDITION CODE REGISTER (CC)

for a power-down reset. The power-on circuitry provides for
a 1920 tcyc delay from the time of the first oscillator operation. If the external RESET pin is low at the end of the 1920
time out, the processor remains in the reset condition.
Either of the two types of reset conditions causes the
following to occur:

The condition code register is a 5-bit register which indicates the results of the instruction just executed. These
bits can be individually tested by a program and specific action taken as a result of their state. Each bit is explained in
the following paragraphs.

• Timer control register interrupt request bit (TCR7) is
cleared to a "0".
• Timer control register interrupt mask bit (TCR6) is set
to a "1".
• All data direction register bits are clearerj to a "0". All
ports are defined as inputs.
• Stack pointer is set to $7F.
• The internal address bus is forced to the reset vector
($7FE, $7FF).
• Condition code register interrupt mask bit (I) is set to a
"1".
• STOP and WAIT latches are reset.
• External interrupt latch is reset.
All other functions, such as other registers (including output ports), the timer, etc., are not cleared by the reset conditions.

HALF CARRY BIT (H) - The H bit is set to a "1" when a
carry occurs between bits 3 and 4 of the ALU during an ADD
or ADC instruction. The H bit is useful in binary coded
decimal subroutines.
INTERRUPT MASK BIT (I) - When the I bit is set, both
the external interrupt and the timer interrupt are disabled.
Clearing this bit enables the above interrupts. If an interrupt
occurs while the I bit is set, the interrupt is latched and is
processed when the I bit is next cleared.
NEGATIVE (N) - Indicates that the result of the last
arithmetic, logical, or data manipulation is negative (bit 7 in
the result is a logical "1 ").
ZERO (Z) - Indicates that the result of the last arithmetic,
logical, or data manipulation is zero.

INTERRUPTS

CARRY /BORROW (C) - Indicates that a carry or borrow
out of the arithmetic logic unit (ALU) occurred during the
last arithmetic operation. This bit is also affected during bit
test and branch instructions, shifts, and rotates.

Systems often require that normal processing be interrupted so that some external event may be serviced. The
MC146805F2 may be interrupted by one of three different
methods, either one of two maskable interrupts (external input or timer) or a non-maskable software interrupt (SWIl.
Interrupts cause the processor registers to be saved on the
stack and the interrupt mask set to prevent additional interrupts. The RTI instruction causes the register contents to be
recovered from the stack and return to normal processing.
The stacking order is shown in Figure 13.
Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered
pending until the current instruction execution is complete.
When the current instruction is complete, the processor
checks all pending hardware interrupts and if unmasked,
proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Note that masked interrupts are latched for later interrupt service.
If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed as any other instruction. Refer to Figure 14 for the interrupt and instruction
processing sequence.

RESETS
The MC146805F2 has two reset modes: an active low external reset pin (RESET) and a power-on reset function; refer
to Figure 5.
RESET

The RESET input pin is used to reset the MCU to provide
an orderly software start-up procedure. When using the external reset mode, the RESET pin must stay low for a
minimum of one tRL. The RESET pin is provided with a
Schmitt Trigger input to improve its noise immunity.
POWER-ON RESET

The power-on reset occurs when a positive transition is
detected on VDD. The power-on reset is used strictly for
power turn-on conditions and should not be used to detect
any drops in the power supply voltage. There is no provision

3-921

•

MC146805F2

TIMER INTERRUPT
Each time the timer decrements to zero (transitions from
$01 to $00), the timer interrupt request bit (TCR7) is set. The
processor is interrupted only if the timer mask bit (TCR6) and
interrupt mask bit (I bit) are both cleared. When the interrupt
is recognized, the current state of the machine is pushed onto the stack and the interrupt mask bit in the condition code
register is set. This mask prevents further interrupts until the
present one is serviced. The processor now vectors to the

FIGURE 14 -

timer interrupt service routine. The address for this service
routine is specified by the contents of $7F8 and $7F9 unless
the processor is in a WAIT mode, in which case the contents
of $7F6 and $7F7 specify the timer service routine address.
Software must be used to clear the timer interrupt request
bit (TCR7). At the end of the timer interrupt service routine,
the software normally executes an RTI instruction which
restores the machine state and starts executing the interrupted program.

RESET AND INTERRUPT PROCESSING FLOWCHART

I
Stack
PC,X,A, CC

O-DDRs
CLR IRO Logic
FF-Timer
7F-Prescaler
7F-TCR

Timer
Load PC From:
SWI: 7FC17FD
IRO: 7FA17FB
TIMER: 7F817F9
Timer Wait: 7F617F7

Put 7FE on
Address Bus

Fetch
Instruction

SWI

Load PC
from
7FE17FF

Execute All
Instruction
Cycles

MC146805F2

EXTERNAL INTERRUPT

struction; refer to Figure 15. The second configuration
shows many interrupt lines "wire ORed" to form the interrupts at the processor. Thus, if after servicing an interrupt
Ithe IRQ remains low, then the next interrupt is recognized.

Either level- and edge-sensitive or edge-sensitive only inputs are available as mask options. If the interrupt mask bit
of the condition code register is cleared and the external interrupt pin (iR"O) is "low" or a negative edge has set the internal interrupt flip-flop, then the external interrupt occurs.
The action of the external interrupt is identical to the timer
except that the service routine address is specified by the
contents of $7FA and $7FB. Figure 15 shows both a functional diagram and timing for the interrupt line. The timing
diagram shows two different treatments of the interrupt line
(IRQ) to the processor. The first method is single pulses on
the interrupt line spaced far enough apart to be serviced. The
minimum time between pulses is a function of the length of
the interrupt service routine. Once a pulse occurs, the next
pulse should not occur until the MPU software has exited the
routine (an RTI occurs). This time (tILlL) is obtained byadding 20 instruction cycles (tcyc) to the total number of cycles
it takes to complete the service routine including the RTI in-

SOFTWARE INTERRUPT (SWI)
The software interrupt is an executable instruction. The
action of the SWI instruction is similar to the hardware interrupts. The SWI is executed regardless of the state of the interrupt mask in the condition code register. The service
routine address is specified by the contents of memory locations $7FC and $7FD.
The following three functions are not strictly interrupts,
however, they are tied very closely to the interrupts. These
functions are RESET, STOP, and WAIT.
RESET - The RESET input pin and the internal power-on
reset function each cause the program to vector to an initialization program. This vector is specified by the contents

FIGURE 15 -

EXTERNAL INTERRUPT

(a) Interrupt Functional Diagram

Level Sensitive
Mask Option
VDD

o
Interrupt Pin

External
Interrupt
Request

O~---~

----_~--_QlC

I Bit ICCR)

Power-On Reset
External Reset
External Interrupt
Being Serviced
(b) Interrupt Mode Diagram

IRO~tILIH

~

U
tILlL~1

Edge Condition
The minimum pulse width (tILlH) is one
tcyc. The period tlLlL should not be less
than the number of tcyc cycles it takes to
execute the interrupt service routine plus
20 tcyc cycles.

IRO(MPU)~L-______________________________- J
Mask Optional Level Sensitive
If after servicing an interrupt the IRO remains low, then the next interrupt is
recognized .

•

IROn

3-923

I

MC146805F2

of memory locations $7FE and $7FF. The interrupt mask of
the condition code register is also set. See preceding section
on Reset for details.

WAIT - The WAIT instruction places the MC146805F2 in
a low-power consumption mode, but the WAIT mode consumes somewhat more power than the STOP mode. In the
WAIT mode, the internal clock is disabled from all internal
circuitry except the timer circuit; refer to Figure 17. Thus, all
internal processing is halted, however, the timer continues
to count normally.
During the WAIT mode, the I bit in the condition code
register is cleared to enable interrupts. All other registers,
memory, and I/O lines remain in their last state. The timer
may be enabled by software prior to entering the WAIT
mode to allow a periodic exit from the WAIT mode. If an external and a timer interrupt occur at the same time, the external interrupt is serviced first; then, if the timer interrupt request is not cleared in the external interrupt routine, the normal timer interrupt (not the timer WAIT interrupt) is serviced
since the MCU is no longer in the WAIT mode.

STOP - The STOP instruction places the MC146805F2 in
its lowest power consumption mode. In the STOP function,
the internal oscillator is turned off causing all internal processing and the timer to be halted; refer to Figure 16.
During the STOP mode, timer control register (TCR) bits 6
and 7 are altered to remove any pending timer interrupt requests and to disable any further timing interrupts. External
interrupts are enabled in the condition code register. All
other registers and memory remain unaltered. All I/O lines
remain unchanged. The processor can only be brought out
of the STOP mode by an external IRQ or RESET.

I

FIGURE 16 -

STOP FUNCTION FLOWCHART

TIMER
The MCU timer contains an 8-bit software programmable
counter (timer data register) with a 7-bit software selectable
prescaler. Figure 18 contains a block diagram of the timer.
The counter may be preset under program control and decrements towards zero. When the counter decrements to zero,
the timer interrupt request bit (i.e., bit 7 of the timer control
register (TCR)) is set. Then, if the timer interrupt is not masked (i.e., bit 6 of the TCR and the I bit in the condition code
register are both cleared) the processor receives an interrupt.
After completion of the current instruction, the processor
proceeds to store the appropriate registers on the stack and
then fetches the timer vector address from locations $7F8
and $7F9 (or $7F6 and $7F7 if in the WAIT model in order to
begin servicing.
The counter continues to count after it reaches zero allowing the software to determine the number of internal or external input clocks since the timer interrupt request bit was
set. The counter may be read at any time by the processor
without disturbing the count. The contents of the counter
become stable, prior to the read portion of a cycle, and do
not change during the read. The timer interrupt request bit
remains set until cleared by the software. TCR7 may also be
used as a scanned status bit in a non-interrupt mode of
operation (TCR6= 1).
The prescaler is a 7-bit divider which is used to extend the
maximum length of the timer. Bit 0, bit 1, and bit 2 of the
TCR are programmed to choose the appropriate prescaler
output within the range of -<- 1 to -<- 128 which is used as the
counter input. The processor cannot write into or read from
the prescaler, however, its contents are cleared to all "Os" by
the write operation into TCR when bit 3 of the written data
equals one. This allows for truncation-free counting.
The timer input can be configured for three different
operating modes plus a disable mode depending on the value
written to the TCR4 and TCR5 control bits. Refer to the
Timer Control Register section.

Stop Oscillator
And All Clocks
TCR Bit 7- a
Bit 6- 1
Clear I Mask

Yes

TIMER INPUT MODE 1
If TCR5 and TCR4 are both programmed to a "0", the input to the timer is from an internal clock and the TIMER input pin is disabled. The internal clock mode can be used for

3-924

MC146805F2

FIGURE 17 - WAIT FUNCTION FLOWCHART

Oscillator Active
Clear I-Bit
Timer Clock Active
All Other Clocks
Stop

•
Fetch External
Interrupt, Reset,
or Timer Interrupt
Vector (from Wait
Mode only)

TIMER INPUT MODE 3
If TCR5= 1 and TCR4=O, all inputs to the timer are disabled.

periodic interrupt generation as well as a reference in frequency and event measurement. The internal clock is the instruction cycle clock. During a WAIT instruction, the internal
clock to the timer continues to run at its normal rate.

TIMER INPUT MODE 4
If TCR5= 1 and TCR4= 1, the internal clock input to the
timer is disabled and the TIMER input pin becomes the input
to the timer. The timer can, in this mode, be used to count
external events as well as external frequencies for generating
periodic interrupts. The counter is clocked on the falling
edge of the external signal.
Figure 18 shows a block diagram of the timer subsystem.
Power-on reset and the STOP instruction invalidate the contents of the counter.

TIMER INPUT MODE 2
With TCR5=O and TCR4= 1, the internal clock and the
TIMER input pin are ANDed to form the timer input signal.
This mode can be used to measure external pulse widths.
The external timer input pulse simply turns on the internal
clock for the duration of the pulse. The resolution of the
count in this mode is ± one internal clock and therefore, accuracy improves with longer input pulse widths.

3·925

MC146805F2

FIGURE 18 -

PROGRAMMABLE TIMER/COUNTER BLOCK DIAGRAM

External
Input

I

Cleared
by TCR3

• Timer 8·Blt Read/Write Counter
7·Blt Software Selectable Prescaler
Input Pin
Timer Interrupt

Read

Write

Interrupt

'~--------____~\/~__________- J /

Software Functions

NOTES:
1. Prescaler and timer data register are clocked on the falling edge of the internal clocks or external input.
2. The timer data register counts down continuously.

TCR3 - Timer Prescaler Reset bit: writing a "1" to this bit
resets the prescaler to zero. A read of this location always indicates "0". (Unaffected by RESET.)

TIMER CONTROL REGISTER (TCR)
76543210
ITCR71TCR61TCR51TCR41TCR31TCR21TCR11TCROI
All bits in this register except bit 3 are read/write bits.

TCR2, TCR1, TCRO - Prescaler select bits: decoded to
select one of eight outputs on the prescaler. (Unaffected by

l1t"SEi.)

TCR7 - Timer interrupt request bit: bit used to indicate
the timer interrupt when it is logic "1".
1 - Set whenever the counter decrements to zero or
under program control.
o - Cleared on external i"fESIT, power-on reset, STOP
instruction, or program control.

Prescaler
TCR2
0
0
0
0
1
1
1
1

TCR6 - Timer interrupt mask bit: when this bit is a logic
"1", it inhibits the timer interrupt to the processor.
1 - Set on external mIT, power-on reset, STOP instruction, or program control.
0- Cleared under program control.
TCR5 - External or internal bit: selects the input clock
source to be either the external timer pin or the internal
clock. (Unaffected by RESET.)
1 - Select external clock source.
o - Select internal clock source.

TCR1
0
0
1
1
0
0
1
1

TCRO
0
1
0
1
0
1
0
1

Result
.... 1
....2
.... 4
.... 8
....16
.... 32
....64
.... 128

INSTRUCTION SET
The MCU has a set of 61 basic instructions. They can be
divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type. All the instructions within a given type are presented in individual
tables.

TCR4 - External enable bit: control bit used to enable the
external TIMER pin. (Unaffected by RESET.)
1 - Enable external TIMER pin.
o - Disable external TIMER pin.
TCR5 TCR4
Internal Clock to Timer
0
0
1 AND of Internal Clock and TIMER
0
Pin to Timer
Inputs to Timer Disabled
1
0
1
1 TIMER Pin to Timer

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One
operand is either the accumulator or the index register. The
other operand is obtained from memory using one of the addreSSing modes. The operand for the jump unconditional
(JMP) and jump to subroutine (JSR) instructions is the program counter. Refer to Table 4.

3-926

MC146805F2

"contents of," an arrow indicates "is replaced by," and a
colon indicates "concatenation of two bytes." For additional
details and graphical illustrations, refer to the M6805 Family
User Manual.

READ-MODIFY-WRITE INSTRUCTIONS
These instructions read a memory location or a register,
modify or test its contents, and write the modified value
back to memory or to the register. The test for negative or
zero (TST) instruction is an exception to the read-modifywrite sequence since it does not modify the value. Refer to
Table 5.

INHERENT
In inherent instructions, all the information necessary to
execute the instruction is contained in the opcode. Operations specifying only the index registers or accumulator and
no other arguments are included in this mode.

BRANCH INSTRUCTIONS
Most branch instructions test the state of the condition
code register and, if certain criteria are met, a branch is executed. This adds an offset between - 127 and + 128 to the
current program counter. Refer to Table 6.
BIT MANIPULATION INSTRUCTIONS
The MCU is capable of setting or clearing any bit which
resides in the first 128 bytes of the memory space where all
port registers, port DDRs, timer, timer control, and on-chip
RAM reside. An additional feature allows the software to
test and branch on the state of any bit within the first 256
locations. The bit set, bit clear, and bit test and branch functions are implemented with a single instruction. For the test
and branch instructions, the value of the bit tested is also
placed in the carry bit of the condition code register. Refer to
Table 7.
CONTROL INSTRUCTIONS
These instructions are register reference instructions and
are used to control processor operation during program execution. Refer to Table 8.
OPCODE MAP
Table 9 is an opcode map for the instructions used on the
MCU.
ALPHABETICAL LISTING
The complete instruction set is given in alphabetical order
in Table 10.

ADDRESSING MODES
The MCU uses ten different addreSSing modes to provide
the programmer with an opportunity to optimize the code to
all situations. The various indexed addressing modes make it
possible to locate data tables, code conversion tables, and
scaling tables anywhere in the memory space. Short indexed
accesses are single-byte instructions while the longest instructions (three bytes) permit tables throughout memory.
Short and long absolute addreSSing is also included. Twobyte direct addressing instructions access all data bytes in
most applications. Extended addreSSing permits jump instructions to reach all memory. Table 10 shows the addressing modes for each instruction with the effects each instruction has on the condition code register. An opcode map is
shown in Table 9.
The term "Effective Address" (EA) is defined as the byte
address to or from which the argument for an instruction is
fetched or stored. The ten addressing modes of the processor are described below. Parentheses are used to indicate

IMMEDIATE
In immediate addressing, the operand is contained in the
byte immediately following the opcode. Immediate addressing is used to access constants which do not change during
program execution (e.g., a constant used to initialize a loop
counter).
EA= PC+ 1; PC-PC+2
DIRECT
In the direct addressing mode, the effective address of the
argument is contained in a single byte following the opcode
byte. Direct addressing allows the user to directly address
the lowest 256 bytes in memory with a single two-byte instruction. This includes all on-chip RAM and I/O registers
and 128 bytes of on-chip ROM. Direct addreSSing is efficient
in both memory and time.
EA=(PC+1); PC+PC+2
Address Bus High-a; Address Bus Low-(PC+ 1)
EXTENDED
In the extended addressing mode, the effective address of
the argument is contained in the two bytes following the opcode. Instructions with extended addressing modes are
capable of referencing arguments anywhere in memory with
a single three-byte instruction. When using the Motorola
assembler, the user need not specify whether an instruction
uses direct or extended addreSSing. The assembler
automatically selects the most efficient addressing mode.
EA=(PC+1):(PC+2); PC-PC+3
Address Bus High-(PC+ 1); Address Bus Low-(PC+2)
INDEXED, NO-OFFSET
In the indexed, no-offset addreSSing mode, the effective
address of the argument is contained in the 8-bit index
register. Thus, this addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is used to move a pointer through a table or
to address a frequently referenced RAM or I/O location.
EA= X; PC-PC+ 1
Address Bus High-a; Address Bus Low-X
INDEXED, 8-BIT OFFSET
Here the EA is obtained by adding the contents of the byte
following the opcode to that of the index register, therefore,
the operand is located anywhere within the lowest 511
memory locations. For example, this mode of addreSSing is
useful for selecting the mth element in an n element table. All
instructions are two bytes. The content of the index register

3-927

I

MC146805F2

(X) is not changed. The content of (PC+ 1) is an unsigned
8-bit integer. One-byte offset indexing permits look-up tables
to be easily accessed in either RAM or ROM.
EA= X+ (PC+ 1); PC- PC+2
Address Bus High--K; Address Bus Low-X+(PC+1)
where K = The carry from the addition of X + (PC + 1)
INDEXED, 16-BIT OFFSET

I

In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit
index register and the two unsigned bytes following the opcode. This addressing mode can be used in a manner similar
to indexed 8-bit offset, except that this three-byte instruction
allows tables to be anywhere in memory (e.g., jump tables in
ROM). As with direct and extended, the M6805 assembler
determines the most efficient form of indexed offset - 8 or
16 bit. The content of the index register is not changed.
EA=X+[(PC+1):(PC+2)); PC-PC+3
Address Bus High-(PC+1)+K;
Address Bus Low-X+(PC+2)
where K = The carry from the addition of X + (PC + 2)
RELATIVE

Relative addressing is only used in branch instructions. In
relative addressing, the contents of the 8-bit signed byte
following the opcode (the offset) is added to the PC if and
only if the branch condition is true. Otherwise, control proceeds to the next instruction. The span of relative addressing
is limited to the range of -126 to + 129 bytes from the
branch instruction opcode location. The Motorola assembler
calculates the proper offset and checks to see if it is within
the span of the branch.

EA=PC+2+(PC+1l; PC-EA if branch taken;
otherwise, PC - PC + 2
BIT SET/CLEAR
Direct addressing and bit addressing are combined in instructions which set and clear individual memory and 1/0
bits. In the bit set and clear instructions, the byte is specified
as a direct address in the location following the opcode. The
first 128 addressable locations are thus accessed. The bit to
be modified within that byte is specified with three bits of the
opcode. The bit set and clear instructions occupy two bytes:
one for the opcode (including the bit number! and the second for addressing the byte which contains the bit of interest.
EA= (PC+ 1); PC- PC+2

Address Bus High-O; Address Bus Low-(PC+ 1)
BIT TEST AND BRANCH

Bit test and branch is a combination of direct addressing,
bit addressing, and relative addressing. The bit address and
condition (set or clear) to be tested is part of the opcode.
The address of the byte to be tested is in the single byte immediately following the opcode byte (EA 1). The signed
relative 8-bit offset is in the third byte (EA2) and is added to
the PC if the specified bit is set or cleared in the specified
memory location. This single three-byte instruction allows
the program to branch based on the condition of any bit in
the first 256 locations of memory.
EA1 = (PC+ 11
Address Bus High-O; Address Bus Low- (PC+ 1)
EA2=PC+3+(PC+2); PC-EA2 if branch taken;
otherwise, PC - PC + 3

3·928

TABLE 4 -

REGISTER/MEMORY INSTRUCTIONS

3:

o

Addressing Modes
Immediate

Function

w

cO
I\)
CD

Mnemonic

Op
Code

Direct

#

#

Bytes

Cycles

Op
Code

Indexed
(No Offset)

Extended

#

#

Bytes

Cycles

Op
Code

Indexed
(S-Bit Offset)

#

#

#

Cycles

Op
Code

#

Bytes

Bytes

Cycles

F6

1

3

~

Indexed
Offset)

(1~Bit

#

#

#

Cycles

Op
Code

#

Bytes

Bytes

Cycles

E6

2

4

06

3

5

Op
Code

Load A from Memory

LOA

A6

2

2

B6

2

3

C6

3

4

Load X from Memory

LOX

AE

2

2

BE

2

3

CE

3

4

FE

1

3

EE

2

4

DE

3

5

Store A in Memory

STA

-

-

-

B7

2

4

C7

3

5

F7

1

4

E7

2

5

07

3

6

Store X in Memory

STX

-

-

-

BF

2

4

CF

3

5

FF

1

4

EF

2

5

OF

3

6

Add Memory to A
Add Memory and
Carry to A

ADD

AB

2

2

BB

2

3

CB

3

4

FB

1

3

EB

2

4

DB

3

5

AOC

A9

2

2

B9

2

3

C9

3

4

F9

1

3

E9

2

4

D9

3

5

Subtract Memory

SUB

AO

2

2

BO

2

3

CO

3

4

FO

1

3

EO

2

4

DO

3

5

Subtract Memory from
A with Borrow

SBC

A2

2

2

B2

2

3

C2

3

4

F2

1

3

E2

2

4

D2

3

5
5

AND Memory to A

AND

A4

2

2

B4

2

3

C4

3

4

F4

1

3

E4

2

4

D4

3

OR Memory with A

ORA

AA

2

2

BA

2

3

CA

3

4

FA

1

3

EA

2

4

DA

3

5

Exclusive OR Memory
with A

EOR

A8

2

2

B8

2

3

C8

3

4

F8

1

3

E8

2

4

D8

3

5

CMP

A1

2

2

B1

2

3

C1

3

4

F1

1

3

E1

2

4

D1

3

5

CPX

A3

2

2

B3

2

3

C3

3

4

F3

1

3

E3

2

4

D3

3

5

Arithmetic Compare A
with Memory
Arithmetic Compare X
with Memory
Bit Test Memory with
A (Logical Compare)

BIT

A5

2

2

B5

2

3

C5

3

4

F5

1

3

E5

2

4

D5

3

5

Jump Unconditional

JMP

-

-

-

BC

2

2

CC

3

3

FC

1

2

EC

2

3

DC

3

4

Jump to Subroutine

JSR

-

-

-

~

5 - - _CD

3

6

FD

1

5

ED

2

6

DD

3

7

-

2_

L. _ _

TABLE 5 -

-

READ-MODIFY-WRITE INSTRUCTIONS
Addressing Modes
I

Inherent (A)

Inherent (X)

Indexed
(No Offset)

Direct

Indexed
(S-Bit Offset)

#

.

Op
Code

#
Bytes

#
Cycles

Op
Code

#
Bytes

#
Bytes

#
Cycles

Op
Code

#
Bytes

Cycles

Op
Code

#

Cycles

Op
Code

#

Mnemonic

Bytes

Cycles

Increment

INC

4C

1

3

5C

1

3

3C

2

5

7C

1

5

6C

2

6
6

Function

#

!

Decrement

DEC

4A

1

3

5A

1

3

3A

2

5

7A

1

5

6A

2

Clear

CLR

4F

1

3

5F

3

3F

2

5

7F

1

5

6F

2

6

Complement

COM

43

1

3

53

1
1

3

33

2

5

73

1

5

63

2

6

Negate
(2's Complement)

NEG

40

1

3

50

1

3

30

2

5

70

1

5

60

'2

6

Rotate Left Thru Carry

ROL

49

1

3

59

1

3

39

2

5

79

1

5

69

2

6

Rotate Right Thru
Carry

ROR

46

1

3

56

1

3

36

2

5

76

1

5

66

2

6

Logical Shift Left

LSL

48

1

3

58

1

3

38

2

5

78

1

5

68

2

6

Logical Shift Right

LSR

44

1

3

54

1

3

34

2

5

74

1

5

2

6

Arithmetic Shift Right

ASR

47

1

3

57

1

3

37

2

5

17

1

5

64
67

2

6

Test for Negative
or Zero

TST

4D

1

3

5D

1

3

3D

2

4

7D

1

4

6D

2

5

..

~
0)

CO

o

U1

."
N

MC146805F2

TABLE 6 -

BRANCH INSTRUCTIONS
Relative Addressing Mode

Function

Mnemonic

I

I

Bytes

Cycles
3

Branch Always

BRA

20

2

Branch Never

BRN

21

2

3

Branch IFF Higher

BHI

22

2

3

BLS

23

2

3

BCC
(BHS)

24

2

3

24

3

BCS
(BLO)

25

2
2

25

2

3

Branch IFF Not Equal

BNE

26

2

3

Branch IFF Equal

BEO

27

2

3

Branch IFF Half Carry Clear

BHCC

28

2

3

Branch IFF Half Carry Set

BHCS

29

2

3

BPL

2A

2

3

Branch IFF Minus

BMI

2B

2

3

Branch IFF Interrupt Mask Bit is Clear

BMC

2C

2

3

Branch IFF Interrupt Mask Bit is Set

BMS

20

2

3

Branch IFF Interrupt Line is Low

BIL

2E

2

3

Branch IFF Interrupt Line is High

BIH

2F

2

3

Branch to Subroutine

BSR

AD

2

6

Branch IFF Lower or Same
Branch IFF Carry Clear
(Branch IFF Higher or Same)
Branch IFF Carry Set
(Branch IFF Lowed

I

Op
Code

Branch IFF Plus

TABLE 7 -

3

BIT MANIPULATION INSTRUCTIONS
Addressing Modes
Bit Test and Branch

Bit Set/Clear

Branch IFF Bit n is Set
Branch IFF Bit n is Clear
Set Bit n
Clear Bit n

Op
Code

Mnemonic

Function

#

#

Bytes

Cycles

Op
Code

#

#

Bytes

Cycles
5

BRSET n (n=O .. 7)
7)

-

-

-

2-n

3

-

-

-

01 + 2-n

3

5

BSET n (n=O .. 71
BCLR n (n=O .. 7)

10+2-n

2

5

-

-

-

11 + 2-n

2

5

-

-

-

BRCLR n (n=O

TABLE 8 -

CONTROL INSTRUCTIONS
Inherent
Mnemonic

Op
Code

I

I

Bytes

Cycles

Transfer A to X

TAX

97

1

2

Transfer X to A

TXA

9F

1

2

2
2
2
2
10
6
9
2
2
2
2

Function

Set Carry Bit

SEC

99

1

Clear Carry Bit

CLC

98

1

Set Interrupt Mask Bit
Clear Interrupt Mask Bit

SEI
CLI

9B
9A

83

1
1
1
1
1
1
1
1
1

Software Interrupt

SWI

Return from Subroutine

RTS

81

Return from Interrupt

RTI

80

Reset Stack Pointer

RSP

9C

No-Operation

NOP

90

Stop

STOP

BE

Wait

WAIT

BF

3-930

s:

0....

TABLE 9- INSTRUCTION SET OPCODE MAP

I Branch

Bit Manipulation

EXT

1X2

J.Kl

IX

1011

1100

1101

1110

1111

A

2

0010

CXXll
2
0010

3

2

Bse

2

4
0100
5
QlQl

BRCLR25
BCLR2
I3
BTB I 2
Bse

!m.!.

r-

J

Ql!Q

Qill
8
lCXXl

VJ

t=:t
1 10
B

!.Ql!

C
1100

E

illQ
F

1111

INH

51

1
-51
B.__R_.SET35..
BSET3

_.JlilL

2~

5L

REI

3[ L COM
~ COMX 3 COM
COMA
IXl I
__ D18_ 1
JNH 1 __ .lliJ::L1 2
31
51
LSR
LSRA 31
LSRX 3
BCC
LSR
REL 2
DTR
INH
INH I 2
IXI I
BLS
___ REL

1

~REL.2.

5[2

-----:r] 2

I

2

I

2

BSET6 51
Bse 2

5[---

BRCLR6
3
BTB

-~------:r

BCLR5
Bse

2

1

51

BRCLR5
BTB
5
BRSET6
I3
BTB

COM
1

SWI
IX I 1
INH

2
2

ROR
ROR 51
RORA 31
RORX 31
ROR
IX
DIR 1
INH 1
INH 2
IXI I 1 - - - 5
ASR 51
ASRA 31
ASRX 31
ASR
ASR
DIR 1
INH 1
INH 2
IX 1 I 1
IX
--5
L~-:
LSLA 3 I --LSLX 31-- LSL 6
LSL
DIR 1
INH I 1
INH 2
IXI 1
IX
--5
3
6
--51
-- 3
ROLX
ROL
ROL
ROLA
ROL
DIR 1
INH I 1
INH 2
IXI 1
IX
--5
3
6
---3
DECX
DEC
DEC
DEC
DECA
INH 2
IXI 1
DIR 1
INH I 1

51

1.1

51 ---

2
INH
2
RSP
1
INH
2
Nap
1
INH

-~M~

REL I 2

1

5

INC

DIR
4

TST
BMS
1
2
REL 2
DIR

INCA 31
1

INH

3
TSTA
1
INH

6

INCX 3
1

INH

INC
2

3

TSTX
INH
1

TST
2

IXI
5
IXI

5

INC
IX

1

4

TST
IX

1

51

BRSET751 BSET7
BIL
I3
BTB 2
Bse 2
REL
5
51
~-.-----:l
CLR
BRCLR7
BCLR7
BIH
3
BTB 2
Bse 2
REL I 2
DIR

I

3
CLRA
1
INH

3

CLRX
1
INH

5

6

CLR
2

IXI

CLR
1

IMM

DIR
EXT
REL
BSC
BTB
IX
IXl
IX2

Inherent
Immediate
Direct
Extended
Relative
Bit Set I Clear
Bit Test and Branch
Indexed (No Offset)
Indexed, 1 Byte (S-Bit) Offset
Indexed, 2 Byte (l6-Bit) Offset

SBC
DIR

CPX
2
DIR
3

Jl

STOP 21
INH

2 ANDDIR

2 EOR
IMM
2
ADC
IMM
2
ORA'
IMM
2

ORA j
2
DIR

ADD 2
IMM

ADD 3
DIR
2
JMP
DIR
2

2

4

EaR
EXT

3

EOR
3

4

ADC

IX2
5

3

ORA •
3
EXT

ORA"
IX2
3

4

ADD
EXT
3
JMP
EXT
3

3

DIR

LDX 3
DIR
2

LDX
EXT
3

STX
DIR
2

2

SBC

~I

SBC

IXl

4

STX 5
EXT
3

3

IX2

ADD 5
IX2
4

JMP
3

IX2

3

IX2

LDX 5
IX2
3
6
STX
IX2
3

J

IX

1

EaR

2

ADC

IXl
IXl

ORA 4
2
IXl
4

1
1
1
1

IX

1

EaR

IX

2

STX

IXl
5
IXI

7
0111

IX

8
lCXXl

3

1

AOC
ORA

1001

J

A
1010

1

1

9

IX
IX

1

4

2

6
0110

3

0

IXl
LDX

5
0101

4

STA

JSR

2

3
0011

3

LOA

JSR

IXl

2
0010

4-3 r-----illf&
BIT IX

JMP 3
2
IXI

ADD

1
CXXll

4

AND

ADD 3
IX
2
JMP
IX
1

2

ck l

3

4

7

JSR

CPX

4

2

J

IX

1

4

5

ADC
EXT
3

6

2

IX2
5

41- --

JSR
EXT
3

JSR

4

WAIT 21 TXA 2
IX I 1
INH 1
INH

SBC

CPX 41
CPX
CPX
IXl
3
EXT 3
IX2 2
4
4
5
I 3 AN~XT I 3 AND ,X2 1 2 AND ,X1 I
51 BIT
81T
BIT
3
EXT 3
IX2 2
IXI I
4 I
5 I
LDA
LDA
LOA
IX2 2
IXl
3
EXT 3
5
6
5
STA
STA
STA
IXI
EXT 3
IX2 2
3

5

6

BSR
REL
2
2
LDX
IMM
2

4

5

SB~XT I 3

3

3

Abbreviations for Address Modes
INH

4

3

2

4

2

0

F

"J

STA
DIR
2
3
EaR
2
DIR
3
ADC
DIR
2

2

E

SUB 3
SUB
SUB 41
SUB
SUB
EXT 3
IX2 _2
IXl I 1
IX
DIR 13
4 I
5 I
3
CMP
CMP
CMP
CMP
CMP
IXl I
IX
DIR 3
IX2 2
2
EXT I 3

BIT
BIT
12
IMM 2
DIR
21
LDA
LDA
IMM 2
DIR
2

SEI

BMI
REL

~-----:r

BCLR6
2
Bse

2
TAX
1
INH
2
CLC
'NH
2
SEC
1
INH
2
CLI
1
INH

0

2

2J-I 3

AN~MM

LSR
1

31 -

BNE.

I

3

1

10

BCS
2
REL

BRCLR351 BCLR3 51
BEQ 31
13
BTB 2
Bse 2
REL
3
BRSET45 r-ssET451 BHc-Z
13
BTB 2
Bse 2
REL
51···
']
BRCLR4
BCLR4
BHC.S
3
BTB 2 __.J!Se 2
REL
5131
BRSE. T5.
BSET5
BPL
BTEi 2
.sse 2
REL
L3

0
l.lQl

5r--

BRCLR1
BCLRl
3
BTB. 2il.SC

6
7

SUB LI
IMM
21
CMP
IMM
2
2
SBC
IMM
2
2
CPX
IMM
2
2

RTS

C

B

12

l)~-~-3
BSET1
BHI

BRSET1
BTB

51 2
5GBRSET2
BSET2 51
I3
BTB 2
Bse 2

3

VJ

OIR

1010

1

0001

I3

1

"""'"

IMM

0CXXl

BRSET05} BSETO 51
BRA
BTB 2
Bse 2
REL I 2
5
BRCLR0 1 BCLRO 51
BRN
3
BTB 2
Bse 2
REL

0
~

cO

Register/Memory

B~l_~~

o

~

Low

,a::...

Q)
Q)

"
IX

B
1011
C
1100

0

1101

3

LOX
1

IX

E
1110

4

STX
1

IX

F

1111

LEGEND
~~~I~------------~

Mnemonic
Bytes

4"

-t

1

Cycles - - - - - - - '

oj?

;0x
J

-

~

J

Opcode in Hexadecimal

Opcode in Binary

WXJ ~
"

Address Mode

c.n

"
N

MC146805F2

TABLE 10 -

INSTRUCTION SET

Addressing Modes
Mnemonic

I

Inherent

ADC
ADD
AND
ASL
ASR
BCC
BCLR
BCS
BEG
BHCC
BHCS
BHI
BHS
BIH
BIL
BIT
BLO
BLS
BMC
BMI
BMS
BNE
BPL
BRA
BRN
BRCLR
BRSET
BSET
BSR
CLC
CLI
CLR
CMP
COM
CPX
DEC
EOR
INC
JMP
JSR
LOA
LOX
LSL
LSR
NEG
NOP
ORA
ROL
ROR
RSP
RTI
RTS
SBC
SEC
SEI
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT

Immediate

Direct

Extended

x
x

x
x

X

X

X
X
X

X
X

Relative

Condition Codes

Indexed
(No Offset)

Indexed
(8 Bits)

Indexed
(16 Bits)

x
x

x
x

X
X
X

X
X
X

X
X
X

x
X

Bit

Setl
Clear

Bit
Test &
Branch

N Z C

H
A
A

A A A
•

X
X
X
X
X
X
X
X
X
X

X

X

X

~~

•

A
A A A
A A A

••
••
••
•
•
••

X

X

AA

•••
••
••
•
•
•

A A

X

X
X
X
X
X
X
X
X
X
X
X

A

•

X
X
X
X
X

0
X

X
X
X
X
X

X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X

X
X

X
X
X

X
X
X
X
X
X
X
X

X

x

x

X
X
X
X
X

X
X
X
X
X

X
X

x
X
X
X
X
X

X

X

• •

X
X
X

X

X
X
X

X
X
X

X

X

X

X

X

X

X

X

X

X

X

X

X
X

X
X

X
X

X
X

X
X

X

X

X
X

1

X
X
X
X
X
X
X

X

•
0
••
1
••
••
0

Condition Code Symbols
H
I
N
Z

Half Carry I From Bit 31
Interrupt Mask
Negative ISlgn BI1I
Zero

C

Carry! Borrow

A
•
?

o

Test and Set If True. Cleared OtherWise
Not Affected
Load CC Register From Stack
Cleared
Sot

3-932

1
A
A 1
A A
A
A
A

••
•• •• •••
A A •
A A •

X

X

X
X
X
X
X

0
A
A
A
A
A
A

X

•0
••
A

A A A
0 A A
A A A

•A •A ••
A A A
A A A
•••
•A •A •A
•• 1
•A •A •
•A •A •••
A A A
•• •• ••
A A
• • ••
•••

MC146805F2

ORDERING INFORMATION

VERIFICATION MEDIA

All original pattern media (EPROM or floppy disk) are filed
for contractual purposes and are not returned. A computer
listing of the ROM code will be generated and returned along
with a listing verification form. The listing should be
thoroughly checked and the verification form completed,
signed, and returned to Motorola. The signed verification
form constitutes the contractual agreement for creation of
the customer mask. If desired, Motorola will program a blank
2716 EPROM (supplied by the customer) from the data file
used to create the custom mask to aid in the verification process.

The following information is required when ordering a
custom MCU. This information may be transmitted to
Motorola in the following media:
EPROM MCM2716
MOOS disk file
To initiate a ROM pattern for the MCU it is necessary to
first contact your local field service office, local sales person,
or your local Motorola representative.
EPROMs

The MCM2716 type EPROM, programmed with the
customer program (positive logic sense for address and
data), may be submitted for pattern generation. The
customer program should begin at address $080 (the address
at which customer ROM begins on the MC146805F2) so that
the EPROM maps directly into the MC146805F2. If the
customer program starts at any other address, please mark
the EPROM accordingly. See Figure 19 for recommended
marking procedure.
After the EPROM is marked, it should be placed in a conductive IC carrier and securely packed. Do not use
styrofoam.

FIGURE 19 -

EPROM MARKING

xxx

080

xxx = Customer I. D.

ROM VERIFICATON UNITS

Ten MCUs containing the customer's ROM pattern will be
sent for program verification. These units will have been
made using the custom mask but are for the purpose of
ROM verification only. For expediency they are usually unmarked, packaged in ceramic, and tested only at room
temperature and 5 volts. These RVUs are included in the
mask charge and are not production parts. These RVUs are
not backed nor guaranteed by Motorola Quality Assurance.
FLEXIBLE DISKS
The disk media submitted must be single-sided, singledensity, 8-inch, MOOS-compatible floppies. The customer
must write the binary file name and company name on the
disk with a felt-tip pen. The floppies are not to be returned by
Motorola as they are used for archival storage. The minimum
MOOS system files as well as the absolute binary object file
(file name. LO type of file) from the M6805 cross assembler
must be on the disk. An object file made from a memory
dump using the ROLLOUT command is also admissable.
Consider submitting a source listing as well as the following
files: filename, LX (EXORciser loadable format) and filename
.SA (ASCII source code). These files will be kept confidential
and used 1) to speed up the process in-house if any problems
arise. and 2) to speed up our customer-to-factory interface if
a user finds any software errors and needs assistance quickly
from the factory representatives.
MOOS is Motorola's Disk Operating System available on
development systems such as EXORciser, EXORsets, etc.

3-933

I

MC146805F2

OPTION LIST

Select the options for your MCU from the following list. A manufacturing mask will be generated from this information. Select
one in each section.
Internal Oscillator Input
Crystal
Resistor

o
o

Internal Divide
->-4
->-2

o
o

Interrupt
Edge-Sensitive
Level- and Edge-Sensitive

o
o

II

Customer Name _________________________________________________________________________________

Address ___________________________________________________________________________________
City _________________________________________

State _________________________ Zip _____________

Phone (_____ )_____________________________ Extension ___________________________________________
Contact Ms/Mr _________________________________________________________________________________
Customer Part Number ____________________________________________________________________________

Pattern Media
02716 EPROM

o
o

MDOS Disk File
Silent 700 Cassette

o

Card Deck

o
o

Tape of Card Deck
(Note 1) _____________________________________________________________

NOTE 1. Other media require prior factory approval.

Signature ______________________________________________________________________________________
Title _________________________________________________________________________________________

Silent 700 Cassette is a trademark of Texas Instruments Incorporated

3-934

®

MC146805G2

MOTOROLA

Advance Information

CMOS
IHIGH-PERFORMANCE SILICON-GATE)

8-BIT MICROCOMPUTER UNIT

8-BIT
MICROCOMPUTER

The MC146805G2 Microcomputer Unit (MCU) belongs to the
M146805 CMOS Family of Microcomputers. This 8-bit MCU contains
on-chip oscillator, CPU, RAM, ROM, I/O, and TIMER. The fully static
design allows operation at frequencies down to dc, further reducing its
already low-power consumption. It is a low-power processor designed
for low-end to mid-range applications in the consumer, automotive, industrial, and communications markets where very low power consumption constitutes an important factor. The following are the major
features of the MC146805G2 MCU.

I

HARDWARE FEATURES
•

Typical Full Speed Operating Power of 12 mW at 5 V

•

Typical WAIT Mode Power of 4 mW

•

Typical STOP Mode Power of 5 p.W

•

Fully Static Operation

•

112 Bytes of On-Chip RAM

•

2106 Bytes of On-Chip ROM

•

32 Bidirectional I/O Lines

•
•

High Current Drive
Internal 8-Bit Timer with Software Programmable 7-Bit Prescaler

•
•

External Timer Input
External and Timer Interrupts

•
•

Self-Check Mode
Master Reset and Power-On Reset

•
•

Single 3 to 6 Volt Supply
On-Chip Oscillator with RC or Crystal Mask Options

•

4O-Pin Dual-In-Line Package

Z SUFFIX
CHIP CARRIER
CASE 761

PIN ASSIGNMENT

• Chip Carrier Also Available
SOFTWARE FEATURES

RESET

VDD

IRQ

2131

OSCl

NUM

3141

OSC2

5161

PD7

7181

PD5

PA7
PA6

•

Similar to the MC6800

•

Efficient Use of Program Space

PA5

•

Versatile Interrupt Handling

PM

•
•

True Bit Manipulation
AddreSSing Modes with Indexed Addressing for Tables

PA3

•

Efficient Instruction Set

•
•
•

TIMER

PD6

PD4

PA2

PD3

PAl

101111

132131

Memory Mapped I/O
Most Self-Check Routines User Callable

PAO

11 1121

Two Power Saving Standby Modes

PBO

PD~

PBl

PCO

PD2
PDl

PB2

PCl

Frequency (MHz)

Temperature

Generic Number

PB3

PC2

Ceramic
L Suffix

1.0
1.0

O°C to 70°C
-40°C to 85°C

MCl46805G2L
MC146805G2CL

PB4

PC3

Cerdip
S Suffix

1.0
1.0

O°C to 70°C
-40°C to 85°C

MC146805G2S
MC146805G2CS

PB5

PC4

PB6

PC5

Plastic
P Suffix

1.0
1.0

O°C to 70°C
-40°C to 85°C

MC146805G2P
MC146805G2CP

PB7

PC6

VSS

PC7

GENERIC INFORMATION
Package Type

Leadless Chip
Carrier
Z Suffix

1.0
1.0

O°C to 70°C
-40°C to 85°C

MC 146805G2Z
MC146805G2CZ

This document contains mformatlon on a new product Specifications and information herein
are subject to change Without notice

3-935

Pin numbers in parentheses represent equivalent Z
suffix chip carrier pins.

MC146805G2

MAXIMUM RATINGS (Voltages Referenced to Vss)
Symbol

Value

Unit

Supply Voltage

Vo

-0.3 to +8.0

V

All Input Voltages Except OSC1

Yin

VSS-0.5 to VDD+0.5

V

I

10

mA

TA

TL to TH
to 70
-40 to 85

°C

Storage Temperature Range

Tstg

-55 to + 150

°C

Current Drain Total (P04-PD7 only)

10H

40

mA

Ratings

Current Drain Per Pin Excluding VDO and VSS
Operating Temperature Range
MCl46805G2
MCl46805G2C

o

THERMAL CHARACTERISTICS
Characteristics

I

Symbol

Thermal Resistance
Plastic
Cerdip
Ceramic
Chip Carrier

9JA

FIGURE 1 -

Value

100
60
50
100

Unit

°C/W

This device contains circuitry to protect the
inputs against damage due to high static
voltages of electric fields; however. it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high impedance circuit. For proper operation it is
recl)mmended that Vin and Vout be constrained to the range VSS s (Vin or
V out ) s VDO. Reliability of operation is
enhanced if unused inputs except OSC2 and
NUM are tied to an appropriate logic voltage
level (e.g .. either VSS or VDDI.

MCl46805G2 CMOS MICROCOMPUTER

OSC2

RESET
1

IRQ

2

TIMER

Port
A
I/O
Lines

Port
B
I/O
Lines

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7

P80
PBl
PB2
PB3
PB4
PB5
PB6
PB7

Accumulator
A
8
Port
A
Reg

Data
Olr
Reg

Index
Register

CPU
Control

X

Condition
Code
Register CC

Data
Dlr
Reg

Port
C
Reg

Data
Olr
Reg

Port
0
Reg

CPU

Stack
POinter

Port
B
Reg

S
Program
Counter
High PCH

Data
Dir
Reg

NOTE:
See Pin Assignments diagram for equivalent chip carrier pin numbers.

8

ALU

Program
Counter
Low PCL

198x8
Self-Check
ROM

3-936

PCO
PCl
PC2
PC3
PC4
PC5
PC6
PC7

POO
PDl
PD2
PD3
PD4
P05
PD6
P07

Port

C
1·0
Lines

Port

0
1.0
Lines

MC146805G2

DC ELECTRICAL CHARACTERISTICS (VDD= 5.0 Vdc ± 10%, VSS=O Vdc, T A =0° to 70°C unless otherwise noted)
Characteristics
Output Voltage ILoad:510.0 p.A
Output High Voltage
(iLoad= -100 p.A) PBO-PB7, PCO-PC7

Symbol

Min

Max

Unit

VOL
VOH

-

0.1

VDD-O.l

-

V
V

VOH

2.4

-

V

(iLoad= -2 mA) PAO-PA7, PDO-PD3

VOH

2.4

-

V

(ILoad= -S mA) PD4-PD7

VOH

2.4

-

V

VOL

-

0.4

V

Output Low Voltage
(I Load = SOO p.A) All Ports
PAD-PA7, PSO-PS7, PCO-PC7, PDO-PD7
Input High Voltage
Ports PAO-PA7, PBO-PB7, PCO·PC7, PDO-PD7

VIH

VDD-2.0

VDD

V

VIH

VDD-O.S

V

Input Low Voltage All Inputs

VIL

VSS

VDD
O.S

Total Supply Current (CL = 50 pF on Ports, no dc Loads, tcyc= 1 p.s)
RUN (VIL = 0.2 V, VIH = VDD - 0.2 V)

TIMER,

TIm, liESET,

OSCl

V

IDD

-

4

mA

WAIT (See Note)

IDD

-

1.5

mA

STOP (See Note)

IDD

-

150

p.A

I/O Ports Input Leakage
PAD·PA7, PBO-PB7, PCO-PC7, PDO-PD7

IlL

-

±10

p.A

Input Current
RESET, IRO, TIMER, OSCl

lin

-

±1

p.A

Cout

-

12

pF

Cin

-

S

pF

Capacitance
Ports
RESET, IRO, TIMER, OSCl

DC ELECTRICAL CHARACTERISTICS (VDD = 3.0 Vdc, VSS = 0 Vdc, T A = 0° to 70°C unless otherwise noted)
Characteristics
Output Voltage ILoad:51.0 p.A
Output High Voltage
(ILoad= -50 p.A) PSO·PB7, PCO·PC7

Symbol

Min

Max

Unit

VOL
VOH

-

0.1

VDD-O.l

-

V
V

VOH

1.4

-

V

(iLoad= -0.5 mA) PAO-PA7, PDO-PD3

VOH

1.4

-

V

(ILoad= -2 mA) PD4-PD7

VOH

1.4

-

V

Output Low Voltage
(iLoad= 300 p.A) All Ports PAD-PA7, PBO-PS7, PCO-PC7, PDO-PD7

VOL

-

0.3

V

Input High Voltage
Ports PAO-PA7, PBO·PB7, PCO-PC7, PDO-PD7

VIH

2.7

VDD

V

VIH

2.7

Input Low Voltage All Inputs

VIL

VSS

VDD
0.3

V

Total Supply Current (no dc Loads, tCyc= 5 p.s)
RUN (VIL=O.l V, VIH=VOD-O.l V)

mA

TIMER, IRO, RESET, OSCl

V

IDO

-

0.5

WAIT (See Note)

IDD

-

200

p.A

STOP (See Note)

IDD

-

100

p.A

I/O Ports Input Leakage
PAD-PA7, PBO-PB7, PCO-PC7, PDO·PD7

IlL

-

±5

p.A

Input Current
RESET, IRO, TIMER, OSCl

lin

-

±1

p.A

Cout

-

12

pF

Cin

-

S

pF

Capacitance
Ports
RESET, IRO, TIMER, OSCl

NOTE: Test conditions for IDD are as follows:
All ports programmed as inputs
VIL =0.2 V (PAO-PAl, PBO-PB7, PCO-PC7, PDO·PD7)
VIH=VDO-0.2 V for RESET, IRO, TIMER
OSCl input is a squarewave from 0.2 V to VDD - 0.2 V
OSC2 output load = 20 pF (wait IDD is affected linearly by the OSC2 capacitance).

I

MC146805G2

TABLE 1 - CONTROL TIMING
(VDD=5.0 Vdc ± 10%, VSS=O, TA=Oo to 70°C, losc=4 MHz)
Symbol
toxOV

Characteristics
Crystal Oscillator Startup Time (Figure 11)
Stop Recovery Startup Time (Crystal Oscillator) (Figure 12)
Timer Pulse Width (Figure 10)
Reset Pulse Width (Figure 11)

Min

-

tlLCH

-

tTH, tTL
tRl

0.5
1.5
1.0
1.0

-

*

-

tTLTl
t(LlH
t(LlL
tOH, tOl
tcyc

Timer Period (Figure 10)
Interrupt Pulse Width Low (Figure 21)
Interrupt Pulse Period (Figure 21)
OSCl Pulse Width
Cycle Time
Frequency 01 Operation
Crystal
External Clock

Max
100
100

Unit
ms
ms
tcyc
tcyc
tcyc
tcyc
tcyc
ns
ns

-

-

100
1000

-

lose

-

lose

DC

4.0
4.0

MHz
MHz

* The

I

minimum period tl LI l should not be less than the number 01 tcyc cycles It takes to execute the Interrupt service routines plus 20 tcyC
cycles.

FIGURE 2 Port
Band C
A, PDO-PD3

R1
24.3 kO
1.21 kO

R2
4.32 kO
3.1 kO

PD4-PD7

3000

1.64 kO

EQUIVALENT TEST LOAD
VDD=4.5 V
Iload
~

MMD6150
or Equiv.

Test Point
R1
(See
Table)

50pF

FIGURE 3 - TYPICAL OPERATING CURRENT vs INTERNAL FREQUENCY

(mAl
4. 0

~

;:: 3.0

~\)~

I13

. , / ~~~

C!>

~ 2.0

~

/

~
-'

~

1.0

~

.......::
0

~

~ ...----

-

L

;...-

~

-

V" V

I"

Voo-4 V

...oIIIII!!!!!!::::-~00-3V
0.2

0.4
0.6
INTERNAL FREQUENCY (1/tcycl.

3-938

0.8

1.0

(MHzl

R2
(See
Table)

MMD7000
or Equiv.

MC146805G2

FIGURE 4 -

MAXIMUM IDD vs FREQUENCY

4.0

~J\~~ V

2.0

E

V

/

1.0

./

/

0

"

"'r--..

VOO= 5 V ± 10%

"'I'...

-1.2

.§.
:z::
0

-0.8

-0.4

2.0

2.5

---

1--1"'"'

40

80
120
FREQUENCY IkHzl

"'r--...

~

~

STO~ 100

160

200

I

MINIMUM IOH, PORT C

I .4 V, -200 I'AI

'"
'"

~ -100

'"

VOO-5V±10%

"" "

l~ 1 V, 0j5 mAl

f'

4.0

o

2.5

2.0

4.5

MINIMUM IOH, PORT A AND B

"

3.0
3.5
VOH IVOLTSI

FIGURE 9 -

VOO- 5 V ± 10%

3.0
3.5
VOH IVOLTSI

......

4.0

~~ ~~

VOO-5 V ±10%
~

1.2

c

0.8

V

14.1 V, 200 I'M

0.4

~
4.0

4.5

o
o

:/

:/

V

~7

.§.

"

4.5

MINIMUM IOL, ALL PORTS

1.6

"',,'"
"

"-..14.1 V, 50 I'M

2.0

12.4 V, - 2 mAl

" '"

-1.6

~

~

3.0
3.5
VOH IVOLTSI

FIGURE 8 -

~

FIGURE 7 -

"' ....

'" ""-

2.5

--

L

V

o
o

1.0

-200

-2.0

o

£.

/

""-,

~ -4.0

~

0.8

12.4 V, -8 mAl

E

-2.0

100

.......

~

20

r--r-

200

MINIMUM IOH, PORT D PINS 33-36

-6.0

o

~

115O l'AI

0.4
0.6
FREQUENCY IMHzl

FIGURE 6 -8.0

-

j

11.5 rnA, 1 MHzl

STOP 100

0.2

/

,/

f--

~

./

~?

300

~

./

~

f-vooL V

/

'tlMi\1l1l

.£.. ~

-

V

VOO- 5 V ±110 %

1c

400

14mA,lMHZV

3.0

MAXIMUM IDD vs FREQUENCY

FIGURE 5 -

/

:/

/
/
0.2

0.4
0.6
VOL IVOLTS)

0.8

1.0

iii
3:
n
FIGURE 10 -

~

\+--tTLTL----..j
External

~

TIMER RELATIONSHIPS

tTH

~

~

~

tTL

k-

FIGURE 11- POWER-ON RESET AND RESET

I
VDD

OSC1

**

1-----------------------------------~I
I

~ ~1z--.-z-r-r//-r-Z-r-r7l~Z~!I~71-r-/-r-T!I-r-7-r-r/l-r-7r-T"71-,--,/-r-/7,.-,77--r-7-r-rO-r-7r-r!l~/,......,O"""Tt/......,-0T777-,-Z7l0~7r-T07l7......,-0T70-,-7717Z~/r-r!l
Itoxov

~

1920 tcyc

1

"T .~ -1

w
cO
~

o

.p2*

,u-

'ev

e

Internal
Address
Bus*

Internal
Data
Bus*

RESET

* Internal

.. * OSC1

U1

C)
N

Timer)
( Pin 37

Clock

en
00
o

J- --

-

r_n

timing signal and bus information not available externally .
line is not meant to represent frequency. It is only used to represent time.

' { "

-¥

tRL-1
--

MC146805G2

FIGURE 12 -

STOP RECOVERY AND POWER-ON RESET

O~::"_~IIIIIIIIIII ~ 111_
~tcyc"

(EdgeSensitive
Only)

~I-

W

rna

-..1"--1_
~

or
RESET

.,.-

tilCH

1920 tcyc

...
...,..

~2*------------------------------------------------J
* Internal

timing signals not available externally.
the internal gating of the OSC1 input pin.

* * Represents

OSC1,OSC2
The MC146805G2 can be configured to accept either a
crystal input or an RC network to control the internal
oscillator. Additionally, the internal clocks can be derived by
either a divide-by-two or divide-by-four of the internal
oscillator output frequency (fosc). Both of these options are
mask selectable.

FUNCTIONAL PIN DESCRIPTION
VDD and VSS
Power is supplied to the MCU using these two pins. VOO
is power and VSS is ground.
IRQ (MASKABLE INTERRUPT REQUEST)
IRQ is mask option selectable with the choice of interrupt
sensitivity being both level-sensitive, and negative edgesensitive or negative edge-sensitive only. The MCU completes the current instruction before it responds to the request. If IRQ is low and the interrupt mask bit (I bit) in the
condition code register is clear, the MCU begins an interrupt
sequence at the end of the current instruction.
If the mask option is selected to include level sensitivity,
then the IRQ input requires an external resistor to VOO for
"wire-OR" operation. See INTERRUPTS for more detail.

RC - If the RC oscillator option is selected, then a resistor
is connected to the oscillator pins as shown in Figure 13(d).
The relationship between Rand fosc is shown in Figure 14.
CRYSTAL - The circuit shown in Figure 13(b) is recommended when using a crystal. The internal oscillator is
designed to interface with an AT-cut parallel resonant quartz
crystal resonator in the frequency range specified for fosc in
the electrical characteristics table. Using an external CMOS
oscillator is suggested when crystals outside the specified
ranges are to be used. The crystal and components should
be mounted as close as possible to the input pins to minimize
output distortion and start-up stabilization time. Crystal frequency limits are also affected by VOO. Refer to Control
Timing Characteristics for limits. See Table 1.

RESET
The RESET input is not required for start-up but can be
used to reset the MCU's internal state and provide an orderly
software start-up procedure. Refer to RESETS for a detailed
description.

EXTERNAL CLOCK - An external clock should be applied to the OSC1 input with the OSC2 input not connected,
as shown in Figure 13(C). An external clock should be used
with the crystal oscillator mask option only. The toxOV or
tilCH specifications do not apply when using an external
clock input.

TIMER
The TIMER input may be used as an external clock for the
on-chip timer. Refer to TIMER for additional information
about the timer circuitry.
NUM - NON-USER MODE
This pin is intended for use in self-check only. In user applications, connect this pin to ground through a 10 kO
resistor.

PAO-PA7
These eight I/O lines comprise PortA. The state of any pin
is software programmable. Refer to INPUT/OUTPUT PROGRAMMING for a description of I/O programming.

3-941

I

MC146805G2

FIGURE 13 - OSCILLATOR CONNECTIONS

RSMAX
Co
C1
COSCl
COSC2
Rp
Q

1 MHz
400

4 MHz

Units

75

0

5
0.008
15-40
15-30
10
30

7
0.012
15-30
15-25
10
40

pF
I'F
pF
pF

MO
K

(a) Cry'stal Parameters

:c

MC146805G2
OSC1

I

39

SC2

Rp

C
RS: f OSCl
1
~

38

OSC2

Co

38

o

-3-8------~IDrl

COSC11"

_______3_9

(c) Equivalent Crystal Circuit

(b) Crystal Oscillator Connections

Unconnected
External Clock

(d) RC Oscillator Connection

(e) External Clock Source Connections

FIGURE 14 - TYPICAL FREQUENCY vs RESISTANCE FOR RC OSCILLATOR OPTION ONLY

10

.......
I-

+4 O~/y
:::'''''t-

~-

-,.....""

~

r- t--.+o..

~
>-

t.>

~

0.5

a:

0.2

~

...

0

r-o;;:

'" ..... "

I-

~

0.1
0.05
0.02
0.01
10

20
RESISTANCE (kO)

3-942

50

100

200

500

1000

MC146805G2

ware programmable. Refer to INPUT/OUTPUT PROGRAMMING for a description of I/O programming.

PBO-PB7

These eight lines comprise Port B. The state of any pin is
software programmable. Refer to INPUT/OUTPUT PROGRAMMING for a description of I/O programming.

INPUT/OUTPUT PROGRAMMING

Any port pin may be software programmed as an input or
output by the state of the corresponding bit in the port data
direction register (DDR). A pin is configured as an output if
its corresponding DDR bit is set to a logic 1. A pin is configured as an input if its corresponding DDR bit is cleared to
a logic O. At reset, all DDRs are cleared, which configures all
port pins as inputs. A port pin configured as an output will
output the data in the corresponding bit of its port data
latch. Refer to Figure 15 and Table 2.

PCO-PC7

These eight lines comprise Port C. The state of any pin is
software programmable. Refer to INPUT/OUTPUT PROGRAMMING for a description of I/O programming.
PDO-PD7

These eight lines comprise Port D. PD4-PD7 also are
capable of driving LEDs directly. The state of any pin is soft-

FIGURE 15 -

TYPICAL PORT 1/0 CIRCUITRY

I
1/0
Pin

Internal
MCl46805G2

Connections

(a)

4

Typical Port
Data Direction
Register
Typical Port
Register

Pin

P-7

P-6

P-5

P-4

P-3

P-2

P-1

p-o

(b)

TABLE 2 -

1/0 PIN FUNCTIONS

R/W*
0
0

DDR
0
1

Data is written into the output data latch and output to the 1/0 pin.

1

0

The state of the 1/0 pin is read

1

The 1/0 pin is in an output mode. The output data latch is read.

1

* R/W

IS

1/0 Pin Function
The 1/0 pin is in input mode. Data is written into the output data latch.

an Internal signal

3-943

MC146805G2

SELF-CHECK
The MCl46805G2 self-check is performed using the circuit
in Figure 16. Self-check is initiated by connecting NUM and
TIMER pins to a logic 1 then executing a reset. After reset,
five subroutines are called that execute the following tests:
1/0 - Functionally exercise ports A, 8, C, D
RAM - Walking bit test
ROM - Exclusive OR with odd 1s parity result
Timer - Functionally exercise timer
Interrupts - Functionally exercise external and timer
interrupts
Self-check results are shown in Table 3. The following
subroutines are available to user programs and do not require any external hardware.

I

RAM SELF-CHECK SUBROUTINES
Returns with the Z bit clear if any error is detected; otherwise the Z bit is set.
The RAM test must be called with the stack pointer at

$OO7F. When run, the test checks every RAM cell except for
$OO7F and $OO7E which are assumed to contain the return
address.
A and X are modified. All RAM locations except the top 2
are modified. (Enter at location $1 F80')
ROM CHECKSUM SUBROUTINE
Returns with Z bit cleared if any error was found, otherwise Z = 1. X = 0 on return, and A is zero if the test passed.
RAM locations $0040-$0043 are overwritten. (Enter at location $1F98.)
TIMER TEST SUBROUTINE
Return with Z bit cleared if any error was found; otherwise

Z=l.
This routine runs a Simple test on the timer. In order to
work correctly as a user subroutine, the internal clock must
be the clocking source and interrupts must be disabled.
Also, on exit, the clock will be running and the interrupt
mask not set so the caller must protect himself from interrupts if necessary.

FIGURE 16 - SELF-CHECK CIRCUIT
~

REs'Ei'

I
I

1

40

VOO
TIMER 37
NUM 3
OSCl

10 kO

1

10kO

T

10MO
OSC2

~

- ..2

iA0
PA7

P07

PA6
P06

6 PA5

P05

7 PA4

..J!.

PD4

PA3

P03

~ PA2

P02

10 PAl

POl

11 PAO

POO

-

;E

PBO

.J1

PBl

PCl
PC2
PC3

15 PB3

.J§.

5V

~

T

38

4MHz

34

20

I

XTAL
Option
Shown

I

2

~
~

20

I
I

-

33
32
31
30

}

T~t

Status
Indica tion

29

peo ~

14 PB2

----....!1.

10KO

39

MC146805G2

0.1

25

~

PC5

~

PB5
PC6
PC7

19 PB7

26

PC4
PB4

18 PB6

(!L -

22
21

Vss

1

0

NOTE: The RC Oscillator Option may also be
used In thiS circuIt.

3-944

MC146805G2

TABLE 3 -

SELF-CHECK RESULTS

PD3

PD2

POl

PDO

Remarks

1

0

1

0

Bad I/O

1

0

1

1

Bad Timer

1

1

0

0

Bad RAM

1

1

0

1

8ad ROM

1

1

1

0

Bad Interrupt or Request Flag

Cycling

Good Part
Bad Part

All Others

FIGURE 17 -

Access
Via
Page 0
Direct
Addressing

[~ ;

255

I/O Ports
Timer
RAM
128 Bytes
Page 0 User ROM

$0000

0

$007F

$ooFF

$08AF
$08BO
80 Bytes
Self-Check ROM

2303
2304

$0000

Port B Data Register

$0001

Port C Data Register

$0002

Port 0 Data Register

$0003

Port A Data Direction Register

$0004

Port B Data Direction Register

$0005

6

Port C Data Direction Register

$0006

7

Port 0 Data Direction Register

$0007

8

Timer Data Register

$0008

Timer Control Register

$0009

4

1968 Bytes
User ROM

2223
2224

Port A Data Register

$0080
$0100

256

II

ADDRESS MAP

$08FF
$0900

10

$oooA
6 Bytes
Unused*

5760 Bytes
Unused*

8063
8064
8181
8182

User
Defined
Interrupt
Vectors

!

8191

118 Bytes
Self-Check ROM

15
16

$1 F7F
$lF80
$lFF5

$oooF
$0010
RAM
(112 Bytes)

63
64

-

$OO3F

".,7 $0040

------------Timer Interrupt From Wait State Only
FF6-$1 FF7
- - - -Timer
-- - - - - $1$1 FF8-$1
Interrupt
FF9

----

External Interrupt

$lFFA-$lFFB

SWI

$lFFC-$lFFD

Reset

$lFFE-$lFFF
.L
127

-------

* Reads of unused locations undefined.

3-945

/'

/

/
/
/
,/

,/ "., Stack (64 Bytes Max)
,/

,/
,/

-+

$OO7F

MC146805G2

A and X register contents are lost; this routine counts how
many times the clock counts in 128 cycles. The number of
counts should be a power of two since the prescaler is a
power of two. If not, the timer probably is not counting correctly. The routine also detects if the timer is running at all.
(Enter at location $1 FB5.l

The stack pointer is used to address data stored on the
stack. Data is stored on the stack during interrupts and
subroutine calls. At power-up, the stack pointer is set to
$OO7F and it is decremented as data is pushed on the stack.
When data is removed from the stack, the stack pointer is incremented. A maximum of 64 bytes of RAM is available for
stack usage. Since most programs use only a small part of
the allocated stack locations for interrupts and/ or subroutine
stacking purposes, the unused bytes are usable for program
data storage.

MEMORY

I

The MC146805G2 has a total address space of 8192 bytes
of memory and I/O registers. The address space is shown in
Figure 17.
The first 128 bytes of memory (first half of page zero) are
comprised of the I/O port locations, timer locations, and 112
bytes of RAM. The next 2096 bytes (including the 128 bytes
of the second half of page zero) comprise the user ROM. The
10 highest address bytes contain the reset and the interrupt
vectors.

FIGURE 18 -

REGISTERS
The MC146805G2 contains five registers, as shown in the
programming model in Figure 18. The interrupt stacking
order is shown in Figure 19.

PROGRAMMING MODEL

0

I

A

Accumulator

0

I

X

Index Register

87

12

Program Counter

PCl

PCH
12

6

0

I

SP

Stack Pointer

CC

l§
1

FIGURE 19 -

N

Z

C

condit. ion Code Register
Carry/Borrow
Zero
Negative
Interrupt Mask
Half Carry

STACKING ORDER
Stack

IncreaSing Memory
Addresses

1i
U
R
N

1

1 1 11

1

Condition Code Register
Accumulator
Index Register

o 10 10 1

PCH
PCl

Unstack

I

~1

DecreaSing Memory
Addresses

T

NOTE: Since the Stack Pointer decrements dUring pushes. the PCl IS
stacked first. followed by PCH, etc Pulling from the stack IS In
the reverse order

3. 946

MC146805G2

ACCUMULATOR (A)

RESETS

This accumulator is an 8-bit general purpose register used
to hold operands, results of the arithmetic calculations, and
data manipulations.

The MC146805G2 has two reset modes: an active low external reset pin (RESET) and a power-on reset function; refer
to Figure 11.

INDEX REGISTER (X)
The X register is an 8-bit register which is used during the
indexed modes of addressing. It provides an 8-bit value
which is used to create an effective address. The index
register is also used for data manipulations with the readmOdify-write type of instructions and as a temporary storage
register when not performing addressing operations.

RESET
The RESET input pin is used to reset the MCU to provide
an orderly software start-up procedure. When using the external reset mode, the RESET pin must stay low for a minimum of one tcyc. The RESET pin is provided with a Schmitt
Trigger input (internally) to improve its noise immunity.

PROGRAM COUNTER (PC)

POWER-ON RESET
The power-on reset occurs when a positive transition is
detected on VDD. The power-on reset is used strictly for
power turn-on conditions and should not be used to detect
any drops in the power supply voltage. There is no provision
for a power-down reset. The power-on circuitry provides for
a 1920 tcyc delay from the time that the oscillator becomes
active. If the external RESET pin is low at the end of the 1920
tcyc time out, the processor remains in the reset condition.
Either of the two types of reset conditions causes the
following to occur:
Timer control register interrupt request bit TCR7 is
cleared to a "0".
Timer control register interrupt mask bit TCR6 is set to
a "1".

The program counter is a 13-bit register that contains the
address of the next instruction to be executed by the processor.
STACK POINTER (SP)
The stack pointer is a 13-bit register containing the
address of the next free location on the stack. When accessing memory, the seven most significant bits are permanently
configured to CXXlOOO1. These seven bits are appended to the
six least significant register bits to produce an address within
the range of $OO7F to $0040. The stack area of RAM is used
to store the return address on subroutine calls and the
machine state during interrupts. During external or power-on
reset, and during a reset stack pointer (RSP) instruction, the
stack pointer is set to its upper limit ($007F). Nested interrupts and/or Subroutines may use up to 64 (decimal) locations, beyond which the stack pointer wraps around and
points to its upper limit thereby losing the previously stored
information. A subroutine call occupies two RAM bytes on
the stack, while an interrupt uses five RAM bytes.
CONDITION CODE REGISTER (CC)
The condition code register is a 5-bit register which
indicates the results of the instruction just executed. These
bits can be individually tested by a program and specific action taken as a result of their state. Each bit is explained in
the following paragraphs.
HALF CARRY BITS (H) - The H bit is set to a one when a
carry occurs between bits 3 and 4 of the ALU during an ADD
or ADC instruction. The H bit is useful in binary coded
decimal subroutines.
INTERRUPT MASK BIT (I) - When the I bit is set, both
the external interrupt and the timer interrupt are disabled.
Clearing this bit enables the above interrupts. If an interrupt
occurs while the I bit is set, the interrupt is latched and is
processed when the I bit is next cleared.
NEGATIVE (N) - When set, this bit indicates that the
result of the last arithmetic, logical, or data manipulation is
negative (bit 7 in the result is a logical 1).
ZERO (Z) - When set, this bit indicates that the result of
the last arithmetic, logical, or data manipulations is O.

All data direction register bits are cleared to logical
zeros. All ports are defined as inputs.
Stack pointer is preset to $OO7F.
The internal address bus is forced to the reset vector
($1FFE, $1FFF).
Condition code register interrupt mask bit (I) is set to a
"1".
STOP and WAIT latches are cleared.
External interrupt latch is cleared.
All other functions, such as other registers (including output ports), the timer, etc. are not cleared by the reset conditions.

INTERRUPTS
The MC146805G2 may be interrupted by one of three different methods: either one of two maskable hardware interrupts (external input or timer) or a nonmaskable software interrupt (SWI). Systems often require that normal processing
be interrupted so that some external event may be serviced.
Interrupts cause the processor registers to be saved on the
stack and the interrupt mask (I bit) set to prevent additional
interrupts. The RTI instruction causes the register contents
to be recovered from the stack followed by a return to normal processing. The stack order is shown in Figure 19.
Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered
pending until the current instruction execution is complete.
NOTE
The current instruction is considered to be the one
already fetched and being operated on.

CARRY /BORROW (C) - When set, this bit indicates that
a carry or borrow out of the arithmetic logic unit (ALU)
occurred during the last arithmetic operation. This bit is also
affected during bit test and branch instructions, shifts, and
rotates.

When the current instruction is complete, the processor
checks all pending hardware interrupts and if unmasked (I bit

3-947

II

MC146805G2

clear), proceeds with interrupt processing; otherwise, the
next instruction is fetched and executed. Note that masked
interrupts are latched for later interrupt service.
If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the same as any
other instruction and as such takes precedence over hardware interrupts only if the I bit is set (hardware interrupts
masked), Refer to Figure 20 for the interrupt and instruction
processing sequence.
Table 4 shows the execution priority of the RESET,
and timer interrupts, and the software interrupt SWI. Two
conditions are shown, one with the I bit set and the other

mo

FIGURE 20 -

with I bit clear; however, in either case RESET has the
highest priority of execution. If the I bit is set as per Table
4(a), the second highest priority is assigned to SWI. This is illustrated in Figure 20 which shows that the IRQ or Timer
interrupts are not executed when the I bit is set and the next
instruction (including SWIl is fetched. If the I bit is cleared as
per Table 4(b), the priorities change in that the next instruction (including SWIl is not fetched until after the IRQ and
Timer interrupts have been recognized (and serviced). Also,
when the I bit is clear, if. both IRQ and Timer interrupts are
pending, the fRO interrupt is always serviced before the
Timer interrupt.

RESET AND INTERRUPT PROCESSING FLOWCHART

I
1--1 (in CCl
007F-- SP
O--DDRs
CLR IRQ Logic
TCR b7--0
TCR b6--1

Clear
IRQ
Request
Latch

Stack
PC, X,A, CC

Timer
Put IFFE on
Address Bus

Load PC From:
SWI: lFFC/lFFD
IRQ: lFFA/1FFB
TIMER: lFFS/lFF9
Timer Wait: 1FF61 1FF7
Fetch
Instruction

SWI

Load PC
from
1FFE/1 FFF
Execute All
Instruction
Cycles

3-948

MC146805G2

TABLE 4 - INTERRUPT/INSTRUCTION EXECUTION
PRIORITY AND VECTOR ADDRESS
(a) I Bit Set
Priority
1

Interrupt/ Instruction
RESET
SWI

2

Vector
Address
$1 FFE-$1 FFF
$1 FFC-$1 FFD

NOTE: IRQ and Timer Interrupts are not executed when the I bit is
set; therefore, they are not shown.
(b) I Bit Clear
Interrupt/ Instruction
RESET

Priority

TIm
Timer

2
3

SWI

4

1

Vector
Address
$1 FFE-$1 FFF
$1 FFA-$1 FFB
$1 FF8-$1 FF9
$1 FF6-$1 FF7*
$1 FFC-$1 FFD

* The Timer vector address from the WAIT mode is $1 FF6-$1 FF7.

external interrupt occurs. The action of the external interrupt
is identical to the timer interrupt with the exception that the
service routine address is specified by the contents of $1 FFA
and $lFFB. Either a level- and edge-sensitive trigger (or
edge-sensitive only) are available as mask options. Figure 21
shows both a functional diagram and timing for the interrupt
line. The timing diagram shows two different treatments of
the interrupt line (IRQ) to the processor. The first method is
single pulses on the interrupt line spaced far enough apart to
be serviced. The minimum time between pulses is a function
of the length of the interrupt service routine. Once a pulse
occurs, the next pulse should not occur until the MPU software has exited the routine (an RTI occursl. This time (tILlL)
is obtained by adding 20 instruction cycles (tcyc) to the total
number of cycles it takes to complete the service routine including the RTI instruction; refer to Figure 21. The second
configuration shows many interrupt lines "wire-ORed" to
form the interrupts at the processor. Thus, if after servicing
an interrupt the IRQ remains low, then the next interrupt is
recognized.

NOTE
Processing is such that at the end of the current instruction execution, the I bit is tested and if set the
next instruction (including SWI) is fetched. If the I bit
is cleared, the hardware interrupt latches are tested,
and if no hardware interrupt is pending, the program
falls through and the next instruction is fetched.
TIMER INTERRUPT
If the timer interrupt mask bit (TCR6) is cleared, then each
time the timer decrements to zero (transitions from $01 to
$00) an interrupt request is generated. The actual processor
interrupt is generated only if the interrupt mask bit of the
condition code register is also cleared When the interrupt is
recognized, the current state of the machine is pushed onto
the stack and the interrupt mask bit in the condition code
register is set. This masks further interrupts until the present
one is serviced. The processor now vectors to the timer interrupt service routine. The address for this service routine is
specified by the contents of $1 FF8 and $1 FF9 unless the processor is in a WAIT mode in which case the contents of
$1 FF6 and $1 FF7 specify the timer service routine address.
Software must be used to clear the timer interrupt request
bit nCR7) At the end of the timer interrupt service routine,
the software normally executes an RTI instruction which
restores the machine state and starts executing the interrupted program.

SOFTWARE INTERRUPT (SWI)
The software interrupt is an executable instruction. The
action of the SWI instruction is similar to the hardware interrupts. The SWI is executed regardless of the state of the interrupt mask in the condition code register. The service
routine address is specified by the contents of memory locations $lFFC and $lFFD. See Figure 20 for interrupt and instruction processing flowchart.

EXTERNAL INTERRUPT
If the interrupt mask bit of the condition code register is
cleared and the external interrupt pin (IRQ) is low, then the

3-949

•

MC146805G2

FIGURE 21 -

EXTERNAL INTERRUPT

(a) Interrupt Functional Diagram

Level-Sensitive Trigger

-----Mask Option
VDD
D

External
Interrupt
Request

Q~---~

Interrupt Pin - - - - - - 1 1 " - - - - - < 0 0 C
Q

I Bit (CCRI

I

Power-On Reset
External Reset
External Interrupt
Being Serviced (Read of Vectorsl

(b) Interrupt Mode Diagram

U

IRQ~tILIH

I..

t ILlL

------4.--t!

Edge-Sensitive Trigger Condition
The minimum pulse width (tILiHI is one
tcyc. The period tlLlL should not be less
than the number of tcyc cycles it takes
to execute the interrupt service routine
plus 20 tcyc cycles.
Level-Sensitive Trigger Condition

IRQ

(MPUI~~______________________________- J

If after servicing an interrupt the fRO remains low, then the next interrupt is
recognized.
Normally used
with Wire-ORed
Connection

.

Interrupt
Request
(MPUI

3-950

MC146805G2

LOW-POWER MODES

WAIT
The WAIT instruction places the MC146805G2 in a low
power consumption mode, but the WAIT mode consumes
somewhat more power than the STOP mode. In the WAIT
mode, the internal clock is disabled from all internal circuitry
except the timer circuit; refer to Figure 23. Thus, all internal
processing is halted; however, the timer continues to count
normally.
During the WAIT mode, the I bit in the condition code
register is cleared to enable interrupts. All other registers,
memory, and I/O lines remain in their previous state. The
timer may be enabled to allow a periodic exit from the WAIT
mode. If an external and a timer interrupt occur at the same
time, the external interrupt is serviced first; then, if the timer
interrupt request is not cleared in the external interrupt
routine, the normal timer interrupt (not the timer wait interrupt) is serviced since the MCU is no longer in the WAIT
mode.

STOP
The STOP instruction places the MC146805G2 in its
lowest power consumption mode. In the STOP mode the internal oscillator is turned off, causing all internal processing
and the timer to be halted; refer to Figure 22.
DUring the STOP mode, timer control register (TCR) bits 6
and 7 are altered to remove any pending timer interrupt requests and to disable any further timer interrupts. The timer
prescaler is cleared. External interrupts are enabled in the
condition code register. All other registers and memory remain unaltered. All I/O lines remain unchanged.

FIGURE 22 -

STOP FUNCTION FLOWCHART

TIMER
The MCU timer contains an 8-bit software programmable
counter (timer data register) with a 7-bit software selectable
prescaler. Figure 24 contains a block diagram of the timer.
The counter may be loaded under program control and is
decremented towards zero by the clock input (prescaler output). When the counter decrements to zero, the timer interrupt request bit (i.e., bit 7 of the timer control register TCR)
is set. Then, if the timer interrupt is not masked (i.e., bit 6 of
the TCR and the I bit in the condition code register are both
cleared) the processor receives an interrupt. After completion of the current instruction, the processor proceeds to
store the appropriate registers on the stack, and then fetches
the timer vector address from locations $1 FF8 and $1 FF9 (or
$lFF6 and $lFF7 if in the WAIT mode) in order to begin
servicing.
The counter continues to count after it reaches zero,
allowing the software to determine the number of internal or
external input clocks since the timer interrupt request bit was
set. The counter may be read at any time by the processor
without disturbing the count. The contents of the counter
become stable prior to the read portion of a cycle, and do not
change during the read. The timer interrupt request bit
nCR7) remains set until cleared by the software. If the timer
interrupt request bit (TCR7) is cleared before the timer interrupt is serviced, the interrupt is lost. TCR7 may also be used
as a scanned status bit in a non-interrupt mode of operation
nCR6= 1).
The prescaler is a 7-bit divider which is used to extend the
maximum length of the timer. Bit 0, bit 1, and bit 2 of the
TCR are programmed to choose the appropriate prescaler
output which is used as the counter input. The processor
cannot write into or read from the prescaler; however, its
contents are cleared to all zeros by the write operation into
TCR when bit 3 of the written data equals a logic one. This
allows for truncation-free counting.
The timer input can be configured for three different
operating modes plus a disable mode, depending on the
value written to the TCR4 and TCR5 control register bits.
Refer to TIMER CONTROL REGISTER.

Stop Oscillator
And All Clocks
TCR Bit7-0
TCR Bit 6-1
Clear I Bit

Yes

3-951

II

MC146805G2

FIGURE 23 - WAIT FUNCTION FLOWCHART

Oscillator Active
Clear I Bit
Timer Clock Active
All Other Processor
Clocks Stop

I

Fetch External
Interrupt, Reset,
or Timer Interrupt
Vector (from WAIT
Mode Only)

TIMER INPUT MODE 1
If TCR4 and TCR5 are both programmed to a zero, the input to the timer is from an internal clock and the TIMER input pin is disabled. The internal clock mode can be used for
periodic interrupt generation, as well as a reference in frequency and event measurement. The internal clock is the instruction cycle clock. During a WAIT instruction, the internal
clock to the timer continues to run at its normal rate.
TIMER INPUT MODE 2
With TCR4= 1 and TCR5=O, the internal clock and the
TIMER input pin are ANDed to form the timer input signal.
This mode can be used to measure external pulse widths.
The external timer input pulse simply turns on the internal
clock for the duration of the pulse. The resolution of the
count in this mode is ± 1 clock; therefore, accuracy im-

proves with longer input pulse widths.
TIMER INPUT MODE 3
If TCR4=O and TCR5= 1, then all inputs to the timer are
disabled.
TIMER INPUT MODE 4
If TCR4= 1 and TCR5= 1, the internal clock input to the
timer is disabled and the TIMER input pin becomes the input
to the timer. The timer can, in this mode, be used to count
external events as well as external frequencies for generating
periodic interrupts. The counter is clocked on the falling
edge of the external signal.
Figure 24 shows a block diagram of the timer subsystem.
Power-on Reset and the STOP instruction cause the counter
to be set to $FO.

3-952

MC146805G2

FIGURE 24 - TIMER BLOCK DIAGRAM

External
Input

Disabled
(No Clock)
Write

Cleared by
TCR3
'~

Interrupt

Read

____________~~~____________- J /

Software Functions
NOTES:
1. Prescaler and timer data register (S-bit counter) are clocked on the falling edge of the internal clock or external input.
2. The timer data register counts down continuously.

TIMER CONTROL REGISTER (TCR)

TCR5 TCR4

o

~

76543210

o
1
1

All bits in this register except bit 3 are Read/Write bits.
TCR7 - Timer interrupt request bit: bit used to indicate
the timer interrupt when it is logic one.
1 - Set whenever the counter decrements to zero, or
under program control.
o - Cleared on external reset, power-on reset, STOP instruction, or program control.

Internal clock to timer

1 . AND of internal clock and TIMER pin
to timer
0
Inputs to timer disabled
1
TIMER pin to timer

TCR3 - Timer prescaler reset bit: writing a "1" to this bit
resets the prescaler to zero. A read of this location always indicates a "0". (U naffected by reset.)
TCR2, TCRl, TCRO - Prescaler select bits: decoded to
select one of eight outputs of the prescaler. (Unaffected by
reset.)

TCR6 - Timer interrupt mask bit: when this bit is a logic
one it inhibits the timer interrupt to the processor.
1 - Set on external reset, power-on reset, STOP instruction, or program control.
o - Cleared under program control.

TCR2

TCR5 - External or internal bit: selects the input clock
source to be either the external TIMER pin or the internal
clock. (Unaffected by reset.)
1 - Select external clock source.
o - Select internal clock source (period= t cyc ).

0

0

a

a
a
a

a

1

1
1
1
1

TCR4 - External enable bit: control bit used to enable the
external TIMER pin. (Unaffected by reset.)
1 - Enable external TIMER pin.
o - Disable external TIMER pin.

3-953

Prescaler
TCRl
TCRO

1
1
0

a
1

a

a

1

1
1

a
1

Result

+1
+2
+4
+8
+16
+32
+64
+ 128

I

MC146805G2

INSTRUCTION SET

ADDRESSING MODES

The MCU has a set of 61 basic instructions. They can be
divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type. All the instructions within a given type are presented in individual
tables.

These instructions read a memory location or a register,
modify or test its contents, and write the modified value
back to memory or to the register. The test for negative or
zero (TST) instruction is an exception to the read-modifywrite sequence since it does not modify the value. Refer to
Table 6.

The MCU uses ten different addressing modes to provide
the programmer with an opportunity to optimize the code to
all situations. The various indexed addressing modes make it
possible to locate data tables, code conversion tables, and
scaling tables anywhere in the memory space. Short indexed
accesses are single byte instructions, while the longest instructions (three bytes) permit tables throughout memory.
Short absolute (direct) and long absolute addressing are also
included. Table 11 shows the addressing modes for each instruction, with the effects each instruction has on the condition code register. An opcode map is shown in Table 10.
The term "Effective Address" (EA) is used in describing
the various addressing modes, and is defined as the byte
address to or from which the argument for an instruction is
fetched or stored. The ten addressing modes of the processor are described below. Parentheses are used to indicate
"contents of" the location or register referred to; e.g., (PC)
indicates the contents of the location pointed to by the PC.
An arrow indicates "is replaced by", and a colon indicates
concatenation of two bytes. For additional detailS and
graphical illustrations, refer to the M6805 Family User's
Manual.

BRANCH INSTRUCTIONS
Most branch instructions test the state of the condition
code register and if certain criteria are met, a branch is executed. This adds an offset between - 127 and + 128 to the
current program counter. Refer to Table 7.

INHERENT
In inherent instructions, all the information necessary to
execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, and
no other arguments, are included in this mode.

BIT MANIPULATION INSTRUCTIONS
The MCU is capable of setting or clearing any bit which
resides in the first 128 bytes of the memory space where all
port registers, port DDRs, timer, timer control, and on-chip
RAM reside. An additional feature allows the software to
test and branch on the state of any bit within the first 256
locations. The bit set, bit clear, and bit test and branch functions are all implemented with a single instruction. For the
test and branch instructions, the value of the bit tested is
also placed in the carry bit of the condition code register.
Refer to Table 8.

IMMEDIATE

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One
operand is either the accumulator or the index register. The
other operand is obtained from memory using one of the addreSSing modes. The operand for the jump unconditional
(JMP) and jump to subroutine (JSR) instructions is the program counter. Refer to Table 5.

II

READ-MODIFY-WRITE INSTRUCTIONS

In immediate addressing, the operand is contained in the
byte immediately following the opcode. Immediate addressing is used to access constants which do not change during
program execution (e.g., a constant used to initialize a loop
counter).
EA= PC+ 1; PC-PC+ 2
DIRECT
In the direct addressing mode, the effective address of the
argument is contained in a Single byte following the opcode
byte. Direct addressing allows the user to directly address
the lowest 256 bytes in memory with a single two byte instruction. This includes all on-chip RAM and I/O registers
and 128 bytes of on-chip ROM. Direct addressing is efficient
in both memory and time.
EA= (PC + 1); PC- PC+ 2
Address Bus High-a; Address Bus Low-(PC+ 1)

NOTE
The MCU is actually capable of operating on the bit set
and bit clear instructions anywhere in the first 256
bytes; however, since only ROM resides in the upper
128 bytes the bit set! clear instructions have no effect
on the upper 128 bytes.

EXTENDED

CONTROL INSTRUCTIONS
These instructions are register reference instructions and
are used to control processor operation during program execution. Refer to Table 9.

In the extended addressing mode, the effective address of
the argument is contained in the two bytes following the opcode. Instructions with extended addressing modes are
capable of referencing arguments anywhere in memory with
a single three-byte instruction. When using the Motorola
assembler, the user need not specify whether an instruction
uses direct or extended addressing. The assembler
automatically selects the most efficient address mode.
EA=(PC+ 1):(PC+2); PC-PC+3
Address Bus High-(PC+ 1); Address Bus Low-(PC+2)

OPCODE MAP
Table 10 is an opcode map for the instructions used on the
MCU.
ALPHABETICAL LISTING
The complete instruction set is given in alphabetical order
in Table 11.

3-954

MC146805G2

INDEXED, NO OFFSET
In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. Thus, this addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is used to move a pointer through a table or
to address a frequently referenced RAM or I/O location.
EA= X; PC--PC+ 1
Address Bus High--O; Address Bus Low--X
INDEXED, 8-BIT OFFSET
Here, the EA is obtained by adding the contents of the
byte following the opcode to that of the index register;
therefore, the operand is located anywhere within the lowest
511 memory locations. For example, this mode of addressing
is useful for selecting the m-th element in an n element table.
All instructions are two bytes. The contents of the index
register (X) is not changed. The contents of (PC + 1) is an
unsigned 8-bit integer. One byte offset indexing permits
look-up tables to be easily accessed in either RAM or ROM.
EA= X+ (PC+ 1); PC--PC+2)
Address Bus High--K; Address Bus Low--X+(PC+1)
Where: K = The carry from the addition of X + (PC + 1)
INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit
index register and the two unsigned bytes following the opcode. This addressing mode can be used in a manner similar
to indexed 8-bit offset, except that this three byte instruction
allows tables to be anywhere in memory (e. g., jump tables in
ROM). As with direct and extended, the M6805 assembler
determines the most efficient form of indexed offset; 8 or
16-bit. The content of the index register is not changed.
EA=X+[(PC+1):(PC+2)l; PC--PC+3
Address Bus High--(PC+ 1) + K;
Address Bus Low--X+ (PC+ 2)
Where: K = The carry from the addition of X + (PC + 2)
RELATIVE
Relative addressing is only used in branch instructions. In

relative addressing, the contents of the 8-bit Signed byte
following the opcode (the offset) is added to the pe; if and
only if the branch condition is true. Otherwise, control proceeds to the next instruction. The span of relative addressing
is limited to the range of -126 to + 129 bytes from the
branch instruction opcode location. The Motorola assembler
calculates the proper offset and checks to see if it is within
the span of the branch.
EA= PC+ 2+ (PC + 1); PC -- EA if branch taken;
otherwise, EA = PC -- PC + 2
BIT SET/CLEAR
Direct addressing and bit addressing are combined in instructions which set and clear individual memory and I/O
bits. In the bit set and clear instructions, the byte is specified
as a direct address in the location following the opcode. The
first 256 addressable locations are thus accessed. The bit to
be modified within that byte is specified within the first three
bits of the opcode. The bit set and clear instructions occupy
two bytes, one for the opcode (including the bit number) and
the other to address the byte which contains the bit of interest.
EA= (PC+ 1); PC-- PC+2
Address Bus High--O; Address Bus Low--(PC+ 1)
BIT TEST AND BRANCH
Bit test and branch is a combination of direct addressing,
bit set or bit clear addressing, and relative addressing. The
actual bit to be tested, within the byte, is specified within the
low order nibble of the opcode. The address of the data byte
to be tested is located via a direct address in the location immediately following the opcode byte (EA1). The Signed
relative 8-bit offset is in the third byte (EA2) and is added to
the PC if the specified bit is set or clear in the specified
memory location. This single three byte instruction allows
the program to branch based on the condition of any bit in
the first 256 locations of memory.
EA1 = (PC+ 1)
Address Bus High--O; Address Bus Low--(PC+ 1)
EA2 = PC + 3 + (PC + 2); PC -- EA2 if branch taken;
otherwise, PC -- PC + 3

3-955

I

TABLE 5 -

•

REGISTER/MEMORY INSTRUCTIONS

s:

.,.....n

Addressing Modes
Direct

Immediate

Function

c.v



Mnemonic

Op
Code

I

I

Bytes

Cycles

Op
Code

I

#

Bytes

Cycles

Indexed
(8-Bit Offset)

Indexed
(No Offset)

Extended
Op
Code

#

#

#

Cycles

Op
Code

#

Bytes

Bytes

Cycles

Indexed
(1S-Bit Offset)

Op
Code

#

#

Bytes

Cycles

Op
Code

,

,

Bytes

Cycles

Load A from Memory

LOA

A6

2

2

B6

2

3

C6

3

4

F6

1

3

E6

2

4

06

3

5

Load X from Memory

LOX

AE

2

2

BE

2

3

CE

3

4

FE

1

3

EE

2

4

DE

3

5

Store A in Memory

STA

-

B7

2

4

C7

3

5

F7

1

4

E7

2

5

07

3

6

STX

-

-

Store X in Memory

-

-

BF

2

4

CF

3

5

FF

1

4

EF

2

5

OF

3

6

Add Memory to A
Add Memory and
Carry to A

ADD

AB

2

2

BB

2

3

CB

3

4

FB

1

3

EB

2

4

DB

3

5

AOC

A9

2

2

B9

2

3

C9

3

4

F9

1

3

E9

2

4

09

3

5

Subtract Memory

SUB

AO

2

2

BO

2

3

CO

3

4

FO

1

3

EO

2

4

DO

3

5

Subtract Memory from
A with Borrow

SBC

A2

2

2

B2

2

3

C2

3

4

F2

1

3

E2

2

4

02

3

5

AND Memory to A

AND

A4

2

2

B4

2

3

C4

3

4

F4

1

3

E4

2

4

04

3

5

OR Memory with A

ORA

AA

2

2

BA

2

3

CA

3

4

FA

1

3

EA

2

4

OA

3

5

Exclusive OR Memory
with A

EOR

A8

2

2

B8

2

3

C8

3

4

F8

1

3

E8

2

4

08

3

5

Arithmetic Compare A
with Memory

CMP

A1

2

2

B1

2

3

C1

3

4

F1

1

3

E1

2

4

01

3

5

Arithmetic Compare X
with Memory

CPX

A3

2

2

B3

2

3

C3

3

4

F3

1

3

E3

2

4

03

3

5

1

3

E5

2

4

05

3

5

1

2

EC

2

3

DC

3

4

1

5

ED

2_

6

DO

3

7

Bit Test Memory with
A (Logical Compare)

A5

2

2

B5

2

3

C5

3

4

F5

Jump Unconditional

JMP

-

-

-

BC

2

2

CC

3

3

FC

Jump to Subroutine

JSR

-

-

~

_2_

__
5_

CD

2

~

FD

BIT

-

-

TABLE 6 -

-

READ-MODIFY-WRITE INSTRUCTIONS
Addressing Modes

Inherent (A)

Function

Mnemonic

Inherent (X)

#

Op
Code

Bytes

#
Cycles

Op
Code

Bytes

#

Indexed
(No Offset)

Direct

#
Cycles

Indexed
(8-Bit Offset)

Op
Code

#

#

#

Cycles

Op
Code

#

Bytes

Bytes

Cycles

Op
Code

#

#

Bytes

Cycles
6

Increment

INC

4C

1

3

5C

1

3

3C

2

5

7C

1

5

6C

2

Decrement

DEC

4A

1

3

5A

1

3

3A

2

5

7A

1

5

6A

2

6

Clear

CLR

4F

1

3

5F

1

3

3F

5

7F

1

5

6F

2

6

5

73

1

5

63

2

6

5

70

1

5

60

2

6

1

Complement

COM

43

1

3

53

1

3

33

2
2

Negate
(2'5 Complementl

NEG

40

1

3

50

1

3

30

2

Rotate Left Thru Carry

ROL

49

1

3

59

1

3

39

2

5

79

5

69

2

6

Rotate Right Thru
Carry

ROR

46

1

3

56

1

3

36

2

5

76

1

5

66

2

6

Logical Shift Left

LSL

1

3

58

1

3

38

2

5

78

1

5

68

2

6

Logical Shift Right

LSR

48
44

1

3

54

1

3

34

2

5

74

1

5

64

2

6

Anthmetic Shift Right

ASR

47

1

3

57

1

3

37

2

5

17

1

5

67

2

6

T est for Negative
or Zero

TST

40

1

3

50

1

3

3D

2

4

7D

1

4

60

2

5

CD
CO

o

UI

Cl

N

I

-

MC146805G2

TABLE 7 -

BRANCH INSTRUCTIONS
Relative Addressing Mode
Mnemonic

Op
Code

#

#

Bytes

Cycles

Branch Always

BRA

20

2

Branch Never

BRN

21

2

3
3

Branch IFF Higher

BHI

22

2

3

Branch IFF Lower or Same

BLS

23

2

3

BCC
(BHS)

24

2

3

24

2

3

BCS
(BLO)

25

2

25

2

3
3

Branch IFF Not Equal

BNE

26

2

3

Branch IFF Equal

BEQ

27

2

3

Branch IFF Half Carry Clear

BHCC

28

2

3

Branch IFF Half Carry Set

BHCS

29

2

3

BPL

2A

2

3

Function

Branch IFF Carry Clear
(Branch IFF Higher or Samel
Branch IFF Carry Set
(Branch IFF Lower)

Branch IFF Plus
Branch IFF Minus

BMI

2B

2

3

Branch IFF Interrupt Mask Bit is Clear

BMC

2C

2

3

Branch IFF Interrupt Mask Bit is Set

BMS

20

2

3

Branch IFF Interrupt Line is Low

BIL

2E

2

Branch IFF Interrupt Line is High

BIH

2F

2

3
3

Branch to Subroutine

BSR

AD

2

6

TABLE 8 -

I

BIT MANIPULATION INSTRUCTIONS
Addressing Modes
Bit Test and Branch

Bit Setl Clear
Mnemonic

Function

Op
Code

Branch IFF Bit n is Set

BRSET n (n=O. .7)

Branch IFF Bit n is Clear

BRCLR n (n=O

71

Set Bit n

BSET n (n=O .. 7)

Clear Bit n

BCLR n (n=O .. 71

#

#

Bytes

Cycles

10+2-n
11 + 2-n

TABLE 9 -

Op
Code

-

-

2-n

-

-

01 + 2-n

2

5

2

5

-

#

#

Bytes

Cycles

3
3
-

5

CONTROL INSTRUCTIONS
Inherent

Function

Mnemonic

Op
Code

#

#

Bytes

Cycles
2

Transfer A to X

TAX

97

1

Transfer X to A

TXA

9F

1

2

Set Carry Bit

SEC

1

2

Clear Carry Bit

CLC

99
98

1

2

Set Interrupt Mask Bit

SEI

9B

1

2

Clear Interrupt Mask Bit

CLI

9A

1

2

Software Interrupt

SWI

83

1

10

Return from Subroutine

RTS

81

1

6

Return from Interrupt

RTI

80

1

9

Reset Stack Pointer

RSP

9C

1

2

No-Operation

NOP

1

2

1

2

1

2

Stop

STOP

90
8E

Wait

WAIT

8F

3-957

5
-

..
3:

TABLE 10 -

o

M146805 CMOS FAMILY INSTRUCTION SET OPCODE MAP

~

~

Bit Manipulation
BTB
Bsc

~

rJk

~

DIR

INH

rllO

J"

01~

~,
5

5

13BASE~~B lBSE~~c
BRCLAO
3
eTe

2

BASET1
eTe
3

2

BCLRO
esc

2

BSE~1c

5

2

5

5

1

5

BCL~~c

3
0011

BACLA1
3
eTB

4
0100

BASE
3
UB

~BSE~~c

5

5

5
0101

BACL
3
:le

6
0110

BRSE
3

5

1

5

5

1
0001
0010

Branch
REL

2

1

5

~BCL~

2
1

5

Ji:

5

7
0111

BRCLR3
3
BTB

2

1000

3BASET4
BTB

9

1001

BACLA4
3
BTe

A
1010

BASET5
3
BTB

B

BRCLA5
3
BTB

5

VJ

5

cO
(J1

2

lOll

3

5

2 BHCC
REI
3
BHCS
2
R

5

2 BSE~~c

5

2

BCLA5
BSC
5

C
1100
D
1101

3BASET6"
eTB

BSET6
2
Bse

5

5

3BACL:T6B

2 BCL~~e

5

5

E
1110

l'ASE~IB

2 BSE~~c

F

5

5

BACLR7
~
BTe

_1111

2

5

BSE~1e

2 BCL~1e

5

(Xl

2

5

2 BCL~le

5

8

BSE~lc

BAA 3
REl
3
BAN
REL
3
BHlfliJ
3
BLS
rn
3
BCC
RFI
3
BCS
rn
3
BNE
REI
3
BEQ
R

2

BCL~~c

2

BM~EI

I

3
NEG
INH

3
NEG
1
INH

BIL

3

5

2

CO~R

5

LSA
DTR
2

COMA
INH
3
LSAA
INH
1
1

5

3
ROAA
INH

3
COM X
INH
3
LSAX
INri
1
1

7

IXI

1

NEG

IX

INH

AOR
DIR
5

3

3

2

ASA
DIR

ASAA
INH
3
LSLA
INH
1
3
AOLA
1
INH

ASAX
INH
3
LSLX
1
INH
3
AOLX
1
INH
3
OECX
1
INH

5

2

LSL

DIR
5

AOL
2

DIR

2

OEC
DIR

1
1

5

3

1

DECA
INH

1

2

1

COM
IXI

1

COM

6

LSA
2

IXI

IXI

1

IXI

ROR

2

ASA

IXI

2

1

DEC

IXI

INH

IX

IX
2
TAX
INH
2
CLC
N
2
SEC
1
INH
2
CLI
1
INH

IX
IX

1

IX
5

DEC

IXI

IX

SEI

1

1

INC
2
2 TST

5

3

3

DIR

INCA
INH
1

INCX
INH
1
3
TSTX
1
INH

3
4

DIR

TSTA
1
INH

5

6

INC
2

IXI

1

INC

5

TST
2

IX1

IX
4

1

TST

IX

CLA
2

5

3

3

DIR

CLAA
INH

CLAX
INH
1

1

6

CLA
2

IXI

5

1

CLA

IX

2
STOP
1
INH
2
WAIT
1
INH

INH
2
ASP
1
INH
2
NOP
1
INH

2
2

STA
DIR

2
2
2
2
2
2

2
EOA
IMM
2
2
AOC
2
IMM

A
X

IMM
DIR
EXT
REL
BSC
BTB
IX
IXl
IX2

Inherent
Accumulator
Index Register
Immediate
Direct
Extended
Relative
Bit Setl Clear
Bit Test and Branch
Indexed INo Offset)
Indexed, 1 Byte IS-Bit) Offset
Indexed,2 Byte 116-Bitl Offset

SUB"
3
IX2

4

3

CMP
EXT

3

SBC
EXT
CPX
EXT

OAA 2
IMM
2
ADD
IMM
2
2

6

BSA
2
REL
2
LOX
IMM
2

2
TXA
1
INH

IX2

2

IXI

2

CMP
IXI

4

IX2

CPX
3

IX2

SBC

IXI

2

CPX

IXI

ANO

IXI

2

BIT

3

EXT

3

LOA
EXT

3

3

STA "
EXT

3

1

4

IX2
IX2

STA

IXI

OIR
3
AOC
2
OIR
2

OAA 3
OIR

ADD 3
OIR
2
JMP
2
OIR
2

EOR
3

IXI

IX2

3

IX2

2

ORA"
IX2

2

3

ADD"
IX2

2

4

4

JMP
3

IX2

JSR 6
3
EXT

LOX 3
OIR
2

LOX
3
EXT

LOX'
IX2
3

STX '
EXT
3

STX

4

ADC

IX2

4

JMP 3
IXI
2

3

IX2

Ii

IXI

2

4

LOX
2

IXI

ADC
OAA

I

4

IXI

STX
2

IXI

IX
3
IX
3
IX
IX
3
IX
3

cJ"
4
0100

01~1
6
0110

ADD
JMP
1

8

1000

9

1001

j

A
1010

j

IX

I

7
0111

IX
IX

1

IX

JSA '
I
IX
3
LDX
1
IX

B
lOll
C
1100
D
1101

E
1110

4

5

6

STX
OIR
2

I

4

IXI
ADD

JSA
3

IXI

ORA

JSA

JSA 5
2
OIR

1

EOA

4

3

ADD
EXT
3
JMP
3
EXT

IXI

2

2

0010

4

1

4

OAA 4
EXT

3

LOA
STA

IXI
EOR

AOC
EXT
3
3

AOC

I

5

2

5

4

1

4

LOA
2

5

4

EOR
EXT
3

ANO
1

STA
IX2

IX
3

I

BIT

2

j

en

C)
N

~

j

IX
CPX

BIT
5

LOA

SBC
I

4

5

4

BIT

1
0001

4

5

IX2

~

SUB 3
IX
1
3
CMP
IX
1

4

ANO
3

II"

4

2

5

4

3

2

4

5

SBC
3

4

ANO
EXT
3

F

SUB

5

CMP
3

4

3

IX

6

EOA

Abbreviations for Addrea Modes
INH

SUB 4
3
EXT

4

1

5

AOL

6

2

SWI

5

LSL

6

AOL

1

5

1

6

LSL

IX

5

1

6

ASA
2

10

5

LSA

6

AOA

ATS
INH

5

REL

BIH REL

1

SUB j
DIR
3
CMP
DIR
3
SBC
DIR
3
CPX
DIR
3
ANO
DIR
3
BIT
DIR
3
LOA
DIR

IX1
E
lIla

"01

lOll

2
SUB
12
lMM
2
CMP
IMM
2
2
SBC
IMM
2
2
CPX
IMM
2
2
ANO
IMM
2
2
BIT
2
IMM
2
LOA
IMM
2

1X2
D

EXT
C
1100

B

A

lOla

9

ATI

DIR

IMM

INH
9
1001

5

6

6

3
AORX
INH

2

3

12

2

NEG

INH
8
1000

IX
0111

6

3
2

01~0

1

3

BPL
REI
3
BMI
REL
2
3
BMC
REL
2
3
2

5

NEG
2
:DlR

5

alaI

en
o
00

~ster/Memory

Control

Read/Modify/Write
IX1
INH

I

STX

IX

F

1111

I

LEGEND

...

MnemoniC
Bytes

~.
1

Cycles - - - - - - - '

~

I

:> Opcode in Hexadecimal

1

J~Xb

~

Opcode in Binary

CXXXJ :::e-:

' - - - - - - - - - Address Mode

MC146805G2

TABLE 11 - INSTRUCTION SET
Condition Codes

Addressing Modes
Mnemonic

Inherent

ADC
ADD
AND
ASl
ASA
BCC
BClA
BCS
BED
BHCC
BHCS
BHI
BHS
BIH
Bil
BIT
BlO
BlS
BMC
BMI
BMS
BNE
BPl
BAA
BAN
BAClA
BASET
BSET
BSA
ClC
CLI
ClA
CMP
COM
CPX
DEC
EOA
INC
JMP
JSA
lOA
lOX
lSl
lSA
NEG
Nap
OAA
AOl
AOA
ASP
ATI
ATS
SBC
SEC
SEI
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT

Immediate

Direct

Extended

x

X
X
X
X
X

X
X
X

X
X
X
X

Relative

Indexed
(No Offset)

Indexed
(8 Bits)

Indexed
(16 Bits)

X
X
X
X
X

X
X
X
X
X

X
X
X

Bit
Set/
Clear

Bit
Test &
Branch

H I N Z C
II
h

,.

X
X
X
X
X
X
X
X
X

X

X

II

Ih

,h

II
II
II

II
II
II

II

II

II

••
••
•
••
•
•• ••

X

X

II

h

••
•••
•••

X

X

II

X

•
A.

I

X
X
X
X
X
X
X
X
X
X
X

II

•

X
X

•
••
a

X
X
X

a

X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X

X
X
X

X

X
X
X
X
X
X
X

•••
•
••
•••
•
••
• •
••
•
••
••
•
•0
••
••
••
•

X
X
X

X

X

X

X

X

X

X

X

X

X

X

X
X

X

X

X

X

•

?

X
X
X

?

1

x
x
X
X
X
X
X

x

x

x

x

1

X

X

X

a

Condition Code Symbols
H
I
N

Half Carry IFrom Bit 31
Interrupt Mask
Negative ISlgn Bltl

Z

Zero

C

Carry/Borrow

II
•
)

o

Test and Set If True Cleared OtherWise
Not Affected
load CC Aeglster From Stack
Cleared
Set

3-959

II
II
II
II
II
II

1
II
II
II
II
II
II

II
II
II
a

II
II
II
II

a

II
1
II

••
•
•• •• ••
•
h

•
II
II
II

II
II
II

II
II

• • ••
•••
•••
•• •• ••
• • ••
•• •• •
•
•• •• ••
II

II

h

II
?

!

?

II

II

II
1

II

II

II
II

II
II

II

I.

II

II

MC146805G2

ORDERING INFORMATION
The following information is required when ordering a
custom MCU. This information may be transmitted to
Motorola in the following media:
EPROM(sl MCM2716s or MCM2532s
MDOS disk file
To initiate a ROM pattern for the MCU, it is necessary to
first contact your local field service office, local sales person,
or your local Motorola representative.
EPROMs

I

The MCM2716 or MCM2532 type EPROMs, programmed
with the customer program (positive logic sense for address
and datal, may be submitted for pattern generation. The
EPROMs must be clearly marked to indicate which EPROM
corresponds to which address space. Figure A-1 illustrates
the recommended marking procedure for two MCM2716
EPROMs.
After the EPROM(sl are marked, they should be placed in
conductive IC carriers and securely packed. Do not use
styrofoam.
FIGURE A-l -

EPROM MARKING

0080

0800

xxx = Customer 10
VERIFICATION MEDIA
All original pattern media (EPROMs or floppy diskl are filed for contractual purposes and are not returned. A computer listing of the ROM code will be generated and returned

·3-960

along with a listing verification form. The listing should be
thoroughly checked and the verification form completed,
signed, and returned to Motorola. The Signed verification
form constitutes the contractual agreement for creation of
the customer mask. If desired, Motorola will program a blank
2716 EPROM (supplied by the customer) from the data file
used to create the custom mask to aid in the verification process.
ROM VERIFICATION UNITS

The MCUs containing the customer's ROM pattern will be
sent for program verification. These units will have been
made using the custom mask but are for the purpose of
ROM verification only. For expediency they are usually unmarked, packaged in ceramic, and tested only at room
temperature and 5 volts. These RVUs are included in the
mask charge and are not production parts. These RVUs are
not backed nor guaranteed by Motorola Quality Assurance.
FLEXIBLE DI.SKS

The disk media submitted must be single-sided, singledensity, 8-inch, MDOS compatible floppies. The customer
must write the binary file name and company name on the
disk with a felt-tip ren. The floppies are not to be returned by
Motorola as they are used for archival storage. The minimum
MDOS system files as well as the absolute binary object file
(filename. LO type of file) from the M6805 cross assembler
must be on the disk. An object file made from a memory
dump using the ROLLOUT command is also admissable.
Consider submitting a source listing as well as the following
files: filename. LX (EXORciser loadable format) and
filename.SA (ASCII Source Codel. These files will of course
be kept confidential and are used 1) to speed up the process
in house if any problems arise, and 2) to speed up our
customer to factory interface if a user finds any software errors and needs assistance quickly from the factory representatives.
MDOS is Motorola's Disk Operating System avai!able on
development systems such as EXORciser, EXORset, etc.

MC146805G2

Option List
Select the options for your MCU from the following list. A manufacturing mask will be generated from this information. Select
one in each section.
Internal Oscillator Input
Crystal
Resistor

o
o

Internal Divide
+4
+2

o
o

Interrupt Trigger
Edge-Sensitive Only
o Level-Sensitive and Edge-Sensitive

o

Customer Name ________________________________________________________________________________
Address ______________________________________________________________________________________
City _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___ State ________________ Zip __________
Phone (________ _________________________ Extension _________________________________________
Contact Ms/Mr _________________________________________________________________________________
Customer Part Number ____________________________________________________________________________

Pattern Media
2708 EPROM
2716 EPROM
MDOS Disk File
Silent 700 Cassette
Card Deck
T ape of Card Deck
(Note 2) ___________________________________________________________

Notes: (2) Other media require prior factory approval.

Signature _____________________________________________________________________________________
Title ________________________________________________________________________________________

Silent 700 Cassette is a trademark of Texas Instruments Incorporated

3-961

I

®

MOTOROLA

MC14680SH2

Advance Information

CMOS
(HIGH-PERFORMANCE SILICON-GATEI

8-BIT
MICROCOMPUTER
8-BIT MICROCOMPUTER UNIT

I

The MC146805H2 Microcomputer Unit (MCU) belongs to the
M146805 CMOS Family of low-cost, single-chip microcomputers. This
8-bit MCU contains an on-chip oscillator, CPU, RAM, 1/0, and a timer.
The fully static design allows operation at two software selectable frequencies, further reducing its already low power consumption. It is a
low-power processor designed for low-end to mid-range applications in
the consumer, automotive, industrial, and communications market
where very low power consumption constitutes an important factor.
The following are the major features of the MC146805H2 MCU.

::%L~
~ijWUUUU"O CE""LM~~::~AGE
CASE 715

o

glW:WN

~1'1'i1li'{j
' Ip

S SUFFIX
CERDIP PACKAGE
CASE 734

HARDWARE FEATURES

• Typical Full Speed Operating Power of 20 mW at 5 V
•
•
•
•
•
•
•
•

Typical WAIT Mode Power of 4 mW
Typical STOP Mode Power of 5 /LW
8-Bit Architecture
Fully Static Operation
112 Bytes of On-Chip RAM
2048 Bytes on On-Chip ROM
24 Bidirectional 1/0 Lines Plus Four Input-Only Lines
Internal 8-Bit Timer with Software Programmable 7-Bit Prescaler

•
•
•
•
•

Watchdog Timer
External Timer Input
External and Timer Interrupts
Self-Check Mode
Master Reset and Power-On Reset

•
•
•
•
•
•

Single 3- to 6-Volt Supply
On-Chip Oscillator
4O-Pin Dual-in-Line Package
Chip Carrier Also Available
Alert Tone Generator
Frequency Synthesizer

,PLASTIC

PACKAGE
CASE 711

Z SUFFIX
CHIP' CARRIER
CASE 761

PIN ASSIGNMENT
VDD

SOFTWARE FEATURES

•
•
•
•
•

P SUFFIX

:
~

Similar to the MC6800
Efficient Use of Program Space
Versatile Interrupt Handling
True Bit Manipulation
Addressing Modes with Indexed Addressing for Tables

• Efficient Instruction Set
• Memory Mapped 1/0
• Most Self-Check Routines User Callable

(3)

OSCl

(41

OSC2

(51

TIMER

(61

Synth VSS

(71

XFC

(8)

CO

(91

PD7

(101

PD6

PAl

PD5

PAO

PD4

PBO

PD3

PBl

PD2

PB2

PDl

PB3

PD~

PB4

ALRT

PB5

PC4

PB6

PC5

PB7

PC6

VSS
Pin numbers in parentheses represent equivalent Z
suffix chip carrier pins.
This document contains information on a new product. Specifications and information herein
are subject to change without notice

3-962

MC146805H2

FIGURE 1 -

TIMER 37
~

---

I

Prescaler
7

Timer!
8 Counter

38

Timer Control Register

BLOCK DIAGRAM

OSC1

OSC2

t

39

~

I

Oscillator

I

~

.---

STOP

Q)

I

(f)

-6>
Q)
a:

~

-.

~

1

Synthesizer

r

I

1

~

1

-I

0

Transition
Circuit

u

I

i

Alert
Tone
Generator

~

11

Port
A
1/0

Ines

PA2~
PA3~

PA4~

PA5~
PA6~

Accumulator
8
A
Port
A
Reg

Data
Dir I---<
Reg

art
B
10

Ines

PBO~
PB1~

PB2~

PB3~
PB4~
PB5~
PB6~

8

Index
Register

6
Port
B
Reg

Data
Dlr H
Reg

PB7~

CPU
Control

IRQ

AlRT

r---

5

S
Program
Counter
High PCH

8

Program
Counter
low PCl

24

Port~
C ~

~~

PC4 Port
PC5
C
PC6 Input
PC7 lines

CPU

~P DO
AlU

112 x 8
RAM

256x8
ROM

3-963

~

Data
Dir
Reg

Port

0
Reg

~P ~;
~P
~PD

~

Port
D
1/0

~PD 5 lines

~PD
~PD6

~PD 7

1

2048x8
ROM
See Pin Assignment diagram for equivalent chip carrier pin numbers_

..--

Stack
POinter

T
N aTE:

NUM

Watchdog
Timer

X

Condition
Code
5 Register CC

PA7~

p..

RESET

IT r-Y

~

34

PAO~
PA1~

3
2

(/)

CO

1

-'-..I

I

MC146805H2

MAXIMUM RATINGS (Voltages Referenced to Vss)
Ratings

Symbol

Supply Voltage
All Input Voltages Except OSCl
Current Orain Per Pin Excluding VOO and VSS
Operating Temperature Range
Storage Temperature Range

Value

Unit

VOO

-0.3 to +8.0

V

Yin

VSS - 0.5 to VOO + 0.5

V

I

10

mA

TA

o to 70

°C

Tstg

-55 to + 150

°C

THERMAL CHARACTERISTICS
Characteristics
Thermal Resistance
Plastic
Cerdip
Ceramic
Chip Carrier

I

Symbol

Value

Unit

This device contains circuitry to protect the
inputs against damage due to high static
voltages of electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high impedance circuit. For proper operation it is
recommended that Yin and V out be constrained to the range VSSS(Vin or
Vout) s VOO. Reliability of operation is
enhanced if unused inputs are connected to
an appropriate logic voltage level (e.g., either
VSS or VOOl.

100

60

(JJA

°C/W

50
TBO

DC ELECTRICAL CHARACTERISTICS (VOO=5.0 Vdc +
- 10%, VSS=O Vdc, TA=O°C to 70°C unless otherwise noted)
Characteristic
Output Voltage, ILoads 10.0 p.A
Output High Voltage
Alert Tone Generator (iLoad= -:2 mAl
CO (ILoad= -4 mAl
PAO-PA7, POO-P07 (ILoad= -2 mAl
PBD-PB7 (ILoad= -100 p.A)

Symbol

Min

Max

Unit

VOL
VOH

....:

0.1

VOO-O.l

-

V
V

2.4
2.4
2.4
2.4

-

-

0.4
0.4
0.4

VOH

Output Low Voltage
Alert Tone Gen.erator (iLoad=900 p.A)
CO (iLoad=800.p.A)
PAO-PA7, PBO-PB7, POO-P07 (I Load= 800 p.A)

VOL

-

Input High Voltage
PAO-PA7, PBO-PB7, PC4-PC7, POO-P07
TIMER, IRQ, RESET
OSCl

VIH

Input Low Voltage All Inputs
Total Supply Current (CL = 50 pF on Ports, no dc Loads, tcyc= lp.s)
RUN (VIL =0.2 V, VIH=VOO-0.2 V)
WAIT
STOP

VOO-2.0
VOO-0.8
VOO-0.8

-

V

-

V

-

-

V

-

VIL

-

0.8

V

-

100

-

mA
mA
p.A

-

TBO
TBO
TBO

1/0 Port Input Leakage

IlL

-

±1O

p.A

Input Curent
RESET, iRQ, TIMER, OSCl

lin

-

±,

p.A

Capacitance
Ports
RESET, iRQ, TIMER, OSCl

Cout
Cin

-

12
8

pF
pF

-

TBO=To be determined.
NOTE:
Test conditions for 100 are as follows:
All ports programmed as inputs
VIL = 0.2 V (PAO-PA7, P60-PB7, PC4-PC7, POO-P07)
VIH=VOO-0.2 V for RESET, IRQ, and TIMER
OSC1 input as a squarewave from 0.2 V to VOO - 0.2 V
OSC2 output load = 20 pF (WAIT 100 is affected linearly by the OSC2 capacitance. STOP 100 is also affected linearly by this capacitance if
the oscillator is not killed.!

3-964

MC146805H2

DC ELECTRICAL CHARACTERISTICS (VOO=3.0 Vdc, VSS=O Vdc, TA=O°C to 70°C unless otherwise noted)
Characteristic
Output Voltage, ILoad::510.0 p.A
Output High Voltage
Alert Tone Generator IILoad= -0.5 mAl
CO IILoad= -1.0 mAl
PAO-PA7, POO-P07 IILoad= -0.5 mAl
PBO-PB7I1Load= -50 p.A)
Output Low Voltage
Alert Tone Generator IILoad=900 p.A)
CO II Load = 800 p.A)
PAO-PA7, PBO-PB7, POO-P07 II Load = 800 p.A)

Symbol

Min

Max

Unit

VOL
VOH

VOO-O.l

0.1

V
V

VOH

1.4
1.4
1.4
1.4
-

-

VOL

-

Input High Voltage
PAO-PA7, PBO-PB7, PC4-PC7, POO-P07
TIMER, iRQ, RESET
OSCl

VIH

Input Low Voltage All Inputs
Total Supply Cur"rent (CL =50 pF on Ports no dc Loads, tcyc=5 p.s)
RUN (VIL =0.2 V, VIH=VOO-0.2 V)
WAIT
STOP

VOO-0.3
VOO-03
VOO-0.3

-

V

-

-

0.3
0.3
0.3

V

V

-

VIL

-

0.3

V

100

-

TBO
TBO
TBO

mA
mA
p.A

I/O Ports Input Leakage Current

IlL

-

±10

p.A

Input Current
RESET, IRO, TIMER, OSCl

lin

-

±1

p.A

Capacitance
Ports
RESET, IRO, TIMER, OSCl

Cout
Cin

-

12

-

8

pF
pF

Max

Unit

TBO=To be determined.
NOTE:
Test conditions for 100 are as follows:
All ports programmed as inputs
VIL =0.2 V (PAO-PA7, PBO-PB7, PC4-PC7, POO-P07)
VIH=VOO-0.2 V for RESET, IRO, and TIMER
OSCl input is a squarewave from 0.2 V to VOO - 0.2 V
OSC2 output load=20 pF (WAIT and STOP 100 are affected linearly by the OSC2 capacitance.)

TABLE 1 - CONTROL TIMING
(VOO=50Vdc±1O% VSS=OVdc TA=0°Ct070°C)
Symbol

Characteristic

Min

Crystal Oscillator Startup Time (See Figure 5)

tOXOV

-

TBO

ms

Stop Recovery Startup Time (Crystal Oscillator) (See Figure 6)

tlLCH

-

TBO

ms

Timer Pulse Width (See Figure 4)

tTH, tTL

0.5

-

tcyc

RESET Pulse Width (See Figure 5)

tRL

1.5

-

tcyc

Timer Period (See Figure 4)

tTLTL

1.0

-

tcyc

Interrupt Pulse Width Low (See Figure 15)

tlLlH

1.0

-

tcyc

Interrupt Pulse Period (See Figure lb)

tlLlL

*

-

tOH, tOl

TBO

-

tcyc
ns

tcyc

1000

-

ns

fosc
fsynth

30
0.5

OSCl Pulse Width
Cycle Time
Frequency of Operation
Crystal
Synthesizer

50
2.0

kHz
MHz

*The minimum period tlLlL should not be less than the number of tcyc cycles It takes to execute the Interrupt service routine plus 20 tCyc
cycles.

3-965

I

MC146805H2

TABLE 2 - CONTROL TIMING
(VOO=30Vdc, VSS=OVdc TA=0°Ct070°C)

Characteristic
Crystal Oscillator Startup Time (See Figure 5)
Stop Recovery Startup Time (Crystal Oscillator) (See Figure 6)

Symbol

Min

Max

Unit

-

TSO
TSO

ms
ms

Timer Pulse Width (See Figure 4)

toxOV
tlLCH
tTH, tTL

0.5

-

tcyc

RESEi Pulse Width (See Figure 5)

tRl

1.5

tcyc

tTLTl
tlLlH

1.0
1.0

-

tlLll
tOH, tOl

Timer Period (See Figure 4)
Interrupt Pulse Width low (See Figure 14)
Interrupt Pulse Period (See Figure 14)
OSCl Pulse Width
Cycle Time
Frequency of Operation
Crystal
Synthesizer

I

tcyc

tcyc

-

tcyc

*

-

TSO
5000

-

tcyc
ns

-

ns

30
kHz
50
fosc
120
600
kHz
fsynth
*The minimum period tlLll should not be less than the number of tcyc cycles It takes to execute the Interrupt service routines plus 20 tcyc
cycles.

FIGURE 2 -

EQUIVALENT TEST LOAD

VOO=4.5 V
MM06150
or Equiv.

TestPoint

o-----...--...- .........

-~

50pF

TYPICAL CURRENT CALCULATIONS

Rl
(See
Table)

R2
(See
Table)

MMD7000
or Equiv.

placed in the active region of the input device. Because of
this, inputs should never be allowed to Simply "float". It is
impossible to determine a "typical" 100 for a particular application without first knowing all of the above conditions
and their corresponding currents. Thus, some "typical" current curves are provided in Figure 3 (a, b, and c). It should be
emphasized that these are only approximations and no minimums or maximums are implied.

The operating current of the MCU (100) is a function of
supply voltage, bus rate, capacitive loading on any active
pins (i.e., OSC1, OSC2, etc.), the processor state (RUN,
WAIT, or STOP), the synthesizer state (ON or OFF), and the
resistive loading on all outputs. Inputs, such as input ports
can also cause significant increases in currents if they are

3-966

MC146805H2

FIGURE 3 - TYPICAL OPERATING CURRENT vs FREQUENCYIVOLTAGE
(a) -

Processor Current vs Bus Frequency

(b) -

Typical Crystal Oscillator Current vs Voltage

4.0...----------------------,
25
6V

]3.0

1 20

I-

Z

I-

a:
a:

Z

Ill:

G 2.0

~ 15

><>.
<>.

a:

en

I-

o

~

~ 10

~1.0

~
j
0.4

0.5

0.6

0.7

0.8

0.9

1.0

O~~----------------------------------~
4.0
o
1.0
2.0
3.0
5.0

Bus Rate (MHz)

VOO·VSS (VOLTS)

(c) - Typical Synthesizer Current vs Frequency
250...------------------------------------~

5V

200
a:
~

!

150

in 100
50

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

fsynth. SYNTHESIZER OUTPUT FREQUENCY (MHz)

FIGURE 4 - TIMER RELATIONSHIPS

External
Clock

Timer)
( Pin
37

3-967

1.8

2.0

I

III
3:

o...a.
~
0)
(X)

o(II
FIGURE 5 - POWER-ON RESET, WATCHDOG RESET, AND RESET

I

I

VOD

Yr~----------------------------------------------

,

OSC1**

I

~~T7~77~Z~77~ZI77Z77777777ZZ77~ZZZZ777~
ltoxov,1

I

,""

1920 tcyc

~II(

,I
,I
4>2*

I
I
.,

i,

tcyc

I-'

ILJ

w

cO

0)
(Xl

Internal
Address
Bus*

Internal
Data
Bus*

RESET

J

* Internal timing signal and
* *OSC1

- - _.

bus information not available externally.
line is not meant to represent frequency. It is only used to represent time.

r- ----1JZ
\k
tRL

l:
I\)

MC146805H2

FIGURE 6 -

STOP RECOVERY AND POWER-ON RESET

O~:··_~IIIIIIIIIII
(EdgeSensitive
Only)
IRQ
or

RESET

; III

~tcyc~

~t-

~

U
..

,./'---,

1\

tilCH

1920tcyc

~2*----------------------------------------------~

* Internal

timing signals not available externally.

* * Represents the internal control of crystal oscillator.

FUNCTIONAL PIN DESCRIPTION

RESET
The RESET input is not required for startup but can be
used to reset the MCU internal state and provide an orderly
software startup procedure. Refer to RESETS for a detailed
description.

VDD, VSS, AND SYNTH VSS
Power is supplied to the MCU using these pins. VDD is
power and VSS is ground. A separate ground is provided for
the synthesizer which must be at the same potential as VSS.
These grounds (synthesizer VSS and VSS) may be bypassed
independently to minimize noise if necessary.

TIMER
The TIMER input may be used as an external clock for the
on-chip timer. Refer to TIMER for additional information
about the timer circuitry.
OSC1, OSC2
The MCl46805H2 is configured to accept a crystal to control the internal oscillator. An external clock may also be used. These are discussed below.

IRQ (MASKABLE INTERRUPT REQUEST)
IRQ is a mask programmable option which provides two
different choices of interrupt triggering sensitivity. These options are: 1) negative edge-sensitive triggering only, or 2)
both negative edge-sensitive and level-sensitive triggering. In
the latter case, either type of input to the IRQ pin will produce the interrupt. The MCU completes the current instruction before it responds to the interrupt request. When the
IRQ pin goes low for at least one t cyc , a logic one is latched
internally to signify an interrupt has been requested. When
the MCU completes its current instruction, the interrupt
latch is tested. If the interrupt latch contains a logic one and
the interrupt mask bit (I bit) in the condition code register is
clear, the MCU then begins the interrupt sequence.

CRYSTAL - The circuit shown in Figure 7(b) is recommended when using a crystal. The internal oscillator is
designed to interface with a parallel resonant quartz crystal
resonator in the frequency range specified for fosc in Table 1
and Table 2 control timing. USing an external CMOS
oscillator is recommended when crystals outside the
specified ranges are to be used. The crystal and components
should be mounted as close as possible to the input pins to
minimize output distortion and startup stabilization time.
EXTERNAL CLOCK - An external clock should be applied to the OSC1 input with OSC2 not connected, as shown
in Figure 7(d)' The toxOV or tilCH specifications do not apply when using an external clock input.

If the option is selected to include level-sensitive triggering, then the IRQ input requires an external resistor to VDD
for "wire-OR" operation. See INTERRUPTS for more detail.

3-969

I

MC146805H2

FIGURE 7 -

OSCILLATOR CONNECTIONS

Vendor A

Vendor B

Units

RS(Max)

50

23

kD

Co

0.8

15

pF

Cl

-

2.35

pF

COSCl

10

35

pF

COSC2

2.5-10

5-30

pF

60

90

K

2-10

2-10

MD

Q

Rp

(a) Typical Crystal Parameters @ 32.768 kHz

I

SC2

~

MC146805H2
OSCl
39

.----*---l
COSCl

~

Rp

L

C~l
RS
OSCl

38

OSC2

39

Co

38

DI-----~,-------,>TJ.lLJ'-"2

F

4

BRSET251 -;SET251
BCC
LSR 51
LSRA 31
LSRX 31
LSR 61
LSR
3
BTB 2
BSC 2
REL 2
OlR
1
INH
1
INri
2
IX 1 1
5
BRCLR2
BCLR251
BCS
3
BTB 2
BSC 2
R
5
3
5
1 RORA 31
- 1
ROR
BRSET3" 1
BSET3
BNEROR
RORX 3
ROR
I3
BTB 2
BSC 2
REL 2
DIR
1
INH
1
INH I 2
IX 1 I 1

~- BSE~~:

IX-

1X1

1~0

Jol

-~3
-41
SUB
SUB

~

RTI
RTS
INH

BRCLR1'1 -;;:CLR,51
BLS
3
BTB 2
BSC 2
R

lrL

1)(2 --1

-Joe

1"1
-51
SUB
SUB
SUB
SUB
12
IMM
DIR
EXT 3
IX2 2
IX 1 I 1
IX
21
31
41
51
CMP
CMP
CMP
CMP
IXl I I
IX2 I 2
IX
IMM 12 CMPDIR 13 CM~XT I 3

REL

I

EXT!

1

---:'1

10
0011

~

Register / Memory

Control

01~,1 o~o

0100

o.....

B

ADD
1

C

JMP
1

IX

1100

IX

1101

IX

1110

IX

1111

o

JSR
1

E

LOX
1

F

STX
1

LEGEND
01(

Mnemonic
Bytes

~..
1

Cycles _ _ _ _ _ _- J

~

~X

I

l

Opcode in Hexadecimal

~

Opcode in Binary

(XXX) ~

' - - - - - - - - - - Address Mode

en
CO
o
C1I

J:

N

MC146805H2

TABLE 12 -

INSTRUCTION SET

Addressing Modes
Mnemonic

Inherent

ADC
ADD
AND
ASl
ASR
BCC
BClR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
Bil
BIT
BlO
BlS
BMC
BMI
BMS
BNE
BPl
BRA
BRN
BRClR
BRSET
BSET
BSR
ClC
CLI
ClR
CMP
COM
CPX
DEC
EOR
INC
JMP
JSR
lOA
lOX
lSl
lSR
NEG
NOP
ORA
ROl
AOA
ASP
ATI
ATS
SBC
SEC
SEI
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT

Immediate

Direct

Extended

X
X
X

X
X
X
X
X

X
X
X

X
X

Relative

Condition Codes

Indexed
(No Offset)

Indexed
(8 Bits)

Indexed
(16 Bits)

X
X
X
X
X

X
X
X
X
X

X
X
X

Bit

Set/
Clear

Bit
Test &
Branch

H

N Z C

A
I\.

•

X
X
X
X
X
X
X
X
X
X

X

X

X

A

A

I\.

I\.

A
A
A

A
A
A

A.

••
•
••

X

X

A
I\.

••
•
••

X

A

••
••
••
•
••
•

•A

I

A

X
X
X
X
X
X
X
X
X
X
X

A

X
X
X
X
X

0
X

X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X

X
X
X

X

X

X

0

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X

X
X
X

X

X

X

X

X
X

X
X
X
X

A
A
A

•
•

0
•
•

•
•
•••
•0
•
•
••
•
•

1

X

X

X

X

X

X
X

X
X

X
X

X
X

X
X

X
X

1

X
X
X
X
X

X

X

X

Condition Code Symbols
Half Carry (From Bit 31
Interrupt Mask
Negative (Sign Bill
Zero
Carry/Borrow

A
•
)

o

Test and Set If True Cleared Otherwise
Not Affected
load CC Register From Stack
Cleared
Set

3-991

1
A
A
A
A
A
A

A
1
A

•

•
•• •• •••
•

X

X
X

H
I
N
Z
C

A
A
A
A
A
A

•
•0
••

•o

I\.

_.

A
A

A
A

A

~_A

•••
•
•••
•••
•• •• •
• • •••
•• ••A ••
•
•• •
• ••
A

A

A

I\.

I\.

A

A

A

A

A

A
1

A

A

A
A

A
A

I\.

A

A

M,C146805H2

ORDERING INFORMATION
The following information is required when ordering a
custom MCU. This information may be transmitted to
Motorola in the following media:
EPROM(s) MCM2716s or MCM2532s
M DOS disk file
To initiate a ROM pattern for the MCU, it is necessary to
first contact your local field service office, local sales person,
or your local Motorola representative.

I

EPROMs
The MCM2716 or MCM2532 type EPROMs, programmed
with the customer program (positive logic sense for address
and date), may be submitted for pattern generation. The
EPROMs must be clearly marked to indicate which EPROM
corresponds to which address space. Figure A-l illustrates
the marking for the two MCM2716 EPROMs required to
emulate the MCl46805H2.
After the EPROM(s) are marked, they should be placed in
conductive IC carriers and securely packed. Do not use
styrofoam.

FIGURE A-1 -

0080

EPROM MARKING

0800

xxx = Customer 10

3-992

VERIFICATION MEDIA
All original pattern media (EPROMs or floppy disk) are
filed for contractual purposes and are not returned. A computer listing of the ROM code will be generated and returned
along with a listing verification form. The listing should be
thoroughly checked and the verification form completed,
signed, and returned to Motorola. The signed verification
form constitutes the contractual agreement for creation of
the customer mask. If desired, Motorola will program a blank
MCM2716 or MCM2532 EPROM (supplied by the customer)
from the data file used to create the custom mask to aid in
the verification process.
ROM VERIFICATION UNITS
Ten MCUs containing the customer's ROM pattern will be
sent for program verification. These units will have been
made using the custom mask but are for the purpose of
ROM verification only. For expediency they are usually unmarked, packaged in ceramic, and tested only at room
temperature and five volts. These RVUs are included in the
mask charge and are not production parts. These RVUs are
not backed nor guaranteed by Motorola Quality Assurance.
FLEXIBLE DISKS
The disk media submitted must be single-sided, single
density, a-inch, MOOS compatible floppies. The customer
must clearly label the disk with the ROM pattern file name
and company name. The floppies are not returned by
Motorola as they are used for archival storage. The minimum
MOOS system files as well as the absolute binary object file
(filename. LO type of file) from the M6805 cross assembler
must be on the disk. An object file made from a memory
dump using the ROLLOUT command is also admissable.
Consider submitting a source listing as well as: filename,
. LX(EXORciser loadable format). This file will of course be
kept confidential and is used 1) to speed up the process in
house if any problems arise, and 2) to speed up our customer
to factory interface if a user finds any software errors and
needs assistance quickly from the factory representative.
MOOS is Motorola's Disk Operating System available on
development systems such as EXORciser, EXORset, etc.

MC146805H2

OPTION LIST

Select the options for the MCU from the following list. A manufacturing mask will be generated from this information. Select
one in each section.
Operating Voltage
3 V (262 kHz bus with 32.768 kHz Crystal)
05 V (1.049 MHz bus with 32.768 kHz Crystal)

o

Interrupt Trigger
Edge-Sensitive
Level- and Edge-Sensitive

o
o

Customer Name' __________________________________________________________________________________
Address ______________________________________

~

_______________________________________________

City,_______________________________ State ____________________________________________ Zip _ _ __
Phone (_), _____________________________________________________________________ Extension ______
Contact Ms/Mr·__________________________________________________________________________
Customer Part Number _________________________________________________________________________

Pattern Media
02532 EPROM
02716 EPROM
MOOS Disk File
(Note), ______________________________________________________________________________

oo

NOTE: Other media require prior factory approval.

Signature' _________________________________________________________________________
Title' ________________________________________________________________

3-993

I

®

MCl46818
Addendum

MOTOROLA
Advance Information

I

REAL· TIME CLOCK PLUS RAM (RTC)
Advance Information Data Sheet
ADI·856·Rl

The following information is an addition to POWER-DOWN CONSIDERATIONS
found on page 11 of the MC146818 Advance Information Data Sheet (ADI-856-R1).

MC146818s with the date code of 3N46XXXX and GC6XXXX require a synchronization of the CE pin with address strobe. The following circuit will satisfy that condition, and also show a typical application of power-down circuitry.
If EE is grounded at all times (no power down required) the following circuit need
not be used.

3-994

MC146818

MC146818

+5V
4
MBD701
(Schottky)
BBV*
lN4148
(Si)

3.9V

ADO

ADO

ADl

ADl

AD2 -

AD2

AD3

AD3

AD4

AD4

AD5

AD5

AD6
AD7

l

470 k

AS

10
11
14
17

32.768 kHz

OSC2

OSCl

-:t.

BBV

STATEK
CXIVor
Equivalent

10 pF

AD6
AD7
AS

100 k

DS
PS

R/W

15

R/W

I

RESET

~50PF

13
CE

BBV

+5V

1M ::>-Of---i

MC74HC373 (See Note 11

1M

(SeeNote2)
* BBV = Battery Backup Voltage
NOTES
1. All unused inputs of the MC74HC373 must be grounded
2. If point
equals 12 V point
should be equal to 406 V If point
for 3.18 V

®

®

3-995

®

equals 10 V point

®

should be equal to 3.38 V with

©

set

®

MC146818

MOTOROLA
Advance Information

CMOS

REAL-TIME CLOCK PLUS RAM (RTC)

I

The MC146818 Real-Time Clock plus RAM is a peripheral device
which includes the unique MOTEL concept for use with various
microprocessors, microcomputers, and larger computers. This part
combines three unique features: a complete time-of-day clock with
alarm and one hundred year calendar, a programmable periodic interrupt and square-wave generator, and 50 bytes of low-power static
RAM. The MC146818 uses high-speed CMOS technology to interface
with 1 MHz processor buses, while consuming very little power.
The Real-Time Clock plus RAM has two distinct uses. First, it is
designed as a battery powered CMOS part (in an otherwise NMOSITTL
system) including all the common battery backed-up functions such as
RAM, time, and calendar. Secondly, the MC146818 may be used with a
CMOS microprocessor to relieve the software of the timekeeping
workload and to extend the available RAM of an MPU such as the
MC146805E2.
•
•
•
•

Low-Power, High-Speed, High-Density CMOS
Internal Time Base and Oscillator
Counts Seconds, Minutes, and Hours of the Day
Counts Days of the Week, Date, Month, and Year

•

3 V to 6 V Operation

•

Time Base Input Options: 4.194304 MHz, 1.048576 MHz, or
32.768 kHz

(HIGH-PERFORMANCE
SILICON-GATE COMPLEMENTARY MOS)

REAL-TIME CLOCK
PLUS RAM

L SUFFIX
CERAMIC PACKAGE
CASE 716

P SUFFIX
PLASTIC PACKAGE
CASE 709

S SUFFIX
CERDIP PACKAGE
CASE 623

•

Time Base Oscillator for Parallel Resonant Crystals

•

40 to 200 p.W Typical Operating Power at Low Frequency Time Base

•

4.0 to 20 mW Typical Operating Power at High Frequency Time
Base

•
•

Binary or BCD Representation of Time, Calendar, and Alarm
12- or 24-Hour Clock with AM and PM in 12-Hour Mode

•

Daylight Savings Time Option

•
•
•
•
•
•
•

Automatic End of Month Recognition
Automatic Leap Year Compensation
Microprocessor Bus Compatible
MOTEL Circuit for Bus Universality
Multiplexed Bus for Pin Efficiency
Interfaced with Software as 64 RAM Locations
14 Bytes of Clock and Control Registers

•
•
•

50 Bytes of General Purpose RAM
Status Bit Indicates Data Integrity
Bus Compatible Interrupt Signals (IRQ)

AD1

(9)

AD2

(10)

(32) 19

iFill

Three Interrupts are Separately Software Maskable and Testable
Time-of-Day Alarm, Once-per-Second to Once-per-Day

AD3

(11)

(31)18

RESET

AD4

8 (12)

(30) 17

DS

AD5

(13)

AD6

10 (18)

AD7

11 (19)

AS

VSS

12 (20)

a

•

Z SUFFIX
CHIP CARRIER
CASE 761

PIN ASSIGNMENT
NC

Periodic Rates from 30.5 p.s to 500 ms
End-of-Clock Update Cycle
•

Programmable Square-Wave Output Signal

•
•

Clock Output May Be Used as Microprocessor Clock Input
At Time Base Frequency + 1 or +4
24-Pin Dual-In-Line Package

•

Chip Carrier Also Available

VDD

OSC1

(3)

(38) 23

OSC2

3 (4)

(37) 22

PS

ADO

(8)

(34) 21

CKOUT

SOW

CKFS

NC
R/W

Pin numbers in parentheses represent equivalent Z
suffix chip carrier pins. Pins that have not been
designated for the chip carrier are not connected.

This document contains information on a new product. Specifications and information herein
are subject to change without notice.

3-996

MC146818

FIGURE 1 - BLOCK DIAGRAM
CKOUT
CKFS

OSC1
OSC2

SOW
VDD -----.
VSS

----+IRQ
RESET
PS

Bus
Interface
Clock/
Calendar
Update

Clock, Alarm,
Calendar RAM
110 Bytes)

BCD/
Binary
Increment
User RAM
150 Bytes)

MAXIMUM RATINGS (Voltages referenced to VSSI
Ratings
Supply Voltage
All Input Voltages Except OSC1
Current Drain per Pin Excluding
VDD and VSS
Operating Temperature Range
MC146818
MC146818C (VDD = 3.0 to 5.5 V
operation)
Storage Temperature Range

Unit

Symbol

Value

VDD

-0.3 to +8.0

V

Vin

VSS-05 to VDD+0.5

V

I

10

mA

TA

TL to TH
o to 70
-40 to 85

°C

Tstg

- 55 to + 150

°C

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Plastic
Cerdip
Ceramic

Symbol

Value

Unit

()JA

120
65
50

°C/W

3-997

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSSslVin or Voutl
s VDD. Reliability of operation is enhanced if
unused inputs are tied to an appropriate logic
voltage level le.g., either VSS or VDDI

I

MC146818

DC ELECTRICAL CHARACTERISTICS (VDD=3 Vde VSS=O Vde TA=TL to TH unless otherwise noted I
Characteristics

Symbol

Min

Max

Unit

Frequency of Operation

fose

32.768

32.768

kHz

Output Voltage

VOL

-

0.1

ILoad<10,..A

VOH

VDD-01

-

1003

-

50

,..A

1004

-

50

,..A

VOH

2.7

-

V

100 - Bus Idle
CKOUT=fos e, CL = 15 pF; SQW Disabled, CE=VDD-0.2; CL (OSC21= 10 pF
fose= 32.768 kHz
100 - Quiescent
fose= DC; OSC1 = DC;
All Other Inputs=VDD-0.2 V;
No Cloek
Output High Voltage
ILLoad= -0.25 mA. All Outputsl

I

Output Low Voltage
(ILoad=025 mA, All Outputsl
Input High Voltage

ADO-AD7, OS, AS, R/W, CE,
RESET, CKFS, PS, OSC1

Input Low Voltage (All Inputsl
Input Current

All Inputs

Three-State Leakage

IRQ, ADO-AD7

V

VOL

-

0.3

V

VIH

2.1
2.5

V

VIL

VSS

VDD
VDD
0.5

lin

-

±1

,..A

ITSL

-

±10

,..A

V

DC ELECTRICAL CHARACTERISTICS (VDD = 5 Vde +
- 10%, VSS = 0 Vdc T A = TL to TH unless otherwise notedl
Symbol

Min

Max

Unit

Frequency of Operation

fose

32.768

4194.304

kHz

Output Voltage

VOL

-

0.1

VOH

VDD-01

-

1001
1002
1003

-

3
800
50

mA
,..A
,..A

1004

-

50

,..A

Output High Voltage
(ILoad = -1.6 mA, ADO-AD7, CKOUTI
(ILoad = -1.0 rnA, SQWI

VOH

4.1

-

V

Output Low Voltage
(ILoad = 1.6 rnA, ADO-AD7, CKOUTI
(ILoad= 1.0 rnA, IRQ and SQWI

VOL

-

0.4

V

CKFS, ADO-AD7, OS, AS, R/W, CE, PS
RESET
OSC1

VIH

VDD-20
VDD-08
VDD-1.0

ADO-AD7, OS, AS, R/W, CE
CKFS, PS, RESET
OSC1

VIL

VSS
VSS
VSS

VDD
VDD
VDD
0.8
0.8
0.8

lin

-

±1

,..A

ITSL

-

±10

,..A

Characteristics

ILoad< 10,..A
100 - Bus Idle (External Clockl
CKOUT = fosc, CL = 15 pF; SQW Disabled,
fosc= 4.194304 MHz
fose= 1.048516 MHz
fosc=32.768 kHz

IT = VDD -

02; CL (OSC21 = 10 pF

100 - Quiescent
fosc= DC; OSC1 = DC;
All Other Inputs=VDD-0.2 V;
No Clock

Input High Voltage

Input Low Voltage

V

Input Current

All Inputs

Three-State Leakage

iRQ, ADO-AD7

3-998

-

V

V

MC146818

BUS TIMING

VDD=3.0 V
50 pF Load

Ident.
Number

VDD=5.0 V
±10%
2 TIL and
130 pF Load

Symbol

Min

Max

Min

Max

Unit

tcyc

5000

-

953

dc

ns

Pulse Width. DS/E Low or RD/WR High

PWEL

1000

-

300

-

ns

3

Pulse Width. DS/E High or RD/WR Low

PWEH

1500

-

325

-

ns

4

Input Rise and Fall Time

-

30

ns

8

ns

Characteristics

1

Cycle Time

2

tr,tf

-

100

R/W Hold Time

tRWH

10

-

10

-

13

R/W Setup Time Before DS/E

tRWS

200

-

80

-

ns

14

Chip Enable Setup Time Before ASI ALE Fall

tcs

200

*

55

*

ns

15

Chip Enable Hold Time

tCH

10

-

ns

18

Read Data Hold Time

tDHR

10

21

Write Data Hold Time

tDHW

100

-

0

-

ns

24

Muxed Address Valid Time to ASI ALE Fall

tASL

200

-

50

-

ns

25

Muxed Address Hold Time

tAHL

100

-

20

-

ns

26

Delay Time DS/E to ASI ALE Rise

500

-

50

-

ns

27

Pulse Width, ASI ALE High

tASD
PW ASH

600

-

135

-

ns

-

1000

0
10

100

ns

28

Delay Time, ASI ALE to DS/E Rise

tASED

500

-

60

-

ns

30

Peripheral Output Data Delay Time from DS/E or RD

tDDR

1300

-

20

240

ns

31

Peripheral Data Setup Time

tDSW

1500

-

200

NOTE: Designations E, ALE, RD, and WR refer to signals from alternative microprocessor signals
* Refer to IMPORTANT NOTICES appearing on page 20 of this data sheet

FIGURE 2 -

MC146818 BUS TIMING

DS

R/W

ADOAD7
WRITE

ADO
AD7
READ
NOTE: VHIGH = VDD - 2.0 V, VLOW = 0.8 V, for VDD = 5.0 V ± 10%

3-999

-

ns

I

MC146818

FIGURE 3 -

BUS READ TIMING COMPETITOR MULTIPLEXED BUS

ALE (Address Latch Enable)
(AS Pin)

RD (Read Output Enable)
(DS Pin)

WR (Write Enable)
(RiW Pin)

I

CE

(Chip Enable)

ADO-AD7
(Address/Data Bus)

------------------~

FIGURE 4 -

BUS WRITE TIMING COMPETITOR MULTIPLEXED BUS

ALE (Address Latch Enable)
(AS Pin!

REi

(Read Output Enable!
IDS Pin)

WR IWrite Enable!
(R/W Pin)

CE(ChipE_n_ab_l_e)______~~~~~~~~~~~--~~----------------------------~~~~~~~_
ADO-AD7
(Address/ Dat-;:.a.,:;:B.,:;:u,:;:;s)_____________________

-< I

NOTE: VHIGH=VDD-2.0 V, VLOW=O.8 V, for VDD=5.0 V ± 10%

3-1000

MC146818

TABLE 1 - SWITCHING CHARACTERISTICS (V DD =5.0 Vdc

± 10%,

VSS=O Vdc, TA=TL to TH)

Symbol

Description

Min

Max

Unit

-

100

ms

-

p's

Oscillator Startup

tRC

Reset Pulse Width

tRWL

5

Reset Delay Time

tRLH

5

Power Sense Pulse Width

tpWL

5

Power Sense Delay Time

tpLH

5

IRO Release from OS

tlRDS

-

2

p's

tlRR

-

2

p's

2

p's

IRO Release from RESET

tVRTO

VRT Bit Delay

~~ VLOW

RESET

~rA

}

IRO

tlRR

tjRDS
NOTE: VHIGH = VOO- 2.0 V, VLOW=0.8 V, for VOO= 5.0 V

}'-

"

VHIGH

± 10%

FIGURE 6 - TTL EQUIVALENT TEST LOAD

Voo
(lRO Only)

2k
Test
Point

Test Point
Vi
130 pF

MM07000
or Equivalent

All Outputs Except OSC2 (See Figure 101

3·1001

p's
p's

11

FIGURE 5 - IRQ RELEASE DELAY

OS

p's

MC146818

FIGURE 7 -

VDD Pin

OV _ _

POWER-UP

-.l/T--------2 (r/>2
clock). During read cycles, DS signifies the time that the
RTC is to drive the bidirectional bus. In write cycles, the trailing edge of DS causes the Real-Time Clock plus RAM to
latch the written data.
The second MOTEL interpretation of DS is that of RiS,
MEMR, or I/OR emanating from the competitor type processor. In this case, DS identifies the time period when the
real-time clock plus RAM drives the bus with read data. This
interpretation of DS is also the same as an output-enable
Signal on a typical memory,
The MOTEL circuit, within the MCl46818, latches the
state of the DS pin on the falling edge of ASI ALE. When the
Motorola mode of MOTEL is desired DS must be low during
AS/ ALE, which is the case with the Motorola multiplexed
bus processors. To ensure the competitor mode of MOTEL,

IRQ -

INTERRUPT REOUEST, OUTPUT

The IRO pin is an active low output of the MC146818 that
may be used as an interrupt input to a processor. The IRO
output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit
is set. To clear the IRO pin, the processor program normally
reads Register C. The RESET pin also clears pending interrupts.
When no interrupt conditions are present, the IRO level is
in the high-impedance state. Multiple interrupting devices
may thus be connected to an IRO bus with one pullup at the
processor,
RESET -

RESET, INPUT

The RESET pin does not affect the clock, calendar, or
RAM functions. On powerup, the RESET pin must be held
low for the specified time, tR LH, in order to allow the power
supply to stabilize. Figure 13 shows a typical representation
of the RESET pin circuit
When RESET is low the following occurs:
a) Periodic Interrupt Enable (PIE) bit is cleared to zero,
b) Alarm Interrupt Enable (AlE) bit is cleared to zero,
cI Update ended Interrupt Enable (UIE) bit is cleared to
zero,
d) Update ended Interrupt Flag (UF) bit is cleared to zero,
e) Interrupt Request status Flag (IROF) bit is cleared to
zero,
f) Periodic Interrupt Flag (PF) bit is cleared to zero,
g) The part is not accessible.

3·1005

I

MC146818

g) Alarm Interrupt Flag (AF) bit is cleared to zero,
h) IRO pin is in high-impedance state, and
i) Square Wave output Enable (SOWE) bit is cleared to
zero.

FIGURE 13 - TYPICAL POWERUP DELAY
CIRCUIT FOR RESET

PS - POWER SENSE, INPUT
The power-sense pin is used in the control of the valid
RAM and time (VRT) bit in Register D. When the PS pin is
low the VRT bit is cleared to zero.
When using the VRT feature during powerup, the PS pin
must be externally held low for the specified tpLH time. As
power is applied, the VRT bit remains low indicating that the
contents of the RAM, time registers, and calendar are not
guaranteed. PS must go high after powerup to allow the
VRT bit to be set by a read of register D.

02

01

....---+.- Backup
Battery

System ---1~--I"'-VOO

Voo
1.0 k

03

I

MC146818

POWER-DOWN CONSIDERATIONS

I

0.005 I'F

In most systems, the MC146818 must continue to keep
time when system power is removed. In such systems, a
conversion from system power to an alternate power supply,
usually a battery, must be made. During the transition from
system to battery power, the designer of a battery backed-up
RTC system must protect data integrity, minimize power
consumption, and ensure hardware reliability.
The chip enable (EE) pin controls all bus inputs (R/W, DS,
AS, ADO-AD7). EE, when negated, disallows any unintended modification of the RTC data by the bus. EE also reduces
power consumption by reducing the number of transitions
seen internally.
Power consumption may be further reduced by removing
resistive and capacitive loads from the clock out (CKOUT)
pin and the squarewave (SOW) pin.
During and after the power source conversion, the VIN
maximum specification must never be exceeded. Failure to
meet the VIN maximum specification can cause a virtual
SCR to appear which may result in excessive current drain
and destruction of the part.

VSS

01 = MB0701 (Schottkyl or Equivalent
02 = 03 = 1N4148 or Equivalent
Note: If the RTC is isolated from the MPU or MCU power by a
diode drop, care must be taken to meet Vin requirements.

FIGURE 14 -

TYPICAL POWERUP DELAY CIRCUIT
FOR POWER SENSE

01

02

System --IIM---...- - - - - - - ;...- .........VOO

VSS

I

Battery
Backup

ADDRESS MAP
Figure 15 shows the address map of the MCl46818. The
memory consists of 50 general purpose RAM bytes, 10 RAM
bytes which normally contain the time, calendar, and alarm
data, and four control and status bytes. All 64 bytes are
directly readable and writable by the processor program except for the following: 1) Registers C and D are read only, 2)
bit 7 of Register Ais read only, and 3) the high-order bit of
the seconds byte is read only. The contents of four control
and status registers (A, B, C, and D) are described in
REGISTERS.

TIME, CALENDAR, AND ALARM LOCATIONS

01 = MB0701 (Schottkyl or Equivalent
02= 1N4148 or Equivalent

The processor program obtains time and calendar information by reading the appropriate locations. The program
may initialize the time, calendar, and alarm by writing to
these RAM locations. The contents of the 10 time, calendar,
and alarm bytes may be either binary or binary-coded decimal (BCD)

3·1006

MC146818

0-to-23. The 24/12 bit cannot be changed without reinitializing the hour locations. When the 12-hour format is selected
the high-order bit of the hours byte represents PM when it is
a "1"The time, calendar, and alarm bytes are not always accessable by the processor program. Once-per-second the 10
bytes are switched to the update logic to be advanced by one
second and to check for an alarm condition. If any of the 10
bytes are read at this time, the data outputs are undefined.
The update lockout time is 248 P.s at the 4.194304 MHz and
1.048567 MHz time bases and 1948 P.s for the 32.768 kHz
time base. The Update Cycle section shows how to accommodate the update cycle in the processor program.

Before initializing the internal registers, the SET bit in
Register B should be set to a "1" to prevent time/calendar
updates from occurring. The program initializes the 10 locations in the selected format (binary or BCD), then indicates
the format in the data mode 10M) bit of Register B. All 10
time, calendar, and alarm bytes must use the same data
mode, either binary or BCD. The SET bit may now be cleared
to allow updates. Once initialized the real-time clock makes
all updates in the selected data mode. The data mode cannot
be changed without reinitializing the 10 data bytes.
Table 3 shows the binary and BCD formats of the 10 time,
calendar, and alarm locations. The 24/12 bit in Register B
establishes whether the hour locations represent 1-to-12 or
FIGURE 15 -

ADDRESS MAP

00
14
BylAS

13

00

14

OE

50
Bytes
User
RAM

3F

63

TABLE 3 -

0

Seconds

1

Seconds Alarm

2

Minutes

3

Minutes Alarm

4

Hours

00

I

01
02
03
04

5

Hours Alarm

05

6

Day of Week

06

7

Date of Month

07

8

Month

08

9

Year

09

10

Register A

OA

11

Register B

OB

12

Register C

OC

13

Register D

00

Binary
or BCD
Contents

TIME, CALENDAR, AND ALARM DATA MODES

Decimal
Range

0

Seconds

0-59

$00-$3B

$00-$59

15

1

Seconds Alarm

0-59

$00-$3B

$00-$59

15

21

2

Minutes

0-59

$00-$3B

$00-$59

3A

58

3

Minutes Alarm

0-59

$00-$38

$00-$59

3A

58

Hours
(12 Hour Mode)

1-12

$Ol-$OC (AM) and
$81-$8C (PM)

$01-$12 (AM) and
$81-$92 (PM)

05

05

Hours
(24 Hour Mode)

4

5

Range
BCD Data Mode
Binary Data Mode

Example*
Binary
BCD
Data Mode Data Mode

Function

Address
Location

21

0-23

$00-$17

$00-$23

05

05

Hours Alarm
(12 Hour Mode)

1-12

$Ol-$OC (AM) and
$81-$8C (PM)

$01-$12 (AM) and
$81-$92 (PM)

05

05

Hours Alarm
(24 Hour Mode)

0-23

$00-$17

$00-23

05

05
05

6

Day of the Week
Sunday= 1

1-7

$01-$ 07

$01-$07

05

7

Date of the Month

1-31

$Ol-$lF

$01-$31

OF

15

8

Month

1-12

$Ol-$OC

$01-$12

02

02

9

Year

0-99

$00-$63

$00-$99

4F

79

'Example: 5:58:21 Thursday 15 February 1979 (time is AM)

3·1007

MC146818

The three alarm bytes may be used in two ways. First,
when the program inserts an alarm time in the appropriate
hours, minutes, and seconds alarm locations, the alarm
interrrupt is initiated at the specified time each day if the
alarm enable bit is high. The second usage is to insert a
"don't care" state in one or more of three alarm bytes. The
"don't care" code is any hexadecimal byte from CO to FF.
That is, the two most-significant bits of each byte, when set
to "1", create a "don't care" situation. An alarm interrupt
each hour is created with a "don't care" code in the hours
alarm location. Similarly, an alarm is generated every minute
with "don't care" codes in the hours and minutes alarm
bytes. The "don't care" codes in all three alarm bytes create
an interrupt every second.
STATIC CMOS RAM

I

The 50 general purpose RAM bytes are not dedicated
within the MC146818. They can be used by the processor
program, and are fully available during the update cycle,
When time and calendar information must use battery
back-up, very frequently there is other non-volatile data that
must be retained when main power is removed, The 50 user
RAM bytes serve the need for low-power CMOS batterybacked storage, and extend the RAM available to the program.
When further CMOS RAM is needed, additional
MC146818s may be included in the system. The time/calendar functions may be disabled by holding the DVO-DV2
dividers, in Register A, in the reset state by setting the SET
bit in Register B or by removing the oscillator. Holding the
dividers in reset prevents interrupts or SQW output from
operating while setting the SET bit allows these functions to
occur. With the dividers clear, the available user RAM is extended to 59 bytes. The high-order bit of the seconds byte,
bit 7 of Register A, and all bits of Registers C and 0 cannot
effectively be used as general purpose RAM.
INTERRUPTS

The RTC plus RAM includes three separate fully automatic
sources of interrupts to the processor. The alarm interrupt
may be programmed to occur at rates from once-per-second
to one-a-day. The periodic interrupt may be selected for
rates from half-a-second to 30.517 ILs. The update-ended
interrupt may be used to indicate to the program that an update cycle is completed. Each of these independent interrupt
conditions are described in greater detail in other sections.
The processor program selects which interrupts, if any, it
wishes to receive, Three bits in Register B enable the three
interrupts. Writing a "1" to a interrupt-enable bit permits
that interrupt to be initiated when the event occurs. A "0" in
the interrupt-enable bit prohibits the IRQ pin from being
asserted due to the interrupt cause.
If an interrupt flag is already set when the interrupt
becomes enabled, the IRQ pin is immediately activated,
though the interrupt initiating the event may have occurred
much earlier. Thus, there are cases where the program
should clear such earlier initiated interrupts before first
enabling new interrupts.

When an interrupt event occurs a flag bit is set to a "1" in
Register C. Each of the three interrupt sources have separate
flag bits in Register C, which are set independent of the state
of the corresponding enable bits in Register B. The flag bit
may be used with or without enabling the corresponding
enable bits.
In the software scanned case, the program does not
enable the interrupt. The "interrupt" flag bit becomes a
status bit. which the software interrogates, when it wishes.
When th.e software detects that the flag is set, it is an indication to software that the "interrupt" event occurred since the
bit was last read.
However, there is one precaution. The flag bits in Register
C are cleared (record of the interrupt event is erased) when
Register C is read. Double latching is included with Register
C so the bits which are set are stable throughout the read
cycle. All bits which are high when read by the program are
cleared, and new interrupts (on any bits) are held until after
the read cycle. One, two, or three flag bits may be found to
be set when Register C is read. The program should inspect
all utilized flag bits every time Register C is read to insure
that no interrupts are lost.
The second flag bit usage method is with fully enabled
interrupts. When an interrupt-flag bit is set and the corresponding interrupt-enable bit is also set, the IRQ pin is
asserted low. IRQ is asserted as long as at least one of the
three interrupt sources has its flag and enable bits both set.
The IRQF bit in Register C is a "1" whenever the IRQ pin is
being driven low.
The processor program can determine that the RTC
initiated the interrupt by reading Register C. A "1" in bit 7
(lRQF bit) indicates that one or more interrupts have been
initiated by the part. The act of reading Register C clears all
the then-active flag bits, plus the IRQF bit. When the program finds IRQF set, it should look at each of the individual
flag bits in the same byte which have the corresponding
interrupt-mask bits set and service each interrupt which is
set. Again, more than one interrupt-flag bit may be set.

DIVIDER STAGES

The MC146818 has 22 binary-divider stages following the
time base as shown in Figure 1. The output of the dividers is
a 1 Hz Signal to the update-cycle logic. The dividers are controller by three divider bus (DV2, DV1, and DVm in Register
A.
DIVIDER CONTROL
The divider-control bits have three uses, as shown in Table
4. Three usable operating time bases may be selected
(4.194304 MHz, 1.048576 MHz, or 32.768 kHz). The divider
chain may be held reset, which allows precision setting of
the time. When the divider is changed from reset to an
operating time base, the first update cycle is one-half second
later. The divider-control bits are also used to facilitate
testing the MC146818.

3-1008

MC146818

TABLE 4 -

DIVIDER CONFIGURATIONS

Divider Bits
Register A

Time-Base
Frequency

Operation
Mode

Divider
Reset

Bypass First
N-Divider Bits

DV2

DV1

DVa

4.194304 MHz

0

0

0

Yes

-

N=O

1048576 MHz

0

0

1

Yes

-

N=2

32.768 kHz

0

1

0

Yes

-

N-7

Any

1

1

0

No

Yes

-

Any

1

1

1

No

Yes

-

Note: Other combinations of divider bits are used for test purposes only.

SQUARE-WAVE OUTPUT SELECTION

PERIODIC INTERRUPT SELECTION

Fifteen of the 22 divider taps are made available to a
1-of-15 selector as shown in Figure 1. The first purpose of
selecting a divider tap is to generate a square-wave output
signal at the SOW pin. The RSO-RS3 bits in Register A
establish the square-wave frequency as listed in Table 5. The
SOW frequency selection shares the 1-of-15 selector with
periodic interrupts.
Once the frequency is selected, the output of the SOW pin
may be turned on and off under program control with the
square-wave enable (SOWE) bit in Register B. Altering the
divider, square-wave output selection bits, or the SOWE
output-enable bit may generate an asymmetrical waveform
at the time of execution. The square-wave output pin has a
number of potential uses. For example, it can serve as a frequency standard for external use, a frequency synthesizer, or
could be used to generate one or more audio tones under
program control.

The periodic interrupt allows the IRO pin to be triggered
from once every 500 ms to once every 30.517 p,s. The
periodic interrupt is separate from the alarm interrupt which
may be output from once-per-second to once-per-day.
Table 5 shows that the periodic interrupt rate is selected
with the same Register A bits which select the square-wave
frequency. Changing one also changes the other. But each
function may be separately enabled so that a program could
switch between the two features or use both. The SOW pin
is enabled by the SOWE bit in Register B. Similarly the
periodic interrupt is enabled by the PI E bit in Register B.
Periodic interrupt is usable by practically all real-time
systems. It can be used to scan for all forms of inputs from
contact closures to serial receive bits or bytes. It can be used
in multiplexing displays or with software counters to measure inputs, create output intervals, or await the next needed
software function.

TABLE 5 -

RS3

PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY

Select Bits
Register A
RS2 RS1

32.768 kHz
4.194304 or 1.048576 MHz
Time Base
Time Base
Periodic
Periodic
Interrupt Rate SQW Output Interrupt Rate SQW Output
RSa
tpi
tPI
Frequency
Frequency
None
3.90625 ms

None

0

0

0

0

None

None

0

0

0

1

30.517 P.s

32.768 kHz

0

0

1

0

61.035 P.s

16.384 kHz

7.8125 ms

128 Hz

0

0

1

1

122070/1.s

8.192 kHz

122.070 P.s

8.192 kHz

0

1

0

0

244.141 P.s

4096 kHz

244.141 P.s

4096 kHz

0

1

0

1

488.281 P.s

2.048 kHz

488.281 P.s

2.048 kHz

0

1

1

0

976.562 P.s

1.024 kHz

976.562 P.s

1.024 kHz

0

1

1

1

1.953125 ms

512 Hz

1.953125 ms

512 Hz

1

0

0

0

3.90625 ms

256 Hz

3.90625 ms

256 Hz

1

0

0

1

7.8125ms

128 Hz

7.8125ms

128 Hz

1

0

1

0

15.625 ms

64 Hz

15.625 ms

64 Hz

1

0

1

1

31.25 ms

32 Hz

31.25 ms

32 Hz

1

1

0

0

62.5 ms

16 Hz

62.5 ms

16 Hz

1

1

0

1

125 ms

8 Hz

125 ms

8 Hz

1

1

1

0

250 ms

4 Hz

250 ms

4 Hz

1

1

1

1

500 ms

2 Hz

500 ms

2 Hz

3-1009

256 Hz

I

MC146818

UPDATE CYCLE

I

time needed to read valid time/ calendar data to exceed

The MC146818 executes an update cycle once-persecond, assuming one of the proper time bases is in place,
the DVO-DV2 divider is not clear, and the SET bit in Register
B is clear. The SET bit in the "1" state permits the program
to initialize the time and calendar bytes by stopping an existing update and preventing a new one from occurring.
The primary function of the update cycle is to increment
the seconds byte, check for overflow, increment the minutes
byte when appropriate and so forth through to the year of
the century byte. The update cycle also compares each
alarm byte with the corresponding time byte and issues an
alarm if a match or if a "don't care" code (11XXXXXX) is
present in all three positions.
With a 4.194304 MHz or 1.048576 MHz time base the update cycle takes 248 p's while a 32.768 kHz time base update
cycle takes 1984 p.s. During the update cycle, the time, calendar, and alarm bytes are not accessable by the processor
program. The MC146818 protects the program from reading
transitional data. This protection is provided by switching
the time, calendar, and alarm portion of the RAM off the
microprocessor bus during the entire update cycle. If the
processor reads these RAM locations before the update is
complete the output will be undefined. The update in progress (UIP) status bit is set during the interval.
A program which randomly accesses the time and date information finds data unavailable statistically once every 4032
attempts. Three methods of accommodating nonavailability
during update are usable by the program. In discussing the
three methods it is assumed that at random points user programs are able to call a subroutine to obtain the time of day.
The first method of avoiding the update cycle uses the
update-ended interrupt. If enabled, an interrupt occurs after
every update cycle which indicates that over 999 ms are
available to read valid time and date information. During this
time a display could be updated or the information could be
transfered to continuously available RAM. Before leaving the
interrupt service routine, the IRQF bit in Register C should be
cleared.
The second method uses the update-in-progress bit (UIP)
in Register A to determine if the update cycle is in progress
or not. The UIP bit will pulse once-per-second. Statistically,
the UIP bit will indicate that time and date information is
unavailable once every 2032 attempts. After the UIP bit goes
high, the update cycle begins 244 P.s later. Therefore, if a low
is read on the UIP bit, the user has at least 244 P.s before the
time/calendar data will be changed. If a "1" is read in the
UIP bit, the time/calendar data may not be valid. The user
should avoid interrupt service routines that would cause the

FIGURE 16 -

244 p.s.
The third method uses a periodic interrupt to determine if
an update cycle is in progress. The UIP bit in Register A is set
high between the setting of the PF bit in Register C (see
Figure 16). Periodic interrupts that occur at a rate of greater
than tBUC + tuc allow valid time and date information to be
read at each occurrence of the periodic interrupt. The reads
should be completed within (Tpi -<- 2) + tBUC to ensure that
data is not read during the update cycle.
To properly setup the internal counters for daylight savings time operation, the user must set the time at least two
seconds before the rollover will occur. Likewise, the time
must be set at least two seconds before the end of the 29th
or 30th day of the month.

REGISTERS
The MC146818 has four registers which are accessible to
the processor program. The four registers are also fully accessible during the update cycle.

REGISTER A ($OA)
Read/Write
Register
except UIP

UIP - The update in progress (UIP) bit is a status flag that
may be monitored by the program. When UIP is a "1" the
update cycle is in progress or will soon begin. When UIP is a
"0" the update cycle is not in progress and will not be for at
least 244 P.s (for all time bases). This is detailed in Table 6.
The time, calendar, and alarm information in RAM is fully
available to the program when the UIP bit is zero - it is not
in transition. The UIP bit is a read-only bit, and is not affected by Reset. Writing the SET bit in Register B to a "1"
inhibit any update cycle and then clear the UIP status bit.
TABLE 6

-

UPDATE CYCLE TIMES
Minimum Time
Update Cycle Time
Before Update
(tUC)
Cycle (tBUC)

UIP Bit

Time Base
(OSC1)

1

4.194304 MHz

248 p's

1

1.048576 MHz

248 p's

-

1

32.768 kHz

1984 p's

-

0

4.194304 MHz

-

244 P.s

0

1.048576 MHz

244 P.s

0

32.768 kHz

-

-

244 P.s

UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIPS

UIP bit In _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'~,.--------Register A
_ ~
tU

R~:,: :;Ce

PF bit in
Register C

'BUe

l

r--L..===_tP_1~~~~:.r-tPI+2
rmm. -1-~

tPI = Periodic Interrupt Time Interval (500 ms, 250 ms, 125 ms, 62.5 ms, etc. per Table 51
tUC= Update Cycle Time (248 P.s or 1984 p.sl
tBUC = Delay Time Before Update Cycle (244 /015)

3-1010

c

hnmww...._

tPI+2

________

MC146818

OV2, OV1, OVO - Three bits are used to permit the program to select various conditions of the 22-stage divider
chain. The divider selection bits identify which of the three
time-base frequencies is in use. Table 4 shows that time
bases of 4.194304 MHz, 1.048576 MHz, and 32.768 kHz may
be used. The divider selection bits are also used to reset the
divider chain. When the time/ calendar is first initialized, the
program may start the divider at the precise time stored in
the RAM. When the divider reset is removed the first update
cycle begins one-half second later. These three read/write
bits are not affected by R"ES'IT.
RS3, RS2, RS 1, RSO - The four rate selection bits select
one of 15 taps on the 22-stage divider, or disable the divider
output. The tap selected may be used to generate an output
square wave (SOW pin) and/ or a periodic interrupt. The program may do one of the following: 1) enable the interrupt
with the PIE bit, 2) enable the SOW output pin with the
SOWE bit, 3) enable both at the same time at the same rate,
or 4) enable neither. Table 5 lists the periodic interrupt rates
and the square-wave frequencies that may be chosen with
the RS bits. These four bits are read/write bits which are not
affected by RESET.
REGISTER 8 ($08)
Read/Write
Register

quency specified in the rate selection bits (RS3 to RSQ) appears on the SOW pin. When the SOWE bit is set to a zero
the SOW pin is held low. The state of SOWE is cleared by
the RESET pin. SOWE is a read/write bit.
OM - The data mode (OM) bit indicates whether time
and calendar updates are to use binary or BCD formats. The
DM bit is written by the processor program and may be read
by the program, but is not modified by any internal functions
or RESET. A "1" in DM signifies binary data, while a "0" in
DM specifies binary-coded-decimal (BCD) data
24/12 - The 24/12 control bit establishes the format of
the hours bytes as either the 24-hour mode (a "1 ") or the
12-hour mode (a "0"). This is a read/write bit, which is affected only by software.
OSE - The daylight savings enable lOSE) bit is a
read/write bit which allows the program to enable two
special updates (when DSE is a "1"). On the last Sunday in
April the time increments from 1:59:59 AM to 3:00:00 AM.
On the last Sunday in October when the time first reaches
159:59 AM it changes to 100:00 AM. These special updates
do not occur when the DSE bit is a "0". DSE is not changed
by any internal operations or reset.
REGISTER C ($OC)
r-M_S_B-.-_-._-'-_ _r-_~_~--:--,-~L~S:-1B Read-Only
Register

SET - When the SET bit is a "0", the update cycle functions normally by advancing the counts once-per-second.
When the SET bit is written to a "1", any update cycle in
progress is aborted and the program may initialize the time
and calendar bytes without an update occurring in the midst
of initializing. SET is a read/write bit which is not modified
by RESET or internal functions of the MC146818.

IROF - The interrupt request flag IIROF) is set to a "1"
when one or more of the following are true:
PF=PIE="l"
AF=AIE="l"
UF=UIE="l"

PIE - The periodic interrupt enable (PIE) bit is a
read/write bit which allows the periodic-interrupt flag (PF)
bit in Register C to cause the IRO pin to be driven low. A program writes a "1" to the PIE bit in order to receive periodic
interrupts at the rate specified by the RS3, RS2, RS1, and
RSO bits in Register A. A zero in PIE blocks IRO from being
initiated by a periodic interrupt, but the periodic flag (PF) bit
is still set at the periodic rate. PIE is not modified by any internal MC146818 functions, but is cleared to "0" by a
RESET.
AlE - The alarm interrupt enable (AlE) bit is a read/write
bit which when set to a "1" permits the alarm flag (AF) bit in
Register C to assert IRO. An alarm interrupt occurs for each
second that the three time bytes equal the three alarm bytes
(including a "don't care" alarm code of binary llXXXXXX).
When the AI E bit is a "0", the AF bit does not initiate an I RO
signal. The RESET pin clears AlE to "0". The internal functions do not affect the AlE bit.

i.e., IROF= PF·PIE+ AF.AIE+ UF·UIE
Any time the IROF bit is a "1", the IRO pin is driven low.
All flag bits are cleared after Register C is read by the program or when the RESET pin is low.
PF - The periodic interrupt flag (PF) is a read-only bit
which is set to a "1" when a particular edge is detected on
the selected tap of the divider chain. The RS3 to RSO bits
establish the periodic rate. PF is set to a "1" independent of
the state of the PIE bit. PF being a "1" initiates an IRO signal
and sets the IROF bit when PIE is also a "1". The PF bit is
cleared by a RESET or a software read of Register C.
AF - A "1" in the AF (alarm interrupt flag) bit indicates
that the current time has matched the alarm time. A "1" in
the AF causes the IRO pin to go low, and a "1" to appear in
the IROF bit, when the AlE bit also is a "1." A RESET or a
read of Register C clears AF.

UIE - The UIE (update-ended interrupt enable) bit is a
read/write bit which enables the update-end flag (UF) bit in
Register C to assert IRO. The RESET pin going low or the
SET bit going high clears the UIE bit.

UF - The update-ended interrupt flag (UF) bit is set after
each update cycle. When the UIE bit is a "1", the "1" in UF
causes the IROF bit to be a "1", asserting IRO. UF is cleared
by a Register C read or a RESET.

SOWE - When the square-wave enable (SOWE) bit is set
to a "1" by the program, a square-wave signal at the fre-

b3 TO bO - The unused bits of Status Register 1 are read
as "0' s". They can not be written.

3-1011

MC146818

REGISTER D ($OD)
MSB

processors. These interfaces assume that the address
decoding can be done quickly. However, if standard metalgate CMOS gates are used the CE setup time may be
violated. Figure 19 illustrates an alternative method of chip
selection which will accommodate such slower decoding.
The MC146818 can be interfaced to single-chip microcomputers (MCU) by using eleven port lines as shown in Figure
20. Non-multiplexed bus microprocessors can be interfaced
with additional support.
There is one method of using the multiplexed bus
MC146818 with non-multiplexed bus processors. The interface uses available bus control Signals to multiplex the
address and data bus together.
An example using either the Motorola MC6800, MC6802,
MC6808, or MC6809 microprocessor is shown in Figure 21.
Figure 22 illustrates the subroutines which may be used for
data transfers in a non-multiplexed system. The subroutines
should be entered with the registers containing the following
data:
Accumulator A: The address of the RTC to be accessed.
Accumulator B: Write: The data to be written.
Read: The data read from the RTC.
The RTC is mapped to two consecutive memory locations RTC and RTC + 1 as shown in Figure 21.

LSB

VRT - The valid RAM and time (VRT) bit indicates the
condition of the contents of the RAM, provided the power
sense (PS) pin is satisfactorily connected. A "0" appears in
the VRT bit when the power-sense pin is low. The processor
program can set the VRT bit when the time and calendar are
initialized to indicate that the RAM and time are valid. The
VRT is a read only bit which is not modified by the RESET
pin. The VRT bit can only be set by reading Register i:).

I

b6 TO bO - The remaining bits of Register D are unused.
Theycannot be written, but are always read as "a's."
TYPICAL INTERFACING
The MC146818 is best suited for use with microprocessors
which generate an address-then-data multiplexed bus.
Figures 17 and 18 show typical interfaces to bus-compatible

FIGURE 17 - MC146818 INTERFACED WITH
MOTOROLA COMPATIBLE MULTIPLEXED BUS MICROPROCESSORS

~8
""

......
Address/Data Multiplexed

8
--V

Address Strobe
Data Strobe IE)

~

MC6801
MCl46805E2

Read/Write IR/W)
Interrupt Request IIRQ)

Other
Peripherals
and
Memory

.....
8/5

Address

8/5

V

U

t
I

Address
Decode'

~
CE

I

~

It

V

IRQ R/W DS AS ADO-AD7

1l

RESET

LJ=l

MC146818

RESET
CKOUT

------------

__ J

'High-Speed SiliconGate CMOS or TTL
Address Decoding

3·1012

CKFS

i

SQW

1

4 . 194304
ITyp)

MHz

MC146818

FIGURE 18 - MC146818 INTERFACED WITH
COMPETITOR COMPATIBLE MULTIPLEXED BUS MICROPROCESSORS

r-.

A

~

8085

Address/ Data

8
v

Address Latch Enable IALE)
Read IR)

8048

Other
Peripherals
and Memory

WritelW)
Interrupt Request

8049

'+

8/4

Address

8~

U

Only

I\.

ii

8/4

V

4

Address
Decode

+ ,

CE

_J

V

IRQ R/W

DS

AS

ADO~AD7

~4.194

RESET
MC146818

RESET

JMHZ

304
lTyp)

SQW

1
FIGURE 19 - MC146818 INTERFACE WITH MC146805E2
CMOS MULTIPLEXED MICROPROCESSOR WITH SLOW ADDRESSING DECODING

-

Interrupt Request IIRQ)
Read/Write IR/W)

'"

Address Strobe lAS)
Data Strobe IDS)

T

MC146805E2
5
.A

(
OSC1

I

I
I
I

Non~Multlplexed

....

Address

5·7 Non·multlplexed address

~

I I I
8 Multiplexed Address/Data

~

U

II'"

IDS
A12

Address
Decode

~

I

I

I
I

DS

V
CE

~

AS R/W IRQ ADO·AD7

MC146818

RESET

I
I
I
I
'--

CKOUT CKFS

+11

1

VDD

ThiS illustrates the use of CMOS gating for address decoding

3-1013

SOW

1

rl.

IT

4.194304 MHz
I Typ)

•

MC146818

FIGURE 20 - MCl46818 INTERFACED WITH THE PORTS OF A
TYPICAL SINGLE CHIP MICROCOMPUTER

MC3870
MC6805
MC146805
S2OO0
8021

I

MC146818

(;

Address! Data

a..

(;

a..

ADO-AD7

Address Strobe
~----------------------~ AS
Read
r-------------------.... DS
Write

r - - - - - - - - - - - - - -....

R!W

SOW

CKFS

CKOUT

VSS

I
I
Port
Lines

I

L________ _

FIGURE 21 -

__...1

MCl46818 INTERFACED WITH MOTOROLA PROCESSORS

Active High Chip S e l e c t - - - - - - - - - - - - - .

DS
AO
MC146818
MC68oo,
MC6802,
MC6808,
or
MC6809

AS

R/W

R/W

00-07

AOO-AD7

VSS

3-1014

CE

MC146818

FIGURE 22 - SUBROUTINE FOR READING AND WRITING
THE MCl46818 WITH A NON-MULTIPLEXED BUS

READ

STA
LDAB
RTS

RTC
RTC+ 1

Generate AS and Latch Data from ACCA
Generate DS and Get Data

WRITE

STA
STAB
RTS

RTC
RTC+ 1

Generate AS and Latch Data from ACCA
Generate DS and Store Data

IMPORTANT NOTICES

Those devices made with date code 3N4GXXXX have the
fOllowing exceptions when used in the Motorola mode of
MOTEL.

1. VOO = 3 to 5.25 V for operation
2. OS VIL =0.6 V Max.
The falling edge of chip select should occur during the active high pulse of address strobe, only on those units with
date code GC6XXXX.

3-1015

I

®

MC146823

MOTOROLA
Advance Information

CMOS
IHIGH-DENSITY HIGH-PERFORMANCE
SILICON-GATE)

PARALLEL INTERFACE
CMOS PARALLEL INTERFACE

I

The MC146823 CMOS parallel interface (CPI) provides a universal
means of interfacing external signals with the MC146805E2 CMOS
microprocessor and other multiplexed bus microprocessors. The unique
MOTEL circuit on-chip allows direct interfacing to most industry CMOS
microprocessors, as well as many NMOS MPUs.
The MC146823 CPI includes three bidirectional 8-bit ports or 241/0
pins. Each 1/0 line may be separately established as an input or an output under program control via data direction registers associated with
each port. Using the bit change and test instructions of the
MC146805E2, each individual 1/0 pin can be separately accessed. All
port registers are readlwrite bytes to accommodate read-modify-write
instructions. Features include:
•
•

24 Individually Programmed 1/0 Pins
MOTEL Circuit for Bus Compatibility with Many Microprocessors

•

Multiplexed Bus Compatibility with: MC146805E2, MC6801, MC6803,
and Competitive Microprocessors

•

Data Direction Registers for Ports A, B, and C

•

Four Port CliO Pins May Be Used as Control Lines for:
Four Interrupt Inputs
Input Byte Latch
Output Pulse
Handshake Activity

•
•

15 Registers Addressed as Memory Locations
Handshake Control Logic for Input and Output Peripheral Operation

•
•

Interrupt Output Pin
Reset Input to Clear Interrupts and Initialize Internal Registers

•

3.0 Volt to 5.5 Volt Operating VDD

PIN ASSIGNMENT
PC2

VDD

PCl

39

PC3

peo

38

PC4/CAl

PAO

37

PC5/CA2
PC6/CBl

PAl
35

PA2

PBO

PA4

33

PBl

PA5

32

PB2

31
PA7

11

ADl

13

ORDERING INFORMATION
Package Type
Plastic -

P Suffix

PB3
PB4

29

PB5

14

MC146823P

Ceramic ISide Brazed) Cerdip -

12
Order Number

PC7/CB2

34

L Suffix

S Suffix

Chip Carrier - Z Suffix

MC146823L
MC146823S

16

MC146823Z

17
18
19
20
Pin assignments are the same tor both the dual-Inline and chip carrier package.

This document contains information on

Ci

new product Specifications and Inlormrltron herein

are subject to change without notice

3-1016

MC146823

BLOCK DIAGRAM

PAO
PAl
PA2
PA3
PA4
PA5
ADO

PA6

ADl

PA7

AD2
AD3
AD4
AD5

PBO

AD6

PBl

AD7

PB2
PB3
PB4
PB5

Bus
Input
Register

PB6
PB7

IRQ

AS
OS
R/W

Control
Inputs

RESET

CE
VDD
VSS

,.•

PCO
PCl
Port
C

1/0

PC2
PC3
PC4/CAl
PC5/CA2
PC6/CBl
PC7/CB2

3-1017

I

MC146823

MAXIMUM RATINGS (Voltages reference to VSSI
Ratings

Symbol

Value

Unit

VOO

-0.3 to +8.0

V

Vin

VSS-0.5 to VOO+0.5

V

10

mA
DC

Supply Voltage
All Input Voltages
Current Drain per Pin Excluding
VOD and VSS
Operating Temperature Range

I

o to

TA
Tstg

Storage Temperature Range

+ 70

- 55 to + 150

DC

THERMAL CHARACTERISTICS
Characteristics

Symbol

Value

Unit

{)JA

50
100
60
TBO

DC/W

Thermal Resistance
Ceramic
Plastic
Cerdip
Chip Carrier

I

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ~ (Vin or Voutl ~ VOO·
Leakage currents are reduced and reliability of
operation is enhanced if unused inputs are tied to
an appropriate logic voltage level (e.g., either
VSS or VOOI.

D
DC ELECTRICAL CHARACTERISTICS (VOO = 5 Vdc +
- 10%, VSS = 0 Vdc, T A = ODC to 70 C, unless otherwise notedl
Parameter

Symbol

Min

Max

Unit

VOL
VOH

-

0.1

VOO-O.l

-

V
V

Output High Voltage
IILoad= -1.6 mAl AOO-A07
IILoad= -0.2 mAl PAO-PA7, Peo-PC7
IILoad= -0.36 mAl PBO-PB7

VOH
VOH
VOH

4.1
4.1
4.1

VOO
VOO
VOO

V

Output Low Voltage
(ILoad=1.6 mAl AOO-A07, PBO-PB7
IILoad=0.8 mAl PAO-PA7, PCO-PC7
(ILoad=1.0 mAl iRO

VOL
VOL
VOL

0.4
0.4
0.4

V

VIH
VIH

VSS
VSS
VSS
VOO-2.0
VOO-0.8

Output Voltage IILoad:510 p.A)

Input High Voltage, AOO-A07, AS, OS, R/W, CE, PAO-PA7, PBO-PB7, PCO-PC7
RESET
Input Low Voltage (All Inputs)

V

VIL

VSS

VOO
VOO
0.8

Quiescent Current - No dc Loads
(All Ports Programmed as Inputs, All Inputs= VOO - 0.2 VI

100

-

160

p.A

Total Supply Current
(All Ports Programmed as Inputs, CE = VIL, tcyc= 1 /Ls)

100

-

3.0

mA

lin

-

p.A

ITSL

-

± 10
± 10.0

Input Current, CE, AS, R/W, OS, RESET
Hi-Z State Leakage, AOO-A07, PAO-PA7, PBO-PB7, Peo-PC7

V

/LA

EQUIVALENT TEST LOADS

VOO
TTL Equivalent

CMOS Equivalent
MM06150
or Equiv.

Test o--~t------4'---Hlf---'"
POint

C

C=50 pF; All Ports
= 130 pF; AOO-A07
for VOO=5 V ± 10%

MM07000
or Equiv

Pin
AOO-A07

Rl
2.55k

R2

TestPoint~

For all outputs except IRQ

C

2.0k

130 pF

PAO-PA7, Peo-PC7

20.0k

4.32k

50 pF

PBO-PB7

11.5k

2.1k

50 pF

1

I

C

-=-

402 k

90 pF

3.. 1018

MC146823

BUS TIMING (VDD= 5 Vdc +
- 10%, VSS = 0 Vdc, T A =0° to 70°C, unless otherwise noted)
Ident.
Number

Characteristics

Symbol

Min

Max

Unit

tcyc

1000

dc

ns

Pulse Width, DS/E Low or RTI/WR High

PWEL

300

-

ns

PWEH

325

-

ns

4

Pulse Width, DS/E High or RD/WR Low
Input Rise and Fall Time

30

ns

8

R/W Hold Time

tRWH

10

-

ns

13

R/W and CE Setup Time Before US/E

tRWS

25

-

ns

15

Chip Enable Hold Time

tCH

0

-

ns

18

Read Data Hold Time

tDHR

10

100

ns

21

Write Data Hold Time

tDHW

0

-

ns

24

Muxed Address Valid Time to ASI ALE Fall

tASL

25

-

ns

25

Muxed Address Hold Time

tAHL

20

-

ns

26

Delay Time DSI E to ASI ALE Rise

tASD

60

-

ns

27

Pulse Width, ASI ALE High

PWASH

170

-

ns

-

ns

1

Cycle Time

2
3

tr,tf

-

28

Delay Time, ASI ALE to DSI E Rise

tASED

60

30

Peripheral Output Data Delay Time from DS/E or RD

tDDR

20

240

ns

31

Peripheral Data Setup Time

tDSW

220

-

ns

NOTE: DeSignations E, ALE, RD, and WR refer to signals from alternative microprocessor signals.

BUS TIMING DIAGRAM

AS

DS

R;"W

ADOAD7
WRITE

ADOAD7
READ
NOTE: VHIGH = VDD - 2.0 V, VLOW = 0.8 V, for VDD = 5.0 V ± 10%

3-1019

I

MC146823

BUS READ TIMING COMPETITOR MULTIPLEXED BUS

ALE (Address Latch Enable)

(AS Pin)

RD (Read Output Enable)

(oS Pin)

WR (Write Enable)

(R/W Pin)

II

CE

(Chip Enable)

ADO-AD?
(Address/Data B_u.;..S)_ _ _ _ _ _ _ _ _ _ _

-<

BUS WRITE TIMING COMPETITOR MULTIPLEXED BUS

ALE (Address Latch Enable)

(AS Pin)

R5

(Read Output Enable)

(oS Pin)

WR (Write Enable)

(R/W Pin)

CE(ChipE_n_a_bl_e)_ _ _~~~~~~~~~~~~~~~~¥-

ADO-AD?
(Address/ Da,;;"a.;;B.;;u,;.;s)_ _ _ _ _ _ _ _ _ _ _

-<

____________~~~~~~~_

Write Data
Valid

NOTE: VHIGH=VDD-20 V, VLOW=08 V, for VDD=50 V ± 10%

3·1020

MC146823

CONTROL TIMING

(VDD=50Vdc +10%
VSS=OVdc TA=O°Ct070°C)
-

Parameter

Symbol

Min

tlRQR

TBD

-

P.s

Delay, CAl (CB1) Active Transition to CA2 (CB2) High (Output Mode 01

tC2

TBD

-

P.s

Delay, CA2 Transition from Positive Edge of AS (Output Modes 0 and 1)

tA2

TBD

-

P.s

Delay, CB2 Transition from Negative Edge of AS (Output Modes 0 and 1)

tB2

TBD

-

P.s

CA2/CB2 Pulse Width (Output Mode 1)

tpw

TBD

TBD

ns

Delay, VDD Rise to RESET High

tRLH

TBD

-

P.s

Pulse Width, RESET

tRW

TBD

-

ns

Interrupt Response (Input Modes 1 and 3)

Max

Unit

TBD=To be determined.

CONTROL TIMING DIAGRAMS

CA2/CB2 DELAY (OUTPUT MODE 1)

IRQ RESPONSE (INPUT MODES 1 AND3)

r

CAl
CA2
AS

CA2/CB2
CA2/CB2 DELAY (OUTPUT MODE 01

CA1/CBl

X _____________
~

tC2

CA2/CB2

AS

3-1021

Read Pl DA/Write Pl DB Cycle

I

MC146823

GENERAL DESCRIPTION
The MC146823, CMOS parallel interface (CPI), contains 24
individual bidirectional I/O lines configured in three 8-bit
ports. The 15 internal registers, which control the mode of
operation and contain the status of the port pins, are accessed via an 8-bit multiplexed address/data bus. The lower four
address bits (ADO-AD3) of the multiplexed address bus
determine which register is to be accessed (see Figure 1).
The four address bits (AD4, AD5, AD6, and AD7) must be
separately decoded to position this memory map within each
256 byte address space available via the 8-bit multiplexed
address bus. For more detailed information refer to
REGISTER DESCRIPTION.
FIGURE 1 -

o

I

4

A
C

REGISTER ADDRESS MAP

PlDA

Port A Data, Clear CA 1 Interrupt
Port A Data, Clear CA2 Interrupt

P2DA

Port A Data

PDA

Port B Data

PDB

Port C Data

PDC

Not Used

-

Data Direction Register for Port A

DDRA

Data Direction Register for Port B

DDRB

Data Direction Register for Port C

DDRC

Control Register for Port A

CRA

Control Register for Port B

CRB

Pin Function Select Register for Port C

FSR

Port B Data, Clear CBl Interrupt

PlDB
P2DB

D Port B Data, Clear CB2 Interrupt
Handshake/lnterrupt Status Register

HSR

Handshake Over-Run Warning Register

HWR

The CPI is implemented with the MOTEL circuit which
allows direct interface with either of the two major multiplexed microprocessor bus types. A detailed description of
the MOTEL circuit is provided in the MOTEL section.
FIGURE 2 -

Motorola Type
MPU Signals

Competitor Type
MPU Signals

Three data direction registers (DDRs), one for each port,
determine which pins are outputs and which are inputs. A
logic zero on a DDR bit configures its associated pin as an inand a logic one configures the pin as an output. Upon
reset, the DDRs are cleared to logic zero to configure all port
pins as inputs.
Actual port data may be read or written via the port data
registers (PDA, PDB, and PDC)' Ports A and B each have
two additional data registers (P1DA and P2DA - P1 DB and
P2DB) which are used to clear the associated handshake/
interrupt status register bits (HSA1 and HSA2 - HSB1 and
HSB2), respectively. Port A may also be configured as an
8-bit latch when used with CA 1. Reset has no effect on the
contents of the port data registers. Users are advised to
initialize the port data registers before changing any port pin
to an output.
Four pins on port C (PC4/CA1, PC5/CA2, PC6/CB1, and
PC7!CB2) may additionally be programmed as handshake
lines for ports A and B via the port C function select register
(FSR). Both ports A and B have one input-only line and one
bidirectional handshake line each associated with them. The
handshake lines may be programmed to perform a variety of
tasks such as interrupt requests, setting flags, latching data,
and data transfer requests and/or acknowledgements. The
handshake functions are programmed via control registers A
and B (CRA and CR B). Additional information may be found
in PIN DESCRIPTIONS, REGISTER DESCRIPTION, or
HANDSHAKE OPERATION.

put;

MOTEL
The MOTEL circuit is a concept that permits the
MC146823 to be directly interfaced with different types of
multiplexed bus microprocessors without any additional
external logic. For a more detailed description of the multiplexed bus, see MULTIPLEXED BIDIRECTIONAL ADDRESS/DATA BUS (ADO-AD7). Most multiplexed microprocessors use one of two synchronous buses to interface
peripherals. One bus was originated by Motorola in the
MC6803 and the other by Intel in the 8085.
The MOTEL circuit (for MOTorola and intEL bus) is built
into peripheral and memory ICs to permit direct connection
to either type of bus. A functional diagram of the MOTEL circuit is shown in Figure 2.

FUNCTIONAL DIAGRAM OF MOTEL CIRCUIT

MC146823
Pin Signals

Competitive Bus
D

AS

ALE

AS

C
Q

DS, E, or2

R/W

Rl5

Internal
Signals

Q

Motorola
Bus

DS

Read Enable

R/W

Write Enable

3-1022

MC146823

The microprocessor type is automatically selected by the
MOTEL circuit through latching the state of the DS/RD pin
with AS/ ALE. Since DS is always low during AS and RD is
always high during ALE, the latch automatically indicates
with which type microprocessor bus it is interfaced.

READ/WRITE (R/W)
The MOTEL circuit treats the R/W input pin in one of two
ways. First, when a Motorola microprocessor is connected,
R/W is a level which indicates whether the current cycle is a
read or write. A read cycle is indicated with a high level on
R/IN while DS is high, whereas a write cycle is a low on
R/IN while OS is high.
The second interpretation of R/W is as a negative write
pulse, WR, MEMW, and I/OW from competitor's microprocessors. The MOTEL circuit in this mode gives the R/W pin
the same meaning as the write (IN) pulse on many generic
RAMs.

PIN DESCRIPTIONS
The following paragraphs contain a brief description of the
input and output pins. References (if applicable) are given to
other paragraphs that contain more detail about the function
being performed.

CHIP ENABLE (CE)
The CE input signal must be asserted (low) for the bus
cycle in which the MC146823 is to be accessed. EE is not
latched and must be stable prior to and during OS (in the
Motorola case of MOTEl) and prior to and during RD and
WR (in the other MOTEL case). Bus cycles which take place
without asserting EE cause no actions to take place within
the MC146823. When EE is high, the multiplexed bus output
is in a high-impedance state.
When EE is high, all data, DS, and R/W inputs from the
microprocessor are disconnected within the MC146823. This
permits the MC146823 to be isolated from a powered-down
microprocessor.

MULTIPLEXED BIDIRECTIONAL ADDRESS/DATA BUS
(ADO-AD7)
Multiplexed bus processors save pins by presenting the
address during the first portion of the bus cycle and using
the same pins during the second portion of the bus cycle for
data. Address-then-data multiplexing does not slow the
access time of the MC146823 since the bus reversal from
address to data is occurring during the internal register
access time.
The address must be valid tASL prior to the fall of
AS/ ALE at which time the MC146823 latches the address
present on the ADO-AD3 pins. Valid write data must be
presented and held stable during the latter portion of the DS
or WR pulses. In a read cycle, the MC146823 outputs eight
bits of data during the latter portion of the DS or RD pulses,
then ceases driving the bus (returns the output drivers to
high impedance) tDHR hold time after DS falls in the
Motorola case of MOTEL or RD rises in the other case.

RESET (RESET)
The RESET input pin is an active-low line that is used to
restore all register bits, except the port data register bits, to
logical zeros. After reset, all port lines are configured as inputs and no interrupt or handshake lines are enabled.

ADDRESS STROBE (AS)

INTERRUPT REQUEST (iRO)
The IRQ output line is an open-drain active-low signal that
may be used to interrupt the microprocessor with a service
request. The "open-drain" output allows this and other
interrupt request lines to be wire ORed with a pullup resistor.
The IRQ line is low when bit 7 of the status register is high.
Bit 7 (IRQF) of the handshake/interrupt status register
(HSR) is set if any enabled handshake transition occurs; and
its associated control register bit is set to allow interrupts.
Refer to INTERRUPT DESCRIPTION or HANDSHAKE
OPERATION for additional information.

The address strobe input pulse serves to demultiplex the
bus. The falling edge of AS or ALE causes the addresses
ADO-AD3 to be latched within the MC146823. The automatic
MOTEL circuit in the MC146823 also latches the state of the
DS pin with the falling edge of AS or ALE.
DATA STROBE OR READ (DS)
The DS input pin has two interpretations via the MOTEL
circuit. When generated by a Motorola microprocessor, DS
is a positive pulse during the latter portion of the bus cycle,
and is variously called DS (data strobe), E (enable), or phase
2 (phase 2 clock). During read cycles, DS or RD signifies the
time that the CPI is to drive the bidirectional bus. In write
cycles, the trailing edge of OS or rising edge of WR causes
the parallel interface to latch the written data present on the
bidirectional bus.
The second MOTEL interpretation of DS is that of RD,
MEMR, or I/OR originating from the competitor's microprocessor. In this case, OS identifies the time period when the
parallel interface drives the bus with read data. This interpretation of DS is also the same as an output-enable signal
on a typical memory.
The MOTEL circuit, within the MC146823, latches the
state of the DS pin on the falling edge of AS/ ALE. When the
Motorola mode of MOTEL is desired DS must be low during
AS/ ALE, which is the case with the Motorola multiplexed
bus microprocessors. To insure the competitor mode of
MOTEL, the DS pin must remain high during the time AS/
ALE is high.

PORT A, BIDIRECTIONAL I/O LINES (PAO-PA7)
Each line of port A, PAO-PA7, is individually programmable as either an input or output via its data direction
register (DDRA). An I/O pin is an input when its corresponding DDR bit is a logic zero and an output when the DDR bit is
a logic one. See Figure 3 for typical I/O circuitry and Table 1
for I/O operation.
There are three data registers associated with port A:
PDA, P1 DA, and P2DA. P1 DA and P2DA are accessed when
certain handshake activity is desired. See HANDSHAKE
OPERATION for more information.
Data written to the port A data register, PDA, is latched
into the port A output latch regardless of the state of the
DDRA. Data written to P1 DA or P2DA is ignored and has no
affect upon the output data latch or the I/O lines. An MPU
read of port bits programmed as outputs reflect the last value
written to the PDA register. Port A pins programmed as inputs may be latched via the handshake line PC4/ CA 1 (see

3-1023

I

MC146823

FIGURE 3 - TYPICAL PORT 1/0 CI.RCUITRY

To
And
From

CPU

I

TABLE 1 - PORT DATA REGISTER ACCESSES (ALL PORTS)

R/lii
0
0

1
1

DDR
Bit
Results
0 The I/O pin is in input mode. Data is written into the
output data latch.
1 Data is written into the output data latch and output to the I/O pin.
0 The state of the I/O pin is read.
1 The I/O pin is in an output mode. The output
data latch is read.

HANDSHAKE OPERATION) and latched input data may be
read via any of the three port A data registers. If the port A
input latch feature is not enabled, an MPU read of any port A
data register reflects the current status of the port A input
pins if the corresponding DDRA bits equal zero. Reset has
no effect upon the contents of the port A data register;
however, all pins will be placed in the input mode (all DDRA
bits forced to equal zero) and all handshake lines will be
disabled.
PORT B BIDIRECTIONAL I/O LINES (PBO-PB7)
Each line of port B, PBO-PB7, is individually programmable
as either an input or an output via its data direction register
(DDRBI. An I/O pin is an input when its corresponding DDR
bit is a logic zero and an output when the DDR bit is a logic
one.
There are three data registers associated with port B:
PDB, P1DB, and P2DB. PDB is used for simple port B data
reads and writes. Pl DB and P2DB are accessed when certain
handshake activity is desired. See HANDSHAKE OPERATION for more information.
. is-ata written to PDB or P1DB data register is latched into
the port B output latch regardless of the state of the DDRB.
An MPU read of port bits programmed as outputs reflect the
last value written to a port B data register. An MPU read of
any port B register reflects the current status of the input
pins whose DDRB bits equal zero. Reset has no effect upon
the contents of the port B data register; however, all pins will
be placed in the input mode (all DDRB bits forced to equal
zero) and all handshake lines will be disabled.

PORT C, BIDIRECTIONAL I/O LINES (PCO-PC3)
Each line of port C, PCO-PC3, is individually programmable
as either an input or an output via its data direction register
(DDRC). An I/O pin is an input when its corresponding DDR
bit is a logic zero and an output when the DDR bit is a logic
one. Port C data register (PDC) is used for Simple port C data
reads and writes.
Data written into PDC is latched into the port C data latch
regardless of the state of the DDRC. An MPU read of port C
bits programmed as outputs reflect the last value written to
the PDC register. An MPU read of the port C register reflects
the current status of the corresponding input pins whose
DDRC bits equal zero. Reset has no effect upon the contents
of the port C data register; however, all pins will be placed in
the input mode (all DDRC bits forced to equal zero) and all
handshake lines will be disabled.
PORT C BIDIRECTIONAL I/O LINE OR PORT A INPUT
HANDSHAKE LINE (PC4/CA1)
This line may be programmed as either a simple port C I/O
line or as a handshake line for port A via the port C function
select register (FSR). If programmed as a port C I/O pin,
PC4/ CA 1 performs as described in the PCO-PC3 pin description. If programmed as a port A handshake line, PC4/ CA 1
performs as described in HANDSHAKE OPERATION.
PORT C BIDIRECTIONAL I/O LINE OR PORT A
BIDIRECTIONAL HANDSHAKE LINE (PC5/CA2)
This line may be programmed as either a simple port C I/O
line or as a handshake line for port A via the port C function
select register (FSR). If programmed as a port C I/O pin,
PC5/CA2 performs as described in the PCO-PC3 pin description. If programmed as a port A handshake line, PC5/CA2
performs as described in HANDSHAKE OPERATION.
PORT C BIDIRECTIONAL I/O LINE OR PORT B INPUT
HANDSHAKE LINE (PC6/CB1)
This line may be progra·mmed as either a simple port C I/O
line or as a handshake line for port B via the port C function
select register (FSR). If programmed as a port C I/O pin,
PC6/CBl performs as described in the PCO-PC3 pin description. If programmed as a port B handshake line, PC6/CBl
performs as described in HANDSHAKE OPERATION.

3-1024

MC146823

PORT C BIDIRECTIONAL I/O LINE OR PORT B
BIDIRECTIONAL HANDSHAKE LINE (PC7/CB2)

A summary of the handshake modes is given in the input
and output sections that follow. All handshake activity is
disabled by reset.

This line may be programmed as either a simple port C I/O
line or as a handshake line for port B via the port C function
select register (FSR). If programmed as a port C I/O line,
PC7/ CB2 performs as described in the PCO-PC3 pin description. If programmed as a port B handshake line, PC7/CB2
performs as described in HANDSHAKE OPERATION.

INPUT
Handshake lines programmed as inputs operate in any of
four different modes as defined by the control registers (see
Table 2). A bit in the handshake/interrupt status register
(H S R) is set to a logic one on an active transition of any
handshake line programmed as an input. Modes 0 and 1
define a negative transition as active; modes 2 and 3 define a
positive transition as active. If modes 1 or 3 are selected on
any input handshake line then the active transition of that
line results in the IRQF bit of the HSR being set to a logic one
and causes the interrupt line (IRQ) to go low. IRQ is released
by clearing the HSR bits that are input handshake lines
which have interrupts enabled.
If an active transition occurs while the associated HSR bit
is set to a logic one, the corresponding bit in the handshake
warning register (HWR) is set to a logic one indicating that
service of at least one active transition was missed. An HWR
bit is cleared to a logic zero by first accessing the appropriate
port data register, to clear the appropriate H S R status bit,
followed by a read of the HWR.

HANDSHAKE OPERATION
Up to four port C pins can be configured as handshake
lines for ports A and B (one input-only and one bidirectional
line for each port) via the port C function select register
(FSR). The direction of data flow for the two bidirectional
handshake lines (CA2 and CB2) is determined by bits 5 and
7, respectively, of the port C data direction register mDRC).
Actual handshake operation is defined by the appropriate
port control register (CRA or CRB).
The control registers allow each handshake line to be programmed to operate in one of four modes. CA2 and CB2
each have four input and four output modes. For detailed information, see Tables 2 and 3.

TABLE 2 - INPUT HANDSHAKE MODES
Control
Mode Register Bits*

Active
Edge

Status Bit
In HSR

IRQ Pin

0

00

- Edge

Set high on
active edge

Disabled

1

01

- Edge

Set high on
active edge.

Goes low when corresponding
status flag in H SR goes high

2

10

+ Edge

Set high on
active edge.

Disabled

3

11

+ Edge

Set high on
active edge

Goes low when corresponding
status flag in HSR goes high.

* Cleared to logiC zero on reset.
TABLE 3 -

Mode

Control
Register
eRA(B)
Bits
3 and 4*

0

00

1

01

2

10
11

3

* Cleared

OUTPUT HANDSHAKE LINES (CA2 AND CB2 ONLY)

Handshake Line Cleared Low

Default
Level

Handshake Line Set High
Handshake set high on active
transition of CAl input.

Read of P1DA or a read of P2DA
while HSA 1 is cleared.

Handshake set high on active
transition of CB 1 input.

Write of port B P1 DB or write
of P2DB while HSB1 is cleared.

High on the first positive
(negative) transition of AS
while CA2 (CB2) is low.

Low on the first positive
(negative) transition on AS following a read (write) of port
A(B) data registers P1DA(B) or
P2DA(BI.

High

Never
Always

Always
Never

Low
High

to logiC zero on reset.

3-1025

High

I

MC146823

I

INPUT LATCH
Port A input-only handshake line (PC4/CA1) can be programmed to function as a latch enable for port A input data
via CAl LE (bit 2 of CRA). If CAl LE is programmed to a
logic one, an active transition of PC4/ CA 1 will latch the current status of the port A input pins into all three port A data
registers (PDA, Pl DA, and P2DA). When CA 1 LE is enabled,
port A and PC4/ CA 1 function as an 8-bit transparent latch;
that is, if the HSA 1 bit in the HSR is a logic zero then a read
of any port A register reflects the current state of the port A
input pins and corresponding bits of the output data latch for
port A output pins. If HSA 1 is a logic one, a read of any port
A data register reflects the state of the port A input pins
when HSA 1 was set and the corresponding bits of the port A
output data latch for port A output pins.
Further transitions of PC4/ CA 1 result only in setting the
HWA 1 bit in the HWR and do not relatch data into the port A
registers. Latched data is released only by clearing HSA 1 in
the HSR to a logic zero (HSAl is cleared by reading P1DA).
OUTPUT
Each bidirectional handshake line programmed as an output by the DDRC operates in one of four modes as described
in Table 3. Modes 2 and 3 force the output handshake line to
reflect the state of bit 4 in the appropriate control register.
In modes and 1, PC5/CA2 is forced low during the cycle
following a read of Pl DA or a read of P2DA while HSA 1 is
cleared. PC7/CB2 is forced low during the cycle following a
write to PlDB or a write to P2DB while HSBl is cleared.
Because of these differences, port A is the preferred input
port and port B is the preferred output port.
In mode 0, PC5/CA2 (PC7/CB2) is set high by an active
transition of PC4/CAl (PC6/CB1). In mode 1, PC5/CA2
(PC7/CB2) is set high in the cycle following the cycle in
which PC5/CA2 (PC7/CB2) goes low. Mode 1 forces a lowgoing pulse on PC5/ CA2 (PC7 / CB2) following a read (write)
of PlDA (PlDB) or P2DA (P2DB) that is approximately one
cycle time wide.
When entering an output handshake mode for the first
time after a reset, the handshake line outputs the default
level as listed in Table 3.

°

INTERRUPT DESCRIPTION
The MC146823 allows an MPU interrupt request (IRQ low)
via the input handshake lines. The input handshake line,
operating in modes 1 or 3 as defined by the control registers

(CRA and CRB), causes iRO to go low when IRQF (interrupt
flag) in the HSR is set to a logic one. fl1(} is released when
iRQF is cleared. See Handshake/Interrupt Status Register
under REGISTER DESCRIPTION for additional information.

REGISTER DESCRIPTION
The MC146823 has 15 registers (see Figure 1) which define
the mode of operation and status of the port pins. The
following paragraphs describe these registers.

Register Names:
Control Register A (CRA)
Control Register B (CRB)
Register Addresses:
$9 (CRA)
$A (CRB)
Register Bits:

$9

x

X

X

$A

X

X

X

CA2
Mode

CB2
Mode

CAl
LE
X

CAl
Mode

CBl
Mode

Purpose:
These two registers control the handshake and interrupt
activity for those pins defined as handshake lines by the
port C function select register (FSR).

Description:
CA2 and CB2 are programmed as inputs or outputs via the
associated DDRC bits. Each handshake line is controlled
by two mode bits. Bit 2 of CRA enables the Port A latch
for an active CA 1 transition. Table 2 describes the input
handshake modes (CAl, CB1, CA2, CB2) and Table 3
describes the output handshake modes for CA2 and CB2.

3-1026

MC146823

Register Names:
Port A Data Registers (PDA, PlDA, P2DA)

Register Names:
Port B Data Registers (PDB, P1 DB, P2DB)

Register Addresses:
$2 (PDA), $0 (PlDA), $1 (P2DA)

Register Addresses:
$3 (PDB), $C(PlDB), $D (P2DB)

Register Bits:
Register Bits:

I Bit 7 I Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

I Bit 0 I
Bit 7

Purpose:
These three registers serve different purposes. PDA is
used to read input data and latch data written to the port A
output pins. P1 DA and P2DA are used to read input data
and to affect handshake and status activity for PC4/ CA 1
and PC5/CA2. If enabled, port A input data may be latched into the three port A data registers on an active
PC4/ CA 1 transition as described in HANDSHAKE
OPERATION.

Bit 6

Bit 5

Bit 4

Bit 3

Bit 0

I

Description:
Data written into PDB and PlDB port B registers is latched
into the port B output latch (see Figure 3) regardless of the
state of DDRB. Output pins, as defined by DDRB, assume
the logic levels of the corresponding bits in the port B output latch. Reads of any port B data registers reflect the
contents of the output data latch for output pins and the
current state of the input pins (as determined by DDRBl.
Users are recommended to initialize the port B output
latch before changing any pin to an output via the DDRB.
MPU accesses of PlDB or P2DB are primarily used to affect handshake and status activity. A summary of the effects on status and warning register bits of port B data
register accesses is given in Table 5. For more information,
see HANDSHAKE OPERATION or Control Register B
(CRB) under REGISTER DESCRIPTION. Reset has no effect upon the contents of any port B data register.

MPU accesses of PlDA or P2DA are primarily used to affect handshake and status activity. A summary of the effects on the status and warning bits of port A data register
accesses is given in Table 4. For more information, see
HANDSHAKE OPERATION and Control Register A (CRA)
under REGISTER DESCRIPTION. Reset has no effect
upon the contents of any port A data register.

TABLE 4 - SUMMARY OF EFFECTS ON HANDSHAKE STATUS, WARNING BITS,
AND OUTPUT LATCH BY PORT A DATA REGISTER ACCESSES
Output Latch
HSR Bit

Bit 1

Purpose:
These three registers serve different purposes. The Port B
data registers are used to read input data and to latch data
written to the port B output pins. Writes to PDB and P1 DB
affect the contents of the output data latch while writes to
P2DB do not affect the output data latch. P1 DB and P2DB
accesses additionally affect handshake and status activity
for PC6/CB1 and PC7/CB2.

Description:
Data written into PDA is latched into the port A output
latch (see Figure 3) regardless of the state of DDRA. Output pins, as defined by DDRA, assume the logic levels of
the corresponding bits in the PDA output latch. The PDA
output latch allows the user to read the state of the port A
output data. If the input latch is not enabled, a read of any
port A data register reflects the current state of the port A
input pins as defined by DDRA and the contents of the
output latch for output pins. Writes into P1 DA or P2DA
have no effect upon the output pins or the output data
latch. Users are recommended to initialize the port A output latch before changing any pin to an output via the
DDRA.

Register
Accessed

Bit 2

HWR Bit

Handshake Reaction

Read

Write

PDA

None

None

None

Yes

Yes

P1DA

HSA 1 cleared
to a logic
zero.

HWAl loaded
into buffer
latch.

CA2 goes low if output modes
o or 1 are selected in the eRA.

Yes

No

P2DA

HSA2 cleared
to a logic
zero.

HWA2 loaded
into buffer
latch.

CA2 goes low if output modes
in the CRA

Yes

No

o or 1 are selected

3-1027

I

MC146823

TABLE 5 - SUMMARY OF EFFECTS ON HANDSHAKE STATUS, WARNING BITS,
AND OUTPUT LATCH BY PORT B DATA REGISTER ACCESSES
Register
Accessed

Output Latch
HSR Bit

Handshake Reaction

HWR Bit

None

None

None

Yes

Yes

P1DB

HSBl cleared
to a logic
zero.

HWBl loaded
into buffer
latch.

CB2 goes low if output modes
or 1 are selected in the CRB

Yes

Yes

o

HSB2 cleared
to a logic
zero.

HWA2 loaded
into buffer
latch.

CB2 goes low if output modes
in CRB.

Yes

No

o or 1 are selected

Register Name:
Port C Data Register (POC)
Register Address:
$4
Register Bits:

7

6

I Bit 7 I Bit 6

4

Bit 5

Write

PDB

P2DB

II

Read

I Bit 4 I Bit 3

Bit 2

Bit 1

Bit 0

I

Description:
A logic zero in a DOR bit places the corresponding port pin
in the input mode. A logic one in a DDR bit places the corresponding pin in the output mode. Any port C pins defined as bidirectional handshake lines also use the port C
OOR (DORC). Input-only handshake lines are not affected
by OORC. Reset clears all ODR bits to logic zero configuring all port pins as inputs. The OORs have no write-inhibit
control over the port data output latches. Data may be
written to the port data registers even though the pins are
configured as inputs.

Purpose:
The port C data register (POC) is used to read input data
and to latch data written to the output pins.

Register Name:
Port C Pin Function Select Register (FSR)

Description:
Register Address:
$B

Data is written into the port C output latch (see Figure 3)
regardless of the state of DORC. Any port C pin defined as
a handshake line by the port C function select register
(FSR) is not affected by POC. Output pins, as defined by
OORC, assume logic levels of the corresponding bits in the
port C output latch. A read of POC reflects the contents of
the output latch for output pins and the current state of
the input pins (as reflected in the DDRC). Reset has no effect upon the contents of PDC. Users are recommended
to initialize the port C output data latch before changing
any pin to an output via the OORC.

Register Bits:
7

6

5

4

ICFB2 I CFBl I CFA21 CFA 1 I XX

XX

XX

XX

Purpose:
The port C pin function select register defines whether the
multifunction port C pins are to operate as "normal" port
C lines or as handshake lines.

Register Name:
Data Direction Register for Port A (B) (C)

Description:
Register Address:
$6 ($7) ($8)

Register Bits:

I Bit 7 I Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I

Purpose:
Each of the three data direction registers (DORA, OORB,
and DORC) define the direction of data flow of the port
pins for ports A, B, and C.

3-1028

A logic zero in any FS R bit defines the corresponding port
C pin as a "normal" I/O pin. A logic one in any valid FSR
bit defines the corresponding port C pin as a handshake
line. Pins defined as handshake lines function according to
the contents of control register A (CRA) or control register
B (CRB). The port C data direction register (DORC) is valid
regardless of FS R contents for all pins except PC4/ CA 1
and PC6/CB1. Transitions on port C pins not defined as
handshake pins do not effect the handshake/interrupt
status register. Reset clears all FS R bits to a logic zero.
Users are recommended to initialize the data direction and
control registers before modifying the FSR.

MC146823

Register Name:
Handshake/Interrupt Status Register (H S R)

Register Name:
Handshake Warning Register (HWR)

Register Address:
SE

Register Address:
SF

Register Bits:

Register Bits:
3

IIRQF

I

XX

XX

XX

2

I HSB21 HSA21

1

0

HSBl

I HSA11

4

XX

xx

3

2

1

0

XX

Purpose:
The handshake interrupt status register is a read-only flag
register that may be used during a polling routine to determine if any enabled input handshake transition, as defined
by the control register (CRA and CRB), has occurred.

Purpose:
The warning register is a read-only flag register that may
be used to determine if a second attempt to set a handshake/interrupt status register bit has been made before
the original had been serviced.

Description:
If an enabled input handshake transition occurs then the
appropriate HSR bit (HSB2, HSA2, HSB1, or HSA1) is
set. The IRQ flag bit (bit 7, IRQF) is set when one or more
of the HSR bits 0-3 and their corresponding control
register bits are set to a logic one as shown in the following equation:

Description:
Each bit in the handshake/interrupt status register, except
I ROF, has a corresponding bit in the handshake warning
register. If an attempt is made to set a bit in the handshake/interrupt status register that is already set, then the
corresponding bit in the handshake warning register is also
set. An attempt is the occurrence of any enabled input
handshake transition as defined by the control registers.

Bit 7 = IRQF = [HSB2-CRB2(3)] + [HSA2-CRA2(3)]
+ [HSB1-CRB1 (Q)] + [HSA 1-CRA 1(0)]

A handshake warning register bit is cleared by first reading
the appropriate data register then reading the handshake
warning register. Reading the data register (either P1 DA,
P2DA, P1 DB, or P2DB) loads a buffer latch with the proper bit in the handshake warning register (HWA 1, HWA2,
HWB1, and HWB2, respectively). The next read of the
handshake warning register clears the appropriate bit
without affecting the other three handshake warning
register bits. The upper four bits, HWR4-HWR7, always
read as logic zeros. If a port data register is not read before
reading the handshake warning register, then the handshake warning register bits will remain unaffected. Reset
clears all HWR bits to a logic zero .

The numbers in ( ) indicate which bit in the control
register enables the interrupt.
Handshake/interrupt status register bits are cleared by
accessing the appropriate port data register. The following
table lists the H S R bit and the port data register that must
be accessed to clear the bit.

To Clear
HSR Bit
HSB2.
HSA2
HSB1
HSA1

Access
Register
. P2DB
P2DA
P1DB
P1DA

Recommended status register handling sequence:

Reset clears all handshake/interrupt status register bits to
a logic zero.

3-1029

1. Read status
register

(User determines which if any
enabled handshake transition
occurred)

2. Read/write port
data indicated by
status register

(Clears associated status bit and
latches appropriate warning
register bit in the buffer latch)

3. Read warning
register

(Latched warning bit is cleared
and the remaining bits are unaffected)

I

MC146823

uses the MC146805E2 CMOS MPU. Other multiplexed
microprocessors can be used as easily.
A single-chip microcomputer (MCU) may be interfaced
with 11 port lines as shown in Figure 5. This interface also requires some software overhead to gain up to 13 additional
I/O lines and the MC146823 handshake lines.

TYPICAL INTERFACING
The MC146823 is best suited for use with microprocessors
which generate an address-then-data-multiplexed bus.
Figure 4 shows the MC146823 in a typical CMOS system that

FIGURE 4 - A TYPICAL CMOS MICROPROCESSOR SYSTEM

MC146818
Real- Time Clock
Plus RAM

I

Bus Control

High Addr

~ ~

~~
~

u

3

Mux AddrlData

N 0
w
(f)

I'

I J3

Clock

8

lMCM6551~

IMCM65516J
16K ROM
~

8

8

3

j

5

"'

/

/

"'

5

[MCM65516J
16K ROM

16K ROM

f

~

8

5

/

8

5

"

/
/

/

Interrupt

0

~

~~

Reset
ChiPV
Enables

,

74HC138
Decoder

5

8

3

8

MC146823
CMOS Parallel Interface

~ 8

8

An 8-Chip CMOS Microprocessor System Includes:
8-Bit Microprocessor
6K Bytes of ROM
162 Bytes of RAM
64 Parallel 1/0 Pins
RTC Function

1i
8

8

MC146823
CMOS Parallel Interface

1 -~8 i
8

f8

FIGURE 5 - MC146823 INTERFACED WITH THE PORTS OF A
TYPICAL SINGLE-CHIP MICROCOMPUTER

MC3870
MC6805
MC146805
S2000
8021

MC146823

o

~_ _ _ _ _F8_ _ _ _----'l~ ADO-AD7

Ports

Q..

Address Strobe
Read

0
Q..

3

8

Write

AS

CA1

OS

CB1

R/W
CA2
VSS

Port
Lines

3-1030

CE

CB2

Port
Lines

8

®

MC146870SF2

MOTOROLA

Product Preview

CMOS
(HIGH-PERFORMANCE SILICON-GATE)

a-BIT EPROM MICROCOMPUTER UNIT

a-BIT EPROM
MICROCOMPUTER

The MCl468705F2 Microcomputer Unit (MCU) is an EPROM member
of the M6805 Family of low-cost single-chip microcomputers. The user
programmable EPROM allows program changes and lower volume applications in comparison to the factory mask programmable versions.
The EPROM versions also reduce the development C9sts and turnaround time for prototype evaluation of mask ROM versions. This 8-bit
microcomputer contains a CPU, on-chip oscillator, EPROM, bootstrap
ROM, RAM, I/O, and a TIMER.
The MC1468705F2 is a low-power processor designed for low-end to
mid-range applications in the consumer, automotive, industrial, and
communications markets where very low-power consumption constitutes an important factor.

I
CERAMIC PACKAGE
CASE 719

HARDWARE FEATURES

• Low Power Wait Mode
• Typical Stop Mode Power of 25 p-W
•
•
•
•

8-Bit Architecture
Fully Static Operation
Single 3- to 5.5-Volt Supply
1080 Bytes of On-Chip User EPROM

• 64 Bytes of On-Chip RAM
• Memory Mapped I/O
• 16 Bidirectional I/O Lines
• Four Input-Only Lines
• Internal 8-Bit Timer with Software Programmable 7-Bit Prescaler
• External Timer Input
• External and Timer Interrupts
• Bootstrap Program in ROM Simplifies EPROM Programming
• Master Reset and Power-On Reset

PIN ASSIGNMENT

RESET
IRQ

Vpp

• On-Chip Oscillator

PCO
PCl

• 1 p-s Cycle Time
• 28-Pin Dual-In-Line Package

OSC2

PC2

PAO

PC3

PA2

PBl

PA3

PB2

SOFTWARE FEATURES

•
•
•
•
•

VOO
TIMER

PBO

Similar to M6800 Family
Efficient Use of Program Space
Versatile Interrupt Handling
True Bit Manipulation
10 Addressing Modes with Indexed Addressing for Tables

PA4

PB3

PAEl

PB4

• Efficient Instruction Set

PA6

PBEl

• Memory mapped I/O
• Two Power Saving Standby Modes

PAl

PB6

VSS

PBl

USER PROGRAMMABLE OPTIONS

• Crystal or Low-Cost Resistor Oscillator Option
• Oscillator Internally Divided by Two or Four
• Interrupts Edge Sensitive Only or Level and Edge Sensitive

fhls docurnent contains information on a product under developrnent Motorola reserves the
right to change or discontinue thiS product without notice

3-1031

MC1468705F2

BLOCK DIAGRAM

Accumulator
A

CPU
Control

Index
Register

I

8

PAO
Port PAl
PA2.
A
PA3
1/0
PA4
Lines PA5
PA6
PA7

X
Condition
Code
Register

Port
Data
A
Direction
Register Register

Pan
Data
Direction
B
Register Register

CC

PSO
PB1
PB2 Port
PB3 B
I'B4 10
PB5 Lines
PB6
PB7

CPU

Stack
POinter
S

Port
C
Register

Program
Counter
High
PCH

8

Program
Counter
Low

ALU

PCL

Bootstrap

ROM

STACKING ORDER

PROGRAMMING MODEL
0

7

I

I

A

7

I

I
I

X

10

I

Accumulator

0
Index Register

10

10 10

4

5

1

0

( 0

1 11

I

I

L§
I

.N

Z

C

I~l~

T

Vi D

U
R

0101010101

~2*

CfJ
~

o

(..)

Internal
Address
Bus*

"""

Internal
Data
Bus*

RESET

* Internal timing signal and bus information not available externally.

it

* OSC1

r-

~

tRL

--1

J!

line is not meant to represent frequency. It is only used to represent time.

II

MC1468705G2

FIGURE 6 -

STOP RECOVERY AND POWER-ON RESET

O~::"-~ZZZZlZZZZZZ ~ III
(Edge
Sensitive
Only)
IRO
or
RESET

I

~teye"

~r-

~

U
,j'-,.6

1920 teye

tlLCH

r\

~2*--------------------------------------------------~

* Internal timing signals not available externally.
* * Represents the internal gating of the OSC1 input

pin.

Vpp

FUNCTIONAL PIN DESCRIPTION

The Vpp pin is used when programming the EPROM. By
applying the negative programming voltage to this pin, one
of the requirements is met for programming the EPROM.
Refer to PROGRAMMING FIRMWARE and the PROGRAMMING OPERATION ELECTRICAL CHARACTERISTICS
table.

Voo and VSS
Power is supplied to the MCU using these two pins. VDD
is power and VSS is ground.
IRQ (MASKABLE INTERRUPT REQUEST)

I RQ is a programmable option which provides two different choices of interrupt triggering sensitivity. These options are: (1) negative edge-sensitive triggering only, or (2)
both negative-edge sensitive and level-sensitive triggering. In
the latter case, either type of input to the I RQ pin will produce the interrupt. The MCU completes the current instruction before it responds to the interrupt request. When the
IRQ pin goes low for at least one t cyc , a logic one is latched
internally to signify an interrupt has been requested. When
the MCU completes its current instruction, the interrupt
latch is tested. If the interrupt latch contains a logic one, and
the interrupt mask bit (I bit) in the condition code register is
clear, the MCU then begins the interrupt sequence.
If the option is selected to include level-sensitive triggering, then the IRQ input requires an external resistor to VDD
for "wire-OR" operation. See INTERRUPTS for more detail.
This pin also detects a negative voltage that is used to initiate
the bootstrap mode program.

NOTE
In normal operation, this pin is connected directly to
VSS.
OSC1,OSC2

The MC1468705G2 can be configured to accept either a
crystal input or an RC network to control the internal oscillator. Additionally, the internal clocks can be derived by either
a divide-by-two or divide-by-four of the internal oscillator frequency (fosc). Both of these options are programmable via
the mask option register (MOR) in the EPROM array. The
programmable options provided via the MOR in the
MC1468705G2 are mask options in the MC146805G2.

RESET
The RESET input is not required for startup but can be
used to reset the MCU internal state and provide an orderly
software startup procedure. Refer to RESETS for a detailed
description.
TIMER
The TIMER input may be used as an external clock for the
on-chip timer. This pin is connected to VDD for the bootstrap mode (EPROM programming!. Refer to TIMER for
additional information about the timer circuitry.

3-1038

RC - If the RC oscillator option is selected, then a resistor
is connected to the oscillator pins as shown in Figure 7(d).
The relationship between Rand fosc is shown in Figure 8.
CRYSTAL - The circuit shown in Figure 7(b) is recommended when using a crystal. The internal oscillator is
designed to interface with an AT-cut parallel resonant quartz
crystal resonator in the frequency range specified for fosc in
Table 1 Control Timing. Using an external CMOS oscillator is
recommended when crystals outside the specified ranges are
to be used. The crystal and components should be mounted
as close as possible to the input pins to minimize output
distortion and startup stabilization time. Refer to Table 1 for
VDD specifications.

MC1468705G2

FIGURE 7 - OSCILLATOR CONNECTIONS

1 MHz

4 MHz

RS (Max)

400

75

{}

Co (Max)

5

7

pF

Cl

0.008

0.012

COSCl

15-40

15-30

I'F
pF

COSC2
Rp (Min)

15-30

15-25

pF

10

10

M{}

30

40

K

Q

Units

(a) Crystal Parameters

~
SC2

MC1468705G2
OSCl
39

Rp

CRS
::F
OSCl
l

38

OSC2

39

Co

38

D

_3_8_ _ _ _.....

10

3_
9

1 - 1_ _ _ _ _

(c) Equivalent Crystal Circuit
(b) Crystal Oscillator Connections

Unconnected
External Clock

(d) RC Oscillator Connection

(e) External Clock Source Connections

FIGURE 8 - TYPICAL FREQUENCY vs RESISTANCE FOR RC OSCILLATOR OPTION ONLY
10

.......
......."

"I

~

~
>-

0

c:::

Q)

0.5
~

:::J

I

~u

0

~

0.2

'" I':

0.1
0.05

0.02
0.01
1

10

20

50

Resistance (kl1l

3-1039

100

200

500

1000

I

MC1468705G2

EXTERNAL CLOCK - An external clock should be applied to the OSC1 input with the OSC2 input not connected,
as shown in Figure 7(e). An external clock should be used
with the crystal oscillator option and its pulse width should
be the tOH, tOl specification. The toxov or tilCH specifications do not apply when using an external clock input.

POD-P07
These eight lines comprise Port D. PD4-PD7 also are capable of driving LEOs directly. The state of any pin is software
programmable. Refer to PROGRAMMING for a detailed
description of I/O programming.

PAD-PA7
These eight I/O lines comprise Port A. The state of any pin
is software programmable. Refer to PROGRAMMING for a
detailed description of I/O programming.

PROGRAMMING
INPUT/OUTPUT PROGRAMMING
Any port pin may be software programmed as an input or
output by the state of the corresponding bit in the port data
direction register !DDR). A pin is configured as an output if
its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding DDR bit is cleared to
a logic zero. At reset, all DDRs are cleared, which configures
all port pins as inputs. A port pin configured as an output will
output the data in the corresponding bit of its port data
latch. Refer to Figure 9 and Table 2.

PBD-PB7
These eight lines comprise Port B. The state of any pin is
software programmable. Refer to PROGRAMMING for a
detailed description of I/O programming.

I

PCD-PC7
These eight lines comprise Port C. The state of any pin is
software programmable. Refer to PROGRAMMING for a
detailed description of I/O programming.

FIGURE 9 -

TYPICAL PORT liD CIRCUITRY

1/0
Pin

Internal
MC1468705G2
Connections

4

Typical Port
Data Direction
Register
Typical Port
Register

Pin

P-7

P-6

P-5

P-4

P-3

P-2

P-l

P-O

(b)

TABLE 2 -

liD PIN FUNCTIONS

R/W*

DDR

liD Pin Function

0

0

The 1/0 pin is in input mode. Data is written into the output data latch.

0

1

Data is written into the output data latch and output to the 1/0 pin.

1

0

The state of the 1/0 pin is read.

1

1

The 1/0 pin is in an output mode. The output data latch is read.

* R/W

is an internal signal.

3-1040

MC1468705G2

EPROM PROGRAMMING

$1 FFF. The MCU uses 10 of the lowest 16 memory locations
for program control and I/O features such as data ports, the
port DDRs, and the timer. The mask option register at
memory location $1 FF5 completes the total. The 112 bytes of
user RAM include up to 64 bytes for the stack. Except for the
MOR, the memory mapping is similar to the MC146805G2;
however, the MC1468705G2 has no self-check ROM because
of the bootstrap ROM requirement.
The stack area is used during the processing of interrupt
and subroutine calls to save the processor state. The contents of the CPU registers are pushed onto the stack in the
order shown in Figure 12. Since the stack pointer
decrements during pushes, the low order byte (PCL) of the
program counter is stacked first; then the higher order five
bits (PCH) are stacked. This ensures that the program
counter is loaded correctly as the stack pointer increments
when it pulls data from the stack. A subroutine call causes
only the program counter (PCl, PCH) contents to be pushed
onto the stack; the remaining CPU registers are not pushed.

When programming the EPROM array within the
MC1468705G2, ports are used in a special arrangement. See
PROGRAMMING FIRMWARE and Figure 20 for a detailed
description.

MEMORY
As shown in Figure 10, the MCU is capable of addressing
8192 bytes of memory and I/O registers with its program
counter. The MC1468705G2 MCU has implemented 2469
bytes of these locations. This consists of: 2106 bytes of user
EPROM, 240 bytes of bootstrap ROM, 112 bytes of user
RAM, an EPROM mask option register (MOR), eight bytes of
I/O, and two timer registers. The user EPROM is located in
two areas. The main EPROM area is in memory locations
$0080 to $08AF. The second area is reserved for ten interrupt/reset vector bytes at memory locations $1 FF6 through

FIGURE 10 -

127
128
255
256

I/O Ports
Timer RAM
128 Bytes
Page 0 User EPROM

1968 Bytes
User EPROM

ADDRESS MAP

$0000

0

Port A Data Register

$0000

$007F

1

Port B Data Register

$0001

1\$0080

2

Port C Data Register

$0002

$OOFF
$0100

3

Port D Data Register

$0003

4

Port A Data Direction Register

$0004

5

Port B Data Direction Register

$0005

6

Port C Data Direction Register

$0006

\

$08AF
$08BO

2223
2224

5712 Bytes
ROM Unused

7

Port D Data Direction Register

$0007

8

Timer Data Register

$0008

9

Timer Control Register

$0009
$oooA

10
6 Bytes
Unused

7935
7936
8175
8176
8180
8181

240 Bytes
Bootstrap ROM
5 Bytes
Unused
Mask Option Register

$1 EFF
$1 FOO

$oooF
$0010

15
16

$1 FEF
$1 FFO

RAM
1112 Bytes)
63 _

$1 FF4

;:;

64

./

$1 FF5

Timer Interrupt Wait State Only

$1 FF6-$1 FF7

Timer Interrupt

$1 FF8-$1 FF9

External Interrupt

$1 FFA-$l FFB

SWI

$lFFC-$1FFD

Reset

,/
$lFFE-$lFFF
127

./
./
./
./

. / ./ Stack 164 bytes Max)
./
./

8191

* Reads of unused locations undefined.

3-1041

$003F
$0040

t

$007F

I

MC1468705G2

PROGRAM COUNTER (PC)
The program counter is a 13-bit register that contains the
address of the next instruction to be executed by the processor.

REGISTERS
The MC1468705G2 contains five registers, as shown in the
programming model of Figure 11. The interrupt stacking
order is shown in Figure 12.

STACK POINTER (SP)
The stack pointer is a 13-bit register containing the
address of the next free location on the stack. When accessing memory, the seven most significant bits are permanently
configured to 0000001. These seven bits are appended to the
six least significant register bits to produce an address within
the range of $OO7F to $0040. The stack area of RAM is used
to store the return address on subroutine calls and the
machine state during interrupts. During external or power-on
reset, and during a reset stack pointer (RSP) instruction, the
stack pointer is set to its upper limit ($OO7F). Nested interrupt
and/or subroutines may use up to 64 (decimal) locations,
beyond which the stack pointer wraps around and points to

ACCUMULATOR (A)
The accumulator is an 8-bit general purpose register used
to hold operands, results of the arithmetic calculations, and
data manipulations.

II

INDEX REGISTER (X)
The X register is an 8-bit register which is used during the
indexed modes of addressing. It provides an 8-bit value
which is used to create an effective address. The index
register is also used for data manipulations with the readmodify-write type of instructions and as a temporary storage
register when not performing addressing operations.

FIGURE 11 -

PROGRAMMING MODEL

0

7

I

A

I

Accumulator

I

Index Register

0
X

12
PCH

Program Counter

PCl

12
6
\01010101010111

0

I

SP

Stack POinter

CC

~
I

FIGURE 12 -

N

Z

C

Condition Code Register
Carry/ Borrow
Zero
Negative
Interrupt Mask
Half Carry

STACKING ORDER

Stack

l

R

Increasing Memory
Addresses

E
T
U
R

N

111 111 Condition Code Register
Accumulator

o,

oT 0-,

Index Register
PCH
PCl

Unstack

I

~1

Decreasing Memory
Addresses

P

T

NOTE: Since the Stack Pointer decrements during pushes, the PCl is
stacked first, fOllowed by PCH, etc. Pulling from the stack is in
the reverse order.

3~1042

MC1468705G2

its upper limit; thereby, losing the previously stored information. A subroutine call occupies two RAM bytes on the
stack, while an interrupt uses five RAM bytes.

Timer control register interrupt mask bit TCR6 is set to
a logic one to preclude timer interrupt processing.
All data direction register bits are cleared to logic zeros
to define all ports as input.

CONDITION CODE REGISTER (CC)
The condition code register is a 5-bit register which indicates the results of the instruction just executed. These bits
can be individually tested by a program and specified action
taken as a result of their state. Each bit is explained in the
following paragraphs.
HALF CARRY BITS (H) - The H bit is set to a one when a
carry occurs between bits 3 and 4 of the ALU and during an
ADD or ADC instruction. The H bit is useful in binary coded
decimal subroutines.
INTERRUPT MASK BIT (I) - When the I bit is set, both
the external interrupt and the timer interrupt are disabled.
Clearing this bit enables the above interrupts. If an interrupt
occurs while the I bit is set, the interrupt is latched and is
processed after the I bit is next cleared.
NEGATIVE (N) - When set, this bit indicates that the
result of the last arithmetic, logical, or data manipulation is
negative (bit 7 in the result is a logic one).
ZERO (Z) - When set, this bit indicates that the result of
the last arithmetic, logical, or data manipulation is zero.
CARRY/BORROW (C) - Indicates that a carry or borrow
out of the arithmetic logic unit (ALU) occurred during the
last arithmetic operation. This bit is also affected during bit
test and branch instructions, shifts, and rotates.

RESETS
The MC1468705G2 has two reset modes: an active low
external reset pin (RESET) and a power-on reset function;
refer to Figure 5.
RESET
The RESET input pin is used to reset the MCU to provide
an orderly software startup procedure. When using the
external reset mode, the RESET pin must stay low for a minimum of one tcyc. The RESET pin contains an internal
Schmitt Trigger as part of its input to improve its noise
immunity.
POWER-ON RESET
The power-on reset occurs when a positive transition is
detected on VDD. The power-on reset is used strictly for
power turn-on conditions and should not be used to detect
any drops in the power supply voltage. There is no provision
for a power-down reset. The power-on circuitry provides for
a 1920 tcyc delay from the time that the oscillator becomes
active. If the external RESET pin is low at the end of the 1920
tcyc time out, the processor remains in the reset condition
until RESET goes high.
Either of the two types of reset conditions causes the following to occur:
Timer control register interrupt request bit TCR7 is
cleared to a logic zero to preclude premature timer
interrupts.

Stack pointer is preset to its upper limit,$007F.
The internal address bus is forced to the reset vector
($lFFE, $lFFF).
Condition code register interrupt mask bit (I) is set to a
logic one to mask any external interrupts.
STOP and WAIT latches are cleared to place MCU in
normal operation.
External interrupt latch is cleared to ensure no external
interrupt is processed.
MCU operation is set up per mask option register
(MOR). External reset does not affect the MOR.
All other functions, such as other registers (including I/O
ports), the timer, etc. are not cleared by the reset conditions.

BOOTSTRAP ROM
The bootstrap ROM contains a factory program which
allows the MCU to present an address and fetch data from
an external device and transfer it into the MC1468705G2
EPROM. The bootstrap program provides: timing of programming pulses, timing of Vpp input, and verification after
programming. See PROGRAMMING FIRMWARE.

MASK OPTION REGISTER (MOR)
The mask option register is an 8-bit user programmed
(EPROM) register in which three of the bits are used. Bits in
this register are used to select the type of system clock
(crystal/RC oscillator), the divide-by-four/divide-by-two
clock option (bus frequency), and the edge-sensitive or
edge- and level-sensitive trigge;ed interrupt recognition. The
MOR is not available on the MC146805G2 ROM-based part.

INTERRUPTS
Systems often require that normal processing be interrupted so that some external event may be serviced. The
MC1468705G2 may be interrupted by one of three different
methods: either one of two maskable hardware interrupts
(external input or timer) or a nonmaskable software interrupt
(SWI).
Interrupts cause the processor registers to be saved on the
stack and the interrupt mask (I bit) set to prevent additional
interrupts. The RTI instruction causes the register contents
to be recovered from the stack followed by a return to normal processing. The stack order is shown in Figure 12.
Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered
pending until the current instruction execution is completed.
When the current instruction is complete, the processor
checks all pending hardware interrupts and, if an interrupt is
pending and is unmasked, proceeds with interrupt processing; otherwise, the next instruction is fetched and executed.
Note that masked interrupts are latched for later interrupt
servicing.
If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the same as any

3-1043

I

MC1468705G2

other instruction. Refer to Figure 13 for the interrupt and instruction processing sequence.
Table 3 shows the execution priority of the RESET, IRQ,
and timer interrupts, and the software interrupt, SWI. Two
conditions are shown, one with the I bit set and the other
with the I bit clear; however, in either case RESET has the
highest priority of execution. If the I bit is set as per Table
3(a), the second highest priority is assigned to SWI. This is illustrated in Figure 13 which shows that the IRQ or Timer interrupts are not executed when the I bit is set and the next
instruction (including SWIl is fetched. If the I bit is clear as

FIGURE 13 -

Fi"ESE'f AND

per Table 3(b), the priorities change in that the next instruction (including SWI) is not fetched until after the IRQ and
Timer interrupts have been recognized (and serviced). Also,
when the I bit is clear, if both IRQ and Timer interrupts are
pending, the IRQ interrupt is always serviced before the
Timer interrupt.

NOTE
The conditions for Table 3 assume that, except for
RESET, the current instruction is completed, thus the
MCU is at an instruction boundary.

INTERRUPT PROCESSING FLOWCHART

I
1-1 lin CCI
007F-SP
O-DDRs
CLR IRO Logic
TCR b7-0
TCRb6-1

Clear

Stack
PC,X, A, CC

TAO
Request
Latch

Timer
Put IFFE on
Address Bus

Load PC From:
SWI: 1FFCI 1FFD
IRO: 1FFA/1FFB
TIMER 1FF811FF9
Timer Wait: 1FF6/ 1FF7
Fetch
Instruction

Load PC
from
1FFE/1 FFF
Execute All
Instruction
Cycles

3-1044

MC1468705G2

TABLE 3 - INTERRUPT INSTRUCTION EXECUTION
PRIORITY AND VECTOR ADDRESS
(a) I Bit Set
Interrupt/ Instruction
RESET
SWI
Note: IRQ and TIMER Interrupts are not executed when the I bit is
set; therefore, they are not shown.
(b) I Bit Clear
Interrupt/ Instruction

Priority

Vector Address

RESET
IRQ
Timer

1

2
3

SWI

4

$1 FFE-$l FFF
$lFFA-$lFFB
$1 FFS-$l FF9
$1 FF6-$1 FF7*
$lFFC-$lFFD

The minimum time between pulses is a function of the length
of the interrupt service routine. Once a pluse occurs, the
next pulse should not occur until the MPU software has
exited the routine (an RTI occurs). This time (tILlLl is obtained by adding 20 instruction cycles (t cyc ) to the total number
of cycles it takes to complete the service routine including
the RTI instruction; refer to Figure 14. The second configuration shows many interrupt lines "wire-ORed" to form the interrupts at the processor. Thus, if after servicing one interrupt the interrupt line remains low, then the next interrupt is
recognized.

NOTE
The internal interrupt latch is cleared in the first part of
the service routine; therefore, one (and only one)
external interrupt pulse could be latched during tl LI L
and serviced as soon as the I bit is cleared.

*The Timer vector address from the WAIT mode is $lFF6-$lFF7.

SOFnNAREINTERRUPT

TIMER INTERRUPT
If the timer interrupt mask bit (TCR6) is cleared, then each
time the timer decrements to zero (transitions from $01 to
$00 to set TCR7) an interrupt request is generated. The actual processor interrupt is generated only if the interrupt
mask bit (in the condition code register) is cleared. When the
interrupt is recognized, the current state of the machine is
pushed onto the stack and the interrupt mask bit in the condition code register is set. This masks further interrupts until
the present one is serviced. The processor now vectors to
the timer interrupt service routine. The address for this service routine is specified by the contents of $1 FF8 and $1 FF9
unless the processor is in a WAIT mode in which case the
contents of $1 FF6 and $1 FF7 specify the timer service
routine address. Software must be used to clear the timer interrupt request bit nCR7). At the end of the timer interrupt
service routine, the software normally executes an RTI instruction which restores the machine state and starts executing the interrupted program.
The actual timer interrupt request can be delayed by controlling TCR6 (interrupt mask bit). If TCR6 is programmed to
a logic one, no interrupt is generated even if TCR7 (interrupt
request bit) is set. Then, TCR6 can be programmed (after a
specific time) to a logic zero to generate the actual timer
interrupt request.

EXTERNAL INTERRUPT
If the interrupt mask bit of the condition code register has
been cleared and the external interrupt pin (I RQ) has gone
low, then the external interrupt is recognized. The action of
the external interrupt is identical to the timer interrupt with
the exception that the interrupt request input at IRQ is
latched internally and the service routine address is specified
by the contents of $1 FFA and $1 FFB. Either a level-sensitive
and edge-sensitive trigger, or an edge-sensitive only trigger
are available as a mask option register (MOR) controlled programmable option. Figure 14 shows both a functional and
mode timing diagram for the interrupt line. The timing
diagram shows two different treatments of the interrupt line
(IRQ) to the processor. The first method shows single pulses
on the interrupt line spaced far enough apart to be serviced.

The software interrupt (SWI) is an executable instruction.
The action of the software interrupt instruction is similar to
the hardware interrupts. The software interrupt is executed
regardless of the state of the interrupt mask bit in the condition code register. The service routine address is specified by
the contents of memory locations $1 FFC and $1 FFD. See
Figure 13 for interrupt and instruction processing flowchart.

LOW-POWER MODES

STOP
The STOP instruction places the MC1468705G2 in its lowest power consumption mode. In the STOP mode the internal oscillator is turned off, causing all internal processing and
the timer to be halted; refer to Figure 15.
During the STOP mode, timer control register (TCR) bits 6
and 7 are altered to remove any pending timer interrupt requests and to disable any further timer interrupts. The timer
prescaler is cleared. The I bit in the condition code register is
cleared to enable external interrupts. All other registers and
memory remain unaltered. All input/output lines remain unchanged.

WAIT
The WAIT instruction places the MC1468705G2 in a low
power consumption mode, but the WAIT mode consumes
somewhat more power than the STOP mode. In the WAIT
mode, the internal clock is disabled from all internal circuitry
except for the timer; refer to Figure 16. Thus, all internal processing is halted; however, the timer continues to count normally.
During the WAIT mode, the I bit in the condition code
register is cleared to enable interrupts. All other registers,
memory, and input/output lines remain in their previous
state. The timer may be enabled to allow a periodic exit from
the WAIT mode. If an external and a timer interrupt occur at
the same time, the external interrupt is serviced first; then, if
the timer interrupt request is not cleared in the external interrupt routine, the normal timer interrupt (not the timer wait
interrupt) is serviced since the MCU is no longer in the WAIT
mode.

3-1045

I

MC1468705G2

FIGURE 14 -

EXTERNAL INTERRUPT

(a) Interrupt Functional Diagram

Level-Sensitive Trigger
MOR Programmed Option

Voo
o

External
Interrupt
Request

QI----~

Interrupt Pin -----4J..----

Timer Int. IWAITI

Filled With
'00' or 'FF'

$1 FF5 \

$lff6~f7\

Timer interrupt

$1 FF8-F9

External Interrupt

$1FFA-FB

SWI

$1 FFC-FO

Reset

$1FFE-FF

3-1051

$1 FF4
$1FF5

•

$1 FFF

III
s:
FIGURE 20 -

o
•

PROGRAMMING CONNECTIONS

0----0

5.25 V
I

.~

0--0 I Sl
I~
SV

*
J-

Yl
1.0MHz

0
R2

Cl~

C3

27PF~

0.1

39
OSCl

Rl
100 k

=-

4~
~

R6[....n

~

100 k

RS
510

~,Q2

PC6

4~ PC?
VSS

-=
.:.

IN4742A f 2 V
VRI

Rll
15 k

Rl0
62

2 IRQ

2N4401

R9
6.S k

Q4
2N4403

IN5534C
VR2 , ,
r ~ 14V

~

""

fym
Ql

3

...

Q5
2N4403

3

~:131Ic6

R12
470

1k

Vpp

*01

-=

R14
3k

Q3
2N4403

-=

~~ IN~~Ol

~

POl

R16
S.2 k
AA

00
10 01

1102
13
03
14
04
15
05
16
06
17
07

<0
<0

~~

=>ff5
2
u
2

24 VCC

N

~
0

g~
'<2

C

"00

TAX
1
INH
2
CLC
NH
2
SEC
1
INH
2
CLI
1
INH

2

AEl
3

7

EX

4

INH
2
RSP
1
INH
2
NOP
1
INH

5
INC

SUB L
IMM
2
CMP
IMM
2
SBC
IMM
2
CPX
IMM
2
AND
IMM
2
BIT
IMM
2
LDA
IMM

B

2

1

5
INC

BIL

~IH AEl

1

LSR
IXl

2

10

COM
IXl
6

SEI

3

5

5

6

COM X
1

2

2

3
BHCC
REI
3
BHCS
A
3
BPL
AFI
3
BMI
AEl
3
BMC
REl
3

5

2

NEG
1

IMM
A

DIR

9
1001

INH

8
1000

0';'

6

1

3

5

2

3

INH

IX

o~o

O,~,
3

en
CO

Register I Memory

Control

2

5

2

2 NEG :
DI

Readl Modify IWrite
INH
IXl

3

STX 5
EXT

SBC 0
IX2
5
CPX
IX2
5
AND
IX2
5
BIT
IX?
5
LDA
IX2
B
STA
IX2
5
EOR
IX2
5
ADC
IX2

SUB
2

SUB

4

IXl
CMP

I

IX

1

SBC J
IX

4

SBC
IXl

2

4

CPX

CPX
IXl

2

1

4

BIT IXl

3

0100

4

1

3

O~,
6

LDA
IXI
5

IX

1

0110

IXl

1

4

IX
3

0111

IX
3

1000

EOR

EOR
1

4

8

9

ADC

ADC

IX

1001

ORA'
IX2

ORA 4
IXI
2

ORA J
1
IX

1010

ADD 5
IX2
3

ADD 4
IXl
2

ADD J
1
IX

1011

JMP 3
IXl
2

JMP L
1
IX

3
3

4

JMP
IX2

3.

JSA

JSA
IX2

3
LDX
3

6

IXI

2

1

JSA
1

4

5
IX2
6

IXI

B
C
1100

"
IX
3

1101

D

IX

1110

E
4

STX
IX2

1

I

A

LDX

LDX
2

STX
3

IXI

2

1

7

STA

IXI

I

4

STA

2

0010

j

IX
3
BIT IX

4

LDA

2

2

AND
IXl

2

N

C1I

0001

0011

4

2

C)

1

IX
3

1

AND
2

~

j

CMP
IXl

2

o

IX
3

1

4

.......

~

2

"
IXl

F

STX
1

IX

1111

LEGEND
41(

Mnemonic
Bytes

~.
1

Cycles - - - - - - - '

I

:> Opcode in Hexadecimal

1

~
,Jx..

"

~

Opcode in Binary

0000 c=

Address Mode

MC1468705G2

TABLE 10 -

INSTRUCTION SET
Condition Codes

Addressing Modes
Mnemonic

Inherent

ADC
ADD
AND
ASL
ASR
BCC
BCLR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
BIL
BIT
BLO
BLS
BMC
BMI
BMS
BNE
BPL
BRA
BRN
BRCLR
BRSET
BSET
BSR
CLC
Cli
CLR
CMP
COM
CPX
DEC
EOR
INC
JMP
JSR
LDA
LDX
LSL
LSR
NEG
NOP
ORA
ROL
ROR
ASP
ATI
ATS
SBC
SEC
SEI
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT

Condition
H
I
N
Z
C

Indexed
(No Offset)

Indexed
(8 Bits)

Indexed
(16 Bits)
X
X
X

Immediate

Direct

Extended

x

X
X
X
X
X

x

x

x

X
X

X
X
X
X

X
X
X
X

X
X
X
X

Relative

Bit
Set/
Clear

Bit
Test &
Branch

•

•
•
••
•
•
•
•
•
••
•
••
•
•
••

X
X

X

X

X

X

X

X
X
X
X
X
X
X
X
X

•••
•
••0
•
•
••

X
X

X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X

X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X

X
X
X

X
X

X
X
X
X

•
X

•
•••
••
••
••
A

X

X

X

X

X

X

X

X

X

X

X
X

X
X

X
X

X
X

X
X

X

Code Symbols
Half Carry (From Bit 3)
Interrupt Mask
Negative (Sign Bit)
Zero
Carry/ Borrow

X

A

X

Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
Cleared
Set

3-1057

•A

I

0 1
A A A
A A 1
A A A
A A
A A
A A

• 0 A A
• •A •A •
•

1\

•. A
•• •
••• ••A
•0 ••
•• •
• •• _.
•o ••
!

A

A
A

1

X

•

•
•••
•••
•

A

1

X

•

••
0
••

A

X
X

X
X
X
X
X

A

~~

••
•••
•• •• •• •••
• AA AA •
•• A A •A

X

!

X

A

A A
A A A
A A II.

••
•
X
X

X
X
X

N Z C

• AA

X
X
X
X
X
X
X
X
X

I

H

A
A •

A

1\

1\

•
•
•A
••
••
••
••
•

A A
A A

•
•A
••
•
A
••
••
!

A

A

A

!

1

A

MC1468705G2

INDEXED, 8-BIT OFFSET
Here the EA is obtained by adding the contents of the byte
following the opcode to that of the index register; therefore,
the operand is located anywhere within the lowest 511
memory locations. For example, this mode of addressing is
useful for selecting the mth element in an n element table. All
instructions are two bytes. The contents of the index register
(X) is not changed. The contents of (PC + 1) is an unsigned
8-bit integer. One byte offset indexing permits look-up tables
to be easily accessed in either RAM or ROM.
EA=X+(PC+1); PC--PC+2
Address Bus High--K; Address Bus Low--X+ (PC+ 1)
Where:
K = The carry from the addition of X + (PC + 1)

I

INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit
index register and the two unsigned bytes following the opcode. This addressing mode can be used in a manner similar
to indexed 8-bit offset, except that this three byte instruction
allows tables to be anywhere in memory (e.g., jump tables in
ROM). As with direct and extended, the M6805 assembler
determines the most efficient form of indexed offset; 8-or
16-bit. The contents of the index register are not changed.
EA= X+ [(PC+ 1):(PC+2))]; PC- PC+3
Address Bus High -- (PC + 1) + K;
Address Bus Low -- X + (PC + 2)
Where:
K = The carry from the additon of X + (PC + 2)
RELATIVE
Relative addressing is only used in branch instructions. In
relative addressing, the contents of the 8-bit signed byte
following the opcode (the offset) are added to the PC if and
only if the branch condition is true. Otherwise, control pro-

ceeds to the next instruction. The span of relative addressing
is limited to the range of - 126 to + 129 bytes from the
branch instruction opcode location. The Motorola assembler
calculates the proper offset and checks to see if it is within
the span of the branch.
EA= PC+2+ (PC+ 1); PC--EA if branch taken;
otherwise, EA = PC -- PC + 2
BIT SET/CLEAR
Direct addressing and bit addressing are combined in instructions which set and clear individual memory and 1/0
bits. In the bit set and clear instructions, the byte is specified
as a direct address in the location following the opcode. The
first 256 addressable locations are thus accessed. The bit to
be modified within that byte is specified with the first three
bits of the opcode. The bit set and clear instructions occupy
two bytes, one for the opcode (including the bit number) and
the other to address the byte which contains the bit of
interest.
EA= (PC+ 1); PC--PC+2
Address Bus High--O; Address Bus Low--(PC+ 1)
BIT TEST AND BRANCH
Bit test and branch is a combination of direct addressing,
bit set/ clear addressing, and relative addressing. The actual
bit to be tested, within the byte, is specified within the low
order nibble of the opcode. The address of the data byte to
be tested is located via a direct address in the location
following the opcode byte (EA 1). The signed relative 8- bit
offset is in the third byte (EA2) and is added to the PC if the
specified bit is set or cleared in the specified memory location. This single three byte instruction allows the program to
branch based on the condition of any bit in the first 256 locations of memory.
EA1 = (PC+ 1)
Address Bus High--O; Address Bus Low--(PC+ 1)
EA2 = PC + 3 + (PC + 2); PC -- EA2 if branch taken;
otherwise, PC - PC + 3

3-1058

®

TCA5600
TCF5600

MOTOROLA
Prod uct Preview

UNIVERSAL MICROPROCESSOR
POWER SUPPLY CONTROLLER

UNIVERSAL MICROPROCESSOR POWER SUPPLY
CONTROLLER

SILICON MONOLITHIC
INTEGRATED CIRCUITS

The TCA5600 is a versatile power supply control circuit for
microprocessor based systems and mainly intended for automotive applications and battery powered instruments. To cover
a wide range of applications, the device offers high circuit flexibility with minimum of external components.
Functions included in this IC are a temperature compensated
voltage reference, on chip dc/dc converter, programmable and
remote controlled voltage regulator, fixed 5.0 V supply voltage
regulator with external PNP power device, undervoltage detection
circuit, power-on RESET delay and watchdog feature for safe and
hazard free microprocessor operations.

I

1

PLASTIC PACKAGE
CASE 707-02

• 6.0 to 30 V Operation Range
• 2.5 V Reference Voltage Accessible for Other Tasks
• Fixed 5.0 V ± 4% Microprocessor Supply Regulator Including
Current Limitation, Overvoltage Protection and Undervoltage
Monitor

PIN CONNECTIONS

• Programmable 6.0 to 30 V Voltage Regulator Exhibiting High
Peak Current (150 mAl, Current Limiting and Thermal Protection
• Two Remote Inputs to Select the Regulator's Operation Mode:
OFF, 5.0 V, 5.0 V Standby and Programmable Output Voltage
• Self Contained dc/dc Converter Fully Controlled By the Programmable Regulator to Guarantee Safe Operation Under All
Working Conditions

RESET

1

Vout1 Sense

2

Delay
lout1 Sense

• Programmable Power-On RESET Delay

Base Drive

• Watchdog Select Input

VCC2

• Negative Edge Triggered Watchdog Input

Gnd

• Low Current Consumption in the VCC1 Standby Mode
• All Digital Control Ports are TIL- and MOS-Compatible
APPLICATIONS INCLUDE

V out 2 Prog

7

Vout 2 Output

8

Current
Sense

Converter
Output

• Microprocessor Systems with E2pROMs

Converter
Input

• High Voltage Crystal and Plasma Displays
• Decentralized Power Supplies in Computer and Telecommunication Systems
(Top View)

RECOMMENDED OPERATION CONDITIONS
Characteristic
Power Supply Voltage
Collector Current
Output Voltage
Reference Source Current

Symbol

Min

Max

Unit

VCC1
VCC2

5.0
5.5

30
30

V

800

rnA

Device

IC

-

ORDERING INFORMATION

V out 2

6.0

30

V

TCA5600

Iref

0

2.0

rnA

TCF5600

This document contains Information on a product under development. Motorola reserves the
right to change or discontinue this product Without notice

3-1059

Operating Junction
Temperature Range

o to

+ 125°C

-40 to + 150°C

Package
Plastic DIP
Plastic DIP

TCA5600, TCF5600
MAXIMUM RATINGS

(TA = + 25°C unless otherwise noted Note 1)

Rating

Symbol

Value

Unit

VCC1, VCC2

35

Vdc

Base Drive Current (Pin 15)

18

20

mA

Collector Current (Pin 10)

IC

1.0

A

Forward Rectifier Current (Pin 10-Pin 9)

IF

1.0

A

Logic Inputs INH1, INH2, WDS
(Pin 6,11,18)

VINP

- 0.3 V to VCC1

Vdc

Logic Input Current WDI (Pin 4)

IWDI

±0.5

mA

Output Sink Current RESET (Pin 1)

IRES

10

mA

-0.3 to 10
-0.3 to 5.0

V

Power Supply Voltage (Pin 3, 14)

I

Analog Inputs (Pin 2)
(Pin 7)

-

Reference Source Current (Pin 5)

Iref

Power Dissipation (Note 2)
TA = +75°C TCA5600
TA = +85°C TCF5600

Po

-

5.0

mA
mW

500
650

Thermal Resistance (Junction to Air)

100

ROJA

Operating Temperature Range
TCA5600
TCF5600

TA

Operating Junction Temperature
TCA5600
TCF5600

TJ

°CIW
°C

o to

+ 75
-40 to +85
°c
+ 125
+ 150

Storage Temperature Range

- 65 to + 150

Tstg

°c

NOTES:
1. Values beyond which damage may occur.
2. Derate at 10 mWrC for junction temperature above + 75°C (TCA5600).
Derate at 10 mWrC for junction temper~ture above + 85°C (TCF5600).

FUNCTIONAL BLOCK DIAGRAM
0>

t::
Q)
> ....
c ::J
o 0.

'E

~~

.... .=l

>
C

~

Q)

o

::J
0.
....
::J

uE uO

C

Q)
VJ

.... C

::J Q)
UC/)

N

~

C

Q)

....

0

£>

E

"' ....

Ne
.... 0>

>

~~

::J

::J
0.

Q)

::J

::J

0::0

C/»

0> ....

::J

0 o
....

>0..

U
U

::J

0.",
o.~

0

:;
.... ..2
C

Q)

~ ~

::J Q)
UC/)

Inhibit 2
(INH2)

Inhibit 1
(lNH1)

>------.

PNP
Base Drive

..--.. . .w..,. Vou t1 Sense

Supply
Voltage VCC1

>-

'"

Qi

0

0O>IUl
0

0>=

B-

00
:g~
B~

~ ~

~

:g~

'" ....
Qi

'"

::J
0.

E

C/)

Q)~

0>

'"

Q)

~>....

0-

>

~

C

Q)

a:;
Q;
0::

3-1060

'0
C
(!J

TCA5600, TCF5600
ELECTRICAL CHARACTERISTICS (VCC1 = VCC2 = 12 V; TJ = 25°C; Iref = 0; lout1 = 0 (Note 3); RSC = 0.50; INH1 =
"High"; INH2 = "High"; WDS = "High"; lout2 = 0 (Note 4); if not otherwise specified)
Characteristic

Symbol

Typ

REFERENCE SECTION

1

Nominal Reference Voltage
Reference Voltage
Iref = 0.5 mA, Tlow ~ TJ ~ Thigh (Note 5).
6.0 V ~ VCC1 ~ 18 V
Line Regulation (6.0 V ~ VCC2 ~ 18 V)
Average Temperature Coefficient
Tlow ~ TJ ~ Thigh (Note 5)

2

Ripple Rejection Ratio
f = 1.0 kHz, Vsin = 1.0 Vpp

3

Vref nom

2.42

2.5

2.58

V

Vref

2.4

-

2.6

V

Regline

-

2.0

~

-

-

RR

60

70

-

dB

Zo

-

1.0

-

Ohm

ICC1

-

3.0

-

mA

15

mV

+/-0.5

mV/oC

~TJ

Output Impedance
o ~ Iref ~ 2.0 mA
4

Standby Current Consumption
VCC2 = Open

I

NOTES:
3. The external PNP power transistor satisfies the following minimum specifications:
hFE '3 60 at IC = 500 mA and VCE = 5.0 V; VCE(sat) ,;; 300 mV at 18 = 10 mA and IC = 300 mA
4. Regulator Vou t2 programmed for nominal 24 V output by means of R4, R5 (see Figure 1)
5. Tlow =
O°C for TCA5600; Tlow = -40°C for TCF5600.
Thigh = 125°C for TCA5600; Thigh =
150°C for TCF5600.

5.0 V MICROPROCESSOR VOLTAGE REGULATOR SECTION
Nominal Output Voltage
Output Voltage
5.0 mA ~ lout1 ~ 300 mA, Tlow ~ TJ ,;;: Thigh (Note 5)
6.0 V ,;;: VCC2 ,;;: 18 V

Vout1(nom)

4.8

V out 1

4.75

= 6.0 V, V15 = 4.0 V)

Undervoltage Detection Level (RSC

3

= 5.0 m
= 5.0 m

V
V

mV

10

50

20

100

mV

IB

10

15

-

mA

RR

50

65

-

dB

Vlow

4.5

0.93 x V ou t1

VRSC

210

250

Regline
Regload

Current Limitation Threshold (RSC

5.2
5.25

-

Line Regulation (6.0 V,;;: VCC2 ,;;: 18 V)

Ripple Rejection Ratio
f = 1.0 kHz, Vsin = 1.0 Vpp

-

5
6

Load Regulation (5.0 mA ,;;: lout1 ,;;: 300 mAl
Base Current Drive (VCC2

5.0

7

~Vout1

Average Temperature Coefficient
Tlow';;: TJ ,;;: Thigh (Note 5)

~TJ

3-1061

-

-

-

V

290

mV

±1.0

mVrC

TCA5600, TCF5600

Characteristic
PROGRAMMABLE VOLTAGE REGULATOR SECTION (Note 6)
Nominal Output Voltage
Output Voltage
1.0 rnA.;; lout2 .;; 100 rnA, Tlow';; TJ .;; Thiah (Notes 5,7)

8

Load Regulation 1.0 rnA .;; lout2 .;; 100 rnA (Note 7l

Vout2(nom)

23

Vou t2

22.8

Peak Output Current (Internally Limited)

OFF State Output Impedance (INH2 = "Low")

I

Average Temperature Coefficient
Tlow .;; TJ .;; Thigh (Note 5)

V

25.2

V

-

40

200

mV

100

-

-

rnA

lout2 p

150

200

-

rnA

RR

45

55

-

dB

Vout2(5.0 V)

4.75

Ripple Rejection Ratio
f = 20 kHz, V = 0.4 V pp
Output Voltage (Fixed 5.0 V)
1.0 rnA .;; lout2 .;; 20 rnA, Tlow .;; TJ .;; Thigh,
INHl = "High" (Note 5)

24

lout2

Regload

DC Output Current

25

-

-

Rout l

-

10

tlV out 2
ilTJV out 2

-

-

350

400
50

5.25

-

V

k!l

±0.25

mV;oCV

450

mV

NOTES:
6. V9 = 28 V, INH1 = "Low" for this Electrical Characteristic section unless otherwise specified.
7. Pu Ise tested tp .;; 300 !,-S

DC/DC CONVERTER SECTION
Collector Current Detection Level "High"
"Low"
RC = 10 k

9

Collector Saturation Voltage
IC = 600 rnA (Note 7)

10

VCE(sat)

-

-

1.6

V

Rectifier Forward Voltage Drop
IF = 600 rnA (Note 7)

11

VF

-

-

1.4

V

VC5(H)
VC5(L)

-

2.5
1.0

-

V

V12(H)
V12(L)

-

-

WATCHDOG AND RESET CIRCUIT SECTION
Threshold Voltage "High"
(static)
"Low"
Current Source Tlow .;; TJ .;; Thigh (Note 5)
Power-Up RESET
Watchdog Time Out
Watchdog RESET

-1.8

-

=

-2.5
5xlC5
- 50xlC5

-3.2

-

-

-

ri

12

15

-

kH

tp

-

-

10

/-Ls

VINP

-

-

-0.3 to
VCCl

V

-

-

100
150

-

-100

VWDI

Watchdog Input Impedance

--

/-LA

IC5

Watchdog Input Voltage Swing

Watchdog Reset Pulse Width (C8

-

1.0 nF) (Note 9)

±5.5

V

--

DIGITAL PORTS: WDS, INH 1, INH 2, RESET (Note 8)'
Input Voltage Range
Input HIGH Current
2.0 V .;; VIH .;; 5.5 V
5.5 V .;; VIH .;; VCCl

IIH

Input LOW Current
-0.3 V.;; VIL .;; 0.8 V for INH1, INH2,
-0.3 V.;; VIL .;; 0.4 V for WDS

IlL

Leakage Current Immunity (INH2, High "Z" State)

-

/-LA

12

IZ

Output LOW Voltage RESET (lOL = 6.0 rnA)

VOL

Output HIGH Current RESET (VOH = 5.5 V)

VOH

NOTES:
8. Temperature range Tlow .;; TJ .;; Thigh applies to this Electrical Characteristics section.
9. For test purposes, a negative pulse is applied to Pin 4 (- 2.5 V", V4 '" - 5.5 V).

3-1062

/-LA

±20

-

-

-

-

0.4

V

-

20

/-LA

/-LA

TCA5600, TCF5600
TYPICAL CHARACTERISTICS
FIGURE 1 -

REFERENCE VOLTAGE versus SUPPLY VOLTAGE

24

'>
~ 2.0

+

I

/

~

3

II

§2 1.6

NC

12

15

LU

u

~

1.2

:i! 0.8

I

~

~0.4
:>

1

o

/

I

/

NC 4

/
R5
10 k

I

2.0

1.0

1-----+--0 Voutl

17

NC

3.0 4.0 5.0
10
20
VCC1, SUPPLY VOLTAGE (VI

Vref nom

I

30 40

FIGURE 2 -

REFERENCE STABILITY versus TEMPERATURE

TCA5600

+ 60

'> +40

.s

~ +20

~
...............

Q

~

§2 - 20

~

h....r-.,

'"
I--'""

~
/

V ....

RSC
0.5 n

~

~

~ ~
.............
V
~

---r--

NC

12

NC

4

,}-40
...,

..............

- 60

NC

-25

o

r--......
R5
10 k

25
50
75
100
TJ, JUNCTION TEMPERATURE (OCI

FIGURE 3 -

70

~60
050
~
~ 40

II

125

150

..lVref~

-=-

-=- Vref nom

l

Vref

RSC
0.5 n

II

Vou~

l

>=

VCel

30

NC

12

15

NC 4
17

NC

~ 20
0: 10

~

1.0 k

+ C4

RIPPLE REJECTION versus FREQUENCY

o

~

ILFI
10

-<0.

TCF5600
- 50

1-----+--0 Vout 1

17

.... ~

01
BD242SP

15

10 k

100 k

1.0 M

f, FREQUENCY (Hzl

3-1063

01
BD242SP
~--..--oVoutl

TCA5600, TCF5600
FIGURE 4 -

STAND-BY CURRENT versus SUPPLY VOLTAGE

RSC

0.5

_V

/"

NC 12

i-'

/
V

NC

n

15

4

I - -......--c Vou t1

I
R5
10 k

2.0

1.0

3.0 4.0 5.0
10
20
VCC1, SUPPLY VOLTAGE (VI

I

30 40

FIGURE 5 - POWER-UP BEHAVIOR OF THE 5.0 V REGULATOR

RSC
0.5

+
f--- -1---

--tt

f-

lout1

=

n

300 rnA
NC 12

15

NC 4

1+--__- - 0 V ou t1

17
NC

R5

10 k

2.0

1.0

3.0 4.0 5.0
10
20
VCC2, SUPPLY VOLTAGE (VI

FIGURE 6 -

30 40

FOLDBACK CHARACTERISTICS OF THE 5.0 V REGULATOR

7.0

~

5.0

0

4.0

~

3.0

>

RSC

VCC2

6.0

0.511

+

:>

)

I

~

'j2.0
u

> 1.0

/

/

fav
V I

1/24 V

NC 12

VCC2 ~ 20 V

+

/
V

100

200
300
400
500
lout1, OUTPUT CURRENT (mAl

NC 4

VCC1-=-

l

15
17

NC

~C4

100 !~O!iF

R5

3-1064

BD242SP

1+--__- - 0 Vou t1
lout1 +

10 k

600

Q1

TCA5600, TCF5600

FIGURE 7 -

UNDERVOLTAGE LOCKOUT CHARACTERISTICS

RSC
0.5 !1

+

./

t:J

I

iL'.

VCC1

~

a:

NC

~

3
2

15

NC 12

~ 4
o

4

1-.--+--0 Vou t1

17

t

NC

I~
>1

R5

o/\
1.0
o

10 k

2.0

3.0

4.0

5.0

6.0

8.0

7.0

Vout 1, OUTPUT VOLTAGE (VI

FIGURE 8 -

I

OUTPUT CURRENT CAPABILITY OF THE PROGRAMMING REGULATOR

28

RSC
0.5 !!

24
I
I

~ 20

I
I

t:J

~ 16
§;

~

12

(f)

8.0

~

~

_.

NC

:

-_..

01

15

NC 12

I
I

BD242SP
1 - - -.......--0 Vou t1

13

+

VCC!l

I,C4

X°l-'F

I

I

4.0

:

o

o

~

20

~
~
100
lout2' OUTPUT CURRENT ImAI

1~

FIGURE 9 -

140

Rout 2

160

5.0 k

COLLECTOR CURRENT DETECTION LEVEL

RSC
0.5 !l

16

01
BD242SP

r - -.......--o V out1
+

o
o

I,C4

X°l-'F

V12(HI

V12(LI

R5
10 k

100

200

300

400

500

V12, CURRENT SENSE VOLTAGE ImVI

3-1065

TCA5600, TCF5600

FIGURE 10 -

POWER SWITCH CHARACTERISTICS

1.8

t5
~

1.6

§;1.4

+

z

o

VCC1

~ 1.2

12

=>

!;;:

en

NC

1.0

15

4

1--4--oVou t1

17

80.8

>

I--- 1--1-

I-

0.6

10

I--

20

30

50

+

NC

Fr C4

10!L~
80 100

200

300

500

800

R5
10 k

IClO, COLLECTOR CURRENT (mAl

I

FIGURE 11 -

RECTIFIER CHARACTERISTICS

1.8
~1.6

I'

NC 12
NC

15

4

17

V

_t--r-

NC

I----

0.6
10

20

30

50

80 100

200

300

500

800

IF, RECTIFIER CURRENT ImA)

FIGURE 12 -

INH 2 LEAKAGE CURRENT IMMUNITY

28
~

t5
~

Vout 2

24
20

§; 16
Spec. Limits

f-

~

o=>

12

High

NC

"z" State

jao

4

I---~--O

IZ

4.0
V10

o
- 40

- 30

- 20

-10
0
10
IZ, LEAKAGE CURRENT I!LA)

I
20

30

40

3-1066

R5
10 k

Vou t1

TCA5600, TCF5600
APPLICATIONS INFORMATION
(See Figure 18)
1. VOLTAGE REFERENCE Vref
The voltage reference Vref is based upon a highly
stable bandgap voltage reference and is accessible on
Pin 5 for additional tasks. This circuit part has its own
supply connection on Pin 3 and is therefore able to
operate in standby mode. The RC network R3, C6 improves the ripple rejection on both regulators.

FIGURE 14 -

VOLTAGE AND CURRENT WAVEFORM ON
THE COIL (not to scale)

2. DC/DC CONVERTER
The dc/dc converter performs according to the fly
back principle and does not need a time base circuit.
The maximum coil current is well defined by means of
the current sensing resistor R1 under all working conditions (start-up phase, circuit overload, wide supply
voltage range and extreme load current change). Figure
13 shows the simplified converter schematic:
FIGURE 13 -

I

SIMPLIFIED CONVERTER SCHEMATIC

VCC2 ---+---

I~~o I'H
Control Feedback

10

The time ratio a for the charging time to dumping time
is defined by equation (3):
t1
t2

VL +
VL-

(3)

a=-=--

The coil charging time t1 is found using equation (4):
(4)

t1 = - - - (1 + ~). f
a

(f : min. oscillation frequency which should be chosen
above the audio frequency band (e.g. 20 kHz))

A simplified method on "how to calculate the coil in-

ductance" is given below. The operation point at min.
supply voltage (VCC2) and max. output current (l out 2)
for a fixed output voltage (V out 2) determines the coil
data. Figure 14 shows the typical voltage and current
wave forms on the coil L 1 (coil losses neglected).
The equations (1) and (2) yield the respective coil voltage VL - and VL + (see Figure 14):
VL + = V out 2 + ~V(Pin 9 - Pin 8) + VF - VCC2(1)
VL - = VCC2 - VCE(sat) - V12(H)
(2)
(~V(Pin 9 - Pin 8): input/output voltage drop of the
regulator, 2.5 V typical)

(VF, VCE(sat), V12(Hr see electrical characteristics)

Knowing the dc output current lout2 of the programmable regulator, the peak coil current IL(peak) can now
be calculated:
IL(peak) = 2 . lout2 . (1

+

a)

(5)

The coil inductance L 1 of the nonsaturated coil is given
by equation (6):
L1 = _t_1_. VL IL(peak)

(6)

The formula (6a) yields the current sensing resister R1
for a defined peak coil current IL(peak):
R1 = V12(H)
Il(peak)

(6a)

TCA5600, TCF5600
In order to limit the by-pass current through capacitor
C7 during the energy dumping phase the value C2»C7
should be implemented.

FIGURE 16 -

TYPICAL E2pROM PROGRAMMING
SEQUENCE (not to scale)

For all other operation conditions, the feedback signal
from the programmable voltage regulator controls the
activity of the converter.
I

3. PROGRAMMABLE VOLTAGE REGULATOR
This series voltage regulator is programmable by the
voltage divider R4, R5 for a nominal output voltage
6.0 V,,:; V ou t2 ,,:; 30 V.

I

5.0 V"'"I-.,...--.,.-----'

R4 = (V out 2 - Vref nom) . R5
Vref nom
(R5 = 10k, Vref nom = 2.5 V)

I.-prOgramming
Voltage Vpp

Vout2i

I

(7)

~"0"~~_:_I--'--.;____,
I
I
I
1

l

I High "z" I
" " ' - ~ 1-.------

INH21

I

Current limitation and thermal shutdown capability are
standard features of this regulator. The voltage drop
AV(Pin 9 - Pin 8) across the series pass transistor generates the feedback signal to control the dc/dc converter
(see Figure 13).

"0" :

FIGURE 15 -INH1, INH2 TRUTH TABLE
INH1

INH2

1

0
0
0

0
High "Z"

1
1
1

0
High "Z"

2

3
4
5
6
INT:
ON:

OFF:

1

,

Vout2
OFF
Vout 2
Vout2
OFF
5.0 V
5.0 V

~

r-----1

The current limitation circuit measures the emitter
current of 01 by means of the sensing resistor RSC'

4. CONTROL INPUTS INH1, INH2
The dc/dc converter and/or the regulator V ou t2 are
remote controllable through the TTL, MOS compatible
inhibit inputs INH1 and INH2 where the latter is a 3-level
detector (Logic "0", high impedance "Z", Logic "1").
Both inputs are setup to provide the following truth
table:

Mode

1

(8)

(IE: emitter current of 01)
(VRSC: threshold voltage (see electrical characteristics))
The voltage protection circuit performs a fold-back characteristic above a nominal operating voltage
VCC2? 18 V.

dc/de
INT
ON
INT
INT
ON
INT

Intermittent operation of the converter means that the
converter operates only if VCC2