1984_TI_High Speed_CMOS_Logic_Data_Book 1984 TI High Speed CMOS Logic Data Book
User Manual: 1984_TI_High-speed_CMOS_Logic_Data_Book
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.
High--speed
CMOS Logic
DataBooK
1984
-
--
~
,
Silicon-gate
. _.,
. Complementary MOS ..
•
TEXAS
INSTRUMENTS
SCLD001A
GENERAL INFORMATION
I
RATINGS AND CHARACTERISTICS
HCMOS DEVICES
HCMOS DEVICES - ADVANCE INFORMATION
HCMOS DEVICES -
PRODUCT PREVIEWS
EXPLANATION OF LOGIC SYMBOLS
DESIGNERS' INFORMATION
MECHANICAL DATA
High--speed CMOS Logic
Data Book
TEXAS
INSTRUMENTS
IMPORTANT NOTICE
Texas Instruments reserves the right to make changes at any time
in order to improve design and to supply the best product possible.
TI cannot assume any responsibility for any circuits shown or represent
that they are free from patent infringement.
Information contained herein supersedes data published in the HighSpeed CMOS Logic Data Book, 1983, SCLD001.
ISBN 0-89512-114-X
Library of Congress No. 82-074480
Copyright © 1984, Texas Instruments Incorporated
INTRODUCTION
The high-speed silicon-gate CMOS logic family (SN54HC/SN74HC) from Texas Instruments offers a broad range
of functions: from basic gates and flip-flops to bus-compatible complex devices. These devices are pin-for-pin
and functionally compatible (but not necessarily interchangeable) with the corresponding devices in the popular
LSTTL family. Also, many of the metal-gate CMOS devices (4000 series) and TTL-voltage-compatible functions
('HCT) are available in the high-speed CMOS logic family from Texas Instruments.
The original CMOS devices were used in applications where the main concerns were low power consumption,
wide power supply range, and high noise immunity. These requirements were satisfied by the metal-gate CMOS
family. However, metal-gate CMOS could not satisfy system designs that required high speeds such as those
imposed by microprocessor-based applications. For such designs, the system designers used faster families
(STTL and LSTTL), and thus traded the advantages of CMOS for faster switching speeds. With the introduction
of the high-speed CMOS family, Texas Instruments now provides the system designer with the best of both
TTL and CMOS; fast switching speeds (comparable to LSTTL) and most of the advantages of CMOS.
The drawbacks of metal-gate CMOS arise because the source and drain areas are diffused before the gate is
defined (Figure 1), and therefore the metal gate needs to overlap the source and drain to allow for misalignment,
resulting in higher gate capacitances. Junction capacitance is increased by the deep diffusions required for the
source and drain. The slow switching speeds are a result of the combined gate and junction capacitances.
New generations of CMOS technology (high-speed CMOS or HCMOS) have now evolved through improvements
in process technology. High speeds and low power consumption have been made possibie by the 3-j.tm, selfaligned poly-silicon-gate CMOS process. In this process, poly-silicon gates are deposited over the gate oxide
before the source and drain implants are made (Figure 2). Then the gate itself is used as a mask for the source
and drain implants. This self-aligning process results in reduced gate capacitance. Junction capacitance, a function
of the junction area, is also minimized on a per gate basis through shallower implants and minimal sideways
diffusion. The net result is an increase in the switching speeds. An added benefit of the self-aligning feature
is that it permits smaller channel lengths, hence smaller gates and less gate capacitance. This corresponds to
higher gate densities and further reduction in power consumption.
-
FIGURE 1. METAL-GATE CMOS
FIGURE 2. HIGH-SPEED SILICON-GATE CMOS
Designers' Information (Section 7) provides detailed discussion of interchangeability, electrostatic discharge
(ESD) protection, latch-up circuitry, design considerations, interfacing, and other pertinent subjects regarding
this family.
v
ATTENTION
These devices contain circuits to protect the inputs and outputs
against damage due to high static voltages or electrostatic fields,
however, it is advised that precautions be taken to avoid application
of any voltage higher than maximum-rated voltages to these highimpedance circuits.
Unused inputs must always be connected to an appropriate logic
voltage level, preferably either Vee or ground.
vi
GENERAL INFORMATION
RATINGS AND CHARACTERISTICS
HCMOS DEVICES
HCMOS
DEVICES~ADVANCE
INFORMATION
HCMOS .DEVICES ·..;....PRODUCT PREVIEWS
EXPLANATION· OF LOGIC SYMBOLS
DESIGNERS' .INFORMATION
MECHANICAL DATA
1-1
II
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m
m
2
:7J
»
r-
-2
o"
:7J
3:
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-f
o2
ATTENTION
These devices contain circuits to protect the inputs and outputs
against damage due to high static voltages or electrostatic fields,
however, it is advised that precautions be taken to avoid application
of any voltage higher than maximum-rated voltages to these highimpedance circuits.
Unused inputs must always be connected to an appropriate logic
voltage level, preferably either Vee or ground.
1-2
NUMERICAL INDEX
TYPE
NUMBER
'HCOO
'HC02
'HC03
'HC04
'HCU04
'HC05
'HC08
'HC09
'HC10
'HCll
'HC14
'HC20
'HC21
'HC27
'HC30
'HC32
'HC36
'HC42
'HC51
'HC73
'HC74
'HC75
'HC76
'HC77
'HC78
'HC85
'HC86
'HC107
'HC109
'HCl12
'HCl13
'HCl14
'HC123
'HC125
'HC126
'HC132
'HC133
'HC137
'HCT137
'HC138
'HCT138
'HC139
'HC147
'HC148
'HC151
'HC152
'HC153
'HC154
'HC157
'HC158
'HC160
'HC161
'HC162
'HC163
'HC164
'HC165
'HC166
'HC173
'HC174
'HC175
'HC180
'HC181
'HC182
'HC189
RATINGS AND
CHARACTERISTICS t
PAGE
TABLE
I
I
I
I
IX
V
I
II
II
II
II
II
II
IV
I
II
II'
II
II
II
IV
III
III
I
I
IV
VIII
IV
VIII
IV
IV
IV
III
III
III
IV
III
III
IV
IV
IV
IV
IV
IV
IV
III
IV
II
IV
IV
IV
III
2-4
2-4
2-4
2-4
2-16
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-10
2-4
2-6
2-6
2-6
2-6
2-6
2-6
2-10
2-4
2-6
2-6
2-6
2-6
2-6
2-10
2-8
2-8
2-4
2-4
2-10
2-15
2-10
2-15
2-10
2-10
2-10
2-8
2-8
2-8
2-10
2-8
2-8
2-10
2-10
2-10
2-10
2-10
2-10
2-10
2-8
2-10
2-6
2-10
2-10
2-10
2-8
DESCRIPTIVE
INFORMATION
PAGE
3-3
3-5
3-7
3-9
3-11
3-13
3-15
3-17
3-19
3-21
3-23
3-25
3-27
3-29
3-31
3-33
3-35
3-37
3-39
4-3
3-41
3-43
3-45
3-47
4-5
4-7
3-49
3-51
3-55
3-59
3-63
3-65
5-3
3-69
3-69
5-5
3-73
3-75
3-79
3-83
3-87
3-91
3-93
3-93
3-99
3-103
3-107
4-9
3-111
3-111
3-115
3-115
3-115
3-115
3-127
3-131
3-135
3-139
3-143
3-143
3-147
3-149
5-7
4-11
*
TYPE
NUMBER
RATINGS AND
CHARACTERISTICS t
TABLE
PAGE
'HCT189
'HC190
'HC191
'HC192
'HC193
'HC194
'HC195
'HC219
'HCT219
'HC221
'HC237
'HCT237
'HC238
'HCT238
'HC239
'HC240
'HCT240
'HC241
'HCT241
'HC242
'HCT242
'HC243
'HCT243
'HC244
'HCT244
'HC245
'HCT245
'HC251
'HC253
'HC257
'HC258
'HC259
'HC266
'HC273
'HC280
'HC283
'HC292
'HC294
'HC298
'HC299
'HC322
'HC323
'HC352
'HC353
'HC354
'HC356
'HC365
'HC366
'HC367
'HC368
'HC373
'HCT373
'HC374
'HCT374
'HC375
'HC377
'HC378
'HC379
'HC381
'HC382
'HC386
'HC390
'HC393
'HC423
VII
IV
IV
IV
IV
IV
IV
III
VII
IV
tv
VIII
IV
VIII
IV
III
VII
III
VII
III
VII
III
VII
III
VII
III
VII
III
III
III
III
IV
I
IV
IV
IV
IV
IV
IV
II
II
III
VII
II
IV
IV
II
IV
IV
I
IV
IV
IV
2-14
2-10
2-10
2-10
2-10
2-10
2-10
2-8
2-14
2-10
2-10
2-15
2-10
2-15
2-10
2-8
2-14
2-8
2-14
2-8
2-14
2-8
2-14
2-8
2-14
2-8
2-14
2-8
2-8
2-8
2-8
2-10
2-4
2-10
2-10
2-10
2-10
2-10
2-10
2-8
2-8
208
2-8
2-8
2-8
2-8
2-8
2-8
2-8
2-8
2-8
2-14
2-8
2-14
2-6
2-10
2-10
2-6
2-10
2-10
2-4
2-10
2-10
2-10
DESCRIPTIVE
INFORMATION
PAGE
4-15
3-155
3-155
3-163
3-163
3-171
3-175
4-11
4-15
5-9
3-179
3-183
3-187
3-191
3-195
3-197
3-201
3-197
3-201
3-207
3-209
3-207
3-209
3-213
3-217
3-219
4-19
3-221
3-225
3-229
3-229
3-233
3-237
3-239
3-243
4-21
5-11
5-11
3-245
4-25
4-31
4-37
3-249
3-253
4-43
4-47
3-257
3-257
3-257
3-257
3-261
4-51
3-265
4-55
4-59
3-269
3-269
3-269
5-17
5-17
3-273
3-275
3-275
5-21
*
II
2:
0
t=
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~
a:
0
LL
2:
....
«a:
W
2:
W
(!'
tSee these pages for absolute maximum ratings, recommended operating conditions, and electrical characteristics.
tSee these pages for description, pin assignments, timing requirements, and switching characteristics .
•
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
1-3
NUMERICAL INDEX
TYPE
NUMBER
II
C)
m
m
2
::D
l>
r-
:2
."
0
::D
s:
l>
-t
0
2
'HC490
'HC533
'HCT533
'HC534
'HCT534
'HC540
'HCT540
'HC541
'HCT541
'HC563
'HCT563
'HC564
'HCT564
'HC573
'HCT573
'HC574
'HCT574
'HC589
'HC590
'HC592
'HC593
'HC594
'HC595
'HC597
'HC598
'HC604
'HC620
'HCT620
'HC623
'HCT623
'HC630
'HC632
'HC640
'HCT640
'HC643
'HCT643
'HC645
'HCT645
'HC646
'HCT646
'HC648
'HCT648
'HC651
'HCT651
'HC652
'HCT652
'HC658
'HCT658
'HC659
'HCT659
'HC664
'HCT664
'HC665
'HCT665
'HC670
RATINGS AND
CHARACTERISTICSt
PAGE
TABLE
IV
III
VII
III
VII
III
VII
III
VII
III
VII
III
VII
III
VII
III
VII
III
III
IV
III
IV
III
IV
III
III
III
VII
III
VII
III
III
III
VII
III
VII
III
VII
III
VII
III
VII
III
VII
III
VII
III
VII
III
VII
III
VII
III
VII
III
2·10
2·8
2·14
2·8
2·14
2·8
2·14
2·8
2·14
2·8
2·14
2·8
2·14
2·8
2·14
2·8
2·14
2·8
2·8
2·10
2·8
2·10
2·8
2·10
2·8
2·8
2·8
2·14
2·8
2·14
2·8
2·8
2·8
2·14
2·8
2·14
2·8
2·14
2·8
2·14
2·8
2·14
2·8
2·14
2·8
2·14
2·8
2·14
2·8
2·14
2·8
2·14
2·8
2·14
2·8
DESCRIPTIVE
INFORMATION;
PAGE
3·281
4·61
4·65
4·69
5·23
4·73
4·77
4·73
4·77
3·285
3·289
3·293
3·297
3·301
3·305
3·309
3·313
4·81
4·87
5·27
5·27
5·31
5·33
5·35
5·35
3·317
3·321
4·89
3·321
4·89
5·41
5·45
4·93
4·97
4·93
4·97
4·93
4·97
3·325
3·331
3·325
3·331
3·337
3·343
3·337
3·343
3·349
3·357
3·349
3·357
3·363
3·371
3·363
3·371
5·55
TYPE
NUMBER
RATINGS AND
CHARACTERISTICS t
TABLE
PAGE·
'HC673
'HC674
'HC677
'HC678
'HC679
'HC680
'HC682
'HC684
'HC686
'HC688
'HC690
'HC691
'HC692
'HC693
'HC696
'HC697
'HC698
'HC699
'HC804
'HC805
'HC808
'HC832
'HC881
'HC882
'HC4002
'HC4016
'HC4017
'HC4020
'HC4022
'HC4024
'HC4040
'HC4049
'HC4050
'HC4051
'HC4052
'HC4053
'HC4060
'HC4061
'HC4075
'HC4078A
'HC4316
'HC4511
'HC4514
'HC4515
'HC4724
'HC7001
'HC7002
'HC7003
'HC7006
'HC7022
'HC7032
'HC7074
'HC7266
'HC7340
III
III
III
III
III
III
IV
IV
IV
IV
I
IV
IV
I
2·8
2·8
2·8
2·8
2·8
2·8
2·10
2·10
2·10
2·10
2·8
2·8
2·8
2·8
2·8
2·8
2·8
2·8
2·8
2·8
2·8
2·8
2·10
2·10
2·4
IV
IV
IV
IV
IV
2·10
2·10
2·10
2·10
2·10
IV
I
I
I
2·10
2·4
2·4
2·4
IV
IV
IV
IV
I
I
I
I
IV
I
II
I
III
2·10
2·10
2·10
2·10
2·4
2·4
2·4
2·4
2·10
2·4
2·6
2·4
2·8
tSee' these pages for absolute maximum ratings, reco~mended operating conditions, and electrical characteristics.
*See these pages for description, pin assignments, timing requirements, and switching characteristics.
1-4
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
DESCRIPTIVE
INFORMATION;
PAGE
4·103
4·103
4·109
4·109
4·115
4·115
4·121
4·121
4·121
4·127
4·129
4·129
4·129
4·129
4·137
4·137
4·137
4·137
3·377
3·379
3·381
3·383
5·57
5·59
3·385
5·61
4·145
3·387
4·149
3·391
3·395
5·63
5·63
5·65
5·65
5·65
3·399
3·403
3·407
3·409
5·67
5·69
5·71
5·71
3·411
5·75
5·77
5·79
5·81
4·153
5·85
4·157
3·415
4·163
FUNCTIONAL INDEX/SELECTION GUIDE
PAGE
FUNCTIONS
AND/NAND Gates, Buffers, and Inverters .......................................... .
OR, NOR, Exclusive-OR, and AND-OR-Invert Gates ................................... .
Gate Buffer/Drivers ........................................................... .
Schmitt-Trigger Gates and Inverters ............................................... .
Multi-Function Circuits (Combinations of SSI Functions) ................................ .
Shift Registers .............................................................. .
Register Files ...................................... ~ ........................ .
D-Type Flip-Flops ............................................................ .
Latches and Registers .................. ' ....................................... .
Monostable Multivibrators ...................................................... .
Bus Drivers and Transceivers with 3-State Outputs ................................... .
Dual J-K Flip-Flops ........................................................... .
Bus Drivers and Transceivers with 3-State Outputs and TTL-Compatible Inputs .............. .
Asynchronous (Ripple-Clock) Counters ............................................. .
Programmable Frequency Dividers/Timers .......................................... .
Synchronous Counters ........................................................ .
Magnitude Comparators, Parity Generators/Checkers, and Priority Encoders ................. .
Address Comparators ........." ............................ '.................... .
Arithmetic Circuits ........................................................... .
Error Detectors/Correctors ...................................................... .
Data Selectors/Multiplexers ..................................................... .
Decoders/Demultiplexers ........................•...............................
Display Decoders/Drivers ....................................................... .
Analog Switches/Multiplexers/Demultiplexers ........................................ .
Random Access Memories ...................................................... .
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
1-6
1-6
1-6
1-7
1-7
1-7
1-7
1-8
1-8
1-8
1-9
1-9
1-10
1-10
1-10
1-11
1-11
1-12
1-12
1-12
1-12
1-13
1-13
1-13
1-13
II
:2
0
i=
«
:!
a:
0
LL
-
:2
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W
Z
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0
1-5
FUNCTIONAL INDEX/SELECTION GUIDE
AND, NAND GATES, BUFFERS, AND INVERTERS
II
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m
Z
m
lJ
l>
r-
z
o"
lJ
S
DESCRIPTION
Hex Inverters
Hex Unbuffered Inverters
OUTPUT
DEVICE
TYPE
TYPE
RATINGS AND
CHARACTERISTICS
TABLE
PAGE
Totem-pole
'HC04
Open-drain
I
2-4
Totem-pole
'HC05
'HC4049
-
-
5-63
Totem-pole
'HCU04
IX
2-16
3-11
'HC4050
-
-
5-63
Hex Buffers
'HC4061
Quad 2-lnput NAND Gates
Quad 2-lnput AND Gates
DESCRIPTIVE
INFORMATION
Totem-pole
'HCOO
Open-drain
'HC03
Totem-Pole
'HC08
Open-drain
'HC09
3-9
3-13
3-403
3-3
I
2-4
3-7
3-15
3-17
Hex 2-lnput NAND Drivers
'HC804
Hex 2-lnput AND Drivers
'HC808
Triple 3-lnput NAND Gate.s
'HC10
3-19
'HC11
3-21
III
2-8
3-377
3-381
l>
Triple 3-lnput AND Gates
Dual 4-lnput NAND Gates
o
z
Dual 4-lnput AND Gates
'HC21
8-lnput NAND Gates
'HC30
3-31
13-lnput AND Gates
'HC133
3-73
::j
Totem-pole
'HC20
I
2-4
3-25
3-27
OR, NOR, EXCLUSIVE-OR, AND AND-OR-INVERT GATES
DESCRIPTION
OUTPUT
DEVICE
TYPE
TYPE
Quad 2-lnput NOR Gates
Quad 2-lnput OR Gates
Quad 2-lnput Exclusive-NOR Gates
Totem-pole
Quad 2-lnput Exclusive-OR Gates
3-35
'HC32
3-33
I
2-4
3-415
'HC266
3-237
'HC86
3-49
3-273
'HC386
Hex 2-lnput OR Drivers
'HC832
Totem-pole
DESCRIPTIVE
INFORMATION
3-5
'HC805
Triple 3-lnput NOR Gates
PAGE
'HC36
Hex 2-lnput NOR Drivers
Dual 2-Wide 2-lnput AND-OR-Invert Gates
TABLE
'HC02
'HC7266
Open-drain
RATINGS AND
CHARACTERISTICS
III
2-8
3-379
3-383
'HC51
3-39
'HC27
3-29
Triple 3-lnput OR Gates
'HC4075
Dual 4-lnput NOR Gates
'HC4002
I
2-4
3-407
3-385
8-lnput ORINOR Gates
'HC4078A
3-409
GATE BUFFER/DRIVERS
,
DEVICE
DESCRIPTION
1-6
TYPE
Hex 2-lnput NAND Drivers
'HC804
Hex 2-lnput AND Drivers
'HC808
Hex 2-lnput NOR Drivers
'HC805
Hex 2-lnput OR Drivers
'HC832
TEXAS
'1.!1
INSTRUMENTS
. POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
RATINGS AND
CHARACTERISTICS
TABLE
PAGE
DESCRIPTIVE
INFORMATION
3-377
III
2-8
3-381
3-379
3-383
FUNCTIONAL INDEX/SELECTION GUIDE
SCHMITT-TRIGGER GATES AND INVERTERS
DESCRIPTION
Hex Inverters
OUTPUT
DEVICE
TYPE
TYPE
Open-drain
Quad 2-lnput AND Gates
Totem-pole
Quad 2-lnput OR Gates
DESCRIPTIVE
INFORMATION
3-23
'HC132
5-5
'HC7003
5-79
2-4
I
'HC7001
Quad 2-lnput NOR Gates
PAGE
TABLE
'HC14
Totem-pole
Quad 2-lnput NAND Gates
RATINGS AND
CHARACTERISTICS
5-75
'HC7002
5-77
'HC7032
5-85
RATINGS AND
DEVICE
CHARACTERISTICS
TYPE
TABLE
Inverter, 3-/4-lnput NAND/NOR Combination
'HC7006
I
Dual D-Type Flip-Flop, Inverter 2-lnput NAND/NOR Combination
'HC7074
II
I
I
I
PAGE
DESCRIPTIVE
INFORMATION
2-4
5-81
2-6
4-157
4-Bit Shift Registers with Clear
4-Bit Bidirectional Shift Registers
with Clear
OUTPUTS
INPUTS
«
oLL
Z
-I
«
a:
w
SHIFT REGISTERS
DESCRIPTION
z
o
i=
:E
a:
MULTI-FUNCTION CIRCUITS
DESCRIPTION
II
DEVICE
TYPE
RATINGS AND
CHARACTERISTICS
TABLE
PAGE
DESCRIPTIVE
zw
(!)
INFORMATION
J-K/Parallel
Parallel
'HC195
3-175
Serial/Parallel
Parallel
'HC194
3-171
2 Serial
'HC165
3-131
Parallel
'HC164
Serial
'HC166
3-135
Serial
'HC597
5-35
Serial/Parallel,
Clear, Clock Inhibit,
Shift/Load
8-Bit Shift Registers
2 Serial, Clear
IV
2-10
3-127
Serial/Parallel,
Clear, Clock Inhibit,
Shift/Load
8-Bit Shift Registers with
Input Registers
3-State Parallel
Serial/Parallel
(Multiplexed I/O)
Serial
8-Bit Shift Registers with
Output Registers
16-Bit Shift Registers
2-8
5-35
4-81
'HC589
'HC594
3-State. Parallel
'HC595
5-33 '
'HC299
4-25
(Multiplexed I/O)
Serial
III
3-State Serial
Parallel
3-State Parallel
Serial/Parallel
'HC598
'HC322
IV
2-10
III
2-8
5-31
4-31
'HC323
4-37
3-State Serial,
'HC673
4-103
Parallel
'HC674
4-103
REGISTER FILES
DESCRIPTION
4-by-4 Register Files
DEVICE
FEATURES
TYPE
3-State Outputs
'HC670
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
RATINGS AND
CHARACTERISTICS
TABLE
III
J
I
PAGE
2-8
DESCRIPTIVE
INFORMATION
5-55
1-7
FUNCTIONAL INDEX/SELECTION GUIDE
LATCHES AND REGISTERS
II
DESCRIPTION
Quad D-type Latches
OUTPUT
DEVICE
CONFIGURATION
TYPE
Complementary
'HC75
'HC375
Q only
Quad D-type Registers
Q only, 3-State
Q only, 3-State
Octal D-type Latches
Q only, 3-State
-2
."
Q only, 3-State
Octal D-type Latches with TTL-Compatible Inputs
o
Q only, 3-State
::xJ
s:
l>
8-Bit Addressable Latches
::j
PAGE
II
2-6
3-43
4-59
3-47
3-139
'HC373
'HC573
DESCRIPTIVE
INFORMATION
3-261
III
2-8
3-301
'HC533
4-65
'HC563
'HCT373
3-285
4-51
'HCT573
'HCT533
VII
2-14
'HCT563
'HC259
3-305
4-61
3-289
IV
2-10
3-411
3-233
MONOSTABLE MULTIVIBRATORS
o
2
TABLE
'HC77
'HC173
'HC4724
Q only
RATINGS AND
CHARACTERISTICS
DESCRIPTION
DEVICE
FEATURES
Dual Monostable Multivibrators
with Direct Clear, Positive and
Negative Inputs, and
Retriggerable
Complementary Outputs
TYPE
II
Will not Trigger from Clear
'HC221
'HC123
'HC423
RATINGS AND
CHARACTERISTICS
TABLE
PAGE
IV
2-10
DESCRIPTIVE
INFORMATION
5-9
5-3
5-21
D-TYPE FLIP-FLOPS
DESCRIPTION
Dual D-type Flip-Flops with
Preset and Clear
Dual D-type Flip-Flops with
2-lnput NAND/NOR Gates
Quad D-type Flip-Flops with
Common Clocks
Hex D-type Flip-Flops with
Common Clocks
Octal D-type
Flip~Flops
with
Common Clocks
Octal D-type Flip-Flops
with Common Clocks and
TTL-Compatible Inputs
1-8
OUTPUT
OTHER
DEVICE
CONFIGURATION
FEATURES
TYPE
Complementary
Complementary
Independent clocks,
Preset, and Clear
Independent clocks,
Preset, and Clear
Common Clear
RATINGS AND
CHARACTERISTICS
TABLE
PAGE
3-41
'HC74
'HC7074
DESCRIPTIVE
INFORMATION
II
2-6
4-"157
'HC175
'HC379
3-143
Output Enable
Common Clear
'HC174
3-143
Output Enable
'HC378
Q only
Common Clear
Output Enable
'HC273
3-State, Q only
Output control
Complementary
Q only
'HC574
'HC534
Output control
3-State, Q only
Output control
'HCT374
'HCT574
Output control
'HCT534
'HCT564
TEXAS
IV
2-10
..J.!}
POST OFFICE BOX 225012 • DALLAS" TEXAS 75265
3-239
\
III
2-8
3-309
4-69
3-293
4-55
'HC564
INSTRUMENTS
3-269
3-269
3-265
'HC377
'HC374
3-State, Q only
3-State, Q only
3-269
VII
2-14
3-313
5-23
3-297
FUNCTIONAL INDEX/SELECTION GUIDE
DUAL J-K FLIP-FLOPS
DEVICE
DESCRIPTION
TYPE
Dual J-K Flip-Flops with Clear
Dual J-K Flip-Flops with Preset
Dual J-K Flip-Flops with Preset, Common Clock, and Common Clear
Dual J-K Flip-Flops with Preset and Clear
Dual J-K Flip-Flops with Preset and Clear
'HC73
'HC107
'HCl13
'HC78
'HCl14
'HC76
'HCl12
'HC109
RATINGS AND
CHARACTERISTICS
TABLE
PAGE
DESCRIPTIVE
INFORMATION
4-3
II
2-6
3-51
3-63
4-5
3-65
3-45
3-59
3-55
BUS DRIVERS AND TRANSCEIVERS WITH 3-STATE OUTPUTS
DESCRIPTION
Quad Bus Drivers/Receivers
Quad Bus Transceivers
Hex Bus Drivers/Receivers
OUTPUT
CONTROL
DEVICE
DATA
INPUTS
TYPE
True
Inverting
True
True
Inverting
True
Inverting
Inverting
Octal Bus Drivers/Receivers
True
Octal Bus Transceivers
Inverting
True
Inverting
True and
Inverting
Individual Enables
Independent Enables
for A and B Buses
Common Enables
Symmetrical Enables
Symmetrical Enables
2 Enables
Complementary Enables
Symmetrical Enables
2 Enables
Independent Enables
for A and B Buses
Enable and
Direction Control
True
Octal Bus Transceivers with Registers
True
Inverting
Inverting
True
Octal Bus Drivers with Registers
Inverting
8-/9-Bit Bus Transceivers with Parity
Checker/Generator
True
Inverting
True
Inverting
Enable and
Direction Control
Independent Enables
for A and B Buses
Independent Enables
for A and B Buses
Enable and
Direction Control
Independent Enables
for A and B Buses
'HC125
'HC126
'HC242
'HC243
'HC365
'HC366
'HC367
'HC368
'HC240
'HC540
'HC241
'HC244
'HC541
'HC620
'HC623
'HC640
RATINGS AND
CHARACTERISTICS
TABLE
PAGE
INFORMATION
3-69
3-69
3-207
3-207
3-257
3-257
3-257
3-257
3-197
a:
o
LL
-
...I
Octal Bus Transceivers with Registers
True
Inverting
Inverting
PAGE
for A and B Buses
Symmetrical Enables
r-
2
o
TABLE
DESCRIPTIVE
INFORMATION
'HCT242
:a
."
RATINGS AND
CHARACTERISTICS
Individual Enables
True
l>
DEVICE
TYPE
Enable and
Direction Control
'HCT643
3-217
2-14
VII
4-97
'HCT645
4-97
'HCT245
'HCT646
'HCT648
4-19
3-331
3-331
Independent Enables
'HCT651
3-343
True
for A and B Buses
'HCT652
3-343
True
Enable and
'HCT659
3-357
8-/9-Bit Bus Transceivers with Parity
Inverting
Direction Control
'HCT658
3-357
Checker/Generator
True
Inverting
Independent Enables
for A and B Buses
'HCT665
'HCT664
3-371
3-371
ASYNCHRONOUS (RIPPLE-CLOCK) COUNTERS
DESCRIPTION
DEVICE
FEATURES
TYPE
RATINGS AND
CHARACTERISTICS
TABLE
PAGE
DESCRIPTIVE
INFORMATION
7-Bit Binary Counters
'HC4024
3-391
12-Bit Binary Counters
'HC4040
3-395
3-387
'HC4020
14-Bit Binary Counters
Dual Decade Counters
On-Chip Oscillator
Biquinary or BCD
'HC4060
Set-to-9 input
'HC490
'HC393
Dual 4-Bit Binary Counters
2-10
IV
3-399
3-275
. 3-281
'HC390
3-275
PROGRAMMABLE FREQUENCY DIVIDERS/TIMERS
DESCRIPTION
Programmable Frequency
Dividers/Digital Timers
1-10
DEVICE
FEATURES
TYPE
Programming range 22 to 2 15
Programming range 22 to 2 31
'HC294
'HC292
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
RATINGS AND
CHARACTERISTICS
TABLE
IV
I
PAGE
I 2-10
DESCRIPTIVE
INFORMATION
5-11
5-11
FUNCTIONAL INDEX/SELECTION GUIDE
SYNCHRONOUS COUNTERS
DESCRIPTION
Async Clear
Decade
Decade Counters with Output
Sync Clear
Sync Clear
Registers
Async Clear
Decade Up/Down
Clock Inhibit
Async Clear
Decade Up/Down Counters
Sync Clear
with Output Registers
Async Clear
Divide-by-8 Johnson Counter
Sync Clear
Divide-by-l0 Johnson Counter
Async Clear
4-Bit Binary
Async Clear
Sync Clear
4-Bit Binary Counters
DEVICE
FEATURES
TYPE
'HC160
Synchronous Load
Multiplexed 3-State Outputs
Multiplexed 3-State Outputs
Synchronous Load
Clock,lnhibit
Async Clear
Asynchronous Load
4-Bit Binary Up/Down Counters
Sync Clear
with Output Registers
Async Clear
8-Bit Binary with Input Registers
Sync Clear
Registers
'HC696
'HC4022
TABLE
PAGE
IV
2-10
III
2-8
IV
2-10
III
IV
.2-8
2-10
'HC161
4-Bit Binary Up/Down
Sync Clear
'HC698
'HC7022
'HC4017
Multiplexed 3-State Outputs
8-Bit Binary with Output
'HC690
'HC190
'HC192
Asynchronous Load
Sync Clear
Async Clear
with Output Registers
'HC162
'HC692
RATINGS AND
CHARACTERISTICS
'HC163
'HC693
'HC691
'HC191
'HC193
Multiplexed 3-State Outputs
'HC699
'HC697
'HC592
Multiplexed 3-State 110
'HC593
3-State Outputs
'HC590
DESCRIPTIVE
INFORMATION
3-115
3-115
4-129
4-129
3-155
3-163
4-137
4-137
4-149
4-153
4-145
3-115
3-115
III
2-8
IV
2-10
III
2-8
IV
2-10
III
2-8
4-129
4-129
3-155
3-163
4-137
II
z
o
i=
Q Outputs
P=Q Outputs
Even, Odd Inputs
TABLE
PAGE
4-7
'HC682
4-121
4-121
'HC684
'HC686
Enable Inputs
Inverting Outputs
True Outputs
IV
2-10
'HC688
'HC180
4-121
4-127
3-147
3-243
'HC659
III
2-8
3-349
Enable and
'HCT659
VII
2-14
3-357
Direction Control
'HC658
III
2-8
3-349
'HCT658
'HC665
VII
III
2-14
2-8
3-357
3-363
'HCT665
'HC664
VII
2-14
III
3-371
3-363
'HCT664
VII
2-8
2-14
IV
2-10
Independent Enables
Inverting Outputs
DESCRIPTIVE
INFORMATION
'HC85
'HC280
True Outputs
8-/9-Bit Bus Transceivers with
Parity Generator/Checkers
RATINGS AND
CHARACTERISTICS
for A and B Buses
8-Line to 3-Line Priority Encoders Enable Inputs and Outputs
10-Line Decimal to 4-Line
BCD Priority Encoders
TEXAS
'HC148
'HC147
"!1
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-371
3-93
3-93
1-11
FUNCTIONAL INDEX/SELECTION GUIDE
ADDRESS COMPARATORS
II
C)
m
DESCRIPTION
DEVICE
FEATURES
TYPE
Output Enable
Latched Output
Output Enable
Latched Output
16-Bit to 4-Bit Address Comparators
12-Bit to 4-Bit Address Comparators
I
\
'HC677
'HC678
'HC679
'HC680
RATINGS AND
CHARACTERISTICS
TABLE
PAGE
2-8
III
DESCRIPTIVE
INFORMATION
4-109
4-109
4-115
4-115
2
m
ARITHMETIC CIRCUITS
:D
:r>
r-
2
"o
:D
s:
:r>
-I
o2
DEVICE
TYPE
DESCRIPTION
4-Bit Arithmetic Logic Units/Function Generators
16 Functions
8 Functions
16 Functions
'HC181
'HC381
'HC881
'HC382
'HC283
'HC182
'HC882
4-Bit ALU with Ripple Carry
4-Bit Adders
16-Bit
32-Bit
Look-Ahead Carry Generators
RATINGS AND
CHARACTERISTICS
PAGE
TABLE
IV
2-10
DESCRIPTIVE
INFORMATION
3-149
5-17
5-57
5-17
4-21
5-7
5-59
ERROR DETECTORS/CORRECTORS
DEVICE
TYPE
DESCRIPTION
16-Bit Parallel Error Detection and Correction
32-Bit Parallel Error Detection and Correction
'HC630
'HC632
RATINGS AND
CHARACTERISTICS
TABLE
PAGE
I
III
I
2-8
DESCRIPTIVE
INFORMATION
5-41
5-45
DATA SELECTORS/MULTIPLEXERS
DESCRIPTION
INPUTS
DEVICE
TYPE
OUTPUTS
Inverting
Complementary
Enable
8-Line to 1-Line
1-12
RATINGS AND
CHARACTERISTICS
PAGE
TABLE
3-103
3-99
3-221
'HC152
'HC151
'HC251
Transparent Latches,
Enable
Registers, Enable
Dual 4-Line to l-Line
Independent Enables
Quad 2-Line to 1-Line
Common Enable
Quad 2-Line to l-Line
with Storage
Octal 2-Line to l-Line
Input Registers
Complementary
3-State
DESCRIPTIVE
INFORMATION
'HC354
4-43
True, 3-State
Inverting, 3-State
True
Inverting
True
Inverting
'HC356
'HC253
'HC353
'HC153
'HC352
'HC157
'HC158
True, 3-State
Inverting, 3-State
'HC257
'HC258
4-47
3-225
3-253
3-107
3-249
3-111
3-111
3-229
3-229
True
True, 3-State
TEXAS
III
2-8
'HC298
IV
2-10
3-245
'HC604
III
2-8
3-317
~
INSTRUMENTS
POST OFFICE BO·X 225012 • DALLAS, TEXAS 75265
FUNCTIONAL INDEX/SELECTION GUIDE
DECODERS/DEMULTIPLEXERS
DESCRIPTION
FEATURES
4-Line to 16-Line
DEVICE
OUTPUTS
TYPE
RATINGS AND
CHARACTERISTICS
TABLE
PAGE
2 Enables
Inverting
'HC154
4-9
Input Latches,
Output Enable
True
Inverting
'HC4514
'HC4515
5-71
5-71
4-Line to 10-Line
IV
2-10
'HC42
BCD-to-Decimal
'HC238
'HCT238
True
3 Enables
Inverting
3-Line to 8-Line
True
3 Enables,
Address Latches
Dual 2-Line to 4-Line
DESCRIPTIVE
INFORMATION
Inverting
Independent Enables
3-37
'HC138
VIII
IV
2-15
2-10
'HCT138
'HC237
VIII
IV
2-15
2-10
'HCT237
VIII
'HC137
IV
2-15
2-10
'HCT137
VIII
2-15
IV
2-10
Inverting
'HC139
True
'HC239
3-187
3-191
3-83
3-87
3-179
3-183
3-75
3-79
3-91
3-195
DEVICE
TYPE
BCD-to-7 -Segment Decoders/Drivers with Input Latches
'HC4511
2
o
i=
«
:e
a:
oLL
~
...I
«
a:
w
2
w
DISPLAY DECODERS/DRIVERS
DESCRIPTION
II
RATINGS AND
CHARACTERISTICS
TABLE
I
IV
I
PAGE
2-10
~
DESCRIPTIVE
INFORMATION
5-69
ANALOG SWITCHES/MULTIPLEXERS/DEMULTIPLEXERS
DEVICE
DESCRIPTION
TYPE
I
I
Quad Analog Switch/Transmission Gate
'HC4016
'HC4316
RATINGS AND
CHARACTERISTICS
PAGE
-
-
5-67
-
5-65
-
5-65
8-Channel Analog Multiplexer/Demultiplexer
'HC4051
Dual 4-Channel Analog Multiplexer/Demultiplexer
'HC4052
-
Triple 2-Channel Analog Multiplexer/Demultiplexer
'HC4053
-
Enable, Level Translators
DESCRIPTIVE
INFORMATION
TABLE
-
5-61 '
5-65
RANDOM ACCESS MEMORIES
DESCRIPTION
ORGANIZATION
DEVICE
TYPE
FEATURES
3-State Inverting Outputs
64-Bit
16 x 4
3-State Noninverting Outputs
TEXAS
RATINGS AND
CHARACTERISTICS
TABLE
PAGE
DESCRIPTIVE
INFORMATION
'HC189
III
2-8
4-11
'HCT189
VII
2-14
'HC219
'HCT219
III
VII
2-8
2-14
4-15
4-11
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
4-15
1-13
PARAMETER MEASUREMENT INFORMATION
FROM OUTPUT _ _ _ _
TEST
e
IpOINT
UNDER TEST
lCL
II
LOAD CIRCUIT
G')
m
2
m
:D
»
r-
clt
PARAMETER
or
tpd
tt
I
50 pF
Standard outputs
I
, 50 pF or , 50 pF
High-current outputs *
tCl includes probe and test fixture capacitance.
*High-current outputs are indicated by the t> in the logic symbol.
Z
"T1
o
FIGURE 1. TOTEM· POLE OUTPUTS
:D
s:
»
-4
--"'--VCC
o2
FROM OUTPUT _ _ _• TEST
UNDER TEST
POINT
lCL=SOPFt
LOAD CIRCUIT
tCl includes probe and test fixture capacitance.
FIGURE 2. OPEN·DRAIN OUTPUTS
PARAMETER
Rl
tpZH
ten
10-
tdis
I tpHZ
tpLZ
1 kO
tpZl
clt
50 pF
or
150 pF
, kO
50 pF
S,
S2
OPEN
CLOSED
CLOSED
OPEN
OPEN
CLOSED
CLOSED
OPEN
OPEN
OPEN
50 pF
tpd or tt
LOAD CIRCUIT
-
tCl includes probe and test fixture capacitance.
FIGURE 3. 3·STATE OUTPUTS
1·14
or
150 pF
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
.i.O%
REFERENCE
INPUT
_ _ _ _ _ _ _J
\----
MI'------th------I~~I
Vee
---- 0 V
If--tsu~
I
~~--------------~~
90%l\:
DATA~90%
INPUT
II
II
50%
10%
- - - VCC
~O%
~
__1_0%
_____ 0 V
~tf
;...rtr
II
z
o
i=
:2:
a:
«
VOLTAGE WAVEFORMS
NOTE 1: Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR s 1 MHz, Zout .. 50 0, tr = 6 ns, tf = 6 ns.
oLL
FIGURE 4. HC AND HCU - SETUP AND HOLD TIMES. AND INPUT RISE AND FALL TIMES
Z
..J
HIGH-LEVEL
PULSE
LOW-LEVEL
PULSE
/00'
«
a:
w
z
14
tw
~
tw
w
C!J
________t~ ---_
\~
I
Vcc
ov
VOLTAGE WAVEFORMS
NOTES:
1. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ::; 1 MHz, Zout .. 50 0, tr = 6 ns, tf = 6 ns.
2. For clock inputs, f max is measured when the input duty cycle is 50%.
FIGURE 5. HC AND HCU - PULSE DURATIONS
TEXAS
"-II
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
1-15
PARAMETER MEASUREMENT INFORMATION
\;-O%---------:~
INPUT-.i50%
II
m
2
I
I4--tpLH~
I4'-tPHL-----+l
II
IN-PHASE
OUTPUT
C)
,
.,..--------':.-----"".1.--- -
I,
90%
'90%
I
10%,
I
1
~trt
I
I
I4--tPHL-tI
m
::D
»
r-
90%j\;1
I
I 50%
I
10%
OUT -OF-PHASE
OUTPUT
2
o
::D
»
_I ~%
~tf
tt'.
'90%
50%
10%
,
."
VOH
50%
VOL
I4--tpLH---.!
tf~
3:
I
I '
I
1----
~trt
VOH
VOL
VOLTAGE WAVEFORMS
t tr is not applicable to SN54/74HCU' devices.
NOTE 1: Phase relationships between waveforms were chosen arbitrarily. A" input pulses are supplied by generators having the following
characteristics: PRR s 1 MHz, Zout '" 50 n, tr = 6 ns, tf = 6 ns.
:::!
FIGURE 6. HC AND HCU -
o
PROPAGATION DELAY TIMES AND OUTPUT TRANSITION TIMES
2
~
~~::.~e!e~~~!~~~
i'
to~
,'-----------1
---.r
50%
I+--- tpZL
I
OUTPUT
WAVEFORM 1
I
I
(See Note 2)
I
Vee
0V
14-- tpLz---+I
I,.,V
~5~%-
I "..-_ _ _
!/
ee
'\
!4-tpZH--.r
OUTPUT
WAVEFORM 2
_________
f
----------~--------
10%
I,
9~0~
, I ~------...;..----.....,i:1 9
50%
(See Note 2)
---------
"'Vee
-
-
- - - VOH
I4--tPHZ--+i
"" 0 V
VOLTAGE WAVEFORMS
NOTES:
1. Phase relationships between waveforms were chosen arbitrarily. A" input pulses are supplied by generators having the following
characteristics: PRR s MHz, Zout '" 50 n, tr = 6 ns, tf = 6 ns.
2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
, Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
FIGURE 7. HC AND HCU - ENABLE AND DISABLE TIMES, 3·STATE OUTPUTS
1-16
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1~
REFERENCE
INPUT
vi
\ .-. _-_-_-_ ::
~~---------th----------~.I
t4---tsu~
I
I~~~_ _ _-------~~I
DATA~2.7V
2.7Vl\:'
1 - - - - - 3V
INPUT
1.3 V
0.3 V
I
I
I
I
1.3 V
0.3 V
\..I-tf
~tr
0V
NOTE 1: Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR :s 1 MHz, Zout == 50 n, tr = 6 ns, tf = 6 ns.
FIGURE 8. HCT - SETUP AND HOLD TIMES, AND INPUT RISE AND FALL TIMES
_ _ _ _ _Jt1.3V
\~~:
-- -- -- - - : :
11111141-----tw,-----I.~1
\'~V
«
a:
oLL
~
...I
ItM---tw----tf,.
LOW·LEVEL
PULSE
2
o
i=
:!
VOLTAGE WAVEFORMS
HI~~'~;~EL
II
«
a:
w
zw
(!)
f~~ ________ ::
VOLTAGE WAVEFORMS
NOTES:
1. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR :s 1 MHz, Zout '" 50 n, tr = 6 ns, tf = 6 ns.
2. For clock inputs, f max is measured when the .input duty cycle is 50%.
FIGURE 9. HCT - PULSE DURATIONS
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
1-17
PARAMETER MEASUREMENT INFORMATION
\-;-.3-;;- -.- - - - ---
INPUT--'/,.3V
II
I
I
~tpLH----+t
I4---tPHL~
I
I
I
I
,
){190%
1.3V
10%
I
I
IN·PHASE
OUTPUT
I
I
I
I
I
~tr
14-- tpHL ---+I
tf
S
l>
:::!
_I
~%
itl ......
VOH
V
OL
90
..% - - VOH
I
I- - - -
VOL
-+/--f4-- tr
~
VOLTAGE WAVEFORMS
"T1
:xJ
I
90%1\1 - - 1.3V
,
~tf
k---tpLH---.!
I
-:
2
o
OV
90%1\;'
, :.3V
1.3V
J:_;.;.1,;;,;0%;.;;..._ _ _ _ _ _ _ _ _ _1,;,;0;,;,:%~
OUT-QF-PHASE
OUTPUT
3V
NOTE 1: Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ~ 1 MHz. Zout '" 50
tr = 6 ns. tf = 6 ns.
n.
FIGURE 10. HCT - PROPAGATION DELAY TIMES, OUTPUT RISE AND FALL TIMES
o
~
2:
OUTPUT CONTROL
(Low·level enabling)
3V
f__1•3_ V _ _ _ _ _ _ _ _ _ 0 V
. ,
13V
,
I ' -.-_ _ _ _ _ _ _ _- - J
1
I4--tPZL~
OUTPUT
WAVEFORM 1
(See Note 2)
,
I'I
r.-tpLZ--+l
I
I
~.'.3V
\
'/ ____
+10.::.
""Vee
VOL
14--- tpZH----"
I~_------_~-------11.3V
1\:,%----- VOH
OUTPUT
WAVEFORM 2
(See Note 2) _ _ _ _ _ _ _ _- J
If--- tPHZ--+t
"" 0 V
VOLTAGE WAVEFORMS
NOTES: 1. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ~ 1 MHz. Zout .. 50
tr = 6 ns. tf = 6 ns.
2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
n.
FIGURE 11. HCT -
1-18
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
EXPLANATION OF FUNCTION TABLES
The following symbols are now being used in function tables on TI data sheets:
H
high level (steady state)
L
low level (steady state)
II
2
transition from low to high level
o
i=
transition from high to low level
X
irrelevant (any input. including transitions)
Z
off (high-impedance) state of a 3-state output
a .. h
a:
o
LL
a before the indicated steady-state input conditions were established
level of
00
complement of
00 or level of Q before the indicated steady-state input conditions were established
level of a before the most recent active transition indicated by t or 1
Jl=
one high-level pulse
LJ =
one low-level pulse
TOGGLE
:!
the level of steady-state inputs at inputs A through H. respectively
00
On
«
~
...I
«
a:
w
2
w
each output changes to the complement of its previous level on each active transition indicated by
t or 1.
~
If. in the input columns. a row contains only the symbols H. L. and/or X. this means the indicated output is valid whenever
the input configuration is achieved and regardless of the sequence in which it is achieved. The output persists so long as the
input configuration is maintained.
If. in the input columns. a row contains. H. L. and/or X together with t and/or 1. this means the output is valid whenever the
input configuration is achieved but the transition(s) must occur following the achievement of the steady-state levels. If the
output is shown as a level (H. L. 00. or 60). it persists so long as the steady-state input levels and the levels that terminate
indicated transitions are maintained. Unless otherwise indicated. input transitions in the opposite direction to those shown
have no effect at the output. (If the output is shown as a pulse.
or 1.J. the pulse follows the indicated input
transition and persists for an interval dependent on the circuit.)
rL
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
1-19
EXPLANATION OF FUNCTION TABLES
Among the most complex function tables in this book are those of the shift registers. These embody most of the symbols used
in any of the function tables, plus more. Below is the function table of a 4-bit bidirectional universal shift register, e.g., type
SN74HC194.
II
FUNCTION TABLE
G')
m
:2
m
::D
l>
r-
:2
'"T1
o
::D
3:
CLEAR
L
H
H
H
H
H
H
H
MODE
S1So
X
X
H
L
L
H
H
L
X
X
H
H
H
L
L
L
INPUTS
SERIAL
CLOCK
LEFT RIGHT
X
X
X
X
X
L
X
X
t
H
X
t
X
L
t
H
X
t
L
X
t
X
X
X
OUTPUTS
PARALLEL
A
B
D
C
X
X
X
X
X
X
X
X
d
a
b
c
X
X
X
X
X
X
X
X
X
X
X
X
QAO QBO Oeo QDO
a
c
d
b
H
QAn OSn OCn
L
OAn OSn OCn
H
OSn OCn OOn
X
X
L
OSn OCn OOn
OAn OSn OCn ODO
X
X
X
X
X
X
QA
QB
QC
QD
L
L
L
L
l>
-I
o
:2
The first line of the table represents a synchronous clearing of the register and says that if clear is low, all four outputs will be
reset low regardless of the other inputs. In the following lines, clear is inactive (high) and so has no effect.
The second line shows that so long as the clock input remains low (while clear is high), no other input has any effect and the
outputs maintain the levels they assumed before the steady-state combination of clear high and clock low was established.
Since on other lines of the table only the rising transition of the clock is shown to be active, the second line implicitly shows
that no further change in the outputs will occur while the clock remains high or on the high-to-Iow transition of the clock.
The third line of the table represents synchronous parallel loading of the register and says that if S1 and SO are both high
then, without regard to the serial input, the data entered atAwili be at output OA, data entered at B will be at OB, and soforth,
following a low-to-high clock transition.
The fourth and fifth lines represent the loading of high- and low-level data, respectively, from the shift-right serial input and
the shifting of previously entered data one bit; data previously at OA is now at OB, the previous levels of OBand Oc are now at
Oc and 00 respectively, and the data previously at 00 is no longer in the register. This entry of serial data and shift takes
place on the low-to-high transition of the clock when S1 is low and SO is high and the levels at inputs A through 0 have no
effect.
The sixth and seventh lines represent the loading of high- and low-level data, respectively, from the shift-left serial input and
the shifting of previously entered data one bit; data previously at OB is now at OA, the previous levels of Oc and 00 are now at
OB and OC, respectively, and the data previously at OA is no longer in the register. This entry of serial data and shift takes
place on the low-to-high transition of the clock when 51 is high and SO is low and the levels at inputs A through 0 have no
effect.
The last line shows that as long as both mode inputs are low, no other input has any effect and, as in the second line, the
outputs maintain the levels they assumed before the steady-state combination of clear high and both mode inputs low was
established.
'-20
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
INTRODUCTION
These symbols, terms, and definitions are in accordance with those currently agreed upon by the JEOEC
Council of the Electronic Industries Association (EIA) for use in the USA and by the International
Electrotechnical Commission (lEC) for international use.
OPERATING CONDITIONS AND CHARACTERISTICS (IN SEQUENCE BY LETTER SYMBOLS)
Cpd
f max
II
z
o
Power dissipation capacitance
Used to determine the no-load dynamic power dissipation per logic function (see individual circuit
pages): Po = Cpd VCC 2 f + ICC VCC.
~
<
~
Maximum clock frequency
The highest rate at which the clock input of a bistable circuit can be driven through its required
sequence while maintaining stable transitions of logic level at the output with input conditions
established that should cause changes of output logic level in accordance with the specification.
a:
ou.
-Z
...I
ICC
Supply current
The current into* the VCC supply terminal of an integrated circuit.
<
a:
IIH
High-level input current
The current into * an input when a high-level voltage is applied to that input.
z
IlL
Low-level input current
The current into * an input when a low-level voltage is applied to that input.
IOH
High-level output current
The current into * an output with input conditions applied that, according to the product specification,
will establish a high level at the output.
IOL
Low-level output current
The current into * an output with input conditions applied that, according to the product specification,
will establish a low level at the output.
IOZ
Off-state (high-impedance-state) output current (of a three-state output)
The current flowing into * an output having three-state capability with input conditions established
that, according to the production specification, will establish the high-impedance state at the output.
VIH
High-level input voltage
An input voltage within the more positive (less negative) of the two ranges of values used to represent
the binary variables.
NOTE: A minimum is specified that is the least-positive value of high-level input voltage for which
operation of the logic element within specification limits is guaranteed.
VIL
Low-level input voltage
An input voltage level within the less positive (more negative) of the two ranges of values used to
represent the binary variables.
.
NOTE: A minimum is specified that is the most-positive value of low-level input voltage for which
operation of the logic element within specification limits is guaranteed.
w
w
o
*Current out of a terminal is given as a negative value.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
1-21
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
II
VOH
High-level output voltage
The voltage at an output terminal with input conditions applied that, according to product specification,
wi" establish a high level at the output.
VOL
Low-level output voltage
The voltage at an output terminal with input conditions applied that, according to product specification,
will establish a low level at the output.
VT+
Positive-going threshold level
The voltage level at a transition-operated input that causes operation of the logic element according
to specification as the input voltage rises from a level below the negative-going threshold voltage, VT _ .
VT-
Negative-going threshold level
The voltage level at a transition-operated input that causes operation of the logic element according
to specification as the input voltage falls from a level above the positive-going threshold voltage, VT + .
ta
Access time
The time interval between the application of a specified input pulse and the availability of valid signals
at an output.
tdis
Disable time (of a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms,
with the three-state output changing from either of the defined active levels (high or low) to a highimpedance (off) state. (tdis = tpHZ or tPLZ).
ten
Enable time (of a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms,
with the three-state output changing from a high-impedance (off) state to either of the defined active
levels (high or low). (ten = tPZH or tpzU.
tf
Fall time
The time interval between two reference points (90% and 10% unless otherwise specified) on a
waveform that is changing from the defined high level to the defined low level.
th
Hold time
The time interval during which a signal is retained at a specified input terminal after an active transition
occurs at another specified input terminal.
NOTES: 1. The hold time is the actual time interval between two signal events and is determined
by the system in which the digital circuit operates. A minimum value is specified that
is the shortest interval for which correct operation of the digital circuit is guaranteed.
G)
m
m
Z
::J:J
»
rZ
."
0
::J:J
3:
»
-I
0
Z
2. The hold time may have a negative value in which case the minimum limit defines the
longest interval (between the release of the signal and the active transition) for which
correct operation of the digital circuit is guaranteed.
tpd
1-22
Propagation delay time
The time between the specified reference points on the input and output voltage waveforms with
the output changing from one defined level (high or low) to the other defined level. (tpd = tPHL or
tPLH)·
TE~.
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS, TeXAS 75265
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
tpHL
Propagation delay time, high-to-Iow level output
The time between the specified reference points on the input and output voltage waveforms with
the output changing from the defined high level to the defined low level.
Disable time (of a three-state output) from high level
The time interval between the specified reference points on the input and the output voltage waveforms
with the three-state output changing from the defined high level to a high-impedance (off) state.
Propagation delay time, low-to-high-Ievel output
The time between the specified reference points on the input and output voltage waveforms with
the output changing from the defined low level to the defined high level.
Disable time (of a three-state output) from low level
The time interval between the specified reference points on the input and output voltage waveforms
with the three-state output changing from the defined low level to a high-impedance (off) state.
tPZH
tpZL
II
2
o
~
r-
:2
o"
:0
s:
l>
:::!
o
:2
1-24
GENERAL INFORMATION
RATINGS AND CHARACTERISTICS
HCMOS DEVICES
HCMOS·DEVICES -
ADVANCE INFORMATION
HCMOS DEVICES·· ~ PRODUCT PREVIEWS
EXPLANATION OF LOGIC SYMBOLS
DESIGNERS' INFORMATION
MECHANICAL DATA
1:1
2-1
II
::u
l>
-I
2
G')
en
l>
:2
C
n
:I:
l>
::u
l>
n
-I
m
::u
C;;
-I
oen
2-2
These devices contain circuits to protect the inputs and outputs against damage due to high static voltages or electrostatic fields, however,
it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits.
Unused inputs must always be connected to an appropriate logic voltage level, preferably either
Vee
or ground.
II
en
o
i=
LIST OF TABLES
en
a:w
t-
Table
I
II
III
IV
V
VI
VII
VIII
IX
Specifications
Specifications
Specifications
Specifications
Specifications
Specifications
Specifications
Specifications
Specifications
for
for
for
for
for
for
for
for
for
Page
HC SSI Circuits ............................................. 2-4
HC Dual and Quad Flip-FLops and Latches ......................... 2-6
HC Circuits with High-Current Outputs . . . . . . . . . . . . . . . . . . . . . .. . . . .. 2-8
HC MSI Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-10
HCT SSI Circuits ........................................... 2-12
HCT Dual and Quad Flip-Flops and Latches . . . . . . . . . . . . . . . . . . . . . . .. 2-13
HCT Circuits with High-Current Outputs ........................ " 2-14
HCT MSI Circuits ......................................... " 2-15
HCU Circuits .............................................. 2~16
O
Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output diode current, 10K(VO < 0 or Vo > Vee) .............................. ± 20 mA
eontinuous output current, 10 (Va = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
eontinuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: FH, FK, or J package .... 300 De
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FN or N package. . . . . . .. 260 De
Storage temperature range ......................................... - 65 De to 1 50 De
II
::c
~
:::!
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
:2
C)
Vee
en
VIH
~
Supply voltage
High-level input voltage
Vee
Vee
Vee
:2
C
Vee
VIL
n
Low-level input voltage
Vee
Vee
J:
~
::c
~
n
VI
Input voltage
Vo
Output voltage
Input transition (rise and fall) times
tt
-I
TA
m
(except Schmitt-trigger inputs)
Vee
Vee
Vee
=
=
=
=
=
=
2 V
4.5 V
6 V
2 V
4.5 V
6 V
=2V
= 4.5 V
=6V
Operating free-air temperature
MIN
2
1.5
3.15
4.2
SN54HC'
NOM MAX
5
6
0.3
0.9
1.2
0
0
0
0
0
0
0
0
-55
Vee
Vee
1000
500
400
125
MIN
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-40
SN74HC'
NOM MAX
5
6
UNIT
V
V
0.3
0.9
1.2
Vee
Vee
1000
500
400
85
V
V
V
ns
De
~
en
:::!
n
en
Copyright © 1982 by Texas Instruments Incorporated
2-4
TEXAS •
INSTRUM·ENTS
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265
TABLE I
SPECIFICATIONS FOR HC SSI CIRCUITS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
TYP MAX
MIN
VCC
2V
1.9 1.998
VOH
(Totem-pole
VI = VIH or VIL. 10H = - 20 p.A
4.5 V
6V
4.4 4.499
5.9 5.999
outputs)
VI = VIH or VIL. 10H = -4 mA
VI = VIH or VIL. 10H = - 5.2 mA
4.5 V
10H
(Open-drain
3.98
5.48
6V
4.30
5.80
SN54HC'
MIN
SN74HC'
MAX
MIN
1.9
4.4
5.9
4.4
5.9
3.7
5.2
3.84
5.34
MAX
1.9
V
6V
0.D1
0.5
10
5
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.001
0.1
0.1
0.1
6V
0.1
0.1
4.5 V
0.17
0.26
0.1
0.4
0.33
6V
0.15
0.26
1.5
0.4
0.33
VI = VIH or VIL. Vo = VCC
UNIT
p.A
outputs)
VI = VIH or VIL. 10L = 20 p.A
VOL
VI = VIH or VIL. 10L = 4 mA
VI = VIH or VIL. 10L = 5.2 mA
VT+ t
VT- t
VT+ - VT- t
2V
0.8
1.2
4.5 V
2
3.15
6V
2.5
2.5
3.3
2V
0.3
0.6
0.8
4.5 V
0.9
1.6
6V
1.2
2
2
2.5
2V
4.5 V
6V
0.2
0.4
0.5
0.6
0.9
II
VI = 0 to VCC
6V
ICC
CI
VI = VCC or O. 10 = 0
6V
2 to 6 V
1.3
V
en
i=
en
(.)
a:
V
4.2
w
I(.)
V
1
1.4
1.7
«
a:
«
J:
V
(.)
2!
±0.1 ±100
2
±1000
40
±100Cl
20
nA
p.A
10
10
10
pF
3
II
C
«
en
e"
2!
tThis parameter applies only for Schmitt-trigger inputs.
switching characteristics
i=
«
a:
See individual circuit pages.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
2-5
TABLE II
SPECIFICATIONS FOR HC DUAL AND
QUAD FLlp·FlOPS A~JD LATCHES
HIGH·SPEED
CMOS LOGIC
02804, DECEMBER 1982-REVISED MARCH 1984
absolute maximum ratings over operating free·air temperature range t
II
Supply voltage range, Vee ............................................ - O. 5 V to 7 V
Input diode current, IIK(VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. ± 20 mA
Output diode current, 10K(VO < 0 or Va > Vee) .............................. ± 20 mA
eontinuous output current, 10 (Va = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
eontinuous current through Vee or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: FH, FK, or J package .... 300 0 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FN or N package. . . . . . .. 260 0 e
Storage temperature range ......................................... - 65 °e to 150 0 e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conc!itions
SN54HC'
Vee
Supply voltage
Vee = 2 V
VIH
High-level input voltage
Vee = 4.5 V
Vee = 6 V
NOM
MAX
MIN
NOM
MAX
2
1.5
3.15
4.2
5
6
2
1.5
3.15
4.2
5
6
a
a
a
a
a
a
a
a
Vee = 2 V
VIL
Low·level input voltage
Vee = 4.5 V
Vee = 6 V
VI
Input voltage
Vo
Output voltage
Vee = 2 V
tt
Input transition (rise and fall) times
Vee = 4.5 V
Vee = 6 V
TA
SN74HC'
MIN
0.3
0.9
1.2
Vee
Vee
1000
500
400
125
-55
Operating free·air temperature
a
a
a
a
a
a
a
a
-40
UNIT
V
V
0.3
0.9
1.2
V
Vee
V
Vee
V
1000
500
400
85
ns
°e
See individual circuits for additional timing requirements.
Copyright © 1982 by Texas Instruments Incorporated
2-6
TEXAS
lj}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TABLE II
SPECIFICATIONS FOR HC DUAL AND QUAD FLlp·FLOPS AND LATCHES
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
Vec
TEST CONDITIONS
VI
=
VIH or VIL. 10H
= - 20 J.lA
VOH
VI
VI
VI
= VIH
= VIH
=
or VIL. 10H
or VIL. 10H
VIH or VIL. 10L
= -4 rnA
= - 5.2 rnA
=
20 J.lA
VOL
VI
II
lee
el
VI
VI
VI
=
=
=
=
VIH or VIL. 10L
VIH or VIL. 10L
0 to Vee
Vee or O. 10
=
=
=
0
4 rnA
5.2 rnA
TA = 25°C
MIN
TYP MAX
SN54HC'
MIN
SN74HC'
MAX
MIN
2V
1.9 1.998
1.9
1.9
4.5 V
4.4 4.499
4.4
4.4
6V
5.9 5.999
5.9
5.9
3.7
3.84
4.5 V
3.98
6V
5.48
4.30
5.80
5.2
MAX
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1 ±100
±1000
4
80
±1000
40
10
10
10
6V
2 to 6 V
3
UNIT
V
II
en
nA
J.lA
pF
u
i=
a:
en
....uw
«
a:
«
::I:
switching characteristics
See individual circuit pages.
U
C
Z
«
en
z
(!'
i=
«
a:
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
2-7
TABLE III
SPECIFICATIONS FOR HC CIRCUITS
WITH HIGH·CURRENT OUTPUTS
HIGH·SPEED
CMOS LOGIC
02804, DECEMBER 1982-REVISED MARCH 1984
absolute maximum ratings over operating free-air temperature range t
Supply voltage range, VCC ,.......................................... -0.5 V to 7 V
Input diode current, 11K (VI < 0 or VI > Vcd .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output diode current, 10K(VO < 0 or Vo > Vcc) .............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: FH, FK, or J package .... 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FN or N package. . . . . . .. 260°C
Storage temperature range ......................................... - 65°C to 150°C
II
:D
»
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
:::!
SN54HC'
:2
G)
rn
»
:2
C
Vee Supply voltage
VIH
High-level input voltage
Vee
Vee
VIL
Low-level input voltage
(")
J:
»
:D
»
(")
-f
m
Vee
Vee
Vee
Vee
=2V
= 4.5 V
=6V
=2V
= 4.5 V
=6V
SN74HC'
MIN
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
0.3
0
0.3
0.9
0
0.9
0
1.2
0
1.2
Vee
Vee
1000
V
ns
Input voltage
0
Vee
0
Output voltage
0
Vee
1000
0
tt
TA
(except Schmitt-trigger inputs)
Vee
=2V
= 4.5 V
=6V
Operating free-air temperature
V
0
Vo
Vee
Vee
V
0
VI
Input transition (rise and fall) times
UNIT
0
0
0
500
0
500
0
400
0
400
-55
125
-40
85
V
V
De
:2
rn
:::!
(")
rn
2-8
'Ii1
INSTRUMENTS
Copyright © 1982 by Texas Instruments Incorporated
TEXAS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TABLE III
SPECIFICATIONS FOR HC CIRCUITS WITH HIGH·CURRENT OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
VOH
=
VIH or VIL. 10H
=
-20 p.A
II
lozt
lee
el t
2V
1.9 1.998
4.5 V
6V
4.4 4.499
5.9 5.999
VI = VIH or VIL.
10H = See Notes 1 and 5
4.5 V
3.98
VI = VIH or VIL.
10H = See Notes 2 and 5
6V
5.48
VI = VIH or VIL. 10L = 20 p.A
VOL
TA = 25°C
MIN
TYP MAX
VCC
VI = VIH or VIL.
VOL = See Notes 3 and 5
Vo = Vee or O. VI
VI
=
MIN
MAX
4.4
5.9
3.7
3.84
5.2
V
5.34
0.1
0.1
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
0.17
0.26
0.15
UNIT
1.9
1.9
4.4
5.9
0.002
0.001
6V
= VIH or VIL
Vee or O. 10 = 0
5.80
SN74HC'
MAX
2V
4.5 V
4.5 V
VI = VIH or VIL.
10L = See Notes 4 and 5
VI = 0 to Vee
4.30
SN54HC'
MIN
0.4
0.1
0.33
(IJ
V
0.26
0.4
0.33
6V
6V
±0.1 ±100
±0.01 ±0.5
±1000
±1000
±10
±5
nA
p.A
6V
8
160
10
10
80
10
p.A
pF
2 to 6 V
3
tThis parameter. 10Z. the high-impedance-state output current. applies only to three-state outputs and transceiver I/O pins.
tThis parameter. el. does not apply to transceiver I/O ports.
.
NOTES: 1. 10H = - 4 rnA for standard outputs and - 6 rnA for high-current outputs.
2. 10H = - 5.2 rnA for standard outputs and -7.8 rnA for high-current outputs.
3. 10L = 4 rnA for standard outputs and 6 rnA for high-current outputs.
4. 10L = 5.2 rnA for standard outputs and 7.8 rnA for high-current outputs.
5. High-current outputs are indicated by the I> in the logic symbol. All 3-state outputs (indicated by the V in the logic symbol)
are also high-current outputs.
u
i=
(IJ
a:w
IU
«
tt:
«
J:
U
C
Z
«
(IJ
~
z
i=
switching characteristics
See individual circuit pages.
«
tt:
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265
2-9
TABLE IV
SPECIFICATIONS FOR HC MSI CIRCUITS
HIGH·SPEED
CMOS LOGIC
02804. DECEMBER 1982-REVISED MARCH 1984
absolute maximum ratings over operating free-air temperature range t
II
»
:ZJ
Supply voltage range, Vee ........................................... -0.5 V to 7 V
Input diode current, IIK(VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
Output diode current, 10K(VO < 0 or Vo > Vee) .............................. ± 20 mA
eontinuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
eontinuous current through Vee or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: FH, FK, or J package .... 300 0 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FN or N package. . . . . . .. 260 0 e
Storage temperature range ......................................... - 65 °e to 150 0 e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
-4
G)
en
»
;2
c
(')
:J:
»
:ZJ
»
(')
-4
m
:ZJ
SN74HC'
SN54HC'
2
Vee Supply voltage
VIH
High-level input voltage
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
Vee = 2 V
VIL
Low-level input voltage
Vee = 4.5 V
Vee = 6 V
VI
Vo
Input voltage
Output voltage
Input transition (rise and fall) times
tt
TA
(except Schmitt-trigger inputs)
Vee = 2 V
Vee = 4.5 V
Vee = 6 V
Operating free-air temperature
MIN
NOM
MAX
MIN
NOM
MAX
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-55
5
6
2
1.5
3.15
4.2
0
0
0
0
0
0
0
0
-40
5
6
0.3
0.9
1.2
Vee
Vee
1000
500
400
125
UNIT
V
V
0.3
0.9
1.2
Vee
Vee
1000
500
400
85
V
V
V
ns
°e
en
-4
n
en
Copyright © 1982 by Texas Instruments Incorporated
2-10
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012. DALLAS. TEXAS 75265
TABLE IV
SPECIFICATIONS FOR HC MSI CIRCUITS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
.
PARAMETER
TEST CONDITIONS
VI
VOH
VI
VI
VI
VOL
VI
VI
VI
II
IS (off) t
VI
VT+i
VT- i
VT+ - VTlee
el
~
VI
VCC
2V
= VIH or VIL. 10H = - 20 ,.A 4.5 V
6V
4.5 V
= VIH or VIL. 10H = -4 mA
6V
= VIH or VIL. 10H = - 5.2 mA
2V
4.5 V
= VIH or VIL. 10L = 20 ,.A
6V
4.5 V
= VIH or VIL. 10L = 4 mA
6V
= VIH or VIL. 10L = 5.2 mA
= 0 to Vee
6V
6V
= Vee or O. Vs = ±Vee
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
6V
= Vee or O. 10 = 0
2 to 6 V
TA = 25°C
MIN TYP MAX
1.9 1.998
4.44.499
5.9 5.999
3.98 4.30
5.48 5.80
0.002
0.1
0.001
0.1
0.8
2
2.5
0.3
0.9
1.2
0.2
0.4
0.5
SN54HC'
MIN
1.9
4.4
5.9
3.7
5.2
0.001
0.1
0.17 0.26
0.15 0.26
±0.1 ±100
±0.1
1.2
1.5
2.5 3.15
3.3
4.2
0.6
0.8
1.6
2
0.6
0.9
1.3
3
2
2.5
1
1.4
1.7
8
10
MAX
SN74HC'
MIN
MAX
1.9
4.4
5.9
3.84
5.34
V
0.1
0.1
0.1
0.1
0.1
0.4
0.4
0.1
0.33
0.33
±1000
±1
±1000
±1
UNIT
V
II
tn
nA
,.A
o
~
tn
V
a:w
V
O
t-
V
160
10
80
10
,.A
pF
«
a:
«
l:
o
C
2
tThis parameter. IS(off). is for analog switches only.
~These threshold parameters apply only to Schmitt-trigger inputs.
«
switching characteristics
~
tn
2
~
See individual circuit pages.
«a:
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
2-11
HIGH·SPEED
CMOS LOGIC
TABLE V
SPECIFICATIONS FOR HCT SSI CIRCUITS
02804, MARCH 1984
absolute maximum ratings over operating free-air temperature range t
Supply voltage range, VCC, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input diode current, IIK(VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output diode current, 10K(VO < 0 or Vo > Vcc) .............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
'Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: FH, FK, or J package .... 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FN or N package ........ 260°C
Storage temperature range ......................................... - 65°C to 150°C
II
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxim urn-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HCT'
Vee
Supply voltage
VIH
High-level input voltage
Low-level input voltage
VIL
VI
SN74HCT'
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
V
I Vee
= 4.5 V to 5.5 V
2
I Vee
= 4.5 V to 5.5 V
0
0.8
0
0.8
V
V
V
2
Input voltage
0
Vee
0
Vee
Vo
Output voltage
0
0
tt
Input transition (rise and fall) times
Vee
500
0
Vee
500
TA
Operating free-air temperature
125
-40
85
0
-55
V
ns
De
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
VI
= VIH
VCC
= - 20 p.A
= -4 rnA
= 20 p.A
VIL, 10L = 4 rnA
or VIL, 10H
VI = VIL, 10H
VI or VIL, 10L
VI
= VIH or
= 0 to Vee
II
VI
lee
VI = Vee or 0, 10 = 0
One input at 0.5 V or 2.4 V,
.::llee*
Other inputs at 0 V or Vee
el
4.5 V
4.5 V
TA = 25 DC
MIN
TYP MAX
4.4 4.499
3.98
4.30
SN54HCT'
MIN
SN74HCT'
MAX
MIN
4.4
4.4
3.7
3.84
MAX
UNIT
V
4.5 V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
5.5 V
±0.1 ±100
2
±1000
40
±1000
20
nA
5.5 V
1.4
2.4
2.9
3
rnA
3
10
10
10
pF
5.5 V
4.5 to
5.5 V
V
p.A
~This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or Vee.
switching characteristics
See individual circuit pages.
2-12
TEXAS
-iii
Copyright © 1982 by Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TABLE VI
SPECIFICATIONS FOR HCT DUAL AND QUAD
FLlp·FLOPS AND LATCHES
HIGH·SPEED
CMOS LOGIC
02804. MARCH 1984
absolute maximum ratings over operating free-air temperature range t
Supply voltage range, Vee ........................................... -0.5 V to 7 V
Input diode current, IIK(VI < 0 or VI > Vee) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 rnA
Output diode current, 10K(VO < 0 or Vo > Vee) .............................. ± 20 rnA
eontinuous output current, 10 (VO = 0 to Vee) .............................. " ± 25 rnA
eontinuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. ± 50 rnA
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: FH, FK, or J package .... 300 De
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FN or N package. . . . . . .. 260 De
Storage temperature range ......................................... - 65 De to 150 De
II
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxim urn-rated conditions f,or extended periods may affect device reliability.
CJ)
recommended operating conditions
(J
SN54HCT'
Vee Supply voltage
High-level input voltage
I Vee
I Vee
VIH
Low-level input voltage
SN74HCT'
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
2
= 4.5 V to 5.5 V
CJ)
a:w
V
....
V
2
VIL
VI
0
0.8
0
0.8
V
Input voltage
0
Vee
0
Vee
,V
= 4.5 V to 5.5 V
i=
UNIT
Vo
Output voltage
0
Input transition (rise and fall) times
0
Vee
500
0
tt
0
Vee
500
ns
TA
Operating free-air temperature
-55
125
-40
85
?e
(J
Supply voltage range, Vee ........................................... -0.5 V to 7 V
Input diode current, IIK(VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output diode current, 10K(VO < 0 or Vo > Vee) .............................. ± 20 mA
eontinuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
eontinuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 70 mA
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: FH, FK, or J package .... 300 0 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FN or N package ........ 260 0 e
Storage temperature range ......................................... - 65 °e to 1 50 °e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
::!
SN54HCT'
2
G')
Vee Supply voltage
VIH High-level input voltage
(J)
l>
2
C
o
:J:
l>
::JJ
l>
VIL
VI
Low-level input voltage
Input voltage
Vo
Output voltage
tt
Input transition (rise and fall) times
TA
Operating free-air temperature
I Vee
I Vee
SN74HCT'
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
V
0.8
V
V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
2
0
2
0.8
0
Vee
0
Vee
500
125
0
-55
0
0
0
0
-40
Vee
V
Vee
500
v
ns
85
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
o
-I
PARAMETER
m
TEST CONDITIONS
= VIH or VIL, 10H = - 20 p.A
VI = VIH or VIL,
10H = See Notes 1 and 3
VI = VIH or VIL. 10H = 20 p.A
VI = VIH or VIL.
10L = See Notes 2 and 3
VI = 0 to Vee
Vo = Vee or O. VI = VIH or VIL
VI = Vee or O. 10 = 0
VI
::JJ
en
VOH
o
(J)
VOL
::!
II
loi"
lee
.ilee§
VCC
One input at 0.5 V or 2.4 V
Other inputs at 0 V or Vee
4.5V
4.5 V
4.4 4.499
3.98
4.30
SN54HCT'
MIN
SN74HCT'
MAX
MIN
4.4
4.4
3.7
3.84
MAX
UNIT
V
4.5 V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
±0.1 ±100
±0.01 ±0.5
8
±1000
±1000
nA
±10
160
±5
80
p.A
p.A
1.4
2.4
2.9
3
mA
3
10
10
10
pF
5.5 V
5.5 V
5.5 V
5.5 V
4.5 to
el'
TA = 25°C
MIN
TYP MAX
5.5 V
V
*This parameter. 10Z. the high impedance-state output current. applies only for three-state outputs and transceiver 1/0 pins.
§This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or Vee.
'This parameter, el. does not apply to transceiver 1/0 ports.
NOTES: 1. IOH = -4 mA for standard outputs and - 6 mA for high-current outputs.
2. IOL = 4 mA for standard outputs and 6 mA for high-current outputs.
3. High-current outputs are indicated by the C> in the logic symbol. All 3-state outputs (indicated by the Q in the logic symbol)
are also high-current outputs.
switching characteristics
See individual circuit pages.
Copyright © 1982 by Texas Instruments Incorporated
2-14
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TABLE VIII
SPECIFICATIONS FOR HCT MSI CIRCUITS
HIGH-SPEED
CMOS LOGIC
02804, MARCH 1984
absolute maximum ratings over operating free-air temperature range t
Supply voltage range, Vee ................. ,......................... - 0.5 V to 7 V
Input diode current, IIK(VI < 0 or VI > Vee) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output diode current, 10K(VO < 0 or Vo > Vee) .............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
Continuous current through Vee or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: FH, FK, or J package ..... 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FN or N package ........ 260°C
Storage temperature range ......................................... - 65°C to 150°C
fI
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
en
o
i=
recommended operating conditions
SN54HCT'
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
Vee
Supply voltage
VIH
High-level input voltage
IVee
VIL
VI
Low-level input voltage
IVee
Input voltage
Vo
Output voltage
0
tt
Input transition (rise and fall) times
TA
Operating free-air temperature
=
=
SN74HCT'
MIN
2
en
UNIT
a:w
V
4.5 V to 5.5 V
2
V
4.5 V to 5.5 V
0
0.8
a
0.8
V
0
Vee
0
V
0
Vee
500
0
0
Vee
Vee
500
-55
125
-40
85
I-
o
«
a:
«J:
V
ns
De
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
VI
VI
VI
=
=
=
=
VCC
= - 20 p.A
4.5 V
VIH or VIL, 10H = -4 rnA
4.5 V
VIH or VIL, IOH
VIH or VIL, 10H
=
20 p.A
II
VIH or VIL, 10L = 4 rnA
VI
VI = 0 to Vee
IS(off)~
VI
ICC
VI = Vee or 0, 10 = 0
One input at 0.5 V or 2.4 V,
dlee§
=
VIH or VIL, Vs
=
± Vee
4.5 V
3.98
4.30
MIN
MAX
MIN
.4.4
4.4
3.7
3.84
0.1
MAX
Z
en
~
V
z
V
«
a:
4.5 V
0.17
0.26
0.4
0.33
5.5 V
±0.1 ±100
±1000
nA
5.5 V
±0.1
±1000
±1
±1
p.A
5.5 V
8
160
80
p.A
1.4
2.4
2.9
3
rnA
3
10
10
10
pF
5.5 V
0.1
C
«
UNIT
0.1
4.5 to
el
4.4 4.499
SN74HCT'
SN54HCT'
0.001
5.5 V
Other inputs at 0 V or Vee
TA = 25 DC
TYP MAX
MIN
o
i=
~This parameter, IS(off). is for analog switches only.
§This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or Vee.
switching characteristics
See individual circuit pages.
Copyright © 1982 by Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
2-15
TABLE IX
SPECIFICATIONS FOR HCU CIRCUITS
HIGH-SPEED
CMOS LOGIC
02804. MARCH 1984
absolute maximum ratings over operating free-air temperature range t
II
:XJ
»
:j
Supply voltage range, Vee ........................................... - O. 5 V to 7 V
Input diode current, IIK(VI < 0 or VI > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output diode current, 10K(VO < 0 or Vo > Vee) .............................. ± 20 mA
eontinuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 mA
eontinuous current through Vee or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: FH, FK, or J package .... 300 0 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FN or N package. . . . . . .. 260 0 e
Storage temperature range ......................................... - 65 °e to 150 °e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute·maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HCU'
2
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
Vee Supply voltage
C)
rJ)
»
2
Vee
vee
High-level input voltage
VIH
Vee
C
n
Vee
Vee
Low-level input voltage
VIL
Vee
::I:
»
:XJ
»
n
VI
Vo
Input voltage
Output voltage
tt
Input transition (rise and falll times
Vee
Vee
Vee
-I
=
=
=
2 V
4.5 V
1.7
3.6
1.7
3.6
6 V
4.8
4.8
UNIT
V
V
2 V
4.5 V
0
0.3
0
0.8
0
0
0.3
0.8
6 V
0
1.1
0
1.1
0
0
Vee
Vee
1000
0
Vee
Vee
1000
V
v
500
ns
0
2 V
4.5 V
0
0
0
0
500
400
0
-55
6 V
Operating free-air temperature
TA
m
=
=
=
=
=
=
SN74HCU'
MIN
125
0
400
-40
85
V
°e
:XJ
en
nrJ)
:j
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VI
=
VI
VI
= VIH
= VIH
VCC
=
lee
el
SN74HCU'
MAX
MIN
2V
1.8
1.8
1.8
4.5 V
6V
4
5.5
4
5.5
4
5.5
or VIL. IOH = -4 mA
or VIL. 10H = - 5.2 mA
4.5 V
6V
3.98
5.48
3.7
3.84
= -
VIH or VIL. 10L
=
20 p.A
VOL
II
SN54HCU'
MIN
20 p.A
VIH or VIL. IOH
VOH
VI
TA = 25°C
TYP MAX
MIN
VI = VIH or VIL. 10L = 4 mA
VI = VIH or VIL. 10L = 5.2 mA
VI = 0 to Vee
VI = Vee or 0, 10
=
0
MAX
V
5.34
5.2
2V
0.2
0.2
0.2
4.5 V
0.5
0.5
6V
4.5 V
0.5
0.26
0.5
0.4
0.5
0.5
6V
6V
0.26
0.4
±100
6V
2
±1000
40
10
10
2 to 6 V
3
UNIT
V
0.33
0.33
±1000
nA
20
10
p.A
pF
switching characteristics
See individual circuit pages.
2-16
TEXAS
~
Copyright © 1982 by Texas Instruments Incorporated
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS. TeXAS 75265
GENERAL INFORMATION
RATINGS AND CHARACTERISTICS
HCMOS DEVICES
HCMOS DEVICES - ADVANCE.INFORMATION
HCMOS DEVICES
~
PRODUCT· PREVIEWS
I_iI
I. .
_EX_.·P_L_A_N_A_T_IO_N...;.·._O_F_L_O_G_IC_S_V_M_B_O_L_S______
DESIGNERS'· INFORMATION
MECHANICAL DATA
3-1
ATTENTION
These devices contain circuits to protect the inputs and outputs
against damage due to high static voltages or electrostatic fields,
however, it is advised that precautions be taken to avoid application
of any voltage higher than maximum-rated voltages to these highimpedance circuits.
III
Unused inputs must always be connected to an appropriate logic
voltage level, preferably either Vee or ground.
::I:
o
3:
o
(/)
C
m
om<
(/)
3-2
TYPES SN54HCOO, SN74HCOO
QUADRUPLE 2·INPUT POSITIVE·NAND GATES
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN54HCOO ... J PACKAGE
SN74HCOO ... J OR N PACKAGE
(TOP VIEW)
VCC
4B
• Dependable Texas Instruments Quality
and Reliability
4A
4Y
description
38
3A
These devices contain four independent 2-input NAND
gates. They perform the Boolean functions Y = A:s
or Y = A+ B in positive logic.
The SN54HCOO is characterized for operation over the
full military temperature range of - 55°C to 125°C.
The SN74HCOO is characterized for operation from
-40°C to 85°C.
........
_ .... 3Y
SN54HCOO ... FH OR FK PACKAGE
SN74HCOO ... FH OR FN PACKAGE
(TOP VIEW)
FUNCTION TABLE (each gate)
lY
INPUTS
A
8
4A
OUTPUT
NC
NC
V
2A
4Y
NC
·28
38
H
H
L
L
X
H
X
L
H
NC
II
en
w
o
:>w
c
logic symbol
NC-No internal connection'
1A
en
o
2
o
18
2A
:I:
28
3A
38
4A
48
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-3
TYPES SN54HCOO. SN74HCOO
QUADRUPLE 2·INPUT POSITIVE·NAND GATES
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
V
tt
Y
vCC
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
45
90
9
8
38
8
6
Power dissipation capacitance per gate
SN54HCOO
MIN
18
15
75
15
13
II
:J:
(')
.3:
o
en
c
m
S
(')
m
en
TEXAS
~
INSTRUMENTS
POST OFFICE
eox
27
23
110
22
19
No load, TA = 25°C
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
3-4
MAX
135
225012 • DALLAS. TEXAS 75265
SN74HCOO
MIN
MAX
115
23
20
95
19
16
UNIT
ns
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC02, SN74HC02
POSITIVE·NOR GATES
2~INPUT
QUADRUPLE
02684, DECEMBER 1982-REVISED MARCH 1984
SN54HC02 ... J PACKAGE
SN74HC02 ... J OR N PACKAGE
(TOPVIEWI
• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
VCC
4Y
4B
4A
• Dependable Texas Instruments Quality
and Reliability
description
3Y
These devices contain four independent 2-input
NOR gates. They perform the Boolean functions
y =A + B or Y =A·a in positive logic.
3B
The SN54HC02 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC02 is characterized for operation from -40°C to 85°C.
SN54HC02 ... FH OR FK PACKAGE
SN74HC02 ... FH OR FN PACKAGE
(TOPVIEWI
q-
logic symbol
1A
18
NC
1B
2Y
2A
NC
2A
2B
48
NC
4A
NC
3Y
3A
II
en
w
(.)
:>
w
c
38
4A
NC - No internal connection
4B
FUNCTION TABLE (each gate)
Pin numbers shown are for J and N packages.
INPUTS
A
OUTPUT
B
en
o
~
(.)
J:
V
H
X
L
X
H
L
L
L
H
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-3.
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright ©1982 by Texas Instruments Incorporated
3-5
TYPES SN54HC02. SN74HC02
QUADRUPLE 2·INPUT POSITIVE·NOR GATES
switching characteristics over recommended operating free-air temperature range (unless otherwise noted),
CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
Cpd
FROM
(INPUT)
A or B
TO
(OUTPUT)
y
Y
Vcc
2V
4.5 V
6V
2V
4.5 V
6V
Power dissipation capacitance per gate
TA = 25°C
MIN TYP MAX
45
9
8
38
8
6
MIN
SN54HC02
MAX
SN74HC02
MIN
MAX
135
27
23
110
22
19
115
23
20
95
19
16
90
18
15
75
15
13
No load, TA = 25°C
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
II
.J:
n
3:
oCJ)
C
m
<
n
m
CJ)
3-6
TEXAS.
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
22 pF typ
UNIT
ns
ns
TYPES SN54HC03, SN74HC03
QUADRUPLE 2·INPUT POSITIVE·NAND GATES
WITH OPEN·DRAIN OUTPUTS
HIGH·SPEED
CMOS LOGIC
02804, MARCH 1984
•
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN54HC03 ..• J PACKAGE
SN74HC03 ..• J OR N PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
26
2Y
GND
Dependable Texas Instruments Quality
and Reliability
description
These devices contain four independent 2-input NAND
gates. They perform the Boolean functions Y = A.B
or Y = A+ Bin positive logic. The open-drain outputs
require pull-up resistors to perform correctly. They
may be connected to other open-drain outputs to
implement active-low wired-OR or active-high wiredAND functions.
VCC
4B
4A
4Y
36
3A
3Y
SN54HC03 •.• FH OR FK PACKAGE
SN74HC03 •.• FH OR FN PACKAGE
(TOP VIEW)
U
al'o:t
4A
NC
4Y
NC
36
FUNCTION TABLE (each gate)
INPUTS
A
B
H
H
X
L
L
X
OUTPUT
Y
L
H
H
II
en
w
CJ
s:w
c
NC-No internal connection
logic symbol
en
o
:2:
CJ
:I:
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions; and electrical characteristics
See Table I, page 2-4.
Copyright © 1984 by Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TexAS 75265
3-7
TYPES SN54HC03, SN74HC03
QUADRUPLE 2·INPUT POSITIVE·NAND GATES
WITH OPEN·DRAIN OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), RL -= 1 k{}, CL = 50 pF (see Note 1)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
tpLH
A or B
Y
tpHL
tt
II
Y
VCC
TA = 25°C
MIN
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TYP
MAX
60
13
10
50
10
8
38
8
6
105
25
23
100
20
17
75
15
13
SN54HC03
MIN
Power dissipation capacitance per gate
NOTE " Fo, lo.d
""u't .nd volt.g. wov"o,m,. ' " .".,-,4.
::t
(")
S
o
en
c
m
<
(")
m
en
3-8
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
MAX
155
36
31
150
30
25
110
22
19
SN74HC03
MIN
MAX
131
31
27
125
25
21
95
19
16
UNIT
ns
ns
TYPES SN54HC04, SN74HC04
HEX INVERTERS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982 - REVISED MARCH 1984
SN54HC04 •.• J PACKAGE
SN74HC04 ... J ORN PACKAGE
(TOPVIEWI
• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
1A
1Y
2A
2Y
3A
3Y
• Dependable Texas Instruments Quality
and Reliability
description
These devices contain six independent inverters.
They perform the Boolean function Y = A.
The SN54HC04 is characterized for operation
over th~ full military temperature range of
- 55 °C to 125°C. The SN74HC04 is
characterized for operation from - 40 °C to
85°C.
VCC
6A
6Y
5A
5Y
4A
4Y
SN54HC04 ..• FH OR FK PACKAGE
SN74HC04 ... FH OR FN PACKAGE
(TOPVIEWI
U
>- w
logic symbol
lA
2A
3A
4A
5A
6A
c
en
(1)
NC - No internal connection
(3)
o
:?!
u
(5)
(9)
(11)
:I:
(13)
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
VCC
tt
Cpd
A
Y
Y
MAX
MIN
MAX
45
95
4.5 V
9
19
29
24
6V
8
16
25
20
145
MIN
MAX
TYP
2V
tpd
SN74HC04
SN54HC04
TA = 25°C
MIN
2V
38
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance per inverter
No load. TA
=
25°C
UNIT
120
ns
ns
20 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-9
II
::I:
(")
3:
otn
o
m
<
o
m
tn
3-10
TYPES SN54HCUD4, SN74HCUD4
HEX INVERTERS
HIGH·SPEED
CMOS LOGIC
02804. MARCH 1984
•
SN54HCU04 ... J PACKAGE
SN74HCU04 ... J OR N PACKAGE
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Unbuffered Outputs
•
Dependable Texas Instruments Quality and
Reliability
(TOP VIEW)
1A
1Y
2A
2Y
3A
3Y
description
VCC
6A
6Y
5A
5Y
4A
4Y
GND
These devices contain six independent inverters.
They perform the Boolean function Y =A.
The SN54HCU04 is characterized for operation
over the full military temperature range of
- 55°C to 125
The SN74HCU04 is
characterized for operation from - 40°C to
85°C.
SN54HCU04 ... FH OR FK PACKAGE
SN74HCU04 ... FH OR FN PACKAGE
ac.
(TOP VIEW)
U
>-«UU«
II
........ 2>«>
FUNCTION TABLE
(each inverter)
INPUT
OUTPUT
A
Y
H
L
L
H
6Y
NC
5A
NC
5Y
2A
NC
2Y
NC
3A
(J)
W
(.)
>
W
logic symbol
C
1A
(J)
o
2A
~
NC - Na internal connection
3A
4A
(.)
SA
J:
6A
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IX, page 2-16.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
VCC
TA = 25°C
TYP MAX
MIN
2V
tpd
tt
A
Y
Y
SN54HCU04
MIN
SN74HCU04
MAX
MIN
MAX
40
80
120
100
4.5 V
8
16
24
20
6V
7
14
20
17
2V
38
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance per inverter
No load. TA
=
25°C
UNIT
ns
ns
20 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
Copyright © 1984 by Texas Instruments Incorporated
TEXAS
-I./}
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265
3-11
II
:I:
n
~
o
rn
c
<
m
n
m
rn
3-12
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC05, SN74HC05
HEX INVERTERS WITH OPEN·DRAIN OUTPUTS
02804. MARCH 1984
•
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN54HC05 •.. J PACKAGE
SN74HC05 ..• J OR N PACKAGE
(TOP VIEW)
1A
1Y
2A
2Y
3A
3Y
Dependable Texas Instruments Quality and
Reliability
description
These devices contain six independent inverters.
They perform the Boolean function Y = A. The
open-drain outputs require pull-up resistors to
perform correctly. They may be connected to
other open-drain outputs to implement activelow wired-OR or active-high wired-AND
functions.
VCC
6A
6Y
5A
5Y
4A
4Y
GND
SN54HC05 ••. FH OR FK PACKAGE
SN74HC05 ••. FH OR FN PACKAGE
(TOP VIEW)
U
~ ~ ~ ~~
The SN54HC05 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC05 is
characterized for operation from - 40°C to
85°C.
II
6Y
NC
en
w
5A
NC
FUNCTION TABLE (each inverter)
CJ
5Y
INPUT
OUTPUT
A
y
H
L
L
H
>
w
C
en
o
NC - No internal connection
~
CJ
logic symbol
J:
1A
2A
3A
4A
5A
6A
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
"J1
INSTRUMENTS
TEXAS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
Copyright © 1984. Texas In;truments Incorporated
3-13
TYPES SN54HC05. SN74HC05
HEX INVERTERS WITH OPEN·DRAIN OUTPUTS
switching characteristics over recommended operating free·air temperature range·(unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tPLH
tpHL
tf
II
Cpd
FROM
(INPUT)
A
A
TO
(OUTPUT)
VCC
TA = 25°C
MIN
TYP MAX
2V
60
Y
4.5 V
13
10
45
Y
6V
2V
4.5 V
6V
Y
SN54HC05
MIN
MAX
MAX
145
115
23
175
35
30
130
25
105
9
20
85
. 17
26
21
8
14
22
18
2V
4.5 V
38
8
75
110
95
15
22
19
6V
6
13
19
16
Power dissipation capacitance per inverter
NOTE " ,,, 'ood "'Cu;' .nd volt••• w,vo'o,m" ...
P·.·
No load, TA = 25°C
1-14.
J:
n
s:
orn
c
m
<
nm
rn
3-14
SN74HC05
MIN
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
29
20 pF typ
UNIT
ns
ns
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC08, SN74HC08
QUADRUPLE 2·INPUT POSITIVE·AND GATES
02684. DECEM8ER 1982-REVISED MARCH 1984
• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN54HCOB ... J PACKAGE
SN74HCOB ... J OR N PACKAGE
(TOP VIEW)
• Dependable Texas Instruments Quality
and Reliability
description
These devices contain four independent 2-input AND
gates. They perform the Boolean functions Y = A.B
or Y = A + B in positive logic.
1A
1B
1Y
VCC
4B
4A
2A
4Y
2B
2Y
3A
3B
--<--_ _~3Y
The SN54HC08 is characterized for operation over the
full military temperature range of - 55 DC to 125 DC.
The SN74HC08 is characterized for operation from
-40 o C to 85°C.
SN54HCOB ... FH OR FK PACKAGE
SN74HCOB ... FH OR FN PACKAGE
(TOP VIEW)
u
~ ~ ~ ~~
II
logic symbol
lA
III
(3) lY
FUNCTION TABLE
18
(each gate)
2A
(6) 2V
3A
4A
48
(10)
(S) 3Y
A
H
Ill) 4Y
L
X
(12)
(13)
B
OUTPUT
Y
H
H
X
L
L
INPUTS
28
38
1Y
NC
2A
NC
28
&
L
4
5
4A
6
7
4Y
NC
en
w
NC
38
8
(.)
9
>
W
>-ou>-«
c
NZZMM
<:l
en
NC - No internal connection
o
Pin numbers shown are for J and N packages.
":2E
(.)
:I:
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL ... 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
Vce
2V
tpd
tt
A or B
Y
Y
TA = 25°C
MIN
TYP MAX
50
100
SN54HC08
MIN
SN74HC08
MAX
150
MIN
MAX
125
4.5 V
10
20
8
30
25
25
6V
110
UNIT
ns
21
2V
38
17
75
4.5 V
8
15
22
95
19
6V
6
13
19
16
ns
Power dissipation capacitance per gate
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
-1!1
INSTRUMENTS
TEXAS
POST OFFICE BOX 225012 • DALLAS. TEXAS 15265
Copyright ©1982 by Texas Instruments Incorporated
3-15
II
J:
(")
s
orJ)
C
m
S
(")
m
rJ)
3-16
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC09, SN74HC09
QUADRUPLE 2·INPUT POSITIVE·AND GATES
WITH OPEN·DRAIN OUTPUTS
02804, MARCH 1984·
•
Package Options include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality
and Reliability
SN54HC09 ... J PACKAGE
SN74HC09 ... J OR N PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
description
These devices contain four independent 2-input AND
gates. They perform the Boolean functions Y = A·B
or Y =
in positive logic. The open-drain outputs
require pull-up resistors to perform correctly. They
may be connected to other open-drain outputs to
implement active-low wired-OR or active-high wiredAND functions.
VCC
4B
4A
4Y
3B
3A
3Y
A+B
SN54HC09 ..• FH OR FK PACKAGE
SN74HC09 ... FH OR FN PACKAGE
(TOP VIEW)
U
The SN54HC09 is characterized for operation over the
full military temperature range of - 55°C to 125°C.
The SN74HC09 is characterized for operation from
-40°C to 85°C.
FUNCTION TABLE (each gate)
INPUTS
OUTPUT
A
B
y
H
L
H
X
L
L
H
H
X
~ ~ ~ ~~
1Y
NC
2A
NC
2B
II
4A
NC
4Y
NC
3B
(/)
W
(.)
>
W
C
(/)
o
:E
NC-No internal connection
logic symbol
(.)
::J:
&
1A
Q
18
(3)1Y
2A
(S)2Y
28
3A
38
4A
48
(10)
(8) 3Y
(12)
(13)
(11)4Y
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characte.ristics
See Table I, page 2-4.
Copyright © 1984 by Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-17
TYPES SN54HC09, SN74HC09
QUADRUPLE 2·INPUT POSITIVE·AND GATES WITH OPEN·DRAIN OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise noted),
RL = 1 kO, CL = 50 pF (see Note 1)
PARAMETER
tPLH
tpHL
tf
Ell
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
A or B
Y
Y
VCC
TA = 25°C
MIN
TYP MAX
SN54HC09
MIN
SN74HC09
MIN
MAX
2V
4.5 V
60
105
155
131
13
25
36
31
6V
2V
10
50
23
100
31
150
27
125
4.5 V
10
25
8
20
17
30
6V
25
21
2V
38
75
110
4.5 V
8
22
95
19
6V
6
15
13
19
16
Power dissipation capacitance per gate
NOTE " Fo' 'o'd ",,";, 'nd ,olt". w""o,m.....
20 pF typ
P'" '-14.
::I:
o
3:
o(J)
C
m
<
o
m
(J)
3-18
MAX
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
UNIT
ns
ns
ns
TYPES SN54HC10, SN74HC10
TRIPLE 3·INPUT POSITIVE·NAND GATES
HIGH·SPEED
CMOS LOGIC
02684. DECEM8ER 1982-REVISED MARCH 1984
SN64HC10 •.. J PACKAGE
SN74HC10 ... J OR N PACKAGE
(TOP VIEW)
• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
lA
1B
• Dependable Texas Instruments Quality
and Reliability
2B
2C
2Y
description
These devices contain three independent 3-input
NAND gates. They perform the Boolean functions
Y=A.B.C or Y=A+B+C in positive logic.
SN64HC10 ... FH OR FK PACKAGE
SN74HC10 .•• FH OR FN PACKAGE
(TOP VIEW)
The SN54HC10 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC10 is characterized for opera. tion from -40°C to 85°C.
u
co.-
3 2 1 2019
logic symbol
lA
lB
lC
2A
2B
2C
3A
3B
3C
VCC
lC
lY
3C
2A
III
(21
(131
(31
II
lY
NC
3C
NC
3B
NC
28
NC
2C
&
en
w
(J
9 10111213
(41
>
W
>-ou>- ....
3
logic symbol
lA
18
lC
2A
28
2C
3A
38
3C
VCC
1C
1Y
3C
3B
3A
(1)
2 1
&
(2)
(12)
lY
(13)
(3)
(4)
(6)
II
1Y
NC
3C
NC
38
2A
NC
en
w
u
9 10 111213
2Y
:>w
>-OU>-<{
(5)
NZZMM
(.!)
(9)
(10)
(8)
NC -
3Y
c
No internal connection
en
o
:E
u
:r::
(11)
FUNCTION TABLE (each gatel
Pin numbers shown are for J and N packages.
A
INPUTS
B
C
OUTPUT
Y
H
H
H
H
L
X
X
X
L
X
X
X
L
L
L
L
maximum ratings, recommended operating c~nditions, and electrical characteristics
See Table I, page 2-4.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A, B. or C
y
2V
4.5 V
Y
6V
2V
4.5 V
tt
VCC
6V
TA = 25°C
MIN TYP MAX
35
100
10
20
8
17
25
75
7
15
5
13
MIN
SN54HC11
MAX
150
30
25
110
22
19
SN74HC11
MIN
MAX
125
25
21
95
19
16
UNIT
ns
ns
Power dissipation capacitance per gate
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS
-1./1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-21
11
::I:
o
s:
oen
cm
<
n
·m
en
3-22
HIGH-SPEED
CMOS LOGIC
TYPES SN54HC14, SN74HC14
HEX SCHMITT-TRIGGER INVERTERS
02684. DECEMBER 1982-REVISED MARCH 1984
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality
and Reliability
SN64HC14 ..• J PACKAGE
SN74HC14 ... J OR N PACKAGE
(TOP VIEW)
lA
lY
2A
2Y
3A
3Y
description
These Schmitt-trigger devices contain six independent
inverters. They perform the Boolean function Y = A.
The SN54HC14 is characterized for operation over the
full military temperature range of - 55°C to 125°C.
The SN 74HC 14 is characterized for operation from
-40°C to 85°C.
FUNCTION TABLE
(each Inverter)
INPUT
A
H
L
VCC
6A
6Y
5A
5Y
4A
4Y
GND
SN54HC14 ... FH OR FK PACKAGE
SN74HC14 •.. FH OR FN PACKAGE
(TOP VIEW)
II
>-<{u ~<
z>co
OUTPUT
V
L
H
2A
NC
2Y
NC
3A
logic symbol
en
w
6Y
NC
5A
NC
5Y
(.)
:>w
c
1A
en
o
>-ou>-<
Z Z v v
2A
(Y)
(,!)
3A
4A
:2!:
NC-No internal connection
(.)
5A
J:
6A
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
tpd
tt
A
Y
4.5 V
6V
2V
Y
4.5 V
6V
TA = 25°C
MIN
TYP MAX
55
125
'12
25
11
21
38
75
8
15
6
13
SN54HC14
MIN
MAX
190
38
32
110
22
19
Power dissipation capacitance per inverter
SN74HC14
MIN
MAX
155
31
26
95
19
16
UNIT
ns
ns
20 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
Copyright©1982 by Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFiCe BOX 225012 • DALLAS, TeXAS 15265
3-23
J:
n
s:o
en
c
m
<
n
m
en
3-24
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC20, SN74HC20
DUAL 4·INPUT POSITIVE·NAND GATES
02684, DECEMBER 1982-REVISED MARCH 1984
• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN64HC20 .•. J PACKAGE
SN74HC20 .•. J OR N PACKAGE
(TOP VIEW)
VCC
• Dependable Texas Instruments Quality
and Reliability
20
2C
NC
2B
2A
-"'_ _..r- 2Y
description
These devices contain two independent 4-input NAND
gates. They perform the Boolean functions
Y=~ or Y=A+B+C+D in positive logic.
SN64HC20 .•• FH OR FK PACKAGE
SN74HC20 •.. FH OR FN PACKAGE
(TOP VIEW)
The SN54HC20 is characterized for operation over the
full military temperature range of - 55°C to 125°C.
The SN74HC20 is characterized for operation from
-40°C to 85°C.
U
CON
NC
NC
NC
28
1C
logic symbol
II
2C
NC
NC
NC
U)
W
CJ
lA
18
lC
10
2A
28
2C
20
(2)
:>w
>-OU>-N
3
logic symbol
1A
ClI'
FUNCTION TABLE (each gate)
&
18
/61
1Y
A
1C
H
L
X
X
X
10
2A
28
/81
2Y
2C
2
1 20 19
D
L
H
X
X
X
X
L
H
X
X
X
5
X
L
Y
H
L
10 11 1213
(J
>
W
~ZZNN
<.:)
L
L
en
W
>-ou>--
lC
2A
2B
2C
3A
3B
3C
II
3 2 1 2019
logic symbol
lB
7
SN54HC27 •.. FH OR FK PACKAGE
SN74HC27 ... FH OR FN PACKAGE
(TOP VIEW)
The SN54HC27 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC27 is characterized for operation from -40°C to 85°C.
lA
VCC
1C
1V
3C
3B
3A
3V
(1)
2A
NC
2B
NC
2C
;>1
(2)
(13)
(3)
lY
NC
3C
NC
3B'
en
w
o
9 10111213
(4)
,>-
0
U
>-
>
w
Z
The SN54HC30 is characterized for operation over the
full military temperature range of - 55°C to 125°C.
The SN74HC30 is characterized for operation from
-40°C to 85°C.
C
NC
D
NC
A
G
NC
NC
E
logic symbol
(1)
&
D
en
w
(.J
:>w
LJ..OU>-U
ZZ
Z
l?
(2)
c
II
H
NC
4
5
6
(3)
c
NC-No internal connection
(4)
(8)
en
o
y
(5)
G
~
FUNCTION TABLE
(6)
(11)
INPUTS A THRU H
H (12)
Pin numbers shown are for J and N packages.
(.J
OUTPUT
J:
Y
All inputs H
L
One or more inputs L
H
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
(INPUT)
A thru H
TO
(OUTPUTI
Y
Y
SN54HC30
TA = 25°C
VCC
MIN
MIN
SN74HC30
TYP
MAX
MAX
MIN
2V
4.5 V
51
130
195
MAX
165
15
26
39
6V
12
22
33
33
28
95
2V
2B
75
110
4.5 V
B
15
22
19
6V
6
13
19
16
Power dissipation capacitance per gate
UNIT
ns
ns
22 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS
-'!}
INSTRUMENTS
POST OFFiCe BOX 225012 • DAL.L.AS. TexAS 75265
Copyright ©1982 by Texas Instruments Incorporated
3-31
lEI
::t
(')
~
o
rn
C
m
<
(')
m
rn
3-32
HIGH-SPEED
CMOS LOGIC
TYPES SN54HC32, SN74HC32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
02684, DECEMBER 1982-REVISED MARCH 1984
• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN54HC32 •.. J PACKAGE
SN74HC32 ... J OR N PACKAGE
(TOP VIEW)
1A
18
lY
2A
28
2Y
GND
• Dependable Texas Instruments Quality
and Reliability
description
These devices contain four independent 2-input OR
gates. They perform the Boolean functions Y = A + B
or Y=A.§ in positive logic.
The SN54HC32 is characterized for operation over the
full military temperature range of - 55°C to 125°C.
The SN74HC32 is characterized for operation from
-40°C to 85°C.
VCC
48
4A
4Y
38
3A
3Y
SN54HC32 ... FH OR FK PACKAGE
SN74HC32 ... FH OR FN PACKAGE
(TOP VIEW)
CD
~
U
u
U CD
Z>~
II
FUNCTION TABLE
(each gate)
lY
OUTPUT
NC
Y
2A
X
H
NC
X
H
H
L
L
L
INPUTS
A
B
H
4A
4
5
6
7
8
NC
4Y
U)
NC
W
(.)
38
5>
w
9 1011 1213
>-ClU>-~
logic symbol
t!)
NC -
1A
c
NZZMM
(1)
U)
o
No internal connection
;;'1
2
1B
(.)
2A
J:
38
4A
48
(13)
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-33
TYPES SN54HC32. SN74HC32
QUADRUPLE 2·INPUT POSITIVE·OR GATES
switching characteristics over recommended operating free·air temperature range (unless otherwise noted),
CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
tt
Y
VCC
TA = 25°C
MIN
TYP MAX
2V
4.5 V
6V
2V
4.5 V
6V
50
10
8
38
8
6
SN54HC32
MIN
100
20
17
75
15
13
Power dissipation capacitance per gate
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
::t:
o
s:
ofA
C
m
<
nm
fA
3-34
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
MAX
150
30
25
110
22
19
SN74HC32
MIN
MAX
125
25
21
95
19
16
UNIT
ns
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC36, SN74HC36
QUADRUPLE 2·INPUT POSITIVE·NOR GATES
02684, DECEMBER 1982-REVISED MARCH 1984
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality
and Reliability
SN64HC36 ... J PACKAGE
SN74HC36 •.. J OR N PACKAGE
(TOP VIEW)
1A
1B
1V
VCC
4B
4A
4V
3B
3A
3V
description
2B
2V
GND
These devices contain four independent 2-input NOR
gates. They perform the Boolean functions Y = A + B
or Y =A08 in positive logic.
The SN54HC36 is characterized for operation over the
full military temperature range of - 55°C to 125°C.
The SN74HC36 is characterized for operation from
-40°C to 85°C.
.
SN64HC36 ... FH OR FK PACKAGE
SN74HC36 ... FH OR FN PACKAGE
(TOP VIEW)
logic symbol
II
4A
NC
4V
lA
lB
2A
2B
2B
en
w
NC
3B
(.)
3A
>
W
>cu>«
3B
NZZMM
c
CI
4A
NC - No internal connection
4B
en
.0
Pin numbers shown ara for J and N packages.
~
FUNCTION TABLE (each gate)
INPUTS
A
B
H
X
X
H
L
L
(.)
OUTPUT
::I:
Y
L
L
H
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), Ci.. - 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
(INPUT)
A or B
TO
(OUTPUT)
V
V
VCC
2V
4.5 V
6V
2V
4.S V
TA = 2SoC
MIN
TYP MAX
SO
100
10
20
17
8
38
8
6
6V
Power dissipation capacitance per gate
75
15
SNS4HC36
MAX
150
30
25
110
22
13
19
MIN
SN74HC36
MIN
MAX
125
25
21
95
19
16
UNIT
ns
ns
No load, TA = 25°C
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright ©1982 by Texas Instruments Incorporated
3-35
II
::r;
"oens:
c
<
m
"en
m
3-36
TYPES SN54HC42, SN74HC42
4-L1NE TO 10-L1NE DECODERS (1-of-10)
HIGH-SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984'
SN54HC42 ... J PACKAGE
SN74HC42 ... J OR N PACKAGE
(TOP VIEW)
•
Full Decoding of Input logic
•
All Outputs Are High for Invalid BCD
Conditions
•
Also for Application as 3-line to 8-line
Decoders
•
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in' Addition to Plastic
and Ceramic DIPs
0
1
VCC
2
B
3
4
C
A
0
9
8
5
6
GND
Dependable Texas Instruments Quality and
Reliability
description
7
SN54HC42 ... FH OR FK PACKAGE
SN74HC42 ... FH OR FN PACKAGE
(TOPVIEWI
These monolithic decimal decoders consist of
eight inverters and ten four-input NAND gates.
The inverters are connected in pairs to make
BCD input data available for decoding by the
NAND gates. Full decoding of valid input logic
ensures that all inputs remain off for all invalid
input conditions.
U
II
U
U
.-oz><{
en
w
B
2
C
NC
3
NC
4
5
The SN54HC42 is characterized for operation
over the full military t,emperature range of
- 55°C to 125°C. The SN74HC42 is
characterized for operation from - 40°C to
85°C.
(.)
:>w
o
9
c
en
COOUI'CO
Z
o
Z
c:J
FUNCTION TABLE
:E
NC-No internal connection
NO.
0
1
2
3
4
5
6
7
8
9
0
::::i
<{
>
~
INPUTS
0
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
L
H
L
H
0
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
1
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
2
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
OUTPUTS
3 4 5 6
H H H H
H H H H
H H H H
L H H H
H L H H
H H L H
H H H L
H H H H
H H H H
H H H H
H H H H
H H H H
H H H H
H H H H
H H H H
H H H H
7
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
8
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
9
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
(.)
::J:
logic symbol
BCD/DEC
A
(151
B
(141
C
(131
o
(121
4
Pin numbers shown are for J and N packages.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS
"'!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-37
TYPES SN54HC42, SN74HC42
4-UNE TO 10-UNE DECODERS (1-of-10)
logic diagram (positive logic)
INPUT A(15)
INPUT 8(14)
J:
(")
~
o
o
C
m
<
(")
m
o
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), ,CL = 50 pF (see Note 1)
.
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
vcc
tpd
A. B. C.
or 0
o thru 9
4.5 V
tt
TA = 25°C
MIN TYP MAX
2V
6V
2V
Any
150
30
45
38
14
26
75
38
110
32
95
15
22
13
19
19
16
Power dissipation capacitance
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
UNIT
190
39 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
3-38
MAX
65
18
8
7
6V
SN74HC42
MIN
MAX
225
28
4.5 V
SN54HC42
MIN
ns
ns
TYPES SN54HC51, SN74HC51
AND·OR·INVERT GATES
HIGH·SPEED
CMOS LOGIC
02684, DECEMBER 1982-REVISED MARCH 1984
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality
and Reliability
SN54HC51 ••. JPACKAGE
SN74HC51 •.• J OR N PACKAGE
ITOPVIEW)
description
The 'HC5l provides 2-wide, 2-input, and 2-wide,
3-input AND-OR-INVERT gates. The device performs
the following Boolean functions:
=
(2A.2B)
+ (2C·2D)
111
&
FUNCTION TABLES
;;;'1
INPUTS
lC 10
(lzl
1E
lB
X
H
H
X
H
X
X
H
Any other combination
lA
H
X
1C
10
lF
X
H
OUTPUT
lV
L
L
H
1E
INPUTS
2C
2B
X
H
H
X
1F
ZA
H
X
ZA
ZB
\
20
X
H
AnV other combination
ZC
1E
10
GNO
-o...._ _-r-1Y
28
NC
2C
NC
20
logic symbol
lB
20
2Y
~ ~ ~ ~~
The SN54HC5l is characterized for operation over the
full military temperature range of - 55°C to 125°C.
The SN74HC51 is characterized for operation from
-40°C to 85°C.
lA
18
1F
SN54HC51 ... FH OR FK PACKAGE
SN74HC51 •.. FH OR FN PACKAGE
ITOPVIEW)
u
lY = (lA·1B·1CI + 11D·1E·1F)
2Y
1A
2A
28
2C
II
18
NC
1F
NC
1E
en
w
9 1011 1213
(.)
:>w
>ou>o
N Z Z ......
c.:J
c
NC-No internal connection
en
OUTPUT
2V
L
L
H
o
~
(.)
:t:
ZD
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
Any
Y
tt
vcc
2V
4.5 V
6V
2V
4.5 V
6V
Y
TA = 25°C
MIN
TYP MAX
140
54
15
12
28
9
8
28
24
75
15
13
SN54HC51
MAX
MIN
210
42
36
110
Power disSipation capacitance per AOI gate
22
19
SN74HC51
MIN
MAX
175
35
30
95
19
16
UNIT
ns
ns
25 pF typ
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
Copyright
W
10
0
N N
C
(!)
INPUTS
PRE
L
H
l
H
H
H
ClR
H
L
l
H
H
H
(J)
NC-No internal connection
FUNCTION TABLE
OUTPUTS
ClK
0
Q
il
X
X
X
X
X
X
H
L
Ht
l
H
Ht
t
t
H
L
H
L
L
H
L
X
00
00
o
:?!
logic symbol
(J
:t:
1Q
1ClK
10
lClR
2PRE
2Q
2ClK
20
tThis configuration is nonstable; that is. it will not
persist when Preset or Clear returns to its inactive (high)
level.
2ClR
Pin numbers shown are for J and N packages.
logic diagram, each flip-flop (positive logic)
PRE----------------------------~~----~
ClK.~:
Q
D
----------1
ij
CIA ----------------__-----------------------------~
Copyright ©1982 by Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-41
TYPES SN54HC74, SN74HC74
DUAL D·TYPE POSITIVE·EDGE·TRIGGERED
FLlp·FLOPS WITH CLEAR AND PRESET
maximum ratings, recommended operating conditions, and electrical characteristics
See Table II, page 2-6.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
Clock frequency
fclock
PRE or ClR
low
Pulse duration
tw
ClK
high or low
II
Data
Setup time
tsu
before ClK t
PRE or ClR
:I:
inactive
('")
S
o
Hold time data after ClK t
th
rJ)
o
m
<
SN54HC74
TA - 25°C
MAX
6
MIN
2V
MIN
0
4.5 V
0
31
6V
36
vcc
SN74HC74
MAX
4.2
MIN
0
0
21
0
5
25
0
25
0
29
0
2V
0
100
150
125
4.5 V
20
30
25
6V
2V
17
80
16
25
120
21
100
24
20
14
20
17
150
4.5 V
100
20
125
25
6V
17
25
21
2V
4.5 V
25
5
40
8
30
4.5 V
6V
2V
30
MAX
UNIT
MHz
ns
ns
6
6V
4
7
5
2V
0
0
0
4.5 V
0
0
0
6V
0
0
0
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
('")
m
PARAMETER
rJ)
FROM
(INPUT)
TO
(OUTPUT)
f max
PRE or ClR
OorO
tpd
ClK
tt
Oor
0
OorQ
Vee
TA = 25°C
MIN
TYP MAX
SN54HC74
MIN
2V
4.5 V
6
31
10
50
4.2
20
5
25
6V
2V
36
60
25
29
70
230
345
20
46
69
58
6V
15
39
59
49
2V
70
175
250
220
4.5 V
35
6V
20
15
44
37
2V
28
30
75
50
42
110
4.5 V
8
15
22
95
19
6V
6
13
19
16
I No load, TA
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS . "
INSTRUMENTS
POST OFFIce BOX 225012 • DALLAS. TeXAS 75265
= 25°C
UNIT
MHz
4.5 V
Power dissipation capacitance per flip-flop
3-42
SN74HC74
MIN
MAX
MAX
290
I
35 pF typ
ns
ns
TYPES SN54HC75, SN74HC75
4·BIT BISTABLE LATCHES
HIGH·SPEED
CMOS LOGIC
02684, DECEMBER 1982-REVISED MARCH 1984
•
Complementary Q and Q Outputs
•
Package Options Include Both Plastic
and Ceramic Chip Carriers in Addition to
Plastic and Ceramic DIPs
•
SN54HC75 ••• J PACKAGE
SN74HC75 •.. J OR N PACKAGE
(TOP VIEW)
10
10
20
3C,.4C
VCC
3D
40
40
Dependable Texas Instruments Quality
and Reliability
description
These latches are ideally suited for use as
temporary storage for binary information
between processing units and input/output or
indicator units. Information present at a data
(0) input is transferred to the Q output when
the enable (C) is high and the Q output will
follow the data input as long as the enable
remains high. When the enable goes low, the
information (that was present at the data input
at the time the transition occurred) is retained
at the Q output until the enable is permitted to
go high.
1 U16
2
15
3
14
4
13
5
12
6
11
10
8
9
10
20
20
1C,2C
GNO
30
30
40
For functionally and electrically
identical parts in chip carrier packages.
see SN54HC375 and SN74HC375.
logic symbol
II
VJ
w
(J
The SN54HC75 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC75 is
characterized for operation from - 40°C to
85°C.
:>w
c
VJ
o
~
Pin numbers shown are for J and N packages.
FUNCTION TABLE
(J
(Each Latch)
INPUTS
C
H
L
OUTPUTS
H
H
H
L
X
L
00
00
D
Q
Q
L
H
l:
logic diagram, each latch (positive logic)
o
r-----------,
I
I
II
C
COMMON TO ONE
II
OTHER LATCH
L ___________
J
'1!1
INSTRUMENTS
Copyright © 1982 by Texas Instruments Incorporated
TEXAS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-43
TYPES SN54HC75, SN74HC75
4·BIT BISTABLE LATCHES
maximum ratings, recommended operating conditions, and electrical characteristics
See Table II, page 2-6.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
2V
tw
Pulse duration, C high
tsu Setup time. data before C ~
th
Hold time. data after C ~
TA
25°C
R
MIN
MAX
SN54HC75
MIN
MAX
120
24
SN74HC75
MIN
MAX
4.5 V
80
16
100
20
6V
14
20
17
125
2V
100
150
4.5 V
20
30
25
6V
2V
17
5
26
5
21
5
4.5 V
5
5
6V
5
5
5
5
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
:I:
n
s:
o
PARAMETER
tpd
en
c
m
tpd
S
nm
tt
en
FROM
(INPUT)
TO
(OUTPUT)
QorO
0
C
QorO
Any
VCC
TA
MIN
25°C
a
SN54HC75
MIN
MAX
MIN
MAX
UNIT
MAX
2V
40
120
180
150
4.5 V
14
24
36
11
44
20
130
31
195
30
26
165
ns
6V
2V
4.5 V
15
26
39
12
33
110
33
28
ns
6V
95
2V
38
22
75
4.5 V
8
15
22
19
6V
6
13
19
16
Power diSSipation capacitance per latch
46 pF typ
NOTE 1: For load circuits and voltage waveforms. see page 1-14:
3-44
SN74HC75
TVP
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
ns
TYPES SN54HC76, SN74HC76
DUAL J·K FLlp·FLOPS WITH CLEAR AND PRESET
HIGH·SPEED
CMOS LOGIC
02684. DECEM8ER 1982-REVISED MARCH 1984
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality
and Reliability
SN54HC76 ... J PACKAGE
SN74HC76 ... J OR N PACKAGE
(TOP VIEW)
1CLK
1PRE
1CLR
1J
description
These devices contain tWo independent J-K negativeedge-triggered flip-flops. A low level at the Preset or
Clear input sets or resets the outputs regardless of
the levels of the other inputs. When Preset and
Clear are inactive (high). data at the J and K inputs
meeting the setup time requirements are transferred
to the outputs on the negative-going edge of the
clock pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the clock
pulse. Following the hold time interval, data at the J
and k inputs may be changed without affecting the
levels at the outputs. These versatile flip-flops can
also perform as toggle flip-flops by tying J and K
high.
Vee
2CLK
2PRE
2CLR
For functionally and electrically identical
parts in chip carrier packages, see
SN54HC112 and SN74HC112.
1PiiE
1J
CLR
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
CLK
X
X
X
+
+
+
+
H
OUTPUTS
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
Q
Q
H
L
L
H
H*
H*
00
Co
en
w
1CLK"':";'~::::...jD
(EACH FLIP-FLOP)
PRE
L
II
logic symbol
1K
(J
1CLR
>
W
FUNCTION TABLE
INPUTS
1K
1Q
10
GND
2K
2Q
20
2J
1PRE
2J
c
en
2Q
2CLK -'-"-Io.~I'>
o
2K
:aE
2CLR
L
H
L
TOGGLE
(J
H
00
J:
Pin numbers shown are for J and N packages.
Co
*This configuration is nonstable; that is. it will not persist when
either Preset or Clear returns to its inactive (high) level.
logic diagram, each flip-flop (positive logic)
PRE ------------------~----------------~.-----------_,
erR --------------------------~~--------------------------------~
Copyright ©1982 by Texas Instruments Incorporated
TEXAS
-1.!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-45
TYPES SN54HC76, SN74HC76
DUAL J·K FLlp·FLOPS WITH CLEAR AND PRESET
maximum ratings, recommended operating conditions, and electrical characteristics
See Table II, page 2-6.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
PRE or ClR low
tw
Pulse duration
ClK high or low
II
Data
tsu
Setup time before ClK.
PRE or ClR
inactive
:I:
(")
S
oen
~
<
th
Hold time after ClK.
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
0
6
31
0
0
36
100
20
17
80
16
14
150
30
25
100
20
17
0
0
0
SN54HC76
MIN
MAX
4.2
0
21
0
0
25
150
30
25
120
24
20
225
45
38
150
30
25
0
0
0
SN74HC76
MIN
MAX
0
5
25
0
0
29
125
25
21
100
20
17
190
38
32
125
25
21
0
0
0
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperture range (unless otherwise
noted), CL = 50 pF (see Note 1)
(")
PARAMETER
m
en
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6 V'
f max
tpd
PRE or ClR
QorO
tpd
ClK
QorO
tt
Qor
0
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
9
6
41
31
50
36
155
65
16
31
15
26
70
145
19
29
16
25
38
75
8
15
13
6
Power dissipation capacitance per flip-flop
SN54HC76
MIN
MAX
4.2
21
25
No load. TA
NOTE 1: For load circuit and voltage 'waveforms. see page 1-14.
3-46
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
250
47
40
220
44
37
110
22
19
=
25°C
SN74HC76
MIN
MAX
5
25
29
190
39
33
180
36
31
95
19
16
36 pF typ
UNIT
MHz
ns
ns
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC77, SN74HC77
4·BIT BISTABLE LATCHES
02684. DECEM8ER 1982-REVISED MARCH 1984
•
Package Options Include Both Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality
and Reliability
SN54HC77 ••• J PACKAGE
SN74HC77 •.• J OR N PACKAGE
ITOPVIEWI
10
20
3C,4C
VCC
description
These latches are ideally suited for use as
temporary storage for binary information
between processing units and input/output or
indicator units. Information present at a data
(0) input is transferred to the Q output when
the enable (C)· is high and the Q output will
follow the data input as long as the enable
remains high. When the enable goes low, the
information (that was present at the data input
at the time the transition occurred) is retained
at the Q output until the enable is permitted'to
go high.
3D
40
NC
1Q
2Q
1C,2C
GNO
NC
3Q
4Q
NC-No internal connection
Not available in chip carrier package
with JEDEC-Standard pin-out. For chip
carrier information, contact the
factory.
II
logic symbol
10 (1)
The SN54HC77 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC77 is'
characterized for operation from - 40°C to
85°C.
10
en
w
2Q
(.)
3Q
c
o
:>w
FUNCTION TABLE
en
lEach Latchl
INPUTS
0
C
OUTPUT
::?i
Q
L
H
L
H
H
H
X
L
00
(.)
Pin numbers shown are for J and N packages.
J:
logic diagram, each latch (positive logic)
o
Q
r----------,
I
I
I
C
COMMON TO ONE
IL _________
OTHER LATCH
--1I
Copyright © 1982 by Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
, POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-47
TYPES SN54HC77, SN74HC77
4·BIT BISTABLE LATCHES
maximum ratings, recommended operating conditions, and electrical characteristics
See Table II, page 2-6.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
tw
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Pulse duration, C high
tsu Setup time, data before C !
III
th
Hold time, data after C !
TA - 25"C
MAX
MIN
80
16
14
100
20
17
5
5
5
SN54HC77
MIN
MAX
120
24
20
150
30
26
5
5
5
SN74HC77
MIN
MAX
100
20
17
125
25
21
5
5
5
UNIT
ns
ns
ns
switching charactarlstics over recommended operating free-air temperature range lunless otherwise
noted), CL = 50 pF (see Note 1)
::I:
o
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
o
en
tpd
0
Q
tpd
C
Q
3:
c
m
<
o
m
tt
en
Any
TA-25"C,
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
MIN
TYP
40
12
10
45
14
11
28
8
6
MAX
120
24
20
130
26
22
75
15
13
SN54HC77
MIN
MAX
180
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
3-48
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
36
31
195
39
33
110
22
19
SN74HC77
MIN
MAX
150
30
26
165
33
28
95
19
16
UNIT
ns
ns
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HCB6. SN74HCB6
QUADRUPLE 2·INPUT EXCLUSIVE·OR GATES
02684. DECEMBER 1982-REVISED MARCH 1984
• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs
SN54HCB6 ... J PACKAGE
SN74HC86 ... J OR N PACKAGE
(TOP VIEW)
• Dependable Texas Instruments Quality and Reliability
1A
1B
1Y
2A
28
2Y
GND
description
These devices contain four independent 2-input ExclusiveOR gates. They perform the Boolean functions
Y = A<±> B = AB + AS in positive logic.
VCC
48
4A
4Y
38
3A
3Y
A common application is as a true/complement element. If one
of the inputs is low, the other input will be reproduced in true
form at the output. If .one of the inputs is high, the signal on
the other input will be reproduced inverted at the output.
SN54HC86 ... FH OR FK PACKAGE
SN74HC86 ... FH OR FN PACKAGE
(TOP VIEW)
The SN54HC86 is characterized for operation over the full
military temperature range of - 55°C to 125°C. The SN74HC86
is characterized for operation from -40°C to 85°C.
.-.-Z>V
FUNCTION TABLE
(each gate)
INPUTS
B
L
3A
38
4A
48
(13)
OUTPUT
V
L
H
H
H
L
H
H
H
L
II
4A
1Y
NC
2A
NC
28
logic symbol
A
L
L
u
cow
c
>-ou>- ...
10
NC
1K
NC
20
II
1CLK
NC
2K
NC
2CLR
12
en
w
U
>
w
c
~ ~ ~ ~
~
C)
en
o
2
NC-No internal connection
u
FUNCTION TABLE
logic symbol
INPUTS
ClR
L
elK
X
H
H
H
H
H
.\.
.\.
. .\.
.\.
H
J
X
L
H
L
H
X
K
X
L
L
H
H
X
J:
OUTPUTS
0
0
L
H
00
00
H
L
H
L
TOGGLE
00
00
Pin ·numbers shown are for J and N packages.
Copyright © 1982. Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-51
TYPES SN54HC107, SN74HC107
DUAL J·K NEGATIVE·EDGE·TRIGGERED
FLlp·FLOPS WITH CLEAR
logic diagram, each flip·flop (positive logic)
Q
K-~"""'-
CLK~:
II
CIR---------------~
maximum ratings, recommended operating conditions, and electrical characteristics
See Table II, page 2-6.
::t:
n
~
o
en
cm
<
nm
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
en
vCC
fclock
Clock frequency
tw
Pulse duration
ClR low
ClK high or low
Data (J, K)
tsu
Setup time
before ClK.
ClR inactive
th
3-52
Hold time, data after ClK.
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MAX
MIN
0
0
0
100
20
17
80
16
14
6
31
36
100
20
17
100
20
17
0
0
0
TEXAS
SN54HC107
SN74HC107
MIN
MAX
MIN
MAX
0
0
0
150
30
25
120
24
20
150
30
25
150
30
25
0
0
0
4.2
21
25
0
0
0
125
25
21
100
20
17
125
25
21
125
25
21
0
0
0
5
25
29
~
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265
UNIT
MHz
ns
ns
ns
TYPES SN54HC107, SN74HC107
DUAL J·K NEGATIVE·EDGE·TRIGGERED
FLlp·FLOPS WITH CLEAR
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
.
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
tpd
ClR
Oor Q
tpd
ClK
o orO
tt
OorO
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
6
9
45
31
36
53
126 155
25
31
21
26
100 125
20
25
17
21
38
75
8
15
6
13
SN54HC107
MIN
MAX
4.2
21
25
235
47
40
185
37
32
110
22
19
SN74HC107
MIN
MAX
5
25
29
195
39
32
160
32
27
95
19
16
35 pF typ
Power dissipation capacitance per flip-flop
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
UNIT
MHz
ns
ns
ns
•
en
w
u
:>w
o
en
o
:2E
u
:t:
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-53
111
J:
(")
s:
o
en
cm
<
(")
m
en
3-54
TYPES SN54HC109, SN74HC109
DUAL J·R POSITIVE·EDGE·TRIGGERED
FLlp·FLOPS WITH CLEAR AND PRESET
HIGH·SPEED
CMOS LOGIC
02684, DECEMBER 1982 - REVISED MARCH 1984
•
•
SN54HC109 ... J PACKAGE
SN74HC109 ... J OR N PACKAGE
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
(TOP VIEW)
1ClR
1J
1K
1ClK
Dependable. Texas Instruments Quality and
Reliability
description
These devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the Preset or Clear inputs sets .or resets the
outputs regardless of the levels of the other
inputs. When Preset and Clear are inactive
(high), data at the J and R inputs meeting the
setup time requirements are transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold time interval,
data 'at the J and K inputs may be changed
without affecting the levels at the outputs.
These versatile flip-flops can perform as toggle
flip-flops by grounding Kand tying J high. They
also can perform as D-type flip-flops if J and K
are tied together.
The SN54HCl 09 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC109 is
characterized for operation from - 40°C to
85°C.
VCC
2ClR
2J
21<
2ClK
2PRE
20
20
SN54HC109 ... FH OR FK PACKAGE
SN74HC109 ... FH OR FN PACKAGE
(TOP VIEW)
0:
ulO:
..,..........
ud
1d uZ>N
II
2J
21<
NC
2ClK
2PRE
11<
1ClK
NC
10 0
C1J
w
(.)
:>w
c
o
U 10 0
..... ZZNN
C1J
(!J
~
NC-No internal connection
(.)
logic symbol
J:
FUNCTION TABLE
INPUTS
PRE
ClR
ClK
l
H
H
OUTPUTS
K
Q
X
J
X
X
H
l
L
X
X
X
L
H
Q
L
L
X
X
X
H*
H*
H
H
L
L
L
H
H
H
H
L
TOGGLE
H
H
H
H
t
t
t
t
H
H
L
L
H
00
H
H
H
L
X
X
00
00
00
Pin numbers shown are for J and N packages.
* This configuration is nonstable; that is, it will not
persist when Preset or Clear return to their inactive
(high) level.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012. DALLAS. TEXAS 75265
Copyright ©1982 by Texas Instruments Incorporaied
3-55
TYPES SN54HC109, SN74HC109
DUAL J.l{ POSITIVE·EDGE·TRIGGERED FLlp·FLOPS WITH CLEAR AND PRESET
logic diagram, each flip-flop (positive logic)
~--------------------------------~~------~
a
"K---+-I
~-------------------------4------------------------------~
II
maximum ratings, recommended operating conditions, and electrical characteristics
See Table II, page 2-6.
:I:
('")
S
oC/)
C
m
~
('")
m
C/)
3-56
-II}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 .
TYPES SN54HC109, SN74HC109
DUAL J.i{ POSITIVE·EDGE·TRIGGERED FLlP·FLOPS WITH CLEAR AND PRESET
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
VCC
2V
4.5 V
6V
2V
4.5 V
Clock frequency
fclock
PRE or ClR
low
'6V
2V
4.5 V
6V
2V
4.5 V
Pulse duration
tw
ClK high
or low
Data (J, K)
Setup time
before ClK t
tsu
PRE or ClR
Hold time, data after ClK t
OK
25°C
MAX
6
31
36
SN54HC109
MIN
0
0
0
150
30
25
80
16
14
100
120
24
20
150
20
17
30
25
40
8
7
0
6V
2V
4.5 V
6V
2V
4.5 V
6V
inactive
th
TA
MIN
0
0
0
100
20
17
25
5
4
0
0
0
MAX
4.2
21
25
SN74HC109
MIN
MAX
5
0
25
0
0
125
25
21
MHz
29
ns
100
20
17
125
25
21
ns
30
6
5
0
0
0
0
0
UNIT
II
ns
Ul
w
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
2V
4.5 V
f max
tpd
PRE or CIR
Qora.
tpd
ClK
Qora.
tt
Cpd
VCC
QorQ
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
6
10
31
50
36
60
60 230
46
15
39
12
175
50
15
35
12
30
28
8
6
Power dissipation capacitance per flip-flop
SN54HC109
MIN
MAX
4.2
21
25
75
15
13
345
69
59
250
50
42
110
22
19
No load, TA = 25°C
SN74HC109
MIN
MAX
5
25
29
290
58
49
220
44
37
95
19
16
(.)
:;
w
C
UNIT
Ul
o
MHz
~
(.)
:::t:
ns
ns
ns
35 pF typ
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-57
II
J:
o
s:
o(J)
C
m
S
o
m
(J)
3-58
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC112, SN74HC112
DUAL J·K NEGATIVE·EDGE·TRIGGERED FLlp·FLOPS
WITH CLEAR AND PRESET
02684. DECEM8ER 1982-REVISED MARCH 1984
•
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN54HC112 ... J PACKAGE
SN74HC112 .• , J OR N PACKAGE
(TOP VIEW)
Dependable Texas Instruments Quality and
Reliability
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the Preset or Clear inputs sets or resets the
outputs regardless of the levels of the other
inputs. When Preset and Clear are inactive
(high), data at the J and K inputs meeting the
setup time requirements are transferred to the
outputs on the negative-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold time interval,
data at the J and K inputs may be changed
without affecting the levels at the outputs.
These versatile flip-flops can perform as toggle
flip-flops by tying J and K high.
GND
SN54HC112 ••• FH OR FK PACKAGE
SN74HC112 ••. FH OR FN PACKAGE
(TOP VIEW)
.~
3
H
L
eLK
J
X
X
X
K
Q
X
X
X
H
L
L
H
H*
H*
L
00
00
L
L
H
H
~
L
II
1
2CLR
2CLK
NC
2K
2J
en
w
o
>
w
c
en
o
9 1011 1213
10 C u 0l~
N~ZN~
~
NC-No internal connection
OUTPUTS
X
X
X
2
1J
1PRE
NC
10
10
FUNCTION TABLE
INPUTS
CLR
H
ul5
:J
u u uu
.-.-z>.-
The SN54HC112 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC112 is
characterized for operation from - 40°C to
85°C.
PRE
L
VCC
1CLR
2CLR
2CLK
2K
2J
2PRE
20
1CLK
1K
1J
1PRE
10
10
20
H
H
~
H
L
H
L
H
~
L
H
L
H
H
H
~
H
H
H
H
H
X
X
:I:
logic symbol
Q
H
o
TOGGLE
00
00
"This configuration is nonstable; that is. it will not persist when
either Preset or Clear returns to its inactive (high) level.
Pin numbers shown are for J and N packages.
Copyright © 1982, Texas Instruments Incorporated
TEXAS
"'.!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-59
TYPES SN54HC112, SN74HC112
DUAL J·K NEGATIVE·EDGE·TRIGGERED FLlp·FLOPS
WITH CLEAR AND PRESET
logic diagram, each flip-flop (positive logic)
PRE--------------------------------~~------~
Q
K
CLR------------------------~~----------------------------~
_
maximum ratings, recommended operating conditions, and electrical characteristics
See Table II, page 2-6.
_
::t
n
S
o
rn
c
m
S
n
m
rn
3-60
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC112, SN74HC112
DUAL J·K NEGATIVE·EDGE·TRIGGERED FLlp·FLOPS
WITH CLEAR AND PRESET
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
Clock frequency
fclock
PRE or CLR low
Pulse duration
tw
Data (J,K)
Setup time
tsu
before ClK!
PRE or CLR
inactive
Hold time, data after CLK!
th
SN54HC112
SN74HC112
MIN
MAX
MIN
5
0
3.3
0
2V
0
4.5 V
0
25
0
17
0
6V
2V
0
100
29
0
150
20
0
125
4.5 V
20
30
25
6V
17
100
25
150
21
125
20
17
100
30
6V
2V
25
150
25
21
125
4.5 V
20
30
25
6V
17
25
21
2V
CLK high or low
TA -25°C
MAX
MIN
4.5 V
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
4.5 V
0
0
6V
0
0
0
0
0
0
0
MAX
4
20
24
UNIT
MHz
ns
ns
ns
II
ns
ns
en
w
(.)
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
VCC
2V
5
10
4.5 V
25
29
6V
tpd
tpd
tt
Cpd
PRE or CLR
CLK
a ora
a or
a
aorO
TA = 25°C
MIN
TYP MAX
SN54HC112
MIN
SN74HC112
MAX
MIN
3.3
4
50
17
60
20
20
24
MAX
W
c
UNIT
en
o
:E
MHz
(.)
2V
54
165
245
4.5 V
6V
16
13
33
28
49
42
2V
56
16
125
185
4.5 V
25
37
155
31
6V
13
21
31
26
2V
29
75
110
95
4.5 V
6V
9
8
15
13
22
19
'19
16
Power dissipation capacitance per flip-flop
>
205
41
::J:
ns
35
ns
ns
35 pF typ
I
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-61
II
J:
(")
!:
o
t/)
C
m
$
(")
m
t/)
3-62
TYPES SN54HC113, SN74HC113
DUAL J·K NEGATIVE·EDGE·TRIGGERED
FLlP·FLOPS WITH PRESET
HIGH·SPEED
CMOS LOGIC
02684, DECEMBER 1982-REVISED MARCH 1984
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC113 .•• J PACKAGE
SN74HC113 •.. J OR N PACKAGE
(TOP VIEW)
1CLK
1K
1J
1PRE
10
10
GND
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the Preset input sets the outputs regardless of
the levels of the other inputs. When Preset (PRE)
is inactive (high), data at the J and K inputs
meeting the setup time requirements are
transferred to the outputs on the negative-going
edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to
the rise time of the clock pulse. Following the
hold time interval, data at the J and K inputs may
be changed without affecting the outputs. These
versatile flip-flops can perform as toggle flipflops by tying J and K high.
SN54HC113 ••. FH OR FK PACKAGE
SN74HC113 ••• FH OR FN PACKAGE
(TOP VIEW)
~
FUNCTION TABLE
:J
U
U
U:J
uu
........ Z>N
II
2K
NC
2J
NC
2PRE
1J
NC
1PRE
NC
10
The SN54HC113 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC113 is
characterized for operation from - 40°C to
85°C.
en
w
()
>
W
I~ ~ ~I~ ~
C
l!l
en
NC-No internal connection
o
~
logic symbol
OUTPUTS
INPUTS
VCC
2CLK
2K
2J
2PRE
20
20
PRE
ClK
J
K
a
a
l
H
x
X
X
H
l
.j.
l
l
H
.j.
H
L
H
L
H
.j.
L
H
.j.
H
H
H
L
TOGGLE
H
H
X
X
00
::I:
10
1J
1ClK
1K
aD 00
H
()
1~
1li
2liRr
20
2J
2ClK
2K
aD
logic diagram, each flip·flop (positive logic)
Pin numbers shown are for J and N packages.
PRE ----------------------------------------------------~
a
K
elK
-----------Ccf>-tt>::;
TEXAS
'1.!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright ©1982 by Texas Instruments Incorporated
3-63
TYPES SN54HC113, SN74HC113
DUAL J·K NEGATIVE·EDGE·TRIGGERED
FLlp·FLOPS WITH PRESET
maximum ratings, recommended operating conditions, and electrical characteristics
See Table II, page 2-6.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
vCC
2V
Clock frequency
fclock
PRE low
Pulse duration
tw
ClK high or low
II
Data (J, K)
Setup time
before ClK~
tsu
:J:
PRE inactive
n
s:o
rn
c
m
<
Hold time. data after ClK +
th
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
6
31
36
100
20
17
80
16
14
100
20
17
25
5
4
0
0
0
SN54HC113
MIN
MAX
4.2
21
25
150
30
25
120
24
20
150
30
25
40
8
7
0
0
0
SN74HCl13
MIN
MAX
5
25
29
125
UNIT
MHz
25
21
100
20
17
125
ns
25
21
30
6
5
0
0
ns
ns
ns
ns
0
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
n
m
PARAMETER
rn
FROM
(INPUT)
TO
(OUTPUT)
f max
tpd
'PRE
aorO
tpd
ClK
aorO
tt
aorO
VCC
TA = 25°C
MIN TYP MAX
2V
4.5 V
6
31
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
36
10
50
60
60
18
15
85
19
16
28
8
6
SN54HC113
MIN
MAX
4.2
21
25
165
250
33
28
140
28
24
50
43
210
42
75
15
13
Power dissipation capacitance per flip-flop .
TEXAS
5
25
29
"'.!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
UNIT
MHz
205
41
35
175
35
30
95
19
16
35 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
3-64
36
110
22
19
SN74HCl13
MIN
MAX
ns
ns
ns
TYPES SN54HC114, SN74HC114
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH PRESET, COMMON CLEAR, AND COMMON CLOCK
HIGH-SPEED
CMOS LOGIC
02684, DECEMBER 1982-REVISED MARCH 1984
•
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
'
SN54HCl14 ... J PACKAGE
SN74HCl14 .•. J OR N PACKAGE
(TOP VIEW)
ClR
1K
1J
1PRE
10
10
GND
Dependable Texas Instruments Quality and
Reliability
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. a low level at
the Preset or Clear inputs sets or resets the
outputs regardless of the levels of the other
inputs. When the Preset and Clear are inactive
(high), data at the J and K inputs meeting the
setup time requirements are transferred to the
outputs on the negative-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold time interval,
data at the J and K inputs may be changed'
without affecting the levels at the outputs.
These versatile flip-flops can perform as toggle
flip-flops by tying J and K high.
SN54HCl14 ... FH OR FK PACKAGE
SN74HCl14 ... FH OR FN PACKAGE
(TOP VIEW)
5
::.:: U U
CLR
CLK
L
H
H
L
L
L
H
H
H
H
X
X
X
I
I
U..J
II
2K
NC
2J
NC
2PRE
1J
NC
1PRE
NC
10
en
w
CJ
>
w
c
en
o
100 UIO 0
.-ZZNN
(!)
NC-No internal connection
:?!
CJ
J:
logic symbol
OUTPUTS
INPUTS
PRE
u~
1
.-.-z>u
The SN54HC114 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC114 is
characterized for operation from - 40°C to
85°C.
FUNCTION TABLE
VCC
ClK
2K
2J
2PRE
20
25
J
X
X
X
K
Q
Q
CLR
X
X
X
H
L
CLK
L
H
H*
"PRE
H*
L
L
00
00
H
L
H
L
H
H
H
I
L
H
L
H
H
I
H
H
TOGGLE
H
H
H
X
X
00
10
lJ
10
lK
2PRE
20
2J
20
2K
00
* This configuration is nonstable; that is, it will not persist
Pin numbers shown are for J and N packages.
when either Preset of Clear returns to its inactive (high)
level.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-65
TYPES SN54HCl14. SN14HCl14
DUAL J·K NEGATIVE·EDGE·TRIGGERED FLlp·FLOPS
WITH PRESET. COMMON CLEAR. AND COMMON CLOCK
logic diagram, each flip·flop (positive logic)
PRE------------------------------~~-------,
J-----r--
Q
K---~-
r----------,
CLK~C
I
I
I
I
_
-
CUi
+l~I
C
I
maximum ratings, recommended operating conditions, and electrical characteristics
__
J:
See Table II, page 2-6.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
(')
VCC
3:
o
tJ)
fclock
Clock frequency
C
m
PRE or ClR
<
om
low
tw
Pulse duration
ClK high
or low
tJ)
Data (J.K)
Setup time
tsu
before
ClK~
PRE or ClR
inactive
th
3-66
Hold time. data after ClK ~
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
0
5
0
25
0
29
100
20
17
100
20
17
100
20
17
100
20
17
0
0
0
SN54HC114
MIN
MAX
0
3.3
0
17
0
20
150
30
25
150
30
25
150
30
25
150
30
25
0
0
0
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SN74HC114
UNIT
MIN
MAX
0
4
0
20 MHz
0
24
125
25
21
ns
125
25
21
125
25
21
ns
125
25
21
0
ns
0
0
TYPES SN54HC114, SN74HC114
DUAL J·K NEGTIVE·EDGE·TRIGGERED FLlp·FLOPS
WITH PRESET, COMMON CLEAR, AND COMMON CLOCK
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
tpd
tpd
tt
PRE or ClR
ClK
OorO
OorO
Oor Q
vCC
TA = 25°C
MIN
MAX
2V
5
9
4.5 V
6V
25
45
29
50
SN54HC114
MAX
SN74HC114
MIN
3.3
MIN
4
17
20
20
24
MAX
MHz
2V
75
175
250
220
4.5 V
35
50
44
6V
20
17
42
250
37
220
37
95
2V
63
30
175
4.5 V
19
35
6V
30
75
50
42
110
44
2V
16
28
4.5 V
8
15
22
19
6V
6
13
19
16
50 pF typ
Power dissipation capacitance
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
UNIT
ns
ns
ns
II
en
w
U
>
w
c
en
o
~
U
J:
TEXAS
"'J}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-67
II
J:
(")
~
otn
C
m
<
(;
m
tn
3-68
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC125. SN54HC126
SN74HC125. SN74HC126
OUADRUPLE BUS BUFFER GATES WITH 3·STATE OUTPUTS
D2804, MARCH 1984
•
SN54HC125, SN54HC126 . , . J PACKAGE
SN74HC125, SN74HC126 ... J OR N PACKAGE
Higl'!-Current 3-State Outputs Interface
Directly with System Bus or Can Drive Up
to 1 5 LSTTL Loads
(TOP VIEW)
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition td Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
1G,1Gt
1A
1Y
2G, 2Gt
2A
2Y
GND
description
These bus buffers feature independent line
drivers with three-state outputs. Each 'HC125
output is disabled when the associated G is high,
and each 'HC126 output is disabled when the
associated G is low.
SN54HC125, SN54HC126 ... FH OR FK PACKAGE
SN74HC125, SN74HC126 ... FH OR FN PACKAGE
(TOP VIEW)
The SN54HC125 and SN54HC126 are
characterized for operation over the full military
temperature range of - 55 DC to 125 DC. The
SN74HC125 and SN74HC126 are characterized
for operation from - 40 DC to 85 DC.
1Y
NC
2G, 2Gt
NC
2A
FUNCTION TABLES
'HC125
II
4A
NC
4Y
NC
3G, 3Gt
'HC126
(EACH BUFFER)
INPUTS
VCC
4G,4Gt
4A
4Y
3G, 3Gt
3A
3Y
G
A
OUTPUT
,y
L
H
L
H
(EACH BUFFER)
, INPUTS
A
Y
H
H
H
H
L
L
H
L
L
X
Z
L
X
Z
5>
w
c
en
o
OUTPUT
G
en
w
(J
tG
2
on 'HC125; G on 'HC126
(J
:I:
NC - No internal connection
logic symbols
'He126
'HC125
(1)
lG
lY
lA
(2)
EN
C>
(3)
\l
(6)
2Y
1Y
2Y
(8)
3Y
3Y
4G
4A (12)
4Y
(11)
4Y
Pin numbers shown are for J and N packages.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-69
TYPES SN54HC125, SN54HC126, SN74HC125, SN74HC126
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
logic diagrams (positive logic)
'HC126
'HC125
1Y
lG
(1)
lA
(2)
1Y
2(;
II
2A
2Y
2Y
J:
0
3:
0
en
3G
30
(10)
C
m
<
3A
3Y
(9)
3Y
0
m
en
4G
40
4A
Pin numbers shown are for J and N packages.
3-70
TEXAS
"'J}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4Y
TYPES SN54HC125, SN74HC125
QUADRUPLE BUS BUFFER GATES WITH 3·STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
switching characteristics over recommended operating free-air temperature range (unless otherwise
no~ed), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
vCC
TA = 25°C
MIN
TYP MAX
2V
tpd
ten
tdis
A
G
IT
Y
Y
Y
Any
tt
48
SN54HC125
MIN
120
SN74HC125
MAX
MIN
MAX
180
150
4.5 V
14
24
36
30
6V
11
20
31
26
150
2V
53
120
180
4.5 V
14
24
36
30
6V
11
20
31
26
2V
30
120
180
150
4.5 V
15
24
36
30
6V
14
20
31
26
2V
28
60
90
75
4.5 V
8
12
18
15
6V
6
10
15
13
UNIT
ns
ns
ns
ns
II
(J)
Power dissipation capacitance per gate
45 pF typ
W
U
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
tpd
ten
tt
FROM
(INPUT)
A
IT
TO
(OUTPUT)
Y
Y
Any
vCC
TA = 25°C
MIN
TYP MAX
SN54HC125
MIN
SN74HC125
MAX
MIN
MAX
2V
67
150
225
190
4.5 V
19
30
45
38
6V
15
39
200
32
170
2V
100
25
135
4.5 V
20
27
40
34
6V
17
23
34
29
265
2V
45
210
315
4.5 V
17
42
63
53
6V
13
36
53
45
UNIT
ns
>
w
C
(J)
o
~
U
J:
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-71
TYPES SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES WITH 3·STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
vCC
2V
tpd
ten
tdis
A
G
G
:I:
n
S
oen
MAX
180
SN74HC126
MIN
MAX
1S0
SNS4HC126
MIN
4.S V
14
24
36
30
6V
11
20
31
26
2V
4.5 V
57
120
180
150
y
16
24
36
30
12
35
17
20
120
31
180
26
150
y
6V
2V
4.5 V
24
36
30
6V
15
20
31
26
75
Y
Any
tt
TA = 2S o C
MIN
TYP MAX
47
120
2V
28
60
90
4.5 V
8
12
18
15
6V
6
10
15
13
UNIT
ns
ns
ns
ns
45 pF typ
Power dissipation capacitance per gate
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
c
PARAMETER
m
FROM
(INPUT)
TO
(OUTPUT)
:$
VCC
TA = 25°C
MIN
TYP MAX
tpd
A
Y
tt
G
y
Any
188
30
45
38
ns
15
100
25
135
39
202
4.5 V
20
·17
45
210
40
36
315
ns
6V
2V
27
23
33
.169
36
4.5 V
17
42
63
6V
13
36
53
4.5 V
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
3-72
UNIT
225
2V
ten
MAX
150
6V
en
SN74HC126
MIN
67
19
2V
nm
SN54HC126
MAX
MIN
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
30
265
53
45
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC133, SN74HC133
l3·INPUT POSITIVE·NAND GATES
02684, DECEMBER 19B2 - REVISED MARCH 1984
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC133 ... J PACKAGE
SN74HC133 ... J OR N PACKAGE
ITOPVIEW)
A
description
These devices contain a single 13-input NAND
gate. They perform the Boolean functions in
postive logic:
Y = A·B·C·D·E·F·G.H·I·J.K.L·M
Y
=
The SN54HC133 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC 133 is
characterized for operation from - 40°C to
85°C.
All)
0
E
G
K
E
J
L
F
G
GND
H
y
SN54HC133 ... FH OR FK PACKAGE
SN74HC133 ... FH OR FN PACKAGE
ITOPVIEW)
3 2
8<
(2)
II
2019
C
L
K
NC
E
F
en
w
u
J
:>w
(3)
c
t?OU>-I
(4)
zz
en
t?
(5)
(6)
H
C
D
D
NC
logic symbol
C
VCC
M
or
A+B+C+D+E+F+G+H+I+J+K+L+M
B
B
o
2
u
NC-No internal connection
(7)
(9)
y
(10)
:::t:
FUNCTION TABLE
(11)
INPUTS A THRU M
(12)
K
L
M
OUTPUT
Y
(13)
All inputs H
L
(14)
One or more inputs L
H
(15)
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
Copyright © 1982, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-73
TYPES SN54HC133, SN74HC133
13·INPUT POSITIVE·NAND GATES
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50pF (see Note 1)
PARAMETER
FROM
(INPUT)
(OUTPUT)
Vce
2V
70
150
225
tpd
Any
Y
4.5 V
16
30
45
38
6V
13
26
38
33
95
tt
TO
Y
TA = 25°C
MIN
TYP MAX
SN54HC133
MIN
MIN
MAX
2V
38
75
110
8
15
22
19
6V
6
13
19
16
24 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
:I:
n
3:
o
en
c
m
S
n
m
en
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
UNIT
190
4.5 V
Power dissipation capacitance
3-74
SN74HC133
MAX
ns
ns
TYPES SN54HC137. SN74HC137
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
HIGH·SPEED
CMOS LOGIC
02684, DECEMBER 1982-REVISED MARCH 1984
•
Combines Decoder and 3-Bit Address Latch
•
Incorporates 2 Output Enables to Simplify
Cascading
•
•
SN54HC137 ..• J PACKAGE
SN74HC137 ... J OR N PACKAGE
(TOP VIEW)
A
B
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
VCC
YO
Yl
Y2
Y3
Y4
Y5
Y6
C
GL
<32
Gl
Y7
GND
Dependable Texas Instruments Quality and
Reliability
description
The 'HC 137 is a three-line to eight-line
decoder/demultiplexer with latches on the three
address inputs. When the latch-enable input (GL)
is
low,
the
'HC137
acts
as
a
decoder/demultiplexer. When GL goes from low
to high, the address present at the select inputs
(A, B, and C) is stored in the latches. Further
address changes are ignored as long as GL
remains high. The output enable controls, G 1
and <32, control the outputs independently of the
select or latch-enable inputs. All of the outputs
are forced high if G 1 is low or G2 is high. The
'HC137 is ideally suited for implementing glitchfree decoders in strobed (stored-address)
applications in bus-oriented systems.
SN54HC137 ... FH OR FK PACKAGE
SN74HC137 ... FH OR FN PACKAGE
(TOP VIEW)
U
u Uo
II
al<{Z>>-
GI
Yl
Y2
NC
NC
<32
Gl
Y3
Y4
C
en
w
(.)
:>w
c
r--OUCOL!)
>-Zz>->-
en
<.9
The SN54HC137 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC137 is
characterized for operation from - 40°C to
85°C.
o
2
NC-No internal connection
(.)
::I:
logic symbols (alternatives)
X/V
·DMUX
A
B
C
0
(1)
(2)
(3)
JGt
2
3
4
EN
·G1
G2
5
6
V6
7
V7
Pin numbers shown are for J and N packages.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-75
TYPES SN54HC137 SN74HC137
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
FUNCTION TABLE
INPUTS
ENABLE
GL G1
OUTPUTS
SELECT
G2
C
B
A
VO
V1
V2
V3
V6
V7
X
X
X
H
X
X
H
H
H
H
H
H
H
H
X
X
X
H
L
X
X
H
H
H
L
L
L
H
H
L
L
H
H
H
H
H
L
L
H
H
H
H
H
L
L
H
H
H
H
H
H
L
H
L
H
L
L
L
H
L
H
L
L
H
L
H
L
H
L
H
H
L
L
L
L
L
H
H
L
L
H
H
H
H
L
H
H
H
H
H
L
X
X
X
V4 V5
H
H
L
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
Output corresponding to stored
address, L; all others, H
illogiC diagram (positive logic1
J:
(")
~
GL
0
rn
(15)
C
VO
m
<
(14)
(")
V1
m
rn
(13)
Y2
(12)
Y3
(11)
(10)
(9)
Y4
Y5
Y6
G1
Y7
G2
Pin numbers shown are for J and N packages.
3-76
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC137, SN74HC137
3·L1NE TO B·L1NE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
absolute maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2·' O.
timing requirements over recommended operating free· air: temperature range (unless otherwise noted)
vcc
2V
Pulse duration,
tw
GL low
4.5 V
Setup time, A, B, and C before
tsu
Hold time, A, B, and C after
th
TA
MIN
80
GL t
GC t
6V
2V
4.5 V
= 25°C
MAX
SN54HC137
MIN
MAX
120
24
16
14
SN74HC137
MIN
100
MAX
20
20
17
75
115
95
15
23
19
6V
13
16
2V
4.5 V
5
5
20
5
6V
5
5
5
5
5
5
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
.
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
vcc
2V
tpd
tpd
tpd
tpd
tt
Cpd
A, B, C
(32
G1
Gt
V
y
V
y
V
TA = 25°C
MIN
TVP MAX
82
190
SN54HC137
MIN
SN74HC137
MAX
MIN
MAX
285
240
4.5 V
23
38
57
48
6V
2V
4.5 V
19
59
17
32
145
41
180
6V
14
29
25
48
220
44
2V
4.5 V
61
145
37
220
17
29
44
6V
14
25
37
2V
4.5 V
77
190
38
285
57
22
36
31
CJ
>
w
ns
c
en
2
ns
o
ns
CJ
J:
240
48
41
6V
19
32
48
2V
38
75
110
4.5 V
8
15
22
95
19
6V
6
13
19
16
Power dissipation capacitance
en
w
UNIT
180
36
31
85 pF typ
II
ns
ns
,I
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
-II}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-77
EJ
J:
n
S.
o
en
c
m
<
n
m
en
3-78
TYPES SN54HCT137, SN74HCT137
3·L1NE TO B·L1NE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
HIGH·SPEED
CMOS LOGIC
02804. MARCH 1984
•
Inputs are TTL·Voltage Compatible
•
Combines Decoder and 3·Bit Address Latch
•
Incorporates 2 Output Enables to Simplify
Cascading
•
•
SN54HCT137 .•• J PACKAGE
SN74HCT137 ••• J OR N PACKAGE
(TOP VIEW)
A
B
C
GL
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
VCC
YO
Y1
Y2
Y3
Y4
Y5
Y6
<32
G1
Y7
Dependable Texas Instruments Quality and
Reliability
GND
~escription
SN54HCT137 •.• FH OR FK PACKAGE
SN74HCT137 ••• FH OR FN PACKAGE
(TOP VIEW)
The 'HCT137 is a three-line to eight-line
decoder/demultiplexer with latches on the three
address inputs. When the latch-enable input (GI)
is
low,
the
'HCT137
acts
as
a
decoder/demultiplexer. When GL goes from low
to high, the address present at the select inputs
(A, S, and C) is stored in the latches. Further
address changes are ignored as long as GL
remains high. The output enable controls, G1
and (32, control the outputs independently of the
select or latch-enable inputs. All of the outputs
are forced high if G1 is low or G2 is high. The
'HCT137 is ideally suited for implementing
glitch-free decoders in strobed (stored-address)
applications in bus-oriented systems.
u
u uo
II
co«z»
c
Y1
Y2
NC
Y3
GI
NC
<32
G1
en
w
(.)
>
W
c
..... OUCOLO
>-zz>->-'
en
(!)
o
NC-No internal connection
~
The SN54HCT137 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCT137 is
characterized for operation from - 40°C to
85°C.
(.)
J:
logic symbols (alternatives)
x/v
A (1)
B (2)
A
2
C (3)
B
2
C
4
EN
G1
5
(;2
6
V6
7
V7
Pin numbers shown are for J and N packages.
Copyright © 1984. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-79
TYPES SN54HCT137 SN74HCT137
3·LlNE TO B·LlNE DECODERS/DEMULJIPLEXERS
WITH ADDRESS LATCHES
FUNCTION TABLE
INPUTS
OUTPUTS
SELECT
ENABLE
GL G1
G2
C
B
A
YO
Y1
V2
V3
V4
V5
V6
X
H
X
X
H
H
V7
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
L
L
L
H
H
H
H
H
H
L
H
H
H
X
X
X
H
L
H
X
X
H
H
H
H
H
L
H
L
L
H
L
H
H
L
H
H
H
H
L
H
L
L
H
H
H
H
L
H
H
H
L
H
L
L
L
H
H
H
L
L
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
L
H
H
L
L
H
H
H
H
L
H
H
H
L
X
X
X
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
Output corresponding to stored
X
X
H
L
H
address. L; all others. H
illogiC diagram (positive logic 1
:t:
n
o
S
en
(151
J:)---
C
YO
m
~
(141
1)---Y1
n
m
en
1>-_(.;...1_31_ Y2
(121
D---Y3
(111
Y4
(101
D---V5
(91
Y6
V7
Pin numbers shown are for J and N packages.
3·80
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HCT137. SN74HCT137
3·L1NE TO B·L1NE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
absolute maximum ratings, recommended operating conditions, and electrical characteristics
See Table VIII, page 2-15 ..
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
4.5
5.5
4.5
5.5
4.5
5.5
GI low
tw
Pulse duration,
tsu
Setup time, A, B, and C before
th
Hold time, A, B, and C after
GI t
GL t
V
V
V
V
V
V
TA = 25°C
MIN
TYP MAX
26
SN54HCT137
MAX
23
15
14
MIN
39
35
23
21
5
5
5
5
SN74HCT137
MIN
MAX
33
30
19
17
5
5
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A, B,C
Y
tpd
02
Y
tpd
G1
y
tpd
GL
Y
tt
Any
VCC
4.5
5.5
4.5
5.5
4.5
V
V
V
V
V
5.5
4.5
5.5
4.5
5.5
V
V
V
V
V
TA = 25°C
MIN TYP MAX
25
38
20
34
20
29
17
25
20
29
25
17
32
25
12
11
SN54HCT137
MAX
57
51
44
40
44
40
MIN
42
36
15
14
Power dissipation capacitance
63
57
22
20
SN74HCT137
MAX
48
43
36
32
MIN
36
32
52
47
19
17
85 pF typ
UNIT
ns
II
(IJ
ns
W
(J
ns
>
W
ns
C
(IJ
ns
o
:E
(J
J:
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-81
:J:
o
3:
oen
c
m
<
o
m
en
3-82
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC13B. SN74HC13B
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
02684. DECEMBER 1982-REVISED MARCH 1984
•
Designed Specifically for High·Speed
Memory Decoders and Data Transmission
Systems
•
Incorporates 3 Enable Inputs to Simplify
Cascading and/or Data Reception
•
•
SN54HC138 ... J PACKAGE
SN74HC138 ... J OR N PACKAGE
(TOP VIEW)
Package Options Include Both Plastic and
Ceramic Chip Carriers In Addition to Plastic
and Ceramic DIPs
Dependable Texas Instruments Quality and
Reliability
Vcc
A
1 V16J
B
2
15
YO
C
3
14
Y1
G2A
G2B
4
13
Y2
5
12
Y3
G1
6
Y4
Y7
7
GND
8
11
10
9
Y5
Y6
description
SN54HC138 ... FH OR FK PACKAGE
SN74HC138 ... FH OR FN PACKAGE
(TOP VIEW)
The 'HC138 circuit is designed to be used in
high-performance memory-decoding or datarouting applications requiring very short
propagation delay times. In high-performance
memory systems this decoder can be used
to minimize the effects of system decoding.
When employed with high-speed memories
utilizing a fast enable circuit, the delay times of
this decoder and the enable time of the memory
are usually less than the typical access time of
the memory. This means that the effective
system delay introduced by the decoder is
negligible.
U
U
Uo
II
al>-
Y1
C
G2A
NC
G2B
Y2
NC
G1
Y4
en
w
(J
Y3
>
W
c
en
f'OUCOLO
>-Zz>->-
The conditions at the binary select inputs at the
three enable inputs ,select one of eight input
lines. Two active-low and one active-high enable
inputs reduce the need for external gates or
inverters when expanding. A 24-line decoder can
be implemented without external inverters and
a 32-line decoder requires only one inverter. An
enable input can be used as a data input for
de multiplexing applications.
o
(!)
~
NC-No internal connection
(J
J:
The SN54HC138 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC138 is
characterized for operation from - 40°C to
85°C.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright © 1982. Texas Instruments Incorporated
3-83
TV-PES SN54HC13B, SN74HC13B
3·L1NE TO B·L1NE DECODERS/DEMULTIPLEXERS
logic symbols (alternatives)
BIN/OCT
A (1)
B (2)
C (3)
EN
logic diagram (positive logic)
:J:
(")
S
oen
c
<
m
(")
m
en
Pin numbers shown are for J and N packages.
3-84
TEXAS •
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC13B, SN74HC13B
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
FUNCTION TABLE
G1
X
X
L
H
H
H
H
H
H
H
ENABLE
INPUTS
G2A G2B
X
H
H
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
SELECT
INPUTS
A
B
C
X
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
L
H
L
H
L
H
L
L
L
H
H
L
L
H
H
H
OUTPUTS
VO
H
H
H
L
H
H
H
H
H
V1
H
H
H
H
H
L
H
H
H
H
H
H
H
V3
H
V2
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
V4
H
H
H
H
H
H
H
L
H
H
H
V5
H
H
H
H
H
H
H
H
L
H
H
V6
H
H
H
H
H
H
H
H
H
L
H
V7
H
H
H
H
H
H
H
H
H
H
L
II
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A. B. or C
Any V
tpd
Enable
Any V
tt
Any
vcc
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TVP MAX
67
180
18
15
66
18
15
38
8
6
36
31
155
31
26
75
15
13
SN54HC138
MIN
MAX
270
54
46
Power dissipation capacitance
235
47
40
110
22
19
SN74HC138
MIN
MAX
225
45
38
195
39
33
95
19
16
UNIT
en
w
(.)
>
W
c
ns
ns
en
o
:!
(.)
::I:
ns
85 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS
-111
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-85
lEI
::I:
n
S
o
CJ)
C
m
<
nm
CJ)
3-86
HIGH-SPEED
CMOS LOGIC
TYPES SN54HCT138, SN74HCT138
3-LlNE TO 8-LlNE DECODERS/DEMULTIPLEXERS
D2804, MARCH 1984
•
Inputs Are TTL-Voltage Compatible
•
Designed Specifically for High-Speed
memory Decoders and Data Transmission
Systems
•
SN54HCT138 ..• J PACKAGE
SN74HCT138 ... J OR N PACKAGE
(TOP VIEW)
A
8
Incorporates 3 Enable Inputs to Simplify
Cascading and/or Data Reception
VCC
YO
Y1
Y2
Y3
Y4
Y5
Y6
C
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas instruments Quality and
Reliability
G2A
G28
G1
Y7
GND
SN54HCT138 ... FH OR FK PACKAGE
SN74HCT138 ... FH OR FN PACKAGE
description
(TOP VIEW)
The 'HCT138 circuit is designed to be used in
high-performance memory-decoding or datarouting applications requiring very short
propagation delay times. In high-performance
memory systems, this decoder can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a
fast enable circuit, the delay times of this
decoder and the enable time of the memory are
usually less than typical access time of the
memory. This means that the effective system
delay introduced by the decoder is negligible.
U
U
Uo
II
0)<(2)>3
2
1 2019
Y1
Y2
NC
Y3
Y4
C
G2A
NC
G28
G1
9
en
w
CJ
>
w
c
en
10 11 1213
"ClUtO!!)
>-22>->-
o
c:J
The conditions at the binary select inputs and the
three enable inputs select one of eight input
lines. Two active-low and one active-high enable
inputs reduce the need for external gates or
inverters when expanding. A 24-line decoder can
be implemented without external inverters and
a 32-line decoder requires only one inverter. An
enable input can be used as a data input for
demultiplexing applications.
~
NC - No internal connection
CJ
::I:
The SN54HCT138 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCT138 is
characterized for operation from - 40°C to
85°C.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS, TEXAS 75265
Copyright
© 1984, Texas Instruments Incorporated
3-87
TYPES SN54HCT13B, SN74HCT13B
3·L1NE TO B·L1NE DECODERS/DEMULTIPLEXERS
logic symbols (alternatives)
BIN/OCT
logic diagram (positive logic)
II
J:
n
S
oen
o
m
<
n
m
en
Pin numbers shown are for J and N packages.
3·88
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HCT13B, SN74HCT13B
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
FUNCTION TABLE
ENABLE
SELECT
INPUTS
G1
OUTPUTS
INPUTS
G2A G2B
C
B
A
VO
V1
V2
V3
V4
V5
V6
X
H
X
X
X
X
H
H
H
H
H
H
H
V7
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
H
X
X
X
X
L
X
X
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
L
L
L
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
II
maximum ratings, recommended operating conditions, and electrical characteristics
See Table VIII. page 2-15.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 60 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A. B. or C
Any Y
tpd
Enable
Any Y
tt
Any
vcc'
TA "" 25°C
MIN
TVP MAX
SN54HCT138
MIN
MAX
SN74HCT138
,MAX
MIN
4.5 V
23
36
54
45
5.5 V
17
32
49
34
4.5 V
22
33
50
42
5.5 V
18
30
45
38
19
17
4.5 V
11
15
22
5.5 V
11
14
20
UNIT
ns
ns
ns
(Jl
W
(.)
>
W
C
(Jl
o
:?!'
(.)
J:
85 pF typ
Power dissipation capacitance
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-89
11
:t:
o
3:
oen
c
m
<
(5
m
en
3-90
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC139, SN74HC139
DUAL 2·LlNE TO 4·LlNE DECODERS/DEMULTIPLEXERS
02684, DECEM8ER 1982-REVISED MARCH 1984
• Designed Specifically for High·Speed Memory
Decoders and Data Transmission Systems
SN54HC139 ... J PACKAGE
SN74HC139 ... J OR N PACKAGE
(TOPVIEWI
• Incorporates 2 Enable Inputs to Simplify Cascading
and/ or Data Reception
113
1A
18
lYO
1Y1
1Y2
1Y3
GND
• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs
• Dependable Texas Instruments Quality and Reliability
description
The 'HC139 circuit is designed to be used in high-performance
memory-decoding or data-routing applications requiring very
short propagation delay times. In high-performance memory
systems, this decoder can be used to minimize the effects of
system decoding. When employed with high-speed memories
utilizing a fast-enable circuit, the delay times of this decoder and
the enable time of the memory are usually less than the typical
access time of the memory. This means that the effective
system delay introduced by the decoder is negligible.
The 'HC139 is comprised of two individual two-line to four-line
decoders in a single package. The active-low e,nable input can
be used as a data line in demultiplexing applications. These
decoders/demultiplexers feature fully buffered inputs, each of
which represents only one normalized load to its driving circuit.
The SN54HC139 is characterized for operation over the full .
military temperature range of -55°C to 125°C. The SN74HC139
is characterized for operation from -40°C to 85°C.
VCC
213
2A
28
2YO
2Y1
2Y2
2Y3
II
SN54HC139 ... FH OR FK PACKAGE
SN74HC139 ... FH OR FN PACKAGE
(TOPVIEWI
UJ
w
CJ
U
UI(!)
.-Z>N
<( I(!) U
>
w
3 2 1 2019
18
1YO
2A
28
NC
NC
1Y1
lY2
2YO
2Yl
C
UJ
o
~
CJ
J:
9 10111213
logic symbols (alternatives)
NC-No internal connection
lA (21
lYO
(31
lVl
1V2
Pin numbers shown are for J and N packages.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-91
TYPES SN54HC139, SN74HC139
DUAL 2·LlNE TO 4·LlNE DECODERS/DEMULTIPLEXERS
logic diagram (positive logic)
ENABLE 16 (1)
DATA
OUTPUTS
ENABLE 26 (15)
lEI
J:
Pin numbers shown are for J and N packages.
n
s:
o
FUNCTION TABLE
INPUTS
ENABLE SELECT
B A
6
H
X X
L L
L
rn
cm
<
n
m
rn
H
OUTPUTS
YO Y1 Y2 Y3
H H H H
L H H H
H L H H
L
L
L
H
L
H
H
L
H
L
H
H
H
H
H
L
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
liN PUT)
TO
IOUTPUT)
tpd
A or B
Y
tpd
tt
G
y
Y
vCC
TA = 25°C
MIN TYP MAX
SN54HC139
MAX
MIN
MAX
2V
4.5 V
47
175
35
255
51
220
14
6V
12
30
44
38
2V
4.5 V
39
11
175
35
255
51
220
44
6V
10
30
44
38
2V
4.5 V
38
75
110
8
15
22
95
19
6V
6
13
19
16
Power dissipation capacitance per decoder
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
3-92
SN74HC139
MIN
TEXAS . .
INSTRUMENTS
POST OFFice BOX 225012 • OALLAS. TeXAS 75265
44
UNIT
ns
ns
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC147, SN54HC14B
SN74HC147, SN74HC14B
10·LlNE TO 4·LlNE AND B·LlNE TO 3·LlNE PRIORITY ENCODERS
02844, MARCH 1984
SN54HC147 ... J PACKAGE
SN74HC147 ... J OR N PACKAGE
(TOP VIEW)
'HC147
•
Encodes 10-line Decimal to 4-line BCD
•
Applications Include:
Keyboard Encoding
Range Selection
4
5
6
7
8
C
8
GND
'HC148
•
Encodes 8 Data lines to 3-line Binary
(Octal)
•
Applications Include:
N-Bit Encoding
Code Converters and Generators
•
•
1 U16
15
14
13
12
VCC
NC
D
3
2
11
1
10
9
9
A
SN54HC147 ... FH OR FK PACKAGE
SN74HC147 ... FH OR FN PACKAGE
(TOP VIEW)
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
U
U
UU
Ln~Z>Z
II
Dependable Texas Instruments Quality and
Reliability
NC
NC
2
8
C
description
These encoders feature priority decoding of the
inputs to ensure that only the highest-order data
line is encoded. The 'HC147 encodes nine data
lines to four-line (8-4-2-1) BCD. The implied
decimal zero condition requires no input
condition as zero is encoded when all nine data
lines are at a high logic level. The 'HC148
encodes eight data lines to three-line (4-2-1)
binary (octal). Cascading circuitry (enable input
EI and enable output EO) has been provided to
allow octal expansion without the need for
external circuitry. For all types, data inputs and
outputs are active at the low logic level.
en
w
CJ
>
w
CDOU<{Ol
zz
c
l!]
en
SN54HC148 ... J PACKAGE
SN74HC148 ••. J OR K PACKAGE
(TOP VIEW)
4
5
6
7
EI
A2
Al
GND
The SN54HC147 and SN54HC148 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74HC147 and SN74HC148 are characterized
for operation from - 40°C to 85 DC.
o
~
CJ
VCC
EO
GS
3
::I:
2
1
0
AO
SN54HC148 .•. FH OR FK PACKAGE
SN74HC148 ... FH OR FN PACKAGE
(TOP VIEW)
U
U
Uo
Ln~Z'>LU
3
6
7
NC
EI
A2
2
4
5
GS
6
NC
3
-ouaa
<{zz<{
l!]
NC-No internal connection
Copyright © 1984, Texas Instruments Incorporated
TEXAS
.J.!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-93
TYPES SN54HC147, SN54HC14B
SN74HC147, SN74HC14B
10·LlNE TO 4·LlNE AND B·LlNE TO 3·LlNE PRIORITY ENCODERS
'HC148
FUNCTION TABLE
'HC147
FUNCTION TABLE
INPUTS
1
2
H
H
H
H
H
X X
X X
X X
X X
X X
X X
X X
X L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
H
H
H
L
1I109;C
H
3
4
5
X
X
L
H
H
H
H
INPUTS
OUTPUTS
B
A
EI
H
H
H
H
H
H
L
H
L
L
6
H
7
8
9
0
H
H
H
H
X
X
X
X
X
X
L
L
L
L
H
H
H
L
H
L
L
H
H
H
H
C
6
7
X
5
X
X
HH
H
H
X
X
X
X
X
L
H
H
X
L
H
H
H
H
H
H
H
X
H
L
H
H
H
H
H
H
H
1
2
H
0
X
X
X
3
X
L
H
H
H
H
L
X
L
H
L
L
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
L
L
H
H
H
H
H
H
H
H
H
H.
H
H
H
H
H
L
L
H
L
L
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
L
L
H
H
H
L
H
H
H
L
H
L
H
H
H
H
H
H
H
L
L
X
X
X
X
X
X
L
H
X
L
4
svmbols
J:
'HC148
HPRI/BCD
HPRI/BIN
(")
0
2
2
4
m
3
5
S
(")
4
6
5
7
m
rn
(10)
(11)
3
C
6
8
7
9
(12)
(13)
(1)
(2)
(3)
(4)
0/Z10
10
1/Z11
11
21Z12
12
3/Z13
13
4/Z14
14
5/Z15
15
6/Z16
16
7/Z17
17
V18
EI
(5)
Pin numbers shown are for J and N packages.
3-94
L
L
L
L
H
L
L
L
H
H
L
L
L
H
H
L
L
H
H
L
H
H
H
L
L
H
L
L
H
H
H
L
L
H
H
H
H
L
H
H = high logic level, L= low logic level, X = ir~elevant
'HC147
S
0
rn
OUTPUTS
A2 A1 AO GS EO
H
H
H
H
H
H
H
L
H
H
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
ENa
H
TYPES SN54HC147, SN54HC14B
SN74HC147, SN74HC14B
10·LlNE TO 4·LlNE AND B·LlNE TO 3·LlNE PRIORITY ENCODERS
logic diagrams
'HC148
'HC147-
II
CJ)
w
U
>
w
C
CJ)
o
maximum ratings, recommended operating conditions, and electrical characteristics
2
See Table IV, page 2-10.
u
'HC147 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
(OUTPUT)
tpd
Any
Any
tt
TO
Any
VCC
TA = 25°C
TYP MAX
MIN
SN54HC147
MIN
SN74HC147
MAX
MIN
MAX
2V
75
190
285
240
4.5 V
25
38
57
48
6V
21
32
48
41
95
2V
28
75
110
4.5 V
8
15
22
19
6V
6
13
19
16
:I:
UNIT
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
-I!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-95
TYPES SN54HC147. SN54HC14B
SN74HC147. SN74HC14B
10·LlNE TO 4·LlNE AND B·LlNE TO 3·LlNE PRIORITY ENCODERS
'HC148 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
1-7
AO, A1,
or A2
tpd
0-7
EO
tpd
0-7
GS
tpd
EI
AO,A1
or A2
tpd
EI
GS
:I:
tpd
EI
EO
S
O.
en
tt
II
(')
c
m
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
69 180
23
36
21
31
60 150
20
30
17
26
75 190
25
38
21
32
78 195
26
39
33'
22
57 145
29
19
25
16
66 165
22
33
28
19
28
75
15
8
13
6
SN54HC148
MIN
MAX
270
54
46
225
45
38
285
57
48
295
59
50
220
44
38
250
50
43
110
22
19
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
<
(')
m
en
3-96
TEXAS
-Ii}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SN74HC148
UNIT
MIN
MAX
225
ns
45
38
190
38
ns
33
240
ns
48
41
245
ns
49
42
180
36
ns
31
205
ns
41
35
95
ns
19
16
TYPES SN54HC147, SN54HC148
SN74HC147, SN74HC148
10·L1NE TO 4·LlNE AND 8·LlNE TO 3·L1NE PRIORITY ENCODERS
TYPICAL APPLICATION DATA
~
16-LlNE DATA
(ACTIVE
______________
.AW
__" LOW)
__________
~
I
o
\
1
2
3
4
5
6
7
8
8
9
10 11 12 13 14 15
ENABLE
(ACTIVE LOW)
'HC148
'HC148
GS
--,
o
_____ JI
3
2
II
I
'HC08
(J)
PRIORITY FLAG
(ACTIVE LOW)
..----~v~------·
W
CJ
>
w
ENCODED DATA (ACTIVE LOW)
~
______________ -______________
16-LlNE DATA (ACTIVE LOW)
.A~
7
8
8
9
C
~
(J)
\
10 11 12 13 14 15
o
ENABLE
(ACTIVE LOW)
2
CJ
J:
'HC148
'HC148
EO
AO
A1
AD
A1
'HCOO
..
o
2
3
----~v~-----
PRIORITY FLAG
(ACTIVE HIGH)
ENCODED DATA (ACTIVE HIGH)
PRIORITY ENCODER FOR 16 BITS
Since the 'HC 147 and 'HC 148 are combinational logic circuits, wrong addresses can appear during input
transients. Moreover, for the 'HC148, a change from high to low at input EI can cause a transient low
on the GS output when all inputs are high. This must be considered when strobing the outputs.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-97
lEI
J:
o
s:
o
en
c
m
<
o
m
en
3-98
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC151, SN74HC151
B·L1NE TO 1·L1NE DATA SELECTORS/MULTIPLEXERS
02684. DECEM8ER 1982-REVISED MARCH 1984
•
8-Line to 1-Line Multiplexers Can
Perform As:
Boolean Function Generators
Parallel-to-Serial Converters
Data Source Selectors
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality' and
Reliability
SN54HC161 ... J PACKAGE
SN74HC161 ... J OR N PACKAGE
(TOPVIEWI
Vcc
02
01
04
05
06
07
A
B
C
description
These monolithic data selectors/multiplexers
provide full binary decoding to select one of eight
data sources. The strobe input (G) must be at
a low logic level to enable the inputs. A high level
at the strobe terminal forces the W output high
and the Y output low.
SN54HC161 ... FH OR FK PACKAGE
SN74HC161 ... FH OR FN PACKAGE
(TOPVIEWI
N cry U
II
U
U<:t
ooz>o
The SN54HC151 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC151 is
characterized for operation from -40°C to
85°C.
01
00
4
NC
6
NC
7
07
8
A
Y
W
FUNCTION TABLE
en
w
05
06
5
(J
>
W
C
en
() 10 11 1213
INPUTS
SELECT
C
X
L
L
L
L
H
H
H
H
OUTPUTS
STROBE
A
G
H
L
X
L
H
L
H
L
H
H
H
L
L
L
L
L
L
L
L
H
L
B
X
L
L
H
H
L
Ie!)
y
W
L
DO
01
02
03
H
=
high level, L
=
low level, X
=
2
(J
NC-No internal connection
::I:
logic symbols
53
04
04
05
05
06
D6
07
07
MUX~
G
EN
A
:}G~
B
C
H
o
U U al
zz
e!)
50
Di
D2
0
DO
irrelevant
0
y
01
DO, 01 ... 07 = the level of the 0 respective input
02
2
03
3
4
04
5
05
06
07
W
1131
(12)
6
Pin numbers shown are for J and N packages
Copyrighl ©1982 by Texas Instrumenls Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265
3-99
TYPES SN54HC151, SN74HC151
B·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
logic diagram (positive logic)
G (71
00 ~(4;,,;..1__---1
>---+-1
_01(31
IIIiiII 02~(2=1
::z::
()
__---1
>-______________~
03~(1~1__~>-____________________~
S
o(J)
~
05~(1_4~1__~~________________________________-+~
:$
()
m
(J)
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
3-100
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC151, SN74HC151
B·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL ... 50 pF (see Note 1)
PARAMETER
tpd
tpd
tpd
FROM
(INPUT)
A, B, or C
Any D
G
TO
(OUTPUT)
YorW
YorW
YorW
tt
vCC
TA = 25°C
MIN
TYP MAX
2V
94
250
4.5 V
6V
2V
30
25
74
4.5 V
23
39
6V
2V
20
33
127
25
SN54HC151
MIN
SN74HC151
MAX
50
73
62
283
63
54
244
ns
43
195
57
4B
49
ns
185
159
37
32
28
6V
13
22
32
2V
4.5 V
22
75
15
110
22
19
Power dissipation capacitance
UNIT
312
49
15
6V
MAX
360
4.5 V
9
8
MIN
13
41
95
19
ns
ns
16
No load, TA = 25°C
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL ... 150 pF (see Note 1)
II
en
w
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
440
YorW
33
350
70
525
A, B, or C
2V
4.5 V
107
tpd
105
ns
30
90
59
275
89
415
YorW
6V
2V
4.5 V
88
76
345
29
51
83
69
ns
>
w
c
en
o
6V
25
72
59
2V
4.5 V
67
47
205
310
255
21
41
62
51
ns
CJ
J:
6V
2V
18
51
35
210
53
315
43
265
4.5 V
16
42
63
53
6V
14
36
53
45
tpd
tpd
. tt
Any D
G
YorW
VCC
TA = 25°C
MIN
TYP MAX
SN54HC151
MIN
SN74HC151
MAX
MIN
MAX
UNIT
CJ
:E
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
-II}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TeXAS 75265
3-101
II
J:
n
S
o
en
c
m
~
n
m
en
3-102
HIGH-SPEED
CMOS LOGIC
TYPES SN54HC152, SN74HC152
B-L1NE TO l-L1NE DATA SELECTORS/MULTIPLEXERS
02684. DECEMBER 1982- REVISED MARCH 1984
SN54HC152 ... J PACKAGE
SN74HC152 ... J OR N PACKAGE
(TOP VIEW)
o
Selects One-of-Eight Data Sources
•
Performs Parallel-to-Serial Conversion
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
e
04
03
02
01
00
Dependable Texas Instruments Quality
and Reliability
description
These monolithic data selectors/multiplexers contain full on-chip binary decoding to select the desired
one-of-eight data sources.
B
GNO
C
o
~
0
u
Z
u
U LO
0
>
02
06
NC
NC
01
07
NC
NC
en
w
DO
OUTPUT
CJ
W
L
L
L
DO
L
L
L
L
H
H
H
L
52
H
H
H
H
L
L
L
H
H
H
L
55
56
H
57
H
A
W
(Y)
FUNCTION TABLE
INPUTS
C B A
05
06
07
SN54HC152 ... FH OR FK PACKAGE
SN74HC152 ... FH OR FN PACKAGE
(TOP VIEW)
The SN54HC152 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC152 is characterized for operation from -40°C to 85°C.
SElECT
VCC
>
w
s~~UaJ
c
o
<:J
i51
NC-No internal connection
OJ
54
en·
2
logic symbol
A
B
c
DO
01
02
03
04
05
06
MUX
(10)
(9)
(8)
(5)
(4)
(3)
(2)
(1)
CJ
::I:
t>
:}G7
0
(6)
2
W
3
(13)
(12)
(11)
07
Pin numbers shown are for J and N packages.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS
.Jtj}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-103
TYPES SN54HC152, SN74HC152
B·L1NE TO 1·L1NE DATA SELECTORS/MULTIPLEXERS
logic diagram (positive logic)
DO
II
01
02
::I:
n
S
0
en
03
04
C
m
<
nm
en
05
06
07
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical' characteristics
See Table III, page 2-8.
3-104
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC152, SN74HC152
B·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A B, or C
W
tpd
Any 0
W
vCC
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
50
170
18
34
16
29
130
38
14
26
12
22
2Y
W
tt
20
8
6
4.5 V
6V
SN54HC152
MIN
MAX
255
51
44
195
39
33
60
12
10
90
18
15
Power dissipation capacitance
SN74HC152
MIN
MAX
213
43
36
163
33
28
75
15
13
UNIT
ns
ns
ns
70 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL .. 150 pF (see Note 1)
PARAMETER
tpd
tpd
tt
FROM
(INPUT)
A, B, or C
Any 0
TO
(OUTPUT)
W
W
W
VCC
TA = 25°C
MIN TYP MAX
2V
4.5 V
63
22
19
52
1B
16
45
17
13
6V
2V
4.5 V
6V
2V
4.5 V
6V
SN54HC152
MIN
MAX
225
51
44
215
43
37
210
42
36
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS . .
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TexAS 75265
385
77
66
325
65
55
315
63
53
SN74HC152
MIN
MAX
318
64
55
268
54
47
265
53
45
UNIT
ns
ns
ns
II
(J)
W
(.)
5>
w
c
(J)
o
~
(.)
J:
3-105
::I:
o
s:
o
en
c
<
m
o
m
en
3-106
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC153, SN14HC153
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
02684. DECEMBER 1982-REVISED MARCH 1984
SN54HC153 ... J PACKAGE
SN74HC163 ... J OR N PACKAGE
(TOPVIEWI
• Permits Multiplexing from N Lines to 1 Line
• Performs Parallel-to-Serial Conversion
• Strobe (Enable) Line Provided for Cascading (N
lines to n lines)
1G
B
1C3
1C2
1Cl
lCO
1Y
GND
• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic
DIPs
• Dependable Texas Instruments Quality and
Reliability
description
It!) U
STROBE
U
UiN
The SN54HC153 is characterized for operation over the
full military temperature range of -55°C to 125°C. The
SN74HC153 is characterized for operation from -40°C to
85°C.
INPUTS
A
SN54HC163 ... FH OR FK PACKAGE
SN74HC153 ... FH OR FN PACKAGE
(TOP VIEW)
Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data
selection to the AND-OR gates. Separate strobe inputs (3)
are provided for each of the two four-line sections.
SELECT
VCC
2(3
en
w
2C3
NC
2C2
2Cl
(.)
>
W
OUTPUT
C
>-OU>-O
B
A
CO
Cl
C2
C3
G
V
X
X
X
X
X
X
H
L
L
L
L
X
X
X
L
L
L
L
H
X
X
X
L
H
L
H
X
L
X
X
L
L
L
H
X
H
X
X
L
H
H
L
X
L
X
L
L
H
H
L
X
X
X
H
X
L
H
H
X
X
X
L
L
L
H
H
X
X
X
H
L
H
"'-ZZNU
t!)
N
en
o
:E
NC-No internal connection
(.)
::J:
logic symbol
Select inputs A and B are common to both sections.
(1)
1Y
(9) 2Y
Pin numbers shown are for J and N packages.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-107
TYPES SN54HC153, SN74HC153
DUAL 4·LlNE TO 1·tINE DATA SELECTORS/MULTIPLEXERS
logic diagram (positive logic)
A
B~----I-----I------t
11
J:
n
S
o(J)
C
m
<
n
m
(J)
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
3-108
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC153, SN74HC153
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
tpd
tpd
Data
(Any C)
Y
G
Y
Y
tt
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
90
150
21
30
17
26
73
126
17
28
14
23
38
95
11
19
9
16
20
60
8
12
6
10
SN54HC153
MAX
225
45
MIN
38
189
42
35
150
28
24
90
18
15
SN74HC153
MIN
MAX
190
38
32
158
35
29
125
24
20
75
15
13
UNIT
ns
ns
ns
ns
I 40pFtyp I
Power dissipation capacitance per multiplexer
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
tpd
Data
(Any C)
Y
tpd
G
Y
tt
Y
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
105
235
27
47
21
41
93
220
23
44
19
38
60
185
17
37
14
32
45
210
17
42
13
36
SN54HC153
MAX
MIN
355
71
60
335
67
57
280
56
48
315
63
53
SN74HC153
MIN
MAX
295
59
. 51
UNIT
ns
274
55
48
230
46
40
265
53
45
ns
II
en
w
o
:>w
c
en
o
:!
o
J:
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS . "
INSTRUMENTS .
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-109
J:
o
s:
oen
c
m
<
o
m
en
3-110
TYPES SN54HC157, SN54HC158, SN74HC157, SN74HC158
QUADRUPLE 2·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC167, SN64HC168 ... J PACKAGE
SN74HC167, SN74HC168 ..• J OR N PACKAGE
ITOPVIEWI
AlB
1A
1B
1Y
2A
2B
2Y
description
These monolithic data selectors/multiplexers
contain inverters and drivers to supply full data
selection to the four output gates. A separate
strobe input (<3) is provided. A 4-bit word is
selected from one of two sources and is routed
to the four outputs. The 'HC157 presents true
data whereas the 'HC158 presents inverted
data.
SN64HC167, SN64HC168 ..• FH OR FK PACKAGE
SN74HC167, SN74HC168 ... FH OR FN PACKAGE
ITOPVIEWI
FUNCTION TABLE
~ I~
~
....
U
Z
~
II
>I(!)
4A
4B
NC
4Y
3A
1B
1Y
NC
2A
2B
en
w
(J
:>w
OUTPUT Y
DATA
G
SELECT
AlB
A
B
H
X
X
X
L
H
L"
L
L
X
L
H
L
L
H
X
H
L
L
H
X
L
L
H
L
H
X
H
H
L
STROBE
4A
4B
4Y
3A
3B
3Y
GND
The SN54HC157 and SN54HC158 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74HC157 and SN74HC158 are characterized
for operation from - 40°C to 85 °C.
INPUTS
VCC
G
'HC167"
c
en
>-ou>-m
(!)
'HC168
NZZMM
o
:2E
NC-No internal connection
(J
J:
logic symbols
'HC168
'HC167
Pin numbers shown are for J and N packages.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-111
TYPES SN54HC157, SN54HC158, SN74HC157, SN74HC158
QUADRUPLE 2·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
logic diagrams (positive logic)
'HC157
1A
1B
2A
2B
3A
3B
II
(2)
(3)
(5)
(6)
111 )
(10)
4A (14)
4B
:t:
o
3:
STROBE G
SELECT AlB
o
en
cm
<
(13)
(15)
(1 )
'HC158
o
1A--------------------~~
en
1B (3)
(2)
m
2A (5)
2B (6)
3A (11)
3B. (10)
4A (14)
4B (13)
STROBE
G _(_15_)--_+_-01
SELECT AlB -:-11~)- . . . . - - t - - G
Pin numbers shown are for J and N packages.
3-112
TEXAS . .
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS. TeXAS 75265
TYPES SN54HC157, SN54HC158, SN74HC157, SN74HC158
QUADRUPLE 2·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
tpd
AlB
y
tpd
IT
y
MIN
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Y
tt
TA = 25°C
vCC
TVP MAX
63 125
13
25
11
21
67 125
18
25
14
21
59 115
16
23
13
20
28
60
8
12
6
10
Power dissipation capacitance
SN54HC157
SN54HC158
MIN
MAX
190
38
32
190
38
32
170
34
29
90
18
15
No load,
TA
= 25°C
SN74HC157
SN74HC158
UNIT
MIN
MAX
160
32
ns
27
160
31
ns
27
145
29
ns
25
75
15
ns
13
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
y
tpd
AlB
y
tpd
G
y
tt
Y
TA = 25°C
vCC
MIN
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TVP MAX
81
190
23
38
18
33
81 210
23
42
18
36
91
190
24
38
18
33
45 210
17
42
13
36
SN54HC157
SN54HC158
MIN
MAX
290
58
49
320
64
54
290
58
49
315
63
53
CJ)
W
(.)
40 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
II
>
W
C
CJ)
SN74HC157
SN74HC15B
UNIT
MIN
MAX
235
47
ns
41
260
52
ns
45
235
47
ns
41
265
53
ns
45
o
~
(.)
J:
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
, TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-113
II
J:
n
!:
oen
c
S
m
n
m
en
3-114
TYPES SN54HC160 THRU SN54HC163
SN74HC160 THRU SN74HC163
SYNCHRONOUS 4·BIT DECADE AND BINARY COUNTERS
HIGH·SPEED
CMOS LOGIC
02684, DECEMBER 1982-REVISED MARCH 1984
•
Internal Look Ahead for Fast Counting
•
Carry Output for N·Bit Cascading
•
Synchronous Counting
•
Synchronously Programmable
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
SN54HC' ... J PACKAGE
SN74HC' ... J OR N PACKAGE
(TOP VIEW)
ClR
ClK
A
VCC
RCO
OA
Os
Oc
OD
ENT
lOAD
S
C
D
ENP
GND
Dependable Texas Instruments Quality and
Reliability
description
SN54HC' ... FH OR FK PACKAGE
SN74HC' ... FH OR FN PACKAGE
These synchronous, presettable counters feature
an internal carry look-ahead for application in
high-speed counting designs. The 'HC 160 and
'HC162 are decade counters, and the 'HC161
and 'HC 163 are 4-bit binary counters.
Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the
outputs change coincident with each other when
so instructed by the count-enable inputs and
internal gating. This mode of operation
eliminates the output counting spikes that are
normally associated with synchronous (ripple
clock) counters. A buffered clock input triggers
the four flip-flops on the rising (positive-going)
edge of the clock input waveform.
(TOP VIEW)
~ Ia:
u0
....J....J U 'Uu
II
uuz>a:
OA
Os
NC
Oc
OD
A
S
NC
C
D
en
w
U
>
w
c
en
o
:2E
u
0 10
a..
u
IZzz«z
w(,9
OW
....J
NC-No internal connection
These counters are fully programmable; that is,
the outputs may be preset to either level. As
presetting is synchronous, setting up a low level
at the load input disables the counter and causes
the outputs to agree with the setup data after
the next clock pulse regardless of the levels of
the enable inputs.
J:
The clear function for the 'HC160 and 'HC161 is asynchronous and a low level at the clear input sets
all four of the flip-flop outputs low regardless of the levels of the clock, load, or enable inputs.
The clear function for the 'HC162 and 'HC163 is synchronous and a low level at the clear input sets all
four of the flip-flop outputs low after the next low-to-high transition of the clock input, regardless of the
levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding
the maximum count desired can be accomplished with one external NAND gate. The gate output is
connected to the clear input to synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bits synchronous applications without
additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry
output. Both count-enable inputs (ENP and ENT) must be high to count, and ENT is fed forward to enable
the ripple carry output. The ripple carry output (RCO) thus enabled will produce a high-level pulse while
the count is m'aximum (9 or 15 with QA high). This high-level overflow ripple carry pulse can be used
to enable successive cascaded stages. Transitions at the ENP or ENT are allowed regardless of the level
of the clock input.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
Copyright © 1982, Texas Instruments Incorporated
3-115
TYPES SN54HC160 THRU SN54HC163
SN74HC160 THRU SN74HC163
SYNCHRONOUS 4·BIT DECADE AND BINARY COUNTERS
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD)
that will modify the operating mode have no effect on the contents of the counter until clocking occurs.
The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by
the conditions meeting the stable setup and hold times ..
The SN54HC160 through SN54HC163 are characterized for operation over the"full military temperature
range of - 55°C to 125°C. The SN74HC160 through SN7 4HC 163 are characterized for operation from
-40°C to 85°C.
11
::I:
(')
s:o
rn
c
m
<
nm
rn
3·116
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC160, SN54HC162
SN74HC160, SN74HC162
SYNCHRONOUS 4·81T DECADE COUNTERS
logic symbols
'HC160 DECADE COUNTER
WITH DIRECT CLEAR
(15)
'HC162 DECADE COUNTER
WITH SYNCHRONOUS CLEAR
RCO
ClK
A
B
C
0
(14)
(13)
(12)
(11)
OA
OB
Dc
00
'HC160 and 'HC162 logic diagram (positive logic)
II
en
w
(.)
>
W
c
en
o
2
(.)
::I:
t For the sake of simplicity, the routing of the complementary signals IT> and CK is not shown on this overall logic diagram. The uses
of these signals are shown on the logic diagram of the OfT flip-flops.
Pin numbers shown are for J and N packges.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-117
TYPES SN54HC161, SN54HC163
SN74HC161, SN74HC163
SYNCHRONOUS 4·BIT BINARY COUNTERS
logic symbols
'HC161 BINARY COUNTER
WITH DIRECT CLEAR
'HC163 BINARY COUNTER
WITH SYNCHRONOUS CLEAR
ClR
lOAD
(15)
RCO
ENT
(14)
A
B
(51
C
(6)
0
(13)
[4)
[8)
(12)
(11)
aA
aB
ac
aD
'HC161 and 'HC163 logic diagram (positive logic)
lOAD ....:(.=.:9)~_ _ _ _ _.q
ENT
::I:
ENP
(')
S
ClK ...=;-+-----i
ot/)
r
CK
!+'HC161 ONLY
1 )'-t_ _--i
ClR ....:(c.:..:
./L
R
~~'~iC1630NLY~r
C
lD
m
:::
(')
m
A
(3)
B
(4)
C
(5)
o
(6)
t/)
t For the sake of simplicity, the routing of the complementary signals iJj and
of these signals are shown on the logic diagram of the D/T flip-flops.
CR: is
not shown on this overall logic diagram. The uses
Pin numbers shown are for J and N packages.
3-118
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC160 THRU SN54HC163
SN74HC160 THRU SN74HC163
SYNCHRONOUS 4·BI1 DECADE AND BINARY COUNTERS
logic symbol, each DfT flip·flop (positive logic)
LD (LOAD)
M1
TE (TOGGLE ENABLE)
G2
CK (CLOCK)
L
j) (INVERTED DATA)
R (INVERTED RESETI
i.2TI1C3
a
G4
(OUTPUT)
3D
:
4R
logic diagram, each DfT flip-flop (positive logic)
CK ....................................................................... -..........~...............- - - -.....-.~--~
LD .....- -...................,
II
TE .....- - - ,
rot
en
w
a
[Ot
j) ....._ _..J
en
CRt
CRt
R .........................~..........----.....----.........................~
tThe origins of the signals
U
>
w
c
Lo
and
CK
o
2
u
::I:
are shown in the logic diagrams of the overall devices.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-119
TYPES SN54HC160, SN54HC162
SN74HC160, SN74HC162
SYNCHRONOUS 4·811 DECADE COUNTERS
'HC160 and 'HC162 output sequence
Illustrated below is the following sequence:
1. Clear outputs to zero (SN54HC160 and SN74HC160 are asynchronous; SN54HC162 and
SN74HC162 are synchronous)
2. Preset to BCD seven
3. Count to eight, nine, zero, one, two, and three
4. Inhibit
m~
U
toAD
A-.J
lEI
DATA
INPUTS
B-.J
c-.J
J:
I--
0
o
3:
oen
L=
L=
c=
I
--
ClK
ENP
c
m
,
ENT .....__~__~__~:~I--~------------------~----------~~
:$
o
°A -
m
en
:
--,
..--.
_'--.-.J
---,
I
°B _
OUTPUTS
-, -,
~
,
I
I
I
I
,
I
I~____________- J
- -, --I
Oc_
_'--.-.Jf----i
- ...., ---1 '
~
I~
,
I
_______________________________________
I
-l
;
I
I
I
:
I
:
. , . . 1-
00_
RCO
iii
I
I
:7
I
-
-
-
,
II
r
I - II~__~~~~_____________
:8
9
0
2
3
..I..- - - - - - C O U N T - - -..........I----INHIBIT
SYNC PRESET
ASYNC CLEAR
CLEAR
3-120
_______
I
I
TEXAS
'1!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC161. SN54HC163
SN74HC161. SN74HC163
SYNCHRONOUS 4·BIT BINARY COUNTERS
'HC161 and 'HC163 output sequence
Illustrated below is the following sequence:
1. Clear outputs to zero (SN54HC161 and SN74HC161 are asynchronous; SN54HC163 and
SN74HC163 are synchronous)
2. Preset to binary twelve
3. Count to thirteen, fourteen, zero, one, and two
4. Inhibit
m~
I
I
I
LoAD
A
___
U
I
1-I--
--
B
DATA
INPUTS
-
~------~I
I
II
-
c-.J
1_-
D.J
I
1_-
I
-
CJ)
W
U
ClK
>
w
C
1
ENP
:I
ENT
:I
1
CJ)
o
2
I
QA
- -, --,
-
-1.
u
_I
J:
OUTPUTS
QD=:;~
I
I
RCO
I
I
:sL pi:ET
I
I
1
I
r--1
I~
1_~---::'7-----------
IM:3_ _1_4_ _
15COUNOT _ _ _--1:"114-4_ _ _ _ INHIBIT _ _ _....
CLEAR
ASYNC
CLEAR
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-121
TYPES SN54HC160. SN54HC161
SN74HC160. SN74HC161
SYNCHRONOUS ~·BIT DECADE AND BINARY COUNTERS
absolute maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
fclock
VCC
2V
4.5 V
0
0
6
31
6V
0
36
2V
4.5 V
80
16
6V
2V
4.5 V
14
80
.16
6V
14
150
30
45
6V
2V
26
q5
38
205
38
32
170
4.5 V
27
41
34
6V
2V
23
170
35
255
215
ENP, ENT
4.5 V
34
51
43
29
125
43
190
37
155
ClR inactive
6V
2V
4.5 V
25
38
31
6V
2V
21
32
0
0
4.5 V
0
0
0
6V
0
0
0
ClK high
Pulse duration
CLR low
A, B, C, or D
J:
('")
s:o
lOAD low
tsu
Setup time,
before ClK t
rn
c
m
S
n
m
rn
th
3-122
Hold time, all synchronous
inputs after ClK t
SN74HC160
SN74HC161
MIN
MAX
MAX
Clock frequency
111
SN54HC161
MIN
MAX
4,2
0
MIN
or low
tw
SN54HC160
TA = 25°C
2V
4.5 V
0
0
21
0
0
120
25
0
100
24
20
20
120
17
100
24
20
20
17
225
190
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
29
5
25
UNIT
MHz
29
ns
ns
26
I
0
ns
TYPES SN54HC160, SN54HC161
SN74HC160, SN74HC161
SYNCHRONOUS 4·BIT DECADE AND BINARY COUNTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
tpd
ClK
RCa
tpd
ClK
Any Q
tpd
ENT
RCa
tpHl
ClR
Any Q
tpHl
ClR
RCa
tt
Any
TA = 25°C
vCC
MIN
2V
4.5 V
6V
2V
4.5 v
6V
2V
4.5 V
6V
2V
4.5 V
6
31
36
TVP
14
40
44
83
24
20
MAX
80
25
21
105
21
18
110
22
19
205
41
35
195
39
33
210
42
36
220
44
37
38
8
6
75
15
13
62
17
14
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
SN54HC160
SN54HC161
MIN
MAX
4.2
21
25
SN74HC160
SN74HC161
MIN
MAX
5
25
29
325
65
55
310
62
53
295
59
50
315
63
54
330
270
54
46
255
51
43
245
66
56
110
22
19
215
43
37
Power dissipation capacitance
MHz
ns
ns
49
42
265.
ns
53
45
275
ns
55
47
95
ns
19
16
ns
60 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
UNIT
II
en
w
(J
:>w
c
en
o
2
(J
:I:
4
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265
3-123
TYPES SN54HC162, SN54HC163
SN74HC162, SN74HC163
SYNCHRONOUS 4·BIT DECADE AND BINARY COUNTERS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
timing requirements over recommended operating free~air temperature range (unless otherwise noted)
PARAMETER
vCC
fclock
Clock frequency
tw
Pulse duration, ClK high or low
A, B, C, or D
i:OAB
low
Setup time,
:::I:
tsu
before ClK t
o
ENP, ENT
~
orJ)
ClR low
C
m
ern inactive
S
o
m
rJ)
th
3-124
Hold time, all synchronous
inputs after ClK t
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
SN54HC162
TA :: 25°C
MIN
MAX
0
'0
0
80
16
14
150
30
26
135
27
.23
170
34
29
160
32
27
160
32
27
0
0
0
6
31
36
SN74HC162
SN74HC163
UNIT
SN54HC163
MIN
MAX
MIN
MAX
0
0
0
120
24
20
225
45
38
205
41
35
225
51
43
240
48
41
240
48
41
0
0
0
0
0
0
100
20
17
190
38
32
170
34
29
215
43
37
200
40
34
200
40
34
0
0
0
5
25
29
-II}
TEXAS
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS, TeXAS 75265
4.2
21
25
MHz
ns
ns
ns
3!
TYPES SN54HC162. SN54HC163
SN74HC162. SN74HC163
SYNCHRONOUS 4·BIT DECADE AND BINARY COUNTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL ... 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
tpd
tpd
tpd
tt
ClK
ClK
ENT
RCO
Any Q
RCO
Any
SN54HC162
TA = 25°C
vCC
MIN
TVP
SN74HC162
SN54HC163
MAX
MIN
SN74HC163
MAX
MIN
2V
6
14
4.2
5
4.5 V
31
21
25
6V
36
40
44
25
29
UNIT
MAX
MHz
2V
83
215
325
4.5 V
24
43
65
270
54
6V
20
37
55
46
255
2V
80
205
310
4.5 V
25
41
62
51
6V
21
35
53
43
2V
62
195
295
245
4.5 V
17
39
59
49
6V
14
33
50
42
2V
38
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance
60 pF typ
ns
ns
ns
ns
II
en
w
U
>
w
c
en
o
2
u
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
J:
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-125
TYPES SN54HC160 THRU SN54HC163
SN74HC160 THRU SN74HC163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
TYPICAL APPLICATION DATA
N-BIT SYNCHRONOUS COUNTERS
This application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit
counter. The 'HC160 and 'HC162 will count in BCD, and the 'HC161 and 'HC163 will count in binary. Virtually
any count mode (modulo-N, N1-to-N2, N1-to-maximum) can be used with this fast look-ahead circuit.
lSB
ClR
CLEAR (ll
r--.
CT=O
lOAD - ' "
COUNT (HI/
DISABLE III
CTR
Ml
ENT
G3
ENP
3CT~MAX
G4
ClK
,
-
RCO
C5/2,3,4+
1"
LOAD (L)
II
J:
(')
S
o
en
c
m
~
,- rl.
COUNT (HII
DISABLE (l
CLOCK
-~
A - 1,50
(II
~QA
B-
(21
~QB
C-
(31
~Qc
0-
(41
f--- Qo
CLRr-,
CT=O CTR
lOAD r-....
Ml
ENT
G3
ENP
3CT= MAX
G4
ClK
,
C5/2,.3,4+
-
RCO
r
A - 1,50
(1)
B-
(21
-QB
C-
(31
-Qc
0-
(41
-Qo
-QA
(')
m
en
ClR .. J"-..,
LOAO
r-,
ENT
CT=O
G3
ENP
CTR
Ml
3CT
~MAX
~
G4
ClK
C5/2,3,4+
"1
r
A - 1,50
(II
~OA
B-
(21
,--QB
C-
(3)
r-°c
0-
(41
~Qo
ClR
r--.
lOAO r-....
ENT
ENP
ClK
CT=O CTR
Ml
G3
3CT -MAX
~
G4
,
C5/2,3,4+
I'"
A - 1,50
B_
121
-OB
C-
(3)
-Oc
0-
(4)
-°0
(II
-OA
--------------~v~------------~
TO MORE SIGNIFICANT STAGES
3-126
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DAllAS. TEXAS 75265
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC164, SN74HC164
8·BIT PARALLEL·OUT SERIAL SHIFT REGISTERS
02684, DECEMBER 1982-REVISED MARCH 1984
SN64HC164 ... J PACKAGE
SN74HC164 ... J OR N PACKAGE
(TOP VIEW)
• AND·Gated (Enable/Disable) Serial Inputs
• Fully Buffered Clock and Serial Inputs
A
S
OA
Os
Oc
OD
GND
• Direct Clear
• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
• Dependable Texas Instruments Quality
and Reliability
description
VCC
OH
OG
OF
OE
ClR
ClK
SN54HC164 ... FH OR FK PACKAGE
SN74HC164 ... FH OR FN PACKAGE
(TOP VIEW)
These 8-bit shift registers feature AND-gated serial
inputs and an asynchronous clear. The gated serial
inputs (A and 8) permit complete control over incoming data as a low at either input inhibits entry of
the new data and resets the first flip-flop to the low
level at the next clock pulse. A high-level input
enables the other input, which will then determine
the state of the first flip-flop. Data at the serial
inputs may be changed while the clock is high or
low, provided the minimum setup time requirements
are met. Clocking occurs on the low-to-high-Ievel
transition of the clock input.
u
u u::r:
COoeiZ>O
II
OA
NC
OB
en
NC
Oc
w
CJ
OZZ-l-l
10:
:>
w
NC-No internal connection
en
00 U
The SN54HC164 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC164 is characterized for operation from -40°C to 85°C.
(!)
~
UU
C
o
~
logic symbol
CJ
J:
FUNCTION TABLE
INPUTS
OUTPUTS
ClR
L
ClK
A
B
X
H
L
H
H
t
t
X
X
H
L
X
X
H
X
H
t
X
L
OA
L
CLR
0B··· OH
L
L
CLK
OAO
aBO
aHa
A
H
OAn
B
L
QAn
°Gn
QGn
L
QAn
QGn
CA
CB
(61
H ; high level Isteady state I. L ; low level (steady state)
X ; irrelevant (any input. including transitions)
(101
t ; transition fr~m low to high level.
(121
CAO. CBO. 0HO ; the level of 0A. 0a. or 0H. respectively. before the
indicated steady-state input conditions were established.
(131
(111
0An. 0Gn ; the level of 0A or 0G before the most-recent t transition
of the clock; indicates a one-bit shift.
.
Cc
Co
Ce
CF
CG
CH
Pin numbers shown are for J and N packages.
. TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright©1982 by Texas Instruments Incorporated
3-127
TYPES SN54HC164, SN74HC164
8·BIT PARALLEL·OUT SERIAL SHIFT REGISTERS
logic diagram (positive logic)
typical clear, shift, and clear sequences
II
CL"R--U
~
I
I
I
SERIAL {
INPUTS
:::t
~--..--..------..+-----..----
A
B ----i-,- - - - - - I
n
S
o(J)
I
I
CLK
I
---,
---,
---,
__________________
---,
________________________
I
QA __
~I_ _ _ _ _ _ _ _ _ _ _--I
C
QB ___ ~I__________________~
S
n
QC ___
m
m
(J)
QO
~I
~I
OUTPUTS
QE ·---~l
~--..---------~------------~-------~--------~~---~-----------
~
~
_________________________
....J
~~----------L.Sl'---________
---,
_____________________________- - - I
---,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-....J
QF ___
QG ___
~I
---,
QH __
I
~I
~,
I
I
I
________________________________________
n'
~
~
____________
I
CLEAR
CLEAR
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
3-128
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
Clock frequency
fclock
ClR low
Pulse duration
tw
ClK high or low
Data
Setup time
before ClKt
tsu
ClR inactive
Hold time. data after ClK t
th
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
TA = 25°C
MIN
MAX
6
31
36
0
0
0
100
20
17
SN54HC164
MIN
MAX
SN74HC164
MIN
MAX
0
0
0
150
30
25
0
0
0
125
25
21
4.2
21
25
4.5 V
6V
2V
4.5 V
6V
2V
80
16
14
100
20
27
100
20
27
5
120
24
20
150
30
25
150
30
25
5
5
4.6 V
6V
5
5
5
5
5
5
5
25
28
UNIT
MHz
ns
100
20
18
125
25
21
125
25
21
ns
II
ns
en
w
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
tpHl
ClR
Any Q
tpd
ClK
Any Q
tt
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
6
10
54
31
62
36
140 205
28
41
24
35
115
175
23
35
20
30
38
75
15
8
13
6
Power dissipation capacitance
SN54HC164
MAX
MIN
4.2
21
25
No load. TA = 25°C
SN74HC164
MIN
MAX
5
25
UNIT
MHz
28
(.)
>
W
C
en
o
~
(.)
295
255
59
51
265
53
45
110
22
19
51
46
220
44
ns
38
95
19
ns
ns
J:
16
135 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265
3-129
:I:
(")
3:
otn
C
m
<
(=)
m
tn
3-130
TYPES SN54HC165. SN74HC165
PARALLEL·LOAD 8·BIT SHIFT REGISTERS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
•
Complementary Outputs,
•
Direct Overriding Load (Data) Inputs
SN54HC165 •.• J PACKAGE
SN74HC165 ..• J OR N PACKAGE
(TOP VIEW)
SH/lD
ClK
E
•
Gated Clock Inputs
•
Parallel·to-Serial Data Conversion
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
description
The SN54HC165 is characterized for operation
over the full military temperature range of
-55 DC'to 125 DC. The SN74HC165 is
characterized for operation -from - 40 DC to
85 D C.
0
F
C
G
H
OH
GND
B
A
SEA
QH
SN54HC165 ••. FH OR FK PACKAGE
SN74HC165 ••• FH OR FN PACKAGE
(TOP VIEW)
The 'HC165 is an 8-bit serial shift register that,
when clocked, shifts the data toward serial
output QH. Parallel-in access to each stage is
provided by eight individual direct data inputs
that are enabled by a low level at the SH/lD
input. The 'HC165 also features a clock inhibit
function and a complementary serial output QH.
Clocking is accomplished by a low-to-high
transition of the ClK input while SH/lD is held
high and ClK INH is held low. The functions of
the ClK and ClK INH (clock inhibit) inputs are
interchangeable. Since a low ClK input and a
low-to-high transition of ClK INH will also
accomplish clocking, ClK INH should be
changed to the high level only while the ClK
input is high. Parallel loading is inhibited when
SH/lD is held high. The parallel inputs to the
register are enabled while SH/lD is low
independently of the levels of ClK, ClK INH, or
SER inputs.
VCC
ClK INH
J:
0
~ 1~
z
II
u;;;
U..J
..J J: U,
UU)z>U
E
o
F
C
en
w
u
NC
NC
G
B
H
A
J:O U
:>w
C
en
o
:!
u
J:a:
10 ~ z 0 ~
NC-No internal connection
:I:
logic symbol
ClK INH,
ClK
SER
A
B
FUNCTION TABLE
C
INPUTS
0
ClK
INH
FUNCTION
X
H
X
l
X
X
H
Parallel load
t
Shift
t
l
Shift
sHi[O
ClK
l
H
H
H
H
E
F
G
No change
H
No change
(9)
(6)
10
(7) OH
O'H
Pin numbers shown are for J and N packages.
Shift - content of each internal register
shifts toward serial output QH. Data at
serial input is shifted into first register.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-131
TYPES SN54HC165, SN74HC165
PARALLEL·LOAD 8·BIT SHIFT REGISTERS
logic diagram (positive logic)
_ _ Pin numbers shown are for J and N packages.
_ _ typical shift, load, and inhibit sequences
CLK
::J:
(")
s:
orJ)
CLKINH
SER
L
SH/LD-U
C
I
I
m
A----flIHl~
!S
(")
B
____ ___________________________________
~
I L
I
m
rJ)
C
D
--f:Hl
I L ------.---------------------------------I
DATA
E~~----~-----------------------------------
F
I L
I
G~~----~----------------------------------I
H---lfHl~__~------------------------------
____.~I--------~------
QH
CH ----
H
H
L
L
~------~I------~
..------
j4-INHIBIT -.~~II4
SERIAL SHIFT - - - - - -••
LOAD
TEXAS
-I/}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC165, SN74HC165
PARALLEL·LOAD 8·BIT SHIFT REGISTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
2V
4.5 V
fclock Clock frequency
6V
2V
4.5 V
SH/iJ5 low
tw
SH/iJ5 high before ClK t
6V
2V
4.5 V
6V
2V
4.5 V
SER before ClK t
6V
2V
4.5 V
Pulse duration
ClK high or low
tsu
Setup time
6V
2V
4.5 V
ClK INH low
before ClKt
ClK INH high
before ClK~
Data before SH/iJ5 t
th
6V
2V
4.5 V
6V
2V
4.5 V
6V
SER data after ClK t
2V
4.5 V
6V
PAR data after SH/LD t
2V
4.5 V
6V
Hold time
TA = 25°C
MIN
MAX
0
0
0
80
16
14
6
31
36
20
120
24
80
16
14
80
16
14
20
120
24
20
60
12
40
8
7
100
20
17
40
8
7
100
20
17
5
5
5
5
5
5
TEXAS
SN54HC165
MAX
MIN
4.2
0
21
0
25
0
120
24
SN74HC165
MIN
MAX
5
0
0
0
100
20
17
100
20
17
100
20
17
50
10
9
125
25
21
50
10
10
150
30
25
60
12
10
150
30
26
5
9
125
25
21
5
5
5
5
5
5
5
5
5
5
5
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
25
29
UNIT
MHz
ns
ns
ns
ns
ns
•
en
w
to)
ns
ns
ns
>
W
C
en
o
.:2E
to)
J:
ns
3-133
TYPES SN54HC165, SN74HC165
PARALLEL·LOAD 8·BIT SHIFT REGISTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
FROM
(INPUT)
PARAMETER
f max
tpd
tpd
tpd
•
tt
::I:
vCC
TA = 25°C
TYP MAX
MIN
2V
4.5 V
SH/ID
ClK
H
QH or GH
QH or GH
QH or GH
Any
6
6V
2V
4.5 V
13
SN54HC165
MIN
MAX
4.2
MAX
50
21
25
36
62
80
25
29
150
225
20
30
45
38
16
38
190
75
26
150
225
32
190
4.5 V
15
30
45
38
6V
2V
13
75
26
150
38
225
32
190
4.5 V
15
13
30
26
45
6V
2V
4.5 V
38
8
75
15
6V
6
3
No load. TA - 25°C
c
<
m
(')
m
en
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
38
110
UNIT
MHz
6V
2V
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
3-134
SN74HC165
MIN
5
31
Power dissipation capacitance
(')
s:
o
en
TO
(OUTPUT)
.,
38
32
ns
ns
ns
95
22
19
19
16
75 pF typ
ns
TYPES SN54HC166. SN74HC166
PARALLEL·LOAD H·BIT SHIFT REGISTERS
HIGH·SPEED
CMOS LOGIC
02684, DECEMBER 1982-REVISED MARCH 1984
SN54HC166 ... J PACKAGE
SN74HC166 ... J OR N PACKAGE
(TOP VIEW)
•
Synchronous Load
•
Direct Overriding Clear
•
Parallel to Serial Conversion
SER
VCC
SH/LD
H
QH
G
A
•
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
C
Dependable Texas Instruments Quality and
Reliability
ClKINH
ClK
GND
B
0
F
E
ClR
description
SN54HC166 ... FH OR FK PACKAGE
SN74HC166 ... FH OR FN PACKAGE
(TOP VIEW)
The 'HC166 parallel-in or serial-in, serial-out
registers feature gated clock inputs and an
overriding clear input. The parallel-in or serial-in
modes are established by the shift/load input.
When high, this input enables the serial data
input and couples the eight flip-flops for serial
shifting with each clock pulse. When low, the
parallel (broadside) data inputs are enabled and
synchronous loading occurs on the next clock
pulse. During parallel loading, serial data flow is
inhibited. Clocking is accomplished on the lowto-high-Ievel edge of the clock pulse through a
two-input positive NOR gate permitting one input
to be used as a clock-enable or clock-inhibit
function. Holding either of the clock inputs high
inhibits clocking; holding either low enables the
other clock input. This, of course, allows the
system clock to be free-running and the register
can be stopped on command with the other
clock input. The clock-inhibit input should be
changed to the high level only when the clock
input is high. A direct clear input overrides all
other inputs, including the clock, and resets all
flip-flops to zero.
B
H
C
QH
NC
NC
o
G
ClK INH
F
~ 0
CLOCK
LOAD
INHIBIT
X
X
H
X
X
L
L
H
L
L
t
t
t
t
CLEAR
L
H
H
L
H
H
L
H
X
H
CLOCK SERIAL
OUTPUTS
2
(.)
B
C
D
OUTPUT
G
QH
H
X
X
L
L
L
X
X
X
OAO
a ... h
a
QBO
b
OHO
h
X
X
X
H
°An
°Gn
L
°An
aBO
°Gn
OHO
°AO
(J)
o
A
QB
X
W
SER
QA
L
>
W
C
ClKINH
ClK
A ... H
H
W
(.)
J:
F
PARALLEL
(J)
logic symbol
FUNCTION TABLE
SHIFT/
10:
II
NC-No internal connection
E
INTERNAL
U
da zd
The SN54HC166 is characterized for operation
over the full· military temperature range of
-55°C to 125°C. The SN74HC166 is
characterized for operation from - 40°C to
85°C.
INPUTS
ul~
0:
w U UI
«(/)z>(/)
TEXAS
(5)
(10)
(11) .
(12)
(14)
(13)
QH
Pin numbers shown are for J and N packages.
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
Copyright ©1982 by Texas Instruments Incorporated
3-135
TYPES SN54HC166, SN74HC166
PARALLEL·LOAD 8·BIT SHIFT REGISTERS
logic diagram (positive logic)
C
B
II
H
(14)
141
131
Pin numbers shown are for J and N packages.
J:
n
s:
typical clear, shift, load, inhibit, and shift sequences
o
rn
c
CLOCK
CLOCK INHIBIT "'-_~_ _ _ _ _ _ _ _ _ _ _~_--'r-.~.:-
m
<
I
I
CLEAR - U I
I
I
I
I
SERIAL INPUT
n
m
SHIFT/LOAD
rn
--L..II1
-~;----------L.-.;--L1r--.......!--"::"-"'---------
I
A
~'-_~~
B .....
.....___________
~~
I
~_~_~L~I
_ _ _ _ _ _ _ _ _ __
_ _~~_ _ _ _ _ _ _ _ _ __
I
C .....~~_ _ _ _ _ _ _ _ _~_~~nHn~_~--..:
PARALLEL
INPUTS
__________
________ ___
~
I
D
E
LI
I
~~_~~~
F .....
~~
______________
~
__
~
__
I
~L~I
____
~~
I
_ _ _ _ _ _ _ _ ___
________________
G .....~~_ _ _ _ _ _ _ _ _~_~~r.Tn~_~:..-...~
___________
I
H......;-~___________-+_~~nHn'-_~~:..-...__________
••
OUTPUTQ H _
--..
'--~
I
I
_ _ _ _ _ _ _ _....
H
INHIBIT
1IlI~--- SERIAL SHIFT -----....~114____tI1~41---- SERIAL SHIFT-----~
CLEAR
LOAD
maximum ratings, recommended operating conditions, and eletrical characteristics
See Table IV, page 2-10.
3-136
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC166, SN74HC166
PARALLEL·LOAD 8·BIT SHIFT REGISTERS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
Vec
fclock Clock frequency
ClR low
tw
Pulse duration
ClK high
or low
SHim high
before ClKt
\
SER before
ClKt
tsu
Setup time
ClK INH
before ClKt
Data before
SHim t
ClR inactive
before ClK t
SHim high
after ClK t
SER after
ClK t
th
Hold time
ClK INH
after ClK t
Data after
SHim t
ClR active
after ClK t
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
BV
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
6
0
31
0
36
0
100
20
17
80
16
14
145
29
25
80
16
14
100
20
17
80
16
14
40
8
7
0
0
0
5
5
5
0
0
0
5
5
5
0
0
0
SN54HC166
MIN
MAX
4.2
0
21
0
25
0
150
30
26
120
24
20
220
44
38
120
24
20
150
30
26
120
24
20
60
12
10
0
0
0
5
5
5
0
0
0
5
5
5
0
0
0
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SN74HC166
MIN
MAX
5
0
25
0
29
0
125
25
21
100
20
17
180
36
31
100
20
17
125
25
21
100
20
17
50
10
9
0
0
"
0
5
".
5
5
0
0
0
5
5
5
0
0
0
UNIT
MHz
ns
ns
II
(J)
W
CJ
>
w
C
(J)
o
::2E
CJ
::I:
ns
3·137
TYPES SN54HC166. SN74HC166
PARALLEL·LOAD 8·BIT SHIFT REGISTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
TO
TA:: 25°C
MIN TYP MAX
11
6
36
31
45
36
62
120
18
24
13
20
75
150
15
30
13
26
38
75
8
15
VCC
2V
f max
tpHl
ern
QH
tpd
ClK
QH
tt
_I
4.5 V
6V
2V
Cpd
Any
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
1 Power dissipation capacitance
6
SN54HC166
MAX
MIN
4.2
21
25
13
I
::I:
n
s:o
tJ)
C
m
<
n
m
tJ)
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
UNIT
MHz
29
180
36
31
225
45
38
110
22
19
150
30
26
190
38
32
95
19
16
50 pF typ
_ _ NOTE 1: For load circuit and voltage waveforms, see page 1-14.
3-138
SN74HC166
MAX
MIN
5
25
ns
ns
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC173, SN74HC173
4·81T D·TYPE REGISTERS WITH 3·STATE OUTPUTS
02684, DECEMBER 1982-REVISED MARCH 1984
•
•
Gated Output-Control Lines for Enabling
or Disabling the Outputs
•
Fully Independent Clock Virtually
Eliminates Restrictions for Operating in
One of Two Modes
•
Package Options Include Both Plastic
and Ceramic Chip Carriers in Addition to
Plastic and Ceramic DIPs
•
SN54HC173 ••• J PACKAGE
SN74HC173 ••• J OR N PACKAGE
High·Current 3·State Outputs Interface
Directly with System Bus or Can Drive
up to 15 LSTTL Loads
(TOP VIEW)
M
VCC
ClR
N
1Q
2Q
3Q
4Q
10
20
3D
40
(32
(31
ClK
GNO
SN54HC173 ••• FH OR FK PACKAGE
SN74HC173 ••• FH OR FN PACKAGE
Dependable Texas Instruments Quality
and Reliability
(TOP VIEW)
U ~5
z~z>u
II
description
The 'HC173 four-bit registers include D-type
flip-flops featuring totem-pole three-state
outputs capable of driving highly capacitive or
relatively low-impedance loads. The highimpedance third state and increased drive
provide these flip-flops with the capability of
being connected directly to and driving the
lines in a bus-organized system without need
for interface or pull-up components.
Gated enable inputs are provided on these
devices for controlling the entry of data into the
flip-flops. When both data-enable inputs are
low, data at the 0 inputs are loaded into their
respective flip:flops on the next positive
transition of the clock input. Gate output
control inputs are also provided. When both are
low, the normal logic states (high or low levels)
of the four outputs are available for driving the
loads or bus lines. The outputs are disabled
independently from the level of the clock by a
high logic level at either output control input.
The outputs then present a high impedance and
neither load nor drive the bus line. Detailed
operation is given in the function table.
10
20
• NC
NC
3Q
4Q
3D
40
til
w
(.)
:;
W
C
~OU.-N
d
~ ZIC,!)IC,!)
en
2
(.)
o
NC-No internal connection
FUNCTION TABLE
J:
INPUTS
DATA ENABLE
DATA
OUTPUT
Q
CLEAR
CLOCK
G1
G2
D
H
X
X
X
X
L
L
L
X
X
X
L
t
t
i
i
L
L
H
X
X
X
H
X
00
00
00
L
L
L
L
H
L
L
H
L
When either M or N (or both) is (are) high the output is
disabled to the high-impedance state; however sequential
operation of the flip-flops is not affected.
The SN54HC173 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC173 is
characterized for operation from - 40°C to
85°C.
Copyright © 1982 by Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFiCe BOX 225012 • DALLAS, TexAS 75265
3-139
TYPES SN54HC173, SN74HC173
4·81T O·TYPE REGISTERS WITH 3·STATE OUTPUTS
logic symbol
10
20
30
40
il
logic diagram (positive logic)
M (1)
OUTPUT
CONTROL {
::t:
N (2)
.
(")
3:
o
rn
cm
S
(")
m
rn
DATA (1
;.....:.;3):-----f---f---f~
20
DATA (12)
3D
'---'-----f----It--1
DATA ;...(1...;.1):....-_ _t--_ _,---~
40
~-------~-~R
Pin numbers shown are for J and N packages.
3-140
-I!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC173, SN74HC173
4·81T O·TYPE REGISTERS WITH 3·STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
fclock
Input clock frequency
ClK high or low
tw
Pulse
duration
ClR high
Gl and G2
tsu
Setup time
before ClK f
0
4.5 V
0
6
31
6V
2V
0
80
4.5 V
16
120
24
100
20
6V
2V
20
120
24
17
100
4.5 V
14
80
16
6V
14
20
17
2V
100
150
125
4.5 V
20
17
100
30
25
150
25
21
125
20
17
30
25
25
90
18
135
21
115
27
23
6V
2V
15
23
0
19
0
4.5 V
0
0
0
0
0
0
4.5 V
2V
Gl and G2
th
Hold time
4.5 V
6V
2V
after ClK t
Data
SN74HC173
MIN
MAX
2V
6V
ClR inactive
SN54HC173
MIN
MAX
MAX
6V
2V
Data
TA = 25°C
MIN
36
0
0
4.2
0
0
0
21
25
0
0
20
0
0
0
4.5 V
0
0
0
6V
0
0
0
TEXAS
-1.!1
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
5
25
29
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
II
en
w
u
:>w
c
en
o
~
U
:I:
3-141
TYPES SN54HC173, SN74HC173
4·81T O·TYPE REGISTERS WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free· air temperature range (unless otherwise
noted), CL
50 pF (see Note 1)
=
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
J:
tpHl
ClR
Any
tpd
ClK
Any
ten
MorN
Any
tdis
MorN
Any
Any
tt
n
S
o
vcc
2V
4.6 V
6V
2V
4.5 V
6V
2V
TA - 26°C
MIN
TVP
8
46
55
78
21
20
78
21
20
78
20
15
40
18
16
20
8
6
6
31
36
4.5 V
6V.
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
MAX
SN64HC173
MIN
MAX
4.2
21
25
6
25
29
225.
45
38
225
45
38
225
45
38
225
45
38
90
18
15
150
30
26
150
30
26
150
30
26
150
30
26
60
12
10
SN74HC173
MAX
MIN
UNIT
MHz
190
38
32
190
38
32
190
38
32
190
38
32
75
15
13
ns
ns
ns
ns
ns
29 pF typ
Power dissipation capacitance
rn
c
m
<
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), ~L
150 pF (see Note 1)
=
nm
rn
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpHl
ClR
Any
tpd
ClK
Any
ten
tt
MorN
Any
Any
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN
-
TVP
100
28
21
100
28
21
100
28
21
45
17
13
MAX
200
40
34
200
SN64HC173
MAX
MIN
300
40
34
200
40
34
210
42
36
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
3-142
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
60
51
300
60
51
300
60
51
315
63
53
SN74HC173
MIN
MAX
250
50
43
250
UNIT
ns
50
43
250
50
43
265
ns
53
45
ns
ns
HIGH-SPEED
CMOS LOGIC
TYPES SN54HC174. SN54HC175
SN74HC174. SN74HC175
HEX/OUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
02684. DECEMBER 1982-REVISED MARCH 1984
•
SN54HC174 ... J PACKAGE
SN74HC174 ..• J OR N PACKAGE
(TOP VIEW)
'HC174 Contains Six Flip-Flops with SingleRail Outputs
o 'HC175 Contains Four Flip-Flops with
ClR
Double-Rail Outputs
•
o
VCC
10
60
60
50
50
40
40
10
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
20
20
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
GNO
ClK
SN54HC174 ... FH OR FK PACKAGE
SN74HC174 ... FH OR FN PACKAGE
o Dependable Texas Instruments Quality and
(TOP VIEW)
5 u 80
01
.... uz>w
Ma Zd ""
oou~o
c
SN54HC175 ... J PACKAGE
SN74HC175 •.. J OR N PACKAGE
en
o
2
u
(TOP VIEW)
ClR
VCC
10
The SN54HC174 and SN54HC175 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74HC174 and SN74HC175 are characterized
for operation from -40°C to 85°C.
40
40
40
30
30
30
10
20
20
20
6
GNO
J:
ClK
SN54HC175 ... FH OR FK PACKAGE
SN74HC175 ... FH OR FN PACKAGE
FUNCTION TABLE
(EACH FLIP-FLOP)
(TOP VIEW)
INPUTS
ClR ClK
D
l
H
H
H
x
t
t
l
X
H
l
X
OUTPUTS
Q
Qt
l
H
l
H
l
H
00
00
5
01
.... u
u >8 0""
Z
40
40
NC
t'HC175 only
30
30
NC-No internal connection
Copyright ©1982 by Texas Instruments Incorporated
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-143
TYPES SN54HC174, SN54HC175
SN74HC174, SN74HC175
HEXIQUADRUPLE D·TYPE FLlp·FLOPS WITH CLEAR
. logic symbols
'HC175
'HC174
ClR
elK
ClK
10
20
3D
40
50
50
60
60
10
10
20
30
40
10
20
20
30
30
40
40
20
3D
40
il
logic diagrams (positive logic)
'HC176
'HC174
J:
n
ClK
S
o
rn
1 0 ~:'----+--+--f
c
<
m
20
(4)
3D
(6)
40
(11)
50
(13)
60
(14)
n
m
rn
Pin numbers shown are for J and N packages.
3-144
TEXAS •
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS. TeXAS 75265
TYPES SN54HC174, SN74HC174
HEX/OUADRUPLE D·TYPE FLlp·FLOPS WITH CLEAR
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
'HC174 timing requirements over recommended operating free·air temperature range (unless otherwise
noted)
vCC
Clock Frequency
f.clock
ClR low
Pulse duration
tw
ClK high
or low
MAX
MIN
2V
0
6
0
4.2
0
5
0
31
0
21
0
25
6V
0
36
25
0
29
2V
80
0
120
4.5 V
16
24
6V
14
20
17
2V
80
120
100
4.5 V
16
24
20
UNIT
MHz
100
20
6V
14
20
17
2V
100
150
125
25
20
30
6V
17
25
21
before ClKt
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
0
0
0
4.5 V
0
0
0
6V
0
0
0
Hold time. data after ClKt
MAX
4.5 V
4.5 V
ClR inactive
th
SN74HC174
SN54HC174
MIN
Setup time
Data
tsu
TA = 25°C
MAX
MIN
ns
II
ns
en
w
U
>
w
ns
c
'HC174 switching characteristics over recommended operating free·air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA = 25°C
TYP MAX
MIN
2V
f max
ClR
Any
tpd
ClK
tt
Any
Any
4.5 V
6
31
9
44
6V
36
50
SN54HC174
MIN
SN74HC174
MAX
MIN
MAX
5
25
4.2
21
25
UNIT
en
o
~
U
J:
MHz
29
2V
58
160
240
200
4.5 V
17
32
48
40
6V
14
27
41
34
2V
4.5 V
58
160
240
200
17
32
48
40
6V
14
27
41
34
2V
38
75
110
90
4.5 V
8
15
22
19
6V
6
13
19
16
ns
ns
27 pF typ
Power dissipation capacitance per flip-flop.
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-145
TYPES SN54HC175, SN74HC175
HEX/QUADRUPLE D·TYPE FLlp·FLOPS WITH CLEAR
maximum ratings, recommended operating conditions, and electrical characteristics
See Table II, page 2-6.
'HC175 timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
vCC
2V
fclock
ClR low
Pulse duration
tw
ClK high
or low
lEI
::I:
Data
Setup time
before ClKt
tsu
n
S
orJ)
C
m
S
n
ClR inactive
Hold time, data after ClKt
th
TA = 25°C
MIN
MAX
0
6
SN54HC175
SN74HC175
MIN
MAX
MIN
MAX
0
4.2
0
0
5
4.5 V
0
31
0
21
6V
0
36
25
2V
80
0
120
4.5 V
16
24
6V
2V
14
80
0
100
20
4.5 V
16
20
120
24
6V
2V
14
20
17
100
150
125
4.5 V
20
30
25
6V
2V
17
100
25
150
21
125
4.5 V
30
25
6V
20
17
25
21
2V
0
0
0
4.5 V
0
0
0
6V
0
0
0
25
UNIT
MHz
29
17
100
ns
20
ns
ns
'HC175 switching characteristics 'over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
m
PARAMETER
rJ)
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
4.5 V
f max
TA = 25°C
MIN
TYP MAX
.6
12
50
31
6V
ClR,
Any
tpd
ClK
tt
Any
Any
36
60
SN54HC175·
MIN
SN74HC175
MIN
MAX
4.2
21
5
25
25
29
2V
52
150
255
190
15
45
6V
13
30
26
38
32
2V
4.5 V
58
6V
150
30
26
255,
45
38
190
16
13
38
2V
38
75
110
90
8
22
19
6V
6
15
13
19
16
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
ns
38
32
4.5 V
Power dissipation capacitance per flip-flop
UNIT
MHz
4.5 V
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
3-146
MAX
30 pF typ
ns
TYPES SN54HC180, SN74HC180
9·81T ODD/EVEN PARITY GENERATORS/CHECKERS
HIGH·SPEED
CMOS LOGl~
02484. MARCH 1984
•
•
SN54HC180 ••. J PACKAGE
SN74HC180 ••• J OR N PACKAGE
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
ITOP VIEW)
G
Dependable Texas Instruments Quality and
Reliability
description
These universal, monolithic, 9-bit (8 data bits
plus 1 parity bit) parity generators/checkers,
feature odd/even outputs and control inputs to
facilitate operation in either odd- or even-parity
applications. Depending on whether even or odd
parity is being generated or checked, the even
or odd inputs can be utilized as the parity or 9thbit input. The word-length capability is easily
expanded by cascading.
VCC
H
F
EVEN
ODD
E EVEN
E ODD
GND
E
0
C
B
A
SN54HC180 .•• FH OR FK PACKAGE
SN74HC180 ••• FH OR FN PACKAGE
ITOP VIEW)
U
U
U
:I:t!)z>u.
The SN54HC180 is characterized for operation
over the full military temperature range of
-55°C to 125°C; and the SN74HC180 is
characterized for operation from - 40°C to
EVEN
NC
ODD
NC
E EVEN
85°C.
II
E
NC
en
w
o
NC
(.)
C
:>w
FUNCTION TABLE
INPUTS
I: OF H's AT
EVEN
ODD
EVEN
H
ODD
H
EVEN
l
l
H
l
l
l
H
H
H
l
A THRU H
ODD
X
X
I:
I:
EVEN
ODD
H
l
H
H
l
l
H
l
l
H
l
H
c
en
o
CCU<{CIJ
czz
ot!)
OUTPUTS
t.l
NC-No internal connection
:2E
(.)
logic symbol
J:
EVEN
ODD
H = high level. l = low level. X = irrelevant
A
IS)
B
:E
EVEN
C
0
E
F
G
(6)
:E
ODD
H
Pin numbers shown are for J and N packages.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
Copyright © 1984, Texas Instruments Incorporated
3-147
TYPES SN54HC180, SN74HC180
9·81T ODD/EVEN PARITY GENERATORS/CHECKERS
logic diagram (positive logic)
EVEN ....;(;.;;;.3)'--_ _ _ _ _ _ _ _ _--t
;K>-----------....,
ODD-(~4~)________________~~----------------~
II
::t
(")
s:o
Pin numbers shown are for J and N packages.
VI
C
maximum ratings, recommended operating conditions, and electrical characteristics
S
(")
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL
50 pF (see Note 1)
m
See Table IV, page 2-10.
=
m
VI
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
Data
(odd = 0)
Even
2V
4.5 V
Data
(odd = 0)
Odd
6V
2V
4.5 V
Data
(even = 0)
Even
6V
2V
4.5 V
Data
(even = 0)
Odd
6V
2V
4.5 V
Even or Odd
Even or Odd
tpd
tpd
tpd
tpd
tt
VCC
6V
2V
Any
TA = 25°C
MIN TYP MAX
119 260
52
36
44
32
113 245
49
33
42
24
119
260
52
36
44
32
113 245
33
49
42
24
110
49
SN54HC180
MIN
MAX
390
78
66
370
74
63
390
78-
22
19
75
15
13
4.5 V
6V
2V
4.5 V
6V
15
12
38
8
6
Power dissipation capacitance
No load. TA
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
3-148
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SN74HC180
MAX
325
65
55
305
61
MIN
UNIT
ns
ns
52
325
ns
63
165
65
55
305
61
52
140
33
28
110
22
19
28
24
95
19
16
ns
66
370
74
= 25°C
ns
ns
TYPES SN54HC181, SN54HC881
SN74HC181, SN74HC881
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
HIGH·SPEED
CMOS LOGIC
02804, MARCH 1984
•
Full Look-Ahead for High-Speed Operations
on Long Words
•
Arithmetic Operating Modes
Addition
Subtraction
Shift Operand A One Position
Magnitude Comparison
Plus Twelve Other Arithmetic Operations
•
Logic Function Modes
Exclusive-OR
Comparator
AND, NAND, OR, NOR
'HC881 Provides Status Register Checks
Plus Ten Other Logic Operations
•
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN54HC181. SN54HC881 •.• JT PACKAGE
SN74HC181. SN74HC881 •.• JT OR NT PACKAGE
(TOP VIEW)
BO
AO
83
82
81
80
Cn
51
52
53
M
Cn
(4)
(3)
A=6
F3
("I)
0
0
cnl1W
A2
82
A3
NC
83
82
81
80
NC
C
CIJ
0
G
:E
Cn +4
FO
(8)
(7)
Cn +4
p
SN54HC181. SN54HC881 •.. FH OR FK PACKAGE
SN74HC181. SN74HC881 ••• FH OR FN PACKAGE
(TOP VIEW)
logic symbol
(5)
G
M
FO
F1
F2
GND
Dependable Texas Instruments Quality and
Reliability
50 (6)
VCC
A1
B1
A2
B2
A3
83
U
J:
12 131415161718
(16) C +4
n
I~ I~ ~ ~ 112 ~ Ia.
CI
(!)
B
AsB
A>B
A
w
c
en
o
2
The combination of signals on the 53 through 50 control lines determine the operation performed on the
data words to generate the output bits Fi. 8y monitoring the j5 and Cn + 4 outputs, the user can determine
if all pairs of input bits are equal (see table above) or if any pair of inputs are both high (see table above).
The 'HC881 has the unique feature of providing an A = 8 status while the Exclusive-OR (
function
is being utilized. When the control inputs (53, 52, 51, 50) equal H, L, L, H; a status check is generated
to determine whether all pairs (Ai, Bi) are equal in the following manner: P = (AO @ 80) + (A 1 @ 81)
+ (A2 @ 82) + (A3 @ 83). This unique bit-by-bit comparison of the data words, which is available
on the totem-pole j5 output, is particularly useful when cascading 'HC881's. As the A = 8 condition is
sensed in the first stage, the signal is propagated through the same ports used for carry generation in the
arithmetic mode (f> and (3). Thus the A = 8 status is transmitted to the second stage more quickly without
the need for external multiplexing logic. The A = 8 open-drain output allows the user to check the validity
of the bit-by-bit result by comparing the two signals for parity.
U
:I:
e)
If the user wishes to check for any pair of data inputs (Ai, Bi) being high, it is necessary to set the control
lines (53, 52, 51, 50) to L, H, L, L. The data pairs will then be ANDed together and the results ORed in
the following manner: j5 = AOBO + A 1B1 + A2B2 + A383.
P = FO+F1 +F2+F3
AOBO+A1B1 +A2B2+A3B3
(AO
0
BO)+(A1
0
B1)+(A2
0
B2)+(A3
0
B3)
The 5N54HC 181 and 5N54HC881 are characterized for operation over the full military temperature range
of -55°C to 125°C. The 5N74HC181 and 5N74HC881 are characterized for operation from -40°C
to 85°C.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-151
TYPES SN54HC181, SN54HC881
SN74HC181, SN74HC881
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
signal designations
In both Figures 1 and 2, the polarity indicators ( ~ ) indicate that the associated input or output is activelow with respect to the function shown inside the symbol and the symbols are the same in both figures.
The signal designations in Figure 1 agree with the indicated internal functions based on active-low data,
and are for use with the logic functions and arithmetic operations shown in Table I. The signal designations
have been changed in Figure 2 to accommodate the logic functions and arithmetic operations for the activehigh data given in Table II. The 'HC181 and 'HC881 together with the 'HC182 and 'HC882 can be used
with the signal designation of either Figure 1 or Figure 2.
'HC181
'HC881
O}
'HC1B1
'HCBB1
ALU
(15)
SO
P
(0 ... 15) CP ~"':"':"::.!.-':"---.
2..
M
/0 ... 15) CG p......:./1.:..::7..:,.).....;G=--...
6(P=Q) Q
31
1I_--:':~:'--I4
/0 ... 15)CO
~
(")
(14)
A=B
(16) Cn +4
S1
52
S3
_M
Cn
(6)
(5)
(4)
(3)
(8)
(7)
ALU
"} *
(0 ... 15)CP
M
(0 ••• 15)CG
6(paQ) 0
(0 ... 15)
4'
co
(15)
x
(17)
V
A=B
Cn +4
C1
AO
[1]
[1]
o
[2]
[2]
C
[4]
[4]
[8]
[8]
S
VJ
m
~
m
(")
VJ
'HC882
'HCSB2
CPG
en
XO
C1
CPO
GO
P1
G1
P2
VO
CGO
CP1
CG1
CP1
C01
X1
V1
(6)
CP4
C05
C07
CGO
CP1
CG1
CP1
Cn+8
CG2
C03
CPG
C1
CPO
C01
CG2
(11)
Cn+16
(17)
Cn+24
CP3
CG3
C03
CP4
cos
CG4
(22)
CP5
Cn+32
C07
CG5
CP6
CG6
3-152
FIGURE 1
FIGURE 2
(U~E WITH TABLE I)
(USE WITH TABLE II)
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
(6)
<=n+8
(11)
(171
(22)
Cn+16
Cn+24
Cn+32
TYPES SN54HC181, SN54HC881
SN74HC181, SN74HC881
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
TABLE I
ACTIVE-LOW DATA
SELECTION
M = L; ARITHMETIC OPERATIONS
M=H
LOGIC
Cn = L
FUNCTIONS
(no carry)
Cn = H
(with carry)
53
52
51
L
L
L
L
F=A
F = A MINUS 1
F = A
L
L
L
H
F = AB
F = AB MINUS 1
F = AB
H
H
L
F =
H
F = 1
F = MINUS 1 (2's COMP)
F
L
L
L
L
L
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
SO
A+
B
F =
=
As MINUS
F
1
A PLUS (A +
B)
L
L
F = A + B
L
H
F
H
H
L
H
F = A <±> B
F = A + S
L
L
L
F = AB
L
L
H
F = A
L
H
H
L
F = B
F = AS PLUS (A + B)
H
F = A + B
F
H
H
L
L
F = 0
F = A PLUS A*
L
H
F
H
H
L
F = AS
F = AB
H
H
H
F = A
F = A
L
=
F = AB PLUS (A + S)
B
®
B
F =
~
MINUS B MINUS 1
F=A+S
F = A PLUS (A + B)
F
F
=
=
AS
ZERO
F = A PLUS (A + S) PLUS 1
F = AB PLUS (A + S) PLUS 1
F = A MINUS B
F = (A + S) PLUS 1
F
=
A PLUS (A + B) PLUS 1
F = AS PLUS (A + B) PLUS 1
F = (A + B) PLUS 1
(A + B)
PLUS A
PLUS
=
=
F = A PLUS B PLUS 1
A PLUS B
= AB
= AS
F
A
F = A PLUS A PLUS 1
F
=
AB PLUS A PLUS 1
F = AS PLUS A PLUS 1
F = A PLUS 1
51
M = L; ARITHMETIC OPERATIONS
Cn = L
(with carry)
Cn = H
(no carry)
LOGIC
53
52
L
L
L
L
F=A
F = A
F = A PLUS 1
L
L
L
H
F = A + B
F=A+B
F
L
L
H
L
F = AB
F=A+S
F
L
L
H
H
F = 0
F
L
H
L
L
F
L
H
L
H
F=S
F
L
H
H
L
F = A MINUS B
H
H
H
F = A <±> B
F = AS
F = A MINUS B MINUS 1
L
F = AS
H
H
H
H
L
L
L
F=A+B
= AS MINUS 1
F = A PLUS AB
L
L
H
F = A PLUS B
F = A PLUS B PLUS 1
L
H
L
F = A <±> B
F = B
L
H
H
F = AB
F = AB MINUS 1
H
H
L
L
F = 1
F
H
H
L
H
F=A+B
F == (A + B) PLUS A
A
H
H
H
H
L
F
= A + B
F = (A + S) PLUS A
F = (A + S) PLUS A PLUS 1
H
H
H
F
=
F = A MINUS 1
F = A
SO
FUNCTIONS
= AB
A
=
MINUS 1 (2's COMP)
F = A PLUS AS
= (A + B) PLUS As
F
F
= (A + S) PLUS AB
= A PLUS A*
w
:>w
TABLE II
M=H
en
u
ACTIVE-HIGH DATA
SELECTION
II
=
=
(A + B) PLUS 1
(A + S) PLUS 1
F = ZERO
F
c
en
o
~
U
::I:
= A PLUS AS PLUS 1
F =(A + B) PLUS AS PLUS 1
F = A PLUS AB PLUS 1
F = (A + Sl PLUS AB PLUS 1
F = AB
F = A PLUS A PLUS 1
= (A + B) PLUS A PLUS 1
*Each bit is shifted to the next more significant position.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-153
II
J:
o
3:
o
C/)
o
m
<
om
C/)
3-154
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC190, SN54HC191, SN74HC190, SN74HC191
SYNCHRONOUS 4·81T UP/DOWN DECADE AND 81NARY COUNTERS
02684, DECEM8ER 1982-REVISED MARCH 1984
SN64HC190. SN64HC191 ... J PACKAGE
SN74HC190. SN74HC191 ... J oR N PACKAGE
(ToP VIEW)
•
Single Down/Up Count Control Line
•
Look·Ahead Circuitry Enhances Speed of
Cascaded Counters
•
Fully Synchronous in Count Modes
•
Asynchronously Presettable with Load
Control
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
description
s
Qs
QA
ClEN
DIU
Qc
Qo
GNO
VCC
A
ClK
RCO
MAXIMIN
lOAD
C
0
SN64HC190.SN64HC191 ., . FH OR FK PACKAGE
SN74HC190.SN74HC191 ., . FH oR FN PACKAGE
(TOP VIEW)
u
co u u
Ocoz>
w
9
00 U
ozz
(!)
NC -
0
U
C
No internal connection
The outputs of the four flip-flops are triggered
on a low-to-high-Ievel transition of the clock
input if the enable input (CTEN) is low. A high
at CTEN inhibits counting. The direction of the count is determined by the level of the downlup (DIU) input.
When % is low, the counter counts up and when DIU is high, it counts down.
en
o
:!
(.)
J:
These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and DIU)
that will modify the operating mode have no effect on the contents of the counter until clocking occurs.
The function of the counter will be dictated solely by the condition meeting the stable setup and hold times.
These counters are fully programmable; that is, the outputs may each be preset to either level by placing
a low on the load input and entering the desired data at the data inputs. The output will change to agree
with the data inputs independently of the level of the clock input. This feature allows the counters to be
used as modulo-N dividers by simply modifying the count length with the preset inputs.
Two outputs have been made available to perform the cascading function: ripple clock and maximuml
minimum count. The latter output produces a high-level output pulse with a duration approximately equal
to one complete cycle of the clock while the count is zero (all outputs low) counting down or maximum
(9 or 15) counting up. The ripple clock output produces a low-level output pulse under those same conditions
but only while the clock input is low. The counters can be easily cascaded by feeding the ripple clock
output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if
parallel enabling is used. The maximumlminimum count output can be used to accomplish look-ahead for
high-speed operation.
The SN54HC190 and SN54HC191 are characterized for operation over the full military temperature range
of -55°C to 125°C. The SN74HC190 and SN74HC191 are characterized for operation from -40°C
to 85°C.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
Copyright ©1982 by Texas Instruments Incorporated
3-155
TYPES SN54HC190, SN74HC190
SYNCHRONOUS 4·81T UP/DOWN DECADE COUNTERS
'HC190 logic symbol
2(CT-OIZ6
(12)
MAXIMIN
3(CT-9)Z6
(11
(21
(41
(81
'HC190 logic diagram (positive logic)
II
::I:
o
3:
ofA
C
m
S
o
m
fA
Pin numbers shown are for J and N packages.
3-156
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC191, SN74HC191
SYNCHRONOUS 4·BIT UP/DOWN BINARY COUNTERS
'HC191 logic symbol
CTRDIV16
1121
MAX/MIN
(1)
(2)
B
(4)
C
o
19
(8)
'HC191 logic diagram (positive logic)
1121
CTEN
DIU
141
7~~
151
1141
ClK
~
Ig
A
MAXIMIN
~
-
I
r
~ aC
.J
"l
-......
r
r
1
-
r~
-+~
LD
aD
---c>C1
10
-
~
::I:
H-L....,..I
___
L-_
~
(J
:1?rL 1
~s
~I>C1
18 -~~~
0
>
W
C
T
~
~~
0
1
~~80 r~l
"'l"
0
en
W
en
>---<:I>C1
1
II
0
1
~~~ aB
1
-
>C1
........,.
0
C
;-~ QA
~ ~~~
1
'--
RCO
(J
>---<
0
B
1131
r~~
'f
I
r
T
Pin numbers shown are for J and N packages.
TEXAS . .
INSTRUMENTS (
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-157
TYPES SN54HC190. SN74HC190
SYNCHRONOUS 4·81T UP/DOWN DECADE COUNTERS
typical load, count, and inhibit sequences
'HC190
Illustrated below is the following sequence:
1.
2.
3.
4.
Load (preset) to BCD seven.
Count up to eight, nine (maximum), zero, one, and two.
Inhibit.
Count down to one, zero (minimum), nine, eight, and seven.
I
L..
II
i
S..J
L.
DATA
INPUTS
J:
o
s:
o
tn
C
m
<
o
L..
r
D
I
CLOCK
I
- ----1--,1
DIU ____I___ !L.I_ _ _ _ _ _ _ _ _ _ _ _~
I
I I
__ ----1--71'
CTEN ___
m
tn
i
C..J
QA
J __ l..,;!I_ _ _ _ _ _ _ _ _ _~
:
___ ..J
I
II
l
QS----:--!l
r--I
QC----;--IlI ..i-~~-------~----~~~--------~·r--I
___ ...J
1 ...- - - - - - - - - - '
•
I
___ ...J
I'
L--iJ
----,
QD ____
~
I I
MAXIMIN
n
===J ::
'RcO----,
___ ...J
I I
:
7 I I
I
8
U..-I.-
u
9
,
0
-2
2
2
COUNT UP - - -..
·I-INH1S1T--I
LOAD
3-158
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
n
u
0
f.---
9
COUNT DOWN
8
7
~
TYPES SN54HC191, SN74HC191
SYNCHRONOUS 4·81T UP/DOWN 81NARY COUNTERS
typical load, count, and inhibit sequences
'HC191
Illustrated below is the following sequence:
Load (preset) to binary thirteen.
Count up to fourteen, fifteen (maximum), zero, one, and two.
Inhibit.
Count down to one, zero (minimum), fifteen, fourteen, and thirteen.
1.
2.
3.
4.
i:OA6--U
I
--
A..J
L_
B
rI
---
I
--
I
DATA
INPUTS
C..J
L-_
D-.J
L_
II
en
w
CJ
:>w
ClK
c
--- --,
Diu ___1_
I
'C'fEiii
1..1------------.. .
~-
-1- - ,
-
_ , _ - - ; 1":-,_ _ _ _- - - - - - - '
-
___ I
en
2
I
o
CJ
J:
"
1
I
I:
0B
==l..Jjr----_.....___--'
L
--I
Oc -__ ....J
00 -
-
I
- ---'
MAXIMIN
=-= ~I,-
_____-
U
I
·RCO __ ....J
L .
: 13
11'------__-----:-__- ......11'--------
....
14
15
0
2,
2
1
I,
U
I 2
I
0
I · - - - C O U N T U P - - -••.I-INHIBIT--I
I---
15
14 .
13
I
COUNT D O W N - - - -...
lOAD
TEXAS·.
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-159
TYPES SN54HC190. SN54HC191. SN74HC190. SN74HC191
SYNCHRONOUS 4·BIT UP/DOWN DECADE AND BINARY COUNTERS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
TA
MIN
fclock Clock frequency
i:OAo low
tw
Pulse duration
ClK high or low
•
Data before lOAD t
:I:
(')
s:o
CTEN before ClKt
SN54HC190
SN54HC191
= 25°C
MIN
SN74HC190
SN74HC191
MIN
2V
0
0
MAX
2.8
4.5 V
0
21
0
14
0
17
6V
0
24
16
0
19
0
2V
120
0
180
4.5 V
6V
24
21
36
31
30
26
2V
120
180
150
4.5 V
24
36
6V
21
2V
150
31
256
30
26
4.5 V
6V
30
25
46
2V
205
306
4.5 V
41
61
38
255
51
35
53
44
306
255
Diu before ClK t
4.5 V
6V
41
35
150
61
53
51
44
250
S
(')
lOAD inactive before ClK t
4.5 V
45
38
190
38
6V
30
25
2V
5
5
5
en
Data after lOAD t
4.5 V
5
5
5
6V
5
5
2V
5
5
5
4.5 V
6V
5
5
5
5
5
5
c
2V
m
m
th
Hold time
CrEN after ClK t
Diu after ClK t
3-160
5
2V
5
5
5
5
5
6V
5
5
5
5
TEXAS . .
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
ns
32
4.5 V
INSTRUMENTS
ns
38
32
205
en
MHz
188
2V
Setup time
MAX
3.3
150
6V
tsu
UNIT
MAX
4.2
ns
TYPES SN54HC190, SN54HC191, SN14HC190, SN14HC191
SYNCHRONOUS 4·BIT UP/DOWN DECADE AND BINARY COUNTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
lOAD
Any a
tpd
A. B.
C. or 0
aA.aB
aC. or aD
tpd
ClK
RCO
tpd
ClK
Any a
tpd
ClK
MAXIMIN
tpd
DIU
RCO
tpd
DIU
MAXIMIN
tpd
tt
CrEN
RCO
Any
TA - 25°C
vcc
2V
4.5 V
6V
2V
4.5 v
6V
2V
4.5 v
6V
2V
4.5 V
6V
2V
4.5 v
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
MIN
4.2
21
24
TYP MAX
8
42
48
130 264
40
53
45
33
135 240
36
48
30
41
58 120
17
24
14
21
107 192
31
38
26
32
123 252
39
50
32
43
102 228
46
29
24
38
86 192
24
38
20
32
50 132
15
26
13
23
38
75
8
15
6
13
SN54HC190
SN54HC191
MIN
MAX
2.8
14
16
396
79
67
360
72
61
180
36
31
288
58
49
378
76
65
342
68
59
288
58
49
198
40
34
110
22
19
SN74HC190
SN74HC191
UNIT
MIN
MAX
3.3
17
MHz
19
330
ns
66
56
300
ns
60
51
150
ns
30
26
240
48
ns
41
315
ns
63
54
285
57
ns
49
240
48
ns
41
165
33
ns
28
95
.19
ns
16
II
en
w
(J
>
W
c
en
o
~
(J
J:
50 pF typ
Power dissipation capacitance
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS
-I!I
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-161
II
J:
n
S
o
en
cm
~
m
n
en
3-162
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC192, SN54HC193
SN74HC192, SN74HC193
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
02684. DECEMBER 1982-REVISED MARCH 1984
SN54HC192. SN54HC193 .•. J PACKAGE
SN74HC192. SN74HC193 ••• J OR N PACKAGE
•
Look-Ahead Circuitry Enhances Cascaded
Counters
•
Fully Synchronous in Count Modes
•
Parallel Asynchronous Load for Modulo-N
Count Lengths
•
Asynchronous Clear
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
(TOP VIEW)
•
8
08
VCC
A
CLR
OA
DOWN
80
UP
Dependable Texas Instruments Quality and
Reliability
CO
L6A5
Oc
OD
GND
C
D
SN54HC192. SN54HC193 .•• FH OR FK PACKAGE
SN74HC192. SN74HC193 ••. FH OR FN PACKAGE
(TOP VIEW)
description
U
CD
U U
dCDZ><{
The 'HC192 and 'HC193 are synchronous,
reversible up/down counters. The 'HC192 is a
4-bit decade counter and the 'HC193 is a 4-bit
binary counter. Synchronous operation is
provided by having all flip-flops clocked
simultaneously so that the outputs change
coincidently with each other when so instructed
by the steering logic. This mode of operation
eliminates the output counting spikes normally
associated with asynchronous (ripple clock)
counters.
The outputs of the four flip-flops are triggered
by a low-to-high-Ievel transition of either count
(clock) input (Up or Down). The direction of
counting is determined by which count input is
pulsed while the other count input is high.
OA
DOWN
NC
II
CLR
en
w
80
NC
CO
LOAD
UP
Oc
00 U 0
dZZ
(.)
5>
w
c
U
en
(!)
o
NC-No internal connection
~
(.)
l:
All four counters are fully programmable; that is, each output may be preset to either level by placing a
low on the load input and entering the desired data at the data inputs. The output will change to agree
with the data inputs independently of the count pulses. This feature allows the counters to be used as
modulo-N dividers by simply modifying the count length with the preset inputs.
A clear input has been provided that forces all outputs to the low level when a high level is applied. The
clear function is independent of the count and the load inputs.
These counters were designed to be cascaded without the need for external circuitry. The borrow output
(80) produces a low-level pulse while the count is zero (all outputs low) and the count-down is low. Similarly,
the carry output (CO) produces a low-level pulse while the count is maximum (9 or 15) and the count-up
input is low. The counters can then be easily cascaded by feeding the borrow and carry outputs to the
'count-down and count-up inputs, respectively, of the succeeding counter.
The SN54HC192 and SN54HC193 are characterized for operation over the full military temperature range
of -55°C to 125°C. The SN74HC192 and SN74HC193 are characterized for operation from -40°C
to 85°C.
Copyright © 1982. Texas Instruments Incorporated
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-163
TYPES SN54HC192, SN74HC192
SYNCHRONOUS 4-81T UP/DOWN DECADE COUNTERS (DUAL CLOCK WITH CLEAR)
'HC192 logic symbol
CTRDIV10
CT=O
'HC192 logic diagram (positive logic)
L
I
lEI
CLR
UP
:r
DOWN
s:
LoAD
(")
A
0
tJ)
C
m
~
B
(")
v-
~
(5)
(4)
~
~
(15)
~=LJ
~ ::u
S~
......-< r>C1
1D
~
(11
~~
1
~ -~ rLl
......-C1
.-
(10)
7
.A.
"l
:u~=t...J
I
~~
~;- ~
~ :~ r~l
~>C1
~
;=u
D
r:
1~1
~;- ~
.-
C
(13)
"
(14)~
~
m
en
(12)
f
r-
I
(9)
~=L)
k-;- ~
-~~>Cl
rLF-J
~ S--pD- --
~
I
=LJ
~2
3-164
]
I
numbers shown are for J and N packages.
. . TEXAS.
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC193, SN74HC193
SYNCHRONOUS 4·81T UP/DOWN 81NARY COUNTERS (DUAL CLOCK WITH CLEAR)
'HC193 logic symbol
CTRDIV 16
CT"'O
(31
(2)
(6)
(7)
a
A
~B
C
aD
'HC193 logic diagrams (positive logic)
(12)
'~
r
CLR
(14) .....
~~
v
(5)
UP
DOWN
'LoAo
A
B
(41
lU
~
(15)
~
'"""~
.~.
~=t.J
o
BO
J>---
-.-
(.)
-;-~ aA
4..J
~
......,.
C1I
.~
1
J
II
en
w
~ >C1
~ FU
C
(13)
co
r:: 1D
T~l
T
~-;- ~ aB
~~r~1
~>C1
,.....,.
I
1
:>
W
C
en
0
:2
(.)
J:
1
(10)
"7 '"""~
(9)
4~~
~ ~~rL~
~t:>C1
~ R-J
"
'f
I
I
1
~~~;
'"""Ft--J'
I
......,.
c:u
I
1
1
Pin numbers shown are for J and N packages.
TEXAS
-I./}
INSTRUMENTS
POST OffiCE BOX 225012 • DALLAS. TEXAS 75265
3-165
TYPES SN54HC192, SN74HC192
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
'HC192 typical clear, load, and count sequence
Illustrated below is the following sequence:
1.
2.
3.
4.
Clear outputs to zero.
Load (preset) to BCD seven.
Count up to eight, nine, carry, zero, one, and two.
Count down to one, zero, borrow, nine, eight, and seven.
CLR
~~------------------------------, 1
LOAD --------~U
1 ,
A
B
II
DATA
-
-,-,--,--, --
I' 'I
I
UP
DOWN
C
1 1
I
-
-,-,--,-,--
-
-1-1--'-1--
- _I_,__ '_I_-J
-
-
-
-
I
m
-
-
-
-,---------------.,
,
r-----~
<
1
o
m
til
-- -- -- --
-_ _
- ,_
- ,_
- -_
- ,L...J._
-_-_-_-_
-_-_
-_-_
-_-_
-_
-_
- _-_
- __
__-__-__-_-_ __-__
_-_-_
_
o
s:
o
til
-- -- -- -- -- -- -- -- -- -- -
1 1
'I
C -_ _
-1
- - r IL
-- - -- -- -- -- -- -- -- -- -- -- -- -- -- _1_---1
____________________________
__
D
J:
1 1
'I
-1-'-,--,
--- --- -- --. -- -- -- -- -- -- -- -- -- -- -- -L
_____________________________
__
,I
I'
_ _ _ _ ....J L - ___________________________ __
- _ _ _ ---I
_
OUTPUTS
1
:1,
:1
:1
~
,
~
,
1
1
~
I
u
SEQUENCE
ILLUSTRATED
,
10
1
7
.
0
u
9
PRESET
NOTES: A. Clear overrides load. data. and count inputs.
B. When counting uP. count-down input must be high; when counting down, count-up input must be high.
3-166
8
'
71
r---COUNT DOWN ~
;--"---... ;--"---...
CLEAR
1
TEXAS
-I./}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC193. SN74HC193
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
'HC193 typical clear, load, and count sequences
Illustrated below is the following sequence:
1 . Clear outputs to zero.
2. Load (preset) to binary thirteen.
3. Count up to fourteen, fifteen, carry, zero, one, and two.
4. Count down to one, zero, borrow, fifteen, fourteen, and thirteen.
CLR
toA'6
~~----~------------------__________________________________
I
,
'
"
I
-------,U
I,
A
,_
-,,- _
- _
- _- _
- -_
- _-_
- _
-_
-_
-_
- _-_
- _
--__
_
.....J, -L.._
_
___
__
B
'- - - , , . - -_ _
- ,I
-,
-_
- __
-_
- _
-- -_-_ _- _ _- _ _
- __
- __
- _-__
_ _ L..J _ _ _ _-_
__
_-_-_
_-__
C
------,-,
--- ---_---_--_--_ _
--_- _-_ _
- _--_-_ _
--_-__ _ , _ , _ --' L
__
__
_-__
DATA
I'
I, "
II
=='='=~'-'L-- =______ ====-= ======
-,-,--,-,--
D
UP -
-
I
I
"
I
I
"
en
w
(.)
-,-1- -,-,-
,
>
W
c
en
o
L-
(.)
__'_I __ '_'_.J
DOWN -
-
-
-
"
,
-
-
-
-..-----------------------.,.......,
I
r-------.
J
QB :
lL.____
--.;....-I
=IL._----'
=IL.-_...I
I
OUTPUTS
Qc
QD
~
J:
,
,
"
ro---~--------~LJ
so
SEQUENCE
ILLUSTRATED
'
--,-,------------------------~LJ
10 I
1131 I
~ ~
CLEAR
r-14
15
0
1
21
COUNT UP - - - - ,
I
1
0
15
14
13
1
r---COUNT DOWN ~
PRESET
NOTES: A. Clear overrides load. data. and count inputs.
B. When counting up. count-down input must be high; when counting down. count-up input must be high.
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-167
TYPES SN54HC192, SN54HC193
SN74HC192, SN74HC193
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
vcc
fclock
Clock frequency
Pulse duration
11
LOAD low
UP or DOWN
high or low
::I:
(")
Data before
LOAD t
S
o
en
tsu
Setup time
c
m
CLR inactive before
UPt or DOWN t
LOAD inactive before
$
UPt or DOWNt
(")
m
en
Data after LOAD
th
Hold time
t
UP high after DOWN
DOWN high after UP
3-168
t
t
MAX
2V
0
4.2
0
6V
0
120
21
24
SN54HC192
SN74HC192
SN54HC193
MIN
MAX
2.8
0
SN74HC193
MIN
MAX
0
3.3
0
14
0
17
0
16
19
180
0
150
24
21
36
31
30
,26
2V
4.5 V
120
180
150
24
36
30
6V
21
26
6V
tw
MIN
4.5 V
2V
4.5 V
CLR high
TA = 25°C
2V
120
31
180
4.5 V
24
36
6V
2V
21
110
31
165
4.5 V
22
6V
19
33
28
2V
110
165
4.5 V
22
6V
2V
4.5 V
19
110
33
28
165
22
33
6V
19
28
2V
4.5 V
5
5
5
5
5
5
6V
2V
5
5
5
5
5
5
4.5 V
5
5
5
6V
5
5
5
2V
4.5 V
5
5
5
5
5
6V
5
5
5
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
UNIT
MHz
ns
150
30
26
140
28
24
140
28
ns
24
140
28
24
5
ns
TYPES SN54HC192, SN54HC193
SN74HC192, SN74HC193
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
tpd
tpd
tpd
UP
CO
DOWN
UP or
DOWN
BO
Any Q
TA = 25°C
VCC
MIN
LOAD
tt
CLR
Any Q
Any
MIN
MAX
MIN
4.2
8
2.8
3.3
21
24
55
60
14
16
17
19
UNIT
MAX
MHz
2V
4.5 V
75
24
165
250
205
33
41
6V
20
28
50
43
2V
75
165
250
205
4.5 V
6V
24
20
190
33
28
5q
43
41
35
250
375
315
50
43
75
64
63
54
260
390
325
52
44
78
66
65
55
240
360
300
72
60
2V
4.5 V
40
35
190
4.5 V
6V
40
35
170
2V
tpHL
SN74HC193
2V
6V
Any Q
MAX
SN74HC192
SN54HC193
4.5 V
6V
2V
tpd
TYP
SN54HC192
36
ns
35
4.5 V
6V
31
48
41
61
51
2V
38
75
110
95
4.5 V
6V
8
15
22
19
6
13
19
16
ns
ns
ns
II
(/)
ns
ns
W
CJ
:>w
c
(/)
Power dissipation capacitance
50 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
o
:E
CJ
J:
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-169
lEI
J:
n
S
oV)
C
m
!5
n
·m
V)
3-170
TYPES SN54HC194, SN74HC194
4·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
•
Parallel Inputs and Outputs
•
Four Operating Modes:
Synchronous Parallel Load
Right Shift
Left Shift
Do Nothing
SN54HC194 ... J PACKAGE
SN74HC194 ... J OR N PACKAGE
(TOP VIEW)
ClR
SR SER
VCC
OA
Os
Oc
OD
A
S
•
Positive Edge-Triggered Clocking
•
Direct Overriding Clear
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
C
ClK
S1
SO
D
Sl SER
GND
SN54HC194 ..• FH OR FK PACKAGE
SN74HC194 .•. FH OR FN PACKAGE
e:w
description
S
Os
Oc
NC
NC
C
GD
D
ClK
A
Parallel (broadside) load
Shift right (in the direction QA toward QD)
Shift left (in the direction QD toward QA)
Inhibit clocking (do nothing)
The SN54HC194 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC194 is
characterized for operation from - 40 °C to
85°C.
en
w
(J
>
W
C
en
o
e:ouo ...
wzzenen
en(!)
...J
en
2
(J
J:
NC-No internal connection
logic symbol
SRG4
Shift right is accomplished synchronously with
the rising edge of the clock pulse when SO is high
and S 1 is low. Serial data for this mode is entered
at the shift-right data input. When SO is low and
S 1 is high, data shifts left synchronously and
new data is entered at the shift-left serial input.
Clocking of the shift register is inhibited when
both mode control inputs are low.
II
Ie:
en
u
e:...JuuO
These bidirectional shift registers are designed
to incorporate virtually all of the features a
system designer may want in a shift register. The
circuit features parallel inputs, parallel outputs,
right-shift and left-shift inputs, operating-modecontrol inputs, and a direct overriding clear line.
The register has four distinct modes of operation,
namely:
Synchronous parallel loading is accomplished by
applying the four bits of data and taking both
mode control inputs, SO and S 1, high. The data
are loaded into the associated flip-flops and
appear at the outputs after the positive transition
of the clock input. During loading, serial data
flow is inhibited.
(TOP VIEW)
(15)
(14)
(13)
0
(12)
SL SER
OA
°B
Oc
00
Pin numbers shown are for J and N packages.
Copyright ©1982 by Texas Instruments Incorporated
4
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-171
TYPES SN54HC194, SN74HC194
4·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
logic diagram (positive logic)
aLR_(~1_)______~________q
ClK
so
~o---------------------------~
1"-..X>------y~-------~-------"'7"""------__.
(11)
{>o-
I'...
V
(9)
S1~~ r - - - - - : - - ----------.- r-l
SR SER
A
(2)
(3)
""
~
~-+----~I-a
THISOETAll
IS TYPICAL
OFAll4
MULTIPLEXERS
TG
X""~---~I~~~~~ ;>o-+---f6
V
~~
,~
II
:::E:
(')
s:
oVJ
L ________
$-
~TG
~_::-
~-;-~QA
..-f-<: >C1
.-+--iI-+--t-C1
2
o
1
D
(6)
1
3
Sl SER
(7)
~""'o---+--------------------------a 2
}MUX
G..Q.
3
0
~
Pin numbers shown are for J and N packages.
3-172
~ QC
~l
0
-
r--....cR
1
C (5)
~QB
..-'-C1
~-+-+---------------------+--~3
.-------------------r--qO
VJ
r---
~R
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
-
L.....oR
~
l-..-..C1
~l
QD
TYPES SN54HC194, SN74HC194
4·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
FUNCTION TABLE
INPUTS
MODE
CLEAR
~
X
X
H
L
L
H
H
H
H
H
L
H
H
H
H
L
CLOCK
X
X
H
H
H
L
L
L
X
L
LEFT RIGHT
X
X
X
t
t
X
X
t
t
t
H
L
X
X
OUTPUTS
SERIAL
X
X
X
H
L
X
X
X
PARALLEL
A
B
X
X
X
X
b
X
X
X
X
a
X
X
X
X
X
X
0
C
X
X
X
d
X
X
X
X
X
X
c
X
X
X
X
X
OA
OB
Oc
00
L
L
L
L
OAO OSO Oeo 000
a
b
c
d
H
OAn OSn OCn
L
OAn OSn OCn
H
OSn °Cn OOn
L
OSn °Cn OOn
OAn OSn OCn 000
typical clear, load, right-shift, left-shift, inhibit, and clear sequences
CLOCK
.
MODE
CONTROL
INPUTS
{so --J
S1
:
::Ji1. .--:--------------------!
I
CLEAR
-u:
,
SERIAL{ R
DATA
INPUTS
L
A
PARALLEL
DATA
INPUTS
II
~~I--~-----------------I
--
til
LI
r--l~__________~~---------------I~i.--~:--I
I
I
i l
I
~_~_______________________________________________________
I
,
I
B__~:~L~:---T--------------------~--------------~--------------~-C
,
I
I
,
II
:
L:
,
,
---L.fH!l~----------------------------------------------------_r--
D
1 . -__________________________- '
- -,!
r---,,--,
,....---,I...
1
L--.....J
1'-________________-'1
I
I
I
aC __
o
2
(.)
J:
L,
_ _ ..,
aB __
til
I
: I'
aA::~
OUTPUTS
>
W
C
--~,~,~~------------------~~~
,
w
(.)
~______________,..I_
,
--,
I
aD __
~-":"__-'
:
f+-
SHIFT RIGHT
---..J
SHIFT LEFT
CLEAR LOAD
...--
---t.~I
INHIBIT ---../
CLEAR
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
4
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-173
TYPES SN54HC194, SN74HC194
4·BI1 BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
vcc
fclock
Clock frequency
ClK high
or low
tw
Pulse duration
a:R low
::t
C')
tsu
Setup time. any input before ClK t
th
Hold time. data after ClK t
TA = 25°C
MIN
MAX
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
0
0
0
80
16
14
80
16
6V
2V
4.5 V
6V
2V
4.5 V
6V
14
100
20
17
6
31
36
SN54HC194
MIN
MAX
0
0
0
120
24
20
120
4.2
21
25
100
20
17
100
20
17
24
20
150
30
26
0
0
0
0
0
0
SN74HC194
MIN
MAX
0
5
0
25
0
29
UNIT
MHz
ns
125
25
21
0
0
0
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL ... 50 pF (see Note 1)
~
PARAMETER
o
en
FROM
(INPUT)
TO
(OUTPUT)
f max
C
m
S
tPHl
C')
a:R
Any
m
en
tpd
tt
Cpd
ClK
Any
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
TA = 25°C
MIN TYP MAX
6
31
36
67
17
14
67
17
14
28
150
30
26
145
29
25
75
8
6
15
13
4.5 V
6V
I
Power dissipation capacitance
SN54HC194
MAX
MIN
4.2
21
25
3-174
TEXAS
5
25
29
~
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS. TeXAS 75265
UNIT
MHz
190
225
45
'37
220
44
37
110
22
19
No load. TA = 25°C
NOTE 1: For load circuit and voltage waveforms. see page 1·14.
SN74HC194
MIN
MAX
38
32
180
ns
36
ns
.31
95
19
16
I
65 pF typ
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC195,SN74HC195
4·81T PARALLEL·ACCESS SHIFT REGISTERS
02684. DECEMBER 1982-REVISED MARCH 1984
•
Synchronous Parallel Load
•
Positive-Edge-Triggered Clocking
•
J and
•
Complementary Outputs from Last Stage
•
•
K Inputs to
SN54HC195 .•• J PACKAGE
SN74HC195 ••. J OR N PACKAGE
(TOP VIEW)
First Stage
ClR
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
1 U,6
J
2
15
K
3
14
4
5
12
A
B
r
C
D
GND
Dependable Texas Instruments Quality and
Reliability
description
bl VCC
13
6
11
7
10
8
9
OA
Os
Oc
°D
OD
ClK
SH/[5
SN54HC195 •.• FH OR FK PACKAGE
SN74HC195 .•• FH OR FN PACKAGE
These 4-bit registers feature parallel inputs,
parallel outputs, J-K serial inputs, shiftlload
control input, and a direct overriding clear. The
registers have two modes of operation: parallel
(broadside) load, and shift (in the direction OA
and 00).
(TOP VIEW)
5u ~<
.,uz>o
1
3
2
Os
Oc
A
Parallel loading is accomplished by applying the
four bits of data and taking the shift/load control
input low. The data is loaded into the associated
flip-flop and appears at the outputs after the
positive transition of the clock input. During
loading, serial data flow is inhibited.
NC
U)
NC
OD
S
C
W
C)
>
OD
9 1011 1213
W
C
o ~ ~19 ~
(!)
Shifting is accomplished synchronously when
the shift/load control input is high. Serial data for
this mode is entered at the J-K inputs. These
inputs permit the first stage to perform as a
J-K-, 0-, or T-type flip-flop as shown in the
function table.
II
1 2019
K
~u
U)
o
(/)
NC - No internal connection
~
(.)
logic symbol
::J:
The SN54HC195 is characterized for operation
over the full military temperature range of
- 55 °C to 125 DC. The SN74HC195 is
characterized for operation from - 40 DC to
85 D C.
Pin numbers shown are for J and N packages.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright -------t
lEI
l:
(')
s:o
en
cm
S
(')
m
en
Pin numbers shown are for J and N packages.
3-176
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC195, SN74HC195
4·81T PARALLEL·ACCESS SHIFT REGISTERS
FUNCTION TABLE
INPUTS
OUTPUTS
PARALLEL
SERIAL
CLR
sHiLi5
CLK
L
x
X
x x x
H
t
H
L
H
X
X
X
X
H
H
L
H
H
H
L
L
H
H
H
H
H
H
H
L
L
t
t
t
t
J
K
A
a
X
X
X
X
X
OA
OB
Oc
aD
x x
X
L
L
L
L
H
c
X
X
X
X
X
d
a
b
c
d
d
B
b
X
X
X
X
X
C
D
X °AO aBO QCO
X °AO QAO OBn
X
L
OAn QBn
X
H
QAn OBn
X OAn °An QBn
OD
QDO ODD
QCn
DCn
QCn
OCn
QCn
OCn
QCn
DCn
typical clear, shift, and load sequences
CLK
I
SERIAL {
J __~____~r-f-,L
INPUTS
K
____________________-+____~___________________
~L____________________~I____~___________________
SH/~D--~--------~--------------------~~~~--------------------
A __
PARALLEL
DATA
INPUTS
~
________
~
__________________
B
L
{
D
a
OUTPUTS .
I
(.)
I
I'"'j:i"IIL----+
____________________
c
L
--.,
I
1
I
A---~I------~r__'~-----------------~r--l~i----------------------
a B ----I
1 - - - - '~L -_____________1L-__
I
- - ..:.1--------.:...1
'"""1~L -_____________
ac ::---,
{
aD
,:::1
I
1
~
I
I...
:
SERIAL SHIFT----~
CLEAR
II
en
w
1
~~
__________
>
W
c
en
o
~
1
(.)
: . - - SERIAL SHIFT--.
J:
LOAD
absolute maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-177
TYPES SN54HC195, SN74HC195
4·81T PARALLEL·ACCESS SHIFT REGISTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
2V
4.5 V
Clock frequency
fclock
6V
2V
4.5 V
6V
2V
4.5 V
ClK high or low
Pulse duration
tw
ClR low
tsu
lEI
l:
n
s:
th
Setup time.
before ClK t
SH/lO. or serial and
parallel data. or
CLR inactive
Hold time.
after ClK t
sHieD or serial
and parallel data
6V
2V
4.5 V
TA = 25°C
MIN
MAX
0
6
0
31
0
80
16
14
36
80
16
14
100
20
17
6V
2V
4.5 V
6V
0
0
0
SN54HC195
MIN
MAX
0
4.2
0
21
0
25
120
24
20
120
24
20
150
30
26
0
0
0
SN74HC195
MIN
MAX
5
0
25
0
29
0
100
20
17
UNIT
MHz
ns
100
20
17
125
25
21
0
ns
ns
0
0
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
o
PARAMETER
o
FROM
(INPUT)
TO
(OUTPUT)
f max
2V
4.5 V
tpd
6V
2V
4.5 V
I
C
m
<
nm
VCC
ClK
QA thru Qo
or
CLR
QO
QA thru QO
or
2V
4.5 V
67
17
Any
6V
2V
4.5 V
13
28
8
6
.0
tpd
tt
TA =25°C
MIN TYP MAX
6
12
31
50
36
60
67
145
17
29
14
25
aD
6V
6V
Cpd
SN54HC195
MIN
MAX
4.2
21
25
150
30
26
75
15
13
38
110
22
19
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
UNIT
MHz
180
36
31
190
38
32
95
19
16
65 pF typ
Power dissipation capacitance
NOTE 1: For load circuit and voltage waveforms. see page 1·14.
3-178
220
44
37
225
45
SN74HC195
MIN
MAX
6
25
29
ns
ns
ns
TYPES SN54HC237, SN74HC237
3-LlNE TO 8-LlNE DECODERSIDEMULTIPLEXERS
WITH ADDRESS LATCHES
HIGH-SPEED
CMOS LOGIC
D2804, MARCH 1984
•
Combines Decoder and 3-Bit Address Latch
•
Incorporates 2 Output Enables to Simplify
Cascading
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC237 •.• J PACKAGE
SN74HC237 •.. J OR N PACKAGE
(TOP VIEW)
A
B
C
VCC
YO
Y1
Y2
Y3
Y4
Y5
Y6
Gl
<32
G1
Y7
GND
description
The 'HC237 is a three-line to eight-line decoder/
demultiplexer with latches on the three address
inputs. When the latch-enable (GL) is low, the
'HC237 acts as a decoder/demultiplexer. When
Gl goes from low to high, the address present
at the select inputs (A, B, and C) is stored in the
latches. Further address changes are ignored as
long as GL remains high. The output enable
controls, G1 and <32, control the outputs
independently of the select or latch-enable
inputs. All of the outputs are forced high if G1
is low or <32 is high. The 'HC237 is ideally suited
for implementing glitch-free decoders in strobed
(stored-address) applications in bus-oriented
systems.
SN54HC237 •.. FH OR FK PACKAGE
SN74HC237 ..• FH OR FN PACKAGE
(TOP VIEW)
•
U
u uo
m<{Z>>-
GI.
Y1
Y2
NC
NC
G2
Y3
Y4
C
G1
en
w
CJ
>
w
c
..... cu-ZZ>->-
o
19
The SN54HC237 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC237 is
characterized for operation from - 40°C to
85°C.
~
NC-No internal connection
CJ
J:
logic symbols (alternatives)
x/v
GL
0
A
B
DMUX
(14)
2
2
C
3
4
(13)
(12)
(11)
(10)
G1
G2
(15)
EN
5
(9)
6
(7)
7
GI.
VO
V1
A
V2
B
V3
C
:}G~
(15)
0
(14)
2
3
V4
4
V5
G1
V6
G2
V7
(13)
VO
V1
V2
(12) V3
(11\ V4
(10)
V5
5
6
(9) V6
(7)
7
V7
Pin numbers shown are for J and N packages.
TEXAS
-I!}
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-179
TYPES SN54HC237, SN74HC237
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES
logic diagram (positive logic)
(15)
VO
(14)
V1
(13) Y2
(12) V3
III
(11)
j---Y4
J:
("')
(10)
s:
oen
1---V5
(9) V6
c
m
<
G1..;.....;.---..,
t -_ _
(7_) Y7
("')
m
en
Pin numbers shown are for J and N packages.
FUNCTION TABLE
INPUTS
ENABLE
3-180
OUTPUTS
SELECT
GL
G1
G2
C
B
A
V1
L
V2
L
V3
V4
L
L
V5
L
V6
L
V7
X
VO
L
X
X
H
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
H
L
L
H
H
L
L
H
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
"H
H
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
H
L
H
L
L
L
L
L
H
L
L
H
L
H
H
L
L
L
L
L
L
H
L
L
H
L
H
H
H
L
L
L
L
H
H
L
X
X
X
L
L
L
I,.
L
L
H
Outputs corresponding to stored address, L;
all others, H
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC237, SN74HC237
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES
maximum ratings, recomme,nded operating conditions, and electrical characteristics
See Table IV, page 2·10.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
vcc
Pulse duration,
tw
Gt
low
Setup time, A, B, and C before
tsu
Hold time, A, 8, and C after
th
Gt t
GL t
TA = 25°C
MAX
MIN
SN54HC237
MIN
SN74HC237
MAX
MIN
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
75
115
95
4.5 V
15
23
19
6V
13
20
16
5
2V
5
5
4.5 V
5
5
5
6V
5
5
5
MAX
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF, (see Note 1)
PARAMETER
tpd
tpd
tpd
tpd
tt
FROM
(INPUT)
A,B, C
G2
Gl
ill.
TO
(OUTPUT)
Any
Any
Any
Any
Any
VCC
TA = 25°C
MIN
TVP MAX
SN74HC237
SN54HC237
MIN
MAX
MIN
MAX
285
240
38
57
48
32
48
41
66
145
220
181
18
29
44
36
2V
91
190
4.5 V
23
6V
17
2V
4.5 V
6V
13
25
37
31
2V
68
145
220
181
4.5 V
18
29
44
36
6V
14
25
37
31
2V
92
190
285
240
38
57
48
6V
24.
19
32
48
41
2V
38
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
4.5 V
Power dissipation capacitance
UNIT
II
en
w
(.)
ns
:>w
ns
en
c
ns
o
2
(.)
::E:
ns
ns
85 pF typ
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS
-Ii}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-181
lEI
:I:
(")
s:
o
rn
c
m
$
(")
m
rn
3-182
TYPES SN54HCT237, SN74HCT237
3·L1NE TO B·LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
HIGH·SPEED
CMOS LOGIC
02804, MARCH 1984
SN54HCT237 ••• J PACKAGE
SN74HCT237 , .. J OR N PACKAGE
•
Inputs are TTL-Voltage Compatible
•
Combines Decoder and 3-Bit Address Latch
•
Incorporates 2 Output Enables to Simplify
Cascading
(TOP VIEW)
A
B
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
description
The 'HCT237 is a three-line to eight-line
decoder/demultiplexer with latches on the three
address inputs. When the latch-enable input (GL)
is low, the 'HCT237 acts as a decoder/
demultiplexer. When GL goes from low to high,
the address present at the select inputs (A, B,
and C) is stored in the latches. Further address
changes are ignored as long as GL remains high.
The output enable controls, G 1 and <32, control
the outputs independently of the select or latchenable inputs. All of the outputs are forced high
if G1 is low or G2 is high. The 'HCT237 is ideally
suited for implementing glitch-free decoders in
strobed (stored-address) applications in busoriented systems.
VCC
YO
Y1
Y2
Y3
Y4
Y5
Y6
C
GL
G2
G1
Y7
GND
SN54HCT237 .•• FH OR FK PACKAGE
SN74HCT237 .•. FH OR FN PACKAGE
(TOP VIEW)
U
u Uo
II
CJ«Z>>3
2
1 2019
Y1
Y2
NC
Y3
Y4
C
GL
NC
(32
G1
C/)
W
CJ
>
w
9 10 111213
C
r--OU-zz>->-
C/)
l!)
o
NC-No internal connection
2
The SN54HCT237 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HCT237 is
characterized for operation from -40°C to
85°C:
CJ
J:
logic symbols (alternatives)
x/v
GL
OMUX
0
A
(14)
B
2
C
4
2
3
4
(13)
(12)
(11)
(10)
Gl
02
(15)
EN
5
(9)
6
(7)
7
vo
Vl
A
V2
B
V3
C
JG~
0
(15)
VO
Vl
2
3
V4
V5
Gl
V6
G2
V7
5
6
7
V7
Pin numbers shown are for J and N packages.
Copyright © 1984, Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS, TEXAS 75265
3-183
TYPES SN54HCT231, SN14HCT231
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES
logic diagram (positive logic)
II
}----'---'- Y 4
::r:
o
} - - - ' - - Y5
oen
)------'- Y6
3:
cm
<
om
en
G1-'--'------,
Y7
Pin numbers shown are for J and N packages.
FUNCTION TABLE
INPUTS
ENABLE
3-184
OUTPUTS
SELECT
B
A
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
C
X
X
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
L
L
L
L
L
L
H
L
L
H
H
L
L
L
H
L
L
L
L
L
H
L
H
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
L
.L
L
L
L
L
H
L
H
L
H
H
L
L
L
L
L
L
L
H
L
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H
H
L
X
X
X
GL
G1
G2
X
X
X
H
L
X
L
H
L
Output corresponding to stored address, L;
all others, H
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
L
TYPES SN54HCT237, SN74HCT237
3-L1NE TO B-L1NE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES
maximum ratings, recommended operating conditions, and electrical characteristics
See Table VIII, page 2-15.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
vCC
Pulse duration,
tw
tsu
th
4.5 V
Gi. low
Setup time, A, B. and C before
Hold time, A, B, and C before
GL t
GL t
TA = 25°C
MIN
MAX
26
SN54HCT237
MIN
39
SN74HCT237
MAX
MIN
33
5.5 V
4.5 V
23
35
30
15
23
19
5.5 V
14
21
17
4.5 V
5
5
5
5.5 V
5
5
5
MAX
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL ... 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A. B.C
Any
tpd
<32
Any
tpd
G1
Any
tpd
m:
Any
tt
Any
VCC
TA = 25°C
MIN TYP MAX
4.5 V
24
5.5 V
4.5 V
20
SN54HCT237
MIN
MAX
SN74HCT237
MIN
MAX
48
38
34
UNIT
29
5.5 V
19
16
57
51
44
26
40
32
4.5 V
19
29
44
36
5.5 V
16
26
40
32
4.5 V
29
25
42
63
. 57
52
47
ns
22
20
19
17
ns
5.5 V
4.5 V
12
11
5.5 V
Power dissipation capacitance
36
15
14
No load. TA = 25°C
43
36
85 pF typ
ns
ns
ns
II
en
w
(.)
:>
w
C
en
2
(.)
o
:I:
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-185
II
::I:
(")
s:
o
en
c
m
~
(")
m
en
3-186
HIGH-SPEED
CMOS LOGIC
TYPES SN54HC23B. SN74HC23B
3-LlNE TO B-LlNE DECODERS/DEMULTIPLEXERS
02804. MARCH 1984
•
•
SN54HC238 ..• J PACKAGE
SN74HC238 ••. J OR N PACKAGE
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
(TOP VIEW)
A
8
Incorporates 3 Enable Inputs to Simplify
Cascading and/or Data Reception
VCC
YO
Y1
Y2
Y3
Y4
C
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
description
The 'HC238 circuit is designed to be used in
high-performance memory-decoding or datarouting applications requiring very short
propagation delay times. In high-performance
memory systems this decoder can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a
fast enable circuit, the delay times of this
decoder and the enable time of the memory are
usually less than the typical access time of the
memory. This means that the effective system
delay introduced by the decoder is negligible.
The conditions at the binary select inputs and the
three enable inputs select one of eight input
lines. Two active-low and one active-high enable
inputs reduce the need for external gates or
inverters when expanding. A 24-line decoder can
be implemented without external inverters and
a 32-line decoder requires only one inverter. An
enable input can be used as a data input for
demultiplexing applications.
G2A
G28
G1
Y7
GND
Y5
Y6
SN54HC238 .•. FH OR FK PACKAGE
SN74HC238 •.. FH OR FN PACKAGE
(TOP VIEW)
U
U
uo
II
CD~z>>-,
G2A
Y1
Y2
NC
NC
G28
G1
Y3
Y4
C
en
w
(J
:>w
c
"OUCCIO
en
>-zz>->-
o
(.!)
NC-No internal connection
:!
(J
::r:
The SN54HC238 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC238 is
characterized for operation from - 40°C to
85°C.
Copyright © 1984 by Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-187
TYPES SN54HC23B, SN74HC23B
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
logic symbols (alternatives)
BIN/OCT
A (1)
B (2)
DMUX
(15) YO
o
A (1)
(14) Y1
B (2)
(13) Y2
C (3)
2
C (3)
2
4
(12) Y3
3
Jot
(11)
4
Y4
(10) Y5
&
(9)
6
(15) VO
0
2
4
V4
(10) Y5
6
Y6
Y7
Y7
Pin numbers shown are for J ar'!d N packages.
BIOglC diagram (positive logic)
VO
J:
A
("')
(1)
s:
V1
0
B (2)
rJ)
V2
C
m
C
<
(3)
V3
("')
m
V4
rJ)
V5
G1 (6)
V6
G2A (4)
V7
G3A (5)
Pin numbers shown are for J and N packages.
3-188
(9) Y6
(7)
(7)
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC23B. SN74HC23B
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
FUNCTION TABLE
ENABLE
G1
SELECT
INPUTS
G2A G2B
X
X
L
H
H
H
H
H
H
H
H
H
X
X
H
X
L
L
L
L
L
L
L
X
L
L
L
L
L
L
L
L
L
INPUTS
B
A
X
X
X
X
X
X
X
L
L
L
C
X
X
L
L
L
H
H
H
H
H
L
H
L
H
L
H
L
H
H
L
L
H
H
OUTPUTS
VO
L
L
L
H
L
L
L
L
L
L
L
V1
L
L
L
L
H
L
L
L
V2
L
L
L
L
L
H
L
L
L
L
L
L
L
L
V3
L
V4
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
V5
L
V6
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
V7
L
L
L
L
L
L
L
L
H
L
L
L
L
H
II
maximum ratings. recommended operating conditions. and electrical characteristics
See Table IV, page 2-10.
en
switching characteristics over recommended operating free·air temperature range
(unless otherwise noted). CL = 50 pF (see Note 1)
PARAMETER
tpd
tpd
tt
FROM
(INPUT)
A. B. or C
Enable
TO
(OUTPUT)
Any
Any
Any
vcc
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
TA = 25°C
MIN
TVP MAX
67
180
20
36
15
31
60
17
13
38
8
6
6V
SN54HC238
MIN
MAX
1,55
31
26
75
15
13
Power dissipation capacitance
270
54
46
235
47
40
110
22
19
MIN
w
(,J
SN74HC238
MAX
225
45
UNIT
ns
38
195
39
33
95
19
ns
>
W
c
en
o
~
(,J'
J:
ns
16
85 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-189
II
:I:
(')
3:
o
rn
c
m
<
n
m
rn
3-190
TYPES SN54HCT238. SN74HCT238
3·L1NE TO 8·L1NE DECODERS/DEMULTIPLEXERS
HIGH·SPEED
CMOS LOGIC
02804, MARCH 1984
•
Inputs are TTL·Voltage Compatible
•
Designed Specifically for High·Speed
Memory Decoders and Data Transmission
Systems
•
Incorporates 3 Enable Inputs to Simplify
Cascading and/or Data Reception
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
SN54HCT238 ••• J PACKAGE
SN74HCT238 ••• J OR N PACKAGE
(TOP VIEW)
A
Vee
B
YO
Y1
Y2
Y3
Y4
Y5
Y6
e
G2A
G2B
G1
Y7
GND
Dependable Texas Instruments Quality and
Reliability
SN54HCT238 .•• FH OR FK PACKAGE
SN74HCT238 .•• FH OR FN PACKAGE
(TOP VIEW)
description
The 'HCT238 circuit is designed to be used in
high-performance memory-decoding or datarouting applications requiring very short
propagation delay times. In high-performance
memory systems this decoder can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a
fast enable circuit, the delay times of this
decoder and the enable time of the memory are
usually less than the typical access time of the
memory. This means that the effective system
delay introduced by the decoder is negligible.
U
U
Uo
II
m«z>>-
e
4
G2A
5
Ne
6
G2B
7
G1
8
en
w
o
:>w
c
en
o
The conditions at the binary select inputs and the
three enable inputs select one of eight input
lines. Two active-low and one active-high enable
inputs reduce the need for external gates or
inverters when expanding. A 24-line decoder can
be implemented without external inverters and
a 32-line decoder requires only one inverter. An
enable input can be used as a data input for
demultiplexing applications.
~
NC-No internal connection
o
J:
The SN54HCT238 is characterized for operation
over the full military temperature range of
....: 55°C to 125°C. The SN74HCT238 is
characterized for operation from - 40°C to
85°C.
Copyright © 1984 by Texas Instruments Incorporated
-I!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-191
TYPES SN54HCT23B. SN74HCT23B
3·L1NE TO B·L1NE DECODERS/DEMULTIPLEXERS
logic symbols (alternatives)
BIN/OCT
DMUX
A (1)
(15) YO
A (1)
B (2)
(14) Y1
B (2)
(13) Y2
c
c
2
(3)
2
3
4
5
0
J-%
(14) Y1
2
(13) Y2
Y3
3
(12) Y3
Y4
(10) Y5
4
(12)
(3)
(11)
(9)
EN
6
Y6
7
illOgiC diagram (positive logic)
J:
YO
s:
til
C
B (2)
<
c
(1)
Y1
0
Y2
m
(3)
Y3
n
m
Y4
til
Y5
G1 (6)
Y6
G2A (4)
Y7
G3A (5)
Pin numbers shown are for J and N packages.
3-192
Y4
(10) Y5
(9) Y6
Y7
Y7
Pin numbers shown are for J and N packages.
A
(11)
(7)
(7)
n
(15) YO
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HCT23B, SN74HCT23B
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
FUNCTION TABLE
SELECT
ENABLE
INPUTS
OUTPUTS
INPUTS
G1
G2A
G2B
C
B
A
VO
V1
V2
V3
V4
V5
V6
X
H
X
X
X
L
L
L
L
L
L
L
L
X
X
X
H
X
X
X
L
L
L
L
L
L
L
L
L
X
L
X
X
L
L
L
L
L
L
L
L
L
X
L
X
H
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
H
L
H
L
L
L
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
L
L
H
L
L
H
L
L
L
L
L
L
H
L
L
L
H
L
L
H
L
H
L
L
L
L
L
H
L
L
H
L
L
H
H
L
L
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
L
L
L
L
L
H
V7
II
maximum ratings, recommended operating conditions, and electrical characteristics
See Table VIII, page 2-15.
en
switching characteristics over recommended operating free-air temperature range
(unless otherwise noted), CL = 50 pF, (see Note 1)
PARAMETER
tpd
tpd
tt
FROM
TO
(INPUT)
(OUTPUT)
A. B. or C
Enable
Any
Any
Any
SN54HCT238
w
O-
SN74HCT238
VCC
TA = 25°C
MIN
TVP MAX
4.5 V
21
36
54
45
5.5 V
18
32
49
41
4.5 V
21
33
50
42
MIN
MAX
MIN
MAX
5.5 V
17
30
45
38
4.5 V
11
15
22
19
5.5 V
9
14
20
17
Power dissipation capacitance
UNIT
ns
ns
ns
s:w
c
en
o
:E
o
J:
85 pF typ
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-193
lEI
::I:
n
~
orJ)
C
m
S
n
m
rJ)
3-194
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC239, SN74HC239
DUAL 2·LlNE TO 4·LlNE DECODERS/DEMULTIPLEXERS
02804. MARCH 1984
•
SN54HC239 ... J PACKAGE
SN74HC239 ••• J OR N PACKAGE
Designed Specifically for High·Speed
Memory Decoders and Data Transmission
Systems
•
Incorporates 2 Enable Inputs to Simplify
Cascading and/or Data Reception
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instrumentss 'Quality and
Reliability
(TOP VIEW)
1<3
1A
1B
1YO
1Y1
1Y2
1Y3
VCC
2(3
2A
2B
2YO
2Y1
2Y2
2Y3
GND
description
SN54HC239 ... FH OR FK PACKAGE
SN74HC239 ..• FH OR FN PACKAGE
The 'HC239 circuit is designed to be used in
high-performance memo~y-decoding or datarouting applications requiring very short
propagation delay times. In high-performance
memory systems, this decoder can be used to
minimize tHe effects of system decoding. When
employed with high-speed memories utilizing a
fast-enable circuit, the delay times of this
decoder and the enable time of the memory are
usually less than the typical access time of the
memory. This means that the effective system
delay introduced by the decoder is negligible.
(TOP VIEW)
« It!)
U
U
Ult!)
II
'-'-Z>N
1B
1YO
2A
2B
NC
1Y1
1Y2
NC
2YO
2Y1
(IJ
W
(J
:>w
c
The 'HC239 is comprised of two individual twoline to four-line decoders in a single package. The
active-low enable input can be used as a data
line in demultiplexing applications. These
decoders/demultiplexers feature fully buffered
inputs, each of which represents only one
normalized load to its driving circuit.
(IJ
o
~
NC - No internal connection
(J
J:
The SN54HC239 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN74HC239 is characterized for operation from -40°C to 85°C.
logic symbols (alternatives)
'X/Y
1A (2),
18 (3)
(4) 1Y0
0
(5) 1Y1
2
EN
DMUX
1A (2)
18 (3)
O} 0
1
G3
o
(4)1YO
(5)1Y1
(6) 1Y2
2
(7) 1Y3
3
(12 2YO
(11) 2Y1
(10) 2Y2
(9) 2Y3
Pin numbers shown are for J and N packages.
Copyright
TEXAS •
INSTRUMENTS
POST OFFiCe BOX 225012 • DALLAS. TeXAS 75265
© 1984. Texas Instruments Incorporated
3-195
TYPES SN54HC239. SN74HC239
DUAL 2·LlNE TO 4·LlNE DECODERS/DEMULTIPLEXERS
logic diagram (positive logic)
(2)
SELECT
1A
INPUTS
18 (3)
{
II
J:
DATA
OUTPUTS
Pin numbers shown are for j and N packages.
FUNCTION TABLE
(")
~
INPUTS
ENABLE
SELECT
o
en
c
m
G
B
H
OUTPUTS
VO
L
V1
L
V2
L
V3·
X
A
X
<
L
L
L
H
L
L
L
L
L
H
L
H
L
L
L
H
L
L
L
H
L
m
L
H
H
L
L
L
H
(")
en
L
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2·10.
switching characteristics over recommended operating free·air temperature .range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tpd
tpd
Cpd
FROM
(INPUT)
A or B
G
TO
(OUTPUT)
vCC
TA = 25°C
MIN
TVP MAX
SN54HC239
MIN·
MAX
MAX
62
150
V
2V
4.5 V
18
30
225
45
14
26
38
38
32
V
6V
2V
4.5 V
53
14
120
24
180
36
150
30
6V
11
20
31
26
2V
4.5 V
38
75
15
110
8
6V
6
13
95
19
16
Y
Power dissipation capacitance per decoder
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
3-196
SN74HC239
MIN
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265
22
19
UNIT
190
25 pF typ
ns
ns
ns
TYPES SN54HC240, SN54HC241, SN74HC240, SN74HC241
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02684, DECEMBER 1982-REVISED MARCH 1984
•
3-State Outputs Drive Bus Lines or
Buffer Memory Address Retgisters
•
High-Current Outputs Drive up to 15
LSTTL Loads
•
Package Options Include Both Plastic
and Ceramic Chip Carriers in Addition to
Plastic and Ceramic DIPs
•
Dependable Texas Instruments Quality
and Reliability
SN64HC' ... J PACKAGE
SN74HC' ..• J OR N PACKAGE
ITOPVIEW)
Vee
10
1A1
2Y4
1A2
2Y3
lA3
2Y2
lA4
2Yl
description
2Gf2G*
1Y1
2A4
1Y2
2A3
lY3
2A2
lY4
2Al
GND
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of three-state memory address drivers,
clock drivers, and bus-oriented receivers and
.transmitters. The designer has a choice of
selected combinations of inverting and
noninverting outputs, symmetrical G (active-low
output control) inputs, and complementary G
and G inputs. These devices feature high fanout.
SN64HC' ... FH OR FK PACKAGE
SN74HC' ... FH OR FN PACKAGE
ITOPVIEW)
II
The SN54HC' family is characterized for
operation over the full military temperature range
of - 55°C to 125°C. The SN74HC' family is
characterized for operation from - 40°C to
85°C.
en
w
1Yl
2A4
lY2
2A3
lY3
2Y3
lA3
2Y2
lA4
(J
5>
w
c
en
o
~
logic symbol
(J
*2G for 'HC240, or 2G for 'HC241
'HC240
:t
'HC241
lG
1A1
1A2
1A3
1A4
1Y1
lY2
lY3
1Y4
lAl
lA2
lA3
lA4
2(;
2A1
2A2
2A3
2A4
1Yl
1Y2
1Y3
1Y4
2G
2Yl
2Y2
2Y3
2Y4
2Al
2A2
2Yl
2Y2
2A3
2A4
2Y3
2Y4
Copyright ©1982 by Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TeXAS 75265
3-197
TYPES SN54HC240, SN54HC241, SN74HC240, SN74HC241
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
FUNCTION TABLES
'HC240
'HC241
'HC241
(EACH BUFFER)
(EACH BUFFER IN FIRST SET)
(EACH BUFFER IN SECOND SET)
INPUTS
OUTPUT
INPUTS
INPUTS
OUTPUT
OUTPUT
G
A
Y
lG
lA
1Y
2G
2A
2Y
L
H
L
L
H
H
H
H
H
L
H
L
H
L.
L
L
L
L
X
Z
H
X
Z
H
L
X
Z
logic diagrams (positive logic)
'HC240
113
III
lAl
'HC241
(1)
(2)
113
(18)
1Yl
lAl
lY2
lA2
1Y3
1A3
1Y4
lA4
(1)
(2)
(18)
(4)
(16)
(6)
(14)
(8)
(12)
1Yl
::I:
n
S
lA2
(4)
(16)
1Y2
0
rn
C
lA3
(6)
(14)
lY3
m
<
n
m
rn
lA4
213
2Al
2A2
2A3
2A4
3-198
(8)
(12)
(19)
(11)
(13)
(15)
(17)
2G
(9)
(7)
(5)
(3)
2Yl
2Al
2Y2
2A2
2Y3
2A3
2Y4
2A4
TEXAS
1Y4
(19)
(11)
(9)
(13)
(7)
(15)
(5)
(17)
(3)
~
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265
2Yl
2Y2
2Y3
2Y4
TYPES SN54HC240, SN74HC240
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted),
CL - 50
pF (see Note
1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
G
Y
tdis
G
Y
vcc
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
Y
tt
TA = 25°C
MIN TYP MAX
50
100
10
20
21
28
30
26
60
30
25
225
45
38
225
45
38
SO
8
6
12
10
18
15
S
75
15
13
44
22
4.5 V
6V
Power dissipation capacitance per buffer
SN54HC240
MIN
MAX
150
17
150
30
26
150
No load, TA = 25°C
SN74HC240
MIN
MAX
125
25
21
1S0
38
32
1S0
38
32
75
15
13
UNIT
ns
ns
ns
II
ns
en
w
35 pF typ
(.)
I
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted),
CL - 150
pF (see Note
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
tt
G
1)
Vcc
Y
2V
4.5 V
6V
2V
4.5 V
Y
6V
2V
4.5 V
TA = 25°C
MIN TYP MAX
75
150
15
30
26
13
100
20
17
45
17
13
6V
200
40
34
210
42
36
SN54HC240
MIN
MAX
225
45
38
300
60
51
315
63
53
SN74HC240
MIN
MAX
190
38
32
250
50
43
265
53
45
5>
w
c
en
UNIT
o
ns
(.)
~
J:
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS
'1.!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-199
TYPES SN54HC241, SN74HC241
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
'maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
SN54HC241
MIN
MAX
39
115
170
145
12
23
34
29
6V
11
20
29
25
190
FROM
(INPUT)
TO
(OUTPUT)
vCC
2V
tpd
A
Y
4.5 V
ten
tdis
G or G
G or G
Y
Y
tt
:::I:
Y
SN74HC241
TA = 25°C
MIN
TYP MAX
PARAMETER
MIN
2V
60
150
225
4,5 V
17
30
45
38
6V
15
40
26
32
150
38
225
18
30
45
38
6V
17
26
38
32
75
2V
4,5 V
UNIT
ns
ns
190
2V
28
60
90
4.5 V
8
12
18
15
6V
6
10
15
13
ns
ns
35 pF typ
Power dissipation capacitance per buffer
(')
MAX
s:
o
rn
cm
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
,
S
PARAMETER
FROM
(INPUT)
(OUTPUT)
TO
tpd
A
Y
(')
m
rn
ten
tt
Gor G
Y
Y
VCC
TA = 25°C
MIN
TYP MAX
SN54HC241
MIN
MIN
MAX
2V
50
165
245
210
4,5 V
16
33
49
42
6V
14
28
42
35
2V
4,5 V
100
200
40
300
250
20
60
50
6V
17
34
51
43
265
2V
45
210
315
4.5 V
17
42
63
53
6V
13
36
53
45
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
3-200
SN74HC241
MAX
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
UNIT
ns
ns
ns
TYPES SN54HCT240, SN54HCT241, SN74HCT240, SN74HCT241
OCTAL BUFFERS AND LINE DRIVERS CMOS LOGIC
WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02804, MARCH 1984
SN54HCT' ... JPACKAGE
SN74Hcr ... J OR N PACKAGE
•
Inputs are TTL·Voltage Compatible
•
3·State Outputs Drive Bus Lines or Buffer
Memory Address Registers
•
(TOP VIEW)
High-Current Outputs Drive up to 15 LSTTL
Loads
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
Vee
113
1A1
2G/2G*
1Yl
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A'l
2Y3
1A3
2Y2
1A4
2Y1
GND
description
SN54Hcr ... FH OR FK PACKAGE
SN74Hcr ... FH OR FN PACKAGE
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of three-state memory address drivers, clock
drivers, and bus-oriented receivers and transmitters.
The designer has a choice of selected combinations
of inverting and noninverting outputs, symmetrical G
(active-low
output
control)
inputs,
and
complementary G and Ginputs. These devices feature
high fan-out.
(TOP VIEW)
II
b
'-
u~
UIN
3
2Y3
1A3
2Y2
1A4
The SN54HCT' family is characterized for operation
over the full military temperature range of - 55°C to
125°C. The SN74HCT' family is characterized for
operation from - 40°C to 85 DC.
<{ 1c.:;J
2
1 2019
1Y1
2A4
1Y2
2A3
lY3
5
6
7
8
9 10 111213
en
w
(J
>
W
c
en
o
* 2<3 for 'HCT240, or 2G for 'HCT241
2
(J
::I:
logic symbols
'HCT240
'HCT241
1(;
lAl
lA2
lA3
lA4
lY1
lY2
lY3
1Y4
lAl
lA2
lA3
lA4
2G
2A1
2A2
2A3
2A4
1Yl
lY2
lY3
lY4
2G
2Y1
2Y2
2Y3
2Y4
2Al
2A2
2A3
2A4
TEXAS
-111
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
2Yl
2Y2
2Y3
2Y4
3-201
TYPES SN54HCT240, SN54HCT241, SN74HCT240, SN74HCT241
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
FUNCTION TABLES
'HCT240
(EACH BUFFER)
INPUTS
G
'HCT241
OUTPUT
L
A
H
L
H
L
L
H
X
Z
'HCT241
(EACH BUFFER IN SECOND SET)
(EACH BUFFER IN FIRST SET)
INPUTS
Y
1G
L
INPUTS
2G
H
L
L
X
Z
H
L
H
L
H
OUTPUT
1Y
H
1A
2A
H
OUTPUT
2Y
H
L
L
X
Z
logic diagram (positive logic)
'HCT240
1~
II
:I:
1A1
(')
1A2
3:
en
1A3
0
'HCT241
(1)
1~
(2)
(18)
(4)
(16)
(6)
(14)
(8)
(12)
1Y1
1A1
1V2
1A2
1V3
1A3
1V4
1A4
(1)
(2)
(18)
(4)
(16)
(6)
.(14)
(8)
(12)
1Y1
1Y2
1Y3
C
m
S
(')
1A4
1Y4
m
en
2~
2A1
2A2
2A3
2A4
3-202
(19)
2G
(11)
(9)
(13)
(7)
(15)
(5)
(17)
(3)
2Y1
2A1
2Y2
2A2
2Y3
2A3
2Y4
2A4
TEXAS
(19)
(11)
(9)
(13)
(7)
(15)
(5)
(17)
(3)
'1!1
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS, TeXAS 75265
2Y1
2Y2
2Y3
2Y4
TYPES SN54HCT240, SN54HCT241, SN74HCT240, SN74HCT241
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table VII, page 2-14.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
ten
G or
G
y
tdis
G orG
y
Y
tt
vcc
TA = 25°C
MIN
TYP MAX
4.5 V
5.5 V
13
12
25
23
4.5 V
21
5.5 V
4.5 V
SN54HCT240
SN54HCT241
MIN
MAX
37
SN74HCT240
SN74HCT241
MIN
UNIT
MAX
32
33
29
35
53
44
19
19
32
35
48
53
40
44
5.5 V
18
32
48
40
4.5 V
8
7
12
18
15
ns
ns
ns
ns
~~~~~~-----,II
5.5 V
Power dissipation capacitance per buffer
11
16
14
No load, T A = 25°C
40 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
tt
G or
G
y
Y
VCC
4.5 V
TA = 25°C
MIN
TYP MAX
20
42
SN54HCT240
SN74HCT240
SN54HCT241
SN74HCT241
MIN
MAX
63
MIN
5.5 V
19
38
56
4.5 V
25
52
79
65
5.5 V
22
47
71
59
4.5 V
17
42
63
53
5.5 V
14
38
57
48
w
UNIT
:>w
ns
en
MAX
53
48
en
(J
ns
c
o
~
(J
ns
J:
Note 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-203
II
:I:
o
!:
o
en
c
m
S
o
m
en
3-204
TYPES SN54HC242, SN54HC243
SN74HC242, SN74HC243
QUADRUPLE BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02684, DECEM8ER 1982-REVISED MARCH 1984
•
2·Way Asynchronous Communication
Between Data Buses
•
High·Current Outputs Can Drive up to 15
LSTTL Loads
SN54HC242, SN54HC243 ... J PACKAGE
SN74HC242, SN74HC243 ••. J OR N PACKAGE
(TOP VIEW)
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Cermic DIPs
•
Dependable Texas Instruments Quality and
Reliability
description
These four-data line transceivers are designed
for asynchronous two-way communications
between data buses. The SN74HC' devices can
be used to drive terminated lines down to 133
ohms.
These parts differ from their TTL counterparts
(LS, ALS, and AS) in that these CMOS parts do
not have a bus-latching mode in which both the
outputs are simultaneously enabled. Instead of
this latched mode, the buses are isolated, thus
preventing potential bus conflicts if both buses
are active. However, with the exception of the
fourth line of the function table, their functional
operation is identical to their TTL counterparts.
The two enables have been renamed G 1 and G2
since they work together to determine the
direction of transmission rather than each enable
controlling one direction independently of the
other. Whenever G1 and G2 are at opposite logic
levels with respect to each other, isolation
between buses results.
G1
NC
A1
A2
A3
A4
GND
VCC
G2
NC
81
82
83
84
SN54HC242, SN54HC243 .•• FH OR FK PACKAGE
SN74HC242, SN74HC243 ... FH OR FN PACKAGE
(TOP VIEW)
U
U .... U UN
Z(!)Z>(!)
A1
NC
A2
NC
A3
II
NC
NC
en
w
B1
NC
U
B2
>
w
c
en
o
NC-No internal connection
~
U
J:
The SN54HC' family is characterized for
operation over the full military temperature range
of -55°C to 125°C. The SN74HC' family is
characterized for operation from - 40°C to
85°C.
FUNCTION TABLE
INPUTS
'HC242
'HC243
A to B
A to B
G1
L
H
G2
L
H
Bto A
B to A
H
L
Isolation
Isolation
L
H
Isolation
Isolation
Copyright © 1982, Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-205
TYPES SN54HC242, SN54HC243
SN74HC242, SN74HC243
QUADRUPLE BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
logic symbol
logic diagrams (positive logic)
'HC242
'HC242
(1)
G1
G2
A1
A2
A3
A4
(13)
G1
(3)
(11)
(4)
J:
G2
(10) 82
A1
(5)
(9)
(6)
(8) 84
II
('")
81
83
'HC243
G1
(1)
s:
0
G2 (13)
C
A1
<
A2
tJ)
A3
A3
G1
G2
tJ)
m
(=;
m
A4
(3)
(11)
(4)
(10)
(5)
(9)
(6)
(8)
81
'HC243
82
83
84
Pin numbers shown are for J and N packages.
3-206
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC242, SN54HC243
SN74HC242, SN74HC243
QUADRUPLE BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
TA .. 25°C
vCC
MIN
2V
tpd
ten
Gl or G2
A or B
4.5 V
6V
2V
4.5 V
6V
tdis
Gl or G2
A or B
2V
4.5 V
6V
2V
A or B
tt
SN54HC242
SN74HC242
SN54HC243
MIN
MAX
SN74HC243
UNIT
TYP
MAX
45
12
100
20
10
17
75
21
17
150
30
26
48
150
38
225
23
20
30
45
38
26
32
28
13
MIN
MAX
150
125
30
26
25
225
45
190
4.5 V
8
60
12
38
90
18
6V
6
10
15
ns
21
38
32
ns
190
75
15
Power dissipation capacitance per transceiver
ns
II
ns
en
w
(.)
34pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
VCC
MIN
TYP
MAX
150
4.5 V
6V
63
17
14
2V
tpd
ten
tt
A or B
Gl or G2
B or A
A or B
A or B
SN54HC243
SN74HC243
SN54HC243
SN74HC243
MIN
30
26
MAX
225
45
MIN
c
en
UNIT
MAX
38
32
2V
100
200
4.5 V
26
40
60
6V
21
34
51
50
43
2V
45
265
17
13
210
42
315
4.5 V
6V
63
53
53
45
o
:!
(.)
190
38
300
36
:>w
ns
J:
250
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-207
II
J:
n
s:
o(J)
C
m
<
n
m
(J)
3-208
TYPES SN54HCT242, SN54HCT243
SN74HCT242, SN74HCT243
QUADRUPLE BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02804, MARCH 1984
SN54HCT242, SN54HCT243 ... J PACKAGE
SN74HCT242. SN74HCT243 ... J OR N PACKAGE
(TOP VIEW)
•
Inputs are TTL-Voltage Compatible
•
2-Way Asynchronous Communication
Between Data Buses
•
High-Current Outputs Can Drive up to 15
LSTTL Loads
•
Package Options Include Both Plastic and
Ceramic Chip Carriers In Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
description
G1
NC
A1
A2
A3
A4
GND
SN54HCT242. SN54HCT243 ... FH OR FK PACKAGE
SN74HCT242. SN74HCT243 ... FH OR FN PACKAGE
(TOP VIEW)
These four-data line transceivers are designed
for asynchronous two-way communications
between data buses. The SN74HCT' devices
can be used to drive terrTlinated lines down to
133 ohms.
These parts differ from their TTL counterparts
(LS, ALS, and AS) in that these CMOS parts do
not have a bus-latching mode in which both the
outputs are simultaneously enabled. Instead of
this latched mode, the buses are isolated, thus
preventing potential bus conflicts if both buses
are active. However, with the exception of the
fourth line of the function table, their functional
operation is identical to their TTL counterparts.
The two enables have been renamed G 1 and G2
since they work together to determine the
direction of transmission rather than each enable
controlling one direction independently of the
other. Whenever G1 and G2 are at opposite logic
levels with respect to each other, isolation
between buses results.
VCC
G2
NC
B1
B2
B3
B4
U
U .... U UN
Z(!)Z>(!)
A1
NC
A2
NC
A3
II
NC
NC
B1
NC
B2
CJ)
W
(.)
>
W
C
CJ)
o
NC - No internal connection
~
(.)
J:
The SN54HCT' family is characterized for
operation over the full military temperature range
of -55°C to 125°C. The SN74HCT' family is
characterized for operation from - 40°C to
85°C.
.
FUNCTION TABLE
INPUTS
G1
L
H
G2
L
H
'HCT242
'HCT243
A to B
A to B
"S'to A
B to A
H
L
Isolation
Isolation
L
H
Isolation
Isolation
Copyright © 1984, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-209
TYPES SN54HCT242, SN54HCT243
SN74HCT242, SN74HCT243
QUADRUPLE BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
logic symbol
logic diagrams (positive logic)
'HCT242
'HCT242
(1)
Gl
G2
Al
A2
A3
A4
(13)
Gl
(3)
(11 )
(4)
(10) B2
(5)
(9)
(6)
(8) B4
II
J:
(")
~
Bl
B3
'HCT243
Gl
(1)
G2 (13)
A3
Gl
G2
0
en
cm
<
(;
m
en
Al
A2
A3
A4
(3)
(11)
Bl
(4)
(10)
(5)
(9)
(6)
(8)
'HCT243
B2
B3
B4
Pin numbers shown are for J and N packages.
3-210
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HCT242. SN54HCT243
SN74HCT242. SN74HCT243
QUADRUPLE BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table VII, page 2-14
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
ten
G1 or G2
A or B
tdis
G1 or G2
A or B
A or B
tt
TA = 25°C
vcc
SN54HCT242
SN74HCT242
SN74HCT243
MIN
MAX
TYP
MAX
SN54HCT243
MIN
MAX
4.5 V
15
30
45
38
5.5 V
13
27
41
34
4.5 V
5.5 V
21
19
40
36
60
54
50
45
4.5 V
19
40
60
50
5.5 V
18
36
54
45
4.5 V
8
18
15
5.5 V
7
12
11
16
14
MIN
UNIT
ns
ns
ns
ns
,....-------y------r----,----------,
Cpd
Power dissipation capacitance per transceiver
No load, T A = 25°C
40 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
B or A
ten
G1 or G2
A or B
PARAMETER
tt
A or B
SN54HCT242
TA = 25°C
VCC
MIN
4.5 V
TYP
21
MAX
5.5 V
18
47
42
4.5 V
27
5.5 V
4.5 V
5.5 V
24
17
14
SN54HCT243
MIN
MAX
71
SN74HCT242
SN74HCT243
MIN
MAX
64
59
53
57
86
71
51
77
64
42
38
63
57
53
48
UNIT
ns
ns
II
en
w
(.)
>
W
c
en
o
~
(.)
ns
J:
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TeXAS 75265
3-211
II
J:
(")
so
en
c
m
<
(")
m
en
3-212
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC244, SN74HC244
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
02684. DECEMBER 1982 - REVISED MARCH 1984
•
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
•
High-Current Outputs Can Drive up to
1 5 LSTTL Loads
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC244 ... J PACKAGE
SN74HC244 ... J OR N PACKAGE
(TOPVIEWI
Vee
1G
1A1
2Y4
1,A2
2Y3
lA3
2Y2
lA4
2Yl
description
2G
1Yl
2A4
lY2
2A3
lY3
2A2
lY4
2Al
GND
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of the three-state memory address
drivers, clock drivers, and bus-oriented receivers
and transmitters. Taken together with the
'HC240 and 'HC241 , these devices provide the
choice of selected combinations of inverting
outputs, symmetrical G (active-low input
control) inputs and complementary G and G
inputs.
SN54HC244 ... FH OR FK PACKAGE
SN74HC244 ... FH OR FN PACKAGE
(TOPVIEWI
U
II
q- ....
>- N
3 2 1 2019
The SN54HC244 is characterized for operation
over the full military temperature range of
- 55 °C to 125°C. The SN74HC244 is
characterized for operation from - 40 °C to
85°C.
en
w
1 Yl
lA2
2Y3
1A3
2Y2
1A4
u
5>
w
c
en
2A4
1Y2
2A3
1Y3
9 1011 1213
o
2
u
logic symbol
J:
1A1
1A2
1Yl
1A3
1A4
1Y3
1Y4
1Y2
2G
2Al
2Yl
2A2
2Y2
2A3
2A4
2Y3
2Y4
-1.!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
Copyright
© 1982. Texas Instruments Incorporated
3-213
TYPES SN54HC244, SN74HC244
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
logic diagram (positive logic)
(1)
lG
lAl
lA2
lA3
lA4
J:
o
(2)
(18)
(4)
(16)
(6)
(14)
(8)
(12)
1Yl
2Al
1Y2
2A2
1Y3
2A3
lY4
2A4
(19)
(11)
(9)
(13)
(7)
(15)
(5)
(17)
(3)
2Yl
2Y2
2Y3
2Y4
maximum ratings, recommended operating conditions, and electrical characteristics
See Table /II, page 2-8.
~
o
en
c
2G
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted),
m
<
o
m
en
CL = 50
pF (see Note
1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
tdis
tt
G
G
Y
Y
Y
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA -= 25°C
MIN TYP MAX
40
115
13
23
11
20
75
150
15
30
13
26
75
150
15
30
13
26
28
60
8
12
6
10
SN54HC244
MIN
MAX
170
34
Power dissipation capacitance per gate
29
225
45
SN74HC244
MIN
MAX
145
29
25
190
UNIT
ns
38
32
190
ns
38
225
45
38
90
18
15
38
32
75
15
13
ns
ns
35 pF typ
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
31
3-214
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC244, SN74HC244
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
G
y
tt
Y
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
56
165
18
33
15
28
100 200
20
40
17
34
45
210
42
17
13
36
SN54HC244
MIN TYP MAX
245
49
42
300
60
51
315
63
53
SN74HC244
MIN TYP MAX
210
42
35
250
50
43
265
53
45
UNIT
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
II
en
w
()
:>w
c
en
o
2
()
::I:
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-215
lEI
J:
n
s:
o
en
cm
<
n
m
en
3-216
HIGH·SPEED
CMOS LOGIC
TYPES SN54HCT244, SN74HCT244
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
02804, MARCH 1984
SN54HCT244 .•. J PACKAGE
SN74HCT244 •.. J OR N PACKAGE
(TOP VIEW)
•
Inputs are TTL·Voltage Compatible
•
3·State Outputs Drive Bus Lines or Buffer
Memory Address Registers
•
High·Current Outputs Can Drive up to 15
LSTTL Loads
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
Vee
1(3
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
2(3
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
description
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of three-state memory address drivers,
clock drivers, and bus-oriented receivers and
transmitters. Taken together with the 'HCT240
and 'HCT241, these devices provide the choice
of selected combinations of inverting outputs,
symmetrical IT iactive-Iow input control) inputs,
and complementary G and IT inputs.
SN54HCT244 .•. FH OR FK PACKAGE
SN74HCT244 ••• FH OR FN PACKAGE
(TOP VIEW)
q. ....
II
(J
>- « 1C!l (J1C!l
"" ........ >""
en
The SN54HCT244 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCT244 is
characterized for operation from - 40°C to
85°C.
W
(.)
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
:>W
'0
en
0
.... 0 .... q.""
~
>-z«>-«
""C!l"" .... ""
(.)
logic symbol
::t:
1G
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
2G
2A1
2A2
2Y2
2A3
2A4
2Y3
2Y4
2Y1
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS, TEXAS 75265
Copyright © 1984, Texas Instruments Incorporated
3-217
TYPES SN54HCT244, SN74HCT244
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
logic diagram (positive logic)
(1)
1G
1A1
1A2
1A3
1A4
:t:
(2)
(18)
(4)
(16)
(6)
(14)
(8) .
(12)
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
(11)
(9)
(13)
(7)
(15)
(5)
(17)
(3)
2Y1
2Y2
2Y3
2Y4
maximum ratings, recommended operating conditions, and electrical characteristics
o
3:
oen
2G
See Table VII, page 2-14.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted),
c
CL
= 50 pF (see Note
m
PARAMETER
FROM
(INPUT)
o
tpd
A
<
m
en
1)
TO
(OUTPUT)
Y
ten
IT
Y
tdis
IT
Y
4.5
5.5
4.5
5.5
4.5
TA = 25°C
MIN
TYP MAX
V
V
V
V
V
5.5 V
4.5 V
5.5 V
Y
tt
vCC
15
13
28
25
21
19
19
18
8
7
35
32
35
32
12
11
Power dissipation capacitance per buffer
SN54HCT244
MIN
MAX
42
38
53
48
53
4818
16
No load, TA = 25°C
SN74HCT244
MIN
MAX
35
32
44
40
44
40
15
14
UNIT
ns
ns
ns
ns
40 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
tt
IT
Y
Y
vCC
4.5 V
5.5 V
4.5 V
TA = 25°C
MIN
TYP MAX
45
21
40
18
25
22
17
14
5.5 V
4.5 V
5.5 V
SN54HCT244
MIN
MAX
SN74HCT244
MIN
MAX
68
61
79
71
56
51
65
59
53
48
52
47
42
38
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
3-218
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
63
57
UNIT
ns
ns
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC245. SN14HC245
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
02684. DECEM8ER 1982-REVISED MARCH 1984
•
High·Current 3·State Outputs Drive Bus Lines
Directly or Up to 15 LSTTL Loads
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN54HC246 ... J PACKAGE
SN74HC246 ... J OR N PACKAGE
(TOP VIEW)
Vee
DIR
A1
G
A4
81
82
83
A5
A6
A7
AS
GND
85
86
87
BB
A2
•
Dependable Texas Instruments Quality and Reliability
A3
description
These octal bus transceivers are designed for synchronous twoway communication between data buses. The control function
implementation minimizes external timing requirements.
The devices allow data transmission from the A bus to the B bus
or from the B bus to the A bus depending upon the logic level at
the direction control (DIR) input. The enable input (G) can be
used to disable the device so that the buses are effectively
isolated.
B4
SN64HC246 ... FH OR FK PACKAGE
SN74HC246 ... FH OR FN PACKAGE
(TOP VIEW)
II
a:: U
~ :;( 0 ~Ic)
3 2 1 2019
The SN54HC245 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC245
is characterized for operation from -40°C to 85°C.
logic diagram (positive logic)
A3
B1
A4
A5
A6
A7
B2
B3
en
w
(J
:>w
B4
B5
9 10111213
c
en
o
A1
~
FUNCTION TA8LE
B1
A2
CONTROL
INPUTS
G
CIR
L
L
H
L
B2
A3
B3
A4
H
X
(J
J:
OPERATION
8 data to A bus
A data to 8 bus
Isolation
B4
A5
logic symbol
B5
A6
B6
A7
B7
AB
B8
Copyright <1:>1982 by Texas Instruments Incorporated
TEXAS
-1./1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-219
TYPES SN54HC245, SN74HC245
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
II
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
B or A
ten
G
A or B
tdis
G
A or B
~
oen
TA = 25°C
MIN TYP MAX
40 105
15
21
12
18
125 230
46
23
20
39
74 200
40
25
21
34
20
60
8
12
6
10
SN54HC245
MIN
MAX
160
32
27
340
68
58
300
60
51
90
18
15
SN74HC245
MIN
MAX
130
26
22
290
58
49
250
50
43
75
15
13
UNIT
ns
ns
ns
ns
40 pF typ
Power dissipation capacitance per transceiver
(")
S
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
A or B
tt
vCC
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
cm
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
(")
tpd
A or B
B or A
ten
G
A or B
S
m
en
tt
A or B
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
54 135
18
27
15
23
150 270
31
54
25
46
45
210
17
42
13
36
SN54HC245
MIN
MAX
200
40
34
405
81
69
315
63
53
SN74HC245
UNIT
MIN
MAX
170
ns
34
29
335
67
ns
56
265
53
ns
45
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
3E
3-220
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC251. SN74HC251
DATA SELECTORS/MULTIPLEXERS WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02684, DECEMBER 1982-REVISED MARCH 1984
SN54HC261 ... J PACKAGE
SN74HC261 ..• J OR N PACKAGE
(TOP VIEW)
• 3·State Version of 'HC151
• High·Current 3·State Outputs Interface Directly
with System Bus or Can Drive up to 15 LSTTL Loads'
03
02
01
00
• Performs Parallel·to·Serial Conversion
• Complementary Outputs Provide True and Inverted
Data
VCC
04
05
06
07
Y
W
• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs
A
G
B
C
GNO
• Dependable Texas Instruments Quality and Reliability
description
These data selectors/multiplexers contain full binary decoding
to select one-of-eight data sources and feature strobe-controlled
complementary three-state outputs.
SN54HC261 .•. FH OR FK PACKAGE
SN74HC261 ... FH OR FN PACKAGE
(TOP VIEW)
N
M
U
U
U'O
The three-state outputs can interface with and drive data lines
of bus-organized systems. With all but one of the common
outputs disabled (at a high-impedance state), the low-impedance
of the single enabled output will drive the bus line to a high or
low logic level. Both outputs are controlled by the strobe (G). The
outputs are disabled when G is high.
05
06
01
00
NC
y
w
07
A
W
The SN54HC251 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC251
is characterized for operation from -40°C to 85°C.
en
NC
1(.9 0
(.)
5>
w
c
U U OJ
zz
(.9
en
o
NC-No internal connection
~
FUNCTION TABLE
INPUTS
SELECT
C
B
(.)
OUTPUTS
STROBE
A
G
V
MUXt>
X
X
X
H
Z
Z
L
L
L
L
DO
L
L
H
L
D1
Do
61
L
H
L
L
D2
52
L
H
H
L
D3
H
L
L
L
D4
OJ
54
01
H
L
H
L
D5
65
02
06
07
H
H
L
L
D6
H
H
H
L
D7
::J:
logic symbol
w
G
EN
A
:)G~
B
C
DO
<:J
<:J
(51
(61
y
W
03
04
05
06
DO, D1 •.. D7 = the level of the respective D input
07
Pin numbers shown are for J and N package.
TEXAS
~
INSTRUMENTS
PO~T
OFFICE BOX 225012 • DALLAS, TEXAS 75265
Copyright ©1982 by Texas Instruments Incorporated
3-221
TYPES SN54HC251. SN74HC251
DATA SELECTORS/MULTIPLEXERS WITH 3·STATE OUTPUTS
logic diagram (positive logic)
A
B
c
00
lEI
01
::I:
(')
02
S
y
0
03
t/)
C
m
<
04
m
05
w
(')
t/)
06
07
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
3-222
"'J}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
31
TYPES SN54HC251, SN74HC251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A. B. or C
WorY
tpd
Any D
WorY
ten
G
WorY
tdis
G
WorY
tt
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
205
58
21
41
19
35
44
195
. 17
39
15
33
30
145
10
29
25
9
25
195
15
39
14
33
20
75
15
8
13
6
SN54HC251
MIN
MAX
300
60
51
283
57
48
210
42
36
283
57
48
110
22
19
Power dissipation capacitance
SN74HC251
MIN
MAX
256
51
44
244
49
41
181
36
31
244
49
41
95
19
16
UNIT
ns
ns
ns
ns
II
ns
en
w
u
70 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 150 pF (see Note 1)
.
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A. B. or C
WorY
tpd
Any D
WorY
ten
tt
G
WorY
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
SN54HC251
TA = 25°C
MAX
MIN TYP MAX- MIN
450
72 300
25
60
90
22
52
71
59
450
300
21
90
60
18
52
71
230
340
50
46
68
17
40
58
15
45
210
315
17
42
63
13
36
53
SN74HC251
MIN
MAX
375
75
65
375
75
65
335
57
50
265
53
45
UNIT
ns
:>w
c
en
o
:E
u
J:
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
-II}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-223
:::t
n
o
S
en
c
m
S
n
m
en
3-224
TYPES SN54HC253, SN74HC253
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISEDMARCH 1984
•
3·State Versions of 'HC153
•
High-Current Outputs Drive up to 15 LSTTL
Loads
•
Permits Multiplexing from N Lines to 1 Line
•
Performs Parallel-to-Serial Conversion
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC253 •.. J PACKAGE
SN74HC253 ••• J OR N PACKAGE
(TOP VIEW)
1<3
VCC
2<3
B
A
lC2
lCl
lCO
lY
2C3
2C2
2Cl
2CO
2Y
GND
SN54HC253 .•• FH OR FK PACKAGE
SN74HC253 ••• FH OR FN PACKAGE
description
(TOP VIEW)
Each of these data selectors/multiplexers
contains inverters and drivers to supply full
binary decoding data selection to the AND-OR
gates. Separate output control inputs are
provided .for each of the two four-line sections.
It!) u
II
A
lC2
The three-state outputs can interface with and
drive data lines of bus-organized systems. With
all but one of the common outputs disabled (at
a high-impedance state) the low-impedance of
the single enabled output will drive the bus line
to a high or low logic level. Each output has its
own strobe {G). The output is disabled when its
strobe is high.
The SN54HC253 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC253 is
characterized for operation from - 40°C to
85°C.
U
ult!)
al..-Z>N
en
w
2C3
NC
(.)
2C2
2Cl
>
W
c
>-OU>-O
"-ZZNU
t!)
en
:E
(.)
N
o
NC-No internal connection
logic symbol
J:
B
FUNCTION TABLE
SELECT
OUTPUT
DATA INPUTS
INPUTS
CONTROL
B
A
CO
C1
C2
C3
G
X
X
X
X
X
X
H
lCO
Y
Z
L
L
L
X
X
X
L
L
L
L
H
X
X
X
L
H
L
L
H
H
H
H
lG
OUTPUT
H
X
L
X
X
L
L
H
X
H
X
X
L
H
L
X
X
L
X
L
L
L
X
X
H
X
L
H
H
X
X
X
L
L
L
H
X
X
X
H
L
H
(7)
lCl
(9)
lY
2Y
Pin numbers shown are for J and N packages
Address inputs A and B are common to both sections.
Copyright © 1982. Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-225
TYPES SN54HC253, SN74HC253
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
logic diagram (positive logic)
A
B~--------r-------~--~
II
::I:
o
3:
o
en
c
m
<
om
en
Pin numbers shown are for J and N packages
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
3-226
.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC253. SN74HC253
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
A or B
tpd
Any Y
225
190
38
32
30
26
45
38
2V
54
126
16
28
210
42
175
4.5 V
6V
13
23
36
30
2V
28
100
150
125
4.5 V
6V
11
9
20
17
30
26
25
21
2V
21
135
14
30
203
45
170
4.5 V
25
38
31
60
90
75
12
10
18
15
15
13
ten
IT
Y
tdis
IT
Y
6V
Y
SN74HC253
MIN
MAX
19
16
Y
. tt
SN54HC253
MIN
MAX
4.5 V
6V
Data
(Any C)
tpd
TA = 25°C
MIN
TYP MAX
150
62
2V
12
28
4.5 V
8
6V
6
Power dissipation capacitance per multiplexer
35
38
UNIT
ns
ns
ns
ns
II
ns
en
w
45 pF typ
No load. TA = 25°C
(.)
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL
150 pF (see Note 1)
=
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
tpd
tpd
ten
tt
A or B
Any Y
Data
(Any C)
Y
IT
Y
Y
SN74HC253
TA = 25°C
MIN
TYP. MAX
235
76
SN54HC253
MIN
MAX
355
295
59
51
4.5 V
23
47
71
6V
20
41
60
2V
4.5 V
220
44
335
67
6V
68
20
17
38
57
MIN
MAX
275
55
51
2V
44
185
280
4.5 V
16
37
56
230
46
6V
14
45
32
48
40
210
42
315
63
36
53
265
53
45
2V
4.5 V
17
13
6V
:>
w
c
en
UNIT
o
ns
(.)
~
J:
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265
3-227
J:
n
S
o
rn
cm
S
n
m
rn
3-228
TYPES SN54HC257, SN54HC258, SN74HC257, SN74HC258
QUAD 2·L1NE TO 1·L1NE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
•
SN54HC257, SN54HC258
J PACKAGE
SN74HC257, SN74HC258
J OR N PACKAGE
(TOP VIEW)
High-Current 3-State Outputs Interface
Directly with System Bus or Can Drive up
to 1 5 LSTTL Loads
0
0
AlB
•
Provides Bus Interface from Multiple
Sources in High Performance Systems
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
description
VCC
G
1A
1B
1Y
2A
2B
2Y
4A
4B
4Y
3A
3B
3Y
GND
SN54HC257, SN54HC258
FH OR FK PACKAGE
SN74HC257, SN74HC258 ••• FH OR FN PACKAGE
(TOP VIEW)
0
These devices are designed to multiplex signals
from four-bit data sources to four-output data
lines in bus-organized systems. The 3-state
outputs will not load the data lines when the
output control pin (<3) is at a high-logic level.
••
••
0
•
1(.:)
The SN54HC257 and SN54HC258 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74HC257 and SN74HC258 are characterized
for operation from - 40°C to 85 °Co
1Y
4A
4B
NC
NC
2A
2B
4Y
3A
II
til
w
(.)
:>w
C
til
FUNCTION TABLE
INPUTS
OUTPUT
SELECT
CONTROL
'HC258
x
z
Z
L
H
X
X
L
H
H
L
X
X
L
L
H
H
A
B
H
x
X
L
L
L
L
L
H
L
H
H
~
NC-No internal connection
'HC257
AlB
G
o
OUTPUT Y
DATA
(.)
::J:
L
logic symbols
'HC257
'HC258
AlB
AlB
1A
1A
1Y
1B
2A
1B
2A
2Y
2B
2B
3A
3A
3Y
3B
4A
3B
4A
4Y
4B
4B
1Y
2Y
3Y
4Y
Pin numbers shown are for J and N packages.
Copyright © 1982. Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TeXAS 75265
3-229
TYPES SN54HC257. SN54HC258. SN74HC257. SN74HC258
QUAD 2·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
logic diagrams (positive logic)
'HC257
•
'HC258
1A
~(2;.;...)---+-+---L~
1A
18
..,;.;(3;..;..)
---+-+-L---I
18
2A-(5~)_ _-+-+-L~
2A
28...;.;(6;";")_ _-+-+-L~
28
S
o(J)
(5)
(6)
3A
38 (10)
38 (10)
:::I:
(3)
(11)
3A (11)
(")
(2)
4A (14)
4A
48 (13)
4B
(14)
(13)
Pin numbers shown are for J and N packages.
C
m
!S
(")
maximum ratings, recommended operating conditions, and electrical characteristics
m
See Table III, page 2-8.
(J)
3-230
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC257, SN74HC257
QUAD 2-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER.
FROM
(INPUT)
(OUTPUT)
tpd
A or B
Any Y
tpd
ten
tdis
AlB
G
G
TO
AnyY
Any Y
Any Y
Any
tt
vCC
TA = 25°C
MIN
TYP MAX
SN54HC257
MIN
SN74HC257
MAX
MIN
MAX
2V
50
100
150
4.5 V
10
20
30
25
6V
9
17
25
21
UNIT
125
2V
50
100
150
125
4.5 V
10
20
30
25
6V
9
17
25
21
190
2V
75
150
225
4.5 V
15
30
45
38
6V
13
26
38
32
2V
75
150
225
190
4.5 V
15
30
45
38
6V
13
26
38
32
2V
28
60
90
75
4.5 V
8
12
18
1'5
6V
6
10
15
13
ns
ns
ns
ns
II
ns
(1J
40 pF typ
Power dissipation capacitance per multiplexer
W
(J
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
tpd
tpd
ten
tt
FROM
TO
(INPUT)
(OUTPUT)
A or B
AlB
G
Any Y
Any Y
Any Y
Any
VCC
TA = 25°C
TYP MAX
MIN
SN74HC257
SN54HC257
MIN
MAX
MIN
MAX
2V
75
150
245
4.5 V
15
30
45
38
6V
13
26
38
32
2V
75
150
245
190
4.5 V
30
45
6V
15
13
26
38
38
32
2V
100
200
250
300
4.5 V
24
40
60
50
6V
18
34
51
43
2V
45
210
315
265
4.5 V
17
13
42
63
53
36
53
45
6V
UNIT
:>
w
c
(1J
o
190
ns
~
(J
:I:
ns
ns
ns
NOTE 1: For load circuits and voltage waveforms, see page 1-14.
TEXAS
"!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-231
TYPES SN54HC258. SN74HC258
QUAD 2·LlNE TO '·LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM.
(INPUT)
TO
(OUTPUT)
VCC
=
TA
25°C
MIN
TYP MAX
2V
tpd
tpd
ten
tdis
II
A or B
AlB
IT
G
Any Y
Any Y
Any Y
Any
tt
J:
Any Y
SN54HC258
MIN
MAX
150
SN74HC258
MIN
MAX
4.5 V
60
13
100
20
30
25
6V
2V
12
60
17
115
25
175
21
145
4.5 V
13
23
35
6V
12
20
29
25
190
2V
70
150
30
225
4.5 V
15
30
45
38
6V
2V
13
75
26
150
38
225
32
190
4.5 V
15
30
45
6V
2V
13
26
38
32
28
75
4.5 V
8
60
12
38
90
18
15
6V
6
10
15
13
Power dissipation capacitance per multiplexer
o
en
c
m
<
ns
ns
ns
ns
ns
40 pF typ
(')
S
UNIT
125
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
tpd
(')
A or B
Any Y
m
en
tpd
ten
tt
AlB
G
Any Y
Any Y
Any
TA = 25°C
TYP MAX
MIN
95
150
4.5 V
23
30
6V
21
26
SN54HC258
MIN
MIN
MAX
245
45
190
32
210
42
2V
95
165
38
240
4.5 V
6V
23
21
33
28
48
41
38
2V
100
200
300
36
250
4.5 V
6V
24
40
18
34
60
51
50
43
2V
45
210
315
265
4.5 V
6V
17
42
13
36
63
53
53
45
NOTE 1: For load circuits and voltage waveforms, see page 1-14.
3-232
SN74HC258
MAX
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
UNIT
ns
ns
ns
ns
TYPES SN54HC259, SN74HC259
8·BIT ADDRESSABLE LATCHES
HIGH·SPEED
'CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
•
8-Bit Parallel-Out Storage Register Performs
Serial-to-Parallel Conversion with Storage
•
Asynchronous Parallel Clear
•
Active-High Decoder
•
Enable Input Simplifies Expansion
•
Expandable for N·Bit Applications
•
Four Distinct Functional Modes
SN54HC269 ... J PACKAGE
SN74HC269 ... J OR N PACKAGE
(TOPVIEWj
50
51
52
00
01
02
03
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
, and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
VCC
CLR
G
D
07
06
05
04
GND
SN64HC269 ... FH OR FK PACKAGE
SN74HC269 ... FH OR FN PACKAGE
(TOPVIEWj
... 0 u ~15
(/)(/)z>1U
description
These 8-bit addressable latches are designed for
general purpose storage applications in digital
systems. Specific uses include working
registers, serial-holding registers, and active-high
decoders or demultiplexers. They are
multifunctional devices capable of storing singleline data in eight addressable latches, and being
a 1-of-8 decoder or demultiplexer with activehigh outputs.
Four distinct modes of operation are selectable
by controlling the clear (ClR) and enable (G)
inputs as enumerated in the function table. In the
addressable-latch mode, data at the data-in
terminal is written into the addressed latch. The
addressed latch will follow the data input with
all unaddressed latches remaining in their
previous states. In the memory mode, all latches
remain in their previous states and are
unaffected by the data or address inputs. To
eliminate the possibility of entering erroneous
data in the latches, enable Gshould be held high
(inactive) while the address lines are changing.
In the 1-of-8 decoding or demultiplexing mode,
the addressed output will follow the level of the
o input with all other outputs low. In the clear
mode, all outputs are low and unaffected by the
address and data inputs.
52
00
G
01
02
07
06
II
D
en
NC
w
(,)
5>
w
c
en
o
NC-No internal connection
~
FUNCTION TABLE
INPUTS
CLR
H
H
G
L
'H
::I:
OUTPUT OF
EACH
ADDRESSED
LATCH
OTHER
OUTPUT
FUNCTION
0
aiO
Addressable Latch
aiO
L
Memory
L
L
L
aiO
0
L
H
L
The SN54HC259 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC259 is
characterized for operation from - 40°C to
85°C.
(,)
8-Line Demultiplexer
Clear
LATCH SELECTION TABLE
SELECT INPUTS
S2
S1
L
L
L
L
LATCH
SO
ADDRESSED
L
L
L
H
H
0
1
L
2
H
H
H
L
L
H
L
H
3
4
5
H
H
L
6
H
H
H
7
Copyright©1982 by Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-233
TYPES SN54HC259, SN74HC259
8·BIT ADDRESSABLE LATCHES
logic diagram (positive logic)
logic symbol
(4)
10,OR
(5)
9,10
10,1R
9,20
10.2R
J:
01
02
9,30
10;3R
(7)
9,40
(9)
10;4R
o
S
00
03
04
9,50
(10) 05
10,SR
9,60
(11) 06
10,SR
9,70
o
(12) 07
10JR
til
C
m
S
o
m
til
Pin numbers shown are for J and N packages.
logic symbol and logic diagram, each internal latch (positive logic)
c
D=t}::'
R
0
c
Q
c
C
Q
1R
R
3-234
C
TEXAS
"!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC259, SN74HC259
8·BIT ADDRESSABLE LATCHES
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2·10.
timing requirements over recommended operating free·air temp~rature range (unless otherwise noted)
VCC
CLR low
Pulse duration
tw
Glow
tsu
Setup time. data or address before
th
Hold time. data or address after
Gt
<31
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
80
16
14
80
16
14
75
15
13
5
5
5
SN54HC259
MIN
MAX
120
24
20
120
24
20
115
23
20
5
5
5
SN74HC259
UNIT
MIN
MAX
100
20
17
ns
100
20
17
95
19
ns
16
5
5
ns
5
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpHL
C'i:R
Any Q
tpd
Data
Any Q
tpd
Address
Any Q
tpd
G
Any Q
tt
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA .. 25°C
MIN TYP MAX
60 150
18
30
14
26
56 130
17
26
13
22
74 200
21
40
17
34
66 170
20
34
16
29
28
75
8
15
13
6
SN54HC259
MAX
MIN
225
45
38
195
39
33
300
60
51
255
51
43
110
22
19
Power dissipation capacitance per latch
SN74HC259
UNIT
MIN
MAX
190
ns
38
32
165
33
ns
28
250
50
ns
43
215
43
ns
37
95
ns
19
16
II
t/)
W
(,)
5>
w
Q
t/)
o
~
(,)
J:
33 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS . ;
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3·235
lEI
J:
n
3:
orJ)
C
m
<
n
m
rJ)
3-236
TYPES SN54HC266. SN74HC266
QUADRUPLE 2·INPUT EXCLUSIVE·NOR GATES
WITH OPEN·DRAIN OUTPUTS
HIGH·SPEED
CMOS LOGIC
02684, DECEMBER 1982-REVISED MARCH 1984
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality
and Reliability
SN54HC266 ... J PACKAGE
SN74HC266 ... J OR N PACKAGE
(TOP VIEW)
description
These devices are composed of four independent
2-input exclusive-NOR gates and feature opendrain outputs. T.!:!!Y-per~o.!:m the Boolean
functions: Y = A (£J B = AB + AB in positive
logic.
The SN54HC266 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC266 is
characterized for operation from - 40°C to
85°C.
vee
1A
1B
1Y
2Y
2A
2B
4B
4A
4Y
3Y
3B
3A
GND
SN54HC266 ... FH OR FK PACKAGE
SN74HC266 ••. FH OR FN PACKAGE
(TOP VIEW)
u
~ ~ ~ ~~
3 2 1 2019
II
4A
NC
4Y
logic symbol
en
NC
w
U
3Y
1A
1B
1Y
2A
2B
2Y
3A
3B
3Y
4A
9 10111213
c
en
o
:2:
u
NC-No internal connection
4Y
4B
>
w
FUNCTION TABLE
INPUTS
Pin numbers shown are for J and N packages.
A
L
L
OUTPUT
B
L
H
H
L
H
H
Y
H
L
L
H
J:
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-237
TYPES SN54HC266, SN74HC266
QUADRUPLE 2·INPUT EXCLUSIVE·NOR GATES WITH OPEN·DRAIN OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpLH
tpHL
tt
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
A or B
Y
Y
Vcc
2V
4.5 V
TA ... 25 D C
MIN TYP MAX
60
125
25
13
6V
2V
4.5 V
6V
2V
4.5 V
10
60
13
10
28
8
6V
6
Power dissipation capacitance per gate
II
23
100
20
17
75
15
13
SN54HC266
MIN
MAX
190
38
32
150
SN74HC266
MIN
MAX
155
31
30
25
110
22
19
25
21
95
19
16
No load, TA = 25°C
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
::E:
(")
s:
o
rn
c
m
S
(")
m
rn
3-238
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
UNIT
ns
26
125
I
35 pF typ
ns
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC273. SN74HC273
OCTAL D·TYPE FLlp·FLOPS WITH CLEAR
02684. DECEMBER 1982 - REVISED MARCH 1984
•
SN54HC273 ... J PACKAGE
SN74HC273 ... J OR N PACKAGE
(TOP VIEW)
Contains Eight Flip-Flops with Single-Rail
Outputs
•
Direct Clear Input
•
Individual Data Input to Each Flip-Flop
•
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
..
Dependable Texas Instruments Quality and
Reliability
ClR
10
10
20
20
30
30
40
40
GNO
VCC
80
80
70
70
60
60
50
50
ClK
SN54HC273 ... FH OR FK PACKAGE
SN74HC273 ... FH OR FN PACKAGE
(TOP VIEW)
description
Information at the 0 inputs meeting the setup time
requirements is transferred to the 0 outputs on the
positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the transition time of the positivegoing pulse. When the clock input is at either the
high or low level. the 0 input signal has no effect at
the output.
The SN54HC273 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC273 is characterized for operation from -40°C to 85°C.
20
20
30
30
40
en
w
80
70
70
60
60
4
5
6
7
B
CJ
:;
w
c
en
o
9 1011 1213
00:.<:00
q-t§dL!)L!)
2
CJ
J:
logic symbol
FUNCTION TABLE
ClK
(EACH FLIP-FLOPS)
INPUTS
OUTPUT
10
CLEAR CLOCK 0
l
X
X
0
20
3D
40
10
20
30
40
50
60
70
80
50
60
70
80
H
H
H
II
o 015
~0
..........
u>co
These circuits are positive-edge-triggered Ootype
flip-flops with a direct clear input.
l
t
t
H
l
l
l
X
00
H
Copyright ©1982 by Texas Instruments Incorporated
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-239
TYPES SN54HC273, SN74HC273
OCTAL O·TYPE FLlp·FLOPS WITH CLEAR
logic diagram, total device (positive logic)
10
20
(3)
(4)
40
3D
(7)
(8)
50
(13)
60
(14)
70
(17)
80
(18)
CLKIII
logic diagram each flip-flop (positive logic)
c
II
c
o--~
a
:J:
(')
s:
oen
CLKm~:
c
m
<
R------a
(')
m
en
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-' O.
3-240
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC273, SN74HC273
OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
SN54HC273
TA = 25°C
VCC
MAX
MIN
MAX
MIN
MAX
0
5
0
4
0
4
4.5 V
0
27
0
18
0
21
6V
0
32
0
21
0
25
2V
80
16
120
100
4.5 V
24
20
6V
14
20
17
2V
Clock frequency
fclock
ClR low
Pulse duration
tw
ClK high or low
Data
Setup time
tsu
before ClK t
ClR inactive
Hold time, data after ClK t
th
SN74HC273
MIN
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
4.5 V
0
0
0
0
0
0
6V
0
0
0
UNIT
MHz
ns
ns
ns
II
ns
ns
en
w
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
. tpHl
tpd
tt
ClR
ClK
Any
Any
Any
VCC
TA = 25°C
MIN
TYP MAX
SN54HC273
MIN
MAX
SN74HC273
MIN
2V
5
11
4
4
4.5 V
27
50
18
21
6V
32
60
28
MAX
MHz
25
2V
55
160
240
200
4.5 V
15
32
48
40
6V
12
27
41
34
2V
56
160
240
200
4.5 V
15
32
48
40
6V
13
27
41
34
95
2V
38
75
110
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance per flip-flop
No load, TA
=
25°C
UNIT
()
>
W
c
en
o
~
()
ns
J:
ns
ns
35 pF typ
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-241
lEI
::I:
n
~
orJ)
C
m
$
n
m
rJ)
3-242
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC280, SN74HC280
9·811 ODD/EVEN PARITY GENERATORS/CHECKERS
02684. DECEM8ER 1982-REVISED MARCH 1984
•
•
Cascadable for n·Bits
•
Can Be Used to Upgrade Existing Systems
Using MSI Parity Circuits
•
•
SN54HC280 ... J PCKAGE
SN74HC280 ..• J OR N PACKAGE
(TOP VIEW)
Generates Either Odd or Even Parity for Nine
Data Lines
G
F
NC
E
E EVEN
E 000
C
B
GNO
A
0
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
Dependable Texas Instruments Quality
and Reliability
SN54HC280 ... FH OR FK PACKAGE
SN74HC280 ..• FH OR FN PACKAGE
(TOP VIEW)
description
These universal, monolithic, f1ine-bit parity generators/ checkers feature odd and even outputs to facilitate operation of either odd or even parity application.
The word-length capability is easily expanded by
cascading.
The SN54HC280 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC280 is characterized for operation from -40°C to 85°C.
U
u u
:I:<.!lZ>u..
E
NC
NC
E
I
NC
o
0,2.4.6,8
1.3.5,7.9
en
w
NC
EVEN
(.)
C
:>w
ccuO
Dependable Texas Instruments Quality and
Reliability
description
This quadruple two-input multiplexer with
storage provides essentially the equivalent
functional capabilities of two separate MSI
functions ('HC157 and 'HC175) in a single
16-pin package.
When the Word-Select (WS) input is low, word
one (A 1, Bl, Cl, 01) is applied to the flip-flops.
A high Word-Select input causes word two
(A2, B2, C2, 02) to be selected. The selected
word is clocked to the output terminals on the
negative-going edge of the clock pulse.
II
U
NNUU«
A1
S1
Qc
NC
NC
C2
Qo
02
ClK
en
w
QS
(.)
:>w
c
en
o
2
NC-No internal connection
(.)
:I:
logic symbol
The SN54HC298 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC298 is
characterized for operation from - 40°C to
85°C.
Pin numbers shown are for J and N packages.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright © 1984. Texas Instruments Incorporated
3-245
TYPES SN54HC298, SN74HC298
QUADRUPLE 2·INPUT MULTIPLEXER WITH STORAGE
logic diagram (positive logic)
II
J:
(")
s:
oen
c
m
<
(=)
m
en
Pin numbers shown are for J and N packages.
absolute maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
3-246
TEXAS •
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS, TeXAS 75265
TYPES SN54HC298. SN74HC298
QUADRUPLE 2·INPUT MULTIPLEXER WITH STORAGE
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
Clock frequency
fcJock
Pulse duration. ClK high or low
tw
Data before ClK ~
Setup time
tsu
WS before ClK ~
Data after
ClK~
Hold time
th
WS after ClK ~
TA = 25°C
MIN
MAX
SN54HC298
MIN
MAX
SN74HC298
MAX
MIN
2V
6.5
4.3
4.5 V
33
22
5.5
27
6V
2V
38
25
31
75
115
4.5 V
15
23
6V
13
2V
4.5 V
80
20
125
105
25
21
6V
16
14
21
18
2V
4.5 V
80
16
105
21
6V
14
125
25
21
2V
0
0
0
4.5 V
0
0
0
6V
2V
4.5 V
0
0
0
0
0
0
0
0
0
6V
0
0
0
95
19
UNIT
MHz
ns
16
ns
18
II
ns
U)
W
c.J
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
f max
tpd
tt
Cpd
FROM
(INPUT)
TO
(OUTPUT)
\
ClK
Any
Any
VCC
TA = 25°C
MIN
TYP MAX
SN54HC298
SN74HC298
MAX
MIN
2V
6.5
MIN
4.3
4.5 V
33
22
27
6V
38
25
31
2V
46
125
190
15
12
25
21
38
32
110
2V
38
75
8
15
6V
6
13
Power dissipation capacitance per multiplexer
UNIT
No load. TA = 25°C
22
19
MHz
155
31
Q
U)
o
5.5
4.5 V
6V
4.5 V
MAX
:>W
~
c.J
J:
ns
26
95
19
ns
16
33 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-247
II
:I:
(")
s
o
(J)
C
m
<
(1
m
(J)
3-248
TYPES SN54HC352, SN74HC352
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
HIGH·SPEED
CMOS LOGIC
02684, DECEM8ER 1982-REVISED MARCH 1984
•
Inverting Versions of 'HC153
•
High·Current Inverting Outputs Can Drive up
to 15 LSTTL Loads
•
Permits Multiplexing from n Lines to 1 Line
•
Performs Parallel-to-Serial Conversion
•
Strobe (Enable) Line Provided for Cascading
(N Lines to n Lines)
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC352 ... J PACKAGE
SN74HC352 ... J OR N PACKAGE
(TOP VIEW)
1<3
1C3
1C2
1C1
1CO
1Y
Separate output enable inputs (<3) are provided
for each of the two four-line sections of these
data s'electors/multiplexers.
II
o
A
>
w
2C3
NC
2C2
2Cl
1C2
NC
1C1
FUNCTION TABLE
c
en
o
9 1011 1213
OUTPUT
DATA INPUTS
2C3
2C2
2C1
2CO
2Y
en
w
The SN54HC352 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC352 is
characterized for operation from - 40°C to
85°C.
SELECT
A
SN54HC352 ... FH OR FK PACKAGE
SN74HC352 ... FH OR FN PACKAGE
(TOP VIEW)
description
INPUTS
VCC
2(3
B
ENABLE
CO
C1
C2
C3
G
Y
X
L
X
L
X
L
X
X
H
X
X
X
X
H
H
L
L
H
X
X
X
L
L
L
H
X
L
X
X
L
H
L
L
H
X
H
X
X
L
L
H
L
X
X
L
X
L
H
H
H
L
X
X
H
X
X
X
X
L
L
H
L
L
H
H
H
X
X
X
H
L
L
o
.... Z Z N U
(!)
A
~
>-ou>-o
OUTPUT
B
N
::I:
NC-No internal connection
logic symbol
B
1G
lCO
Select inputs A and B are common to both sections.
lY
lCl
2Y
2C2
2C3 (13)
Pin numbers shown are for J and N packages.
Copyright
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
© 1982, Texas Instruments Incorporated
3-249
TYPES SN54HC352, SN74HC352
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
logic diagram (positive logic)
A
8...;;;,;,----+----+----1
II
::t
(")
S
o
~
C
m
<
Ci
m
~
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
3-250
TEXAS
-I/}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3
TYPES SN54HC352, SN74HC352
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
tpd
tpd
Data
(Any C)
G
Y
Y
Y
tt
VCC
2V
4.5 V
6V
2V
TA = 25°C
MIN TYP MAX
58
185
17
37
32
14
47
175
SN54HC352
MIN
MAX
280
56
48
265
SN74HC352
MIN
MAX
230
46
39
220
35
30
135
27
23
60
12
10
53
45
205
41
35
90
18
15
44
37
170
34
29
75
15
13
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
14
12
27
10
8
20
8
6
UNIT
ns
ns
ns
ns
Power dissipation capacitance per data selector
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
y
tpd
A or B
tpd
Data
(Any C)
Y
G
y
tpd
tt
Y
Vee
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
270
72
22
54
47
19
62 260
52
19
45
16
43 220
44
14
12
38
45 210
17
42
13
36
SN54HC352
MIN
MAX
410
82
70
395
79
67
335
67
57
315
63
53
SN74HC352
MIN
MAX
335
67
58
325
63
56
275
55
48
265
53
45
UNIT
ns
II
(J)
W
(J
:>w
c
(J)
o
ns
~
(J
J:
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS
-I/}
INSTRUMENTS
POST OFFice BOX 225012 • OALLAS. TeXAS 75265
3-251
II
J:
(")
s
oen
cm
<
(")
m
en
3-252
TYPES SN54HC353, SN74HC353
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
•
Inverting Versions of 'HC253
•
Permits Multiplexing from N Lines to 1 Line
•
Performs Parallel· to-Serial Conversion
lG
•
High-Current Outputs Can Drive up to 15
lSTTlloads
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
SN54HC353 ... J PACKAGE
SN74HC353 ... J OR N PACKAGE
(TOP VIEW)
Dependable Texas Instruments Quality and
Reliability
l
W
>-ou>-o
-
Z
N
The three-state outputs can interface with and
drive data lines of bus-organized systems. With
all but one of the common outputs disabled (at
a high-impedance state), the low-impedance of
the single enable output will drive the bus line
to a high or low logic level. Each output has its
own output enable (0). The output is disabled
when its output enable is high.
SELECT
2Cl
2CO
SN54HC353 ... FH OR FK PACKAGE
SN74HC353 ... FH OR FN PACKAGE
(TOP VIEW)
description
The SN54HC353 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC353 is
characterized for operation from - 40°C to
85°C.
VCC
2G
A
2C3
2C2
B
lC3
lC2
lCl
lCO
lV
L
L
L
H
1G
1CO
1C1
L
L
L
H
2CO
L
L
2C1
L
L
H
2C2
H
L
L
2C3
Select inputs A and B are common to both sections.
1Y
1C2
2Y
Pin numbers shown are for J and N packages.
Copyright©1982 by Texas Instruments Incorporated
"'J}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-253
TYPES SN54HC353. SN74HC353
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
logic diagram (positive logic)
A
B~--------~------~--~
1G~--------r-------r---------~-------r----'
(71
1V
(91
2V
11
::I
(')
S
o
tJ)
C
m
<
o
m
tJ)
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
3
3-254
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC353, SN74HC353
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
tpd
A or 8
Y
tpd
Data (Any C)
Y
ten
G
y
tdis
G
y
Any
tt
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
TA = 25°C
MIN TYP MAX
60
185
17
37
14
32
48
175
14
35
11
37
11
9
22
13
11
20
6V
2V
4.5 V
6V
8
6
30
135
27
23
135
27
SN54HC353
MIN
MAX
280
56
48
265
53
45
205
41
35
205
41
23
60
12
10
35
90
18
15
Power dissipation capacitance per multiplexer
SN74HC353
MIN
MAX
230
46
39
220
44
37
170
34
29
170
34
29
75
15
13
UNIT
ns
ns
ns
ns
II
ns
en
w
40 pF typ
(J
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL
150 pF (see Note 1)
=
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
tpd
Data (Any C)
y
ten
G
y
tt
Any
Vec
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
75
270
21
54
18
47
67
260
19
52
45
16
54
220
16
44
14
38
45
210
17
42
13
36
SN54HC353
MIN
MAX
410
82
70
395
79
67
335
67
57
315
63
53
SN74HC353
MIN
MAX
335
67
UNIT
ns
58
325
63
56
275
55
48
265
53
45
>
W
c
en
o
~
(J
::t
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-255
III
J:
o
:s:
orJ)
o
m
<
(=)
m
rJ)
3-256
TYPES SN54HC365 THRU SN54HC368
SN74HC365 THRU SN74HC368
HEX BUS DRIVERS WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982 - REVISED MARCH 1984
•
High·Current 3-StBte Outputs Drive Bus
Lines. Buffer Memory Address Registers. or
up to 15 LSTTL Loads
•
Choice of True or Inverting Outputs
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
SN54HC365. SN54HC366 ... J PACKAGE
SN74HC365. SN74HC365 .•. J OR N PACKAGE
(TOP VIEWI
Dependable Texas Instruments Quality and
Reliability
'HC365, 'HC367
'HC366, 'HC368
True Outputs
Inverting Outputs
lU16
<31
A1
V1
A2
V2
A3
VCC
<32
2
15
3
14
A6
4
Y6
5
13
12
6
11
AS
VS
V3
7
10
A4
GND
8
90 V4
SN54HC365. SN54HC366 ... FH OR FK PACKAGE
SN74HC365. SN74HC366 ... FH OR FN PACKAGE
(TOP VIEWI
description
- - U
<{I(!) Z
These Hex buffers and line drivers are designed
specifically to improve both the performance and
density of three-state memory address drivers,
clock drivers, and bus-oriented receivers and
transmitters. The designer has a choice of
selected combinations of inverting and
noninverting outputs, symmetrical G (active-low
control) inputs.
The SN54HC' family is characterized for
operation over the full military temperature range
of - 55 DC to 125 DC. The SN74HC' family is
characterized for operation from - 40 DC to
85 D C.
3
2
U
UN
>I(!)
II
1 20 19
A6
Y6
en
w
NC
AS
Y5
(J
:>w
c
en
SN54HC367. SN54HC368 ..• J PACKAGE
SN74HC367. SN74HC368 ... J OR N PACKAGE
o
(TOP VIEWI
1G
1A1
lY1
1A2
1Y2
1A3
1Y3
GND
1
U
16
15
14
4
13
5
12
11
6
10
9
:E
(J
VCC
2<3
2A2
2Y2
2A1
2Yl
lA4
1Y4
J:
SN54HC367. SN54HC368 ... FH OR FK PACKAGE
SN74HC367. SN74HC368 ... FH OR FN PACKAGE
(TOP VIEWI
~
<{ I(!) U
U
UI(!)
~~Z>N
3
2 1 20 19
1Y1
lA2
NC
1Y2
2A2
2Y2
NC
2A1
2Y1
maximum ratings. recommended operation conditions.
and electrical characteristics
See Table III, page 2-8.
NC-No internal connection
Copyright © 1982. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-257
TYPES SN54HC365 THRU SN54HC368
SN74HC365 THRU SN74HC368
HEX BUS DRIVERS WITH 3·STATE OUTPUTS
logic symbols
'HC365
'HC366
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
V6
'HC367
'He368
10
11
:t:
1A1
1Y1
1A2
1Y2
lY2
1A3
1A4
1Y3
1V3
lY4
lY4
lYl
o
20
o
en
2A1
2Y1
2Yl
2A2
2Y2
2Y2
~
c
m
logic diagrams (positive logic)
<
'HC365
(=;
01
m
(1)
'HC366
(;1
'HC367
'HC368
(1)
en
(11)2Yl
Pin numbers shown are for J and N packages.
3-258
-I!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
(11) 2Yl
TYPES SN54HC365 THRU SN54HC368
SN74HC365 THRU SN74HC368
HEX BUS DRIVERS WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), Cl = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
vCC
TA = 25°C
TYP MAX
MIN
2V
SN54HC'
MIN
SN74HC'
MAX
MIN
MAX
50
12
10
95
145
120
19
16
29
25
24
20
tpd
A
Y
4.5 V
6V
285
G
y
4.5 V
100
26
190
ten
38
57
238
48
6V
21
32
48
41
2V
50
175
265
240
4.5 V
6V
2V
21
19
35
30
53
45
48
41
28
75
8
60
12
90
4.5 V
18
15
6V
6
10
15
13
2V
tdis
G
y
Any
tt
Power dissipation capacitance per driver
UNIT
ns
ns
ns
ns
35 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), Cl= 150 pF (see Note 1)
PARAMETER
tpd
ten
tt
FROM
(INPUT)
A
G
TO
(OUTPUT)
Y
y
VCC
TA = 25°C
MIN
TYP MAX
2V
4.5 V
70
17
SN54HC'
MIN
120
24
SN74HC'
MAX
180
30
285
57
14
20
2V
140
345
4.5 V
30
230
46
6V
28
45
59
315
17
39
210
42
13
36
53
6V
MAX
150
36
31
6V
2V
4.5 V
MIN
69
63
UNIT
CJ)
W
(.)
>
W
ns
25
C
CJ)
o
ns
~
(.)
48
265
53
45
II
:r:
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
\
TEXAS.
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-259
J:
o
s:
otJ)
C
m
<
o
m
tJ)
3-260
TYPES SN54HC373. SN74HC373
OCTAL D·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
•
8 High·Current Latches in a Single Package
•
High·Current 3·State True Outputs Can
Drive up to 15 LSTTL Loads
•
Full Parallel Access for Loading
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC373 ... J PACKAGE
SN74HC373 , , , J OR N PACKAGE
(TOP VIEW)
description
oe
Vee
10
10
20
20
30
30
80
80
70
70
60
60
50
50
e
GNO
These 8-bit latches feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
SN54HC373 .. , FH OR FK PACKAGE
SN74HC373 , , , FH OR FN PACKAGE
(TOP VIEW)
The eight latches of the 'HC373 are transparent
D-type latches. While the enable (C) is high the
Q outputs will follow the data (D) inputs. When
the enable is taken low, the Q outputs will be
latched at the levels that were set up at the D
inputs.
An output-control input (DC) can be used to
place the eight outputs in either a normal logic
state (high or low logic levels) or a highimpedance state. In the high-impedance state
the outputs neither load nor drive the bus lines
significantly. The high-impedance third state and
increased drive provide the capability to drive the
bus lines in a bus-organized system without need
for interface or pull-up components.
II
u
9~rc5~g
en
80
70
70
60
60
20
30
30
40
w
c.J
>
w
C
en
o
aeuae
'
w
ns
ns
ns
C
en
o
:!
o
J:
100 pF typ
Power dissipation capacitance per latch
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-263
TYPES SN54HC373, SN74HC373
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
D
Q
tpd
C
Any
Q
ten
OC
Any
Q
tt
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
'2 V
4.5 V
6V
TA = 25°C
MIN TYP MAX
82 200
40
22
34
19
100 225
24
45
20
38
90 200
23
40
19
34
45 210
17
42
13
36
SN54HC373
MIN TYP MAX
300
60
51
335
67
57
300
60
51
315
63
53
SN74HC373
MIN TYP MAX
250
50
43
285
57
48
250
50
43
265
53
45
UNIT
ns
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
o
::I:
("')
s
o
(J)
C
m
<
n
m
latch signal conventions
It is TI practice to name the outputs and other inputs of a O-type latch and to draw its logic symbol based
on the assumption of true data (0) inputs. Then outputs that produce data in phase with the data inputs
are called Q and those producing complementary data are called O. An input that causes a Q output to
go high or a 0 output to go low is called Preset; an input that causes a Q output to go high or a Q output
to go low is called Clear. Bars are used over these pin names (PRE and CLR) if they are active-low.
In some applications it may be advantageous to redesignate the data input D. In that case all the other
inputs and outputs should be renamed as shown below. Also shown are corresponding changes in the
graphical symbol. Arbitrary pin numbers are shown in parentheses.
(J)
Notice that Q and Q exchange names, which causes Preset and Clear to do likewise. Also notice that the
polarity indicators ( I::::::.. ) on PRE and CLR remain since these inputs are still active-low, but that the presence
or absence of the polarity indicator changes at 5, Q, and Q. Of course pin 5 (0) is still in phase with the
data input 0, but now both are considered active low.
3-264
TEXAS
~
INSTRUMENTS
POST OFFICE BOX ~25012 • DALLAS. TEXAS 75265
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC374, SN74HC374
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS
WITH 3·STATE OUTPUTS
02684, DECEMBER 1982-REVISED MARCH 1984
SN64HC374 ..• J PACKAGE
SN74HC374 ... J OR N PACKAGE
. (TOP VIEW)
•
8 D·Type Flip-Flops in a Single Package
•
High-Current 3-State True Outputs Can
Drive up to 15 LSTTL Loads
•
Full Parallel Access for Loading
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
description
These 8-bit flip-flops feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
20
20
30
30
40
L
H
X
ex>
en
80
70
70
60
60
w
(J
>
W
c
:!:
(J
:r:
logic symbol
(2) 10
(5) 20
3D
4D
5D
6D
8D
(61
30
(91 40
(12)
sa
(15) 60
(16)
70
(19) SO
OUTPUT
INPUTS
L
>
en
FUNCTION TABLE (EACH FLlP·FlOP)
l
II
U
diu Ud
o
7D
l
elK
.- .-Ib
The SN54HC374 is characterized for operation
over the full military temperature range of
- 55 °C to 125°C. The SN74HC374 is
characterized for operation from - 40°C to
85°C.
ClK
f
f
80
80
70
70
60
60
50
50
o
The output control (OC) does not affect the
internal operation of the flip-flops. Old data can
be retained or new data can be entered while the
outputs are in the high-impedance state.
~
Vee
10
10
20
20
30
30
40
40
GNO
SN64HC374 .•. FH OR FK PACKAGE
SN74HC374 •.. FH OR FN PACKAGE
(TOP VIEW)
The eight flip-flops of the 'HC374 are edgetriggered D-type flip-flops. On the positive
transition of the clock the Q outputs will be set
to the logic levels that were set up at the D
inputs.
An output-control input can be used to place the
eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state.
In the high-impedance state the outputs neither
load nor drive the bus lines significantly. The
high-impedance third state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pull-up components.
oe
D
Q
H
H
l
l
X
X
Qo
Z
Copyright ©1982 by Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 15265
3-265
TYPES SN54HC374. SN74HC374
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS
WITH 3·STATE OUTPUTS
logic diagram (positive logic)
141
20---H
17_1
30_
--+-I
(81
40---H
1131
50---H
III
J:
C')
1171
70---+-t
S
o
(J)
80.;....11_81_---t
C
:sm
maximum ratings, recommended operating conditions, and electrical characteristics
C')
m
See Table III, page 2-8.
(J)
3-266
-iii
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS, TEXAS 75265
31
TYPES SN54HC374. SN74HC374
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS
WITH 3·STATE OUTPUTS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
VCC
Clock frequency
fclock
I
eLK high 0' low
tw
Pul.. du,""..
tsu
Setup time. data before ClK t
Hold time. data after ClK t
th
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MAX
MIN
0
0
0
80
16
14
100
20
6
30
35
17
5
5
5
SN54HC374
MAX
MIN
4
0
20
0
24
0
120
24
20
150
30
25
5
5
5
SN74HC374
MIN
MAX
UNIT
5
24
28
MHz
0
0
0
100
20
17
ns
125
25
21
5
5
5
ns
ns
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL ::: 50 pF (see Note 1)
,
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
2V
4.5 V
6V
2V
f max
tpd
ClK
Any
ten
OC
Any
tdis
OC
Any
tt
Cpd
Vcc
Any
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TVP MAX
12
6
30
60
35
70
180
63
17
36
15
31
150
60
30
16
14
26
150
36
17
30
16
26
60
28
12
8
10
6
SN54HC374
MAX
MIN
4
20
24
Power dissipation capacitance per flip-flop
SN74HC374
MIN
MAX
5
24
UNIT
225
45
38
190
38
32
ns
o
:>w
C
en
ns
190
38
32
75
15
13
en
w
MHz
28
270
54
46
225
45
38
225
45
38
90
18
15
II
ns
o
~
o
:I:
ns
100 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
!l4
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-267
TYPES SN54HC374, SN74HC374
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS
WITH·3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
f max
tpd
ClK
Any
ten
OC
Any
tt
II
Any
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
12
6
60
30
70
35
230
80
22
46
19
39
70
200
25
40
22
34
45
210
17
42
13
36
SN54HC374
MAX
MIN
4
20
24
345
69
58
300
60
51
315
63
53
SN74HC374
MIN
MAX
5
24
28
290
58
49
250
50
43
265
53
45
UNIT
MHz
ns
ns
ns
NOTE 1: For load ·circuit and voltage waveforms, see page 1-14.
o flip-flop signal conventions
:J:
o
s:
o
en
c
m
<
o
m
It is TI practice to name the outputs and other inputs ofa D-type flip-flop and to draw its logic symbol
based on the assumption of true data (D) inputs. Then outputs that produce data in phase with the data
inputs are called 0 and those producing complementary data are called O. An input that causes a 0 output
to go high or a Q output to go low is called Preset; an input that causes a 0: output to go high or a 0
output to go low is called Clear. Bars are used over these pin names (PRE and CLR) if they are active-low.
In some applications it may be advantageous to redesignate the data input D. In that case all the other
inputs and outputs should be renamed as shown below. Also shown are corresponding changes in the
graphical symbol. Arbitrary pin numbers are shown in parentheses.
en
(6)a
Notice that 0 and Q exchange names, which causes Preset and Clear to do likewise. Also notice that the
polarity indicators ( ~ ) on PRE and CLR remain since these inputs are still active-low, but that the
presence or absence of the polarity indicator changes at 5, 0, and O. Of course pin 5 (0) is still in phase
with the data input 5, but now both are considered active-low.
38~
3-268
TEXAS •
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS. TEXAS 75265
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC377. SN54HC378. SN54HC379
SN74HC377. SN74HC378. SN74HC379
OCTAL. HEX. AND QUAD D·TYPE FLlp·FLOPSWITH CLOCK ENABLE
02684, DECEMBER 1982-REVISED MARCH 1984
•
'HC377 and 'HC378 Contain Eight and Six
Flip·Flops, Respectively, with Single· Rail
Outputs
•
'HC379 Contains Four Flip-Flops with
Double-Rail Outputs
•
Clock Enable Latched to Avoid False
Clocking
•
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC377 ... J PACKAGE
SN74HC377 ... J OR N PACKAGE
(TOP VIEW)
G
VCC
80
80
70
70
60
60
50
50
ClK
10
10
20
20
30
3D
40
40
GNO
description
These circuits are positive-edge-triggered Ootype
flip-flops with an enable input. The 'HC377,
'HC378, and 'HC379 devices are similar to
'HC273, 'HC174, and 'HC175 respectively, but
feature a latched clock enable (G) instead of a
common clear,
Information at the 0 inputs meeting the setup
time requirements is transferred to the Q outputs
on the positive-going edge of the clock pulse if
G is low. Clock triggering occurs at a particular
voltage level and is not directly related to the
transition time of the positive-going pulse. When
the clock input is at either the high or low level,
the 0 input signal has no effect at the output.
The circuits are designed to prevent false
clocking by transitions at the G input.
The
SN54HC377,
SN54HC378,
and
SN54HC379 are characterized for operation
over the full military temperature range of
- 55 DC to 125 DC. The SN74HC377,
SN74HC378,
and
SN74HC379
are
characterized for operation from - 40 DC to
85 D C.
SN54HC377 ... FH OR .FK PACKAGE
SN74HC377 ... FH OR FN PACKAGE
(TOP VIEW)
001'"
~O
II
~.-,,-,>Q)
20
20
30
3D
40
en
w
(.)
60
60
:>w
c
en
o
SN54HC378 ... J PACKAGE
SN74HC378 ... J OR N PACKAGE
(TOPVIEW)
G
:2
(.)
:I:
VCC
60
60
50
50
40
40
ClK
10
10
20
20
3D
GNO
SN54HC378 ... FH OR FK PACKAGE
SN74HC378 ... FH OR FN PACKAGE
(TOP VIEW)
o~
\c:l
u
Z
~O
> co
10
20
60
50
NC
NC
20
3D
50
40
o 0 u ~ 0
M{5Zd'
W
C
en
2
(.)
o
J:
(2) 10
10 (4)
(3) 10
(7) 20
20 (5)
(6) 20
3D (12)
(11) 30
40 (13)
(15) 40
(14) 40
FUNCTION TABLE
(10) 30
(EACH FLIP-FLOP)
OUTPUTS
INPUTS
G
CLOCK
DATA
0
0
H
X
L
t
X
H
00
H
00
L
L
t
L
L
H
X
L
X
00
00
Pin numbers shown are for J and N packages.
4
TEXAS "'"
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-271
TYPES SN54HC377, SN54HC378, SN54HC379
SN74HC377, SN74HC378, SN74HC379
OCTAL, HEX, AND QUAD D·TYPE FLlP·FLOPS WITH CLOCK ENABLE
maximum ratings, recommended operating conditions, and electrical characteristics
'HC377, 'HC378: See Table IV, page 2-6.
'HC379: See Table II, page 2-4.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
2V
4.5 V
Clock frequency
fclock
Pulse duration, ClK high or low
tw
D
II
Set up time
tsu
before ClKt
low
J:
o
S
o
en
cm
Ghigh or
Hold time after ClK t
th
TA = 25°C
MAX
MIN
5
0
MIN
SN54HC'
MAX
MIN
SN74HC'
MAX
0
3
0
4
0
25
0
16
0
20
6V
2V
0
100
29
0
150
19
0
125
23
4.5 V
20
30
25
6V
2V
25
150
21
125
4.5 V
17
100
20
30
25
6V
17
21
UNIT
MHz
ns
ns
2V
100
25
150
4.5 V
20
30
25
6V
'2 V
4.5 V
17
0
25
0
21
0
0
0
0
6V
0
0
0
125
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
S
o
m
FROM
(INPUT)
VCC
2V
4.5 V
-
f max
en
TO
(OUTPUT)
6V
tpd
ClK
Any
2V
4.5 V
6V
2V
tt
Any
TA = 25°C
TYP MAX
MIN
11
5
SN74HC'
MAX
MIN
25
54
3
16
20
29
64
19
23
56
15
12
4.5 V
38
8
6V
6
Power dissipation capacitance
SN54HC'
MIN
MAX
4
MHz
160
32
240
48
27
75
41
200
40
34
110
95
15
22
19
13
19
16
No load, TA = 25°C
UNIT
ns
ns
30 pF typ
NOTE .1: For load circuit and voltage waveforms, see page 1-14.
3:
3-272
TEXAS"
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC386. SN74HC386
QUADRUPLE 2·INPUT EXCLUSIVE·OR GATES
D26B4, DECEMBER 19B2-REVISED MARCH 19B4
•. Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN54HC3B6 ... JPACKAGE
SN74HC386 ... J OR N PACKAGE
(TOP VIEW)
1A
• Dependable Texas Instruments Quality and Reliability
VCC
48
18
1Y
2Y
4A
4Y
2A
3Y
28
GND
38
3A
description
These devices contain four independent 2-input ExclusiveOR gates. They perform the Boolean functions
Y = A (j) B =AB + AS in positive logic.
SN54HC386 ... FH OR FK PACKAGE
SN74HC3B6 ... FH OR FN PACKAGE
(TOP VIEW)
A common application is as a true/complement element. If one
of the inputs is low, the other input will be reproduced in true
form at the output. If one of the inputs is high, the signal on
the other input will be reproduced inverted at the output.
The SN54HC386 is characterized for operation over the full
military temperature range of - 55°C to 125°C. The
SN74HC386 is characterized for operation from - 40°C to
85°C.
logic symbol
1Y
4A
NC
2Y
NC
4Y
NC
2A
NC
3Y
II
U)
W
(J
FUNCTION TABLE
lA (11
-1
2A (51
INPUTS
A
B
L
L
H
L
(41 2Y
2B (61
(81
3A
(91
38
(121
4A
(131
>
W
leach gate)
(31 1Y
lB (21
(101 3Y
(111 4Y
4B
OUTPUT
Y
L
C
U)
NC-No internal connection
o
H
H
L
H
H
H
L
:e
(J
:r:
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
Y
VCC
TA = 25°C
MIN TYP MAX
SN54HC386
MIN
MAX
SN74HC386
MIN
MAX
2V
40
100
150
125
4.5 V
30
25
21
95
6V
2V
12
10
20
17
28
75
4.5 V
8
15
25
110
22
6V
6
13
19
19
16
UNIT
ns
ns
Power dissipation capacitance per gate
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
Copyright © 19B2 by Texas Instruments Incorporated
TEXAS
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-273
lEI
:I:
o
~
o
CJ)
C
m
<
o
m
CJ)
3-274
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC390, SN54HC393~SN74HC39t SN74HC393
DUAL 4·BIT DECADE AND BINARY COUNTERS
02684. DECEM8ER 1982-REVISED MARCH 1984
•
'HC390 ... Individual Clock for A and B
Flip·Flops Provide Dual + 2 and + 5
Counters
•
'HC393 .•. Dual 4·Bit Binary Counter with
Individual Clocks
•
All Have Direct Clear for Each 4-Bit Counter
•
Dual 4-Bit Versions Can Significantly
Improve System Densities by Reducing
Counter Package Count by 50%
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
SN54HC390 ... J PACKAGE
SN74HC390 ... J OR N PACKAGE
(TOP VIEW)
lCKA
lClR
lOA
lCKB
laB
lac
lao
GNO
vcc
2CKA
2ClR
20A
2CKB
20B
20C
20 0
SN54HC390 ... FH OR FK PACKAGE
SN74HC390 ... FH OR FN PACKAGE
(TOP VIEW)
Dependable Texas Instruments Quality and
Reliability
II
description
lOA
lCKB
NC
laB
lac
Each of these monolithic circuits contains eight
flip-flops and additional gating to implement two
individual four-bit counters in a single package.
The 'HC390 incorporates dual divide-by-two and
divide-by-five counters, which can be used to
implement cycle lengths equal to any whole
and/or cumulative multiples of 2 and/or 5 up to
divide-by-100. When connected as a biquinary
counter, the separate divide-by-two circuit can
be used to provide symmetry (a square wave)
at the final output stage. The 'HC393 comprises
two independent four-bit binary counters each
having a clear and a clock input. N-bit binary
counters can be implemented with each package
providing the capability of divide-by-256. The
'HC390 and 'HC393 have parallel outputs from
each counter stage so that any submultiple of
the input count frequency is available for systemtiming signals.
2ClR
20A
NC
2CKB
20a
4
5
6
7
8
00 U
0
U
("oj
("oj
en
w
(.)
>
W
c
02200
...
l!)
en
o
SN54HC393 ... J PACKAGE
SN74HC393 ... J OR N PACKAGE
(TOP VIEW)
:2E
(.)
J:
lClK
VCC
lCLR
2ClK
lOA
2ClR
laB
20A
lac
20B
lao
20c
GNO __________.....- 20 0
SN54HC393 ... FH OR FK PACKAGE
SN74HC393 ... FH OR FN PACKAGE
(TOP VIEW)
The SN54HC390 and SN54HC393 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74HC390 and SN74HC393 are characterized
for operation from - 40°C to 85 °C.
5:S
u:S
3 2
1 2019
u
UU2~~
2CLR
NC
20A
NC
20B
lOA
NC
NC
lac
o
o
...
0
u
0
u
("oj
("oj
2 20 0
l!)
NC - No internal connection
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright ©1982 by Texas Instruments Incorporated
3-275
TYPES SN54HC390, SN74HC390
DUAL 4·81T DECADE COUNTERS
logic symbol
logic diagram, each counter (positive logic)
CLR------I
CKA---------d
~-------~-~
10s
10 C
CKB---------~~~
100
t----Oc
lEI
20s
20c
:J:
n
~
o
J--+-Qo
200
o
C
Pin numbers shown are for J and N packages.
m
n
W
Pin numbers shown are for J and N packages.
C
tn
FUNCTION TABLE
0
COUNT SEQUENCE
2
(EACH COUNTER)
COUNT
0
1
2
3
4
5
6
7
8
9
10
QO
L
QC
L
L
L
L
L
L
L
L
H
L
H
H
H
H
12
H
H
13
H
11
(.)
OUTPUT
QB
L
QA
L
L
L
H
L
H
H
H
L
L
H
H
H
H
H
L
H
L
L
L
L
L
L
H
H
L
H
H
L
H
H
L
L
H
H
H
H
14
H
H
15
H
H
J:
L
L
L
L
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012- DALLAS. TEXAS 75265
3-277
TYPES SN54HC390, SN74HC390
DUAL 4-BIT BINARY COUNTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
vcc
CKA
fclock
Clock frequency
CK8
CKA high
or low
tw
lEI
J:
Pulse duration
CKB high
or low
ClR high
tsu
("')
Setup time, ClR inactive
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
0
6
0
31
0
36
0
6
0
31
0
36
80
16
14
80
16
14
80
16
14
25
SN54HC390
MIN
MAX
0
4.2
21
0
0
0
0
0
120
24
20
120
24
20
120
24
20
25
5
5
5
5
s:o
en
cm
S
("')
m
en
3-278
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
25
4.2
21
25
SN74HC390
MAX
MIN
0
0
0
0
0
0
100
20
18
100
20
18
100
20
18
25
5
5
5
25
28
5
25
28
UNIT
MHz
ns
ns
TYPES SN54HC390, SN74HC390
DUAL 4-BIT BINARY COUNTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
FROM
(INPUT)
TO
(OUTPUT)
CKA
'OA
CKB
Os
tpd
CKA
OA
tpd
CKA
Oc
tpd
CKB
Os
tpd
CKS
Oc
tpd
CKB
PARAMETER
fmax
tpHL
tt
CLR
°D
Any
Any
vcc
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
6
10
31
50
36
60
6
10
31
50
36
60
50 120
24
16
20
13
100 290
5S
35
50
30
58 130
18
26
15
22
83 185
26
37
21
32
60 130
26
18
22
14
45 165
17
33
28
14
75
28
15
8
13
6
SN54HC390
MAX
MIN
4.2
21
25
4.2
21
25
180
35
31
430
87
74
195
39
33
280
55
48
195
39
33
250
49
42
110
22
19
Power dissipation capacitance per counter
SN74HC390
UNIT
MIN
MAX
5
25
28
MHz
5
25
28
150
30 ns
26
365
ns
72
62
165
ns
33
28
230
ns
46
40
160
ns
33
28
205
41
ns
35
95
ns
19
16
II
en
w
o
:;
w
c
en
o
:E
o
J:
40 pF typ
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS . . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-279
TYPES SN54HC393, SN74HC393
DUAL 4·BIT BINARY COUNTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
Clock frequency
fclock
ClK
ClK high
Pulse duration
ClR high
Setup time, ClR inactive
tsu
II
SN54HC393
MIN
MAX
4.2
SN74HC393
UNIT
MIN
MAX
5
0
2V
0
6
0
4.5 V
0
31
0
21
0
25
6V
2V
0
36
0
25
0
28
80
16
4.5 V
6V
or low
tw
TA = 25°C
MAX
MIN
MHz
100
20
120
24
14
20
18
2V
80
100
4.5 V
16
120
24
6V
14
20
18
2V
4.5 V
25
5
25
5
25
5
6V
5
5
5
ns
20
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
::I:
FROM
(INPUT)
TO
(OUTPUT)
Vce
2V
6
QA
4.5 V
31
10
50
6V
2V
36
60
(")
S
o
en
f max
c
ClK
S
(")
30
26
100
290
430
360
32
58
87
72
6V
24
50
74
62
250
49
205
41
42
35
4.5 V
2V
45
165
4.5 V
6V
17
14
33
28
2V
28
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance per counter
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
3-280
MHz
150
Qo
Any
28
36
31
ClK
tt
25
180
tpd
Any
25
24
20
4.5 V
6V
2V
ClR
-f-
5
21
120
QA
tpHl
SN74HC393
UNIT
MIN
MAX'
15
13
ClK
m
en
SN54HC393
MAX
MIN
4.2
50
tpd
m
TA = 25°C
TYP MAX
MIN
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265
40 pF typ
ns
ns
ns
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC490, SM74HC490
DUAL 4·81T DECADE COUNTERS
02684, DECEM8ER 1982-REVISED MARCH 1984
SN54HC490 .•• J PACKAGE
SN74HC490 .•• J OR N PACKAGE
(TOP VIEW)
•
Individual Clock, Direct Clear, and Set-to-9
Inputs for Each Decade Counter
•
Dual Counters Can Significantly Improve
System Densities as Package Count Can be
Reduced by 50%
•
•
VCC
2CLK
2CLA
,1CLK
lCLR
lOA
15ET9
Package Options Include Both Plastic and
Ceramic Chip Carriers In Addition to Plastic
and Ceramic DIPs
20A
25ET9
laB
lac
lao
GNO
Dependable Texas Instruments Quality and
Reliability
description
20B
20c
20 0
SN54HC490 •.• FH OR FK PACKAGE
SN74HC490 ••. FH OR FN PACKAGE
(TOP VIEW)
Each of these monolithic circuits contains eight
master-slave flip-flops and additional gating to
implement two individual 4-bit decade counters
in a single package. Each decade counter has
individual clock, clear, and set-to-9 inputs. BCD
count sequences of any length up to divideby-100 may be implemented with a single
'HC490. The counters have parallel outputs from
each counter stage so that submultiples of the
input count frequency are available for system
timing signals.
II
3 2 1 2019
2CLR
til
20A
NC
2SET9
14
W
(.)
>
20B
W
C
9 10111213
The SN54HC490 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC490 is
characterized for operation from - 40°C to
85°C.
0 0 (.)
0
(.)
til
ozzoo
.- (!l
N N
o
:E
NC-No internal connection
(.)
l:
CLEAR/SET-TO-9
FUNCTION TABLE
(EACH COUNTER)
INPUTS
OUTPUTS
CLEARSET-TO-9 QA QB QC
H
L
L
L
L
H
L
H
L
L
L
L
COUNT
BCD COUNT SEQUENCE
(EACH COUNTER)
OUTPUT
COUNT
QO Oc OB QA
QO
L
H
0
1
2
3
4
5
6
7
8
9
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
L
H
L
H
Copyright © 1982. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 15265
3-281
TYPES SN54HC490, SN74HC490
DUAL 4·811 DECADE COUNTERS
logic symbol
CTROIV10
(3) 10A
1CLR (2)
1SET9 (4)
CT=O
CT=9
CT{03
+
(5) 10B
(6)
(7)
10C
10
0
(13) 20A
2CLR (14)
(11 )
20B
(10) 20C
2SET9 (12)
(9)
200
_ _ Pin numbers shown are for J and N packages.
_ _ logic diagram, each counter (positive logic)
::I:
0
S
0
CJ)
ClR
SET9
ClK
C
m
<
0
m
CJ)
t-t--
3-282
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Qc
TYPES SN54HC490, SN74HC490
DUAL 4·81T DECADE COUNTERS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
2V
Clock frequency
fclock
Pulse duration. any input
tw
Setup time. ClR or set-to-9 inactive
tsu
TA = 25°C
MIN
MAX
0
6
SN54HC490
MIN
0
SN74HC490
MAX
4.2
MIN
0
4.5 V
0
31
0
21
0
6V
0
36
0
120
25
0
100
2V
80
4.5 V
16
24
20
6V
2V
14
25
20
25
18
25
4.5 V
5
5
5
6V
5
5
5
MAX
5
25
UNIT
MHz
28
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA = 25°C
MIN
TYP MAX
2V
f max
ClK
tpd
tplH
ClK
°A
Os. 00
ClK
Oc
Set-to-9
OA.OO
Set-to-9
OS.OC
tpHl
Clear
Any
Any
SN74HC490
MIN
MAX
4.5 V
21
25
6V
36
25
28
MHz
lZ5
190
38
12
25
21
155
31
32
26
2V
4.5 V
50
15
6V
2V
80
185
280
230
4.5 V
23
37
56
46
6V
18
31
48
2V
100
235
355
39
295
4.5 V
6V
30
23
47
40
71
60
59
50
2V
4.5 V
60
185
280
230
19
37
56
46
6V
16
54
31
48
39
140
210
175
6V
18
16
28
24
2V
4.5 V
50
17
130
42
36
195
35
30
165
26
39
33
15
22
28·
8
6
75
33
110
28
95
22
19
16
2V
4.5 V
2V
4.5 V
15
13
Power dissipation capacitance per counter
UNIT
5
4.2
6V
Cpd
MAX
6
31
6V
tt
SN54HC490
MIN
19
II
en
w
(J
>
W
c
en
o
ns
~
(J
J:
ns
ns
ns
40 pF typ
NOTE 1: For load circuits and voltage waveforms. see page 1-14.
TEXAS
"'11
INSTRUMENTS
POST OFFice BOX 225012. DALLAS. TeXAS 15265
3-283
J:
o
!s:
o(J)
C
m
<
(=)
m
(J)
3-284
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC563. SN74HC563
OCTAL D·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
02684, DECEMBER 1982-REVISED MARCH 1984
•
High-Current 3-State Outputs Drive BusLines Directly or up to 1 5 LSTTL Loads
•
Bus-Structured Pinout
•
Package Options Include Both Plastic
and Ceramic Chip Carriers in Addition to
Plastic and Ceramic DIPs
•
Dependable Texas Instruments Quality
and Reliability
SN54HC563 ... J PACKAGE
SN74HC563 .•• J OR N PACKAGE
ITOPVIEW)
De
description
These 8-bit latches feature three-state outputs
designed specifically for driving highly
capacitive or relatively low-impedance loads.
They are particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus
.
drivers, and working registers.
15
25
35
45
55
65
75
85
e
SN54HC563 ••• FH OR FK PACKAGE
SN74HC563 ••• FH OR FN PACKAGE
II
ITOPVIEW)
°N O!U
~Id
.... O>
....
The eight latches are transparent O-type
latches. While the enable (C) is high the Q
outputs will follow the complements of data (0)
inputs. When the enable is taken low the
outputs will be latched at the inverses of the
levels that were set up at the 0 inputs.
3
2
en
w
1 2019
25
35
3D
40
50
60
70
An output-control input can be used to place
the eight outputs in either a normal logic state
(high or low logic levels) or a high-impedance
state. In the high-impedance state the outputs
neither load nor drive the bus lines significantly.
The high-impedance state and increased highlogic level provide the capability to drive the
bus lines in a bus-organized system without
. need for interface or pull-up components.
(.)
:>
w
40
50
60
c
en
9 1011 1213
o
0 0 Uldld
OOZ
00"
~
l!)
(.)
J:
FUNCTION TABLE
lEach Latch)
INPUTS
OUTPUT
ENABLE
The output control (OC) does not affect the
internal operation of the latches. Old data can
be retained or new data can be entered while
the outputs are in the high-impedance state.
The SN54HC563 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC563 is
characterized for operation from - 40°C to
85°C.
TEXAS
Vee
10
20
3D
40
50
60
70
80
GNO
'1!1
a
OC
C
D
L
H
H
L
L
H
L
H
L
L
X
X
X
Qo
H
Copyright © 1982 by
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS, TEXAS 75265
Z
Tex~s
Instruments Incorporated
3-285
TYPES SN54HC563. SN74HC563
OCTAL O·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
logic symbol
oc
c
(1),...,
(11)
(2)
10
(3)
20
3D
40
(4)
(5)
(6)
50
(7)
60
70
II
80
(8)
(9)
logic diagram (positive logic)
-
(1)
oc----oa
EN
,
C1
10
t>
r
\l
~
(19)
1'0
1 0 - - - - + -.....
~ 20
r-....
(17)
30
40
50
(16)
(15)
r--.. (14)
~
(12)
20
60
70
80
30
::I:
o
~
4 0 - - - - + -......
o(/)
C
m
5 0 - - - - + -......
:!S
o
m
(/)
6 0 - - - - + -.....
70----+--4
8 0 - - - -......
3-286
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC563, SN74HC563
OCTAL O·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2·8.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
vcc
tw
Pulse duration, enable C high
tsu
Setup time, data before
enable C ~
th
Hold time, data after enable C ~
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA
= 25"C
MIN
MAX
80
16
14
50
10
9
5
5
5
SN54HC563
MIN
MAX
120
24
20
75
15
13
5
5
5
SN74HC563
MIN
MAX
100
20
17
63
13
11
5
5
5
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL == 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
0
IT
tpd
C
Any
ten
OC
Any
tdis
OC
Any
tt
Any
Vcc
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA
MIN
25"C
os
TYP
17
26
23
90
27
23
70
24
21
47
23
21
28
8
6
MAX
175
SN54HC563
MAX
MIN
265
SN74HC563
MIN
MAX
220
35
30
175
35
30
150
30
26
150
30
26
60
12
10
53
45
265
53
45
225
45
38
225
45
38
90
18
15
44
38
220
44
38
190
38
32
190
ns
38
32
75
15
13
ns
Power dissipation capacitance per latch
UNIT
ns
II
en
w
CJ
:>
w
c
en
o
~
ns
CJ
J:
ns
50 pF typ
NOTE 1: For load circuits and voltage waveforms, see page 1-14.
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-287
TYPES SN54HC563, SN74HC563
OCTAL O·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
.
II
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
D
Q
tpd
C
Any
ten
OC
Any
tt
NOTE I, Fm ,,,'
vcc
MIN
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Any
0;"",,, 00' v,It.,. wov.'mm,. , .. p'"
TA·25°C
TYP MAX
200
95
40
33
34
29
103
225
33
45
29
38
85
200
40
29
26
34
210
60
42
17
14
36
SN54HC563
MIN
MAX
300
60
51
335
67
57
300
60
51
315
. 63
53
SN74HC563
MIN
MAX
250
50
43
285
57
48
250
50
43
265
53
45
UNIT
ns
ns
ns
ns
1-14.
D latch signal conventions
:I:
C')
S
o
en
c
m
<
C')
It is TI practice to name the outputs and other inputs of a Ootype latch and to draw its logic symbol based
on the assumption of true data (0) inputs. Then outputs that produce data in phase with the data inputs
are called a and those producing complementary data are called Q. An input that causes a a output to go
high or a 0 output to go low is called Preset; an input that causes a Q output to go high or a a output to go
low is called Clear. Bars are used over these pin names (PRE and CLR) if they are active-low.
In some applications it may be advantageous to redesignate the data input D. In that case all the other
inputs and outputs should be renamed as shown below. Also shown are corresponding changes in the
graphical symbol. Arbitrary pin numbers are shown in parentheses.
m
en
s
10
R
Notice that a and 0 exchange names, which causes Preset and Clear to do likewise. Also notice that the
polarity indicators ( t:::::::,.. ) on PRE and CLR remain sipce these inputs are still active-low, but that the
presence or absence of the polarity indicator changes at 0, a, and O. Of course pin 5 (0) is still in phase
with the data input 0, but now both are considered active-low.
3-288
,
TEXAS-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
HIGH·SPEED
CMOS LOGIC
TYPES SN54HCT563, SN74HCT563
OCTAL D·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
02804, MARCH 1984
SN54HCT563 ... J PACKAGE
SN74HCT563 ... J OR N PACKAGE
•
Inputs are TTL·Voltage Compatible
•
High·Current 3·State Outputs Drive BusLines Directly or up to 15 LSTTL Loads
(TOP VIEWI
•
Bus-Structured Pinout
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
description
These 8-bit latches feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, 1/0 ports, bidirectional bus drivers, and
working registers.
The eight latches are transparent Ootype latches.
While the enable (C) is high the Q outputs will
follow the complements of the data (0) inputs.
When the enable is taken low the outputs will
be latched at the inverses of the levels that were
set up at the 0 inputs.
De
Vee
10
20
30
40
50
60
70
80
GNO
10
20
30
40
50
60
70
80
SN54HCT563 ... FH OR FK PACKAGE
SN54HCT563 ... FH OR FN PACKAGE
II
(TOP VIEWI
U
~ ~Ig ~I~
en
W
20
30
40
50
60
70
(.)
30
:>W
40
50
60
An output-control input can be used to place the
eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state.
In the high-impedance state the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and increased high-logic
level provide the capabifity to drive the bus lines
in a bus-organized system without need for
interface or pull-up components.
The output control (OC) does not affect the
internal operation of the latches. Old data can
be retained or new data can be entered while the
outputs are in the high-impedance state.
e
Q
en
0
C C UIOIO
CO2
cor-..
~
(!)
(.)
~
FUNCTION TABLE
(Each Latch)
INPUTS
OUTPUT
ENABLE
Q
OC
C
D
L
H
H
H
L
L
H
L
L
X
X
X
00
H
L
Z
The SN54HCT563 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCT563 is
characterized for operation from - 40°C to
85°C.
TEXAS·~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TeXAS 75265
Copyright © 1984, Texas Instruments Incorporated
3-289
TYPES SN54HCT563, SN74HCT563
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
logic symbol
logic diagram (positive logic)
c
10
20
30
40
50
60
3D (4)
70
80
40 -,-(5-,-)_-+-.....
•
50 -,-(6-,-)_-+-1
::r:
o
3:
60 (7)
oo
70 (8)
C
m
• 8D....;.(9....;.)_ _-l~
<
n
m
o
maximum ratings, recommended operating conditions, and electrical characteristics
See Table VII, page 2·14.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
tw
Pulse dUration. enable C high
tsu
Setup time. data before enable C ~
th
Hold time. data after enable C ~
TA = 25°C
MIN
MAX
SN54HCT563
MAX
MIN
4.5 V
20
30
25
5.5 V
4.5 V
17
10
27
15
23
5.5 V
9
14
13
12
4.5 V
5.5 V
5
5
5
5
5
5
TEXAS . .
INSTRUMENTS
3·290
SN74HCTS63
MIN
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
MAX
UNIT
ns
ns
ns
384
TYPES SN54HCT563, SN74HCT563
OCTAL D·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
50 pF (see Note 1)
.
noted). CL
=
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
0
Q
tpd
C
Any
ten
Oc
Any
tdis
OC
Any
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
Any
tt
Vcc
V
V
V
V
V
V
V
V
V
V
TA = 25°C
MIN TYP MAX
28
35
24
32
30
35
28
32
29
35
25
32
25
35
24
32
10
12
9
11
SN54HCT563
MAX
MIN
53
48
53
48
53
48
53
48
18
16
SN74HCT563
MIN
MAX
44
40
44
40
44
40
44
40
15
14
UNIT
ns
ns
ns
ns
ns
50 pF typ
Power dissipation capacitance per latch
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted). CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
0
Q
tpd
ten
tt
C
OC
Any
Any
Any
Vcc
4.5 V
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
V
V
V
V
V
V
TA = 25°C
MIN TVP MAX
36
52
32
47
40
52
47
38
35
52
29
47
18
42
16
38
SN54HCT563
MAX
79
71
79
71
79
71
63
57
MIN
SN74HCT563
MIN
MAX
65
59
65
59
65
59
53
48
Ul
UNIT
ns
ns
:>w
c
Ul
o
ns
(J
~
:I:
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
w
(J
ns
NOTE 1: For load circuits and voltage waveforms. see page 1-14.
384
II
3-291
TYPES SN54HCT563, SN74HCT563
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
D latch signal conventions
It is TI practice to name the outputs and other inputs of a O-type latch and to draw its logic symbol based
on the assumption of true data (0) inputs. Then outputs that produce data in phase with the data inputs
and those producing complementary data are called Q. An input that causes a output to
are called
go high or a Q output to go low is called Preset; an input that causes a Q output to go high or a output
to go low is called Clear. Bars are used over these pin names (PRE and CLR) if they are active-low.
a
a
a
In some applications it may be advantageous to redesignate the data input 5. In that case all the other
inputs and outputs should be renamed as shown below. Also shown are corresponding changes in the
graphical symbol. Arbitrary pin numbers are shown in parentheses .
•
J:
n
3:
o
Notice that a and Q exchange names, which causes Preset and Clear to do likewise. Also notice that the
polarity indicators (t:::.. ) on PRE and CLR remain since these inputs are still active-low, but that the presence
or absence of the polarity indicator changes at 5, a, and Q. Of course pin 5 (Q) is still in phase with the
data input 5, but now both are considered active-low.
en
cm
$
n
m
en
TEXAS . .
INSTRUMENTS
3-292
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
384
TYPES SN54HC564, SN74HC564
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
•
High·Current 3·State Inverting Outputs Drive
Bus·Lines Directly or up to 15 LSTTL Loads
•
Bus·Structured Pinout
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC564 .•. J PACKAGE
SN74HC564 ... J OR N PACKAGE
(TOP VIEW)
oc
Vee
15
20
30
40
55
65
75
80
10
20
30
40
50
60
70
80
GNO
description
These 8-bit registers feature three-state outputs
designed specifically for bus driving. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
elK
SN54HC564 ... FH OR FK PACKAGE
SN74HC564 ... FH OR FN PACKAGE
(TOP VIEW)
II
u
~ ~Ig ~I~
The eight-bit edge-triggered D-type flip-flops
enter data on the low-to-high transition of the
clock.
3
2
30
40
50
60
70
An output control does not affect the internal
operation of the flip-flops. Old data can be
retained or new data can be entered while the
outputs are in the high-impedance state.
. The SN54HC564 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC564 is
characterized for operation from - 40°C to
85°C.
CJ)
25
35
40
50
60
W
(.)
:>w
c
9 1011 1213
o
co
0
CJ)
o
~Idld
co I '
t§d
2!
(.)
J:
logic symbol
FUNCTION TABLE
(EACH FLIP-FLOP)
OC
l
l
l
H
INPUTS
ClK
0
t
H
t
l
l
X
X
X
OUTPUT
Q
ClK
l
H
10
00
20
Z
30
40
50
60
70
80
-1!1
INSTRUMENTS
TEXAS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
Copyright © 1982. Texas Instruments Incorporated
3-293
TYPES SN54HC564, SN74HC564
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
, logic diagram (positive logic)
oc
(1)
ClK (11)
10 (2)
(19) 10
20 (3)
~~~-2Q
70 (8)
JO--+.;...(13.,;.) 70
(18)
(12)
80 (9)
_
80
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
31
3-294
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC564 SN74HC564
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
Clock frequency
fclock
Pulse duration. ClK high or low
tw
tsu
th
TA = 25°C
MAX
MIN
SN54HC564
MIN
MAX
4.2
0
SN74HC564
MIN
0
MAX
5
0
25
29
2V
0
6
4.5 V
0
31
0
6V
2V
0
80
36
0
120
100
4.5 V
16
24
20
6V
14
20
17
21
25
0
2V
100
150
125
Setup time. data before ClK t
4.5 V
20
17
25
21
Hold time. data after ClK t
6V
2V
4.5 V
30
26
5
5
5
5
6V
5
5
UNIT
MHz
ns
ns
I
5
ns
5
5
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
tpd
ten
ClK
OC
Any
Any
VCC
TA = 25°C
MIN TYP MAX
2V
4.5 V
6
31
6V
36
tt
OC
Any
Any
SN74HC564
MAX
MIN
5
11
36
40
21
25
25
29
MAX
54
18
180
36
270
54
225
45
6V
15
45
31
150
46
225
38
190
15
30
45
13
45
26
38
150
225
45
2V
4.5 V
2V
4.5 V
6V
30
26
2V
15
13
28
4.5 V
8
6V
6
Power dissipation capacitance per flip-flop
38
32
ns
ns
190
38
38
32
60
90
75
12
18
15
10
15
13
No load. TA = 25°C
UNIT
MHz
2V
4.5 V
6V
tdis
SN54HC564
MIN
4.2
ns
II
en
w
c.J
>
w
c
en
o
2
c.J
J:
ns
100 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-295
TYPES SN54HC564 SN74HC564
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
ClK
Any
ten
OC
Any
tt
Any
vce
TA = 25°C
MIN TYP MAX
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
75
24
21
57
19
17
60
17
14
230
46
34
200
40
34
210
42
36
SN54HC564
MIN
MAX
345
69
58
300
60
51
315
63
53
SN74HC564
MIN
MAX
290
58
49
250
50
43
265
53
45
UNIT
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14 .
0 flip-flop signal conventions
•
J:
(")
~
o
en
cm
S
(")
It is TI practice to name the outputs and other inputs of a Ootype flip-flop and to draw its logic symbol
based on the assumption of true data (0) inputs. Then outputs that produce data in phase with the data
inputs are called 0 and those producing complementary data are called Q. An input that causes a 0 output
to go high or a 5 output to go low is called Preset; an input that causes a 5 output to go high or a 0
output to go low is called Clear. Bars are used over these pin names (PRE and CLR) if they are active-low.
In some applications it may be advantageous to redesignate the data input D. In that case all the other
inputs and outputs should be renamed as shown below. Also shown are corresponding changes in the
graphical symbol. Arbitrary pin numbers are shown in parentheses.
m
en
Notice that 0 and 0 exchange names, which causes Preset and Clear to do likewise. Also notice that the
polarity indicators ( t::::... ) on PRE and CLR remain since these inputs are still active-low, but that the presence
or absence of the polarity indicator changes at 0, 0, and 5. Of course pin 5 (0) is still in phase with the
data input 0, but now both are considered active-low.
3-296
TEXAS
"'I
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HCT564, SN74HCT564
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02804, MARCH 1984
•
Inputs are TTL·Voltage Compatible
•
High·Current 3-State Inverting Outputs Drive
Bus-Lines Directly or up to 15 LSTTL Loads
•
Bus-Structured Pinout
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HCT564 ... J PACKAGE
SN74HCT564 ... J OR N PACKAGE
(TOP VIEW)
These 8-bit registers feature three-state outputs
designed specifically for bus driving. They are
particularly suitable for impl~menting buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
OUTPUT
II
U
~ ~Ig ~I~
en
w
(J
4D
5D
6D
7D
An output control does not affect the internal
operation of the flip-flops. Old data can be
retained or new data can be entered while the
outputs are in the high-impedance state.
INPUTS
elK
SN54HCT564 ... FH OR FK PACKAGE
SN74HCT564 ••. FH OR FN PACKAGE
(TOP VIEW)
The eight-bit edge-triggered D-type flip-flops
enter data on the low-to-high transition of the
clock.
FUNCTION TABLE
(EACH FLlp·FlOP)
10
20
30
40
55
60
70
80
1D
2D
3D
4D
5D
6D
7D
8D
GND
description
The SN54HCT564 is characterized for operation
over the full military temperature range of
- 55 °C to 125°C. The SN74HCT564 is
characterized for operation from - 40 °C to
85°C.
Vee
De
:>w
c
en
o
~
(J
J:
logic symbol
elK
OC
ClK
0
Q
l
l
t
t
H
l
H
20
L
L
00
30
H
X
X
X
L
10
Z
40
50
60
70
80
Copyright © 1984, Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-297
TYPES SN54HCT564, SN74HCT564
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
logic diagram (positive logic)
oc
(1)
ClK (11)
10..:;(2;;.;.)_'---..f-~
(19) 10
(18)
20 (3)
II
(17)
3D (4)
30
::r:
("")
(16)
40 (5)
s:
_
~-"~2Q
_
4Q
0
VJ
C
C1
m
50 (6)
(15)
10
<
0m
VJ
sCi
(14)
60 (7)
60
(13)
_
70 (8)
~---4-~7Q
80..;,(;.;.9)------1
~_~(12;.;..) 80
maximum ratings, recommended operating conditions, and electrical characteristics
See Table VII, page 2·14.
3-298
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3
TYPES SN54HCT564 SN74HCT564
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
vcc
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
Clock frequency
fclock
tw
Pulse duration. ClK high or low
tsu
Setup time. data before ClK t
th
Hold time. data after ClK t
5.5 V
TA = 25 D C
MIN
MAX
0
31
0
36
16
14
20
17
5
5
SN54HCT564
MIN
MAX
21
23
24
22
30
27
5
5
SN74HCT564
MIN
MAX
25
28
20
18
25
23
5
5
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
f max
tpd
ClK
Any
ten
OE
Any
tdis
OC
Any
Any
tt
VCC
V
V
V
V
V
V
V
V
V
V
TA = 25 D C
MIN TYP MAX
31
36
40
36
18
36
16
32
30
14
27
10
22
20
10
9
SN54HCT564
MIN
21
23
MAX
54
48
45
41
45
41
18
16
30
27
12
11
Power dissipation capacitance per flip-flop
SN74HCT564
MIN
MAX
25
28
UNIT
MHz
45
41
ns
38
34
ns
38
34
15
14
II
VJ
w
u
:>w
ns
c
VJ
o
ns
2
93 pF typ
u
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL
150 pF (see Note 1 )
J:
=
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
vCC
4.5 V
5.5 V
tpd
ClK
Any
ten
OE
Any
tt
Any
4.5
5.5
4.5
5.5
V
V
V
V
TA = 25 D C
MIN TYP MAX
38
38
47
36
47
30
27
39
42
18
16
SN54HCT564
MIN
MAX
80
71
71
59
SN74HCT564
MIN
MAX
63
57
53
48
38
66
60
59
49
UNIT
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS . .
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS, TeXAS 75265
3-299
TYPES SN54HCT564 SN74HCT564
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS WITH 3·STATE OUTPUTS
o flip-flop
signal conventions
It is TI practice to name the outputs and other inputs of a Ootype flip-flop and to draw its logic symbol
based on the assumption of true data (0) inputs. Then outputs that produce data in phase with the data
inputs are called 0 and those producing complementary data are called Q. An input that causes a 0 output
to go high or a' Q output to go low is called Preset; an input that causes a Q output to go high or a 0
output to go Irjw is called Clear. Bars are used over these pin names (PRE and CLR) if they are active-low.
In some applications it may be advantageous to redesignate the data input O. In that case all the other
inputs and outputs should be renamed as shown below. Also shown are corresponding changes in the
graphical symbol. Arbitrary pin numbers are shown in parentheses.
II
:z::
(")
S
Notice that 0 and Q exchange names, which causes Preset and Clear to do likewise. Also notice that the
polarity indicators ( ~ ) on PRE and CLR remain since these inputs are still active-low, but that the presence
or absence of the polarity indicator changes at 5, 0, and O. Of course pin 5 (0) is still in phase with the
data input 5, but now both are considered active-low.
o
en
cm
<
(")
m
en
3-300
TEXAS
-1!1
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC573, SN74HC573
OCTAL D·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
02684, DECEMBER 1982-REVISED MARCH 1984
•
High·Current 3·State Outputs Drive Bus·
Lines Directly or up to 15 LSTTL Loads
•
Bus-Structured Pinout
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC573 ... J PACKAGE
SN74HC573 ... J OR N PACKAGE
(TOP VIEW)
Vee
10
20
10
20
30
40
50
60
70
80
40
50
60
70
80
GNO
description
These 8-bit latches feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
e
SN54HC573 ... FH OR FK PACKAGE
SN74HC573 ... FH OR FN PACKAGE
(TOP VIEW)
~ ~ Ig
The eight latches are transparent D-type latches.
While the enable (C) is high the outputs (Q) will
respond to the data (D) inputs. When the enable
is taken low the outputs will be latched to retain
the data that was set up.
An output-control input can be used to place the
eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state.
In the high-impedance state the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pull-up components.
De
II
u
;;> ~
en
W
20
30
40
50
60
30
40
50
60
70
(.)
:>W
C
en
0
oouoo
ooz
(!)
oor--
:!
(.)
:r:
logic symbol
The output control (OC) does not affect the
internal operation of the latches, Old data can
be retained or new data can be entered while the
outputs are in the high impedance state.
The SN54HC573 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC573 is
characterized for operation from - 40°C to
85°C.
FUNCTION TABLE
(EACH LATCH I
INPUTS
OUTPUT
ENABLE
Dc
C
L
L
H
H
L
L
H
X
Q
0
H
H
L
L
X
X
00
Z
Copyright 101982 by Texas Instruments Incorporated
4
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-301
TYPES SN54HC573, SN74HC573
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
logic diagram (positive logic)
oc
(1 )
C
(19)
10
(2)
(1S)
20
II
3D
(3)
(17)
(4)
::I
(")
40
S
(16)
(5)
1Q
2Q
3Q
4Q
0
CJ)
(15)
C
m
50
(6)
5Q
:$
(")
m
CJ)
(14)
(7)
60
(13)
(S)
6Q
7Q
70
(12)
(9)
SQ
SO
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
3-302
TEXAS
'1.!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC573. SN74HC573
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
vcc
tw
tsu
Pulse duration, C high
2V
4.5 V
Setup time, data before enable C,j.
6V
2V
4.5 V
6V
2V
4.5 V
6V
Hold time, data after enable C.j.
th
TA = 25°C
MAX
MIN
80
16
14
50
10
9
5
5
5
SN54HC573
MIN
MAX
120
24
20
75
15
13
5
5
5
SN74HC573
MIN
MAX
100
20
17
UNIT
ns
63
13
11
ns
5
5
5
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL
50 pF (see Note 1)
=
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
0
Q
tpd
C
Any
ten
OC
Any
tdis
OC
Any
tt
Any
Vcc
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
77
175
26
35
23
30
87
175
27
35
23
30
68
150
24
30
21
26
47
150
23
30
21
26
28
60
8
12
6
10
Power dissipation capacitance per latch
SN54HC573
MIN
MAX
265
53
45
265
53
45
225
45
38
225
45
38
90
18
15
No load, TA = 25°C
SN74HC573
MIN
MAX
220
44
38
220
44
UNIT
ns
en
w
ns
(.)
>
W
38
190
38
32
190
38
32
75
15
13
II
ns
ns
c
en
o
~
(.)
ns
J:
50 pF typ
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-303
TYPES SN54HC573, SN74HC573
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
0
Q
tpd
C
Any
ten
Any
OC
Any
tt
lEI
Vee
TA = 25°C
MIN
TVP MAX
2V
4.5 V
6V
2V
4.5 V
6V
2V
95
33
21
103
4.5 V
6V
2V
4.5 V
6V
29
26
60
17
14
33
29
85
SN54HC573
MIN
MAX
SN74HC573
MIN
MAX
300
60
51
335
67
57
250
50
43
285
57
48
250
200
40
34
225
45
38
200
300
60
51
315
63
53
40
34
210
42
36
50
43
265
53
45
UNIT
ns
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
o latch signal conventions
::I
o
S
oCJ)
C
m
S
o
m
CJ)
It is TI practice to name the outputs and other inputs of a O-type latch and to draw its logic symbol based
on the assumption of true data (0) inputs. Then outputs that produce data in phase with the data inputs
are called Q and those producing complementary data are called Q. An input that causes a Q output to
go high or a Q output to go low is called Preset; an input that causes a Qoutput to go high or a Q output
to go low is called Clear. Bars are used ov~r these pin names (PRE and yLR) if they are active-low.
In some applications it may be advantageous to redesignate the data input D. In that case all the other
inputs and outputs should be renamed as shown below. Also shown are corresponding changes in the
graphical symbol. Arbitrary pin numbers are shown in parentheses.
S
R
C1
C1
10
10
R
S
(6) Q
Notice that Q and Q exchange names, which causes Preset and Clear to do likewise. Also notice that the
polarity indicators ( t:::... ) on PRE and CLR remain since these inputs are active-low, but that the presence
or absence of the polarity indicator changes at 0, Q and Q. Of course pin 5 (0) is still in phase with the
data input 0, but now both are considered active-low.
3-304
l!1
INSTRUMENTS
TEXAS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
31
TYPES SN54HCT573, SN74HCT573
OCTAL D·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02804. MARCH 1984
SN54HCT573 •.• J PACKAGE
SN74HCT573 ••. J OR N PACKAGE
•
Inputs are TTL-Voltage Compatible
•
High-Current 3-State Outputs Drive BusLines Directly or up to 1 5 LSTTL Loads
•
Bus-Structured Pinout
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
(TOP VIEW)
Vee
De
description
These 8-bit latches feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, 110 ports, bidirectional bus drivers, and
working registers.
e
SN54HCT573 .•• FH OR FK PACKAGE
SN74HCT573 .•• FH OR FN PACKAGE
(TOP VIEW)
II
u
~ ~Ig ~~
The eight latches are transparent O-type latches.
While the enable (C) is high the outputs (Q) will
respond to the data (0) inputs. When the enable
is taken low the outputs will be latched to retain
the data that was set up.
An output-control input can be used to place the
eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state.
In the high-impedance state the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pull-up components.
10
20
30
40
50
60
70
80
10
20
3D
40
50
60
70
80
GNO
en
w
20
30
40
50
60
40
50
60
70
(.)
:>w
c
en
o
eeuaa
002
COl'
~
(!)
(.)
J:
logic symbol
The output control (DC) does not affect the
internal operation of the latches. Old data can
be retained or new data can be entered while the
outputs are in the high impedance state.
oc
c
10
20
The SN54HCT573 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HCT573 is
characterized for operation from - 40°C to
85°C.
3D
40
50
60
70
FUNCTION TABLE
80
(EACH LATCH)
INPUTS
OUTPUT
ENABLE
oc
Q
0
L
C
H
L
H
l
l
l
l
X
00
H
X
X
Z
H
H
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
Copyright © 1984, Texas Instruments Incorporated
3-305
TYPES SN54HCT573, SN74HCT573
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
logic diagram (positive logic)
DC
(1)
C
10
(2)
20
(3)
30
:I:
o
s:o
40
50
10
(18)
20
(17)
(4)
(16)
(5)
en
cm
(19)
(15)
(6)
30
40
50
<
o
m
en
~--60
(7)
60---~1--I
~---~-
(8)
70
70 -------4~
(12)
80
-.;..(9~)- - - - t
80
maximum ratings, recommended operating conditions, and electrical characteristics
See Table VII, page 2-14.
3-306
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3f
TYPES SN54HCT573. SN74HCT573
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
TA = 25 DC
MIN
MAX
VCC
Pulse duration. C high
tw
tsu
Setup time. data before enable C ~
th
Hold time. data after enable C ~
SN54HCT573
MIN
MAX
SN74HCT573
MIN
4.5 V
20
30
25
5.5 V
17
27
23
4.5 V
10
15
13
5.5 V
9
14
12
4.5 V
5
5
5
5.5 V
5
5
5
MAX
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tpd
ten
tdis
FROM
(INPUT)
TO
(OUTPUT)
D
Q
C
OC
OC
Any
Any
Any
Any
tt
TA = 25°C
VCC
MIN
TYP
SN54HCT573
MAX
MIN
MAX
SN74HCT573
MIN
MAX
4.5 V
25
35
53
44
5.5 V
21
32
48
40
4.5 V
28
35
53
44
48
40
5.5 V
25
32
4.5 V
26
35
53
44
5.5 V
23
32
48
40
4.5 V
23
35
53
44
5.5 V
22
32
48
40
4.5 V
9
5.5 V
9
12
11
18
16
15
14
Power dissipation capacitance per latch
UNIT
•
ns
ns
ns
en
w
o
ns
5>
w
ns
c
en
50 pF typ
o
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
D
Q
tpd
C
Any
ten
OC
Any
tt
Any
vee
TA = 25 DC
MIN
TYP MAX
4.5 V
32
52
79
65
5.5 V
27
47
71
59
4.5 ~
38
52
79
65
5.5 V
36
47
71
59
4.5 V
5.5 V
33
52
47
79
65
28
71·
59
4.5 V
18
42
63
53
5.5 V
16
38
57
48
SN54HCT573
MIN
Power dissipation capacitance per latch
MAX
SN74HCT573
MAX
MIN
~
o
J:
UNIT
ns
ns
ns
ns
50 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-307
TYPES SN54HCT573. SN74HCT573
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
o
latch signal conventions
It is TI practice to name the outputs and other inputs of a O-type latch and to draw its logic symbol based
on the assumption of true data (0) inputs. Then outputs that produce data in phase with the data inputs
are called
and those producing complementary data are called Q. An input that causes a
output to
go high or a Q output to go low is called Preset; an input that causes a Q output to go high or a a output
to go low is called Clear. Bars are used over these pin names (PRE and CLR) if they are active-low.
a
a
In some applications it may be advantageous to redesignate the data input D. In that case all the other
inputs and outputs should be renamed as shown below. Also shown are corresponding changes in the
graphical symbol. Arbitrary pin numbers are shown in parentheses.
S
II
::I:
o
S
R
(51 Q
C1
C1
10
10
H
S
a
Notice that and Q exchange names, which causes Preset and Clear to do likewise. Also notice that the
polarity indicators ( c:::". ) on PRE and CLR remain since these inputs are still active-low, but that the presence
or absence of the polarity indicator changes at is, a, and Q. Of course pin 5 (0) is still in phase with the
data input is, but now both are considered active-low.
o
en
cm
S
o
en
m
3-308
(61 Q
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC574, SN74HC574
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
02684. DECEMBER 1982-REVISED MARCH 1984
•
High·Current 3·State Noninverting Outputs
Drive Bus-Lines Directly or up to 15 LSTTL
Loads
•
Bus·Structured Pinout
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC574 •.. J PACKAGE
SN74HC574 .•. J OR N PACKAGE
Vee
description
10
20
3D
40
10
20
30
40
so
SO
60
70
60
70
so
SO
elK
GNO
These 8-bit registers feature three-state outputs
designed specifically for bus driving. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
SNS4HC574 ... FH OR FK PACKAGE
SN74HCS74 ... FH OR FN PACKAGE
(TOP VIEW)
eo
The eight edge-triggered D-type flip-flops enter
data on the low-to-high transition of the clock.
a
alu
('1 .... 0> ....
en
321
The output-control does not affect the internal
operation of the flip-flops. Old data can be
retained or new data can be entered while the
outputs are in the high-impedance state.
w
20
30
(.)
:>w
so
C
60
The SN54HC574 is characterized for operation
over the full military temperature range of
- 55 °C to 125°C. The SN74HC574 is
characterized for operation from - 40°C 'to
85°C.
9 10111213
en
o
:!
(.)
:I:
logic symbol
FUNCTION TABLE
(EACH FLIP-FLOP)
OUTPUT
OC
l
l
l
INPUTS
ClK
I
I
l
0
H
l
X
00
H
X
X
Z
Q
H
l
20
3D
40
50
60
70
Copyright©1982 by Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-309
TYPES SN54HC574, SN74HC574
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS WITH 3·STATE OUTPUTS.
logic diagram (positive logic)
20 (3 )
30 (4 )
•
40
50
(5
(6
)
)
l:
(')
s:0
60 (7 )
en
c
m
70 (8 )
<
(')
80 (9 )
m
en
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time. data before ClK t
th
Hold time. data after ClK t
3-310
I
eLK high
0'
low
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25 D C
MIN
MAX
0
6
0
30
0
36
80
16
14
100
20
17
5
5
5
SN54HC574
MIN
MAX
0
4
0
20
0
24
120
24
20
150
30
26
5
5
5
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 15265
SN74HC574
MIN
MAX
0
5
0
24
. 28
0
100
20
17
125
25
21
5
5
5
UNIT.
MHz
ns
ns
ns
TYPES SN54HC574, SN74HC574
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
vCC
2V
f max
tpd
ten
tdis
4.5 V
6V
2V
Any
ClK
4.5 V
6V
2V
Any
OC
4.5 V
6V
2V
4.5 V
6V
2V
Any
OC
Any
tt
4.5 V
6V
TA .,. 25°C
MIN TYP MAX
6
11
30
36
36
40
90
180
28
36
24
31
77
150
26
30
23
26
52
150
24
30
22
26
28
60
8
12
6
10
Power dissipation capacitance
SN54HC574
MAX
MIN
4
20
24
SN74HC574
MIN
MAX
5
24
UNIT
MHz
28
270
225
45
54
46
225
45
ns
38
190
38
225
45
38
90
18
15
38
32
190
ns
38
32
75
15
13
ns
II
ns
en
w
o
100 pF typ
No load. TA .,. 25°C
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
2V
4.5 V
f max
tpd
ClK
Any
ten
OC
Any
tt
VCC
Any
6V
2V
4.5 V
6V
2V
TA .,. 25°C
MIN TYP MAX
6
30
36
105
265
36
53
31
46
95
32
28
60
17
14
4.5 V
6V
2V
4.5 V
6V
SN54HC574
MAX
MIN
4
20
24
235
47
41
210
42
36
SN74HC574
MIN
MAX
5
24
28
400
80
68
355
71
60
315
63
53
UNIT
MHz
>
w
c
en
o
:E
o
:I:
330
66
57
295
59
51
265
53
45
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-311
TYPES SN54HC574, SN74HC574
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
o flip-flop signal conventions
It is TI practice to name the outputs and other inputs of a D-type flip-flop and to draw its logic symbol
based on the assumption of true data (D) inputs. Then outputs that produce data in phase with the data
inputs are called 0 and those producing complementary data are called O. An input that causes a 0 output
to go high or a 0 output to go low is called Preset; an input that causes a Q output to go high or a 0
output to go low is called Clear. Bars are used over these pin names (PRE and Ci:R) if they are active-low.
In some applications it may be advantageous to redesignate the data input D. In that case all the other
inputs and outputs should be renamed as shown below. Also shown are corresponding changes in the
waphical symbol. Arbitrary pin numbers are shown in parentheses.
PRE
ClK
0
•
(5) Q
ClK
C1
(6)
a
CLR
::I:
(")
~
C1
0
PiiE
Notice that 0 and Q exchange names, which causes Preset and Clear to do likewise. Also notice that the
polarity indicators ( b.. ) on PRE and CLR remain since these inputs are still active-low, but that the
presence or absence of the polarity indicator changes at 0, 0, and Q. Of course pin 5 (0) is still in phase
with the data input 5, but now both are considered active-low.
oen
c
m
<
(")
m
en
3-312
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
HIGH·SPEED
CMOS LOGIC
TYPES SN54HCT574, SN74HCT574
OCTAL D·TYPE EDGE·TRIGGERED FLlP·FLOPS WITH 3·STATE OUTPUTS
02804, MARCH 19134
SN54HCT574 •.. J PACKAGE
SN74HCT574 ... J OR N PACKAGE
•
Inputs Are TTL-Voltage Compatible
•
High-Current 3-State Noninverting Outputs
Drive Bus-lines Directly or up to 1 5 lSTTl
loads
•
Bus·Structured Pinout
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
Dc
10
20
3D
30
40
50
60
70
80
40
50
60
70
80
GNO
elK
description
These 8-bit registers feature three-state outputs
designed specifically for bus driving. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
.
SN54HCT574 ..• FH OR FK PACKAGE
SN74HCT574 ... FH OR FN PACKAGE
(TOP VIEWI
~
The eight edge-triggered D-type flip-flops enter
data on the low-to-high transition of the clock.
The output-control does not affect the internal
operation of the flip-flops. Old data can be
retained or new data can be entered while the
outputs are in the high-impedance. state.
The SN54HCT574 is characterized for operatio..n
over the full military temperature range of
- 55°C to 125°C. The SN74HCT574 is
characterized for operation from - 40°C to
85°C.
e Ig ~2
3D
20
. 40
50
60
70
30
en
w
(.)
:>w
4Q
50
60
C
en
o
:!
(.)
:I:
logic symbol
FUNCTION TABLE
(EACH FLIP-FLOP)
OC
l
L
l
H
INPUTS
ClK
0
t
H
t
L
X
L
X
X
OUTPUT
0
H
L
20
00
3D
Z
40
50
60
70
10
80
Copyright © 1984, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-313
TYPES SN54HCT514, SN14HCT514
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
logic diagram (positive logic)
20 (3 )
30
•
40
141
(5
)
50 (6)
J:
0
3:
0
en
cm
60
171
70 (8 )'
<
0m
80
en
(9
)
maximum ratings, recommended operating conditions, and electrical characteristics
See Table VII, page 2-14.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
vcc
fclock Clock frequency
I
tw
Pulse duration
tsu
Setup time, data before elK t
th
Hold time, data after ClK t
3-314
ClK high or low
4.5
5.5
4.5
5.5
4.5
V
V
V
V
V
5.5 V
4.5 V
5.5 V
TA = 25°C
MAX
MIN
0
30
33
0
16
14
20
17
5
5
SN54HCT674
MIN
MAX
0
20
0
22
24
22
30
27
5
5
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SN74HCT574
MIN
MAX
24
0
27
0
20
18
25
23
5
5
UNIT
MHz
ns
ns
ns
TYPES SN54HCT574, SN74HCT574
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
tpd
ClK
Any
ten
OC
Any
tdis
OC
Any
Any
tt
Cpd
vcc
4.5
5.5
4.5
5.5
4.5
5.5
V
V
V
V
V
V
4.5
5.5
4.5
5.5
V
V
V
V
TA = 25°C
MIN TYP MAX
30
36
40
33
30
36
25
32
26
30
23
27
23
30
22
27
12
10
9
11
Power ,dissipation capacitance per flip-flop
SN54HCT574
MIN
MAX
20
22
54
48
45
41
45
41
18
16
No load. TA = 25°C
SN74HCT574
MIN
MAX
24
27
45
41
38
34
38
34
15
14
UNIT
MHz
ns
ns
ns
ns
93 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted) CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
4.5 V
f max
tpd
ten
tt
VCC
ClK
Any
OC
Any
Any
5.5 V
4.5 V
5.5
4.5
5.5
4.5
5.5
TA = 25°C
MIN TYP MAX
30
33
V
V
V
V
V
36
40
40
35
34
29
18
16
53
47
47
39
42
SN54HCT574
MAX
MIN
20
22
80
71
71
94
38
NOTE 1.: For load circuit and voltage waveforms. see page 1-14.
63
57
SN74HCT574
MIN
MAX
24
27
66
60
59
78
53
48
UNIT
II
en
W
(J
MHz
ns
ns
ns
:>w
c
en
o
~
(J
J:
384
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-315
TYPES SN54HCT574. SN74HCT574
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS WITH 3·STATE OUTPUTS
o flip·flop
signal conventions
It is TI practice to name the outputs and other inputs of a Ootype flip-flop and to draw its logic symbol
based on the assumption of true data (0) inputs. Then outputs that produce data in phase with the data
inputs are called a and those producing complementary data are called Q. An input that causes a a output
to go high or a Q output to go low is called Preset; an input that causes a Q output to go high or a a
output to go low is called Clear. Bars are used over these pin names (PRE and CLR) if they are active-low.
In some applications it may be advantageous to redesignate the data input O. In that case all the other
inputs and outputs should be renamed as shown below. Also shown are corresponding changes in the
graphical symbol. Arbitrary pin numbers are shown in parentheses.
PRE
CLK
D
II
::r:
(')
s:
(51
a
(5) -
C1
a
C1
(6)
a
(6)
a
CLR
a
Notice that and Q exchange names, which causes Preset and Clear to do likewise. Also notice that the
polarity indicators ( ~ ) on PRE and CLR remain since these inputs are still active-low, but that the
presence or absence of the polarity indicator changes at 5, a, and O. Of course pin 5 (a) is still in phase
with the data input 5, but now both are considered active-low.
o
en
om
<
o
rn
en
3·316
~
TEXAS
INSTRUMENTS
POST oFFice BOX 225012 • DALLAS. TeXAS 75265
384
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC604, SN74HC604
OCTAL 2·INPUT MULTIPLEXED LATCHES WITH 3·STATE OUTPUTS
02804. MARCH 1984
•
•
High·Current 3-State Outputs Can Drive up
to 15 LSTTL Loads
SN54HC604 ... J PACKAGE
SN74HC604 ... J OR N PACKAGE
(TOP VIEW)
16 0-Type Registers, One for Each Data
Input
•
Multiplexer Selects Stored Data from Either
A Bus or B Bus
•
Application-Oriented for Maximum Speed
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and .Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
.
SEl
elK
Vee
AlB
A1
81
A2
A5
85
A6
86
A7
87
A8
88
Y8
Y7
Y6
82
A3
83
A4
84
Y4
Y3
Y2
description
Y5
Y1
GND
The 'HC604 multiplexed latch is ideal for storing
data from two input buses. A and 8. and for
providing the output bus with stored data from
either the A or 8 register.
II
SN54HC604 ... FH OR FK PACKAGE
SN74HC604 ... FH OR FN PACKAGE
(TOP VIEW)
The clock loads data on the positive-going (lowlevel to high-level) transition. The clock pin also
controls the active and high-impedance states
of the outputs. When the clock pin is low, the
outputs are in the high-impedance or off state.
When the clock pin is high. the outputs are
enabled.
A2
A6
The device is optimized for high-speed operation.
82
A3
86
A7
87
A8
88
en
w
U
1m
~
..J ~ U
.-'-w..JUl!)l!)
m->-z>->->->-
The SN54HC604 is characterized for operation
over the full military range of - 55°C to 125°C.
The SN74HC604 is characterized for operation
from -40°C to 85°C.
19
FUNCTION TABLE
A1-A8
A data
A data
X
X
X
INPUTS
B1-B8
AlB
B data
B data
X
X
X
L
H
X
L
H
CLOCK
OUTPUTS
V1-V8
t
t
B data
A data
L
H
H
B register stored data
Z
A register stored data
Copyright © 1984. Texas Instruments Incorporated
:4
TEXAS
"'.!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-317
TYPES SN54HC604, SN74HC604
OCTAL 2·INPUT MULTIPLEXED LATCHES WITH 3·STATE OUTPUTS
logic symbol
logic diagram (positive logic)
A1 131
Y1
Y2
1151 Y1
B1 141
Y3
Y4
A2 151
Y5
Y6
II
(13) Y2
B2 161
Y7
Y8
A3 171
1121 Y3
:::I
B3 181
S
oen
A4 191
(")
C
m
<
n
m
en
~-I-.:..:11..:!11 Y4
B4 1101
AS
1271
~-I-.:...:11.::.!61 Y5
B5 1261
A6
1251
1171 Y6
B6 1241
A7 (23)
(18) Y7
B71221
A8 1211
>-_.:..;;11=9) Y8
B8
1201
38'
3-318
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC604, SN74HC604
OCTAL 2-INPUT MULTIPLEXED LATCHES WITH 3-STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
Clock frequency
fclock
Pulse duration. ClK high or low
tw
Setup time. data before ClK t
tsu
Hold time. data after ClK t
th
TA = 25°C
MAX
MIN
SN54HC604
MIN
MAX
SN74HC604
MIN
MAX
4
0
2V
0
5
0
4.5 V
0
25
0
'6 V
2V
0
100
29
0
150
4.5 V
20
30
25
6V
2V
17
75
25
21
4.5 V
15
115
23
95
19
6V
13
20
16
2V
5
5
5
4.5 V
5
5
5
5
5
5
6V
3.3
17
20
0
20
0
125
24
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
.
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
tpd
AlB
Y
VCC
TA;" 25°C
MIN
TYP MAX
2V
4.5 V
5
25
6V
29
ten
tdis
tt
ClK
ClK
Y
y
Any
3.3
17
92
4.5 V
23
17
2V
4.5 V
6V
96
25
19
2V
84
4.5 V
6V
2V
4.5 V
6V
SN74HC604
MIN
MAX
4
20
24
20
2V
6V
SN54HC604
MIN
MAX
MHz
170
34
255
215
51
43
29
195
43
37
295
59
245
49
39
UNIT
33
50
42
300
250
30
200
40
60
26
34
51
50
43
20
60
8
6
12
10
90
18
75
15
15
13
II
en
w
CJ
>
w
c
en
o
ns
:!
CJ
::t:
ns
ns
ns
100 pF typ
Power dissipation capacitance per latch
NOTE 1: For load circuits and voltage waveforms. see page 1-14.
384
TEXAS
"'J}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-319
TYPES SN54HC604, SN74HC604
OCTAL 2·INPUT MULTIPLEXED LATCHES WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
tpd
ten
tt
FROM
(INPUT)
AlB
elK
TO
(OUTPUT)
V
v
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
110 255
28
51
44
21
120
280
30
56
23
48
45
210
42
17
13
36
SN54HC604
MIN
MAX
385
77
65
425
85
72
315
63
53
SN74HC604
MIN
MAX
320
64
56
350
70
61
265
53
45
UNIT
ns
ns
ns
NOTE 1: For load circuits and voltage waveforms, see page 1-14.
II
:::I:
o
S
oCJ)
C
m
<
o
m
CJ)
384
3-320
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC620, SN54HC623, SN74HC620, SN74HC623
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
SN54HC· .•. JPACKAGE
SN74HC' .•• J OR N PACKAGE
•
Lock Bus-Latch Capability
•
Choice of True or Inverting Logic
•
High-Current 3-State Outputs Can Drive up
to 1 5 LSTTL Loads
(TOP VIEW)
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
Vee
GAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
LOGIC
GBA
B1
B2
B3
B4
B5
B6
B7
B8
Inverting
True
SN54HC' .•. FH OR FK PACKAGE
SN74HC' •.. FH OR FN PACKAGE
description
These octal bus transceivers are designed for
asynchronous two-way communication
between data buses. The control function
implementation allows for maximum flexibility in
timing.
II
(TOP VIEW)
«
al U
N'--«Ual
« «
e)
> Ie)
til
W
(.)
B1
B2
B3
B4
B5
These devices allow data transmission from the
A bus to the B bus or from the B bus to the A
bus depending upon the logic levels at the enable
inputs (GBA and GAB).
>
W
C
en
o
:E
(.)
The enable inputs can be used to disable the
device so that the buses are effectively isolated.
The dual-enable configuration gives these
devices the capability to store data by
simultaneous enabling of GBA and GAB. Each
output reinforces its input in this transceiver
configuration. Thus when both control inputs are
enabled and all other data sources to the two
sets of bus lines are at high impedance, both sets
of bus lines (16 in all) will remain at their last
states. The 8-bit codes appearing on the two
sets of buses will be identical for the 'HC623 or
complementary for the 'HC620.
::J:
The SN54HC620 and SN54HC623 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74HC620 and SN74HC623 are characterized
for operation from -40°C to 85°C.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS
-1.!1
INSTRUMENTS
POST OFFiCe BOX 225012 • DALLAS, TexAS 75265
3-321
TYPES SN54HC620, SN54HC623, SN74HC620, SN74HC623
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
FUNCTION TABLE
ENABLE INPUTS
OPERATION
GBA
GAB
'HC620
'HC623
L
L
B data to A bus
B data to A bus
H
H
H
L
A data to B bus
Isolation
A data to B bus
Isolation
L
H
B data to A bus,
B data to A bus,
A data
A data to B bus
to B bus
B2
A2
TO OTHER SIX TRANSCEIVERS
3-322
82
A2
TO OTHER SIX TRANSCEIVERS
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC620. SN54HC623. SN74HC620. SN74HC623
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
B or A
ten
GBA
A
tdis
GBA
A
ten
GA8
B
tdis
GAB
B
PARAMETER
A or B
tt
TA = 25°C
vCC
MIN
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TVP MAX
29 105
21
10
18
8
112 210
42
27
20
36
40 150
18
30
16
26
112 210
42
27
36
20
40 150
18
30
16
26
20
60
12
8
10
6
Power dissipation capacitance per transceiver
SN54HC620
SN54HC623
MIN
MAX
160
32
27
315
63
54
225
45
38
315
63
54
225
45
38
90
18
15
No load. TA
=
25°C
SN74HC620
SN74HC623
MIN
MAX
130
26
22
265
53
45
190
38
32
265
53
45
190
38
32
75
15
13
UNIT
ns
ns
II
ns
ns
en
w
U
ns
>
w
c
ns
en
o
~
U
40 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
B or A
ten
GBA
A
ten
GAB
B
PARAMETER
tt
A or B
TA = 25°C
VCC
MIN
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TVP MAX
44 135
27
14
23
11
130 270
54
31
46
23
130 270
54
31
46
23
45 210
42
17
36
13
SN54HC620
SN54HC623
MIN
MAX
200
40
34
405
81
69
405
81
69
315
63
53
SN74HC620
SN74HC623
MIN
MAX
170
34
29
335
67
56
335
67
56
265
53
45
J:
UNIT
ns
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-323
II
::z::
o
s:
o
en
cm
<
o
m
en
3-324
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC646, SN54HC648, SN74HC646, SN74HC648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
02684. DECEM8ER 1982-REVISED MARCH 1984
•
Independent Registers for A and B Buses
•
Multiplexed Real-Time and Stored Data
•
Choice of True or Inverting Data Paths
•
High-Current 3-State Outputs Can Drive up
to 15 LSTTL Loads
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC' ... JT PACKAGE
SN74HC' ... JT OR NT PACKAGE
(TOP VIEW)
CA8
SA8
VCC
C8A
S8A
DIR
G
A1
A2
A3
A4
A5
A6
A7
A8
description
81
82
83
84
85
86
87
88
GND
These devices consist of bus transceiver circuits
with 3-state outputs, D-type flip-flops, and
control circuitry arranged for multiplexed
transmission of data directly from the input bus
or from the internal registers. Data on the A or
B bus will be clocked into the registers on the
low-to-high transition of the appropriate clock
pin (CAB or CBA). The examples on the following
page demonstrate the four fundamental busmanagement functions that can be performed
with the 'HC646 or 'HC648.
II
SN54HC' ••. FH OR FK PACKAGE
SN74HC' •.. FH OR FN PACKAGE
(TOP VIEW)
!!: ~ ~ u ~ri3
ri3
Ocnuz>ucn
4
3 2
en
w
(.)
1 282726
>
W
G
81
82
C
en
NC
Enable (<3) and direction (DIR) pins are provided
to control the transceiver functions. In the
transceiver mode, data present at the highimpedance port may be stored in either register
or in both. The select controls (SAB and SBA)
can multiplex stored and real-time (transparent
mode) data. The direction control determines
which bus will receive data when enable G is
active (low). In the isolation mode (enable G
high), A data may be stored in one register and/or
B data may be stored in the other register.
o
83
84
85
2
(.)
12 131415161718
::I:
NC-No internal connection
When an output function is disabled, the input
function is still enabled and may be used to store
and transmit data. Only one of the two buses,
A or B, may be driven at a time.
The SN54HC' family is characterized for
operation over the full military temperature range
of - 55°C to 125°C. The SN74HC' family is
characterized for operation from - 40°C to
85°C.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright ©1982 by Texas Instruments Incorporated
3-325
TYPES SN54HC646, SN54HC648, SN74HC646, SN74HC648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
(21)
(3)
G
OIR
L
•
L
(1)
(23)
CAB CBA
X
X
(2)
(22)
(21)
(3)
SAB
X
SBA
G
OIR
H
L
(1)
(23)
CAB CBA
X
(2)
(22)
SAB
SBA
X
L
X
REAL-TIME TRANSFER
REAL-TIME TRANSFER
BUS B TO BUS A
BUS A TO BUS B
J:
0
s:0
en
cm
S
0
m
en
(21)
(3)
G
OIR
(1)
(23)
CAB CBA
X
X
t
X
X
X
H
X
t
X
(2)
(22)
(21)
(3)
SAB
SBA
G
OIR
X
X
L
X
X
X
X
(23)
(2)
L
X
H
H or L
H or L X
H
X
TRANSFER STORED DATA
TO A OR B
STORAGE FROM
A. B. OR A AND B
Pin numbers shown are for JT and NT packages.
3-326
(1)
CAB CBA SAB
-1.!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
(22)
SBA
H
X
TYPES SN54HC646, SN54HC648, SN74HC646, SN74HC648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
FUNCTION TABLE
DATA IIOt
INPUTS
G
X
Not specified
'HC646
Store A, B unspecified
X
Not specified
Input
Store B, A unspecified
Store B, A unspecified
Input
Input
Store A and B Data
Isolation, hold storage
Store A and B Data
Isolation, hold storage
L
H
Output
Input
X
X
Input
Output
CAB
CBA
SAB
SBA
X
f
X
X
X
X
X
X
H
H
X
X
X
L
f
H or
L
L
H
X
X
X
L
H
H or
L
L
f
f
L H or L
X
H or L
X
L
X
X
X
X
X
L
H
OPERATION OR FUNCTION
'HC648
A1 THRU A8
Input
DIR
X
X
B1 THRU B8
Store A, B unspecified
Real-Time B Data to A Bus Real-Time
Stored B Data to A Bus
Stored
B Data to
B Data to
A Bus
A Bus
Real-Time A Data to B Bus Real-Time A Data to B Bus
Stored A Data to B Bus
Stored
A Data to
B Bus
t The data output functions may be enabled or disabled by various signals at the Gand DIR inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.
logic symbols
II
'HC648
'HC646
G
(21)
DIR (3)
[BA)
CBA (23)
[BA)
en
W
C4
0
SBA (22)
CAB (1)
>
C6
W
SAB (2)
(20)
Bl
Al
(20)
(4)
Bl
Al
S
7
'1
(19)
A2
(S)
B2
A4
B4
(S)
BS
B6
B7
(11)
B8
(17)
(S)
(16)
(9)
(15)
(10)
(14)
(11)
(13)
B3
~
0
::I:
B4
BS
B6
B7
A7
(13)
A8
(7)
A6
(14)
A7
(1S)
AS
(15)
A6
B2
(6)
A4
(16)
AS
(19)
A3
(17)
en
0
;;'1
A2
(1S)
B3
'1
C
AS
BS
Pin numbers shown are for JT and NT packages.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-327
TYPES SN54HC646, SN54HC648, SN74HC646, SN74HC648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
logic diagram (positive logic)
'HC646
'HC648
G 1211
G
,.----D.,....l:-L.ri--------i
DIR ~I3~I
CBA~I2=31-~---~r_---~--~~-~
SBA ~I27'21-----~r__I ::>O-..-:C".....,
CAB ..:.":..:..1_~::~
DIR
1211
~I3~I,.----D.".j~L.rI------_:_-__,
CBA7.12~31-~---~r__"7--7_"--,)~"
SBA ~I2'?f21--:----~r_-i::>O-~~>,..,
CAB -;.":.;-1- - I >-,
SAB ..!I2~I-....:::.....-+-+-C><>_1rll»__,
SAD -,,12,,-1---"-----\---\-C:>O-t-<'I;'O,
AI 141
AI
1
41
1201 81
1201 81
II
::I:
(")
S
o(J)
C
m
<
(")
A2~
---
-----
A3~
A4
AS
~
~
A6~
~B2
A2~
~B3
A3~
A4 ~
AS ~
~ 04
7 CHANNELS IDENTICAL
TO CHANNEL 1 AOOVE
~ OS
~07
A7~
AB~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~B8
A8~
-----
TO CHANNEL 1 ABOVE
A6~
~06
A7~
--7 CHANNELS IDENTICAL
~B2
~03
~ B4
~ 85
i" ::::
_____________________
06
~B7
~B8
Pin numbers shown are for JT and NT packages.
absolute maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
m
(J)
VCC
fclock
Clock frequency
tw
Pulse duration, CBA or
CAB high or low
tsu
Setup time, A before CABi
or B before CBA i
th
Hold time, A after CABi
or B after CBA i
3-328
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN
0
0
0
80
16
14
100
20
17
5
5
5
MAX
6
31
36
SN54HC646
SN54HC648
MIN
MAX
4.3
0
22
0
25
0
SN74HC646
SN74HC648
MAX
MIN
0
5.5
0
27
0
31
115
23
20
95
19
16
125
25
21
5
5
5
150
30
26
5
5
5
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
UNIT
MHz
ns
ns
ns
TYPES SN54HC646, SN54HC648, SN74HC646, SN74HC648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA - 25°C
VCC
tpd
CBA or CAB
A or B
tpd
A or B
B or A
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
A or B
6V
2V
4.5 V
f max
tpd
SBA or SABt
ten
G
A or B
tdis
G
A or B
ten
tdis
tt
DIR
DIR
A or B
Aor B
Any
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
MIN
6
31
36
TYP MAX
11
54
64
65
180
36
18
14
31
50
135
14
27
11
23
70
190
20
16
85
25
20
85
25
20
80
25
20
80
25
20
38
32
245
49
42
245
49
42
245
49
42
245
49
42
28
8
6
60
12
10
SN54HC646
SN54HC648
MIN
MAX
4.4
22
25
270
54
46
205
41
35
285
57
48
Power dissipation capacitance
SN74HC646
SN74HC648
MIN
MAX
5.5
27
31
225
45
38
170
34
29
240
48
41
305
61
52
305
61
52
305
61
52
305
61
52
75
15
13
370
74
63
370
74
63
370
74
63
370
74
63
90
18
15
UNIT
MHz
ns
ns
ns
ns
II
til
ns
ns
w
o
:>w
C
til
ns
ns
o
:E
o
:::I:
50 pF typ
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
tThese parameters are measured with the internal output state of the storage register opposite to that of the bus input.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-329
TYPES SN54HC646, SN54HC648, SN74HC646, SN74HC648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 150 pF (see Note 1)
PARAMETER
tpd
tpd
tpd
ten
II
ten
FROM
(INPUT)
TO
(OUTPUT)
CBA or CAB
A or B
A or B
SBA or SABt
G
DIR
tt
S
o
en
cm
<
Ci
m
en
SN54HC646
TA - 25°C
MAX
2V
4.5 V
90
24
265
6V
B or A
A or B
A or B
MIN
SN74HC648
SN54HC648
TYP
MIN
SN74HC648
MAX
400
MIN
330
80
20
53
46
68
66
57
2V
4.5 V
70
220
335
280
20
44
67
15
80
24
38
275
55
57
415
56
49
345
ns
6V
2V
4.5 V
ns
20
47
83
70
69
6V
60
2V
113
330
33
66
500
100
410
4.5 V
6V
27
57
85
71
82
2V
113
330
500
410
4.5 V
6V
33
27
66
57
100
85
82
71
2V
45
210
315
265
Any
4.5 V
17
42
63
53
6V
13
36
53
43
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
t These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
3-330
UNIT
MAX
A or B
::J:
("')
VCC
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
ns
·ns
ns
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HCT646, SN54HCT648, SN74HCT646, SN74HCT648
OCTAL BUS TRANSCEIVERS AND REGISTERS
, WITH 3·STATE OUTPUTS
02804, MARCH 1984
SN54HCT' ... JT PACKAGE
SN74HCT' .•. JT OR NT PACKAGE
(TOP VIEW)
•
Inputs are TTL-Voltage Compatible
•
Independent Registers for A and B Buses
•
Multiplexed Real-Time and Stored Data
•
Choice of True or Inverting Data Paths
•
High-Current 3-State Outputs Can Drive up
to 15 LSTTL Loads
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
CAB [ 1 U24
23
SAB 2
DIR 3
22
Al 4
21
A2 5
20
A3 6
19
A4 7
18
A5 8
17
A6 =9
16
A7 10 15
A8 11
14
GND 12 13 ]
VCC
CBA
SBA
G
B1
B2
B3
B4
B5
B6
87
B8
description
These devices consist of bus transceiver circuits
with 3-state outputs, D-type flip-flops, and
control circuitry arranged for multiplexed
transmission of data directly from the input bus
or from the internal registers. Data on the A or
B bus will be clocked into the registers on the
low-to-high transition of the appropriate clock
pin (CAB or CBA). The examples on the following
page demonstrate the four fundamental busmanagement functions that can be performed
with the 'HCT646 or 'HCT648.
Enable (G) and direction (DIR) pins are provided
to control the transceiver functions. In the
transceiver mode, data present at the highimpedance port may be stored in either register
or in both. The select controls (SAB and SBA)
can multiplex stored and real-time (transparent
mode) data. The direction control determines
which bus will receive data when enable G is
active (low). In the isolation mode (enable G
high), A data may be stored in one register and/or
B data may be stored in the other register.
II
SN54HCT' •.. FH OR FK PACKAGE
SN74HCT' •.• FH OR FN PACKAGE
(TOP VIEW)
en
W
£f~~u~~~
C (f)AJ 2 > U (f)
432
(.)
1
5>
W
G
A1
A2
A3
NC
A4
A5
A6
B1
B2
NC
B3
B4
B5
C
en
0
:E
(.)
::J:
12 13 14 1516 17 18
,....CllCUCll,....CO
« « 2 2 0l0l0l
t!)
NC-No internal connection
When an output function is disabled, the input
function is still enabled and may be used to store
and transmit data. Only one of the two buses,
A or B, may be driven at a time.
The SN54HCT' family is characterized for
operation over the full military temperature range
of - 55°C to 125°C. The SN74HCT' family is
characterized for operation from - 40°C to
85°C.
Copyright © 1984, Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TeXAS 75265
3-331
TYPES SN54HCT646, SN54HCT648, SN74HCT646, SN74HCT648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
~
(21)
(3)
(1)
(23)
(2)
(22)
(21)
(3)
(1)
(23)
(2)
(22)
G
DIR
CAB
CBA
SAB
SBA
IT
DIR
CAB
CBA
SAB
SBA
L
X
X
X
H
X
X
L
X
III
REAL-TIME TRANSFER
REAL-TIME TRANSFER
BUS B TO BUS A
BUS A TO BUS B
::I
("')
S
0
CJ)
C
m
<
0m
CJ)
~
(21)
(3)
(1)
(23)
(2)
(22)
(21)
(3)
(1)
G
DIR
CAB
CBA
SAB
SBA
IT
DIR
CAB
X
X
t
X
X
X
L
L
X
X
X
X
X
X
L
H
H or L
H
X
X
X
(2)
H or L X
X
H
TRANSFER STORED DATA
STORAGE FROM
TO A OR B
A. B. OR A AND B
Pin numbers shown are for JT and NT packages.
3-332
(23)
CBA SAB
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
(22)
SBA
H
X
:
TYPES SN54HCT646, SN54HCT648, SN74HCT646, SN74HCT648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
FUNCTION TABLE
DATA I/Ot
INPUTS
G
X
DIR
CAB
CBA
SAB
X
X
t
X
X
t
t
X
X
X
H
H
L
L
L
L
X
X
L
L
H
H
t
X
X
X
X
L
H
H or L H or L
X
X
H or L
X
X
X
X
H or L
OPERATION OR FUNCTION
SBA
X
A1 THRU AS
B1 THRU 8S
Input
Not specified
X
X
X
L
H
X
X.
Not specified
Input
Output
Input
Input
Output
'HCT646
Store A, B unspecified
'HCT648
Store A, B unspecified
Input
Store B, A unspecified
Store B, A unspecified
Input
Store A and B Data
Isolation, hold storage
Store A and B Data
Isolation, hold storage
i.i Data to A Bus
B Data to A Bus
Real-Time B Data to A Bus Real-Tillie
Stored B Data to A Bus
Stored
Real-Time A Data to B Bus Real-Time A Data to B Bus
Stored A Data to B Bus
Stored
A Data to
B Bus
t The data output functions may be enabled or disabled by various signals at the Gand DlR inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.
logic symbols
G
(21)
G'·(211
DIR (3)
DIR (3)
[BA)
CBA (23)
0
:>W
C6
SAB (2)
(20)
;;'1
(4)
Bl
Al
;;'1
Bl
Al
5
;;'1
7
(5)
en
W
SBA (22)
CAB (1)
C6
SAB (2)
(4)
[BA)
CBA (23)
SBA (22)
CAB (1)
II
'HCT648
'HCT646
7
(19)
A2
(5)
B2
(6)
(lS)
(7)
(17)
(S)
(16)
A3
A2
A4
AS
(9)
A3
(10)
B4
A4
S5
AS
(11)
B6
A6
B7
A7
BS
AS
(9)
(10)
(13)
AS
J:
(S)
(14)
A7
~
(7)
(15)
A6
en
0
(J
(6)
B3
7
C
(111
Pin numbers shown are for JT and NT packages.
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-333
:
TYPES SN54HCT646, SN54HCT648, SN74HCT646, SN74HCT648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
logic diagram (positive logic) .
'HCT648
'HCT646
G 1211
,..---t;:oo.:..l(..-LJ-t---------=--i
CIR .!:13~)
CBA 1231
SBA 122)
CAB -,-11.:.:..)--C)--'
SAB -,-12~1--"-_1H-C~t__:....,
A1 141
1201 B1
1201 B1
--- ----- ]..J!!L~
II~-...
A3~
::I:
(')
s:o
A4
AS
~
~
TO CHANNEL 1 ABOVE
~
A4
___ J
i:: ::~::~
A7~
AB~_...;
~B2
-----
~B3
~ B4
~B5
7 CHANNELS IDENTICAL
TO CHANNEL 1 ABOVE
A6~
~B6
__________________
---
A3~
~
A5~
~ B4
~ B5
7 CHANNELS IDENTICAL
A6~
:~~
A2~
~B3
I" ::::
B6
r---t3IB7
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~BB
Pin numbers shown are for JT and NT packages.
CJ)
C
m
absolute maximum ratings, recommended operating conditions, and electrical characteristics
m
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
S
(')
See Table VII, page 2-14.
CJ)
VCC
fclock
tw
tsu
th
3-334
Clock frequency
TA - 25°C
SN54HCT646
SN74HCT646
SN54HCT648
MIN
MAX
SN74HCT648
MIN
MAX
MIN
MAX
4.5 V
0
31
0
22
5.5 V
0
16
14
36
0
23
21
24
0
0
19
27
29
UNIT
MHz
Pulse duration, CBA or
4.5 V
CAB high or low
Setup time, A before CABt
or B before CBA t
5.5 V
4.5 V
5.5 V
20
18
30
27
25
23
ns
Hold time, A after CABt
4.5 V
5
5
or B after CBA t
5.5 V
5
5
5
5
ns
".!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
17
ns
TYPES SN54HCT646, SN54HCT648, SN74HCT646, SN74HCT648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL .. 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
CBA or CAB
A or B
tpd
A or B
B or A
tpd
SBA or SABt
A or B
ten
G
A or B
tdis
G
A or B
ten
tdis
vCC
4.5 V
5.5 V
f max
DIR
DIR
31
36
Any
SN54HCT648
TYP MAX
54
64
MIN
MAX
22
24
SN74HCT646
SN74HCT648
MIN
UNIT
MAX
27
29
MHz
4.5 V
18
36
54
45
5.5 V
16
14
32
27
49
41
41
12
24
37
31
5.5 V
20
17
38
34
48
43
ns
4.5 V
25
49
57
51
74
5.5 V
22
44
67
61
55
ns
4.5 V
25
49
74
61
5.5 V
4.5 V
22
44
55
25
5.5 V
4.5 V
22
25
49
44
67
74
5.5 V
4.5 V
A or B
tt
MIN
4.5 V
A or B
SN54HCT646
TA - 25°C
34
67
49
74
ns
ns
ns
5.5 V
22
44
67
4.5 V
9
12
18
15
5.5 V
7
11
16
14
II
ns
61
55
61
55
Power dissipation capacitance
ns
en
w
(.)
ns
:>
w
c
50 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL ... 150 pF (see Note 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
CBA or CAB
A or B
tpd
A or B
B or A
PARAMETER
tpd
SBA or SABt
A or B
ten
G
A or B
ten
tt
DIR
A or B
Any
SN54HCT646
TA - 25°C
SN74HCT648
MIN
MAX
53
47
80
52
66
60
22
44
67
55
20
60
50
5.5 V
4.5 V
26
24
39
55
49
83
74
69
62
33
66
100
87
5.5 V
22
59
4.5 V
33
66
90
100
87
5.5 V
4.5 V
22
17
59
42
90
63
74
53
5.5 V
14
38
57
48
TYP
MAX
4.5 V
24
5.5 V
22
4.5 V
5.5 V
4.5 V
MIN
MIN
74
2
(.)
SN74HCT646
SN54HCT648
MAX
vCC
en
o
UNIT
J:
ns
ns
ns
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
t These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-335
II
J:
C')
s:
o
en
c
m
<
C')
m
en
3-336
TYPES SN54HC651, SN54HC652, SN74HC651, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGIStERS
WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
SN54HC651. SN54HC652 ... JT PACKAGE
SN74HC651. SN74HC652 ... JT OR NT PACKAGE
(TOP VIEW)
•
Bus Transceivers and Registers
•
Independent Registers and Enables for A
and B Buses
•
High-Current 3·State Outputs Can Drive up
to 15 LSTTL Loads
•
Multiplexed Real-Time and Stored Data
•
Choice of True and Inverting Data Paths
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
description
These devices consist of bus transceiver circuits,
Ootype flip-flops, and control circuitry arranged
for multiplexed transmission of data directly from
the data bus or from the internal storage
registers. Enable GAB and GBA are provided to
control the transceiver functions. SAB and SBA
control pins are provided to select whether realtime or stored data is transferred. A low input
level selects real-time data, and a high selects
stored data. The examples on the following page
demonstrate the four fundamental busmanagement functions that can be performed
with the 'HC651 and 'HC652.
CAB
SAB
GAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
CBA
SBA
GBA
B1
B2
B3
B4
B5 '
B6
B7
B8
II
SN54HC651. SN54HC652 ... FH OR FK PACKAGE
SN74HC651. SN74HC652 ... FH OR FN PACKAGE
(TOP VIEW)
~~~u ~~~
en
w,
e>cnuz>ucn
4
A1
A2
A3
NC
A4
A5
A6
3 2
1 282726
(.)
:>w
GBA
B1
B2
NC
B3
B4
B5
7
c
en
o
:!!
Co)
12 13 14 1516 1718
Data on the A or B data bus, or both, can be
"", CD C U CD "" co
<{<{ZZCDIDID
stored in the internal 0 flip-flops by low-to-high
e>
NC-No internal connection
transitions at the appropriate clock pins (CAB or
CBA) regardless of the select or enable control
pins. When SAB and SBA are in the real-time
transfer mode, it is also possible to store data
without using the internal Ootype flip-flops by simultaneously enabling GAB and GBA. In this configuration
each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high
impedance, each set of bus lines will remain at its last state.
:r:
The SN 54HC651 and SN 54HC652 are characterized for operation over the full military temperature range
of -55°C to 125°C. The SN74HC651 and SN74HC652 are characterized for operation from -40°C
to 85°C.
'1!1
INSTRUMENTS
TEXAS
POST OFFICE BOX 225012 • DAllAS. TeXAS 75265
Copyright © 1982. Texas Instruments Incorporated
3-337
TYPES SN54HC651, SN54HC652, SN74HC651, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
(3)
II
(21)
(1)
(23)
GAB GBA CAB CBA
L
J:
o
L
X
(2)
(22)
SAB
SBA
X
L
X
(3)
(21)
(1)
GAB GBA CAB
H
H
X
(23) - (2)
(22)
CBA
SAB
SBA
X
L
X
REAL-TIME TRANSFER
REAL-TIME TRANSFER
BUS B TO BUS A
BUS A TO BUS B
s:
o
U)
C
m
~
o
m
U)
(3)
(21)
(1)
(23)
GAB GBA CAB CBA
X
H
t
L
L
X
X
t
H
(2)
(22)
SAB
SBA
X
X
X
X
X
X
X
t
(3)
(1)
(23)
TRANSFER
TO A AND/OR B
Pin numbers shown are for JT and NT packages.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
(2)
(22)
CBA SAB SBA
H or L H
H
STORED DATA
STORAGE FROM
A AND/OR B
3-338
(21)
GAB GBA CAB
H
. L H or L
TYPES SN54HC651, SN54HC652, SN74HC651, SN74HC652
OCTAL· BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
FUNCTION TABLE
DATA IIOt
INPUTS
GAB GBA
L
H
CAB
CBA
SAB
SBA
X
L
H
H
H
H
t
t
t
L
X
H or L
L
L
t
L
L
X
OPERATION OR FUNCTION
t
X
Input
Input
H or L
X
X
Input
Not specified
t
t
t
X
X
X
X
Input
Not specified
Output
Input
X
X
Output
Input
X
L
Output
Input
X
H
X
L
X
H
X
X
Input
Output
H
H
Output
Output
L
L
X
H
H
H
X
H or L
H
L
H or L H or L
'HC652
Isolation
Isolation
Store A and B Data
Store A and B Data
Store A, Hold B
Store A, Hold B
Store A in both registers
Store A in both registers
Hold A, Store B
Hold A, Store B
Store B in both registers
Store B in both registers
Real-Time B Data to A Bus Real-Time B Data to A Bus
X
H or L
H
'HC651
Bl THRU B8
X
X
H or L H or L
X
Al THRU A8
Stored
B Data
to A Bus
Stored B Data. to A Bus
Real-Time A Data to B Bus Real-Time A Data to B Bus
Stored
A Data
to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and
Stored A Data to B Bus and
Stored B Data to A Bus
Stored B Data to A Bus
t The data output functions may· be enabled or disabled by various signals at the GAB and GBA i·nputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.
logic symbols
GBA
GAB
CBA
SBA
CAB
SAB
(21)
(3)
(23)
(22)
(1)
(2)
GBA
GAB
CBA
SBA
CAB
SAB
(20)
(4)
Al
;;'1<1
5
1
(5)
.,
en
w
'HC652
'HC651
(21)
(3)
(23)
(22)
(.)
ENl [BA]
>
W
c
en
EN2 [AB]
C4
(1)
(2)
o
(20)
(4)
Bl
II
Bl
Al
2
(.)
5
::I:
(5)
(19)
A2
B2
(6)
(18)
(7)
(17)
(8)
(16)
(9)
(15)
(10)
(14)
B3
A3
A4
B4
A5
B5
A6
A7
A8
(19)
A2
B2
(6)
(18)
(7)
(17)
(8)
(16)
(9)
(15)
(10)
(14)
(11)
(13)
A3
B3
A4
B4
A5
B6
A6
B7
A7
B8
A8
(13)
(11)
"1
B5
B6
B7
B8
Pin numbers shown are for JT and NT packages.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-339
TYPES SN54HC651, SN54HC652, SN74HC651, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
logic diagram (positive logic)
'HC652
'HC651
GBA _(2_11~• .....----,
GBA
.:.:(2:.:..:11_~>----,
GAB~(3~1__~>
__+-__________________-,
+-____~________~~~
CBA7.(2~31~____
SBA ~(~1'-----I----~C>_+-d"..........
~::J2=-~~-+~~~~~~
(201 Bl
(201 Bl
II
::I:
o
s:
o
fJ)
AS ::: ••
I
A6~
:~
~
7 CHANNELS IDENTICAL
TO CHANNEL I ABOVE
:~
B2
A4
AS
B3
I •• (~~: ::
:::1141 B6
::::: :
~
7 CHANNELS IDENTICAL
TO CHANNEL I ABOVE
~
A6~
I::g::
!....!ill
~
B2
:!
BS
~B6
A7~
~B7
AS (.l14~·L ___________________
B8
(111:: L____________ .:. . ______ .r-ill! :~
.r-ill!
Pin numbers shown are for JT and NT packages.
absolute maximum ratings, recommended operating conditions, and electrical characteristics
C
See Table III, page 2-8.
m
<
(;
I~::~::
A2 ::::: :
:! ~
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
m
fJ)
VCC
fclock Clock frequency
tw
. tsu
th
3.:340
Pulse duration, CBA or
CAB high or low
Setup time. A before CABt
or B before CBM
Hold time. A after CABt
or B after CBM
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25°C
MIN
0
0
0
80
16
14
100
20
17
5
5
5
TEXAS
MAX
6
31
36
SN54HC651
SN54HC652
MAX
MIN
4.3
0
22
0
25
0
115
23
20
150
30
26
5
5
5
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SN74HC651
SN74HC652
MIN
MAX
5.5
0
0
27
31
0
95
19
16
125
25
21
5
5
5
UNIT
MHz
ns
ns
ns
38
TYPES SN54HC651. SN54HC652. SN74HC651. SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
tpd
CBA or CAB
A or B
vcc
MIN
2V
4.5 V
6
31
6V
36
TYP MAX
10
40
45
tpd
A or B
SBA or SABt
B or A
2V
65
180
18
14
36
31
50
135
6V
2V
14
11
27
23
A or B
70
4.5 V
20
6V
16
ten
GBA or GAB
A or B
tdis
GBA or GAB
A or B
Any
tt
2V
4.5 V
SN54HC652
MAX
MIN
4.3
22
SN74HC652
SN74HC652
UNIT
MAX
MIN
5.5
MHz
27
31
25
4.5 V
6V
tpd
SN54HC651
TA - 25°C
270
54
225
45
46
205
41
38
170
34
35
29
190
285
240
38
57
48
48
41
2V
85
32
245
4.5 V
6V
25
20
49
42
370
74
63
305
61
52
2V
4.5 V
50
23
245
370
305
49
74
61
6V
2V
20
42
63
52
2B
60
90
75
8
6
12
10
18
15
15
13
4.5 V
6V
ns
ns
ns
II
ns
en
w
ns
U
>'
w
c
ns
en
50 pF typ
Power dissipation capacitance
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
,
PARAMETER
tpd
tpd
tpd
ten
tt
FROM
(INPUT)
TO
(OUTPUT)
CBA or CAB
A or B
A or B
SBA or SASt
GSA or GAB
B or A
A or B
A or B
Any
vCC
TA = 25°C
MIN
2V
4.5 V
TYP
90
24
MAX
SN74HC651
SN54HC652
SN74HC652
MIN
265
6V
2V
70
53
46
220
4.5 V
20
44
6V
15
38
18
SN54HC651
MAX
400
MIN
J:
UNIT
MAX
80
330
66
57
275
ns
70
55
ns
57
48
345
68
335
o
2
u
2V
80
275
415
4.5 V
24
55
6V
2V
20
47
83
70
100
330
4.5 V
33
6V
85
71
2V
27
45
66
57
210
315
265
4.5 V
17
42
63
53
6V
13
36
53
43
500
100
69
ns
60
410
82
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
tThese parameters are measured with the internal output state of the storage register opposite to that of the bus input.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-341
II
::I:
(")
s:o
en
c
m
S
(")
m
en
3-342
HIGH·SPEED
CMOS LOGIC
TYPES SN54HCT651, SN54HCT652, SN74HCT651, SN74HCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
02804. MARCH 1984
•
SN54HCT651. SN54HCT652 ... JT PACKAGE
SN74HCT651. SN74HCT652 .•• JT OR NT PACKAGE
(TOP VIEW)
Inputs are TTL-Voltage Compatible
o
Bus Transceivers and Registers
•
Independent Registers and Enables for A
and B Buses
o
High-Current 3-State Outputs Can Drive up
to 1 5 LSTTL Loads
o
Multiplexed Real-Time and Stored Data
o
Choice of True and Inverting Data Paths
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
o
Dependable Texas Instruments Quality and
Reliability
CA8
SA8
GA8
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
C8A
S8A
G8A
81
82
83
84
85
86
87
88
II
SN54HCT651. SN54HCT652 .•. FH OR FK PACKAGE
SN74HCT651. SN74HCT652 ... FH OR FN PACKAGE
(TOP VIEW)
description
These devices consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged
for multiplexed transmission of data directly from
the data bus or from the internal storage
registers. Enable GAB and GBA are provided to
control the transceiver functions. SAB and SBA
control pins are provided to select whether realtime or stored data is transferred. A low input
level selects real-time data, and a high selects
stored data. The examples on the following page
demonstrate the four fundamental busmanagement functions that can be performed
with the 'HCT651 and 'HCT652.
~~~U~~~
(!)CJ)UZ>UCJ)
4
3
2
en
w
(.)
1 282726
A1
A2
:>w
G8A
81
82
NC
83
84
85
NC
A4
A5
A6
c
en
o
~
(.)
12 1314151617 18
J:
Data on the A or B data bus, or both, can be
NC-No internal connection
stored in the internal D flip-flops by low-to-high
transitions at the appropriate clock pins (CAB or
CBA) regardless of the select or enable control
pins. When SAB and SBA are in the real-time
transfer mode, it is also possible to store data
without using the internal D-type flip-flops by
simultaneously enabling GAB and GBA. In this configuration each output reinforces its input. Thus, when
all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain
at its last state.
The SN54HCT651 and SN54HCT652 are characterized for operation over the full military temperature
range of - 55°C to 125°C. The SN74HCT651 and SN74HCT652 are characterized for operation from
-40°C to 85°C.
Copyright
4
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
©
1984. Texas Instruments Incorporated
3-343
TYPES SN54HCT651, SN54HCT652, SN74HCT651, SN74HCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
~
(3)
II
(21)
(1)
(23)
GAB GBA CAB CBA
X
(2)
(22)
SAB
SBA
X
(3)
(1)
H
X
H
X
(2)
(22)
SAB
SBA
L
X
(23)
GAB GBA CAB CBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
::J:
(21)
(")
s:
o
en
c
m
:$
(")
m
en
(3)
(21)
(1)
(23)
GAB GBA CAB CBA
X
X
1
H
X
H
(2)
(22)
SAB
SBA
X
X
X
X
X
X
X
1
(3)
(21)
(1)
GAB GBA CAB
H
L H or L
(23)
(2)
(22)
CBA SAB SBA
H or L H
H
TRANSFER
STORED DATA
TO A AND/OR B
STORAGE FROM
A AND/OR B
Pin numbers shown are for JT and NT packages.
31
3-344
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HCT651, SN54HCT652, SN74HCT651, SN74HCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH a-STATE OUTPUTS
FUNCTION TABLE
DATA I/Ot
INPUTS
GAB GBA
L
CAB
CBA
SAB
SBA
H
H or L
H or L
H or L
X
X
X
X
X
X
H or L
X
X
X
X
X
X
X
X
X
X
H
H
L
H
X
H
H
H
t
t
t
L
X
H or L
L
L
L
L
L
L
t
t
t
t
X
H
H
t
X
X
X
H
H
H or L
H
L
H or L H or L
L
OPERATION OR FUNCTION
Bl THRU B8
Al THRU A8
Input
Input
Input
Not specified
Input
Output
Not specified
Input
Output
Input
Output
Input
X
X
Input
Output
H
Output
Output
L
H
'HCT651
'HCT652
Isolation
Isolation
Store A and B Data
Store A and B Data
Store A, Hold B
Store A, Hold B
Store A in both registers
Store A in both registers
Hold A, Store B
Hold A, Store B
Store B in both registers
Store B in both registers
Real-Time B Data to A Bus
Stored
B Data
to A Bus
Real-Time A Data to B Bus
Stored
A Data
to B Bus
Real-Time B Data to A Bus
Stored B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and
Stored A Data to B Bus and
Stored B Data to A Bus
Stored B Data to A Bus
t The data output functions may be enabled or disabled by various signals at the GAB and GBA inputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.
logic symbols
'HCT651
GBA
GAB
CBA
SBA
CAB
SAB
(21)
(3)
(23)
(22)
(1)
GBA
C4
(2)
Al
;;'1<]
5
1
>
W
C
(1)
(2)
(4)
Bl
U
(21)
(3)
(23)
(22)
SAB
(4)
en
W
'HCT652
GAB
CBA
SBA
CAB
en
0
(20)
Bl
Al
5"
"1
A2
(6)
A3
(5)
(19)
(6)
(lS)
(7)
(17)
(S)
(16)
(9)
(15)
(10)
(14)
(11)
(13)
A2
B2
B3
B2
A3
B3
(7)
A4
B4
A4
B5
A5
B6
A6
B7
A7
I3s
AS
B4
(S)
A5
B5
(9)
A6
(10)
A7
(11)
AS
2
U
J:
7
(5)
II
B6
B7
BS
Pin numbers shown are for JT and NT packages.
TEXAS
-1!1
INSTRUMENlS
POST OFFICE BOX 225012 • OALLAS, TEXAS 75265
3-345
~-TYPES SN54HCT651. SN54HCT652. SN74HCT651. SN74HCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3·STATE OUTPUTS
logic diagram (positive logic)
'HCT652
'HCT651
GBA
..::(2:..:.;1):....-~>---,
GAB..::(3~)__;~~+-
__________________-,
+-____--..,-____,--__~">___+_,
CBA ..;:;(2:;3);.-____
SBA ~11~)'----::--~+_---f').,....,_
W
C
UNIT
en
o
ns
(,J
ns
~
J:
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
tThese parameters are measured with the internal output state of the storage register opposite to that of the bus input.
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-347
lEI
:::I:
(")
so
CJ)
C
m
S
(")
m
CJ)
3-348
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC658, SN54HC659, HC74HC658, SN74HC659
OCTAL BUS TRANSCEIVERS WITH PARITY
02839. MARCH 1984
•
Bus Transceivers with Inverting Outputs
('HC658) or True Outputs ('HC659)
•
Generates a Parity Bit for A Bus and B Bus
•
Easily Cascadable
SN54HC658. SN54HC659 ... JT PACKAGE
SN74HC658. SN74HC659 ... JT OR NT PACKAGE
(TOP VIEW)
•
Internal Active Pull-Ups and Pull-Downs
•
High-Current 3-5tate Outputs Can Drive up
to 15 L5TTL Loads
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
, Reliability
GAB
A1
A2
A3
A4
A5
A6
A7
A8
BPI
BPO
GND
description
II
SN54HC658. SN54HC659 ... FH OR FK PACKAGE
SN74HC658. SN74HC659 ... FH OR FN PACKAGE
(TOP VIEW)
These octal bus transceivers are designed for
asynchronous, bidirectional communication
between data buses. The devices transmit data
from the A Bus to the B Bus or from the B Bus
to the A Bus, depending on the level at the
direction control inputs, GAB and GBA. These
devices also generate parity outputs, APO and
BPO, which reflect the number of high levels at
the A Bus and B Bus, respectively, taking into
account the parity inputs API and BPI.
The bidirectionalI/O ports feature active circuitry
on the input stage that, when the output shared
by that pin is disabled, will maintain the input in
the last state taken by the output. This state will
be maintained until changed by activity on the
bus. The advantage of this arrangement is that
when all outputs on the bus are disabled, the
inputs will be prevented from floating, resulting
in minimum power dissipation and minimum
susceptibility to noise. This eliminates any need
for external pull-up or pull-down resistors. The
parity inputs API and BPI have similar circuits.
For further information, see Typical Application
Data.
VCC
GBA
B1
B2
B3
B4
B5
B6
B7
B8
API
APO
en
III
U«
N .... «UUIIl ....
««(!)Z>I(!)1Il
4
3 2
W
CJ
1
A3
A4
A5
NC
A6
A7
A8
:>W
B2
B3
B4
NC
B5
B6
B7
C
en
0
2
CJ
:I:
12 131415161718
o:oouoo:co
lIl~aZ~«1Il
NC-No internal connection
The SN54HC658 and SN54HC659 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74HC658 and SN75HC659 are characterized
for operation from - 40°C to 85 DC.
Copyright © 1984. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-349
TYPES SN54HC658. SN54HC659. SN74HC658. SN74HC659
OCTAL BUS TRANSCEIVERS WITH PARITY
FUNCTION TABLE
CONTROL
NUMBER OF HIGH
INPUTS
INPUTS ON
GBA GAB
A BUS AND API
L
X
X
H
H
0,2,4,6,8
1,3,5,7,9
H
L
L
L
H
X
X
X
NUMBER OF HIGH
INPUTS ON
B BUS AND BPI
0,2,4,6,8
1,3,5,7,9
X
X
X
OUTPUTS
APO
BPO
Z
Z
H
H
L
Z
Z
Z
Z
0, 2, 4, 6, 8
X
X
1,3,5,7,9
'HC659
'HC658
B Data
L
to A Bus
A Data to
B Data to A Bus
A Data to B Bus
B Bus
Isolation
Isolation
H
1,3,5,7,9
0,2,4,6,8
OPERATION
B Data
L
to A Bus,
A Data to
H
B Data to A Bus,
A Data to B Bus
B Bus
L
logic symbols
III
'HC658
:::t
(")
S
0
en
C
m
<
(5
m
'HC659
GBA
GAB
GAB
A1
A1
A2
A2
A3
A3
A4
A4
A5
A5
A6
A6
A7
A7
A8
AS
API
API
en
2k
2k
Pin numbers shown are for JT and NT packages.
3-350
TEXAS •
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC658, SN54HC659, SN74HC658, SN74HC659
OCTAL BUS TRANSCEIVERS WITH PARITY
logic diagram (positive logic)
r
I
---------------
I
I
I
I
I
'HC659
I
(21
A1
(22)
-
w
c
API
en
(14)
lO----------I
>4-4--+-+-+-1-4--+--";"(1_3_) APO
0
:E
o
J:
BPO
(11)
- - - + - - - - - - < 1-----------0(.
(10) BPI
Pin numbers shown are for JT and NT packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-B.
Because ofthe nature of the transceiver I/O ports and the parity inputs, the following additional parameter
also applies. It is the peak current as the input changes from 0 V to Vee.
SN54HC658
PARAMETER
TEST CONDITION
VCC
TA - 25°C
MIN
11M
VI = 0 to Vee
6V
TYP
MAX
SN54HC659
MIN
±400
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
MAX
±520
SN74HC658
SN74HC659
MIN
UNIT
MAX
±520
p.A
3-351
TYPES SN54HC658. SN74HC658
OCTAL BUS TRANSCEIVERS WITH PARITY
'HC658 switching characteristics over recommended operating free-air temperature range (unless
. otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
A or B
tpd
A or B
tpd
ten
II
tdis
J:
FROM
(INPUT)
API
or
BPI
GAB
APO
or
BPO
APO
or
BPO
APO
or
GBA
GAB
or
GBA
or
BPO
APO
or
BPO
cm
<
TA = 25°C
MIN TYP MAX
150
75
15
13
115
23
20
77
15
13
117
23
20
117
23
20
28
8
6
6V
2V
4.5 V
6V
2V
4.5 V
6V
Any
S
oen
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
B or A
tt
(")
TO
(OUTPUT)
30
26
230
46
39
155
31
26
235
47
SN54HC658
MIN
MAX
225
45
38
345
69
59
235
47
40
355
71
60
355
71
60
90
18
15
40
235
47
40
60
12
10
Power dissipation capacitance
Cpd
SN74HC658
MIN
MAX
190
38
32
290
58
49
195
39
33
295
59
50
295
59
50
75
15
13
UNIT
ns
ns
ns
ns
ns
ns
56 pF typ
'HC658 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 150 pF (see Note 1)
(;
PARAMETER
m
en
tpd
FROM
(INPUT)
A or B
tpd
A or B
tpd
API
or
BPI
ten
GAB
or
GBA
tt
TO
(OUTPUT)
B,or A
APO
or
BPO
APO
or
BPO
APO
or
BPO
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
117
235
23
47
20
41
157
315
31
63
27
54
120 240
24
48
20
41
160 320
32
64
27
55
37
210
12
42
10
36
SN54HC658
MIN
MAX
355
71
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
3-352
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
365
73
62
485
SN74HC658
MIN
MAX
295
59
51
395
79
68
300
60
52
400
97
82
315
63
53
80
69
265
53
45
60
475
95
81
UNIT
ns
ns
ns
ns
ns
TYPES SN54HC659, SN74HC659
OCTAL BUS TRANSCEIVERS WITH PARITY
'HC659 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
B or A
tpd
A or B
tpd
ten
tdis
API
or
BPI
GAB
or
GBA
GAB
or
GBA
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
APO
or
BPO
APO
or
BPO
APO
or
BPO
APO
or
BPO
Any
tt
VCC
TA = 25°C
MIN TYP MAX
70 140
14
28
24
12
115 230_
46
23
20
39
77
155
15
31
13
26
117 235
23
47
20
40
117 235
23
47
20
40
28
60
8
12
10
6
SN54HC659
MIN
MAX
210
42
36
345
69
59
235
47
40
355
71
60
355
71
60
90
18
15
•
CJ)
W
(.)
:>w
56 pF typ
Power dissipation capacitance
Cpd
SN74HC659
UNIT
MIN
MAX
175
35
ns
30
290
58
ns
49
195
39
ns
33
295
59
ns
50
295
59
ns
50
75
15
ns
13
C
'HC659 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
B or A
tpd
A or B
tpd
ten'
tt
API
or
BPI
GAB
or
GBA
APO
or
BPO
APO
or
BPO
APO
or
BPO
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
,2 V
4.5 V
6V
TA = 25°C
MIN TYP MAX
117 225
45
23
20
39
157 315
31
63
54
27
120 240
48
24
41
20
160 320
32
64
27
55
37 210
12
42
10
36
SN54HC659
MIN
MAX
340
68
58
475
95
81
365
73
62
485
97
82
315
63
53
SN74HC659
UNIT
MAX
MIN
280
56
ns
49
395
79
ns
68
300
60
ns
52
400
80
ns
69
265
53
ns
45
CJ)
0
~
(.)
::I:
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-353
TYPES SN54HC658. SN54HC659. SN74HC658. SN74HC659
OCTAL BUS TRANSCEIVERS WITH PARITY
TYPICAL APPLICATION DATA
The unique structure used on the I/O ports and the parity inputs of these devices deserves some special
consideration (see Figure 1). Only the input structure is shown. The conventional 3-state output structure
associated with each I/O port has been omitted to facilitate understanding
>-.....-1.... TO INTERNAL CIRCUITRY
INPUT -1.--.....
G1
G2
FIGURE 1. INPUT STRUCTURE
II
:J:
o
s:
oen
cm
<
om
en
The two inverters (G 1 and G2) have a transmission gate (TG1) connected in a feedback loop around them.
This transmission gate is connected in an unusual fashion, that is, with the gates of both transistors connected
to the output of G 1. Thus, with the output of G 1 at either a high or a low level, one or the other of the transistors
will be turned on allowing feedback of the output of G2 to the input of G 1. The effect of TG 1 is that the input
level will be maintained at whatever level existed prior to the bus being disabled or the level currently existing
on the bus will be reinforced.
I
To understand the operation of this input, assume that initially the input is at a low logic level. As the input
voltage is raised, TG1 sinks current to attempt to maintain the low level. However, TG1 consists of small geometry
transistors and appears resistive as current flows thus allowing the input voltage to rise toward the threshold
voltage of G1. When the threshold voltage is reached; G1 changes state causing G2 to change state. G2 then
attempts to maintain a high level on the input through TG1. A similar operation occurs when the input voltage
is decreased toward the threshold voltge of G1. G2 sources current through TG1 until the threshold is reached.
This characteristic of the input stage has some implications for the input current levels. With the input held
at either VCC or GND, there is no voltage across TG1 and negligible input current. However, as the input voltage
is raised from GND or lowered from VCC, the input current rises as the voltage across TG1 increases. The input
current continues to rise until it reaches a maximum just as the threshold voltage of G 1 is reached. This maximum
corresponds to parameter 11M shown in the electrical characteristics table. Because G 1 consists of small geometry
transistors, 11M has a value much lower than the output drive capability of a conventional 'HC output stage.
Also for this reason, the input configuration has negligible effect when the I/O port is used as an output.
This configuration provides for minimum power dissipation when the bus is inactive (all outputs on the bus
in the high-impedance state) and minimum susceptibility to noise on the bus during this time. The increase in
input current may go unnoticed as it only occurs during transitions on the bus. Care must be taken when measuring
input currents (e.g., at incoming inspection) to ensure that the input voltage is set to the correct value.
The use of these devices for interfacing to 8-, 16-, and 24-bit-wide memory arrays with parity is illustrated
in Figures 2, 3, and 4.
3-354
TEXAS
-I/}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC658. SN54HC659. SN74HC658. SN74HC659
OCTAL BUS TRANSCEIVERS WITH PARITY
TYPICAL APPLICATION DATA
'HC6581'HC659
GBA
RM
GAB
OATA BUS
OOTHRU 07
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
B8
A8
API
APO
BPO
BPI
FIGURE 2. a·BIT·WIDE MEMORY ARRAY WITH PARITY
'HC6581'HC659
CONTRO
L
{-~
~t-i
....
-"".
OATABUS
OOTHRU 07
GBA
RM
GAB
A1
B1
A2
B2
A3
B3
A4
84
A5
B5
A6
B6
A7
B7
A8
•
en
w
CJ
:;
..oL--",
w
c
en
o
..oL--",
~
CJ
:J:
B8
APO t-
BPI'
BPO
ERROR
_.RAM
[R/W)
API
'HC6581'HC659
'--
RAM
GBA
RJW
[Rm)
" - - - GAB
~
OATA BUS
08 THRU 015
....
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
r-
B8
BPI
APO
API
BPO
.L
- J
FIGURE 3. 16·BIT·WIDE MEMORY ARRAY WITH PARITY
'1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-355
TYPES SN54HC658, SN54HC659, SN74HC658, SN74HC659
OCTAL BUS TRANSCEIVERS WITH PARITY
TYPICAL APPLICATION DATA
'HC65S/'HC659
CONTROL {
~R/WJRAM
GBA
GAB
r"'_
.....
DATA
BUS
<
DO THRU
D7
,p
....
"-
I
~
III
en
C
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
AS
BS
API
BPO
r
, ...
..
APO~
BPI
~
q.
r
PARITY BIT
'HC65S/'HC659
~
~!WIRAM
GBA
~- GAB
A1
(")
o
B1
RtW
::t
S
A1
p
DATA
BUS
DS THRU
D15
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
...
(
-"'
m
B7
AS
BS
API
~
(")
===
m
A7
[
en
BPO
'HC2S0
APO~
BPI~
A
2k
C
'HC65S/'HC659
L---
'"
DATA
BUS
D16 THRU
D23
-
GBA
r-- E
[R/WI RAM
GAB
.......
..La.
<
B1
B2
~
A3
B3
~I
A4
B4
A5
B5
A6
B6
A7
B7
BPO
I:
EVEN
~
PARTOF
'HCOO
~u-
F
A2
AS
I"
~
A1
~API
-=
;--- D
B
PART OF
'HC367
B
~G
,p
~
p
H
I:
ODD
~ERROR
J
-=
..
,p
BS
APO
BPI
*
FIGURE 4. 24·BIT·WIDE MEMORY ARRAY WITH PARITY
NOTE: The 'HC280 elin;tinates ripple carry delays associated with Figures 2 and 3. However, in those two cases the delays are probably
too small to be of concern.
3-356
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
HIGH·SPEED
CMOS LOGIC
TYPES SN54HCT65B, SN54HCT659, SN74HCT65B, SN74HCT659
OCTAL BUS TRANSCEIVERS WITH PARITY
02839. MARCH 1984
SN54HCT658. SN54HCT659 ... JT PACKAGE
SN74HCT658. SN74HCT659 ... JT OR NT PACKAGE
(TOP VIEW)
•
Inputs are TTL·Voltage Compatible
•
Bus Transceivers with Inverting Outputs
('HCT658) or True Outputs ('HCT659)
•
Generates a Parity Bit for A Bus and B Bus
•
Easily Cascadable
•
Internal Active Pull-Ups and Pull-Downs
•
High-Current. 3-State Outputs Can Drive up
to 15 LSTTL Loads
•
Pac~age Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
description
These octal bus transceivers are designed for
asynchronous, bidirectional communication
between data buses. The devices transmit data
from the A Bus to the B Bus, or from the B Bus
to the A Bus, depending on the levels at the
direction control inputs, GAB and GBA. These
devices also generate parity outputs, APO and
BPO, which reflect the number of high levels at
the A Bus and B Bus, respectively, taking into
account the parity inputs API and BPI.
GA8
A1
A2
A3
A4
A5
A6
A7
A8
8PI
8pa
GND
VCC
~8A
81
82
83
84
85
86
87
88
API
APa
II
SN54HCT658. SN54HCT659 ... FH OR FK PACKAGE
SN74HCT658. SN74HCT659 ... FH OR FN PACKAGE
(TOP VIEW)
III
U <{
N..-<{UUIll..<{ <{ t!) Z
It!) III
(J)
>
4
3
2
W
U
1
A3
A4
A5
82
83
84
NC
NC
A6
A7
A8
85
86
87
>
w
C
(J)
The bidirectional I/O ports feature active circuits
12131415161718
on the input stage that, when the output shared
by that pin is disabled, will maintain the input in
the last state taken by the output. This state will
be maintained until changed by activity on the
NC-No internal connection.
bus. The advantage of this arrangement is that
when all outputs on the bus are disabled, the
inputs will be prevented from floating, resulting in minimum power dissipation and minimum susceptibility
to noise. This eliminates any need for external pull-up or pull-down resistors. The parity inputs API and
BPI have similar circuits. For further information, see Typical Application Data in 'HC658 series data sheet.
o
2
u
::I:
The SN54HCT658 and SN54HCT659 are characterized for operation over the full military temperature
range of - 55 °e to 125°e. The SN74HCT658 and SN74HCT659 are characterized for operation from
-40°C to 85°C.
Copyright © 1984. Texas Instruments Incorporated
TEXAS
-1.11
INSTRUMENTS
POST OFFiCe BOX 225012 • DALLAS. TeXAS 75265
3-357
TYPES SN54HCT658, SN54HCT659, SN74HCT658, SN74HCT659
OCTAL BUS TRANSCEIVERS WITH PARITY
FUNCTION TABLE
CONTROL
INPUTS
GBA
NUMBER OF HIGH
NUMBER OF HIGH
INPUTS ON
INPUTS ON
OUTPUTS
GAB
A BUS AND API
B BUS AND BPI
APO
L
X
X
0,2,4,6,8
Z
Z
H
0,2.4,6,8
X
X
X
H
Z
Z
Z
L
H
H
H
L
L
1,3,5,7,9
1,3,5,7,9
X
X
X
H
L
L
Z
0,2.4,6,8
X
X
1,3,5,7,9
OPERATION
'HCT658
'HCT659
B Data to
A Bus
B Data to A Bus
A Data to
B Bus
A Data to B Bus
Isolation
Isolation
H
1,3,5,7,9
0, 2, 4, 6, 8
BPO
L
B Data
to A Bus,
A Data to
H
B Bus
L
logic symbols
II
'HCT659
'HCT658
GBA
GAB
::t
GAB
[>
C
m
~
n
m
en
[>
A3
A3
A4
A4
A5
A5
A6
A6
A7
A7
[>
2k
API
11
, 12
13
14
15
16
17
18
2k
11
12
13
14
15
16
17
18
Pin numbers shown are for JT and NT packages.
3-358
2k
API
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
2k
B Data to A Bus,
A Data to B Bus
TYPES SN54HCT658, SN54HCT659, SN74HCT658, SN74HCT659
OCTAL BUS TRANSCEIVERS WITH PARITY
logic diagram (positive logic)
r
I
I
I
I
I
I
Al
A2
A3
A4
AS
AS
A7
AS
(3)
'HCTS59
I
(2)
(22)
---w
c
API
(14)
»--------1
>+-+-+-+-+-1-+-+---:..(1:...;.3:,..) APO
en
o
~
(.)
::I:
(11)
BPO
- - - + - - - - - - < 1-------«
(10) BPI
Pin numbers shown are for JT and NT packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table VII, page 2-14.
Because of the nature of the transceiver I/O ports and the parity inputs, the following parameter also applies.
It is the peak current as the input changes from 0 V to Vee. '
PARAMETER
TEST CONDITION
VCC
TA - 25°C
MIN
11M
VI = 0 to Vee
TYP
5.5 V
TEXAS
MAX
±400
SN54HCT658
SN54HCT659
MIN
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
MAX
±520
SN74HCT658
SN74HCT659
MIN
MAX
±520
UNIT
p.A
3-359
TYPES SN54HCT658. SN74HCT658
OCTAL BUS TRANSCEIVERS WITH PARITY
'HCT658 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL "" 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
B or A
tpd
A or B
APa or BPa
tpd
ten
tdis
API or BPI
GAB or GBA
GAB or GBA
APO or BPa
APa or BPO
APa or BPa
Any
tt
vCC
TA - 25°C
MIN
TYP MAX
SN54HCT658
MIN
SN74HCT658
MAX
MIN
MAX
4.5 V
15
30
45
38
5.5 V
4.5 V
13
23
27
46
41
34
58
5.5 V
20
41
62
52
4.5 V
15
31
47
39
28
42
35
69
5.5 V
14
4.5 V
24
47
71
59
5.5 V
·4.5 V
21
42
64
53
24
47
71
59
5.5 V
21
42
64
53
4.5 V
8
12
18
15
5.5 V
7
11
16
14
UNIT
ns
ns
ns
ns
ns
ns
1IIIIiII~1-----C-P-d----~----p-o-w-e-r-d-is-si-pa-t-io-n-c-ap-a-ci-ta-n-ce--------r----N-o-l-oa-d-,-T-A-=--2-5-oC----~-------62--PF--ty-p----~
J:
C')
S
'HCT658 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 150 pF (see Note 1)
oen
PARAMETER
cm
::5
C')
m
en
FROM
TO
(INPUT)
(OUTPUT)
tpd
A or B
B or A
tpd
A or B
APO or BPa
tpd
API or BPI
APO or BPa
ten
GAB or GBA
APO or BPa
tt
Any
Vcc
TA - 25°C
MIN
TYP MAX
SN54HCT658
MIN
SN74HCT658
MAX
MIN
MAX
4.5 V
23
47
71
59
5.5 V
21
42
64
53
4.5 V
31
63
95
79
5.5 V
28
56
85
71
4.5 V
24
48
73
60
5.5 V
21
43
65
54
4.5 V
32
64
97
80
5.5 V
28
57
87
72
4.5 V
17
42
63
53
5.5 V
14
38
57
48
UNIT
ns
ns
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
For typical application data and a description of the unique input structure, see the 'He658 series data sheet.
3-360
TEXAS·
..J.!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HCT659, SN74HCT659
OCTAL BUS TRANSCEIVERS WITH PARITY
'HCT659 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL ... 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
B or A
tpd
A or B
APO or BPO
tpd
API or BPI
APO or BPO
ten
GAB or GBA
APO or BPO
tdis
GAB or GBA
APO or BPO
Any
tt
vCC
TA - 25°C
MIN TYP MAX
SN54HCT659
MIN
SN74HCT659
MAX
MIN
MAX
4.5 V
14
28
42
5.5 V
4.5 V
12
23
25
46
61
5.5 V
20
41
4.5 V
31
28
39
5.5 V
15
14
62
47
42
35
4.5 V
24
71
59
5.5 V
4.5 V
21
24
47
42
47
64
71
53
59
5.5 V
21
42
8
7
12
64
18
53
4.5 V
11
16
5.5 V
69
UNIT
35
50
ns
58
52
ns
15
14
ns
ns
ns
ns
r---;::-----,~:___:___:__~~~--,
Cpd
Power dissipation capacitance
No load. T A = 25 DC
62 pF typ
'HCT659 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 150 pF (see Note 1)
,
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
tpd
A or B
B or A
4.5 V
5.5 V
tpd
A or B
APO or BPO
tpd
API or BPI
APO or BPO
ten
GAB or GBA
APO or BPO
tt
Any
TA - 25-DC
MIN
TYP MAX
45
40
4.5 V
23
20
32
5.5 V
28
4.5 V
24
56
48
5.5 V
21
43
4.5 V
5.5 V
4.5 V
32
29
64
57
21
42
5.5 V
19
38
SN54HCT659
MAX
MIN
63
68
84
95
85
73
65
97
87
63
57
SN74HCT659
MIN
MAX
UNIT
II
en
w
(.)
:>w
c
en
56
67
ns
79
71
ns
o
60
54
ns
(.)
80
72
53
48
:E
J:
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
For typical application data and a description of the unique input structure, see the 'He658 series data sheet.
4
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-361
II
J:
(')
s
o
C/J
C
m
~
(')
m
C/J
3-362
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC664, SN54HC665, SN74HC664, SN74HC665
OCTAL BUS TRANSCEIVERS WITH PARITY
D2839. MARCH 1984
o
SN54HC664. SN54HC665 ... JT PACKAGE
SN74HC664. SN74HC665 ... JT OR NT PACKAGE
(TOP VIEW)
Bus Transceivers with Inverting Outputs
('HC664) or True Outputs ('HC665)
•
Generates a Parity Bit for A Bus and B Bus
•
Easily Cascadable
•
Internal Active Pull-Ups and Pull-Downs
•
High-Current 3-State Outputs Can Drive up
to 15 LSTTL Loads
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in· Addition to Plastic
and Ceramic DIPs
DIR
VCC
A1
G
A2
B1
A3
A4
B2
B3
A5
A6
B4
A7
B6
B5
A8
BPI
o Dependable Texas Instruments Quality and
Reliability
B7
BPO
B8
API
GND
APO
description
These octal bus transceivers are designed for
asynchronous, bidirectional communication
between data buses. The devices transmit data
from the A Bus to the B Bus or from the B Bus
to the A Bus, depending on the level at the
direction control input, DIR. The enable input, G,
can be used to disable the device so that the
buses are isolated. These devices will also
generate parity outputs, APO and SPO, which
reflect the number of high levels at the A Bus
and B Bus, respectively, taking into account the
parity inputs API and BPI.
The bidirectional I/O ports feature active circuitry
on the input stage that, when the output shared
by that pin is disabled, will maintain the input in
the last state taken by the output. This state will
be maintained until changed by the activity on
the bus. The advantage of this arrangement is
that when all outputs on the bus are disabled,
the inputs will be prevented from floating,
resulting in minimum power dissipation and
minimum susceptibility to noise. This eliminates
any need for external pull-up or pull-down
resistors. The parity inputs API and BPI have
similar circuitry. For further information, see the
Typical Application Data.
II
SN54HC664. SN54HC665 ... FH OR FK PACKAGE
SN74HC664. SN74HC665 ... FH OR FN PACKAGE
(TOP VIEW)
a:
en
U
~ ~ 0 ~ ~I(!) co
432
W
U
1
>
W
A3
82
A4
A5
83
84
NC
NC
A6
A7
85
0
86
87
U
A8
C
en
~
J:
12 131415161718
a:oouoa:CX)
CD~aZ~
A2 (3)
:J:
0
[>
s:0
en
cm
<
[>
A3 (4)
A3 (4)
A4 (5)
A4 (5)
A5 (6)
A5 (6)
A6 (7)
A6 (7)
A7 (8)
A7 (8)
0
m
en
AS (9)
Q1
2k
API (14)
AS (9)
2k
2k
11
12
13
14
15
16
11
12
13
14
15
16
17
18
17
18
BPO (11)
(10) BPI
Q1
BPO (11)
Q1
24
25
26
27
28
(10) BPI
Pin numbers shown are for JT and NT packages.
38
3-364
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC664. SN54HC665. SN74HC664. SN74HC665
OCTAL BUS TRANSCEIVERS WITH PARITY
logic diagram (positive logic)
ii(23)
~
~~+-----~
DIR .:..:(1~)_ _ _ _--f
r----l---~~h
J'o....
~
~
I
A
1 ~------------~~-.~I~
(2)
2
A
3
A
A4
A5
A6
7
A
8
A
~--l-~~'HC664
TG
1
1-- - - - - - - - - - -'- -
(7)
(8)
(9)
b
.....
-+-+-+--+-~-+-+--+-
API ..:..,;(1:...:,4;..)
:l---+--fTG
___
(JJ
w
(J
>
V - - .-.,.
1>+-+--+-+-1-+-+--+---,-(1---,,, APO
./
l...-'=--=--=--=--=-_=_=~~i~lIi=)'
(11)
II
~[
'----+-~JJr
BPO
i
---~
(21)
B2
I~~~----------~
(20)
B3
(19)
I
B4
(18)
7 INVERTING (NONINVERTING FOR 'HC665) ..................
'
-t-+--ir--t-.........------:-=
B5
(17)
CHANNELS IDENTICAL TO CHANNEL 1 ABOVE ...........
'
_-+-+-+-1-+.........-----:-:-::-:B6
(16)
B5
I
(15)
BS
'HC665
(3)
(4)
(5)
(S)
I
'HC665
(22)
~I~~.-__________~~ B1
'HC664
~~-=-_=_=_=======~~1--~~
0~
(f
"'-.
,...-..
,-
_
~
J:
r<'-l\-II-----------'
~,==_~[.------------~
,-.
~
I--J+--------------------'(~10) BPI
~
Pin numbers shown are for JT and NT packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
Because of the nature of the transceiver I/O ports and the parity inputs, the following additional parameter
applies. It is the peak current as the input changes from 0 V to Vee.
SN54HC664
PARAMETER
TEST CONDITION
VCC
TA MIN
11M
VI = 0 to Vee
25°C
TYP
MAX
SN54HC665
MIN
±400
6V
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
MAX
±520
SN74HC664
SN74HC665
MIN
UNIT
MAX
±520
p.A
3-365
TYPES SN54HC664. SN74HC664
OCTAL BUS TRANSCEIVERS WITH PARITY
'HC664 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL 1:1 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
tpd
tpd
tpd
ten
II
J:
APO or
A or B
BPO
API or
APO or
BPI
BPO
Gor
190
45
38
32
13
115
30
26
230
38
345
4.5 V
23
46
69
58
6V
20
39
59
2V
4.5 V
77
15
13
125
25
22
125
25
22
28
8
6
155
235
47
49
195
4.5 V
6V
2V
Any
225
6V
2V
2V
A or B
150
4.5 V
6V
DIR
SN74HC664
MIN
MAX
MIN
75
15
6V
2V
4.5 V
A or B
DIR
tt
o
en
c
B or A
Gor
tdis
o
3:
m
A or B
SN54HC664
MAX
TA - 25°C
MIN
TYP MAX
4.5 V
6V
31
33
320
77
64
65
54
255
385
51
43
60
77
65
90
18
15
320
64
Power dissipation capacitance
Cpd
39
40
385
12
ns
290
26
255
51
43
10
UNIT
ns
ns
ns
ns
54
75
15
ns
13
56 pF typ
'HC664 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL - 150 pF (see Note 1)
S
om
PARAMETER
en
tpd
tpd
tpd
ten
tt
FROM
(INPUT)
A or B
A or B
TO
(OUTPUT)
B or A
APO or
BPO
API or
APO or
BPI
BPO
Gor
DIR
A or B
Any
VCC
TA - 25°C
MIN TYP MAX
2V
116
4.5 V
6V
SN54HC664
MIN
MAX
SN74HC664
MIN
MAX
23
20
157
235
47
41
355
71
60
295
59
51
315
475
395
63
54
95
81
79
6V
31
27
2V
4.5 V
120
24
240
365
48
6V
2V
20
170
41
340
73
62
515
300
60
52
4.5 V
34
68
103
425
85
6V
29
87
73
2V
37
58
210
315
265
4.5 V
12
10
42
63
53
36
53
45
2V
4.5 V
6V
UNIT
ns
ns
68
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
38
3-366
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC665, SN74HC665
OCTAL BUS TRANSCEIVERS WITH PARITY
'HC665 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tpd
tpd
ten
tdis
FROM
(INPUT)
A or B
A or B
API or
BPI
TO
(OUTPUT)
vCC
B or A
2V
4.5 V
6V
APO or
BPO
APO or
BPO
G or
A or B
DIR
G or
A or B
DIR
Any
tt
TA - 25°C
MIN
TYP MAX
MAX
140
210
28
24
42
2V
70
14
12
115
4.5 V
23
230
46
6V
20
39
2V
4.5 V
6V
77
155
31
26
36
345
SN74HC665
MIN
MAX
175
35
30
58
59
235
49
195
47
40
39
33
2V
25
255
51
385
4.5 V
77
320
64
6V
22
43
65
54
2V
125
255
385
4.5 V
6V
25
22
51
43
77
65
320
64
54
2V
28
90
75
4.5 V
8
60
12
18
6V
6
10
15
15
13
No load, TA
=
UNIT
ns
290
69
15
13
125
Power dissipation capacitartce
Cpd
SN54HC665
MIN
ns
ns
ns
II
ns
(J)
ns
W
(.)
>
56 pF typ
25°C
W
'HC665 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 150 pF (see Note 1)
PARAMETER
tpd
tpd
tpd
ten
tt
FROM
(INPUT)
A or B
A or B
API or
BPI
G or
DIR
TO
(OUTPUT)
VCC
B or A
2V
4.5 V
6V
APO or
BPO
SN54HC665
MIN
MAX
SN74HC665
MIN
MAX
22
225
45
340
68
39
2V
20
157
315
58
475
280
56
49
4.5 V
31
6V
27
120
63
54
95
81
240
365
24
20
48
41
73
62
TA - 25°C
MIN
TYP MAX
112
395
79
(J)
o
:E
(.)
ns
:I:
ns
68
APO or
BPO
2V
4.5 V
6V
2V
170
340
4.5 V
34
68
515
103
425
A or B
6V
29
37
12
10
87
315
73
2V
4.5 V
6V
58
210
42
36
63
53
Any
UNIT
C
300
60
52
85
265
53
45
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-367
TYPES SN54HC664, SN54HC665, SN74HC664, SN74HC665
OCTAL BUS TRANSCEIVERS WITH PARITY
TYPICAL APPLICATION DATA
The unique structure used on the I/O ports and the parity inputs of these devices deserves some special
consideration (see Figure 1). Only the input structure is shown. The conventional 3-state output structure
associated with each I/O port has been omitted to facilitate understanding.
INPUT
>-....-t~ TO INTERNAL CIRCUITRY
--1~.-t
G1
G2
FIGURE 1. INPUT STRUCTURE
J:
(")
S
o
tn
C
m
$
(")
m
tn
The two inverters (G 1 and G2) have a transmission gate (TG 1) connected in a feedback loop around them.
This transmission gate is connected in an unusual fashion, that is, with the gates of both transistors connected
to the output of G 1. Thus, with the output of G 1 at either a high or a low level, one or the other of the transistors
will be turned on allowing feedback of the output of G2 to the input of G1. The effect of TG1 is that the input
level will be maintained at whatever level existed prior to the bus being disabled or the level currently existing
on the bus will be reinforced.
To understand the operation of this input, assume that initially the input is at a low logic level. As the input
voltage is raised, TG 1 sinks current to attempt to maintain the low level. However, TG 1 consists of small geometry
transistors and appears resistive as current flows thus allowing the input voltage to rise toward the threshold
voltage of G1. When the threshold voltage is reached, G1 changes state causing G2 to change state. G2 then
attempts to maintain a high level on the input through TG 1 . A similar operation occurs when the input voltage
is decreased toward the threshold voltage of G 1 . G2 sources current through TG 1 until the threshold is reached.
This characteristic of the input stage has some implications for the input current levels. With the input held
at either Vccor GND, there is no voltage across TG 1 and negligible input current. However, as the input voltage
is raised from GND or lowered from VCC, the input current rises as the voltage across TG 1 increases. The input
current continues to rise until it reaches a maximum just as the threshold voltage of G 1 is reached. This maximum
corresponds to parameter 11M shown in the electrical characteristics table. Because G1 consists of small geometry
transistors, 11M has a value much lower than the output drive capability of a conventional 'HC output stage.
Also for this reason, the input configuration has negligible effect when the I/O port is used as an output.
This configuration provides for minimum power dissipation when the bus is inactive (all outputs on the bus
in the high-impedance state) and minimum susceptibility to noise on the bus during this time. The increase in
input current may go unnoticed as it only occurs during transitions on the bus. Care must be taken when measuring
input currents (e.g., at incoming inspection) to ensure that the input voltage is set to the correct value.
The use of these devices for interfacing to 8-, 16-, 24-bit-wide memory arrays with parity is illustrated in Figures 2,
3, and 4.
3-368
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC664, SN54HC665, SN74HC664, SN74HC665
OCTAL BUS TRANSCEIVERS WITH PARITY
TYPICAL APPLICATION DATA
'HC6641'HC665
G
RJW
DlR
DATA BUS
DOthru D7
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
ERROR
B8
API
APO
BPO
BPI
FIGURE 2. 8-BIT-WIDE MEMORY ARRAY WITH PARITY
'HC664/'HC665
CONTRO
L
RAM
{~~ G
~~f--
DIR
~
DATA BUS
DOthru D7
~
RJW
..
ERROR
A1
B1
A2
B2
A3
B3
A4
64
A5
B5
A6
B6
A7
B7
A8
B8
BPI
APO
BPO
API
[RtW]
.
II
en
w
o
:>w
~
c
en
o
2
o
:x::
r-
'HC6641'HC665
RAM
'-6
RtW
[RtWl
'----- DIR
~
DATA BUS
D8 thru D15
...,
C-
A1
B1
A2
B2
A3
83
A4
84
A5
B5
A6
B6
A7
B7
A8
B8
BPI
APO
BPO
API
....
....
,
~
~
~
r-
r
FIGURE 3. 16-BIT-WIDE MEMORY ARRAY WITH PARITY
-'!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-369
TYPES SN54HC664. SN54HC665. SN74HC664. SN74HC665
OCTAL BUS TRANSCEIVERS WITH PARITY
TYPICAL APPLICATION DATA
'HC664/'HC665
• CDNTRDL{
~
RAM
(R/W)
G
OIR
DATA 8US
oOthru 07
~
A1
81
A2
82
A3
83
A4
84
A5
85
A6
86
A7
87
A8
88
I - "- API
r
8PO
II
A~~
8Plq
H;
'HC664/'HC665
RAM
(R/WI
...... G
~
...... OIR
:I:
(')
S
o
oATA8US
CJ)
08 thru 015
or
C
m
<
nm
.f"
CJ)
A1
81
A2
82
A3
83
A4
84
A5
85
A6
86
A7
87
A8
88
r
I - -API
8PO
I
I~
a:
"D~
8PI~
'HC280
2k
PARTOF
'HC367
A
8
C
'HC664/'HC665
RAM
(R/W)
-G
"-
DATA 8US
016thru 023
-0
A1
81
...... F
A2
82
~G
A3
83
~H
A4
84
~I
A5
85
A6
86
A7
87
- r
~API
BPO
~
r--E
OIR
A8
L
EVEN
~
QD-
~
'ARTDF
L
000 ~ERROR
J
':l='
88
APO
8PI~
FIGURE 4. 24-BIT-WIDE MEMORY ARRAY WITH PARITY
NOTE: The 'HC280 eliminates ripple carry delays associated with Figures 2 and 3. However, in those two cases the delays are probably
too small to be of concern.
3-370
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3E
HIGH·SPEED
CMOS LOGIC
TYPES SN54HCT664, SN54HCT665, SN74HCT664, SN74HCT665
OCTAL BUS TRANSCEIVERS WITH PARITY'
02839. MARCH 1984
SN54HCT664. SN54HCT665 •.• JT PACKAGE
SN74HCT664. SN74HCT665 ••• JT OR NT PACKAGE
•
Inputs Are TTL-Voltage Compatible
•
Bus Transceivers with Inverting Outputs
('HCT664) or True Outputs ('HCT665)
•
Generates a Parity Bit for A Bus and B Bus
(TOP VIEW)
•
Easily Cascadable
•
Internal Active Pull-Ups and Pull-Downs
•
High-Current 3-5tate Outputs Can Drive up
to 1 5 L5TTL Loads
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
description
These octal bus transceivers are designed for
asynchronous, bidirectional communication
between data buses. The devices transmit data
from the A Bus to the B Bus or from the B Bus
to the A Bus, depending on the level at the
direction control input, DIR. The enable input, G,
can be used to disable the device so that the
buses are isolated. These devices will also
generate parity outputs, APO and BPO, which
reflect the number of high levels at the A Bus
and B Bus, respectively, taking into account the
parity inputs API and BPI.
The bidirectionalI/O ports feature active circuitry
on the input stage that, when the output shared
by that pin is disabled, will maintain the input in
the last state taken by the output. This state will
be maintained until changed by the activity on
the bus. The advantage of this arrangement is
that when all outputs on the bus are disabled,
the inputs will be prevented from floating,
resulting in minimum power dissipation and
minimum susceptibility to noise. This eliminates
any need for external pull-up or -pull-down
resistors. The parity inputs API and BPI have
similar circuitry. For further information, see the
Typical Application Data on the 'HC664, and
'HC665 data sheet.
DIR
Al
A2
A3
A4
A5
A6
A7
A8
8PI
8PO
GND
VCC
G
81
82
83
84
85
86
87
88
API
APO
II
SN54HCT664. SN54HCT665 ••. FH OR FK PACKAGE
SN74HCT664. SN74HCT665 ••. FH OR FN PACKAGE
(TOP VIEW)
en
w
432
(J
1
A3
82
83
84
NC
NC
A6
A7
A8
85
86
87
>
W
c
en
o
:E
(J
J:
12 131415161718
NC - No internal connection
The input threshold voltages on these devices are adjusted to be TTL compatible, allowing direct interface
to TTL levels on the bus or to memories with TTL output voltage levels.
The SN54HCT664 and SN54HCT665 are characterized for operation over the full military temperature
range of - 55°C to 125°C. The SN74HCT664 and SN74HCT665 are characterized for operation from
-40°C to 85°C.
Copyright © 1984. Texas Instruments Incorporated
TEXAS
-111
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-371
TYPES SN54HCT664, SN54HCT665, SN14HCT664, SN14HCT665
OCTAL BUS TRANSCEIVERS WITH PARITY
FUNCTION TABLE
CONTROL
NUMBER OF HIGH
NUMBER OF HIGH
INPUTS
G OIR
INPUTS ON
B BUS AND BPI
INPUTS ON
B BUS AND BPI
APO
X
0,2,4,6,8
Z
X
0,2,4,6,8
1,3,5,7,9
Z
H
L
L
L
H
H
X
X
X
X
1,3,5,7,9
X
OPERATION
OUTPUTS
BPO
H
L
Z
Z
Z
L
Z
'HCT664
'HCT665
B Data to
A Bus
B Data to A Bus
A Data to
B Bus
A Data to B Bus
Isolation
Isolation
logic symbols
'HCT665
'HCT664
G (23)
G (23)
OIR (1)
lEI
OIR (1)
A1 (2)
A2 (3)
:c
/Z12
0
A3 (4)
s:
0
A1 (2)
E>
A3 (4)
A4 (5) .
A4 (5)
C
A5 (6)
A5 (6)
<
A6 (7)
A6 (7)
A7 (8)
A7 (8)
(J)
m
n
m
(J)
A8 (9)
/Z18
A8 (9)
/Z18
2k
API (14)
V1
BPO (11)
2k
21
22
23
24
25
26
27
28
11
12
13
14
15
16
17
18
(10) BPI
V1
BPO (11)
V1
Pin numbers shown are for JT and NT packages.
3-372
E>
2k
API (14)
2k
11
12
13
14
15
16
17
18
-.....--L-~
r
I
I
I
I
I
~
.--+--~ ~-_--_.q
'HCT665
A1~(2~'_ _ _ _ _ _~~~~I~
(22' B1
I
+
A2~(3~,--_'H_C_T_66_5--+~~~
A3_(4~'_ _ _ _ _~+-~~,
A4~(5~'______-.~+-~~~
A5 ..,;(6~'_ _ _ _>-+-~+-~-+---o
A6 (7'
II
(21' B2
(20' B3
(1S' B4
7 INVERTING (NONINVERTING FOR 'HCT665'
(18' 85
CHANNELS IDENTICAL TO CHANNEL 1 ABOVE
(17' B6
(16' B5
(15' B6
A7~(S~'--~~~4-~~~'
AS(S'
(/)
W
()
:>w
API .;..;(1....;.4,-'-t-+-+--t-t-t-+-+--t---+-i
~-~ "","-...o..:.~-}O_ _ _ _ _-I :>-t-t-I-+-+-+-t-+---,(:...:.;13~'
;>O-......
APO
c
(/)
o
:E
()
~
BPO.;..;(1....;.1,-'+ - - - - - - - < . t - - - - - - - - Q {_ _.--....
b-_-..-w
c
en
o
~
ns
(J
J:
ns
ns
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
For typical application data and a description of the unique input structure, see the 'HC664 series data sheet.
TEXAS
-1./1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-375
II
J:
o
S
o
en
c
m
~
o
m
en
3-376
TYPES SN54HCB04, SN74HCB04
HEX 2·INPUT NAND DRIVERS
HIGH·SPEED
CMOS LOGIC
02804. MARCH 1984
SN54HC804 ••• J PACKAGE
SN74HC804 ••• J OR N PACKAGE
ITOPVIEW)
•
High·Current Outputs Can Drive up to
1 5 LSTTL Loads
•
Package Options Include Both Plastic
and Ceramic Chip Carriers in Addition to
Plastic and Ceramic DIPs
•
Dependable Texas Instruments Quality
_and Reliability
description
These devices contain six independent 2-input
NAND drivers. They perform the Boolean functions Y = A' B or Y = A+ B in positive logic.
The SN54HC804 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC804 is characterized for operation from -40°C to 85°C.
Vee
1A
18
1Y
2A
28
2Y
3A
38
3Y
68
6A
6Y
58
5A
5Y
48
4A
4Y
GND
SN54HC804 ..• FH OR FK PACKAGE
SN74HC804 .•• FH OR FN PACKAGE
II
ITOP VIEW)
()
~~~~~
FUNCTION TABLE leach-driver)
INPUTS
A
B
H
H
L
X
L
X
OUTPUT
2A
V
L
H
H
3A
38
en
w
o
>
w
C
en
:!
o
o
logic symbol
(1)
1A
(2)
18
2A
28
3A
38
4A
48
5A
58
6A
68
(4)
(5)
&[>
~.
(3)
.....
(6)
t-...
(9)
(7)
(8)
(12)
(13)
"""'"
(15)
(16)
(18)
(19)
"""'"
t.....
(11)
(14)
(17)
1Y
J:
2Y
3Y
4Y
5Y
6Y
Copyright © 1984 by Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-377
TYPES SN54HC804, SN14HC804
HEX 2-INPUT NAND DRIVERS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
FROM
(INPUT)
AorB
TO
(OUTPUT)
Y
Any
tt
vcc
MIN
2V
4.5 V
6V
2V
4.5 V
6V
TA - 25"C
TYP MAX
40
100
12
20
10
17
28
60
8
12
6
10
SN54HC804
MIN
MAX
150
30
26
90
18
15
Power dissipation capacitance per gate
II
o
3:
oen
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
tt
o
m
<
UNIT
ns
ns
40 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
.
:J:
o
SN74HC804
MIN
MAX
125
25
22
75
15
13
Any
VCC
2V
4.5 V
6V
2V
4.5 V
6V
TA" 25"C
MIN
TYP
60
20
16
45
17
13
MAX
185
37
32
210
42
36
SN54HC804
MIN
MAX
280
56
48
315
63
53
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
m
en
3-378
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SN74HC804
MAX
MIN
230
46
41
265
53
45
UNIT
ns
ns
TYPES SN54HC805, SN74HC805
HEX 2·INPUT NOR DRIVERS
HIGH·SPEED
CMOS LOGIC
D2804, MARCH 1984
SN54HC805 ... J PACKAGE
SN74HC805 ... J OR N PACKAGE
(TOP VIEW)
•
High-Current Outputs Can Drive up to 15
LSTTL Loads '
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
description
These devices contain six independent 2-input
NOR drivers. They perform the Boolean functions
y = A+ B or Y = ,A. B in positive logic.
68
6A
6Y
58
5A
5Y
48
4A
4Y
GND
0
The SN54HCS05 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCS05 is
characterized for operation from - 40°C to
S5°C.
Vee
1A
18
1Y
2A
28
2Y
3A
38
3Y
SN54HC805 ••• FH OR FK PACKAGE
SN74HC805 ..• FH OR FN PACKAGE
(TOP VIEW)
II
U
>-co«Uco
'-.-.-><0
FUNCTION TABLE (each driver)
INPUTS
A
B
Y
H
X
L
X
H
L
L
L
H
lB
2A
2B
(1)
(2)
(.)
:>W
C
en
0
1:;~~~~
logic symbol
lA
en
W
6A
6Y
58
5A
5Y
2A
28
2Y
3A
38
OUTPUT
:!
(!)
>1[>
(4)
(5)
(.)
1Y
J:
2V
(7)
3A
(8)
3B
(12)
4A
(13)
4B
(15)
5A
(16)
5B
4V
6A
6B
6V
3V
5V
(18)
(19)
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III. page 2-S.
Copyright © 1984, Texas Instruments Incorporated
4
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-379
SN54HC805. SN74HC805
HEX 2·INPUT NOR DRIVERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
FROM
TO
(INPUT)
(OUTPUT)
A or B
Any
tt
Cpd
Y
vCC
TA = 25°C
MIN
TYP MAX
SN54HC805
MIN
SN74HC805
MAX
MIN
MAX
2V
31
95
145
120
4.5 V
10
19
29
24
6V
8
16
25
20
2V
28
60
90
75
4.5 V
8
12
18
15
6V
6
10
15
13
Power dissipation capacitance per gate
UNIT
ns
ns
40 pF typ
switching characteristics over re~ommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
II
J:
o
3:
oen
cm
<
PARAMETER
FROM
(INPUT)
(OUTPUT)
tpd
A or B
Y
tt
TO
Any
VCC
TA = 25°C
MIN
TYP MAX
SN54HC805
MIN
MIN
MAX
2V
44
180
275
225
4.5 V
14
11
55
47
45
6V
36
31
265
2V
45
210
315
17
42
63
53
6V
13
36
53
45
o
m
(J)
-I!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
UNIT
ns
39
4.5 V
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
3-380
SN74HC805
MAX
ns
TYPES SN54HC808. SN74HC808
HEX 2·INPUT AND DRIVERS
HIGH·SPEED
CMOS LOGIC
02804. MARCH 1984
•
High-Current Outputs Can Drive up to
1 5 LSTTL Loads
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN54HC808 ... J PACKAGE
SN74HC808 .•. J OR N PACKAGE
(TOP VIEW)
•
\
Vee
lA
18
1Y
2A
28
2Y
3A
38
3Y
Dependable Texas Instruments Quality and
Reliability
description
These devices contain six independent 2-input
AND drivers. They perform the Boolean
functions Y = A·B or Y = A+B in positive
logic.
68
6A
6Y
58
5A
5Y
48
4A
4Y
GND
SN54HC808 ... FH OR FK PACKAGE
SN74HC808 ..• FH OR FN PACKAGE
The SN54HC808 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC808 is
characterized for operation from - 40°C to
85°C.
U
3
FUNCTION TABLE (each driver)
B
H
l
H
X
X
L
Y
H
L
en
w
2 1 20 19
6A
6Y
58
5A
5Y
2A
28
2Y
3A
38
OUTPUT
INPUTS
A
Ell
(TOP VIEW)
>- CD « >(1)
u CD
............
u
:>w
c
en
9 1011 1213
L
o
~
logic symbol
&[>
U
J:
(3) 1V
2A
28
3A
38
4A
48
5A
58
68
-1!1
Copyright © 1984 by Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265
3-381
TYPES SN54HC808, SN74HC808
HEX 2·INPUT AND DRIVERS
absolute maximum ratings, recommended operating conditions, and electrical characteristics
Se'e Table III, page 2-8.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
111
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
Y
Vcc
2V
4.5 V
6V
2V
4.5 V
6V
MIN
TA" 25°C
TYP MAX
50
100
10
20
8
17
28
60
8
12
6
10
SN54HC808
MIN
MAX
150
30
25
90
18
15
20 pF typ
Power dissipation capacitance per gate
NOTE " Fo, lo,d d,,"" "d volt". w.v""m,. '" P'" 1· 14.
J:
('")
s:
otJ)
C
m
<
n
m
tJ)
3-382
SN74HC808
MIN
MAX
125
25
21
75
15
13
-I.!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
UNIT
\
ns
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC832. SN74HC832
HEX 2·INPUT OR DRIVERS
02804, MARCH 1984
•
High-Current Outputs Can Drive up to
15 LSTTL Loads
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
SN54HC832 ... J PACKAGE
SN74HC832 ..• J OR N PACKAGE
(TOP VIEW)
Dependable Texas Instruments Quality and
reliability
description
These devices contain six independent 2-input
OR drivers. They perform the Boolean functions
Y = A + B or Y = Aoi3 in positive logic.
The SN54HC832 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC832 is
characterized for operation from - 40°C to
85°C.
Vee
1A
18
1Y
2A
28
2Y
3A
38
3Y
68
6A
6Y
58
5A
5Y
48
4A
4Y
GND
SN54HC832 ... FH OR FK PACKAGE
SN74HC832 ... FH OR FN PACKAGE
(TOP VIEW)
•
U
>-co«Uco
.-.-.-><0
FUNCTION TABLE (each driver)
INPUTS
2A
28
2Y
3A
38
OUTPUT
A
B
Y
H
X
H
X
H
H
L
L
L
en
W
6A
6Y
58
5A
5Y
U
>
W
C
en
0
~~~~~
logic symbol
2
(!)
;;'11>
(31
u
1y
J:
2A
28
3A
38
4A
48
5A
58
6A
68
(191
-1!1
INSTRUMENTS
Copyright © 1984 by Texas Instruments Incorporated
TEXAS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-383
TYPES SN54HC832, SN74HC832
HEX 2·INPUT OR DRIVERS
absolute maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
III
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
Y
vCC
2V
4.5 V
TA = 25°C
MIN
TYP
50
MAX
SN54HC832
MIN
MAX
SN74HC832
MIN
MAX
100
150
10
20
125
25
6V
2V
8
17
30
25
28
60
90
75
4.5 V
6V
8
6
12
10
18
15
15
13
Power dissipation capacitance per gate
NOTE " Fa< '"d
:t:
n
S
o
en
c
m
<
nm
en
3-384
-Ij}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
ns
21
20 pF typ
"",It ,"d volt", w'"""m,. '" p'g' 1-14.
UNIT
ns
HIGH-SPEED
CMOS LOGIC
TYPES SN54HC4002, SN74HC4002
DUAL 4-INPUT POSITIVE-NOR GATES
02684, DECEMBER 1982-REVISED MARCH 1984
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN64HC4002 •.. J PACKAGE
SN74HC4002 ... J OR N PACKAGE
(TOP VIEW)
Vee
1Y
2Y
20
2e
description
2B
These devices contain two independent 4-input
positive NOR gates. They perform the Boolean
functions:
Y = "="A-+--=B:--+'"""C=--+--=D or Y = A • B • C • D
in positive logic.
The SN54HC4002 is characterized for operation
over the fuff military temperature range of
- 55 DC to 125 DC. The SN74HC4002 is
characterized for operation from - 40 DC to
85°C.
2A
""'L_ _
~Ne
SN64HC4002 ... FH OR FK PACKAGE
SN74HC4002 ... FH OR FN PACKAGE
(TOP VIEW)
U
~ ~ ~ ~~
FUNCTION TABLE
INPUTS
A
B
C
H
X
X
X
H
X
X
X
H
X
X
X
L
L
L
en
w
OUTPUT
0
X
X
Y
X
H
L
L
L
H
(,)
L
L
>
W
c
UOUU«
ZZZZN
t!)
NC-No internal connection
en
o
~
logic
(,)
~ymbol
1A
18
J:
(2)
;;'1
(3)
1C
10
2A
28
2C
20
(12)
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
-1!1
INSTRUMENTS
TEXAS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
Copyright ~1982 by Texas Instruments Incorporated
3-385
TYPES SN54HC4002, SN74HC4002
DUAL 4·INPUT POSITIVE·NOR GATES
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
TO
(INPUT)
(OUTPUT)
A thru 0
Y
Y
TA = 25°C
MIN
TYP MAX
vCC
SN54HC4002
MIN
SN74HC4002
MIN
MAX
2V
44
110
165
140
4.5 V
12
22
33
28
6V
11
19
28
24
2V
38
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance per gate
No load. T A = 25°C
NOTE 1: For load circuit and voltage waveforms. see page 1- 14.
J:
n
o
en
c
m
:5
s:
n
m
en
3-386
MAX
TEXAS
INSfRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
25 pF typ
UNIT
ns
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC4020, SN74HC4020
ASYNCHRONOUS 14·BIT BINARY COUNTERS
02684. DECEM8ER 1982-REVISED MARCH 1984
•
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN54HC4020 •.• J PACKAGE
SN74HC4020 ... J OR N PACKAGE
(TOP VIEW)
Dependable Texas Instruments Quality and
Reliability
d~scription
These devices are 14·stage binary ripple-carry
counters that advance on the negative-going
edge of the clock pulse. The counters are reset
to zero (all outputs low) independently of the
clock when CLR goes high.
OL
OM
VCC
OK
ON
OF
OE
OJ
OH
O(
OG
ClR
ClK
OD
GND
OA
SN54HC4020 ... FH OR FK PACKAGE
SN74HC4020 ... FH OR FN PACKAGE
The SN54HC4020 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC4020 is
characterized for operation from - 40°C to
85°C.
(TOP VIEW)
:2...JutL~
3 2 1 2019
OJ
OH
NC
O(
logic symbol
RCTR14
OA
ClR
(11)
ClK (10)
II
ddz>d
en
w
(.)
>
w
ClA
00
9 1011 12 13
c
en
o
OE
OF
OG
CT=O
J]'+
°H
CT
NC-No internal connection
2
01
(.)
OJ
OK
Ol
OM
ON
J:
Pin numbers shown are for J and N packages.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-387
TYPES SN54HC4020, SN74HC4020
ASYNCHRONOUS 14·BIT BINARY COUNTERS
logic diagram (positive logic)
•
::t:
o
Pin numbers shown are for J and N packages.
3:
oen
cm
<
om
en
3-388
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC4020, SN74HC4020
ASYNCHRONOUS 14·BIT BINARY COUNTERS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
vcc
TA = 25°C
MAX
MIN
6V
0
0
0
90
18
15
70
14
12
2V
Clock frequency
fclock
tw
4.3
90
12
18
6V
10
15
13
2V
4.5 V
Setup time, ClR inactive before ClK!
tsu
3.7
60
6V
ClR high
MAX
0
0
0
135
2V
2V
4.5 V
Pulse duration
MIN
4.5 V
6V
ClK high
SN74HC4020
MAX
0
0
0
115
23
20
90
18
25
75
15
4.5 V
or low
5.5
28
SN54HC4020
MIN
33
19
22
27
23
105
21
18
22
UNIT
MHz
25
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
f max
TA = 25°C
MIN
TYP MAX
5.5
4.5 V
28
10
45
6V
33
53
2V
tpd
tpHl
tt
Cpd
ClK
ClR
QA
Any
Any
SN54HC4020
MIN
MAX
SN74HC4020
MIN
3.7
19
4.3
22
22
25
MAX
W
UNIT
>
w
C
CJ)
150
4.5 V
16
30
45
38
6V
12
26
38
32
2V
63
140
210
175
4.5 V
17
28
42
35
6V
13
24
36
30
2V
28
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance
CJ)
U
MHz
62
225
II
o
190
ns
2
u
::I:
ns
ns
88 pF typ
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS •
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS. TeXAS 75265
3-389
::J:
o
s:
o
c
m
<
en
om
en
3-390
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC4024, SN74HC4024
ASYNCHRONOUS 7·BIT BINARY COUNTERS
02804, MARCH 1984
SN54HC4024 •.. J PACKAGE
SN74HC4024 ... J OR N PACKAGE
.. Package Options Include Both Plastic
and Ceramic Chip Carriers in Addition to
Plastic and Ceramic DIPs
"
(TOP VIEW)
ClK
ClR
OG
OF
OE
00
GNO
Dependable Texas Instruments Quality
and Reliability
description
The 'HC4024 is an asynchronous 7·stage
binary counter designed with an input pulseshaping circuit. The outputs of all stages are
available externally. A high clear signal
asynchronously clears the counter and resets
all outputs low. The count is advanced on the
high-to-Iow transition of the clock pulse.
Applications include time-delay circuits,
counter controls, and frequency-dividing
circuits.
VCC
NC
OA
Os
NC
Oc
NC
SN54HC4024 ... FH OR FK PACKAGE
SN74HC4024 ... FH OR FN PACKAGE
(TOP VIEW)
5:Ju~u
uuz>z
II
OA
NC
Os
NC
NC
The SN54HC4024 is characterized for
operation over the full military temperature
range of - 55°C to 125°C. The SN74HC4024
is characterized for operation from - 40°C to
85°C.
00 U U
en
w
u
:>w
U
c
en
dZZZd
logic symbol
(!)
RCTR7
NC-No internal connection.
o
~
U
::I:
ClR (2)
ClK . .:,(. . ;,;1):.......L.~ +
CT
Pin numbers shown are for J and N packages.
Copyright © 1984 by Texas Instruments Incorporated
-II}
" TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3-391
TYPES SN54HC4024, SN74HC4024
ASYNCHRONOUS 7·BIT BINARY COUNTERS
logic diagram (positive logic)
II.
Pin numbers shown are for J and N packages.
typical clear and count sequences
CLR-----,
o
2
3
4
5
6
7
8
126
127
~8 r1 r1
~~ 4.J LJ
16
32
64
~
J-,
r
l-J: LJ
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
~~~~~
L~~~4-rii-.....&-....!----~------,~ ~ ~ ~ ~ ~
--!---+------~~~~ ~
_ - - + - -_ _ _ _
-----Ir~ ~ ~ ~
_~-----------'r~~ ~
------~~--------------------------------~~ ~
~------------------------------------------~~: ~
COUNT
3-392
TEXAS
-I/}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
CLEAR
31
TYPES SN54HC4024, SN74HC4024
ASYNCHRONOUS 7·BIT BINARY COUNTERS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
2V
fclock
Clock frequency
4.5 V
6V
ClK high or low
tw
2V
4.5 V
TA - 25°C
SN54HC4024
SN74HC4024
MIN
MAX
MIN
MAX
MIN
MAX
0
0
5.5
28
0
3.7
19
0
0
0
33
22
0
4.3
22
25
0
0
135
27
90
18
Pulse
6V
15
23
20
2V
80
120
100
4.5 V
16
24
20
Setup time. ClR low
be fate ClK ~
tsu
MHz
115
23
duration
ClR high
UNIT
6V
14
20
17
2V
80
100
4.5 V
6V
16
14
120
24
20
ns
20
17
II
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
Vee
4.5 V
5.5
28
10
50
6V
33
60
2V
tpd
tpHl
tt
ClK
ClR
QA
Any
= 25°C
TYP
2V
f max
TA
MIN
MAX
SN54HC4024
MIN
MAX
SN74HC4024
MIN
MAX
w
UNIT
C
MHz
o
en
4.3
3.7
19
22
22
26
:!
(J
56
120
180
150
4.5 V
6V
16
12
24
ns
20
36
31
ns
2V
61
130
195
30
26
165
4.5 V
17
26
39
33
6V
13
22
28
2V
28
75
33
110
95
4.5 V
8
6
15
22
19
13
19
16
6V
No load. TA = 25°C
Power dissipation capacitance
·1
en
w
(J
:;:
J:
ns
40 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-393
lEI
::J:
n
~
o
en
cm
<
(;
m
en
3-394
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC4040, SN74HC4040
ASYNCHRONOUS 12·BIT BINARY COUNTERS
02684. DECEM8ER 1982-REVISED MARCH 1984
•
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN54HC4040 ... J PACKAGE
SN74HC4040 •.. J OR N PACKAGE
(TOP VIEW)
QL
QF
QE
QG
QD
QC
Qs
GND
Dependable Texas Instruments Quality and
Reliability
description
This device is an asynchronous 12-state binary
counter with the outputs of all stages available
externally. A high level at ClR asynchronously
clears the counter and resets all outputs low. The
count is advanced on a high-to-Iow transition at
ClK. Applications include time delay circuits,
counter controls, and frequency-dividing circuits.
SN54HC4040 .•. FH OR FK PACKAGE
SN74HC4040 •.. FH OR FN PACKAGE
(TOP VIEW)
The SN54HC4040 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC4040 is
characterized for operation from -40°C to
85°C.
U
u....JU U
QE
QG
NC
QD
RCTR12
ClR
II
~
aaz>a
logic symbol
(111
VCC
QK
QJ
QH
Q(
ClR
ClK
QA
o
w
4
o
>
w
Qc
C
OA
Os
Oc
CT=O
o
o
00
ClK (10)
..D"+
OE
OF
CT
:E
o
NC - No internal connection
J:
°G
OH
01
OJ
OK
°l
Pin numbers shown are for J and N packages.
Copyright ©1982 by Texas Instruments Incorporated
-1.!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-395
TYPES SN54HC4040, SN74HC4040
ASYNCHRONOUS 12·BIT BINARY COUNTERS
logic diagram (positive logic)
III
::t
n
S
o
tn
C
m
Pin numbers shown are for J and N packages.
n
maximum ratings, recommended operating conditions, and electrical characteristics
<
m
See Table IV, page 2-10.
tn
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock Clock frequency
ClK high or low
tw
Pulse duration
ClR high
ts~
3-396
Setup time. ClR inactive before ClK ~
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
5.5
0
28
0
33
0
90
18
15
70
14
12
60
12
10
SN54HC4040
MAX
MIN
0
3.7
0
19
0
22
135
27
23
105
21
18
90
18
15
-1.!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SN74HC4040
UNIT
MIN
MAX
4.3
0
22 MHz
0
25
0
115
ns
23
20
90
18
ns
15
75
15
ns
13
TYPES SN54HC4040, SN74HC4040
ASYNCHRONOUS 12·BI1 BINARY COUNTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
tPHl
tt
ClK
ClR
QA
Any
Any
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
5.5
10
45
28
53
33
62 150
16
30
12
26
63 140
17
28
13
24
28
75
15
8
6
30
SN54HC4040
MIN
MAX
3.7
19
22
225
~5
38
210
42
36
110
22
19
SN74HC4040
UNIT
MIN
MAX
4.3
22
MHz
25
19~
38
32
175
35
30
95
19
16
ns
ns
ns
r----c~p-d----.-----~P~o-w-e-r~di~ss~ip-a~tio-n-c-a-p-ac7it-an-c-e------r---~N~o-l~oa-d~.~T~A--~2~5~oC~---r----8~8~p~F~t-y-p---'1
IIiIII
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
U)
W
(.)
5=
w
c
U)
o
:?!
(.)
J:
TEXAS
"'J1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-397
l:
n
S
o
tn
C
m
<
n
m
tn
3-398
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC4060, SN74HC4060
ASYNCHRONOUS 14·STAGE BINARY COUNTERS
AND OSCILLATORS
02684. DECEMBER 1982-REVISED MARCH 1984
SN54HC4060 •.. J PACKAGE
SN74HC4060 .•. J OR N PACKAGE
•
Allows Design of Either RC or Crystal
Oscillator Circuits
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
(TOP VIEW)
•
OL
Dependable Texas Instruments Quality and
Reliability
description
The 'HC4060 consists of an oscillator section
and 14 ripple-carry binary counter stages. The
oscillator configuration allows design of either
RC or crystal oscillator circuits. A high-to-Iow
transition on the clock input increments the
counter. A high level at CLR disables the
oscillator (CKO goes high and CKO goes low) and
resets the counter to zero (all Q outputs low).
VCC
OM
OJ
ON
OH
OF
01
°E
CLR
°G
CKI
00
CKO
GNo
CKO
SN54HC4060 •.. FH OR FK PACKAGE
SN74HC4060 ... FH OR FN PACKAGE
(TOP VIEW)
:E...JU
~.,
Ooz>O
The SN54HC4060 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC4060 is
characterized for operation from - 40°C to
85°C.
OH
(/)
01
NC
CLR
CKI
logic symbol
o0 0
z
Cl
RCTR14
U
Z
W
(,)
:>w
c
(/)
o
010
uu
~
~
~
NC-No internal connection
(,)
J:
CLR (...
1....
2).---t
CKI (11)
Pin numbers shown are for J and N packages.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-399
TYPES SN54HC4060, SN74HC4060
ASYNCHRONOUS 14·STAGE BINARY COUNTERS
AND OSCILLATORS
logic diagram (positive logic)
__
CK,1111
'--___.:.;.I~;:;.:.::~::
_ _ Pin numbers shown are for J and N packages.
J:
o
maximum ratings, recommended operating conditions, and electrical characteristics
3:
See Table IV, page 2-10.
o
en
cm
<
(;
m
en
3-400
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC4060, SN74HC4060
ASYNCHRONOUS 14·STAGE BINARY COUNTERS
AND OSCILLATORS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
VCC
Clock frequency
fclock
CKI high
or low
Pulse duration
tw
CLR high
Setup time. CLR inactive before CKI .\.
tsu
SN54HC4060
TA = 25°C
MIN
MAX
MIN
5.5
0
2V
0
4.5 V
0
28
0
6V
33
0
135
MAX
3.7
SN74HC4060
MIN
0
MAX
4.3
19
0
22
22
0
25
2V
0
90
4.5 V
18
27
23
6V
15
23
20
UNIT
MHz
115
2V
90
135
115
4.5 V
18
27
23
6V
15
23
20
200
2V
160
240
4.5 V
32
48
40
6V
27
41
34
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherWise.
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
f max
tpd
tpHL
tt
CKI
CLR
°D
Any 0
Any
TA = 25°C
MIN
TYP MAX
10
5.5
SN54HC4060
MIN
MAX
SN74HC4060
MIN
MAX
4.5 V
28
45
19
22
6V
33
53
22
25
2V
240
490
735
615
4.5 V
58
98
147
123
6V
42
105
66
83
140
125
2V
210
175
4.5 V
18
28
42
35
6V
14
24
36
30
95
2V
28
75
110
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance
UNIT
4.3
3.7
en
w
MHz
(.)
ns
C
>
W
ns
ns
en
2
(.)
o
:::t
88 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS
~
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS. TeXAS 75265
3-401
J:
C')
s:
otJ)
C
m
S
C')
m
tJ)
3-402
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC4061, SN74HC4061
ASYNCHRONOUS 14·STAGE BINARY COUNTERS
AND OSCILLATORS
02804, MARCH 1984
•
Allows Design of Either RC or Crystal
Oscillator Circuits
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
SN54HC4061 ... J PACKAGE
SN74HC4061 ... J OR N PACKAGE
(TOP VIEW)
OL
Dependable Texas Instruments Quality and
Reliability
description
The 'HC4061 consists of an oscillator section
and 14 ripple-carry binary counter stages. The
oscillator configuration allows design of either
RC or crystal oscillator circuits. A high-to-Iow
transition on the clock input increments the
counter. A high level at CLR resets the counter
to zero (all Q outputs low) but has no effect on
the oscillator.
VCC
OM
OJ
ON
OH
OF
01
OE
CLR
OG
CKI
00
CKO
GNO
CKO
SN54HC4061 .•. FH OR FK PACKAGE
SN74HC4061 ... FH OR FN PACKAGE
(TOP VIEW)
::E
...J U
~
•
...,
Ooz>O
The SN 54HC4061 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC4061 is
characterized for operation from - 40°C to
85°C.
OH
en
w
01
NC
CJ
s:w
CLR
CKI
logic symbol
aZ
oa (!)
RCTR14
U
Z
c
010
uu
~
en
o
~
NC-No internal connection
:2
CJ
J:
1.D"+
CT
CLR (12)
CKI (11)
CT=O
(9) CKO
Z1
Pin numbers shown are for J and N packages.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright © 1984, Texas Instruments Incorporated
3-403
TYPES SN54HC4061, SN74HC4061
ASYNCHRONOUS 14·STAGE BINARY COUNTERS
AND OSCILLATORS
logic diagram (positive logic)
CKI 1111
_
191 CKO
110l
CKO
Pin numbers shown are for J and N packages.
_
J:
o
maximum ratings, recommended operating conditions, and electrical characteristics
s:o
See Table IV, page 2-10.
en
c
m
<
o
m
en
3-404
TEXAS
-It}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
31
TYPES SN54HC4061, SN74HC4061
ASYNCHRONOUS 14-STAGE BINARY COUNTERS
AND OSCILLATORS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
Clock frequency
fclock
CKI high
or low
Pulse duration
tw
CLR high
Setup time. CLR inactive before CKI ~
tsu
TA = 25°C
MAX
MIN
SN54HC4061
MIN
MAX
SN74HC4061
MAX
MIN
2V
4.5 V
5.5
3.7
19
4.3
28
6V
33
22
25
22
2V
4.5 V
90
18
135
27
115
23
6V
15
23
2V
135
4.5 V
90
18
20
115
27
23
6V
15
23
20
2V
4.5 V
6V
160
240
48
41
200
40
32
27
UNIT
MHz
ns
ns
ns
34
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
f max
tpd
tpHL
tt
CKI
CLR
QD
Any Q
Any
TA = 25°C
MIN
TYP MAX
SN54HC4061
MIN
MAX
3.7
SN74HC4061
MIN
MAX
5.5
10
4.5 V
28
45
19
22
6V
33
22
25
2V
53
240
490
735
615
4.5 V
6V
58
42
98
83
147
125
123
105
2V
66
18
140
28
210
42
175
4.5 V
6V
2V
14
24
75
36
110
30
28
4.5 V
6V
8
6
15
13
22
19
19
16
Power dissipation capacitance
UNIT
4.3
MHz
35
ns
II
en
w
(J
:>
w
C
en
ns
o
~
(J
95
ns
::J:
88 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
14
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-405
::I:
(")
s
o
en
c
<
m
(")
m
en
3-406
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC4075, SN74HC4075
TRIPLE 3·INPUT OR GATES
02684. DECEM8ER 1982-REVISED MARCH 1984
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC4075 ... J PACKAGE
SN74HC4076 ... J OR N PACKAGE
(TOP VIEW)
lA
18
2A
28
2C
2Y
GND
description
These devices contain three independent
3-input OR gates and' perform the Boolean
functions Y = A + B + C or Y = A • B • C in
positive logic.
(1)
(2)
2A
NC
28
NC
2C
1C
(B)
2:1
(9)
lC
al~~~g
logic symbol
18
1Y
SN54HC4075 •.. FH OR FK PACKAGE
SN74HC4075 ... FH OR FN PACKAGE
(TOP VIEW)
The SN54HC4075 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC4075 is
characterized for operation from - 40°C to
85°C.
1A
VCC
3C
38
3A
3Y
1Y
II
38
NC
3A
NC
3Y
en
w
CJ
>
w
.>OUU>
N
2A
Z
Z
po
po
c
Cl
28
NC-No internal connection
en
o
:E
2C
FUNCTION TABLE
3A
38
A
3C
H
X
X
L
Pin numbers shown are for J and N packages.
INPUTS
B
C
X
X
H
X
X
H
L
L
OUTPUT
CJ
Y
H
H
H
L
:I:
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
Vcc
tpd
A. 8. or C
Y
2V
4.5 V
6V
Y
2V
4.5 V
6V
tt
TA = 25°C
TYP MAX
MIN
38
100
11
20
17
9
38
8
6
Power dissipation capacitance per gate
SN64HC4075
MAX
MIN
150
30
25
SN74HC4075
MIN
MAX
125
25
21
110
22
19
95
19
16
75
15
13
UNIT
ns
ns
No load. TA = 25°C
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-407
II
::I:
o
S
o
en
c
m
S
o
en
m
3-408
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC4078A. SN74HC4078A
8·INPUT OR/NOR GATE
02804. MARCH 1984
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC4078A •.. J PACKAGE
SN74HC4078A ••. J OR N PACKAGE
(TOP VIEW)
y
A
description
o
NC
These devices contain a single 8-input OR/NOR
gate and perform the following Boolean
functions in positive logic:
GND _____rSN54HC4078A ... FH OR FK PACKAGE
SN74HC4078A . : . FH OR FN PAKCAGE
(TOP VIEW)
W=A+B+C+D+E+F+G+H
or
'A. B • C • 0 • E • F • G • H
W =
u
«>-~~~
and
Y=A+B+C+D+E+F+G+H
II
H
NC
or
NC
C
Y=A·B·C·D·E·F·G·H
The SN54HC4078A is characterized for
operation over the full military temperature range
of - 55°C to 125°C. The SN74HC4078A is
characterized for operation from - 40°C to
85°C.
en
w
G
NC
NC
o
o
F
:>w
uouuw
zzzz
(!)
C
en
o
NC-No internal connection
~
FUNCTION TABLE
INPUTS A
o
::c
OUTPUTS
THRU H
One or more inputs H
W
L
All inputs L
H
V
H
L
logic symbol
;>1
(1)
V
G
H (12)
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
Copyright © 1984 by Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-409
TYPES SN54HC4078A, SN74HC4078A
8·INPUT OR/NOR GATE
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A thru H
VI'?
tt
viv
vCC
2V
4.5 v
6V
2V
4.5 v
6V
TA = 25°C
MIN TVP MAX
40
130
12
26
10
22
38
75
15
8
13
6
SN54HC4078A
MIN
MAX
195
39
33
110
22
19
SN74HC4078A
MIN
MAX
165
33
28
95
19
16
UNIT
ns
ns
Power dissipation capacitance per gate
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
II
J:
o
3:
o
en
c
m
<
(=;
m
en
3-410
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
31
TYPES SN54HC4724, SN74HC4724
8·BIT ADDRESSABLE LATCHES
HIGH·SPEED
CMOS LOGIC
02684. DECEM8ER 1982-REVISED MARCH 1984
SN54HC4724 ... J PACKAGE
SN74HC4724 ... J OR N PACKAGE
(TOP VIEW)
•
8-Bit Parallel-Out Storage Register Performs
Serial-to-Parallel Conversion with Storage
•
Asynchronous Parallel Clear
so
•
Active-High Decoder
•
Enable Input Simplifies Expansion
•
Expandable for N-Bit Applications
S1
S2
00
01
02
03
•
Four Distinct Functional Modes
•
Package Options Include Both Plastic and
Ceramic. Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
VCC
CLR
G
D
07
06
05
04
GND
SN54HC4724 ... FH OR FK PACKAGE
SN74HC4724 ... FH OR FN PACKAGE
(TOP VIEW)
Ua:
...-oUU-l
U)U)Z>U
description
These 8-bit addressable latches are designed for
general purpose storage applications in digital
systems. Specific uses include working
registers, serial-holding registers, and active-high
decoders or demultiplexers. They are
multifunctional devices capable of storing singleline data in eight addressable latches, and being
a 1-of-8 decoder or demultiplexer with activehigh outputs.
II
G
S2
00
NC
D
NC
01
02
07
06
en
W
(.J
=>
W
C
(\')OU~L!l
en
OzzOO
(!)
Four distinct modes of operation are selectable
by controlling the clear (ClR) and enable (3)
inputs as enumerated in the function table. In the
addressable-latch mode, data at the data-in
terminal is written into the addressed latch. The
addressed latch will follow the data input with
all unaddressed latches remaining in their
previous states. In the memory mode, all latches
remain in their previous states and are
unaffected by the data or address inputs. To
eliminate the possibility of entering erroneous
data in the latches, enable IT should be held high
(inactive) while the address lines are changing.
In the 1-of-8 decoding or demultiplexing mode,
the addressed output will follow the level of the
D input with all other outputs low. In the clear
mode, all outputs are low and unaffected by the
address and data inputs.
0
2
NC-No internal connection
(.J
::t:
FUNCTION TABLE
INPUTS
CLR
G
OUTPUT OF
EACH
ADDRESSED
OTHER
OUTPUT
FUNCTION
LATCH
Addressable Latch
L
L
0
aiO
L
H
H
L
H
aiO
0
L
aiO
L
H
The SN54HC4724 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC4724 is
characterized for operation from - 40°C to
85°C.
L
Memory
8-Line Demultiplexer
Clear
LATCH SELECTION TABLE
SELECT INPUTS
52
S1
LATCH
SO
ADDRESSED
0
1
L
L
L
L
L
H
L
H
L
2
L
H
H
H
L
L
3
4
H
L
H
H
H
H
H
L
H
5
6
7
\
Copyright ©1982 by Texas Instruments Incorporated
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-411
TYPES SN54HC4724, SN74HC4724
8·BIT ADDRESSABLE LATCHES
logic diagram (positive logic)
logic symbol
II
::t
(")
3:
otJ)
C
m
<
om
Pin numbers shown are for J and N packages.
tJ)
logic symbol and logic diagram, each internal latch (positive logic)
c
D------i
D=t!]-D
~
~1
R
1R
Q
Q
38
3·412
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC4724, SN74HC4724
8-BIT ADDRESSABLE LATCHES
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
vCC
2V
CLR high
Pulse duration
tw
Glow
Setup time. data or address before
tsu
Hold time. data or address after
th
Gt
Gf
TA = 25°C
MIN
MAX
80
SN54HC4724
MIN
MAX
120
SN74HC4724
MIN
-4.5 V
16
24
6V
14
20
20
17
2V
80
16
120
100
4.5 V
24
20
6V
2V
14
75
20
115
17
95
4.5 V
15
23
19
6V
13
20
16
2V
5
5
5
4.5 V
5
5
5
5
5
5
6V
MAX
UNIT
100
ns
ns
II
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
•
PARAMETER
tpHL
tpd
tpd
tpd
tt
FROM
(INPUT)
CLR
Data
Address
G
TO
(OUTPUT)
VCC
Any Q
2V
4.5 V
6V
60
18
14
26
38
32
2V
4.5 V
56
130
195
165
-
17
26
39
33
ns
6V
13
22
33
28
2V
74
21
200
40
300
60
250
4.5 V
6V
17
34
51
50
43
Any Q
Any Q
Any Q
Any
TA = 25°C
MIN
TYP MAX
SN54HC4724
MIN
150
30
MAX
225
45
SN74HC4724
MIN
MAX
190
38
UNIT
c
o
2
()
:I:
ns
2V
66
170
255
215
20
34
51
43
ns
6V
16
29
43
2V
4.5 V
28
8
75
15
110
22
37
95
19
ns
6V
6
13
19
16
No load. TA = 25°C
()
:>w
en
ns
4.5 V
Power dissipation capacitance per latch
en
w
33 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3-413
II
::I
(1
s
oen
c
m
<
n
m
en
3-414
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC7266, SN74HC7266
QUADRUPLE 2·INPUT EXCLUSIVE·NOR GATES
02804. MARCH 1984
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality
and Reliability
SN54HC7266 .•• J PACKAGE
SN74HC7266 •.• J OR N PACKAGE
(TOP VIEW)
1A
description
These devices are composed of four independent
2-input exclusive-NOR gates. 'HC7266 devices
are totem-pole-output versions of the 'HC266.
They perform the Boolean functions
y = A(±) B = AS + AB in positive logic.
18
Vec
48
1Y
4A
2Y
4Y
2A
3Y
28
38
GND
3A
SN54HC7266 •.. FH OR FK PACKAGE
SN74HC7266 ... FH OR FN PACKAGE
(TOP VIEW)
The SN54HC7266 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC7266 is
characterized for operation from - 40°C to
85°C.
~ ~ Zu >~ qen
..
logic symbol
1A
1Y
4A
NC
2Y
NC
4Y
NC
2A
3Y
•
en
w
NC
C,.)
1Y
18
en c u
2A
28
3A
N
2Y
Z
Z
<{
M
:>w
en
M
l:J
c
NC-No internal connection
en
o
3Y
38
4A
FUNCTION TABLE
4Y
48
INPUTS
Pin numbers shown are for J and N packages.
B
L
L
H
L
H
,C,.)
Y
H
L
L
H
L
H
H
~
OUTPUT
A
J:
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or 8
Y
tt
Y
SN54HC7266
MAX
SN74HC7266
VCC
TA = 25°C
MIN
TYP MAX
2V
4.5 V
40
12
100
20
150
30
125
25
6V
10
17
25
21
2V
28
75
8
6
15
110
22
95
4.5 V
13
19
16
6V
Power dissipation capacitance per gate
MIN
No load. TA
=
25°C
MIN
MAX
19
UNIT
ns
ns
35 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1- 14.
Copyright
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
© 1984. Texas Instruments Incorporated
3-415
J:
(')
s
oen
cm
<
(')
m
en
3-416
GENERAL INFORMATION
I
'_1
,--_RA_T_I_N_G_S_A_N_D_C_H_A_R_A_C_T_E_R_IS_T_IC_S_.__________
HCMOS DEVICES
I
HCMOS DEVICES - ADVANCE INFORMATION
I
HCMOS DEVICES -
PRODUCT PREVIEWS
II
II
EXPLANATION· OF LOGIC SYMBOLS
DESIGNERS'.·INFORMATION
MECHANICAL·DATA
4-1
ADVANCE INFORMATION
II»
c
<
»
2
(")
m
2
"T'I
o:a
S
»
:j
o
2
4-2
This section contains information on new products in the sampling
or preproduction stage. Characteristic data and other specifications
are subject to change without notice.
TYPES SN54HC73, SN74HC73
DUAL J·K FLlP·FLOPS WITH CLEAR
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
•
Package Options Include Both Plastic and
Ceramic Chip Carriers In Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC73 .•. J PACKAGE
SN74HC73 •.• J OR N PACKAGE
(TOP VIEW)
1ClK
1ClA
1K
VCC
2ClK
2ClA
2J
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the Clear input resets the outputs regardless of
the other inputs. When Clear is inactive (high)'
data at the J and K inputs meeting the setup time
requirements are transferred to the outputs on
the negative-going edge of the clock pulse.
Following the hold time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. These flip-flops can
perform as toggle flip-flops by tying J and K high.
1J
1Q
10
GND
2K
20
20
For functionally and electrically identical
parts in chip carrier packages. see
SN54HC107 and SN74HC107.
The SN54HC73 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN74HC73 is characterized for operation from -40°C to 85°C.
logic symbol
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
Q
lCLK
lK
l
H
1CLR
00
00
2J
2CLK
ClK
X
J
X
K
X
Q
L
H
H
L
L
L
H
L
H
H
!
l
l
!
H
H
H
X
H
X
ClR
l
H
H
H
L
2
0
i=
~
:E
a:
2K
TOGGLE
00
II
lJ
OUTPUTS
2CLR
00
0
Pin numbers shown are for J and N packages.
LL
~
logic diagram, each flip-flop (positive logic)
W
J-_Z--
0
2
Q
K-""'''---
~
>
C
~
CLK~:
crR--------~ ~~--------------e_----------------------------------~
Copyright © 1982. Texas Instruments Incorporated
ADVANCE INFORMATION
This document contains Information
on a new product. Specifications are
subject to change without notice.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-3
TYPES SN54HC73. SN74HC73
DUAL J·K FLOp·FLOPS WITH CLEAR
absolute maximum ratings, recommended operating conditions, and electrical characteristics
See Table II, page 2-6.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
vCC
fclock
Clock frequency
tw
Pulse duration
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
. 2 V
CLK high or low
CLR low
II
~
tsu
Setup time. CLR inactive
or data before CLK~
th
Hold time. data after
<
CLK~
PARAMETER
FROM
IINPUT}
TO
(OUTPUT)
f max
l>
2
n
tPHL
CLR
Q
2"T1
tpLH
CLR
Q
m
o
:g
~.
tpd
CLK
Q
tpd
CLK
Q
l>
:::j
o
TA = 25°C
MAX
5
25
29
SN54HC73
MIN
MAX
SN74HC73
MIN
MAX
UNIT
MHz
ns
100
20
17
100
20
17
0
0
0
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted),CL = 50 pF (see Note 1)
,
l>
C
4.5 V
6V
2V
4.5 V
6V
MIN
0
0
0
100
20
17
2
tt
Any
VCC
TA = 25°C
MIN ·TYP MAX
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
5
25
29
SN54HC73
MIN
MAX
SN74HC73
MIN
MAX
9
50
60
42
16
14
MHz
ns
35
11
6V
2V
4.5 V
6V
2V
4.5 V
ns
9
40
13
11
42
16
14
6V
2V
4.5 V
6V
ns
ns
38
8
6
Power dissipation capacitance per flip-flop
UNIT
ns
30 pF typ
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
381
4-4
TEXAS . .
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC78. SN74HC78
DUAL J·K NEGATIVE·EDGE·TRIGGERED FLlp·FLOPS
WITH PRESET. COMMON CLEAR. AND COMMON CLOCK
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
•
SN54HC78 ... J PACKAGE
SN74HC78 ... J OR N PACKAGE
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
(TOP VIEW)
CLR
Dependable Texas Instruments Quality and
Reliability
1PRE
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the Preset or Clear inputs sets· or resets the
outputs regardless of the levels of the other
inputs. When the Preset and Clear are inactive
(high), data at the J and K inputs meeting the
setup time requirements are transferred to the
outputs on the negative-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold time interval,
data at the J and K inputs may be changed
without affecting the levels at the outputs.
These versatile flip-flops can perform as toggle
flip-flops by tying J and K high.
logic symbol
1 U14
1K
2
13
10
1J
3
12
10
VCC
CLR
4
11
GND
5
10
2J
2PRE
6
2K
7
9
8
20
20
For functionally and electrically identical
parts in chip carrier packages, see
SN54HC114 and SN74HC114.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
J
K
0
L
H
X
X
X
H
0
L
H
L
X
X
X
L
H
L
L
X
X
X
H*
H*
H
H
l
L
L
00
00
H
H
L
H
L
H
l
l
H
H
L
H
L
H
H
H
l
H
H
TOGGLE
H
H
H
X
X
00
00
* This configuration is nonstable; that is, it will not persist
when either Preset or Clear returns to its inactive (high)
level.
II
z
o
i=
«
~
ex:
oLL
Pin numbers shown are for J and N packages.
Z
logic diagram, each flip-flop (positive logic)
W
U
PRE----------------------------------~~------,
z
....
J----~-
o
r----------,
I
I
I
I
CLK~I C
«
>
c
«
I I
C
CLR
I
maximum ratings, recommended operating conditions, and electrical characteristics
See Table II, page 2-6.
ADVANCE INFORMATION
This document contains information
on a new product. Specifications are
subject to change without notice.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-5
TYPES SN54HC18, SN14HC18
DUAL J·K NEGATIVE·EDGE·TRIGGERED FLlP·FLOPS
WITH PRESET, COMMON CLEAR, AND COMMON CLOCK
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
vcc
fclock
2V
4.5 V
Clock frequency
ClR or PRE
low
tw
Pulse duration
ClK high
or low
ClR or PRE
tsu
Setup time before ClK.t
inactive
or data
0
6V
20
17
2V
4.5 V
100
20
6V
2V
4.5 V
17
100
SN54HC78
MIN
MAX
SN74HC78
MIN
MAX
5
25
0
0
100
2V
4.5 V
0
6V
0
UNIT
MHz
29
ns
ns
20
17
6V
Hold time. data after ClK .t
th
6V
2V
4.5 V
TA = 25 D C
MIN
MAX
ns
ns
0
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), Cl = 50 pF (see Note 1)
II
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
<
l>
om
tplH
;2
tpHl
CUi
ClR
PRE
Q
Q
Q
."
o:JJ
S
tPlH
PRE
Q
o:2
tpd
tpd
ClK
ClK
tt
Q
Q
SN54HC78
MIN
MAX
2V
4.5 V
17
6V
14
2V
4.5 V
40
13
6V
11
2V
4.5 V
52
6V
2V
4-6
volt~ge
MAX
14
ns
ns
ns
36
12
4.5 V
UNIT
ns
17
ns
10
4.5 V
52
17
6V
14
2V
48
ns
ns
16
14'
4.5 V
6V
2V
38
4.5 V
8
6V
6
ns
30 pF typ
Power dissipation capacitance per flip-flop
NOTE 1: For load circuit and
SN74HC78
MIN
9
50
60
52
6V
2V
l>
~
5
25
29
6V
tpHl
:2
TA = 25 DC
MIN TYP MAX
2V
4.5 V
f max
l>
C
VCC
waveforms. see page 1-14.
TEXAS
~
INSTRUMENTS '
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3E
:4
TYPES SN54HC85. SN74HC85
4·81T MAGNITUDE COMPARATORS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
•
•
SN54HC85 •.. J PACKAGE
SN74HC85 .•. J OR N PACKAGE
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
(TOP VIEW)
Dependable Texas Instruments Quality and
Reliability
INPUTS
description
These four-bit magnitude comparators perform
comparison of straight binary and straight BCD
(8-4-2-1) codes. Three fully decoded decisions
about two 4-bit words (P, Q) are made and are
externally available at three outputs. These
devices are fully expandable to any number of
bits without external gates. Words of greater
length may be compared by connecting
comparators in cascade. The P>Q, P Q,
P < Q, and P = Q inputs of the next stage handling
more-significant bits. The stage handling the
least-significant bits must have a high-level
voltage applied to the P = Q input. The cascading
path of the 'HC85 is implemented with only a
two-gate-Ievel delay to reduce overall
comparison times for long words.
The SN54HC85 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC85 is
characterized for operation from - 40°C to
85°C.
r
Q3
OUTPUTS
o
P=Q
P>Q
r
o
P=Q
PQ
NC
t~: ~
I-OOUOO
::JVZZOa..
!=a..(!)
'::J
o
NC-No internal connection
Pl
P2
P3
po
00
Q1
02
03
(12)
t=
«
~
a:
COMP
(10)
z
o
ou.
logic symbol
PO
II
:}
<
~
w
p
}
(7)
(6)
(5)
p
c
«
po
Pin numbers shown are for J and N packages.
Copyright © 1982. Texas Instruments Incorporated
ADVANCE INFORMATION
This document contains information
on a new product. Specifications are
subject to change without notice.
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TeXAS 75265
4-7
TYPES SN54HC85, SN74HC85
4·81T MAGNITUDE COMPARATORS
FUNCTION TABLE
COMPARING
CASCADING
INPUTS
INPUTS
P3.03
P2.02
P3>03
P3=Q3
X
X
P2>02
P2<02
P2=02
P2=02
P3=03
P2=02
P3=Q3
P3=Q3
P3=Q3
P2=02
P2=Q2
P2=Q2
P3=Q3
P2=Q2
P3Ql
PlQO
POO
X
OUTPUTS
PO
H
PQ
or
4.5 V
P
c
:2
"n
o
tpd
:xl
S
»
~
o
tpd
Any P or Q
PQ
P>Q
or
P=Q
P
C
L
H
L
H
H
A
0
1
2
3
4
5
6
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H.
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
L
L
H
H
H
.H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
H
H
H
L
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
H
X
X
X
H
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
10
11
12
13
14
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
Ii
L
H
Ii
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
9
H
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
15
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
See Table IV, page 2-10.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
2
PARAMETER
FROM
(INPUT)
TO
IOUTPUT)
Vce
2V
72
180
tpd
A, B,C,orO
Any
4.5 V
24
6V
m
2
."
o
:xJ
tpd
G1orG2
l>
tt
::j
TA = 25°C
MIN TYP MAX
SN54HC154
MIN
MAX
SN74HC154
MIN
MAX
36
270
54
225
45
20
31
46
38
2V
72
180
270
225
Any
4.5 V
6V
24
20
36
31
54
46
45
38
2V
28
75
110
95
Any
4.5 V
8
22
19
6V
6
15
13
19
16
S
2
H
H
H
maximum ratings, recommended operating conditions, and electrical characteristics
('")
o
OUTPUTS
7
8
B
H = high level, L = low level, X = irrelevant
l>
c
L
H
INPUTS
0
C
UNIT
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
3!
4-10
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
14
TYPES SN54HC189, SN54HC219, SN74HC189, SN74HC219
64·BIT RANDOM·ACCESS MEMORIES WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
•
Organized as 16 Words of Four Bits Each
•
Choice of Noninverted or Inverted Outputs
•
High·Current 3-State Inverting Outputs Can
Drive up to 15 LSTTL Loads
•
•
SN54HC189 ... J PACKAGE
SN74HC189 ... J OR N PACKABE
(TOP VIEW)
AO
1
U
S
Riw
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
01
4
01
02
5
6
VCC
15
14
A1
A2
A3
13
12
11
02
Dependable Texas Instruments Quality and
Reliability
16
04
04
03
10
GNO
03
SN54HC189 ... FH OR FK PACKAGE
SN74HC189 ... FH OR FN PACKAGE
(TOP VIEW)
description
Information to be stored in the memory is written
into the selected address location when the chipselect (5) and the write-enable (R/W) inputs are
low. While the write-enable input is low, the
memory outputs are off (Hi-Zl. When a number
of outputs are bus-connected, this off state
neither loads nor drives the data bus; however,
it permits the bus line to be driven by the other
active outputs or a passive pUll-up.
Information stored in the memory (see function
table for input/output phase relationship) is
available at the outputs when the write-enable
input is high and the chip-select input is low.
When the chip-select input is high, the outputs
will be off.
o U
I(/) <{ Z
U
U~
>
<{
A2
01
A3
NC
NC
01
04
02
04
NOUMM
10
Z
II
zlO 0
(!)
SN54HC219 ... J PACKAGE
SN74HC219 ... J OR N PACKAGE
(TOP VIEW)
l U16
VCC
5
2
15
A1
R/W
3
4
14
A2
01
01
5
13
12
02
6
11
A3
04
04
10
03
AO
The SN54HC189 and SN54HC219 are
characterized for operation over the full military
temperature range of - 55°C to ·125 °C. The
SN74HC189 and SN74HC219 are characterized
for operation from -40°C to 85°C.
02
7
GNO
B
2
o
~
~
a::
o
LL
-
90 03
2
w
FUNCTION TABLE
INPUTS
CHIP
WRITE
Write
SELECT
L
ENABLE
L
Read
L
H
FUNCTION
OUTPUTS
'HC189
Z
Complement
of data
entered
Inhibit
H
X
SN54HC219 ... FH OR FK PACKAGE
SN74HC219 ... FH OR FN PACKAGE
Z
(.)
(TOP VIEW)
'HC219
o
Z
I(/) <{
U
2
«
>
c
«
U
U~
z >
<{
Oata
A2
A3
entered
Z
NC
01
04
02
Q4
NOUMM
ozzoo
(!)
, NC - No internal connection
Copyright © 1982. Texas Instruments Incorporated
ADVANCE INFORMATION
This document contains information
on a new product. Specifications are
subject to change without notice.
TEXAS •
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS. TeXAS 75265
4-11
TYPES SN54HC189, SN54HC219, SN74HC189, SN74HC219
64·BIT RANDOM·ACCESS MEMORIES WITH 3·STATE OUTPUTS
logic symbols
'HC189
AD
Al
A2
(11
(15)
(14)
'HC219
RAM 16X 4
RAM 16 X 4
]A~
AD
Al
A2
S
S
R/W
R/W
01
01
02
02
04
]A~
(15)
(14)
A3
A3
03
(1)
01
02
D3
(12)
(11)
D4
03
04
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
II
See Table VII, page 2-14.
timing requirements over recommended operating free-air temperature range lunless otherwise noted)
VCC
TA = 25°C
MIN
»
c
<
»
2
o
m
tw
Pulse duration, R/W low
Address before R/IN ~
tsu
Setup time
Data before R/Vii t
2
'"T1
o
:J:J
s:
Chip-select before R/Wt
»
-t
o
2
Address after R/IN t
th
Hold time
Data after R/W t
Chip-select after R/Vii t
4-12
MAX
SN54HC189
SN54HC219
MIN
MAX
SN74HC189
SN74HC219
MIN
2V
275
400
350
4.5 V
55
80
70
6V
47
68
60
2V
0
0
0
4.5 V
0
0
0
6V
0
0
0
2V
275
400
350
4.5 V
55
80
70
6V
47
68
60
2V
275
400
350
4.5 V
55
80
70
6V
47
68
60
0
0
0
0
0
0
0
0
0
2V
0
0
4.5 V
0
0
6V
0
0
2V
0
0
4.5 V
0
6V
0
2V
0
0
0
0
4.5 V
0
0
6V
0
0
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
UNIT
MAX
ns
ns
ns
TYPES SN54HC189, SN54HC219, SN74HC189, SN74HC219
64·BIT RANDOM·ACCESS MEMORIES WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted) CL = 50 pF (see Note 1)
PARAMETER
ta(ad)
ta(S)
ten
FROM
TO
(FROM)
(OUTPUT)
A
Any
S
R/W
S
Any
Any
Any
tdis
R/IN
Any
Any
tt
Cpd
TA = 25°C
vcc
MIN
TYP
2V
81
4.5 V
27
6V
23
2V
81
4.5 V
27
6V
23
2V
50
4.5 V
16
6V
14
2V
25
4.5 V
8
6V
7
2V
35
4.5 V
11
6V
10
2V
28
4.5 V
8
6V
6
MAX
SN54HC189
SN54HC219
MIN
Power dissipation capacitance
MAX
SN74HC189
SN74HC219
MIN
ns
ns
ns
ns
ns
55 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
UNIT
MAX
II
2
o
i=
C
U
U ....
C
c
<
l>
tw
Pulse duration, R/W low
Address before R/W +
2
(')
m
tsu
Setup time
Data before R/W t
Chip-select before R/Wt
2
."
o
Address after R/Wt
::xJ
S
th
l>
::!
o
TA = 25°C
Hold time
Data after R/Wt
Chip-select after R/W t
MAX
SN54HCT189
SN54HCT219
MIN
SN74HCT219
MIN
4.5 V
55
80
70
5.5 V
50
75
63
4.5 V
0
0
0
5.5 V
0
0
0
4.5 V
55
80
70
5.5 V
50
75
63
4.5 V
55
80
70
5.5 V
50
75
63
4.5 V
0
0
0
5.5 V
0
0
0
4.5 V
0
0
0
5.5 V
0
0
0
4.5 V
0
0
0
5.5 V
0
0
0
2
4-16
MAX
SN74HCT189
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
UNIT
MAX
ns
ns
ns
ns
ns
ns
\
ns
TYPES SN54HCT189, SN54HCT219, SN74HCT189, SN74HCT219
64·BIT RANDOM·ACCESS MEMORIES WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL - 50 pF (see Note 1)
FROM
(INPUT)
TO
(OUTPUT)
ta(ad)
A
Any
ta(S)
S
Any
PARAMETER
ten
R/W
Any
S
Any
R/W
Any
tdis
tt
Any
TA = 25°C
vcc
MIN
4.5 V
5.5 V
4.5 V
5.5
4.5
5.5
4.5
V
V
V
V
5.5
4.5
5.5
4.5
V
V
V
V
TYP MAX
27
SN54HCT189
SN54HCT219
MIN
MAX
SN74HCT189
SN74HCT219
MIN
MAX
ns
23
27
ns
23
16
14
ns
8
7
11
10
12
11
5.5 V
Power dissipation capacitance
UNIT
ns
ns
No load. TA
= 25°C
55 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
II
z
o
i=
C
C
<
J>
2
(')
m
2
o"
::D
s:J>
-t
o
;2
4-18
HIGH·SPEED
CMOS LOGIC
TYPES SN54HCT245. SN74HCT245
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
02804. MARCH 1984
•
Inputs Are TTL-Voltage Compatible
•
High·Current 3-State Outputs Drive Bus
Lines Directly or Up to 15 LSTTL Loads
•
Package Options Include Both Plastic
and Ceramic Chip Carriers in Addition to
Plastic and Ceramic DIPs
•
SN54HCT245 ... J PACKAGE
SN74HCT245 .•. J OR N PACKAGE
(TOPVIEWI
description
B1
B2
B3
B4
B5
B6
B7
B8
GND
These octal bus transceivers are designed for
asynchronous two-way communication
between data buses. The control function
implementation minimizes external timing
requirements.
SN54HCT245 .•• FH OR FK PACKAGE
SN74HCT245 •.• FH OR FN PACKAGE
(TOPVIEWI
N
.-
««
The devices allow data transmission from the A
bus to the B bus or from the B bus to the A bus
depending upon the logic level at the direction
control (DIR) input. The enable input (G) can be
used to disable the device so that the buses are
effectively isolated.
A4
A5
A6
A7
The SN54HCT245 is characterized for
operation over the full military temperature
range of - 55°C to 125°C. The SN74HCT245
is characterized for operation from - 40°C to
85°C.
.
G
A1
A2
A3
A4
A5
A6
A7
A8
Dependable Texas Instruments Quality
and Reliability
FUNCTION TABLE
vee
DIR
~ ~
0
>
I(!)
B1
B2
B3
B4
B5
II
2:
o
i=
C
A4
(15)
B4
c
<
:r>
:2
tpdten
tt
FROM
(INPUT)
A or B
G
TO
(OUTPUT)
BorA
A or B
A or B
TA =25°C
TYP
MAX
SN54HCT245
MIN
MAX
4.5 V
20
30
45
5.5 V
18
36
27
59
41
63
4.5 V
30
17
89
80
42
63
5.5 V
14
38
57
VCC
4.5 V
5.5 V
MIN
SN74HCT245
MIN
MAX
38
34
74
67
53
48
UNIT
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
(')
m
:-2
."
o
:XJ
s::r>
::f
o
:2
4-20
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3:
TYPES SN54HC283, SN74HC283
4·BIT BINARY FULL ADDERS WITH FAST CARRY
HIGH·SPEED
CMOS LOGIC
02804, MARCH 1984
•
Full-Carry Look-Ahead Across the Four Bits
•
Systems Achieve Partial Look-Ahead
Performance with the Economy of Ripple
Carry
SN54HC283 •.. J PACKAGE
SN74HC283 ... J OR N PACKAGE
(TOP VIEW)
•
Supply Voltage and Ground on Corner Pins
to Simplify P-C Board Layout
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
1:2
B2
A2
1:1
A1
B1
CO
GND
VCC
B3
A3
1:3
A4
B4
1:4
C4
SN54HC283 ..• FH OR FK PACKAGE
SN74HC283 •.• FH OR FN PACKAGE
description
(TOP VIEW)
These improved full adders perform the addition
of two 4-bit binary words. The sum (E) outputs
are provided for each bit and the resultant carry
(C4) is obtained from the fourth bit.
These adders feature full internal look-ahead
across all four bits generating the carry term.
This capability provides the system designer
with partial look-ahead performance at the
economy and reduced package count of a ripplecarry implementation.
The adder logic, including the carry, is
implemented in its true form, End around carry
can be accomplished without the need for logic
or level inversion.
N
U
N UU",
mt.lz>m
A2
1:1
A3
1:3
NC
A1
B1
A4
84
NC
II
z
o
t=
NC-No internal connection
C
~;x
.A0f:"'"
:fg .•.•
WHEN
CO = H
~l:'~::·····
>/ ... ''1 .:.x ~.
~-
/:& l/i ~ % ~ ~ ~ ~ l/i ~
C4
A4
64
L
L
L
L
L
1:3
H
L
L
I::4
1:4
H
L
L
L
H
L
L
L
H
L
L
H
L
L
H
L
L
L
H
L
H
H
L
L
L
H
L
H
L
L
H
L
L
H
H
L
L
L
H
H
H
L
L
H
H
H
L
L
H
L
H
H
L
H
H
L
L
H
H
H
H
L
L
H
L
H
L
L
L
L
H
L
H
L
H
L
H
H
L
H
L
L
H
L
L
H
H
L
H
H
H
L
L
H
H
H
L
L
L
H
H
L
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
L
H
H
H
H
L
H
H
H
H
H
H
L
H
L
L
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H = high level. L = low level
NOTE: Input conditions at A 1. Bl. A2. B2. and CO are used to determine outputs El and
E2 and the value of the internal carry C2. The values at C2. A3. B3. A4. and B4
are then used to determine outputs E3. E4. and C4.
l>
C
~
C4
B3
L
L
H
II
~3
A3
L
logic symbol
2
n
Al
m
Jp
A2
2
A3
'TI
o
A4
S
l>
B2
Bl
:xJ
B3
B4
::i
o
CO
(6)
(2)
(15)
(11)
]0
~
k[
(4)
:El
:E2
:E3
:E4
C4
(7)
CI
2
Pin numbers shown are for J and N packages.
4-22
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC283, SN74HC283
4·BIT BINARY FULL ADDERS WITH FAST CARRY
logic diagram (p,ositive logic)
II
2
o
i=
C
5l
G/OG
Ow
E/OE
Two function-select inputs and two output
control inputs can be used to choose the modes
of operation listed in the function table.
Synchronous parallel loading is accomplished by
taking both function-select lines, SO and S 1,
high. This places the three-state outputs in a
high-impedance state. Which permits data that
is applied on the I/O ports to be clocked into the
register. Reading out of this register can be
accomplished while the outputs enabled in any
mode. A direct overriding input is provided to
clear the register whether the outputs are
enabled or off. Taking either of the output
controls, <31 or <32, high disables the outputs but
this has no effect on shifting or storage of data.
~
1(91(9
C/OC
A/OA
H/OH
F/OF
ON
D/OD
II
2
o
i=
«
logic symbol
2
a:
oLL
2
w
CJ
2
«
>
c
«
The SN54HC299 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC299 is
characterized for operation from - 40°C to
85°C.
2,40
ADVANCE INFORMATION
This document contains information
on a new product. Specifications are
subject to change without notice.
Copyright ©, 1982. Texas Instruments Incorporated
../t!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-25
TYPES SN54HC299. SN74HC299
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH DIRECT CLEAR AND 3·STATE OUTPUTS
logic diagram (positive logic)
Ei:ii
-a
..:..;9:..:,.1_ _ _ _ _ _ _ _ _--,-_ _
~_-,
G1 ~12~1_____Q>_----------~
02
so
S1
ClK ...;..11...;..21_---f
SR
(11)
A/QA ...;..17...;..1...........<
II»
c
<
»
:2
(")
m
">--+--+--+-1-+-_ _ _ _ _ _ _ _-+-_ _--.
I--+-+--+-+-l--.-+-------:---+-+---t-----J
C1
---4-< f--+-+--+-~-o--+--------+-+----t------J
B/QB ...;..11...;..31.....
C/Q
D/Q
E/Q
C
D
~I
E
~II
:2
F/QF~
o
G/QG~L ____
."
::rJ
---------,
r---~I
I
I
I
I
I
5 CHANNELS IDENTICAL
TO CHANNEL B ABOVE
I
I
I
I
I
--- - - - - -
_
S
»
-4
o:2
H/QH~11_61~-.< r------r------.----------~
Sl 1181
4-26
TEXAS "-/}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
I
--~
TYPES SN54HC299, SN74HC299
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH DIRECT CLEAR AND 3·STATE OUTPUTS
FUNCTION TABLE
INPUTS
MODE
OUTPUT
SELECT
SO
CONTROL
G1 t G2 t
CLEAR
S1
Clear
Hold
Shift Right
Shift left
load
INPUTS/OUTPUTS
FUNCTION
CLOCK
SERIAL
SL
SR
OUTPUTS
A/OA B/OB C/OC 0/00 E/OE F/OF G/OG H/OH
°A'
°H'
L
X
L
L
L
X
X
X
l
l
l
l
l
l
l
l
L
l
l
l
X
l
l
X
X
X
l
l
l
L
L
l
L
l
L
L
X
X
X
X
X
X
L
l
l
H
H
X
X
X
X
X
X
X
H
l
X
L
L
l
X
X
OAO OSO
OCO QOO
QEO
QFO
QGO QHO
QAO QHO
H
X
l
l
L
L
X
X
H
H
l
l
l
X
X
QAO QSO
X
X
QCO QDO
X
X
QEO
X
QFO
X
QGO QHO
X
X
QAO QHO
H
H
l
H
l
l
X
H
QEn
QFn
QGn
l
H
l
l
QCn
QCn
QO n
H
QO n
QEn
QFn
H
H
l
L
L
QEn
QFn
QGn
QHn
QGn
H
H
H
l
l
l
H
H
H
X
X
t
t
t
t
t
QEn
d
QFn
e
QGn
f
OHn
g
H
QAn
QS n
°Sn
QO n
QO n
c
X
l
l
QAn
H
X
QS n
QCn
l
X
X
X
QS n
a
QCn
b
l
h
QAO QHO
H
QGn
l
QGn
QS n
H
QS n
a
h
l
t When one or both output controls are high the eight input/output terminals are disabled to the high-impedance state; however, sequential
operation or clearing of the register is not affected.
a ... h = the level of the steady-state input at inputs A through H, respectively. These data are loaded into the flip-flops while the flip-flop
outputs are isolated from the input/output terminals.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
SN54HC299
TA = 25°C
VCC
fclock
tw
Clock frequency
Pulse duration
ClK high, ClK low,
or ClR low
Select
tsu
MAX
MIN
MAX
MIN
2V
0
5
0
3.3
0
4
0
25
0
17
0
20
6V
29
0
19
150
0
125
24
2V
0
100
4.5 V
20
30
25
6V
17
26
21
2V
150
225
190
4.5 V
30
45
38
6V
25
38
32
before CLK t
2V
100
150
125
4.5 V
20
30
25
6V
17
26
21
Data or
Hold time
Select or
after ClK t
data
MAX
4.5 V
Setup time
ClR inactive
th
MIN
SN74HC299
2V
0
0
0
4.5 V
0
0
0
6V
0
0
0
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
UNIT
II
2!
o
MHz
i=
ns
a:
«
~
oLL
2!
ns
w
(J
ns
ns
2!
«
>
c
«
4-27
TYPES SN54HC299, SN74HC299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH DIRECT CLEAR AND 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
vCC
TA = 25 D C
MIN
TVP MAX
tpd
ClK
0A thru OH
G1 or G2
0A thru OH
ten
SO or S1
G1 or G2
0A thru OH
tdis
II»
SO or S1
OA' or Ow
o
tpHl
<
»
2
ClR
0A thru OH
(")
m
tt
2
."
o
::xJ
S
Cpd
Y
SN74HC299
MIN
5
3.3
4.5 V
25
17
4
20
29.
19
24
4.5 V
35
11
6V
2V
9
42
4.5 V
14
6V
2V
12
50
4.5 V
15
6V
2V
12
50
4.5 V
15
6V
2V
12
60
4.5 V
20
6V
17
2V
60
4.5 V
20
6V
2V
17
40
4.5 V
6V
13
11
2V
55
4.5 V
16
6V
14
2V
4.5 V
38
8
6V
6
MAX
»
::!
o
2
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
100 pF typ
Power dissipation capacitance
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
4-28
MAX
2V
6V
2V
OA' or OH'
SN54HC299
MIN
TYPES SN54HC299, SN74HC299
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH DIRECT CLEAR AND 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA = 25°C
MIN
TYP MAX
2V
QA' or QW
ClK
tpd
QA thru QH
<31 or <32
QA thru QH
ten
SO or S1
ch
or <32
QA thru QH
tdis
SO or S1
QA' or QH'
tpHl
ClR
QA thru QH
SN54HC299
MIN
MAX
SN74HC299
MIN
MAX
UNIT
50
4.5 V
17
6V
12
2V
55
4.5 V
20
6V
18
2V
90
4.5 V
30
6V
24
2V
90
4.5 V
30
6V
24
2V
90
4.5 V
30
6V
24
2V
90
4.5 V
30
6V
24
2V
60
4.5 V
26
6V
22
2V
70
4.5 V
28
6V
24
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
ns
ns
ns
ns
\
ns
ns
ns
ns
II
2
o
i=
C
0
A/OA
C/OC
E/OE
G/OG
OE
SE
D1
BlOB
D/OD
F/OF
II
2
o
i=
c
OE
<
sip
:2
CLK
C
l>
G
0
m
:2
SE
."
os
::u
S
01
A/OA
:::!
BIas
0
l>
0
:2
DO
C/Oc
(12)
4-32
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC322, SN74HC322
8·BIT SHIFT REGISTERS WITH SIGN EXTEND AND 3·STATE OUTPUTS
logic diagram (positive logic)
B/OB
INPUTS/OUTPUTS NOT SHOWN
(5) C/OC
(15) D/OD
(6) E/OE
(14) F/OF
maximum ratings, recommended operating conditions, and electrical characteristics
II
2
o
i=
«
~
a::
ou.
See Table III, page 2-8.
2
w
CJ
2
«
>
c
«
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-33
TYPES SN54HC322. SN74HC322
8·BIT SHIFT REGISTERS WITH SIGN EXTEND AND 3·STATE OUTPUTS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
CLK high
tw
Pulse duratio~
eLK low
CLR low
DS
tsu
Setup time before CLK t
CLR inactive
II
l>
o
<
l>
Data inputs
state
DS
th
Hold time after CLK t
Data inputs
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
0
3.3
0
17
0
20
200
40
34
100
20
17
150
30
26
100
20
17
150
30
26
150
30
26
75
15
13
0
0
0
SN54HC322
MIN
MAX
2.2
0
11
0
13
0
300
60
51
150
30
26
225
45
38
150
30
26
225
45
38
225
45
38
115
23
20
0
0
0
:2
om
:2
."
o
:c
~
l>
:::!
o
:2
4·34
TEXAS
~
- INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SN74HC322
MAX
MIN
2.7
0
13
0
16
0
250
50
43
125
25
21
190
38
32
125
20
21
190
38
32
190
38
32
95
19
16
0
0
0
UNIT
MHz
ns
ns
ns
TYPES SN54HC322. SN74HC322
8-BIT SHIFT REGISTERS WITH SIGN EXTEND AND 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
tpd
tpHL
tpd
tpHL
Clock
Clear
Clock
Clear
Output
ten
enable
Output
tdis
tt
enable
Qw
QH'
QA thru QH
QA thru QH
QA thru QH
QA thru QH
vCC
SN54HC322
TA = 25°C
TYP MAX
MIN
MIN
MAX
SN74HC322
MIN
2V
3.3
6
2.2
4.5 V
17
35
11
13
6V
20
40
13
16
2V
95
4.5 V
31
6V
26
2V
95
4.5 V
32
6V
27
2V
80
4.5 V
26
6V
22
2V
80
4.5 V
26
6V
22
2V
55
4.5 V
18
6V
15
2V
55
4.5 V
18
6V
15
2V
38
4.5 V
8
6V
6
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
MAX
UNIT
2.7
MHz
ns
ns
ns
ns
ns
ns
ns
II
2
o
i=
c
en
5l
°H'
H/OH
II
F/OF
D/OD
2:
o
i=
«
logic symbol
~
a:
o
LL
2:
w
(J
2:
«
>
c
«
The SN54HC323 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC323 is
characterized for operation from - 40°C to
85°C.
Copyright © 1982. Texas Instruments Incorporated
ADVANCE INFORMATION
This document contains Information
on a new product. Specifications are
subject to change without notice.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-37
TYPES SN54HC323, SN74HC323
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH SYNCHRONOUS CLEAR AND 3·STATE OUTPUTS
logic diagram (positive logic)
m
61
....:..;.;,.------------~ ~-.....,
"';';;';"---<1
>-------.....,
02
so
S1
ClK
--~ ~_+__I_4_I_+--------_+_--__,
SR 1111
A/oA .....;1......
71......-..<
I---+-_+-+-+--I~_+-----__+_+---t_-----'
II
l>
C
<
l>
2
om
2
"TI
o
:D
BlaB
CI
161
_~
---------,I
r---I
OC~
0100
EI
_11_31. . ._< I--+-+-+--f-t---.-+------.-t---t------'
~I
151
I
OE ----4+-'1
5 CHANNELS IDENTICAL
I
I
I
TO CHANNEL B ABOVE
1
I
I
F/OF~
G/OG~L ____
I
I
_______ ---..II
_
s:
l>
:::!
o
2
_11_61....._<
Sl 1181
H/OH
4-38
t-------+---------4----------'
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3:
TYPES SN54HC323. SN74HC323
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH SYNCHRONOUS CLEAR AND 3·STATE OUTPUTS
FUNCTION TABLE
INPUTS
MODE
CLEAR
OUTPUT
SELECT
CONTROL
G1t G2 t
S1
Clear
Hold
Shift Right
Shift Left
load
INPUTS/OUTPUTS
FUNCTION
SO
CLOCK
SERIAL
SL
SR
X
OUTPUTS
A/OA B/OB C/OC D/OD E/OE F/OF G/OG H/OH
°A'
°H'
l
X
l
l
l
l
l
l
l
l
L
X
X
l
l
l
l
l
l
l
L
L
l
X
t
t
t
X
X
X
X
X
X
X
X
X
X
l
l
l
l
L
X
X
QAO QBO
QCO QDO
QEO
QFO
QGO QHO
QAO QHO
l
L
L
X
X
l
L
L
X
X
QBO
X
QCO QDO
X
X
QEO
X
QFO
X
QGO QHO
X
X
QAO QHO
H
QAO
X
l
H
l
l
t
t
t
t
t
X
H
H
QAn
QBn
QCn
QDn
QEn
QFn
QGn
QGn
H
l
X
L
l
l
l
L
X
l
l
l
H
H
X
H
L
X
H
H
H
H
H
H
H
X
l
H
l
H
L
l
H
l
l
l
H
l
L
l
H
H
X
X
X
l
l
QAn
QBn
QCn
QDn
QEn
QFn
H
X
QBn
QCn
QDn
QEn
QFn
QGn
QHn
L
X
X
X
QBn
a
QCn
b
QDn
c
QEn
d
QFn
e
QGn
f
QHn
g
l
h
QAO QHO
H
QGn
l
QGn
QBn
H
QBn
a
L
h
t When one or both output controls are high the eight input/output terminals are disabled to the high-impedance state; however, sequential
operation or clearing of the register is not affected.
a ... h = the level of the steady-state input at inputs A through H, respectively. These data are loaded into the flip-flops while the flip-flop
outputs are isolated from the input/output terminals.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
tw
Clock frequency
Pulse duration
ClK high or low
SO or S1
tsu
SN54HC323
MAX
MIN
2V
0
5
0
3.3
0
4
0
25
0
17
0
20
6V
2V
0
100
29
0
150
19
0
125
24
4.5 V
20
30
25
6V
17
26
21
2V
150
225
190
4.5 V
30
45
38
6V
26
38
32
2V
100
150
125
4.5 V
20
30
25
6V
17
26
21
0
Hold time
SO or S1,
after ClK t
data, or ClR low
MAX
4.5 V
Setup time
ClR low
2:
SN74HC323
MIN
before ClK t
or data
th
TA = 25°C
MIN
MAX
2V
0
0
4.5 V
0
0
0
6V
0
0
0
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
II
UNIT
MHz
ns
o
i=
C
ns
SO or S1
tt
C
<
>
Z
(')
OA thru OH
Any
SN54HC323
MIN
SN74HC323
MIN
5
25
3.3
4
17
20
6V
2V
29
19
24
MAX
UNIT
MHz
36
4.5 V
12
6V
10
2V
50
14
4.5 V
ns
12
50
15
6V
12
2V
50
4.5 V
15
6V
2V
60
ns
12
20
17
6V
2V
4.5 V
60
6V
2V
17
28
4.5 V
8
6V
6
ns
20
ns
100 pF typ
Power dissipation capacitance
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
m
Z
~
ojJ
s:
>
::!
o
z
4-40
MAX
2V
4.5 V
4.5 V
G1, G2
tdis
TA = 25°C
MIN
TYP MAX
6V
2V
4.5'V
G1, G2
ten
VCC
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC323. SN74HC323
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH SYNCHRONOUS CLEAR AND 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
QA' or QH'
tpd
elK
QA thru QH
<31, <32
QA thru QH
ten
SO or S1
<31, <32
QA thru QH
tdis
SO or S1
tt
Any
VCC
TA = 25°C
MIN
TYP MAX
2V
50
4.5 V
17
6V
15
2V
50
4.5 V
17
6V
15
2V
90
4.5 V
30
6V
24
2V
90
4.5 V
30
6V
24
2V
90
4.5 V
30
6V
24
2V
90
4.5 V
30
6V
24
2V
45
4.5 V
17
6V
13
SN54HC323
MIN
NOTE 1: For load circuit and voltage waveforms, see page 1- 14.
MAX
SN74HC323
MIN
MAX
UNIT
ns
ns
ns
ns
II
2
o
~
~
a:
oLL
2
w
U
2
«
>
c
«
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-41
II»
c
<
»
2
o
m
2
'TI
o
:tI
3:
»
::::!
o
2
4-42
TYPES SN54HC354, SN74HC354
B·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS/
TRANSPARENT REGISTERS WITH 3·STATE OUTPUTS
HIGH·SPEED
. CMOS LOGIC
02684, DECEM8ER 1982-REVISED MARCH 1984
•
Transparent Latches on Data Select Inputs
•
Transparent Data Registers
•
High·Current 3·State Outputs Can Drive up
to 1 5 LSTTL Loads
(TOP VIEW)
o
Complementary Outputs
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
SN54HC354 ... J PACKAGE
SN74HC354 ... J OR N PACKAGE
D7
D6
D5
D4
D3
D2
D1
DO
De
GND
Dependable Texas Instruments Quality and
Reliability
Vee
y
W
G3
<32
51
50
51
52
5e
description
SN54HC354 ... FH OR FK PACKAGE
SN74HC354 ... FH OR FN PACKAGE
These monolithic data selectors/multiplexers
contain full on-chip binary decoding to select one
of eight data sources. The data-select is stored
in transparent latches that are enabled by a low
level on pin 11. SC. A similar enable for data is
obtained by a low level on pin 9. OC.
(TOP VIEW)
U
r-- U
,000>>Ltl (0
D4
D3
D2
D1
DO
The SN54HC354 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC354 is
characterized for operation from - 40°C to
85°C.
W
G3
G2
Iu °lu
t9
logic symbol
II
51
50
('oj
z
o
.-
OZUlUlUl
t=
MUX
C
C
<
l>
:2
0
m
(19)
y
03 (5)
2
"T1
0
:0
S
l>
:::i
0
:2
4-44
04 (4)
(18)
w
05 (3)
06
(2)
07
(1)
TEXAS
-'i1
:v
,
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
38~
TYPES SN54HC354, SN74HC354
B·L1NE TO 1·L1NE DATA SELECTORS/MULTIPLEXERS/
TRANSPARENT ,REGISTERS WITH 3·STATE OUTPUTS
FUNCTION TABLE
INPUTS
DATA
SELECTt
S2
S1
SO
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
L
L
H
H
H
H
H
L
L
H
H
L
L
H
H
H
H
H
H
H
L
X
Z
H
L
L
H
H
L
L
L
L
H
H
DC
X
X
X
G1
X
G2
X
H
X
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
OUTPUTS
OUTPUT
ENABLES
CONTROL
H
X
L
L
L
L
L
L
L
L
G3
W
Y
X
Z
Z
Z
Z
Z
Z
X
L
H
Do
DO
H
H
DOn
01
DOn
01
H
D1n
02
01n
02
D2n
03
02n
03
H
03 n
04
03 n
04
H
H
D4 n
05
H
05 n
04n
05
05 n
H
H
H
H
H
06
06
H
D6 n
H
H
'07
06 n
07
D7 n
07 n
II
= high level (steady state)
= low level (steady state)
= irrelevant (any input, including transitions)
2
o
= high-impedance state (off state)
t = transition from low to high level
00 ... 07 = the level of stead-state inputs at inputs DO through
07, respectively
DOn ... 07 n = the level of steady state inputs at inputs DO through
07, respectively, before the most recent low-to-high
transition of data control
tThis column shows the input address setup with SC low.
i=
C
C
Y
<
:t>
ten
G1, G2
:2
W
(")
m
Y
:2
."
o
tdis
<31, G2
:u
W
S
:t>
Y
~
o
ten
G3
:2
W
VCC
TA = 25°C
MIN
TYP MAX
2V
90
4.5 V
29
6V
2V
25
85
4.5 V
28
6V
24
2V
85
4.5 V
28
6V
24
2V
4.5 V
85
28
6V
24
2V
100
4.5 V
32
6V
27
2V
4.5 V
90
6V
26
2V
85
28
6V
24
2V
80
4.5 V
6V
26
22
2V
75
4.5 V
24
6V
20
2V
75
4.5 V
24
6V
20
2V
45
4.5 V
15
6V
13
2V
45
4.5 V
15
6V
2V
13
75
4.5 V
24
6V
20
2V
75
24,
6V
Y
tdis
G3
W
2V
20
50
4.5 V
17
6V
15
2V
50
4.5 V
17
6V
15
Power dissipation capacitance
MAX
SN74HC354
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
30
4.5 V
4.5 V
SN54HC354
MIN
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
No load, TA
= 25°C
40 pF typ
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
4-46
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
31
TYPES SN54HC356. SN74HC356
B·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS/
EDGE·TRIGGERED REGISTERS WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
•
Transparent latches on Data Select Inputs
•
Edge·Triggered Data Registers
•
High-Current 3-State Outputs Can Drive up .
to 15 lSTTl loads
/
G
Complementary Outputs
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN54HC356 ... J PACKAGE
SN74HC356 .•. J OR N PACKAGE
(TOP VIEW)
07
06
05
04
03
02
01
00
elK
GNO
o Dependable Texas Instruments Quality and
Reliability
Vee
y
W
G3
<32
<31
50
51
52
5e
description
These monolithic data selectors/multiplexers
contain full on-chip binary decoding to select one
of eight data sources. The data-select address
is stored in transparent latches that are enabled
by a low level on pin 11, SC. The edge-triggered
data registers are clocked by a low-to·high
transition on pin 9, ClK. Both true and
complementary outputs are available.
TheSN54HC356 is characterized for operation
over the full military temperature range of
- 55 °C to 125 ac. The SN74HC356 is
characterized for operation from - 40 °C to
85°C.
SN54HC356 ... FH OR FK PACKAGE
SN74HC356 •.. FH OR FN PACKAGE
(TOP VIEW)
LOtOt--
(J
(J
000»
04
03
02
01
00
W
G3
G2
II
<31
50
:2
o
i=
logic symbol
C
CLK
DO
0
<
:t>
02
(6)
(19)
2
0
m
y
(5)
03
2
"T1
0
:0
(4)
04
(18)
S
:t>
::!
0
2
05
(3)
06
(2)
(1)
07
4-48
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
w
TYPES SN54HC356, SN14HC356
B·L1NE TO 1·L1NE DATA SELECTORS/MULTIPLEXERS/
EDGE·TRIGGERED REGISTERS WITH 3·STATE OUTPUTS
FUNCTION TABLE
INPUTS
OUTPUT
SELECTt
S2
CLOCK
OUTPUTS
ENABLES
H
DO
H
H
DOn
01
DOn
01
L
H
L
L
H
H
01n
02
Dln
02
L
H
D2n
03
D2n
03
03 n
04
03 n
H
L
H
04 n
04 n
L
L
H
H
05
05 n
06
05 n
06
SO
G1
G2
G3
X
X
X
X
X
H
X
X
H
X
X
X
X
X
X
L
L
L
X
t
X
L
L
L
L
L
H
H or L
L
L
L
L
L
t
L
H
L
L
H
H
H or L
L
L
L
H
L
L
H
H or L
t
L
L
L
L
t
L
L
H
H
H
H or L
L
L
H
L
L
t
L
L
H
H
L
H or L
L
L
L
H
H
L
L
L
H
H
H
L
L
H
H
H
H
H
H
H
H
t
H or L
t
Y
Z
Z
Z
W
Z
Z
Z
DO
S1
X
X
X
04
05
L
L
H
H or L
L
L
H
L
L
H
06 n
07
06 n
t
H or L
L
L
H
07 n
07 n
07
II
tThis column shows the input address setup with SC low.
z
o
maximum ratings, recommended operating conditions, and electrical characteristics
i=
See Table III, page 2-8.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
2V
tsu
Setup time, data before CLKt
4.5 V
6V
th
Hold time, data after CLKt
2V
4.5 V
6V
TA = 25°C
MIN
MAX
SN54HC356
MIN
MAX
SN74HC356
MIN
75
15
115
23
95
19
13
5
20
16
5
5
5
5
5
5
5
5
MAX
UNIT
ns
cd:
~
a:
o
LL
Z
W
(.)
ns
Z
cd:
>
C
cd:
-I!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-49
TYPES SN54HC356, SN74HC356
B·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS/
EDGE·TRIGGERED REGISTERS WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL a 50 pF (see Note 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
2V
95
4.5 V
6V
31
26
2V
85
W
4.5 V
28
6V
24
elK
50,51,
52
W
y
tpd
SC,
W
II
Y
ten
01,02
W
l>
C
<
l>
Y
2
tdis
o
m
01,132
-2
W
o
Y
."
:lJ
ten
S
G3
W
l>
~
o
y
2
tdis
=
TA
25°C
TYP MAX
MIN
y
y
tpd
VCC
G3
W
2V
100
4.5 V
32
6V
2V
27
90
4.5 V
30
26
6V
2V
80
4.5 V
26
6V
2V
22
80
4.5 V
6V
26
22
2V
75
4.5 V
24
6V
2V
20
75
4.5 V
24
6V
2V
20
45
4.5 V
15
6V
2V
13
45
4.5 V
15
6V
13
2V
75
4.5 V
24
6V
20
75
2V
4.5 V
6V
SN54HC356
MIN
SN74HC356
MAX
MIN
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
24
20
2V
4.5 V
50
17
6V
15
2V
4.5 V
50
17
6V
15
ns
ns
40 pF typ
Power dissipation capacitance
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
4-50
MAX
TEXAS
"'!1
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS. TeXAS 75265
HIGH-SPEED
CMOS LOGIC
TYPES SN54HCT373, SN74HCT373
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
02804, MARCH 1984
•
SN54HCT373 ... J PACKAGE
SN74HCT373 ••. J OR N PACKAGE
Inputs are TTL-Voltage Compatible
•
8 High-Current Latches in a Single Package
•
High-Current 3-State True Outputs Can
Drive up to 15 LSTTL Loads
(TOP VIEW)
oe
•
Full Parallel Access for Loading
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
Vee
1Q
10
20
2Q
3Q
3D
40
4Q
GNO
8Q
80
70
7Q
6Q
60
50
5Q
e
description
SN54HCT373 ... FH OR FK PACKAGE
SN74HCT373 ... FH OR FN PACKAGE
These 8-bit latches feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
(TOP VIEW)
u
ooJuuo
~ ~IO
3
>
80
70
7Q
6Q
60
II
9 10 11 1213
2:
oouoo
'
~
FUNCTION TABLE (EACH LATCH)
OUTPUT
INPUTS
This document contains information
on a new product. Specifications are
subject to change without notice.
ex>
1 2019
20
2Q
3Q
3D
40
The eight latches of the 'HCT373 are
transparent D-type latches. While the enable (C)
is high the Q outputs will follow the data (D)
inputs. When the enable is taken low, the Q
outputs will be latched at the levels that were
set up at the D inputs.
An output-control input (OC) can be used to
place the eight outputs in either a normal logic
state (high or low logic levels) or a highimpedance state. In the high-impedance state
the outputs neither load nor drive the bus lines
significantly. The high-impedance third state and
increased drive provide the capability to drive the
bus lines in a bus-organized system without need
for interface or pull-up components.
2
OC
ENABLE C
0
Q
L
H
H
H
L
H
L
L
L
L
X
H
X
X
00
Z
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
Copyright © 1984, Texas Instruments Incorporated
4-51
TYPES SN54HCT373, SN74HCT373
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
logic diagram (positive logic)
oc
111
10 131
20 141
3~. 171
40 181
II
50 1131
l>
60 1141
C
<
l>
z
70 1171
(')
m
2:
o
:u
."
3:
l>
80 1181
maximum ratings, recommended operating conditions, and electrical characteristics
-I
oZ
4-52
See Table VII, page 2-14.
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
31
TYPES SN54HCT373, SN74HCT373
OCTAL O·TYPE TRANSPARENT LATCHES WITH 3·STATE OUTPUTS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
VCC
4.5 V
Pulse duration. enable C high
tw
Setup time. data before enable C ~
tsu
Hold time. data after enable C.j.
th
TA = 25°C
MIN
MAX
SN54HCT373
MIN
20
sN74HCT373
MAX
MIN
30
27
25
13
12
5.5 V
17
4.5 V
10
5.5 V
9
15
14
4.5 V
5
5
5
5.5 V
5
5
5
MAX
UNIT
ns
23
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
D
Q
tpd
ten
tdis
C
DC
DC
Any Q
Any Q
Any Q
Any
tt
VCC
TA = 25°C
MIN
TVP MAX
sN54HCT373
MIN
MAX
53
48
4.5 V
25
35
5.5 V
21
32
4.5 V
28
35
sN74HCT373
MIN
MAX
44
40
44
5.5 V
25
32
53
48
4.5 V
26
35
53
40
44
5.5 V
23
32
48
40
4.5 V
5.5 V
23
35
44
22
4.5 V
10
32
12
53
48
5.5 V
9
11
Power dissipation capacitance per latch
40
18
15
16
14
No load. TA = 25°C
UNIT
ns
ns
ns
ns
II
ns
50 pF typ
z
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
,
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
D
Q
tpd
C
Any Q
ten
DC
Any Q
tt
Any
~
ns
o
u.
sN74HCT373
MIN
TVP MAX
52
79
65
27
47
71
59
38
36
52
47
79
71
65
59
ns
4.5 V
5.5 V
33
28
52
47
79
71
65
59
ns
4.5 V
18
42
53
5.5 V
16
38
63
57
TA = 25°C
MIN
TVP MAX
4.5 V
32
5.5 V
4.5 V
5.5 V
NOTE 1: For load circuit and voltage waveforms. see page 1- 14.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
48
i=
c
C
<
l>
2
o
m
2
-n
o
:D
s:
l>
(5
-I
2
4-54
.
TEXAS
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HCT374, SN74HCT374
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS
WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02804, MARCH 1984
SN54HCT374 ••• J PACKAGE
SN74HCT374 •.• J OR N PACKAGE
•
Inputs Are TTL-Voltage Compatible
•
8 D-Type Flip-Flops in a Single Package
•
High-Current 3-State True Outputs Can
Drive Up to 1 5 LSTTL Loads
•
Full Parallel Access for Loading
•
Package Options Include Both Plastic
and Ceramic Chip Carriers in Addition to
Plastic and Ceramic DIPs
•
Dependable Texas Instruments Quality
and Reliability
(TOP VIEW)
oe
Vee
10
10
20
20
30
3D
40
40
80
80
70
70
60
60
50
50
elK
GNO
description
SN54HCT374 ... FH OR FK PACKAGE
SN74HCT374 •.. FH OR FN PACKAGE
These 8-bit flip-flops feature three-state outputs designed specifically for driving highly
capacitive or relatively low-impedance loads.
They are particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
(TOP VIEW)
0IUe >co
go
......
C
3
20
20
30
3D
40
The eight flip-flops of the 'HCT374 are edgetriggered Ootype flip-flops. On the positive transition of the clock the Q outputs will be set to
the logic levels that were set up at the 0 inputs.
80
70
70
60
60
II
z
An output-control input can be used to place
the eight outputs in either a normal logic state
(high or low logic levels) or a high-impedance
state. In the high-impedance state the outputs
neither load nor drive the bus lines significantly.
The high-impedance third state and increased
drive provide the capability to drive the bus
lines in a bus-organized system without need
for interface or pull-up components.
The output control (OC) does not affect the internal operation of the flip-flops. Old data can
be retained or new data can be entered while
the outputs are in the high-impedance state.
2 1
4
o
i=
C
logic symbol
The SN54HCT374 is characterized for operation over the full military temperature range of
- 55°C to 125°C. The SN74HCT374 is
characterized for operation from - 40°C to
85°C.
o
<
l>
2
om
2
."
ojJ
s:
l>
::!
o
2
4-56
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3£
TYPES SN54HCT374, SN74HCT374
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS
WITH 3·STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table VII, page 2-14.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
vcc
fclock Clock frequency
tw
Pulse duration, ClK high or low
tsu
Setup time, data before ClK i
Hold time, data after ClK i
th
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
V
V
V
V
V
V
V
TA - 25"C
MIN
MAX
0
0
16
14
20
17
31
36
5
5
SN54HCT374
MAX
MIN
0
0
24
22
30
27
5
5
21
23
SN74HCT374
MIN
MAX
0
25
0
28
20
18
25
23
5
5
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
tpd
ClK
Any
ten
OC
Any
tdis
OC
Any
Any
tt
Vcc
V
V
V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5
5.5
4.5
TA = 25"C
TYP
36
40
30
MIN
31
36
MAX
SN54HCT374
MAX
SN74HCT374
MIN
MAX
25
28
54
45
48
45
41
45
41
18
16
41
38
34
MIN
21
23
25
26
23
23
22
10
9
38
34
15
14
UNIT
MHz
II
ns
ns
2
o
ns
i=
C
~
2 1 2019
40
10
lC.2C
40
NC
NC
20
3C.4C
20
30
II
9 1011 1213
00
U
Old
NZZMM
z
(!)
The SN54HC375 is characterized for operation
over the full military temperature range of
- 55 °C to 125°C. The SN74HC375 is
characterized for operation from - 40 °C to
85°C.
o
NC-No internal connection
t=
C
3'0
o
<
:t>
(')
PARAMETER
tt
C
TO
Qor
Q
Any
Vcc
TA = 25°C
MIN
TYP MAX
MAX
MIN
MAX
2V
40
120
180
150
4.5 V
14
24
36
30
6V
11
20
31
26
2V
42
130
195
165
4.5 V
15
26
39
33
6V
12
22
33
28
2V
38
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
m
-
2
-n
o
::c
~
:t>
-I
(5
2
4-60
SN74HC375
SN54HC375
MIN
-I!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
UNIT
ns
ns
ns
TYPES SN54HC533, SN74HC533
HIGH·SPEED
CMOS LOGIC
OCTALD~YPETRANSPARENTLATCHES
WITH 3·STATE OUTPUTS
02684. DECEM8ER 1982-REVISED MARCH 1984
SN54HC533 ••• J PACKAGE
SN74HC533 ••• J OR N PACKAGE
•
8 Latches in a Single Package
•
High·Current 3-State Inverting Outputs
Can Drive up to 15 LSTTL Loads
(TOP VIEW)
•
Full Parallel Access for Loading
•
Package Options Include Both Plastic
and Ceramic Chip Carriers in Addition to
Plastic and Ceramic DIPs
•
Dependable Texas Instruments Quality
and Reliability
description
These 8-bit latches feature three-state outputs designed specifically for driving highly
capacitive or relatively low-impedance loads.
They are particularly suitable for implementing
buffer registers, 1/0 ports, bidirectional bus
drivers, and working registers.
Vee
10
10
20
20
30
3D
40
40
GNO
80
80
70
70
60
60
50
50
e
SN54HC533 •.. FH OR FK PACKAGE
SN74HC533 ••• FH OR FN PACKAGE
(TOP VIEW)
Q Ie ICJ tlle
......
0:> co
The eight latches of the 'HC533 are transparent Ootype latches. While the enable (C) is
high, the IT outputs will follow the complements of the 0 inputs. When the enable is
taken low, the 5 outputs will be latched at the
inverses of the levels that were set up at the 0
inputs. The 'HC533 is functionally equivalent
to the 'HC373 except for having inverted outputs.
An output-control (OC) input can be used to
place the eight outputs in either a normal logic
state (high or low logic levels) or a highimpedance ;;tate. In the high-impedance state
the outputs neither load nor drive the bus lines
significantly. The high-impedance third state
and increased drive provide the capability to
drive the bus lines in a bus-organized system
without need for interface or pull-up components.
oe
20
20
30
3D
40
80
70
70
60
60
4
Ie
Q
'lt2
"
CJ 10
II
z
o
Q
1010
i=
«
:2E
FUNCTION TABLE (EACH LATCH)
INPUTS
oc
ENABLE C
D
a
H
L
H
L
H
L
H
L
L
H
x
a:
OUTPUT
X
X
ou.
-w
L
Z
aD
z
(.)
z
«
>
c
«
The output control does not affect the internal
operation of the latches. Old data can be retained or new data can be entered while the
outputs are off.
The SN54HC533 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC533 is characterized for operation from -40°C to 85°C.
ADVANCE INFORMATION
This document contains information
on a new product. Specifications are
subject to change without notice.
-1!1
INSTRUMENTS
Copyright © 1982 by Texas Instruments Incorporated
TEXAS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-61
TYPES SN54HC533, SN74HC533
OCTAL O·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
logic symbol
logic diagram (positive logic)
11)
OC----a
10
20
3D
1Q
1 D -----+--1
14)
2D----+--I
3D
4D
II»
5D
171
18)
113)
C
<
»
:2
0
114)
60
m
2:
."
0
7D
117)
::D
~
»
-I
8D
(5
118)
:2
4-62
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC533, SN74HC533
OCTAL O·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
timing requirements over recommended operating free·air temperature range (unless otherwise
noted)
vcc
tw
tsu
th
Pulse duration, enable C high
Setup time, data before
enable C ~
Hold time, data after enable C ~
2V
4.5 V
BV
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MAX
MIN
SN54HC533
MIN
MAX
120
24
20
75
15
13
5
5
5
80
16
14
50
10
9
5
5
5
SN74HC533
MIN
MAX
100
20
17
63
13
11
5
5
5
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tpd
ten
tdis
tt
FROM
(INPUT)
0
C
OC
OC
TO
(OUTPUT)
IT
Any
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
Any
4.5 V
Any
6V
2V
4.5 V
Any
6V
2V
4.5 V
6V
TA = 25°C
MIN
TYP
77
26
23
87
27
23
68
24
21
47
23
21
28
8
6
MAX
175
35
30
175
35
30
150
30
SN54HC533
MIN
MAX
265
53
45
265
53
45
225
45
2S
150
30
26
60
12
10
Power dissipation capacitance per latch
NOTE 1: For load circuits and voltage waveforms, see page 1-14.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
38
225
45
38
90
18
15
SN74HC533
MIN
MAX
220
44
UNIT
ns
38
220
44
ns
38
190
38
32
ns
75
15
13
50 pF typ
o
i=
«
~
190
38
32
II
z
ns
a:
oLL
Z
ns
W
(.)
z
«
c>
«
4-63
TYPES SN54HC533, SN14HC533
OCTAL O·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
0
Q
tpd
C
Any
ten
OC
Any
PARAMETER
Any
tt
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA
MIN
25°C
TVP MAX
95
200
33
40
21
34
103
225
45
33
29
38
85
200
40
29
26
34
60
210
17
42
14
36
a
SN54HC533
MIN
MAX
300
60
51
335
67
37
300
60
31
315
63
33
SN74HC533
MIN
MAX
250
50
43
285
57
48
250
50
43
265
53
45
UNIT
ns
ns
ns
ns
NOTE 1: For load circuits and voltage waveforms. see page 1·14.
o latch signal conventions
II
l>
c
<
l>
It is TI practice to name the outputs and other inputs of a Ootype latch and to draw its logic symbol based
on the assumption of true data (0) inputs. Then outputs that produce data in phase with the data inputs
are called a and those producing complementary data are called O. An input that causes a a output to go
high or a output to go low is called Preset; an input that causes a 0 output to go high or a a output to go
low is called Clear. Bars are used over these pin names (PRE and CLR) if they are active-low.
a
In some applications it may be advantageous to redesignate the data input D. In that case all the other inputs and outputs should be renamed as shown below. Also shown are corresponding changes in the
graphical symbol. Arbitrary pin numbers are shown in parentheses.
2
o
m
-2
~
o
:D
3:
l>
::j
o
2
4-64
a
Notice that a and exchange names, which causes Preset and Clear to do likewise. Also notice that the
polarity indicators ( t:::::::,. ) on PRE and CLR remain since these inputs are still active·low, but that the
presence or absence of the polarity indicator changes at '0, a. and O. Of course pin 5 (a) is still in phase
with the data input '0, but now both are considered active-low.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HCT533, SN74HCT533
HIGH·SPEED
CMOS LOGIC
OCTALD~YPETRANSPARENTLATCHES
WITH 3·STATE OUTPUTS
02804. MARCH 1984
•
SN54HCT533 ••. J PACKAGE
SN74HCT533 •.• J OR N PACKAGE
Inputs Are TTL-Voltage Compatible
o 8 Latches in a Single Package
(TOP VIEW)
o High-Current 3-State Inverting Outputs
Can Drive up to 15 LSTTL Loads
o
Full Parallel Access for Loading
41)
Package Options Include Both Plastic
and Ceramic Chip Carriers in Addition to
Plastic and Ceramic DIPs
o Dependable Texas Instruments Quality
and Reliability
oe
Vee
10
10
20
20
30
3D
40
4Q
80
80
70
70
60
60
50
50
e
GNO
description
These a-bit latches feature three-state outputs designed specifically for driving highly
capacitive or relatively low-impedance loads.
They are particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
SN54HCT533 ..• FH OR FK PACKAGE
SN74HCT533 ••• FH OR FN PACKAGE
(TOP VIEW)
Q 10 ICJ 810
....... 0::> CX)
An output-control (OC) input can be used to
place the eight outputs in either a normal logic
state (high or low logic levels) or a highimpedance state. In the high-impedance state
the outputs neither load nor drive the bus lines
significantly. The high-impedance third state
and increased drive provide the capability to
drive the bus lines in a bus-organized system
without need for interface or pull-up components.
80
70
20
30
3D
40
The eight latches of the 'HCT533 are transparent Ootype latches. While the enable (C) is
high, the Q outputs will follow the complements of the 0 inputs. When the enable is
taken low, the Q outputs will be latched at the
inverses of the levels that were set up at the 0
inputs. The 'HCT533 is functionally equivalent
to the 'HCT373 except for having inverted outputs.
to
II
6a
60
10
Q
'l:tZ
CJ 10
z
'0
Q
Inln
c.:l
i=
«
FUNCTION TABLE (EACH LATCH)
INPUTS
~
IX
OUTPUT
OC
ENABLE C
D
0
L
H
H
L
oLL
L
H
L
Z
00
H
X
L
X
X
H
L
W
(.)
Z
z
«
>
c
«
The output control does not affect the internal
operation of the latches. Old data can be retained or new data can be entered while the
outputs are off.
The SN54HCT533 is characterized for operation over"the full military temperature range of
- 55°C to 125°C. The SN74HCT533 is characterized for operation from - 40°C to a 5°C.
ADVANCE INFORMATION
This document contains information
on a new product. Specifications are
subject to change without notice.
Copyright © 1984 by Texas Instruments Incorporated
TEXAS . .
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-65
TYPES SN54HCT533, SN74HCT533
OCTAL O·TYPE TRANSPARENT LATCHES
WITH 3·STATE OUTPUTS
logic symbol
logic diagram (positive logic)
-
(1)
OC------
Q
«
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265
4-69
TYPES SN54HC534, SN74HC534
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS
WITH 3·STATE OUTPUTS
logic symbol
logic diagram (positive logic)
II>
0
20
(4)
<
30 (7)
(")
40 (8)
>
:2
m
:2
."
0
50
(13)
:a
3:
>
60 (14}
::!
0
:2
70
80
4-70
(17)
(18)
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC534. SN74HC534
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS
WITH 3·STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time, data before ClK t
th
Hold time, data after ClK t
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
I
elK high", low
TA = 25°C
MIN
MAX
0
0
0
80
16
14
100
20
17
5
5
5
6
31
36
SN54HC534
MIN
MAX
4.2
0
21
0
25
0
120
24
20
150
30
26
5
5
5
SN74HC534
UNIT
MIN
MAX
5
0
25 MHz
0
29
0
100
20
ns
17
125
25
ns
21
5
5
5
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50, pF (see Note 1)
-
PARAMETER
FROM
(INPUT)
TO
(OUTPUTI
tpd
ClK
Any
ten
OC
Any
tt
Cpd
TA = 25°C
MIN
TYP MAX
2V
4.5 V
f max
tdis
Vee
OC
Any
Any
6
31
36
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
11
36
40
SN54HC534
MAX
MIN
4.2
21
25
SN74HC534
MIN
MAX
5
25
29
88
28
24
180
36
31
270
54
46
225
45
38
77
26
23
51
150
30
26
150
225
45
25
23
28
8
6
30
26
45
38
90
18
190
38
32
190
38
32
75
15
15
13
60
12
10
38
225
100 pF typ
Power dissipation per flip-flop
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 .; DALLAS. TEXAS 75265
UNIT
MHz
ns
ns
II
2
o
i=
C
IC!)
The three-state control gate is a 2-input NOR
such that if either G 1 or G2 is high, all eight
outputs are in the high-impedance state.
A3
A4
The 'HC540 provides inverted data and the
'HC541 provides true data at the outputs.
A6
A7
A5
Y1
Y2
Y3
Y4
Y5
2:
The SN54HC540 and SN54HC541 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN7HC540 and SN74HC541 are characterized
for operation from - 40°C to 85 °C.
o
i=
~
~
a:
oLL
~
W
CJ
2:
~
>
C
~
ADVANCE INFORMATION
This document contains information
on a new product. Specifications are
subject to change without notice.
'1!1
INSTRUMENTS
TEXAS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
Copyright © 1984. Texas instruments Incorporated
4-73
TYPES SN54HC540, SN54HC541
SN74HC540, SN74HC541
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
logic symbols
'HC541
'HC540
A1
A2
A3
A4
A5
A6
A7
A8
(9)
logic diagrams (positive logic)
'HC540
G1
G2
II
'HC541
(1)
(19)
(1 )
(19)
G1
G2
(2)
(18)
(2)
(18)
V1
A1
l>
A2 (3)
(17)
V2
A2 (3)
(17)
<
l>
A3 (4)
(16)
A3
(4)
(16)
0
m
:-2
A4 (5)
(15)
A4
(5)
(15)
0
."
A5 (6)
(14)
A5 (6)
(14)
A6 (7)
(13)
A6
(7)
(13)
A7 (8)
(12)
(8)
(12)
A8 (9)
(11)
A1
C
:2
V3
V4
V5
V1
V2
V3
V4
V5
::D
s:
l>
::i
0
V6
:2
V7
A7
V8
A8
(9)
(11 )
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
4-74
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
V6
V7
V8
TYPES SN54HC540, SN74HC540
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
'HC540 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 5.0 pF (see Note 1)
PARAMETER
tpd
ten
tdis
FROM
(INPUT)
A
IT
G
TO
(OUTPUT)
Y
y
y
Y
tt
vCC
TA = 25°C
MIN
TYP MAX
2V
50
4.5 V
10
6V
9
2V
75
4.5 V
15
6V
13
2V
40
4.5 V
18
6V
17
2V
28
4.5 V
8
6V
6
Power dissipation capacitance
SN54HC540
MIN
MAX
SN74HC540
MIN
MAX
UNIT
ns
ns
ns
ns
No load, TA = 25°C
35 pF typ
'HC540 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 150 pF (see Note 1)
PARAMETER
tpd
ten
tt
FROM
TO
(INPUT)
(OUTPUT)
A
G
Y
y
Y
VCC
TA = 25°C
MIN
TYP MAX
2V
4.5 V
SN54HC540
MIN
MAX
SN74HC540
MIN
MAX
UNIT
75
15
6V
13
2V
100
4.5 V
20
6V
17
2V
45
4.5 V
17
6V
13
ns
II
2
o
i=
2
ns
«
ns
ou.
a::
2
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
w
(.)
2
«
>
c
«
TEXAS
~
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS. TeXAS 75265
4-75
TYPES SN54HC541, SN74HC541
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
'HC541 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA = 25°C
MIN
TYP MAX
2V
tpd
A
6V
2V
ten
tdis
IT
IT
tt
SN74HC541
MIN
MAX
UNIT
ns
11
4.5 V
80
, 17
6V
15
2V
4.5 V
40
y
17
28
Y
6V
2V
4.5 V
y
MAX
55
12
4.5 V
Y
SN54HC541
MIN
ns
ns
18
ns
8
6
6V
35 pF typ
Power dissipation capacitance
'HC541 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 150 pF (see Note 1)
II»
FROM
(INPUT)
TO
(OUTPUT)
VCC
tpd
A
Y
4.5 V
TA = 25°C
MIN
TYP MAX
2V
ten
»
:2
om
tt
IT
y
Y
SN54HC541
MIN
75
16
14
6V
2V
c
<
:2
PARAMETER
4.5 V
100
20
6V
17
2V
45
4.5 V
6V
17
13
NOTE 1: For load circuit a'nd voltage waveforms. see page 1-14.
"T1
o
::xJ
s:
»
::!
o
:2
4-76
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
MAX
SN74HC541
MIN
MAX
UNIT
ns
ns
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HCT540, SN54HCT541
Sru74HCT540, SN74HCT541
OCTAL BUFFERS ArdD UrJE DRIVERS WITH 3·STATE OUTPUTS
D2804, MARCH 1984
SN54HCT54~SN54HCT541 ... JPACKAGE
SN74HCT540, SN74HCT541 ... J OR N PACKAGE
•
Inputs are TTL·Voltage Compatible
•
High·Current 3·State Outputs Interface
Directly with System Bus or Can Drive up
to 1 5 LSTTL Loads
o
Data Flow· Thru Pinout (All Inputs on
Opposite Side from Outputs)
o
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
(TOP VIEW)
Vee
<31
A1
A2
A3
A4
A5
A6
A7
A8
GND
<32
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
description
These octal buffers and line drivers are designed
to have the performance of the popular
SN54HCT240/SN74HCT240 series and. at the
same time. offer a pinout with inputs and
outputs on opposite sides of the package. This
arrangement greatly enhances printed circuit
board layout.
SN54HCT540, SN54HCT541 ... FIl OR FK PACKAGE
SN74HCT540,SN74HCT541 ... FH OR FN PACKAGE
(TOP VIEW)
N
~
~
U
UN
c
«
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _............._Il3IZl""""............."""n=n-BI.2TC::rm::rm:~2
4
ADVANCE INFORMATION
This document contains information
on a new product. Specifications are
subject to change without notice.
~~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
1I!7!17:!mS"f'TTT
Copyright © 1984, Texas Instruments Incorporated
4-77
,TYPES SN54HCT540, SN54HCT541
SN74HCT540, SN74HCT541
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
logic symbols
'HCT540
'HCT541
&
A1
A1
A2
A2
A3
A3
(18) Y1
(17) Y2
(16) Y3
(15) Y4
A4
(14) YS
,AS
(13) Y6
A6
(12) Y7
A7
(9)
A8
(11) Y8
logic diagrams (positive logic)
'HCT540
G1
G2
II
'HCT541
( 1)
(19)
(1)
(19)
Q"1
G2
121
1181
Y1
A1
121
1181
C
A2 (31
(17)
Y2
A2 (31
1171
:2
A3 (4)
1161
A3
(41
1161
A4 151
1151
A4
(51
(151
A5 161
1141
AS (61
1141
A6 171
(131
A6
(7)
1131
A7 181
1121
181
1121
A8 (91
( 111
191
1111
A1
l>
<
l>
0
Y3
Y1
Y2
Y3
m
:2
Y4
Y4
."
0
:D
S
l>
:::!
Y5
Y6
Y5
Y6
0
:2
Y7
A7
Y8
A8
Y7
Y8
maximum ratings, recommended operating conditions, and electrical characteristics
See Table VII, page 2-14.
4-78
TEXAS
"'J}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
31
TYPES SN54HCT540, SN74HCT540
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
'HCT540 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
G
y
tdis
y
G
Y
tt
vcc
TA = 25°C
MIN
TVP MAX
4.5 V
13
5.5 V
4.5 V
12
21
5.5 V
19
4.5 V
19
5.5 V
18
4.5 V
8
7
5.5 V
SN54HCT540
MIN
MAX
SN74HCT540
MIN
MAX
UNIT
ns
ns
ns
ns
Power dissipation capacitance
35 pF typ
'HCT540 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
vcc
4.5 V
5.5 V
20
19
4.5 V
26
5.5 V
25
17
14
tpd
A
Y
ten
G
y
tt
Y
TA = 25°C
MIN
TVP MAX
4.5 V
5.5 V
SN54HCT540
MIN
MAX
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
SN74HCT540
MIN
MAX
UNIT
ns
ns
ns
II
;2
o
i=
C
FROM
(INPUT)
Y
Vec
TA = 25°C
MIN
TYP MAX
4.5 V
20
5.5 V
19
4.5 V
26
5.5 V
25
4.5 V
17
5.5 V
14
SN54HCT541
MIN
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
C
<
l>
2
o
m
2
-n
o
:lJ
S
»
::::!
o
2
4-80
.
TEXAS
~
INSTRUMENTS
,POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
MAX
SN74HCT541
MIN
MAX
UNIT
ns
ns
ns
TYPES SN54HC589, SN74HC589
8-BIT SHIFT REGISTERS WITH INPUT LATCHES
AND 3-STATE OUTPUTS
HIGH-SPEED
CMOS LOGIC
02804, MARCH 1984
SN54HC589 . , . J PACKAGE
SN74HC589 . , . J OR N PACKAGE
•
a-Bit Parallel Storage Inputs
•
Parallel 3-State I/O Storage Register Inputs,
Shift Register Output
•
High-Current 3-State Output Can Drive Up
to 15 LSTTL Loads
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
(TOP VIEW)
B
VCC
C
D
E
A
G
SER
SRLOAD
RCK
SRCK
H
G
F
Dependable Texas Instruments Quality and
Reliability
GND
OH'
SN54HC589 ... FH OR FK PACKAGE
SN74HC589 ... FH OR FN PACKAGE
description
The 'HC589 is similar to 'HC598 but has a threestate output whose control input replaces the
direct 'clear input for the shift register. Like
'HC598, 'HC589 consists of an 8-bit storage
register feeding a parallel-in, serial-out 8-bit shift
register. Parallel loading of the storage register
takes place on the positive-going edge of the
RCK signal. If SRLOAD is low, data from the
storage register is loaded into the shift register
on the positive edge of the SRCK signal. If
SRLOAD is high, data in the storage register is
shifted one bit with new data entering serially
at SER.
If the output enable IT is high, the output is in
the high-impedance state, but this does not
affect loading, transfer of data from storage, or
shifting.
(TOP VIEW)
U
U U
UCIlZ>
c
«
Pin numbers shown are for J and N packages.
ADVANCE INFORMATION
This document contains Information
on a new product. Specifications are
subject to change without notice.
TEXAS
~
INSTRUMENTS
POST OFFtCE BOX 225012 • DALLAS. TEXAS 75265
Copyright © 1984, Texas Instruments Incorporated
4-81
TYPES SN54HC589. SN74HC589
8·BIT SHIFT REGISTERS WITH INPUT LATCHES
AND 3·STATE OUTPUTS
logic diagram (positive logic)
G
(10)
SRCK -,"(1_1.;....)- - - - - - - - - 1
A
~~_-,
(15)
B (1)
II
C
(2)
o
(3)
l>
C
E (4)
<
l>
2:
(')
m
F
(5)
G
(6)
2:
"T1
o
::c
s:
l>
::j
o
2:
H (7)
Pin numbers shown are for J and N packages.
4-82
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC589, SN74HC589
8·BIT SHIFT REGISTERS WITH INPUT LATCHES
AND 3·STATE OUTPUTS
typical load and shift sequence
SRCK
,
SER..,....____________
G
SRLOAD
I
~I~----------------------~------------~I
I
I...
,
I
I
-----J
I
Ii
U'I
:
rl~------------------~
I I
I
n!: n I:
n
II
17:1"
I
-l:-LflHl:
--JI
U
II
RCK
B
I
I
i
IL : ilL
1h I
In. .__
'I
II
I :
ilL
IlL
:
I
I
1,IIL
l
I
,I
...-tll+l_____
L
I
A
li
Ii~,_______
----~II
I
I
I
I
II
2
o
i=
~
II
I
H~I
II I I
I
I
4SERIAL
1
IH
I
1,...1_--:-;
High-Impedance
I 1
"
IH
HI
SHIFT~I
~ORAGE
LOAD
REGISTER
I
L
HI
I
14
AND SHIFT REGISTER
H
L
IH
I
1
L
I
L
L
I
~I, ~ SERIAL SHIFT~I
SERIAL SHIF,T
tpARALLEL LOAD
SHIFT REGISTER
CLEAR STORAGE REGISTER
L
PARALLEL LOAD
SHIFT REGISTER
LOAD STORAGE
REGISTER
H
I
t
I
14
•
SERIAL SHIFT
PARALLEL LOAD BOTH
STORAGE REGISTER
AND SHIFT REGISTER
maximum ratings, recommended operating conditions, and electrical characteristics
:2:
a:
ou..
2
w
(.)
2
~
>
C
~
See Table III, page 2-8.
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-83
TYPES SN54HC589, SN74HC589
8·BIT SHIFT REGISTERS WITH INPUT LATCHES
AND 3·STATE OUTPUTS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
VCC
2V
Shift clock frequency
fclock
4.5 V
6V
Pulse duration, RCK or SRCK high or
low, or SRLOAD low
tw
A thru H before RCK t
Setup time
tsu
SER data
or SRt'5Ao
before SRCK t
A thru H after RCK t
Hold time
th
II
SER data
or SR'i:OAo
after SRCK t
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
0
0
0
80
16
14
100
6
31
36
SN54HC589
MIN
MAX
0
5
0
25
29
SN74HC589
MIN
MAX
UNIT
4.2
21
25
MHz
0
0
0
120
24
20
17
0
100
20
17
126
25
21
100
20
17
126
25
21
25
32
30
25
149
30
25
37
5
4
5
5
6
5
5
5
7
6
5
5
5
5
5
ns
20
149
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
l>
C
f max
<
l>
:2
SRCK
tpd
RCK
°H'
tpd
SRCK
°H'
o
s:
tpd
SRLOAD
°H'
-I
ten
G
Ow
o
m
2
'T1
:c
l>
o:2
tdis
tt
G
°H'
Any
VCC
TA = 25°C
MIN TYP MAX
2V
4.5 V
6
31
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
36
72
21
18
88
18
15
88
18
15
75
15
13
75
15
13
28
8
6
6V
SN54CH589
MIN
MAX
5
25
29
SN74HC589
MAX
MIN
4.2
21
25
265
313
63
53
261
52
44
261
52
44
224
45
210
42
36
175
35
30
175
35
30
150
30
26
150
30
26
60
12
10
53
45
221
44
37
221
44
37
189
38
32
189
38
32
75
15
38
224
45
38
90
18
13
15
UNIT
MHz
ns
ns
ns
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
4-84
-III
INSTRUMENTS
TEXAS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3!
TYPES SN54HC589. SN74HC589
8·BIT SHIFT REGISTERS WITH INPUT LATCHES'
AND 3·STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL
150 pF (see Note 1)
=
PARAMETER
tpd
tpd
tpd
FROM
(INPUT)
RCK
SRCK
SRLOAD
TO
(OUTPUT)
Ow
°H'
Ow
TA = 25°C
MIN
MAX
SN54HC589
MIN
MAX
SN74HC589
MAX
MIN
2V
260
328
387
4.5 V
6V
52
44
2V
4.5 V
225
45
6V
38
2V
225
45
284
335
57
67
38
48
4.5 V
200
40
252
50
57
298
6V
34
43
VCC
4.5 V
6V
2V
ten
G
Ow
66
77
56
284
66
335
57
67
48
57
60
UNIT
ns
ns
ns
ns
51
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
II
2:
o
i=
C
o
G
RCK
NC
CCKEN
II
CCK
Both the counter and register clocks are positiveedge triggered. If the user wishes to connect
both clocks together, the counter state will
always be one count ahead of the register.
Internal circuitry prevents clocking from the
clock enable.
The SN54HC590 is characterized for operation
over the full military temperature range of
- 55 DC to 1.25 DC. The SN74HC590 is
characterized for operation from - 40 DC to
85 D C.
Oc
lOla:
:I: 0 u
o~z~g
z
o
i=
NC-No internal connection
c:r:
~
logic symbol
a::
o
u.
-Zw
CTR8
CJ
Z
ICT= 255) Z4
c:r:
>
c
c:r:
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
ADVANCE INFORMATION
This document contains information
on a new product. Specifications are
subject to change without notice.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS ,75265
4·87
TYPES SN54HC590, SN74HC590
8·BIT BINARY COUNTERS
WITH 3·STATE OUTPUT REGISTERS
timing requirements over recommended operating free·air temperature range (unless otherwise noted)
fclock
2.6
0
3.2
0
13
0
16
0
16
0
19
0
20
24
CCK or RCK
high or low
125
190
155
4.5 V
25
38
6V
21
32
31
26
100
150
125
CCLR low
4.5 V
20
30
25
6V
17
2V
4.5 V
100
20
26
150
30
21
125
6V
17
26
21
2V
CCLR high (inactive)
before CCKt
(see Note 1)
l>
0
0
CLKt before RCKt
II
2V
SN74HC590
MIN
MAX
6V
2V
CCKEN low
~
MAX
SN54HC590
0
before CCKt
Setup time
MIN
4.5 V
Pulse duration
tsu
TA = 25°C
MIN
MAX
4
Clock frequency, CCK or RCK
tw
vcc
I
2V
100
150
125
20
30
25
6V
17
26
21
2V
4.5 V
200
40
300
60
250
50
6V
34
51
43
MHz
ns
ns
25
4.5 V
UNIT
ns
ns
ns
NOTE 1: This setup time ensures the register will see stable data from the counter outputs. The clocks may be tied together in which
case the register will be one clock pulse behind the counter.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted),
C
CL = 50
<
l>
z(')
PARAMETER
Z
tpd
f max
pF (see Note
FROM
(INPUT)
2)
TO
(OUTPUT)
CCK or RCK
m
CCKt
RCO
"TI
o
tpHL
:0
s:
CCLR
~
RCO
vCC
TA - 25°C
TYP MAX
MIN
2V
4
8
4.5 V
6V
20
24
35
40
l>
tpd
o
z
ten
RCi I(!)
1 2019
B1
B2
B3
B4
B5
4
5
6
7
8
II
9 1011 1213
2
cnocnr-.co
o
i=
«zalalal
(!)
The enable inputs can be used to disable the
device so that the buses are effectively isolated.
Q
OPERATION
GBA
L
a:
o
LL
C
<
'HCT623
GBA
GSA
GAB
GAS
>
2
0
m
A1
B1
A1
B1
A2
B2
A2
B2
2
"T1
0
::D
s:
>
:::!
0
2
TO OTHER SIX TRANSCEIVERS
TO OTHER SIX TRANSCEIVERS
4-90
-1.!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HCT620, SN54HCT623, SN74HCT620, SN74HCT623
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
/
maximum ratings, recommended operating conditions, and electrical characteristics
See Table VII, page 2-14.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
,
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
ten
GBA
A
tdis
GBA
A
ten
GAB
B
tdis
GAB
B
tt
A or B
I
SN54HCT620
SN54HCT623
TA" 25°C
vCC
MIN
MAX
5.5 V
13
11
21
18
32
27
26
23
ns
4.5 V
30
42
63
5.5 V
4.5 V
23
18
38
ns
5.5 V
16
30
28
57
45
53
48
42
38
35
ns
4.5 V
30
42
63
53
5.5 V
23
38
57
48
4.5 V
18
16
30
28
45
42
38
5.5 V
4.5 V
9
8
12
11
18
16
5.5 V
Power dissipation capacitance per transceiver
I
MAX
MIN
UNIT
TYP
4.5 V
MIN
SN74HCT620
SN74HCT623
MAX
35
15
14
No load, T A = 25°C
ns
ns
ns
40 pF typ
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
.
PARAMETER
tpd
ten
ten
tt
FROM
(INPUT)
TO
(OUTPUT)
VCC
A or B
B or A
GBA
GAB
A
B
A or B
SN54HCT620
TA" 25°C
MIN
SN74HCT620
SN74HCT623
SN54HCT623
MAX
4.5 V
5.5 V
18
38
58
11
34
52
4.5 V
36
30
59
53
89
80
36
59
89
67
74
30
53
80
67
17
14
42
63
38
57
53
48
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
MIN
MAX
MIN
UNIT
TYP
MAX
47
42
74
ns
ns
ns
ns
a
2:
o
i=
C
C
~
2
(")
m
:2
"T1
o
3:
::rJ
l>
-I
o2
4-92
TYPES SN54HC640, SN54HC643, SN54HC645
SN74HC640, SN74HC643, SN74HC645
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02684. DECEM8ER 1982-REVISED MARCH 1984
•
Choice of True or Inverting Logic
•
High-Current 3-State Outputs Can Drive up
to 15 LSTTL Loads
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
SN54HC' •.• J PACKAGE
SN74HC' ..• J OR N PACKAGE
(TOP VIEW)
OIR
A1
A2
A3
A4
A5
A6
A7
A8
Dependable Texas Instruments Quality and
Reliability
DEVICE
'HC640
LOGIC
Inverting
'HC643
'HC645
True and Inverting
True
GNO
Vee
G
81
82
83
84
85
86
87
88
SN54HC' •.. FH OR FK PACKAGE
SN74HC' •.• FH OR FN PACKAGE
(TOP VIEW)
description
These octal bus transceivers are designed for
asynchronous two-way communication
between data buses. The devices transmit data
from the A bus to the B bus or from the B bus
to the A bus depending upon the level at the
direction control (DIR) input. The enable input (G)
can be used to disable the device so the buses
are effectively isolated.
81
A4
A5
A6
A7
The
SN54HC640,
SN54HC643,
and
SN54HC645 are characterized for operation
over the full military temperature range of
- 55 °C to 125°C. The SN74HC640,
SN74HC643,
and
SN74HC645
are
characterized for operation from - 40°C to
85°C.
B2
II
83
84
85
:2
o
i=
C
'HC645
'HC643
'HC640
B4
B4
A5
B5
B6
A6
B6
A7
B7
A7
B7
AS
BS
AS
BS
A5
B5
A5
B5
A6
B6
A6
A7
B7
AS
BS
logic diagrams (positive logic)
'HC640
'HC643
'HC645
'G-------,
G-------,
'G-------.
c
<
l>
:2
nm
:-2
A1
81
A1
81
A1
81
."
o:xl
s:
TO SEVEN OTHER TRANSCEIVERS
TO SEVEN OTHER TRANSCEIVERS
TO SEVEN OTHER TRANSCEIVERS
maximum ratings. recommended operating conditions. and electrical characteristics
l>
~
o
See Table III, page 2-8.
:2
4-94
-III
INSTRUMENTS
TEXAS
POST OFFice BOX 225012 • DALLAS, TeXAS 75265
3E
TYPES SN54HC640, SN74HC640
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
'HC640 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
FROM
(INPUT)
A or B
TO
(OUTPUT)
B or A
VCC
TA = 25°C
MIN
TYP MAX
tdis
G
G
A or B
A or B
tt
MIN
MAX
29
105
160
130
4.5 V
6V
10
21
18
32
26
27
340
22
290
58
49
8
109
230
27
46
39
2V
20
40
68
58
150
225
190
4.5 V
18
30
45
38
6V
2V
16
20
26
38
90
32
75
4.5 V
8
12
18
15
6V
6
10
15
13
4.5 V
6V
A or B
SN74HC640
MAX
2V
2V
ten
SN54HC640
MIN
Power dissipation capacitance per transceiver
60
No load. TA
=
UNIT
ns
ns
ns
ns
40 pF typ
25°C
'HC640 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 150 pF (see Note 1)
PARAMETER
tpd
ten
tt
FROM
(INPUT)
A or B
IT
TO
(OUTPUT)
B or A
A or B
A or B
VCC
TA = 25°C
MIN TYP MAX
SN54HC640
MIN
SN74HC640
MAX
MIN
MAX
2V
44
190
4.5 V
14
6V
11
2V
124
4.5 V
31
63
94
79
6V
23
54
88
68
2V
4.5 V
45
17
210
42
315
63
265
6V
13
36
53
38
290
58
235
47
33
49
41
315
470
395
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
53
45
UNIT
ns
ns
ns
II
z
o
~
~
a:
o
LL
~
W
(.)
z
C
ten
(")
tt
2
m
2
FROM
(lNPUTI
A or B
G
TO
(OUTPUT}
B or A
A or B
A or B
VCC
TA = 25°C
MIN
TYP MAX
SN54HC643
MIN
MIN
MAX
2V
4.5 V
44
14
195
39
295
59
245
49
6V
11
34
43
2V
124
315
50
470
4.5 V
31
63
94
6V
54
2V
23
45
210
80
315
4.5 V
6V
17
13
42
36
63
53
NOTE 1: For load circuit and voltage waveforms, see page 1-14 .
."
o
::Jl
S
»
::!
o
2
4-96
SN74HC643
MAX
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
UNIT
ns
395
79
ns
68
265
53
ns
45
TYPES SN54HC645, SN74HC645
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
'HC645 switching characteristics over recommended operating free·air temperature range (unless
otherwise noted), Cl = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
vCC
TA = 25°C
MIN
TYP MAX
2V
tpd
A or B
4.5 V
B or A
6V
2V
ten
tdis
G
G
A or B
A or B
A or B
tt
I
SN54HC645
MIN
SN74HC645
MAX
MIN
MAX
40
105
160
130
15
21
32
26
12
18
27
22
290
125
230
340
4.5 V
23
46
68
58
6V
20
39
58
49
250
2V
74
200
300
4.5 V
25
40
60
50
6V
21
34
51
43
2V
20
60
90
75
4.5 V
8
12
18
15
6V
6
10
15
13
Power dissipation capacitance per transceiver
UNIT
ns
ns
ns
ns
40 pF typ
'HC645 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), Cl = 150 pF (see Note 1)
PARAMETER
tpd
ten
tt
FROM
(INPUT)
A or B
G
TO
B or A
A or B
A or B
SN54HC645
TA = 25°C
(OUTPUT)
VCC
MIN
TYP
MAX
2V
54
150
4.5 V
18
6V
15
2V
4.5 V
MIN
SN74HC645
MAX
MIN
MAX
225
190
30
45
38
26
38
33
150
315
470
395
31
63
94
79
6V
25
54
80
68
2V
45
210
315
265
4.5 V
17
42
63
53
6V
13
36
53
45
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
UNIT
ns
ns
ns
II
z
o
i=
«
~
a:
ou..
Z
w
U
2
«
>
c
«
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-97
II
l>
c
<
z
l>
om
Z
"T1
o
:xl
s:
l>
::!
o
z
4-98
TYPES SN54HCT640, SN54HCT643, SN54HCT645
SN74HCT640, SN74HCT643, SN74HCT645
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
HIGH·SPEED
CMOS LOGIC
02804, MARCH 1984
SN54HCT' .•• JPACKAGE
SN74HCT' .•. J OR N PACKAGE
•
Inputs are TTL-Voltage Compatible
•
Choice of True or Inverting Logic
•
High-Current 3-State Outputs Can Drive up
to 1 5 LSTTL Loads
(TOP VIEW)
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
DEVICE
Vee
DIR
G
A1
A2
A3
A4
A5
A6
A7
A8
LOGIC
81
82
83
84
85
86
87
88
GND
'HCT640
'HCT643
Inverting
True and Inverting
'HCT645
True
SN54HCT' •.. FH OR FK PACKAGE
SN74HCT' •.• FH OR FN PACKAGE
description
(TOP VIEW)
These octal bus transceivers are designed for
asynchronous two-way communication
between data buses. The devices transmit data
from the A bus to the B bus or from the B bus
to the A bus depending upon the level at the
direction control (DIR) input. The enable input (<3)
can be used to disable the device so the buses
are effectively isolated.
N
~ ~
« «
0
t3
> I(!)
81
82
83
84
85
A3
A4
A5
A6
A7
The SN54HCT640, SN54HCT643, and
SN54HCT645 are characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HCT640,
SN74HCT643 and
SN74HCT645 are
characterized for operation from - 40°C to
85°C.
:2
o
i=
C
94
94
A5
B5
B6
A6
B6
A7
B7
A7
B7
A8
B8
A8
B8
A5
B5
AS
B5
A6
B6
A6
A7
B7
A8
B8
logic diagrams (positive logic)
'HCT640
'HCT643
0-------.
'HCT645
G-------,
'G-------,
C
<
l>
2
om
A1
B1
B1
A1
A1
B1
2-n
o:tJ
s:
l>
TO SEVEN OTHER TRANSCEIVERS
TO SEVEN OTHER TRANSCEIVERS
TO SEVEN OTHER TRANSCEIVERS
maximum ratings, recommended operating conditions, and electrical characteristics
-f
.0
See Table VII, page 2-14 .
2
4-100
-I/}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HCT640, SN54HCT643
SN74HCT640, SN74HCT643
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
'HCT640, 'HCT643 switching characteristics over recommended operating free-air temperature range
(unless otherwise noted)' CL = 50 pF (see Note 1)
PARAMETER
tpd
ten
tdis
FROM
TO
(INPUT)
(OUTPUT)
A or B
B or A
G
G
A or B
A or B
A or B
tt
SN54HCT640
TA - 25°C
VCC
SN54HCT643
MAX
SN74HCT643
TYP
MAX
4.5 V
14
12
21
18
32
5.5 V
27
23
4.5 V
27
35
53
44
MIN
MIN
SN74HCT640
MIN
26
5.5 V
24
32
47
39
4.5 V
20
30
45
38
5.5 V
18
26
41
34
4.5 V
9
12
18
15
5.5 V
8
11
16
14
Power dissipation capacitance per transceiver
UNIT
MAX
ns
ns
ns
ns
40 pF typ
'HCT640, 'HCT643 switching characteristics over recommended operating free-air temperature range
(unless otherwise noted), CL = 150 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
B or A
ten
G
A or B
tt
A or B
SN54HCT640
TA - 25°C
SN54HCT643
VCC
MIN
MIN
MAX
SN74HCT640
SN74HCT643
MIN
UNIT
MAX
TYP
MAX
4.5 V
17
27
41
34
5.5 V
15
24
37
30
4.5 V
5.5 V
31
28
45
41
68
61
56
51
4.5 V
17
42
63
53
5.5 V
14
38
57
48
ns
ns
ns
II
2
o
i=
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
C
tt
FROM
(INPUT)
A or B
G
TO
(OUTPUT)
B or A
A or B
A or B
VCC
TA .: 25°C
MIN
TYP MAX
4.5 V
SN54HCT645
MIN
MAX
20
30
45
MAX
38
UNIT
ns
5.5 V
18
27
41
34
4.5 V
36
5.5 V
30
59
63
89
80
74
67
ns
4.5 V
5.5 V
17
14
42
38
63
57
53
48
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
C
<
z
l>
n
m
Z
'T1
o
:0
s:
l>
-I
oZ
4-102
SN74HCT645
MIN
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC673, SN54HC674, SN74HC673, SN74HC674
.
16·81T SHIFT REGISTERS
02804, MARCH 1984
'HC673
•
16-Bit Serial-In, Serial-Out Shift Register
with 16-Bit Parallel-Out Storage Register
o
Performs Serial-to-Parallel Conversion
SN54HC673 ••. JT PACKAGE
SN74HC673 •.• JT OR NT PACKAGE
(TOP VIEW)
SH ClK
R/W
STRClR
MODE/STRClK
SER/a15
YO
Yl
Y2
Y3
Y4
GND
'HC674
•
16-Bit Parallel-In, Serial-Out Shift Register
•
Performs Parallel-to-Serial Conversion
•
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
description
4
The 'HC673 is a 16-bit shift register and a 16-bit
storage register in a single 24-pin package. A
three-state input/output (SER/015) port to the
shift register allows serial entry and/or reading
of data. The storage register is connected in a
parallel data loop with the shift register and may
be asynchronously cleared by taking the storeclear input low. The storage register may be
parallel loaded with shift-register data to provide
shift-register status via the parallel outputs. The
shift register can be parallel loaded with the
storage-register data upon command.
22
21
20
6
19
18
17
16
10
15
11
14
12
13
VCC
Y15
Y14
Y13
Y12
Yll
Yl0
Y9
Y8
Y7
Y6
Y5
SN54HC673 ••. FH OR FK PACKAGE
SN74HC673 ... FH OR FN PACKAGE
(TOP VIEW)
Dependable Texas Instruments Quality and
Reliability
SN54HC673,SN74HC673
3
STRCi:R
5
MODE/STRClK
SER/a15
NC
YO
Yl
Y2
6
The SN54HC673 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC673 is
characterized for' operation from - 40°C to
85°C.
1 282726
25
24
23
22
21
20
10
11
19
Y13
Y12
Yll
NC
Yl0
Y9
Y8
II
z
SN54HC674 •.• JT PACKAGE
SN74HC674 ... JT OR NT PACKAGE
(TOP VIEW)
A high logic level at the chip·-select (CS) input
disables both the shift-register clock and the
storage-register clock and places SERIO 1 5 in the
high-impedance state. The store-clear function
is not disabled by the chip select.
Caution must be exercised to prevent false
clocking of either the shift register or the storage
register via the chip-select input. The shift clock
should be low during the low-to-high transition
of chip select and the store clock should be low
during the high-to-Iow transition of chip select.
3 2
cs
vcc
ClK
Pf5
P14
P13
P12
Pll
Pl0
P9
P8
P7
P6
P5
MODE
SER/a15
PI
P2
P3
P4
GND
10
15
11
14
12
13
o
i=
C
o
<
J>
MODEl
SERI
Cs
Rm
SH CLK
STRCUi
H
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
Q14n
H
H
L
Y15n
t
z
L
L
~
L
H
H
X
~
L
H
H
~
L
H
L
L
X
H
L
L
~
STRCLK
015
SHIFT
Z
NO
-
2
"T1
o
:D
s:
J>
::!
o
2
4-104
STORAGE REGISTER
PARALLEL
SERIAL OUTPUT
SERIAL INPUT
LOAD
NO
NO
NO
FUNCTIONS
CLEAR
LOAD
NO
YES
Z
NO
YES
YES
NO
YES
YES
NO
NO
YES
YES
YES
NO
NO
YES
YES
NO
NO
NO
NO
NO
YES
YES
015
'HC674 FUNCTION TABLE
2
om
SHIFT REGISTER FUNCTIONS
READ FROM
WRITE INTO
INPUTS
SERf
CS
RfW
MODE
ClK
015
H
X
l
~
Z
Z
l
H
~
014n
l
H
X
X
l
H
X
l
~
P15
OPERATION
Do nothing
Shift and write (serial load)
Shift and read
Parallel load
H = high level (steady state)
l = low level (steady state)
t = transition from low to high level
~ = transition from high to low level
X = irrelevant (any input including transitions)
Z = high impedance, input mode
o 14n = content of 14th bit of the shift register before the most
recent ~ transition of the clock
01 5 = present content of 15th bit of the shift register
Y15n = content of the 15th bit of the storage register before
the most recent ~ transition of the clock
P15 = level of input P15
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
NO
NO
NO
NO
TYPES SN54HC673, SN54HC674, SN74HC673, SN74HC674
16·81T SHIFT REGISTERS
logic symbols
'HC673
'HC674
SRG16
MODE (5)
Rm (3)
7,3,40
10,3,40
50 6Z10
11,3,40
50 6Z11
l,2M3
Gl/2EN
(7) VO
(81
(91
(101
(111
Vl
V2
V3
V4
(131
V5
(141
V6
(151
V7
(161
V8
(111
50 6Z25
25,3,40
[)
8117
V9
(181
Vl0
(191
Vll
(201
V12
(211
V13
(221
V14
(231
V15
(61 SER/Q15
Z7
3,40
[)
117
,.) SERfQ15
II
2
0
i=
C
o
<
:t>
z
o
m
Z
(61
>----<.....~SER/Q15
o"
lJ
S
:t>
::!
o
z
*When PE is active. data is synchronously parallel loaded into the shift registers from the 16 P inputs and no shifting takes place.
Pin numbers shown are for JT and NT packages.
maximum ratings recommended operating conditions, and electrical characteristics
See Table III, page 2-8_
4-106
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC673, SN54HC674, SN74HC673, SN74HC674
16-81T SHIFT REGISTERS
'HC673 timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
vcc
fclock
Clock frequency
Pulse duration, SH ClK or
tw
SER/a15,
tsu
Setup time
before
SH
th
ClK~
2V
0
4.5 V
6V
0
0
2V
100
20
YO thru Y15
--
MODE, R/W, CS
Hold time, SER/a15, YO thru Y15,
MODE, R/W, CS
5
25
29
SN54HC673
MIN
0
0
0
150
MAX
3.3
17
19
SN74HC673
MIN
MAX
4
0
0
0
125
30
25
6V
2V
17
26
21
100
150
125
4.5 V
6V
2V
20
17
175
30
26
25
21
265
220
4.5 V
35
53
44
6V
30
45
37
4.5 V
STRClK high or low
TA = 25°C
MAX
MIN
2V
0
0
0
4.5 V
0
6V
0
0
0
0
0
20
24
UNIT
MHz
ns
ns
ns
ns
'HC674 timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
2V
fclock
tw
Clock frequency
Pulse duration,
ClK high or low
SER/a15,
Setup time
tsu
before
ClK~
th
PO thru P15
MODE, R/W, CS
Hold time, SER/a15, PO thru P15,
MODE, R/W, CS
TA = 25°C
MIN
MAX
0
5
_ SN54HC674
MIN
0
SN74HC674
MAX
3.3
MIN
0
4.5 V
0
25
0
17
0
6V
0
29
0
19
2V
4.5 V
100
150
0
125
20
17
30
25
26
150
21
125
17
30
26
21
6V
2V
100
4.5 V
20
6V
25
2V
175
265
220
4.5 V
35
53
44
6V
2V
30
45
0
37
0
4.5 V
6V
0
0
0
0
0
TEXAS
"'J1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
0
0
MAX
4
20
24
UNIT
MHz
ns
II
2:
o
t=
«
:E
a::
ns
oLL
2:
ns
w
(.)
ns
2:
«
>
c
«
4-107
TYPES SN54HC673, SN54HC674, SN74HC673, SN74HC674
16·811 SHIFT REGISTERS
'HC673 switching characteristics over recommended operating free·air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
f max
MODE/STRClK
tpd
STRClR
tpd
SH ClK
tpd
Cs.
ten
Cs.
tdis
~
»
c
<
»
2
R/W
R/W
Y
y
SER/015
SER/015
SER/015
2V
5
4.5 V
6V
25
29
.....
7
28
32
2V
4.5 V
66
23
6V
2V
20
4.5 V
19
6V
16
72
SN54HC673
SN74HC673
MAX
MIN
MIN
3.3
4
17
19
20
24
MAX
UNIT
MHz
ns
57
2V
4.5 V
ns
24
6V
20
2V
66
4.5 V
23
6V
2V
20
66
4.5 V
6V
23
20
~ ~
L-..........
TA = 25°C
TYP MAX
MIN
vcc
~
...............P_o_w_e_r_di_ss_ip_a_ti_o_n_ca_p_a_ci_ta_n_ce.....
ns
ns
ns
lo_ad_._T~A
...................._N_o.....
~
.....
=_2_5_o_C.....
~
..............._1_5_0_p_F_ty_p..........
'HC674 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(lr~PUT)
TO
(OUTPUT)
Vcc
2V
f max
("")
TA = 25°C
TYP MAX
MIN
7
5
4.5 V
m
25
29
6V
2
tpd
ClK
SER/015
."
o
28
32
2V
4.5 V
72
24
6V
20
2V
70
::JJ
ten
CS.
R/W
SER/015
»
-I
4.5 V
6V
23
20
2V
tdis
CS. R/W
SER/015
4.5 V
70
23
6V
20
S
o2
SN54HC674
MIN
SN74HC674
MIN
3.3
4
17
19
20
24
Power dissipation capacitance
MAX
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
UNIT
MHz
ns
ns
ns
150 pF typ
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
4-108
MAX
HIGH-SPEED
CMOS LOGIC
TYPES SN54HC677, SN54HC678, SN74HC677, SN74HC678
16-BIT ADDRESS COMPARATORS
02833, MARCH 1984
SN54HC677 ... JT PACK~GE
SN74HC677 ... JT OR NT PACKAGE
•
'HC677 is a 16-BitAddress Comparator
with Enable
•
'HC678 is a 16-Bit Address Comparator
with Latch
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
(TOP VIEW)
A4
A5
AB
A7
AS
A9
Al0
All
GNO
description
10
11
12
15
14
13
P3
P2
Pl
PO
AlB
A15
A14
A13
A12
SN54HC677 .•. FH OR FK PACKAGE
SN74HC677 .•. FH OR FN PACKAGE .
(TOP VIEW)
The 'HC677 and 'HC678 address comparators
simplify addressing of memory boards and/or
other peripheral devices. The four P inputs are
normally hard wired with a preprogrammed
address. An internal decoder determines what
input information applied to the 16 A inputs
must be low or high to cause a low state at the
output (Y). For example, a positive-logic bit
combination of 0111 (decimal 7) at the P input
determines that inputs A 1 through A7 must be
low and that inputs A8 through A 16 must be
high to cause the output to go low. Equality of
the address applied at the A inputs to the
preprogrammed address is indicated by the
output being low.
M N
_
U
U
u
«l
4
A4
A5
3 2 1 282726
5
25
6
A6
NC
A7
A8
A9
10
11
P3
P2
Pl
NC
PO
AlB
A15
II
121314 151617 18
z
SN54HC678 •.• JT PACKAGE
SN74HC678 ... JT OR NT PACKAGE
(TOP VIEW)
The 'HC677 features an enable input ((3). When
G is low, the device is enabled. When G is high,
the device is disabled and the output is high
regardless of the A and P inputs. The 'HC678
features a transparent latch and a latch enable
input (C). When C is high, the device is in the
transparent mode. When C is low, the previous
logic state of Y is latched.
Al
A2
A3
A4
A5
AB
A7
AS
A9
Al0
All
GNO
The SN54HC677 and SN54HC678 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN54HC677 and SN74HC678 are characterized
for operation from - 40°C to 85 °C.
o
i=
2
«
VCC
C
10
11
12
15
14
13
a:
P3
P2
Pl
PO
AlB
A15
A14
A13
A12
oLL
2
w
(.)
2
c
u
u>
4
A4
A5
AB
NC
A7
AS
A9
3 2 1 282726
25
24
7
23
22
21
20
19
10
11
P3
P2
Pl
NC
PO
AlB
A15
121314 151617 18
O_OUNM~
:;: :;:.~ z :;::;::;:
NC - No internal connection
ADVANCE INFORMATION
This document contains information
on a new product. Specifications are
subject to change without notice.
TEXAS
-I./}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
Copyright © 1984. Texas Instruments Incorporated
4-109
TYPES SN54HC677, SN54HC678, SN74HC677, SN74HC678
16·BIT ADDRESS COMPARATORS
FUNCTION TABLE
INPUTS COMMON TO 'HC677 AND 'HC678
'HC677
'HC678
G
C
P3
P2
P1
PO
A1
L
H
L
L
L
L
H
H
L
H
L
L
L
H
L
H
L
H
L
L
H
L
L
L
L
L
H
L
H
H
L
H
L
L
L
L
L
H
L
L
L
L
H
L
H
L
H
L
L
L
L-
L
H
L
H
H
L
L
L
L
H
L
H
H
H
L
L
H
H
L
L
L
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
V
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
L
H
H
L
H
L
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
L
L
H
H
L
H
H
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
H
H
H
H
H
L
L
L
L
L
L
L
L
All other combinations
L
L
L
L
L
L
H
L
H
L
L
'HC677: Any combination
H
H
'HC678: Any combination
Latched
logic symbols
G 1231
EN
PO 1181
C
<
»
2
PI
'HC677
'HC678
[AODRESS COMP)
[ADDRESS CaMP)
1231
P;;' 1
-I
&
PO
(191
PI
P2 1201
P3
(")
m
Al
-2
."
:xJ
~
'}
P3
3
Al
Zl
Z2
• A3
Z3
A3
A4
Z4
A4
AS
Z5
AS
AB
0
2
111
(201
A2
A7
:::!
1211
1191
C20
Zl
A6
»
P2
(181
Z2
A2
0
A9
(21
(61
171
(BI
(9)
1221 y
Z6
A6
Z7
A7
ZB
AB
Z9
A9
AID 1101
Z10
AID
All 1111
Zl1
All
A12 (13)
Z12
A12
A13 1141
Z13
A13
A14 1161
A15 (16)
A16 (17)
Z14
P;;'14
14
-I
A14
Z15
po 15
-I
A15
Z16
15
A16
141
151
(61
(7)
IBI
191
1101
(11)
1131
1141
1151
1161
(17)
P
P;;' 1
-I
,
-I
P;;' 2
2
P;;' 3
-I
3
P;;' 4
Z4
Z5
Z6
Z7
ZB
Z9
Z10
Zll
Z12
Z13
Z14
Z15
p- 1
Z16
16
16
Pin numbers shown are for JT and NT packages.
4-110
L
L
L
H
II»
OUTPUT
A2 A3 A4 A5 A6 A7 AB A9 A 10 A 11 A 1 2 A 1 3 A 14 A 1 5 A 16
•
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC677, SN74HC677
16·81T ADDRESS COMPARATORS
'HC677 logic diagram (positive logic)
In order to understand the
implementation of this device, it
is essential that the function of
the vertical string of transmission gates be understood. A
schematic of one of these gates
is shown below. If the input to
the transmission gate labeled
"X 1" is high, then the
transmission path between the
two ports labeled "1" is on. If
the" X 1" input is low, then the
transmission path between the
two ports labeled "1" is off.
Only one of the 16 transmission
gates can be off while the
device is operating; which one is
off is determined by inputs PO
through P3. The lines going from
the string of transmission gates
to the exclusive-OR gates
located above the transmission
gate that is off will be high. The
lines going to the exclusive-OR
gates located below that
transmission gate will be low.
G ~~--------------------------,
PO
~~--i~~--~~>,
P1
P2
vee
P3 =-:.q>>t-+-t--t-,
A1 ...:.(.:...:1I--;-+-t-;----t-+-+-t------I~~
A2 . .;. (2.. ;. )_
_+_+-f_+_---+-+-+-+-------+-j'-L.../
A4 (4)
A5-(5...;..)--_r~r+--_;_+_t_;_----~~H_/
A6 (6)
A7 (7)
A8-(8-1--_r~r+--_r+_t_;_----~r_H_/
II
Z
o
~
«
A9...:.(9~1----~r+--_;_+_t_;_-----r_~
~
a:
oLl-
A10...:.(.:...:10~)---I_;_+_--+-+-;-r-----_r~~
-w
Z
(.)
Z
«
>
c
«
A12...:.(1.:...:3~)_____+_+_--~-+-~----_+__H_/
A13...:.(...;..14...:.)----_;_+_--+-+-;-r----r+~~
A14~(~15~)______+_--+-+_;_r-----r+~~
A15...;..(1_6~)__________~-+-~_____+__H_/
A16 (17)
Pin numbers shown are for JT and NT packages.
-I!}
. TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
4-111
TYPES SN54HC678, SN74HC678
16·81T ADDRESS COMPARATORS
'HC678 logic diagram (positive logic)
c
PO
P1
P2
An explanation of the function
of the string of transmission
gates appears with the 'HC677
logic diagram on the previous
page.
~~--~----~~--------------------,
........
~:i---t~
---:--'
~~~~~~~~~,
~~~H-+-·<:D"""
P3 J..:::...:J't;>c......,H-+o
A1 ~(~1)--~r+~--+1~+-----~-n~
A3~(3~)--~~-r--~H-+------r-H~
A4 141
A5-(_5)--~~~--~H-+------r-H~
A6 (6)
II
A7 (7)
l>
C
<
l>
A9~(~9)----~~--1-r++------r~~
:2
n
m
A10~(1~O~)---+;-r-~~++______+-~~
:2
."
o
l:J
A11~(1~1~)---+~~-+-rr+------~H-/
l>
-t
A12~(1~3~)--__~~-+-rr+______~~
:2
A13 (14)
s:
o
A14 (15)
A15~(1_6~)--______-+~~______r-~~
A16 (171
Pin numbers shown are for JT and NT packages.
4-112
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 2f5012 • DALLAS. TEXAS 75265
TYPES SN54HC677, SN54HC678, SN74HC677, SN74HC678
16·BIT ADDRESS COMPARATORS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
'HC677 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tpd
FROM
(INPUT)
Any P
Any A
TO
(OUTPUT)
Y
Y
vCC
TA = 25°C
MIN
TYP MAX
2V
160
4.5 V
32
6V
27
2V
90
4.5 V
18
15
6V
tpd
G
Y
Y
tt
2V
4.5 V
70
6V
12
2V
4.5 V
38
SN54HC677
MIN
MAX
SN74HC677
MIN
MAX
ns
ns
14
ns
ns
8
6
6V
UNIT
'HC678 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tpd
tpd
tt
FROM
(INPUT)
Any P
Any A
C
TO
(OUTPUT)
VCC
TA = 25°C
MIN TYP MAX
2.V
165
Y
4.5 V
33
28
Y
6V
2V
4.5 V
105
21
6V
18
2V
4.5 V
75
6V
13
2V
4.5 V
38
8
6V
6
Y
Y
SN54HC678
MIN
MAX
15
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
SN74HC678
MIN
MAX
UNIT
ns
II
2
o
i=
C
C
<
4
'HC677
'HC163
ADDRESS
COMP
CTR16
1R
ClK _--4I~_ _C_l_K-c:> C1/+
J.
EN
VCC
l>
2
"m
2
."
8
0 ••• 7
-=
A1
8~--~r---------------~
9 ••• 15
15
A2 ••• A16
0
::c
:s:
MODUlO·N SYNCHRONOUS COUNTER
l>
-I
(5
2
4-114
TEXAS
-1/1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
[P= 1)
MAX COUNT
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC679, SN54HC680, SN74HC679, SN74HC680
12·81T ADDRESS COMPARATORS
02833, MARCH 1984
•
'HC679 is a 12·Bit Address Comparator
With Enable
•
'HC680 is a 12·Bit Address Comparator
With Latch
•
•
SN54HC679 ... J PACKAGE
SN74HC679 .•. J OR N PACKAGE
(TOP VIEW)
Vee
Al
A2
A3
A4
A5
A6
A7
A8
A9
GND
Package Options Indude Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
Dependable Texas Instruments Quality and
Reliability
G
P3
P2
P1
PO
A12
All
A10
17
16
15
14
13
12
6
8
9
10
11
description
The 'HC679 and 'HC680 address comparators
simplify addressing of memory boards and/or
other peripheral devices. The four P inputs are
normally hard wired with a preprogrammed
address. An internal decoder determines what
input information applied to the 12 A inputs must
be low or high to cause a low state at the output
(Y). For example, a positive-logic bit combination
Of 0111 (decimal 7) at the P input determines
that inputs A 1 through A 7 must be low and that
inputs AB through A 12 must be high to cause
the output to go low. Equality of the address
applied at the A inputs to the preprogrammed
address is indicated by the output being low.
The 'HC679 features an enable input (G). When
Gis low, the device is enabled. When Gis high,
the device is disabled and the output is high
regardless of the A and P inputs. The 'He6BO
features a transparent latch and a latch enable
input (e). When e is high, the device is in the
transparent mode. When e is low, the previous
logical state of Y is latched.
The 'He679 and 'He6BO are functionally
unilaterally interchangeable with the ALSTTL
counterparts, 'ALS679 and' ALS6BO, in all cases
of normal use as 12-bit address comparators.
They differ in two respects. First, they may be
programmed to recognize all A inputs low either
by
connecting
all
P
inputs
high
(1111 = decimal 15), or by combination HHLL
(1100 = 12), the latter option not being valid
for the ALSTTL parts. Second, the combinations
HHLH and HHHL (1101 = 13 and 1110 = 14)
cannot be used (but are not needed) in addresscomparator
applications.
These
two
combinations cause the outputs to be disabled
(high).
SN54HC679 ..• FH OR FK PACKAGE
SN74HC679 ... FH OR FN PACKAGE
(TOP VIEW)
C"')
-
U
U
A4
A5
A6
P3
P2
Pl
PO
II
2
SN54HC680 .•. J PACKAGE
SN74HC680 ... J OR N PACKAGE
(TOP VIEW)
Al
A2
A3
A4
A5
A6
A7
AS
A9
GND
lU20
19
2
18
3
17
9
10
16
15
14
13
12
II
o
i=
c
U
A4
A5
A6
A7
AS
P3
P2
Pl
PO
Copyright © 1984, Texas instrumenls Incorporated
ADVANCE INFORMATION
This document contains information
on a new product. Specifications are
subject to change without notice.
N
I(!)
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
4-115
TYPES SN54HC679. SN54HC680. SN74HC679. SN74HC680
12·81T ADDRESS COMPARATORS
description (continued)
The SN54HC679 and SN54HC680 are characterized for operation over the full military temperature range
of - 55°C to 125°C. The SN74HC679 and SN74HC680 are characterized for operation from - 40°C
to 85°C.
FUNCTION TABLE
II
'HC679
'HC6S0
G
C
P3
P2
Pl
PO
Al
L
H
L
L
L
L
H
L
H
L
L
L
H
L
H
H
H
H
H
H
H
L
H
L
L
H
L
L
H
H
H
H
H
L
H
L
L
H
L
H
L
L
L
H
H
H
L
L
H
L
H
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
l
L
H
L
H
H
L
L
L
L
L
L
H
L
H
H
H
L
L
L
L
H
H
L
L
L
L
L
L
H
H
L
L
H
L
L
H
H
L
H
L
L
<
OUTPUT
Al0
All
A12
y
H
H
H
L
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
L
A2 A3 A4 AS A6 A7 AS A9
H
H
H
H
H
H
H
H
L
H
H
L
H
H
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
H
H
H
H
H
L
X
X
X
X
H
H
H
H
H
L
L
X
X
L
X
H
X
X
L
X
X
L
X
L
X
X
L
L
L
L
H
H
L
:t:O
INPUTS COMMON TO 'HC679 AND 'HC6S0
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
All other combinations
'HC679: Any combination
'HC6S0: Any combination
H
Latched
.
'HC679
2
om
;2
-n
o
:u
~
l>
:::!
o
2
'He6S0
[ADDRESS COMP)
G
=1
[ADDRESS CaMP)
&
C
PO
PO
Pl
Pl
P2
P2
P3
P3
A1
A1
A2
A2
A3
A3
A4
(18) y
A4
A5
A5
A6
A7
A7
A8
AS
A9
A9
A10
A10
A11
A11
A12
4-116
A6
(191
(16)
}:~
1.17)
3
(14)
(15)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
A12
Z1
Z2
Z3
Z4
Z5
Z6
Z7
ZS
Z9
pP;> 3
3
P;> 4
4
P;> 5
5
P;> 6
6
P;> 7
7
P;> 8
8
P;> 9
9
P;>10
10
P;> 11
(11)
(12)
(13)
L
H
logic symbols
l>
H
Z10 P;>
~~
12
P = 13
Z12 P =14
Z11
TEXAS •
INSTRUMENTS .
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
.. 1
~1
=1
"1
=1
TYPES SN54HC679, SN74HC679
12·81T ADDRESS COMPARATORS
'HC679 logic diagram (positive logic)
In order to understand the
implementation of this device, it
is essential that the function of
the
vertical
string
of
transmission
gates
be
understood. A schematic of one
of these gates is shown below.
If the input to the transmission
gate labeled "X 1" is high, then
the transmission path between
the two ports labeled "1" is on.
If the "X1" input is low, then
the transmission path between
the two ports labeled "1" is off.
Only one of the 16 transmission
gates can be off while the
device is operating; which one is
off is determined by inputs PO
through P3. The lines going from
the string of transmission gates
to the Exclusive-OR gates
located above the transmission
gate that is off will be high. The
lines going to the Exclusive-OR
gates located below that
transmission gate will be low.
vee
A1 _(1_)__~~~__~~~____4-~-/
A2
(2)
A3
(3)
A4
(4)
A5
(5)
AS
(S)
A7
(7)
A8
(8)
y
AS
(111
A11
(12)
A12
o
i=
«
~
(9)
A10
II
z
a:
oLL.
Z
W
(J
z
«
c>
«
(13)
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-117
TYPES SN54HC680, SN74HC680
12·BIT ADDRESS COMPARATORS
'HC680 logic diagram (positive logic)
An explanation of the function
of the string of transmission
gates appears with the 'HC679
logic diagram on the previous
page.
A1
II
J>
C
111
A2
121
A3
131
A4
141
A5
151
A6
161
A7
171
A8
181
A9
191
<
J>
2
(")
m
-2
A10~
"T'I
0
::xJ
A1l
1121
::1
A12
1131
3:
J>
0
2
4-118
TEXAS
"'J1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC679. SN54HC680. SN74HC679. SN74HC680
12·BIT ADDRESS COMPARATORS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
'HC679 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL - 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
Any P
Y
tpd
Any A
Y
tpd
G
y
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Y
tt
vcc
TA .. 25°C
MIN TYP MAX
160
32
27
90
18
15
70
14
12
38
8
6
SN54HC679
MIN
MAX
SN74HC679
MIN
MAX
UNIT
ns
ns
ns
ns
'HC6S0 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted),' CL = 50 pF (see Note 1)
PARAMETER
. FROM
(INPUT)
TO
(OUTPUT)
tpd
Any P
Y
tpd
Any A
Y
tpd
tt
C
Y
Y
vCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
165
33
28
105
21
18
75
15
13
38
8
6
SN54HC680
MAX
MIN
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
SN74HC680
MIN
MAX
UNIT
ns
ns
II
2:
o
i=
C
<
l>
z
o
m
Z
"T1
ADDRESS
CDMP
M'EM'E'N
,.
SYSTEM
ADDRESS
LINES
AO (MSB)
TOA19
AO ••• A2
A4 ... A11
P1
P2
r.;
11
I
..
It
A3
s:
A12
::!
A14 •.. A19:/
l>
o
z
4-120
A13
I
I
A1 ... A11
Jp
8
LLLL
llll
LLLL
lLLL
12
16
LLLL 'LLLL
LHll
llll
HLll
lLLl
HHlL
lllL
1/2
'HC139
XIV
IP=11)
A12
A
II.
4
LLLL
LLLL
lLll
llll
~
~
'"
", .
0
= LLLH
= LLLH
= lLLH
= lLLH
1000016
1004016
1008016
100C016
EN
PO
VCC
o
::D
G"
f,
B
....
1000016
1r-...
10040 16
.
2r-...
1008016
...
1
2
,6
3r-...
1OOC016
8O ... S5
REGISTER BANK DECODER
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
..
Or-...
64X N·BIT
REGISTERS
}
HIGH-SPEED
CMOS LOGIC
TYPES SN54HC682, SN54HC684, SN54HC686
SN74HC682, SN74HC684, SN74HC686
8-BIT MAGNITUDE COMPARATORS
02804, MARCH 1984
SN54HC682. SN54HC684 ... J PACKAGE
SN74HC682. SN54HC684 ... J OR N PACKAGE
(TOP VIEW)
•
Compares Two 8-Bit Words
•
'HC682 has 20-kO Pullup Resistors on the
Q Inputs
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
description
These magnitude comparators perform
comparisons of two eight-bit binary or BCD
words. All types provide P = Q and P> Q outputs.
The 'HC682 features 20-kO pullup termination
resistors on the Q inputs for analog or switch
data.
p>o
VCC
PO
00
P1
01
P2
02
P3
03
GND
p=o
07
P7
06
P6
05
P5
04
P4
SN54HC682. SN54HC684 ..• FH OR FK PACKAGE
SN74HC682. SN74HC684 ... FH OR FN PACKAGE
(TOP VIEW)
0
001\
UIO
U II
o a.. 1a.. > a..
The
SN54HC682,
SN54HC684,
and
SN54HC686 are characterized for operation
over the full military temperature temperature
range of - 55°C to 125°C. The SN74HC682,
SN74HC684,
and
SN74HC686
are
characterized for operation from - 40°C to
85°C.
P1
01
Q7
P7
06
P6
05
P3
C"lO~~LO
oza..oa..
(!)
2
0
SN54HC686 ... JT PACKAGE
SN74HC686 .•. JT OR NT PACKAGE
(TOP VIEW)
SN54HC686 ... FH OR FK PACKAGE
SN74HC686 ... FH OR FN PACKAGE
(TOP VIEW)
i=
0
O~I\UUNII
10
U
1
a..1(!) a.. z >I(!) a..
a:
0
1 U24
VCC
G1
2
23
G2
PO
00
P1
01
NC
P2
02
P3
03
GND
3
22
p=o
4
21
07
P7
NC
06
P6
05
P5
04
P4
P>O
5
20
6
19
7
18
8
17
~
16
10
15
11
14
12
13
4
00
P1
01
NC
3
2
C
12131415161718
Q
P=Q
P>Q
PQ
L
X
L
H
X
L
H
L
X
H
X
X
H
H
H
H
X
H
H
H
H
H
H
H
X
NOTES:
ENABLES
p, Q
1. The last 3 lines of the function table apply only to the
device having enable inputs, i.e., 'HC6S6.
2. The PQ outputs to a 2-input NAND gate.
logic symbols
'HC682, 'HC684
'HC6S6
COMP
P1
G1
G2
P2
PO
PO
II
P3
P4
P5
l>
C
P6
2
00
<
l>
P2
P=O
P3
P4
01
-2
02
o
:a
04
05
s:
06
l>
-I
(5
07
o0
P>O
03
."
(23)
(3)
Q1
o
o2
o3
o4
o c:
o6
o7
(14)
(16)
(18)
7
COMP
G1
G2
0
(5)
(8)
(10)
~P
(13)
(15)
P5
(17)
P6
(20)
P7
P7
om
2
P1
P
(2)
(4)
(6)
1P=0 ,...
(22)
7~
O'
(9)
2P>0 ....
(1)
(11)
~O
(14)
(16)
(18)
(21)
7
'HC6S2 has 20-kO pullup resistors on the Q inputs
'HC6S6 pin numbers shown are for JT and NT packages.
4-122
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
P=O
P>O
TYPES SN54HC682, SN54HC684
SN74HC682, SN74HC684
8-BIT MAGNITUDE COMPARATORS
'HC682, 'HC684 logic diagram (positive logic)
~_ _ _ _ _ _....;..(1--,-91
pea
II
2:
o
i=
«
~
a:
oLL
~
W
o
2:
«
«
>
c
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
4-123
TYPES SN54HC686. SN74HC686
8-BIT MAGNITUDE COMPARATORS
'HC686 logic diagram (positive logic)
(2
(23)
-
:::t=r-.
PO
00
P1
01
P2
II
l>
C
<
l>
02
P3
m
~
(3)
~~
(4)
(5)
(6)
--
(8)
(9)
(10)
003
P4
:2
0
04
P5
(11)
(13)
----
~~
-
(14)
(15)
:2
."
0
::D
05
3:
P6
l>
::!
0
:2
(22)
06
P7
07
,P>a
r~
(16)
(111
~
I-~
(18)
I
(20)
(21)
(1)
f
~
~-
F
I
I
I
Pin numbers shown are for JT and NT packages.
31
4-124
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC682, SN54HC684, SN54HC686
SN74HC682, SN74HC684, SN74HC686
8·BIT MAGNITUDE COMPARATORS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
'HC682, 'HC684 switching characteristics over recommended operating free-air temperature range
(unless otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
TA ~ 25°C
FROM
(INPUT)
TO
(OUTPUT)
VCC
P or Q
Any
4.5 V
16
6V
14
MIN
Any
tt
MAX
MIN
MAX
SN74HC682
SN74HC684
MIN
UNIT
MAX
80
2V
tpd
TYP
SN54HC682
SN54HC684
2V
38
4.5 V
8
6V
6
ns
ns
'HC686 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA = 25°C
MIN
TYP MAX
tpd
tt
P or Q
(31orG2
Any
Any
Any
MAX
SN74HC686
MIN
MAX
UNIT
80
2V
tpd
SN54HC686
MIN
4.5 V
16
6V
14
2V
55
4.5 V
6V
11
2V
38
4.5 V
8
6V
6
ns
ns
II
ns
o
9
NOTE 1: For load circuit and voltage waveforms see page 1-14.
:2
t=
Q
c
<
:J>
2
o
m
2
o
."
:IJ
3:
:J>
-4
(5
2
4-126
TYPES SN54Ht68t SN74HC688
8·BIT IDENTITY COMPARATORS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
SN54HC688 ..• J PACKAGE
SN74HC688 ... J OR N PACKAGE
•
Compares Two Eight·Bit Words
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
(TOP VIEWI
Vee
G
'P=Q
07
P7
06
P6
05
P5
04
P4
PO
00
P1
01
P2
02
P3
03
GND
Dependable Texas Instruments Quality and
Reliability
description
These
identity
comparators
perform
comparisons of two eight-bit binary or BCD
words. An enable input (<3) may be used to force
the output to the high level.
The SN54HC688 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC688 is
characterized for operation from - 40°C to
85°C.
SN54HC688 ... FH OR FK PACKAGE
SN74HC688 ..• FH OR FN PACKAGE
(TOP VIEWI
00
d a..leJ
3
logic symbol
2
el9
> a..
1 2019
07
P7
06
P6
05
COMP
a-
EN
o
PO
Pl
II
9 1011 1213
P2
(61
P3
(81
2
o
i=
p
P4 (111
c:t
P5 (131
P7 (171
(31
01
(51
02
(71
03
(91
a:
INPUTS
7
ENABLE
P.Q
P=Q
P>Q
G
P=Q
L
L
H
o
o
04 (121
P
05 (141
C
06 (161
07 (181
l4
c:t
7
ADVANCE INFORMATION
This document contains information
on a new product. Specifications are
subject to change without notice.
Copyright ©1982 by Texas Instruments Incorporated
TEXAS
-1.11
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-127
TYPES SN54HC688, SN74HC688
8·BIT IDENTITY COMPARATORS
logic diagram (positive logic)
G
(1)
PO
00--"7'11..-_
P1
01 --T'Io.-""
P2
--'---'-~--
02 --TL..-""
P3
03--..,....__
P4
-=----'--~-
04 - - T L . . - " "
P5
-'------'--~-
05 --",""--",,
P6
---=---'----~--
06 --"'""--""
P7 --~---07 - - T ' L . - " "
II»
c
<
»
:2
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
om
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
vcc
tpd
P
P=Q
2V
4.5 V
75
15
6V
13
;2
"o::D
tpd
3:
tpd
~
o
tt
:2
Q
G
TA = 25°C
MIN
TYP MAX
2V
75
P=Q
4.5 V
15
13
P=Q
6V
2V
4.5 V
50
10
6V
9
2V
4.5 V
38
8
6V
6
Any
SN54HC688
MIN
MAX
SN74HC688
MAX
MIN
UNIT
ns
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
3.
4-128
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC690 THRU SN54HC693, SN74HC690 THRU SN74HC693
SYNCHRONOUS COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3·STATE OUTPUTS
02804. MARCH 1984
SN54HC690 THRU SN74HC693 ... J PACKAGE
SN74HC690 THRU SN74HC693 ... J OR N PACKAGE
•
4·Blt Counters/Registers
•
3·State Outputs Drive Bus Lines Directly
(TOP VIEW)
CCLR
CCK
A
•
·HC690 ... Decade Counter, Direct Clear
•
'HC691 .•. Binary Counter, Direct Clear
•
'HC692 .•. Decade Counter, Synchronous
Clear
•
'HC693 ..• Binary Counter, Synchronous
Clear
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition- to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
VCC
RCO
OA
Os
Oc
OD
ENT
LOAD
G
S
C
D
ENP
RCLR
RCK
GND
RIC
SN54HC690 THRU SN54HC693 ... FH OR FK PACKAGE
SN74HC690 THRU SN74HC693 ... FH OR FN PACKAGE
(TOP VIEW)
~15
description
uo
U U uu
a:
These devices incorporate synchronous
up/down counters, four-bit Ootype registers, and
quadruple two-line to one-line multiplexers with
three-state outputs in a single 20-pin package.
The up/down counters are programmable from
the data inputs and feature enable P (ENP) and
enable T (ENT) inputs and a ripple-carry output
(RCO) for easy expansion. The register/counter
select input (R/C) selects the counter when low
and the register when high for th'e three-state
outputs, aA. aB, aC. and aD.
OA
Os
Oc
OD
ENT
D
ENP
II
z
o
i=
«
Individual clock and clear inputs are provided for
both the counter and the register. Both clock
inputs are positive-edge triggered. The clear line
is active low and is asynchronous on the 'HC690
and 'HC691, synchronous on the 'HC692 and
'HC693.
:?i
a:
oLL
Z
w
The SN54HC690 through SN54HC693 are
characterized for operation over the full military
range of -55°C to 125°C. The SN74HC690
through SN74HC693 are characterized for
operation from - 40 DC to 85 DC.
ADVANCE INFORMATION
This document conteins Information
on a new product. Speclflcetlons ere
subject to change without notice.
TEXAS
(.)
z
«
>
c
«
~
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
Copyright
© 1984. Texas Instruments Incorporated
4-129
TYPES SN54HC690 THRU SN54HC693. SN74HC690 THRU SN74HC693
SYNCHRONOUS COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3·STATE OUTPUTS
logic symbols
'HC690
'HC691
MUX
3CT=9
Z22
22
(19)
RCO
RCO
OA
B
(2)
C
(4)
D
(8)
OB
Oc
OD
OA
B
C
D
'HC692
II
OB
Oc
OD
'HC693
l>
C
<
l>
2
n
m
-2
."
0
:D
s:
l>
:::!
0
2
4-130
OA
B
C
OB
Oc
OD
°A
B
c
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
Os
Oc
OD
TYPES SN54HC690, SN54HC691, SN74HC690, SN74HC691
SYNCHRONOUS COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3·STATE OUTPUTS
logic diagrams (positive logic)
'HC690
G~:~~~~~~~~~~~~~==~r-----~
--~----------
R:~!~I
RCK~
C-C-L-R ..:..(1;. . :. 1<1.)<:>--------'
-LO-A-O (131
ENP (71
ENT (141
CCK -'..(2-,-11;>0---+1-'
(191
RCO
II
2
o
i=
'HC691
C
=r~------------------~(~19~1
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
RCO
4-131
TYPES SN54HC692, SN54HC693, SN74HC692, SN74HC693
SYNCHRONOUS COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3·STATE OUTPUTS
logic diagrams (positive logic)
'HC692
II
l>
C
'HC693
<
l>
2
n
RCLR
2
CCLR
m
."
0
RCK
LOAO
lJ
S
l>
:::!
0
A
2
Qc
QD
~~~~!:~[)~--------------------~~ ~co
4-132
-Ii}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC690, SN54HC692, SN74HC690, SN74HC692
SYNCHRONOUS COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3·STATE OUTPUTS
typical operating sequences
'HC690 OECAOE COUNTER, Asynchronous Clear
'HC692 DECADE COUNTER, Synchronous Clear
LJ
CCLR~
LJ
LOAD
r-
ENP
ENT
RCK _________I1~
______________
~ilLllLl1~
___________________
CCK
Rm ______________________
L - I I_______
~
A
\\\\\\\\\1
ISSSSs\\\\\\SSSSS\\\\\\S\\S\\S\SS\\SS\ \SS DON'T CARE \S\\\S\\\\SS\\
B
S\\\\\\\I
KS\\SS\\\\\\SSs\\\\\\\S\\\\\\\\SS\\\\\\S' DON'T CARE\SSSS\\S\\\\\\
C
\\\\\\\\1
f\\SS\\SSS\\\\\\\\\\\\\\S\\\S\\S\\S\\\\\\S DON'T CAR E\\\SSSS\SS\\\\
D
\\\\\\\\1
QA
;2
:::C::
~.~~ lhHI.ZI/I
;.-.1-----1
QC : ::C:LSI~
________--,r1,-______--,
- .. r·- o
QD ___ '-._t.._ _ _ _.....
r-1~
7
t
8
SYNC
LOAD
LoV!~H....I..:;;.Z.L.m'-lL...-_ _ _ __
VI HI·Z I'/J
VI
0
RCO ____________
ASYNCJ Sytc
CLR
CLR
II
9
HI·Z
«1
_______________________________________________________
01
2
7
2
3
ASYNC
CLR
4
TEXAS
56
j
t
SYNC
CLR
-Ij}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
8
~HI.Z_+_INHIBIT4
o
t=
«
2
a:
oLL
;2
W
(.)
;2
«
«
>
c
4-133
TYPES SN54HC691, SN54HC693, SN74HC691, SN74HC693
SYNCHRONOUS COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3·STATE OUTPUTS
typical operating sequences
'HC691 BINARY COUNTER, Asynchronous Clear
'HC693 BINARY COUNTER, Synchronous Clear
G
--------------------------------------~
LJ
CCLR~
LOAD
LJ
ENP
.--
ENT
RCK _ _ _ _ _..:I
CCK
L--fi""'--_____
Ric
II»
A
"SSW
B
S\\\SS~
C
SSS\\\S\1
D
\\,\\\\\1
t\ss\\\\\\\\\\\\\\\\SSSSSSS\\SS\\SSSS\\\\\ DON'T CARE S\\SS\\\\\S\\
K\SS\\\\\\S\\\\S\\\\\\s\\\s\\S\SS\s\SSSW DON'T CARE \\\SSS\\\\\\\
f\\SSS\\SSS\\S\\\S\\\\\\SSSS\SSSSSSSSSSSSS DON'T CARE SS\\\s\SS\\\\
f\\\\SSS\s\SS\\\\\\' \\SSSSSSSS\\\SSSS SSSS, DON'T CARE \\\\\\\SSSSS\S
.-_",'
_ ~n I VtHI·Z'lJ
c
<
»
:2
o
m
2
OD::I::L..J
»
-I
~
RCO ____________
o
s:
'--____~r1..._____~
OC:::~: :L-J
"T1
::c
\-_~
OB:::(::,-'_ _-'
13
ASYNcJ SJNC
CLR
CLR
t
14
SYNC
LOAD
~r_l'--
15
0
____r-1...__________
Ko,V",1H;.;.;I..;;;.Z~a~a,--_______
VI HI.ZVJ
£e",2_H_I.z~2~~
_____________________________________
2
13
2
3
1t
ASYNC
CLR
5 6
8
I+-HI.Z-+--INHIBIT--.j
SYNC
CLR
(5
:2
4-134
-II}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265
31
TYPES SN54HC690, SN54HC691, SN74HC690, SN74HC691
SYNCHRONOUS COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3·STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical characteristi'cs
See. Table III, page 2-8.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
CCKt
RCO
4.5 V
105
21
6V
18
2V
4.5 V
50
10
6V
9
2V
4.5 V
85
17
6V
14
TA = 25°C
MIN
2V
tpd
tpd
tpd
tpd
tpHL
ENT
CLKt
RCO
Q
TYP
2V
75
RCKt
Q
4.5 V
6V
15
13
2V
85
CCLR~
Q
4.5 V
17
6V
14
2V
115
tpHL
CCLR.j.
RCO
4.5 V
6V
23
20
2V
tpHL
RCLR.j.
Q
4.5 V
80
16
6V
14
2V
55
tpd
RIC
Q
4.5 V
6V
2V
11
9
50
ten
G.j.
Q
4.5 V
10
tdis
tt
G't
MAX
SN54HC690
SN54HC691
MIN
MAX
SN74HC690
SN74HC691
MIN
UNIT
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
II
z
o
t=
c
c
<
l>
:2
tt
RIC
G~
G'f
Any Q
Any Q
Any Q
Any
TA = 25°C
vcc
MIN
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TVP MAX
105
21
18
50
10
SN54HC692
SN74HC692
SN54HC693
MIN
MAX
SN74HC693
MIN
MAX
ns
ns
9
85
17
14
80
16
14
55
11
ns
ns
ns
9
50
10
ns
9
80
16
14
38
8
6
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
om
:2
"TI
ol:J
~
l>
::!
o
:2
4-136
UNIT
-II}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
ns
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC696 THRU SN54HC699. SN74HC696 THRU SN74HC699
SYNCHRONOUS UPIDOWN COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3·STATE OUTPUTS
02804. MARCH 1984
•
4·Bit Counters/Registers
•
Multiplexed Outputs for Counter or Latched
Data
•
High-Current 3·State Outputs Drive Bus
Lines Directly or up to 15 LSTTL Loads
•
•
•
'HC696
'HC697
'HC698
Clear
'HC699
Clear
SN54HC696 THRU SN54HC699 ... J PACKAGE
SN74HC696 THRU SN74HC699 ..• J OR N PACKAGE
(TOP VIEW)
ufo
VCC
AGo
CCK
S
... Decade Counter, Direct Clear
... Binary Counter. Direct Clear
... Decade Counter. Synchronous
C
D
ENP
CCLR
RCK
..• Binary Counter, Synchronous
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
Dependable Texas Instruments Quality and
Reliability
QA
Qs
Qc
QD
ENT
i:OA5
G
9
GND
RIC
SN54HC696 THRU SN54HC699 •.. FH OR FK PACKAGE
SN74HC696 THRU SN74HC699 ..• FH OR FN PACKAGE
(TOP VIEW)
Ole ~18
«u=»a:
description
These high-speed CMOS devices incorporate
synchronous up/down counters, four-bit D-type
registers, and quadruple two-line to one-line
multiplexers with three-state outputs in a single
20-pin package. The up/down counters are
.programmable from the data inputs and feature
enable P (ENP) and enable T (ENT) and ripplecarry output (RCO) for easy expansion. The
register/counter select input (R/C) selects the
counter when low and the register when high for
the three-state outputs aA, aB, aC, and aD.
II
z
o
~ OIUIl!)10
uz«0
a:l!)a:
~
....I
~
a:
Both the counter clock (CCK) and register clock
(RCK) are positive-edge triggered. The counter
clear (CCLR) is active low and asynchronous on
the 'HC696 and 'HC697, synchronous on the
'HC698 and 'HC699.
oLL
~
W
(.)
z
C
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TeXAS 75265
4-137
TYPES SN54HC696 THRU SN54HC699, SN74HC696 THRU SN74HC699
SYNCHRONOUS UP/DOWN COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3·STATE OUTPUTS
logic symbols
'HC696
'HC697
B
C
II>
0
'HCG98
0
'HC699
MUX
MUX
<
>
2
0
m
CTRDIV16
CTRDIV10
-2
."
0
:c
3:
>
-f
3,5CT=9
222
4,5CT=O
V23
RCO
3,5CT=15
Z22
4,5CT=O
V23
RCO
0
2
B
B
C
4-138
(4)
C
(4)
(8)
0
(8)
'1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
38
TYPES SN54HC696, SN54HC697, SN74HC696, SN74HC697
SYNCHRONOUS UP/DOWN COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3·STATE OUTPUTS
logic diagrams (positive logic)
'HC696
II
Z
0
'HC697
i=
C
QC
>---J
r-:======;===4-----.
2
CCLii
o
~~11~3)~~~~~=====t~==~==t-_i--~t_--W
'TI
:Jl
~
»
::!
-<1>--+0
..:..;:(8;,:....)
UfO -,-,(1;.:. . 1-C>c,..q;>-t-HI
EiiiP
..:..:(7..:....)_ _--1-tH,
CCK
...:,:(2:..:...,)- ;
:>C>-----t'
o
2:
L-____~~~~[)~------------------~(1~91 RCO
3E
4-140
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC696, SN54HC698, SN74HC696, SN74HC698
SYNCHRONOUS UP/DOWN COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3·STATE OUTPUTS
typical operating sequences
'HC696 DECADE COUNTER, Asynchronous Clear
'HC698 DECADE COUNTER, Synchronous Clear
G __________________________________
r----1~
_____________________________
~~--------------------------------------------------------------__________________________________________________________
LOAD~~
ENP ____________________________________________________________________________
ENT
ulii
~~
----------------------------------------------------------~
1\\\\\\\\\\\\\\\\
RCK ______- J
~
___________________ z
CCK
RIC
----------------~------~
A
illilll
1\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' DON'T CARE S\\\\S\\\\\\\S\S\\\\\\S\\\\S\\SS§\\S
B
m.mJ
t\SS\\\S\s\\\\\SS\S\\sSSS\\\\\\\\\\S DON'T CARE \\SSSSSSSSSSSS\S SSs\\\\SS\\S\\\\SS\\\
f\SSSSS\\SS\\\\SSss\\ss\SS\\\S\SSSSS
DON'T CAR E
SS\\SSS\\\\\\\SS \\ \\S\\\\\\\\\\\\S SS\
t}\SS\\\SSSSSS\S\\\\\sS\\\SS\\s\\\\S
DON'T CARE
,S\\S\S\SSSSS\S\\S\\\\\\\\\SS\\\\\SSS
II
~
z
o
~
~
RCO
ASYNC
CLR
j ,
SYNC
CLR
t
7
U
L.J
8
9
0
1
2
37
5
M~----- COUNT UP-----..........
SYNC
LOAD
4
3
2
I.I-------
0
9
8
76
COUNT DOWN------.MI••-INHIBIT~
ct
o
LL
Z
W
(.)
z
C
o
<
l>
aB
aC
::t:J...-..-.J
::l::U
aD
m
ReO
:2
, Jt
o
'TI
o:xJ
tl,HI.zllI
::r.::u
:2
ASYNC
CLR
SYNC
CLR
t
13
~
14
LJ
15
0
______~r____l~~~~H_I_.Z~______~
2
14-1_---COUNT UP
SYNC
LOAD
3 1,3
5
4
3
-I-
LJ
2
0
15
COUND DOWN
14
13 12
_,_
INHIBIT~
3:
:::!
l>
o
:2
4-142
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
38
TYPES SN54HC69~ SN54HC697, SN14HC69~ SN74HC691
SYNCHRONOUS UP/DOWN COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3-STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical charC)cteristics
See Table III, page 2-8.
switching characteristics over recommended operating free-air temperature range (unless otherwise
60 pF (see Note 1)
noted), CL
=
FROM
(INPUT)
TO
(OUTPUTI
tpd
CCKt
RCO
tpd
00
RCO
PARAMETER
tpd
CCLRi
RCO
tpd
CCKt
Any Q
tpd
RCKf
Any Q
TA .. 25°C
VCC
MIN
2V
4.5 V
BV
2V
4.5 V
BV
2V
4.5 V
BY
2V
4.5V
BV
2V
4.5.V
aVo
2V
tpHL
tpd
ten
tdis
tt
CCLR'
Any Q
RIC
Any Q
13,
13t
Any Q
Any Q
Any
4.5 V
BV
2V
4.5 V
TVP MAX
115
23
20
55
11
ns
17
ns
85
17
14
90
18
15
70
14
12
6V
ns
14
70
4.5 V
UNIT
, ns
6V
2V
4.5 V
6V
2V
SN74HC696
SN74HC697
MIN
MAX
9
115
23
20
85
2V.
4.5V
BV
SN54HC696
. SN54HC697
MIN
MAX
14
12
95
19
1B
38
8
6
ns
ns
II
ns
z
o
.~
ns
:E
ns
ns
a:
o
11. .
~
W
o
2
Q
NOTE 1: For load circuits and vOltaQe waveforms. see page 1-14.
->-z>U
YO
ClK
Y2
ClKEN
NC
NC
Y6
CO
Y7
Y9
II
MQUCXlq>-zz>->-
2
<.!)
o
i=
NC-No internal connection
C
V5
V6
...
v
~
~
i>Cl
R
-I-
""'"--
ClR
I
L-;;-
~
~
>Cl
~
,--
H
-
~ >Cl
-~
R
-
I
L~r-
~
-J
-I-
~Cl
R
c
'---
<
»
2
om
-
-
L~
I>
-,...-
Cl
R
2
o
::c
s:
V2
(7)
V3
(1)
V4
V5
(5)
V6
(6)
(9)
(11)
(12)
'---
."
n-
Vl
(4)
~
10
II»
--L
(2)
VO
V7
VB
V9
co
Pin numbers shown are for J and N packages.
»
:::!
o
2
4-146
TEXAS
"I}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3:
TYPES SN54HC4017, SN74HC4017
DECADE COUNTERS/DIVIDERS
typical clear, count, and inhibit sequences
CLEAR~
_________________________________________________
CLOCK
ENABLE ____________________________________________~r--l~----YO~-----,~
I
____________________________~r__l~I__________
____________________________
L_______ ________________________
_________---'r__l
r
-I
Yl:J~~
_J
r-l~
Y2----'
_I
~~
Y3----'
Y4--'
____________
Y5--'
_________________
-I
OUTPUTS
-I
Y6 --,
-I
Y7--'
-I
--'r_1~
______________________
r-l~
~
_____
______________ ________
~
__________________~r_1~________________~-----
______________________
--'r-1~
___________________
--________________________~r_l~______~~-----__________________________
__ _______
yg--'
_ I
Y8 --,
II
-I
~r_1~
CARRY - I
OUTPUT --'
I
I
~
t-L
INHIBIT.
CLEAR
2
o
i=
'
~~-------------COUNT-----------------
COUNT
«
absolute maximum ratings, recommended operating conditions, and electrical characteristics
~
a:
See Table IV, page 2-10.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
fclock
vCC
Clock frequency
ClK high or low
tw
Pulse duration
CLR high
ClKEN low
Setup time,
tsu
before ClK t
ClR high
2V
4.S V
6V
2V
4.S V
6V
2V
4.S V
6V
2V
4.S V
6V
2V
4.S V
6V
TA = 25°C
MIN
MAX
0
0
0
80
16
14
80
16
14
SO
10
9
SO
10
9
TEXAS
SN54HC4017
MIN
6
31
36
MAX
SN74HC4017
MIN
MAX
ou..
-w
2
UNIT
(.)
MHz
ns
2
«
>
c
«
ns
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-147
TYPES SN54HC4017, SN74HC4017
DECADE COUNTERS/DIVIDERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted),CL
50 pF (see Note 1)
=
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
f max
tpd
ClK
Any Y
Vcc
2V
4.5 V
6V
2V
4.5 V
tpd
ClK
CO
tpd
ClR
Any Y
6V
2V
4.5 V
6V
2V
4.5 V
CO
6V
2V
4.5 V
Any
6V
2V
4.5 V
tpd
tt
ClR
TA = 25°C
MIN
TVP· MAX
6
10
31
50
36
55
69
23
20
69
23
20
60
19
16
60
19
16
28
6V
II»
SN54HC4017
MIN
MAX
8
6
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
o
<
»
:2
n
m
:2
"o
:JJ
s:
»
-I
o:2
4-148
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SN74HC4017
MIN
MAX
UNIT
MHz
ns
ns
ns
ns
ns
TYPES SN54HC4022. SN74HC4022
OCTAL COUNTERS/DIVIDERS
HIGH·SPEED
CMOS LOGIC
02831. MARCH 1984
SN54HC4022 ... J PACKAGE
SN74HC4022 ... J OR N PACKAGE
•
Carry-Out Output for Cascading
•
Divide-by-N Counting
•
DC Clock Input Circuit Allows Slow Rise
Times
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
(TOP VIEW)
Y1
YO
Y2
Y5
Y6
NC
Y3
GND
description
VCC
ClR
ClK
ClKEN
CO
Y4
Y7
NC
SN54HC4022 ... FH OR FK PACKAGE
SN74HC4022 •.. FH OR FN PACKAGE
The 'HC4022 is a four-stage divide-by-8
Johnson counter with eight decoded outputs and
a carry-out bit. High-speed operation and spikefree outputs are obtained by use of the Johnson
octal counter configuration.
(TOP VIEW)
0
.... U
Ua;
U...J
>->-z>U
The eight decoded outputs are normally low and
go high only at their respective octal time
periods. A high signal on ClR asynchronously
clears the octal counter and sets the carry output
and YO high. With ClKEN low, the count is
advanced on a low-to-high transition at ClK.
Alternatively, if ClK is high, the count is
advanced on a high-to-Iow transition at ClKEN.
Each decoded output remains high for one full
clock cycle. The carry output CO is high while
YO, Y1, Y2, or Y3 is high, then is low while Y4,
Y5, Y6, or Y7 is high.
II
2
o
t=
c
«
Pin 'numbers shown are for J and N packages.
ADVANCE INFORMATION
This document contains information
on a new product. Specifications are
subject to change without notice.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright © 1984, Texas Instruments Incorporated
4-149
TYPES SN54HC4022, SN74HC4022
OCTAL COUNTERS/DIVIDERS
logic diagram (positive logic)
Y3
Y5
Y6
III
l>
o
~
Y7
co
Pin numbers shown are for J and N packages.
typical clear, count, and inhibit sequences
2
o
nn
Z
o
ClK
~
___ ________________________
~
."
~
YO
:IJ
s:l>
-I
o
2
Y1 ____
~r-1'
________~______--Jr-1
I~---I
~~r-1~------------------~
Y2 ______
~-J~~----------------~---Jr-1~---
Y3 _ _ _~~_~r-1
~
Y4 ____~--------~r-1
r--
~~--------~~~----------~---------____~---------------Jr-1.~------~----------____~~--------------~r-1~--~------------
Y5 ____
Y6
Y7
co
~ClEAR-.j
4-150
INHIBIT--f4-t.f
...
I.I------COUNT----~.I
j4--COUNT---'
TEXAS •
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS. TeXAS 75265
TYPES SN54HC4022, SN74HC4022
OCTAL COUNTERS/DIVIDERS
maximum ratings. recommended operating conditions. and electrical characteristics
See Table IV, page 2-10.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
MAX
MIN
VCC
Clock frequency
fclock
Pulse duration. ClK high or low.
tw
ClKEN high or low. or ClR high
Setup time. ClKEN low
tsu
or ClR inactive
SN54HC4022
MIN
SN74HC4022
MIN
MAX
2V
0
6
0
MAX
4.2
0
5
4.5 V
0
31
0
21
0
25
6V
0
36
0
25
0
29
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
50
75
65
4.5 V
10
15
13
6V
9
13
11
UNIT
MHz
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
f max
TA = 25°C
MIN
TYP MAX
VCC
2V
6
10
4.5 V
31
6V
36
tpd
tt
ClK or ClR
ClK or ClR
Any Y
CO
Any
MAX
SN74HC4022
MIN
4.2
5
50
21
25
55
25
29
MAX
70
24
230
345
46
69
58
6V
20
39
59
49
2V
60
230
345
290
4.5 V
19
46
69
58
6V
16
39
59
49
2V
38
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
Power dissipation capacitance per counter
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
UNIT
MHz
4.5 V
2V
tpd
SN54HC4022
MIN
290
100 pF typ
ns
II
2
ns
o
i=
C
C
<
l>
2
o
m
2
o
"t1
:lJ
s:
l>
::!
o
2
4-152
TYPES SN54HC7022, SN74HC7022
OCTAL COUNTERS/DIVIDERS WITH POWER·UP CLEAR
HIGH·SPEED
CMOS LOGIC
02804, MARCH 1984
SN54HC7022 ••• J PACKAGE
SN74HC7022 ••• J OR N PACKAGE
•
Carry·Out Output for Cascading
•
Divide-by-N Counting
•
DC Clock Input Circuit Allows Slow Rise
Times
(TOP VIEW)
Y1
•
Power-Up Reset
•
Pin-Out Compatible with 'HC4022
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
1 U16
2
15
14 F
3
YO
Y2
Y5
Y6
XCAP
Dependable Texas Instruments Quality and
Reliability
4
13
CO
12
Y4
11
10 ;; Y7
5
6
Y3
7
GND
8
VCC
ClR
ClK
CIi<"EN
ClROUT
9
SN54HC7022 ••• FH OR FK PACKAGE
SN74HC7022 ••• FH OR FN PACKAGE
(TOP VIEW)
description
The 'HC7022 is a four-stage divide-by-8
Johnson counter with eight decoded outputs and
a carry-out bit. High-speed operation and spikefree outputs are obtained by use of the Johnson
octal counter configuration.
The eight decoded outputs are normally low and
go high only at their respective octal time
periods. A high signal on ClR asynchronously
clears the octal counter and sets the carry output
and YO high. With ClKEN low, the count is
advanced on a low-to-high transition at ClK.
Alternatively, if ClK is high, the count is
advanced on a high-to-Iow transition at ClKEN.
Each decoded output remains high for one full
clock cycle. The carry output CO is high while
YO, Y1, Y2, or Y3 is high, then is low while Y4,
Y5, Y6, or Y7 is high.
This part is similar to the 'HC4022; the main
difference is that it includes a power-up-clear
circuit to reset the counter during the power-up
of the device. The active-low open-drain clear
output, ClROUT, can be used to clear or reset
external circuitry. The pulse duration of the
power-up reset circuit can be controlled with an
external capacitor Cext connected to pin XCAP.
If XCAP is connected to VCC, the power-up
reset function is bypassed.
0
... U
3
2
uUa:
....
»z>u
ClK
ClKEN
NC
Y2
Y5
NC
CO
Y6
XCAP
14
II
Y4
9 10111213
"
> CUll::>.>
0
('I)
Z
2
Z
l!)
o
i=
C
5
CLR (15)
6
CT=O
CT<4
The SN54HC7022 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC7022 is
characterized for operation from - 40°C to
85°C.
1=1
-"'~VI
< 1.8V
(See Notel
oZ
XCAP~(6~1...............~~.............................................~
NOTE:
The output of the each threshold detector is logically high until the input voltage exceeds the threshold level, typically 1 .7 volts.
Pin numbers shown are for J and N packages.
31
4-154
TEXAS •
INSTRUMENlS
POST OFFiCe BOX 225012 • DALLAS. TeXAS 75265
TYPES SN54HC7022, SN74HC7022
OCTAL COUNTERS/DIVIDERS WITH POWER·UP CLEAR
typical power-up clear, count,' and inhibit sequences
VCC
----r
,_ .
~I
INTERVAL DETERMINED BY Cext
I
ClROUT
ClK
ClKEN __________________________________________~~~___________
I
I
I
I
YO~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~r_l
I
I
I
Y1
r--l~
______________________~
I
I
Y2
r--l~
______________________~~r-l~-----
Y3 ________________~~~________________~__~__~~
Y4 ________
Y5 ____________
Y6 ________
r--
~--------~r-l
~----------~r-l~------------~--------------
~------------------~r--l~----------~------------
Y7 ________________________________~r__l~
CO _ _ _ _ _ _ _
+-CLEAR--+l
I
I
I
____________________
I
I
I
I
INHIBIT+-+!
~M---------------COUNT-------------+l~1
L
ft---COUNT-----+
II
2:
o
i=
2
C
-«UU>-«
(,,)N~Z>~N
4
3
2
1 282726
38
68
4CLK
6Y
II
6A
4D
NC
5CLK
5PRE
4Q
5D
NC
4PRE
:2
o
i=
C
c
«
2·INPUT NOR GATE
FUNCTION TABLE
INPUTS
6Y
OUTPUT
A
B
H
X
L
X
H
L
L
L
H
positive logic: Y =
Y
A+'B
or Y =
A.'B
Pin numbers shown are for JT and NT packages.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-159
TYPES SN54HC7074, SN74HC7074
6·SECTION MULTIFUNCTION
(NAND, INVERT, NOR, FLlp·FLOP) CIRCUITS
absolute maximum ratings, recommended operating conditions, electrical characteristics
For D-type flip-flops, see Table II, page 2-6. For gates and inverters, see Table I, page 2-4.
timing requirements for each D-type flip-flop over recommended operating free-air temperature range
(unless otherwise noted)
vCC
fclock
Clock frequency
tw
Pulse duration
PRE low. ClR low.
ClK high. or
ClK low
tsu
Setup time
before ClKt
PRE high. or
th
II
2V
4.5 V
Data.
ClR high
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
Hold time. data after ClK t
TA = 25°C
MIN
MAX
5
0
25
0
29
0
100
20
17
100
20
17
5
SN54HC7074
MIN
MAX
0
3.3
0
17
0
20
150
30
25
150
5
5
SN74HC7074
MIN
MAX
0
4
0
20
0
24
125
25
21
125
30
25
25
21
5
5
5
5
5
5,
UNIT
MHz
ns
ns
ns
switching characteristics for each D-type flip-flop over recommended operating free-air temperature
range (unless otherwise noted). CL = 50 pF (see Note 1)
PARAMETER
»
c
<
»
2
FROM
(INPUT)
TO
(OUTPUT)
2V
4.5 V
6V
2V
4.5 V
6V
2V
f max
tpd
ClK
Q
tpd
ClK
Q
("')
m
VCC
2
TA = 25°C
MIN TYP MAX
5
10
25
50
29
60
45
15
13
45
4.5 V
15
6V
13
SN54HC7074
MIN
MAX
3.3
17
20
SN74HC7074
MIN
4
20
24
MAX
UNIT
MHz
ns
ns
"T1
o
:D
s:
»
switching characteristics for gates and inverters over recommended operating free-air temperature
range (unless otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
:::!
o
2
tpd
tt
FROM
(INPUT)
A or B
TO
(OUTPUT)
VCC
TA = 25°C
MIN JYP MAX
30
10
Y
2V
4.5 V
9
38
Y
6V
2V
4.5 V
6V
6
SN54HC7074
MIN
MAX
8
SN74HC7074
MIN
MAX
UNIT
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
4-160
-II}
TEXAS
INSTRUMENTS
POST OFFice BOX 225012 • DALLAS. TeXAS 75265
3
TYPES SN54HC7074, SN74HC7074
6·SECTION MULTIFUNCTION
(NAND, INVERT, NOR, FLlP·FLOP) CIRCUITS
TYPICAL APPLICATION DATA
.&
(1)
~m
1
(2) . /
1
(10) ........ R
PR'E
(17) ......... S
'HCOO
(11)
...... (9)
10
(18)
~
..
~
C1
erR
:I
..
ClK
S
(6)
(8)
RESET 1
RESET 2
(3)
(4)
171 ........
1
(22)
&
(5) . /
2Q
...... (23)
(13)
C2
i'-.. (15)
20
Q
Q
RESET
RESE'i'
(14) ........ R
t
~
-
;;>1
(21)
r-....
(19)
II
2
o
FIGURE 1. CLOCK AND RESET GENERATION FOR MICROPROCESSOR·BASED SYSTEM
i=
C
1Il1Il
4
3 2
1
B3
B4
B5
NC
B6
B7
B8
A3 5
A4 6
A5
NC
A6
A7
A8
logic symbol
GA
VCC
B1
B2
B3
B4
B5
B6
B7
B8
GB
NC
ClK
(10)
GB (15)
2
o
i=
NC - No internal connection
A 1 ..;.;12.;.;;)_._--i
~
FUNCTION TABLE
A2..;.;13;.;.)_....~
A3 (4)
INPUTS
1 - - - - - - 1 . ........
. ---'0;;......;.
I/O
OUTPUT
CLR
CLK
GA
GB
A
B
L
X
X
X
X
t
L
L
L
H
L
H
L
Z
H
H
L
Z
Z
H
H
A4 ..;.;15;';')_+-I~
A5 (6)
A6
~----------~
L
l
l
_17_)_...,~
A7 IS)
t-------L
H
H
H
H
H
H
H
H
H
AS (9)
Pin numbers shown are for JT and NT packages.
4
ADVANCE INFORMATION
This document contains information
on a naw product. Specifications ara
subject to change without notice.
TEXAS
W
-1!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TeXAS 75265
L
H
00
00
00
L
L
L
H
t
t
H
H
H
L
L
l
L
C
A4 (5)
0
<
>
2
A5 (6)
0
m
2
."
0
A6 (7)
:a
3:
l>
-f
0
A7 (8)
2
A8~(9~1_. ._e.-----~~--~
Pin numbers shown are for JT and NT packages ..
4-164
TEXAS
-I/}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
31
TYPES SN54HC7340, SN74HC7340
OCTAL BUS DRIVERS WITH BIDIRECTIONAL REGISTERS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table 11/, page 2-8.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
Clock high
or low
tw
Pulse duration
Clear low
Data
Setup time
tsu
before ClK t
Clear inactive
th
Hold time. data after ClK t
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
MAX
0
5
a
25
0
29
100
20
17
100
20
17
100
20
17
100
20
17
0
0
0
SN54HC7340
MAX
MIN
3.3
0
17
0
19
0
150
30
26
150
30
26
150
30
26
150
30
26
0
0
0
SN74HC7340
MIN
MAX
4
0
20
a
24
a
125
25
21
125
25
21
125
25
21
125
25
21
a
a
a
UNIT
MHz
ns
ns
ns
ns
ns
II
2:
o
i=
C
.....
IX
1C ex t
10
1CLR
10
NC
NC
20
20
2CLR
,2C ex t
The SN54HC123 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC123 is
characterized for operation from - 40°C to
85°C.
>
w
0-
J-
(.,)
::l
C
o
IX
~~ ~ ~ ~
0-
~(,!)
x
Q)
a:
N
FUNCTION TABLE
NC - No internal connection
OUTPUTS
INPUTS
CLEAR
A
B
0
0
L
Lt
H
Ht
L
X
X
X
H
X
X
X
L
Lt
H
L
t
H
't
~
H
Sl
Sl
L
H
.n..
logic symbol
Ht
1A
'LJ'
'LJ'
U
18
1CLR
tThe second and third lines each indicate the
logic levels the outputs will take on after the
completion of any pulse already started.
1Cex t
I1..
(1 )
(2)
(13)
(4)
(3)
10
10
(14)
(15)
1 Rext/Cext
2A
28
2CLR
2Cex t
2R ex t /Cext
...n..
(9)
(10)
(11 )
(5)
(12)
20
20
(6)
(7)
Pin numbers shown are for J and N packages.
PRODUCT PREVIEW
This document contains infonnation on a product under
development. Tex.llnstruments raserve. the right to
change or discontinue this product without notice.
Copyright © 1982, Texas Instruments Incorporated
-I/}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
5-3
TYPES SN54HC123, SN74HC123
RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
RETRIGGER PULSE
BINPUT~
OUTPUTQ
r-=J,L----------~I~--I+--tw + tpHL -----:
L________ L
J
14--- tw
'" I OUTPUT WITHOUT RETRIGGER
OUTPUT PULSE CONTROL USING RETRIGGER PULSE
BINPUT~~________________________
CLEAR
OUTPUT Q
"tJ
::xJ
-4
0
OUTPUT WITHOUT CLEAR
L,I-_-_-_-_-_-_'...:,.:_____________
OUTPUT PULSE CONTROL USING CLEAR INPUT
o
o
c::
(")
J
FIGURE 1 - TYPICAL INPUT/OUTPUT PULSES
maximum ratings, recommended operating condi~Jions, and electrical characteristics
See Table IV, page 2-10.
"tJ
::xJ
m
<
iii
~
t/)
lEI
3
5-4
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC132. SN74HC132
SCHMITT·TRIGGER POSITIVE·NAND GATES WITH TOTEM·POLE OUTPUTS
02684, DECEM8ER 1982-REVISED MARCH 1984
SN54HC132 .•. J PACKAGE
SN74HC132 .•. J OR N PACKAGE'
(TOP VIEW)
•
Operation from Very Slow Transitions
•
Temperature-Compensated Threshold Levels
•
High Noise Immunity
VCC
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
48
4A
4Y
38
•
Dependable Texas Instruments Quality and
Reliability
3A
....,.
. .- 3Y
description
SN54HC132 ... FH OR FK PACKAGE
SN74HC132 ... FH OR FN PACKAGE
Each circuit functions as a NAND gate, but
because of the Schmitt action, it has different
input threshold levels for positive- and negativegoing signals. It performs the Boolean function
y = A-B or Y = A+B in positive logic.
(TOP VIEW)
en
~
w
These circuits are temperature compensated and
can be triggered from the slowest of input ramps
and still give clean jitter-free output signals.
:>
w
a:
a.
The SN54HC132 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC132 is
characterized for operation from - 40°C to
85°C.
I-
(.)
::l
C
NC-No internal connection
logic symbol
FUNCTION TABLE (each gate)
lA (1)
&.0'
INPUTS
lB (2)
2A (4)
2B (5)
3A (9)
OUTPUT
Y
A
B
H
H
~
L
X
H
X
L
H
o
a:
a.
II
3B (10)
4A (12)
4B (13)
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
PRODUCT PREVIEW
This document contains Information on a product under
development. Texa. Instrument. r••• rv•• tha right to
change or discontinue this product without notlc •.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright © 1982, Texas Instruments Incorporated
5-5
TYPES SN54HC132, SN74HC132
SCHMITT·TRIGGER POSITIVE·NAND GATES WITH TOTEM·POLE OUTPUTS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 50 pF' (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
y
tt
Any
vCC
=
TA
25°C
MIN
TYP MAX
SN54HC132
MIN.
SN74HC132
MIN
MAX
UNIT
40
2V
4.5 V
6V
13
11
2V
28
4.5 V
8
6V
6
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
5-6
MAX
TEXAS •
INSTRUMENlS
POST OFFice BOX 225012 • DALLAS. TeXAS 75265
ns
ns
34
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC182, SN74HC182
LOOK·AHEAD CARRY GENERATOR
02804, MARCH 1984
•
Offers Carry Functions in a Compatible Form
for Direct Connections to the ALU
•
Cascadable to Perform Look-Ahead Across
n-Bit Adders
SN54HC182, •. J PACKAGE
SN74HC182 ... J OR N PACKAGE
(TOP VIEW)
•
VCC
P2
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
G2
Cn
Cn + x
Cn + y
Dependable Texas Instruments Quality and
Reliability
G
GND~;"'-';"'-';J-Cn+z
PIN DESIGNATIONS
ALTERNATIVE
DESIGNATIONS t
FUNCTION
GO, Gl, G2, G3
GO,Gl,G2,G3
Carry Generate Inputs
PO, Pl, P2, P3
PO, Pl, P2, P3
Carry Propagate Inputs
Cn
Cn + X , Cn + y ,
Cn
Cn + X , Cn + y ,
Carry Input
Cn + z
G
Cn + z
y
Carry Generate Output
P
X
Carry Propagate Output
SN54HC182 ... FH OR FK PACKAGE
SN74HC182 .•. FH OR FN PACKAGE
(TOP VIEW)
.--.-- U
(e..lt!) z
Carry Outputs
VCC
GND
3
Supply Voltage
Ground
2
en
U
UN'
~
w
> Ie..
1 2019
GO
PO
<32
NC
NC
Cn + x
Cn
G3
t Interpretations are illustrated in connection with the Function Tables for
the 'HC181 and 'HC88l.
Cn + y
9 1011 1213
Ie.. 0 uNIt!)
Z Z +
t!)
description
cJ
The 'HC182 look-ahead carry generators are
capable of anticipating a carry across four binary
adders or group of adders. They are cascadable
to perform full look-ahead across n-bit adders.
NC-No internal connection
This generator, when used in conjunction with the 'HC181 or 'HC881 Arithmetic Logic Unit ALU, provides
high-speed carry look-ahead capability for any word length. The 'HC182 generates the look-ahead
(anticipated carry) across a group of four ALUs. In addition, other carry look-ahead circuits may be employed
to anticipate carry-across sections of four look-ahead packages up to n-bits.
:>
w
a:
a.
~
(.)
::l
C
oa:
a.
II
The carry functions (inputs, outputs, generate, and propagate) of the look-ahead generators are implemented
in the compatible forms for direct connections to the ALU. Reinterpretations of carry functions as explained
on the 'HC181 and 'HC881 data sheet are also applicable to and compatible with the look-ahead generator.
Logic equations for the 'HC182 are:
Cn+x = GO + PO Cn
Cn+y = Gl + Pl GO + Pl PO Cn
Cn+z = G2 + P2 Gl + P2 Pl GO + P2 Pl PO Cn
G = G3 + P3 G2 + P3 P2 Gl + P3 P2 Pl GO
P = P3 P2 Pl PO
or
Cn +x = YO (XO + Cn)
C n +y = Yl [Xl + YO (XO + Cn)]
Cn+z = Y2 {X2 + Yl [Xl + YO (XO + Cn)]}
Y = Y3 (X3 + Y2) (X3 + X2 + Yll (X3 + X2 + Xl + YO)
X = X3 + X2 + Xl + XO
maximum ratings recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
Copyright
PRODUCT PREVIEW
This document contains information on a product under
development. Texasln.trumants reserv.s the right to
change or discontinue this product without notice.
TEXAS
-IJ}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
© 1983 by Texas Instruments Incorporated
5-7
TYPES SN54HC182, SN74HC182
LOOK·AHEAD CARRY GENERATOR
FUNCTION TABLE FOR
G OUTPUT
INPUTS
FUNCTION TABLE
FUNCTION TABLE
OUTPUT
G3
G2
Gl
GO
P3
P2
Pl
G
L
X
X
X
X
X
L
L
L
X
X
X
L
L
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
All other
H
combinations
L
All other combinations
FOR Cn + x OUTPUT
INPUTS
OUTPUT
FORi> OUTPUT
INPUTS
L
P3
L
L
FUNCTION TABLE Cn + y OUTPUT
INPUTS
OUTPUT
P2
Pl
PO
L
L
L
OUTPUT
GO
PO
Cn
Ii"
L
X
X
Cn + x
H
L
X
L
H
H
All other
H
combinations
FUNCTION TABLE FOR Cn + z OUTPUT
INPUTS
OUTPUT
Gl
GO
Pl
PO
Cn
Cn + y
G2
Gl
GO
P2
Pl
PO
Cn
L
X
X
L
L
X
X
L
L
X
X
X
X
X
X
L
H
H
H
X
X
X
X
H
L
X
X
X
X
X
X
L
L
L
X
X
X
X
X
X
X
L
.L
L
H
All other
combinations
L
L
L
All other combinations
Cn + z
H
H
H
H
L
P2orX27(1~5~)~~--rT4-~
G2orV2~(1~4~)~----rT~~
-
(2)
PlorXl~(l~)-+~---r~-+~
GlorVl~-+-----r+--+~
Pin numbers shown are for J and N packages only.
3!
5-8
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
).100
TYPES SN54HC221. SN74HC221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMITT·TRIGGER N
HIGH·SPEED
CMOS LOGIC
DECEMBER 19B2 - REVISED
•
Overriding Clear Terminates Output Pulse
•
Package Options Include Both Plastic
and Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
SN54HC221 ... J PACKAGE
SN74HC221 ... J OR N PACKAGE
(TOP VIEW)
lA
lB
lClA
Dependable Texas Instruments Quality
and Reliability
VCC
1 Aext/Cext
lCext
10
20
2ClA
10
20
description
2C ex t
2Aext/Cext
GND
These devices are monolithic dual multivibrators featuring a
negative-transition-triggered input and a positive-transitiontriggered input either of which can be used as an inhibit input.
2B
2A
SN54HC221 .•. FH OR FK PACKAGE
SN74HC221 ... FH OR FN PACKAGE
. (TOP VIEW)
Pulse triggering occurs at a particular voltage level and is not
directly related to the transition time of the input pulse. Schmitttrigger input circuitry for the B input allows jitter-free triggering
from inputs with slow transition rates.
en
~
w
Once fired, the outputs are independent of further transitions of
the A and B inputs and are a function of the timing components,
or the output pulses can be terminated by the overriding clear.
Input pulses may be of any duration relative to the output pulse.
Output rise and fall times are independent of pulse length.
5>
w
Pulse duration stability is achieved through internal compensation and is virtually independent of VCC and temperature. In
most applications, pulse stability will be limited only by the
accuracy of external timing components.
lClA
4
10
NC
20
5
6
7
2C ext
8
The SN54HC221 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC221
is chara~terized for operation from -40°C to 85°C.
a:
lCext
10
NC
20
2ClA
Q.
I-
o
::::>
c
oa:
;cOU<{al
(liZ Z
~t!)
N
N
Q.
;c
(II
II
a:
N
NC-No internal connection
FUNCTION TABLE
(EACH MONOSTABlE)
logic symbol
INPUTS
CLEAR
A
l
X
X
H
H
I
OUTPUTS
B
Q
Q
X
H
X
X
l
'H
X
l
I
l
I
H
H
It
It
Ht
Ht
l
1.n.
1A
1B
(13)
(41
lCLR
JL U
JL U
10
10
lCext
1 Aext/Cext
JL 1..J
1rL
2A
tThe second and third lines each indicate
the logic levels the outputs will take on
after the completion of any pulse already
started.
2B
2CLR
2Cext
2Aext / Cext
111
(51
20
121
20
CX
RX/ex
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
NOTE: The minimum recommended supply voltage for this device is 3 V.
PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.
Copyright. ©1982 by Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS, TEXAS 75265
5-9
."
:D
o
C
c
n
-I
."
:D
m
S
m
:E
tn
II
5-10
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC292, SN54HC294, SN74HC292, SN74HC294
PROGRAMMABLE FREQUENCY DIVIDERS/DIGITAL TIMERS
02804, MARCH 1984
•
Count Divider Chain
•
Digitally Programmable from 22 to 2 31 for
'HC292 or 2 1 5 for 'HC294
•
Usable Frequency Range from DC to
30 MHz
•
Easily Expandable
•
Applications
Frequency Division
Digital Timing
SN54HC292 , , , J PACKAGE
SN74HC292 , , , J OR N PACKAGE
(TOP VIEW)
B
E
1 U16
TP1
ClK1
ClK2
TP2
14
13
12
11
VCC
C
D
TP3
NC
ClR
Q
10
A
15
NC
GND
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN54HC292 •.• FH OR FK PACKAGE
SN74HC292 •.. FH OR FN PACKAGE
(TOP VEIW)
•
Dependable Texas Instruments Quality and
Reliability
walZ>U
description
These
are
programmable
frequency
dividers/digital timers whose count modulo is
under digital control of the inputs provided.
Both types feature an active-low clear input to
initialize the state of all flip-flops. To facilitate
incoming inspection, test points are provided
(TP1, TP2, and TP3 on the 'HC292 and TP on
ths 'HC294). These test points are not intended
to drive system loads. Both types feature two
clock inputs; either one may be used for clock
gating. (See the function table.)
U
The sN54HC292 and sN54HC294 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
sN74HC292 and sN74HC294 are characterized
for operation from -40°C to 85°C.
en
~
TP1
ClK1
NC
ClK2
TP2
W
D
>
w
TP3
NC
NC
ClR
a:
c.
l-
t..)
::)
OOUUU
D
NC
NC
NC
ClR
TP
ClK1
NC
OOUUU
ZZZZ
l!l
NC-No internal connection
Copyright © 1984, Texas Instruments Incorporated
PRODUCT PREVIEW
Thb document contains information on • product under
devalopment. Tax•• In.trumanU ra.arve. the right to
change
discontinue thI. product without" notice.
0'
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
5-11
TYPES SN54HC292, SN54HC294, SN74HC292, SN74HC294
PROGRAMMABLE FREQUENCY DIVIDERS/DIGITAL TIMERS
;HC292, 'HC294 FUNCTION TABLE
CLEAR
CLK 1
CLK 2
Q OUTPUT MODE
L
X
Cleared to L
H
H
H
H
t
X
L
Count
H
t
X
Inhibit
X
H
Inhibit
L
Count
operation
The logic diagram shows that the count modulo is controlled by an X/V decoder connected to the modecontrol inputs of several flip-flops. These flip-flops with mode controls each have a "D" input connected
to the parallel clock line and a "T" input driven by the preceding stage. The parallel clock frequency is
always the input frequency divided by four .
."
The X/Y decoder output selected by the programming inputs goes low. While a mode control is low, the
"D" input of that flip-flop is enabled, and the signal from the parallel clock line (fin -;- 4) is passed to the
"T" input of the following stage. All the other mode controls are high enabling the "T" inputs and causing
each flip-flop in turn to divide by two.
::D
o
C
C
o
-I
PARALLEL CLOCK - - -......-
."
2D
::D
m
OUTPUT OF
PRECEDING
STAGE -
S
m
~
,-----
ACTIVE·LOW CLEAR
R
TO TOGGLE
INPUT OF
NEXT STAGE
.....o(V 2T
FROM
en
x/v
1iII091C
CODER
symbols
'HC294
'HC292
[~J
CLK1
CLK2
[fil
(3)
[TP1)
(6)
[TP2)
(13)
[TP3)
A (10)
B (1)
C (15)
o
(14)
E (2)
}1"1~1
ro=~
(7)
TP1
TP2
TP3
~ 2n'f;~
fo =
Q
Pin numbers shown are for J and N packages.
5-12
[TP)
[til
TEXAS
-I!}
INSTRUMENTS
POST 'OFFICE BOX 225012 • DALLAS. TEXAS 75265
(3)
(7)
TP
Q
TYPES SN54HC292, SN74HC292
PROGRAMMABLE FREQUENCY DIVIDERS/DIGITAL TIMERS
'HC292 logic diagram (positive logic)
~'-'o-~""",-o--e----...--.......~~-e--.......--.---,
CLR (111
rI
CLK1~41
-
-
R
R
I:>TC~T
CLK2 (51
x/v
oU
t-t.......- - t -.......-+--+-+t--t---,
'---
~J-.Jl
r----e---41'~T
20 R
C~2TC
.J
R
))
t: >T
l
~E::13::::::=--~M~2~~C~~==~CtP~P
~31
c~
C
26 "
.Jl
24
TP1
W
T T
>
w
Ib !
20
R
R
C
_j
l..c~2TC~T
M2
22 h.
20~
cpa
c~ cj:>
18 h
16
a:
c..
') ')
~
l
J
Cp Cp
C
~TP2
t-
O
:::l
C
oa:
c..
T
]11
o.!.l!!1--
en
~
lOR
R
LoP.2TCPTCp
8
14Cr---+-+----tM2
')
.J~
1
c~
1;;'R
cpa
12....
10 ....
Cp
C
;:>2T
~
8....
r
II
131
TP3
T
~---------~~-------------------~~
Pin numbers shown are for J and N packages.
4
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
5-13
TYPES SN54HC294. SN74HC294
PROGRAMMABLE FREOUENCY DIVIDERS/DIGITAL TIMERS
'HC294 logic diagram (positive logic)
""C
JJ
o
C
C
("')
-I
""C
JJ
m
<
m
~
c
(15)
o
(14)
4
rJ)
II
6o-------------~
5D-----------------~
4D---------------------~
3D-------------------------~
2D-----------------------------~
Pin numbers shown are for J and N packages.
5-14
-I.!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
31
TYPES SN54HC292, SN74HC292
PROGRAMMABLE FREQUENCY DIVIDERS/DIGITAL TIMERS
'HC292 FUNCTION TABLE
FREQUENCY DIVISION
PROGRAMMING
Q
INPUTS
E
D
C
B
A
BINARY
DECIMAL
BINARY
TP3
TP2
TP1
DECIMAL
BINARY
DECIMAL
BINARY
DECIMAL
L
L
L
L
L
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
L
L
L
H
Inhibit
22
23
Inhibit
Inhibit
29
Inhibit
Inhibit
Inhibit
L
L
L
L
H
L
L
L
H
H
L
L
H
L
L
L
L
L
H
L
H
L
L
H
H
L
L
H
H
L
H
L
L
H
L
L
L
L
L
H
4
8
~
25
16
32
64
128
2B
27
28
256
512
L
H
L
H
L
29
2 10
L
H
H
H
211
2,048
L
H
L
H
L
L
4,096
L
H
H
L
H
212
2 13
L
H
H
H
L
H
H
H
H
L
H
214
2 15
L
L
L
L
2 16
217
2 18
H
H
L
L
H
H
L
L
L
H
H
L
L
H
H
H
L
H
L
L
1,024
131,072
Inhibit
224
29
29
512
217
131,072
224
16,777,216
512
217
131,072
~4
16,777,216
29
29
512
217
131,072
224
16,777,216
512
131,072
224
16,777,216
29
29
29
512
217
217
131,072
224
16,777,216
512
512
217
131,072
131,072
22
22
4
4
29
29
512
512
217
217
512
8,192
29
29
217
217
512
217
16,384
32,768
29
29
512
512
65,536
29
29
512
29
29
512
29
29
512
131,072
262,144
2 19
220
512
Inhibit
217
524,288
1,048,576
512
512
131,072
~
16
131,072
~
26
64
131,072
131,072
Disabled Low
26
28
Disabled Low
23
28
2 10
23
25
16,777,216
8
16
64
256
256
1,024
32
2 10
212
4,096
8
1,024
25
27
32
212
4,096
128
214
16,384
128
214
16,384
512
216
65,536
512
216
65,536
2,048
262,144
H
L
H
L
L
H
221
2.097.152
H
L
H
H
L
222
4,194,304
Disabled Low
27
29
H
L
H
H
H
223
8,388,608
H
H
L
L
L
16,777,216
29
211
H
H
L
L
H
224
2 25
Disabled Low
23
33,554,432
23
8
211
2,048
218
2 18
H
H
L
H
L
226
67,108,864
32
220
1,048,576
H
L
H
H
134,217,728
8,192
H
H
H
L
L
227
228
2 13
2 13
8,192
H
25
25
268,435,456
27
128
32,768
220
222
4,194,304
H
H
H
536,870,912
1,073,741,824
27
29
32,768
222
4,194,304
H
229
230
128
H
H L
H·H
215
2 15
512
217
131,072
224
16,777,216
H
H
H
231
2,147,483,648
29
512
217
131,072
224
16,777,216
H
L
H
512
8
32
262,144
1,048,576
en
::w
:>w
a:
0..
lt.)
::J
C
oa:
0..
II
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
34
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
5-15
TYPES SN54HC294, SN74HC294
PROGRAMMABLEFREOUENCY DIVIDERS/DIGITAL TIMERS
'HC294 FUNCTION TABLE
FREQUENCY DIVISION
Q
PROGRAMMING INPUTS
TP
D
C
B
A
BINARY
DECIMAL
BINARY
DECIMAL
L
L
L
L
L
Inhibit
Inhibit
Inhibit
Inhibit
L
Inhibit
29
Inhibit
L
L
H
H
Inhibit
22
23
Inhibit
L
L
H
L
H
L
H
L
z4
16
L
L
H
H
L
L
H
25
26
64
L
H
H
H
H
L
L
L
H
L
L
H
'"C
H
L
H
o
H
L
H
H
H
H
H
H
H
H
H
:xJ
C
C
o
-I
'"C
:xJ
m
<
H
L
L
27
28
4
8
32
29
29
512
512
512
29
29
512
512
Disabled Low
128
512
22
23
L
29
2 10
1,024
:z4
16
H
211
2,048
25
32
L
L
H
212
2 13
4,096
L
H
H
L
H
214
2 15
16,384
32,768
~
27
28
29
128
256 .
256
8,192
4
8
64
512
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
iii
~
en
II
38
5-16
TEXAS . .
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC381, SN54HC382
SN74HC381, SN74HC382
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
HIGH·SPEED
CMOS LOGIC
02804, MARCH 1984
SN54HC381 .•• J PACKAGE
SN74HC381 ••. J OR N PACKAGE
(TOP VIEW)
• Fully Parallel 4-8it ALUs in 20-Pin Package
• Ideally Suited for High-Density Economical
Processors
• 'HC381 Features G and
Ahead Carry Cascading
P Outputs
Vcc
A1
61
AO
60
SO
S1
S2
FO
F1
GNO
for Look-
• 'HC382 Features Ripple Carry (C n +4) and
Overflow (OVR) Outputs
• Arithmetic and Logic Operations Selected
Specifically to Simplify System
Implementation:
A Minus 8
8 Minus A
A Plus 8
and Five Other Functions
A2
62
A3
B3
Cn
p
G
F3
F2
SN54HC381 •.. FH OR FK PACKAGE
SN74HC381 .•• FH OR FN PACKAGE
(TOP VIEW)
en
U
0 _ - UN
«m«>«
• Package Options Include 80th Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
60
SO
Sl
S2
FO
• Dependable Texas Instruments Quality and
Reliability
~
w
:>w
62
A3
63
a:
Cn
Q.
p
I-
description
-
The 'HC381 and 'HC382 are arithmetic logic
units (ALUs)/function generators that perform
eight binary arithmetic/logic operations on two
4-bit words as shown in the function table. The
Exclusive-OR, AND, or OR function of the two
800lean variables is provided without the use of
external circuitry. Also the F outputs can be
cleared (low) or preset (high) as desired. The
'HC381 provides two cascade outputs (P and (3)
for
expansion
utilizing
SN54HC182/
SN74HC182 look-ahead carry generators. The
'HC382 provides a Cn + 4 output to ripple the
carry to the Cn input of the next stage. The
'HC382 detects and indicates two's
complement overflow condition via the OVR
output. The overflow output is logically eqivalent
to Cn + 3 Et> Cn + 4· When the 'HC382 is
cascaded to handle word lengths longer than
four bits in length, only the most significant
overflow (OVR) output is used.
PRODUCT PREVIEW
ThIa doc:unaIt contalna Infonnatlon an a product I.WIder
development. Texa.ln.tNmenlll re ..rve. the right to
change or discontinue this produc:t without notice.
TEXAS
N
o
MIt!)
::J
t!)
C
oa:
SM54HC382 ••• J PACKAGE
SN74HC382 ••• J OR N PACKAGE
Q.
(TOP VIEW)
A1
61
AO
BO
SO
Sl
S2
FO
1 U20
II
VCC
4
19
18
17
5
16
A2
62
A3
B3
7
15
14
13
Cn
Cn +4
OVR
12
11
F3
F2
2
3
8
F1 ~ 9
GNO[ 10
SN54HC382 •.. FH OR FK PACKAGE
SN74HC382 .•. FH OR FN PACKAGE
(TOP VIEW)
U
0 _ - UN
«Ill«>«
The SN54HC381 and SN54HC382 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74HC381 and SN74HC382 are characterized
for operation from -40°C to 85°C.
14
0
u.zu.u.
B2
A3
B3
Cn
Cn +4
.J.!1
INSTRUMENTS
POST OFFICE BOX 225012 e DALLAS. TEXAS 75265
Copyright © 1984, Texas Instruments Incorporated
5-17
TYPES SN54HC381, SN54HC382
SN74HC381, SN74HC382
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
FUNCTION TABLE
SELECTION
ARITHMETIC/LOGIC
S2
S1
SO
OPERATION
L
L
L
CLEAR,
L
L
H
B MINUS A
L
H
H
L
L
H
L
H
L
H
A MINUS B
L
H
H
H
H
L
H
H
A PLUS B
A(±)B
A
+
B
AB
PRESET
H = high level, L = low level
logic symbols
"'0
:D
'HC381
0
C
so
'HC382
ALU
(5)
so
C
ALU
(5)
:}M4
(6)
n
S1
S2 (7)
-I
"'0
:D
m
5:
m
AO (3)
~
(1)
BO (4)
FO
en
B1
B2 (18)
(4)
(11)
(2)
F1
A2
F2
F2
(4)
Q
B2
OVR
A3 (17)
B3 (16)
FO
A1
F1
(2)
II
(1)
BO
Q
(8)
(12)
F3
A3
(17)
P
(8)
B3
(16)
Q
(12)
F3
function table
Certain differences exist in the <3, j5 ('HC381) and OVR, Cn +4 ('HC382) function table compared with
similar parts from other technologies and other vendors. No differences exist in the arithmetic modes (B
minus A, A minus B, and A plus B), where these outputs perform valuable cascade functions.
There are slight differences in other modes (CLEAR, A + B, A Et> B, AB, and PRESET) where these outputs
are strictly "don't care." The CMOS implementation will be the same as for the LSTTL counterparts from
Texas Instruments.
This function table is a condensed version and assumes for An that AO,A 1, A2, and A3 inputs all agree
and for Bn that BO, B1, B2, and B3 inputs all agree. This table is intended to point out the response of
these G, P ('HC381) and OVR, Cn + 4 ('HC382) outputs in all modes of operation to facilitate incoming
inspection.
5-18
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
31
TYPES SN54HC381, SN54HC382
SN74HC381, SN74HC382
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS·
FUNCTION TABLE
ARITHMETIC/LOGIC
OPERATION
Clear
B MINUS A
A MINUS B
A PLUS B
S2
L
L
L
L
S1
L
L
H
H
INPUTS
Cn
SO
An
Bn
X
X
X
L
L
L
L
H
H
H
L
L
H
H
L
H
L
L
H
H
L
L
L
L
H
H
H
H
H
L
L
H
H
L
L
H
H
L
L
L
L
L
H
L
H
H
H
H
H
L
L
L
H
H
H
H
L
L
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
L
L
H
L
H
H
L
L
H
H
L
H
L
H
H
X
X
X
X
L
H
L
H
X
A0B
H
L
L
L
H
L
H
X
X
L
A + B
AB
H
H
L
H
H
L
H
L
H
L
H
X
X
X
L
H
PRESET
H
H
H
L
H
L
H
H
L
L
L
H
H
H
L
L
H
F3
L
H
H
L
H
L
H
L
L
H
L
H
H
L
L
H
L
L
H
H
H
L
L
L
H
L
H
H
H
H
L
L
H
H
H
H
H
H
L
L
L
H
H
H
H
OUTPUTS
F2
F1
L
H
H
L
H
L
H
L
L
H
H
L
H
L
H
L
L
H
L
H
H
L
L
H
L
L
H
H
H
L
L
L
H
L
H
H
H
H
L
L
H
L
H
L
H
H
H
H
H
H
H
L
L
L
H
H
H
H
L
L
H
L
L
H
H
H
L
L
L
H
L
H
H
H
H
L
L
H
H
H
H
H
H
L
L
L
H
H
H
H
('HC381I
FO
G
P
L
H
L
L
H
L
H
H
L
H
H
H
L
H
H
L
L
H
H
H
L
L
H
L
H
H
L
L
H
H
L
H
L
L
H
L
H
H
H
H
L
L
H
H
H
H
H
H
L
L
L
H
H
H
H
L
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
L
L
L
L
L
L
H
H
H
L
L
L
L
,'HC382)
OVR
Cn +4
L
L
L
L
L
H
L
L
L
L
L
H
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
H
L
H
L
H
L
L
L
L
H
L
H
L
H
L
H
L
H
H
L
L
L
H
L
H
H
H
L
L
H
L
H
L
L
L
H
L
H
L
H
L
L
L
L
H
L
H
(J)
~
w
5=
w
a:
Q.
t-
O
::l
Q
oa:
Q.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
184
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
5-19
TYPES SN54HC381, SN54HC382
SN74HC381, SN74HC382
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
'HC381 switching 'characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL ... 50 pF (see Note 1)
FROM
(INPUT)
(OUTPUT)
tpd
Cn
Any F
tpd
tpd
tpd
"'C
TO
PARAMETER
Ai or Bi
50,51,
or 52
tpd
C
c:
MAX
SN74HC381
MIN
MAX
UNIT
36
12
ns
10
36
12
ns
6V
10
G orF>
2V
4.5 V
36
12
10
Fi
6V
2V
4.5 V
GorP
ns
52
17
ns
14
6V
2V
SO, Sl.
or S2
SN54HC381
MIN
2V
:xJ
o
TA .. 25°C
MIN
TVP MAX
4.5 V
6V
2V
4.5 V
Fi
Any A or B
vCC
4.5 V
50
17
6V
14
ns
("')
-I
"'C
:xJ
m
Power dissipation capacitance
100 pF typ
'HC382 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
S
PARAMETER
~
en
FROM
(INPUT)
TO
(OUTPUT)
tpd
Cn
Any F
m
tpd
tpd
OVR
Cn
Cn
Cn +4
tpd
Ai or Bi
Any A or B
2V
4.5 V
TA = 25°C
MIN
TVP MAX
36
12
6V
10
2V
36
4.5 V
12
6V
2V
10
Fi
Cn +4
tpd
Any A or B
SO, S1.
or S2
SO, S1,
tpd
or S2
OVR
Fi
Cn +4
or OVR
UNIT
ns
ns
ns
36
4.5 V
12
6V
2V
10
39
13
4.5 V
2V
11
42
4.5 V
14
6V
2V
12
52
4.5 V
17
6V
14
2V
4.5 V
60
20
17
6V
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
5-20
SN74HC382
MIN
MAX
10
6V
tpd
SN54HC382
MIN
MAX
33
11
4.5 V
6V
2V
-
tpd
VCC
TEXAS
-III
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
ns
ns
ns
ns
ns
TYPES SN54HC423, SN74HC423
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
HIGH·SPEED
CMOS LOGIC
02684, DECEM8ER 1982-REVISED MARCH 1984
•
Retriggerable for Very Long Output Pulses.
Up to 100% Duty Cycle
•
Overriding Clear Terminates Output Pulse
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality
and Reliability
SN54HC423 ... J PACKAGE
SN74HC423 ... J OR N PACKAGE
ITOPVIEW)
1A
1B
1CLR
VCC
1 Rext/Cext
1Cex t
10
20
2ClR
2B
2A
Hi
20
2Rext/Cext
GND
description
These dc-triggered multivibrators feature outputpulse-duration control by two methods. The basic
pulse duration is programmed by selection of external resistance and capacitance values. Once triggered, the basic pulse duration may be extended by
retriggering the gated low-level-active (A) or highlevel-active (B) inputs, or be reduced by use of the
overriding clear. Figure 1 illustrates pulse control by
retriggering and early clear.
SN54HC423 ... FH OR FK PACKAGE
SN74HC423 ... FH OR FN PACKAGE
ITOPVIEW)
~
w
5=
w
a:
The B input is a Schmitt trigger enabling jitter-free
triggering from input signals with slow transition
rates.
1ClR
NC
20
2ClR
Z
('oj
c.
('oj
)
CIl
a:
('oj
OUTPUTS
Q
Q
L
L·
L·
H
H·
H·
n.
1..f
n
oa:
~ou
w
a:
UNIT
a..
MHz
O
t-
:::;)
C
ns
o
a:
ns
a..
II
ns
ns
93 pF typ
No load. TA = 25°C
switching characteristics, over recommended operating free-air temperature range (unless otherwise
noted), CL = 150 pF (see Note 1)
PARAMETER
tpd
ten
tt
FROM
liN PUT)
CLK
OC
TO
(OUTPUT)
Any
Any
Any
VCC
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
TA = 25°C
MIN TYP MAX
38
53
36
47
30
47
27
39
42
18
5.5 V
16
SN54HCT534
MIN
MAX
38
80
71
71
59
63
57
SN74HCT534
MIN,
MAX
66
60
59
49
53
48
UNIT
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
84
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • OAI.LAS. TEXAS 75265
5-25
TYPES SN54HCT534, SN74HCT534
OCTAL D·TYPE EDGE·TRIGGERED FLlp·FLOPS
WITH 3·STATE OUTPUTS
o flip-flop
signal conventions
It is TI practice to name the outputs and other inputs of a D-type flip-flop and to draw its logic symbol
based on the assumption of true data (D) inputs. Then outputs that produce data in phase with the data
inputs are called Q and those producing complementary data are called O. An input that causes a Q output
to go high or a Q output to go low is called Preset; an input that causes a Q output to go high or a Q
output to go low is called Clear. Bars are used over these pin names (PRE and CLR) if they are active-low.
In some applications it may be advantageous to redesignate the data input D. In that case all the other
inputs and outputs should be renamed as shown below. Also shown are corresponding changes in the
graphical symbol. Arbitrary pin numbers are shown in parentheses .
."
:D
o
C
C
n
-f
."
:D
Notice that Q and 0 exchange names, which causes Preset and Clear to do likewise. Also notice that the
polarity indicators (~ ) on PRE and CLR remain since these inputs are still active-low, but that the presence
or absence of the polarity indicator changes at 5, Q and Q. Of course pin 5 (0) is still in phase with the
data input 5, but now both are considered active-low.
m
<
m
~
tn
31
5-26
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC592, SN54HC593, SN74HC592, SN74HC593
8·BIT BINARY COUNTERS WITH INPUT REGISTERS
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 1984
SN54HC592 ... J PACKAGE
SN74HC592 ••• J OR N PACKAGE
(TOP VIEW)
•
Parallel Register Inputs rHC592)
•
Parallel 3-State 1/0: Register Inputsl
Counter Outputs ('HC593)
•
Counter Has Direct Overriding Load and
Clear
•
High-Current Outputs Can Drive up to
1 5 LSTTL Loads rHC593)
•
Package Options Include Both Plastic
and Ceramic Chip Carriers in Addition to
Plastic and Ceramic DIPs
•
Dependable Texas Instruments Quality
and Reliability
vcc
B
C
D
E
F
G
H
GND
A
CLOAD
RCK
CCKEN
CCK
CCLR
RCa
SN54HC592 .•• FH OR FK PACKAGE
SN74HC592 .•• FH OR FN PACKAGE
(TOP VIEW)
U
description
en
U
U
3:
w
Ua:lZ>~
The 'HC592 consists of a parallel input, 8-bit
storage register feeding an 8-bit binary
counter. Both the register and the counter have
individual positive - edge-triggered clocks. In
addition, the counter has direct load and clear
functions. Expansion is easily accomplished by
connecting RCO of the first stage to the count
enable of the second stage, etc.
I
The 'HC593 has all the features of the 'HC592
plus 3-state 1/0;- which provides parallel
counter outputs.
:>w
CLOAD
RCK
NC
CCKEN
CCK
E
NC
F
G
a:
0.
t-
O
::J
UIOIa:
(!J
C
0
ZZU..J
oa:
a:~
NC-No internal connection
0.
II
The SN54HC592 and SN54HC593 are
characterized for operation over the full military
temperature range of - 55°C to 125°C.
The SN74HC592 and SN74HC593 are
characterized for operation from - 40°C to
85°C.
SN54HC593 •.. FH OR FK PACKAGE
SN74HC593 •.. FH OR FN PACKAGE
(TOP VIEW)
SN54HC593 ..• J PACKAGE
SN74HC593 ••• J OR N PACKAGE
(TOP VIEW)
A/QA
B/QB
C/QC
D/QD
E/QE
F/QF
G/QG
H/QH
CLOAD
GND
4
Ua:I<{u
VCC
G
d d d U
UCD~>(!J
G
RCKEN
RCK
CCKEN
CCKEN
CCK
CCLR
RCa
D/QD
E/QE
F/QF
G/QG
H/QH
development. Texaslnstrumants reserves the right to
change or discontinue this product without notice.
G
RCKEN
RCK
CCKEN
CCKEN
Copyright © 1982 by Texas Instruments Incorporated
PRODUCT PREVIEW
This document contains information on • product under
4
TEXAs •
INSTRUMENTS
POST OFFiCe BOX 225012 • DALLAS. TeXAS 75265
5-27
TYPES SN54HC592, SN54HC593, SN74HC592, SN74HC593
8·BIT BINARY COUNTERS WITH INPUT REGISTERS
logic symbols
'HC593
'HC592
CTR8
&
CCLR
EN6
~
CCK
'C'['(:)"A'5
RCK
G4
A
B
C
0
(4)
E
"g
:xl
0
C
F
G
C
H
(5)
(6)
(7)
(")
-I
BlOB _(2.....
) ...--4
C/O (3)
I-------i---~
"g
C (4)
0/0 0 ":-(5.....
) ....--41--_ _ _--1_ _ _----4
E/OE -...... . .--1
F/OF (6)
I-------i---~
:xl
m
<
m
~
tn
II
G/O
_(7.....
) ...--II-------i:-----~
G (8)
H/OH--..:.... . .- ;_ _ _ _..J._--.:._..J
Pin numbers shown are for J and N packages.
maximum ratings. recommended operating conditions. and electrical characteristics
5-28
'HC592: See Table IV, page 2-10.
'HC593: See Table III, page 2-8.
"'-!}
.
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
38
TYPES SN54HC592, SN54HC593, SN74HC592, SN74HC593
8·BIT BINARY COUNTERS WITH INPUT REGISTERS
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA
VCC
fclock Clock frequency. CCK or RCK
CCK or RCK
high or low
tw
Pulse
duration'
CClR low
ClOAD low
CCKEN low
before CCK
CClR high
(inactive) before
tsu Setup time
ClK t
RCK t before
CCK t (see Note 1)
Data A thru H
before RCK t
th
Hold time
2V
MIN
0
4.5 V
0
6V
2V
0
6V
30
26
2V
125
4.5 V
6V
2V
21
125
4.5 V
6V
25
21
2V
125
4.5 V
25
21
MIN
SN74HC'
MAX
MIN
MAX
3.3
17
19
UNIT
MHz
ns
25
6V
ns
ns
en
~
w
ns
:>w
125
6V
25
21
a:
ns
2V
200
4.5 V
6V
40
2V
125
25
4.5 V
6V
SN54HC'
MAX
150
4.5 V
2V
4.5 V
25"C
a
0..
....
U
::J
ns
34
C
oa:
ns
21
2V
5
4.5 V
5
0..
ns
6V
5
NOTE 1: The RCK t to CCK t setup tIme ensures that the counter
~III
see stable data from the. regIster outputs.
'HC592 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 2)
PARAMETER
FROM
(INPUT)
f max
CCK or
RCK
tpd
tpd
tpHL
CCKt
CLOAD!
CCLR!
TO
(OUTPUT)
VCC
2V
4.5 V
TA = 25"C
MIN
TYP
3.3
8
35
17
19
6V
RCO
RCO
RCO
2V
75
25
6V
21
2V
75
4.S V
6V
25
21
2V
85
4.S V
28
24
2V
RCKt
~
MAX
SN74HC592
MIN
MAX
UNIT
MHz
ns
ns
ns
lOS
ns
4.S V
6V
35
30
NOTE 2: For load circuits and voltage waveforms. see page 1-14.
tpd
RCO
MIN
40
4.5 V
6V
SN54HC592
MAX
II
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
5-29
TYPES SN54HC593, SN74HC593
8·BIT BINARY COUNTERS WITH INPUT REGISTERS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted). CL = 50 pF (see Note 1)
\J
PARAMETER
FROM
(INPUT)
f max
CCK or
RCK
TO
(OUTPUT)
VCC
2V
4.5 V
tpd
CCKt
'Q
tpd
CCKt
RCO
tpd
CLOAD~
Q
:u
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
m
tpHL
CCLR~
Q
~
tpHL
CCLR~
RCO
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
Q
6V
2V
4.5V
Q
6V
2V
4.5 V
o
C
tpd
CLOAD~
RCO
tpd
RCKt
RCO
c:
(')
-4
."
:u
<
m
rn
ten
ten
Gt
Ci~
6V
2V
!dis
G~
Q
!dis
Cit
Q
tt
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA - 2SoC
MIN
3.3
17
19
TYP
8
35
40
75
25
21
75
25
21
75
25
MAX
SN54HCS93
MIN
MAX
SN74HC593
MIN
MAX
UNIT
MHz
ns
ns
ns
21
75
25
21
105
35
30
90
30
26
90
30
26
ns
ns
ns
ns
66
22
19
ns
75
25
21
ns
60
20
17
60
20
17
28
8
6
ns
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
5-30
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
31
TYPES SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS
HIGH-SPEED
CMOS LOGIC
02684, DECEMBER 1982-REVISED MARCH 1984
•
8-Bit Serial-In, Parallel-Out Shift Registers
With Storage
•
Independent Direct-Overriding Clears On
Shift and Storage Registers
•
Independent Clocks for Both Shift and
Storage Registers
SN54HC594 ... J PACKAGE
SN74HC594 ... J OR N PACKAGE
(TOP VIEW)
Os
Oc
VCC
OA
SER
RCLR
RCK
SRCK
SRCLR
OH'
00
•
High-Current Outputs Can Drive up to 15
LSTTL Loads
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
OE
OF
°G
OH
GNO
SN54HC594 ... FH OR FK PACKAGE
SN74HC594 ... FH OR FN PACKAGE
(TOP VIEW)
u
CD
u
u u
c:(
OOz>O
description
These devices each contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit Dtype storage register. Separate clocks and directoverriding clears are provided on both the shift
and storage registers. A serial output (OH') is
provided for cascading purposes.
SER
RCLR
NC
RCK
SRCK
:>w
a:
Q.
I-
(J
:::>
Both the shift register and storage register clocks
are positive-edge triggered. If the user wishes to
connect both clocks together, the shift register
will always be one clock pulse ahead of the
storage register.
The parallel outputs (OA thru 0H) have highcurrent capability; output 0H' is a standard
output.
en
~
w
oJ:
:CIa:d
a:
ou
ZZ 0
(!)
CJ)
NC - No internal connection
logic symbol
c
oa:
Q.
II
The SN54HC594 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC594 is
characterized for operation from - 40°C to
85°C.
Pin numbers shown are for J and N packages.
maximum ratings, over recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
PRODUCT PREVIEW
This ~ contaila information on. product under
development. T.... Instruments ..serves the right to
change or discontinue this product without notice.
TEXAS
~
Copyright © 1982, Texas Instruments Incorporated
INSTRUMENlS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
5-31
."
:c
o
c
c
o
.....
."
:c
m
:$
m
~
CJ)
II
5-32
TYPES SN54HC595, SN74HC595
8·BIT SHIFT REGISTERS WITH 3·STATE OUTPUT REGISTERS
HIGH·SPEED
CMOS LOGIC
02684, DECEM8ER 1982-REVISED MARCH 1984
SN54HC595 ••• J PACKAGE
SN74HC595 ••• J OR N PACKAGE
(TOP VIEW)
•
a·Bit Serial· In, Parallel·Out Shift
Registers with Storage
•
High-Current 3-State Outputs Can Drive
Up to 1 5 LSTTL Loads
•
Shift Register Has Direct Clear
•
Package Options Include Both Plastic
and Ceramic Chip Carriers in Addition to
Plastic and Ceramic DIPs
•
Os
Oc
OD
OE
OF
vcc
OA
SER
G
RCK
SRCK
SRCLR
OH'
0(;
OH
GND
Dependable Texas Instruments Quality
and Reliability
SN54HC595 ••. FH OR FK PACKAGE
SN74HC595 ••• FH OR FN PACKAGE
ITOPVIEW)
description
These devices each contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit
D-type storage register. The storage register
has parallel 3-state outputs. Separate clocks
are provided for both the shift register and the
storage register. The shift register has a directoverriding clear, serial input, and serial output
pins for cascading.
3
OD
OE
NC
OF
OG
Both the shift register and storage register
clocks are positive-edge triggered. If the user
wishes to connect both clocks together, the
shift register state will always be one clock
pulse ahead of the storage register.
The SN54HC595 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC595 is characterized for operation from - 40°C to 85°C.
en
CJIXlCJ g~
002>0
2
~
w
1 2019
G
:>
w
NC
RCK
SRCK
I-
SER
4
a:
c..
o
9 1011 1213
:::l
l:1a:
a:en
C
:x: 2
C CJ
0
20d
~
o
a:
c..
NC-No internal connection
II
logic symbol
SRCK
SER (14)
OA
Os
Oc
00
OE
OF
OG
(7)
OH
191
OH'
(6)
20 [> 3\7
Pin numbers shown are for J and N packages.
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
PRODUCT PREVIEW
TIU document c:ontaInalnformatian on • product under
development. Texa. Instrument. reserve. the right to
chlnge or discontinue this product without notice.
-1!1
INSTRUMENTS
Copyright © 1982 by Texas Instruments Incorporated
TEXAS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
5-33
-g
:D
o
C
c:
(')
....
-g
:D
m
S
m
:een
II
5-34
TV'PES SN54HC597, SN54HC598, SN74HC597, SN74HC598
8·BIT SHIFT REGISTERS WITH INPUT LATCHES
HIGH·SPEED
CMOS LOGIC
02684. DECEMBER 1982-REVISED MARCH 19B4
SN54HC597 ••• J PACKAGE
SN74HC597 .•• J OR N PACKAGE
•
8-Bit Parallel Storage Register Inputs
('HC597)
•
Parallel 3-State 1/0; Storage Register
Inputs, High-Current Shift Register
Outputs Can Drive up to 15 LSTTL
Loads ('HC598)
B
1 U16
VCC
C
2
3
15
A
14~
4
•
Shift Register Has Direct Overriding
Load and Clear
G
13
12
11
10
•
Package Options Include Both Plastic
and Ceramic Chip Carriers in Addition to
Plastic and Ceramic DIPs
SER
SRLOAO
RCK
SRCK
SRCLR
°H'
•
(TOP VIEWI
o
E
F
5
6
H
7
8
GNO
9
SN54HC597 •.• FH OR FK PACKAGE
SN74HC597 ••. FH OR FN PACKAGE
Dependable Texas Instruments Quality
and Reliability
(TOPVIEWI
U
en
U
U
~
w
UalZ>«
description
3
2
o
The 'HC597 consists of an 8-bit storage latch
feeding a parallel-in, serial-out 8-bit shift
register. Both the storage register and shift
register have positive edge-triggered clocks.
The shift register also has direct load (from
storage) and clear inputs.
F
.G
The 'HC598 has all the features of the 'HC597
plus 3-state I/O ports that provide parallel shift
register outputs. The 'HC598 also has
multiplexed serial data inputs.
:>w
SER
SRLOAO
NC
RCK
SRCK
E
IX:
Q.
~
(J
::')
C
o
IX:
Q.
NC-No internal connection
II
The SN54HC597 and SN54HC598 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74HC597 and SN74HC598 are
characterized for operatiol'} from - 40°C to
85°C.
SN54HC598 •.. J PACKAGE
SN74HC598 ••• J OR N PACKAGE
SN54HC598 ••• FH OR FK PACKAGE
SN74HC598 ••• FH OR FN PACKAGE
(TOPVIEWI
A/OA
BlOB
VCC
OS
SERO
SER1
C/OC
0/0 0
0/00
G
E/OE
F/OF
G/OG
H/OH
SRLOAO
GND
4
(TOPVIEWI
Ual«U
Q 0 Q UCIl
uiii«>c
E/OE
F/OF
G/OG
H/OH
RCK
SRCKEN
SRCK
SRCLR
°H'
PRODUCT PREVIEW
on.
this ~t c:ontIIIM information
product under
development. Tex•• Instruments reaenr.s the right to
change or dIocontinue thl. product without no&..
TEXAS
~
4
SERO
SER1
G
RCK
SRCKEN
Copyright © 1982 by Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
5-35
TYPES SN54HC591, SN54HC598, SN14HC591, SN14HC598
8·BITSHIFT REGISTERS WITH INPUT LATCHES
logic symbols
'HC597
'HC598
SRG8
G (16)
SRm
SRC'i<'EN
SRCK
SRLOAD
RCK
DS
B
SER
D
0
E
C
c:
F
n
G
-I
H
(12)
EN14
~R
(14)
r.....
(13)
G4
~4C5/4-
(9)
j'ooo."
(15)
C3
C2
(19)
G1
~
(17)
(9)
0H'
C/oc
"tJ
:xJ
D/OD
I..- \7
'PI..- \7
.....
<
F/OF
E/OE
m
(3)
(4)
...
~
7,14
3D
l>
3D
Z7
-
A-Ao
~
P
(7)
(f!! .. '" P
H/OH
G/OG
m
~
en
6,14
2D
(5)
(6)
Z6
2D
(2)
BlOB
~
C>
1,5D
1,5D
1 (18)
SER
(1 )
A/OA
C
"tJ
:xJ
o
~
~l..
2D
'V
13,14
3D
Z~
------
(11)
I!I
iii maximum ratings, recommended operating conditions, and electrical characteristics
Pin numbers shown are for J and N packages.
'HC597: See Table IV, page 2-10.
'HC598: See Table III, page 2-8.
31
5-36
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC597, SN54HC598, SN74HC597, SN74HC598
8·BIT SHIFT REGISTERS WITH INPUT LATCHES
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
fclock
Clock frequency. RCK
or SRCK
RCK or SRCK
tw
Pulse
duration
high or low
SRCLR low or
SRLOAD low
100
20
6V
17
2V
4.5 V
100
20
ive) before SRCK t
6V
17
2V
200
4.5 V
6V
40
before RCK t
2V
MIN
SN74HC'
MAX
MIN
MAX
UNIT
MHz
29
ns
20
17
100
or A thru H
Hold time
2V
4.5 V
4.5 V
SER before SRCK t
th
5
25
6V
0
0
0
2V
4.5 V
SRCLR high (inact-
RCK t before
SRCK t (see Note 1)
SN54HC'
MAX
6V
2V
SRCKEN low or
tsu Setup time
TA 225°C
MIN
en
~
ns
34
100
4.5 V
6V
20
a:
c..
17
2V
0
4.5 V
0
6V
0
w
:>
w
I-
ns
(.)
::)
C
NOTE 1: The RCK t before SRCK t setup time ensures that the shift register will see stable data coming from the input register.
o
a:
c..
II
4
TEXAS
'Ii1
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
5-37
TYPES SN54HC597, SN74HC597
8·BIT SHIFT REGISTERS WITH INPUT LATCHES
'HC597 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 2)
PARAMETER
TO
(OUTPUT)
f max
RCK or
SRCK
tpd
SRCKt
Ow
tpd
SRLOAD!
Ow
SRCLR!
Ow
RCKt
Ow
tpHL
"'tJ
FROM
(INPUT!
::D
o
tpd
C
c:
(1
-4
VCC
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
'4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN
5
25
29
TYP
SN54HC597
MAX
MIN
SN74HC597
MAX
MIN
UNIT
8
35
40
75
MHz
25
21
75
ns
25
21
60
20
17
60
20
17
ns
ns
ns
NOTE 2: For load circuits and voltage waveforms. see page 1-14.
"'tJ
::D
m
<
m
:een
II
5-38
MAX
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC598, SN74HC598
8·BIT SHIFT REGISTERS WITH INPUT LATCHES
'HC598 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), CL = 50 pF (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
2V
4.5 V
6V
2V
f max
RCK or
SRCK
tpd
SRCKf
Ow
tpd
SRLOAD~
°H'
SRCLR~
Ow
tpd
RCKf
Ow
tpd
SRCKf
OA thru OH
tpHL
tpd
SRLOAD~
OA thru OH
SRCLR~
OA thru OH
ten
cH
OA thru OH
tdis
Gf
OA thru OH
tpHL
vCC
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
2V
4.5 V
6V
TA" 25°C
MIN
TYP
5
8
35
40
75
25
21
75
25
21
60
20
17
60
20
17
60
20
17
60
20
17
75
25
21
66
22
19
60
20
17
25
29
SN54HC598
MAX
MIN
MAX
SN74HC598
MAX
MIN
UNIT
MHz
ns
ns
ns
ns
ns
en
~
w
:>w
a:
0..
Ins
CJ
::;)
C
ns
oa:
0..
ns
ns
II
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
5-39
"'0
:x:J
o
C
c:
(')
-I
"'0
:x:J
m
<
iii
~
rn
5-40
TYPES SN54HC630, SN74HC630
16·81T PARALLEL ERROR DETECTION
AND CORRECTION CIRCUITS
HIGH·SPEED
CMOS LOGIC
02804, MARCH 1984
•
High·Current 3-State Outputs Can Drive up
to 15 LSTTL Loads
•
Detects and Corrects Single-Bit Errors
•
Detects and Flags Dual-Bit Errors
•
Dependable Texas Instruments Quality and
Reliability
SN54HC630 .. , J PACKAGE
SN74HC630 , . , J OR N PACKAGE
(TOP VIEW)
OEF
OBO
DB1
OB2
OB3
DB4
OB5
OB6
OB7
OBB
OB9
OB10
OB11
GNO
description
The 'HC630 device is a 16-bit parallel error
detection and correction circuit (EDAC) in a
28-pin, 600-mil package. It uses a modified
Hamming code to generate a 6-bit check word
from a 16-bit data word. This check word is
stored along with the data word during the
memory write cycle. During the memory read
cycle, the 22-bit words from memory are
processed by the EDAC to determine if errors
have occurred in memory.
VCC
5EF
51
SO
CBO
CB1
CB2
CB3
CB4
CB5
OB15
OB14
OB13
OB12
en
~
w
:>w
a:
Single-bit errors in the 16-bit data word are
flagged and corrected.
c..
t-
Single-bit errors in the 6-bit check word are flagged, and the CPU sends the EDAC through the correction
cycle even though the 16-bit word is not in error. The correction cycle will simply pass along the original
16-bit word in this case and produce error syndrome bits to pinpoint the error-generating location.
O
::J
C
Dual-bit errors are flagged but not corrected. These dual errors may occur in any two bits of the 22-bit
word from memory (two errors in the 16-bit data word, two errors in the 6-bit check word, or one error
in each word).
The gross-error condition of all lows or all highs from memory will be detected. Otherwise, errors in three
or more bits of the 22-bit word are beyond the capabilities of these devices to detect.
The SN54HC630 is characterized for operation over the full military temperature range of - 55 DC to 125 DC.
The SN74HC630 is characterized for operation from - 40 DC to 85 DC.
oa:
c..
II
CONTROL FUNCTION TABLE
MEMORY
CONTROL
CYCLE
51
SO
WRITE
READ
L
L
L
H
READ
H
H
READ
H
L
EDAC FUNCTION
DATA 1/0
Generate Check Word
Read Data & Check Word
Latch & FlaQ Errors
Correct Data Word &
Generate Syndrome Bits
PRODUCT PREVIEW
ThIs doc:urI*It contIIIna information on • product under
development. Tex•• lnll1tUment. re..",.. the right to
change or discontinue thI. p
C
o
a:
0..
II
FOR CHIP CARRIER INFORMATION,
CONTACT THE FACTORY.
Dual-bit errors are flagged but not corrected. These errors may occur in any two' bits of the 39-bit word
from memory (two errors in the 32-bit data word, two errors in the 7-bit check word, or one error in each
word). The gross-error condition of all lows or all highs from memory will be detected. Otherwise, errors
in three or more bits of the 39-bit word are beyond the capabilities of these devices to detect.
Read-modify-write (byte-control) operations can be performed with the 'HC632 EDAC by using output
latch enable, LEDBO, and the individual DEBO thru OEB3 byte control pins.
Diagnostics are performed on the EDAC by controls and internal paths that allow the user to read the
contents of the DB and CB input latches. These will determine if the failure occured in memory or in the
EDAC.
The SN54HC632 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN74HC632 is characterized for operation from - 40°C to 85 DC.
PRODUCT PREVIEW
"!1
This document contain. information on a product under
development. Texas Instruments reserves the right to
TEXAS
change or discontinue this product without notice.
INSTRUMENTS
POST OFFiCE BOX 225012 • DALLAS. TEXAS 75265
Copyright © 1984, Texas Instruments Incorporated
5-45
TYPES SN54HC632, SN74HC632
32·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
TABLE I. WRITE CONTROL FUNCTION
MEMORY
EDAC
CYCLE
FUNCTION
Write
Gererate
check word
CONTROL
S1
L
SO
DB CONTROL
DATA 1/0
OEBO THRU
DB OUTPUT LATCH
LEDBO
------'-
OEB3
Input
L
H
CB
CHECK 1/0 CONTROL
ERROR FLAGS
OECB
Output
X
check bitst
L
ERR
MERR
H
H
tSee Table II for details on check bit generation.
memory write cycle details
During a memory write cycle, the check bits (CBO thru CB6) are generated internally in the EDAC by seven
16-input parity generators using the 32-bit data word as defined in Table II. These seven check bits are
stored in memory along with the original 32-bit data word. This 32-bit word will later be used in the memory
read cycle for error detection.
"'tJ
TABLE II. PARITY ALGORITHM
:Jl
o
CHECK WORD
C
c:
n
CSO
X
CB2
"'tJ
CB3
:Jl
m
CB4
<
CB5
CB6
m
:IE
en
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
CB1
-f
32-BIT DATA WORD
BIT
X X
X
X
X X X
X
X
X X X
X
X
X
X
X
X
X
X X X
X
X X
X
X
X
X
X X
X X
X
X X
X X X
X X
X X X
X
X X X
X
X X
X X X X X X
X X
X X X X X X X X
X X X X X X X X
X
X X X X X X X X
5 4
3 2
1 0
X
X
X
X
X X X
X
X X
X
X X
X X
X X X X X
X X X X X X X
The seven check bits are parity bits derived from the matrix of data bits as indicated by "X" for each bit.
error detection and correction details
During a memory read cycle, the 7-bit check word is retrieved along with the actual data. In order to be
able to determine whether the data from memory is acceptable to use as presented to the bus, the error
flags must be tested to determine if they are at the high level.
The first case in Table III represents the normal, no-error conditions. The FDAC presents highs on both
flags. The next two cases of single-bit errors give a high on MERR and a low on ERR, which is the signal
for a correctable error, and the EDAC should be sent through the correction cycle. The last three cases
of double-bit errors will cause the EDAC to signal lows on both ERR and MERR, which is the interrupt
indication for the CPU.
TABLE III. ERROR FUNCTION
TOTAL NUMBER OF ERRORS
5-46
ERROR FLAGS
32-BIT DATA WORD
7-BIT CHECK WORD
ERR
MERR
DATA CORRECTION
0
1
0
1
2
0
0
0
1
1
0
2
H
H
Not applicable
L
H
Correction
L
H
Correction
L
L
Interrupt
L
L
Interrupt
L
L
Interrupt
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC632, SN74HC632
32·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
Error detection is accomplished as the 7-bit check word and the 32-bit data word from memory are applied
to internal parity generators/checkers. If the parity of all seven groupings of data and check bits are correct,
it is assumed that no error has occurred and both error flags will be high.
If the parity of one or more of the check groups is incorrect, an error has occurred and the proper error
flag or flags will be set low. Any single error in the 32-bit data word will change the state of either three
or five bits of the 7-bit check word. Any single error in the 7-bit check word changes the state of only
that one bit. In either case, the single error flag (ERR) will be set low while the dual error flag (MERR) will
remain high.
Any two-bit error will change the state of an even number of check bits. The two-bit error is not correctable
since the parity tree can only identify single-bit errors. Both error flags are set low when any two-bit error
is detected.
Three or more simultaneous bit errors can cause the EDAC to believe that no error, a correctable error,
or an uncorrectable error has occurred and will produce erroneous results in all three cases. It should be
noted that the gross-error conditions of all lows and all highs will be detected.
MEMORY
EDAC
CYCLE
FUNCTION
Read
Read & flag
~ONTROL
DATA 110
S1 SO
H
L
Latch input
Read
data & check
H
H·
Output
corrected data
OEBO THRU
DB OUTPUT LATCH
OEB3
LEDBO
X
H
Latched
bits
Read
Input
DB CONTROL
H
& syndrome bits
H
input
CB
CHECK I/O CONTROL
OECB
Input
L
input
data
check word
Output
Output
corrected
W
>
w
a:
ERROR FLAGS
ERR
MERR
H
Enabledt
H
Enabledt
c..
Latched
H
X
L
data word
en
~
TABLE IV. READ. FLAG. AND CORRECT FUNCTION
syndrome
L
I-
U
:::l
C
oa:
Enabledt
bitst
c..
tSee Table III for error description.
tSee Table V for error location.
As the corrected word is made available on data I/O port (DBa thru DB311, the check word I/O port (CBO
thru CB6) presents a 7-bit syndrome error code. This syndrome error code can be used to locate the bad
memory chip. See Table V for syndrome decoding.
TEXAS
-I./}.
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
II
5-47
TYPES SN54HC632, SN74HC632
32·81T PARALLEL ERROR' DETECTION AND CORRECTION CIRCUITS
TABLE V. SYNDROME DECODING
SYNDROME BITS
6 5 4 3 2 1 0
L L L L L L L
L L L L L L H
L L L L L H L
L L L L L H H
L L L L H L L
L L L L H L H
L L L L H H L
L L L L H H H
L L L H L L L
L L L H L L H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
":Do
C
C
C')
-I
"m
:D
<
m
~
en
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H'
H
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
ERROR
unc
2-bit
2-bit
' unc
2-bit
unc
unc
2-bit
2-bit
unc
OB31
2-bit
unc
2-bit
2-bit
OB30
2-bit
unc
OB29
2-bit
OB28
2-bit
2-bit
OB27
OB26
2-bit
2-bit
OB25
2-bit
OB24
unc
2-bit
SYNDROME BITS
6
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
5
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
4
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
2 1 0
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
ERROR
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
2-bit
unc
OB7
2-bit
DB6
2-bit
2-bit
OB5
OB4
2-bit
2-bit
OB3
2-bit
OB2
unc
2-bit
OBO
2-bit
2-bit
unc
2-bit
OB1
unc
2-bit
2-bit
unc
unc
2-bit
unc
2-bit
2-bit
CB6
6
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
SYNDROME BITS
5 4 3 2 1 0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L L
L H
H L
H H
L L
L H
H L
H H
L L
L H
H L
H H
L L
L H
H L
H H
L L
L H
H L
H H
L L
L H
H L
H H
L L
L H
H L
H H
L L
L H
H L
H H
ERROR
2-bit
unc
unc
2-bit
unc
2-bit
2-bit
unc
unc
2-bit
2-bit
OB15
2-bit
unc
OB14
2-bit
unc
2-bit
2-bit
OB13
2-bit
OB12
OB11
2-bit
2-bit
OB10
OB9
2-bit
OB8
2-bit 2-bit
CB5
6
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
SYNDROME BITS
5 4 3 2 1 0
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L L L
L L L
L L H
L L H
L H L
L H L
L H H
L H H
H L L
H L L
H L H
H L H
H H L
H H L
H H H
H H H
L L L
L L L
L L H
L L H
L H L
L H L
L H H
L H H
H L L
H L L
H L H
H L H
H H L
H H L
H H H
H H H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
ERROR
unc
2-bit
2-bit
OB23
2-bit
0922
OB21
2-bit
2-bit
OB20
OB19
2-bit
OB18
2-bit
2-bit
CB4
2-bit
OB16
unc
2-bit
OB17
2-bit
2-bit
CB3
unc
2-bit
2-bit
CB2
2-bit
CB1
CBO
none
CB X = error in check bit X
DB Y = error in data bit Y
2-bit = double-bit error
unc = uncorrectable multibit error
read· modify-write (byte control) operations
The 'HC632 is capable of byte-write operations. The 39-bit word from memory must first be latched into
the DB and CB input latches. This is easily accomplished by switching from the read and flag mode
(51 = H,50 = L) to the latch input mode (51 = H,50 = H). The EOAC will then make any corrections,
if necessary, to the data word and place it at the input of the output data latch. This data word must
then be latched into the output data latch by taking LEOBO from a low to a high.
Byte control can now be employed on the data word through the OEBO through OEB3 controls. OEBO
controls OBO-OB7 (byte 0), OEB1 controls OB8-0B15 (byte 1), OEB2 controls OB16-0B23 (byte 2),
and OEB3 controls OB24-0B31 (byte 3). Placing a high on the byte control will disable the output and
the user can modify the byte. If a low is placed on the byte control, then the original byte is allowed to
pass onto the data bus unchanged. If the original data word is altered through byte control, a new check
word must be generated before it is written back into memory. This is easily accomplished by taking control
51 and 50 low. Table VI lists the read-modify-write functions.
5-48
TEXAS
-Ii}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3.
TYPES SN54HC632, SN74HC632
32·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
TABLE VI. READ-MODIFY-WRITE FUNCTION
MEMORY
CYCLE
Read
Read
EDAC FUNCTION
Read & Flag
Latch input data
& check bits
CONTROL
S1
SO
H
L
H
H
data word into
OEBnt
LATCH
H
H
output latch
CHECK I/O
LEDBO
Input
H
X
H
L
Input
CB
CONTROL
ERROR FLAG
ERR
MERR
H
Enabled
H
Enabled
Latched
Latched
Latch -corrected
Read
DB OUTPUT
BYTEnt
Input
input
data
check word
Latched
f-------
H
-------
Syndrome
L
Hi-Z
output
H
data
H
Output
Enabled
bits
word
Input
Modify appropriate
Modify
byte or bytes &
Iwrite
generate new
check word
modified
L
L
H
BYTEO
-----------Output
unchanged
H
Output
check word
L
H
H
L
BYTEO
en
3:
w
tOE'Bo controls OBO- OB7 (BYTEO), OEB 1 controls OB8 - DB 15 (BYTE 1), OEB2 controls DB 16- OB23 (BYTE2L 0E'B3 controls OB24- OB31
(BYTE3).
>
w
diagnostic operations
0..
The 'HC632 is capable of diagnostics that will allow the user to determine whether the EDAC or the memory
is failing. The diagnostic function tables will help the user to see the possibilities for diagnostic control.
In the diagnostic mode (S1 = L, SO = HI, the checkword is latched into the input latch while the data
input latch remains transparent. This lets the user apply various data words against a fixed known
checkword. If the user applies a diagnostic data word with an error in any bit location, the ERR flag should
be low. If a diagnostic data word with two errors in any bit location is applied, the MERR flag should be
low. After the checkword is latched into the input latch, it can be verified by taking OECB low. This outputs
the latched checkword. The diagnostic data word can be latched into the output data latch and verified.
By changing from the diagnostic mode (S1 = L, SO = HI to the correction mode (S1 = H, SO = HI, the
user can verify that the EDAC will correct the diagnostic data word. Also, the syndrome bits can be produced
to verify that the EDAC pinpoints the error location. Table VII lists the diagnostic functions.
a:
I(,J
::J
C
o
a:
0..
II
l4
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
5-49
TYPES SN54HC632. SN74HC632
32·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
TABLE VII. DIAGNOSTIC FUNCTION
EDAC FUNCTION
Read & flag
CONTROL
S1
SO
H
L
L
H
Latch input check
word while data
input latch remains
H
:D
C
C
Output diagnostic
o
data word &
(")
diagnostic data
m
word & output
$
~
H
syhdrome bits
H
X
H
L
H
H
H
Input correct
check bits
input
input
diagnostic
diagnostic
corrected
diagnostic
check bits
'-------Hi-Z
ERROR FLAGS
ERR
MERR
H
H
H
Enabled
H
L
----H
Enabled
Output
H
H
syndrome
L
bits
f--------Hi-Z
Enabled
H
Output
L
H
Output
H
OECB
Output latched
diagnostic
data word
H
CONTROL
check bits
data word
H
CB
CHECK I/O
Latched
diagnostic
Output
Output corrected
"'C
:D
LEDBO
Latched
H
syndrome bits
-4
OEBn
data word t
Latch diagnostic
input latch
LATCH
Input
L
output latch
"'C
DB OUTPUT
data word t
Latch diagnostic
data word into
Input correct
data word
DB BYTE
CONTROL
Input
transparent
data word into
DATA I/O
syndrome
bits
f-------Hi-Z
L
Enabled
----H
Output
L
L
syndrome
..!:i~_~ ___
Hi-Z
data word
L
Enabled
---H
t Diagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case, the diagnostic
c:::::
data word will contain errors in two bit locations.
en
5-50
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC632. SN74HC632
32·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
logic diagram (positive logic)
DECODER
X/Y
-1
S1 -
7
,
3
1
3 ....
2
r-
~
2r-
.---
SYNDROME
GENERATOR
~r-*-
o .....
so
J
I
0
r--=1
h
~
CHECK-BIT
GENERATOR
h
~
~
---.....
---.....
LATCHES
r---
~
--i C1
C BOCB6
7
7
~
,
1D
'--
r
C
o
a::
1D
c..
32
BUFFERS
BO
EN
1D
8
DB24-D B31
"-
1D
8
DB16-D B23
8
a::
c..
t-
C1
8.,
8
:>w
ERROR
DETECTOR
~
DBO- DB7
8
w
~
G1
'-
DB8-D B15
8
en
~
...
7L
,.. EN
CB
[7
X-OR]
'--
MUX
BUFFERS
WK::=:x--"""(j;OUU,TrPPU-UTrisiVy:;.;NDiDR;;ComMiEEccoDiDDiE:--...)~)~)~)~»:;:)~~~--
W/f41~;MID'fWM4'-______________V_AL_'D_E_R_R_F_LA_G______________~>W4iMlcl,sWltl
o
C
'c::
FIGURE 1-READ,FlAG,AND CORRECT MODE SWITCHING WAVEFORMS
(")
-I
."
:xl
m
<
m
~
rn
II
I
I
--~~::~R~E~A~D:::t~I~~::::::::::::~CO~R~R~EC~T~::::::::::::::~.~1.~=========Ww~RlmTEE-=========:;
SI --.J
I
so
DBa THRU DB7
---<
OUTPUT CORRECTED DATA WORD
INPUT DATA WORD
~==::====:)~)~)Z»~--_C::!'~NP~U~T~M~OD~I~FI~ED~BY~T~E~O=:»»»--~Z]
DBB THRU DB15
INPUT DATA WORD
OUTPUT CORRECTED DATA WORD
DB16 THRU OB23
INPUT DATA WORD
OUTPUT CORRECTED DATA WORD
DB24 THRU DB31
INPUT DATA WORD
OUTPUT CORRECTED DATA WORD
OEBO
__________________________________
__________________________________
__________________________________
~
~r----
~
~r----
~
~r----
~
L - -_ _ _ _ _ _ _ _ _ _ _ _
CBO THRU CB6
INPUT CHECK WORD
~--------------~r----
OUTPUT SYNDROME CODE
OUTPUT CHECK WORD
.Jl
\'-__________v...;A...;L...;IO...;E...;R...;R_F...;LA...;G~________
\~________
vA_L_ID_M_E_R_R_F_LA_G______
_Jl
FIGURE 2-READ,CORRECT,MODIFY MODE SWITCHING WAVEFORMS
3:
5-52
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC632, SN74HC632
32·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
L
so
SI
DBO THRU DB31
INPUT VALID DATA WORD
INPUT DIAGNOSTIC DATA WORD
OUTPUT DIAGNOSTIC
DATA WORD
OEBO - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
THRU
L.______________________________~r_____
OEB3
THRlJ
CBG
OUTPUT SYNDROME CODE
OUTPUT VALID CHECK WORD
~
____________________________________
~r__
en
~
W
>
w
a:
FIGlJRE 3·DIAGNOSTIC MODE SWITCHING WAVEFORM
a.
I-
U
::J
C
oa:
a.
II
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
5-53
"'C
:xJ
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n
-I
"'C
:xJ
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<
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en
5-54
4
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC670, SN74HC670
4·BY·4 REGISTER FILES WITH 3·STATE OUTPUTS
02804, MARCH 1984
•
Separate Read/Write Addressing Permits
Simultaneous Reading and Writing
o
Organized as 4 Words of 4 Bits
o
Expandable to 512 Words of n-Bits
o
For Use as:
Scratch-Pad Memory
Buffer Storage Between Processors
Bit Storage in Fast Multiplication Designs
o
High-Current 3-State Outputs Can Drive up
to 1 5 LSTTL Loads
o
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN54HC670 , .. J PACKAGE
SN74HC670 . , . J OR N PACKAGE
{TOP VIEW)
o
02
03
04
RB
RA
Q4
Q3
SN54HC670 .. , FH OR FK PACKAGE
SN74HC670 .. , FH OR FN PACKAGE
M N U
2
:>w
1 2019
RB
WA
WB
NC
NC
RA
GW
GR
04
The SN54HC670 and SN74HC670 are 16-bit
register files. The register file is organized as 4
words of 4 bits each and separate on-chip
decoding is provided for addressing the four
word locations to either write-in or retrieve data.
This permits simultaneous writing into one
location and reading from another word location.
The individual address lines permit direct
acquisition of data stored in any four of the
latches. Four individual decoding gates are used
to complete the address for reading a word.
When the read address is made in conjunction
with the read-enable signal, the word appears at
the four outputs.
~
w
U
U ....
ooz>o
3
Four data inputs are used to supply the 4-bit
word to be stored. Location of the word is
determined by the write-address inputs W A and
WB in conjunction with a write-enable signal
GW. Data applied at the inputs should be in its
true form. That is, if a high-level signal is desired
from the output, a high-level is applied at the
data input for that particular bit location. When
GW is high, the data inputs are inhibited and their
levels can cause no change in the information
stored in the internal latches. When the readenable input GR is high, the data outputs are
inhibited and go into the high-impedance state.
en
(TOP VIEW)
description
PRODUCT PREVIEW
01
WA
WB
GW
GR
Q1
Q2
GNO
Dependable Texas Instruments Quality and
Reliability
This document contains information on a product under
development. Texas Instruments reserves the right to
change or discontinue this product without notice.
VCC
Q4
a:
a..
I-
U
::>
9 10 11 1213
C
o
MOUN ....
OzzOO
a:
<.9
a..
NC- No internal connections.
II
logic symbol
(14)
WA (13)
WB
(5)
RA
(4)
RB
Gw
RAM 4x4
O} 1A.!!.
1
3
O}2A .!!.
1
3
C4 [WRITE)
OR
D1
D2
D3
D4
(15)
01
(1)
02
(2)
03
(3)
04
Pin numbers shown are for J and N packages.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright © 1984, Texas Instruments Incorporated
5-55
TYPES SN54HC670, SN74HC670
4·BY·4 REGISTER FILES WITH 3·STATE OUTPUTS
This arrangement-data-entry addressing separate from data-read addressing and individual sense lineeliminates recovery times, permits simultaneous reading and writing, and is limited in speed only by the
write time and the read time. The register file has a nondestructive readout in that data is not lost when
addressed.
The outputs are high-current, three-state outputs. These outputs may be bus connected for increasing
the word capacity. Any number of these registers may be paralleled to provide n-bit word length.
The SN54HC670 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN74HC670 is characterized for operation from - 40°C to 85 DC.
WRITE FUNCTION TABLE (SEE NOTES A. B. AND C)
WRITE INPUTS
"tI
lJ
o
C
C
(")
~
"tI
WB
L
WA
L
Gw
L
WORD
0
1
2
3
Q=D
Qo
Qo
RB
L
RA
L
GR
L
Qo
L
H
H
L
H
X
L
H
L
Qo
Qo
Q=D
H
L
L
Qo
Qo
Qo
Q=D
H
H
L
Qo
Qo
Qo
Qo
Q=D
X
X
H
Qo
Qo
Qo
Qo
NOTES: A.
B.
C.
D.
READ FUNCTION TABLE (SEE NOTES A AND D)
READ INPUTS
Q1
OUTPUTS
Q2
Q3
Q4
WOBl
WOB2
WOB3
WOB4
L
W1B1
W1B2
W1B3
W1B4
L
W2Bl
W2B2
W2B3
W2B4
H
L
W3Bl
W3B2
W3B3
W3B4
X
H
Z
Z
Z
Z
H = high level. L = low level. X = irrelevant. Z = high impedance (off) ,
(Q = D) = The four selected internal flip-flop outputs will assume the states applied to the four external data inputs.
QO = the level of Q before the indicated input conditions were established.
WOBl = The first bit of word O. etc.
lJ
m
S
m
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-8.
:E
en
3E
5-56
-1.!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TYPES SN54HC881, SN74HC881
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
HIGH·SPEED
CMOS LOGIC
D2804, MARCH 1984
•
Full Look-Ahead for High-Speed' Operations
on Long Words
•
Arithmetic Operating Modes
Addition
Subtraction
Shift Operand A One Position
Magnitude Comparison
Plus Twelve Other Arithmetic Operations
5N54HC881 ... JT PACKAGE
5N74HC881 ... JT OR NT PACKAGE
ITOPVIEW)
•
•
80
AO
S3
S2
S1
SO
Logic Function Modes
Exclusive-OR
Comparator
AND, NAND, OR. NOR
Status Register Checks
Plus Ten Other Logic Operations
VCC
A1
81
A2
B2
A3
83
Cn
M
G
Fa
F1
F2
C n +4
p
A=B
F3
GND
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
en
3:
w
5N54HC881 ... FH OR FK PACKAGE
5N74HC881 ... FH OR FN PACKAGE
:>w
(TOP VIEW)
•
Dependable Texas Instruments Quality and
Reliability
U
C")OOUU.-.4
S1
S2
53
M
Cn
(6)
(5)
(4)
(3)
(8)
(7)
3
2
ALU
"}M~
P
IT
4
C n+4
31
a.
1 282726
JU
:J
C
A2
B2
A3
S2
S1
logic symbol
SO
a:
c.n1«lco z >I«ICO
NC
NC
Cn
83
o
G
a.
M
Fa
a:
C n +4
II
12 1314151617 18
A=B
I~ I~ ~ ~ 1f2 ~ Ill..
(!)
CI
«
NC - No internal connection
AO
80
[1]
[2]
[8]
Pin numbers shown are for JT and NT packages.
For additional information on the 5N54HC881 and 5N74HC881. see page 3-149.
PRODUCT PREVIEW
ThIs cIoc:umM>t contains Infonnatlon on a product under
development. Texa.lnstruments re.erve. the right to
change or discontinue this product without notice.
Copyright © 1984. Texas Instruments Incorporated
TEXAS . .
INSTRUMENJS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
5-57
""C
:c
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~
(J)
5-58
TYPES SN54HC882, SN74HC882
32·811 LOOK·AHEAD CARRY GENERATORS
HIGH·SPEED
CMOS LOGIC
02804, MARCH 1984
SN54HC882 •.. JT PACKAGE
SN74HC882 ... JL. OR NT PACKAGE
(TOP VIEW)
•
Directly Compatible with the New 'HC181
and 'HC881 ALUs
•
Capable of Anticipating the Carry Across a
Group of Eight 4-Bit Binary Adders
•
Cascadable to Perform Look-Ahead Across
n-Bit Adders
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
Cn
GO
PO
(31
VCC
NC
Cn +32
P7
(37
P6
G6
Cn +24
P5
<35
P4
(34
Pl
Cn +8
G2
P2
G3
P3
Cn +16
GND
description
The 'HC882 is a high-speed look-ahead carry
generator capable of anticipating the carry
across a group of eight 4-bit adders permitting
the designer to implement look-ahead for a
32-bit ALU with a single package or, by
cascading 'HC882's, full look-ahead is possible
across n-bit adders.
en
~
SN54HC882 ... FH OR FK PACKAGE
SN74HC882 .•• FH OR FN PACKAGE
(TOP VIEW)
W
>
w
N
a:
("I')
I~ 18
The SN54HC882 is characterized for operation
over the full military temperature range of
- 55 °C to 125°C. The SN74HC882 is
characterized for operation from - 40 DC to
85°C.
4
Cn +8
NC
<32
P2
<33
logic symbol
CPG
3
U
+
c..
cf ~ ~ ~ cf
2
IU
::J
1
P7
<37
P6
NC
<36
9
C
oa:
c..
II
C n +24
P5
12 131415161718
("I')
co
0
U "w
NC
4A
a:
NC
description
2C
The 'HC4016 is a quadruple bilateral switch for
either digital or analog signals. Low power
dissipation and high noise immunity allow the
'HC4016 to. be used in many diverse environments.
Applications include digital switching and
multiplexing, analog-to-digital and digital-toanalog conversion, digital control of frequency,
impedance, phase, and analog-signal gain,
signal gating, and as a squelch control, chopper, modulator, demodulator, or commutating
switch.
0..
4B
tU
UOUw
Pin 16 of the 'HC4049 and 'HC4050 in the J or
N package is not internally connected; therefore,
any external connection to this pin does not
affect circuit operation.
a:
a..
t-
U
::>
FUNCTION TABLE
INPUT
A
C
OUTPUT Y
'HC4049
H
L
L
H
oa:
I 'HC4050
H
I
a..
L
II
logic symbols
'HC4049
(3)
lA
2A (5)
lA (3)
2A (5)
'HC4050
lY
2Y
3A (7)
3A (7)
(6)
4A (9)
4A (9)
(10)
5A (11)
5A (11)
6A (14)
6A (14)
(12)
5Y
(15) 6Y
3Y
4Y
Pin numbers shown are for J and N packages.
34
PRODUCT PREVIEW
This document contains information on a product under
development. Texas Instruments raserves the right to
change or discontinue this product without notice.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright © 1984. Texas Instruments Incorporated
5-63
."
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(")
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."
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5-64
TYPES SN54HC4051, SN54HC4052, SN54HC4053
SN74HC4051, SN74HC4052, SN74HC4053
ANALOG MULTIPLEXERS/DEMULTIPLEXERS
HIGH·SPEED
CMOS LOGIC
02804. MARCH 1984
•
Fast Switching
•
Low Crosstalk Between Switches
•
High On/Off Output Voltage Ratio
•
Analog Supply Voltage Range
(VCC-VEE) ... 3 V to 12 V
G
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
lBO
lB2
lA
lB3
lBl
VCC
82
Bl
BO
83
50
VEE
GND
Digital Supply Voltage Range
(VCC-GNDI ... 2 V to 6 V
SN54HC4052 ... J PACKAGE
SN74HC4052 ... J OR N PACKAGE
(TOP VIEW)
SN54HC4051 ... J PACKAGE
SN74HC4051 ... J OR N PACKAGE
(TOP VIEW)
84
86
A
B7
85
•
G
VEE
GND
51
52
~----';";-
SN54HC4053 ... J PACKAGE
SN74HC4053 ... J OR N PACKAGE
(TOP VIEW)
VCC
2B2
2Bl
2A
2BO
2B3
lB1
lBO
2Bl
2A
2BO
50
51
VEE
VCC
1A
3A
3Bl
3BO
35
G
GN D
en
~
w
:>w
15
'"'"1,;;_---'J-'
25
ex:
SN54HC4051 ... FH OR FK PACKAGE
SN74HC4051 ... FH OR FN PACKAGE
(TOP VIEW)
SN54HC4052 ... FH OR FK PACKAGE
SN74HC4052 ... FH OR FN PACKAGE
(TOP VIEW)
U
CD <:t U UN
[l)[l)Z>[l)
NOUN
[l) [l) U U[l)
G
o
1A
lB3
NC
181
C
oex:
3A
3Bl
NC
3BO
35
G
(,J
::J
«
....
2B1
2A
NC
2BO
D..
I-
D..
II
we U en (/)
Wz z N ...
>t!)
we U ~ 0
Wz z en en
>t!)
we U N ~
wzzenen
>t!)
U
U
~~Z>
2Bl
2A
NC
2BO
2B3
G
~
[l) [l) U
~~Z>N
B1
BO
NC
B3
50
A
B7
NC
B5
SN54HC4053 ... FH OR FK PACKAGE
SN74HC4053 ... FH OR FN PACKAGE
(TOP VIEW)
NC-No internal connection.
logic symbols
so
(11)
Sl (10)
(9)
'HC4051
'HC4052
MUXOMUX
MUXOMUX
o}
2
o}
0
1
8Xi
'HC4053
0
4X3
G4
84
85
86
87
Pin numbers shown are for J and N packages.
134
Copyright © 1984. Texas Instruments Incorporated
PRODUCT PREVIEW
This document contain. information on 8 produc:t under
development. Tex•• Instrument. reserves the right to
chenge or discontinue this product without notice.
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
5-65
TYPES SN54HC4051. SN54HC4052. SN54HC4053
SN74HC4051. SN74HC4052. SN74HC4053
ANALOG MUL TIPLEXERS/DEMULTIPLEXERS
description
VCC(MOST POSITIVE)
These devic~s are analog multiplexers/
demultiplexers incorporating built-in level
shifting. The level shifting allows a control input
range of GND to VCC for an analog signal range
of VEE to Vcc. Thus the common situation of
positive digital signals controlling the
multiplexing of both positive and negative analog
signals can be accommodated.
SO-Sn
VEE
(0 V OR NEGATIVE
WITH RESPECT TO GND)
These digitally controlled bilateral analog
switches have Iowan-state impedance and very
low off-state current. When the inhibit input
terminal is high, all channels are off.
"'tJ
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C
("")
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S
m
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en
The 'HC4051 is a single eight-channel multiplexer/demultiplexer having three binary control inputs (SO,
S 1, and S2) and an enable input (13). The three binary signals select one of eight channels to be turned on.
The 'HC4052 is a dual four-channel multiplexer/demultiplexer having two control inputs (SO and S1) and
an enable input (<3). The two binary signals select one of four channels in each of the two sections.
The 'HC4053 is a triple two-channel multiplexer/demultiplexer having three separate control inputs (1 S,
2S, and 3S) and a common enable input (<3). Each S input independently selects one of two channels in
one of the three sections.
The SN54HC4051, SN54HC4052, and SN54HC4053 are characterized for operation over the full military
temperature range of - 55 ac to 125 ac. The SN74HC4051, SN74HC4052, and SN74HC4053 are
characterized for operation from - 40 ac to 85 ac.
'HC4051
'HC4052
'HC4053
FUNCTION TABLE
FUNCTION TABLE
FUNCTION TABLE
(EACH BILATERAL SWITCH)
(EACH BILATERAL SWITCH)
INPUTS
5-66
FIGURE 1. INTERNAL POWER SUPPLY CONNECTIONS
CHANNEL
G
S2
Sl
SO
TURNED ON
H
L
X
L
X
L
X
L
None
G
Sl
SO
TURNED ON
G
S
TURNED ON
0
H
X
X
None
H
X
None
L
L
L
H
1
L
L
L
0
L
L
L
L
H
L
2
L
L
H
1
L
H
0
1
L
L
H
H
H
L
2
H
L
L
L
H
H
3
H
3
4
5
6
7
L
L
L
H
L
L
H
H
L
L
H
H
H
INPUTS
CHANNEL
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
INPUTS
CHANNEL
3E
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC4316. SN74HC4316
QUAD BILATERAL SWITCHES
02804. MARCH 1984
•
SN54HC4316 .•• J PACKAGE
SN74HC4316 ... J OR N PACKAGE
(TOP VIEW)
Fast Switching Speeds
•
Low Crosstalk Between Switches
•
High On/Off Output Voltage Ratio
•
Analog Supply Voltage Range
(VCC-VEE) ... 3 V to 12 V
•
Digital Supply Voltage Range
(VCC-GND) ... 2 V to 6 V
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
1A
18
28
2A
2C
3C
G
GND
VCC
1C
4C
4A
48
38
3A
VEE
SN54HC4316 ... FH OR FK PACKAGE
SN74HC4316 ... FH OR FN PACKAGE
(TOP VIEW)
The 'HC4316 is a quadruple bilateral switch. The
switches can transmit analog or digital signals
in either direction. The 'HC4316 offers high
control input impedance and low crosstalk
between switches.
Applications include digital switching and
multiplexing analog-to-digital and digital-toanalog conversion; digital control of frequency,
impedance, phase and analog-signal gain; and
use as a squelch control, chopper, modulator,
demodulator, or commutating switch.
The SN54HC4316 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74HC4316 is
characterized for operation from - 40°C to
85°C.
(J)
u
co«uuu
........ 2> ....
description
~
W
28
2A
4C
4A
NC
NC
2C
3C
48
38
>
w
a:
Q.
I-
o
::l
C
o
a:
Q.
NC-No internal connection
II
logic symbol
logic diagram, each switch (positive logic)
B
Pin numbers shown are for J and N packages.
84
PRODUCT PREVIEW
ThIs document contalnslnformatlon on 8 product under
development. Texas Instruments reserves the right to
change or discontinue this product without notic ••
Copyright © 1984. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265
5-67
"'tJ
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!S
m
:e
rJ)
II
5-68
TYPES SN54HC4511, SN74HC4511
BCD·TO·SEVEN·SEGMENT DECODERS/DRIVERS
WITH LATCHED INPUTS
HIGH·SPEED
CMOS LOGIC
02684, DECEMBER 1982-REVISED MARCH 1984
•
SN54HC4511 ... JPACKAGE
SN74HC4511 ... J OR N PACKAGE
(TOP VIEW)
Latch Storage of Code
•
Blanking Input
•
Lamp Test Provision
B
VCC
f
C
•
Readout Blanking on All Illegal Input Combinations
Lr
G
Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic
and Ceramic DIPs
LE
o
BI
D
A
Dependable Texas Instruments Quality and Reliability
GND
description
SN54HC4511 ... FH OR FK PACKAGE
SN74HC4511 ... FH OR FN PACKAGE
(TOP VIEW)
The 'HC4511 provides the functions of a 4-bit storage latch, a
BCD-to-seven-segment decoder, and an output driver. Lamp test
(U), blanking (Si), and latch enable (eE) inputs are used to test the
display, to turn off or pulse-modulate the brightness of the
display, and to store a BCD code, respectively.
.
U
U
ID Z
en
>~ _
3:
w
>
w
IT
The SN54HC4511 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC4511
is characterized for operation from -40°C to 85°C.
Bi
NC
a:
NC
c.
IT
IU
::J
D
FUNCTION TABLE
9 1011 1213
INPUTS
184
OUTPUTS
LE
BI
LT
D
C
L
H
H
L
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
H
L
H
H
B
L
A
a
b
c
d
e
f
L
H
H
H
H
H
H
L
L
H
L
'H
H
L ' L
L
L
1
L
H
L
H
H
L
H
H
L
H
L
H
H
H
H
H
H
L
H
L
H
L
L
L
H
H
L
L
L
H
H
2
3
4
L
H
L
H
H
L
H
H
L
H
H
L
H
H
L
L
L
H
H
H
H
H
9
L
L
H
H
L
H
H
H
H
H
H
L
L
L
L
H
H
H
L
L
L
H
H
H
H
H
H
H
L
H
H
H
L
L
H
H
H
H
L
L
H
H
BCD/7·SEG [>
[T4)
H
H
H
L
H
L
L
L
L
L
L
L
L
Blank
H
H
H
L
H
H
L
L
L
L
L
L
Blank
H
H
L
L
L
L
c.
logic symbol
L
L
a:
NC-No internal connection
L
L
H
o
t:)
L
H
C
Z Z
0
5
6
7
8
9-
L
L
«ClUQl'O
DISPLAY
L
L
L
Blank
IT
BI
IE
C9
A
90
Vll
(13)
Gl0
al0,11
bl0,11
cl0,11
dl0,11
el0,ll
L
H
H
H
H
L
H
L
L
L
L
L
L
L
Blank
B
L
H
H
H
H
H
L
L
L
L
L
L
L
L
Blank
C
4
110,11
L
H
H
H
H
H
H
L
L
L
L
L
L
L
Blank
D
8
g10,11
X
X
L
X
X
X
X
H
H
H
H
H
H
H
8
X
L
H
X
X
X
X
L
L
L
L
L
L
L
Blank
H
H
H
X
X
X
X
(12)
Pin numbers shown are for J and N packages.
All outputs remain in state
existing before LEI
PRODUCT PREVIEW
This document contains information on a product under
development. Texas Instruments reserves the right to
change or discontinue this product without notice.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TeXAS 75265
Copyright ©1982 by Texas Instruments Incorporated
5-69
TYPES SN54HC4511, SN74HC4511
BCD·TO·SEVEN·SEGMENT DECODERS/DRIVERS WITH LATCHED INPUTS
FONT TABLE T4 RESULTANT DISPLAYS USING 'HC4511
SEGMENT IDENTIFICATION
II_II :Ie' 131'-II =,j b I-n l:::i'-/I
23456789
maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
"'C
::tI
o
C
C
(')
-I
"'C
::tI
m
~
m
~
en
5-70
TEXAS.
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
TYPES SN54HC4514, SN54HC4515, SN74HC4514, SN74HC4515
4·LlNE TO 16·LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES'
HIGH·SPEED
CMOS LOGIC
02684, DECEM8ER 1982-REVISED MARCH 1984
•
Two Output Options:
'HC4514 Has Active·High Outputs
'HC4515 Has Active·Low Outputs
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
SN54HC' ... JT PACKAGE
SN74HC' ... JT OR NT PACKAGE
(TOPVIEWI
LE
G
B
D
Y7
Y6
Dependable Texas Instruments Quality and
Reliability
•
C
Y10
Y5
Yll
Y4
ya
description
Y9
These devices present two output options of a
4-line to 16-line decoder with latched inputs. The
'HC4514 presents a high level at the selected
output. The 'HC4515 presents a low level at the
selected output.
INPUTS
OUTPUT
LE
G
D
C
B
A
H
L
L
L
L
L
H
L
L
L
L
H
H
L
L
L
H
L
2
H
L
L
H
H
.3
H
L
L
L
H
L
L
4
H
L
L
H
L
H
5
H
L
L
H
H
L
6
SELECTED
0
1
H
L
L
H
H
H
7
H
L
H
L
L
L
a
OUTPUTS
'HC4514
II
IAll Olh",
.,
Y12
Y13
en
~
w
:>w
C
Y6
Y10
Y5
Y11
NC
Y4
ya
Y3
Y9
Y1
Y14
t-
U
:::l
C
NC
oa:
Q.
II
NOOUMNIl'l
>- >- l:)
Z Z >- ->- >NC-No internal connection
'HC4515
Selected
Output = L
L All others = H
H
L
H
L
L
H
9
H
L
H
L
H
L
10
H
L
H
L
H
H
11
H
L
H
H
L
L
12
H
L
H
H
L
H
13
H
L
H
H
H
L
14
H
L
H
H
H
H
15
X
H
X
X
X
X
L
L
X
X
X
X All outputs remain in state existing before LEI
All = H
Copyright
PRODUCT PREVIEW
Thil document conllln.lnformadon on • product under
development. Tex•• lnltruments relervelthe right to
change or dilcontinue thil product without notice.
YO
GND
a:
Selected
AII=L
Y15
Q.
Output = H
0
Y14
Y2
Y7
The SN 54HC4514 and the SN 54HC451 5 are
characterized for operation over the full military
temperature range of - 55 ac to 125 ac. The
SN74HC4514 and SN54HC4515 are
characterized for operation from - 40°C to
85°C.
FUNCTION TABLE
Y1
SN54HC' ... FH OR FN PACKAGE
SN74HC' ... FH OR FN PACKAGE
(TOPVIEWI
These devices consist of four storage latches
with common latch enable (LE) and inhibit (3)
inputs. When a low signal is applied to the LE
input, the input data is stored, decoded, and
presented to the output. When G is high, all
sixteen 'HC4514 outputs are at a low logic level,
or all'HC4515 outputs are at a high logic level.
84
VCC
A
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
© 1982, Texas Instruments Incorporated
5-71
TYPES SN54HC4514, SN54HC4515, SN74HC4514, SN74HC4515
4·LlNE TO 16·LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
'HC4514 logic symbols (alternatives)
x/v
LE
A
B
(1)
(2)
(3)
C20
200
2
C
0
4
8
C
13
14
15
""0
0
C
(")
-I
""0
:ll
m
(10)
(8)
(7)
V3
V4
V5
V6
V7
V10
V11
(15)
OMUX
VO
V1
V2
V8
V9
8
:ll
EN
(9)
2
3
4
5
6
9
10
11
12
G
(11)
0
LE
(1)
A
}G&
B
C
0
G
0
(11)
(9)
vo
V1
2
3
4
5
6
V2
V3
V4
V5
V6
7
V7
V8
V9
V10
V11
V12
V13
V14
V15
8
9
10
11
V12
V13
V14
12
13
14
V15
15
(15)
Pin numbers shown are for JT and NT packages.
'HC4515 logic symbols (alternatives)
::=
m
XIV
~
en
II
LE
(1 )
C20
200
B
1
2
C
0
4
8
A
G
EN
0
1
2
3
4
5
6
7
vo
8
V8
V9
V1
V2
V3
V4
V5
V6
V7
9
10
V10
Vll
11
12
13
14
15
OMUX
0
vo
V1
LE
(1)
C20
200
A
B
C
0
G
}G&
4
5
6
7
8
9
10
11
V12
V13
V14
12
13
14
V15
15
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
Pin numbers shown are for JT and NT packages.
5-72
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3E
TYPES SN54HC4514, SN54HC4515, SN74HC4514, SN74HC4515
4·LlNE TO 16·LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
'HC4514 logic diagram (positive logic)
C/)
~
W
>
w
a:
Q.
I-
(.)
::J
C
oa:
'HC4515 logic diagram (positive logic)
Q.
II
Pin numbers shown are for JT and NT packages.
.84
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
5-73
TYPES SN54HC4514, SN54HC4515, SN74HC4514, SN74HC4515
4·LlNE TO 16·LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
absolute maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-10.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TA == 25°C
VCC
MAX
MIN
tw
Pulse duration. LE high
Setup time. A thru D before LE.j,
tsu
":ao
c
c:
n
th
Hold time. A thru D before LE.j,
2V
40
4.5 V
8
6V
7
2V
50
4.5 V
10
6V
2V
9
0
4.5 V
0
6V
0
SN54HC4514
SN54HC4515
MIN
MAX
SN74HC4514
SN74HC4515
MIN
UNIT
MAX
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), Cl = 50 pF (see Note 1)
-t
PARAMETER
:a
"
FROM
TO
(INPUT)
(OUTPUT)
VCC
A thru D
Any
4.5 V
24
6V
21
m
TA == 25°C
MIN
tpd
:E
(J)
tpd
tpd
tt
Cpd
LE
G
Any
Any
Any
MAX
SN54HC4515
MIN
MAX
SN74HC4514
SN74HC4515
MIN
UNIT
MAX
72
2V
:sm
TYP
SN54HC4514
2V
78
4.5 V
26
6V
22
2V
60
4.5 V
20
6V
17
2V
38
4.5 V
8
6V
6
ns
ns
ns
ns
60 pF typ
Power dissipation capacitance
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
5-74
TEXAS
l!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
30
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC7001, SN74HC7001
QUADRUPLE POSITIVE·AND GATES WITH SCHMITT·TRIGGER INPUTS
02831, MARCH 1984
•
Operation from Very Slow Transitions
•
Temperature·Compensated Threshold Levels
•
High Noise Immunity
•
Same Pinouts as 'HC08
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC7001 ... J PACKAGE
SN74HC7001 ... J OR N PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
VCC
4B
4A
4Y
3B
3A
3Y
SN54HC7001 ... FH OR FK PACKAGE
SN74HC7001 ... FH OR FN PACKAGE
description
(TOP VIEW)
Each circuit functions as a quadruple AND gate,
They perform the Boolean function Y = A· B or
Y = A+ B in positive logic. However, because
of the Schmitt action, the inputs have different
input threshold levels for positive- and negativegoing signals.
U
m'w
a:
c.
I-
U
The SN54HC7001 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC7001 is
characterized for operation from - 40°C to
85°C.
::J
C
oa:
NC - No internal connection
c.
FUNCTION TABLE
logic symbol
1A
1B
2A
2B
3A
3B
4A
4B
(1)
(2)
II
(each gate)
...IT
INPUTS
&
(3) 1Y
.IT
(4)
(6) 2Y
(5)
OUTPUT
A
B
Y
H
H
H
L
X
L
X
L
L
(9)
(8) 3Y
(10)
logic diagram, each gate (positive logic)
(12)
(11) 4Y
(13)
Pin numbers shown are for J and N packages,
34
Copyright © 1984, Texas Instruments Incorporated
PRODUCT PREVIEW
This document contains information on a product under
development. Texa.lnstruments reserves the right to
change or discontinue this product without notice.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
5-75
TYPES SN54HC7001, SN74HC7001
QUADRUPLE POSITIVE·AND GATES WITH SCHMITT·TRIGGER INPUTS
absolute maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
."
FROM
(INPUT)
A or B
TO
(OUTPUTI
Y
Any
vCC
TA = 25°C
MIN
TYP MAX
2V
40
4.5 V
13
6V
11
2V
28
4.5 V
8
6V
6
SN54HC7001
MIN
NOTE 1: For load circuit and voltage waveforms. see page 1·14 .
:xl
o
C
C
n
~
."
~
m
S
m
~
rn
5-76
TEXAS "'"
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
MAX
SN74HC7001
MIN
MAX
UNIT
ns
ns
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC7002, SN74HC7002
QUADRUPLE POSITIVE·NOR GATES WITH SCHMITT·TRIGGER INPUTS
D2831, MARCH 1984
o
Operation from Very Slow Transitions
4)
Temperature-Compensated Threshold Levels
o
High Noise Immunity
o
Same Pinouts as 'HC36
o
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
o
Dependable Texas Instruments Quality and
Reliability
SN54HC7002 , , , J PACKAGE
SN74HC7002 ... J OR N PACKAGE
(TOP VIEW)
1A
18
1Y
2A
28
2Y
VCC
48
4A
4Y
38
3A
3Y
GND
SN54HC7002 ..• FH OR FK PACKAGE
SN74HC7002 ... FH OR FN PACKAGE
description
(TOP VIEW)
Each circuit functions as a quadruple NOR gate.
They
perform the
Boolean function
y = A + B or Y = Ao"B in positive logic.
However, because of the Schmitt action, the
inputs have different input threshold levels for
positive- and negative-going signals.
U
m«UUm
en
z>.;t
~
The circuits are temperature compensated and
can be triggered from the slowest of input ramps
and will still give clean jitter-free output signals.
W
4A
NC
4Y
NC
38
1Y
NC
2A
NC
28
>
w
a:
c..
.....
u
:::>
c
The SN54HC7002 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC7002 is
characterized for operation from - 40°C to
85°C.
o
a:
NC - No internal connection
c..
FUNCTION TABLE
II
logic symbol
INPUTS
OUTPUT
lA
A
B
V
1B
H
X
L
X
H
L
L
L
H
2A
2B
3A
logic diagram, each gate (positive logic)
3B
:~v
4A
4B
Pin numbers shown are for J and N packages.
PRODUCT PREVIEW
This document contain. Informetion on a product under
development. Texas Instruments rsssrves the right to
change or discontinue this product without notice.
'1.!1
INSTRUMENTS
TEXAS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
Copyright © 1984, Texas Instruments Incorporated
5-77
TYPES SN54HC7002, SN74HC7002
QUADRUPLE POSITIVE-NOR GATES WITH SCHMITT-TRIGGER INPUTS
absolute maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-4.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
""C
:xl
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
Any
VCC
TA = 25°C
MIN
TYP MAX
2V
40
4.5 V
13
6V
11
2V
28
4.5 V
8
6V
6
SN54HC7002
MIN
MAX
SN74HC7002
MIN
MAX
UNIT
ns
ns
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
o
C
C
n
-I
""C
:xl
m
!S.
m
~
rn
5-78
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3E
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC7003, SN74HC7003
QUADRUPLE POSITIVE·NAND GATES WITH SCHMITT·TRIGGER INPUTS
AND OPEN·DRAIN OUTPUTS
02831. MARCH 1984
•
Operation from Very Slow Transitions
•
Temperature-Compensated Threshold Levels
•
High Noise Immunity
•
Same Pinouts as 'HC03
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54HC7003 ••• J PACKAGE
SN74HC7003 •.. J OR N PACKAGE
(TOP VIEW)
1A
18
1Y
2A
2B
2Y
VCC
4B
4A
4Y
3B
3A
3Y
GND
SN54HC7003 ..• FH OR FK PACKAGE
SN74HC7003 ... FH OR FN PACKAGE
(TOP VIEW)
description
Each circuit functions as a quadruple NAND
gate. They perform the Boolean function
y = A. B or Y = A+ B in positive logic.
However, because of the Schmitt action, the
inputs have different input threshold levels for
positive- and negative-going signals.
a:l <{ U
U
U a:l
en
.... .... Z>o:t
3
The circuits are temperature compensated and
can be triggered from the slowest of input ramps
and will still give clean jitter~free output signals.
2
~
1 20 19
1Y
4A
NC
NC
2A
4Y
NC
NC
2B
38
w
:>
w
a:
Q.
~
9 10 11 1213
The SN54HC7003 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC7003 is
characterized for operation from - 40°C to
85°C.
CJ
::l
>-OU>-<{
NZZMM
C
(!)
o
a:
Q.
NC - No internal connection
FUNCTION TABLE (each gate)
logic symbol
INPUTS
A
B
V
18
H
H
L
L
X
H
X
L
H
2A
II
OUTPUT
1A
28
3A
logic diagram, each gate (positive logic)
38
4A
48
Pin numbers shown are for J and N packages.
34
PRODUCT PREVIEW
This document contains information on a product undar
development. Texallnstruments relerves the right to
chang. or discontinue this product without notice.
~
TEXAS
INSTRUMENTS
POST OFFiCE BOX 225012 e DALLAS. TEXAS 75265
Copyright
© 1984. Texas Instruments Incorporated
5-79
TYPES SN54HC7003, SN74HC7003
QUADRUPLE POSITIVE·NAND GATES WITH SCHMITT·TRIGGER INPUTS
AND OPEN·DRAIN OUTPUTS
absolute maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2·4.
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted), CL = 50 pF (see Note 1)
.
~
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
vCC
TA = 25°C
TYP MAX
MIN
2V
tpd
tt
A or B
Y
Any
SN54HC7003
MIN
MAX
SN74HC7003
MIN
MAX
UNIT
40
4.5 V
13
6V
11
2V
28
4.5 V
8
6V
6
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14 .
."
:Xl
o
C
C
(")
-I
."
:Xl
m
<
m
~
en
5-80
-I/}
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
3E
TYPES SN54HC7006, SN74HC7006
6·SECTION MULTIFUNCTION (NAND, INVERT, NOR) CIRCUITS
HIGH·SPEED
CMOS LOGIC
02831. MARCH 1984
•
•
SN54HC7006 ..• JT PACKAGE
SN74HC7006 ... JT OR NT PACKAGE
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
Dependable Texas Instruments Quality and
Reliability
(TOP VIEW)
1A
18
NAND
1Y
INV
(131
(161
(171
(181
(191
(201
INV
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1C
5
6Y
10
6
68
2A
7
6A
::J
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8
NC
5C
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58
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2C
2Y
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....... _ _.J-'
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logic symbol
(41
(51
(61
5A
5Y
4Y}
SN54HC7006 ..• FH OR FK PACKAGE
SN74HC7006 .•• FH OR FN PACKAGE
(TOP VIEW)
The SN54HC7006 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC7006 is
characterized for operation from - 40°C to
85°C.
1C
10
2A
2B
58
3A
GND
NOR
6A
5C
28
2C
2Y
3Y
NAND
They perform the Boolean functions shown
under each function table.
1A (11
1B (21 .
6C
6Y
68
1C
1D
2A
description
The SN54HC7006 and SN74HC7006 are each
comprised of the following sections:
One 3-input NAND gate
One 4-input NAND gate
One 3-input NOR gate
One 4-input NOR gate
Two inverters
VCC
6D
l?
1
NC - No internal connection
·1
~1
~1
6C (22)
60 (231
Pin numbers shown are for JT and NT packages.
:4
Copyright © 1984 by Texas Instruments Incorporated
PRODUCT PREVIEW
ThIs document contain. information on 8 product under
development. Texas Instruments reserves the right to
change or discontinue this product without notice.
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
5-81
TYPES SN54HC7006, SN74HC7006
6·SECTION MULTIFUNCTION (NAND, INVERT, NOR) CIRCUITS
logic diagrams (positive logic)
4·INPUT NAND GATE
FUNCTION TABLE
INPUTS
OUTPUT
A
B
C
D
H
H
H
H
L
L
X
X
X
L
X
X
X
H
X
X
X
X
X
X
L
H
L
Y
H
H
positive logic: Y = A· B· C' D or
Y = A+B+C+D
"tI
3·INPUT NAND GATE
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FUNCTION TABLE
INPUTS
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OUTPUT
A
B
C
H
H
H
L
X
X
X
L
X
X
X
L
Y
L
H
H
H
positive logic: Y = A·B·C or
m
Y = A+B+C
:E
rn
INVERTERS
FUNCTION TABLE
(EACH INVERTER)
3A~3Y
INPUT
OUTPUT
A
Y
L
H
H
4A~4Y
L
positive logic: Y =
A
3·INPUT NOR GATE
FUNCTION TABLE
OUTPUT
INPUTS
A
B
C
Y
H
X
L
X
X
H
X
X
X
H
L
L
L
L
H
L
positive logic: Y = A + B + Cor,
Y = A'B'C
Pin numbers shown are for JT and NT packages.
5-82
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
3E
TYPES SN54HC7006. SN74HC7006
6·SECTION MULTIFUNCTION (NAND. INVERT. NOR) CIRCUITS
logic diagram (positive logic)
4·INPUT NOR GATE
FUNCTION TABLE
INPUTS
OUTPUT
A
B
C
D
Y
H
X
X
X
L
X
H
X
X
L
X
X
H
X
L
X
X
X
H
L
L
L
L
L
H
positive logic: Y = A + B + C + D or
Y = A'B'C'D
Pin numbers shown are for JT and NT packages.
absolute maximum ratings, recommended operating conditions, electrical characteristics
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See Table I, page 2-4.
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TEXAS.
INSTRUMENTS
POST OFFICE BOX 22,012 • DALLAS. TEXAS 75265
5-83
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5-84
HIGH·SPEED
CMOS LOGIC
TYPES SN54HC7032. SN74HC7032
QUADRUPLE POSITIVE·OR GATES WITH SCHMITT·TRIGGER INPUTS
D2831. MARCH 1984
SN54HC7032 •.. J PACKAGE
SN74HC7032 ... J OR N PACKAGE
•
Operation from Very Slow Transitions
•
Temperature·Compensated Threshold Levels
•
High Noise Immunity
•
Same Pinouts as 'HC32
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to PJastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
(TOP VIEW)
1A
18
1Y
2A
28
2Y
VCC
48
4A
4Y
38
3A
3Y
GND
SN54HC7032 ... FH OR FK PACKAGE
SN74HC7032 ..• FH OR FN PACKAGE
description
(TOP VIEW)
Each circuit functions as a quadruple OR gate.
They
perform
t~Boolean
function
Y = A+B or Y = A.S in positive logic.
However, because of the Schmitt action, the
inputs have different input threshold levels for
positive· and negative-going signals.
U
co.:t
4A
NC
4Y
NC
38
1Y
NC
2A
NC
28
The circuits are temperature compensated and
can be triggered from the slowest of input ramps
and will still give clean jitter-free output signals.
:>w
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....
(J
The SN54HC7032 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74HC7032 is
characterized for operation from - 40°C to
85°C.
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NC-No internal connection
0.
FUNCTION TABLE
II
logic symbol
INPUTS
IT
1A
;;;'1
(3) 1Y
IT
1B
2A
(6) 2Y
OUTPUT
A
B
Y
H
X
H
X
H
H
L
L
L
2B
3A
(8) 3Y
logic diagram, each gate (positive logic)
3B
4A
4B
(13)
:~v
(11) 4Y
Pin numbers shown are for J and N packages.
Copyright © 1984. Texas Instruments Incorporated
PRODUCT PREVIEW
This document contain. Information on a product under
development. Texas Instruments feserves the right to
change or discontinue this product without notice.
TEXAS
"-!}
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
5-85
TYPES SN54HC7032, SN74HC7032
QUADRUPLE POSITIVE·OR GATES WITH SCHMITT·TRIGGER INPUTS
absolute maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-6.
switching characteristics over recommended free-air temperature range (unless otherwise noted).
CL = 50 pF (see Note 1)
PARAMETER
tpd
tt
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
Any
VCC
TA
MIN
=
25°C
TYP
2V
40
4.5 V
13
6V
11
2V
28
4.5 V
8
6V
6
MAX
SN54HC7032
MIN
SN74HC7032
MIN
MAX
UNIT
ns
ns
NOTE 1: For load circuit and voltage waveforms, see page 1-14.
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TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
GENERAL INFORMATION
RATINGS AND CHARACTERISTICS
HCMOS DEVICES
HCMOS DEVICES - <
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6-2
Explanation of Logic Symbols
F. A. Mann
Contents
Title
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
Page
INTRODUCTION.................................................. 6-5
SYMBOL COMPOSITION ........................................... 6-5
QUALIFYING SYMBOLS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-7
3.1
General Qualifying Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-7
3.2
Qualifying Symbols for Inputs and Outputs ......................... 6-7
3.3
Symbols Inside the Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-11
DEPENDENCY NOTATION ......................................... 6-11
4.1
General Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-11
4.2
G, AND .................................................. 6-12
4.3
Conventions for the Application of Dependency Notation in General ..... 6-13
4.4
V, OR ................................................... 6-14
4.5
N, Negate (Exclusive-OR) ...................... '.' ............. 6-14
4.6
Z, Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-15
4.7
X, Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-16
4.8
C, Control ....................................... .' . . . . . . .. 6-17
4.9
S, Set and R, Reset ......................................... 6-18
4.10 EN, Enable ............................................... 6-18
4.11 M, Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-19
4.12 A, Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-21
BISTABLE ELEMENTS ............................................ 6-23
CODERS...................................................... 6-24
USE OF A CODER TO PRODUCE AFFECTING INPUTS. . . . . . . . . . . . . . . . . . . .. 6-26
USE OF BINARY GROUPING TO PRODUCE AFFECTING INPUTS . . . . . . . . . . . .. 6-26
SEQUENCE OF INPUT LABELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-27
SEQUENCE OF OUTPUT LABELS ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-28
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If you have questions on this Explanation
of Logic Symbols, please contact:
Texas Instruments Incorporated
F.A. Mann, MS 49
P.O. Box 225012
Dallas, Texas 75265
Telephone (214) 995-2867
IEEE Standards may be purchased from:
><
w
Institute of Electrical and Electronics Engineers, Inc.
IEEE Standards Office
345 East 47th Street
New York, N.Y. 10017
International Electrotechnical Commission (IEC)
publications may be purchased from:
American National Standards Institute, Inc.
1430 Broadway
New York, N.Y. 10018
Copyright © 1984, Texas Instruments Incorporated
6-3
List of Tables
Table
I
II
III
IV
Title
General Qualifying Symbols . . . . . . . . . . .
Qualifying Symbols for Inputs and Outputs
Symbols Inside the Outline. . . . . . . . . .. .
Summary of Dependency Notation . . . . . .
Page
.
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. .. 6-8
. .. 6-9
.. 6-10
.. 6-23
List of Illustrations
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6-4
Figure
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Title
Page
Symbol Composition .............................................. 6-6
Common-Control Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-6
Common-Output Element . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. 6-7
G De'pendency Between Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-12
G Dependency Between Outputs and Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-13
G Dependency with a Dynamic Input .... . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-13
ORed Affecting Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-13
Substitution for Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-14
V (OR) Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-14
N (Negate/Exclusive-OR) Dependency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-15
Z (Interconnection) Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-1 5
X (Transmission) Dependency .... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-16
CMOS Transmission Gate Symbol and Schematic . ... . . . . . . . . . . . . . . . . . . . .. 6-16
Analog Data Selector (Multiplexer/Demultiplexer) . . . . . . . . . . . . . . . . . . . . . . . .. 6-16
C (Control) Dependency ............... ; .................... '. . . . . .. 6-17
S (Set) and R (Reset) Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-18
EN (Enable) Dependency .......................................... 6-19
M (Mode) Dependency Affecting Inputs ............. . . . . . . . . . . . . . . . . .. 6-20
Type of Output Determined by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-20
An Output of the Common-Control Block . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. 6-21
Determining an Output's Function ................................... 6-21
Dependent Relationships Affected by Mode ............................ 6-21
A (Address) Dependency ...................... : . . . . . . . . . . . . . . . . . .. 6-22
Array of 16 Sections of Four Transparent Latches with 3-State Outputs
Comprising a 16-Word x 4-Bit Random-Access Memory. . . . . . . . . . . . . . . . . .. 6-23
Four Types of Bistable Circuits ................... .- . . . . . . . . . . . . . . . . .. 6-24
Coder General Symbol ........ : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-24
An XIV Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-25
An X/Octal Code Converter " ..... '1' • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 6-26
Producing Various Types of Dependencies ............................. 6-26
Producing One Type of Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-26
Use of Binary Grouping Symbol ..................................... 6-27
Input Labels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-27
Factoring Input Labels ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-28
Placement of 3-State Symbols '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-28
Output Labels .................................................. 6-28
Factoring Output Labels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-29
1.0
INTRODUCTION
The International Electrotechnical Commission (lEC) has been developing a very powerful
symbolic language that can show the relationship of each input of a digital logic circuit to each
output without showing explicitly the internal logic. At the heart of the system is dependency
notation, which will be explained in Section 4.
The system was introduced in the USA in a rudimentary form in IEEE/ANSI Standard
Y32.14-1973. Lacking at that time a complete development of dependency notation, it offered
little more than a substitution of rectangular shapes for the familiar distinctive shapes for
representing the basic functions of AND, OR, negation, etc. This is no longer the case.
Internationally, Working Group 2 of IEC Technical Committee TC-3 has prepared a new
document (Publication 617-12) that consolidates the original work started in the mid 1960's
and published in 1972 (Publication 117-15) and the amendments and supplements that have
followed. Similarly for the USA, IEEE Committee SCC 11.9 has revised the publication IEEE
Std 91/ANSI Y32.14. Now numbered simply IEEE Std 91-1984, the IEEE standard contains
all of the IEC work that has been approved, and also a small amount of material still under
international consideration. Texas Instruments is participating in the work of both organizations
and this document introduces new logic symbols in accordance with the new standards. When
changes are made as the standards develop, future editions will take those changes into account.
The following explanation of the new symbolic language is necessarily brief and greatly
condensed from what the standards publications will contain. This is not intended to be sufficient
for those people who will be developing symbols for new devices. It is primarily intended to
make possible the understanding of the symbols used in various data books and the comparison
of the symbols with logic diagrams, functional block diagrams, and/or function tables will further
help that understanding.
2.0
SYMBOL COMPOSITION
A symbol comprises an outline or a combination of outlines together with one or more qualifying
symbols. The shape of the symbols is not significant. As shown in Figure 1, general qualifying
symbols are used to tell exactly what logical operation is performed by the elements. Table I
shows general qualifying symbols defined in the new standards. Input lines are placed on the
left and output lines are placed on the right. When an exception is made to that convention,
the direction of signal flow is indicated by an arrow as shown in Figure 11.
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All outputs of a single, unsubdivided element always have identical internal logic states
determined by the function of the eleme-nt except when otherwise indicated by an associated
qualifying symbol or label inside the element.
6-5
OUTLINE
INPUT
LINES
I **
,
**
GENERAL QUALIFYING
SYMBOL
**1
.
OUTPUT
LINES
**
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*Possible positions for qualifying symbols relating to inputs and outputs
Figure 1. Symbol Composition
The outlines of elements may be abutted or embedded in which case the following conventions
apply. There is no logic connection between the elements when the line common to their outlines
is in the direction of signal flow. There is at least one logiG connection between the elements
when the line common to their outlines is perpendicular to the direction of signal flow. The
number of logic connections between elements will be clarified by the use of qualifying symbols
and this is discussed further under that topic. If no indications are shown on either side of
the common line, it is assumed there is only one connection.
When a circuit has one or more inputs that are common to more than one element of the circuit,
the common-control block may be used. This is the only distinctively shaped outline used in
the lEe system. Figure 2 shows that unless otherwise qualified by dependency notation, an
input to the common-control block is an input to each of the elements below the commoncontrol block.
COMMON~ONTROLBLOCK
(J)
Figure 2. Common·Control Block
6-6
A common output depending on all elements of the array can be shown as the output of a
common-output element. Its distinctive visual feature is the double line at its top. In addition
the common-output element may have other inputs as shown in Figure 3. The function of the
common-output element must be shown by use of a general qualifying symbol.
COMMON·OUTPUT
ELEMENT
(must,like other elements,
have a qualifying symbol to
denote its logic function)
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Figure 3. Common-Output Element
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3.0
QUALIFYING SYMBOLS
3.1
General Qualifying Symbols
o...I
Table I shows general qualifying symbols defined by IEEE Standard 91. These characters are
placed near the top center or the geometric center of a symbol or symbol element to define
the basic function of the device represented by the symbol or of the element.
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3.2
Qualifying Symbols for Inputs and Outputs
Qualifying symbols for inputs and outputs are shown in Table II and will be familiar to most
users with the possible exception of the logic polarity and analog signal indicators. The older
logic negation indicator means that the external 0 state produces the internal 1 state. The
internal 1 state means the active state. Logic negation may be used in pure logic diagrams;
in order to tie the external 1 and 0 logic states to the levels H (high) and L (Iowl. a statement
of whether positive logic (1 = H, 0 = L) or negative logic (1 = L, 0 = H) is being used is
required or must be assumed. Logic polarity indicators eliminate the need for calling out the
logic convention and are used in various data books in the symbology for actual devices. The
presence of the triangular polarity indicator indicates that the L logic level will produce the
internal 1 state (the active state) or that, in the case of an output, the internal 1 state will
produce the external L level. Note how the active direction of transition for a dynamic input
is indicated in positive logic, negative logic, and with polarity indication.
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II
The internal connections between logic elements abutted together in a symbol may be indicated
by the symbols shown in Table II. Each logic connection may be shown by the presence of
qualifying symbols at one or both sides of the common line and if confusion can arise about
the numbers of connections, use can be made of one of the internal connection symbols.
6-7
Table I. General Qualifying Symbols
DESCRIPTION
SYMBOL
CMOS
EXAMPLE
EXAMPLE
TTL
&
AND gate or function.
'HCOO
SN7400
2:1
OR gate or function. The symbol was chosen to indicate that at least
one active input is needed to activate the output.
'HC02
SN7402
=1
Exclusive OR. One and only one input must be active to activate the
output.
'HC86
SN7486
Logic identity. All inputs must stand at the same state.
'HC86
SN74180
2k
An even number of inputs must be active.
'HC280
SN74180
m
2k+ 1
An odd number of inputs must be active.
'HC86
SN74ALS86
1
The one input must be active.
'HC04
SN7404
r-
C>or
A buffer or element with more than usual output capability
(symbol is oriented in the direction of signal flow).
'HC240
SN74S436
SN74LS18
><
-C
»
:2
»
:::!
0
Highly complex function; "gray box" symbol with limited
detail shown under special rules.
2m.
'HC4020
SN74187
'HC189
SN74170
SN74LS222
SN74AS877
'HC7022
SN74AS877
SN74LS608
*Not all of the general qualifying symbols have been used in Tl's CMOS and TTL data books, but they are included here for the sake of
completeness.
6-8
Table II. Qualifying Symbols for Inputs and Outputs
Logic negation at input. External
a produces internal 1.
Logic negation at output. Internal 1 produces external O.
Active-low input. Equivalent to
-q in positive logic.
Active-low output. Equivaient to p--in positive logic.
Active·low input in the case of right-to-Ieft signal flow.
Active-low output in the case of right-to-Ieft signal flow.
Signal flow from right to left. If not othen:,ise indicated. signal flow is from left to right_
Bidirectional signal flow.
POSITIVE
LOGIC
Dynamic
inputs
active
on
indicated
transition
'L o
oI'
not used
NEGATIVE
LOGIC
,.-1
POLARITY
INDICATION
0
not used
°L,
not used
HLLH
LS
en
....I
om
2
>
en
u
C!)
o....I
LL
"*1
Nonlogic connection. A label inside the symbol will usually define the nature of this pin.
-LLf
Input for analog signals (on a digital symbol) (see Figure 14).
o
2:
o
Input for digital signals (on an analog symbol) (see Figure 14).
----r---
<
w
1 state on
Internal input (virtual input). It always stands at its internal 1 state unless affected by an
overriding dependency relationship.
Internal output (virtual output). Its effect on an internal input to which it is connected is
indicated by dependency notation.
The internal (virtual) input is an input originating somewhere else in the circuit and is not
connected directly to a terminal. The internal (virtual) output is likewise not connected directly
to a terminal. The application of internal inputs and outputs requires an understanding of
dependency notation, which is explained in Section 4.
6-9
Table III. Symbols Inside the Outline
-+-
Postponed output (of a pulse-triggered flip-flop). The output changes when input
initiating change (e.g., a C input) returns to its initial external state or level. See § 5.
-1JT
Bi·threshold input (input with hysteresis).
Q~
N-P-N open-collector or similar output that can supply a relatively
low-impedance L level when not turned off. Requires external
pull-up. Capable of positive-logic wired-AND connection.
~~
Passive-pull-up output is similar to N-P·N open-collector output but
is supplemented with a built-in passive pull-up.
o~
N-P-N open-emitter or similar output that can supply a relatively lowimpedance H level when not turned off. Requires external pull-down.
Capable of positive-logic wired-OR connection.
~~
Passive-pull-down output is similar to N-P-N open-emitter output but
is supplemented with a built-in passive pull-down.
:::!
\7l----
3-state output.
2
l>~
m
><
"'C
r-
»
2
»
0
0
r0
+
Output with more than usual output capability (symbol is oriented in the direction
of signal flowl.
-1 EN
."
+
Enable input
When at its internal '-state, all outputs are enabled.
When at its internal Q-state, open-collector and open-emitter outputs are off,
three-state outputs are in the high-impedance state, and all other outputs
(e.g., totem-poles) are at the internal O-state.
G')
n
rn
<
0
r-
rn
II
.
---1D
m
--1
--1-
+m
. . . , - 1~
SR
Data Input to a storage element equivalent to:
-1- --1-
m
m
Shift right (left) inputs, m = 1, 2, 3, etc. If m = 1, it is usually not shown.
Counting up (down) inputs, m = 1,2,3, etc. If m = 1, it is usually not shown.
D:}
Binary grouping. m is highest power of 2.
---1CT = 15
The contents-setting input, when active, causes the content of a register to take
on the indicated value.
CT = 9
6-10
Usual meanings associated with flip-flops (e.g., R = reset, T = toggle)
J, K, R, S, T
s:tJ:J
r-
The content output is active if the content of the register is as indicated.
qJ
e.g., The paired expander inputs of SN7450.
"1"1-
Fixed-state output always stands at its internal 1 state. For example, see SN74185.
Input line grouping ... indicates two or more terminals used to implement a single
logic input_
~~JE
In an array of elements, if the same general qualifying symbol and the same qualifying symbols
associated with inputs and outputs would appear inside each of the elements of the array,
these qualifying symbols are usually shown only in the first element. This is done to reduce
clutter and to save time in recognition. Similarly, large identical elements that are subdivided
into smaller elements may each be represented by an unsubdivided outline. The SN54HC242
or SN54LS440 symbol illustrates this principle.
3.3
Symbols Inside the Outline
Table III shows some symbols used inside the outline. Note particularly that open-collector
(open-drain), open-'emitter (open-source), and three-state outputs have distinctive symbols.
An EN input affects all the external outputs of the element in which it is placed, plus the external
outputs of any elements shown to be influenced by that element. It has no effect on inputs.
When an enable input affects only certain outputs, affects outputs located outside the indicated
influence of the element in which the enable input is placed, and/or affects one or more inputs,
a form of dependency notation will indicate this (see 4.10). The effects of the EN input on
the various types of outputs are ~hown.
en
...J
oal
:2E
>
en
~
~
It is particularly important to note that a D input is always the data input of a storage element.
At its internal 1 state, the D input sets the storage element to its 1 state, and at its internal
o state it resets the storage element to its 0 state.
o
...J
LL
o
Z
o
The binary grouping symbol will be explained more fully in Section 8. Binary-weighted inputs
are arranged in order' and the binary weights of the least-significant and the most-significant
lines are indicated by numbers. In this document weights of input and output lines will be
represented by powers of two usually only when the binary grouping symbol is used, otherwise
decimal numbers will be used. The grouped inputs generate an internal number on which a
mathematical function can be performed or that can be an identifying number for dependency
notation (Figure 28). A frequent use is in addresses for memories.
i=
<
w
Reversed in direction, the binary grouping symbol can be used with outputs. The concept is
analogous to that for the inputs and the weighted outputs will indicate the internal number
assumed to be developed within the circuit.
II
Other symbols are used inside the outlines in accordance with the lEG/IEEE standards but are
not shown here. Generally these are associated with arithmetic operations and are selfexplanatory.
When nonstandardized information is shown inside an outline, it is usually enclosed in square
brackets [like these].
4.0
DEPENDENCY NOTATION
4. 1
General Explanation
Dependency notation is the powerful tool that sets the IEC symbols apart from previous systems
and makes compact, meaningful, symbols possible. It provides the means of denoting the
relationship between inputs, outputs, or inpllts and outputs without actually showing all the
6-11
elements and interconnections involved. The information provided by dependency notation
supplements that provided by the qualifying symbols for an element's function.
In the convention for the dependency notation, use will be made of the terms "affecting" and
"affected." In cases where it is not evident which inputs must be considered as being the
affecting or the affected ones (e.g., if they stand in an AND relationship), the choice may be
made in any convenient way.
So far, eleven types of dependency have been defined and all of these are used in various TI
data books. X dependency is used mainly with CMOS circuits. They are listed below in the
order in which they are presented and are summarized in Table IV following 4.12.
m
Section
4.2
4.3
4.4
><
"'C
r-
»2
4.5
4.6
»
::::!
4.7
e
2
e"T1
4.8
4.9
4.10
4.11
4.12
r-
eC)
4.2
Dependency Type or Other Subject
G,AND
General Rules for Dependency Notation
V,OR
N, Negate (Exclusive-OR)
Z, Interconnection
X, Transmission
C, Control
S, Set and R, Reset
EN, Enable
M, Mode
A, Address
G (AND) Dependency
(")
rJ)
-<
S
CJ
er-
rJ)
II
A common relationship between two signals is to have them ANDed together. This has
traditionally been shown by explicitly drawing an AND gate with the signals connected to the
inputs of the gate. The 19721EC publication and the 1973 IEEE/ANSI standard showed several
ways to show this AND relationship using dependency notation. While ten other forms of
dependency have since been defined, the ways to invoke AND dependency are now reduced
to one.
In Figure 4 input b is ANDed with input a and the complement of b is ANDed with c. The letter
G has been chosen to indicate AND relationships and is placed at input b, inside the symbol.
A number considered appropriate by the symbol designer (1 has been used here) is placed after
the letter G and also at each affected. input. Note the bar over the 1 at input c.
--
:=[r_
a
:~--
1
=
c~
Figure 4. G Dependency Between Inputs
In Figure 5, output b affects input a with an AND relationship. The lower example shows that
it is the internal logic state of b, unaffected by the negation sign, that is ANDed. Figure 6 shows
input a to be ANDed with a dynamic input b.
6-12
r=L[J]
=
Figure 5. G Dependency Between Outputs and INputs
a-fG1--
b-t 1
en
..J
=
oal
~
Figure 6. G Dependency with a Dynamic Input
The rules for G dependency can be summarized thus:
When a Gm input or output (m is a number) stands at its internal 1 state, all inputs and
outputs affected by Gm stand at their normalfy defined internal logic states. When the
Gm input or output stands at its 0 state, all inputs and outputs affected by Gm stand
at their internal 0 states.
4.3
Conventions for the Application of Dependency Notation in General
>
en
u
CJ
o..J
U.
o
2
o
i=
The rules for applying dependency relationships in general follow the same pattern as was
illustrated for G dependency.
«
2
«
..J
c.
Application of dependency notation is accomplished by:
X
1)
2)
labeling the input (or output) affecting other inputs or outputs with the letter symbol
indicating the relationship involved (e.g., G for AND) followed by an identifying number,
appropriately chosen, and
labeling each input or output affected by that affecting input (or output) with that
same number.
EI
w
•
If it is the complement of the internal logic state of the affecting input or output that does
the affecting, then a bar is placed over the identifying numbers at the affected inputs or outputs
(Figure 4).
If two affecting inputs or outputs have the same letter and same identifying number, they stand
in an OR relationship to each other (Figure 7).
a=i
G-1-
b
G1
c
1
=
a~~1
b
&
c
Figure 7. ORed Affecting Inputs
6-13
If the affected input or output requires a label to denote its function (e.g., "0"), this label will
be prefixed by the identifying number of the affecting'input (Figure 15).
If an input or output is affected by more than one affecting input, the identifying numbers of
each of the affecting inputs will appear in the. label of the affected one, separated by commas.
The normal reading order of these numbers is the same as the sequence of the affecting
relationships (Figure 15).
If the labels denoting the functions of affected inputs or outputs must be numbers (e.g., outputs
of a coder), the identifying numbers to be associated with both affecting inputs and affected
inputs or outputs will be replaced by another character selected to avoid ambiguity, e.g., Greek
letters (Figure 8).
m
><
."
=t
a
b
rl>
C
2
l>
=[
a
Ga
ex
b
--
1
~1
1
c
Figure 8. Substitution for Numbers
:::!
o
2
o'"T1
-
a
4.4
V (OR) Dependency
The symbol denoting OR dependency is the letter V (Figure 9).
r-
oG)
(')
en
~:- =ro=
-('
S
OJ
o
ren
;;;.1
--
3 £ = -a
a
b
_
b
--
Figure 9. V (OR) Dependency
When a Vm input or output stands at its internal 1 state, all inputs and outputs affected by
Vm stand at their internal 1 states. When the Vm input or output stands at its internal 0 state,
all inputs and outputs affected by Vm stand at their normally defined internal logic states.
4.5
N (Negate) (Exclusive-OR) Dependency
The symbol denoting negate dependency is the letter N (Figure 10). Each input or output affected
by an Nm input or output stands in an Exclusive-OR relationship with the Nm input or output.
6-14
If a =0, then c =b
If a = 1, then c = ii
Figure 10. N (Negate) (Exclusive·OR) Dependency
When an Nm input or output stands at its internal 1 state, the internal logic state of each input
and each output affected by Nm is the complement of what it would otherwise be. When an
Nm input or output stands at its internal 0 state, all inputs and outputs affected by Nm stand
at their normally defined internal logic states.
en
...J
oal
~
4.6
>
en
Z (Interconnection) Dependency
(.)
The symbol denoting interconnection
dep~ndency
is the letter Z.
~
Interconnection dependency is used to indicate the existence of internal logic connections
between inputs, outputs, internal inputs, and/or internal outputs.
The internal logic state of an input or output affected by a Zm input or output will be the same
as the internal logic state of the Zm input or output, unless modified by additional dependency
notation (Figure 11).
where
o
...J
LL
o
2
o
t=
<
W
where
II
a-fGl;Lc
b-t!zl J
Figure 11. Z (Interconnection) Dependency
6-15
4.7
X (Transmission) Dependency
The symbol denoting transmission dependency is t.he letter X.
Transmission dependency is used to indicate controlled bidirectional connections between
affected input/output ports (Figure 12).'
.
.
If a = " there is a bidirectional
connection between band c.
If a = 0, there is a bidirectional
connection between c and d.
m.
><
-a
rl>
z
l>
::!
o
Figure 12. X (Transmission) Dependency
When an Xm input or output stands at its internal 1 state, all input-output ports affected by
this Xm input or output are bidirectionally connected together and stand at the same internal
logic state or analog signal level. When an Xm input or output stands at its internal 0 state, .
the connection associated with this set of dependency notation does not exist.
z
o."
n
~
r-
'-1II-'
T
oCi)
o
C/)
s:-
CI)
Note AND relationship of a and b
~
c.J
-
i
a
b
c
G1
1.20
~
o...I
=
C2
a
120
b
1.20
LL
o
a~;;'1
_
&
& S
c
G1
b
c
d
C2
d
&
Z
o
i=
R
«
z
«
-
...I
Input c selects which of a or b is stored when d goes low.
Q.
X
Figure 15. C (Control) Dependency
W
When a Cm input or output stands at its internal 1 state, the inputs affected by Cm have their
normally defined effect on the function of the element, i.e., these inputs are enabled. When
a Cm input or output stands at its internal 0 state, the inputs affected by Cm are disabled and
.
have no effect on the function of the element.
II
6-17
4.9
The symbol denoting set dependency is
the letter S. The symbol denoting reset
dependency is the letter R.
Set and reset dependencies are used if it
is necessary to specify the effect of the
combination R = S = 1 on a bistable
element. Case 1 in Figure 16 does not use
S or R dependency.
m
)(
."
r-
»
z
»
-I
5
z
When an Sm input is at its internal 1 state,
outputs affected by the Sm input will
react, regardless of the state of an R input,
as they normally would react to the
combination S = 1, R =0. See cases 2, 4,
and 5 in Figure 16.
oG)
m
When an Sm or Rm input is at its internal
o state, it has no effect.
o
r-
n
-<
s:to
o
rm
s-1l-:
R-LJ-a
s---fl-:
R---lJ-a
s-fl-a
R--t5s---fl-:
Note that the noncomplementary output
patterns in cases 4 and 5 are only pseudo
stable. The simultaneous return of the
inputs to S = R = 0 produces an
unforeseeable stable and complementary
output pattern.
R
Q
0
0
nc nc
0 1
1
0
1
1
?
?
S
0
0
R
Q
Q
0
1
1
0
1
nc nc
0 1
1
0
1
0
S
0
0
R
Q
0
1
nc nc
0 1
1
0
0 1
R
Q
0
0
nc nc
0 1
1
0
1
1
1
1
S
0
0
R
Q
Q
0
1
1
0
nc nc
0 1
0
1
0 0
S
0
0
1
1
Q
CASE 2
1
CASE 3
0
When an Am input is at its internal 1 state,
outputs affected by the Rm input will
react, regardless of the state of an S input,
as they normally would react to the
combination S =0, R = 1. See cases 3, 4,
and 5 in Figure 16.
."
CASE 1
S (Set) and R (Reset) Dependencies
1
1
1
0
Q
CASE 4
R~a
S
0
0
1
1
Q
CASE 5
s---fl-:0
R--t5o= external 0 state
nc =no change
1
1
1 = external 1 state
1 =unspecified
Figure 16. S (Set) and R (Reset) Dependencies
4.10 EN (Enable) Dependency
The symbol denoting enable dependency is the combination of letters EN ..
An ENm input has the same effect on outputs as an EN input, see 3.3, but it affects only those
outputs labeled with the identifying number m. It also affects those inputs labeled with the
identifying number m. By contrast, an EN input affects all outputs and no inputs. The effect
of an ENm input on an affected input is identical to that of a Cm input (Figure 17).
6-18
When an ENm input stands at its internal 1 state, the inputs affected by ENm have their normally
defined effect on the function of the element and the outputs affected by this input stand at
their normally defined internal logic states, i.e., these inputs and outputs are enabled.
1V'
b
-.----iEN1
If a = 0, b is disabled and d = c
Ita = 1, c is disabled and d = b
en
Figure 17. EN (Enable) Dependency
..J
om
When an ENm input stands at its internal 0 state, the inputs affected by ENm are disabled
and have no effect on the function of the element, and the outputs affected by ENm are also
disabled. Open-collector outputs are turned off, three-state outputs stand at their normally
defined internal logic states but externally exhibit high impedance, and all other outputs (e.g.,
totem-pole outputs) stand at their internal 0 states.
:!
>
en
CJ
CJ
o
..J
4.11 M (MODE) Dependency
LL
o
Z
o
The symbol denoting mode dependency is the letter M.
Mode dependency is used to indicate that the effects of particular inputs and outputs of an
element depend on the mode in which the element is operating.
i=
<
"'C
In MODE 2 (b = 0, c = 1), shifting down
and serial loading thru input d take place.
In MODE 3 (b = c = 1), counting up by
increment of 1 per clock pulse takes place.
r-
»
2
»
::!
o
1,40
Figure 18. M (Mode) Dependency Affecting Inputs
2
o
"or-
G)
n
m
-<
s:
DJ
o
r-
m
6-20
4.11.2 M Dependency Affecting Outputs
When an Mm input or Mm output stands at its internal 1 state, the affected outputs stand
at their normally defined internal logic states, i.e., the outputs are enabled.
When an Mm input or Mm output stands at its internal 0 state, at each affected output any
set of labels containing the identifying number of that Mm input or Mm output has no effect
and is to be ignored. When an output has several different sets of labels separated by solidi
(e.g., 2,4/3,5), only those sets in which the identifying number of this Mm input or Mm
output appears are to be ignored.
Figure 19 shows a symbol for a device
whose output can behave like either a
3-state output or an open-collector
output depending on the signal applied
to input a. Mode 1 exists when input
a stands at its internal 1 state and, in
that case, the three-state symbol
applies and the open-element symbol
has no effect. When a = 0, mode 1
does not exist so the three-state symbol
has no effect and the open-element
symbol applies.
M1
b
EN
1 '\1/1Q
d
Figure 19. Type of Output Determined by Mode
In Figure 20, if input a stands at its internal
1 state establishing mode 1, output b will
stand at its internal 1 state only when the
content of the register equals 9. Since
output b is located in the common-control
block with no defined function outside of
mode 1, the state of this output outside
of mode 1 is not defined by the symbol.
In Figure 21, if input a stands at its
internal 1 state establishing mode 1,
output b will stand at its internal 1 state
only when the content of the register
equals 15. If input a stands at its internal
o state, output b will stand at its internal
1 state only when the content of the
register equals O.
In Figure 22 inputs a and b are binary
weighted to generate the numbers 0, 1,
2, or 3. This determines which one of the
four modes exists.
a--f
M1
~b
1CT=9
I
I
I
I
I
(
I
~
Figure 20. An Output of the Common·Control Block
'lMl
l~T'15p-'
1CT=O
I
I
I
I
I
I
~
S
Figure 21. Determining an Output's Function
en
...J
oal
~
>
en
(J
(!)
o
...J
LL
At output e the label set causing negation
(if c = 1) is effective only in modes 2 and
Figure 22. Dependent Relationships
Affected by Mode
3. In modes 0 and 1 this output stands
at its normally defined state as if it had
no labels. At output f the label set has
effect when the mode is not 0 so output
e is negated (if c = 1) in modes 1 , 2, and
3. In mode 0 the label set has no effect so the output stands at its normally defined state.
In this example 5,4 is equivalent to (1/2/3)4. At output 9 there are two label sets. The first
set, causing negation (if c = 1)' is effective only in mode 2. The second set, subjecting 9 to
AND dependency on d, has effect only in mode 3.
o
Z
o
i=
«
z
«
...J
Q.
X
W
Note that in mode 0 none of the dependency relationships has any effect on the outputs, so
e, f, and 9 will all stand at the same state.
4.12 A (Address) Dependency
The symbol denoting address dependency is the letter A.
Address dependency provides a clear representation of those elements, particularly memories,
that use address control inputs to select specified sections of a multildimensional arrays. Such
a section of a memory array is usually called a word. The purpose of address dependency is
to allow a symbolic presentation of the entire array. An input of the array shown at a particular
6-21
element of this general section is common to the corresponding elements of all selected sections
of the array. An output of the array shown at a particular element of this general section is
the result of the OR function of the outputs of the corresponding elements of selected sections.
Inputs that are not affected by any affecting address input have their normally defined effect
on all sections of the array, whereas inputs affected by an address input have their normally
defined effect only on the section selected by that address input.
m
X
rl>
An affecting address input is labeled with the letter A followed by an identifying number that
corresponds with the address of the particular section of the array selected by this input. \7'Jhliin
the general section presented by the symbol, inputs and outputs affected by an Am input are
labeled with the letter A, which stands for the identifying numbers, i.e., the addresses, of the
particular sections.
"tJ
a
2:
b
~
d
l>
c
A1
A2
AJ
C4
EN1
EN2
ENJ
C4
o
2:
o
."
r-
o
G')
Figure 23. A (Address) Dependency
(")
m
-<
s:
D:J
or-
m
II
Figure 23 shows a 3-word by 2-bit memory having a separate address line for each word and
uses EN dependency to explain the operation. To select word 1, input a is taken to its 1 state,
which establishes mode 1. Data can now be clocked into the inputs marked "1,40." Unless
words 2 and 3 are also selected, data cannot be clocked in at the inputs marked "2,40" and
"3,40." The outputs will be the OR functions of the selected outputs, i.e., only those enabled
by the active EN functions.
The identifying numbers of affecting address inputs correspond with the addresses of the
sections selected by these inputs. They need not necessarily differ from those of other affecting
dependency-inputs (e.g., G, V, N, ... ), because in the general section presented by the symbol
they are replaced by the letter A.
If there are several sets of affecting Am inputs for the purpose of independent and possibly
simultaneous access to sections of the array, then the letter A is modified to 1A,
2A, .... Because they have access to the same sections of the array, these sets of A inputs
may have the same identifying numbers. The symbols for 'HC170 or SN74LS170 make use
of this.
Figure 24 is another illustration of the concept.
6-22
RAM 16 X 4
EN
}A~
C1
en
..J
Figure 24. Array of 16 Sections of Four Transparent Latches with 3·State Outputs
Comprising a 16-Word X 4-Bit Random·Access Memory
oCO
Table IV. Summary of Dependency Notation
TYPE OF
DEPENDENCY
LETTER
SYMBOL*
2
AFFECTING INPUT
AT ITS '-STATE
AFFECTING INPUT
AT ITS O-STATE
Address
A
Permits action (address selected)
Prevents action (address not selected)
Control
C
Permits action
Enable
EN
Permits action
Prevents action
Prevents action of inputs
Ooutputs off
~outputs at external high impedance,
no change in internal logic state
Other outputs at internal 0 state
AND
G
Permits action
Imposes 0 state
Mode
M
Permits action (mode selected)
Prevents action (mode not selected)
Negate (Ex-OR)
N
Complements state
No effect
R
Affected output reacts as
it would to S = 0, R = 1
No effect
Set
S
Affected output reacts as
it would to S = 1, R = 0
No effect
OR
V
Imposes 1 state
Permits action
Transmission
X
Bidirectional connection exists
Bidirectional connection does not exist
Interconnection
Z
Imposes 1 state
Imposes 0 state
Reset
>
en
u
CJ
o-I
LL
o
2
o
i=
«
z
«
..J
0..
><
W
"These letter symbols appear at the AFFECTING input (or output) and are followed by a number. Each input (or output) AFFECTED by
that input is labeled with that same number. When the labels EN, R, and S appear at inputs without the following numbers, the descriptions
above do not apply. The action of these inputs is described under "Symbols Inside the Outline," see 3.3.
5.0
II
BISTABLE ELEMENTS
The dynamic input symbol, the postponed output symbol, and dependency notation provide
the tools to differentiate four main types of bistable elements and make synchronous and
asynchronous inputs easily recognizable (Figure 25). The first column shows the essential
distinguishing features; the other columns show examples.
Transparent latches have a level-operated control input. The D input is active as long as the
C input is at its internal 1 state. The outputs respond immediately. Edge-triggered elements
accept data from D, J, K, R, or S inputs on the active transition of C. Pulse-triggered elements
6-23
require the setup of data before the start of the control pulse; the C input is considered static
since the data must be maintained as long as C is at its 1 state. The output is postponed until
C returns to its 0 state. The data-lock-out element is similar to the pulse-triggered version except
that the C input is considered dynamic in that shortly after C goes through its active transition,
the data inputs are disabled and data does not have to be held. However, the output is still
postponed until the C input returns to its initial external level.
Notice that synchronous inputs can be readily recognized by their dependency labels (10, 1J,
1 K, 15, 1 R) compared to the asynchronous inputs (5, R), which are not dependent on the C
inputs.
r---,
m
l
X
-C
r,l>
I
I
Cm
I
r-I
L __ ...J
TRANSPARENT
LATCHES
:2
l>
ti
D
C1
C2
20
1/2 SN74HC75
r---'
::!
ten ~
o
:2
o"T1
EDGE·TRIGGERED
r-
r---,
Cl
1K
R
I ___ .JI
L
oG)
I
lCm
n
1/2 SN74HC74
I
<'
PULSE·TRIGGERED
S
1/2 SN74HC107
1J
~r--
C1
1K
R
IL ___ JI
en
fl
u
SN74L71
1/2 SN74107
r---,
aJ
+cm'~
or-
en
IL ___ JI '
DATA·LOCK·OUT
1/2SN74111
Figure 25. Four Types of Bistable Circuits
6.0
CODERS
The general symbol for a coder or code
converter is shown in Figure 26. X and Y
may be replaced by appropriate
indications of the code used to represent
the information at the inputs and at the
outputs, respectively.
6-24
Figure 26. Coder General Symbol
Indication of code conversion is based on the following rule:
Depending on the input code, the internal logic states of the inputs determine an internal
value. This value is reproduced by the internal logic states of the outputs, depending on
the output code.
The indication of the relationships between the internal logic states of the inputs and the internal
value is accomplished by:
1)
2)
labeling the inputs with numbers. In this case the internal value equals the sum of
the weights associated with those inputs that stand at their internal 1-state, or by
replacing X by an appropriate indication of the input code and labeling the inputs with
characters that refer to this code.
The relationships between the internal value and the internal logic states of the outputs
are indicated by:
1)
2)
labeling each output with a list of numbers representing those internal values that
lead to the internal 1-state of that output. These numbers shall be separated by solidi
as in Figure 27. This labeling may also be applied when Y is replaced by a letter
denoting a type of dependency (see Section 7). If a continuous range of internal values
produces the internal 1 state of an output, this can be indicated by two numbers
that are inclusively the beginning and the end of the range, with these two numbers
separated by three dots (e.g., 4 ... 9 = 4/5/6/7/8/9) or by
replacing Y by an appropriate indiction of the output code and labeling the outputs
with characters that refer to this code as in Figure 28.
Alternatively, the general symbol may be used together with an appropriate reference to a table
in which the relationship between the inputs and outputs is indicated. This is a recommended
way to symbolize a PROM after it has been· programmed.
FUNCTION TABLE
x/v
1
2
4
1/4
2/3
3/4
7
INPUTS
c
b a
0
0 0
0
0 1
0
1 a
0
1 1
1
0 a
a 1
1
1 a
1
1
1 1
OUTPUTS
f
e d
9
0 0 0
0
a a a 1
a 0 1 0
a 1 1 0
a 1 0 1
a 0 0 a
a a 0 0
1 a a 0
CJ)
...J
or:o
~
>
CJ)
(J
C!J
o
...J
U.
o
2
o
i=
«
2
«
...J
a..
><
w
II
Figure 27. An XIV Code Converter
6-25
FUNCTION TABLE
INPUTS
c
b a
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0
1
1 1 0
1 1 1
X/OCT
1
2
2
4
m
3
4
9
h
j
0
0
0
0
0
0
0
1
i
0
0
0
0
0
0
1
0
OUTPUTS
f
h
9
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
e
0
0
d
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
Figure 28. An X/Octal Code Converter
><
""0
rl>
7.0
2:
USE OF A CODER TO PRODUCE AFFECTING INPUTS
It often occurs that a set of affecting
inputs for dependency notation is
produced by decoding the signals on
certain inputs to an element. In such a
case use can be made of the symbol for
a coder as an embedded symbol
(Figure 29).
l>
~
(5
2:
o
..,
r-
oG)
If all affecting inputs produced by a coder
are of the same type and their identifying
numbers shown at the outputs of the
coder, Y (in the qualifying symbol X/Y)
may be replaced by the letter denoting the
type of dependency. The indications of
the affecting inputs should then be
omitted (Figure 30).
n
tJ)
-<
s:
D:J
o
r-
XIV
o
G1
1 G2
2
2 V4
2/3
N5
C3
Figure 29. Producing Various Types of
Dependencies
=[J
X/MO
2
1
2
I
=D
IY
--
=
1
2
--
0 MO
1
M1
2
M2
I
I
I
tJ)
Figure 30. Producing One Type
of Dependency
8.0
USE OF BINARY GROUPING TO PRODUCE AFFECTING INPUTS
If all affecting inputs produced by a coder are of the same type and have consecutive identifying
numbers not necessarily corresponding with the numbers that would have been shown at the
outputs of the coder, use can be made of the binary grouping symbol. k external lines effectively
generate 2k internal inputs. The bracket is followed by the letter denoting the type of
dependency followed by m 11m2. The m 1 is to be replaced by the smallest identifying number
and the m2 by the largest one, as shown in Figure 31.
6-26
x/v
=f:}~~-
4
I
I
=f}~~
D
1
2
J
4
5
6
7
AD
Al
A2
AJ
A4
A5
A6
A7
D
1
2
J
G5
G6
G7
G8
X/V
I
'en
...I
om
I
~
>
en
Figure 31. Use of the Binary Grouping Symbol
(J
9.0
~
SEQUENCE OF INPUT LABELS
If an input having a single functional effect is affected by other inputs, the qualifying symbol
(if there is any) for that functional effect is preceded by the labels corresponding to the affecting
inputs. The left-to-right order of these preceding labels is the order in which the effects or
modifications must be applied. The affected input has no functional effect on the element if
the logic state of anyone of the affecting inputs, considered separately, would cause the affected
input to have no effect, regardless of the logic states of other affecting inputs.
o
...I
LL
o
2:
o
i=
«
«
If an input has several different functional effects or has several different sets of affecting inputs,
2:
depending on the mode of action, the input may be shown as often as required. However,
...I
there are cases in which this method of presentation is not advantageous. In those cases the
0..
input may be shown once with the different sets of labels separated by solidi (Figure 32). No
meaning is attached to the order of these sets of labels. If one of the functional effects of
W
an input is that of an unlabeled input to the element, a solidus will precede the first set of labels _ _
><
l11li
shown.
If all inputs of a combinational element are
disabled (caused to have no effect on the
function of the element), the internal logic
states of the outputs of the element are
not specified by the symbol. If all inputs
of a sequential element are disabled, the
content of this element is not changed and
the outputs remain at their existing
internal logic states.
Labels may be factored using algebraic
techniques (Figure 33).
---1
a
G2
b
21~~ __
Figure 32. Input Labels
6-27
Figure 33. Factoring Input Labels
m
10.0
><
"'C
r-
l>
SEQUENCE OF OUTPUT LABELS
If an output has a number of different labels, regardless of whether they are identifying numbers
of affecting inputs or outputs or not, these labels are shown in the following order:
:2
1)
::!
2)
l>
o
:2
o
."
3)
If the postponed output symbol has to be shown, this comes first, if necessary
preceded by the indications of the inputs to which it must be applied
Followed by the labels indicating modifications of the internal logic state of the output,
such that the left-to-right order of these labels corresponds with the order in which
their effects must be applied
Followed by the label indicating the effect of the output on inputs and other outputs
of the element .
.r-
oG)
n
C/)
-<
S
Dl
o
r-
C/)
11
Symbols for open-circuit or three-state
outputs, where applicable, are placed just
inside the outside boundary of the symbol
adjacent to the output line (Figure 34).
If an output needs several different sets
of labels that represent alternative
Figure 34. Placement of 3·State Symbols
functions (e.g., depending on the mode
of action), these sets may be shown on
different output lines that must be
connected outside the outline. However, there are cases in which this method of presentation
is not advantageous. In those cases the output may be shown once with the different sets
of labels separated by solidi (Figure 35).
Two adjacent identifying numbers of affecting inputs in a set of labels that are not already
separated by a nonnumeric character should be separated by a comma.
If a set of labels of an output not
containing a solidus contains the
identifying number of an affecting Mm
input standing at its internal 0 state, this
set of labels has no effect on that output.
Labels may be factored using algebraic
techniques (Figure 36).
6-28
ai;'--fc;:~ b
1CT=15
-------
af~-~~;=;n~;=~t. b =
-
---------
b
at.'-------lc;::t
1CT=15
Figure 35. Output Labels
Figure 36. Factoring Output Labels
If you have questions on this Explanation of Logic Symbols, please contact:
Texas Instruments Incorporated
F.A. Mann, MS 49
P.O. Box 225012
Dallas, Texas 75265
Telephone (214) 995-2867
IEEE Standards may be purchased from:
Institute of Electrical and Electronics Engineers, Inc.
IEEE Standards Office
.
345 East 47th Street
New York, N.Y. 10017
International Electrotechnical Commission (lEC) publications may be purchased from:
American National Standards Institute, Inc.
1430 Broadway
New York, N.Y. 10018
en
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oal
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en
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o
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U.
o
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o
i=
c:(
z
c:(
...I
a.
X
w
6-29
m
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rl>
2
l>
-I
6
2
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6-30
GENERAL INFORMATION
RATINGS AND CHARACTERISTICS
HCMOS DEVICES
HCMOS DEVICES - ADVANCE INFORMATION
HCMOS DEVICES -
I
PRODUCT PREVIEWS
EXPLANATION OF LOGIC SYMBOLS
DESIGNERS' INFORMATION
MECHANICAL DATA
7-1
C
m
tn
c;
Z
m
:g
tn.
-z
o":g
s:
»
::!
o
z
I
7-2
DESIGNERS' INFORMATION
CMOS Circuitry
The elementary CMOS building blocks are the inverter and the transmission gate. Each uses a complementary pair of
one n-channel and one p-channel enhancement-type field-effect transistor. Figures 1 and 2 show these together with various
logic symbols t used in this book to represent them.
Vee
d
o
~J
~
Figure 1. Inverters
N
-L
2:
o
-(~)I
i=
c:t
:!
a:
oLL
2:
p
Figure 2. Transmission Gates
Logic gates are created by transistors added in parallel or series to the transistors making up the elementary inverter.
Thus the simplest gates are inverting. See Figure 3. An odd number of additional inverters are sometimes added to the outputs
of gates to make themnoninverting. Basic CMOS gates usually have no more than three inputs. Arrays of gates are used
when moore than three signals are ANDed or ORed.
The Exclusive-OR or Exclusive-NOR gate is most easily implemented using two inverters and two transmission gates
as shown in Figure 4. In complex chains of gates, the inverters may be made unnecessary by complementary signals being
already available.
.
en
a:
w
2:
"Ciiw
C
II
t The various logic symbols are equivalent. The distinctive-shape form of the inverter and gate symbols and the "TO" form of the transmission gate are
usually used in the device logic diagrams. The logic inversion symbol (0) is shown at the input or the output. whichever maintains logical consistency
with the driving output or the driven input. and this technique is used to indicate the true/complement levels of the signal as it progresses through the
circuit. For example. see Figure 7 in this section. The rectangular forms of the inverter and gate symbols and the polarity indicator (~) replacing the
inversion symbol are usually used in this book only in the device logic symbols. The C> indicates a high-current output.
7-3
C
m
rn
C5
:2
m
l:l
rn.
:2
"T1
o
l:l
~
l>
::!
o:2
A~----------~--~
:=Q-v
B ...- - - - - I - - I
v
POSITIVE LOGIC: V = AS + A B or A0 B
Figure 4. Exclusive-OR/NOR Gates
7-4
The three-state output buffer has logic elements in the gate connections to each of the transistors in the final inverter
so that both may be turned off under the control of an enable function. Figure 5 illustrates an inverting output buffer.
The transparent latch is typically implemented as shown in Figure 6. This is the simplest form. Logic diagrams in this
book show that additional inverters may be added as buffers or to optimize timing. The true and complementary outputs
(Q and Q) may be taken off at other points. Outputs brought out to terminals are always buffered to minimize any feedback
effects. The one exception to this is the 'HCU device, which has unbuffered outputs.
Putting two transparent latches in series produces thl! edge-triggered D-type flip-flop. The inverters can be converted
to two-input gates to provide asynchronous set and reset functions. Figure 7 illustrates a negative-edge-triggered circuit.
Exchanging the connections of C and C produces a positive-edge-triggered version.
C>
EN
y
Figure 5. Inverting Three-State Output Buffer with Active-Low Enable
C
o
.x>-..--a
I-__- - Q
D-n-a
a
2!
c-U-
0
i=
~
~
a::
C
0
Figure 6. Transparent Latches
LL
2!
.CJ)
a::
w
2!
Q
S
Q
W
ClK
R
a
C)
CJ)
0
a
C
II
Figure 7. Negative-Edge-Triggered D-Type Flip-Flops
7-5
Detailed logic diagrams for flip-flops are given on the data sheets in this book when useful to illustrate special features
such as synchronous clearing, 11K inputs, and toggle enabling.
In general the logic diagrams in this book have been simplified. They are believed to correctly indicate the logic
implementation but should not be used to predict dynamic performance. Inverters existing in series may be combined or
eliminated in the diagram as shown in Figure 8.
-l>-
OR
.-{)O-
OR
---
::!
o
2:
II
METAL
GATE
GATE
CMOS
CMOS
SN74HC
4000
0.0000025
0.001
0.17
0.1
8
105
40
1.4
STD
TTL
SN74
LOW-POWER
SCHOTTKY
TTL
ADVANCED
SCHOTTKY
LOW-POWER
TTL
SCHOTTKY
TTL
ADVANCED
SCHOTTKY
TTL
SN74LS
SN74AS
SN74ALS
SN74AS
10
2
19
1
8.5
10
2
19
1
8.5
10
10
3
4
1.5
12
35
40
125
70
200
11
100
20
57
4
13
16
. 48
8
20
24
64
8
24/48
20
48/64
Power dissipation per gate (mW)
G)
(J)
SILICON-
=
15 pF)
=
15 pF)
Speed/Power product (pJ) (at 100 kHz)
=
0.4 V)
Standard outputs
4
1.6
High-current outputs
6
1.6
Standard outputs
10
4
40
20
50
20
50
High-current outputs
15
4
120
60
160
60/120
120/160
±0.001
-0.001
-1.6
-0.4
-2.0
-0.1
-0.5
Fan-out (LS loads)
Maximum input current, IlL (rnA) (VI = 0.4 V)
:I: Family characteristics at 25°e, Vee = 5 V; all values typical unless otherwise noted. This table is provided for broad comparisons only.
Parameters for specific devices within a family may vary. For detailed comparisons, please consult the appropriate data book.
The major advantages of high-speed CMOS can be summarized as follows:
1. The high-speed CMOS family can operate at speeds comparable to LSTTL. The high-speed CMOS family has ac
parameters guaranteed at a supply voltage of 2 V, 4.5 V, and 6 V over the full operating temperature range into
a 50-pF load (also, 150 pF for high-current outputs). Note that at the higher operating frequencies, the power
consumption is also comparable to LSTTL (Figure 9).
2. Figure 9 also shows that the high-speed CMOS family covers a wide range of applications: low power drain for
low-speed systems, and a slightly higher drain for higher speed systems.
7-6
3. Minimum system power - only the gates that are switching contribute to system power consumption. This reduces
the size of the power supply required, hence provides lower system cost and improved reliability through lower
heat dissipation.
As mentioned previously, the power consumption for an individual gate at the maximum speed is comparable to
LSTTL. However in typical systems, only a fraction of the gates are switching at the clock frequency; therefore,
significant power savings can be realized. On a system level where the individual gate switching frequencies are
distributed between zero and the system clock frequency (Figure 10), the power saved with high-speed CMOS can
be quite significant, as illustrated in Figure 11. The total system power is the area under each curve. The graph
in Figure 11 is obtained by multiplying the individual gate characteristics (Figure 9) by the frequency distribution
in Figure 10.
4. High-speed CMOS is ideal for battery-operated systems, or systems requiring battery back-up, because there is virtually
no static power dissipation (Figure 9).
a:1----....-;;;;;..--------~
w
~
Co
FREQUENCY
Figure 9. Power Consumed Versus Frequency for High-Speed CMOS Compared to LSTTL
z
o
i=
«
~
a:
ou.
Z
..(/)
a:
w
z
(!)
Cii
w
FREQUENCY
~
Figure 10. Typical Distribution of Switching Frequencies for Gates
within a System with Maximum Clock Frequency, fs
5. Improved noise immunity over bipolar devices is due to the rail-to-rail (Vce to ground) output voltage swings.
Figure 12 illustrates the noise immunity provided by the high-speed CMOS family as it compares to the LSTTL
family. This noise immunity makes it ideal for high-noise environments. Minimum and maximum output voltages
are guaranteed at 4 rnA (6 rnA for high-current devices). If the output currents exceed these limits, the noise immunity
will be impaired. 'HCT devices have similar input noise margins to LSTTL because their inputs are TTL-voltage
compatible. The outputs of 'HCT are the same as standard 'HC outputs.
C
II
7-7
6. High-speed CMOS devices can drive up to 10 LSTTL loads (15 LSTTL loads for high-current outputs) while
maintaining good noise immunity. Although VOHmin and VOLmax are guaranteed for output currents up to 4 rnA
(6 rnA for high-current outputs), currents up to ±25 rnA (±35 rnA for high-current outputs) can be obtained to
drive LEDs or relays (see Driving LEDs and Relays in this section.)
a:
OW
I-~
z~
Q:;
I-w
::JIalln
->
a: In
1-...1
Zet
01-
Uo
I-
FREaUENCY~
Figure 11. Contribution to Total Power by Gates Running at Frequencies from 0 to fs
6
VOH=VCC-O.1 V
5
VNHIHC) = 0.29 VCC
4
VIH =0.7 VCC
I
l-
::J
a..w
I-CJ
::Jet
C
01...... ...1
1-0
en
~
m
1
i2>
G')
:2
m
r
::J3
en..
VOH =2.7 V
:2
VNHILS) = 0.14 VCC
o
VIH=2V
"TI
::J3
+
"
-2
3:
:t>
:::!
o
:2
II
7-8
Vil = 0.2 VCC
t
VIL = 0.8 V
VNLIHC) = 0.19 VCC
VNLILS) = 0.08 VCC:
~
VOL =0.4V
VOL =0.1 V
VCC = 5 V ±10%
- - -•• POWER SUPPLY VOLTAGE
Figure 12. High-Speed CMOS and LS Noise Margins
7. High-speed CMOS devices are guaranteed over an extended temperature range:
SN54HC/HCT'
SN74HC/HCT'
-55°C to 125°C
-40°C to 85°C
(military)
(industrial)
All specified ac and dc characteristics are guaranteed over this range with the exception of Power Dissipation
Capacitance (Cpd) , which is specified as a typical value at 25°C.
Protection Circuitry
Electrostatic discharge (ESD) and latch-up are two traditional causes of CMOS device failure. In order to protect HCMOS
devices from ESD and latch-up, additional circuitry has been implemented on the inputs and outputs.
ESD PROTECTION
ESD occurs when a buildup of static charges on one surface arcs through a dielectric to another surface that has the
opposite charge. The end effect is the ESD causes a short between the two surfaces. These damaged devices (walking-wounded)
may still pass normal data sheet tests, but will eventually fail. The unique input protection circuitry designed by Texas Instruments
provides immunity to typically 4500 V on the inputs and 3000 V on the outputs, which exceeds
MIL-STD-883B, Method 3015, requirements for ESD protection (2000 V, 1.5 kO, 100 pF).
Figure 13 shows the circuitry implemented to provide protection for the input gates against ESD. The diode is forward
biased for input voltages greater than Vcc + 0.5 V. The two transistors and resistor (actually one transistor diffused across
a resistor) act as a resistor-diode network against negative-going transients. As illustrated in Figure 14, the ESD protection
for the output consists of an additional diffused diode (03) from the output to Vce. The other diodes (D1 and D2) are parasitics.
For further information on handling CMOS devices, see Guidelines for Handling ESDS Devices and Assemblies in this section.
r-----------~--------------~-----vcc
INPUT PIN 0----41.....- - - - - - - - - -....- - - - . " " " ' - - - -...- - - - . TO GATES
Figure 13. ESD Input Protection Circuitry
z
o
i=
::!
Figure 16. Schematic of Parasitic SCR - P Gate and N Gate Electrodes are Connected Together
o
2:
A conventional thyristor is fired (turned on) by applying a voltage to the base of the n-p-n transistor, but the parasitic
CMOS thyristor is fired by applying a voltage to the emitter of either transistor. One emitter of the p-n-p transistor is connected
to an emitter of the n-p-n transistor, which is also the output of the CMOS gate. The other two emitters of the p-n-p and
n-p-n transistors are connected to Vee and ground, respectively. Therefore, to trigger the thyristor there must be a voltage
greater than Vee + 0.5 V or less than -0.5 V and there has to be sufficient current to cause the latch-up condition.
Latch-up cannot be completely eliminated! The alternative is to impede the thyristor from triggering. Texas Instruments
has improved the circuit design by adding four additional diffusions or guard rings alternately connected to Vee and ground
as shown in Figure 17. The guard rings provide isolation between the device pins and any p-n junction that is not isolated
by a transistor gate. All internal p-njunctions are separated by two guard rings. Tests have shown effective latch-up protection
ranges from 450 rnA to greater than 1 A at 25°C, and typically greater than 250 rnA at 125°C.
7-10
FOUR-GUARD-RING ISOLATION
GATE
DRAIN
SOURCE
(OUTPUT).-l.- (VCC)
GATE
I
VCC
GND
VCC
GND
DRAIN
(GND)
I SOURCE
-L (OUTPUT)
PWELL
N SUBSTRATE
Figure 17, Unique Latch-Up Suppression Utilizes Guard Rings to Virtually Eliminate Latch-Up
Fan-Out and Capacitance Loading Effects
High-Speed CMOS is capable of driving up to 10 LSTTL loads from a single standard output, or 15 loads from a highcurrent output. From the dc values in Table Ion page 2-4, the fan-out of high-speed CMOS devices is unlimited for all practical
purposes_ However, from an ac point of view, there is a definite limit to the fan-out. The limiting constraint is the input rise time.
With a worst-case model, about 15 pF of capacitance is associated with the input of a high-speed CMOS device (10 pF
from the device itself plus 5 pF of stray capacitance; typically the input capacitance is 3 pF for all devices except the transceivers,
whiCh are 6 pF). The input resistance, fI, can be approximated with the following equation using the information in Table
I on page 2-4.
where
VI= Vee = 6 V
11= 0.1 nA
:2
The output resistance can also be calculated from the values in Table I, page 2-4 and the following equation:
ro = (Vcc
-
VOH)/IOH
where
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0.7
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0.6
G)
l-
0.5
2
0
0
0.4
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0.2
2
'T1
0.1
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2
II
/
V
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/
1.5
/
3.0
V
4.5
6.0
7.5
9.0
Distance From Package-Inches
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/'
0.3
rJ)
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L
Figure 21. VCC Transients vs Decoupling Capacitor Distance from DIP
The results indicate the importance of adequate decoupling, and illustrate the correct procedure for obtaining it. This
procedure consists of locating decoupling capacitors as close as possible to the integrated circuit package, in order to maximize
noise margins.
Connecting Unused Inputs
Unused inputs should be tied to Vee or ground to prevent the input from floating. If left to float, the power consumption
of the device will increase.
7-14
Matching
Another factor to consider when designing with high-speed CMOS is the VOHmin-to-VI matching. This is important
when the VOHmin of the driving device exceeds the Vee + 0.5 V of the driven device. If this occurs, the ESD protection
diode on the inputs will be forward biased. At this point, the driving device will attempt to "power-up" the driven device's
power supply. No damage will occur to the driven device, provided the current flowing through the diode does not exceed
20mA.
Powering Up/Down Sequence for High-Speed CMOS
To avoid any possible damage and reliability problems to the high-speed CMOS devices when applying power, the following
steps should be followed:
1. Connect ground
2. Connect Vee
3. Connect the input signal
When powering down a high-speed CMOS device, follow the above steps in reverse order.
High-Speed CMOS Interfacing
INTRODUCTION
The High-Speed CMOS logic family from Texas Instruments contains a broad spectrum of SSI/MSI functions. Within
this family are TTL functions, HCT devices, HC4000 series, and an HCU device. l Entire CMOS systems may be implemented
using this logic family. There is also a broad range of CMOS-system to non-CMOS-system interfaces that need to be considered.
The design engineer will inevitably encounter these interfaces. To develop the necessary interfaces, a thorough understanding
of data sheet parameters of both systems and an organized approach is recommended. This report uses basic examples to
present one possible approach to the SN54174HC interface solution.
There are two types of interfacing that must be considered: (1) interfacing CMOS system signals to non-CMOS systems
and (2) interfacing non-CMOS system signals to CMOS systems. The first type requires an understanding of the CMOS
output parameters and the non-CMOS input parameters and vice versa for the second type. In both cases, a model of the
inputs and outputs of both systems may be useful.
.
GENERAL INTERFACING SOLUTION
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An interfacing problem arises when the output logic levels and/or the current requirements of the driving system (or
device) are different from the input logic levels and/or the current requirements of the driven system (or device). When
determining the compatibility of the systems (or devices), the most important system/device parameters are VIH,VIL, VOH,
VOL, IIH, IlL, IOH, and VOL·
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Figure 22 is the voltage transfer characteristic of a typical unloaded inverter showing the various input and output voltage
parameters. Loading the output of the inverter will tend to lower VOH and raise VOL. The tables of electrical characteristics
specify minimum VOH and maximum VOL for various loads.
Noise Margin
There are two noise margins to be considered: the low-voltage noise margin and the high-voltage noise margin. The
voltage difference between VILmax of the driven system/device and VOLmax of the driving system/device is the low-voltage
noise margin. The voltage difference between VOHmin of the driving system/device and VIHmin of the driven system/device
is the high-voltage noise margin (Figure 23).
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II
1 HCT devices are explained later. The HC4000 series devices are pin-far-pin functionally compatible, but not electrically compatible, with the older metalgate CMOS devices. The HCU device is unbuffered.
7-15
It is desirable to have the noise margin as large as possible and the uncertain region (the difference between VIHmin and
VILmax) as small as possible. When an input voltage falls into the uncertain region, we do not know how the output in conjuction
with other inputs driven by that output will respond. The problem with small noise margins is that any noise on the output
of the driving system or device will cause the signal to fall into the uncertain region and possibly cause a bit error in the
system. There are various sources of noise in digital systems. Three possible internal sources are inductive and resistive
drops, capacitive coupling from another logic node, and mutual inductance with another logic node. Radio signals are possible
external sources of noise.
Vo
---+I
I
I
I
I
I
I
I
_L __
~
C
______ ____________L--'.
~
VI
Figure 22. Voltage Transfer Characteristic of a Typical Inverter
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Vo DRIVING DEVICE
VI DRIVEN DEVICE
2
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Figure 23. Noise Margins
As an aid for interfacing between the various TTL families, the eight parameters previously defined are shown in Table 3.
The values are for Vee = 5 V and TA = 25 °C (worst-case device parameters - the device will perform at least this well).
All currents are designated positive when flowing into. the device.
7-16
Table 3. Worst-Case Values of Primary Interfacing Parameters
PARAMETER
74HCMOS
3.5 V
74TTL
2V
VILrnax
VOHrnin
1V
4.9 V
0.8 V
2.4 V
VOLrnax
0.1 V
0.4 V
0.4 V
0.4 V
0.4 V
40 JlA
-1.6 rnA
20 JlA
-400 JlA
200 JlA
-2 rnA
20 JlA
-100 JlA
IOHrnax
1 JlA
-1 JlA
-4 rnA
-2 rnA
4 rnA
-400 JlA
16 rnA
-400 JlA
IOLrnax
8 rnA
20 rnA
-400 JlA
4 rnA
IIHrnax
IILrnax
74LSTTL
74ASTTL
VIHrnin
74ALSTTL
2V
2V
2V
0.8 V
2.7 V
0.8 V
2.7 V
0.8 V
2.7 V
Driving Gate Output Model
Figure 24 shows the model of a driving gate derived from the data sheet specifications. VOH(nl) (nl = no load) is the
high-level output voltage expected when the output gate is unloaded. VOL(nl) is the low-level output voltage expected when
the output gate is unloaded. The values for these two voltages are usually not given on the data sheets. As a rule of thumb
for MOS devices, the output switches between the power rails VOH(nl) = Vee and VOL(nl) = GND; for bipolar devices
(e.g., the TTL Family) VOL(nl) is about Vedsat) or about 0.3 V. Within the TTL family VOH(nl) varies. Standard TTL
has a VOH(nl) within two base-emitter drops of VedVOH(nl) = Vee - 1.2 V); LSTTL has a VOH(nl) within one baseemitter drop of VedVOH(nl) = Vee -0.6 V). The data sheets specify VOHmax and VOLmax at a nonzero IOH and IOL,
respectively. Therefore to calculate the approximate series resistances, the following two equations may be used:
ROH
ROL
1VOH(nl) - VOHminl
IOH
1VOL(nl) - VOLmaxl
IOL
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The output logic level of CMOS devices are completely compatible with the input logic levels of ALSTTL devices. The
_ _ interface structure with ALSTTL is shown in Figure 30. As with the other CMOS-to-TTL interfaces, there is no pull-up
resistor required. The fan-out of ALSTTL devices is determined by the amount of current that flows through Q3 into the
7-20
CMOS device, and the amount of current the CMOS device can sink. When the input of the ALSTTL device is low, there
is 0.1 rnA flowing though Q2. The maximum current that the CMOS device can sink (according to the parameters) is 4 rnA.
This corresponds to a ALSTTL fan-out of 40.
vcc----------------,
R1
.-------~----vcc
Rp
04
Figure 29. LSTTL to SN54l74HC Interface with a Pull-Up Resistor
.-----~
vcc~
R1
. n :!J
__----vcc
R2
01
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of ASTTL and the current sinking capability of CMOS (IOL). IlL for the ASTTL is 2 rnA,
and the current sink limit of CMOS is 4 rnA. Therefore, the fan-out is two ASTTL devices.
vcc~
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Figure 32. SNS4174HC to ASTTL Interface
ASTTL-to-CMOS INTERFACE
Not all the ouput logic levels of ASTTL are compatible with the input logic levels of CMOS. Table 3 shows there is
incompatibility between the VOH of ASTTL and VIH of CMOS. As with other TTL-to-CMOS interfaces, a pull-up resistor
is required (Figure 33). The appropriate value of the pull-up resistor is determined by the same procedure previously explained.
7-22
vcc----------------,
r-------~~---------vcc
Rp
R1
Figure 33. ASTTL to SN54/74HC Interface with a Pull-Up Resistor
CMOS-to-NMOS INTERFACE
NMOS is used extensively in large-scale-integration products such as microprocessors, microcomputers, and memories.
The logic levels of NMOS are usually TTL-compatible. CMOS devices can drive NMOS devices with no pull-up resistors.
The input impedance of NMOS is very high, which is similar to the input impedance of CMOS.
NMOS-to-CMOS INTERFACE
A pull-up resistor may be necessary when an NMOS device drives a CMOS device. The method of determining the
value range of the pull-up resistor is the same as the method described previously for TTL. A quick look afNMOS output .
parameters and CMOS input parameters will determine if a pull-up resistor will be required.
USING HCT DEVICES TO INTERFACE TO CMOS FROM TTL
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.....- - OUTPUT
>-~
__- - OUTPUT
R: 2.7 kn to 2.7Mn
50 pF to 10 J'F
c:
Figure 34. Simple RC Oscillator
Using Two 'HC04 Gates
Figure 35. Oscillator Circuit
Using a Crystal to Set the Period
VOLTAGE-CONTROLLED OSCILLATORS
Voltage-controlled oscillators (VCOs) can also be designed using a minimal number of components. Figure 36 shows a
VCO using NAND and inverter gates. This VCO design exploits the phenomena of the slight variations in the propagation
delay of an 'HC gate with changes in the supply voltage. The 'HCOO is connected as a three-stage ring oscillator with a
buffer. As the control (supply) voltage Vc is varied, the ring oscillator's frequency changes according to the following:
fout :::::; 5.8 x Vc
Vc
r---------
~;;::)----lO.O~'F
.100kn
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(8)
I
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-= (7)
::xJ
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L_______ ~------_J
C;
"T1
OUTPUT
12
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(11)
Figure 36. Voltage-Controlled Oscillator· (VCO)
The inverter, which is powered by a separate voltage source, serves to restore the oscillator output voltage to 5 V peak-topeak. This function is required, because the 'HCOO switches from rail-to-rail (as do all HC devices). The magnitude of the
oscillator output voltage is thus dependent on VC. The lOO-kD. resistor across the inverter provides bias such that operation
will be within the linear operating region of the gate. The capacitor serves to ac-couple the oscillator to the inverter.
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7-24
The VCO output is linear for control voltages in the range of 1.5 to 4.5 V (Figure 37).
To prevent oscillator •'bleed-through" onto the VCC line, adequate decoupling of the 'HC device power supply is required.
~
30
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~
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20
g-
~
;
a::l
10
0
L::l
_0
0
0
2
3
4
5
VC-Control Voltage-V
Figure 37. VCO Output Frequency vs Input Voltage
Drivers for LEDs and Relays
INTRODUCTION
SN54174HC devices are capable of sinking or sourcing up to 25 rnA (35 rnA for high-current devices) per gate. As the
device sinks or sources more current, VOHmin or VOLmax levels will begin to fall or rise respectively.
Because of these characteristics, SN54174HC devices can be used to drive LEDs and relays.
DRIVING LEDs
Figure 38 shows an 'HC04 driving a TIL221 gallium phosphide light-emitting diode. The resistor performs the function
of current limiter. The luminous intensity of the LED depends on the amount of forward current.
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VIL AT THE INPUT TURNS ON THE LED
.
en
VIH AT THE INPUT TURNS ON THE LED
a:
Figure 38. 'HC04 Driving a LED
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Example: Using 10 rnA forward current and 2.2 V forward voltage, the value of the current-limiting resistor can
be calculated using the following equations:
[for Figure 38(a)] R
[for Figure 38(b)] R
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VOH - 2.2 V
lOrnA
II
VCC - 2.2 V - VOL
10 rnA
It should be noted that as used here, VOH and VOL are not the VOHmin and VOLmax specified in the data book. Figures 39
and 40 show typical values for VOH and VOL for an 'HCOO.
7-25
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So
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3
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So
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-10
-20
4 -VI=VIH
TA" 25°C
1/
-30
3
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~
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1
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VCC=5V
"0
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VI=VIL
TA=25°C_
1\
2
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5
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VCC =5 V
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2
0
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0
>
\
-40
o
-50
/
/
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10
IOH-High-Level Output Current-mA
//
20
30
40
50
IOL-Low-Level Output Current-mA
Figure 40. Typical Values for VOL
Figure 39. Typical Values for VOH
DRIVING RELAYS
Multiple gates can be connected in parallel to increase the current sinking or sourcing capability of SN54174HC devices.
Figure 41 shows two 'HC04 gates connected in parallel for relay driver application.
Precautions should be taken to prevent one gate from "hogging" the current. Small resistors (typically 50 0) in series
with the output gate will limit the possibility of "current hogging" by anyone gate.
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In all applications in which the SN54174HC output is required to source or sink substantial current (6 rnA to 25 rnA),
particular attention should be paid to providing adequate power supply decoupling for the driving device.
G)
2
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en.
50n
:J:J
~~~~--
__
-e~~
------0
A...--....o
2
50n
"T1
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Figure 41. SN54/74HC04 Gates Connected in Parallel to Drive a Relay
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SN54HC/SN74HC Interchangeability Guide
2
INTRODUCTION
The following has been prepared as a guide to interchanging devices from other logic families, both bipolar and CMOS,
with those from the SN54HC/SN74HC family. This is not intended to b.e a comprehensive guide since interchangeability
can depend on many factors, and only careful data sheet comparisons can provide definitive answers. The considerations
listed below are based upon information accumulated in answering a large number of inquiries in this area.
First, a brief review is given on each logic technology, and second, discussion is given on the various aspects involved
in attempting to interchange that technology with the SN54HC/SN74HC family.
7-26
TTL: Transistor-Transistor Logic
TTL is the generic name for several bipolar families that have evolved over the past 20 years. Low-Power Schottky
(LSTTL) is the most widely used bipolar logic family today. Other families, e.g., Schottky (STTL), Advanced Schottky
(ASTTL or AS), and Advanced Low-Power Schottky (ALSTTL or ALS) are also used, depending on the speed versus power
performance required by a given system design.
4000 Series: Metal-Gate CMOS Logic
The device type numbers in this series have a variety of prefixes, although "CD" is probably the most widely recognized.
The suffix "B" is frequently used, indicating an improvement over the original family, i.e., buffered outputs and typical
output sink and source current capabilities of ± 1 rnA. This logic family became popular because it offered very low power
consumption, even though it is slower than TTL with a typical operating frequency of about 5 MHz, has a low level of ESD
protection, and is latch-up prone.
4OHOO Series: Metal-Gate CMOS
~c
This series was designed to overcome the speed limitations of the original 4000 family. Even though these devices are
somewhat faster, they are still slow when compared to LSTTL.
74COO Series: Metal-Gate CMOS Logic
The distinguishing feature of this family is that the pinouts correspond to those of TTL, making interchangeability easier.
The devices, however, exhibit many of the same speed/power limitations as those of the 4000 series. The fan-out is typically
higher than the 4000 series, however, with typical output sink and source capabilities of ± 1.75 rnA.
74SCOO Series: Silicon-Gate CMOS Logic
This series was the forerunner to the SN54HC/SN74HC family, or more closely, to the SN54HCT/SN74HCT family.
The 74SC family was designed to overcome many of the 4000 series deficiencies, particularly the slower speed and the lower
drive capability.
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Higher frequency of operation
Improved ESD protection and latch-up performance
Higher output drive capability
Multiple-sourced family.
As a quick reference guide, Table 4 shows highlights of interchanging other logic families with high-speed CMOS.
CONCLUSION
-I
II
Within the constraints given above, the SN54HC/SN74HC family can be regarded as pin-for-pin equivalents to the other
logic families. The rapidly-expanding SN54HC/SN74HC family is ideally suited for system upgrading, system shrinking,
or espedally. new system design.
7-28
Table 4. Highlights of Interchangeability
TTL FAMILY (TTL. LSTTL. STTL. ALS. AS)
Power
Speed
METAL-GATE CMOS
HCMOS offers lower system power consumption
Power consumption of HCMOS is less than metal-gate
than any of the TTL families.
CMOS.
HCMOS operating speed is comparable to LSTTL.
HCMOS operating speed is much faster than metal-gate
Some TTL families (STTL. AS. and ALS) offer
CMOS.
greater operating speed.
Input
The VIHmin of HCMOS is not compatible with the
HCMOS input voltage levels are compatible with metal-gate
Voltage
VOHmin of TTL. In a mixed family system. it is
CMOS outputs only when the power supply voltage for the
necessary to use 'HCT devices. pull-up resistors. or
metal-gate CMOS devices is between 2 V and 6 V.
level shifters.
Output
The output voltages of HCMOS are TTL-compatible.
HCMOS output voltage levels are compatible with metal-gate
CMOS inputs only when the power supply voltage for the
Voltage
metal-gate CMOS devices is between 2 V and 6 V.
Drive
The output current capability of HCMOS is not as
Capability
large as the TTL family.
HCMOS has a higher current drive capability.
Fan-out
HCMOS has a smaller fan-out to LS devices than
(LS devices)
the TTL family.
HCMOS has a higher fan-out to LS devices.
Supply
HCMOS has a wide operating supply voltage range
Operating supply range of metal-gate is larger than HCMOS
Voltage
(2 V to 6 VI.
(from 3 V to 15 VI.
ESD and
TTL family devices are not as vulnerable to ESD and
HCMOS has an improved protection circuitry against ESD
Latch-Up
latch-up damage.
and latch-up.
:2
Guidelines for Handling Electrostatic-Discharge Sensitive (ESDS)
Devices and Assemblies
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This specification establishes the requirements for methods and materials used to protect electronic parts, devices, and
assemblies (items) susceptible to damage or degradation from electrostatic discharge (ESD). The electrostatic charges referred
to in this specification are generated and stored on surfaces of ordinary plastics, most common textile garments, ungrounded
people's bodies, and many other commonly unnoticed static generators. The passage of these charges through an electrostaticsensitive part may result in catastrophic failure or performance degradation of the part.
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The part types for which these requirements are applicable include, but are not limited to, those listed:
1)
2)
3)
4)
All metal-oxide semiconductor (MOS) devices, e.g., CMOS, PMOS, etc.
Junction field-effect transistors (JFET)
Bipolar digital and linear circuits
Op Amps, monolithic microcircuits with MOS compensating networks, on-board MOS capacitors, or other MOS
elements
5) Hybrid microcircuits and assemblies containing any of the types of devices listed
6) Printed circuit boards and any other type of assembly containing static-sensitive devices.
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Definitions
1. Antistatic material: ESD protective material having a surface resistivity between 109 and 10 14 fl/square.
2. Static dissipative material: ESD protective material having surface resistivity between 105 and 109 flIsquare.
3. Conductive material: ESD protective material having a surface resistivity of 105 O/square maximum.
7-29
4. Electrostatic discharge (ESD): A transfer of electrostatic charge between bodies at different electrostatic potentials
caused by direct contact or induced by an electrostatic field.
5. Surface resistivity: An inverse measure of the conductivity of a material and is the resistance of unit length and
unit width of a surface. Note: Surface resistivity of a material is numerically equal to the surface resistance between
two electrodes forming opposite sides of a square. The size of the square is immaterial. Surface resistivity applies
to both surface and volume conductive materials and has the dimension of O/square.
6. Volume resistivity: Also referred to as bulk resistivity; It is normally determined by measuring the resistance
(R) of a square of material (surface resistivity) aqd multiplying this value by the thickness (T).
7. Ionizer: A blower that generates positive and negative ions, either by electrostatic means or by means of a radioactive
energy source, in an airstream, and distributes a layer of low velocity ionized air over a work area to neutralize
static charges.
.
8. Close proximity: For the purpose of this specification, is 6 inches or less.
Device Sensitivity per Test Circuit of Method 3015, MIL-STD-883
Devices are categorized according to their susceptibility to damage resulting from electrostatic dis~harge (ESD), and
the type packaging required to adequately protect them.
1) Device electrostatic sensitivity:
Category
A
B
ESO Sensitivity (V) .
20-2000
>2000
. Minimum Protective Packaging
Antistatic Magazine & Conductive Bag/Box
Antistatic Magazine & Antistatic Bag
2) Devices are to be' categorized by their sensitivity
3) Devices are to be protected from ESD damage from receipt at incoming inspection through assembly, test and
shipment of completed equipment.
APPLICABLE REFERENCE DOCUMENTS .
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The following reference documents (of latest issue) can provide additional infortnation on ESD controls.
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2)
3)
4)
5)
6)
7)
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MIL-M-38510 Microcircuits, General Specification
MIL~STD-883 Test Methods and Procedures for Microelectronics
MIL-S~19491 Semiconductor Devices, Packaging of
MIL-M-55565 Microcircuits, Packaging of
DOD-HDBK-263 Electrostatic Discharge Control Handbook for Protection
DOD-STD-1686 Electrostatic Discharge Control Program
NAVSEA SE 003-11-TRN-OlO Electrostatic Discharge Training Manual
FACILITIES FOR STATIC-FREE WORK STATION
The minimum acceptable static-free work station shall consist of the work surface covered with an ESD protective material
attached to ground through a 1 MO· ± 10% resistor. an attached grounding wrist strap with integral 1 MO ± 10% resistor
for each operator,· and air ionizer(s) of sufficient capacity for each operator. The wrist strap shall be connected to the ESD
protective material. Ground shall utilize the standard building earth ground, refer to Figure 42. Conductive floor tile along
with conductive shoes may be used in lieu of the conductive wrist straps. The Site Safety Engineer must review and approve.
all electrical connections at the static-free work station prior to its implementation.
.
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Air ionizers shall be positioned so that the devices at the static-free work stations are within a 4-foot arc measured by
a vertical line from the face of the ionizer and 45 degrees on each side of this line.
General grounding requirements are to be in accordance with Table 5.
7-30
ESD PROTECTIVE
TRAYS. ETC.
PERSONNEL
GROUND STRAP
j
R
.J\A"
vvv
R
ESD PROTECTIVE
TABLE TOP
OTHER
ELEC.
EQUIP.
I
IONIZER
I
vv
CHAIR
WITH GROUND
(OPTIONAL)
=
ESD PROTECTIVE
FLOOR MAT
~J~V~~Av~_(_O~P;I:NAl~
WORK BENCH
[
All electrical equipment sitting on the conductive table top must be hard grounded but must be isolated from the conductive
table top.
NOTE: Earth ground is not computer ground or RF ground or any other limited type ground.
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Figure 42. Static-Free Work Station
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Table 5. General Grounding Requirements
Handling Equipment/Handtools
GROUNDED TO
OR MADE OF CONDUCTIVE MATERIAL
COMMON POINT
~
X
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X
Metal Parts of Fixtures
and Tools/Storage Racks
Handling Trays/Tubes
X
X
Soldering Irons/Bath
Table Tops/Floor Mats
«
TREATED WITH ANTISTATIC SOLUTION
X
Personnel
X
X Using Wrist Strap'
'With 1 MO ± 10% resistor
Usage of Antistatic Solution in Areas to Control the Generation of Static Charges
The use of antistatic chemicals (antistats) should be a supplemental part of an overall organized ESD program. Any antistatic
chemical application shall be considered as a means to reduce or eliminate static charge generation on nonconductive materials
in the manufacturing or storage areas.
The application of any antistatic chemical in a clean room of class 10,000 or less shall not be permitted. Accordingly,
any user of antistatic solutions must consider the following precautions:
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1. Do not apply antistatic spray or solutions in any form to energized electrical parts, assemblies, panels, or equipment.
2. Do not perform antistatic chemical applications in any area when bare chips, raw parts, packages, and/or personnel
are exposed to spray mists and evaporation vapors.
7-31
The need for initial application and frequency of reapplication can only be established through routine electrostatic voltage
measurements using an electrostatic voltmeter. The following durability schedule is a reasonable expectation.
1) Soft surfaces (carpet, fabric seats, foam padding, etc.): each 6 months or after cleaning, by spraying.
2) Hard abused surfaces (floors, table tops, tools, etc.): each week (or day for heavy use) and after cleaning, by
wiping or mopping.
3) Hard unabused surfaces (cabinets, walls, fixtures, etc.): each 6 months or annually and after cleaning, by wiping
or spraying.
4) Company-furnished and maintained clothing and smocks: after each cleaning, by spraying or adding antistatic
concentrate to final rinse water when cleaned.
The use of antistatic chemicals, their application, and compliance with all appropriate specifications, precautions, and
requirements shall be the responsibility of the Area Supervisor where antistatic chemicals are used.
ESD Labels and Signs in Work Areas
ESD caution signs at work stations and labels on static-sensitive parts and containers shall be consistent in color, symbols,
class, and voltage sensitivity identification, and appropriate instructions. Signs shall be posted at all work stations performing
any handling operations with static-sensitive items. These signs shall contain the following information.
CAUTION
STATIC CAN DAMAGE COMPONENTS
Do not handle ESDS items unless grounding wrist strap is properly
worn and grounded. Do not let clothing or plain plastic materials
contact or come in close proximity to ESDS items.
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Labels shall be affixed to all containers containing static-sensitive items at a place readily visible and proper for the intended
purpose. Additionally, labels must be consistently placed on containers and packages at a standard location to eliminate
mishandling. Use only QC accepted and approved signs and labels to identify static-sensitive products and work areas. The
use of ESD signs and labels, and their information content shall be the responsibility of the Area Supervisor to assure consistency
and compatibility throughout the static-sensitive routing.
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Relative Humidity Control
Since relative humidity has a significant impact on the generation of static electricity, when possible, the work area should
be maintained within the following relative humidity ranges: incoming/assembly/test/storage 50%-65% (ref. Ashrae, 55-74),
within ± 5 % to avoid static voltage monitor variations.
PREPARATION FOR WORKING AT STATIC-FREE WORK STATION
A work station with a COIl~llctive work surface connected to ground through a 1 MO ± 10% resistor, a grounding wrist
strap with the ground wire connected to the conductive work surface, and an ionizer constitute a static-free work station
(Figure 42). An operator is properly grounded when the wrist strap is in snug (no slack) contact with the bare skin, usually
positioned on the left wrist for a right-handed operator. The wrist strap must be worn the entire time an operator is at a
static-free work station. The operator should first touch the grounded bench top before handling static-sensitive items. This
precaution should be observed in addition to wearing the grouding wrist strap. If possible, operators should avoid touching
leads or contacts even though grounded.
CAUTION
Personnel shall never be attached to ground without the presence
of the 1 MO ± 10% series resistor in the ground wire.
7-32
An operator's clothing should never make contact or come in close proximity with static sensitive items. They must
be especially careful to prevent any static-sensitive items (being handled) from touching their clothing. Long sleeves must
be rolled up or covered with antistatic sleeve protector banded to the bare wrist which shall "cage" the sleeve at least as
far up as the elbow. Only antistatic finger cots may be used when handling static-sensitive items.
Any person not properly prepared, while at or near the work station, shall not touch or come in close proximity with
any static-sensitive items. It is the responsibility of the operator and the Area Supervisor to ensure that the static-free work
area is clear of unnecessary static hazards, including such personal items as plastic coated cups or wrappers, plastic cosmetic
bottles or boxes, combs, tissue boxes, cigarette packages, and vinyl or plastic purses. All work-related items, including
information sheets, fluid containers, tools, and parts carriers must be those approved for use at the static-free work station.
GENERAL HANDLING PROCEDURES AND REQUIREMENTS
1. All static-sensitive items must be received in an antistatic/conductive container and must not be removed from
the container except at static-free work station. All protective folders or envelopes holding documentation (lot
travelers, etc.) shall be made of nonstatic-generating material.
2. Each packing (outermost) container and package (internal or intermediate) shall have a bright yellow warning
label attached, stating the following information or equivalent:
CAUTION
ELECTROSTATIC
SENSITIVE
DEVICES
DO NOT OPEN OR HANDLE
EXCEPT AT A
STATIC·FREE WORKSTATION
The warning label shall be legible and easily readable to normal vision at a distance of 3 feet.
3. Static-sensitive items are to remain in their protective containers except when actually in work at the static-free
station.
4. Before removing the items from their protective container, the operator should place the container on the conductive
grounded bench top and make sure the wrist strap fits snugly around the wrist and is properly plugged into
the ground receptacle, then touch hands to the conductive bench top.
S. All operations on the items should be performed with the items in contact with the grounded bench top as much
as possible. Do not allow conductive magazine to touch hard grounded test gear on bench top.
6. Ordinary plastic solder-suckers and other plastic assembly aids shall not be used.
7. In cases where it is impossible or impractical to ground the operator with a wrist strap, a conductive shoe strap
may be used along with conductive tile/mats.
8. When the operator moves from any other place to the static-free station, the start-up procedure shall be the
same as in PREPARATION FOR WORKING AT STATIC-FREE WORK STATION.
9. The ionizer shall be in operation prior to presenting any static-sensitive items to the static-free station, and shall
be in operation during the entire time period the items are at the station.
10. "Plastic snow" polystyrene foam, "peanuts," or other high-dielectric materials shall never come in contact
with or be used around electrostatic sensitive items, unless they have been treated with an antistat (as evidenced
by pink color and generation of less than ± 100 volts).
11. Static-sensitive items shall not be transported or stored in trays, tote boxes, vials, or similar containers made
of untreated plastic material unless items are protectively packaged in conductive material.
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PACKAGING REQUIREMENTS
Packaging of static-sensitive items is to be in accordance with Device Sensitivity, item 1). The use of tape and plain
plastic bags is prohibited. All outer and inner containers are to be marked as outlined in GENERAL HANDLING
PROCEDURES AND REQUIREMENTS, item 2, and conductive magazines/boxes may be used in lieu of conductive bags.
7-33
SPECIFIC HANDLING PROCEDURES FOR STATIC-SENSITIVE ITEMS
Stockroom Operations
1. Containers of static-sensitive items are not to be accepted into stock unless adequately identified as containing
static-sensitive items.
2. Items may be removed from the protective container (magazine/bag, etc.) for the purpose of subdividing for
order issue only by a properly grounded operator at an approved static-free station as defined in FACILITIES
FOR and PREPARATION FOR WORKING AT STATIC-FREE WORK STATION.
3. All subdivided lots must be carefully repackaged in protective containers (magazine/bag, etc.) prior to removal
from the static-free work station and labeled to indicate that the package(s) contain static-sensitive items. If it
is suspected that a static-sensitive item is not adequately protected, do not transfer it to another container, return
it to the originator,for disposition unless the originator is a Customer. In that case, the QC Engineer should
contact the Customer and negotiate an appropriate disposition.
4. It is the responsibility of the Stockroom Supervisor to ensure that all personnel assigned to this operation are
familiar with handling procedures as outlined in this specification. A copy of this specification is to be posted
in the vicinity so that it is accessible to the operators. Stock handlers and all others who might have occasion
to move stock are to be inst~cted to avoid direct contact with unprotected static-sensitive items.
Module and Subassembly Operations
1. Static-sensitive items are not to be received. from a stockroom, kitting, or machine insertion area unless received
in approved static-protective packaging, and properly labeled to indicate that its contents are static sensitive.
2. All single station, progressive line manual assembly operators, and visual inspectors prior to wave soldering
operations are to be properly grounded with a grounding wrist strap when handling static-sensitive items.
3. Progressive lines used as single stations where operators will be working on a mix of boards, both static-sensitive
and nonstatic-sensitive, will require that all operators working on the line be properly grounded. This is necessary
to accomrn'odate the sliding of static-sensitive boards along the assembly bench or across positions not engaged
in the assembly of this type board.
4. It is the responsibility of the Area Supervisor to ensure that all personnel handling static-sensitive items are
familiar with this procedure and fully aware of the damage or degradation of these units in the event of
noncompliance. A periodic inspection should be made using an electrostatic voltmeter to assure that the staticfree stations are in proper working order and to ensure that operators are wearing grounding wrist straps properly
(snugly in contact with bare skin).
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Soldering and Lead-Forming Operations
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7-34
All soldering machines, conveyors, cleaning machines, and equipment shall be electrically grounded to ensure
that they are at the same ground potential as the grounded operators working on their stations. No machine
surfaces exposed to static-sensitive items are to be above the ground potential.
All processing equipment shall be grounded, including all loading and unloading stations, that is, the stations
.
before and after each piece of processing equipment.
All nonmetallic, static-generating components in the handling systems shall be treated to ensure protection from
static.
All stations shall be identified by posting signs as outlined in ESD Labels and Signs in Work Areas.
Operators are to be properly grounded with a grounding wrist strap during any handling, loading, unloading,
inspection, rework, or proximity to static-sensitive items.
Unloading operators working at a grounded station shall place static-sensitive items into approved static-protective
bags or containers.
All manual soldering, repair, and touch-up work stations on the solder line are to be static protected. Operators
are to wear grounding wrist straps when working on static-sensitive items. Only grounded-tip soldering/desoldering
irons are allowed when working on static-sensitive items.
It is the responsibility of the Area Spervisor to ensure that all personnel handling static-sensitive items are familiar
with this procedure and fully aware of the damage or degradation of these units in the event of noncompliance.
A periodic inspectiori should be made using an electrostatic voltmeter to assure that the static-free stations are
in proper working order and to ensure that operators are wearing grounding wrist straps properly (comfortably
snug in contact with bare skin).
Electrical Testing Operatioris
1.
2.
3.
4.
5.
6.
7.
8.
9.
All electrical test stations shall be static protected. Operators shall be properly grounded when working on these
items.
Reused antistatic magazines must be monitored for maintenance of antistatic characteristics.
Devices should be in an antistatic/conductive environment except at the moment when actually under test.
Devices should not be inserted into or removed from circuits or tester with the power on or with signals applied
to inputs to prevent transient voltages from causing permanent damage.
All unused input leads should be biased if possible.
Device or module repairs must be performed at static-free stations with the operator attached to a grounding
wrist strap. Grounded-tip soldering irons shall be used when working on static-sensitive items.
Static-sensitive items shall be handled through all electrical inspections in static protective containers. Removal
of the items from the protective containers shall be done at a static-free work station as discussed in
PREPARATION FOR WORKING AT A STATIC-~E WORK STATION. The units must be returned
to the containers before leaving the station.
All such items shall be shipped with anESD warning label affixed as listed.
It is the responsibility of the Area Supervisor to ensure that all personnel handling static-sensitive items are
familiar with this procedure and fully aware of the damage or possible degradation of these units in the event
of noncompliance. A periodic inspection should be made using an electrostatic voltmeter to assure that the static-free
stations are in proper working order and to ensure that operators are wearing grounding straps properly (snugly
in contact with bare skin).
Packing Operations
1. Static-sensitive items are not to be accepted into the packing area unless they are contained in a static-protected
2.
3.
.
bag or conductive container.
A static-sensitive item delivered to the packer within an approved container or bag and found to be in order
regarding identification shall be packed in the standard shipping carton or other regular packaging material.
Containers are to be labeled in accordance with GENERAL HANDUNG PROCEDURES AND
REQUIREMENTS, item 2.
Any void-fillers shall be made of an approved antistatic material.
Bum-In Operations
1;
Burn-in board loading and unloading of static-sensitive items shall be done at a static-free station.
2. Shorting clips/shorted connectors shall be installed on the board plug-in tab prior to loading any units into the
3.
4.
board sockets. The clip/connector shall be taken off just prior to plugging the board into the oven connector.
The clip/connector shall be installed immediately upon removal of the board from the oven connector.
Installation and removal of the clip/connector shall be done by a properly grounded operator.
All automatic or semiautomatic loading and unloading equipment shall be properly electrically grounded.
It is the responsibility of the Area Supervisor to ensure that all personnel handling static-sensitive items are
familiar with this procedure and fully aware of the damage or possible degradation of these units in the event
of noncompliance. A periodic inspection should be made using an electrostatic voltmeter to assure that the static-free
stations are in proper working order and to ensure that operators are wearing grounding straps properly (snugly
in contact with bare skin).
CUSTOMER RETURNED ITEM HANDLING PROCEDURE
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7-36
GENERAL INFORMATION
I
RATINGS AND CHARACTERISTICS
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HCMOS DEVICES
HCMOS DEVICES -
ADVANCE.INFORMATION
I
HCMOS DEVICES -
PRODUCT PREVIEWS
I
EXPLANATION OF LOGIC SYMBOLS
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DESIGNERS' INFORMATION
MECHANICAL DATA
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8-1
ORDERING INSTRUCTIONS
Electrical characteristics presented in this data book, unless otherwise noted, apply for circuit type(s) listed
in the page heading regardless of package. The availability of a circuit function in a particular package
is denoted by an alphabetical reference above the pin-connection diagram(s). These alphabetical references
refer to mechanical outline drawings shown in this section.
Factory orders for circuits described in this catalog should include a four-part type number as explained
in the following example.
EXAMPLE
(1.
Prefix
SN
54HC02
J
-00
)J-_ _ _ _ _ _ _---.J,!f
MUST CONTAIN TWO TO FOUR LETTERS
SN
SNJ
JANB
Standard Prefix
MIL-STD-883 Processed and Screened
per JEDEC Standard 101
MIL-M-38510 Processed
2. Unique Circuit Description
MUST CONTAIN SIX TO NINE CHARACTERS
Examples:
54HCOO
74HC74
74HCT620
74HC4002
3. Package
MUST CONTAIN ONE OR TWO LETTERS
J. JT. N. NT (Dual-in-line packages) t
FH. FK. or FN (Chip carriers)
(From pin-connection diagram on individual data sheet)
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4. Instructions (Dash No.)
MUST CONTAIN TWO NUMBERS
- 00 No special instructions
- 10 Solder-dipped leads (N and NT packages only)
t These circuits in dual-in-line packages are shipped in one of the carriers shown below. Unless a specific method of shipment is specified
by the customer (with possible additional costs). circuits will be shipped in the most practical carrier. Please contact your TI sales
representative for the method that will best suit your particular needs.
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Dual-in-line (J. JT. N. NT)
Slide Magazines
- A-Channel Plastic Tubing
Barnes Carrier (N only)
- Sectioned Cardboard Box
- Individual Plastic Box
8-2
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
MECHANICAL DATA
FH and FK ceramic chip carrier packages
Both versions of these hermetically sealed chip carrier packages have ceramic bases. The FH package
is an all-ceramic package with a glass seal. The FK package has a three-layer base with a metal lid and
braze seal.
The packages are intended for surface mounting on solder lands on 1,27 (0.050) centers. Terminals require
no additional cleaning or processing when used in soldered assembly.
FH and FK package terminal assignments conform to JEDEC Standards 1 and 2.
FH AND FK CERAMIC CHIP CARRIER PACKAGES
(28-terminal package shown)
CERAMIC CHIP CARRIERS
JEDEC
OUTLINE
DESIGNATION"
NO.OF
TERMINALS
MS004CB
20
MS004CC
28
A
B
MIN
MAX
MIN
MAX
8,69
(0.342)
11,23
(0.442)
9,09
(0.358)
11,63
(0.458)
7,80
(0.307)
10,31
(0.406)
9,09
(0.358)
11,63
(0.458)
• All dimensions and notes for the specified JEDEC outline apply.
2:
0,81 (0.032)
0,66 (0.026)
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ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS
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INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
1,35 (0.053)
1,19 (0.047)
MECHANICAL DATA
J ceramic packages (including JT packages)
Each of these hermetically sealed dual-in-line packages consists of a ceramic base, ceramic cap, and a
lead frame. Hermetic sealing is accomplished with glass. Once the leads are compressed and inserted,
sufficient tension is provided to secure the package in the board during soldering. Tin-plated ("brightdipped") leads require no additional cleaning or processing when used in soldered assembly.
14-PIN J CERAMIC
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7,87 (0 3'0)
~-~f--7'-11-(oJ8~~ (0.290)
CD (] 0) 0 0 ® CD
6,22 (0.245)
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1,7B (0.070) MAX '4 PLACES
1,27
(0 050) NOM
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• SEATING PLANE
'05'
8
5,08(0200)
MAX
90'
GLASS·
1-I-,.........,.,~'"""....,..,1IIj¥ SEALANT
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0,356 (0 014)
a 203 (0 OOB)
14 PLACES
3,30 (0 130)
MIN
2,54 (0 lOa)
1,78 (0 070)
4 PLACES
-11-
PIN SPACING 2,54 (0 lOa) T P.
(See Nol. e)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
16-PIN J CERAMIC
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6,2210.246)
1,27 10.OSO) NOM
f.r\
10So
'90'
16 PLACES
\;:;;:;~;:;~;:;;:;;:;~ SEc;.L.:i.~T
~SEATINGPLANE--....--.-I~
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16PLACES
0,76(0.030) MIN
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12 PLACES
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16 PLACES
-II~ 0,3610.016)
~:~ :~:~~~: 4 PLACES
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
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TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
8-5
MECHANICAL DATA
J ceramic dual-in-line packages (continued)
2a-PIN J CERAMIC
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6.22i0245T
1
1.27 (00501 NOM
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20 PLACES
GLASS
SEALANT
5.08(02001
•
MAX
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3.30(01301'.
M~
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0.356(0.0141
~~0.203(0.0081
20 PLACES
.------~-y
I 0.305(0.0121 MIN
'•
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11r-'1+-++-ttt-0,76 (0.0301 MIN
16 PLACES
4 PLACES
PIN SPACING 2.54(0.1001 T. P.
(See Note AI
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN I'NCHES
24-PIN JT CERAMIC
~----31.8
(1.250) MAX-----+I
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1,27 (0.050) NOM
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0,356 (0.014)
0,203 (0.008)
24 PLACES
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
MECHANICAL DATA
JD ceramic dual-in-line packages - side-braze
This is a hermetically sealed ceramic package with a metal cap and side-brazed tin-plated leads.
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