1984_Western_Digital_Communications_Products 1984 Western Digital Communications Products
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June, 1984
Communication
Products Handbook
WESTERN DIGITAL
CORPORA
TID
N
June, 1984
Communications
Products Handbook
COPYRIGHT©1984 WESTERN DIGITAL CORP
ALL RIGHTS RESERVED
This document is protected by copyright, and contains information proprietary to Western Digital Corp. Any copying, adaptation, distribution,
public performance, or public display of this document without the express written consent of Western Digital Corp. is strictly prohibited. The
receipt or possession of this document does not convey any rights to reproduce or distribute its contents, or to manufacture, use, or sell any1hing
that it may describe, in whale or in part, without the specific written consent of Western Digital Corp.
Making The Leading Edge
Work For You.
This handbook is designed for you, the engineer. It's intended to
be a useful tool, enabling you to make a preliminary evaluation of
our products and later, with samples in hand, design our products
into your own systems.
The data in these pages have been reviewed by our Marketing,
Engineering, Manufacturing, and Quality groups. Now we would
like you to review the information we've provided and tell us how
we can improve it. Please feel free to suggest any changes,
additions, or clarifications that occur to you. And don't hesitate to
call to our attention any sins of omission or commission we may
have made.
We're eager to help upgrade the quality of information our industry
provides to its customers. So, please, help us. Direct your commentsto:
Corporate Communications Director
WESTERN DIGITAL CORPORATION
2445 McCabe Way
Irvine, CA 92714
(714) 863-0102
iii
WESTERN DIGITAL
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Regional and District Sales Offices
Northeastern
United States/Eastern Canada
Southern
United States
Western
United States/Western Canad.
70 Atlantic Avenue
Marblehead, MA 01945
Phone: (617) 631-6466
TWX: 710-347-1060
1015 Semoran Blvd.
Summit Plaza II, Suite 0
Casselberry, FL 32707
Phone: (305) 331-4434
TWX: 810-853-0297
1151 Dove Street
Suite 170
Newport Beach, CA 92660
Phone: (714) 851-1221
TWX: 910-595-2430
4950 Westgrove Dr., Suite 115
Dallas, TX 75248
Phone: (214) 248-6785
TWX: 910-997-0509
5677 Oberlin Drive, Suite 202
San Diego, CA 92121
Phone: (619) 457-1777
TWX: 910-337-1257
2300 W. Meadowview Road
Suite 209
Greensboro, NC 27407
Phone: (919) 299-6733
TWX: 510-922-7309
201 San Antonio Circle
Building E, Suite 172
Mountain View, CA 94040
Phone: (415) 941-0216
TWX: 910-379-5038
Europe
5743 Corsa Ave.
Suite 201
Westlake Village, CA 91361
Phone: 818-991-2556
72 Sumit Avenue
Montvale, NJ 07645
Phone: (201) 930-0700
TWX: 710-991-8360
North Central
United States
3600 West 80th Street
Suite 620
Bloomington, MN 55431
Phone: (612) 835-1003
TWX: 910-576-2417
1301 West 22nd Street
Suite 217
Oakbrook, IL 60521
Phone: (312) 655-8781
TWX: 910-651-3193
28/30 Upper High Street
Epsom, Surrey KT174QJ
United Kingdom
Phone: 44-3727-42178
Telex: 851-925796
Deutschland GMBH
Prinzregentenstrasse 1201111
0-8000 Muenchen 80
Federal Republic of Germany
Phone: 011-49-89-470-7021
TWX: 841-521-4568
WESTERN DIGITAL
CORPORATION
2445 McCABE WAY
IRVINE, CALIFORNIA 92714
iv
(114) 863·0102, TWX 910·595-1139
Table of Contents
Functionallndex .........................................................................
Numerical Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Product Quality/Reliability ...........................................................
Quality/Reliability to Leading Edge Technology .................................................
Announcing Burn-In Program AvailabilitylWarranties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hi-Rei "K" Testing Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Protocol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Local Area Network Products ...............................................................
SDLC/HDLC/X.25 Products ................................................................
Asynchronous/Bisynchronous Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Data Security Products ....................................................................
Video Products ..........................................................................
Support Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Package Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pin Functional Compatibility Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Storage Management Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Terms and Conditions .....................................................................
vii
ix
1
5
11
13
15
17
87
177
267
287
327
383
384
386
387
389
Bulletin: New products soon to be announced.
Advance Information: This product has not been produced in volume and is subject to functional and timing
revisions. Please contact Western Digital Corporation for current information.
Preliminary: This product is limited production and may be subject to change after device characterization has been
completed. Please contact Western Digital Corporation for current information.
Final: This product is in full production and intended for normal commercial applications. For military, extended
temperature, burn-in, or hi-rei applications, contact Western Digital Corporation for information regarding further
processing.
Application Note: This is specific application information related to the designated product(s).
v
vi
COMMUNICATION PRODUCTS
Functional Index
Part Number
Page
LOCAL AREA NETWORK PRODUCTS
WD2840 Local Network Token Access Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WD2840 Application Note. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Local Network Access Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Token Passing Cashes In With Controller Chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Token Access Controller Minimizes Network Complexity. . . . . . . . . . . . . . . . . . . . . . . . .
WD4028 Net Source/PC-LAN Local Area Network Controller . . . . . . . . . . . . . . . . . . . . .
..
..
..
..
..
..
....
....
....
....
....
....
.
.
.
.
.
.
....
....
....
....
....
....
..
..
..
..
..
..
17
53
65
69
77
83
SDLC/HDLC/X.25 PRODUCTS
WD2511 X.25 Packet Network Interface (LAPB) . . .
WD2511 Application Note. . . . . . . . . . . . . . . . . . . .
WD1935 Synchronous Data Link Controller (SDLC)
WD1935 Application Note. . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 117
......................................... 137
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 155
ASYNCHRONOUS/BISYNCHRONOUS PRODUCTS
WD2123 Dual Enhanced Universal Communications Element (DEUCE) .........................
WD8250 Asynchronous Communications Element. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TR1863/1865 Universal Asynchronous Receiver/Transmitter (UART) ............................
TR1863/1865 Application Note ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
UC1671 Asynchronous/Synchronous Transmitter/Receiver (ASTRO) . . . . . . . . . . . . . . . . . . . . . . . . . . ..
WD1993 Arinc 429 Receiver/Transmitter and Multi-Character Receiver/Transmitter . . . . . . . . . . . . . . . ..
177
195
213
223
235
251
DATA SECURITY PRODUCTS
WD2001/WD2002 Data Encryption Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 267
WD2001/WD2002 Application Note ...................................................... 279
VIDEO PRODUCTS
WD8275 Programmable CRT Controller
WD8276 Small System CRT Controller
287
309
SUPPORT PRODUCTS
WD1943 Dual Baud Rate Clock ......................................................... 327
WD1510 LIFO/FIFO Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 335
WD9914 General Purpose Interface Bus Controller (GPIB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 339
vii
viii
Numerical Index
Part Number
Page
WD1510 ................................................................................ 335
UC1671 ................................................................................ 235
TR1863/1865 ............................................................................ 213
WD1935 ................................................................................ 137
WD1943 ................................................................................ 327
WD1993 ................................................................................ 251
WD2001IWD2002 ........................................................................ 267
WD2123 ................................................................................ 177
WD2511 ................................................................................ 87
WD2840 ................................................................................ 17
WD4028................................................................................ 83
WD8250 ................................................................................ 195
WD8275 ................................................................................ 287
WD8276 ................................................................................ 309
WD9914 ................................................................................ 339
ix
x
WESTERN DIGITAL
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System Product Quality/Reliability
QUALITY PROGRAM DESCRIPTION
The Quality Organization shown on the attached
organization chart (Figure 2) reports directly to the
President of Western Digital. It assures compliance
to design control, quality and reliability specifications pursuant to corporate policy. Quality assurance
provisions are derived in part from MIL-Q-9858, as
applied to high grade commercial products.
CORPORATE QUALITY POLICY
It is the policy of Western Digital Corporation that
every employee be committed to quality excellence
in producing products/processes which conform to
acceptable requirements. The total quality program is
managed and monitored by the quality assurance
organization. Quality assurance is chartered to review marketing product requirements, qualify hardware and software designs, certify manufacturing
operations and monitor performance/control conformance to product specifications.
Primary responsibility for execution of the quality
program rests with functional organizations to design, produce, and market high quality and high reliability products specified to our customers.
DESIGNING FOR RELIABILITY
The premise upon which board and system manufacturing operations are based is that quality is planned
and designed-in, not screened-in or selected. A welltested, high-quality design is far more reliable than a
marginal design with any amount of burn-in or fixes.
To assure top quality design, Western Digital maintains one of the most experienced board/system
design staffs in the industry. A tightly controlled
design review team comprising members from Quality Assurance, Marketing, Manufacturing and several
experienced design engineers, provides review of
each new design several times during its development to ensure widest possible performance margins. The production release procedure assures a
checklist for:
~ Test Method/Program Qualifications
~ Characterization Report
~ Field Test (Beta Test) Report
~ Product Qualification Audit
~ Documentation Package Release for Document
Control
~ SoftwarelDiagnostics Qualification
MAINTAINING QUALITY/RELIABILITY IN
PRODUCTION
The Quality Control Testing Flow Chart shown on
Figure 1 defines the exact stages contained in the
production process. Internally manufactured LSI
components undergo 100% testing at maximum
specified operating temperatures as well as strict
quality controls defined to assure high quality and reliability. Components not designed and manufac·
tured by Western Digital are also 100% screened as
shown in photos during incoming inspection at 70·C.
The tests performed include selective active component burn-in performed at 125·C for 160 hours to
insure guaranteed levels of reliability. This 125·C accelerated testing eliminates defects that cannot effectively be accelerated by burning-in boards and
systems which have temperature limitations. Key
quality control procedures include:
10" Incoming Inspection Procedure
10" In-Process Travel Card Traceability
10" Workmanship Standards
10" Quality Corrective Action Notice/MRB Procedure
10" Quality Audit Procedure
PRODUCT FINAL TEST/CORRECTIVE ACTION
All boards are 100% in-circuit tested and 100%
functional tested for acceptable performance according to applicable test specifications on testers
qualified by QA. Products are tested at maximum
speCified temperature and voltage margins using
diagnostic software to ensure greater performance
margins. Failures are logged on a travel card
specifically designed to insure traceability to
manufacturing steps and to maintain failure records
for QA corrective action.
If the board is designed to perform in a host system,
further diagnostics are performed in an environment
configured to actual customer requirements.
PRODUCT ACCEPTANCE
Upon completing the final test, the board/system
undergoes QC final workmanship standards inspection and selective samples are audited to the functional product specification to guarantee quality at
specified operating margins to the customer.
~J\.~ ...
In-circuit test
2
Complete documentation available for you at our facility.
Receiving Inspection
• 100% Bare Board Testing
• 100% LSI Test (max. temp.)
• 100% IC Test at 70·C
• Power Supply Inspections
• Mechanical/Visual Inspections
Selective Static/Dynamic Burn·in
(Active components)
Mainframe Mechanical
Assembly
P.C. Board Assembly
Travel Card Traceability
Assembly Test (Bed of Nails)
• Shorts/Opens
• Orientation
Assembly Outgoing Inspection
Test Incoming/Travel Card
Traceability
Functional Test
• Voltage Margins
• Temperature Margins
• Diagnostic Software
Mainframe Inspection
Final Inspection
• Revision Control
System Configuration
Functional Test
• Temp. Margins
• Diagnostic Software
Functional Audit
Travel Card Review
Final Inspection
Ship System
Ship Board Product
o
LEGEND:
D
Mfg. Operation
Figure 1.
Mfg. Inspection Gate
QUALITY CONTROL TESTING FLOW CHART
3
~ QCGate
WESTERN DIGITAL CORPORATION
CHIEF EXECUTIVE
• Systems Quality
• New Product
Qualification
• System Test
Qualification
• Software
Qualification
• LSI Qualification
• Burn·ln/Stress
Requirements
• Reliability Monitor
Data
• Reliability Testing
•
•
•
•
~---JII,--------,I
"Systems Design
Control"
Document Control
Wafer Defects Control
Subsidiary/Offshore QC
Process Qualification
1 - . - 1_
"LSI Design Control"
Figure 2.
•
•
•
•
•
•
•
•
•
Incoming QC
Vendor Quality
LSI Burn·ln
LSI Package Monitors
Precap Visuals (883 optional)
100% Test Audit
Failure Analysis
Package Qualification
Calibration Control
_
_- - - - - '
"Manufacturing Assurance"
QUALITY ORGANIZATION
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed
by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
4
Printed tn U S.A
WESTERN DIGITAL
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Quality/Reliability To Leading Edge Technology
QUALITY PROGRAM DESCRIPTION
Purchased FAB and assembly operations are
individually qualified and are certified against
standard specifications during vendor qualifi·
cation and monitored against reliability
criteria.
Defect control within the process assures the
highest levels of built·in reliability.
• Quality audits and gates are located throughout
the manufacturing process in order to assure a
stable process and thus, a quality product to our
customers. Figure 1 illustrates the manufacturingl
screening/inspection flow diagram and identifies
the steps as they relate to the production of LSI
devices.
• Testing assures quality margins through 100%
testing by manufacturing and, in addition, all
products must pass a specified AQL sample test
performed by QA at maximum operating tem·
perature as follows:
The Quality Organization shown in Figure 2 assures
compliance to design control, quality and reliability
specifications, pursuant to corporate policy.
CORPORATE QUALITY POLICY
It is the policy of Western Digital Corporation that
every employee be committed to quality excellence
in producing products/processes which conform to
acceptable requirements. The total quality program is
managed and monitored by the quality assurance
organization. Quality assurance is chartered to
review marketing product requirements, qualify
hardware and software designs, certify manufac·
turing operations and monitor performance/control
conformance to product specifications.
Primary responsibility for execution for the quality
program rests with functional organizations to
design, produce and market high quality and high
reliability products specified to our customers.
Outgoing Quality Levels
SUBGROUPS
INSPECTION LEVEL
Subgroup 1 - Final 100% Electrical
Audit @ Max ·C
Subgroup 2 - Visual (Marking, Lead
Integrity, Package, Verify customer
shipper)
Subgroup 3 - Shipping Visual Audit
LSI QUALITY ASSURANCE PROGRAM
HIGHLIGHTS
• LSI manufacturing assurance provisions are
derived in part from MIL·M-38510 and MIL·STD883B as applied to high grade commercial com·
ponents.
0.5 AQL·
1.0 AQL
1.0 AQL
'The double sampling techniques used allow considerably
better AQL's in most all cases.
• All process raw materials used in the Mask/Wafer
fabrication and assembly operations are
monitored by Material Assurance.
• Material Assurance maintains a thorough control
of incoming material and has developed unique
"use/stress tests" (look ahead sample build ac·
ceptance) which critical material must pass before
acceptance.
• LSI devices are 100% tested on industry standard
test systems like that shown below. Quality
outgoing testing (auditing) is done on the Fairchild
Sentry Series 20 where possible to allow better
correlation with customers.
• The Product Assurance Department continuously
monitors the internal and external manufacturing
flow (shown in Figure 1) and issues process
control reports displaying detailed data and trends
for the associated areas.
Document control is an integral part of Product
Assurance. All specifications are issued and
controlled by this activity.
The Western Digital Malaysian assembly
operation uses specifications and quality
control provisions controlled by Document
Control. Indicators of Malaysia quality are
reviewed weekly.
5
Starting Material
Receiving Inspection
Lid Seal
Optional
Offshore
Assembly
Design and Mask
Fabrication
Final Assembly
Inspection
Outgoing
Inspection
100% Stab:lization Bake
Plastic 125·C, 24 hrs.
Ceramic 150·C, 24 hrs.
100% Temperature rycle
Plastic - 55·C te' + 125·C
10 cycles
Ceramic - 65·C to + '50·C
10 cyclef
Wafer In·Process Audits/
Defects Control
(See Table 1)
Gross Leak (.65 AQL)
Fine Leak Test
(.65% AQL)
Solder Dip Leads
Lead Inspection
Cut and Form Inspection
Base SeallnspeGtlon
Assembly
Incoming
Inspection
100% Electrical Test
Wire Bond Inspection
Final Test Audit - 0.5 AQL
Precap Inspection
,.
~
Reliability Monitors
(Table 3 & 4)
- i5Pi iona 1- -
- - - -;::
Static/Dynamic
:
Burn·ln
I
100% Electrical
Test
:
I
Burn·ln Brand
I
Shipping Audit
I
'- _ _ _ _ _ _ _ _ _ _ _ JI
Ship By Customer
Specified Carrier
LEGEND
o
Figure 1
Manufacturing operation
o
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Quality Assurance Audit
'V
Quality Assurance Gate
Manufacturing Inspection Gate
LSI PRODUCTION FLOW
6
Reliability Means Lasting Value
• DESIGNING FOR RELIABILITY
The production release procedure for an LSI device is
designed to assure maximum reliability with a
Quality checklist for:
i!1' Test program qualifications
li:j'" Characterization report
Li1' Field test (Beta Test) report
C!?' Reliability Lifetest Qualifications
C!?' Infrared Thermal Analysis
[j?" Static Protection
All new devices and major process changes must
pass reliability qualification before incorporation into
production using the criteria defined in Tables 2-4.
The infrared microscope shown on the right assures
optimum burn-in temperatures and margins of safety.
The dynamic burn-in system shown on the right is
one of two custom designed systems which assure
protective device isolation during burn-in .
• MAINTAINING RELIABILITY IN PRODUCTION
Process defects control are defined to continually
measure built-in reliability, as measured by the
following criteria:
TABLE 1
PROCESS RELIABILITY CONTROL
Subgroup 1 - Defects Control
a. Oxide Integrity
b. Polysilicon Integrity
Subgroup 2 - Electro-Migration Control
Metal Step Coverage
Subgroup 3 - Defect Density
Subgroup 4 Integrity
METHOD
Non-destructive
bubble test
SEM Analysis
CONDITION
SAMPLE"
Pinhole defect density
5 wafers
Visual
5 wafers
SEM Analysis
5 wafers
MIL-STD-883
Method 2018
Critical layers
Field
Gate
Contact
Metal
Visual of Photo defects
(Defects/in2)
MIL-STO-883 Method
2021
Visual of Pinhole
defect density
8 wafers
each layer
Passivationllnsulation
'Inspection intervals are defined by the in-line process control data reviewed on a lot-by-Iot basis.
7
Final Silox
5 wafers
Intermediate
5 wafers
• PROGRAMS TO ASSURE OPTIMUM RELIABILITY
Improved levels of reliability are available under custom reliability programs using static and dynamic burn-in to
further improve reliability. These programs focus on MOS failure mechanisms as follows:
FAILURE MECHANISMS IN MOS
FAILURE
MECHANISM
Slow Trapping
Contamination
Surface Charge
Polarization
Electromigration
Microcracks
Contacts
Oxide Defects
Electron Injection
EFFECT ON
DEVICE
ESTIMATED
ACTIVATION ENERGY
Wearout
Wearoutl
Infant
Wearout
Wearout
Wearout
Random
Wearoutl
Infant
Infantl
Random
Wearout
-----
1.0eV
1.4 eV
Static Burn-In
Static Burn-In
0.5-1.0eV
1.0eV
1.0eV
Static Burn-In
Static Burn-In
Dynamic Burn-In
100% Temp. Cycling
Dynamic Burn-In
-
Dynamic Burn-In
at max. voltage
Low Temp. Voltage
Operating Life
0.3eV
-
Temperature Acceleration of Failure
10 10
The Arrhenius Plot defines a failure rate proportional to exp( - Ea/kt) where Ea is the activation
energy for the failure mechanism. The figure on
the right indicates that lower activation energy
failures are not effectively accelerated by temperature alone; hense, maximum voltage operation
is selectively applied to optimize the burn-in
process.
10'
10'
m
ex:
10'
::l
0
::s
Static Bum-In (125°C - 48 hours or 160 hours)
10'
w
ex:
Provided on a sample baSis for process
monitor/control of 0.5 eV 1.0 eV failure
mechanisms. 100% static burn-in may be
specified at an additional cost. However, static
burn-in is considered only partially effective for
internal LSI gates at logic "0" levels.
Dynamic Burn-In (Pattern test/125°C 160 hours)
SCREENING
METHOD
::l
..J
10'
~
U.
0
tW
~
f=
10'
10'
10'
8 hours to
10'
Accelerated functional dynamic operating life
effectively controls internal MOS gate defects
buried from external pin access. The input pattern
is optionally pseudo-random or fixed pattern
programmable to simulate 1000-3000 hours of field
operation at maximum operating voltage(s).
10'
25
50
75
100
125 150 175200
250]
TEMPERATURE (0C)
'---------------------------
High.Rel "K" Testing Program
General conformance to MIL-STD-883B method
5004.4, Class B with static Burn-In (Dynamic BurnIn may be specified as an option).
8
LSI RELIABILITY STANDARDS
TABLE 2
TEST
STANDARD RELIABILITY LEVELS
CONDITION
METHOD
Infant
Mortality
(see note)
Long Term
Failure Rate
Static
Burn-In
125'C - 160 hrs.
Dynamic
Life Test
125'C - 1000 hrs.
FAILURE
<0.5%
I
!-
<.05%/1000 hrs.
@55'C
60% Confidence
'NOTE: Devices failing the infant mortality target remain on burn·in until acceptable failure rates are obtained.
TABLE 3
TEST
GROUP A DEVICE RELIABILITY MONITORS
METHOD
Subgroup 1
a. Internal Visual
b. Thermal Shock
c. Bond Strength
d. Die Shear Strength
CONDITIONS
15
1011
2011
2019
Test Failure Used (cond. B or C)
Test Failures (cond. B)
Test Failures
b. Seal - Fine Leak
1014
Fluorocarbon detection 10 - 3
atm/cc/sec
Test Condition A
Subgroup 3
a. Rotating Steady State Life Test
1005
Subgroup 2
a. Seal- Gross Leak
-
b. Electrical Parameters
TABLE 4
TEST
Subgroup 1
a. Thermal Shock
b. Temperature Cycling
c. Seal - Gross Leak
d. Seal - Fine Leak (ceramic)
e. Electrical Parameters
f. 85/85 Moisture Resistance
(plastic only)
g. Electrical Parameters
Subgroup 2
a. High Temp. Storage
b. Mechanical Shock
c. Seal - Gross Leak
d. Seal - Fine Leak
(ceramic)
e. Electrical Parameters
Subgroup 3
a. Lead Integrity
LTPD
Static 160 hr. Burn-In 125'C
plus 125'C Lifetest - 1000 hrs.
Final electrical @ 25°C (with data @
70'C)
15
5
GROUP B PACKAGE RELIABILITY MONITORS
CONDITIONS
METHOD
1011
1010
1014
-
-
Test Condition B or C
Test Condition B orC
Fluorocarbon detection 10 - 3
atm/cc/sec
Test Condition A
Electrical at max -C
85% RH/85'C for 1000 hours
PDA
10%
Final electrical @ 25°C
1014
-
Final electrical @ 25°C/max. C
2004
Test Condition B2
(Lead Fatigue)
Fluorocarbon detection 10 - 3
atm/cc/sec
Test Condition A
-
b. Seal - Gross Leak
-
c. Seal - Fine Leak
(ceramic)
1014
15
=
Test Condition B or C
Test Condition B
Fluorocarbon detection 10 - 3
atm/cc/sec
Test Condition A
1008
2002
LTPD
9
15
15
WESTERN DIGITAL CORPOIIATION
CHIEF EXECUTIVE
• Systems Quality
• New Product
Qualification
• System Test
Qualification
• Software
Qualification
• LSI Qualification
• Burn-In/Stress
Requirements
• Reliability Monitor
Data
• Reliability Testing
•
•
•
•
Document Control
Wafer Defects Control
Subsidiary/Offshore QC
Process Qualification
•
•
•
•
•
•
•
•
•
Incoming QC
Vendor Quality
LSI Burn-In
LSI Package Monitors
Precap Visuals (883 optional)
100% Test Audit
Failure Analysis
Package Qualification
Calibration Control
L-------II 1.. --1_ I ,---I_ _ _-----'
"Systems Design
Control"
"LSI Design Control"
Figure 2
"Manufacturing Assurance"
QUALITY ORGANIZATION
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
10
Printed in U,S.A.
WESTERN DIGITAL
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Announcing Burn-In Program Availability/Warranties
I
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Western Digital now supports customer burn-in
requirements for both static and dynamic burn-in
under the strict control of the QA-Reliability
organization.
This burn-in provides high performance 125°C static
and dynamic burn-in for 8-160 hours to eliminate
infant mortality and improve reliability. This process
is executed using custom modified 32Bit AEHR test
commercial burn-in equipment which provide monitored fixed pattern or pseudorandom burn-in with
power supply and resistor device pin isolation.
LSI dynamic burn-in is verified in all cases by the
design engineer for proper functioning. LSI Chip sets
are also individually burned-in with dynamic equivalency to assure high performance bundled reliability.
The warranty on the program will optionally provide
certificate of compliance to standard or custom designed burn-in programs and guarantee <.05%/Khrs
fai lure rate.
CAUTION
Using outside burn-in methods not certified as acceptable by Western Digital may result in voided warranty, due to mishandling, junction temperature
stress, or electrical damage. Further, since most
burn-in houses do not support testing, catastrophic
system condition can result in substantial damage
before a problem is identified.
One consistent problem experienced with outside
LSI burn-in houses can cause reliability problems;
namely, parallelling totem pole MOS outputs, where
the output states are not predictable, can cause a
single (or a few) device(s) to sink all the current from
the other devices on the burn-in tray - electromigration or current zaps are both possible.
Western Digital burn-in diagrams, dated after 1/1/82,
must be used exactly as shown and will be provided
upon request.
SEE YOUR LOCAL REPRESENTATIVE FOR COSTS
AND ORDERING INFORMATION ON THIS NEW
PROGRAM.
11
12
WESTERN DIGITAL
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Hi- Rei "K" Testing Program
GENERAL DESCRIPTION
FEATURES
GENERAL CONFORMANCE TO MIL·STD·883B,
METHOD 5004.4, CLASS B (SEE COMPARISON ON
FOLLOWING PAGES)
• INCLUDES:
PRECAP VISUALS
SEAL INTEGRITY
POWER CONDITIONING
ENHANCEMENT OPTIONS
PACKAGE PROBED WAFERS
Western Digital's Hi·Rel "K" program is designed to
provide high reliability devices for extended tempera·
ture environments. Individual enhancements may be
specified to meet a customer's requirements .
INITIATE
LOT
TRAVELER
OC
AUDIT
FINE LEAK
SCRIBE/SAW
GROSS LEAK
BREAK/SORT
CUT/FORM LEADS
INSPECT
PRE BURN·IN
ELECTRICALS
CHIPBOND
BURN·IN
160 HRS @ 125'C
INSPECT
FINAL TEST
WIRE BOND
FINAL TEST
0.5% AOL
INSPECT
CLEAN/BAKE/SEAL
CERTIFICATE
OF
CONFORMANCE
TEMP CYCLE
10CYCLES
-65'/+150'C
STABAKE
24 HRS 150'C
BRAND
MOVETO
FINISHED
GOODS
PACK
SHIP VIA
CUSTOMER
SPECIFIED
CARRIER
HI·REL "K" PROGRAM FLOW DIAGRAM
13
COMPARISON OF MIL·STD·883
AND HI·REL "K" TEST PROGRAM
HI·REL "K" TEST
MIL·STD·883B, METHOD 5004.4, CLASS B
3.1.1 Internal Visual
Method 2010.3
Test condition B
All Hi-Rei UK" devices receive 100% inspections
prior to lid seal. These inspections together comprise criteria comparable to Mil-Std-883, method
2010.3, test condition B.
3.1.2 Stabilization Bake
Method 1008.1
Test condition C
24 hours at 150°C
Same
3.1.3 Temperature Cycling
Method 1010.2, Test condition C
- 65°C to 150°C for 10 cycles, with 10 minutes
dwell and 5 minutes maximum transfer time
Same
3.1.4 Constant Acceleration
Method 2001.2, Test condition E. 30,000 G stress
level
Not Done Unless Specified
3.1.5 Visual Inspection
Visual inspection for catastrophic failures after
screens
Same
3.1.6 Seal Method 1014.2
(a) Helium fine leak - Test condition A1. Bomb
condition 2 hours at 60 psig. Reject limit 5 x 10- 8
torr
(b) Flourocarbon gross leak - Test condition C
Same
Same
3.1.9 Interim (pre·burn·in) Electricals
Per applicable device specification
Preburn-in test at 25°C. Must meet requirements of
device data sheets.
3.1.10 Burn·in Test
Method 1015.2 160 hours @ 125°C
Same
3.1.13 Interim (Post burn·in) electricals
Per applicable device specification
Burn-in equipment isolate failures automatically to
assure no harmful interaction.
3.1.15 Final Elect~ical Test
(a) Static Tests
(1) 25°C
(2) Minimum and Maximum Operating
Temperatures
(b) Dynamic and Switching Tests at 25°C
(c) Functional Tests at 25°C
Same
3.1.17 Qualification or Quality Conformance
Inspection and Test Sample Selection
Not done unless defined using method 5005 as a
guide.
3.1.18 External Visual
Method 2009.2
Same
WESTERN DIGITAL RELIABILITY ENHANCEMENT
OPTIONS
Extended High Temperature Storage
100% Temperature Testing
+ 150°C for 24 hours standard, other time/temperature storage requirements available as required .
Level ....................... - 40° to + 85°C
. . . . . . . . . . . . . . . . . . . . .. - 55° to + 125°C
Thermal, Shock (Liquid to Liquid)
Level. ............... 0° to + 100°C, 15 cycles
. . . . . . . . . . . . . . . . . . . . . . - 55° to + 125°C
...................... - 65° to + 150°C
Dynamic Bum·ln
Per note previously supplied .
14
Printed
In
U.S,A
COMMUNICATION FAMILIES
UART - Universal Asynchronous Receiver-Transmitter
PSAT - Programmable Synchronous/Asynchronous Transmitter
PSAR - Programmable Synchronous/Asynchronous Receiver
USART - Universal Synchronous/Asynchronous Receiver-Transmitter
BOART - Bus Oriented Asynchronous Receiver-Transmitter
DLC
- Data Link Controller
PROTOCOL DEFINITIONS
• START and STOP Bits
• 5,6,7, a Bits/Character
• Plus option of Parity (Even or Odd)
Multiple Character Asynchronous
•
•
•
•
5,6,7, ora bits/character
Up to a characters/word
Start and Stop bits
Parity inside or outside of word
6
aJPlss
7
Stop Bit(s)
~
l
parlty....l
Line Marking
2 eight bit characters with start stop bits and parity
Programmed stop bits
Start bit
----~t~~~~I.T.~~cr.~~~r_----Marking line or
next transmission
1st a bit Character
2nd a bit Character
Previous Fil lor
Data Charac ters
• No START and STOP Bits
• 5,6,7,8 Bits/Character
• Plus option of Parity Bit
1
(Even or Odd)
Bisync Characte r(Byte)
Transmission
Data or Fill Character
2
- Start of Header
- Synchronization Character
- Start Text
- End olText
- Block Check Character
FillorNul1
3
4
5
6
,
0
SOH
SYN
STX
ETX
BCC
5
' - Data Bits
Marking line or . ,
end of previous
character
Synchronous
(Byte Oriented)'
r
r Start Bit
I ' r1 2 3
Marking Line ""\
Asynchronous
(Character Oriented)
S
0
H
S
Y
N
Data or
Fill Characters
Data or Fill Character
7
P
1
2
3
4
5
6
7
P
I.Xft'--_L-~+g-L-_
Header
.
BCC Field------I~
i 4 - - - - - - S D L C Frame------I~
Synchronous Data Link Control (SDLC)
Flag = 7E (Hex)
Packet Switching (X.25)
Data Link Control
(Bit Oriented)
~-----------l-Frame(Packet) _ _ _ _ _ _ _ _ _ _ _...~I
Flag
----X.25 LeveI2----~ X.25 Level 3
tol
......
15
1--'~:~~~X.25 Level 2
16
WESTERN DIGITAL
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WD2840 Local Network Token Access Controller
FEATURES
DNC
• Broadcast Medium Independent (Coax, RF, CATV,
IR, etc.)
• Up to 254 nodes
• Dual DMA/Highly efficient Memory Block
Chaining
• Token based protocol
• Acknowledge option on each datagram
• Adjustable fairness, stations may be prioritized
• Frame format similar to industry standard HDLC
• Supports Global Addressing
• Diagnostic Support: Self-Tests, System and
Network
• TTL Compatible
VCC(+SV)
IA1
sa
WE
lAO
CS
IA2
IA3
RE
ClK
MR
VDD( + 12V)
AS
A4
A3
A2
A1S
A14
A13
A12
A11
A10
A9
AS
A7
A6
DAlO
DAl1
DAl2
DAl3
DAL4
DAlS
DAl6
DAL7
RD
RC
(GND)VSS
TC
TO
RTS
CTS
AO
DROO
DROI
A1
DACK
PIN DESIGNATION
DESCRIPTION
The WD2840 is a MOS/LSI device intended for local
network applications, where reliable data communications over a shared medium is required. The device
uses a buffer chaining scheme to allow efficient memory utilization. This scheme minimizes the host CPU
time requirements for handling packets of data. The
WD2840 frees the host CPU from extensive overhead
by performing network initialization, addressing, coordination, data transmission, acknowledgements and
diagnostics.
multi-point communications applications. The token
protocol allows the sharing of one bus by up to 254
nodes. WD2840's will be designed into process control
equipment, micro-computers, mini-computers, personal computers, proprietary micro-processor based
applications, intelligent terminals, front-end processors, and similar equipment.
The great advantage for the design engineer is the
ease with which he can implement a local network
function. The WD2840 handles autonomously all major
communications tasks as they relate to the local network function.
APPLICATIONS
The WD2840 is a general purpose Local Network
Token Controller applicable to virtually all types of
17
1
I
1.1
PIN DEFINITIONS
PIN NUMBER
SYMBOL
1
DNC
PIN NAME
DO NOT CONNECT
FUNCTION
leave pin open.
2
SQ
SIGNAL QUALITY
An active low input which signals the WD2840
that a frame may be received. The modem may
negate this signal if its receive signal quality is
below a reliability threshold, ensuring that the
WD2840 will not accept the frame.
3
WE
WRITE ENABLE
The data on the DAl are written into the
selected register when CS and WE are low. RE
and WE must not be low at the same time.
4
CS
CHIPSElECT
Active low chip select for CPU control of 1/0
registers.
5
RE
READ ENABLE
The content illhe selected register is placed
on DAl when CS and RE are low.
6
7
ClK
MR
CLOCK
MASTER RESET
Clock input used for internal timing.
Initialize on active low. All registers reset to zero,
except control bit ISOL is set to 1. DACK must be
stable high before MR goes high. Status Register
o is not defined at power-up (this register will be
set-up upon entry into the Network mode).
DAlO-7
DATA ACCESS LINES
An 8·bit bi-directional three·state bus for CPU
and DMA controlled data transfers.
RD
RC
RECEIVE DATA
Receive serial data input.
RECEIVE CLOCK
This is a 1X clockJ!:!put, and RD is sampled on
the riSing edge of RC.
GROUND
8·15
16
17
18
19
VSS
TC
TRANSMIT CLOCK
Ground.
A 1X clock input. TD changes on the falling
edge ofTC.
20
TD
TRANSMIT DATA
Transmitted serial data output.
21
RTS
REQUEST·TO·SEND
An open collector output which goes low when
the WD2840 is ready to transmit either data or
flags.
22
CTS
CLEAR·TO·SEND
An active low input which signals the WD2840
that transmission may begin.
DRQO
DMA REQUEST OUT
An active low output signal to initiate CPU bus
request so that the WD2840 can output onto the
bus.
24
DRQI
DMA REQUEST IN
An active low output signal to initiate CPU bus
requests so that data may be input to the
WD2840.
25
DACK
DMA ACKNOWLEDGE
An active low input from the CPU in responseJQ
DRQO or DRQI. DACK must not be low if CS
and RE are low or if CS and WE are low.
AO-A15*
ADDRESS LINES OUT
Sixteen address outputs from the WD2840 for
DMA operation.
VDD
INTR
POWER SUPPLY
INTERRUPT REQUEST
+ 12VDC power supply input.
An active low interrupt service request output.
Returns high when Interrupt Register is read.
IAO-IA3*
ADDRESS LINES IN
Four address inputs to the WD2840 for CPU
controlled readlwrite operations with registers
in the WD2840. If ADRV = 0, these may be tied
to AO-A3.
VCC
POWER SUPPLY
+ 5VDC power supply input.
23
26·41
42
43
44·47
48
-
--
18
WD2840 LOCAL NETWORK
TOKEN ACCESS CONTROLLER
The WD2840 is designed to logically interconnect 2
to 254 user devices over a shared communications
medium. Examples of typical mediums include coax
cable, twisted pair bus, RF, and CATV. All network control functions, such as data framing and error checking,
destination filtering, fair and adjustable transmission
scheduling, and network initialization and fault recovery (caused by noise for example) are handled completely by the WD2840.
The protocol implemented allows guaranteed station
access intervals allowing applications in factory
automation and other critical communications environments where "statistical delays" are not acceptable. The WD2840 token protocol also allows the
addition and/or removal of stations to a network at
anytime, including while operating.
INTRODUCTION
The WD2840 is a single LSI device which gives
systems designers the ability to include networking
capabilities into their unique products simply and
economically.
A general and fundamental advantage to the use of
complex LSI in a given system is the partitioning of
required technical expertise. A successful user of the
WD2840 need not be a data-communications expert,
and further, he need not be at all concerned with low
level network details (though these details are documented and available to him if he is interested). The
potential user of the WD2840 must Simply evaluate
the communications facilities provided by the device
to determine its suitability for the intended use.
~-
:
-- ------------ ---------------- -------------------1
DALO.7, IAO.3
~T
I
I
I
I
140---.1 RE~:~~ER
(16 HOST
' - - - - - L _ - r -_ _~---l
VISABLE)
DMA REGS
(2 CHAN)
I
I
I
'--------- ----- -- ----- -- Figure 1.1
- - - - -- -- -- - ----- - --:
BLOCK DIAGRAM
19
,
I
tails of the communications protocol implemented
by the WD2840 Token Access Controller.
The document is organized into three main sections:
SECTION ONE is much like a traditional data sheet
including register descriptions, pin definitions, and
hardware architecture.
SECTION TWO describes the interfaces to the
WD2840. The network side is conventional, the host
side consists of an elaborate DMA interface with
control blocks and WD2840/host handshaking.
SECTION THREE details the network protocol implemented by the device. Normal operation, initialization, and the handling of error conditions are
described.
Serious attention has also been given to the user's
interface to the device. The interface is a combination of conventional I/O registers and an
elaborate DMA buffer chaining interface. This
chaining feature allows the user much more efficient
use of his system memory, particularly in situations
where the maximum message sent over the network
is much longer than the average size. This feature
also allows the automatic queueing of messages
independently of the user's consumption rate, in
effect, speed decoupling the user's CPU and
processing requirements from the network.
The WD2840 has several parameters (registers) that
allow tailoring to the user's requirements. In this way,
network priority and access ordering, to name two,
can be manually set if desired.
Using an integrated version of these network
algorithms saves not only the development costs
already mentioned, but further, the total processing
power required for the user's application is not increased. In other words, a CPU upgrade can likely be
avoided by "distributing" the network processing
task into LSI devices such as the WD2840.
SCOPE
This document differs from traditional LSI data
sheets in that it details not only the LSI implementation of a function, but also defines the overall function in detail. Specifically, this document includes de-
MEDIUM
AO·15
TO
DROI
TC
WD2840
DROO
RTS
DACK
CTS
DALO·?
RD
cs
RC
WE
so
RE
IAO·3
INTR
MR
TYPICAL SYSTEM CONNECTION
20
MODEM
terrupt Event Register, a Counter Register and a
variety of Parameter Registers. In general the host is
responsible for defining these registers (except certain host read-only registers: SR0-2, IRO, CTRO and
NA) to contain proper and meaningful values prior to
entering Network Mode from Isolate State. Furthermore, while the WD2840 is in Network Mode, the
CBP (H,L) and MA registers must not be changed by
the host. Register NAR may be changed arbitrarily
but will only be considered by the WD2840 in
response to the NEWNA (CR10) control bit being set.
The two Control Registers and the TA, TD, AHOLT,
TXLT registers may change dynamically to control
the behavior of the WD2840.
1.2 DEVICE ARCHITECTURE
A detailed block diagram of the WD2840 is shown in
Figure 1.1.
Mode control and monitor of status by the user's
CPU is performed through the Read/Write Control
circuit, which reads from or writes into registers
addressed by IAO-IA3.
Transmit and receive data are accessed through DMA
control. Serial data is generated and received by the
bit·oriented controllers.
Internal control of the WD2840 is by means of three
internal micro-controllers; one for transmit, one for
receive, and one for overall control.
Parallel transmit data is entered into the Transmitter
Holding Register (fHR), and then presented to the
Transmitter Register(fR) which converts the data to a
serial bit stream. The Frame Check Sequence (FCS)
is computed in the sixteen bit CRC register, and the
results become the transmitted FCS.
REG
(1]
A
NAME
CRO
CR1
SRO
IRO
SR1
SR2
CTRO
NA
TA
TD
CBPH
B
C
D
E
F
CBPL
NAR
AHOLT
TXLT
MA
0
1
2[2]
3[2]
4[2]
5[2]
6[2]
7[2]
8
DESCRIPTION
Control Register 0
Control Register 1
Status Register 0
Interrupt Event Register
Status Register 1
Status Register 2
Counter Register 0
Next Address
ACKTimer
Net Dead Timer
Control Block Pointer
(MSB)
Control Block Pointer (LSB)
Next Address, Request
Access Hold-off Limit
Transmit Limit
My Address
Parallel receive data enters the Receiver Holding
Register (RHR) from the 24 bit serial Receive Register
(RR). The 24-bit length of RR prevents received FCS
data from entering the RHA. The receiver CRC
register is used to test the validity of the received
FCS. A three level FIFO is included in the receiver.
The WD2840 sends all information, network control
and user data, in blocks called frames. Each frame
starts and ends with a single flag (binary pattern
01111110). In between flags, data transparency is
provided by the insertion of a zero bit after all
sequences of five contiguous one bits. The receiver
will strip the inserted zero bits. (See section on frame
format for location of address, control, and FCS
fields.)
[1]
[2]
1.3 REGISTER DEFINITION
The WD2840 is controlled and monitored by sixteen 8
bit registers. This set of registers consists of two
Control Registers, three Status Registers, an In-
Control, status, and interrupt bits will be referred to
as CR, SR, or IR, respectively, along with two digits.
For example, SR21 refers to status register #2 and bit
1, which is "STATE."
9
21
= Hexadecimal representation of IAO-IA3.
=CPU read only, write not possible.
SUMMARY -
CONTROL, STATUS, INTERRUPT REGISTERS
REGISTER
7
6
5
BIT #
4
3
2
1
0
CRO
TXDEN
TXEN
RXEN
ITOKON
ILOOP
COpy
NOINT
ISOL[i]
CRi[2]
CRi[4]
DIAGC
DIAGC
PIGT
0
INIT
0
ADRV
ADRV
GIRING
DMAT
0
LOOPT
TOFF
RAMT
NEWNA
NUDIAG
SRO
LASTF
SENDACK
L2
0
BSZ3
IRO[3]
ITERR
IROR
INS
ITRAN
IREC
ITOK
ITA
ITD/M
SRi
TAOUT
IRTS
RECIDL
1
1
1
1
1
SR2
NXnO
NXTRO
TR
ACKRQ
RETRY
TSENT
STATE
INRING
.. .
BSZ2
.. .
BSZi
... BSZO
NOTE: ZERO BITS (0) SHOWN ABOVE ARE RESERVED AND SHOULD NOT BE USED.
NOTES:
[1]
=Set to 1 on power-up or master reset.
[2]
=Non diagnostic mode only (CR17-DIAGC cleared).
[3]
=Any bit set causes host interrupt (INTR
[4]
=Diagnostic State only (CR17-DIAGC set). See diagnostic section for register usage in diagnostic mode.
goes true) when Master Interrupt Suppress (CR01) is clear. All
bits are cleared when register is read by the host.
CRO -
CONTROL REGISTER 0 DEFINITION
REGISTER
CR07
CR06
TXEN
CR05
CR04
CR03
CR02
CR01
CROO
RXEN
ITOKON
ILOOP
COPY
NOINT
ISOL
CRO
TXDEN
BIT
NAME
DESCRIPTION
CROO
ISOL
Isolate. Set true on power up or master reset. Host clears this bit after the host
memory based WD2840 control block and other WD2840 registers have been set
up. May be set by the host at any time (will be ignored if WD2840 is in diagnostic
state). There is some delay for the WD2840 to respond to any state change request.
A state change to network mode is acknowledged by the state confirmation status
bit (SR21-STATE) being cleared. Setting ISOL while the WD2840 is in Network State
will cause a state change to Isolate State, confirmed by an interrupt event (IROOITM) and the STATE status bit (SR21) being set. This transaction will be delayed
until the node does not possess the token. Any in-progress frame transmission will
be completed normally (at the current frame, regardless of queue length), followed
by a normal token pass sequence.
CR01
NOINT
Master Interrupt Suppress. When clear, the WD2840 will generate host interrupt
requests (INTH low) if any bit in the WD2840 interrupt request register (IRO) is set.
When set, only the interrupt request is suppressed, not the setting of bits in IRO.
Note that any interrupt request will be dropped by the WD2840 when IRO is read
since this will clear IRO.
CR02
COPY
Enables COPY mode. When set causes all received data frames to be accepted
and DMA'ed into memory regardless of destination address. (See description in
Diagnostics Section.)
CR03
ILOOP
Instructs the WD2840 to loop data internally from transmitter to receiver. Used with
the LOOP diagnostic. Must NOT be set while in network mode (CROO-ISOL clear).
CR04
ITOKON
Enable Token received interrupts. When clear no Token received interrupts are generated. When set the WD2840 generates an Itok interrupt when a token is received.
22
BIT
NAME
CR05
RXEN
DESCRIPTION
Receive Data Enable. When clear, the WD2840 still makes normal responseStO
supervisory frames (scan, token pass), but will not DMA any data frames into
memory and ignores the receiver buffer chain. However any data frame which is
addressed to this node and for which an ACK is requested, will be NAK'ed with a
"receiver not enable" Nak code. When RXEN is set, it allows the receiver to DMA
appropriate data frames into memory. RXEN may be arbitrarily set and reset while
in Network State but changes will not affect any frames in progress.
NOTE: Even when RXEN is clear, the WD2840 is "following" the receiver buffer
chain with an internal register pointing either to the next available buffer (NXTRO
set) or, if the chain is exhausted, to a link field of zero (NXTRO clear). The constraints on host manipulation of the receiver buffer chain are the same regardless
of the state of RXEN. See the subsequent section on Receiver Memory Interface
for more details.
CR06
TXEN
CRO?
TXDEN
Master Transmit Enable. When clear no transmissions will occur and the transmit
buffer chain will be ignored. When set, transmission activity is further dependent
upon TXDEN (CRO?).
NOTE: Even when TXEN is clear, the WD2840 is "following" the transmitter buffer
chain with an internal register pointing either to the next frame to transmit (NXTTO
set) or, if the chain is exhausted, to a link field of zero (NXTTO clear). The constraints on host manipulation of the transmitter buffer chain are the same regardless of the state of TXEN. See the subsequent section on Transmitter Memory
Interface for more details.
Data Transmit Enable. Has no meaning unless TXEN is set. When set in conjunction with TXEN, normal WD2840 transmission of data and supervisory frames
will occur. When clear and with TXEN set, only data frame transmission will be
suppressed. That is, token pass and Ack/Nak supervisory frames will still be
transmitted when appropriate.
NOTE: The note above for TXEN applies.
CR1 -
CONTROL REGISTER 1 DEFINITION
REGISTER
CR17
CR16
CR15
CR14
CR13
CR12
CR11
CR10
CR1
CR1
DIAGC
DIAGC
PIGT
0
INIT
0
ADRV
ADRV
GIRING
DMAT
0
LOOPT
TOFF
RAMT
NEWNA
NUDIAG
BIT
NAME
CR10
NEWNA
Update NA register. When set causes WD2840 to copy the contents of register
NAR into register NA. The WD2840 clears this bit after the function is complete.
This mechanism allows the host to define the WD2840's successor in the logical
ring. The node's next token pass will be to the new NA node.
NOTE: The normal token pass recovery applies. If the token pass to the new NA is
not successful, a normal scan sequence will occur where the WD2840 attempts a
single token pass to each node address in numerical sequence until a successful
pass occurs or the node's address itself is reached.
CR11
TOFF
When set causes WD2840 to ignore timers. (This is NOT intended to be used in an
operational network, but is provided to support network diagnosis.) CAUTION: This
control bit disables all automatic network error recovery.
CR12
-
CR13
GIRING
(Not used, Reserved.)
Get in logical ring. Instructs the WD2840 to gain entry into the logical ring at the
next opportunity (Le. respond to a token pass). The INRING status bit (SR20) is
confirmation; when INRING is set, it indicates that the WD2840 is participating in a
logical ring of at least two nodes. If the host clears GIRING while INRING is set,
the WD2840 will not accept the next token pass to it at which time INRING will be
cleared as confirmation.
DESCRIPTION (eR17
23
= 0, Network mode)
BIT
NAME
DESCRIPTION (CR17 = 0, Network mode)
CR14
ADRV
Address Driver Enable. Enables the sixteen output address (AO-A15). If ADRV = 0,
the outputs are tri-state and are in HI-Z, except when DACK goes low. If ADRV =
1, the outputs are always TTL levels.
CR15
INIT
Network Initialization Enable. When clear, the WD2840 will not attempt to
(re)initialize the network if the net dead timer (TO) expires. When set, TO timer
expiration causes the WD2840 to enter Scan Mode. In this mode it transmits a
token pass frame to each node numerically higher in address, one after another,
until either network activity occurs (another node responds) or until the node's own
address is reached. When Scan Mode begins, the first node address used is the
then current NA (Next Address) node address. This value is derived from and is
affected by the following actions:
At transition into Network State it defaults to MA + 1.
It may be set by the host using the NAR register and the NEWNA (CR1O)
control flag.
3. Upon receipt of a Scan Mode frame, NA is redefined to MA + 1.
The successful initialization of the network by Scan Mode causes NA to be defined
as the first responding node (hence, this node's success00.
All node address computations are ascending and circular within the valid node
address range of 1-254.
1.
2.
CR16
PIGT
CR17
DIAGC
CR1 -
NOTE: Since this network initialization activity comes about because of a timer
expiration, TOFF (CR11) must be clear.
If set, instructs WD2840 to piggy back token on last data frame transmitted. This
request is honored if the last frame is determined as a result of limit TXLT or the
LAST bit set in the TX-FCB, but not if transmission ends due to the reaching of the end
of the chain.
Enables diagnostic mode. In network mode this bit must be zero.
CONTROL REGISTER 1 DEFINITIONS
BIT
NAME
DESCRIPTION (CR17 = 1, Diagnostic mode)
CR10
NUDIAG
Perform a new diagnostic. When set causes WD2840 to perform the selected
diagnostics. The host initializes the appropriate registers for the particular
diagnostic and by setting this bit can initiate the test, The WD2840 clears this bit
after completion of the diagnostic.
Selects internal RAM test if in diagnostic mode.
Selects Loop Test if in diagnostic mode.
CR11
RAMT
CR12
CR13
LOOPT
DMAT
CR14
ADRV
CR15
CR16
-
CR17
DIAGC
Selects DMA Test if in diagnostic mode.
Address Driver Enable. Enables the sixteen output address (AO-A 15). If ADRV = 0,
the outputs are tri-state and are in HI-Z, except when DACK goes low. If ADRV =
1, the outputs are always TTL levels.
(Not used, Reserved.)
(Not used, Reserved.)
Enables diagnostic mode. Confirmation of diagnostic mode is via status bit STATE
(SR21). When DIAGC and STATE are both set, diagnostic functions of CR1 apply.
When DIAGC is cleared, after the selected set of diagnostics in progress complete, the WD2840 will transition to the Isolate state. This transition will cause an
interrupt event (ITM).
24
SRO - STATUS REGISTER 0 DEFINITION
REGISTER
SR07
SR06
SROS
SR04
SR03
SR02
SR01
SROQ
SRO
LASTF
SENDACK
L2
0
BSZ3
BSZ2
BSZ1
BSZO
BIT
NAME
SROO
BSIZ
..
..
SR03
DESCRIPTION
BSIZO - BSIZ3
Buffer size, defines the buffer size in multiples of 64 bytes (the value ranges from 0 to
15H. Corresponding to a buffer size of 64 to 1024 bytes in 64 byte increments). This
value is used internally to define buffer boundaries to allow the chip to link buffers. A
maximum of 16 buffers may be used for a single frame.
Not used.
SR04
-
SR05
L2
An internal flag set during frame transmission if the length value of the current
frame is equal to eight. For normal data frame transmission this means the frame
has no data field and for transparent frame transmission this means the frame is an
access control frame. (SCAN FRAME)
SR06
SENDACK
An internal flag set during data frame reception to indicate that the incoming frame
should be acknowledged (send ack/nak frame). This flag is cleared when the
acknowledgement has been transmitted.
SRO?
LASTF
An internal flag set during data frame transmission to indicate that the current frame
will be the last to be transmitted with this token. Five situations can cause this to
occur: 1) ISOL (CROO) becoming set, 2) TXDEN (CRO?) becomes clear, 3) current
frame flagged (via FCB) to be "last frame," 4) the current token frame count reaching
the TXLT limit, 5) transmitter under-run detection. Note in particular that the last frame
in the transmit queue will not cause LASTF to set since it's being last is not known until
frame end. Also if a piggy-back token is permitted (CR16 set) and no acknowledge is
requested (via FCXB), the token will be piggybacked on the current (last) data frame.
LASTF is not cleared until the next data frame transmission begins.
IRO -
INTERRUPT REGISTER DEFINITION
REGISTER
IRQ7
IR06
IROS
IR04
IR03
IR02
IR01
IROO
IRO
ITERR
IROR
INS
ITRAN
IREC
ITOK
ITA
ITD/M
The setting of any bit in this register by the WD2840 causes an interrupt request (INTR = low) if NOINT (CR01)
is clear. The reading of this register by the host clears all bits (and any interrupt request).
BIT
NAME
DESCRIPTION (1)
I ROO
ITD/M
Network dead or mode change (dual use). When in Network mode, timer TD expiring (with TOFF clear) causes this bit to be set to indicate no network activity has
occurred within the timeout period. Also INRING (SR20) is cleared and, if INIT (CR15)
is set, the WD2840 will enter Scan Mode (see INIT - CR15 for details). Transition from
Network or Diagnostic State to the Isolate State will be confirmed by this interrupt. The
choice between the lTD and ITM interpretations is easily made based on the ISOL
(CROO) bit.
IR01
ITA
Date Frame Transmission Unsuccessful. This interrupt indicates that a transmitted
data frame with an acknowledge request was not successfully acknowledged.
Either a NAK or no response after two transmissions will cause this. The exact
cause can be determined by inspecting the appropriate FSB.
IR02
ITOK
The token has been received.
25
BIT
NAME
DESCRIPTION (1)
IR03
IREC
Data Frame Received. This interrupt signifies that a good data frame has been
properly received and DMA'ed into the buffer chain. Frames that have been
received can be identified by following the buffer chain noting the WD2840 frame
status bytes (FSB). A non-zero FSB (host must clear when queuing free buffers)
indicates a properly received frame. The host may freely remove all received
frames from the chain up to but NOT necessarily including the last one posted.
The last one posted may only be removed if the WD2840 NXTRO (SR26) is set. For
more details see the explanation for NXTRO.
IR04
ITRAN
Indicates that at least one data frame has been transmitted. The number of frames
transmitted and the status of each (Le. ACKINAK, retry count) is determined by
following the transmit chain and inspecting frame status bytes (FSB). All transmitted frames up to but NOT including the last posted may be freely removed. The
last one posted may only be removed if the WD2840 NXnO (SR27) is set. For more
details see the explanation for NXnO.
IR05
INS
IR06
IROR
New successor. The WD2840 has identified a new successor in the logical ring.
This happens when the prior successor either failed to respond to a token pass or
as instigated by a network scan frame.
Receiver over-run. The WD2840 ran out of buffers or access to the DMA channel
was delayed by the host so long as to cause loss of received data.
IR07
ITERR
Transmitter error. Three abnormal frame transmission cases can cause the ITERR
interrupt. The causes are "transmitter underrun," "premature end of chain," and
"exceeded 16 buffers." The frame transmission will repeat once per token until the
host removes the WD2840 from the network, or the cause of the error is fixed.
(1) = Non diagnostic mode only. See diagnostic section for register usage for diagnostics.
SR1 - STATUS REGISTER 1 DEFINITION
REGISTER
SR17
SR16
SR15
SR14
SR13
SR12
SR11
SROO
SR1
TAOUT
IRTS
RECIDL
1
1
1
1
1
BIT
NAME
SR10
-
SR14
SR15
RECIDL
SR16
IRTS
SR17
TAOUT
....
DESCRIPTION
(Not used, reserved.)
Receiver Idle. Indicates the WD2840 has received at least 15 contiguous ones.
Internal Request To Send. Indica~s the transmitter is attempting (successful or not) to
send either data or flags. If the RTS pin is not tied to ground or WIRE-OR'ED with
another signal, then IRTS = RTS.
TimerTA expired.
26
SR2 - STATUS REGISTER 2 DEFINITION
REGISTER I SR27
SR2
I Nxno
SR26
NXTRO
I
I
SR25
TR
I
I
SR24
ACKRQ
I
I
SR23
RETRY
I
J
SR22
TSENT
I
I
SR21
STATE
I
SR20
I INRING
BIT
NAME
DESCRIPTION
SR20
INRING
SR21
STATE
SR22
TSENT
SR23
RETRY
SR24
ACKRQ
SR25
TR
SR26
NXTRO
SR27
NXnO
In logical ring. Indicates the node has had the token and has successfully passed it
at least once (therefore it is included in a logical ring of at least two nodes). See
GIRING (CR13) for other comments.
Mode confirmation. Depending on DIAGC (CR17), the WD2840 is either in Isolate or
Diagnostic state. When ISOL (CROO) is set, STATE set confirms the WD2840 is not
in Network State. When ISOL is clear, STATE clear confirms Network State. Note
any state transition into Isolate State causes an interrupt event to occur (ITM).
An internal flag. TSENT is set when the WD2840 passes the token. It may have
been either a piggyback or explicit token pass frame. TSENT is cleared when the
next frame is received.
An internal flag which is set when either a data frame or a token pass frame must
be retransmitted. Data frames are only retransmitted if they have an acknowledge
request and no response at all occurred. Token pass frames (except Scan) are
retransmitted if no network activity was detected. Both of these situations are
detected as a result of a TA timeout.
An intemal flag set during data frame transmission if an acknowledgement is
requested for the specific frame. If this is the case, the WD2840 pauses to await
the ACK/NAK response frame; if the TA timer expires before the response, a single
retry will occur (see RETRY-SR23). ACKRQ is not cleared until the beginning of the
next data frame transmission.
An internal flag set when the WD2840 receives a token passed to it. It is cleared
when the token is passed (or if it is ignored for any reason. For example, piggyback
token on a bad data frame, TXEN clear, or detection of duplicate tokens in the
logical ring).
Intemal Receive Buffer Pointer State. Because of the linked list approach used in
the buffer chains, the WD2840 internal register used to follow the list is either
pointing to the next buffer in the chain or at the address of the next buffer in the
chain (prior buffer's link field). The WD2840 will always advance along the chain so
that it has the address of the next buffer to be used. However, when a zero link is
encountered, the WD2840 retains the link field address expecting eventually that
the chain will be extended by the host making the link some non-zero value. When
the WD2840 actually needs the next buffer, it looks again at the contents of the link
field expecting it to have been changed (chain extended) to the address of an
available buffer. The NXTRO bit differentiates between these two situations. When
set it indicates the WD2840 has the address of the next buffer and that all prior
frames (denoted by posted FSB's) can be removed from the chain for received
frame processing by the host. When NXTRO is clear it indicates that the WD2840
has advanced to a zero link (end of chain).
NOTE: In this situation, the last posted frame CANNOT be removed from the chain
for processing since it is the link field of his last buffer that must be set in order to
extend the receiver buffer chain.
Internal Transmit Buffer Pointer State. The comments for NXTRO (SR26) apply (in an
analogous manner) to NXnO since the transmit buffer chain is handled by the
WD2840 using an identical scheme. When NXnO is set it indicates that the
WD2840 has the address of the next frame to transmit in its intemal register.
However when clear, it indicates that the transmit chain intemal register points to
the link field of the last buffer of the last transmitted frame. This link field contained zero when first read. For the transmit case, this is a normal situation
corresponding to no data frames to transmit.
NOTE: As in the receive case, when NXnO is set, all previously transmitted frames
(denoted by posted FSB's) can be removed from the chain for reuse. However,
when NXnO is clear it indicates that the transmit chain must be extended by the
host before removing the very last frame that has been transmitted (posted).
27
OTHER REGISTER DEFINITIONS
NAME
DESCRIPTION
CTRO
Running Limit Counter. Used by the WD2840 for Access Hold·Off Limit (AHOl1) checking and
Transmit Limit (TXl1) checking. When transmitting data frames CTRO is used for TXlT
counting; otherwise it is used for AHOlT counting. The counter runs from zero to the 8-bit
limit value.
Next Address. This register shows the current (instantaneous) successor node in the network
logical ring. For validity, the WD2840 should be "in the ring" (see GIRING· CR13 and INRING·
SR20 for more details). The successor node may be changed for a variety of reasons:
NA
1. Any attempted token pass that fails twice will cause the WD2840 to attempt to locate a
new successor by sequentially trying token passes to successively higher node ad·
dresses beginning with NA + 1.
2. A received Scan frame will cause NA to be set to MA" 1. If the next token pass fails case 1
applies.
3. The host may arbitrarily redefine NA by using the NAR register and the NEWNA (CR10)
control bit. At a convenient point the WD2840 recognizes NEWNA, copies NAR into NA,
then clears NEWNA as confirmation. If the next token pass fails case 1 applies.
TA
TO
CBP (H,l)
NAR
AHOlT
TXlT
MA
Acknowledgement Timer. Value of maximum allowed time between frame transmission and
ACKINAK (if requested), or between token sent and network activity. The delay is in in·
crements of 64 times the period of the clock ClK. Thus, if ClK = 2 MHz, then TA may be set
in increments of 32 microseconds (range of 32 /-Is to 8.2 ms).
Network Dead Timer. Value of maximum time interval between received valid frames on the
network. 32X range of TA.
Control Block Pointer. A sixteen bit pOinter to the WD2840 control block in the user's memory.
Must not be modified while the WD2840 is in network mode.
Next Address, Request. Used in conjunction with the NEWNA (CR10) control bit to cause the
WD2840 to update the NA register. This redefines the node's successor in the network logical
ring. It MUST be an address in the range 1·254. The acceptance of this update is confirmed
when the NEWNA control bit is cleared. On the next token pass, if the redefined successor
fails to accept the token, this WD2840 enters Scan mode where it sequentially attempts a
token pass to successively higher nodes.
Access Hold·off Limit. This register is set at a value indicating the number of access cycles
(tokens received) that must be skipped before the data frame may be transmitted. (A token pass
frame will be sent even if a data frame may not be sent at a given access cycle.) Initialized to zero
at power up.
Transmit Limit. This register is set at the maximum number of consecutive data frames the
WD2840 may transmit during one access cycle. A value of zero allows the WD2840 to transmit all
frames queued up to 256. Initialized to zero at power up.
My Address. The WD2840 receives only frames with this destination address (along with the
broadcast address) and inserts this address into the SA field of any transmitted frame. Must
be set by the host (range is 1 to 254).
28
dividual node, and those that are limited to the
WD2840 as a device. These tests are Network
Diagnostics, System Diagnostics and Self Diagnostics respectively. The Network Diagnostics can be
performed while the WD2840 is in the logical ring, but
the System Diagnostics and the Self Diagnostics
may be used only while the WD2840 is in the
diagnostic mode.
Diagnostic mode may be entered after power-up or
from the network mode by manipulation of the mode
control bits. The mode transition is confirmed by the
WD2840 via the STATE status bit.
Once in diagnostic mode, the desired test is selected
via CR1. Because most of registers 8 through Fare
interpreted differently for each test, only one of the
diagnostic test bits should be set at a time. In
conjunction with setting the diagnostic bits, the
NUDIAG (CR10) bit must be set to perform the
diagnostic test requested.
At the completion of the selected test NUDIAG is
cleared by the WD2840. Therefore the host can initiate a diagnostic by entering the diagnostic mode, initializing the proper registers, setting the desired
diagnostic bit, and setting NUDIAG. The host then
moniters CR1 for NUDIAG going to zero, indicating
the completion of the requested diagnostic.
1.4 DIAGNOSTIC AIDS
There are three levels of diagnostics supported by
the WD2840; those that are associated with the
network as a whole, those associated with the inDIAGNOSTIC
MODE CONTROL
CROO CR17 SR21
ISOL DIAGC STATE
1
0
0
0
1
0
0
0
1
1
1
0
1
1
1
0
0
0
0
1
1
0
1
1
DEFINITION
WD2840 "Isolated." Powerup condition or isolate
request.
WD2840 active.
Isolate request function
confirmed.
Host request to enter
diagnostic mode.
Diagnostic mode confirmed. Diagnostic functions of CR1 apply.
Illegal.
Illegal.
Illegal.
DIAGNOSTIC STATE FLOW CHART
ISOL = 1? ;rcNO=--_ TO NETWORK STATE
(CRDD)
INTR PIN 43 r-=---~
GOES LOW
NO
DIAGC = 1?
(CR17)
YES
I -_ _ _ _ _ _ _ _ _Y-'E:..::S-< DIAGC=1?
~
YES
(CR17)
NUDIAG= 1?>Nc:.:0"--_ _ _ _ _ _-.
(CR1D)
Poll CR1 for 0 in
NUDIAG for test
complete, process
results, then clear
DIAGC in CR1 to exit or
set NUDIAG and NEXT
TEST to continue
diagnostics.
29
POWER UP
ITM INTERRUPT
DIAGNOSTIC
Figure 1.3
NETWORK
FUNCTIONAL STATES
match. The same is true for registers D and 6 and
memory location N + 1.
Loop-Back Test
The host can test the WD2840 transmitter and receiver
logic by using the Loop Test.
1.4.1 SELF DIAGNOSTICS
Internal Ram and Interrupt Test
There are nine eight bit registers in the WD2840
which are not directly accessable by the users CPU.
This test provides a means to check those registers
and the interrupt register. The contents of register A
are placed into the interrupt register and five even
internal registers, and the contents of register B in
four odd internal registers. The nine registers are
then added together without carry and the result is
placed in registers 2, 5, 6,7.
There are two Loop Tests available for diagnostic purposes - internal and external.
Use the following procedure to initiate the RAM test:
1. Enter diagnostic mode.
2. Set up registers A and B
(CR12)
LOOPT
(CR03)
1LOOP
0
0
0
1
1
0
1
1
DEFINITION
Not in Loop Test
Do not use in network mode
External loop
Internal loop
When using the external loop the Interface or modem
must have the necessary logic to tie TD to RD and TC
to RC.
3. Set RAMT.
4. Set NUDIAG (can be set with RAMT bit together).
5. Wait for NUDIAG to be cleared.
Use the following procedure to run the loop test.
6. Read registers 2, 5,6, 7. Clear RAMT.
Note that the setting of any bit in the interrupt
register while NOINT is clear will generate a hardware interrupt (INTR , pin 43 goes true).
1, Set up a 256 byte transmit buffer with the data pattern to be transmitted.
2, Initialize a 256 byte receive buffer with all "ODs" or
"FFs."
1.4_2 SYSTEM DIAGNOSTICS
3, Load register A (MSB) and B (LSB) with the address
of the transmit buffer.
4. Load register C (MSB) and D (LSB) with the address
of the receive buffer.
5. Load register 0 for Internal or External Loop.
6, Load register 1 for diagnostic & loop. (85H)
DMATest
This test verifies proper operation of the DMA subsystem by reading the value from a register and
writing it into the user memory. The test continues by
reading the value from the same location in memory
and writing it into another register.
7. Refer to Diagnostic State Flow Chart.
NOTE:
If this test frame is allowed onto the network, transmission collisions may occur. Further, the first three
bytes of the transmit buffers will be interpreted as
TC, DA and SA, respectively, by the other stations.
Therefore in case this test is initiated while this node
is in the logical ring, care should be taken for
choosing these three values for external loop-back
test.
For proper operation of the internal loop-back test the
CTS and SO pins of the WD2840 should be either tied
to ground or tied to RTS pin of the WD2840.
The value is read from register C. Using the transmitter DMA sub-system, it is written into memory location addressed by register A and B (location N;
register A is the MSB). The receiver DMA sub-system
is used and contents of the same address is read and
it is stored into the register 7. Next the receiver dma
is used and the contents from register D is written
into location N + 1. The transmitter dma reads the
value from location N + 1 and stores it into register 6.
It is the host's responsibility to check if the contents
of registers C and register 7 and memory location N
30
several circumstances. The NAK prevents the
transmitting node from wasting bandwidth retrying
indiscriminately, and further, lends visibility to individual network node problems. The NAK includes a
reason code which is available to the transmitter's
software (via the TFSB).
Each data frame to be transmitted can be specifically
marked (via the FCB) by the host to require an
ACKINAK response from the receiving WD2840. In
the absence of errors, an acknowledge (ACK) frame
will be returned to the transmitter as confirmation.
However, several circumstances cause a Negative
Acknowledge (NAK) to be returned:
1.4.3 NETWORK DIAGNOSTICS
Duplicate Station Detection
Duplicate stations (more than one station with the
same address) can result from the faulty program·
ming of internal register MA (due to wrong address
switch settings on the user's device, for example).
This is expected to occur often enough to warrant the
addition of a detection algorithm in the users
WD2840 initialization procedure.
After initialization, the user should place the WD2840
in the network mode with TXEN off and ITOKON on.
This will cause the WD2840 to generate an ITOK inter·
rupt each time a token is passed to its address (MA).
The host must provide the timeout algorithm which
should be greater than the maximum time for the
network to pass the token around the ring twice. Checking twice eliminates the possibility that the Network is
in the scan mode and sending tokens to non-existing
stations.
1. Insufficient buffer space
2. Receiver not enabled (RXEN - CROS cleared)
3. Receiver overrun
4. Frame exceeded 16 buffers in length
This information is placed in the transmitted
frames's FSB. See section 2.1.2 for more details on
the Transmit Frame Status Byte (TFSB).
It is useful to note that this constraint requiring each
node which is participating in the network logical
ring to have a unique address does not extend to
nodes which are "listening" but not "in the ring." It
might be useful to a network designer to have groups
of receive only nodes which have the same node
address but do not participate in the network token
passing (see GIRING . CR13). Data frames transmitted to such clusters must not request acknowledgement since all nodes in the cluster would
simultaneously respond.
2.0 INTERFACES
There are two interfaces to the WD2840: the host
computer side, and the network side. The network
side is conventional from an electrical point of view,
the WD2840 performs all logical functions required to
ensure communications capability on broadcast
media (such as coax or RF).
The host interface involves two separate functional
interfaces: the status/control registers described in
section one, and a DMA interface that is described in
the following subsection.
Copy Mode
The COPY Mode is selected by setting the COPY
control bit (CR02). Normally the WD2840 receives
(DMA's into the receive buffer chain) data frames only
if they contain tlie general broadcast destination
address or if they are specifically addressed to the
WD2840. This occurs when the frame's destination
address (DA) matches the WD2840 my address (MA,
set by the host).
However, when COPY mode is selected data frames
which are specifically addressed to other nodes will
be treated as broadcast frames by this node. The
COpy mode allows a specific node to "eavesdrop" on
data frame traffic on the network.
2.1 HOST
The WD2840 uses a complex memory buffer architec·
ture allowing it to respond in real time to its network
obligations (e.g., to meet network data rate and processing delay requirements). These memory struc·
tures are managed cooperatively by the host and the
WD2840.
Memory management functions requiring real time
response (e.g., traversing chains) are completely
handled by the WD2840. Other important, but not
time critical operations are the responsibility of the
host software (such as removing used buffers from
the transmit chain).
All memory references by the WD2840 are pointed to
by memory locations (and internal registers) initially
defined and set up by the host software. Initial values
and memory based registers are grouped together
and called the WD2840 Control Block.
Nak Response
The WD2840 sends negative acknowledgements
(NAK's) on response to received frames under
31
r
it is expected that the host will maintain both a FIRST
and a LAST address for each chain. On transition into
Network State, the chain origin information in the
WD2840 control block is the same as FIRST. In fact,
since the WD2840 does not change these control
block entries, they can be maintained directly as
FIRST by the host. An explicit LAST could be placed
In an extended control block section.
The WD2840 "follows" the linked buffer chains by
maintaining a NEXT address internally for each
chain. This NEXT address can be in one of two
states: 1) it can be the address of the next buffer in
the chain, or 2) at the chain end (zero link), it can be
the address of the buffer containing the zero link. The
WD2840 uses a status bit for each chain, NXTRO
(receive) and NXnO (transmit), to differentiate the
two states. When set they indicate the WD2840 chain
NEXT address is in state 1 above; when clear they
indicate state 2 above. This is an important distinction since it indicates whether the last buffer posted
in a chain can be removed by the host (because the
WD2840 has advanced to the buffer beyond) or must
be left until the chain can be extended so the
WD2840 can advance.
The host software monitors the progress of the NEXT
pOinter, and updates FIRST and LAST as it adds (and
removes) buffers to (from) the chains as required. The
WD2840 provides Interrupt Events (see IRO) and
NXTRO, NXnO status bits to indicate when it advances along the two chains and exactly what state
its NEXT address registers are in. The operation of
these chains will be explained by example in later
sections.
The location of this control block is written into the
registers CBPH and CBPL anytime the WD2840 i~ in
Isolate State. This control block has the following
structure:
CBP- +0
NXTR(H)
+1
NXTR (L)
+2
NXn(H)
+3
NXn(L)
+4
BSIZE
+5
+6
EVTO
EVT1
+F
EVT10
Receive Buffer Chain
(MSByte)
Receive Buffer Chain
(LSByte)
Transmit Buffer Chain
(MSByte)
Transmit Buffer Chain
(LSByte)
Buffer Size / 16 (O-F = 641024 bytes)
Eleven separate Event
Counters, see section
2.1.1 for details
As the WD2840 transitions to Network State, it reads
and uses the first five bytes of the control block. The
remaining eleven bytes of event counters are accessed by the WD2840 only when each specific event
condition occurs.
Either the Receive (NXTR) or Transmit (NXTl) chain
entries in the control block may initially be zero; in
such a case the WD2840 expects the chain to be
extended by the host's changing the zero link field in
the control block. Thereafter any such zero link would
be in a buffer.
The WD2840 uses constant size buffers; their length
is set by the value in location BSIZE. The buffer size
is indicated by a 4-bit count in the least significant 4
bits of the BSIZE byte in the WD2840 control block.
The buffer sizes available are multiples of 64;
(BSIZE + 1) 64 is the buffer size used by the WD2840.
Thus a BSIZE range of 0-15 corresponds to actual
buffer sizes of 64 through 1024 bytes. This buffer
length is inclusive of control bytes and buffer link
pointers.
"Deadly Embrace" Prevention
A "Deadly Embrace" can occur when two processors
reach a state where each is waiting for the other. In
this case, the two processors are the user's CPU and
the micro-controller inside the WD2840. Therefore, to
prevent the "deadly embrace," the following rule is
obeyed by the WD2840 and should also be obeyed by
the user's CPU. This rule applies to the WD2840
memory registers and to the I/O registers. The Event
Counters are an exception to this rule.
Rule:
If a bit is set by the CPU, it will not be set by the
WD2840 and vice versa. If a bit is cleared by the
WD2840: it will not be cleared by the CPU, and vice
versa.
As an example, the NEWNA (CR10) control bit is only
set by the host and is only cleared by the WD2840.
The WD2840 includes a chained-block feature which
allows the user more efficient use of memory, particularly in situations where the maximum packet
size is much larger than the average packet size. One
or up to 16 buffers may make up a frame but a buffer
may not contain more than one frame.
Byte counters are associated with each frame (at the
memory interface, not actually transmitted within the
frame) so that frames on the network need not be
integer multiples of buffers. The byte counters include
all buffer management overhead. Therefore, a frame
consisting of 100 transmitted data bytes, occupying two
64-byte buffers, would have a byte count of 110 (six
bytes per frame + 2 bytes per buffer).
Dual DMA
The WD2840 may, for effiCiency, interleave frame data
fetch/store operations with fetches and stores of
pointers and flags in memory. In all cases, operation
sequencing is such as to prevent deadlocks and
ambiguities between the WD2840 and software.
Since the WD2840 receive and transmit buffer chains
are linked lists (see section 2.1.2 and 2.1.3) and are
"followed" by the WD2840 but managed by the host;
32
2.1.1 EVENT COUNTERS
Several non-fatal logical events are tabulated by the
WD2840 and made visible to the host via memory
based event counters (see WD2840 control block
organization for specific locations). The WD2840 will
increment each counter at the occurance of the
specified event. Note that the WD2840 will not increment past 255. The host has the responsibility of
initializing each counter.
COUNTER
DESCRIPTION
EVTO
"Set scan mode" frame received from the network. The NA register was redefined to
MA + 1 at the time.
EVT1
Transmission error first attempt, second try successful. Can only occur for frames
requiring an acknowledgement. It indicates no response was received for the first
transmission; however, the second transmission was either ACK'ed or NAK'ed.
Transmission error. Attempt aborted due to either transmitter underrun or frame
length exceeding 16 buffers.
..
!
EVT2
EVT3
EVT4
EVT5
TimerTD (network dead) expired.
Access Control Frame Reception Error. A one or two byte supervisory frame
(ACKINAK, Token Pass, Scan Mode) has been received in error. This may be due to an
FCS error, frame abort, or carrier loss detection.
Data Frame Reception Error. An incoming data frame was incorrectly received due to
an FCS error, frame abort, carrier loss detection, or receiving a data frame when expecting an ACKINAK frame.
EVT6
NAK sent. Can occur for any of the following reasons:
1. Insufficient buffers in chain
2. Receiver not enabled (RXEN clear)
3. Receiver overrun
4. Frame length exceeded 16 buffers
EVT7
Invalid frame received. Caused by the detection of certain abnormal network conditions such as receiving an ACKINAK frame when not expecting one, receiving a
Scan mode frame when expecting an ACKINAK frame, or receiving an invalid
supervisory frame.
EVT8
Duplicate token detected. This counter will be incremented when the WD2840
determines that more than one token exists in the logical ring. This happens if a
token pass is received when the WD2840 already has the token, or a data frame is
received when the WD2840 is waiting for an acknowledgement frame.
Not used.
Duplicate node address. This counter will be incremented when a data frame being
DMA'd into memory has a source address (SA) equal to the WD2840 node address
(MA). This counter when used with COPY mode (CR02) is one way for detecting other
nodes with the same node number(MA).
EVT9
EVT10
2.1.2 TRANSMIT MEMORY INTERFACE
When the token is received, data transmission is
enabled (TXEN - CR06 and TXDEN - CRO? both set),
and if the access hold-off counter has reached its
limit, the WD2840 will determine whether any data
frames are pending in the transmit chain. If so, it will
transmit the first data frame In the chain. Otherwise
the token will be passed. A given data frame will be
the last frame transmitted for this token if any of
several conditions occur:
4. The running frame counter has reached its limit
(TXLl).
5. No further frames are pending in the transmit
chain.
If any of the first four reasons above are true a token
pass will occur. If the last frame does not require an
acknowledgement, the WD2840 will piggyback the
token pass if that is permitted (CR16). If the token
cannot be piggybacked or if the last frame transmitted is the last frame pending (condition #5 above),
an explicit token pass will occur. A piggyback token
will not occur for the last pending frame because, for
the general multiple buffer case, it is not known to be
the last pending frame until after the transmission is
complete.
1. ISOL (CROO) is set indicating the host has
requested a transition to Isolate State.
2. TXDEN (CRO?) is clear indicating the host has
changed data frame transmission rights.
3. The frame FSB indicates this frame should be the
last transmitted for this token.
33
Examples: Find L given NO
The W02840 will read and evaluate the address of the
next frame at two specific points in time:
o
2. When the token is received and data frame
transmission is permitted.
BK = 64
If a non·zero frame address is found at time 1 above,
it is kept and used without being re·read at time 2
above. However, if no pending frame is found at time
1, this is noted with the NXTTO flag clear a~d the
chain re·inspected on each occurrence of time 2
above.
BK = 128
As frame transmission commences, the W02840
reads the address of the next buffer, the frame
control byte, (FCB) and the frame length. It then
starts reading bytes from the buffer and sending
them until the frame length count or the end of the
buffer is reached. The new buffer is read and data
transmitted as before. (See Figure 2.1)
BK = 64
Simplified formula for LENGTH:
LENGTH = /I of data bytes + 2 link bytes per buffer
+ 6 overhead constants per frame.
BK = 128
Example #1
= 8 (0010H in LENGTH field)
=
8
9
64
67
128
131
120
121
246
247
128
131
256
259
1 bufr
2 bufrs
3 bufrs
1 bufr
2 bufrs
3 bufrs
L
#B's
8
9
64
67
128
131
1
1
1
2
2
3
1
56
57
118
119
L
#B's
NO
128
131
256
258*
259
1
2
2
3
3
120
121
246
246
247
NO
o
"NOTE:
Case corresponds to buffer end and frame end on
same byte ... extra buffer consumed.
implies one buffer is used for this frame (64 bytes)
two link + six overhead, no data.
Example #2
LENGTH
1
56
57
118
119
Find #B's, NO given L
The frame length provided in the LENGTH field must
be the sum of the overhead bytes and number of data
bytes (see Fig. 2.1).
LENGTH
L
NO
1. At the end of the prior frame, even if the prior
frame is the last to be transmitted for this token.
# of data bytes + 2 link bytes per buffer
+ 6 overhead constants per frame.
Programmed buffer size = 64 bytes per buffer. Two
buffers are used in this frame for a total of four link
bytes (2 per buffer), six overhead, and 57 data bytes.
The General Formula for LENGTH
WHERE
NO = # of data bytes (max 4095)
6 = Overhead Constant per frame (FSB, FCB,
LENGTH (H), LENGTH (L), OA, SA)
When the frame length is finally reached, the
W02840 pauses if an acknowledgement has been
requested. The frame status byte (FSB) is updated
when the frame is completed; its posting indicates
frame completion and gives information about the
success or failure of the frame transmission. At
frame completion, the W02840 attempts to advance
along the transmission chain to identify the next
frame regardless of whether it will be transmitted
with this token or later.
The host may add frames to the end of the transmit
chain at any time by changing the zero link in the last
buffer. Also buffers of all posted frames up to but
NOT including the last buffer of the most recently
posted, may be arbitrarily removed from the chain.
The last posted frame (more specifically,. the last
buffer of the last frame) may only be removed and
reused if NXTTO is set. This indicates that the
W02840 has advanced its NEXT address to the next
frame but that its transmission has not been com·
pleted (in fact, perhaps not even started).
BK = B SIZE in bytes (64, 128, etc.) a constant
preprogrammed into the W02840 on 64
byte boundaries to a max of 1024 bytes.
GIVEN NO
No + 5
L = NO + 8 + 2* TRUNC BK _ 2
GIVEN L
L - 1
#B's = 1 + TRUNC
-----sK
NOTE:
The W02840 checks only the most significant byte of
the link field for zero link detection. This has the
following implications:
1. When writing into a zero link field, the host must
write the LSB of the new link field first, followed by
the corresponding MSB.
NO = L - 6 - 2 (#B's)
NOTE:
The expression for NO fails for values of L = BK + 1.
This is okay since the 2840 doesn't generate such
values.
34
2. All buffers must have a starting address greater
than or equal to Hex '0100'.
TRANSMIT FRAME STATUS BYTE (WRITIEN BY WD2840)
BIT#
Name
I
7
I
DONE
I
6
I
J WIRING I
5
X
I
I
4
X
I
I
NAME
BIT
I
3
I
SELF
2
VAL2
--
1
VAL1
--
0
VALO
1,
DESCRIPTION
7
DONE
Set to guarantee a non·zero value for the posted FSB.
6
WIRING
Value of the corresponding bit in received ACK frame.
5·4
3
SELF
2·0
VAL
Reserved.
When set, indicates the ACKINAK code appears in the value field (bit 2·0) of this
FSB is assigned by the WD2840 transmitter routine. When clear, indicates value
resulted from ACKINAK code from receiving station.
An encoded field whose interpretation depends upon the SELF flag (bit 3) in this
FSB.
a. SELF clear
000 - No receive error (= ACK when DON E is set).
001 - Insufficent buffers for frame.
o 1 0 - Receiver not enabled at frame start.
o 1 1 - Receiver over·run.
1 0 0 - Frame exceeded 16 receive buffers.
b. SELF set
000 - No transmit error.
o 0 1 - Transmission failed after retry.
o 1 0 - Transmission under·run.
o 1 1 - Premature end of chain.
1 0 0 - Transmission frame exceeded 16 buffers.
Transmit Frame Status and Control Bytes
Each frame has two bytes reserved, one for host
control information needed by the WD2840, the other
for status information posted by the WD2840 at frame
transmission completion. The frame control byte
(FCB) is only read by the WD2840, never changed; the
frame status byte (FSB), is written (posted) by the
WD2840 with no regard for its prior contents. On
completion, the FSB value will always be non·zero; it
is important that the host zero the FSB byte in order
to be able to recognize a posted frame.
NOTE:
Specifically note in Figure 2.1 that the first buffer of
each frame has a different structure than any over·
flow buffers for that frame. In particular, each frame
has only one set of FSB, FCB, and LENGTH fields
regardless of the number of buffers required by the
frame.
TRANSMIT FRAME CONTROL BYTE (WRITIEN BY HOST)
BIT #
Name
I
I
7
WACK
I
6
I
5
I
I FCBLF I TRANSP I
4
X
I
I
3
X
I
I
2
X
1
X
0
X
BIT
NAME
DESCRIPTION
7
WACK
Wait for Acknowledgement. Instructs the WD2840 to wait for an ACKINAK
response from the receiver for this particular frame only. The token control (TC)
byte in the frame is automatically set to cause the destination node to respond.
This bit must NOT be set if the frame uses the broadcast destination address.
Inadvertently doing so will cause the frame to be posted "Transmission failed, due
to max retries."
6
FCBLF
Last Frame. This bit will cause the WD2840 to pass the token either piggybacked
with this frame (if possible) or explicitly after the frame transmission completes.
5
TRANSP
Transparent Frame. This bit will cause the WD2840 to interpret the buffer contents
to be the exact sequence of bytes to be transmitted. The normal token control (TC)
byte and source address (SA) byte generation is suppressed. Note that for a non·
transparent data frame the TC byte must NOT appear in the buffer.
4·0
-
Reserved.
35
NXTT(H)
-- -
--
NXTT(L)
INTERNAL REGISTERS
LINK (H)
-----LINK (L)
..
LINK (H)
-----LlNK(L)
-
LINK (H)
.... ---.. -----LINK (L)
FSB
--_ ..
0
---- XX
END
OF
CHAIN
FSB
--- ----
-------
FCB
FCB
LENGTH (H)
LENGTH (H)
------
------
LENGTH (L)
LENGTH (L)
DA
DA
SA
SA
D
A
D
A
T
T
A
A
TRANSMITTED BUFFERS, TO BE REFILLED
AND RE·QUEUED BY THE HOST
TO BE TRANSMITTED
Figure 2.1 TRANSMIT BUFFER CHAIN,
2. Current buffer capacity exhausted. If 16 buffers
have been used for the current frame, an event
occurs with the frame being dropped and the
chain reset. Otherwise the WD2840 attempts to
advance to the next buffer in the receiver buffer
chain. The frame data will be continued in this
subsequent buffer. If the end of the receiver
buffer chain is reached an event counter is
incremented, the frame is dropped, and the
chain reset.
2.1.3 Receive Memory Interface
After the third byte of an incoming data frame is
detected, the WD2840 will begin to place frame data
into memory if several conditions are satisfied:
1. Receiver Enabled (RXEN·CR05 set).
2. There is an available buffer in the receive buffer
chain.
3. The frame is addressed to this node specifically,
it is a broadcast frame, or COpy mode has been
selected by the host.
As the frame continues, it may completely fill its
buffer. If this happens the WD2840 reads and in·
spects the link field of the current buffer. If this link is
zero, an error occurs and the receive chain is reset to
reuse from the first buffer used by the dropped frame.
However, if another buffer is available, the incoming
frame is continued beginning in the third byte of that
buffer. This continues until one of several things
happen:
1. Receiver overrun. The WD2840 has a four byte
FIFO to buffer incoming frame data; however, if
the host DMA responds too slowly a receiver
overrun will occur. If this happens an event
counter is incremented, the frame is dropped,
and the receiver buffer chain is reset to reuse
buffers of the dropped frame.
3. Frame ends. If the FCS is not correct an event
counter is incremented, the frame is dropped,
and the chain is reset. If correct however, the
frame length is placed in the LENGTH field and
the Frame Status Byte (FSB) is posted "done, no
error."
If the frame is addressed to this node and indicates
an acknowledgement is required (TC 255), whether
or not an error occurs, the WD2840 responds with an
ACK/NAK supervisory frame indicating either
success or failure. In case of receiver over·run, bad
FCS, and SA MA acknowledgement request will be
ignored. (See section 1.4.3 for detai Is)
=
=
It is the host's responsibility to ensure that buffers
are available, initialized (FSB zero'ed), and attached
to the end of the receive buffer chain.
36
RECEIVE FRAME STATUS BYTE (WRITTEN BY WD2840)
BIT
NAME
7
DONE
2
x
x
o
x
x
DESCRIPTION
Set to indicate the frame reception is complete.
Reserved.
-
6-0
3
RECEIVE FRAME CONTROL BYTE (WRITTEN BY HOST)
BITH
7
6
5
4
3
2
Name
X
X
X
X
X
X
BIT
NAME
7-0
0
X
X
DESCRIPTION
IRe"."ve.
2.2 MODEM INTERFACE
The modem interface is the conventional half duplex
NRZ type with separate data and clock (Figure ~
When the WD2840 desires to transmit, it asserts RTS
and awaits CTS. RTS is generally used to enable the
modem transmitter. After a system dependent
preamble is generated, the modem asserts CTS
which allows the WD2840 to ~n the actual transmission of the frame. (Note: CTS may be asserted
permanently if the transmission system does not
need to generate a preamble).
The SQ input is used on receive to indicate a valid
carrier. If this term is negated anytime during a
receive message, the WD2840 will presume the
message is in error and treat it as an abort. This
signal is used to augment message integrity beyond
that of the CRC by allowing a modem to detect and
report low level faults (such as out·of-frequency
carrier or missing clock).
r'"
NXTR(H)
... - -
--
NXTR(L)
INTERNAL REGISTERS
LlNK(H)
-----LlNK(L)
LlNK(H)
• -----LlNK(L)
FSB
------ -----LlNK(H)
-----LlNK(L)
--- ---FeB
LENGTH(H)
------
LENGTH(L)
DA
SA
D
A
T
A
FILLED BUFFERS, TO BE EVALUATED BY THE HOST
Figure 2_2
AVAILABLE FORWD2840 USE
RECEIVE BUFFER CHAIN
37
0
----xx
END
OF
CHAIN
I
I
I
fC
RC
I
TD
DATAl
CLOCK
ENCODER
TRANSMISSION
f
1..-: .......
MEh~UM
DATAl
CLOCK
ENCODER
RD
SO
I
I
I
I
I
I
I
I
RTS
I
I
I
CTS
I
I
OPTIONAL
PREAMBLE
DELAY
TRANSMIT
Figure 2.3
I
I
I
I
RECEIVE
CONCEPTUAL MODEM
3.0 NETWORK PROTOCOL
To enable operation on a broadcast medium without
the need for a central controller performing device
polling, the WD2840 implements a media access
protocol. The particular access protocol designed
into the WD2840 prevents self·induced transmission
collisions and ensures a fair and guaranteed
distribution of transmission time among attached
controllers. (See Appendix A for Protocol flowcharts.)
Both functions are parameterized, allowing tuning
and optimization by the user to his unique ap·
plication. These parameters may be adjusted in real
time by the user's software, allowing a dynamic
network, responsive to constantly changing
requirements.
The two functions, access control and data transmis·
sion, function simultaneously though independently.
Thus they are described separately as subprotocols
for clarity.
This design·out of collisions allows the WD2840 a
greatly expanded selection of transmission media,
since no physical characteristics of a particular
medium are relied upon for proper network operation.
Another benefit of this lack of collisions is the
visibility of network faults. If a collision is detected, it
is treated consistently in a error recovery mode by
the WD2840 and is also unambiguously visible to
service personnel as a fault.
Secondly, the WD2840 can ensure that a transmitted
message was correctly received and buffered by
requiring acknowledgement of its receipt. This is
sometimes called "acknowledging datagrams"
where the sender awaits a predefined period after a
frame is sent for a reply from its destination. With
this method, no sequence counters nor multi·frame
retransmission buffering is required. The scheme is
efficient since local network applications such as the
WD2840 address do not encounter extremely long
transmission delays (such as satellite links) as in
conventional data networks (such as X.25).
3.1 Data Transmission
The data transmission cycle is entered after the
token has been received and data transmission rights
validated (see section 3.2 "access method"). The
WD2840 determines if there is a frame to be sent and,
if not, simply sends the token to the next station.
If something is queued for transmit, the WD2840
DMA's it from memory and sends it. After the
complete frame has been sent, the WACK (Wait for
ACK) bit is tested in the TFSB (Transmit Frame Status
Byte). If set, the WD2840 waits for, and expects, an
acknowledgement from the frames recipient. A timer
(TA) is started. In the normal case, the ACK is
received before TA expires which causes the WD2840
to send the next frame queued, repeating this
procedure. Thus, the WD2840 sends multiple frames
to various destinations until the transmit queue is
emptied or a programmed limit (register TXLl) is
exceeded.
38
----,
I
I
I
I
MEDIUM
I
I
I
I
1_ _ _ _
Figure 3.1
MA
=
Node (" My") Address
NA = Next (Successor) Address
.. = does not apply
TOKEN PASSING ON A LOGICAL RING
In the event TA expires, the frame is re-transmitted
once. (Note: it is the responsibility of higher level
protocol operating in the host to protect against the
possibility of duplicate frame reception.) If TA expires
again, usually indicating the destination node is offline, the FSB is updated to reflect the unsuccessful
transmission, interrupt bit ITA is set, and the frame is
skipped.
A frame is also skipped and tagged if the destination
station sends a NAK, indicating it cannot presently
process the frame.
token is held at this instant by station 4 (the station
whose MA register = 4).
When station 4 is ready to pass his access right on,
he sends a message to the station number called out
in his intemal register NA, in this case 11. The
message, and thus the token, are received by station
11 who can now transmit its message(s). When
station 11 is ready to pass the token, it sends a
message to station 19, as directed by its intemal
register NA and the cycle continues, in a circular
fashion, from station 4 to 11 to 19 to 54 to 4 ...
Notice that the station numbers need not be contiguous. This relatively arbitrary station numbering (in the
example) poses no inefficiency to the access method.
The value of this is the ability to add and remove stations (re-configure) on the network without re-arranging
everyone elses addresses, (See section 3,2,2 for an
example),
TRANSMISSION OF ABORT
An ABORT is transmitted by the WD2840 to terminate a frame in such a manner that the receiving
station will ignore the frame. An ABORT is sent when
there is a Transmitter Under-Run. The abort sequence
is a zero, followed by seven ones, after which RTS is
set false.
In this way, the token is passed from one station to
the next in a logical ring.
3.2 ACCESS METHOD
The WD2840 network access method is based on the
use of tokens, the specific granting of transmission
rights passed from station to station. At any given
time, exactly one station has the right to transmit
(this right is called the token) and is obligated to pass
it on when finished with it.
This can be clarified by referring to Figure 3.1. We
assume in this figure that the network has already
been initialized (meaning that the linkages in the
access ring have already been established) and the
3.2.1 ACCESS INITIALIZATION/ERROR RECOVERY
When the WD2840 is commanded into Network
State, the Next Address Request (NAR) register and
the NEWNA (CR10) flag must be used to define the
Next Address (NA) register. When it is necessary to
pass the token, it is passed to the current node
number in register NA. If station NA is not on-line,
determined by its lack of response, station NA + 1 is
tried. This process continues until a station is found
39
which does respond. The responding station
number is written into register NA so that this
scanning procedure need not be repeated on subsequent access cycles.
NOTE: 1. Node numbers 0 and 255 are reserved and
cannot be used. Consequently scanning
occurs circularly in the range 1-254.
2. During Scan mode token passing to each
node is only tried once.
3.2.3 ADDING STATIONS
There are three primary methods by which a station
can be added to a network. The first is a distributed
method, in which each station in the network can poll
for new statiohs in the gap between its address and the
next address (between MA and NA). Second is a centralized method, in which an individual station designated by the network architect can interrogate the
entire address space seeking a new station desiring
INRING. The third - central scan - is a simpler (from
the host point of view), centralized method in which a
station can send a global frame causing all the on-line
TACs to reset their next address register. This causes
each TAC to poll its address space at its next tokenpass attempt. Each method has advantages and
disadvantages.
Distributed Method
The distributed method does not rely on a specific station. Thus, there are no problems or efforts spent
selecting the administrator, nor is there any concern
about backup administrators. In the distributive
method, each station has the same responsibility to
allow new access members as other stations. This
method is the most host intensive and requires each
station to maintain a timer (that can be configuration
set as to its value) as to how often it should poll its gap
for new stations.
For example, assume the timer in each station is 5 sec.
and that station 4's timer has expired (Fig. 3.2.3.1). The
host attached to station 4 notes that the next address
register (NA in the TAC) is set to 11, which indicates that
a new station might be added to the network as station
number 5, 6, 7, 8, 9, or 10.
The host queues a frame into the TAC transmit chain,
polling station 5. This frame will be sent by 4 with an
acknowledgement requested from 5. If 5 is present it
responds; otherwise, the TAC aborts its attempt after
time TA. The TAC marks the result on the frame in the
host memory space and proceeds with other tasks.
After this exchange, the host, at its leisure, checks the
transmit status of the frame. The host sees that the
frame acknowledgement timed out, meaning that station 5 has not been added to the network, or that station
5 is on the network and whether the request INRING is
set in the network code field. In either case, the host
takes appropriate action. If the desired INRING bit is
set, station 4 changes its NA register to 5, allowing its
next token to be passed to 5. This action puts station 5
in the ring.
Depending all an application's sophistication, a control
message can be sent to station 5. That message says,
"Your successor is X." In this case, X = 11, so that 5 is
not forced to poll for its successor. In any case, 4
updates its next address register to 5 and does not
need to go through this distributive polling cycle again
because there is no gap between 5's address and the
next address; there is no possibility that a new station
can be inserted between addresses 4 and 5. If 5 didn't
respond to 4's poll, station 4 updates its poll counter so
that the next time that the poll timer times out, station 6
will be tried.
Anytime a station cannot successfully pass a token
within two attempts, register NA is updated to
NA + 1, and a new "next" station is searched for. The
result is the rem.oval of non-responding station(s)
from the access nng. An interrupt (INS) is generated
indicating a network exception caused a change to
NA.
The above description covers network recovery from
station failure and purposeful removal of stations
during on-line network operation. Setting stations in
the scan mode can also be accomplished by sending
control frames (a Scan frame redefines NA = MA + 1)
over the network. The control frame may be directed
to ~ single station, or all stations simultaneously
(using the broadcast address). It is this scanning for
new stations that permits on line addition to the
access ring.
NOTE:
The policy of the SCAN frame is redefined by the
user software as required by the application. For
example: in a process control environment where
stations are not often added while the network is in
use, this procedure would be initiated rarely if at all.
3_2.2 REMOVING A STATION
There are two ways a station can be removed from
the access ring: non-response due to station failure
and non-response due to host commanded transition
to the Isolate State. Both are treated identically from
a network point of view.
Referring to Figure 3.1, assume that station 19 is
removed from the network (either physically or
logically). In this example, station 11 would detect a
network fault when trying to pass the token to 19
(time TA would expire since station 19 will not
respond). Station 11 detects this and finds the next
station in the access ring by using the "scan" function (similar to initialization). The next attempt at
passing the token would be to station 20, register
NA+1.
By starting the token ring recovery procedure at the
intended station plus one (station 20) rather than
MA + 1 (station 12) as is done in initialization,
recovery delays are minimized (since fewer stations
are tested for presence, 8 less in this example).
The next station found would be number 54 in the
example which station 11 writes into his register NA
(now "patching out" dead station 19). The next time
station 11 is finished with the token, it directly sends
it to 54, making the sequence now 11 to 54 to 4 to 11
t054 ...
40
When the polling station determines that a station has
been added, it must place the new station in the access
ring. For example, station 4 is the centralized station
doing all the polling (Fig. 3.2.3.2), and it discovers that
station 27 has recently been added. Station 4 knows
this because station 27 now responds to a first-time
poll, and because its status bit is set, indicating that it
wants to be added to the ring. (Some stations may be
receive only, never desiring the right to initiate transmissions.) Station 4 sends a high-level message to the
software in station 19, telling it to change its next
address register to 27. This message can also prompt
station 19 to tell 27 its next address register should be
54. This gets confusing, but it is all done with high-level
software. These tasks are not real time and are quite
efficient from the network point of view.
Fig. 3.2.3.1 Distributed polling. Each host polls the
gap in its address space for the possible addition of new
stations. The host internal poll timer and poll counter set
the polling rate and range as desired.
Station 4, the administrator, need not create and maintain a table of active stations on the network because
the poll response returns three pieces of information.
As node 4 polls the stations on the network, it finds out
(a) that the polled station does not respond at all, as it
would if it polled station 12 in Fig. 3.2.3.2 (b) that the station is already part of the network an is already in the
ring or is receive only, as it would if station 4 happened
to poll station 11 or 19; and (c) whether the station is
attached to the network, is alive and wants to be in
the ring, as is the case with a poll to 27. These indications are conveyed by a combination of status bits sent
back by the acknowledge frame. This acknowledge
frame and status information are transferred at a TAC
device level, so a host is not concerned with whether its
station wants to be in the ring. The host simply sets up
the proper bits in the control registers; the bits are
relayed automatically by the TAC. Thus, with a simple
algorithm, an administrative station can poll the entire
network address range and know the network's exact
membership and status.
If node 6 responds, its desired INRING bit is tested as
above. If 6 does not respond, the host will queue a poll
to station 7 the next time its poll timer expires. This continues until the host completes 10, when the cycle goes
back to 5 and repeats. In this example, with a gap of 6
stations (between 4 and 11), and with a 5-sec. clock, a
new node can be added within 30 sec.
In the centralized station-addition method, a single station can poll the entire address space, seeking a new
station that desires INRING. One reason for centralizing this function might be the more careful control that
can be placed in a network. There can also be optimizations. For example, the central polling station can keep
track of the stations that already exist and, therefore,
bypass some address ranges. A polling station may
know the network will never have more than, say, 75
stations, In the example of Fig. 3.2.3.2, when station 4
starts polling, it polls only to address 75 before resetting to zero. This works like the distributed method
except that a single station does all the work.
Central Scan
Central scan is the simplest method of adding stations
to a network. It involves sending a global frame to all
21nring desired
'-----<
>--+-----'
3 Set NA to 27
Fig. 3.2.3.2 Central polling. A single station - in this
case, station 4 - dubbed "the administrator, " can be
charged with all polling tasks. This simplifies the software in the other stations and centralizes network
control.
FIG. 3.2.3.3 Central scan request. A special command can be sent by any station causing all attached
TACs to set their NA register to the address of the next
possible node. This causes each TAC to poll without the
help of the host.
41
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c
N
CO
o-'="
stations on the network, which forces each to update its
own next address register to its station address plus
one (NA = MA + 1). Assume station 4 is the centralized station and sends the scan command frame (Fig.
3.2.3.3). Station 11, upon receiving it, automatically
sets its next address register to 12 (the TAC does this;
the host is not involved but is notified of the situation).
Also, station 19 sets its next address register to 20, and
station 54 sets its NA register to 55.
The trade-off of all these methods is the software complexity distribution. If a TAC user assumes more
responsibility, providing more intelligence distributed
in the software, the system can be more sophisticated
in handling new stations. If a user wants the TAC to handle this task itself, saving host software development,
he pays only slightly in inefficiency. TAC gives the user
an option.
3.2.4 INTERACTION OF THE SUB-PROTOCOLS
The result of this is a round of polling at the TAC level.
Station 11, on completing its use of the token, tries to
send it to 12. The token to station 12 times out because
12 is not present. Station 11 reclaims the token trying to
send it to 13 and so on, causing 11 to poll for station
addition. The drawback of this is the huge time disruption incurred by the simultaneous polling.
It is not required that station 4 send this scan control
frame to all stations at the same time. If it is known that
station 11 exists in the network and that a station may
be trying to add into the network after station 11 in the
address space, acommand can be sentto 11 telling itto
set its next address register to 11 + 1. Now 11 will go
through scanning station 12, 13, 14 ... again without
intervention from station ii's host software. This
directed scanning has the effect of smoothing the polling disturbance over a greater time.
After a station is given the token, it will send an information frame, a token frame, or a combination of
both. It is this combination frame, referred to as a
"piggy back" token, that causes the sub-protocols to
interact slightly.
In the normal case (no time-out), the SOURCE may
transmit a combination frame to the DATASINK when
his access period is over. All stations on the network
observe this; after the reception of the current frame
is complete, the one whose MA register matches the
token address in the frame (TC) knows it has the
token.
In the case of a combination frame, the SENDer
resets his timer TA on transmission complete and
waits for the NA station to transmit something valid,
FIELD DESCRIPTIONS AND ENCODING
TC
The token control byte has the dual purpose of transferring access control between
stations and conveying a request for immediate acknowledgement of the frame by its
intended receiver.
There is no interaction between the TC field and the DA or SA fields. Thus the token
may be transferred to one station and data sent to the same or a different station, with
one single frame. The value entered into the TC field is determined by the WD2840
and does not appear in the buffer (except for transparent frames).
TC Value
o
1·254
255
DA
Meaning
Token not affected at this time.
After current frame, the token belongs to station TC.
(The sending station has recovery responsibility).
Immediate ACK requested. Token not affected.
NOTE:
The sharing of this field prevents the passing of the token with data (piggy-back) and
acknowledgement requests on the same frame. This combination is specifically
disallowed because of its undesirable characteristics in network error situations.
Destination address. Value of zero is reserved, 1 to 254 indicates the destination
address of the frame. The value 255 is the global (or broadcast) address.
SA
Source address. The values of 0 and 255 are reserved. A value of 1 thru 254 is the
address of the sender of the frame.
I
FCS
Information Field. User defines format and content.
Frame Check Sequence. The FCS calculation includes all data between the opening
flag and the first bit of the FCS, except for O's inserted for transparency. The sixteen
bit FCS is compatible with the standard HDLC FCS.
Access Control. Conveys supervisory information. May be sent as a command using
transparent mode or received in response to an ACK/NAK request. Its format is
shown below:
AC
42
ACCESS CONTROL FIELD
BIT#
7
6
5
4
3
2
Name
SCANF
WIRING
0
0
0
NVAL2 - NVAL1 -
BIT
NAME
DESCRIPTION
7
SCANF
Scan Mode (Command). Indicates that the addressed node(s) must redefine NA =
MA + 1 for use on its next token pass.
6
WIRING
5-3
2-0
Wants in ring (Response). This bit when set informs the node requesting the ACK
frame that this node is not in the logical ring, but is requesting entry. It is the logical
function of the transmitting node's GIRING .AND. INRING. ,(see CR13 and SR20) The
WD2840 does not act on this information but merely passes it to the host via the
ACK'ed frame's FSB.
Reserved,
NVAL
-
1
0
NVALO
An encoded NAK/ACK value (Response). The receiving node will set one of the
following codes depending upon the state of the last received frame:
o0
o0
o1
o1
01011 0 0-
No error
Insufficient buffers for frame
Receiver not enabled at frame start
Receiver overrun
Frame exceeded 16 receive buffers
Normal Frame Format:
F - TC - DA - SA - I - FCS - F
= Flag, binary pattern 01111110
F
TC = Token Control (8 bit)
DA = Destination Address (8 bit)
SA = Source Address (8 bit)
I
= Information Field (0 to 4095 bytes or 16
buffers, whichever is less).
FCS = Frame Check Sequence (16 bit)
to verify his reception of the piggy back token. If the
timer expires, the sender sends an explicit token (the
data from the combination frame is assumed to have
been accepted) and enters the normal token subprotocol.
The user is prevented from sending a combination
frame and requesting an acknowledgement at the
same time to prevent possible network state conflict
under time-out conditions.
Access Control Format:
F-DA-AC-FCS-F
F
= Flag, binary pattern 01111110
DA = Desti nation Address (8 bit)
AC = Access Control Field (8 bit)
FCS = Frame Check Sequence (16 bit)
Token Pass Format:
3.3 FRAME FORMAT
The frame format the WD2840 uses to transmit all
data and control frames is similar to the industry
standard HDLC. A 16 bit CRC is implemented and
standard zero insertion (CRC16-CCITT) is used for
framing, This framing method allows the use of
standard network monitoring and diagnostic
equipment such as data scopes and logic analyzers.
Additional address fields and control pOints are
defined as required to support the protocol.
F-TC-FCS-F
F
= Flag, binary pattern 01111110
TC = Token Control (8 bit)
FCS = Frame Check Sequence (16 bit)
43
TRANSPARENT FRAME
3.4 SENDING A TRANSPARENT OR
ACCESS FRAME
Link (H)
Link (L)
FSB
20H FCB
XX Length (H)
>08H Length (L)
TC
Two types of frames are transmitted under the transparent mode under user control. A scan access frame
or a transparent frame. The format of the frames are
described under 3.3 Frame Format with the transparent format the same as Normal Frame Format.
ACCESS FRAME COMMANDS
DA
SA
DATA
There is only one Access Frame type permitted under
user control - Scan Frame. The node that is
addressed must redefine NA = MA + 1 for use on its
next token pass. The format for sending this frame is:
LINK (H)
LINK (L)
00 LENGTH (H)
08 LENGTH (L)
DA
80h
The Transparent Data Frame allows a user to control
the token pass, or TC field of a frame by using the first
by1e after length rather than the FCB. The frame transmitted will look like the User Info part of the buffer without the WD2840 firmware generating anything else but
the flags and FCS.
Pointer to next frame.
00 (FSB)
20h (FCB)
pass token, broadcast,
ackreq.
Transparent frame, no
acknowledge allowed.
Access Control frame
size (H, L).
4.0 ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS:
Destination Address or
255 broadcast.
Set Scan Mode.
Voltages referenced to VSS
High Supply Voltage (VDD) ........... - 0.3 to 15V
Voltage at any Pin .................. - .03 to 15V
Storage Temperature Range .... - 55°C to + 125°C
Electro-static voltage at any pin ...... 400V (Note 6)
The FC~ can be set for last frame, the acknowledge bit
has no effect and no acknowledgements will be given
to access frames nor will they be expected by the transmitting WD2840.
NOTE:
Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous
operation at these limits is not intended and should
be limited to those conditions specified under DC
Electrical Characteristics.
The node receiving the access frame will only recognize a scan access frame as a command. Event count
#0 will increment and the receiving node will set its NA
to MA + 1. Any other access code will increment Event
Counter #7.
OPERATING CHARACTERISTICS (DC):
Operating Temperature Range ...... O°C to
SYMBOL
IDD
ICC
VDD
VCC
VIH
VIL
VOH
VOL
10ZH
10ZL
IIH
IlL
PARAMETER
VDD Supply Current
VCC Supply Current
High Voltage Supply
Low Voltage Supply
Input High Voltage
I nput Low Voltage
Output High Voltage
Output Low Voltage
Three·State Leakage
Three-State Leakage
Input Current
Input Current
+ 70°C
MIN.
1104
4.75
TYP.
MAX.
UNIT
18
160
12
5
30
220
12.6
5.25
mA
rnA
V
V
V
V
V
V
j.lA
204
0.8
2.8
004
50
50
10
10
44
!iA
j.lA
j.lA
CONDITIONS
10
10
VIN
VIN
VIN
VIN
=
=
=
=
=
=
-0.1rnA
1.6rnA
VCC
0.4V
VCC
OAV
5.0 TIMING CHARACTERISTICS (AC):
SYMBOL
ClK
RC
TC
MR
TAR
TRO
THO
THA
TAW
TWW
TOW
TWRR
TROR
TRR
TOAK
TAHW
TOHW
TOA1
TOAO
TOO
TOAH
TOMW
TTDV
TSRD
THRD
PARAMETER
Clock Frequency
Receive Clock Range
Transmit Clock Range
Master Reset Pulse Width
Input Address Valid to FiE
Read Strobe (or OACK
Read) to Data Valid
Data Hold Time From
Read to Strobe
Address Hold Time
From Read Strobe
Input Address Valid _
to Trailing Edge of WE
Minimum WE Pulse Width
Data Valid to Trailing
Edge of WE or Trailing
Edge of OACK for OMA
Write
CS High Between
Writes
CS High Between RE
RE Pulse Width
OACK Pulse Width
Address Hold Time
After WE
Data Hold Time After WE
or After OACK for OMA
Write
Time From ORQO (or
'[)'ROT) to Output
Address Valid if
AORV = 1
Time From DACK to
Output Address Valid if
AORV = 0
Time From Leading Edge
of OACK to Trailing
Edge of D1m(5
(orORQI)
Output Address Hold
Time From OACK
Data Hold Time From
OACK For OMA Read
TO Valid
RDSetup
RDHold
MIN.
TYP.
MAX.
UNIT
CONDITIONS
0.5
0
0
10
0
2
2.05
Note 1, 1
Note 4, 7
Note 4, 7
375
MHz
MHz
MHz
mS
nS
nS
20
100
nS
0
nS
100
nS
200
100
nS
nS
300
nS
300
375
375
80
nS
nS
Note5,2
Note 2, 3
nS
100
80
nS
375
nS
NoteS
375
nS
Note 5
20
100
nS
20
100
nS
Note 2
nS
nS
nS
100
0
320
NOTES:
1. Clock must have SO% duty cycle.
2. There must not be a CPU read or write (CS-FiE or CS-VVE) within SOO nanoseconds after the trailing (rising) edge of PACK.
3. There must not be the leading (falling) edge of 'i5Ii'CK allowed within SOO nanoseconds after the completion of a CPU write (CS-WE).
4. See "Ordering Information" for maximum serial rates.
S. C(load) = 100pf
6. Measured by discharging a 100pf capacitor to each pin through a 1K ohm resistor.
7. TC/RC must be <43% of ClK when transmitting multiple buffers.
45
X
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1 ' -_ _
-W-E--~~t
OM~M~
~
X
_ _- - J
T==TOW==?~f---TA-H-W
I~
I-
---------~(
--1
TOO
/
I
I
j.
.j
_TOA1
(AO-A15SAMEAS OMAOUT)
<
= 0)
)
OR6I~
I
j.;:TOAO
':~~ ~:T ~~~~~~~~.--~-~~~ ~~ ~-;:'l-
AO-A15
(AORV
1)
=
OACK
r--TOAK~ TOAH
/
-I
'\
1
OACK
OALO-OAL7
r-
~
/'
AO-A15
(AORV
TOHW
CPU WRITE (CS IS LOW)
CPU READ (CS IS LOW)
1
>--
OATA VAllO
I
ORQO~
'---
TAW--_I
OIl
<
TOMW
1-
ITOO--I
/
r-TOAK--l
V
"J
I ..TOW..
OALO-OAL7
OATA VAllO ')
<
I~H~!
OATA VALID
>--
LTROj
DMAIN
DMAOUT
6.0
ORDERING INFORMATION
DEVICE NUMBER
WD2840-01
WD2840-05
WD2840-11
MAXIMUM RATE
100 Kbps
500 Kbps
1_0 Mbps
Package Diagram
100
t r..----
MAX
-
2.430
MAX
.015
---------I MIN
TO
.610
MAX
l.:::=.i
=. n!fl1rrnmmmnr f-t- ~
jl' r-r-~
-1'1'_...
0.35 ~
055
014
_I
~
.100
TYP
---.
.120
MIN
RO
021
TD-RD TIMING
46
Printed In U.S.A.
L_
WD2840
NO
"NITWORl('
RETUR~
..lAVE VALID
10
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INTERRUPT
I
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NO
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DJA6IJOSllC.
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GETlJ.lE CURRENT BUFFER':>
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WD2840 Application Note
INTERFACING THE WD2840 TO A VERSABUS
SYSTEM USING A DUAL PORT MEMORY
This application note describes one possible method
of interfacing the WD2840 Token Access Controller
with a general purpose microprocessor based system. This is intended to be an example design only,
no effort has been made to minimize the logic required to perform these functions as would be done
in a production design. Rather, the design has been
kept "clean" to promote readability.
This implementation is designed with a dual-port
memory concept allowing its use in systems that
either do not support DMA at all, as well as systems
that are unable to guarantee reasonable DMA response to a request (Figure 1). Examples of these
systems are low end personal computers that allow
their disk controllers to "hog" the DMA channel for
an entire sector transfer. Very high end systems are
also candidates for the dual-port memory technique.
Here, the system bus may be shared by multiple
hosts and be of such extreme bandwidth that the
internal WD2840 DMA controller may be inefficient.
In most applications, the WD2840, can simply selfDMA its data directly to/from the host system's working memory. In the applications described above, the
WD2840 must DMA its messages to/from the network into a local RAM allowing the host to access it
at its leisure.
REFERENCES
• WD2840 Token Access Controller Specification,
Western Digital Corporation, 1983.
I\)
• "Token Passing Cashes in with Controller Chip" ~
Electronic Design, October 14,1982.
C)
• Versabus Technical Reference Manual Motorola,
• RS-422 Technical Specification
This design is described in six sections:
• Host dependent logic, here designed for the
Motorola Versabus system, including all required
bus interface drivers and timing.
• Local two-port buffer memory which is shared by
the host and the WD2840.
• Arbitration logic to fairly share the buffer memory,
especially when both the host and WD2840 demand access at the same time.
• WD2840 Token Access Controller and associated
timing
• Media interface consisting of a manchester
encoder/decoder and liner drivers
~
• Generalized initialization flowchart
IV"
~
H
0
S~
~~
HOST
INT
&
CONTROL
TAC I HOST ARBIT
TIMING
2840
AND
!CONTROL
t
DRIVERSI
RECEIVERS
8k
U
S
~
ADDR
DECODE
li
,...
I----
x8
RAM
~
DATA 8
ADDRES§,16
IT Tf
J l
MAN·
CHESTER
ENCODE
DECODE
11
BASE ADDRESS: FF4000
INTERRUPT LEVEL: 6
INTERRUPT VECTOR: #255
Figure 1.
Versabus Application of WD2840 Using Dual Port Memory
53
~
MEDIA
INTERFACE
~
Ot8~OM
DATA DRIVER ENABLES
NEN EN
o 0 RECFM. HOST
0 1 ILLEGAL
1 o OFF
1 1 DRIVE HOST
Jl
r::
5
6
7
8
'"f1
9
10
11
12
...
.j::.
I
::t:
0
2l.
::l
...i»CD
0
CD
4
5
D2
10
9
'1
6 11
3
D3
D4
D5
13 8
4
242
00
5
All
D7
6
NEN
EN
CD
'"
'kt "
DO
lYi
11
10
9
8
DO
Dl
D2
D3
3LS3~
!Z...2 Al
DTACK
13
14
15
16
17
18
19
20
DB
3'242~1
D9
4
Al0
9
5
6 1
13 8
iJiij
Dll
D12
3
4
5
6
513
D14
)15
242
A9
9
8
S"
~
Dl0
Dl1
D12
26
34
95
74
~
DSO
DSl
RESET
WRITE
ACKIN
SYSRESET
ACKOUT
HWRITE
2_
240
4
A8
6
8
[>0
11
13
15
17
16
14
12
9
7
5
3
;P19
DATA/CONTROL
O~
1
21 C4
RESET
HWRITE
il121, 122
19
2r----- 18
Jl
f#A9
4[>ot-1§.
-t,o
6
~
!-=
Al0
All
AU
A13
A14
A15
A16
~
DSA3
12 DOlO
8
11
13
15
17
TACS
r-"
ADDRESS MODIFIER
~~
A6
9
240
7
~
83
84
85
63
59
94
86
60
~
Ii'" f-ffi"
f-t ~
~ r=
1y"y;9
83
"':;";'~lrl
18
)1;09
44
45
46
47
48
49
50
51
.~'D'Q~
FC 9
-12
92
,"00
~~D
I
~
1
IR06
ADDR SET UP DLY
+5
+ 12 125-128
~
17
1,2,129,130,131,132
+5
29
N/C
D13
D14
D15
I
~
~
240 7
AS
15
18 4.--.,
~6
1119
5 Al
LJ:rW.
25
43
C9
1::v-r 13
A07
A08
42
1....-
A7
11
13
AD6
41
TACS
6
8
A05
40
J2
GND 13, 4, 23, 24, 27, 28, 31, 32
61,62,119,120,135-140
AD
4[>o~
~
l@
A04
39
D4
D5
D6
D7
2"'--- 18
AOl
A02
36
37
38
TACINTR 2
cO
c
(]I
/'
AMO
AMl 4
AM2 6
AM3 8
AM411
AM5 13
AM6 15
AM7 17
96
LS32
ACKIN
RESET
HWRITE
r--
A17
A18
A19
A20
A21
A22
A23
52
53
54
55
56
57
58
~~N.C.
l-q9
~
DSA3 4....--..
AMMEMAD
18
2
A5
4 LS240 16
14
6
8
12
[>0
11
9
13
7
15
5
1Z
3
5
84'\. 6
LS08
A14
15 D7 5
A13
:~
DEVSEL
12
tl§.....l
>0
'1t-i
14
A15
r---;;v
6 AMIACK
= X7 7 AMMEMAD
3
rs
~
A2
N/C
N/C
N/C
S472 N/C
N/C
~
N/C
H
It"fs
19
':"
':'
10
~B2
1
2
51----/
LS30
6
11
A3
1
""\..
ACKOUT
3DSA
2'240 jlL..l
LSll
8
...
15
interrupt was indeed generated by this module
(IRaQ).
HOST INTERFACE
The host interface (Figure 2) utilizes common threestate bus drivers buffering the Versabus from the
internal data bus. They are enabled low-Z onto the
host bus whenever the host "reads" from the local
memory (or WD2840 registers) and are enabled to
drive the intemal bus whenever the host writes to the
intemal memory (or registers). All other times these
are hi-Z allowing other modules on the Versabus side
to use that bus, as well as allowing the WD2840 to
use the intemal bus. Only an eight bit internal data
bus is used mapping all host memory accesses into
the lower byte. (8us drivers A 10 and A 11 are not used)
Sixteen address bits are buffered and driven onto the
intemal address bus when the host has access to the
RAMs (otherwise the WD2840 drives the intemal address bus). The additional address lines of the Versabus are "anded" with the 1/0 Data Strobe signals DSO
and DS1 and address modifier bits creating a device
select signal (DEVSEl) when all are active simultaneously indicating the host actually wants to access
this module.
The Host Interrupt and Driver control logic (Figure 3)
supplies the host interrupt vector (OFFH) when
acknowledged (C10). Acknowledgement occurs
when the Versabus ACKIN is received in conjunction
with the proper priority level (set at 4 in this design),
the proper address modifier (AM lACK), a short deskew delay (DSA3), and a Signal indicating an
The logic on this sheet also controls the direction of
the data buffers previously described (with signals
EN and NEN), presuming the host has active control
of the local bus (HOST = 1). The host requests control of the bus for access to the on-board RAM and
during interrupt acknowledgement.
CLOCKI ARBITRATION
This logic (Figure 4) generates the synchronous
timing used in the rest of the sections. A 16MHz
signal derived from a crystal oscillator (part of the
manchester logic, described late0 is buffered (by C9
and then called FC). This high speed clock is also
divided down for the WD2840 system clock ClK at 2
M Hz (other slower rates are not used in this design).
This high speed clock clocks a simple latch (87) until
either the host or the WD2840 request local bus
access. If the host desires access to this module,
HOST is made true, the on-board WD2840 DMA request generated TACDRQ. When either (or both) of
these signals occur, IDLE goes false (85 pin4)
freezing the state of latch 87.
IDLE going false starts the timing chain (81, C1) that
generates general timing pulses used later.
When the local memory sequence is complete, at
time T10 for the TAC (88 pin 6) or at time T7 for the
3 ACKOUT
r-------------~ C5
A1
ACKIN
IROO
DSA3
AM lACK
3
4
5
6.
11
12
+5
5 HOST
LS240
HOST
1 012
REG
3
8
_ 4"")..::...-------------"L""LS32
.......______+---.;.1""0L C
HWRITE
9
LS32
2
240
-f>
18
16
DO
01
HOST
HWRITE
(READ)
10
C5
LS08
8
EN
(DATA TO HOST)
8
\7AOD7\CK
4
TACS
5
NEN
(RCV FROM HOST)
LSOO
C4
I NT VECTOR (= FF)
LS32
Figure 3.
Host Interrupt and Driver Control
55
HRAiViON
r
!
host (82 pin 6) a special end of cycle delay is initiated
(via shift register E7). This delay ensures that at least
500ns is maintained between WD2840 DMAs and
possible host 1/0 accesses. At the end of this delay
flip-flop 86 generates a one clock "DONE" pulse re:
setting the arbitration logic.
MANCHESTER ENCODER I DECODER
The manchester encoderldecoder used here is a
Harris HD-6409 (Figure 7). This device is ideal for use
with the WD2840 in that its "invalid manchester
output," that detects missing clocks, etc., can be
directly connected to the WD2840's SO input. A 16
Mhz crystal controls the internal digital phase locked
loop used for clock recovery and generated the 16
Mhz master clock (FC) used for general timing in this
design.
The "modem" consists of a simple RS-422 balanced
driver and receiver. More elaborate media interfaces are possible, including FSK and broadband,
depending on speed I distance I number of taps I cost
requirements.
MEMORY ARRAY
The memory (Figure 5) uses simple static memories
configured as 8K by 8 bits. The RAM data lines are
buffered onto the local data bus due to loading
considerations. The RAM array is enabled during all
1/0 operations except those to the first sixteen
locations, which are used for accessing the sixteen
internal WD2840 registers (REG).
WD2840 SUPPORT
INITIALIZATION
The WD2840 interface logic is given in Figure 6. The
system clock (ClK) is derived from the timing
generator (Figure 4). (This clock may be asynchronous with the transmit and receive data clocks if
desired.) Address latches are used in this design to
provide additional signal drive and to improve
memory access timing (the WD2840 does have internal address latches that are useful in less stringent
applications).
Host Write (HWRITE) is used to control the direction
of 1/0 operations with the WD2840. When true, the
WD2840 expects its internal registers to be written
into. This occurs when both WE (pin 3) and CS (pin 4)
are both low. Gate C7 1,2,3 ensures that the WE'
signal goes false prior to the data changing (ensures
hold time) ..Chip select logic (D10, 1,2,13,12) enables
reads or wntes only when the host has access to the
internal bus, the internal address bus holds a value in
the range of 0-15 (REG true), and a short set-up timer
has expired (11).
Gate F10 (11,12,13) "ands" the WD2840s DMA input
and output requests and presents them to the arbitration logic described earlier (via TACDRO). The sense
of the WD2840 DMA request (input or output) is
latched (with E10). The DMA output signal is delayed
for RAM setup (12) and turned off before the data is
removed to meet RAM hold timing (17) and presented
to the RAM control logic to generate the write pulse.
Figure 10 "flow chart" gives a generalized method of
initializing a WD2840 based communications subsystem. First the WD2840 internal diagnostic are
preferred, followed by loading of station parameters.
Next the network is tested for activity and potential
duplicate addresses. Finally the WD2840 TXEN is set
allowing normal network generation. The Host now
simply monitors TX and RX chains to sent/receive
network data.
SUMMARY
This application note details a simple WD2840 subsystem designed around the VERSAbus form factor.
The on-board RAM makes removes any DMAlhost
bus access questions from the system design. A very
simple line driver allows a number of these modules
to communicate at speeds of 1 Mbps.
Note that this application note is intended for illustration only; simpler and more elaborate interfaces are
possible.
56
A 3 caM
4 C4M
5 C2M
6
C1M
0 11 C500K
A1
B1 10 C250K
C125K
C1 9
~tf~
FROM
MANCHESTER
12
clr1
13 C
1
Fe
ryo9~21
NC
NC
NC
TACORO
HOST
NC
NC
FC
1 __
B7
175 0
5 0
0
0
0
9 0
0
4 0
2 TACS
3 TACS
7 H STS
LS08
7 IDLE
_0'\
11 HOSTGNT
FC
."
lEi
c
iiJ
LS240.
~
CLOCK
0
U1
'""
I
0'
()
273
:0\"
I»
E7
HOST
::l
C.
g;>
IDLE 3
DO 273 00
4 01 B1 01
T1
T1
T2
T3
~
T2
702
02
:I
T3
8 03
Q3
o·
Q4
05
06
07
TAC/HOST ARBITRATION
T4
9 T12
T5
12 T13
T6
15 T14
T7
16 T15
~
LS240
T8
19 T16
~
R
OON"E
RESET
~Du16
07
~
I'
2 R1
5 R2
6 R3
9 R4
12 R5
15R6
16 R7
19 R8
DONE
'f6
17
+5V
'f6
1119
STATE GENERATOR
0t79C:OM
Ot8~OM
AO
3
DRQIL
HWRITE 13
T4
12
TACW
LS32
,':,0
~
..L
~5
C
iii
4118
D1
4118
F1
r-r-4118
4
3
2
1
A7
RAMWE 21
RAMOE 20
RCSO
18
II
D2
RCS4 18 1
CS
4118
D5
?'
01
())
RCS2
I s:
(1)
REG
T1
HOSTGNT 13
3
0
-<
18
62
A8
23
A9
22
RCS3
...~
4118
F2
4118
D4
WE
OE
Vee
12-+ 24
ReS1 +5
18
~
F11 LS240
'"M
/Zl'
-
--
RDTO
RDT1
RDT2
RDT3
RDT4
RDT5
RDT6
RDT?
9
10
11
13
14
15
16
17
RCS5
1
1
181
RCS6
1
1 4118
F4
1
1
1
18
19 N/C
18
RAMCE
II>
RCS7
'<
A10
A11
A12
+5
1~15
2 6 C8
3Jc
I
v
I
138
14
13
12
11
10
9
-
7
RCSO
RCS1
RCS2
RCS3
RCS4
RCS5
RCS6
RCS7
DO
D1
D2
D3
D4
D5
D6
D7
2 r - - 18
16
4
244
C12
14
6
12
8
11
9
7
13
15
5
17
3
-I>-
U - ~,
RAMOE
17
LS240
3
D7
RDTO
RDT1
RDT2
RDT3
RDT4
RDT5
RDT6
RDT?
RDTO
RnT1
RDT2
RDT3
RDT4
RDT5
RDT6
RDT?
2 . - - - - 18
244
16
4
C11
14
6
12
8
11
13
15
17
-RAMOE
-t>-
9
7
5
3
DO
D1
D2
D3
D4
D5
D6
D7
18
1 4118
F5
TACGNT
T2
D7
1
21B4~
27
26
1 38
2
339
440
3......--4 DO 00
7
B12
8
373
13
2
5
6
9
12
AO
A1
A2
A4
A3
A5
A4
A6
2 " C2
1311
5 41
6 28
7 29
14
15
16
19
1
2
5
6
9
12
15
16
19
A5
A6
A7
A7
A8
A9
41\ C2
5fL
A10
9
AO
C1M
(1MHZ)
6 CLK
D9
AO
46
47
45
44
A1
A2
A3
"TI
"rc
CO
~
.~ 'fC
17
Re
CTS
SO
~
HWRITE
c
C
'C
'C
o
1
C7
f6
::.
5
I21 LS~
HWRITE
12
13
14
15
2840
21
RiS
22
CTS
2
SO
=E
o
8
9
10
11
20
16 TD
RD
RD
TC
RC
RTS
,<
4.7K~
iii
!»
01
TD
+5V
lAO
IA1
IA2
IA3
T1
HOSTGNT
RE (OUT OF 2840)
WE (TO 2840)
CS
3
~
3
DROO
LSOO
Tii
4~ 6
TACGNT
51 C7
25
J'~
--
17
18
11 G
OC
3......--4
B11
7
373
8
13 _
30
31
32
33
34
35
36
37
14
17
18
11 G
A8
A9
A10
A11
A12
A13
A14
A15
LS27
1
12
3
9 LS10
:...--
6
8
D10
A11
101r~
A12
111-
REG
I
~
C9
LS240
REG/RAM DECODE
OC
-.z:::...1..
1~LS10
REG
TACS
DROI
DACK
8
9
10
11
12
13
14
15
DO
D1
D2
D3
D4
D5
D6
D7
~
~
,......"..,."
4
D
5 D
E10
I~
0
0
3 DROOL
7 DROlL
"'i'7 4 LS10
~
---s1 D10"\ 6
TACW
"1
175
DACK
1
RESET
+5V
J G7 ""'J6PEiREsET
4
rt~121.L
=16
LS08
.~
7
MR
INTO
N/C....!. DO NOT CONNECT
.+5
43
TACiNrR
+5
13
~11
I
TACDRO
c:::.nn
+12
Ot8~aM
~
~
RS422
DRIVER
15 CTS
RTS---~
BZO
7 NVM
so_--.....!..I
m
o
~
18
OJ
.....
OJ
4§i5
TD_--..::.!
TC
z
(JJ
s::
1 1K
ENCODER
DECODER UDI
RD_---I SDO
RC
»
HD6409
16 ECIK MANCHESTER
RD 3
iii
(JJ
1K
(5
DCIK
z
s::
m
RS422
RECEIVER
CO 11
16 MHZ OUT
Fe
o
C
s::
~T
R1
1. C1, C2 = 32 pi
2. R1 = 15 Mr, 1/4W
3. Xi = 16 MHZ, AT CUT PARALLEL RESONANCE
FUNDAMENTAL MODE
4. RT = DEPENDENT ON FREO & LENGTH APPROX. 90·2400
Figure 7.
Manchester Encoder/Driver
60
HOST TIMING.
I-- 62.5 ns.
--l
I
FC
1-
~ 'i--.-.--;-,--i--;--;--;--:--.!.-.--------~
AS-rl l
DSA
I
..J1
DSA3 -,-_ _ _ _ _
DEVSEL _ _ _ _ _~_.;.JIrl-----;---.-.:~---:------HOSTS _ _ _ _ _ _ __
I
I
T1 _ _~~-~-~--..J
T2 ____
~
___
~~_~~
T3 _ _~.....;.-.:..--.:....--.-.:-~.-:.......J
T4 ____
~
___
~
___
.....;._~
T5 ----r-~-_._~~__:_~~-~~-J
T6
--~~-7_-~-~_7-~-~~
I I
I
T7 _ _;-~--~~-~.....;.-~~~-~~
REG ____~_.-.__.--~I~~'--.....;.r-T~-~I----~I-----I~
TACCS ____~--..:.-~.-:..----'~..:..,I
WE (TAC)
---i
I
I
I'
HWRITE
RAMOE
~ ---------~-~
RAMWE
I
DTACK
ABi'RsT
I
-----------I~----------------~L...f
WRITE WIDTH ~
770ns
r--
Figure 8.
Host Timing
61
u:>
ff?
~
CHECK FOR
DUPLICATE MA
'a
TOKENS WILL
BE PASSED BY
SCAN METHOD
NO
IMPLIMENTED ON
, NETWORK
,SCAN TIME)
E
;
:::J
2
~
r------L----~i ITOKINTERRUPTS
OFF TO REDUCE
PROCESSOR
OVERHEAD
::E
~
OK TO ENTER
ACTIVE
NETWORK
I
MAY HAVE
BROUGHT
ISOLATE
FROM NETWORK DOWN
CRO - 01
NETWORK
DUPLICATE
ADDRESS
TAKE RECOVERY
ACTION
IF ALLOWED
TO INIT
SET-UP WHEN
ALLOWED TO
TX & RX FRAMES
(INIT ON)
WD2840 WILL AUTOMATICALLY
FOLLOW TX & RX CHAINS
AS THEY ARE ENABLED,
MONITOR INTERRUPTS,
(EVENT COUNTERS)
0t78i:CM
-
I --
64
LOCAL NETWORK
ACCESS TRADEOFFS
Cost/complexity tradeoffs are examined in CSMA/CD and
token passing techniques for accessing local area networks
by Mark Stieglitz
l
ocal networks are characterized by problems that
are very similar to those encountered in conventional data communications networks.' Local networks, however, generate new problems and opportunities that require reconsideration of tradeoffs in
system cost/complexity. A fundamental point of decision in local network design is the choice of access
method. Chief contenders among access techniques are
carrier sense multiple access and token passing.
What is a local network?
The current controversial nature of local area networks
(LANS) is highlighted by their many definitions. A common theme in these is that the LAN be privately owned
and/or administered by the user. An LAN need not be
considered only as a high speed data transfer
mechanism; current private branch exchanges also meet
the definition of a private system. The opportunity to
optimize the network for a particular user's application,
therefore, becomes a key feature of the network. In this
discussion we assume the following: that a local network is a privately owned communication system; it
usually runs at data rates of lOOk bits/s and above; and
it is usually restricted geographically (100 to 25,000 m).
It is often asked if the X.25 protocol can be used in
LAN applications, especially now that X.25 large scale integration (LSI) controllers are available. This question
Mark Stieglitz is local networks program manager at
Western Digital Corp, 2445 McCabe Way, Irvine, CA
92714. He is responsible for planning and developing
the company's LSI and system level local network
products. Active in IEEE standards activities, he is
currently chairman of the IEEE-802 Token Access
Working Group.
OCTOBER 1981
"Reprinted with permission from com~uter
Design - October, 1981 iss~e ..CoPYright
"
1981 Computer Design Publishing Company.
65
can be more readily answered by comparing LAN
and X.25 protocol functions
using the International
Standards Organization
Open Systems Interconnection (ISOIOSI) reference
model. 2,3 The model was
developed to help conceptualize the relationships of
various elements in a communications protocol. The access function resides between physical and link level functions, often referred to
as a link layer sub-layer (Fig I). The primary difference
is that the concept of a shared medium is foreign to X.25.
Addresses at the link level are actually command/response indicators, since it is assumed that pairs
of stations have point to point links between them.
The local network access layer implements both the
device arbitration and addressing necessary for shared
medium operation. Once this layer is chosen and implemented, it is expected that the remaining layers may
be used in this new application with little change.
Network topologies
In simple terms, topology is the way in which networks
are tied together (Fig 2). Many networks are wired in
ring or star configurations in order to eliminate the contention problems that occur when more than one connected device tries to send data at the same time. The
primary advantage of the bus topology is easy reconfigurability, more important, perhaps, than its reliability advantage. Costs of improving reliability in a star
or ring network, eg, adding redundant subsystems, can
be much less than reconfiguration costs of the same network over its lifetime. Reconfiguration is labor intensive, and the cost of labor is increasing at a faster rate
than that of reliable electronics.
The security of a broadcast bus system is often questioned by users who are apprehensive of the party line
COMPUTER DESIGN
APPLICATION
PRESENTATION
SESSION
TRANSPORT
NETWORK
,,' "'.
'/"'"
,
I
l
LINK
PHYSICAL
I
J
LINK
ACC£SS
PHYSICAL
LAN
X25
Fig 1 ISO/OSI reference model applicability. The model
directly applies to locid networks with addition of access layer
concept, where they share a network with diverse user
groups. This problem is readily overcome by encrypting
the appropriate data on the network. This alternative
was at one time unfeasible because of high costs. Now
several solutions are made possible by extensive LSI implementation of the National Bureau of Standards data
encryption standard, which resolves this obvious problem in bus topology.
STAR TOPOLOGY
"Y
~~
o
ADVANTAGES. SIMPLE PROTOCOL; LOW
INCREMENTAl COST: NET INFORMATION
RATE MAY BE HIGHER THAN TRANSMISSION
BANDWIDTH; EASY NETWORK MONITORING
AND CONTROL
DISADVANTAGES HIGH INITIAL COST
RELIABILITY. DIFFICULT TO RECONFIGURE
(ASSUMING CABLE OR FIBER)
RING TOPOLOGY
ADVANTAGES SIMPLE PROTOCOL. WELL
UNDERSTOOD; IDEAL FOR FIBER. NET
Ir~FORMATION RATE MAY BE HIGHER THAN
TRANSMISSIDN BANDWIDTH
DISADVANTAGES REQUIRES ACTIVE TAPS
RELIABILITY MEDIA DEPENDENT - NOT
SUITABLE FOR RADIO FREQUENCY DR
INFRARED
BUS TOPOLOGY
ADVANTAGES EASILY RECONFIGURED.
MEDIA INDEPENDENT. DISTRIBUI ED CONTROL
IMPROVES RElIABILITY; COMPLEX PROTOCOL
DISADVANTAGES REQUIRES" COMPLEX' ACCESS
CONTROL DIFFICULT TO MONITOR NETWORK
NOT SUITABLE FOR FIBER WITHOUT ACTIVE
TAPS
Fig 2 Typical local network topologies. Each has
fundamental strengths and weaknesses. Bus topology's
efficiency, maintainability, and cost are heavily dependent
on access method used
66
Access methods
Currently the most controversial open question in the
local network area is the choice of access methods in
LAN buses. An access method is that part of a protocol
that coordinates bandwidth use among all network
subscribers. It ensures that only one station transmits at
a given time, or, if more than one, that proper recovery
action is taken to provide correct data transmission.
Two common methods for allowing multiple transmission sources on a broadcast medium are frequency division and time division multiplexing (FOM and TOM).
Both are fixed assignment schemes and require some
centralized network intelligence to assign channels
(FOM) or time slots (TOM). There are cost and reliability
drawbacks to this centralized scheme. Also, it is difficult to effectively use the communications bandwidth
where there are many sporadIC data sources, such as
word processing terminals. The solution to this lies in a
demand access scheme, two of which are currently being
promoted.
Carrier Sense Multiple Access (CSMA). In this method
a station wishing to transmit listens first for channel
clear, and transmits if such is the case. When two stations hear that the channel is clear and transmit simultaneously, a collision occurs. This must be detected and
recovered by the CSMA protocol. The simplest 'type of
collision detection requires a higher, usually link level,
intelligence to note that a frame has been lost on the network. All frames would be buffered until acknowledged
and retransmitted if no timely ACK is received.
Carrier sense multiple access with collision detection
(CSMA/CO) is a CSMA implementation that can detect
transmission collisions while the data are being
transmitted. This enhancement greatly minimizes bandwidth wastage during collisions, but imposes a
minimum size restriction on every frame to ensure that
collisions are detected (Fig 3). A more serious drawback
in collision detection is in its actual implementation. It
must detect two simultaneous transmissions (a station's
receiver must "listen" for others while its own transmitter is "talking"). Transceiver design is critical.
Special cable and cable taps are often needed to
minimize noise and impedance problems. Special installation and grounding practices that have been
developed may necessitate additional training of cable
installers and modifications to building codes. All these
constraints have recurring cost implications. So, while
many solutions have been implemented, some are
costly, and each is media/speed dependent. Several different systems using CSMA/CO are commercially
available. The most notable is Ethernet, a joint offering
of DEC, Intel, and Xerox.'"
The CSMA scheme is comparatively simple and has
enjoyed much academic research, but it has some shortcomings. In the pursuit of simplicity, visibility of network errors and the potential for future upgrade have
been sacrificed. Since CSMA allows and expects collisions on the transmission medium, it is difficult for
diagnostic equipment to distinguish expected errors
from those that are induced by noise or faults. Determinism, or the ability to guarantee the successful (no
collision) access of a station within a
fixed tirne interval, cannot be accornrnodated in a CSMA environrnent.
Office autornation, which is not
real tirne and therefore CSMA corn,
patible, is a rnajor local network
i".~--------- 2: FRAME SIZE ( M 1 N l - - - - - - - - - -.....:
rnarket. Process control, the other
rnajor application category, requires
absolute delay lirnits and reliability
guarantees. Both rnarkets can be ad- Fig 3 CSMAlCD frame. Filler is needed to ensure sufficient frame lengtb for
dressed with the sarne "standard" collision dete~tion. Minimum fra~e lengtb is function of propagation delay
protocol and access rnethod only if :tb::r.:o.::ug!!:b::...::m::a::X1=m=u::m::.:le=n::!g~tb::....::o:.f.::m:.:e.::d:.:lu=m=--_ _ _ _ _ _ _ _ _ _ _ _ _ __
the needs of both are rnet. The token access rnethod is a cost. This adrninistrative rnethod is also generally rnore
way to accornplish this.
expeditious than distributed schernes, since the latter reToken passing. A token is an exclusive right, held by quire delays in their distributed algorithrns and require
exactly one station at any given instant, to initiate trans- all stations to rediscover their part of the network conactions on the rnediurn. Distributed network intelligence figuration each tirne.
In the distributed scherne, reliability and ease of conpasses this access right around the network in a logical
ring, resulting in an ordered and controlled access figuration are achieved; the network configures itself
rnethod. In the token passing scherne, sornetirnes re- each tirne it is initialized. The best of both worlds, speed
ferred to as "baton passing," each station sends a and reliability, are achieved in the hybrid systern. Here
rnessage to its access successor when it has finished its the distributed algorithrns are retained as backup in case
of an adrninistrative failure.
transactions (Fig 4).
The token protocol rnakes no assumptions about, or
Control rnessages are sent in the sarne forrnat as is inforrnation, in frarnes. At first glance the token access "irnproper" use of, the transrnission rnediurn or
scherne's frarnes look rnuch like those of CSMA systerns transrnission rate. Any collisions are treated sirnply as
as shown in Fig 3. The sirnilarities are purposely at the manifestations of noise and are consistently handled as
physical and link layers (Fig 5). The sirnilarity ends with exceptions. No expected collisions mean no confusion
the access field; the required filler in CSMAlCD systerns is as to cause, resulting in irnproved maintainability and
replaced in the token passing frarne with a token control serviceability. The use of strictly "inband" signaling
allows true rnedia independence. Radio frequency, infield, usually of one octet.
The required control inforrnation could have been frared, CATV, baseband coaxial, fiber, and other broadcoded into the link level control field, but instead is cast rnedia are usable with no change in the access
placed directly ahead of the link field. There are three algorithrn or any sacrifice of efficiency. This flexibility
reasons for this. First, it provides adherence to the will be useful as data rates and distances grow and as
ISO/OSI rnodel's sense of encapsulation. This says that a
new transrnission technologies are developed.
given layer rnust not rnodify or require the use of any
Inband signaling also rneans that existing cornponents
data in a higher layer for its own proper operation. and technology can be used. This gives network
Observing this requirernent saves software developrnent
and redeveloprnent as users switch between X.25 and
LANS. Second, the ability to send "piggyback" tokens
requires separate access and link control fields; link inforrnation can go to one station while control is (op,,--------------------------------,:
tionally) passed to another. This is an efficiency
,,
enhancernent that allows a reduction in the bandwidth
used for network rnanagernent. Third, special forrnat
access frarnes can be sent. Since the access control field
rnay be thought of as defining the rest of the frarne (for
exarnple, an opcode), very short access frarnes can be
transferred and evaluated without rnodifying link control programs.
,
While both access rnethods are conceptually sirnple,
"'-- - ------- --------"
there are several irnplernentation challenges in the token
scherne. These include network initialization, building
and rnaintaining the logical ring (online addition/rernoval of stations), and the resolution of fault
recovery conditions. Centralized and fully distributed Fig 4 Model of logical ring. Eacb station bas sufficient
intelligence to receive and validate tokens from its
are two categories of solutions for these tasks.
predecessor (P) and send tokens to its successor (5). Pbysical
The centralized scherne uses an adrninistrative station ordering of stations is not relevant. Dashed lines indicate
to watch for and resolve unusual network conditions. control Dow
Rernoving this chore frorn the bulk of the stations
sirnplifies their processing requirernents and thus their
67
implementors the option to
capitalize on established production
efficiencies and low costs such as are
represented by CATV components.
From the use of existing broadcast
LINK
LAYER
technologies follows the applicability of existing regulations and
trained cable installers.
Fig 5 Token frame. Separate access control field allows option of passing
Token protocol's insensitivity to control
to one station while sending link level information to another
transmission speed is another important factor. It is unreasonable to assume that all net- quirements. Choice of an initialization algorithm, for
work users need the same arbitrary data rate, such as example, depends heavily on the address range allowed
10M bits/so Users with lesser requirements should be in the network: a 48-bit address range uses a different
able to scale systems to their needs and budgets. Some station sort scheme than does an 8-bit range. Work on
the distillation of these tradeoffs is underway by stanCSMA implementations have minimum frame size
restrictions that are directly based on the data rate and dards committees and commercial organizations.
the physical length of the medium, to say nothing of the
Standardization is key to volume manufacture of
cost of multi-megabit hardware. There is no reason that token controllers and to the interconnectivity of
a few cathode ray tube terminals cannot be linked multivendor equipment. Standardization also advances
together with inexpensive twisted pair cable, using the the development of network diagnostic equipment and
same token protocol and controllers as those used in ap- tools.
plications with higher speed requirements.
tions with higher speed requirements.
Summary and conclusions
Depending on the application, networks must either A new science requires fresh consideration of engibe fair (where all stations have equal access to the neering challenges. The needs of users and the progress
medium), or include some priority mechanism. The of implementation technology, especially LSI, can be
token access method supports both conditions by being projected. There is no reason to accept any scheme
generically fair, but also allows tuning of network and simply because it exists, as proposed in References 5 and
station parameters if desired. Features such as sending 6. Professional skill and judgment must be used in selec"n" frames while holding the token are easily sup- ting all elements of any system, especially one as new
ported. This allows prioritization of stations where and with such potential impact as the local area
some may be allowed to transmit more than others network.
The general token access scheme enjoys current combefore giving up the token. The network may be set to
guarantee access to all nodes within strict time boun- mercial use, generality, and expandability that make it a
truly useful standard. Investment costs in up-front comdaries, as required in control applications.
If tokens solve all LAN problems, why is there any plexity will be continually reduced with further LSI
controversy? The answer to this lies in the real and developments and as network uses proliferate.
perceived complexities of the token access scheme.
References
Is token complexity worth it?
1.
Complexity considerations must be evaluated on two
fronts: technical (Can it be implemented reliably?) and
economic (Is any additional incurred cost justified?).
Intensive efforts by individual companies and standards
groups have yielded some commercial offerings and
several technical proposals. The token access method
has been reviewed and evaluated by academicians, network implementors, and users. With the systems,
models, and documents available today, it can safely be
said that the token scheme is implementable.
The LSI developer is challenged to deliver this complex protocol at low cost. With such an LSI controller, a
day can be envisioned when users need be as little concerned about low level network protocols as they are
today with bit locations and formats on floppy discs.
Efforts in protocol design are nonrecurring, but the
benefit of a sophisticated, forward-looking design
course will manifest itself more and more as network requirements grow.
2.
3.
4.
5.
6.
J. M. McQuillan, "Local Network Architectures,"
Computer Design, May 1979, pp 18-26
H. Zimmerman, "OSI Reference Model-The ISO Model
of Architecture for Open Systems Interconnection," IEEE
Transactions on Communications, Apr 1980, pp 425-431
J. M. Kryskow and C. K. Miller, "Local Area Networks
Overview-Part 2: Standards Activities," Computer
Design, Mar 1981, pp 12-20
The Ethernet, A Local Area Network-Data Link Layer
and Physical Layer Specifications, Version 1.0, Sept 30,
1980, Digital Equipment Corp, Intel Corp, Xerox Corp
P. Franson, "It's time to get on the Ethernet bus,"
Electronic Business, Oct 1980, p 6
L. J. Curran, "Seconding an Ethernet motion," MiniMicro Systems, Nov 1980, p 73
Please rate the value of this article to you by circling
the appropriate number in the "Editorial Score Box"
on the Inquiry Card.
High 713
Algorithm details and standardization
In the general token scheme just described, detailed
algorithms vary depending on the system and design re-
68
Average 714
Low 715
LOCAL NETWORKS
Token passing
casnes in
with controller chip
1
I
Token-passing protocols
can upgrade a datacommunication system,
especially if a dedicated
controller relieves the host
from token-processing tasks.
~&
Mark Stieglitz, Network Products Manager
Western Digital Corp., Communications
Division
2445 McCabe Way, Irvine, Calif. 92714
Designers can now implement a
distributed-access token-passing
systems without worrying about
the complex details involved in the
communications protocol. Those
are taken care of by one LSI chip,
called the token-access controller.
Token passing is one method of
sharing a communications path. It
enjoys the benefits of distributedaccess systems while eliminating
the drawbacks of schemes employing carrier-sense m ul tiple access
with collision detection (CSMAI
CD). Until recently, however, token-passing techniques had little
currency because of their need for
complex controllers. This need relegated tokens primarily to proprietary uses. (For a complete review of local
networks, including token-passing techniques, see
"Broad Standards, Many Implementations Are on
the Way," ELECTRONIC DESIGN, Sept. 30, p. 87.)
The introduction of Ethernet in 1980 marked the
beginning of commercial local networks using
distributed-access techniques. A distributed system
does not rely on a single device for polling. Early
versions of Ethernet were designed to use simple
controllers because most of the development work
began in the 1970s, before the LSI era. Although
CSMA/CD offered a simplified access protocol, users
incurred cost, performance, and flexibility penalties.
Progress in LSI technology has now given designers
the benefits of complexity-increased efficiency and
enhanced flexibility-but without high cost.
The availability of the WD2840 token-passing
controller chip brings token-access communications
capability to a range of critical-process applications
that were previously unsuited to the token method.
Copyright 1982 Hayden Publishing Co., Inc.
Reprinted from ELECTRONIC DESIGN - Oct. 14, 1982
69
Local Networks: Token-passing controller
CPU bus
What's more, the controller sufficiently reduces
system communication costs, encouraging its use
with very inexpensive end products.
The controller is designed to connect distributed
intelligent devices over a shared broadcast medium
-usually coaxial cable, free-air radio, or twistedpair party line. Shared by all stations through the
use of a token-passing protocol, the broadcast
medium enables each attached device to hear everything on the network. A station is a microprocessorbased device that incorporates the controller. Complementing the token protocol's efficiency is a highlevel, software-friendly DMA (direct memory access)
interface contained within the controller. In conjunction with conventional hardware and serial communications interfaces, the DMA interface and token
protocol make the WD2840 simple to use.
The primary purpose of a token-access controller
is to free the designer from data communications
concerns. Once the chip is initialized, for example,
the host microprocessor need never bother with the
protocol; it merely processes frames addressed to it
-the controller filters out all others-and generates
messages to send later. In fact, it is the controller
that sends messages when a token is received. This
decoupling of the functions between the network and
any user processing simplifies programming and
system timing considerations.
Tasks that affect network performance-such as
processing tokens and generating acknowledgments
-are performed inside the controller. Thus designers can use any type of host processor in a station
(Fig. 1). The circuit interfaces with systems in which
a processor is busy with a specific application.
Illustrating that point is the microprocessor found
in a CRT terminal. Its duties are to scan the keyboard
and perform a limited amount of editing. That leaves
enough processing power remaining to drive the
controller, which handles data flow only for one
specific terminal. If the processor falls behind
momentarily, just one terminal is affected; all others
in the network continue to operate at full speed. Thus
a network of controller chips is not slowed by its
weakest link.
Medium
Modem
1--'5:.:;":::-QI'---1 WD2840
DRQO
DACK
Clear to send
DALo-DALs
WREN
elK
1. Two interfaces connect the WD2840 token-access
controller chip to a local-area network. The network side
(medium) is electrically conventional, whereas the host side
(CPU) combines both a control and status register and a
direct-memory-access interface.
No
.---'-''<
Frame
received?
Token passing in a system environment
When a token-access controller receives a data
frame addressed either to itself or to all broadcast
stations-there are 254 stations in a system-it
transfers the frame to the host's memory via a DMA
operation. If the frame is invalid, the close coupling
of protocol handling and DMA operations allows the
chip to manage its own housekeeping. For example,
if errors are detected through a CRC (cyclic redundancy code) or signal-quality check, the memory
space is automatically reclaimed.
2. After initialization, the loken-access controller idles in its
"watching" loop (bold lines), waiting for a data frame or token
addressed to it. The upper portion of the flow chart shows
the steps in the initialization procedure.
70
On the successful reception of a data frame, the
controller sets an interrupt and checks to determine
whether an acknowledgment was requested by the
sending station. If so, it sends the acknowledgment,
adding the receiver status, as well. A typical message
might be "Received successfully" or "Encountered
DMA problem on this end. Please retry." While the
controller evaluates each frame as it looks for its own
data message, it simultaneously checks for tokens
passed to it. This combined token-and-data framein which each part can be directed to a different
station-is referred to as piggybacking, a feature
that increases system efficiency, since most of the
overhead associated with conventional token-passing
is eliminated (Fig. 2).
Receipt of a token allows the WD2840 to transmit
A three-controller architecture
A single NMOS LSI chip, the
WD2840 token-access controller,
comprises three major elements: a
fast serial communications subsystem, a two-channel DMA controller, and a microprocessor with
internal ROM and RAM.
The device's three preprogrammed microcontrollers handle
media access and host memorymanagement functions. This type
of architecture facilitates internal
parallel processing: for example,
prefetching a new buffer address
while transmitting or receiving
data. Although the token-passing
protocol is essentially a halfduplex scheme, separate receiving
and transmitting subsystems permit loop back testing.
The primary m icrocon troller
has the capabilities and ins truction set of a conventional 8-bit
microprocessor, including subrou-
,-------I
I
----
-
error-recovery operations.
The serial-to-parallel and parallel-to-serial converter block ineludes standard IS-bit cyclic redundancy code (CRC) checking
and generation, along with the
framing logic specified by the
HDLC (High-level Data Link Control) protocol. Also, the receiver
contains an input FIFO buffer to
speed internal processing and relieve DMA latency constraints.
Hardware in terfacing is designed for flexibility. The DMA
interface, for example, uses the
familiar DMA request signals as
outputs-one for input requested,
one for output. Together with a
grant signal that both notifies the
token-access controller that the
bus is available and optionally
enables the address drivers, it
permits synchronization with
slower external memories.
-
DALo-OAL7. IAo-IA3
I
I
I
I
ROM
I
I
I
CS
I
INTA
I
MA
uT
~ Accumulatol ~
Microcontroller
I
I
-,
I
I
I
AOM
I
TO
I
I
ATS
I
CTS
I
TC
I
~
Parallel-taserial converter,
CRC, flag~
generation
control
Register
file
(16 hostvisible)
I
I
Tlmer2
Control
I ClK
i
tines, bit manipUlation, conditional branching, and arithmetic
operations. This part, whose chief
task is to implement the token
algorithms and maintain the host
memory chain, has its firmware
located in the internal I-kbyte
ROM. Repetitive and simple
operations such as DMA fetching
and storing are controlled by the
receiving and transmitting microcontrollers.
Two internal timers keep the
network independent of the host
microprocessor's timing. The first
timer is set for a relatively short
duration to limit the time it must
wait for the required response
from a transmission. The second
timer has a longer and less critical
duration that restricts the period
that a network can normally be
"idle." Limits on idle time are
useful for initialization and some
uA
1
I
I
ADM
I
I
Ao A'5
I ORal
I DRaa
DMA
l-
B-
I DACK
I
I
IL
DMA registers
(2 channels)
Serial-ta-parallel
converter,
CRC,
flag-detection
control
RC
RD
SO
__________________________________
71
I
I
I
i
I
I
~
I
r
Local Networks: Token-passing controller
messages that its host has queued. Before transmitting, however, the device checks its internal holdoff register, AHOLT, to determine whether it should
defer use of the token on the current cycle. With this
optional deference capability, the system designer
can bias the intrinsically fair token protocol in favor
of selected stations. Those that have more access
opportunities have effectively higher priorities.
Key to a token system is the visibility that each
station has to network loading conditions. The less
often a token is received in a given time, the greater
the load on the network. This indication of load data
is available to the host as an optional interrupt/token
received, and the host can scale down its data over
time. Since the host knows the importance of data
it sends, it can defer (or set higher delay values in
the priority registers) data transmissions of lesser
importance to a later time.
If transmission proceeds, messages are sent
automatically to their appropriate destination addresses, with acknowledgment requests optionally
encoded into each frame's header. Such transmissions continue for each frame queued until either a
preprogrammed limit or the end of a transmission
chain is reached (preprogramming is an optional
priority feature). When transmission is complete, the
controller passes the token to the next station. After
frames having an acknowledge option are
transmitted, the transmitting controller awaits a
response from the intended receiver. Responses can
be positive (indicating that the frame was received
correctly), negative, or nonexistent. In the last situation, the receiving station either received the frame
incorrectly or was out of service. The waiting period
is controlled by an interval timer. If a time out occurs
from a no-response condition, the WD2840 automatically retries the transmission.
Automatic retransmissions overcome most network noise glitches quickly and automatically. In
this case, the host makes no decisions. If the retry
is unsuccessful, the frame is tagged and an interrupt
is generated that allows the host to decide the
disposition of the frame. To avoid holding up the
network, the tagged frame is passed over in the
transmission chain and the next frame's transmission is attempted.
Control block __
User
memory
First
transmission
First
reception
Buffer size
Event
counters
LJ
;nk
Transmitting
chain
r
..
,
lj
,
Buffer contents have been transmitted,
may be reused by the host
;nk
...
Receiving
cham
,
Filled buffers,
ready for host use
1J
I
Initialized buffers. ready
forcontroUer use
3. The chaining technique allows either the host processor
or the controller chip to vary the number of buffers in a
system. In chaining, buffers are linked so that data frames
may span multiple buffers, making memory operations more
efficient and simplifies the host's memory allocation tasks.
A universal device
The WD2840 interfaces with any conventional,
general-purpose microprocessor or minicomputer
bus. Equally as important as that capability are the
chip's contributions to host-speed independence (decoupling) and system efficiency. To achieve these
goals, the device combines I/O register programming, interrupts, and dual DMA interfaces for data,
exception reporting, and extended control (see "A
Three-Controller Architecture").
The memory interface is a self-contained subsystem that consists of two sets of 16-bit registers, byte
counters, and DMA control logic. Backing this up is
internal intelligence that interprets and manipulates
the high-level buffer control structures.
Fetching and storing user data destined for or
received from the network are the most important
functions of the DMA system. However, these are
not simple tasks because of the speed decoupling
4. In a logical ring, atoken can pass from station 4(MA-4)
to 11, to 19, to 54, and back to 4. The physical orderofthe
ring is irrelevant, since token passing is based only on station
addresses.
72
needed between the n~al-time controller and the nonreal-time host processes. The WD2840 solves the
problem using an open-ended FIFO (first-in, firstout) method of buffer chaining (Fig. 3). In chaining,
either the controller or host adds or removes buffers
as they consume or generate data, but neither need
be concerned about the state of the other.
Though residents of the host's buffer memory,
chains are visible to the token-access chip. They are
constructed by the host from linked buffers prior to
the controller's initialization. Linking the buffers
maximizes use of the memory by permitting frames
to span multiple buffers, an advantage when most
frames are short but long frames must occasionally
be accommodated. When receiving a frame, the chip
fills the receiving buffer pointed to by an internal
register until the frame is complete. If the buffer
is filled and the frame is not complete, the device
automatically reads the link field of the filled buffer
to find the next one available and continues receiving. Of particular importance when interfacing with
an existing operating system, this automatic link
handling of variable-sized buffers simplifies the
host's task of allocating memory.
The transmitting and receiving chains' linked
buffers are maintained cooperatively through the
use of control fields located in the first buffer of each
frame. This header information includes frame
status, destination address, and actual frame length
in bytes. The length, which determines how many
buffers the associated frame spans, is written by the
host in the transmitting chain. Each device has its
own status bytes and can only read the status of the
other device, thus preventing deadlocks.
The control field written by the host is called the
frame-control byte and determines what options to
put into a frame. An example of a per-frame option
is the wait-for-acknowledgment command bit. This
bit is tested while the frame is transmitted; if set,
it causes the controller to await a response after a
frame transmission is complete. The control byte
written by the controller is called the frame-status
byte. It indicates receiving or transmitting status,
including the received "negative acknowledgment,"
_
N~ork~tro~
5. A high-performance word-processing application needs a two-ported memory interface between
the token-access controller and the local network. This minimizes memory access latency time when
the disk controller "hogs" the DMA bus for several consecutive cycles.
73
Local Networks: Token-passing controller
if any has been received.
Also contained in the logical memory interface is
a series of 8-bit event counters. Located in the host's
visible memory in the last section of the WD2840's
control block (Fig. 3), they tabulate all noncritical
but important network conditions. One such condition is the detection of a transmission error; by the
time the host learns of the error, the controller has
retransmitted. However, the chip increments the
appropriate counter, since the event is valuable to
the host for diagnostic purposes.
There are 16 control registers visible to the host
(see table). The register file stores initial timer values
and such fixed station parameters as station addresses and transmission limits. Included is a pointer
to the initial DMA control block, which is used both
when initializing the controller and when network
exceptions are encountered. The register file also
contains locations not visible to the host that are used
by the internal controller for scratchpad functions,
including the 16-bit pointers to the active receiving
and transmitting buffers.
The controller's network (serial) interface accom-
Transmit clock
~".-,
data and clock
Transmit data
~~~~~~r-
I
I
I
I
I
I
--t;-sr
I
:
:
Request to send
Clear to send
Preamble
delay
(optional)
modates standard modems and clock encoders. The
device accepts non-return· to-zero (NRZ) data and
permits the transmitting and receiving clocks to be
stopped immediately upon completion of a frame if
desired. Ordinarily this type of operation is not
allowed, as most conventional devices use the clocks
to clear the internal shift registers and perform other
functions. A pair of request-to-send and clear-tosend signals is available for externally generating
preambles for any type of medium.
Locating errors
Furnishing the network interface with novel
features, the signal-quality input warns the controller that the frame in progress contains an error
due to a media, modem, or clock-recovery fault. An
example of such a error is the detection of a missed
clock transition by a Manchester decoder (see
"Manchester II Transfers Data with Integrity,
Speed," ELECTRONIC DESIGN, March 19, 1981, p. 233).
Coupled with appropriate external logic (optional),
this input enhances data integrity beyond that offered by the frame-check sequence included with
each transmission.
A common problem in token systems involves the
actions necessary if a station is removed or fails; that
is, what if Lhp logical ring is broken? Prompt correction of such a condition affects the entire network
and is therefore handled autonomously by the controller chip (Fig. 4).
The primary responsibility for assuring that a
token arrives at its intended destination rests \\I ith
the controller chip that sent it. Similarly, if the token
does not arrive, the sending device also must retrieve
it. To accomplish this, the sending controller sets its
short internal timer to indicate the longest time that
it must wait for a receiving station to use the token.
If the token pass is unsuccessful-time expires on
the internal timer without a successful pass-the
chip begins error-recovery procedures.
Since the chief cause of these dropped tokens is
a station improperly leaving the network, the
WD2840 initiates a station scan. First it polls the
address space for an active station to which it can
pass the token. When one is found, the chip then
updates its successor register so that the poll need
not be repeated on the next cycle. After the logical
ring is restored, the host is informed by means of
a new-successor interrupt.
The WD2840 incorporates several types of
diagnostics that are necessary in conventional intelligent subsystems and LSI systems. Network-level
tests provide confidence and maintainability for the
distributed token-access system and its associated
medium and modems. System tests validate local
interfaces, such as external RAM and the interrupt
Receive clock
/
~.- -'".~,/
data and clock
~~~~~:~ - sa
"/
I
I Coaxial
I cable
~
I
I
I
I
I
I
I
I
Transmit : Receive
6. One of the simplest network Interfaces Is the Manchester
encoder·decoder, which operates through an RS·442 bus
transceiver. A nonvalld Manchester output signal connects
to the controller's signal·quallty pin.
74
Initialize
No,
token~access
subsystem, and internal tests validate the chip itself,
including the internal controllers and register file.
All three diagnostics are used cooperatively.
As a new station powers up-or attaches itself to
the network for any reason-it tests itself before
transmitting on the network, thus ensuring that any
faults do not disrupt the operating network. Selftesting is initiated by the host, whirh interprets the
results. The host must be involved IweUllse an LSI
device cannot always find and report its own failure.
Network testing occurs continuously. For example, a token-access controller watches for frames
transmitted on the network by another station having the chip's own address as its destination. Source
stations having the same address are prohibited from
a token network. If that occurs, there is usually a
hardware failure in the station or a misconfiguration
(setting DIP switches incorrectly).
controller
Pass?
Local networks in word processing
A common application of a distributed network is
multiple-user word processing. A typical system
consists of a combined file server and print station
connected to several remote CRT terminals. Each
node contains its own processor and controller, and
all communicate via the network. The CRTs are
essentially "dumb" terminals having hardware
modifications and internal firmware extensions that
permit network use. The most critical station is the
file server.
CRT terminals can be added or removed from the
network while it operates. Either the control chip
in each station or the host software configures the
network. The choice depends on the speed with which
new stations must be admitted and the tolerance of
the network to access delays. This application
tolerates delays of about 100 ms, so a simple tokenaccess-control polling method is used.
The file server has a two-ported memory interface
that minimizes memory access latency resulting
from the disk interface's so-called hogging mode.
Controllers that retain the DMA bus for several
consecutive cycles are in the hogging mode. The twoported memory is physically located on the network
interface module and appears logically in the host
processor's address space (Fig. 5).
The host interface matches the timing of the
normal microcomputer bus to that of the controller
and its local memory. This includes the memorymapping logic of the host's operating system.
Arbitration logic controls access to the local RAM
and ensures that simultaneous memory requests by
the host and controller do not end in improper
memory operations or timing deadlocks. The logic
is designed for FIFO-type command priority, with
ties awarded to the controller.
None?
7. I nitiallzing the token-access controller Is necessary before
a host processor can access a local network. The procedure
includes buffer allocation, building a linked receiving chain,
and performing diagnostic testing.
75
Local Networks: Taken-passing controller
The media interface here is implemented in its
simplest form: a Manchester encoder-decoder chip
and an RS-449 (three-state) bus transceiver (Fig. 6).
That device handles its own preamble generation and
detection at the start of each frame, so that the clearto-send pin of the controller is tied directly to its
request-to-send pin. Even more, the Manchester part
provides a nonvalid Manchester output that is tied
to the controller's signal-quality input.
Simple modems of this type are suitable for
operation over moderate distances-about 1 km at
a I-Mbitls transmission rate using twisted-pair
cable. Other commercially available modems use
more elaborate techniques to increase message reliability and distance or for other types of media.
The software interface with the host's file manager
has three phases: initialization, file transmission,
and command reception. The controller's initialization and network maintenance routines are included
in the operating system. The software receives incoming frames from the WD2840, checks for proper
frame sequencing, and builds messages that are
compatible with normal operating-system file requests.
Before the operating system can access the
network, the controller must be initialized. That
process consists of allocating buffers, building an
initial linked receive chain, and performing selfdiagnostics. The flow chart shown in Fig. 7 gives the
sequence of events. After diagnostics are complete,
the host's initialization routine clears the event
counters and writes the address of the chip's control
block into the latter's internal registers. It then
stores the proper values in the controller's registers
(station addresses, priority values, timer settings)
and puts the chip into the network mode.
A driver removes the incoming frames from the
receiving chain and then ties them into the operating
system in response to a controller interrupt. These
messages are then separated into network management and information request groups. Network
management frames serve primarily for the orderly
addition and removal of stations. The file server
periodically polls the network address space to allow
new members in, but all stations process stationremoval requests as they occur. There are many ways
to maintain a network, each having a tradeoff
between simplicity and timeliness. For this application, new stations need not be added very rapidly,
allowing for greater simplicity.
Information requests always include a sequence
number added by the controller's driver. These
numbers are used in conjunction with the chip's
automatic acknowledgment and thus ensure data
integrity: the controller makes certain that no requests are lost, and the driver filters possible
duplicates. The resultant messages are then removed
from the controller's receiving chain and reformatted
(including blocking if needed) before being passed to
the filer. As a background task, the receiver driver
initializes and attaches any free buffers returned by
the file manager to the head of the chain for future
use. Moreover, the operating system can add new
buffers to the pool as the load increases.
Transmission is initiated after the filer obtains
previously requested data. The information is passed
to the network data, which then formats it into
controller-compatible buffers, adds the correct sequence number and destination address, and finally
attaches it to the transmitting chain. As its background task, the transmitting driver periodically
checks the chain for buffers that can be returned
to the transmission pool. This is an option that can
be performed whenever a frame-transmission interrupt occurs. 0
A summary of register files
Register
Name
a
1
2
4
5
6
7
8
9
A
CRO
CR1
SRO
IRa
SR1
SR2
CTRO
NA
TA
TO
CPBH
B
CPBL
C
D
NAR
AHOLT
TXLT
MA
3
E
F
Function
Control register a
Control register 1
Status register a
Interrupt register
Status register 1
Status register 2
Temp counter
Next address
Acknowledge timer
Network dead timer
Control block pointer
(most significant byte)
Control block pointer
(least significant byte)
Next address, request
Access hold-off limit
Transmit limit
My address
76
LOCAL-UIA IIIITWOIIKS
Token-access cOldroller
.Iwork
complexity
MARK STIEGLITZ, Western Digital Corp.
Users can benefit from the increased speed
this transmission method provides
temporary but exclusive right to transmit on the
medium, a right the station must then relinquish to the
next designated station. This method has been historically used on sequential media on which access
sequence is implied by the physical interconnection, but
tokens can also be used on broadcast media such as
baseband coaxial or CATV systems by assigning unique
addresses to each station or node (MA: "my address")
and passing transmission rights between them (Fig. 1).
The simplicity and non-reliance on quirks of a
medium make token methods superior for use on a wide
array of applications. Relatively simple (from the
data-movement viewpoint) applications such as file
transfer to the complex time-critical applications of
factory automation are supported with the same access
In a data-communicatioris network, contention
among stations trying to get through to the central
computer is inevitable. One of the more effective
procedures to eliminate this contention is a form of
distributed polling known as token passing. Despite its
effectiveness, however, token passing has not been
very popular with system integrators. Most network
architects have been intimidated by the complexity of
the algorithms required to set up the station linkages
and to recover from network exception conditions, and
have settled for less complex control methods. A new
LSI token-access controller (TAC) residing in each
station of the network minimizes this complexity for
network designers.
A token is a message granting a polled station the
,...----------------------------------,.
I
I ·
I.
.
I
I
.
I
I
I
_1
I
I
I
fig. 1. AccHa control flow. When a station (MA: "my address") has
transmitted lis data, It sends the transmission rlghts-the lOken-to
the station identified in the next address (NA) reglstar. Station
numbers are in ascending order but need not be sequential for
network efficiency.
Fig. 2. Station dropout. Station 4 attampts to pass the token to 11,
which haS dropped out of the network. Station 4 then ''tImes out" and
scans for another station to which it can pass the token, finding 19.
MINI-MICRO SYSTEMS/March 1982
"Copyright 1982 by cahners Publishing
Company, Division of Reed Holdings Inc. Reprinted with permission
from Mlni·MlcroSystems, March 1982."
77
station of a previous message. These timers are user
settable and depend greatly on a network-transmission
rate, and to a lesser extent, on an application. The
timers work together and are the key to solving the
initialization and failed-node challenges.
Two manifestations of a failed node can occur. One
happens when a token holder tries to pass the token to
the next station in the ring. If the next station does not
respond to the token, the token-passing station soon
knows because it knows how long it should take for a
node to pass the token or to send a data message (time
protocol. Also, data rates optimized for the application, TA). In this case, the node that tries to pass the token
not mandated by the network implementation, are has primary responsibility to recover. It does so by
entering a scan mode from an access level, and polling
possible with the same LSI network controllers.
the network for another successor.
TAC's tasks
Assume that station 11 (Fig. 2) is removed from the
TAC must handle three main exception conditions: network and station 4 is attempting to pass the token to
network initialization and recovery from failed nodes, it. Station 4 will time out because 11 does not respond
addition of stations to the access ring while the network to the token within time TA and will attempt recovery
is in use and recovery from an error situation in which by passing the token to station 12. Station 12 will not
two or more tokens have been generated on the respond because it also is not present, which will cause
network.
TAG must handle three main exception
conditions: network initialization and
recovery from failed nodes, addition of
stations to the access ring while the
network is in use and recovery from an
error situation in which ·two or more
tokens have been generated on
the network.
I
I
1_____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
.JI
Fig. 3. Station patched out. Station 11 is logically removed from the
network when station 4 changes its next address (NA) register to 19.
Thus, station 11 no longer consumes network time.
Initialization and recovery
Initialization is setting up the network's token
linkages and determining the correct values for registers in all TACS wanting to be part of the access ring
(desiring INRING status). Failed-node recovery refers to
the network restart when a token is lost or damaged.
Token loss results from exception or expected
conditions. Error cases may be a product of noise hits
on the transmission medium corrupting the token
message, or simply a controller failure. A token loss
usually occurs with the intentional removal of a station
from the access ring. The ratio of noise hits to
controller failures depends on a network's application
and administration, but both are recovered identically.
Recovery requires the detecting station to set its
linkage register to the address of an active station.
Initialization is a form of failed-node recovery in that
all of the access linkage registers of the network must
be updated. Before initialization it is not known which
node follows which. Two timers assist in these cases: a
fairly long-time value called TD, which times out
network inactivity and a shorter timer called TA, which
is the maximum turnaround time required for a
response (token or data) to be sent by the receiving
Fig. 4. With no token, there Is no transmission. All stations detect
this and start internal timers. When one expires and has the proper
control bit enabled, it restarts the network. TO is the stetion-inactivity
timer. INIT is a switch that, when false (F), tells TAG not to attempt
recovery regardless of TO. When INiT is true (T), TAG attempts to
initialize the network after there has been no activity for duration of
TD.
station 4 to try 13. This "polling" continues by station 4
until it finally gets to 19. Station 19 will respond,
causing station 4 to update its next address register
(NA) to 19, bypassing station 11. The next time station 4
gets the token, it immediately passes it to 19 (after
sending any messages).
At this stage, station 11 is logically removed from the
network, or "patched out" (Fig. 3). If station 11 wants
to get back into the network later, the standard
station-adding procedures must be followed.
This station-by-station access polling consumes network time (each poll takes TA time), and may appear to
be an inefficient use of network bandwidth. But this is a
rare error-recovery case. Further, it is handled completely and autonomously by the TAC, which at least
bounds the delay. The host J.Lp is not burdened with this
critical task and, as a result, does not slow the recovery
procedure.
The second failed-node manifestation occurs when a
station holding the token itself fails before it has a
chance to pass the token to another. If station 4 has the
token (Fig. 4) and dies before passing it, no activity
76
MINI-MICRO SYSTEMS/March 1982
couple of them are not on-line at a time, one will come
up and reinitialize the network.
Additional stations can be added to an operating
token network at any time. If a supervisory communication path can be assumed, a candidate station requests
of the administrator that it be admitted to the access
ring. This approach is not unlike the method pay-TV
companies use to enable new subscribers' decoder
boxes. When installed, a service representative of the
cable-TV company telephones (the supervisory commuoccurs on the network and no station has the short nications method) the central site, which then sends the
timer (TA) running. All stations, however, have the properly addressed enabling signal over the network.
timer TD, or network dead timer, running. The station While this method is efficient from the network
whose TD timer expires first takes recovery responsibil- viewpoint (the infrequent control messages are handled
"out of band"), such duplicate communications schemes
ity.
To simplify network administration, not all stations do not usually exist.
A more acceptable solution is to allow the control
must be able to reinitialize the network. The first
station whose network timer TD times out tests the communications to share the data bandwidth. To avoid
control bit "INIT," saying, in effect, "when timer TD data collisions and retain the prized asset of a token
expires, should I claim the token?" If INIT is false, the system~eterminism-new stations are added on a
station waits, as does every other station, for a station's controlled-polling basis. To accomplish this, the TAC
requires the host to initiate the test for a new station.
TD to expire that has IN IT true.
One station on the network's timer TD that has the Although, in this case, host interaction is required to
ability to initialize will eventually expire. That station expand the network, that interaction doesn't set back
will claim the token and send its messages, ot send the the goal of autonomous TAC network control in that
token to its successor station as directed by its NA adding stations is not a real-time requirement. The
register. Thus, if station 19 happens to have the shorter time to add a new station is not critical to the
timer TD and has its initialize enable bit set (Fig. 3), performance of the rest of the network.
station 19 assumes the token, sends whatever messages
There are three primary methods by which a station
can be added to a network. The first is a distributed
it had queued and sends the token to station 54.
On receiving the token, station 54 (Fig. 4) sends its method, in which each station in the network can poll
messages and tries to pass the token to station 4. If for new stations in the gap between its address and the
station 4 has recovered from its problem (its failure next address (between MA and NA). Second is a
caused this recovery condition), it receives the token centralized method, in which an individual station
designated by the network architect can interrogate
and transmits with it.
If station 4 still does not transmit, station 54 has the entire address space seeking a new station desiring
primary recovery responsibility (54 has started its INRING. The third-central seam-is a simpler (from
timer TA) and will enter the scan method. The scan the host point of view), centralized method in which a
starts at station 5 and searches until it finds the next station can send a global frame causing all the on-line
available on-line station (11 in this example).
TACs to reset their next address register. This causes
The power-up initialization case behaves in the same each TAC to poll its address space at its next token-pass
manner. As stations come up, they wait for a message attempt. Each method has advantages and disadvanor for their timer TD to expire.
tages.
Host software is responsible for setting up the next
The distributed method does not rely on a specific
address register before enabling the transmitter in the station. Thus, there are no problems or efforts spent
TAC. This is set to the station address plus one (which selecting the administrator, nor is there any concern
will in effect cause a polling by that station) or, if it has about backup administrators. In the distributive methsome prior knowledge of what the network configura- od, each station has the same responsibility to allow
tion looks like, it sets NAto reflect the correct address new access members as other stations. This method is
of the successor. Host software is also responsible for the most host intensive and requires each station to
setting the time-out values in the recovery timers (TA maintain a timer (that can be configuration set as to its
and TD). The value for TA should be consistent among value) as to how often it should poll its gap for new
all stations of a network, but TD is not critical, and thus stations.
may vary greatly because it is used only in exception
For example, assume the timer in each station is 5
situations.
sec. and that station 4's timer has expired (Fig. 5). The
For example, there can be half a dozen stations on the host attached to station 4 notes that the next address
network that are intended to recover from catastrophic register (NA in the TAC) is set to 11, which indicates
conditions such as loss of token. These stations can all that a new station might be added to the network as
have substantially different time values TD so that if a station number 5, 6, 7, 8, 9 or 10.
Additional stations can be added to an
operating token network at any time.
The distributed method does not rely
on a specific station. Thus, there are no
problems or efforts spent selecting
the administrator.
79
MINI-MICRO SYSTEMS/March 1982
I
r
A token is a message granting a
polled station the temporary but
exclusive right to transmit on the
medium, a right the station must
then relinquish to the next
designated station.
The host queues a frame into the TAC transmit chain,
polling station 5. This frame will be sent by 4 with an
acknowledgement requested from 5. If 5 is present it
responds; otherwise, the TAC aborts its attempt after
time TA. The TAC marks the result on the frame in the
host memory space and proceeds with other tasks.
After this exchange, the host, at its leisure, checks
IMPLEMENTING TAC
The TAC is a single-chi" NMOS LSI
device that performs all real-time
communication tasks in a ILP-based
system. The assumed existence of a
ILP allows some less critical, nonnetwork performance-affecting tasks
to be performed outside the TAC, such
as flow control and adding new
stations.
Removing these functions from the
device results in:
• Less processing power, which, in
turn, makes the chip smaller and less
expensive;
• No processing burdens, enabling
the TAC to respond faster to network
conditions, thus improving efficiency;
• Saved firmware space and
processing power, which can be used
for internal diagnostics and a more
sophisticated host interface-a
chained frame buffer scheme, which
is a trade-off in favor of system
efficiency.
To meet the network requirements
and to include the other features
expected in LSI, such as internal
validation, a three-processor design
was used consisting of a primary
microcontroller, a receiver and a
transmitter.
The primary microcontroller performs all token-algorithm support
such as network initialization and
error recovery, manages host inter-
rupts and coordinates internal and
system diagnostics. It also evaluates
the host commands and arms and
Local network Interface
Each node (or .tatlon) Include. a
modem, a network controller (TAC: token
access controller) and appropriate hardware as required by the application
("'host"').
supervises the receiver and transmitter microcontrollers.
The receiver does minor frame
(group of bytes) filtering and frame
validation and, independently of and
simultaneously with the primary
controller, performs OMA operations
storing incoming data. The transmitter
sends data via its OMA interface when
allowed by the main controller, that is,
when a token is received.
The register file is used by the host
to set memory pOinters, network
address registers, long-term parame-
ters such as frame transmit limits
(allowing users to select exhaustive or
non-exhaustive transmission) and the
conventional command, status and
interrupt indications. The TAC'S primary interface to the host is its OMA
system. Data to and from the network
and options selectable on a frame-byframe basis are read in this manner.
The half-duplex network interface
has standard RTSlcTS handshakes.
Another feature of the receiver is a
signal-quality input that allows errors
that are easily detected by the modem
(such as a missing clock detected in a
Manchester decoder or low carrier in
a broadband system) to be signaled to
the TAC. The use of these low-level
checks further enhances the basic
frame integrity beyond that of the CRC.
Messages are sent between stations on the network in frames. The
frame structures are similar to the
industry standard HOLC; delimiters are
unique flag patterns with zero
insertion used for dal~ transparency.
In addition to adding the required
control fields to support the token
protocol, the TAC recognizes three
basic frame types: a short token pass
frame, a short frame conveying only
acknowledgement and control information and variable-length frames
holding user inforl]1~tion and optional
network control information.
Data access lines 0-8
Internal address 0-3
Register
1+_-+1
_
Chip select (CS)
Interrupt request (INTR)
Master reset (MR)
Clock (CLK)
file
~!~~:)t
L........J---,...---r-...J
......r - - - ,
Address (A) 0-15
DMA request Input (DROI)
DMA reque$! output (DROO)
OMA acknowledge (DACK)
Transmit clock (TC)
Transmit data (TO)
Request to send (ATS)
Clear to sand (CTS)
Receive clock (RC)
Receive data (RD)
Carrier detect (CD)
DMA
REGS
TAC includes three processors implemented in a single LSI device that interfaces with the host through a register file and a DMA
subsystem.
80
MINI·MICRO SYSTEMS/March 1982
the example of Fig. 6, when station 4 starts polling, it
polls only to address 75 before resetting to zero. This
works like the distributed method except that a single
station does all the work.
When the polling station determines that a station
has been added, it must place the new station in the
access ring. For example, station 4 is the centralized
station doing all the polling (Fig. 6), and it discovers
that station 27 has recently been added. Station 4
knows this because station 27 now responds to a
first-time poll, and because its status bit is set,
indicating that it wants to be added to the ring. (Some
stations may be receive only, never desiring the right
to initiate transmissions.) Station 4 sends a high-level
message to the software in station 19, telling it to
change its next address register to 27. This message
In the centralized station addition
method, a single station can poll the
entire address space, seeking a new
station that desires INRING.
the transmit status of the frame. The host sees that the
frame acknowledgement timed out, meaning that
station 5 has not been added to the network, or that
station 5 is on the network and whether the request
INRING is set in the network code field. In either case,
the host takes appropriate action. If the desired IN RING
bit is set, station 4 changes its NA register to 5, allowing
its next token to be passed to 5. This action puts station
5 in the ring.
Depending on an application's sophistication, a control message can be sent to station 5. That message
says, "Your successor is X." In this case, X = 11, so that
5 is not forced to poll for its successor. In any case, 4
updates its next address register to 5 and does not need
to go through this distributive polling cycle again
'-----<.
3 Set NA to 27
Fig. 5. Distributed pOlling. Each host polls the gap in its address
space for the possible addition of new stations. The host internal poll
timer and pOll counter set the polling rate and range as desired.
Fig. 6. Central polling. A single station--jn this case, station
4-dubbed "the administrator, " can be charged with all polling tasks.
This simplifies the software in the other stations and centralizes
network control.
because there is no gap between 5's address and the
next address; there is no possibility that a new station
can be inserted between addresses and 5. If 5 didn't
respond to 4'S poll, station 4 updates its poll counter so
that the next time that the poll timer times out, station
6 will be tried.
If node 6 responds, its desired INRING bit is tested as
above. If 6 does not respond, the host will queue a poll
to station 7 the next time its poll timer expires. This
continues until the host completes 10, when the cycle
goes back to 5 and repeats. In this example, with a gap
of 6 stations (between 4 and 11), and with a 5-sec. clock,
a new node can be added within 30 sec.
In the centralized station-addition method, a single
station can poll the entire address space, seeking a new
station that desires INRING. One reason for centralizing
this function might be the more careful control that can
be placed in a network. There can also be optimizations.
For example, the central polling station can keep track
of the stations that already exist and, therefore, bypass
some address ranges. A polling station may know the
network will never have more than, say, 75 stations. In
can also prompt station 19 to tell 27 its next address
register should be 54. This gets confusing, but it is all
done with high-level software. These tasks are not real
time and are quite efficient from the network point of
view.
Station 4, the administrator, need not create and
maintain a table of active stations on the network
because the poll response returns three pieces of
information. As node 4 polls the stations on the
network, it finds out (a) that the polled station does not
respond at all, as it would if it polled station 12 in Fig. 6;
(b) that the station is already part of the network and is
already in the ring or is receive only, as it would if
station 4 happened to poll station 11 or 19; and (c)
whether the station is attached to the network, is alive
and wants to be in the ring, as is the case with a poll to
27. These indications are conveyed by a combination of
status bits sent back by the acknowledge frame. This
acknowledge frame and status information are transferred at a TAC device level, so a host is not concerned
with whether its station wants to be in the ring. The
host simply sets up the proper bits in the control
81
MINI·MICRO SYSTEMS/March 1982
To simplify network administration, not
all stations must be able to reinitialize
the network.
registers; the bits are relayed automatically by the TAC.
Thus, with a simple algorithm, an administrative
station can poll the entire network address range and
know the network's exact membership and status.
Central scan
Central scan is the simplest method of adding
stations to a network. It involves sending a global
frame to all stations on the network, which forces each
to update its own next address register to its station
address plus one (NA = MA + 1). Assume station 4 is the
centralized station and sends the scan command frame
(Fig. 7). Station 11, upon receiving it, automatically
sets its next address register to 12 (the TAC does this;
the host is not involved but is notified of the situation).
Also, station 19 sets its next address register to 20, and
station 54 sets its NA register to 55.
The result of this is a round of polling at the TAC
level. Station 11, on completing its use of the token,
tries to send it to 12. The token to stati«;1ll 12 times out
because 12 is not present. Station 11 reclaims the token
trying to send it to 13 and so on, causing 11 to poll for
station addition. The drawback of this is the huge time
disruption incurred by the simultaneous polling.
It is not required that station 4 send this scan control
frame to all stations at the same time. If it is known
that station 11 exists in the network and that a station
may be trying to add into the network after station 11
in the address space, a command can be sent to 11
telling it to set its next address register to 11 + 1. Now
11 will go through scanning station 12, 13, 14 ... again
without intervention from
station l1'S host
software. This directed scanning has the effect of
smoothing the polling disturbance over a greater time.
The trade-off of all these methods is the software
complexity distribution. If a TAC user assumes more
responsibility, providing more intelligence distributed
in the software, the system can be more sophisticated
in handling new stations. If a user wants the TAC to
handle this task itself, saving host software development, he pays only slightly in inefficiency. TAC gives
the user an option.
Fig. 7. Central scan request. A special command can be sent by any
station causing all attached TACs to set their NA register to the
address of the next possible node. This causes each TAC to poll
without the help of the host.
Recovery from multiple tokens
Multiple tokens are not allowed on a token bus
because their presence causes a breakdown of the
orderly nature of the protocol. Their presence can only
be the result of a combination of exception and
hardware failure conditions but, once present, must be
handled immediately.
The primary defense against multiple tokens is
prevention. The control algorithms and the frame
formats have been designed to minimize multiple
tokens. For example, the TAC can refuse to allow a
piggyback token (a single frame containing both the
token and a user-information field) with the dataacknowledge option. If this were allowed, conditions
could result in which the data was negative acknowledged by its receiver and retransmitted, but the token
arrived successfully at its destination-in this case,
twice--creating two tokens.
Duplicate tokens, or at least network confusion, can
result from more than one station having the same
network address. Unless the stations are receive only,
their simultaneous responses to data frames and tokens
will probably result in their response not being
accepted. While conceptually simple to prevent, address duplication can be the result of hardware failure
(a bad DIP switch), operator error or configuration
error (if a device is moved from one network to
another).
Because the access controller must monitor the
network for messages addressed to itself anyway, it is
simple to check for messages sent by a station with its
address (most frames contain both a source and a
destination address). Part of a host's attachment
algorithm would normally check this counter in the TAC
before allowing it to transmit anything, thereby
catching most of these duplicate station faults before
they have a chance to affect the network.
A token access controller can also detect duplicate
tokens by knowing that, when it has the token, no other
station can transmit. This ability is supported in the
TAC by incorporating separate receive, transmit and
control sub-controllers. This allows the receiver to
monitor the medium while the primary controller is, for
example, searching the host's memory for a frame to be
sent. If another token exists or is suspected, the TAC
drops its token, allowing the other to circulate. If there
is no other token, the network is left in a no token state
and is easily restarted with the aid of recovery timer
TD.
•
Mark Stieglitz is manager, local networks, Western Digital
Corp., Newport Beach, Calif., and chairman of the IEEE
committee working to set a token-passing protocol standard.
82
M!N!-M!CAO SYSTEMS/Msrch 1982
WESTERN DIGITAL
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WD4028 NetSource/PC-LANTM Local Area Network Controller
FEATURES
ARCHITECTURE
• IBM POM COMPATIBLE
The following is a brief description of the hardware
functions included on the PN-IBM interface card:
• TOKEN PASSING PROTOCOL FOR
PREDICTABLE PERFORMANCE
• RING TOPOLOGY
• AVAILABLE WITH MS-DOSTM COMPATIBLE
SOFTWARE
Network Control Processor - The WD2840 is the
heart of the PC-LAN Interface board. This device consists of three individual processors plus the micro-code
containing the token passing algorithm (see WD2840
data sheet).
• RELIABLE OPERATION OVER 10,000 FEET AT 1.0
MBITS/SEC (1000' MAX BETWEEN ADJACENT
STATIONS)
Data Buffer - This part of the circuitry includes the
64Kx9 RAM and the associated control logic for storing
both the incoming and outgoing data packets.
• UP TO 254 NODES PER NETWORK
Peripheral Logic - The three main peripheral devices
shown here are the PPI parallel interface, the Programmable Timer, and the optional Data Encryption device.
The PPI reads the user programmed node address
straps on the board and provides additional control outputs used by the Cable Interface. The timer is available
for use by higher level software interface routines for
such functions as a security. Finally, a population
option is available on the board for the addition of a
high speed data encryption device (WD2001) for use
with networks requiring data security.
• LOW COST TWISTED PAIR CABLE
• INCLUDES 64 KBYTE PACKET BUFFER
• NBS ENCRYPTION AVAILABLE ON-BOARD
• EASILY INSTALLED
DESCRIPTION
The WD4028 PC-LAN is the Western Digital interface
board for the IBM-PCTM Personal Computer. It is the first
of a family of Local Area Network board level products
from Western Digital. The NetSource/PC-LAN board
provides a fast, reliable, yet inexpensive means for
interconnecting a variety of different microcomputer
systems. The basic design of the network combines a
unique cable interface method with a new Western Digital LSI network control processor, the WD2840 Token
Access Controller.
Cable Interface - Since this portion of the circuit
determines the reliability of the network, the cable
interface for the PC-LAN was designed very carefully.
In particular, circuitry is included to permit uninterrupted operation even in the presence of high ambient
electromagnetic noise (typical of industrial environments). Circuitry is also included to automatically
bypass any network node from which power is
removed. For encoding the data on the network, a Manchester type Modem is used. This restricts the information content of the signal to a single octave of
bandwidth. This increases the signal-to-noise ratio,
minimizing distortion due to non-linearities within the
cable, and permitting complete DC isolation between
nodes.
The network processor (WD2840) used in all PC-LAN
boards is designed by Western Digital Corporation to
handle the major communications tasks as they relate
to the local ring network token passing protocol. These
tasks include network initialization, addressing, data
transmission, acknowledgments, and diagnostics. In
addition, global addressing and dynamically alterable
station priority is supported.
MS-DOS is a trademark of Microsoft Inc.
IBM-PC is a trademark of International Business
Machines Inc.
Communication with the Host is accomplished through
a dual port memory included on the PC-LAN board.
This 64 Kbyte memory is used as a FIFO for all data
sent and received via the ring network, with the
WD2840 Control Processor managing the data
pointers.
83
.--------------------------~"~~----------------.
2MHz
18MHz
W
NETWORK
D
ARBITER
2
8
4
o
B
DATA
BUFFER
64Kx9
DRAM
2MHz
1 MHz
U
S
I
N
T
E
HOST COMPUTER
R
F
CONTROL
SIGNALS
A
C
E
1 MHz
FIGURE 1.
WD4028 PC·LAN SIMPLIFIED BLOCK DIAGRAM
WD2840 NETWORK BOARD CONTROL
PROCESSOR
BUS INTERFACE
The Bus Interface consists of Address Buffers, Data
Buffers, and Control Buffers. These buffers isolate the
PC-LAN from the Host bus and prevent the bus from
overloading.
The WD2840 Token-Access Controller is comprised of
three major elements: a fast serial communications
subsystem, a two-channel DMA controller, and a microprocessor with an internal ROM and RAM.
The device's three pre-programmed microcontrollers
handle network access and Host memory-management functions. This type of architecture facilitates
internal parallel processing, for example, prefetching a
new Buffer Address while transmitting or receiving
data. Although the token-passing protocol is a halfduplex scheme, separate receiving and transmitting
subsystems permit loopback testing.
The primary microcontroller has the capabilities and
instruction set of a conventional 8-bit microprocessor,
including subroutines, bit manipulation, conditional
branching, and arithmetic operations. The primary
microcontroller, whose chief task is to run the token
algorithms and maintain the Host memory chain, has
its firmware located in the internal1-kbyte ROM. Repetitive and simple operations (i.e. DMA fetching and storing), are controlled by the receiving and transmitting
microcontrollers.
The control ports of the WD2840 are addressed at
280H-28FH.
ARBITER
The PC-LAN uses custom logic devices to create a
dual-port memory, allowing access to the Data Buffer
by both the Host and the Network. Because of the realtime nature of the Network, the WD2840 has priority
over the Host for access to the buffer. If the Host
requests access while the WD2840 is accessing the
memory, the Host is given WAIT states until the
WD2840 releases the buffer. The WD2840 interleaves
its accesses in such a manner that the Host is never
denied access for more than about 1 microsecond at a
time. WAIT states are generated only when the Host is
accessing the PC-LAN Buffer Memory or Control Ports.
DATA BUFFER
The Data Buffer consists of nine 64Kx1 dynamic
RAMs. A standard delay line timing control circuit is
used to assure maximum reliability.
MODEM
The Data Buffer appears to the Host as a contiguous
64K byte block of read/write random access memory
that is addressable in the 90000H-9FFFFH range.
A CMOS HD6409 Manchester Modem device is used
to encode data on the cable. The use of Manchester
code restricts the information content of the signal to a
single octave of bandwidth (f to 2f); thereby increasing
the signal-to-noise ratio, minimizing distortion
84
Port C - Status inputs: interrupts and cable interface.
(because of the nonlinear frequency response of the
cable), minimizing group delay distortion, and permitting complete DC isolation between the nodes (if
desired).
The PPI is addressed as ports 290H-293H.
PROGRAMMABLE INTERVAL TIMER (PIT)
Two channels of the PIT Programmable Interval Timer
device are available for use by high level software interface routines for functions such as a Watchdog Timer.
These two channels are cascaded to provide for a 32bit time interval generation or measurement. The timer
is clocked at 1 MHz.
LINE DRIVERS AND RECEIVERS
The PC-LAN uses a unique line driver/receiver
arrangement to permit uninterrupted operation in the
presence of high ambient electromagnetic noise (typical of industrial environments).
A differential current mode line driver switches a constant low current (approximately 10 mA) between a pair
of conductors and uses the shield for return. The resultant current in the shield is constant and does not radiate. Although the current in the pair is constant, the
locus of the current moves slightly as the current is
switched from conductor to conductor; however, the
change in the locus is small, causing minimal radiation
which is trapped by the shield. The overall result is a
cable that radiates far less than traditional coax or
twisted pair. Radiation is so low that two pairs of conductors operate within the same shield with no crosscoupling.
The pit is addressed as ports 294H-297H.
ENCRYPTION
The optional WD2001 Data Encryption device can be
used to provide high speed data security services. The
WD2001 is addressed as ports 298H-299H.
CLOCK GENERATION
The modem device is also used as the master oscillator
for the PC-LAN. The Modem device uses a 16 MHz
crystal, and provides a high frequency clock for the
Modem and the Arbiter. A portion of the custom logic
circuit is used to divide the 16 MHz to 2 MHz for the
WD2840 (Network Controller) and WD2001 (Encryptor), and to 1 MHz for the PIT.
A differential line receiver is used to detect the received
signal. This receiver provides 3 to 5 volts of common
mode noise rejection and detects differential signals of
30 to 40 millivolts.
CABLE CONNECTION
RING TOPOLOGY
The transmission line is terminated at the receiver with
its characteristic impedance (100 ohms) to minimize
reflection noise.
The unique topology chosen for the PC-LAN combines
the best features ofthe commonly used Ring (IBM) and
Bus (Ethernet) topologies. The result is a system with
the low cost and high reliability of the Ring, but with the
flexible topology of the Bus.
D-type 9-pin connectors are used to interconnect the
PC-LAN nodes. Live pins connect to the cable (two pair
plus one to the shield) to improve ground conductivity
and minimize common mode noise problems. Two of
the remaining pins are used to detect unplugged
cables.
PhYSically, the network nodes are interconnected using
pre-assembled lengths of cable having a 9-pin male
connector at one end, and a 9-pin female connector at
the other. Each node also has two 9-pin connectors;
one male and one female. The user installs the system
by simply interconnecting the nodes together in a daisy
chain fashion as shown in Figure 2.
Having one male and one female connector at each
node prevents improper cable installation and allows
cables to connect to cables as well as to nodes for use
as extensions.
Electrically, the network resembles a Ring configuration with each node regenerating the signal. This eliminates cumulative noise and signal attenuation
problems which can severely limit the size and reliability of bus oriented networks.
BYPASS
High reliability relays are included to automatically
bypass any network node which has power removed.
These relays can also be de-energized under program
control should self-diagnostics determine that the node
has developed a fault.
The network cable itself consists of two twisted pairs
with an overall shield. This permits the separation of
the Send and Receive signals, so that data flows in only
one direction in each signal pair.
PARALLEL PORT INTERFACE (PPI)
Each network node located at the physical end of the
cable (or Cable Branch) has a termination plug connected to the unused 9-pin connector(s). These plugs
are wired such that the two cable pairs are tied
together, thus completing the ring.
The Parallel Port Interface device provides three 8-bit
ports that are used as follows:
Controls outputs to the cable interface and
interrupt circuits.
Port A Port B -
Node address input (8 bit binary value).
85
NETWORK
SERVER
FIGURE 2.
PC-LAN SYSTEM RING CONFIGURATION
Computer Interface:
Power:
+5VDC(±5%)
+ 12VDC (± 5%)
-5VDC(±5%)
Bus compatibility: IBM PC, Compaq, etc.
SPECIFICATIONS
Physical:
width: 4.25" (10.8 cm.)
Length: 13.32" (33.8 cm.)
Thickness: .60" (1.5 cm.)
Weight: 11 oz. (312 g.)
Environmental:
Operating Temperature 0 to + 55°C
Relative Humidity to 90% (without condensation)
Network Cable Type:
Belden 9855/UL 2582 (standard)
Belden 89855 (Plenum)
Network Specifications:
Data Rate: 1.0 Mbitlsec
Packet size: 1 to 4095 bytes
Access Protocol: Token Passing
Maximum number of nodes: 254
Buffer size: 65536 bytes + parity
Buffer access: dual port RAM
Maximum length: greater than 10,000 ft.
Maximum dis!. between nodes/repeaters: 500 ft.
Frame format: similar to HDLC
Error detection: CRC16-CCITT (16 bit CRC)
Cable Connectors:
9-pin male D-type
9-pin female D-type
Cable Interface:
Impedance: 100 ohm balanced
Min. signal level: 25 mv differential
EMI susceptibility:
2 volts/meter from 10 kHz through 30 MHz
5 volts/meter from 30 MHz through 1 GHz
RFI emission:
Complies with Part 15, Subpart J of FCC 47 CFR
Address Space Required:
Memory: 65536 bytes contiguous; selectable on any
64Kbyte boundary
Ports: 280h through 29Fh inclusive
Interrupts: optional; one required if used
DMA: Provided by 2840; IBM channels not used
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western
Digital Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the
right to change specifications at anytime without notice.
86
Prtnted In
u.s A
WESTERN DIGITAL
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WD2511 X.25 Packet Network Interface (LAPB)
FEATURES
NO
CONNECTION
REPLY
WE
CS
RE
ClK
MR
DAlO
DAll
DAl2
DAl3
DAl4
DAl5
DAl6
DAl7
RD
• Packet switching controller, complies with CCITT
Recommendation X.25, level 2, LAPB.
• Programmable primary timer (T1) and retransmission counter (N2).
• Programmable A-field which provides a wider range
of applications than defined by X.25. These include:
DTE-to-DTE connection, multipoint and loop-back
testing.
• Direct memory access (DMA) transfer: two channels; one for transmit and one for receive. Sendl
receive data accessed by indirect addressing
method. Sixteen output address lines.
• Zero bit insertion and deletion.
RC
• Automatic appending and testing of FCS field.
(GND)VSS
• Computer bus interface structure: 8 bit bi-directional
data bus. CS, WE, RE and four input address lines.
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TC
TO
RTS
CTS
DROO
DROI
• DC to 1.1 MBPS data rate.
• TTL compatible.
• 48 pin dual in-line packages.
21
23
24
VCC(+5V)
IAl
lAO
IA2
IA3
INTR
VDD( +12V)
A5
A4
A3
A2
A15
A14
A13
A12
All
Al0
A9
A8
A7
A6
AO
A1
DACK
PIN DESIGNATION
DESCRIPTION
APPLICATIONS
The WD2511 is a MOSILSI device which handles bitoriented, full-duplex serial data communications with
DMA, which conforms to CCID X.25's LAPB with programmable enhancements.
X.25 PACKET SWITCHING CONTROLLER
PART OF DTE OR DCE
PRIVATE PACKET NETWORKS
LINK LEVEL CONTROLLER
STORE AND FORWARD SYSTEM
HIGH REL POINT TO POINT COMMUNICATIONS
BIT ORIENTED PROTOCALS WITH BUILT IN DMA
The device is fabricated in N-Channel silicon gate MOS
technology and is TTL compatible on all inputs and
outputs.
87
INTERFACE SIGNALS DESCRIPTION (All signals are TIL compatible.)
PIN
NUMBER
SYMBOL
1
FUNCTION
PIN NAME
No Connection
Leave pin open.
Reply
An active low output indicates the WD2511 has
either a CS-RE or a CS-WE input condition.
2
REPLY
3
WE
Write Enable
The data on the DAl are written into the
selected register when CS and WE are low.
4
CS
Chip Select
Active low chip select for CPU control of 110
registers.
5
RE
Read Enable
The contents of the selected register is placed
on DAl when CS and RE are low.
6
ClK
Clock
Clock input used for internal timing. Must be
square wave and should be greater than 500
KHz.
7
MR
Master Reset
Active low initializes the chip. All registers reset
to zero, except control bits MDISC and LINK
which are set to 1. DACK must be stable high
before MR goes high.
8-15
DAlO-DAl7
Data Access Lines
An 8-bit bi-directional three-state data bus for
CPU and DMA controlled transfers.
16
RD
Receive Data
Receive serial data input.
17
RC
Receive Clock
This is a 1x clock input. RD is sampled on the
rising edge of RC.
18
VSS
Ground
Ground.
19
TC
Transmit Clock
A 1x clock input. TD changes on the falling
edgeofTC.
20
TD
Transmit Data
Transmit serial data output.
21
RTS
Request-To-Send
An open collector (drain) output which goes
low when the WD2511 is ready to transmit
either flags or data.
22
CTS
Clear-To-Send
An active low input which signals the WD2511
that transmission may begin. If high, the TD
output is forced high. May be hard-wired to
ground.
23
DRQO
DMA Request Out
An active low output signal which initiates CPU
bus request so the WD2511 can output data
onto the bus.
24
DRQI
DMA Request In
An active low output signal which intitiates
CPU bus request so that data may be input to
theWD2511.
25
DACK
DMA Acknowledge
An active low input from the CPU in response
to DRQI or DRQO. DACK must not be low if CS
and RE are low or if CS and WE are low.
27,26,
38-41,
28-37
AO-A15
Address Lines Out
Sixteen address outputs from the WD2511 for
DMA operation. If the control bit ADRV is 1; the
outputs are TIL drives at all times. If ADRV is 0,
the outputs are three-state, and are HI-Z whenever DACK is high. (ADRV is in Control Register #1.)
42
VDD
Power Supply
+ 12VDC power supply input.
88
INTERFACE SIGNALS DESCRIPTION CONTINUED (All signals are TTL compatible,)
PIN
NUMBER
SYMBOL
43
INTR
Interrupt Request
An active low interrupt service request output
Returns to high when Status Register #1 is
read,
46,47,
45,44
IAO-IA3
Address Lines In
Four address inputs for CPU controlled read/
write operation of the 110 registers in the
WD2511, If ADRV = 0, these may be tied to AOA3, (ADRV is in Control Register = 1,)
48
VCC
Power Supply
+ 5VDC power supply input
FUNCTION
PIN NAME
ORGANIZATION
receive, and one for overall control.
Note: See appendix 0 for a glossary of terms used
throughout this document
Parallel transmit data are entered into the Transmitter
Holding Register (THR), and then presented to the
Transmitter Register (TR) which converts the data to a
serial bit stream, The Cyclic Redundancy Check (CRC)
is computed in the 16-bit CRC register, and the result
becomes the transmitted Frame Check Sequence
(FCS),
A detailed block diagram of the WD2511 is shown in
Figure 1,
Mode control and monitor of status by the user's CPU is
performed through the Read/Write Control circuit
which reads from or writes into I/O registers addressed
by IAO-IA3,
Parallel receive data enters the Receiver Holding Register (RHR) from the 24-bit serial Receiver Register
(RR), The 24-bit length of RR permits stripping of the
FCS prior to transfer in to the RHA. The receiver CRC
register is used to test the validity of the received FCS,
A 3-stack FIFO is included in the receiver,
Transmit and receive data are accessed through the
DMA control. Serial data is generated and received by
the bit-oriented controllers,
Internal Control of the WD2511 is by means of three
internal microcontrollers; one for transmit, one for
8 BIT OAL
MICRO
C
110
0
r-----I~IREGISTERS
IAO,IA3
N
T
R
REPLY
0
16 x8
INTERNAL
REGISTERS""'"
16X8
L
L
E
R
OMA
A
0
0
R
E
S
S
E
S
OMA
CONTROL
LOGIC
OACK
AO,A15
+12V~
+5V_
MR _
TRANSMITTER
MICRO,CONTROLLER
CLK_
GNO_
RO
TO
Figure 1
WD2511 BLOCK DIAGRAM -
89
DETAILED
:e
c
N
U1
.....
.....
FRAME FORMAT
After the frame is received, if there were no errors then
the remainder in the CRC register (internal in the
W02511) will be:
1111000010111000 FOB8
The WD2511 generates and tests the Flag, FCS, AField, C-Field, and performs zero bit insertion and
deletion.
The WD2511 performs "bit-oriented" data communications control. According to the general format for bit-oriented procedures (HDLC, SOLC, ADCCP), each serial
block of data is called a frame.
Each frame starts and ends with a Flag (01111110). A
single flag may be used both as the closing flag of one
frame and the opening flag of the next frame. In
between flags, data transparency is provided by the
insertion of a 0 bit after all sequences of 5 contiguous 1
bits. The receiver will strip the inserted 0 bits. The last
16-bits before the closing flag is in the Frame Check
Sequence (FCS). Each frame also includes address
and control fields (A and C fields).
According to the X.25 protocol, there are three types of
frames: supervisory (S-frame), un-numbered (Uframe), and information (I-frame). The WD2511 performs frame level {level 2) link access control. All S- and
U-frames are automatically generated and tested by
the WD2511. The user need only be concerned with the
I-frames, which are packets.
The FCS calculation includes all data between the
opening flag and the first bit of the FCS, except for O's
inserted for transparency. The 16-bit FCS has the following characteristics:
Polynomial = X16 + X12 + X5 + 1
Transmitted Polarity -Inverted
Transmitted Order -High Order Bit First
Preset Value
-All I's
The WD2511 will transmit contiguous flags for
interframe time fill (full duplex mode).
..
I·FRAME (PACKET)
I"
I·FIELD (PACKET DATA)
14
FLAG
~
ADDRESS CONTROL
K""""
PACKET
CONTROL
INFORMATION
K."cm"
"I
USER DATA
~,"~~:~'~X'25
APPENDED--~_----
DMAACCESSED
FLAG
FCS
..
LEVEL2j
APPENDED
BY
BY
WD2511
WD2511
X.25 MODE
NOTE: X.25 Level 1, is the Physical Interface
90
MODEM
CONTROLS
CPU INTERFACE
=e
c
I..
N
....
CII
....
00
~I
OJ
=i
0
»
r
illl ~I
5>
@I 95>
'"
£7
~I ~I '"
C)
r
~I §I ~I
~CTC
TO
WD2511
MEMORY
CTS
LEVEL 1
RTS
AO-A15
16
INTERFACE
r-
MODEM
RC
RD
1 1 1
+12VDC +5VDC
Figure 2.
GND
SYSTEM CONNECTION
II. PROGRAMMING THROUGH REGISTERS
Control, status, and error bits will be referred to as CR,
SR, or ER, respectively, along with two digits. For
example, SR16 refers to status register #1 and bit 6,
which is "XBA:'
The WD2511 is controlled and monitored by sixteen 110
registers.
REGISTER DEFINITION
REG
#
0
1
2
3
4
5
6
7
8
9
IA3
IA2
IA1
lAO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
1
1
1
1
0
A
B
C
D
1
1
1
1
E
F
1
1
1
1
1
1
1
1
1
1
REGISTER
CRO
CR1
"SRO
"SR1
"SR2
"ERO
REGISTER
GROUPING
OVERALL CONTROL
AND
MONITOR
"CHAIN MONITOR
"RECEIVED C-FIELD
T1
N2fT1
RECEIVER
MONITOR
TIMER
TLOOKHI
TLOOKLO
CHAIN/BUFFER SIZE
NOT USED
XMT COMMAND "E"
XMT RESPONSE "F" (Note 1)
"CPU READ ONLY. (Write Not Possible)
NOTE:
1. Registers E and F should be set-up while MDISC = 1.
91
DMASET-UP
"Pt FIELD
i
r
CONTROL, STATUS, ERROR REGISTERS
=:c
N
U1
....a.
....a.
BIT#
REGISTER
7
6
5
4
3
2
1
0
LOOP
TEST
RAMT
RECR
MDISC
CRO
ADISC
0
H/F
ACTIVE/
PASSIVE
CR1
TXMT
TRCV
XI
ADRV
0
0
0
SEND
SRO
NA2
1PKR
NA1
1XBA
NAO
RNRR
NB2
NB1
NBO
RNRX
1ERROR
0
NE2
NE1
NEO
0
0
0
0
0
LINK
ER04
ER03
ER02
ER01
EROO
SR1
SR2
T10UT
IRTS
REC
IDLE
ERO
ERO?
ER06
ER05
1 Causes Interrupt (INTR Goes Low).
CONTROL REGISTER 0
REGISTER
CRO
CR07
ADISC
CR06
0
CR05
CR04
CR03
CR02
CR01
CROO
H/F
ACTIVE/
PASSIVE
LOOP
TEST
RAMT
RECR
MDISC
BIT
DESCRIPTION
CROO
MDISC (mandatory disconnect command) MDISC will cause a logical disconnect in the
link. No DMA accessed data will be transferred as long as MDISC = 1. After Master
Reset, MDISC will be set. The WD2511 will neither transmit nor accept received data
until MDISC = O.
CR01
RECR (Receiver Ready) indicates the CPU's is receiver buffer is Ready (CR01
RECR = 1, the WD2511 may begin receiving I-frames. (See SROO)
= 1). If
CR02
RAMT - Internal Register Test when set. (See Self Tests)
CR03
The LOOP TEST bit will connect the transmit data output to the receive data input. The
receiver input pins RD and RC are then logically disconnected from the internal circuitry.
The "E" and "F" data registers of the A-field must be equal.
CR04
The Active/Passive bit when set, in conjunction with MDISC = 0, will cause the WD2511
to initiate link set-up. When this bit is reset, the WD2511 will wait for a link setup from the
remote station.
CR05
H/F selects full duplex if CR05 == 0, and half duplex if CR05
CR06
Unused control bits should remain at O.
CRO?
ADISC (disconnect) is used when CR04 = 1 (ACTIVE). When the WD2511 actively initiates link set-up, a DISC will be transmitted and acknowledged prior to transmission of
the SABM if CRO? = O. If CRO? = 1, the WD2511 will send only the SABM.
92
= 1. (See Appendix A).
CONTROL REGISTER 1
REGISTER
CR1
I
I
CR17
TXMT
BIT
CR10
I
I
CR16
I
I
CR15
XI
I
I
CR14
I
I
CR13
I
I
CR12
I
I
CR11
I
I
CR10
SEND
0
0
0
DESCRIPTION
The SEND bit is used to command the WD2511 to send the next packet or packets. If
SEND = 1, the WD2511 will read from TLOOK the BRDY bit of the next segment for
transmission. If BRDY = 0, the WD2511 will clear SEND and no action occurs. If BRDY
= 1, the WD2511 will then read TSADR and TCNT, followed by the transmission of that
buffer. After transmission, the WD2511 clears BRDY ofthe segment just transmitted, and
reads BRDY ofthe next segment. If 1, the next segment is transmitted. If 0, the SEND bit
is cleared, and transmission of packets is stopped. As a matter of good practice, the CPU
should set SEND each time a BRDY bit is set.
TRCV
ADRV
CR11-13
Unused bits, write in O's.
CR14
The ADRV (ADDRESS VALID) bit is the control for the 16 bit output addresses (AO-A 15).
If ADRV = 0, the outputs are tri-state and are in HI-Z, except when DACK is low. If ADRV
= 1, the outputs are always low impedance (TTL), and are forced high-level (logical 1)
when DROO, DROI and DACK are all high.
CR15
Xi - J..Transparent I-field) Used when TXMT = 1
2:9 = O.Frame ~ 3 bytes excluding FCS and Flag.
XI = 1.Frame < 3 bytes excluding FCS and Flag.
CR16
TRCV - Transparent Receive. Receive all frames including unknown frames. See
Appendix A.
CR17
TXMT - Transparent transmit. See Appendix A.
STATUS REGISTER 0
REGISTER
SRO
I
I
SR07
NA2
I
I
SR06
NA1
I
I
SR05
NAO
I
I
SR04
RNRR
BIT
SROO
I
I
SR03
NB2
DESCRIPTION
I
I
SR02
NB1
I
I
SR01
NBO
I
I
SROO
RNRX
RNRX. An RNR has been transmitted or will be at next opportunity. The CPU should set
RECR when receive buffers are available.
SR03-SR01
NB2-NBO. Next block to be transmitted.
SR04
RNRR. This bit is set when an RNR frame is received. Once set, it is cleared when an
RR, REJ, SABM, or UA is received:
SR07-SR05
NA2-NAO. Next block of transmitted data to be Acknowledged.
93
r
STATUS REGISTER 1
:ec
REGISTER I
SR17
I
SR16
I
1PKR
I
1XBA
SR1
I\,)
BIT
CJ'1
.....
.....
SR15
I
SR14
I
I 1ERROR I
°
°
°
SR10
I
SR13
I
NE2
DESCRIPTION
I
SR12
I
SR11
I
SR10
I
NE1
I
NEO
I
°
(not used)
NE2-NEO, Next Expected packet number and next RlOOK segment number,
SR13-SR11
SR14
(not used)
The ERROR bit indicates: 1) An error has occurred which is not recoverable by the
WD2511 or 2) A significant event has occured,
SR151
For the specific reason for the ERROR bit being set, see error register (ERO) on next
page,
SR161
The XBA (transmitted block acknowledgement) bit set, indicates that a previously transmitted Block, or Blocks, have been acknowledged by the remote device, Upon acknowledgement, the AGK'ED bit is set to "1" for each segment in TlOOK which was
acknowledged,
SR171
The PKR bit stands for Packet Received, PKR = 1 indicates a packet has been received
error-free and in correct sequence according to the received N (S) count. The I-field data
has been placed in the host's RAM memory, NE is advanced,
NOTE 1:
The three interrupt-causing bits are SR17, SR16, and
SR15, Any of the three will cause an interrupt request
(INTR goes low), After SR1 is read, all three bits are
resetto 0, and INTR returns to high,
STATUS REGISTER 2
REGISTER
SR2
SR27
T10UT
SR26
SR25
IRTS
REG
IDLE
BIT
SR24
SR23
SR22
SR21
°
0
0
0
SR20
-liNK
DESCRIPTION
SR20
If the link is established, liNK = 0, If the link is logically disconnected, liNK = 1,
ST24-21
Unused Bits - 0,
SR25
REG IDLE (Receiver Idle) indicates that the WD2511 has received at least 15 contiguous
1's,
SR26
IRTS stands for the Internal Request-To-Send bit, and indicates that the transmitter is
attempting (successful or not) to send either data or flags,
SR27
T1 OUT bit means that timer T1 has timed-out. This bit returns to 0 when T1 is re-started,
When T1 OUT = 1, T1 is not running, NOTE: This bit could be a 1 for a few microseconds
in between intervals when T1 stops and is restarted,
94
ERROR REGISTER (ERO)
HEX
VALUE
ERROR/EVENT
02
Receiver overrun. The Receiver Register (RR) had a character to load into the FIFO but the
FIFO was full. See note 2.
04
Transmitter underrun. The Transmitter (TR) needed a character from the Transmitter Holding Register (THR) but the THR was not ready. The frame being transmitted is aborted. See
note 2.
10
RLOOK not ready. REC ROY bit of next segment is 0 but RECR
occur if RECR = O.
21
Link is up. Was down.
22
DISC sent. REC IDLE for time T1 xN2.
24
DISC sent. SABM sent N2 times without receiving UA.
30
Received DISC or OM while link was up.
41
Going to next chain segment.
42
Next chain segment of the Receiver was not ready.
= 1. This interrupt will not
80
Link reset (SABM) received.
88
S-command sent N2 times without acknowledgement.
CO
Frame Reject (FRMR) received. See note 1.
C1
Frame Reject (FRMR) transmitted. See note 3. The received C-field (returned in the first
I-field byte of the FRMR frame) was invalid.
C3
Frame Reject (FRMR) transmitted. See note 3. The received and rejected frame contained
an I-field which is not permitted with this frame type.
C4
Frame Reject (FRMR) transmitted. See note 3. Received I-field exceeded the total amount
of I-field data bytes established in Register C.
C8
Frame Reject (FRMR) transmitted. See note 3. The received frame contained an invalid
N(R).
Y set to 1 indicates the received I-field exceeded the
maximum I-field data byte count established (CHAIN/
BUFFER SIZE). Y is mutually exclusive with W.
NOTES:
1. Whenever a Frame Reject (FRMR) is received, the
I-field will have been placed in the appropriate memory location by the DMA. A link reset (SABM) will be
transmitted. The NB is not advanced.
Z set to 1 indicates the received control field contained
an invalid N(R). Z is mutually exclusive with W.
2. Receiver overrun and Transmitter underrun are indication that the Te/RC clocks are either too fast for
the WD2511, or the DACK response is too slow, or
both.
Upon receiving a FRMR, the WD2511 will place the 3
byte I-field in memory by DMA, just as if the FRMR were
a packet.
When the WD2511 transmits a FRMR, the frame reject
condition is entered. Only a received SABM or DISC
will clear this condition. If any other command is
receiVed, the WD2511 will re-transmit the FRMR. Also,
the WD2511 will not transmit packets while in the
frame reject condition.
3. As a result of FRMR transmitted, a SABM is
received, causing link reset. In this case, only the
Frame Reject interrupt is indicated.
w, X, V, Z OF FRMR
A frame reject (FRMR) contains a three byte I-field. The
first byte is the rejected frame control field. The second
byte contains the current N(S) and N(R) counts of the
station reporting the reject condition. The third byte
contains W-X-Y-Z-O-O-O-O where W is the LSB.
In the FRMR I-field, bit #4 of the second byte is a "1 " if
the rejected frame was a response and a "0" if the
frame was a command.
W set to 1 indicates that the control field received and
returned in the first I-field byte was invalid.
The WD2511 memory access is accomplished by the
use of DMA and two look-up tables. These tables are
set-up to allow up to 7 I-frames to be outstanding in
each direction of the communications link. The look-up
tables are divided into a transmit and a receive area
(TLOOK and RLOOK) and are located in memory external to the WD2511.
MEMORY ACCESS METHOD
X set to 1 indicates the rejected frame contained an
I-field which is not permitted with this command.
W is also set to 1 in this case.
95
=e
cI\)
c.n
.....
.....
the flag, address, and control fields. Next, the information field data will be transmitted using DMA from the
"SEND #0 PACKET" memory buffer. At the end of the
information field, the WD2511 will automatically send
the FCS and closing Flag. The WD2511 will then move
on to the next packet.
TLOOK
RLOOK
These tables contain address and control information
for individual Transmit/Receiver packets.
To provide the WD2511 access to TLOOK and RLOOK
load only the starting address of TLOOK into the
WD2511 registers A and S.
If retransmission of one or more (up to seven) packets
becomes necessary, the WD2511 will automatically
retrace the previous transmissions through the TLOOK
table. The user's CPU software does not become
involved in the retransmission. However, an ERROR
COUNTER is incremented. (See Error Counter
Section.)
REGA
REGS
AO-A 15 16 bit TLOOK starting address
RECEIVE
The TLOOK and RLOOK tables are each divided into 8
segments and each segment contains 8 bytes. Figure 3
illustrates the segmentation of TLOOK and RLOOK.
Figure 5 and 6 illustrate the contents of a single TLOOK
and RLOOK segment.
When received, each frame is checked for correct
address and FCS fields and for type of control field. If
the frame is a packet, the information field is placed in
the assigned memory location in a method similar to
that used in transmit mode. If the packet is received
error-free and in proper N{S) sequence count, an interrupt is generated and the WD2511 is ready for the next
packet which will be placed in the next location.
TRANSMIT
To transmit, the WD2511 will have read from TLOOK
the starting address and length of the first packet to be
transmitted. The WD2511 will automatically transmit
Figure 4 shows a "store-and-forward" example that is
useful in a network node.
TSADR#O
TLOOK
TCNT
#0
SEGMENT 0
SEGMENT 1
SEGMENT 2
TSADRN1
SEGMENT3
SEND
PACKET
#1
(FIRST PART)
SEGMENT4
SEGMENTS
XFRADR
RECEIVE
PACKET NO
(FIRST BLOCK)
SEGMENT 3
SEGMENT 4
SEGMENTS
FOR THIS EXAMPLE,
TCNTN11S
GREATER THAN
BUFFER SIZE. THUS.
SECOND PART
OFN11S
CHAINED.
RECEIVE
PACKET NO
(SECOND BLOCK)
XFR ADR
SEGMENT 6
SEGMENT7
ERROR
COUNTERS
SEND
PACKET#1
(SECOND PART)
LIM
~
XFR ADR
Figure 3. MEMORY ACCESS SCHEME
96
r - -
I
MEMORV __ I
I
- - -
CHA - - - - - - - - - - - - - LOOK-UP
TABLE
C~B
-
°
TLOOK
I
-
-
-,
TLOOK
2
I
3
I
I
4
I
:
I
7
:
-
LOOK-UP
TABLE
RLOOK
0:1
I
4
i
;
L __ /
WD2511
CHA
SE"AL
RECEIVE
CHANNEL A
/
/---_~
TSAD~
/ RSADR #3
I/V(CiHA
RCNT #3
CH A
:
'- ..~1-----6-t
BB~~~R
CTH
B
7
1 - - - - -0-1
2
3
RECEIVED
THRU
TCNT #6
CH A
CH B
lt~~l
RLOOK
1
:
~-- ~
______________
After the Data Buffer is received by CH A, the length (RCNT) is
in RLOOK segment #3. The CPU interrogates the packet header
(at tKe beginning of the Data Buffer) and concludes that the
buffer must be send out of CH B. RSADR, RCNT, and the
residual information are transferred from #3 segment to next
available TLOOK segment in CH B which is #6 in this example.
WD2511
CH B
+
SERIAL
TRANSMIT
CHANNEL B
Figure 4. STORE-AND-FORWARD EXAMPLE
TLOOK AND RLOOK
Figures 5 and 6 detail the individual segments for
TlOOK and RlOOK.
BRDY means that the transmit buffer is ready. The
WD2511 will send the block only after the CPU sets
BRDY = 1. (BRDY is used in conjunction with the
SEND bit.) At the completion of the transmission, the
WD2511 will set BRDY = 0 and then read the BRDY of
the next segment.
After transmitting a packet, an acknowledgement must
be received from the remote device. The acknowledgement is contained in the received N(R) count of an Iframe or S-frame. Upon acknowledgement, the
WD2511 will set ACK'ED = 1, and generate a blockacknowledged interrupt. Before assigning a new block
to a segment in TlOOK, the CPU must make sure that
the previous block which used that segment number
has been acknowledged.
REC ROY informs the WD2511 that the receive buffer is
ready. The WD2511 will not receive a packet into a
buffer referenced by a particular segment until REC
ROY = 1. If the WD2511 progresses to a segment
which has REC ROY = 0, an error interrupt will be
generated.
After receiving an error-free packet with correct N(S),
the WD2511 will, in order: 1) Set FRCMl (Frame
Complete), clear REC ROY and store received residual
count. 2) Store the received length, in characters, of the
I-field in RCNT HI and RCNT La. 3) Advance the NE
count and generate a packet received interrupt. 4)
Acknowledge the received packet at the first opportunity.
The addresses (TSADR and RSADR) are 16-bit binary
addresses. HI represents the upper 8-bits and lO represents the lower 8-bits. The counts (TCNT and RCNT)
are 12-bit binary numbers for the number of characters
in the I-field.
TSADR is the starting address of the buffer to transmit
and TCNT is the binary count of the number of bytes to
transmit.
RSADR is the starting address of the receive buffer.
After successfully receiving the packets, the WD2511
will write the value of RCNT which is the binary length
of the received packet.
Whether the WD2511 accesses a look-up table or a
memory block, a DMA Cycle is required for each
access.
97
BIT #
:ec
N
U'I
.....
.....
BYTE#IN
SEGMENT
7
6
5
4
3
2
1
0
1
ACK'ED
NU
NU
NU
NU
NU
NU
BRDY
2
TSADR HI
3
TSADRLO
4
TCNTHI
SPARE
5
6
SPARE FOR USER DEFINITION
7
SPARE
8
SPARE
TCNTLO
NU = Not Used
FIGURE 5.
TLOOK SEGMENT
The control bits in TLOOK (BRDY and ACK'ED) and in
RLOOK (FRCML and REC ROY) define various states
for each segment. These states are shown below:
TLOOK STATES
ACK'ED
BRDY
0
1
STATE
Ready To Transmit (CPU set BRDY, cleared ACK'ED)
0
0
"Transmitted and Awaiting Acknowledge (WD2511 cleared BRDY)
1
0
Received Acknowledge (WD2511 set ACK'ED)
1
1
This state not allowed
"State 0-0 could also occur whenever there is no data ready to send.
BIT#
BYTE # IN
SEGMENT
1
7
FRCML"
6
NU
5
NU
NU
RES2
2
RSADR HI
3
RSADRLO
4
2
3
4
RES1
NOT USED
1
0
RESO
REC
ROY
RCNTHI
5
RCNTLO
6
SPARE FOR USER DEFINITION
7
SPARE
8
SPARE
NU = Not Used (NOTE: The "not used" bits may be either 1 or 0).
"FRCML = Frame Complete
FIGURE 6.
RLOOK SEGMENT
98
CPU SETS
BRDY
~ '-----~
CPU
CLEARS
ACK'ED
RECEIVED
ACKNOWLEDGE
1-0
==
C
I\)
c.n
....
CPU CLEARS ACK'ED
AND SETS BRDY
....
DATA HAS BEEN
SENT WAITING
FOR ACKNOWLEDGE
WD2511 SETS
ACK'ED
a-a
TLOOK SEGMENT STATE FLOW
Notice that in a TLOOK segment, the 0-0 state could
have two meanings, Due to control internal to the
WD2511, this will not pose an ambiguityto the WD2511,
However, if it is a difficulty to the CPU, the CPU could at
start-up, set all ACK'ED bits, Since this would only be a
start-up procedure, this would not violate the "deadly
embrace" rule,
In the "WAITING FOR ACKNOWLEDGE" state, one or
more re-transmissions could occur,
RLOOK STATES
FRCML
RECRDY
0
1
Ready To Receive (CPU set REC RDY, cleared FRCML)
Received Packet (WD2511 set FRCML, cleared REC RDY)
STATE
1
0
0
0
Not Ready (CPU cleared FRCML)
1
1
This state not allowed
NOT
READY
CPU SETS
RECRDY------.
a-a
,-=----,
CPU
CLEARS
FRCML
READY TO
RECEIVE
0-1
CPU CLEARS
FRCML,AND
SETS
REC ROY
WD2511 CLEARS REC ROY
AND SETS FRCML
PACKET HAS
BEEN RECEIVED
1,0
RLOOK SEGMENT STATE FLOW
REGISTER
C
BUFFER SIZE
CHAIN
Bit
7
I
Bit
6
I
Bit
5
I
Bit
4
CHAINING/BUFFER SIZE
Bit
3
I
Bit
2
I
Bit
1
1
Bit
0
segments allowed in addition to the first segment. (If
this feature is not used, make CHAIN all O's.)
The WD2511 includes a chained-block feature which
allows the user more efficient use of memory particularly in situations where the maximum packet size is
much larger than the average packet size,
The lower 4 bits of Register C define the buffer size,
which is the size of the buffer in multiples of 64 bytes
including the transfer address (XFR ADR), If buffer size
is 0000, the size is 64, For 0001, the size is 128, and so
on,
Register C is used to program the chaining feature, The
upper 4 bits define CHAIN which is the number of chain
99
The maximum amount of I-field data bytes that can be
contained in this buffer is the buffer size minus 2 bytes
(XFR ADR) for all transmitter and receiver chaining
blocks, except for the last receiver chaining block. For
this block, the maximum amount of I-field data bytes is
the buffer size minus 3.
RULE: If a bit is set by the CPU, it will not be set
by the WD2511, and vice versa. If a bit is
cleared by the WD2511, it will not be
cleared by the CPU, and vice versa.
As an example, the BRDY bit in the TLOOK segments
is only set by the CPU and only cleared by the WD2511.
For example, suppose that the buffer size defines a
segment size of 128 and that CHAIN defines 8 additional segments in addition to the first. (Register C
would be hex 81 in this example.) When 126 bytes of
I-field data have been received, the WD2511 will read
the next two buffer bytes as a transfer address (XFR
ADR) pointing to another segment. At the end of that
segment is another XFR ADR, and so on, up to a maximum of 9 total segments, (in this example).
SEND BIT CONTENTION
The WD2511 may be clearing the Send bit when the
host is setting it. To insure that the bit is set the host
should read the status of the Send bit after it is set. If
the Send bit is cleared the host should set it again.
TLOOK AND RLOOK POINTERS
For the receiver, a XFR ADR of all O's will mean that the
next segment is not ready. If the WD2511 reaches a
XFR ADR on the receiver with all Os, there will be an
Error Interrupt code 42. Otherwise, there will be an
Interrupt code 41 which is a status indication that the
WD2511 is going to the next segment. I/O Register 6
upper 4 bits gives a status of which chain segment is
currently being used.
There are three 3-bit counters for the status of the segments in TLOOK and RLOOK. Status Register #0
(SRO) contains counters NA and NB which are used in
conjunction with TLOOK. NB is the segment number of
the next block to be transmitted and is advanced at the
end of each block transmission. NA is the value of the
segment of the next block to be acknowledged. If all
transmitted blocks have been acknowledged, then NA
= NB.
The transmitter chaining works like the receiver with
the following exceptions:
1. XFR ADR
ready.
In SRl is a 3-bit counter, NE, used in conjunction with
RLOOK. NE is the value of the segment number where
the next received packet will be placed.
= all O's will not indicate next segment not
NA = Next to be Acknowledged
2. There is no interrupt when going from one segment
to another.
3. There is no status of the current segment being
used.
NB = Next Block to be Transmitted
NE = Next Expected to be Received
4. Last chaining block is allowed to contain one more
I-field data byte.
VARIABLE BIT LENGTH
AND RESIDUAL BITS
Total amount of I-field data bytes in receiver = (64 x (1
+ BUFFER SIZE) - 2) x (1 + CHAIN) - 1.
The WD2511 will only send 8 bits per character and all
transmitted frames will have an integral number of
bytes.
The total amount of I-field data bytes in transmitter =
(64 x (1 + BUFFER SIZE) - 2) x (1 + CHAIN).
The WD2511 may receive a packet with, or without, an
integral number of bytes. The "RES" bits in the
RLOOK tables indicate the number of received residual bits. The residual bits occupy the lower portion of
the last received character.
Also, note that the transmitter and receiver counts are
modified by 2 for each time a chain boundary is
crossed. For example, if BUFFER SIZE = 0001 (segment size = 128 bytes including XFR ADR), and if an
I-field of 270 bytes is to be transmitted, then there will
be two times that a chain boundary is crossed. The
TCNT must be made 274 to send 270 bytes. The same
is true for RCNT. Note that the largest block of data that
can be sent without chaining is 1021 bytes.
RES2 RESl
0
0
0
0
1
"DEADLY EMBRACE" PREVENTION
A "deadly embrace" can occur when two processors
reach a state where each is waiting for the other. In this
case, the two processors are the user's CPU and the
micro-controller inside the WD2511. Therefore, to prevent the "deadly embrace," the following rule is
obeyed by the WD2511 and should also be obeyed by
the user's CPU. This rule applies to TLOOK, RLOOK
and to the I/O registers. The Error Counters do not
apply to this rule.
1
1
1
100
0
0
1
1
0
0
1
1
RES 0
Received Residual Bits
0
1
0
1
0
1
0
1
0
7
6
5
4
3
2
1
OTHER 1/0 REGISTERS
RECEIVED C-FIELD
ERROR COUNTERS
Following contiguously after RLOOK are six 8-bit error
counters. The WD2511 will increment each counter at
the occurrence of the defined event. However, the
WD2511 will not increment past 255 (aIl1's). The CPU
has the responsibility of clearing each counter. The first
counter past RLOOK is #1, etc.
TIMER
TYPE OF ERROR
Registers 8 and 9 define a 10-bit timer (T1), and a 6-bit
Maximum Number of Transmissions and Retransmissions counter (N2).
'Received Frames with FCS Error
(includes frames ABORTed in the
I-field).
2
81T#
Received Short Frames (less than
32-bits)
3
REGISTER
"Number of times T1 ran-out
(completed)
4
T1
8
Not used
6
71&151413121110
9
LSB
N2
MSB
'REJ Frames Received
5
MSB
LSB
REJ Frames Transmitted
=
=
LSBjMSB
Most Significant Bit
Least Significant Bit
T1 provides the value of a delay in waiting for a
response andlor acknowledgement. The delay is the
binary count multiplied by time CT where:
'These counters are incremented only if the received
A-field is equal to either Register E or F.
"Incremented only when attempting to transmit a
command.
16384
CT = CLK sec
The Error Counters are accessed by the WD2511 transmitter DMA channel. Therefore, if multiple errors are
received while the WD2511 is transmitting a long frame,
only the last error will be counted. The only Counters
which could miss counts because of this are Counters
#1, #2, and #5. The error Counters are incremented
only when the link is up (iJj\j'i{ = 0).
Thus, if CLK = 1 MHz, then T1 may be set in increments 16.384 milliseconds, to a maximum delay of
16.78 seconds. All ones in T1 is maximum delay.
Once the CPU establishes T1 and N2, there is no need
into T1 and N2 again unless a master reset
(MR) has occurred, there is a power loss, or the CPU
needs to change T1 or N2. If a time-out occurs, the
WD2511 will still retain T1 and N2.
t~rite
The conditions for starting, stopping; or restarting T1
are shown below: CRe-start" means starting T1 before
it ran-out).
STARTT1
1.
2.
3.
I
r
I
ERROR
COUNTER
1
Register 7 is the C-field of the last received frame, provided the A-field of the frame was equal to either register E or F, the FCS was good, the frame contained 32 or
more bits, and the WD2511 is not waiting for a SABM or
DISC in response to a transmitted FRMR.
'I-frame sent and T1 not already
in progress due to previous Iframe.
'SABM or DISC sent. (N2
restarted at first occurrence)
4.
Receiver Idle (REC IDLE = 1)
5.
S - command sent
RE-STARTT1
, Acknowledgement received
to some, but not all, I-frames.
STOPT1
Acknowledgement received
for alii-frames.
'RNR received while link up.
-
UA or DM Received
'Frame sent, while REC IDLE
= 1
Detected REC IDLE = 0
-
'N2 is restarted.
"A" FIELD REGISTERS
Registers E and F= provide a programmable A-field.
This allows the WD2511 to be a super-set of the X.25
document. That is, the WD2511 can handle a wider
range of application than the DTE-DCE links defined
in X.25. These wider ranges include: DTE-to-DTE connection, multipoint, and loop-back testing.
101
=e
cI\)
U1
.....
.....
that each can transmit and receive commands and
responses. Whether a particular frame is to be taken
as a command or a Response is determined by the contents of the address field. Commands from the DCE and
the associated responses from the DTE use address
A (hex 03) .
If the WD2511 is strictly in an X.25 DTE-DCE link, use
the values shown below:
DTE
Register E = 01
Register F = 03
DCE
Register E = 03
Register F = 01
Commands from the DTE and the associated
responses from the DCE use address B (hex 01).
If performing a loop-back test, either internal (CR03 =
1) or external (CR03 = 0), registers E and F should be
the same.
The individual commands and responses are shown in
Figure 7.
V. LAPB PROCEDURE
USE OF POLL BIT
The Link Access Procedure Balanced (LAPB) is
described in CCITT Recommendation X.25 as the
Level 2 protocol for the Asynchronous Balanced Mode
(ABM).
One use of the Poll bit (P) is in conjunction with TimeOut Recovery. Timer T1 is started at the beginning of a
transmitted command provided it has not been previously started. If T1 runs out, the command will be
retransmitted with P = 1.lf T1 runs out again, the command will again be retransmitted, with P = 1 up to N2
times. At N2 + 1, an error interrupt will occur. If the
command was an S-frame (originally an I-frame), the
WD2511 will reset the link by transmitting a SABM. If
the command was a SABM, the WD2511 will send a
DISC. If a DISC, the WD2511 will continue to send a
DISC indefinitely.
Zero bit insertion/deletion, use of flags, and FCS are
part of Level 2, and have been discussed in this document.
The DTE is the Data Terminal Equipment and the DCE
is the Data Circuit Termination Equipment (the network
side of the DTE-DCE connection).
The DTE and DCE are each "combined" stations in
LAPB Commands and Responses (Bit 0 is transmitted first).
Only the FRMR and I-frame contain I-fields.
FRAME TYPE
COMMAND
RESPONSE
BIT#
7
6
5
4
3
P
N(S)
2
1
0
INFORMATION
(I)
I-FRAME
(PACKET)
UNNUMBERED
(U)
SABM
0
0
1
P
1
1
1
1
DISC
0
1
0
P
0
0
1
1
SUPERVISORY
(S)
N(R)
0
UA
0
1
1
F
0
0
1
1
FRMR
1
0
0
F
0
1
1
1
DM
0
0
0
RR
RR
RNR
RNR
*REJ
REJ
F
1
1
1
1
P/F
0
0
0
1
N(R)
P/F
0
1
0
1
N(R)
P/F
1
0
0
1
N(R)
*The WD2511 will not send a REJ command (will send REJ response, only), but may receive either a REJ command
or REJ response.
FIGURE 7.
102
TRANSMISSION OF ABORT
WD2511 ELECTRICAL SPECIFICATIONS:
An ABORT (seven contiguous 1's) is transmitted to terminate a frame in such a manner that the receiving station will ignore the frame. There are two conditions
which will cause the WD2511 to transmit an ABORT:
Voltages referenced to VSS
ABSOLUTE MAXIMUM RATINGS:
High Supply Voltage (VDD) .......... - 0.3 to + 15V
Voltage at any Pin ................. - 0.3 to + 15V
Operating Temperature Range ...... O°C to + 70°C
Storage Temperature Range .... - 55°C to + 125°C
1. Transmitter Under-Run
2. While transmitting a packet, a REJ is received.
NOTE:
Maximum limits indicate where permanent device
damage occurs. Continuous operation at these limits is
not intended and should be limited to those conditions
specified in the DC Electrical characteristics.
lOOP-BACK TEST
The loop-back may be internal (CR03 = 1) or external
(CR03 = 0). Of course, if external, RD and TD must be
tied together either directly or remotely.
If CR03 = 1, TD is internally tied to RD, and the RD signal (pin 16) is internally disconn~ed. Also, TC is internally tied to RC and the pin at RC (pin 17) is internally
disconnected. CTS must be connected externally to
GND or RTS.
Operating DC Characteristics: VSS
SYMBOL
= OV, VCC = + 5.0V ± 0.25, VSS = + 12.0V ± 0.6V TA = 0° to
PARAMETER
IDD
VDD Supply Current
MIN
TYP
MAX
UNIT
20
70
mA
ICC
VCC Supply Current
200
280
mA
VDD
High Voltage Supply
11.4
12
12.6
V
VCC
Low Voltage Supply
4.75
5
5.25
V
VIH
Input High Voltage
VIL
Input Low Voltage
2.4
+ 70°C
CONDITIONS
V
0.8
V
VOH
Output High Voltage
VOL
Output Low Voltage
0.4
V
ILH
Input Source Current
10
iJA
= -0.1mA
= 1.6mA
Vin = VCC
III
Input Sink Current
10
iJA
Vin
=:
10ZH
Output Leakage (High
Impedance)
50
iJA
Vin
= VCC
10Zl
Output Leakage (High
Impedance)
50
iJA
Vin
=
2.8
103
V
10
10
+O.4V
+O.4V
AC Timing Characteristics (AC):
SYMBOL
ClK
PARAMETER
Clock Frequency
MIN
0.5
TYP
MAX
UNIT
2.05
MHz
CONDITIONS
Note 1
RC
Receive Clock Range
0
MHz
Note 4
TC
Transmit Clock Range
0
MHz
Note 4
mS
MR
Master Reset Pulse Width
10
TAR
Input Address Valid to RE
0
TRD
Read Strobe (or DACK
Read) to Data Valid
2
375
nS
THD
Data Hold Time from Read
to Strobe
20
100
nS
THA
Address Hold Time from
Read Strobe
0
nS
TAW
Input Address Valid to
Trailing Edge of WE
100
nS
TWW
Minimum WE Pulse Width
200
nS
TDW
Data Valid to Trailing Edge
of WE or Trailing Edge of
DACK for DMA Write
100
nS
TWRR
CS High between Writes
300
nS
TRDR
CS High between RE
300
nS
RE Pulse Width
375
nS
TRR
nS
Note 5, 2
Note 2, 3
TDAK
DACK Pulse Width
375
TAHW
Address Hold Time after
WE
80
TDHW
Data Hold Time after WE or
after DACK for DMA Write
100
TDA1
Time from DRaa (or DROI)
to Output Address Valid if
ADRV = 1
80
nS
Note 3
TDAO
Time from DACK to Output
Address Valid if ADRV = 0
375
nS
Note 5
TDD
Time from leading Edge of
DACK to Trailing Edge of
DRaa (or DROI)
375
nS
Note 5
TDAH
Output Address Hold Time
from DACK
20
100
nS
TDMW
Data Hold Time from DACK
for DMAOut
20
100
nS
nS
TTDV
TDVaiid
100
nS
TSRD
RD Setup
0
nS
THRD
RDHold
320
nS
Note 2
NOTES:
1. Clock must have 50% duty cycle.
2. Th~ust not be a CPU read or write (CS-RE or CS-WE) within 500 nanoseconds after the trailing (rising) edge
of DACK.
3. There must notkthe leading (falling) edge of DACK allowed within 500 nanoseconds after the completion of a
CPU write (CS-WE).
4. See "Ordering Information"·for maximum serial rates.
5. C(load) = 100pf
6. Measured by discharging a 100pf capacitor to each pin through a 1K ohm resistor.
104
>.--
DALO-DAL7
, D A T A VALID
I
CPU READ (CS IS LOW)
DRQO,
AO-A15
(ADRV
TDD
I--- .j
TDA1
(AO-A15 SAME AS DMA OUT)
<
)
DRQj~
I
j.;=TDAO
r---
~
DALO-DAL7
TDAK
1
I-
1;:=
':,~~ ~_-_l~ ~ ~ ~ ~ ~~~ ~---~-~~ ~ ~ ~ ~)l-
DACK
TDHW
CPU WRITE (CS IS LOW)
;/
I
I
~~
AO-A15
(ADRV ~ 1)
1
-I
4
T DAH
(
DATA VALID )
;(
--..1
TDMW
DACK
I-
i
TDD
r-
"J
---1
/
TDAK
-1V
I..
TDW__
DALO-DAL7
<
I
LTRD....
DMAIN
DMAOUT
ORDERING INFORMATION
Order Number
Maximum Data Rate
WD2511AN-01
WD2511AN-05
WD2511AN-11
100 Kbps
500 Kbps
1.1 Mbps"
I:DH~!
DATA VALID
TD
"Higher speeds available on special order.
RD
TD-RD TIMING
105
>---
i
f..
APPENDIX A
:ec
N
U"I
.....
.....
Atthe end ofthe transparenttransmission, there will be
an interrupt with XBA = 1. The SEND bit will be
cleared, but the BRDY bit will not be cleared. The NB
pointer will not be incremented. To send another transparent frame, set SEND. To resume packet transmission, clear TXMT and set SEND. (Of course, the
TLOOK segment must be set-up prior to setting SEND.)
TRANSPARENT MODES
The WD2511 was originally intended to be a link level
controller meeting the requirements of X.25 LAPB and
this has been accomplished. However, there has been
an increasing demand from potential WD2511 users for
additional frame types not included in the LAPB frame
type repertoire.
If SEND is set while the link is down, a transmission will
occur even if TXMT = O. Under this condition, a packet
will be transmitted from current TLOOK segment, NB
and YeS) will be incremented, and the chip will go on to
the next TLOOK segment just as if the link were UP.
However, the WD2511 will expect no acknowledgment
to the packet(s). If the link is brought UP later, NB and
YeS) are cleared to 0 at the time the link comes UP.
For example, the Bell System standard, BX.25, calls for
the use of XID (exchange identification) in LAPB connections of DTE-to-DTE and in Dial access. (Of course,
DTE-to-DTE and Dial access are not X.25 in the strictest sense.) Also, Western Digital has received several
requests for the use of a SIM (set initialization mode).
Also, there has been one request to allow "unknown"
frames to pass thru the chip for the purpose of
teleloading.
The bit XI (CR15) is used only when TXMT = 1. XI
stands for Transmit I-field. If the frame contains three,
or more bytes, not counting FCS, set XI = O. If the
frame contains two bytes not counting FCS, set XI = 1.
When Xi = 1, only two frame bytes will be transmitted
regardless of TCNT. DO NOT attempt to transmit a
frame with TXMT = 1 and XI = 0 ifTCNT is 2,1, or O.
Therefore, we have added two selectable modes to the
WD2511: transparent transmit and transparent receive.
Basically, these two modes allow the user the option to
pass certain non-LAPB frames thru the chip without
controlling these frames according to the LAPB
protocol.
1.2 TRANSPARENT RECEIVE
For the purposes of this discussion, it is necessary to
define an "unknown frame:' That is, a frame which is
"unknown" to the WD2511.
FEATURES OF THE TRANSPARENT MODES
• May transmit any A and C field under transparent
control.
Unknown Frame: A U-frame (unnumbered) frame
which is not part of the LAPB repertoire. The U-frame
repertoire in LAPB is SABM, DISC, OM, UA, and
FRMR. For the purposes of this discussion, "UF" will
refer to an unknown frame without an I-field, and "UFI"
will refer to an unknown frame with a I-field.
• May receive any U-frame not part of the LAPB repertoire if transparent-receive enabled.
• Transparent modes are link state independent.
1.0 HOW THE TRANSPARENT MODES WORK
A received SREJ (Selective REJect), which is an Sframe, is not considered an unknown frame by the
WD2511. If the link is DOWN and an SREJ command is
received, a OM response will be sent. If the link is
DOWN and a SREJ response is received, the SREJ is
disregarded. If the link is UP and a SREJ command or
response is received, a FRMR will be sent with W = 1.
The WD2511 will treat a received SREJ the same
whether TRCV is 0 or 1.
Two control bits have been added. TXMT (CR17) is the
bit to enable the Transparent Transmit and TRCV
(CR16) will enable the Transparent Receive.
1.1 TRANSPARENT TRANSMIT
When TXMT = 1, the WD2511 will transmitthe frame in
the next TLOOK segment provided SEND (CR10) = 1
and BRDY of that TLOOK segment is 1. The link may
be either UP or DOWN. The WD2511 will not add the A
and C fields to the Transparent Transmitted frame. The
user's CPU must add these fields as the first two bytes
in the transmit buffer. Thus, the significance of the
transmit count (TCNT) is different from normal packet
transmission. In packet transmission, TCNT is the
count of the I-field. In transparent transmission, TCNT
is the I-field plus the A and C fields (I-field plus two
bytes).
A received packet (I-frame) response is not considered
an unknown frame by the WD2511. If the link is DOWN,
the frame is disregarded. If the link is Up, a FRMR will
be sent with W = 1 and X = 1. The received packet
response is treated the same whether TRCV is 0 or 1.
Whether TRCV is 0 or 1, the WD2511 will check all
received frames to insure that the A-field equals either
Register E or F, that the FCS is correct, and that the
framecontains32bitsormore.lfTRCV = 0, and if a UF
or UFI is received, and if the link is Up, the WD2511 will
send a FRMR with W = 1 (Wand X are 1 in the case of
a UFI). See "States of the WD2511:'
The timer, T1, will be disabled in transparent transmission. Therefore, if using this feature while the link is Up,
it is advised that TXMT be set only when there are no
outstanding (unacknowledged) packets which is indicated whenever NA = NB.
When TRCV = 1, the WD2511 will be enabled to
receive all frames. If the frame is "known" by the
WD2511, it will be treated according to the protocol just
as if TRCV = o. However, if the frame is a UF or UFI, it
will be passed on to the user's CPU.
106
will not cause a sequence problem in the protocol since
the actual V(R) is maintained in an internal register in
the WD2511. Note that NE is cleared when the link is
brought UP. Thus, if transparent receive is used only
when the link is DOWN, then NE will be equal to V(R).
When an unknown frame is received while TRCV = 1,
there will be an interrupt with ERROR = 1 and the Error
Register (ERO) will contain one of the following hexidecimal values:
ERO
FRAME RECEIVED
60
61
62
63
UFI Response
UFICommand
UF Response
UFCommand
A word of caution. If the next RLOOK segment is not
ready when a UFI is received, the Error Register (60 or
61) will be overwritten almost immediately with an error
code 10 (RLNR) and the user will not know if the
received UFI was a command or response.
If RECR is set while the link is DOWN, the WD2511 will
prepare to receive I-fields, whether TRCV is 0 or 1. If a
packet command is received, there will be a PKR interrupt, and the NE and V(R) will be incremented. Of
course, NE and V(R) are cleared once the link is
brought up.
The C-field of the received frame is contained in Register #7. If the frame had an I-field, the frame will be
placed in the next RLOOK segment and the value of
RCNTwili represent the count of bytes in the I-field (not
including the A and C fields). The RLOOK pointer, NE,
will be incremented. Therefore, the relationship
between NE and V(R) will not be guaranteed if transparent receive is used while the link is UP. However, this
TABLE 1.
The following tables show what action the WD2511 will
take when various frames are received.
PACKET RECEIVED (command, not response)
RLOOKREADY
TRCV
DOWN
NO
DOWN
YES
oor 1
oor 1
UP
NO
Oor1
If N(S) = V(RT), RNR sent, Else, REJ condition entered.
UP
YES
oor 1
If N(S) = V(R), PKR interrupt, V(R) and NE
incremented. Acknowledgement sent at
next opportunity. If N(S) not = V(R), enter
REJ condition.
LINK
RLOOKREADY
TRCV
DOWN
NO
Oor1
DISREGARD
DOWN
YES
0
DISREGARD
DOWN
YES
1
Error interrupt 60 or 61. NE incremented.
UP
NO
0
FRMRsent. W
UP
NO
1
DISREGARD
UP
YES
0
FRMR sent. W
UP
YES
1
Error interrupt 60 or 61. NE incremented.
LINK
TABLE II.
ACTION BY WD2511
DISREGARD
If N(S) = V(R), PKR interrupt, V(R) and NE
incremented. No ack transmitted. If N(S) not
= V(R), DISREGARD.
UFI RECEIVED
IfTRCV = 1 and UF (no I-field) is received, there will be
an Error interrupt 62 or 63, independent of the link state
or the readiness of RLOOK.
Of course, the received C-field of any frame will be in
Register #7 provided the A-field matched either Register E or F, the FCS was good, and the frame contained
32, or more, bits.
107
ACTION BY WD2511
= 1X = 1
= 1X = 1
APPENDIXB
C
==
N
en
......
......
HALF DUPLEX OPTION
The WD2511 is basically a full duplex device. The
receiver is maintained in an "always ready" condition
even if the receive buffer is not ready. Thus, whether
the received frame came from a full or half duplex system is of no consequence to the WD2511.
Therefore, the half duplex option affects only the
WD2511 transmitter. Half duplex is enabled when H/F
(CR05) = 1.
The WD2511 will transmit one frame at a time according to the following procedure:
A.
Enable RTS (RTS goes low).
B. Wait for CTS (CTS input goes low).
C. Transmit frame (when CTS is active).
D.
Remove RTS (RTS goes high 2'/2 bits of time after
the last 0 of the trailing flag.)
NOTES:
The leading flag will be transmitted somewhere
between 5 and 13 bits after CTS goes low.
Interframe fill will be all 1's (IDLE).
If T1 is internally activated it is started when RTS goes
low.
After RTS~s low, the frame will not begin transmission until CTS goes low. After the frame has started, the
transmission of that frame is completed even if CTS
returns high during the frame.
108
1>
I
APPENDIX C
STATE DESCRIPTIONS
LINK DOWN
r!
SEND IDLE.
RECEIVER
IGNORED.
CLEAR
SEND
BIT
SEND
TRANSPARENT
FRAME
N
TRANSPARENT
RECEIVE
109
CONDITION FOR RESET OR DISCONNECT
LINK IS UP
=E
cN
U1
.....
.....
LINK GOES UP
FROM STATE TABLE I
INTERRUPT
ERO-22
o
INTERRUPT
ERo-ao
LINK
RESETIING
SABM
y
CLEAR
NE, ETC
SENDUA
N
INTERRUPT
ERo-aa
y
INTERRUPT
ERO-30
CLEAR
NE,ETC
INTERRUPT
ERO = CO
y
Y
INTERRUPT
ERO -30
N
SENDUA
SOFTWARE
DISCONNECT
SEND DISC
SET LINK
110
=1
SENDFRMR
STATE TABLE I
LINK DOWN, BUT GOING UP
(Column 2 also applies to link reset)
o==
ACTION BY WD2511
U'1
I\)
COLUMN 1:
DISC sent. Waiting for UA or DM.
COLUMN 2:
SABM sent. Waiting for UA.
T1 runs out
Re-send DISC. P = 1.
Re-send SABM. P = 1.
T1 and N2 run out
Re-send DISC. P = 1.
Send DISC. Interrupt ERO = 24. Go
to column 1
Received UA
Send SABM. Go to column 2
Clear NA, NB, NE, V(R), V(S). Go to
link up flow.
Received DISC
Send OM.
Send OM.
Received SABM
Disregards
Send UA. Clear NA, NB, NE, V(R),
V(S). Keep waitiing for UA.
Received OM
Send SABM. Go to column 2.
Send DISC. Go to column 1.
Received something
other than UA, OM,
DISC, or SABM
Disregard.
Disregard.
STIMULUS:
STATE TABLE II
LINK GOING DOWN (WAS UP)
DEFINITIONS OF COMMAND AND RESPONSE
A transmitted or received command or response is a
frame with the A-field defined below:
User sets MDISC, Chip sends DISC.
ACTION BY WD2511
FRAME
A-FIELD =
STIMULUS
DISC sent. Waiting
for UA.
Transmitted Command
Register E
T1 runs out
Re-send DISC. P = 1.
Received Command
Register F
Go to Link Down Flow
Transmitted Response
Register F
Received SABM
Disregard
Received Response
Register E
Received DISC
Send OM. Go to Link
Down Flow
Received something
other than DISC,
SABM, UA, or OM
Disregard.
Received UA or OM
For non-transparent transmitted frames, only commands or responses are transmitted. A transparent
transmitted frame (TXMT = 1) may have any A-field the
user chooses.
All received frames must be either commands or
responses or the frame is disregarded ("thrown
away"), even if transparent receive is enabled (TRCV
= 1).
USE OF FLAGS BY THE WD2511
Once MDISC has been reset the WD2511 will send
interframe flags (hex 7E) if full duplex is selected (CR05
= 0) (point ST of the Link Down Flow point has been
entered). If half duplex is selected, (CR05 = 1),
interframe fill will be all 1's (IDLE).
The WD2511 does not require the interframe time fill
flags. Either idle or flags will be accepted. However, if
the receiver detects idle for time T1 X N2, the WD2511
will send a DISC.
When sending continuous flags, the WD2511 will send:
011111100111111001111110011 . . .
The WD2511 will accept either the above sequence as
continuous flags, or the "shared zero" pattern:
011111101111110111111011111 . . .
111
........
STATE TABLE III
SENDING I-FRAMES (PACKETS) AND S-COMMANDS
NOTES:
In all subsequent pages, the link is considered Up (LINK
Table II!.
= 0) unless otherwise stateq. X = don't care. TXMT = 0 for
SEND
BRDY
NAANDNB
RNRR
T1 EXPIRES
RCVDREJ
1
0
X
No
No
Clear SEND (CR1O)
1
1
X
0
0
No
No
Send next packet with
N(S) = NB. After transmission complete. Increment NB. Exception: If
NB + 1 = NA, do not send
next packet. There are 7
outstanding.
ACTION BY WD2511
X
X
X
1
Yes
No
Send S-command, P = 1.
X
X
not
X
Yes
No
Send S-command, P
X
X
=
not =
X
No
Yes
Make NA = received N(R).
Start sequential retransmission of packets beginning
with N(S) = NA. See Note 3.
= 1.
NOTES ON STATE TABLE III
1. Received S-frames in Table III are assumed to have
valid N(R)'s.
The WD2511 will not transmit a null packet. TCNT must
not be allowed to be all O's.
2. When an acknowledgement of one or more previously transmitted packets is received, NA is set
equal to the received N(R). All TLOOK segments
from the old value of NA up to N(R) - 1 are acknowledged and the appropriate ACKED bits in the
TLOOK segments will be set. After setting the
ACKED bits, an XBA interrupt is generated.
SENDING A REJ (RESPONSE)
1. The REJ condition is entered any time an error-free
packet is received with an out-of-sequence N(S).
Exception: If the received N(S) + 1 = V(R), then the
received N(S) has been acknowledged, and either
an RR or RNR is transmitted.
3. Assuming appropriate TLOOK segments are ready,
packets are transmitted sequentially without waiting for an acknowledgement, with three
exceptions:
2. When the REJ condition is entered, the REJ frame
with N(R) = V(R) is transmitted immediately if a
packet is not being transmitted, or, at the completion
of the current packet. There are two exceptions, as
noted in 3 and 4 below.
a. There are already seven outstanding (unacknowledged) packets (NB + 1 = NA).
b.
c.
3. If a link resetting SABM needs to be transmitted, the
SABM is sent. When the UA is received for the
SABM, the REJ condition is cleared.
The remote station has indicated a busy conqition by sending an RNA frame (ANAR). T1 is
started and an S-command will be transmitted
with P = 1 when T1 expires.
4. If the receiver is not ready (RNRX = 1), the REJ is
not sent.
T1 expired and there are one or more outstanding packets. An S-command Will be transmitted
withP = 1.
5. Once the REJ condition is entered, only one REJ will
be transmitted. Another REJ is not transmitted
unless the REJ condition is cleared and re-entered.
The AEJ condition is cleared if a packet is with correct N(S) if a SABM is received, or if a SABM is transmitted and a UA received.
4. If an S-frame command is received, the WD2511
will transmit an S-frame response at the next
opportunity.
5. If SEND
and TXMT = 1, a frame will be transmitted from the next TLOOK segment if BRDY
1.
Aftertransmission, SEND is cleared by the WD2511.
6. When the REJ is transmitted, error counter #6 is
incremented.
RECEIVING AND TRANSMITTING A NULL PACKET
Suppose a AEJ has been received error-free with no
I-field, then:
=
=
RECEIVING A REJ (RESPONSE OR COMMAND)
If an error-free (FCS good) packet is received with a correct N(S), but has no I-field, that packet will be treated
the same as a packet with an I-field. The fact that there
was no I-field is shown by RCNT equal to all O's.
1. If the N(R) is not valid, an interrupt is generated with
ERO = ca, and a FAMA is transmitted.
112
,
2. If the N(R) is valid, and greater than NA, at least one
transmitted packet is acknowledged. The appropriate ACKED bits in TLOOK are set and an XBA interrupt is generated.
DEFINITION OF VALID RECEIVED N(R)
3. If the N(R) is valid and less than NB, the WD2511 will
begin sequential retransmission starting with V(S)
= received N(R). If a packet is being transmitted
when the REJ was received, that packet is aborted.
If the N(R) is valid and equal to NB and a packet is
being transmitted, that packet (which will be #NB) is
aborted and retransmission will begin.
Definition
A valid received N(R) is greater than or equal to NA,
and less than or equal to NB.
1. The "greater than" and "less than" relationships
must be understood in a circular sense. 0 could be
greater than 7 depending on the values of NA and
NB.
Reference
CCITT Recommendation X.25 paragraphs 2.4.10 and
2.3.4.10.
4. If the N(R) is valid and equal to NB and there is no
packet being transmitted, there is no retransmission
initiated. In this case the REJ has the same effect as
anRR.
2. If NA = NB, there is only one possible valid received
N(R), N(R) = NA.
3. If NB + 1 = NA, there are seven outstanding packets and any received N(R) will be valid: N(R) = NB
ACK's all of the outstanding frames, N(R) = NA
ACK's none of them, and an N(R) in between ACK's
some of the packets.
5. If in 2, 3, or 4 above, the received REJ is a command,
the WD2511 will transmit a RR or RNR response at
the next respond opportunity.
4. Basically, a received N(R) which is not valid is one
which acknowledges a packet, or packets, never
transmitted.
STATE TABLE IV
LOCAL STATION BUSY (SENT RNR: RNRX
= 1)
LINK
RECR
RECRDY
1
1-+0
X
X
ACTION
1
1
RLOOK ready. No RNR frame sent.
1-+0
1
0
1-+0
0
X
RNR response sent immediately after link
Up. RNRX set. RLNR Interrupt
RNR response sent immediately after link
Up. RNRX set. No RLNR interrupt
0
0
1
1-+0
1
Receiver ready to accept packets.
0
1
0
RNR response sent. RNRX set. RLNR Interrupt.
0
0-+1
1
0
°
0
If RNRX was set, then RNRX will be cleared
after the next received packet or S-command. After that, an RR or REJ response is
sent.
RNR response sent. RNRX set. There is no
RLNR interrupt.
No S-frame transmitted when link down.
Receiver ready to accept packets.
1
NOTES ON STATE TABLE IV
1. The arrows (-+) indicate a change in state from the
value on the left to the value on the right.
4. Whenever RNRX = 1, the I-field of a received frame
is not brought into memory. For received packets,
the N(S) and N(R) are checked as usual. Ifthe N(S) is
out-of-sequence, the REJ will not be transmitted.
2. The RNRX status bit is set at the time the receivernot-ready condition was established. The RNR
frame will be sent immediately if no packet is being
sent or after the end of the current packet.
5. If a link resetting SABM is transmitted when RNRX
= 1, RNRX will be cleared when the UA is received.
If the condition which caused receiver-not-ready still
exists, an RNR is sent and RNRX is set. However, if
the receiver instead is ready, I-field data may be
brought into memory.
3. When a received packet is brought into memory with
RNRX = 0, the packet will be accepted provided the
FCS and N(S) are correct and the I-field is not too
long. The N(R) mayor may not be correct but is
checked separately. If N(R) is not valid, a FRMR is
transmitted.
The same also applies when a link resetting SABM
is received.
113
:e
cI\)
U1
.....
.....
iI
:ec
........
I\)
(II
STATE TABLE V
REMOTE STATION BUSY (RECEIVED RNR: RNRR = 1)
SEND
NAANDNB
RECVD
ACK?
RECVD
RNR
RECVDRR,
REJORUA
T1 EXPIRES
ACTION
No
No
Set RNRR. Restart T1 and
N2. Update NA.
X
not
=
Yes
Yes
0
Equal
No
Yes
No
No
Set RNRR. Start T1.
X
not
=
No
No
No
Yes
Send S-command (P = 1). If
RNR subsequently received
restart T1 and N2.
X
not
=
Yes
No
Yes, but not UA
No
Clear RNRR. Restart T1 and
N2. Update NA.
X
X
X
No
Yes
No
ClearRNRR.
0-1
Equal
No
No
No
No
Send next packet. Increment
NB after transmission. (Then,
NB does not = NA). Start T1
and N2.
2. NOTES OF TABLE V
1. If SEND = 1, it is assumed for this table that BRDY
of the next TLOOK segment is set.
2. If RNRR = 1, an RR or RNR command is transmitted at T1 intervals.
If an S or I-frame is received which acknowledges a previously transmitted packet(s), the acknowledgement(s)
is accepted, the appropriate ACKED bits in TLOOK are
set, and there is an XBA interrupt.
SENDING S-FRAME COMMANDS
While in the FRMR condition, the WD2511 will act as
shown below:
When an S-frame command is to be transmitted, an RR
command is transmitted if RNRX = 0 or an RNR command is transmitted if RNRX = 1. If RNRX = 0, and a
REJ is waiting to be transmitted, a REJ command is
transmitted.
FRAME RECEIVED
For all transmitted S-commands, the P bit is set to 1.
An S-command will be transmitted at T1 intervals if an
RNR is received (RNRR = 1) or ifT1 has expired due to
waiting for an acknowledgement to previouusly transmitted packets.
CONDITIONS FOR SENDING SABM (LINK RESET)
1. FRMR received.
2. Have sent an S-command N2 times with P = 1 (at
T1 intervals) without receiving an S-response with
F = 1.
ACTION BY WD2511
SABM
Send UA. Clear FRMR
condition. Enter information transfer phase.
DISC
Send UA. Clear FRMR
condition. Enter logical
disconnect state.
Packet with good N(R)
Retransmit FRMR
. S-frame with good N(R)
(command or response)
Retransmit FRMR
Packet or S-frame with
bad N(R)
Transmit new FRMR (Z
= 1)
Any frame with violation
W,X,Y
Transmit new FRMR
RECEIVING AN FRMR
UNSOLICITED UA OR UNSOLICITED F BIT
After a FRMR has been received:
If an unsolicited UA or an unsolicited F bit is received
with the link up, a FRMR will be transmitted with W = 1.
1. The FRMR I-field will bee in the memory referenced
by the current NE segment, provided the receiver
was ready.
SENDING AN FRMR
2. The SEND bit is cleared.
An FRMR may be transmitted for any of the reasons
indicated in X.25 (W, X, Y, Z). An FRMR is transmitted
only if the link is up.
3. No more I-field data is allowed to come into memory
until the user makes the receiver memory ready.
4. A link resetting SABM is transmitted and an error
Upon sending a FRMR, the WD2511 will not send a
packet until the FRMR condition is cleared. The
WD2511 will also discard any received I-fields. The
FRMR condition is cleared when either a SABM or
DISC is received.
interrupt, ERO = CO is generated.
5. After the UA is received for the SABM, the NA, NB,
NE, V(R), and V(S) are cleared to O.
114
FRCML = O. Furthermore, if RLOOKO has RECRDY =
1 and RECR is set to 1, a packet can be stored into
RLOOKO immediately after a Link Reset. Therefore,
the host should also look for received packets beginning at RLOOKO after a Link Reset.
PROTOCOL SIGNIFICANCE OF TLOOK/RLOOK
POINTERS
The NE, NA, and NB pointers have a relationship with
the sequence counters used in the LAPB protocol.
The RLOOK pointer NE is equal to V(R) at all times if
TRCV = O. HoweverTRCV = 1 and the link is Up, there
is no guaranteed relationship between NE and V(R).
The chip resets the SEND bit after a Link Reset so no
new TLOOK buffers will be sent until the host sets
SEND again. After a Link Reset the host should look for
any unprocessed acknowledged packets (ACKED = 1)
in the TLOOK table beginning at its Next Packet to be
Acknowledged segment and proceeding in order until
it finds a segment with ACKED = O. Then the host must
set up the TLOOK segments again so that the oldest
unacknowledged packet is in TLOOKO, the next in
TLOOK1, and so on, setting the BRDY = 1 in each
occupied segment. (New packets may be added to the
TLOOK at the next available segment.) When the host
has finished setting up the TLOOK segments, it should
set the SEND bit to 1. At this pOint packet transmission
will resume if the remote station is up and is not in a
receiver not ready (RNRR = 1) condition.
TLOOK pointer NB is the Next Block to be transmitted.
If the chip is not in packet retransmission, NB is equal
to the V(S) of the next new packet to be transmitted.
TLOOK pointer NA is the Next packet to be Acknowledged. It represents the V(S) number for the oldest
packet in the retransmission buffer.
USE OF THE RECR BIT
The RECR (CR01) bit should be understood as an
instruction to the WD2511 to enable the receiver function. The WD2511 will test RECR as soon as MDISC is
cleared, and will retest RECR after each link set-up and
each link reset. Once the receiver is ready, the WD2511
will not test RECR again unless there is a link set-up or
a link reset.
When presenting packets to the chip for transmission,
the host should implement a timer. The value of the
timer is system dependent and varies with packet size
and line speed but should be in the order of seconds. If
a packet has not been acknowledged by the time the
timer expires, the host should check the SEND bit. If it
is reset, set it to 1 again and restart the timer. If it was
still set, the link must be reset. Do this by setting the
MOISC bit (CROO = 1), waiting for the link to go down
(LINK = 1), then resetting MDISC (CROO = 0), and
waiting for the link to come back up (ERO = 21 or, if
RLOOKO was not ready, 11 and LINK = 0).
The receiver-not-ready condition is indicated by RNRX
= 1. This condition is cleared after the user makes
RECR = 1 with RECRDY = 1 (in RLOOK #0) and after
either a packet or an S-frame is received from the
remote station.
If RECRDY of the next RLOOK is 0 but RECR = 0,
there will not be an RLNR interrupt, but RNRX will be
set. If RECR = 1 but the RECRDY bit of the next
RLOOK segment is 0, there will be an RLNR interrupt
(error code 10) and RNRX will be set.
For more software information refer to the WD2511
Application Note.
HOST PROCEDURE FOR LINK RESET
The host should keep its own set of variables to determine the index of the Next Packet to be Received and
the Next Packet to be Acknowledged because if a Link
Reset occurs, the chip resets its NA, NB, and NE
counters. After a Link Reset the host should look for
unprocessed received packets (FRCML = 1) in the
RLOOK table beginning at its Next Packet to be
Received segment and proceeding in order until it finds
115
,
~
N
.....
.....
CII
APPENDIXD
GLOSSARY OF DATA COMMUNICATIONS TERMS
The following is a list of industry-accepted data communications terms that are applicable to this specification.
ABM
Asynchronous Balanced Mode
ADCCP
Advanced Data Communications Control Procedure (ANSI BSR X3.66)
ANSI
American National Standards Institute
ARM
Asynchronous Response Mode
CCITT
International Consultative Committee for Telegraphy and Telephony
CMDR
Command Reject. AU-Frame
DCE
Data Circuit Termination EqUipment (the network side of the DTEIDCE link)
DISC
Disconnect. AU-Frame
DTE
Data Terminal Equipment
OM
Disconnect Mode. AU-Frame (LAPB, only)
ECMA
European Computer Manufacturers Association
FCS
Frame Check Sequence
FOX
Full Duplex (also called "two way simultaneous")
FRAME
Basic serial block of bit-oriented data. Includes leading and trailing flags, address field, control field,
FCS field, and an optional information field.
FRMR
Frame Reject. AU-Frame (LAPB, only)
HDLC
High-Level Data Link Control (ISO 3309)
HDX
Half Duplex (also called "two way alternate")
HOST
Another name for a DTE
I-Frame
Information Frame. Control field bit 0 is O. In X.25 an I-frame is a packet.
ISO
International Standards Organization
LINK
The logical and physical connection between two data terminals
LAP
Link Access Procedure
LAPB
Link Access Procedure Balanced
N2
Maximum number of retransmissions of a frame. (Also called retransmission count variable.)
NODE
Another name for a DCE or DTE.
N(R)
Sequence number of next frame expected to be received.
N(S)
Sequence number of current frame being transmitted.
OCTET
An 8-bit byte
PACKET
An I-Frame in X.25
PAD
Packet AssemblylDisassembly facility
REJ-
Reject. An S-Frame
RNR-
Receiver Not Ready. An S-Frame
RR-
Receiver Ready. An S-Frame
= 1 and bit 1 = 0
S-Frame
Supervisory Frame. Control field bit 0
SARM
Set Asynchronous Response Mode. (LAp, only)
SABM
Set Asynchronous Balanced Mode. (LAPB, only)
SDLC
Synchronous Data Link Control (IBM document GA27-3093)
T1
A Primary Timer for a delay in waiting for a response to a frame
=
=
U-Frame
Unnumbered Frame. Control Field bit 0
UA
Unnumbered Acknowledge. AU-Frame
X.25
Recommendation by CCITT on InterfaCing to Public Packet Switching Networks
1 and bit 1
1
X.3, X.28, X.29 Recommendations by CCITT involving PAD facilities
-There are also RR, RNR, and REJ packets which are not the same as the S-frame RR, RNR and REJ discussed in
this document.
See page 383 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital Corporation for
its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change specifications at anytime without notice.
116
,
WESTERN DIGITAL
c
o
R
p
o
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A
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/
o
N
WD2511 Application Note
This application note provides an introduction to the
X.25 communication protocol and introduces the ISO
reference model. The link layer of X.25 is highlighted
as it can today be implemented with a single LSI
device, the WD2511.
The bulk of this document provides details of the hardware and software interfaces that a user typically
encounters when using the WD2511. Schematic and
timing diagrams for a typical Z80 interface along with
high level flowcharts for initialization and operation are
given. This circuitry is applicable for applications
where the TC/RC speed is 64 Kbps and below.
CONTENTS
1.0 The WD2511 General Description
2.0 The WD2511 and the ISO Model
3.0 Hardware
4.0 Software
for passage over the physical line.
These three levels are completely independent of each
other, which allows changes to be made to one level
without disrupting the operation of any other level. An
adjacent level is affected only if the changes affect the
interface to that level.
Each level performs one well defined set of functions,
using only a well defined set of services provided by the
level below. These functions implement a set of
services that can be accessed only from the level
above. Each level is strictly controlled by the systems
engineer according to formal functional and interface
specifications.
The WD2511 implements level 2. Without additional
logic, it generates the frame, performs error checking,
performs link management (set up/disconnect) and
ensures reliable data transmission by evaluating the
sequence number associated with each I-frame. The
device automatically acknowledges received I-frames
and fully supports up to 7 outstanding (unacknowledged) frames, including retransmission if required.
Appendix A Glossary
Appendix B LAP vs LAPB
3.0 HARDWARE
The WD2511 must be connected to the Physical Level
(Level 1). This generally amounts to simple line drivers/
receivers.
A typical X.25 DTE/DCE station block diagram is
shown in Figure 2. Figure 3 shows a circuit diagram of
the actual X.25 hardware interface ofthis same station.
Table 1 is a description of signal functions for this circuit
diagram. This is to be connected directly to a Z80
microprocessor on one side and an EIA RS-422 interface on the other side.
1.0 THE WD2511 GENERAL DESCRIPTION
The WD2511 is an LSI device that fully handles the link
level (level 2) of the CCITT X.25 communications
protocol.
In addition to the traditional parallel/serial converters
and FCS logic, the WD2511 incorporates a highly efficient micro-programmed processor that fully handles
the required link set-up and frame sequencing operations conventionally delegated to a "user defined"
processor. The WD2511 also contains an intelligent
two-channel DMA controller to further simplify its integration into a user's system.
Figures 4 and 5 are DMA cycle timing diagrams for this
particular station.
General notes to this interface:
• A modem would be needed for long-distance communication lines.
• The hardware interface in Figure 3 includes all hardware options. Simpler interfacing is possible.
2.0 THE WD2511 AND THE ISO MODEL
The CCITT X.25 recommendation comprises three
levels of protocols (Level 1 to 3). See Figure 1.
Level 1 is the physical level, which concerns the actual
means of bit transmission across a physical medium.
Level 2 is the link level which includes frame formatting, error control and link control.
• The function of the CPU Bus Driver Control Circuit
(CBDCC) is to control the direction and/or timing of
the data-line transceivers and the two address
latches.
• If the CPU clock frequency is not higher than the
WD2511 CLK maximum frequency, the High Speed
Control Circuit (HSCC) is not needed. The function
of the HSCC circuit is to divide a high speed CPU
Level 3 is the packet (network) level which controls the
traffic ofthe different virtual calls and multiplexes these
,
117
LEVEL
4·7
USER
PROCESS
LEVEL 314 INTERFACE
t
3
PACKET
LEVEL
LEVEL 2/3 INTERFACE
2
LEVEL 1/2 INTERFACE
4------_
-----_....
t
LINK
LEVEL
USER
PROCESS
PACKET
LEVEL
t
~-----
l
PHYSICAL
LINK
PHYSICAL
LEVEL
OTE
LINK
LEVEL
1
PHYSICAL
LEVEL
OTE/OCE
Figure 1. LAYERED ARCHITECTURE FOR COMPUTER NETWORKS
up by the respective protocols for that particular level.
The only real physical connection between the two stations (DTE and DTE/DCE) is the Physical Link between
the two physical layers. The other connections shown
between two of the same layers (peer to peer interface)
is not a physical but rather a logical connection made
Each level n "interfaces" to the corresponding level n
on the other side of the Data Communication Link
through the level n-1, then n-2 etc., via the physical link
and up through the levels to n-2, n-1 and to level n.
programmed to be interrupt controlled inQuts; the
CPU can be interrupted by DSR and/or INTR as
programmed.
clock signal (0) down to half the frequency (01A). It
also delays the reset of BUSRQ with one additional
01 clock cycle when a high speed CPU clock is used.
These functions are needed to establish a time window of at least 500ns between DACK being active
and a CPU Write/Read function.
• MRW (Memory Read/Write) signal enables the output of the memory address decoder for the computer system memory chips. As an example, if a
PROM type 28S42 is used as the memory address
decoder, MRW is connected direct to 'E (Pin 15)
input.
• When a high speed CPU clock is used, connect 0.1 A
Signal to 01 signal and BUSRQA signal to BUSRQ
signal. When a low speed CPU clock is used, connect CPU clockdO) direct to 01 signal and BUSRQ2
signal to USR signal.
s
• The WD2511 CS input is to be connected to a port
address decoder (or memory address decoder).
MWE is connected to all WE inputs, and MOE is connected to all OE inputs of the system memory chips.
• The DMA I/O circuit matches the timing between the
Z80 and the WD2511.
• The RTS open collector output needs a pull-up
resistor.
• REPLY output is not used in this application.
• In this particular example, line drivers/receivers are
of type EIA RS-422. However, RS-232C or RS-423
can also easily be used.
The sixteen I/O registers are qirectly accessible from
the CPU data bus (DALO-DAL7) by a read and/or write
operation by the CPU. The CPU must activate the
WD2511 register address (IAO-IA3). Cl!!.!.> Select (CS).
Write Enable (WE) or Read Enable (RE) before each
data bus transfer operation. The readlwrite operation is
3.1 READ/WRITE CONTROL OF I/O.REGISTERS
• Port A of a PIO in this example is programmed to be
an output. In this case, the CPU controls the DTR
output to the modem. Port B of the PIO is
118
,
completed when CS or REIWE is bro~ high. During
a write operation, the falling edge of WE will initiate a
WD2511 write cycle. The addressed register will then
be loaded with the content of the Data Bus. The rising
edge of WE will latch that data into the addressed
register.
time, the CPU also switches the control over to the
WD2511 by activating the BUSAK signal. This causes
DACK to go LO at the following rising edge of 01 clock.
This is the actual indication for the WD2511 to start the
DMA In cycle. DACK also causes DRQI to return to the
HI state.
During a read operation, the falling edge of RE will initiate a WD2511 read cycle. The addressed register will
then place its content onto the Data Bus.
At the next rising edge of the 01 clock, MOE (Memory
Output Enable) is activated. This causes the memory to
output the addressed data byte onto the Data Bus.
Also, the address is now latched into the address bus
latches (74LS373) at this time.
The CPU must set-up all transmit data, TSADR HI and
LO, TCNT HI and LO, and residual bits before setting
BRDY in the applicable TLOOK segment.
At the next falling edge of the 01 clock, DACK gets
deactivated, causing the WD2511 to latch the data byte
(DALO-DAL7) and to set its address lines (AO-A15) to
logical HI state (ADRV bit = 1). The address bus
latches hold the address active until DMOE signal is
deactivated.
The CPU must set aside receiver memory (at least one
chain segment with transfer address), and set-up
RSADR HI and LO before setting REC RDY in the applicable RLOOK segment.
At the next rising edge of the 01 clock (low speed CPU
clock), BUSRQ gets deactivated. When high speed
CPU clock is used, BUSRQ is deactivated after an
additional 01 clock cycle.
3.2 DMA IN/OUT OPERATION
The Direct Memory Access (DMA) operation is completely controlled by the WD2511. During a DMA cycle,
the CPU sets its address bus, data bus and three-state
control signals to their high impedance states.
At the next following rising edge of 01 clock, BUSRQ is
sampled by the CPU. This causes BUSAK and MOE to
become deactivated, but not until the next falling edge
of the CPU (0) clock. This is the end of the DMA In
cycle. At the next rising edge of the CPU clock, the
CPU again controls the CPU bus.
(See DMA In/Out timing diagrams, Figures 4 and 5.)
In this application example, the data bus transceivers
are permanently enabled (low impedance state). When
the CPU has control, the direction of these transceivers
is pointing from the CPU bus towards the WD2511. During a DMA In cycle, this is not changed. During a DMA
Out cycle however, the direction is reversed (WD2511
towards the CPU bus).
3.2.2 DMA OUT
This operation is very similar to the DMA In function.
During this cycle, one byte of I-field data is transferred
from the WD2511 to the memory. The CPU-time in this
example described to perform this task is the same as
for the DMA In cycle.
The address bus latches are in high impedance state
while the CPU has control of the bus. When the
WD2511 has control of the CPU bus, the address
latches are in the low impedance state. During the
DMA Out cycle, these latches function as regular bus
drivers. During the DMA In cycle however, the address
gets latched to assure enough data hold time for the
WD2511.
The DMA Out function starts when the WD2511 is holding a received I-field byte and is ready to transfer this to
the memory. This condition activates the DRQO signal,
which in turn sets the BUSRQ to LO. Also at this time
(ADRV bit = 1), the WD2511 presents the address to
the memory location to where the respective data byte
is to be loaded.
3.2.1 DMAIN
During a DMA In cycle, the task of transferring one byte
of I-field data from memory into the WD2511 is performed. The CPU time (in the example described in this
paragraph to execute this task) is five T-states for a low
speed CPU clock system and ten T-states for a high
speed CPU clock system.
The BUSRQ signal is sampled by the CPU with the rising edge of the last CPU clock period of any machine
cycle. Since the BUSRQ signal is active, the CPU goes
into high impedance state with the rising edge of the
following CPU clock pulse. Now the CPU also switches
the control over to the WD2511 by activating the
BUSAK signal. This causes DACK to go LO at the next
rising edge of 01 clock, which indicates to the WD2511
to start the DMA Out cycle. This causes DRQO to reset
back to HI state and to load the data byte to be transferred onto the data-bus.
The DMA In function starts when the WD2511 is ready
to receive a byte from memory to be transmitted out to
the remote station. This condition causes the DRQI signal to go LO, which in turn activates the BUSRQ (Bus
Request) signal. Also at this time (ADRV bit = 1), the
WD2511 presents the address (on AO-A15) of the data
byte to be retrieved from memory.
At the next rising edge of the 01 clock, MWE (Memory
Write Enable) is activated. This causes the memory to
input the addressed data byte.
The BUSRQ signal is sampled by the CPU with the rising edge of the last CPU clock (0) period of any
machine cycle. In this case, because the BUSRQ signal is active, the CPU goes into high impedance state
with the rising edge of the next CPU clock pulse. At this
At the following rising edge of the 01 clock, MWE goes
HI, latching the data into the memory. Also at this time
119
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o
N
UI
.....
.....
l
I
!
I·
TABLE 1.
=e
c
N
SIGNAL NAMES FOR THE HARDWARE INTERFACE (See Note)
NAME
SYMBOL
FUNCTION
RECEIVE
RCV
When activated (LO), sets the direction of the data
bus transceivers from WD2511 towards the CPU
bus. This is done only during CPU Read or DMA
Out cycle.
DRM TRANSFER
PTFR
When activated (LO), enables the output of the
address bus latches. This is done during a DMA
In/Out cycle.
DMA MEMORY OUTPUT ENABLE
DMOE
Is activated during a DMA In cycle. Generates the
MOE signal and latches the DMA In addresses.
MEMORY OUTPUT ENABLE
MOE
Is activated during a DMA In or a CPU Read
cycle. Enables the memory outputs. Is to be connected to the OE pin of the memory circuits.
MEMORY WRITE ENABLE
MWE
Is activated during a DMA Out or a CPU Write
Cycle. Enables the m~ry write function. Is to
be connected to the WE input of the memory
circuits.
MEMORY READIWRITE
MRW
Is activated during a DMA In/Out function or a
Memory Read/Write cycle by the CPU. Enables
the output of the Memory Address decoder.
DMAOUT
DMAOUT
Is activated during a DMA Out function.
DMAIN
DMAIN
Is activated during a DMA In function.
INTERNAL LOOP
ILOOP
Is activate--__
..
--'N"'oT..:E.,:.'_ _ _+I
.._ _.-::N::..oT"'E:::'_ _ _...,+I....___...:.N:::OT:.:E""_ _ _-+I
----~~I----------------------------~
L===u
I
I
INTERNAL CLOCK
!
l
SAMPLE
DATA
SAMPLE
DATA
NOTE 1. FIRST DATA TRANSITION (FIRST FLAG) SETS THE DPLL COUNTER TO 01.
NOTE 2. DATA TRANSITION IN BETWEEN HERE, OR NO DATA TRANSITION AT ALL, CAUSES NO CORRECTION OF THE
DPLL COUNTER.
NOTE 3. DATA TRANSITION IN BETWEEN HERE, WILL INCREMENT ONE COUNT TO THE DPLL COUNTER (ADD 01 TO
WHAT IS SHOWN).
NOTE 4. DATA TRANSITION IN BETWEEN HERE, WILL DECREMENT ONE COUNT TO THE DPLL COUNTER (SUBTRACT 01
TO WHAT IS SHOWN).
FIGURE 5.
WD1935 DPLL TIMING DIAGRAM
142
r-
At each received data transition, if the internal clock and
the received data is out of synchronization, a correction is
autornatically made by :!: I external clock period. See OPLL
Timing Diagram in Figure 5.
will configure the WDI935 for the user's specific data communication environment. These registers should be loaded
during power-on initialization and after a reset operation.
They can be changed at any time that the respective transmitter or receiver is deactivated. The CRI-3 dictate what the
transmitter will send: the type of character (DATA, ABORT,
FLAG or FCS), the number of bits per character, and the number of bits in the reSidual character. Similarly, they tell the
receiver the types of frames to look for: the number of bits per
I-field character, whether to perform an address compare,
and whether to watch for an extended address. The Control
Register also control Data Terminal Ready (OTR), Misc Out
and the activation of both the transmitter and the receiver. For
more detailed information, see Register Formats.
End Of Block (EOB)
This is an FCS command. The rnain purpose of EOB is to
allow the user to initiate FCS and FLAG without the need of
using extra computer time. This is particularly practical in
OMA applications. At the end of a frame, when the last information data character has already been loaded into the
THR and once again ORaO is set, either a regular FCS comrnand is written into CRI Register, or EOB is to be activated.
At the end of FCS, when INTRa is set (XMIT OPCOM), the
EOB if activated is to be reset again.
Monitoring Operation
Serial Data Synchronization
Monitoring is done by use of the Interrupt Register (IR) and
Status Register (SR). The IR register indicates when a frame
is completed (transmitted or received), if there was an error
and if there is a Data Set Change. It also monitors the states
of INTRa, DRao and ORQI.
The SR register indicates if an error is recognized by IR,
what type of error. It also monitors the modem control
signals; Ring Indicator (RI), Carrier Detect (CD), Data Set
Ready (OSR) and M isc iii.
Furthermore, the SR register monitors if the Receiver is
idle, and also if in receive mode if the user has programmed
the Receiver Character Length to be 8 bits per character, this
register indicates the number of residual bits received. For
more detailed information, see Register Formats.
The serial data is synchronized by the externally supplied Transmit Clock (TC) and Receive Clock (RC). When IX
clock is selected, the falling edge of TC generates new
transmitted data and the rising edge of RC is used to sample the received data When 32X clock is selected, a 32counter (in the OPLL Logic) is used to synchronize the internal clock. At time 0, when the counter is reset to 0, the
new transrnitted data is generated. At tirne 16 (counter
16) the received data is sarnpled, insuring that sampling is
done in the middle of the received serial data bit. At count
32, the counter is reset to 0 again.
=
Self Test (Diagnostic) Mode
This feature is a programmable Loop back of data, enabling the user to make a complete test of the WOl935 with a
minimum of external circuitry. In this mode, transmitted data
to the TO pin, is internally routed to the received data input
circuitry, thus allowing a CPU to send a message to itself to
verify proper operation of the W01935. The modem control
signals OTR and RTS are deactivated (off) to insure no interference to/from the Data Communication Equipment (DC E).
OSR and CTS are internally activated for proper input conditions. TC and RC should be supplied by the same source if I X
clock is selected.
Read/Write Control Of CPU Interlace Registers
These registers are directly accessible from the CPU bus
(07-00) by a read and/or write operation by the CPU.
The CPU must set up the W01935 register address (A2AO), Chip Select (CS), Write Enable (WE) or Read Enable
(RE) before each data bus transfer operation.
During a write operation, the falling edge of WE will initiate
a WOl935 write cycle. The addressed register will then be
loaded with the content of the Data Bus (07-00). During a
read operation, the falling edge of RE will initiate a· WOl935
read cycle. The addressed register will then place its content
onto the Data Bus (07-00). The read/write operation is completed, when CS or RE/WE is brought high.
See Read/Write Timing diagram for more detailed information.
For read and write operation, the CRI-3 registers normally need no external clock. After reset of CRI-3, TC clock is
required. The AR and THR registers need no external clock,
and can only be written into. The RHR, IR and SR registers
need Transmit Clock (TC) or Receive Clock (RC) to set
various bits, and are read-only.
All these registers will get initialized by a Master Reset. A
read operation of RHR resets the ORal. A write operation
to THR, resets the ORaO. A read operation of IR, resets IR
bits 0 and 3-7. A read operation of SR, resets SR bits 0-2.
For addressing and external clocks needed, see TABLE 2.
Auto Flag
If this is selected and Data Command is executed, conti nuous Flags will be sent between frames. This eliminates the
need to execute the Flag Command. In OMA applications in
particular, this is very practical.
Extended AddreSSing
This type of addressing means, that there is more than one
address character in the A-field. In receive mode, the first
address character is compared in the Address Comparator of
the W01935. The other address character/s is to be compared by the CPU. The last address character is recognized
by the fact that the LSB (bit 2°) is a I.
PROGRAMMING
A more detailed description is shown in Figure 6 of each bit
location. It should be known, that because the Data Bus
Lines (07-00) have inverted logic, a logic I, asserted means
low state. Also, a modem control signal which is inverted
(example OTR), is in on-state (asserted) when low.
Controlling Operation
Prior to initiating data transmission or reception, CONTROL REGISTER 1-3 (CRI-3) must be loaded with control
information from the CPU. The contents of these registers
143
,
~
TABLE 2.
=e
C
.....
CD
W
U1
DEVICE ADDRESS CODES
CS
A2
AT
AO
Read
Write
L
L
L
L
L
L
H
H
H
H
H
L
L
X
H
H
L
L
H
H
X
H
L
H
L
H
L
X
CRI
CR2
CR3
RHR
IR
SR
X
CRI
CR2
CR3
AR
THR
External Clock
None*
None*
None*
RHR=RC. AR=None
IR=TC". THR=None
SRO-3=RC. SR4-7=None.
X
L = V,L at pins
H = V,H at pins
X = Don't care
* 2.5 TC clock cycles are required
after a Master Reset to be able to
read and write.
REGISTER FORMATS
DTR Command (CR11) This bit controls the data Terminal Ready (DTR) signal to the data set. When CRll is a
logical 0, DTR is off. When CRll is a logical 1, DTR is on.
When the Self-Test mode is selected, DTR signal is forced
to an off state.
Transmitter Character Length (CR13, 12) These bits
control the transmitted I-field data character length. The
data character may be 5, 6, 7 or 8 bits long.
Below shows a short form register format.
BIT
--+-
17
,.
,.
15
13
12
11
10
CR1
27
2.
2.
25
23
22
21
20
CR2
TABLE 3.
37
3.
35
3.
33
32
31
30
CR3
CR13 (TCL1)
CR12 (TCLO)
0
1
0
RHR
0
0
1
1
REOMt~EOM
XMIT
PPCOM
WI
RROA
XMIT
0";.';"
DSC
DRal
DROO INTRO
UNDER
NO
ERROR RUN
Bits Per
Character
8
7
6
5
Transmitter Commands (CR15, 14) These bits control
the transmission of DATA (A-field, C-field and I-field), ABORT,
FLAG, and FCS (FCS plus FLAG). When these commands
are programmed, the previous command currently still in
progress, will complete the transmission of its character.
When this is done, a new character generated by this new
command, will be transmitted.
AR
wi N0'IRRC!R
TRANSMITTER CHARACTER LENGTH
IR
CR 14, 15 can be programmed as follows:
A. If DATA is programmed, the new character to be transmit-
Control Register 1 (CR1)
ted will be the character loaded (or still to be loaded) in the
THR REGISTER.
B. If ABORT is programmed, the new character will be eight
logical 1'so
C. If FLAG is programmed, the new character will be
01111110.
D. If FCS is programmed, the new character which will be
transmitted consists of the residual byte (which was automatically transferred to the XMIT REGISTER, provided
that CR30-32 and are set correctly), followed by the 16-bit
content of the FCS XMIT REGISTER and the FLAG.
When initiating a transmit/receive operation, this should be
the last register programmed.
Miscellaneous Output (CR10) This bit controls the Miscellaneous Output signal to the data set. When CR10 is a
logical 0, Misc Out is off, when it is a logical 1, Misc Out
is on.
One serial bit ahead of this new character (for FCS command the FLAG character), the CPU is signalled by DRaO or
INTRa that the WD1935 is again ready to receive a new command. DRaO is asserted by a DATA command and INTRa
(XMIT OPCOM) is asserted by an ABORT, FLAG or FCS command.
THR
5.
SR
FIGURE 6.
WD1935 BIT ASSIGNMENTS
144
TABLE 4.
CR15 (TC1)
CR14 (TCO)
o
o
o
TRANSMITTER COMMANDS
Command
DATA
ABORT
FLAG
FCS
1
o
1
Activate Transmitter (CR 16) This bit when set, enables
the transmitter and sets RTS signal. If in SDLC Loop Mode
(CR22 = set), the transmitter waits for a Go-Ahead pattern
before the transmitter is enabled.
Activate Receiver (CR 17) This bit when set activates
the receiver, which begins shifting in frames one character
at a time into RR register for inspection.
CONTROL REGISTER 2 (CR2)
Auto Flag (CR20) When set, Flags (without INTRas) will
be continuously transmitted in between frames, when otherwise the transmitter would be in idle state.
Self-Test Mode (CR21) When set, the Transmitter Data
Output is intemally connected to the Receiver Data input
circuitry. The modem control output signals are deactivated
(off state). The modem control input signals are internally
activated. This mode allows off-line diagnostic.
SOLC Loop Mode (CR22) When set, the WD1935 is
conditioned to operate in an SDLC Loop Data Link system
(see SDLC Loop Mode).
Receiver Character Lengtll (CR24, 23) These bits indicate to the receiver how many bits per character there are
to assemble for the I-field. The I-field characters may be 5,
6, 7 or 8 bits long. The unused bits read from RHR will be
10gical.0.
CR23
(RCLO)
Bits Per
Character
0
0
1
1
0
1
0
1
8
7
CONTROL REGISTER (CR3)
1i'ansmlt Residual Character Length (CR32, 31, 30)
(Table 6) These bits inform the transmitter what bit-length the
residual character will be. If no residual character is to be
sent, these bits must be set to logical O. (See Transmitter
Commands).
Unused (CR33-37) These bits are not used, and are
always a logical O.
INTERRUPT REGISTER (IR)
This register contains the information why an interrupt
INTRa was generated. An IR register read operation, will
reset bits 0, and 3-7. The Transmitter clock must be active to
generate an interrupt.
Loading the iHR register, will reset DRQO (bit 1). Reading
the RHR register, will reset ORal (bit 2). A new interrupt will
occur if one is pending.
6
5
TABLE 6.
DRaO
INTRa
INTRa
INTRa
Extended Control (CR27) When set, indicates that
there are two control characters per name. If not set, there is
only one control character per frame. The purpose of this bit:
If a non-8-bit I-field character length is to be received, the
ORals will get out of synchronization if the WD1935 does not
know when the I-field will start. Not used in transmit mode.
RECEIVER CHARACTER LENGTH
CR24
(RCL1)
Signal to CPU
Content of THR
1111 1111
0111 1110
FCS + 01111110
Extended Address (CR25) When set, this bit indicates
to the receiver that there is more than one address character
in the A-field. The receiver will expect another address character if the LSB in the current address character is a logical O.
The purpose of this bit: If a non-8-bit field character length is
expected, the ORals will get out of synchronization if the
WD1935 does not know exactly when the I-field will start. Not
used in transmit mode.
Address Compare (CR26) When set, the first address
character will be inspected in the Address Comparator. If
there is a match with the AR register, or if the address compared is a Global Address (eight l's) the frame is considered
valid, causing ORals to be generated. Otherwise, the receiver does not react, and will continue comparing for a new
valid address. If not set, all frames are considered valid.
In the case of the DATA command the user has two
choices; 1. Change the command. 2. Keep the DATA command and load a new character into the THR register. For
more information, please see the Transmission Timing diagram, Figure 7. See Table 4 for programming information.
TABLE 5.
Character/s Transmitted
TRANSMITTER RESIDUAL COMMANDS
CR32
(TRES 2)
CR31
(TRES 1)
CR30
(TRES 0)
o
o
o
o
o
o
1
o
1
1
1
o
1
o
1
o
o
1
o
1
145
Residual Char. Length
No residual char. sent
1 bit
2 bits
3 bits
4 bits
5 bits
6 bits
7 bits
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....
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C
w
U1
i
r
TABLE 7.
:eo
COl
COO
.....
LO
to)
LO
U1
HI
HI
LO
HI
LO
HI
CD
DATA SET CHANGE PROGRAMMING
Interrupting edge of CD
FiTf
RlO
Interrupting edge ofAI
Rising and falling
Falling
Rising
• None
LO
LO
HI
LO
HI
Rising and falling
Falling
Rising
None
LO
HI
HI
If a new interrupt is generated while the CPU is reading
the IR register, this new interrupt will set the respective bit
in the IR register one bit time later (this to avoid losing any
interrupt). The status of bits 3-7 will accumulate until the IR
register is read by CPU.
If REOM WITH ERROR (IR 6) is set, these bits indicate the
type of error that occurred (Table 9).
TABLE 8.
INTRQ (IRa) When set, indicates an interrupt and that
there are one or more bits set in positions 3 through 7 of this
register. This bit is a mirror image of INTRO signal (pin 6).
When pin 6 (INTRO) is not used for pending interrupts
information and only the IR register is read to obtain the
status of the interrupt bits (polling method), a minimum of
two (2) bits times must be allowed between IR registers
"read's" to insure an orderly flow of pending interrupts.
RES.
BITS
S
R
a
S
R
1
R
2
8
Bits/Char.
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
Bits/Char.
0
1
2
3
4
5
6
0
0
1
1
1
1
0
0
1
0
1
0
1
1
6
Bits/Char.
0
1
2
3
4
5
5
Bits/Char.
0
1
2
3
4
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
1
0
1
1
0
0
1
0
1
0
1
DRQO (IR1) When set, indicates a Data request output.
This bit is a mirror image of DROO signal (pin 18).
DRQI (IR2) When set, indicates a Data Request input.
This bit is a mirror image of DROI signal (pin 19).
Data Set Change (IR3) When set, indicates a change of
state of the Data Set (Data Communication Equipment). This
is a change of state ofDSR, CD orffiThe type of change of
CD andRi that this bit will react to, is programmed by use of
input Signals COl/COO and Rll/RIO (Table 7).
XMIT Operation Complete with Underrun Error
(IR4) When set, indicates that the transmitter command
has been completed and there was an Underrun error. An
Underrun error occurs when the Data Request Output
(DROO) is set, but THR register is not loaded in time.
XMIT Operation with No Error (IRS) When set, indicates that the transmitter command has been completed and
there was no error.
Received End of Message With Errors (IR6) When set,
indicates that a Received End of Message is detected, and
there was an error. Errors include CRC, Overrun, Invalid
Frame and Aborted Frame.
The SR Register bits 0-2 will indicate the exact type of
error.
Received End Of Message With No Error (IR7) When
set, indicates that a Received End of Message is detected,
and there was no error.
S
CHAR.
LENGTH
0
1
0
1
0
1
TABLE 9.
STATUS REGISTER (SR)
Bit Set
Error
SRO
SRl
SR2
CRC
Overrun
Aborted or
Invalid frame
,.-"
This register contains the status of the receiver and some
modem control signals. It also indicates (if REOM w/Errors)
exactly what type of errors. If the Receiver Character Length
is 8 bits, this register indicates the amount of Residual bits
that was received. A read operation will reset bits 0-2.
Receiver Idle (SR 3) When set, indicates that the receiver is currently IDLE.
Miscellaneous Input (SR4) This is a mirror image of
MISC IN signal. When this dignal is set, SR4 bit is set.
Data Set Ready (SRS) This is mirror image of DSR signal. When this signal is set, SR5 bit is set.
Carrier Detect (SR6) This is a mirror image of CD signal.
When this signal is set, SR6 bit is set.
Received Error/Received Residual Character Length
(SR 2-0) If REOM wINO ERROR (lR7) is set, these bits (SR 20), indicate the number of residual bits received (Table 8).
146
Ring Indicator (SR7) This is a mirror image of Ai signal.
When this signal is set, SR7 bit is set.
Also, the ACT TRAN bit should be kept set in between
frames. Every time DRQO gets set, the user must load the
THR register before the last loaded character only has 1.5
bits left to be transmitted. In other words, when DRQO gets
set, the user may wait (if 8-bit characters) up to 7.5 serial
data bits before loading the THR. If THR is not loaded within
this time, an Underrun error will occur.
If Auto Flag is not selected (CR20 = logical 0) the sequence
will be a little different than described below. When the first
DRQO is set, and after the Address character is loaded into
THR, a Flag command is also programmed (CR15, 14 = 10).
This will set an interrupt (INTRQ). which indicates that the
IR register must be read. Now, the Data Command is reprogrammed (CR15, 14 =00).
For more information, see Transmission Timing diagram.
TRANSMITTER OPERATION
Prior to this operation, the programmable inputs and the
transmit mode related register bits need to be programmed
according to the user's specific data communications environment. The last bit to be set is always the ACT TRAN
(CR16) bit.
Before this, the INTRQ has to be cleared, which can be
done by reading the IR register. For more detailed information
how to program the WD1935 see Programming.
As an example of how to program the WD1935 let's
assume a 24-bit information is to be transmitted. The I-field
would then consist of three 8-bit characters with no residual
bits. CR3 should then be 00 (Hex).
ABORT CONDITIONS
Bits CR23-CR27 are for reception only (see Receiver
Operation). The last register to be programmed is CR1. If
MISC OUT is not used, this may be ignored. If a modem is
used, DTR (CR11) is to be set. CR13 and CR12 should be
logical O's (8-bit char. length). CR15 and CR14 should be
logical O's (Data Command). ACT TRAN (CR16) bit is to be
set. The ACT REC (CR17) is for reception only.
The function of prematurely terminating a data link is
called an "Abort." The transmitting station aborts by sending eight consecutive 1'so Unintentional Abort caused by
1's in the A-C- or I-field is prevented by zero insertion. Inten·
tional Abort may be sent by programming an Abort command. Abort will also be sent in the case where THR is not
loaded in time or FCS command is not programmed in time
(= underrun). This means that after the DRQO is set, to
avoid Abort; THR must be loaded, EOB activated or FCS
command programmed before there is only 1.5 bits left of
the last character to be transmitted.
If this is not done, INTRQ (XMIT OPCOM w/underrun) is
set and Aborts are transmitted until, either the command is
changed or the THR is loaded. If in this same case, Auto
Flag was programmed, one Abort (with INTRQ) would be
generated, and thereafter continuous Flags (with no INTRQs)
will be sent.
The DTR bit, when set, activates the DTR signal, indicating to the modem to prepare for communication. When the
modem is ready, it sends back a Data Set Ready (DSR) to the
WD1935. This causes the DSC (IR3) bit to set, which in turn
activates INTRQ. The IR register is now read. Simultaneously, when the ACT TRAN (CR16) bit is set, this activates the
Request to Send (RTS) signal, instructing the modem to enter
into transmit mode. When the modem is ready to transmit
data, it responds by activating the Clear to Send (CTS) signal.
The WD1935 is now conditioned to transmit. Now DRQO
gets, set, indicating to the CPU (or DMA) to load the first character (Address) into the THR. When this is done, DRQO will
reset. As soon as the WD1935 is ready to be loaded with the
next character to be transmitted, DRQO is again set. When
the THR register is again loaded with a character, DRQO will
again reset.
RECEIVER OPERATION
Prior to this operation, the programmable inputs and the
receive mode related register bits have to be programmed
according to the user's specific data communication environment. Also, the INTRQ has to be cleared. The last bit to be
set is always the ACT REC (CR17) bit.
This same sequence continues until the last I-field character to be transmitted is loaded into the THR. If CRC checking is to be used, the next time when DRQO is set, an FCS
command has to be programmed. This is accomplished bv
either setting CR15, 14 to both logical 1's or by activating the
EOB signal.
At the end of the FCS being transmitted, INTRQ will set
indicating XMIT Operation Complete. The IR register is to be
read to find out whether the frame was sent with or without
error. Also the FCS Command which was used as described
above has to be changed. If CR15, 14 were set, these have
to be reset (to Data Command), or if EOB was activated, this
signal has to be deactivated. At this same time, the ACT
TRAN bit is allowed to be reset, causing the TD output to go
idle after the end Flag is sent. If the ACT TRAN bit is kept
set, continuous Flags will be sent following the FCS.
If a new frame is to be sent right after this first frame, only
one Flag is needed in between frames, meaning the frames
have one common Flag character. In this case, the second
frame Address character may be loaded at the same time
the FCS command is programmed during the first frame.
For more detailed information how to program the WD1935
see Programming. As an example, let's assume a 26-bit information is to be received, and the I-field is made up by 8-bit
characters. The CR3 register is only for transmit mode, and
may be ignored here. CR20 and CR 12-16 bits are also for
transmit mode only, and therefore may also be ignored. CR21
and CR22 are to be logical Os (no Self-Test and no SDLC
Loop Mode). CR24, 23 are to be logical O's (8-bit character 1field). If only one A-field and one C-field character is
expected, and this WD1935 has a specific address, CR25
should be a logical 0, CR26 should be a 1, and CR27 should
be a O. The address to which the Afield should compare
should be loaded into the AR register.
The status of the modem is monitored by the SR register,
and it may be useful to read it at this time. CR1 is loaded as
the last register. CR10 (Misc In) bit is optionable to the user.
CR11 (DTR) is to be set if modem is used. CR17 (ACT REG)
is now set, starting the input of frame characters into the
Receiver Register (RR). When a Flag is detected, the next
147
CRC Error (SRO) If the CRC calculation performed on
the incoming data does not equal to FOB8 (HEX), this bi(will
be set.
Overrun Error (SR1) After ORal is set, if the RHR is not
read within one character minus one bit time, this bit will be
set.
Aborted or Invalid Frame Error (SR2) If the frame is
aborted or if in a frame the number of bits between flags are
less than the required minimum (see Table 10), this bit will be
set.
8-bit character (address-character), when received, is compared to the character in the AR register. If these match, or
if the received character is a Global address, this frame is
valid, and the ORal gets set. If the Address Comparator
(CR26) bit is not set, all frames would be considered valid
and generate ORals. When the RHR register is read, ORal
will be reset. All characters in a valid frame which are input
into the RR register will set ORal, and every time RHR is
read by the CPU, ORal will be reset.
During reception, the receiver also performs a CRC calculation on the incoming data. When the end Flag is received, INTRa will get set, indicating Received End of
Message. If the reception is completed with no error, IR7
(REOM wino Error) bit will be set. When 8-bit characters are
received SR 0-2 bits indicate the number of residual bits, in
this case two. If IR6 (REOM wi Error) was set, SR 0-2 bits
indicate the type of errors (see Receiver Error Indication).
When all characters including the A-field and the FCSfield are read, and when the REOM interrupt is recognized,
it is up to the user to disassemble these mentioned characters from the received data If non-8-bit characters are received, the amount of residual bits have to be calculated by
the CPU after masking out the part of the ending Flag
showing up in the last read character.
After end of frame, the receiver begins searching for a
new frame.
NOTES
1. TC-command-If two or more contiguous ABORTS or
FLAGS are executed, the ACT TRAN (CR16) bit has to be
reset before DATA-command can be executed.
2. Master Reset (MR)-Needs no clock during activation of
MR. However, 2.5 clock cycles are required to reset the
W01935 after the falling edge of MR.
3. IR-register-Immediately when IR register is read, bit 0
will reset. Bits 3-7 are reset one bit time later.
4. SR-register-Bits 0-2 are reset one bit time after SR register is read.
5. SOLC Loop mode-Go-ahead pattem may be sent by
either sending IDLE or ABORT after Flag.
6. TC and RC clocks are completely independent of each
other.
(For more information, see Figure 8.)
RECEIVER ERROR INDICATION
7. It is recommended to verify that the INTRQ signal (pin 6)
is set prior to reading the IR register.
When a frame is received, and REOM w/Error (IR6) is set,
the type of error is indicated by the SR bits 0-2.
B. End Of Block (EOB) - Minimum activated time must be
one (1) character time. It can be activated indefinitely
using IDOLE or AUTO FLAG (CR20).
TABLE 10.
Valid Frame For WD1935
Receiver Programmed for
8 bit char
7 bit char
6 bit char
5 bit char
1 address, 1 control
~25
bits
~23
bits
~21
bits
~19
2 addresses, 1 control
1 address, 2 controls
~25
bits
~24
bits
~23
bits
~22bits
3 addresses, 1 control
2 addresses, 2 controls
~25
bits
~25
bits
~25bits
~25bits
148
bits
TC
(1XCLOCK)
TO
-4,..----,
IDLE
I
-j
OROO
II
=
~
.,TAO
pATA BITS
I
FCS
r
_ \ LlOATA
BIT
L~
THRj
~
________________________
-- --~ --l
~
____________________
~r___lL
l
~
~~ tiC[
o I'!
~~~
~~!i
iii '0'
~~"
~~~
~ ~
!
~~~
.~C[
c5
~~~
::ii8~
Wo~
"'«
i:915
'0'
~~"
r~
_____
w
~~
~
~§
~
~ ~~
NOTE 1. CR3 = OOH, CR2 = 01H, CRl = 02H (FOR THIS EXAMPLE ONLY)
NOTE 2. WRITE FCS COMMAND, OR ACTIVATE n5B.
NOTE 3. INF. DATA MAY CONSIST OF ANY NUMBER OF BITS.
FIGURE 7.
WD1935 TRANSMISSION TIMING DIAGRAM
RO -----1J
FCS
IOI.E
O:TArBITS
ORal
INTRQ
-----i
r
c;
~"
,.
"'~bw
8~
f!
~
~
iii
--l --l
~
.~
~~~
~~~
f:il:
"''''''
.5
o~~
~8~
.. ~~
~"'''
---
I
I
t
Iii~a:
1ii .... a:M'
--t
~O~
~~~b
~fl~
l
-'-
<
~~~
Ul!
"'~"
o~ww
~~!~
C[a:o!e
WD1935 R~CE;PTlON TIMING DIAGRAM
149
1 L'R
READ
~:ffi
~!i!i
~~B
NOTE 1. AR ~ 19H, CR2 ~ 40H, CRl ~ 02H (FOR THIS EXAMPLE ONLY)
NOTE 2. INF. DATA (I·FIELD) MAY CONSIST OF ANY AMOUNT OF BITS.
IIIQT!= 3. CPU DOES NOT KNOW UNTIL RECEIVED END OF MESSAGE (REOM) THAT THIS IS AN FCS CHARACTER.
FIGURE 8.
IL
~~
~!;.
SPECIFICATIONS
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Storage Temperature
Storage Temperature
Voltage on any pin
with respect to GND (V SS)
Power Dissipation
DC Characteristics
TA
O°C to + 70°
=
-55°C to + 125°C (plastic package)
-65°C to +150°C (ceramic package)
-0.3 to + 7.0V
1W
VSS
= OV,
VCC
TABLE 11.
Symbol
III
ILO
VIH
VIL
VOH
VOL
ICC
Parameter
=
+ 5 ± 0.25V
Min
Input Leakage
Output Leakage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Supply Current
AC Characteristics
TA
O°C to + 70°
=
WD1935 DC CHARACTERISTICS
Max
Units
10
10
J.lA
J.lA
V
V
V
V
ma
2.4
0.8
2.4
0.4
210
70
Conditions
VIN = VCC
VOUT
VCC or VSS
=
All Inputs
-1ooJ.lA
10
10
1.6mA
=
=
VSS = OV, VCC = + 5 ± 0.25V
TABLE 12.
WD1935 AC CHARACTERISTICS
-.
Parameter
Min
TAS
TAH
TCSS
TCSH
READ & WRITE (Fig. 9, 10)
Address Set·Up
Address Hold
Chip Select Set-up
Chip Select Hold
TRED
TDV
TDRQIR
TINTRQf
TRE
READ (Fig. 9)
Data Delay from RE Asserted'
Date Valid from RE Deasserted
0
DRQI Reset Delay
INTRQ Reset Delay
RE Pulse width
325
WRITE (Fig. 10)
DataSet-up
TDS
Data Hold
TDH
TDRQOF DRQO Reset Delay
WE Pulse width
TWE
-12
-11
-10
Symbol
Typ
Max
20
20
20
20
Min
Max
20
20
20
20
315
140
280
280
0
Min
-13
Max
20
20
20
20
290
140
280
280
0
Min
Max
20
20
20
20
265
140
280
280
0
300
275
250
180
20
160
20
140
20
Units Conditions
ns
ns
ns
ns
240
140
280
280
ns
ns
ns
ns
ns
330
ns
ns
ns
125
125
ns
ns
ns
1.0
1.5
2.0
1.0
1.5
2.0
2.5
20
20
20
20
20
20
20
20
200
20
330
330
330
200
180
160
140
TRDS
TRDH
TroO
TRANSMIT& RECEIVE (Fig.11)
150
Receive Data Set Up
Receive Data Hold
150
Transmit Data Out Delay
150
150
150
150
150
150
125
125
1xFc
CLOCK
1XClock
.5
32xFc
32XCIock
TR
TF
RISE & FALL (Fig. 12)
Rise Time
Fall Time
NOTE: All A.C. Timing Measurements made at 0.8V and 2.0V.
150
MHz at 50% duty
cycle
MHz at 50% duty
cycle
ns
ns
See figure 1
HIGH IMP STATE
O7-5O------------------Q
VALID
i
HIGH IMP
07·00
~
VALID
STATE
AD. Al. A2
RE
-----------..,.c 1:'
DAal ___TO_Aa_'A__~t
TOROOR
INTAa------------------------l---t
''"'~
ORao
NOTE 1. TREO and TOV starts from where both
CS and 1i!" are active.
FIGURE 9.
RC
AD
FIGURE 10.
WD1935 READ TIMING DIAGRAM
WD1935 WRITE TIMING DIAGRAM
#".Li<
TC
'to: '-)1
TR
TF
TO
FIGURE 11.
FIGURE 12.
RECEIVER AND TRANSMITTER TIMING
151
WD1935 RISE AND FALL TIMING DIAGRAM
2 FCSTTO - FRAMECHECKSEOVENCETOTD
THE 16 BIT FCS IS SHIFTEIl QUT HIGH ORDER BI1 FIRS1
FIGURE 13.
WD1935 TRANSMITTER FLOW CHART
152
MASTER
RESET
NOTE: STATE 0 IS WHERE WE SEARCH FOR OR
HAVE FOUND THE OPENING FLAG AND SYNC
THE FRAME TO IT. AFTER THE OPENING FLAG
HAS BEEN DETECTED WE GO TO STATE 1
RECEIVE BIT COUNTER .- MODULO 8 COUNTER
USED TO PROGRAM THE NUMBER OF
BITS PER CHARACTER & CALCULATE THE
NUMBER OF RESIDUAL BITS
(START FRAME)
HAVE
(lNTRQ)
--L_--'-<
~_ _-,__
NOTE: IN STATE 1 WE ARE IN SYNC
WITH THE INCOMING DATA AND WE
INCREMENT BY CHARACTER UNTIL THE
FRAME ENOS OR IS ABORTED
RECEIVE
ABORT
BYTE
N
(CONTINUOUS
FLAGS
LOOP)
(RECEIVE BIT COUNTER
AT TERMINAL COUNT)
NEXT
~~::~~~~~ >:,----'
(ADDRESS)
RECEIVER
7g;I~::~~
(CR24)
RCL1
(CR23)
RCLO
0
0
0
,,
,
,
0
.,
>-------------------'
BITS PER
CHAR
,
6
ORal SET
(ORal)
RR = RECEIVE REGISTER
RHR = RECEIVE HOLDING REG1STER
ADDRESS
RECE1VED
COMPLETE
FIGURE 14.
WD1935 RECEIVER FLOW CHART
153
TABLE 13.
WD1935 ORDERING INFORMATION
Maximum
Part Number
Data Rate
WD1935 *-10
WD1935*-11
WD1935*-12
WD1935 *-13
500KBPS
1.0MBPS
1.5MBPS
2.0MBPS
Temperature
Range
OOCto
O°Cto
O°Cto
OOCto
+ 70°C
+70°C
+70°C
+ 70°C
* Please contact your local Western Digital Sales
Representative for package availability and price
information.
See page 383 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
154
Prlnled in U.S.A
WESTERN DIGITAL
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WD1935 Application Note
acters to/from the WD1935. This device takes care of the serialization or deserialization of this data, plus control and
timing.
INTRODUCTION
The purpose of this document is to provide the reader with
information about the WD1935. Various applications examples are given showing flowcharts and timing diagrams. As
the device is designed for use in a very large range of applications, many different features are described and illustrated
for the benefit of the reader.
Some control signals on the computer side of the device are
needed for read, write, and control purposes. Additional signals can also be used for special purposes or modes for the
convenience of the user. Typically, these other control signals
are used to enable communication with a modem or DCE
(Data Communications Equipment).
For detailed product information such as A.C. and D.C.
parameters, please refer to the data sheet.
Interrupt outputs are provided to inform the microcomputer
when to retrieve from, or to provide data to the holding registers. Interrupts can be generated to provide status information (i.e. changes in modem control lines, or events such as
Transmission Complete or Received End of Message have
occurred).
GENERAL DESCRIPTION
The WD1935 is an MOS/LSI device which interfaces a parallel digital system to a serial data communication channel
(and vice versa). This circuit is capable of simplex, half
duplex, and full duplex operation.
SYSTEM APPLICATIONS
The WD1935 is designed for bit-oriented SDLC, HDLC and
ADCCP protocols. The device is programmable and compatible with most a-bit microcomputers on the market. The purpose of the device is to convert paraliel data from a computer
or terminal to a serial data stream at one end of a communication channel. At the other end of the channel. At the other end
of the channel, the data is converted back to the original parallel data.
Switched network
Multipoint network
Non-switched pOint to point network
Simplex, half-duplex, or full duplex
Synchronous Communication
Message switching
Multiplexing systems
Data concentrator systems
Loop data link systems
DMA applications
Parallel to serial data conversion (and vice versa)
Local Networks
Packet Switching
X.25
Multidrop line systems
Serial data communications minimizes the number of physical channels required to transfer data and therefore reduces
the cost to send data between two (or more) distant points. A
microcomputer can perform the same serial/parallel conversion function as this device, but at a much slower speed.
However, using the WD1935 to do this function is much more
efficient. This makes the computer free to perform other tasks
during transmission and reception. The only work that the
computer is required to do is to initialize and write data char-
A typical block diagram of a data link is shown in Figure 1.
WD1935
WD1935
~~------------~v~--------------~
I
STATION A
STATION B
FIGURE 1.
DATA LINK BLOCK DIAGRAM
155
...
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CD
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The communication media used could be a direct communication channel (such as a leased telephone line), a switched
telephone line, or one of many other possibilities. Typically
these applications would require the use of a modem.
A modem is needed for long distance communication lines.
For shorter distance, line drivers/receivers may be sufficient.
In some very well controlled environments, such as a laboratory, two devices may be connected without line drivers and
receivers.
bus, but buffers are normally recommended. Figure 2 shows
a typical schematic of an interface between a zao microcomputer and a modem.
Some example of various WD1935 systems are shown here
by use of block diagrams. The station shown in Figure 3 consists of a computer or terminal, and a modem. A station may
consist of only the computer or terminal, and one WD1935
device. Whether the modem, line drivers and receivers, or
CPU buffers are needed depends on the details of the particular design situation.
The WD1935 may be connected directly to a microcomputer
EIA RS-422
LINE DRIVER/RECEIVER
BUFFERS
WD1935
DM~17
1m
DO
01
D2
TO
D3
D.
_===-
1
13
DS
07
"
15
25
CIN
AD
23
Al
liE
lID
,.
WI!
~
Z-BO
COMPUTER
OR eQulV.
,.
PBO
PBl
PB2
r
"
..
"'"
30
l
36
"B
A
DTR
ATS
B
B TO
A
i54
Os
156
Of
l5§ll
33
A'
Ali
AI
Ai
liE
WE
MIi
RD
<:rl
24
-;;c
INTRa
1'e
31
ORCI
E-
~
i.I
.1.
.1.
.....
CD
-.r
JL
AOOR
C
·1·
·1·
'1
n
I
I
n
I
I
I
I
I
I
t
!
!
rL
"'_
l:w
a:~
IW
I@
....
w
>-"
t
I~ ~
t
~
~~i
0
"-
>-"
t~
::la:
!Wa;1-
~~
5~
"
<;
FIGURE 17.
DMA TIMING OF MIDDLE FRAMES
END FRAME
I.
tAODR
.1·
"LCONTfI..
·1·
~--
LS
INF.OATA
·1 •
·1·
'1'
DMA CONTR
80 TIME
n
I
"D'fR
""
·1
ee"
TIME
L ___
n
I
I
I
l
I
l
I@
~h
~
m~~
FIGURE 18.
~~.
DMA TIMING OF LAST FRAME
167
r- -
CN
CJ1
r
WD1935 RECEPTION EXAMPLE 1
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A sequence of events is shown in illustrating how to receive a
message with the WD1935. For simplicity, the same SDLC
frame structure is used as in Transmission Example 1. Also,
please refer to the same interface circuitry shown in Figure 2.
Co)
Fi~ure 19.iII~str~tes the functional flow, and Figure 20 contains the timing Information.
CD
CII
typical frame, but it shows how the WD1935 works in a wide
range of frame structures.
The first FLAG and FCS are not shown in detail and are not
critical to this example.
'
Figure 21 illustrates the functional flow, and Figure 22 contains the timing information.
WD1935 LOOP DATA LINK EXAMPLE
WD1935 RECEPTION EXAMPLE 2
this exa~pl~ shows how to program a secondary station
to function In SDLC Loop mode. The functional flow is
illustrated in Figure 24, and the interface circuit is show in
Figure 2.
This example shows a frame with two ADDRESS characters
two CONTROL characters, one 5-bit INFORMATION DATA
character, and two residual bits. This example may not be a
FIGURE 19.
FLOW DIAGRAM OF FRAME RECEPTION (EXAMPLE NO.1)
168
RECEIVE DATA
INTERRUPT NO. 2-N
(ADDRESS MATCH)
READIR.
ENABLE
INTERRUPT.
NO
READ
RHR
NO
(ERROR)
READ SR REG.
BITS 0-2
TO FIND
OUT WHAT
TYPE OF
ERROR
COMPUTER
DOING OTHER
TASKS
REMOVE
LAST TWO
CHAR. RECEIVED
READ SR
REGISTER
BITS 0-2
YES
SAVE RESIDUAL
BITS, BUT
MASK OUT THE
OTHERS IN
LAST CHAR.
NOT REMOVED
FIGURE 19.
FLOW DIAGRAM OF FRAME RECEPTION (CONTINUED)
169
~
C
..I.
co
W
en
.,.,
(IX CLOCK)
I
n
I
n
I
I
I
I
~~~
~~G
~6..,
OI:~
Un
NOTE 1. DATA SET CHANGE INTERRUPT
NOT SHOWN HERE
NOTE 2. PROGRAMMED ADDRESS (IN AR REG) ~ 331-1
FIGURE 20.
TIMING DIAGRAM OF FRAME RECEPTION (EXAMPLE NO.1)
170
FLOWCHART
INITIATE
---
RECEIVE MODE
(
START
~
~
PORT A
PORT B
~
MOMENTARILY
ACTIV. MR.
CONFIGURE
PIO
OUTPUT
INTERRUPT
INPUT
PA7-Q
=
0111 1111
PBO/PB2 (INTROIDRQI)
~
INTERRUPTS
t
WRITE
ADDRESS 1
INTO AR
REGISTER
ADDRESS 1 INTO AR
SET EXT
CONTR, ADDR.
COMP, EXT
AD DR AND
RCL ~ 5
DATA SET READY
ACTIVATE
RECEIVER
COMPUTER
DOING OTHER
TASKS
FIGURE 21 ,
1CH
CR2
~
11111000
CRl
~
00000010
t
SET
DTR
DATA TERM. READY
1ST INTERRUPT
(DATA SET CHANGE)
~
~
PROGRAM
EXTENDED CONTROL
ADDRESS COMPARE
EXTENDED ADDRESS
RECEIVE CHAR. LENGTH
~ 5 BITS
COMPUTER
DOING OTHER
TASKS
EXAMPLE: AR
t
(
WAIT
(
INTERRUPT
)
I
SEE DATA SET
READY IN
RECEPTION EXAMPLE 1
FLOWCHART
cb
FLOW DIAGRAM OF FRAME RECEPTION (EXAMPLE NO.2)
171
RECEIVE DATA
INTERRUPT NO. 2·N
(ADDRESS MATCH)
READIA.
ENABLE
INTERRUPT
YES
NO
YES
READ RHR
(ERROR)
EX.
IS
B3H
READ SR
REGISTER
BITS 0-2
(TYPE OF ERROR)
RECONFIGURE
COMPUTER
PIO TO IGNORE
DROI (ADDA.
2 MISMATCH)
NO
CALCULATE
NO. OF RESI·
DUAL BITS
(SEE RESIDUAL
BIT CALCU·
LATION NEXT
PAGE)
REMOVE FCS
AND NON·
RESID. BITS
IN LAST READ
INF. DATA CHAR.
COMPUTER
DOING
OTHER
TASKS
FIGURE 21.
FLOW DIAGRAM OF FRAME RECEPTION (CONTINUED)
172
RESIDUAL BIT CALCULATION
LOCATE THE
CHARACTER WITH
THE START OF THE
CLOSING FLAG
THIS METHOD IS USED TO
CALCULATE THE RESIDUAL
BITS FROM THE COLLECTED
DATA, RATHER THAN USING
THE STATUS REGISTER
BITS SRO-SR2.
I
:-
t
REMOVE THE FLAG
BITS FROM THIS
CHARACTER.
ADD THE RESULT
TO THE BITS/CHAR.
MODE VALUE
SUBTRACT 16
FROM THE
RESULT
THE REMAINDER
IS THE NUMBER
OF RESIDUAL BITS
IN THE FRAME
FIGURE 22.
FLOW DIAGRAM OF RESIDUAL BIT CALCULATION
I
t
________~------~----~----~----~--~--~--~--~~L
FIGURE 23.
TIMING DIAGRAM OF FRAME RECEPTION
173
FLOWCHART
INITIATE LOOP
MODE
C
START)
~
PORT A
PORT B
~
MOM. ACTIV.
OUTPUT
INTERRUPT
INPUT
~
ADDR_AR
m.
PA,.,
~
CONFIGURE
PIO. •
PB,.,
~
WRITE ADDRESS
INTOAR REG.
SET ADDR. COMP,
LOOP MODE,
AUTO FLAG
SET DTR
BIT
DATA TERM READY
COMPUTER
DOING OTHER
TASKS
C
INTERRUPT (ORal, DROO, INTRa)
AR ~ 00110011
CR3 ~ 00000000
CR2 ~ 01000101
CR1
~
00000010
WAIT
RECEIVE DATA (ACT TRAN BIT = 0)
DATA SET READY
1ST INTERRUPT
0111 1111
INTERRUPT 2-N
(ADDRESS COMPARED
AND MATCHED)
(INTETPT)
(
INTERRUPT)
SEE TIMING
DIAGRAM FIG. 22
SEE DATA seT
ACTIVATE
RECEIVER
COMPUTER
DOING OTHER
TASKS
READY IN
RECEPTION EXAMPLE 1
FLOWCHART
CR1 ~ 10000010
SEE RECEIVE DATA
IN RECEPTION EXAMPLE 1
FLOWCHART
cb~,~"=
(
FIGURE 24_
ENDOF RE-)
CEIVE DATA
FLOW DIAGRAM OF SOLe LOOP MODE OPERATION
174
TRANSMISSION"""
AEQUEST
V
I
CAl = 11000010
ACTIVATE TRANSMITTER
l
(SECONDARY STATION IS STILL FUNCTIONING AS A REPEATER,
RECEIVING DATA WHEN ADDRESSED, BUT IT IS NOW ALSO
WAITING FOA A GO·AHEAD PATTERN FROM PRIMARY
STATION TO BE ALLOWED TO TRANSMIT)
RECEIVE DATA (ACT TRAN BIT
= 1) OR XMIT DATA (GA IS RECEIVED)
INTERRUPT 2 - N
(ACT TRAN BIT = 1).
READ SR REG.
BITS 0-2
TO FIND
OUT WHAT
TYPE OF
REOM ERROR
RESID.
YES
BITS?= 00 ) - - - - - - - - ,
NO
SAVE RESIDUAL
BITS, BUT
MASK OUT THE
OTHERS IN
LAST CHAR.
NOT REMOVED
FIGURE 24.
FLOW DIAGRAM OF SDLC LOOP MODE (CONTINUED)
175
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U1
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
176
WESTERN DIGITAL
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WD2123 DEUCE
Dual Enhanced Universal Communications Element
FEATURES
TXADY-B
NC
• TWO INDEPENDENT ASYNCHRONOUS FULL DUPLEX
DATA COMMUNICATION CHANNELS (2 BOARTS)
• TWO INDEPENDENT BAUD RATEGEtIU::RATORS (ONE
PER CHANNEL)
• EACH CHANNEL WITH FOLLOWING FEATURES:
• SELECTABLE 5 TO 8 BIT CHARACTERS
• 1X, 16X, 64X CLOCK RATES
• 16 SELECTABLE BAUD RATE CLOCK FREQUENCIES
(INTERNAL)
• LINE BREAK DETECTION AND GENERATION
• 1, W2, OR 2 STOP BIT SELECTION
• FALSE START BIT DETECTION
• ODD OR EVEN PARITY GENERATE AND DETECTION
• OVERRUN AND FRAMING DETECTION
• DOUBLE BUFFERING OF DATA
• TTL COMflI!.TIBLE INPUTS AND OUTPUTS
• COMA6.TIBLE WITH 8251 A (ASYNC ONLy) AND WD1983
DEVICES
• DIAGNOSTIC LOCAL LOOP-BACK MODE
• RXD INITIALIZATION UPON MASTER RESET
• ON-BOARD OSCILLATOR FOR EASE OF USE WITH A
CRYSTAL
• VERSATILE CLOCK SELECT OPTIONS FOR INDEPENDENT TRANSMIT AND RECEIVE RATES
TXO·B
AXAOY·B
AXO·B
TXE·B
II!'
CS1
i'iTS-B
ciI1
Ci'S-ii
BAKOET·B
SELCLK·B
DO
01
8
XCI/BCO·B
02
9
XTAl2
XTAL1
VSS
VCC
03
D4
MA
05
XCIIBCO-A
06
SELCLK·A
07
Gin
CS2
im=A
~
BAKOET·A
Cs3
TXE·A
RXO·A
AXAOY·A
TXO-A
TXRDY-A
PIN DESIGNATION
DESCRIPTION
The Western Digital WD2123 Dual Enhanced Universal
Communications Element (DEUCE) is a single chip MOS/LSI
Data Communications Controller Circuit that contains two
independent full-duplex asynchronous RECEIVER/TRANSMITTER CHANNELS and two independent BAUD RATE
GENERATORS. The WD2123 is fabricated in N-Channel silicon gate technology and is packaged in a 40 pin plastic or
ceramic package. All inputs and outputs are TTL compatible.
forms serial-to-parallel conversion on data characters received from an input/output device or a MODEM, and parallel-to-serial conversion on data characters received from the
CPU. The CPU can read the status of either channel at any
time. Status information on a per channel basis reported includes the type and the cond ition of the transfer operations
being performed by the WD2123 as well as any transmission
error conditions (parity, overrun, or framing). Programming
the WD2123 is identical to the 8251A in the asynchronous
mode, remembering that CS1, when low, selects CHANNEL
A and when CS2 is low, selects CHANNEL B.
The WD2123 Block Diagram is shown in Figure 1. The
WD2123 is a merger of two WD1983s and one WD1941 from
WDC's line of communications devices on one piece of silicon. The 1983 is an asynchronous only version of the 8251 A
and the 1941 is a baud rate generator. In this manner, 8251 A
compatibility is maintained with the WD2123 with the added
features of 2 channels and 2 baud rate generators on a single
Chip.
The WD2123 BAUD RATE GENERATORS may be selected
either internally or externally. The clock select logic includes
a clock select control bit CR1 (CS) in each COMMAND INSTRUCTION REGISTER. This control bit allows selection of
the internal baud clock or an externally applied clock and
works in conjunction with the select clock pin, "SELCLK" and
the external clock input/baud clock output pin, "XCI/BCO".
When CS is logic 1, the external clock select mode is selected. This means that the transmit and receive clocks (TXC
and RXC) are internally tied together and the select clock
pin, SELCLK, will determine whether those clocks are driven
from the intemal baud rate generator (SELCLK is high) or
from the external clock input pin, "XCI/BCO", (SELCLK is
lOW).
As depicted from the block diagram, the channels are referred to as CHANNELS A and B. CHANNEL A, which is an
asynchronous 8251 A, is addressed or controlled by the input
signal ~. CHANNEL B is Similarly controlled by~. Finally, the BAUD RATE GENERATORS are controlled by
CS3.
Each channel of the WD2123 can be programmed to receive
and transmit asynchronous serial data. The WD2123 per-
177
PIN DESCRIPTION
PIN
NUMBER
SIGNAL
MNEMONIC
10
VSS
GROUND
Ground
30
VCC
POWER SUPPLY
+5VDC power supply input.
7
8
9
11
12
13
14
15
DO
01
02
03
04
05
06
07
DATA BUS
This is the 8 bit Bidirectional Data Bus. It is the means of
communication between the WD2123 and the CPU. Data,
control, mode and status registers are accessed via this bus.
5
CS1
CHIP SELECT ONE
V,L on this input selects Channel A and enables computer
communications with Channel A Data, control and status
registers.
16
CS2
CHIP SELECT TWO
V,L on this input selects Channel B and enables computer
communications with Channel B Data, control and status
registers.
18
CS3
CHIP SELECT THREE
V,L on this input select the Baud Rate registers for programming.
6
ctr:i
CONTROL or
SELECT
4
FiE
READ ENABLE
V I L on this input allows the CPU to read data, or status information from the selected register.
17
WE
WRITE ENABLE
V,L on this input allows the CPU to write data or control information into the selected register.
29
MR
MASTER RESET
V,H on this input resets both channels to the idle state and
resets the status, command, mode and Data registers.
31
XTAL1
CRYSTAL OSCILLATOR
INPUT
This is the input side of the on-chip oscillator. It can also be
driven by an external clock source.
32
XTAL2
CRYSTAL OSCILLATOR
OUTPUT
This is the output side of the on-chip oscillator.
27
SELCLK-A
SELECT CLOCK
(Channel A)
This input is used in conjunction with the Clock Select bit
(CR1) in the command register to determine the baud clock
source for Channel A.
34
SELCLK-B
SELECT CLOCK
(Channel B)
This input is used in conjunction with the Clock Select bit
(CR1) in the command register to determine the baud clock
source for Channel B.
28
XCI/BCO-A
EXTERNAL CLOCK
INPUT/BAUD
CLOCK OUTPUT(Channel A)
This is a bidirectional port, which is used as the externally
applied baud clock input or the internal baud rate generator
output depending on the states of SELCLK and CR1 command bit. (Channel A)
33
XCI/BCO-B
EXTERNAL CLOCK
INPUT/BAUD CLOCK
OUTPUT-(Channel B)
This is a bidirectional port, which is used as the externally
applied baud clock input or the internal baud rate generator
output depending on the states of SELCLK and CR1 command bit. (Channel B)
26
CTS-A
CLEAR-TO-SEND
(Channel A)
V,L on this input enables Channel A to transmit serial data if
the Transmitter is enabled.
SIGNAL NAME
i5A'i'A
FUNCTION
This input is used in conjunction with the appropriate Chip
Select and an active read or write operation to determine
register access via the Data Bus.
178
PIN
NUMBER
SIGNAL
MNEMONIC
SIGNAL NAME
FUNCTION
35
Ci'S-B
CLEAR-TO-SEND
(Channel B)
V IL on this input enables Channel B to transmit serial data if
the Transmitter is enabled.
20
TXD-A
TRANSMIT DATA
(Channel A)
This is the Serial Data Output from Channel A.
2
TXD-B
TRANSMIT DATA
(Channel B)
This is the Serial Data Output from Channel B.
19
RXD-A
RECEIVE DATA
(Channel A)
This is the Serial Data Input for Channel A.
3
RXD-B
RECEIVE DATA
(Channel B)
This is the Serial Data Input for Channel B.
21
TXRDY-A
TRANSMITTER READY
(Channel A)
This output, when high (VOH), alerts the CPU that Channel A
is ready to accept a new data character. The TXRDY output is
automatically reset whenever a character is written into the
Transmit Holding Register and can be used as an interrupt to
the system. CTS must be asserted.
40
TXRDY-B
TRANSMITTER READY
(Channel B)
This output, when high (VOH), alerts the CPU that Channel B
is ready to accept a new data character. The TXRDY output is
automatically reset whenever a charaC1er is written into the
Transmit Holding Register and can be used as an interrupt to
the system. CTS must be asserted.
22
RXRDY-A
RECEIVER READY
(Channel A)
This output, when high 01 OH), alerts the CPU that Channel B
contains a data character that is ready to be input. This output is automatically reset whenever the new character is
read from the Receive Holding Register and can be used as
an interrupt to the system.
39
RXRDY-B
RECEIVER READY
(Channel B)
This output, when high01 OH), alerts the CPU that Channel B
contains a data character that is ready to be input. "ihis output is automatically reset whenever the new character is
read from the Receive Holding Register and can be used as
an interrupt to the system.
23
TXE-A
TRANSMITTER EMPTY
(Channel A)
This output, when high 01 OH), indicates that Channel A
Transmitter has no new characters to send and is waiting in
an idle state.
38
TXE-B
TRANSMITTER EMPTY
(Channel B)
This output, when high 01oH), indicates that Channel B
Transmitter has no new characters to send and is waiting in
an idle state.
24
BRKDET-A
BREAK DETECT
(Channel A)
This output, when high 01 OH), indicates that the Receiver for
Channel A has detected a break condition.
37
BRKDET-B
BREAK DETECT
(Channel B)
This output, when high 01 OH), ind icates that the Receiver for
Channel B has detected a break condition.
25
Ri'S-A
REQUEST-TO-SEND
(Channel A)
A general purpose output that is controlled by the command
register bit CR5 for Channel A.
36
R'fS-B
REQUEST-TO-SEND
(Channel B)
A general purpose output that is controlled by the command
register bit CR5 for Channel B.
1
NC
No Internal Connection.
179
ARCHITECTURE
If the internal BRG clock is selected, (SELCLK is high) then
the external clock input pin becomes a BRG clock output.
Hence, the mnemonic, "XCI/BCO".
The WD2123 is an eight bit bus-oriented device. Communication between the controlling CPU and the two RECEIVER/
TRANSMITTER CHANNELS or the two BAUD RATE GENERATORS occurs via the 8-bit data bus through a common
set of bus transceivers. Figure 1 is a Block Diagrarn of the
WD2123.
When CR1 (CS) is logic 0, then internal clock select mode is
selected. The transmit clock (TXC) is driven by the internal
BRG clock and the receive clock is driven by the select clock
pin, (SELCLK). The XCI/BCO pin becomes the baud clock
output (the same signal that is being applied to TXC).
A diagram of one of the two communication controllers is
shown in Figure 2. There are two accessible data registers,
which buffers transmit and receive data. They are the
TRANSMIT HOLDING REGISTER and the RECEIVE HOLDING REGISTER. There is a parallel-to-serial shift register, the
TRANSMIT REGISTER and a serial-Io-parallel shift reg isler,
the RECEIVE REGISTER.
The WD2123 also provides a local loop-back test mode of
operation for each channel. This diagnostic mode is independently controlled via the LB(CR7) bit of the COMMAND
REGISTER. When LB is logic 1, the channel is programmed
for Local Loop-Back. In this diagnostic mode, the TXD output
is set to the marking (logic "1 ") state; the output of the
TRANSMIT REGISTER is "looped-back" into the RECEIVER REGISTER input; RTS output is held high; the CTS
and RXD inputs are ignored. An additional requirement is
that the TEN(CRO) command bit and the REN(CR2) be logic
1. The status and output flags operate normally.
Operational Control and monitoring of the CHANNEL is performed by two CONTROL REGISTERS (the COMMAND INSTRUCTION REGISTER and the MODE INSTRUCTION
REGISTER) and the STATUS REGISTER.
A read/write control circuit allows programming/monitoring
or loading/reading of data in the CONTROL, STATUS and
HOLDING REGISTERS by activating the appropriate control
lines: Chip Select (CS1, CS2, CS3), READ ENABLE (RE),
WRITE ENABLE (WE) and CONTROL or DATA SELECT
(C/O).
Each channel is also provided with break character generation and detection. (A break character is defined as all zero
data bits, parity bit and stop bits after a valid start bit.) For
break character generation, SBRK (CR3) command bit is set
to a logic 1. This causes the TXD output to be forced low
(spacing) for as long as SBRK is programmed high. The
break detect output and status bit (SR6) is set to logic 1, indicating that the receiver has detected a break character.
The framing error flag is also set to 1 for this condition.
Internal control of each channel is by means of two internal
microcontrollers: one for transmit and one for receive. The
control registers, various counters and external signals provide inputs to the microcontrollers, which generate the necessary control signals to send and receive serial data according to the programmed protocol.
DATA
BUS
CSi
WE
CS2
(8)
AE
c/o
MA
BUS TRANSCEIVERS
TXD-B
TXD·A
AXO-A
TXADY-A
CHANNEL
CHANNEL
______
RXADY-A
TXRDY-B
RXRDY-8
TXE-S
TXE-A
BRKDET·B
BRKDET-A
RTs-B
CrS-B
RTS-A
ffi·A
SELCLK-B
SElCLK-A
BAUD RATE
BAUD RATE
GENERATOR
GENERATOR
XCI/BCO-S
XCI/BCO-A
GND
+5V
FIGURE 1.
WD2123 BLOCK DIAGRAM
180
The contents of the RATE REGISTER is decoded and ad·
dresses a FREQUENCY SELECT ROM for the proper fre·
quency, which is generated by the DIVIDER circuitry and the
control logic.
A diagram of one of the two BAUD RATE GENERATORS is
shown in Figure 3. The 4 low order DATA BUS bits, 00·03, are
used to program the desired rate by loading the RATE REGIS·
TER. Control signals CS3, We and C/O are used to select and
load the appropriate register.
TXRDY
RECEIVE AND
TRANSMIT
MICRO CONTROLLERS
TXE
/ - - - -.. RXRDY
/ - - - -.. BRKDET
t - - - -..
FiTS
~----CTs
READ/WRITE
CONTROL
LOGIC
TXC
RXC
C§O
Ai'! WE C/O
MR
CS1
CS2
FIGURE 2.
RECEIVE/TRANSMIT COMMUNICATIONS CONTROLLER DIAGRAM
181
INTERNAL DATA BUS (00·03)
~ ----'1J"-~WV;R;;rITrEE~....,
WE
(A) CII')
--_~
CONTROL
----t'"l_~L:::O:G:IC~_.J
(8) GIl')
~---,~
FREQUENCY
SELECT
__________________
ROM
~--~----L-__-=~~=-
~I
__
~~~~:>
DIVIDER
XTAL1
FIGURE 3.
XTAL2
WD2123 BAUD RATE GENERATOR DIAGRAM
The WD2123 registers are addressed by the following lable:
C/D
FiE
WE
CS1
CS2
CS3
L
L
H
L
H
H
RECEIVI: HOLDING REG.
-
CHA
L
H
L
L
H
H
TRANSMIT HOLDING REG.
-
CHA
H
L
H
L
H
H
STATUS REG.
-
CHA
H
H
L
L
H
H
MODI: AND COMMAND REG.
-
CHA
L
L
H
H
L
H
RECEIVE HOLDING Rm.
-
CHB
L
H
L
H
L
H
TRANSMIT HOLDING REG.
-
CHB
H
L
H
H
L
H
STATUS REG.
-
CHB
H
H
L
H
L
H
MODE and COMMAND REG.
CHB
L
H
L
H
H
L
RATE REG.
-
H
H
L
H
H
L
RATE REG.
-
CHB
X
X
X
H
H
H
DATA BUS IN HIGH IMPEDANCE MODE
Note:
"L" means VIL
pins.
"H" means VIH at pins.
"X" means don't care.
TABLE 1.
REGISTER SELECTED
WD2123 REGISTER ADDRESSING
at
182
CHA
FO
The WD2123 contains two MODE REGISTERS-one for
each channel. The format and definition of the
MODE REGISTERS are shown below:
B2
B1
0
0
0
1
1
0
1
Undefined
1X
16X
64X
L2
L1
CHARACTER LENGTH
1
The WD2123 contains two COMMAND REGISTERS-one
per channel. The format and definition of the
COMMAND REGISTERS are shown below:
BAUD RATE FACTOR
TRANSMIT ENABLE
TEN
Enable
Disable
1
0
CLOCK SELECT
XMIT and RCV Clock source
common
XMIT and RCV Clock sources
different
CS
1
0
0
0
0
1
1
0
1
1
5
6
7
8
Bits
Bits
Bits
Bits
RECEIVE ENABLE
REN
1
Enable
Disable
0
PARITY ENABLE
PEN
SEND BREAK CHARACTER
SBK
Disable Parity
Enable Parity
0
1
1
Force TXD Low
Normal Operation
0
PARITY SELECT
EP
ER
Odd Parity
Even Parity
0
1
ERROR RESET
1
Reset Error Flags
No Reset
0
S2
S1
0
0
0
1
1
0
NUMBER OF STOP BITS.
RTS
1
1
Invalid
1 Bit
1V2 Bits *
2 Bits
REQUEST TO SEND
1
Force RTS pin
Force RTS pin
0
IR
TABLE 2.
0
* 16X and 64X only. 1X will be 2 stop bits.
1 (VOH)
LB
LOOP BACK ENABLE
0
Normal Operation Mode
Local Loop-Back Mode
1
TABLE 3.
183
o (VOL)
INTERNAL RESET
Next Write to Mode Register
Next Write to Command
Register
1
WD2123 MODE REGISTERS
=
=
WD2123 CONTROL REGISTERS
The WD2123 contains two STATUS REGISTERS-one per channel. The STATUS REGISTER is a read-only register. The format and definition of the STATUS REGISTERS are shown below:
SR7
SR6
SR5
CTS
BRK
DET
FE
TXRDY
SR3
SR4
SR2
SRI
SRO
RX
ROY
TX
ROY
TRANSMITTER READY
1
Denotes THR is empty and ready for a
new character
THR not empty. (Reset when THR is
loaded by CPU)
0
RECEIVER READY
RXRDY
Denotes that the RHR contains a valid
character
RHR does not contain a valid character.
(Reset when the CPU reads the RHR)
I
0
TXE
TRANSMITTER EMPTY
Denotes that the TR is empty
Denotes that the TR is not empty
I
0
PE
PARITY ERROR
1
0
Denotes Parity Error
No Parity Error. (Reset by ER bit of command register)
OVERRUN ERROR
OE
Denotes Overrun Error
No Overrun Error. (Reset by ER bit of
command register)
1
0
FE
FRAMING ERROR
1
0
Denotes Framing Error
No Framing Error. (Reset by ER bit of
command register)
BRKDET
BREAK DETECT
Indicates that the receiver has detected a
line break condition. (FE will also be set)
No Break Condition detected for at least
one bit time
1
0
CTS
CLEAR-TO-SEND
1
0
Indicates that the CTS pin is active (VIl)
Indicates that the CTS pin is not active
(VIH)
TABLE 4.
WD2123 STATUS REGISTERS
184
The WD2123 contains two RATE REGISTERS that are used to select 16 BAUD rates when CR1 = 1 and
SELCLK = 1. The Format of the RATE REGISTERS is shown below. Note that the Receiver and the Transmitter of any channel run off the same Baud clock except when CR1 = 0, then the Transmitter runs off the
Baud Clock and the Receiver runs off an externally applied signal input on the SELCLK pin.
DO
07
RAO
RBO
RA3
x
x
RB3
When C/D=O, RA3 to RAO are loaded.
When C!D=1, RB3 to RBO are loaded.
em
The C/O line is used in conjunction with CS3 and ~to program the desired BAUD rate. When
is low, Channel
A is selected, and when C/O is high, Channel B is selected. The low order 4 bits of the DATA BUS are loaded into
the selected rate register, and the high order 4 bits are ignored.
When the crystal frequency equals 1.8432 MHz the following baud rates may be programmed.
R3
R2
R1
RO
BRF1X
BAUD RATE
BRF16X
BRF64X
FREQUENCY
(KHZ)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
800
1,200
1,760
2,150
2,400
3,200
4,800
9,600
19,200
28,800
38,400
57,600
76,800
115,200
153,600
307,200
50.0
75.0
110.0
134.5
150.0
200.0
300.0
600.0
1,200.0
1,800.0
2,400.0
3,600.0
4,800.0
7,200.0
9,600.0
19,200.0
12.50
18.75
27.50
33.59
37.50
50.00
75.00
150.00
300.00
450.00
600.00
900.00
1,200.00
1,800.00
2,400.00
4,800.00
0.80
1.20
1.76
2.15
2.40
3.20
4.80
9.60
19.20
28.80
38.40
57.60
76.80
115.20
153.60
307.20
TABLE 5.
WD2123 BAUD RATE SELECTION
185
DIVISOR
2304
1536
1049
855
768
576
384
192
96
64
48
32
24
16
12
6
READIWRITE OPERATIONS
The TXRDY, RXRDY, TXE and BRKDET FLAGS may be
connected to the microprocessor system as interrupt inputs
or the STATUS REGISTER can be periodically read in a
polled environment to support data communication control
operations.
The WD2123 must be initialized after a MASTER RESET
pulse by first writing the MODE INSTRUCTION word and
then the COMMAND INSTRUCTION word. Thereafter,
every control write to the device is interpreted as a
COMMAND word. If it is desired to re-program the MODE
REGISTER, a COMMAND REGISTER bit, INTERNAL
RESET (CR6), allows the next control write data to be
entered into the MODE REGISTER.
C/D = H
C/D
=L
(
=L
CID = H
The Receiver is equipped with logic to look for a break character. When a break is received, the BREAK DETECT
(BRKDET) FLAG and STATUS bit are set to "1". When the
receiver input line goes high 01IH) for at least one clock period, the receiver resets the BRKDET FLAG and resumes its
search for a start bit.
MODE INSTRUCTION WORD
COMMAND INSTRUCTION WORD
DATA
CHARACTER(S)
-
COMMAND INSTRUCTION WORD
CID = H
C/D
The SBRK bit of the COMMAND REGISTER (CR3) is used
to send a Break Character. (A Break Character is defined as
a start bit, and a II zero data, parity and stop bits.) When the
CR3 bit is set to a "1 ", it causes the transmitter output, TXD,
to be forced low after the last bit of the last character is
transmitted.
DATA
CHARACTER(S)
-
PROGRAMMING PROCEDURE
The programming sequence of the two channels will be different, depending on whether it is an initialization sequence
(that is, one performed right after a hardware master reset
occurs) or a re-programming sequence (that is, one performed to change the protocol characteristics (Parity, rate,
character length, etc.) after the device has been previously
operating in the system). The programming sequence differs, in that, after a master reset, the chip is set to expect the
first control write operation (C/D = 1) to contain a mode instruction. Any subsequent control write operations will be
transferred to the command instruction register.
COMMAND INSTRUCTION WORD
TYPICAL DATA BLOCK TRANSFER
OPERATING DESCRIPTION
The WD2123 is primarily designed to operate in an 8 bit microprocessor environment, although other control logic
schemes are easily implemented. The DJl:fA BUS and the interface control signals (CS1, CS2, CS3, ciiS, RE, WE) should
be connected to the microprocessor's data bus and system
control bus. A 1.8432 MHz crystal should be connected to
the WD2123 as shown in figure 5. The appropriate TXC
(RXC) clock frequencies should be programmed via system
software. Different Baud clock configurations are possible,
such as separate transmit and receive frequencies, and are
outlined in the general description.
Now when it is desired to change the mode instruction
register contents, the following re-programming sequence
should be performed. A Command Control word of "40" Hex
is written to the Chip. This tums off the Receiver and Transmitter and sets the IR (Internal Reset) bit. This bit causes the
read/write control logic to expect the next control write operation to be a new mode instruction. After the new mode
instruction is written to the chip, all subsequent control write
operations will again be interpreted as command instructions. Therefore, after the new mode instruction is performed, the next command would turn the receiver and
transmitter back on and resume normal Data operations.
For typical data communication applications, the RXD and
TXD inpuVoutputs can be connected to RS-232C interface
circuits. Interface control signals, C'fS and R'i'S, are controlled and sensed by the CPU through the COMMAND and
STATUS REGISTERS and can be configured in several
ways. The C'fS input can be used to synchronize the transmitter to external events.
186
~
C
N
N
W
+5V
30
DATA BUS
*
VCC
20
00-07
19
RXD-A
25
R'fS-A
26
Ci's:A
2
TXD-B
3
RXD-B
36
Ri'S-B
35
C'fS-ii
4
FiE
READ D---"-..-.
17
WRi'i"E o--~",
WE
TXD-A
29
RESETD--,.:;::.. . . MR
INTR
6
21
23
cio
TXRDY-A
RXRDY-A
TXE-A
24
BRKDET-A
40
TXRDY-B
38
37
WD2123
RXRDY-B
TXE-B
34
BRKDET-B
+5V
27
28
INTRA
BAUD CLOCK A OUTPUT
BAUD CLOCK B OUTPUT
AO
• RS232 INTERFACE
ADDRESS BUS
FIGURE 4.
WD2123 MICROPROCESSOR APPLICATION
187
ABSOLUTE MAXIMUM RATINGS
VDD with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Voltage on Any Pin with Respect to Ground .........................
Power Dissipation .............................................
Lead Temperature (Soldering 10 sec.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
0.5V to + 12V
- 0.5V to + 7V
500 Mw.
300°C
STORAGE TEMPERATURE:
Ceramic: -65°C to + 150°C
Plastic: -55°C to + 125°C
CRYSTAL SPECIFICATIONS:
Temperature range ............................................ O°C to + 70°C
Series resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 300Q to 500Q
Overall tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 0.01%
Note: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not
intended and should be limited to those conditions specified under dc electrical characteristics.
TABLE 6.
T A = O°C to
SYMBOL
DC ELECTRICAL CHARACTEFlISTICS
+ 70°C; Vee = 5.0V ±5%; GND = OV
PARAMETER
MIN
V,L
Input Low Voltage
-0.5
V,H
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
IOL
Data Bus Leakage
(High Impedance State)
I,L
Input Leakage
lee
TYP
100
TABLE 7.
SYMBOL
PARAMETER
UNIT
0.8
V
Vee
V
0.45
V
IOL = 1.6 mA
V
IOH
-50
10
uA
uA
VOUT
VOUT
10
uA
Y,N
125
mA
Vee - 5.25V
No Load
MAX
UNIT
TEST CONDITIONS
2.4
Power Supply Current
MIN
TEST CONDITIONS
MAX
= -100 uA
= 0.45V
= Vee
= Vee
CAPACITANCE
TYP
C'N
Input Capacitance
10
pF
fe == lMHz
CliO
I/O Capacitance
20
pF
Unmeasured pins
returned to
GND.
188
AC ELECTRICAL CHARACTERISTICS
TA
= O°C to + 70C;
SYMBOL
Vee
= 5.0V
TABLE 8.
±5%; GND
A.C. CHARACTERISTICS
= OV
CHARACTERISTIC
MIN
MAX
tAR
Address Stable Before READ (Cs,C/D)
50
ns
tRA
Address Hold Time for READ (CS,C/D)
50
ns
tRE
READ Pulse Width
230
ns
tRO
Data Delay from READ
tROH
READ to Data Floating
25
tAW
Address Stable Before WRITE
50
ns
tWA
Address Hold Time for WRITE
50
ns
tWE
WRITE Pulse Width
230
ns
tos
Data Set-Up Time for WRITE
TWE
ns
tWOH
Data Hold Time for WRITE
100
ns
1.6
us
UNITS
CONDITIONS
BUS PARAMETERS
Read Cycle
200
ns
200
ns
CL
= 50 pF
CL (Max)
CL(Min)
= 50 pF
= 15pF
Write Cycle
OTHER TIMINGS
tTxe
Transmit Clock Period
torx
TxD Delay from Falling Edge of TxC
tSRX
Rx Data Set-Up Time to Sampling Pulse
tHRX
fTX
tTPW
tTPO
ns
CL
=
100 pF
200
ns
CL
=
100 pF
Rx Data Hold Time to Sampling Pulse
200
ns
CL
=
100 pF
Transmitter Input Clock Frequency
1x Baud Rate
16x and 64x Baud Rate
DC
DC
Transmitter Input Clock Pulse Width
1x Baud Rate
1QX and 64x Baud Rate
1.0
800
us
ns
Transmitter Input Clock Pulse Delay
1x Baud Rate
16x and 64x Baud Rate
1.0
800
us
ns
1000
189
500
600
kHz
kHz
Clock
50% Duty
Cycle
TABLE 9.
CHARACTERISTICS
SYMBC
fRX
tRPW
tRPD
A.C. CHARACTERISTICS (CONTINUED)
MIN
MAX
Receiver Input Clock Frequency
1x Baud Rate
16x and 64x Baud Rate
DC
DC
500
600
Receiver Input Clock Pulse Width
1x Baud Rate
16x and 64x Baud Rate
1.0
800
us
ns
Receiver Input Clock Pulse Delay
1x Baud Rate
16x and 64x Baud Rate
1.0
800
us
ns
tTX
TxRDY Delay from Center of Stop Bit
tRX
RxRDY Delay from Center of Stop Bit
tiS
Internal BRKDET Delay from Center
of Data Bit
tTRD
tTOD
twc
8
Y2
UNIT
kHz
kHz
tRXC
tRXC
1
RXC
TxRDY Delay from Falling Edge of
WRITE
450
ns
TXD Output from Falling Edge of
WRITE
1Y2
tTXC
Control Delay from Rising Edge of
WRITE (RTS)
200
ns
tCR
Control to READ Set-Up Time (CTS)
tMR
Master Reset
1
ns
500
x::
VHAC
VLAC
FIGURES.
::X
A.C. TEST POINTS
.. ~
OATABUS
C§.c7D
~
tAR
tR'
FIGURE6.
READ TIMING
190
tTXC
l.oo
TEST
CONDITION
Clock
50% Duty
Cycle
CL = 50pF (16X)
~
DATA BUS
CS,
c75
'DS
I
I
I
\
"
1-
I
I
I
WE
II
\
~
j
-'AW- r-
E
\
RTS
'wc
~
CTS
RE
I·
1+----
'TPW
f-'WA
~
}
'CR
FIGURES.
-
'WE
WRITE TIMING
FIGURE 7.
WE
~
-
I
INTERFACE CONTROL TIMING
---+---
'TPD
--~~
TXC (1 x CLOCK)
16 TXC PERIODS
------1
TXD
ton
FIGURE 9.
TRANSMITTER CLOCK AND DATA TIMING
191
-
AXD
--- - ,/
v-- -
-
tSRX
\
AXC (1 x CLOCK)
f--
IRPW
AXD
-t
----
__ ,../f'I..
'-tHRX
\
tRPD
-
j;_______
START BIT
~
1s_1_DA_T_A_B_IT_________
AXC (16 x CLOCK)
IINTERNAL
SAMPLING PULSE
'I'
8 AXC
PEAIODS
__________
FIGURE 10.
~n~
16 AXC PERIODS
---1
____________________
~~
RECEIVER CLOCK AND DATA TIMINGS
TXC
cS,c75
u
tTRD
TXRDY
TXD
' -____________S:.;T.;,;A;,,;,AT;..;B::;.IT;......__________- J DATA
FIGURE 11.
TRANSMITTER OUTPUT TIMINGS WITH RESPECT TO TRANSMIT CLOCK
192
RXD - - - ,
START
~~
I~._B~IT~__~________D_A~~BITS
RXRDY
~--------------------------------------------~
FIGURE 12.
TXE
RXRDY TIMING
i
l fL
~,,-zn
'n
~-(;-G----uTXD
--------:I_~_~A_R_T____'__________DA~~tBITS
1"".------------------
PARITY
BIT
1st DATA BYTE
STOP
SIT(S)
I
C
~~ART
---+j+-,.I.I
r
2nd DATA
BYTE
FIGURE 13.
TXRDY TIMING
193
Printed
In
U S.A
See page 383 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However. no responsibility
IS
assumed by WeShHn D~qltti!
Corporation for Its use; nor for any infringements of patents or other rights of thtrd parties which may result from lIs use 1110 lIcense is granteo oy
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right tv change
specifications at anytime without notice.
194
Pnnted In U.S.A
WESTERN DIGITAL
c
o
R
p
o
R
A
T
/
o
N
WD8250 Asynchronous Communications Element
FEATURES
• Designed to be Easily Interfaced to Most Popular Microprocessors (Z-80, 8080A, 6800, etc.)
DO
D,
D2
D3
D4
D5
D6
D7
RCLK
SIN
SOUT
CSO
CS1
CS2
BAiJDOu'i'
XTAL1
XTAL2
DOSTR
DOSTR
vSS
• Full Double Buffering
• Independently Controlled Transmit, Receive,
Line Status, and Data Set Interrupts
• Programmable Baud Rate Generator Allows
Division of Any Input Clock by 1 to (2 '6 - 1)
and Generates the Internal 16x Clock
• Independent Receiver Clock Input
• Fully Programmable Serial-Interface
Characteristics
-5-, 6-, 7-, or 8-Bit Characters
-Even, Odd, or No-Parity Bit Generation and
Detection
-1-, 1 V2-, or 2-Stop Bit Generation
-Baud Rate Generation (DC to 56K Baud)
• False Start Bit Detector
• Complete Status Reporting Capabilities
3
vcc
Ai
RLS5
DSR
Ci'S
6
MR
6Oi"i"
8
9
DTR
RTS
5D"'i'2
12
14
15
INTRPT
NC
AO
A,
A2
ADS
CSOUT
DDIS
DISTR
DISTR
PIN DESIGNATION
• THREE-STATE TTL Drive Capabilities for Bidirectional Data Bus and Control Bus
• Line Break Generation and Detection
• Internal Diagnostic Capabilities
-Loopback Controls for Communications
Link Fault Isolation
-Break, Parity, Overrun, Framing Error
Simulation
• Full Prioritized Interrupt System Controls
• Single
+ 5-Volt Power Supply
DESCRIPTION
Internal registers enable the user to program
various types of interrupts, modem controls, and
character formats. The user can read the status of
the ACE at any time monitoring word conditions,
interrupts and modem status.
An additional feature of the ACE is a programmable baud rate generator that is capable of
dividing an internal XTAL or TTL signal clock by a
division of 1 to 2" - 1.
The ACE is designed to work in either a polling or
interrupt driven system, which is programmable
by users software controlling an internal register.
The WD8250 is a programmable Asynchronous
Communication Element (ACE) in a 40-pin package. The device is fabricated in N/MOS silicon
gate technology.
The ACE is a software-oriented device using a
three-state 8-bit bi-directional data bus.
The ACE is used to convert parallel data to a serial
format on the transmit side, and convert serial
data to parallel on the receiver side. The serial
format, in order of transmission and reception, is
a start bit, followed by five to eight data bits, a
parity bit (if programmed) and one, one and one
half (five bit format only) or two stop bits. The
maximum recommended data rate is 56K baud.
195
PIN DESCRIPTION
PIN
NUMBER
1
thru
8
MNEMONIC
DO
thru
07
SIGNAL NAME
DATA BUS
9
RCLK
RECEIVE CLK.
10
SIN
SERIAL INPUT
11
SOUT
SERIAL OUTPUT
12
13
14
CSO
CS1
CS2
CHIP SELECT
CHIP SELECT
CHIPSELECT
15
BAUDOUT
BAUDOUT
16
17
XTAL 1
XTAL2
18
19
DOSTR
DOSTR
20
21
22
VSS
DISTR
DISTR
23
DDIS
24
CSOUT
25
FUNCTION
3·state input/output lines. Bi·directional communication lines between WD8250 and Data Bus.
All assembled data TX and RX, control words, and
status information are transferred via the 00-07
data bus.
This input is the 16X baud rate clock for the
receiver section of the chip (may be tied to
BAUDOUT pin 15).
Received Serial Data In from the communications
link (Peripheral device, modem or data set).
Transmitted Serial Data Out to the communication
link. The SOUT signal is set to a (logic 1) marking
condition upon a MASTER RESET.
When CSO and CS1 are high, and CS2 is low, chip
is selected. Selection is complete when the address strobe ADS latches the chip select signals.
16X clock signal for the transmitter section of the
WD8250. The clock rate is equal to the oscillator
frequency divided by the divisor loaded into the
divisor latches. The BAUDOUT signal may be used
to clock the receiver by tying to (pin 9) RCLK.
EXTERNAL CLOCK IN
These pins connect the crystal or signal clock to
EXTERNAL CLOCK OUT the WD8250 baud rate divisor circuit. See Fig. 3
and Fig. 4 for circuit connection diagrams.
DATA OUT STROBE
When the chip has been selected, a low DOSTR or
DATA OUT STROBE
high DOSTR will latch data into the selected
WD8250 register (a CPU write). Only one of these
lines need be used. Tie unused line to its inactive
state. DOSTR - high or DOSTR - low.
GROUND
System signal ground.
DATA IN STROBE
When chip has been selected, a low DISTR or high
DATA IN STROBE
DISTR will allow a read of the selected WD8250
register (a CPU read). Only one of these lines need
be used. Tie unused line to its inactive state.
DISTR - high or DISTR - low.
DRIVER DISABLE
Output goes low whenever data is being read from
the WD8250. Can be used to reverse data direction
of external transceiver.
CHIP SELECT OUT
Output goes high when chip is selected. No data
transfer can be initiated until CSOUT is high.
ADDRESS STROBE
When low, provides latching for R~ter Select (AO,
A1, A2) and Chip Select (CSO, CS1, CS2)
NOTE: The rising edge (.) of the ADS signal is
required when the Register Select (AO, A1,
A2) and the Chip Select (CSO, CS1, CS2)
signals are not stable for the duration of a
read or write operation. If not required, the
ADS input can be tied permanently low.
196
PIN
NUMBER
26
27
28
A2
A1
AO
FUNCTION
SIGNAL NAME
REGISTER SELECT A2 These three inputs are used to select a WD8250
REGISTER SELECT A 1 internal register during a data read or write. See
REGISTER SELECT AO Table below.
29
30
NC
INTRPT
NO CONNECT
INTERRUPT
31
OUT2
OUTPUT 2
MNEMONIC
NoConnect
Output goes high whenever an enabled interrupt
is pending.
User-designated output that can be programmed
by Bit 1....QL the modem control register
1,
causes OUT2 to go low.
Output when low informs the modem or data set
that the WD8250 is ready to transmit data. See
Modem Control Register.
Output when low informs the modem or data set that the
WD8250 is ready to receive.
=
32
RTS
REQUEST TO SEND
33
DTR
DATA TERMINAL
READY
34
OUT1
OUTPUT 1
35
MR
MASTER RESET
36
CTS
CLEAR TO SEND
37
DSR
DATA SET READY
38
RSLD
RECEIVED LINE
SIGNAL DETECT
39
Ai
RING INDICATOR
40
VCC
+5V
User designated output can be programmed by Bit
2 of Modem Control Register
1 causes OUT1 to
go low.
When high clears the registers to states as indicated in Table 1.
=
Input from DCE indicating remote device is ready to
transmit. See Modem Status Register.
Input from DCE used to indicate the status of the local
data set. See Modem Status Register.
Input from DCE indicating that it is receiving a signal
which meets its signal quality conditions. See Modem
Status Register.
Input, when low, indicates that a ringing signal is being
received by the modem or data set. See Modem Status
Register.
+ 5 Volt Supply.
DATA
SER'ALIN
}
TO/FROM
PERIPHERAL
MODEM, OR
DATA SET
SYSTEM
PROCESSOR
I--tc:,.,.;~
SELECT AND
SERIAL
OAT A OUT
I--F~ CONTROL
LOGIC
1--+--1
MODEM-CONTROL
FUNCTIONS
TO FROM MODEM
OR DA TA SET
SYSTEM
INTERRUPT
FIGURE 1.
WD8250 GENERAL SYSTEM CONFIGURATION
197
I
I
Ii
INTERNAL
DATA BUS
(l-S)
DATA BUS
BUFFER
RECEIVER
BUFFER
REGISTER
~
LINE
CONTROL
REGISTER
_(2~~ .....
:~::
GSO
GSl
1552
m
MR
DISTR
i5iSrR
DOSTR
DOSTR
DDIS
CSOUT
XTAL1
:
RECEIVER
SHIFT
REGISTER
~
~
.--
~
DIVISOR
LATCH (LS)
(9)
i4----
-..
RCLK
(15)
BAUD
GENERATOR
(14)
.
(25)
SELECT AND
CONTROL
LOGIC
(35)
SIN
BAUDOUT
DIVISOR
LATCH (MS)
~
(13)
(22) -,.
RECEIVER
TIMING AND
CONTROL
(10)
(21)
LINE STATUS
REGISTER
TRANSMITTER
TIMING AND
CONTROL
TRANSMITTER
HOLDING
REGISTER
TRANSMITTER
SHIFT
REGISTER
(19)
(18)
(23)
(24)
(16)
_ (17)
(11)
SOUl
XTAL2
(32)
MODEM
CONTROL
REGISTER
I
(40)
(20)
. . +5V
... GND
MODEM
STATUS
REGISTER
INTERRUPT
ENABLE
REGISTER
NOTE:
A PPLICABLE PINOUT NUMBERS ARE
I NCLUDED WITHIN PARENTHESES
MODEM
CONTROL
LOGIC
r
INTERRUPT
ID REGISTER
FIGURE 2.
RTs
Ci'S
~~
(33)
~
INTERRUPT
CONTROL
LOGIC
I
i'iTR
liS'R
RSLD
m~
(34)
(31)
WD8250 BLOCK DIAGRAM
198
(37)
oun
0liT2
(30)
I~~
CHIP SELECTION AND REGISTER ADDRESSING
DLAB
Address Strobe (ADS pin 25): When low provides
latching for register select (AO, A1, A2) and chip
select (CSO, CS1, CS2).
0
0
0
0
0
0
NOTE: The rising edge ( .. ) of the ADS input is
required when Register Select (AO, A1, A2)
and Chip Select (CSO, CS1, CS2) signals are
not stable for the duration of a read or write
operation. If ADS is not required for latching,
this input can be tied permanently low.
X
0
0
1
1
1
1
0
0
1
1
1
0
0
0
0
X
X
X
X
X
1
1
Chip Select (CSO, CS1, CS2) pins 12·14: The
definition of chip selected is CSO, CS1 both high
and CS2 is low. Chip selection is complete when
latched by ADS or ADS is tied low.
Register Select (AO, A 1, A2) pins 26·28: To select a
register for read or write operation, see Register
Table.
NOTE: (DLAB) Divisor Latch access bit is the MSB
of the Line Control Register. DLAB must
be programmed high logic 1 by the system
software to access the Baud Rate Generator Divisor Latches.
TABLE 1.
A2 A1 AO
1
Register
0 Receiver Buffer (read), Transmitter
Holding Register (write)
1 Interrupt Enable
0 Interrupt Identification (read only)
1 Line Control
0 MODEM Control
1 Line Status
0 MODEM Status
1 None
0 Divisor Latch (least significant byte)
1 Divisor Latch (most significant byte)
WD8250 OPERATIONAL DESCRIPTION
Master Reset
A high-level input on pin 35 causes the WD8250 to
reset to the condition listed in Table 1.
WD8250 Accessible Registers
The system programmer has access to any of the
registers summarized in Table 2. For individual
register descriptions, refer to the following pages
under register heading.
RESET CONTROL OF REGISTERS AND PINOUT SIGNALS
Register/Signal
Reset Control
Receiver Buffer Register
Fi rst Word Received
Data
Transmitter Holding Register
Writing into the
Transmitter Holding Register
Data
Interrupt Enable Register
Master Reset
All Bits Low
(0-3 forced and 4-7 permanent)
Interrupt Identification Register
Master Reset
Bit 0 is High and
Bits 1-7 Are Permanently Low
Line Control Register
Master Reset
All Bits Low
MODEM Control Register
Master Reset
All Bits Low
Line Status Register
Master Reset
All Bits Low,
Except Bits 5 and 6 Are High
Modem Status Register
Master Reset
MODEM Signal Inputs
Gits 0-3 Low
Bits 4-7 - Input Signal
Data
Reset State
Divisor Latch (low order bits)
Writing into the Latch
Divisor Latch (high order bits)
Writing into the Latch
Data
SOUT
Master Reset
High
BAUDOUT
Writing Into either Divisor Latch
Low
CSOUT
ADS Strobe Signal and State of
Chip Select Lines
High/Low
DDIS
DDIS = CSOUT • RCLK • DISTR
(At Master Reset. the CPU
sets RCLK and DISTR lOW.)
High
INTRPT
Master Reset
Low
OUT 2
Master Reset
High
High
F-~
RTS
Master Reset
DTR
Master Reset
High
OUT 1
Master Reset
High
07-00 Data Bus Lines
In THREE-STATE Mode.
Unless CSOUT • DISTR = High
or CSOUT • DOSTR = High
THREE-STATE
Data (ACE to CPU)
Data (CPU to ACE)
199
TABLE 2.
SUMMARY OF WD8250 ACCESSIBLE REGISTERS
Register Address
Bit
No.
0
1
ODLAB=O
oDLAB=O
Receiver
Buffer
Register
(Read
Only)
Transmitter
Data BitO'
Data Bit 1
1DLAB=0
2
3
4
5
6
ODLAB 1
1DLAB=l
Interrupt
Enable
Register
Interrupt
Identification
Register
Line
Control
Register
MODEM
Control
Register
Line
Status
Register
MODEM
Status
Register
Divisor
Latch
(LS)
Divisor
Latch
(MS)
Holding
Register
(Write
Only)
Data BiIO·
Enable
Received
Data
Available
Interrupt
(ERBFI)
"0" if
Interrupt
Pending
Word
Length
Select
Bit 0
(WLSO)
Data
Terminal
Ready
(DTR)
Data
Ready
(DR)
Delta
Clear to
Send
(DCTS)
Bit 0
Bit 8
Data Bit 1
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
Interrupt
10
Bit (0)
Word
Length
Select
Bit 1
(WLS1)
Request
to Send
(RTS)
Overrun
Error
(OR)
Delta
Data Set
Ready
(DDSR)
Bit 1
Bit 9
Interrupt
10
Bit (1)
Number
of Stop
Bits
(STB)
Out 1
Parity
Error
(PE)
Trailing
Edge Ring
Indicator
(TERI)
Bit 2
Bit 10
Out 2
Framing
Error
(FE)
Delta
Receive
Line Signal
Detect
(DSLSD)
Bit 3
Bit 11
Loop
Break
Interrupt
(BI)
Clear to
Send
(CTS)
Bit 4
Bit 12
0
Transmitter
Holding
Register
Empty
(THRE)
Data
Set
Ready
(DSR)
Bit 5
Bit 13
Ring
Indicator
(RI)
Bit 6
Bit 14
Received
line
Signal
Detect
(RLSD)
Bit 7
Bit 15
Enable
Receiver
Line
Status
Interrupt
(ELSI)
2
Data Blt2
Data Bit 2
3
Data Bit3
Data Bit 3
Enable
MODEM
Status
Interrupt
(EDSSI)
0
Parity
Enable
(PEN)
4
Data Bit 4
Data Bit 4
0
0
Even
Parity
Select
(EPS)
5
Data Bit 5
Data Bit 5
0
0
Stick
Parity
6
Data Blt6
Data Bit 6
0
0
Set Break
0
Transmitter
Shift
Register
Empty
(TSRE)
7
Data Bit 7
Data Bit 7
0
0
Divisor
Latch
Access
Bit
(DLAB)
0
0
'Bit 0 is the least significant bit. It
IS
the first bit serially transmitted or received
200
Spacing (logic 0) state and remains there (until reset by
a low·level bit 6) regardless of other transmitter activity.
The feature enables the CPU to alert a terminal in a
computer communications system.
Line Control Register
Bits 0 and 1: These two bits specify the number of
bits in each transmitted or received serial character.
The encoding of bits 0 and 1 is as follows:
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Bit 7: This bit is the Divisor Latch Access Bit (DLAB).
It must be set high (logic 1) to access the Divisor
Latches of the Baud Rate Generator during a Read
or Write operation. It must be set low (logic 0) to
access the Receiver Buffer, the Transmitter Holding
Register, or the Interrupt Enable Register.
Word Length
5 Bits
6 Bits
7 Bits
8 Bits
WD8250 Programmable Baud Rate Generator
Bit 2: This bit specifies the number of stop bits in
each transmitted or received serial character. If bit
2 is a logic 0, 1 Stop bit is generated or checked in
the transmit or receive data, respectively. If bit 2 is a
logic 1 when a 5-bit word length is selected via bits 0
and 1, 1'12 Stop bits are generated or checked. If bit 2
is a logic 1 when either a 6-, 7-, or 8-bit word length is
selected, 2 Stop bits are generated or checked.
The WD8250 contains a programmable Baud Rate
Generator that is capable of taking any clock input
(DC to 3.1 MHz) and dividing it by any divisor from 1
to (2 '6 - 1). The output frequency of the Baud Generator is 16x the Baud rate. Two 8-bit latches store the
divisor in a 16·bit binary format. These Divisor
Latches must be loaded during initialization in order
to insure desired operation of the Baud Rate Generator. Upon loading either of the Divisor Latches, a
16-bit Baud counter is immediately loaded. This
prevents long counts on initial load.
Bit 3: This bit is the Parity Enable bit. When bit 3 is a
logic 1, a Parity bit is generated (transmit data) or
checked (receive data) between the last data word
bit and Stop bit of the serial data. (The Parity bit is
used to produce an even or odd number of 1s when
the data word bits and the Parity bit are summed.)
Bit 6: This bit is the Set Break Control bit. When bit 6
is a logic 1, the serial output (SOUT) is forced to the
Tables 3 and 4 illustrate the use of the Baud Generator with two different driving frequencies. One is referenced to a 1.8432 MHz crystal. The other is a 3.072
MHz crystal.
NOTE
The maximum operating frequency of the Baud
Generator is 3.1 MHz. However, when using
divisors of 6 and below, the maximum frequency
is equal to 1/2 the divisor in MHz. For example,
if the divisor is 1, then the maximum frequency is
1/2 MHz. In no case should the data rate be
greater than 56K Baud.
Line Status Register
This 8-bit register provides status information to the
CPU concerning the data transfer. The contents of
TABLE 3. BAUD RATES USING 1.8432 MHz CRYSTAL.
TABLE 4. BAUD RATES USING 3.072 MHz CRYSTAL.
Bit 4: This bit is the Even Parity Select bit. When bit 3
is a logic 1 and bit 4 is a logic 0, an odd number of
logic 1s is transmitted or checked in the data word
bits and Parity bit. When bit 3 is a logic 1 and bit 4 is a
logic 1, an even number of bits is transmitted or
checked.
Bit 5: This bit is the Stick Parity bit. When bit 3 is a
logic 1 and bit 5 is a logic 1, the Parity bit is transmitted and then detected by the receiver in the opposite
state indicated by bit 4.
Desired
Baud
Rate
Divisor Used
to Generate
16. Clock
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
NOTE: 1.8432 MHz
IS
Percent Error
Difference Between
Desired and Actual
0.026
0.058
-
0.69
_.
2.86
the standard 8080 frequency divided by 10.
201
Desired
Baud
Rate
Divisor Used
to Generate
16. Clock
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
3840
2560
1745
1428
1280
640
320
160
107
96
80
53
40
27
20
1(l.
5
3
Percent Error
Difference Between
Desired and Actual
0.026
0.034
0.628
1.23
-
14.285
:e
c
00
I\)
CJ'I
o
the Line Status Register are indicated in table 2 and
are described below.
Bit 0: This bit is the receiver Data Ready (DR) indicator.
Bit 0 is set to a logic 1 whenever a complete incoming
character has been received and transferred into the
Receiver Buffer Register. Bit 0 will be reset to a logic 0
either by the CPU reading the data in the Receiver
Buffer Register or by writing a logic 0 into it from the
CPU.
Bit 1: This bit is the Overrun Error (OE) indicator. Bit
1 indicates that data in the Receiver Buffer Register
was not read by the CPU before the next character
was transferred into the Receiver Buffer Register,
thereby destroying the previous character. The OE
indicator is reset whenever the CPU reads the contents of the Line Status Register.
Bit 2: This bit is the Parity Error (PE) indicator. Bit 2
indicates that the received data character does not
have the correct even or odd parity, as selected by
the even-parity-select bit. The PE bit is set to a logic
1 upon detection of a parity error and is reset to a
logic 0 whenever the CPU reads the contents of the
Line Status Register.
Bit 3: This bit is the Framing Error (FE) indicator. Bit
3 indicates that the received character did not have a
valid Stop bit. Bit 3 is set to a logic 1 whenever the
Stop bit following the last data bit or parity bit is
detected as a zero bit (Spacing level).
Bit 4: This bit is the Break Interrupt (BI) indicator. Bit
4 is set to a logic 1 whenever the received data input
is held in the Spacing (Logic 0) state for longer than
a full word transmission time (that is, the total time
of Start bit + data bits + Parity + Stop bits).
NOTE
Bits 1 through 4 are the error conditions that
produce a Receiver Line Status interrupt whenever any of the corresponding conditions are
detected.
Bit 5: This bit is the Transmitter Holding Register
Empty (THRE) indicator. Bit 5 indicates that the
WD8250 is ready to accept a new character for
transmission. In addition, this bit causes the
WD8250 to issue an interrupt to the CPU when the
Transmit Holding Register Empty Interrupt enable
is set high. The THRE bit is set to a logic 1 when a
character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The
bit is reset to logic Oconcurrently with the loading of
the Transmitter Holding Register by the CPU.
Bit 6: This bit is the Transmitter Shift Register Empty
(TSRE) indicator. Bit 6 is set to a logic 1 whenever
the Transmitter Shift Register is idle. It is reset to
logic 0 upon a data transfer from the Transmitter
Interrupt Identification Register
The WD8250 has an on chip interrupt capability that
allows for complete flexibility in interfacing to all
popular microprocessors presently available. In
order to provide minimum software overhead during data character transfers, the WD8250 prioritizes
interrupts into four levels. The four levels of interrupt conditions are as follows: Receiver Line Status
(priority 1); Received Data Ready (priority 2); Transmitter Holding Register Empty (priority 3); and
MODEM Status (priority 4).
Information indicating that a prioritized interrupt is
pending and source of that interrupt are stored in
the Interrupt Identification Register (refer to table
5). The Interrupt Identification Register (IIR), when
addressed during chip-select time, freezes the highest priority interrupt pending and no other interrupts are acknowledged until the particular
interrupt is serviced by the CPU. The contents of the
IIR are indicated in table 2 and are described below.
Bit 0: This bit can be used in either a hardwired
prioritized or polled environment to indicate
whether an interrupt is pending. When bit 0 is a logic
O. an interrupt is pending and the IIR contents may
be used as a pointer to the appropriate interrupt service routine. When bit 0 is a logic 1. no interrupt is
pending and polling (if used) continues.
Bits 1 and 2: These two bits of the IIR are used to
identify the highest priority interrupt pending as
indicated in table 5.
Bits 3 through 7: These five bits of the II R are always
logic O.
Interrupt Enable Register
This 8·bit register enables the four interrupt sources of
the WD8250 to separately activate the chip Interrupt
(INTRPT) output signal. It is possible to totally disable
the interrupt system by resetting bits 0 through 3 of the
Interrupt Enable Register. Similarly, by setting the
appropriate bits of this register to a logic 1, selected
interrupts can be enabled. Disabling the interrupt
system inhibits the Interrupt Identification Register
and the active (high) INTRPT output from the chip. All
other system functions operate in their normal manner,
including the setting of the Line Status and MODEM
Status Registers. The contents of the Interrupt Enable
Register are indicated in table 2 and are described
below.
Bit 0: This bit enables the Received Data Available
Interrupt when set to logic 1.
Bit 1: This bit enables the Transmitter Holding Register
Empty Interrupt when set to a logic 1.
Holding Register to the Transmitter Shift Register.
Bit 6 is a read-only bit.
Bit 2: This bit enables the Receiver Line Status Interrupt when set to logic 1.
Bit 7: This bit is permanently set to logic O.
202
TABLE 5.
INTERRUPT CONTROL FUNCTIONS.
Interrupt Identification
Register
Bit 2
Bit 1
Bit 0
0
0
1
Interrupt Set and Reset Functions
Priority Interrupt
Level
Flag
-
Interrupt
Source
Interrupt
Reset Control
None
-
Overrun Error or
Parity Error or
Framing Error or
Break Interrupt
Reading the
Line Status Register
Received
Data Available
Receiver
Data Available
Reading the
Receiver Buffer
Register
Transmitter
Holding Register
Empty
Transmitter
Holding Register
Empty
Reading the II R
Register (if source
of interrupt) or
Writing into the
Transmitter Holding
Register
MODEM
Status
Clear to Send or
Data Set Ready or Reading the
MODEM Status
Ring Indicator or
Register
Received Line
Signal Detect
None
1
1
0
Highest Receiver
Line Status
1
0
0
Second
0
0
1
0
0
0
Third
Fourth
Bit 3: This bit enables the MODEM Status Interrupt
when set to logic 1.
Bit 3: This bit controls the Output 2 (OUT 2) signal,
which is an auxiliary user-designated output. Bit 3
affects the OUT 2 output in a manner identical to
that described above for bit O.
Bits 4 through 7: These four bits are always logic O.
MODEM Control Register
Bit 4: This bit provides a loopback feature for diagnostic testing of the WD8250. When bit 4 is set to logic 1,
the following occur: the transmitter Serial Output
(SOUT) is set to a logic one (high) state; the receiver
Serial Input (SIN) is disconnected; the output of the
Transmitter Shift Register is "looped back" into the
Receiver Shift Register input; the four MODEM Control
Inputs (CTS, DSR, RLSD, and RI) are disconnected; and
the four MODEM Control outputs (DTR, RTS, OUT 1,
and OUT 2) are internally connected to the four MODEM
Control inputs. In the diagnostic mode, data that is
transmitted is immediately received. This feature
allows the processor to verify the transmit- and receivedata paths of the WD8250.
This 8-bit register controls the interface with the
MODEM or data set (or a peripheral device emulating a MODEM). The contents of the MODEM Control Register are indicated in table 2 and are
described below.
Bit 0: This bit controls the Data Terminal Ready
(DTR) output. When bit 0 is set to a logic 1. the DTR
output is forced to a logic O. When bit 0 is reset to a
logic O. the DTR output is forced to a logic 1.
NOTE
The DTR output of the WD8250 may be applied
to an EIA inverting line driver (such as the
DS1488) to obtain the proper polarity input at
the succeeding MODEM or data set.
In the diagnostic mode, the receiver and transmitter
interrupts are fully operational. The MODEM Control Interrupts are also operational but the interrupts' sources are now the lower four bits of the
MODEM Control Register instead of the four
MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register.
The WD8250 interrupt system can be tested by writing into the lower six bits of the Line Status Register
Bit 1: This bit controls the Request to Send (RTS)
output. Bit 1 affects the RTS output in a manner
identical to that described above for bit O.
Bit 2: This bit controls the Output 1 (OUT 1) signal,
which is an auxiliary user-designated output. Bit 2
affects the OUT 1 output in a manner identical to
that described above for bit O.
203
I
r
Bit 1: This bit is the Delta Data Set Ready (DDSR)
indicator. Bit 1 indicates that the DSR input to the
chip has changed state since the last time it was
read by the CPU.
and the lower four bits of the MODEM Status Register. Setting any of these bits to a logic 1 generates
the appropriate interrupt (if enabled). The resetting
of these interrupts is the same as in normal WD8250
operation. To return to this operation. the registers
must be reprogrammed for normal operation and
then bit 4 must be reset to logic O.
Bits 5 through 7: These bits are permanently set to
logic O.
Bit 2: This bit is the Trailing Edge of Ring Indicator
(TERI) detector. Bit 2 indicates that the AT input to
the chip has changed from an On (logic 1) to an Off
(logic 0) condition.
Bit 3: This bit is the Delta Received Line Signal
MODEM Status Register
Detector (DR LSD) indicator. Bit 3 indicates that the
This 8-bit register provides the current state of the
RLSD input to the chip has changed state.
control lines from the MODEM (or peripheral
NOTE
device) to the CPU. In addition to this current-state
Whenever bit O. 1. 2. or 3 is set to logic 1. a
information. four bits of the MODEM Status RegisMODEM Status Interrupt is generated.
ter provide change information. These bits are set to
a logic 1 whenever a control input from the MODEM
Bit 4: This bit is the complement of the Clear to Send
changes state. They are reset to logic 0 whenever
(CTS) input.
the CPU reads the MODEM Status Register.
Bit 5: This bit is the complement of the Data Set
The contents of the MODEM Status Register are
Ready (DSR) input.
indicated in table 2 and are described below.
Bit 6: This bit is the complement of the Ring IndicaBit 0: This bit is the Delta Clear to Send (DCTS) inditor
(AT) input.
cator. Bit 0 indicates that the CTS input to the chip
Bit 7: This bit is the complement of the Received
has changed state since the last time it was read by
Line Signal Detect (RLSD) input.
the CPU.
Typical Applications
Figures 3 and 4 show how to use the WD8250 chip in an 8080A system and in a microcomputer system with a highcapacity data bus.
"
"
AO
.,
.or---.
AO
XTALl
.,
26
8080A
MICROPAOCESSOR
"
,
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'>5
A..
~
"
CS'
DB3
8228/8238
SYSTEM
CONTROLLER
DB'
,
3
Dffi
0iJf"2
WD8250
(ACE)
OATA2
...
OATA4
6
,
,
DB5
DB6
CTs
DATA6
SOUT
21
iiOR
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liOW
AND DRIVER
FIGURE 3.
OISTA
DOSTA
SIN
35
RESET
8224 Clock
GENERATOR
,,~
1488
II~
1468
~
19
25
~
~
~
~
~.'5V
r---
~ r-"-
38
I/~
37
1489
'-I~ r-"-
36
r-"r---
DATA 7
DB'
,Z(TTLf
--:--t>
Al
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5
AU ANATE
MR
lNTAPT
i5iSTR
CSOUT
nOis
DOSTR
~
10
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r:-.
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29
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NCIl;ND
t-=-
GND
IVSS)
l"'5V
IVeel
-
1/.1488
r---
f-'..-
r---
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F:==
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i....-.!.--
TYPICAL 8·BIT MICROPROCESSOR/RS·232 TERMINAL INTERFACE USING THE ACE.
204
I
-2T~C~A2!J
DATA 1
,
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L _
ftS·232
DATAO
DB'
DB'
I
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II
5DTi ~
,
DATAPQRT
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DBO
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Typical Applications (continued)
ABSOLUTE MAXIMUM RATINGS
~=DO=ST~R-------
WRITE CYCLE TIMING
211
TABLE 12
READ/WRITE CYCLE TIMING
PARAMETER
SYMBOL
UNITS
MIN.
120
100
10
tACH
Address Strobe Width
Address and Chip Select Setup Time
Address and Chip Select Hold Time
tcss
tOlD
CSOUT Delay from latch
DISTRIDISTR Delay from latch
tDIW
tRC
RC
DISTR/DISTR Strobe Width
ns
ns
Read Cycle Delay
ns
Read Cycle = tACS + tOlD + tDIW + tRC + 20 ns
DISTR/DISTR to Driver Disable Delay
Delay from DISTR/DISTR to Data
ns
ns
ns
DISTR/DISTR to Floating Data Delay
ns
ns
60
20
ns
ns
175
685
1000
175
60
tAW
tACS
too
tODD
tHZ
tDOD
tDOW
twc
WC
tDS
tDH
tesc'
tDIC'
toOC'
tACR*
tACW'
tMR
ns
ns
ns
ns
DOSTRIDOSTR Delay From latch
DOSTR/DOSTR Strobe Width
Write Cycle Delay
Write Cycle = tACS + tDOD + tDOW + twc + 20 ns
Data Setup Time
ns
ns
Data Hold Time
CSOUT Delay from Select
ns
DISTR/DISTR Delay from Select
DOSTR/DOSTR Delay from Select
-Address and Chip Select Hold Time from DISTRIDISTR
ns
ns
ns
ns
Address and Chip Select Hold Time 10m DOSTRIDOSTR
ns
Master Reset Pulse Width
ns
MAX.
TEST
CONDITIONS
nTl load
160
nTl load
nTl load
nTl load
50
nTl load
300
nTl load
655
1125
nTl load
nTl load
nTl Load
200
300
nTl load
1TTl load
nTl load
1TTl load
nTl load
260
150
150
10
10
500
nTl load
1TTl load
nTl load
1TTl load
nTl load
1TTl load
1TTl load
nTl load
nTl load
'Only applicable when ADS is permanently low.
See page 383 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or otoer rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
212
WESTERN DIGITAL
r:
f7
R
P
0
RAT
/
0
N
TR1863/TR1865
Universal Asynchronous Receiver/Transmitter (UART)
FEATURES
• SINGLE POWER SUPPLY - +5'1DC
• D.C. TO 1 MHZ (64 KB) (STANDARD PARl)
TR1863/5
• FULL DUPLEX OR HALF DUPLEX OPERATION
• AUTOMATIC INTERNAL SYNCHRONIZATION
OF DATA AND CLOCK
• AUTOMATIC START BIT GENERATION
• EXTERNALLY SELECTABLE
Word Length
Baud Rate
Even/Odd Parity (ReceiveriVerification Transmitter/Generation)
Parity Inhibit
One, One and One-Half, or Two Stop Bit
Generation (1 V2 at 5 Bit Level)
• AUTOMATIC DATA RECEIVEDiTRANSMITTED
STATUS GENERATION
Transmission Complete
Buffer Register Transfer Complete
Received Data Available
Parity Error
Framing Error
Overrun Error
• BUFFERED RECEIVER AND TRANSMITTER
REGISTERS
• THREE-STATE OUTPUTS
Receiver Register Outputs
Status Flags
• TTL COMPATIBLE
• TR1865 HAS PULL-UP RESISTORS ON ALL
INPUTS
VCC
NC
vss
RRD
RRB
RR7
RR6
RR5
RR4
RR3
RR2
RR1
PE
FE
OE
SFD
RRC
DRR
DR
RI
10
11
12
13
14
15
16
17
18
19
20
TRC
EPE
WLS1
WLS2
SBS
PI
CRL
TRB
TR7
TA6
TR5
TR4
TA3
TR2
TA1
TRO
TRE
THRL
THRE
MR
PIN DESIGNATION
APPLICATIONS
• PERIPHERALS
• TERMINALS
• MINI COMPUTERS
• FACSIMILE TRANSMISSION
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
The Universal Asynchronous ReceiveriTransmitter
(UARl) is a general purpose, programmable or
hardwired MOS/LSI device. The UART is used to
convert parallel data to a serial data format on the
transmit side, and converts a serial data format to
parallel data on the receive side.
The serial format in order of transmission and
reception is a start bit, followed by five to eight data
bits, a parity bit (if selected) and one, one and onehalf, or two stop bits.
Three types of error conditions are available on each
received character: parity error, framing error (no valid
stop bit) and overrun error.
The transmitter and receiver operate on external16X
clocks, where 16 Qlock times are equal to one bit
MODEMS
CONCENTRATORS
ASYNCHRONOUS DATA MULTIPLEXERS
CARD AND TAPE READERS
PRINTERS
DATASETS
CONTROLLERS
KEYBOARD ENCODERS
REMOTE DATA ACQUISITION SYSTEMS
ASYNCHRONOUS DATA CASSETTES
time. The receiver clock is also used to sample in the
center of the serial data bits to allow for line
distortion.
Both transmitter and receiver are double buffered
allowing a one character time maximum between a
data read or write. Independent handshake lines for
receiver and transmitter are also included. All inputs
and outputs are TTL compatible with three-state
outputs available on the receiver, and error flags for
bussing multiple devices.
213
PIN DESCRIPTION
PIN
SIGNAL
NUMBER
MNEMONIC
1
2
3
4
VCC
NC
SIGNAL
NAME
FUNCTION
+ 5 volts supply
POWER SUPPLY
VSS
RRD
NC
GROUND
RECEIVER REGISTER
DISCONNECT
RR8RR1
RECEIVER HOLDING
REGISTER DATA
13
PE
PARITY ERROR
14
FE
FRAMING ERROR
15
OE
OVERRUN ERROR
16
SFD
STATUS FLAGS
DISCONNECT
17
RRC
RECEIVER REGISTER
CLOCK
DATA RECEIVED
RESET
DATA RECEIVED
5-12
18
19
DR
No Internal Connection
=
Ground
OV
A high level input voltage, VIH, applied to this
line disconnects the RECEIVER HOLDING
REGISTER outputs from the RR1-8 data outputs
(pi ns 5-12).
The parallel contents of the RECEIVER
HOLDING REGISTER appear on these lines if a
low-level input voltage, VIL, is applied to RRD.
For character formats of fewer than eight bits
received characters are right-justified with RR1
(pin 12) as the least significant bit and the
truncated bits are force(i..to a low level output
voltage, VOL.
A high level output voltage, VOH, on this line
indicates that the received parity differ from that
which is programmed by the EVEN PARITY
ENABLE (pin 39) and the PARITY INHIBIT (pin
35) control lines. This output is updated each
time a character is transferred to the RECEIVER
HOLDING REGISTER. PE lines from a number
of arrays can be bussed together since an
output disconnect capability is provided by
Status Flag Disconnect line (pin 16).
A high-level output voltage, VOH, on this line
indicates that the received character has no
valid stop bit, Le., the bit (if programmed) is not
a high level voltage. This output is updated each
time a character is transferred to the Receiver
Holding Register, FE lines from a number of
arrays can be bussed together since an output
disconnect capability is provided by the Status
Flag Disconnect line (pin 16).
A high-level output voltagE:, VOH, on this line
indicates that the Data Received Flag (pin 19)
was not reset before the next character was
transferred to the Receiver Holding Register.
OE lines from a number of arrays can be bussed
together since an output disconnect capability
is provided by the Status Flag Disconnect line
(pin 16).
214
A high-level input voltage, VIH, applied to this
pin disconnects the PE, FE, OE, DR and THRE
allowing them to be buss connected.
The receiver clock frequency is sixteen (16)
times the desired receiver shift rate.
A low-level input voltage, VIL, applied to this
line resets the DR line.
A high-level output voltage, VOH, indicates that
an entire character has been received and
transferred to the RECEIVER HOLDING
REGISTER.
PIN DESCRIPTION
PIN
NUMBER
SIGNAL
MNEMONIC
SIGNAL
NAME
FUNCTION
20
RI
21
MR
MASTER RESET
22
THRE
TRANSMITTER
HOLDING REGISTER
EMPTY
23
THRL
TRANSMITTER
HOLDING REGISTER
LOAD
24
TRE
TRANSMITTER
REGISTER EMPTY
25
TRO
TRANSMITTER
REGISTER OUTPUT
26-33
34
. RECEIVER INPUT
TRANSMITTER
REGISTER DATA
INPUTS
CRL
CONTROL REGISTER
LOAD
215
Serial input data. A high-level input voltage, VIH,
must be present when data is not being
received.
This line is strobed to a high-level input voltage,
VIH, to clear the logic. It resets the TRANSMITTER and RECEIVER HOLDING REGISTERS, the TRANSMITTER REGISTER, FE, OE,
PE, DR and sets TRO, THRE, and TRE to a
high-level output voltage, VOH.
A high-level output voltage, VOH, on this line
indicates the TRANSMITTER HOLDING REGISTER has transferred its contents to the
TRANSMITTER REGISTER and may be loaded
with a new character.
A low-level input voltage, VIL, applied to this
line enters a character into the TRANSMITTER
HOLDING REGISTER. A transition from a lowlevel input voltage, VIL. to a high-level input
voltage, VIH, transfers the character into the
TRANSMITTER REGISTER if it is not in the
process of transmitting a character. If a
character is being transmitted, the transfer is
delayed until its transmission is completed.
Upon completion, the new character is
automatically transferred simultaneously with
the initiation of the serial transmission of the
new character.
A high-level output voltage, VOH, on this line
indicates that the TRANSMITTER REGISTER
has completed serial transmission of a full
character including STOP bit(s). It remains at
this level until the start of transmission of the
next character.
The contents of the TRANSMITTER REGISTER
(START bit, DATA bits, PARITY bit, and STOP
bits) are serially shifted out on this line. When
no data is being transmitted, this line will
remain at a high-level output voltage, VOH. Start
of transmission is defined as the transition of
the START bit from a high-level output voltage
VOH, to a low-level output voltage VOL.
The character to be transmitted is loaded into
the TRANSMITTER HOLDING REGISTER on
these lines with the THRL Strobe. If a character
of less than 8 bits has been selected (by WLS1
and WLS2), the character is right justified to the
least significant bit, TR1, and the excess bits
are disregarded. A high-level input voltage, VIH,
will cause a high-level output voltage, VOH, to
be transmitted.
A high-level input voltage, VIH, on this line
loads the CONTROL REGISTER with the
control bits (WLS1, WLS2, EPE, PI, SaS). This
line may be strobed or hard wired to a high-level
input voltage VIH.
PIN DESCRIPTION
PIN
NUMBER
SIGNAL
MNEMONIC
SIGNAL
NAME
FUNCTION
35
PI
PARITY INHIBIT
36
SBS
STOP BIT(S) SELECT
WLS2-WLS1
WORD LENGTH
SELECT
37-38
A high-level input voltage, VIH, on this line
inhibits the parity generation and verification
circuits and will clamp the PE output (pin 13) to
VOL. If parity is inhibited, the STOP bit(s) will
immediately follow the last data bit of transmission.
This line selects the number of STOP bits to be
transmitted after the parity bit. A high-level
input voltage VIH, on this line selects two STOP
bits, and a low-level input voltage, VIL, selects a
single STOP bit. The TR1863 and TR1865
generate 11/2 stop bits when word length is 5
bits and SBS is High VIH.
These two lines select the character length
(exclusive of parity) as follows:
Word Length
WLS2
WLS1
---
39
40
I
EPE
EVEN PARITY
ENABLE
TRC
TRANSMITTER
REGISTER
---
5 bits
VIL
VIL
6 bits
VIL
VIH
7 bits
VIH
VIL
8 bits
VIH
VIH
This line determines whether even or odd
PARITY is to be generated by the transmitter
and checked by the receiver. A high-level input
VOltage, VIH, selects even PARITY and a lowlevel input voltage, VIL, selects odd PARITY.
The transmitter clock frequency is sixteen (16)
times the desired transmitter shift rate.
THRL
TRO
CONTROL
REGISTER
TRANSMITTER
TIMING AND
CONTROL
VCC(+5V)~
VSS(GND)~
TR1863/TR1865 BLOCK DIAGRAM
216
TRC
THRE
TRE
c
NO
A
TRANSMITTER FLOW CHART
217
-I
~
......
CO
Q)
~
~
1. TURN ON POWER
2. PULSE MASTER
RESET
3. SELECT BAUD
C
RATE 16XCLK
4. SET CONTROL BITS
......
CO
Q)
U1
TRANSFER DATA BITS FROM
RECEIVER REGISTER TO
RECEIVER HOLDING REGISTER
ANDSETOETO
PROPER STATE
RESET DR
ORR = VOL
DR-VOL
C
RECEIVER FLOW CHART
218
THRE
-t
:tI
u
THRL
-----.U
.....
CO
en
~
15CLOCKTIMES
AFTER START OF
LAST STOP BIT
(1)
TRE
.....!
:tI
.....
~ 1/2 CLOCK
CO
I
-:flL....:..i_________
I+-
TRO
1/2 CLOCK
l...... END OF LAST STOP
..
BIT (COUNT 16)
(1) NOT VALID FOR 5.0 MHZ OPTION
CR1
CR2
CF1
r-THRL
THRE
CASE I
lr-
r--
f--
...---...
THRE
CF5
r-'---
f--
f:\{~
~
L
THRE
lA
CF4
~
-....
(.... j
I
/'
f:\
~
/'
~
-i tpd ~
~TRE
~ I--""
TRO
THRL
-
r-
I"----'
TRE
CF4
CF3
r--
TRC ;---
CR5
CR4
CR3
CF2
~
DETAIL II
I CR4
L{~
f::\
~
....
1
TRO
tpd
I--
L
.-/
CASE I:
...---...
Li J )
r--
I
CASE II
TRE
TRO
DETAIL I
TRANSMITTER TIMING
219
IF THE POSITIVE TRANSITION OF
THRL OCCURS >250n8 PRIOR TO ANY
CLOCK FALLING EDGE (CF3 IN
SAMPLE) THE A, B, C, AND D SIGNALS
WILL BE GENERATED AS SHOWN IN
DETAIL II.
CASE II: IF THE POSITIVE TRANSITION OF
THRL OCCURS <;250n8 PRIOR TO ANY
CLOCK FALLING EDGE (CF3 IN
SAMPLE), THE B, C, AND D SIGNALS
MAY BE GENERATED ON THE FOL·
LOWING CLOCK TIME I.E. THE B, C,
AND D SIGNALS AS SHOWN IN
DETAIL MAY CHANGE AS FOLLOWS:
CF3 TOCF4
CF4 TOCF5
CR4 TO CR5
en
CJ1
I
r
START (1)
STOP START
-R-I----~I~~I~-_-_-_-_-_-D_-A_T~A~~~~~~~I~I
_R_R1_.R_R_8_A_N_D_E_R_R_0_R_F_~_G_S_P_E~,_FE_,_0_E_(5~)~
STOP
~I------D-AT-A------~----------
__________________
--JX~________
L
LJ
DR(19)
(2)U
DRR(18)
DETAIL:
2
3
5
4
6
7
8
10
9
11
12
13
14
15
0
RRC
NOMINAL
STOP BIT
RI
-1~~~ TRANSITION
NOMINAL BIT CENTER
I#'
I
PE'F~~:____________________________~X~------------------1
(5)
1,.1;......________________
~11------------------------~y\..:..II-------------it
y\
RR1·RR8,OE(3)
~~~--------~\EF~!I-------------DRR
-4t
--J
(2) -I
DR(3)
.rt--------LV
td
A....I (4)
(1) SEE APPLICATION FLAGS REPORT NO.1 FOR DESCRlp·
TION OF START BIT DETECTION
(2) THE DELAY BETWEEN DRR AND DR = td = 500 NS
(3) DR. ERROR FLAGS, AND DATA ARE VALID AT THE
NOMINAL CENTER OF THE FIRST STOP BIT
(4) DRR SHOULD BE HIGH A MINIMUM OF "A" NS (ONE·
HALF CLOCK TIME PLUS tpd) PRIOR TO THE RISING
EDGEOFDR
(5) DATA AND OE PRECEDES DR, PE, AND FE FLAGS BY
V. CLOCK
(6) DATA FLAGS WILL REMAIN SET UNTIL A GOOD CHARAC·
TER IS RECEIVED OR MASTER RESET IS APPLI ED.
FIGURE 1.
RECEIVER TIMING
220
ABSOLUTE MAXIMUM RATINGS
NOTE: These voltages are measured with respect to GND
Storage Temperature
Plastic ................. " - 55°C to + 125°C
Ceramic .................. - 65°C to + 150°C
VCC Supply Voltage ............. - 0.3V to + 7.0V
Input Voltage at any pin .......... - 0.3V to + 7.0V
Operating Free-AirTemperature
TA Range ....................... O°C to 70°C
Lead Temperature (Soldering, 10 sec.) ....... 300°C
ELECTRICAL CHARACTERISTICS
(VCC
= 5V ± 5%, VSS = OV)
SYMBOL
IlL
PARAMETER
OPERATING CURRENT
Supply Current
LOGIC LEVELS
Logic High
Logic Low
OUTPUT LOGIC LEVELS
Logic High
Logic Low
Output Leakage
(High Impedance State)
Low Level Input Current
IIH
High Level Input Current
ICC
VIH
VIL
VOH
VOL
IOC
MIN
TR1863/5
MAX
35ma
2.4V
0.6V
2.4V
0.4V
± 10fia
100fia
1.6ma
10fia
- 1Ofi a
X=-----==-=----Y2.0V
I
--------
= 5.25V
= 4.75V
VCC = 4.75V, IOH = 100fia
VCC = 5.25V, IOL = 1.6 ma
VOUT = OV, VOUT = 5V
SFD = RRD = V1H
VIN = 0.4V TR 1865 only
VIN = VIL. TR 1863 only
VIN = VIH, TR 1863 only
VCC
WLS1, WLS2, SBS, P1, EPE
TRB·TR1
__ J
CONDITIONS
VCC
r--------.
*--- ----......ljr
\ O.BV
'- __ _
CRLSTROBE
I
d
t s e t - ; ; . o _ t pw
te
I..
FIGURE 2.
DATA INPUT LOAD CYCLE
FIGURE 3.
221
~
CONTROL REGISTER LOAD CYCLE
RRD
SFD
~
~O.BV
------ -,
+tpd1-i
*PE, FE, OE, DR, THRE
-------
2.0V
" "-k..:B~
*RR1·RRB
__
4- t pdO.j
"""'
"
2.0V
~.~--
.... tpdO--!
* OUTPUTS PE, FE, OE, DR, THRE ARE DIS·
CONNECTED AT TRANSITION OF SFD
FROM O.BV TO 2.0V.
FIGURE 4.
O.BV
.... t pd1+f
*RR1·RR:J, ARE DISCONNECTED AT
TRANSITION OF RRD FROM O.BV TO 2.0V.
STATUS FLAG OUTPUT DELAYS
FIGURES.
DATA OUTPUT DELAYS
SWITCHING CHARACTERISTICS
(See FIGURE 1-5)
SYMBOL
fclk
tpw
PARAMETER
MIN
MAX
TR1863-00
DC
1.0MHz
TR1863-02
DC
2.5 MHz
TR1863-04
DC
3.5 MHz
TR1865·00
DC
1.0 MHz
with internal pull-ups on all inputs
TR1865·02
DC
2.5 MHz
with internal pull-ups on all inputs
TR1865-04
DC
3.5 MHz
with internal pull-ups on all inputs
Clock Frequency
CONDITIONS
VCC
= 4.75V
Pulse Widths
CRL(Fig.3)
200ns
THRL (Fig. 2)
200ns
DRR(Fig.1)
200ns
MR
500 ns
tc
Coincidence Time
200ns
thold
Hold Time (Fig. 2, 3)
tset
Set Time (Fig. 2, 3)
20ns
0
OUTPUT PROPAGATION
DELAYS
tpdO
To Low State (Fig. 4, 5)
250ns
tpd1
To High State (Fig. 4, 5)
250ns
CL
= 20 pf, plus one TTL load
CAPACITANCE
cin
Inputs
20pf
f
Co
Outputs
20pf
f
= 1 MHz, VIN = 5V
= 1 MHz, VIN = 5V
See page 383 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights Of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
222
WESTERN DIGITAL
CDR
P
0
RAT
/
0
N
TR1863/65 MOS/LSI Application Notes
Asynchronous Receiver/Transmitter
INTRODUCTION
With asynchronous transmission, a clock signal is not
transmitted with the data and the characters need not
be contiguous, In order for. the receiver to. properly
recover the message, the bits are grouped Into data
characters (generally from 5 to 8 bits in length) and synchronizing start and stop elements are added to each
character as shown in Figure 2.
The start element is a single logic zero (space) data
bit that is added to the front of each character. The
stop element is a logic one (mark) that is added to the
end of each character. The logic one (mark) level is
maintained until the next data character is ready to
be transmitted. (Asynchronous transmission is often
referred to as start-stop transmission for obvious
reasons). Although there is no upper limit to the
length of the stop element, there is a lower limit that
depends on the system characteristics. Typical lower
limits are 1.0, 1.42 or 2.0 data bit intervals, although
The transfer of digital data over relatively long distances is generally accomplished by sending the data
in serial form thru a single communications channel
using one of two general transmission techniques;
asynchronous or synchronous. Synchronous data
transmission requires that a clock signal be transmItted with the data in order to mark to location of the data
bits for receiver. A specified clock transition (either rising or falling) marks the start of each. data bit interval. as
shown in Figure 1. In addition, speCial synchronization
data patterns are added to the start of the transmission
in order for the receiver to locate the first bit of the message. with synchronous transmission, each data bit
must follow contiguously after the sync word, since one
data bit is assumed for every clock period or a fixed
multiple of clock periods.
CLOCK SIGNAL
r-LJ
\.----
LJLJ
, _ _ _ _ _ _ _,
V 8 BIT
TYPICAL
SYNC PATTERN
FIRST DATA
BIT
Figure 1.
FIRST DATA BIT
DATASIGNAL
!
SYNCHRONOUS DATA
START
ELEMENT
STOP ELEMENT
IDLE
_ _ _,.,A
...._ _--.,
STOP ELEMENT
r
~----~~~----START
ELEMENT
ONE8BIT
CHARACTER
(11001000)
/
FIRST
DATA
BIT
ONE8BIT
CHARACTER
(00100000)
START
ELEMENT
"'-
/
LAST
DATA
BIT
Figure 2.
FIRST
DATA
BIT
ASYNCHRONOUS DATA
223
"'-
LAST
DATA
BIT
LAST
DATA
BIT
1
-f
:a
.....
Q)
0)
to)
-0)
U1
Asynchronous transmission over a simple twisted wire
pair can be accomplished at moderately high baud
rates (10K baud or higher depending on the length of
the wire, type of the line drivers, etc.) while it is generally limited to approximately 2K baud over the telephone network. Other types of asynchronous
transmission can be as high as 218K baud. When operating over the telephone network, a modem is required
to convert the data pulses to tones that can be transmitted through the network.
most modern systems use 1.0 or 2.0. The negative
going transition of the start element defines the
location of the data bits in one character. A clock
source at the receiver is reset by this transition and is
used to locate the center of each data bit.
The rate at which asynchronous data is transmitted is
usually measured in baud, where a baud is defined to
be the reciprocal of the shortest signal element
(usually one data bit interval). It is interesting to note
that the variable stop bits is what makes the baud
rate differ from the bit rate. For synchronous transmission, each data element is equal to the clock
period therefore the baud rate equals the bit rate. The
same is true for asynchronous transmission if the
stop element is always one bit in duration (this is
referred to as isochronous transmission). However,
when the stop code is longer than one bit, as shown
in Figure 3, the baud rate differs from the bit rate.
One of the major limiting factors in the speed of
asynchronous transmission is the distortion of the
signal elements. Distortion is defined as the time
displacement between the actual signal level transmission and the nominal transition (at), divided by
the nominal data bit interval (See Figure 4).
The nominal data bit interval is equal to the reciprocal
of the nominal transmission baud rate and all data
transitions should ideally occur at an integer number
of intervals from the negative transition of the start
bit. Actual data transitions may not occur at these
nominal points in time as shown in the lower
waveform of Figure 4. The distortion of any bit
transition is equal to at x NOMINAL BAUD RATE.
Each character in Figure 3 is 11 data bit intervals in
length, and if 15 characters are transmitted per
second, then the shortest signal element (one data
bit interval) is 66.6 msJ11 = 6.06 ms; giving a rate of
1/6.06 ms
165 baud. However, since only 10 bits of
information (8 data bits, one start bit and 1 stop bit)
are transmitted every 66.6 msec, the bit rate is 150
bit/sec. (Even though the stop element lasts for two
data intervals, it still is only one bit of information.)
=
This distortion is generally caused by frequency jitter
and frequency offset in the clock source, used to
generate the actual waveform as well as transmission channel, noise, etc. Thus, the amount of
distortion that can be expected on any asynchronous
signal depends on the device used to generate the
signal and the characteristics of the communication
channel over which it was sent. Electronic signal
generators can be held to less than 1 % distortion
while electromechanical devices (such as a teletype)
typically generate up to 20% distortion. The transmission channel may typically add an additional 5%
to 15% distortion.
There are several reasons for using asynchronous
transmission. The major reason is that since a clock
signal need not be transmitted with the data, transmission equipment requirements are greatly simplified. (Note, however, that an independent clock
source is still required at both the transmitter and
receiver). Another advantage of asynchronous transmission is that characters need not be contiguous in
time, but are transmitted as they become available.
This is a very valuable feature when transmitting data
from manual entry devices such as a keyboard. The
major disadvantage of asynchronous transmission is
that it requires a very large portion of the communication channel bandwidth for the synchronizing
start and stop elements (a much smaller portion of
the bandwidth is required for the sync words used in
synchronous transmission).
The distortion previously described referred only to a
single character as all measurements were referenced to the start element transition of that character. However, there may also be distortion between
characters when operating at the maximum possible
baud rate (I.e., stop elements are of minimum length).
START ELEMENT
(ONE DATA BIT INTERVAL)
STOP ELEMENT - 2 STOP BITS
(2 DATA BIT INTERVALS)
~==~~~~~~~====~
I~•
.I
AT 15 CHARACTER/SEC
= 66.6 ms
I~
6.06 msec
Figure 3.
224
NOMINAL DATA
BIT INTERVAL
1-1
--~~~~~I
_____
MAj ~ J~
~~
__
STOP
~O~NJ::"
At3
At4
Us
Ats
~--------~
ACTUAL
WAVEFORM
LJ
At7
r--------
Figure4A.
tG
STOP ELEMENT
START ELEMENT
~START ELEMENT
{
L--.C--- -
DATABIT-;-- - -
~CHARAC~~::=---.
-~;ABIT;
------------
-
---
Figure4B.
cal tolerances or variations in the power line
frequency. With electronic receivers, the inaccuracies are due to frequency offset, jitter and
resolution of the clock source used to find the bit
centers. (The bit centers are located by counting
clock pulses). For example, even if the receiver clock
had no jitter or offset, and it was 16 times the baud
rate, then the center of the bit could only be located
within 1116 of a bit interval (or 6.25%) due to clock
re~olution. However, by properly phasing the clock,
thiS tolerance can be adjusted so that the sampling
will always be within ±3.125% of the bit center.
Thus, signals with up to 46.875% distortion could be
received. This number (the allowable receiver input
distortion) is often referred to as the receiver
distortion margin. Electromechanical receivers have
distortion margins of 25 to 30%. The receiver must
also be prepared to accept a new character after the
minimum character interval. Most receivers are
specified to operate with a minimum character interval distortion of 50%.
This type of distortion is usually measured by the
minimum character interval as shown in Figure 4B.
The minimum character interval distortion is generally specified as the percentage of a nominal data bit
interval that any character interval may be shortened
from its nominal length. Since many of the same
parameters that cause distortion of the data bits are
also responsible for the character length distortion
the two distortions are often equal. However, som~
systems may exhibit character interval distortions of
up to 50% of a data bit interval. This parameter is
important when operating at the maximum baud rate
since the receiver must be prepared to detect the
next start bit transition after the minimum character
interval.
Asynchronous receivers operate by locating the
nominal center of the data bits as measured from the
.start bit negative going transition. However. due to
receiver inaccuracies, the exact center may not be
properly located. In electromechanical devices such
as teletypes, the inaccuracy may be due to mechani-
225
-I
:D
.....
co
0')
c,.)
0 ')
C1I
TR1863/65 OPERATION
TR1863/65 is designed to transmit and receive asynchronous data as shown in Figure 5. Both the transmitter and the receiver are in one MOS CHIp, packaged in
a 40 lead ceramic DIP. The array is capable of full
duplex (simultaneous transmission and reception) or
half duplex operation.
The receiver assembles the asynchronous characters
into a. parallel data character by searching for the
start b~t of every char~cter, finding the center of every
data bit, and outputting the characters in a parallel
format with the start, parity and stop bits removed.
Three error flags are also provided to indicate if the
parity was in error, a valid stop bit was not decoded or
the last character was not unloaded by the external
device before the next character was received (and
therefore the last character was lost). The receiver
clock is set at 16 times the transmitter baud rate.
Both the transmitter and receiver have double character buffering so that at least one complete character interval is always available for exchange of the
characters with the external devices. This double buffering is especially important if the external device is
The transmitter basically disassembles parallel data
characters into a serial asynchronous data system.
Control lines are included so that the characters may
b~ 5, 6, 7 or 8 ~its in length, have an even or odd parity
bit, and have either one or two * stop bits. Furthermore,
the baud rate can be set anywhere between DC and
218K baud (3.5 MHz clock) by providing a transmit
clock at 16 times the desired baud rate.
* 1-1/2 with 5 bit code
RECEIVER
STATUS
TRANSMITTER
STATUS
DATA ERROR FLAGS
TRANSMITTER
I-
r - - - - -
CLOCK---I--~
I
I
PARALLEL
DATA IN ----,:+_~
I
TRANSMITTER
I
I
I
RECEIVER
1-.,-1---I. PARALLEL DATA
OUT
8
I
1-------"-- CONTROL
I
I DATA
I
PARALLEL
DATA
OUT
RECEIVER
CLOCK
RECEIVER CLOCK
• UART I
I
I 4.SYNCRHONOUS
I SERIAL
I
CONTROL --r-------"
3-- - - - ,
1
5
I
1_+--- PARALLEL DATA
IN
-+----'
3
DATA
ERROR
FLAGS
' - - - - - - r - - - TRANSMITTER
CLOCK
_ _ _ _ -.I
--...I
TRANSMITTER
STATUS
RECEIVER
STATUS
FigureS.
226
a computer, since this provides a much longer permissible interrupt latency time (the time required for
the computer to respond to the interrupt).
Table 1.
CONTROL DEFINITION
W W
L L
S
2
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
UART DESCRIPTION
Figure 6 is a block diagram of the transmitter portion of
the UART. Data can be loaded into the Transmitter
Holding Register whenever the Transmitter Holding
Register Empty (THRE) line is at a logic one, indicating
the the Transmitter Holding Register is empty. The data
is loaded in by strobing the Transmitter Holding Register Load (THRL) line to a logic zero. The data is automatically transferred to the Transmitter Register as
soon as the Transmitter Register becomes empty. The
desired start, stop and parity bits are then added to the
data and serial transmission is started. The number of
stop bits and the type of parity bit is under control of the
Control Register. The state of the control lines is loaded
into the Control Register when the Control Register
Load (CRL) line is strobed to a logic one. The 5 control
lines allow 24 different character formats as shown in
Table 1. These 24 formats cover almost all of the transmission schemes presently in use.
A Master Reset (MR) input is provided which sets the
transmitter to the idle state whenever this line is
strobed to a logic one. In addition, a Status Flag
Disconnect (SFD) line is provided. When this signal is
at a logic one, the THRE output is disabled and goes
to a high impedance. This allows the THRE outputs
of a number of arrays to be tied to the same data bus.
Figure 7 illustrates the relative timing of the transmitter signals. After power turn-on, the master reset
should be strobed to set the circuits to the idle state.
The external device can then set the transmitter
register data inputs to the desired value and after the
data inputs are stable, the load pulse is applied. The
data is then automatically transferred to the Trans-
CHARACTER FORMAT
CONTROL WORD
The status of the transmitter buffer and the receiver
buffer (empty or full) is also provided as an output.
Another feature of the UART is that the control information can be strobed into the transmitter and
receiver and stored internally. This allows a common
bus from a computer to easily maintain the controls
for a large number of transmitter/receiver.s.
The UART data and error flag outputs are designed
for direct compatibility with bus organized systems.
This feature is achieved by providing completely TTL
compatible Three-state outputs (no external components are required). Three-state outputs may be set
to a logic one or logic zero when enabled, or set to an
open circuit (very high impedance) when disabled. A
separate control line is provided to enable the data
outputs and another one to enable the error flags so
that the data outputs can be tied to a separate bus
from the flag outputs.
The TR1865 has internal pullups connected to its
inputs making it TTL compatible, while the TR1863
requires external pull ups to be connected to its input
pins.
S
P
I
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
S
P B START DATA PARITY STOP
BITS
BITS
S
BIT
BIT
E
1
0
0
0
0
0
0
E
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
x
x
0
0
1
1
x
x
0
0
1
1
x
x
0
0
1
1
x
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
5
1
1
1
1
1
5
5
5
5
5
6
6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
6
6
6
7
7
7
7
7
7
8
8
8
8
8
8
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
1
1.5
1
1.5
1
1.5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
mitter Register where the start, stop and parity (if
required) bits are added and transmission is started.
This process is then repeated for each subsequent
character as they become available. The only timing
requirement for the external device is that the data
inputs be stable during the load pulse (and 20 nsec
after).
The UART Transmitter output will have less than 1%
Distortion at baud rates of up to 218K baud (assuming
the Transmitter Register Clock is perfect) and is, therefore, compatible with virtually all other asynchronous
receivers.
Figure 8 is a block diagram of the Receiver portion of
the UART. Serial asynchronous data is provided to
the Receiver Input (RI). A start bit detect circuit
continually searches for a logic one to logic zero
transition while in the idle (logic one) state. When this
transition is located, a counter is reset and allowed to
count until the center of the start bit is located. If the
input is still a logic zero at the center, the signal is
assumed to be a valid start bit and the counter
continues to count to find the center of all subsequent data and stop bits. (Verification of the start
bit prevents the receiver from assembling an
erroneous data character when a logic zero noise
227
-I
l:J
..,I,
0)
en
w
en
U'I
S9/&98U:lJ.
STATUS FLAG DISCONNECT (16) (SFD)
TRANSMITTER
HOLDING REGISTEREMPTY
(22) (THRE)
ct
H ..
TRANSMITTER REGISTER OUT
(25) (TRO)
MASTER RESET (21) (MR)
START
TRANSMITTER REGISTER CLOCK (40) (TRG)
TRANSMITTER REGISTER EMPTY (24) (TRE)
TRANSMITTER REGISTER
DATA INPUTS
(26-33) (TR1 TO TRB)
8
TRANS
HOLD
REG
8
TRANS
REG
DATA
..
I\)
I\)
CD
TRANSMITTER HOLDING
REGISTER LOAD (23) (THRL)
..
EVEN PARITY ENABLE (39)
..
STOP BIT(S) SELECT (36)
CONTROL
8
L....
PARITY
GEN
¢:=
CONTROL
REG
PARITY INHIBIT (35) (PI)
(EPE)
(SBS)
WORD LENGTH SELECT (37-38)
STOP
BIT(S)
2WLS1-WLS2)
f
Figure 6.
TRANSMITTER BLOCK DIAGRAM
CONTROL REGISTER LOAD (34)
(CRL)
I IIL---_MASTER
RESET_ _ _ _ _
_
~
________-'x'-____---'x
u
TRANSMITTER REGISTER DATA INPUTS
u
TRANSMITTER HOLDING REGISTER LOAD
U
1
,
TRANSMITTER HOLDING REGISTER EMPTY
11:
----" f'
_I I
1/2 EXTERNAL CLOCK
iI--
r
I t I '-1
1/2 EXTERNALCLOCKI r--1I2EXTERNALCLOCK
START
START
DATA
--D-AT.-A--"--S-T-OP-
IS~~
TRANSMITTER REGISTER OUTPUT
15 EXTERNAL CLOCKS __
-II-
"-----_----'n~
__-----'I
TRANSMITTER REGISTER EMPTY
Figure 7.
TRANSMITTER TIMING DIAGRAM
spike is presented to the Receiver Input). The Receiver is under control of the Control Register described in the previous paragraph. This register
controls the number of data bits, number of stop bits,
and the type of parity as described in Table 2. The
word length gating circuit adjusts the length of the
Receiver Register to match the length of the data
characters. A parity check circuit checks for even or
odd parity if parity was programmed. If parity does
not check a Parity Error signal will be set to a logic
one and this signal will be held until the next
character is transferred to the Holding Register. A
circuit is also provided that checks the first stop bit
of each character. If the stop bit is not a logic one, the
Framing Error line will be set to a logic one and held
until the next character is transferred to the Holding
Register. This feature permits easy detection of a
break character (null character with no stop element).
As each received character is transferred to the
Holding Register, the Data Received (DR) line is set to
a logic one indicating that the external device may
sample the data output. When the external device
samples the output, it should strobe the Data
Received Reset (ORR) line to a logic zero to reset the
DR line. If the DR line is not reset before a new
character is transferred to the Holding Register (i.e., a
character is lost) the Overrun Error line will be set to a
logic one and held until the next character is loaded
into the Holding Register. The timing for all of the
Receiver functions is obtained from the external
Receiver Register Clock which should be set at 16
times the baud rate of the transmitter.
229
S9/£98U:U
I NTERNAL CONTROLS
FROM CONTROL REGISTER
Jl
RECEIVER
REGISTER
---
!
CLOCK (RRC) (17)
RECEIVER
DISCONNECT (RRD) (4)
WORD
LENGTH
GATING
RECEIVER
REG
RECEIVER INPUT
(Rl)(20)
~
FRAMING ERROR
(FE)(14)
PARITY ERROR
(PE)(13
START/STOP
DETECT &
BIT COUNTER
S
RECEIVER
HOLDING
REG
DATA
a
I
S
RECEIVER
HOLDING REG
DATA
(RR1- RRS)
(5-12)
PARITY
CHECK
"
DATA
RECEIVED
DETECT
-.J
DATA RECEIVED
RESET (DRR) (lS)
ENDOF
CHARACTER
DATA RECEIVED
(DR) (19)
-_ ...
~rn
---
STATUS FLAG DISCONNECT
(SFD)(16)
Figure 8.
RECEIVER BLOCK DIAGRAM
OVERRUN ERROR (15)
(OE)
Figure 9 illustrates the relative timing of the Receiver
signals. A Master Reset strobe places the unit in the
idle mode and the Receiver then begins searching for
the first start bit. After a complete character has been
decoded, the data output and error flags are set to
the proper level and the Data Received (DR) line is set
to a logic one. Although it is not apparent in Figure 9,
the data outputs are set to the proper level one half
clock period before the DR and error flags, which are
set in the center of the first stop bit. The Data
Received Reset pulse resets the DR line to a logic
zero. Data can be strobed out at any time before the
next character has been disassembled.
The UART Receiver uses a 16X clock for timing
purposes. Furthermore, the center of the start bit is
defined as clock count 7-1/2. Therefore, if the receiver
clock is a symmetrical square wave as shown in
Figure 10, the center of the bits will always be
located within ±3.125% (assuming a perfect input
clock) thus giving a receiver margin of 46.875%.
In Figure 10, the start bit could have started as much
as one complete clock period before it was detected
as indicated by the shaded area of the negative going
transition. Therefore, the exact center is also
unknown by the shaded area around the sample
point. This turns outto be ± 1/32 = ± 3.125%.
If the receiver clock is not perfect, then the receiver
distortion margin must be further reduced. For
example, if the clock had 1.0% jitter, 0.1 % offset and
the positive clock pulse was only 40% of the clock
cycle; then, for a 10 element character, the clock
would add:
1.0%
(Jitter)
+ (0.1% x 10) +
(Offset)
0.1 (1/16)
(Non-symmetrical Clock)
=
2.3% Distortion
(The frequency offset was multiplied by the number
of elements per character since the offset is cumulative on each element.
Since a clock with these characteristics is very easy
to obtain, it is apparent that a receiver operating
margin of slightly over 45% is very easy to achieve
when using the UART. Furthermore, this margin is
sufficient for virtually all existing transmitters and
modems presently in use.
The UART also begins searching for the next start bit
exactly in the center of the first stop bit so that
minimum character distortions of up to 50% can be
accepted.
II
MASTER RESET
~ I~----------------------
r ____
START
~I~I
STOP
r
START
I I
~_A_ _~I
D~
RECEIVER DATA INPUT
DATA RECEIVED (DR)
*
AND ERROR FLAGS
RECEIVER HOLDING REGISTER DATA OUT
u
DATA RECEIVED RESET
* NOTE:
DATA OUT AND OVERRUN ERROR PRECEDES
DR & ERROR FLAGS BY
112 CLOCK
Figure 9.
RECEIVER TIMING DIAGRAM
231
STOP
-I
:a
.CO
en
w
en
U'I
-4
....CO:::c
-
rCOUNT7-1/2
DETECT START I NVERVAL
0')
W
0 ')
c.n
RECEIVER CLOCK (16X)
TRUE CENTER OF START
RECEIVER INPUT
SAMPLE POINT
Figure 10_
A break character (null character without a stop bit)
will lock the receiver up since it will not begin looking for the next start bit until a stop bit has been
received.
pulse under control of the Data Out Strobe from the
micro-computer. When the control register should be
changed, a new 5 bit control word is placed on the
Data Output Bus and along with an appropriate
device address which is converted to a CRL load
pulse in the Address Decode circuits, again under
control of the Data Out Strobe_ A THRE Pulse to the
Interrupt Request circuit will notify the microcomputer when a new character may be provided to
the UART for transmission.
When a character has been received, a DR signal to
the Interrupt Request circuit will request an interrupt
from the micro-computer. The micro-computer will
respond by setting the proper device address and
provide a Data in Strobe pulse. The Address-Decode
circuit then sets the RRD line and SFD line to the
appropriate receiver to enable the Data Outputs onto
the mini Data Input Bus. The Data in Strobe from the
micro-computer then resets the DR signal with a
ORR pulse from the Address Decode circuit.
The UART Transmitter Output (TRO) and Receiver
Input (RI) must generally be converted to RS232
levels if they interface with a modem as shown in
Figure 12. RS232 is a standard that has been
established by the Electronic Industries Association
for the interface between data terminals and data
communications equipment. RS232-C defines a
space as greater than 3 volts and a mark as less than
negative 3 volts at the Receiver input. A transmitter
output of between 5 and 15 volts is a space while a
level between - 5 and -15 is a mark. The input/output impedances and signal rise and fall times are
also specified by RS232_ Fairly simple discrete level
translators can be used to convert from the TTL
levels to the RS232 levels, or monolithic IC's are also
available_
It should be noted that the typical application
illustrated in Figure 12 is only one of many and it
does not take advantage of many of the UART
features. For example, the Status Flags could be tied
to a separate interrupt request bus or the TRE output
could be used to implement half-duplex operation.
TYPICAL UART APPLICATION
The UART is ideally suited for use in distributed
computer networks such as is illustrated in Figure
11_ One of the primary purposes of the communications controller is to assemble and disassemble the
asynchronous characters (required for communication with the data terminals) to/from the parallel data
format required by the host computer. Often the communications controller is a micro-computer and character assembly/disassembly is performed by the
software_ When this is the case, the micro-computer
must be interrupted at a rate equal to 8 to 16 times
the baud rate of all terminals being handled by the
controller. (The actual interrupt rate depends on the
amount of distortion that can be experienced on the
received characters)_ When the number of terminals
exceeds 8 to 16, even the most powerful micro-computers become overloaded due to the high interrupt
rate and the complex algorithms required by the
software.
The UART greatly reduces this problem by performing the character assembly/disassembly functions in external hardware as shown in a typical
configuration in Figure 12. This solution not only
reduces the interrupt rate by a factor of up to 176, but
it also greatly reduces the micro-computer load, thus
freeing it for other functions.
Since the UART inputs and outputs are TTL compatible, it interfaces directly with virtually all microcomputer I/O busses. In Figure 12, the microcomputer Data Output Bus is connected to the
Transmitter Register (TR) inputs and the Control
Register inputs. When the micro-computer has a
character to transmit, the character is placed on the
Data Output bus and the address of the appropriate
UART is placed on the Device Address Bus. The
Address Decode circuit will output a THRL load
232
I.,
I
Figure 11.
233
DATA IN STROBE
I
BAUD RATE
CLOCK
(WDt943)
I
+
~
~
CRL THRL
TRC
I..-.--.
RRC
ADDRESS
DECODE
+
r
S RRD
ASYNC
MODEM
~
I
~
TRO
TOTTL
CONV
RI
II
DATA OUT STROBE
DDR
F
0
TRt
TRB
RS232
CONV
DEVICE ADDRESS BUS
A
~
EPE
WLSt
WLS2
TRt863/65
PI
SBS
RRt
RRB
PE
OE
•
•
•
•
•
•
•
•
•
•
OUTPUT
BUS
MICRO·PROCESSOR
COMPUTER
COMMUNICATIONS
CONTROLLER
•
•
•••
••
••
} M"
•
•
•
•
•
}M"
INPUT
BUS
FE
THRE DR
+ +
I
Figure 12.
INTERRUPT REQ
INTERRUPT
REQUEST
r
TYPICAL MICROCOMPUTER INTERFACE
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility Is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
234
Printed in U.S.A
WESTERN DIGITAL
c
o
R
p
o
R
A
T
o
/
N
UC1671 ASTRO
FEATURES
SYNCHRONOUS AND ASYNCHRONOUS
• Full Duplex Operations
SYNCHRONOUS MODE
• Selectable 5-8 Bit Characters
• Two Successive SYN Characters Sets
Synchronization
• Programmable SYN and OLE Character
Stripping
• Programmable SYN and DLE-SYN Fill
ASYNCHRONOUS MODE
• Selectable 5-8 Bit Characters
• Line Break Detection and Generation
• 1-, 1112-, or 2-Stop Bit Selection
• False Start Bit Detection Automatic Serial
Echo Mode
SYSTEM COMPATIBILITY
• Double Buffering of Data
• 8-Bit Bi-Directional Bus For Data, Status,
and Control Words
• All Inputs and Outputs TTL Compatible
• Up to 32 ASTROS Can Be Addressed On Bus
• On-Line Diagnostic Capability
TRANSMISSION ERROR DETECTION-PARITY
• Overrun and Framing
BAUD RATE -
(-5V) VBB
"iAcKi
Cs
TDATA (SA)
CTS(CB)
lACKO
IXTC (DB)
RPLY
'iNTR
IXRC(DD)
DALO
R4
9
DAU
R3
R2
DAL2
DAL3
R1
OAL4
CARR (CF)
DSR (CC)
DAL5
DAL6
14
RDATA (BB)
103
DAL7
15
OTR(CD)
15
104
ID7
17
ID5
RING (GEl
18
MR
Mise
19
iDs
(GND) Vss
20
VCC (·5V)
PIN DESIGNATION
DC TO 1M BIT/SEC
8 SELECTABLE CLOCK RATES
• Accepts 1X Clock and Up to 4 Different 32X
Baud Rate Clock Inputs
• Up to 47% Distortion Allowance with
32X Clock
APPLICATIONS
SYNCHRONOUS COMMUNICATIONS
ASYNCHRONOUS COMMUNICATIONS
SERIAL/PARALLEL COMMUNICATIONS
DESCRIPTION
The UC1671 (ASTRO) is a MOS/LSI device which
performs the functions of interfacing a serial data
communication channel to a parallel digital system.
The device is capable of full duplex communications
(receiving and transmitting) with synchronous or
asynchronous systems. The ASTRO is designed to
operate on a multiplexed bus with other bus-oriented
devices. Its operation is programmed by a processor
or controller via the bus and all parallel data transfers
with these machines are accomplished over the bus
lines.
The ASTRO is fabricated in n-channel silicon gate
MOS technology and is TTL compatible on all inputs
and outputs.
235
plemented to allow for an inversion when converting
to EIA RS232C levels. The names and symbols
assigned to the Data Set interface signals follows
EIA standard nomenclature.
PIN DESCRIPTION
c:
o
....
~
....
The device is packaged in a 4O-pin plastic or ceramic
cavity package. The interface signals are defined
below with all input/output signals complemented to
facilitate bussing and interfacing with TIL. The Data
Set controls and Status signals are also com-
PIN
NUMBER
1
MNEMONIC
A bar over a signal (SiGNAL), means active low (set
low).
=
FUNCTION
SIGNAL NAME
POWER SUPPLIES
-5V
INTERRUPT
ACKNOWLEDGE IN
This input becomes low when polling takes place on the
bus by the Controller to determine the interrupting
source. When this signal is received, the ASTRO places
its 10 code on the DAL if it is requesting interrupt, otherwise it makes IACKO a low.
2
VBB
IACKI
3
CS
CHIP SELECT
The low logic transition of CS identifies a valid address
on the DAL bus during Read and Write operations.
4
WE
WRITE ENABLE
This signal, when low, gates the contents of the DAL bus
into the addressed register of a selected ASTRO.
5
IACKO
INTERRUPT
ACKNOWLEDGE OUT
This output is made a logic low in response to a low
IACKI if the ASTRO receiving an IACKI input is not the
interrupting device.
6
RPLY
REPLY
This open drain output is made low when the ASTRO is
responding to being selected by an address on the DAL
during read or write operations or in affirming that it is
the interrupting source during interrupt pOlling.
7
INTR
INTERRUPT
This open drain output is made low when one of the communication interrupt conditions occur.
DALO-DAL7
DATA ACCESS LINES
Eight-bit bi-directional bus used for transfer of data, control, status, and address information.
DTR(CD)
DATA TERMINAL READY
This output is generated by a bit in the Control Register
and indicates Controller readiness.
107-103
SELECT CODE
Five input pins which when hard-wired assign the device
a unique identification code used to select the device
when addressing and used as an identification when
responding to interrupts.
18
RING (CE)
RING INDICATOR
This input from the Data Set generates an interrupt when
made low with Data Terminal Ready in the "Off" condition.
19
MISC
MISCELLANEOUS
This output is controlled by a bit in the Control Register
and is used as an extra programmable signal.
20
VSS
21
VCC
MR
MASTER RESET
The Control and Status Registers and other controls are
cleared when this input is low.
27
RDATA(BB)
RECEIVED DATA
This input receives serial data into the ASTRO.
28
I5SR (CC)
DATA SET READY
29
CARR(~)
CARRIER DETEC'fOR
This input generates an interrupt when going On or Off
while the Data Terminal Ready signal is On. It appears as
a bit in the Status Register.
This input from the Data Set generates an interrupt when
going On or Off if Data Terminal Ready is On. It appears
as a bit in the Status Register.
8-15
16
17,22,24,
25,26
23
Ground.
+5V
236
PIN DESCRIPTION (CONTINUED)
PIN
NUMBER
30-33
MNEMONIC
R1-R4
SIGNAL NAME
CLOCK RATES
FUNCTION
These four inputs accept four different local 32X data
rate Transmit and Receive clocks. The input on R4 may
be divided down into a 32X clock from a 32X, 64X, 128X,
or 256X clock input. The clock used in the ASTRO is
selected by the control Register.
34
IXRC(DD)
RECEIVER TIMING
This input is the Receiver 1X Data Rate Clock. Its use is
selected by the Control Register. The Received Data is
sampled by the ASTRO on the positive transition of this
signal.
35
IXTC(DS)
TRANSMITTER TIMING
This input is the Transmitter 1X Data Rate Clock. Its use
is selected by the Control Register. The transmitted data
changes on the negative transition ofthis signal.
36
CTS(CB)
CLEARmSEND
37
TDATA(BA)
TRANSMITTED DATA
This input, when low, enables the transmitter section of
the ASTRO.
This output is the transmitted serial data from the
ASTRO. This output is held in a Marking condition when
the transmitter section is not enabled.
38
RTS(CA)
REQUEST m SEND
This output is enabled by the Control Register and
remains in a low state during transmitted data from the
ASTRO.
39
RE
READ ENABLE
This signal, when low, gates the contents of an
addressed register from a selected ASTRO onto the DAL
bus.
40
VDD
+12V
\XRC
IxTc
A4
A3
A2
A1
J----~--~~-MISC
CARR
RING
DfR
i5SR
CTs
FiTs
MA
INTA
RPlY
iAci«5
IACKI
WE
Re
Cs
19 III 1919 Ie
UC1671 BLOCK DIAGRAM
237
c
o......
(J)
.......
......
c:
o....a.
Q)
.....
....a.
RECEIVER REGISTER - This 8-bit shift register
inputs the received data at a clock rate determined by
the Control Register. The incoming data is assembled to the selected character length and then
transferred to the Receiver Holding Register with
logic zeroes filling out any unused high-order bit
positions.
TRANSMITTER REGISTER - This 8-bit shift register
is loaded from the Transmitter Holding Register, SYN
register, or DLE register. The purpose of this register
is to serialize data and present it to the transmitted
Data output.
RECEIVER HOLDING REGISTER This 8-bit
parallel buffer register presents assembled receiver
characters to the DAL bus lines when requested
through a Read operation.
CONTROL REGISTERS - There are two 8-bit
Control Registers which hold device programming
signals such as mode selection, clock selection,
interface signal control, and data format. Each of the
Control Registers can be loaded from the DAL lines
by a Write operation or read onto the DAL lines by a
Read operation. The registers are cleared by a Master
Reset.
COMPARATOR - The 8-bit comparator is used in
the Synchronous mode to compare the assembled
contents of the Receiver Register and the SYN
register or DLE register. A match between the
registers sets up stripping of the received character,
when programmed, by preventing the data from
being loaded into the Receiver Holding Register. A bit
in the Status Register is set when stripping is performed. The comparator output also enables
character synchronization of the Receiver on two
successive matches with the SYN register.
STATUS REGISTER - This 8-bit register holds information on communication errors, interface data
register status, match character conditions, and
communication equipment status. This register may
be read onto the DAL lines by a Read operation.
DATA ACCESS LINES - The DAL is an 8-bit bidirectional bus port over which all address, data,
control, and status transfers occur. In addition to
transferring data and control words the DAL lines
also transfer information related to addressing of the
device, reading and writing requests, and interrupting
information.
SYN REGISTER - This 8-bit register is loaded from
the DAL lines by a Write operation and holds the
synchronization code used to establish receiver
character synchronization. It serves as a fill character
when no new data is available in the Transmitter
Holding Register during transmission. This register
cannot be read onto the DAL lines. It must be loaded
with logic zeroes in all unused high-order bits.
ASTRO OPERATION
ASYNCHRONOUS MODE
Framing of asynchronous characters is provided by a
Start bit (logic low) at the beginning of a character
and a Stop bit (logic high) at the end of a character.
Reception of a character is initiated on recognition of
the first Start bit by a positive transition of the
receiver clock, after a preceding Stop bit. The Start
and Stop bits are stripped off while assembling the
serial input into a parallel character.
The character assembly is completed by the reception of the Stop bit after reception of the last character or parity bit. If this bit is a logic high, the character
is determined to have correct framing and the ASTRO
is prepared to receive the next character. If the Stop
bit is a logic low the Framing Error Status flag is set
and the Receiver assumes this bit to be the Start bit
of the next character. Character assembly continues
from this point if the input is still a logic low when
sampled at the theoretical center of the assumed
DLE REGISTER - This 8-bit register is loaded from
the DAL lines by a Write operation and holds the
"DLE" character used in the Transparent mode of
operation in which an idle transmit period is filled
with the combination DLE-SYN. pair of characters
rather than a single SYN character. In addition the
ASTRO may be programmed to force a single DLE
character prior to any data character transmission
while in the transmitter transparent mode.
TRANSMITTER HOLDING REGISTER - This 8-bit
parallel buffer register holds parallel transmitted data
transferred from the DAL lines by a Write operation.
This data is transferred to the Transmitter Register
when the transmitter section is enabled and the
Transmitter Register is ready to send new data.
238
Start bit. As long as the Receive input is spacing, all
zero characters are assembled and error flags and
data received interrupts are generated so that line
breaks can be determined. After a character of all
zeroes is assembled along with a zero in the Stop bit
location, the first received logic high is determined
as a Stop bit and this resets the Receiver circuit to a
Ready state for assembly of the next character.
In the Synchronous mode a continuous stream of
characters are transmitted once the Transmitter is
enabled. If the Transmitter Holding Register is not
loaded at the time the Transmitter Register has
completed transmission of a character, this idle time
will be filled by a transmission of the character
contained in the SYN register in the Nontransparent
mode, or the characters contained in the DLE and
SYN registers respectively while in the Transparent
mode of operation.
In the Asynchronous mode the character transmission occurs when information contained in the
Transmitter Holding Register is transferred to the
Transmitter Register. Transmission is initiated by the
Insertion of a Start bit, followed by the serial output
of the character least significant bit first with parity, if
enabled, following the most significant bit; then the
insertion of a 1-,1.5-, or 2-bit length Stop condition. If
the Transmitter Holding Register is full, the next
character transmission starts after the transmission
of the Stop bit of the present character in the
Transmitter Register. Otherwise, the Mark (logic high)
condition is continually transmitted until the Transmitter Holding Register is loaded.
In order to allow re-transmission of data received at a
slightly faster character rate, means are provided for
shortening the Stop bit length to allow transmission
of characters to occur at the same rate as the
reception of characters. The Stop bit is shortened by
1/16 of a bit period for 1-Stop bit selection and 3/16
of a bit period for 1.5-, or 2-Stop bit selection, if the
next character is ready in the Transmitter Holding
Register.
DETAILED OPERATION
Receiver - The Receiver Data input is clocked into
the Receiver Register by a 1X Receiver Clock from a
modem Data Set, or by a local 32X bit rate clock
selected from one of four externally supplied clock
inputs. When using the 1X clock, the Receiver Data is
sampled on the positive transition of the clock in
both the Asynchronous and Synchronous modes.
When using a 32X clock in the Asynchronous mode,
the Receive Sampling Clock is phased to the MarkTo-Space transition of the Received Data Start bit and
defines, through clock counts, the center of each
received Data bit within + 0%, - 3% at the positive
transition 16 clock periods later.
In the Synchronous mode the Sampling Clock is
phased to all Mark-To-Space transitions of the
Received Data inputs when using a 32X clock. Each
transition of the data causes an incremental correction of the Sampling Clock by 1/32nd of a bit period.
The Sampling Clock can be immediately phased to
every Mark-To-Space Data transition by setting Bit 4
of Control Register 1 to a logic high, while the
Receiver is disabled.
SYNCHRONOUS MODE
Framing of characters is carried out by a special
Synchronization Character Code (SYN) transmitted at
the beginning of a block of characters. The Receiver,
when enabled, searches for two continuous characters matching the bit pattern contained in the SYN
register. During the time the Receiver is searching,
data is not transferred to the Receiver Holding
Register, status bits are not updated, and the Receiver interrupt is not activated. After the detection of
the first SYN character, the Receiver assembles
subsequent bits into characters whose length is
determined by contents of the Control Register. If,
after the first SYN character detection, a second SYN
character is present, the Receiver enters the Synchronization mode until the Receiver Enable Bit is
tumed off. If a second successive SYN character is
not found, the Receiver reverts back to the Search
mode.
When the complete character has been shifted into
the Receiver Register it is then transferred to the
Receiver Holding Register, the unused, higher number bits are filled with zeroes. At this time the Receiver Status bits (Framing Error/Sync Detect, Parity
Error/DLE Detect, Overrun Error, and Data Received)
are updated in the Status Register and the Data
Received interrupt is activated. Parity Error is set, if
encountered while the Receiver parity check is
enabled in the Control Register. Overrun Error is set if
the Data Received status bit is not cleared through a
239
c:
(')
.....
en
.....
""""
r
I
c:
(")
.....
-..
.....
en
Read operation by an external device when a new
character is ready to be transferred to the Receiver
Holding Register. This error flag indicates that a
character has been lost, as new data is lost and the
old data and its status flags are saved.
of the four selected rate inputs and divides the clock
down to the baud rate. This clock is phased to the
Transmitter Holding Register empty flag such that
transmission of characters occurs within two data bit
times of the loading of the Transmitter Holding Register when the Transmitter Register is empty.
The characters assembled in the Receiver Register
that match the contents of the SYN or OLE register
are not loaded into the Receiver Holding Register,
and the OR interrupt is not generated, if Bit 3 of
Control Register 2 (CR23 = SYN Strip) or Bit 4 of
Control Register 1 (CR14 = OLE Strip) are set
respectively, the SYN-OET and OLE-OET status bits
are set with the next non SYN or OLE character.
When both CR23 and CR14 are set (Transparent
mode), the OLE-SYN combination is stripped. The
SYN comparison occurs only with the character
received after the OLE character. If two successive
OLE characters are received only the first OLE
character is stripped. No parity check is made while
in this mode.
When the Transmitter is enabled, a Transmitter interrupt is generated each time the Transmitter Holding Register is empty. If the Transmitter Holding
Register is empty when the Transmitter Register is
ready for a new character the Transmitter enters an
idle state. Ouring this idle time a logic high will be
presented to the Transmitted Oata output in the
Asynchronous mode or the contents of the SYN
register will be presented in the Synchronous Nontransparent mode (CR16 = 0). In the Synchronous
Transmit Transparent mode (enabled by Bit 6 of
Control Register 1 = Logic 1), the idle state will be
filled by a OLE-SYN character transmission in that
order. When entering the Transparent mode the OLESYN fill will not occur until the first forced OLE.
Transmitter - Information is transferred to the
Transmitter Holding Register by a Write operation.
Information can be loaded into this register at any
time, even when the Transmitter is not enabled.
Transmission of data is initiated only when the
Request To Send bit is set to a logic one in the
Control Register and the Clear To Send input is a
logiC low. Information is normally transferred from
the Transmitter Holding Register to the Transmitter
Register when the latter has completed transmission
of a character. However, information in the OLE
register may be transferred prior to the information
contained in the Transmitter Holding Register if the
Force OLE signal condition is enabled (Bit 5 = Force
OLE and 6 = TX Transparent Control Register 1 set to
a logic one). The control bit CR15 must be set prior to
loading of a new character in the transmitter holding
register to insure forcing the OLE character prior to
transmission of the data character. The Transmitter
Register output passes through a flip-flop which
delays the output by one clock period. When using
the 1X clock generated by the Modem Oata Set, the
output data changes state on the negative clock
transition and the delay is one bit period. When using
a local 32X clock the transmitter section selects one
If the Transmitter section is disabled by a reset of the
Request to Send, any partially transmitted character
is completed before the transmitter section of the
ASTRO is disabled. As soon as the CTS goes high
the transmitted data output will go high.
When the Transmit parity is enabled, the selected
Odd or Even parity bit is inserted into the last bit of
the character in place of the last bit of the
Transmitted Register. This limits transfer of character
information to a maximum of seven bits plus parity or
eight bits without parity. Parity cannot be enabled in
the Synchronous Transparency mode.
DEVICE PROGRAMMING
The two 8-bit Control Registers of the ASTRO determine the operative conditions of the ASTRO chip.
Control Register 1 is shown in the following table.
240
BIT7
7
6
SYNC/ASYNC
ASYNC
O-LOOPMODE
1-NORMAL
MODE
O-NON BREAK
MODE
1-BREAK MODE
4
5
ASYNC ITRANS.
ENABLED)
0-1 1/2 or 2 STOP BIT
SELECTION
1-SINGLE STOP BIT
ASYNC ITRANS.
DISABLED
O-MiSCOOi'RESET
1- MISCOO'f SET
SYNC ICR16
=0)
O-NO PARITY
GENERATED
1-TRANSMIT PARITY
ENABLED
SYNC ICR16
= 11
2
1
0
~
~
SYNC/ASYNC
SYNC/ASYNC
SYNC/ASYNC
O-NON ECHO
MODE
1-AUTOECHO
MODE
O-NOPARITY
ENABLED
1-PARITY CHECK
ENABLED ON
RECEIVER PARITY
GENERATION
ENABLED ON
TRANSMITTER
O-RECEIVER
DISABLED
1-RECEIVER
ENABLED
O-RTs RESET
O-DTRRESET
1-RTsSET
1-i'ifRSET
§Y!::!f
O-NON TRANSMITTERTRANS·
PARENT MODE
1-TRANSMIT
TRANSPARENT
MODE
3
SYNC ICR12
=11
O-DLE
STRIPPING
NOT
ENABLED
1-DLE
STRIPPING
ENABLED
SYNC ICR12
=01
SYNC
O-RECEIVER PARITY
CHECK IS DISABLED
1-RECEIVER PARITY
CHECK IS ENABLED
o-MiSe RESET
1-MlSCSET
O-NO FORCE OLE
1-FORCE OLE
CONTROL REGISTER 1
Control Register 1
Bit 7 - A logic 0 configures the ASTRa into an Internal Data and Control Loop mode and disables the
Ring interrupt. In this diagnostic mode the following
loops are connected internally:
a. The Transmit Data is connected to the Receive
Data with the TD pin held in a Mark condition and
the input to the RD pin disregarded.
b. With a 1X clock selected, the Transmitter Clock
also becomes the Receive Clock.
c. The Data Terminal Ready (DTR) is connected to the
DataSet Ready (DSR) input, with the DTR output in
held in an Off condition (logiC high), and the DSR
input pin is disregarded.
d. The Request to Send Control bit is connected to
the Clear To SeQ.QlCTS) and Carrier Detector inputs, with the RTS output pin held in an Off
condition (logic high), and the CTS and Carrier
Detector input pins are disregarded.
3. The Miscellaneous pin is held in an Off (logic high)
condition.
A logic 1 on Bit 7 enables the Ring interrupt and
returns the ASTRa to the normal full duplex configuration.
Register when CR15 is a logic one in the sync mode.
Bit 5 - In the Asynchronous mode a logic 1, with the
Transmitter enabled, causes a single Stop bit to be
transmitted. A logic 0 causes 2-Stop bit transmission
for character lengths of 6, 7, or 8 bits and one-and-ahalf Stop bits for a character length of 5 bits.
With the Transmitter disabled this bit controls the
Miscellaneous output on Pin 19, which may be used
for Make Busy on 103 Data Sets, Secondary Transmit
on 202 Data Sets, or dialing on CBS Data Couplers.
In the Synchronous mode a logic 1 combined with a
logic 0 on Bit 6 of control Register 1 enables Transmit
parity; if CR15= 0 or CR15 = 1 no parity is generated.
When set to a logic 1 with Bit 6 also a logic 1, the
contents of the DLE register are transmitted prior to
the next character loaded in the Transmitter Holding
Register as part of the Transmit Transparent mode.
Bit 4 - In the Asynchronous mode a logic 1 enables
the Automatic Echo mode when the receiver section
is enabled. In this mode the clocked regenerated
data is presented to the Transmit Data output in place
of normal transmission through the Transmitter
Register. This serial method of echoing does not
present any abnormal restrictions on the transmit
speed of the terminal. Only the first character of a
Break condition of all zeroes (null character) is
echoed when a Line Break condition is detected. For
all subsequent null characters, with logic zero Stop
bits, a steady Marking condition is transmitted until
normal character reception resumes. Echoing does
not start until a character has been received and the
Transmitter is idle. The Transmitter does not have to
be enabled during the Echo mode.
In the Synchronous mode a logic 1, with the Receiver
enabled, does not allow assembled Receiver data
matching the DLE register contents to be transferred
to the Receiver Holding Register, also, parity checking is disabled.
Bit 6 - In the Asynchronous mode a logic 1 holds
the Transmitted Data output in a Spacing (Logic 0)
condition, starting at the end of any current transmitted character, when the Transmitter is enabled.
Normal Transmitter timing continues so that this
Break condition can be timed out after the loading of
new characters into the Transmitter Holding Register.
In the Synchronous mode a logic 1 sets the Transmitter in a transparent transmission which implies
that idle transmitter time will be filled by DLE-SYN
character transmission and a DLE can be forced
ahead of any character in the Transmitter Holding
241
c:
o
......
0)
......
......
When the Receiver is not enabled this bit controls
the Miscellaneous output on Pin 19, which may be
used for New Sync on a 201 Data Set. When
operating with a 32X clock and a disabled Receiver a
logic 1 on this bit also causes the Receiver timing to
synchronize on Mark-To-Space transitions.
Bit 3 - In the Asynchronous mode a logic 1 enables
check of parity on received characters and generation of parity for transmitted characters.
In the Synchronous mode a logic 1 bit enables check
of parity on received characters only. Note: Transmitter parity enable is controlled by CR15.
Bit 2 - A logic 1 enables the ASTRO to receive data
into the Receiver Holding Register, update Receiver
Status Bits 1, 2, 3, and 4, and to generate Data
Received interrupts. A logic 0 disables the Receiver
and clears the Receiver Status bits.
Bit 1 - Controls the Request To Send output on.£.!.!:!
38 to control the CA circuit of the Data Set. The RTS
output is inverted from the state of CR11. A logic 1
combined with a low logic Clear To Send input
enables the Transmitter and allows THRE interrupts
to be generated. A logic 0 disables the Transmitter
and turns off the external Request To Send signal.
Any character in the Transmitter Register will be
completely transmitted before the Transmitter is
turned off. The Request To Send output may be used
for other functions such as "Make Busy" on 103 Data
Sets.
Bit 0 - Controls the Data Terminal Ready output on
Pin 16 to control the CD circuit of the Data Set. A
logic 1 enables the Carrier and Data Set Ready. interrupts. A logic 0 enables only the telephone line
Ring interrupt. The DTR output is inverted from the
state of CR10.
Control Register 2
Control Register 2, unlike Control Register 1, cannot
be changed at any time. This register should be
changed only while both the receiver and transmitter
sections of the ASTRa are in the idle state.
Bits 7-6 - These bits select the character length as
follows:
BIT
7
6
SYNC/ASYNC
CHARACTER LENGTH SELECT
00
01
10
11
~
~
~
~
8 BITS
7 BITS
6 BITS
5 BITS
Character Length
Bits 7-6
8 bits
00
01
7 bits
10
6 bits
11
5 bits
When parity is enabled it must be considered as a bit
when making character length selection, i.e. 5
character bits plus parity 6 bits.
Bit 5 - A logic 1 selects the Synchronous Character
mode. A logic 0 selects the Asynchronous Character
mode.
Bit 4 - A logic 1 selects odd parity and a logic 0
selects even parity, when parity is enabled by CR13
and/or CR15.
Bit 3 - In the Asynchronous mode a logic 0 selects
the rate 1(-32X) clock input (pin 30) as the Receiver
Clock rate and a logic 1 selects the same clock rate
for the Receiver as selected by Bits 2-0 for the
Transmitter. This bit must be a logic 1 for the 1X clock
selection by Bits 2-0.
In the Synchronous mode a logic 1 causes all DLESYN combination characters in the Transparent
mode when DLE strip CR14 is a logic 1, or all SYN
characters in the Non-transparent mode to be
stripped and no Data Received interrupt to be
generated. The SYN Detect status bit is set ~i~h
reception of the next assembled character as It IS
transferred to the Receiver Holding Register.
Bits 2·0 - These bits select the Transmit and
Receive clocks. The Input Clock to the Rate 4 pin
may be divided down to form the 32X clock from a
multiple clock as shown:
Clock
Bits 2·0
1X clock for Transmit and Receive
000
(Pins 35 and 34 respectively)
32X clock - Rate 1 input (Pin 30)
001
32X clock - Rate 2 input (Pin 31)
010
011
32X clock - Rate 3 input (Pin 32)
32X clock - Rate 4 input + 1 (Pin 33)
100
32X clock - Rate 4 input + 2 (Pin 33)
101
32X clock - Rate 4 input + 4 (Pin 33)
110
32X clock - Rate 4 input + 8 (Pin 33)
111
=
5
4
3
2
MODE SELECT
SYNC/ASYNC
~
SYNC/ASYNC
O-ASYNCHRONOUS
MODE
1-SYNCHRONOUS
MODE
1-0DD PARITY
SELECT
O-EVEN PARITY
SELECT
1- RECEIVER CLOCK
DETERMINED BY
BITS 2-D
O-RECEIVER CLK
~ RATE 1
SYNC (CR14
~
0)
O-NO SYN STRIP
1-SYN STRIP
SYNC (CR14 ~ 1)
O-NO DLE-SYN STRIP
1-DLE-SYN STRIP
CONTROL REGISTER 2
242
1
0
CLOCK SELECT
000 - IX CLOCK
001 - RATE 1 CLOCK
010 - RATE 2 CLOCK
011 - RATE 3 CLOCK
100 - RATE 4 CLOCK
101- RATE 4 CLOCK + 2
110- RATE 4 CLOCK + 4
111- RATE 4 CLOCK + 8
Received is not reset, at the time a new character is
to be transferred to the Receiver Holding Register.
This bit is cleared when no Overrun condition is
detected, i.e., the next character transfer time or
when the Receiver is disabled.
Bit 1 - A logic 1 indicates that the Receiver Holding
Register is loaded from the Receiver Register, if the
Receiver is enabled. It is cleared to a logic 0 when the
Receiver Holding Register is read onto the Data
Access Lines, or the Receiver is disabled.
Bit 0 - A logic 1 indicates that the Transmitter
Holding Register does not contain a character while
the Transmitter is enabled. It is set to a logic 1 when
the contents of the Transmitter Holding Register is
transferred to the Transmitter Register. It is cleared to
a 0 bit when the Transmitter Holding Register is
loaded from the DAL, or when the Transmitter is
disabled.
Status Register
The data contained in the Status Register define
Receiver and Transmitter data conditions and status
of the Data Set. The Status word is shown and
defined below.
Bit 7 - This bit is set to a logic 1 whenever there is a
change in state of the Data Set Ready or Carrier
Detector inputs while Data Terminal Ready (Bit 0 of
Control Register 1) is a logic 1 or the Ring Indicator is
turned on, with DTR a logic O. This bit is cleared when
the Status Register is read onto the Data Access
Lines.
Bit 6 - This bit is the logic complement of the Data
Set Ready input on Pin 28. With 202-type Data Sets it
can be used for Secondary Receive.
Bit 5 - This bit is the logic complement of the
Carrier Detector input on Pin 29.
Bit 4 - In the Asynchronous mode a logic 1 indicates that received data contained a log 0 bit after
the last data bit of the character in the stop bit slot,
while the Receiver was enabled. This indicates a
Framing error. This bit is set to a logic 0 if the proper
logic 1 condition for the Stop bit was detected.
In the Synchronous mode a logic 1 indicates that the
contents of the Receiver Register matched the contents of the SYN Register. The condition of this bit
remains for a full character assembly time. If SYN
strip (CR23) is enabled this status bit is updated with
the character received after the SYN character. In
both modes the bit is cleared when the Receiver is
disabled.
Bit 3 - When the OLE Strip is enabled (Bit 4 of
Control Register 1) the Receiver parity check is
disabled and this bit is set to a logic 1 if the previous
character to the presently assembled character
matched the contents of the OLE register, otherwise
it is cleared. The OLE DET remains for one character
time and is reset on the next character transfer or on
a Status Register Read. If OLE Strip is not enabled,
this bit is set to a logic 1 when the Receiver is
enabled, Receiver parity (Bit 3 of Control Register 1)
is also enabled, and the last received character has a
Parity error. A logic 0 on this bit indicates correct
parity. This bit is cleared in either of the above modes
when the Receiver is disabled.
Bit 2 - A logic 1 indicates an Overrun error which
occurs if the previous character in the Receiver
Holding Register has not been read and Data
BIT 7
• DATA
SET
CHANGE
INPUT/OUTPUT OPERATIONS
All Data, Control, and Status words are transferred
over the Data Access Lines (DAL 0-7). Additional
input lines provide controls for addressing a particular unit, and regulating all input and output
operations. Other lines provide interrupt capability to
indicate to a Controller that an input operation is
requested by the ASTRO. All input/output terminology below is referenced to the Controller so that a
Read or Input takes data from the ASTRO and places
it on the DAL lines, while a Write or Output places
data from the DAL lines into the ASTRO. Bit 0 (DALO)
must be a logic low in a Read or Write operation.
Read
A Read Operation is initiated by the placement of an
eight-bit address on the DAL by the Controller. When
the Chip Select signal goes to a logic low state, the
ASTRO compares Bits 7-3 of the DAL with its hardwired 10 code (Pins 17, 22, 24, 25, and 26) and
becomes selected on a Match condition. The ASTRO
then sets its REPLY line low to acknowledge its
readiness to transfer data. Bits 2-0 of the address are
used to select ASTRO registers to read from as
follows:
Bits 2-0
Selected Register
Control Register 1
000
Control Register 2
010
Status Register
100
Receiver Holding Register
110
6
5
4
3
2
1
0
• DATA
SET
READY
• CARRIER
DETECTOR
• FRAMING
ERROR
• SYN
DETECT
• OLE
DETECT
• PARITY
ERROR
• OVERRUN
ERROR
• DATA
RECEIVED
• TRANSMITIER
HOLDING
REGISTER
EMPTY
STATUS REGISTER
243
c:
o...a.
0)
......
...a.
c::
o.....
0)
~
.....
When the Read Enable (RE) line is set to a logic low
condition by the Controller the ASTRO gates the
contents of the addressed register onto the DAL. The
Read operation terminates, and the devices becomes
unselected, when both the Chip Select and Read
Enable return to a logic high condition. Reading of
the Receiver Holding Register clears the DR Status
bit.
2. Transmitter Holding Register Empty (THRE) Indicates that the THR register is empty while the
Transmitter is enabled. The first interrupt occurs
when the Transmitter becomes enabled if there is
an empty THR, or after the character is transferred
to the Transmitter Register making the THR empty.
3. Carrier On -
Indicates Carrier Detector input
goes low when DTR is on.
4. Carrier Off - Indicates Carrier Detector input
goes high when DTR is on.
5. DSR On - Indicates the Data-SefReady input
goes low when DTR is on.
6. DSR Off - Indicates the Data Set Ready input
goes high when DTR is on.
7. Ring On - Indicates the Ring Indicator input goes
low when DTR is off.
Each time an Interrupt condition exists the INTR
output from the ASTRO is made a logic low. The
following interrupt procedure is then carried out even
if the interrupt condition is removed.
The Controller acknowled~ the Interrupt request by
setting the Chip Select (CS) and the mterrupt Acknowledge Input (~) to the ASTRO to a Low
state. On this transition all non-interrupting devices
receiving the IACKI set their Interrupt Acknowledge
Output (lAOKO) low, enabling lower priority daisy·
chained devices to respond to the Interrupt request.
The highest priority device that is interrupting will
then set its RPLY low. This device places it~ code
on Bit Positions 7-3 of the DAL when a low RE signal
is received. In addition Bit 2 is set to a logic one if any
of the interrupt numbers 1 and 3·7 above occurred,
and remains a logic zero if the THRE has caused the
interrupt.
To reset the Interrupt condition (INTR) Chip Select
(CS) and (IACKI) must be received by the ASTRO. A
setup time must exist between CS and the RE or WE
signals to allow chip selection prior to read/write
operations and deselection control through the latter
~nals. The data is removed from the DAL when the
RE signal returns to the logic high state.
Write
A Write operation is initiated by the placement of an
eight-bit address on the DAL by the Controller. The
ASTRO co~res Bits 7·3 of the DAL with its ID code
when the Chip Select input goes to a logic low state.
If a Match condition exists, the device is selected
and makes it's RPLY line low to acknowledge its
readiness to transfer data. Bits 2-0 of the address are
used to select ASTRO registers to be written into as
follows:
Bits2"()
000
010
100
110
Selected Register
Control Register 1
Control Register 2
SYN and DLE Register
Transmitter Holding Register
When the Write Enable (WE) line is set to a logic low
condition by the Controller the ASTRO gates the data
from the DAL into the addressed register. If data is
written into the Transmitter Holding Register, the
THRE Status bit is cleared to a logic zero.
The 100 address loads both the SYN and DLE registers. After writing into the SYN register the device is
conditioned to write into the DLE if followed by
another Write pulse with the 100 address. Any intervening Read or Write operation with other addresses resets this condition such that the next 100
will address the SYN register.
Interrupts
The following conditions generate interrupts:
1. Data Received (DR) - Indicates transfer of a new
character to the Receiver Holding Register while
the Receiver is enabled.
244
MAXIMUM RATINGS
Note:
VDD With Respect to VSS
(Ground)
Max Voltage To Any Input With
Respect to VSS
Operating Temperature
Storage Temperature Plastic
Ceramic
Power Dissipation
+20to -0.3V
+20to -0.3V
O°C to 70°C
- 55°C to + 125°C
-65°C to + 150'C
l000mW
Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous
operation at these limits is not intended and should
be I imited to those cond itions specified under DC
Electrical Characteristics.
OPERATING CHARACTERISTICS
TA = ooe to 70 oe, VOO = + 12.0V ± 5%, VSS = - 5.0V ± 5%, VSS = OV, Vee =
MIN
CHARACTERISTIC
SYMBOL
TYP
MAX
+ 5V
± 5%
CONDITIONS
UNITS
=
III
Input Leakage
10
~A
VIN
ILO
Output Leakage
10
~A
VOUT
ISS
Vss Supply Current
1
mA
Vss
ICCAVE VCC Supply Current
80
mA
IDDAVE VDD Supply Current
10
mA
VIL
Output High Voltage
VOL
Output Low Voltage
AC CHARACTERISTICS
TA = ooe to 70 oe, VOO =
eLMAX = 20pf
TAS
tAH
TARL
TCS
+ 12.0V
± 5%, VSS
V 10
2.8
V
.45
= - 5.0V
CHARACTERISTIC
Address Set·Up Time
Address Hold Time
MIN
CSWidth
± 5%, Vee
TYP
= + 5.0
MAX
= OV
CONDITIONS
ns
400
ns
ns
250
0
± 5%, VSS
UNITS
= -100~A
= 1.6 mA
10
ns
0
150
Address to RPL Y Delay
TCSRLF CS to Reply OFF Delay
TMR
V
.8
Input Low Voltage
(All Inputs)
VOH
SYMBOL
V
2.4
Input High Voltage
VIH
VDD
= VDD
= - 5V
250
ns
MRWidth
1.0
I1 s
Address and RE Spacing
250
ns
RL = 2.7 KQ
READ
TARE
TRECSH RE and CS Overlap
TRECS
RE to CS Spacing
TDV
RE to Data Out Delay
TOV
RE Off to DAL Open Delay
TRE
20
ns
250
ns
180
ns
20
250
ns
REWidth
200
1000
ns
Address to WE Spacing
250
WRITE
TAWE
ns
ns
TWECSH WE and CS Overlap
20
TWE
WE Width
200
TDS
Data Set·Up Time
150
TDH
Data Hold Time
100
ns
250
ns
TWECS WE to CS Spacing
245
1000
ns
ns
CL = 20 pI
c:
5AC
..
Cs
..
0
....,
CD
cs -----t---J
fiE
WE---+----=:-J
1 ;
VIH(min)
2 ; VIL (max)
3; VOH (min)
4 ; VOL (max)
NOTE 1;
10 DECODE is the major factor in
TARE and TAAL timing.
NOTE 2:
If changing the Control Registers
while processing data the WE pulse
width must be contained within the
Data Valid envelope to insure correct
data processing.
READ CYCLE TIMING DIAGRAM
WRITE CYCLE TIMING DIAGRAM
INTERRUPT
CHARACTERISTIC
TCSI
TCSRE
CS to IACKI Delay
CS to RE Delay
MIN
TYP
MAX
UNITS
0
ns
250
ns
TCSREH
CS and RE Overlap
20
ns
TRECS
RE to CS Spacing
250
ns
IACKI Pulse Width
200
Tpi
TIAD
IACKI to Valid ID
CONDITIONS
ns
250
ns
250
ns
250
ns
See Note 1.
Code Delay
TOV
TIARL
RE OFF to DAL Open Delay
20
iACKf to RPLY Delay
250
ns
300
ns
IACKI to IACKO Delay
200
ns
IACKO OFF Delay
250
ns
TCSRLF
CS to RPLY OFF Delay
TIAIH
IACKI ON to INTR OFF
0
RL = 2.7 KQ
Delay
Til
TioFF
From CS OFF, RE OFF, or
IACKI HIGH.
Note1: If RE goes low after IACKI goes low, the delay will be from the falling edge of RE.
Note 2: IACKO goes false after the last one of the following three signals go false: CS, REand
lACK!. TIOFF is measured from the last signal going false.
246
See Note2.
!
!'"
RP~-----+----------~~
Note1: i5A[O must bea logic low during CS to form
an Interrupt Cycle Address during Daisy Chain
Interrupt Response.
AE-------~
INTR----------------~--/
~--------------~
.--Tpi
CD ]'-0------=1
IACKO
TII,j
"{'-"0"--_ _ _~
INTERRUPT CYCLE TIMING DIAGRAM
247
c:
o
....
0)
.....
....
PRESET BIT COUNT
ASSEMBLE NEXT CHAR
RECEIVER SECTION
248
SYNC
ASYNC
ASYNCHRONOUS
SYNCHRONOUS
TRANSMITTER SECTION
249
See page 383 for ordering information.
c:
...o
...
CD
......
Inlormation furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its uSe. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporaticn. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
250
WESTERN DIGITAL
COR
PO
RAT
ION
WD1993 Arinc 429 Receiver/Transmitter
and Multi-Character Receiver/Transmitter
FEATURES
•
•
RETURN TO ZERO (RZ) OUTPUT
• AUTO SPACE GENERATION
•
DOUBLE BUFFERED RECEIVER AND TRANSMITTER
•
UNDERRUN ERROR DETECTION FOR TRANSMISSION
• OVERRUN, FRAMING AND PARITY ERROR DETEC
TION ON RECEIVER
• WORD ERROR FLAG FOR COMPREHENSIVE
ERROR REPORTING
•
FIRST CHARACTER OF WORD FLAG FOR SINGLE
INTERRUPT APPLICATIONS
•
DIAGNOSTIC LOCAL LOOP-BACK TEST MODE
•
DC TO 200 KILOBITS PER SECOND OPERATION
RE
vss
PRESENT UPON MASTER RESET FOR ARINC 429
PROTOCOL
WEF
cHi
1m
TXC
Ci
WE
N.C.
07
MA
06
TXE
05
AXAOY
D4
TXAOY
03
TXOO
02
TX01
01
AXC
DO
FCA
AX01
AXOO
VCC
PIN DESIGNATION
• TTL COMPATIBLE INPUTS AND OUTPUTS
• SINGLE +5 VOLT SUPPLY
• TEMPERATURE RANGES O·C to 70·C, - 1993-03,
- 4Q·C to + 85·C - 1993-02, - 55·C to + 125·C 1993-01
DESCRIPTION
The Western Digital WD1993 Avionic ReceiverlTransmitter
is designed to handle digital data transmission, according to
the Avionic Arinc 429 protocol.
The WD1993 is a bus-orientated MOS/LSI device designed
to provide the Avionics Arinc 429 Data Communication
Protocol.
Parallel data is converted into a serial data stream during
transmission and serial to parallel during reception. The
WD1993 is packaged in a 28 pin plastic or ceramic package
and is available in three temperature ranges: Commercial,
Industrial and Military.
Also, the WD1993 contains a local loop-back test mode of
operation, which is controlled by the Loop Test Enable (LTE)
bit in the command register. In this diagnostic mode, the
transmitter output is "looped-back" into the receiver input.
The REN and TEN control bits must also be active ("1") and
the CTS input must be low. The status and output flags operate normally.
251
PIN DESCRIPTION
PIN NO.
SIGNAL
MNEMONIC
FUNCTION
SIGNAL NAME
1
VSS
GROUND
Ground
2
WEF*
WORD ERROR
FLAG
This pin is an output, which when active indicates an error
in either the transmitter or receiver has been detected. It
reflects an underrun, overrun, parity or framing (receive
word) error and is intended as an error Interrupt. The
Status Register should be read to determine the specific
error.
3
CTS
CLEAR·TOSEND
This input is activated (VIIJ to enable the transmitter
logic.
4
TXC
TRANSMIT CLOCK
This input is the source clock for transmission. The data
rate is a function of this clock frequency.
ARINC MODE 4 x bit rate
I
=
5
EGND
EXTERNAL GROUND
Requires external ground for proper operation.
6
MR
MASTER RESET
When active (VI H), presets the WD1993 mode and
command registers to the ARINC protocol. Master Reset
also resets the data registers and piaces the WD1993
transmitter and receiver into idle states. After MR, the
command register is set to 00100101 and the mode
register is set to 00111100.
7
TXE
TRANSMITTER
EMPTY
This output goes high to indicate the end of a transmit
operation. TXE is automatically reset after the Transmit
Holding Register is ioaded.
8
RXRDY
RECEIVER READY
This output, when high, alerts the CPU that the Receiver
Holding Register contains a data character that is ready
to be input. This output is automatically reset whenever a
character is read from the WD1993. RXRDY is enabled
unless inhibited by setting command bit CR3 (RXRDYIN)
to a logiC "1." It is automatically enabled again after a
receive sequence is completed.
9
TXRDY
TRANSMITTER
READY
This output, when high, alerts the CPU that the Transmit
Holding Register is ready to accept a data character. The
TXRDY output is automatically reset whenever a charac·
ter Is written Into the WD1993 and can be used as an
interrupt to the system.
10
TXDO
TRANSMIT DATA
ZERO
This output drives the VIZ circuit when logic zero is to
be transmitted and is active for one-haif bit time.
11
TXD1
TRANSMIT DATA
ONE
This output drives the VIZ circuit when a logic one is to be
transmitted and is active for one-half bit time.
a
* The follOWing operation must be performed to clear the error in the Status Register and de-assert the Word Error Flag
1. Perform a Master Reset (MR) or;
2. Transfer a new character to the Receiver Holding Register after a reload of the Receiver Register.
252
PIN DESCRIPTION (CONTINUED)
PIN NO.
SIGNAL
MNEMONIC
~
FUNCTION
SIGNAL NAME
12
RXC
RECEIVE CLOCK
This input is the source clock for reception. The data rate
characteristics are the same as the transmit clock.
13
FCR
FIRST CHARACTER
READY
This output goes high after the receiver has completed
reception of the first character in a multi-character
sequence.
14
RXDO
RECEIVE DATA ZERO
RXDO is driven by the line VIZ receiver circuit. When the
VIZ circuit detects a logic zero, a TTL logic one (active for
one-half bit time) is provided to the WD1993.
15
VCC
POWER SUPPLY
+5VDC
16
RXD1
RECEIVE DATA ONE
The RXD1 input is driven by the VIZ line receiver. Each
time the VIZ circuit detects a logic one, a TTL level logic
one (active for one-half bit time) is provided to this input.
17
DATA BUS
This is the bi·directional data bus. It is the means of
communication between the WD1993 and the CPU.
Control, Mode, Data and Status Registers are accessed
via this bus.
22
DO
D1
D2
D3
D4
D5
23
24
D7
25
WE
18
19
20
21
D6
When active (VIU, allows the CPU to write into the
selected register.
When active (VIU, the device is selected. This enables
communication between the WD1993 and a microprocessor.
26
27
C/D
This input is used in conjunction with an active read or
write operation to determine register access via the DATA
BUS.
CONTROL/DATA
When active (VIU, allows the CPU to read data or status
information from the WD1993.
28
ARCHITECTURE
A readlwrite control circuit allows programming/monitoring
or loading/reading of data in the control, status or holding
registers by activating the appropriate control lines: Chip Select (CS), Read Enable (RE), Write Enable (WE),and Control
or Data Select (C/O).
A block diagram of the WD1993 is shown in Figure 1.
As mentioned, the WD1993 is an eight bit bus-oriented
device. Communication between the WD1993 and the controlling CPU occurs via the 8 bit data bus through the bus
transceivers. There are 2 accessible data registers, which
buffer transmit and receive data. They are the Transmit Holding Register and the Receive Holding Register. There is a
parallel-to-serial shift register (parallel in-serial out), the
transmit register and a seriaHo-parallel shift register (serial
in-parallel out), the receive register.
Internal control of the WD1993 is by means of two internal
microcontrollers; one for transmit and one for receive. The
control registers, null detect logic and various counters,
provide inputs to the microcontrollers which generate the
necessary control Signals to send and receive serial data according to the Arinc 429-1 protocol, along with the programmable multicharacter capabilities.
Operational control and monitoring of the WD1993 is performed by two control registers (the command instruction
register and the mode instruction register) and the status
register.
253
C
.....
CD
CD
W
FIGURE 1.
WD1993 BLOCK DIAGRAM
OPERATION
OPERATING DESCRIPTION
Upon master reset (MR), the device is programmed to transmit and receive four 8-bit contiguous characters with the
32nd bit inside odd parity. (ARINC protocol.)
The WD1993 is primarily designed to operate in an 8 bit
micro-processor environment. The DATA ELUS and the Interface Control Signals (CS, RE, WE and C/O) should be connected to the microprocessor's data bus and system control
bus.
A minimum four bit time space is automatically inserted after
the character transmission. Two receiver inputs, RXD1/RXOO
and two transmitter outputs, TXD1/TXDO, are provided to interface with voltage-impedance (VIZ) circuits to translate
± 10 volt ARINC line levels to 5 volt TTL logic levels. The
transmit clock (TXC) and receive clock (RXC), in ARINC
mode, are four times (4X) the bit rate desired.
The receiver monitors the received data input to detect a four
bit time null, which delimits the word. If the communications
link is broken during a word reception, the receiver will generate a word error flag to (WEF) to notify the CPU to request
retransmission. When a null is detected, the receiver logic is
reset and returned to an idle state awaiting the next word.
The Command Register is used to select features such as
parity options, loop test capability, RXRDY flag enabling,
transmitter and receiver enabling, and may also cause the
WD1993 to return to the Mode instruction.
The Status Register contains information such as Transmitter Ready, Transmitter Empty, Receiver Ready, error conclitions, and First Character Ready.
The appropriate TXC and RXC clock frequencies should be
selected for the particular application, using a programmable
baud rate generator such as a WD1943. A master reset pulse
initializes the WD1993 and presets the control registers to the
ARINC protocol.
The RXD1/RXDO inputs are interfaced to the DITS data line
via external level translators that provide TTL (5V) logic levels to the WD1993. The TXD1/TXDO outputs are connected
to high voltage (± lOV) driver circuits. Figures 16 and 17
show some typical ± 10V translator and driver circuits.
The TXRDY, RXRDY, FCR and WEF Flags may be connected to the microprocessor system as interrupt inputs. The
status register can be periodically read in a polled environment to supportWD1993 operations.
The ~ input can be used to synchronize the transmitter to
external events.
The WD1993 is designed such that a control register write
operation accesses the command instruction register.
The RXRDYIN bit of the command register is used to inhibit
the RXRDY output pin for ARINC operations.
254
Several "flags" are provided for interrupt purposes so that
continuity is maintained and data integrity is preserved.
These flags are First Character Ready (FCR), Receiver Ready
(RXRDY), Transmitter Ready (TXRDY) and Transmitter
Empty (TXE).
The Receiver operates similarly:
a) With the control registers suitably programmed, the
receiver is enabled, REN (CR2) = "1 ".
b) The RXRDY and FCR flags are "0". (Inactive).
The Transmitter operates as follows:
c) The incoming data word activates the receive logic and
the data begins to be assembled in the Receiver Register.
a) With the mode and command registers programmed
as desired, the transmitter is enabled, TEN (CRO) =
"1" .
d) When the first character is completely assembled in the
Receiver Register, the data is loaded into the Receive
Holding Register and the FCR (First Character Ready)
and RXRDY (Receiver Ready) flags become active. The
CPU should read the data in the Receiver Holding Register to reset the FCR and first RXRDY. If the Arinc 429
character is accepted, three more RXRDY's will be generated for the three remaining bytes of this character,
i.e., every time a byte is transferred from the Receiver
Register to the Receiver Holding Register (see Figure 3,
Data Accepted). The CPU should read the data prior to
the reception of the next character (next RXRDY) or an
overrun error will be generated as the receiver will overwrite the old data with the new data character just
received.
b) The TXE and TXRDY flags are "1" (active).
c) The external CTS signal = "0".
d) The CPU loads data into the Transmitter Holding Register, TXE and TXRDY go Low.
e) When the Transmitter Holding Register has transferred
its contents to the Transmitter Register for the character
to be transmitted, it will activate the TXRDY (pin 9) output, to alert the CPU that the next 8-bit character can be
accepted. When this new character is loaded into the
Transmitter Holding Register (while the Transmitter Register is still transmitting its contents, thereby preventing
the Transmitter Holding Register to transfer its character
contiguously), TXRDY is not deactivated (reset low to a
logic zero) when WRITE ENABLE (WE) is deactivated
(set high to a logic one), as shown by the dotted line in
Figure 2. An underrun error will be generated if the next
character is not loaded before the previous word is completely shifted out, unless the current character is the
last character in a sequence.
The first character in the Arinc protocol contains a label.
The FCR and RXRDY Flags become active to indicate
the reception of the first character of data. The CPU
reads the first character and decides whether or not it
wants to acquire the subsequent characters. If not, then
the CPU performs a "control write" to the Command
Register, setting the RXRDYIN (CR3) billo a "1." This bit
in Arinc mode should inhibit the RXRDY flag from interrupting the CPU during the reception of the 3 remaining
characters. The RXRDYIN bit is then automatically reset
upon completion of the receive sequence and RXRDY is
enabled again (see Figure 3, Conforming Data Rejection).
However, the WD1993 will delay the deactivation of
TXRDY until the end of the fourth clock or the end of a
data bit being transmitted (see Figure 2).
f) If the last character is transmitted and no more new'
data is to be sent, the transmitter will indicate its status
by raiSing the TXE flag. (No error is generated as a result of this condition.)
I
FOUR CLOCKS
, I
I
CLOCK
I
I
I
DATA
X
L
TXRDY
WE
:>K
ONE DATA BIT
~
I I
u
FIGURE 2
255
I
EXPECTED TXRDY RESET
:
______ IL____
=E
o......
CO
CO
(0)
i
I
The WD1993 however generates a RXRDY after the null
character (see Note), thereby conceivably misleading
the CPU that a first 8 bit character (label) of the following
32 bit ARINC 429 character, has been assembled in the
Receiver Register and transferred to the Receiver Holding Register, ready to be read (see Figure 3, "WD1993
Data Rejection").
For basic testing, failing to reload the Transmit Holding Register in the middle of a data send sequence will cause an underrun error in the transmitter and a word error in the receiver. Failure to read the Receive Holding Register after a
FCR or RXRDY flag will cause an overrun error to be
generated.
A solution to overcome this misreading, is to gate (AND)
the FCR and RXRDY outputs to interpret this combination as a valid RXRDY for the Label.
For Loop-Back test operations, the user should be sure that
the TXC and RXC clock frequencies are the same. This is
normally implemented by placing the same clock signal on
both pins (TXC and RXC).
NOTE: A NULL character is the four bit (all zero's) character
ARINC BACKGROUND
which is used in the ARINC 429 protocol to synchronize, differentiate and signify the start of the 32 bit
ARINC 429 characters.
Aeronautical Radio Inc. (ARINC) publishes the ARINC 429
specification. This document defines the air transport industries standards for the transfer of digital data between avionics systems elements. This specification was adopted by The
Airlines Electronic Engineering Committee April 11, 1978. By
the adoption of this specification the foundation is set for a
standard protocol governing all intersystems equipment (Line
Replaceable Units).
LOOP TEST MODE
As mentioned, the WD1993 is equipped with a diagnostic
test mode, local loop-back. This mode is activated by setting
the LTE command bit to a "1". The TEN and REN bits should
be "1" and CTS should be "VIL". The receiver inputs are ignored and the transmitter outputs are sending nulls. The
transmitter is internally "looped-back" to the receiver and the
error and status flags operate normally.
MARK 33 DIGITAL INFORMATION TRANSFER
SYSTEM (DITS)
Basic Philosophy
Transmit from a designated output port over a single
twisted and shielded pair of wires to designated receiver.
DATA
I..
I
I
1
ARINC 429----1..32 BIT CHARACTER
I
I
FCR
n
I
~
1
I
I
I
n
I
' - 2ND ARINC 429 CHARACTER
I
I
RXRDY
I
I
I
1
I
I
.1
1
1
I
h
DATA ACCEPTED
I
h
I
n
~
I
I
I
I
1
RXRDY
1
h
L-
I
1
1
I
I
I
I
RXRDY
CONFORMING
DATA REJECTION
n
h
FIGURE 3
256
I
WD1933
DATA REJECTION
~
Bidirectional data flow not permitted on a given pair.
Receiver Voltage Levels:
(noisy
(in absence
of noise)
environment)
high + 6.0V to + 10V
+S.OV to + 13V
-S.OV to -13V
low
-6.0V to +10V
No damage to receiver up to 20 vac rms between A &
B; +28, A to Gnd; -28, B to Gnd.
Data Transfer
Numeric
Iso Alphabet # S
Graphic
Data Format
32 bits or less (unused bit positions should be filled with
binary zeros or valid data pad bits).
Data Rate
100 kilo bit per second ± 1%
Low speed 12 to 14.S kilo bit per second ± 1%
Word Synchronization
All zero gap of a minimum of 4 bit times
Bit #32 is assigned to parity.
Modulation
Return to Zero (RZ)
Transmit Voltage Levels
high
+ 10
null
0
low
-10
±O.SV
±O.SV
±O.SV
REGISTER DEFINITIONS
The format and definition of the Command Register is shown below:
TEN
0
NA
REN
0
RXRDYIN
CR7
CR6
CRS
CR4
CR3
CR2
NA
IR
NA
LTE
RXRDYIN
REN
Transmit ENable
LTE
Enabled
Disabled
1
0
TEN
Loop Test ENable
Local loop-back mode
Normal Operation
Not Used
NA
Not Used
Receive ENable
IR
Internal Reset
0
Returns WD1993 to mode instruction
format
Stays in Command Register
Enabled
Disabled
-----
RXRDY Inhibit
NA
Inhibit RXRDY output flag
0
NA
Normal transmitter ooeration
enable RXRDY output flag
257
Not Used
The WD1993 registers are addressed according to the following table:
~
C
.....
CO
CO
W
CS
C/O
Re
WE
L
L
L
L
L
L
L
H
H
H
X
H
H
L
L
H
H
X
X
Registers Selected
Read Receive Holding Register
Write Transmit Holding Register
Read Status Register
Write Command Register
Data Bus Tri-Stated
L
L = Vllat pins
H = VIH at pins
X = don't care
The format of the Status Register is shown below:
SR?
SR6
SRS
SR4
SR3
SR2
UE
FCR
WEF
OE
PE
TXE
TXRDY
1
0
illillQY.
1
0
Receiver Ready
Active (RHR should be read)
Inactive
Transmitter Empty
Transmitter idle
Transmitter active
1
0
OE
0
FE
Parity Error
Parity Error reported
No error
Overrun Error
RHR has been written over with a new character before
previous character was read.
No error
Framing Error
1
Indicates improper receive sequence detected.
0
No error
FCR
TXRDY
Active (THR can be reloaded)
Inactive (transmitter is busy)
1
PE
RXRDY
SRO
Transmitter Ready
TXE
0
SR1
First Character Ready
This bit indicates the receiver has just completed assembly of the 1st character
in a multi-character sequence and that the data is contained in the RHA.
0
UE
0
First character not ready.
Underrun Error
Indicates that the THR has not been loaded with a new character in time for a
contiguous data transmission sequence.
No error
258
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
- 55°C to + 125°C (Plastic Package)
- 65°C to + 150°C (Ceramic Package)
Voltage on any Pin with Respect to Ground . - 0.3V to + 7V
Power Dissipation .......................... 400 MW
Lead Temperature (soldering 10 sec) ............. 300°C
Note:
Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous
operation at these limits is not intended and should
be limited to those conditions specified under DC
Electrical Characteristics.
DC ELECTRICAL CHARACTERISTICS
T A = O°C to + 70°C; VCC = 5.0V ± 5%; GND
SYMBOL
OV
PARAMETER
MIN
VIL
Input Low Voltage
-0.3
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
IDL
IlL
ICC
MAX
TYP
Input Leakage
45
Power Supply Current
TEST CONDITIONS
0.8
V
VCC
0.45
V
10L
V
10H
2.4
Data Bus Leakage
UNIT
V
50
uA
10
uA
10
uA
80
rnA
= 1.6mA
= -1001LA
Data Bus is in
High Impedence
State
VIN = VCC
Vee = 5.2SV
No Load
CAPACITANCE
TA
= 25°C; Vee = GND = 0V
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
TEST CONDITIONS
CIN
Input Capacitance
10
pF
IC
CliO
1/0 Capacitance
20
pF
Unmeasured pins
returned to GND
+20
Iii
.s
+10
w
0
/
>«
-J
0
I:::l
a.
I:::l
0
-10
------..........--!f--+----IV'V\.-~~v-."'"-...
12
15K
RXOl
3
~
)
·5V
LM3l90
OR EQUIV
100K
5001!
15K
100K
AXOO
LOW
LF356
OR EQUIV
330K
1 "'
4.7
1M
2QOK
12V
01
"'
Note
FIGURE 15.
ARINC 429 LINE LEVEL TRANSLATOR (RECEIVER)
·12V
.~
4.7K
01 04 - IN400 1
All caps: 35V
lOOK
50K
4.7K
100K
511!
HIGH
TXD1
'\
lOOK
lHOO02C
OR EQUIV
OR EQUIV
lOOK
5111
LOW
TXOO
100K
-l2V
FIGURE 16.
ARINC 429-1 LINE DRIVER
265
See page 383 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
266
Printed
In
U.S.A
WESTERN DIGITAL
o
c
p
R
o
R
A
T
o
I
N
WD2001/02 Data Encryption Devices
FEATURES
• CERTIFIED
DARDS_
NC
BY
NATIONAL
BUREAU
OF
KA
STAN-
• TRANSFER RATE:
WD2001/2-Q5 300Kbs with 500KHz clock
WD2001/2-20 1.3 Mbs with 2MHz clock
WD2001/2-30 1.8 Mbs with 3MHz clock
( +5)VCC
(+12)VDD
WE
• ENCRYPTS/DECRYPTS 64 BIT DATA WORDS USING
56 BIT KEY WORD
Cs
DAL1
DAL3
DAL5
DAL?
• PARITY CHECK ON KEY WORD LOADING
• STANDARD 8 BIT MICROPROCESSOR INTERFACE
• INPUTS AND OUTPUTS TIL COMPATIBLE
ON
CHIP
IS
NOT
MR
WD
2002
COP?
CDP5
CDP3
CDP1
CLK
• COMMAND BIT PROGRAMMING VIA DAL BUS OR
INPUT PINS
EID
ACT
KPE
8
9
FiE
• SINGLE PORT 28 PIN PACKAGE WD2001 OR DUAL
PORT 40 PIN PACKAGE WD2002
• KEY STORED
ACCESSIBLE
KR
KEOE
VSS(GND)
NC
DIA
DOA
NC
EXTERNALLY
PIN DESIGNATION
SEPARATE CLEAR AND CIPHER BUS STRUCTURE
ON WD2002
DOR
DIR
KR
VSS(GND)
NC
KA
DIA
APPLICATIONS
DOA
( +5)VCC
(+12)VDD
WE
• SECURE BROKERAGE TRANSACTIONS
ELECTRONIC FUNDS TRANSFERS
E/D
7
ACT
KPE
MR
• SECURE BANKING/BUSINESS ACCOUNTING
CRPS
AD
DAL6
DAL4
DAL2
DALD
CLK
Cs
• MAINFRAME COMMUNICATIONS
• REMOTE AND HOST
COMMUNICATIONS
CRPS
CDPD
CDP2
CDP4
CDP6
AD
DPS
DAL6
DAL4
DAL2
DALD
DAL1
DAL3
DAL5
DAL?
COMPUTER
• SECURE AID
• SECURE DISK OR MAG TAPE DATA STORAGE
PIN DESIGNATION
• SECURE PACKET SWITCHING TRANSMISSION
DESCRIPTION
the cipher text word is decrypted to produce the
original clear text word.
The WD2001/02 are fabricated in N-channel silicon gate
MOS technology and are TTL compatible on all inputs and
outputs.
The Western Digital WD2001 and WD2002 Data
Encryption / Decryption devices are designed to encrypt
and decrypt 64-bit blocks of data using the algorithm
specified in the Federal Information Processing Data
Encryption Standard (#46). These devices encrypt a
64-Bit clear text word using a 56-Bit user-specified key
to produce a 64-Bit cipher text word. When reversed,
NOTE: This device can not be shipped outside of the United
States of America without authorization from the
State Department and Department of Defense.
267
PIN DESCRIPTION
WD2001 WD 2002
SIGNAL NAME
MNEMONIC
FUNCTION
11-18
17-24
DATA LINES
DALO...
DAL 7
Eight active true three-state bi-directional I/O lines
used for information transfer to and from the DES
chip's registers. During Single port operation, all
COMMAND/STATUS, KEY WORD and DATA WORD
transfers are via this bus. During dual port operation,
all COMMAND/STATUS, KEY WORD and clear DATA
WORD transfers are via this bus. (Cipher DATA WORD
transfers are via the CIPHER DATA PORT (COP) bus.)t
N/A*
11-14
27-30
CIPHER DATA PORT
CDPO...
COP 7
Eight active true three-state bi-directional I/O lines
used ~ in dual port operation. Cipher DATA WORD
transfers are via this bus. These pins are available on
the WD2002 40 pin package version only.t
8
POWER SUPPLY
VDD
7
POWER SUPPLY
VCC
+ 12v
+ 5v
25
36
GROUND
9
15
CLOCK
VSS
CLK
System clock input.
21
32
MASTER RESET
MR
10
16
CHIP SELECT
CS is made low to access registers within the device.
8
10
READ ENABLE
The contents of the selected register are placed on the
DAL (or COP) bus lines when CS and RE are made low.
7
9
WRITE ENABLE
Information on the DAL (or COP) bus lines is written
into the selected DES register when CS and WE are
made low.
19
26
AO
AO
When this input is active high (during CS active) the
COMMAND/STATUS REGISTER is addressed. (AO
active high will override internally generated addressing of the KEY and DATA REGISTERS as described
on page 6.) This input is ignored when CRPS is active.
26
38
KEY REQUEST
KR
This output is active high when the DES chip is
requesting that a byte of the KEY WORD be written into
the KEY REGISTER. (The KEY REGISTER is automatically addressed when KR is active, unless
overriden by AO.)
2
2
KEY ACKNOWLEDGE KA
This output is active low when WE is made low while
the KEY REGISTER is addressed. (Can be used for
handshake.)
27
39
DATA-IN REQUEST
DIR
This output is active high when the DES chip is
requesting that a byte of the DATA WORD be written
into the DATA REGISTER. (The DATA REGISTER is
automatically addressed when DIR is active, unless
overriden by AO.)
3
4
DATA-IN
DIA
This output is active low when WE is made low while
the DATA REGISTER is addressed. (Can be used for
handshake.)
This output is active high when the DES chip is
requesting that a byte of the DATA WORD be read from
the DATA REGISTER. (The DATA REGISTER is
automatically addressed when the DOR is active, unless
overridden by AO.)
6
5
ACKNOWLEDGE
28
40
DATA·OUT REQUEST
DOR
GROUND
MR active low resets the COMMAND/STATUS
REGISTER and resets internal circuitry. (Requires
active clock for reset operation.)
268
PIN DESCRIPTION (Continued)
WD2001
SIGNAL NAME
WD2002
4
5
22
33
DATA·OUT
ACKNOWLEDGE
KEY PARITY ERROR
31 * * . COMMAND REGISTER
PIN SELECT
23
34
ACTIVATE
ACT
37
KEY ERROR
OUTPUT ENABLE
KEOE
35
ENCRYPTIDECRYPT
EID
25 * *
DUAL PORT SELECT
N/A*
24
N/A*
This output is active low when RE is made low while the
DATA REGISTER is addressed. (Can be used for hand·
shake.)
This output is active low when enabled via the COM·
MAND/STATUS REGISTER BIT 2 (KEOE) and a parity error
has been detected during loading of the KEY REGISTER.
This input selects DAL bus or input pin programming of
the COMMAND/STATUS REGISTER. CRPS high or open
selects DAL bus programming. CRPS low selects input
pin programming.
When CRPS is high or open, this pin is an output
reflecting the status of the ACTIVATE bit (bit 1) of the
COMMAND/STATUS REGISTER. When CRPS is low, this
pin is an input that overrides the ACTIVATE bit of the
COMMAND/STATUS REGISTER.
This output indicates the status of the KEY ERROR
OUTPUT ENABLE bit (bit 2) of the COMMAND/STATUS
REGISTER. This output is active when input pin
programming is selected (CRPS low). This pin is available
on the WD2002 40 pin package version Q!!!y
When CRPS is high or open, this pin is an output
reflecting the status of the ENCRYPTIDECRYPT bit (bit 3)
of the COMMAND/STATUS REGISTER. When CRPS is
low, this pin is an input pin that overrides the EN·
CRYPTIDECRYPT bit of the COMMAND/STATUS
REGISTER.
When this input is high or open, single port operation is
selected and ali DES chip transfers are via the DAL bus.
When DPS is low, dual port operation is selected and both
the DAL bus and the CDP bus are used [separate busses
for clear data (DAL bus) and cipher data (CDP bus»). This
pin is available on the WD2002 40 pin package version
only.
DOA
20* *
=e
FUNCTION
MNEMONIC
c
~
o......
-
NOTE: * The WD2001 28 pin package version does not have the following pins: The 8 CDP pins, the KEOE pin, and the DPS pin.
* * These inputs have internal pull·up resistors.
t L.S.B. (DATA BIT 0) at DAL7 and CDP7. M.S.B. (DATA BIT 7) at DALO and CDPO.
ttlttttt
t t t
COP BUS'
,--_ _ _ _ _ _ _ _..L-_ _ _ _ _ _ _ _ _ _ _ _ _- , _(+121 Voo
_ ( + 5IV CC
...---,r-.-...,...---,r-.-...,..........,-,-,....~-,__.,.._r-,__.____,_r_r elK
MR
CS
WE
RE
A0
KPE
KR
KA
D1R
OIA
DDR
DOA ACT
E/O CRPS KEOE DPS
"NOT AVAILABLE ON WD2DOl
WD2001/WD2002 BLOCK DIAGRAM
269
(GNDI Vss
o
I\)
:ec
I\)
o
o
......
o
I\)
ORGANIZATION
The Data Encryption Standard chip consists of a 56-bit KEY
REGISTER, a 64-bit DATA REGISTER, an 8-bit COM·
MAND/STATUS REGISTER, plus the necessary logic to
check KEY parity and implement the NBS algorithm. A
typical system implementation is shown on page 10 and
the block diagram is shown on page 1. Although the DES
chip interfaces to a wide variety of processors including
mini·computers, the interface is tailored to the 8080A class
microprocessor.
...
BIT
55
BIT
0
KEY REGISTER
(LOAD ONLy)
Data Register
GENERAL OPERATING DESCRIPTION
This 64·bit register contains plain or cipher text. When in
the encrypt mode, the DATA REGISTER is loaded with plain
text, and when read contains cipher text. When in the
decrypt mode, the DATA REGISTER is loaded with cipher
text, and when read contains plain text. The DATA
REGISTER is always read or loaded with eight successive
byte transfers. The DATA REGISTER can be loaded only
when there is a DATA·IN REQUEST (status bit and output);
similarly the DATA REGISTER can be read only when there
is a DATA·OUT REQUEST (status bit and output).
The user programs the DES chip for encryption or
decryption, and single or dual port operation.' Data is
encrypted/decrypted with a 64-bit user defined KEY WORD.
Data encrypted with a given KEY WORD can be decrypted
only using that KEY WORD. The KEY REGISTER is loaded
by the computer with eight successive 8-bit bytes. Parity is
checked on each byte of the KEY WORD as it is loaded into
the KEY REGISTER (The 8th bit (DALO) of each 8-bit byte is
reserved for odd parity for that byte and is not used in the
algorithm calculation.) Similarly the DATA REGISTER is
loaded with eight successive 8·bit bytes. The DATA
REGISTER is read by reading eight successive 8-bit bytes.
When the DES chip is programmed for encryption, the
DATA REGISTER is loaded with eight bytes of plain or clear
text. The DES chip encrypts the data, then the encrypted
data may be read from the DATA REGISTER (64·bits of
encrypted text). When the DES chip· is programmed for
decryption, the DATA REGISTER is loaded with eight bytes
of encrypted or ciphertext. The DES chip decrypts the data,
then the plain text may be read from the DATA REGISTER
(64-bits of plain text). Note that all transfers to and from the
KEY REGISTER and/or DATA REGISTER must occur in
eight successive 8-bit bytes.
.•.
BIT
63
BIT
0
DATA REGISTER
Command/Status Register (C/S R)
"Note: Dual port operation available with WD2002 40 pin
package version only. (Single and dual port
operation is described in detail under PART V.
OPERATION.)
This 8-bit register controls the operation of the DES
chip and monitors its status. Bits 7, 6, 5 and 4 are
status·only bits (read only). Bits 3, 2 and 1 are
COMMAND/STATUS bits (read/write). Bit 0 is not
used. The COMMAND/STATUS bits (bits 3, 2, and 1)
are normally loaded only once for an entire encrypt or
decrypt process.
REGISTER DESCRIPTION
The following describes the KEY, DATA, and COM·
MAND/STATUS REGISTERS of the DES Chip.
Key Register
This 56-bit register contains the KEY by which the Data
Encryption Algorithm operates. Eight successive bytes are
needed to load the KEY REGISTER. The KEY REGISTER
can be loaded only when there is a KEY REQUEST (Status
bit and output). THIS REGISTER IS LOAD ONLY AND
CANNOT BE READ.
7
6
5
DOR
DIR
KPE
STATUS BITS
(READ ONLy)
4
KR
3
EtD
2
KEOE
1
ACT
COMMAND STATUS
BITS[ READ]
WRITE
COMMAND/STATUS REGISTER
270
0
N/U
COMMAND/STATUS REGISTER (C/S R)
Bit
Name
C/SRO
NOT USED
CIS R1
ACTIVATE
C/SR2
KEY ERROR OUTPUT ENABLE
(KEOE)
Function
~
C
N
This bit must be set from '0' to '1' to initiate loading the KEY
REGISTER. This bit must be '1' for encrypt/decrypt operation. This is
a read I write bit.
When '0', the KEY PARITY ERROR output pin (KPE) remains inactive
regardless of the status of the KEY PARITY ERROR bit (bit 5). When
'1', the KEY PARITY ERROR output pin is active when the KPE bit
(bit5) is '1'. This bit is set to '1' upon a MASTER RESET. This is a
read I write bit.
C/SR3
ENCRYPT/DECRYPT (E/ D)
When '0' data is to be encrypted. When '1' data is to be decrypted.
This is a read/write bit.
CIS R4
KEY REQUEST (KR)
This bit is set one clock period after the ACTIVATE bit is set (from
'0' to '1 '). It is reset upon loading of the 8th and final byte of the KEY
REGISTER. This is a read only bit.
C/SR5
KEY PARITY ERROR (KPE)
This bit is set internally upon detection of a parity error during
loading of the KEY REGISTER. It is reset when the ACTIVATE bit is
programmed from '1' to '0' (I.e., chip is deactivated). This is a read
only bit.
C/SR6
DATA-IN REQUEST (DIR)
This bit is set upon either:
a) Completion of KEY REGISTER loading - or b) Completion of DATA REGISTER reading, (ie, the last DATA-OUT
REQUEST has been serviced by an 8-byte read and the DATA
REGISTER is now empty and ready to be loaded with the next
DATA WORD).
It is reset upon loading of the 8th and final byte of the DATA
REGISTER. This is a read only bit.
CIS R7
DATA-OUT REQUEST (DOR)
This bit is set upon completion of the internal encrypt/decrypt
calculation of a DATA WORD. It is reset upon reading of the 8th and
final byte of the DATA REGISTER. This is a read only bit.
Note: All bits of the COMMAND/STATUS REGISTER are reset to '0' upon MASTER RESET, except bit 2 (KEOE)
which is set to '1' and bit 0 (not used) which will read '1' by default during a COMMAND/STATUS REGISTER
read.
271
o
o
......
o
N
::e
o
!\)
8
:::.
C
!\)
DETAILED OPERATING DESCRIPTION
The DES chip is initiated by programming a '1' in the
ACTIVATE bit of the COMMAND/STATUS REGISTER.
The DES chip will respond by activating the KEY
REQUEST (KR) bit (bit 4) of the STATUS REGISTER
and the KEY REQUEST output.
Again, for both data-in and data-out, further
activations of the DIR, DOR and DIA, DOA outputs,
after the first request, can be ignored and the DATA
REGISTER loaded (read) by 8 successive activations
of WE (RE).
After the last (8th) byte of the DATA REGISTER has
been read, the DES chip will reactivate the DATA-IN
RECUEST. This cycle of loading the DATA REGISTER,
internal algorithm calculation, and reading the new
data from the DATA REGISTER can continue indefinitely until all desired data has been encrypted or
decrypted with the current KEY WORD.
The user must deactivate AO (allowing the chip to
internally address the KEY REGISTER), and load the
KEY REGISTER with the 64-bit KEY WORD. The KEY
REGISTER is loaded with 8 consecutive 8-bit bytes by
activating WE 8 times (with CS active).
When WE is made active, the DES chip deactivates the
KR output. When WE is deactivated, the KR output is
again activated. The DES chip will activate 8 KEY
REQUESTs in this fashion until the KEY REGISTER is
full.
Also, when WE is made active, the DES chip responds
by activating the KEY ACKNOWLEDGE (KA) output.
Thus, 8 KA activations will be made.
After all desired data has been encrypted I decrypted
with the current KEY WORD, the ACTIVATE bit of the
COMMAND/STATUS REGISTER should be programmed to '0'. When the ACTIVATE bit has been reset to
'0', an unauthorized user will not have access to the
last KEY loaded into the DES chip since to resume
operation, the ACTIVATE bit must be programmed to
'1' which activates KEY REQUEST and a new KEY must
be loaded before access to the DATA REGISTER is
possible.
The KR and KA outputs can be used for asynchronous
handshaking (as in DMA control) or further activations
following the first KR can be ignored and the KEY
REGISTER can be loaded in a synchronous (programmed I/O) manner via 8 successive activations of
WE.
To encrypt plain data, plain data is loaded into the
DATA REGISTER, and encrypted data is read from the
DATA REGISTER. (The ENCRYPT/DECRYPT bit (bit 3
of the COMMAND/STATUS REGISTER) must have
been previously programmed to '0'.)
To decrypt encrypted data, encrypted data is loaded
into the DATA REGISTER, and plain data is read from
the DATA REGISTER. (The ENCRYPT/DECRYPT bit
must have been previously programmed to '1'.)
Each byte of the KEY WORD is checked for odd parity
as it is loaded. If a parity error is found, the chip will
set the KEY PARITY ERROR (KPE) bit (bit 5) of the
COMMAND/STATUS REGISTER. If the KEY ERROR
OUTPUT ENABLE bit (bit 2) of the COMMAND/
STATUS REGISTER has been set, the DES chip will
also activiate the KPE output. The KPE bit will be reset
when the ACTIVATE bit is re-programmed to a '0'.
Note: If it is desired to switch from encrypt to decrypt
(or vice versa) under the same KEY WORD, this
can be accomplished before a DATA WORD
transfer is initiated. By making AO high, the
DES chip will override the internal addressing of
the DATA REGISTER, and address the COMMAND/STATUS REGISTER. The COMMAND/
STATUS REGISTER can be re-programmed.
When AO is returned to a low state, the
DES chip will internally address the DATA
REGISTER awaiting loading of the next DATA
WORD.
After loading the last (8th) byte of the KEY WORD into
the KEY REGISTER, the DES chip will set the DATA-IN
REQUEST bit (bit 6) of the STATUS REGISTER and
activate the DATA-IN REQUEST (DIR) output. The
64-bit DATA WORD must then be loaded into the DATA
REGISTER. The DATA REGISTER is loaded in the same
manner as the KEY REGISTER via 8 successive
activations of DATA-IN REQUEST (DES output), WE
(DES input, and DATA-IN ACKNOWLEDGE (DES
output).
DUAL PORT OPTION
(Available on WD2002 40 Pin Version Only)
When the DUAL PORT SELECT (DPS) input is high or
left open (ie., single port operation is selected), all
transfers to/from the DES chip are via the DAL bus.
The CDP bus is not used and remains three-stated.
After the last (8th) byte of the DATA WORD has been
loaded, the chip begins the internal calculation of the
NBS algorithm. Upon completion of the calculation,
the new data is internally loaded into the DATA
REGISTER, and the DES chip sets the DATA-OUT
REQUEST bit (bit 7) of the STATUS REGISTER and
activates the DATA-OUT REQUEST (DOR) output. The
DATA WORD must then be read from the DATA
REGISTER. The DATA REGISTER is read in the same
manner as it was loaded via 8 successive activations of
DATA-OUT REQUEST (DES output), RE (DES input),
and DATA-OUT ACKNOWLEDGE (DES output).
When DPS is made low (ie., dual port operation is
selected), all transfers to/from the COMMAND/
STATUS REGISTER, and transfers to the KEY
REGISTER are still via the DAL bus. Clear DATA
WORDS are also transferred via the DAt bus. However,
cipher DATA WORDS are now transferred via the CDP
bus. This provides separate busses for clear and
ciphered text.
272
Encryption during dual port operation requires loading
clear data via the DAL bus, and reading cipher data via
the CDP bus.
=e
c
I\)
Decryption during dual port operation requires loading
cipher data via the CDP bus, and reading clear data via
the DAL bus.
o
o
.....
(:)
COMMAND SELECT OPTION
I\)
When the COMMAND REGISTER PIN SELECT(CRPS)
input is made low, the ACT and E/ D pins are
enabled as inputs. These inputs override bits 1 and 3
(respectively) of the COMMAND/STATUS REGISTER.
This allows input pin control of the DES chip. The
KEOE bit (bit 2) of the COMMAND/STATUS REGISTER
will be held to '1'.
Input AO will be disregarded in this mode of operation,
and the COMMAND/STATUS REGISTER cannot be
accessed via the DAL lines.
Note that the ACT pin must be toggled from '1' to a '0'
to clear a parity error detection in this mode of
operation.
All other operation remains as described previously.
WD2001/WD2002 FLOW CHARTS
273
MAXIMUM RATINGS
=e
c
I\)
o
o
.....
(3
I\)
VDD with Respect to VSS (Ground)
+ 15 to - 0.3V
Max. Voltage to any Input with Respect to VSS + 15 to - 0.3V
Operating Temperature
O·C to 70·C
Power Dissipation
1W
OPERATING CHARACTERISTICS
TA = 0·Ct070·C, VDD = +12.0V
SYMBOL
±
.6V, VCC = + 5.0V
CHARACTERISTIC
±
Storage Temp. Ceramic -65·C to + 150·C
Plastic -55·C to + 125·C
.25V, VSS = OV
MAX.
UNITS
10
1.6
uA
rnA
VIN = VDD
Input Current Low
ILO
Output Leakage
10
uA
VOUT = VCC
ICCAVE
VCC Supply Current
100
rnA
IDDAVE
VIH
VDD Supply Current
25
rnA
VIL
Input Low Voltage (All Inputs)
VOH
Output High Voltage
VOL
Output Low Voltage
* III
* *IIL
MIN.
TYP.
Input Leakage
68
17
Input High Voltage
2.4
CONDITIONS
VIN = VSS
V
.8
2.8
.4
V
V
10 = -100uA
V
10 = 1.6 rnA
* III applies only to inputs without pull-up resistors.
* * IlL applies only to inputs with pull-up resistors.
2001/2002·05 500KHz CLOCK
AC CHARACTERISTICS
TA = O·C to 70·C, VDD = + 12.0V ± 0.6V, VSS = OV, VCC = + 5.0 ± .25V
CHARACTERISTIC
SYMBOL
MIN.
TYP.
MAX.
UNITS
CONDITIONS
READ
TACS
AD, CS Set up to REI
TRDV
RE +to DAL (CDP) Valid
TRD
RE Pulse Width
TDF
RE t to DAL Float
TACH
AD, CS Hold From RE t
100
ns
500
500
ns
CLOAD
= 50PF
CLOAD
= 50PF
ns
50
250
ns
0
ns
WRITE
CS Set up to WE +
TACS
AD,
100
ns
TDVW
DAL (CDP) Set up to WE t
300
ns
TWR
WE Pulse Width
300
ns
TOH
DAL (CDP) Hold From WE t
90
ns
TACH
AD, CS Hold From WE t
0
HAND·
SHAKE
TO
KR (DIR) +, KA (DIA) +From WE +
KR (DIR) t, KA (DIA) t From WE t
DOR +, DOA +From RE +
DOR t, DOA t From RE t
450
NOTE: All output timing specifications reflect the following: High Output 2.0V
Low Output 0.8V
274
700
ns
200112002·20 2MHz CLOCK
AC CHARACTERISTICS
TA = o·e to 70·e, Voo = + 12.0V ± 0.6V, Vss = OV, Vee = + 5.0 ± .25V
I
SYMBOL
CHARACTERISTIC
MIN.
TYP.
MAX.
UNITS
CONDITIONS
TACS
AO. CS Set up to REI
TRDV
FiE I to DAL (COP) Valid
TRD
Ai: Pulse Width
TDF
Ai: t to DAL Floet
TACH
N:i.
ns
80
330
330
CLOAD
= 50PF
CLOAD
= 50PF
ns
200
30
CS Hold From Ai: t
ns
ns
0
ns
WRITE
TACS
AO, CS Set up to WE I
80
ns
TDVW
DAL (COP) Set up to WE t
200
ns
TWR
WE Pulse Width
200
ns
TDH
DAL (COP) Hold From WE t
90
ns
TACH
AO,
CS Hold From WE t
0
HANDSHAKE
TO
KR (DIR) I, KA (DIAl I From WE I
KR (DIR) t, KA (DIAl t From WE t
DOR I, ImA I From Ai: I
DORt, DOAt From Ai:t
300
450
ns
..
NOTE: All output tIming specIfIcatIons reflect the follOWIng: HIgh Output 2.0V
Low Output O.BV
200112002·30 3MHz CLOCK
AC CHARACTERISTICS
TA o·e to 70·e, VOO = + 12.0V ± 0.6V, Vss = OV, Vee
=
SYMBOL
CHARACTERISTIC
MIN.
= + 5.0 ± .25V
TYP.
MAX.
UNITS
CONDITIONS
READ
TRD
AO, CS Set up to REI
FiE I to DAL (COP) Valid
FiE Pulse Width
TOF
RE t to DAL Floet
TACH
AO,
TACS
TADV
ns
50
220
130
20
c5S Hold From FiE t
ns
CLOAD
=50PF
CLOAD
=50PF
ns
300
ns
0
ns
WRITE
TACS
AO, CS Set up to WE I
50
ns
TDVW
DAL(CDP) Set up to WE t
130
ns
TWR
WE Pulse Width
175
ns
TDH
DAL(CDP) Hold From WE t
60
ns
TACH
.AO, CS Hold From WE t
0
HANDSHAKE
TO
~
I
READ
KR (DIR) I, ~ (DIAl I From WE I
KR (DIR) t, KA (DIAl t From WE t
DOR I, OOA I From RE I
DOR t, DOA t From RE t
150
..
NOTE: All output tlmmg speCIfIcatIons reflect the following: High Output 2.0V
Low Output O.BV
275
300
ns
~
C
N
o
o
.....
o
KR(DIR)
OS
N
DAL(CD~------)L~~J:~t=ttl::xt:~==:x==:!==:x==~==tx==~==:X==:J==~==b[~-----KA(DIA)
TYPICAL KEY OR DATA REGISTER LOAD
5
8
7
6
DOR
CS
DAL(CD~
----1(,"-'-----'-",,-."------'--'
fie
""
II
TYPICAL DATA REGISTER READ & TIMING
----G~:--------~-~b---
~~;------------------~b----
r-
---i
----~i~,
TACS - :
DAL
(CD~
i
--+:
I
I
r--ri--~
b--= TRD_I
~
DAL
,_TACH
(CD~
!~
:..- -... i 1.--f
I
-.! ~CH
ib---
-----j
WE
I
I
i
:
q
:_ TDVW-':
TWR
TA-C-S----!i~......,I-
WRITE TIMING
276
I
: _ TDH
-I .
TOF
READ TIMING
I
9. The initial DaR activation will be valid within 49
ClK • + 450 nsec from WE t of the Bth write into
the DATA REGISTER.
10. When reading the DATA REGISTER (in response to
DaR), subsequent data bytes are made available
internally to the DAl (CDP) output buffers within 2
ClK. + 450 nsec from RE t
11. After reading the DATA REGISTER in response to DORs,
DIR will be activated and valid within 2 ClK. + 450 nsec.
from RE t of the Bth read from the DATA REGISTER.
MISCELLANEOUS TIMING
1.
CLOCK INPUT
FREQUENCY
MIN.
MAX.
PULSE WIDTH
MIN
500KHz
100KHz
500nsec
2 MHz
100KHz
250nsec
3 MHz
100KHz
165nsec
NOTE: All output timings assume ClOAD
2. MASTER RESET PULSE WIDTH: 10 Clock Periods
3. Time between consecutive RE or WE pulses:
TSR
TSW
2 CLOCK PERIODS MINIMUM
4. ACT, EID, KEOE OUTPUTS
These pins will be valid within 2 ClK. + 450 nsec
from WE t of a COMMAND REGISTER write
operation.
5. KPE OUTPUT
This pin will be active within 2 ClK • + 450 nsec
from WE t of a write of a KEY WORD byte that
results in a parity error.
6. CRPS, DPS, EID INPUTS require a 300 ns set-up
time.
7. The initial KR activation will be valid within 3 ClK
• + 450 nsec from WE t of a write operation that
programs a '1' into the COMMAND REGISTER
ACTIVATE bit (or 2 ClK • + 450 nsec from ACT
input t, if CRPS = 0).
B. The initial DIR activation will be valid within 2 ClK
• + 450 nsec from WE t of the Bth write into the
KEY REGISTER.
=
=
Shown below is a block diagram for a floppy disk
based DES secure smart terminal. The Direct Memory
Access (DMA) controller optimizes data transfer
operations for not only the floppy but also for file
encryption and decryption operations. Secure features
for the terminal include: secure file storage on floppy
disks, optical clearlsecure transmission via the communications 1/0 and battery backup of the Terminal ID
key.
Tampering with the Terminal by unauthorized persons either
through the key board, power supply, interrupt interlock, or
attempting to open the service panel results in memory
scrambling and terminal ID key destruction. Finally, a hardware option was also included to allow the use of the UC1671
or the WD1935 for bit oriented SDlC, HDlC, or ADCCP protocols.
WD2001
DES
cpu
DMA
PWR SUPPLY &.J
BATTERY
CRT
CONTROLLER
t------.
f----+
PF
TYPICAL APPLICATION
MEMORY
SYSTEM
CLOCK
= 50
FLOPPY DISK
CONTROLLER
UC1671
SYNC/ASYNC I/O
WD1935
SDLC/HDLC/ADCCP
KEY BOARD
Block Diagram: Secure Smart Terminal
277
K:~
FLOPPY
DISK
DRIVE
MODEM
f------.
I+--
:E
o
N
o
o
.....
-.
o
N
i
r
See page 383 for ordering information.
Information furnisHed by Western Digital Corporation Is believed to be accurate and reliable. However, no responsibility is aasumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise u~der any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
278
Printed in U.S.:&..
WESTERN DIGITAL
COR
PO
RAT
/
ON
WD2001/2 Applications Note
"One Bit Cipher Feedback In A Synchronous System"
INTRODUCTION
WD2001/2 TIMING REQUIREMENTS
The WD2001/2 Data Encryption device interfaces easily to
both microcomputer and hard-wired logic circuits. This Applications Note provides suggestions for the implementation
of a synchronous circuit to perform system timing in a one bit
cipher feedback appl ication.
The WD2001/2 may be operated from a 2 MHZ clock. This
provides a fundamental time period of 500 nSec that easily
fits into the timing requirements for the device. For example,
the minimum pulse width for a read (RD) or write (WR) pulse
is 450 nSec.
SYSTEM TIMING CONSIDERATIONS
Generation of the RD or WR pulse can be directly obtained
from a synchronous device that transitions at each edge of
the synchronous clock (SYNCLK). Figure 1 illustrates the
timing relationship between SYNCLK and RD or WR.
The synchronous operation of a digital circuit often leads to
both minimal hardware count and simple, easy to understand
timing relationships. In addition, the concern over individual
device characteristics become non-critical through the use
of a worst case design approach. Common problems such
as race conditions and temperature sensitivity can be virtually eliminated by synchronizing all logical events to a well
defined clock edge.
Once the timing relationship is understood, the implementation becomes qUite straightforward. The circuit of Figure 2
suggests a possible method of RD or WR generation.
T = PERIOD
500
NSEC
L
I
(2MHZ)
SYNCLK
RD OR WR
T
STATES
T1
T3
T2
T1
T2
T2 _ _ _ _-.J
T3~L__________~r----l~
__________
Figure 1 SYNCLK, RD, AND WR TIMING RELATIONSHIPS.
279
i\5
+5V
r
2.2K
RIPPLE OUT
L
-
SYNCLK
ENABLE T
I
--
ENABLE P
LOAD
SYNCHRONOUS
COUNTER
CLOCK
2.2K
QA
74163
I
QS
A
r:
(TT)
OR
WR
QC
QD
D
CLEAR
T STATE
COUNTER STATE
QS
QA
RD OR WR
T1
13
0
1
0
T2
14
1
0
1
T3
15
1
1
1
Figure 2 RD AND WR TIMING GENERATION
FUNDAMENTAL TIMING SEQUENCES
The Load Key, Load Data, and Unload Data sequences are
highly similar. Figure 4 shows the logical flow associated
with the Key Load or Data Load, or Data Unload. The Data
Encryption Algorithm sequence can be derived from the timing associated with the other three sequences. For simplicity,
the DES timing is accomplished by counting groups of three
clock periods in a fashion similar to the method shown in
Figure 4. The logical flow for the DES timing is shown in Figure 5.
Any cryptographic implementation using the Data Encryption
Standard (DES) can be broken down into four fundamental
timing sequences. First, the key is loaded into the WD2001/
2 (Load Key). Second, the data to be encrypted or decrypted
is loaded into the device (Load Data). Next, the DES is executed. Finally, the result of the DES is unloaded from the
WD2001/2 (Unload Data). Figure 3 lists the timing requirements for each timing sequence.
SEQUENCE
NUMBER OF CLOCK PERIODS
Load Key
8 bytes x 3 clocks
24
Load Data
8 bytes x 3 clocks
24
DES
17 x 3 clocks
51
Unload Data
8 bytes x 3 clocks
24
Figure 3 FUNDAMENTAL TIMING SEQUENCES
280
TOTAL
T1
T2
T3
YES
r------
r------
DONE
Figure 4 KEY LOAD, DATA LOAD,
AND DATA UNLOAD FLOW
DONE
Figure 5 DES LOGICAL FLOW
and also highlights the three I/O operations. Note that the
Key Load sequence is outside of the tight loop.
SYSTEM TIMING OVERVIEW
The normal operation of a cryptographic system would require three classes of inpuVoutput (I/O) operations with the
WD2001/2. First, the key is loaded (Key Load) through eight
consecutive write cycles. Second, the data to be encrypted
or decrypted is loaded (Load Data) in a similar fashion. After
the Data Encryption standard is completed, the data is unloaded (Unload Data) through eight consecutive read cycles.
Typically, the Key Load sequence would occur much less
frequently than the Load Data or Unload Data sequences.
Using the four fundamental timing sequences as logical
building blocks, a functional block diagram of system timing
can be designed. Figure 7 illustrates the overall system timing functions.
An implementation of the functions shown in Figure 7 is suggested in Figure 8. Note that all timing transitions are synchronous with the rising edge of SYNCLK.
Figure 9 details the timing of the Load Key sequence, and is
similar to the Load Data, Unload Data, and DES sequences
also.
The flow diagram of Figure-6 shows the relationship between
the four fundamental timing sequences defined previously,
281
I/O
I/O
YES
110
NO
DONE
NO
YES
Figure 6 FUNDAMENTAL TIMING SEQUENCES INTERRELATIONS
CONTROL LOGIC
(8 x 3)
T
STATE
GENERATOR
(8
x 3)
(17 x 3)
T1,T2,T3
1
3
RD
GENERATION
WR
GENERATION
I
DES
COUNTER
l
l
Figure 7 SYSTEM TIMING BLOCK DIAGRAM
282
OATA Au
WRQrij
""""
""""
ROON
,. KEYLOAD RQ AND DATA RQ DO NOT OCCUR
SIMULTANEOUSLY.
2. ALL J·K PRESETS TO +5V.
3. ALL J-K CLEARS TO "RESET".
4. RESET SHOULD LOAD ALL 74LS163 COUNTERS.
Figure 8 SYSTEM TIMING IMPLEMENTATION
'_.=C;~M==
~~
{CCR)fi
(1)
(j)
(01
(KI
(2)
(3)
(8)
KEYLOAD-r
if
~C---------------!f(-KEYON
KEYOONE
-----------------------------------#if~~~----
SYNCLK
Figure 9 SINGLE KEYLOAD SEQUENCE
283
ONE BIT CIPHER FEEDBACK
of data, and hence the WD2001/2 can be used in a multichannel communications environment.
The one bit cipher feedback (OBCFB) architecture is widely
used in Data Communications. The WD2001/2 device, when
operated with a 2 MHZ clock, will run at an effective bit rate
of over 19,200 bits/second, which is the practical upper limit
of many communications links.
In OBCFB, the WD2001/2 is always set to encrypt mode.
The selection of either the SOl as the feedback element to
the shift register, or the SDO as the feedback element, determines whether the incoming data is encrypted or
decrypted.
FUNDAMENTAL LOGICAL COMPONENTS OF OBCFB
Another factor involved with OBCFB is the propagation of errors through a 64 bit block of data. Because of the 64 bit shift
register that feeds the INV, a single bit error will cause the
following 63 bits to be in error also. After the last bit of the 64
erred bits, the data will become resynchronized and the effect of the shift register will no longer cause bad data.
A one bit cipher feedback system can be broken down into
nine logical components, as listed in Figure 10.
NAME
DESCRIPTION
KEY
56 bit number that maps INV to OV
IV
Initialization Vector
INV
Input Vector
DES
Data Encryption Standard
OV
Output Vector
SOl
Serial Data In
SDO
Serial Data Out
SR
Shift Register (used with INV)
MOD2
Modulo 2 Adder
msb
DES (WD2001/2)
msb
of
OV
Figure 10
NINE FUNDAMENTAL COMPONENTS OF OBCFB
SOl
SOO
FUNCTIONAL DESCRIPTION OF OBCFB
Modulo 2
Adder
The OBCFB algorithm operates on a one bit wide data input,
hence it is ideally suited to serial Data Communications applications. In encryption mode, the serial data in is added
modulo 2 with the most significant bit (msb) of the 64 bit output vector. The result of this operation is then fed into the
least significant bit (Isb) of a 64 bit shift register, and also is
used as the serial data output. The shift register is then
shifted from the Isb to the msb, and the result becomes the
next input vector. After the Data Encryption Standard is
completed, the process is repeated again for the next single
bit of serial input data. Because each serial data bit requires
an entire 64 bit INV and OV, the effective bit rate of this operation is 64 times less than that of a operation which uses
all 64 bits of the OV, such as Code Book. Figure 11 shows a
block diagram of a OBCFB circuit operating in encryption
mode.
Figure 11 OBCFB ENCRYPTION BLOCK DIAGRAM
msb
DES (W02001/2)
msb
of
OV
To decrypt, the operation is changed in one way. Instead of
feeding the result of the modulo 2 adder to the shift register,
the unmodified serial data is used. All other operations are
identical. Figure 12 shows a circuit which supports both encryption and decryption.
SOl
Because the OBCFB algorithm uses a 64 bit shift register on
the INV, each SDO bit is a function of its corresponding SOl
bit and the 64 previous operations. This implies that the past
history of the encryption operation is necessary to initialize
a system. The IV is used to supply the history required to allow immediate use of the OV from the DEA. Typically, the IV
is either a predefined value, or the last 64 SDO bits from the
data stream being encrypted or decrypted. This allows the
encryption process to be accomplished with discrete blocks
~~
____________
~
__
~
SOO
SOO if ENCRYPT
SOl if OECRYPT
Figure 12
OBCFB ENCRYPTION/DECRYPTION BLOCK DIAGRAM
284
ONE BIT CIPHER FEEDBACK IMPLEMENTATION
Digital FIFO and some common TTL logic.
Since the WD2001!2 is a byte input/output oriented device,
the implementation of a OBCFB circuit can be accomplished
without the 64 bit shift register shown in Figures 11 and 12.
Through the use of a 9 bit wide FIFO, a "virtual" 64 bit shift
register can be built. Figure 13 illustrates this with a Western
Once the modulo 2 adder, the encrypt/decrypt selector, and
the shift register are defined, the overall circuit can be generated by combining these pieces along with the logic shown
in Figure 8. The overall block diagram of the one bit cipher
feedback system is given in Figure 14.
WRON· T2
RoON.t,
8
2.2
2.2
TEST POINTS
0.8
0.45
<
0.8
DEVICE
UNDER
TEST
)C
-YCL
':'"
AC TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" AND
0.45V FOR A LOGIC "0" TIMING MEASUREMENTS ARE MADE AT
2.2V FOR A LOGIC "1" AND 0.8V FOR A LOGIC "0."
WAVEFORMS
Typical Dot Level Timing
EXT DOT CLK
l~
CCLK'
C(;0·6
_____~
SECOND CHARACTER CODE
FIRST CHARACTER CODE
CHARACTER
GENERATOR
OUTPUT
FIRST CHARACTER
SECOND CHARACTER
ATTRIBUTES
& CONTROLS
SHIFT REGISTER SETUP __
VIDEO
(FROM SHIFT
REGISTER)
~
ATTRIBUTES
& CONTROLS
(FROM
SYNCHRONIZER)
_______y ________J
FIRST CHARACTER
ATTRIBUTES & CONTROLS
FOR FIRST CHAR.
'CCLK IS A MULTIPLE OF THE DOT CLOCK AND AN INPUT TO THE 8275.
306
ATTRIBUTES & CONTROLS
FOR 2ND CHAR.
WAVEFORMS (Continued)
Line Timing
'LAo-1, VSP, LTEN, HGLT, RVV, GPAO_1
Row Timing
CCLK
HRTC
PROGRAMMABLE FROM 1 TO 16 LlNES~
INTERNAL
ROW
COUNTER
______
-J.~ ---P-R-ES-E-N-T-R-O-W----~;
__
Frame Timing
307
~OW
:eC
00
I\)
......
WAVEFORMS (Continued)
Write Timing
Read Timing
(,J1
AO, CS
VALID
INVALID
RD
WR
tDF
INVALID
DBO_?
DBO-7
DMA Timing
Clock Timing
CCLK
~---tCLK --_~
ORO
CCLK
DACK - - - - - - - - - ,
WR
LPEN
Interrupt Timing
CCLK:
CCO_6 LAST RETRACE
X FIRST RETRACE CHARACTER
CS
CHARACTER
LCO-3
C'~HT=_
HRTC
INTERNAL
ROW
COUNTER
LAST DISPLAY ROW
IRO
See page 383 for ordering information,
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
308
WESTERN DIGITAL
c
o
R
p
o
R
A
T
o
/
N
WD8276 Small System CRT Controller
FEATURES
• PROGRAMMABLE SCREEN AND CHARACTER
FORMAT
• 6 INDEPENDENT VISUAL FIELD ATTRIBUTES
• 11 VISUAL CHARACTER ATTRIBUTES (GRAPHIC
CAPABILITY)
• CURSOR CONTROL (4 TYPES)
• LIGHT PEN DETECTION AND REGISTERS
• DUAL ROW BUFFERS
• PROGRAMMABLE DMA BURST MODE
• SINGLE + 5V SUPPLY
• 40-PIN PACKAGE
• 2 MHz VERSION (WD8276-00)
• 3 MHz VERSION (WD8276-02)
LC3
40
LC2
LC1
LC o
39
38
37
36
35
34
BRDY
BS
HRTC
VRTC
AD
WR
NC
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
GND
DESCRIPTION
309
NC
LTEN
RVV
VSP
GPA1
33
32
31
GPAo
HLGT
INT
30
29
28
CCLK
27
26
CC4
CC3
CC2
CC1
25
24
23
22
21
Pin Designation
The WD8276 Programmable CRT Controller is a
single chip device to Interface CRT raster scan
displays with microcomputer systems. Its primary
function is to refresh the display by buffering the
information from main memory and keeping track of
the display position of the screen. The flexibility
designed into the WD8276 will allow simple interface
to almost any raster scan CRT display with a minimum of external hardware and software overhead.
VCC
NC
CC6
CC5
CCo
CS
C/i>
Table 1.
Pin Descriptions
PIN
NO.
TYPE
1
0
LINE COUNT
5
0
BUFFER READY
LC3
LC2
LC1
LCO
BRDY
6
I
BUFFER SELECT
BS
Input signal enabling WR for character data into
the Row Buffers.
7
0
HORIZONTAL
RETRACE
HRTC
Output signal which is active during the pro·
grammed horizontal retrace interval. During this
period the VSP output is high and the LTEN
output is low.
8
0
VERTICAL RETRACE
VRTC
Output signal which is active during the pro·
grammed vertical retrace interval. During this
period the VSP output is high and the LTEN
output is low.
9
10
I
I
READ INPUT
WRITE INPUT
RD
WR
NO CONNECTION
NC
A control signal to read registers.
A control signal to write commands into the
control registers or write data into the row
buffers.
No connection
BIDIRECTIONAL
DATA BUS
DBO
DB1
DB2
DB3
DB4
DBS
DB6
DB7
Ground
Three·state lines. The outputs are enabled
during a read of the C or P ports.
C/P
A high input on this pin selects the "C" port or
command registers and a low input selects the
"P" port or parameter registers.
PIN NAME
2
3
4
11
12
13
14
15
16
17
18
19
110
SYMBOL
FUNCTION
Output from the line counter which is used to
address the character generator for the line
positions on the screen.
Output signal indicating that a Row Buffer is
ready for loading of character data.
20
21
I
GROUND
PORT ADDRESS
22
I
CHIP SELECT
CS
Enables RD of status or WR of command or
parameters.
23
24
25
26
27
28
29
0
CHARACTER CODES
Output from the row buffers used for character
selection in the character generator.
30
I
31
0
0
CHARACTER CLOCK
INTERRUPT OUTPUT
CCo
CC1
CC2
CC3
CC4
CC5
CC6
CCLK
INT
HIGHLIGHT
HLGT
Interrupt output.
Output signal used to intensify the display at
particular positions on the screen as specified
by the field attribute codes.
GENERAL PURPOSE
ATTRIBUTE CODES
GPA1
GPAO
Outputs which are enabled by the general
purpose field attribute codes.
32
33
34
0
Character clock (from dot/timing logic).
310
Table 1.
PIN
NO.
Pin Descriptions (Continued)
TYPE
PIN NAME
SYMBOL
35
0
VIDEO SUPPRESSION
VSP
36
0
REVERSE VIDEO
RVV
37
0
LIGHT ENABLE
LTEN
NO CONNECTION
NO CONNECTION
+ 5V POWER SUPPLY
NC
NC
38
39
40
FUNCTION
Output signal used to blank the video signal to
the CRT. This output is active:
-during the horizontal and vertical retrace
intervals.
-at the top and bottom lines of rows if underline is programmed to be number 8 or
greater.
-when an end of row or end of screen code is
detected.
-when a Row Buffer underrun occurs.
-at regular intervals (1/16 frame frequency for
cursor, 1132 frame frequency for attributes) to create blinking displays as specified by
cursor or field attribute programming.
Output signal used to activate the CRT circuitry
to reverse the video signal. This output is active
at the cursor position if a reverse video block
cursor is programmed or at the positions
specified by the field attribute codes.
Output signal used to enable the video signal to
the CRT. This output is active at the programmed underline cursor position, and at
positions specified by attribute codes.
No connection.
No connection.
+ 5V power supply.
VCC
FUNCTIONAL DESCRIPTION
Data Bus Buffer
This 3-state, bidirectional, 8-bit buffer is used to
interface the WD8276 to the system Data Bus.
This functional block accepts inputs from the System Control Bus and generates control signals for
overall device operation. It contains the Command,
Parameter, and Status Registers that store the
various control formats for the device functional
definition.
DBO_?
DATA
BUS
BUFFER
BRDV ....- - _ - ,
C/P
0
0
1
1
OPERATION
Read
Write
Read
Write
ss_----,
REGISTER
RESERVED
PARAMETER
STATUS
COMMAND
CCO_6
LINE
COUNTER
LCO·3
INT
ROW
COUNTER
RD
HRTC
VRTC
WR
RD(READ)
A "low" on this input informs the WD8276 that the
CPU is reading status information from the WD8276.
RASTER TIMING
AND
VIDEO CONTROL
cs-_......J
WR(WRITE)
A "low" on this input informs the WD8276 that the
CPU is writing data or control words to the WD8276.
Figure 1.
WD8276 Functional Block Diagram
311
HLGT
RVV
LTEN
VSP
GPAO_1
CS (CHIP SELECl)
A "low" on this input selects the WD8276 for RD or
WR of Commands, Status, and Parameters.
horizontal retrace interval. It is driven by the CCLK
(Character Clock) input, which should be derived
from the external dot clock.
BRDY (BUFFER READY)
A "high" on this output indicates that the WD8276 is
ready to receive character data.
Line Counter
The Line Counter is a programmable counter that is
used to determine the number of horizontal lines
(Raster Scans) per character row. Its outputs are
used to address the external character generator.
BS (BUFFER SELECl)
A "low" on this input enables WR of character data to
the WD8276 row buffers.
Row Counter
The Row Counter is a programmable counter that
is used to determine the number of character rows
to be displayed per frame and length of the vertical
retrace interval.
INT (INTERRUPl)
A "high" on this output informs the CPU that the
WD8276 needs interrupt service.
C/P RD WR CS
0
0
1
0
0
1
0
0
1
1
0
0
1
1
0
0
X
1
1
0
X
X
1
X
1
X
BS
1
1
1
1
0
Raster Timing and Video Controls
The Raster Timing circuitry controls the timing of
the HRTC (Horizontal Retrace) and VRTC (Vertical
Retrace) outputs. The Video Control circuitry
controls the generation of HGLT (Highlight), RVV
(Reverse Video), LTEN (Light Enable), VSP (Video
Suppress), and GPAO.1 (General Purpose Attribute)
outputs.
Reserved
Write WD8276 Parameter
Read WD8276 Status
Write WD8276 Command
Write WD8276 Row
Buffer
X High Impedance
1 High Impedance
X
1
Row Buffers
Buffers are two 80-character buffers. They
from the microcomputer system memory
character codes to be displayed. While
buffer is displaying a row of characters,
Character Counter
The Character Counter is a programmable counter
that is used to determine the number of characters
to be displayed per row and the length of the
INT
The Row
are filled
with the
one row
LCO·3
BRDY
BOBB
MICRO·
PROCESSOR
.
CCO-6
EiS
WDB276
CS
i'-
•
r
v
CRT
CONTROLLER
VIDEO SIGNAL
CHARACTER
GENERATOR
(ROM OR
RAM)
I
CCLK
B205
DECODER
r
HIGH
SPEED
DOT
TIMING
LOGIC
AND
INTERFACE
HORIZONTAL SYNC
TO CRT
VERTICAL SYNC
INTENSITY
VIDEO CONTROLS
.
SYSTEM BUS
4
.
;:.
4
to-
,.
.
~
8253-5
COUNTERI
TIMER
4
.
r:-
~
!or
!or
PROGRAMI
DISPLAY
MEMORY
WD1983
UART
~
tRIA!
COMMUNICATIONS
CHANNEL
Figure 2.
8255A-5
KEYBOARD
CONTROLLER
KEYBOARD
CRT System Block Diagram
312
I
STATUS
J
the other is being filled with the next row of
characters.
next row of characters to be displayed. The number
of display characters per row and the number of
character rows per frame are software programmable, providing easy interface to most CRT
displays. (See Programming Section.)
The WD8276 uses BRDY to request character data
to fill the row buffer that is not being used for
display.
The WD8276 displays character rows one scan line
at a time. The number of scan lines per character
row, the underline pOSition, and blanking of top and
bottom lines are programmable. (See Programming
Section.)
The WD8276 provides special Control Codes which
can be used to minimize overhead. It also provides
Visual Attribute Codes to cause special action on
the screen without the use of the character
generator. (See Visual Attributes Section.)
The WD8276 also controls raster timing. This is
done by generating Horizontal Retrace (HRTC) and
Vertical Retrace (VRTC) Signals. The timing of these
signals is also programmable.
The WD8276 can generate a cursor. Cursor location
and format are programmable. (See Programming
Section.)
Buffer Input/Output Controllers
The Buffer Input/Output Controllers decode the
characters being placed in the row buffers. If the
character is a field attribute or special code, they
control the appropriate action. (Example: A "Highlight" field attribute will cause the Buffer Output
Controller to activate the HGLT output.)
SYSTEM OPERATION
The WD8276 is programmable to a large number of
different display formats. It provides raster timing,
display row buffering, visual attribute decoding and
cursor timing.
It is deSigned to interface with standard character
generators for dot matrix decoding. Dot level timing
must be provided by external circuitry.
GENERAL SYSTEMS OPERATIONAL
DESCRIPTION
Display characters are retrieved from memory and
displayed on a row-by-row basis. The WD8276 has
two row buffers. While one row buffer is being
used for display, the other is being filled with the
1st
2nd
3rd
4th
5th
6th
7th
Character Character Character Character Character Character Character
~~~~_~--~~~-A~~~~r~_ _
DO • • • • ODO.OCOO.oO • • • • • ODDDDDDDO • • • • ODDO • • • DOO.ODO.O
First Line of a Character Row
1st
2nd
3rd
4th
5th
6th
7th
Character Character Character Character Character Character Character
~r--"---.r--"---.~~~
00 • • • • 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
0.0000_00 • • 000.00_0000000000000_000_00_000_00_000.0
Second Line of a Character Row
1st
2nd
3rd
4th
5th
6th
7th
Character Character Character Character Character Character Character
~,.--A--.,,.--A--.,~~~,--A---..
00 • • • • 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
0.0000.00 • • 0 0 0 . 0 0 . 0 0 0 0 0 0 0 0 0 0 0 0 0 . 0 0 0 . 0 0 . 0 0 0 . 0 0 . 0 0 0 . 0
0.0000.00.0000.00.0000000000000.000.00.000.00.000.0
Third Line of a Character Row
1st
2nd
3rd
4th
5th
6th
7th
Character Character Character Character Character Character Character
,.--A--.,,.--A--.,r--./'-v--,A-.,,-"----,,---A--,,~
00 • • • • 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
0.0000.00 • • 000.00.0000000000000.000.00.000.00.000.0
0.0000.00.0.00.00.0000000000000.000.00.000.00.000.0
0.0000.00.0000.00 • • • • 0000000000 • • • • 000.000.00.0.0.0
0.0000.00.00.0.00.0000000000000.0.0000.000.00.0.0.0
o.onnn.oo.ooo •• oo.ooooooooooooo.oo.ooo.ooo.oo.o.o.o
00 • • • • 000.0000.00 • • • • • 000000000.00.0000 • • • 0000.0.00
Seventh Line of a Character Row
Figure 3.
Display of a Character Row
313
r
DISPLAY ROW BUFFERING
Before the start of a frame, the WD8276 uses BRDY
and BS to fill one row buffer with characters.
When the first horizontal sweep is started, character
codes are output to the character generator from the
row buffer just filled. Simultaneously, the other row
buffer is filled with the next row of characters.
After all the lines of the character row are scanned,
the buffers are swapped and the same procedure is
followed for the next row.
'eJ'f1>t:1'f-l!:} CCO-6
This process is repeated until all of the character
rows are displayed.
Row Buffering allows the CPU access to the display
memory at all times except during Buffer Loading
(about 25%). This compares favorably to alternative
approaches which restrict CPU access to the display
memory to occur only during horizontal and vertical
retrace intervals (80% of the bus time is used to
refresh the display.)
Figure 6.
First Buffer Filled with Third Row,
Second Row Displayed
DISPLAY FORMAT
Screen Format
The WD8276 can be programmed to generate from 1
to 80 characters per row, and from 1 to 64 rows per
frame.
CCO·6
123456789 .................... 80
2
3
4
Figure 4.
First Row Buffer Filled
5
6
7
8
9
64
Figure 7.
Screen Format
The WD8276 can also be programmed to blank
alternate rows. In this mode, the first row is displayed, the second blanked, the third displayed, etc.
Display data is not requested for the blanked rows.
Figure 5.
Second Buffer Filled, First Row Display~d
314
In mode 1, the line counter is offset by one from the
line number.
NOTE:
In mode 1, while the first line (line number 0) is being
displayed, the last count is output by the line counter
(see examples).
123456789 .................... 80
2
3
4
5
Line
Number
0
u i:J
I
I]
1
I.-j II
2
3
r:
IJ
[J
4
U
•
5
u •
6
II
LJ
7
u
u
8
I.-! [J L::J
9
Ll LJ U
I~l
64
•
Row Format
The WD8276 is designed to hold the line count stable
while outputting the appropriate character codes
during each horizontal sweep. The line count is incremented during horizontal retrace and the whole
row of character codes are output again during the
next sweep. This is continued until the entire
character row is displayed.
The number of lines (horizontal sweeps) per character row is programmable from 1 to 16.
The output of the line counter can be programmed to
be in one of two modes.
In mode 0, the output of the line counter is the same
as the line number.
20DO.O.OOCJ
3ou.ooo.CJo
4o.oCJcuo.o
5o.[J[J[J[J[J.o
6 [J • • • • • • •
7 [J • [J [J [J [J [J • [J
8[J.o[J[J[Jo.[J
9 [J • [J [J [J [J 0 • [J
10 [J [J [J [J [J [J
0 [J
11 [J [J [J 0 [J [J [J [J 0
12 [J [J 0 CJ 0 0 0 U 0
13 U 0 0 0 U [J [J [J 0
14 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0
1:1
u u
II
[J
•
•
••••
•
•
•
•
[J
FigureS.
Blank Alternative Rows Mode
Line
Number
OOCioeo
000
1ooCio.oeoo
II
•u
• •
II
-~
Line
Line
Counter Counter
Mode 0 Mode 1
000 0 1 0 1
000 1
0 0 0
o 0 1 0 000 1
o0 1 1 0 1 0
0 1 0
0 1 1
0 1 0 1 0 1 0
0 1 1 0 0 1 0 1
0 1 1 1 0 1 1 0
1 000 0 1 1 1
1 0 1 1 000
I~"
C--[
II
1--1
[OJ
l.J
U
LJ
o
[J
[]
U
U
0
Ll
II
[J
U U L-:l
o
o
o
o
o
o
Figure 10.
Example of a 10·Line Format
Mode 0 is useful for character generators that leave
address zero blank and start at address 1. Mode 1 is
useful for character generators which start at address zero.
Underline placement is also programmable (from line
number 0 to 15). This is independent of the line
counter mode.
If the line number of the underline is greater than 7
(line number MSB = 1), then the top and bottom
lines will be blanked.
Line
Number
0 o
1 U
2 []
3 o
4 o
5 o
6 o
7 C
8 o
9 o
10
11 []
Line
Line
Counter Counter
Mode 0 Mode 1
000 0 1 1 1 1
000 1 o 0 0 0
001 0 000 1
001 1 001 0
o 1 0 0 001 1
o1 0 1 o1 0 0
o1 1 0 o1 0 1
o1 1 1 o1 1 0
1 000 o 1 1 1
1 0 0 1 1 000
101 0 1 0 0 1
1 0 1 1 1 0 1 0
1 1 0 0 1 0 1 1
1 1 0 1 1 1 0 0
1 1 1 0 1 1 0 1
1 1 1 1 1 1 1 0
c:: []
0
0
U
LJ
0
['
0
C •
0
[J
0
LJ
LJ
U •
Ll
•
0
o
0
0
•
0
[]
0
•
LJ
0
•
•
0
0
u
U
0
•
0
L:i
o
0
0
0
•
U
•
•
[J
o [] •
[j
• •
•
0
o • u
ooou.u
0
0
0
•
•
•••
0
000
cJ
• •0 •0 • •0 •0 •0 • •
[J
[J
Line
Line
Counter Counter
Mode 0 Mode 1
000 0 1 0 1 1
000 1
0 0 0
001 0
0 0 1
001 1 001 0
o 1 00 001 1
o1 1 1 0 0
o1 1 0 1 1
o1 1 1 1 1 0
1 000
1 1 1
1 0 0 1 1 000
101 0 1 0 0 1
1 0 1 1 101 0
o
o
o
o
o o
o
o
Top and Bottom
Lines are Blanked
Figure 11.
Underline in Line Number 10
If the line number of the underline is less than or
equal to 7 (line number MSB = 0), then the top and
bottom lines will not be blanked.
Figure 9.
Example of a 16·Line Format
315
Line
Number
0
o 0 0 0 0 o 0
1
DDLJ.D[JD
2
DO. o • o 0
3
o • 0 DO.
4
o • 0 o 0 • 0
5
6
7
o • • •
o • 0 o
•
•
0
0
•
0
•••••••
Line
Line
Counter Counter
Mode 0 Mode 1
0000 o 1 1 1
000 1 o 0 0 0
001 0 000 1
001 1 001 0
o 1 0 0 001 1
o1 0 1 o1 0 0
o1 1 0 o1 0 1
o1 1 1 o1 1 0
Top and Bottom
Lines are not Blanked
RASTER TIMING
The character counter is driven by the character
clock input (CCLK). It counts out the characters
being displayed (programmable from 1 to 80). It then
causes the line counter to increment, and it starts
counting out the horizontal retrace interval (programmable from 2 to 32). This process is constantly
repeated.
CCLK
Figure 12.
Underline in Line Number7
HRTC
If the line number of the underline is greater than the
maximum number of lines, the underline will not
appear.
Blanking is accomplished by the VSP (Video Suppression) signal. Underline is accomplished by the
LTEN (Light Enable) signal.
Dot Format
Dot width and character width are dependent upon
the external timing and control circuitry.
Dot level timing circuitry should be designed to
accept the parallel output of the character generator
and shift it out serially at the rate required by the CRT
display.
PROGRAMMABLE 1 TO 80 CCLKS
PRESENT
LINE
COUNT
LCO_3 _ _ _ _
____
__
_ _ _ _- J
Figure 14.
Line Timing
The line counter is driven by the character counter. It
is used to generate the line address outputs (LCO-3)
for the character generator. After it counts all of the
lines in a character row (programmable from 1 to 16),
it increments the row counter, and starts over again.
(See Character Format Section for detailed description of Line Counter functions.)
The row counter is an internal counter driven by the
line counter. It controls the functions of the row
buffers' and counts the number of character rows
displayed.
LC
8276
ONE CHARACTER ROW
VIDEO
Figure 13_
Typical Dot Level Block Diagram
Dot width is a function of dot clock frequency.
Character width is a function of the character generator width.
Horizontal character spacing is a function of the shift
register length.
NOTE:
Video control and timing Signals must be synchronized with the video signal due to the character
generator access delay.
NEXT
LINE COUNT
LCO_3
INTERNAL
ROW COUNTER
PROGRAMMABLE 1 TO 16
LINE COUNTS
Figure 15.
Row Timing
After the row counter counts all of the rows in a
frame (programmable from 1 to 64), it starts counting
out the vertical retrace interval (programmable from 1
to 4).
A reset command will also cause INT to go inactive,
but this is not recommended during normal service.
NOTE:
Upon power-up, the WD8276 Interrupt Enable Flag
may be set. As a result, the user's cold start routine
should write a reset command to the WD8276 before
system interrupts are enabled.
ONE FRAME
VISUAL ATIRIBUTES
AND SPECIAL CODES
The characters processed by the WD8276 are 8bit quantities. The character code outputs provide
the character generator with 7 bits of address. The
Most Significant Bit is the extra bit and it is
used to determine if it is a normal display character
(MSB = 0), or if it is a Field Attribute or Special Code
(MSB = 1).
PROGRAMMABLE
PROGRAMMABLE
1 TO 64 ROW COUNTS 1 TO 4 ROW COUNTS
Special Codes
Figure 16.
Frame Timing
Four special codes are available to help reduce bus
usage.
The Video Suppression Output (VSP) is active during
horizontal and vertical retrace intervals.
SPECIAL CONTROL CHARACTER
Dot level timing circuitry must synchronize these
outputs with the video signal to the CRT Display.
MSB
INTERRUPT TIMING
The WD8276 can be programmed to generate an
interrupt request at the end of each frame. If the
WD8276 interrupt enable flag is set, an interrupt
request will occur at the beginning of the last display
row.
INTERNAL
ROW
COUNTER
=x=x
S
S
S
0
0
0
1
1
0
1
1
End
End
End
End
of
of
of
of
FUNCTION
Row
Row-Stop Buffer Loading
Screen
Screen-Stop Buffer Loading
The End of Row Code (00) activates VSP and holds it
to the end of the line.
The End of Row-Stop Buffer Loading (BRDY) Code
(01) causes the Buffer Loading Control Logic to stop
buffer loading for the rest of the row upon being
written into the Row Buffer. It affects the display in
the same way as the End of Row Code (00).
The End of Screen Code (10) activates VSP and holds
it to the end of the frame.
The End of Screen-Stop Buffer Loading (BRDY) Code
(11) causes the Row Buffer Control Logic to stop
buffer loading for the rest of the frame upon being
written. It affects the display in the same way as the
End of Screen Code (10).
If the Stop Buffer Loading feature is not used, all
characters after an End of Row character are ignored,
except for the End of Screen character, which
operates normally. All characters after an End of
Screen character are ignored.
NOTE:
If a Stop Buffer Loading is not the last character in a
row, Buffer Loading is not stopped until after the next
character is read. In this situation, a dummy
character must be placed in memory after the Stop
Buffer Loading character.
VRTC~l-_~9---'
INT
Figure 17.
Beginning of Interrupt
t
INT will go inactive after the status register is read.
RD-----""I\...._ _ _ _- - '
0 S
Lspecial Control Code
LAST
FIRST
DISPLAY RETRACE
ROW
ROW
INT
LSB
o
----
Figure 18.
End of Interrupt
317
I
r
Field Attributes
The field attributes are control codes which affect
the visual characteristics for a field of characters,
starting at the character following the code up to, and
including, the character which precedes the next
field attribute code, or up to the end of the frame. The
field attributes are reset during the vertical retrace
interval.
The WD8276 can be programmed to provide visible
field attribute characters; all field attribute codes will
occupy a position on the screen. These codes will
appear as blanks caused by activation of the Video
Suppression output (VSP). The chosen visual attributes are activated after this blanked character.
FIELD ATIRIBUTE CODE
MSB
1 0 U R G G B
ABC D E
I L-. Highlight
L--Blink
?eneral Purpose
Reverse Video
Underline
H = 1 for highlighting
B = 1 for blinking
R
1 for reverse video
U = 1 for underline
GG = GPA1, GPAO
NOTE:
More than one attribute can be enabled at the
same time. If the blinking and reverse video attributes are enabled simultaneously, only the
reversed characters will blink.
=
Cursor Timing
The cursor location is determined by a cursor row
register and a character position register which are
loaded by command to the controller. The cursor
can be programmed to appear on the display as:
1. a blinking underline
2. a blinking reverse video block
3. a non-blinking underline
4. a non-blinking reverse video block
The cursor blinking frequency is equal to the
screen refresh frequency divided by 16.
If a non-blinking reverse video cursor appears in a
non-blinking reverse video field, the cursor will
appear as a normal video block.
If a non-blinking underline cursor appears in a nonblinking underline field, the cursor will not be
visible.
Device Programming
The WD8276 has two programming registers, the
Command Register and the Parameter Register. It
also has a Status Register. The Command Register
can only be written into and the Status Register
can only be read from. They are addressed as
follows:
F G H I J K L M
P Q R STU V
CIP
0
0
1 2 3 4 5
_
.
There are six field attributes:
1. Blink - Characters following the code are
caused to blink by activating the Video Suppression output (VSP). The blink frequency is
equal to the screen refresh frequency divided by
32.
2. Highlight - Characters following the code are
caused to be highlighted by activating the
Highlight output (HGlT).
3. Reverse Video - Characters following the code
are caused to appear with reverse video by
activating the Reverse Video output (RVV).
4. Underline - Chaiacters following the code are
caused to be underlined by activating the Light
Enable output (lTEN).
5,6. General Purpose - There are two additional
WD8276 outputs which act as general purpose,
independently programmable field attributes.
GPAO-1 are active high outputs.
N 0
L
II
lSB
H
1
1
6 789
OPERATION
Read
Write
Read
Write
REGISTER
Reserved
Parameter
Status
Command
The WD8276 expects to receive a command and
a sequence of 0 to 4 parameters, depending on
the command. If the proper number of parameter
bytes are not received before another command is
given, a status flag is set, indicating an improper
command.
Figure 19_
End of a Visible Field Attribute
(Underline Attribute)
318
INSTRUCTION SET
The WD8276 instruction set consists of 7 commands.
NO. OF PARAMETER BYTES
4
0
0
2
0
0
0
COMMAND
Reset
Start Display
Stop Display
Load Cursor
Enable Interrupt
Disable Interrupt
Preset Counters
In addition, the status of the WD8276 can be read by
the CPU at any time.
1. Reset Command
Command
Parameters
OPERATION
Write
Write
Write
Write
Write
C/P
DATA BUS
MSB
LSB
000 0 0 000
S H H H H H H H
VVRRRRRR
UUUULLLL
M1CCZZZZ
DESCRIPTION
Reset Command
Screen Comp Byte 1
Screen Comp Byte 2
Screen Comp Byte 3
Screen Comp Byte 4
1
0
0
0
0
Action
After the reset command is written, BRDY goes
inactive, WD8276 interrupts are disabled, and the
VSP output is used to blank the screen. HRTC and
VRTC continue to run. HRTC and VRTC timing are
random on power·up.
As parameters are written, the screen composition is
defined.
Parameter-RRRRRR Vertical Rows/Frame
NO. OF ROWS/FRAME
R R R R R R
1
0 0 0 0 0 0
2
0 0 0 0 0 1
3
0 0 0 0 1 0
1
Parameter-S Spaced Rows
FUNCTIONS
S
Normal Rows
0
Spaced Rows
1
1
1
1
1
64
1
Parameter-UUUU Underline Placement
LINE NO. OF UNDERLINE
U U U U
1
0 0 0 0
2
0 0 0 1
0 0 1 0
3
Parameter-HHHHHHH Horizontal Characters/Row
NO. OF CHARACTERS
HHHHHHH
PERROW
1
o0 0 0 0 0 0
o0 0 0 0 0 1
2
o0 0 0 0 1 0
3
1
1
1
1
16
Parameter-LLLL
Number of Lines per Character Row
1 00111 1
1 o 1 0 0 0 0
1 1 1 1 1 1 1
80
Undefined
L
0
0
0
L
0
0
0
L
0
0
1
L
0
1
0
NO. OF LINES/ROW
1
2
1
1
1
1
16
3
Undefined
Parameter-W Vertical Retrace Row Count
NO. OF ROW COUNTS PER VRTC
V V
1
0 0
2
0 1
1 0
3
1 1
4
Parameter-M Line Counter Mode
LINE COUNTER MODE
M
Mode 0 (Non·Offset)
0
Mode 1 (Offset by 1 Count)
1
319
Parameter-CC Cursor Format
C
o
o
C
0
1
1
1
0
1
Parameter-ZZZZ Horizontal Retrace Count
CURSOR FORMAT
Blinking reverse video block
Blinking underline
Non-blinking reverse video block
Non-blinkinQ underline
NOTE:
uuuu MSB determines blanking of top and bottom
lines (1
blanked,O
not blanked).
=
=
Z
0
0
0
Z
0
0
0
Z
0
0
Z
0
1
0
NO. OF CHARACTER COUNTS
PERHRTC
2
4
6
1
1
1
1
32
1
2. Start Display Command
Command
OPERATION
Write
No parameters
C/P
DESCRIPTION
Start Display
1
DATA BUS
MSB
LSB
00100 0 0 0
Action
WD8276 interrupts are enabled, BRDY goes active,
video is enabled, Interrupt Enable and Video Enable
status flags are set.
3. Stop Display Command
Command
OPERATION
Write
No parameters
cip
DESCRIPTION
Stop Display
1
DATA BUS
LSB
MSB
o
1 0 0 0 0 0 0
Action
Disables video, interrupts remain enabled, HRTC and
VRTC continue to run, Video Enable status flag is
reset, and the "Start Display" command must be
given to reenable the display.
4. Load Cursor Position
OPERATION
Write
Write
Write
Command
Parameters
cip
DESCRIPTION
Load Cursor
Char. Number
Row Number
1
0
0
DATA BUS
MSB
LSB
1 0 0 0 0 0 0 0
(Char. Position in Row)
(Row Number)
Action
The WD8276 is conditioned to place the next two
parameter bytes into the cursor position registers.
Status flag not affected.
5. Enable Interrupt Command
Command
OPERATION
Write
No parameters
cip
DESCRIPTION
Enable Interrupt
1
Action
The interrupt enable flag is set and interrupts are
enabled.
320
DATA BUS
LSB
MSB
101 0 0 0 0 0
6. Disable Interrupt Command
Command
OPERATION
Write
No parameters
cip
DATA BUS
MSB
LSB
1 100 0 000
DESCRIPTION
Disable Interrupt
1
!
f-
Action
Interrupts are disabled and the interrupt enable
status flag is reset.
7. Preset Counters Command
Command
OPERATION
Write
No parameters
C/P
1
DATA BUS
MSB
LSB
11100000
DESCRIPTION
Preset Counters
Action
The internal timing counters ar:e preset, cor·
responding to a screen display pOSition at the top left
corner. Two character clocks are required for this
operation. The counters will remain in this state until
any other command is given.
This command is useful for system debug and
synchronization of clustered CRT displays on a
single CPU.
STATUS FLAGS
OPERATION
Read
Command
IE
IR
IC
DESCRIPTION
Status Word
C/P
1
-(Interrupt Enable) Set or reset by command. It
enables vertical retrace interrupt. It is
automatically set by a "Start Display" com·
mand and reset with the "Reset" command.
-(Interrupt Request) This flag is set at the
beginning of display of the last row of the
frame if the interrupt enable flag is set. It is
reset after a status read operation.
-(Improper Command) This flag is set when a
command parameter string is too long or too
short. The flag is automatically reset after a
status read.
VE
BU
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ..... O°C to 70°C
Storage Temperature ......... - 65°C to + 150°C
Voltage On Any Pin
With Respect to Ground ........ - 0.5V to + 7V
Power Dissipation ...................... 1 Watt
=
DC Characteristics (TA O°C to 70°C; VCC
SYMBOL
PARAMETER
Input Low Voltage
VIL
Input High Voltage
VIH
VOL
VOH
IlL
10FL
ICC
Output Low Voltage
Output High Voltage
Input Load Current
Output Float Leakage
VCC Supply Current
DATA BUS
MSB
LSB
IE IR X IC VE BU X
o
-(Video Enable) This flag indicates that video
operation of the CRT is enabled. This flag is
set on a "Start Display" command, and reset
on a "Stop Display" or "Reset" command.
-(Buffer Underrun) This flag is set whenever a
Row Buffer is not filled with character data in
time for a buffer swap required by the display.
Upon activation of this bit, buffer loading
ceases, and the screen is blanked until after
the vertical retrace interval.
* NOTICE:
Stresses above those listed under "Absolute Max·
imum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other con·
ditions above those indicated in the operational
sections of this specification is not implied.
= 5V ± 5%)
MIN
-0.5
2.0
MAX
0.8
VCC
+0.5V
0.45
2.4
±10
±10
160
321
UNITS
V
V
V
V
/-I A
~
mA
TEST CONDITIONS
=
=
=
=
10L 2.2mA
10H
-400~
VIN
VcctoOV
VOUT VCCtoO.45V
= 25°C; VCC = GND = OV)
~
Capacitance(TA
SYMBOL
CIN
CliO
~
AC Characteristics (TA
~
PARAMETER
Input Capacitance
110 Capacitance
MIN
MAX
10
20
UNITS
TEST CONDITIONS
pF
fC = 1 MHz
pF
Unmeasured pins returned to VSS.
= O°C to 70°C; VCC = 5.0V ± 5%; GND = OV)
BUS PARAMETERS (Note 1)
Read Cycle
SYMBOL
tAR
tRA
tRR
tRD
tDF
PARAMETER
Address Stable Before
READ
Address Hold Time for
READ
READ Pulse Width
Data Delay from READ
READ to Data Floating
MIN
PARAMETER
Address Stable Before
WRITE
Address Hold Time for
WRITE
WRITE Pulse Width
Data Setup Time for
WRITE
Data Hold Time for
WRITE
MIN
MAX
UNITS
0
ns
0
250
100
ns
ns
ns
ns
MAX
UNITS
200
TEST CONDITIONS
CL = 150pF
Write Cycle
SYMBOL
tAW
twA
tW{IJ
tow
two
0
ns
0
250
ns
ns
150
ns
0
ns
TEST CONDITIONS
Clock Timing
8276-02
8276·00
SYMBOL
tCLK
tKH
tKL
tKR
tKF
PARAMETER
Clock Period
Clock High
Clock Low
Clock Rise
Clock Fall
Other Timing
SYMBOL
tcc
tHR
tLC
tAT
tVR
tRI
two
tRO
tLR
tRL
tPR
tpH
MIN
MAX
30
UNITS
ns
ns
ns
ns
ns
MAX
UNITS
150
150
ns
200
400
150
250
ns
ns
275
250
ns
275
250
250
200
250
250
250
200
ns
ns
ns
ns
ns
ns
ns
ns
480
240
160
5
5
30
30
8276'()0
PARAMETER
Character Code Output
Delay
Horizontal Retrace
Output Delay
Line Count Output Delay
Control/Attribute Output
Delay
Vertical Retrace Output
Delay
INn from ROt
DROt from WRt
DRO~ from WR..
DACK~ to WR+
WRt to DACKt
LPEN Rise
LPEN Hold
MIN
MIN
320
120
120
5
5
MAX
30
TEST
CONDITIONS
8276-02
MAX
0
0
MIN
0
0
50
100
50
100
322
TEST
CONDITIONS
= 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL
WAVEFORMS
Typical Dot Level Timing
EXT DOT CLK
CCLK·l..._ _ _ _ _ _-'
CCO·6
FIRST CHARACTER CODE
-JI'-__________________--'
SECOND CHARACTER CODE
ROM ACCESS
CHARACTER ------------------.I,--------------------------~
GENERATOR
FIRST CHARACTER
OUTPUT _ _ _ _ _ _ _ _ 1""_ _ _ _ _ _ _ _ _ _ _ _"
ATTRIBUTES
&CONTROLS
,-------------------SECOND CHARACTER
'----------
ATTRIBUTES & CONTROLS
FOR FIRST CHAR.
SHIFT REGISTER SETUP
VIDEO
(FROM SHIFT
REGISTER)
ATTRIBUTES
& CONTROLS
(FROM
SYNCHRONIZER)
'---------y~----------~
FIRST CHARACTER
ATTRIBUTES & CONTROLS
FOR FIRST CHAR.
---y-SECOND CHARACTER
ATTRIBUTES & CONTROLS
FOR SECON D CHAR.
• CCLK IS A MULTIPLE OFTHE DOT CLOCK AND AN INPUTTO THE 8276.
Line Timing
CCLK
LCO.3
-+____PR_E_S_E_N_T_L_IN_E_CO_U_NT_ _
-lI:~------------------...I~XT
VIDEO
CONTROLS
AND ATTRIBUTES·
VSP, LTEN, HGLT, RVV, GPAO.1
323
LINE COUNT
Row Timing
CCLK
LCO·3
INTERNAL
ROW
COUNTER
----''1-----------4J------I 1'"---
Frame Timing
CCLK
INTERNAL
ROW
COUNTER
Interrupt Timing
\
CCLK
CCO-6
LCo·3
LAST RETRACE
CHARACTER
X
CIPJ
\
CS~
I
FIRST RETRACE
CHARACTER
FIRST LINE COUNT
AD
\
HRTC
INT
INTERNAL
ROW
COUNTER
INT
LAST DISPLAY ROW
]
I-tlR
if
324
\
t1
Timing for Buffer Loading
CCLK
BRDY
J
\'---
BS
WR
Write Timing
BS,C/F'
CS
Read Timing
INVALID
C/P,CS
--t.____
V_A_L_ID_ _ __
---=4AR
WR
DBO_7
DBO_7
INVALID
Input and Output Waveforms for A.C. Tests
Clock Timing
2.4
0.45
--yo
~
~.O
AO.8
TEST
2.~ ~
POINTS 0.8
fL-
FOR A.C. TESTING, INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1"
AND 0.45V FOR A LOGIC "0." TIMING MEASUREMENTS FOR INPUT
AND OUTPUT SIGNALS ARE MADE AT 2.0V FOR A LOGIC "1" AND
0.8V FOR A LOGIC "0."
325
See page 383 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
326
Pnnted In U S.A
WESTERN DIGITAL
c
o
R
p
o
R
A
T
I
o
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WD1943(8136) Dual Baud Rate Clock
FEATURES
XTALIEXT 1
-16 SELECTABLE BAUD RATE CLOCK FREQUENCIES
+5V
- OPERATES WITH CRYSTAL OSCILLATOR OR EXTERNALLY GENERATED FREQUENCY INPUT
fR
RA
RB
RC
RO
STR
NC
- ROM MASKABLE FOR NON-STANDARD FREQUENCY
SELECTIONS
-INTERFACES EASILY WITH MICROCOMPUTERS
1
2
3
4
5
6
XTALlEXT 2
'T
TA
TB
TC
To
7
STl
8
9
GNO
F/4
- OUTPUTS A 50% DUTY CYCLE CLOCK WITH 0.01 %
ACCURACY
PIN DESIGNATION
- 6 DIFFERENT FREQUENCY/DIVISOR PAIRS
AVAILABLE
-SINGLE +5V POWER SUPPLY
- COMPATIBLE WITH BR1941
-TTL, MOS COMPATIBILITY
- XTAL FREQ .,. 4 OUTPUT INCLUDED
- WD1943IS PIN COMPATIBLE TO THE COM8136 AND
COM5036 (PIN 9 ON WD1943 IS A NO CONNECT)
- CAN REPLACE COM8116 AND COM5016 (Contact Western Digital Representative)
DESCRIPTION
The WD1943 is a combination Baud Rate Clock Generator
and Programmable Divider. It is manufactured in N-channel
MOS using silicon gate technology. This device is capable of
generating 16 externally selected clock rates whose frequency is determined by either a single crystal or an externally generated input clock. The WD1943 is a programmable
counter capable of generating a division by any integer from
4to 2 15 -1, inclusive.
The WD1943 is available programmed with the most used
frequencies in data communication. Each frequency is
selectable by strobing or hard wiring each of the two sets of
four Rate Select inputs. Other frequencies/division rates can
be generated by reprogramming the internal ROM coding
through a MOS mask change. Additionally, further clock division may be accomplished through cascading of devices.
The frequency output is fed into the XTAUEXT input on a subsequent device.
The WD1943 can be driven by an external crystal or by TTL
logiC.
327
PIN DESCRIPTION
SIGNAL NAME
FUNCTION
1
XTAUEXT1
Crystal or
External Input 1
This input receives one pin of the crystal package or one
polarity of the external input.
2
VCC
Power Supply
+ 5 volt Supply
3
fR
Receiver Output
Frequency
This output runs at a frequency selected by the Receiver
Address inputs.
RA, RS, RC, RD
Receiver Address
The logic level on these inputs as shown in Table 1 thru 6,
selects the receiver output frequency, fRo
8
STR
Strobe-Receiver
Address
A high-level input strobe loads the receiver address (RA, RS,
RC, RD) into the receiver address register. This input rnay be
strobed or hard wired to + 5V.
9
NC
No Connection
No Internal Connection
10
F/4
XTAL freq .;- 4
Output
XTAL 1 input freq divided by four.
11
GND
Ground
Ground
12
STT
Strobe-Transmitter
Address
A high-level input strobe loads the transmitter address (TA,
TS, TC, TD) into the transmitter address register. This input
may be strobed or hard wired to + 5V.
TD, TC, TS, TA
Transmitter
Address
The logic level on these inputs, as shown in Table 1 thru 6,
selects the transmitter output frequency, fr.
17
fT
Transmitter
Output
Frequency
This output runs at a frequency selected by the Transmitter
Address inputs.
18
XTALlEXT2
Crystal or
External
Input 2
This input receives the other pin of the crystal package or the
other polarity of the external input.
PIN NUMBER
4-7
13-16
MNEMONIC
TA
T8
TC
TO
~====~.f/4
RA
R8
RC
RD
BLOCK DIAGRAM
328
ELECTRICAL CHARACTERISTICS (TA
= O°C to + 70°C, VCC = + 5V ± 5% standard.)
PARAMETER
MIN
TYP
COMMENTS
MAX
UNIT
0.8
VCC
V
V
See Note 1
0.4
V
V
IOL
IOH
= 3.2mA
= 1ool'A
-10
10
I'A
I'A
~:~
: ~~%f STR(8) and STT (12) Only
300
I'A
VIN
= GND
pf
VIN
= GND, excluding XTAL inputs
DC CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low·level, VIL
High·level, VIH
2.0
OUTPUT VOLTAGE LEVELS
Low·level, VOL
High·level, VOH
VCC·1.5
4.0
INPUT CURRENT
High·level,IIH
Low·level, IlL
Low-level, IlL
INPUT CAPACITANCE
All Inputs, CIN
5
10
EXT. INPUT LOAD
4
5
INPUT RESISTANCE
Crystal Input, RXTAL
POWER SUPPLY CURRENT
ICC
40
80
Resistance to ground for
Pin 1 and Pin 18
mA
= +25°C
AC CHARACTERISTICS
TA
CLOCK FREQUENCY
See Note 2
PULSE WI DTH (Tpw)
Clock
Receiver strobe
Transmitter strobe
150
150
INPUT SET-UP TIME (TSET-UP)
Address
OUTPUT HOLD TIME (THOLD)
Address
STROBE TO NEW FREQUENCY
DELAY
(All inputs except
XTAL, STR and STl)
Series 7400 unit loads
KQ
1.1
r
ns
ns
50% Duty Cycle ± 10%. See Note 2
See Note 3
See Note3
50
ns
See Note3
50
ns
.
DC
DC
6
CLK
NOTE 1: XTAUEXT inputs are either TTL compatible or crystal compatible. See crystal specification in
Applications Information section.
All inputs except XTAL, STR and STT have internal pull-up resistors.
NOTE 2: Refer to frequency option tables for maximum input frequency on XTAUEXT pins.
Typical clock pulse width is 1/2 x CL
NOTE 3: Input set-up time can be decreased to >0 ns by increasing the minimum strobe width (50 ns) to a total of 200 ns.
T A.D and RA-D have internal pull-up resistors.
OPERATION
Non·Standard Frequencies
Standard Frequencies
To accomplish non-standard frequencies do one of the
following:
Choose a Transmitter and Receiver frequency from the
table below. Program the corresponding address into TA·TD
and RA-RD respectively using strobe pulses or by hard
wiring the strobe and address inputs.
1. Choose a crystal that when divided by the WD1943
generates the desired frequency.
2. Cascade devices by using the frequency outputs as an
input to the XTAUEXT inputs of the subsequent
WD1943.
3. Consult the factory for possible changes via ROM mask
reprogramming.
329
FREQUENCY OPTIONS
TABLE 1.
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Transmit/Receive
Address
C
B
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
1
0
0
1
0
1
1
0
1
1
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CRYSTAL FREQUENCY
Baud
Theoretleal
Rate
Clock) FreQ. (kHz)
0.8
50
1.2
75
1.76
110
134.5
2.152
2.4
150
300
4.8
9.6
600
19.2
1200
28.8
1800
32.0
2000
38.4
2400
57.6
3600
4800
76.8
7200
115.2
9600
153.6
19,200
307.2
I (16X
= 5.0688 MHZ
Actual
FreQ. (kHz)
0.8
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8
Percent
Error
-
0.016
-
-
0.253
-
-
-
3.125
Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
48/52
50/50
Divisor
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16
WD1943·QO
TABLE 2.
I
I
D
0
0
0
0
0
a
a
a
1
1
1
1
1
1
1
1
Transmit/Receive
Address
C
B
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
a
a
a
a
1
1
1
1
a
a
1
1
0
0
1
1
A
0
1
0
1
0
1
a
1
a
1
a
1
0
1
0
1
CRYSTAL FREQUENCY
Baud
Theoretical
Rate
(16X Clock) FreQ. (kHz)
50
0.8
75
1.2
110
1.76
134.5
2.152
2.4
150
4.8
300
9.6
600
19.2
1200
1800
28.8
2000
32.0
2400
38.4
3600
57.6
76.8
4800
115.2
7200
9600
153.6
307.2
19200
=4.9152 MHZ
Actual
Fr8ll.~Hl!t
0.8
1.2
1.7598
2.152
2.4
4.8
9.6
19.2
28.7438
31.9168
38.4
57.8258
76.8
114.306
153.6
307.2
Percent
Error
-
-0.01
-
~
-
-0.19
-0.26
0.39
-0.77
-
Duty
Cycle
%
50/50
50/50
·
50/50
50150
50/50
50/50
50/50
·
·
·
50/50
50/50
50/50
50/50
50/50
Divisor
6144
4096
2793
2284
2048
1024
512
256
171
154
128
85
64
43
32
16
WD1943-05
TABLE 3.
D
a
a
a
a
0
0
a
a
1
1
1
1
1
1
1
1
·When
CRYSTAL FREQUENCY
Transmit/Receive
Address
C
B
0
a
Baud
Rate
Theoretical
A
I (32X Clock) Freq. (kHz)
1.6
0
50
1
2.4
75
a
a
0
1
a
110
3.52
1
1
134.5
4.304
a
1
a
a
150
4.8
1
1
6.4
a
200
1
1
9.6
a
300
)9.2
1
1
1
600
38.4
a
a
a
1200
1
57.6
a
a
1800
a
1
a
2400
76.8
a
1
1
3600
115.2
1
a
4800
153.6
0
1
0
1
7200
230.4
1
a
9600
307.2
1
19,200
614.4
1
1
1
the duty cycle IS not exactly 50% It IS 50% ± 10%
WD1943-06
330
=5.0688 MHZ
Actual
Fre~tkHzt
Percent
Error
1.6
2.4
3.52
4.303
4.8
6.4
9.6
19.2
38.4
57.6
76.8
115.2
153.6
230.4
298.16
633.6
2.941
3.125
.026
-
Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
·
·
50/50
50/50
Divisor
3168
2112
1440
1178
1056
792
528
264
132
88
66
44
33
22
17
8
APPLICATIONS INFORMATION
OPERATION WITH A CRYSTAL
The method that is easiest to implement in many systems
is method 1, the series resistor. The series resistor will
cause the D.C. level to shift up, but that does not cause a
problem since the OSC is triggered by an edge, as opposed
to a TTL level.
The WD1943 Baud Rate Generator may be driven by either a
crystal or TTL level clock. When using a crystal, the waveform
that appears at pins 1 (STALlEXT 1) and 18 (XTALlEXT 2)
does not conform to the normal TTL limits of VIL '" O.8V and
VIH .. 2.0V. Figure 1 illustrates a typical crystal waveform
when connected to a WD1943.
The 1943 Baud Rate Generator can save both board space
and cost in a communications system. By choosing either a
crystal or a TTL level clock, the user can minimize the logic
required to provide baud rate clocks in a given design.
Since the D. C. level of the waveform causes the least positive
point to typically be greater than O.8V, the WD1943 is
designed to look for an edge, as opposed to a TTL level. The
XTALlEXT logic triggers on a rising edge of typically 1V in
magnitude. This allows the use of a crystal without any additional components.
POWER LINE SPIKES
OPERATIONS WITH TTL LEVEL CLOCK
Voltage transients on the AC power line may appear on the
DC power output. If this possibility exists, it Is suggested
that a by-pass capacitor is used between + 5V and GND.
With clock frequencies in the area of 5 MHz, significant
overshoot and undershoot ("ringing") can appear at pins 1
and/or 18. The clock oscilator may, at times be triggered on
a rising edge of an overshoot or undershoot waveform,
causing the device to effectively "double· trigger." This
phenomenon may result as a twice expected baud rate, or
as an apparent device failure. Figure 2 shows a typical
waveform that exhibits the "ringing" problem.
CRYSTAL SPECIFICATIONS
User must specify termination (pin, wire, other)
Frequency - See Tables 1-6.
Type: Microprocessor Crystal
Temperature range O°C to + 70°C
Series resistance 50Q to 100Q
Series resonant to 100Q
Overall tolerance ± 0.01%
The design methods required to minimize ringing include
the fOllowing:
1. Minimize the P.C. trace length. At 5 MHz, each inch of
trace can add significantly to overshoot and undershoot.
2. Match impedances at both ends of the trace. For
example, a series resistor near the device may be
helpful.
3. A uniform impedance is important. This can be accomplished through the use of:
a parallel ground lines
b. evenly spaced ground lines crossing the trace on the
opposite side of PC board
c. an inner plane of ground, e.g., as in a four layered PC
board.
CRYSTAL MANUFACTURERS (Partial List)
American Time Products Div.
Frequency Control Products, Inc.
Woodside, New York 11377
Bliley Electric Co.
Erie, Pennsylvania 16508
M-tron Ind. Inc.
Yankton, South Dakota 57078
In the event that ringing exists on an already finished
board, several techniques can be used to reduce It. These
are:
Erie Frequency Control
Calisle, Pennsylvania 17013
1. Add a series resistor to match Impedance as shown in
Figure 3.
2. Add pull-uplpull-down resistor to match Impedance, as
shown in Figure 4.
3. Add a high speed diode to clamp undershoot, as shown
in FigureS.
Q-Malic Corporation
Costa Mesa, California 92626
331
+5,0
5.0
+4.0
4.0
VOLTS
VOLTS
+ 3,0
3,0
+2,0
20
+1.0
10
-1,0
2T
FIGURE 1.
3T
Time
Time
FIGURE 2.
TYPICAL CRYSTAL WAVEFORM
TYPICAL "RINGING" WAVEFORM
from TTL INPUT
18\---...J
Typical Values
A-1- ~-RT~33Q
WDl943
FIGURE 3.
SERIES RESISTOR TO MATCH IMPEDANCE
.5V
.5V
R1
R3
1
R4
1>----+---+-11
I
181-----'
fypical Values
R2
WDl943
FIGURE 4.
R1' ~~ -R3~-2.7K
A2
= A4 = 3.3K
PULL-UP/PULL-DOWN RESISTORS TO MATCH IMPEDANCE
:;.I'>----.
Il
-
DATA OUT
..(~
CPT
J L
V
I
MICROPROCESSOR DATA BUS
00-07
Figure 1.
Table 1.
SIMPLIFIED BLOCK DIAGRAM
WD9914 READ REGISTERS
ADDRESS
RS2 RS1 RSO
REGISTER NAME
DO
D1
D2
BIT ASSIGNMENT
D3
D4
D5
D6
D7
MAC
0
0
0
Int Status 0
INTO
INT1
BI
BO
ENO
SPAS
RLC
0
0
1
Int Status 1
GET
ERR
UNC
APT
OCAS
MA
SRO
IFC
0
0
1
0
Address Status
REM
LLO
ATN
LPAS
TPAS
LAOS
TAOS
ulpa
1
1
Bus Status
ATN
OAV
NOAC
NRFO
EOI
SRO
IFC
REN
1
0
1
0
0
1
1
0
Cmd Pass Thru
0108
0107
0106
0105
0104
0103
0102
0101
1
1
1
Oata In
0108
0107
0106
0105
0104
0103
0102
0101
1
,
,
'The W09914 host interface data lines will remain in the high impedance state when these register locations are
addressed. An Address Switch Register may therefore be included in the address space of the device at these
locations.
342
Table 2.
WD9914 WRITE REGISTERS
ADDRESS
RS2 RS1 RSO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
REGISTER NAME
Int MaskO
Int Mask 1
*
Auxiliary Cmd
0
1
0
1
0
1
0
1
Address
Serial Poll
Parallel Poll
Data Out
DO
01
GET
xx
cs
edpa
S8
PP8
0108
ERR
xx
xx
dal
rsvl
02
BIT ASSIGNMENT
04
03
END
05
06
07
SPAS
MA
xx
f2
MAC
IFC
xx
A3
RLC
SRQ
xx
f1
A2
BI
UNC
xx
xx
dat
BO
APT
xx
f4
A5
OCAS
xx
f3
A4
PP7
S6
PP6
S5
PP5
S4
PP4
S3
PP3
S2
PP2
S1
PP1
0107
0106
0105
0104
0103
0102
0101
to
A1
*This address is not decoded by the W09914. A write to this location will have no effect on the device, as if a
write had not occurred.
REGISTERS
Interrupt Mask and Status Registers 0
an external interrupt (["NT" Low) when it is set (Le., INT
= INT STATUS.INT MASK). The mask register is not
cleared by 'swrst' or the Hardware Reset pin (RESET)
and will power on in a random state. It must, there·
fore, be written to by the host MPU before 'swrst' is
cleared to avoid extraneous interrupts.
The Interrupt Mask and Interrupt Status registers
operate independently of each other. The status bits
will always be set when the appropriate events occur
regardless of the state of the corresponding mask bit.
All interrupt bits, with the exception of INTO and INT1
which are not storage bits, are edge triggered and are
set when the appropriate condition becomes true.
The storage bits are cleared immediately after the
corresponding Interrupt Status Register is read by
the host MPU. If an interrupt condition becomes true
during this read operation, then the event is stored.
The corresponding bit is set when the read operation
ends, hence no interrupts are lost. In addition to
being cleared by a read operation, the BO interrupt is
also cleared by writing to the Data Out Register, and
the BI interrupt is cleared by reading the Data In
Register.
The INTO and INT1 bits of the Interrupt Status
Register are not true status bits. INT1 will be true if
there are any unmasked interrupt status bits set to a
1 in Interrupt Status Register 1. INTO will be true if
any of bits 2·7 of Interrupt Status Register 0 are un·
masked and set to a 1. If either INT1 or INTO is true,
then the external interrupt pin (I NT) will be pulled low
provided that the Disable All Interrupts feature (dai)
has not been set.
The individual bits of Interrupt Status and Interrupt
mask Register 0 are described are in the following
paragraphs. The conditions which set these bits,
shown in parentheses, are given in terms of the state
diagrams. Each bit is set on the rising edge of the
condition shown.
The interrupt status bits are cleared and held in the 0
condition while Software Reset (swrst) is set.
The corresponding bit of the Interrupt mask register
must be set to a 1 if an interrupt status bit is to cause
INTERRUPT MASK/STATUS REGISTER 0
xx
xx
BI
BO
END
SPAS
RLC
MAC
INT
MASKO
INTO
INT1
BI
BO
END
SPAS
RLC
MAC
INT
STATUS 0
01
DO
02
03
04
05
06
NOTE: A 0 masks and a 1 unmasks the bits in the interrupt mask registers.
INT1
This will be a 1 when an unmasked sta·
tus bit in Interrupt Status Register 1 is set
to a 1.
INTO
This will be a 1 when any of bits 2·7 of
Interrupt Status Register 0 is unmasked
and set to a 1.
Byte In. A data byte has been received in
the Data In register. If the mask bit is not
BI
07
MPU BUS
set, then no interrupt is generated but a
RFD holdoff will still occur before the next
data byte is accepted. If the Shadow Hand·
shake feature is used, then this status bit
will not be set. This bit is cleared by
reading the Data In Register as well as
after Interrupt Status Register 0 has been
read. (Set On: ACOS1.LACS)
343
r
BO
Byte Out. This is set when the Data Out
Register is available to send a byte over
the GPIB. This byte may be either a command if the device is a controller or data if
the device is a talker. It is set when the device becomes an active talker or controller
but will not occur if the Data Out register
has been loaded with a byte which has not
been sent. Subsequently, it will occur after
each byte has been sent and the WD9914
returns to SGNS. This bit is cleared by
writing to the Data Out Register as well as
by reading Interrupt Status RegisterO. (Set
On: SGNS.CACS + SGNS.TACS.SHFS)
in the Remote/Local function. (Set On:
(LOCS-REMS) + (REMS-LOCS) + (LWLSRWLS) + (RWl.,S-LWLS)
MAC
Interrupt Mask and Status Registers 1
The operation of Interrupt Mask and Status Register 1
is similar to that of Interrupt Mask and Status Register 0 except that all bits are true storage bits. The
status bits are cleared only following the register
being read and by 'swrst'.
There is one distinct group of interrupts in this register:
GET, UNC, APT, DCAS, MA. These are all set in
response to commands received over the bus and if
unmasked, a Data Accepted (DAC) holdoff will occur
when the interrupt in question is set, It may be released
with a 'dacr' auxiliary command. This is further discussed in the Acceptor Handshake discussions.
NOTE:
When a controller addresses itself as a talker and
then goes to standby, there will be a momentary transition of the source handshake into SIDS before
TACS becomes true and it reenters SGNS. Under
these circumstances, the WD9914 is guaranteed to
givea BO interrupt on reentering 'SGNS'.
END
This indicates that a byte just received by
a listener was the last byte in a string, that
is, it was received with the EOI line true. It
is set at the same time as the BI interrupt.
(Set On: (ACDS1.LACS.EOI)
SPAS
This indicates that the WD9914 has
requested service via rsv1 or rsv2 (in the
Serial Poll Register or Auxiliary Command
Registe~ and has been polled in a serial
poll. It is set on the false transition of
STRS when the serial poll status byte is
sent. (Set On: STRS.SPAS.(APRS1 +
APRS2)
RLC
Remote/Local Change. This is set by any
transition between local and remote states
My Address Change. This indicates that a
command has been received from the
GPIB which has resulted in the addressed
state of the WD9914 to change. It will not
occur if secondary addressing is being
used, nor indicate that the WD9914 has
been readdressed on its other primary address. (Set On: ACDS1. (MTA.TADSUNT +
OTA.TADS + MLA.LADS + UN.LADS)
The mask bit of the APT Interrupt is further used in
the talker and listener functions. When the interrupt
is unmasked, the talker and listener functions of the
WD9914 implement the extended talker and extended listener functions of IEEE-488. Otherwise
these functions implement the talker and listener
functions of IEEE·488.
The individual bits of Interrupt Status and Interrupt
Mask Register 1 are described below. The conditions
which set these bits, shown in parentheses, are given
in terms of the state diagrams.
INTERRUPT MASK/STATUS REGISTER 1
GET
ERR
UNC
APT
CDAS
MA
SRO
IFC
INT
MASK 1
GET
ERR
UNC
APT
DCAS
MA
SRO
IFC
INT
STATUS 1
DO
D1
D2
D3
D4
D5
D6
D7
MPU
BUS
GET
This is set if a Group Execute Trigger
command is received_ A DAC holdoff occurs if the interrupt is unmasked. The TR
pin becomes high when this command is
received and persists high for the duration
of a DAC holdoff if one occurs. If the interrupt is masked, the TR pin becomes high
for approximately five clock cycles. (Set
On: GET.LADS.ACDS1)
ERR
Error. This is set if the source handshake
becomes active and finds that the NDAC
and NRFD lines are both high. This indicates that, for whatever reason, there are
no acceptors on the bus. (Set On: SERS)
UNC
344
Unrecognized Command. This is set if a
command has been received which has no
meaning to the WD9914. Unrecognized addressed commands will only cause this interrupt if the device is LADS except for
TCT which will only interrupt in TADS.
Secondary commands will only cause this
interrupt if the 'pts' auxiliary command has
been set previously. A DAC holdoff will occur if this interrupt is unmasked which
effectively enables the command pass
through feature. Unrecognized commands
may be inspected in the Command Pass
Through Register before this holdoff is released. (Set On: ACDS1. (UCG.[LD. SPE.
SPD.DCL + ACG.GET.GTL.SCD.TCT.
LADS + TCT.TADS + SCG.pts)
APT
DCAS
Address Pass Through. Unmasking this
interrupt enables secondary addressing. It
is set if a secondary command is received
provided that the last primary command
received was a primary talk or listen address of the WD9914. A DAC holdoff will
occur and the secondary address may be
read from the Command Pass Through
Register. The holdoff may be released by a
'dacr' auxiliary command and the 'cs' bit of
the Auxiliary Command Register is used
to indicate that a valid (cs = 1) or an invalid (cs = 0) secondary has been identified by the host MPU. (Set On: ACDS1.
SCG.(LPAS + TPAS)
Device Clear Active State. This is set when
a device clear command (DCL) is received
or when a selected device clear (SDC) is re-
SRO
MA
IFC
ceived with the WD9914 in LADS. This will
cause a DAC holdoff if unmasked. (Set On:
ACDS1.(DCL + SDC.LADS)
Service Request. This is provided for the
benefit of the controller which should execute a serial poll in response to this interrupt. It is set when the SRO line becomes
true. (Set On: SRO.(CIDS + CADS)
My Address. This is set when the WD9914
recognizes its primary talk or listen address. A DAC holdoff will occur if this is
unmasked. (Set On: (MLA + MTA).SPMS.
aptmk)
Interface Clear. This is provided for the
benefit of devices which are not the System Controller. It is set when the IFC line
becomes true and indicates that the
WD9914 has been returned to an idle state.
If the device is the System Controller, then
the IFC interrupt is not set. (Set On: IFCIN)
Address Status Register
REM
LLO
ATN
LPAS
TPAS
LADS
TAOS
ulpa
DO
D1
02
D3
04
05
06
07
MPU
BUS
REM
The device is in the remote state
LLO
Local lockout is in operation
ATN
The attention line is low (true) on the bus
LPAS
WD9914 is in the listener primary addressed state
TPAS
WD9914 is the talker primary addressed state
LADS (or LACS) The device is addressed to listen
TAOS (orTACS) The device is addressed to talk
This bit shows the LSB of the last address recognized by the WD9914.
ulpa
Address Register
edpa
dal
dat
A5
A4
A3
A2
A1
DO
01
02
D3
04
D5
D6
07
edpa
dal
dat
A5-A1
Enable dual primary addressing mode
Disable listener function
Disable talker function
Primary address of the WD9914.
into these bits. Often this will be read from an Address Switch Register.
The 'edpa' bit is used to enable the dual addressing
mode of the WD9914. It causes the LSB of the address to be ignored by the address comparator giving
two consecutive primary addresses for the device.
The address by which the WD9914 was selected is
indicated by the 'ulpa' bit of the Address Status
Register.
The Address Register is not cleared by 'swrst' or
hardware reset.
Bits A5-A1 of this register contain the primary address of the device (denoted AAAAA in Table 19).
IEEE-488 1975/78 does not allow a device to be assigned the value 11111 for bits A5-A 1. When 'swrst' is
true at power-up or if set by the host MPU, the
WD9914 is held in an idle state. During this time the
host MPU may load the primary address of the device
Auxiliary Command Register
cs
DO
f4-fO
cs
F2
F1
FO
05
04
01
02
03
Auxiliary command select (see Table 3)
Clear or set the feature (where applicable)
D6
07
xx
xx
F4
F3
345
Auxiliary commands are used to enable and disable
most of the selectable features of the WD9914 and to
initiate many of the actions of the device. The desired
feature is selected by writing a byte to this register
with the appropriate value in bits f4-fO. These values
are given in Table 3.
All the clear/set auxiliary commands are cleared by
the hardware RESET pin except 'swrst,' which is set
true by RESET.
The force group execute trigger (fget) and return to
local (rtl) auxiliary cornmands have a clear/set mode
of operation and a pulsed mode of operation. They
behave as normal clear/set features, but if they are
written with 'cs' = '0' when they have not been previously set, then they will pulse true. Using the 'fget'
command in this manner will produce a pulse of approximately 1 JAS at the TR pin (with a 5 MHz clock).
The 'rtl' command used in this way will cause a return
to one of the local states (assuming local lockout is
not in force) but the WD9914 may reenter the remote
state next time the listen address occurs.
The 'cs' bit is used in most cases when the feature
selected by f4-fO is of the clear/set type. The feature
is enabled if 'cs' = '1' and disabled if 'cs' = '0'. The
holdoff on all data (hdfa) feature is an example of
such a feature. Other auxiliary commands initiate an
action of the WD9914, such as release RFD holdoff
(rhdf). In most cases, the 'cs' bit is unused and ignored by these commands.
Table 3_
AUXILIARY COMMANDS
cis
f4
f3
f2
f1
fO
MNEMONIC
0/1
0/1
na
0
0
0
0
0
0
0
0
0
0
0
1
0
1
Software reset
Release DAC holdoff
0
swrst
dacr
rhdf
0/1
0
0
0
1
1
hdfa
Holdoff on all data
0/1
0
0
0
0
0
0
1
Holdoff on EOI only
0
1
1
hdfe
na
0/1
0
0
0
0
1
1
0
1
New byte available false
Force group execute trigger
1
0
1
1
nbaf
fget
0
rti
feoi
Return to local
Send EOI with next byte
1
1
0
0
0
1
0
1
Ion
ton
Listen only
Talk only
0
1
1
0
0
1
0
1
gts
Go to standby
Take control asynchronously
Take control synchronously
1
1
0
1
0
1
0/1
na
0/1
0/1
0
0
0
na
na
na
0
0
0
1
1
1
0/1
0/1
0
0
1
1
1
1
1
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
1
0
0
0
1
0/1
na
na
0/1
na
0/1
0/1
0/1
0/1
1
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
1
0
FEATURES
Release RFD hold off
tca
tcs
rpp
sic
sre
I
Request parallel poll
Send interface clear
Send remote enable
Request control
rqc
ric
Release control
Diable all interrupts
dai
pts
stdl
shdw
vstdl
rsv2
I
Pass through next secondary
ShortTI settling time
Shadow handshake
Very short T1 delay
Request Service Bit 2
tion should include writing the address of the device
into the Address Register, writing mask values into
the Interrupt Mask Registers and selecting the desired features in the Auxiliary Command Register and
Address Register. After this, 'swrst' may be cleared at
which point the device becomes logicaly existent on
the GPIB. The Serial Poll Register and Parallel Poll
Registers may also be written in this period but this
DESCRIPTION OF AUXILIARY COMMANDS
Software Reset (swrst) 0/1 xxOOOOO
Setting this command causes the WD9914 to be returned to a known idle state during which it will not
take part in any activity on the GPIB. This auxiliary
command is set by the power-on RESET and the chip
should be configured while 'swrst' is set. Configura-
346
is not necessary if there is no status to report as both
of these are cleared by the power-on RESET pin.
Table 4 lists the various states and other conditions
forced by 'swrst'.
Table 4_
Set New Byte Available False (nbaf)naxx001 01
If a talker is interrupted before the byte just stored in
the data out register is sent over the interface, this
byte will normally be transmitted as soon as the ATN
line returns to the false state. If, as a result of the interrupt, this byte is no longer required, its transmission may be suppressed using the 'nbat' command.
SOFTWARE RESET CONDITIONS
MNEMONIC
SIDS
AIDS
DESCRIPTION
Source idle state
Force Group Execute Trigger (fget)0/1 xx00110
The state of the TR output from the WD9914 is affected when this command is executed. If the CS bit
is zero, the line is pulsed high for approximately 5
clock cycles (1 !ls at 5 MHz). If CS is one, the TR line
goes high until 'fget' is sent with CS equal to zero. No
interrupts or handshakes are initiated.
TIDS
Acceptor idle state
Talker idle state
TPAS
LIDS
LPAS
NPRS
Talker primary idle state
Listener idle state
Listener primary state
Negative poll response state
LOCS
CIDS
SPIS
Local state
Controller idle state
PPSS
Parallel poll standby state
Return to Local (rtl)O/1 xx00111
Provided the local lockout (LLO) has ~en enabled, the remote/local status bit is reset, and an interrupt is generated (if enabled to inform the host
microprocessor that it should respond to the front
panel controls. If the CS bit is set to one the 'rtl' command must be cleared (CS = 0) before the device is
able to return to remote control. If CS is set to zero,
the device may return to remote without first clearing
'rtl'.
Serial poll idle state
ADHS
DAC holdoff state
AEHS
SHFS
RFD holdoff on end state
Source holdoff state
EN IS
END idle state
Force End or Identify (feoQnaxx01 000
This command causes the EOI message to be sent
with the next data byte. The EOlline is then reset.
NOTES: 1. See State Diagram Implementation for definition of above.
2. All interrupt status bits are held in a 0 state,
but interrupt mask bits are not affected.
Listen Only (lon)O/1 xx01 001
The listener state is activated until the command is
sent with CS set to 0 or until deactivated by a bus
command.
Release DAC Holdoff (dacr)O/1xx00001
The Data Accepted (DAC) holdoff allows time for the
host microprocessor to respond to unrecognized
commands, secondary addresses, and device trigger
or device clear commands. The holdoff is released by
the MPU when the required action has been taken.
Normally the command is loaded with the clear/set
bit at zero; however, when used with the address pass
through feature CS is set to one if the secondary address was valid or to zero if invalid see APT interrupt.
Talk Only (ton)O/1 xx01 01 0
The talker state is activated until the command is
sent with CS set to 0 or until deactivated by a bus
command.
NOTE:
'ton' and 'Ion' are included for use in systems without
a controller. However, where the WD9914 is being
used as a controller, it utilizes the 'Ion' and 'ton' functions to set itself up as a Iistener or talker, respectively. Care must therefore be taken to ensure these
functions are reset if sending UN L or OTA.
Release RFD Holdoff (rhdf)naxx00010
Any Ready For Data (RFD) holdoff caused by a 'hdfa'
or'hdfe' is released.
Go to Standby (gts)naxx01011
Holdoff on All Data (hdfa)O/1 xx00011
A Ready For Data (RFD) holdoff is caused on every
data byte until the command is loaded with CS set to
zero. The handshake must be completed after each
byte has been received by the MPU using the 'rhdf'
command.
Issued by the controller in charge to set the ATN line
false.
Take Control Synchronously (tcs)naxx011 01
Control is again taken by the controller in charge, and
ATN is asserted. If the controller is not a true listener,
the shadow handshake command must be used to
monitor the handshake lines so that the WD9914 is
synchronous with the talkerllisteners and only sends
ATN true at the end of byte transfer. This ensures that
no data is lost or corrupted.
Holdoff on End (hdfe)O/1xx00100
A RFD holdoff will occur when an end of data string
message (EOI tru with ATN false) is received over the
interface. This holdoff must be released using 'rhdt'.
347
via the Command Pass Through Register. This would
be the parallel poll enable (PPE), which is read by the
microprocessor.
Request Parallel Poll (rpp)0/1xx01110
This is executed by the controller in charge to send
the parallel poll command over the interface (the
WD9914 must be in the Controller Active State so
that the Attention line is asserted). The poll is completed by reading the Command Pass Through Register to obtain the status bits, then sending 'rpp' with
the CS bit at zero.
SetT1 Delay(std1)1xx10101
The T1 delay time can be set to 6 clock cycles (1.2 lAS
at 5 MHz) if this command is sent with the CS bit at
one. The TI delay time is 11 clock cycles (2.2 lAS at 5
MHz) following a power-on reset or if the command is
sent with CS set to zero.
Take Control Asynchronously (tca)naxx011 00
This command is used by the controller in charge to
set the attention line true and to gain control of the
interface. The command is executed immediately
and data corruption or loss may occur if a talkerl
listener is in the process of transferring a data byte.
Shadow Handshake (shdw)0/1 xx1 0110
This feature enables the controller in charge to carry
out the listener handshake without participating in a
data transfer. The Data Accepted line (DAC) is pulled
true a maximum of 3 clock cycles after Data Valid
(DAV) is received, and Not Ready For Data (NRFD) is
allowed to go false as soon as DAV is removed.
The shadow handshake function allows the 'tcs'
command to be synchronized with the Acceptor Not
Ready State (ANRS) so that ATN can be re-asserted
without causing the loss or corruption of data byte.
The END interrupt can also be received and causes a
RFD holdoff to be generated.
Send Interface clear (sic)0/1 xx01111
The IFC line is set true when this command is sent
with CS set to one. This must only be sent by the system controller and should be reset (CS = 0) after the
IEEE minimum time for IFC has elapsed (100 lAs). The
system controller is put into the controller active
state.
Send Remote Enable (sre)0/1 xx1 0000
Issued by the system controller to set the REN line
true and send the remote enable message over the interface, REN is set false by sending 'sre' with CS at
zero.
Very Short T1 Delay (vstd1)0/1 xx1 0111
If this feature is enabled, the GPIB settling time (T1)
will be reduced to 3 clock cycles (600 ns at 5 MHz) on
the second and subsequent data bytes when ATN is
false. Otherwise, the GPIB settling time is determined by the std1 feature.
Request Control (rqc)naxx10001
When the TCT command has been recognized via the
unidentified command pass through, this command
is sent by the MPU. The WD9914 waits for the ATN
line to go false and then enters the controller active
state (CACS).
Request Service Bit 2 (rsv2)0/1 xx11 000
The rsv2 bit performs the same function as the rsv1
bit but provides a means of requesting service which
is independent of the Serial Poll Register.
This allows minor updates to be made to the Serial
Poll Register without affecting the state of the request service.
In addition, rsv2 is cleared when the serial poll status
byte is sent to the controller during a serial poll. It is
therefore used in situations where a service request
is simply a request from an instrument for the controller to poll its status. As soon as this happens, rsv2
is cleared since the reason for requesting service has
been satisfied. This eliminates the burden of clearing
the bit from the host MPU but also guarantees that
rsv2 is cleared before another serial poll can occur. If
this were not so, there would be a possibility of a
second status byte being sent with the RQS message true, which could result in confusion for the
controller. (rsv2 is cleared on: SPAS.(APRS1 +
APRS2).STRS).
Release Control (ric)naxx10010
This command is used after TCT has been sent and
handshake completed to release the ATN line and
pass control to another device.
Disable All Interrupts (dai)O/1 xx1 0011
The INT line is disabled, but the interrupt registers
and any holdoffs selected are not affected.
Pass Through Next Secondary (pts)naxx1 01 00
This feature may be used to carry out a remote configuration of a parallel poll. The parallel poll configure
command (PPC) is passed through the WD9914 as an
unrecognized addressed command and is identified
by the MPU. The Opts' command is loaded, and the
next byte received by the WD9914 is passed through
348
Bus Status Register
ATN
OAV
NRFO
NOAC
EOI
03
04
01
DO
02
The host MPU may examine the status of the GPIB
management lines at the time of reading.
SRO
IFC
REN
07
MPUBUS
05
06
The IFC bit of this register does not indicate a true
value if the device is a system controller using the
'sic' auxiliary command.
Serial Poll Register
S8
rsv1
S6
S5
S4
S3
S2
S1
0108
0107
0106
0105
0104
0103
0102
0101
DO
01
02
03
04
05
06
07
GPIB
MPUBUS
GPIB, and the controller typically responds by setting
up a serial poll to obtain the status of all instruments
on the bus that may require service. When the
W09914 is addressed to send its status byte, SRO is
set false, and the status byte is sent with the ROS
message true on 0107. The rsv1 bit must then be
cleared and set true again if service is to be requested a second time. The SPAS interrupt is set immediately following the status byte being sent.
S8, S6-S0 Device status
rsv1
Request service bit 1
Bits S8, S6-S1 of this register are sent out over the
GPIB when the device is addressed during a serial
poll. They are cleared by a hardware reset but not by
'swrst' and may therefore be set up during configuration of the chip. These bits are fully double buffered
and if the register is written to while the device is
addressed during a serial poll (serial poll active state,
SPAS), the value written is saved, and these bits are
updated when SPAS is terminated.
The rsv1 bit provides an input to the service request
function of the W09914 and is used to instruct this to
request that the controller service the device. When
rsv1 is set true, the SRO line is pulled true on the
The rev1 bit is also cleared by the hardware reset pin
but not by 'swrst'. It is not double-buffered but the
service request function comprehends changes in
the state of rsv1 while the device is in SPAS. The
Serial Poll Register may therefore be written to any
time.
Command Pass Through Register
,
0108
DO
,
0107
01
,
0106
02
,
0105
03
,
0104
0103
0102
0101
04
05
06
07
This provides a means of directly inspecting the
GPIB data lines (010(8-1)). It has no storage and
should only be used when the data lines are known
to be in a steady state such as will occur during a
OAC holdoff or in CPWS during a parallel poll. It is
used to read unrecognized commands and secondar-
GPIB
MPUBUS
ies following a UNC interrupt or to read secondary
addresses following an APT interrupt. In addition, an
active controller uses this register to read the results
of a parallel poll at least 21ls after setting the 'rpp'
auxiliary command.
Parallel Poll Register
PP8
PP7
PP6
PP5
PP4
PP3
PP2
PP1
0108
0107
0106
0105
0104
0103
0102
0101
DO
01
02
03
04
When a controller initiates a parallel poll, the contents of this register are presented to the GPIB data
lines. If all bits of the register are cleared, then none
of the lines 010(8-1) will be pulled low during a parallel poll which corresponds to the Parallel Poll Idle
State (PPIS) of IEEE-488. If it is desired to participate
in a parallel poll, then the bit corresponding to the
desired parallel poll response is set to a 1.
GPIB
05
06
07
MPU BUS
held until the parallel poll ends, at which point the
register is updated. This permits the host MPU to update the parallel poll response completely asynchronously to the GPIB.
If this register is cleared by the hardware RESET pin
but not by 'swrst,' it may be loaded while the chip is
being configured with 'swrst' set.
The Parallel Poll Register is fully double buffered. If it
is written to during a parallel poll, the new value is
349
Data In Register
I
DI08
I
DI07
DI06
DI05
DI04
DO
D1
D2
D3
D4
This register is used to hold data received by the
WD9914 when it is a listener. It is loaded during Ac·
cept Data State (ACDS1) and, following this, an RFD
holdoff will occur. This will normally be released
when the byte is read by the host MPU, but if the
Holdoff On All Data (hdfa) feature is selected, this
holdoff must be released by the 'rhdf' auxiliary
command.
DI03
DI02
DI01
GPIB
D5
D7
MPU BUS
D6
If the Holdoff On End (hdfe) feature is selected, the
RFD holdoff will be released by reading the Data In
Register. But if the EOlline is true when the byte is reo
ceived, reading the data byte will not release the
holdoff and rhdf must be used.
As the Data In Register is loaded, the BI interrupt is
set. The END interrupt is set simultaneously if the
byte is accompanied by a true EOlline.
Data Out Register
I
DI08
I
DI07
DI06
DI05
DI04
DO
D1
D2
D3
D4
The Data Out register is used by a controller or talker
for sending interface messages and device depen·
dent messages. When the WD9914 enters the Talker
Active State (TACS) or the Controller Active State
(CACS), the contents of the Data Out Register are
presented to the GPIB data lines (DI0(8·1)), and the
byte is sent over the bus under the control of the
Source Handshake. Each time a byte is written, the
source handshake is enabled, and the byte is sent. If
the handshake is interrupted before the byte can be
sent, then it will be sent next time the Source Hand·
shake becomes active unless a new byte available
false (nbat) auxiliary command is written. This has
the effect of clearing an unsent byte from the Data
Out Register, and although the register itself is not
cleared the WD9914 behaves as if it had not been
loaded.
DI03
D5
DI02
DI01
D6
D7
GPIB
MPU BUS
NOTE:
The sense of DBIN is inverted for DMA operation.
At the end of a DMA read from memory sequence,
the ACCRO will be left low (also BO bit set). It may be
necessary for the 'mpu' to clear this in some circum·
stances, e.g., starting DMA write to memory
sequence.
In DMA it is recommended that the MA interrupt be
unmasked to prevent errors due to interrupted data
streams.
if DMA is not being utilized, the ACCGR signal must
be held high. In this case, the ACCRO signal can be
used as a separate interrupt line for BO and BI. This
allows faster 'mpu' transfers to take place as it is not
necessary to read the interrupt register to find the
cause of the interrupt. Figure 2 shows a typical DMA
configuration.
Each time the source handshake becomes active and
there is no unsent byte in the Data Out Register, a BO
interrupt will occur informing the host MPU that the
Data Out Register is available for use.
The Data In Register and Data Out Register operate
independently. The Data Out Register is not double
buffered, and its contents are output directly to the
data lines of the GPIB.
TERMINAL ASSIGNMENTS AND FUNCTIONS
The IEEE·488 standard uses the negative logic convention for the GPIB lines. The FALSE state (0) is represented by a high voltage (>2.0 V); the TRUE state (1) is
represented by a low voltage «0.8 V). The GPIB termi·
nations of the WD9914 are in agreement with this con·
vention. For example, if Data Valid is true (1), the DAV
line is pulled low by the device. These terminations are
connected to the bus via noninverting buffers to obtain
the correct signal polarity.
DIRECT MEMORY ACCESS
The WD9914 can operate in DMA using the ACCRO
(DMA request) and ACCGR (DMA grant) DMA hand·
shake lines. The operation is automatic within the
WD9914 and needs no 'mpu' configuration.
The ACCRO signal is set by (BO.CACS + BI) and can
therefore not be used by a controller while ATN is
asserted. It is reset by 'swrst' readin data in register,
writing to the data out register and ACCGR. It is not
cleared by reading interrupt status registerO.
Note that the terminations on the microprocessor
side of the device are in positive logiC (true state (1)
= high voltage: false state (0) = low voltage). This is
in agreement with the logic convention used by most
microprocessors. Thus if:
DO(MSB)
D7(LSB)
o
o \ 1
is written into the data out register, it will appear as:
If using DMA, the internal CE and addressing is dis·
abled by the ACCGR signal going low and ACCGR
will automatically address either the data in register
(DBIN
0) or the data out register (DBIN
1).
=
I
DI08(MSB)
=
\
DI01(LSB)
\ HIGHjLOwILOWIHIGH\LOW\HIGH\HIGHILOW \
on the IEE·488 D10 lines.
350
=E
ACCRQ
c
(0
DMA CONTROL LOGIC
~
.tao
ACCGR
CE
.-1.
DBIN
~
WE
':::.
WE
A
MPU
1\
'I
r-r/
B
U
S
A
~
ADDRESS
DECODE
IY
I---
,;
RS2
0
IEEE
STD 488
INTERFACE
BUS
~
V
1\
RS1
B
U
F
F
E
R
S
r
A
00-07
CE
r--
J
\
j
CONT
I~
~
GPIB
DATA
DI01-DI08
TE
SEMICONDUCTOR
MEMORY
DATA BUS
1\
I
V
WD9914
~~
to.
iI
DBIN
A
D
D
R
E
S
S
GPIB
MANAGEMENT /
RSO
\
B
U
F
F
E
R
S
W
ADDRESS
SWITCHES
ENABLE
I
Figure 2.
DMA CONFIGURATION
TRANSCEIVER CONNECTIONS
There are three linear transceivers designed to work
with the WD9914: The SN75160, SN75161, and
SN75162. Data sheets for these are included as Appendix C. Figure 3 shows the possible transceiver
connections. Note that there is a corresponding pin·
out between the WD9914 and the transceivers. This
allows the whole GPIB interface to be laid out in a
very small area of printed circuit board.
The SN75160 is a 20 pin device used to buffer the
IEEE·488 data lines (DI0(8-1)) in all applications. The
direction of the buffers is controlled by the Talk En·
able (TE) output of WD9914. This active high signal
becomes true whenever there is an interface function
of the WD9914 not sending the NUL message on
DI0(8-1), that is, when the device is in TACS, CACS,
SPAS, or PPAS_ The Pull-Up Enable (PE) input of the
SN75160 is an active high input which selects whether the 'DI0(8·1), lines are driven by open collector or
push/pull buffers. A push/pull buffer is required if
faster data rates are required and the 'stdl' and/or the
'vstdl' features are used. Open collectors must be
used if parallel polling is being used in a particular
GPIB environment. If only one of these features is desired the PE input may be hardwired otherwise it
must be derived from ATN and EIO, as shown in
Figure 3.
The SN75161 is a 20-pin device used to buffer the
IEEE·488 management lines. It may be used for a
talkerllistener device or for a controller which does
not pass control. The direction of the handshake line
buffers NRFD, NDAC, DAV are again controlled by
the TE signal. However, the SRQ, ATN, REN, and IFC
buffers are controlled by the DC input of the
SN75161, which connects to the Controller Active
(CONl) output of the WD9914. CONT becomes low
whenever the WD9914 is an active controller, that is,
when it is not in CIDS or CADS. The SN75161 also includes the logic necessary to control the direction of
the EOI buffer. This is dependent on the TE signal
when ATN is false (high) and the DC signal when ATN
is true (low).
351
L
I
WE
DBIN
I
cations including devices which pass control. The
SN75162 has a separate pin to control the direction
The SN75162 is a 22-pin device which may be used to
buffer the IEEE-488 management lines in all appliVCCr
1/4 SN74LS32
HIGH SPEEO
PARALLE
L P 0 ' 1 'L ___
b
~
PE
GNO
--
EJ~ ffi
~:~~IIII~
1
------
-----
ACCRO
ACCGR
CE
WE
OBIN
RSO
RSl
RS2
INT
07
WD9914
06
05
04
03
02
01
00
0
RESET
VSS
0101
0102
0103
0104
0105
0106
0107
0108
VCC
rl
0103
0104
0105
0106
0107
0108
CONT
-
~
0101
0102
0103
0104
0105
0106
0107
0108
TE I-1
~
SRO
ATN
EOI
OAV
NRFO
NOAC
SN75161
10
GNOiSRO
SRO
ATN
ATN
EOI
EOI
OAV
NRFO
NOAC
NOAC
IFC
IFC
REN
REN
TE I---i
VCC
20
1
~ oc
~~~~
r-TE
I
I1
21
20
SN75160
GNO
~~~o
VCC
..
HIGHSPEEI
PARALLEL
1/4 SN74LS32
POL~ i..
GNO
-
-
-
~
1
----------
-20
VCC-
ACCRO
ACCGR
CE
WE
OBIN
RSO
RSl
RS2
INT
07
06
05
04
03
02
01
00
0
RESET
VSS
WD9914
1
<-J-TR0101
01020103
0104
0105
0106
0107
0108
SN75160
10
GNO0101
0102
0103
0104
0105
0106
0107
0108
TE
- VCC
20
1
PE
0101
jlllr~!i~
~"~
1
C~~6
~
ATN
EOI
OAV
NRFO
NMC
IFC
REN
TE -
-
I1
SN75162
11
GNO ISRO
ATN
ATN
OC
~SRO
~
I
w
21
-22
OAV
NRFO
NOAC
IFC
REN
NC
VCC
VCCT
SYSTEM
CONTROLLER
NON·SYSTEM
CONTROLLER
GNO
1
~
Figure 3.
TRANSCEIVER CONNECTIONS
352
w
OAV
NRFO
NOAC
IFC
REN
TE
,......
sc I-1
of the REN and IFC buffers, but is otherwise identical
to the SN75161 in all other respects. This input is the
System Controller input (SC) which may be hardwired
or switchable to determine whether or not the instrument in question is a system controller or not. Note
that a device which has its buffers configured as a
non-system controller should never use the 'sic' and
'sre' auxiliary commands.
with its recommended transceivers meets aIiIEE-488
maximum timing requirements. If the WD9914 is
used with other transceivers, then it must be ensured
that these requirements are still met.
AUXILIARY COMMANDS
There are two basic types of commands
implemented in the auxiliary command regiater. immediate execute and clear/set.
The clear/set commands are used to enable and
disable the various features of the WD9914. The particular feature is selected by the code on fO-f4 and it is
set or cleared according to the value on the cs bit.
For the purposes of the state diagrams, the mnemonic of a clear/set command simply represents its
current state.
STATE DIAGRAM IMPLEMENTATION
This section presents the state diagrams for the
WD9914.
Where equivalent, the names of WD9914 states are
the same as those of IEEE-488. In some cases,
IEEE-488 states have been divided, for example,
ACDS of the IEEE-488 has been split into ACDS1 and
ACDS2. The convention of lower case characters for
local messages and upper case for remote messages
and interface states is retained.
State diagrams with remote message outputs are
supplemented with tables. T is used to represent a
true output and F a false output. Parentheses denote
a passive output; otherwise, it is active. The outputs
shown are the values presented to the bus and assume the use of the SN75160 and SN75161 or
SN75162 transceivers or their logical equivalents.
The symbol (NUL) associated with DIO(1-8) indicates
that each of these lines is sent passive false by the
function in question.
The immediate execute auxiliary commands remain
active for the duration of a strobe signal after the
auxiliary command register has been written to. This
is represented in the form of a state diagram in
Figure 5. Note that writes to the auxiliary command
register must be spaced by at least five clock cycles.
For the purposes of the remaining state diagrams,
the immediate execute commands are represented
as the mnemonic gated by the auxiliary command
strobe state (AXSS).
The clear/set bit of the auxiliary command register is
used by several of the immediate execute commands, for example, 'dacr' uses it to differentiate between valid and not valid secondary addresses when
releasing a DAC holdoff on a secondary address. The
'Ion' and 'ton' auxiliary commands are also
considered immediate execute.
The 'fget' and 'rtl' auxiliary commands are both immediate execute and clear/set. They may be cleared
or set in the normal way, but if they are cleared when
they are already in the false state, they will pulse true
for the duration ofAXSS. In the following state diagrams, however, these are simply included in their
clear/set form.
NOTE:
An arrow into a state with no state as its origin
represents a transition from every other state on the
diagram. Note, however, that this does not imply that
all exit conditions from the destination state are overridden. If such an entry condition is true and,
simultaneously, an exit condition is true then this represents an illegal situation and should be avoided.
Such situations will not occur in normal operation of
the device.
No maximum timings are discussed. The WD9914
waux
waux
RST
Figure 4.
WD9914 AUXILIARY COMMAND STATE DIAGRAM
353
i
Table 5.
:ec
CD
CD
......
.bo
AUXILIARY COMMAND STATE DIAGRAM MNEMONICS
MESSAGES
waux
tc(O)
STATES
write to auxiliary command register
=
AXIS
AXWS
AXSS
clock cycle time
auxiliary command register idle state
=
=
auxiliary command write state
auxiliary command strobe state
ACDS1 and, if the interrupts are unmasked, a DAC
holdoff will occur. The interrupts concerned are GET,
MA, DCAS, UCG, and APT. This is represented in the
state diagram by the signal SAHF which becomes
true when one of the above interrupts is set if it is un·
masked. It persists for the duration of ACDS1. This
event is stored by causing the ADHS to become ac·
tive which inhibits the transition from ACDS2 to
AWNS. ADHS is cleared by 'dacr.' Table 19 shows the
response of the WD9914 to the various bus
commands.
ACCEPTOR HANDSHAKE
The WD9914 acceptor handshake is shown in Figure
5. The main variation from IEEE·488 to note is that the
device remains in AIDS while the controller function
is in CACS. The WD9914, therefore, does not monitor
the commands which it sends over the bus and this
places some restrictions on the user.
The accept data state of IEEE·488 (ACDS) is divided
into two states. The first, (ACDS1) is used to strobe
data into the Data In Register or to sequence the de·
coding of commands from the bus. All interrupts gen·
erated by the acceptor handshake (GET, MA, MAC,
DCAS, APT, UCG, BI, and END) are generated by this
state. The second (ACDS2) is used as a holding state
where the device will remain in the event of a DAC
holdoff.
If a GET command is received in ACDS1, then the TR
pin will be set high. This high condition persists
throughout ACDS1 and ACDS2, which means that if a
DAC hold off occurs, the TR pin will remain high until
the holdoff is released by a 'dacr' auxiliary command.
Two additional state diagrams are included to record
Certain of the commands will cause interrupts in
swrst.(ATN.(CIDS + CADS)
+ ATN.(LADS x LACS)
CwAs.DAV.
+ ANHS.AEHS.
rdin.rhdf.AXSS)
~
swrst + (ATN.CIDS.CADS)
(ATN.LADS.LACS)
daer.AXSS
'".'--E[B
DAV
te(O)
SWrSI.SAHF.ACDS1
(rhdf.AXSS) + shdw + (rdin.hdfa)
swrst
ATN.5t e(0) +
ATN.te(O)
swrst.ATN.ACDS1.Sfidw
rhdf.AXSS
Qb
swrst~
swrst.A TN.ACDS 1. hdfe.EOI
Figure 5.
WD9914 ACCEPTOR HANDSHAKE STATE DIAGRAM
354
the type of data received in ACDS1 when ATN is
false. ANHS indicates that a data byte has been received and that an RFD holdoff should be caused
before the next data byte is accepted. The holdoff
may be released by reading the Data In Register
Table 6.
unless the 'hdfa' feature is enabled in which case
'rhdf' must be used. AEHS shows that the last data
byte was accepted with the EOI message true and
the 'hdfe' feature set. This will cause an RFD holdoff
which can only be released by 'rhdf.'
ACCEPTOR HANDSHAKE MNEMONICS
STATES
MESSAGES
=
=
=
=
=
=
swrst
dacr
rhdf
shdw
rdin
hdfe
software reset
DAC release
release RFD holdoff
AIDS
ANRS
ACRS
shadow handshake
read data in register
ACDS1
ACDS2
enable RFD holdoff after EN 0 messages
received
enable RFD holdoff on all data
AWNS
ADHS
=
=
=
=
=
acceptor idle state
acceptor not ready state
acceptor ready state
acceptor wait for new cycle state
accept data holdoff state
data valid
ANHS
AEHS
end or identify state
CWAS
=
=
=
=
=
accept data state 1
accept data state 2
EOI
=
=
=
=
RFD
=
ready for data
AXSS
=
DAC
=
data accepted
LADS
=
listener addressed state (listener function)
SAHF
=
=
set accept data holdoff state
clock cycle time
LACS
CIDS
=
=
CADS
=
listener active state (listener function)
controller idle state (controller function)
controller addressed state (controller
function)
hdfa
ATN
DAV
tc(O)
Table 7.
attention
acceptor not ready holdoff state
acceptor not ready holdoff after 'END'
controller wait for ANRS state (controller function)
auxiliary command strobe state (auxiliary command register)
ACCEPTOR HANDSHAKE MESSAGE OUTPUTS
REMOTE MESSAGES SENT
STATE
RFD
DAC
AIDS
(l)
F
(l)
F
(l)
ANRS
ACRS
ACDS1
OTHER ACTIONS
F
F
F
ACDS2
F
F
AWNS
F
(l)
ATN False:
-
ATN true:
-
TR
-
355
data entered into Data In Register
BI interrupt generated
end interrupt generated if EOI is true.
commands decoded
command related interrupts set
sahf set if command requires a DAC
holdoff
- TR pin set true if GET message is
received
- 'pts' feature cleared after UNC interrupt set
pin set true if GET command was
received in ACDS1
not dependent on SHFS during a serial poll, that is,
while SPAS is active. By separately recording the
availability of a byte in the Data Out Register, a talker
sending data may be interrupted for a serial poll without risk of a byte being lost.
SOURCE HANDSHAKE
The WD9914 source handshake state diagram is
shown in Figure 6. IEEE-488 states SIWS and SWNS
have been removed. These record the false then true
transition of 'nba' (new byte available) as the old data
byte is removed and a new data byte is made ready.
Instead the WD9914 uses a separate state (SHFS) to
record the availability of a data byte in the Data Out
Register. This state is exited when a byte is written to
the Data Out Register which enables the transition
from SGNS to SDYS and the subsequent transmission of the byte. The SHFS is reentered as the byte is
sent in STRS, but if the handshake is interrupted
before this, then the fact that the byte has not been
sent is recorded until the source handshake again becomes active. If, however, the byte in the data out register is to be disregarded, then 'nbaf' may be used to
return the device to SHFS.
The status byte in the Serial Poll Register is contino
ually available. The transition from SGNS to SDYS is
The additional state SERS is included to detect an
error condition on the bus. This will be entered when
the source handshake tries to send a byte but finds
both the NRFD and NDAG lines false at the same
time. This condition will normally indicate for a controller that there are no devices powered up on the
bus, or for a talker that there are no devices
addressed to listen on the bus.
The state VSTS will be entered after the first data
byte of a talker has been sent if the 'vstdl' feature is
enabled. This enables a very short bus settling time
(4tc(O)) for all subsequent bytes until ATN next becomes true. The WD9914 will not use the short bus
settling time when it is an active controller.
RFD.DAC.
(12t c(0) + std
8t c(0) + VSTS.
4t c(0)
(ATN.CACS) + (ATN.(TACS +
SPAS)) + swrst
5wrst.wdot
~
swrst
DAC
nbaf.AXSS + STRS.SPAS
ATN.vstd1.STRS
e:=B
ATN.vstd1
Figure 6.
Table 8.
WD9914 SOURCE HANDSHAKE STATE DIAGRAM
SOURCE HANDSHAKE MNEMONICS
MESSAGES
swrst
nbaf
=
=
STATES
software reset
new byte available false
SIDS
SGNS
wdot
--
write to the data out register
SDYS
stdl
vstdl
ATN
RFD
DAG
=
=
=
=
=
=
enable short bus settling time
enable very short bus settling time
attention
ready for data
SERS
data accepted
clock cycle time
TAGS
tc(O)
STRS
SHFS
VSTS
source idle state
=
=
=
=
=
=
356
source error state
source transfer state
source holdoff state
very short bus settling time state
talker active state (talker function)
controller active state (controller
function)
serial poll active state (talker function)
GAGS
SPAS
AXSS
source generate state
source delay state
=
auxiliary command strobe state (auxiliary command registe~
Table 9.
SOURCE HANDSHAKE MESSAGE OUTPUTS
STATE
REMOTE MESSAGES SENT
DAV
SIDS
SGNS
(F)
F
SDYS
SERS
STRS
F
F
T
OTHER ACTIONS
BO interrupt and ACCRa set
true if SHFS is false and
SPAS is not true
ERR interrupt set true
TALKER AND LISTENER FUNCTIONS
Figures 7 and 8 show the WD9914 listener and talker
state diagrams, which serve the purpose of the listener and talker or extended listener and extended
talker functions of IEEE-488, depending on the state
of the APT interrupt mask bit.
The WD9914 does not recognize secondary addresses on-chip and these must be passed through
to the host MPU for verification. Secondary addressing is enabled by unmasking the APT interrupt.
A secondary address will cause this interrupt if the
last primary command received was a primary ad·
dress of the device, that is, it is in TPAS or LPAS. A
DAC holdoff will also occur. The host MPU must
respond to the interrupt by reading the secondary
from the Command Pass Through Register and iden·
tifying it as being valid or not valid. The holdoff may
then be released with a 'dacr' auxiliary command, the
sense of the 'es' bit being used to indicate a valid
(cs = 1) or not valid (cs = 0) secondary. If a valid
secondary address is indicated then the WD9914 will
enter TADS or LADS depending on whether it is in
TPAS or LPAS.
The 'Ion' and 'ton' auxiliary commands together with
the clear/set bit (cs) have a direct influence on the appropriate state diagrams. Therefore, although they
appear as ordinary clear/set auxiliary commands,
they can be effectively cleared by other bus events.
For example, if a WD9914 addresses itself as a listener via the 'Ion' command it may be returned to LIDS
by an UNL command from the bus at a later time.
The 'Ion' and 'ton' auxiliary commands are used to
implement two features of IEEE·488. First, talk only
and listen only are used in situations where there is
no active controller on the bus. Note that the 'Ion'
and 'ton' commands are linked with these features to
indicate to the user that these commands are not
enabled by CAS as are 'Itn' and 'Iun' of IEEE·488.
Second, the 'Ion' and 'ton' auxiliary commands are
used by an active controller to address itself. IEEE·
488 provides for a controller to address itself to listen
via the 'Itn' and 'Iun' message but there is no corres·
ponding message for the talker. Hence, when a con·
troller addresses itself to talk via 'ton,' it must send
its talk address over the bus and similarly, if it sends
another talk address over the bus then it must un·
address itself by writing 'ton' false.
LAF
swrst + dal + sic + IFelN +
10n.cs.AXSS
TAF + UNl.ACDS1
MLA.ACDS1
LAF
swrst
PCG.MLA.ACDS1
Figure 7.
= daI.lFCIN.
sic.(MLA.aptmk.
ACDS1 + LPAS.aptmk.
dacr.cs.AXSS + Ion.
cs.AXSS)
WD9914 LISTENER STATE DIAGRAM
357
A separate state diagram is included to control the
sending of the END message of IEEE-488. If the 'feoi'
auxiliary command is written followed by loading a
byte into the Data Out Register, the WD9914 will
enter ERAS, and the EOI line will be asserted as
'010(8-1)' begin to change. The function will enter
ENAS as soon as the source handshake begins to
send this byte, and EOI will be released when the
Data Out Register is next loaded. If it is desired to
send EOI true with the next byte as well, then 'feoi'
may be written before the Data Out Register returns
the device to ERAS.
When the WD9914 enters SPAS, the contents of the
serial poll register are sampled and presented on
010(8-1). These will remain unchanged until SPAS is
exited. The source handshake will, however, send
this status byte as many times as the controller will
accept it.
The intemallFC signal of the WD9914 (IFCIN) is suppressed when the device itself is sending IFC in
order to simplify implementation of the controller
function. Therefore, the send interface clear (SiC)
auxiliary command is included with IFCIN to return
the talker and listener functions to their idle states
and allow a system controller to clear its own
Interface.
ATN.SPMS
TAF
swrst + dat + sic +
ton.cs.AXSS +
IFCIN
ATN
(TPAS.aptmk.dacr.
cs.AXISS) + LAF +
OTA.ACDSI
MTA.ACDSI
ATN.SPMS
PCG.MTA.ACDSI
swrst
TAF
= dat.sic.IFCIN.(MTA.aptmk.ACDSl +
TPAS.aptmk.dacr.cs.AXSS + ton.CS.
AXSS)
=::e
IFCIN.SPE.ACDSI
r::r:-
LAF: See Figure 7.
~~+CIDS+CADS
IFCIN+
swrst
feoLAXSS
SDYS.S"PMS
swrst+
nbaf.AXSS
wdot
wdot
feoi.AXSS
SDYS.SPMS
Figure 8.
WD9914 TALKER STATE DIAGRAM
358
Table 10.
TALKER AND LISTENER MNEMONICS
STATES
MESSAGES
swrst
dal
dat
sic
Ion
ton
cs
dacr
aptmk
nbaf
feoi
wdot
ATN
IFCIN
EOI
PCG
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
TIDS
=
=
=
=
=
=
talker idle state
clear/set bit of the auxiliary command
register
TADS
=
talker addressed state
release 'DAC' holdoff
TACS
=
talker active state
address pass through interrupt mask
SPAS
=
=
serial poll active state
=
=
=
serial poll mode state
software reset
LIDS
disable listener
LADS
disable talker
LACS
send interface clear
LPIS
listen only
LPAS
talk only
new byte available false
SPIS
force 'EOI'
SPMS
write to the Data Out Register
TPIS
attention
TPAS
internal interface clear message (a
debounced signal, suppressed by 'sic')
ENIS
end or identify
ENRS
ERAS
primary command group
=
=
=
=
=
=
=
listener idle state
listener addressed state
listener active state
listener primary idle state
listener primary addressed state
serial poll idle state
talker primary idle state
talker primary addressed state
end idle state
end ready state
end ready and active state
my listen address
ENAS
my talk address
SDYS
other talk address
SPE
=
=
serial poll enable
CIDS
CADS
SPD
=
serial poll disable
ACDS1
=
accept data state 1 (acceptor hand·
shake)
UNL
=
unlisten
AXSS
=
auxiliary command strobe state (auxili·
ary command registe~
PCG
=
primary command group
MLA
MTA
OTA
Table 11.
end active state
source delay state (source handshake)
controller idle state (controller function)
controller addressed state (controller
function)
TALKER FUNCTION MESSAGE OUTPUTS
REMOTE MESSAGES SENT
STATE
QUALIFIER
TIDS
EOI
(F)
(F)
(F)
(NUL)
F
DATA OUT REG
TACS
ENIS.ENRS
TACS
ENAS.ERAS
(F)
(F)
(F)
SPAS
NPRS.SRQS
SPAS
APRS1.APRS2
TADS
OTHER ACTIONS
010(8·1)
RQS
(NUL)
T
DATA OUT REG
F
F
SERIAL POLL REG
T
F
SERIAL POLL REG
SERVICE REQUEST FUNCTION
Register, the second is the auxiliary command 'rsv2.'
These are simply ORed together to provide an input
to the service request function, and, in any particular
application, only one would normally be used, the
other being left in its hardware reset state.
Figure 9 shows the state diagram for the WD9914 ser·
vice request function. The device has two means of
implementing the request service (rsv) local message
of IEEE·488: the first, 'rsv1,' is bit 7 of the Serial Poll
359
The affirmative poll response state (APRS) of
IEEE-488 is split into two states on the WD9914 for
the following reason: Consider the case where a device has requested service, has been serial polled,
and then wishes to request service again. The host
MPU must clear the 'rsv' message and then set it true
again. Now suppose this temporary false condition
happens within one occurrence of SPAS. If the service request function has been implemented exactly
as per IEEE-488, it will not be recognized, and SRQ
will not be asserted a second time. Therefore, 'rsv'
may only be cleared when the device is known not to
be in SPAS, which can only happen if it is cleared as
a consequence of some pre-arranged action of the
controller. This action would normally be a part of the
service routine executed by the controller as a response to the request for service. For example, if service was requested by an instrument which had
some data to send for processing or to a printing device then 'rsv' could be cleared when it is addressed
to talk and send its data over the bus.
swrst.(rsv1
For many applications, the fact that the device has
been serial polled after requesting service is considered sufficient response from the controller. The
'rsv' local message therefore simply becomes a request for the controller to read its serial poll status
byte. It is then desirable to be able to clear and reassert 'rsv' at any time after the serial poll status byte
has been polled and the SPAS interrupt set. The
WD9914 is able to record a false transition of 'rsv1' or
'rsv2' by moving from APRS1 to APRS2 even if the device is in SPAS. This makes the above approach to
serial polling possible.
To further support this approach, the 'rsv2' auxiliary
command is automatically cleared when the serial
poll status byte is polled, ensuring that 'rsv2' is
cleared before a second serial poll can occur. If this
were not the case, then the same status byte might
be polled twice by the controller with the RQS bit
true, which may indicate that two reasons for requiring service have arisen.
+ rsv2).SPAS
swrst
(rsvi
+ rsv2).SPAS
SPAS
(rsv1
Figure 9.
+ rsv2)
SERVICE REQUEST STATE DIAGRAM
The WD9914 will only send one serial poll status byte
during each active period of SPAS. However, it will
send this status byte as many times as the controller
is prepared to accept it. Therefore, the controller
Table 12.
should only read the status byte once per serial poll;
otherwise, each time a status byte is sent with the
RQS message true, the SPAS interrupt will be generated and 'rsv2' will be cleared.
SERVICE REQUEST MNEMONICS
STATES
MESSAGES
swrst
srv1
rsv2
=
--
=
software reset
request service 1 (bit 7 of serial poll
register)
request service 2 (auxiliary command
register)
360
NPRS
=
negative poll response state
SRQS
=
service request state
APRS1
APRS2
SPAS
=
=
=
affirmative poll state 1
affirmative poll state 2
serial poll active state (talker function)
Table 13.
SERVICE REQUEST MESSAGE OUTPUTS
STATE
REMOTE MESSAGES SENT
SRQ
NPRS
(F)
OTHER ACTIONS
SROS
T
APRS1
(F)
-
rsv2 cleared if in SPAS and STRS
SPAS interrupt set if in SPAS when STRS is
exited
APRS2
(F)
-
same as APRS1
masked, the device will enter one of the remote
states in response to its listen address, but if
secondary addressing is enabled, then this will not
happen until 'dacr' is written with 'cs' true in
response to a valid secondary address. In addition,
the transition to one of the remote states will occur if
'Ion' is used to address the device to listen.
REMOTE/LOCAL FUNCTION
The WD9914 remote local state diagram is shown in
Figure 10. If differs little from that of IEEE-488.
The complete listener function (LAF) is used to effect
the transition from LOCS to REMS or from LWLS to
RWLS. This means that if the APT interrupt is
RENIN7tfLAF
RENIN.
LLO
ACDS1
GTL.LADS.ACDS1
r1l.(LLO.ACDS1)
+
LLO.
ACDS1
LAF
LAF: See Figure 7.
GTL.LADS.ACDS
Figure 10.
Table 14.
WD9914 REMOTE LOCAL STATE DIAGRAM
REMOTE/LOCAL MNEMONICS
MESSAGES
swrst
rtl
RENIN
GTL
LLO
=
=
=
=
=
STATES
software reset
LOCS
return to local
REMS
internal remote
(debounced)
enable
=
=
local state
remote state
message
go to local
LWLS
local lockout
LADS
=
=
=
ACDS1
=
RWLS
361
remote with lockout state
local with lockout state
listener addressed
function)
state
(listene
accept data state 1 (acceptor handshake)
dary (pts) auxiliary command should be written
before releasing the DAC holdoff. This will cause the
next command received to also set a UNC interrupt if
it is a secondary command. The secondary command
will be either the parallel poll enable command (PPE)
or the parallel poll disable command (PPO) and
should be read from the Command Pass Through
Register and identified. If it is the PPE command,
then the attendant bits (S, P1, P2, P3) should be
extracted and stored by the host MPU. The S bit
should then be matched against the individual status
of the instrument (represented by 'ist'), and if they are
the same, the bit corresponding to the parallel poll response, specified by P1, P2, P3, should be set true in
the Parallel Poll Register. If this is not the case, then
the Parallel Poll Register should be cleared if it is not
already clear. After this, each time the individual
status of the device changes, the 'ist' should again
be matched against the S bit and the Parallel Poll
Register updated accordingly until PPD or PPU is
received.
If a PPO command is passed through after the 'pts'
feature has been written, the Parallel Poll Register
should be cleared before the OAC holdoff is released.
The PPC command that precedes PPD is an address
command; it is a means of eliminating individual
members of a parallel poll. The parallel unconfigure
command is treated by the W09914 as an unrecognized universal command. When it is passed through,
the host MPU should clear its Parallel Poll Register
before releasing the DAC holdoff. This command will
clear all members of a parallel poll.
PARALLEL POLL FUNCTION
The parallel poll function of the W09914 only
nominally supports logically-configured parallel poll.
With a suitable software package, remotely-configured parallel poll may also be easily implemented.
The state diagram is shown in Figure 11.
When the EOI and ATN lines become true simultaneously (the Identify message), the contents of the
Parallel Poll Register are output to 010(8-1). If parallel
poll is to be used in a particular bus environment,
then the Pull-Up Enable (PE) input of the SN75160
must be held low so that the DI0(8-1) are driven by
open collector buffers. Parallel Poll, occurring when
the Parallel Poll Register is in the hardware reset condition of all zeros, will result in none of 010(8-1) being
pulled low. This corresponds to the parallel poll idle
state (PPIS). If it is desired to participate in a parallel
poll, then the bit corresponding to the desired parallel poll response is set true. This implements the
parallel poll standby state (PPSS), and, when the Identify message becomes true, the appropriate line of
DI0(8-1) is pulled low. This is equivalent to the
parallel poll active state (PPAS). Only one bit of the
parallel Poll Register should be set true at once.
Remotely Configured Parallel Poll
The parallel poll configure command (PPC) is treated
by the W09914 as an unrecognized addressed command. It is passed through when the WD9914 is in
LADS. If an instrument is to be remotely configured
for parallel poll, then the pass through next secon-
swrst.ATN. EOI.(CI DS + CADS)
swrst
Figure 11.
Table 15.
WD9914 PARALLEL POLL STATE DIAGRAM
PARALLEL POLL MNEMONICS
MESSAGES
swrst
ATN
EOI
=
=
=
STATES
software reset
attention
end or identify
PPSS
PPAS
CIDS
CADS
362
=
=
=
=
parallel poll standby state
parallel poll active state
controller idle state (controller function)
controller addressed state (controller
function)
Table 16.
PARALLEL POLL MESSAGE OUTPUTS
REMOTE MESSAGES SENT
OTHER ACTIONS
STATE
010(8·1)
PPSS
PPSS
(NUL)
PARALLEL POLL REG'
'If there is a true bit in the Parallel Poll Register, it must be sent active; any false bit must be sent passive.
When the controller is active, it uses 'ton' or 'Ion' to
address and unaddress itself. IEEE-488 provides for
the controller to locally address itself to listen, but
there is no corresponding local message for the talk·
er. The WD9914 should always accompany a 'ton'
auxiliary command with 'cs' true with its own talk
address or an UNT command sent over the bus. Simi·
larly, if the WD9914 sends the talk address of another
device over the bus, it should ensure that it is in TIDS
by writing the 'ton' auxiliary command false.
CONTROLLER FUNCTION
The controller function of the WD9914 is greatly sim·
plified compared with that of IEEE·488. It relies heavily on software support but, with suitable software, it
enables all subsets of the controller function to be
implemented. With this -approach the controller logic
is reduced to a small proportion of the chip area
which means that the device may be economically
used in situations where a talker/listener only is
required.
Figure 12 shows the controller function state diagram. With suitable software, it will perform the full
controller function, as described in the IEEE·488A
1980 supplement to the IEEE·488 1978. It therefore includes the additional state CSHS, which allows time
for DAV to be recognized false by all devices on the
bus before ATN is asserted. The 'tcs' local message
is implemented by an immediate execute auxiliary
command. The state CWAS is therefore added to
record the occurrence of this command until the ac·
ceptor handshake enters ANRS and the device can
enter CSHS. The 'tca' auxiliary command also causes
entry into CSHS although IEEE·488A 1980 allows it to
move directly from CSBS to CSWS. This is done for
convenience of implementation and results in the
'tca' auxiliary command taking an extra 1.6 microseconds to assert ATN.
The delay between CSWS and CAWS is slightly less
than specified in IEEE·488A 1980 but the total time
taken in moving from CSWS to CACS is still greater
than the specified minimum.
The Controller Parallel Poll State (CPPS) is not included on the WD9914. To conduct a parallel poll, a
WD9914 based controller must set the 'rpp' clear/set
auxiliary command true when it is in CACS, moving it
to CPWS which sends EOI true. The host MPU must
then wait 2 microseconds before reading back the
parallel poll responses via the Command Pass
Through Register. The 'rpp' auxiliary command can
then be cleared, EOI will go false, and the parallel poll
is complete. The host MPU will receive a BO interrupt
as soon as the WD9914 reenters CACS and the
source handshake becomes active.
Passing Control
As Figure 12 shows, the controller transfer state
(CTRS) of IEEE-488 is not present, and all transitions
associated with the TCT command have been reo
moved. Instead, two immediate execute auxiliary
commands are included. Request control (rqc) will
cause a transition from CIDS to CADS, and the reo
lease control command (ric) will return the function
to CIDS. The TCT command is treated similarly to an
unrecognized addressed command but will cause a
UNC interrupt if the device is in TADS.
Figure 13 is a representation of the sequence of
events involved in passing control from one WD9914
based device to another. The device passing control
must initially ensure that it is not in TADS; then it
should send out the talk address of the device to receive control. The receiving device will enter TADS,
and after any DAC holdoff has been released, the
host MPU of the device passing control will set a BO
interrupt indicating that it may then send the TCT
command. The TCT command will cause a UNC inter·
rupt to the host MPU of the receiving device, and also
a DAC holdoff will occur. The host MPU of the
receiving device must examine its Command Pass
Through Register, and upon identifying TCT, should
write the auxiliary command 'rqc' to put its WD9914
into CADS. The receiving device may then release
DAC with a 'dacr' auxiliary command causing anoth·
er BO interrupt at the device passing control. This
indicates that the 'ric' auxiliary command may then
be used by the host MPU of the device passing con·
trol to return its WD9914 to CIDS and allowing ATN to
go false. The receiving device then enters CACS,
asserts ATN, and its host MPU gets a BO interrupt as
the source handshake becomes active. The passing
of control is complete.
Controller Self Addressing
The acceptor handshake does not operate when the
controller is active. This means commands being
sent are not monitored, and special precautions are
required as a consequence of this when addressing
devices and when passing control.
363
sic
swrst+IFCIN+
rlc.AXSS
sre
SIC+
rqc.AXSS
sre
gts.AXSS.STRs.SDvS
Figure 12. WD9914 CONTROLLER STATE DIAGRAMS
Table 17.
CONTROLLER FUNCTION MNEMONICS
MESSAGES
swrst
sic
sre
rqc
ric
gts
STATES
=
software reset
send interface clear
CIDS
CADS
=
send remote enable
request control
release control
CACS
go to standby
CSWS
take control synchronously
take control asynchronously
CAWS
=
=
=
=
CSBS
CSHS
rpp
=
=
=
IFCIN
=
internal interface clear message (a
debounced signal which is suppressed
if 'sic' is true)
SDYS
ATN
=
attention
STRS
tc(O)
=
clock cycle time
AXSS
tcs
tca
CPWS
ANRS
request parallel poll
LWAS
364
=
=
=
=
=
=
controller idle state
controller addressed state
controller active state
controller standby state
controller standby hold state
controller synchronous wait state
=
controller active wait state
=
controller parallel poll wait state
acceptor not ready state (acceptor
handshake)
=
=
=
=
=
source delay state (source handshake)
source transfer state (source hand·
shake)
auxiliary command strobe state (auxili·
ary command registe~
controller wait for ANRS state
Table 18.
CONTROLLER FUNCTION MESSAGE OUTPUTS
REMOTE MESSAGE SENT
STATE
ATN
EOI
010(8·1)
CIOS
(F)
(F)
(F)
(F)
(NUL)
CADS
CACS
T
F
DATA OUT REG
CSBS
F
(F)
(NUL)
CWAS
F
F
(F)
(F)
(NUL)
CSHS
CSWS
T
F
(NUL)
CAWS
T
F
(NUL)
CPWS
T
T
(NUL)
OTHER ACTIONS
(NUL)
Data Out Reg. may contain any of the commands in Table 19
(NUL)
010(8-1) may be read via the Command Pass Through Register
REMOTE MESSAGES SENT
STATE
IFC
OTHER ACTIONS
SIIS'
(F)
SIIS
F
SIAS
T
Internal interface
clear message IF·
CIN
is held false
REMOTE MESSAGES SENT
STATE
REN
SRIS'
(F)
SRIS
F
SRAS
T
OTHER ACTIONS
• Buffers not configured for a system controller; otherwise, buffers are configured for system controller.
IFC are both debounced to prevent noise on these
lines from causing permanent state changes on the
WD9914. In addition, the intemal interface clear sig·
nal (IFCIN) is held false if the WD9914 is sending IFC.
Figure 12 shows the reason for this. If the device is
not a system controller, then the occurence of IFC
will return the controller function to CIOS. If, however,
the device is a system controller, when it asserts
IFC and is in CIDS, the 'sic' auxiliary command will
cause it to enter CADS. As IFCIN is suppressed, it
will not be forced back into CIDS, and there will be no
conflict.
The REN and IFC outputs of the WD9914 are con·
trolled by the auxiliary commands 'sre' and ·sic.'
These should never be used by the host MPU of a device unless it is the system controller. As may be
seen from Figure 14, the REN and IFC outputs of the
WD9914 are open drains with internal pull·ups. This
means that the outputs are capable of driving the in·
puts of the buffers if the device is a system controller.
If not, the buffers will drive into the REN and IFC pins
and override the pull·ups. Hence, no direction control
is required.
The false transition of REN and the true transition of
365
System Controller
:ec
CD
CD
.....
The WD9914 has no on-chip means of determining
whether or not it is the system controller. Instead,
this is determined by the software and by the configuration of the buffers to the IEEE-488 bus.
~
RECEIVES CONTROL
PASSES CONTROL
A
/
CPU
ton.Cs
II
~
A
/
"
WD9914
WD9914
II
"
CPU
CLEARS
TADS
TAG
MA
wdot
80
~
ENTERS
SGNS
wdot
-I
SENDS
TCT
I.I
DAC
TCT
RELEASE
ACDS
HOLD
~I
RECEIVES
TCT
ENTERS
CADS
ENTERS
CIDS
dacr
~
une
I
-
~
rqe
RELEASE
ACDS
HOLD
dacr
ATN
ENTERS
CACS&
SGNS
BO
ATN
Figure 13.
rept
DAC
BO
ric
L-
PASSING CONTROL BETWEEN WD9914
366
r
Vee
REW
Vee
-,
I - - - -....Osre
I
I
I
Vss
I
I
IFe'
I- - - - - 1--.....- - - - - 0 sic
D---o
RENIN
Vss
DELAY L-
D - - - O IFelN
*The REN and IFe signals are at the pins of the WD9914 and are therefore
negative logic signals. The remaining signals are conventional
positive logic signals.
Figure 14.
IFe AND REN PINS
367
Table 19.
MULTILINE INTERFACE MESSAGES
DAC(3)
HOlDOFF
SYMBOL
010
8·1
Addressed Command
Group
Device Clear
ACG
DCl
OOOXXXX
XOO10100
AC
UC
DCAS
Yes
Group Execute Trigger
GET
XOOO1000
AC
GET
Yes
Go To local
GTl
XOOOOOO1
AC
RlC
No
listen Address Group
LAG
X01XXXXX
AD
-
local Lockout
My Listen Address
LLO
XOO10001
UC
None
No
MLA
X01AAAAA
AD
MA,MAC,RLC
MAOnly
My Talk Address
MTA
X10AAAAA
AD
MA,MAC
MAOnly
4
My Secondary Address
MSA
X11SSSSS
SE
APT
Yes
Other Secondary Address
OSA
SCG.MSA-
SE
APT
Yes
5,6
6,7
Other Talk Address
OTA
TAG.MTA-
AD
MAC
No
Primary Command Group
PCG
ACG + UCG +
LAG + TAG
-
-
Parallel Poll Configure
PPC
XOOOO101
AC
UNC
Yes
8
SE
SE
UNC
Yes
9,10
UNC
Yes
9,11
UC
UNC
Yes
12
COMMAND
Parallel Poll Enable
PPE
Parallel Poll Disable
PPD
INTERRUPT
CLASS
X110SPPP
X111DDDD
(1,2)
-
-
PPU
XOO10101
Secondary Command
Group
SCG
X11XXXXX
SE
Selected Device Clear
Serial Poll Disable
SOC
SPD
XOOOO100
XOO11001
AC
UC
DCAS
Serial Poll Enable
SPE
XOO11000
UC
None
No
Take Control
TCT
XOOO1001
AC
UNC
Yes
Talk Address Group
TAG
X10XXXXX
AD
-
-
Unlisten
UNL
X0111111
AD
MAC
Untalk
UNT
X1011111
AD
-
Universal Command Group
UCG
XOO1XXXX
UC
None
Classes:
UC
AC
AD
SE
universal command
addressed command
address
secondary command
Symbols:
0
logical zero (high level on
GPIB)
logical one (lOW level on GPIB)
don't care (received message)
x
None
14
-
Parallel Poll Unconfigure
-
NOTE
4,14
Yes
No
13
No
No
NOTES:
4. AAAAA represents the primary address of a
device.
1. Interrupts listed are as a direct consequence of
the command received. They are set during
ACDS1 and will cause the INT pin to be pulled
low if unmasked.
5. SSSSS represents the secondary address of a
device.
6. Secondary addresses are handled via address
pass through (APT interrupt). The host MPU
should respond by writing the 'dacr' auxiliary
command with 'cs' false.
2. The addressed commands will only cause their
corresponding interrupt if the device is in LADS
with the exception of TCT.
3. A DAC holdoff will only be caused if the
corresponding interrupt is unmasked.
7. If OSA is passed through via the APT interrupt,
368
11. DODD specifies don't care bits which must be
sent as zeros but need not be decoded by the
host MPU of the receiving devices.
12. PPU is not recognized by the WD9914 and will
cause a UNC interrupt.
13. TCT is not recognized directly by the WD9914. It
will cause a UNC interrupt when the device is in
TAOS.
14. RLC is set if MLA or GTL causes an appropriate
transition in the Remote/Local function.
the host MPU should respond by writing the
'dacr' auxiliary command with 'cs' false.
8. PPC is not recognized by the WD9914 and is
therefore treated as an unrecognized addressed
command.
9. PPE and PPD are secondary commands. These
may be passed through to the host MPU using
the 'pts' auxiliary command. When the PPC
command is received the 'pts' auxiliary
command should be written. PPE or PPD will
then cause an APT interrupt.
10. SPPP specifies the sense bit, and the desired
parallel poll response is a remotely configured
parallel poll.
TYPICAL SEQUENCES OF EVENTS FOR THE CONTROLLER
I ,---I II~
U
L...---cP-----I
C0-----lNT
II~
S.H-----I'
OTH----JER
sic
sic
"" ...>- - -
I
t..~
_---IL..-_
ATN
BO
wdot
RFD.DAC
T1
DAV
DAC
BO
Figure 15.
CONTROLLER TAKING CONTROL
369
CPU
DAC
BO
gts
CSBS
ATN
RFD
DAV
RFD
BI
200 ns
DAC
DAV
rdin
·ASSUME NO
HOLDOFF
CSBS
LACS
SIDS
RFD
DAV
BI
(+END)
tes
DAC
1',
rdin
I
....
DAV
>- - - -
r-=~:;---+---t--'::::=f~----1
DAC
ATN
LADS
CAWS
RFD
+
SGNS
DAC
BO
·CWAS INHIBITS ANRS ~ ACRS, SO RDIN CAN OCCUR BEFORE ATN IS SET.
Figure 16.
CONTROLLER AS A LISTENER (GOING TO STANDBy)
370
CPU
II
II
CO NT
II
S.H.
TALKER
II
OTHER
=E
C
CO
CO
.....
.1::0
DAC
60
ATN
SGNS
60
wdot
Tl
RFD.DAC
STRS
DAV
DAC
SGNS
60
10
ATN
TADS
SIDS
SGNS
60
wdot
RFD.DAC
DAC
SGNS
60
·MOMENTARY TRANSITION FOLLOWING 60 INTERRUPT IS GUARANTEED ON THE WD9914.
Figure 17.
CONTROLLER AS A TALKER (GOING TO A STANDBy)
371
CPU
OTHER
S.H.
CO NT
-
, ...
--<.
..
I
~
OAC
BO
rpp
lOY
Figure 18.
CONTROLLER PARALLEL POLLING
*Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions beyond those indicated in the "Recommended Operating Conditions" section of this
specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods
may affect device reliability.
WD9914 ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS OVER
OPERATING FREE-AIR TEMPERATURE RANGE
(Unless otherwise noted)*
Supply Voltage, VCC (see Note 1) .... - 0.3V to 20V
All Input and Output Voltages .. . . . .. - 0.3V to 20V
Continuous Power Dissipation ............. 0.8 W
Operating Free-Air Temperature Range. O·C to 70·C
Storage Temperature Range. . . . .. - 55·C to 150·C
NOTE 1:
Under absolute maximum ratings voltage values are
with respect to VSS.
RECOMMENDED OPERATING CONDITIONS
MIN
4.75
Supply voltage, VCC
Supply voltage, VSS
NOM
MAX
UNIT
5
5.25
V
V
0
High-level input voltage, VIH
2
Low-level input voltage, VIL
Vss-D·3
0
Operating free-air temperature, TA
372
VCC+1
0.8
70
V
V
·C
ELECTRICAL CHARACTERISTICS OVER FULL RANGE OF RECOMMENDED OPERATING CONDITIONS
PARAMETER
VOH
=
-4oo1J.A
IOH
IOH - - 100llA
= 2mA
= 2VtoVCC
VOL
Low-level output voltage
IOL
II
Input current (any input)
VI
ICC
Ci
t
TEST CONDITIONS
High-level output voltage
Except REN,IFC,INT
REN,IFc only
MIN
TYPt
2.4
2.2
VSS
VCC supply current
=
Input capacitance
(any input)
All typical values are atTA
f
1 MHz, unmeasured
pinsatOV
MAX
UNIT
VCC
VCC
0.4
V
V
±10
150
IlA
mA
15
pF
MAX
UNIT
ns
V
= 25°C and nominal voltage.
TIMING CHARACTERISTICS AND REQUIREMENTS
Timing characteristics and requirements are given in
the following and relevant timing diagrams are
shown in Figure 10 through Figure 27.
Clock and Host Interface Timing Requirements Over Full Range of Operating Conditions
PARAMETER
MIN
TYP
tc(O)
Clock cycle time
200
2000
tw(OH)
Clock high pulse width
100
1955
tw(OL)
Clock low pulse width
45
ns
ns
tsu(AD)
Address setup time
0
ns
tsu(DBIN)
DBIN setup time
0
ns
tsu(CE)
CE setup time
100
ns
tsu(WE)
WE setup time
0
ns
tw(WE)
WE low pulse width
80
ns
tsu(DA)
Data setup time
60
ns
th(DA)
Data hold time
0
ns
th(AD)
Address hold time
0
ns
th(DBIN)
DBIN hold time
0
ns
th(CE)
CE hold time
tsu(GR)
ACCGR setup time
th(GR)
ACCGR hold time
80
ns
100
ns
80
ns
Host Interface Timing Characteristics Over Full Range of Operating Conditions
PARAMETER
MIN
TYP
MAX
UNIT
ta(CE)
Access time from CE
150
ns
ta(DBIN)
Access time from DBIN
150
ns
tsu(AD)
Address setup time to CE
tz(DBIN)
Hi-Z time from DBIN
50
100
ns
tz(CE)
Hi-Z time from CE
50
100
ns
ta(GR)
Access time from ACCGR
tz(GR)
Hi-Z time from ACCGR
td(GRlRO)
Delay of ACCRO high from ACCGR
ns
0
50
373
150
ns
100
ns
100
ns
Source Handshake Timing Characteristics Over Full Range of Operating Conditions (see Note 1)
PARAMETER,
TEST CONDITIONS
MIN
MAX
UNIT
12(0)t
8(O)t
4(0)f
121Q)t+310
8(O)f+310
4(0)f+310
ns
ns
ns
140
ns
Delay of BO interrupt from BO interrupt unmasked
'DACtrue
300
ns
td4
Delay of ACCRQ DAC true
300
ns
td5
Delay of DAV false from
DACtrue
160
ns
td1
Delay of DAV true from end Normal T 1 (see Note 2)
of write operation to data I short T1 (see Note 2)
out register
Very short 11 (see Note 2)
td2
Delay of valid GPIB data
lines from end of write
cycle
td3
NOTES:
is false if the 'vstd1' feature is set. A slightly longer
bus settling time takes place if 'std1' is set unless
there is a very short bus settling time. In all other
instances, a normal bus settling time occurs.
1. The timing of the source handshake is the same
whether ATN is true or false, i.e., whether the
device is in TACS, CACS, or SPAS.
2. A very short bus settling time (T1) occurs on the
second and subsequent data byte sent when ATN
Acceptor Handshake Timing Characteristics Over Full Range of Operating Conditions
TEST CONDITIONS
PARAMETER
td6
Delay of BI interrupt from
DAVtrue
BI interrupt unmarked ATN
false device is in LACS
td7
Delay of ACCRa from
DAVtrue
ATN
false device is
in LACS
td8
Delay of DNAC false from
DAVtrue
td9
Delay of N RFD false from
end of read operation of
Data In register
td10
=
=
ATN = false device is
in LACS
ATN = false device is
=
Delay of NDAC false
from DAV true
td12
Delay of NDAC false from
end of write operation
td13
Delay of N RFD false from
DAVfalse
MAX
UNIT
2(0)t
2(0)t+415
ns
2(0)t
2(0)t+290
ns
3(O)t
3(0)t+445
ns
220
ns
2(0)t
2(0)t+415
ns
5(O)t
5(0)t+415
ns
7(0)t
7(0)t+415
ns
230
ns
180
ns
in LACS
Delay of interface message ATN
true device not
in CACS all interface
interrupt from DAV true
message interrupts
except UNO)
UNU mterrupt only
td11
MIN
=
ATN
true device not in
CACS no DAC holdoff
=
ATN
true device not
inCACS
374
ATN, EOI, and IFC Timing Characteristics Over Full Range of Operating Conditions
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td14
Delay of NDAC true
from ATN true
Device is not in CACS
195
ns
td15
Delay of TE high
from EOI true
Device is not in CACS
125
ns
td16
Delay of valid data
from EOI true
Device is not in CACS
140
ns
td17
Delay of TE low from
EOI false
Device is not in CACS
125
ns
td18
Delay of NRFD true
from ATN false
Device is in LADS/LACS
140
ns
td19
Response time to IFC
3Ot9QL
ns
MIN
MAX
UNIT
16tc(0)
Controller Timing Characteristics Over Full Range of Operating Conditions
PARAMETER
TEST CONDITIONS
td20
Delay of ATN true from end
of tca aux command
8tc(0)
10(0)t+ 220
ns
td21
Delay of BO interrupt from
end of tca aux command
18tc(0)
22(0)t + 415
ns
td22
Delay of ATN true from end BO unmasked device is
inANRS
of tcs aux command
8tc(0)
10(0)t + 220
ns
td23
Delay of BO interrupt from BO unmasked device is
end of tcs aux command
inANRS
18tc(0)
22(0)t + 415
ns
td24
Delay of EOI true from
rpp aux command set
230
ns
td25
Delay of EOI false from
rpp aux command cleared
230
ns
td26
Delay of EOI from rpp
aux command cleared
BO unmasked
10(0)t + 415
ns
td27
Delay of ATN false from
sts aux command
Device is not in SDYS
orSTRS
210
ns
J1
\-
I..
8tc(0)
r
I I
tw(OH)
-I I..
tw(Ol)
1
te(O)
I"
Figure 19.
WD9914 CLOCK CYCLE TIMING
375
I 1
-I 1
1
·1
~
c
co
co
..A.
ifI..
DBIN
J:iIo
\
~:
ta(DBIN)
WE
, .. ~ltz(DBIN)
1
-'
~ tsu(WE)
CE
----!--'
'{
~I
,
a(CE)
/:
1
I.- tSU(AD)~
1
,
,1 )
00-07
I
/--.itz(CE)
I
C
~
VALID DATA
1
)(
RSO-RS2
VALID ADDRESS
Figure 20.
WD9914 READ CYCLE TIMING
~---tw(WE)
I"
______
\t-~
I
WE
I
~)f~----------
,~-+-----tsu(CE)
.. ,
I
'X-
DBIN
~th(AD)'-I
~I
1
I1.-----tW(CE),---I--...,~~1
..
I
1
",11-1-::___
------1"~'I;SU(DBIN)
1-o1
..
~
th(DBIN)
I
~th(AD)':
: x=
=x
i-tSU(AD):;j
RSO-RS2
I"
tSU(DA):.j·I--.~j.-th(DA):....j
~tSU(DA)'
00-07
/1
__----'x
~I"
th(DA)~
x=
tsu(DA), thIDA), AND th(AD) ARE ONLY APPLICABLE TO THE FIRST SIGNAL TO BECOME INACTIVE, WHETHER IT IS WE OR
Figure 21.
WD9914 WRITE CYCLE TIMING
376
CE_
ACCRO
\
ACCGR
=e
Ii
c
.a:..
ji
'\
DBIN
$....
I - tC(GR/RO)--i
I
\
I
/
I
I
I
I
WE--------~--I~------~\_,(~SE~E~/r.--------------
:
\~O~E3/:
I
I
:
DO·D7
I-
~~I------~:I-____~~~I---H-I.-Z--------
ta(DBIN)-I
tz(GR)-.j
~I
1
....
_--ta(GR)
NOTE 3: A WRITE ENABLE PULSE MAY OCCUR IN A DMA READ OPERATION. A WRITE ENABLE PULSE MAY THEREFORE BE
PROVIDED FOR SYSTEM MEMORY AND NEED NOT BE SUPPRESSED AT THE WD9914.
Figure 22.
WD9914 DMA READ OPERATION
t
I--tW(WE)~
WE------------------------~~
I
I
ACCGR----------------""'~~~~--~i-t-s-U(G-R-)-----~~:~;r
1..
_--th(GR)I-.......:....--I:J~i._th(DBIN)~
..
i--tsu(DBIN)-+j
DBIN
..
-------I
:!
I-- tsu(DA)· ~ I" I th(DA):""'"
I -tsu(DA)· ~ I.. th(DA)=.j
I
I
DO.D7 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....)("
11"-'_ __
VALID DATA
X\..____
·tsu(DA) AND th(DA) ARE ONLY APPLICABLE TO THE FIRST SIGNAL TO BECOME INACTIVE, WHETHER IT IS WE OR ACCGR.
Figure 23.
WD9914 DMA WRITE OPERATION
377
WE~
1-1 td2
DI08'DI0-l------ki>{.,.I......._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
s
o
00------7 :
U
R
C
E
\:-..___
~ td3"1
1
(SEE NOTE 4)
,,'--7"';";---------r-___\ _____
,
I
I,
td41---,
1
\ ___ 1,'
td5~
1\
1
I_ dl-J'I=
DAV
t
(,
NRFD
I
IIIIIf////
: /r------
I'
I
'-ltd9
:1\ '----+1----+I--J
I rj+'-td8~
NDAC
A
C
C
E
P
T
1\\..--+-__
-----------+:-~\- -----7
1
1
INT
o
r-td6--i
R
(SEE NOTE 5)
I
ACCRQ------------~:~~~_ _ _ _ ___J~~:~---~td7
I
ACCGR---------------------------~,~---7J--------
'- - --' I
CE---------------------------------~~~-------
NOTES:
4: THE INTERRUPT LINE IS TAKEN LOW BY A BO INTERRUPT,
5: THE INTERRUPT LINE IS TAKEN LOW BY A BI INTERRUPT.
Figure 24_
WD9914 SOURCE AND ACCEPTOR HANDSHAKE TIMING(S)
378
____ _______________________
~x~
S
o
U
R
C
E
DAV------------~~~____________________~;f
i -1d13- \
NRFD--------------~~~_____________________________J~~~----I
~ld11--J
I
NDAC
I-ld12~
,7f(SEENOTE6)1--
I
,
-T\- _______
I.
I
~.
I
INT
A
C
C
E
P
T
I
\
I
I
/
I-ld10-+-!
V'\lJ
V
CE
0
P
WE
I
READ INTERRUPT
STATUS
I
WRITE dacr TO
AUXILIARY
COMMAND REG
NOTES:
6: THE BROKEN LINE SHOWS THE WAVEFORM IF THERE IS NO DAC HOLDOFl=. THE SOLID LINES ASSUME THERE IS A DAC HOLDOFF.
Figure 25.
WD9914 ACCEPTOR HANDSHAKE TIMING "ATN" TRUE
379
--J(,
ATN--"""""\F_ _ _ _ _ _ _ _ _
I
I
EOI.---_,...._ _""\\"._ _ _ _"
~-.f!d15
:
I
I
TE------~------~;'~----:~~~~~:-------------------td17~
NRFD------T----~~".......~H~I.~Z_
I
(SEE NOTE
7)r-_______
:V
I!r--------
__';I
j..td18~
NDAC----+-'"
I
I
\
~td14
HI·Z
,..-..;.;;---""\
\\.-_---J I
I
DAV--------~I--J;I
HI·Z
I
~\.
~td16
DI08.DI01---------~~
_______
.J)
......._ _ _ _ _
t d19
~:-------
!
i
1--+j
IFC------------------(-SE-E-N-O-TE""\~~_~:-------
-
I
I
INT----------------------~~~I~_ _ _ _ __
NOTES:
-
7: THIS ASSUMES THAT AN RFD HOLDOFF OCCURS.
8: IFC CAUSES THE WD9918 TO BE UNADDRESSED AND AN IFC INTERRUPT OCCURS.
Figure 26.
W09914 RESPONSE TO 'ATN' AND 'EOI'
380
f-oI---i td27
\
ATN
!.--i
J-I
td20, td22
I
\
EOI
I
I
~td24
INT
I
I
I
I
I
t d25
r
I
I
I
(SEE N,OTE 9)
td21,
f - l td26
11
WRITE
tcs or tea
I
I
I
I
I
I--td23~
,READ INT
STAT 0
SET
rpp
1--_...1 L-_ - - - '
CLEAR
WRITE
Sts
'pp
NOTE: 9: A BD INTERRUPT OCCURS AS THE WD9914 ENTERS CACS.
Figure 27.
WD9914 CONTROLLER TIMING
381
I
I
=E
C
(0
(0
...&.
J:a
i
i
I
See page 383 for ordering information.
Information furnished by Western Digital Corporation is believed to. be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No. license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to. change
specifications at anytime without notics.
382
Printed in U,S.A
ORDERING INFORMATION
OBSOLETE PACKAGE DESIGNATIONS
A
B
C
E
F
L
M
P
R
T
U
V
X
Y
CURRENT PACKAGE DESIGNATIONS
40 Lead DIP-Ceramic
40 Lead DIP-Relpak
24 Lead DIP-Ceramic
28 Lead DIP-Ceramic
28 Lead DIP-Relpak
18 Lead DIP-Ceramic
18 Lead DIP-Plastic (Totally Encapsulated)
40 Lead DIP-Plastic (Totally Encapsulated)
28 Lead DIP-Plastic (Totally Encapsulated)
48 Lead DIP-Ceramic
20 Lead DIP-Ceramic
20 Lead DIP-Plastic (Totally Encapsulated)
Ceramic Kit
Plastic Kit
PACKAGE TYPE:
LEAD COUNT:
A
C
P
D
A
B
C
D
E
G
H
J
Ceramic Side Braze
Cerdip
Plastic (Encap)
Ceramic Chip
Carrier-Lead less
Ceramic Chip
Carrier-Leaded
Plastic Chip
Carrier-Leadless
Plastic Chip
Carrier-Leaded
<14 Lead
14 Lead
16 Lead
18 Lead
20 Lead
F
22 Lead
G
24 Lead
H
28 Lead
40 Lead
L
M
44 Lead
N
48 Lead
S
64 Lead
T
68 Lead
Z
Kit
Example of current method:
WD1943PDOO Where PO = Double Digit
Package Designator (P = Plastic and D = 18 Lead)
Example of obsolete method:
WD1943MOO Where M = Single Digit
Package Designator (M = 18 Lead Plastic)
The following listing indicates the available packages for each product. The package diagrams are located on
page 384.
Product
Plastic
WD1510-00,01,02,03
UC1671-00
PL
Ceramic
CER-DIP
AH
CH
AL
TR1863-00,02,04
PL
AL
CL
TR1865-00,02,04
PL
AL
CL
WD1935-10,11 ,12, 13
PL
AL
WD1943-00
PD
AD
WD1943-02
PO
AD
WD1943-03
PD
AD
WD1943-04
PO
AD
WD1943-05
PD
AD
WD1943-06
PO
AD
WD1993-01,02,03
PH
AH
WD2001-05,20,30
PH
AH
WD2002-05,20,30
PL
AL
WD2123-00
PL
AL
WD2511-01,05,11
CL
AN
WD2840-01,05,11
AN
WD8250-00
PL
WD8275-00,02
AL
PL
WD8276-00,02
PL
CL
WD9914-00
PL
CL
CL
383
Package Diagrams
I
.310
MAX
r-
II~
--1
~ I
295
.325
I--
100
MAX
.015
l,~
.820
MIN
~MAX~-~l
~
.320
~t.-- ~!~
100
MAX
J.
.035 _
.055 ~
_
.120MIN
R
155MAx~1,
T
T120MIN
T~¥f9
.100TYP~ ~I
.014
.015
__ ~MIN
f-~l.j h-'
.035
~~
390
.100TYP...J .
014
.021
021
16 LEAD CERAMIC "AC"
16 LEAD PLASTIC "PC"
1--
.920
.015
MIN
~MAX---"l
~
.310
,_ _
L
155 MAX
I MAX
T~¥F9
-J I"'JI ~;;.j q -J -~~.~ k
~021
...-
920
: - - -..- -
j
~
.01 5MIN
MAX~
320
r
MAX
t~¥~~ZA
.100TYP
.014
.055
.100TYP
.120
MIN
--I
~~~ -~rc-
18 LEAD CERAMIC "AD"
--I34~
.390
5--.1
~I L
I-I i
T
.03
.055
1_ _ 11
k-
18 LEAD PLASTIC "PD"
t
t
.310
MAX
.015
MIN
1.020
1_
d
~--MAX~l
100MA>WDlmW
.,00TYP-.!
I
I.-IL
.
"'1
.014
~
L ,
FoMIN
m.5
- II .055 ~ ~
'.. -:325~1
T
"02-:"
20 LEAD CERAMIC "AE"
18 LEAD CERDIP "CD"
.015
.155 MAX
1
,~
1.040
.015 MIN
--.I
.320
I
rcJ1~~
T
II
150MAx~lt ~
=VWWWVWJl,~~~·
t
---. B-~-~
.,00TYP...!
.i..~~!~~MIN
·I.-.I~~·~~"'II.-"'t -J~:~ k-
I
100TYP~
.014
VoMIN
Ij~048
_ I I _ ::--T
I"'C.062~ ~
.014
:O21~
.021
20 LEAD PLASTIC "PE"
20 LEAD CERDIP "CE"
384
~
I _ .340 _ I
~~
Package Diagrams
.100 MAX
t
.015
-------.J MIN
1.425
1-
~ MAX---~I--,-
.155 MAX
J
i4-.610~
I_MAX
I
r-
.014
021
~
100TYP-J~l055---11-
.015
.1.
1_
1.460
MIN
150
.062
.100TYP
f.-:T
.120MIN
1:. ---i
610
MAX_1
.100 MAX
T'~L
~ U\lll!
-I j.-'00T~P ~
f.,.-~
.625
035-JQ
.055
.014
.021
40 LEAD CERAMIC "AL"
.480 ± .020
.1
D~""., !
.11
.155 MAX
I.e
.015 MIN
2.080
~
.620
MAX
r-
l~#~~~~
~ ~100~L035~ ~
.014
I~~
.055
.690
.021
,
--jJt11
~ 1~035MIN ---I
...
-J
n
i40MIN
~~
.690
28 LEAD CERDIP "CH"
.040
TYP
I-- .610--1
I:'" MAX--=-. I
.021
i
.055
.015
MIN
2.025
.014
-:065
.690
28 LEAD PLASTIC "PH"
TWM1WG¥ 9
~ ~L·048-..j
I
l.- .640 --J
.035
28 LEAD CERAMIC "AH"
-1-'------ MAX --~1
r---
:!~
.120
MIN
595--1
.625
.120 MIN
---1
I
.015 MIN
,WVWWWWVW-=lJ Pi
T~=¥ I I
-.I .~ ~I ~;;-l ~'f I.-
.100 TYP
1.460
L~MAX-----.jl
!---.100MAX
40 LEAD PLASTIC "PL"
.020
-TYP
40 LEAD CERAMIC CHIP CARRIER "DL"
.100
MAX
2.430
MAX
~l~
[.,50MAX
.015MIN
t-----~~~i'~610MAX
1-
T~~MIN~
-'~'~JL- I~
TYP
.062 ---
.015
~IMIN
.610
MAX
I~
-rmmmmmmmffl¥F1
~;;...jl-m4
~-I
.JL-l ~;~
!1~::~~1
.021
.690
.014
.021
48 LEAD CERAMIC "AN"
40 LEAD CERDIP "CL"
385
M~
l
64 LEAD CERAMIC CHIP CARRIER "OS"
48 LEAD CERAMIC CHIP CARRIER "ON"
COMMUNICATION PIN/FUNCTIONAL COMPATIBILITY GUIDE
WESTERN DIGITAL
AMI
SMC
INTEL
SSS
01
HARRIS
INTERSll
SCRt854
AY·3·1014A
H06402
IM64025
NYL
TI
FUJITSU
VIDEO DISPLAY
PROCESSORS
W08275
8275
WDB276
8276
PROTOCOL
CONTROLLERS
TRI863
51602
COMI863
TRtOOS
S6850
eMB018
UCt671
WB8868A
AY·3·1015
INS,S71
COM'67,
W08250
INS8250
TMS9914A
W09914
BAUD RATE
GENERATOR
WDt943
GQM5016
COMBtt6
386
STORAGE MANAGEMENT PRODUCTS
Part
Number
Floppy Disk
Controller
Components
Technical
Power
Package
__ ~nformation______ ..£l~9.lJ~ElIT!Ell'l.t~_§i~ __ .. __
FDI771
WDI770
Inverted data bus
Single chip
+ 5V, - 5V, + 12V
+ 5V
40 pins
28 pins
WDI772
Single chip
+5V
28 pins
WDI773
Single chip
+5V
28 pins
FD1791
FD1793
FD1795
FD1797
WD277X
+5V,
+5V,
+5V,
+5V,
+5V
WD2791
Inverted data bus
True data bus
Inverted data bus
True data bus
Improved data
separation
Inverted data bus
+5V
40 pins
WD1000·05
Board
+5V
5.75X8
WD1002·05
Board
+5V
5.75X8
WD1002·HDO
Board
+5V
5,75X8
WD1002·SAS
WD1002·SHD
WD1002WX2
WD1002·MTB
Board
Board
Board
Board
Sing-Ie-c-hi-p- -
+5V
+5V
+5V, -12V, + 12V
+5V
5.75X8
5.75X8
3.85X13
12X7
+5V
68 pins
+5V
68 pin_s_ _ _D"'y_n_a_m_ic_R_A_M_co_n_tr_ol_le_r._____
+12V
+12V
+ 12V
+12V
40 pins
40 pins
40 pins
40 pins
40 pins
Single density, IBM compatible
FD179X functionality with built·in
Digital Data Separator and Write
Precompensation.
WDI770 with enhanced stepping rates of
2, 3, 5, and 6 msec.
WD1770 with software compatibility to
FDI79X.
Single/double density, IBM compatible.
Single/double density, IBM compatible.
Single/double density, double sided.
Single/double density, double sided.
WD279X with improved data separator.
FD179X with built·in analog data separator
and write precompensation, single/double
density, and internal clock divide.
WD2793
True data bus
40 pins
FD179X with built·in analog data separator
+5V
and write precompensation, single/double
density, and internal clock divide.
WD2795
FD179X with built·in analog data separator
Inverted data bus
40 pins
+5V
and write precompensation, single/double
density, and side select out.
WD2797
True data bus
40 pins
FD179X with built·in analog data separator
+5V
and write precompensation, single/double
._________________ ..___.___ _.<:iEln~Yc.~~ige sele<:~ ________ _
WD1691
8" or 5.25 11 drives
20 pins
Floppy disk data separation/write
+5V
Floppy Disk
precompensation.
Support Devices
18 pins
Four phase clock generator.
WD2143
2.5 MHz
+ 5V
___ ._._._._._____.__ WD9~ ____.J>ingle chie. ___ ._~!;~ _____. ______!ljlins _ . __FloPPLdisk data separa~..r... _____..___ _
Winchester Disk
WD10l0
5 MHz
+ 5V
40 pins
5.25" and 8" Winchester Controlier chip.
Controller Devices
WD1050
Single chip
+ 5V
68 pins
SMD Controller.
WDll00
Chip Series
+ 5V
20 pins
5.25" and 8" Winchester Controller chips.
_. ________________ W_D_2_()1Q...
5 MHz
+5V
40 pins ___
W_D_l()1Q.w_it_h_E_CC.
Winchester Disk
WD10ll
CMOS
+ 5V
16 pins
Data separator de-v"-ic-e-c-om-p-at'C'ib'C'le with the
Support Devices
WD10l0.
+ 5V
18 pins
Write precompensation device compatible
WD1012
CMOS
with the WD10l0.
WD1014
Single chip
40
pins
Winchester error correction device.
+5V
WD1015
Single chip
Winchester Buffer Manager Control
40 pins
+5V
Processor.
Single chip
WDll00·13
20 pins
ECC Support device compatible with the
+5V
WD10l0.
Single chip
WDll00·21
14 pins
Winchester Buffer Manager Support
+5V
Device.
Winchester Board
Products
Main Memory
Devices
WD8206
WD8207 _ _ _S_in~g~le_c_h~ip~_ __
387
5.25" Winchester Controller board with
CRC.
5.25" Winchester/Floppy Controller board
with ECC.
5.25" Winchester-only controlier board
with ECC.
WD1002 with SASI interface.
WD1002·SASI interfaceWinchester only.
WD1002 with IBM PC compatible interface.
WD1002 w/Multibus interface.
Error detection and correction device for
main memory units (static and dynamic).
I
1-.
388
Component Products
Terms and Conditions
1.
ACCEPTANCE: Unless otherwise provided, it is agreed that sales are made on the terms, conditions and warranties contained herein and that to
the extent of any conflict, the same take precedence over any terms or conditions which may appear on Buyer's order form. Seller shall not be
bound by Buyer's terms and conditions unless expressly agreed to in writing. In the absence of written acceptance of these terms, acceptance of
or payment for any of the articles covered hereby shall constitute an acceptance of these terms and conditions.
2.
F.O.B. POINT: All sales are made F.O.B. point of shipment. Seller's title passes to Buyer and Seller's liability as to delivery ceases upon making
delivery of articles purchased hereunder to carrier at shipping point in good condition; the carrier acting as Buyer's agent. All claims for damages
must be filed with the carrier. Unless specific instructions from Buyer specify which method of shipment is to be used, the Seller will exercise his
own discretion.
3.
DELIVERY: Shipping dates are approximate only. Seller shall not be liable for any loss or expense (consequential or otherwise) incurred by Buyer
if Seller fails to meet the specified delivery schedule because of unavoidable production or other delays. Seller may deliver the articles in in-
stallments, Seller shall not be liable for any delay in delivery or for non-delivery, in whole or in part, caused by the occurrence of any contingency
beyond the control either of Seller or Seller's suppliers, including, by way of illustration but not limitation, war (whether an actual declaration
thereof is made or not), sabotage, insurrection, riot or other act of civil disobedience, act of a public enemy, failure or delay in transportation, act
of any government or any agency or subdivision thereof, judicial action, labor dispute, accident, fire, explosion, flood, storm or other act of God,
shortage of labor, fuel, raw material or machinery or technical failure where Seller has exercised ordinary care in the prevention thereof. If any
contingency occurs, Seller may allocate production and deliveries among Seller's customers.
4.
TERMS AND METHODS OF PAYMENT: Where seller has extended credit to Buyer, terms of payment shall be net thirty (30) days from date of
invoice. The amount of credit or terms of payment may be changed or credit withdrawn by Seller at any time. If the articles are delivered in installments, Buyer shall pay for each installment in accordance with the terms hereof. Payment shall be made for the articles without regard to
whether Buyer has made or may make any inspection of the articles. If shipments are delayed by Buyer, payments are due from the date when
Seller is prepared to make shipments. Articles held for Buyer are at Buyer's sale risk and expense,
5.
TAXES: All prices are exclusive of all federal, state and local excise, sales, use, and similar taxes. Such taxes; when applicable to this sale or to
the articles sold, will appear as separate additional items on the invoice unless Seller receives a properly executed exemption certificate from
Buyer prior to shipment.
6.
PATENTS: The Buyer shall hold the Seller harmless against any expense or loss resulting from infringement of patents or trademarks arising from
compliance with Buyer's designs or specifications or instructions. The sale of products by the Seller does not convey any license, by implication,
estoppel, or otherwise, under patent claims covering combinations of said products with other devices or elements. Except as otherwise
provided in the preceding paragraph, the Seller shall defend any suit or proceeding brought against the Buyer so far as based on a claim that any
product, or any part thereof, furnished under this contract constitutes an infringement of any patent of the United States, if notified promptly in
writing and given authority, information and assistance (at the Seller's expense) for the defense of same, and the Seller shall pay all damages and
costs awarded therein against the Buyer. In case said product, or any part thereof, is in such suit held to constitute infringement and the use of
said product or part is enjoined, the Seller, shall at its own expense, either procure for the Buyer the right to continue using said product or part,
or replace same with non-infringing product, or modify it so it becomes non·infringing, or remove said product and refund the purchase price and
the transportation and installation costs thereof. The foregoing states the entire liability of the Seller for patent infringement by the said products
of any part thereof.
7.
ASSIGNMENT: The Buyer shall not assign his order or any interest therein or any rights thereunder without the prior written consent of Seller.
S.
WARRANTY: Seller warrants articles of its manufacture against defective materials or workmanship for a period of one year from date on which
Seller delivers said articles. The liability of Seller under this warranty is limited at Seller's option, solely to repair, replacement with equivalent
articles, or an appropriate credit adjustment not to exceed the original sales price of articles returned to the Seller provided that (a) Seller is
promptly notified in writing by Buyer upon discovery of defects, (b) the defective article is returned to Seller, transportation charges prepaid by
Buyer, and (c) Seller's examination of such article disclosed to its satisfaction that defects were not caused by negligence, misuse, improper
installation, aCCident, or unauthorized repair or alteration by the Buyer. In the case of equipment articles, this warranty does not include
mechanical parts failing from normal usage nor does it cover limited life electrical components which deteriorate with age. In the case of ac·
cessories, not manufactured by Seller, but which are furnished with the Seller's equipment, Seller's liability is limited to whatever warranty is
extended by the manufacturers thereof and transferable to the Buyer. This Warranty is expressed in lieu of all other Warranties, expressed or
implied, including the implied Warranty of fitness for a particlar purpose, and of all other obligations or liabilities on the Seller's part, and it
neither assumes nor authorizes any other person to assume for the Seller any other liabilities. This Warranty should not be confused with or
construed to imply free preventative or remedial maintenance, calibration or other service required for normal operation of the equipment articles.
These Warranty provisions do not extend the original Warranty period of any article which has either been repaired or replaced by Seller. In no
event will Seller be liable for any incidental or consequential damages.
9.
TERMINATION: Buyer may terminate this contract in whole or from time to time in part upon 60 days written notice to Seller. In such event Buyer
shall be liable for termination charges which shall include a price adjustment based on the quantity of articles actually delivered, and all costs,
direct and indirect, incurred and committed for this contract together with a reasonable allowance for pro· rated expenses and profits. Any termination or back off in scheduling witl not be allowed on shipments scheduled for the month in which the request is made and for the month
following.
10.
GOVERNMENT CONTRACTS: If the articles to be furnished under this contract are to be used in the performance of a Government contract or
subcontract and a Government contract number shall appear on Buyer's purchase order, those clauses of the applicable Government
procurement regulation which are mandatorily required by Federal Statute to be included in Government subcontracts shall be incorporated
herein by reference.
11.
ORIGIN OF ARTICLES: Seller engages in off·shore production, assembly and/or processing and makes no warranty or representation, expressed
or implied, that the articles delivered hereunder are United States articles or of U.S. origin for the purpose of any statute, law, rule, regulation or
case thereunder. If Buyer ships the articles hereunder out of the U.S. for assembly, then at Buyer's request in writing, Seller shall provide in·
formation applicable to identification of any articles not of U.S. origin.
389
Corita Kent, the cover artist, is an American whose work presents an optimistic,
yet philosophical vievv of the world 'vve live in. A former Catholic nun and
teacher, Corita now devotes her life and energies to her artwork and the "human
needs she feels transcend national and religious barriers." A true "citizen of the
world," Corita's philosophy positions her "on the positive side of hope." Her
depiction of the Western Digital mission ... "Making the leading edge work for
you" ... dramatizes the spectrum of solutions we provide our customers.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
390
WESTERN DIGITAl.
CORPORA
TION
2445 McCabe Way, Irvine, CA 92714
(714) 863·0102' TWX 910-595-1139
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