1985_Exar_Databook 1985 Exar Databook
User Manual: 1985_Exar_Databook
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Disclaimer
Exar reserves the right to make changes in the products contained in this book in order to improve design or performance and to supply the best possible products. Exar also assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representations that the circuits are
free from patent infringement. Applications for any integrated circuits contained in this publication are for illustration
purposes only and Exar makes no representation or warranty that such applications will be suitable for the use specified without further testing or modification. Reproduction of any portion hereof without the prior written consent of
Exar is prohibited.
Second printing - March 1985
750 Palomar Avenue
Sunnyvale, CA 94086
Telephone (408) 732-7970
TWX: 910-339-9233
Application Notes
II
Quality Assurance
II
General Information
II
EXAR Corporation
750 Palomar Avenue
Sunnyvale, CA 94086
Telephone (408) 732·7970
TWX: 910·339·9233
Introduction
Introduction
This Data Book contains a complete summary of technical information covering Exar's full line of standard,
semi-custom, and custom IG products. Each of the
products presented covers a wide range of applications, greatly simplifying most system designs. To help
the designer find the right device for his application,
the products are grouped by function, and a convenient
cross-reference chart is provided to show Exar's direct
replacement for a number of popular industry products.
EXPERIENCE AND PRODUCTS
Exar's innovativeness, product quality, and responsiveness to customer need, has been the key to its success. Exar offers a broad line of linear and interface circuits. In the field of standard linear IG products, Exar
has extended its circuit technological leadership into
the areas of communications and control circuits. Today, Exar has one of the most complete lines of oscillators, timing circuits and phase-locked loop IGs in the
industry. Exar also manufactures a large family of
telecommunication circuits, such as tone decoders,
compandors, modulators, PCM repeaters, and FSK and
PSK modem circuits. In the field of industrial control circuits, Exar manufactures a broad line of quad and dual
operational amplifiers, voltage regulators, radio-control
and servo driver ICs, and power control circuits.
Exar's experience and expertise in the area of bipolar,
CMOS and 12L IC technology extends into both custom
and standard IC products. In the area of custom ICs,
Exar has designed, developed, and manufactured a
wide range of full custom monolithic circuits, particularly for applications in the areas of telecommunications, consumer electronics, and industrial controls.
In addition to the full custom capability, Exar also offers
a unique semi-custom IC development capability, for
low to medium volume requirements. This semi-custom
program is intended for those customers seeking costeffective solutions; reducing component count and
board size in order to compete more effectively in a
changing marketplace. The program allows a customized monolithic IC to be developed with a turnaround
time of several weeks, at a small fraction of the cost of
a full custom development program.
EXCELLENCE IN ENGINEERING
Exar quality starts in Engineering where highly qualified
people are backed up with the advanced instruments
and facilities needed for design and manufacture of
custom, semi-custom and standard integrated circuits.
Exar's engineering and facilities are geared to handle
all three classes of IC design: (1) Semi-custom design
programs using Exar's bipolar and 12L Master Chips; (2)
Full custom IC design, and (3) Development and highvolume production of standard products.
Some of the challenging and complex development programs successfully completed by Exar include analog
compandors and PCM repeaters for telecommunication, electronic fuel-injection, anti-skid braking systems, and voltage regulators for automotive electronics, digital voltmeter circuits, 40-MHz frequency synthesizers, high-current, high-voltage display and relay
driver ICs, and many others.
NEW TECHNOLOGIES
Through company sponsored research and development activities, Exar constantly stays abreast of all
technology areas related to changing customer needs
and requirements. Exar has a complete design engineering group dedicated to new technology.
FIRST IN QUALITY
From incoming inspection of all materials, to the final
test of finished goods, Exar performs sample testing of
each lot to ensure that every product meets Exar's high
quality standards. Exar's manufacturing process is inspected or tested in accordance with its own stringent
Quality Assurance Program, which is in compliance
with MIL-I-45208. Additional special screening and testing can be negotiated to meet individual customer
requirements.
Throughout the wafer fab and assembly process, the
latest scientific instruments, such as scanning electron
microscopes, are used for inspection, and modern automated equipment is used for wafer probe, ac, dc, and
functional testing. Environmental and burn-in testing of
finished products is also done in-house. For special environmental or high-reliability burn-in tests, outside testing laboratories are used to complement Exar's own extensive in-house facilities.
FIRST IN SERVICE
Exar has the ability and flexibility to serve the customer
in a variety of ways, from wafer fabrication to full parametric selection of assembled units for individual customer requirements. Special marking, special packaging, and military screening, are only a few of the service
options available from Exar. We are certain that Exar's
service is flexible enough to satisfy 99% of your needs.
The company has a large staff of Applications Engineers to assist the customer in the use of the product,
and to handle any request, large or small.
Standard Products
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STANDARD PRODUCTS
Phase-Locked Loops
Fundamentals of Phase-Locked Loops ........................................................ 1-5
Applications of PPL IC's ................•........•..•..•.....•......•...............•...•.. 1-6
Choosing the Right PLL Circuit .......................•....•....••..••••••.•.••..•..•..•..... 1-8
XR-210 .......•.... " ......•..•••••..••..•..•......•............................••.•..•• 1-9
XR-215 ..•.............•...•.....•.........•...................•..•...........•..••.... 1-14
XR-2211 ..................•................................•.................•..•...... 1-23
XR-2212 ..................•............................................................ 1-31
XR-2213 .............................................•...........••.................... 1-38
Tone Decoders
XR-567 ........................................................•....................... 1-43
XR-567A ........................................••....••.....•.....•............•...... 1-53
XR-L567 ..........•.............•...•............•.....••.•........••.....•...•........ 1-55
XR-2567 •........•...........•.••...•....•.••..•.......•..•.•••....•..................• 1-62
Filters
XR-1000/1008 ...................•...•....•......••.....•..•...•.....•.................. 1-71
XR-2103 ...•....•..•.......•..••....•...•..•...••..•..•..•...•.....•.....•..••..•.••••. 1-73
XR-2120 ........•.............••..•.•...•..•................•.....•...•••..••.......... 1-78
XR-2120A ..•.•.••••..•...•..•••....••.....•..••......•....••...•.•.....•............... 1-84
Modem Circuits
Modem 8asics •..•....•........•........••.....•...•.••..••••.........................•.• 1-87
XR-14412 ..................................................................••...•...... 1-93
XR-2121/2122 ...................••........•.............•.....••....•.•....•...•....... 1-99
XR-2123 ...............................................••.....••.....•.....•........... 1-103
XR-2125 .••........••......•........•••..•...•..•..•..•••...•••...........•............ 1-109
Interface Circuits
XR-1488/1489A .....•..........•..•..•......•......•...............•......•••......•..•.. 1-111
Disk Drive Circuits
XR-2247/2247A ....•......•.........••............•..••..........••..•..•............... 1-114
XR-3470A/3470B ..••......•...•.•....•..•..•.....••..•.....•...•.•..•......•.....•..•... 1-121
Timing Circuits
Fundamentals of IC Timers ...........•..•.............•..••.....•.........•.....••.•....••. 1-12B
Choosing the Right IC Timer •...•...•........•..•...•..•..•..............•.•.....•••....••.. 1-131
1·1
STANDARD PRODUCTS
(CONTINUED)
XR·320 .....•.•...•••.•••..•.•..••.•...•.....•....••...............•.........•....•..•.. 1·134
XR·555 .•.•.•••.•..•..•..•.•.••..•.••.•..•...•.••.••..•••.••.••...•...••...•....•...... 1·139
XR·L555 ...............................•........•..••.. : ....•••••.•...••...•........... 1·142
XR·556 •.•....••...•..•............•..•................................................ 1·146
XR·L556 ................................................................................ 1·149
XR·558/559 .....•.....••••••.•.•••••...••.•...••...••...••..•....•....•..•............. 1·155
XR·2556 ••...•.••...•.•......••...•....•............................................... 1·159
XR·2240 .••.•..•.•.....•.................•.............•............................... 1·168
XR·2242 .•...••..•..•.•...........•..•...•......•..•.•.••....•....•.......•.....•...... 1·176
XR·2243 ..•...•..........••...•..•••.•..•.•.•..•..................•.................... 1·180
Function Generators
Fundamentals of Monolithic Waveform
Generation and Shaping .....••.•..•.•••..••••..•.•..•.•....•.......•.•....•............... 1·184
Choosing the Right IC Oscillator .....•..............•....•....•.•............................ 1·186
XR·205 .••....•....•......•.......•................•..............•.................•.. 1·188
XR·2206 .•...........•.•........•.••....••....•............•...............••.......... 1·193
XR·2207 .............•....••..•..•..•...•..•.•••....•...•..........•...... , ............ 1·199
XR·2209 ....................•..•...........•....•...........•.......................... 1·208 .
XR·8038 •.......•....•.••....•.........•...............•..•.........•.................. 1·213
XR·8038A ...............••.•..•.•.•..•..•••.•....•.•..•...•............................ 1·217
Multipliers/Modulators
XR·2208 .•.......•..........•..••..•....••••.•••......•.•..........•....•.............. 1·219
XR·2228 ••..•..•...••.•.......................•..•..................................... 1·22.7
Display Drivers
XR·2271 .•.......•.... : .•.......................••........•....•....................... 1·236
XR·2272 .•...•......•.•.•..•.•....•..•.•.••.•..........................•............... 1·238
XR·2276 •............•.•.•....••••..•.•.•.•.•.••...•..••.•.....•.•..•....•............. 1·241
XR·2277/2278 ......•..•..•.....................................•....•.................. 1·246
XR·2279 .•.....•...•..............•...........•...•.............................•...... 1·251
XR·2284/2288 .......•...•..........................................•................... 1·255
XR·6118/6128 .............•..••..•..•..•••....•...........................•............ 1·259
Operational Amplifiers
Fundamentals of Operational Ampilfiers ...........................................•..•........ 1-262
Definitions of Operational Amplifier Terms ..•.•....................••...••.•..•.•.....•........ 1·263
Basic Applications of Operational Amplifiers ................................................... 1·264
Choosing the Right Op Amp .•....•.........•................••...•.....•...•......•.•...... 1-270
XR·082/083 ............................................................................. 1-272
XR·084 .........••...•.•.....••••..•••..•••.•.•..•....•....•.........•...•....•.•.. ; ... 1-275
1·2
\
STANDARD PRODUCTS
\
(CONTINUED)
XR·094/095 ............................................................................ 1·277
XR·096 ................................................................................ 1·279
XR·146/246/346 .....•.................................................................. 1·281
XR·1458/4558 .......................................................................... 1·285
XR·340313503 .......................................................................... 1·287
XR·4136 ............................................................................... 1·290
XR·4202 ............................................................................... 1·293
XR·4212 ............................................................................... 1·297
XR·4739 ............................................................................... 1·300
XR·4741 ............................................................................... 1·303
XR·5532/5532A ......................................................................... 1·306
XR·5533/5533A ......................................................................... 1·310
XR·5534/5534A ......................................................................... 1·314
Voltage Regulators
XR·1468/1568 .......................................................................... 1·318
XR·494 ................................................................................ 1·320
XR·495 ................................................................................ 1·324
XR·1524/2524/3524 ..................................................................... 1·328
XR·1525A/2525A/3525A
XR·1527A/2527A/3527A .................................................................. 1·336
XR·1543/2543/3543 ..................................................................... 1·343
XR·223o ............................................................................... 1-351
XR·4194 ............................................................................... 1·358
XR·4195 ............................................................................... 1·361
High Current Drivers
XR·2oo1/2oo2/2oo3/2oo4 ................................................................ 1·364
XR"201112o1212o1312o14 ................................................................ 1·368
XR·22oo ............................................................................... 1·372
XR·2201122o2122o3122o4 ................................................................ 1·374
Special Functions
XR·S2oo ............................................................................... 1-376
XR·131o ............................................................................... 1·385
XR·2264/2265 .......................................................................... 1·387
XR·2266 ............................................................................... 1·390
XR·9201 ............................................................................... 1·398
XR-4151 ............................................................................... 1·406
XR·7ooo ............................................................................... 1·411
1·3
STANDARD PRODUCTS
(CONTINUED)
XR·2216 ............................................................................... 1·413
XR~13600 .............................................................................. 1·417
Repeaters
XR·C240 ...............................................................................
XR·C262 ...............................................................................
XR·C277 ............................................•..................................
XR·C587/C588 ..........................................................................
XR·T5600/T5620 ........................................................................
XR·T5640 ..............................................................................
XR·T5650 ..............................................................................
XR· T5660 ..............................................................................
XR·T5700/T5720 ........................................................................
XR·T5740 .........................•....................................................
XR· T5750 ..............................................................................
XR· T5760 ..............................................................................
1·4
1·428
1·430
1·432
1·434
1·440
1·447
1·449
1·451
1·453
1·460
1·462
1·464
Phased~locked
loops
Fundamentals of Phase-Locked Loops
is always smaller than the lock range and is related to
the low-pass filter bandwidth. It decreases as the filter
bandwidth is reduced.
The phase locked loop provides frequency selective
tuning and filtering without the need for coils or inductors. As shown in Figure 1. the PLL in its most basic
form is a feedback system comprised of three basic
functional blocks: a phase comparator. low-pass filter
and voltage controlled oscillator (VeO).
The lock and the capture ranges of a PLL can be illustrated with reference to Figure 2. which shows the typical frequency-to-voltage characteristics of a PLL. In the
figure. the input is assumed to be swept slowly over a
broad frequency range. The vertical scale corresponds
to the loop error voltage.
The basic principle of operation of a PLL can briefly be
explained as follows: With no input signal applied to the
system. the error voltage Vd is equal to zero. The veo
operates at a set frequency. fo • which is known as the
free-running frequency. If an input Signal is applied to
the system. the phase comparator compares the phase
and frequency of the input signal with the veo frequency and generates an error voltage. Ve(t). that is related
to the phase and frequency difference between the two
signals. This error voltage is then filtered and applied to
the control terminal of the veo. If the input frequency.
fs • is sufficiently close to fo• the feedback nature of the
PLL causes the veo to synchronize. or lock. with the
incoming signal. Once in lock. the veo frequency is
identical to the input signal. except for a finite phase difference.
In the upper part of Figure 2. the loop frequency is being gradually increased. The loop does not respond to
the signal until it reaches a frequency f1. corresponding to the lower edge of the capture range. Then. the
loop suddenly locks on the input. causing a negative
jump of the loop error Voltage .. Next. Vd varies with
frequency with a slope equal to the reciprocal of the
veo voltage-to-frequency conversion gain. and goes
through zero as fs = fa. The loop tracks the input until
the input frequency reaches f2. corresponding to the
upper edge of the lock range. The PLL then loses lock.
and the error voltage drops to zero.
If the input frequency is now swept slowly back. the cycle repeats itself as shown in the lower part of Figure 2.
The loop recaptures the signal at f3 and traces it down
to f4. The frequency spread between (f1. f3) and (f2. f4)
corresponds to the total capture and lock ranges of the
system; that is. f3 - f1 = capture range and f2 - f4 =
lock range. The PLL responds only to those input signals sufficiently close to the veo frequency. f o• to fall
within the "lock" or "capture" range of the system. Its
performance characteristics. therefore. offer a high degree of frequency selectivity. with the selectivity characteristics centered about fo .
Two key parameters of a PLL system are its lock and
capture ranges. They can be defined as follows:
Lock range: The range of frequencies in the vicinity of fa.
over which the PLL can maintain lock with an input signal. It is also known as the tracking or holding range.
Lock range increases as the over-all gain of the PLL is
increased.
Capture range: The band of frequencies in the vicinity of
fo where the PLL can establish or acquire lock with an
input signal. It is also known as the acquisition range. It
t-- {\fL--!
Vd
. :,,~ I-~
M
V'"
'I
FREaUENCY
I,
-I
I
LOCK RANGE
I
---.l
I + - - 2t;IL
I
CAPTURE RANGE
:
I- 2t;f c --I
'4
Figure 1_ The basic phase locked loop consists of three functional blocks: a phase comparator, a low pass finer
and a vonage-controlled oscillator.
FREQUENCY
Figure 2. Typical PLL frequency-to-voltage transfer characteristics are shown for increasing (upper diagram) and
decreasing (lower diagram) input frequency.
1·5
Applications of PLL Ie's
The basic concept of the phase locked loop (PLL) has
been around since the early 1930's and has been used
for a variety of applications in instrumentation and
space telemetry. However, before the advent of monolithic integration, cost and complexity considerations
limited its use to precision measurements requiring
very narrow bandwidths. In the past few years, the advantages of monolithic integration have changed the
phase locked loop from a specialized design technique
to a general-purpose building block. Therefore, what is
"new" at this point is not the concept of the PLL, but its
availability in a low-cost self contained monolithic Ie
package.
Applications for PLLs Abound
As a versatile building block, the PLL covers a wide
range of applications. Some of the more important are
the following:
FM demodulation: In this application,the PLL is locked on
the input FM signal, and the loop-error voltage, Vd(t) in
Figure 1 (see Box), which keeps the
in lock with
the input signal, represents the demodulated output.
Since the system responds only to input signals within
the capture range of the PLL, it also provides a high degree of frequency seleCtivity. In most applications the
quality of the demodulated output (I.e_, its linearity and
signal/noise ratio) obtained from a PLL is superior to
that of a conventional discriminator.
veo
In many ways, this is similar to the case of the monolithic operational amplifier, which, until less than a decade
ago, was an expensive building block. Today, with the
advent of monolithic technology, it has become a basic
building block in nearly every system design. The
monolithic phase locked loop also offers a similar potential. In fact, many of the applications of the PLL outlined in this article become .economically feasible only
because the PLL is now available as a low-cost Ie building block.
FSKdemodulation: Frequency-shift keyed (FSK) signals
are commonly used to transmit digital information over
telephone lines. In. this type of modulation, the carrier
signal is shifted between two discrete frequencies to
encode the binary data. When the PLL is locked on the
input signal, tracking the shifts in the input frequency,
the error voltage in the loop, Vd(t), converts the frequency shifts back to binary logic pulses.
Signal conditioning: When the PLL is locked on a noisy input signal, the
output duplicates the frequency of
the desired input but greatly attenuates the nOise, undesired sidebands and interference present at the input. It
is also a tracking filter since it can track a slowly varying input frequency.
veo
Today, over a dozen different integrated PLL products
are available from a number of Ie manufacturers. Some
of these are designed as "general-purpose" circuits,
suitable for a multitude of uses; others are intended or
optimized for special applications such as tone detection, stereo decoding and frequency synthesis. This article is intended as a brief survey of the expanding field
of monolithic phase locked loops. Its purpose is to familiarize the reader with their individual characteristics,
capabilities and applications.
Frequency synthesis: The PLL can be used to generate
new frequencies from a stable reference source by either frequency multiplication and division, or by frequency translatiori. Figure 3 shows a typical frequency
multiplication and division circuit, using a PLL and two
programmable counters. In this application, one of the
counters is inserted between the veo and phase comparator and effectively divides the
frequency by
veo
OFFSET
PLL
"ROGFtAMMABLE
COUNTEH
1 - - - - - - - - - -1
INPUT
I,
PLl.
-----1
1
1
1
1
1
1
1
1
1
1
1
1
- - _ _ _ _ _ _1
1
'- ____ J
Figure 4. Frequency translation. can be accomplished with a
phase locked loop. by adding a multiplier and an addHlonal low-pass filter to the basic PLL.
Figure 3. A frequency multiplier/divider can be constructed
using a phase locked loop_
1-6
the counter's modulus N. When the system is in lock,
the VCO output is related to the reference frequency,
fR' by the counter moduli M and N as:
fo =
(f~)
AMOA
TONE
fR
INPUT
By adding a multiplier and an additional low-pass filter
to a PLL (Figure 4), one can form a frequency translation loop. In this application, the VCO output is shifted
from the reference frequency, fR, by an amount equal
to the offset frequency, f1, i.e., fo = (fR + f1).
Data synchronization: The PLL can be used to extract synchronization from a composite signal, or can be used to
synchronize two data streams or system clocks to the
same frequency reference. Such applications are useful in PCM data transmission, regenerative repeaters,
CRT scanning and or drum memory read-write synchronization.
DEMOOULATED
OUTPUT
Figure 5. AM and tone detection are possible by adding three
functional blocks to the basic phase locked loop.
AM detection: The PLL can be converted to a synchro-
achieved using a PLL system, as shown in Figure 6.
The VCO section of the monolithic PLL is separated
from the phase-comparator and used to generate a voltage controlled reference frequency, fRo The motor shaft
and the tachometer output provide the second signal,
frequency fM, which is compared to the reference frequency. The controller is a power amplifier which drives
the speed-control windings of the motor. Thus, the motor and tachometer combination essentially functions
as a VCO which is phase locked to the voltage controlled reference frequency, fRo
nous AM detector with the addition of a non·critical
phase-shift network, an analog multiplier and a lowpass filter. The system block diagram for this application is shown in Figure 5.
In this application, as the PLL tracks the carrier of the
input signal, the VCO regenerates the unmodulated car·
rier and feeds it to the reference input of the multiplier
section. In this manner, the system functions as a synchronous demodulator with the filtered output of the
multiplier representing the demodulated audio information.
Stereo decoding: In commercial FM broadcasting, suppressed carrier AM modulation is used to superimpose
the stereo information on the FM signal. To demodulate
the complex stereo signal, low-level pilot tone is transmitted at 19 kHz (1/2 of actual carrier frequency). The
PLL can be used to lock onto this pilot tone, and regenerate a coherent 38 kHz carrier which is then used to
demodulate the complete stereo signal. A number of
highly specialized monolithic circuits have been developed for this application. A typical example of monolithic stereo decoder circuits using the PLL principle is the
XR-1310 stereo demodulator IC.
Tone detection: In this application, the PLL is again connected as shown in Figure 5. When a signal tone is
present at the input, within a frequency band corresponding to the capture range of the PLL, the output dc
voltage is shifted from its tone-absent level. This shift is
easily converted to a logic signal by adding a threshold
detector with logic-compatible output levels.
Motor speed contrOl: Many electromechanical systems,
such as magnetic tape drives and disc or drum head
drivers, require precise speed control. This can be
L ________ _
ANALOG CONTROL
INPUT
Figure 6. Very preCise motor speed contrails possible with a phase locked loop system of this type.
1-7
Choosing the Right PLLCircuit
o
o
o
Center frequency stability.
Logic compatible output.
Control of VCO conversion gain.
Center frequency stability is essential to insure that the
VCO frequency range stays within the signal band over
the operating temperature range. A logic compatible
output is desirable to avoid the need for an external
voltage comparator (slicer) to square the output pulses.
It is particularly convenient if the output conforms to
RS-232C standard, thereby eliminating the need for a
separate line-driver circuit. Control of the VCO's conversion gain allows the circuit to be used for both large deviation FSK signals (such as 1200 baud operation) as
well as for small deviation (75 baud) FSK signals.
'
At the onset of his design, the user of monolithic PLL
products is faced with the key question of choosing the
phase-locked loop IC best suited to his application. The
broad line of PLL products offered by Exar cover a wide
range of applications. It is often difficult to determine at
a glance the best circuit for a given application. The
purpose of this section is to review some of the key performance requirements, from an applications pOint of
view, and help answer the question; "What is the best
PLL product for the job?"
Table 2 gives a brief listing of some of the major classes
of PLL applications, and lists the recommended circuits
'for each. A further discussion of the key performance
parameters associated with each application are also
listed below.
For FSK decoding at low frequencies (i.e., below 300
kHz) the XR-2211 is by far the optimum circuit to use
because of its frequency stability and carrier-detect capability. For FSK detection at higher frequencies (up to
10 MHz) the XR-210 is the recommended circuit.
FM demodulation: Essentially all the PLL circuits listed in
Table 1 can be used for FM demodulation. However, it is
often possible to narrow the choice down to 2 or 3 circuits, based on the particular performance criteria. In
general, there are three key performance parameters
which should be examined:
o
Quality of demodulated output: This is, normally
measured in terms of the output level, distortion,
and signal/noise ratio for a given FM deviation.
o
VCO frequency range and frequency stability: For
reliable operation, VCO upper frequency limit (see
Table 1) should be at least 20% above the FM carrier frequency. VCO frequency stability is important,
especially if a narrow-band filter is used in front of
the PLL, or multiple input channels are present. If
the VCO exhibits excessive drift, the PLL can drift
out of the input signal band as the ambiel'lt temperature varies.
o
Detection threshold: This, parameter determines
minimum signal level necessary for the PLL to lock
and demodulate an FM signal of given deviation.
Frequency synthesis: This application requires a PLL circuit with the loop opened between the VCO output and
the phase comparator input, so that an external frequency divider can be inserted into the feedback loop
of the PLL. This requirement is satisfied by XR-S200,
XR-210, XR-215 and the XR-2212 PLL circuits.
For frequency synthesis at low frequencies (i.e., with
maximum output frequency less than 300 kHz) the
XR-2212 is by far the best suited circuit since it has the
best VCO stability and interfaces easily with all logic
families. For operation above 300 kHz, either the
XR-210 or the XR-215 PLL IC's can be used for frequency synthesis; however the XR:215 offers the highest frequency capability.
Signal conditioning: Most signal conditioning applications
require very narrow-band operation of the PLL. This in
turn may require the use of active filters within the loop
(between the phase detector and the VCO). The PLL circuits which allow active filers to be inserted into the
loop are the XR-S200 arid the XR-2212. Both of these
circuits already contain an op. amp. on the chip for active filtering. For low frequencies (i.e. below 300 kHz)
the XR-2212 is the best suited circuit because of its adjustable tracking bandwidth and excellent frequency
stability. For higher frequencies the XR-S200 is the recommended circuit.
In most FM demodulation applications, it is also desirable to control the amplitude of the demodulated output. This feature is provided in some of the PLL circuits
(such as the XR-215 and the XR-2212) by means of a
variable-gain amplifier contained on the chip.
For low-frequency FM detection (below 300 kHz carrier
frequency) the XR-2212 is recommended because of its
versatility and temperatlire stability. For FM demodulation at frequencies above 300 kHz, the XR-2215 offers
the best performance because of its high frequency capability.
Tone decoding: The PLL circuits especially designed for
this application are the XR-567, the XR-L567, the
XR-2567 and the XR-2211. The XR-2211 offers the highest frequency stability, and independent control of system bandwidth and response time, among the three circuits. The XR-567 has a relatively high input threshold
('" 20 mV, rms) and may require input preamplification;
however it requires fewer external components that the
XR-2211. The XR-2567, which contains two independent 567-type tone decoders on the same chip may be
more economical to use in multiple-tone detection systems.
FSK decoding: Frequency-shift keying used in digital
communications is very similar to analog FM modulation. Therefore, any PLL IC can be used for FSK decoding, provided that its input sensitivity and the tracking
range are sufficient for a given FSK signal deviation.
Some of the basic requirements and desirable features
for a PLL used in FSK decoding are:
1-8
XR·210
FSK Modulator/Demodulator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-210 is a highly versatile monolithic phaselocked loop system, especially designed for data communications. It is particularly well suited for FSK
modulation/demodulation (MODEM) applications, frequency synthesis, tracking filters, and tone decoding.
The XR-210 operates over a power supply range of 5V
to 26V, and over a frequency band of 0.5 Hz to 20 MHz.
The circuit can accommodate analog signals between
300 p.V and 3V, and can interface with conventional
DTL, TTL, and ECL logic families.
VOLTAGE
COMPARATOR
INPUT
+Vcc
r
VCO
OUTPUT
PHASE
OETECTOR
OUTPUTS
-,
L
VCO
TIMING
CAPACITOR
INPUT
#1
J
1
BIAS
VCOGAIN
AND SWEEP
CONTROLS
INPUT
#2
FEATURES
Wide Frequency Range
0.5 Hz to 20 MHz
Wide Supply Voltage Range
5V to 26V
Digital Programming Capability
RS-232C Compatible Demodulator Output
DTL, TTL and ECL Logic Compatibility
Wide Dynamic Range
300 p.V to 3V
ON-OFF Keying & Sweep Capability
Wide Tracking Range
±1 % to ±50%
200 ppm/DC
Good Temperature Stability
50 rnA
High-Current Logic Output
Independent "Mark" and "Space"
Frequency Adjustment
VCO Duty Cycle Control
J
GROUND
(-V"i
VCO
KEYING
INPUT
LOGIC
OUTPUT
VCO
FINE-TUNE
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-210M
XR-210CN
Ceramic
Ceramic
-55°C to +125°C
O°C to + 70°C
APPLICATIONS
Data Synchronization
Signal Conditioning
FSK Generation
Tone Decoding
Frequency Synthesis
FSK Demodulation
Tracking Filter
FM Detection
FM and Sweep Generation
Wideband Discrimination
SYSTEM DESCRIPTION
The XR-210 is made up of a stable wide-range voltagecontrolled oscillator (VCO), exclusive OR gate type
phase detector, and an analog voltage comparator. The
VCO, which produces a square wave as an output, is either used in conjunction with the phase detector to
form a phase-locked loop (PLL) for FSK demodulation
and tone detection or as a generator in FSK modulation
schemes. The phase detector when used in the PLL
configuration produces a differentional output voltage
with a 6 KO output impedance, which when capacitively
loaded forms a single pole loop filter. The voltage comparator is used to sense the phase detector output and
produces the output in the FSK demodulation connection.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Derate Above + 25°C
Storage Temperature
26 Volts
750mW
6.0 mW/oC
-65°C to +150°C
1-9
XR·210
ELECTRICAL CHARACTERISTICS
= 12V (single supply), TA = + 25·C, Test circuit of Figure 1 with Co
S6, S7 open, unless otherwise specified.
Test Conditions: V+
SYMBOL
PARAMETERS
MIN
TYP
MAX
UNIT
26
±13
16
V dc
V dc
500
0.5
ppm/·C
= 0.02 ,..F, Sl, S2, S5closed, S3, S4'
CONDITIONS
GENERAL CHARACTERISTICS
Supply Voltage
VCC
ICC
fUL
fLL
Single Supply
Split Supply
Supply Current
Upper Frequency Limit
Lowest Practical Operating
Frequency
5
±2.5
9
15
12
20
0.5
See Figure 1
See.Figure2
See Figure 1, S2 open
See Figure 1, Sl open, S4 closed
Co = 500,..F
mA
MHz
Hz
VCO SECTION
TC
PSR
fSW
Vo
DC
TR
TF
Stability
Temperature
Power Supply
Sweep Range
Output Voltage Swing
Duty Cycle Asymmetry
Rise Time
Fall Time
5:1
1.5
200
0.05
8:1
2.5
±1
20
40
±3
f
= 10 kHz, V+
~ 10V,0
< V+ < 24V
<
TA
<
75·C
%N
10V
Vp-p
%
ns
ns
S3 closed, S4 open, 0 < Vs < 6V
See Figure 5, V+ = 12V
S5 open
S5 open
10 pF to ground at Pin 15, S5 open
10 pF to ground at Pin 15, S5 open
Vlrad
Yin
PHASE DETECTOR SECTION
KD
lO
VOOS
Conversion Gain
Output Impedance
Output Offset Voltage
2
6
35
> 50 mV rms, see Figure 8
Measured looking Into Pin 2 or 3
Measured across Pin 1 and 3, Yin
S5 open
kD
150
mV
= 0,
VOLTAGE COMPARATOR SECTION
AVOL
liN
VOS
IS
CMRR
Open Loop Voltage Gain
Input Impedance
Input Offset Voltage
Input Bias Current
Common Mode Rejection
66
0.5
80
2
1
80
90
dS
MD
f - 20 Hz
Measured looking into Pin 1
mV
nA
dB
LOGIC OUTPUT SECTION
SR
IOL
VOL
ISINK
Slew Rate
"1" Output Leakage Current
"0" Output Voltage
Current Sink Capability
30
VI,..sec
15
0.02
0.2
50
10
0.4
RL - 3 kD, CL - 10 pF, S2 closed
,..A
Vo
V
IL
mA
Vo
= +24V
= 10 mA
s 1V
EQUIVALENT SCHEMATIC DIAGRAM
PRINCIPLES OF OPERATION
Description of Controls
Phase-Detector Inputs (Pin 4 and 6):
One input to the phase detector is used as the signal input; the remaining input should be ac coupled to the
veo output (Pin 15), to complete the PLL (see Figure 1).
For split supply operation, these inputs are biased from
ground as shown in Figure 2.
Phase-Detector Bias (Pin 5):
L - .,...
This terminal should be dc biased as shown in Figures
1 and 2, and ac grounded with a bypass capacitor. The
OHICTOR
1-10
----1---
XR·210
bias resistor in series with this pin should be half as
large as those in series with Pin 4 and 6.
Fine Tune Control (Pin 9):
For a given choice of timing capacitor, CO, the VCO frequency can be further fine-adjusted to a desired frequency, f1' by means of a trimmer resistor, Rr. connected from Pin 9 to Pin 7, as shown in Figure 6. The fine
tuned VCO frequency, f1' is related to AT as:
Phase-Detector Outputs (Pin 2 and 3):
The low-frequency (or dc) voltage across these pins
corresponds to the phase difference between the two
signals at the phase-detector inputs (Pin 4 and 6).
These differential phase-detector outputs are internally
connected to the VCO control terminals. Pin 3 is also internally connected to the reference input of the voltage
comparator section.
f1 '" 220
Co
0 QJ)
+
RT
Hz
where Co is in /.IF, and RT is in kO.
VCO Timing Capacitor (Pin 13 and 14):
The VCO free-running frequency, fo, is inversely proportional to the timing capacitor, CO, connected between
Pin 13 and 14. With Pin 9 and 10 open-circuited, the
VCO frequency is related to Co as:
In normal use, the low-pass loop-filter capacitor, C1, is
connected between Pin 2 and 3. The 6 kO impedances
of the two outputs add to 12 kO in the single-pole RC
low-pass loop filter. Pin 2 is externally connected to the
voltage comparator input (Pin 1) through an RC lowpass filter.
fa '" 220 Hz
Co
Frequency-Keying Input (Pin 10):
The VCO frequency can be varied between two discrete
frequencies, f1 and f2' by connecting an external resistor, RX, to this terminal. Referring to Figure 6, the VCO
frequency is proportional to the sum of currents, 11 and
12, through the transistors, T1 and T2, on the monolithic
chip. These transistors are biased from a fixed internal
reference. The current, 11, is set internally, and is partially controllable by the fine-tune adjustment, AT. The
current, '2, is set by the external resistor, RX, connected between Pin 10 and Pin 7. For any Co setting, the
VCO frequency, f2' with RX connected to Pin 10, can be
expressed as:
f2 = f1
0 ~:)
+
where Co is in /.IF.
VCO Output (Pin 15):
The VCO produces approximately a 2.5V pop square
wave output signal at this pin. The dc output level is approximately 2 volts below VCC. This pin should be connected to Pin 7 through a 10 kO resistor to increase the
output current drive capability. For high-voltage operation (VCC > 20V), a 20 kO resistor is recommended. It
is also advisable to connect a 5000 resistor in series
with this output, for short-circuit protection.
Using the frequency-keying control, the VCO frequency
can also be stepped in a binary manner by applying a
logic signal to Pin 10, as shown in Figure 6. For highlevel logic inputs, the transistor, T2, is turned off, RX is
effectively switched out of the circuit, and the VCO frequency is shifted from f2 to f1.
Hz
where f1 is the frequency with Pin 10 open-circuited,
and RX is in kO. Note that f2 can be fine-tuned to a desired value by the proper choice of RX.
Voltage' Comparator Input (Pin 1):
This pin provides the signal input to the voltage comparator section. The comparator section is normally used
for post-demodulation slicing and pulse shaping. Normally. Pin 1 is connected to Pin 2 through a 15K external resistor, as shown in Figures 1 and 2. The input impedance level at this pin is approximately 2 MO.
VCO Sweep Input (Pin 12):
The VCO frequency can be swept over a broad range
by applying an analog sweep voltage, Vs to Pin 12 (see
Figure 5). The impedance level looking into the sweep
input is approximately 500. Therefore, for sweep applications, a current limiting resistor, RS, should be connected in series with this terminal. Typical sweep characteristics of the circuit are shown In Figure 5. The VCO
temperature dependence is minimal when the sweep
input is not used, and should be left open-circuited.
Logic Driver Output (Pin 8):
This pin provides a binary logic output corresponding to
the polarity of the input signal, at the voltage comparator inputs. It is a bare-coliector type stage with highcurrent sinking capability.
CAUTION: For safe operation of the circuit, the maximum current, 'S, drawn from the sweep terminal should
be limited to 5 mA or less, under all operating conditions.
Definition of Terms
Phase-Dejector Gain, Kd:
Kd is the output voltage from the phase detector per radian of phase difference at the phase-detector inputs
(Pin 4 and 6). Kd is proportional to the input signal for
low-level inputs (s25 mV rms), and is constant at highinput levels (see Figure 8).
VCO Conversion Gain (Pin 11):
The VCO voltage-to-frequency conversion gain, KO, is
inversely proportional to the value of the external gaincontrol resistor, RO, connected across Pin 11 and 12.
1-11
XR·210
.,,,;.,1 i" I~ L,~
v'
OR
GROUND
002
1-"<>--"-00-0"
"
"'OUI
ill
OUTPUT
VCOOU'~Vl
TOCOV,"HII
Figure 2. Test Circuit for Split Supply Operation
Figure 1. Test Circuits for Single Supply Operation
VCO Conversion Gain,
KO
z
1<0:
700
CORO
(radians/sec)/volt
where Co is in I'F and RO is in kO. For most applications, recommended values for RO range from 1 kO to
10 kO.
O.II'F
FS~H--4----o!lH
INPUT
When the XR-210 is connected as a PLL, its lock range
can be controlled by varying the VCO gain control resistor, RO, across Pin 11 and 12. For input signals greater
than 30 mV rms, the PLL loop-gain is independent of
signal amplitude, but is inversely proportional to RO.
Figure 7 shows the dependence of lock range, ± afL,
on RO.
Lock Range (awL):
Figure 3. Circuit Connection for FSK Demodulation
(Single Supply)
The range of frequencies in the vicinity of fa over which
the PLL can maintain lock with an input signal. If saturation or limiting does not occur, the lock range is equal to
the loop gain; i.e., aWL z KT = KdKo.
Capture Range (awC):
+5
The band of frequencies in the vicinity of fa where the
PLL can establish or acquire lock with an input signal. It
is also known as the acquisition range. It is always
smaller than the lock range, and is related to the lowpass filter bandwidth. It can be approximated by a parametric equation of the form:
I/~
§
w
(!l
~
0
J:
U
>-
U
Z
w
where IF(jawC) I is the low-pass filter magnitude response at w = awC. For a simple lag filter, it can be expressed as:
=>
-
5l -s
a:
"-
o
~
-10
APPLICATIONS INFORMATION
o
I
5
10
15
20
TOTAL SUPPLY VOLTAGE (VOLTS)
2S
FSK Demodulation
Figure 3 shows a generalized circuit connection for
FSK demodulation. The circuit is connected as a PLL
Figure 4. VCO Frequency Variation as a Function of Supply
Voltage
1-12
§.O
i)
5
>U
2
w
:J
4
Cl
w
a:
u.
-
3
0
w
N
::i
;
Vs
ffi~
2K
>2 ~
1
/'
1.0
I
8~
/
a:~
O-J
f-O
<1:>
a:-
~ l><~
(NOTE: VSO ~"VCC - 5V = Open Circuit Voltage at pin 12)
0.1
02
~ 10V
S3 closed, S4 open,
0< Vs < 6V
See Figure 9, Co = 2000 pF
S5 open
10 pF to ground at Pin 15
Yin > 50 mV rms (See
characteristic curves)
Measured looking into Pins 2 or 3
Measured across Pins 2 and 3
Yin = 0, S5 open
S2 open
AV = 1
RL
= 30 kO from
Pin 8 to ground
nA
dB
0.8
500
0.15
40
65
250
0) Tracking Filter
Test Conditions: Test circuit 01 Figure 5, V+
Tracking Range (% of fa)
=
kO
mV
dB
VII' sec
MO
kO
80
2.5
2
2
10
1
80
90
66
II-SPECIAL APPLICATIONS
A) FM Demodulation
Test Conditions: Test circuit of Figure 4, V+
100
Figure
Figure
Figure
Figure
=
10.7 MHz FM with "I
3
0.5
mVrms
mVrms
%
dB
dB
=
75 ~Hz, fmod
=
1 kHz.
500 source
Measured at Pin 8
Yin
=
10 mV rms, 30% AM
1 MHz, Vin '" 100 mV rms, 500 source.
±50
See Figures 5 and 25
Discriminator Output
"Vout
50
mVI%
"fifo
EQUIVALENT SCHEMATIC DIAGRAM
1-15
Adjustable information
See applications
XR·215
veo output (pin 15) to complete the PLL (see Figure 2).
DESCRIPTION OF CIRCUIT CONTROLS
For split supply operation, these inputs are biased from
ground as shown in Figure 3. For single supply operation, a resistive bias string similar to that shown in
Figure 2 should be used to set the bias level at approximately Vee/2. The dc bias current at these terminals is
nominally 8 p.A.
PHASE COMPARATOR INPUTS (PINS 4 ANO 6)
One input to the phase comparator is used as the signal
input; the remaining input should be ac coupled to the
PHASE COMPARATOR BIAS (PIN 5)
This terminal should be dc biased as shown in Figures
2 and 3, and ac grounded with a bypass capacitor.
DE MOO
OUTPUT
"""
vco
OUTPUT
ITOCOUNTflU
[J1$CIHMI'IIA10R
OUTPUT
XR·215
Figure 2. Test Circuit For Single Supply Operation
\ICC
OUTPUT
..
XA 215
so---,
J!.o!!
COUI'II"'t, tAI'ACITOR
lI'1'I'A"~
CAPAn!!I"
Figure 5. Test Circuit For Tracking Filter
IItMt)[IlJllITIII
10K
Cr
(H
OUTPuT
p
1
!
-:;
4~6V
'800
>-
~
~
~
VC(JIJ"'PIJ!
'TtJnIlJ~.rIIC,
""NA'f
INI'UT
1501!
SllunC~1
,400
Q
15
w
0
01
0,,..1
"r
"-
u
w
a:
DI-
"
400 I-
~
01
",
~
~
Figure 3. Test Circuit For Split-Supply Operation
.1.
BOO
10 KHl
0
U
100 KH/
>
1 MHl
10MHz
FREOUENCY
Figure 6. Typical YCO Temperature Coefficient Range as a
Function of Operating Frequency (pin 10 open)
10'r-~~~-------------------------,
RX
~ 106
7501l BETWEEN PINS 9 AND 10
0
u
w
u
z
veo
U 10'
OUTPUT
"
J
105
;:.
:;.
u
"
":;z
103
;: 10 2
'1:/V
O
10
'"
10
10 2
10'
veo FREOUENCY (Hz)
Figure 4. Test Circuit For FM Demodulation
Figure 7. YCO Free Running Frequency vs Timing Capacitor
1-16
XR·215
l00dBr------r------r_----------~----__,
PHASE COMPARATOR OUTPUTS (PINS 2 AND 3)
The low frequency (or dc) voltage across these pins
corresponds to the phase difference between the two
signals at the phase comparator inputs (pins 4 and 6).
The phase comparator outputs are internally connected
to the veo control terminals (see Figure 1). One of the
outputs (pin 3) is internally connected to the noninverting input of the operational amplifier. The low-pass
filter is achieved by connecting an Re network to the
phase comparator outputs as shown in Figure 14.
BOdB~..::..:.:.=::::,.::..;:::
WdB~~--_+------~,
40dB~~~~------r-~--_r~
VCO TIMING CAPACITOR (PINS 13 AND 14)
OdB~~~_r--~--r_----~----_1,
The veo free-running frequency, fo, is inversely proportional to timing capacitor eO connected between pins
13 and 14. (See Figure 7).
-20 dB L-l.-.L...l..J.L..l..--L...u.1-1-l...L:':I::J...-'-~::_:_'---'':''_'u
100 H
VCO OUTPUT (PIN 15)
1 KHz
Figure 10. XR-215 Op Amp Frequency Response
The veo produces approximately a 2.5 Vp_p output signal at this pin. The dc output level is approximately
2 volts below Vee. This pin should be connected to pin
9 through a 10 ko resistor to increase the output current drive capability. For high voltage operation (Vee>
20V), a 20 ko resistor is recommended. It is also advisable to connect a 5000 resistor in series with this output for short circuit protection.
VCO SWEEP INPUT (PIN 12)
The veo Frequency can be swept over a broad range
by applying an analog sweep voltage, VS, to pin 12 (see
Figure 9). The impedance level looking into the sweep
input is approximately 500. Therefore, for sweep applications, a current limiting resistor, RS, should be connected in series with this terminal. Typical sweep characteristics of the circuit are shown in Figure 9. The veo
temperature dependence is minimum when the sweep
input is not used.
HIGH LEVEL INPUT
CONSTANT· IV. Iml
CAUTION: For safe operation of the circuit, the maxi-
lOW LEVEL INPUT AMPLITUOE ImV. 1m"
mum current, IS, drawn from the sweep terminal should
be limited to 5 mA or less under all operating conditions.
Figure B. Phase Comparator Conversion Gain, Kd, versus
Input Amplitude
~
ON-OFF KEYING: With pin 10 open circuited, the veo
can be keyed off by applying a positive voltage pulse to
the sweep input terminal. With RS = 2 ko, oscillations
will stop if the applied potential at pin 12 is raised
3 volts above Its open-circuit value. When sweep, sync,
or on-off keying functions are not used, RS should be
left open circuited.
4
>
u
z
~ J
Sl
:::
~
2
::;
"
~
o
z
INTERNAL
:;i~;-;-~~r::...,-+-,I~tJo--r--kl---o
'O'A-:S
Bias Pins 1,4,5,6 to Vcc/2
I
J:
f
600~l
-2
-4
-6
-8
-10
AX
'2
-12
'.
12
(1'~:)
NET APPLIED SWEEP VOLTAGE. "S - VSO (VOLTS)
Figure 9. Typical Frequency Sweep Characteristics as a
Function of Applied Sweep Voltage
Figure 11. Explanation of VCO Range-Select Controls
(Note: VSO ... VCC - 5V = Open Circuit Voltage at pin 12)
1-17
·~v
INPUT
13\1
0\1 f
-2
I,
HAN{it- S[ LEel
XR·215
RANGE-SELECT (PIN 10)
tem comprised of three basic functional blocks: phase
comparator, low-pass filter and voltage-controlled oscillator (VeO). The basic principle of operation of a PLL
can be briefly explained as follows: with no input signal
applied to the system, the error voltage Vd, is equal to
zero. The veo operates at a set frequency, fo, which is
known as the "free-running" frequency. If an input signal is applied to the system, the phase comparator
compares the phase and frequency of the input signal
with the
frequency and generates an error voltage,
Ve(t), that is related to the phase and frequency difference between the two signals. This error voltage is then
filtered and applied to the control terminal of the
If
the input frequency, fs, is sufficiently close to fo, the
feedback nature of the PLL causes the veo to synchronize or "lock" with the incoming signal. Once in lock,
the veo frequency is identical to the input Signal, except for a finite phase difference.
The frequency range of the XR-215 can be extended by
connecting an external resistor, RX, between pins 9 and
10. With reference to Figure 11, the operation of the
range-select terminal can be explained as follows: The
frequency is proportional to the sum of currents 11
and 12 through transistors Tt and T2 on the monolithic
chip. These transistors are biased from a fixed internal
reference. The current 11 is set internally, whereas 12 is
set by the external resistor RX. Thus, at any eO setting,
the veo frequency can be expressed as:
veo
fo = f1 (:
+
veo
veo.
~:)
where f1 is the frequency with pin 10 open circuited
and RX is in kO. External resistor RX ('" 7500) is recommended for operation at frequencies in excess of
5 MHz.
A LINEARIZED MODEL FOR PLL
The range select terminal can also be used for fine tuning the veo frequency, by varying the value of RX. Similarly, the
frequency can be changed in discrete
steps by switching in different values of RX between
pins 9 and 10.
When the PLL is in lock, it can be approximated by the
linear feedback system shown in Figure 13. q,s and q,o
are the respective phase angles associated with the input signal and the veo output, F(s) is the low-pass filter
response in frequency domain, and Kd and Ko are the
conversion gains associated with the phase comparator and veo sections of the PLL.
veo
DIGITAL PROGRAMMING
veo
Using the range select control, the
frequency can
be stepped in a binary manner, by applying a logic signal to pin 10, as shown in Figure 11. For high levellcilic
inputs, transistor T2 is turned off, and RX is effectively
switched out of the circuit. Using the digital programming capability, the XR-215 can be time-multiplexed between two separate input frequencies, as shown in
Figures 18 and 19.
DEFINITION OF XR-215 PARAMETERS FOR
PLL APPLICATIONS
VCO FREE-RUNNING FREQUENCY,
'0
The veo frequency with no input signal. It is determined by selection of eO across pins 13 and 14 and can
be increased by connecting an external resistor RX between pins 9 and 10. It can be approximated as:
AMPLIFIER INPUT (PIN 1)
fo
This pin provides the inverting input for the operational
amplifier section. Normally it is connected to pin 2
through a 10 kO external resistor (see Figure 2 or 3).
= 200 (: + 0.6)
eO
RX
where eO is in /LF and RX is in kO. (See Figure 7).
AMPLIFIER OUTPUT (PIN 8)
This pin is used as the output terminal for FM or FSK
demodulation. The amplifier gain is determined by the
external feedback resistor, RF, connected between pins
1 and 8. Frequency response characteriRtics of the amplifier section are shown in Figure 10.
AMPLIFIER COMPENSATION (PIN 7)
Figure 12. Block Diagram of a Phase-Locked Loop
The operational amplifier can be compensated by a single 300 pF capacitor from pin 7 to ground. (See Figure
10).
¢,
BASIC PHASE-LOCKED LOOP OPERATION
PRINCIPLE OF OPERATION
The phase-locked loop (PLL) is a unique and versatile
circuit technique which provides frequency selective
tuning and filtering without the need for coils or inductors. As shown in Figure 12, the PLL is a feedback sys-
Figure 13. Linearized Model of a PLL as a Negative
Feedback System
1-18
XR·215
LAG· LEAD FILTER
LAG FILTER
PHASE COMPARATOR GAIN Kd
The output voltage from the phase comparator per radian of phase difference at the phase comparator inputs
(pins 4 and 6).
VCO CONVERSION GAIN
,
Ko
fed "I. 2R,C 11
The VCO voltage·to-frequency conversion gain is determined by the choice of timing capacitor Co and gain
control resistor, RO connected externally across pins 11
and 12. It can be expressed as
1<0 '"
I I
C
700 (radians/sec)/volt
CORO
fll)·
,.
C
'
A,
!e·li~~RlR21
Figure 14.
and 3. The low-pass filter components can be connected either between pins 2 and 3 or, from each pin to
ground. Typical filter configurations and corresponding
filter transfer functions are shown in Figure 14 where
R1 (6 kO) is the internal impedance at pins 2 and 3.
(~wL)
The range of frequencies in the vicinity of fo, over
which the PLL can maintain lock with an input signal. It
is also known as the "tracking" or "holding" range. If
saturation or limiting does not occur, the lock range is
equal to the loop gain, i.e. ~wL '" KT = Kd 1<0.
CAPTURE RANGE
'
A,
where Co is in /LF and RO is in kO. For most applications, recommended values for RO range from 1 kO to
10 kO.
LOCK RANGE
~
1:
APPLICATIONS INFORMATION
FM OEMODULATION
(~wc)
Figure 15 shows the external circuit connections to the
XR-215 for frequency-selective FM demodulation. The
choice of Co is determined by the FM carrier frequency
(see Figure 7). The low-pass filter capacitor C1 is determined by the selectivity requirements. For carrier frequencies of 1 to 10 MHz, C1 is in the range of 10 Co to
30 CO. The feedback resistor RF can be used as a
"volume-control" adjustment to set the amplitude of
the demodulated output. The demodulated output amplitude is proportional to the FM deviation and to resistors RO and RF For ± 1 % FM deviation it can be approximated as:
The band of frequencies in the vicinity of fo where the
PLL can establish or acquire lock with an input signal. It
is also known as the "acquisition" range. It is always
smaller than the lock range and is related to the lowpass filter bandwidth. It can be approximated by a parametric equation of the form:
~wC '" ~wLIF(j~wc)1
where I F(j~wcl is the low-pass filter magnitude response at w = ~wC. For a simple lag filter, it can be expressed as:
VOUT '" RORF
0 ~~)
+
mY, rms
where T 1 is the filter time constant.
AMPLIFIER GAIN AV
The voltage gain of the amplifier section is determined
by feedback resistors RF and Rp between pins (8,1)
and 2,1) respectively. (See Figures 2 and 3). It is given
by:
-RF
AV=--R1 + Rp
where R1 is the 6 kO internal impedance at pin 2, and
Rp is the external resistor between pins 1 and 2.
LOW·PASS FILTER
Cc COUPLING CAPACITOR
Ca BYPASS C,.tJ>ACITOR
The low-pass filter section is formed by connecting an
external capacitor or RC network across terminals 2
Figure 15. Circuit Connection for FM Demodulation
1-19
XR·215
where all resistors are in kll and RX is the range extension resistor connected across pins 9 and 10. For circuit operation below 5 MHz, RX can be open circuited.
For operation above 5 MHz, RX .. 7501l is recommended.
Typical output signal/noise ratio and harmonic distortion are shown in Figures 16 and 17 as a function of FM
deviation, for the component values shown in Figure 4.
MULTI-CHANNEL DEMODULATION
The ac digital programming capability of the XR-215 allows a single circuit be time-shared or multiplexed between two information channels, and thereby selectively demodulate two separate carrier frequencies. Figure
18 shows a practical circuit configuration for timemultiplexing the XR-215 between two FM channels, at
1 MHz and 1.1 MHz respectively. The channel-select
logic signal is applied to pin 10, as shown in Figure 18
with both input channels simultaneously present at the
PLLinput (pin 4). Figure 19 shows the demodulated output as a function of the channel-select pulse where the
two inputs have sinusoidal and triangular FM modulation respectively.
Figure 18. Tlme-MuHiplexing XR-215 Between Two
Simultaneous FM Channels
.
~ l00.-----------~_,
~
'0: IOMHI
~
'mod = 1 kHz
V IN ' 20mV mil
<
z
u;" BO
(TEST CIRCUIT OF FIGURE 41
~
~
Figure 19. Demodulated Output Waveforms for
Time-MuHiplexed Operation
~
o
~ 60
3
Top: Demodulated Output
Sinewave - Channel 1
Triangle Wave - Channel 2
il
~
~ ~~':::o,,,...,--::-':::---.~I('"-,--.-:!:''''",---.-:-:!,00''-,,
Bottom: Channel Select
Pulse
FREQUENCy DEVIATiON, ;.1 fo
Figure 16. Output Signal/Noise Ratio as a Function of FM
Deviation
3) is ac grounded and serves as the bias reference for
the operational amplifier section. Capacitor C1 serves
as the PLL loop filter, and C2 and C3 as post-detection
filters. Range select resistor, RX, can be used. as a finetune adjustment to set the VCO frequency.
oe".------------_,
tu
IClMt"
',,,Od
VIN
VOU1
I ..... '
~OmV"l'~
CONST ANT"" '2 VI' II
Typical component values for 300 baud and 1200 baud
operation are listed below:
!TEST CIRCUIT OF fiGURE 41
OPERATING
CONDITIONS
·~~t"-:-"..--·:::-o'::-,·.----,.7,o""·"--'~'":-"--.:!.
FHEUUENCY DEViATION·· .. I"
TYPICAL COMPONENT
VALUES
300 Baud
Figura 17. Output Distortion as a Function of FM Deviation
Low Band: 11 = 1070 Hz
12 = 1270 Hz
FS.K DEMODULATION
High Band: 11 = 2025 Hz
Figure 20 contains a typical circuit connection for FSK
demodulation. When the input frequency is shifted, corresponding to a data bit, the dc voltage at the phase
comparator outputs (pins 2 and 3) also reverses polarity. The operational amplifier section is connected as a
comparator, and converts the dc level shift to a binary
output pulse. One of the phase comparator outputs (pin
12 = 2225 Hz
1200 Baud
11 = 1200 Hz
12 = 2200 Hz
1-20
RO = 5 kll, Co = 0.17 p.F
01 = C2 = 0.047 p.F,
C3 = 0.033 p.F
RO = 8 kll, Co =-0.1 p.F
C1 = C2 = C3 = 0.033 "F
RO = 2kll,CO = 0.12"F
C1= C3 =.0.003 "F,
C2 = 0.01"F
XR·215
Note that for 300 Baud operation the circuit can be
time-multiplexed between high and low bands by
switching the external resistor RX in and out of the circuit with a control signal, as shown in Figure 11.
,"
FSK GENERATION
The digital programming capability of the XR-215 can
be used for FSK generation. A typical circuit connection for this application is shown in Figure 21. The VCO
frequency can be shifted between the mark (f2) and
space (fl) frequencies by applying a logic pulse to pin
10. The circuit can provide two separate FSK outputs: a
low level (2.5 Vp_p) output at pin 15 or a high amplitude
(10 Vp_p) output at pin 8. The output at each of these
terminals is a symmetrical squarewave with a typical
second harmonic content of less than 0.3 %.
6IN"'II"
AAfIIGESELECT
IOPTIO"A.lO
Figure 22. Circuit Connection For Frequency Synthesis
follows: The counter divides down the oscillator frequency by the programmable divider modulus, N. Thus,
when the entire system is phase-locked to an input signal at frequency, fs, the oscillator output at pin 15 is at a
frequency (Nf s), where N is the divider modulus. By
proper choice of the divider modulus, a large number of
discrete frequencies can be synthesized from a given
reference frequency. The low-pass filter capacitor Cl is
normally chosen to provide a cut-off frequency equal to
0.1 % to 2 % of the signal frequency, f s .
The circuit was designed to operate with commercially
available monolithic programmable counter circuits using TTL logic, such as MC4016, SN5493 or equivalent.
The digital or analog tuning characteristics of the VCO
can be used to extend the available range of frequencies of the system, for a given setting of the timing capaCitor CO.
Figure 20. Circuit Connection for FSK Demodulation
Typical input and output waveforms for N = 16 operation with fs = 100 kHz and fo = 1.6 MHz are shown in
Figure 23.
TRACKING FILTER/DISCRIMINATOR
The wide tracking range of the XR-215 allows the system to track an input signal over a 3:1 frequency range,
JlJUL
'!
' ..
FSK OUTPUT
ilOWL[VElJ
i25V p _p l
Figure 21. Circuit Connection For FSK Generation
FREQUENCY SYNTHESIS
In frequency synthesis applications, a programmable
counter or divide-by-N circuit is connected between the
VCO output (pin 15) and one of the phase detector inputs (pins 4 or 6), as shown in Figure 22. The principle
of operation of the circuit can be briefly explained as
Figure 23. Typical Input/Output Waveforms For N
Top: Input (1 DO kHz)
Bollom: VCO Output (1.6 MHz)
Vertical Scale 1 V/cm
1-21
=
16
XR·215
'OOO~-r----------------~--~
flO·:2 KO
'00
[)ISCHIMIt./A r OR
'0
OutpuT
1.0o!-:.--.L.....J......I.....I.~~----.l----~2.0
NORMALIZED TRACKrNu RANGE, 111101
Figure 25. Tracking Range vs Input Amplitude (Pin 10
Open Circuited)
3DOpF
·3.---'1<:"'"--------,.--------------,
Cc COUPLING CAPACITOR
C, BYPASS CAPACITOR
~
'2
~
.,
~
~
Figure 24. Circuit Connection For Tracking Filter Applications
5
.
~
centered about the veo free running frequency. The
tracking range is maximum when the binary rangeselect (pin 10) is open circuited. The circuit connections for this application are shown in Figure 24_ Typical
tracking range for a given input signal amplitude is
shown in Figure 25. Recommended values of external
components are: 1 ko < RO < 4 kO and 30 Co < C1 <
300 eO where the timing capacitor Co is determined by
the. center frequency requirements (see Figure 7).
OF FREOUENCY
i
Or-L-------~~--------,_~
::::i
·1
~
o
z
-2
V,n
&OmY .• ""
.~':-.---:o'='.---:o!-:.---:,..,o-----,LI2:--....J..,...:>Io-l,•
NORMALIZED FREOUENCY, 's!lg
Figure 26. Typical Discriminator Output Characteristics For
Tracking Filter Applications
"1Vo---..,o~'r(r-~r---'
The phase-comparator output voltage is a linear measure of the veo frequency deviation from its freerunning value. The amplifier section, therefore,can be
used to provide a filtered and amplified version of the
loop error voltage. In this case, the dc output level at
pin 15 can be adjusted to be directly proportional to the
difference between the VCO free-running frequency, fo,
and the input Signal, f s. The entire system can operate
as a "linear discriminator" or analog "frequencymeter" over a 3:1 change of input frequency. The discriminator gain can be adjusted by proper choice of RO
or Rf. For the test circuit of Figure 24, the discriminator
output is approximately (0.7 RORF) mV per % of frequency deviation where RO and RF are in kO. Output
non-linearity is typically less than 1 % for frequency deviations up to ± 15 %. Figure 27 shows the normalized
output characteristics as a function of input frequency,
with RO = 2 kO and RF = 36 kO.
i~~-'
INPUT
S'G~Hr+--o'-+--i
ru'.
00'
VOQ
OUTPUT
CRYSTAL-CONTROLLED PLL
~f
<0,01"
~K
L....~----'--'
O.Q'joIF
Figure 27. Typical Circuit Connection For Crystal-Controlled
FM Detection
The XR-215 can be operated as a crystal-controlled
phase-locked loop by replacing the timing capacitor
with a crystal. A circuit connection for this application
is shown in Figure 26. Normally a small tuning capacitor ('" 30 pF) is required in series with the crystal to set
the crystal frequency. For this application the crystal
should be operated in its fundamental mode. Typical
pull-in range of the circuit is ± 1 kHz at 10 MHz.
1-22
XR·2211
FSK Demodulator/Tone Decoder
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2211 Is a monolithic phase-locked loop (Pll)
system especially designed for data communications. It
Is particularly well suited for FSK modem applications.
It operates over a wide supply voltage range of 4.5 to
20V and a wide frequency range of 0.01 Hz to 300 kHz.
It can accommodate analog signals between 2 mV and
3V, and can interface with conventional DTl, TIL, and
ECl logic families. The circuit consists of a basic Pll
for tracking an input signal within the pass band, a
quadrature phase detector which provides carrier detection,and an FSK voltage comparator which provides
FSK demodulation. External components are used to independently set center frequency, bandwidth, and output delay. An internal voltage reference proportional to
the power supply provides ratio metric operation for low
system performance variations with power supply
changes.
r
OUTPUTS 0
L
NC
OATA
OUTPUT
FSK
COMPINPUT
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-2211M
XR-2211CN
XR-2211CP
XR-2211N
XR-2211P
Ceramic
Ceramic
Plastic
Ceramic
Plastic
- 55·C to + 125·C
O·C to +70·C
O·C to +70·C
-40·C to +85·C
-40·C to +85·C
SYSTEM DESCRIPTION
The main Pll within the XR-2211 is constructed from
an input preamplifier, analog multiplier used as a phase
detector, and a precision voltage controlled oscillator
(VCO). The preamplifier is used as a limiter such that input signals above typically 2MV RMS are amplified to a
constant high level signal. The multiplying-type phase
detector acts as a digital exclusive or gate. Its output
(unfiltered) produces sum and difference frequencies of
the input and the VCO output, f input + f input (2f input)
and f input - f Input (0 Hz) when the phase detector output to remove the "sum" frequency component while
passing the difference (DC) component to drive the
VCO. The VCO is actually a current controlled oscillator
with its nominal input current (fo) set by a resistor (RO)
to ground and its driving current with a resistor (R1)
from the phase detector.
20V
3V rms
5.0 mW/·C
REF
VOLTAGE
OUT
LOCK 0
ABSOLUTE MAXIMUM RATINGS
+ 25·C
DET.
OUT
DETECT
FSK Demodulation
Data Synchronization
Tone Decoding
FM Detection
Carrier Detection
=
LOOP
GROUND
APPLICATIONS
750 mW
6 mV/·C
TIMING
RESISTOR
FILTER
Wide Frequency Range
0.01 Hz to 300 kHz
4.5V to 20 V
Wide Supply Voltage Range
DTUTILlECl logic Compatibility
FSK Demodulation, with Carrier Detection
Wide Dynamic Range
2 mV to 3 V rms
Adjustable Tracking Range (± 1 % to ± 80 %)
Excellent Temp. Stability
20 ppm/·C, typo
+ 25·C
J
LOCK
eeTeCT
FEATURES
=
TIMING
CAPACITOR
INPUT
The XR-2211 is available in 14 pin DTl ceramic or plastic packages specified for commercial or military temperature ranges.
Power Supply
Input Signal level
Power Dissipation
Ceramic Package
Derate Above TA
Plastic Package
Derate Above TA
l
+vcc
The other sections of the XR-2211 act to: determine if
the VCO is driven above or below the center frequency
(FSK comparator); produced both active high and active
low outputs to indicate when the main Pll is in lock
(quadrature phase detector and lock detector comparator).
1-23
XR·2211
ELECTRICAL CHARACTERISTICS
Test CondHlons:.Test Circuit of Figure 1, V + = V - = 6V, TA = + 25·C, C = 5000 pF, R1 = R2 = R3 = R4 = 20 kO,
RL = 4.7 kO. Binary Inputs grounded, S1 and S2 closed, unless otherwise specified.
XR-2211C
XR-2211/2211M
PARAMETER
GENERAL
MIN
Supply Voltage
Supply Current
4.5
TVP
MAX
MIN
TVP
MAX
UNITS
20
7
4.5
4
5
20
9
V
mA
±1
±3
±1
%
±20
0.05
0.2
300
±50
0.5
±20
0.05
0.2
300
ppm/·C
0.01
Hz
CONDITIONS
RO
~
10 kO. See Fig. 4
OSCILLATOR SECTION
Frequency Accuracy
Frequency Stability
Temperature
Power Supply
Upper Frequency Limit
Lowest Practical
Operating Frequency
Timing Resistor, RO
Operating Range
Recommended Range
100
0.01
2000
100
5
15
5
15
%N
.%N
kHz
2000
100
kO
kO
Deviation from fO = 1/ROCo
R1 = 1/2
See Fig. 8.
V+ = 12± 1V. See Fig. 7.
V+5 ± 0.5V. See Fig. 7 .
Ro = 8.2 kO, Co = 400 pF
RO = 2 MO, Co = 50,.F
See Fig. 5.
See Figs. 7 and 8.
LDOP PHASE DETECTOR SECTION
Peak Output Current
Output Offset Cu rrent
Output Impedance
Maximum Swing
±150 ±200 ±300
±1
1
±4
±5
±100 ±200 ±300
±2
1
±4
±5
,.A
,.A
MO
V
QUADRATURE PHASE DETECTOR
Peak Output Current
Output Impedance
Maximum Swing
100
Measured at Pin 11.
Referenced to Pin 10.
Measured at Pin 3.
,.A
150
1
11
150
1
11
MO
Vpp
20
20
kO
2
mV
rms
2
100
70
300
0.01
MO
nA
dB
mV
INPUT PREAMP SECTION
Measured at Pin 2.
Input Impedance
Input Signal
Voltage Required to
Cause Limiting
2
10
VOLTAGE COMPARATOR SECTIONS
Input Impedance
Input Bias Current
Voltage Gain
Output Voltage Low
Output Leakage Current
55
2
100
70
300
0.01
55
,.A
Measured at Pins 3 and 8.
RL = 5.1 kO
IC=3mA
Vo = 12V
INTERNAL REFERENCE
Voltage Level
Output Impedance
4.9
5.3
100
5.7
4.75
5.3
100
1-24
5.85
V
0
Measured at Pin 10.
XR·2211
This terminal is a low impedance pOint, and is Internally
biased at a dc level equal to VR. The maximum timing
current drawn from Pin 12 must be limited to s3 mA for
proper operation of the circuit.
Reference Voltage, VR (Pin 10): This pin is internally biased
at the reference voltage level, VR: VR = V +/2 - 650
mV. The dc voltage level at this pin forms an internal
reference for the voltage levels at Pins 5, 8, 11 and 12.
Pin 10 must be bypassed to ground with a 0.1 p.F capacitor for proper operation of the circuit.
lOOP
DATA
FILTER
FILTER
VCO Timing Capacitor (Pins 13 and 14): VCO frequency is
inversely proportional to the external timing capacitor,
CO, connected across these terminals (see Figure 5).
Co must be nonpolar, and in the range of 200 pF to 10
p.F.
VCO Frequency Adjustment: VCO can be fine-tuned by
connecting a potentiometer, RX, in series with RO at Pin
12 (see Figure 9).
VCO Free·Runnlng Frequency, fO: XR-221l does not have a
separate VCO output terminal. Instead, the VCO outputs are internally connected to the phase deteptor
sections of the circuit. However, for set-up or adjustment purposes, VCO free-running frequency can be
measured at Pin 3 (with CD disconnected), with no input and with Pin 2 shorted to Pin 10.
LOCK DETECT
FIL TEA
DESIGN EQUATIONS
LOCK DETECT
CaMP.
(See Figure 2 for definition of components.)
Figure 1. Functional Block Diagram of a Tone and FSK
Decoding System Using XR-2211
1. VCO Center Frequency, fO:
Loop Phase Detector Output (Pin 11): This terminal provides
a high impedance output for the loop phase detector.
The PLL loop filter is formed by Rl and C, connected
to Pin 11 (see Figure 2). With no input signal, or with no
phase error within the PLL, the dc level at Pin 11 is very
nearly equal to VR. The peak voltage swing available at
the phase detector output is equal to ± VR.
510 KII RB
RL
fO = 1/ROCO Hz
2. Internal Reference Voltage, VR (measured at Pin
10):
VR = V+/2 - 650 mV
3. Loop Low·Pass Filter Time Constant, T:
1
Y+
T
= R1Cl
4. Loop Damping,
1= 114
I:
~
VC1
5. Loop Tracking Bandwidth, ±AflfO:
AfifO = RO/Rl
INPUT
SIGNAL
~~~
-!-'
I
ILL
I
I,
I
to
I
'2
I
ILH
6. FSK Data Filter Time Constant, TF:
TF = RFCF
Figure 2. Generalized Circuit Connection for FSK and Tone
Detection
7. Loop Phase Detector Conversion Gain, K.p: (K.p is
VCO Control Input (Pin 12): VCO free-running frequency is
determined by external timing resistor, RO, connected
from this terminal to ground. The VCO free-running frequency, fO, is:
the differential dc voltage across Pins 10 and 11,
per unit of phase error at phase detector input):
K.p = 02VR/r volts/radian
fO = _l_Hz
ROCo
8. VCO Conversion gain, KO: (KO is the amount of
change in VCO frequency, per unit of dc voltage
change at Pin 11):
where Co is the timing capacitor across Pins 13 and 14.
For optimum temperature stability, RO must be in the
range of 10 KO to 100 KO see Figure 8).
Ko
1-25
= -lNRCORl Hz/volt
XR·2211
9. Total Loop Gain, Kr.
The recommended value is RO '" 20 KO. The final
value of RO is normally fine-tuned with the series potentiometer, RX.
KT = 211'Kt/>KO = 4/COR1 rad/sec/volt
10. Peak Phase Detector Current IA:
c) Calculate value of Co from design equation (1) or
from Figure 6:
IA = VR (volts)/25 mA
Co = 1/ROfO
APPLICATIONS INFORMATION
d) Calculate R1 to give a af equalto the mark space
deviation:
FSK DECODING:
R1 = RO[fO/(f 1 = f2)]
Figure 9 shows the basic circuit connection for FSK decoding. With reference to Figures 2 and 9, the functions of external components are defined as follows: RO
and Co set the PLL center frequency, R1 sets the system bandwidth, and C1 sets the loop filter time constant and the loop damping factor. CF and RF form a
one-pOle post-detection filter for the FSK data output.
The resistor RS (= 510 KO) from Pin 7 to Pin 8 introduces positive feedback across the FSK comparator to
facilitate rapid transition between output logic states.
e) Calculate C1 to set loop damping. (See design equation No.4.):
Normally,
t ..
112 is recommended.
Then: C1 = CO/4 for
t
= 112
f) Calculate Data Filter Capacitance, CF:
For RF = 100 KO, RS = 510 KO, the recommended
value of CF is:
Recommended component values for some of the most
commonly used FSK bands are given in Table 1.
CF .. 3/(Saud Rate) JLF
Design Instructions:
The circuit of Figure 9 can be tailored for any FSK decoding application by the choice of five key circuit components: RO, R1, CO, C1 and CF For a given set of FSK
mark and space frequencies, f1 and f2' these parameters can be calculated as follows:
Note: All calculated component values except RO can
be rounded to the nearest standard value, and RO can
be varied to fine-tune center frequency, through a series potentiometer, RX' (See Figure 9.)
a) Calculate PLL center frequency, fO:
f
_ f1
+
0 - -2-
f2
b) Choose value of timing resistor RO, to be in the
range of 10 KO to 100 KO. This choice is arbitrary.
IS
y+
~
s
t--1---
>
Ro.
i
WI
II:
II:
TO PHASE
OETECTOR
..
:>
u
t
iil
10
"o-10K
- -~~ ~
~
VIN MINIMUM ... V+
(PEAK)
V
V V f..- I-"'~
V
I-'"
V V
.--I-'" f..- H--f....
YREF
(~V+121
5 KII
.... V
H
"
rr
~
~
~
U
SUPPLY VOLTAGE. V+ (yOlTS!
'0K-] ± 2.8 mV
[ -Rx + 20K
Figure 4. Typical Supply Current vs V+ (Logic Outputs
Open Circuited)
Figure 3. Desensitizing Input Stage
1-26
H
XR·2211
1.0
""
"-
'"
f'...
..
3
{1
0.'
"\.
"
"- ~
"[\..
"
I'
"-
"\.;1,.
~!'-it~~~
••~~
I'\.'" 1'\..1,.
1,.~
"0+"
Ml,."~~~;,J'\: '\.
1"-
'\,,";, I'\..
100
"-
'\.
I'\.
'\.
f\...
r-.."-
I' [\.. "-
0.0 1
I" f',
lGOO
10(Hz)
'"
['\
"r\~"
1000
10,000
10 (Hz)
Figure 5. VCD Frequency vs Timing Resistor
Figure 6. VCD Frequency vs Timing CapacHor
1.02
t;
1.01
ffi
S
II.!
If
~
c
1.00
0.99
:II
~
0.l1li
0.97
IO=1kHz
R '10RO
5
5
-
~
...- ~
4~ ~
~~~
{/
,
2
!
3
4
5
'0
12
14
16
3
4
CURVE
I
/~
'1
Ro
5K
10K
30K
100 K'
300K
20
I-22
24
V+ (VOLTSt
TEMPERATURE
Figure 7. Typical fO vs Power Supply Characteristics
reI
Figure 8. Typical Center Frequency Drift vs Temperature
Figure 9. ClrcuH Connection for FSK Decoding
1·27
XR·2211
Design Example:
will be disabled at "low" state, until there is a carrier
within the detection band of the PPL, and the Pin 6 output goes "high," to enable the data output.
75 Baud FSK demodulator with mark space
frequencies of 1110/1170 Hz:
The minimum value of the lock detect filter capacitance
Co is inversely proportional to the capture range, ±
Afc. This is the range of incoming frequencies over
which the loop can acquire lock and is always less than
the tracking range. It is further limited by C1. For most
applications, Afc > Af/2. For RO = 470 KD, the approximate minimum value of CD can be determined by:
Step 1: Calculate fO: fO (1110 + 1170) (112) =
1140 Hz
Step 2: Choose RO - 20 KD (18 KD fixed resistor in
series with 5 KD potentiometer)
Step 3: Calculate Co from Figure 6: Co = 0.044 I'F
CD (J'F)
Step 4: Calculate R1: R1 = RO (2240/60) = 380 KD
Note: All values except RO can be rounded to nearest
standard value.
TONE DETECTION:
Table 1. Recommended Component Values for
Commonly Usad FSK Bands.
(See Circuit of Figura 9.)
FSK BAND
300 Btilicf -.-'"
11 = 2025 Hz
f2 = 2225 Hz
1200 Baud
f1 = 1200 Hz
f2 = 2200 Hz
Co = 0.027 p.F CF = 0.0022
C1 = 0.01 p.F
RO = 18 KD
R1 = 30 KD
'·1'· (I:.);
~~~
Figure 11 shows the generalized circuit connection for
tone detection. The logic outputs, Q and Q at Pins 5 and
6 are normally at "high" and "low" logic states, respectively. When a tone is present within the detection band
of the PLL, the logic state at these outputs become reversed for the duration of the input tone. Each logic output can sink 5 mA of load current.
COMPONENT VALUES
= 0.039 p.F
= 0.01 p.F
= 100 KD
Co = 0.022 p.F
C1 = 0.00471'F
R1 = 200 KD
Co
C1
R1
CF
RO
l6/capture range in Hz.
With values of CD that are too small, chatter can be observed on the lock detect output as an incoming signal
frequency approaches the capture bandwidth. Excessively large values of CD will slow the response time of
the lock detect output.
Step 5: Calculate C1: C1 = CO/4 = 0.011 I'F
300 Baud
f1 = 1070 Hz
F2 = 1270 H~
2:
= 0.0051'F
= 18 KD
Both logic outputs at Pins 5 and 6 are open collector
type stages, and require external pull-up resistors RL1
and RL2, as shown in Figure 11.
CF = 0.005 I'F
RO = 18 KD
~F
FSK DECODING WITH CARRIER DETECT:
The lock detect section of XR-2211 can be used as a
carrier detect option, for FSK decoding. The recommended circuit connection for this application is shown
in Figure 10. The open collector lock detect output, Pin
6, is shorted to data output (Pin 7). Thus, data output
CD
LOGIC
"'LJ'"
OUT'IIT
*
Q
0*
LOGIC
OUTPIIT
.IL..
Figure 11. .Circuit Connection for Tona Detection
With reference to Figures 2 and 11, the functions of the
external circuit components can be explained as follows: RO and Co set VCO center frequency; R1 sets the
detection bandwidth; C1 sets the low pass-loop filter
time constant and the loop damping factor. RL 1 and
RL2 are the respective pull-up resistors for the Q and
Qlogic outputs.
Daslgn Instructions:
Figure 10_ External Connectors for FSK Demodulation with
Carrier Detact Capability
The circuit of Figure 11 can be optimized for any tone
detection application by the choice of the 5 key circuit
components: RO, R1, CO, C1 and CD. For a given input,
Note: Data Output Is "Low" When No Carrier Is Presant.
1-28
\
\
XR·2211
the tone frequency, fS, these parameters are calcu·
lated as follows:
at Pin 11. Normally, a non·inverting unity gain op amp
can be used as a buffer amplifier, as shown in Figure
12.
a) Choose RO to be in the range of 15 KO to 100 KO.
This choice is arbitrary.
,..-_---_-0
b) Calculate Co to set center frequency, fO equal to fs
(see Figure 6): Co = 1/ROfS
c) Calculate R1 to set bandwidth ±.DOUW'UT
3. Loop Low-Pass Filter Time Constant,
T:
T
= R1C1
'f
\ = 1/4JNCO
C1
rv
"
where N is the external frequency divider modular
(See 2). If no divider is used, N = 1.
5. Loop Tracking Bandwidth, ±M/fO:
~f/fO =
RO/R1
6. Phase Detector Conversion Gain, K¢: (Kq, is the differential dc voltage across Pins 10 and 11, per unit
of phase error at phase-detector input) K¢ =
- 2VRhr volts/radian
Figura 10. Circuli Connection for FM Demodulation
7. vce Conversion Gain, KO: (KO is the amount of
change in vce frequency, per unit of dc voltage
change at Pin 10. It is the reciprocal of the slope of
conversion characteristics shown in Figure 9). KO
= -1IVRCOR1 Hz/volt
a) Choose vce center frequency fO to be the same as
FM carrier frequency.
b) Choose value of timing resistor RO, to be in the
range of 10 KO to 100 KO. This choice is arbitrary.
The recommended value is RO ;; 20 KO. The final
value of RO is normally fine-tuned with the series potentiometer, RX.
8. Total Loop Gain, Kr:
KT
= 211'K¢KO = 4/COR1
rad/sec/volt
9. Peak Phase-Detector Current, IA; available at pin 10.
c) Calculate value of Co from design equation (1) or
from Figure 6:
IA = VR (volts)/25 mA
Co = 1/ROfO
APPLICATION INFORMATION
d) Choose R1 to determine the tracking bandwidth, ~f
(see design equation 5). The tracking bandwidth, ~f,
should be set significantly wider than the maximum
input FM signal deviation, ~fSM' Assuming the
tracking bandwidth to be "N" times larger than
~fSM' one can re-unite design equation 5 as:
FM DEMODULATION:
XR-2212 can be used as a linear FM demodulator for
both narrow-band and wide-band FM signals. The generalized circuit connection for this application is shown
in Figure 10, where the vce output (pin 5) is directly
connected to the phase detector input (pin 16). The demodulated signal is obtained at phase detector output
(pin 10). In the circuit connection of Figure 10, the op
amp section of XR-2212 is used as a buffer amplifier to
provide both additional voltage amplification as well as
current drive capability. Thus, the demodulated output
signal available at the op amp output (pin 8) is fully buffered from the rest of the circuit.
~f
RO
~fSM
fO
R1
fO
-=-=N-Table I lists recommended values of N, for various
values of the maximum deviation of the input FM
signal.
In the circuit of Figure 10, ROCO set the vce center frequency, R1 sets the tracking bandwidth, C1 sets the
low-pass filter time constant. ep amp feedback resistors RF and RC set the voltage gain of the amplifier section.
Design Instructions:
The circuit of Figure 10 can be tailored to any FM demodulation application by a choice of the external components RO, R1, RC, Rf, Co and C1. For a given FM
center frequency and frequency deviation, the choice
of these components can be calculated as follows,
using the design equations and definitions given on
page 1-34, 1-35 and 1-36.
% Deviation of FM
SIgnal (~fSMIfO)
Recommended valua of
Bandwidth Ratio, N
(N = ~fI ~fSM)
1 % or less
1 to 3%
1 to 5%
5 to 10%
10 to 30%
30 to 50%
10
5
4
3
2
1.5
TABLE I
Recommended values of bandwidth ratio, N, for various
values of FM signal frequency deviation. (Note: N is the
ratio of tracking bandwidth ~f to max. signal frequency
deviation, ~fSM).
1-35
XR·2212
N is the modulus of the external frequency divider. Conversely, the VCO output frequency, f1 is equal to NfS.
e) Calculate C1 to set loop damping (see design equation 4). Normally, l" = 112 is recommended. Then, C1
= COl4 for l" = 112.
In the circuit configuration of Figure 11, the external
timing components, RO and CO, set the VCO freerunning frequency; R1 sets the tracking bandwidth and
C1 sets the loop damping, i.e., the low-pass filter time
constant (see design equations).
f) Calculate RC and RF to set peak output signal amplitude. Output signal amplitude, Vout, is given as:
Vout =
e:~M) (VR) (:~) [RC R: RF]
r---.---------------~~V<
In most applications, RF = 100 KO is recommended;
then RC, can be calculated from the above equation
to give desired output swing. The output amplifier
can also be used as a unity-gain voltage follower, by
open circuiting RC (i.e., RC = co).
0-;
INPUT
SIGNAL
t,
Note: All calculated component values except RO
can be rounded-off to the nearest standard value,
and RO can be varied to fine-tune center frequency,
through a series potentiometer, RX' (See Figure 10.)
OUTPUT "
V<
Design Example:
Demodulator for FM signal with 67 kHz carrier frequency with ± 5 kHz frequency deviation. Supply voltage is
+ 12V and required peak output swing is ± 4 volts.
5
Nfs
1<
·/4SL9QOR----------~~_4~~~----------------------------------------------+_----4-~
INPUT
300kU
19 kHz "ii '1
19 kHz > '1
~
:>
21 kHz
21 kHz
Q
is
Vee 0
0
Vec
Figure 4. Tone Detector
.4
.5YO-----P-........------.....-1~....----_1O_'.1~F
·'o-+-----+--------....u;;;::;...---------j
10KU
SKU
100K
GNDC>--------4_--------------~~--~~--------------------------------------------------~
-=-
'1&:10 kHz. 10 a 40 kH.z,IC1 '" IC2
=
Figure 5. Frequency Synthesizer
1-42
'h DM7473 DUAL JK FLlP·FLOP
Tone Decoders
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XR·567
Monolithic Tone Decoder
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-567 is a monolithic phase-locked loop system
designed for general purpose tone and frequency decoding. The circuit operates over a wide frequency
band of 0.01 Hz to 500 kHz and contains a logic compatible output which can sink up to 100 milliamps of
load current. The bandwidth, center frequency, and output delay are independently determined by the selection of four external components.
OUTPUT
fll TlR
lOW PASS
lOOP flL TER
Figure 1 contains a functional block diagram of the
complete monolithic system. The circuit consists of a
phase detector, low-pass filter, and current-controlled
oscillator which comprise the basic phase-locked loop;
plus an additional low-pass filter and quadrature detector that enable the system to distinguish between the
presence or absence of an input signal at the center
frequency.
ORDERING INFORMATION
FEATURES
Bandwidth adjustable from 0 to 14%
Logic compatible output with 100 mA current sinking
capability
High stable center frequency
Center frequency adjustable from 0.01 Hz to 500 kHz
Inherent immunity to false signals
High rejection of out-of-band signals and noise
Frequency range adjustable over 20:1 range by external resistor
Part Number
Package
Operating Temperature
XR-567M
XR-567CN
XR-567CP
Ceramic
Ceramic
Plastic
- 55°C to + 125°C
O°C to + 70°C
O°C to +70°C
SYSTEM DESCRIPTION
The XR-567 monolithic tone decoder consists of a
phase detector, low pass filter, and current controlled
oscillator which comprise the basic phase-locked loop,
plus an additional low pass filter and quadrature detector enabling detection on in-band signals. The device
has a normally high open collector output capable of
sinking 100 mAo
APPLICATIONS
Touch-Tonelli Decoding
Sequential Tone Decoding
Communications Paging
Ultrasonic Remote-Control
Telemetry Decoding
The input signal is applied to Pin 3 (20 kO nominal input
resistance). Free running frequency is controlled by an
RC network at Pins 5 and 6 and can typically reach 500
kHz. A capacitor on Pin 1 serves as the output filter and
eliminates out-of-band triggering. PLL filtering is accomplished with a capacitor on Pin 2; bandwidth and
skew are also dependant upon the circuitry here. Bandwidth is adjustable from 0% to 14% of the center frequency. Pin 4 is +VCC (4.75 to 9V nominal, 10V maximum); Pin 7 is ground; and Pin 8 is open collector output, pulling low when an in-band signal triggers the
device.
ABSOLUTE MAXIMUM RATINGS
Power Supply
to volts
Power Dissipation (package limitation)
Ceramic Package
385mW
Plastic Package
300mW
2.5 mW/oC
Derate Above +25°C
Temperature
Operating
XR-567M
-55°C to +125°C
XR-567CN/567CP
O°C to + 70°C
Storage
-65°C to +150°C
In applications requiring two or more 567-type devices,
consider the XR-2567 dual tone decoder. Where center
frequency accuracy and drift are critical, compare the
XR-567A. Investigate employing the XR-L567 in low
power circuits.
1-43
XR·567
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC
=
+5V. TA
= 25°C,'unless otherwise specilied.Test circuit 01 Figure 2.
PARAMETERS
MIN
LIMITS
TYP
MAX
UNITS
CONDITIONS
GENERAL
Supply Voltage Range
Supply Current
Quiescent XR-567M
XR-567C
Activated XR-567M
XR-567C
Output Voltage
Negative Voltage at Input
Positive Voltage at Input
4.75
6
7
11
12
9.0
V dc
8
mA
mA
mA
mA
V
V
V
10
13
15
15
-10
VCC + 0.5
RL
RL
RL
RL
=
=
=
=
20kO
20 kO
20 kO
20 kO
CENTER FREQUENCY
Highest Center Frequency
Center Frequency Stability
Temperature TA = 25°C
0< TA < 70°C
-55 < TA < +125°C
Supply Voltage
XR-567M
XR-567C
100
500
kHz
35
±60
±140
ppm/oC
ppm/oC
ppm/oC
See Figure 9
See Figure 9
See Figure 9
0.5
0.7
1.0
2.0
%IV
%IV
10 = 100 kHz
10 = 100 kHz
14
14
16
18
% 0110
% 0110
10 = 100 kHz
10 = 100 kHz
1
2
2
3
% 0110
% 0110
DETECTION BANDWIDTH
Largest Detection Bandwidth
XR-567M
XR-567C
Largest Detection Bandwidth Skew
XR-567M
XR-567C
Largest Detection Bandwidth Variation
Temperature
Supply Voltage
12
10
%/OC
%IV
±0.1
±2
Yin = 300 mV rms
Yin = 300 mV rms
INPUT
Input Resistance
Smallest Detectable Input Voltage
Largest No-Output Input Voltage
Greatest Simultaneous Out band
Signal to Inband Signal Ratio
Minimum Input Signal to Wideband
Noise Ratio
10
20
20
15
25
kO
mVrms
mVrms
IL = 100 mA, Ii = 10
IL = 100 mA, Ii = 10
+6
dB
-6
dB
Bn = 140 kHz
V
V
pA
IL = 30 mA, Yin = 25 mV rms
IL = 100 mA, Yin = 25 mV rms
ns
ns
RL = 500
RL = 500
OUTPUT
Output Saturation Voltage
Output Leakage Current
Fastest ON-OFF Cycling Rate
Output Rise Time
Output Fall Time
0.2
0.6
0.01
10/20
150
30
1-44
0.4
1.0
25
XR·567
DEFINITION OF XR-567 PARAMETERS
If the value of C3 becomes too large, the turn· on or
turn·off time of the output stage will be delayed until the
voltage change across C3 reaches the threshold volt·
age. In certain applications, the delay may be desirable
as a means of suppressing spurious outputs. Con·
versely, if the value of C3 is too small, the beat rate at
the output of the quadrature detector (see Figure 1)
may cause a false logic level change at the output.
(Pin 8)
CENTER FREQUENCY fo
fo is the free· running frequency of the current·
controlled oscillator with no input signal. It is deter·
mined by resistor Rl between pins 5 and 6, and capaci·
tor Cl from pin 6 to ground fo can be approximated by
fo",,_l-
The average voltage (during lock) at pin 1 is a function
of the inband input amplitude in accordance with the
given transfer characteristic.
R1 Cl
where Rl is in ohms and Cl is in farads.
Vcc
DETECTION BANDWIDTH (BW)
~5V
The detection bandwidth is the frequency range cen·
tered about fo, within which an input signal larger than
the threshold voltage (typically 20 mV rms) will cause a
logic zero state at the output. The detection bandwidth
corresponds to the capture range of the PLL and is de·
termined by the low·pass bandwidth filter. The band·
width of the filter, as a percent of '0' can be determined
by the approximation
BW
= 1070
~~F_+__~________- .
XR 567
Jf,
i
foC2
-
where Vi is the input signal in volts, rms, and C2 is the
capacitance at pin 2 in I'F.
LARGEST DETECTION BANDWIDTH
24K
The largest detection bandwidth is the largest frequen·
cy range within which an input signal above the thresh·
old voltage will cause a logical zero state at the output.
The maximum detection bandwidth corresponds to the
lock range of the PLL.
• Adlust for fo
100 kHl
II - 100 kHl, • 5V
c'
100033
Figure 2. XR-567 Test Circuit
DETECTION BAND SKEW
The detection band skew is a measure of how accu·
rately the largest detection band is centered about the
center frequency, fo . It is defined as (f max + fmin - 2
fo)/lo , where fmax and fmin are the frequencies corre·
sponding to the edges of the detection band. If neces·
sary, the detection band skew can be reduced to zero
by an optional centering adjustment. (See Optional
Controls).
INPUT
LOW PASS
F I L TE R
0---1
,..------00--'
XR
DESCRIPTION OF CIRCUIT CONTROLS
OUTPUT FILTER - C3 (Pin 1)
Capacitor C3 connected from pin 1 to ground forms a
simple low·pass post detection filter to eliminate spuri·
ous outputs due to out·of·band signals. The time con·
stant of the filter can be expressed as T3 = R3C3,
where R3 (4.7 kD) is the internal impedance at pin 1.
J1J1f
\AN
The precise value of C3 is not critical for most applica·
tions. To eliminate the possibility of false triggering by
spurious signals, it is recommended that C3 be ~ 2 C2,
where C2 is the loop filter capacitance at pin 2.
f
0
o
- _ . ' •• -
R,C 1
Figure 3. XR-567 Connection Diagram
1·45
567
XR·567
TYPICAL CHARACTERISTIC CURVES
,.
"r---r---r---r---,---,---,
'0·
'\
'\
,ol--+--+--\-
<
,
E
151--+---b~-b-~-__1-~
ffi
E, '0'
~
~
~
il
~
,
10C7~+--+-~~~--1-~
t
~
,
'\.
E
a
,o4
~ 0~
~ r--.... r-....
N
~
°4~-~-~~-~-~-~_-J,0'
°
100Hz
SUPPLY VOLTAGE - VOLTS
M~
M~
-
M~
M~
,
-
M~
%
,.
14
12.5
12
so
~
0
,
w
x
C
<
b
"
'0
0
z
~
>~
'.0
,..
~
-25
+25
r--.t--.
.......
50
~
!!,
~
>
'\
-2.0
~
..•
-3.0
~
u
!!
-4.0
"
ii'
'00
r--c,
10
°
BANDWIDTH - % OF '0
'0
~
BANDWIOTH - % OF
1 MHz
Figure 5. Largest Detection Bandwidth
Versus Operating Frequency
·300
,so
100 KHz
CENTER FREQUENCY
Figure 4. Supply CUllent Versus Supply
Voltage
~
>
E
,
10 KHz
1 KHz
r--.. I'-- I""---. c3
,03
'0,
2
3 4 5
'0
20 30 4050
BANDWIDTH (% of fol
Figure 12. Greatest Number 01 Cycles
Belore Output
100
XR·567
LOOP FILTER - C2 (Pin 2)
Capacitor C2 connected from pin 2 to ground serves as
a single pole, low-pass filter for the PLL portion of the
XR-567. The filter time constant is given by T 2 = R2C2,
where R2 (10 kG) is the impedance at pin 2.
INPUT
The selection of C2 is determined by the detection
bandwidth requirements, as shown in Figure 6. For additional information see section on "Definition of
XR-567 Parameters".
OUTPUT
The voltage at pin 2, the phase detector output, is a linear function of frequency over the range of 0.95 to 1.05
fo, with a slope of approximately 20 mV/% frequency
deviation.
Response to 100 mV rms tone burst.
RL = 100 ohms.
INPUT (Pin 3)
The input signal is applied to pin 3 through a coupling
capacitor. This terminal is internally biased at a dc level
2 volts above ground, and has an input impedance level
of approximately 20 kG.
INPUT
TIMING RESISTOR Rl AND CAPACITOR Cl (Pins 5 and 6)
The center frequency of the decoder is set by resistor
Rl between pins 5 and 6, and capacitor Cl from pin 6
to ground, as shown in Figure 3.
OUTPUT
Pin 5 is the oscillator squarewave output which has a
magnitude of approximately VCC - lAV and an aver·
age dc level of VCC/2. A 1 kG load may be driven from
this point. The voltage at pin 6 is an exponential triangle
waveform with a peak-to·peak amplitude of 1 volt and
an average dc level of VCC/2. Only high impedance
loads should be connected to pin 6 to avoid disturbing
the temperature stability or duty cycle of the oscillator.
Response to same input tone burst with wideband noise.
S
R
= -6 dB
R L = 100 ohms
Noise Bandwidth = 140 Hz
Figure 13. Typical Response
1. Rl and Cl should be selected for the desired center
frequency by the expression fo ~ l/Rl Cl. For optimum temperature stability, Rl should be selected
such that 2kG ,;; Rl ,;; 20 kG, and the R1Cl product
should have sufficient stability over the projected
operating temperature range.
LOGIC OUTPUT (Pin 8)
Terminal 8 provides a binary logic output when an input
signal is present within the pass-band of the decoder.
The logic output is an uncommitted, "base·collector"
power transistor capable of switching high current
loads. The current level at the output is determined by
an external load resistor, RL, connected from pin 8 to
the positive supply.
2. Low-pass capacitor, C2, can be determined from the
Bandwidth versus Input Signal Amplitude graph of
Figure 7. One approach is to select an area of oper·
ation from the graph, and then adjust the input level
and value of C2 accordingly. Or, if the input ampli·
tude variation is known, the required foC2 product
can be found to give the desired bandwidth. Constant bandwidth operation requires Vi > 200 mV
rms. Then, as noted on the graph, bandwidth will be
controlled solely by the foC2 product.
When an in-band signal is present, the output transistor
at pin 8 saturates with a collector voltage less than 1
volt (typically O.6V) at full rated current of 100 mAo If
large output voltage swings are needed, RL can be connected to a supply voltage, V +, higher than the VCC
supply. For safe operation, V + ,;; 20 volts.
OPERATING INSTRUCTIONS
3. Capacitor C3 sets the band edge of the low-pass filter which attenuates frequencies outside of the de·
tection band and thereby eliminates spurious out·
puts. If C3 is too small, frequencies adjacent to the
detection band may switch the output stage off and
on at the beat frequency, or the output may pulse off
and on during the turn-on transient. A typical minimum value of C3 is 2 C2.
SELECTION OF EXTERNAL COMPONENTS
A typical connection diagram for the XR-567 is shown
in Figure 3. For most applications, the following procedure will be sufficient for determination of the external
components Rl, Cl, C2, and C3.
1-47
XR·567
Conversely, if C3 is too large, turn-on and turn-off of
the output stage will be delayed until the voltage
across C3 passes the threshold value.
losing information due to turn-on transient or output
chatter is about 10 cycles/bit, which corresponds to an
information transfer rate of fo/l0 baud.
PRINCIPLE OF OPERATION
C2
= 130,
C3
= 26°I'F
fo
. The XR-567 is a frequency selective tone decoder system based on the phase-locked loop (PLL) principle.
The system is comprised of a phase-locked loop, a
quadrature AM detector, a voltage comparator, and an
output logic driver. The four sections are internally interconnected as shown in Figure 1.
fo
In situations where minimum turn-off time is of less importance than fast turn-on, the optional sensitivity adjustment circuit of Figure 14 can be used to bring the
quiescent C3 voltage closer to the threshold voltage.
Sensitivity to beat frequencies, nOise, and extraneous
Signals, however, will .be increased.
When an input tone is present within the pass-band of
the circuit, the PLL synchronizes or "locks" on the input signal. The quadrature detector serves as a lock indicator: when the PLL is locked on an input signal, the
dc voltage at the output of the detector is shifted. This
dc level shift is then converted to an output logic pulse
by the amplifier and logic driver. The logic driver is a
"bare collector" transistor stage capable of switching
100 mA loads.
+v
~,~"
L::JicI
OECREASE
SENSITIVITY
The logic output at pin 8 is normally in a "high" state,
until a tone that is within the capture range of the decoder is present at the input. When the decoder is
locked on an input signal, the logic output at pin 8 goes
to a "low" state.
XR-S67
C3
3
INCREASE
SENSITIVITY
_
I-=
R
-=
·V
DECREASE
SENSITIVITY
~
RB
2.SK
INCREASE
SENSITiVITY
. The cenier frequency of the detector is set by the freerunning frequency of the current-controlled oscillator in
the PLL. This free-running frequency, fo, is determined
by the selection of Rl and Cl connected to pins 5 and
6, as shown in Figure 3. The detection bandwidth is determined by the size of the PLL filter capacitor, C2; and
the output response speed is controlled by the output
filter capacitor, C3.
}
SILICON
DIODES FOR
TEMPE RATUR E
COMPENSATION
10PTIONALI
OPTIONAL CONTROLS
PROGRAMMING
Figure 14. Optional Sensitivity Connections
Varying the value of resistor Rl and/or capacitor Cl will
change the center frequency. The value of Rl can be
changed either mechanically or by solid state switches.
Additional Cl capaCitors can be added by grounding
them through saturated npn transistor-so
CHATTER
When the value of C3 is small, the lock transient and ac
components at the lock detector output may cause the
output stage to move through its threshold more than
once, resulting in output chatter.
SPEED OF RESPONSE
Although some loads, such as lamps and relays will not
respond to chatter, logic may interpret chatter as a series of output signals_. Chatter can be eliminated by
feeding a portion of the output back to the input (pin 1)
or, by increasing the size of capaCitor C3- Generally, the
feedback method is preferred since keeping C3 small
will enable faster operation. Three alternate schemes
for chatter prevention are shown in Figure 15. Generally, it is only necessary to assure that the feedback
time constant does not get so large that it prevents operation at the highest antiCipated speed.
The minimum lock-up time is inversely related to the
loop frequency. As the natural loop frequency is lowered, the turn-on transient becomes greater. Thus maximum operating speed is obtained when the value of capacitor C2 is minimum. At the instant an input signal is
applied its phase may drive the oscillator away from the
incoming frequency rather than toward it. Under this
condition, the lock-up transient is in a worst case situation, and the minimum theoretical lock-up time will not
be achievable.
The following expressions yield the values of C2 and
C3, in microfarads, which allow the maximum operating
speeds for various center frequencies. The minimum
rate that digital information may be detected without
SKEW ADJUSTMENT
The circuits shown in Figure 16 can be used to change
the position of the detection band (capture range) with1-48
XR·567
.y
.y
~"'
XR tlS1
HL
.y
Figure 18 shows Ufe proper method of redUCing the
loop gain for reducEld bandwidth. This technique will improve damping and permit faster performance under
narrow band operation. The reduced impedance level
at pin 2 will require a larger value of C2 for a given cutoff frequency.
RA
:100 TO IK
8
XR 56/
R,
",
C,
I
31
.y
10K
RL
10K
C,
cRt'
XR-561
10K
RA
200T01K
PERMITS
LOWER VALUE OF C,
'OPTIONAL
"::-
Figure 15. Methods of Reducing Challer
TV
aI"
LOWERS
fo
I-=-
UNlATOt
CA PREVENTS LATCH UP
XR-567
WHEN POWER SUPPLY IS
TURNED ON
C2
C2
RAISES
fo
I-=-
Figure 17. Output Latching
R
-=-
TV
R,
XR·S67
LOWERS
~ ~;K
I--.....--"IIV'.......
SOK
I
RAISES
RAISES
fo
fo
IJl
a:
>
fo
E
150
w
to
R3
lK
)
200
:<
100
>--
~
z
50
Figure 16. Connections to Reposition Detection Band
16
DETECT ION BAND
in the largest detection band (or lock range). By moving
the detection band to either edge of the lock range, input signal variations will expand the detection band in
one direction only. Since R3 also has a slight effect on
the duty cycle, this approach may be useful to obtain a
precise duty cycle when the circuit is used as an oscillator.
%
of fo
+V
OUTPUT LATCHING
In order to latch the output of the XR-567 "on" after a
signal is received, it is necessary to include a feedback
resistor around the output stage, between pin 8 and pin
1, as shown in Figure 17. Pin 1 is pulled up to unlatch
the output stage.
OPTIONAL SILICON
DIODES FOR
TEMPERATURE
COMPENSATION
BANDWIDTH REDUCTION
The bandwidth of the XR-567 can be reduced by either
increasing capacitor C2 or reducing the loop gain. Increasing C2 may be an undesirable solution since this
will also reduce the damping of the loop and thus slow
the circuit response time.
NOTE· ADJUST CONTROL FOR SYMMETRY OF
DETECTION BAND EDGES ABOUT f o .
Figure 18. Bandwidth Reduction
1-49
XR·567
+VCC
PRECAUTIONS
1. The XR-S67 will lock on signals near (2n + 1) fo and
produce an output for signals near (4n + 1) fo, for n
. = 0,1,2 - etc. Signals at S fo and 9 fo can cause an
unwanted output and should, therefore, be attenu·
ated before reaching the input of the circuit.
0.'
rt
2. Operating the XR-S67 in a reduced bandwidth mode
of operation at input levels less than 200 mV rms
results in maximum immunity to noise and out-band
signals. Decreased loop damping, however, causes
.the worst-case lock-up time to increase, as shown
by the graph of Figure 12.
~F
Q 1 = 2N2906
~,
-=
3. Bandwidth variations due to changes in the in-band
signal amplitude can be eliminated by operating the
XR-S67 in the high input level mode, above 200 mV.
The input stage is then limiting, however, so that outband signals or high noise levels can cause an apparent bandwidth reduction as the in-band signal is
suppressed. In addition, the limited input stage will
create in-band components from subharmonic signals so that the circuit components from subhar·
monic signals so that the circuit becomes sensitive
to signals at fo/3, fo/S etc.
2
XR-567
Co
v,o--j
0.1
3
6
~F
rt
-=
4
+VCC
Figure 19. Dual Time Constant Tone Decoder
can be used to detect the presence of the carrier signal. The output of the XR·S67 is used to turn off the FM
demodulator when no carrier is present, thus acting as
a squelch. In the circuit shown, an XR-21S FM demodulator is used because of its wide dynamic range, high
signal/noise ratio and low distortion. The XR-S67 will
detect the presence of a carrier at frequencies up to
SOO kHz.
4. Care should be exercised in lead routing and lead
lengths should be kept as short as possible. Power
supply leads should be properly bypassed close to
the integrated circuit and grounding paths should be
carefuily determined to avoid ground loops and undesirable voltage variations. In addition, circuits requiring heavy load currents should be provided by a
separate power supply, or filter capacitors increased
to minimize supply voltage variations.
ADDITIDNAL APPLICATIONS
DUAL TIME CONSTANT TONE DECODER
For some applications it is important to have a tone decoder with narrow bandwidth and fast response time.
This can be accomplished by the dual time constant
tone decoder circuit shown in Figure 19. The circuit has
two low-pass loop filter capacitors, C2 and C' 2. With no
input signal present, the output at pin 8 is high, transistor 01 is off, and C' 2 is switched out of the circuit. Thus
the loop low-pass filter is comprised of C2,which can
be kept as small as possible for minimum response
time.
,OOK
DEMOOULATED
OUTPUT
When an in-band signal is detected, the output at pin 8
will go low, 01 will turn on, and capacitor C'2 will be
switched in parallel with capacitor C2. The low·pass filter capacitance will then be C2 + C' 2. The value of C' 2
can be quite large in order to achieve narrow bandwidth. Notice that during the time that no input signal is
being received, the bandwidth is determined by capacitor C2.
NARROW BAND FM DEMODULATOR WITH
CARRIER DETECT
For FM demodulation applications where the bandwidth
is less than 10% of the carrier frequency, an XR-S67
Figure 20. Narrow Band FM Demodulator with Carrier Detect
1-S0
XR·567
DUAL TONE DECODER
other. Due to the internal biasing arrangement the
actual phase shift between the two outputs is typically 80°.
In dual tone communication systems, information is
transmitted by the simultaneous presence of two separate tones at the input. In such applications two XR-567
units can be connected in parallel, as shown in Figure
21 to form a dual tone decoder. The resistor and capacitor values of each decoder are selected to provide the
desired center frequencies and bandwidth requirements.
- -- .... ......
..II
-
VCC
~
~~ rJ ~.~
~~,
n
~ .
R,
NOR
INPUT
;~c~i0~~ 0--1
Vo
C'I C2I I C3
-=
~~
l~
~
~
f4 ~ ~ ~ ~
11!J . g
~j
~~ I~
.
Figure 22. Oscillator Output Waveform Available From CCO
Section.
Top: Square Wave Output at Pin 5:
Amplitude = (V+ -1.4V), pp.,
Avg. Value = V+ /2
Bottom: Exponential Triangle Wave at Pin 6:
Amplitude = 1V pp., Avg. Value = V+ 12
1/4 SN7402
-= -=
VCC
C', I C2 I I C3
,/
.
V·
Figure 21. Dual Tone Decoder
X R S67
PRECISION OSCILLATOR
The current-controlled oscillator (CeO) section of the
XR-567 provides two basic output waveforms as shown
in Figure 22. The squarewave is obtained from pin 5,
and the exponential ramp from pin 6. The relative phase
relationships of the waveforms are also provided in the
figure. In addition to being used as a general purpose
oscillator or clock generator, the ceo can also be used
for any of the following special purpose oscillator applications:
··/co
1
'6'-,1
1
1. High-Current Oscillator
The oscillator output of the XR-567 can be amplified
using the output amplifier and high-current logic output available at pin 8. In this manner, the circuit can
switch 100 mA load currents without sacrificing oscillator stability. A recommended circuit connection
for this application is shown in Figure 23. The oscillator frequency can be modulated over ±6% in frequency by applying a control voltage to pin 2.
Figure 23. Precision Oscillator to Switch 100 rnA Loads
3. Oscillator with Frequency Doubled Output
The ceo frequency can be doubled by applying a
portion of the squarewave output at pin 5 back to the
input at pin 3, as shown in Figure 25. In this manner,
the quadrature detector functions as a frequency
doubler and produces an output of 2 fo at pin 8.
2. Oscillator with Quadrature Outputs
Using the circuit connection of Figure 24 the XR-567
can function as a precision oscillator with two separate squarewave outputs (at pins 5 and 8, respectively) that are at nearly quadrature phase with each
FSK DECODING
XR-567 can be used as a low speed FSK demodulator.
In this application the center frequency is set to one of
1-51
XR·567
V'
the input frequencies, and the bandwidth is adjusted to
leave the second frequency outside the detection band.
When the input signal is frequency keyed between the
in-band signal and the out-band signal, the logic state of
the output at pin 8 is reversed. Figure 26 shows the
FSK input (f2 = 3 11) and the demodulated output signals, with 10 = 12 = 1 kHz. The circuit can handle data
rates up to 10/10 baud.
XR 567
I
8
JUUlI2f o
r;
V'
V'
4
3 XR 567 8
'(
6
!>
CONNECT PIN J
TO/ElVTO
INVERT OUTPuT
Figure 25. Oscillator with Oouble Frequency Output
rC;1
Figure 24. Oscillator with Quadrature Output
Figure 26. Input and Output Waveforms lor FSK Decoding
Top: Input FSK Signal (I2 = 311)
Bottom: Demodulated Output
1-52
XR·567A
Precasion Tone Decoder
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-567A provides all the necessary circuitry for
constructing a variety of tone detector and frequency
decoder applications_ Phase-locked loop circuit techniques are used to provide operation from 0_01 Hz to
500 kHz. The circuit also features an input preamp, a
high-current logic output, and programmable output delay.
OUTPUT
FILTER
LOW-PASS
LOOP FILTER
GROUND
-,
INPUT
The XR-567A, available in an 8-Pin DIL package, is designed to offer improved frequency accuracy and drift
characteristics over the standard industry 567. These
changes offer improved overall circuit performance,
while reducing initial circuit adjustments.
TIMING
RESISTOR
AND
CAPACITOR
+Vcc
-.J
ORDERING INFORMATION
FEATURES
Programmable Detection Bandwidth
0% to 14%
Logic Output
100 mA
Wide Center
Frequency Range
0.01 Hz to 500 kHz
High Rejection
of Out-of-Band Signals and Noise
Direct Replacement for standard 567
Inherent immunity to
out-of-band signals & noise
Part Number
Package
Operating Temperature
XR-567AM
XR-567ACN
XR-567ACP
Ceramic
Ceramic
Plastic
-55°C to + 125°C
O°C to + 70°C
O°C to +70°C
SYSTEM DESCRIPTION
The XR-567A is an improved version of the popular 567
tone decoder. Center frequency accuracy is guaranteed by design modifications and testing to 5 %, and is
typically better than 2%. Temperature drift of the center frequency is also improved. Thus, in most applications, no trimming is required.
APPLICATIONS
Tone Detection
Touch-Tone® Decoding
Communications Paging
Ultrasonic Remote Control
Precision Oscillator
Wireless Intercom
Carrier-Tone Transceiver
FSK Demodulation
Dual Time Constant Tone Detector
The XR-567A monolithic tone decoder consists of a
phase detector, low pass filter, and current controlled
oscillator which comprise the basic phase-locked loop,
plus an additional low pass filter and quadrature detector enabling detection of in-band signals. The device
has a normally high open collector output capable of
sinking 100 mA.
The input signal is applied to Pin 3 (20 kO nominal input
resistance). Free running frequency is controlled by an
RC network at Pins 5 and 6 and can typically reach 500
kHz. A capacitor on Pin 1 serves as the output filter and
eliminates out-of-band triggering. PLL filtering is accomplished with a capacitor on Pin 2; bandwidth and
skew are also dependant upon the circuitry here. Bandwidth is adjustable from 0 % to 14 % of the center frequency. Pin 4 is +VCC (4.75 to 9V nominal, 10V maximum); Pin 7 is ground; and Pin 8 is open collector output, pulling low when an in band Signal triggers the
device.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Ceramic Package
Plastic Package
Derate above 25°C
Operating Temperature Range
XR-567AM
XR-567 ACN/ACP
Storage Temperature Range
OUTPUT
10 volts
385 mW
300 mW
2.5 mW/oC
- 55°C to + 125°C
O°C to + 70°C
-65°C to +150°C
1-53
XR·567A
ELECTRICAL CHARACTERISTICS
Test Conditions: Vee = + 5V. TA = 25° e, unless otherwise specified.
LIMITS
PARAMETt.
MIN
TYP
MAX
UNITS
9.0
Vdc
8
10
13
15
15
-10
VCC +0.5
mA
mA
mA
mA
V
V
V
CONDITIONS
GENERAL
Supply Voltage Range
Supply Current
Quiescent XR·567AM
Quiescent XR·567AC
Activated XR·567 AM
Activated XR·567AC
Output Voltage
Negative Voltage at Input
Positive Voltage at Input
4.75
6
7
11
12
RL
RL
RL
RL
=
=
=
=
20
20
20
20
kO
kO
kO
kO
CENTER FREQUENCY
Highest Center Frequency
Center Frequency Stability
Temperature TA = 25°C
0< TA < 70°C
-55 < TA < +125°C
Supply Voltage
XR·567AM
XR·567AC
Initial Accuracy
100
500
kHz
35
±60
±120
ppm/DC
ppm/DC
ppm/DC
0.5
0.7
±2.0
1.0
2.0
±5.0
%N
%N
%
10 = 100 kHz
10 = 100 kHz
10 = 100 kHz
14
14
16
18
% 0110
% 0110
10 = 100 kHz
10 = 100 kHz
1
2
2
3
% 0110
% 0110
±0.1
±1
±2
'/oI°C
%N
DETECTION BANDWIDTH
Largest Detection Bandwidth
XR·567AM
XR·567AC
Largest Detection Bandwidth Skew
XR·567AM
XR·567AC
Largest Detection Bandwidth Variation
Temperature
Supply Voltage
12
10
Yin = 300mV rms
Yin = 300 mV rms
INPUT
Input Resistance
Smallest Detectable Input Voltage
Largest No·Output Input Voltage
Greatest Simultaneous Outband
Signal to Inband Signal Ratio
Minimum Input Signal to Wideband
Noise Ratio
10
20
20
15
25
kO
mVrms
mVrms
IL = 100 mA, Ii = 10
IL = 100 mA, Ii =10
+6
dB
-6
dB
Bn = 140 kHz
V
V
IL = 30 mA, Vln = 25 mV rms
IL = 100 mA, Yin = 25 mV rms
OUTPUT
Output Saturation Voltage
Output Leakage Current
Fastest ON/OFF Cycling Rate
Output Rise Time
Output Fall Time
0.2
0.6
0.01
10120
150
30
1-54
0.4
1.0
25
,.A
ns
ns
RL = 500
RL = 500
XR·L567
Micropower Tone Decoder
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-L567 is a micropower phase-locked loop (PLL)
circuit designed for general purpose tone and frequency decoding. In applications requiring very low power
dissipation, the XR-L567 can replace the popular 567type decoder with only minor component value
changes. The XR-L567 offers approximately 111 Oth the
power dissipation of the conventional 567-type tone decoder, without sacrificing its key features such as the
oscillator stability, frequency selectivity, and detection
threshold. Typical quiescent power dissipation is less
than 4 mW at 5 volts. It operates over a wide frequency
band of 0.01 Hz to 60 kHz and contains a logic compatible output which can sink up to 10 milliamps of load
current. The bandwidth, center frequency, and output
delay are independently determined by the selection of
four external components.
OUTPUT
FILTER
LOW PASS
LOOP fiLTER
ORDERING INFORMATION
FEATURES
Very Low Power Dissipation (= 4 mW at 5V).
Bandwidth Adjustable from 0 to 14%.
Logic Compatible Output with 10 rnA Current Sinking
Capability.
Highly Stable Center Frequency.
Center Frequency Adjustable from 0.01 Hz to 60 kHz.
Inherent Immunity to False Signals.
High Rejection of Out-of-Band Signals and Noise.
Frequency Range Adjustable Over 20:1 Range by External Resistor.
Part Number
Package
Operating Temperature
XR-L567CN
XR-L567CP
Ceramic
Plastic
O°C to + 70°C
O°C to + 70°C
SYSTEM DESCRIPTION
The XR-L567 monolithic circuit consists of a phase detector, low pass filter, and current controlled oscillator
which comprise the basic phase-locked loop, plus an
additional low pass filter and quadrature detector enabling detection of in-band signals. The device has a normally high open collector output.
APPLICATIONS
ABSOLUTE MAXIMUM RATINGS
The input Signal is applied to Pin 3 (100 kO nominal input reSistance). Free running frequency is controlled by
an RC network at Pins 5 and 6. A capacitor on Pin 1
serves as the output filter and eliminates out-of-band
triggering. PLL filtering is accomplished with a capacitor on Pin 2; band-width and skew are also dependant
upon the circuitry here. Pin 4 is + VCC (4.75 to 8V nominal, 10V maximum); Pin 7 is ground; and Pin 8 is the
open collector output, pulling low when an in-band signal triggers the device.
Power Supply
10 volts
Power Dissipation (package limitation)
Ceramic Package
385 mW
Plastic Package
300 mW
2.5 mW/oC
Derate Above +25°C
Operating Temperature
O°C to + 70°C
Storage Temperature
- 65°C to + 150°C
The XR-L567 is pin-for-pin compatible with the standard
XR-567-type decoder. Internal resistors have been
scaled up by a factor of ten, thereby redUCing power
diSSipation and allowing use of smaller capacitors for
the same applications compared to the standard part.
This scaling also lowers maximum device center frequency and load current sinking capabilities.
Battery-Operated Tone Detection
TOUCh-Tone" Decoding
Sequential Tone Decoding
Communications Paging
Ultrasonic Remote-Control
Telemetry Decoding
1-55
XR·L567
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = + 5V. TA = 25 DC, unless otherwise specified. Test Circuit of Figure 1.
PARAMETERS
MIN
LIMITS
TYP
MAX
UNITS
CONDITIONS
General
Supply Voltage Range
Supply Current
Quiescent
Activated
4.75
0.6
0.8
8.0
V
1.0
1.4
mA
mA
= 20 kll
= 20 kll
RL
RL
Center Frequency
Highest Center Frequency
Center Frequency Drift
Temperature TA = 25 DC
0< TA < 70 DC
Supply Voltage
10
60
kHz
-35
-150
0.5
ppm/DC
ppm/DC
3.0
%N
14
2
18
3
% of fo
% offo
See Figures 10 and 11
See Figu res 10 and 11
fo = 10kHz, VCC = 5.25 ± 0.5V
Detection Bandwidth
Largest Detection Bandwidth
Largest Detection Bandwidth Skew
Largest Detection Bandwidth Variation
Temperature
Supply Voltage
10
%/DC
±0.1
±2
fo = 10 kHz
See Figure 13 for Definition
%N
Vin
Vin
kll
mVrms
mVrms
IL
IL
= 300 mV rms
= 300 mV rms
Inputs
Input Resistance
Smallest Detectable Input Voltage
Largest No·Output Input Voltage
Greatest Simultaneous Outband
Signal to Inband Signal Ratio
Minimum Input Signal to Wideband
Noise Ratio
10
100
20
15
25
+6
dB
-6
dB
Bn
V
V
IL
IL
=
=
=
10 mA, fi
10 mA, fi
=
=
fo
fo
140 kHz
Outputs
Output Saturation Voltage
Output Leakage Current
Fastest On/Off Cycling Rate
Output Rise Time
Output Fall Time
0.2
0.3
0.01
fo/20
150
30
EQUIVALENT SCHEMATIC DIAGRAM
0.4
0.6
25
=
=
2 mA, Vin = 25 mV rms
10 mA, Vin = 25 mV rms
p.A
ns
ns
RL
RL
=
=
1 kll
1 kll
PRINCIPLES OF OPERATION
The XR-L567 is a frequency selective tone decoder system based on the phase-locked loop (PLL) principle.
The system is comprised of a phase-locked loop, a
quadrature am detector, a voltage comparator, and an
output logic driver.
When an input tone is present within the pass-band of
the circuit, the PLL synchronizes or "locks" on the input signal. The quadrature detector serves as a lock indicator: when the PLL is locked on an input signal, the
dc voltage at the output of the detector is shifted. This
dc level shift is then converted to an output logic pulse
by the amplifier and logic driver. The logic output at Pin
8 is an "open-collector" NPN transistor stage capable
of switching 10 mA current loads.
1-56
XR·L567
The logic output at Pin 8 is normally in a "high" state,
until a tone that is within the capture range of the decoder is present at the input. When the decoder is
locked on an input signal, the logic output at Pin 8 goes
to a "low" state.
Vee
RL
Figure 3 shows the typical output response of the circuit for a tone-burst applied to the input, within the detection band.
OUTPUT
The center frequency of the detector is set by the freerunning frequency of the current-controlled oscillator in
the PLL. This free-running frequency, fo, is determined
by the selection of R1 and C1 connected to Pins 5 and
6, as shown in Figure 2. The detection bandwidth is determined by the size of the PLL filter capacitor, C2 (see
Figure 10); and the output response speed is controlled
by the output filter capacitor, C3.
Figure 2. XR-L567 Generalized Connection Diagram
DEFINITION OF DEVICE PARAMETERS
Largest Detection Bandwidth
Center Frequency to
The largest detection bandwidth is the largest frequency range within which an input signal above the threshold voltage will cause a logical zero stage at the output.
The maximum detection bandwidth corresponds to the
lock range of the PLL.
fo is the free-running frequency of the currentcontrolled oscillator with no input signal. It is determined by resistor R1 between Pins 5 and 6, and capacitor C1 from Pin 6 to ground. fo can be approximated by
Detection Band Skew
fo " _1_Hz
R1 C1
The detection band skew is a measure of how accurately the largest detection band is centered about the
center frequency, fo . This parameter is graphically iIIus·
trated in Figure 4. In the figure, fmin and f max correspond to the lower and the upper ends of the largest detection band, and fl corresponds to the apparent center of the detection band, and is defined as the
arithmetic average of fmin and f max and fo is the freerunning frequency of the XR-L567 oscillator section.
The bandwidth skew, Afx , is the difference between
these frequencies. Normalized to fo, this bandwidth
skew can be expressed as:
where Rl is in ohms and C1 is in farads.
Detection Bandwidth (BW)
The largest detection bandwidth is the frequency range
centered about fo, within which an input signal larger
than the threshold voltage (typically 20 mV rms) will
cause a logic zero state at the output. The detection
bandwidth corresponds to the capture range of the PLL
and is determined by the low-pass loop filter at Pin 2.
Typical dependence of detection bandwidth on the filter capacitance and the input signal amplitude is shown
in Figures 10 and 11, or may be calculated by the approximation
Vi (RMS)
BW (%) .. 338
Fo(Hz)·C2 (ILF)
Bandwidth Skew
fo
••
- 2fo)
2fo
INPUT
Vee
~.F
= Afx = (fmax + fmin
"V
:ZOkn
OUTPUT
OUTPUT
=
'AdJUI"orlo 10kHz
'1 .. 'OkHz, +SY
Response to 100 mV rms tone burst.
RL = 1K ohms
c,
~ 0.0022.0'
Figure 3. Typical Output Response to 100 mV Input
Tone-Burst
Figure 1. XR-L567 Test Circuit
1-57
XR·L567
stant of the filter can be expressed as T3 = R3C3,
where R3 (47 kO) is the internal impedance at Pin 1.
If necessary, the detection band skew can be reduced
to zero by an optional centering adjustment. (See Optional Controls.)
I-
OUTPUT
LOGIC LEVEL
LARGEST DETECTION
BAND
L~
-I ~
'min
II
'0 "
If the value of C3 becomes too large, the turn-on or
turn-off time of the output stage will be delayed until the
voltage change across C3 reaches the threshold voltage. In certain applications, the delay may be desirable
as a means of suppressing spurious outputs. Conversely, if the value of C3 is too small, the beat rate at
the output of the quadrature detector may cause a
false logic level change at the output (Pin 8).
-I
r=;SINO
FREQUENCV
1m••
•
The average voltage (during lock) at Pin 1 is a function
of the in-band input amplitude .in accordance with the
given transfer characteristic.
10 .. PLL ',..runnlng 1'ltCIuency
1m•• + 'min
I, "* Cenl... lreq. 01 detection blind .. - _ . _
Figure 4. Definition of Bandwidth Skew
Logic Output (Pin 8)
OESCRIPTION OF CIRCUIT CONTROLS
Terminal 8 provides a binary logiC output when an input
signal is present within the pass-band of the decoder.
The logic output is an uncommitted, open-collector
power transistor capable of switching high current
loads. The current level at the output is determined by
an external load reSistor, RL, connected from Pin 8 to
the positive supply.
Input (Pin 3)
The input signal is applied to Pin 3 through a coupling
capacitor. This terminal is internally biased at a dc level
2 volts above ground, and has an input impedance level
of approximately 100 kO.
Timing Resistor R1 and Capacitor C1 (Pins 5 and 6)
When an in-band signal is present the output transistor
at Pin 8 saturates with a collector voltage of less than
0.6V at full rated output current of 10 mAo If large output voltage swings are needed, RL can be connected to
a supply voltage, V +, higher than the Vee supply. For
safe operation, V + ::s 15 volts.
The center frequency of the decoder is set by resistor
R1 between Pins 5 and 6, and capacitor C1 from Pin 6
to ground, as shown in Figure 2.
Pin 5 is the oscillator squarewave output which has a
magnitude of approximately VCC - 1.4V and an average dc level of VCcJ2. A 5 kO load may be driven from
this point. The voltage at Pin 6 is an exponential triangle
waveform with a peak-to-peak amplitude of .. (Vee 1.3}/3.5 volts and an average dc level of VCcJ2. Only
high impedance loads should be connected to Pin 6 to
avoid disturbing the temperature stability or duty cycle
of the oscillator.
OPERATING INSTRUCTIONS
Selection of External Components
A typical connection diagram for the XR-L567 is shown
in Figure 2. For most applications, the following procedure will be sufficient for determination of the external
components R1, C1, C2, and C3·
1. R1 and C1 should be selected for the desired center
frequency by the expression fo .. lIR1C1. For optimum temperature stability, R1 should be selected
such that 20 kO ::s R1 ::s 200 kO, and the R1C1 product should have sufficient stability over the projected operating temperature range.
Loop Fllter-C2 (Pin 2)
Capacitor C2 connected from Pin 2 to ground serves as
a single pole, low-pass filter for the PLL portion of the
XR-L567. The filter time constant is given by T2 =
R2C2, where R2 (100 kO) is the impedance at Pin 2.
2. Low-pass capacitor, C2, can be determined from the
Bandwidth versus Input Signal Amplitude graph of
Figure 10. One approach is to select an area of operation from the graph, and then adjust the Input level and value of C2 accordingly. Or, if the input amplitude variation is known, the required fo C2 product
can be found to give the desired bandwidth. Constant bandwidth operation requires Vi > 200 mV
rms. Then, as noted on the graph, bandwidth will be
controlled solely by the f oC2 product.
The selection of C2 is determined by the detection
bandwidth requirements, as shown in Figure 10. For
additional information see section on "Definition of Device Parameters."
The voltage at Pin 2, the phase detector output, is a linear function of frequency over the range of 0.95 fo to
1.05 fo, with a slope of approximately 20 mV/% frequency deviation.
Output Fllter-C3 (Pin 1)
3. Capacitor C3 sets the band edge of the low-pass filter which attenuates frequencies outside of the detection band and thereby eliminates spurious outputs. If C3 is too small, frequencies adjacent to the
Capacitor C3 connected from Pin 1 to ground forms a
simple low-pass post detection filter to eliminate spurious outputs due to out-of-band signals. The time con-
1-58
XR·L567
der this condition, the lock-up transient is in a worst
case situation, and the minimum theoretical lock-up
time will not be achievable.
detection band may switch the output stage off and
on at the beat frequency, or the output may pulse off
and on during the turn-on transient. A typical minimum value for C3 is 2 C2.
The following expressions yield the values of C2 and
C3, in microfarads, which allow the maximum operating
speeds for various center frequencies where fo is Hz.
Conversely, if C3 is too large, turn-on and turn-off of
the output stage will be delayed until the voltage
across C3 passes the threshold value.
C2 = ~, C3 = 26 /LF
fo
fo
Precautions
1. The XR-L567 will lock on signals near (2n + 1) fo
and produce an output for signals near (4n + 1) fo ,
for n = 0,1 ,2-etc. Signals at 5 fo and 9 fo can
cause an unwanted output and should, therefore, be
attenuated before reaching the input of the circuit.
The minimum rate that digital information may be detected without losing Information due to turn-on transient or output chatter is about 10 cycleslbit, which corresponds to an information transfer rate of fo/10 baud.
In situations where minimum turn-off is of less importance than fast turn-on, the optional sensitivity adjustment circuit of Figure 5 can be used to bring the quiescent C3 voltage closer to the threshold voltage. Sensitivity to beat frequencies, noise, and extraneous
signals, however, will be increased.
2. Operating the XR-L567 in a reduced bandwidth
mode of operation at input levels less than 200 mV
rms results in maximum immunity to noise and outband signals. Decreased loop damping, however,
causes the worst-case lock-up time to increase, as
shown by the graph of Figure 13.
+V
~JR
3. Bandwidth variations due to changes in the in-band
signal amplitude can be eliminated by operating the
XR-L567 in the high input level mode, above 200 mV.
The input stage is then limiting, however, so that outband signals or high noise levels can cause an apparent bandwidth reduction as the in-band signal is
suppressed. In addition, the limited input stage will
create in-band components from subharmonic signals so that the circuit becomes sensitive to signals
at fo/3, fo/5 etc.
Dir
DECREASE
SENSITIVITY
C3
_
+V
DECREASE
SENSITIVITY
XR-L567
t-_IIV'_< RS
15K
4. Care should be exercised in lead routing and lead
lengths should be kept as short as possible. Power
supply leads should be properly bypassed close to
the integrated circuit and grounding paths should be
carefully determined to avoid ground loops and undesirable voltage variations. In addition, circuits requiring heavy load currents should be provided by a
separate power supply, or filter capacitors increased
to minimize supply voltage variations.
t
•
INCREASE
SENSonVITY
SILICON
DIODES FOR
} TEMPERATURE
COMPENSATION
(OPTIONAL)
Figura 5. Adjustable Sensitivity Connections
OPTIONAL CONTROLS
Chatter
Programming
When the value of C3 is small, the lock transient and ac
components at the lock detector output may cause the
output stage to move through its threshold more than
once, resulting in output chatter.
Varying the value of resistor Rl and/or capacitor Cl will
change the center frequency. The value of R1 can be
changed either mechanically or by solid state switches.
Additional Cl capacitors can be added by grounding
them through saturated npn trallsistors.
Although some loads, such as lamps and relays will not
respond to chatter, logic may interpret chatter as a series of output signals. Chatter can be eliminated by
feeding a portion of the output back to the input (Pin 1)
or, by increasing the size of capacitor C3. Generally, the
feedback method is preferred since keeping C3 small
will enable faster operation. Three alternate schemes
for chatter prevention are shown in Figure 6. Generally,
it is only necessary to assure that the feedback time
constant does not get so large that it prevents operation at the highest anticipated speed.
Speed of Response
The minimum lock-up time is inversely related to the
loop frequency. As the natural loop frequency is lowered, the turn-on transients becomes greater. Thus
maximum operating speed is obtained when the value
of capacitor C2 is minimum. At the instant an input signal is applied, its phase may drive the oscillator away
from the incoming frequency rather than toward it. Un-
1-59
XR·L567
+y
+Y
+y
15
+y
.
..,
g
0
~.
~
10
iQ
..Iii
Z
C
w
RA
"...
2K 10 101(
0:
C
'OPTIONAL - PERMITS
LOWER VALUE OF C,
o
10 Hz
Figure 6. Methods of Reducing Chatter
,
~
t,
...
104
u
&
~~
g
IL
r::::)R
,
~
t
10'
I
10 2
+y
o
8
........
10
--
12
C,
C2
14
16
BANDWIDTH - % OF '0
LOWERS·O
;
Figure 10. Detection Bandwidth as a Function
of C2 and C3
SOK
RAISES '0
R,
RAISES 10
~ ~ ........ .......
~
~
C2
":"'
R1
100 kHz
105
IL
+Y
I-<,...,IVV--: ~:
10 kHz
Figure 9. Largest Detection Bandwidth Versus
Operating Frequency
The circuits shown in Figure 7 can be used to change
the position of the detection band (capture range) with·
in the largest detection band (lock range). By moving
the detection band to either edge of the lock range, in·
put signal variations will expand the detection band in
one direction only. Since R3 also has a slight effect on
the duty cycle, this approach may be useful to obtain a
precise duty cycle when the circuit is used as an oscillator.
LOWERS '0
1 kHz
CENTER FREQUENCY
Skew Adjustment
l::fir
100 Hz
1K
SILICON
}
Figure 7.
DIODES FOA
TEMPERATURE
COMPENSATION
(OPTN)NAL)
Detection Band Skew Adjustment
'00
CHARACTERISTIC CURVES
2.5
r----.-...,.-..,--..,---r--,
OJ
:r;
250
~
6200 1600 730 410 260 160 130~
0:
>
c
E 200
2.0
I
,
E
t-
zw
W
""~
1.5
.......
> 100
..
:>
u
:>
OJ
.so
Q
0:
0:
t-
OPTIONAL
:>
1.0
!l:
0.5
50
SENSITIVITY
~'-:I~~~F"-t
-:.!!!L--+-rT
10
BANDWIDTH -
0..
12
14
:~~~~;:~NT
16
OF '0
10
SUPPLY VOLTAG~ - VOLTS
Figure 11. Bandwidth Versus Inpllt Signal Amplitude
(C21n ,..F)
Figure B. Supply Current Versus Supply Voltage
1·60
XR·L567
'5
'000
'4
'2.5
u.
0
...,
:z:
l-
'0
.
z
500
'0
300
7.5
:-
2
2D
BANDWIDTH AT 25'C
o
-75
-so
-25
'0
0 +25 +50 +75 +100 +125
TEMPERATURE,
/~~~:~~-
2345
'0
(MINIMUM C2)
20304050'00
Figure 13. Greatest Number 01 Cycles Belore Output
'00
'.0
u
0.8
~
""" K
1
BANDWIDTH
LIMITED BY_
BANDWIDTH (% OF 'D)
0.9
>
,
·c
Figure 12. Bandwidth Variation With Temperature
l,
u
>
..,u
BANDWIDTH LIMITED
BYC2
['.
50
40
3D
4
2.5
>=
"
'00
6
5.0
III
-'
0
'-
2DO
8
e
ie
'2
400
S
~...
I
II
0.7
0.6
0.5
t:
"\
c:i -200
I--'
0.4
-'00
~
IE
w -300
0.3
~
0.2
~ -400
0.'
o
0.1
0.20.30.40.5 '.0
2 3 4 5
-500
-25
'0
,
1\
w
25
50
75
TEMPERATURE. C
CENTER FREQUENCY - kHz
Figure 14. Power Supply Dependence 01 Center Frequency
Figure 15. Typical Center Frequency Drill With Temperature
(V+ = 5V, R1 = 80 kll, 10 = 1 kHz)
~
:>
lil
......
IE
1-0
~
o
-1
w
"
-2
~
-3
~_..o
-4
~
'"
i
~'o='kHZ~
ili
~
t"'--
t--
-25
Y+
5Y
I
to = 10
R~
".Hz
~ C\.
1\
I
25
50
75
TEMPERATURE. 'C
Figure 16. Typical Frequency Drill as a Function 01
Temperature
1-61
XR·2567
Dual Monolithic Tone Decoder
FUNCTIONAL BLOCK OIAGRAM
GENERAL DESCRIPTION
The XR-2567 is a dual monolithic tone decoder of the
567-typethat is ideally suited for tone or frequency de·
coding in multiple-tone communication systems. Each
decoder of the XR-2567 can be used independently or
both sections can be interconnected for dual operation. The matching and temperature tracking characteristics between decoders on this monolithic chip are
superior to those available from two separate tone decoder packages.
The XR-2567 operates over a frequency range of 0.01
Hz to 500 kHz. Supply voltages can vary from 4.5V to
12V, with internal voltage regulation provided for supplies between 7V and 12V. Each decoder consists of a
phase-locked loop (PLL), a quadrature AM detector, a
voltage comparator, and a logic compatible output that
can sink more than 100 mA of load current
Operating Temperature
XR·2567M
XR-2567C
Storage Temperature
The center frequency of each decoder is set by an ex·
ternal resistor and capacitor which determine the freerunning frequency of each PLL When an input tone is
present within the passband of the circuit, the PLL
"locks" on the input signal. The logic output, which is
normally "high", then switches to a "low" state during
this "lock" condition.
ORDERING INFORMATION
FEATURES
Replaces two 567-type decoders
Excellent temperature tracking between decoders
Bandwidth adjustable from 0 to 14 %
Logic compatible outputs with 100 mA sink capability
Center frequency matching (1 % typ.)
Center frequency adjustable from 0.01 Hz to 500 kHz
Inherent immunity to false triggering
Frequency range adjustable over 20:1 range by
external resistor.
Part Number
Package
Temperature Range
XR-2567M
XR-2567CN
XR-2567CP
Ceramic
Ceramic
Plastic
- 55 DC to + 125 DC
ODC to + 70 DC
ODC to + 70 DC
SYSTEM DESCRIPTION
The XR-2567 dual monolithic tone decoder consists of
two independant 567-type circuits and an on board voltage regulator. Each decoder has a phase detector, low
pass filter, and current controlled oscillator which comprise the basic phase locked loop, plus an additional
low pass filter and quadrature detector enabling detection of in-band signals. Both devices have normally high
open collector outputs capable of sinking 100 mA.
APPLICATIONS
Touch-Tonelli> Decoding
Sequential Tone Decoding
Dual-Tone Decoding/
Encoding
Communications Paging
Ultrasonic RemoteControl and Monitoring
-55 DC to +125 DC
ODC to· + 70 DC
- 65 D C to + 150 D C
Full-Duplex Carrier-Tone
Transceiver
Wireless Intercom
Dual Precision
Oscillator
FSK Generation and
Detection
The input signal is applied to Pin 14 (device A) or Pin 11
(device B), both with 20 kO nominal input resistance.
Free running frequency is controlled by an RC network
at Pins 1 and 16 (device A) or Pins 8 and 9 (device B). A
capaCitor on Pin 2 (A), or Pin 7 (B) serves as the output
filter and eliminates out-of-band triggering. PLL filtering
is accomplished with a capaCitor on Pin 15 (A), or Pin
10 (B); bandwidth and skew are also dependant upon
the circuitry here. Bandwidth is adjustable from 0% to
14% of the center frequency. Pin 13 is + VCC (4.75 to
12V nominal, 14V maximum); Pin 7 is ground; and Pin 3
(A) or Pin 6 (B) is the open collector output, pulling low
when an in-band signal triggers the device.
ABSOLUTE MAXIMUM RATINGS
Power Supply
With Internal Regulator
14V
Without Regulator (Pins 12 and 13 shorted)
10V
Power Dissipation
Ceramic Package
750 mW
Derate Above + 25 DC
6 mW/DC
Plastic Package
625 mW/DC
5.5 mW/DC
Derate Above + 25 DC
Voltage supplies below 7V necessitate bypassing the
internal regulator. This is accomplished by shorting Pin
12 to VCC; for supplies over 7V, a bypass capacitor of
at least l,..F should AC ground Pin 12.
1-62
XR·2567
ELECTRICAL CHARACTERISTICS
Test Conditions: Vee = + 5V, TA = 25° e, unless otherwise specified.Test circuit of Figure 2, 81 closed unless
otherwise specified.
LIMITS
PARAMETERS
MIN
TYP
MAX
UNITS
7
12
Vdc
Vdc
16
20
26
30
15
-10
VCC+0.5
mA
mA
mA
mA
V
V
V
CONDITIONS
GENERAL
Supply Voltage Range
Without Regulator
With Internal Regulator
Supply Current (both decoders)
Quiescent XR·2567M
XR-2567C
Activated XR·2567M
XR·2567C
Output Voltage
Negative Voltage at Input
Positive Voltage at Input
4.75
6.5
12
14
22
24
See Figure 5, SI closed.
See Figure 5, SI open.
See Figure 7, 8
RL = 20 kO
RL = 20 kO
RL = 20 kO
RL = 20 kO
CENTER FREQUENCY (each decoder section)
Highest Center Frequency
Center Frequency Stability
Temperature TA = 25·C
O· -----"""'-Iq ~f---4-+---O
Cc COUPLING CAPACITOR
Ca BYPASS CAPACITOR
f" foB
NVV
5, OPEN FOR 7V TO 12V
OPERATION CL.OSED
FOR 4.5V TO 7V OP.ERA-TION
Figure 4. Circuit Connection Diagram
For decoder section A, the oscillator output can be obtained at either Pin 1 or 16. Pin 16 is the oscillator
squarewave output which has a magnitude of approximately VCC ~ 1.4V and an average dc level of VCC/2. A
1 kO load may be driven lrom this point. The voltage at
Vi
foC2
where Vi is the input signal in volts, rms, and C2 is the
capacitance in /LF at Pins 10 or 15.
1-64
XR·2567
TYPICAL CHARACTERISTICS
1000 r--,----,-----,---.-..,
60r--,---,---,---,--..,---..,
1.0
0.9
..
800
a
600
g
z
~
~
Q
400
0.1
~
0.6
1
0.5
>8
0.4
~
"~
2
I
0.8
~
J
V
0.2
I
o
12
4
6
B
10
SUPPLY VOLTAGE, v· IVOLTSI
40
3OHH--i--7I'=
0.3
200
50r--4---4---t---t---r--~
I
I-'
2
I
3 4 5
1Or-~r--4---+---t---+--~
V
10
20 304050
100
5
CENTER FREQUENCY -kHz
Figure 6. Power Supply Dependence
of Center Frequency
Figure 5. Internal Power Dissipation
vs. Supply Voltage. Both Units
Activated, RL = 20 k
0
C~OR~~~~ "'-
"ON"
0
v·
10
11
(VOLTSI
~
,~.LH~,-L~'~K~H'~~IO~K~H-'~'~OO~K~H-'~'~MH'
12
.1"-
~ 10
0
0
0
0
Figure 9. Largest Detection
Bandwidth
,
LIMITED
'" f\
15
I~
,..
!;
I\.
'\
,.5
~
BVC 2
2
3 4 5
10
20 304050
,% 01 'oJ
BANDWIDTH
>
3.0
2.0
~
1.0
~[\
I'-1"'
1"'- i"'--
~.
....
L..k:
10
-4.0
-5.0
-15
14
u
~
-so
~
'-
§
"-
"~
....
I I
I soI
100
1<
A
VCC" , ·0V /
11
12
.
I "/
-2.0
~
r--. c,
10
1.5
-
5.0
2.5
i"'-- r-C2
BANDWIDTH AT 2S"C
0
-75
16
Figure 12. Detection Bandwidth as a
Function of C2 and C3
Vee· 5.7SV
-3.0
~
U
~ -1.0
200 mV rms. Then, as noted in Figure 10,
bandwidth will be controlled solely by the foC2 product.
(For additional information, see Optional Controls Section, "Speed of Response" and "Bandwidth Reduction".)
When an in-band signal is present, the output transistor
at Pins 3 or 6 saturates with a collector voltage less
than 1 volt (typically 0.6V) at full rated current of 100
mA. If large output voltage swings are needed, RL can
be connected to a supply voltage, V + higher than the
Vee supply. For safe operation, V + :s 15 volts.
REGULATOR BY-PASS (Pin 12)
This pin corresponds to the output of the voltage regulator section. For circuit operation with a supply voltage
greater than 7V, Pin 12 should be ac grounded with a
bypass capacitor ;:: 1 /LF. For circuit operation over a
supply voltage range of 4.5 to 7V, the voltage regulator
section is not required; Pin 12 should be shorted to
VCC·
GROUND TERMINALS (Pins 4 and 5)
Pins 10 and 15 correspond to the PLL phase detector
outputs of sections A and B, respectively. The voltage
level at these pins is a linear function of frequency over
the range of 0.95 to 1.05 fo, with a slope of approximately 20 mV/% frequency deviation.
To eliminate parasitic interaction, each decoder section
has a separate ground terminal. The internal regulator shares a common ground with decoder section A
(Pin 4).
OUTPUT FILTER, C3 (Pins 2 and 7)
Independent ground terminals also allow additional
flexibility for split supply operation. Pin 4 can be used as
V - , and Pin 5 as ground, as shown in Figure 16. When
the circuit is operated with split supplies, the positive
supply should always be > 6V, and the dc potential
across Pins 13 and 14 should not exceed 15 volts.
Capacitors CSA and CSB connected from Pins 2 and 7
to ground form low-pass post detection filters for sections A and B respectively. The function of the post detection filter is to eliminate spurious outputs caused by
out-of-band signals. The time constant of the filter can
be expressed as T3 = R3C3, where R3 (4.7 k) is the internal impedance at Pins 2 or 7.
v'
The precise value of C3 is not critical for most applications. To eliminate the possibility of false triggering by
spurious Signals, a minimum value for C3 is 2C2, where
C2 is the loop filter capaCitance for the corresponding
decoder section. If C3 is smaller than 2C2, then frequencies adjacent to the detection band may switch
the output stage "off" and "on" at the beat frequency,
or the output may pulse "off" and "on" during the turnon transient.
"FOR OPERATION WITH v· <' 7V.
SHORT PINS 11 AND 11
v'
RLB
t-l.r---o
v. OR
OUTPUT
B
r
v'
j" GROUND
GROUND
-::-
'CA
r
t - l . r - - - o OU~UT .J
v' OR GROUND
V'
[NOTE. DCVOtTA(iEATrIN4
MUST AlWAYS8[ -.PlN!>\
If the value of C3 becomes too large, the turn-on or
turn-off time of the output stage will be delayed until the
voltage change across C3 reaches the threshold voltage. In certain applications, this delay may be desirable
as a means of suppressing spurious outputs. (For additional information, see Optional Controls Section,
"Speed of Response" and "Chatter".)
Figure 16. Split-Supply Operation Using Independent Ground
Terminals 01 Units A and B. Unit A Operates
Between V+ and V-; Unit B Operates Between
V+ and Ground
1-66
XR·2567
'.
v'
OPTIONAL CONTROLS
SPEED OF RESPONSE
v'
v'
200 TO IK
The minimum lock-up time is inversely related to the
loop frequency. As the natural loop frequency is lowered, the turn-on transient becomes greater. Thus, maximum operating speed is obtained when the value of capacitor C2 is minimum. At the instant an input signal is
applied, its phase may drive the oscillator away from
the incoming frequency rather than toward it. Under
this condition, the lock-up transient is in a worst case
situation, and the minimum theoretical lock-up time will
not be achievable.
'.
200TOIK
'OPTIONAL-PERMITS
LOWER VALUE OF CI
Figure 18. Methods of Reducing Chatter
SKEW ADJUSTMENT
The following expressions yield the values of C2 and
C3, in microfarads, which allow the maximum operating
speeds for various center frequencies. The minimum
rate that digital information may be detected without
losing information due to turn-on transient or output
chatter is about 10 cycles/bit, which corresponds to an
information transfer rate of fo/l 0 baud.
The circuits shown in Figure 19 can be used to change
the pOSition of the detection band (capture range) within the largest detection band (or lock range). By moving
the detection band to either edge of the lock range, input signal variations will expand the detection band in
one direction only. Since R3 also has a slight effect on
the duty cycle, this approach may be useful to obtain a
precise duty cycle when the circuit is used as an oscillator.
C2 = 130, C3 = 260
fa
fa
In situations where minimum turn-off time is of less importance than fast turn-on, the optional sensitivity adjustment circuit of Figure 17 can be used to bring the
quiescent C3 voltage closer to the threshold voltage.
Sensitivity to beat frequencies, noise, and extraneous
signals, however, will be increased.
"
'.
"
OECJl~"S.t
S[IIISIT'V,T'f
H:h-"'
........~;:~
Figure 19. Connections to Reposition Detection Band
t
I"ICIlEA,SE
lie
1.111(
511.SlTIVI1Y
OUTPUT LATCHING
After a signal is received, the output of either decoder
section can be latched "on" by connecting Ii. 20 kD resistor and diode from the "output" terminal to the "output filter" terminal as shown in Figure 20. The output
stage can be unlatched by raising the voltage level at
the output filter terminal.
Figure 17. Optional Connections for Sensitivity Control
CHATTER
v'
When the value of C3 is small, the lock transient and ac
components at the lock detector output may cause the
output stage to move through its threshold more than
once, resulting in output chatter.
''".
Although some loads, such as lamps and relays will not
respond to chatter, "logic" may interpret chatter as a
series of output signals. Chatter can be eliminated by
feeding a portion of the output back to the input or, by
increasing the size of capacitor C3. Generally, the feedback method is preferred since keeping C3 small will
enable faster operation. Three alternate schemes for
chatter prevention are shown in Figure 18. Generally, it
is only necessary to assure that the feedback time constant does not get so large that it prevents operation at
the highest anticipated speed.
-uUNLATCH
C... PAEVENTS LATCH UP
WHEN POWER SUPPLY IS
TUANEDON,
Figure 20. Output Latching
POSITIONING OF DETECTION BANDS
Figure 21 defines the respective band-edge and bandcenter frequencies for sections A and B of the dual tone
decoder.
1-67
XR·2567
Frequencies fL and FH with appropriate subscripts refer to the low and the high band-edge frequencies for
decoder sections A and B, and fo is the center frequency.
I
DeneTION ItANO
OF UNIT A
I
I
OFUNITB
~,
""I'" I'"
'"
'oA
'08
J!I
'"
/'
/.
,,~
...
/'00'
Ih
I
~ ~ ~ :'-:::v
11~
is
/
/
!~ (!...O!t-ii~!) '.C2':~:r.; (~D~l')
NOTE
OEteCTION8AND-,"Ollo
__
ADJUSTCONTAOlFOASVtlltllETRVOF
DETECTIOr.lBANOEDGESABOIJTl o
Figure 22. Bandwidth Reduction
FREOUENCY
(a) Indapendent Detection 01 Two Separate Tones
APPLICATIONS
I
TOTAL DE:EJc;rON BAND
I
DUAL-TDNE DETECTION
11~
6
'GA
foB
In most dual-tone detection systems, the decoder out·
put is required to change state only when both input
tones are present simultaneously. This can be implemented by setting the detection bandwidth of each of
the XR-2567 decoder sections to cover one of the input
tones; and then connecting the respective outputs
through a NOR gate, as shown in Figure 23. In this
case, the output of the NOR gate will be "high" only
when both input tones are present simultaneously.
_
FREOUENCY
(b) Addition 01 Detection Bandwidth lor Wide· Band
Detection
TOTAL DETECTION
-j
r
loA
'oB
BAND
~
(c) Subtraction 01 Bandwidths lor Narrow-Band Detection
Figure 21. Positioning of Detection Bands
The two sections can be interconnected to form a sin·
gle tone detector with an overall detection bandwidth
equal to the sum or the difference of the detection
bands for the two individual detector sections. For example, if the individual decoder sections are interconnected as shown in Figure 25, then the total detection
bandwidth would be approximately equal to the sum of
the respective bandwidths as shown in Figure 21(b).
Similarly, if the decoders are interconnected as shown
in Figure 23, then the overall detection band would be
equal to the difference, or the overlap, between the respective bandwidths as shown in Figure 21(c).
'"-_...r...... NOR
10K
v' o-"""".----<~-----:l.....;
1/4SN1402
Figure 23. Connection for Decoding Dual-Tone Encoded Input
Signals
BANDWIDTH REDUCTIDN
Figure 24 shows additional circuit configurations which
can be used for decoding multiple-tone input signals. In
Figure 24(a), the output of Unit A is connected to the
output filter (Pin 7) of Unit B through the diode 01. If no
The bandwidth of each decoder can be reduced by either increasing the loop filter capacitor C2 or reducing
the loop gain. Increasing C2 may be an undesirable solution since this will also reduce the damping of the
loop and thus slow the circuit response time.
input tone is present within the detection-band of Unit
A, then its output (pin 3) is "high", which keeps diode
Figure 22 shows the proper method of reducing the
loop gain for reduced bandwidth. This technique will improve damping and permit faster performance under
narrow band operation. Bandwidth reduction can also
be obtained by subtracting overlapping bandwidths of
the two decoder sections (see Figures 21(c) and 23).
01 conducting and "disables" Unit B by keeping its output (pin 6) "high". If an input tone is present within the
detection-band of Unit A, Pin 3 is low, diode 01 is reverse biased, and decoder B is no longer disabled. If
under these conditions an input signal is· present within
the detection-band of Unit B, then its output at Pin 6
would be "low". Thus, the output at Pin 6 is "low" only
1-68
XR·2567
SEQUENTIAL TDNE DECDDING
when input tones within the detection-band of A and B
are present simultaneously.
The dual-tone decoder circuit of Figure 24(b) makes
use of the split-ground feature of the XR-2567. The output terminal of Unit A is used as a "switch" in series
with the ground terminal (Pin 5) of Unit B. If the input
tone A is not present, Pin 3 is at its high-impedance
state, and the ground terminal of Unit B is opencircuited. When the input tone A is present, Pin 3 goes
to a low-impedance state and Unit B is activated. In this
manner, the output of Unit B will be "low" only when
both tones A and B are present.
Dual-tone decoder circuits can also be used for sequentialtone decoding where one tone must be present
before the other for the circuit to operate. This can be
achieved by making the output filter capacitance, C3,
of one of the sections large with respect to the other.
For example, in the circuits of Figures 24(a) and 24(b), if
C3A is chosen to be much larger than C3B (C3A ~
C3B), then Unit A will remain "on" and activate B for a
finite time duration after tone A is terminated. Thus, the
circuit will be able to detect the two tones only if they
are present sequentially, with tone A preceding tone B.
In the circuit connection of Figure 24(b), Unit B does
not draw any current until it is activated. Therefore, its
power dissipation in a stand-by condition is lower than
other dual-tone decoder configurations. However, due
to finite series resistance between Pin 3 and ground
when Unit B is activated, the output current sink capability is limited to ::; 10 mAo
The circuit of Figure 24(a) can also be modified for sequential tone decoding by addition of a diode, D2, between pins 3 and 6. Once activated by Unit A, Unit B
will stay "on" as long as tone B is present, even though
tone A may terminate. Once tone B disappears, the circuit is reset to its original state and would require tone
A to be present for activation.
HIGH-SPEED NARRDW-BAND TDNE DECODER
The circuit of Figure 23 can be used as a narrow-band.
tone decoder by overlapping the detection bands of
Units A and B (see Figure 21(c)). The output of the NOR
gate will be high only when an input Signal is present
within the overlapping portions of the detection band.
To maintain uniform response within the pass-band, the
input Signal amplitude should be O!!: 80 mV rms. For
minimum response time, PPL filter capacitors C2A and
C2B should be:
RIB
R'A
C2A = C2B ==
~/LF
fo (Hz)
Under this condition, the worst-case output delay is
=10 to 14 cycles of the input tone.
1.0KU
I
L_~~
+--'WI.---.Qv'
The practical matching and tracking tolerances of individual units limit the minimum bandwidth to =4% of fo.
(a)
WIDE-BAND TONE DECODER
Figure 25 is a circuit configuration for increasing the
detection bandwidth of the XR-2567 by combining the
respective bandwidths of individual decoder sections. If
the detection bands of each section are located adjacent to each other as shown in Figure 21(b), and if the
two outputs (pins 3 and 6) are shorted together, then
the resulting bandwidth is the sum of individual bandwidths. In this manner, the total detection bandwidth
can be increased to 24 % of center frequency. To maintain uniform response throughout the pass band, the input signal level should be 0!!:80 mV, rms, and the respective pass-bands of each section should have
"" 3 % overlap at center frequency.
~--'wv---()
v'
TONE TRANSCEIVER
The XR-2567 can be used as a full-duplex tone transceiver by using one section of the unit as a tone detector and the remaining section as a tone generator.
Since both sections operate independently, the circuit
(b)
Figure 24_ Additional Dual-Tone Decoding Circuits
1-69
XR·2567
v'
"
f---o4-l:---I-~:J---.L.() RECEIVER
!OUTI'UT
r
-.-l::J-2.1--r-.,--1-4!..lJ1-_-J:...·:oL
J,nfif
TRANSMITTER
OUTPUT
Figure 25. Wide-Band Tone Detection
Cc • COUPLING CAPACITOR
can transmit and receive simultaneously. A recommended circuit connection for transceiver applications
is shown in Figure 26. In this case, Unit A is utilized as
the receiver, and Unit B is used as the transmitter. The
transmitter section can be keyed "on" and "off" by applying a pulse to pin 8 through a disconnect diode D1.
The oscillator section of Unit B will be keyed "off" when
the keying logic level at pin 8 is at a "low" state.
Figure 26. Tone Transceiver
The output of the transmitter section (Unit B) can also
be frequency modulated over a +6% deviation range
by applying a modulation signal to pin 10.
HIGH CURRENT OSCILLATOR
The oscillator output of each section of XR-2567 can be
amplified using the high current logic driver sections of
the circuit. In this manner, each section of the circuit
can switch 100 mA loads, without sacrificing oscillator
stability. A recommended circuit connection for this application is shown in Figure 27. The oscillator frequency
can be modulated over ± 6 % of fo by applying a control
voltage to pins 15 or 10.
·.FOAV ec r.JV
SHORT PIN 12 TO PIN tl.
Figure 27. Precision Oscillator wHh High Current Output
CapabllHy
1-70
Filters
XR·1 000·1 008
General Purpose Low Pass Filter
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAMS
The XR-1000 is a general purpose 4th order low pass
filter utilizing switched capacitor (SCF) circuit techniques. XR-1000 is available in several options providing Butterworth or Chebyshev filter responses. The
Chebyshev option is also available with passband ripple
specifications of 0.01, 0.1, or 1.0 dB specifications.
XR-1000
elK IN
FILTER IN
4TH
ORDER
LOW
elK R
The SCF techniques used provide a clock tunable cutoff frequency, with either 50:1 or 100:1 clock to cutoff
frequency ratios available. The clock may be externally
generated or an on-board Schmitt trigger is supplied for
providing an internal clock with an external resistor/
capacitor combination.
13 v+
PASS
FILTER
12
l. SH
The XR-1000, utilizing CMOS technology, is available in
either a 14-Pin or 8-Pin DIL package.
AGND
v-
FILTER OUT
NC
NC
RLO
FEATURES
B
FILTER
9
SO/100
8
NC
ESPONSE
lOGIC
Switched Capacitor Circuit Techniques
Single 5 Volt Operation
Low External Parts Count
No Precision Components Necessary
Low Power Operation
50:1/100:1 Clock to Cutoff Frequency Options
8-Pin/14-Pin Package Options
0.1 to 20 kHZ Cutoff Frequency Range
Internal/External Clock Operation
FILTER IN
APPLlCATlDNS
elK A
General Purpose Low Pass Filters
Telecom Filtering
Medical Systems
Audio Applications
Data Acquisition Systems
L. SH
AGND
v-
FILTER OUT
ORDERING INFORMATION
Part Number
XR-1000CP/CN
XR-1001CP/CN
XR-1002CP/CN
XR-1003CP/CN
XR-1004CP/CN
XR-1005CP/CN
XR-100BCP/CN
XR-1007CP/CN
XR-1008CP/CN
Package
Pins
Response/Ripple
fCLKllc
Plastic/Ceramic
Plastic/Ceramic
Plastic/Ceramic
Plastic/Ceramic
Plastic/Ceramic
Plastic/Ceramic
Plastic/Ceramic
Plastic/Ceramic
Plastic/Ceramic
14
8
8
8
8
8
8
8
8
BW-CH/BW/BW/CH/0.01 dB
CH/O.Q1 dB
CH/0.1 dB
CH/0.1 dB
CH/1.0 dB
CH/1.0 dB
50/100
100
50
100
50
100
50
100
50
1-71
Operating Temperature Range
O°C
O°C
O°C
O°C
O°C
O°C
O°C
O°C
O°C
to
to
to
to
to
to
to
to
to
70°C
70°C
70°C
70°C
70°C
70°C
70°C
70°C
70°C
XR·1000·1008
or internal clocking, connect L.SH to V - (or ground,
with single supplies). Forcing l.SH to V + disables the
filter.
ABSOLUTE MAXIMUM RATINGS
Power Supply v+ + IV-I
Power Dissipation
14-Pin
B-Pin
Derate Above 2S·
14-Pin
B-Pin
Storage Temperature Range
14 Volts
Analog Ground (AGND)-The analog, or signal ground
should be directly connected to system power supply
ground for dual supply operation. This pin is internally
biased to (V+ + V-)/2, and should be heavily bypassed with capacitors to power supply ground for single supply operation. In noisy environments, performance may be improved with an additional bypass capacitor to V + .
7S0mW
SOOmW
6 mW/·C
2.S mW/·C
- 6S·C to + 1S0·C
PIN DESCRIPTIONS
Y+, Y- ,-The power supplies are applied to these
pins. The XR-l000 series will operate over a range of
SV to 14V with a single supply, or ± 2.SV to ± 7V for dual supplies.
Filter OUl-The filter output will typically source 3 mA
and sink 0.9 mA. With a SkI] or larger load reSistance,
the output will typically swing to within tV of either supply.
Filter In-The raw signal, biased to mid-supply or capacilively coupled, is applied to this pin.
.
Frequency Ratio Select (50/100)-(XR-l000 only) The
clock to center frequency ratio is determined by this
pin. When tied to V+, the ratio is SO:I, when tied to
V-, 100:1 operation is selected.
Clock Input (CLK IN)-A dual purpose Schmitt trigger, accessed at this pin, aids system flexibility by allowing either an external CMOS level clock or generation of an
internal clock signal (self clocking) with an external resistor and capacitor. See ClK R for further information.
Filter Response Select (RLO and RL1)-(XR-l000 only) The
desired filter response is selected by programming
these pins. logic 1 is V + , logic 0 is V - . Table 1 depicts
the programming necessary to select the various options available from the XR-l000.
Clock Resistor (CLK R)-A TIL level clock may be applied
here. Alternately, a resistor connected between ClK R
and ClK IN and a capacitor from ClK IN to ground, allows self clocking operation with the internal Schmitt
trigger.
Table 1_ XR-1000 Programming
Level Shift (L.SH)-The level shift pin provides clock selection and switching thresholds. The voltage at L.SH
determines the threshold of the clock levei shift stage,
which converts either external TIL, external CMOS, or
the internally generated clock signal to full V+ to Vexcursions. Comparison threshold voltage level is two
volts above the voltage on L.SH. For TIL clocks, L.SH
should be held at power supply ground and dual supplies of ± SV or greater must be employed. For CMOS
1-72
RLO
RL1
50/100
RESPONSE
RIPPLE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Butterworth
Butterworth
Chebyshev
Chebyshev
Chebyshev
Chebyshev
Chebyshev
Chebyshev
X
X
0.01 dB
0.01 dB
0.1 dB
0.1 dB
O.S dB
O.S dB
ICLK/lc
SO:1
100:1
50:1100:1
SO:1
100:1
SO:1
100:1
XR·2103
ADVANCE INFORMATION
FSK Modem Filter
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-2103 is a Monolithic Switched-Capacitor Filter
designed to perform the complete filtering function
necessary for a Bell 103 Compatible Modem. The XR2103 is specifically intended for use with the XR-14412
ModulatoriDemodulator to form a complete stand
alone two-chip modem. In addition to complete high
and low bandpass filters, the XR-2103 contains internal
mode switching, auto-zeroing limiter and dedicated duplexer op amp. An on board carrier detect circuit is also included to complete the overall system. Designed
for crystal-controlled operation, the XR-2103 may operate from a 1.0 MHz or 4.0 MHz crystal or external
clock. A 1 MHz buffered clock output is provided for the
XR-14412. A self-test circuit is included.
The XR-21 03, available in a 20 pin package, utilizes
CMOS technology for low power operation with a supply voltage range from 4.75V to 15V.
FEATURES
Single 5 Volt Operation
4.0 MHz/1 MHz Clock Input-Slaveable
Complete On Board Output Active Filters
Low Supply Current
Internal Answer/Originate Mode Switching
Programmable Input Receive Gain
Carrier Detect Output
Active Duplexer
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-2103CP
XR-2103CN
Plastic
Ceramic
O°C to 70°C
O°C to 70°C
APPLICATIONS
SYSTEM DESCRIPTION
Bell 103 Transmit/Receive Filtering
Complement to XR-14412 or other Modulator/
Demodulators
The XR-2103 internally consists of four main signal
blocks. They are: input and output multiplexers to route
the transmit and receive signals to the proper filter and
output, according to the mode input; high and low band
filters, 6 poles each, to perform precise bandpass filtering; output RC active filters to perform output reconstruction and filtering; carrier detection circuit for system interfacing.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Derate Above 25°C
Operating Temperature
Storage Temperature
Any Input Voltage
(VDD
+
16V
1.0W
5.0 mW/oC
O°C to 70°C
-65°C to 150°C
0.5V) to (VSS - 0.5V)
An input amplifier with programmable gain is provided
for the receive signals. The XR-2103 contains an internal clock oscillator which accepts either a crystal or an
external oscillator of 1 MHz or 4 MHz.
1-73
XR·2103
ELECTRICAL CHARACTERISTICS
Tast CondHlons: VDD
= 5V, VSS = OV, XIN = 4.0 MHz, Xsel = VDD, TJ = 25°C, unless otherwise specified.
SYMBOL
PARAMETERS
MIN
VDD
IDD
Power Supply Voltage Range
Power Supply Current
4.75
CONDITIONS
TYP
MAX
UNIT
8
15
10
35
V
mA
50
mV
dB
pA
RL
=
100k
4.5
Vp-p
RL
=
100k to GND (Pin 2)
20
4.5
dB
Vp-p
mV
R2
=
Line Resistance = 600
%
Vp-p
p.A
Cc
RL
Rl
=
=
=
1 p.f Deviation from 50%
1 meg
Duty Cycle
1k
dBM
dB
msec
msec
Receive Amplifier Gain
VSS
VDD
VDD
=0
= 5V
= 15V
ANALOG SECTION RECEIVE AMPLIFIER
Vas
AoL
IB
SR
-50
Offset Voltage
Open Loop Gain
Input Bias Current
Slew Rate
Output Swing
66
1
2
3
V/p.s
OUPLEXER
Vas
Isolation
Output Swing
Offset Voltage
3
-100
100
n
LIMITER
Output Symmetry Error
Output Swing
Output Current
±15
4
100
±2.0
CARRIER DETECT
Vth
ton
toff
Threshold Voltage
Hysteresis
Turn On Time
Turn Off Time
2
-48
4
;;'100
.;;100
6
Ccd
= 0.1p.F, Yin =
= 14 dB
-48dBM
LOW BAND FilTER
fo
BW
Vfs
Ar
DR
PSRR
GD
Center Frequency
Bandwidth
Full Scale Input
Pass Band Gain
Dynamic Range
Power Supply Rej.
Pass Band Ripple
High Band Rejection
Differential (Group) Delay
Clock Feedthrough
1160
3
1170
500
2.5
4
50
15
1180
5
2
40
200
-60
500
2125
500
2.5
4
50
18
2145
Hz
Hz
Vp-p
dB
dB
dB
dB
dB
f = 2 KHz
POp 1070 Hz-1270 Hz
2025 Hz-2225 Hz
p's
dBV
HIGH BAND FILTER
fo
BW
Vfs
Ar
DR
PSRR
GD
Center Frequency
Bandwidth
Full Scale Input
Pass Band Gain
Dynamic Range
Power Supply Rej.
Pass Band Ripple
Rejection
Differential Delay (Grp.)
Clock Feedthrough
2105
3
5
2
40
200
-60
500
Hz
Hz
Vp-p
dB
dB
dB
dB
dB
p's
dBV
f = 1 kHz
pop 2025 Hz-2225 Hz
1070 Hz-1270 Hz
2025 Hz-2225 Hz
62.5 kHz
TRANSMIT
Vas
DC Offset Voltage
Output Swing
Output Current
DIGITAL CMOS lOGIC lEVELS (VOD
Vih
Vii
loh
101
loh
101
fc
fx
Input Voltage
Input Voltage
Output Current
Output Current
Output Current
Output Current
Clock Frequency
Crystal Frequency
100
2.2
1.2
= 5V,
mV
Vp-p
mA
R2
= Line Resistance = 600n
'1'
'0'
'1'
'0'
'1'
'0'
level
level
Level
level
level
level
VSS = OV)
1.5
2.75
2.25
500
1000
100
200
1.0
1.0
1-74
3.5
4.0
4.0
V
V
p.A
p.A
p.A
p.A
MHz
MHz
ClK OUT
ClK OUT
X OUT
X OUT
.'\
XR·2103 ..
one half supply. The amplifier features open loop'gain
of 66 dB, output swings of 4.5 Vp-p, and a slew rate of
2V/p.s. This pin-out allows flexible signal processing capabilities: for example, an input low pass filter for eliminating aliasing is easily achieved.
OPERATING PRINCIPLES
The XR-2103 contains all the filtering and multiplexing
functions necessary for a Bell 103 type (300 baud) FSK
modem. A complete modem requires only the XR-2103,
the XR-14412, and telephone line interfacing hardware.
A description of the main functional blocks follows.
Auto-Zeroing Limiter: An automatic offset zeroing comparator (limiter) compensates for errors caused by system offset voltages and currents, and converts the received carrier into an accurate 50% duty cycle waveform. The resultant square wave on Pin 16 is at digital
logic levels and can interface directly with the modulator/demodulator circuit.
Bandpass Filtering: Two six pole, 500 Hz bandwidth
switched capacitor filters, designed for Bell 103 standard center frequencies of 1170 Hz (low band) and
2125 Hz (high band), constitute the main portion of the
device. Both filters feature +4 dB passband gain,
50 dB dynamic range, and more than 40 dB opposite
band rejection. Filter response curves are depicted in
Figure 3. On board multiplexing allows using these filters for both transmitting and receiving. Active low pass
filters reconstruct the time sampled output signals,
characteristic of switched capacitor filters, and attenuate the unwanted energy above 15 kHz.
Carrier Detector: An on board carrier detection circuit
simplifies total system interfacting. Carrier detect output (Pin 18) pulls low when a suitable signal is received.
With 14 dB of gain in the receiver preamplifier, the
threshold level is - 48 dBm and has 4 dB of hysteresis.
Turn on/off delay time is externally programmable by a
capaCitor from Pin 19 to ground. A 0.1 p.F unit yields
100 ms; delay is directly proportional to capacitance.
Duplexer: An operational amplifier is employed as an
active two to four wire converter (duplexer). The two
phone wires are "split" into transmit and receive components for proper processing; the transmit output
from Pin 8 is applied to the lines through a resistor and
the received signal is drawn from the line and routed into a preamplifier. Transmit energy appears as a common mode signal, hence does not appear on the duplexer output. The received signal, meanwhile, is amplified by two. Isolation is maximized when the transmit
injection resistor (between Pins 6 and 8) is equal in
magnitude to the phone line impedance (600 Il nominal). Transmit signal levels are typically - 9 dBm. Received signals can vary over a 50 dB dynamic range.
Clocking: Filter frequency accuracy is directly related to
the clock frequency. The device operates within specifications with a 1 MHz clock, provided by either a 1 MHz
or 4 MHz crystal (divided down internally) or by sharing
the 1 MHz clock signal from the XR-14412. The device
will operate at other clock frequencies, but the filter
center frequencies will differ. The crystal and a parallel
10 Mil resistor are attached between Pins 11 and 12.
The crystal should be series resonant with a shunt capacitance less than 9 pF. Pin 13, when high, divides the
input frequency by 4; when low, the internal prescaler
is bypassed. Pin 10 is the clock output for interconnection with other devices.
Received Carrier Amplifier: An operational amplifier, with
its inverting input on Pin 20 and output on Pin 3, serves
as a received carrier amplifier. Duplexer output (Pin 7)
is routed to Pin 20 through a 100 kll or larger resistor.
Gain, typically 5 (14 dB), equals the ratio of the feedback resistor (Pin 3 to Pin 20) to the input resistor (Pin 7
to Pin 20)Jhe non-inverting input is internally biased to
Self Test: An on board self test diagnostic activates an
analog loop-back mode: the transmit carrier is routed
through the proper filter and back through the receive
carrier preamplifier and filters, allowing performance
verification of all systems.
XSEL@r------j
'OUT~2
i
OSC
XIN
II
.,
MODE 41-------------'
ST
•
EQUIVALENT SCHEMATIC DIAGRAM
1-75
XR·2103
100kQ
510kQ
Voo
+5-15v
1---='-----0 CARRIER DETECT OUTPUT
)TX INPUT
o------i
1---='-----0 RX CARRIER OUTPUT
,i '
1 - - - - - - 0 ICRYSTAl SELECT
600Q
SELF TEST
o-~P----i
BUFFERED CLOCK
OUTPUT
o--F--l
10kQ
Figure 1. Basic Applications Circuit
'4
~
0
LOGIC INPUT
1
\
ORIGINATE
MODE
ANSWER
ST
NORMAL OPERATION
SELF TEST MODE
XSEL
1 MHZ
4 MHZ
//
\
\
I
\ I
\1
V
g20 1170 1420
181521252315
FREQUENCY IIld
Figure 2. Control Inputs
Figure 3. Filter Characteristics
1-76
XR·2103
APPLICATIONS
limiter and carrier detect circuit. Carrier detect output
(Pin 18) pulls low after a 100 ms delay, controlled by the
0.1 /-IF capacitor on the CCD pin (Pin 19). The limiter circuit compensates for circuit imperfections (offset voltages, etc.), and outputs a 50% duty cycle waveform to
the demodulator input (Pin 1) of the XR-14412. The demodulated data appears on Pin 7 of the XR-14412.
The Bell 103 compatible modem of Figure 4 consists of
the XR-2103 FSK modem filter and the XR-14412 FSK
modulator/demodulator. Designed for full duplex 300
baud operation, the circuit requires only telephone line
and computer interfacing. The entire system uses a
single 5V supply, and performs both answer and originate functions. Answer/Originate selection is controlled
by the mode input; low inputs select answer, high selects originate.
Transmit data is applied to the modulator input (Pin 11)
of the XR-14412. Depending on mode, originate or answer, the data modulates either the high or low band.
The modulated signal exits Pin 9 and is applied to the
transmit multiplexer input (Pin 5) of the XR-21 03; is filtered, reconstructed, and sent into the duplexer and
the phone line.
The telephone line is connected via an isolation transformer to the duplexer input (Pin 6) of the XR-2103. A
resistor, equal to the line resistance, attaches from Pin
6 to the transmit output (Pin 8) and couples the transmit
signal to the line. The received signal is removed from
the line via the duplexer (also called a "two to four wire
converter" or "hybrid"). Duplexer output is coupled
through the receive carrier preamplifier into the multiplexer, where the proper band pass filter is selected.
Transmit energy is seen as a common mode signal and
does not appear on the duplexer output.
One shared time base is employed: here, the oscillator
of the XR-2103 serves both devices. Buffered output is
routed from Pin 10 of the XR-2103 into Pin 4 of the
XR-14412. With a 1 MHz crystal; the oscillator divide by
four prescaler is bypassed-Pin 13 is held low. With
Pin 13 high, a 4 MHz crystal is used.
If the system is in the originate mode (mode pin pulled
high), the received signal passes through the low band,
filter. Then, the sampled signal is reconstructed by an
on board RC active low pass filter and is fed into the
This circuit requires no adjustments. With suitable telephone line coupling and data system interfacing, this
modem realizes its goals of high performance and reliability at low cost.
100K
51 OK
Tx DATA
MODE
1...-....;;;:---------++0
Figure 4. Bell 103 Compatible Modem
1-77
Ax DATA
XR·2120
PSK Modem Filter
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2120 is a self-contained bandpass filter set designed for realization of Bell 212A compatible 1200 bits/
sec PSK Modems. The XR-2120 utilizes CMOS technology and switched capacitor circuit techniques to
minimize external components to a single crystal or frequency source. Contained in the device are two complete bandpass filters centered around the Bell standard 1200 Hz and 2400 Hz send and receive frequencies. These filters also provide compromise line
equalization. Additional features included are digitally
programmable transmit and receive gains as well as input anti-aliasing and complete output smoothing filters.
Separate VSS pins for transmit, receive, and digital sections are provided to minimize crosstalk.
CLKour
Voo
eLKIN
XOUT
X'N
D1GYss
INPUTGND
MOOE
RECVIN
TRANS IN
~e,
e, --,
RECEIVE rlLTER
TRANS FILTER
GAIN SET
GAIN SET
I..-e,
The XR-2120, available in a 22-Pin package (0.4 inch
wide), is designed to operate from a single 12 volt or
dual 6 volt supplies.
e,
RECV OUT Vss
TRAN OUTVSS
RECVOUT
FEATURES
TRAN OUT
LBGNO
HBGNO
LB ~$
On-board Crystal Oscillator With Buffered Output
Internal Anti-aliasing Filters
Complete On-board Output Active Filters
Digitally Programmable Transmit and Receive Gains
MODE Input Internally Switches Filters
for Answer/Originate
Single or Split Supply Operation
Center Frequencies Movable with Input Clock
High-Impedance Inputs (100 k", min)
low Supply Current
1 % Center Frequency Accuracy
Separate ClK IN and ClK OUT Pins
--I
UBVSS
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-2120CN
XR-2120CP
Ceramic
Plastic
O°C to +70°C
O°C to + 70°C
SYSTEM DESCRIPTION
i
The XR-2120 is comprised of four main signal blocks:
The digitally programmable gain amplifier, an input antialiasing switched capacitor filter, switched capacitor
bandpass filters at 1200 Hz and 2400 Hz, and output
RC active filters. These sections serve to: (1) Amplify
and condition incoming signals, (2) remove noise which
can cause aliasing problems in the bandpass filters, (3)
provide very precise bandpass filtering and phase compensation, and (4) perform output reconstruction and
filtering. To perform these necessary filtering and phase
compensation functioris, a total of 48 poles are used in
the XR-2120.
APPLICATIONS
Bell 212A Transmit/Receive Filtering
Answer Back Signal Filtering
ABSOLUTE MAXIMUM RATINGS
Power Supply
16 V
Power Dissipation
1.0 W
Derate above 25°C
5 mW/oC
Operating Temperature
O°C to 70°C
Storage Temperature
-65°C to 150°C
Any Input Voltage
(VOD + 0.5V) to (VSS "-0.5V)
DC Current Into Any Input
± 1 mA
The programmable gain stages provide 4 selectable
gains for transmit or receive. Separate clock output and
input pins are provided for flexibility.
1-78
XR·2120
ELECTRICAL CHARACTERISTICS
Test Conditions: VDD = 6V, VSS
specified.
SYMBOL
=
-6V, XIN
PARAMETERS
= 4.032 MHz (ClK IN =
MIN
TYP
1.008 MHz), TJ
MAX
UNIT
= 25°C, unless otherwise
CONDITIONS
DIGITAL SECTION
ClKOUT
ClK OUT Drive Capability
50
pF
II
Digital Input Current
1.0
~DC
Vil
Digital Input Voltage
VSS
VSS+2
V
For "0" level
Vdd- 2
Vdd
V
For "0" level
VIH
ANALOG SECTION
fOl
Filter Center
1190
1200
1210
Hz
Low Band
fOH
Frequencies
2380
2400
2420
Hz
High Band
BW
3 dB Bandwidth
Hz
Either Band
RI
Input Impedance
CI
Input CapaCitance
fSI
Anti-Aliasing Filter
Sampling Frequency
fSB
High/low Band
Sampling Frequency
Tran/Recv Output
Drive Capability
Output Clock Feedthrough
960
100K
Ohms
10
pF
504
kHz
126
kHz
Ohms
pF
mVrms
at 126 kHz
10K
50
2
e0100
Output Noise
160
/LV rms
In Passbands (100 Hz BW)
e01000
Output Noise
700
/LV rms
In Passbands (1 kHz BW)
eirange
Dynamic Range of Filters
85
dB
Note 1
VOsw
Output Voltage Swing
8.2
V pp
Note 2
2ndHarm
2nd Harmonic Content
-60
dB
TSW
Mode Switching
10
ms
IDD
Supply Current
18
27
rnA
VSUP
Supply Voltage Range
±6
12
±7.5
15.0
V
V
7.2
±4.75
9.5
Note 1: Dynamic range is defined as: eirange = 20 log (Vosw/eo).
Note 2: VOsw is the maximum output swingoefore output clipping occurs.
1-79
fiN = 1200 Hz
Referenced to Fundamental
Vdd Reference to VSS
XR·2120
gle noise pole RC filter at 30 kHz is usually sufficient for
filtering input noise. The third signal block is the main
bandpass filtering .section at 1200 Hz or 2400 Hz, depending on the mode selected. The last section is the
output smoothing filter; a two-pole RC active filter used
to reconstruct the Signal from its sampled data form.
PRINCIPLES OF OPERATION
Figure 1 shows the typical connection for the XR-2120
in a split supply configuration. In this mode, Pins 4, 10,
and 13, are simply tied to ground. For Single supply operation, Pins 10 and 13 internally bias to half supply and
should be externally bypassed with 2.2 ,..F capacitors.
Pin 4 does not internally dc bias, however, Pin 10 or 13
can provide it with a half supply bias point. In this ~on
nection, a 10 kD resistor should be used between Pin 4,
and Pin 10 or 13, with Pin 4 bypassed with a 2.2,..F capacitor.
The mode input pin is used to direct the transmit and receive signals to the appropriate filter section. Figure 4
shows mode selection logic convention.
The XR-2120 is designed to be operated with a 4.032
MHz crystal between the XIN and >___~---o~R
""" I
+
'4 XR·346
1...£.0,
X_
20K
Figure 5. Carrier Detect Circuit
1-97
/"
XR·14412
GRND.
PHONE UNE
PHONE LINE
'5V
DATA TO)(·MH
DATA RECIEVED
GRND.
COMPONENT
SIDE
SHOWN
(SCAL.E32:1)
Figure 6. Complete FSK Modem Printed Circuit Board Layout
(Circuit Shown in Figure 4)
Table 2. Parts List lor 300 Baud MODEM.
*1 % tolerance; all other resistors are 1/4W, 10%; all capacitors are 10%.
Resistors are in ohms and capacitors are in "F.
*Rl
*R2
*R3
*R4
*R5
*R6
*R7
*R8
*R9
Rl0-Rll
R12
R13
R14
R15
R16
R17-R18
*R19
R20
R21
R22
R23
R24
R25
ANSWER
ORIGINATE
40.2K
499
270K
383K
680
60.4K
160K
24.9K
1.21K
lK
500K
500K Pot
10K
220K
15M
10K
600
220K
22K
2.2M
3.0K
20K
30K
47.5K
191
357K
270K
160
39.4K
160K
20K
360
lK
500K
500K Pot
10K
220K
15M
10K
600
220K
22K
2.2M
3.0K
20K
30K
ANSWER
ORIGINATE
R24
R26
*R27
20K
500
600
20K
500
600
Cl-C6
C7
C8
C9
Cl0
Cl1
.01
.1
22.
.01
4.7
3.3
.01
.1
22
.01
4.7
3.3
0.1
02
IN914
LED
IN914
LED
Tl
Microtran
Tll04
Microtran
Tl104
CRYSTAL
1 MHz ± .1%
lMHz±.l%
Al-A8
XR-346
XR-346
MODEM ICl
XR-14412VP
XR-14412VP
1-98
ADVANCE
INFORMATION
XR·2121/2122
Bell 212A Modulator/Demodulator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAMS
The XR-2121 and XR-2122 are designed to provide the
complete modulator and demodulator functions for the
Bell Standard 212A PSK Modem. These devices, when
used with the XR-2120 PSK Filter, offer a three-chip solution for realizing this 1200/300 bps Modem System.
The XR-2121 Modulator Provides either a 1200 bps PSK
or 0 to 300 bps FSK output. Crystal controlled operation
offers extremely accurate and stable 1200/2400 Hz carriers for the PSK and 1170/2125 Hz carriers for the
FSK. An enableldisable pin is provided for blanking the
modulator output. A transmit clock output, 1200 Hz, is
also provided for synchronization of the terminal and
other facilities. An internal scrambler and an asynchronous to synchronous converter are also provided.
The XR-2122 Demodulator provides the complete demodulation function for either 1200 bps PSK or 0 to 300
bps FSK incoming carriers. Auto speed selection is provided for the answer mode. An internal descrambler
and an synchronous to asynchronous converter are also provided.
Both XR-2121 and XR-2122 utilize CMOS technology for
low power operation. They are designed to operate
from dual 6-volt power supplies, and provide CMOS or
T2L compatible inputs and outputs.
FEATURES
Bell Standard 212A Compatible
XR-2121-Modulator
6-Bit Synthesized Sine Wave Output
EnablelDisable Input
1200 Hz Transmit Clock Output
Internal Scrambler
Asynchronous to Synchronous Converter
Crystal Controlled with Buffered Clock Output
External Clock Input
CMOSITTL Compatible Inputs
XR-2122-Demodulator
Automatic Speed Selection in Answer Mode
36 dB (- 9 to - 45 dBm) Dynamic Input Range
On-Board Descrambler
Synchronous to Asynchronous Converter
Carrier Detect Output
ORDERING INFORMATION
APPLICATIONS
Stand-Alone Modems
Remote Terminals
Built-In Modems
1-99
Part Number
Package
XR-2121/22CN
XR-2121/22CP
Ceramic
Plastic
Operating Temperature
O°C to
O°C to
+ 70°C
+ 70°C
XR·2121/2122
ELECTRICAL CHARACTERISTICS
Tast Conditions: VDD = 6V, VSS = -6V, XIN = 1.8432 MHz, TJ = 25°C
SYMBOL
DIGITAL SECTION
VOH
VOL
VIH
VIO
liN
IOH
IOl
Cl
PARAMETERS
MIN
Output High Voltage
Output low Voltage
Input High Voltage
Input low Voltage
Input Current
Output Drive Current
Output Drive Current
ClK OUT Drive Capability
TYP
MAX
3.5
0.5
3.5
1.5
10
-0.5
2.0
-1.5
4.0
50
UNIT
V
V
V
V
/loA
mA
mA
pF
CONDITIONS
10 - 1 mA
10 = 1.5 mA
VOH = 3.5V
VOL = 0.5V
ANALOG SECTION
liN
VOCAR
V2H
ViCAR
IDD
VSUP
Terminal:
or
CPU
Input Impedance RXCAR
Output level - TX CAR
2nd Harmonic Content TXCAR
Dynamic Range - RX CAR
Power Supply Current
Supply Voltage Range
kO
50
0.3
V rms
0.4
-40
-9
-45
100
±6
150
dB
dBM
mA
V
XH·2122
XR-2121, Rl ~ 6000
Referenced to Vo CAR
XR-2122
MODEM
UART
SIGNAL
PROCESSOR
Telephone
or Leased
Line
RS ;.... 232
HANDSHAKING CONTRO
~~ACU-~
Figura 1. Modam Block Diagram
1·100
XR·2121/2122
PRINCIPLES OF OPERATION
SPEED SEl: 1200 bps PSK or 0 to 300 bps operation is
selected by this input.
Figure 1 illustrates a general block diagram of a complete modem system. These blocks are necessary for
the modem to be able to: (1) Interface to the telephone
network; (2) accept control signals and supply timing,
(3) process data, and (4) modulate and demodulate
data.
ENABLE CONY/CONY lENGTH: These pins select the bit
length of input characters, and if the internal asynchronous to synchronous converter is used or not. Input character length is either 9 or 10 bits.
The XR-2121 and XR-2122 provide the modulation and
demodulation function, and when used with the
XR-2120 filter, perform the complete modem signal
processor function.
TX DATA: This is the input for data to be transmitted.
XR-2122
Description of Control Inputs and Outputs
ClK IN: A 1.8432 MHz clock is fed into this pin from the
XR-2121 or other source.
XR-2121
RC elK: A 1200 Hz Signal is available at this output for
XIN, XoUT: These are the crystal input pins.
synchronization of other circuits.
ClK OUT: This provides a buffered crystal output for the
XR·2122 or other circuits.
CD, RCD, CCD: CD provides a carrier detect output indicating a valid carrier is present at the RX CAR input.
The RCD and CCD input provide the carrier ON and carrier OFF times.
TRANS ClK: A 1200 Hz square wave is available at this
output for a terminal or other circuits.
MODE SEl: Answer or originate mode is selected by this
TRANS ClK IN/EXT: This selects whether an external
pin.
trans clock at the EXT TRANS ClK input is used for carrier timing or an internal clock is used.
RX DATA: Demodulated Data is present at this output.
EXT TRANS ClK: Provides an input for an external trans-
RX CAR: Received modulated carriers are input to this
mit clock input.
pin.
TX CAR: This output provides a digitally synthesized
sine wave output. The modulation on this carrier, either
FSK or PSK, is determined by the speed input.
ATTACK TIME: These pins are used to set attack and decay times of the input AGC circuit.
APPLICATIONS INFORMATION
TX ENABLE: This input can be used to enable or disable
the TX CAR output.
Figure 2 shows the interconnections between the
XR-2121 and XR-2122 Modulator/Demodulator, and the
XR-2120 Filter. Here the XR-2121 supplies the XR-2122
with its clock input. The auto speed function of the
XR-2122 sets the speed of the XR-2121 automatically
through the speed indicator output of the XR-2122.
CTS: The clear-to·send Signal is supplied by this pin.
MODE: Answer or originate mode of operation is selected by this pin.
1.8432 MHZ
R -::.:2",'2'-'.'_,
,.--.....!OXcc
r-'~-1 XIN
c.............-1
CAR
ADJ
XOUT
COMP
XR - 2125
TXD
~
TXD
TxD
TxCAR
TXC
SYNC
TXC
XR-2120A
600n
TxCAR
elK OUT
MODULATOR
XR - 2122
DEMODULATOR
TELEPHONE
ClK
IN
RxD
RxD
RxC
IIC
CLK
IN
ClK
IN
SYNC
NETWORK
RxCAA
RxCAR
600n
FILTER
DATA
BUFFER
Figure 2, Complete 1200/300 BPS Modem Signal Processor
1-101
><
XR·212AS
BElL 212A TYPE MODEM
:a
•
I\)
......
......
........
I\)
R"
I\)
......
VDO
XR·2125
DATA BUFFER
-t-
R, r-_!!!...AI
EXT Txc
I
I
TXOIN
......
......
o
I\J
L
RXDOUT
R,
RXClKOUT
MANUAL
1200J300
SELECT
CD
R,~
...
ANAlOGGND
'¢'
DIGITAL GND
Voo
vss
DAA
-+5V· O.25v
·5V· O.25v
FCC REGISTERED CIRCUIT
FOR DIRECT CONNECT
XR-212AS Bell 212A Type Modem
--
T,
C.
III
~
TELEPHONE
C NETWORK
I\)
I\)
XR·2123
PSK Modulator/Demodulator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR·2123 provides the phase·shift keying (PSK)
Modulator and Demodulator Functions for implement·
ing a full·duplex 1200 bps or 2400 half·duplex Modem
System. Using fully digital circuit techniques allows the
XR·2123 to be externally programmed for operation for
Bell Standards 201 Band C or 212A (1200 bps only),
and CCITT V.22 or V.26. Internal logic and timing func·
tions minimized external parts, while crystal controlled
operation provides stable and accurate operation.
VOO
LSD
C22
Nay
RXS
The XR·2123 utilizes CMOS technology for low power
operation while providing single + 5 volt operation,
packaged in a standard 28 pin DIL plastiC or ceramic
package. The XR·2123 operates from O°C to 70°C.
PSK
MODULATOR
26
SYN
RBA
BAC
RXD
iiXc
QUA
RBY
FEATURES
Single + 5 Volt Operation
Low Power Consumption (Typ 10mw)
1200 bps Full·Duplex
2400 bps Half·Duplex
Programmable for US or European Standards
(CCITT)
Dibit PSK (DPSK) Operation
Crystal Controlled
Synthesized Sine Wave Modulator Output
Adjustable Modulator Output Amplitude
Input Protection
TTG
MOC
CCl
CONTROL
lOGIC
TXC
TRM
V,22
TXS
19 COD
APPLICATIONS
TlV
18 RTE
Bell Standard 201 or 212A Modems
CCITT Standard V.22 or V.26 Modems
RlO
ABSOLUTE MAXIMUM RATINGS
4CR
ANI
vss
RTS
Power Supply
Power Dissipation
Derate Above 25°C
Operating Temperature
Storage Temperature
All Input Voltage
DC Current Into Any Input
5.5V
1.0W
5 mW/oC
O°C to 70°C
-65°C to 150°C
-O.5V to (VDD to O.5V)
±1 mA
Package
XR·2123CN
XR·2123CP
Ceramic
Plastic
The XR·2123 provides the complete demodulation,
modulation, and control functions for DPSK Modem
Systems. The Demodulation is a digital type using
Phase·Locked Loops (PLL). The Modulator provides a
synthesized sine wave output in a dibit Phase·Shift Key·
ing (DSPK) Format. The Phase Shifts and carrier fre·
quencies are programmable with logic inputs.
Operating Temperature
O°C to
O°C to
TOA
SYSTEM DESCRIPTION
ORDERING INFORMATION
Part Number
PSK
DEMODULATOR
+ 70°C
+ 70°C
1·103
XR·2123
ELECTRICAL CHARACTERISTICS
Test Conditions: VDD = + 5V, VSS
Digital Inputs:
= OV, Tj = O·C to 70·C
RXS, MOC, CCL, RTS, ANS, TDA, RTE, COD, V22, TXC, BAC, SYN, NSY, LSD
Digital Outputs: C22, RBA, RXD, QUA, TBA, 4CR, TTG, RBY, RXC
SYMBOL
PARAMETERS
VOL
VOH
VIL
VIH
IlL
IDD
CI
tR
tF
VTXS
Output Low Voltage
Output High Voltage
Input Low Voltage
Input High Voltage
Input Leakage Current
Power Supply Current
Input Capacitance
Low to High Logic Transition Time
High to Low Logic Transition Time
Transmitted Carrier Signal Level
MIN
TYP
4.6
0.5
3.5
MAX
UNIT
CONDITIONS
0.4
V
V
V
V
pA
MA
pF
nS
nS
dBm
IOL = 1.6 MA
IOH = 1.0 MA
11
5
100
2.5
5
20
20
4
-9
CL = 10 pF
CL = 10 pF
VPIN 11 = O.BV
EQUIVALENT SCHEMATIC DIAGRAM
TLV ~~.
10
17
13
TDA
TXC
FiTs
RTE
MODULATOR
21
.~. TRM
18
20
COD
19
ANS
16
(4.608 MHz)
BAC
----
LSD
28
NSY
27
~
~
~
~
,
~'N
+,
VDD
VSS
20~ I - or 415 ~
+32
r--
r
~
.-f.;. 2/15
SYN
CCl
,
~~
25
~~
GATING
-1""10 or
26
RXS
4CR
1~. RlD
15
V.22
MOC
TXS
--i
--
r;::":1.
J-1-.r.;+32
2
12.:J
22
6 or 16 I
~
.:I
C22
TTG
24
4
RBA
23
RBY
r-~.
OUA
~~
RXD
'---
DEMODULATOR
1·104
XR·2123
·Coding
00
01
10
11
European/US Sto.
+90°
0°
180°
-90°
ALT.A
chronized digital phase-locked loop which maintains
the basic timing and initiates all phase shift detection
operations.
ANSI Std.
+45°
135°
315 0
225°
ALT.B
This filtered signal is then applied to Pin 3 (RXS). The
phase-locked loop is synchronized by the signal available from Pin 13 (4CR). Synchronization is maintained
by generating a sync pulse from the phase-locked loop
and applying it to Pin 26 (SYN). RBA, Pin 4, provides the
output from the receiver's synchronizer. This output
command the phase shift detector to start a single
measuring cycle.
RTE (Pin 18) controls the baud rate of the modem.
When RTE is LO the transmission rate is 1200 bls, and
when RTE is HI, the transmission rate is 2400 b/s. ANS
(Pin 16) controls the answering tone (2100 Hz) to the
transmission line. When ANS is LO and V22 is HI, the
answering tone (2100 Hz) is connected to the transmission line.
Coherent demodulation techniques are used in the receiver section. The reference frequency used to detect
phase shifts in the carrier from the transmission line is
generated in an internal phase locked loop. In the case
of a 1200 bitlsec application, the reference frequency
is synchronized to the line carrier.
BAC (Pin 25) is the time base input which is 512 times
the normal receiver baud timing. In the case of a 1200
bls, full duplex modem, BAC = 307.2 kHz or MOC/15
TXC (Pin 21) is the transmitter bit timing input. It may be
tied directly to TIG (Pin 22) which is the transmitter timming set by RTE.
In applications requiring 2400 bitslsec and upwards,
the reference frequency is five (5) times the carrier.
This permits phase detection at much higher rates.
RTE HI TIG = BAC/256
RTE LO TIG = BAC/512
This phase shift detector subtracts the carrier from the
reference. The difference sets a "window" in which
standard pulses are counted. The following table shows
the correlation between angles and counts:
Of course external timing signals may be applied for
nonstandard uses.
TLV (Pin 11) sets the transmitter amplitude by using a
resistive divider between + 5V and ground. This signal
may be set between 1.0V and 5V. TRM (Pin 9) signals
that the modem is in the transmit mode. When TRM is
HI, the unit is transmitting, When TRM is LO, the unit is
not transmitting. The relationship between the voltage
at TLV and the amplitude of TXS is shown in the Electrical Characteristics.
Phase Angles (0)
A
B
90
180
270
45
135
225
315
o
Pulse Counts
Reg. 1 Reg. 2
64
64
192
64
192
192
64
192
MSB (bit 8)
Reg. 1 Reg. 2
o
0
1
1
0
1
1
o
The counting results should be identical to the table. If
not, the reference is either ahead or behind the ideal
phase. This information is decoded and the phase
locked loop is either accelerated or decelerated.
The data to be modulated and transmitted is applied at
TDA (Pin 17). The modulated signal is output at TXS (Pin
10).
DEMODULATION
Once demodulation has been accomplished, the data is
available at Pin 5 (RXD). The data at RXD is changed to
"1" when Pin 28 (LSD) is "0" or Pin 27 (NSY) is "1".
LSD is a line signal detector which tells the system that
there is a signal present. The 1.8 kHz filter is applied to
a level detection circuit, which consists of a comparator. NSY is a "new synchronizer" input. When it is "1 ",
data is disabled; when "0", date is enabled. However,
on the transition from "1" to "0", the receiver clock,
Pin 24 (RXC), immediately synchronizes with the SYN
signal during the next symbol interval. RXC provides the
user with bit rate timing (baud timing) for synchronized
transmission to the receiving terminal. The following table represents the above discussion.
There are two types of incoming signal processing
which will be discussed. The first concerns full duplex
reception. In this case, using the Bell 212A as our example, the received signal will be centered on 1200 Hz.
The signal is passed through a 1200 Hz filter and applied to a peak detection circuit. This signal is then
passed through an amplification stage and applied to
Pin 3 (RXS). After the amplifier stage, the signal is simultaneously applied to a sync-generating circuit and
passed to Pin 26 (SYN). The output of the peak detector
is also applied to a level detector and provides the input
for Pin 28 (LSD) and Pin 27 (NSY).
LSD
0
0
1
1
1
The second type of modem to discuss is a half-duplex
system. Speeds of up to 3200 bls are available for use
on leased lines. The received signal is coupled through
the line interface to a 1.8 kHz filter. The signal is then
sent to a peak-detector circuit and is then applied to a
narrow band filter. The signal is then applied to a syn-
1-105
NXY
0
1
0
1
!
RXD
1
1
Data
Data
RXC
free running
free running
Synchronized
Synchronized
Fast Synchronization
XR·2123
Pin 2 (C22ITBY) provides the carrier clock signal for
both reception and transmission. When V22 is "0", C22
is defined as in the following table:
V22
ANS
o
o
o
o
FITS
COD C22
o 1228.8 kHz (512 x 2400 Hz)
1
614.4 kHz (512 x 1200 Hz)
o 614.4 kHz
1
1228.8 kHz
o
1
o
TXC
1
...112=====r----:--
'L_ _ _ _ _ _ _
,.........., ......::; ""'---"""'1""""-""
11 ,.....--....L,e:::.,,14
3:•
"C7
P
~.c--F'
TXS
raM ..J
R,.
RTS
..,!-__________...I12==r-----
f",
TXS
C22 may be tied directly to Pin 8 (CCl). With V22
"1", TBY provides transmitter byte timing which is 16
times the transmitter baud timing.
TBM
Ie, , cJc..' c l ' D
QI--r-'V-rC7
I~
I-, •
'4
v
,....,L
'P~
..J
I
Figure 1. Timing Diagram of the Transmitter
10
~
SVN
V
10
I
;?
~
·20
z
R.D _ _ _ _ _ _ _ _ _ _LI~'~I~'~ICJCCI4LIII\II~'~I~Ir_
V
0:
>
30
RTE 1
Figura 2. Timing Diagram of the Receiver
~
40
V221
/
·50
0.01
0.1
1.0
TOV
-UU1SUlrU1Sl.fl.nJ"1..fl..flILI'LJl.J1.f"
TTO
-,
1
\
1
L-
10
RTE 0
RBV
Figure 5. TXS vs VTLV
.BA
,C====~=::::::::===~L
Pin 12 (RlD) provides a signal which indicates to the reo
ceiving terminal that a signal has been detected. RlD
= "1" when a received signal is detected, and RlD =
"0" when a received signal is not present.
Figure 3. Timing Circuit
RBY, Pin 23, provides a timing signal for 3000 b/s, half·
duplex modem usage. It is similar in use to RXC.
QUA, Pin 6, provides an indication of the quality of the
demodulated signal. It is "0" when errors are greater
than 22.5° during one symbol interval. This phase error
is measured with respect to RBA.
Figure 4. Quality
1-106
XR·2123
·5V
~•
-=L
·5V
XR.!!!!...lvOO
TtV
11
iNs
16
c-:-'-'="____________tiIf
18
ANS
I
1.8k
1
TX.~ I> ~
10
OG"'·O""O'--_ _ _ _ _ _ _ _ _ ~~2 19
• ~.L 20
Transmit Filcer
13 UR
14 x IBW Hz)
T~},
i
I .r,~--------~17
I
._
RIo 15
I
TBA p
I
IICC ;
+I
eeL
_ _ _ .-11~ 25
I
I
I
L.
-.!J.'. ."
T~
RXC
/1(3 .JJ
, ~.--IRXD
--11~
_!2'iC
__h~tA
nc~----------~~~
-~
-.-
28
:?:J
21.
l
TRN
56
L----T"~V~55~-~
-rC"'AR:!.-.,<-____________•_ _•• _ _ ._________ _
FjEC
¢'-H"'D"'X____ •________________._ _........--I
fOp
~~----------------·-----+_~l
CAR
REC
HOI(
LOP
Carrier detector
Re,"elve mode
Half ,fupleK
··0·· Connects Local Leop
~--I
V.26/201 Modem 2400 bps
·5V
VOO
LOP ." .. Connilcls Local Loop
ANS .. , .. Connects answering tone to line
CHN
Selects the channels
V.221212A (PSK Only) Modem 1200 bps
1-107
XR·2123
OUTPUTS
The following is a description of the operation of each
pin of the XR-2123.
INPUTS
Pin
Number
Deslgnation
1
14
VDD
VSS
+5V ± 0.5%
ground
19
20
16
COD
V.22
ANS
code
V.22 mode
answering tone
Description
V22
0
11
TlV
~ Mode
0
0
0
0
1
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Transmitter level.
The sending level is directly dependent
on the voltage of TlV signal 1 ... 5.5V
(Soo Eloctrlcal Charactorl.tlcs)
TDA
Transmitted data
21
TXC
Transmitter bit timing
18
RTE
Rate
low bit rate
1 high bit rate
15
RTS
28
LSD
Transmitted signal
Modulated 8 level sine. wave
Transmit mode
Description
9
TRM
13
4CR
4
2
C22
V22 = 0
x
Carrier frequency in square wave
E!.!!.
17
SYN
TXS
Carrier clock for V.22 modem
C22 can be connected directly 10
8 Jf9.l)
V22 ANS COD C22
1228.8 kHz (512 x 2400 Hz)
0
0
0
6144 kHz (512 x 1200 Hz)
0
0
1
0
1
6144 kHz
0
0
1
1228.8 kHz
1
V.22/212A modem; Tx high ch;
Rx high ch. (local loop)
V.22/212A modem; Tx low ch;
Rx low ch. (local loop)
V.22/212A modem; Tx high ch;
Rx low ch. (answer mode)
V.22/212A modem; Tx low ch;
Rx high ch. (call mode)
Answering tone (2100 Hz)
Answering tone (2225 Hz)
V.26 modem code A (n x 90')
V.26 modem code B (n x 45')
Modulator clock
4.608 MHz square wave
26
10
iiNs COD
MOC
BAC
Deslgnation
selection
7
25
Pin
Number
TBY
V22 = 1
Transmitter byte timing
Square wave 16 x transmitter baud timing
22
TTG
Timing for transmitter
RTE = 0 TTG = BAC/512
RTE = 1 TTG = BAC/256
23
RBY
Receiver byte timing
Square wave 16 x received baud timing
24
RxC
Received bit timing
4
RBA
Received baud timing
6
QUA
Quality of demodulated signal.
"0" when error is demodulated signal
is more than 22.5°
5
RXD
Received data
12
RlD
Received data. Ready signal to terminal.
o
Request·to·send
1 transmitter clamped
o transmitter sending
V.221212A APPLICATION
Baud clock
512 x nominal receiver baud timing
Synchronizaton
The receiver baud timing will synchronize
to this square wave signal
INPUT
STATE
V22
COD
COD
La
La
HI
Line signal detector
1 Receive
27
NSY
New synchronizing
l·state torces the received data to "1" state.
New synchronizing Is made when the NSY
goes from 1 to 0
3
RXS
Received signal
Received signal in square wave form
8
CCl
Carrier clock
512 x Received carrier signal
(Max. 4.608 MHz)
fc
fc
'Coding
o The receiver Is clamped
00
01
11
10
1200 BPS
EURO/US
DESCRIPTION
2400 Hz'
1200 Hz'
European/US SId.
0
90
0
270 (-90)
180
600 BPS
EURO
modes i, ii, iii, iv
V.261201 APPLICATION
TRANSMISSION
The transmission sequence is initiated by the external
signal at RTS (Pin 15) changing from a HI state to a La
state. The transmission mode may be selected from
several possibilities by the concurrent manipulation of
the external signals at RTE (Pin 18), V22 (Pin 20), COD
(Pin 19), ANS (Pin 16). With the input frequency at MaC
(Pin 7) at 4.608 MHz, the following table applies:
1-108
INPUT
STATE
V22
COD
COD
HI
La
DESCRIPTION
fc = 1800Hz
European/U.S. Std. Coding"
ANSI Coding"
"Coding
European/US SId.
ANSI SId.
00
01
11
10
o
90
180
270
all. A
45
135
225
315
all. B
XR·2125
ADVANCE INFORMATION
Data Buffer
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2125 is a logic circuit designed to perform the
data buffer function for Bell 212A Type Modem Systems. Both asynchronous to synchronous and synchronous to asynchronous conversion are performed at
nominal data rates of 1200 bits per second. The XR2125 is selectable for character lengths of 9 or 10 bits.
Separate enable/disable inputs are supplied for async
to sync and sync to async converter sections. These inputs allow the same data lines to be used for asynchronous or synchronous operation.
VDD
TXD OUT
TXC IN
eLK IN
AXD IN
The receive data buffer section (sync to async) accepts
input sync data (typically from the modem demodulator) at 1200 BPS and converts it to a 1219 BPS async
data format. The transmit data buffer (async to sync)
accepts input async format data with a data rate of
1200 BPS ± 1 %, - 2.5 % and it is synchronized to
1200 BPS, which is typically sent to the modem modulator. This section also provides break signal automatic
extension.
Axe IN
10/9
ORDERING INFORMATION
The XR-2125 is constructed using silicon gate CMOS
technology for low power operation. Operation is designed for an input clock frequency of 1.8432 MHz. The
XR-2125, available in a 14 Pin package, is designed for
single 5 volt operation.
Part Number
Package
Operating Temperatura
XR-2125CN
XR-2125CP
Ceramic
Plastic
DOC to 70°C
DoC to 70°C
SYSTEM DESCRIPTION
FEATURES
The XR-2125 provides the complete interface between
synchronous and character - asynchronous data systems. The synchronous side consists of two data lines
TXD and RXD, each with their respective clocks, TXC
and RCX. The synchronous portion is designed for data
rates of 1200 ± .01 % BPS. The asynchronous side
handles data oriented in characters where the actual
data bits are bracketed by a start and stop bit. Character lengths are 9 or 10 bit (7 or 8 data bits), pin selectable.
Bell 212A Compatible
Asynchronous to Synchronous Conversion
Synchronous to Asynchronous Conversion
Independent Disable Input for
.
Receiver and Transmitter Sections
1.8432 MHz Clock
Break Signal Automatic Extension for Transmitter
1200 BPS + 1 %, - 2.5 % Operation
Single 5 Volt Operation
To perform this interface, the XR-2125 consists of two
main sections: synchronous to asynchronous (receive
section) converter to reinsert stop bits deleted by the
sending modem. The other section is asynchronous to
synchronous converter (transmit section) to add or delete stop bits to correct the transmit data rate to 1200
BPS. This section also extends the break signal to two
character lengths plus three bits when it comes in at a
shorter period.
APPLICATlDNS
Bell 212A Data Buffer
ABSOLUTE MAXIMUM RATINGS
Power Supply
Input Voltage
DC Input Current (any input)
Power Dissipation
Storage Temperature Range
- 0.3 to + 5.5V
- 0.3 to VDD + 0.3
±10 mA
250 mW
- 65°C to + 125°C
A standby mode is included to put the XR-2125 in a low
supply current, non-operative, mode on command.
1-109
XR·2125
ELECTRICAL CHARACTERISTICS
Tast CondHlons: VDD = ± 5V ± 5 %, TJ = 25°C, ClK IN = 1.8432 MHz, unless otherwise specified.
SYMBOL
PARAMETERS
MIN
TYP
MAX
UNIT
0.4
V
V
V
V
rnA
CONDITIONS
DC CHARACTERISTICS
VOL
VOH
Vil
VIH
IOl
IOH
liN
IDD
Output low Voltage
Output High Voltage
Input low Voltage
Input High Voltage
Output low Current
Output High Current
Input Cu rrent
Supply Current Quiesent
IDD
Supply Current Standby
2.4
2
0.8
4
400
±10
80
SOO
10
p.A
p.A
p.A
p.A
p.A
IOl = 1.S rnA
IOH = 400 p.A
TA = 70°C
AC CHARACTERISTICS
ftxd
f scx
tdtxd
th
f rxco
tWrxco
TXD In Baud Rate
Internal Sampling
Clock Frequency
TXD Out Delay Time
1170
RXD Out Delay Time
RXC Out Frequency
RXCO Out Pulse Width
1200
1212
BPS
1200
10.5
Hz
Bits
See Note 1
Cl = pF; 10/9= Hi
8
1219
410
Bits
Hz
/ls
10/9= Hi
Note 1: f sxc = f clk/153S. When the character start bit comes, internal sampling clock is synchronized with
this bit.
10/9
LOAD PULSE GENERATOR
19.2 KHZ
ClKIN
+96 COUNTER
RS
PRESETT ABLE +16 COUNTER
TX EN
RX EN
RXDIN
RXCIN
RXD OUT
5 t-------+-----4
RXC OUT
6 1--------1
EQUIVALENT SCHEMATIC DIAGRAM
1-110
Interface Circuits
XR·1488/1489A
Quad Line Driver/Receiver
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAMS
The XR-1488 is a monolithic quad line driver designed
to interface data terminal equipment with data communications equipment in conformance with the specifications of EIA Standard No. RS232C. This extremely versatile integrated circuit can be used to perform a wide
range of applications. Features such as output current
limiting, independent positive and negative power supply driving elements, and compatibility with all DTL and
TIL logic families greatly enhance the versatility of the
circuit.
The XR-1489A is a monolithic quad line receiver designed to interface data terminal equipment with data
communications equipment. the XR-1489A quad receiver along with its companion circuit, the XR-1488
quad driver, provide a complete interface system between DTL or TIL logic levels and the RS232C defined
voltage and impedance levels.
ABSOLUTE MAXIMUM RATINGS
Power Supply
XR-1488
XR-1489A
Power Dissipation
Ceramic Package
Derate above + 25°C
Plastic Package
Derate above + 25°C
±15 Vdc
+10 Vdc
1000 mW
6.7 mW/oC
650 mW/oC
5 mW/oC
SYSTEM DESCRIPTION
The XR-1488 and XR-1489A are a matched set of quad
line drivers and line receivers designed for interfacing
between TIUDTL and RS232C data communication
lines.
The XR-1488 contains four independent split supply line
drivers, each with a ± 10 mA current limited output. For
RS232C applications, the slew rate can be reduced to
the 30 V/p.S limit by shunting the output to ground with a
410 pF capacitor. The XR-1489A contains four independent line receivers, designed for interfacing RS232C to
TIUDTL. Each receiver features independently programmable switching thresholds with hysteresis, and
input protection to ± 30 V. The output can typically
source 3 mA and sink 20 mA.
ORDERING INFORMATION
Part Number
Package
XR-1488N
XR-1488P
XR-1489AN
XR-1489AP
Ceramic
Plastic
Ceramic
Plastic
Operating Temperature
O°C
DOC
DoC
O°C
to
to
to
to
+70°C
+70°C
+ 70°C
+ 70°C
1-111
XR~1488/1489A
ELECTRICAL CHARACTERISTICS
Test CondHions: (V +
=
+ 9.0 ± 1 % Vdc, V -
= - 9.0
± 1 % Vdc, TA
= O°C to + 70°C, unless otherwise noted)
XR·1488 LIMITS
PARAMETERS
MIN
Forward Input Current
TYP
MAX
UNITS
1.0
1.6
mA
Reverse Input Current
10
p.A
Output Voltage High
V+
V+
=
=
Vdc
+9.0 Vdc, V- = -9.0 Vdc
+13.2Vdc,V- = -13.2 Vdc
+6.0
+9.0
+7.0
+10.5
Output Voltage Low
V+
V+
=
=
Vdc
+9.0 Vdc, V- = -9.0 Vdc
+ 13.2 Vdc, V- = -13.2 Vdc
-6.0
-9.0
-7.0
-10.5
Positive Output Short-Circuit Current
+6.0
+10
+12
Negative Output Short-Circuit Current
-6.0
-10
-12
=V =0
Positive Supply Current (RI = 00)
Yin = 1.9 Vdc, V+ = +9.0 Vdc
Yin = 0.8 Vdc, V+ = +9.0 Vdc
Yin = 1.9Vdc, V+ = +12Vdc
Yin = 0.8 Vdc, V+ = + 12 Vdc
Yin = 1.9 Vdc, V + = + 15 Vdc
Yin = 0.8 Vdc, V+ = + 15 Vdc
Negative Supply Current (RL = 00)
Yin = 1.9 Vdc, V- = -9.0 Vdc
Yin = 0.8 Vdc, V- = -9.0 Vdc
Yin = 1.9 Vdc, V- = -12 Vdc
Yin = 0.8 Vdc, V- = -12 Vdc
Yin = 1.9 Vdc, V- = -15 Vdc
Yin = 0.8 Vdc, V- = -15 Vdc
300
Output Resistance V +
Yin = 1.9 Vdc,
RL = 3.0 kO
mA
mA
Ohms
IVol
=
±2.0V
mA
+15
+4.5
+19
+5.5
+20
+6.0
+25
+7.0
+34
+12
-13
0
-18
0
-17
mA
Power Dissipation
V+ = 9.0 Vdc, VV+ = 12 Vdc, V-
= -9.0 Vdc
= 12 Vdc
Switching Characteristics (V + = + 9.0
CONDITIONS
= 0 Vdc
Yin = + 5.0 Vdc
Yin = 0.8 Vdc,
RL = 3.0 kO
Yin
0
-23
0
-34
-2.5
mW
333
576
± 1 % Vdc, V -
=
- 9.0 ± 1 % Vdc, TA
=
+ 25°C)
Propagation Delay time (tpd +)
150
200
ns
ZL
Fall Time
45
75
ns
ZL
Propagation Delay Time (tpd )
65
120
ns
ZL
Rise Time
55
100
ns
ZL
1-112
= 3.0k and 15 pF
= 3.0k and 15 pF
= 3.0k and 15 pF
= 3.0k and 15 pF
XR·1488/1489A
ELECTRICAL CHARACTERISTICS
Test CondHlons: Response control pin is open. (V+
+5.0 Vdc ± 1 %, TA = O°C to + 75°C,
unless otherwise noted)
XR-1489 LIMITS
PARAMETERS
MIN
TYP
MAX
Positive Input Current
Yin = +25 Vdc
Yin = + 3.0 Vdc
3.6
0.43
8.3
Negative Input Current
Yin = -25 Vdc
-3.6
-
UNITS
CONDITIONS
mA
mA
8.3
Yin = - 3.0 Vdc
-0.43
Input Turn-On Threshold Voltage
TA = +25°C, VOL :s0.45 V
1.75
1.95
2.25
Input Turn-Off Threshold Voltage
TA = + 25°C, VOH
14o--~---~-.....,.-K1-..,.....-'\M....-o
INPUT 4
R£SPO,,",SE
CONTROL
........."""""-t---+
2o---~
INPUTS
INPUT
ONO 7+
1-113
,o--'VVv_..........,....-C
14
v'
J OUTPUT
Disk Drive Circuits
XR·2247/2247A
Floppy Disk Write Amplifier
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-224 7/224 7A is a write amplifier designed to provide the complete interface between write data signals
and tunnel-erase magnetic heads. Although primarily
intended for floppy disk drive systems, the XR-2247/
2247A can also be used in other magnetic media systems such as tape drives. To minimize external part
count for dual head systems, complete head switching
is does internally with emitter-coupled PNP transistors
in the XR-2247 and diodes (which offer improved broadband noise characteristics) In the XR-2247A. Write and
erase currents are each externally programmable with
a single resistor. Also included is circuitry for inner
track write current compensation. To prevent false
write current outputs during power-on, an inhibit input
has been provided. Erase turn-on and turn-off times are
each externally programmable.
Vee
CTO
v.,
~
RW
READOUT
~
~
HEADO
lOOH
~
GNO
I,ws
HS
The XR-2247/2247A, available In a 22-Pin DIP, operates
from a single power supply and provides TTL compatible inputs.
I.,
(GND
FEATURES
ORDERING INFORMATION
Fully Programmable Write and Erase Currents
Fully Programmable Erase Turn-onlTurn-off Times
Internal Head Switching for Dual Head Drives
Single Supply Operation
Inner Track Write Current Compensation
Inhibit Input
TTL Compatible Inputs
Low External Parts Count
Part Number
Package
XR-2247CN
XR-2247CP
XR-2247ACN
XR-2247ACP
Ceramic
Plastic
Ceramic
Plastic
Operating Temperature
O°C
O°C
O°C
O°C
to
to
to
to
+70°C
+70°C
+70°C
+70°C
SYSTEM DESCRIPTION
The XR-2247/2247A accepts a serial binary data
stream input. With the write mode selected, negative
transitions of this input signal will alternately provide
write current to each half of the head. The XR-2247/
2247A provides two sets of current outputs for dual
head drives, with the head select (HS) control determining which is active. The write current is externally programmed with a resistor between the internal voltage
reference and the current setting input. Two highcurrent open-collector outputs provide the erase coil
drive. Turn-on and turn-off delay circuitry is provided for
these outputs, with the delay externally programmed.
APPLICATIONS
Floppy Disk Drives
Single/Dual Head Systems
Magnetic Tape Write Amplifier
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage (Pin 1)
16 V dc
Input Voltage (all digital inputs)
-0.2V to + 16 V dc
10 mA dc
Reference Current (Pin 4)
Output Current (Pins 2, 10, 12, 22)
100 mA dc
Storage Temperature
-55°C to + 150°C
Operating Junction Temperature
150°C
Power Dissipation
750 mW
Derate Above 25°C
6.5 mW/oC
An inhibit input (INH) is provided to disable the outputs
to prevent false writing during power-on. With the read
mode selected, internal head switching channels the
proper head to the read outputs.
1-114
XR·2247/2247 A
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C, VCC
SYMBOL
ICC
VCC
=
12V, Rref
=
PARAMETERS
Power Supply Current
Power Supply Range
10 kll, unless otherwise specified.
MIN
9
TYP MAX
UNIT
13
12
20
16
mA
V
-
CONDITIONS
VCC
= 9V to 16V
DIGITAL INPUT VOLTAGE
High Level Voltage
VIH
Low Level Voltage
VIL
2.0
-
-
0.8
V
V
DIGITAL INPUT CURRENTS
High Level Current
IIH
Low Level Current
IlL
-
0.1
15
4.0
100
p.A
p.A
9.5
10.2
0.1
0.2
V
V
20
1.5
0.55
1.1
p.A
V
mS
mS
VCC = 16V
lout = 100 mA
RDI = 4.55 KIl, CDI
RD2 = 9.54 KIl, CD2
8.0
8.5
9.0
7.8
8.2
8.8
0.65 0.80 0.95
- 0.03 15
V
V
V
p.A
Iref - 1 mA
Iref = 10 mA
Iref = 1 mA
7
-
12
V
3.7
4.1
4.5
mA
IRWS
=
Low
5.1
5.7
6.3
mA
IRWS
=
High
-
-
40
p.A
IRWS
=
Low (Note 1)
-
4
1
-
CTO Dr CT1 OUTPUTS
Output High Voltage
VCTH
Output Low Voltage
VCTL
ED Dr E1
IOL
VOEL
TD ON
TDOFF
OUTPUTS
Output High Leakage
Output Low Voltage
Erase Turn·on Delay
Erase Turn·off Delay
CURRENT SOURCE
Reference· Pin 4
Vref
Vmir
IWRL
V comp
IWR
IWRS
AIWR
Iref Input Voltage· Pin 13
Write Current Off Leakage Pins 15, 16, 19, 20
Current Sink Compliance Pins 15, 16, 19,20
Write Current wlo IRWS Pins 15, 16, 19,20
Write Current with IRWS Pins 15, 16, 19,20
Difference in Write Current
READ OUTPUT
Differential Noise Voltage at Read
eno
Output 2247
2247A
-
0.01
1.0
0.45 0.5
0.9
1.0
Note 1: Difference = 1(lplN 15,16 - IplN 19,20)1
1·115
VI
= 2.4V
lout - 100 mA
lout = 1 mA
= 0.1
= 0.1
p.V rms SW = 10 Hz to 1.0 MHz
p.V rms IS = 200 p.A
p.F
p.F
XR·2247/224 7A
AC SWITCHING CHARACTERISTICS
Test Conditions: Test Circuit of Figure 4, VCC = 12V, TA = 25°C, IRWS = O.4V
SYMBOL
PARAMETER
td1
Delay from R/W going low through O.BV
to CTO or CT1 going high through 9.0V.
td2
Delay from RIW going low through O.BV
to AO, A1, BO, or B1 settling to final
value.
MIN TYP MAX UNIT
-
0.11
-
,.,.s
0.40
-
,.,.s
CONDITIONS
R/W signal at Pin 5: f = 50
KHz, 50% duty cycle,
amplitude = O.4V to 2.4V
See Figure 1
td3
Delay from R/W going high through 2.0V to
AO, A 1, BO, or B1 settling to final value.
-
0.20
-
,.,.s
td4
Delay from RIW going low through O.BV
to Vref going high through B.OV.
-
0.13
-
,.,.s
td5
Delay from RIW going high through 2.0V
to Vref going low through 1.0V.
-
3.50
-
,.,.s
td6
Delay from HS goin9 hi9h through 2.0V
to CTO going high through 9.0V.
-
0.12
-
,.,.S
td7
Delay from HS going high through 2.0V
to CT1 going low through 1.0V.
-
0.11
-
,.,.S
tdB
Delay from HS going low through O.BV
to CTO going low through 1.0V.
-
0.10
-
,.,.S
td9
Delay from HS going low through O.BV
to CT1 going high through 9.0V.
-
0.20
-
,.,.s
tlO
WD low hold time.
150
-
-
ns
t11
WD high hold time.
500
-
-
ns
td12
Delay from WD going low through 1.4V
to AO or A1 turning on through 50%.
-
75
-
ns
td13
Delay from WDgoing low through 1.4V
to BO or B1 turning off through 50%.
-
75
-
ns
td14
Delay from WD going low through 1.4V
to AO or A1 turning off through 50%.
-
75
-
ns
td15
Delay from WD going low through 1.4V
to BO or B1 turning on through 50%.
-
75
-
ns
t16
Turn-on time, 10% to 90%, of AO or A1
-
ns
Turn-on time, 10% to 90%, of BO or B1
50
-
ns
t18
Turn-off time, 90% to 10%, of AO or A1
50
-
ns
t19
Turn-off time, 90% to 10%, of BO or B1
-
50
t17
50
-
ns
1-116
HS signal at Pin 9: f = 50 KHz,
50% duty cycle, amplitude
= O.4V to 2.4V
See Figure 1
See Figure 1
See Figure 3
XR·2247/2247 A
PRINCIPLES OF OPERATION
Erase 0 - EO (Pin 10), Erase 1 - El (Pin 12): These pins
provide high-current open-collector outputs for supplying erase current to the head. With R/W low, the erase
output selected by HS will be low with the other open.
With R/W high, both EO and E1 will be open or high Impedance outputs.
The functions of the input and output pins are as follows:
Head Select - HS (Pin 9): The head select input makes a
selection between head 0 and head 1. It channels the
proper drive signals to the CT and E pins.
AD (Pin 16), 80 (Pin 15): These pins provide the write current to the head. AO is connected to one side of the
head, with BO connected to the other. They provide outof-phase drive to each end of the head write coil. These
outputs are selected when HS is low.
Read/Write - R/W (Pin 5): This input selects read data
when high, and write data when low_
Write Data - WO (Pin 21): Digital data to be written to the
head is fed into this pin_ Data is alternately written to
AO, BO or A1, B1 on negative transitions of WD_
Al (Pin 20),81 (Pin 19): These outputs provide the same
current-sink drive as AO/BO, except to the other head
when HS is high.
IRW Select - IRWS (Pin 14): This pin is used to provide a
digital control for the amount of current written to the
head_ It is used to provide inner track compensation_
When low, the head current is that dictated, by RrefWhen driven high, the head current is increased by
RA (Pin 18), R8 (Pin 17): These are read Signal outputs.!2.
be connected to the read amplifier inputs. With R/W
high, the head selected by HS will be connected to
these pins.
40%_
Inhibit - INH (Pin 3): When active (low), this input will turn
off both erase and center taps to avoid erroneous outputs during power-on.
Vrel (Pin 4), Irel (Pin 13): A resistor, Rref, connected between these pins control the write current. With IRWS
low, the write current is approximately five times the
Rref current, and seven times with IRWS high.
TO ON (Pin 6), TO OFF (Pin 7): The resistor, RD, and capacitor, CD, combination of these pins will set the turnon and turn-off times of the erase outputs. Figure 5
shows the connection of these components, with section 3 of the applications information describing the
time as a function of RD and CD.
Center Tap 0 - CTO (Pin 2), Center Tap 1 - CTl (Pin 22):
These pins are high-current outputs used to apply VCC
to the center taps of the head. With R/W low, both CT
outputs are in the high state.
EQUIVALENT
SCHEMATIC
DIAGRAM
1-117
XR·2247/2247 A
2.0V
HS
191 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _J
RNi
O.8V
2.DV
lSI
JO ON
TO ON
TOOFF
TOOFF
~-------Ir
9.0V
ED
1101
El
112)
9.0V
1.0V
eTD
12)
'd'
eT1
1221
Wi)
121)
AD
116)
ID
115)
Al
I--to,
'd2
120)
91
1191
V,e'3F to.
141
Figure 1. Timing Diagram
CT1
OUTPUT
EO
H
H
H
L
L"
Low
Open
Open
Open
Open
INPUT
INH
1
1
1
1
0
R/W
HS
0
0
0
1
1
0
-
1
1
-
CTO
H
H
L
H
L"
"High impedance
Figura 2. Truth Tabla
1-118
E1
Vref
Open
Low
Open
Open
Open
H
H
L
L
H
XR·2247/2247 A
24V
WI)
(211
1.4V
----
Q.4V - -
=J"f
10%
/10, A1
116.20)
50%
-:-~
00%
1ax.
00, B1
(15,19)
50%
00%
Figure 3. WrHe Current Output Characteristics
Vee
r
L
H1J.lF
9.4KU
[
4.7KU •
AtW
4
5
18
L
6
17
-'L
7
16 11.
r
8
15
9
14
10
13
11
12 J
I
.~
XA·2247
3
I
HS
21. t1
r
L
12KU
2
[
L
r-
22
20 t1
fI
19 11.
fI
r
0.1J.lF TO.1J.lF
~
~
fI
':"
10KU
Figure 4. Test Circuit lor AC Switching Characteristics
1-119
~
1
,
WD
1im
1Kn
...1Kn
1Kn
J
J
lAWS
]--
,
12KU
XR·2247/2247 A
APPLICATIONS INFORMATION
Control of the erase outputs can also be done from
an external source by grounding Pin 6 and driving
Pin 7 directly. The selected erase output will be on
when Pin 7 is low and off when Pin 7 is high. This input is not TIL compatible, however, with the threshold voltage being approximately 2f3 Vee.
A typical dual head connection of the XR-2247 in a floppy disk system is shown In Figure 5. Referring to Figure
5 and the electrical characteristics, the external components are calculated as follows:
1) Write Current, IWR
IWR = (5.3) (Vref - Vmir)
Rref
4) Resistors RWO are used to damp any ringing that
may occur when the write current transitions are applied to the head. Their value is determined by the
head characteristics and the desired damping.
IRWS = Low
Given IWR = 4.1 mA, Rref = 10 kO
Iref' the current into Pin 13, should not exceed 2.0
mA.
RRO is used to provide additional damping in the
read mode if this is desired. Usually, RRO is only
used with the XR-2247A where the head switching
diodes make the total read damping resistance approximately RROIIRWO. In the XR·2247, the transistors used for head switching act to buffer RRO from
the head.
2) Erase Current, IE
Vee - 2V
RE
Resistors RS are used to bias the head switching
network in the read mode and their value is selected
to provide currents in the 100 ",A to 300 ",A range.
Given IE = 50 mA and Vee = 12V, RE = 2000 Y2 W
3) Erase Delay Time, TO ON and TO OFF
5) When in the read mode, digital signals appearing
along the WO line (Pin 21) can couple externally
through stray capacitances into the read si~
coming from the head. It is recommended that WO
be held low while reading.
TO ON '" 1.1 (R01 x C01)
TO OFF'" 1.05 (R02 x C02)
Given TO ON = 0.5 ms and TO OFF = 1.0 ms,
R01
C01
= 4.55 kO, R02 = 9.54 kO
= C02 = 0.1 ",F
Vee
DIGIT AL
READ DATA
I lOUT)
READ AMP
See Data Sheet
Figure 5. Typical Dual Head Floppy Disk System
1-120
XR·3470A/3470B
Floppy Disk Read Amplifier
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-3470N3470B is read amplifier system designed
primarily for use in a floppy disk drive system. It is designed to perform the complete read back function, by
accepting the readback signal from a magnetic head
and converting it into digital output pulses. To perform
this function, the circuit contains a high-frequency amplifier, an active differentiator, a zero-crossing detector,
and a time domain filter.
r
AMPLIFIER
INPUTS
L
]PLIFIER
OUTPUTS
J
OFFJ:
OECQUPLING
L
The XR-3470N3470B is suited for systems with data
transfer rates up to 3 megabaud. High input sensitivity
allows operation with Signal levels as low as 1.4 mV pp,
which gives it the flexibility to be used for single or double density floppy disk systems_
"JTIVE
DIFFERENTIATOR
INPUTS
GROUND
..J
r
.l.lONE-SHOT
JFERENTIATOA
COMPONENTS
COMPONENTS
L
r
The XR-3470N3470B offers improvements (over the
standard 3470) of lower peak shift and power part-topart input amplifier gain variations.
J
Vee,
DIGITIZER
ONE-SHOT
COMPONENt:.
DATA
OUTPUT
The XR-3470N3470B, available in an 18 Pin DIP, is
powered by + 5 and + 12 volt power supplies.
ORDERING INFORMATION
FEATURES
Complete Floppy Disk Read Amplifier
Low Input Voltage detection
Low Peak Shift 3470A
3470B
Low Amplifier Gain Variation
High Amplifier Frequency Response
1.4 mV pp
2% Max
4% Max
100 VIV Min
130 VIV Max
10 MHz, Min.
Part Number
Package
Operating Temperature
XR-3470ACN
XR-3470ACP
XR-3470BCN
XR-3470BCP
Ceramic
Plastic
Ceramic
Plastic
O°C to + 70°C
ooe to + 70 0e
oDe to + 70 0e
oDe to + 70 0e
SYSTEM DESCRIPTION
APPLICATIONS
The XR-3470N3470B contains four internal signal
blocks. Their functions are as follows: Input Amplifier This section receives an input directly from the magnetic head. It provides a nominal gain of 110 VIV, with
gain select pins to reduce gain or tailor it for ac response. The amplifier has differential inputs and outputs_ Active Diiferentiator - This circuit differentiates the
signal from the amplifier which causes a zero-crossing
for each peak of the readback signal. The time constant
and response of this section is externally set. ZeroCrossing Detector - This function is performed by a voltage comparator. It produces complementary outputs
for the internal digital section. Digital Section - This section consists of 2 one-shots and other control circuitry.
The one-shots are used to prevent false outputs, and
set the output pulse width.
Single/Double Density Floppy Disk Read Amplifier
Magnetic Read Amplifier
ABSDLUTE MAXIMUM RATINGS
Power Supply Voltage (Pin 11)
Power Supply Voltage (Pin 18)
Input Voltage (Pins 1 and 2)
Output Voltage (Pin 10)
Operating Ambient Temperature
Storage Temperature
Operating Junction Temperature
7 V dc
16 V dc
-2V to +7 V dc
-2V to + 7 V dc
O°C to + 70°C
- 65°C to + 150°C
150°C
1-121
XR·3470Al34708
ELECTRICAL CHARACTERISTICS
Tesl CondHions: TA = O°C to 70°C; VCC1 = 4.75V to 5.25V; VCC2 = 10V to 14V; unless otherwise specified.
SYMBOL
PARAMETERS
MIN
TYP
MAX
UNIT
CONDITIONS
100
110
-10
130
-25
1.5
VN
V
5% max THD
25
mVpp
5% max THD
-
V pp
mA
mA
kO
GAIN AMPLIFIER SECTION
AVD
liB
VICM
VID
VOD
10
lOS
RI
RO
BW
Differential Voltage Gain
Input Bias Current
Input Common Mode Range
Linear Operation
Differential Input Voltage Linear
Operation
Output Voltage Swing Differential
Output Source Current, Toggled
Output Sink Current
Small Signal Input Resistance
Small Signal Output Resistance
Single-Ended
Bandwidth, -3 dB
-
-0.1
3.0
2.8
100
-
10.0
-
4.0
8.0
4
250
15
-
CMRR
Common Mode Rejection Ratio
50
PSSRI
VCCI Supply Rejection Ratio
50
PSSR2
VCC2 Supply Rejection Ratio
60
VDO
VCO
Dilferentlal Output Offset
Common Mode Output Offset
-
3.0
Differential Noise Voltage
Referred to Input
-
15
1.4
en
-
0.4
-
I
= 200 kHz, VID = 5 mV (RMS)
p.A
0
MHz
dB
dB
dB
V
V
p.V
(RMS)
Pins 16 and 17
TA
25°C
TA
25°C, VCCI
5V
VCC2
12V
TA
25°C, VCCI
5V
VID
2 mV (RMS), VCC2
12V
TA
25°C, I
100 kHz
AVD
40 dB, VCCI
5V
VIN
200 mV pp, VCC2
t2V
TA
25°C, AVD
40 dB
4.75 < VCCI < 5.25, VCC2
12V
TA
25°C, AVD
40 dB
10 < VCC2 < 14V, VCCI
5V
TA
25°C, VID
VIN
OV
VIN
OV
VID
Differential and Common Mode
BW
10 Hz to 1.0 MHz
TA
25°C
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
= =
=
=
=
=
ACTIVE DIFFERENTIATOR SECTION
10D
PS
Differentiator Output Sink Current
Peak Shift 3470A
3470B
1.0
RID
Differentiator Input Resistance
Differential
Differentiator Output Resistance
Differential
-
30
-
40
2.7
-
ROD
-
-
2.0
4.0
-
mA
%
%
kO
0
=
Pins 12 and 13, VOD
VCCI
f
250 kHz, VID
tV pp
ICAP
500 p.A
VCCI
5V, VCC2
12V
See Figure 2
TA
25°C
=
=
=
=
=
=
TA = 25°C
DIGITAL SECTION
VOH
VOL
tTLH
trHL
tlAB
Etl
t2
Et2
ICCI
ICC2
Output Voltage High Logic Level
Output Voltage Low Logic Level
Output Rise Time
Output Fall Time
Timing Range Mono #1
Timing Accuracy Mono #1
Timing Range Mono #2
Timing Accuracy Mono #2
VCC1, Power Supply Current
VCC2, Power Supply Current
-
500
85
150
85
-
-
25
3
. 1. Accuracy guaranteed for Rl and Cl In range
1.5kO (AyO EP}max
min
DIGITAL OUTPUT
(052)
where
Figure 7a-f. Waveforms Through the XR-347DAl347DB
The amplifier stage will typically amplify the read back
signal by a factor of 110. In order to eliminate any offset
between the amplifier stages, a capacitor, Cl, should
be inserted between Pins 3 and 4. If the input signal to
the amplifier is to be above 25 mY, clamping of the amplifier may occur. To reduce the gain, a resistor Rx may
be inserted in series with Cl between Pins 3 and 4. The
graph in Figure 8 shows a plot of normalized gain vs Rx.
ACTIVE DlFFERENTIATOR
The amplified filtered read back signal is fed into the active differentiator. Here, the peaks of the read back signal are transformed into zero crossings as shown by
Figures 7a and 7b.
It should be noted that capacitor Cl with Rx and the resistance looking into Pins 3 and 4, will create a pole at
approximately
+
AyO is the gain of the amplifier
Ep is the maximum peak voltage of the
input signal
The differentiator inputs are dc biased internally. This
implies that the dc level from the amplifier stage must
be blocked in order riot to disturb these levels. Therefore blocking capacitors, Cbl and Cb2, should be
placed before the differentiator inputs. In order to keep
the transient response to a minimum it Is best to place
the dc blocking capacitors before the filter network.
AMPLIFIER STAGE
Wp = (Rx
2.8 mA
In order to perform the differentiator function a capacitor Co is needed across Pins 12 and 13. The selection
of CD for accurate zero crossing is optimized by maximizing current slew rate through CD, which occurs
when
250) Cl
NORMALIZED
GAIN
Co=
1.000.80
Where
0.60
0.40
0.20
'--+-++-+-1-+--+-+-+--11--100 200 300
400 500
600
700
aoo
R.I!!)
lmA
(AyO Epw}max AF
AyO is the gain of the amplifier
Ep is the maximum expected input voltage
w is the maximum operating frequency in
radians/sec of the system
AF is the gain of the filter network
900 1000
If CD is greater than the maximum value calculated
above, peak shifting will occur.
Figure 8. Normalized Gain vs Rx for Amplifier SIage
1-125
XR·3470Al3470B
As can be seen from Figure 9; the capacitor Co and the
effective output resistance, RO of transistors 01 and
02 produce a pole given by
lell)
1
wp = 2ROCO
Co AVO Epw
where RO is typically 400.
Figure 10. Differentiator Response for Co and R
~~nlt~I--------~----------+----------'
In order to reduce the noise bandwidth further a second
pole can be introduced at 10 wmax by placing an inductor in series with Co and RO, where LO is given by
LO
Figure 9. Simplified Active Olfferentiator Section
=
1
100{wmax)2 Co
The damping ratio, 0, should be between .3 and 1 where
+ 0. 5R O) Co
'--..::--:2'..j;=LO=C'""O==-=-
{, = (RO
In order to obtain a phase shift approaching 90° for perfect differentiation wp would have to approach 00 since
6 = tan - 1 (wp/wo)
Wo
= operating frequency
ic(l)
It must be considered, however, that making wp as high
as possible also produces a noise bandwidth as high as
possible.
In order to come to a reasonable compromise wp
should be selected to be ten times the maximum ex·
pected operating frequency.
wp = 10 wmax
where wmax is the maximum operating frequency of
the system in radians/sec.
wVinld
Doing this produces a phase shift of approximately 84°,
while limiting the noise bandwidth. The design criteria
is now given by
Figure 11. Differentiator Response with RO, CD, and L
1
Wmax = 20ROCO
It may be that RO is too low, creating a pole at a higher
frequency than 10 wmax. If this is so one can insert a
resistor RO in series with CO, giving the equation
PEAK SHIFT CONSIDERATIONS
The arrangement shown in Figure 12 will eliminate the
current imbalance in the differentiator, and offset in the
comparator, thus minimizing the peak shift at the digital
output. The potentiometer is adjusted with a minimum
sinusoidal Epw at the input, for symmetrical digital
waveform at the digital output, Pin 10.
1
wmax = 20RCO
where R = RO
+
0.5RO
1-126
XR·3470Al3470B
ZERO CROSSING DETECTOR
MONOSTABLE #2 (OS2)
The differentiated output signals from the active differentiator are run into a comparator. Since the outputs of
the active differentiator are 180 0 out of phase, the comparator will produce an output pulse whenever the differentiated signal crosses zero. This is shown in Figures 7b and 7c.
This one shot is used to adjust the pulse width of the
digital output pulses at Pin 10. The adjustment of this
one shot is done via external components R2 and C2
where
MONOSTABLE #1 (OS1)
The pulse width of the output pulse is given by
1.5 K
150 pF
This one shot is used to prevent false digital outputs
due to noise at zero crossings as shown at time tA, in
Figure 7a. The adjustment of the one shot is done via
external components Rl and Cl where
< R2 < 10 K
< C2 < 680 pF
to = R2C2 (0.625)
This one shot is triggered on the rising and falling edges
of the time domain filter output, as shown on Figures 7e
and 7f, giving the corresponding digital pulses for the
peaks of the read back Signal, shifted by OSI 's time, t,
as can be seen from Figures 7a, 7d, and 7f.
1.5 K < Rl < 10 K
0.150 pF < Cl < 680 pF
and t = R1Cl (0.625) + 0.2,..sec
Pin 10 OUTPUT
The value of t is determined by the maximum period of
expected distortion, aT, and the maximum operating
frequency
where
aT
PS = 'h (IPS)
-IPS2)
IPSI + IPS2
< t < _1_ _ aT
4fmax
2
Co
AD
LO
20KT050K
The one shot is triggered on the rising and falling edge
of the comparator output as can be seen in Figures 7c
and 7d. The time domain filter will change state on the
rising edge of OSI 's output if and only if the pulse width
of the comparator output is grl3ater than the time of
OSI 's pulse, t. This is shown in Figures 7c, 7d, and 7e.
10K
Figure 12. Nulling Network to Minimize Peak Shill IPS)
1-127
Timing Circuits
Fundamentals of
Ie Timers
ONE-SHOT OR SINGLE-CYCLE TIMERS
Monolithic timing circuits or timers find a wide variety
of applications in both linear and digital signal processing. In a large number of industrial control or test sequencing applications, these circuits provide direct and
economical replacement for mechanical or electromechanical timing devices.
One-shot or single-cycle timers operate by charging a
timing capacitor through an external resistor or a current source. The simplest form of the one-shot type timer is the "exponential-ramp generator" circuit shown in
Figure 1. Normally all the components except the Rand
the C shown in the Figure are internal to the IC, and the
switch 81 is a grounded-emitter NPN transistor included in the IC chip.
Monolithic timers generate precise timing pulses, or
time delays whose length or repetition rate is determined by an external timing resistor, R, and a timing capacitor, C. The timing interval is proportional to the external (RC) product, and can be varied from microseconds to minutes, days or months, by the choice of
the external Rand C. Integrated circuit timers can be
classified into two categories, based on their principle
of operation:
The operation of the circuit can be briefly explained
as follows: In the rest, or reset condition, the switch 81
is closed; and the voltage across the capacitor is
clamped to ground. The timing cycle is initiated by
applying an external trigger pulse to "set" the flip-flop
and to open the switch 81 across the timing capacitor.
The voltage across the capacitor rises exponentially toward the supply voltage, VCC, with a time-constant of
RC. When this voltage level reaches an internally set
threshold voltage, VREf; the voltage comparator
changes state, resets the flip-flops, closes the switch
81, and end the !Lming cycle. The output is taken from
either the Q or Q terminal of the flip-flop and corresponds to a timing pulse of duration T, where:
1. One-Shot or Single-Cycle Timers: These timer IC's operate by charging an external capacitor with a current
set by an external resistor. Upon triggering, the
charging cycle happens only once during the timing
interval. The total timing interval, T, is the time duration necessary for the voltage across the capacitor
to reach a threshold value.
2. Multiple-Cycle or Timer/Counters: These timer circuits
charge and discharge the external timing capacitor,
not once, but a multiple number of times during the
timing interval. The number of times the capacitor is
charged and discharged is set by means of a pre-set
count, N, stored in a binary counter included on the
chip. Thus, the resulting time interval is proportional
to N times the external (RC) product.
vee]
T = RC In [
(1)
VCC - VREF
Normally, the internal threshold voltage, VREf; is generated from the supply voltage by means of a resistor divider as shown in Figure 1. Then, VREF is equal to a
fraction of the supply voltage:
Both the one-shot and the timer/counter type IC's can
be operated in either their monostable or free-running
(I.e., self-triggering) mode. They can also be used for
sequential timing, clock generation, as well as for
pulse-position or pUlse-width modulation, as outlined in
Table I.
VREF = Vee
[~]
Rl + R2
(2)
and the basic timing equation becomes independent of
the supply voltage:
Precision Timing
T = RC In [1
+
:~]
(3)
Time-Delay Generation
Sequential Timing
--------,
Pulse Generation/Shaping
Pulse-Position Modulation
1 RI
Pulse-Width Modulation
I
I
Missing-Pulse Detection
Jl
Sweep Generation
Pulse Counting
1-' -I
Clock Generation
Table 1. Typical Applications of Monolithic Timers
c
I
~
I
lSI_____ .J
J ":
I
ML"'··'"
Figure 1. Exponential-Ramp Type Timing Circuit
1-128
Since the resistors R1 and R2 are inside the IC, their
ratio is set by the design of the IC, and is normally accurate to within ± 1 %. Thus, virtually all the accuracy
of the timing interval is determined by the external R
and C.
(PWM), or pUlse-position modulated (PPM) signals, or
allows the timer circuit to be used as a voltagecontrolled oscillator.
An alternate approach to the design of one-shot timers
is the "linear-ramp generator" circuit, shown in Figure
2. This circuit operates on a principle similar to that of
the basic exponential timer, except the timing capacitor
C is now charged linearly with a constant current, I, and
generates a linear-ramp waveform with a constant
slope of (I/C). The constant-current is in turn controlled
by an external control voltage, VC, applied to the current source. The total timing interval, T, is the time riecessary for the voltage across C to rise from ground to
VREF, at a constant slope of (I/C), or:
The accurate timing intervals which can be obtained
from commercially available one-shot type timer IC's
are limited to the range of several micro-seconds to
several minutes. For generating very short timing
pulses (in the few micro-second range) the internal time
delays associated with the switching speeds of the
comparator, the flip-flop and the discharge transistor
(I.e., the switch S1) may contribute additional timing er-'
rors. Similarly, for long time delays (in the several minute range) which require large values of Rand C, the input bias current of the comparator, and the leakage currents associated with the timing capacitor, or the
internal discharge transistor, may limit the timing accuracy of the circuit.
T = (VREF)(CII)
PRACTICAL LIMITATIONS OF ONE·SHOT TIMERS
(4)
Normally, VREF and Vc (and consequently I) would be
derived from VCC by means of resistor-dividers; therefore, they would be both proportional to VCC. Thus, the
effects of supply voltage variations cancel, and the basic timing equation for the linear-ramp type timer circuit
of Figure 2 becomes
In general, for timing applications requiring time delays
in excess of several minutes, the multiple-cycle or
timerlcounter type timer circuits provide a more economical and practical solution than the one-shot type
ICtimers.
T = aRC
Vee
where a is a constant of proportionality set by the internal resistor-dividers within the IC, and Rand C are the
external timing components.
The exponential-ramp type timing circuit of Figure 1 is
inherently simpler and more accurate than the linearramp type circuit. However, the latter has the advantage of providing a linear voltage across the capacitor
which is proportional to the elapsed-time during the timing cycle and can be used as a "linear sweep" or timebase signal for oscilloscope or X-V recorder displays.
I
Normally, the internal threshold reference, VREf; of
one-shot IC's is available as a package terminal and
can be modulated by an external input signal. This permits the user to modulate or vary the timing interval by
means of an external control signal. This feature can also be used for generating pulse-width modulated
JL",Co--CE.- - - '
JLESEo_T------'
To' NT
Figure 3. Simplified Block Diagram 01 a Timer/Counter
TIMER/COUNTER CIRCUITS
The timerlcounter, or multiple-cycle timing circuits use
the combination of a time-base oscillator and a binary
counter to generate the desired time delay. Figure 3
shows a simplified block diagram of a timerlcounter IC,
which is made up of three basic blocks: (1) a time-base
oscillator; (2) a binary counter; and (3) a control flip-flop.
With reference to the simplified block diagram of Figure
3, the principle of operation of a timerlcounter can be
explained as follows: when the circuit is at rest, or reset
condition, the time-base oscillator is disabled, and the
counter is reset to zero. Once the circuit is triggered,
the time-base oscillator is activated and produces a
series of timing pulses whose repetition rate is proportional to external timing resistor R, and the capacitor
Figure 2. Block Diagram of a Linear-Ramp Type Timer Clrcuil
1-129
C. These timing pulses are then counted by the binary counter; and when a pre-programmed count Is
reached, the binary-counter resets the control flip-flops,
stops the time-base oscillator and ends the timing cycle. The total timing interval, TO, is then proportional
to N times the (RC) product, where N Is the preprogrammed count.
ed by the binary counter; and when a given count, N, is
reached, the control flip-flop is latched in its reset condition until the next trigger input to the circuit.
In most timer/counter deSigns, it is convenient to set
the ratio of resistors R1 and R2 such that:
(7)
r----,-------------,---<> Vee
"\
"L
where "e" Is the base of the natural logarithm. This
makes the period of the time-base oscillator directly
equal to 1.0 RC and simplifies the selection of external
R or C values for a given timer setting.
.... , ...
JLJL
T'Rt
UNIQUE FEATURES OF TIMER/COUNTERS
The combination of a stable time-base oscillator and a
programmable binary counter on the same IC chip offer
some unique application and performance features.
Some of these are outlined below:
Generating Long Delays with Small Capacitors: For a given
time delay setting, the timer/counter would require a
timing capacitor, C,that is N times smaller than that
needed for the "one-shot" type timer, where N is the
count programmed into the binary counter. Since largevalue, low-leakage capacitors are quite expensive, this
technique may provide substantial cost savings for generating long time delays in excess of several minutes.
Figure 4. Simplified Schematic of a Time-Base Oscillator
Circuit
Time-Base Oscillator: The time-base oscillator used in
most of the timer/counter IC's is derived from the simple exponential-ramp type timer circuit. Figure 4 shows
the simplified circuit diagram of such an oscillator. The
timing components, Rand C, are external to the chip.
The operation of such an oscillator can be described as
follows: when the circuit is at rest the flip-flop is latched
in its reset state, and the transistor Q1 is "off", the external capacitor C is fully charged to a voltage approximately equal to VCC. When the circuit is triggered, the
flip-flop is unlatched and set, which causes the discharge transistor Q1 to turn "on" and discharge Crapidly. When the voltage across C discharges to the voltage level VB, the comparator #2 changes state, resets
the flip-flop and turns Q1 "off". Then, C charges toward
VCC with a time constant set by the external Rand C.
When the voltage across it reaches the upper threshold, VA, comparator #1 changes state and sets the flipflop again, and discharges C back to the lower threshold level. VB. In this manner, the circuit continues to oscillate, with the voltage level across C exponentially
rising to VA, then rapidly decaying to VB, and then repeating its cycle. The output of the circuit is a sequence of narrow pulses, with a repetition rate T, given
as:
T = RC1n [1
+
:~]
Generating Ultra-Long Delays by Cascading: When a cascading two timer/counters, one cascades the counter stages of both timers. Since the second timer/counter further divides down the counter output of the first timer,
the total available count is increased geometrically,
rather than arithmetically. For example, "if one timer/
counter gives a time delay of NRC, two such timer/
counters cascaded will produce a time delay of N2 RC
where N is the count setting of the binary counter. Thus,
a cascade of two timer/counter IC's, each with an a-bit
binary counter, can produce a time delay in excess of
32,000 RC.
Generating Multiple Delays From Same RC Selting: By using a
programmable binary counter, whose total count can
be programmed between a minimum count of 1, toa
maximum count of N, one can obtain N different time
intervals from the same external RC setting.
Easy to Set or Calibrate: Although timer/counters are normally used for generating long time delays or intervals,
their accuracy characteristics are only determined by
the characteristics of the time-base oscillator. The
counter section does not affect the over-all timing accuracy. Thus, time setting or calibration for long interval
timing can be done quickly, without waiting for the entire timing cycle, by setting the accuracy of the timebase oscillator.
(6)
where R1 and R2 are the internal bias resistors setting
up the threshold levels VA and VB. The train of output
pulses coming out of the time-base oscillator are count-
1-130
Choosing the Right IC Timer
Because of its versatility, the monolithic IC timer offers
a very wide range of applications in circuit or system
design. However, during the design phase, once the
"paper design" is accomplished, the user is faced with
the key question: which IC timer is the best choice for a
given application? If the performance characteristics
and the limitations of the timer IC is not carefully considered, the total system performance may be degraded; similarly, if the timing function is overspecified with
an excessive amount of "overkill", particularly with regards to its stability and accuracy requirements, then
the system cost will increase unnecessarily.
Sequential Timing: Many timing applications require sequencing of timing functions, i.e., one timer completes
its operation and initiates the next timer, and so on.
Since these applications require a multiplicity of timer
circuits, they are best served by dual-timer IC's, such
as the XR-556 or the XR-2556.
Delayed Timing: Certain timing applications require that
the start of the timing pulse be delayed by a specific
time from the occurrence of the trigger. This can be
easily accomplished by using a dual-timer, such as the
XR-556, where one section of the dual-timer can be
used to set the initial "delay" subsequent to the trigger;
and the second section can be used to generate the actual timing pulse.
The key selection criteria in choosing the right timer for
the job is finding the monolithic IC which will result in
the lowest system cost (including the external components) for a given performance requirement.
Event Counting: In such an application, one needs to
keep an accurate count of "events" which are normally
a series of incoming pulses. This function can be easily
performed with a programmable timerlcounter IC, such
as the XR-2240, where the binary counter section can
be programmed to count a given number of input
pulses and stop the count, andlor reset the circuit when
the programmed count is reached. In the case of the
XR-2240, the existing count in the counters is displayed
in a 8-bit parallel binary-format.
A very large majority of applications for IC timers can
be classified into one of the four categories listed below:
o Interval or Event Timing
o Pulse Generation and Shaping
o Oscillation or Clock-Generation
o Ramp Generation
These categories of applications are discussed in more
detail in the following sections, with the particular emphasis on "choosing the right IC timer" for the particular application.
Digitally-Programmed Timing: Some timing applications
may require that the timing interval be digitally programmable, without switching additional precision resistors and capacitors into the circuit. Such a function
can be easily achieved by using a programmable timerl
counter, such as the XR-2240, where output duration
can be programmed from 1.0 RC to 255 RC, in 1 RC increments, where Rand C are the external timing components.
INTERVAL OR EVENT TIMING
In such an application one uses the IC timer either to
control the time interval between events, or the duration of an event. A typical example of such application
would be to control the opening or closing of an electromechanical relay or sequencing of indicator lights.
PULSE GENERATION AND SHAPING
General Purpose Timing: Most timing applications fall within the time interval range of a few microseconds to several minutes. For such applications the basic one-shot
timer, such as the XR-555, is often the best choice,
based on its low cost and versatility.
A popular class of applications for the one-shot type
timers is pulse shaping or stretching. Some specific examples of such applications and the recommended
types of IC timers for each are given below.
Pulse Stretching: In such an application the IC timer is
operated in its monostable mode and is triggered by an
input series of pulses, whose repetition period is longer
than that timing period of the IC. The output from the
timer will then have the same repetition rate as the input pulse train, except that each output pulse will now
have a uniform duration or length, as set by the RC time
constant of the timer. The two IC's best suited to this
application are the XR-555 and the XR-320. The XR-555
has the advantage of low unit price, whereas the
XR-320 has the advantage of being able to trigger on
either positive- or negative-going edge of the input
pulses.
Low-Power Timing: Many timing applications involving
battery-operated or portable equipment, require a lowpower. timer which can perform the general purpose
timing functions with a minimum amount of power dissipation. The XR-L555 Micropower Timer IC, which operates with less than 1 mW of power dissipation and with
supply voltages as low as 2.7 volts, is especially designed for such applications.
long Interval Timing: For timing applications requiring interval timing in the minutes, hours, or days range, the
timerlcounter IC's present the most economical approach, since they can produce long time delays using
a small value capacitor. For such an application of the
low-cost XR-2242 Long Range Timer, which operates
on the timerlcounter principle, is the most costeffective circuit.
Delayed-Pulse Generation: In this application it is necessary to convert the input pulse train to a different pulse
sequence which has the same repetition rate but a different duration and a different phase. This function can
1-131
be accomplished with a dual·timer circuit, such as the
XR·556 or the XR·2556, where the first timer which is
triggered by the input signal, sets the phase difference
or "delay" between the input and the output pulse se·
quence; and the second timer which is triggered at the
trailing·edge of the first one, sets the output pulse·
width.
Micropower Oscillator: Battery operated or remote-controlled instruments often require a low-power clock oscillator. The XR-L555 Micrbpower Timer, which operates
with less than 1 mW of power drain, is the recom·
mended choice for such applications, since it dissipates 1/15th the power of the conventional 555-type
timer.
Pulse Blanking: In this application it is necessary to selectively "interrupt" or "blank-out" a pulse train. Such
an application can be performed using a dual-timer IC,
such as the XR-556, where one section of the timer can
be operated as a "pulse-stretcher" triggered by the input pulse train; and the second timer section can be
triggered by a separate timing signal and serve as an
enable/disable control for the first timer, thus interrupting or "blanking" its output during its timing interval.
Voltage-Controlled Oscillator: Voltage-controlled oscillator
(VCO) circuits find a wide range of applications in
phase-locked loop systems. The XR·555 (or its low·
powerllow-voltage version of the XR·L555) which has a
separate modulation terminal (Pin 5) can be used as a
VCO by applying the proper control voltage to its modulation terminal and operating the IC in its self-triggering
mode.
Low-Voltage Oscillator: Low threshold CMOS logic circuits
normally require stable clock oscillators which can operate with a single 3 volt supply. The XR-L555 Micropower Timer which can operate with supply voltages as
low as 2.7 volts is particularly suited for such applications.
Pulse-Width Modulation: In certain timing applications it is
necessary to modulate the pulse·width of an output
pulse sequence, without affecting its repetition rate.
Such a requirement can be met by a one-shot timer,
such a::; the XR-555, operating in its monostable mode
and being triggered by a fixed-frequency input pulsetrain. The width of the output pulses from the timer IC
can be modified without affecting the repetition rate, by
simply applying a control·voltage to the modulation ter·
minal of XR·555.
Ultra-Low Frequency Oscillator: Certain battery operated or
remote-controlled equipment require a stable ultra-low
frequency clock oscillator, whose frequency can be as
low as one cycle per day. The XR-2242 Long·Range
Timer circuit which produces a square-wave output
with a period of 256 RC, when operating in its freerunning mode, is a very cost-effective replacement for
such an oscillator.
Pulse-Position Modulation: This application requires the
generation of a pulse sequence whose pulse-width is
constant (and usually very narrow) and, whose repetition rate is modulated. Such a function can be easily
implemented using a dual-timer IC, such as the XR-556,
where the second timer generates the narrow output
pulses when triggered by the output of the first timer.
The first timer section is then operated in its freerunning (I.e., astable) mode and its frequency is then
externally modulated by applying a control-voltage to its
modulation terminal.
Digitally-Programmed Oscillator: In certain applications it
may be necessary to program the frequency of an os·
cillator by means of a binary control signal, without
switching additional resistors or capacitors .into the circuit. The XR-2240 Programmable Timer/Counter, when
operating in its delayed-trigger mode (see Exar Application Note AN-07) can be used in such an application to
generate an output frequency whose period is equal to
(N + 1)RC, where N is the binary count which can be
digitally programmed by an external a·bit binary Signal,
to be any in.teger between 1 and 255.
OSCILLATION OR CLOCK-GENERATION
IC Timers can be operated in their free-running or "selftriggering" mode, to generate periodic timing pulses.
Since the output pulse·width or the frequency can be
controlled by the choice of external resistors and ca·
pacitors. These circuits make excellent low-cost clock
oscillators, for a number of digital systems. Some of
these applications are outlined below.
Binary Pattern Generator: In certain test instrumentation
deSign, it is necessary to generate a pseudorandom binary data pattern, which would then repeat itself periodically. The XR-2240 Programmable Timer/Counter
which provides eight separate "open-collector" outputs, can perform such a function by selective shorting
of one or more of its outputs to a common pull-up resistor_
Clock Generator: In such applications; the IC is used to
generate a fixed-frequency output waveform with nearly
50% duty cycle. The XR-555 timer, whose output dutycycle can be controlled by the choice of two external
resistors, is ideally suited for such an application, for
clock frequencies up to 300 kHz.
Tone-Burst Generator: Some instrumentation applications
require the generation of a certain tone or frequency
signal, at periodic intervals. This function can be accomplished using a dual-timer IC, such as the XR·556
or the XR-2556, where one of the timer sections would
operate as a keyed oscillator which is turned "on" and
"off" by the other timer section. The output of the first
timer section will then be a "tone-burst", which will be
present only during the timing cycle of the second timer.
High-Current Oscillator: Certain oscillator applications require that the circuit output should be able to source or
sink high load currents (2! 100 mAl in order to drive
electromechanical relays or capacitive loads. The
XR-555 Timer IC, which can provide up to 200 mA of
current drive, is well suited for such applications.
1-132
RAMP GENERATION
from the ground level and rises up to a voltage level approximately equal to 80% of the supply voltage, during
the timing interval. Since the current·source output at
Pin 3 is a high impedance terminal, the sweep or linear
ramp signal at this point should be buffered by a high
impedance op amp connected as a voltage follower.
amp connected as a voltage follower.
In a number of timing applications, it is necessary to
generate an analog voltage which is proportional to the
time elapsed during the timing cycle. This function is
particularly useful for generating linear sweep voltage
for oscilloscope or X-V recorder display applications
and it can be accomplished either linear/y or digitaJly,
as described below.
Digital Ramp Generator: In certain applications, a digitally
generated "staircase" voltage is preferred over a linear
ramp signal. Such a digital ramp signal can be generated using the XR-2240 Programmable Timer/Counter,
along with an external resistor ladder and a currentsumming op amp. The digital ramp signal is particularly
useful for analog-to-digital conversion or digital sampleand-hOld applications.
tions.
Linear Ramp Generator: A linear ramp can be obtained by
charging a timing capacitor with a constant·current
source. Since the XR-320 Timer IC operates on such a
principle, it is ideally suited for this application. Upon
triggering, the XR-320 produces a positive-going ramp
at its current-source output (Pin 3). This ramp starts
1-133
XR·320
Monolithic Timing Circuit
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-320 monolithic timing circuit is designed for use
in instrumentation and digital communications equipment, and for a wide variety of industrial control and
special testing applications. In many cases, this circuit
provides a monolithic replacement for mechanical or
electromechanical timing devices.
CIJHRINl
s()un(:£
INPut
The XR-320 timing circuit generates precise timing
pulses (or time delays) whose repetition rate (or length)
is determined by an external timing resistor, R, and timing capacitor, C. The timing period is exactly equal to
2RC and can be continuously varied from 1 "sec to 1
hour. The circuits can be operated in a monostable or
free-running (self-triggering) mode. They can be used
for sequential timing and sweep generation, and also
for pulse-position and pulse-width modulation.
HIGH
5tnmCf
CURRENt
OUrpUT
SH 1
fNEGArlV(
LOGIC
(iOlN(j
IIUUmRI
Sill
IPOSllIVf.
ctOING
rRmUfHI
The XR-320 integrated circuit Is comprised of a stable
internal bias reference, a precision current source, a
voltage comparator, a flip-flop, a timing switch, and a
pair of output logic drivers. The high current output at
pin 12 can sink or source up to 100 milliamps of current.
OUTPUT
GROUND
RUfI
ORDERING INFORMATION
FEATURES
Wide Timing Range: 1 "sec to 1 hour
High Accuracy: 1 %
Excellent Temperature Stability: 100 ppm/'C
Wide Supply Voltage Range: 4.5V to 18V
Triggering with Positive or Negative-Going Pulses
Programmable
Resistor Programming: 3 decades
Capacitor Program: 9 decades
Logic Compatible Outputs
High Current Drive Capability: 100 mA
Part Number
Package
XR-320P
Plastic
Operating Temperature
O'C to +70'C
SYSTEM DESCRIPTION
The XR-320 is an extremely versatile monolithic timer
capable of delays ranging from 1 ",sec to 1 hour_ It
works with both positive and negative triggering, and
features both normally high and normally low outputs.
An on board current source, programmable by an external reSistor, changes the timing capacitor. This produces a true ramp function and allows accurate timing
intervals equal to 2 RC.
APPLICATIONS
Precision Timing
Time-Delay Generation
Sequential Timing
Pulse Generation/Shaping
Pulse-Position Modulation
Pulse-Width Modulation
Sweep Generation
Positive going triggering is applied to Pin 6; negative
triggering is applied to Pin 5. After a trigger pulse is applied, the open collector output (Pin 10) will go high and
the high current output (Pin 12) switches into the current sink mode. At timeout, the open collector pulls low,
and can sink 10 mA; the high current output goes high
and can source 100 mAo Utilizing the high current output requires a pull-up resistor from Pin 10 to + Vee.
The resistor must limit current to no more than 10 mA;
1 mA is sufficient. Timing is interrupted and the device
is reset when Pin 7 is grounded. Astable operation is attained by tying the negative going (falling) trigger (Pin 5)
to the timing capacitor (Pin 3). In this configuration, the
device will automatically ret rigger itself upon completion of the timing interval.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Internal Power DisSipation
Plastic Package:
Derate above TA = + 25'C
Storage Temperature Range
CIIR"f""
uutpu1
18 volts
750 mW
625 mW
5 mW/'C
-65'Cto +150'C
1-134
XR·320
ELECTRICAL CHARACTERISTICS
Test Conditions: Supply Voltage
=
12V ±5%, Test Circuit of Figure 2, TA
= 25°C, unless otherwise specified.
XR-32D
PARAMETERS
MIN
Supply Voltage
Quiescent Supply Current
V+ = 5V
V+ = 12V
V+ = lBV
4.5
MAX
UNITS
lB
Vdc
2.0
6.0
10.0
3.5
7.0
12.5
rnA
rnA
rnA
2.5
6.5
12.0
4.0
B.O
14.0
rnA
rnA
rnA
Timing Accuracy
V+ = 5V
V+ = 12V
V+ = lBV
1.0
1.0
1.0
5.0
5.0
5.0
%
%
%
Temperature Drift
100
Timing vs. Supply Voltage
0.1
Stand·by Voltage (Pin 3)
0.7
Timing Cycle Supply Current
V+ = 5V
V+ = 12V
V+ = lBV
Comparator Threshold
Voltage (Pin 3)
V+ = 5V
V+ = 12V
V+ = lBV
Current Source Input
Voltage (Pin 1)
V+ = 5V
V+ = 12V
V+ = lBV
Trigger Voltage
Set (Pin 5)
Set 2 (Pin 6)
Reset (Pin 7)
TYP
Output 1 (Pin 10) (Normally low)
"Low" Voltage
"High" Voltage
Rise Time
Fall Time
Output 2 (Pin 12) (Normally high)
"High" Voltage
"Low" Voltage
Rise Time
Fall Time
ppm/DC
0.5
%N
V
4.5
2.4
5.2
BA
6.0
V
V
V
9.0
4.15
9.75
16.15
10.6
V
V
V
0.5
1.0
104
0.7
Trigger Current
Set 1 (Pin 5)
Set 2 (Pin 6)
Reset (Pin 7)
1.5
1.5
V
V
V
10
60
30
p.A
p.A
0.1
5.0
140
50
V
V
nsec
nsec
IDA
1.5
100
40
V
V
nsec
nsec
4.0
CONDITIONS
See Figure 11
See Figure 12
/lA
Isource = 100 rnA
Isink = 100 rnA
DEFINITIONS
Timing Accuracy:
the timing error solely introduced by the XR·320, defined in per cent
Stand·by Voltage:
as:
measured timing
2 RC based on actual
100 X _-"p.=ul",se:....:.:le",ng",t",h_-_c;:,;o",m",p:.:o",ne::;n.:.:t",v.=al",ue;:,;s,-- %
2 RC based on actual component values
Timing vs Supply
Voltage:
the maximum timing drift over the power supply range of 5 to 18 volts
referenced to 12 volt operation, defined in per cent per volt as:
100 X
15
max. timing pulse length
min. timing pulse length
over 5 to 18 volt supply -over 5 to t8 volt supply %N
timing pulse length with 12 volt supply
1·135
the voltage between pin
3 and ground in reset
condition.
Comparator Threshold
Voltage (Pin 3):
Trigger Voltage:
the voltage at which the
internal comparator triggers the flip· flop and the
timing capacitor discharges.
the DC voltage level ap·
plied to each set or reo
set terminal
which
causes the output to
change state.
EQUIVALENT SCHEMATIC DIAGRAM
OPERATING INSTRUCTIONS
A· lOOK
Figures 2 and 3 show typical connections for the XR320. Only three external components are required for
basic operation: the resistor R and capacitor C which
determine the time delay (2RC); and an external load resistor, RL. The circuit provides two independent logic
outputs: a medium current output (up to 10 mAl at pin
10, and a high current output (up to 100 mAl at pin 12.
The output at pin 10 is of the "bare-collector" type
which requires an external pull-uf resistor, RL, connect·
ed between this terminal and V for proper circuit operation.
~-+--o OUTPUT ~
r-_-oOUTPUT 1
SET 2
AlSET
Figure 1. Tesl Circuit
R
With no trigger pulse applied, the output at pin 10 is in a
low state near ground potential; and the output at pin 12
is in a high slate, near V + . The circuit is triggered by
the application of a negative-going pulse to pin 5 or a
positive-going pulse to pin 6. At that instant, the outpul
levels change slate such that pin 10 becomes high and
pin 12 low. The .outputs will remain in this (switched)
state until the delay time, T = 2RC, expires, at which
time the outputs will return to their original state. In this
mode of operation, the trigger input can be activated repeatedly without further influencing the time cycle, i.e.,
once the circuit is triggered it becomes immune to subsequent triggering until the entire timing cycle is completed.
t-'--+--oOUTPUT 2
SET 1
F-_-oOUTPUl 1
I
v'
Figure 2. Monostable Operation, Negative Trigger
A
For reliable operation, the trigger pulse width must he
shorter than the output pulse width. Although many
units will function when this rule is not observed, proper
operation cannot be guaranteed.
r--I--oOUTPUT 2
r---O OUTPuT 1
Figure 4 shows the waveforms at various circuit locations for a negative·going trigger applied to pin 5. A similar set of waveforms is displayed in Figure 5 for a
positive-going pulse applied to pin 6. The timing cycle
can be reset at any time by simply grounding pin 7.
IV'
Figure 3. Monostabla Operation, Positive Trigger
1-136
XR·320
Iy high will go low. See Figure 11 for additional details.
When not used, pin 5 should be connected to V+ to
avoid false triggering.
~------l SET 1
INPUT (PIN 5)
VOLTAGE ACROSS
TIMING CAPACITOR
(PIN 3)
By grounding or applying a negative pulse to the reset
(Pin 7), the timing cycle is automatically interrupted and
the outputs return to their original state. When the reset
function is not in use, it is recommended that it be connected to V + to avoid any possibility of false resetting.
OUTPUT 1
(PIN 10)
SET 2 - POSITIVE TRIGGER (PIN 6)
Figure 4. Waveforms for Negative-Going Trigger
VOLTAGE ACROSS
TIMING CAPACITOR
(PIN3)
A positive·going pulse applied to pin 6 will cause the
outputs to change state. The normally low output at pin
10 will go high, and the normally high output at pin 12
will go low. See Figure 12 for additional details. When
not used, pin 6 should be grounded to avoid false triggering.
OUTPUT 1
(PIN 10)
ADDITIONAL APPLICATIONS
SET 2
L - - - - - - - I INPUT (PIN 6)
FREE-RUNNING MODE
Figure 5. Waveforms for Positive-Going Trigger
By shorting pins 3 and 5, the XR·320 will operate in a
"free-running" or self-triggering mode. In this mode of
operation, the circuit functions as a stable clock pulse
generator with a repetition rate of approximately 11
(2RC). The circuit connection and free-running frequency in this application are shown in Figure 7. Note that
one cycle is not precisely equal to 2RC because of capacitor discharge time. Typical waveforms for selftriggered operation are shown in Figure 8.
DESCRIPTION OF CIRCUIT CONTROLS
TIMING RESISTOR (PIN 1)
Timing resistor, R, is connected between pin 1 and V + ,
pin 14. For maximum timing accuracy, R should be in
the range 6 kO :5 R :5 1 MO. See Figure 6 for the minimum and maximum values for R for various supply voltages .
.
;; 100 Mil
z
~
10 Mil
0:
~
5
r----r-.,.----.--,---.,---.
T A " 25 C
~
1 MU
1----4--.+_
I-·-H~~~~~~~-I
~
='
~ lOOKIi
:;;
~
10KS!
"
Z
~
I KII
~----!---~---l---:l:--:l-....J
8
12
16
20
2.
FREE RUNNING FREOUENCY IHlt
r--_IYv--...,.......,....-
40
'"
,,'J
II)
"'"
::J 30
For this application, the XR·320 should be connected
as shown in Figure 9.
A.
/
~
i
The modulation input is applied to pin 1 through coup·
ling capacitor, ee. The input signal modulates the cur·
rent through the timing resistor, R, and, in turn, changes
the width of the output timing pulses. The resistor RM,
in series with the signal source, is used to control the
amount of modulation for a given input signal level.
20
Z
i
~:p
.~
~~
~~
0.25
0.5
/'
/
~
10
o
o
0.75
1.0
1.25
VOL T AGE LEVE L AT PIN 5 (VOLTS)
R
Figure 11. Minimum Pulse Width lor Triggering at Pin 5
I--+-() OUTPUT 2
~-..-.() OUTPUT 1
Figure 9. Circuit Connection lor Pulse-width Modulation
70
\
TA"2& C
l\.". ,
'"
~
c(
~~
."
-..
'~lrr.
0
...
%
u
. /~
i..s
'I-\\~
%
I-
~
~---
80
\
!iO
\~
0
i
40
\
lC
i"'"
~ -2%
30
:I
::J 20
:I
'"ua:
Z
i
: -4%
2.5
5
10
15
20
SUPPLY VOLTAGE'(VOLTS)
~~.
i-
10
o
-6%
'\,
~(\ \
~
\
\
(\1
o
0.5
1.0
1.5
2.0
VOL T AGE LEVEL AT PIN. IVOL TS)
Figure 1D. Change in Timing vs. Supply VoHage
Figure 12. Minimum Pulse Width lor Triggering at Pin 6
1·138
2.5
XR·555
liming Circuit
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-555 monolithic timing circuit is a highly stable
controller capable of producing accurate timing pulses.
It is a direct, pin-far-pin replacement for the SEINE 555
timer. The circuit contains independent control terminals for triggering or resetting if desired.
In the monostable mode of operation, the time delay is
controlled by one external resistor and one capacitor.
For astable operation as an oscillator, the free-running
frequency and the duty cycle are accurately controlled
with two external resistors and one capacitor (as
shown in Figure 2).
ORDERING INFORMATION
The XR-555 may be triggered or reset on falling waveforms. Its output can source or sink up to 200 mA or
drive TIL circuits.
FEATURES
Direct Replacement for SEINE 555
Timing from Microseconds Thru Hours
Operates in Both Monostable and Astable Modes
High Current Drive Capability (200 mAl
TIL and DTL Compatible Outputs
Adjustable Duty Cycle
Temperature Stability of 0.005%/OC
Part Number
Package
Operating Temperature
XR-555M
XR-555CM
XR-555CP
Ceramic
Ceramic
Plastic
- 55°C to + 125°C
O°C to + 70°C
O°C to + 70°C
SYSTEM DESCRIPTION
The XR-555 is an industry standard timing circuit capable of both monostable and astable operation with timing intervals ranging from low microseconds up
through several hours. Timing Is independent of supply
voltage, which may range from 4.5 V to 18 V. The output stage can source or sink 200 mAo
APPLICATIONS
Precision Timing
Pulse Generation
Sequential Timing
Pulse Shaping
Clock Generation
Missing Pulse Detection
Pulse-Width Modulation
Frequency Division
Pulse-Position Modulation
Appliance Timing
In the monostable (one shot) mode, timing is determined by one resistor and capacitor. Astable operations (oscillation) requires an additional resistor, which
controls duty cycle. An internal resistive divider provides a reference voltage of 2/3 VCC, which provides a
timing interval of 1.1 RC. As the reference is related to
VCC, the interval is independent of supply voltage; however, for maximum accuracy, the user should ensure
Vee does not vary during timing.
The output of the XR-555 is high during the timing interval, and pulls low at timeout. It is triggered and reset on
falling waveforms. The·control voltage input (Pin 5) may
serve as a pulse width modulation point.
ABSOLUTE MAXIMUM RATINGS
Power Supply
18 volts
Power DiSSipation (package limitation)
385 mW
Ceramic Package
300 mW
Plastic Package
2.5 mW/oC
Derate above + 25°C
Storage Temperature
-65°C to + 125°C
For applications requiring dual matched 555-type timers, see the XR-556 and XR-2556. For low voltage andl
or low power drain applications, consider the XR-L555
and XR-L556 devices.
1-139
XR·555
ELECTRICAL CHARACTERISTICS
Tast Conditions: (TA = 25°C, VCC =
+ 5V to + 15V,
unless otherwise specified.)
XR-555M
PARAMETERS
Supply Voltage
MIN
TYP
4.5
XR-555C
MAX
MIN
18
4.5
TYP
MAX
UNITS
16
V
Supply Current
3
10
5
12
3
10
6
15
mA
mA
Timing Error (Monostable)
Initial Accuracy
Drift with Temperature
Drift with Supply Voltage
0.5
30
0.05
2.0
100
0.2
1.0
50
0.1
3.0
%
ppm/DC
0.5
%N
Timing Error (Astable)
Initial Accuracy (Note 2)
Drift with Temperature
Drift with Supply Voltage
1.5
90
0.15
2.25
150
0.3
Threshold Voltage
9.4
2.7
10.0
3.33
10.6
4.0
Trigger Voltage
1.45
4.8
f67
5.0
1.9
5.2
0.5
0.9
0.7
1.0
Trigger Current
Reset Voltage
0.4
8.8
2.4
10.0
3.33
11.2
4.2
1.67
5.0
0.4
CONDITIONS
Low State Output (Note 1)
= 5V, RL = co
= 15V, RL = co
VCC
Vee
RA, RS = 1 KG to 100 KG
Note 2, C = 0.1 p.F
O°C s TA s75°C
RA, RS = 1 KG to 100 KG
C = 0.1 p.F
%
ppm/DC
VCC
%N
V
V
= 15V
Vee
VCC
V
V
VCC
Vee
= 15V
= 5V
= 5V
= 15V
0.5
2.0
p.A
0.7
1.0
V
Trigger Input High
Reset Current
0.4
1.0
0.4
1.5
mA
Threshold Current
0.1
0.25
0.1
0.25
p.A
(Note 3)
3.33
10.0
4.0
10.6
3.33
10.0
4.2
11.2
V
V
Vee
VCC
0.10
0.05
0.25
0.2
0.3
0.25
0.35
V
V
0.1
0.4
2.0
2.5
0.15
0.5
2.2
0.1
0.4
2.0
2.5
Control Voltage level
2,7
9.4
2.4
8.8
Output Voltage Drop (Low)
0.25
0.75
2.5
V
V
V
V
3.3
13.3
2.75
12.75
Isink
Isink
Isink
Isink
= 10 mA
3.3
13.3
V
V
= 50 mA
= 100 mA
= 200 mA
Isource = 100 mA
VCC = 5V
Vee = 15V
12.5
V
VCC
p's
VRESET High
Output Voltage Drop (High)
3.0
13
= 5V
= 15V
VCC = 5V
Isink = 8.0 mA
Isink = 5.0 mA
Vee = 15V
Isource
12.5
Turn Off Time (Note 4)
0.5
0.2
0.5
Rise Time of Output
100
200
100
300
nsec
Fall Time cif Output
100
200
100
300
nsec
Discharge Transistor Leakage
20
100
20
100
nA
= 200 mA
= 15V
Nota 1: Supply current when output is high is typically 1.0 mA less.
Nota 2: Tested at VCC = 5V and VCC = 15V.
Nota 3: This will determine the maximum value of RA + RS for 15V operation. The maximum total R = 20
megohms and for 5V operation, the maximum RT = 3.4 megohms.
Nota 4: Time measured from a positive-going input pulse from 0 to 0.8 x Vee into the threshold to the drop from
high to low of the output. Trigger is tied to threshold.
1-140
XR·555
5
CONTROL
THRESHOLD
3
OUTPUT
TRIGGER o - - - J : - - - - + - - - r
DISCHARGE
EQUIVALENT SCHEMATIC DIAGRAM
.-=....- .....---9--=--J
I-=
f"'-~~
(R A + 2R B)C
O.Ol/J F
Rs
CONTROL
VOLTAGE
DUTY CYCLE '" RA + 2RB
Figure 1. Monostable (One-Shot) Circuit
Figure 2. Astable (Free-Running) Circuit
1·141
XR·L555
Micropower Timing Circuit
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-L555 is a stable micropower controller capable
of producing accurate timing pulses. It is a direct replacement for the popular 555-timer for applications requiring very low power dissipation. The XR-L555 has
approximately 1/15th the power dissipation of the standard 555-timer and can operate down to 2.7 volts without sacrificing such key features as timing accuracy
and frequency stability. At 5-volt operation, typical
power dissipation of the XR-L555 is 900 microwatts.
The circuit contains independent control terminals for
triggering or resetting if desired. In the monostable
mode of operation, the time delay is controlled by one
external resistor and one capacitor. For astable operation as an oscillator the free-running frequency and the
duty cycle are accurately controlled with two external
resistors and one capacitor as shown in Figure 2. The
XR-L555 is triggered or reset on falling waveforms. Its
output can source up to 100 mA or drive TIL circuits.
ABSOLUTE MAXIMUM RATINGS
Power Supply
18 volts
Power Dissipation (package limitation)
Ceramic Package
385mW
Plastic Package
300mW
2.5 mW/·C
Derate above + 25·C
Storage Temperature
-65·Cto + 125·C
ORDERING INFORMATION
Because of its temperature stability and low-voltage
(2.7V) operation capability, the XR-L555 is ideally suited
as a micropower clock oscillator or VCO for low-power
CMOS systems. It can operate up to 1500 hours with
only two 300 mA-Hr NiCd batteries.
Part Number
Package
Operating Temperature
XR-L555M
XR-L555CN
XR-L555CP
Ceramic
Ceramic
Plastic
- 55·C to + 125·C
O·C to + 70·C
O·C to + 70·C
SYSTEM DESCRIPTION
FEATURES
The XR-L555 is a micropower timing circuit similar to
the industry standard 555-type timer. It is capable of
both monostable and astable operation with timing intervals ranging from low microseconds up through several hours. Timing is independent of supply voltage
which may range from 2.7 V to 15 V. The output stage
can source 50 mA.
Pin Compatible with Standard 555 Timer
Less than 1 mW Power DisSipation (V + = 5V)
Timing from Microseconds to Minutes
Over 1000-Hour Operation with 2 NiCd Batteries
Low Voltage Operation (V + = 2.7V)
Operates in Both Monostable and Astable Modes
CMOS TIL and DTL Compatible Outputs
In the monostable (one shot) mode, timing is determined by one resistor and capacitor. Astable operation
(oscillation) requires an additional reSistor, which controls duty cycle. An internal resistive divider provides a
reference voltage of 2/3 VCC, the interval is independent of supply voltage; however, for maximum accuracy, the user should ensure Vee does not vary during
timing.
APPLICATIONS
Battery Operated Timing
Micropower Clock Generator
Pulse Shaping and Detection
Micropower PLL Design
Power-On Reset Controller
Micropower Oscillator
Sequential Timing
Pulse Width Modulation
Appliance Timing
Remote-Control Sequencer
The output of the XR-L555 is high during the timing interval. It is triggered and reset on falling waveforms.
The control voltage input (Pin 5) may serve as a pulse
width modulation pOint.
For applications requiring dual L555-type timers, see
the XR-L556.
1-142
XR·L555
ELECTRICAL CHARACTERISTICS
Test Conditions: (TA
= 25°C, VCC = + 5V,
unless otherwise specified.)
XR-L555M
PARAMETERS
MIN
Supply Voltage
TYP
XR-L555C
MAX
MIN
15
2.7
2.7
TYP
MAX
UNITS
15
V
500
pA
Low State Output
VCC = 5V, RL =
1.0
50
0.05
%
ppm/oC
RA, RS = 1 KO to
100 KO
C = 0.1 /LF
O°C :s; TA :s; 75°C
2/3
x VCC
1.67
5.0
V
V
Supply Current
150
190
300
Timing Error
Initial Accuracy
Drift with Temperature
Drift with Supply Voltage
0.5
30
0.05
Threshold Voltage
2.0
100
2/3
Trigger Voltage
1.45
4.8
1.67
5.0
0.4
0.7
Trigger Current
1.9
5.2
0.5
Reset Voltage
Reset Current
0.4
0.1
Threshold Current
Control Voltage Level
2.90
9.6
Output Voltage Drop (Low)
0.7
0.1
0.25
3.80
10.4
0.1
0.3
2.60
9.0
3.3
13.3
2.75
12.75
V
0.1
0.25
pA
3.33
10.0
4.00
11.0
V
0.25
0.35
V
3.3
13.3
V
V
12.5
12.5
V
Rise Time of Output
100
100
nsec
Fall Time of Output
100
100
nsec
Discharge Transistor
Leakage
0.1
0.1
/LA
T=l.lR A C
= 5V
= 15V
Isink = 1.5 mA
Isource = 10 mA
Vee = 5V
VCC = 15V
Isource = 100 mA
VCC = 15V
VCC
VCC
R
L 4
~OUTOP~U_T-o~3~
f--.!--l
lJ
= 5V
= 15V
mA
Output Voltage Drop (High)
3.0
13
VCC
VCC
/LA
1.0
0.1
3.33
10.0
8
lJ1.J
XR·L555
TRIGGER
OUTPOU~T__~3~~~,
XR·L~?5
r---v--...,
2
CONTROL
5
INPUT ~--cr-L--,_..J
f 1.46
- (R A +2R BIC
Re
DUTY CYCLE = RA + 2Re
Figure 1. Monostable (One-Shot) Circuit
Figure 2. Astable (Free-Running) Circuit
1·143
00
%N
0.5
1.0
CONDITIONS
XR·L555
CHARACTERISTIC CURVES
GENERAL CHARACTERISTICS
400
360
_
.ffi
320
A. 2ao
240
>
f-i
aD
40
V
~
V
180
120
V
/
~200
u
5
~U~OC
rr
V-
I
l:i
900
i!
600
awn w
~
~
-
I
J
..
5
700
TA • -2SQ C
Q
600
~
ii
z
ii
vCr~A'75~ VI~
> 80D -T,...• U50C
Vee" 2.5V/- /
/
400
300
20D
~
~
...-
.L
0.1
~
0.2
Z
0
600
l!
400
a:
20D
~
l!v
..
~
CC "5V-
/
100
246
'200
li
1,000
BOO
i
!l
II
Figura 3. Supply Current as a Function 01
Supply VoHage
1.
TA "+25bC
:: 1000
;:
..
i-"'"
":"'T1-""'• +7Sf"lC- i A
V
'200
1100
1...1-
TA ·-25;.... ~
f-' i--
0:
1 1 1
I I .!,-:;
L
I
0.3
0.'
0.4
Figure 4. Minimum Pulse·Wldth Requlrad lor
Triggering
0.2
0.3
0.4
Figure 5. Propagation Delay as a Function 01
Voltage Level 01 Trigger Pulse
MONOSTABLE OPERATION
+4
l:
V
"3
~ +2
0:
~
Z
0
~
.. ,
N
~
0:
0:
co
! 0 r--.. I"z
V
/
S
N
II
-2
~
5
10
15
-3
"25
20
Figure 6. Typical Timing Accuracy as a
Function 01 Supply Voltage
_ +2
.
i
+1
Q
~
..a~
0:
N
~0:
Blb~R)'00IK
A
>
A
~.
0
~ -3
-4
10
15
20
Figure 9. Typical Frequency StabliHy as a
Function 01 Supply VoHage
g
~100
~
0.6
0.8
'.0
,
::l
"""
l"- t"--
.:il.
1.5
~
0:
D 1.0
I"-..
N
i",-
c
I
g
I
::i 0.5
Vcc·SV
Vi
I
a
0
25
50
75
Figure 10. Typical Frequency Stability as a
Function 01 Temperature (RA = RS = 10KO.
C = 0.1 "F)
~
!
a
o.a
o.e
'.0
Figure 11. Normalized Fraquency 01 Oscillation
as a Funcllon 01 Control Voltage
0.2
0.4
J5°C
1 400
ACONVENTIONAL
555-TIMER
..• 300 I - il
0.4
100 ""'''''''''-r-..,.--.,-.".--,,----'
TA
iii
0.2
:;
-1.5
-25
500
1200
I
o
o
i
-0.5
~
TA -ZSOc
5
'r--..
i -,
C
o
~
2.0
+0.5
Q
~
:;
~
I
I
0:
Figure 8. Normalized Time Delay as a Funcllon
01 Control VoHage
1\
!il
0:
II
-2
k"":
~ 0.5
::i .
+'
Q
>
0
-1
~
75
50
v:
Q
g +1.5
RlJ,J~
!!
25°C
0
t= 1.0
Figure 7. Typical Timing Accuracy as a
Function 01 Temperature (VCC = 51V.
RA = 100KO, C = 0.01 "F)
ASTABLE OPERATION
J
L
::i
"
z
o
L
IL
Q
~ -2
~ -3
2.0
~ 1.5
-,
~
::i
-4
.
~
.
2
.
/
+,
ii
;:
!!
!Ii
1/
0:
-\
\
0
ii:
E!w
!il
i!
ij
~
\
400
ii:
BOO
Figure 12. Comparison 01 Supply Current
Transient 01 Convenllonal 555-Tlmer with
XR·L555 Micropower Timer
aoo
w
1.0 1-+--1~
!il
i!
u~
0.1
0.001
"-...J<..~~"""-+_-'--I---'
10 Il' 1.0 m.
100 ms
10.
Figure 13. Timing Period. T. as a Funcllon 01
Extarnal R·C Network
1·144
10
E!-
~ 0.01
XR·L555
TIMER
200
10 I--+-t-~
0.01
0.001
'---"-_J..........J...---JL....>...L.._"'-'
0.1
1.0
10 100 10K 1.0K lOOK
, Figure 14. Free Running Frequency as a
Function 01 External Timing Components
(Note: R = RA + 2Ra)
XR·L555
FEATURES OF XR-L555
The XR-L555 micropower timer is, in most instances, a
direct pin-for-pin replacement for the conventional 555type timer. However, compared to conventional 555timer, it offers the following important performance features:
enced to 2/3 VCC with the use of three equal internal resistors. When the voltage across the capacitor reaches
this level, the flip-flop is reset, the capacitor is discharged rapidly, and the output level moves toward
ground, and the timing cycle is completed.
Reduced Power Dissipation: The current drain is 1/15th of
the conventional 555-timer.
The duration of the timing period, T, during which the
output logic level is at a "high" state is given by the
equation:
T = 1.1 RAC
No Supply Current Transients: The conventional 555-timer
can produce 300 to 400 mA of supply current spikes
during switching. The XR-L555 is virtually transient-free
as shown in Figure 12.
The time delay varies linearly with the choice of RA and
C as shown by the timing curves of Figure 13. For
proper operation of the circuit, the trigger pulse-width
must be less than the timing period.
Low-Voltage Operation: The XR-L555 operates down to 2.7
volts of supply voltage, vs. 4.5V minimum operating
voltage needed for conventional 555-timer. Thus, the
XR-L555 can operate safely and reliably with two 1.5V
NiCd batteries.
APPLICATIONS INFORMATION
Once the circuit is triggered it is immune to additional
trigger inputs until the present timing-period has been
completed. The timing-cycle can be interrupted by using the reset control (pin 4). When the reset control is
"low", the internal discharge transistor is turned "on"
and prevents the capacitor from charging. As long as
the reset voltage is applied, the digital output level will
remain unchanged, I.e. "low". The reset pin should be
connected to + VCC when not used to avoid the possibility of false triggering.
MONOSTABLE (ONE-SHOT) OPERATION
ASTABLE (SELF-TRIGGERING) OPERATION
The circuit connection for monostable, or one-shot operation of the XR-L555 is shown in Figure 1. The internal flip-flop is triggered by lowering the trigger level at
pin 2 to less than 1/3 of VCC. The circuit triggers on a
negative-going slope. Upon triggering, the flip-flop is
set to one side, which releases the short circuit across
the capacitor and also moves the output level at pin 3
toward VCC. The voltage across the capacitor, therefore, starts increasing exponentially with a time constant T = RAC. A high impedance comparator is refer-
For astable (or self-triggering) operation, the correct circuit connection is shown in Figure 2. The external capacitor charges to 2/3 VCC through the parallel combination of RA and RB, and discharges to 1/3 VCC
through RB. In this manner, the capacitor voltage oscillates between 1/3 VCC and 2/3 Vcc, with an exponential waveform. The oscillations can be keyed "on" and
"off" using the reset control. The frequency of oscillation can be readily calculated from the equations in Figure 2 and Figure 14.
Proven Bipolar Technology: The XR-L555 is fabricated using conventional bipolar process technology. Thus, it is
immune to electrostatic burn-out problems associated
with low-power timers using CMOS technology.
EQUIVALENT SCHEMATIC DIAGRAM
1-145
XR·556
Dual Timer
GENERAL DESCRIPTION
FUNCTIONAL BLDCK DIAGRAM
The XR-556 dual timing circuit contains two independent 555-type timers on a single monolithic chip. It is a
direct, pin-for-pin replacement for the SEINE 556 dual
timer. Each timer section Is a highly stable controller
capable of producing accurate time delays or oscillations. Independent output and control terminals are
provided for each section as shown in the functional
block diagram.
DISCHARGE
In the monostable mode of operation, the time delay for
each section is precisely controlled by one external resistor and one capacitor. For astable operation as an
oscillator, the free-running frequency and the duty cycle of each section are accurately controlled with two
external resistors and one capacitor..
THRESHOLD
DISCHARGE
CONTROL
VOLTAGE
THRESHOLD
CONTROL
VOLTAGE
RESET
OUTPUT
The XR-556 may be triggered or reset on failing waveforms. Each output can source or sink up to 150 mA or
drive TIL circuits. The matching and temperature track. ing characteristics between each timer section of the
XR-556 are superior to those available from two separate timer packages.
RESET
TRIGGER
OUTPUT
GROUND
TRIGGER
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Ceramic Dual-In-Line
Derate above TA = 25°C
Plastic Dual-In-Line
Derate above TA = 25°C
Storage Temperature Range
FEATURES
Direct Replacement for SEINE 556
Replaces Two 555-Type Timers
TIL Compatible Pinouts
Timing from Microseconds Thru Hours
Excellent Matching Between Timer Sections
Operates in Both Monostable and Astable Modes
High Current Drive Capability (150 mA each output)
TIL and DTl Compatible Outputs
Adjustable Duty Cycle
Temperature Stability of 0.005%/OC
18V
750mW
6 mW/oC
625 mW
5 mW/oC
-65°C to + 150°C
ORDERING INFORMATION
APPLICATIONS
Precision Timing
Pulse Generation
Sequential Timing
Pulse Shaping
Time Delay Generation
Clock Pattern Generation
Missing Pulse Detection
Pulse-Width Modulation
Frequency Division
Clock Synchronization
Pulse-Position Modulation
Appliance Timing
Part Number
Package
Operating Temperatura
XR-556M
XR-556CN
XR-556CP
Ceramic
Ceramic
Plastic
-55°C to +125°C
O°C to +70°C
DOC to + 70°C
SYSTEM DESCRIPTION
The XR-556 is an industry standard dual timing circuit
capable of both monostable and astable operation with
timing intervals ranging from low microseconds up
through several hours. Timing is independent of supply
voltage, which may range from, 4.5 V to 18 V. The output stage can source or sink 150 mAo Each timer section is fully independent and similar to 555-type devices.
1-146
XR·556
CONTROL
OUTPUT
5K
DISCHARGE
5K
GNO~
EQUIVALENT SCHEMATIC DIAGRAM
SYSTEM DESCRIPTION (continued)
The output of the XR-556 is high during the timing interval, and pulls low at timeout. It is triggered and reset on
falling waveforms. The control voltage inputs (Pins 3
and 11) may serve as pulse width modulation points.
Matching between sections is typically better than
0.05% initially, with temperature drift tracking to ± 10
ppm/oe and supply voltage drift tracking to 0.1 %N. For
low voltage and/or low power drain applications, consider the XR-L556.
In the monostable (one shot) mode, timing is determined by one resistor and capacitor. Astable operation
(oscillation) requires an additional resistor, which controls duty cycle. An internal resistive divider provides a
reference voltage of 2/3 Vee, which produces a timing
interval of 1.1 Re. As the reference is related to Vee,
the interval is independent of supply voltage; however,
for maximum accuracy, the user should ensure Vee
does not vary during timing.
1-147
XR·556
ELECTRICAL CHARACTERISTICS
Test Conditions: (Each timer section, TA
= 25°e, Vee = + 5V to + 15V, unless otherwise specified.)
XR·556M
PARAMETERS
Supply Voltage
MIN
TYP
4.5
XR·556C
MAX
MIN
18
4.5
TYP
MAX
UNITS
16
V
Supply Current
(Each Timer Section)
3
5
3
6
mA
10
11
10
14
mA
6
10
6
12
mA
20
22
20
28
mA
Tolal Supply Currenl
(Soth Timer Sections)
Timing Error (Monos table)
Initial Accuracy
Drift with Temperature
Drift with Supply Voltage
0.5
3D
0.05
.75
50
0.1
1.5
100
0.2
3
0.5
%
ppm/'C
%N
Timing Error (Astable)
Initial Accuracy (Note 2)
Drift with Temperature
Drift with Supply Voltage
1.5
90
0.15
%
ppm/'C
%N
2.25
150
0.3
CONDITIONS
Low State Output,
Note 1
Vee ~ 5V,
RL ~ 00
VCC ~ 15V,
RL ~ 00
Low Slate Output,
Note 1
VCC ~ 5V,
RL ~ 00
Vee ~ 15V,
RL ~ 00
Timing, R ~ 1 KD
to 100 KD
Note 2, C ~ 1.0 "F
O'C sTA s75'C
RA' RS ~ 1 KD
to 100 KD
C ~ 0.1 "F
VCC ~ 15V
9.4
2.7
10.0
3.33
10.6
4.0
8.8
2.4
10.0
3.33
11.2
4.2
V
V
Vee ~ 15V
VCC ~ 5V
1.45
4.8
1.67
5.0
1.9
5.2
4.5
1.67
5.0
5.6
V
V
VCC ~ 5V
Vee ~ 15V
0.5
0.9
0.4
0.7
1.0
Reset Current
0.4
Threshold Current
Threshold Voltage
Trigger Voltage
Trigger Current
Reset Voltage
0.5
2
1.0
"A
V
VTRIG ~ OV
0.7
1
0.4
1.5
mA
VRESET ~ OV
0.03
0.1
0.03
0.1
"A
Note 3
3.33
10.0
3.80
lOA
3.33
10.0
4.00
11.0
0.10
0.05
0.25
0.20
0.3
0.25
0.35
0.1
0.4
2.0
2.5
0.15
0.5
2.25
0.1
0.4
2.0
2.5
0.4
VTRIG High
Control Voltage Level
2.90
9.6
2.60
9.0
VCC ~ 5V
Vee ~ 15V
Output Voltage Drop (Low)
0.25
0.75
2.75
V
V
V
V
V
V
Output Voltage Drop (High)
3.0
13
3.3
13.3
2.75
12.75
12.5
V
V
3.3
13.3
V
12.5
Rise Time of Output
100
200
100
300
nsec
Fall Time of Output
100
200
100
300
nsec
0.05
±10
0.1
0.1
±10
0.2
%
ppm/'C
0.1
0.2
0.2
0.5
%N
Matching Characteristic
Initial Timing Accuracy
Timing Drift with
Temperature
Drift with Supply Voltage
Vee
Isink
Isink
VCC
Isink
Isink
Isink
Isink
~
~
~
~
~
~
~
~
5V
8.0 mA
5.0 mA
15V
10 mA
50 mA
100 mA
200 mA
Isource ~ 100 mA
VCC = 5V
VCC = 15V
Isource = 200 mA
Vee ~ 15V
Note 4
Note 1: Supply current when output is high is typically 1.0 mA less.
Note 2: Tested at Vee = 5V and Vee ~ 15V.
Note 3: This will determine the maximum value of RA + RS for 15V operation. The maximum total R = 10
megohms, and for 5V operation, the maximum R = 3.4 megohms.
Note 4: Matching characteristics refer to the difference between performance characteristics of each timer section.
1-148
XR·L556
Micropower Dual Timer
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-L556 dual timer contains two independent micropower timer sections on a monolithic chip. It is a direct replacement for the conventional 556-type dual
timers, for applications requiring very low power dissipation. Each section of the XR-L556 dual timer is equivalent to Exar's XR-L555 micropower timer. The circuit
dissipates only 1/15th of the stand-by power of conventional dual timers and can operate down to 2.5 volts
without sacrificing such key features as timing accuracy and stability. At 5 volt operation, typical power dissipation of the dual-timer circuit is less than 2 mW; and
it can operate in excess of 500 hours with only two 300
mA-Hr NiCd batteries.
THRESHOLD
DISCIiAnCE
CONTROL
'HRESUCLO
VOLtAGE
coumOL
REsn
VOLTAGE
Rnn
OUTPUT
The two timer sections of the circuit have separate controls and outputs, but share common supply and
ground terminals. Each output can source up to 100
mA of output current or drive TTL circuits.
FEATURES
tRIGGER
outPUT
GROUND
TRIGctR
ORDERING INFORMATION
Replaces two XR-L555 Micropower Timers
Pin Compatible with Standard 556-Type Dual Timer
Less than 1 mW Power Dissipation per Section (VCC =
5V)
Timing from Microseconds to Minutes
Over 500-Hour Operation with 2 NiCd Batteries Low
Voltage Operation (Vee = 2.5V)
Operates in Both Monostable and Astable Modes
CMOS TTL and DTL Compatible Outputs
Introduces No Switching Transients
Part Number
Package
Operating Temperature
XR-L556 M
XR-L556 CN
XR-L556 CP
Ceramic
Ceramic
Plastic
- 55 DC to + 125DC
ODC to + 70 DC
ODC to + 70 DC
SYSTEM DESCRIPTION
The XR-L556 is a micropower version of the industry
standard XR-556 timing circuit, capable of both
monostable and astable operation with timing intervals
ranging from low microseconds up through several
hours. Timing is independent of supply voltage, which
may range from 2.5 V to 15 V. The output stage can
source 100 mA. Each timer section is fully independent
and similar to the XR-L555.
APPLICATIONS
Battery Operated Timing
Micropower Clock Generator
Pulse Shaping and Detection
Micropower PLL Design
Power-On Reset Controller
Micropower Oscillator
Sequential Timing
Pulse-Width Modulation
Appliance Timing
Remote-Control Sequencer
In the monostable (one shot) mode, timing is determined by one resistor and capacitor. Astable operation
(oscillation) requires an additional reSistor, which controls duty cycle. An internal resistive divider provides a
reference voltage of 2/3 VCC, which produces. a timing
interval of 1.1 RC. As the reference is related to VCC,
the interval is independent of supply voltage; however,
for maximum accuracy, the user should ensure Vee
does not vary during timing.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Ceramic Dual-In-Line
Derate above TA = 25 DC
Plastic Dual-In-Line
Derate above TA = 25 DC
Storage Temperature Range
Vee
DISCHARGE
18V
750 mW
6 mW/DC
The output of the XR-L556 is high during the timing interval. It is triggered and reset on falling waveforms.
The control voltage inputs (Pins 3 and 11) may serve as
pulse width modulation points.
625mW
5 mW/DC
-65 DC to + 150 DC
1-149
XR·L556
ELELTRICAL CHARACTERISTICS
Test CondHlons: (TA = 25° DC, VCC = +5V, unless otherwise specified)
XR-L556C
XR-L556M
PARAMETERS
MIN
Supply Voltage
TYP
MAX
MIN
15
2.7
2.5
TYP
MAX
UNITS
15
V
Supply Current
(Each Timer Section)
Total Supply Current
(Soth Timer Sections)
150
300
200
500
p.A
300
600
400
1000
p.A
Timing Error
Initial Accuracy
Drift with Temperature
Drift with Supply Voltage
0.5
50
0.5
200
1.0
50
0.5
ppm/oC
Threshold Voltage
2/3
2/3
XVCC
1.67
5.0
V
V
Trigger Voltage
1.45
4.8
1.9
5.2
1.67
5.0
Trigger Current
0.4
0.7
Reset Curerent
1.0
0.4
10
Threshold Current
Control Voltage Level
2.90
9.6
Output Voltage Drop (Low)
%N
20
20
Reset Voltage
%
0.7
10
50
3.80
10.4
0.1
0.3
2.60
9.0
3.3
13.3
2.75
12.75
RA, RS = 1 KIl to 100 KIl
C = 0.1 p.F
O°C s TA s 70°C
Monostable Operation
VCC
VCC
= 5V
= 15V
V
20
100
nA
3.33
10.0
4.00
11.0
V
V
0.15
0.35
V
V
V
3.3
13.3
12.5
12.5
V
Rise Time of Output
200
200
nsec
Fall Time of Output
100
100
nsec
Discharge Transistor
Leakage
0.1
0.1
p.A
. . - - - -.....-
= 5V
= 15V
Isink = 1.5 mA
Isource = 10mA
VCC = 5V
VCC = 15V
Isource = 100 mA
VCC = 15V
VCC
Vee
r----~--?'-<>v
.......- - ( ) Vee
RESET
,.
RA
R,
00
p.A
Output Voltage Drop (High)
3.0
13
Low State Output
VCC = 5V, RL =
nA
1.0
10
3.33
10.0
CONDITION
.
RA
OUTPUT
OUTPUT
1/10F KR L5S6
In
DISCHARGE
lJlS
DISCftARGE
1--<>---,
T>RI-GG-'R-----TR~,GrG'-R~..__, _ - -
1/20F )(R558
RO
THRESHOLD
CONTROL
I·e
IRleGER
THRESHOLD
CONTROL
INPUT
INPUT
Figure 1. Monostable (One-Shot) Circuit
CONTROL
Figure 2. Astable (Free-Running) CircuH
1-150
XR·L556
CHARACTERISTIC CURVES
GENERAL CHARACTERISTICS
800
720
_ 640
~560
I-
l - f-
TA
V
~ 480
a:
/
~ 400
u
~ 320
R:
iil
l.J(!
'-25:;';
I I
.J
1o
V
L..-;A "'+7S"C-
-
BOO
VCC ·2.5V/
700
~
:;;
::J
:;;
600
Z
300
500
/
200
'--
4
6
8
10
12 14
16
18
"
II
V
0.1
20
0.2
-
600
0.3
""~
400
g:
200
0.1
0.4
LEVEL ( X Vcci
Figure S. Propagation Delay as a
Function of Voltage Level of
Trigger Pulse
Figure 4. Minimum Pulse-Width
Required for Triggering
MONOSTABLE OPERATION
2.0
+4
V
~ +3
a:
~
+2
ffi
"
2
+1
~
0
S
N
-1
~
-2
;::
/
J
V
V
:5
1/
,:
~
t=
o
2
1.0
W
o
l"-
W
N
:; -1
N
:::;
«
:;;
a:
2
-3
o
-25
20
o
ASTABLE OPERATION
a:
+2
R
+1
o
>-
ffi
@ -1
ow
a:
BI.o~RB~'00IK
-2
ffi~
+1
~ +0.5
", --
a:
IL
~
:::;
-0.5
:::;
-4
"o~
T A'" 25°C
I
r
o
10
15
SUPPLY VOLTAGE, Vee (VOLTS)
Figure 9. Typical Frequency
Stability as a Function of
Supply Voltage
ow
r-..
w
o
,
2.0
ow
2
75
>-
::J
"o~ -3
O.B
1.0
0.6
CONTROL VOLTAGE AS FRACTION OF Vee
0.4
0.2
u
o
>-
II
ff
N
1;:
It
::J
50
_ +1.5
~
lelJ%tJ
A
u
25°C
I
o
Figure 7. Typical Timing
Figure 8. Normalized Time
Accuracy as a Function of
Delay as a Function of
Temperature
Con trol Voltage
(V CC =SV, RA = IOOKU, C =O.OIJ.LF)
Figure 6. Typical Tim ing
Accuracy as a Function of
Supply Voltage
1;:
I
TEMPERATURE (oCI
SUPPLY VOL TAGE Vee (VOLTS)
~
~
/
I
2
15
V
0.5
o
"
:;;
a:
10
I
~
"~ t'--.. t-;:: 0
~ -2
o
II
"o 1.5
2
a:
a:
w
-4
/
I-
~
:;;
~ -3
_
0.4
0.3
0.2
LOWEST TRIGGER VOLTAGE
TRIGGER PULSE IX Vee'
Figure 3. Total Supply Current as a
Function of Supply Voltage
TA "-2SoC
0
LOWEST VOLTAGE LEVEL OF
SUPPLY VOLTAGE, Vee (VOLTS)
I?
r-- TA- +25 0 C
;::
I
J
I
I
0
Z
0
./
:...-
1./1
V '5V+. 1
0
CF I
TA"":5,5- I
lOaD
>- BOO
oj
l/vcc'5V
/
100
o II
II
I
400
~
I
80
~
900
~
"..-
160
iI-
1:
V
1200
III
TA= +25 bC
c 1000
0
I--"
V
1100
;;;
,T A "-25C
1-' .....
V
240
01
1200
-1
V
2
-
.........
1,5
'"
ff
c 1.0
w
N
:::;
r-.....
t--..
I,
I
"a:o
:;; 0.5
I
z
0.2
CF = 5~
"-
I
0.4
0.6
O.B
1.0
CONTROL VOLTAGE AS FRACTION OF Vee
-1.5
20
-25
o
25
50
TEMPERATURE ,oCI
75
Figure 10. Typical Frequency
Stability as a Function of
Temperature
(R A =RB = IOKU. C =O.IJ.lF)
1·151
Figure II. Normalized Frequency
of Oscillation as a Function of
Control Voltage
XR·L556
FEATURES OF XR-L556
500
TA _25°C
The XR-L556 micropower dual timer is, in most instances, a direct pin-for-pin replacement for the conventional 556-type dual timer. However, compared to
conventional 556-timer, it offers the following important
performance features:
A
400
CONVENTIONAL
NE556 DUAL TIMER
c
E
...z
300
\
\
\
-
III
II:
II:
Reduced Power Dissipation: The current drain is 1I15th of
the conventional 556-type dual timer.
:;,
..
200
:;,
100
u
>
II.
II.
No Supply Current Transients: The conventional 556-timer
can produce 300 to 400 mA of supply current spikes
during switching of either one of its timer sections. The
XR-L556 is virtually transient-free as shown in Figure
12.
'"
0
Low-Voltage Operation: The XR-L556 operates down to 2.7
volts of supply voltage, vs. 4.5V minimum operating
voltage needed for conventional 556-timer. Thus, the
XR-L556 can operate safely and reliably with two 1.5V
NiCd batteries.
I\....
XR·L556
DUALTlrER
o
200
600
400
TIME AFTER TRIGGER INPUT InS.c)
aoo
Figure 12. Comparison of Supply Current Transiant of
Convantional NE556 Dual Timer with XR-L556
Micropower Dual Timer
Proven Bipolar Technology: The XR-L556 is fabricated using conventional bipolar process technology. Thus, it is
immune to electrostatic burn-out problems associated
with low-power timers using CMOS technology.
i.e. "low". The reset pin should be connected to + Vee
when not used to avoid the possibility of false triggering.
PRINCIPLES OF OPERATION
ASTABLE (SELF-TRIGGERING) OPERATION
MoNoSTABLE (ONE-SHOT) OPERATION
For astable (or self-triggering) operation, the correct circuit connection is shown in Figure 2. The external capacitor charges to 213 VCC through the series combination of RA and RS, and discharges to 1/3 Vee through
RS. In this manner, the capacitor voltage oscillates between 113 VCC and 2/3 VCC, with an exponential waveform. The output level at pin 5 (or 9) is high during the
charging cycle, and goes low during the discharge cycle. The charge and the discharge times are independent of supply voltage. The oscillations can be keyed
"on" and "off" using the reset controls (pin 4 or 10).
The circuit connection for monostable, or one-shot operation is one of the timer sections of the XR-L556 is
shown in Figure 1. The internal flip-flop is triggered by
lowering the trigger level to less than 1/3 of VCC. The
circuit triggers on a negative-going slope. Upon triggering, the flip-flop is set, which releases the short circuit
across the capacitor and also moves the output level
toward Vee: The voltage across the capacitor, therefore, starts increasing exponentially with a time constant T = RAC. A comparator is referenced to 2/3 Vee
with the use of three equal internal resistors. When the
voltage across the capacity reaches this level, the flipflop is reset, the capacitor is discharged rapidly, the
output level moves toward ground and the timing cycle
is completed. The duration of the timing period, T, during which the output logic level is at a "high" state is
given by the equation:
T = 1.1 RAC
This time delay varies linearly with the choice of RA and
C as shown by the timing curves of Figure 13. For
proper operation of the circuit, the trigger pulse-width
must be less than the timing period.
Once the circuit is triggered it is immune to additional
trigger inputs until the present period has been completed. The timing-cycle can be interrupted by using the
reset control. When the reset control is "low", the internal discharge transistor is turned "on" and prevents the
capacitor from charging. As long as the reset voltage is
applied, the digital output level will remain unchanged
TIMING PERIOD, T
Figure 13. Timing Period, T, as a Function of External R-C
Natwork
1-152
XR·L556
The charge time (output high) is given by:
t1 = 0.695 (RA
+
100
RS)C
u::
The discharge time (output low) by:
w
t2 = 0.695 (RS)C
Z
-=---o OUTPUT
1f
l-
TRIGOER
SUUUl.
IT1.1.1A1C,1
Figure 18. Frequency Divider and Pulse-Shaper
1.45
fRAt2RalC2
MICROPOWER OSCILLATOR WITH INDEPENDENT
FREQUENCY AND DUTY CYCLE ADJUSTMENT
Figure 17. Keyed Oscillator
If Timer 1 is operated in its astable mode and Timer 2 is
operated in its monostable mode, as shown in Figure
19, then an oscillator with fixed frequency and variable
duty cycle results.
FREQUENCY DIVIDER AND PULSE SHAPER
If the frequency of the input is known, each timer sec·
tion of the XR·L556 can be used as a frequency divider
by adjusting the length of its timing cycle. If the timing
interval T 1 (= 1.1 R1C1) is larger than the period of the
input pulse trigger, then only those input pulses which
are spaced more than 1.1 R1 C1 will actually trigger the
circuit.
Timer 1 generates a basic periodic waveform that is
then used to trigger Timer 2. If the time delay, T2, of
Timer 2 is chosen to be less than the period of oscillations of Timer 1, then the output at pin 9 has the same
frequency as Timer 1, but has its duty cycle determined
by the timing cycle of Timer 2. The output duty cycle
can be adjusted over a wide range (from 1 % to 99%)
by adjusting R2.
,------t"----r--o'\lcc
The output frequency is equal to (1/N) times the input
frequency. The division factor N is in the range:
l_1 Vcc
Figure 19. Micropower Oscillator with Fixed Frequency and
Variable Duty-Cycle
Where N1 and N2 are the division factors for respective
timer sections, set by external resistors and capacitors
at pins (1, 2) and (12, 13).
Frequency division can be performed by 1/2 of the XRL556. The remaining timer section can be used as a
"pulse-shaper" to adjust the duty cycle of the output
waveform. As seen in Figure 18, Timer 1 is used as the
frequency divider section and Timer 2 is used as the
pulse shapero
The output of Timer 1 (pin 5) triggers Timer 2, which
produces an output pulse whose frequency is the same
as the output frequency of Timer 1, and whose duty cycle is controlled by the timing resistor and capacitor of
Timer 2. The duty cycle of the output of Timer 2 (pin 9)
can be adjusted from 1 % to 99% by varying the value
of R2.
ONE SECTION OF
~R·L556
EQUIVALENT SCHEMATIC DIAGRAM
1-154
XR·558/559
Q!Uladl lomulnlg Cnrcuits
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-558 and the XR-559 quad timing circuits contain four independent timer sections on a single monolithic chip. Each of the timer sections on the chip are
entirely independent, and each one can produce a time
delay from microseconds to minutes, as set by an external R-C network. Each timer has its separate trigger
terminal, but all four timers in the IC package share a
common reset control.
OUTPUT 0
TIMING 0
TRICCER 0
COMMON
RESET
Both the XR-558 and the XR-559 quad timer circuits are
"edge-triggered" devices, so that each timer section
can be cascaded, or connected in tandem, with other
timer sections, without requiring coupling capacitors.
GROUNO
TRIGGER C
The XR-558 is designed with open-collector outputs;
each output can sink up to 100 mAo The XR-559 is designed with emitter-follower outputs. Each output can
source up to 100 mA of load current. The outputs are
normally at "low" state, and go to "high" state during
the timing interval.
TIMING C
OUTPUT C
ORDERING INFORMATION
FEATURES
Four Independent Timer Sections
High Current Output Capability
XR-558: 100 mA sinking capability/output
XR-559: 100 mA sourcing capability/output
Edge Triggered Controls
Output Stage Independent of Trigger Condition
Wide Supply Range: 4.5 V to 16 V
Package
Operating Temperature
Ceramic
Ceramic
Plastic
Ceramic
Ceramic
Plastic
-55°C to +125°C
DoC to +70°C
DoC to + 70°C
-55°C to +125°C
DoC to + 70°C
DoC to + 70°C
SYSTEM DESCRIPTION
The XR-558 and XR-559 are easy to use quad timers
capable of operation with supply voltages between 4.5
V and 18 V. Each section has independent timing and
triggering, and can operate over intervals ranging from
the low microseconds up through several minutes. The
devices are triggered on falling waveforms and are immune to long trigger pulses. When the reset pin (Pin 13)
is held below 0.8 V, all four outputs are set low and all
triggers are disabled. Timing period accuracy is typically better than 1 %, independent of VCC, and drift is
better than 150 ppm/DC and 0.5 % IV. The timing period,
in seconds, equals R times C.
APPLICATIONS
Precision Timing
Pulse Shaping
Clock Synchronization
Appliance Timing
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Ceramic Dual-In-Line
Derate above TA = 25"
Plastic Dual-In-Line
Derate above TA = 25"C
Storage Temperature Range
Part Number
XR-558M
XR-558CN
XR-558CP
XR-559M
XR-559CN
XR-559CP
18V
The XR-558 features open collector outputs, capable of
sinking 100 mA, that are driven low during the timing interval. The XR-559 has emitter followers, active upon
timeout, capable of sourcing 100 mAo The XR-558 siriks
load current from + VCC, the XR-559 sources load current to ground.
750 mW
6 mW/oC
625 mW
5 mW/oC
-65°C to +150°C
1-155
XR·558/559
ELECTRICAL CHARACTERISTICS
Test Conditions: (TA = 25°C, VCC = + 5V to + 15V, unless otherwise noted.)
PARAMETERS
Supply Voltage
XR-558M/XR-559M
MIN TYP MAX
4.5
18
XR-558C/XR-559C
MIN
TYP
MAX
16
4.5
Supply Current
XR-558 Family
XR-559 Family
21
9
32
16
27
12
Timing Accuracy
Initial Accuracy
Drift with Temperature
Drift with Supply Voltage
1
150
0.1
3
2
150
0.1
36
18
UNITS
mA
mA
%
ppm/oC
0.8
1.5
5
2.4
30
0.8
1.5
10
2.4
100
V
,..A
Reset Characteristics
Reset Voltage
Reset Current
0.8
1.5
50
2.4
300
0.8
1.5
50
2.4
V
,..A
0.63
15
XR-558 Output
Characteristics
Output Voltage
Output Voltage
Output Leakage
XR-559 Output
Characteristics
Output Voltage
Output Voltage
VCC = VRESET
Outputs Open
Outputs Open
R
C
= 15V
= 2 kO to 100 kO
= 1,..F
%N
Trigger Characteristics
Trigger Voltage
Trigger Current
Threshold Characteristics
Threshold Voltage
Threshold Leakage
CONDITIONS
V
0.63
15
XVCC
nA
See Note: 1
VCC = 15V
VTRIGGER = OV
See Note: 2
Measured at Timing Pins
(Pins 2, 7, 10 or 15)
See Note: 3
0.1
0.7
10
0.2
1.5
0.1
1.0
10
0.4
2.0
V
V
nA
IL = 10 mA
IL = 100 mA
Output High Condition
See Note: 4
13
12.5
13.6
13.3
12.5
12.0
13.3
13.0
V
V
Propagation Delay
XR-558 Family
XR-559 Family
1.0
0.4
1.0
0.4
,..sec
,..sec
Output Rise-time
Output Fall-time
100
100
100
100
nsec
nsec
IL
IL
= 10 mA, VCC = 15V
= 100 mA, VCC = 15V
IL
IL
= 100 mA
= 100 mA
NOTES:
1. The trigger functions only on the falling edge of the trigger pulse only after previously being high. After reset the
trigger must be brought high and then low to implement triggering.
2. For reset below 0.8 volts, outputs set low and trigger inhibited. For reset above 2.4 volts, trigger enabled.
3: The XR-558 output structure is open collector which requires a pull up resistor to VCC to sink current. The
output is normally low sinking current.
4. The XR-559 output structure is a darlington emitter follower which requires a pull down resistor to ground to
source current. The output is normally low and sources current only when switched high.
the IC. All four timing sections can be used simultane~
ously, or can be interconnected in tandem, for sequential timing applications. For astable operation, two sections of the quad-timer IC can be interconnected to provide an oscillator circuit whose duty-cycle can be
adjusted from close to zero, to nearly 100 %.
DESCRIPTION OF CIRCUIT OPERATION
The XR-558/559 quad timing circuits are designed to be
used in timing applications ranging from few microseconds up several hours. They provide cost-effective alternative to single-timer IC's in applications requiring a
multiplicity of timing or sequencing functions.
The generalized test and evaluation circuit for both the
XR-558 and the XR-559 quad timer circuits is shown in
Figure 1. Note that, the only difference between the two
circuit types is the structure of the output circuitry.
Each quad-timer circuit contains four independent timer sections, where each section can generate a time
delay set by its own resistor and capacitor, external to
1-156
XR·558/559
The frequency of oscillation can be externally con·
trolled by applying a control,voltage to the control ter·
minal (pin 4). Since the control terminal is common to
all the timer sections, the duty cycle of the output
waveform is not effected by the modulation voltage;
thus the circuit can function as a variable·frequency,
fixed duty·cycle oscillator.
~
l.OAD
SWITCH
15581
,.
11
IS
,.
The frequency of oscillation increases as the voltage at
the control terminal (pin 4) is lowered below its opencircuit value.
15591
,.
Frequency of Oscillation
.,r-r---t=~----------~
At
Vee
=
R1 Cl
+ R2 C2
Figure 1. Generalized Test and Evaluation Circuit lor XR-55BI
XR-559 Quad Timer Circuits
."
MONOSTABLE OPERATION
In the monostable, or one-shot mode of operation, it is
necessary to supply two external components, a resis'
tor and a capacitor, for each section of the timer IC. The
timing terminals of those timer-sections not being used
can be left open-circuited. The time period is equal to
the external RC product. A plot of the timing period, T,
as a function of the external R·C combination is shown
in Figure 2.
OUTPUl2
1.n..rL
Figure 3. Typical Circuit Connection lor Astable Operation Using Two Timer-Sections. (Note: For XR-559, RL1
and RL2 are Connected Irom Outputs to Ground.)
IOOr---,---~--~----r_--~--~--~
OUTPUT STRUCTURE
10
...u:3
.....:
The XR-558 family of quad timers have "opencollector" NPN·type output stages. Each output can individually sink up to 100 mA of load current. However,
with more than one output active, the total current ca·
pability is limited by the power·dissipation rating of the
IC package (see Absolute Maximum Ratings). In the
normal operation of the circuit, each output will require
a pull-up resistor to + VCC. The output is normally
"low" state (i.e. sinking current) when the timer is at reset; and goes to "high" state during the timing cycle.
10
z
.
U
..:
..:
u
01
U
10 .... ·
10 m.
100 milO
__
I
The XR-559 family of quad timers have Darlington NPN
"emitter·follower" type outputs. Each output can
source up to 100 mA, during its "high" state. The total
amount of output current, available from all outputs, is
limited by the package power dissipation rating. For
normal operation of the circuit, a pull·down resistor is
required from each output to ground. The output of XR·
559 is normally low (i.e. at "off-state"), and goes to
"high" state when the circuit is triggered.
___d
~
__
~
__
~
_
'
__
1 0 nu
~
__
100..,.
~
0001 ____
~
001f---~--~--~~_,f---+---_r--;
10 ,
100 ,
TIMINe; PERIOD T
Figure 2. Timing Period, T, as a Function 01 External R-C
Combination (Note: T = 1.0 RC)
ASTABLE OPERATION
TRIGGER INPUTS
For astable, or free· running, operation of the quad timer
circuits, it is desirable to cross-couple two of the timer
sections on the chip, as shown in Figure 3. In this circuit configuration, the outputs of each section are
direct·coupled to the opposite trigger input. Thus, the
"high" and "low" half-periods of the output can be set
by the external R-C products, as R1Cl and R2C2, reo
spectively. The frequency of oscillation, and the output
duty,cycle are given as:
Each timer section of the quad-timer IC's has its own
trigger input. The trigger level is set at nominally + 1.5
V, and the trigger input is edge-triggered on the falling
edge of an input trigger pulse. In other words, for
proper triggering, the trigger signal must first go "high"
and then go "low". If both the trigger and the reset controls are activated, the reset control overrides the trigger input.
1-157
XR·558/559
RESET INPUT
an over-all timing variation of approximately 50:1. Since
the time period of each timer section is proportional to
the control voltage, all four timing periods can be simultaneously varied, and their relative ratios remain unchanged over the adjustment range.
The reset control (pin 13) is common to all four timer
section and resets all of the timer sections simultaneously.
The reset voltage must be brought below 0.8 V to insure
reset condition. When reset is activated, all the outputs
go to "low" state. While the reset is active, the trigger
inputs are inhibited. After reset is finished, the trigger
voltage must be taken high and then low to implement
triggering.
APPLICATIONS EXAMPLE
Sequential Timer:
Figure 4 shows a typical application for the quad-timer
in sequential timing application. For illustration purposes, the XR-558 is used in the example. Note that,
when triggered, the circuit produces four sequential
time delays, where the duration of each output is independently controlled by its own R-C time constant. Yet,
all four outputs can be modulated over a 50:1 range,
and remain proportional over this entire range. Since
each timer section is edge-triggered, the sections can
be cascaded by direct coupling of respective outputs
and trigger inputs.
CONTROL VOLTAGE
The control voltage terminal (pin 4) is common to all
four timer sections of the XR-558 or the XR-559. This
terminal allows the internal threshold voltages of all
four timer sections to be modulated, and thus provides
the control of the pulse-width or the duty-cycle of the
output waveforms. The range of this control voltage is
from 0.5 V to + Vee minus 1 Volt. This range provides
TRI(jGE~
R,
OUT"UT~L.._ _ _ _ _ __
(Jurf'UT
IH!titaN
~
OUTPUT]
}---AUJ
CONTHOL
UI'TO~
OUTPUT.
VOl TACit
1 RAI'\jIif.---/
I7'L
NOTE
t,. t,. '3. 14 remain proportional over entire adi. range
(b1 Timing Waveforms
la,'Circuit Connection
Figure 4, Using the XR-558 as a Four-Stage Sequential Timer with VoRage Control Capability
VCOItTIIIOLo-H--I-...J
XR-558 EQUIVALENT SCHEMATIC
XR-559 EQUIVALENT SCHEMATIC
1-158
XR·2556
Dual Timing Circuit
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-2556 dual timing circuit contains two independent 555-type timers on a single monolithic chip. Each
timer section is a highly stable controller capable of
producing accurate time delays or oscillations. Independent output and control terminals are provided for
each section as shown in the functional block diagram.
In the monostable mode of operation, the time delay for
each section is precisely controlled by one external resistor and one capacitor. For astable operation as an
oscillator, the free-running frequency and the duty cycle of each section are accurately controlled with two
external resistors and one capacitor.
The XR-2556 may be triggered or reset on falling waveforms. Each output can source or sink up to 200 mA or
drive TIL circuits. The matching and temperature tracking characteristics between each timer section of the
XR-2556 are superior to those available from two separate timer packages.
ORDERING INFORMATION
FEATURES
Replaces Two 555-Type Timers
TIL Compatible Pinouts (Gnd-Pin 7, VCC-Pin 14)
Timing from Microseconds Thru Hours
Excellent Matching Between Timer Sections
Operates in Both Monostable and Astable Modes
High Current Drive Capability (200 mA each output)
TIL and DTL Compatible Outputs
Adjustable Duty Cycle
Temperature Stability of 0.005%/oC
Normally ON and Normally OFF Outputs
Operating Temperature
- 55°C to + 125°C
O°C to +70°C
O°C to +70°C
SYSTEM DESCRIPTION
In the monostable (one shot) mode, timing is determined by one resistor and capacitor. Astable operation
(oscillation) requires an additional resistor, which controls duty cycle. An internal resistive divider provides a
reference voltage of 2/3 VCC, which produces a timing
interval of 1.1 RC. As the reference is related to VCC,
the interval is independent of supply voltage; however,
for maximum accuracy, the user should ensure VCC
does not vary during timing.
Missing Pulse Detection
Pulse-Width Modulation
Frequency Division
Clock Synchronization
Pulse-Position Modulation
The output of the XR-2556 is high during the timing interval and pulls low at timeout. It is triggered and reset
on falling waveforms. The control voltage inputs (Pins 4
and 10) may serve as pulse width modulation pOints.
Matching between sections is typically better than
0.2% initially with temperature drift tracking to ± 10
ppm/DC.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Ceramic Dual-In-Line
Derate above TA = 25°C
Plastic Dual-In-Line
Derate above TA = 25°C
Storage Temperate Range
Package
Ceramic
Ceramic
Plastic
The XR-2556 is a high output dual timing circuit similar
to the popular 555-type timer, capable of both monostable and astable operation with timing intervals ranging
from low microseconds up through several hours. Timing is independent of supply voltage, which may range
from 4.5 V to 18 V. The output stage can source or sink
200 mAo Each timing section is fully independent.
APPLICATIONS
Precision Timing
Pulse Generation
Sequential Timing
Pulse Shaping
Time Delay Generation
Clock Pattern Generation
Part Number
XR-2556M
XR-2556CN
XR-2556CP
18 volts
750 mW
5 mW/oC
625mW
5 mW/oC
-65°C to +150°C
For low voltage and/or low power drain applications
consider the XR-L556.
.
1-159
XR·2556
ELECTRICAL CHARACTERISTICS
Test Conditions: (Each timer section, TA = 25°C, VCC
XR-2556M
PARAMETERS
Supply Voltage
MIN
TYP
4.5
=
+ 5V to + 15V, unless otherwise specified.)
XR-2556C
MAX
MIN
18
4.5
TYP
MAX
UNITS
FIGURE
16
V
7
Supply Current
(Each Timer Section)
3
10
5
12
3
10
6
15
mA
mA
6
20
10
24
6
20
12
30
mA
mA
Timing Error
Initial Accuracy
Drift with Temperature
Drift with Supply
Voltage
0.5
30
0.05
2.0
100
0.1
1.0
50
0.05
%
ppm/oC
%/V
Threshold Voltage
2/3
2/3
xVCC
1.67
5.0
V
V
Total Supply Current
(Soth Timer Sections)
CONDITIONS
7
low State Output,
Note 1
Vee = 5V,Rl = 00
VCC = 15V, Rl = 00
7
low State Output
VCC = 5V, Rl = 00
VCC = 15V, Rl = 00
RA, RS = 1 kD to 100kD
Note 2, C = 0.1/LF
13
12
Trigger Voltage
1.45
4.8
Trigger Current
Reset Voltage
1.9
5.2
0.5
0.4
Reset Current
0.7
0.5
1.0
0.4
0.1
Threshold Current
Control Voltage level
1.67
5.0
2.90
9.6
0.7
0.1
0.25
3.80
10.4
0.10
0.25
2.60
9.0
VCC
Vee
= 5V
= 15V
/LA
1.0
0.1
3.33
10.0
6
V
mA
0.1
0.25
3.33
10.0
4.00
11.0
Note 3
/LA
VCC = 5V
VCC = 15V
Output Voltage Drop
(low)
9
0.25
0.35
0.1
0.4
2.0
2.5
0.25
0.75
2.5
V
V
11
0.1
0.4
2.0
2.5
0.15
0.5
2.2
V
V
V
V
Output Voltage Drop
(High)
8
3.0
13
3.3
13.3
2.75
12.75
3.3
13.3
V
V
12.5
12.5
V
Rise Time of Output
100
100
nsec
Fall Time of Output
100
100
nsec
0.2
%
±10
ppm/oC
Matching Characteristics
Initial Timing
Accuracy
Timing Drift with
Temperature
Note
Note
Note
Note
1:
2:
3:
4:
Vee = 5V
Isink = 8.0 mA
Isink = 5.0 mA
VCC = 15V
Isink = 10 mA
Isink = 50 mA
Isink = 100 mA
Isink = 200 mA
Isource = 100 mA
Vee = 5V
VCC = 15V
Isource = 200 mA
VCC = 15V
Note 4
0.2
±10
0.6
Supply current when output is high is typically 1.0 mA less.
Tested at VCC = 5V and VCC = 15V.
This will determine the maximum value of RA + RS for 15V operation. The maximum total R = 20 meg-ohms.
Matching characteristics refer to the difference between performance characteristics of each timer section.
1·160
XR·2556
PRINCIPLES OF OPERATION
Figure 4 shows the waveforms during the monostable
timing cycle. The top waveform is the trigger pulse; the
Figure 2 is the functional block diagram for each timer
section of the XR-2556. These sections share the same
V+ and ground leads, but have independent outputs
and control terminals. Therefore, each timer section
can operate independently of the other. The timing cycle of each section is determined by an external
resistor-capacitor network.
~~~--~---,--ov+
T= 1.1 RAe
L
J
5
OUTPUT 0---<>--1
I-T-j
U
MONOSTABLE (ONE-SHOT) OPERATION
When operating either timer section of the XR-2556 in
the monostable mode, a single resistor and a capacitor
are used to set the timing cycle. The discharge and
threshold terminals are also interconnected in this
mode, as shown in Figure 3.
1/2
XR.2556
3
...---0.........,
TRIGGER 0---<>2
__-i
Figure 3. Monostablo (One-Shot) Circuit
Referring to Figure 2, monostable operation of the
XR-2556 is explained as follows: the external timing capacitor
is held discharged by the internal transistor,
To. The internal flip-flop is triggered by lowering the trigger levels (pins 2 or 12) to less than 1/3 Vee. The circuit
triggers on a negative-going slope. Upon triggering, the
flip-flop is set to one side, which releases the short circuit across the capacitor and also moves the output
level at pins 1 or 13 toward Vee. The voltage across the
capacitor, therefore, starts increasing exponentially
with a time constant T = RA. A high impedance comparator is referenced to 2/3 Vee with the use of three
equal interval resistors. When the voltage across the
capacitor reaches this level, the flip-flop is reset, the
capacitor is discharged rapidly, and the output level
moves toward ground, and the timing cycle is completed.
e
CONTROL
VOLTAUE
t40R 101
Vee
14
Figure 4. Monostable Waveforms
Top: Trigger Input
Middle: Exponential Ramp across Timing Capacitor
Boltom: Output Logic Level
100r---~--'----'--7T--~--~r-~
10
u:
.3
w
(J
z
1.0
"e:;
a..
""ti
l-
Figure 2. Functional Diagram of One Timer Section
(J
Once the circuit is triggerd it is immune to additional
trigger inputs until the present timing-period has been
completed. The timing-cycle can be interrupted by using the reset control (pins 6 or 8). When the reset control is "low", the internal discharge transistor is turned
"on" and prevents the capacitor from charging. As long
as the reset voltage is applied, the digital output level
will remain unchanged, i.e. "low". The reset pin should
be connected to V + when not used to avoid the possibility of false triggering.
0.01
O.OO11·';:0-1J-'-:10~0~"-'--:"1.~0'-m-'-1::-:0~m-'-:1~oo=-m-'--::-1.-!:-0-.-::-:10!-'--::-:'.100.
TIMING PERIOD, T (sac.)
Figure 5. Timing Period, T, as a Function of External R-C
Network
1-161
XR·2556
TYPICAL CHARACTERISTICS (Each Timer Section)
ASTABLE (SELF-TRIGGERING) OPERATION
middle is the exponential ramp across the timing capacitor. The bottom waveform is the output logic state
(at pins 1 or 13) during the timing cycle. For proper operation of the circuit, the trigger pulse-width must be
less than the timing period.
For astable (or self-triggering) operation, the correct circuit connection is shown in Figure 15. The external capacitor charges to 2/3 Vee through the parallel combination of RA and RS, and discharges to 1.3 Vee
through RS. In this manner, the capacitor voltage oscillates between 1/3 Vee and 2/3 Vee, with the exponential waveform as shown in Figure 16. The output level at
pin 1 (or 13) is high during the charging cycle, and goes
low during the discharge cycle. The charge and the discharge times are independent of supply voltage. The
oscillations can be keyed "on" and "off" using the reset controls (pin 6 or 8)
The duration of the timing period, T, during which the
output logic level is at a "high" state is given by the
equation:
T = 1.1 RAe
This time delay varies linearly with the choice or RA
and as shown by the timing curves of Figure 5.
e
16
tj
IlH
~~ -~ 1
-+
o ~' -----.'-
OL,......I.~~~L-.~,0......l.~-'--~"
03
VTlnllll! MINIMlJM TRIGGER VOLTAca
IX Vee Vlld
04
lOll
'SOURCF P1IA)
Figure 7. Supply Current (Both Timer
Sections)
Figure 6. Trigger Pulse Width
Hl
bO
Vs. SLH'Pl V VOL T Alil IVtlc)
Figure B. High Output Voltage
r--r-r...,-,..---,--r--r-T'T-'
">
~
6
>
~
~
"
0
>
0
>
01
o 01 '--......I.......I.~L-.......I._-'--'-.w._-'
1
10
70
!:IO
100
1tl
ISIN",·IIllAI
Figure 10. Low Output Voltage
Vee = 10 Vdc
Figure 9. Low Output Voltage
Vee = 5.0 Vdc
I DIS
,..--,.-.,-r--'--"'--"T"-r---.
1015
C
N
~
~
~
1000
~
--
~
;:
>
~
~ 0995
~
-
--
100;, - - - - - -
--,--
1 000 f--f----
--
-- --
--
f--i------ - - - -
_-e
0990
t-'----1=-t-..!::,----,---I-
l""-t--t-0995 J--+--\-+--+-\-- 1--1--
098~
10
"
Vs SUPPl V VOLTAGE IVttcl
Figure 12. Delay Time vs. Supply
Voltage
20
0990
f--+---+-+--+-i---,--
o !}a~ ~15--;&'::'0~-";--!-0-'~25~',:-::0--:',~&-.~'00::-:"1:?~
T A' AMBIENT
300
:t;:
>
~
2&0
200
c
Q
0
100
Figure 11. Low Output Voltage
Vee = 15 Vdc
r-"T"-r-.,--r-,..---,---r--.
1010 ---- - C
N
;t
~
~
~o
:/0
'SINK- (mAl
lEMPERATU~E
(
c)
Figure 13. Delay Time vs. Temperature
1-162
z
0
;:
1&0
~
";;:
~
100
_R 50
01
03
VTtm.nl MINIMUM TRIGGER VOL TAGE
IX Vee
V,ld
Figure 14. Propagation Delay VS.
Trigger Voltage
04
XR·2556
The charge time (output high) is given by:
t1
= 0.695 (RA +
To obtain the maximum duty cycle, RA must be as small
as possible; but it must also be large enough to limit the
discharge current (pin 5 current) within the maximum
rating of the discharge transistor (200 mA).
RB)C
The discharge time (output low) by:
DESCRIPTION OF CIRCUIT CONTROLS
t2 = 0.695 (RB)C
OUTPUT (PINS 1 or 13)
Thus the total period is given by:
The output logic level is normally in a "low" state, and
goes "high" during the timing cycle. Each output of the
XR·2556 is a "totem pole" type capable of sinking or
sourcing 200 mA of load current (see Figure 18).
T = t1 + t2 = 0.695 (RA + 2RB)C
The frequency of oscillation is then:
f =
.1.
=
T
100
1.44
and
(RA + 2RB)C
may be easily found as shown in Figure 17.
The duty cycle, D, is given by:
RB
D = ---''''--
RA + 2RB
.....-o v+
r----~~-
1..n..f
5
OUTPUT
1/2
XR·2556
O.Oll----+--~~__IPIt:___+""'\;:__t_~_,
RS
0.001 L---:-L:----:-:---:-:~--::-::~--:;:;;--_;_;;;100K
0.1
1.0
10
CONTROLO_~4--1
INPUT
f. FREE-RUNNING FREQUENCY (Hz)
f=
1.46
(R A
+ 2RSic
Figure 17. Free Running Frequency as a Function of
External TIming Componants
7
RS
DUTY CYCLE = RA + 2RS
Figure 15. Astable (Free-Running) Circuit
Figure 18. Circuit Schematic-1/2 of XR-2256
TRIGGER (PINS 2 OR 12)
The timing cycle is initiated by lowering the dc level at
the trigger terminal below 113 VCC. Once triggered, the
circuit is immune to additional triggering until the timing
cycle is completed.
THRESHOLD (PINS 3 or 11)
The timing cycle is completed when the voltage level at
the trigger terminal reaches 2/3 VCC. At this point,
Comparator #2 of Figure 2 changes state, resets the in·
ternal flip·flop, and initiates the discharge cycle.
Figure 16. Astable Waveforms
Top: Output Waveform
Bottom: Waveform Across Timing Capacitor
1·163
XR·2556
...----.---..--..,..........:.-r---........--..,
rately in the monostable mode to produce respective
time delays of T1 and T2, where:
2.0
...z
>'
T1
J
1.5
= 1.1
R2C2
In this application, the output of one timer section
(Timer 1) is capacitively coupled to the trigger terminal
of the second, as shown in Figure 21. When Timer 1 is
triggered at pin 2, its output at pin 1 goes "high" for a
time duration T 1 = 1.1 R1 C1. At the end of this timing
cycle, pin 1 goes "low" and triggers Timer 2 through
the capacitive coupling, CC, between pins 1 and 12.
Then, the output at pin 13 goes "high" for a time duration T2 = 1.1 R2C2. In this manner, the unit behaves as
a "delayed one-shot" where the output of Timer 2 is
delayed from the initial trigger at pin 2 by a time delay
of T1.
w
0
w
::E
;::: 1.0
0
w
N
~
«
::E
ex:
z
1.1 R1C1 and T2
SEQUENTIAL TIMING (DELAYED ONE-SHOT)
«
....J
0
=
0.5
v'
MODULATION VOLTAGE AT CONTROL TERMINAL
(PINS 4 OR 101
Figure 19. Normalized Time Delay vs. Modulation Voltage
CONTROL OR FM (PINS 4 OR 10)
The timing cycle or the frequency of oscillation can be
controlled or modulated by applying a dc control voltage to pin 4 or 10. This terminal is internally biased at
2/3 Vee. The control signal for frequency modulation or
pUlse-width modulation is applied to this terminal. Figure 19 shows the variation of the timing period, T, as a
function of dc voltage at the control terminal. When not
in use, the control terminals should be ac grounded
through 0.01 p.F decoupling capacitors.
Figure 20. Generation of Two Independent Time Delays
...-------r-ov·
DISCHARGE (PINS 5 OR 9)
",
",
c,
c,
This terminal corresponds to the collector of the discharge transistor, To, of Figure 2. During the charging
cycle, this terminal behaves as an open-circuit; during
discharge, it becomes a low impedance path to ground.
~
RESET (PINS 6 OR 8)
~
11
Rl
v'
OUTPUT ;:2
1f
The timing cycle can be interrupted by grounding the
reset terminal. When the reset signal is applied, the
output goes "low" and remains in that state while the
rest voltage is applied. When the reset signal is reo
moved, the output remains "loW" until re-triggered.
When not used, the reset terminals should be connect·
ed to VCC in order to avoid any possibility of false triggering. When the timing circuits are operated in the
astable mode, the reset terminals can be used for "on"
and "off" keying of the oscillations. (See Figure 22).
l-
TRIGGER
0.01 "F
J1.
~
OU~~UT
T'-1
--IL
T,+ ., T,
~
0.01 "F
T, = 1.1 R,e,
30K
v'
T2'" 1.1 R 2C2
0,001 j.lF
Cc
Figure 21. Sequential Timing
KEYED OSCILLATOR
One of the timer sections of the XR·2556 can be operated in its free-running mode, and the other timer section
can be used to key it "on" and "off". A recommended
circuit connection is shown in Figure 22. Timer 2 is
used as the oscillator section, and its frequency is set
by the resistors RA, RB and the capacitor C2. Timer 1 is
operated as a monostable circuit, and its output is con·
nected to the reset terminal (pin 8) of Timer 2.
APPLICATIONS INFORMATION
INDEPENDENT TIME DELAYS
Each timer section of the XR-2556 can operate as an independent timer to generate a time delay, T, set by the
respective external timing components. Figure 20 is a
circuit connection where each section is used sepa-
1-164
XR·2556
When the circuit is at rest, the logic level at the output
of Timer 1 is "low"; and the oscillations of Timer 2 are
inhibited. Upon application of a trigger signal to Timer
1, the logic level at pin 1 goes "high" and the oscillator
section (Timer 2) is keyed "on". Thus, the output of
Timer 2 appears as a tone burst whose frequency is set
by RA, RS and C2, and whose duration is set by R1 and
C1 of Figure 22.
FREQUENCY DIVIDER
If the frequency of the input is known, each timer section of the XR-2556 can be used as a frequency divider
by adjusting the length of its timing cycle. If the timing
interval T 1 (= 1.1 R1C1) is larger than the period of the
input pulse trigger, then only those input pulses which
are spaced more than 1.1 R1C1 will actually trigger the
circuit.
RI
t
Figure 23. Frequency Divider Waveforms
Top: Input Pulse Train (f = 5 kHz)
Middle: Waveforms Across Timing Capacitor
BoHom: Output Waveform (f = 1 kHz)
Re
cl
TIMER
#1
TIMER
#2
C2
11
~
12
v,
RL
13
1J
7
TRIGGER
10
fREQUENCY DIVIDER AND PULSE SHAPER
Frequency division can be performed by 112 of the
XR-2556. The remaining timer section can be used as a
"pulse-shaper" to adjust the duty cycle of the output
waveform. As seen in Figure 24, Timer 1 is used as the
frequency divider section and Timer 2 is used as the
pulse-shaper.
OUTPUT
8
v'
v'
20K
Figure 22_ Keyed Oscillator
The output frequency is equal to (1IN) times the input
frequency. The division factor N is in the range:
( l_
Tp
INPUT
1) < N< l
'·'IIN
Tp
where Tp is the period of the input pulse signal.
v·C>-"""""......~---_...J
Figure 23 shows the circuit waveforms for divide-by-five
operation for one of the timer sections of the XR-2556.
In this case, the timing period of the circuit is set to be
approximately 4.5 times the period of the input pulse.
Figure 24. Frequency Divider and Pulse-Shaper
The output of Timer 1 (pin 1) triggers Timer 2, which
produces an output pulse whose frequency is the same
as the output frequency of Timer 1, and whose duty cycle is controlled by the timing resistor and capacitor of
Timer 2. The duty cycle of the output of Timer 2 (pin 13)
can be adjusted from 1 % to 99 % by varying the value
of R2.
.
Since the two timer sections of the XR-2556 are electrically independent, each can be used as a frequency divider. Thus, if the trigger terminals of both timer sections are connected to a common input, the XR-2556
can produce two independent outputs at frequencies f1
and f2:
f1
= fslN1
and f2
Figure 25 shows the circuit waveforms in this application. The top waveform is the input signal of frequency
fs applied to the trigger input (pin 2) of Timer 1. The middle waveform is the output of Timer 1 for divide-by-three
operation; and the bottom waveform is the pulseshaped output obtained from Timer 2 (pin 13).
= fslN2
where N 1 and N2 are the division factors for respective
timer sections, set by external resistors and capaCitors
at pins (3, 5) and (9, 11).
1-165
XR·2556
Frequency =
(RA
Duty Cycle =
1.44
2RS)C1
+
(1.6) R2C2
---'----'---=-=-(RA
+ 2RSC1)
OSCILLATOR WITH SYNCHRONIZED OUTPUTS
The circuit of Figure 26 can also be used as an oscillator with synchronized multiple frequency outputs.
Timer 1 generates an output at frequency f1 at pin 1, as
set by resistor RA, RS, and C1. Timer 2 is used as a frequency divider by setting its timing cycle, T2, to be larger than the period of Timer 1 (see section on frequency
division). The resulting output of Timer 2 (pin 13) is at
frequency f2 given as:
f2 = h/N
Figure 25. Frequency Divider and Pulse-Shaper Waveforms
Top: Input Signal (Is = 9 kHz)
Middle: Output at Pin 1 lor oivide-by-3
Bottom: Variable Duty Cycle Output at Pin 13
v+
where N is the divider ratio set by the external R-C networks as described by Figures 23 and 24.
PULSE-WIDTH MODULATION
For pulse-width modulation, one-half of the XR-2556 is
connected as shown in Figure 27. The circuit operates
in its monostable mode and is triggered with a continuous pulse train. Output pulses are generated at the
same rate as the input pulse train, except the output
pulse-width is determined by the timing components R1
and C1.
y+
DUTY CYCLE
ADJ.
OUTPUT
PWM
OUTPUT.i
FREQUENCV • fRA
~::~)C1
1/2
XA·2556
(1.6IRM
CLOCK INPUT o--- 7V) and small values of timing capacitor (C < o. 1 p.F) the pulse-width of the time-base output
at pin 14 may be too narrow to trigger the counter section. This can be corrected by connecting a 300 pF capaCitor from pin 14 to ground.
To
t1 a
.··
!
!,
~
·
= NT = NRC
where T = RC is the time-base period as set by the
choice of timing components at pin 13 (See Figure 9). N
is an integer in the range of:
r· \
~
ui
n<'. .
Figure 12. Free-running Operation
Self-Trlugered When Power
Supply Is Turned On
OPERATION WITH EXTERNAL CLOCK
]tllESfT
The XR-2242 can be operated with an external clock or
time-base, by disabling the internal time-base oscillator
and applying the external clock input to pin 8. The internal time-base can be de-activated by connecting a 1 KO
resistor from pin 7 to ground. The counters are triggered on Ihe negative-going edges of the external clock
pulse. For proper operation, a minimum clock pulse
amplitude of 3 volts is required. Minimum external
clock pulse width must be ~ 1 ILS.
Figure 14. Sequential Timing Using lWo XR-2242 Timer
Circuits
CASCADED OPERATION:
a) Ultra-Long Delay Generation:
Ultra-long time delays, up to one-year duration, can be
generated by cascading two XR-2242 timers as shown
in Figure 13. In this configuration, the counter section
of Unit 2 is cascaded with the counter output of Unit 1,
to provide a total count of 32,640 clock cycles before
the output (pin 3 of Unit 2) changes state. In the appli-
EQUIVALENT SCHEMATIC DIAGRAM
1-179
XR·2243
Micropower Long Range Timer
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-2243 is a monolithic Timer/Controller capable
of producing ultra-long time delays from micro-seconds
to days. Two timing circuits can be cascaded to generate time delays or timing intervals up to one year. The
circuit is comprised of an internal time-base oscillator,
an 11 -bit binary counter and a control flop-flop. For a
given external R-C network connected to the timing terminal, the circuit produces an output timing pulse of
1024 RC. If the two circuits are cascaded, a total time
delay of (1024)2 or 1,048,576 RC is obtained.
The XR-2243 long range timer was designed for low
power operation. Its supply current requires less than
100 p.A in standby or reset mode. Normal operation requires less than 1mAo
The timing cycle is initiated by applying a positive going
pulse to the trigger input, Pin 6. The time-base oscillator generates timing pulses with its period, T, equal to 1
RC. These clock pulses are counted by the binary
counter section. The timing cycle is completed when a
positive-going reset pulse is applied to Pin 5.
High Accuracy: 0.5%
Excellent Supply Rejection
Monostable and Astable Operation
Micro Power Consumption-Standby Operation
Low Power Consumption-Normal Operation
In monostable timer applications, the output terminal
(Pin 3) is connected to the reset terminal, Pin 5. In this
manner, after 1024 clock pulses are counted, this output goes to "high" state and resets the circuit, thus
completing the timing cycle. Therefore, after triggering,
the output at Pin 3 will produce a total timing pulse of
1024 RC before the circuit resets itself to complete the
timing cycle. During the timing interval, the secondary
output at Pin 2 produces a square-wave output with the
period of 2 RC.
ABSOLUTE MAXIMUM RATINGS
If the output at Pin 3 is not connected back to the reset
terminal, the circuit continues to operate in an astable
mode, subsequent to a trigger input.
18 Volts
Power Supply
Power Dissipation (package limitation)
385 mW
Ceramic Package
300 mW
Plastic package
2.5 mW/oC
Derate above + 25°C
Temperature Range
Operating
XR-2243C
O°C to + 70°C
- 65°C to + 150°C
Storage
APPLICATIONS
ORDERING INFORMATION
Long Delay Generation
Sequential Timing
Precision Timing
Ultra-Low Frequency Oscillator
Battery Powered Applications
Part Number
Package
XR-2243CN
XR-2243CP
Ceramic
Plastic
Operating Temperature
O°C to
O°C to
+ 70°C
+ 70°C
PRINCIPLES OF OPERATION
FEATURES
The ultra-long time delay micropower timer, in simplest
block diagram terms, consists of a timing section followed by a counter section and a control flip-flop.
High Output Current Sink Capability
Timing from Micro-seconds to Days
Wide Supply Range: 2.2V to 15V
TTL and DTL Compatible Outputs
The main functional portion of the circuit is the time
base section. It is a relaxation oscillator whose period
H80
XR·2243
ELECTRICAL CHARACTERISTICS
Test Conditions: See Figure 3, V+ = 5V, TA = 25°C, R = 22 kD, C = 0.047 pF, unless otherwise noted.
XR-2243C
PARAMETERS
Supply Voltage
MIN
Supply Current
Standby
Operating
Time Base Section
Timing Accuracy·
Temperature Drift
Supply Drift
Maximum Frequency
Recommended Range of
Timing Components
Timing Resistor, R
Timing Capacitor, C
Trigger/Reset Controls
Trigger
Trigger Threshold
Trigger Current
Impedance
Response Time
Reset
Reset Threshold
Reset Current
Impedance
Response Time
Counter Section
Max. Toggle Rate
Input:
Impedance
Threshold
Output:
Sink Current
Leakage Current
TYP
MAX
UNIT
15
V
45
80
250
900
750
1250
95
135
415
1000
900
1500
pA
pA
0.5
80
150
300
0.30
35
3
125
225
650
1.0
2.7
25
0.005
0.005
pA
pA
pA
pA
%
ppm/DC
ppm/DC
ppm/DC
CONDITIONS
VCC
VCC
VCC
VCC
VCC
Vee
=
=
=
=
=
=
2.7V VTR = OV VRS = 5V
5V
15V
5V VTR = 5V VRS = OV
2.7V
15V
VCC
Vee
Vee
VCC
=
=
=
=
2.7V VTR = 5V VRS = OV
5V
15V O°C :S TA :S 70°C
8V
%N
kHz
10
1000
mD
pF
1.4
22
25
2.0
30
V
1.4
22
25
2.0
30
100
250
Measures at Pin 11, VRS = 0
pA
VRS = 0, VTR = 2V
kD
V
pA
VTR = 0, VRS = 2V
kD
kHz
15
1.4
kD
V
10
0.01
mA
pA
.,
.,
.,
Figure 1. Simplified Circuit Schematic
1-181
See Figure 4, V + = 5V
VRS = 0, VTR = 5V
Measured at Pin 14
VOL:S 0.4V
VOH :S 15V
XR·2243
a divide by 2 block. With eleven stages, one could create delays of 1024 Re in a monostable mode of operation. The counters change state on the falling edge of
the clock pulses.
of oscillation is determined by the external Rand e values. The timing section is followed by an 12L counter,
which consists of eleven binary stages, with high current drive capability output stages from the first and the
last. A third subsection of the circuit is the control logic
circuit consisting of a flip-flop that is set and reset by
Pins 6 and 5, respectively. This section controls the resetting of all counter stages, and starting the timing cir·
cuit upon application of a positive-going trigger pulse.
The control logic also activates the power shut down
circuit when a reset pulse is received, or when the timing cycle is completed. The power shut down circuit
turns off the bias line to the time base and 12L counters
to reduce the standby power.
When the trigger pulse is applied, the internal power
line which is supplying voltage for 12L circuitry (12LVec)
is set up first, a Schmitt trigger circuit with a built in delay ensures the application of an internal set pulse,
right after the power for the 12 section is made available. The counters are all set to "1" and are ready to
count with the incoming falling edges of clock impulses.
OUTPUT SECTIONS (Pins 2 and 3)
CONTROL FLIP-FLOP
The output sections are designed such that they can
handle 10mA load currents @ VOL = 300mV. Both of
the transistors in this section are operating in a nonsaturated mode because of the clamping action. This
ensures faster operation and also decreases the need
of high base drive at full load operation.
The logic flip-flop circuit controls the time/counter, as
well as the internal power, to reduce standby current
consumption to approximately 100,.A. Upon command,
by a positive-going trigger pulse applied to Pin 6, the
control logic circuit will first establish the upper and
lower threshold voltages and then setup all internal current sources, biasing the time base and counter sections.
The timing cycle for the circuit is initiated by applying a
positive-going trigger to the set, or trigger pin, (Pin 6) of
the device. The trigger pulse actuates the time base oscillator, enables the counter section, and sets the outputs to "low" state. The time base oscillator generates
timing pulses with its period, T = 1Re. These timing or
clock pulses are counted by the binary counter section.
The timing cycle is completed when a positive-going reset pulse is applied to the reset pin (Pin 5).
The circuit will automatically reset itself when power is
first applied. Once triggered, the circuit is immune to
additional trigger pulses until it is reset. A reset pin terminates the timing cycle by resetting the internal logic
and shuts off the internal bias circuitry.
TIME BASE OSCILLATOR
....---------_--o.vcc
The time base oscillator is a simple exponential ramp
type timer circuit. The timing components, Rand e, are
external to the chip. The operation of such an oscillator
can be described as follows: when the circuit is at rest
the flip-flop is latched in its reset state, the discharge
transistor is "off", and the external capacitor, e, is fully
charged to a voltage approximately equal to Vee.
When the circuit is triggered, the flip-flop is unlatched
and set, which causes the discharge transistor to turn
"on" and discharge e rapidly. When the voltage across
e discharges to the voltage level Vth _, the upper comparator changes state, resets the flip-flop and turns the
discharge transistor "off". Then, e charges toward
Vee with a time constant set by the external Rand e.
When the voltage across it reaches the upper threshold, Vth +, the comparator changes state, sets the flip·
flop again, and discharges e back to the lower threshold level, Vth _. In this manner, the circuit continues to
oscillate with the voltage level across e exponentially
rising to Vth + ' then rapidly decaying to Vth _ and then
repeating this cycle until the timing period ends.
IoTo-l
~
OUTPUT
11
L-_ _- 10V
Sweep Input open circuit
I - General Characteristics
Supply Voltage:
Single Supply
Split Supply
8
±5
Supply Current
8
Frequency Stability:
Power Supply
Temperature
Frequency Sweep Range
Output Swing:
Single Ended
Differential
Output Dill. Offset ,Voltage
7:1
10:1
2
4
3
6
0.1
Amplitude Control Range
Buffer Amplilier Output
Resistance
Output Current Swing
See Figure 7
Vpp
Vpp
Vdc
Measured at pin 1 or 2
Measured across 1 and 2
Measured across 1 and 2
60
dB
Controlled by Rq(see Figure 1)
0.4
RL ~ 7500
50
ohms
±6
±10
mA
2
2
4
3
2.5
MHz
Vpp
%
Measured at Pin 11
Sl, S3 closed, S2 open
closed S2 open
II - Output Wavelorms
Sinusoidal:
Upper Frequency Limit
Peak Output Swing
Distortion (THD)
Triangle:
Peak Swing
Non·Linearity
Asymmetry
4
2
4
±1
±1
Vpp
%
%
Measured at Pin 11
Sl, S2 open, S3 closed
I ~ 10 kHz
Sawlooth:
Peak Swing
Non·Linearity
2
3
1.5
Vpp
%
See Figure 1, S2 closed;
S2 and S3 closed
Ramp:
Peak·Swing
Non·Linearity
1
1.4
1
Vpp
%
See Flgu re 1, S2 and S3 open
pin 10 shorted to pin 15
0.5
0.7
q±l
:<0
20
Vpp
%
ns
ns
See Figure 1, S2 and S3 open,
pin 10 shorted to pin 12
10 pF connected Irom pin 11
10 ground
Vpp
%
ns
ns
See Figure 3, S2 open
3
3
80
60
Vpp
Vpp
ns
ns
See Figure 3, S2 closed
See Figure 3, S2 closed
20·80
%
Adjustable (see Figure 6)
0·100
0.5
1.0
%
%
%
See Figure 2
for 30% modulation
52
dB
1< 1 MHz
0.3
%
See Figure 2 (± 10 frequency
deviation)
Squarewave (Low Level):
Output Swing
Duty Cycle Asymmetry
Rise Time
Fall Time
Squarewave (High Level):
Peak Swing
Duty Cycle Asymmetry
Rise Time
Fall Time
Pulse Output:
Peak Swing
Rise Time
Fall Time
Duty Cycle Range
2
2
2
3
±1
80
60
±4
±4
10 pF connecled from pin 11
to ground
III - Modulation Characteristics (sine, triangle and squarawava):
Amplitude Modulation:
Double Sideband
Modulation Range
Linearity
Sideband Symmetry
Suppressed Carrier
Carrier Suppression
Frequency Modulation:
Distortion
1-189
XR·205
DESCRIPTION OF CIRCUIT CONTROLS
TEST CIRCUITS
(Refer to functional block diagram)
. - - - - - - - 0 .n..n...
TIMING CAPACITOR (PINS 14 AND 15)
The oscillator frequency is inversely proportional to the
value of the timing capacitor, Co. connected between
pins 14 and 15. With the sweep input open circuited. fre·
quecy fo can be approximated as: fo = 400/Co where fo
is in Hz and Co is in microforads. (See Figure 4.)
,.
MODULATOR V-INPUTS (PINS 5 AND 6)
- These inputs are normally connected to the oscillator
outputs. For sinewave or trianglewave outputs, they are
dc coupled to pins 14 and 15 (see Figure 1); for high·
level squarewave or pulse output, ac coupling is used
as shown in Figure 3.
BUFFER OUTPUT
Figure 1. Test Circuit for Single-Supply Operation
MODULAR X-INPUTS (PINS 3 AND 4)
Modulator output (at pins 1 or 2) is proportional to a dc
voltage applied across these inputs . (see Figure 5).
These inputs can be used for amplitude modulation or,
as an output amplitude control. The phase of the output
voltage is reversed if the polarity of the dc bias across
pins 3 and 4 is reversed; therefore these inputs can be
used for phase-shift keyed (PSK) modulation.
••v
-.v
MODULATOR OUTPUTS (PINS 1 AND 2)
All of the high level output waveforms are obtained at
these terminals. The output waveforms appear differen·
tially between pins 1 and 2. The terminals can, there·
fore, be used for either in·phase or out·of·phase out·
puts. Normally, a 15 KO load resistor should be connected between these terminals to prevent the output
from saturating or clipping at large output voltage
swings.
AMPLITUDE MODULATION
INPUT
5,
l----~-"----'
1-0-,--0 '"V'v
lSK
~~---r--'---rr-o-r+-----o
OR
I\.I'v
LOW LEVEL SQUAREWAVE OUTPUT (PIN 12)
Figure 2. Test Circuit for Split-Supply Operation and AM/FM
Modulation
SWEEP OR
SYNC
INPUT
The output at this pin is a symmetrical squarewave with
0.7V amplitude and 20 ns rise time. It can be used di·
rectly as an output waveform. or amplified to a 3 Vpp
signal level using the modulator section of the XR·205
as an amplifier (see Figure 3).
11(
I"
SWEEP OR FM INPUT (PIN 13)
The oscillator frequency increases linearly with an in·
creasing negative voltage, Vs. applied to this terminal.
Normally a series resistor, Rs (Rs ... approx. 1 KO) is
connected in series with this terminal to provide current
limiting and linear voltage-to-frequency transfer characteristics. The frequency derivation (for any given modulation level) is inversely proportional to Rs. Typical
sweep characteristics of the circuit are shown in Figure
7. For proper operation of the circuit with Rs = 1 KO,
the sweep voltage. Vs , must be within range: (Vso - 6)
> Vs > (Vso + 1) where Vso is the open circuit voltage
at pin 13. The frequency of oscillation can also be synchronized to an external source by applying a sync
..
,
...n.n...
-r-u-
'-----o.....JL.JL
SOK
OUTPUT
RQ
AMPlITUOE ' - -_ _ _
+_..J
?3~T:T
OUTPUT SQUARE WAVE 51 OPEN
PULSE S2ClOSEO
Figure 3. Test Circuit for High-level Pulse and Squarewave
Output
1-190
XR·205
pulse to this terminal. For Rs = 1 KIl, a sync
pulse of 0.1V to 1V amplitude is recommended.
OUTPUT WAVEFORMS
TRIANGLE OUTPUT
WAVEFORM ADJUSTMENT (PINS 7 AND 8)
The circuit is connected as shown in Figures 1 or 2,
with switches 81 and 82 open.
The shape of the output waveform at pins 1 and 2 is
controlled by a potentiometer, Rj, connected between
these terminals as shown in Figure 1. For sinewave outputs at pins 1 and 2, the value of Rj is adjusted to minimize the harmonic content of the output waveform. This
adjustment is independent of frequency and needs to
be done only once. The output can be converted to a
symmetrical triangle waveform by increasing the effective resistance across these terminals. This can be
done without changing the potentiometer setting, by
opening the switch 82 as shown in Figures 1-3.
SINEWAVE OUTPUT
BUFFER INPUT AND OUTPUT (PINS 10 AND 11)
The buffer amplifier can be connected to any of the circuit outputs (pins 1, 2, 12, 14 or 15) to provide low output impedance and high current drive capability. For
proper operation of the buffer amplifier, pin 11 must be
connected to the most negative potential in the circuit,
with an external load resistor RL (0.75 KIl < RL < 10
KIl). The maximum output current at this pin must not
exceed 20 mAo
DUTY CYCLE ADJUSTMENT
The duty-cycle of the output waveforms can be adjusted by connecting a resistor RS across pins 13 and 14,
as shown in Figures 1-3. With switch 82 open, the output waveform will be symmetrical. Duty cycle is reduced as RS is decreased. (8ee Figure 6.)
The circuit is connected as shown in Figures 1 or 2,
with switch S2 open and S1 closed. The output waveform is adjusted for minimum harmonic distortion using
trimmer resistor Rj connected across pins 7 and 8. Sinusoidal output is obtained from pins 1 or 2 (or pin 11 if
the buffer amplifier is used). The amplitude of the output waveform is controlled by the differential dc voltage
appearing between pins 3 and 4. This bias can be controlled by potentiometer Rq . for a differential bias between these terminals of ± 2 volts or greater, the output
amplitude is maximum and equal to approximately 3
volts pop.
SAWTOOTH OUTPUT
The circuit is connected as shown in Figures 1 or 2,
with switch S1 open and S2 closed. Closing S2 places
resistor RS across pins 13 and 14. This changes the duty cycle of the triangle output and converts it to a sawtooth waveform. The polarity of the sawtooth can be
changed by reversing the polarity of the dc bias across
pins 3 and 4. If S1 is closed, the linear sawtooth waveform is converted to the sinusoidal sawtooth waveform
of Figure 9A.
RAMP OUTPUT (FIGURE 9B)
ADDITIONAL GAIN CONTROL
For ramp outputs, switch S3 of Figure 1 or 2 is opened,
and pin 10 is shorted to pin 14. This results in a 1.4 volt
pop ramp output at pin 11. The duty cycle of this ramp
can be controlled by connecting RS across pins (13-14)
or (13-15).
For amplitude modulated output signals, the dc level
across pins 3 and 4 is fixed by the modulation index required. In this case, the output amplitude can be controlled without effecting the modulation by connecting a
potentiometer between pins 1 and 2.
SQUAREWAVE AND PULSE OUTPUTS
ON-OFF KEYING
The oscillator can be keyed off by applying a positive
voltage pulse to the sweep input terminal. With Rs = 1
KIl, oscillations will stop if the applied potential at pin
13 is raised 3 volts above its open-circuit value.
1-191
For squarewave outputs, the circuit is connected as
shown in Figure 3, with S2 open. The output can be
converted to a pulse by closing S2. The duty cycle of
the pulse output is controlled by potentiometer RD. The
amplitude and polarity of either the pulse or squarewave output can be controlled by potentiometer Rq .
XR·205
10'
""
r-- --
r----1-----j----------
- r-' -
1
1~
1.'
•.• 1----'<+--
"
.-~ -
f\
'0'"
10.6
1
10
,02
103
104
105
,0&
0.'
'.2
10 7
FREQUENCY IHd
Flgura 4. F..quancy as a Function of Co
Acros. PIns 14 and 15
Figura 5. Modular Sao1lon Phasa and
AmplHuda TTansmr Charao1arlsllcs
Flgurs 6. Outy·CyclB and Frtqusncy
Variation as a Funo1lon of Rs.lslor R8
Connso1sd Across PIns 13 and 14
NORMALllr.D FREQUENCY IIlto)
Figura 7. Normalized Frtquency vo.
SWllP VoRage
Flgura 8. Sinusoidal Oulput Olslortlon
as a Funo1lon of Frtqusncy SWllP
Flgull 9. Sinusoidal Sawtooth and
Unsar Ramp Outputs
BUFFER
AMI'\.IFI1R
EQUIVALENT SCHEMATIC DIAGRAM
1·192
XR·2206
Monolithic Function Generator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2206 is a monolithic function generator integrated circuit capable of producing high quality sine,
square, triangle, ramp, and pulse waveforms of highstability and accuracy. The output waveforms can be
both amplitude and frequency modulated by an external voltage. Frequency of operation can be selected
externally over a range of 0.01 Hz to more than 1 MHz.
The circuit is ideally suited for communications, instrumentation, and function generator applications requiring sinusoidal tone, AM, FM, or FSK generation. It has a
typical drift specification of 20 ppm/DC. The oscillator
frequency can be linearly swept over a 2000:1 frequency range, with an external control voltage, having a
very small affect on distortion.
FEATURES
Low-Sine Wave Distortion
Excellent Temperature Stability
Wide Sweep Range
Low-Supply Sensitivity
Linear Amplitude Modulation
TTL Compatible FSK Controls
Wide Supply Range
Adjustable Duty Cycle
SYMMETRY
ADJ.
""..ORN
OUTPUT
MULT.OUT
WAVEFORM
ADJ.
J
+vcc
GROUND
TIMC:
CAPACITOR
L
SYNC
OUTPUT
I
BYPASS
L
FSK
INPUT
TIMING
RESISTORS
0.5%,
20 ppm/DC,
2000:1,
0.01 %V,
Typical
Typical
Typical
Typical
ORDERING INFORMATION
10V to 26V
1 % to 99%
APPLICATIONS
Waveform Generation
Sweep Generation
AM/FM Generation
V/F Conversion
FSK Generation
Phase-Locked Loops (VCO)
Part Number
Package
Operating Temperature
XR-2206M
XR-2206N
XR-2206P
XR-2206CN
XR-2206CP
Ceramic
Ceramic
Plastic
Ceramic
Plastic
-55°C to + 125°C
O°C to + 70°C
O°C to + 70°C
O°C to + 70°C
O°C to + 70°C
SYSTEM DESCRIPTION
The XR-2206 is comprised of four functional blocks; a
voltage-controlled oscillator (VCO), an analog multiplier
and sine-shaper; a unity gain buffer amplifier; and a set
of current switches.
The VCO actually produces an output frequency proportional to an input current, which is produced by a resistor from the timing terminals to ground. The current
switches route one of the timing pins current to the
VCO controlled by an FSK input pin, to produce an output frequency. With two timing pins, two discrete output
frequencies can be independently produced for FSK
Generation Applications.
ABSOLUTE MAXIMUM R1.TINGS
Power Supply
Power DiSSipation
Derate Above 25°C
Total Timing Current
Storage Temperature
l
J
l
AM
INPUT
26V
750mW
5 mW/oC
6 mA
- 65°C to + 150°C
1-193
XR·2206
ELECTRICAL CHARACTERISTICS
= 12V, TA = 25°, C = 0.01 /LF, R1 = 100 kn, R2
unless otherwise specified. S1 open for triangle, closed for sine wave.
Test CondHlons: Test Circuit of Figure 1, V +
PARAMETERS
MIN
XR-2206M
TYP MAX
MIN
10
±5
26
±13
10
±5
XR-2206C
TYP MAX
UNITS
=
10 kn, R3
= 25 kn
CONDITIONS
GENERAL CHARACTERISTICS
Single Supply Voltage
Split-Supply Voltage
Supply Current
12
17
14
26
±13
20·
V
V
mA
R1 2: 10kn
OSCILLATOR SECTION
Max. Operating Frequency
Lowest Practical Frequency
Frequency Accuracy
Temperature Stability
0.5
Supply Sensitivity
Sweep Range
Reference Bypass Voltage
0.01
0.5
±4
±50
1
0.01
±2
±20
MHz
Hz
% offo
ppm/oC
0.1
0.01
%N
2000:1
fH=fL
2
8
2
8
%
%
0.1
0.1
%
1000:1 2000:1
Sweep Linearity
10:1 Sweep
1000:.1 Sweep
FM Distortion
Recommended Timing
Components
Timing Capacitor: C
Timing Resistors:
R1 & R2
Triangle Sine Wave Output
Triangle Amplitude
Sine Wave Amplitude
Max. Output Swing
Output Impedance
Triangle Linearity
Amplitude Stability
Sine Wave Amplitude
Stability
Sine Wave Distortion
Without Adjustment
With Adjustment
Amplitude Modulation
Input Impedance
Modulation Range
Carrier Suppression
Linearity
Square-Wave Output
Amplitude
Rise Time
Fall Time
Saturation Voltage
Leakage Current
FSK Keying Level (Pin 9)
1
0.01
±1
±10
0.001
1
40
100
2000
160
60
6
600
1
0.5
4800
2.5
0.4
50
0.001
1
2.5
0.5
1.0
50
/L F
kn
mV/k n
mV/k n
V pop
n
%
dB
ppm/DC
160
60
6
600
1
0.5
4800
80
100
100
55
2
100
2000
C = 1000 pF, R1 = 1 k n
C = 50/LF, R1 = 2 M n
fo = 1/R1 C
O°C :s; TA :s; 70°C,
R1 = R2 = 20 k n
VLOW = 10V, VHIGH =
20V,
R1 = R2 = 20 k n
fH @ R1 = 1 k n
fL @ R1 = 2 M n
fL = 1 kHz, fH = 10 kHz
fL = 100 kHz, fH = 100
kHz
± 10% Deviation
See Figure 4.
See Note 1, Figure 2.
Figure 1, S1 Open
Figure 1, S1 Closed
For 1000:1 Sweep
See Note 2.
%
%
R1 = 30 k n
See Figures 6 and 7.
100
100
55
2
kn
%
dB
%
For 95 % modulation
0.6
100
2.4
V pop
nsec
nsec
V
/LA
V
3.5
V
0.8
12
250
50
0.2
0.1
1.4
0.4
20
2.4
0.8
12
250
50
0.2
0.1
1.4
2.9
3.1
3.3
2.5
3
1.5
Measured at Pin 11.
CL = 10 pF
CL = 10 pF
IL = 2 mA
V11 = 26V
See section on circuit
controls
Measured at Pin 10.
Note 1: Output amplitude is directly proportional to the resistance, R3, on Pin 3. See Figure 2.
Note 2: For maximum amplitude stability, R3 should be a positive temperature coefficient resistor.
1-194
XR·2206
- rJ Lr-
5, '" OPEN FOR TRIANGLE
CLOSED FOR SINE WAVE.
1.0
\
V
1\
0.'
\
[}----~~vvY-ov+
/
V
1\V
V+12
DC VOLTAGE AT PIN 1
Figure 1. Basic Test Circuit.
T~IANGLE
/
Figure 5. Normalized Output Amplitude versus OC Bias at
AM Input (Pin 1).
/
/
/
/
~RI~~JO~O~
MINIMUM
DISTORTION AT 30 K!I
SINE WAVE
/
/
/V
~ ........
!j/
20
40
60
.0
10
1.0
100
103
TIMING R KO
Figure 2. Output Amplitude as a Function 01 the Resistor,
R3, at Pin 3.
2'
.....-
100
Figure 6. Trimmed Distortion versus Timing Resistor.
r----r---.--~,---~--__,
22 f---+~>""1'------+7"'-t-----1
OO"'U~ ~1~.5 VRM~ PIN 2
RL = 10K!!
i
18
I
/
f-----1,..L.-j----.."...S4-----1
"
9
10 L-__-L____L-__-L__~__~
16
12
20
VCc(V)
"
"
10
r----r--r----r--r----r--,--r-
1 Mn
1-+--1-+--1-+--+--+-
lK
10K
100K
1M
FREQUENCY (Hz)
Figure 3. Supply Current versus Supply Voltage, Timing, R.
10 Mil
100
Figure 7. Sine Wave Distortion versus Operating Frequency
with Timing Capacitors Varied.
-,
_3L--L__L--L__
10
10'
-50 -25
FREQUENCY Hz
25
~~
50
__
75
~~
100
125
AMBIENT TEMPERATURE ("C)
Figure 4. R versus Oscillation Frequency.
Figure 8. Frequency Orill versus Temperature.
1·195
XR·2206
Ae
SWEEP
INPUT
+ Ve
1-=-
-'T
-'e
~
'.
A
PIN7
OAB
3f
12
Figure 9. Circuit Connection for Frequency Sweep.
y+
o--+-------lJ
V+o-~----~~--il
10K
SQUAREWAVE
OUTPUT
I.F
~M
5, CLOSED FOR SiNEWAVE
n-----'-I+ ~
Figure 10. Circuit for Sine Wave Generation without External
Adjustment. (See Rgure 2 for Choice of R3).
J
·2Y
'1
*1V
'2
KEYING
INPUT?
Figure 12. Sinusoidal FSK Generator.
rvoRN
C
A,' R2
RC
!J~~'~L
V·
I' ,
,
OUTPUT
DUTY CYCLE
--~~31
__
0--.
~~E ~'o'
__ ' .. F
1
I
o
5, CLOSED FOR SINEWAVE
't.
saUAAEWAVF
OUTPUT
M
Figure 13. Circuit for Pulse and Ramp Generation.
Figure 11. Circuit for Sine Wave Generation with Minimum
Harmonic Distortion. (R3 Determines Output
Swing-See Figura 2.)
1·196
R,
A,' R2
-=-
XR·2206
Frequency-Shift Keying:
FSK Generation
The XR-2206 can be operated with two separate timing
resistors, R1 and R2, connected to the timing Pin 7 and
8, respectively, as shown in Figure 12. Depending on
the polarity of the logic signal at Pin 9, either one or the
other of these timing resistors is activated. If Pin 9 is
open-circuited or connected to a bias voltage ";?;2V, only
R1 is activated. Similarly, if the voltage level at Pin 9 is
:s 1V, only R2 is activated. Thus, the output frequency
can be keyed between two levels, f1 and f2, as:
Figure 12 shows the circuit connection for sinusoidal
FSK signal operation. Mark and space frequencies can
be independently adjusted, by the choice of timing resistors, R1 and R2; the output is phase-continuous during transitions. The keying signal is applied to Pin 9. The
circuit can be converted to split-supply operation by
simply replacing ground with V-.
f1
=
1/R1C and f2
Pulse and Ramp Generation
= 1/R2C
Figure 13 shows the circuit for pulse and ramp waveform generation. In this mode of operation, the FSK keying terminal (Pin 9) is shorted to the square-wave output
(Pin 11), and the circuit automatically frequency-shift
keys itself between two separate frequencies during
the positive-going and negative-going output waveforms. The pulse width and duty cycle can be adjusted
from 1 % to 99%, by the choice of R1 and R2. The values of R1 and R2 should be in the range of 1 kO to 2
MO.
For split-supply operation, the keying voltage at Pin 9 is
referenced to V-.
Output DC Level Control:
The dc level at the output (Pin 2) is approximately the
same as the dc bias at Pin 3. In Figures 10, 11 and 12,
Pin 3 is biased midway between V+ and ground, to
give an output dc level of '" V + 12.
APPLICATIONS INFORMATION
PRINCIPLES OF OPERATION
Sine Wave Generation
Description of Controls
Without External Adjustment:
Frequency 01 Operation:
Figure 10 shows the circuit connection for generating a
sinusoidal output from the XR-2206. The potentiometer,
R1 at Pin 7, provides the desired frequency tuning. The
maximum output swing is greater than V + 12, and the
typical distortion (THO) is <2.5%. If lower sine wave
distortion is desired, additional adjustments can be provided as described in the following section.
The frequency of oscillation, 10 , is determined by the external timing capacitor, e, across Pin 5 and 6, and by
the timing resistor, R, connected to either Pin 7 or 8.
The frequency is given as:
The circuit of Figure 10 can be converted to split-supply
operation, simply by replacing all ground connections
with V-. For split-supply operation, R3 can be directly
connected to ground.
and can be adjusted by varying either R or C. The recommended values of R, for a given frequency range, as
shown in Figure 4. Temperature stability is optimum for
4 kO < R < 200 kO. Recommended values of Care
from 1000 pF to 100 ,.F.
fo =
With External Adjustment:
J....
RC
Hz
Frequency Sweep and Modulation:
The harmonic content of sinusoidal output can be reduced to '" 0.5 % by additional adjustments as shown
in Figure 11. The potentiometer, RA, adjusts the sineshaping resistor, and RB provides the fine adjustment
for the waveform symmetry. The adjustment procedure
is as follows:
Frequency of oscillation is proportional to the total timing current, IT, drawn from Pin 7 or 8:
_ 320 IT (mA) H
C (,.F)
z
f -
1. Set RB at midpoint, and adjust RA for minimum
distortion.
Timing terminals (Pin 7 or 8) are low-impedance pOints,
and are internally biased at + 3V, with respect to Pin 12.
Frequency varies linearly with ITo over a wide range of
current values, from 1 ,.A to 3 mA. The frequency can
be controlled by applying a control voltage, Ve, to the
activated timing pin as shown in Figure 9. The frequency of oscillation is related to Ve as:
2. With RA set as above, adjust RB to further reduce
distortion.
Triangle Wave Generation
The circuits of Figures 10 and 11 can be converted to
triangle wave generation, by simply open-circuiting Pin
13 and 14 (Le., S1 open). Amplitude of the triangle is approximately twice the sine wave output.
1
R
Vc
f = - 1 + - ( 1 - - ) Hz
Re
RC
3
1-197
XR·2206
Amplitude Modulation:
where Veis in volts. The voltage-to-frequency conversion gain, K, is given as:
K = lJf/lJVe = -
Output amplitude can be modulated by applying a dc bias and a modulating signal to Pin 1. The internal impedance at Pin 1 is approximately 100 kD. Output amplitude varies linearly with the applied voltage at Pin 1, for
values of dc bias at this pin, within ± 4 volts of V + /2 as
shown in Figure 5. As this bias level approaches V + /2,
the phase of the output signal is reversed and the amplitude goes through zero. This property i~ suitable for
~hase-shift keyin.g' and suppressed-carrier AM generation. Total dynamic range of amplitude modulation is approximately 55 dB.
0.32 HzN
Ree
CAUTION: For safety operation of the circuit, IT
should be limited to oS 3 mAo
Output Amplitude:
Maximum output amplitude is inversely proportional to
the exte~nal resistor, R3, connected to Pin 3 (see Figure
2). For sine wave output, amplitude is approximately 60
~V peak .per kD of R3: for triangle, the peak amplitude
IS approximately 160 mV peak per kD of R3. Thus, for
example, R3 = 50 kD would produce approximately
± 3V sinusoidal output amplitude.
CAUTION: AM control must be used in conjunction
with a well-regulated supply, since the output amplitude
now becomes a function of V + .
EQUIVALENT SCHEMATIC DIAGRAM
1-198
XR·2207
Voltage"Co01ltroUed Oscillator
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-2207 is a monolithic voltage-controlled oscillator (VCO) integrated circuit featuring excellent frequency stability and a wide tuning range. The circuit provides simultaneous triangle and square wave outputs
over a frequency range of 0.01 Hz to 1 MHz. It is ideally
suited for FM, FSK, and sweep or tone generation, as
well as for phase-locked loop applications.
+Vcc
TRIANGLE
WAVE OUT
I
saUARE
WAVE OUT
TIMING
CAPACITOR
L
~
The XR-2207 has a typical drift specification of 20 ppm/
DC. The oscillator frequency can be linearly swept over
a 1000:1 range with an external control voltage; and the
duty cycle of both the triangle and the squarewave outputs can be varied from 0.1 % to 99.9% to generate
stable pulse and sawtooth waveforms.
I
I
BIAS
GROUND
R,
TIMING
RESISTORS
--,
R3
BINARY
KEYING
INPUTS
~
FEATURES
Excellent Temperature Stability (20 ppm/DC)
Linear Frequency Sweep
Adjustable Duty Cycle (0.1 % to 99.9%)
Two or Four Level FSK Capability
Wide Sweep Range (1000:1 Min)
Logic Compatible Input and Output Levels
Wide Supply Voltage Range (± 4V to ± 13V)
Low Supply Sensitivity (0.1 %/V)
Wide Frequency Range (0.01 Hz to 1 MHz)
Simultaneous Triangle and Squarewave Outputs
~
ORDERING INFORMATION
.'
Part Number
Package
Operating Temperature
XR2207M
XR2207N
XR2207P
XR2207CN
XR2207CP
Ceramic
Ceramic
Plastic
Ceramic
Plastic
-55°C to +125°C
DoC to + 70°C
DoC to +70°C
DoC to + 70°C
O°C to + 70°C
SYSTEM DESCRIPTION
APPLICATIONS
The XR-2207 utilizes four main functional blocks for frequency generation. These are a voltage controlled oscillator (VCO), four current switches which are activated
by binary keying inputs, and two buffer amplifiers for triangle and squarewave outputs. The VCO is actually a
current controlled oscillator which gets its input from
the current switches. As the output frequency is proportional to the input current, the VCO produces four discrete output frequencies. Two binary input pins determine which timing currents are channelled to the VCO.
These currents are set by resistors to ground from each
of the four timing terminals.
FSK Generation
Voltage and Current-to-Frequency Conversion
Stable Phase-Locked Loop
Waveform Generation
Triangle, Sawtooth, Pulse, Squarewave
FM and Sweep Generation
ABSOLUTE MAXIMUM RATINGS
Power Supply
26V
Power Dissipation (package limitation)
750 mW
Ceramic package
6.0 mW/oC
Derate above + 25°C
625 mW
Plastic package
5 mW/oC
Derate above +25°C
Storage Temperature Range
-65°C to + 150°C
The triangle output buffer provides a low impedance
output (1011 TYP) while the squarew;:lve is an opencollector type. A programmable reference point allows
the XR-2207 to be used in either single or slip supply
configurations.
1-199
XR·2207
ELECTRICAL CHARACTERISTICS
Test Conditions: Test Circuit of Figure 1, V + = V - = 6V, TA = + 25°C, C = 5000 pF, R1 = R2 = R3 = R4
20 KIl, RL = 4.7 KIl, Binary Inputs grounded, 81 and 82 closed unless otherwise specified.
XR-2207/XR-2207M
PARAMETERS
MIN
TYP
=
XR-2207C
MAX
MIN
26
±13
8
±4
TYP
MAX
UNITS
26
±13
V
V
CONDITIONS
GENERAL CHARACTERISTICS
Supply Voltage
Single Supply
Split Supplies
Supply Current
Single Supply
8
±4
Split Supplies
Positive
Negative
See Figure 3
5
7
5
8
rnA
Measured at pin 1, Sl and S2 open
See Figure 2
5
4
7
6
5
4
8
7
rnA
rnA
Measured at pin 1, Sl, S2 open
Measured at pin 12, Sl, S2 open
OSCILLATOR SECTION - FREQUENCY CHARACTERISTICS
Upper Frequency Limit
Lowest Practical Frequency
Frequency Accuracy
Frequency Matching
Frequency Stability
Temperature
Power Supply
Sweep Range
Sweep Linearity
10:1 Sweep
1000:1 Sweep
FM Distortion
Recommended Range 01
Timing Resistors
Impedance at Timing Pins
DC Level at Timing Terminals
0.5
1000:1
1.0
0.01
±1
0.5
20
0.15
3000:1
0.5
±3
50
1.0
0.01
±1
0.5
±5
30
0.15
1000:1
MHz
Hz
% 0110
% 0110
C=500pF,R3=2KIl
C = 50 I'F, R3 = 2 Mil
ppm/oC
DoC
IH"L
%
1
5
0.1
1.5
2
2000
1.5
5
0.1
1.5
75
10
< TA < 70°C
%N
2000
%
KIl
Il
mV
75
10
R3 = 1.5 KIl lor IH1
R3 = 2 Mil lor IL
C = 5000 pF
IH = 10 kHz, IL = 1 kHz
IH = 100 kHz, IL = 100 Hz
± 10% FM Deviation
See Characteristic Curves
Measured at pins 4, 5, 6, or 7
BINARY KEYING INPUTS
Switching Threshold
1.4
Input Impedance
2.2
2.8
1.4
5
2.2
2.8
V
5
KIl
6
10
+100
0.1
Vpp
Il
mV
%
Measured at pins 8 and 9,
Relerenced to pin 10
OUTPUT CHARACTERISTICS
Triangle Output
Amplitude
Impedance
DC Level
Linearity
Squarewave Output
Amplitude
Saturation Voltage
Rise Time
Fall Time
Measured at pin 13
4
11
4
6
10
+100
0.1
12
0.2
200
20
11
0.4
12
0.2
200
20
0.4
Vpp
V
nsec
nsec
Relerenced to pin 10
From 10% to 90% to swing
Measured at pin 13, S2 closed
Relerenced to pin 12
CL:S 10 pF
CL :S 10 pF
PRECAUTIONS
nent damage to the device may occur if the total
timing current exceeds 10 mAo
2. Terminals 2, 3, 4, 5, 6, and 7 have very low internal
impedance and should, therefore, be protected from
accidental shorting to ground or the supply voltages.
3. The keying logic pulse amplitude should not exceed
the supply voltage.
The following precautions should be observed when operating the XR-2207 family of integrated circuits:
1. Pulling excessive current from the timing terminals
will adversely effect the temperature stability of the
circuit. To minimize this disturbance, it is recommended that the total current drawn from pins 4, 5,
6, and 7 be limited to s6 mAo In addition, perma·
1·200
XR·2207
r---,---------~r_----~~r_----~--~------~----T__r----------~----oy.
TRIANGLE WAVE
14 OUTPUT
2.'
4.
~------~--------~----~--~~--ov12
EQUIVALENT SCHEMATIC DIAGRAM
o.~
v'
I,'
52
--a v'
1-'::30-4-<0
~~~~RJUT
1-'::30-+-- 3V for
"one" logic levels referenced to the dc voltage at pin
10 (see Figure 8).
Note: For Single-Supply Operation, LogiC Levels are
Referenced to Voltage at Pin 10
BIAS FOR SINGLE SUPPLY (PIN 11)
For single supply operation, pin 11 should be externally
biased to a potential between V + 13 and V + 12 volts
(see Figure 2). The bias current at pin 11 is nominally
5 % of the total oscillation timing current, IT-
SINGLE SUPPLY OPERATION
The circuit should be interconnected as shown in Figure 11 for single supply operation. Pin 12 should be
grounded, and pin 11 biased from V + through a resistive divider to a value of bias voltage between V + 13
and V + 12. Pin lOis bypassed to ground through a 1 ,..F
capacitor.
GROUND (PIN 10)
For split supply operation, this pin serves as circuit
ground. For single supply operation, pin 10 should be
ac grounded through a 1 ,..F bypass capacitor. During
split supply operation, a ground current of 21T flows out
of this terminal, where IT is the total timing current.
For single supply operation, the dc voltage at pin 10
and the timing terminals (pins 4 through 7) are equal
and approximately O.SV above VB, the bias voltage at
pin 11. The logiC levels at the binary keying terminals
are referenced to the voltage at pin 10.
SQUAREWAVE OUTPUT (PIN 13)
The squarewave output at pin 13 is a "open-collector"
stage capable of sinking up to 20 mA of load current.
RL serves as a pull-up load resistor for this output. Recommended values for RL range from 1 KO to 100 KO.
For a fixed frequency of f3 = 1/R3C, the external circuit connections can be simplified as shown in Figure
llb.
TRIANGLE OUTPUT (PIN 14)
The output at pin 14 is a triangle wave with a peak
swing of approximately one-half of the total supply voltage. Pin 14 has a very low output impedance of 100
and is internally protected against short circuits.
Tabla 1
Logic Table for Binary Keying Controls
BYPASS CAPACITORS
The recommended value for bypass capacitors is 1 ,..F,
although larger values are required for very low frequencyoperation.
LOGIC
LEVEL SELECTED
TIMING
FREQUENCY
PINS
8 9
-r--
SPLIT SUPPLY OPERATION
Figure 1 is the recommended circuit connection for
split supply operation. The frequency of operation is determined by the timing capacitor, C, and the activated
timing resistors (Rl through R4). The timing resistors
0
0
6
0
1
6 and 7
1 0
1 1 I 4 and 5
1-202
11
5
12
DEFINITIONS
11
11 - 1/R3C, al1 - 1/R4C
+ al1
12 - 1/R2C, al2 - lIRIC
12
Logic Levels: 0 - Ground
+ al2
1 = >3 V
XR·2207
25r------r------r------r----~
,..
20f----i7&~----t_----~----~
~
Vi
....
ri
o
o
~
>
~
-'
~ 15~----~~~~~~~--_;------_1
-'
:t
l!
w 10r---,-~~~~~~~~~~-----1
;:
;::
~
100 KU
1-----~0~ij}~~~10r__--~
~
iil
-'
>
~ 5~--~~~~--r_----_+----_4
1 KU O
L -----.~.l..V-----• .L8V-----.-12J..V-----.,~.V
SPLIT SUPPLY
1~
°OL--------~5-------~1~0-------~,5-------J-20
24
32
SINGLE SUPPL V
SUPPLY VOLTAGE IVOLTSI-
NEGATIVE SUPPLY (VOL TI
Figure 4. Recommended Timing Resistor Value VS. Power
Supply Vonage'
Figure 3. Typical Operating Range For spin Supply Vonage
1,04 ,-----.-----,-----.-----,r---..,-----,
7
6
!
a:
o
a:
a:
/
t 1,02 ~---jlo..:---+---_+----+
ii:
o
C =5000pF
>
~ 1.00 ~--+-'~IIC:~-t-----+'.w
/
3
V
w
:l
C
/
~ .98~---h~--+---_4--~~~--+_--~
u.
ow
./
>
u
..
N
./
~ -1
5 -2
w
e:
/
Vs = '6V
5
~
.96~--+----+---_+----+--4_+_--~
:;;
-3
,/
-4
a:
/'
o
Z
.94
C
-5
,L----,1.6----,.L8----'-,1..0----'.L,2----'~,4
4 ---,.L
.92 2
-6
SPLIT SUPPLY VOLTAGE (VOLTSI
-7
lK
10K
1M
lOOK
liMING RESISTANCE (OHMSI
10M
B
4
lk
16
~O
2'4
SINGLE SUPPL Y VOLTAGE (VOL lSI
Figure 5. Frequency Accuracy vs. Timing Resistance
Figure 6. Frequency Drift vs. Supply Vonage
+2% ,---,---,---,----,---,---,---,----,
~
....
u. +1%
ii:
0
>
u
Z
w
0
:l
C
w
u.
a:
0
-1%
w
N
~
3V
f2 +6f2
Figure 8. Logic Table For Binary Keying Controls.
Note: For Single-Supply Operation, Logic Levels are
Referenced to Voltage at Pin 10
A
v'
TIMING CAPACITOR
v'
v'
SQUARE WAVE
OUT
'0
TRIANGLE WAVE
OUT
BINARV
~g~~~C;;lS I--+--/-~
v12
v-
Figure 10. Split-Supply Operation:
(a) General
(b) Fixed Frequency
Figure 9. Simplified Schematic of Frequency Control
Mechanism
The frequency f will increase as the control voltage is
made more negative. If R3 = 2 MD, Re = 2 KD, e =
5000 pF, then at 1000: 1 frequency sweep would result
V- .
for a negativ sweep voltage Ve
FREQUENCY CONTROL (SWEEP AND FM)
=
The frequency of operation is controlled by varying the
total timing current, IT, drawn from the activated timing
pins 4, 5, 6, or 7. The timing current can be modulated
by applying a control voltage, Ve, to the activated timing pin through a series resistor Re as shown in Figures
12 & 13.
The voltage to frequency conversion gain, K, is controlled by the series resistance Re and can be expressed as:
K = ~ = - __l-Hz/volt
tJoVe
For split supply operation, a negative control voltage,
Ve, applied to the circuits of Figures 15 & 16 causes
the total timing current, IT, and the frequency, to increase.
The circuit of Figure 12 can operate both with positive
and negative values of control voltage. However, for
positive values of Ve with small (RcJR3) ratio, the direction of the timing current IT is reversed and the oscillations will stop.
As an example, in the circuit of Figure 12, the binary
keying inputs are grounded. Therefore, only timing pin
6 is activated.
The frequency of operation, normally f =
R~e'
Figure 13 shows an alternate circuit for frequency control where two timing pins, 6 and 7, are activated. The
frequency and the conversion gain expressions are the
same as before, except that the circuit would operate
only with negative values of Ve. For Ve > 0, pin 7 becomes deactivated
is now
proportional to the control voltage, Ve, and determined
as:
f
= _1_
R3e
ReeV-
R3 HZ]
[1 _Ve
ReV -
and the frequency is fixed at f
1-204
= R~e'
XR·2207
with Figure 11. For a "high" logic level at pin 8, the timing resistors Rl and R2 are activated. Similarly, for a
"low" logic level, timing resistors R3 and R4 are enabled.
CAUTION
For operation of the circuit, total timing current IT must
be less than 6 mA over the frequency control range.
The "high" and "low" logic levels at pin 9 determine
the respective high and low frequencies within the selected FSK channel.
OUTY CYCLE CONTROL
The duty cycle of the output waveforms can be controlled by frequency shift keying at the end of every half
cycle of oscillator output. This is accomplished by con·
necting one or both of the binary keying inputs (pins 8
or 9) to the squarewave output at pin 13. The output
waveforms can then be converted to positive or negative pulses and sawtooth waveforms.
Recommended component values for various commonly used FSK frequencies are given in Table 1. When
only a single FSK channel is used, the remaining channel can be deactivated by connecting pin 8 to either
V+ or ground. In this case, the unused timing resistors
can also be omitted from the circuit.
The low and high frequencies, fl and f2' for a given
FSK channel can be fine tuned using potentiometers
connected in series with respective timing resistors. In
fine tuning the frequencies, f1 should be set first with
the logic level at pin 9 in a "low" level.
Figure 14 is the recommended circuit connection for
duty cycle control. Pin 8 is shorted to pin 13 so that the
circuit switches between the "0,0" and the "1,0" logic
states given in Figure 11. Timing pin 5 is activated
when the output is "high," and the timing pin is activated when the squarewave output goes to a low state.
Typical frequency drift of the circuit for O°C to 75°C operation is ±0.2%. Since the frequency stability is directly related to the external timing components, care
must be taken to use timing components with low temperature coefficients.
The duty cycle of the output waveforms is given as:
Duty Cycle =
R2
R2 + R3
FSK TRANSCEIVER (FULL-DUPLEX MODEM)
and can be varied from 0.1 % to 99.9% by proper
choice of timing resistors. :The frequency of oscillation,
f, is given as:
f -
~ [R2 :
The XR-2207 can be used in conjunction with the XR210, FSK demodulator, to form a full-duplex FSK transceiver, or modem. A recommended circuit connection
for this application is shown in Figure 20. Table 1 shows
the recommended component values for 300-Baud
(103-type) and 1200-Baud (202-type) Modem applications.
R3]
The frequency can be modulated or swept without
changing the duty cycle by connecting R2 and R3 to a
common control voltage VC, instead of to V - (see Figure 15). The sawtooth and the pulse output waveforms
are shown in Figure 15.
v'
BINARY KEYING
INPUts
ON-OFF KEYING
v'
The XR-2207 can be keyed on and off by simply activating an open circuited timing pin. Under certain conditions, the circuit may exhibit very low frequency « 1
Hz) residual oscillations in the "off" state due to internal bias currents. If this effect is undesirable, it can be
eliminated by connecting a 10 MO resistor from pin 3 to
V+.
A
TWO-CHANNEL FSK GENERATOR
(MODEM TRANSMITTER)
The multi-level frequency shift-keying capability of XR2207 makes it ideally suited for two-channel FSK generation. A recommended circuit connection for this application is shown in Figure 16.
v'
B
For two-channel FSK generation, the "mark" and
"space" frequencies of the respective channels are
determined by the timing resistor pairs (Rl, R2) and
(R3, R4). Pin 8 is the "channel-select" control in accord
Figure 11. Single Supply Operation:
(a) General
(b) Fixed Frequency
1-205
XR·2207
v'
v'
SQUARE WAVE
OUT
TRIANGLE WAVE
OUT
A
Co· BYPASS CAPACITOR
, -1CRJ
[t VeA3]
RCV-
r;~EP+
-
v-
OR
FM
INPUT
Figure 12. Frequency Sweep Operation
B
v'
SQUARE WAVE
OUT
TRIANOlE WAVE
OUT
c
v'
Figure 15. Output Waveforms:
(a) Squarewave and Triangle Outputs
(b) Pulse and Sawtooth Outputs
(c) Frequency-Shift Keyed Output
Top: FSK Output With f2 = 2fl
Bottom: Keying Logic Input
CD· BYPASS CAPACITOR
I·C~J [1-:~:~]
FORVCSOONLY,
RJ
v-
• vc
'?':J...
SWEEP
":'"
OR
FM INPUT
Figure 13. Alternate Frequency Sweep Operation
v· f+SVI
v'
SAWTOOTH
OUTPUT
v'
CB .. BYPASS CAPACITOR
DUTY CYCLE ..
"2
R;+'FG
14
v-
frequency .. { -
I'J1F
10K
SOK
10K
SOK
4.7K
v-
Figure 14. Sawtooth and Pulse Outputs
PULSE
OUTPUT
'-"-'~"-'-~-~--o
Figure 16. Multi-Channel FSK Generation
1-206
v- {-6V)
XR·2207
V' - 12V
lJ,F
o l .. F
Co
r-l
i~:UT 0-----1
12
11
4.
,.
XR-210
,S.
DEMODULATOR
'K
0.1 "F
500!!
10K
'K
FINE TUNE
rr
FSK OUTPUT
IWMI\
10K
50K
SPACE
MARK
AOJ.
AOJ.
Figure 17. Full Duplex FSK Modem Using XR-210 and
XR-2207 (See Table 1 For Component Values)
5
TA=2S'C
0
V
V
~
V
0
'6
'8
'10
'12
-SPLIT SUPPLY VOL TAGE (VOL TSI
'6
'8
'10
'12
SPLIT SUPPl V VOLTAGE (VOL IS)
'14
'14
1~ 1~ 1~ ~ 1~ ~ ~ ~ ~ ~
SINGLE SUPPL V VOL TAGE (VOL TSI
Figure 18. Positive Supply Current, I + (Measured at Pin 1)
vs. Supply Voltage"
Figure 19. Negative Supply Current, 1- (Measured at Pin
12) vs. Supply Voltage
·Note: RT
1·207
Parallel Combination 01 Activated Timing Resistors
XR·2209
Precision Oscillator
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-2209 is a monolithic variable frequency oscillator circuit featuring excellent temperature stability and
a wide linear sweep range. The circuit provides simultaneous triangle and squarewave outputs over a frequency range of 0.01 Hz to 1 MHz. The frequency is set
by an external RC product. It is ideally suited for frequency modulation, voltage to frequency or current to
frequency conversion, sweep or tone generation as
well as for phase-locked loop applications when used in
conjunction with a phase comparator such as the XR2208.
TRIANGLE
OUTPUT
7
saUARE
WAVE
OUTPUT
FEATURES
Excellent Temperature Stability (20 ppm/OC)
Linear Frequency Sweep
Wide Sweep Range (1000:1 Min)
Wide Supply Voltage Range (± 4V to ± 13V)
Low Supply Sensitivity (0.15%1V)
Wide Frequency Range (0.01 Hz to 1 MHz)
Simultaneous Triangle and Squarewave Outputs
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-2209M
XR-2209CN
XR-2209CP
Ceramic
Ceramic
Plastic
-55°C to + 125°C
O°C to + 70°C
O°C to + 70°C
APPLICATIONS
Voltage and Current-to-Frequency Conversion
Stable Phase-Locked Loop
Waveform Generation
FM and Sweep Generation
SYSTEM DESCRIPTION
The XR-2209 preciSion oscillator is comprised of three
functional blocks: a variable frequency oscillator which
generates the basic periodic waveforms and two buffer
amplifiers for the triangle and the squarewave outputs.
The oscillator frequency, set by an external capacitor,
C, and the timing resistor, R, operates over 8 frequency
decades, from 0.01 Hz to 1 MHz. With no sweep signal
applied, the frequency of oscillation is equal to 1IRC.
ABSOLUTE MAXIMUM RATINGS
Power Supply
26 volts
Power Dissipation (package limitation)
Ceramic Package
385 mW
Plastic Package
300 mW
2.5 mW/oC
Derate above + 25°C
Operating Temperatue Range
XR-2209M
- 55°C to + 125°C
XR-2209C
DOC to + 70°C
Storage Tem'perature Range
- 65°C to + 150°C
The XR-2209 has a typical drift specification of 20 ppml
°C. Its frequency can be linearly swept over a 1000:1
range with an external control signal. Output duty cycle
is adjustable from less than 1 % to over 99%. The device may operate from either single or split supplies
from 8 V to 26 V (±4 V to ± 13 V).
1-208
XR·2209
ELECTRICAL CHARACTERISTICS
Test Conditions: Test Circuit of Figure 1, V + = V - = 6V, TA = + 25°C, C = 5000 pF, R - 20 KIl, RL = 4.7 kll. SI and S2
closed unless otherwise specified.
XR-2209C
XR-2209M
PARAMETERS
MIN
TYP
MAX MIN
TYP
MAX UNITS
CONDITIONS
GENERAL CHARACTERISTICS
Supply Voltage
Single Supply
Split Supplies
Supply Current
Single Supply
26
±13
8
±4
Split Supplies
Positive
Negative
8
±4
26
±13
V
V
See Figure 2
See Figure 1
5
7
5
8
mA
Measured at pin 1, SI, S2 open
See Figure 2
5
4
7
6
5
4
8
7
mA
mA
Measured at pin 1, S1, S2 opAn
Measured at pin 4, SI, S2 open
MHz
Hz
% of
fa
C = 500 pF, R = 2 KIl
e = 50 I'F, R = 2 MO
OSCILLATOR SECTION - FREQUENCY CHARACTERISTICS
Upper Frequency Limit
Lowest Practical Frequency
Frequency Accuracy
Frequency Stability
Temperature
Power Supply
Sweep Range
Sweep Linearity
10:1 Sweep
1000: 1 Sweep
FM Distortion
Recommended Range of
Timing Resistors
Impedance at Timing Pin
0.5
1.0
0.01
±1
20
0.15
1000:1 3000:1
0.5
±3
1.0
0.01
±1
±5
ppm/oe O°C < TA < 70 D e
30
0.15
1000:1
50
%/V
fH/fL
%
KO
R = 1.5 KO for fHl
R = 2 MO for fL
e = 5000 pF
fH = 10 kHz, fL = 1 kHz
fH = 100 kHz, fL = 100Hz
± 10% FM Deviation
See Characteristic Curves
75
0
Measured at pin 4
6
10
0.1
Vpp
%
1
5
0.1
2
2000
1.5
1.5
5
0.1
1.5
2000
75
OUTPUT CHARACTERISTICS
Triangle Output
Amplitude
Impedance
Linearity
Squarewave Output
Amplitude
Saturation Voltage
Rise Time
Fall Time
Measured at pin 8
4
11
6
10
0.1
12
0.2
200
20
4
11
0.4
0
%
12
0.2
200
20
0.4
Vpp
V
nsec
nsec
10% to 90% of swing
Measured at pin 7, S2 closed
Referenced to pin 6
eL s 10 pF, RL = 4.7 KO
CL s 10 pF
3. Triangle waveform linearity is sensitive to parasitic
coupling between the square and the triangle-wave
outputs (pins 7 and 8). In board layout or circuit wiring care should be taken to minimize stray wiring capacitances between these pins.
PRECAUTIONS
The following precautions should be observed when operating the XR-2209 family of integrated circuits:
1. Pulling excessive current from the timing terminal
will adversely effect the temperature stability of the
circuit. To minimize this disturbance, it is recommended that the total current drawn from pin 4 be
limited to s 6 mAo
2. Terminals 2, 3, and 4 have very low internal impedance and should, therefore, be protected from accidental shorting to ground or the supply Voltages.
DESCRIPTION OF CIRCUIT CONTROLS
TIMING CAPACITOR (PINS 2 and 3)
The oscillator frequency is inversely proportional to the
timing capacitor, C. The minimum capacitance value is
limited by stray capacitances and the maximum value
1-209
XR·2209
1N
Figure 1. Test Circuit for Split Supply Operation (01
4148 or Equivalent)
Figure 2. Test Circuit for Single Supply Operation
CHARACTERISTIC CURVES
$PLlTSUPPLY
t~
Figure 3. Typical Operating Range
For Spilt Supply Voltage
Figure 4. Recommended Timing Resistor Value vs. Power supply Voltage*
.
RT"lLu
>
~'.00
~
S
:: .n
..
--..;;
~
r-....... \
"\
TA" 2S"C
RT-TOTAL
2
2KU
-
RES1STT C£
C
•
roo
14
Figure 6. Frequency Accuracy vs.
Timing Resistance
"T
TIMING
,9
lOKI!
I200KU
RT
~
~ .!Hi
I
RT
~ I...:::::: p-c:
~
TIMING RESISTANCE IOHMSI
Figure 5. Output Waveforms
Top: Triangle Output (Pin 8)
Boltom: Squarewave Output (Pin 7)
,
t:',.02
-',''::,----::!::---"'',oo:O:,:--,±.,--~'''.
32
24
SINOLESU"LY
SUPPLY VOLTAGE IVOLTSI
NEGATIVE SUPPl V (VOL TSI
PF
16
18
tiD
il2
SPLIT SUPPLY VOLTAGE (VOL lSI
A
l~
16
M
2~
2'
SINGLE SUPPLY VOLTAGE (VOL TSI
Figure 7. Frequency Drift VS. Supply
Voltage
*Note: RT = Timing Resistor at Pin 4
Figure 8. Normalized Frequency
Drift With Temperature
RECOMMENDED CIRCUIT CONNECTIONS
"
,,...,
,_.tU'L_.
Figure 11. Simplified Circuit Connection
for Spilt Supply Operation With VCC =
VEE > ± 7V (Note: Triangle wave
Figure 9. Circuit Connection for Single
Supply Operation
Figure 10. Generalized Circuit Connection for Split Supply Operation
1·210
output has + O.6V offset with reo
spect to ground.)
OPERATING
by physical size and leakage current considerations.
Recommended values range from 100 pF to 100 ,.,F.
The capacitor should be non-polar.
XR·2209
INSTRUCTIO~~S
SPLIT SUPPLY OPERATION
The recommended circuit for split supply operation is
shown in Figure 10. Diode 01 in the figure assures that
the triangle output swing at pin 8 is symmetrical about
ground. This circuit operates with supply voltages ranging from ±4V to ± 13V. Minimum drift occurs at ±6V
supplies. See Figure 3 for operation with unequal supplies.
TIMING RESISTOR (PIN 4)
The timing resistor determines the total timing current,
IT, available to charge the timing capacitor. Values for
the timing resistor can range from 1.5 KO to 2 MO; however, for optimum temperature and power supply stability, recommended values are 4 KO to 200 KO (see Figures 4,7, and 8). To avoid parasitic pick up, timing resistor leads should be kept as short as possible.
Simplified Connection
For operation with split supplies in excess of ± 7 volts,
the simplified circuit connection of Figure 11 can be
used. This circuit eliminates the diode 01 used in Figure 10; however the triangle wave output at pin 8 now
has a + 0.6 volt DC offset with respect to ground.
SUPPLY VOLTAGE (PINS 1 AND 6)
The XR-2209 is designed to operate over a power supply range of ±4V to ± 13V for split supplies, or 8V to
26V for single supplies. At high supply voltages, the frequency sweep range is reduced (see Figures 3 and 4).
Performance is optimum for ± 6V, or 12V single supply
operation.
SINGLE SUPPLY OPERATION
The recommended circuit connection for single-supply
operation is shown in Figure 9. Pin 6 is grounded; and
pin 5 is biased from V + through a resistive divider as
shown in the figure, and is bypassed to ground with a 1
,.,F capacitor.
BIAS FOR SINGLE SUPPLY (PIN 5)
For single supply operation, pin 5 should be externally
biased to a potential between V + 13 and V + 12 volts
(see Figure 9). The bias current at pin 5 is nominally 5%
of the total oscillation timing current, ITo at pin 4. This
pin should be bypassed to ground with 0.1 ,.,F capacitor.
For Single supply operation, the DC voltage at the timing terminal, pin 4, is approximately 0.6 volts above VB,
the bias voltage at pin 5.
The frequency of operation is determined by the timing
capacitor C and the timing resistor R, and is equal to 11
RC. The squarewave output is obtained at pin 7 and has
a peak-to-peak voltage swing equal to the supply voltage. This output is an "open-collector" type and requires an external pull-up load resistor (nominally 5 KO)
to V + . The triangle waveform obtained at pin 8 is centered about a voltage level Vo where:
SQUAREWAVE OUTPUT (PIN 7)
The squarewave output at pin 7 is a "open-collector"
stage capable of sinking up to 20 mA of load current.
RLserves as a pull-up load resistor for this output. Recommended values for RL range from 1 KO to 100 KO.
TRIANGLE OUTPUT (PIN 8)
The output at pin 8 is a triangle wave with a peak swing
of approximately one-half of the total supply voltage.
Pin 8 has a very low output impedance of 100 and is internally protected against short circuits.
Vo = VB + 0.6V
where VB is the bias voltage at pin 5. The peak-to-peak
output swing of triangle wave is approximately equal to
V+/2.
FREQUENCY CONTROL (SWEEP AND FM)
-- r-Ie
+
t
RS
o+
Ve
~
The frequency of operation is proportional to the total
timing current IT drawn from the timing pin, pin 4. This
timing current, and the frequency of operation can be
modulated by applying a control voltage, VC, to the timing pin, through a series resistor, RS, as shown in Figure 12. If Vc is negative with respect to VA, the voltage
level at pin 4, then an additional current 10 is drawn
from the timing pin causing IT to increase, thus increasing the frequency. Conversely, making Vc higher
than VA causes the frequency to decrease by decreasing IT.
IT
R
f
4
XR-2209
VA
~
The frequency of operation, is determined by:
6
f = fo
'::'
Figure 12. Frequency Sweep Operation
where fo = l/RC.
1-211
[1 + RSR-
R]
Vc
VA RS
XR·2209
r-~--------~----~~----~--~----~--~~~--------~--O~
I
TlltANGLl .AVI
lOUTNT
OM
'IMING
IIIIIITOII
IIAI
EQUIVALENT SCHEMATIC DIAGRAM
1-212
XR·8038
Precision Waveform Generator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-8038 is a precision waveform generator IC capable of producing sine, square, triangular, sawtooth
and pulse waveforms with a minimum number of external components and adjustments. Its operating frequency can be selected over nine decades of frequency, from 0.001 Hz to 1 MHz by the choice of external RC components. The frequency of oscillation is highly
stable over. a wide range of temperature and supply
voltage changes. The frequency control, sweep and
modulation can be accomplished with an external control voltage, without affecting the quality of the output
waveforms. Each of the three basic waveforms, i.e.,
sinewave, triangle and square wave outputs are available simultaneously, from independent output terminals.
ORDERING INFORMATION
The XR-8038 monolithic waveform generator uses advanced processing technology and Schottky-barrier diodes to enhance its frequency performance. It can be
readily interfaced with a monolithic phase-detector circuit, such as the XR-2208, to form stable phase-locked
loop circuits.
Part Number
Package
Operating Temperature
XR-8038M
XR-8038N
XR-8038P
XR-8038CN
XR-8038CP
Ceramic
Ceramic
Plastic
Ceramic
Plastic
- 55°C to + 125°C
DoC to + 70°C
DoC to + 70°C
DoC to + 70°C
DoC to + 70°C
FEATURES
SYSTEM DESCRIPTION
Direct Replacement for Intersil 8038
Low Frequency Drift-50 ppm/oC Max.
Simultaneous Sine, Triangle and Square-Wave Outputs
Low Distortion-THD "" 1 %
High FM and Triangle Linearity
Wide Frequency Range-0.001 Hz to 1 MHz
Variable Duty-Cycle-2% to 98%
APPLICATIONS
The XR-8038 precision waveform generator produces
highly stable and sweepable square, triangle and sine
waves across nine frequency decades. The device
time base employs resistors and a capacitor for frequency and duty cycle determination. The generator
contains dual comparators, a flip-flop driving a switch,
current sources, a buffer amplifier and· a sine wave
converter. Three identical frequency waveforms are simultaneously available. Supply voltage can range from
10V to 30V, or ±5V with dual supplies.
Precision Waveform Generation Sine, Triangle, Square,
Pulse
Sweep and FM Generation
Tone Generation
Instrumentation and Test Equipment Design
Precision PLL Design
Unadjusted sine wave distortion is typically less than
0.7%, with Pin 1 open and 8 kO from Pin 12 to Pin 11
( - VEE or ground). Sine wave distortion may be improved by including two 100 kO potentiometers between VCC and VEE (or ground), with one wiper connected to Pin 1 and the other connected to Pin 12.
ABSOLUTE MAXIMUM RATINGS
Frequency sweeping or FM is accomplished by applying modulation to Pins 7 and 8 for small deviations, or
only to Pin 8 for large shifts. Sweep range typically exceeds 1000: 1.
Power Supply
36V
Power Dissipation (package limitation)
750mW
Ceramic package
6.0 mW/oC
Derate above + 25°C
Plastic package
625 mW
5 mW/oC
Derate above + 25°C
Storage Temperature Range
-65°C to + 150°C
The square wave output is an open collector transistor;
output amplitude swing closely approaches the supply
voltage. Triangle output amplitude is typically 1/3 of the
supply, and sine wave output reaches 0.22 VS.
1-213
XR·8038
ELECTRICAL CHARACTERISTICS
Test Conditions: Vs = ± 5V to ± 15V, TA = 25·C, RL = 1 Mil, RA = RS
unless otherwise specified. See Test Circuit of Figure 1.
PARAMETERS
GENERAL CHARACTERISTICS
Supply Voltage, Vs
Single Supply
Dual Supplies
Supply Current
10
±5
12
Lowest Practical Frequency
OUTPUT CHARACTERISTICS
Square-Wave
Amplitude
Saturation Voltage
Rise Time
Fall Time
Duty Cycle Adj.
Triangle/Sawtooth/Ramp
Amplitude
Linearity
Output Impedance
Sine-Wave Amplitude
Distortion
Unadjusted
Adjusted
= 3300 pF, S1
10 kll, C1
XR·8038M/XR·8038
XR·8038C
MIN TYP MAX MIN TYP MAX UNITS
30
±15
15
10
±5
MHz
0.001
0.001
Hz
100
1000:1
0.1
100
1000:1
0.2
kHz
20
50
-
50
100
-
-
0.9
0.98
0.2 :
100
40
2
0.3
0.2
0.9
0.4
98
-
-
0.98
0.2
100
40
0.5
2
0.33
0.05
200
0.3
0.22
0.2
0.7
0.5
1000
50
0.05
0.05
1.5
Vs
98
=
±10V. See Note 1.
RA = RS = 50011, C1
RL = 15 kll
RA = RS = 1 Mil, C1
500/lF
= 0,
=
S1 Open. See Notes 2 and 3.
S1 Open. See Note 3.
Values of RA and RS
%
1000 0.5
closed,
CONDITIONS
V
V
mA
1
0.5
-
30
±15
20
12
FREQUENCY CHARACTERISTICS (Measured at Pin 9)
Range of Adjustment
Max. Operating Frequency
1
Max. FM Sweep Frequency
FM Sweep Range
FM Linearity
Range of Timing Resistors
Temperature Stability
XR-8038M
XR-8038
XR-8038C
Power Supply Stability
=
kll
ppm/·C
ppm/·C
ppm/·C.
%N
See Note 4.
x Vs
V
nsec
nsec
Measured at Pin 9.
RL = 100 kll
Isink = 2 mA
RL = 4.7 kll
RL = 4.7 kll
%
Measured at Pin 3.
RL = 100 kll
0.33
0.1
200
x Vs
%
II
lout
0.22
x Vs
RL
= 5 mA
= 100 kll
%
%
RL
RL
= 1 Mil. See Note 5.
= 1 Mil
0.8
0.5
3
Note 1: Currents through RA ad RS not Included.
Note 2: Vs = 20V, f = 10 kHz, RA = RS = 10kll.
Note 3: Apply sweep voltage at Pin 8.
(2/3 Vs + 2V) S Vsweep S Vs
Note 4: 10V S Vs S 30Vor ±5V S Vss ± 15V.
Note 5: 81 kll resistor connected between Pins 11
and 12.
.---_._--..__--..--0
5,
'ISV
XR-8038
81k
'----+---+-----<)
Figure 1. Generalized Test Circuit
1-214
-,.v
XR·8038
CHARACTERISTIC CURVES
20
z
o
~
~
10
,
20
, i
09Sf- '-f-
]5
30
10
Supply Voltage
Power Dissipation vs. Supply Voltage
II
I
,
A
VI
--i-
~
15
'0
-t
-
099
~
,
"
!
I
I
, 00
/-~ v- I· j
10
a
!
,
, 0
"- // VI
~ ~~ !
125ft
s
~
, 0
L ~v
)".1
,,
~
1I
, 0J
v
-t15
-'-+I
r-
_i-
UNADJUSTE~
I
10
25
30
10Hl
Supply Voltage
Frequency Drift vs. Power Supply
WAVEFORM ADJUSTMENT
J
II -1'OJI'\1" ~r-- r--
IOOHI
'kH,
IOkHI
IOO"Hz
'MH,
Sinewave THO vs. Frequency
slightly more convenient. If no adjustment of the duty
cycle is desired, terminals 4 and 5 can be shorted together, as shown in Figure 2c. This connection, however, carries an inherently larger variation of the dutycycle.
The symmetry of all waveforms can be adjusted with
the external timing resistors. Two possible ways to accomplish this are shown in Figure 2. Best results are
obtained by keeping the timing resistors RA and RB
separate (a). RA controls the rising portion of the triangle and sine-wave and the "Low" state of the square
wave.
With two separate timing resistors, the frequency is
given by
The magnitude of the triangle waveform is set at 1/3
Vee; therefore, the duration of the rising portion of the
triangle is:
e x V e x 1/3 x Vee x RA
t1 = - - =
I
1/5 x Vee
5
=-
3
RA x
or, if RA = RB = R
e
f = 0.3/Re (for Figure 2a)
The duration of the falling portion of the triangle and the
sinewave, and the "High" state of the square-wave is:
t2 = e x V =
e x 1/3 Vee
=
~ x Vee _ ~ x Vee
5
RB
5
RA
§ x
3
If a single timing resistor is used (Figures 2b and c), the
frequency is
RARBe
2RA - RB
f
= 0.15/Re
The frequency of oscillation is independent of supply
voltage, even though none of the voltages are regulated
inside the integrated circuit. This is due to the fact that
both currents and thresholds are direct, linear function
of the supply voltage and thus their effects cancel.
Thus a 50% duty cycle is achieved when RA = RB.
If the duty-cycle is to be varied over a small range
about 50% only, the connection shown in Figure 2b is
'vee
-Vee
'vee
JU1
JU1
XR-8038
"
"
"
V\,
XR-8038
V\,
~
'"
Figure 2. Possible Connections for the External Timing Resistors •
. 1-215
JU1
XR-8038
V\,
~
XR·8038
(load resistor connected to + 5 Volts) while the waveform generator itself is powered from a higher supply
voltage.
DISTORTION ADJUSTMENT
To minimize sine-wave distortion the a1 kO resistor between pins 11 and 12 is best made a variable one. With
this arrangement distortion of less than 1 % is achievable. To reduce this even further, two potentiometers can
be connected as shown in Figure 3. This configuration
allows a reduction of sine-wave distortion close to
0.5%
RR
V
FREQUENCY MODULATION AND SWEEP
The frequency of the waveform generator is a direct
function of the DC voltage at terminal a (measured from
+ Vee). By altering this voltage, frequency modulation
is performed.
For small deviations (e.g., ± 10%) the modulating signal can be applied directly to pin a by merely providing
ac coupling with a capacitor, as shown in Figure 4a. An
external resistor between pins 7 and a is not necessary,
but it can be used to increase input impedance. Without it (I.e. terminals 7 and a connected together), the input impedance is akO); with it, this impedance increases to (R + akO).
Rl
RS
~
[~
,
,
•
XR-8038
10
t,
11
12
9~nn
3~Vv
, ,~
""
For larger FM deviations or for frequency sweeping, the
modulating signal is applied between the positive supply voltage and pin a (Figure 4b). In this way the entire
bias for the current sources is created by the modulating signal and a very large (e.g., 1000:1) sweep range is
obtained (f = a at Vsweep = 0). eare must be taken,
however, to regulate the supply voltage; in this configuration the charge current is no longer a function of the
supply voltage (yet the trigger thresholds still are) and
thus the frequency becomes dependent on the supply
voltage. The potential on Pin a may be swept from Vec
to 2/3 Vee + 2V.
......
'OOkn
l00kf2
-v or GNO
Figura 3. Connection to Achieve Minimum Sine-Wave Distortion.
SELECTING TIMING COMPONENTS
For any given output frequency, there is a wide range of
Re combinations that will work. However certain constraints are placed upon the magnitude of the charging
current for optimum performance. At the low end, currents of less than 0.1 ,.A are undesirable because circuit leakages will contribute significant errors at high
temperatures. At higher currents (1 > 5 mAl, transistor
betas and saturation voltages will contribute increasingly larger errors. Optimum performance will be obtained for charging currents of 1 p. to 1 mAo If pins 7 and
a are shorted together the magnitude of the charging
current due to RA can be calculated from:
.------1r-----1~-
(a)
_
__o +Vcc
RS
FM
o-j H-c>-l
XR·8038
11
'0
12
."
·V 0' GNO
A similar calculation holds for RB.
(b)
SINGLE-SUPPLY AND SPLIT-SUPPLY OPERATION
The waveform generator can be operated either from a
single power-supply (10 to 30 Volts) or a dual powersupply (± 5 to ± 15 Volts). With a single power-supply
the average levels of the triangle and sine-wave are at
exactly one-half of the supply voltage, while the squarewave alternates between + Vee and ground. A split
power supply has the advantage that all waveforms
move symmetrically about ground.
The square-wave output is not committed. A load resistor can be connected to a different power-supply, as
long as the applied voltage remains within the breakdown capability of the waveform generator (30V). In this
way, the square-wave output will be TIL compatible
'Vee
I
RR
RS
Rl
SwfEP
VOL TAGE
nn
j
Vv
XR-8038
'0
""
"
.. >
L.._~>--_-4_--''----o
- v 0'
G"IO
Figure 4. Connections lor Frequency Modulation (a) and Sweep (b).
1-216
XR·8038A
IPrecusDon Waveform Generator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-8038A is a precision waveform generator IC capable of producing sine, square, triangular, sawtooth,
and pulse waveforms, with a minimum number of external components and adjustments. The 8038A allows
the elimination of the external distortion adjusting resistor which greatly improves the temperature drift of distortion, as well as lowering external parts count. Its operating frequency can be selected over nine decades
of frequency, from 0.001 Hz to 1 MHz, by the choice of
external R-C components. The frequency of oscillation
is highly stable over a wide range of temperature and
supply voltage changes. The frequency control, the
sweep, and the modulation can be accomplished with
an external control voltage, without affecting the quality of the output waveforms. Each of the three basic
waveform outputs, (Le., sine, triangle and square) are
simultaneously available from independent output terminals.
SINE ADJ
M
r
DUTY CYCLE
AOJ
L
FM BIAS
ORDERING INFORMATION
Part Number
Package
Operating Temperature
The XR-8038A monolithic waveform generator uses advanced processing technology and Schottky-barrier diodes to enhance its frequency performance. It can be
readily interfaced with a monolithic phase-detector circuit, such as the XR-2228 to form stable phase-locked
circuits.
XR-8038AM
XR-8038AN
XR-8038AP
XR-8038ACN
XR-8038ACP
Ceramic
Ceramic
Plastic
Ceramic
Plastic
-55°C to +125°C
O°C to + 70°C
O°C to + 70°C
O°C to + 70°C
O°C to +70°C
FEATURES
The XR-8038A preCision waveform generator produces
highly stable and sweepable square, triangle, and sine
waves across nine frequency decades. The XR-8038A
is an advanced version of the XR-8038, with improved
sine distortion temperature drift. The device time base
employs resistors and a capacitor for frequency and
duty cycle determination. The generator contains dual
comparators, a flip-flop driving a switch, current
sources, a buffer amplifier, and a sine wave convertor.
Three identical frequency outputs are simultaneously
available. Supply voltage can range from 10V to 30V, or
± 5V to ± 15V with dual supplies.
SYSTEM DESCRIPTION
Low Frequency Drift
50 ppm/DC, Typical
Simultaneous Sine, Triangle, and Square Wave Outputs
Low Distortion
THD 1 %
High FM and Triangle Linearity
Wide Frequency Range
0.001 Hz to 1 MHz, Typical
2% to 98%
Variable Duty Cycle
Low Distortion Variation with Temperature
APPLICATIONS
Precision Waveform Generation
Sweep and FM Generation
Tone Generation
Instrumentation and Test Equipment Design
Precision PLL Design
Unadjusted sine wave distortion is typically less than
0.7% with the sine wave distortion adjust pin (Pin 1)
open. Distortion levels may be improved by including a
lOOk!) potentiometer between the supplies, with the
wiper connected to Pin 1.
ABSOLUTE MAXIMUM RATINGS
Frequency sweeping or FM is accomplished by applying modulation to Pins 7 and 8 for small deviations, or
only Pin 8 for large shifts. Sweep range typically exceed 1000:1.
Power Supply
36V
Power Dissipation (package limitation)
750 mW
Ceramic Package
6.0 mW/oC
Derate Above + 25°C
Plastic Package
625 mW
5 mW/oC
Derate Above +25°C
Storage Temperature Range
- 65°C to + 150°C
The square wave output is an open collector transistor;
output amplitude swing closely approaches the supply
voltage. Triangle output amplitude is typically 1/3 of the
supply, and sine wave output reaches 0.22VS.
1-217
XR·8038A
ELECTRICAL CHARACTERISTICS
Test CondHlons: Vs = ±SV to ± lSV, TA = 2SoC, RL = .1 MO, RA = RB = 10 kO, Cl = 3300 pF, Sl closed,
unless otherwise specified.
.
XR-B03BAM
PARAMETERS
MIN
TYP
XR-B03BAC
MAX MIN
TYP
MAX
UNITS
12
30
±lS
20
V
V
mA
CONDITIONS
GENERAL CHARACTERISTICS
Supply Voltage, Vs
Single Supply
Dual Supplies
Supply Current
10
±S
30
±lS
lS
12
10
±S
Vs = ± 10V (Note 1)
FREQUENCY CHARACTERISTICS (Measured at Pin 9
Range 01 Adjustment
Max. Operating Frequency
Lowest Practical Frequency
Max. FM Sweep Frequency
FM Sweep Range
FM linearity
Range 01 Timing Resistors
Temperature Stability
XR-8038AM
XR-8038AC
Power Supply Stability
1
1
MHz
0.001
0.001
Hz
100
1000:1
0.1
100
1000:1
0.2
kHz
O.S
SO
1000
O.S
100
-
1000
-
-
20
O.OS
O.OS
%
kO
RA = RB = SOOO,
Cl = 0, RL = lS kO
RA = RB = 1 MO,
Cl = SOO "F
Sl Open (Note 2 & 3)
Sl Open (Note 3)
Values 01 RA and RB
ppm/DC TA = -SsoC to + 12SoC
ppm/DC TA = O°C to + 70°C
%N (Note 4)
OUTPUT CHARACTERISTICS
Square-Wave
Amplitude
Saturation Voltage
Rise Time
Fall Time
Duty Cycle Adjustment
Triangle/Sawtooth/Ramp
Amplitude
linearity
Output Impedance
SineWave Amplitude
Distortion
Unadjusted
Adjusted
0.9
0.98
0.2
100
40
0.9
0.4
2
0.3
0.2
98
0.33
O.OS
200
0.22
~THD/~T
0.2
1.S
Note 1: Currents through RA ad RB not included.
Note 2: Vs = 20V,1 = 10 kHz, RA = RS = 10kO.
Note 3: Apply sweep ·voltage at Pin 8.
2/3 Vs :S Vsweep :S VSN.
Note 4: 10V:s VS:S 30Vor ±SV:s VS:S ±lSV.
Note 5: Pin 12 open circuited (No 81 kO resistor as
standard 8038).
.
Note 6: Triangle duty cycle set to SO%, use RA and
RB·
2
0.3
0.7
O.S
O.S
.
1-218
0.98
0.2
100
40
x Vs
O.S
98
x Vs
0.33
0.1
200
0.22
0.8
O.S
0.3
V
nsec
nsec
%
Measured at Pin 9
RL = 100 kO
Isink = 2 mA
RL = 4.7 kO
RL = 4.7 kO
Measured at Pin 3
RL = 100kO
%
x Vs
3
%
%
%
lout = SmA
RL = 100kO
RL = 1 MO (Note S & 6)
RL = 1 MO (Note S & 6)
Multipliers/Modulators
I
I
I
I
I
I
I
I
I
I
!
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
XR·2208
Operational Multiplier
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2208 operational multiplier combines a fourquadrant analog multiplier (or modulator), a high frequency buffer amplifier, and an operational amplifier in
a monolithic circuit that is ideally suited for both analog
computation and communications signal processing
application. As shown in the functional block diagram,
for maximum versatility the multiplier and operational
amplifier sections are not internally connected. They
can be interconnected, with a minimum number of external components, to perform arithmetic computation,
such as multiplication, division, square-root extraction.
The operational amplifier can also function as a preamplifier for low-level input signals, or as a post detection amplifier for synchronous demodulator applications. For signal processing, the high frequency buffer
amplifier output is available at pin 15. This multiplier/
buffer amplifier combination extends the small signal
3-db bandwidth to 8-MHz and the transconductance
bandwidth to 100 MHz.
v+
MULTIPLIER
OUTPUTS
HIGH FREQ.
OUTPUT
L
1
OPAMP
X
INPUT
INPUTS
COMMON
J
y
INPUT
COMPo
r
l
OPAMP
OUTPUT
Y·GAIN
v-
X-GAIN
ABSOLUTE MAXIMUM RATINGS
The XR-2208 operates over a wide range of supply voltages, ±4.5V to ± 16V. Current and voltage levels are
internally regulated to provide excellent power supply
rejection and temperature stability. The XR-2208 operates over a O°C to 70°C temperature range. The XR2208M is specified for operation over the military temperature range of - 55°C to + 125°C.
Power Supply V +
+ 18 Volts
-18 Volts
V-
Power Dissipation
Ceramic Package
Derate above +25°C
Plastic Package
Derate above + 25°C
Storage Temperature Range
FEATURES
750mW
6mW/oC
625mW
5 mW/oC
-65°C to +150°C
Maximum Versatility
Independent Multiplier, Op Amp, and Buffer
Excellent Linearity (0.3% typ.)
Wide Bandwidth
3 dB BW.-8 MHz typo
3° Phase Shift B.w.-1.2 MHz typo
Transconductance B.W.-100 MHz typo
Simplified Offset Adjustments
Wide Supply Voltage Range (± 4.5V to ± 16V)
ORDERING INFORMATION
APPLICATlDNS
SYSTEM DESCRIPTION
Analog Computation
Triangle-to-Sinewave
Multiplication
Converter
AGC Amplifier
Division
Squaring
Phase Detector
Square-Root
Phase-Locked Loop (PLL)
Signal Processirig
Applications
AM Generation
Motor Speed Control
Frequency Doubling
Precision PLL
Frequency Translation
Carrier Detection
Synchronous AM Detection Phase-Locked AM
Demodulation
The XR-2228 multiplier/detector contains a four quadrant multiplier and a fully independent operational amplifier. The four quadrant multiplier has fully differential
X and Y inputs and outputs. Both inputs have 3 MHz dynamic response and 100 MHz transconductance bandwidth. The operational amplifier features high gain and
a large common mode range. The device is powered by
4.5V to 16V split supplies.
Part Number
Package
Operating Temperature
XR-2208M
XR-2208N
XR-2208P
XR-2208CN
XR-2208CP
Ceramic
Ceramic
Plastic
Ceramic
Plastic
- 55°C to + 125°C
O°C to + 70°C
O°C to + 70°C
O°C to + 70°C
O°C to + 70°C
For higher frequency applications, consider the XR2208.
1-219
XR·2208
ELECTRICAL CHARACTERISTICS
Tast,Conditions: Supply Voltage = ± 15V, TA
= 25°C,
XR-2208/
XR-2208M
PARAMETERS
MIN
unless otherwise specified.
XR-2208C
TYP
MAX MIN
TYP
4
±16 ±4.5
7
5
MAX UNITS FIGURES
CONDITIONS
I. GENERAL
±4,5
Supply Voltage
Supply Current
±16
8
Vdc
mA
2
See Figure 11
Measured at Pin 16
II. MULTIPLIER SECTION
No external offset trim
Non-linearity
(Output Error
in % of Full Scale)
Feedthrough
a) With Offset Adj.
X-input
Y·input
b) No Offset Adj.
X-input
Y-input
Temperature Coefficient of Scale
Factor
Input Bias Current
X, Y input
Common input
Input Resistance
Output Offset Voltage
Avg. Temp. Drift
Dynamic Response
3-dB Bandwidth
X-input
Y-input
3° Phase-Shift Bandwdith
1 % Absolute Error Bandwidth
Transconductance Bandwidth
Output Impedance
0.5
0.5
1.0
0.5
0.5
0.8
1.0
1.0
45
60
80
100
70
90
120 mVp-p
150 mVp-p
Vx
Vy
= 20 Vp-p "v: = 0
= 20 Vp-p, x = 0
mVp-p
mVp-p
Vx
Vy
%IOC
= 20 Vp-p, Vx = 0
= 20 Vp-p, Vx = 0
how
120
120
±0.07
0.5
200
200
'±0.07
2
4
1.0
6
12
50
0.5
80
3
6
1.0
8
16
80
0.5
140
%
%
%
~
3
Mil
2
2
2
mV
2
,.A
mV/oC
5
6
3
Vy = ±10V, -10V < Vx < +10V
Vx = ±10V, -10V < V~ < +10V
TLOW :S TA :S THIGH ( ate 1)
f = 50 Hz
0.3
0.3
0.7
6
3
8
4
1.2
30
100
6
:S TA :S THIGH (Note 1)
13,15 of Figure 2
14 of Figure 2
Measured looking into Pin 3 or
Pin 5
Measured across Pins 1 and 2
TLOW :S TA :S THIGH
See Definition Section
8
4
1.2
30
100
6
MHz
MHz
MHz
kHz
MHz
kll
200
1.0
11
5
Measured looking into Pin 15
mV
6
RS < 5011
TLOW :S TA :S THIGH
IB1- I B2
IB1 + IB2
Measured looking Into Pins 1 or 2
III. BUFFER AMPLIFIER
Output Impedance
Gain
200
1.0
IV_ OPERATIONAL AMPLIFIER
Input Offset Voltage
Temperature Coefficient of Input
Offset Voltage
Input Offset Current
1
6
4
75
Input Bias Current
30
200
Voltage Gain
Differential Input Resistance
Output Voltage Swing
Input Common
Mode Range
Common Mode Rejection
Output Resistance
Slew Rate
Power Supply Sensitivity
Note 1: TLOW
70
0.5
±10
+12
-10
70
75
3
±12
+14
-12
90
2
0.5
3
20
2
9
70
±10
+12
-10
70
30
= -55°C, THIGH = + 125°C for XR-2208M
6
30
",V/oC
10
100
nA
6
50
300
nA
6
dB
Mil
V
6
6
2
RL'" 2K, Va
75
3
±12
+14
-12
90
2
0.5
V
dB
kll
6
6
V/p.S
7
Gain = 1, RL
Cc = 20 pF
30
",VN
6
RS :S 10K
=
±10V, f
= 20 Hz
RL '" 2K, TLOW :S TA :S THIGH
f
= 20 Hz
6
'" 2K CL :S 100 pF
T LOW = O°C, THIGH = + 70°C for XR-2208IXR-2208C
CAUTION: When using only the op amp or only the multiplier section of the XR-2208, the Input terminals to the unused
section must be grounded. Thus, when using the multiplier section alone, ground pins 13 and 14; when using
the op amp section alone, ground pins 3, 4 and 5.
1-220
XR·2208
"'"
"
'O"F
,.
t15\1
51.
Figure 1. Test Circuit lor Quiescent Supply Current.
Multiplier Input Bias and Output Offset Voltage.
51.
·15"
Figure 4. Test Circuit lor Multiplier Small-Signal Bandwidth
lor X-Input (For Y-Input. reverse connections
between Pin 3 and 5).
XR 1108
'.,
Y,. -=:-<>"""i'1---1
'"
>---;...:.:0-"-",,,,-,,---0 Yo
..
"Y
Figure 2. Linearity Test Circuit
Figure 5. Test Circuit lor Op Amp DC Parameters
Figure 3. Test Circuit lor Feedthrough Measurement.
X-Input Feedthrough = Vz with S1. open. S2 closed.
Y-Input Feedthrough = Vz with S1. closed. S2 open.
Figure 6. Op Amp AC Test Circuit
plier with scale factor K can be written as:
DEFINITION DF MULTIPLIER TERMS
Vz = K[(Vx
NONLINEARITY: Nonlinearity is the maximum deviation
of the output voltage from a straight·line transfer func·
tion. It is measured separately for the X and Y inputs
and is specified as (%) of full scale output.
+
-5
~
~
·12
-,.
-15
,.':--J.,.
- ,. L....L-1:-..L.---'.•':-....J.,.,--.''=-2---''
•
75
+'00
'bV
-,1OV
+125
"sonJ "o . . . . \"..., t - C
2
•
R, .. SOOU'cc "2.SpF
~
C~"SPF
Rl·~.ccl.
~
R,'"SK
"
20pF
----
SUPf'LY VOL TACif.,VOl TS
Figure 10. Multiplier Input Dynamic
Range vs Powar Supply
60
2
5
~
+50
R, sO,cc-a
R1
j
'5
"
0
'DO
a.
2
~
25
Figure 9. Temperature Dependence of
Output Nonlinearity for X or Y Inputs
(See Figure 2).
r----""T'----,-----,
0
---
.i
- 25
TA' AMBIENT TEMPERATURE lOCI
Figure 8. Small-Signal Frequency
Response for the Multiplier Saction.
(Output Measured at Pin 15-See
Fig. 4) .
Figure 7. Supply Currant vs Supply
Voltage
~
~
55
FReaUENCY (MHz)
SUPPLY VOLTAGE, VOL TS
~
'lSV
100 HI
SVPPl V VOLTAGE, VOLTS
Figure 11. Op Amp Output Swing vs
Power Supply
1
1 kHz
"\
10kHz
100kHz
1 MHz
fRE~UENCY
Figure 12. Op Amp Frequency
Response
In most arithmetic applications the multiplier and op
amp sections of the XR-2208 are interconnected as
shown in Figure 14. In such applications, over·all scale
factor K can be written as:
K = (Km)(Ka) =
(~)
VxYy
'.
(Vz)
Va
..
where Km is the gain constant of the multiplier section,
and Ka is the gain of the op amp stage in Figure 14, Va
is the multiplier output across pins 1 and 2, and Vz is
the op amp output at pin 11. With reference to Figure
14, these gain constants can be expressed as:
Km =<
Figura 13. Offset Adjustment
MULTIPLIER BANDWIDTH: Depending on the particular
application, a different definition of "multiplier band·
width" may be used. The most commonly accepted
definitions are:
Rf
~(volts)-1; Ka=<-6 + Ri
RxRy
a) 3-dB Bandwidth: Frequency where the multiplier
output is 3-dB below its low frequency (f = 20 Hz)
level.
where all resistors are in kO.
Thus, overall scale factor K can be adjusted by varying
Rx , Ry, Rf. For fine adjustment of the scale factor, K, an
additional potentiometer can be included into the cir·
cuit, as shown in Figure 14.
b)· 3° Phase Shift Bandwidth: Frequency where the net
phase shift across the multiplier is equal to 3°.
c) 1 '~. Absolute Error Bandwidth: Frequency where
the phase vector error between the actual and ideal
output vectors is equal to 1 %. This frequency is
reached when the net phase shift across the multi·
plier is equal to 0.01 radian or 0.57°.
INPUT DYNAMIC RANGE: The maximum peak signal
which can be applied to the X or Y inputs for a given
supply voltage without impairing linearity. (See Figure
10).
1-222
XR·2208
DP AMP INPUTS (PINS 13 AND 14)
d) Transconductance Bandwidth: Frequency where
the transconductance of the multiplier drops 3-dB
below its low frequency value. This bandwidth defines the frequency range of operation for phasedetector and synchronous AM detector applications.
DESCRIPTION OF CIRCUIT CONTROLS
Pin 13 is the non-inverting and pin 14 the inverting inputs for the op amp section. In most multiplier applications, these terminals are connected to the multiplier
outputs (pins 1 and 2). Note: When the op amp section Is not
used, these terminals should be grounded.
MULTIPLIER INPUTS (PINS 3, 4, AND 5)
OP AMP COMPENSATION (PIN 12)
The X and Y inputs to the multiplier are applied to pins 3
and 5 respectively. The third input (pin 4) is common to
both X and Y portions of the multiplier, and in most applications serves as a "reference" or ground terminal.
The typical bias current at the multiplier inputs is 3 /LA
for the X- and Y- inputs and 6 /LA for the "common" terminal. In circuit applications such as "synchronous AM
detection" or "frequency doubling" where the same input signal is applied to both X and Y inputs, pin 4 can be
used as the input terminal since it is common to both X
and Y sections of the multiplier.
The op amp section can be compensated for unconditional stability with a 20 pF capacitor connected between pin 12 and pin 11. For op amp voltage gains
greater than unity, this compensation capacitance can
be reduced to improve slew rate and small signal bandwidth as shown in Figure 12.
OP AMP OUTPUT (PIN 11)
This terminal serves as the output for the op amp section. It is internally protected against accidental short
circuit conditions, and can sink or source 10 mA of current into a resistive load. In most multiplier applications,
pin 11 is the actual XR-2208 output, with the op amp inputs being connected to the multiplier outputs.
MULTIPLIER OUTPUTS (PINS 1 AND 2)
The differential output voltage, Vo , across these terminals is proportional to the linear product of voltages Vx
and Vy applied to the inputs. Vo can be expressed as:
Vo
BUFFER AMPLIFIER OUTPUT (PIN 15)
~ (R~~y) (VXvy)
The buffer amp is internally connected to the multiplier
section. The buffer amp has unity voltage gain, and provides a low-impedance output at pin 15 for the multiplier section. The buffer amp is particularly useful for high
frequency operation since it minimizes the capacitive
loading effects at the multiplier outputs.
where all voltages are in volts and the resistors are in
kO. Rx and Ry are the gain control resistors for X and Y
sections of the multiplier.
The buffer amplifier is activated by connecting a load
reSistor, R1, from pin 15 to ground. When it is not used,
pin 15 can be left open circuited. However, since the
buffer amplifier output is a low impedance pOint, reasonable care should be taken to avoid burnout due to
accidental short circuits. The maximum dc current
drawn from pin 15 should be limited to 10 mA. The dc
voltage at pin 15 is typically 4.5 volts below V + .
The common-mode dc potential at the multiplier outputs is approximately 3 volts below the positive supply.
One of the multiplier outputs (pin 1) is internally connected to the unity-gain buffer amplifier input for highfrequency applications.
In most analog computation operations, such as multiplication, division, etc., pins 1 and 2 are dc coupled to
the op amp inputs (pins 13 and 14). The final output, Vz,
is then obtained from the op amp output at pin 11, as
shown in Figure 14.
APPLICATIONS INFORMATION
PART I: ARITHMETIC OPERATIONS
X AND Y GAIN ADJUST (PINS 6, 7, B, 9)
Multiplication
The gains of the X and Y sections of the multiplier are
inversely proportional to resistors Rx and Ry connected
across the respective gain terminals. Tne multiplier
conversion gain, Km , can be expressed as:
Km
For most multiplication applications, the multiplier and
op amp sections are interconnected as shown in Figure
15 to provide a single-ended analog output with a wide
dynamic range. The circuit of Figure 14 provides a linear output swing of 10V for maximum input signals of
10V, with a scale factor K = 0.1. The trimming procedure for the circuit is as follows:
== ~ (volts)-1
RxRy
where Rx and Ry are in kO.
1. Apply OV to both inputs and adjust the output offset
to OV using the output offset control.
X AND Y OFFSET ADJUST (PINS 7 AND 8)
Two of the gain-control terminals, pins 7 and 8, are also
used for adjusting X and Y offsets. Figure 13 shows the
typical adjustment circuitry which can be connected to
these pins to nUll-out input offsets.
2. Apply 20V pop at 50 Hz to the X-input and OV to the
Y-input. Trim the V-offset adjust for minimum peak-topeak output.
.
1-223
XR·2208
Dividing Circuit
3. Apply 20V p.p to the Y·input and OV to the X-input.
Trim X-offset adjust for minimum peak-to-peak output.
Recommended circuit connection for performing analog division is shown in Figure 16. This circuit uses the
multiplier in the feedback path of the op amp. For the
circuit shown, Vo = + 10 Vz/Vx where Vx < 0 and Vz
can have either sign. Positive values of Vx are not allowed, since this will reverse the polarity of the feedback loop, causing positive feedback and latchup.
4. Repeat step 1.
5. Apply + 10V to both inputs and adjust scale factor
for Vo = + 10V. This step may be repeated with different amplitudes and polarities of input voltages to
optimize accuracy over the entire range of input
voltages, or over any specific portion of input voltage range.
This latchup mode is nondestructive to the XR-2208,
and is common to all analog division circuits. The divide
circuit is trimmed as follows:
Squaring Circuit
1. Apply Vz = 0 and trim the output offset adjustment
for constant output voltage as Vx is varied from - 1V
to -10V.
The recommended circuit connection for squaring applications is shown in Figure 15. This circuit is the same
as the basic multiplier circuit with both inputs tied together, except only one input offset adjustment is necessary. Trimming procedure for the squaring circuit is
as follows:
2. Keeping Vz = 0, and applying Vx = -10V, trim the
Y-offset adjust until Vo = O.
1. Apply 0 volts to the input and adjust the output offset
to zero.
3. Let Vz = Vx and/or Vz = - Vx and trim the X-offset
adjustment for constant output voltage as Vx is varied from -1V to -10V.
2. Apply 1.0V to the input and adjust the Y-offset until
Vo = 0.10V.
4. Repeat steps 1 and 2 if step 3 required a large initial
adjustment.
3. Apply 10V to the input and adjust the scale factor
until Vo = + 10V.
5. Keeping Vz = Vx , adjust the scale factor trim for Vo
-10V as Vx is varied from - 1V to - 10V.
4. Apply -10V to the input and check that Vo = + 10V.
If not, repeat steps 1 through 3. Some compromise
may be necessary in scale factor adjustments given
in steps 3 and 4.
i---'~~~-----l
, .n"
t
••.. '1 ••• ,
!~"'II
',_.,..... T,I·"
II
I
b'
lqoll
L~~~~_~~~ ___
.J
Figure 16. Dividing Circuit
Square Root Circuit
This is essentially the dividing circuit with the X input
tied to the output. Thus, the voltage on the Z input is divided by the output voltage, i.e. the output is proportional to the square root of the input. A diode is included in
series with the output to prevent a latchup condition
which would result if Vz were allowed to go negative.
The square root circuit may be trimmed as a divider by
disconnecting the X-input from the output, keeping Vz
> 0 and Vx < O. The square root circuit may also be
trimmed in the closed-loop mode by the following procedure:
Figure 14. Multiplication Circuit
",
~
.,.0"511
·1'" l"!>1t
"OJ
1. ApplyVz = +O.10Vandtrimtheoutputoffsetadjust
for Vo = -0.316V.
."
100"
2. Apply Vz = + 0.9V and trim the X-offset adjust for
Vo = -3.0V.
'"
Figure 15. Squaring Circuit
1-224
XR·2208
3. Apply Vz = + 10V and trim the scale factor adjust
for Vo = -10V.
SYNCHRONOUS AM DETECTION
Figure 18 is a typical circuit connection for synchronous AM detection for carrier frequencies up to 100
MHz. The AM input signal is applied to the multiplier
"common" terminal (pin 4). The Y-gain terminals are
shorted, and this section of the multiplier serves as a
"limiter" for input signals O!: 50 mVrms; the X-section of
the multiplier operates in its linear mode. The low-pass
filter capacitors, Cl, at pins 1 and 2 are used to filter
the carrier feedthrough. If deSired, the op amp section
can be used as an audio preamplifier to increase the
demodulated output amplitude.
4. Repeat steps 1 through 3 until desired accuracy is
achieved.
EQUIVALENT SCHEMATIC DIAGRAM
TRIANGLE-TO-SINEWAVE CONVERSION
A triangular input can be converted into a low distortion
(THO < 1 %) sinusoidal output with the XR-2208. A recommended connection for this application is shown in
Figure 19. The triangle input signal is applied to the
X-input (pin 3). The multiplier section rounds off the
peaks of this input and converts it to a low distortion
sine wave. For the component values shown in Figure
19, the recommended input signal level at pin 3 is '"
300 mV pp in order to obtain a 2V pp sine wave output
at pin 15. This waveform can be further amplified using
the op amp section to provide high level (10V pp), low
distortion output at pin 11.
PART II: SIGNAL PROCESSING
AM GENERATION
Figure 17 is the recommended circuit connection for
generating double side-band (OSB) or suppressed carrier AM signals. Modulation and carrier inputs are applied to the X and Y inputs respectively. The carrier level at the output can be adjusted by the dc voltage applied to pin 3. For suppressed carrier operation, the
carrier feedthrough can be further reduced by using the
X and Y offset adjustments. In this application, the
unity-gain buffer amplifier section will provide a low impedance output if desired. If the buffer amp is not used,
pin 15 should be open circuited to reduce power dissipation.
TRIAN(jLE INPUT
'V'v
Typical carrier suppression without offset adjustment is
40 dB for frequencies up to 1 MHz, and 30 dB for frequencies up to 10 MHz. For low frequency applications
(f < 10kHz), carrier suppression can be reduced to
60 dB by using the offset adjustment controls.
OUTPUT
oI""IHlTuO(
A.,
"
"'.'
0-;<--"""'"-'-'"--'
OOOC:,,~:'Dfotc
Figure 19. Trlangle-to-Sine Converter
PHASE DETECTION
IOO ......... ~ •• O~
The multiplier section can be used as a phase detector.
A recommended circuit connection is shown in Figure
20. The reference input is applied to pin 5, and the input
signal whose phase is to be detected is applied to pin 3.
The differential dcvoltage, Vep' at the multiplier outputs
(pins 1 and 2) is related to the phase difference, ep, between the two input Signals, Vl and V2, as:
_~u"o
O.U~TIOto.
(lOon,
Figure 17. AM Generation
Vep = Kd cos
ep
where Kd is the phase detector conversion gain. For input signals 0!:50 mV rms, Kd is =2V/radian and is independent of signal amplitude. For lower input amplitudes, Kd decreases linearly with the decreasing input
level. The capacitors Cl at pins 1 and 2 provide a lowpass filter with a time constant Tl = Rl Cl, where Rl
= 6 kO is the internal impedance level at these pins.
Figure 18. Synchronous AM Detector.
1-225
XR·2208
If needed, the phase conversion gain can be increased
by using the op amp section of the XR-2208 to further
amplify the output voltage, V",. The XR-2208 is suitable
for phase detection for input frequencies up to 100
MHz.
V.
OUTPUT
J!-o---o
'--------------~JW;-o
INPUT 1
..,
v,· E, ,in Iw,tJ
'REFERENCE INPUT!
Figure 22. Precision PLL
::::t&OmV,rml.
Figure 20_ Phase· Detector Circuit
PHASE·LOCKEO AM AND CARRIER DETECTION
PART III: PHASE· LOCKED LODP APPLICATIONS
The XR-2208 can be used as a "quadrature detector" in
conjunction with monolithic PLL circuits to perform
phase-locked AM demodulation and for carrier-level detection. Figure 23 shows a recommended circuit connection for such applications. The XR-210 or XR-215
monolithic PLL circuits can be adjusted to lock on the
desired input AM signal and re-generate the unmodulated carrier. This carrier frequency appears across the
timing capacitor, Co' of the PLL and is used as the "reference input" to the XR-220B multiplier. The AM signal
is applied simultaneously to the PLL input and to the
XR-2208 multiplier input (pin 3), as shown in Figure 23.
MOTOR SPEED CONTROL
A motor speed control where the frequency of the motor is "phase-locked" to the input reference frequency,
fr' is shown in Figure 21. The multiplier section of the
XR-2208 is used as a phase-comparator, comparing the
phase of the tachometer output signal with the phase of
the reference input. The resulting error voltage across
pins 1 and 2 is low-pass filtered by capaCitors C1 and
amplified by the op amp section. This error signal is
then applied to the motor field-winding to phase-lock
the motor speed to the input reference frequency.
The demodulated signal is then low-pass filtered by capacitor C1 at the multiplier output, and can be amplified
further to the desired audio level by using the op amp
section of the XR-2208.
In the carrier detector applications, the op amp is used
as a voltage comparator and produces a "high" or
"low" level logic signal at the op amp output when the
input carrier level reaches a detection threshold level
set by an external potentiometer. The output from the
carrier detector can then be used to enable the "Iogicoutput" stage of the XR-210 FSK modem.
The phase-locked AM or carrier detector system of Figure 23 shows a high degree of frequency selectivity, as
determined by the monolithic PLL "capture" bandwidth.
Figure 21. Motor Speed Control Circuit
PRECISION PLL
A precision phase-locked loop may be constructed using an XR-2207 voltage controlled oscillator and an
XR-2208. (See Figure 22.) Due to the excellent temperature stability and wide sweep range of the XR-2207 this
PLL circuit exhibits especially good stability of center
frequency and wide lock range. In this application the
XR-2208 serves as a phase comparator and level shifter. Resistor RL adjusts the loop gain of the PLL, thus
varying the lock range. Tracking range may be varied
from about 1.5:1 up to 12:1. For large values of RL, temperature stability of center frequency is better than
30 ppm/oC.
·CC·COUOl.otCIC ..... "C'TOR
c."Y""PtAl'oltI10R
Figure 23. Phase·Locked AM Demodulation or Carrier
Detection
1-226
XR·2228
Monolithic Multiplier/Detector
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2228 is a monolithic multiplier/detector circuit
especially designed for interfacing with integrated
phase-locked loop (PLL) circuits, to perform synchronous AM detection and triangle-to-sinewave conversion. It combines a four-quadrant analog multiplier (or
modulator) and a high-gain operational amplifier in a
single monolithic circuit.
MUL TlPLIER
MUl TlPLIER
OUTPUT
OUTPUT
I
2
L
J
tVCC
MUl TlPlIER
)C.·INPU1S
As shown in the equivalent schematic diagram, the
four-quadrant multiplier section is designed with fully
differential X- and Y-inputs and differential outputs. For
maximum versatility, the multiplier and the operational
amplifier sections are not internally connected. The operational amplifier can also function as a pre-amplifier
for low-level input signals, or as a post-detection amplifier for synchronous demodulation, phase-detection or
for sine-shaper applications.
MUL lIPll(R
V-INPUTS
L_
COMPo
5
OP AMP
OUTPUT
V-GAIN
>C-GAIN
FEATURES
Independent Multiplier and Op Amp Sections
Differential X and Y Inputs
Interfaces with all PLL and VCO Circuits
Wide Common Mode Range
Wide Transconductance Bandwidth (100 MHz, Typ.)
Wide Supply Voltage Range (± 4.5V to ± 16V)
ORDERING INFORMATION
APPLICATIONS
Phase-Locked Loop Design
Phase Detection
Synchronous AM Detection
AM Generation
Triangle-to-Sinewave Conversion
Frequency Translation
Package
Operating Temperature
XR-2228M
XR-2228N
XR-2228P
XR-2228CN
XR-2228CP
Ceramic
Ceramic
Plastic
Ceramic
Plastic
- 55°C to + 125°C
-40°C to +85°C
-40°C to +85°C
O°C to + 70°C
O°C to + 70°C
SYSTEM DESCRIPTION
The XR-2228 multiplier/detector contains a four quadrant multiplier and a fully independent operational amplifier. The four quadrant multiplier has fully differential
X and Y inputs and outputs. Both inputs have 3 MHz dynamic response and 100 MHz transconductance bandwidth. The operational amplifier features high gain and
a large common mode range. The device is powered by
4.5V to 16V split supplies.
ABSDLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Ceramic Package
Derate above +25°C
Plastic Package
Derate above +25°C
Storage Temperature Range
Part Number
± 18 Volts
750 mW
6 mW/oC
625 mW
5 mW/oC
- 65°C to + 150°C
For higher frequency applications, consider the XR2208.
1-227
XR·2228
ELECTRICAL CHARACTERISTICS
Test CondHlons: Supply Voltage
=
± 15V, TA
= 25°C, unless otherwise specified.
XR·2228M
XR·2228/XR·2228C
TYP MAX MIN TYP MAX UNITS FIGURES
PARAMETERS
I. GENERAL
MIN
Supply Voltage
Supply Current
±4.5
4
±16 ±4.5
7
5
±16
S
Vdc
mA
1
2
CONDITIONS
See Figure 11
Measured at Pin 15
II. MULTIPLIER/MODULATOR SECTION
Non-linearity
(Output Error in % of
Full Scale)
Feedthrough
a. With Offset Adj.
X-input
Y-input
b. No Offset Adj.
X-input
Y-input
Temperature Coefficient
of Scale Factor
Input Bias Current
X or Y inputs
Input Resistance
Output Offset Voltage
Avg. Temp. Drift
Dynamic Response
3-dB Bandwidth
X-input
Y-input
3° Phase-Shift
Bandwidth
1 % Absolute Error
Bandwidth
Transconductance
Bandwidth
Output Impedance
0.3
0.5
0.5
1.0
%
0.3
0.5
0.5
1.0
%
0.7
1.0
O.S
45
60
80
100
70
90
120
120
±0.07
0.5
2
1.0
50
0.5
%
120
150
3
1.0
SO
0.5
SO
3
= 20 Vp-p Vy = 0
= 20 Vp-p, Vx = 0
Vx = 20 Vp-p, Vx = 0
Vy = 20 Vp-p, Vx = 0
fLow s TA s THIGH (Note 1)
1
2
2
Measured at Pins 2, 3, 4 or 5.
Measured at Pins 2, 3, 4 or 5.
Measured across Pins 1 and 16
TLOW s TA s THIGH
See Definition Section
mVp-p
mVp-p
200
200
±0.07
6
mVp-p
mVp-p
%IOC
S
p.A
140
MO
mV
mV/oC
4
1
1
1
1
3
3
1
MHz
MHz
MHz
30
30
kHz
100
100
MHz
5
5
kO
3
3
1
No external offset trim
Vy = ±10V, -10V < Vx <
+10V
Vx = ±10V, -10V < Vy <
+10V
fLow s TA s THIGH (Note 1)
f = 50 Hz
Vx
Vy
Measured looking Into Pins 1
or 16
III. OPERATIONAL AMPLIFIER SECTION
Input Offset Voltage
Temp. Coef. of Input
Offset Voltage
Input Offset Current
1
6
3
20
2
9
6
30
p.V/oC
4
75
10
100
nA
5
Input Bias Current
30
200
50
300
nA
5
Voltage Gain
70
75
Differential Input
Resistance
Output Voltage Swing
0.5
3
±10
±12
+12
-10
70
+14
-12
90
2
0.5
Input Common Mode
Range
Common Mode Rejection
Output Resistance
Slew Rate
Power Supply Sensitivity
Note 1:
30
70
mV
5
75
dB
5
3
MO
5
±10
±12
V
+12
-10
70
+14
-12
90
2
0.5
V
dB
kO
V/p.s
5
5
30
p.VN
5
fLow =
fLow =
RS
<
500
TA
fLow s
s
THIGH
IBl - IB2
181 + 182
2
Rl ~ 2K, Va = ±10V,
f = 20 Hz
Rl ~ 2K, TLOW
s THIGH
5
5
f
s
TA
= 20 Hz
Gain = 1, Rl ~ 2K,
Cl s 100 pF Cc
RS s 10K
= 20 pF
-55°C, THIGH = + 125°C for XR-222SM
TlOW = O°C, THIGH = + 70°C for XR-222SC
-40°C, THIGH = +S5°C for XR-222S
CAUTION: When using only the op amp or only the multiplier section of the XR-222B, the input terminals to the
unused section must be grounded. Thus, when using the multiplier section alone, ground pins 13 and
14; when using the op amp section alone, ground pins 2. 3, 4 and 5.
1-228
XR·2228
,,
1....- - - - - - -
MUL TlPLIER - - - - - -...'11
EQUIVALENT SCHEMATIC DIAGRAM
1-229
XR·2228
+ISV
+ I!jV
0.'
20"
.7"
13
MV
RX
5.1K
S,1X
8
-16V
6.1X
7.
It
5,1X
"
_,51,1
Figura 1. Test Circuit for Quiescent Supply Current,
Multiplier Input Bias and Output Offset Voltage
Figure 4. Test Circuit for Multipllar Small-Signal Bandwidth
lor X-Input (For Y-Input, reverse connections
between Pins 2 and 5)
Va
. . .F
'"
V,"
"
-=,-0.,+--1
'B'
ADJUSTICALE
FACTOR FOR NULL IN Eo
FOR EACH POSITION OF I,
'a
LINEARITY, % ERROR"
i~,~::::
Figure 5. Test Circuit for Op Amp DC Parameters
Figura 2. linearity Tast Circuit
'"
3"K
ZOpF
Vz
Va
OUTPUT
oz.
TOXANO
VOFF$ET
A".
FIGURE 13
'''K
_ _ _-O..J
'''K
Figura 3. Test Circuit for Feedthrough Measurement. X-Input
Feedthrough = Vz with S1, open S2 closed.
Y-Input Faedthrough = Vz with S1 closed, S2
open.
Figure 6. Op Amp AC Tast Circuit
DEFINITION OF MULTIPLIER TERMS
OFFSET VOLTAGES: A four-quadrant analog multiplier
has three separate offsets: the X and Y input offsets
and the output offset. The transfer function of a practical multiplier with scale factor K can be written as:
NONLINEARITY: Nonlinearity is the maximum deviation
of the output voltage from a straight·line transfer function. It is measured separately for the X and Y inputs
and is specified as (%) of full scale output.
Vz = K[(Vx
+ --
K
+125
related to the X and Y inputs as Vz = K (Vx . Vy). The
scale factor K has the dimensions of (volts}-1 and can
be adjusted externally.
9
Ry
+100
FREQUENCY
lOOK
X OFFSET
ADJ
Rl·5O!l.~C·O
R,.!:IOOllICc- Z.5PF
IkHl
_1SV
Figure 11. Op Amp output Swing vs
Power Supply
(
+75
R, ...... ccl.20PF
tiOV
X
15K
"~
PEAK·TO PEAK
60
SUPPLY VOLTAGE. VOLTS
XR-2228
Y OFFSET
ADJ
~
z
5
6
.50
R,"O.CC·O
80
"'-..
,16
Figure 10. Multiplier Input Dynamic
Range vs Power Supply
+25
Figure 9. Temperature Dependence of
Output Nonlinearity for X or
Y Inputs (See Figure 2)
""""--
SUPPL V VOL TAGE,vOl TS
r·
0
TA• AMBIENT TEMPERATURE I"CI
/
0
i'.2
-25
100
0
.
-~5
/~
0
,/
-I
1000
5
V
./
,
100
Figure 8. Small-Signal Frequency
Response for the Multiplier
Section. (Output Measured
at Pin 16-See Fig. 4)
0
-I
1.0
FREQUENCY!MHd
Figure 7. Supply Current vs Supply
Voltage
L
o
-30
~I
-
I-
0."
SUPPLY VOLTAGE, VOLTS
,
0.50
Y'N~
-zo
, mA!·"'.v:----""",,!;;v------:'-!:,2V~---'7!"V
0.15
X·INPUT
Vo )
VxYx
(Vz)
Vo
where Km is the gain constant of the multiplier section,
and Ka is the gain of the op amp stage in Figure 14. Vo
is the multiplier output across pins 1 and 16, and Vz is
the op amp output at pin 11. With reference to Figure
14, the gain constants can be expressed as:
lOOK
Iv
Figure 13. Offset Adjustment
where x and y are the offset voltages associated with
the respective inputs, <1>0 is the offset voltage of the out·
put. Vz is the multiplier output, Vx and Vy are the multi·
plier inputs. As shown in Figures 13 and 14, each of
these offset voltages can be nulled to zero by external
adjustments.
25
Km = - - (volts) -1;
RxRy
Rf
Ka=-6 + Ri
where all resistors are in kilo-ohms.
Thus, overall scale factor K can be adjusted by varying
Rx , Ry, Rf. For fine adjustment of the scale factor, K, an
additional potentiometer can be included into the circuit, as shown in Figure 14.
SCALE FACTOR, K: The constant of proportionality that
relates the multiplier output to the X and Y inputs. If the
offset terms are neglected, the multiplier output, Vz . is
1-231
XR·2228
X AND Y GAIN ADJUST (PINS 6, 7, 8, 9): The gains of the X
and Y sections of the multiplier are inversely proportional to resistors Rx and Ry connected across the resp,ective gain terminals, The multiplier conversion gain,
Km , can be expressed as:
INPUT DYNAMIC RANGE: The maximum peak signal
which can be applied to the X or Y inputs for a given
supply voltage without impairing linearity. (See Figure
10).
MULTIPLIER BANDWIDTH: Depending on the particular
application, a different definition of "multiplier bandwidth" may be used. The most commonly accepted
definitions are:
Km ==
where Rx and Ry are in kll,
X AND Y OFFSET ADJUST (PINS 7 AND 8): Two of the gaincontrol terminals, pins 7 and 8, are also used for adjusting X and Y offsets. Figure 13 shows the typical adjustment circuitry which can be connected to these pins to
null-out input offsets.
b) 3° Phase Shift Bandwidth: Frequency where the net
phase shift across the multiplier is equal to 3°.
c) 1 % Absolute Error Bandwidth: Frequency where the
phase vector error between the actual and ideal output vectors is equal to 1 %. This frequency is
reached when the net phase shift across the multiplier is equal to 0.01 radian or 0.57°.
OP AMP INPUTS (PINS 13 AND 14): Pin 13 is the noninverting and pin 14 the inverting inputs for the op amp section. In most multiplier applications, these terminals are
connected to the multiplier outputs (pins 1 and 16).
Note: When the op amp section is not used, these terminals
should be grounded.
d) Transconductance Bandwidth: Frequency where the
transconductance of the multiplier drops 3-dB below
its low frequency value. This bandwidth defines the
frequency range of operation for phase-detector and
synchronous AM detector applications.
OP AMP COMPENSATION (PIN 12): The op amp section
can be compensated for unconditional stability with a
20 pF capacitor connected between pin 12 and pin 11.
For op amp voltage gains greater than unity, this compensation capacitance can be reduced to improve slew
rate and small signal bandwidth as shown in Figure 12.
DESCRIPTION OF CIRCUIT CONTROLS
MULTIPLIER INPUTS (PINS 2, 3, 4 AND 5): These four terminals provide the differential inputs to the X- and
Y-sections of the multiplier, respectively. The output will
be a linear product of the two voltages, Vx and Vy, ap·
plied differentially across pins (2,3) and (4,5). Typical input bias current at the multiplier inputs is approximately
3 "A, for each of the four inputs. In circuit applications
requiring single-ended, rather than differential, input
Signals, pins 3 and 4 can be shorted together and connected to a common bias point.
OP AMP OUTPUT (PIN 11): This terminal serves as the
output for the op amp section .It is internally protected
against accidental short circuit conditions, and can
sink or source 10 mA of current into a resistive load. In
most multiplier applications, pin 11 is the actual
XR-2228 output, with the op amp inputs being connected to the multiplier outputs,
APPLICATIONS INFORMATION
PART I: ARITHMETIC OPERATIONS
MULTIPLIER OUTPUTS (PINS 1 AND 16): The differential
output voltage, Yo, across these terminals is proportional to the linear product of voltages Vx and Vy applied to the inputs. Vo can be expressed as:
(~)
RxRy
(volts)-l
RxRy
a) 3-dB Bandwidth: Frequency where the multiplier
output is 3-dB below its low frequency (f = 20 Hz)
level.
Vo '"
~
MULTIPLICATION
For most multiplication applications, the multiplier and
op amp sections are interconnected as shown in Figure
14 to provide a Single-ended analog output with a wide
dynamic range. The circuit of Figure 14 provides a linear output swing of 10V for maximum input Signals of
10V, with a scale factor K = 0.1. The trimming procedure for the circuit is as follows:
(VxVy)
where all voltages are in volts and the resistors are in
kll. Rx and Ry are the gain control resistors for X and Y
sections of the multiplier.
1. Apply OV to both inputs and adjust the output offset
to OV using the output offset control.
The common-mode dc potential at the multiplier outputs is approximately 3 volts below the positive supply.
2. Apply 20V pop at 50 Hz to the X-input and OV to the
V-input. Trim the V-offset adjust for minimum peakto-peak output.
In most analog computation operations, such as multiplication, division, etc., pins 1 and 16 are dc coupled to
the op amp inputs (pins 13 and 14). The final output, Vz ,
is then obtained from the op amp output at pin 11, as
shown in Figures 14 and 15.
3. Apply 20V pop to the V-input and OV to the X-input.
Trim X-offset adjust for minimum peak-to-peak output.
1-232
XR·2228
4. Repeat step 1.
and is common to all analog division circuits. The divider circuit is trimmed as follows:
5. Apply + 10V to both inputs and adjust scale factor
for Vo = + 10V. This step may be repeated with different amplitudes and polarities of Input voltages to
optimize accuracy over the entire range of input
voltages, or over any specific portion of input voltage range.
1. Apply Vz = a and trim the output offset adjustment
for constant output voltage as Vx is varied from 1V to -10V.
2. Keeping Vz = 0, and applying Vx = -10V, time the
V-offset adjust until Va = O.
".
'"
3. Let Vz = Vx and/or Vz = - Vx and trim the X-offset
adjustment for constant output voltage as Vx is varied from -W to -10V.
",
4. If step 3 requires a large initial adjustment, repeat
steps 1, 2 and 3.
V'o--o-:+"'-'
5. Keeping Vz = Vx , adjust the scale factor trim for Vo
= -10V as Vx Is varied from -W to -10V.
PART II: ANALOG SIGNAL PROCESSING
PHASE DETECTION
The multiplier section of the XR-2228 can be used as a
linear phase-discriminator. A recommended circuit connection for this application is shown in Figure 16. In this
case, the reference input (input 1) is applied to pin 2,
and the input signal whose phase is to be detected (input 2) is applied to pin 5. For input signal amplitudes
0!:50 mV rms, the differential output voltage, Vo across
pins 1 and 16 is directly proportional to the phase difference, , between the two input signals. It can be expressed as
Figure 14. Multiplication Circuit
vz
300.
0----'1,..,.....-----.
241<
241<
>JU¢----o
:ZOpF
Vo' .10 Vz
Vo( Is the phase difference expressed in radians.
S'
-:" .'~sv
'00''''
-uv
·15V
~
100K
Y - OFFSET ADJ
...
OUTPUT
OFFSET ADJ,
V _OFFSET AOJ
lOOK
"
INP~ t-;....,;-:-::-.,
"::'
-15V
XR·;rz:r8
x
Cc
Figure 15. Dividing Circuit
DIVIDING CIRCUIT
INP~ 1-+-_-"
"
.r'
Cc
Recommended circuit connection for performing analog division is shown in Figure 15. This circuit uses the
multiplier in the feedback path of the op amp. For the
circuit shown, Vo = + 10 VzNx where Vx < a and Vz
can have either sign. Positive values of Vx are not allowed, since this will reverse the polarity of the feedback loop, causing positive feedback and latchup.
INPUT' -y,·lhl",j":oll
Cc .. COUPLING CAPACITOR
INPUT2 "V2-EZI.nf'"'C!I.O'
Cs .. IY'ASS CAPACITOR
OUTPUT • Vo '''' ..
s{~ - 1)
" .. PHASE DIFFERENCE IN RADIANS
Figure 16. Phase-Detector Circuit
This latchup mode is nondestructive to the XR-2228,
1-233
XR·2228
Figure 19. The triangle input signal is applied to the
X-input (pin 2). The multiplier section rounds off the
peaks of this input and converts it to a low distortion
sine wave.
The capacitors C1 at pins 1 and 16 provide a low-pass
filter with a time constant T { = A1 C1, where A1 = 5
kO is the international impedance level at these pins.
If needed, the phase conversion gain can be increased
by using the op amp section of the XA-2228 to further
amplify the output voltage, Vo("'). The XA-2228 is suitable for phase detection of input frequencies up to 100
MHz.
For the component values shown in Figure 19, the recommended input signal level at pin 2 is ==300 mV pp, in
order to obtain a 2V pp Signal at pins 1 or 16, with AX
set at approximately 1000. The dc level at pin 5 can be
used for adjusting the output amplitude, or providing
amplitude modulation. The sensitivity of the output amplitude to the dc voltage level at pin 5 is inversely proportional to the external resistor across pins 6 and 7.
SYNCHRONOUS AM DETECTION
Figure 17 is a typical circuit connection for synchronous AM detection for carrier frequencies up to 100
MHz. The AM input signal is applied to the multiplier Xand Y-input terminals (pins 3 and 4) simultaneously.
If higher amplitude output signal is required, the op
amp section of XA-2228 can be used to provide additional amplification.
The Y-gain terminals (pins 6 and 7) are shorted, and this
section of the multiplier serves as a "limiter" for input
signals 2: 50 mVrms; the X-section of the multiplier operates in its linear mode. The low-pass filter capacitors,
C1, and at pins 1 and 16 are used to filter the carrier
feedthrough. If desired, the op amp section can be
used as an audio preamplifier to increase the demodulated output amplitude.
Cc
AM
IN~~-+-<)-''H
X
PHASE-LOCKED AM DETECTION
The XA-2228 can be used in conjunction with anyone
of the commercially available monolithic phase-locked
loop (PLL) IC's to provide phase-locked AM detection.
In this manner, frequency-selective detection capabilities of PLL circuits can be extended to AM signals.
DEMODULATED
Figure 17. Synchronous AM Detector
' ..
~
1140Ub
10, Co' 200 of and RL' 16K
SWEEP RANGE' 120 kHllO 1 4 MH,
PRECISION PHASE-LOCKED LOOP DESIGN
Figure 18. !'recision PLL
A preCision phase-locked loop may be constructed using an XA-2209 voltage controlled oscillator and an
XA-2228. (See Figure 18.) Due to the excellent temperature stability and wide sweep range of the XA-2209 this
PLL circuit exhibits especially good stability of center
frequency and wide lock range. In this application the
XA-2228 serves as a phase comparator and level shifter. Resistor AL adjusts the loop gain of the PLL, thus
varying the lock range. Tracking range may be varied
from about 1.5: 1 up to 12: 1. For large values of AL, temperature stability of center frequency is better than 30
ppm/cC.
SlIllUSOIOAl
OUTPUT
TfllANGLE
INPUT
V'
x.
j
2."
,
OUTPUT
LEVEL
TRIANGLE-TO-SINEWAVE CONVERSION
v·
A triangular input can be converted into a low distortion
(THD < 1 %) sinusoidal output with the XA-2228. A recommended connection for this application is shown in
lOPTlONAL
AM
CONrROLI
."
!iOO! ~
IhfOR
MIN HID
Figure 19. Triangle-to-Sinewave Converter
1-234
\lour
XR·2228
Figure 20 shows the circuit connection diagram for a
two-chip AM and FM detection system, using the
XR-215 high-frequency PLL in conjunction with the
XR-222B multiplier/detector. Because of the highfrequency capability of the XR-215, the circuit is useful
as a phase-locked AM detector for carrier frequencies
up to 20 M Hz, and operates over a supply voltage range
of 10V to 20V.
The VCO section of XR-215 does not have a separate
"quadrature" output. However, this problem can be
overcome by driving the XR-222B multiplier directly
from the timing capacitor terminals (pins 13 and 14) of
XR-215. The Y-input of the XR-222B is operated with
maximum gain, since the Y·gain control terminals (pins
6 and 7) are shorted together. This causes the triangu,
lar waveform across the timing capacitor, CO, to be converted to an effective "quadrature" drive.
Figure 20. Phase-Locked AM Detection Using XR-215
Monolithic PLL and XR-2228 Multiplier/Detector
The Y-inputs (pins 4 and 5) are driven differentially from
the VCO timing capacitor Signal (available at pins 13
and 14 of the PLL IC) which is AC coupled to pins 4 and
5 of the XR-2228 multiplier input. the differential DC
voltage level at the multiplier output terminals (pins 1
and 16) is offset by means of an external resistor, RA.
This initial offset causes the op amp output of the XR·
2228 to settle to a known state when there is no carrier
or tone signal to be detected. With the op amp input
connections as shown in Figure 21, the op amp output
(pin 11) would be at a "low" state when the PLL is not
locked on a tone, and goes to a "high" state (i.e., near
+ VCC) when the PLL circuit is "locked" on to an input
tone. The output logic polarity can be reversed simply
by reversing the op amp inputs.
The modulated input signal is simultaneously applied to
both circuits through coupling capacitors. The phasedetector inputs of the XR-215, as well as the multiplier
X-inputs of the XR-2228, are biased at approximated
one-half of VCC, by means of an external resistive divider.
In Figure 20, Co sets the VCO frequency of the XR-215.
In the case of FM demodulation, R1 and C1 serve as
the post-detection filter for the detected FM signal and
RF1 sets the gain of the FM post-detection amplifier.
The Y·input of the XR-2228 is operated in its switching
mode, with the Y-gain terminals (pins 6 and 7) shorted
together. The AM and/or FM signal is simultaneously
applied to both circuits through coupling capacitors;
the output of the multiplier, at pin 16, is AC coupled to
the op amp section of the XR-2228, which serves as the
post·detection amplifier for the demodulated AM signal.
In the circuit, RX sets the amplifier demodulation gain,
C3 serves as the low· pass post·detection filter.
The filter capacitor, CA, connected across pins 1 and
16 of the multiplier outputs, serves as the postdetection low-pass filter. The value of CA is chosen to
provide a compromise between the response time and
the spurious noise rejection characteristics of the circuit: increasing CA improves the noise rejection characteristics of the Circuit, but slows down the response
time.
A detailed description of the principle of operation of
the circuit of Figure 21 is given in Exar's Application
Note AN-12 entitled: "Designing High Frequency
Phase-Locked Loop Carrier-Detector Circuits".
A detailed description of the circuit operation, and the
design equations for calculating the external component values are given in Exar's Application Note AN-13,
entitled "Frequency Selective AM Detection using
Monolithic Phase· Locked Loops."
,.,::);:
PHASE-LOCKED LOOP TONE DETECTION
1--'-1
"
:::::, ___
t--<>'!-....J
0:
The XR-2228 multiplier/detector can be used in conjunction with the XR-210 or the XR-215 high-frequency
PLL circuits, to provide high-frequency tone or carrier·
detect systems. The generalized circuit connection for
such an application is given in Figure 21. The circuit, as
shown, can operate with a single power supply, from
10V, to 20V, or with split supplies in the range of ± 5V to
± 10V. In the case of split power supplies, the resistor
string biasing the input terminals of the XR-2228 is not
necessary and can be eliminated by connecting node A
of Figure 21 to ground.
,.
~--t---ll-i:~'~
H1GH::i~"~'
'H""·~OC~ID ~OOI'
II
I
I
I
"I
1
_______ ...1
+'"
Figure 21. Recommended Circuit Connection of the XR-2228
with the XR-210 or the XR-215 High-Frequency
Phase-Locked Loops for Tone or Carrier-Detector
Application
The input signal is AC coupled, with separate coupling
capacitors, both to the input of the particular PLL circuit to be used and to the X-input terminal (pin 2) of the
XR-2228.
1-235
Display Drivers
XR·2271
Fluorescent Display Driver
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2271 is a monolithic 7-digit or 7-segment display driver designed to interface MOS logic with fluorescent displays. It features active high logic and low input
current. Each XR-2271 is capable of driving seven digits
or segments of a display panel and provides complete
input and output isolation. Since the output pull up resistors are incorporated on chip, no external parts are
required to interface fluorescent displays.
INl1 UTS
FEATURES
Active High Logic
Low Input Current
Complete Input Output Isolation
Output Pull Up Resistors On Chip
No External Parts Required To Drive
Fluorescent Displays
APPLICATIONS
Fluorescent Display Driver
MOS Logic/High-Voltage Interface
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-2271CN
XR-2271CP
Ceramic
Plastic
O°C to +70°C
O°C to + 70°C
ABSOLUTE MAXIMUM RATINGS (Note 1)
VSS - V Input to VOutputs to V ISS
Power Dissipation TA :s; 25°C
Derate above 25°C
Storage Temperature
SYSTEM DESCRIPTION
50V Max.
50V Max.
50V Max.
20 mA Max.
625 mW Max.
5 mW/oC
-65°C to + 150°C
The XR-2271 fluorescent display driver requires no additional components to interface seven segment flu()rescent displays to MOS Logic. The output is an emitter
follower and can switch up to 50V at 20 mA. All inputs
are protected to 50V and pull up resistors are integrated onto the device.
1-236
ELECTRICAL CHARACTERISTICS (TA = +25°C, VSS = OV, VPARAMETERS
MIN
TYP
MAX
XR·2271
- 40V, Note 2)
UNITS
CONDITIONS
SYMBOL
10
= -2.0V
= -7.5 mA
Yin off
Vo
= V- +2V
mA
lin on
Yin
Vo
50
p.A
p.A
lin off
Vo
Yin
Yin
= -1.2V
= -2.0V
= V-+2V
= -SV
= -15V
-0.9
0
V
Vo on
Vo on
Logical "0"
Output Voltage
-40
-38
V
Vo off
Yin
Output Pull
Down Resistance
45
KO
RO
Yin = -SV
Note 3
Output Pull
Down Current
350
p.A
IS
Vo = -5V
Yin = -SV
Note 3
Power Supply
Current
-1.2
-7
mA
mA
I-off
I-on
All inputs - SV
All inputs - 1.2V
CONDITIONS
Logical "1"
Input Voltage
-1.2
0
V
Yin on
-s
V
0.25
0.8
-50
0
-90
-2.0
Logical "0"
Input Voltage
Logical "1"
Input Current
Logical "0"
Input Current
Logical "1"
Output Voltage
-1.4
-12.0
Vo
=
-SV
AC Parameters (TA = + 25°C, Test Circuit Figure 2)
PARAMETERS
MIN
TYP
MAX
UNITS
SYMBOL
1
5
p.S
td
CL
RL
Output on
Rise Time
0.5
2
p.S
tr
CL
RL
= 10 KO
= 25 pf
= 10K
Output off
Storage Time
0.8
5
p.S
ts
CL
RL
= 25 pF
= 10 KO
Output off
Fall Time
O.S
2
2.0
25
p.S
p.S
tf
CL
RL
RL
= 25 pF
= 10K
= 00
Output on
Delay Time
= 25 pF
Note 1. The "Absolute Maximum Ratings" are those values beyond which the device may be damaged.
Note 2. All voltages measured with respect to VSS unless otherwise noted. Positive current flow is into a device pin.
Note 3. The output pull down resistance is an N channel junction FET. For Vo '" V- it is resistive, and for IVo (V - ) I > 20V, it is current sink.
"'U'J:-\
>v
6V
Oy_
ou"U'
I
I
It-"-j
~_
-+-
~I
'0 I
I
I
EQUIVALENT SCHEMATIC DIAGRAM
I
I'RI
I
'"
I
I-,:....J~
S
I
I
___ ~T~,
I
1",,---
--;0;:--- ,'"'
Figure 2. XR·2271 AC Parameter Test Circuit
1-237
XR·2272
High-Voltage 7-Digit Display Driver
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2272 is a monolithic high voltage display driver
array specifically designed to drive gas-filled digit displays. The circuit is made up of seven independent digit
driver sections in the same monolithic package. Its
main application is to act as buffer interface between
MOS outputs and the anodes of a gas discharge panel.
The XR-2272 is particularly well suited to interfacing
with Panaplex " type displays.
FEATURES
Active Low Inputs
High Breakdown Voltage
Low Power Dissipation
Complete Input-Output Isolation
On-Chip Pull-Up Resistors
Versatility for Display Interface
APPLICATIONS
Gas Discharge Display Driver
Panaplex Display Driver
MOS Logic to High-Voltage Interface
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ( - VEE)
- 75V Max.
Output on Current Each Output
- 20 mA Max.
- 50 mA Max.
Output on Current All Combined
Positive Supply Current Iss
60 mA Max.
Input Current
± 3 mA Max.
Input Voltage
- VEE, Min., VSS, Max.
Package Power DiSSipation, 25°C
625 mW (Plastic)
Derating above 25°C
5 mW/oC
O°C to + 70°C
Operating Temperature Range
Storage Temperature Range
- 65°C to 150°C
Part Number
Package
XR-2272CN
XR-2272CP
Ceramic
Plastic
Operating Temperature
O°C to
O°C to
+ 70°C
+ 70°C
SYSTEM DESCRIPTION
The XR-2272 high voltage display driver features seven
independent sections, each capable of switching - 75
V at up to 20 mAo Each has active low inputs and monolithic pull-up resistors. The output is an emitter follower.
1-238
XR·2272
- ----,
I
r----I
I
I
I
I
I
I
I
I
I
I
I
I
I
I N PUT
(9-15)
.----+-+1-0
0-.....--------'
OUTPUT
(2-8)
I
I
I
I TYPICAL
LJ2~_?--P~VERS
_
EQUIVALENT SCHEMATIC DIAGRAM
1-239
I
J
XR·2272
ELECTRICAL CHARACTERISTICS (TA
= + 25°C, VSS = OV, V-
-60V, Note 1)
TYP
MAX
UNITS
SYMBOL
Input Off Voltage
-1.8
-1.2
V
Vin off
10 = -5 ~
Input Off Current
-20
/-IA
linoff
Yin = -1.2V
10 = -5/-1A
-6
V
Yin on
Va = -1.4V
10 = -15 mA
/-IA
lin on
Va = -1.4V
10 = -15mA
PARAMETERS
MIN
Input On Voltage
Input On Current
-600
-250
-100
-60
-48
V
Va off
Yin
-1.4
-0.9
0
V
Va on
Yin = -6V
10 = -15 mA
Output Off Voltage
Output On Voltage
CONDITIONS
=
-1.2V
Output Pull
Down Resistance
45
KO
RO
Yin = -6V
Note 2
Output Pull
Down Current
350
p.A
IS
Vo = -5V
Yin = -6V
Note 2
p.A
1-
All inputs at -1.2V
One input at -6V
Supply Current
Off State
1
150
One Segment On
0.35
2
mA
l-
All Segments On
2.2
6
mA
I
All inputs at - 6V
1
5
/-IS
td
CL = 25 pF
RL = 10 KO
Output on Rise Time
0.5
2
/-IS
tr
CL = 25 pF
RL = 10 K
Output off Storage Time
0.8
5
/-IS
ts
CL
RL
Output off FilII Time
0.6
2
2.0
25
/-IS
/-IS
tf
CL
RL
RL =
AC Parameters (TA = +25°C, Test Circuit Figure 2)
Output on Delay Time
..
= 25 pF
= 10 KO
= 25 pF
= 10K
00
Nota 1. All voltages measured With respect to VSS unless otherwise noted. Positive current flow IS Into a device
pin.
Note 2. The output pull down resistance is an N-Channel junction FET. For Vo .. V - it is resistive, and for IVo (V -) I > 20V, it is a current sink.
INPUT
.----oVss
_3\1.
I
'NPUT
7/
-3V
"'I-'-R""!--6VWttI
I~
O--+--f
OV
+- t - . - _.......-:
'F
OUTPUT
t:
-GOV
40V
-----1-",'
-
-1-- I
!--~
Figura 2. XR·2272 AC Para mater Test Circuit
Figura 3. AC Test Waveforms
1-240
:
-+- --- -.
!
r--._.-_.
--'
'all
XR·2276
Bar Graph Display Generator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2276 is a 12-point logarithmic bar graph display
generator designed for interfacing with fluorescent displays. The device's twelve comparators, internally biased at logarithmic intervals about an adjustable reference, controlling twelve fluorescent drivers. The XR2276 may also drive LEOs if the maximum device
power dissipation is not exceeded.
The XR-2276 is especially suited for generating 12point bar graphs or other multi-segment fluorescent
displays, such as those used for audio level-detector or
level-indicator applications.
INPUT
DdB
··20 dB
+8 dB
-10dS
+3dB
7 dB
., dB
5dB
DdB
·3dB
-1 dB
GROUND
+Vcc
AQJUSTMENT
OUTPUTS
OUTPUTS
FEATURES
High Input Impedance
Internal Pull-Down Resistors
Logarithmic Display Characteristics
External Reference Level Adjustment
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-2276CP
Plastic
O°C to +70°C
APPLICATIONS
Bar-Graph Display Generator
12-Point Display Driver
Audio Level Indicator
Channel Separation Indicator
12-Point Digital Controller
Sequential Display Generator
SYSTEM DESCRIPTION
The XR-2276 is a logarithimic level detection and fluorescent display driver. The circuit is comprised of an input buffer amplifier, 12 high gain comparators, an internal voltage reference and a bias-setting resistor string.
All of the twelve comparator stages have independent
buffered outputs.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Input Signal Range
Output Current
Power Dissipation
Derate Above + 25°C
Operating Temperature
Storage Temperature
Each of the comparators have a threshold level higher
than the preceeding comparator stage. With no input
signal, all of the comparators are "off" and all the outputs are at a low state. As the input level is increased,
the outputs successively switch to their high state. The
threshold levels are within the range of - 20 dB to + 8
dB with reference to a 0 dB level setting. The 12 ranges
are: -20dB, -15dB, -10dB, -7dB, -5dB, -3dB,
-1 dB, 0 dB, 1 dB, 3 dB, 5 dB, and 8 dB.
24V
-1V to +10V
5 mA
625mW
5 mW/oC
O°C to +70°C
-65°C to + 125°C
1-241
XR·2276
ELECTRICAL CHARACTERISTICS
Test Conditions: Vee
= 18 Volts, TA = 25°C, unless otherwise specified. (See Test Circuit of Figure 1)
LIMITS
TYP
MAX
UNITS
SYMBOL
Input Current
30
300
nA
liN
Output Low Voltage
0
0.5
V
VOL
RL
Measured at each output
V
VOH
RL = 15 KG
Measured at each output
V
VOS
PARAMETERS
MIN
Output High Voltage
14.0
15.5
Input Bias Voltage
0.9
1.25
1.6
Comparator Threshold
Voltages
- 20 dB Output
- 15 dB Output
- 10 dB Output
-7 dB Output
-5 dB Output
-3 dB Output
-1 dB Output
+ 1 dB Output
+3 dB Output
+5 dB Output
+8 dB Output
-
2.10
0.40
0.65
0.92
1.15
1.43
1.77
2.21
2.76
3.37
4.72
0.3
0.46
0.73
0.99
1.23
1.52
1.88
2.34
2.93
3.66
5.12
ODB
Adjust
Range
0.52
0.83
1.07
1.30
1.61
2.00
2.49
3.10
3.97
5.56
V
V
V
V
V
V
V
V
V
V
V
V
10K Trim Pot from pin 16
to GND
VIN = 3.35V
+1
Segments
-2
Comparator Threshold
Change with Supply
-0.6
+0.6
dB
= 7.5 Volts
= 220 KG
Input level above VOS
necessary to change
comparator state.
Measured at pin 11 after 0
dB adjustment
Measured at pin 2
Measured at pin 3
Measured at pin 4
Measured at pin 5
Measured at pin 6
Measured at pin 7
Measured at pin 10
Measured at pin 12
Measured at pin 13
Measured at pin 14
Measured at pin 15
Vc
o dB Output
CONDITIONS
VIN
= 6V
= 15 KG
VIN = 7.5V
RL = 220 KG, Vee = 18V
~Vee
tINC
RL
Supply Current
13
20
mA
ICC
_ICC
----------fT .
.------0 ..-Yeev
••
11(1:
v,.
vc
-liN
AL
____
0,
~_____
•Vo
(al
(bl
Figure 1. Basic Test Circuit: (a) Circuit Connection, (b) Output Waveform.
1-242
XR·2276
TYPICAL PERFORMANCE CHARACTERISTICS
TURN ON TIME VS SEGMENT
OUT1'I.IT VOLTAGE VS LOAD CURRENT
....
I
I'
I
TURN OFF TIME VS SEGMENT
Vee ~ 18V
ODa .. 3.J5V TOTAL
Al- 220K
"'-
"'-
.sw
;--..
Cl
~
22.5 pF
I
VIN·O~9V
V
::;
Z
"'i'-
I
z
a::
j:
;::
......o
,/
o
w
::;
V
;::
j'
'
"
Vee' 1BV
ODe ~ 1.l5v TOTAL
Rl ~ 220K
Cl ~ 22.5 DF
........
i'--
.......
z
V
a::
...
:::l
l - f-
VIN.o~9V
r--.
•
SEGMENT
IL (mol
SEGMENT
APPLICATION INFORMATION
plate segments that are to remain constantly on are
tied to the V + line. All other plate connections are
switched by either the XR-2276 or some other means
(i.e., a selective switch for a Dolby symbol, etc.). The
o db point is adjusted for each device by the 10K pot
from pin 16 to ground.
Vacuum Fluorescent Displays: Vacuum fluorescent displays operate like vacuum tubes. The display consists
of a filament, a grid and several plates. Each segment
on the bar graph and the other symbols, reference numbers, etc., are plates coated with fluorescent material.
As with a vacuum tube, when the plate is at a potential
lower than that of the grid, no plate current flows and
the segment associated with that plate is cut off. When
the plate is at the same potential as the grid, electrons
flow from the filament to the plate, striking the fluorescent material, thus, causing it to glow. Most of the new
low voltage vacuum fluorescent displays operate with a
plate voltage of about 16V-18V, a filament voltage of 3V
rms and a filament current of about 100 mao
Design Example: Design a gain scaling and peak detector
circuit to drive the circuit in Figure 2, to yield an audio
level indicator with 0 db referenced to 1 mw into 6000.
The circuit should have an input impedance of 100 kO,
respond to frequencies from 50 Hz to 15 kHz, have an
output dc offset of 1.25V to bias the input of the
XR-2276 and operate from a single 16V supply. This circuit is shown in Figure 3.
XR-2276 Detailed Description: The XR-2276 contains an input buffer amplifier, a bias network and 12 comparators. The input buffer amplifier, pin 1, must be biased at
approximately + 1.25V under quiescent conditions. The
signal is then applied in addition to this bias voltage.
The full scale calibration of the XR-2276 can be fine
tuned by varying the bias voltage slightly.
The buffer amplifier is a high input impedance unity
gain amplifier that applies the input voltage to one input
of each of the twelve comparators.
The bias network consists of a voltage reference and a
string of weighted resistors which provide the threshold
voltages for the twelve comparators. The reference
voltage is adjustable by connecting a 10K trimpot from
pin 16 to ground. This feature allows a precise setting
of the 0 db point.
Figure 2. 2 Channel Display
Calculate the component values for the gain scaling
stage.
The rms voltage that corresponds to 1 mw in 6000 is:
Since decibels are ratios with respect to a reference
value, the threshold voltages determined by the resistor
string may not correspond to the desired reference. In
this case it will be necessary to scale the input signal
with either gain or attenuation to obtain the desired correspondence (see the design examples below).
...rPR = "(1
mw)(6000)
= .774 Vrms
Therefore
Vpeak = (1.414)(.774)Vrms = 1.095V
The comparators have a high open loop gain, NPN output transistors with 220K resistors connected from the
emitters to the ground terminal, pin 8, and a 1.5K resistor in series with the output.
The dc input voltage to the XR-2276 that gives a 0 db indication is 2.10V.
The gain required is 2.10/1.095 = 1.92. For a noninverting amplifier gain = 1 + RF/RS. If we choose,
Applications Circuits: Figure 2 shows a typical connection
for a two channel display. Note that the grid and any
RF = 22K Then RS = 22K1.92 = 24K
1-243
XR·2276
R1 = R2 = 200K to bias the input at V + 12 and yield an
input impedance of 100K.
C1
= 1/2'/1"(50 Hz)(100K)
The gain for the input amplifier would have to be
Gain
= (2.10)/1.735 = 1.21
'" .033 p.F
Rs/Rf = .21 for non inverting amplifier
C2 = 1/2'/1"(50 Hz)(24K) '" .15 p.F
if
The input impedance to the peak detector is:
Rf = 24K
Rs = (24K)(.21) '" 5.1 K
47K H 100K '" 32K
Driving LED's with the XR-2276: LED's can be driven by
the XR-2276 provided care is taken not to exceed the
maximum power dissipation of the device. This can be
accomplished in two ways. First, the cathodes of the
display device can be multiplexed such that the total
current sourced by the XR-2276 at anyone time, does
not cause excessive power to be dissipated. An alternate method is to drive an external pass device, such
as an XR·2203, which in turn drives the LED's. In this
way the power dissipation is moved off of the XR-2276.
C3 = 1/2'/1"(50 Hz)(32K) == 0.1 p.F
The peak detector circuit provides full wave rectification of the incoming audio signal. A1 serves an inverting unity gain peak detector giving a positive output for
the negative half cycle of the incoming signal. A2
serves as a unity gain non-inverting peak detector giving a positive output for the positive half cycle of the incoming signal. 03 and 04 serve as rectifier diodes and
01 and 02 keep the feedback loops on A1 and A2, respectively, closed during the amplifiers non-rectifying
half cycle. R5 and R7 set the closed loop gain of A1 at
unity. RS and R7 together with C5 provide a filter for the
peak detector output. C5 can be adjusted to provide the
desired damping. R4, R6, C4, 05 and 06 prevent the input of A2 from being pulled below ground by the large
negative transients. R9 ' R10 and C6 establish the 1.25
volt (adjustable by R10) dc bias for the XR2276 input.
The operational amplifier chosen to be used in this circuit is the XR-3403. It has adequate ac performance
and is ideally suited to single supply operation, since its
common mode input voltage range includes ground.
Design Example: How many LED's can be driven simultaneously without exceeding the maximum power dissipation of 625 mw? VCC = + 1SV, TA = 25°C.
The 1.5K resistor in series with the output can be as
high as 3K and the no load output high voltage of the
XR·2276 should be '" Vee - 1V. If the forward voltage
on an LED is '" 1.7V, the current typically available to
drive the LED would be:
(1SV - 1V - 1.7V)/1.5K = 10.2 ma
(5.1 ma if the series resistor = 3K)
The total voltage across each output would be 16.3V.
The total. power dissipated per segment is:
Po
= (16.3V)(10.2 mal = 166 mw
The quiescent dissipation of the device
r--'~+-- ~'""
.....
PDq = (Isupply max)(Vsupply)
or
(20ma)(1SV) = 360 mw
The total number of segments that can be on at once is:
625 mw - 360 mw/166 mw1segment '" 1 Segment
Figure 3. Peak Detector
The circuit in Figure 4 shows an acceptable method for
using the XR-2276 in conjunction with LED's.
Design Example: Design a vu indicator. The circuit above
could be used to make a vu indicator with a slight adjustment in the circuit gain. Since 0 vu is 4 dB above
1 mw into 6000:
Design Example: How can 12 LED's be driven simultaneously at 20 ma without causing excessive power dissipation in the XR-2276:
4 dB = 20 10g(0 vu)/1.095
This can be done easily using two XR-2203's to drive
the LED's as shown in Figure 7. The current through the
LED's is limited by the series resistors.
(10)1/5(1.095)V = 0 vu
o vu
= 1.735Vpea k
1-244
XR·2276
...;-.
r
i
!!
UL"~;,/L;;'"
-I
1,,','
, .,
i
I '"~"
1~
1
~
"'m~llIJ
_.
-{>o-
-=:-
=117 XR·220J
-{>o-
=1/7 XR·2203
Figure 4. Multiplexed Display
Figure 5. Continuous Display
1~
-
-
-
-
-
-
-
-
-
-
-
-
COMP 11
OUTPU!
GROIJND
16
OdR
ADJ\JSTMfNl
1_ INTERNAl_,'_
I ' BIAS
INPIJT
HUfF! R
--i... _ COMPARATOR
-I
NO 1
I. _ ... -,.
I
--,
COMPARATOR .......0-+1...- NO 12
EQUIVALENT SCHEMATIC DIAGRAM
1·245
INTERNAL
HEGUlATOH
----j
XR·2277/2278
Dot and Bar Graph Display Generators
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2277 and XR-2278 are 12 point level detector
circuits designed for direct interfacing to light emitting
diode (LED) moving-dot or bar-graph displays. Each of
the circuits is comprised of an input buffer amplifier
and 12 comparators, biased from a resistor string at
logarithmic intervals. Accuracy is enhanced by an internal reference. Each comparator provides a high impedance current source output which are all very
closely matched and simultaneously adjustable with a
single external resistor. A control signal applied to the
mode select pin determines whether the display is driven in a moving-dot or bar-graph format.
FEATURES
High Impedance Buffered Input
Direct LED Interface
Constant Current Outputs
External Dot/Bar Mode Select
ORDERING INFORMATION
Part Number
Package
XR-2277P
XR-2278P
Plastic
Plastic
Operating Temperature
o·e to
o·e to
+ 70·e
+ 70·e
SYSTEM DESCRIPTION
APPLICATIONS
The XR-2277 and XR-2278 are 12 point logarithmic level detectors and LED drivers. LED driving current is
provided by on board adjustable current sinks; no series limiting resistors are required. All LEOs receive
matched currents, ensuring equal brightness. The drivers can be programmed to source up to 22 mA.
Bar-Graph Display Generator/Driver
Moving-dot Display Driver
Sequential Display Indicator
Audio Level Indicator
The LED current is set by a resistor from Pin 2 to
Ground. The zero dB reference is set by varying the bias on Pin 3. The output may be either moving dot (one
segment only) or bar mode (all segments up to the measured value illuminated). This is determined by Pin 18.
The XR-2277 provides 12 discrete outputs for an input
level range of - 30 dB to + 6 dB, referenced to an internally set zero dB level which is typically 0.2 VRMS. The
XR-2278 has similar electrical charcteristics, providing
a - 20 dB to + 8 dB input dynamic range referenced to
0.13 VRMS. Both parts operate from a nominal 12V
supply.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Derate Above 25·e
Operating Temperature Range
Storage Temperature Range
15V
625 mW
5 mW/·e
o·e to + 70·e
-65·e to + 150·e
1-246
ELECTRICAL CHARACTERISTICS vcc
XR·2277/2278
= 12 Volts, TA = 25°C, unless otherwise specified. (See Test Circuit of Figure 2.)
XR-2277
PARAMETERS
Supply Voltage
MAX
MIN
TYP
12
14
10
5
10
MIN
TYP
10
Supply Current
XR-2278
LED Current
UNITS
12
14
10
VDC
mA
VF(LED)
5
22
mA
R2 Varied
See Figure 4
22
LED Current
12
15
ILED Matching between Outputs
-1.5
Input Voltage for 0 dB Output
0.10
0.20
Input Current
Outputs
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
MAX
18
12
+1.5
-1.5
0.25
0.09
15
-31.5 -30.0
-27.0
-25.0 -24.0
-21.5 -20.0
-18.5 -17.0
-15.5 -14.0
-11.0 -10.0
-8.0 -7.0
-5.0 -4.0
0
+2.0
+3.0
+4.5
+6.0
-28.5
-23.0
-18.5
-15.5
-12.5
-9.0
-6.0
-3.0
+4.0
+7.5
VIN
18
mA
R2
+1.5
mA
R2
0.18
50
VRMS
nA
20.0
-16.5 -15.0 -13.5
-11.5 -10.0 -8.5
-8.0 -7.0
-6.0
-6.0 -5.0
-4.0
-4.0 -3.0
-2.0
-1.5 -1.0
-0.5
0
+0.5
+1.0
+1.5
+2.0
+3.0
+4.0
+4.0
+5.0
+6.0
+6.5
+8.0
+9.5
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
0.13
50
1 (pin 17)
2 (pin 16)
3 (pin 15)
4 (pin 14)
5 (pin 13)
6 (pin 12)
7 (pin 11)
8 (pin 10)
9 (pin 8)
10 (pin 7)
11 (pin 6)
12 (pin 5)
CONDITIONS
= 2V
= 0V
= 27 KIl
= 27 KIl
o dB Output Threshold
See Note 1
See Note 2
NOTES:
1. Calibration adjustment for XR-2277: An input voltage, VIN, is applied at -27 dB level, referenced to zero dB
setting, and R1 is adjusted until Output 2 (Pin 16) turns on.
2. Calibration adjustment for XR-2278: An input voltage, VIN, is applied at -20 dB level, referenced to zero dB
setting, and Rl is adjusted until Output 1 (Pin 17) turns on.
Vcc
--------------
RL
OUTPUT
0--
I
~~
~
~ ILED
17
15
16
14
13
2
4
3
S
6
10
11
7
9
8
I
liiN
RL
-------
R4
Rl
o--t i +
12
XR-2277/XR-2278
R3
Cl
RL
r
R2
RS
l C2
GND
Figure 2. Generalized Test Circuit
1-247
RL
R1
R2
R3
R4
Rs
C1
= soon
= 27KH
= 330KH
= 10KH
= 10Kn
=
2.2/LF
C2 = 10Jl.F
RL = 200H
XR·2277/2278
CURRENT ADJ.
17
16
12
15
~
A
~
. -______________________ OUTPUTS
_________________________
OUTPUT
11
20------.,
GROUND
9
EQUIVALENT SCHEMATIC DIAGRAM
1-248
10
B
7
6
5
XR·2277/2278
PRINCIPLES OF OPERATION
As shown in the equivalent circuit schematic of Figure
1, each circuit is comprised of 12 voltage comparators
with current source outputs. One input in each of the
comparators is connected to a common voltage line.
The input voltage, VIN, is applied to this signal line
through a buffer amplifier. The remaining input of each
of the comparators is biased from an internal resistor
ladder connected to a voltage reference on the IC chip.
Thus, each of the 12 ladder taps corresponds to the
particular output thresholds, listed as outputs one
through twelve, in the electrical characteristics.
shows the available output drive current, ILED, as a
function of R2.
Response Adjustment
Transient response of the circuit is adjusted by an external resistor, R5, and capacitor, C2, connected from Pin
4 to ground. Typical component values for audio frequency applications, from 20 Hz to 20 kHz, are: R5 =
10 kO and C2 = 10 p.F. The internal impedance at Pin 4
is approximately 100 ohms. C2 functions as a holding
capacitor of the internal peak rectifier circuit, with R5
controlling its decay time.
As the input voltage applied to the device is increased,
each of the 12 comparators in the chip changes state
sequentially at the time the input signal levels reach
their respective threshold levels. The current source
outputs of these comparators can directly drive LED
displays. The circuit can operate both in moving-dot or
bar-graph display format.
Scale Adjustment
The output thresholds for the XR-2277 or the XR-2278
are measured relative to an internal zero dB reference
level. Thus, for a given input signal dynamic range,
each circuit must be calibrated with respect to the zero
dB reference level setting. This calibration is performed
by adjusting the potentiometer, Rl, shown in Figure 2.
The scale adjustment is performed with an audio frequency ac signal applied to the circuit.
Figure 3 shows the typical output current waveforms
for operating in either the moving·dot or the bar-graph
modes. The mode of operation is selected by the logic
state at Pin 18. If this pin is grounded, the output display is in the moving-dot format where only one of the
current outputs is active at anyone time, depending on
the input signal level.
XR-2277
Step 1: Determine exact value of input voltage to produce zero dB output. This is done by increasing the ac
input Signal amplitude until Output 10 (Pin 7) begins
conduction.
If Pin 18 is left an open Circuit, then the IC operates as
a bar-graph display generator. In this mode of operation, the external LEOs are connected in series, in
groups of four to minimize power dissipation.
Step 2: Reduce input voltage level to - 27 dB referenced to the input level of Step 1. Adjust Rl until Output
1 (Pin 16) begins conduction.
The outputs of the comparators (4), (8), and (12), continue conducting in this manner as long as the voltage
level is above in respective threshold pOints.
XR-2278
EXTERNAL ADJUSTMENTS
Step 1: Determine exact value of input voltage to produce zero dB output. Do this by increasing ac input signal level until Output 8 (Pin 10) begins conduction.
Output Brightness Adjustment
The output current level for each of the 12 outputs is
controlled by an external current setting resistor, R2,
(R2 ~ 20 kO) connected from Pin 2 to Ground, Figure 4
v~z
Step 2: Reduce input voltage level by - 20dB referenced to its zero dB level. Adjust Rl until Output 1 (Pin
17) beings conduction.
20
- - - - - - - - ___ _
r'\.
" "-
1.
i
!
"
LNPUTSIGNAL LEVEL, VIN
(.)LINEARLYI!ISINOINPUYSICNAL
L12
ON
"
ON
.,
ON
........
........
I---...
-
"'"-
20
(b) O\ITPUTCUIIRDfTtll--------,--------,.-------r-----,
RL
______________
V'2
RL
r--+--_O'_'''--,''<>-I''''
RI :.
RZ '"
R3 '"
A4'"
RS'"
C 1 '"
In
500U
27K!l
330KIl
w
"
@i~
~g
10KIl
lOKI!
2.2/-1F
CO
Q. ...
:1 0
0"
Cz '" lOJ-IF
RL'" 200n
u::Ja:
"
I-
V2
V,
Figure 2. Generalized Test Circuit
INPUT SIGNAL LEVEL, VIN
(0) LINEARLY RISING INPUT SIGNAL
PRINCIPLES OF OPERATION
112
ON
OFF
As shown in the equivalent circuit schematic, the circuit is comprised of 12 voltage comparators with current source outputs. One input in each of the comparators is connected to a common voltage line. The input
voltage, YIN, is applied to this signal line through a
buffer amplifier. The remaining input of each of the
comparators is biased from an internal resistor ladder
connected to a voltage reference on the IC Chip. Thus,
each of the 12 ladder taps corresponds to the particu·
lar output thresholds, listed as outputs one through
twelve, in the electrical characteristics.
12
1----------.....1
ON
OFF
1,
ON
OFF
I-~~--------------
(b) OUTPUT CURRENTS IN MOVING·DOT MODE
Figure 3. Typical Output Waveforms in Moving-Dot Display
Mode
As the input voltage applied to the device is increased,
each of the 12 comparators in the chip changes state
sequentially at the time the input signal levels reach
their respective threshold levels. The output currents of
the last four outputs (Pins 5 through 8) are set at onehalf the current output of the first eight outputs. This is
done to minimize power dissipation since the last four
outputs normally drive red LEDs to indicate "over·
range" condition. The red LEDs are normally more efficient than other colors and require approximately onehalf as much current for the same brightness.
EXTERNAL ADJUSTMENTS
Output Brightness Adjustment
The output current level for each of the 12 outputs is
controlled by an external current setting resistor, R2,
(R2 ~ 20 kO) connected from Pin 2 to Ground. Figure 4
shows the available output drive current, ILEO, as a
function of R2 .
.
Figure 3 shows the typical output current waveforms
for operating in the moving-dot mode. The mode of operation is selected by the logic state at Pin 18. If this pin
is grounded, the output display is in the moving-dot format where only one of the current outputs is active at
anyone time, depending on the input signal level (see
Figure 3(b)).
,.
i
;
If Pin 18 is left an open circuit, then the IC operates as
a bar-graph display generator. In this mode of operation, the external LEOs are connected in series, in
groups of four to minimize power dissipation.
~
"- f'....
r
.......
12
"
O~tr"U::U9h 8
/ O~'r'=uah 12 ............ r-....
~
--- --- r---
I--
..
The outputs of the comparators, (4), (8), and (12), can·
tinue conducting in this manner as long as the voltage
level is above the respective threshold points.
25
30
35
.
50
Figure 4. Output Drive Current as a Function of Current
Setting ReSistor, R2
1-253
XR·2279
Response Adjustment
Yee
Transient response of the circuit is adjusted by an external resistor, R5, and capacitor, C2, connected from Pin
4 to ground. Typical component values for audio frequency applications, from 20 Hz to 20 kHz, are: R5 =
10 kll and C2 = 10 /-IF. The internal impedance at Pin 4
is approximately 100 ohms. C2 functions as a holding
capacitor of the internal peak rectifier circuit, with R5
controlling its decay time.
·3
330.
c,.,'
>-"W'o~~
Scale Adjustment
~~I-"-fF---''''-'--'
The output thresholds for the XR-2279 are measured
relative to an internal zero dB reference level. Thus, for
a given input signal dynamic range, each circuit must
be calibrated with respect to the zero dB reference level setting. This calibration is performed by adjusting the
potentiometer, R1, shown in Figure 2, with an audio frequency ac signal applied to the circuit in two steps, as
follows:
Figure 6. Circuit Connection for Bar-Graph Display
Generation
will turn on and stay on as the input signal amplitude is
increased as long as the input voltage stays above the
threshold level corresponding to that particular output.
Step 1: Determine exact value of input voltage to produce zero dB output. This is done by increasing the ac
input signal amplitude until Output 10 (Pin 7) begins
conduction.
AUDIO LEVEL INDICATOR
Figure 7 shows a complete audio level indicator system
made up of the XR-2279 Display Generator and an adjustable gain amplifier. For a given dynamic range of
the input audio voltage, VA, the potentiometer R6 is
used to set the gain of the input amplifier which is adjusted to give the desired zero dB output level from the
display generator IC. The potentiometer R1 is then adjusted to set the lowest output level; i.e., the - 27 dB
level. The display output format can be either the
moving-dot or the bar-graph type, by choosing the LED
interconnections and the logic signal applied to Pin 18.
Step 2: Reduce input voltage level to - 27 dB referenced to the input level of Step 1. Adjust R1 until Output
1 (Pin 7) begins conduction.
Yee
BAR-GRAPH DISPLAY
·3
Figure 6 shows the basic circuit connection for the XR2279 as a bar-graph display generator and driver. Note
that in this mode of operation the 12 LEOs are connected in series in three groups of four LEOs, and the modeselect terminal (Pin 18) is left an open circuit. Each LED
330.
10.
aND
'~o------.--....,..---.-
-R1- !Soon. CALIBRATION POTENTIOMETER.
Figure 5. Circuit Connection lor Moving-Dot Display
Generation
MOVING-DOT DISPLAY
Figure 5 shows the basic connection of the XR-2279 as
a moving-dot display generator and driver. In this mode
of operation pin 18 is connected to ground. Increasing
the voltage at the input will cause each one of the 12
LEOs to turn on, one at a time, at the appropriate input
level, and thus generate a moving dot of light. Output
waveforms for this mode are shown in Figure 3(b).
"1I,,,CALJBIIATIONPOl'!NlIDMeTlR.
Figure 7. Typical Audio Level Indicator System
Using the XR-2279.
1-254
XR·2284/2288
High-Voltage AC Plasma Display Drivers
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAMS
The XR·2284 and the XR·2288 are high voltage display
driver arrays especially designed for interfacing with ac
plasma display systems. The XR·2284 contains four in·
dependent driver channels, whereas its dual version,
the XR·2288, contains eight driver channels. Each driv·
er array can be used for either the segment or the col·
umn (or digit) drive, and several arrays can be
"stacked" together to drive a large number of display
segments.
NC
NC
r
/Oo::-~l
INPUTS
L~'------i
OUTPUTS
J
TOGGLE
.'NPUT
SUBSTRATE
l
OUTPUTS
J
All four channels of the XR·2284 are driven by a com·
man ac toggle voltage; however, the XR·2288 has two
independent toggle inputs, one for each of the four
channels in the IC. The XR·2284 and the XR·2288 are
designed for 360 volt ac plasma systems and have min·
imum stand·off voltages of 90 volts. The XR·2284C and
the XR·2288C are designed for 240 volt plasma sys·
tems, and have minimum stand·off voltages of 60 volts.
NC
NC
The circuits can operate with ac toggle frequencies up
to 200 kHz, and each driver channel can sink or source
100 mA of capacitive load current. For proper opera·
tion, the substrate terminals of all drivers must be
grounded through an external disconnect diode, DX, as
shown in the schematic diagram.
FEATURES
High Stand·off Voltage
90 V minimum for XR·2284/XR·2288
60 V minimum for XR·2284CIXR·2288C
Very Low AC Standby Power
( .. 25 mW/channel at 100 kHz)
Zero DC Standby Power
100 mA Output Drive Capability
TTL and CMOS Compatible Inputs
Digital or Segment Drive Capability
Power Dissipation
XR·2284P/XR·2284CP
XR·2288P/XR·2288CP
Derate above + 25°C
Storage Temperature
APPLICATIONS
High Voltage AC Plasma Panels
High Voltage Pulsed Displays
Pulsed AC Switching
625 mW
900 mW
5 mW/oC
- 65°C to 150°C
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Part Number
Toggle Input Voltage
XR·2284P/XR·2288P
XR·2284CP/XR·2288CP
XR·2284P
XR·2284CP
XR·2288P
XR·2288CP
±90V peak
±60B peak
1·255
Package
Plastic
Plastic
Plastic
Plastic
Operating Temperature
O°C
O°C
O°C
O°C
to
to
to
to
70°C
70°C
70°C
70°C
XR·2284/2288
ELECTRICAL CHARACTERISTICS
Test CondHions: Test Circuit of Figure 1, with external diode DX
= IN4002 or equivalent, TA = 25°C, unless otherwise
specified. (See operating precautions.)
XR-2284/XR-2288
XR-2284C/XR-2288C
MIN
TYP
MAX MIN
TYP
MAX UNIT
PARAMETERS
Maximum Toggle Voltage
±90
Output Current Capability
Max Sourcing Current
100
150
100
Max Sinking Current
100
120
100
±60
SYMBOL
CONDITIONS
Peak-to-peak
AC voltage·
See Figure 3.
V pp
VT
120
mA
Isource
120
mA
Isink
12% Duty Cycle
12% Duty Cycle
See Figure 4.
Output Voltage
High Output)
(selected)
High Output
(non-selected)
Low output
(VT-4)
(VT-4)
4V
4V
(-VT+2)
Maximum Toggle
Frequency
200
High-Level Input
2
Low-Level Input
Input Current
Switching Characteristics
Rise Delay
Fall Delay
(selected)
Fall Delay
(non-selected)
1.4
VOHS
VOHN
(-VT+2)
Vpeak
VOL
100
200
kHz
fT
2
1.4
V
VIH
1.2
0.8
1.2
0.8
V
VIL
8
16
8
16
mA
liN
See Figure 3.
See Figure 4.
500
500
500
500
nsec
nsec
trd
tfds
500
500
nsec
tfdn
IMPORTANT OPERATING PRECAUTIONS
nel does not exceed 100 mAo This can be done by limiting the slewrate of toggle voltage to:
1. External diode DX with reverse breakdown voltage
~ VT must be included in all circuit applications. This
diode decouples or "floats" the IC from the circuit
ground during the negative excursions of the toggle
voltage, VT.
( dVT) max
dt
s
100 mA,
CL
where CL is the total load capacitance, including the
capacitance of the display elements, driven by the particular output.
2. the rise and fall times of toggle voltages, VT, must be
held to a value such that output current of each chan-
v,-
Vpeak
-
J:::·:.
+YT
--~-:':"o
T---~---Y-r
TOGGLE OV
INPut
10"-
5V
/
/
"'YT
>-="'+-_--0 YOUT
lOOK
(+Yr-"
g~~:ST ~
,0%
=
(-Vt+ 2J
/I
- I.....
J
~
-
1\
.....
Figure 2. Typical Timing Waveforms
Figure 1. Generalized Test CircuH
1-256
/
I.:
XR·228412288
FUNDAMENTALS OF AC PLASMA DISPLAYS
~n~ n~ ~
Ac plasma display offer significant advantages over
other alpha-numeric displays such as fluorescent or
LEO type panels. Some of these advantages are the
low cost of the display itself, its wide viewing angle, and
the ease of formatting in the selection of display seg·
ments and digits. Plasma systems typically require high
voltage (200V or higher) ac drivers operating at relatively high frequencies (100 kHz and up). Although the
plasma display panel is a capacitive load and does not
draw dc current, the display driver output is required to
provide a high output drive current (typically 50 to 100
mAl, during the rising and the falling edges of the toggle
voltage, so that the driver output can still follow the ac
toggle voltage at high frequencies.
(a) Toggle
+VT
vo~
VIN~
OV------------~---------
(b) Input YoltIgII. VIN
V*O=+Vy
OV
The ac plasma displays normally require a net voltage
in excess of 200 volts across the display to turn it on. In
practice, this is achieved by "pulsing" the display with
two out-of-phase toggle voltages (VT), such that a net
peak-to-peak voltage of 2VT appears across the selected display portion to make it turn on. Thus, in controlling the plasma display, one must control the amplitude
of two peak-to-peak toggle swings, one on the
"segment-side" and the other on the "digit-side" of the
display, where each toggle swing is equal to only onehalf of the total voltage swing needed to light up the display. For example, for 240 volt ac plasma display systems, the toggle voltage used (VT) would be 120 volts;
and for 360 volt display systems, 180 volt toggle voltage
will be needed.
I
= -Vy
DEc~'i~:~IED
'ACllVATEO'
CHANNEL
te) Channel output voltage,
Your
Figure 3. Timing Diagram of Circuil Waveforms
pearing across the entire plasma panel.
CIRCUIT DESCRIPTION
Both the XR-2284 and the XR-2288 are multichannel
driver circuits, packaged in 14 and 20-pin dual·in-line IC
packages respectively. The XR-2284 is a four-channel
display driver, whereas the XR-2288 is an eight-channel
circuit, made up of two four·channel driver chips in the
same dual-in-line package. Thus, the XR-2288 has two
toggle voltage and substrate inputs; one for each of the
two four-channel IC chips sharing the same package.
PRINCIPLES OF OPERATION
The XR-2284 and the XR-2288 ac plasma display driver
circuits control the drive voltage applied to the segment
or the digit section of an ac plasma panel.
The equivalent circuit diagram for a typical driver channel is shown in the schematic. All the channels have
their own independent inputs and outputs, but share a
common toggle or clock input and a common substrate
or ground connection. The circuit is designed as a series connection of two controlled-switches, or SCR's.
The transistors, 03 and 02, form one of the controlledswitches, and 01 and 04, form the second controlledswitch. The internal junction capacitance, Cj, causes
Figure 3 shows the timing waveforms associated with
the ac plasma driver circuit, for the case of a 360 volt
display system (Le., VT = ±90V = 180V pp). In normal
operation, all of the driver channels are driven by a
common ac toggle voltage (VT) shown in Figure 3(a).
When the control input to a driver channel, Yin, is at
"high" state, as shown in Figure 3(b), its output would
be clamped nearly to ground and would follow the negative excursions of the toggle voltage, VT. This produces only 1/2 of the required peak-to-peak voltage
across the particular display segment, which is not
enough to light it. However, if Yin is at a "low" state, the
driver output, Vout, would be enabled and follow closely
the peak-to-peak excursions of the toggle voltage. This
would then cause the nearly full peak-to· peak swing of
the ac drive to appear across the selected display segment.
COMMOHTO
ALL DRIVERS
COMMON TO
AU DRIVERS
~ SUBSTRATE
COIIIION TO
AUDRrvERS
COMMON TO
ALLOA~ERS
, SUBSTRATE
I
:Yr
I
It should be noted that due to the external blocking diode Ox of Figure 1, the monolithic IC substrate is completely decoupled from ground during the negative excursion of the toggle voltage and the internal diode, 02,
of the schematic diagram causes the output to follow
the toggle voltage within one diode drop. In this manner, the IC has to withstand only one-half of the total ac
signal swing, or the one-fourth of the total voltage ap-
D.
TOGGLE INPU1'
Yr
Figure 4. Generalized Connection Diagram XR-22B4 and
XR-22BB.
1·257
XR·2284/2288
the respective controlled-switches to be turned on durIng the positive and negative edges of the toggle input,
Vr.
I
I
An external diode, Ox with a brekdown voltage ;;:Vr. is
used to "float" the substrate or decouple it from ground
during the negative excursions of the toggle voltage.
This external decoupling diode Is common to all channels, and can serve more than one IC package, as
shown in Figure 4. In this manner, many driver IC's, either of the four-channel (XR-2284) or the eight-channel
(XR-2288) type, can be "stacked" to drive a large number of display segments or columns, with only one common blocking diode and a common toggle input, as
shown in the Figure 4.
I I I II I I
I. I I. I I. I I.
TOGGLE
VOLTAOE
~
~~~~~~~-r~
COMPLEMENTARY
TOGGLE VOLTAGE
NOTE: EXTERNAL DIODE, DX (1N4D02 OR EQUWALENT) SHOULD
IE SEPARATE FOR DeGIT AND SEGMENT SIDES
Under dc conditions, i.e., with no ac toggle drive, the
driver IC's do not dissipate any appreciable standby
power. However, when the ac toggle voltage, VT, is applied and a particular channel is enabled, then the corresponding output can follow the peak-to-peak toggle
voltage and sink or source up to 100 mA of capacitive
load current to the plasma panel.
Figure 5. Typical Circuit Connection for Driving 7-Segment
4-DlgH Display wHh Decimal Point
swing of the toggle voltage, VT, is chosen so that the firing voltage, Vf, necessary for the display to light up,
falls into the range of:
APPLICATIONS
3 VT
Driving Seven-Segment Displays
< Vf < 4 Vr.
In this manner, only the selected and enabled display
cells will have an energizing voltage ;;: Vf.
Figure 5 illustrates a four digit, seven-segment plasma
display panel with decimal point. The entire display can
be driven by one XR-2288 driver for the segment side
and one XR-2284 driver for the digit side. The segment
and the digit drivers each must have their external disconnect diode, OX, as shown in the figure. The segment and the digit sides of the display are driven by outof-phase toggle Signals, VT and VT, which cause a total
firing voltage of four VT to appear across the enabled
display segment. Segments not enabled will have a net
voltage of three VT across them. The peak-to-peak
Driving Alpha-Numeric Displays
Figure 6 shows the circuit connection for driving an
eight digit, 16-segment alpha-numeric display. The
number of digits can be increased by connecting additional XR-2284 or XR-2288 driver arrays into the digit
side. These additional arrays can be directly "stacked"
using the same external disconnect diode, OX, and the
same toggle voltage drive lines already present on the
digit side.
EQUIVALENT SCHEMATIC DIAGRAM
OUTPUT
NOTE: EXTERNAL DIODE.
COIIP'LEIIII!NTAAY
TOGGLI!
""TAO<
'--I----t---.~
..
Figure 6. ClrcuH Configuration for Driving 16-Segment
Alpha-Numeric DIsplay Panel
INPUT D--+lC~I--="""
DX' IS REQUIRED FOR
PROPER OPEAAT1ON.
.". - one channel only -
1-258
XR·6118/6128
Fluorescent Dnsplay Drivers
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-6118 and the XR-6128 are high-voltage display
driver arrays which are designed to interface between
low-level digital logic and vacuum fluorescent displays.
Each circuit consists of eight independent signal channels comprised of Darlington output stages and
common-emitter type inputs. All stages on the chip
share common power supply and ground connections.
Both device types are capable of driving digits and/or
segments of fluorescent displays, and all of the eight
outputs can be activated simultaneously.
OUTPUTS
INPUTS
FEATURES
Direct Replacement for Sprague UDN-6118A,
UDN-6128A, and UDN-6118P-2 (60V)
Digit or Segment Drive Capability
Low Input Current
Integral Output Pulldown Resistors
Low Power
High Output Breakdown Voltage
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-6118P
XR-6128P
XR-6118P-2
Plastic
Plastic
Plastic
O°C to +70°C
O°C to +70°C
O°C to +70°C
SYSTEM DESCRIPTION
The XR-6118 and XR-6128 fluorscent display drivers
can switch up to 85V and 40 mA. Inputs are protected
to 20V. The XR-6118 is compatible with TIL, Schottky
TIL, DTl and 5 Volt CMOS logic families. The XR-6128
is intended for use with PMOS or CMOS logic families
operating with supply voltages of 6V to 15V. The two device types differ only in their input threshold levels (See
Figure 1). With either device type, the output load is activated when the inputs are pulled toward positive supply. Output pulldown resistors are included on the die.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VBB
Output Voltage, VOUT
Input Voltage, Y,N
Output Current, lOUT
Power Dissipation, (TA :$ 25°C)
Derate Above 25°C
Operating Temperature
Storage Temperature
85V
85V
20V
40 mA
1W
8 mW/oC
O°C to +85°C
- 55°C to + 150°C
1-259
XR·6118/6128
ELECTRICAL CHARACTERISTICS
Test Conditions: (TA = 25·C, VSS = 80V) Full Temp. Range O·C to + 70·C, XR-6118A only.
SYMBOL
PARAMETERS
ICEX
Output Leakage
Current
VOUT
Output ON Voltage
ISS(OFF)
XR·6118A
TYP MAX
MIN
XR·6128A
TYP MAX
15
15
15
75
75
75
UNIT
p.A
lOUT = 25 mA
4.0
V
Input ON Current
500
550
900
p.A
Supply Current
Off Condition
225
225
Output Pulldown
Current
VIN = 0.4 V
lOUT = 25 mA
VIN = 2.4 V (XR-6118)
VIN = 4 V (XR-6128)
2.4
2.4
On Condition
CONDITIONS
V
Input On Voltage
ISS(ON)
lOUT
MIN
VIN = 5 V (XR-6118)
VIN =' 15 V (XR-6128)
225
p.A
ALL Inputs Open
8
8
8
mA
VIN = 2.4 V (XR-6118)
(ALL Inputs)
800
950
800
p.A
ALL Inputs Open
VOUT = 80 V
va.
SEGMENT SELECT
XA-6118128
n ·
d.
0
0
D,
D.
n
D:I
D.
DS
Do
0---
".,
VFIL
D.
Figure 2. Typical Multiplexed Fluorescent Display Drive Application
1-260
XR·6118/6128
+VBB
30 K
OUTPUT
INPUT
RIN"
RB"
One of Eight
Stages
8K
120 K
(*) For XR-6118
RIN = 10K, RS = 30 K
For XR-6128:
RIN = RS = 20 K
EQUIVALENT SCHEMATIC DIAGRAM
1·261
Operational Amplifiers
Fundamentals of Operational Amplifiers
The "ideal" operational amplifier can be defined as a
vOltage-controlled voltage amplifier circuit which offers
infinite voltage gains with an infinite input impedance,
zero output impedance, and infinite bandwidth. The advantage of such an idealized block of gain is that one
can perform a large number of mathematical "operations", or generate a number of circuit functions by applying passive feedback around the amplifier.
The key features of operational amplifier application
can be illustrated using the simple feedback circuit of
Figure 1, and assuming that the operational amplifier
has infinite gain and Infinite input impedance. Then, the
following two conditions have to be satisfied:
AS
+ o---vv-....--_---f
VIN
a) Since the voltage gain is infinite, the net voltage
across the input terminals of the operational amplifier must be zero, if the operational amplifier output
voltage is to be finite. In the circuit of Figure 1, this
causes the inverting input terminal of the operational amplifier to behave as a "virtual ground".
Figure 2. Basic Feedback Configuration Using an Operational
Amplifier With Finite Input Impedance and Gain
It should be noted that, for large values of RIN, as the
voltage gain increases (I.e. A ... co), this expression rapidly converges to that given in equation 2; and the circuit performance becomes solely determined by the external components.
b) Since the input impedance of the ideal operational
amplifier is infinite, no input current is drawn by the
operational amplifier, the total current going into the
circuit node connected to the inverting input of the
operational amplifier (node Q in Figure 1) must be
equal to the total current coming out, I.e.:
IS = -IF and VIN = _ Vo
RS
RF
In addition to having finite gain and input impedance,
an actual operational amplifier circuit also has finite input bias currents as well as input offset voltage and currents. A more complete model of a practical operational
amplifier is shown in Figure 3 where IB indicates the finite input bias currents: Via and lio represent the voltage and current offsets associated with the circuit and
RO is the output resistance. Due to non-zero values of
Via and lio in a practical operational amplifier circuit,
VOUT "" 0 for VIN = O.
(1)
Solving for the overall voltage gain, one obtains:
(2)
Because of this property, the noninverting input of
an operational amplifier is often referred to as its
"summing input".
1' .... .....
~
I
+o-~vv--~~--~
VIN
AS
-o--------.---~
I
>--.......~--<>+
As
J~OUT
+
1
~
In the case of actual operational amplifiers, both the
voltage gain and the input impedance are quite high,
but still finite. Figure 2 shows the same basic feedback
circuit assuming that the amplifier now has a finite input resistance, RIN, and a finite voltage gain A. For simplicity, the output impedance of the operational amplifier is assumed to be negligible. The overall voltage gain
of the circuit can now be expressed as:
lI
.....
...........
......
I v io-: ;..( "lIB
v IN
Figure 1. The "Ideal" Operational Amplifier as a Feedback
Amplifier
.... .....
-
VII
lAIN
A2
I
'-
'
1+
I
I
~..-
/
f-'
' ,~tJ
I
..- ..-
'I
'1ft-
..- ..-
/'
~-~
I
lio
..-
..... .....
AVI ..... "'1'-, RO ......
/,/'"
/
./
i'
'"
va Ul'
Figure 3. Equivalent Circuit of a Practical Operational
Amplifier Showing the Effects of Finite Input
Impedance, Current and Voltage Offsets
1-262
-
!l)efirnuiooli1s of Operational Amplifier Terms
Since the operational amplifier has become a universal
building block for circuit and system design, a number
of widely accepted design terms have evolved which
describe the comparative merits of various operational
amplifiers. Some of these terms are defined below:
Output Voltage Swing: The peak output voltage swing, referred to zero, that can be obtained without clipping.
Large-Signal Voltage Gain: The ratio of the output voltage
swing to the change in input voltage required to drive
the output from zero to this voltage.
Input Offset Voltage: The input voltage which must be ap·
plied across the input terminals to obtain zero output
voltage.
Full-Power Bandwidth: Maximum frequency over which
the full output voltage swing can be obtained.
Input Offset Current: The difference of the currents into
the two input terminals with the output at zero volts.
Unity-Gain Bandwidth: Frequency at which the open loop
voltage gain is equal to unity.
Input Bias Current: The average of the two input currents.
Slew Rate: The maximum time rate of change of the output voltage, for a voltage step applied to the input. It is
normally measured at the zero crossing point of the
output voltage swing with the amplifier frequency compensated for unity gain.
Input Common-Mode Range: Maximum range of input voltage that can be simultaneously applied to both inputs
without causing cutoff or saturation of amplifier gain
stages.
Overload Recovery Time: Time required for the output
stage to return to active region, when driven into hard
saturation.
Common-Mode Rejection Ratio: Ratio of the differential
open-loop gain to the common-mode open·loop gain.
Gain Margin: The amount by which the voltage gain is
below the unity (0 dB) level, at the frequency where the
excess phase shift across the amplifier is exactly 180 0 •
It is measured in decibels, and must be positive for unconditional stability.
Supply Voltage Rejection Ratio: Input offset voltage
change per volt of supply voltage change.
Input Resistance: The ratio of the change in input voltage
to the change in input current on either input with the
other grounded.
Phase Margin: 180 0 minus the excess phase shift at the
Frequency where the magnitude of the open loop voltage gain is equal to unity. It is measured in degrees and
must be positive for unconditional stability.
Supply Current: The current required from the power
supply to operate the amplifier with no load and the output at zero.
1-263
Basic Applications of
Operational Amplifiers
The general usefulness of the operational amplifier
stems from the fact that when used in a feedback loop,
its overall performance and transfer characteristics are
determined almost totally by the choice of feedback
components. To be universally useful in such an application, the "ideal" operational amplifier should exhibit
infinite gain, infinite input impedance and infinite bandwidth. Although these are all idealized characteristics,
the practical monolithic operational amplifiers closely
approximate these features, particularly for low frequency applications.
the amplifier input without circuit adjustment, the
source resistance for both inputs should be equal. In
this case, the maximum offset voltage would be the algebraic sum of amplifier offset voltage and the voltage
drop across the source resistance due to offset current. Amplifier offset voltage is the predominant error
term for low source resistances, and offset current
causes the main error for high source resistances.
The availability and the low-cost of the integrated oper·
atlonal .ampllfier makes it an extremely versatile build·
ing block for analog system or equipment design.
Therefore, it is mandatory that the circuit designer be
familiar with the fundamental applications of operational amplifiers. This section of Exar's Operational Amplifier Data Book is intended to familiarize the designer with
some of the simple but fundamental circuit configurations using IC operational amplifiers. The discussion Is
slanted toward the practical applications of operational
amplifiers, as controlled by the external feedback circuitry. The particular operational amplifier parameters
will be discussed as they effect the circuit performance
and accuracy.
Figure 1. Inverting Amplifier
The integrated operational amplifiers shown in the figures are for the most part internally compensated, so
frequency stabilization components are not shown:
however, other amplifiers using external compensation
may be utilized to achieve greater operating speed in
many circuits.
In high source resistance applications, offset voltage at
the amplifier output may be adjusted by adjusting the
value of R3 and using the variation in voltage drop
across it as an input offset voltage trim.
The Inverting Amplifier
Offset voltage at the amplifier output is not as important
in AC coupled applications. Here the only consideration
is that any offset voltage at the output reduces the
peak-to-peak linear output swing of the amplifier.
The basic operational amplifier circuit is shown in Figure t. This circuit gives closed-loop gain of R2/Rt when
this ratio is small compared with the amplifier openloop gain and, as the name implies, is an inverting circuit. The input impedance is equal to Rt. The closedloop bandwidth is equal to the unity-gain frequency divided by one plus the closed-loop gain.
The gain-frequency characteristic of the amplifier and
its feedback network must be such that oscillation does
not occur. To meet this condition, the phase shift
through amplifier and feedback network must never exceed t80° for any frequency where the combined gain
of the amplifier and its feedback network is greater than
unity. In practical applications, the phase shift should
not approach t80° since this is the situation of conditional stability. Obviously, the most critical case occurs
when the attenuation of the feedback network is zero.
The only cautions to be observed are that R3 should be
chosen to be equal to the parallel combination of Rt
and R2 to minimize the offset voltage error due to bias
current; and that there will be a DC offset voltage error
due to bias current; and that there will be a DC offset
voltage at the amplifier output equal to closed-loop gain
times the offset voltage at the amplifier input.
Amplifiers which are not internally compensated may
be used to achieve increased performance in circuits
where feedback network attenuation is high, i.e., the
amount of feedback around the amplifier is low. The
compensation trade-off for a particular connection is
stability versus bandwidth. Larger values of compensation capacitor yield greater stability and lower bandwidth and vice versa.
Offset voltage at the input of an operational amplifier is
comprised of two components, these components are
identified in specifying the amplifier as input offset voltage and input bias current. The input offset voltage is
fixed for a particular amplifier; however, the contribution due to input bias current is dependent on the circuit configuration used. For minimum offset voltage at
1-264
The NDn-lnverting Amplifier
The cautions to be observed in applying this circuit are
as follows: the amplifier must be compensated for
unity-gain operation, and the output swing of the amplifier may be limited by the amplifier common-mode
range. The input signal swing should not exceed the input common-mode range, since this may cause a latchup condition.
Figure 2 shows a high input impedance non-inverting
circuit. This circuit gives a closed-loop gain equal to the
ratio of (R1 + R2) to R1. Its closed-loop 3-dB bandwidth
is equal to the amplifier unity-gain frequency divided by
the closed-loop gain.
V,No---------i
>-...~JVOUT
VOUT
VOUT ~V'N
Figure 3. Unity-Gain Buffer
Summing Amplifier
The summing amplifier, a special case of the inverting
amplifier, is shown in Figure 4. The circuit gives an inverted output which is equal to the weighted algebraic
sum of all three inputs. The gain of any input of this circuit is equal to the inverse ratio of the appropriate input
resistor to the feedback resistor, R4. Amplifier bandwidth may be calculated as in the inverting amplifier
shown in Figure 1 by assuming the input resistor to be
the parallel combination of R1, R2, and R3. Application
cautions are the same as those for the inverting amplifier. If an uncompensated amplifier is used, compensation is calculated on the basis of this bandwidth as is
discussed in the section describing the simple inverting
amplifier.
::Figure 2. Non-Inverting Amplifier
The primary differences between this connection and
the inverting circuit are that the output is not inverted
and that the input impedance is very high and is equal
to the differential input impedance multiplied by loop
gain (open-loop gain/closed-loop gain). In DC coupled
applications, input impedance is not as important as input current and its voltage drop across the source resistance. To minimize the output error due to the input
bias current of the operational amplifier, (R1 + R2)
should be chosen equal to the source impedance of the
input signal. Applications cautions are the same for this
amplifier as for the inverting amplifier with one exception: the amplifier output will go into saturation if the input is allowed to float. This may be important if the amplifier must be switched from source to source. The
compensation trade off discussed for the inverting amplifier is also valid for this connection.
V,o--~~v--o---~~'V----,
VOUT
The Unity-Gain Buffer
The unity-gain buffer is shown in Figure 3. The circuit
gives the highest input impedance of any operational
amplifier circuit. Input impedance is equal to the differential input impedance multiplied by the open-loop
gain, in parallel with common mode input impedance.
The gain error of this circuit is equal to the reciprocal of
the amplifier open-loop gain or to the common-mode rejection, whichever is less. Input impedance is a misleading concept in a DC coupled unity-gain buffer. Bias
current for the amplifier will be supplied by the source
resistance and will cause an error at the amplifier input
due to its voltage drop across the source resistance.
Figure 4_ Summing Amplifier
The advantage of this circuit is that there is no interaction between inputs, therefore, operations such as summing and weighted-averaging are implemented very
easily.
1-265
The Difference Amplifier
tion of two additional components, R1 and C2. R2 and
C2 form a 6 dB per octave high frequency roll-off in the
feedback network, and R1C1 form a 6 dB per octave
roll-off network In the input network for a total high frequency roll-off of 12 dB per octave, to reduce the effect
of high frequency input and amplifier noise. ln addition
R1C1 and R2C2 form lead networks in the feedback
loop which, if placed below the amplifier unity-gain frequency, provide 90 0 phase lead to compensate the 90 0
phase lag of R2C1 and prevent loop instability.
The difference amplifier is the complement of the summing amplifier and allows the subtraction of two voltages or, as a special case, the cancellation of a single
common to the two inputs. This circuit is shown in Figure 5 and is useful as a computational amplifier, In making a differential to single-ended conversion, or in rejecting an unwanted common-mode signal.
VINo---t
C1
VOUT
-
VOUT
R2
0
Ai (V2 -
V1)
Figure 5. Difference Amplifier
Figure 6. Basic Dlfferentlator Connection
Circuit bandwidth may be calculated in the same manner as for the inverting amplifier, but input impedance is
somewhat more complicated. Input impedance for the
two inputs is not necessarily equal: inverting input impedance is the same as for the inverting amplifier of
Figure 1 and the non inverting input impedance is the
sum of R3 and R4. Gain for either input is the ratio of R1
to R2 for the special case of a differential input singleended output where R1 = R3 and R2 = R4. The .general expression for gain is given in the figure. Compensation should be chosen on the basis of amplifier bandwidth.
Care must be exercised in applying this circuit since in·
put impedances are not equal for minimum bias current
error.
IC=_12nR1C1
Dlfferentiator Circuit
Figure 7. Practical Differentiator Circuit
The basic principle of a differentiator circuit is shown in
the simplified connection diagram of Figure 6. However, although mathematically accurate, this particular
connection is not directly useful in practice because it
is extremely susceptible to high frequency noise since
AC gain increases at the rate of 6 dB per octave. In addition, the feedback network of the differentiator made
up of the resistor R3 and the capacitor C3 is an RC low
pass filter which contributes goo phase shift to the loop
and may cause stability problems even with an amplifi·
er which is compensated for unity-gain.
Integrator Circuit
Figure 8 shows the basic circuit connection for performing the mathematical operation of integration. This
circuit is essentially a low-pass filter with a constant
frequency roll-off of - 6 dB per octave.
The circuit must be provided with an external method of
establishing initial conditions. This is shown in the figure as the double-pole, single-throw switch 81. When
81 is in position 1, the amplifier is connected in unitygain configuration, and capaCitor C1 is discharged, setting an initial condition of zero volts. When 81 is in posi-
A practical differentiator which corrects the high frequency nOise problem is shown in Figure 7. Here both
the stability and noise problems are corrected by addi1-266
tion 2, the amplifier is connected as an integrator, and
its output will be the time-integral of the input voltage.
c,
r---------,S'B
I
I
I
I
c,
I
I
I
I
I
VOUT
S'AI
fL
=-'-
2nR,C,
fC=-'-
2nR3C,
Av=-~
R,
Figure 9. A Simple Low-Pass Filter ClrcuH
Figure 8. The Integrator Circuil
The cautions to be observed with this circuit are two:
the amplifier used should generally be stabilized for
unity-gain operation and R2 must equal R1 for minimum
error due to bias current.
60
40
The simple low-pass filter is shown in Figure 9. This circuit has a 6 dB per octave roll-off after a closed-loop
3-dB point defined by fC. Gain below this corner frequency is defined by the ratio of R3 to R1. The circuit
may be considered as an AC integrator at frequencies
well above fC; however, the time domain response is
that of a single RC rather than an integral.
20
o
A gain vs. frequency plot of circuit response is shown in
Figure 10 to illustrate the difference between this circuit and the true integrator. Note that the frequency response is flat for frequencies below fC
where fC
A3
A,
-=100
fe
Simple Low-Pass Filter
-20
0-1
= __1_
""""
10
fL
~
100
1000
Normalized Frequency. fife
2·n-R3 C1
Current-to-Voltage Converter
Figure 10. Frequency Response 01 the Simple Low-Pass
Filter
Current may be measured in two ways with an operational amplifier: the current may be converted into a
voltage with a resistor and then amplified or it may be
injected directly into a summing node. Converting into
voltage is undesirable for two reasons: first, an impedance is inserted into the measuring line causing an error; second, amplifier offset voltage is also amplified
with a subsequent loss of accuracy. The use of a
current-to-voltage converter avoids both of these problems.
scale factor of this circuit is R1 volts per ampere of current. The only conversion error in this circuit is the bias
current of the operational amplifier input which is
summed algebraically with the input current, liN. The
main design constraints are that scale factors must be
chosen to minimize errors due to bias current and since
voltage gain and source impedance are often indeterminate (as with photocells) the amplifier must be compensated for unity-gain operation.
The current-to-voltage converter is shown in Figure 11.
The input current is fed directly into the summing note,
and the amplifier output voltage changes to extract the
same current from the summing node through R1. The
1-267
V+
Rl
10
~
Rl
......... 'IN
+
VOUT
1-
':'
VOUT = -liN Rl
VIN
-=-
SDK
Figure 11. Operational Amplifier as a Current-to-Voltage
Converter
Voltage Controlled Current-Source
Figures 12, 13, and 14 show three simple circuit config·
urations for voltage·controlled constant·current stages.
The circuit of Figure 12 is a basic current·sink circuit
which uses a pair of Darlington connected NPN transis·
tors external to the operational amplifier. Assuming that
the base current of T 1 is negligible compared to the
controlled current 10, the current of the output transis·
tors is equal to VIN/Rl.
Figure 13. Voltage-Controlled Current-Source Circuit
Figure 14 shows an alternate approach to obtaining a
voltage·controlled current source which does not reo
quire additional active devices. The circuit provides an
output current proportional to the input voltage VIN. If
the resistors Rl through R4 are chosen to be equal and
much larger than R5, then the output current is:
10
The above expression assumes that the current
through R3 is much smaller than 10.
R4
Figure 14. A Voltage-Controlled Current Source Circuit
Which Does Not Require External Active Devices
Figure 12. Voltage-Controlled Current-Sink Circuit
This circuit can supply an output current of either polarity, up to the maximum positive or negative output cur·
rent available from the operational amplifier. The maxi·
mum voltage compliance of the output is limited by the
output swing of the operational amplifier minus the volt·
age drop across the sensing resistor, R5.
Figure 13 shows a current·source circuit which uses a
composite connection of external PNP and NPN tran·
sistors and produces a constant output current which is
proportional to the net voltage drop across the sensing
resistor, R 1.
1·268
Triangle Wave Oscillator
state until the voltage at its input again reverses. The
complete circuit operation may be understood by examining the operation with the output of the threshold detector in the positive state. The detector positive saturation voltage is applied to the integrator summing junction through the combination R3 and R4 causing the
current IA to flow.
A constant amplitude triangular wave generator is
shown in Figure 15. This circuit provides a variable frequency triangular wave whose amplitude is independent of frequency. This entire circuit can be built inexpensively, using a dual operational amplifierlC, such as
the XR-4558.
The integrator then generates a negative-going ramp
with a rate of IA/C1 volts per second until its output
equals the negative trip point of the threshold detector.
The threshold detector then changes to the negative
output state, and supplies a negative current, IB, at the
integrator summing point. The integrator now generates
a positive-going ramp with a rate of IB/C1 volts per second until its output equals the positive trip point of the
threshold detector, where the detector again changes
output state and the cycle repeats.
INTEGRATOR
C1
Triangular wave frequency is determined by R3, R4 and
C1 and the positive and negative saturation voltages of
the amplifier A1. Amplitude is determined by the ratio of
R5 to the combination of R1 and R2 and the threshold
detector saturation voltages. Positive and negative
ramp rates are equal and positive and negative peaks
are equal if the detector has equal positive and negative saturation voltages. The output waveform may be
offset with respect to ground if the inverting input of the
threshold detector, A1, is offset with respect to ground.
8.2K
Figure 15_ A Simple Triangle Wave Oscillator
The generator embodies an integrator as a ramp generator and a threshold detector with hysteresis as a reset
circuit. The integrator has been described in a previous
section and requires no further explanation. The threshold detector is similar to a Schmitt trigger in that it is a
latch circuit with a large dead zone. This function is implemented by using positive feedback around an operational amplifier. When the amplifier output is in either
the positive or negative saturated state, the positive
feedback network provides a voltage at the noninverting input which is determined by the attenuation
of the feedback loop and the saturation voltage of the
amplifier. To cause the amplifier to change states, the
voltage at the input of the amplifier must be caused to
change polarity by an amount in excess of the amplifier
input offset voltage. When this is done, the amplifier
saturates in the opposite direction and remains in that
The generator may be made independent of temperature and supply voltage if the detector is clamped with
matched zener diodes.
The integrator section should be compensated for
unity-gain. The detector section may require compensation if power supply impedance causes oscillation
during its transition time. The current into the integrator
should be large with respect to the input bias current
for maximum symmetry; and offset voltage should be
small with respect to peak output voltage swing.
1-269
Choosing the Right Op Amp
Because of its versatility and ease of application, the
op-amp is often the easiest active component to design
into the circuit. However, once the initial "paper design" is accomplished, the user is faced with the key
question: which op-amp is the best choice for the particular application? The availability of a very wide
choice of IC op-amps of varying part numbers, types
and features does not make the answer to this question
an easy one. If the op-amp characteristics are not carefully considered, the total system performance may be
degraded: similarly if each op-amp is overspecified with
an excessive amount of "overkill" for the particular application, then the system cost will increase unnecessarily. The key selection criteria is finding the lowest
cost operational amplifier which will be sufficient to
meet the system performance requirements. This section provides a brief summary of various classes of IC
op-amps, their features and key applications, to assist
the user in choosing the most cost-effective operational
amplifier for his application.
they can be operated with a single positive supply, and
still be able to detect or sense small signals near
ground potential. The particular circuit recommended
for this application is Exar's XR-3403 quad operational
amplifier.
Programmable Op-Amps
Programmable op-amps allow the user to "program" or
set the operating current levels within the IC op-amp by
means of an external setting reSistor, and thus be able
to trade-off power dissipation for slew-rate or signal
bandwidth. These Circuits are normaHy available in
quad form, where the power levels of all or some of the
op-amps in the package can be programmed by one or
two external setting resistors. The key areas of applications for programmable op-amps are active filters and
telecommunication channel filters where the user is
normally concerned with power dissipation. These opamps can also be programmed to operate at micropower levels, by the choice of external setting resistors.
General Purpose Op-Amps
The programmable quad operational amplifiers are
available with either one or two separate setting controls. Those with a single setting control have all four of
the operational amplifiers programmed from same current setting control. Those with two setting controls
have the four op-amps on the chip programmed either
in groups of two, or in groups of one and three op-amps.
The advantage of partitioned programming is that some
of the op-amps in the IC package can be operated at a
different power or bandwidth level than the rest of the
op-amps in the same chip. For example, in an active filter application, the three op-amps performing the filtering can be operated at a low-power level, yet the fourth
op-amp which may be serving as an output buffer can
be operated at a higher power level to provide loaddrive capability.
A wide variety of op-amp applications such as lowfrequency amplifiers, active filters, vOltage-to-current
converters and voltage regulators are most economically accomplished using the low-cost general purpose
IC op-amps. These op-amps are almost all variations of
the basic 741-type op-amp, and offer significant cost
savings over any special-purpose op-amps. They are
commercially available in Single, dual or quad versions.
The dual and quad op-amps are particularly costeffective for applications such as active filters which require a multiplicity of op-amps. The cost per op-amp is
usually lower if one can use multiple op-amp IC's rather
than single op-amps.
The single and dual general purpose op-amps are available in both internally compensated and uncompensated versions. The quad op-amps are almost invariably internally compensated, to reduce the IC package pin
count. Most general purpose IC op-amps have comparable electrical characteristics, namely open loop gain
of ;:: 20 mVIV, small-signal unity gain bandwidth of 1 to
2 MHz and a slew rate of '" 1V/p.sec.
Exar offers the broadest product line of programmable
op-amps in the industry: The XR-4202, XR-146 and the
XR-346-2 families of op-amps are all-bipolar programmable quad op-amp circuits. The XR-4202 offers a single current-setting control for all of the four op-amps on
the chip; the XR-146 and the XR-346-2 offer partitioned
programming of the four op amps. The XR-094 and
XR-095 families are programmable FET-input quad opamps which have the same pin configuration as the
XR-146 and the XR-346-2 families, respectively. These
programmable FET-input quad op-amps are fabricated
using Exar's ion-implanted bipolar/FET or BIFET process technology which combines matched junction
FETs and high-performance bipolar transistors on the
same chip.
Exar manufactures a wide choice of dual or quad general purpose op-amps. All of these op-amps are internally compensated to make them cost-effective and reduce the external parts count. Exar's general purpose
op-amps recommended for most applications are
XR-1458 and XR-4558 for duals, and XR-4136, XR-4212
and XR-4741 for quad op-amps.
Ground Sansing Op-Amps
FET-Input Op-Amps
These types of op-amps have an input stage commonmode range which extends all the way to the negative
supply rail. This is obtained by using Darlingtonconnected PNP transistors at the input stage of the opamp. The key advantage of this class of op-amps is that
Finite input impedance or input bias currents associated with conventional bipolar op-amps can be a problem in specific applications such as sample-hold circuits or signal sensing applications from high1-270
impedance signal source such as transducer systems.
For such applications, op-amps with junction-FET input
stages offer significant performance advantages since
they offer input resistances of the order of 10 12 ohms,
and input bias currents in the low pi co-ampere range.
Another unique feature of FET-input op-amps is their
high slew-rate and wide bandwidth. For example, most
FET-input op-amps offer slew-rates in excess of 10
V/p.sec and unity gain bandwidth of 3 MHz.
low noise characteristics than the FET-input op-amps.
Exar manufactures a number of low noise op-amp circuits uniquely suited to audio applications. Among Exar's family of low noise op-amps, the XR-5534 operational amplifier, and its dual versions, the XR-5532 and
the XR-5533 offer the best noise performance.
The FET-input op-amps offer somewhat higher offset
voltages and input noise than all-bipolar op-amps.
In addition to low noise characteristics, another key
performance requirement for audio applications is low
distortion. The distortion characteristics of op-amps are
normally determined by the design of the output stage
as well as the amplifier bandwidth characteristics. The
total harmonic distortion (THD) is made up of three
components: (a) intermodulation distortion; (b) crossover distortion which depends on output stage design,
and (c) slew-induced distortion which occurs when the
output of the op-amp is forced to slew faster than its
slew-rate.
Low Distortion Op-Amps
Exar offers a wide selection of FET-input dual and quad
op-amps which are manufactured using Exar's ionimplanted BIPOLAR/FET process. The XR-082/XR-083
are dual op-amps; the XR-084 is a quad FET-input opamp. The XR-094 and the XR-095 are programmable
quad FET-input op-amps. Because of their low power
capability, the programmable JFET op-amps are particularly suitable for low-power active filter designs.
Low Noise Op-Amps
The cross-over distortion can be avoided by using opamps which have class-AB, rather than class-B type
output stages. All of Exar's op-amps fall into this category.
These op-amps are particularly suited for audio amplifier and mixer applications, where low noise is of prime
importance. The noise characteristics of an op-amp are
determined by the noise generated at the input stage,
since the noise generated at this point is amplified by
the full open-loop gain of the a..illPlifier. In most cases,
input noise voltages of 10 nV/y'Hz or less is required to
be suitable for high quality or professional audio Signal
processing applications. Such low noise characteristics are normally obtained by careful device deSign and
manufacturing processing of the Ie chips. In general,
all-bipolar operational amplifiers tend to have better
To avoid slew-induced distortion, one should ensure
that the slew rate of the amplifier is never exceeded
during the excursions of the input signal. The highspeed operational amplifiers such as Exar's XR-5533 or
XR-5534 op-amps which have slew rates in excess of
10 V/p.sec with a power bandwidth of 200 kHz can easily cover the entire audio frequency range without introducing slew-induced distortion.
1-271
XR·082/083
Dual Bipolar J FET
Operation~1
Amplifier
FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
The XR-082/XR-083 family of dual bipolar JFET operational amplifiers are designed to offer higher performance than conventional bipolar op amps. Each amplifier
features high slew rate, low input bias and offset currents, and low offset voltage drift with temperature.
These operational amplifier circuits are fabricated using ion-implantation technology which combines wellmatched junction JFETs and high-performance bipolar
transistors on the same monolithic chip.
XR·082
The XR-082 of family of dual bipolar JFET op amps are
packaged in 8-pin dual-in-line packages. The XR-083
family of op amps offer independent offset adjustment
for each of the individual op amps on the same chip,
and are available in 14-pin dual-in-line packages.
OUTPUT A
-Vee
-INPUT A
OUTPUT B
+INPUT A
-INPUT B
+INPUT B
FEATURES
Direct Replacement for TL082ITL083
Low Power Consumption
Wide Common-Mode and Differential Voltage Ranges
Low Input Bias and Offset Currents
Output Short Circuit Protection
High Input Impedance .. JFET Input Stage
Internal Frequency Compensation
Latch-Up-Free Operation
High Slew Rate .. 13 V/p.s, Typical
XR-083
OFFSET
NULL A
-INPUT A
APPLICATIONS
Buffer Amplifiers
Summing/Differencing Amplifiers
Instrumentation Amplifiers
Active Filters
Signal Processing
Sample and Differencing
I to V Converters
Integrators
Simulated Components
Analog Computers
+INPUT A
13
+Vee
OFFSET
NULL A
12
OUTPUT A
-VEE
11
Ne
OFFSET
NULL B
OUTPUT B
+INPUT B
-Vee
-INPUT B
OFFSET
NULL B
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
±18V
Differential Input Voltage
±30V
Input Voltage Range (Note 1)
±15V
Output Short Circuit Duration (Note 2)
Indefinite
Package Power Dissipation:
Plastic Package
625mW
5.0 mWoC
Derate Above TA = +25°C
Ceramic Package
750 mW
6.0 mW/oC
Derate Above TA = + 25°C
Storage Temperature Range
- 65°C to + 150°C
ORDERING INFORMATION
1-272
Part Number
Package
XR-082MIXR-083M
XR-082N/XR-083N
XR-082PIXR-083P
XR-082CN/XR-083CN
XR-082CP/XR-083CP
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Operating Temperature
-55°C to
- 25°C to
- 25°C to
O°C to
O°C to
+125°C
+ 85°C
+ 85°C
+ 70°C
+ 70°C
XR·082/083
ELECTRICAL CHARACTERISTICS TA
= 25°C, VCC =
± 15V, unless otherwise specified.
XR·D82MI
XR·083M
SYMBOL
PARAMETERS
3
Offset Voltage
Temp. Coel.
10
IB
Input Bias Current
30
IB
Input Bias Current
Over Temp.
l!.VOS/l!.T
lOS
Input Offset Current
5
Input Common Mode
Range
AVOL
Voltage Gain
VOPP
Max. Output Swing
(peak-to-peak)
1.4
±12
50
Input Resistance
BW
Unity-Gain Bandwidth
24
24
6
g
200
200
30
200
30
20
100
5
100
5
10
2.8
1.4
50
24
24
15
20
2.8
1.4
±10
200
25
27
24
24
UNIT
mV
mV
p.V/oC
10
25
27
5
10
±12
25
RIN
3
20
Supply Current
(per amplifier)
ViCM
6
g
50
I nput Offset Cu rrent
Over Temp.
ICC
XR·D82CI
XR·083C
MIN TYP MAX MIN TYP MAX MIN TYP MAX
Input Offset Voltage
Vas
Vas
XR·D821
XR·D83
400
pA
20
nA
200
pA
5
2.8
= Full Range
nA
TA
=
mA
No Load,
No Input Signal
200
V/mV
RL 2: 2 k{},
Va = ±10V
TA = Full Range
27
V
RL 2: 10 k{}
TA = Full Range
15
10 12
10 12
10 12
{}
3
3
3
MHz
80
86
80
86
70
76
dB
PSRR
Supply-Voltage
Rejection
80
86
80
86
70
76
dB
dB
120
120
120
dVOUTIDT Slew Rate
13
13
13
Rise Time
0.1
0.1
0.1
10
10
10
20
20
20
TO
EN
Overshoot
Equivalent Input
Noise Voltage
Full Range
V
Common-Mode
Rejection
TR
= 50{}
= 50{},
= Full Range
RS = 50{},
TA = Full Range
TA
CMRR
Channel Separation
CONDITIONS
RS
RS
TA
RS
:$
10 k{}
AV = 100,
Freq. = 1 kHz
= 1,
= 2 k{}
= 100 pF,
= 10V
p'sec AV = 1,
RL = 2 k{}
%
CL = 100 pF,
V1 = 20 mV
nV/...rRz RS = 100{}
f = 1 kHz
V/p.S
AV
RL
CL
V1
Nota 1: For Supply Voltage less than ± 15 V, the absolute maximum input voltage is equal to the supply voltage.
Nota 2: The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be
limited to ensure that the dissipation rating is not exceeded.
1-273
XR·082/083
+Vcc o-------------~----------------~~--------~--------~--------~--~_,
NON,INVERTING
INPUT
INVERTING
INPUT
0-------------+-----------------.
o---.. . . I+-r----~----------,
rI
+Vcc
12811
+-~W"v---t------+-o OUTPUT
I
I
1
610 II
610 II
I
I
I
o--+----~--------~------~~~~--------~----------~--------~----~~-J
o
b
(N1)'
OFFSET NULL
(N2)'
OFFSET NULL
'AVAILABLE IN XR·083 ONLY.
(ONE CHANNEL ONLY)
EQUIVALENT SCHEMATIC DIAGRAM
1-274
XR·084
Quad Bipolar J FET Operational Amplifier
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-084 quad bipolar JFET operational amplifier is
designed to offer higher performance than conventional bipolar quad op amps. Each of the four op amps on
the chip is closely matched in performance characteristics, and each amplifier features high slew rate, low
input bias and offset currents, and low offset voltage
drift with temperature. The XR-084 JFET input quad op
amp is fabricated using ion-implanted bipolar JFET
technology which combines well-matched JFETs and
high-performance bipolar transistors on the same monolithic integrated circuit.
OUTPUT A
OUTPUT D
-INPUT A
-INPUT D
+INPUTA
+INPUT 0
-VEE
+Vce
+INPUT B
+INPUT C
-INPUT B
-INPUT
OUTPUTB
OUTPUT
FEATURES
Direct Replacement for TL084
Same Pin Configuration as XR-3403, LM324
High-Impedance JFET Input Stage
Internal Frequency Compensation
Low Power Consumption
Wide Common-Mode and Differential Voltage Ranges
Low Input Bias and Offset Currents
Output Short Circuit Protection
Latch-Up-Free Operation
High Slew Rate ... 13 V/p.s, Typical
e
e
APPLICATIONS
ORDERING INFORMATION
Buffer Amplifiers
SumminglDifferencing Amplifiers
Instrumentation Amplifiers
Active Filters
Signal Processing
Sample and Differencing
I to V Converters
Integrators
Simulated Components
Analog Computers
Part Number
Package
Operating Temperature
XR-084M
XR-084N
XR-084P
XR-084CN
XR-084CP
Ceramic
Ceramic
Plastic
Ceramic
Plastic
- 55°C to + 125°C
- 25°C to + 85°C
- 25°C to + 85°C
O°C to + 70°C
O°C to + 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
±18V
Differential Input Voltage
±30V
±15V
Input Voltage Range (Note 1)
Output Short Circuit Duration (Note 2)
Indefinite
Package Power Dissipation:
625 mW
Plastic Package
5.0 mW/oC
Derate Above TA = +25°C
750mW
Ceramic Package
6.0 mW/oC
Derate Above TA = +25°C
- 65°C to + 150°C
Storage Temperature Range
SYSTEM DESCRIPTION
The XR-084 is a quad JFET input operational.amplifier
featuring extremely high input reSistance, low input bias and offset currents, large common mode voltage
range, and large output swing range. Unity gain bandwidth is 3 MHz and slew rate is 13V/"S. The devices are
unity gain compensated.
1-275
XR·084
ELECTRICAL CHARACTERISTICS TA
25°e, vee
± 15, unless otherwise specified.
XR·084M
SYMBOL
PARAMETERS
MIN
XR·084
TYP
MAX
3
6
vas
Vas
Input Offset Voltage
J;.vOS"n
Offset Voltage
Temp. Coel.
10
IB
Input Bias Current
30
IB
Input Bias Current
Over Temp.
MIN
MAX
3
6
10
200
30
50
Input Offset Current
5
Input Offset Current
Over Temp.
ICC
Supply Current
(per amplifier)
VICM
Input Common Mode
Range
AvOL
Voltage Gain
100
5
50
200
25
1.4
2.8
50
200
25
27
CONDITIONS
mV
mV
RS = 500
RS = 500,
TA = Full Range
~VloC
RS = 500,
TA = Full Range
10
200
30
100
5
24
24
2.8
1.4
25
400
pA
20
nA
200
pA
5
nA
TA = Full Range
2.8
mA
No Load,
No Input Signal
27
RIN
Input Resistance
BW
Unity·Gain Bandwidth
CMRR
Common·Mode
Rejection
80
86
80
86
PSRR
Supply·Voltage
Rejection
80
86
80
86
24
24
TA = Full Range
V
200
VlmV
RL '" 2 kll,
Vo = ±10V
TA = Full Range
27
V
RL'" 10 kO
TA = Full Range
15
Max. Output Swing
(peak·to·peak)
Channel Separation
UNIT
15
20
±10
VOpp
24
24
MAX
5
10
±12
±12
TYP
20
20
1.4
MIN
9
9
lOS
XR·084C
TYP
1012
10'2
10'2
0
3
3
3
MHz
70
76
dB
70
76
dB
120
120
120
dB
RS:S 10 kll
Av = 100,
Freq. = 1 kHz
DVOUTIDT
Slew Rate
13
13
13
VI~S
Av
RL
CL
VI
= 1,
='2kll
= 100 pF,
= 10V
TR
Rise Time
Av
RL
CL
V1
= 1,
= 2 kll
= 100 pF,
=20mV
0.1
0.1
0.1
",sec
TO
Overshoot
10
10
10
%
EN
Equivalent Input
Noise Voltage
20
20
20
nVl.JFiz
RS = 1000
f = 1 kHz
Note 1: For Supply Voltage less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
Note 2: The output may be shorted to ground or to either supply. Temperature andlor supply voltages must be limited to ensure that the dissipation rating
is not exceeded.
-::~ ==:;:::::C==::;--=:l
EQUIVALENT SCHEMATIC DIAGRAM
1·276
XR·094/095
Quad Programmable Bipolar J FET
Operataonal Amplifiers
FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
The XR-094 and XR-095 bipolar JFET input quad programmable operational amplifiers consist of four independent, high gain, internally compensated amplifiers.
Two external resistors (RSET) allow the user to program
supply current slew-rate input noise without the usual
sacrifice of gain bandwidth product. For example, the
user can trade-off slew-rate for supply current or optimize the noise figure for a given source impedance. Except for the two programming pins at the end of the
package, the XR-094 and XR-095 pin-out is the same as
the popular 324, 3403, 124, 148 and 4741 operational
amplifiers.
OUTPUT A
1
-INPUT A 2
+INPUT A 3
-VEE
+INPUT C
+INPUT B 5
OUTPUT B 7
In the case of the XR-094, three of the op amps on the
chip share a common programming pin; and the fourth
op amp is programmed separately. In the case of the
XR-095, each pair of op amps share a common programming pin.
FEATURES
Same Pin Configuration as LM-346
High-Impedance FET Input Stage
Internal Frequency Compensation
Low Power Consumption
Wide Common-Mode and Differential Voltage Ranges
Low Input Bias and Offset Currents
Output Short-Circuit Protection
High Slew-Rate ... 13 V/p.s, Typical
Programmable Electrical Characteristics
+INPUT C
-INPUT C
ABSOLUTE MAXIMUM RATINGS (Continued)
Derate Above TA = + 25°C
Ceramic Package
Derate Above TA = + 25°C
Storage Temperature Range
APPLICATIONS
Total Supply Current = 5.6 mA (ISET/320 p.A)
Slew Rate = 13 V/p.s (ISET/320 p.A)
ISET = Current into set terminal
ISET =
Note 1: For Supply Voltage less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
VCC - (VEE - O.6V)
RSET
Note. ISET must be
:$
Note 2: The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded.
400p.A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Differential Input Voltage
Input Voltage Range (Note 1)
Output Short-Circuit Duration (Note 2)
Package Power Dissipation:
Plastic Package
5.0 mV/oC
750 mW
6.0 mW/oC
-65°C to +150°C
ORDERING INFORMATION
±18V
±30V
±15V
Indefinite
625 mW
1-277
Part Number
Package
XR-094/XR-095N
XR-094/XR-095P
XR-094/XR-095CN
XR-094/XR-095CP
Ceramic
Plastic
Ceramic
Plastic
Operating Temperature
-25°C
- 25°C
O°C
DoC
to
to
to
to
+85°C
+ 85°C
+70°C
+70°C
XR·094/095
ELECTRICAL CHARACTERISTICS
TA = 25°C, Vce = ± 15V, unless otherwise specified.
ISET = 320 p.A.
XR-094/095
PARAMETERS
XR-094/095C
MIN TYP MAX MIN TYP MAX
Input Offset Voltage
3
Offset Voltage
Temp. Coef.
10
6
5
15
20
9
UNITS
SYMBOL
CONDITIONS
mV
mV
VOS
VOS
RS = 500, TA = 25°C
RS = 500, TA = Full Range
p.V/oC
10
Input Bias Current
IB
80
600
20
80
800
20
pA
nA
40
300
10
40
500
5
pA
nA
1.4
2.8
1.4
2.8
mA
ICC
V
ViCM
Input Offset Current
±12
±10
Voltage Gain
Max. Output Swing
(peak-to-peak)
= 25°C
= Full Range
TA
TA
= 25°C
= Full Range
200
25
15
200
24
24
27
24
24
27
Input Resistance
Unity-Gain Bandwidth
V
Full Range
No Load, No Input Signal
AVOL
RL ~ 2KO, Vo = ±10V
TAo = 25°C
TA = Full Range
VOpp
RL ~ 10 KO
TA = 25°C
TA = Full Range
V/mV
50
25
= 500, TA =
TA
TA
lOS
Supply Current
(per amplifier)
Input Common Mode
Range
AVOS/AT RS
10"
10"
0
Rin
TA
3
3
MHz
BW
TA
Common-Mode Rejection
80
86
70
76
dB
CMRR
Supply-Voltage Rejection
80
86
70
76
dB
PSRR
= 25°C
= 25°C
RS::;; 10 KO
=
= 1 kHz
120
120
dB
Slew Rate
13
13
V/p.S
dVout/dt
Rise Time
Overshoot
0.1
10
0.1
10
p'sec
%
tr
to
AV = 1, RL = 2 KO
CL = 100 pF, VI = 20 mV
Equivalent Input
Noise Voltage
18
18
nV/.JHz
en
RS = 1000
f = 1 kHz
Channel Separation
(One Channel
Only~
EQUIVALENT SCHEMATIC DIAGRAM
1-278
AV
100, Freq.
h.J
= 1, RL = 2 KO
CL = 100 pF, VI = 10V
fEWDtlfEj)
XR·096
~411f'%
lPrnQ)~rrCB1rmma!b~e Bipolar
(Q)[p)®rr~~n(Q)trllal ~ Am!p~ niner
(Q)lUJaltdJ
GENERAL DESCRIPTION
JFET
FUNCTIONAL BLOCK DIAGRAM
The XR-096 monolithic circuit contains four independently programmable JFET operational amplifiers in a
single IC package. Each of the four op amp sections on
the chip has its own external bias terminal; thus its performance characteristics and power dissipation can be
independently controlled, without effecting the other op
amp sections on the chip. The respective bias-setting
resisters, RSET, connected to the programming terminals of the circuit allow one to trade-off power dissipation for slew-rate, without sacrificing the gainbandwidth product of the circuit. These individual bias
terminals can also be used to switch the op amp sections "on" and "off", and thus, multiplex between various op amp channels on the same chip.
SET A
OUTPUT A
-INPUT A
+INPUT A
+Vcc
+INPUT B
FEATURES
-INPUT B
Programmable Version of XR-084
Independent Programming of All Four Op Amps
Programmable for Micropower Operation
High-Impedance JFET Input Stage
Internal Frequency Compensation
Low Input Bias and Offset Currents
OUTPUT B
SET B
APPLICATIONS
Total Supply Current = 5.6 mA (ISET/320 pA)
Slew-Rate = 13 V/p.s (ISET/320 pA)
ISET = Current into set terminal
ORDERING INFORMATION
Part Number
Package
ISET = _VC:::,:C=---...,:(....,:VE::.::E:....-_0_.6....:,V)
XR-096N
XR-096P
XR-096CN
XR-096CP
Ceramic
Plastic
Ceramic
Plastic
RSET
Note. ISET must be
:$
400p.A
Operating Temperature
-25°C to
- 25°C to
DoC to
DoC to
+85°C
+ 85°C
+ 70°C
+ 70°C
ABSOLUTE MAXIMUM RATINGS
±18V
Supply Voltage
±30V
Differential Input Voltage
±15V
Input Voltage Range (Note 1)
Indefinite
Output Short-Circuit Duration (Note 2)
Package Power Dissipation:
625mW
Plastic Package
5.0 mV/oC
Derate Above TA = +25°C
750 mW
Ceramic Package
6.0 mW/oC
Derate Above TA = +25°C
- 65°C to + 150°C
Storage Temperature Range
The XR-096 is a quad independently programmable
JFET input operational amplifier featuring extremely
high input resistance, low input bias and offset current,
large common mode voltage range, and large output
swing range. Unity gain bandwidth is 3 MHz, and slew
rate is 13V/p.S. The devices are unity gain compensated.
Note 1: For Supply Voltage less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
Note 2: The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded.
Each of the form amplifiers may be independently
"programmed"-rebiased-by connecting a resistor from
the bias adjust pin to the positive supply. Bias c.urrent
may range up to 400 p.A, thus affording the designer
flexibility along the POWfH consumption/speed curve.
SYSTEM DESCRIPTION
1-279
XR·096
ELECTRICAL CHARACTERISTICS
TA = 25°C, Vcc
ISET = 320 pA.
=
± 15V, unless otherwise specified.
XR-096
PARAMETERS
XR-096C
MIN TYP MAX MIN TYP MAX
Input Offset Voltage
3
6
Offset Voltage
Temp. Coel.
10
5
9
15
20
UNITS
SYMBOL
CONDITIONS
mV
mV
VOS
VOS
RS = 500, TA = 25°C
RS = 500, TA = Full Range
p.v/oC
10
aVOS/aT RS = 500, TA = Full Range
Input Bias Current
IB
80
600
20
80
800
20
pA
nA
40
300
10
40
500
5
pA
nA
1.4
2.8
1.4
2.8
mA
ICC
V
ViCM
TA = 25°C
TA = Full Range
Input Offset Current
lOS
Supply Current
(per amplifier)
Input Common Mode
Range
±12
±10
Voltage Gain
Max. Output Swing
(peak-to-peak)
TA = 25°C
TA = Full Range
V/mV
50
25
200
25
15
200
24
24
27
24
24
27
Input Resistance
Unity-Gain Bandwidth
No Load, No Input Signal
AVOL
RL ;?; 2KO, Vo = ±10V
TA = 25°C
TA = Full Range
V
VOpp
RL ;?; 10 KO
TA = 25°C
TA = Full'Range
10"
10"
0
3
3
MHz
Rin
BW
Common-Mode Rejection
80
86
70
76
dB
CMRR
Supply-Voltage Rejection
80
86
70
76
dB
PSRR
TA = 25°C
TA = 25°C
RS ~ 10 KO
Channel Separation
120
120
dB
Slew Rate
13
13
V/p.S
Rise Time
Overshoot
0.1
10
0.1
10
p'sec
%
tr
to
AV = 1, RL = 2 KO
CL = 100 pF, V1 = 20 mV
Equivalent Input
Noise Voltage
18
18
nV/..JHz
en
RS = 1000
f = 1 kHz
AV 100, Freq. = 1 kHz
dVout/dt AV = 1, RL = 2 KO
CL = 100 pF, V1 = 10V
. "'.
etIIvtltTIMI
.VII
(Onl Channel Onlyl
.........."
EQUIVALENT SCHEMATIC DIAGRAM
1-280
XR·146/246/346
Programmable Quad Operational Amplifiers
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAMS
The XR-146 family of quad operational amplifiers contain four independent high-gain, low-power, programmable op-amps on a monolithic chip. The use of external bias setting resistors permit the user to program
gain-bandwidth product, supply current, input bias current, input offset current, input noise and the slew rate.
J----...._
OUTPUT A
OUTPUT 0
-INPUT 0
+INPUT 0
The basic XR-146 family of circuits offer partitioned
programming of the internal op-amps where one setting resistor is used to set the bias levels in the three
op-amps, and a second bias setting is used for the remaining op-amp. Its modified version, the XR-346-2 provides a separate bias setting resistor for each of the
two op-amp pairs.
-VEE
FEATURES
ISET
Programmable
Micropower operation
Low noise
Wide power supply range
Class AB output
Ideal pin out for biquad active filters
Overload protection for input and output
Internal frequency compensation
+INPUT C
-INPUT C
OUTPUTC
OUTPUT A
-INPUT A
+INPUT A
-VEE
APPLICATIONS
Total Supply Current = 1.4 mA (ISET/10 p.A)
Gain Bandwidth Product = 1 MHz (lSET/10p.A)
Slew Rate = O.4V/p.s (ISET/10 p.A)
Input Bias Current == 50 nA (lSET/1 0 p.A)
+INPUT B
+INPUTC
-INPUT B
-INPUTC
OUTPUT B
OUTPUT C
ISET
ISET = Current into pin 8, pin 9 (see schematic)
V+ -V- -0.6V
ISET =
RSET
XR-346-2
ABSOLUTE MAXIMUM RATINGS (continued)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
XR-146
XR-246/346
Differential Input Voltage (Note 1)
XR-146/246/346
Common Mode Input Voltage (Note 1)
XR-146/246/346
Power Dissipation (Note 2)
XR-146
XR-246/346
Output Short Circuit Duration (Note 3)
XR-146/246/346
Maximum Junction Temperature
XR146
XR-246
XR-346
Storage Temperature Range
XR-146/246/346
±22V
±18V
±30V
ORDERING INFORMATION
±15V
900mW
500mW
Indefinite
1-281
Part Number
Package
Operating Temperature
XR-146M
XR-246N
XR-246P
XR-3461
346-2CN
XR-3461
346-2CP
Ceramic
Ceramic
Plastic
- 55°C to + 125°C
-25°C to +85°C
-25°C to +85°C
Ceramic
O°C to + 70°C
Plastic
O°C to + 70°C
XR·146/246/346
=
ELECTRICAL CHARACTERISTICS (TA
=
+25°C, Vs
± 15V, ISET
XR-146
PARAMETERS
MIN
Input Offset Voltage
= 10,.A)
XR-246/346
TYP
MAX
0.5
5
MIN
TYP
MAX
UNITS
0.5
6
mV
VCM = OV,
RS s 500
CONDITIONS
Input Offset Current
2
20
2
100
nA
VCM
Input Bias Current
50
100
50
250
nA
VCM
1.4
2.0
1.4
2.5
Supply Current (4 Op·Amps)
Large Signal Voltage Gain
Input CM Range
100
1000
50
1000
mA
V/mV
RL = 10 kO,
.6.VOUT = ±10V
±13.5
±14
±13.5
±14
V
CM Rejection Ratio
80
100
70
100
dB
RS
Power Supply Rejection Ratio
80
100
74
100
dB
RS
±12
±14
±12
±14
V
RL
Output Voltage Swing
Short·Clrcult Current
Gain Bandwidth Product
5
20
0.8
1.2
30
5
20
0.5
1.2
30
= OV
= OV
s
s
s
10 kO
10 kO
10 kO
mA
MHz
Phase Margin
60
60
Deg
Slew Rate
0.4
0.4
Vllls
Input Noise Voltage
28
28
nV/,,[Rz
Channel Separation
120
120
dB
Input Resistance
1.0
1.0
MO
Input Capacitance
2.0
2.0
pF
f
= 1 kHz
RL = 10 kO,
.6.VOUT = OVto +12V
The following specifications apply over the Maximum Operating Temperature Range
Input Offset Voltage
0.5
6
0.5
7.5
mV
VCM = OV,
RS s 500
Input Offset Current
2
25
2
100
nA
VCM
Input Bias Current
50
100
50
250
nA
VCM
1.5
2.0
1.5
2.5
mA
25
1000
V/mV
Supply Current (4 Op-Amps)
Large Signal Voltage Gain
Input CM Range
50
1000
= OV
= OV
RL = 10 kO,
.6.VOUT = ±10V
±13.5
±14
±13.5
±14
V
CM Rejection Ratio
70
100
70
100
dB
RS
Power Supply Rejection Ratio
76
100
74
100
dB
RS
±12
±14
±12
±14
V
RL" 10 kO
6
mV
VCM = OV,
RS s 500
VCM = OV
Output Voltage Swing
ELECTRICAL CHARACTERISTICS (TA
= 25°C, Vs =
Input Offset Voltage
0.5
± 15V, ISET
0.5
Input Bias Current
7.5
20
7.5
100
nA
140
250
140
300
IlA
80
ELECTRICAL CHARACTERISTICS (TA
=
Input Offset Voltage
Input CM Range
50
+ 25°C, Vs
=
0.5
5
±0.7
CM Rejection Ratio
Output Voltage Swing
100
± 1.5V, ISET
±0.6
100
±0.7
1-282
kHz
7
mV
VCM = OV,
RS s 500
V
80
±0.6
500
= 10,.A)
0.5
80
500
= 1 ,.A)
5
Supply Current (4 Op-Amps)
Gain Bandwidth Product
s
s
dB
V
RS
s
500
RL" 10 kO
XR·146/246/346
EQUIVALENT SCHEMATIC DIAGRAM
(One Channel Only)
1-------._O:;'I.::.~'7I~------_t_---:':.:,.--__;--
TYPICAL PERFORMANCE CHARACTERISTICS
.
Input Bias Current VI ISET
Open Loop Voltage Gain v.
ISET
Supply Current VI IS ET
lID
~
.5~
..:!
;;
IDO
;
140
"~
120
~
lOG
~
II
•. 1
i!
!!
10
>
ll;
611
~
40
co
2.
VS· 115V
~
o
U
10
IDO
lDO
II
ISET "'AI
Slow Ralllv.ISET
,.1.1
10
Gain Bandwidth Product VI
ISET
IDO
11
Pha.o Margin v. ISET
10.
rf-
••
I" ,.
'"
1M
~
a
:c..
0.1
'SET "'AI
l-
II
f-
~
10
1.1
100'
!il
;:j
1.11
10k
ii
;
50
4.
l-
~
3a
f-
2.
I-
if
,.
VS· !15V
T... ·U·C
a
II
la
1.
lao
lao
•. 1
I•
11
'SET"'AI
'SET"'AI
Slew Rate v.
Temperature
Gain Bandwidth Product
v. Temperature
Open Loop Voltage Gain
Temperature
VI
10'
§§
141
ISET • I "A TO 1O"A
Isn- 1DJ,.A
IlD
IDO
•. 1
••
~
DO
,a" ...
r-
I I I
E'=' 'sn s
Isn· 1"A- rIsn- D.l "A
41
ISET·
f-
0.01
'IJA
I I I
FE E'SET-UIIA
2Q
•
VS·.t15V
-55 -15 -15 5 25 45 15 15 '.5 125
TEM'ERATURE rCI
103
-55 -35 -II
VS·t15V
5 25 45 15 15 105 125
TEM'ERATURE C·CI
1-283
I I I
VS· !'5V
a.ODI
-55 -35 -15 5 25 45 15 15 115 US
TEM'ERATURE rCI
XR·146/246/346
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
~
I
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1111
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la
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II
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~-+-+-~__,-.~~~
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fl.
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1M
FREQUENCY (Ha)
Common-Mode Rejection
Ratio v. ISET
Power Supply Rejection
Ratio v. ISET
'"a '"
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0.1
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I
Power Supply Rejection
Ratio VI Frequency
Input Noise Current VI
Input Nol .. Voltage v.
Frequency
Input Bias Current vs
Inpul Common-Modo
Voltage
Input Voltage Range v.
Supply Voltage
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INPUT CDMMDN-MDOE YOLTAGE (V)
Input Off,et Current VI
Tlmperature
Supply Current VI
Temperature
!I5V
~lsn·IDjlA
c
i-f- f-,.. ~ ••
lA-ZS·C
'---'--",---I.--'---~--'
-15 -10
tI
SUPPLY YOLTAGE by)
Input Bils Current ,I
Temperature
f-+-- f-_1L
VS· !ISV
lA-ZS·t
ISET·fIJlA
s
L. f - - -
!I
>-
a,l
IUT.I ~A
10
I
-IS -35 -II I
• 1-t---f-+++-+VS·!15Y
25 __......__--r-_-o
VOUT
VOUT
100"1
60011
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN LOOP FREQUENCY
RESPONSE
CLOSED LOOP FREQUENCY
RESPONSE
LARGE-SIGNAL FREQUENCY
RESPONSE
vs·,ls
TYPICAL VALUES
TYPICA\.VALUES
I
YPtCAL VALUES
"\
li
~
\
20r-~~~~.-r-~~r--r~
'\
1\
\
10102,03,0.,05,06,0'
10'10'
IDS
lithl
106
101
101
I\HtI
OUTPUT SHORT-CIRCUIT
CURRENT
INPUT BIAS CURRENT
VS~"SV
INPUT COMMON MODE
VOLTAGE RANGE
VS··I!iV
Tvl.CAL vlLu£S
-- '---- r-'N
_v.
r--
0.'
I-- -
--1-+-+-1-+--1
r-r-
--.+--1---+--1---!---1
~
/
r--
/
k
L
o
-55
55
_2!i 0
SUPPLY VOLTAGE IVI
1-308
XR·5532/5532A
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
SUPPLY CURRENT
12
102
INPUT NOISE VOLTAGE DENSITY
r-----r---,----.----,
I~
..(.
"<
E
....2
r
w
a:
a:
=>
>
....
u
---
TYP
~
..,.........
10
.....
w
~
'-'
....
0
>
"-
TYP
W
VI
a2
8:
..
....
....0::
=>
'"
~
101
"VI
102
o
tl0
:!:20
~
____
~~
10
____
~
102
______
______
~
1()4
103
SUPPL Y VOLTAGE (VI
~
FReaUENCY (Hzl
TYPICAL APPLICATION
PREAMPLIFIER-RIAA/NAB
COMPE NSATI ON
JO
"
..
,-,:~
50
BODE PLOT
OUTPUT
-r~",*
"
"
ACTUAL RESPONSF
'\.
'~
Z
~
BOOE PLOT
V-~
-',
30
20
",
JOJ
",
~
",
",
",
fREOUENt;Y IHrl
·SHECT TO PROVIDE SPEClnED TRANSOUCER LOADING
OUTPut NOISE
013 mit .m, I\'\IITH I"IPUT SHORTED'
ALL R£SIS10R VAlUES ARE IN OHMS
ACTUAL
/RESPONSE
'"
'\.
",
'\
,.J
-
,,,.
'.'
FREQUENCY IHrl
RESPONSE l'lEAtllEO IN AN ACTUAl CIRCUn
BODE PLOT OF NAB EQUALIZATION AND THE
RESPONSE REALllED IN THE ACtUAL CIRCUIT USING
USING THE XR !>f>ll
THE XRSSJJ
BODE PLOT OF RIAr. EOUAlIZATION AND THE
EQUIVALENT SCHEMATIC DIAGRAM
1/2 of XR-5532
1-309
XR·5533/5533A
Dual Low-Noise Operational Amplifier
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-5533 dual low-noise operational amplifier is especially designed for applications in high quality professional audio equipment. The low-noise, wide bandwidth
and output drive capability make it ideally suited for instrumentation and control circuits as well as active filter design.
BALANCEI
COMP.A
COMPo A
The XR-5533A is the specially screened version of the
XR-5533 with guaranteed worst-case noise specifications.
OUTPUT A
-VCC
FEATURES
OUTPUTB
Direct Replacement for Signetics SEINE 5533
Wide Small-Signal Bandwidth: 10 MHz
High-Current Drive Capability
(10V rms into 6000 at Vs = ± 18V)
High Slew Rate: 13 V/p.s
Wide Power-Bandwidth: 200 kHz
Very Low Input Noise: 4 nV/..JHZ
COMP.B
BALANCEI
COMP.B
APPLICATIONS
High Quality Audio Amplification
Telephone Channel Amplifier
Servo control Systems
Low-Level Signal Detection
Active Filter Design
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Power Supply
±22V
Input Common-Mode Range
-VEE to +VCC
±0.5V
Differential Input Voltage (Note 1)
Short Circuit Duration (Note 2)
Indefinite
Power Dissipation (Package Limitation)
Ceramic Package 14-Pin
750mW
Plastic Package 14-Pin
600mW
5 mW/oC
Derate Above TA = 25°C
Storage Temperature
- 60°C to + 150°C
Part Number
Package
XR-5533AN
XR-5533AP
XR-5533N
XR-5533P
Ceramic
Plastic
Ceramic
Plastic
Operating Temperature
O°C
O°C
O°C
O°C
to
to
to
to
+70°C
+70°C
+ 70°C
+ 70°C
SYSTEM DESCRIPTION
Note 1: Diodes protect the inputs against over-voltage. Therefore, unless current-limiting resistors are used, large
currents will flow if the differential input voltage exceeds O.BV. Maximum current should be limited to ±
10 mA.
The XR-5533 and XR-5533A are dual monolithic operational amplifiers featuring low noise and very large gain
bandwidth products. The devices have low output resistance and can drive 10 Vrms into 6000. Input noise
is 100 % tested on the XR-5533A. and is typically only 4
nV/..JHZ. The small signal bandwidth is 10 MHz and
slew rate exceeds 13 V/p.S.
Note 2: Output may be shorted to ground at Vee = VEE =
15V, TA = 25°C. Temperature and/or supply voltages
must be limited to ensure dissipation rating is not exceeded.
1-310
XR·5533/5533A
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°e, Vee
= VEE = 15V unless otherwise specified.
XR-5533A
PARAMETERS
MIN.
XR-5533
TYP.
MAX.
0.5
MIN.
TYP.
MAX.
UNITS
4
5
0.5
4
5
mV
mV
20
300
400
20
300
400
nA
nA
500
1500
2000
500
1500
2000
nA
nA
CONOITIONS
SYMBOL
DC CHARACTERISTICS
Inpul Offsel Vollage
Inpul Offsel Currenl
TA = 25'C
TA = Full Range
lOS
Input Bias Current
TA = 25'C
TA = Full Range
IB
Large Signal Voltage
Gain
TA = 25'C
TA = Full Range
AvOL
25
15
Supply Current
(Each Amplilier)
100
4
25
15
VlmV
VlmV
100
8
4
8
mA
Outpul Swing
±12
±15
Oulput Short Circuit
Current
Input Resistance
VOS
±13
±16
±12
±15
±13
±16
V
V
38
mA
38
ICC
VOUT
ISC
30
100
30
100
kO
RIN
Common·Mode
Range
±12
±13
±12
±13
V
ViCM
Common· Mode
Rejection
70
100
70
100
dB
CMRR
p.VN
PSRR
Power Supply
Rejection
10
Channel Separation
110
110
20
20
20
20
%
6
2.2
6
2.2
VlmV
V/mV
Unity·Gain
Bandwidth
10
10
MHz
Slew Rate
13
6
13
6
Vlp.lsec
Vlp.lsec
95
95
kHz
200
200
kHz
7
4
nVI.fRz
nV/.fRz
1.5
0.4
2.5
0.6
pN.fRz
pN.fRz
0.9
0.9
dB
100
10
100
dB
RL'"
VO=
TA =
TA =
6000.
±10V
25'C
Full Range
RL = Open
RL '" 6000
VCC = VEE = 15V
VCC = VEE = 18V
(Note 2)
1= 1 kHz,
RS = 5 kO
AC CHARACTERISTICS
Transient Response
Rise Time
Overshoot
' nsec
tr
to
ACGain
Power Bandwidth
Vollage Follower
RL = 6000,
CC=22pF
CL = 100 pF
VIN = 50 mV
I = 10 kHz
Cc = 0
Cc = 22pF
BW
Cc = 22 pF,
CL = 100 pF
Cc = 0
= 22 pF
Cc
Ip
VOUT = ±10V,
Cc = 22pF
Cc = 0 pF
NOISE CHARACTERISTICS
Input Noise Vollage
en
5.5
3.5
7
4.5
Input Noise Current
Broadband Noise
Figure
10 = 30 Hz
10 = 1 kHz
in
1-311
10 = 30 Hz
10 = 1 kHz
RN
FS = 5 kO
1=10Hzto
20 kHz
XR·5533/5533A
TEST CIRCUITS
FREOUENCY COMPENSATION AND OFFSET
VOLTAGE ADJUSTMENT CI RCUIT
CLOSED LOOP FREOUENCY RESPONSE
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN LOOP FREQUENCY RESPONSE
SLEW-RATE AS A FUNCTION OF
COMPENSATION CAPACITANCE
CLOSED LOOP FREQUENCY
RESPONSE
Vs-' 15V
TYPICAL VAlues
"
"\~
~C'O
CC~22pF'
=0-
1\
_\
~
'\
1'\
He
I'10102,03,04
105
'06
,07
FREQUENCY(Hll
CelpF)
LARGE-SIGNAL FREQUENCY
RESPONSE
Vs
~.
OUTPUT SHORT-CIRCUIT
CURRENT
INPUT BIAS CURRENT
VS ··15V
15V
Vs~
t 15V
.)YP1CAl VALUES
L. / t- ""
22~F
\~ t-47~f
-
_
[1
t-- t-t-- t--
1\
\\\
""0
I'--
I".,
r-- t-';" r-
t::--
m
l - t---
t--
~~
102
103
104
105
106
107
15
100
12!>
50
FRECUENCV(Hzl
"
TAI'C)
INPUT COMMON MODE
VOLTAGE RANGE
INPUT NOISE VOLTAGE
DENSITY
SUPPLY CURRENT
PER OP-AMP
10'
10
TYPICAL VALUES
~
0
~
m
ld
f
~
' / pos
r
f---' r---
~
~
I.............
~
OVP
~
.
"t; 10'
~I
~
,02 ' -_ _' - _ - - ' -_ _----'-_ _---'-_ _...J
!
10
SUf>PL y VOLTAGE (V)
~
10
.:20
SUPPLY VOLTAGE (VI
1-312
10'
103
,'"
FREQUENCY (Hzl
XR·5533/5533A
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
INPUT NOISE CURRENT DENSITY
BROADBAND INPUT
NOISE VOLTAGE
TOTAL INPUT NOISE DENSITY
",
10'
10'
TVPICAL VALUES
~
1
~
'0
~
"'-
s
~
~
i
.04
!
103
>
~
~
TVP
~
10
/
10Hl
V ,,'"
/
10'
~
•0'
102
10'
./. ~I'
10
THERMAL NOISE OF
.....
r-""
SOURCE RESISTANCE
10'
.0'
103
10'
f---+--+-+--+--+---1
10'
L._.L_...1-_..L_...J.._-'-_....I
10'
.04
10
102
103
104
FREQUENCY IH,)
105
106
RSIHI
RSIII!
TYPICAL APPLICATION
PREAMPLIFIER-RIAA/NAB
COMPENSATION
60
+15V
.
0.22
.N?uT
Fh--~
OUTPUT
..-
GO
....;~
50
~~
.
ACTUAL RESPONse
'~
z
~
,
70
3D
50
"
40
'\
z
~
-'I\..
,.
BODE PLOT
,,-~
30
,.
'\.
o
10'
103
10'
.04
10'
10'
FREQUENCV IH,)
·SELECT TO PROVIDE SPECIFIED TRANSDUCER LOADING
OUTPUT NOISE;;:' 0.8 mV frill (WITH INPUT SHORTEDI
COMP
1I2ofXR·5533
1-313
103
,04
,05
BODE PLOT OF NAB EQUALIZATION AND THE
BODE PLOT OF RIAA EQUALIZATION AND THE
RESPONSE REALIZED IN AN ACTUAL CIRCUIT
RESPONSE REALIZED IN THE ACTUAL CIRCUIT USING
THE )CR·5533
EQUIVALENT SCHEMATIC DIAGRAM
BALANCE
~ f-
FREQUENCY (H,)
USING THE XR·5533.
ALL RESISTOR VALUES ARE IN OHMS.
,02
ACTUAL
/FiESPONSE
COMP
Vee
(SUBSTRATE)
XR·5534/5534A
Low-Noise Operational Amplifier
GENERAL DESCRIPTIDN
FUNCTIONAL BLOCK DIAGRAM
The XR-5534 is a high performance low-noise operational amplifier especially designed for application in
high quality and professional audio equipment. It offers
five-fold improvement in noise characteristics, output
drive capability and full-power bandwidth over conventional741-type op amps. The op amp is internally compensated for gain equal to, or higher than, three. The
frequency response can be optimzed with an external
compensation capacitor for various applications such
as operating in unity gain mode or driving capacitive
loads.
XR·5534
The XR-5534A is a specially-screened version of the
XR-5534, with guaranteed noise specifications.
FEATURES
Direct Replacement for Signetics NE/SE 5534
Wide Small-Signal Bandwidth: 10 MHz
High-Current Drive Capability
(10V rms into 6000 at Vs = ± 18V)
High Slew Rate: 13 VII'S
Wide Power-Bandwidth: 200 kHz typo
Very Low Input Noise: 4 nV/..JHz typo
ORDERING INFORMATION
APPLICATIONS
Part Number
Package
Operating Temperature
High Quality Audio Amplification
Telephone Channel Amplifiers
Servo Control Systems
Low-Level Signal Detection
Active Filter Design
5534AM
5534M
5534ACN
5534CN
5534ACP
5534CP
Ceramic
Ceramic
Ceramic
Ceramic
Plastic
Plastic
-55°C to +125°C
-55°C to +125°C
O°C to + 70°C
O°C to +70°C
O°C to +70°C
O°C to + 70°C
ABSOLUTE MAXIMUM RATINGS
SYSTEM DESCRIPTION
Power Supply
±22 V
Input Common-Mode Voltage
+VCC to -VEE
Differential Input Voltage (Note 1)
±0.5 V
Power Dissipation (Package Limitation)
Ceramic Package
385 mW
Plastic Package
300mW
2.5 mW/oC
Derate Above +24°C
Short Circuit Duration (Note 2)
Indefinite
Storage Temperature
- 60°C to + 150°C
The XR-5534 and XR-5534A are monolithic operational
amplifiers featuring low noise and a very large gain
bandwidth product. The devices offer low output resistance and can drive 10 Vrms into 6000. Input noise is
100% tested on the XR-5534A, and is typically only 4
nV/~z. The small signal bandwidth is 10 MHz and
slew rate exce,eds 13 VII'S.
Note t: Diodes protect the inputs against over-voltage. Therefore, unless current-limiting resistors are used, large
currents will flow if the differential input voltage exceeds 0.6V. Maximum current should be limited to ±
Reverse parallel diodes provide input pr-otection; maximum differential input voltage is 0.7 V. Balance pins are
provided to zero offset voltage. The device is internally
compensated for gains ~3 and provides external compensation pins for unity gain applications. Supply voltage may range from ± 3V to ± 20V.
to mA.
Note 2: Output may be shorted to ground at Vs = ± t5V, TA =
25°C. Temperature and/or supply voltages must be limited to ensure dissipation rating is not exceeded.
1-314
XR·5534/5534A
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°e, Vee = VEE = 15V, unless otherwise specified.
XR-5534M/5534AM
XR-5534AC/XR-5534C
PARAMETERS
DC CHARACTERISTICS
MIN
TYP
MAX
0.5
MIN
TYP
MAX
UNITS
2
3
0.5
4
5
mV
mV
10
200
500
20
300
400
nA
nA
400
800
1500
500
1500
2000
nA
nA
Input Offset Voltage
Input Offset Current
Input Bias Current
VOS
lOS
CONDITIONS
T = 25°C
~ = Full Range
T = 25°C
~ = Full Range
IB
Large Signal Voltage
Gain
TA = 25°C
TA = Full Range
"vOL
50
25
Supply Current
100
4
25
15
6.5
V/mV
V/mV
100
4
8
mA
Output Swing
±12
±15
Output Short Circuit
Current
Input Resistance
SYMBOL
±13
±16
±12
±15
38
±13
±16
V
V
38
mA
ICC
VOUT
ISC
50
100
30
100
kll
RIN
Common·Mode
Range
±12
±13
±12
±13
V
ViCM
Common·Mode
Rejection
80
100
70
100
dB
CMRR
p.VN
PSRR
Power Supply
Rejection
10
50
10
100
RL '" 60011,
VO= ±10V
T = 25°C
~ = Full Range
RL = Open
RL'" 60011
VCC = VEE = 15V
VCC = VEE = 18V
(Note 2)
AC CHARACTERISTICS
Transient Response
Voltage Follower
Rise Time
20
20
nSec
tr
RL",6001l,
Cc = 22 pF
Overshoot
20
20
%
to
CL = 100 pF
6
2.2
6
2.2
6
2.2
V/mV
V/mV
I = 10 kHz
Cc = 0
CC=22pF
Unity·Gain
Bandwidth
10
10
MHz
BW
Slew Rate
13
6
13
6
Vlp.sec
Vlp.sec
Power Bandwidth
95
95
kHz
200
200
kHz
ACGain
Cc = 22 pF,
CL = 100 pF
Cc = 0
Cc = 22pF
Ip
VOUT = ±10V,
Cc = 22 pF
Cc = 0
NOISE CHARACTERISTICS
PARAMETERS
MIN
XR-5534A
TYP
MAX
XR-5534
MIN
TYP
MAX
UNITS
Input Noise Voltage
5.5
3.5
7
4.5
7
4
nV/-IHz
nV/.JHz
2.5
0.6
pN.JFiZ
pN.JFiZ
Input Noise Current
CONDITIONS
en
10 = 30 Hz
10 = 1 kHz
in
1.5
0.4
Broadband Noise
Figure
SYMBOL
0.9
dB
1-315
10 = 30 Hz
10 = 1 kHz
FN
RS = 5 kll
I = 10 Hz to
20 kHz
XR·5534/5534A
TEST CIRCUITS
FREQUENCY COMPENSATION AND OFFSET
VOLTAGE ADJUSTMENT CIRCUIT
CLOSED LOOP FREQUENCY RESPONSE
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN LOOP FREQUENCY RESPONSE
CLOSE!) LOOP FREQUENCY
RESPONSE
SLEW-RATE AS A FUNCTION OF
COMPENSATION CAPACITANCE
\IS"
I
Hi\!
=61.
\--
\:
..
i\
to
102
1(!4
\0:1
191j
10'
.
f--
"'
-- f- -
m
r---. ~ \--
.----_.-
rT~"~l·-L_
.. - f-c._ f--
Co ."."
\-- f--
".'1J=[-J
la1
rAf:OUEHCV IH,I
F1UQUUtCV IHrl
LARGE-SIGNAL FREQUENCY
RESPONSE
OUTPUT SHORT-CIRCUIT
CURRENT
INPUT BIAS CURnENT
~.-'--
VS··'SV
---- f-- ----+-1-1
1- -.. -- -
30
-
f-- f - l·- i -
,03
1011
loS
10&
~.t"V
1-
-- -- I--
--- f-- --
t'.... ...
~
.. f-- -- --j:--t--+-l--+-l
1--1--
-- f--
---- 1--+--1-- -
~
102
1Y"CAl VAL un
4~-r
tc
---+--+---+--I---f--j
2S
107
50
11
tOO
125
f"EQUENCYI",)
INPUT COMMON MODE
VOLTAGE RANGE
r---,---,--'"T--,--.-
SUPPLY CURRENT
INPUT NOISE VOLTAGE DENSITY
,
10
T",",Ca.L VAlUlS
10-0
TV>
/"
~ I-""'"
-
I'-.....
m
10
10'
.
~
10
SUPPLY VOLTAGE IVI
!
10
IUPPlYVOLTAG£\Y1
1-316
,"
,.'
.
,
'''EOUENCV IH,I
XR·5534/5534A
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
INPUT NOISE CURRENT DENSITY
",
.
TYPICAL VALUES
L
b--.
/ V
........... TV'"
V
17" ~
",
",
",
,,.
BROADBAND INPUT
NOISE VOLTAGE
TOTAL. INPUT NOISE DENSITY
",
-.-
," ,-,.--,.--,.--.,---.,----,
10HI
IkHI
~THERMAL NOISE OF
SOURCE RlSISTANCE
," f--f--f--f--f--f--;
," L_.L_.L_.L_.L_.L-.I
10
10l
10l
104
lOS
102
108
10l
RSIHI
H'.
105
101
RSI:1I
TYPICAL APPLICATION
PREAMPLIFIER-RIAA/NAB
COMPE NSA1"1 ON
",
16K
000]
'---'VV'.--i~-
",
",
,,.
",
FRfDUfNt't Ilhl
'UL[CT
to PROYID!
OUTPuT NDIU
08
SPECIFllo TAANSOUCEfl LOADINO
BODE PLOT OF RIAA EOUAlll.ATLDN ANO THE
onOE PLOY OF NAB laVALIZAllON MID TN!:
",V.",.I~IlH
AESPCNsr REALIZED IN AN ACTUAL eIReu"
USINOTHE XR_55J4.
R!:SPONSE REALIZED IN THE ActUAL CIRCun USING
''''''Ul SHOll ItO)
ALL RUISfOR VJI,LUU ARE IN O!1MS
BALANCE
BALANCE/COMP
CaMP.
(SUBSTRATE'1
EQUIVALENT SCHEMATIC DIAGRAM
1-317
Voltage Regulators
XR·1468/1568
Dual·Polarity Tracking Voltage Regulator
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-1468/1S68 is a dual polarity tracking voltage
regulator, internally trimmed for symmetrical positive
and negative lSV outputs. Current output capability is
100 mA, and may be increased by adding external pass
transistors. The device is intended for local "on-card"
regulation, which eliminates the distribution problems
associated with single point regulation.
GND
BALANCE
ADJUST
CDMP'
The XR-1468CN and XR-1S68N are guaranteed over
the O·C to 70·C commercial temperature range. The
XR-1S68M is rated over the full military temperature
range of - SS·C to + 12S·C.
SENSE'
vo'
FEATURES
Internally Set for ± lSV Outputs
± 100 mA Peak Output Current
Output Voltages Balanced Within i % (XR-1S68)
0.06% Line and Load Regulation
Low Stand-By Current
Output Externally Adjustable from ± 8 to ± 20 Volts
Externally Adjustable Current Limiting
Remote Sensing
N.C.
N.C.
VCC
VEE
ORDERING INFORMATION
APPLICATIONS
Part NumbBr
Main Regulation in Small Instruments
On-Card Regulation in Analog and Digital Systems
Point-of-Load Precision Regulation
XR-1S68M -SS·C to + 12S·C ± lS0 mV maxCeramic
XR-1S68N
O·C to + 70·C ± lS0 mV maxCeramic
XR-1468CN O·C to + 70·C ±300 mV max Ceramic
ABSOLUTE MAXIMUM RATINGS
SYSTEM DESCRIPTION
Power Supply
±30 Volts
Minimum Short-Circuit Resistance
4.0 Ohms
±100 mA
Load Current, Peak
Power Dissipation
1.0 Watt
Ceramic (N) Package
6.7 mW/·C
Derate Above + 2S·C
Operating Temperature
XR-1S68M
-SS·C to + 12S·C
XR-1S68/XR-1468C
O·C to + 70·C
Storage Temperature
- 6S·C to + lS0·C
The XR-1468/1S68 is a dual polarity tracking voltage
regulator combining two separate regulators with a
common reference element in a single monolithic circuit, thus providing a very close balance between the
positive and negative output voltages. Outputs are internally set to ± lS Volts but can be externally adjusted
between ± 8.0 to ± 20 Volts with a single control. The
circuit features ± 100 mA output current, with externally adjustable current limiting, and provision for remote voltage sensing.
1-318
Temperature
Output Offset
Package
XR·1468/1568
ELECTRICAL CHARACTERISTICS
Test conditions: (VCC
=
= IL -
+ 20V, VEE = - 20V, Cl = C2 = 1500 pF, C3
= +25°C unless otherwise noted.)
= 0, TC
= C4 = 1,0 !,F, RSC + = RSC - = 4.00. IL +
XR-1468C
PARAMETERS
Output Voltage
XR-1568
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
14.5
15
15.5
14.8
15
15.2
Vdc
Input Voltage
-
-
30
-
-
30
Vdc
Input-Output Voltage Differential
2.0
-
-
2.0
-
-
Vdc
Output Voltage Balance
-
Line Regulation Voltage
(Vin = 18V to 30V)
(Td to TH)tt
-
±50
-
±300
-
10
20
-
±50
± 150
mV
mV
-
10
20
-
-
mV
Load Regulation Voltage
(lL = 0 to 50 mA, TJ
(TA = TL to TH)
= constant)
-
-
10
30
-
-
10
30
8.0
-
20
8.0
-
20
Vdc
-
75
-
-
75
-
dB
Output Voltage Temperature Stability
(TL to TH)
-
0.3
1.0
-
0.3
1.0
Short-Circuit Limit
(RSC = 10 ohms)
-
60
-
-
60
-
Output Noise Voltage
(BW = 10 Hz - 10 kHz)
-
100
-
-
100
-
Positive Standby Current
(Vin = +30V)
-
2.4
4.0
-
2.4
4.0
Negative Standby Current
(Vin = -30V)
-
1.0
3.0
-
1.0
3.0
Long-Term Stability
-
0.2
-
-
0.2
-
Output Voltage Range
Ripple Rejection (f
tTL
=
120 Hz)
%
mA
!,V(rms)
mA
= O°C for XR-1468C/1568
=
-
ttTH
=
-55°C for XR-1568M
+70°CforXR-1468C/1568
+ 125°C for XR-1568M
mA
%/KHr
TJ = Junction Temp.
TC = Case Temp.
INPUT '+I,o---<,!..f;'vc;c---:V;;EJE.!'o.---oINPUT H
1
INPUT (.)
...
Vo-I-"°=O----,
·sc·
'oc'
•
•
-
'00'
c,
C2
1500pF
.... pI'
Vee
VEE
v.'
v.-
SENSE
SENSE
H
(.)
f" V-tj
GND
·,5Vdc
I.h'
a
-:
1.0",
C4
a
'NPU TI-I
-
"
• '00'
eOMPEN~t jOMPENH
lSOOpF
.V.
Balldj
..
, '
1500pF
.
.
-Vo
-15Vdc
Cl MdC2shouki t.1ocI1Id IS cia. to thtdeva IS possible. A O.1/AF Clflmic CIIpKitor
,...y bt rlquiNd on the input lines If thI device II located an Ipprec:ilbll distance from
Ctl.01l'
C31.QIoI'
1M tKtlfilr fill. apIICitors.
C3 ... C,'''''' be incran.f lQ improveloacl tr",lient response and 10 reduc. the output
no" '10...... At low ttmpetMur. apll'Mion. it !NY be necessary to bypnl C4 with.
0.1 p.F CIeNmic: djsc ClplCltor.
+,5Vdc
Figure 1. Basic 50 rnA Regulator
Figure 2. Voltage Adiust and Balance Adjust Circuit
.V.
1-319
0:-
-vo
-,5Vdc
XR·494
Pulse·Width Modulating Regulator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-494 is a monolithic pulse width modulating regulator designed to contain all the blocks necessary for
a switching regulator. Included in a 16 pin dual in-line
package is a voltage reference, oscillator, control logic,
error amplifiers, and dual uncommitted outputs. This
device can be used for switching regulators of either
polarity, polarity converters, transformer coupled DC to
DC converters, transformerless voltage doublers, and
many other power control applications. The XR-494M is
fully specified for operation over the full military temperature range from -55°C to + 125°C, while the XR494CN and XR-494CP are designed for commercial applications over O°C to + 70°C.
NON
INV
1
'NV
INPUT
'NV
INPUT
DEAD
TIME
CONTROL
4
I---lr--;'
OUTPUT
CONTROL
FEATURES
Complete PWM Power Control Circuitry
Uncommitted Outputs for 200-mA Sink or Source
Output Control Selects Single-Ended
or Push-Pull Operation
Internal Circuitry Prohibits Double Pulse
at Either Output
Variable Dead Time Provides Control Over Total
Range
Internal Regulator Provides a Stable
5-V Reference Supply
Circuit Architecture Provides Easy Synchronization
ORDERING INFORMATION
Amplifier Input Voltages
Output Current
Supply Voltage
Collector Output Voltage
Power Dissipation
Total, at or below 25°C
Ceramic Package
Derate above + 28°C
Plastic· Package
Derate above +41°C
Operating Temperature
- 55°C to + 125°C
O°C to +70°C
O°C to + 70°C
All functions required to construct a pulse-width modulating regulator are incorporated on a single monolithic
chip in the XR-494. The device is primarily designed for
power supply control and contains a on-Chip five volt
regulator, two error amplifiers, an adjustable oscillator,
dead-time control comparator, a pulse-steering flip-flop,
and output control circuits. Either common emitter or
emitter follower output capability is provided by the uncommitted output transistors. Single ended or push-pull
output operation may be selected through the output
control function. The XR-494 architecture prohibits the
possibility or either output being pulsed twice during
push-pull operation. The internal amplifiers'S circuitry
allows for a common-mode input voltage range of - 0.3
volt to Vee - 2 volts. The dead time control comparator provides approximately 5% dead time unless the
dead time control is externally driven. The on-chip
oscillator may be used to drive the common XR-494
circuitry and provide a sawtooth input for associated
control circuitry in synchronous multiple-rail power
supplies, or may be bypassed by terminating RT (Pin 6)
to the reference output and providing a sawtooth input
to CT (Pin 5).
Pulse-Width Modulated Power Control Systems
Switching Regulators
=
Package
Ceramic
Ceramic
Plastic
SYSTEM DESCRIPTION
APPLICATIONS
ABSOLUTE MAXIMUM RATINGS, TA
Part Number
XR-494M
XR-494CN
XR-494CP
25°C
VCC = ± 0.3 Volts
250 mA
41 Volts
41 Volts
1000 mW
8.2 mW/oC
9.2 mW/oC
1-320
XR·494
RECOMMENDED OPERATING CONDITIONS
XR-494CN
XR-494CP
XR-494M
PARAMETERS
Supply voltage, Vce
Amplifier input voltages, VI
MIN
MAX
MIN
MAX
UNIT
7
40
7
40
V
-0.3
VCC -2
-0.3
VCC -2
V
Collector output voltage, Vo
Collector output current
(each transistor)
40
40
V
200
200
mA
Current into feedback terminal
0.3
Timing capacitor, CT
Timing resistor, RT
Oscillator frequency
Operating free-air temperature, TA
0.3
mA
0.47
10,000
0.47
10,000
nF
1.8
500
1.8
500
kD
1
300
1
300
kHz
-55
125
0
75
°c
SWITCHING CHARACTERISTICS TA = 25°C
.-
TVp'1
MAX.
UNIT
Output Voltage Rise Time
Output Voltage Fall Time
100
25
200
100
ns
ns
Common·Emitter Configuration,
See Figure 1
Output Voltage Rise Time
Output Voltage Fall Time
100
40
200
100
ns
ns
Emitter·Foliower Configuration,
See Figure 2
PARAMETER
MIN.
TEST CONDITIONS
1. All typical values except for temperature coefficients are at TA = 25°C.
,EA~H
J'"
1
r- - -
I
I
OUTPUT
: ""'""'-C;".',
,I
,
'
~_
:
:
,
,
IL _________
c,
"p'
'(Y""""'
.JI~"
2 ..
,'.O'UOe6PRoa.... o
.'GCA'ACITANCE)
Figure 1. Common-Emitter Configuration
Figure 2. Emitter-Follower Configuration
ERROR AMPLIFIER
UNDER TEST
FUNCTION TABLE
VREF
0----1
Figure 3. Error-Amplifier Characteristics
1-321
INPUTS
OUTPUT CONTROL
OUTPUT FUNCTION
Grounded
AtVref
AtVref
At Vref
Single-ended or parallel output
Normal push-pull operation
PWM Output at 01
PWM Output at 02
XR·494
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C, unless otherwise specified.
PARAMETERS
Reference Section
Output Voltage (V ref)
Input Regulation
Output Regulation
Output Voltage Change
with Temperature
Short Circuit Output l
Current
Oscillator Section
Frequency
Standard Deviation 2
of Frequency
Frequency Change with
Voltage
Frequency Change with
Temperature
Dead Time Control Section
(See Figure 2)
Input Bias Current (Pin 4)
Maximum Duty Cycle
(each output)
Input Threshold Voltage
(Pin 4)
Error-Amplifier Sections
Input Offset Voltage
Input Offset Current
Input Bias Current
Common-Mode Input
Voltage Range
Open Loop Voltage
Amplification
Unity Gain Bandwidth
Common-Mode Rejection
Ratio
Output Sink Current
(Pin 3)
Output Source Current
(Pin 3)
Output Section
Collector Off-State Current
Emitter Off-State Current
XR-494
TYP
MAX
UNIT
4.75
5.0
2.0
1
0.2
5.25
25.0
15
1
V
mV
mV
%
10 = lmA
VCC = 7V to 40V
10 = 1 to 10mA
~TA = Min to Max
10
35
50
mA
Vref
10
10
kHz
%
Cr = 0.01
0.1
%
"F, RT = 12k!}
Vee, CT, Rr. TA:
all values constant
VCC = 7V to 40V
%
CT
MIN
2
Average Supply Current
=0
= 0.D1 ,.F, RT = 12k!},
= Min to Max
~TA
= 0 to 5.25V
= 0 (Pin 4)
-2
-10
"A
%
VI
VI
3
3.3
V
Zero Duty Cycle, Maximum
Duty Cycle = OV Min
2
25
0.2
10
250
1
mV
nA
"A
V
Vo (Pin
Vo (Pin
Vo (Pin
VCC =
45
3) = 2.5V
3) = 2.5V
3) = 2.5V
7V to 40V
-0.3 to
Vee -2
70
95
dB
~VO
=
65
800
80
kHz
dB
VCC
0.3
0.7
mA
= 40V
= -15mVto
-2
Collector-Emitter Saturation
Voltage Common-Emitter
Emitter-Follower
Output Control Input
Current
PWM Comparator Section
Input Threshold Voltage
(Pin 3)
Input Sink Current (Pin 3)
Total Device
Standby Supply Current
CONDITIONS
0.3
= 3V, Vo
0.5V to 3.5V
mA
VID
-5V, V
(Pin 3) = 0.7V
VID = 15mV to 5V, V
(Pin 3) = 3.5V
2
100
-100
"A
"A
VCE = 40V, Vee = 40V
Vee = Vc = 40V, VE = 0,
XR-494M Max = -150,.A
1.1
1.3
V
1.5
2.5
3.5
V
mA
VE = 0, IC = 200mA,
XR-494M Max = 1.5V
Vc = 15V, IE = -200mA
VI = Vref
4
4.5
V
0.7
6
9
10
15
7.5
= 0.7V
mA
V (Pin 3)
mA
mA
Vee = 15V, Pin 6 at Vref
Vee = 40V, All Other Inputs
and Outputs Open
V = 2V (Pin 4)
mA
1-322
Zero Duty Cycle
XR·494
OUTPUT
CONTROL
(SEE FUNCTION
TABLE)
r-=::J:IC>-----l..------- CI
......- - - - - - 0 1
Rr----C:::-:-:::-::1
r--+_~~)_i=~~----~---------C'
CT--r--;==:1
DEAD -O.~'V~:::::[:>~----~~C:>-_~~~~~~~____~
. . . ------E2
nME--t
CONTROL
ERROR
AMPLIFIERS
NONINVERnNQ INPUT ------r.~
INYERnNQ INPUT
------1;""
NOMNYERnNG INPUT
-------1....
-------1"
INYEFmNG INPUT
FEEDBACK _ _ _ _ _ _ _ _ _--.J
EQUIVALENT SCHEMATIC DIAGRAM
.-.."r----- Vee
VOLTACE
Vee. UV
ATCt
...-...,,_ _ _ -Vee
YOUAG!
ATC2
¥CLUOI!
AT C,
DUD-nut:
CONTROl.
INPUT
.V,
I
I
nED.ACIt
c~~~:
I
O.7Y;.I------+,-i::::=~~
MAl
D-.. t--t
.,VOLTACE waVEFORMS
., TEST CUICUIT
Figure 4. Dead-Time and Feedback Control
DSCILLATOfifREQUENCVa....
FAEQUENCYVARIATIOft' .a
TIMINGRESlSU.NCE
AMPLIFIEIIVOLTAO! AMPLIfiCATION
!'REGUINCY
~
Vee-UY
I--~
~
··
I
... -
III --
"J",
~:o:::-c-
t--
'\
t\.
"
r---..
FRED.
VAA'
·
··
",,;,~L..J.-!;llll!!:,~;-LL.:!:"illli,,~~..l..-1..J.llllll
RT-T ....NQRE$lSTANCE·1I
1 Frequency variation I. the change In osclUator lrequency that
occura over the full temperatura range.
'\
1\
'\
1\
"
Figure 6. Amplifier Voltage Amplification vs Frequency
Figure 5. Oscillator Frequency and Frequency Variation' vs
Timing Resistance
1-323
XR·495
Pulse-Width Modulating Regulator
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-495 is a monolithic pulse width modulating regulator designed to contain all blocks necessary for a
switching regulator. Included in the 16 pin dual in-line
packages is a voltage reference, oscillator, control
logic, error amplifiers, and dual uncommitted outputs.
This device can be used for switching regulators of either polarity, polarity converters, transformer coupled
DC to DC converters, transformerless voltage doublers, and many other power control applications. A
39V zener diode allows operation with supply voltages
exceeding 40V. The XR-495M is fully specified for operation over the full military temperature range from 55°C to + 125°C, while the XR-495CN and XR-495CP
are designed for commercial applications over O°C to
+ 70°C.
NON
'NY
INPUT
'NY
'NY
INPUT
INPUT
FEED
REF
OUT
BACK
DEAD
TIME
4
CONTROl.
OUTPUT
CONTROL
STEERING
INPUT
FEATURES
Complete PWM Power Control Circuitry
Uncommitted Outputs for 200-mA Sink or Source
Output Control Selects Single-Ended
or Push-Pull Operation
Internal Circuitry Prohibits Double Pulse
at Either Output
Variable Dead Time Provides Control Over Total Range
Internal Regulator Provides a Stable
5-V Reference Supply
Circuit Architecture Provides Easy Synchronization
On-Chip 39-V Zener
External Control of Output Steering
SYSTEM DESCRIPTION
All functions required to construct a pulse-width modulating regulator are incorporated on a single monolithic
chip in the XR-495. The device is primarily designed for
power supply control and contains a on-chip five volt
regulator, two error amplifiers, an adjustable oscillator,
dead-time control comparator, a pulse-steering flip-flop,
and output control circuits. Either common emitter or
emitter follower output capability is provided by the uncommitted output transistors. Single ended or push-pull
output operation may be selected through the output
control function. The XR-495 architecture prohibits the
possibility or either output being pulsed twice during
push-pull operation. The internal amplifier's circuitry allows for a common-mode input voltage range of - 0.3
volt to VCC - 2 volts. The dead time control comparator provides approximately 5% dead time unless the
dead time control is externally driven. The on-Chip oscillator may be used to drive the common XR-495 circuitry and provide a sawtooth input for associated control circuitry in synchronous multiple-rail power supplies, or may be bypassed by terminating RT (Pin 6) to
the reference output and providing a sawtooth input to
CT (Pin 5).
APPLICATIONS
Pulse-Width Modulated Power Control Systems
SWitching Regulators
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-495M
XR-495CN
XR-495CP
Ceramic
Ceramic
Plastic
- 55°C to + 125°C
O°C to + 70°C
O°C to + 70°C
ABSOLUTE MAXIMUM RATINGS, TA = 25°C
Amplifier Input Voltages
Output Current
Supply Voltage
Collector Output Voltage
Power Dissipation
Total, at or below 25°C
Ceramic Package
Derate above +28°C
Plastic Package
Derate above + 41°C
VCC = + 0.3 Volts
250 mA
41 Volts
41 Volts
1000 mW
The XR-495 also contains an on-chip 39 volt zener diode for high voltage applications where VCC is greater
than 40 volts, and an output steering control that overrides the internal control of the pulse steering flip-flop.
1-324
XR·495
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C. unless specified otherwise.
XR-495
PARAMETERS
Reference Section
Output Voltage (V ref)
Input Regulation
Output Regulation
Output Voltage Change
with Temperature
Short Circuit Output 1 Current
TYP
MAX
UNIT
4.75
5.0
2.0
1
0.2
5.25
25.0
15
1
V
mV
mV
%
10 = lmA
VCC = 7V to 40V
10 = 1 to 10mA
10
35
50
mA
Vref = 0
kHz
%
Vee. CT, RT. TA: all values constant
Oscillator Section
Frequency
Standard Deviation 2 of
Frequency
Frequency Change with Voltage
Frequency Change with
Temperature
10
10
0.1
2
Dead Time Control Section
(See Figure 2)
Input Bias Current (Pin 4)
Maximum Duty Cycle
(each output)
Input Threshold Voltage (Pin 4)
Error-Amplifier Secllons
Input Offset Voltage
Input Offset Current
Input Bias Current
Common-Mode Input Voltage
Range
Open Loop Voltage
Amplification
Unity Gain Bandwidth
Common· Mode Rejection Ratio
Output Sink Current (Pin 3)
Output Source Current (Pin 3)
CONDITIONS
MIN
CT = 0.01 1'. RT = 12kll
%
%
VCC = 7V to 40V
VI = 0 to 5.25V
VI = 0 (Pin 4)
CT = O.Olp.F. At = 12kll,
ATA = Min to Max
-2
-10
p.A
%
3
3.3
V
2
25
0.2
10
250
1
mV
45
ATA = Min to Max
Zero Duty Cycle. Maximum Duty
Cycle = OV Min
V
Vo (Pin 3) = 2.5V
Vo (Pin 3) = 2.5V
Vo (Pin 3) = 2.5V
VCC = 7V to 40V
95
dB
AVO = 3V. Vo = 0.5V to 3.5V
800
80
0.7
kHz
dB
mA
mA
-0.3 to
nA
p.A
VCC -2
70
65
0.3
-2
Output Secllon
Collector Off-State Current
Emitter Off-State Current
2
100
-100
Vee = 40V
VID = -15mVto -5V. V (Pin 3) = 0.7V
VID = 15mV to 5V, V (Pin 3) = 3.5V
p.A
p.A
VCE = 40V. VCC = 40V
Vee = Vc = 40V. VE = O.
XR-494M Max = - 150p.A
Collector-Emitter Saturation
Voltage Common-Emitter
Emitter-Follower
Output Control Input Current
PWM Comparator Secllon
Input Threshold Voltage (Pin 3)
Input Sink Current (Pin 3)
0.3
Total Device
Standby Supply Current
1.1
1.3
V
1.5
2.5
3.5
mA
4
0.7
4.5
6
9
10
15
VE = O. IC = 200mA.
XR-494M Max = 1.5V
Vc = 15V, IE = -200mA
VI = Vref
V
V
Zero Duty Cycle
mA
V (Pin 3) = O.7V
mA
mA
VCC = 15V, Pin 6 at Vref
VCC = 40V, All Other Inputs
mA
V = 2V (Pin 4)
and Outputs Open
Average Supply Current
7.5
1. Duration of the short circuit should not exceed one second.
2. Standard deviation is a measure of the statistical distribution about the mean as derived from the formula
SWITCHING CHARACTERISTICS
PARAMETER
f1
=.
TA = 25°C
MIN
Typ1
MAX.
UNIT
TEST CONDITIONS
Output Voltage Rise Time
Output Voltage Fall Time
100
25
200
100
ns
ns
Common-Emitter Configuration.
See Figure 1
Output Voltage Rise Time
Output Voltage Fall Time
100
40
200
100
ns
ns
Emitter-Follower Configuration.
See Figure 2
..
1. All tYPical values except for temperature coeffiCients are at TA = 25°C.
1-325
XR·495
RECOMMENDED OPERATING CONDITIONS
XR·495CN
XR·495CP
XR·495M
MAX
MIN
PARAMETERS
Supply voltage, VCC
MIN
MAX
7
40
7
40
V
UNIT
-0.3
VCC-2
-0.3
VCC-2
V
Collector output voltage, Vo
40
40
V
Collector output current (each transistor)
200
200
mA
Current into feedback terminal
0.3
0.3
mA
nF'
Amplifier input voltages, VI
Timing capacitor, CT
Timing resistor, RT
Oscillator frequency
Operating free-air temperature, TA
r-- --------,
(!ACHOUTf'UT
CIIIICUIT)
0.47
10,000
0.47
10,000
1.8
500
1.8
500
kll
1
300
1
300
kHz
-55
125
0
75
·C
,---------,
....
:
lug~~~UT
I
I
r-~I----~
I
I
I
I
I
I
I
I
IL _________ -.lI
ow
I
I
CL"I'>pF
(ItiCLUO!.SPR08EAMD
JIG CAPACITANCE)
I
....'w
CL"npF
__________ .JI
flNCLUDES PROBE AND
JlGCAPACITANCI:)
Al TEST CIRCUIT
AITESTCIPlCUIT
I
,.-H
B) OUTPUT VOLTAGE WAVEfORM
III OUT"": VOLTAGE WAVEFORM
Figure 2. Emmer·Follower Configuration
Figure 1. Common·Emmer Configuration
.----·-ycc
VOLTAGE
Vee. 'IV
ATe.
........ ,...._ _ _ VCC
H -....O
OUT1'UT I
H--=-o OutPUT •
VOLTAGE
ATtl
VOLTAGE
ATCT
(OPEN)
(OPE",
DUD-TIllE
CONTROL
INPUT
IVI
I
I
FEEDBAC.
I
'------+--+:-...,.-r.M::":A"::'.
G.1v ..
Duty
CYCLE
....•
o..h
I) VOLTAGE WAVEFORMS
A, TEST CIRCUIT
Figure 3. Dead·Tlme and Feedback Control
1-326
XRII495
OUTPUT
CONTROL
(SEE FUNCTION
TABLE)
>-----te==
RT
t--------L..J~>_______C===
C2
, r
.2
------1=::-::::1
CT--~--t
C'
E1
____-J
DEAD
.OU"'V~====~~------~:r~~_~~~~~~-r~~~~~
TIME~lr------...,
CONTROL
EnROR
I
AMPLIFIERS
I
Vee
I
NONINYERTINCi INPUT
-----...p....
INVERTING INPUT
------b;
I
------P......
I
HONINVERTING INPUT
I
I------~~~
I
I t--~~--T---~-------GND
INVERTING INPUT - - - - - - - \ ; ; " ,
IL Vz______ .JI
FEEDBACK - - - - - - - - - -
EQUIVALENT SCHEMATIC DIAGRAM
ERROR AMPLIFIER
FUNCTION TABLE
UNDER TEST
INPUTS
VREF
0----;
Figure 4. Error Amplifier Characteristics
OUTPUT
CONTROL
STEERING
INPUT
Grounded
Open
At Vref
At Vref
AtVref
Open
VIO.4V
OUTPUT FUNCTION
Single·ended or parallel
output
Normal push·pull operation
PWM Output at 01
PWM Output at 02
OSCILLATOR FREQUENCY and
FREQUENCY VARIATION'
In
TIMING RESISTANCE
.
..... PLlFIER VOLTAGE AMPLIFICATION
Vee·ISV
TA .2S'C
FREQUENCY
I----
Vee
Lnv
::0 :~:.c-
"\
I\.
'\
I'\.
'\
\.
\..
" •.L.-.L.LI:-L'.u:."'=----l.--l.="..LU7:"'~"'--l.....l.;-=:..LU~
"-
RT-TlMII.a RESISTANCE-II
1 Frequency variation Is the change In oscillator frequency thai
occurs over the lull temperature rangs.
0
\..
I-FAEQUENCy-tb:
Figure 5. Oscillator Frequency and Frequency Variation' vs
Timing Resistance
Figure 6. Amplifier Voltage Ampliffcation vs Frequency
1·327
XR·15/25/3524
Pulse-Width Modulating Regulator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-1524 family of monolithic integrated circuits
contain all the control circuitry for a regulating power
supply inverter or switching regulator. Included in a 16pin dual-in-line package is the voltage reference, erroramplifier, oscillator, pulse width modulator, pulse steering flip-flop, dual alternating output switches and current limiting and shut-down circuitry. This device can be
used for switching regulators of either polarity, transformer coupled DC to DC converters, transformerless
voltage doublers and polarity converters, as well as
other power control applications. The XR-1524 is specified for operation over the full military temperature
range of - 55°C to + 125°C, while the XR-2524 and XR3524 are designed for commercial applications of O°C
to + 70°C.
FEATURES
Direct Replacement for SG-1524/2524/3524
Complete PWM power control circuitry
Single ended or push-pull outputs
Line and load regulation of 0.2%
1 % maximum temperature variation
Total supply current less than 10 mA
Operation beyond 100 kHz
ORDERING INFORMATION
APPLICATIONS
Switching Regulators
Pulse-width Modulated Power Control Systems
Package
Operating Temperature
Ceramic
Ceramic
Plastic
Ceramic
Plastic
-55°C to +125°C
O°C to +70°C
GOC to +70°C
O°C to +70°C
O°C to +70°C
SYSTEM DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
Input Voltage
Output Current (each output)
Reference Output Current
Oscillator Charging Current
Power Dissipation
Ceramic Package
Derate above +25°C
Plastic Package
Derate above + 25°C
Operating Temperature Range
XR-1524
XR-2524/XR-3524
Storage Temperature Range
Part Number
XR-1524M
XR-2524N
XR-2524P
XR-3524N
XR-3524P
The XR-1524/2524/3524 pulse width modulating regulator is a complete monolithic switching regulator. An internal 5V reference, capable of supplying up to 50 mA
to external loads, provides an on board operating standard. The oscillator frequency and duty cycle are adjusted by an external RC network. Regulation is controlled by an error amplifier which, combined with the
sense amplifier, also allows current limiting and remote
shutdown functions. The outputs of the XR-1524/25241
3524 are two identical NPN transistors with both emitters and collectors uncommitted. Each output transistor has antisaturation circuitry for fast response and local current limiting set at 100 mAo
40V
100 mA
50 mA
5 mA
1000 mW
8 mW/oC
625 mW/oC
5 mW/oc
- 55°C to + 125°C
O°C to + 70°C
- 65°C to + 150°C
1-328
XR·15/25/3524
ELECTRICAL SPECIFICATIONS
Test Conditions: TA = - 55°C to + 125°C for the XR-1524 and O°C to + 70°C for the XR-2524 and XR-3524, VIN =
20V, and f = 20 kHz, unless specified otherwise.
XR·15241
XR-2524
PARAMETERS
XR·3524
MIN TYP MAX MIN TYP MAX UNITS
CONDITIONS
REFERENCE SECTION
Output Voltage
Line Regulation
Load Regulation
Ripple Rejection
Short Circuit Current Limit
Temperature Stability
Long Term Stability
4.8
5.0
10
20
66
100
0.3
20
5.2
20
50
4.6
1
5.0
10
20
66
100
0.3
20
5.4
30
50
1
V
mV
mV
dB
mA
%
mV/khr
VIN = 8 to 40 Volts
IL = 0 to 20 mA
f = 120 Hz, TA = 25°C
VREF = 0, TA = 25°C
Over Operating Temperature Range
TA = 25°C
KHz
%
%
%
V
/LS
CT = .001 /LF, RT = 2 K!l
RT and CT constant
VIN = 8 to 40 Volts, TA = 25°C
Over Operating Temperature Range
Pin3, TA = 25°C
CT = .01 mfd, TA = 25°C
mV
/LA
dB
V
dB
MHz
V
VCM - 2.5 Volts
VCM = 2.5 Volts
OSCILLATOR SECTION
Maximum Frequency
Initial Accuracy
Voltage Stability
Temperature Stability
Output Amplitude
Output Pulse Width
300
5
300
5
1
2
1
2
3.5
0.5
3.5
0.5
ERROR AMPLIFIED SECTION
Input Offset Voltage
Input Bias Current
Open Loop Voltage Gain
Common Mode Voltage
Common Mode Rejection Ratio
Small Signal Bandwidth
Output Voltage
72
1.8
0.5
2
80
5
10
3.4
60
1.8
70
3
0.5
2
2
80
10
10
3.4
70
3
3.8
0.5
45
0
3.8
TA
TA
AV
TA
= 25°C
= 25°C
= 0 dB, TA = 25°C
= 25°C
COMPARATOR SECTION
Duty Cycle
Input Threshold
Input Threshold
Input Bias Current
0
1
3.5
1
45
%
V
V
~
220
mV
1
3.5
1
CURRENT LIMITING SECTION
Sense Voltage
Sense Voltage Temp. Coef.
Common Mode Voltage
190 200
0.2
-1
210
+1
180 200
0.2
-1
% Each Output On
Zero Duty Cycle
Max. Duty Cycle
Pin 9 = 2V with Error Amplifier
Set for Max. Out, TA = 25°C
mV/oC
+1
V
OUTPUT SECTION (Each Output)
Max. Collector-Emitter Voltage
Collector Leakage Current
Saturation Voltage
Emitter Output Voltage
Rise Time
Fall Time
TOTAL STANOBY CURRENT
40
17
40
0.1
1
18
0.2
0.1
50
8
10
2
17
0.1
1
18
0.2
0.1
50
8
10
(Excluding oscillator charging
current, error and current limit
dividers, and with outputs
open)
1-329
2
V
~
V
V
/LS
/LS
VCE = 40V
IC = 50 mA
VIN = 20V
RC = 2 K!l, TA
RC = 2 K!l, TA
mA
VIN
= 40V
= 25°C
= 25°C
XR·15/25/3524
OPEN LOOP TEST CIRCUIT
2k
r-------------------------------------------------~
2k
lW
12I---4I-~~C)OUTPUTS
'--C~__I15
3
16
lW
131---~--O
XR-1524
11
14
6
8
CURREN
LIMIT
V ,N
8-40V
0.1
2k
DESCRIPTION OF CIRCUIT OPERATION
VOLTAGE REFERENCE SECTION
The internal voltage reference and regulator section
provides a 5·volt reference output at pin 16. This volt·
age also serves as a regulated voltage source for the
internal timing and control circuitry. This regulator may
be bypassed for operation from a fixed 5·volt supply by
connecting pins 15 and 16 together to the input voltage.
In this configuration, the maximum input voltage is 6.0
volts.
J
'L T0 1.0A
DEPENDING
ONCHQlCE
FOR 01
This reference regulator may be used as a 5·volt source
for other circuitry. It will provide up to 50 mA of current
itself and can easily be expanded to higher currents
with an external PNP as shown in Figure 2.
Figure 2. Using the Internal Regulator as 5V Power Supply
for External Circuitry
I~~m~---"'-;,INTERNAL
+5VTOAll
L.:
CIRCUITRY
GROUND
~
(SUBSTRATE) 8
1k
,0)-JVVI_-r
SHUT DOWN
Figure 1. Detailed System Block Diagram of XR-1524
1·330
XR·15/25/3524
OSCILLATOR SECTION
10
The oscillator section in the XR-1524 uses an external
resistor (RT) to establish a constant charging current into an external capacitor (CT). While this uses more current than a series connected RC, it provides a linear
ramp voltage on the capacitor which is also used as a
reference for the comparator. The charging current is
equal to 3.6V + RT and should be kept within the range
of approximately 30 p.A to 2 mA, i.e., 1.SK < RT <
100K.
v
V
2
V
0
-- ~
o. s
The oscillator period is apprqximately T = RrCT where
T is in microseconds when RT = ohms and CT =
microfarads.
o. 3
.001
The use of Figure 3 allows the selectiori of RT and CT
for a wide range of operating frequencies. Note that for
series regulator applications, the two outputs can be
connected in parallel for an effective 0 - 90% duty cycle and the frequency of the oscillator is the frequency
of the output. For push-pull applications, the outputs
are separated and the flip-flop divides the frequency
such that each output's duty cycle is 0 - 45% and the
overall frequency is 1/2 that of the oscillator.
100
~
.005
.01
.02
.os
.002
TIMING CAPACITOR VALue IC r ' - MICROFARADS
Figure 4, Output Stage Dead Time as a Function of the
Timing Capacitor Value
If it is desired to synchronize the XR-1524 to an external
clock, a pulse of =- + 3 volts may be applied to the oscillator output terminal with RrCT set slightly greater
than the clock period. The same considerations of
pulse width apply. The impedance to ground at this
point is approximately 2K ohms.
I-+-+--+---'I---I...---I..-......,.+--".+:..-I
If two or more XR-1524 circuits must be synchronized
together, one must be deSignated as master with its
RrCT set for the correct period. The slaves should each
have an RrCT set for approximately 10% longer period
than the master with the added requirement that CT
(slave) = 1/2 CT (master). Then connecting pin 3 on all
units together will insure that the master output pulse which occurs first and has a wider pulse width - will reset the slave units.
~!jQI-+-+--+--bI'41C-;,.«~~T+:.~
9
~
ERROR AMPLIFIER SECTION
10
20
50
100
200
500
1 ms
The error amplifier is a simple differential-input, transconductance amplifier. The output is the compensation
terminal, pin 9, which is a high-impedance node (RL =5 MO). The gain is
2m.
OSCILLATOR PERIOD - MICROSECONDS
Figure 3, Oscillator Period as a Function of RT and CT
The range of values for CT also has limits as the discharge time of CT determines the pulse width of the oscillator output pulse. This pulse is used (among other
things) as a blanking pulse to both outputs to insure that
there is no possibility of having both outputs on simultaneously during transitions. This output dead time relationship is shown in Figure 4. A pulse width below approximately 0.5 microseconds may allow false triggering of one output by removing the blanking pulse prior
to the flip-flop's reaching a stable state. If small values
of CT must be used, the pulse width may still be expanded by adding a shunt capacitance (=- 100 pF) to
ground at the oscillator output. (Note: Although the oscillator output is a convenient oscilloscope sync input,
the cable and input capacitance may increase the
blanking pulse width slightly_) Obviously, the upper limit
to the pulse width is determined by the maximum duty
cycle acceptable. Practical values of CT fall between
.001 and 0.1 p.F.
AV
SiC RL
= gm RL = - - - = - _002 RL
2kT
and can easily be reduced from a nominal of 10,000 by
an external shunt resistance from pin 9 to ground, as
shown in Figure 5.
In addition to DC gain control, the compensation terminal is also the place for AC phase compensation. The
frequency response curves of Figure 5 show the uncompensated amplifier with a single pole at approximately 200 Hz and a unity gain cross-over at 5 MHz.
Typically, most output filter deSigns will introduce one or
more additional poles at a significantly lower frequency.
Therefore, the best stabilizing network is a series R-C
combination between pin 9 and ground which introduces a zero to cancel one of the output filter poles. A
good starting point is 50 KO plus .001 p.F.
1-331
XR·15/25/3524
",
....--NV--
'0
R
1 M~!
RL
Jook!!
RL
IOU
RL
JOk!!
60
~
,
0
Z
;;
"
"~
40
~
k!~
"...... .....
"-
""'"
~
",
•
1K
!OK
FREQUENCY. HERTZ
100K
Sk
ONO--'--'-
NEGATIVE"
OUTPUT
VOL TAGES
GNO
tAl. n.1
2.SV
VO'-R-, -
"-
1M
2
",
,,
R L .. R~sistant'1! from Pin 9 to ground
100
"
2
'0
10
VRE~~
1
0
>
POSIT1VE
OUTPUT
VOLTAGES
RL~
.!!!..!.!.
R, +R.
-2.5tn
Figure 6. Error Amplifier Blasing CircuHs. (Note: Change
in Input Connections for Opposite Polarity
Outputs)
"
age to get 25% duty cycle with the error amplifier signaling maximum duty cycle.
10M
In addition to constant current limiting, pins 4 and 5
may also be used in transformer-coupled circuits to
sense primary current and shorten an output pulse,
should transformer saturation occur. (Refer to Figure
15.) Another application is to ground pin 5 and use pin 4
as an additional shutdown terminal, i.e., the output will
be off with pin 4 open and on when it is grounded. Finally, foldback current limiting can be provided with the
network of Figure 8. This circuit can reduce the short-
Figure 5. Error Amplilier Frequency Response as a Function
01 External Resistor, RL, at Pin 9
One final point on the compensation terminal is that
this is also a convenient place to insert any programming signal which is to override the error amplifier. Internal shutdown and current limit circuits are connected here, but any other circuit which can sink 200 p.A
can pull this point to ground, thus shutting off both outputs.
While feedback is normally applied around the entire
regulator, the error amplifier can be used with conventional operational amplifier feedback and is stable in either the inverting or non·inverting mode. Regardless of
the connections, however, input common-mode limits
must be observed or output signal inversions may
result. For conventional regulator applications, the 5volt reference voltage must be divided down as shown
in Figure 6. The error amplifier may also be used in
fixed duty cycle applications by using the unit gain configuration shown in the open loop test circuit.
Figure 7. Current Limiting Circuitry 01 the XR·1524
CURRENT LIMITING CONTROLS
circuit current (lSC) to approximately one· third the maximum available output current (lMAlO.
The current limiting circuitry of the XR-1524 is shown in
Figure 7.
OUTPUT CIRCUITS
The outputs of the XR-1524 are two identical NPN transistors with both collectors and emitters uncommitted.
Each output transistor has antisaturation circuitry for
fast response, and current limiting set for a maximum
output current 6f approximately 100 mAo The availability
of both collectors and emitters allows maximum versatility to enable driving either NPN or PNP external transistors.
By matching the base-emitter voltages of 01 and 02,
and assuming negligible voltage drop across R1,
Threshold = VBE (01)+ 11 R2 - VBE (02) = 11 R2
:.200 mV
Although this circuit provides a relatively small threshold with a negligible temperature coefficient, there are
some limitations to its use, the most important of which
is the ± 1 volt common mode range which requires
sensing in the ground line. Another factor to consider is
that the frequency compensation provided by R1C1
and 01 provides a roll-off pole at approximately 300
Hertz.
Ite.:!l.!!
R.
WMr.
V'M·200mV
Since the gain of this circuit is relatively low, there is a
transition region as the current limit amplifier takes
over pulse width control from the error amplifier. For
testing purposes, threshold is defined as the input volt-
Figure 8. Foldback Current Limiting Can Be Used to Reduce
Power Dissipation Under Shorted Output Conditions
1·332
XR·15/25/3524
In considering the application of the XR-1524 to voltage
regulator circuitry, there are a multitude of output configurations possible. In general, however, they fall into
three basic classifications:
1. Capacitor-diode coupled voltage multipliers
2. Inductor-capacitor single-ended circuits
3. Transformer-coupled circuits
Examples of each category are shown in Figures 9, 10
and 11. In each case, the switches indicated can be either the output transistors in the XR-1524 or added external transistors according to the load current requirements.
(a) Push-Pull
(b) Flyback
Figure 11. Push-Pull and Flyback Connections for
Transformer-Coupled Outputs
DEADBAND CONTROL
The XR-1524 pulse width modulating regulator provides
two outputs which alternate in turning on for push-pull
inverter applications. The internal oscillator sends a
momentary blanking pulse to both outputs at the end of
each period to provide a deadband so that there cannot
be a condition when both outputs are on at the same
time. The amount of deadband is determined by the
width of the blanking pulse appearing on pin 3 and can
be controlled by anyone of the four techniques described below:
Figure 9. Capacitor-Diode Coupled Voltage Multiplier Output
Stages. (Note: Diode 01 is Necessary to
Prevent Reverse Emitter-Base Breakdown of
Transistor Switch S/J
.V'N-rrm
~
SA"Sa
I
~I
I
I
Method 1: For 0.2 to 2.0 microseconds, the deadband
is controlled by the timing capacitor, Cr, on
pin 7. The relationship between CT and
deadband is shown in Figure 4. Of course,
since CT also helps determine the operating
frequency, the range of control is somewhat
limited.
·V o
V 1N '
Vo
Method 2: For 0.5 to 5.0 microseconds, the blanking
pulse may be extended by adding a small
capacitor from pin 3 to ground. The value of
the capacitor must be less than 1000 pF or
triggering will become unreliable.
Vo
Method 3: For longer and more well-controlled blanking
pulses, a simple one-shot latch similar to the
circuit shown in Figure 12 should be used.
Figure 10. Single-ended Inductor Circuits Where the Two
Outputs of the XR-1524 are Connected in Parallel
1-333
XR·15/25/3524
APPLICATIONS INFORMATION
POLARITY CONVERTING REGULATOR
10k
The XR-1524 pulse width modulating regulator can be
interconnected as shown in Figure 14. The component
values shown in the figure are chosen to generate a -5
volt regulated supply voltage from a + 15 volt input.
This circuit is useful for an output current of up to 20
mA with no additional boost transistors required. Since
the output transistors are current limited, no additional
protection is necessary. Also, the lack of an inductor allows the circuit to be stabilized with only the output capacitor.
10k
FLYBACK CONVERTER
Figure 12. Recommended External Circuitry for Long
Duration Blanking Pulse Generation (Method 3 o,f
Deadband Control. Note: For 5 ,.sec blanking,
choose CB = 200 pF, RB = 10 KO)
Figure 15 shows the application of XR-1524 in a lowcurrent DC-DC converter, using the flyback converter
principle (see Figure 11 b). The particular values given
in the figure are chosen to generate ± 15 volts at 20
mA from a + 5 volt regulated line. The reference generator in the XR-1524 is unused. The reference is provided by the input voltage. Current limiting in a flyback
converter is difficult and is accomplished here by sensing current in the primary line and resetting a soft-start
circuit.
When this circuit is triggered by the oscilla·
tor output pulse, it will latch for a period determined by CSRS providing a well-defined
deadband.
Another use for this circuit is as a buffer
when several other circuits are to be synchronized to one master oscillator. This oneshot latch will provide an adequate signal to
insure that all the slave circuits are completely reset before allowing the next timing
period to begin.
SINGLE ENDED REGULATOR
The XR-1524 operates as an efficient single-ended
pulse width modulating Fegulator, using the circuit connection shown in Figure 16. In this configuration, the
two output transistors of the circuit are connected in
parallel by shorting pins (12, 13) and (11, 14) together,
respectively, to provide for effective 0 - 90% duty-cycle
modulation. The use of an output inductance requires
an R-C phase compensation on pin 9, as shown in the
figure.
Note that with this circuit, the blanking pulse
holds off the oscillator so its width must be
subtracted from the overall period when selecting RT and CT
Method 4: Another way of providing greater deadband
is just to limit the maximum pulse width.
This can be done by using a clamp to limit
the output voltage from the error amplifier. A
simple way of achieving this clamp is with
the circuit shown in Figure 13.
This circuit will limit the error amplifier's voltage range since its current source output
will only supply 200 pA. Additionally, this circuit will not affect the operating frequency.
VREF
.'5V
••
16 l-------...
20,..,
Gild
®I----I~)li--~~~~
-s.
2.
IN916
Compo
IN9tS
20mA
,.,
lNg,S
5k
8
SO"I
GND
Figure 13. Using a Clamp Diode to Control Deadband
(Method 4 of Daadband Control)
Figure 14. Circuit Connection for Polarity Converting
Regulator (Vln = + 15V, Vout = -5V)
1·334
GND
XR·15/25/3524
PUSH-PULL CONVERTER
The circuit of Figure 17 shows the use of XR-1524 in a
transformer-coupled DC-DC converter with push-pull
outputs (see Figure 11 a)_ Note that the oscillator must
be set at twice the desired output frequency as the XR1524's internal flip-flop divides the frequency by 2 as it
switches the P.WM_ signal from one output to the other.
Current limiting is done in the primary. This causes the
pulse/width to be reduced automatically if the transformer saturation occurs.
"
SK
..-"'iI----tCT
cLt.-------+--t
c,-I--------+
osc.
SH. ON.
GND
COMP
001
..,
RETURN
GNO
.,
IN9!6
,,,. ,.,
"
"
"
., "
f
'ON
. .
,.,
,
c.
'
V AH
C.
"r
'.
Cr
SH.ON.
COMP
0.0
I
GROUND
1M
'e II~
GO
20T
so
':? .,
1~9'6
~
~
1500/01'·
'"
CORf'
"f . ,.r·""
·38'
IN9"
SOD
UROXCU8
!IV
E--t--1ro"
SVTGQ_5
Ct'
c,-
0 - - - OSC
0---
""
Figure 16_ Conventional Single-Ended Regulator Connection
(Vin = + 28V, Vo = + 5V, lout s 1 Amp)
,
2213P- A2 so
'"
RUUAN
Figure 15. A Low-Current DC-DC Converter Using Flyback
Principle (Vout = ± 15V, Vin = + 5V, IL s 20
Figure 17 _ A High-Current DC-DC Converter with Push-Pull
Outputs (Vin = + 28V, Vo = + 5V, 10 s 5A)
rnA)
1-335
XR·1525A12525A/3525A
XR·1527 A/2527 A13527 A
Pulse-Width Modulating Regulators
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-1525A11527A is a series of monolithic integrated circuits that contain all of the control circuitry
necessary for a pulse-width modulating regulator. Included in the 16-Pin dual-in-line package is a voltage
reference, an error amplifier, a pulse-width modulator,
an oscillator, under-voltage lockout, soft-start circuitry,
and output drivers.
INV
INPUT
NON-INV
INPUT
SYNC
The XR-1525A12525A13525A series features NOR logic,
giving a LOW output for an OFF state. The XR-1527A1
2525A13527A series features OR logic, giving a HIGH
output for an OFF state.
OSCILLATOR
OUTPUT
CT
RT
FEATURES
DISCHARGE
BV to 35V Operation
5.1V Reference Trimmed to ± 1 %
100 Hz to 500 kHz Oscillator Range
Separate Oscillator Sync Terminal
Adjustable Deadtime Control
Internal Soft-Start
Input Under-voltage Lockout
Latching PWM to Prevent Double Pulsing
Dual Source/Sink Output Drivers
Capable of Over 200 mA
Power-FET Drive Capability
SOFT-START
ORDERING INFORMATION
APPLICATIONS
Power Control Systems
Switching Regulators
Industrial Controls
Part Number
Package
Operating Temperature
XR-1525A127M
XR-2525A127 AN
XR-2525A127AP
XR-3525A127CN
XR-3525A127CP
Ceramic
Ceramic
Plastic
Ceramic
Plastic
- 55°C to + 125°C
-25°C to +B5°C
-25°C to +B5°C
O°C to + 70°C
O°C to + 70°C
SYSTEM DESCRIPTION
The on-chip 5.1-volt reference is trimmed to ± 1 % initial accuracy, and the common-mode input range of the
error amplifier is extended to include the reference
voltage. Deadtime is adjustable with a single external
resistor. A sync input to the oscillator allows multiple
units to be slaved together, or a single unit to be synchronized to an external clock. A positive-going signal
applied to the shutdoown pin provides instantaneous
turnoff of the outputs. The under-voltage lockout circuitry keeps the output drivers off, and the soft-start capacitor discharged, for an input voltage below the required value. The latch on the PWM comparator insures the outputs to be active only once per oscillator
period, thereby eliminating any double pulsing. The
latch is reset with each clock pulse.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (+ VIN)
+40V
Collector Supply Voltage (VC)
+40V
Logic Inputs
- 0.3V to 5.5V
Analog Inputs
- 0.3V to + VIN
Output Current, Source or Sink
500 mA
Reference Output Current
50 mA
Oscillator Charging Current
5mA
Power DiSSipation
Ceramic Package
1000 mW
B.O mW/oC
Derate above TA = +25°C
Plastic Package
625 mW
Derate above TA = +25°C
5.0 mW/oC
+ 150°C
Operating Junction Temperature (TJ)
Storage Temperature Range
-65°C to + 150°C
The output drivers are totem-pole designs capable of
sinking and sourcing over 200 mAo
1-336
XR·1527 A/2527 A/3527 A
XR·1525A/2525A/3525A
ELECTRICAL CHARACTERISTICS
Test Conditions: VIN
=
+20V, TJ
= Full operating temperature range, unless otherwise specified.
XR·1525A12525A
XR·1527A/2527A
PARAMETERS
XR·3525A
XR·3527A
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
5.05
5.10
10
20
20
5.00
5.10
10
20
20
80
5.15
20
50
50
5.20
100
80
5.20
20
50
50
5.25
100
V
mV
mV
mV
V
mA
40
20
200
50
40
20
200
50
p.V rms
mV/kHR
±2
±3
±0.3
±6
±6
±1
100
±2
±3
±1
±6
±6
±2
100
2.0
3.5
0.5
2.0
1.0
2.2
2.0
3.5
0.5
2.0
1.0
2.2
%
%
%
Hz
kHz
mA
V
p'sec
V
mA
2
1
10
10
1
CONDITIONS
VOLTAGE REFERENCE SECTION
Output Voltage
Line Regulation
Load Regulation
Temperature Stability (2)
Total Output Variation (2)
Output Short Circuit
Current
Output Noise Voltage (2)
Long Term Stability (2)
5.00
4.95
TJ = 25'C
VIN = BV to 35V
IL = 0 to 20 mA
TJ = Full Operating Range
Line, Load and Temperature
TJ = 25'C, Vrel = OV
TJ
TJ
= 25'C, 10 Hz :s 1 :s
= 125'C
10 kHz
OSCILLATOR SECTION (Note 3)
Initial Accuracy (2,3)
Temperature Stability (2)
Input Voltage Stability (2,3)
Minimum Frequency
Maximum Frequency
Current Mirror
Clock Amplitude (2,3)
Clock Pulse Width (2,3)
Sync Threshold
Sync Input Current
400
1.7
3.0
0.3
1.2
ERROR AMPLIFIER SECTION (VCM
Input Offset Voltage
Input Bias Current
Input Offset Current
DC Open-Loop Gain
Gain Bandwidth Product (2)
Output Low Voltage
Output High Voltage
Common· Mode Rejection
Ratio
Supply Voltage Rejection
Ratio
1.0
2.8
2.5
TJ
= 25'C, RD = 00
Sync Voltage
= 3.5V
= 5.1V)
0.5
1
60
1
1.0
2.8
2.5
400
1.7
3.0
0.3
1.2
TJ = 25'C,1 = 40 kHz
TJ = Full Operating Range
VIN = 8V to 35V
RT = 150 kO, CT = 0.1 p.F
RT = 2 kO, CT = 1 nF
IRT = 2 mA
3.8
60
75
2
0.2
5.6
75
50
60
5.0
10
1
60
1
mV
p.A
p.A
dB
MHz
V
V
dB
3.8
60
75
2
0.2
5.6
75
50
60
45
0.6
49
0.9
3.3
0.05
3.6
1.0
%
%
V
V
p.A
50
0.4
0.4
80
0.6
1.0
p.A
V
mA
0.2
1.0
19
18
7
0.4
2.0
0.5
0.5
dB
RL'" 10 MO
TJ = 25'C
VCM
VIN
= 1.5V to 5.2V
= BV to 35V
PULSE·WIDTH MODULATING COMPARATOR
Minimum Duty Cycle
Maximum Duty Cycle
Input Threshold (3)
Input Threshold (3)
Input Bias Current (2)
0
0
45
0.6
49
0.9
3.3
0.05
3.6
1.0
50
0.4
0.4
80
0.6
1.0
Zero Duty Cycle
Maximum Duty Cycle
SOFT· START SECTION
Soft-Start Current
Soft-Start Voltage
Shutdown Input Current
25
OUTPUT DRIVERS (Each Output) Vc
Output Low Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
Under-voltage Lockout
Collector Leakage (4)
Rise Time (2)
Fall Time (2)
Shutdown Delay (2)
18
17
6
25
Vshutdown
Vshutdown
Vshutdown
= OV
= 2V
= 2.5V
= 20V
0.2
1.0
19
18
7
0.4
2.0
100
50
0.2
8
200
600
300
0.5
14
20
18
17
6
100
50
0.2
B
200
600
300
0.5
V
V
V
V
V
p.A
nsec
nsec
p'sec
14
20
mA
Isink = 20 mA
Isink = 100 mA
Isource = 20 mA
Isource = 100 mA
Vcomp and Vss = High
Vc = 35V
TJ = 25'C, CL = 1 nF
TJ = 25'C, CL = 1 nF
VSD = 3V, Cs = 0, TJ = 25'C
TOTAL STANDBY CURRENT
Supply Current
VIN
= 35V
Note 2: These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
Note 3: Tested at 1 = 40 kHz (RT = 3.6 kO, CT = 0.01 p.F, RD = 00).
Note 4: Applies to XR-1525A12525A13525A only, due to polarity 01 output pulses.
1·337
XR·1525AJ2525AJ3525A
XR·1527 AJ2527 AJ3527 A
PRINCIPLES OF OPERATION
Error Amplifier
The different control blocks within the XR-1525N1527A
function as follows:
The error amplifier of the XR-1525N1527A is a differential input transconductance amplifier. Its commonmode range covers the reference voltage. Its open-loop
gain, typically 75 dB, can be reduced by a load resistor
on Pin 9. To ensure proper operation, the output load
should be limited to 50 kO or greater. An equivalent circuit schematic of the error amplifier is shown in Figure 9.
Voltage Reference Section
The internal voltage reference circuit of the XR-1525N
1527A is based on the well-known "band-gap" reference, with a nominal output voltage of 5.1 volts, internally trimmed to ± 1 % accuracy. It is short circuit protected and is capable of providing up to 20 mA of
reference current. A simplified circuit schematic is
shown in Figure 7.
Soft-Start Circuitry
The soft-start function is provided to achieve controlled
turn-on of the pulse-width modulator. When power is
applied to the device, the external capacitor, Csoftstart, on Pin 8 is charged by a 50 !tA constant current
source. The ramp voltage appearing on this capacitor
is fed into the pulse-width modulator, which gradually
increases its output duty cycle from zero to the prescribed value. When the shutdown terminal is raised to
a positive value, an internal transistor turns ON, and
discharges the capacitor, CS, causing the PWM to turn
OFF. When the shutdown terminal is open or pulled low,
the transistor turns OFF, and Cs begins charging as before. The turn-on time (time required to charge Cs to
+ 2.7 volts) can be approximated as:
Oscillator Section
The sawtooth oscillator derives its frequency from an
external timing resistor/capacitor pair. The timing resistor, fir. determines the charging current into the timing
capacitor, Cr- The magnitude of this current is approximately given by:
Vref - 2VBE
3.7V
AT
RT
where RT may range from 2 kO to 150 kO. In general,
temperature stability is maximized with lower values of
Rr- The current source charging CT creates a linear
ramp voltage which is compared to fixed thresholds
within. When the capacitor voltage reaches + 3.3 volts,
the oscillator output (Pin 4) goes high, turning ON the
discharge transistor. The capacitor is discharged
through the deadtime resistor, RO. When the voltage on
CT falls to + 1.0 volt, the oscillator output goes low, the
discharge transistor is turned OFF, and the capacitor is
charged through the constant current source as another cycle starts. With large values of RO (5000, maximum), deadtime is increased. The actual operating frequency is thus a function of the charge and discharge
times. Figure 2 shows how charge time is related to RT
and CT, with RO = 00. Oeadtime is a function of RO
and Cr, and can vary between 0.5 to 7 "sec, with RO =
00, as shown in Figure 3. The equivalent circuit schematic of the oscillator section is shown in Figure 8.
RECOMMENDED OPERATING CONDITIONS
A unit can be synchronized to an external source by selecting its free-running oscillator period to be 10%
longer than the period of the external source. A
positive-going pulse of at least 300 nsec wide should be
applied to the sync terminal for reliable triggering; however, it should not exceed the free-running pulse width
by more than 200 nsec. The amplifier of the pulse
should be kept between 2 and 5 volts. Multiple units
can be synchronized to each other by connecting all CT
pins, and oscillator output pins together; RT pins and
discharge pins on slave oscillators must be I.eft open.
Note 1: Range over which the device is functional
and parameter limits are guaranteed.
Collector Supply Voltage (VC)
+4.5V to +35V
Sink/Source Load Current
(Steady State)
o to 100 mA
Sink/Source Load Current (Peak)
o to 400 mA
Reference Load Current
o to 20 mA
Oscillator Frequency Range
100 Hz to 400 kHz
2 kO to 150 kO
Oscillator Timing Resistor
Oscillator Timing Capacitor
0.001 "F to 0.1 "F
Deadtime Resistor Range
o to 5000
TC (msec) = 54 Cs
where Cs is in "F.
Output Section
The output drivers of the XR-1525N1527A are totempole designs capable of sinking and sourcing 200 mAo
The low source impedance in the high or low states provides ideal interfacing with bipolar as well as FET
power transistors. Either push-pull or single-ended output configurations are possible with separate collector
supply terminals. The equivalent schematic of the output drivers is shown in Figure 10.
1-338
XR·1525AJ2525A/3525A
XR·1527 AJ2527 AJ3527 A
r
VREF
GROUND
I
I
~:
I
DISCHARGE
I
J
I
COMPENSATION
SOFT START
.J
EQUIVALENT SCHEMATIC DIAGRAM
P.W,M.
INPUT 19)
P.W.M.
OUTPUT
osc
200
~100
Ii
50
~
~
~
OUTPUT A III,
OUTPUT B ('41
J
u
u
L
~
20
RICT~
10
"~
"
";"
5
OUTPUT ""11)
OUTPUT B (141
1020
50100200 SOO,m.ZmISm,tOml
CHARGE TIME (" . .cl
1
n
L - ._ - - '
n
'--_--'
r
. . . . ._ - - '
Figure 1: Typical Waveforms-XR-1525A/1527A
Figure 2. Oscillator Charge Time vs RT and CT
1·339
~
XR·1525AJ2525AJ3525A
XR·1527 AJ2527 AJ3527 A
801-_ _~_~
-
400
0
60
II:
I
II:
0
iw
fl[>~I9
300
II:
,.
W
1=
200
0
cw
Cp
RZ
0
'DO
10
100
1K
10 K
100 K
1M
10 M
FREQUENCY (Hz)
DISCHARGE TIME (J.lsec:)
Figure 4. Error Amplifier Open-Loop Frequency Response.
Figure 3. Oscillator Discharge Time vs RO and CT
~
6
~
50
3
l
~
~
40
~
~
o 2
>
z
o
u
~ 30
::I
:
o
20
~ ,~----------
~
'0
.
O,O~':::::::,O;2=-,~03:-C,O'c4-:,O'":5-:,O':-7--:,''::0---,2~-'::,3-,4~,~5-:,7:--:" A
ERROR VOLTAGE (YOLTS)
OUTPUT CURRENT, SOURCE OR SINK (AMPS)
Figure 6. Output Duty Cycle vs Error Voltage
Figure 5. Output Saturation Characteristics
y"~-----------~--~----~-~
A,
A,
D,
.
..
'0
OutPUTS
A,
A,
AJ
FROM
SHUTDOWN
"
A,
Figure 7. Equivalent Schematic of Voltage Reference Section
1·340
FROM
O$C
XR·1525A/2525A13525A
XR·1527 A/2527A13527 A
~ .~----~------~
C1
,~--------------~--------+--;
-0
t---------------------¥>N.--G osc
-,
SYNC
3
-.
••
,-------..-------------1 7
DISC
0,
-,
·s
Figure 8. Equivalent Schematic of the Oscillator Section
Y,N 0-----..---------,
COMP
OUTPUT
t---c
Os
-IN
FIF
Figure 9. Equivalent Schematic of Error Amplifier Section
CSC
PWM
Q40MITTED
IN XR·'527A
Figure 1D. Equivalent Schematic of Output Drivers
1·341
XR·1525AJ2525AJ3525A
XR·1527 AJ2527 AJ3527 A
+VSUPPLY
O---t---,
+VSUPPLV
0------....,.---,
OPEN
r----1.. ~~O"TPUT
",
"2
'3
XR·1527A
XR·152SA
'2
'2
Figure 12. Single-Ended Output for XR-1527A
Figure 11. Single-Ended Output for XR-1525A
+VSUPPLY~----~---------------------,
+YSUPPLY
o---t---------,
T1'1(0
TlII (
TO OUTPUT
RECTIFIERS
AND FILTERS
OUTPUT
"ECTIFlE"S
"NDFILTERS
1----'
Figure 13. Push-Pull Outputs with XR-1525A
Figure 14. Power FET Push-Pull Outputs with XR-1525A
VelDel
UK
10k
OUTPUT
•
'IN MONITOR
SYNC
1 Kilit WATT)
o~;~ ()-----4~--------__1
l"F
1 Kllet WATT)
NORMALLY OPEN
OUTPUT
•
tOKn
Figure 15. Generalized Test Circuit
1·342
XR·15/25/3543
Power Supply Output Supervisory Circuit
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-1543/2543/3543 are monolithic integrated circuits that contain all the functions necessary to monitor
and control the output of a power supply system. Included in the 16-Pin dual-in-line package is a voltage
reference, an operational amplifier, voltage comparators, and a high-current SCR trigger circuit. The functions performed by this device include over-voltage
sensing, under-voltage sensing and current limiting,
with provisions for triggering an extemal SCR "crowbar."
seA TRIGGER
REMOTE
ACTIVA1E
GROUND
RESET
CL
OVER-VOLTAGE
OUTPUT
INDICATE
OVER-VOLTAGE
OFFSET\
COMPENSATION
OVER-VOLTAGE
CL NI
INPUT
DELAY
The internal voltage reference on the XR-1543 is guaranteed for an accuracy of ± 1 % to eliminate the need
for external potentiometers. The entire circuit may be
powered from either the output that is being monitored
or from a separate bias voltage.
INPUT
UNDER-VOLTAGE
CL INV
INPUT
INPUT
UNDEA-VOLTAGE
UNDER-VOLTAGE
DELAY
FEATURES
INDICATE
Over-Voltage Sensing Capability
Under-Voltage SenSing Capability
Current Limiting Capability
Reference Voltage Trimmed
± 1%
SCR "Crowbar" Drive
300 mA
Programmable Time Delays
Open Collector Outputs
and Remote Activation Capability
Total Standby current
Less than 10 mA
Part Number
Package
Operating Temperature
XR-1543M
XR-2543N
XR-3543N
XR-3543P
Ceramic
Ceramic
Ceramic
Plastic
- 55°C to + 125°C
-25°C to +85°C
O°C to +70°C
O°C to + 70°C
APPLICATlDNS
SYSTEM DESCRIPTION
DCIDC Converters
Switch Mode Power Supplies
Power Line Monitors
Linear Power Supplies
An output supervisory circuit, such as the XR-1543, is
used to control and monitor the performance of a
power supply. In many systems, it is crucial that the
supply voltage is always within some minimum and
maximum level, to guarantee proper performance, and
to prevent damage to the system. If the supply voltage
is out of tolerance, it is often desirable to shut down the
system or to have some form of indication to the operator or system controller. As well as protecting the system, the power supply sometimes needs to be protected under short circuit and current overload situations.
By providing an SCR "crowbar" on the output of a
power supply, it can be shut off under certain fault conditions as well.
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage, VIN
40V
Sense Inputs
VIN
SCR Trigger Current (Note 1)
300 mA
Indicator Output Voltage
40V
50 mA
Indicator Output Sink Current
Power Dissipation (Ceramic)
1000 mW
Derate Above TA = +25°C
8 mW/oC
Power Dissipation (Plastic)
625 mW
Derate Above TA = + 25°C
5 mW/oC
Operating Junction Temperature (TJ)
+ 150°C
Storage Temperature Range
- 65°C to + 150°C
The over-voltage sensing circuit (O.V.) can be used to
monitor the output of a power supply and provide triggering of an SCR, when the output goes above the prescribed voltage level. The under-voltage sensing circuit
(U.V.) can be used to monitor either the output of a
power supply or the input line voltage.
Note 1: At higher input voltages, a dissipation limiting
resistor, RG, is required.
1-343
XR·15/25/3543
ELECTRICAL CHARACTERISTICS
Tast Conditions: VIN = 10V, TJ = full operating temperature range, unless otherwise specified. Refer to Figure 9 for component
aesignation.
XR-1543/2543
PARAMETERS
MIN
Input Voltage Range
Input Voltage Range
Supply Current
4.5
4.7
XR-3543
TYP
MAX
MIN
4.5
4.7
7
40
40
10
TYP
MAX
UNIT
7
40
40
10
V
V
mA
2.52
2.55
5
10
25
2.45
2.40
2.55
2.60
5
10
25
V
V
mV
mV
mA
ppm/DC
400
100
200
12
13
0
0.4
2
0.4
400
mA
0.1
0.8
6
0.8
V
V
mA
V
mA
2
6
CONDITIONS
TJ = 25°C to max
TJ = min to max
TJ = 25°C, VIN = 40V
REFERENCE VOLTAGE SECTION (Pins 15 and 16)
Output Voltage
Output Voltage
Line Regulation
Load Regulation
Short Circuit Current
Temperature Stability
2.48
2.45
12
2.50
1
1
15
50
2.50
1
1
15
50
12
TJ = 25°C
TJ = min to max
VIN = 5 to 30V
Iref = 0 to 10 mA
Vref = OV
SCR TRIGGER SECTION (Pins 1, 2, and 3)
Peak Output Current
100
200
Peak Output Voltage
Output OFF Voltage
Remote Activate Current
Remote Activate Voltage
Reset Current
12
13
0
0.4
2
0.4
0.1
0.8
6
0.8
2
6
Reset Voltage
V
Output Current Slew Rate
400
400
mAlp.s
Propagation
(From Pin
Propagation
(From Pin
300
300
nsec
500
500
nsec
Delay Time
2)
Delay Time
6)
VIN = 5V, RG = Oil,
Vo = 0
VIN = 15V, 10 = 100 mA
VIN = 40V
Pin 2 = GND
Pin 2 = Open
Pin 2 = GND,
Pin 3 = GND
Pin 2 = GND,
Pin 3 = Open
TJ = 25°C, RL = 5011,
CD.= 0
TJ = 25°C, RL = 5011
CD = 0, Pin 2 = O.4V
TJ = 25°C, RL = 5011,
CD = 0, Pin 6 = 2.7V
COMPARATOR SECTIONS (Pins 4, 5, 6, 7, 8, and 9)
Input Threshold
(Input Voltage Rising
on Pin 6 and
Falling on Pin 7)
Input Hysteresis
Input Bias Current
Delay Saturation
Delay High Level
Delay Charging Current
Indicate Saturation Voltage
Indicate Leakage Current
Propagation Delay Time
2.45
2.50
2.40
200
Propagation Delay Time
25
0.3
0.2
6
250
0.2
0.01
400
2.55
2.40
2.60
2.35
1.0
0.5
7
300
0.5
1.0
2.50
25
0.3
0.2
6
250
0.2
0.01
400
200
10
2.60
V
2.65
V
mV
p.A
V
V
p.A
V
p.A
nsec
1.0
0.5
7
300
0.5
1.0
10
msec
TJ = min to max
TJ = 25°C
Sense input = OV
VD = OV
IL = 10 mA
Vout = 40V
Pin 6 = 2.7V
CD = 0
Pin 7 = 2.3V
CD = 1 p.F TJ = 25°C
CURRENT LIMIT AMPLIFIER SECTION (Pins 10, 11, 12, and 13)
Input Voltage Range
Input Bias Current
Input Offset Voltage
Input Offset Voltage
Common Mode
Rejection Ratio
Open Loop Gain
Output Saturation Voltage
Output Leakage Current
Small Signal Bandwidth
Propagation Delay Time
0
80
60
72
0.3
0
100
70
80
0.2
0.01
5
200
VIN-3V
1.0
10
120
0
70
60
72
0.5
1.0
0.3
0
100
70
80
0.2
0.01
5
200
1-344
VIN-3V
1.0
15
130
0.5
1.0
V
p.A
mV
mV
dB
dB
V
p.A
MHz
nsec
Pin 12 = Open, VCM = OV
Pin 12 = Open, VCM = OV
Pin 12 = 10 kll to GND
VIN = 15V, Os
VCM s 12V
VCM = OV, Pin 12 = Open
IL = 10 mA
Vout = 40V
TJ = 25°C, Av = 0 dB
TJ = 25°C,
Voverdrive = 100 mV
>'
..g
,
200
100
70
50
"~
0
>
...0
'"a:
Q
30
X
20
.lov
VIJ
RL ·2 KO
"
.. 11~
.y:
iE
V
10
;:;
11
-=+{?i
7
~
XR·15/25/3543
"" ,
"'
1~.
1-==1
lK
3K
2K
5K
7K
20K
50K 0.1101
0.3101
10 K
30 K
70 K
0.2101
0.5101
1101
lK
10K
lOOK
FREQUENCY (HERTZ)
1M
5M
AT. THRESHOLD SEnlNG RESISTOR (OIlMS)
Figure 1. Current Limiting Threshold (VTH) VS. Threshold
Setting Resistor (RT)
80
D
:!!.
RT =
00
RT
100Kn
RL = 2 KO
0
TJ = 25'C
uLL11
INPUT
INPUT
;6
70
~
RT =3OKO
!:i
;!
z
LL11
~
YIN -= lOY
1;1
!
".."
"...
.g
8...
...
Figure 2. Current Limiting Amplifier-Frequency Response
g
RT =10KO
80
53
..~~
0
50
0
0
Q
010
100
1K
10K
lOOK
FREQUENCY (HERTZ)
2.46
1M
Figure 3. Current Limiting Amplifier Gain VS. Threshold
Setting Resistor (RT
iii
Q
...a:
~
0
a:
1.0
z
DELAY = 2.5 C
ID
I
0.01
u
0.001
"'
f-RG"
I
~O
/"
Q
0.0001
0.001
0.01
0.1
1.0
DELAY TIME (MILLISECONDS)
2.54
RECOMMENDED SERIES GATE RESISTANCE. RG
FOR USE WITH HIGHER SUPPLY VOLTAGES
0.1
~
u
..."
..::l
2.50
2.50
2.52
SENSE INPUT VQLTAGE (VOLTS)
Figure 4. Over-Voltage and Under-Voltage Comparator
Hysteresis
~
u
"'
2.48
10
V
10
/'
15
V
20
/'
25
/'
30
~
35
010
VIN SUPPLY VOLTAGE (VOLTS)
Figure 6. SCR Trigger-Series Gate Resistance (RG) VS.
Input VoHage
Figure 5. Comparator Activation Delay vs. Capacitor Value
1-345
XR·15/25/3543
PRINCIPLES OF OPERATION
input common mode range extending from ground to
approximately 3 volts below the positive supply. With a
2 kO pull-up resistor, the open-loop voltage gain is 72
dB minimum with a unity gain bandwidth beyond 5
MHz. The operational amplifier may be used as a comparator or, if linear amplification is required, external
compensation may be added for stable performance
over a wide frequency range.
The internal control blocks of the XR-1543 operate as
follows:
Vonage Reference Section
The internal voltage reference circuit of the XR-1543 is
based on the well-known "band-gap reference" with a
nominal output voltage of 2.50 volts, intermilly trimmed
to give an accuracy of ± 1 % at 25°C. It is capable of
providing a stable output voltage over a wide input voltage range. Furthermore, its performance is guaranteed
for changes in line and load conditions. The accuracy
of the output voltage is guaranteed to ± 2% maximum
for the XR-1543/2543, and ± 4 % maximum for the XR3543, over the entire operating temperature range.
The input offset voltage of this amplifier is specified for
10 mV maximum; however, it may be programmed externally for thresholds up to 200 mV. By connecting a
resistor, Rr. from Pin 12 to ground, the input threshold
voltage can be varied. For most current sensing applications, the required threshold polarity calls for a positive voltage on the inverting input. Reducing the impedance on Pin 12 also lowers the overall voltage gain of
the amplifier, which makes this pin a convenient pOint
to apply frequency compensation. This can be accomplished by either connecting C1 to the output, or C2 to
ground as shown in Figure 8. The diode, D1, and the reSistor, RC, are used only if it is necessary to increase
the frequency response by operating the output at a
higher current and/or isolating the load from RC and
C1, when the amplifier is off.
The output of the reference circuit is capable of providing up to 10 rnA of current for use as a reference for external circuitry. The primary function of this circuit is to
provide a very accurate and stable reference input for
the under-voltage and over-voltage comparators, thereby enabling very precise monitoring of line and output
voltages without potentiometers.
Comparator Section
SC R Trigger Section
The under-voltage and over-voltage sensing comparators of the XR-1543 are identical except for the input polarities. Each section is made up of two comparators in
series whose inputs are referenced to 2.50 volts. The
delay terminal between the comparators requires an
external capacitor to ground for programmable time delays on the output.
The SCR trigger sectionof the XR-1543 is connected to
the output of the over-voltage comparator and is capable of handling 300 rnA. The circuit also provides for remote activation of the output as well as a reset terminal. When an over-voltage situation occurs, the output
of the sensing comparator goes low, turning "on" the
over-voltage indicate transistor. At the same time, the
comparator drives an npn Darlington pair which provides 300 rnA to activate an external SCR crowbar.
When an out-of-tolerance situation occurs, the first
comparator activates a current source which then
charges the external capacitor at a constant rate. This
ramp voltage is then compared to the reference voltage
by the second comparator which activates the output
indicating circuit. With no external capacitor, the overall
time delay from sense input to output is approximately
0.5 JLSec. The charging current for the capacitor, CD, is
approximately 250 p.A which results in the following relationship:
A remote activation circuit is included to allow the user
to activate the SCR crowbar in other than an overvoltage situation. When this terminal, Pin 2, is grounded, it forces the output of the comparator low which activates the output circuitry in the same manner as the
over-voltage comparator does.
Another function of this circuit is to provide the capability to latch the O.V. indicate and SCR trigger outputs
"on", after a fault is sensed. This is done by connecting
the remote activate terminal (Pin 2) to the O.V. indicating terminal (Pin 4). When an O.V_ condition occurs, Pin
2 is pulled low, which in turn holds the outputs in the
"on" condition until the reset terminal is externally
grounded, removing the latch and turning "off" the outputs. If the external connection is not made, the high
current output will be activated only as long as a fault
condition exists. When the fault condition disappears,
the outputs will be disabled. The thresholds for both remote activation and reset terminals are approximately
1.2 volts.
Time delay = 10 CD (msec)
where CD is in p.F.
The output npn transistors are capable of sinking 10
rnA with saturation voltage of less than 0.4 volts. The
outputs can be "wired OR'd" to provide a single output
indicator.
Current Sensing Amplifier
The operational amplifier used in the XR-1543 is a highgain, externally compensated amplifier with open collector outputs. The pnp input stage provides for a wide
1-346
XR·15/25/3543
EQUIVALENT SCHEMATIC DIAGRAM
VIN
16r-~~~~~~~~~--------lr~~--10~~--------~~~~------r-------r--------'--1.1 KIl 1.1 KIl"
U.Y.
INDICATE
U.V.
SENSE
VREF
SE~S~ L!r--------...J
SCR
TRIGGER
VIN
_______J '
INV.
N.J.
REMOTE
ACTIVATE
OFFSETICOMP
GROUND
2
RESET
(GROUND TO ACTIVATE)
~t-------
1
'::"
Figura 7. XR-1543 Block Diagram
1·347
_
IC"":""
O.V.
1NDICATE
XR·15/25/3543
APPLICATIONS INFORMATION
2. C1 is determined by the loop dynamics.
A typical application of the XR-1543 is to monitor a single power supply output voltage as shown in Figure 9.
In this circuit, both over- and under-voltage sensing and
current-limiting functions are performed. The circuit
shown is powered from an external bias capable of supplying 10 mA in addition to the activation current for the
SCR trigger. With Pin 2 tied to Pin 4, a latch has been
provided such that when an over-voltage situation occurs, the o.v. indicator and SCR trigger are activated
and held until the reset terminal is externally grounded.
3. Peak current to load,
In powering an SCR from supply voltages greater than 5
volts, an external resistor, RG, is required on Pin 1 to
limit the power dissipation for the XR-1543. Although
the XR-1543 is capable of handling 300 mA of current,
its power dissipation must be kept below the absolute
maximum ratings.
5. Low output voltage limit,
I
VTH
P '" RSC
Vo (
R2
)
+ RSC R2 + R3
4. Short circuit current,
ISC = VTH
RSC
Vo (low) = 2.5(R4 + R5 + R6)
R5 + R6
6. High output voltage limit,
In this circuit, current-limiting Is performed by sensing
the voltage drop across the resistor, RSC, in the positive supply line. The threshold for the amplifier is externally set by the resistor, RT
Vo (high) = 2.5(R4
.
+ R5 + R6)
R6
7. Voltage sensing delay, TO = 10,000 Co
The values of the external components useei'in Figure 9
are calculated as follows:
8. SCR trigger power limiting resistor,
1. Current limiting threshold, VTH '" 1~o
RG
> V,N -5
0.2
TO CONTROL
LOOP
Figure 8. Current Umlting Amplifier Connections for
Threshold Control and Frequency Compensation
1-348
XR·15/25/3543
V,N o---1r"--......- - - - - - - - - - - - - - - - - - - - - - - - . - - ,
RSC
FROU
;~~~--~---;----~JV~~-~r-------------.---t--.~----4r-RL
RL
TO
SYSTI;:M
CONTROL
R.
R2
TO VOLTAGE
CONTROL LOOP
R.
~-Cl~-- __+----_+-~----~~--~
_
Figure 9. Typical Connection lor Linear Foldback Current Limiting as well as Over-Voltage and Under-VoHage Protection.
r-----------------I
XR..1S43
I
I
I
I
I
I
I
I
I
I
I
I
~--~--~~IH
I
I
I
I
I
I
I
I
L______
I
_~
PIN 7
INPUT
a
PIN
DELAY _ _ _
'L__' L - _ J
..-----OFF
OU;~~~------------...,U
ON
Figure 10. XR-1543-lnput Line Monitor Circuit
1-349
XR·15/25/3543
MAIN SUPPLY
~--------------------------------------------------------------------~~
BUS
VOLT~~: 00---------------·-----1
r----------
I
I
I
SCR
"CROWBAR"
I
I
I
I
I
I
GND
I
L.
t--f,4J-,
_J
-..
1.
RESET
RSC
SUPPLY BUS
RETURN
Figura 11. XR·1543-0var Currant Shutdown Circuitry
Vour
Figure 12. XR·1543 - DC Convarter with Isolatad Currant Umltlng
1-350
XR·2230
Pulse-Width
Mod!l.ll~ator
GENERAL DESCRIPTION
Control System
FUNCTIONAL BLOCK DIAGRAM
The XR-2230 is a high-performance monolithic pulse
width modulator control system_ It contains all the necessary control blocks for designing switch mode power
supplies, and other power control systems. Included in
the 18-Pin dual-in-line package are two error amplifiers,
a sawtooth generator, and the necessary control logic
to drive two open-collector power transistors. Also included are protective features, such as adjustable
dead-time control, thermal shutdown, soft-start control,
and double-pulse protection circuitry.
.
COMP1
COMP2
SET
OSCILLATOR
OUTPUT
Vcc
The device provides two open-collector output transistors which are driven 180° out-of-phase, and are capable of sinking 30 mA. These outputs can be used to implement single-ended or push-pull switching regulation
of either polarity in transformerless or transformercoupled converters.
EXTERNAL
SHUTOOWN
PWM OUT
GND
OUT2
OUT1
FEATURES
Thermal Shutdown
Adjustable Dead-time
Dual Open-Collector
30 mA Output Transistors
Double-Pulse Protection Circuit
Soft-Start Control
High-Speed Remote Shut-Down Input
Two High-Performance Error Amplifiers
with ± 5V Input Common-Mode Range
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-2230CP
Plastic
O°C to + 70°C
SYSTEM DESCRIPTION
The XR-2230 PWM circuit contains two highperformance error amplifiers with wide input commonmode range, and large voltage gains. Typically, one amplifier (Pins 16, 17, 18) is used for current sensing and
the other (Pins 1, 2, 3) is used as an error amplifier to
sense the output voltage. The XR-2230 requires a split
supply between ± 8 volts and ± 15 volts, however, it
can be operated from a Single supply with proper external biasing on the ground pin and input pins of the error
amplifiers. The output drivers capable of sinking 30 mA
at a saturation voltage of about 0.3V can be used in a
push-pull configuration, or can be paralleled for a
single-ended configuration with a duty cycle between
0% to over 90%.
APPLICATIONS
Switching Regulators
Motor-Speed Controllers
Pulse-Width Modulated Control Systems
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage
Negative Supply Voltage
Input Voltage
Output Voltage
Power Dissipation (TA :5 25°C)
Operating Temperature
Storage Temperature
PWM IN
-0.5
+0.5
-18
-0.5
to + 18V
to -18V
to +18V
to +18V
400 mW
-10°Cto +85°C
-55°C to + 125°C
The XR-2230 features a self-protecting thermalshutdown circuitry which turns off the output drivers
when the junction temperature exceeds 130°C. The onboard regulator stabilizes the oscillator frequency to
0.1 %IV for reliable performance.
1-351
XR·2230
ELECTRICAL CHARACTERISTICS
Tast Conditions: TA
SYMBOL
= 25°C, VCC =
+ 12V, VEE
PARAMETERS
SUPPLY SECTION
Positive Supply Voltage
VCC
Negative Supply Voltage
VEE
Positive Supply Current
ICC
Negative Supply Current
lEE
OSCILLATOR SECTION
Frequency Range
fOSC
Initial Accuracy
VOSC
0
Supply Voltage Stability
Low Supply Voltage
Temperature Stability
Sawtooth Peak Voltage
Duty Cycle Range
VOLTAGE ERROR AMPLIFIER
Input Offset Voltage
VOS
Input Bias Current
IBIAS
Open-Loop Gain
AVO
Closed-Loop Bandwidth
f-3dB
CMMR
Common-Mode Rejection
Ratio
Output Voltage Swing
VOM
SR
Slew Rate
= -12V,
MIN
SR
Slew Rate
7.0
-2.0
MAX
UNIT
11.0
-6.0
-10
15.0
-2.0
V
V
mA
mA
100
15
kHz
%
10
3.0
10
60
+20
0.01
3.5
2
-.5
90
25
unless otherwise specified.
%N
0.1
-20
4.0
90
10
-30
%
%/oC
V
%
±5
V
60
60
±5
±4
4
3.1
2.8
3.1
2.8
-50
4
V/p.s
±5
V
4
-1.0
90
25
90
20
-60
mV
p.A
dB
kHz
dB
8
V
V
V/p.s
±5
V
3.6
3.3
3.6
3.3
-10
60
4.1
4.3
4.1
4.3
0.3
0.4
0.3
30
0.3
0.4
0.3
0.4
0.6
130
1-352
RT = 30 k~,
eT = 4700 pF
Vce = + 10V .. + 15V
VCC = + 18V, VEE = -8V
fose
= 20 kHz
p.A
60
2
CONDITIONS
mV
dB
kHz
dB
Input Voltage Range
MODULATOR SECTION
Set Input Open Voltage
(Pin 15)
Modin Input Open Voltage
(Pin 11)
Inhibit Input Current (Pin 13)
Inhibit Propagation Delay
td
Out1, Out2, Output Voltage
(Pins 9 and 10)
Low Supply Voltage
Out1, Out2 Fall Time
tf
Modout Output Voltage
(Pin 12)
Under Low Supply Voltage
Oscillator Output Voltage
(Pin 14)
Thermal Shutdown Temp.
= 20 kHz,
TYP
+10
Input Voltage Range
CURRENT ERROR AMPLIFIER
Input Offset Voltage
VOS
Input Bias Current
IBIAS
Open-Loop Gain
AVO
Closed-Loop Bandwidth
f-3 dB
CMRR
Common-Mode Rejection
Ratio
Output Voltage Swing
VOM
fOSC
V
V
V
V
p.A
ns
V
V
V
ns
V
V
V
V
V
°c
AveL ,,; 40 dB
VICM = ±4.5V
RL = 10 kO
Vce = +8V, VEE
AVCL = 14 dB,
RF = 10kO
=
-8V
=
-8V
AVCL = 40 dB
VICM = ±4.5V
RL = 10 kO
Vce = +8V, VEE
AACL = 14 dB,
RF = 10 kO
VCC
=
+8V, VEE = -8V
VCC
=
+8V, VEE = -8V
10 = 30 mA, TA = 25°C
TA = -10"" +85°e
10 = 27 mA, TA = 25°e
10
TA
10
10
TA
=
=
=
=
=
16 mA, TA = 25°e
-10"" +85°C
24 mA, TA = 25°C
3 mA, TA = 25°C
-10 "" +85°e
XR·2230
OSCILLATOR
OUTPUT
,.
DEAD TIME
COMJlARATOR
EXTERNAL
SHUTDOWN
IS'
Figure 1. Equivalent Schematic Diagram
PWM output so that the output transistor's off time is
a function of the error amplifier's input voltage.
PRINCIPLES OF OPERATION
The heart of the XR-2230 is the sawtooth generator. As
seen in Figure 1, this saw100th drives one input of each
of the three system comparators. Comparators one and
two have their other inputs tied to the outputs of the error amplifiers. These comparators will now produce, at
their outputs, square waves which will have a duty cycle proportional to the voltage at the inputs to the error
amplifiers, or pulse width information. The pulse width
information is fed into the NOR gate and used to provide the reset information to the pulse-width modulation
flip·flop (PWM). The PWM flip·flop information is fed in
to the NAND gate with the external shutdown and PWM
flip-flop set input. The information from the NAND gate
drives an open-collector transistor to provide the pulse·
width modulation output, Pin 12. The PWM output will
be a square wave with a frequency set by the sawtooth
generator, and a duty cycle equal to either comparator,
one or two, whichever is shorter. If the external shut·
down, Pin 13 is driven low, the PWM output will remain
low or go to zero duty cycle. The set input of the PWM
flip·flop, Pin 15, is normally connected to the buffered
sawtooth generator output, Pin 14, so that a reset pulse
is provided every cycle. Each output transistor is driven
by a three input NAND gate. These inputs consist of:
2. Pulse-steering information from flip-flop two, which
will determine which output transistor receives the
PWM input signal. Flip-flop two will toggle once every cycle of the sawtooth generator's output, which
will make the output transistor's toggle frequency
one-half that of the sawtooth generator's.
3. Information from dead-time and thermal shutdown
circuitry. The dead-time is an externally adjustable
time between one output transistor turning off and
the other turning on. This is used to protect external
circuitry. This dead-time is controlled by an external
voltage applied to Pin 6, which is internally compared with the saw100th waveform. The thermal
shutdown circuitry will drive the input to the NAND
gate low, if the junction temperature exceeds 130°C.
This will make both outputs low.
The circuit control blocks and functions operate as follows:
Error Amplifiers-These are high-gain op amps which are
used to sense output conditions, voltage and current,
and provide a dc voltage to comparators one and two.
This will in turn adjust the PWM output duty cycle and
ultimately that of the output transistors to correct for errors in the output voltage or overcurrent conditions. The
amplifier's outputs are provided for tailoring the closed-
1. Pulse width information from the PWM input, Pin 11,
which is used to control the off time of the output
transistors. The PWM input is normally tied to the
1-353
XR·2230
loop gain or frequency response of the system. Figure
2 shows the relationship between output duty cycle,
Pins 11 and 12 connected, and the voltage at Pins 1 or
18. Amplifier two is approximately twice as fast as Amplifier one, and should, therefore, be used to sense output current.
FADJ, Pin 7-A resistor, Rext to + VCC, and a capacitor,
Cext, to ground from this pin, set the frequency of the
sawtooth and oscillator output, by the relationship:
FOSC
External Shutdown, Pin 13-A low level signal applied to
this pin will turn both outputs on. If not. used, this input
should be left open-circuited. The impedance at this
node is approximately 1 MO.
=
2.68
Rext x Cext
The sawtooth waveform a signal varying from zero volts
to +5V, will be present at Pin 7. Normal values of Rext
will range from 1 kO to 100 kG. Figure 3 shows the oscillator period as a function of various Rext and Cext values.
Oscillator Output, Pin 14-This is an open-collector output
which will be a square wave with a frequency set by the
sawtooth generator. The duty cycle of this output will
vary from 10 to 90%, and is a function of the dead-time
setting. This pin is normally connected to Pin 15, set to
provide reset pulses for the PWM flip-flop.
The dead-time (minimum time from one output turning
on to the other turning off) is controlled by the voltage
applied to Pin 6.
Dead-time Control, Pin 6-Figure 4 shows output deadtime
as a function of VPIN 6. The maximum duty cycle of
each output is also controlled by the dead-time, and
may be determined by the following expression:
Set, Pin 15-This is the set input for the PWM flip-flop. A
low-going signal at this pin will cause the flip-flop to be
reset. The impedance at this pin is approximately 7.5
kO. This pin is normally connected to the oscillator output, Pin 14.
-~)
Duty Cycle Max(%) = (1
x 50%
VplN 6
PWM Out, Pin 12-This is an open-collector output which
provides a square wave with a duty cycle determined
by the error amplifiers. This output is normally connected to PWM IN, Pin 11.
VplN 6 <3.5V
The impedance into this pin is approximately 10 kG.
PWM In, Pin 11-This is the input which controls the duty
cycle of the output transistors. A low level on this pin
will drive both output transistors on. The impedance into this pin is approximately 7.4 kG.
APPLICATIONS INFORMATION
The soft-start function may be implemented as shown
in Figure 7. This configuration will reduce the output duty cycle to zero, and gradually increase to its normal
operating point, whenever power is applied to the circuit, or after an external shutdown command has been
given. This is used to keep the magnetics in the circuit
from saturating.
Output Transistors, Pins 9 and 10-These pins provide the
open-collector output transistors which are capable of
sinking 30 mA, typically. They are alternately turned off,
180 0 out-of-phase, at a rate equal to one-half the frequency of the oscillator.
100
-
0
1-'_- t-----
~
0
~
L
L
/
100.
•
•
20
K
300
...
V
/
V
/
VV L
V
:-L-
/
1/ V
/
S,.
$DO
/
/
•
•
V',11(MV)
}/
30
•
•
200
Z'~f/
..,'
~
100
V~I
!
~.;V
y r-v:r
V
~
lL /
/
V /V
10..
20#'
3O,.!IQ,.
too,..
200"
S.lIIttooth wsntorm P.rtodts.)
Figure 3. Oscillation Period vs REXT and CEXT
Figure 2. Modulation Duly Cycle vs Error Voltage
1-354
XR·2230
'.0
The time for the duty cycle to start will be approximately
equal to R1 x C1.
-
'cc
A typical step-down switching regulator configuration is
shown in Figure 8. Only one output transistor is used,
so that the maximum duty cycle will be limited to 45 %.
If a larger duty cycle range is needed, the two outputs
may be externally NOR'd as shown in Figure 9. This
configuration will allow up to 90% duty cycles.
o.0
L
C 1.0
oS
Figure 10 shows a detailed timing diagram of circuit op·
eration.
V
iJ
.Y •.0
50
40
\
'.0
\
/
'.0
tOY
IV
"V
t2Y
16V
Vee '-EElevt
Figure 5. Supply Current vs Supply Voltage
0
\\
o f----
/
1'•• 1
SOD ..V
\
0
s
oS
:;
'00
,
TA - 2SC
[
\
~
..!¥
0
z
~
300
VPWMOUT
.,,..'Y ~UT1.2
...
/"
N
~
Figure 4. Dead Time vs Dead Time Adjustment Voltage
,-«-II,
~
"V
100
V
~
..
10
..
30
'oUTf"''''1
Figure 6. Output Saturation Voltage vs Load Current
RECOMMENDED OPERATING CONDITIONS
SYMBOL
CONDITION
UNIT
Positive Supply Voltage
+10", +15
V
VEE
Negative Supply Voltage
-10", -15
V
RR
Minimum Feedback Resistance
10
kll
AV
Minimum Voltage Gain
14
5
dB
VN
VCC
PARAMETER
1-355
..
XR·2230
EXTERNAL
SHUTDOWN
OR POWER DOWN
Vee
13
6
XR-2230
.D.T.ADJ
D.T.ADJ.
Figure 7. Soft Start Connection
XR-2230
-15Vo------.----------1---------------;
GN~
DI .. MR 850
01 .. MJE 171
+15V @ 200 mA
Ll
Figure 8. + 10Y Step-Down Regulator
1-356
,.. 40 TURNS #20 WIRE ON
FERROXCUBE #K300502
TOROID CORE
XR·2230
Figure 9. Outputs Nor'd for up to 90% Duty Cycle's
NORMAL OP!.AAnON
STEADY STATE WITH
VOLTACE ERROR FEEOBACK
PROT£CTlOH OF
MAXIMUM CoUTY
DOUBLE·PULSING
CYCLE LIMIT
OPERAnON
DrTlCTfON
Figure 10. Timing Waveform Diagram
1-357
XR·4194
Dual-Tracking Voltage Regulator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-4194 is a dual-polarity tracking regulator designed to provide balanced or unbalanced positive and
negative output voltages at currents of up to 200 mA_ A
single resistor can be used to adjust both outputs between the limits of ± 50mV and ± 42 V. The device is
ideal for local on-card regulation, which eliminates the
distribution problems associated with single-point regulation. The XR-4194 is available in a 14-pin ceramic
dual-in-line package, which has a 900 mW rating.
FEATURES
Direct Replacement for RM/RC 4194
Both Outputs Adjust with Single Resistor
Load Current to ±200 mA with 0.2% Load Regulation
Low External Parts Count
Internal Thermal Shutdown at TJ = 175·C
External Adjustment for ± Vo Unbalancing
APPLICATIONS
On-Card Regulation
Adjustable Regulator
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-4194CN
XR-4194M
Ceramic DIP
Ceramic DIP
O·C to +70·C
-55·C to + 125·C
ABSOLUTE MAXIMUM RATINGS
Input Voltage ± V to Ground
±45 V
XR-4194M
±35V
XR-4194CN
±45V
Input/Output Voltage Differential
900 mW
Power Dissipation at TA = 25·C
150 mA
Load Current
Operating Junction Temperature Range
XR-4194M
-55·C to +150·C
XR-4194CN
O·C to + 125·C
-65·C to + 150·C
Storage Temperature Range
SYSTEM DESCRIPTION
The XR-4194 is a dual polarity tracking voltage regulator. An on board reference, set by a single resistor, determines both output voltages. Tracking accuracy is
better than 1 %. Non-symmetrical output voltages are
obtained by connecting a resistor to the balance adjust
(Pin 4). Internal protection circuits include thermal
shutdown and active current limiting.
1-358
XR·4194
ELECTRICAL CHARACTERISTICS
Test Conditions: +
-5
- 55°C oS
TJ
oS
VOUT
VMAX; XR-4194M - 55°C
oS
oS
XR-4194M
oS +125°C
+ 125°C; XR-4194CN O°C
TJ
oS
oS
+ 70°C
XR-4194CN
TYP
MAX
TYP
MAX
UNIT
Line Regulation
0_02
0_1
0.02
0.1
%VOUT
l"vIN = 0.1 VIN
Load Regulation
0.001
0.0025
0.001
0.004
%VO/mA
XR-4194CN, M:
IL = 5 to 100 rnA
PARAMETERS
MIN
MIN
CONDITIONS
0.002
0.020
0.003
0.015
%/oC
from
+0.3
+1.0
+0.3
+1.5
rnA
to
-1.2
-2.0
-1.2
-2.0
±45
±9.5
±35
V
2.5
2.55
2.38
2.5
2.62
KON
RSET = 71.5 K
TJ = 25°C
+42
0.05
±32
V
RSET = 71.5 K
2.0
%
TC of Output Voltage
'Stand-by Current Drain
Input Voltage Range
±9.5
Output Voltage Scale Factor
2.45
Output Voltage Range
0.05
Output Voltage Tracking
1.0
Ripple Rejection
70
Input-Output Voltage Differential
70
3.0
VIN = VMAX, Vo = OV
VIN = VMAX, Vo = OV
f = 120 Hz, TJ = 25 DC
dB
3.0
V
IL = 50mA
Output Short Circuit Current
300
300
rnA
Output Noise Voltage
250
250
p.V RMS
Internal Thermal Shutdown
175
175
DC
VIN = ±30 V Max
CL = 4.7 p.F, Vo = ±15 V
f = 10 Hz to 100 KHz
• ± IQuiescent will increase by 50 P.ANOUT on positive side and 100 p.ANOUT on negative side.
THERMAL CHARACTERISTICS
XR-4194M
PARAMETERS
MIN
TYP
Power Dissipation
XR-4194CN
MAX
MIN
TYP
900mW
2.2 W
Thermal Resistance
Junction to Ambient
Junction to Case
128°C/W
55°C/W
1
-VOUT
A.
4.7,.F TANTALUM
.AL
'vo
~
-Vo
AO
Ao
X~l"
Ao
GH'
GN'
0.0011"'
r
O.ooI",F
c-
c·
O.OOI"F
'Vo.
AS
-VIN
c'
c-
VIN+
VIN-
I ·
71.S""
I.G!"F
0 1}.F
V,,-
'"='
o.ool,..F
AS
p. ,
11.5Ko
"VIN
R(J(KUj .. :UVOUT
" For Btsl T,acIung Temp8,.lu,. Coelfll;lQnl
of
TA = 25°C
TC = 25°C
-VOUT
Ao
XR-41M
r
CONDITIONS
128°C/W
55°C/W
"VOUT
+\lOUT
MAX
900mW
2.2W
Ao ShouICl Be sam. .... F!)l RS
""'.... Rolor -Vs -IiVpSKIIIIr..n
.\dII.sIRator +VS· 12 V (20KUl
Figure 2_ Typical Applications
1-359
-VIN
~
AO (Kill = Z.$ YOUT
XR·4194
COlI'.
Vo·
.AL
flo
fiiE;EIIENCE UN;; -
I
I
I
I
I
I
I
-
-
-
-
-
-
-
llSET
L __ _
...,
-- -- -,
QNa
I
Vo-
I
I
I
I
COIIP-
IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
I
~
L ________________
EQUIVALENT SCHEMATIC DIAGRAM
1-360
~
-VIN
XR·4195
+ 15V Dual-Tracking Voltage Regulator
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-4195 is a dual-polarity tracking regulator designed to provide balanced positive and negative 15V
output voltages at currents of up to 100mA.
UIMp·
The device is ideal for local "on·card" regulation, which
eliminates the distribution problems associated with
single-point regulation. Intended for ease of application,
the XR-4195 requires only two external components for
operation.
POSITIVl
IHliUl ATOfl
GND
BAI
FEATURES
Direct Replacement for RM/RC 4195
± 15V Operational Amplifier Power
Thermal Shutdown at Tj = + 175°C
Output Currents to 100mA
As a Single Output Regulator, it may be used with up to
+50V Output
Available in 8-Pin Plastic Mini·DIP
Low External Parts Count
ORDERING INFORMATION
Part Number
Package
XR-4195CP
Dip
Operating Temperature
O°C to
+ 70°C
APPLICATIONS
Operational Amplifier Supply
On-Card Regulation
Regulating High Voltage
SYSTEM DESCRIPTION
The XR-4195 is a dual polarity tracking voltage regulator, internally trimmed to ± 15V. Only output capacitors
are required for operation. Internal protection circuits
include thermal shutdown and active current limiting.
The device may be configured as a single output high
voltage regulator by adding a voltage divider between
an output pin, the device ground (Pin 2) and system
ground.
ABSOLUTE MAXIMUM RATINGS
Input Voltage ± V to Ground
Power Dissipation at TA = 25°C
Load Current
Operating Junction Temperature
Range
Storage Temperature Range
±30 V
600 mW
100 mA
O°C to + 125°C
- 65°C to + 150°C
1-361
XR·4195
ELECTRICAL CHARACTERISTICS
Test Conditions: (lL = 1mA, VCC = ± 20V, CL = 1O/LF unless otherwise specified)
XR-4195CP
PARAMETERS
TYP
MAX
UNITS
Line Regulation
MIN
2
20
mV
VIN = ±18to ±30V
Load Regulation
5
30
mV
IL = 1 to 100 mA
0.005
0.015
%IOC
±1.5
±3.0
mA
30
V
Output Voltage Temperature
Stability
Standby Current Drain
Input Voltage Range
18
Output Voltage
14.5
Output Voltage Tracking
Ripple Rejection
15
15.5
V
±50
±300
mV
CONDITIONS
VIN = ± 30V, IL = OmA
Ti = +25°C
75
dB
V
IL = 50mA
Short·Circuit Current
220
mA
Ti = +25°C
Output Noise Voltage
60
/LV RMS
Internal Thermal Shutdown
175
°C
Input-Output Voltage Differential
3
f = 120 Hz, Ti =
+25°C
Ti = +25°C,
f = 100 Hz to 100 kHz
THERMAL CHARACTERISTICS
XR·4195CP
PARAMETERS
MIN
TYP
Power Dissipation
Thermal Resistance
+15Vat lOOrnA
MAX
CONDITIONS
0.6W
TA = 25°C
TC = 25°C
OJ-C
OJ-A
210°C/W
-15V at 100mA
10pF
.P~
-=- iI","'v"'o--"'v-o" -=XR-4195
XR-4195
GNO
GNO
Vo
A2
=+15V (1 + - )
Al
(V O +JV) --...-_.£
INPUT 1.7
XR-2003
XR-2004
OUTPUT 10·16
INPUT '.7
2.7k
10.5K
3K
3K
1-365
OUTPUT 10.11
XR·2001/2/3/4
CHARACTERISTIC CURVES
(a) XR-2002
(c) XR-2003
(b) XR-2004
•. S
y
~ 2.0
I
1 1.5
..
.
~ 'fIf\C~
!
~ 1.0
a0.5 ~
i
0
12
,.
J
- .-
--
r--r--,--r---.-...,.---r---.
2.0
I
1,.51--t-+-t--t-+-t-::::I
..ffi
!
1.0
'"
§
F::-Io-'-F'-'-+--+-+-+--+
u 0.5
m
n
16
II
INPUT VOLTAGE - Y,N
i
H
~
r--r--,--r--r-...,.---r---.--,
oL-J-~__L--L_-J~~~
7
a
II
'0
INPUT VOLTAGE - Y,N
5
It
12
Figure 1. Input Currant as a Function of Input Voltages
600
I
lOG
/
/
/
/
//
It"ci'/
~/
/
as -'"
/
,.
1/'/
/
/
/
/
/
/
/
y
I
/.
/
/
1 400
..
i!;
'#~~
.....
/
z
~
w
a:
a:
..0"
';10+
.;
. .J'/
'a:"
~
~
~~
200
II
::l
o
u
/
/
/
I
/ V
!/ /
,V
1.5
,~
SATURATION VOLTAGE -
/
"/
U
,>'"
/
/
V
/
~ INPUT CURRENT
MAXIMUM REOUIRED
/
200
•.0
VeE (SAT)
600
400
INPUT CURRENT IN /-I-A -
Figure 2. Collector Current as a Function of Saturation
Vollage.
/
liN
Figure 3. Collector Current as a Function of Input Current
2.0
~
\DEYICE LIMIT
'\ "I\~Q
~ ~
u
DEVICE UtltlT
~ 'CJO
~~
SEAlES XR·2000
r-.....-.:-~-r--...,...,---..:,--r----r---.;:---,
-'CJ,:
:c
~
z
;
\0
-.~
1', \
'50 r---tT"",.r~-i----'''''''+--P......,-t--+--i
\. r-.
a xol---t--~~~-~d--~~~-t--~~~
., \'&.
~, \%.
~ \
I.50~--+---+-,--+~~-P~~~~~--~~~
"
"~ ~I---+--+---t--+--I-~~~~"~~
;
\
~
NUU:~:~:~~'r:UTS
! ,. ~:-_~~:~U_U_A_NE_O+.:~SL_Y_~
...-_...~_~~~_-t.80'-_~"'-_7....
50
PER CENT DUTY CYCLE
.00
'\
'50
AMBIENT TEMPERATURE IN °C
Figure 4. Peak Collector Current as a Function of Duty Cycle
and Number of Outputs
Figure 5. Allowable Average Power Dissipation as a Function
of Ambient Temperature
1-366
XR·2001/2/3/4
TYPICAL APPLICATIONS
XR-2002
+Vss
PMOS
OUTPUT
TTL
OUTPUT
Figure 6. PMOS to Load
Figure 7. TTL to Load
XR-2004
XR-2003
TTL
CMOS
OUTPUT
OUTPUT
Figure B. Buller for Higher Current Loads
Figure 9. Use of Pull-up Resistors to Increase Drive Current
1·367
XR·2011/12/13/14
High-Voltage, High-Current Darlington
Transistor Arrays
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-2011/2012/2013/2014 are high-voltage, highcurrent Darlington transistor arrays consisting of seven
silicon NPN Darlington pairs on a common monolithic
substrate. All units feature open collector outputs and
integral protection diodes for driving inductive loads.
Peak inrush currents of up to 750 mA are allowed,
which makes the arrays ideal for driving tungsten filament lamps. The outputs may be paralleled to achieve
higher load current capability although each driver has
a maximum continuous collector current rating of 600
mA. "The arrays are directly price competitive with discrete transistor alternatives.
INPUTS
FEATURES
Peak Inrush Current Capability of 750 mA
Internal Protection Diodes for Driving Inductive Loads
Excellent Noise Immunity
Direct Compatibility with Most Logic Families
Opposing Pin Configuration Eases Circuit Board Layout
APPLICATIONS
Relay Drive
High Current Logic Driver
SYSTEM DESCRIPTION
The XR-2011 device is a general purpose array to be
used with bipolar digital logic (with external current limiting), or with CMOS or PMOS directly. Output pins opposite input pins facilitates circuit board layout.
ABSOLUTE MAXIMUM RATINGS TA = 25°C
Output Voltage, VCE
50V
Input Voltage, VIN
30V
Continuous Collector Current, IC (Each Driver)600 mA
Continuous Base Current, IB (Each Driver)
25 mA
Power Dissipation, Po (Each Driver)
1.0 W
(Total Package)
See graph
16.67 mW/oC
Derate Above 25°C
Storage Temperature Range
- 55°C to + 150°C
The XR-2012 was specifically designed to interface
with 14 to 25 volt PMOS devices. The input current is
limited to a safe value by a Zener diode and resistor in
series.
A 2.7 kO series base resistor to each Darlington pair in
the XR-2013 permits operation directly with CMOS or
TIL operating with a 5 volt supply. Interface requirements beyond the scope of standard logic buffers are
easily handled by the XR-2013.
ORDERING INFORMATION
Pari Number
XR-2011
XR-2012
XR-2013
XR-2014
CN
CN
CN
CN
Package Type
Ceramic
Ceramic
Ceramic
Ceramic
Operating Temperatura
O°C
O°C
O°C
O°C
to
to
to
to
The XR-2014 requires less input current than the XR2013 and the input voltage is less than that required by
the XR-2012. The XR-2014 has a 10.5 kO series input
resistor, permitting operation directly from PMOS or
CMOS outputs using supply voltages of 6 to 15 volts.
+ 70°C
+ 70°C
+ 70°C
+ 70°C
1-368
XR·2011/12/13/14
ELECTRICAL CHARACTERISTICS (TA 25°C unless otherwise noted)
LIMITS
SYMBOL
ICEX
PARAMETERS
MIN
TYP
MAX
UNITS
100
500
500
p.A
p.A
VCE
VCE
VCE
1.7
1.3
1.1
1.9
1.6
1.3
V
V
V
IC
IC
IC
0.82
0.93
0.35
1.0
1.25
1.35
0.5
1.45
mA
mA
mA
mA
VIN
VIN
VIN
VIN
p.A
IC
V
V
V
V
V
V
V
VCE
VCE
VCE
VCE
VCE
VCE
VCE
Output Leakage Current
XR-2012
XR-2014
VCE
Collector-Emitter Saturation
Voltage
liN
Input Current (on)
XR·2012
XR-2013
XR-2014
liN
Input Current (off)
VIN
Input Voltage
XR-2012
XR-2013
50
65
17
2.7
3.0
3.5
7.0
8.0
9.5
XR-2014
hFE
D·C Forward Current Transfer
Ratio
XR-2011
CIN
Input Capacitance
pA
1000
15
CONDITIONS
= 50 V, TA = 70°C
= 50 V, TA = 70·C, VIN = 6V
= 50 V, TA = 70·C, VIN = 1V
= 500mA, 18 = 600p.A
= 350mA, 18 = 500p.A
= 200mA, 18 = 350p.A
= 17V
= 3.85V
= 5V
= 12V
= 500p.A, TA = 70·C
IC
IC
IC
IC
IC
IC
IC
= 500mA
= 250mA
= 300mA
= 500mA
= 275mA
= 350mA
= 500mA
VCE = 2 V, IC
= 350mA
30
PF
50
p.A
VR
= 2 V,
= 2 V,
= 2 V,
= 2 V,
= 2 V,
= 2 V,
= 2 V,
= 50V
= 500mA
IR
Clamp Diode Leakage Current
VF
Clamp Diode Forward Voltage
2.1
2.5
V
IF
tPLH
Turn-On Delay
0.25
1.0
p.S
0.5 EIN to 0.5 EOUT
tpHL
Turn-Off Delay
0.25
1.0
p.S
0.5 EIN to 0.5 EOUT
SCHEMATIC DIAGRAMS (One of 7 Identical Drivers is shown for each device.)
XR-2011
r----,.-~-,..--O
INPUT ,.,
OUTPUT '0-1'
-r--11::.
-r:-'K--t-o
XR-2013
INPUT',"
INPUT 1·'
UK
la.!5K
,.
1-369
XR·2011/12/13/14
CHARACTERISTIC CURVES
(a)
XA-2012
(c)
XA-2014
(b)
XA-2013
'.5 r---r-,--,r--'--'--'-'----:J
J
2.0
y
I
11.5
!
I··D V
e
0.5
..
..."./ '('I~~ •
I-"
... ....
J
....
E '.5
!
D••
'4
-
~ '.D
60.5 f --
!;
~
2.0
I
c
l'
1.
20
22
INPUT VOLUGE - V,N
2t
..
i
0
~
..,.y..
P--;'P\C"~
p- f-"":I;""-
I-'
5
7
•
•
INPUT VOLTAGE -
---
10
VIN
11
12
Figure 1. Input Current as a Function of Input VoHagas
600
100
I
/
/
/
!i
I
/
/
/
/
/
I
V
/lJl'
~
0.5
J
_l
/
/
1/ /
V
1.1
V
I
",
1"
/
if
~J'I
R'
'#:"
~ ....
I
/
I
/) .rIII
'.r
/~'/
......
/
z.o
L
K
L
MAXIMUM REOUIRED
INPUT CURRENT
V
400
200
IlATV..... - VOLTAGE - VCE CSATJ
L
V
INPUT CURRENT IN IJA -
600
liN
Figure 3. Collector Currant as a Function of Input Currant
Figure 2. Collector Current as a Function of Saturation
VoHaga
'.0
5• '.5
.... ....
!
~
~
~
6
a:
~ '.0
i
~
;
l~
\"'DEVICE UMIT
'\
1\ 1\,
~ ~~
~~~\)~
~\1L!
1', \
,
1\
\Of>.
0.5
~'~
"
~
\
'~
'~.LD--J--~--·~~-~~L--~mr---~~-~-~
50
.00
AMBIENT TEMPERATURE IN "C
PER CENT DUTY CYCLE
Figura 4. Peak Collector Currant as a Function of Duty Cycle
and Number of Outputs
~
'50
Figure 5. Allowable Average Power Dissipation as a Function
of Ambient Temperature
1-370
TYPICAL APPLICATIONS
XR·2011/12/13/14
XR-2013
XR-2012
+Vcc
+Vss
.l
PMOS
OUTPUT
LAMP
TEST
TTL
OUTPUT
Figure 7. TTL to Load
Figure 6. PMOS to Load
XR-2014
XR-2013
TTL
CMOS
OUTPUT
OUTPUT
Figure 9. Use of Pull-up Resistors to Increase Drive Current
Figure 8. Buller for Higher Current Loads
1-371
XR·2200
Hammer Driver
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2200 is an array of five Darlington transistor
pairs which are capable of driving high-current loads
such as solenoids, relays, and LED's. Each of the five
circuits contained on the XR-2200 is capable of sinking
up to 400 mA.The XR-2200 was specifically designed
for use with 14 V to 25 V PMOS devices.
FEATURES
Output Capability of 400 mA for Each Driver
Drivers may be used in parallel for increased output
drive capability.
Input is directly compatible with PMOS outputs
APPLICATIONS
Printing Calculator Hammer Driver
High Current LED Driver
Solenoid and Relay Driver
Tungsten Lamp Driver
High Current Switch
ORDERING INFORMATION
Part Number
Package Type
XR-2200 CP
Plastic
Operating Temperature
- 25·C to
+ 70·C
ABSOLUTE MAXIMUM RATINGS
Collector to Base Voltage
Collector to Emitter Voltage
Emitter to Base Voltage
Collector Current
Input Terminal Breakdown
Voltage (plus)
Input Terminal Breakdown
Voltage (minus)
Power Dissipation
30V
30V
5.5V
450 mA
30V
SYSTEM DESCRIPTION
The XR-2200 hammer driver contains five Darlington
connected transistor pairs, each capable of switching
30V. All five emitters are connected to a common
ground (Pin 7). With a guaranteed current gain of 2000,
each section of the XR-2200 can sink 400 mA.
-0.5V
550 mW
1-372
ELECTRICAL CHARACTERISTICS (TA
XR·2200
= 25°C)
LIMITS
PARAMETERS
MIN
TYP
MAX
UNITS
26
Vdc
Power Supply Voltage
Output Leakage Current
100
pA
Output Current
One Driver
400
rnA
CONDITIONS
VCE = 26 V, VIN = 0 V
See Figure 2
Output Current
5 Drivers
Output Saturation Voltage
Current Gain
2.2
Vdc
lOUT = 400 rnA
VIN = 17 V
lOUT = 200 rnA
VIN = 17 V
2000
Input Current
VCE = 3 V
lOUT = 200 rnA
0.7
rnA
VIN = 17 V
lOUT = 0 rnA
500
OUTPUT
400
,
300
INPUT o-~M-'---C
\
25 K
200
2K
25 K
100
20
PULSE FREQUENCY ~ 10 Hz
I'"I"40
80
-
80
100
% DUTY CYCLE
Figure 1. Schematic Diagram (1 of 5 Circuits Shown)
Figure 2. Maximum Permissible Output Current per Driver vs
Duty Cycle with 5 Drivers Pulsed Simultaneously.
LOAD
PMOS
GATE
1/5 XR-2200
PMOS
GATE
115 XR·2200
DIODES ARE 1N4002
OR eQUIVALENT
Figure 3. Circuit Connection for Driving Non-Inductive Loads
Figure 4. Circuit Connection for Driving Inductive Loads.
NOTE: The XR·2200 may be damaged if the di·
odes are omitted when driving an inductive
load.
1·373
XR·2201/2/3/4
High-Voltage, High-Current Darlington
Transistor Arrays
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-22D1, XR-22D2, XR-2203, and XR-2204
Darlington transistor arrays are comprised of seven silicon NPN Darlington pairs on a single monolithic substrate. All units feature open-collector outputs and integral protection diodes for driving inductive loads. Peak
inrush currents of up to 600 mA are allowable, making
them also ideal for driving tungsten filament lamps. Although the maximum continuous collector current rating is 500mA for each driver, the outputs may be paralleled to achieve higher load current capability.
FEATURES
High Peak Current Capability-600mA
Internal Protection Diodes for Driving Inductive Loads
Directly Compatible with TIL, CMOS, PMOS, and DTL
Logic Families
Exact Replacement for Sprague Types ULN-2001A,
ULN-2002A, ULN-2D03A, and ULN2004A
ORDERING INFORMATION
Part Number
Package
XR-2201CP
XR-2202CP
XR-2203CP
XR-2204CP
Plastic
Plastic
Plastic
Plastic
Operating Temperature
O°C to
DOC to
DOC to
DOC to
+85°C
+85°C
+85°C
+85°C
SYSTEM DESCRIPTION
APPLICATIONS
The XR-2201 is compatible with most common logic
forms, including PMOS, CMOS, and TIL. It requires a
current-limiting resistor placed in series with the input
to limit base current to less than 25mA.
Relay Drivers
Solenoid Drivers
High Current Inverters
The XR-2202 is designed for direct compatibility with
14V-25V PMOS devices.
ABSOLUTE MAXIMUM RATINGS TA
The XR-2203 is compatible with TIL or CMOS operating
at 5 volts. Each input has a series base resistor to limit
the input current to a safe valve.
= 25°C
50V
Output Voltage, VCE
Input Voltage,VIN
30V
Emitter-Base Voltage, VEBO
6V
Continuous Collector Current, IC (Each Driver) 500mA
Continuous Base Current, IB (Each Driver)
25mA
Power Dissipation, Po (Each Driver)
1.0W
(Total Package)
2.0W
Derate Above 25°C
16.67 mW/oC
Storage Temperature Range
- 55°C to + 150°C
The XR-2204 is designed for direct operation from
CMOS or PMOS outputs utilizing supply voltages of 6 to
15V.
With all four devices, the load should be connected between the driver output and + VCC. For protection from
transient voltage spikes, Pin 9 should be connected to
+VCC·
1-374
XR·2201/2/3/4
ELECTRICAL CHARACTERISTICS
Test Conditions: TA
=
25 c C
unless otherwise noted
PARAMETERS
MIN
LIMITS
TYP
MAX
UNITS
1.25
100
500
500
1.6
p.A
p.A
p.A
V
1.1
0.9
1.3
1.1
V
V
IC
IC
0.85
0.93
0.35
1.0
1.3
1.35
0.5
1.45
mA
mA
mA
mA
VIN
VIN
VIN
VIN
p.A
IC
Output Leakage Current
XR-2202
XR-2204
Collector-Emitter Saturation
Voltage
Input Current
XR-2202
XR-2203
XR-2204
Input Current
50
65
Input Voltage
XR·2202
XR-2203
XR-2204
D-C Forward Current Transfer
Ratio XR-2201
13
2.4
2.7
3.0
5.0
6.0
7.0
8.0
V
V
V
V
V
V
V
V
pF
CONDITIONS
VCE = 50 V, TA
VCE = 50 V, TA
VCE = 50 V, TA
IC = 350mA, IS
= 200mA, IS = 350p.A
= 100mA, IS = 250p.A
= 17V
= 3.85V
= 5V
= 12V
= 500p.A, TA = 70 c C
VCE = 2V, IC
VCE = 2V, IC
VCE = 2V, IC
VCE = 2V, IC
VCE = 2V, IC
VCE = 2V, IC
VCE = 2V, IC
VCE = 2V, IC
1000
= 70 c C
= 70 c C, VIN = 6V
= 70 c C, VIN = 1V
= 500p.A
VCE
= 2V,
IC
= 300mA
= 200mA
= 250mA
= 300mA
= 125 mA
= 200mA
= 275mA
= 350mA
= 350mA
Input Capacitance
15
30
Turn-On Delay
1.0
5
p.S
Turn·Off Delay
1.0
5
p.S
0.5 EIN to 0.5 EOUT
50
p.A
VR = 50V
2
V
Clamp Diode Leakage Current
Clamp Diode Forward Voltage
1.7
0.5 EIN to 0.5 EOUT
IF
= 350mA
SCHEMATIC DIAGRAMS (One of 7 Identical Drivers is shown for each device.)
OUTPUT 10·16
r---1~--1--O OUTPUT 10·16
INPUT ,.,
<>---
OUTPUT 10-16
, - - - . - - . - -........-0
XR-2203
XR-2204
1·375
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Special Functions
XR·S200
Multi-Function PLL System
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-S200 integrated circuit is a highly versatile,
multipurpose circuit that contains all of the essential
functions of most communication system designs on a
single monolithic substrate. The function contained in
the XR-S200 include: 1. a four quadrant analog multiplier, 2. a high frequency voltage controlled oscillator
(VCO) and 3. a high performance operational amplifier.
The three functions can be used independently, or directly interconnected in any order to perform a large
number of complex circuit functions, from phaselocked loops to the generation of complex waveforms.
The XR-S200 can accommodate both analog and digital
signals, over a frequency range of 0.1 Hz to 30 MHz,
and operate with a wide choice of power supplies extending from ± 3 volts to ± 30 volts.
FEATURES
Wide VCO Frequency Range
0.1 Hz to 300 MHz
Wide Supply Voltage Range
± 3V to ± 30 V
Uncommitted Inputs and Outputs for Maximum
Flexibility
Large Input Dynamic Range
UP AMP
C:UMP
APPLICATIONS
Phase-locked loops
FM demodulation
Narrow and wideband FM
Commercial FM-IF
TV sound and SCA detection
FSK detection (MODEM)
PSK demodulation
Signal conditioning
Tracking filters
Frequency synthesis
Telemetry coding/decoding
AM detection
Quadrature detectors
Synchronous detectors
Linear sweep & AM generation
Crystal controlled
Suppressed carrier
Double sideband
Tone generation/detection
Waveform generation
Single/squareltriangle/sawtooth
Analog multiplication
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Derate above +25°C
Temperature
Operating
Storage
Input Signal Level, Vs
30 Volts
900 mW
5 mW/oC
-55°C to +125°C
-65°C to + 150°C
6 V,p-p
ORDERING INFORMATION
1-376
Part Number
Package
Operating Temperature
XR-S200
Ceramic
O°C to + 70°C
ELECTRICAL SPECIFICATIONS (T
= 25°C, VSUPPLY =
XR·S200
± 10V)
LIMITS
PARAMETERS
MIN
TYP
MAX
UNITS
CONDITIONS
MULTIPLIER SECTION: See Figure 2, Rx = Ry = 15k, Pins 1, 2, 6, 23, 24 Grounded.
Output Offset Voltage
Input Bias Current
Input Offset Current
Linearity
(Output error, %
of full scale)
Scale Factor, KM
Input Resistance
3 dB Bandwidth
Phase detection B.w.
Differential Output Swing
Output Impedance
Single Ended
Differential
±40
5
0.1
0.3
3
50
±4
±120
15
1.0
mV
p.A
p.A
1.0
1.5
0.1
1.0
6
100
±6
MO
MHz
MHz
V pop
6
12
kO
kO
%
%
-
Vx = Vy = 0, Vio = IV3 Measured at pins 5 and 7
Measured at pins 5 and 7
V41
-5 < Vx < +5, Vy = ±5V
- 5 < Vs < + 5, Vx = ± 5V
KM = 2 IRxRy (Adjustable)
f = 20 Hz, Measured at pins 5 and 7
CL :s 5 pF
Rx = Ry = 0
Measured across pins 3 and 4
Measured at pins 3 and 4
OPERATIONAL AMPLIFIER SECTION: See Figure 10 and 11, RL = 20k, CL = 550 pF.
Input Bias Current
Input Offset Current
Input Offset Voltage
Differential Input Impedance
Resistance
CapaCitance
Common Mode Range
Common Mode Rejection
Open Loop Voltage Gain
Output Impedance
Output Voltage Swing
Power Supply Sensitivity
Slew Rate
O.OS
0.02
1.0
0.5
0.2
6.0
p.A
p.A
mVdc
Open loop, f = 20 Hz
0.4
70
66
±7
MO
pF
V
dB
dB
kO
V
p.VIV
2.0
1.0
±S
90
SO
2
±9
30
2.5
V/p.sec
f = 20 Hz
RL ~ 20 kO
Rs :s 10 kO
Av = 1, CL = 10 pF
VCO SECTION: See Figure 11, RL = 10k, fo = 1 MHz.
Upper Frequency Limit
Sweep Range
Linearity
(distortion for
.Ilflf = 10%)
Frequency Stability
Power Supply
Temperature
Analog Input Impedance
Resistance
CapaCitance
Output Amplitude
Output Rise Time
Fall Time
Input Common Mode Range
15
S:1
MHz
30
10:1
-
Co = 10 pF
fo = 10 kHz, See Figure 14
Digital Controls Off
Digital Controls Off
.2
1.0
%
O.OS
300
0.5
650
%IV
ppm/oC
VCC > SV, fo = 1 MHz
Sweep Input Open
Measured at pins 23 and 24
0.1
+6
-4
0.5
1.5
3
15
20
+S
MO
pF
V pop
ns
ns
Vdc
Vdc
-6
Squarewave
CL = 10 pF, RL = 5 kO
CAUTION: When using only some of the blocks within the XR-S200, the input terminals to the unused section must
be grounded (for split-supply operation); or connected to an ac ground biased at V + 12 (for single supply
operation).
1-377
XR·S200
XR-S200 ANALOG MULTIPLIER SECTION
The analog multiplier in the XR-S200 (Figure 2) provides
linear four-quadrant multiplication over a broad range of
input signal levels. It also serves as a balanced modulator, phase comparator, or synchronous detector. Gain is
externally adjustable. Nonlinearity is less than 2% of
full scale output.
'IOV
,
n
I
1001<..
TYPICAL APPLICATIONS OF MULTIPLIER SECTION
•
•
•
•
•
•
10K
lOOK
-=-V,
Analog multiplication/division
Phase detection
Balanced modulation/demodulation
Electronic gain control
Synchronous detection
Frequency doubling
~ ACIOf'
ADJUST
X
>-+"<>---0
OlJlPUI
IOV
..
ElK
TO X AND Y
Of
~SET
-=-
1!l1<:
A[).J
ANALOG MULTIPLICATION
Figure 3. Analog Multiplication
The XR-S200 multiplier section can be combined with
the amplifier section to perform analog multiplication
without the need for dc level shifting between input and
output. The amplifier functions as an operational amplifier with a single-ended output at ground level when
connected as shown in Figure 3.
tVcc
VR(tl
REFERENCE INPUT
o--j ~--o;.-i
c,
lK
10
11
XA ·5200
MUL TlPLIEA
SECTION
C,
J
5
XR-S200
MULTIPLIER
SECTION
L - - . - - - . . . - - - T " " ".....
Y-INPUT
L-T"""---'--T"""....I
Cc
VAW = ERcos wo 1
Vsltl '- Estos(wot
-=- Vy
OUTPUT
lK
SIGNAL INPUT
Vo
X-v GROUND
CB
v~~-o'---l
OUTPliT
X-INPUT
I
i
Q)
~
COUPLING CAPACITOR
C B ~ BYPASS CAPACITOR
Figure 4. XR-S200 Multiplier Section as a Phase Comparator
8
normally a high level reference signal and the other input a low level information signal. Since the XR-S200
multiplier section offers symmetrical response with respect to the X and Y inputs, either input can be used as
the carrier or signal input. For low input levels, the conversion gain is proportional to the input signal amplitude. For high level inputs, (Vs > 40 mV, rms) Kef> is
constant and approximately equal to 2V/rad.
Figure 2. XR-S200 Multiplier Section
PHASE COMPARATOR
For phase comparison, a lOW-level reference signal is
normally applied to one input and a high-level reference
or carrier signal to the other input, as in Figure 4. The
signal .may be applied to either the X or Y input, since
the response is symmetrical.
SUPPRESSEO,CARRIER AM
The multiplier generates suppressed-carrier AM signals
when connected as in Figure 6. Again, the symmetrical
response allows the X or Y inputs to be used interchangeably as the carrier or modulation inputs. The X
and Y offset adjustments optimize carrier suppression.
Gain control resistors RX and Ry typically range from 1
KO to 10 KO, depending on input signal amplitudes. The
values shown give approximately 60 dB carrier suppression at 500 kHz and 40 dB at 10 MHz.
If the two inputs, VR(t) and VS(t) are at the same frequency, then the dc voltage at the output of the phase
comparator can be related to the phase angle ef> between the two signals as
Vef> = Kef>cOSef>
where Kef> is the conversion gain in volts per radian (Figure 5). For phase comparator applications, one input is
1-378
XR·S200
DOUBLE·SIDEBAND AM GENERATION
RX
The connection for double-sideband AM generation is
shown in Figure 7. The dc offset adjustment on the
modulation input terminal sets the carrier output level,
while the dc offset of the carrier input governs symmetry of the output waveform. The modulation input can
also be used as a linear gain control (AGe), to control
amplification with respect to the carrier input signals.
-t V
+10V
22
MODULATION
INPUT
BK Ry
8K
ee
10
11
·IOV 0---4----\
XA·S200
MULTIPLIER
SECTION
;;
"
<.::!
Z
0
in
0:
>2
z:'!'
1.0
+lOV
00
U"
ou;
......
12
0:0:
i
I
,,~
..,,>0:0
-lOV
':: 2V'rad
0.1
:;
0
Figure 7. Double Sideband Amplitude Modulation Using
XR·S200 Multiplier Section
u
w
"
11:
0.01
0.1
LOW LEVEL INPUT AMPLITUDE (mV, rmsl
Figure 5. Phase Comparator Conversion Gain Versus Input
Amplitude
R.
+Vcc
OK
q.
OK
+VCC
22
10
11
0
o--i~---t
MODULATION
INPUT
lK
XR-S200
MULTIPLIER
SECTION
lK
Figure 7·1. AM Modulation, 95% AM, Ie = 50 kHz,
1m = 1 kHz
11
Figure 6. Suppressed Carrier Modulation Using XR·S200
Multiplier Section
FREQUENCY DOUBLING
XA S200
MULTIPLIER
Figure 8 shows how to double a sinusoidal input signal
of frequency fs to produce a lOW-distortion sinewave
output of 2f s. Total harmonic distortion is less than
0.6% with an input of 4V, pop, at 10 kHz and an output
of 1V, pop, at 20 kHz. The multiplier's X and Y offsets are
nulled as shown to minimize the output's harmonic
content.
SECTION
IK
+10V
...
100K~...,.._-..,~_.....,.._
10V
SYNCHRONOUS AM DETECTION
75K
Vs
V0
A typical synchronous AM detector is shown in Figure
9. The signal is applied to the multiplier common input
and the X and Y inputs are grounded. Since the Y input
Esslnwst
Eosm2 ...... st
Figure 8. Multiplier Section as Frequency Doubler
1-379
XR·S200
operates at maximum gain with Ry = 0, the detector
gain and demodulated output linearity are determined
by RX. An RX range of 1 KO to 10 KO is recommended
for carrier amplitudes of 100 mV, pop; or greater. The
multiplier output can be low-pass filtered to obtain the
demodulated output. Figure 9-1 shows the carrier and
modulated waveforms for a 30% modulated input signal with a 10 MHz carrier and 1 kHz modulation.
'OOdB~----~----~----~----~----~
~dBr-~--r-----~~
6K
+10V
22
RX
10
11
-~dBL-~~~~~U-~~U-~~~~~~
50
100 Hz
MULTIPLIER
XR-S200
SECTION
1 KHz
10 KHz
100 KHz
FREOUENCY
Figure 10_ Amplifier Section
Freq~ency
1 MHz
lOMHz
Response
XR-S200 OSCILLATOR SECTION
The voltage-controlled oscillator section, (Figure 11) is
an exceptionally versatile design capable of operating
from a fraction of a cycle to in excess of 40 MHz. Frequencies can be selected and controlled by three methods, and used in various combinations for different applications:
Figure 9. Synchronous AM Detector
1. External timing capacitor eO tunes the veo to a center frequency between 0.1 Hz and 40 MHz. The freerunning frequency is inversely proportional to eO.
(see Figure 12)
2. Two digital control inputs allow four discrete frequencies to be selected at any center frequency. The digital inputs convert the logic signal voltages to internal control currents. (see Figure 13)
3. A sweep voltage, applied through a limiting resistor
RS is used for frequency sweeping, on-off keying,
and synchronization of the veo to a sync pulse. (see
Figure 14)
The voltage-to-frequency conversion of the veo section is highly linear. In addition, the conversion gain can
be controlled through the analog control input. Gain is
inversely proportional to Ro. When the digital controls
are also used, gain decreases as the frequency is
stepped up.
Figure 9-1_ Synchronous AM Demodulation
XR-S200 AMPLIFIER SECTION
This multi-purpose function (Figure 10) can be used as
a general-purpose operational amplifier, high-speed
comparator, or sense amplifier. It features an input impedance of 2 megohms, high voltage gain, and a slew
rate of 2.5V/microsecond .. The frequency response
curves for the amplifier section are also shown in Figure 10.
The veo interfaces easily with Eel or TTL logic. It can
be converted to a highly stable crystal-controlled oscillator by simply substituting a crystal in place of the timing capacitor, eO.
Typical performance characteristics of the veo section
are shown in Figures 12, 13, and 14.
1-380
XR·S200
EXPLANATION OF VCO DIGITAL CONTROLS
The VCO frequency is proportional to the total charging
current, IT, applied to the timing capacitor. As shown in
Figure 15, IT is comprised of three separate components: 10, 11, and 12, which are contributed by transistors TO, T 1, and T2, respectively. With pins 15 and 16
open circuited, these currents are interrelated as
OUTPUT
21
FREO. TUNE
ISWEEPIINPUT
Currents 11and 12 can be externally controlled through
pins 16 and 15 respectively. By increasing the dc level
at either of these pins, T1 or T2 can be turned "off" and
11 or 12 can be reduced to zero. With reference to Figure 15, this can be done by applying a 3 volt logic pulse
to these pins, through disconnect diodes D1 and D2. In
this manner, the VCO frequency can be stepped in four
discrete intervals, over a frequency range of 2.5:1, as
shown in Figure 13.
DIGITAL
CONTROL
INPUTS
Figure 11. XR-S2oo Oscillator Section
DIGITAL CONTROL "OFF"
PINS 15 & 16
CONNECTED TO
GROUND THROUGH
lkH
,"
__ DIGITAL CONTROLS "ON"
(51 (loBI Hz
t(J'~
o
~
104
~
8
0:
~
103
a
u
DIGITAL CONTROLS 'OFF'
!2l (10 8 1 HI
lo'-~
FREQUENCY,'o (Hz)
Figure 12. VCO Frequency as a Function of Timing
CapaCitor, Co
10
NEGATIVE
_°
'a
2 ,5
u
:>
8
=
2.0
'0'"
INTERNAL
I 'a
>
1.5
18
20
2.
~ '10
~
I
3.0V
-VEE
12
~-----4---------+-----O0.
DIGITAL INPUT CODE
GRDUND
Figure 15. Explanation of VCO Digital Controls
Figure 13. VCO Digital Tuning Characteristics
1-381
(MOST NEGATIVE
POINTI
XR·S200
TYPICAL APPLICATIONS OF VCO SECTION
FREQUENCY-SELECTIVE FM DEMODULATION
•
•
•
•
•
•
•
•
•
•
For FM demodulation, the PLL connection is used (Figure 17.) The multiplier, with its gain terminals shorted,
serves as the phase detector, and the VCO and filter
govern the operating frequencies.
Voltage/frequency conversion
Phase-locked loops
Frequency synthesis
Signal conditioning
Carrier generation
Synchronization
Sweep and FM generator
Crystal oscillator
Waveform generator
Keyed oscillator
The gain block is used as an audio preamplifier to set
the demodulated output signal level. Volume is controlled by the variable feedback resistor R7. If R6
equals R7, the dc output level will be very close to
ground, for circuit operation with split power supplies.
C3 is the amplifier's compensation capacitor. R8 and
C2 set the output de-emphasis time constant TO, which
is normally 75 /Lsec. for commercial FM applications (fo
= 10.7 MHz).
APPLICATIONS OF THE XR-S200 SYSTEM
PHASE-LOCKED LOOP
FSK DETECTION
A self-contained phase-locked loop is formed by connecting the XR-S200 as outlined in Figure 16.
FSK signals are detected and demodulated with the
PLL connection, as well. It is shown in Figure 18 as a
monolithic MODEM suitable for 8ell103 or 202 type data sets operating at data rates to 1800 baud. An input
frequency shift corresponding to a data bit causes the
multiplier's dc voltage output to reverse polarity. The dc
level is changed to a binary output pulse by the gain
block, connected as a voltage comparator.
In most PLL applications, the amplifier is available for
functions useful outside the loop, since the phase comparator (multiplier section) and VCO provide sufficient
conversion gain. In this case, the amplifier gain does
not enter the PLL gain expression. Assuming unity dc
gain for the filter, the PLL loop gain is KT = K", KO
where K", and KO are the multiplier and VCO conversion
gains, respectively.
VCO
OUTPUT
Rgure 16. XR-S2DO as a Phase· Locked Loop
C,
C.OlJPL INt> CAPAC I TOR
CH
BYPAS~CAPACITOH
Figure 18. FSK Detection
FREQUENCY SYNTHESIZER
Frequency synthesis is performed in Figure 19 by a
phase-locked loop closed with a programmable counter
or digital divide-by-N circuit inserted into the feedback
loop. The VCO frequency is divided by N, so that when
the circuit locks to an input signal at frequency fs, the
Figure 17. Circuit Connection for FM Detection
1·382
XR·S200
oscillator output is Nfs . A large number of discrete frequencies can be synthesized from a given reference
frequency by changing N.
SWEE~
vOLTAGE
INPuT
'NPUT ,]V "",
'~
0,
~
>--+---
1.4 Y
RTRIM = 6 KII
1.0
-Vee = -7.0 V
'H
(STAYS IN ORIGINAL STATE)
OUTPUT
+Vee (VOLTSI
Figure 4. Timing Diagram
Figure 6. VREF VS. + VCC
1-401
XR·9201
DEFINITIONS OF SWITCHING PARAMETERS
Settling Time (t s):
Time required for output to reach
its final value (to within ± .19% of
full scale output) after data is applied to the inputs. Chip enable,
CE, is held "high."
Data Set-Up Time (tsu): Minimum time required for
data to be present at the inputs
while CE is "high", in order to obtain valid output data. It is measured from when proper data is
applied to the inputs to when CE
goes "low".
Data Hole Time (th): Maximum time required for data to
be present at the inputs before CE
goes "low", in order to obtain valid
output data. It is measured from
when the input data changes state
to when CE goes "low", and still
obtain valid output data of the previous input state. Data hold time
indicates that the input data does
not have to be present during the
latter part of the CE high state, and
still have valid output data.
Chip Enable Pulse Width (tw): Minimum pulse width
required for chip enable signal in
order to obtain valid output data.
Propagation Delay Time (td): Time required for output
to reach its final value (50 %) after
CE is applied. It is measured from
the falling edge of the CE pulse to
50% of the output pulse under
minimum data set-up time conditions.
DESCRIPTION OF PIN CONTROLS
VREF (PIN 2):
Internal voltage reference output pro·
vides + 2.00 V Nominal voltage. Can
be used as reference voltage for oth·
er circuitry. Maximum output current
cfability is approximately 9 mA with
V = 5.0 V.
TRIM (PIN 3):
VREF can be adjusted by connecting
a 10 KIl potentiometer between the
trim pin and ground. Temperature stability is optimized for VREF = 2.00 V
to 10-50 ppm/oC.
the D/A converter. Either the internal
VREF (Pin 2) or an external VREF can
be connected to this pin. IREF is approximately equal to VREF/R. Maximum value for IREF is about 1.5 mA
before internal saturation occurs.
-VREF IN (PIN 4): This pin is tied to ground through
a resistor, R, equal in value to that of
Pin 5 and VREF
+VREF IN (PIN 5): Reference voltage is connected
to this pin using a resistor, R, to pro·
vide the reference current, IRE~ for
~ 2.010
~...
~
>
+Vcc
-Vee
To (PIN 6):
Complement output current.
10 (PIN 7):
Output current. The sum of To and 10
is always equal to the full scale output
current (IFS).
CE (PIN 8):
Chip enable pin controls the input data into the internal data latch. The
latch is transparent in the "high"
state.
DBO-DB7 (PIN 10-17): Data input pins. DBO corresponds to the LSB. DB7 corresponds
to the MSB.
+Vcc'" 5.0 V
=5.0 V
= -7.0 V
RTRIM
-Vee = -7.0 V
IREF = 1.000 mA
= 6 KU
2.000
1.990
-25 C
0 C
25C
50-C
1.996-':25:--~-~25"-----:50:------'7=5--'~DO:-----
75'C
AMBIENT TEMPERATURE ( C)
AMBIENT TEMPERATURE (,CI
Figure 7. VREF VS. Temperature
Figure 8. 'FS VS. Temperature
1-402
XR·9201
PRINCIPLES OF OPERATION
Figure 10 shows lhe basic configuration of the XR-9201
D/A converter. The input data bits to the chip can be
latched (stored) in the D/A by controlling the chip enable (CE) pin. When CE is "high" (>2.0 volts), the latch
is transparent and data bits present are passed
through the latch and directly control the D/A converter
switches. When CE is "low" « 0.8 volts), the data bits
within the latch are retained and remain there until CE
goes "high" again. When CE is "low", the data bits at
the inputs are ignored until CE goes "high". This interval latch provides a useful interface with microprocessors.
1.0
+Vcc = 5.0 V
-Vee = -7.0 Y
0.1
The output currents, 10 and 10 , are related to IREF as
follows:
0.01 L-..J!.'--..L....-:-'::c------:--'-:-_ _ _-:::--_ _----'
0.001
0.10
1.00
IREF (mA)
10
b7
b6
b5
b4
b3
b2
b1
2
4
8
16
32
64
128
= 21REF [ - + - + - + - + - + - + -
bO ]
Figura 9. IFS vs. IREF
+-
256
CE
Where: bn
8--BIT DATA
+5 Y
= 1 if Bit N is
= 0 if Bit N is
"High"
"Low"
b7 = MSB (Pin 17)
bO = LSB (Pin 10)
10 is the complement current output of 10, For all possi-
IREF
ble input data combinations,
10 + 10
= IFS = full
where IFS = 2 IREF
I
."":-----:=::-0 10
~------oio
"
scale output current.
L.....j---i~--T-_J
(~;~)
R
The XR-9201 D/A converter contains an internal reference voltage (VREF) with nominal value of 2.00V using
a 6 KG resistor to ground. VREF can be adjusted using
a 10 KG potentiometer tied between Pin 3 and ground.
For maximum temperature stability, VREF should be
set to 2.00V. The maximum output current capability of
VREF is about 9 mA (see Figure 5) and can be used to
provide a reference voltage for other DACs, as well as
other circuitry.
10 Kif
-7 V
RTRIM
-=
Figure 10. Basic Configuration
board layout. Specifically, connection between the current output terminals, 10 and 10 , and the operational
amplifier inputs needs to be as short as possible so as
to minimize capacitance at the node. Oscillations on
the operational amplifier output may result with long
wires. A capacitor in the feedback loop of the operational amplifier can reduce these oscillations.
The reference current (lREF) for the D/A converter is
established by a resistor, R, connected between VREF
and Pin 5 (+ VREF IN), or between an external reference source and Pin 5, and is approximately given as:
ZERO AND FULL SCALE ADJUSTMENTS
Figure 13 shows a circuit for zero and full scale adjustments. It allows tile output voltage to be nulled with
zero scale input conditions (0000,0000). This is done by
shorting out RFB and adjusting the vas adjust potentiometer of the operational amplifier until the output
reads zero volts. This is performed with all digital bits
set to zeros. lITo is the output being used, then all digital bits are set to ones and the zero scale is adjusted.
VREF
IREF = - R
For IREF sImA. The maximum IREF allowed is about
1.5 mA beyond which saturation occurs in the internal
circuitry. To balance the internal operational amplifier, a
resistor equal to R must be placed between Pin 4
(- VREF IN) and ground.
For full scale adjustment, all digital inputs are set to
ones and the IREF potentiometer, from Pin 2 to Pin 5, is
adjusted until the output is at the desired voltage level
(e.g., output is adjusted to 10.000 volts for nominal
9.960 volts output).
NOTE:
When operating the XR-9201 D/A converter with an operational amplifier, care must be taken with the PC
1-403
XR·9201
+5V
+Vcc
+VREF
Jl.JL
16 ,
~
(MSBI
SN
11
..
5
6
7
8
to 11
9
RF
7.'93
15
10
-=
'.BIT
..
9 COUNTEA
I
13
71---------+-1-1-1--+
Vo
12
LSB
lOUT
CE
l
Msa
-=
-15 V
16 ,
17 16 15 '4 13 12 "
11
15
SN
7.. 93
10
XA·9201
10
..
'·BIT
COUNTEA
SKU
tOKU
Vo
AF
-VCC
Cf
= AF (IERRORI
= 10 Kt/
= .01",F
Figure 11. Relative Accuracy Test Circuit
I-BIT DATA
I
,mA'
'REF:::I
EO
2
10
VREF
EO
XR·1I201
3 Kn
FULL
SCALE
ADJUST
ZEAO
SCALE
-VCC ADJUST
0'1- Eo, 10VFORRFB=SKU,IREF,,'mA
IFS • 21IAEF) (255/2$6)
FOR OPERATION WITH NEGATIVE LOGIC OIA CONVERSION, I.E. ZERO FULL SCALE
Figure 13. Full Scale and lero Scale Adjustment
(0000 0000) CORRESPONDING TO FULL SCALE OUTPUT, CONNECT THE INVERTING
INPUT OF OP AMP TO 10 (PIN 5) AND CONNECT 10 (PIN 7) TO GROUND.
Figure 12. Dlgital-to-Analog Conversion: Unipolar Operation
Table 1. Unipolar Operation - Input/Output Relationship
87
86
85
84
83
82
81
80
10 (mA)
1
1
1
1
1
1
1
1
1.992
9.960
LSB
1
1
1
1
1
1
1
0
1.984
9.922
MSB
0
1
1
1
1
1
1
1
0.992
4.961
0
1
0.008
0.039
Positive Full Scale
Pos. Full Scale
-
Zero Full Scale
+ LSB
Pos. Full Scale
0
0
0
0
1·404
0
0
EO (V)
XR·9201
Table 2. Bipolar Operation: Input/Output Relationship
B7
B6
B5
B4
B3
B2
B1
BO
E1 (V)
Full Scale Output
1
1
1
1
1
1
1
1
0.000
EO (V)
10.00
Full Scale - LSB
1
1
1
1
1
1
1
0
0.016
Zero Scale + MSB
1
0
0
0
0
0
0
0
1.984
9.921
0.Q78
Full Scale - MSB
0
1
1
1
1
1
1
1
2.000
0.000
Zero Scale + LSB
0
0
0
0
0
0
0
1
3.968
-9.844
Zero Scale
0
0
0
0
0
0
0
0
3.984
-9.922
.001 JJF
BIPOLAR OUTPUT OPERATION
,F
Figure 14 shows a basic bipolar output operation. For
full scale input (1111,1111) the output voltage is equal
to 1.0V. For zero scale input (0000,0000), output voltage
is equal to - 1.0V. Due to the internal circuitry of the
XR-9201, the current output terminals should not be
pulled below approximately - 1.0 volt. Therefore the cir·
cuit shown in Figure 14 would not function for Eo less
than - 1.0V. For bipolar operation with larger output
voltages, the circuit shown in Figure 15 is recommended. Note that the current outputs, 10 and To, are
held at zero volts for all digital inputs for greater accuracy.
.E.7~F~
+5 V
+VIN o---~'4
.001,.F
RO = 17.5 KII
ADJUST RO FOR - YOUT = -7 V
RA=50KlI
ADJUST RA FOR +VOUT = +5 V
Figure 15. Digital-to-Analog Conversion - Bipolar Operation
8-811 DATA
8·81T DATA
VREF
IREF =
0.5 mA
E,
I
~ ~-r---------'
IREF
-1.0Y· EO' 1.0V
IE: 2(IREF) (RF)' 1.0 VOLT
Figure '14. Digital-to-Analog Conversion - Bipolar Operation
EO
=,* (VREF - E1 )
VREF
= 2 Y. R = 2 K. RFO "" 2 K. R2
= 50 K. Rt = 10 K
NOTE: (I + IREF) MUST BE LESS THAN 6 rnA FOR PROPER OPERATION.
Figure 16. Regulated Supplies for XR-9201
1-405
XR·4151
Voltage-to- Frequency Converter
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-4151 is a device designed to provide a simple,
low-cost method for converting a DC voltage into a proportional pulse repetition frequency. It is also capable
of converting an input frequency into a proportional
output voltage. The XR-4151 is useful in a wide range of
applications including AID and D/A conversion and data transmission.
CURRENT
SOURCE OUTPUT
FEATURES
Single Supply Operation ( - BV to + 22V)
Pulse Output Compatible With All Logic Forms
Programmable Scale Factor (K)
Linearity ± 0.05 % Typical-Precision Mode
Temperature Stability ± 100% ppm/oC Typical
High Noise Rejection
Inherent Monotonicity
Easily Transmittable Output
Simple Full Scale Trim
Single-Ended Input, Referenced to Ground
Also Provides Frequency-to-Voltage Conversion
Direct Replacement for RC/RV/RM-4151
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-4151P
XR-4151CP
Plastic
Plastic
-40°C to +B5°C
DoC to + 70°C
APPLICATIONS
Voltage-to-Frequency Conversion
AID and D/A Conversion
Data Transmission
Frequency-to-Voltage Conversion
Transducer Interface
System Isolation
SYSTEM DESCRIPTION
The XR-4151 is a precision voltage to frequency convertor featuring 0.05% conversion linearity, high noise
rejection, monotonicity, and single supply operation
from BV to 22V. An RC network on Pin 5 sets the maximum full scale frequency. Input voltage on Pin 7 is
compared with the voltage on Pin 6 (which is generally
controlled by the current source output, Pin 1). Frequency output is proportioned to the voltage on Pin 7.
The current source is controlled by the resistance on
Pin 2 (nominally 14kll) with 1 = 1.9 VIR. The output is
an open collector at Pin 3.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Output Sink Current
Internal Power Dissipation
Input Voltage
Output Short Circuit to Ground
22V
20 mA
500mW
- 0.2V to + VCC
Continuous
1-406
XR~4151
ELECTRICAL CHARACTERISTICS
Test Conditions: (VCC
= 15V, TA =
+ 25 DC, unless otherwise specified)
MIN
LIMITS
TYP
MAX
UNITS
CONDITIONS
2.0
2.0
3.5
4.5
6.0
7.5
mA
mA
8V VI. When this condition is achieved,
the current source remains off and the voltage VB decays until VB is again equal to VI. This completes one
cycle. The VFC will now run in a steady state mode. The
current source dumps lumps of charge into the capacitor CB at a rate fast enough to keep VB ~ VI. Since the
discharge rate of capacitor CB is proportional to VB/
RB, the frequency at which the system runs will be proportional to the input Voltage.
SINGLE SUPPLY MODE VOLTAGE-TO-FREQUENCY CONVERTER
In this application, the XR-4151 functions as a standalone voltage-to-frequency converter operating on a
Single positive power supply. Refer to the functional
block diagram and Figure 3, the circuit connection for
single supply voltage-to-frequency conversion. The XR4151 contains a voltage comparator, a one-shot, and a
precision switched current source. The voltage comparator compares a positive input voltage applied at pin
7 to the voltage at pin 6. If the input voltage is higher,
the comparator will fire the one·shot. The output of the
one-shot is connected to both the logic output and the
precision switched current source. During the one-shot
period, T, the logic output will go low and the current
source will turn on with current I. At the end of the one
shot period the logic output will go high and the current
source will shut off. At this time the current source has
injected an amount of charge Q = lOT into the network
RB-CB. If this charge has not increased the voltage VB
such that VB > V" the comparator again fires the oneshot and the current source injects another lump of
AI
1001(11
5.1K"
1.lIl..J
'---I t--
fO· KV,. WHERE It-ll..... ::AoCO
Figure 3. VOltage-to-Frequency Converter
1-407
~
XR·4151
TYPICAL APPLICATIONS
op-amp prevents the voltage at pin 7 of the XR-4151
from going below O. Use a low-leakage diode here,
since any leakage will degrade the accuracy. This circuit can be operated from a single positive supply if an
XR-3403 ground-sensing op-amp is used for the integrator. In this case, the diode can be left out. Note that
even though the circuit itself will operate from a single
supply, the input voltage is necessarily negative. For
operation above 10kHz, bypass pin 6 of the XR-4151
with .01,.F.
SINGLE SUPPLY VOLTAGE-TO-FREQUENCY CONVERTER
Figure 3 shows the simplest type of VFC that can be
made with the XR-4151. The input voltage range is from
o to + 10V and the output frequency is from 0 to 10
kHz. The f~1I scale frequency can be tuned by adjusting
RS, the output current set resistor. This circui~ has the
advantage of being simple and low in cost, but It suffers
from inaccuracy due to a number of error sources. linearity error is typically 1 %. A frequency offset will also
be Introduced by the input comparator offset voltage.
Also, response time for this circuit is limited by the passive integration network RB CB. For the component values shown in Figure 3, response time for a step change
input from 0 to + 10V will be 135 msec. For applications
which require fast response time and high accuracy,
use the circuit of Figure 4.
FREQUENCY-TO-VOLTAGE CONVERSION
The XR-4151 can be used as a frequency-to-voltage
converter. Figure 5 shows. the single-supply FVC configuration. With no signal applied, the resistor bias networks tied to pins 6 and 7 hold the input comparator in
the off state. A negative going pulse applied to pin 6 (or
positive pulse to pin 7) will cause the comparator to fire
the one-shot. For proper operation, the pulse width
must be less than the period of the one-shot, T = 1.1
RO CO. For a 5V pop square-wave input the differentiator network formed by the input coupling capacitor and
the resistor bias network will provide pulses which correctly trigger the one-shot. An external voltage comparator can be used to "square-up" sinusoidal input Signals before they are applied to the XR-4151. Also, the
component values for the input signal differentiator and
bias network can be altered to accommodate square
waves with different amplitudes and frequencies. The
passive integrator network RB CB filters the current
pulses from the pin 1 output. For less output ripple, increase the value of CB.
PRECISION VOLTAGE-TO-FREQUENCY CONVERTER
In this application (Figure 4) the XR-4151 is used with
an operational amplifier integrator to provide typical linearity of 0.05% over the range of 0 to -10V. Offset is
adjustable to zero. Unlike many VFC designs which
lose linearity below 10mV, this circuit retains linearity
over the full range of input voltage, all the way to OV.
Trim the full scale adjust pot at VI = -10V for an output
frequency of 10kHz. The offset adjust pot should be set
for 10Hz with an input voltage of -10mV.
The operational amplifier integrator improves linearity
of this circuit over that of Figure 3 by holding the output
of the source, Pin 1, at a 90nstant OV. Therefore, the linearity error due to the current source output conductance is eliminated. The diode connected around the
For increased accuracy and linearity, use an operational amplifier integrator as shown in Figure 6, the precision FVC configuration. Trim the offset to give -10mV
out with 10Hz in and trim the full scale adjust for -1 OV
out with 10kHz in. Input Signal conditioning for this circuit is necessary just as for the single supply mode and
the scale factor can be programmed by the choice of
component values. A tradeoff exists between the
amount of output ripple and the response time, through
the choice or integration capacitor CI. If CI = 0.1 ,.f the
ripple will be about 100mV. Response time constant TR
= RB CI. For RB = 100 kO and CI = 0.1 ,.f, TR =
10msec.
.,
Yo VOLTAGE OUTJI'UT
fREQUENCV INI'UT
TO laY
LJ'1J'L
5 V .... SQUARE""YE
Y.. ·11V
RQUKn
10KU
DESIGN EOUATIONS:
AI
~~,::~K WHEREK·OAII ~
Figure 4. Precision VOHage-to-Frequency Converter
HZ
_._
Figure 5. Frequency-to-Voltage Converter
1-408
XR·4151
PRECAUTIONS
2. Set T = 1.1 ROCO = 0.75[1/fo] where fo is the de·
sired full scale frequency. For optimum performance
make 6.8kO >RO >680kO and O.OOl/Lf ""-"""",_-+--O VOLTAGE OUTPUT
too..
-'OY" Yo, a
~
5. For the FVC's, pick the value of Cs or CI to give the
optimum tradeoff between the response time and
output ripple for the particular application.
I FREQUENCY INPUT
CK. 'I"; 10kHr
Ii Yp-p SOUAAEWAVE
DESIGN EXAMPLE
Y+ -'IV
.022,.F
I. Design a precision VFC (from Figure 5) with fo
100kHz and Via = -10V.
101C1I
1. Set RS = 14.0kO
S.t""
fto i.lten
to
ItO
2. T = 0.75 [1jl05] = 7.5/Lsec
10
KO
= 6.8kO and Co = 0.001/L1.
Let RO
=5
3. CI
Figure 6. Precision Frequency-to-Voltage Converter
x 105 [1110 5]
= 500pl.
Op-amp slew rate must be at least
PROGRAMMING THE XR-4151
SR
=
135 x 106 [1/500pf]
4. RS
=
10V/l00/LA
= 100kO.
II. Design a precision VFC with fo
10V.
The XR-4151 can be programmed to operate with a full
scale frequency anywhere from 1.0Hz to 100kHz. In the
case of the VFC configuration, nearly any full scale in·
put voltage from 1.0V and up can be tolerated if proper
scaling is employed. Here is how to determine compo·
nent values for any desired full scale frequency.
= 0.27V//Lsec
=
1Hz and Via
1. Let RS = 14.0kQ
2. T
= 0.75 [1/1] = 0.75 sec
Let RO = 680kO and Co = 1.0/Lf.
1. Set RS = 14kO or use a 12k resistor and 5k pot as
shown in the figures. (The only exception to this is
Figure 4.)
3. CI
=5
x 10- 5 [1/1]F
4. RS = 100kQ.
1-409
= 50/Lf.
=
XR·4151
III. Design a single supply FVC to operate with a supply
voltage of 9V and full scale input frequency fo =
83.3 Hz. The output voltage must reach at least
0.63 of its final value in 200msec. Determine the
oUtPUI ripple.
4. RS = 5V/100/LA = 50kO.
5. Output response time constant is TR :;; 200
msec
Therefore-
= (200
1. Set RS = 14.0kO
Cs :;; TR/RS
2. T = 0.75 [1/83.3] = 9msec
Worst case ripple voltage is
Let RO
= 82kO and Co = 0.1
/Lf.
3. Since this FVC must operate from B.OV, we shall
make the full scale output voltage at pin 6 equal
to 5.0V.
EQUIVALENT SCHEMATIC DIAGRAM
1-410
x 10 - 3)/(50 x 103)
= 4/Lf
XR·7000
ADVANCE INFORMATION
Log Vide«J)
Amp~nfnelt"
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-7000 is a universal logarithmic video amplifier
chip. Because of its extremely wide bandwidth, it can
be used in systems ranging from audio applications to
radar subsystems. The XR-7000 utilizes seven separate
precision logarithmic elements. These elements may
be used separately for small dynamic ranges or cascaded to offer an extremely wide dynamic range of operation.
The XR-7000 has an internal band-gap voltage reference, a differential video summing amplifier, and a precision die temperature sensor, to aid in its system interfacing. Also included are internal power supply regulators to provide excellent power supply rejection.
The XR-7000 is available in a 40-Pin ceramic or plastic
package. It is designed to operate from dual 11 to 15
volt power supplies
FEATURES
Seven Uncommitted Logging Elements
Internal Band-Gap Voltage Reference
Dual Tracking Regulators On-Board
Precision Die Temperature Sensor
ORDERING INFORMATION
APPLICATIONS
Receiver Subsystems
Radar Subsystems
Spectrum Analyzers
Power Meters
Test Equipment
Video Cartridge Tape Recorders
Audio Tape Recorders
Smoke Detectors
Chemical Process Systems
Ultrasonic Imaging
Medical Equipment (Tomography)
Package
Operating Temperature
Ceramic
Plastic
- 55°C to + 125°C
DOC to +70°C
SYSTEM DESCRIPTION
30V
1.0W
5 mW/oC
The main section of the XR-7000 comprises seven logarithmic sections. Each section has a dynamic range of
approximately 12 dBV. For wide range applications, the
seven sections may be cascaded to provide a total dynamic range of over 90 dBV. The logarithmic sections
provide current outputs, which can be summed and
converted to voltages, using the on-board summing
amplifiers. A unipolar output with built-in offset is also
available for use with an external I to V converter.
-55°C to + 125°C
O°C to + 70 0 e
VCC + .5V to VEE - .5V
The precisi~n die temperature sensor is useful in dccoupled applications to provide stability over its temperature range.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Derate Above at 25°C
Operating Temperature
Ceramic
Plastic
Any Input Voltage
Part Number
XR-7000M
XR-7000CP
1-411
XR·7000
ELECTRICAL CHARACTERISTICS
Tast Conditions: With VCC = + 12V, VEE + -12V, TAMB = 25°C, dual polarity output load resistances =
100 ohms, unipolar internal load resistance = 200 ohms, unless specified otherwise.
SYMBOL
PARAMETERS
MIN
TYP
MAX
UNIT
Vcc
Vee
Icc
lee
+Vout
Positive Supply Voltage
Positive Supply Voltage
Positive Supply Current
Negative Supply Current
Positive Regulator
Output Voltage
Negative Regulator
Output Voltage
11
11
12
12
15
15
15
15
V
V
mA
mA
5.8
6.0
6.2
V
Reference Untrimmed
-5.8
-6.0
-6.2
V
Reference Untrimmed
-Vout
CONDITIONS
LOG SECTION
LG
BW
Tr
Tpd
Trec
lin
PSRR
VTRAC
Ttcv
Vout
Vout
Rout
Nout
Log Range per Element
Bandwidth
Risetime
Prop. Delay
Saturation Recovery
Input Bias Current .
Power Supply Rejection
Ratio
Tracking of Regulators
Output Tempco
Output Voltage
per Stage
Output Voltage
per Stage
Unipolar Output
Resistance
Output Noise
14
6
60
150
12
30
12
10
20
2
65
25
12
dB
MHz
ns
ns
ns
Dual Polarity Output
100n Diff. Load
10% Points
pA
dBV
DC to 100 MHz
20
50
118
ppm
ppm
mV
Trimmed
Unipolar
120
mV
Bipolar each Output
200
100
1·412
250
ohms
/LVrms
Unipolar connection
XR·2216
Monolithic Compandor
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTlDN
The XR-2216 is a monolithic audio frequency compandor designed to compress or expand the dynamic
range of speech or other analog signals transmitted
through telecommunication systems. The monolithic
circuit can be connected as either a compressor or an
expander, the choice being determined by the external
circuitry.
AMPLIFIER
COMPENSATION
AMPLIFIER
OUTPUT
REFERENCE
LEVEL
SCALE SET
FILTER
LOW LEVEL
TRACKING
TRIM
FEATURES
Functions as either a Compressor or an Expander
Wide Dynamic Range: 60 dB
Wide Supply Range: 6 to 20 Volts
Excellent Transfer Function Tracking
Low Power Supply Drain
Controlled Attack and Release Times
Low Noise and Low Distortion
AC/DC
CONVERTER
INPUT
EXPANDER
INPUT
ORDERING INFORMATION
APPLICATIONS
Telephone Trunk-Line Compandor
Speech/Data Compression and Expansion
Telecommunication Systems
Mobile Communications
Model Data Processing
Part Number
Package
(16 Pin DIP)
XR-2216CN
XR-2216CP
Ceramic
Plastic
Operating Temperature
- 40°C to + 60°C
- 40°C to + 60°C
SYSTEM DESCRIPTION
20V
The XR-2216 is comprised of four basic blocks: (1) an
internal voltage reference; (2) an AC/DC converter
which converts AC signal input to a DC current level;
(3) an impedance converter whose impedance level is
a function of a DC control signal; and (4) a high gain operational amplifier.
750 mW
6 mW/oC
625 mW
5 mW/oC
- 60°C to + 150°C
The XR-2216 is designed to accommodate a wide
range of system configurations. It can be operated with
positive or negative single supply systems, or dual
power supplies over a power supply range of 6 volts to
20 volts.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Power Dissipation
Ceramic Package
Derate above +25°C
Plastic Package
Derate above + 25°C
Storage Temperature
1-413
XR·2216
ELECTRICAL CHARACTERISTICS
Test CondHlons: Vc = + 12V, TA
= 25°C
COMPANOOR
MAX
UNITS
Power Supply Voltage
PARAMETERS
6
20
VDC
Nominal Power Supply Voltage
12
18
VDC
3
mA
+1
dB
MIN
TYP
Power Supply Current, No Signal Input
Gain Change Over Frequency Tolerance
-1
Distortion Measured at -4 dB'
Input Level at 1 KHz
CONOITIONS
300 - 3500 Hz
% THD
3
Attack Time Measured at -10 dB
Input Level
5
ms
To 90% of Final Value
Decay Time Measured at - 10 dB
Input Level
5
ms
To 10% of Final Value
7.5
3.5
+1.5
Transfer Characteristics"
Compandor Output With Input Levels of:
-4 dB
-8dB
-10 dB
-14 dB (reference)
-24 dB
-34 dB
-44 dB
-54 dB
-64 dB
3.5
-0.5
-1.5
-15.5
-25.5
-36.5
-49
-59
+6
+2
0
-4
-14
-24
-34
-44
-54
-12.5
-22.5
-32.5
-42.5
-52.5
dB
dB
dB
dB
dB
dB
dB
dB
dB
MIN
TYP
MAX
UNITS
COMPRESSOR
PARAMETERS
Input Impedance
50
Output Impedance
50
Output Signal Level for - 10 dB
Input at 1 KHz
Output Voltage Swing
-10
Output Noise, Input AC Grounded
ohm
dB
dB
0
30
Compressor Transfer Characteristics"
Compressor Output With Input Levels of:
-4 dB
-8 dB
-10 dB
-14 dB(reference)
-24 dB
-34 dB
-44 dB
-54 dB
-64 dB
CONOITIONS
Kohm
-7
-9
-10
-12
dBrnc
dB
dB
dB
dB
dB
dB
dB
dB
dB
-17
-22
-27
-32
-37
EXPANOER
PARAMETERS
Input Impedance
MIN
TYP
50
Output Signal Level for -10 dB
0
Output Noise Input AC Grounded
Notes: '0 dB
=
0.775 Vrms (1 mW across 600 ohm load)
+5
-7
-9
-10
-12
-17
-22
-27
-32
-37
ohm
dB
+8
Expander Transfer Characteristics"
Expander Input Levels Required for
Output of:
+6dB
+2 dB
o dB
- 4 dB(reference)
-14 dB
-24 dB
-34 dB
-44 dB
-55 dB
UNITS
Kohm
Output Impedance
Output Voltage Swing
MAX
50
dB
dBrnc
dB
dB
dB
dB
dB
dB
dB
dB
dB
"Recommended transfer characteristics.
1-414
CONOITIONS
XR·2216
EQUIVALENT SCHEMATIC DIAGRAM
9
CIRCUIT DESCRIPTION
The analog signal compressor/expander or "compandor" circuits are among the most fundamental building
blocks in telecommunication systems. These circuits
are intended to compress or expand the dynamic range
of speech or other analog signals transmitted through
telecommunication systems.
system is comprised of four basic blocks: (1) an internal
voltage reference; (2) an ac/dc converter which converts ac signal input to a dc current level; (3) an impedance converter whose impedance level is a function of
a dc control signal; and (4) a high gain operational amplifier.
Figure 1 shows the simplified block diagram of a typical
speech transmission system, using the compression/
expansion or "companding" technique. The dynamic
range of the input signal is first compressed at the
transmitting end; then transmitted through the system,
and finally expanded back to the original amplitude at
the receiving end. Thus, the "compressor" and the "expander" sections of a compandor system perform reciprocal functions. In a bi-directional transmission system, there is a compandor at each end of the line which
compresses the out-going signal, or expands the incoming signal by an equal amount.
The XR-2216 is designed to accommodate a wide
range of system configurations It can be operated with
positive, or negative, single-supply systems, or with balanced power supplies, over a power supply range of
6 volts to 20 volts.
Some of its key features are: low external component
count, excellent transfer function, tracking, low power
supply drain, controlled attack and release times, low
noise and low distortion.
EXPANDER (Figure 3)
Figure 3 shows the external circuit connections and
components necessary to operate XR-2216 as an expander. An input signal is applied to Pin 7 which is the
Figure 2 shows the typical transfer characteristics of
compressor and expander circuits commonly used in
telecommunication systems. In the compressor, the
output amplitude varies 1 dB for every 2 dB change of
input amplitude; the reverse is true for the expander.
AC/DC converter input. The AC/DC converter converts
the AC signal input to a dc current level which in turn
controls the transconductance of the impedance converter. Part of the input signal is applied to the impedance converter by connecting Pins 8 and 10. Thus the
signal current at Pin 11is proportional to the product of
the input Signal and its average value.
The functional block diagram of XR-2216 compandor is
shown on Page 1, in terms of the monolithic circuit
package. The XR-2216 is designed to be connected as
either a compressor or an expander, the choice being
determined by the external circuitry. The monolithic
INT
J-.
SIGNAL
COMPRESSOR
~
TRANSMISSION
SYSTEM
SIGNAL
EXPANDOR
16°on
Figure 1. Simplified Block Diagram of a Speech Transmission System Using Companding Technique
1-415
H
XR·2216
The output signal current is then fed to the operational
amplifier by connecting Pins 11 and 16, and the output
signal voltage is directly proportional to the signal current flowing into Pin 16. The output signal of the expander is available at Pin 2. In this operation, the reference level is set by the trim pot Rl, and the trim pot R2
provides a means for trimming low level tracking.
l/
-'0
./
-20
COMPRES/
-30
;I'
In the connection of Figure 3, the input signals of - 37
dBm to - 7 dBm are expanded to 60 dB output range
with up to 0 dBm power matched output to 6000 load.
./
I
II
./
-40
I
-50
COMPRESSOR (Figure 4)
f
/
E,XPANP ER
-60
-80 -70 -60
Figure 4 shows the typical circuit connection for compressor operation. It is just a non-inverting voltage amplifier whose input level is proportional to the product of
the incoming signal and the impedance of the impedance converter which is inversely proportional to the
amplifier output. Consequently, the output signal at Pin
2 is proportional to square root of the input signal.
50 -40
-30
-20
-10
0
INPUT IdBml
Figure 2. Transfer Characteristics of Compressor a
Expander Circuits
EXPANDER
OUTPUT
In this operation, just like expander operation, the reference level is set by the trim pot R1 and low level tracking is adjusted by the trim pot R2. In the connection of
Figure 4, the output change is 1 dB for 2 dB change at
input. The output range can be adjusted to - 37 dBm to
- 7 dBm for input signals of 60 dB dynamic range.
Note: Attack and Decay Times:
The speed with which gain changes to follow changes
in input signal levels is determined by the capacitor Cl
and the resistor R1. A small capaCitor will yield rapid response but will not fully filter low frequency signals. Any
ripple on the gain control signal will modulate the signal
passing through the impedance converter. In an expander and compressor application, this would lead to
a 3rd harmonic distortion, so there is a tradeoff to be
made between fast attack and decay times, and distortion.
Agure 3. External Connections for Operation Expander
COMPRESSOR
OUTPUT
Figure 4. External Connections for Compressor Operation
TYPICAL PERFORMANCE CURVES
'2
Tf"60~
~
1
v;V
\
TA"'
""
....
15~C
-;:--:"'25"C
A
I
!8
+1
r--t-t--t-::t:~=;;t:::-i
~
~
~
300
r--..
200
'00
10
'00
'K
FREQUENCY CHzl
FBi ,O K
'OK
TYPICAL CIRCUIT CONNECTION
+15V
D.Olj.lF
~
10K
INPUT o-~--"M,...---.-----~:r,
390
'.'
UK
' - -_ _'"'OUTPUT
'OK
_TSY
O.OOljlF
UNITY GAIN FOLLOWER
CIRCUIT DESCRIPTION
approaches unity and the Taylor series of the 1n function can be approximated as:
The differential transistor pair Q4 and Q5 form a transconductance stage in that the ratio of their collector
currents is defined by the differential input voltage according to the transfer function:
VIN = KT 1n!.§
q
14
KT 1n!.§ "" ~ 15- 14
q
14
q
14
14"" 15 ""
(1)
~2
VIN [ (IB)(q)] = 15 -14
2KT
where VIN is the differential input voltage, KT/q is approximately 26 mV at 25° C and 15 and 14 are the collector currents of transistors Q5 and Q4 respectively. With
the exception of Q3 and Q13, all transistors and diodes
are identical in size. Transistors Q1 and Q2 with Diode
D1 form a current mirror which forces the sum of currents 14 and 15 to equal 18;
(4)
Collector currents 14 and 15 are not very useful by themselves and it is necessary to subtract one current from
the other. The remaining transistors and diodes form
three current mirrors that produce an output current
equal to 15 minus 14 thus:
(2)
VIN [(lB)(q)] = lOUT
2KT
where 18 is the amplifier bias current applied to the gain
pin.
(5)
The term in brackets is then the transconductance of
the amplifier and is proportional to lB.
For small differential input voltages the ratio of 14 and 15
1-420
LINEARIZING DIODES
APPLICATIONS
For differential voltages greater than a few millivolts,
Equation 3 is no longer accurate, and the transconductance becomes increasingly nonlinear. Figure 1 demonstrates how the internal diodes can linearize the transfer function of the amplifier. For convenience assume
the diodes are biased with current sources and the input signal is the form of current IS. Since the sum of 14
and 15 is IB and the difference is lOUr. currents 14 and
15 can be written as follows:
VOLTAGE CONTROLLED AMPLIFIERS (VCA)
Figure 2 shows how the linearizing diodes can be used
in a voltage controlled amplifier. To understand the input biasing, it is best to consider the 13 KG resistor as a
current source and use a Therenin equivalent circuit as
shown in Figure 3. This circuit is similar to Figure 1 and
operates the same. The potentiometer in Figure 2 is adjusted to minimize the effects of the control signal at
the output.
>0'
~-'VVIr---o ~~~~ROl
-
IOUT·21$
+ ,.
I'D
('.)
R.
13.
RA
t-----Q-I
,..
OUTPUT
RIN
-VI
-vs
VIN
INPUT
Figure 2. Voltage Controlled Amplifier (VCA) Clrcuil
Figure 1. linearizing Diodes
Since the diodes and the input transistors have identical geometries and are subject to similar voltages and
temperatures, the following is true:
!.a
10 + IS
+ lout
2 _ _ = KT 1n_
2_ _2_
KT 1n_
10 _ IS
q
lout
q
2
2
2
!.a _
:_ lout
=
IS
(3.!a)
10
for \IS \
<.!Q.
RTH
tiS
(6)
2
Figure 3. Equivalent VCA Input Circuit
Notice that in deriving Equation 6, no approximations
have been made and there are no temperature dependent terms. The limitations are that the signal current
not exceed 10/2 and that the diodes be biased with currents. In practice, replacing the current sources with
resistors will generate insignificant errors.
For optimum signal-to'noise performance, IB should be
as large as possible as shown by the Output Voltage vs.
Amplifier Bias Current graph. Larger amplitudes of input signal also improve the SIN ratio. The linearizing diodes help here by allowing larger input signals for the
same output distortion as shown by the Oistortion vs.
Oifferential Input voltage graph. SIN may be optimized
by adjusting the magnitude of the input signal via RIN
(Figure 2) until the output distortion is below some desired level. The output voltage swing can then be set at
any level by selecting RL.
CONTROLLED IMPEDANCE BUFFERS
The upper limit of transconductance is defined by the
maximum value of IB (2 mAl. The lowest value of IB for
which the amplifier will function therefore determines
the overall dynamic range. At very low values of IB, a
buffer which has very low input bias current is desirable. A FET follower satisfies the low input current requirement, but is some what non-linear for large voltage
wing. The controlled impedance buffer is a Oarlington
which modifies its input bias current to suit the need.
For low values of IB' the buffer's input current is minimal. At higher levels of IB, transistor Q3 biases up to
Q12 with a current proportional to IB for fast slew rate.
Although the noise contribution of the linearizing diodes
is negligible relative to the contribution of the amplifier's internal transistors, 10 should be as large as possible. This minimizes the dynamic junction resistance of
the diodes (re) and maximizes their linearizing action
when balanced against RIN. A value of 1 mA is recommended for 10 unless the specific application demands
otherwise.
1-421
XR·13600
STEREO VOLUME CONTROL
"
RC
The circuit of Figure 4 uses the excellent matching of
the two XR-13600 amplifiers to provide a Stereo Volume Control with a typical channel-to-channel gain
tracking of 0.3 dB. Rp is provided to minimize the output offset voltage and may be replaced with two 5100
resistors in AC-coupled applications. For the component values given, amplifier gain is derived from Figure
2 as being:
1'0
Vos
VIN,
CARRIER
~
,..
v,
,..
Va = 940xIB(mA)
VIN
Figure 5. Amplitude Modulator
30.
'0'
v,.
VO,
30K
VcO-~VV------------------~
RC
OUTPUT
'OK
AMPLITUDE
Figure 6. Four-Quadrant Multiplier
V02
,..
Figure 4. Stereo Volume Control
If Vc is derived from a second signal source then the
circuit becomes an amplitude modulator or twoquadrant multiplier as shown in Figure 5, where:
10
= - 21S (IB) = - 21S
10
10
VIN2 _ 3.!§. (V = l.4V)
RC
10
RC
Figure 7. AGC Amplifier
VOLTAGE CONTROLLEO RESISTORS (VCR)
The constant term in the above equation may be cancelled by feeding IS x IORct2(V + 1.4 V) into 10. The
circuit of Figure 6 adds RM to provide this current, resulting in a four-quadrant multiplier where RC is
trimmed such that Va = OV for VIN2 = OV. RM also
serves as the load resistor for 10.
An Operational Transconductance Amplifier (OTA) may
be used to implement a Voltage Controlled Resistor as
shown in Figure 8. A signal voltage applied at RX generates a VIN to the XR-13600 which is then multiplied by
the gm of the amplifier to produce an output current,
thus:
Noting that the gain of the XR-13600 amplifier of Figure
3 may be controlled by varying the linearizing diode
current 10 as well as by varying IB, Figure 7 shows an
AGC Amplifier using this approach. As Va reaches a
high enough amplitude (3VBE) to turn on the Darlington
transistors and the linearizing diodes, the increase in
10 reduces the amplifier gain so as to hold Va at that
level.
RX = R + RA
gmRA
where gm '" 19.2 IB at 25°C. Note that the attenuation
of Va by Rand RA is necessary to maintain VIN within
the linear range of the XR-13600 input.
1-422
XR·13600
JO'
Q---'Vv'v---oVc
20011
Vo
RA
200U
Figure 11. Voltage Controlled Low-Pass Filter
Figure 8. Voltage Controlled Resistor, Single-Ended
Figure 12 shows a voltage controlled high-pass filter
which operates in much the same manner, providing a
single RC roll-off below the defined cut-off frequency.
Figure 9 shows a similar VCR where the linearizing di·
odes are added, essentially improving the nose per·
formance of the resistor. A floating VCR is shown in Fig·
ure 10, where each "end" of the "resistor" may be at
any voltage within the output voltage range of the XR13600.
10'
:>--'V'.tv--"T"--o-j
vo. )
( NULL
Vo
30'
-15V
Figure 12. Voltage Controlled High-Pass Filter
Additional amplifiers may be used to implement higher
order fillers as demonstrated by the two-pole Butterworth lowpass filter of Figure 13 and the state variable filter of Figure 14. Due to the excellent gm tracking
of the two amplifiers and the varied bias of the buffer
Darlingtons, these filters perform well over several decades of frequency.
Figure 9. Voltage Controlled Resistor with Linearizing Diodes
Vc
V'N
_1SV
' - - - - - - 0 Rx· !:RA 0 - - - - - - - - 1
Figure 10. Floallng Voltage Controlled Resistor
VOLTAGE CONTROLLED FILTERS
Figure 13. Voltage Controlled 2-Pole Butterworth Low-Pass
Filter
OTA's are extremely useful for implementing voltage
controlled filters, with the XR-13600 having the advan·
tage that the required buffers are included on the I.C.
The VC La-Pass Filter of Figure 11 performs as a unitygain buffer amplifier at frequencies below cut-off, with
the cut-off frequency being the point at which XcJgm
equals the closed-loop gain of (R/RA). At frequencies
above cut-off the circuit provides a single RC roll-off (6
dB per octave) of the input signal amplitude with a - 3
dB point defined by the given equation, where gm is
again 19.2 x IB at room temperature.
VOLTAGE CONTROLLED OSCILLATORS (VCD)
The classic Triangular/Square Wave VCO of Figure 15 is
one of a variety of Voltage Controlled Oscillators which
may be built utilizing the XR-13600. With the component values shown, this oscillator provides signals from
200 kHz to below 2 Hz as IC is varied from 1mA to
10nA. The output amplitudes are set by IA x RA. Note
that the peak differential input voltage must be less
than 5 volts to prevent zenering the inputs.
1-423
XR·13600
360 0 or 180 0 for the inverter and 60 0 per filter stage.
This veo operates from 5 Hz to 50 kHz with less than
1% THD.
V,N
Q - - - , - ; - - - - - - Q -......IVV--Ovc
LO-PASS
OUT
1<
"'<
BANDPASS OUT
Figure 14. Voltage Controlled State Variable Filter
Vc
Figure 17. Sinusoidal VCO Using Two XR-13600 Circuits
Figure 18 shows how to build a VCO using one amplifier
when the other amplifier is needed for another function.
Figure 15. Triangular/Square-Wave VCO
'OK
R,
3DK
Q--.J\IVV-+-oVc
A few modifications to this circuit produce the ramp/
pulse VCO of Figure 16. When V02 is high, IF is added
to IC to increase amplifier A1's bias current and thus to
increase the charging rate of capacitor C. When V02 is
low, IF goes to zero and the capacitor discharge cur·
rent is set by Ie.
Vo
-15V
Figure 18. Single Amplifier VCO
ADDITIONAL APPLICATIONS
VPK
L -_ _ _ _ _ _ _ _
lOOK
-+_-J~~~
RI
~
!V+-.8VIAZ
R;"iFi2
Figure 19 presents an interesting one-shot which draws
no power supply current until it is triggered. A positivegoing trigger pulse of at least 2V amplitude turns on the
amplifier through RS and pulls the non-inverting input
high. The amplifier regenerates and latches it output
high until capacitor C charges to the voltage level on
the non-inverting input. The output then switches low,
turning off the amplifier and discharging the capacitor.
The capacitor discharge rate is speeded up by shorting
the diode bias pin to the inverting input so that an additional discharge current flows through D1 when the amplifier output switches low. A special feature of this timer is that the other amplifier, when biased from Va, can
perform another function and draw zero stand-by power
as well.
2VPKC
IH·~
2v'KC
tL-iC
Ie" ~PKO
tIlIIC«IF
Figure 16. Ramp/Pulse VCO
The voltage·controlled low-pass filter of Figure 11 may
be used to design a high-quality sinusoidal veo. The
circuit of Figure 17 employs two XR-13600 packages,
with three of the amplifiers configured as low-pass filters and the fourth as a limiter/inverter. The circuit oscil'
lates at the frequency at which the loop phase-shift is
1-424
XR·13600
,. S
2Q'
r-...-----'VVV-----.-l~
TRIGGER
O.OlJ'F
o---"v'lAr~
1M'
Jl
Vo
t-----oVo
'OK
VI.o-I_"WI,--_-'
10K
Figure 21. Phase-Locked Loop
Figure 19. Timer With Zero Stand-By Power
+5V
82K
The operation of the multiplexer of Figure 20 is very
straight-forward_ When AI is turned on it holds Va
equal to VINI and when A2 is supplied with bias current
then it controls Va. Cc and RC serve to stabilize the
unity-gain configuration of amplifiers AI and A2. The
maximum clock rate is limited to about 200 kHz by the
XR-13600 slew rate into 150 pF when the (VIN1-VIN2)
differential is at its maximum allowable value of 5 volts.
.. v
Va
10 K
-5V
R
10 K
Figure 22. Schmitt Trigger
-tZV
Figure 23. Tachometer
Figure 2D. Multiplexer
represent the maximum low and maximum high output
voltage swing of the XR-13600. 01 added to provide a
discharge path for Ct and AI switches low.
The phase-locked loop of Figure 21 uses the fourquadrant multiplier of Figure 6 and the VCO of Figure
18 to produce a PLL with a ± 5 % hold-in range and an
input sensitivity of about 300 mV.
The sample-hold circuit of Figure 24 also requires that
the Darlington buffer used be from the other (A2) half of
the package and that the corresponding amplifier be biased on continuously.
The Schmitt trigger of Figure 22 uses the amplifier output current into R to set the hysteresis of the comparator; thus VH = 2 x R x IS will produce a Schmitt trigger with variable hysteresis.
The peak detector of Figure 25 uses A2 to turn on AI
whenever VIN becomes more positive than Va. AI then
charges storage capacitor C to hold Va equal to VIN
PK. One precaution to observe when using this circuit:
the Darlington transistor used must be on the same
side of the package as A2 since the AI Darlington will
be turned on and off with AI. Pulling the output of A2
low through 01 serves to turn off At so that Va remains
constant.
Figure 23 shows a tachometer or frequency-to-voltage
converter. Whenever AI is toggled by a positive-going
input. an amount of charge equal to (VH - VLl Ct is
sourced into Cj and Rt. This once per cycle charge is
then balanced by the current of VO/Rt. The maximum
FIN is limited by the amount of time required to charge
Ct from VL to VH with a current of IS. where VL and VH
1-425
XR·13600
.. v
+5n SAMPLE
,. K
o--'V'V\'--O_5~
L
the input signal. Because the output power of A1 is held
constant, the RMS value is constant and the attenuation is directly proportional to the RMS value of the input voltage. The attenuation is also proportional to the
diode bias current. Amplifier A4 adjusts the ratio of currents through the diodes to be equal and therefore the
voltage at the output of A4 is proportional to the RMS
value of the input voltage. The calibration potentiometer
is set such that Vo reads directly in RMS volts.
HOLD
VIN
Vo
-5V
, K
-SV
Figure 24_ Sample-Hold Circuit
PEAK OEUCT
Figure 27. True RMS Converter Circuit
The circuit of Figure 28 is a voltage reference of variable Temperature Coefficient. The 100 KO potentiometer
adjusts the output voltage which has a positive 1C
above 1.2 volts, zero 1C at about 1.2 volts and negative
TC below 1.2 volts. This is accomplished by balancing
the TC of the A2 transfer function against thecomplementary 1C of 01.
Vo
··15V
Figure 25_ Peak Detector and Hold Circuit
The ramp-and-hold of Figure 26 sources IB into capacitor C whenever the input to A1 is brought high, giving a
ramp-rate of about IV/ms for the component values
shown_
U.
RAMP
I0
01 1'F
_15V
Figure 28. Delta VBE Reference
Figure 26. Ramp and Hold Circuit
The log amplifier of Figure 29 responds to the ratio cif
current thru buffer transistors 03 and 04. Zero temperature dependence for VOUT is ensured i!" that the TC of
the A2 transfer function is equal and opposite to the 1C
of the logging transistors 03 and 04.
The true RMS converter of Figure 27 is essentially an
automatic gain control amplifier which adjusts its gain
such that the AC power at the output of amplifier A1 is
constant. The output power of amplifier A1 is monitored
by squaring amplifier A2 and the average compared to
a reference voltage with amplifier A3. The output of A3
provides bias current to the diodes of A1 to attenuate
The wide dynamic range of the XR-13600 allows easy
control of the output pulse width in the pulse-width
modulator of Figure 30.
1-426
XR·13600
VIN1 =
_-_2_K_T,...,13"", __ 2KTVC
ql2
ql2RC
The voltage on the base of 01 is then
VB1 =.::..(RJ._+,--,R2"",)-,V.!!.INu1
R1
The ratio of the 01 to 02 collector currents is defined
by:
Figure 29. Log Amplifier
VB1
= KT 1n IC2 == KT 1n~
q
IC1
q
11
Combining and solving for IB yields:
2(R1 + R2) Vc]
IB= (I)
1 exp [
12R1RC
-i
t-Tp
This logarithmic current can be used to bias the circuit
of Figure 4 to provide temperature independent stereo
attenuation characteristic.
Tp_~
-ILrl-
VOUl I-T~
2
CONSTANT
Tp'-,-C-
Figure 30. Pulse Width Modulator
For generating IB over a range of 4 to 6 decades of current, the system of Figure 31 provides a logarithmic
current out for a linear voltage in.
Since the closed-loop configuration ensures that the input to A2 is held equal to OV, the output current of A1 is
equal to 13 = - VC/RC.
The differential voltage between 01 and 02 is attenuated by the R1, R2 network so that A1 may be assumed
to be operating within its linear range. From equation
(5), the input voltage to A1 is:
-1~V
Figure 31. Logarithmic Current Source
'Vcc~------~--~------------------~----~------~---,
"
DIODE 81AS
BUFFER
OUTPUT
OUTPUT
-INPUT
o--'.......-f
-INPUT
3.1'
AMP BIAS
INPUT
o---~---r
VEE
(One
Channel Only)
(lSUeSTRATEJ
6
EQUIVALENT SCHEMATIC DIAGRAM
1-427
Repeaters
XR·C240
Monolithic PCM Repeater
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-C240 is a monolithic repeater circuit for PulseCode Modulated (PCM) telephone systems. It is designed to operate as a regenerative repeater at 1.S44
Megabits per second (Mbps) data rate on THype PCM
lines.
ALBO
OUTPUT
PREAMP {
INPUTS
The XR-C240 monolithic IC is packaged in a hermetic
16-Pin DIP package, and is designed to operate over a
temperature range of -40°C to +8SoC. It contains all
the basic functional blocks of a regenerative repeater
system including Automatic Line Build-Out (ALBO) and
equalization, and is insensitive to reflections caused by
cable discontinuities.
PREAMP{
OUTPUTS
GNO
V· =4.3V
Compared to conventional repeater designs using discrete components, the XR-C240 monolithic repeater IC
offers greatly improved reliability and performance,
along with significant savings in power consumption
and system cost.
SYSTEM DESCRIPTION
The XR-C240 contains all the active circuits required to
build one side of a T1 or 2 M bitls PCM repeater. T1 is
the most widely used PCM transmission system, operating at 1.S44 M bit/so It can operate on either pulp or
plastic insulated twisted pair cables. Although the cable gauge may vary, the total cable loss should not exceed 36 dB at 772 kHz. For a 22 gauge pulp insulated
cable and a bit error rate (BER) of less than 10- 6 , the
max allowable repeater to repeater spacing is about
6300 feet.
FEATURES
Contains all Active Components of PCM Repeater
On-Chip ALBO Equalizer
High-Current Output Drivers
Low-Power Consumption
Increased Reliability over Discrete Designs
2 Megabit Operation Capability
Bipolar PCM signal is attenuated and dispersed in time
as it travels along a transmission cable. This signal,
when received, is amplified and reconstructed by the
preamplifier automatic line build out (ALBO), clock and
data threshold detector circuits contained within the
XR-C240. Amplitude equalization and frequency spectrum shaping is achieved through the variable impedance of the ALBO ports and its associated ALBO network.
APPLICATIONS
PCM Repeater for T1 Systems
Repeater for 2 Megabit PCM Systems
ABSOLUTE MAXIMUM RATINGS
- 6SoC to ± 1SO°C
Storage Temperature
-40°C to ±8SoC
Operating Temperature
-O.S to 10 V
Supply Voltage
-O.S to + 7 V
Input Voltage (Except Pin 1,16)
-O.S to +O.S V
Input Voltage (Pin 7,16)
+20 V
Data Output Voltage (Pin 8,9)
SO V
Voltage Surge (Pin 2,3,8,9) (10 msec only)
Incoming pulse stream is full wave rectified and timing
information is extracted by the clock threshold detector. Clock recovery is then achieved by driving an injection locked oscillator tuned to 1.S44 MHz. The oscillator's sinusoidal waveform is amplified and phase shifted by 90 degrees with the help of a capacitor between
Pins 11 and 12.
Data is sampled and stored in the output data latches
by an internally generated sampling pulse. Buffer drivers are then enabled to produce precisely timed output
pulses whose width and time of occurrence are controlled by the regenerated clock signal.
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-C240
Ceramic
-40°C to +8SoC
1-428
XR·C240
ELECTRICAL CHARACTERISTICS
Test Conditions: (Measured at 25°C with V+ +
= 8.2V, V+ = 4.3V, unless otherwise specified.)
LIMITS
PARAMETERS
MIN
MAX
UNITS
Supply Voltage
V++
V+
7.79
4.085
8.61
4.515
V
V
Supply Current:
IA
IS
Total Current
1.1
6
7.1
2.5
11
13.5
mA
mA
mA
15
54
4
2
mV
db
p.A
p.A
k!l
Preamplifier
Input Offset Voltage, VOS
Open Loop Differential Gain, AO
Input Sias Current, IS
Input Offset Current, lOS
Input Impedance, Rin
50
50
CONDITIONS
Measured at Pin 10
Measured at Pins 7 and 15
Supply = 8.2V
Comparator Thresholds
Measured Differentially Across
Pins 4 and 5
Peak Detector (ALSO)
Threshold
Full-Wave Rectifier
Threshold
Data Threshold
Clock Extractor Section
Tank Drive Impedance
Tank Drive Current
"Zero" Signal Current
"One" Signal Current
Recommended Tank Q
Phase Shifter Offset Voltage
±1.3
±1.6
V
±0.9
± 1.15
V
±0.28
±0.48
V
50
12
80
100
-18
k!l
24
220
p.A
p.A
+18
mV
At Pin 14
Voltage applied to Pins 7 and 14
to reduce differential voltage
across Pins 11 and 12 to zero.
Output Drive Section
Output Voltage Swing
Low Output Voltage
Output Leakage Current
Output Pulse
Maximum Pulse Width Error
Rise and Fall Times
3.0
0.65
V
V
0.95
50
p.A
±30
80
ns
ns
1-429
Voltage levels referenced to Pin 7
RL = 100!l
Referenced to Pin 7, IL = 30 mA
XR·C262
High·Performance PCM Repeater
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
XR·C262
The XR-C262 is a high-performance monolithic repeater
IC for pulse-code modulated (PCM) telephone lines. It is
designed to operate as a regenerative repeater at 1.544
Megabits per second (Mbps) data rates on T1-type PCM
lines.
The XR-C262 operates with a single 6.8 volt power supply, and with a typical supply current of 13 mAo It provides bipolar output drive with high-current handling capability. The clock-extractor section of XR-C262 uses
the resonant-tank circuit principle, rather than the
injection-locked oscillator technique used in earlier
monolithic repeater designs. The bipolar output drivers
are designed to go to their "off" state automatically,
when there is no input signal present.
FEATURES
Contains all Necessary Active Components
of a PCM Repeater
Uses L-C Tank for Clock Recovery
Low-Voltage Operation (6.8 volts)
Low-Current Drain (13 mA, typical)
High-Current Bipolar Output Drivers
On-Chip ALBO Equalizer
Automatic Zero-Input Shutdown
Increased Reliability Over Discrete Designs
2 Megabit Operation Capability
SYSTEM DESCRIPTION
The XR-C262 contains all the active functions required
to build one side of a T1 or 2 M bitls PCM repeater. T1 is
the most widely used PCM transmission system, operating at 1.544 M bit/s. It can operate on either pulp or
plastic insulated twisted pair cables. Although the cable gauge may vary, the total cable loss should not exceed 36 dB at 772 kHz. For a 22 gauge pulp insulated
cable and a bit error rate (BER) of less than 10 - 6, the
max allowable repeater to repeater spacing is about
6300 feet.
APPLICATIONS
PCM Repeater for T1 Systems
Repeater for 2 Megabit PCM Systems
Bipolar PCM signal is attenuated and dispersed in time
as it travels along a transmission cable. This Signal,
when received, is amplified and reconstructed by the
peamplifier automatic line build out (ALBO), clock and
data threshold detector circuits contained within the
XR-C262. Amplitude equalization and frequency spectrum shaping is achieved through the variable impedance of the ALBO port and its associated ALBO network.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
- 65°C to ± 150°C
- 40°C to ± 85°C
Operating Temperature
Supply Voltage
-0.5 to +10V
Input Voltage (Except Pin 6,7)
-0.5 to +7 V
Input Voltage (Pin 6,7)
-0.5 to +0.5 V
+20 V
Data Output Voltage (Pin 9,11)
Voltage Surge (Pin 3,5,9,11) (10 msec only)
50 V
Incoming pulse stream is full wave rectified and timing
information is extracted by the clock threshold detector. Clock recovery is then achieved by pulsing a tank
circuit tuned to 1.544 MHz.
ORDERING INFORMATION
Pari Number
Package
Operating Temperature
XR-C262
Ceramic
-40°C to +85°C
Data is sampled and stored in the output data latches.
Buffer drivers are then enabled to produce precisely
timed output pulses whose width and time of occurrence are controlled by the regenerated clock signal.
1-430
XR·C262
ELECTRICAL CHARACTERISTICS
Test Conditions: +VCC = 6.8 V, TA = -40°C to +85°C.
PARAMETERS
Supply Current
Digital Current
Analog Current
Total Current
Preamplifier
Input Offset Voltage
DC Gain
Output High Level
Output Low Level
Clock Recovery Section
Clock Drive Swing (High)
Clock Drive Swing (Low)
Clock Bias
Clock Source Input
Current
MIN
7
2
LIMITS
TYP
MAX
10
3.5
13
13
5
17
mA
mA
mA
Measured at Pin 12
Measured at Pin 8
+15
mV
Measured between
Pins 3 and 5
74
0.5
dB
V
V
Measured at Pin 1
Measured at Pin 1
4
3.8
4.2
V
V
V
Measured at Pin 13
Measured at Pin 13
Measured at Pin 15
0.5
4
p.A
Measured at Pin 16
-15
60
4.3
69
5.1
3.8
UNITS
Comparator Thresholds
ALBO Threshold
Clock Threshold
Data Threshold
Internal Reference Voltages
Reference Voltage
Divider Center Tap
ALBO Section
Off Voltage
On Voltage
On Impedance
Filter Drive Current
Output Driver Section
Output High Swing
Output Low Swing
Leakage Current
Output Pulse Width
Output Rise Time
Output Fall Time
Pulse Width Unbalance
CONDITIONS
Measured at Pin 1
relative to Pin 14
0.75
0.323
0.323
0.9
0.4
0.4
1.1
0.517
0.517
V
V
V
5.2
2.6
5.45
2.78
5.55
2.85
V
V
10
75
1.7
15
1.5
mV
V
11
mA
0.9
100
V
V
p.A
354
100
100
15
nsec
nsec
nsec
nsec
1.2
0.7
1
5.9
0.6
6.8
0.7
294
324
1·431
Measured at Pin 2
Measured at Pin 14
Measured at Pin 7
Measured at Pin 7
Measured at Pin 7
Drive current available
at Pin 6
Measured at Pins 9 and 11
RL = 40011
IL = 15 mA
Measured with output
in off state
XR·C277
Low-Voltage PCM Repeater
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-C277 is a monolithic repeater circuit for PulseCode Modulated .(PCM) telephone systems. It is designed to operate as a regenerative repeater at 1.544
Megabits per second (Mbps) data rates on T1-type PCM
lines. It is packaged in a hermetic 16-Pin CERDIP package and is designed to operate over a temperature
range of - 40°C to + 85°C. It contains all the basic
functional blocks of a regenerative repeater system, including Automatic Line Build-Out (ALBO) and equalization, and is insensitive to reflections caused by cable
discontinuities.
30-40
The key feature of the XR-C277 is its ability to operate
with low supply voltage (6.3 volts and 4.3 volts) with a
supply current of less than 13 mAo Compared to conventional repeater designs using discrete components,
the XR-C277 monolithic repeater IC offers greatly improved reliability and performance, along with significant savings in power consumption and system cost.
FEATURES
ating at 1.544 M bit/s. It can operate on either pulp or
plastic insulated twisted pair cables. Although the cable gauge may vary the total cable loss should not exceed 36 dB at 772 kHz. For a 22 gauge pulp insulated
cable and a bit error rate (BER) of less than 10 - 6 the
max allowable repeater to repeater spacing is about
6300 feet.
Contains all the Active Components of a PCM Repeater
Low-Voltage Operation (6.3 volts)
Low-Power Dissipation (13 mAl
On-Chip ALBO Equalizer
High-Current Output Drivers
Increased Reliability over Discrete Designs
2 Megabit Operation Capability
Pin-Compatible with XR-C240
Bipolar PCM Signal is attenuated and dispersed in time
as it travels along a transmission cable. This signal,
when received, is amplified and reconstructed by the
preamplifier automatic line build out (ALBO), clock and
data threshold detector circuits contained within the
XR-C277. Amplitude equalization and frequency spectrum shaping is achieved through the variable impedance of the ALBO port and its associated ALBO network.
APPLICATIONS
PCM Repeater for T1 Systems
Repeater for 2 M/bits PCM Systems
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
- 65°C to ± 150°C
Operating Temperature
- 40°C to ± 85°C
Supply Voltage
-0.5 to 10 V
Input Voltage (Except Pin 1,16)
-0.5 to +7 V
Input Voltage (Pin 1,16)
-0.5 to +0.5 V
Data Output Voltage (Pin 8,9)
20 V
Voltage Surge (Pin 2,3,8,9) (10 msec only)
50 V
Incoming pulse stream is full wave rectified and timing
information is extracted by the clock threshold detector. Clock recovery is then achieved by pulsing a tank
circuit tuned to 1.544 MHz. Either injection locking or
pulsed tank type clock extraction are possible with the
XR-C277. By grounding Pin 13, the circuit works in the
pulsed tank mode. Floating (open) Pin 13 switches the
XR-C277 to an injection locked mode. The oscillator's
sinusoidal waveform is amplified and phase shifted by
90 degrees with the help of a capacitor between Pins
11 and 12.
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-C277
Ceramic
-40°C to +85°C
pf
PHASE
SHIFT CAP
Data is sampled and stored in the output data latches
by an internally generated sampling pulse. Buffer drivers are then enabled to produce precisely timed output
pulses whose width and time of occurrence are controlled by the regenerated clock signal.
SYSTEM DESCRIPTION
The XR-C277 contains all the active circuits required to
build one side of a T1 or 2 M bills PCM repeater. T1 is
the most widely used PCM transmission system, oper1-432
XR·C277
ELECTRICAL CHARACTERISTICS
Test Conditions: (+25°C, V+ +
= 6.3V±5%, V+ = 4.4V±
5%, unless otherwise specified.)
LIMITS
PARAMETERS
MIN
TYP
MAX
UNITS
CONDITIONS
8
3.5
7.5
11
13
mA
mA
mA
Measured at Pin 10
Measured at Pin 15
(lc + IB)
44
1.5
0.3
48
15
4
51
mV
p.A
dB
Measured at Pins 2 and 3
Measured at Pins 2 and 3
Single-ended Gain
3.45
1.25
2.47
3.6
1.4
2.55
3.75
1.55
2.72
V
V
V
Maximum Voltage Swing
Minimum Voltage Swing
10
75
mV
0.87
1.5
1.50
1.1
2.1
1.65
V
V
V
+75
mV
10
{)
Measured from Pin 1
and 16 to Ground
Measured at Pin 1
Measured at Pin 16
Measured Differentially
Across Pins 4 and 5
Threshold Difference for
Polarity Reversal at
Pins 4 and 5
Measured at Pin 1
k{)
Measured at Pin 1
%
% of ALBa Threshold
% of ALBO Threshold
Supply Current
IA
IB
Total Current
Preamplifier
Input Offset Voltage
Input Bias Current
Voltage Gain
Preamp Output Swing
High Swing
Low Swing
Output DC Level
Measured at Pins 4 and 5
ALBa Section
ALBa "Off" Voltage
ALBa "On" Voltage
ALBa "On" Voltage
ALBa Threshold
0.6
1.2
1.35
Differential Threshold
-75
ALBa "On"
Impedance
ALBa "Off"
Impedance
5
20
50
68
47
73
50
78
53
%
10
14
50
20
p.A
100
6.0
7
7.5
0.65
0.75
0.95
V
5
100
p.A
±30
80
80
n sec
n sec
n sec
Comparator Thresholds
Clock Threshold
Data Threshold
Clock Extractor
Oscillator Current
Tank Drive Impedance
Recommended OSC 0
linjectionllOSC
k{)
Ratio of Current 01 B to
Current in 01A
Output Driver
Low Output Voltage
Output "Off" Current
Output Pulse
Max. Pulse
Width Error
Rise Time
Full Time
1-433
Measured at Pins 8 and 9
IL = 15 mA
Vout = 20V
XR·C587/C588
T1 C PCM Repeater Chip Set
FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
The IC pair, XR·C587 and XR·C588, provides all the ac·
tive circuitry needed to form one side of a T1C PCM Re·
peater (3.152 MBits/sec). Each chip is packaged in a
16·Pin CERDIP package, with an operating temperature
range of - 40·C to + 85·C. The supply voltage range is
6.0 to 6.8 VDC, with a typical supply current for the pair
of 16mA.
.M.
.M.
OUTPUT
."
INVERTING
"'"
COI.I.ECTO~
INPUT
.MP
"'"
HONINYEMINQ
INPUT
SASE
....
The XR·C587 contains an amplifier, three AlBO ports,
and an npn transistor. The amplifier is a modified ver·
slon of the amplifier in Exar's XR·C262 T1 repeater chip.
This amplifier has its own ground pin for isolation, as
well as for eliminating the amplifier current drain if only
the XR·C587 AlBO diodes and/or the transistor are
used. Each of the three ALBO ports has a separate
ground and one common drive input. Any number, up to
three, can be used while eliminating current in any not
used. The npn transistor is provided for incidental uses.
"'"
GNO
EMITTER
Al.BO
DRIVE
INPUT
AL80
PORT'
AL80
"L.BOOND
PO",'
AND
SUBSTRATE
GN!)
ALBO
PORT'
ALIa
PO"',
OND
ALBO
PORT'
OND
The XR·C588 contains a preamplifier, an AlBO drive
output, a voltage reference, comparators, a clock reo
covery circuit, ECl latches and two output drivers. The
XR·C588 is a modified version of XR·C262 for T1C per·
formance. The amplifiers in the XR·C587 and XR·C588
are the same. The clock driver output is modified to
drive a crystal and has higher gain. Both inputs to the
clock amplifier are available. The clock amplifier may
be biased, both from the center tap voltage (Pin 14),
and the clock bias voltage (Pin 7).
--,
...
AMPLIFIER
OUTPUT
CLOCK
AMPlifiER
',.,PUTS
.....
..J
ZENER VOLTAGE
vcr
PREAMP
INPUT
AMPLIFIER BIAS
VOLTAGE
H
Two options for the clock comparator threshold voltage
are provided. Option 1 is 65% of AlBO threshold, and
Option 2 is 50% (the same as C262).
.coo
ANALOG
GROUND
CLOCK DRIVE
OUTPUT
.c.
"".....
INPUT
FEATURES
DIGITAL
SUPPLY
{,'
I.,.
Modified Preamplifier with Improved Phase Margin
Separate Grounds for Preamplifier and AlBO Ports
Crystal Drive Capability
Optional Clock Comparator Threshold levels (50%
and 65%)
·~TA
ALBODRIVE
OUTPUT
CURRENT
.co
DIOITAL
ClOCKe,AS
VOLTAGE
GROUND
ANALOG
+OATA
."
OUTPUT
SUPPLY
ABSOLUTE MAXIMUM RATINGS
Analog Supply Voltage
Digital Supply Voltage
Differential Input Voltage
Output Voltage
Storage Temperature
Operating Temperature
lead Soldering (10 seconds)
-0.5V to 10V
-0.5V to 10V
-5V to 5V
-0.5V to 20V
- 65·C to + 150·C
-40·C to +85·C
300·C
ORDERING INFORMATION
1·434
Part Number
Package
Operating Temperature
XR·C587
XR·C588
Ceramic
Ceramic
-45°C to +85°C
- 45°C to + 85°C
XR·C587/C588
ELECTRICAL CHARACTERISTICS-XR-C587/C588
Test Conditions: TA
=
-40°C to 85°C, at a supply voltage of VCC
PARAMETERS
SUPPLY
Supply Current
ALBa Bias Current
AMPLIFIER
DC open-loop gain
AC gain at 1 MHz
Corner Frequency
Input Offset Voltage
Input Bias Current
Output Sink Current
= 6.0V to 6.8V dc,
TYP
MAX
UNIT
6.0
2.3
6.4
2.7
6.8
3.3
V dc
rnA
200
280
360
rnA
54
34
60
68
+15
4
500
dB
dB
kHz
mV
p.A
p.A
1 V pop output level,
RL = 4 kll returned
to VCM = 2.7V
RS = 10 kll to both inputs
Total current to Ground
through all ALBa Ground
Pins, Drive input returned
to VCC = 6.0V through
51 kll.
Measured with 1 rnA nominal
level in each ALBa Ground
Pin.
Two VBE above Ground,1 rnA
in each Port.
Drive input and ALBa Ground
Pins
Grounded Frequency =
1.5 MHz
300
ALBO
One Common Drive Input,
Three Ports, Each With
Its Own Ground
Max ALBa Current
2.5
4.5
6
rnA
ALBa Current Mismatch
-5
0
+5
%
1.2V
1.45
1.7V
V dc
ALBa OFF Impedance
SINGLE TRANSISTOR
Beta ({3)
Leakage
CONDITIONS
MIN
110
0
1
400
ALBa Port Voltage
unless otherwise specified.
-15
kll
10
75
0.01
150
1
400
5
1-435
p.A
All ALBa Pins open
VCC = 6.3V
ALBa Grounds open
ALBa drive pin at 3.5V
( .. 5 VBE's)
VCE = 6.8V, IC
VCEO = 6.8V
= 100 rnA
XR·C587/C588
ELECTRICAL CHARACTERISTICS-XR-C588
= - 40°C to + 85°C, at a supply voltage of VCC
otherwise specified.
Tast CondHions: TA
=
VCA
=
VCO
=
6.0V to 6.8V dc, unless
MIN
TYP
MAX
UNIT
CONDITIONS
ICA, VCA Supply Current
1.8
3.5
5
mA
ICO, VCO Supply Current
ICCT, ICA + ICO
5
7
8
12.5
12
14.5
mA
mA
VCA is Analog Supply Voltage
VCO is Oigital Supply Voltage
Outputs off, VAO = VCT
Outputs off, VAO = VCT
PARAMETERS
SUPPLY CURRENTS
AMPLIFIER
VAO = Amplifier Output
Voltage
Same specifications as
amplifier in C587
VOLTAGE REFERENCES
Vzref, Zener Voltage
VCT Center Tap Voltage
VCS, Clock Bias
5.0
2.35
3.5
5.4
2.70
4.0
5.65
2.90
4.3
Volts
Volts
Volts
No external loading
No external loading
No external loading
.75
.9
1.05
Volts
VAO measured wlrespect to
VCT, with IADO = 100 pA
-.75
-.9
-1.05
Volts
-50
0
50
mV
42
48
53
% of
VAPD+
42
48
53
30
0
30
% of
VAPDmV
*57/42
62148
67/53
*57/42
62148
67/53
35/30
010
35/30
THRESHOLD VOLTAGES
ALBO Comparator
VAPO+, ALBO + peak
detector voltage
VAPD - , ALBa - peak
detector voltage
VAPD+ - VAPOData Comparators
VDT+, + data
threshold
VDT-, - data
threshold
VOT+ - VOTClock Comparator
VCLK +, + clock
threshold
VCLK -, - clock
threshold
VCLK + - VCLK-
*
Upper limits are for Option 1, lower limits are for Option 2.
1-436
% of
VAPO+
% of
VAPOmV
VAO varied, clock drive
input = 3.152 MHz sine
wave at .5V pp. Detect
onslaught of output pulses
at 3.152 MHz, measure
VAO·
Same as for VOT+
VAO varied. detect 100 mV
change in VCDO.
XR·C587/C588
ELECTRICAL CHARACTERISTICS-XR-C588 (Continued)
Tast conditions: TA = -40°C to +85°C, at a supply voltage of VCC
= VCA = VCD = 6.0V to 6.8V dc, unless
otherwise specified.
PARAMETERS
MIN
TYP
MAX
UNIT
CONDITIONS
-2.7
-3.0
-3.3
VN
2.7
3.0
3.3
VN
VAO changed from VCLK+
to (VCLK + + .5V)
measure change in VCDO.
VAO changed from VCLK- to
(VCLK- - .5V) meas.ure
change in VCDO.
-1.1
-1.8
-1.0
-1.5
-.9
-1.1
V
VCDO+ Low
-3.2
V
VCDO- Low
-3.2
V
4.3
V
15
4
mV
1
1.5
3.0
mA
10
p.A
CLOCK DRIVE OUTPUT VCDO
ACD + , gain from
VAO to VCDO
ACD-
ACD+/ACDVCDO High
VCDO measured w/respect to
VCC· VAO = VCT
VCDO measured w/respect to
VCC· VAO = VCT +
1.5 volts.
VCDO measured w/respect to
VCC VAO = VCT 1.5 volts.
CLOCK AMPLIFIER
VCACM, Clock Input
Common Mode Bias
Voltage
Input Offset Voltage
Input Bias Current
ALBO DRIVE IADO
IADO Max
2.35
-15
.7
IADO Off
VCT or VCB can be used as
VCACM
p.A
VAO at VCT ± 1.5 volts
IADO measured to Gnd.
VAO = VCT, IADO measured
to Gnd.
OUTPUT DRIVER
VOL±
VOL + - VOLTOPW ±, output
pulse width
TOPW+ - TOPWTRT±, Rise time
TFT±, Fall time
p.A
100
IO± Leak
.5
-80
143
.8
0
159
1.0
+80
175
Volts
mV
nsec
-10
0
10
40
nsec
nsec
40
nsec
NO SIGNAL PROTECTION
Output off and returned to
20 volts.
ILOAD = 15 mA
ILOAD = 15 mA
50% Pts. RL = 350(J
RL = 350(J
20% to 80% Pts.
RL = 350(J
20% to 80% Pts.
With no clock signal, Output
will be off
1-437
XR·C587/C588
PRINCIPLES OF OPERATION
data comparators which are internally biased from a
voltage reference and precision voltage divider network. The preamplifier output is sliced at various voltage levels to eliminate the effects of baseline noise.
This output is full wave rectified, and applied to a crystal time extraction circuit. The sinusoidal wave shape
from the time extraction circuit is differentially coupled
to a clock slicer block to produce the internal square
wave clock signal.
T1C is a digital line system operating at 3.152 Mbitsl
sec, very similar, in principle, to the T1 line system. It
provides 48 digitally encoded and time division multiplexed voice channel repeaters containing 2 regenerators which have the approximate spacing of 6300 ft.
Power is provided by a simplex arrangement with a line
current of 120 mAo Two regenerators share a common
power supply. Basic repeater functions, namely reshaping, retiming and regenerating, are performed for cable
losses from 6 to 54 dB, as measured at 1.576 MHz.
The bipolar PCM signal, which is attenuated and distorted due to transmission medium, is applied to a preamplifier through a pulse-shaping network. This network,
and the variolosser diodes, forms the AlBO circuitry
which provides attenuation and shaping to automatically adjust for varying cable characteristics.
The regeneration of data is achieved through a pair of
data comparators and ECl latches. The data slicing levels are set to ±50% of the preamplifier output peak
voltages. Eel latch outputs and clock signal are then
gated to produce two precisely timed output data signals. The positive and negative data paths are separate
but identical in design.
A feedback network is used around the preamplifier for
gain equalization, as well as to reject out-of-band noise.
The output of the preamplifier is controlled to swing between two established peak levels, and drives a set of
A zero input protection circuit is provided for the dual
task of preventing the output switches from latching in
an ON state, as well as reducing the likelihood of output
pulses with no input signal.
70
iii
w
w
cr
(!l
w
:0-
~-60
z
ew
<
<
J:
9
rn
D.
(!l
~-50
Z
W
0
D.
0
0-40
-...::-~
"",
-2So
-Soo
30
~
-7S o
-1000
20
I
___ PHASE OF C587
C588 AMPLIFIER
-12So
-1500
PHASE OF C262 "-......
AMPLIFIER
10
10K
1M
100K
FREO. (HZ)
Figure 1. Bode Plot of C262 and C587/C58B Amplifiers
1-438
10M
XR·C587/C588
BLOCK DIAGRAM OF C587 AND C588 INTERCONNECTED
VCD (OR VCT) FOR CLOCK BIAS
VCT FOR AMPLIFIER BIAS
THEEYEr-~~__~
XR-C587
~AO
XR-C588
VCDO
CLOCK DRIVE
OUTPUT
FEEDBACK Ioooi.......
> ..--!t.....u NETWORK
rt-t-.tl-l
CLOCK
INPUTS
ALBO DRIVE
CURRENT
ALBO
HII+--IDIODES I -....~......I--.....t-II
ALBO
FILTER
Figure 2. Block Diagram of C5871C588 Interconnected
1-439
V+
X-TAL
CIRCUIT
XR· T56001T5620
T1, T148C, & 2 M Bitls PCM Line Repeater
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-T5600fT5620 is a bipolar monolithic repeater IC
designed for PCM carrier systems operating at 1.544 M
bitls (T1), 2 M bitls, or 2.37 M bitls (T148C). It provides
ali of the active circuits required for one side of a PCM
repeater. A crystal filter clock extraction version of
XR-T5600fT5620 is available as XR-T5700fT5720.
SUBSTRATE GROUND
ALBO GROUND
ALBO
PORT 1
ALBO
CONTROL
CLOCK
ALBO
AMPLIFIER
I"OAT2
BIAS
ALBO
POAT3
FEATURES
PREAMP
-VE INPUT
Single 5.1 V Power Supply
Less than 10 ns Sampling Pulse over the Operating
Range
Triple Matched ALBO Ports
2 M Bitls Capability
PREAMP
~VE
INPUT
PREAMP
-VEOUTPUT
PREAMP
,vE OUTPUT
~_I!-
_ _ I-...;.,j
GLOCK
OUTPUT
PHASE SHIFTED
CLOCK INPUT
-VE DATA
OUTPUT
DIGITAL
GROUND
APPLICATIONS
T1 PCM Repeater
T148C PCM Repeater
European 2 M Bitls PCM Repeater
T1C PCM Repeater (requires external preamplifier)
SYSTEM DESCRIPTION
The XR-T5600fT5620 performs most of the functions required for one side of a PCM repeater operating at 2 M
bitls or similar baud rate. The integrated circuit amplifies the received positive and negative pulses and
feeds them into Automatic Line Build-out (ALBO), clock
and data threshold detectors, see Figure 1. The ALBO
threshold detector ensures that the received pulses at
Pins 7 and 8 have the correct amplitude and shape.
This is carried out by contrOlling the gain and frequency
shaping of the ALBO network with three variable impedance ALBO ports.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
- 65°C to + 150°C
Operating Temperature
-40°C to +85°C
Supply Voltage
-0.5 to +10V
Supply Voltage Surge (10 ms)
+25V
Input Voltage (except Pin 2,3,4,17)
-0.5 to 7V
Input Voltage (Pin 2,3,4,17)
- 0.5 to + 0.5V
Data Output Voltage (Pin 10,11)
20V
Voltage Surge (Pin 5,6,10,11) (10 msec only)
50V
The clock threshold detector extracts timing information from the pulses received at Pins 7 and 8 and
passes it into the external tank coil at Pin 15. The
sinusoidal-type waveform is amplified into a square
wave at Pin 13, and forwarded through an external
phase shift network into Pin 12. This waveform provides the Qata sampling pulse which opens latches into
which the data from the data threshold detectors is
passed. The resulting pluses are stored for half a bit
period (normally 488 ns) in the latches. They appear as
half-width output pulses at Pins 10 and 11.
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-T5600fT5620
Ceramic
-40°C to 85°C
1-440
XR·T5600
ELECTRICAL CHARACTERISTICS
Tast Conditions: TA = 25°C, VCC = 5.1 V ± 5%, unless sp~cified otherwise (see Figure 1).
PARAMETERS
Supply Current
Data Output Leakage Current
ALBO Port Off Voltage
Amplifier Pin Voltage
PINS
MIN
TYP
MAX
UNIT
22
0
30
100
mA
J.lA
0
2.9
0.1
3.4
V
V
0
50
50
53
200
mV
dB
kO
0
25
25
kO
0
1.6
80
49
1.4
V
%
%
mA
14
10,11
2,3,4
5,6,7,8
2.4
CONDITIONS
Vpull-up = 15 V, Vcc =
5.35 V
DYNAMIC CHARACTERISTICS AMPLIFIER
Output Offset Voltage
AC Gain @ 1 MHz
Input Impedance
Output Impedance
-50
47
20
Rs = 8.2 kO
ALBO
ALBO Off Impedance
ALBO On Impedance
20
THRESHOLDS
ALBO Threshold
Clock Threshold as % of ALBO Threshold
DATA Threshold as % of ALBO Threshold
Clock Drive Current
1.4
68
42
0.7
1.5
OUTPUT STAGES
Output Pulse Rise Time
Output Pulse Fall Time
Output Pulse Width
Output Pulse Width Differential
Buffer Gate Voltage (Low)
Buffer Gate Voltage Differential
At Vo = VALBO Threshold
RL = 1300, Vpull- up =
5.1 ±5%
224
-10
0.65
-0.15
244
1-441
40
40
264
+10
0.95
0.15
ns
ns
ns
ns
V
V
XR·T5620
ELECTRICAL CHARACTERISTICS
Tast Conditions: Unless otherwise stated, all characteristics shall apply over the operating temperature range of -40·C to +85·C
with Vcc = 5.1 V ±5%, all voltages referred to ground = 0 V.
SYMBOL
PARAMETERS
PINS
Supply Current
Data Output Leakage
Current
10,11
MIN
TYP
MAX
UNIT
22
30
mA
6
100
IlA
2.9
0
3.4
0.1
V
V
CONDITIONS
GENERAL (Ral. Figura 2)
IS
ILD
14
Amplifier Pin Voltages
ALBO Ports Off Voltage
5,6,7,8
2,3,4
2.4
From Vs
(See Note 1)
Note 1: Vs = 15V, VCC = 5.35V
AMPLIFIER (Ral. Figure 2, Only Pins 1,9,10... 18 (connactad)
Input Offset Voltage
5&6
-10
+10
mV
Input Bias Current
5&6
0
5
!lA
Input Offset Current
5&6
-1
1
IlA
Output Offset Voltage
7&8
-50
-50
mV
Common Mode
Rejection Ratio
Output Voltage Swing
7&8
7&8
30
2.2
0
RS =
(See
RS =
(See
RS =
(See
RS =
(See
8.2 kG
Note 1)
8.2 kG
Note 1)
8.2 kG
Note 1)
8.2 kG
Note 1)
dB
V
Vcc ±10%
RS = 10kG
(See Note 1)
T = 25·C
Note 1: RS = Source ReSistance
CLOCK AMPLIFIER (Ral. Figura 2 Disconnect Pin 15 Irom Pin 16)
Notes: 1.
2.
3.
4.
5.
Input Offset Voltage
15& 16
Input Bias Current
Max Output Voltage
Min Output Voltage
Max.lMin Output
Voltage Difference
15 & 16
13
13
0.7
0.7
-
0.7
..
0.5
6
mV
10
IlA
V
V
50
mV
~'6
mA
mA
RS = Source reSistance, Pin 15 positive With respect to Pin 16
Pin 15 = Pin 16 = 3.6V
Pin 15 = 2.6V, Pin 16 = 3.6V
Pin 15 = 4.6V, Pin 16 = 3.6V
Calculation only
ALBO (Ral Figura 2)
On Current
1
Drive Current
Resistance Pin 17 to Ground
1
17
1
DYNAMIC CHARACTERISTICS
3
0.4
35
1
47
20
1
50
1
I
50
53
1200
1
kn
1
dB
kG
G
1
V8,V7= ±1.75V
V8,V7 = ±1.75V
Not Powered
AMPLIFIER (Ral. Figura 3)
Ao
lin
lout
1
AC Gain at 1 MHz
Input Impedance
Output Impedance
I
5 to 8
5
7,8
I
(See Note 1)
1 (See Note 2)
Notes: 1. At 1 MHz, AC ground Pins 7 and 8 disconnect 51 G resistor. Allow for in-circuit R,C
2. At 1 MHz, use Figure 2.
CLOCK AMPLIFIER (Ral. Figure 3)
Ao
BW
td
lout
AC Gain
- 3 dB Bandwidth
Delay
Output Impedance
Notes: 1. Remove dc offset,
2. Remove dc offset,
3. Remove dc offset,
edge.
4. Remove dc offset,
15,16 to 13
15, 16 to 13
15 to 13
13
32
10
8
12
200
dB
MHz
ns
G
(See
(See
(See
(See
Note
Note
Note
Note
1)
2)
3)
4)
at 2,048 MHz, Pin 13 = 1 V pk·pk sine wave
Pin 13 = 1 V pk·pk sine wave
Pin 15 = 2 V pk·pk sine wave; delay from Pin 15 negative-going zero crossover to Pin 13 positive
at 2,048 MHz
1-442
XR·T5620
SYMBOL
PARAMETERS
PINS
MIN
2,3,4
20
TYP
MAX
UNIT
CONDITIONS
ALBO (Ref. Figure 2)
Off Impedance
Intermediate Impedance
Difference
On Impedance
Transconductance
Notes: 1.
2.
3.
4.
At
At
At
At
1
1
1
1
MHz,
MHz,
MHz,
MHz,
kll
(See Note 1)
5
25
0.03
%
11
dB
(See Note 2)
(See Note 3)
(See Note 4)
1.5
1.5
0
1.6
1.6
5
V
V
%
(See Notes 1 & 2)
(See Notes 1 & 2)
(See Note 3)
18
1.0
1.4
mA
(See Note 4)
IS
1.0
1.3
mA
(See Note 5)
0
5
SO
80
5
4S
4S
3
%
%
%
%
%
%
%
2,3,4
2,3,4
7/8 to 1
allow for in-circuit R,C
VS-V7 adjusted for current at Pin 1 = 100!LA
VS-V7 adjusted for ± 1.75 V
change in VS-V7 for current at Pin 1 = 10 p.A to 100 !LA
THRESHOLD VOLTAGES (Ref. Figure 3)
ALBa Threshold +ve
ALBO Threshold - ve
ALBa Threshold Difference
Clock Drive on Current
(Peak) +ve
Clock Drive on Current
(Peak) -ve
Clock Drive on Currenl
Difference
Clock Threshold + ve
Clock Threshold - ve
Clock Threshold Difference
Data Threshold +ve
Data Threshold - ve
Data Threshold Difference
Notes:
8-7
7-8
-
-
8-7
7-8
-
S-7
7-8
-
1.4
1.4
-5
-5
6S
68
-5
44
44
-3
0
46
46
0
(See
(See
(see
(See
(See
(See
(See
Note 3)
Notes 1, 6, 8)
Notes 1, 7, 8)
Note 3)
Notes 1, 8, 9, 11)
Notes 1,8,10,11)
Note 3)
1. Pklpk voltage at PinS 7 and S of a 1 MHz sine wave derived through amplifier and measured differentially
2. Pklpk voltage at Pins 7 and 8 adjusted for current at Pin 1 = 3 mA
3. Calculation only
( higher value
)
lower value -1
x 100 %
percentage difference calculated from
4.
5.
6.
7.
S.
9.
10.
11.
VS-V7 adjusted to ALBa threshold +ve voltage ref. Pin 16 = 3.6 V
V?,V8 adjusted to ALBa threshold -ve voltage ref. Pin 16 = 3.6 V
V8-V7 adjusted to peak current at Pin 18 = 1/2 (clock drive on current peak + vel
V?,V8 adjusted to peak current at Pin IS = 1/2 (clock drive on current peak - vel
Figure taken as a percentage of lower ALBO threshold
V8N7 increased until 1 MHz PRF on counter at Pin 10
V?,VS increased until 1 MHz PRF on counter at Pin 11
With 2,048 MHz 2 V pk-pk sine wave to Pin 15 with ISO p.H in parallel with 36 11 to Pin 16 = 3.6 V
OUTPUT STAGES (ReI. Figure 3. Use lBO JLH inductor between Pins 15 and 16. Apply 2.04B MHz 2V pk/pk to Pin 15.)
tr
tr
tf
tf
tw
.1tw
VOL
VOL
.1VOL
Output Pulse Rise
Time +ve
Output Pulse Rise
Time -ve
Output Pulse Fall
Time +ve
Output Pulse Fall
Time -ve
Output Pulse Width +ve
Output Pulse Width - ve
Output Pulse Width
Difference
Buffer Gate Voltage
(low) +ve
Buffer Gate Voltage
(low) -ve
Buffer Gate Voltage
Difference
10
40
ns
10% - 90%
11
40
ns
10% to 90%
10
40
ns
10%-90%
40
264
264
ns
ns
ns
10%-90%
at 50%
at 50%
11
10
11
224
224
244
244
-
-10
10
ns
10
0.65
0.95
V
11
0.65
0.95
V
-
-0.15
0.15
V
1-443
XR·T5620
I
Vee
Vs
Figure 2. D.C. Parameter Test Circuit
CLOCK
INPUT
Vee
I""
33 k
o lliF
AMPLIFIER INPUT
~
1"
Figure 3. A.C. Parameter Test Circuit
1-444
Vee
XR·T5620
SYMBOL
I
PARAMETERS
I
I
PINS
MIN
I
TYP
I
I
10
I
MAX
I
UNIT
I
I
ns
J
CONOITIONS
SAMPLE PULSE WIDTH (Ral. Figura 4. Cy = 27 pF)
ISample Pulse Width 1
I
(See Notes 1... 5)
Notes: 1. The sample pulse width IS the penod dunng which the output latches are opened to accept a signal above the data
threshold at Pin 7 or 8 and cause a half·width output pulse at Pin 11 or 10 respectively.
2. Sample pulse width is specified with a 2.048 MHz TTL waveform at clock input (Pin 15) and a 2.400 MHz Schottky TTL
waveform at amplifier input in the circuit of Figure 4. Figure 7 shows the relevant Ie waveforms.
3. Monitor the frequency of coincident output pulses at Pins 10 and 11 either directly or through output circuit to
frequency counter.
4. Sample pulse width = X ns + (0.1 x measured frequency in kHz) ns where X is the mean riselfall times of the
waveform at Pin 8 between 25% and 75%.
5. X to be within the range 10 ns < X < 12 ns. This requires HF layout techniques with the amplifier operated closed
loop.
SAMPLE PULSE GENERATOR INPUT WAVEFORM (Pin 12 Ral. Figura 4, Cy = 40 pF)
Output Pulse FreqUency,
10,11
,
1.024
'1.024'
1.024
,
-100 ppm
+ 100 ppm
MHZ'
(See Note 1)
Notes: 1. Width
' 2.048 MHz ± 100 ppm TTL waveform at clock input with half of above waveform frequency at amplifier input.
CLOC'"
INPUT
1".,
'cc
* *
Figura 4. Sampling Pulsa Test Circuit
1-445
XR·T5620
TYPICAL AT 5.1 V AND AT 25°C
60
-
53
50
47
40
~ ~~
r--... I"-....
30
~
GAIN (dB I
r-...
..
~r-. . .
20
10
~
~~~
'"
GAIN
180
GAIN (MAXI
~~~K
I~INI t":~~~
\\
PHASE (MAXI '
~V
0
\
-10
-30
3
4
6
8 10
2
3
PHASE (DEGREESI
~
60
,, ~1"TI
0
r\
-20
2
120
4
6
8 100
2
3
4
-60
-120
6
81000
FREQUENCY (MHzI
Figure 5. Typical and Limiting Values of Gain and Phase
INPUT WAVEFORMS
CLOCK liP 2.048 MHz
+2.4V
+O.4V
AMPLIFIER liP 2.400 MHz
+O.4V
+2.4V
IC WAVEFORMS
SAMPLE PULSE !lNTERNALI
PIN 8
+5.1V
PIN 10
+0.7V TYP.
+5.1V
PIN 11
+0.7V TYP.
NOTE
COINCIDENT OUTPUT PULSES
Figure 6.
Ie Waveforms for Measuring Sampling Pulse Width
1·446
XR·T5640
PCM AMI Line Receiver and
Clock Recovery Circuit
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-T5640 is a monolithic bipolar IC designed for T1
type line receiver application operating at 1.544 M bit/s.
It provides all the active circuitry required to perform
automatic line build out (ALBO), threshold detection,
binary NRZ data and clock recovery.
ALBO
GND
ALBO
PORT'
A clock recovery using crystal filter circuit version of
the XR-T5640 is also available as XR-T5740.
ALBO
PORT?
ALBO
PORT
FEATURES
-~
PREAMP
-'JE INPUT
On Chip NRZ Data and Clock Recovery
Less than 10 ns Sampling Pulse Over the Operating
Range
Triple Matched ALBO Ports
Single 5.1 Power Supply
PRE AM"
JE INPUT
PREAMP
. VE OUTPUT
SUBSTRATE
GND
ALBO
CONTROL
CLOCK
AMPLIFIER
BIAS
LC TANK
vee
CLOCK
OUTPUT
PHASE SHIFTED
CLOCK INPUT
PREAMP
·VE OUTPUT
DIGITAL
GROUND
NRZ OATA
APPLICATIONS
T1 PCM Line Receiver
T1C PCM Line Receiver (requires external gain)
General Purpose Bipolar Line Receiver
SYSTEM DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
The XR-T5640 is deSigned as a receiver for interfacing
T1 PCM carrier lines on plastic or pulp insulated cables. It can also be used as a general purpose alternate
mark inversion (AMI) receiver.
-65°Cto +150°C
Storage Temperature
- 40°C to + 85°C
Operating Temperature
-0.5 to +10V
Supply Voltage
+25V
Supply Voltage Surge (10 ms)
-0.5 to 7V
Input Voltage (except Pins 2,3,4,17)
- 0.5 to + 0.5V
Input Voltage (Pins 2,3,4,17)
20V
Data Output Voltage (Pins 10,11)
50V
Voltage Surge (Pins 5,6,10,11) (10 msec only)
The XR-T5640 is a modified version of XR-T5620 PCM
repeater IC. It contains all the active circuitry needed
to build a T1 line receiver for interfacing up to 6300 ft.
The preamplifier, the clock amplifier, threshold detectors, ALBO port, data latches and output drivers are
similar to the ones on XR-T5620. Clock extraction is
done by means of an L-C tank circuit.
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-T5640
Ceramic
- 40°C to 85°C
Bipolar + 1 and - 1 pulses are combined within the IC
to form a binary non-return to zero PCM signal at Pin
10. A synchronous clock signal is made available at Pin
11. Both outputs have open collector transistors.
1-447
XR·T5640
ELECTRICAL CHARACTERISTICS
Test CondHlons: TA = 25°C, VCC = 5.1 V ± 5 %
PARAMETERS
Supply Current
Clock & Data Output Leakage Current
Amplifier Pin Voltages
Amplifier Output Voltage Swing
Amplifier Output Offset Voltage
Amplifier Input Bias Current
ALBO on Current
Drive Current
MIN
2.4
2.2
-50
TYP
MAX
UNIT
22
0
2.9
30
100
3.4
rnA
0
50
5
3
!!A
V
V
mV
CONDITIONS
ALBO Off
Vrull- uP = 15V
A Unity DC Gain
Rs = 8.2 kO
!!A
mA
mA
1
AC CHARACTERISTICS
Pre-Amplifier
AC Gain at 1 MHz
Input Impedance
Output Impedance
Clock Amplifier
AC Gain
- 3 dB Bandwidth
Delay
Output Impedance
50
Open Loop
200
dB
kO
0
Open Loop
200
dB
MHz
ns
0
25
kO
0
20
32
10
10
ALBO
Off Inpedance
On Impedance
20
CLOCK DATA OUTPUT BUFFERS
RL = 1300, Vpull- up =
5.1V ± 5%
Rise Time
Fall Time
Output Pulse Width
Sample Pulse Width
VOL
IL sink
ns
ns
ns
ns
V
mA
30
30
244
10
0.7
35
THRESHOLDS
ALBO
Clock Drive Current Peak
Clock Thresholds
% of ALBO
Data Threshold
% of ALBO
1.4
1.5
1.0
63
40
46
1-448
1.6
V
mA
75
%
52
%
At Vo = VALBO Threshold
XR·T5650
PCM lune Receiver and
C~ock Recovery Cnrcuut
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-T5650 is a monolithic bipolar IC designed for
PCM type line receiver applications operating at Tl,
T14SC, Tl C and 2 M bitls data rates. It provides all the
active circuitry required to perform automatic line build
out (ALBO), threshold detection, positive and negative
data and clock recovery.
ALBO
GND
ALBO
PORT I
ALBO
PORT 2
Clock recover using a crystal filter instead of an LC
tank circuit is also available as XR-T5750.
FEATURES
vee
AMPLIFIER
·VE OUTPUT
CLOCK
OUTPUT
AMPLIFIER
-VE OUTPUT
PHASE SHIFTED
CLOCK INPUT
The XR-5650 is a modified version of XR-T5620 PCM repeater IC. It contains all the active circuitry needed to
build a PCM line receiver up to 6300 It cable length.
The preamplifier, the clock amplifier, threshold detectors, data latches and output drivers are similar to the
ones on XR-T5620. Clock extraction is done by means
of an LC tank circuit.
In addition to plus and minus one outputs, a synchronous clock signal is made available at Pin 11 by deleting one of the ALBO ports on XR-T5620 thus leaving
two matched ALBO parts. All outputs have high current
open collector transistors.
ORDERING INFORMATION
Package
Operating Temperature
Ceramic
- 40°C to + S5°C
-1 DRIVER
The XR-T5650 is designed for interfacing Tl, T14SC
and 2 Mbitls PCM carrier lines on plastic or pulp insulated cables. It can also be used at Tl Crate (3.152 M
bitls) with external gain. Since it outputs plus and minus
ones on a bipolar pulse stream together with the clock,
it can be used to interface systems having different line
codes like AMI, AMI-BSZS or AMI-HDB3.
-65°C to +150°C
Storage Temperature
-40° to +S5°C
Operating Temperature
-0.5 to + 10V
Supply Voltage
+25V
Supply Voltage Surge (10ms)
-0.5 to 7V
Input Voltage (except Pins 2,3,4,17)
- 0.5 to + 0.5V
Input Voltage (Pins 2,3,4,17)
20V
Data Output Voltage (Pins 10,11)
50V
Voltage Surge (Pins 5,6,10,11) (10 msec only)
Part Number
CLOCK
SYSTEM DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
XR-T5650
AMPLIFIER
BIAS
AMPLIFIER
.\ DRIVER
Tl PCM Line Receiver
T14SC Line Receiver
T1C PCM Line Receiver (requires external amplifier)
General Purpose Bipolar Line Receiver
HDB3 Line Receiver
BSZS Line Receiver
CLOCK
LC TANK
INPUT
DIGITAL
GROUND
APPLICATIONS
AL.BO
CONTROL
AMPLIFIER
VE INPUT
.VE INPUT
On Chip Positive and Negative Data, Clock Recovery
Less than 10 ns Sampling Pulse over the Operating
Range
Double Matched ALBO Ports
Single 5.1 V Power Supply
2 M Bitls Capability
SUBSTRATE
GND
1-449
XR·T5650
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC
= 5.1
V ± 5%, TA
PARAMETERS
Supply Current
Clock and Data Output
Output Leakeage Current
Amplifier Pin Voltages
Amplifier Output
Offset Voltage
Voltage Swing
Amplifier Input
Bias Current
Albo on Current
Drive Current
=25°C, unless specified otherwise.
MIN
2.4
-50
2.2
TYP
MAX
UNIT
24
30
mA
ALBa Off
0
2.9
100
3.4
p.A
Vrull- uB = 15 V
A DC nity Gain
0
50
mV
V
5
p.A
mA
mA
3
1
V
CONDITIONS
Rs = 8.2 kO
Measured Differentially
from Pin 7 to Pin 6
AC CHARACTERISTICS
Pre-Amplifier
AC Gain at 1 MHz
Input Impedance
. Output Impedance
Clock Amplifier
AC Gain
- 3 dB Bandwidth
Delay
Output Impedance
ALBa
Off Impedance
On Impedance
50
200
dB
kO
0
200
dB
MHz
ns
0
25
kO
0
20
32
10
10
20
CLOCK DATA OUTPUT BUFFERS
RL = 1300, Vpull-up =
5.1 V±5%
Rise Time
Fall Time
Output Pulse Width
Sample Pulse Width
VOL
IL sink
ns
ns
ns
ns
V
mA
30
30
244
10
0.7
35
THRESHOLDS
ALBa
Clock Drive Current Peak
1.4
1.5
1.0
1.6
V
mA
63
68
75
%
40
46
52
%
CLOCK THRESHOLD
% of ALBa
DATA THRESHOLD
% of ALBa
1-450
At Vo = VALBO Threshold
XR·T5660
Low Power T1, T148C, & 2 M Bitls Repeater
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-T5660 is a monolithic bipolar low power version
of the XR-T5620 repeater circuit for T1 type carrier system operating at 1.544 M bitls (T1), European 2 M bitls
or 2.37 M bitls (T148C). It provides all of the active circuitry required for one side of a PCM repeater. A crystal
filter clock extraction version is available as XR-T5760.
ALBO
GROUND
ALBO
PORT 1
ALBO
PORT 2
FEATURES
ALBO
PORT 3
Low Power
Single 5.1 V Power Supply
Triple Matched Automatic Line Build-out (ALBO) Ports
2 M Bitls Capability
PREAMP
APPLICATIONS
ALBO
CONTROL
CLOCK
AMPLIFIER
BIAS
LC TANK
-liE INPUT
Vee
PREAMP
.. VE INPUT
CLOCK
OUTPUT
PREAMP
-liE OUTPUT
T1 PCM Repeater
T148C PCM Repeater
European 2 M Bitls PCM Repeater
T1C PCM Repeater (requires external amplifier)
SUBSTRATE
GROUND
PREAMP
.VE OUTPUT
DIGITAL
GROUND
PHASE SHIFTED
CLOCK INPUT
-VE DATA
OUTPUT
·VE DATA
OUTPUT
ABSOLUTE MAXIMUM RATINGS
- 65·C to + 150·C
Storage Temperature
Operating Temperature
-40·C to +85·C
Supply Voltage
-0.5 to + 10V
Supply Voltage Surge (10 ms)
+25V
Input Voltage (except Pins 2,3,4,17)
-0.5 to 7V
Input voltage (Pins 2,3,4,17)
- 0.5 to + 0.5V
Data Output Voltage (Pins 10,11)
20V
Voltage Surge (Pins 5,6,10,11) (10 msec only)
50V
Bipolar PCM signal is attenuated and dispersed in time
as it travels along the transmission cable, characteristics of which vary with length, frequency, temperature
and humidity. The PCM signal when received is amplified, equalized for amplitude characteristics and reconstructed by the preamplifier, automatic line build out
(ALBO), clock and data threshold circuits. Amplitude
equalization is achieved through shaping the frequency
spectrum with the help of variable impedance ALBO
ports.
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-T5660
Ceramic
- 40·C to + 85·C
Timing information is contained in the incoming pulse
stream. This signal is full wave rectified and applied to
an L-C tank circuit to extract the clock signal at the data rate. The clock signal is amplified and phase shifted
between Pins 13 and 12 to obtain 90· phase shift by
means of an R-L-C circuit.
SYSTEM DESCRIPTION
The XR-T5660 is a monolithic bipolar PCM repeater IC
operating at 1.544 (T1), 2.048 and 2.37 (T148C) M bitsl
sec. It is the low power version of XR-T5620 PCM repeater IC. It contains all the active circuitry to implement one side of a PCM repeater operating on either
pulp or plastic insulated cables. Repeater to repeater
spacing on either type of cable is 6300 ft. max.
Data is sampled and stored in the output data latches
by an internally generated sampling pulse. Buffer drivers are then enabled to produce precisely timed output
pulses whose width and time of occurence are controlled by the regenerated clock.
1-451
XR·T5660
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC
= 5.1V,
PARAMETERS
Supply Current
Clock & Data Output
Output Leakage Current
Amplifier Pin Voltages
Amplifier Output
Offset Voltage
Voltage Swing
Amplifier Input
Bias Current
ALBO on Current
Drive Current
±5%, TA
= 25°C, unless otherwise specified.
MIN
2.4
-50
2.2
TYP
MAX
UNIT
9
14
mA
ALBO Off
0
2.9
100
3.4
/LA
V
Vfull- uB = 15 V
A DC nity Gain
0
50
mV
V
Rs = 8.2 k{)
Measured Differentially
from Pin 8 to Pin 7
5
/LA
mA
mA
3
1
CONDITIONS
AC CHARACTERISTICS
Pre-Amplifier
AC Gain at 1 MHz
Input Impedance
Output Impedance
Clock Amplifier
AC Gain
- 3 dB Bandwidth
Delay
Output Impedance
ALBO
Off Impedance
On Impedance
dB
k{)
50
20
200
()
dB
MHz
ns
32
10
10
200
()
k{)
20
25
()
RL = 130{), Vpull- up
5.1 V ± 5%
DATA OUTPUT BUFFERS
Rise Time
Fall Time
Output Pulse Width
Sample Pulse Width
VOL
IL sink
=
ns
ns
ns
ns
V
mA
30
30
244
10
0.7
35
THRESHOLDS
ALBO
Clock Drive Current Peak
1.4
1.5
1.0
1.6
V
mA
63
68
75
%
40
46
52
%
CLOCK THRESHOLD
% of ALBO
DATA THRESHOLD
% of ALBO
1-452
At Va
= VALBO Threshold
XR· T5700/T5720
T1, T148C, & 2 M Bitls PCM Line Repeater
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-T5700fT5720 is a bipolar monolithic repeater IC
that provides all the active circuits required for one
side of a PCM repeater. The IC is designed for clock extraction by using a crystal filter.
ALBO GROUND
ANALOG GROUND
SUBSTRATE GROUND
CLOCK
DRIVE
- - u :.....'"
ALBO
ALBO
PORT 1
The primary applications of XR-T5700 are T1 (1.544 M
bit/s), T148C (2.37 M bitls) and European 2 M bitls PCM
repeater.
CONTROL
CLOCK
ALBO
PORT 2
AMPLIFIER
CLOCK
ALBO
AMPLIFIER
PORT 3
A tank circuit clock extraction version of XR-T57001
T5720 is available as XR-T5600fT5620.
INPUT
AMPLIFIER
Vee
-VE INPUT
AMPLIFIER
+veINPUT
FEATURES
AMPLIFIER
-ve OUTPUT
Crystal Clock Extraction
Single 5.1 V Power Supply
Less than 10 ns Sampling Pulse over the Operating
Range
Triple Matched ALBO Ports
AMPLIFIER
+VEOUTPUT
GROUND
APPLICATIONS
---L-~
CLOCK
OUTPUT
PHASE SHIFTeD
CLOCK INPUT
-VE DATA
OUTPUT
+ve DATA
OUTPUT
SYSTEM DESCRIPTION
T1 PCM Repeater
T148C PCM Repeater
T1C PCM Repeater (requires external preamplifier)
European 2 M Bitls PCM Repeater
The XR-T5700fT5720 performs most of the functions required for one side of a PCM repeater operating at 2 M
bitls or similar baud rate. The integrated circuit amplifies the received positive and negative pulses and
feeds them into Automatic Line Build-out (ALBO), clock
and data threshold detectors, see Figure 1. The ALBO
threshold detector ensures that the received pulses at
Pins 7 and 8 have the correct amplitude and shape.
This is carried out by controlling the gain and frequency
shaping of the ALBO network with three variable impedance ALBO ports.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
- 65°C to + 150°C
Operating Temperature
-40°C to +85°C
Supply Voltage
-0.5 to +10V
Supply Voltage Surge (10 ms)
+25V
Input Voltage (except Pins 2,3,4,17)
-0.5 to 7V
Input Voltage (Pins 2,3,4,17)
- 0.5 to + 0.5V
Data Output Voltage (Pins 10,11)
20V
Voltage Surge (Pins 5,6,10,11) (10 msec only)
50V
The clock threshold detector extracts timing Information from the pulses received at Pins 7 and 8 and
passes it into open collector Pin 18. A crystal filter is
connected from Pin 18 to clock amplifier input Pins 16
and 15. The sinusoidal-type waveform is amplified into
a square wave at Pin 13, and forwarded through an external phase shift network into Pin 12. This waveform
provides the data sampling pulse which opens latches
into which the data from the data threshold detectors is
passed. The resulting pulses are stored for half a bit period (normally 488 ns for 2 M bitls) in the latches. They
appear as half-width output pulses at Pins 10 and 11.
ORDERING INFORMATION
Pari Number
Package
Operating Temperature
XR-T57001
T5720
Ceramic
-40C to +85°C
1-453
XR·T5700
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C, Vee = 5.1 V ± 5% unless specified otherwise (see Figure 1).
PARAMETERS
Supply Current
Data Output Leakage Current
ALBO Port Off Voltage
Amplifier Pin Voltage
PINS
MIN
14
10,11
2,3,4
5,6,7,8
2.4
TVP
MAX
UNIT
22
0
30
100
mA
0
2.9
0.1
3.4
V
V
0
50
50
53
200
mV
dB
kO
0
25
25
kO
0
1.6
80
49
1.4
V
%
%
mA
tJA
CONDITIONS
Vpull-up
5.35 V
= 15 V, Vcc =
DYNAMIC CHARACTERISTICS AMPLIFIER
Output Offset Voltage
AC Gain @ 1 MHz
Input Impedance
Output Impedance
-50
47
20
Rs
= 8.2 kO
ALBO
ALBO Off Impedance
ALBO On Impedance
20
THRESHOLDS
ALBO Threshold
Clock Threshold as % of ALBO Threshold
DATA Threshold as % of ALBO Threshold
Clock Drive Current
1.4
68
42
0.7
1.5
Output Pulse Rise Time
Output Pulse Fall Time
Output Pulse Width
Output Pulse Width Differential
Buffer Gate Voltage (Low)
Buffer Gate Voltage Differential
At Vo
= VALBO Threshold
=
RL = 1300, Vpull- up
5.1 ±5%
OUTPUT STAGES
224
-10
0.65
-0.15
1-454
244
40
40
264
+10
0.95
0.15
ns
ns
ns
ns
V
V
XR·T5720
ELECTRICAL CHARACTERISTICS
Test Conditions: Unless otherwise stated, all characteristics shall apply over the operating temperature range of - 40°C to + 85°C
with Vcc = 5.1 V ±5%, all voltages referred to ground = 0 V.
SYMBOL
PARAMETERS
PINS
MIN
TYP
MAX
UNIT
22
30
mA
100
p.A
3.4
0.1
V
V
-10
+10
mV
5
",A
CONDITIONS
GENERAL CHARACTERISTICS (Ref. Figure 2)
Supply Current
Data Output Leakage
Current
IS
ILD
14
10,11
Amplifier Pin Voltages
ALBO Ports Off Voltage
5,6,7,8
2,3,4
2.4
2.9
0
fromVS
(See Note 1)
Note 1: Vs = 15V, VCC = 5.35V
AMPLIFIER (Ref. Figure 2, Only Pins 1,9,10 ... 18 (Connected)
Input Offset Voltage
5&6
Input Bias Current
RS =
(See
RS =
(See
RS =
(See
RS =
(See
8.2 kll
Note 1)
8.2 kll
Note 1)
8.2 kll
Note 1)
8.2 kll
Note 1)
5&6
0
Input Offset Current
5&6
-1
Output Offset Voltage
7&8
-50
7&8
30
dB
Vcm ±0.3 V
7&8
7&8
30
2.2
dB
V
Vee ±10
6
mV
10
",A
V
V
RS
kll
(See Note 1)
T 25°C
50
mV
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
Output Voltage Swing
1
0
-50
mV
Note 1: RS = Source Resistance
CLOCK AMPLIFIER (Ref. Figure 2 Disconnect Pin 15 from Pin 16)
Input Offset Voltage
15 & 16
0.5
Input Bias Current
Max Output Voltage
Min Output Voltage
Max.lMin Output
Voltage Difference
15 & 16
13
13
0.7
0.7
Notes: 1. RS = Source resistance, Pin 15 positive with respect to Pin 16
2. Pin 15 = Pin 16 = 3.6V
3. Pin 15 = 2.6V, Pin 16 = 3.6V
4. Pin 15 = 4.6V, Pin 16 = 3.6V
5. Calculation only
ALBO (Ref Figure 2)
On Current
Drive Current
I Resistance
Pin 17 to GN
I
1
17
I
1: I I ~'~I
50
mA
mA
kll
=
=
l
V8- V7 = ±1.75 V
V8-V7=±1.75V
Not Powered
DYNAMIC CHARACTERISTICS
AMPLIFIER (Ref. Figure 3)
Ao
Zin
Zout
I
AC Gain at 1 MHz
Input Impedance
Output Impedance
I
5 to 8
5
7,8
(See Note 1)
(See Note 2)
Notes: 1. At 1 MHz, AC ground Pins 7 and 8 disconnect 51 11 resistor. Allow for in-circuit R,C
2. At 1 MHz, use Figure 2.
CLOCK AMPLIFIER (Ref_ Figure 3)
Ao
BW
AC Gain
- 3 dB Bandwidth
Delay
Output Impedance
Notes: 1. Remove dc offset,
2. Remove dc offset,
3. Remove dc offset,
edge.
4. Remove dc offset,
15,16 to 13
15,16 to 13
15,16 to 13
13
32
10
8
12
200
dB
MHz
ns
11
(See
(See
(See
(See
Note
Note
Note
Note
1)
2)
3)
4)
at 2,048 M Hz, Pin 13 = 1 V pk-pk sine wave
Pin 13 = 1 V pk-pk sine wave
Pin 15 = 2 V pk-pk sine wave. Delay from Pin 15 negative-going zero crossover to Pin 13 positive
at 2,048 MHz
1-455
XR·T5720
SYMBOL
PARAMETERS
PINS
MIN
TYP
MAX
CONDITIONS
UNIT
ALBO (Rei. Figure 2)
2,3,4
Off Impedance
Intermediate Impedance
Difference
On Impedance
Transconductance
Notes: 1.
2.
3.
4.
At
At
At
At
1
1
1
1
MHz,
MHz,
MHz,
MHz,
kO
(See Note 1)
M
dB
(See Note 2)
(See Note 3)
(See Note 4)
20
5
25
0.03
2,3,4
2,3,4
7/8 to 1
allow for in,clrcuit R,C
Va,V7 adjusted for current at Pin 1 = 100~
Va·V7 adjusted for ± 1.75 V
change In Va,V7 for current at Pin 1 = 10 p.A to 100 p.A
THRESHOLD VOLTAGES (Rei. Figure 3)
ALBO Threshold +ve
ALBO Threshold - ve
ALBO Threshold Difference
Clock Drive on Current
(Peak) +ve
Clock Drive on Current
(Peak) -ve
Clock Drive on Current
Difference
Clock Threshold +ve
Clock Threshold -ve
Clock Threshold Difference
Data Threshold + ve
Data Threshold - ve
Data Threshold Difference
Notes:
8·7
7·a
-
1.4
1.4
.5
1.5
1.5
0
1.6
1.6
5
V
V
(See Notes 1 & 2)
(See Notes 1 & 2)
(See Note 3)
18
0.65
1.0
1.4
mA
(See Note 4)
la
0.65
1.0
1.3
mA
(See Note 5)
-
.5
6a
68
-5
44
44
-3
0
5
ao
ao
5
4a
48
3
%
%
%
%
%
(See Note 3)
(See Notes 1,6,8)
(see Notes 1, 7, 8)
(See Note 3)
(See Notes 1, a, 9, 11)
(See Notes 1, a, 10, 11)
(See Note 3)
8·7
7·8
a·7
7·a
-
0
46
46
0
..
1. Pklpk voltage at PinS 7 and a of a 1 MHz sine wave denved through amplifier and measured differentially
2. Pklpk voltage at Pins 7 and a adjusted for current at Pin 1 = 3 mA
3. Calculation only
( higher value
)
x 100 %
percentage difference calculated from
lower value - 1
4.
5.
6.
7.
a.
9.
10.
11.
Va,V7 adjusted to ALBO threshold +ve voltage (ref. Pin 16 = 3.6 V)
VrVa adjusted to ALBO threshold - ve voltage (ref. Pin 16 = 3.6 V)
Va,V7 adjusted to peak current at Pin 18 = 112 (clock drive on current peak +ve)
V7,V8 adjusted to peak current at Pin la = 112 (clock drive on current peak -vel
Figure taken as a percentage of lower ALBO threshold
Va,V7 increased until 1 MHz PRF on counter at Pin 10
V7,Va increased until 1 MHz PRF on counter at Pin 11
With 2,04a MHz 2 V pk·pk sine wave to Pin 15 with lao p.H in parallel with 360 to Pin 16 = 3.6 V
OUTPUT STAGES (Raf. Figure 3. Usa 180 p.H Inductor between Pins 15 and 16. Apply 2.048 MHz 2V pk/pk to PIn 15.)
tr
tr
tf
tf
tw
tw
Ytw
VOL
VOL
bVOL
Output Pulse Rise
Time +ve
Output Pulse Rise
Time -ve
Output Pulse Fall
Time +ve
Output Pulse Fall
Time -ve
Output Pulse Width + ve
Output Pulse Width - ve
Output Pulse Width
Difference
Buffer Gate Voltage
(low) +ve
Buffer Gate Voltage
(low) -ve
Buffer Gate Voltage
Difference
10
40
ns
10%·90%
11
40
ns
10% to 90%
10
40
ns
10%·90%
40
264
264
ns
ns
ns
10%·90%
at 50%
at 50%
11
10
11
244
244
-
-10
10
ns
10
0.65
0.95
V
11
0.65
0.95
V
-
-0.15
0.15
V
1·456
244
244
XR·T5720
Figure 2. D.C. Parameter Test Circuit
CLOCK
INPUT
Vee
I"PF
3.3k
O.1"F
AMPLIFIER INPUT
~
1
51
Figure 3. A.C. Parameter Test Circuit
1-457
Vee
XR·T5720
SYMBOL
I
PARAMETERS
I
I
PINS
MIN
I
TYP
I
MAX
I
UNIT
I
CONDITIONS
I
10
I
20
I
ns
I
(See Notes 1...5)
SAMPLE PULSE WIDTH (Ref. Figure 4. Cy = 27 pF)
I
Sample Pulse Width
I
-
I
Notes: 1. The sample pulse width IS the penod dunng which the output latches are opened to accept a signal above the data
threshold at Pin 7 or 8 and cause a half·width output pulse at Pin 11 or 10 respectively.
2. Sample pulse width is specified with a 2.048 MHz TIL waveform at clock input (Pin 15) and a 2.400 MHz Schottky TL
waveform at amplifier input In the circuit of Figure 5. Figure 7 shows the relevant IC waveforms.
3. Monitor the frequency of coincident output pulses at Pins 10 and 11 either directly or through output circuit to
frequency counter.
4. Sample pulse width = Xns + (0.1 x measured frequency in kHz ns where X is the mean riselfall times of the
waveform at Pin 8 between 25% and 75%.
5. X to be within the range 10 ns < X < 12 ns. This requires HF layout techniques with the amplifier operated closed
loop.
SAMPLE PULSE GENERATOR INPUT WAVEFORM (Pin 12 ReI. F1gure 4, Cy = 40 pF)
j
Output Pulse Frequency
I
10,11
I
1,024
-100 ppm
l
1,024
I+
1,024
100 ppm
I
MHz
I
(See Note 1)
Notes: 1. Width 2.048 MHz ± 100 ppm TIL waveform at clock Input with half of above waveform frequence at amplifier input.
2. Sample pulse width is specified with a 2,048 MHz TIL waveform at clock input (Pin 15) and a 2,400 MHz Schottky TL
waveform at amplifier Input in the circuit of Figure 5. Figure 7 shows the relevant IC waveforms.
CLOCK
INPUT
36
!Ol~F
Vee
130
130
33 ,
,.0
240
* *
Figure 4. Sampling Pulse Test Circuit
1·458
XR·T5720
TYPICAL AT 5.1V AND AT 25 0 C
180
120
GAIN (dBI
PHASE
(DEGREESI
20 I-
60
lOr-
2
3
4
6
8 10
2
3
4
6
8100
3
2
4
6
81000
FREQUENCY (MHz)
Figure 5. Typical and Limiting Values of Gain and Phase
INPUT WAVEFORMS
+2.4V
+O.4V
CLOCK liP 2.048 MHz
+2.4V
AMPLIFIER liP 2.400 MHz
+O.4V
IC WAVEFORMS
SAMPLE PULSE (lNTERNALI
PIN 8
+5.1V
PIN 10
+0.7V TYP.
+5.1V
PIN 11
+0.7V TYP.
NOTE
COINCIDENT OUTPUT PULSES
Figure 6.
Ie Waveforms for Measuring Sampling Pulse Width
1-459
XR·T5740
PCM AMI Line Receiver and
Clock Recovery Circuit
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-T5740 is a monolithic bipolar IC designed for T1
line receiver application operating at 1.544 M bit/so It
provides all the active circuitry required to perform automatic line build out (ALBO), threshold detection,
binary NRZ data and clock recovery as the XR-T5640
but with a crystal filter instead of a LC tank circuit.
ALBO GROUND
ANALOG GROUND
SUBSTRATE GROUND
ALBO
PORT 1
A clock recovery using an LC filter circuit version of the
XR-T5740 is also available as the XR-T5640.
AlBO
POAT2
ALBO
PORTJ
FEATURES
AMPLIFIER
_VE INPUT
Clock Recovery using Crystal Filter
On-chip NRZ Data and Clock Recovery Circuitry
Less than 10 ns Sampling Pulse Over the Operating
Range
Triple Matched ALBO Ports
Single 5.1 V Power Supply
AMPLIFIER
+ve INPUT
CLOCK
DRIVE
ALBO
CONTROl.
CLOCK
AMPLIFIER
INPUT
CLOCK
AMPLIFIER
INPUT
'cc
CLOCK
OUTPUT
AMPLIFIER
-VEOUTPUT
PHASE SHIFTED
CLOCK INPUT
AMPLIFIER
.. VEOUTPUT
CLOCK
APPLICATIONS
T1 PCM Line Receiver
T1C PCM Line Receiver (requires external gain)
General Purpose Bipolar Line Receiver
SYSTEM DESCRIPTION
The XR-T5740 is designed as a receiver for interfacing
T1 PCM carrier lines on plastic or pulp insulated
cables. It can also be used as a general purpose alternate mark inversion (AMI) receiver.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65°C to + 150°C
Operating Temperature
- 40°C to + 85°C
-0.5 to + 10V
Supply Voltage
Supply Voltage Surge (10 ms only)
+25V
Input Voltage (except Pins 2,3,4,17)
-0.5 to + 7V
Input Voltage (Pins 2,3,4,17)
-0.5 to +0.5V
Data and Clock Output Voltage
- 0.5 to 20V
Voltage Sure (Pins 5,6,10,11) (10 ms only)
+ 50V
The XR-T5740 is a modified version of XR-T5720 PCM
repeater IC. It contains all the active circuitry needed
to build a T1 receiver for interfacing up to 6300 ft. The
preamplifier, the clock amplifier, threshold detectors,
ALBO port, data latches and output drivers are similar
to the ones on XR-T5720. Clock extraction is done by
means of a crystal filter circuit.
ORDERING INFORMATION
Part Number
Package
Operating Temperatura
XR-T5740
Ceramic
-40°C to +85°C
Bipolar + 1 and - 1 pulses are combined within the IC
to form a binary non-return to zero PCM signal at Pin
10. A synchronous clock signal is made available at
Pin 11. Both outputs have open collector transistors.
1-460
XR·T5740
ELECTRICAL CHARACTERISTICS
Tasl Conditions: TA
= 25°C, VCC = 5.1
PARAMETERS
Supply Current
Clock & Data Output Leakage Current
Amplifier Pin Voltages
Amplifier Output Voltage Swing
Amplifier Output Offset Voltage
Amplifier Input Bias Current
ALBO on Current
Drive Current
V ± 5%
MIN
2.4
2.2
-50
TYP
MAX
UNIT
22
0
2.9
30
100
3.4
ALBO Off
Vrull-uP = 15V
A Unity DC Gain
0
50
5
mA
p.A
V
V
mV
p.A
mA
mA
Open Loop
200
dB
kO
0
Open Loop
200
dB
MHz
ns
0
25
kO
0
3
1
CONDITIONS
Rs = 8.2 kO
AC CHARACTERISTICS
Pre-Amplifier
AC Gain at 1 MHz
Input Impedance
Output Impedance
Clock Amplifier
AC Gain
- 3 dB Bandwidth
Delay
Output Impedance
50
20
32
10
10
ALBO
Off Inpedance
On Impedance
20
CLOCK DATA OUTPUT BUFFERS
RL = 1300, Vpull- up =
5.1V ± 5%
Rise Time
Fall Time
Output Pulse Width
Sample Pulse Width
VOL
IL sink
THRESHOLDS
ALBO
Clock Drive Current Peak
Clock Thresholds
% of ALBO
Data Threshold
%of ALBO
ns
ns
ns
ns
V
mA
30
30
244
10
0.7
35
1.4
1.5
1.0
63
40
46
1-461
1.6
V
mA
75
%
52
%
At Vo = VALBO Threshold
XR·T5750
PCM Line Receiver and
Clock Recovery Circuit
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-T5750 is a monolithic bipolar IC designed for
PCM type line receiver applications operating at T1,
T148C, T1C and 2 M bltls data rates. It provides all the
active circuitry required to perform automatic line build
out (ALBO), threshold detection, positive and negative
data and clock recovery using a crystal filter.
ALBO
GND
SUBSTRATE
GNO
CONTROL
ALBO
CLOCK
AMPLIF'IER
PREAMPLIFIER
CLOCK
AMPLIFIER
PORT 2
VEINPUT
PREAMPLIFIER
FEATURES
"VE INPUT
On Chip Positive and Negative Data, Clock Recovery
Less than 10 ns Sampling Pulse over the Operating
Range
Double Matched ALBO Ports
Single 5.1 V Power Supply
2 M Bitls Capability
Clock Recovery using Crystal Filter
ALBO
ALBO
1
~ORT
Clock recovery using an LC tank circuit instead of a
crystal filter is also available as XR-T5650.
CLOCK
DRIVE
INPUT
INPUT
Vee
CLOCK
PREAMPLIFIER
·VEOUTPUT
OUTPUT
PREAMPLIFIER
PHASE
SHIFTED
CLOCK
INPUT
+VEOUTPUT
DIGITAL
GROUND
_1 DRIVER
APPLICATIONS
SYSTEM DESCRIPTION
T1 PCM Line Receiver
T148C Line Receiver
T1C PCM Line Receiver (requires external amplifier)
General Purpose Bipolar Line Receiver
HD83 Line Receiver
B8ZS Line Receiver
The XR-T5750 is designed for interfacing T1, T148C
and 2 Mbitls PCM carrier lines on plastic or pulp insulated cables. It can also be used at T1C rate (3.152 M
bitls) with external gain. Since it outputs plus and minus
ones on a bipolar pulse stream together with the clock
it can be used to interface systems having different lin~
codes like AMI, AMI-B8ZS or AMI-HDB3.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
- 65°C to + 150°C
Operating Temperature
-40° to +85°C
Supply Voltage
-0.5 to +10V
Supply Voltage Surge (10 ms)
+25V
Input Voltage (except Pins 2,3,4,17)
-0.5 to 7V
Input Voltage (Pins 2,3,4,17)
- 0.5 to + 0.5V
Data Output Voltage (Pins 10,11)
20V
50V
Voltage Surge (Pins 5,6,10,11) (10 msec only)
The XR-5750 is a modified version of XR-T5720 PCM repeater IC. It contains all the active circuitry needed to'
build a PCM line receiver up to 6300 ft cable length.
The preamplifier, the clock amplifier, threshold detectors, data latchs and output drivers are similar to the
ones on XR-T5720. Clock extraction is done by means
of a crystal filter circuit.
In addition to plus and minus one outputs, a synchronous clock signal is made available at Pin 11 by deleting one of the ALBO ports on XR-T5720 thus leaving
two matched ALBO ports. All outputs have high current
open collector transistors.
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-T5750
Ceramic
-40°C to 85°C
1-462
XR·T5750
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 5.1V, ± 5%, TA = 25°C, unless otherwise specified.
PARAMETERS
Supply Current
Clock & Data Output
Output Leakage Current
Amplifier Pin Voltages
Amplifier Output
Offset Voltage
Voltage Swing
Amplifier Input
Bias Current
ALBO on Current
Drive Current
MIN
2.4
-50
2.2
TYP
MAX
UNIT
24
30
mA
0
2.9
100
3.4
V
0
50
5
3
/L
mV
V
CONDITIONS
ALBO Off
Vrull- uB = 15 V
A DC nity Gain
Rs = 8.2 kO
Measured Differentially
from Pin 7 to Pin 6
p.A
mA
mA
1
AC CHARACTERISTICS
Pre-Amplifier
AC Gain at 1 MHz
Input Impedance
Output Impedance
Clock Amplifier
AC Gain
- 3 dB Bandwidth
Delay
Output Impedance
ALBa
Off Impedance
On Impedance
50
200
dB
kO
0
200
dB
MHz
ns
0
25
kO
0
20
32
10
10
20
CLOCK DATA OUTPUT BUFFERS
RL = 1300, Vpull-up =
5.1 V ± 5%
Rise Time
Fall Time
Output Pulse Width
Sample Pulse Width
VOL
IL sink
ns
ns
ns
ns
V
mA
30
30
244
10
0.7
35
THRESHOLDS
ALBO
Clock Drive Current Peak
1.4
1.5
1.0
1.6
V
mA
63
68
75
%
40
46
52
%
CLOCK THRESHOLD
% of ALBa
DATA THRESHOLD
% of ALBa
1-463
At Va = VALBO Threshold
XR·T5760
Low Power T1, T148C & 2 M Bitls Repeater
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIDN
The XR-T5760 is a low power version of the XR-T5700
repeater circuit for Tl carrier system operating at
1.544 M bitls (Tl), European 2 M bitls or 2.37 M bitls
(TI48C). It provides all of the active circuitry required
for one side of a PCM repeater and also has the cability
of clock extraction using a crystal filter.
ALBO GROUND
ANALOG GROUND
SUBSTRATE GROUND
ALBO
Vee
AMPLIFIER
---L'-=-'
OUTPUT
AMPLIFIER
OUTPUT
PHASE SHIFTED
CLOCK INPUT
AMPLIFIER
.... EDAlA
OUTPUT
+ve OUTPUT
GAOUND
+VE DATA
OUTPUT
peater IC. It contains all the active circuitry to implement one side of a PCM, repeater operating on either
pulp or plastic insulated cables. Repeater to repeater
spacing on either type of cable is 6300 ft. max.
Tl PCM Repeater
T148C PCM Repeater
European 2 M Bitls PCM Repeater
TIC PCM Repeater (requires external preamplifier)
Bipolar PCM signal is attenuated and dispersed in time
as it travels along the transmission cable, characteristics of which vary with length, frequency, temperature
and humidity. The PCM Signal when received is amplified, equalized for amplitude characteristics and reconstructed by the preamplifier, automatic line build out
(ALBO), clock and data threshold circuits. Amplitude
equalization is achieved through shaping the frequency
spectrum with the help of variable impedance ALBO
ports.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65°C to +150C
-40°C to +85°C
Operating Temperature
-0.5 to +10V
Supply Voltage
Supply Voltage Surge (10 ms)
+25V
-0.5 to 7V
Input Voltage (except Pins 2,3,4,17)
Input Voltage (Pins 2,3,4,17)
- 0.5 to + 0.5V
Data Output Voltage (Pins 10,11)
20V
Voltage Surge (Pins 5,6,10,11) (10 msec only)
50V
Timing information is contained in the incoming pulse
stream. This signal is full wave rectified and applied to
a crystal filter circuit to extract the clock signal at the
data rate. The clock signal is amplified and phase
shifted between Pins 13 and 12 to obtain 90° phase
shift by means of an R-L-C circuil.
ORDERING INFORMATION
-40°C to +85°C
AMPLIFIER
CLOCK
-ve
APPLICATIONS
Ceramic
CLOCK
INPUT
AMPLIFIER
-VE INPUT
+VEINPUT
XR-T5760
INPUT
ALBO
PORT 3
Low Power
Crystal Filter Clock Extraction
Single 5.1 V Power Supply
Less than 10 ns Sampling Pulse Over the Operating
Range
Triple Matched Automatic Line Build-out (ALBO) Ports
2 M Bitls Capability
Operating Temperature
CLOCK
AMPL.IFIER
ALBO
PORT 2
FEATURES
Package
ALBO
CONTROL
PORT 1
Clock recovery using an LC tank circuit instead of a
crystal filter is also available as XR-T5660.
Part Number
CLOCK
DRIVE
-"'1,tl..lll"Q.
SYSTEM DESCRIPTION
Data is sampled and stored in the output data latches
by an internally generated sampling pulse. Buffer drivers are then enabled to produce precisely timed output
pulses whose width and time of occurence are controlled by the regenerated clock.
The XR-T5760 is a monolithic bipolar PCM repeater IC
operating at 1.544 (Tl), 2.048 and 2.37 (TI48C) M bitsl
sec. It is the low power version of XR-T5720 PCM re1-464
XR·T5760
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 5.1 V ±5%, TA =25°C, unless specified otherwise.
PARAMETERS
Supply Current
Clock and Data Output
Output Leakeage Current
Amplifier Pin Voltages
Amplifier Output
Offset Voltage
Voltage Swing
Amplifier Input
Bias Current
ALBO on Current
Drive Current
MIN
2.4
-50
2.2
TYP
MAX
UNIT
14
mA
ALBO Off
0
2.9
100
3.4
pA
V
Vrull-u~ =15V
0
50
mV
V
Rs = 8.2 kO
Measured Differentially
from Pin 8 to Pin 7
5
p.A
mA
mA
3
1
CONDITIONS
A DC
nity Gain
AC CHARACTERISTICS
Pre-Amplifier
AC Gain at 1 MHz
Input Impedance
Output Impedance
Clock Amplifier
AC Gain
- 3 dB Bandwidth
Delay
Output Impedance
ALBO
Off Impedance
On Impedance
50
200
dB
kO
0
200
dB
MHz
ns
0
25
kO
0
20
32
10
10
20
DATA OUTPUT BUFFERS
RL = 1300, Vpull- up =
5.1 V ±5%
Rise Time
Fall Time
Output Pulse Width
Sample Pulse Width
VOL
IL sink
ns
ns
ns
ns
V
mA
30
30
244
10
0.7
35
THRESHOLDS
ALBO
Clock Drive Current Peak
1.4
1.5
1.0
1.6
V
mA
63
68
75
%
40
46
52
%
CLOCK THRESHOLD
% of ALBO
DATA THRESHOLD
% of ALBO
1-465
At Vo =VALBOThreshold
Custom/Semi-Custom Products
CUSTOM/SEMI-CUSTOM PRODUCTS
Semi-Custom Design Concept .......•.......................................................... 2-2
Answers to Frequently Asked Questions ........................................••............. 2-5
Economics of Semi-Custom Design ....................•....................................... 2-6
Converting Semi-Custom to Full Custom ....................................................... 2-7
Full Custom Development ................................................................... 2-8
Testing of Semi-Custom IC's .....•...........•..••..••.....•.•••...•...••...•••....••........ 2-10
Linear Semi-Custom Design ...........................•....................................... 2-11
XR-A100 Master-Chip ..................•................. " ......................•......... 2-13
XR-B100 Master-Chip .....•........................•.......................••.............. 2-14
XR-C100A Master-Chip .................•..........•......•.......................•......... 2-15
XR-D100 Master-Chip ............•..............•..................•....................... 2-16
XR-E100 Master-Chip .....................•.......•........................................ 2-17
XR-F100 Master-Chip .................•...............•.................................... 2-18
XR-G100 Master-Chip .........................................•...•........................ 2-19
XR-H100 Master-Chip ...................................................................... 2-20
XR-J100 Master-Chip ......................................................•............... 2-21
XR-L 100 Master-Chip ................•..................................................... 2-22
XR-M100 Master-Chip ..................................................................... 2-23
XR-U100 Master-Chip .................................................................... 2-24
XR-V100 Master-Chip ...............•...................................................... 2-25
XR-W100 Master-Chip ..................................................................... 2-26
XR-X100 Master-Chip .....................•...................................•............ 2-27
XR-400 12L Master-Chip ..................................................••................ 2-28
Linear Semi-Custom Design Cycle ...........•..•...........................•................. 2-29
Electrical Characteristics of Linear Master-Chip Components ......................................• 2-35
12L Semi-Custom Design .......................•............................................. 2-36
Features of 12L Technology ........•......................................................... 2-36
Designing with 12L Master-Chip .............................................................. 2-37
XR-200 12L Master-Chip .................................................•....•............. 2-42
XR-300 12L Master-Chip .............................•....................................•. 2-43
XR-400 12L Master-Chip .....................................................•.............. 2-44
XR-500 12L Master-Chip .................................................................... 2-45
12L Design Kit .........................................................................•.. 2-47
XR-C409 12L Evaluation Circuit .......................................................•....•. 2-49
Electrical Characteristics of 12L Master-Chip ....•....................................•..•....•.. 2-51
CMOS Semi-Custom Design and Features ........................................................ 2-52
CMOS Semi-Custom Design Cycle ...............•............................................ 2-53
Electrical Characteristics of CMOS Master-Chips ................................................. 2-54
Designing with CMOS Master-Chips ................................•.......................... 2-55
XR-CMA Master-Chip .................•.................................................... 2-57
XR-CMB Master-Chip ..............................•....................................... 2-58
XR-CMC Master-Chip .................•...............................•.................... 2-59
XR-CMD Master-Chip ...............••.....•.......................•....................... 2-60
2·1
SEMI·CUSTOM DESIGN CONCEPT
tive or cooperative development effort between Exar
and the customer. In most cases, the cost and develop·
ment time for the program can be reduced even further,
if the customer does the design and breadboarding of
his own semi-custom IC, using Exar Design Kits, instruction manuals and layout sheets.
Traditionally, the development of custom IC's has been
a long and costly undertaking. The development time
would normally run in excess of one year, design
changes are slow and costly, and it may take a long
time to get from the prototype stage to full production.
Because of these difficulties, the use of custom IC's
could be economically justified only when a very large
quantity of circuits, i.e., several hundred-thousand
units, were required during the life of the end product.
In the past, these drawbacks have severely limited the
use of custom monolithic IC's.
The semi-custom design approach is based on a number of standardized IC chips with fixed component locations. These standardized IC chips, called MasterChips, contain a large number of undedicated active
and passive components (i.e., transistors, resistors,
logic gates, etc.). These integrated components can be
interconnected in thousands of different ways with a
customizing interconnection pattern. Each different
metal interconnection pattern creates a new custom IC.
The figures below show the magnified photograph of a
Master-Chip, both in its prefabricated form and after its
customization with a special interconnection pattern.
This method is called semi-custom rather than full custom, since only the last layer of tooling is changed to
customize an IC chip, and rest of the layers are stan·
dard. As a result, the development phase is very short,
far less expensive and risk free, compared to conven·
tional full or dedicated custom IC's. Similarly, if a design
change or iteration is necessary, it can be readily accommodated within a matter of weeks by simply generating a new or modified interconnection pattern.
The semi-custom design concept, pioneered by Exar,
now overcomes this traditional problem. Exar makes
this possible by stocking wafers that are completely
fabricated except for the final process step of device interconnection which metalizes all selected components together in the required circuit configuration. This
enables an engineer to design a metal mask based on
his circuit which will interconnect the uncommitted
components on the prefabricated wafers, and thus convert them into customized chips corresponding to the
customer's design. This unique method of IC design
and development allows one to develop an almost unlimited variety of custom linear or digital integrated circuits at very substantial cost savings.
The semi-custom program is intended for those customers seeking cost effective methods of reducing
component count and board size in order to compete
more effectively in a changing marketplace. The program allows a customized monolithic IC to be developed with a turnaround time of several weeks, at approximately 10% to 20 % of the development costs for
tooling associated with the conventional full custom designs. The semi-custom design concept is an interac-
Exar offers a wide choice of Master-Chips for linear and
digital semi-custom design. Presently, Master-Chips are
available in linear bipolar, linear compatible 12L and
CMOS technologies. Additional chips are under development for a variety of special applications. The details
of each of the presently available chips are discussed
in the later section of this book.
Magnified Photograph of a Linear Master-Chip Before and After Customizing
2-2
DESIGN KITS
tomer and is essential to the success of the program. It
avoids any possible design pitfalls or misunderstandings. This early interaction also allows you to find out
some of the options or variations available in Exar's
semi-custom programs and choose the one which is
best suited to your needs.
Exar offers three Design Kits: One for linear bipolar, one
for 12L and one for CMOS. Since the general approach
to semi-custom design is the same as that for full custom, these design kits are valuable tools for both full
custom and semi-custom design work. This is especially true in the case of linear design. Each of these kits
contain a comprehensive design manual, a set of semicustom layout sheets and a P.C. board, IC sockets and
other hardware for building your breadboard. The only
active components in these kits, that are meant for use
in breadboarding, are the transistor arrays found in the
linear bipolar and 12L deSign kits. The logiC blocks
found in the 12L design kit is meant to be used for process evaluation. Digital breadboarding can be done using the appropriate logic family such as 74LXX, 74CXX
or 4XXX. The kits are deSigned so that an engineer,
armed only with a background in discrete design, a calculator and a pencil, can design his own customized integrated circuit. The technical material is presented in
a straight forward, no·nonsense format with iots of illustrative figures and all of the pertinent equations.
The following is required by Exar's technical staff to provide you with an accurate feasibility study of your project. and a budgetary estimate of the development
costs, timetables and production pricing.
• A block diagram of circuit function and inputloutput
interface requirements.
• A circuit schematic or logic diagram of your circuit.
• Preliminary or objective performance specifications
and limits on critical circuit parameters (also possible
tradeoffs which may be allowed).
o Types of electrical testing required for production
units (I.e., ac or dc parametric testing, functional testing, etc.).
After the circuit is designed, and before it is breadboarded, it is recommended that the customer send
Exar a schematic and a circuit description for an engineering evaluation. Normally, there is no charge for
such an evaluation. Exar has successfully completed
well over 850 custom design programs and our experience can provide valuable guidelines. Exar's Applications Engineering department is ready and able to help
our semi-custom design program customers in both the
breadboard and layout stage. We can provide immediate answers to your circuit design or testing questions,
and speed your custom design on its way.
Packaging requirements.
o
Production quantity requirements.
o
Desired development and production timetables.
o An indication of how much of the breadboarding, lay-
out, etc., can be done by you, the customer, using
Exar's Design Kits or standard logic blocks (74 LXX,
74CXX or 4XXX).
YOUR FIRST STEP
Once the above data package is submitted to Exar, we
would review it and respond to you within a few days.
Your very first step, at the start of a semi-custom program, should be to contact Exar for a preliminary analysis and discussion of your needs. This can be done
even while the program is still at the thought stage. This
initial review by Exar is performed at no cost to the cus-
CUSTOMER
LAYOUT
o
Normally, the test system development effort is initiated
in parallel with chip development. Exar has a complete
computer controlled IC test facility and offers complete
IC testing capability for production units.
METAL
MASK
Steps of Semi-Custom DeSign
2-3
FINISHED
CHIP
WHAT PACKAGE TYPES ARE AVAILABLE?
WHAT IF MY PRODUCTION REQUIREMENTS
EXCEED MY INITIAL EXPECTATIONS?
All semi·custom IC's are available in dual·in·line (DIP)
packages. Commercial grade units are normally pack·
aged in plastic DIP packages. Exar offers a wide selec·
tion of such packages, in B·, 14·, 16·, 1B·, 20·, 22·,24·,
2B· and 40·pin versions. The industrial or military grade
products requiring hermetic packaging are available in
frlt·seal ceramic packages (CERDIP). Other packages,
such as molded plastic flat packs, single·ln·line (SIP),
small-outline (8.0.) packages and lead less carriers, are
also available. All of the packaged units are subjected
to Exar's stringent quality assurance specifications pri·
or to shipment.
Using the semi·custom IC, it is not unusual for an end
product to be extremely successful in a very short time.
In that case, the anticipated volume of the custom IC
may jump from a few thousand units to several hundred
thousand units. When this happens, Exar can quickly
convert your semi·custom design to a full custom chip
and make it much more cost effective for you. Translat·
ing a semi·custom design to a full custom IC is a very
simple, trouble free step which can normally be done in
less than six months, and at a modest cost.
CAN EXAR SUPPLY CHIPS?
IS THERE A SECOND SOURCE FOR
SEMI-CUSTOM IC's?
All of Exar's semi·custom products can also be sup·
plied in chip form for hybird assemblies. A detailed description of the electrical specifications, visual inspec·
tion criteria, and the handling and shipping options
available for monolithic chips is given in a later section
of this book.
In most high volume production applications of IC's the
customer often requires more than one supplier of a
given IC. Anticipating this alternate source require·
ment, Exar has made contractual agreements with oth·
er IC manufacturers to provide a second source for
Exar's seml·custom IC's.
CAN EXAR DO ENVIRONMENTAL SCREENING?
In certain cases, where a critical supply situation may
exist, Exar can also provide a special bonded inventory
of parts, either in chip form or in packaged form, by pri·
or arrangement with the customer.
Exar has complete burn·in, environmental test and
screening services available for temperature stressing,
thermal shock or humidity and hermeticity tests. For a
detailed analysis of your needs, consult Exar's Market·
ing department.
START
Circuit Function
and Spec.
Final_by
Customer
-
Seml-Custom
Feasibility
Study
""""--
Initial
Production
Pricing
-
Oeslgn
Review
'---
Pencil
layout
r--
Breadboard
Construction
-
M.sk
or Digitizing
*
Computer
Mask
.Toollng
*
-
Prototype
Waler
Fabrication
*
*
r-**
Prototype
Evaluation
by Customer
r--
Simulation
*
r--
I-*
-
and Evaluation
*
**
Circuit
Oeslgn
**
*
~
-
Preliminary
Cost estimate
I--
Prototype
Test and
Assembly
I-**
*lIt_steps are not dona by Eor they should be done In consultation with Ex.r.
* *Thsse steps must be done by Exar.
FLOW CHART OF TYPICAL SEMI-CUSTOM DEVELOPMENT
2-4
FInish
FREQUENTLY ASKED QUESTIONS
AND THEIR ANSWERS
Typical costs of additional deSign cycles are $2,000 to
$4,500 for bipolar and CMOS designs and $3,500 to
$5,000 for 12L designs. These costs also include the additional prototypes supplied at the completion of the deSign iteration cycle.
Based on our long experience with Exar's semi-custom
Master-Chips, we have compiled a comprehensive
glossary of the most often asked questions concerning
the program. The following is a list of these questions
and their answers.
WHAT ABOUT PRODUCTION PRICING?
WHAT IS THE COST OF THE BASIC PROGRAM?
The production pricing of monolithic IC's depends upon
a number of important factors such as:
The cost of the semi-custom development program depends on how much of the design and layout is done by
the customer. In general, the basic semi-custom program is where the customer does the design, breadboard evaluation and pencil layout on the Master-Chip
worksheet; and Exar does only the IC tooling and prototype fabrication. This is the most economical and cost
effective approach.
a) Master-Chip type.
b) Circuit complexity (i.e., yield).
c) Device performance and test requirements.
d) Special environmental screening requirements
(burn-in, hermeticity tests, etc.).
For bipolar semi-custom designs, the development cost
of the basic program is in the range of $3,500 to
$6,000, starting with an accurate layout supplied by the
customer. The above prices also include the cost of 50
monolithic prototypes delivered at the completion of the
program. Additional prototypes are available at a nominal cost, in minimum lots of 200 units.
e) Package type required.
In the case of a custom IC, it is impossible to anticipate
the impact of these factors without detailed knowledge
about the circuit and its application. Each custom IC,
by definition, has some unique requirement or feature
associated with it. After reviewing your specific needs,
particularly with regard to the circuit performance and
quality requirements, Exar can provide you with a detailed proposal outlining the development costs and
production pricing for your particular circuit.
In the case of 12L or CMOS semi-custom deSigns, the
basic development program costs are in the range of
$4,200 to $8,500, depending on the layout complexity
and the particular Master-Chip used. This development
cost also includes 25 monolithic prototypes. Additional
prototypes are available at a nominal cost, in minimum
lots of 200 units each.
WHAT ABOUT THE TESTING OF SEMI·CUSTOM IC's?
WHAT IS THE DEVELOPMENT TIME?
Exar will develop test software and fixtures to provide
fully tested production IC's. All production devices receive 100% electrical test and screening to a mutually
agreed upon device specification. In addition to the
complete electrical testing, all of the production devices are screened by Exar's Quality Assurance department to assure compliance with the agreed upon Acceptable Quality Level (AQL) standards.
Typical development time for the basic bipolar semicustom program is four to six weeks, starting with the
customer's pencil layout and ending with the monolithic
prototypes. If Exar is required to do the IC layout or
breadboard evaluation, several additional weeks may
be required to complete the development program.
In the case of 12L or CMOS semi-custom development
programs, the typical development time is eight to ten
weeks, starting with the pencil layout of the MasterChip worksheet. The 12L semi-custom program takes
slightly longer than bipolar or CMOS because it requires three layers of custom tooling, rather than one,
to customize a prefabricated Master-Chip.
There is normally a nonrecurring engineering charge
associated with this test system generation. This covers the cost of the test fixture and computer software
development. Depending on the complexity of the test
reqUirements, this test engineering charge is normally
in the range of $800 to $1,250.
Exar can perform two basic types of tests for production IC's: (1) parametric testing which measures a specific parameter value (normally current or voltage) and
compares it against pre-established limits; (2) functional testing which applies a series of operating conditions
and compares the circuit under test with a known good
device. These two types of tests can be performed both
as steady state (dc) or dynamic (ac) measurements.
WHAT IF ADDITIDNAL DESIGN CYCLES ARE NEEDED?
If the customer desires to modify the design or layout
after evaluation of the initial prototypes, a new design iteration cycle can be completed within five weeks for
the bipolar and CMOS designs, and within eight to ten
weeks for the 12L designs.
2-5
ECONOMICS OF SEMI-CUSTOM DESIGN
In developing either linear or digital custom circuits,
one is always confronted with the following key question: for a given product type and production requirement, is it cheaper to develop a semi-custom or full
custom IC? Since the functional requirements of each
custom IC program vary greatly, there is no general answer to the above question. However, based on Exar's
long experience in both full and semi-custom IC design
and depending on the overall production requirements,
it is possible to establish some sound economic guidelines for choosing the most cost effective approach.
priced at $3.20 each, at the same 50,000 production
level. Then, its amortized per unit price will be $3.30, or
approximately 20% cheaper than a full custom.
The figure below gives a comparative graph of the amortized unit price for a typical full custom design, along
with the equivalent in semi-custom form for various production quantities. For comparison purposes, the relative ratio of the amortized unit price is plotted along the
vertical axis. If this ratio is greater than 1.0 then the
semi-custom method is the more cost effective solution.
COST FACTORS INVOLVED.
NO TWO IC's ARE THE SAME
Any custom IC development, whether full or semicustom, involves similar types of cost factors. These
are:
By definition, each custom IC type is unique. Therefore,
the cost comparison curve given below is shown as a
spread rather than a single line. This is because, in addition to the production quantity, the cost of monolithic
IC's also depends on the circuit complexity, special test
requirements and the IC package type.
1. Non recurring engineering (NRE) or development
costs.
2. Cost or unit price of the product in production quantities.
The key information contained in the relative cost vs.
quantity figure can be summarized as follows:
In the case of monolithic IC's, particularly those which
have relatively limited production volume, the development costs may be a significant factor in the cost of the
end product. Therefore, when discussing the economics of custom IC's for medium to low production
quantities, it is best to consider the cost tradeoffs in
terms of the amortized unit price of the IC at a given
production volume. This amortized unit price is defined
as the actual cost of each unit including its share of the
development cost. As an example, a full custom IC may
cost $50,000 to develop and may be priced at $2.90
each at a 50,000 piece total production level. Then, its
true amortized unit price including development costs
will be $2.90 plus $1.00, or $3.90. Similarly, an equivalent semi-custom IC may cost $5,000 to develop and be
1. For a total production requirement of 50,000 pieces
or less, the semi-custom approach is definitely the
most economical.
2. For a production requirement of 200,000 pieces or
more, the full custom design is more cost effective.
3. For production quantity requirements in the 50,000
to 200,000 piece range, the crossover point for the
most economical approach will depend strongly on
the specifics of a particular IC function; i.e., its special test, environmental screening, and package reqUirements.
3.0
"typical
. 01 coot
diotrlbutlon depending
on circuit type. t••••nd
screening requirements,
d1i
.!
Il~
pockegetype, elc .
20
~_ _ _ _...j.....:
.
H
5i
h
~~
cl
1.0
1-----+-----+------1-=
Ik
3k
10k
30k
lOOk
300k
Totel Quantity 01 IC'o Purcho_ (In lhouoando)
TYPICAL COST VS QUANTITY COMPARISON OF FULL CUSTOM AND SEMI-CUSTOM DESIGNS
2-6
1000k
CONVERTING SEMI-CUSTOM TO FULL CUSTOM
Exar can offer you the combined advantages of semicustom and full custom design programs. This is because Exar has a complete semiconductor manufacturing facilities. This unique capability allows Exar to state
a custom development program using a combination of
semi-custom Master-Chips during the initial phases of a
customer's product, taking full advantage of the low
tooling cost and short development cycle. As the product matures and its market expands (resulting in higher
volume production run rates) Exar can convert the mUltiple semi-custom chip approach into a single custom
IC, thus achieving a cost reduction and in many cases
a performance improvement. The significant advantage
of this type of program is that the risk associated with a
custom development is greatly reduced. The IC deSign
approach has been proven, production "bugs" are out
of the product and your production line continues to
flow during the full custom chip development. Once the
custom chip is completely characterized and found acceptable, the semi-custom IC system in your product
can be phased out while the full custom IC is being
phased in.
In this manner, the customer has the best of both
worlds with the combination of these two technologies.
The quick turnaround advantage of semi-custom
Master-Chips provide prototypes and initial production
units, while the subsequent full custom design provides
cost savings at high volume production. During this
transition, the customer is assured of a continuous flow
of product through its production line.
In such a two-step development, the semi-custom prototypes often serve as a monolithic breadboard to optimize and debug the final design. This allows deSign iterations or changes to be made quickly and inexpensively. In fact, the only difference between the semi-custom
and full custom chip is the actual size of the silicon
chip.
Once the design is satisfactory, conversion of a semicustom to a full custom chip is very straight forward
and relatively risk free. We simply remove the unused
electrical components from the chip to reduce the chip
size and pass the resulting cost savings on to you in the
form of a reduced unit price.
SEMI- AND FULL CUSTOM COMBINATION:
THE TWO-STEP DEVELOPMENT
The two-step development capability; i.e., start as semicustom and finish as full custom, is a very powerful design technique. It avoids the risks associated with a
conventional black box type of custom design where
one does not know until the very last day of development whether the circuit works or if it can be manufactured.
In many custom development programs one is faced
with very short development times and a rapid transfer
into high volume production. Such a requirement does
not leave room for lengthy development and design
change or iteration cycles associated with conventional
full custom IC design.
The two-step program is faster and less expensive than
the conventional full custom development, since it
avoids costly and lengthy design iteration or modification cycles for a full custom IC. In addition, it gives the
customer a very high degree of assurance that the final
full custom unit will work the first time.
Exar combines full and semi-custom design capabilities, and a complete wafer fabrication facility under one
roof, therefore, providing a unique solution to this problem; initially developing the prototypes in a semicustom form, and then converting them to full custom.
SEMI-CUSTOM DESIGN AND ITS FULL CUSTOM EQUIVALENT
2-7
FULL CUSTOM DEVELOPMENT
Exar offers a complete design and production capability
for full custom IC development. This provides an excellent complement to Exar's unique semi-custom capability. Exar's full custom IC development and production
capabilities offer complete flexibility to meet changing
customer needs or design problems. We can develop a
complete custom IC starting from your black box specifications, or reduce your working breadboard prototype
to a monolithic chip. Alternately, if you have the facilities and resources to do the IC design and layout, Exar
will provide you with the device characteristics and IC
layout rules for the particular process suitable to your
design and review your IC layout for you. Then, Exar
can generate the IC tooling and fabricate your IC prototypes.
els, operating frequency, timing diagrams, input!
output impedances, power dissipation, etc.
5. Production requirements and the desired development timetable.
6. Packaging requirements.
7. Level of screening required.
IC FABRICATION FROM CUSTOMER'S TOOLING
Exar has a complete in-house silicon wafer fabrication
and processing line at its main manufacturing plant in
Sunnyvale, California. This facility currently runs 3-inch
silicon wafers and will soon add 4-inch capability, and is
also available for manufacturing custom IC's directly
from a set of customer supplied IC tooling, in coordination with Exar's Mask Design department.
YOUR FIRST STEP FOR FULL CUSTOM DESIGN
The following technical data package is required in order for Exar to provide you with a quotation for your full
custom development program:
3. Description of circuit operation and pertinent application information.
If you have a set of IC tooling (masks and composite
overlays) or are contemplating having one designed for
you, Exar's technical staff will be glad to review it for
you to assure compatibility with Exar's technology and
layout tolerances. Our wafer processing technology
and capabilities are compatible with the industry standards, and with the technologies of other leading IC
manufacturers.
4. Preliminary or objective device specification indicating min/max conditions and limits for the critical parameters; i.e., input/output voltage and current lev-
For additional information on Exar's wafer fabrication
services, contact Exar directly. We pride ourselves in
our flexibility and quick response to your needs.
1. Circuit block diagram with subblocks.
2. Circuit schematic or logic diagram.
START
Circuit Function
and Specs
Finalized by
f--
Full Custom
Feasibility
Study
f--
Preliminary
I---
Cost Estimate
Circuit
Design
-
Customer
*
.---
Initial
Production
Pricing
I--
Design
Review
**
'--
Pencil
I--
Breadboard
Construction
and Evaluation
Mask
-
Digitizing
*
Mask
Tooling
these steps are not done by Exar they should be done In consultation with Exar.
**These steps must be done by Exar.
FLOW CHART OF TYPICAL FULL CUSTOM DEVELOPMENT
2-8
Computer
Simulation
Flntsh
I--
*
-
Prototype
-
Wafer
Fabrication
*
*
Prototype
Evaluation
by Customer
*tf
r-----
*
*
f--
Layout
*
**
**
I---
Prototype
Test and
Assembly
I--
**
Advantages of
Semi-Custom Design
over Discrete Design
Quick Turn-around
Advantages of
Full Custom Design
over Discrete Design
md------------~--~
Low initial Development Cost
High Reliability
100% Tested
Small Size
Fewer Connections
Fewer Components
Simple to Trouble-Shoot
Reduced Labor Costs
Smaller Inventory of Parts
Increased Protection Against Imitation
Lower Supply Current Possible
Reduced System Cost
Increased System Features
Specialized Components Possible
Higher Level of Integration than Semi-Custom
Lower Unit Cost Than Semi-Custom
More Optimum Design Possible
THE RELATIVE ADVANTAGES OF SEMI-CUSTOM AND FULL CUSTOM DESIGN OVER DISCRETE DESIGN
2-9
TESTING OF SEMI-CUSTOM IC's
TEST INTERFACE DEVELOPMENT
All production units of semi-custom IC's are 100%
electrically tested and screened to test specifications
which have been mutually agreed upon between Exar
and the customer, using one of Exar's several computerized test systems. In addition, Exar's Quality Assurance department performs an independent set of electrical tests on randomly selected samples of production
units, prior to shipment, to assure conformity with
Exar's Acceptable Quality Level (AQL) standards.
The performance and characterization data derived
from careful prototype evaluation is the basis upon
which test hardware and software is developed. Exar
and the customer will jointly determine the performance expectations to be placed on this new IC, and
once these specifications are agreed upon, Exar will
proceed with test development.
Test development involves the design and construction
of a test interface circuit, probe card and automatic
handler hardware as well as writing the software which
allows Exar's test system to perform the desired electrical tests. All these elements are then brought together under actual production conditions for evaluation
and system debugging. This process can take from
four to six weeks to complete, depending on the sophistication and complexity of the test plan under development. Test development begins concurrently with the
start of production wafers (which require approximately
6 weeks to process).
EXAR's TEST CAPABILITIES
Exar can perform two basic types of tests for production IC's: (1) parametric testing which measures a specific parameter value (normally current or voltage) and
compares it against pre-established limits; (2) functional testing which applies a series of operating conditions
and compares the circuit under test with a known good
device. These two types of tests can be performed both
as steady state (dc) or dynamic (ac) measurements.
Exar provides 100 % electrical testing of IC chips in wafer form, using automated wafer probe stations, and in
packaged form, using automatic handlers. Exar's test
facility currently has fifteen independent computer controlled test systems, with more being added as we
grow. Exar's automated test system compliment is
comprised of:
•
•
•
•
•
SPECIFICATION AGREEMENT LETTER
With each new custom IC Exar issues a Specification
Agreement Letter. This specification states precisely
the test conditions, performance levels and environmental requirements which each production IC must
meet before it can leave our factory, and is the document upon which acceptability of the IC is judged. It is
issued in duplicate and signed by responsible representatives from both companies prior to beginning production. One copy is retained by the customer, the other is returned to Exar.
Teradyne A311
Teradyne A312
Teradyne A360
Teradyne J273
Fairchild 5000C
Testing is one of the most critical steps in IC production. Therefore, to insure efficient and cost effective
testing of production IC's, it is essential that a preliminary test plan be prepared jointly between the customer and Exar at an early stage of the custom development. This preliminary test plan will lead to the final
detailed test specifications, once the development prototypes are fully evaluated and characterized and the
circuit is ready to release to production.
If, for some reason, changes in the IC's specification
are required, a new Specification Agreement Letter will
be issued by Exar reflecting these changes. No
change, however, will be put into effect until both companies have signed the new agreement. This document
will then supercede all prior agreements and remain in
effect until both firms, again agree, a change is required.
2-10
(E~#flroJ
~~ll\\
cases are those where the package pin-outs are predetermined, or the choice of component locations on the
die may be fixed due to thermal consideration, circuitry
symmetry or offset requirements. In certain cases the
series or parallel connection of several resistors to obtain a predetermined value, or paralleling several transistors to increase their current handling capability,
may also limit the total component utilization.
COMPONENT UTILIZATION
The total number of components on the Exar Linear
Master-Chips range from 110 on the XR-Cl00A to 850
on the XR-Wl00. However, the number of these components that are actually usable depends upon many
considerations. The first thing that must be evaluated is
the general requirements of the finished circuil. Factors such as the number of pins that are required,
breakdown voltage as well as die size limitation imposed by packaging requirements, determine which of
the Master-Chips are suitable. This can impose limitations on the number of available components.
Over 850 custom programs have been completed to
date, using Exar's bipolar Master-chips. Thus, Exar's
Engineering department has a great wealth of experience concerning the layout techniques utilizing the
Master-Chips. In many cases, it is advantageous for the
customer to call Exar for a free consultation regarding
the choice of a particular Master-Chip which may be
best suited for his application.
Circuit characteristics also impose limitations upon the
number of usable components. For example, a circuit
whose package pin configuration can be chosen freely,
that handles small signals, low supply voltages, is insensitive to dc offset voltages, and whose various circuit blocks follow one another with a minimum of interconnections between blocks, may be able to use over
90% of the components on the selected Master-Chip.
The bipolar Master-Chips are laid out to provide easy
routing of metal interconnection paths. In addition, a
multiplicity of low resistance crossunders are provided
on the chip to simplify the interconnection layoul.
Based on our experience in the layout of various
Master-Chips, the table below gives a rough estimate of
the ease of Interconnection of a circuit on each of the
Master-Chips, versus the number of components used
in the circuil.
On the other hand, in more complex designs requiring
special layout or design considerations, the component
utilization may be as low as 50%. Examples of such
Ease of Metal Interconnection vs Components Used
Master-Chip
Type
Somewhat
Difficult
Easy
Difficult
NPN
PNP
Resistance
NPN
PNP
ResistanclI
NPN
PNP
XR-A100
40
12
120k ohm
45
15
140k ohm
48
16
ResistanclI
160k ohm
XR-Bl00
50
7
150k ohm
52
9
170k ohm
58
12
200k ohm
XR-Cl00A
17
6
50k ohm
18
7
60k ohm
20
8
75k ohm
41
24"
100k ohm
45
26*
120k ohm
XR-D100
38
20"
90k ohm
XR-El00
38
20*
90k ohm
41
24*
100k ohm
45
26*
120k ohm
XR-Fl00
60
40*
250k ohm
70
46*
300k ohm
80
54*
340k ohm
XR-Gl00
50
7
150k ohm
52
9
170k ohm
58
12
200k ohm
XR-Hl00
50
28
190k ohm
55
34
225k ohm
61
38
260k ohm
XR-Jl00
23
16
90k ohm
28
18
110k ohm
30
20
125k ohm
XR-Ll00
56
28
200k ohm
61
34
230k ohm
68
38
265k ohm
XR-Ml00
103
80
410k ohm
113
95
475k ohm
126
108
550k ohm
XR-Ul00
to be announced -
call for information
XR-Vl00
100
77
1440k ohm
(l.4M)
110
92
1675k ohm
(1.675M)
122
104
1940k ohm
(1.94M)
XR-Wl00
150
86
1790k ohm
(1.79M)
165
103
2080k ohm
(2.08M)
183
117
2400k ohm
(2.4M)
XR-X100
17
20
170k ohm
20
25
200k ohm
22
26
220k ohm
2-11
EXAR LINEAR MASTER-CHIPS
The following section profiles the available Exar linear Master-Chips. The brief description of each Master-Chip includes a small layout of the chip indicating component locations, a brief outline of the key features of the chip, and applications that it is especially well suited for, as well as a tabulation of the type and number of components each
Master-Chip contains.
Linear Master-Chip Salection Guide
Master-Chip
Type
Chip Size
Mils
Possibla
Pins
Maximum
Voltaga
Total
Componants
XR-A100
78x73
16
20V
260
XR-B100
85x85
24
20V
300
XR-C100A
62x56
14
20V
110
XR-D100
81 x80
16
36V
209
XR-E100
82x82
18
20V
200
XR-F100
115x98
24
20V
472
XR-G100
90x90
18
20V
309
XR-H100
95x80
18
20V
378
XR·J100
80x75
18
20V
170
XR-L 100
102x85
24
20V
408
XR-M100
176 x 121
28
20V
812
T.B.D.
T.B.D.
36V
T.B.D.
XR-U100
XR-V100
147x113
28
36V
672
XR-W100
164 x 134
40
36V
850
XR-X100
115 x 95
18
75V
230
2-12
XR"A100 Master-ChipTM
Chip Size: 73 x 83 mils
Total Components: 260
Bonding Pads: 16
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 58
High Current: 2 (200 mAl
PNP Transistors: 18
Schottky Diodes: 15
Pinch Resistors
3OkQ: 4
100kQ: 4
Diffused Resistors
2OOQ: 16
1.8kQ: 29
4500: 43
3.6kQ: 28
9OOQ: 43
Total Resistance: 214kQ
I
B
F
XR-A100
2·13
XR·B100 Master·ChipTM
Chip Size: 85 x 85 mils
Total Components: 300
Bonding Pads: 16
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 69
High Current: None
Dual PNPTranslstors: 12
Schottky Diodes: 16
Pinch Resistors
3OkQ: 6
100kQ: 6
Diffused Resistors
2OOQ: 27
1.8kQ: 39
4500: 44
3.6kQ: 36
9000:45
Total Resistance: 255k
t
:.1:
i
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:L!!l -:-~T
~ ',. ~ :
1
I
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S!IiIIIlI[]
I ElCmOI~G""O /.
I
j
I
I
II
L==':==-=-=_~~~";:';-::'-;-========::'====::'-=--==--=.:=-.-=--:.:-_-_-_-_--=======-=--=--=--=-=.="::.=-;~~';;;-=~...,;-~=-===-=l_.Ll
XR-B1DD
2·14
Chip Size: 56 x 62 mils
Total Components: 110
Bonding Pads: 14
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 23
High Current: None
PNP Transistors: 8
Schottky Diodes: 6
Pinch Resistors
3OkQ: 2
Difused Resistors
200Q: 8
1.8kQ: 13
45QQ: 18
3.6kQ: 12
9OQQ: 20
Total Resistance: 154kQ
1-------------1
1
1::ili:::::::t:::::,:,::':':::':::::1 :
l!1;\@imill
l
I
I
I
1
I
I
1
1
)(R-C100A
2-15
XR·D100 Master·ChipTM
Chip Size: 80 x 81 mils
Total Components: 193
Bonding Pads: 16
Max. Operating Voltage: 36V
NPN Transistors
Small Signal: 50
Dual PNP Transistors: 16
Pinch Resistors
60kQ:2
Diffused Resistors
200Q: 15
1.8kQ: 29
45QQ: 29
3.6kQ: 24
9OOQ: 28
Total Resistance: 180kQ
-,
-,
-,
-,
XR-D100
2-16
XR·E100 Master.. ChipTM
Chip Size: 80 x 81 mils
Total Components: 187
Bonding Pads: 18
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 48
Dual PNP Transistors: 15
Pinch Resistors
3OkQ: 5
Diffused Resistors
2OOQ:8
1.8kQ: 25
45QQ: 32
3.6kQ: 26
9QOQ:28
Total Resistance: 180kQ
•
XR-E100
2·17
XR·F100 Master·ChipTM
Chip Size: 98 x 115 mils
Total Components: 440
Bonding Pads: 24
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 93
High Current: 4
Dual PNP Transistors: 36
Pinch Resistors
3OkQ: 9
Diffused Resistors
2Q()Q: 18
1.8kQ: 61
4500: 90
3.6kQ: 61
9Q()Q:
68
Total Resistance: 425kQ
XR-F100
2·18
Chip Size: 90 x 90 mils
Total Components: 309
Bonding Pads: 18
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 58
High Current: 2
PNP Transistors: 18
Schottky Diodes: None
Pinch Resistors
6OkQ: 8
Diffused Resistors
200Q: 19
1.8kQ: 44
450Q: 68
3.6kQ: 27
9000: 65
Total Resistance: 269kQ
XR-G100
2-19
XR·H100 Master·ChipTM
Chip Size: 95 x 80 mils
Total Components: 378
Bonding Pads: 18
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 70
Medium: 2
PNP Transistors
Lateral: 22
Pinch Resistors
60kQ:8
Diffused Resistors
2OOkQ: 29
1.8kQ: 54
450kQ: 82
1.8kQ: 36
9OOkQ: 75
XR·H1DD
2-20
XR·J100 Master-ChipTM
Linear, bipolar
Chip Size: 80 x 75 mils
Total Components: 170
Bonding Pads: 18
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 36
Medium: 2
Dual PNP Transistors: 12
Pinch Resistors
6OkQ:4
Diffused Resistors
200Q: 8
1.8kQ: 20
450Q: 34
3.6kQ: 20
9()()Q: 30
Total Resistance: 399k
rI-=-=-::::+.
I
I
I I
I I
I I
:I
't-----t'
iI
I
I
I
I
I
XR-J100
2·21
XR·L 100 Master·ChipTM
Chip Size: 102 x 85 mils
Total Components: 408
Bonding Pads: 24
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 76
Medium: 2
Large: 2
PNP Transistors
Lateral: 22
Quad Collector: 4
Pinch Resistors
6OkQ: 10
Diffused Resistors
200kQ: 23
450kQ: 103
900kQ: 77
1.8kQ: 53
3.6kQ: 36
XR·L100
2·22
Chip Size: 176 x 121 mils
Total Components: 812
Bonding Pads: 28
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 137
Low Noise: 4
Medium: 4
Large: 4
PNP Transistors
Lateral: 44
Quad Collector. 8
Large Vertical: 4
Pinch Resistors
6OkQ: 16
Diffused Resistors
200kQ: 60
450kQ: 188
9OOkQ: 140
1.8kQ: 104
3.6kQ: 84
Cross Under Resistors
15kQ: 11
2·23
XR·U100 Master·ChipTM
XR-U100
2-24
XR·V100 Master·ChipTM
Chip Size: 113 x 147 mils
Total Components: 672
Bonding Pads: 28
Max. Operating Voltage: 36V
NPN Transistors
Small Signal: 140
Large: 4
PNP Transistors
Lateral: 56
Small Vertical: 4
Large Vertical: 4
JFET Transistors
P·Channel: 4
Diffused Resistors
2000: 2B
3.6kQ: 60
450Q: 84
1.8kQ: 68
OOOQ: 68
Total Resistance: 443k
Ion Implant
5Ok: 24
5k: 24
2Ok: 24
1k: 20
10k: 24
Total Resistors: 2.06 MegQ
Cross Under Resistors
5Q:4
XR-V100
2-25
Oxide Capacitor. 4 x 10 pF
XR·W100 Master·ChipTM
Chip Size: 164 x 134 mils
Total Components: 850
Bonding Pads: 40
Max. Operating Voltage: ::k3V
NPN Transistors
Small Signal: 196
Medium Quad: 4
Large: 4
PNP Transistors
Lateral: 60
Small Vertical: 10
Large Vertical: 4
Diffused Resistors
200kQ: 24
1.8kQ: 88
450kQ: 100
3.6kQ: 72
9OOkQ: 100
Ion Implant
5OkQ: 28
5kQ: 32
2OkQ: 32
1kQ: 32
10kQ: 32
Cross Under Resistors
5kQ:4
XR-W100
2-26
Oxide Capacitor 8 x 10 pF
Chip Size: 115 x 95 mils
Total Components: 230
Bonding Pads: 18
Max. Operating Voltage: 75V
NPN Transistors
Small Signal: 30
High Current: 4
PNP Transistors: 46
Pinch Resistors
3OkQ: 3
100kQ: 3
Diffused Resistors
5Q: 14
1kQ: 27
10Q: 7
2kQ: 57
20Q: 8
5kQ: 12
500R: 49
Total Resistance: 615k
)(R·X1DD
2-27
XR·400 12L Master·ChipTM
Chip Size: 119 x 149 mils
5-0utput 12L Gates: 256
Bonding Pads: 40
Max. Operating Voltage: 7V
NPN Transistors: 45
4-Coliector PNP
Transistors: 12
Schottky-Bipolar 1/0
Interfaces: 18
Diffused Resistors
700Q: 200
2.5kQ: 116
5kQ: 20
Total Resistance: 530k
XR-400 12L
2-28
LINEAR SEMI-CUSTOM DESIGN CYCLE: SIX SIMPLE STEPS
The basic linear semi-custom design program involves only 6 single steps, from the beginning of circuit design to the
completion of monolithic prototypes. The first four of these steps can be done by either the customer in consultation
with Exar or by Exar. The last two are performed by Exar.
Step 1
Circuit design and
breadboard using
Linear Design Kit.
Customer purchases Exar's Linear IC Design Kit, made up of a comprehensive Design Manual and monolithic kit parts. The circuit is designed, breadboarded and its
performance evaluated using these kit parts. The electrical characteristics of the kit
parts Are virtually identical to the component which will be on the finished IC chip.
Thus, this step provides a true simulation of the final IC performance.
Circuit layout
is prepared
After the completion of breadboard evaluation, a layout of the circuit on the selected
Master Chip by following the basic layout rules given in the Design Manual. The layout is done simply by interconnecting appropriate device terminals with pen or pencil lines on oversize drawings of the Master Chips supplied with the kit.
Layout review
Exar reviews the circuit layout and schematic to check the following:
a) That basic circuit function is feasible
b) No layout rules are violated
c) Circuit layout accurately represents the circuit schematic.
NOTE: Exar offers consulting service and design advice during these first three
steps.
Exar generates custom
interconnection pattern.
Using the completed Master-Chip layout sheet, Exar generates a custom interconnection pattern, or metal mask to be applied to pre-fabricated Master-Chip wafers.
Exar fabricates customized
IC wafers.
Exar applies the custom interconnection patterns to pre-fabricated Master-Chip wafers. During this customization process, the hardware and software necessary to
test the prototypes is made ready. After the wafers are customized, each die is tested by an automatic tester.
Exar assembles and
delivers monolithic
prototypes.
The customized IC wafers are scribed or cut into individuallC chips. After a visual inspection, several die that tested "good" are assembled in cerdip packages. These
packaged devices are then tested again before shipment. Fifty assembled IC's, and
test data for correlation purposes, are sent to the customer in a prototype package
that includes a die photo, device schematic test details and a layout sheet.
Step 2
Step 3
Step 4
Step 5
Step 6
2-29
LINEAR DESIGN KIT
Exar's Linear Design Kit is comprised of thirty-eight
monolithic kit parts or breadboard components, a comprehensive Linear Design Manual, and a number of layout forms corresponding to Exar's Linear Master-Chips.
This design kit provides an ideal vehicle for the customer to do his own semi-custom IC design. he can
evaluate his breadboard performance using the kit
parts and then proceed to do his own layout on the
Master-Chip worksheet.
on a breadboard In a couple of minutes with a pair of
pliers and a hot soldering iron. Changes on an IC are
much more expensive and time consuming. The breadboard can be tested over temperature in a temperature
chamber and circuit performance can be measured
with worst case resistor values. Preliminary test specifications can also be readily developed from a properly
functioning breadboard. Next to the initial paper design, breadboarding is the most important step in IC development.
The Linear Design Manual Provided as a part of the design kit gives a detailed description of the basic guidelines and rules of IC design, evaluation and layout. It also describes the electrical characteristics of each type
of component available in the Master-Chips, and gives
some of the anticipated parameter distribution and
worst case tolerances associated with each. In addition, several design and layout examples are provided
to demonstrate the efficient use of the IC chips.
KIT PARTS
Since the purpose of breadboarding is to build a Circuit
that will duplicate, as closely as possible, the performance of the finished IC, Exar has included with this design kit a generous supply of kit parts. These kit parts
are the same integrated components that you will find
on the finished IC. They are metalized and brought out
individually so that you can use them to connect your
circuit. The table below lists the kit parts that come with
the design kit; how many of each are included, and
which components are found on each Master-Chip.
Once the breadboard evaluation is complete, the designer is ready to start his own IC layout using the appropriate Master-Chip layout form supplied with the kit.
When this layout is ready and is reviewed by Exar, the
prototype fabrication portion of the custom program is
ready to begin.
Generally speaking, the integrated resistor arrays need
only be used in circuits where certain characteristics of
these resistors, such as high frequency response or
temperature coefficients, are critical to circuit performance. In most cases, standard off-the-shelf carbon film
resistors are entirely adequate for breadboarding.
TECHNICAL ASSISTANCE
If any special or unusual circuit design or layout problems are encountered in the preparation of your semicustom IC layout, Exar's technical staff will be glad to
review your design problem and provide technical guidance. In many cases, it is beneficial to call Exar for a
preliminary discussion of your custom IC needs even
before you decide to buy a design kit.
BREADBOARDING TECHNIQUES
The single most important thing to remember when you
are building a breadboard is that you are trying to simulate the operation of a circuit that measures approximately a tenth of an inch on a side with one that measures several inches on a side. Although this task is not
impossible, it does require a significant amount of planning and forethought, if it is to be successful.
ADDITIONAL KIT PARTS
The number of kit parts supplied as part of the Linear
Design Kit is sufficient for most designs. However, if
additional kit parts are required to complete your evaluation, these can be obtained either directly from Exar
or through your local Exar technical representative.
Included in the Exar DeSign Kit are conveniences, such
as a prototyping board and IC sockets, to make breadboarding easier and quicker.
It Is arranged on a matrix format so that individual kit
parts can be easily located and identified. Space is provided at the top of the breadboard for identifying the circuit title, the design engineeJ, the revision, as well as
the data of construction. The interdigitated metal runs
are designed to serve as V+ and ground for single supply applications; or as V + and V - with the outside border serving as ground or dual supply applications. An
edge connector has been provided so that you can easily connect your breadboard to power supplies, signal
sources and test equipment, without having to solder
leads directly to the breadboard. This allows you to disconnect the breadboard to test kit parts on a curve
tracer or to make circuit modifications without destroying your test setup.
BREADBOARDING
After a circuit has been designed and analyzed on paper, it is time to reduce the theoretical design to a functioning circuit that will duplicate, as closely as possible,
the operation of the finished integrated circuit. This is
the purpose of breadboarding. A great deal of care
needs to be taken during this phase of IC development.
Accurate breadboarding will not only allow you to gain
an accurate assessment of the performance you can
expect from the finished IC, but it will also allow you to
discover circuit design flaws. A correctly connected,
nonfunctional breadboard is a very vivid indication that
something has been overlooked. Changes can be made
2-30
Kit Part #
20V
Masterchips
101
XR-A-
103
108
111
112
114
117
206
202
210
213
215
216
V'
V'
421
V'
XR-B-
V'
XR-F-
V'
V'
V'
V'
XR-J-
V'
XR-M-
V'
V'
V'
V'
36V
Masterchips
XR-D-
V'
XR-W-
V'
V'
V'
V'
V'
V'
V'
V'
V'
75V
Masterchips
XR-X-
V'
General Notes on Kit Parts
1) Dual collector PNP's will have both collectors tied together and acting as one collector unless shown otherwise in a kit part outline.
2) Kit parts with small NPN's use all available collector
contacts on each device. The designer should note
that if fewer than the full complement of collector
contacts (generally four) are used when designing
the I.C. layout, slightly degraded performance may
result.
3) For proper operation of these kit parts the substrate
pin, labeled -:!:- ,must be tied to the lowest potential
in the circuit. Resistor kit parts require connection to
both the most positive and most negative potentials
within a circuit for proper operation.
Breadboarding Recommendations
For Designs Using
Exar Master-Chip
Use Kit Parts
Al00
Bl00
ClOO
XR-A-NNN*
XR-B-NNN
D100
XR-D-NNN
El00
F100
Gl00
Hl00
Jl00
K100
L100
M100
XR-F-NNN
XR-J-NNN
XR-M-NNN
Ul00
Vl00
Wl00
XR-W-NNN
Xl00
XR-X-NNN
4)
5)
.-0::
Denotes transistors designed to operate
above 10 mA.
~
Denotes Schottky transistors.
6) J;:N:i:- Denotes pinch or FET resistors.
Resistor networks RN 1 and RN2 are only available for
Exar's 20V process. RN3 devices are available for both
20V and 36V operation. To order, specify:
RN1:
RN2:
RN3:
* NNN = Kit part number_
XR-A-104
XR-A-l05
XR-F-XXX
XR-W-XXX
For 20V operation
For 36V operation
xxx = Resistor value in kQ. Avalilable Values for base
diffused and ion implant resistors are shown below.
Ordering Information
ION IMPLANT
BASE
Additional or extra kit parts may be ordered from your
local distributor or Exar representative. To order, specify the desired device(s) by using the part number code as
shown above.
Example: XR-F-101
XR-J-215
XR-W-421
2-31
Value
XXX
3.6K
1.8K
9000
4500
2000
3R6
1R8
R90
R45
R20
Value
50K
20K
10K
5K
1K
XXX
50R
20R
lOR
05R
01R
EXAR LINEAR KIT PARTS
101
111
103
108
112
114
2 Medium NPN's
2 Large Vertical PNP's
1 Small NPN
117
,..-------.
202
~---.
2-32
206
EXAR LINEAR KIT PARTS
210
213
215
NOTE: 5 Small & 2 Large Vertical PNP's.
Resistance shown Is substrate
resistance between middle and
edge of die.
216
421
NOTE: Drain and Source
are Interchangeable
Resistor Networks
RN1
RN2
RN3
NOTE: All resistors are the same value
2·33
ELECTRICAL CHARACTERISTICS OF LINEAR MASTER-CHIP COMPONENTS
The following tables list the electrical characteristics of the circuit components available on Exar's linear MasterChips. Whenever applicable, the "worst case" tolerances and the parameter distributions are also listed.
PARAMETERS
Small-Signal NPN Transistors
Current gain (hFE) @ 1 mA, 5V
Temperature Coefficiency of hFE
- 55°C to 25°C
25°C to 125°C
Matching of hFE
Breakdown voltage (LVCEO)
20-V Master-Chips
36-V Master-Chips
Collector-Base Leakage Current @ 20 V
Cutoff Frequency (tT) @ 5 mA
Storage Time (t s)
Saturation Resistance (All except D100)
One collector contact
Two collector contacts
Saturation Resistance (D1 00 chip)
One collector contact
Two collector contacts
TYPICAL VALUES
a-LIMIT
180
-
+0.5%/oC
+1%/oC
-
23V
40V
1 nA
500 MHz
50 nsec
-
WORST CASE
TOLERANCE
80-300
-
3%
10%
-
20-30V
36-50V
0.1-50 nA
-
-
100 Ohms
50 Ohms
±50 Ohms
±20 Ohms
60-160 Ohms
30-80 Ohms
300 Ohms
150 Ohms
± 100 Ohms
±50 Ohms
150-480 Ohms
75-240 Ohms
High-Current NPN Transistors
Current Gain (hFE)
@ 1 mA,5V
@ 100 mA, 5V
Temperature Coefficient of hFE
- 55°C to 25°C
25°C to 125°C
Matching hFE
Breakdown Voltage (LVCEO)
Collector-Base Leakage Current @ 20V
Cutoff Frequency (tT)
Storage Time (Is)
Saturation Resistance
180
100
-
+0.5%/oC
+1%/oC
-
23V
20 nA
100 MHz
200 nsec
5 Ohms
3%
-
-
-
±10hm
80-300
50-200
10%
20-35V
1-500 nA
3-8 Ohms
Lateral PNP Transistors
Current Gain (hFE) @ 100 ,.,.A, 5V
Temperature Coefficient of hFE
Matching ot hFE
Breakdown Voltage (LVCEO)
20-V Master Chips
36-V Master Chips
Collector-Base Leakage Current @ 20V
Cutoff Frequency (tT)
Storage Time (t s)
Saturation Resistance
20
±1.0%/oC
35V
45V
5 nA
5 MHz
500 nsec
600 Ohms
-
5%
-
5-80
15%
25V-40V
36-60V
0.1 to 100 nA
-
-
± 100 Ohms
300-900 Ohms
±200 mV
2 mV
5,.,.V/oC
D.68-D.8V
6 mV
15,.,.V/oC
±200 mV
3 mV
8,.,.VfOC
0.62-0.76V
5 mV
25,.,.V/oC
TRANSISTORS CONNECTED AS DIODES
(Collector and Base Shorted)
Small NPN
Forward Voltage
Forward Voltage
Forward Voltage
Lateral PNP
Forward Voltage
Forward Voltage
Forward Voltage
Drop @ 1 mA, 25°C
Matching
Tracking
0.74V
Drop @ 200 ,.,.A, 25°C
Matching
Tracking
0.7DV
2-34
PARAMETERS
TYPICAL VALUES
u-LlMIT
WORST CASE
TOLERANCE
6.35V
6.7V
+2.5 mVloC
±0.15V
±0.2V
±0.3 mVloC
5.9-6.8V
6.0-7.2V
1.8-3.1 mV/oC
0.36V
±0.02V
0.22 to 0.44V
-1.5 mVloC
30V
200 nA
±0.1 mV/oC
-
±0.3 mVloC
20-40V
1 nA-lp.A
±10%
±25%
NPN Base-Emitter Junctions Used
as Zener Diodes
Small NPN Transistors
Breakdown Voltage @ 100 p.A
20·V Master Chips
36·V Master Chips
Temperature Coefficient
Schottky-Barrier Diodes
(AI DDIBI DDICI DO Only)
Forward Voltage Drop @ 10 p.A
Temperature Coefficient of Forward
Voltage Drop
Reverse Breakdown Voltage
Leakage Current @ 20V
Dillused Resistors (All Master-Chips)
Absolute Values
Temperature Coefficients
- 55°C to - 25°C
-25°C to O°C
O°C to 25°C
25°C to 75°C
75°C to 125°C
Matching Between Resistors
Identical Values
Non·ldentical Values
200-450
200-900
200-1.8K
200-3.6K
450-900
450-1.8K
450-3.6K
900-1.8K
900-3.6K
1.8K-3.6K
-650 ppmloC
+150 ppmloC
+680 ppmloC
+ 1040 ppmloC
+ 1400 ppmloC
±100 ppm
±40 ppm
±40 ppm
±20 ppm
±40 ppm
-
-
±0.8%
±2.4%
-
±1.6%
±1.7%
±1.9%
±2.0%
±1.5%
±1.7%
±1.9%
±1.5%
±1.7%
±1.5%
±4.8%
±5.1%
±5.7%
±6.0%
±4.5%
±5.1%
±5.7%
±4.5%
±5.1%
±4.5%
-
-
-
-
Pinch-Resistors
Absolute Value Tolerance
Matching Between Identical Resistors
Breakdown Voltage
Temp. Coefficient
±50%
±20%
6.4V
+ 6,000 ppmloC
2·35
-
-
+100% to -50%
-
8,000 ppmloC
12L SEMI-CUSTOM DESIGN
used with 12L Master-Chips to be generated simultaneously from a customer's pencil layout on the MasterChip worksheet. This unique mask generation technique, and the three-mask customizing method, are the
heart of Exar's 12L semi·custom program. In this manner, one is able to combine low cost, quick turnaround
capabilities of semi-custom designs with the high functional density of 12L technology, and still make very efficient use of the chip area.
Integrated Injection Logic (12L) technology extends the
capabilities of semi-custom design to high complexity
digital or combined analog/digital systems. Exar has
made this possible by the development of a family of
12L Master-Chips which combine a large number of 12L
gates and Schottky bipolar transistors on the same
chip. Similar to its bipolar counterpart, Exar's 12L semicustom program also utilizes partially fabricated silicon
wafers which are then customized by the application of
special mask patterns.
WHEN TO USE DIGITAL SEMI-CUSTOM
Exar's 12L Master-Chips utilize bipolar input/output (I/O)
interface circuitry on the same chip with the high density 12L logic arrays. Thus, outwardly the 12L semicustom chip looks and performs exactly as a bipolar LSI
chip, which can readily interface with TIL level signals.
In other words, these gate array Master-Chips combine
the high functional density advantages of 12L technology with the interface and load drive capability of the bipolar circuitry on the same IC. This feature makes it
very convenient to retrofit 12L LSI designs into existing
TIL type logic systems.
The key application of 12L semi-custom design is to replace complex blocks of random logic with a single
monolithic chip. An entire digital subsystem comprised
of many SSI or MSI chips, or discrete components, can
be put on a single 12L Master-Chip. This can provide
significant cost and space savings and greatly improve
system reliability. The availability of bipolar input/output
interface circuitry on the same chip with the high density 12L logic makes it very convenient to retrofit 12L designs into existing TIL logic systems. Therefore, semicustom 12L LSI designs provide cost effective solutions
for complex custom LSI requirements, even at production volumes as low as a few thousand pieces.
ACHIEVING HIGH COMPLEXITY
Traditionally, the application of semi-custom technology
to complex digital systems has been somewhat limited
due to one key factor; in order to be economically feasible, a complex digital LSI circuit must achieve a high
functional density on the chip (high gate count per unit
of chip area). This requirement is not compatible with
the random interconnection concept which is key to the
semi-custom or Master-Chip design technique. Exar's
approach overcomes this limitation, by making use of
the unique layout and interconnection properties of 12L
gates, and by extending the customizing steps to mask
layers. In addition to the metal interconnection pattern,
Exar can achieve high packing density and still retain
the quick turnaround features and low cost of semicustom.
FEATURES OF 12L TECHNOLOGY
High Functional Density: 12L logic gates offer a much
smaller size than their bipolar counterparts. Thus, a
much higher degree of logic complexity or functional
density can be achieved on a given IC chip.
Easy to Interconnect: Unique structure and geometry of
121 gates make them ideal for semi-custom design. An
entire array of gates can be easily customized and interconnected using only three masks without sacrificing high functional density.
Bipolar Compatible Processing: 12L is a direct derivative of
conventional bipolar Ie technology. Therefore, one can
combine bipolar devices on the same chip as 12L gates.
This feature has the following key advantages:
Exar's 12L Master-Chips are customized by not one but
three mask layers:
• Input/output section of 12L chips are bipolar. Thus,
they can readily interface with existing logic families
or retrofit into existing systems.
1. A custom diffusion pattern to define gate outputs
and custom underpasses for interconnection.
2. A custom contact mask which opens contact windows or activates only those devices actually used
in the design.
o Analog and digital functions can be combined on the
same chip. One of Exar's Master-Chips, the XR-400,
is specifically deSigned for such an application.
3. A custom metal interconnection mask which interconnects all the activated devices.
FULLY AUTOMATED MASK GENERATION
Low Voltage Operation: 12L gates can operate with supply
voltages as low as one volt, and require only a single
power supply.
Exar has developed a fully automated mask generation
technique which allows all three custom mask layers
Low Current and Low Power Operation: Depending on
speed requirements, 12L gates can operate with current
2-36
LOGIC CONVERSION TO 12L GATES
levels in the nanoampere range. This feature, along
with its low voltage operation makes it ideal for applications in low power, battery operated systems.
Converting conventional logic diagrams from their
NAND/NOR gate equivalents to 12L gates is a simple
and straightforward procedure. This information is contained in the 12L Design Manual, which is available as a
part of Exar's 12L Design Kit. In addition, Exar has developed a large library of 12L logic subblocks corresponding to popular logic functions, such as decoders,
flip-flops and counters, which greatly simplifies this
conversion process.
Higher Reliability Than MOS: Since 12L gates have the
same basic features as bipolar transistors, they are not
subject to electrostatic burn-out problems associated
with MOS transistors and do not require special handling precautions.
Wide Operating Temperature: 12L gates are not seriously
affected by leakage currents as are their MOS counterparts. Thus, they can accommodate the full military
temperature range.
,,
III
!u '.'
!l
~, .. oo
iI..
IOn.
DESIGNING WITH 12L MASTER·CHIPS
Exar currently has four 12L Master-Chips in production.
These are the XR-200, XR-300, XR-400 and the XR-500
Master-Chips. The XR-200, XR-300 and the XR-500 are
designed for digital systems. The XR-400 Master-Chip is
intended for systems requiring both analog and digital
functions.
,
'" , /I"'\.IIOS
,, , I-"
,
12:""
'~hNIIOS
,,
t=fj, WLTTL,
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, 54LS ttL
~ f:l
,,
,,
,,
TTL
,Opt
•.OP,
O" ..PI
,,
"', £CL o EC
,,
'JOK
I~
All four of these Master-Chips are fabricated with the
same manufacturing process. They differ only in their
architecture and in the number of components. All of
these chips are especially designed for Exar's unique
three-mask customization process using fully automated mask generation techniques.
$4"
0
'oo
I~W
10~W
l00J£W
lmW
POWER/GATE
HlmW
"'
l00mW
COMPARISON OF SPEED AND POWER CAPABILITIES
OF VARIOUS LOGIC FAMILIES
XR·200, XR·300 and XR·50D MASTER·CHIPS
These Master-Chips are primarily designed for applications requiring only digital signal processing. They contain a large number of multiple output 12L gates along
with Schottky bipolar input/output buffers. Except for
the difference in size, all three chips have the same architecture shown below. The 12L gates are arranged in
array form at the center of the chip and the input/output
buffers are located along the periphery of the chip. The
bipolar I/O sections of the chips contain two identical
sets of resistor arrays located at opposite ends of the
chip which are used for biasing the injectors of the 12L
gates. The XR-200 contains 192 five-output 12L gates
and 24 I/O buffers. The XR-300 contains 288 five-output
12L gates and 28 I/O buffers. The XR-500 contains 520
five-output 12L gates and 40 I/O buffers. A detailed description of the bipolar input/output interface circuitry is
given further on in the text.
THE BASIC 12L GATE
The 12L logic technology is derived from the basic single input, multiple output inverter circuit shown below.
The logic functions are performed in a manner similar
to the conventional open-collector logic. The outputs of
various gates are interconnected together in a wiredAND configuration. Many sections of the 12L gate share
common semi-conductor regions. For example, the collector of the pnp is the same as the base of the npn,
and the emitter of the npn is the same as the base of
the pnp. This leads to a very compact device structure
which occupies a correspondingly small chip area. As a
result, the functional density of 12L gates is comparable
to that of some MOS technologies and is approximately
5 times higher than conventional TTL logic.
THE BASIC 12L GATE
(a) Actuat Gate
(b) Equivalent Circuit
2-37
(c) LogiC" Symbol
BIPOLAR I/O INTERFACE
INPUT/OUTPUT
INTERFACE
INPUT/OUTPUT
INTERFACE
BIPOLAR I/O INTERFACE
BASIC LAYOUT OF XR-400 MASTER CHIP
BASIC LAYOUT OF XR-200, XR-300 AND XR-500
MASTER CHIPS
Components on XR 12L Master-Chips
XR-400 MASTER-CHIP
The XR-400 Master-Chip Is designed primarily for applications requiring the combination of analog and digital
functions on the same chip. Thus, it is made up of both
a linear and a digital section. The digital section of the
chip has the same basic architecture as the XR-300. It
contains 256 five-output 12L gates and 18 Schottky bipolar 1/0 interface sections. The linear section of the
chip is made up of an array of npn and pnp transistors
and resistors' and is very similar to Exar's bipolar
Master-Chips.
Quantity
Componan! Typa
XR·200
XR·300
XR·400
XR·500
5-0utput 12L Gates
192
288
256
520
24
28
18
40
7V
7V
7V
7V
0
0
45
0
0
0
12
0
0
0
0
0
0
0
200
116
20
0
0
0
Schottky-Bipolar
1/0 Interfaces
Max Operating
Voltage
NPN Transistors
4-Collector PNP
Transistors
Diffused Resistors
700(1
2.5 K
5K
COMPONENT UTILIZATION
The unique three-mask customizing technique used in
Exar's 12L Master-Chips makes them very efficient for
both ease of logic layout and component utilization.
One of the three customizing mask steps is a custom
diffusion step which allows the placement of low resistance crossunders, or underpasses, selectively on the
chip. This technique provides the designer with virtually
two layers of interconnection on the chip and, thus,
greatly simplifies the logic layout and improves the
component utilization efficiency. Normally, in the case
of random combinational logiC, one can easily utilize
60% to 80% of the total gates available on a given 12L
Master-Chip. In the case of sequential and repetitive
logic circuits, the gate utilization is normally as high as
80% to 100%.
Bonding Pads
Chip Size (mils)
In the case of the XR-400 Master-Chip, which combines
analog circuit components and digital gates on the
same chip, the three-mask customizing technique is
applicable to the digital section, while the analog section of the chip is customized with one mask in the
same way as the linear Master-Chips.
2-38
30
34
40
42
98 x 119
106 x 144
119 x 149
122 x 185
-1 1'---_--'
I!
~~
iI
ii
THE 12L GATE ARRAY SECTION
L-
P·TVPE"FINGER"
DIFFUSION FOR
12 lGATES
This section of the 12L Master-Chip is made up of logic
cells which contain a number of multiple output 12L inverters grouped together. The figure below shows a typicallayout of such a cell made up of eight multiple output inverters which share a common set of four injectors. The basic gate cells forming the 12L gate array are
made up of p-type injectors and p-type gate fingers
which serve as the base regions of the 12L gates. The
six dots on each gate area indicate the possible locations (or sites) for gate inputs or outputs. The particular
use of these sites as an input or output is determined
by two custom masks. An n-type collector diffusion
mask defines the locations of outputs and a custom
contact mask opens the appropriate input and output
contacts. Finally, a third custom mask is applied to
form the metal interconnections between the gates and
the gate cells. The custom n-type diffusion step, which
determines the locations of gate outputs, is also used
for forming low resistivity underpasses between the
gate cells. The area between each of the gate cells can
accommodate two or three parallel underpasses in the
horizontal or vertical direction. Since the n-type diffusion which forms these underpasses is a part of the
customizing step, the location and length of each underpass can be chosen to fit a given interconnection
requirement. This method provides the designer with
virtually all of the advantages and capabilities of mUltilayer interconnection paths on the surface of the chip
and allows approximately 80% of the gates on the chip
to be utilized in a typical logic layout.
The custom logic interconnections can be easily laid
out in pencil on a layout sheet by simply interconnecting the desired gate sites with a pencil line and appropriately defining the function of the site as an input, output, injector contact or an underpass. The function of
each of the potential sites is defined by simply drawing
an appropriate symbol on it, such as a circle for an output and a square for an input, as defined in the example
below.
ADJACENT
CELL
~
II
....
i i e~~~
Ii
~"
I
lj- . . .
I
I
DOTS INDICATE LOCATION 0
BASIC 8 GATE CELL PRIOR TO CUSTOMIZATION
__
o
o
.. METAL INTERCQNNECTI(lfIf
-INJECTOl!.CONTACT
.
-GATE OUTPUT
o
"GATEINP\JT
~.UNDlR'AU
"--_---'I
~
-
IN~l- ~
!e
0,
:;
~
~ i';'
I~
INJECTO"
IUS
~1Y
~~
.,- ~~ I- ~
0,
-
'--
II
I
SAMPLE PENCIL LAYOUT ON MASTER CHIP
WORKSHEET
~
.-J
"'"'
,-GATE OUTPUT
r-
:,
~
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i ~Ha!
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:;-
~[az
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it'
~~IFFUS m
UNDER 'ASS
~fJlti
-
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INJECT
a'
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-
0,
-
.,
I
I
I
SAMPLE LAYOUT OF 8 GATE CELL AFTER
CUSTOMIZING WITH N+ COLLECTOR DIFFUSION,
CONTACT MASK AND METAL INTERCONNECTION
PATTERN
2-39
BIPOLAR INPUT/OUTPUT INTERFACE SECTION
~
R7 =
500 u
D
[EJ
~1~S1
BONDING
PAD
The bipolar Inputloutput Interface sections of the 12L
Master-Chips are located along the periphery of the
chips. The component locations in a typical 1/0 cell are
shown in the adjacent figure. Each 1/0 cell is designed
to be either an input or an output Interface depending
on the choice of the metal interconnection pattern applied to the cell. Furthermore, two adjacent cells can
be combined together to provide a three-state type output buffer. Some of the basic input and output circuit
configurations available from the 1/0 interface are
shown below. In the case of a three-state output configuration, one would also utilize several gates from the
12L logic section to perform the necessary gating functions.
01
IU~S2
II
:~J;
02
-
R2 = 10 K
Each Inputloutput interface cell contains one bonding
pad, several resistors of varying values, a clamp diode
to substrate and two npn transistors with optional
Schottky diode clamps. Each npn transistor is capable
of sinking 5 mA of current with Schottky diode clamps
and 10 mA of current without, at a saturation voltage of
:s 0.5V. The breakdown voltage of the bipolar I/O section Is 7V.
Rl = 10 K
A TYPICAL SCHOTTKY-BIPOLAR INPUT/OUTPUT
INTERFACE CELL
, - - -.....-11'
INPUT
SK
20K
OUTPUT
(a) Input Interlace Circuit
(b) Outpul Interface Circuit
15K
DATA INPUT
FROM 12L
GATES
10K
10K
--~- 1 MHz)
Low-Frequency «1 MHz)
In many of the applications, more than one product
type is recommended. In such cases, the user can
choose the device best suited to his specific application by either consulting with Exar's Applications department, or by reviewing the electrical specifications
of the individual devices involved.
Low-Power
Carrier-Tone Transceiver
Clock Generation (See Oscillators)
Low-Frequency ( < 1 MHz)
Low-Power
*AOVANCEO INFORMATION
High-Frequency
Phase Locked
A
Clock Extraction
Phase Locked
Active Filters
XR-084. XR-094.
XR-096. XR-346.
XR-3403. XR-4202
Acoustical Couplers (See Modems)
XR-2206. XR-2207,
XR-2211
ND Conversion (Pulse Counting Type) XR-2240
Amplitude Detection
XR-215IXR-2228,
Phase-Locked AM Detection
XR-2212IXR-222B
Synchronous AM Detection
XR-S200, XR-2208,
XR-222B
XR-2276, XR-2277,
Amplitude Level Detection
XR-2278, XR-2279
Amplitude Modulated Oscillator
XR-205, XR-2206
Crystal Controlled AM Oscillator
XR-S200. XR-205
Amplitude Modulation
XR-2206, XR-220B,
XR-2228. XR-13600
Analog Computation
Analog Multiplication/Division
XR-2208, XR-2228
Analog Square/Square-Root OperationXR-2208
Analog-To-Frequency Conversion
XR-2209., XR-4151
Analog Sample-Hold
XR-13600/XR-OB2
Analog Semi-Custom Design
XR-Al00, XR-Bl00,
(Master Chips)
XR-Cl00. XR-Dl00.
XR-Fl00, XR-Gl00,
XR-Xl00
XR-555, XR-556,
Appliance Timing
XR-55B, XR-559,
XR-2240, XR-2242,
XR-2243
XR-5532, XR-5534
Audio Amplifier/Preamp
XR-2276, XR-2279
Audio Level Detector
Automatic Gain Control (AGC)
XR-220B, XR-2216.
XR-2228, XR-13600
PCM Signal Clock
Clock Pattern Generation
Clock Synchronization
High-Frequency (>1 MHz)
Low-Frequency « 1 MHz)
Commandor (Speech/Data)
Current-to-Frequency Converter
Current Drive
XR-215/XR-2228
XR-567A, XR-2211,
XR-L567
XR-L567
XR-2567
XR-555. XR-2209.
XR-2242
XR-L555. XR-L556,
XR-2243
XR-205
XR-215, XR-2212,
XR-2213
XR-210. XR-215,
XR-2212, XR-2213
XR-C262. XR-C277
XR-2240
XR-210, XR-215
XR-2212, XR-2213
XR-2216
XR-2206, XR-2207,
XR-2209
XR-2247, XR-2247A
o
Darlington Arrays
(High-Current, High-Voltage)
Data Synchronization
High-Frequency (> 1 MHz)
Low-Frequency « 1 MHz)
DC/DC Converter (See
Switching Regulators)
3-2
XR-2200, XR-2201,
XR-2202, XR-2203,
XR-2204, XR-2001,
XR-2002, XR-2003,
XR-2004, XR-2011,
XR-2012, XR-2013,
XR-2014
XR-210, XR-215
XR-2212, XR-2213
XR-1524, XR-2524.
XR-3524, XR-1525A,
XR-1527A,
XR-2525A,
XR-3525A,
XR-2527A,
XR-3527A
Detector
FM
FSK
Tone
PSK
Amplitude Level
Amplitude Modulation
Differential Multiplier
Digital Sample/Hold
Digital Semi-Custom Design (12L,
CMOS Gate Arrays)
Complete Digital Design (12L)
Complete Digital Design (CMOS)
Combined Analog/Digital Design
Display Driver
Fluorescent
Bar-Graph
Plasma Displays
Division (Analog)
Division (Frequency)
Dual Operational Amplifiers
Dual-741 Type
High-Frequency (> 1 MHz)
Low-Frequency « 1 MHz)
XR-215, XR-2122
XR-210, XR-2211,
XR-14412, XR-2122
XR-567, XR-L567,
XR-2211, XR-2567,
XR-2122, XR-2123
XR-2276, XR-2279
XR-22DB
XR-222B
XR-224D
Frequency Division
Frequency Doubling
FM Detection
High-Frequency (> 1 MHz)
Low-Frequency « 1 MHz)
Low-Power
Dual Tone Detector
XR-215
XR-215, XR-2212,
XR-2213
FM Generation
High-Frequency (> 1 MHz)
Low-Frequency « 1 MHz)
XR-2DD, XR-3DD,
XR-5DD
CMA, CMB, CMC,
CMD
XR-4DD
XR-S2DD, XR-2D5
XR-22D6, XR-22D7,
XR-22D9, XR-BD3B
Frequency Multiplication (Synthesis)
High-Frequency (> 1 MHz)
Low-Frequency « 1 MHz)
Frequency Translation
High-Frequency (> 1 MHz)
Low-Frequency « 1 MHz)
FrequencyNoltage (F/V) Converter
Wideband
Narrow-Band
FSK Detection (Decoding)
High-Frequency (>1 MHz)
Low-Frequency « 1 MHz)
FSK Generation (Encoding)
High-Frequency (> 1 MHz)
Low-Frequency « 1 MHz)
XR-2271, XR-2272,
XR-611B, XR-612B
XR-2276, XR-2277,
XR-227B, XR-2279
XR-22B4, XR-22B8
XR-22D8
XR-224D
XR-1458, XR-455B,
XR-4739
XR-5532, XR-5533
XR-D82, XR-D83
XR-13600
XR-556, XR-2556,
XR-2567
XR-L556
XR-2567
Low-Noise
Bipolar FET
Transconductance
Dual Oscillator
XR-215
XR-2212, XR-4151,
XR-2213
XR-32D, XR-555,
XR-224D, XR-2242,
XR-2243
XR-22DB, XR-222B
Sinusoidal Output
Multiple Frequency Levels
FSK Modem (Modulator/
Demodulator)
XR-S2DD, XR-215
XR-2212, XR-2213
XR-215IXR-222B
XR-2212/XR-222B
XR-4151
XR-2212, XR-2213
XR-21 0
XR-2211, XR-14412,
XR-21 0
XR-22D6, XR-22D7,
XR-14412, XR-2121
XR-2206, XR-14412,
XR-2121
XR-22D7
.XR-22111XR-2206
XR-2211IXR-2207,
XR-14412,
XR-21211XR-2122
E
Electronic Gain Control
G
XR-22DB, XR-2216,
XR-2228, XR-136DD
XR-2216
Expandor (SpeechlData)
F
Filters
Active Filters
Tracking Filters (Phase Locked)
Switched Capacitor
Floppy Disk
Read Amplifier
Write Amplifier
Fluorescent Display Driver
Medium Voltage (:s50V)
Hlgh-Voltage (>50V)
Bar-Graph Display
Frequency Detection (See
Tone Detection)
High-Frequency (> 1 MHz)
Low-Frequency « 1 MHz)
Multiple Frequency
Frequency Discriminator (See
FN Converter)
XR-2DO, XR-30D,
XR-400, XR-5DD
CMA, CMB, CMC,
CMD
XR-2D5, XR-2206,
XR-B038
XR-3403
XR-094, XR-346,
XR-34D3, XR-42D2,
XR-13600
Gate Arrays (See
Digital Semi-Custom)
Generator (See
Function Generators)
Ground-Sensing Op Amps
Gyrator Design
XR-D84, XR-D94,
XR-346, XR-34D3,
XR-4202
XR-S200, XR-215,
XR-2212
XR-2120, XR-2103
H
XR-3470A, XR-347DB
XR-2247, XR-2247A
Hammer Driver (See HighCurrent Drivers)
XR-2271, XR-2272
XR-6118, XR-6128
XR-2276, XR-2277,
XR-227B, XR-2279
High-Voltage Driver
XR-215/XR-2228
XR-567, XR-2211,
XR-2213
XR-2567
Indicator, Amplitude (See
AM Detector, Level Detector)
3-3
XR-22DD, XR-22Dl,
XR-22D2, XR-2203,
XR-2204
XR-6118, XR-6128,
XR-2284, XR-2288
XR-2208, XR-2228,
XR-2276, XR-2279
Indicator, Frequency (See
Frequency Detector)
Intercom
XR-215, XR-2212,
XR-4151
XR-2206/XR-2211,
XR-2567
XR-555, XR·L555,
XR-556, XR·L556,
XR-558, XR-559
Interval Timing
Pro~rammable
Ground Sensing Quad Op Amp
Ultra Low·Noise Op Amp
Bipolar FET Op Amps
Dual Bipolar FET
Quad Bipolar FET
Programmable Bipolar FET
L
LED Driver
XR-2200, XR-2201,
XR-2202, XR-2203,
XR-2204
XR-320, XR-2207
XR-2206, XR-2207,
XR-2209
XR-2216
XR-1488
XR-1489A
XR-2242, XR-2243
XR·L555
XR·L567
XR·L555, XR·L556,
XR-2243
XR·L555, XR·L556,
XR-2243
Linear·Ramp Generation
Linear·Sweep Oscillator
Line Compandor
Line Driver (RS-232C Spec)
Line Receiver (RS-232C Spec)
Long Delay Generation
Low·Power Oscillator
Low·Power PLL
Low·Power Timer
Low·Voltage Timer/Oscillator
Quad Op Amp
XR:4136, XR-4212,
XR·4741
XR·094, XR·095,
XR·096, XR-346,
XR·4202
XR-3403
XR-5532, XR-5333,
XR-5534
XR·082, XR·083
XR·084
XR·094, XR·095,
XR·096
Operational Transconductance
Amplifier (OTA)
XR-13600
Oscillators (See Function Generators)
XR-205, XR-210,
High·Frequency Oscillator
(>1 MHz)
XR-215
Low·Frequency Oscillator
XR-2206, XR-2207,
«1 MHz)
XR-2209, XR-8038,
XR-8038A
High·Current Output Oscillator
XR-567
Low·Cost Oscillator
XR·555, XR·L555
Low·Power Oscillator (Single)
XR·L555, XR·L567
Low·Power Oscillator
XR·L556, XR-2243
XR-558, XR-559
Dual Oscillator
Sinusoidal Output
XR-205, XR-2206,
XR-8038
XR-2206, XR-2207
FSK Keyed Oscillator
Oscillator with Quadrature Outputs XR-2212
M
P
Micropower Circuits (See Low·Power)
Micropower Oscillator
XR·L555, XR·L556
Micropower Tone Decoder (PLL)
XR·L567
Micropower Timer
XR·L555, XR·L556,
XR-2243
Missing Pulse Detection
XR-320, XR-555,
XR·L555
Modem Filter Design
XR-346, XR-3403,
XR-4202, XR-2120,
XR-2103
Modem (Frequency·Shift Keyed)
XR-210, XR-2206,
XR-2207, XR-2211,
XR-14412,
XR-21211XR-2122
(Phase·Shift Keyed)
XR-2121 IXR-2122
XR-2123
Modulators (See Multipliers)
XR-205, XR-2206
Amplitude Modulator
FSK Modulator
XR-2206, XR-2207,
XR-2121
Frequency Modulator
XR-205, XR-2206,
XR-2209
XR-2121*, XR-2123
PSK Modulator
XR-2212
Phase Modulator
Motor·Speed Control
XR-2208, XR-2212,
XR-2213
Multi·Function PLL
XR·S200
Multiplier, Analog
XR-2208, XR-2228
PCM Repeater (See Regenerator)
Phase·Comparator (Phase·Detector)
Phase· Locked Loop
High·Frequency (>1 MHz)
Low·Frequency « 1 MHz)
Ultra·Stable
FM Detector
FSK Detector
Tone Detector
Low·Power
AM Detector
Stero Decoder
Plasma Display Driver
Power Supply Supervision
Power·On·Reset
Precision Oscillator
Precision PLL
Process Controller
Programmable Op Amp (See
OpAmps)
Quad Bipolar
0
Quad Bipolar FET
Operational Amplifiers
Single Op Amp
Dual Op Amp
Quad OpAmp
XR-5534
XR·082, XR·083,
XR-1458, XR-4558,
XR-4739
XR·084, XR-3403,
Programmable Oscillator
Programmable Timer
PSK Generator (Bipolar·phase
and Quad·phase
3-4
XR·C240, XR·C262,
XR·C277
XR-2208, XR-2228
XR·S200, XR-210,
XR-215
XR-567, XR·L567,
XR-2567, XR-2211,
XR-2212, XR-2213
XR-2211, XR-2212
XR-215, XR-2212
XR-210, XR-2211
XR-567A, XR·L567,
XR-2567
XR·L567
XR-215/XR-2228,
XR·2212/XR-2228
XR-1310
XR-2284, XR-2288
XR-1543
XR·320, XR-555,
XR·L555
XR-2206, XR-2209,
XR-8038A
XR-2212, XR-2213
XR-2206IXR·2211,
XR-2240, XR-4151
XR-346, XR-346-2,
XR-4202
XR·094, XR·095,
XR·096
XR-2206, XR-2207
XR-2240
XR-205, XR-2206,
XR-2228, XR-2121 ,
XR-2123
Pulse Blanking
Pulse-Code Modulation (PCM)
Regenerator
Pulse Counting
Pulse Generation
Pulse-Position Modulation (PPM)
Pulse-Proportioned Servo Controller
Pulse Shaping
Pulse Stretching
Pulse-Width Modulation (PWM)
Pulse-Width Modulating Regulator
XR-556, XR-2556
XR-C240, XR-C262,
XR-C277
XR-2240
XR-320, XR-555,
XR-L555, XR-556
XR-320
XR-2264, XR-2265,
XR-2266
XR-555, XR-556,
XR-558, XR-559
XR-320, XR-555,
XR-556
XR-320, XR-555
XR-1524, XR-2524,
XR-3524, XR-1525A,
XR-2525A,
XR-3525A,
XR-1527A,
XR-2527A,
XR-3527A
Low-Frequency « 1 MHz)
Simultaneous AM/FM Detection
Simultaneous AM/FM Generation
Sine Wave Converter
Sine Wave Generator
Solenoid Driver (See
Relay Driver)
Speech Compandor
Square-Root Extraction
Squaring (Analog)
Stable PLL
Stereo Demodulator (Decoder)
Suppressed Carrier AM Generator
Sweep Generation (See
Saw-Tooth Generation)
Switching Regulators
Q
Synchronization (Clock Frequency)
Synchronous AM Detection
XR-2208, XR-2228
XR-2212
Quadrature AM Detector
Quadrature-Output Oscillator
Radio-FM I.F_ Demodulation
-AM I.F. Detection
Relay Driver (See
Hammer Driver)
Remote-Control Timer/Sequencer
Remote-Control Transceiver
Reset Controller (See
Power-On Reset)
XR-2264, XR-2265,
XR-2266
XR-215
XR-2228
XR-2200, XR-2201,
XR-2202, XR-2203,
XR-2204
XR-L555, XR-L556,
XR-2240
XR-567A, XR-L567,
XR-2567
XR-L555, XR-L556
Telecommunication Circuits
PCM Repeater (T1-type)
Speech Compandor
Tone Decoder (PLL-type)
Tone Encoder
Timing Circuits (Timers)
General Purpose Timers - Single
General Purpose Timers - Dual
General Purpose Timers - Quad
Low-Power Timers
Long Delay Timer
Programmable Timer
Tone Decoder (PLL-type)
General Purpose - Single
General Purpose - Dual
Precision
Low-Power
Tone Encoder
Tracking Filter
High-Frequency (> 1 MHz)
Low-Frequency « 1 MHz)
Tracking Regulator
S
Sample/Hold (See Bipolar
FET Op Amps)
Saw-Tooth Generator
Semi-Custom Design
Linear Master-Chips
Digital (12L) Master-Chips
Digital (CMOS) Master-Chips
Sequential Timing
Sequential Tone Decoding
Servo Controller/Driver
Signal Conditioning
High-Frequency (> 1 MHz)
XR-1524, XR-2524,
XR-3524, XR-1525A,
XR-2525A, XR-3525A,
XR-1527A, XR-2527A,
XR-3527A, XR-2230,
XR-494, XR-495
XR-215, XR-2212
XR-215/XR-2228,
XR-2212/XR-2228
T
R
Radio-Controlled Servo Driver
XR-2212, XR-2213
XR-215/XR-2228,
XR-2212/XR-2228
XR-205, XR-2206
XR-2212/XR-2228
XR-205, XR-2206,
XR-8038, XR-8038A
XR-2200, XR-2201,
XR-2202, XR-2203,
XR-2204
XR-2216
XR-2208
XR-2208, XR-2228
XR-2211, XR-2212
XR-1310
XR-205, XR-2206,
XR-2208, XR-2228
XR-320, XR-2207
XR-082, XR-084
XR-320, XR-2207
XR-A100, XR-B100,
XR-C100, XR-D100,
XR-E100, XR-F100,
XR-G100, XR-H100,
XR-L100, XR-M100,
XR-U100, XR-V100,
XR-W100, XR-X100
XR-200, XR-300,
XR-400, XR-500
CMA, CMB, CMC,
CMD
XR-566, XR-L566,
XR-588, XR-559
XR-567A, XR-L567
XR-2567
XR-2264, XR-2266
XR-C240, XR-C262,
XR-C277
XR-2216
XR-567, XR-L567,
XR-2211, XR-2567
XR-2206, XR-2207
XR-320, XR-555
XR-556, XR-2556
XR-558, XR-559
XR-L555, XR-L556,
XR-2243
XR-2242, XR-2243
XR-2240
XR-567A
XR-2567
XR-2211, XR-2213
XR-L567
XR-2206, XR-2207
Transceiver (Wireless Intercom)
Triangle-to-Sine Wave Converter
Triangle Wave Oscillator
TV Sound Detection
XR-S200, XR-215
XR-2212, XR-2213
XR-1468, XR-4194,
XR-4195
XR-2567
XR-2208, XR-2228
XR-2206, XR-2207,
XR-2209, XR-8038
XR-215
U
Ultra Low-Frequency Oscillator
Ultrasonic Remote Control
XR-S200, XR-215,
XR-2212
Universal Sine Wave Converter
3-5
XR-2242, XR-2243
XR-567, XR-2211,
XR-2567
XR-2212IXR-2228
Voltage-to-Frequency (V/F)
Conversion
v
Voltage-Controlled Amplifier
Voltage-Controlled OSCillator (VCO)
High-Frequency (> 1 MHz)
Low-Frequency « 1 MHz)
Ultra-Stable
Sinusoidal Output
Wide Linear Sweep
Voltage-to-Current Conversion
XR-2209. XR-4151
W
XR-220B. XR-222B.
XR-13600
Waveform Generator (See Oscillators)
XR-205
High-Frequency (> 1 MHz)
XR-2206. XR-2209.
Low-Frequency « 1 MHz)
XR-B03B. XR-B038A
Waveform Shaping/Modulation
XR-220B. XR-222B
Wideband Discriminator (FM)
XR-S200. XR-215
High-Frequency (> 1 MHz)
XR-2212. XR-4151
Low-Frequency «1 MHz)
Wireless Intercom
XR-215. XR-567A.
XR-2212
XR-S200. XR-205
XR-2206. XR-2207.
XR-2209. XR-B03BA
XR-2206. XR-2207.
XR-2209
XR-2206. XR-B03B.
XR-B03BA
XR-2207. XR-2209
XR-13600
3-6
AN·01
Stab~e
fSK M(Q)td1ems ffeaihJ1lTung
the XA,,22(Q)1 ~ XfR{,,22(Q)(5 ~lnldJ XR .. 2211
INTROOUCTION
The circuit connection for the XR-220e FSK Generator
is shown in Figure 1. The data input is applied to Pin g.
A high-level signal selects the frequency (1/ReC3) Hz; a
low level signal selects the frequency (lIR7C3) Hz, (resistors in ohms and capacitors in farads). For optimum
stability, Re and R7 should be within the range of 10 kO
to 100 kO. The voltage applied to Pin 9 should be select·
ed to fall between ground and V +.
Frequency-shift keying (FSK) is the most commonly
used method for transmitting digital data over telecommunications links. In order to use FSK, a modulator/
demodulator (modem) is needed to translate digital 1's
and O's into their respective frequencies and back
again. This application note describes the design of a
modem using state-of-the-art Exar devices specifically
intended for modem application.
Note: Over and under voltage may damage the device.
The devices featured in this application note are the
XR-220e and XR-2207 FSK Modulators, and the
XR-2211 FSK demodulator with carrier detect capability. Because of the superior frequency stability of these
devices (typically 20 ppm/DC), a properly designed modem will be virtually free of the temperature and
voltage-dependent drift problems associated with many
other designs. In addition, the demodulator performance is independent of incoming signal strength variation over a eo dB dynamic range. Because bias voltages are generated internally, the external parts count
is much lower than in most other designs. The modem
designs shown in this application note can be used with
mark and space frequencies, anywhere from several
Hz to 100 kHz.
Potentiometers, RS and Rg, should be adjusted for mini'
mum total harmonic distortion. Iri applications where
minimal distortion is unnecessary, Pins 15 and 1e may
be left open-circuited and RS may be replaced by a
fixed 2000 resistor.
PRINCIPLES OF OPERATION
+12V Q--<~-----l
THE XR·2206 FS({ MOOULATOR
FEATURES
Typically 20 ppm/DC Temperature Stability
Choice of 0.5% THD Sine Wave, Triangle,
or Square Wave Output
Phase-Continuous FSK Output
Inputs are TIL and CMOS Compatible
Low-Power Supply Sensitivity (0.01 %)
Low-Power Supply Sensitivity (0.01 'ioN)
Split or Single Supply Operation
Low External Parts Count
Figure 1. The XR·22D6 Sinusoidal FSK Generator.
The XR-220e is ideal for FSK applications requiring the
spectral purity of a sinusoidal output waveform. It offers
TIL and CMOS compatibility, excellent frequency stability, and ease of application. The XR-220e can typically
provide a 3-volt pop sine wave output. Total harmonic
distortion can be trimmed to 0.5%. If left untrimmed, it
is approximately 2.5%.
In applications where a triangular output waveform is
satisfactory, Pins 13 through 1e may be left open·
circuited.
The output impedance at Pin 2 is about eooo, with ac
coupling normally being used.
3·7
AN·01
+12V
THE XR-2207 FSK MODULATOR
FEATURES
RL
S.1K
4.7K
Typically 20 ppm/oC Temperature Stability
Phase-Continuous FSK Output
Provides Both Triangle and Square Wave Outputs
Operates Single-Channel or Two·Channel Multiplex
Inputs are TTL and CMOS Compatible
Split- or Single-Power Supply Operation
Low·Power Supply Sensitivity (0.15%N)
Low External Parts Count
The XR-2207 is a stable FSK generator which is designed for those applications where only a triangle or
square wave output is required. It is capable of either
single-channel or two-channel multiplex operation, and
can be used easily with either split- or single·power
supplies.
Figure 2. The XR-2207 FSK Modulator Single-Supply
Operation.
+6V
Figure 2 shows the XR-2207 using a single-supply and
Figure 3 shows split-supply operation. When used as an
FSK modulator, Pin 8 and 9 provide the digital inputs.
When the 2207 is used with a split-supply; the threshold
at these pins is approximately + 2 volts, which is a le\(el
that is compatible with both TTL and CMOS logic forms.
When used with a single-supply, the threshold is near
mid-supply and is CMOS compatible. Table 1 shows
how to select the timing resistors, R1 through R4, to de·
termine the output frequency based on the logic levels
applied to Pin 8 and 9. For optimum stability, the values
of R1 and R3 should be selected to fall between 10 kO
and 100 kll.
O.l"'F~
AL
UK
uf-...,...."li,i!l.---l--o MIN.
FSK
!ID--+--oO JU1Jl ourpUT
Iill---o -6V
rn--=--o DATA INPUT
Ui__.J!l---O ~=::~~~':~iiTOR
-6Vo-.J--+-_~""
With Pin 8 grounded, Pin 9 serves as the data input. A
high·level signal applied to Pin 8 will disable the oscilla·
tor. When used in this manner, Pin 8 of the XR-2207
serves as the channel select input. For two·channel
multiplex operation, Pin 4 and 5 should be connected
as shown by the dotted lines. (For single channel operation, Pin 4 and 5 should be left open-circuited.)
Figure 3. The XR-22D7 FSK Modulator Split-Supply Operation.
Table 1.
XR-22D7 FSK Input Control LogiC
logic Level
The XR-2207 provides two outputs: a square wave at
Pin 13 and a triangle wave at Pin 14. (For safe operation, current into Pin 13 should be limited to 20 mA.)
When used with a split-supply, the triangle wave peakto-peak amplitude is equal to V - and the dc level is
near ground. Direct coupling is usually used. With a
single-supply, the peak-to-peak amplitude is approximately equal to one-halfN + , the dc level is approximately at mid-supply, and ac coupling is usually necessary. In either case, the output impedance is typically
100 and is internally protected against short circuits.
Pin 8
Pin 9
Active
Timing
Resistor
L
L
Pin 6
-1-
Output
Frequency
Co Rl
L
H
Pins 6 and 7
_1_+_1_
Co R1
Co R2
H
L
Pin 5
-1Co R3
H
The square wave output has an npn open-collector configuration. When connected as shown in Figure 2 and 3,
this output voltage will swing between V+ and the voltage at Pin 12.
H
Pin 4 and 5
_1_+_1_
CoR3
Units: Resistors - Ohms; Capacitors Frequency - Hz
3-8
CoR4
Farads;
AN·01
The XR-2211 FSK DEMODULATOR
FEATURES
The XR-2211 has three npn open·collector outputs,
each of which is capable of sinking up to 5 mA. Pin 7 is
the FSK data output, Pin 5 is the Q lock-detect output
which goes low when a carrier is detected, and Pin 6 is
the Q lock-detect output which goes high when lock is
detected. If Pin 6 and 7 are wired together, the output
signal from these terminals will provide data when FSK
is applied, and will be LOW when no carrier is present.
Typically 20 ppm/DC Temperature Stability
Simultaneous FSK and Carrier-Detect Output
Outputs are TTL and CMOS Compatible
Wide Dynamic Range (2 mV to 3V rms)
Split or Single Supply Operation
Low-Power Supply Sensitivity (0.05 % IV)
Low External Parts Count
If the lock-detect feature is not required, Pins 3, 5 and 6
may be left open-circuited.
The XR-2211 is an FSK demodulator which operates on
the phase-locked loop principle. Its performance is virtually independent of input signal strength variations,
over the range of 2 mV to 3V rms.
Figure 4 shows the circuit connection for the XR-2211.
The center frequency is determined by fo = (lICI R4)
Hz, where capacitance is in farads and resistance is in
ohms. Calculation for fo should fall mid-way between
the mark and space frequencies.
The tracking range (± .1.f) is the range 01 frequencies
over which the phase-locked loop can retain lock with a
swept input signal. This range is determined by the formula: .1.f = (R4fO/R5) Hz . .1.1 should be made equal to,
or slightly less than, the difference between the mark
and space frequencies. For optimum stability, choose
an R4 between 10 kO and 100 kO.
Figure 4: The XR-2211 FSK Demodulator with Carrier
Detect
The capture range (±.1.fcl is the range of frequencies
over which the phase-locked loop can acquire lock. It is
always less than the tracking range. The capture range
is limited by C2, which, in conjunction with R5, forms
the loop filter time constant. In most modem applica·
tions, .1.fc = (80%-99%).1.1.
VPO
~LOtkRangB----J
I
I
:----." - > 1 - -'f
I
2VREF
r--'i ~
I
m
j
The loop-damping factor
determines the amount of
overshoot, undershoot, or ringing present in the phase·
locked loop's response to step change in frequency. it
is determined by l" = 114 Cl/C2. For most modem ap·
plications, choose l" "" 1/2.
4
:
-T---il----
:
I
I
I
:
VnEF
r--r-------
I
I
%VREF- -
-
+- !
fS
I
1- I
fa
-------------------
The FSK output filter time constant (TF) removes chatter from the FSK output. The formula is: TF = RFCF
Normally calculate TF to be approximately equal to [0.3/
(baud rate)] seconds.
XR-2211 TRACKING CHARACTERISTICS
The lock-detect filter capacitor (CD) removes chatter
from the lock-detect output. With RD = 510 kO, the
minimum value of CD can be determined by: CD(J.lI) ""
16/capture range in Hz.
As seen above, the XR·2211 produces at its phase de·
tector output a voltage VPD, which has a peak to peak
value equal to about VREF for a frequency swing from
fM (mark) to FS (space). The DC level VpD will be about
VREF (V2't -.65).
Note: Excessive values 01 CD will unnecessarily slow
the lock·detect response time.
3-9
AN-01
CIRCUIT DESIGN
DESIGN EXAMPLES
I. Design a modem to handle a 10 kilobaud data rate, using
Table 2 shows recommended component values for the
three most commonly used FSK bands. In many instances, system constraints dictate the use of some
non-standard FSK bands. The XR-2206/XR-2207/XR2211 combination Is suitable for any range of frequencies from several Hertz to 100 kiloHertz.
the minimum necessary bandwidth.
A. Frequency Calculation
Because we want to use the minimum possible
bandwidth (lowest possible upper frequency) we
will use a 55:100 frequency ratio. The frequency
difference, or 45%·.of the upper frequency, will
be 83% of 10,000. We therefore chose an upper
frequency:
Here are several guidelines to use when calculating
non-standard frequencies:
• For maximum baud rate, choose the highest upper
frequency that is consistent with the system bandwidth.
83 x 10,000 = 18.444 kHz =18.5 kHz.
45
• The lower frequency must be at least 55% of the upper frequency (less than a 2:1 ratio).
and the lower frequency:
0.55 x 18.5 kHz
• For minimum demodulated output pulse-width jitter,
select an FSK band whose mark and space frequencies are both high, compared to the baud rate. (i.e.,
for a 300 baud channel, mark and space frequencies
of 2025 Hz and 2225 Hz would result in significantly
less pulse-width jitter than 300 Hz and 550 Hz).
B. Component Selection
1. For the XR-2207 FSK modulator, set R1 = 30
kO. Now, select a value of Co to generate
10.175 kHz with Rr
10.175 kHz = 1/(CO x 30,000): Co = 3300pF.
• For any given pair of mark and space frequencies,
there is a limit to the baud rate that can be achieved.
When maximum spacing between the mark and
space frequencies Is used (where the ratio is close to
2:1) the relationship
mark-space frequency difference (Hz)
.
maximum data rate (baud)
= 10.175 kHz.
To choose R2:
18.500 khz - 10.175 kHz = 8.325 kHz =
1/Co R2: R2 = 36 kO.
A good choice would be to use 10 kO potentiometers for R1A and R2A, and to set R18 = 24 kO
and R2B = 30 kO.
~83%
should be observed.
2. For the XR-2206, we can make R7 equal to
R1, and C3 equal to Co above. To determine
R6:
For narrower spacing, the minimum ratio should be
about 67%.
18.5 kHz = lIR6C3: R6 = 16 kO
The values shown in Table 2 may be scaled proportionately for mark and space frequencies, maximum baud
rate, and (inversely) capaCitor value. It is best to retain
(approximately) the resistor values shown.
Use at 10 kO potentiometer for R6A and set
R6B = 13 kO.
Table 2.
Recommended Component Values for Typical FSK Bands
FSK Band
Baud
Rate
fL
XR-2207
fH
XR-2211
XR-220S
R1A R1B R2A R2B
R3A R3B R4A R4B
Co
RSA RSB R7A R7B
C3
R4A R4B
R5
C1
C2
CF
CD
300 1070 1270 10
20
100 100 .039
10
18
10
20
.039
10
18
100 .039 .01
.005
.05
10
18
150 160 .022
10
16
10
18
.022
10
18
200 .022 .0047 .005
.05
1200 1200 2200 20
30
20
10
16
20
30
.022
10
18
300 2025 2225
Units: Frequency -
Hz: Resistors -
36 .022
kO: Capacitors -
I'F
3-10
30 .027 .0033 .0022 .01
AN·01
III. Design a 2 channel multiplex FSK modulator to operate at
the following pairs of mark and space frequencies: 600 Hz
and 900 Hz, and 1400 and 1700 Hz (each of these channels could handle about 400 baud).
3. For the XR-2211 demodulator, we need to
first determine R4 and C1. First, fa = (fL +
fH)/2 = (10.175 + 18.500)/2 = 14.338 kHz.
If we make R4 = 25 kO, then 1/(C1 x 25,000)
= 14,338; C1 = 2790 pF =2700 pF. With
that value of C1, the precise value of R4 is
now 25.8 kO. Select R4B = 18 kO and use a
10 kO for R4A.
For this task, we will use the XR-2207. The only real
consideration here is that, if possible, we want to
keep the following resistances all between 10 kO
and 100 kO: R1, R1/R2, R3 and R3/R4. The ratio between the maximum and minimum frequencies is
less than 3: 1, so we should have no trouble meeting
this criterion. If we set our maximum frequency with
an R of about 20 kO, we have: 1700 = 11
(Co x 20,000); Co = 0.029 Itf which is approximately equal to 0.033 Itf.
C. Frequency Component Selection
1. To calculate R5, we first need our Af, which is
18,500 - 10.175, or 8.325 kHz:
8325 = (25,800 x 14,338)/R5
R5 = 44.4 kO =47 kO.
2. To determine C2 use l' = 1/2 = 114
Then, C2 = 1/4C1; C2 = 670 pF:
Calculating R1 using 600 Hz and 0.033 Itf, we get
R1 = 50,5 kO. We can use R1 B = 47 kO and R1A =
10 kO. For R2, we get 101 kO. Use R2B = 91 kO and
R2A = 20 kO. To determine R3, use: 1400 Hz = 11
R3Co, which gives us R3 = 21.6 kO. Use R3B = 18
kO and R3A = 5 kO. R4 must generate a 300 Hz
shift in frequency, the same as R2. Therefore, set
R4 equal to R2.
C1/C2.
3. To select CF, we use TF = [O.3/(baud rate)]
seconds:
TF = 0.3/10,000 = 30 Itsec.
with
v+
v+
SINEWAVE
RF = 100 kO, CF = 300 pF
Vl Q-j.-----".--=~TI
O. Lock Range Selection
To select CO, let us start with the actual lock
range:
Af
=
R4fo/R5 Hz
AL
OUTPUT
4.7K
saUAREWAVE
Wl-...:=;:--_~FSK OUT
51K
S.1K
+
~OIJF
= 7870 Hz
If we assume a capture range of 80%:
DLL__j:!p:....:==-_..:::OA.::,TA.:,oIN,P:r-"
I,
10K
AfC = 6296 Hz
therefore, our total capture range of ±AfC is
12,592 Hz. Our minimum value for Co is (161
12,592) Itf or 0.0013 Itf.
FSK IN
E. Completed Circuit Example
See Figure 5.
b----l
S.1K
DATA OUT
II. Design a 3 kilobaud modem to operate with low output jitter. The bandwidth available is 13 kHz.
CARRIER DeTeCT
10K
For this modem, we can take the values from two
for the 300 baud modem operating at 1070 Hz and
1270 Hz, multiply our baud rate and mark and
space frequencies by ten, and divide all capacitor
values on the table by ten. Resistor values should
be left as they are.
Figure 5: Full Duplex FSK Modem Using XR-2206 and
XR-2211. (See Table 2 lor Component Values.)
3-11
AN·01
Adjustment Procedure
The only adjustments that are required with any of the
circuits in this application note are those for frequency
fine tuning. Although these adjustments are fairly simple and straightforward, there are a couple of recommendations that should be followed.
the lock range. There are several ways that fo can
be monitored:
The XR-2207: Always adjust the lower frequency first
2. Open R5 and monitor Pin 13 or 14 with a highimpedance probe; or
1. Short Pin 2 to Pin 10 and measure fo at Pin 3 .
with CD disconnect;
with R1 Bor R3B and a low level on Pin 9. Then with
a high level on Pin 9, adjust the high frequency using R2B or R4B. The second adjustment affects only the high-frequency, whereas the first adjustment
affects both the low- and the high-frequencies.
3. Remove the resistor between Pin 7 and 8, and
find the input frequency at which the FSK output changes state.
The XR-2206: The upper and lower frequency adjust-
Note: Do NDT adjust the center frequency of the XR-2211
by monitoring the timing capacitor frequency with everything connected and no input signal applied.
ments are independent, and the sequence is not
important.
The XR-2211: With the input open-circuited, the loop-
For further information regarding the use of the XR2207, XR-2206 and XR-2211 refer to the individual product data sheets.
phase detector output voltage is essentially undefined and VCO frequency may be anywhere within
3·12
AN·02
XR·C240 Monolithic PCM Repeater
INTRODUCTION
The XR-C240 is a monolithic repeater circuit for PulseCode Modulated (PCM) telephone systems_ It is designed to operate as a regenerative repeater at 1.544
Mega bits per second (Mbps) data rates on T-1 type
PCM lines. The device is packaged in hermetic 16-pin
DIP package and is designed to operate over a temperature range of -40°C to +85°C. It contains all the basic functional blocks of a regenerative repeater system
including Automatic Line Build-out (ALBO) and equalization, and is insensitive to reflections caused by cable
discontinuities. Compared to conventional repeater designs using discrete components, the XR-C240 monolithic repeater IC offers greatly improved reliability and
performance and provides significant savings in power
consumption and system cost.
SIGNAL FLOW -
II
\I
lie
~II
_
SIGNAL FLOW
Figure 1_ Block Diagram of a BI-directional Digital
Repeater System.
THE T-1 REPEATER SYSTEM:
The T-1 Repeater Line is designed to provide a transmission capability for 24 two-way voice frequency signals which are transmitted digitally using a Pulse-Code
Modulation (PCM) technique. The system operates at a
data rate of 1.544 Mbps, with bipolar data pulses. It can
operate on either pulp- or polyethylene-insulated paired
cable that is either pole mounted or buried. Operation is
possible with a variety of wire gauges, provided that the
total cable loss at 772 kHz is less than 36 dB. Thus, the
system can operate satisfactorily on nearly all paired
cables which are used for voice frequency trunk circuits.
The XR-C240 monolithic IC replaces about 90% of the
electronic components and circuitry within the "digital
repeater" sections of Figure 1. Thus, a bi-directional repeater system would require two XR-C240 ICs, one for
each direction of information flow.
Figure 2 shows the functional block diagram of one of
the digital repeater sections, along with the external
zener regulator. The basic system architecture shown
in the figure is the same as that utilized in the design of
the XR-C240 monolithic IC.
The transmission system is designed to operate with
both directions of transmission within the same cable
sheath. The system performance is limited primarily by
near-end crosstalk produced by other systems operating within the same cable sheath. In order to insure that
the probability of a bit error is less than 10 - 6, the maximum allowable repeater spacing, when used with 22gauge pulp cable, is approximately 6000 feet.
BIPOLAR
11
OUTPUT
The details of the T-1 type PCM systems are well covered in the literature listed in References 1 through 5.
Figure 1 shows the block diagram of a bi-directional
PCM repeater system consisting of two identical digital
regenerator or repeater sections, one for each direction
of transmission. These repeaters share a common
power supply. The dc power is simplexed over the
paired cable and is extracted at each repeater by
means of a series zener diode regulator.
Figure 2. Functional Block Diagram of a Digital PCM
Repeater Section.
3·13
AN·02
The supply currents IA and IB drawn from the two supply voltages applied to the chip are specified to be within the following limits:
In terms of the functional blocks shown in Figure 2, the
basic operation of the repeater can be briefly explained
as follows:
a. Current from B.2V supply voltage, IA:
The bipolar signal, after traversing through a dispersive,
noisy medium Is applied to a linear amplifier and automatic equalizer. It is the function of this circuit to pro·
vide the necessary amount of gain and phase equaliza·
tion and, in addition, to band limit the signal in order to
optimize the performance of the repeater for near-end
crosstalk produced by other systems operating within
the same cable sheath.
1.1mA s IA s 2.5mA
b. Current from 4.3V supply voltage, IB:
6mA siB s 11mA
The external components necessary for proper operation of the circuit are shown in Figure 5, in terms of the
The output signals of the preamplifier which are bal·
anced and of opposite phases are applied to the clock
extraction circuit and also to the pulse regenerator. The
signals applied to the clock extraction circuit are recti·
fied and then applied to a high-Q resonant circuit. This
resonant circuit extracts a 1.544 MHz frequency component from the applied signal. The extracted Signal is
first amplified and then used to control the time at
which the output signals of the preamplifier are sam·
pled and also to control the width of the regenerated
pulse.
It is the function of the pulse regenerator to perform the
sampling and threshold operations and to regenerate
the appropriate pulse. The regenerated pulse is in turn
applied to a discrete switch which is used to drive the
next section of the paired cable.
REFERENCES ON PCM REPEATERS:
1. Mayo, J. S., "A Bipolar Repeater for Pulse Code Signals," B.S.T.J., Vol. 41, January, 1962,pp. 25-97.
2. Aaron, M. R., "PCM Transmission in the Exchange
Plant," B.S.T.J., Vol. 41, January, 1962, pp. 99-143.
3. Davis, C. G., "An Experimental Pulse Code Modulation System for Short-Haul Trunks," B.S.T.J., Vol. 41,
January, 1962, pp. 1-25.
4. Fultz, K. E., and Penick, D. B., "The T-1 Carrier System," B.S.T.J., Vol. 44, September, 1965, pp. 14051452.
5. Tarbox, R. A, "A Regenerative Repeater Utilizing Hybrid IC Technology," Proceedings of International
Communications Conference, 1969, pp. 46-5 46·10.
Figure 3. Package Diagram of XR·C240 Monolithic
PC M Repeater.
v++
+
V22
3.9V
_18 7
+
8.2V
V21
OPERATION OF THE XR·C240
XR·C240
+
t
The XR-C240 combines all the functional blocks of a
PCM repeater system in a single monolithic IC chip.
The pin connections for each of the functional circuits
within the repeater chip are shown in Figure 3, for a
16·pin dual-in-line (DIP) package.
4.3V
~
The circuit is designed to operate with two positive sup·
ply voltages, V++ andV+ which are nominally set to
be B.2V and 4.3V, respectively. Figure 4 gives a typical
recommended power supply connection for the circuit.
15
300\!
13
Figure 4. Recommended supply Voltage Connection
for XR-C240 (Note: See Figure 6 for
Recommended bypass capacitors).
3·14
AN·02
15
°Set C, to obilin , ••onlnl
link
fr~u.ncy
01 t.s.c.4MHz
3.51K
311
O"1'F*
Figure 5. External Components Necessary for Circuit Operation.
At R3
1.1K
A,
A,
R4
R,
C7
L2
3.3J..t.H
A,
R7
'30
INPUT
Ca
'02pl
5.'
556
A,3K
C6
0.'
A, RS
5.S2K
OUTPUT
+
L,
R25
300
C'6
6.8
C17
0.'
4.3V
8.2V
POWER TO REPEATER
SECTION NO.2
Figure 6. A Typical Circuit Connection for XR·C240 in 1.544 MHz T·1 Repeater System.
3·15
AN·02
DESCRIPTION OF CIRCUIT OPERATION:
system block diagram. Note that all the blocks shown in
Figure 6 are a part of the monolithic IC; and the numbered circuit terminals correspond to the IC package
pins (see Figure 4).
This section gives a brief description of the internal circuitry contained within the XR-C240 monolithic IC.
Figure 6 shows a practical circuit connection for the
XR = C240 in an actual PCM repeater application for
1.544 Mbps T-1 Repeater application. For simplification
purposes, the lightening protection circuitry and the
second repeater section are not shown in the figure.
The circuit diagram of the preamplifier section is shown
in Figure 7. This section is designed as a two-stage differential amplifier with a broadband voltage gain of
52db. The differential outputs of the preamplifier (Pins 4
and 5) are internally connected to the peak-detector,
Y+ =4.3Y
PEAK
DETECTOR
INPUT
B
~--JVV~--~------~16
'1--+---......._>---(') Va = INTERNAL BIAS
Figure 9. Automatic Line Bulld-Dut (ALBO) Section.
Figure 7. Circuit Diagram of Preamplifier Section.
GND 6
PEAK
DETECTOR
, . . -_ _ _A....._ _- - . .
B
FULL WAVE
RECTIFIER
THRESHOLD
DETECTOR
r---------~,--------~
.--------~-------~
INPUT
FROM
PREAMP
,---...
A- A+
15
D
v+ = 4.3V
Figure 8. Circuit Diagram of Threshold-Detector, Full-Wave'Rectifier and Peak-Detector Sections.
3-16
AN·02
full-wave rectifier and the threshold detector sections
of the XR-C240 as shown in Figure 8.
of the second gain stage is "integrated" by the phaseshift capacitor, Cl, externally connected to Pins 11 and
12. (See timing diagrams of Figure 13.) The nominal value of this capacitor is in the 30 to 40pf range. The triangular waveform across Pins 11 and 12 is at quadrature
phase with the sinusoidal voltage swing across the L-C
tank circuit. This waveform is then used to generate the
"strobe" signal, Cp , and the clock pulse C, which is
applied to the data latches of the logic section.
The peak-detector output (terminal B of Figure 8) is internally connected to the Automatic Line Build-out
(ALBO) section of the circuit and controls the DC bias
current through the ALBO diodes 019 through 020, as
shown in Figure 9.
The full-wave rectifier output (output D of Figure 8) is internally connected to the clock-extractor section of the
repeater and provides the excitation signal for the L-C
tuned tank circuit (Pin 14) of the injection locked oscillator. The threshold-detector outputs (G+ and G- of
Figure 8) provide the differential logic drive to the data
latches of the logic section of XR-C240.
The strobe and clock pulses out of the clockregenerator section are applied to the output data
latches shown in Figure 11. The two parallel output R-S
flip-flops are driven by the differential inputs (G + and
G -) from the data comparator of flgure 8. T~ two
sets of differential data signals, Fl, Fl and F2, F2 are
then applied to the output driver amplifier shown in Figure 12. The high-current outputs of the driver stage
(Pins 8 and 9) are connected to the center-tapped output transformer as shown in Figure 5. The voltage
swing across the output is one diode drop (VBE) less
than the supply voltage spread, i.e.:
The clock-extractor section of XR-C240 is designed as
an injection locked oscillator as shown in the circuit
schematic of Figure 10. The excitation is applied to the
emitter of 023, through terminal D which is internally
connected to the output of the threshold comparator.
This signal in turn controls the current in the resonant
L-C tank circuit connected to Pin 14. The sinusoidal
waveform across the tank is then amplified and
squared through the cascaded differential gain stages
made up of 031,032 and 035, 036. The output swing
Peak Output Swing = (V++) - (V+) - (VBE)
= 3.2V
The output stage is designed to work into a nominal
load impedance of 100 ohms, and can handle peak
load currents of 30m A.
10
r-------::--:r<
Figure 10. Circuit Diagram of Clock Extractor Section.
3-17
v++ = B.2V
AN·02
,....,..---r---"""1---r---®10 y++. 1.:lV
"51
"51
G+
F'''''f-+~
F,""f-+~--"'"
Va
= ~~"NAL Hf------t-E--;;::+----K:
Figure 11. Data Output Latches (Logic Section).
Figure 12. Output Driver Section.
3·18
AN·02
ELECTRICAL CHARACTERISTICS
(Measured at 25°C with V + + = 8.2V, V + = 4.3 V, unless specified otherwise.)
LIMITS
PARAMETER
MIN.
MAX.
UNITS
Supply Voltage:
V+ +
V+
7.79
4.085
8.61
4.515
V
V
Supply Current:
IA
IB
Total Current
1.1
6
7.1
2.5
11
13.5
mA
mA
mA
15
54
4
2
mV
db
Preamplifier
Input Offset Voltage, VOS
Open Loop Differential Gain, AO
Input Bias Current, IB
Input Offset Current, lOS
Input Impedance, Rin
50
50
Clock Extractor Section
Tank Drive Impedance
Tank Drive Current
"Zero" Signal Current
"One" Signal Current
Recommended Tank Q
Phase Shifter Offset Voltage
See Figure 4
Supply = 8.2V
Supply = 4.3V
p.A
See Figure 8
Measured Differentially Across
Pins 4 and 5
±1.3
±0.9
±0.28
±1.6
± 1.15
±0.48
50
12
80
100
-18
V
V
V
kO
24
220
p.A
p.A
+18
mV
Output Drive Section
Output Voltage Swing
Low Output Voltage
Output Leakage Current
Output Pulse
Maximum Pulse Width Error
Rise and Fall Times
Measured at Pin 10
Measured at Pins 7 and 15
p.A
kO
Comparator Thresholds
Peak Detector (ALBO)
Threshold
Full·Wave Rectifier Threshold
Data Threshold
CONDITIONS
3.0
0.65
V
V
0.95
50
p.A
±30
80
ns
ns
See Figure 10
At Pin 14
Voltage applied to Pins 7 and 14
to reduce differential voltage
across Pins 11 and 12 to zero.
See Figure 12
Voltage levels referenced to Pin 7
RL = 1000
Referenced to Pin 7, IL = 30 mA
See Figure 13
Figure 13. Typical Timing Waveforms for a 1-0-1
Input Data Pattern
3-19
AN·03
Active Filter Design with Ie OP Amps
INTRODUCTION
This application note will assist the designer in selecting the optimum filter for his application. It begins with
a table of transfer functions, and. network defining
equations, for the high-pass, low-pass, bandpass, and
band-reject filters. A guide to the three types of filter responses will be presented, along with illustrations of
several filter realizations, with their respective merits
and limitations. Finally, the entire contents are brought
together, to provide the designer a complete working
schematic of an active filter in a modem configuration,
utilizing the XR-4202 Quad Programmable Operational
Amplifier, along with the XR-2206 Waveform generator,
and the XR-2211 Precision Tone Decoder.
Since the operational amplifier plays such a key role in
the active filter, its characteristics are of prime importance. By using operational amplifiers as the basic gain
stage of the active filter, problems previously encountered due to low-input impedance, high-output impedance and low-gain are virtually eliminated. Operational
amplifiers provide the required response for various filter types. Some of the more popular filters are multiple
feedback, state variable, bi-quad and Sallen Key, which
can be used to obtain high-p;3.ss, bandpass and lowpass filter functions_ They are capable of giving the designer all of the standard filter responses, i.e., Butterworth, Chebychev, and Bessel.
PRINCIPLES OF OPERATION
The XR-4202 Quad Programmable Operational Amplifier is a basic building block for active filters, and is
ideally suited for most filter applications. The XR-4202
provides the user the flexibility to externally program
the gain-bandwidth product, the supply current, the input bias current, the input offset current, the input
noise, and the slew rate. The user, therefore, can tradeoff bandwidth for supply current or optimize the noise
figure. Likewise, other amplifier characteristics can be
programmed for a specific need.
There are many single, dual, and quad operational amplifiers that can be used to implement the filters discussed. Table 1 lists some standard operational amplifiers and compares their important characteristics.
Table 2 gives the designer a brief review of the basic
transfer functions and network defining equations. Note
that a family of curves exists for all filters except first order low-pass and high-pass. This is due to the presence
of loop damping. This point will be expanded upon in
the next section on filter responses.
Table 1_
DEVICE CHARACTERISTICS
XR·4202
XR·3403
XR·4136
XR·4558
741
UNITS
Slew Rate
1.5
.6
1.6
1
.5
VII'S
Gain-Bandwidth Product
3.5
1
3
3
1
MHz
Input Offset Current
10
30
10
5
20
nA
Input Bias Current
80
200
80
40
80
nA
Supply Current (max)
6.0
7.0
4.0
5_7
2.8
mA
Note: All values typical unless otherwise specified.
3-20
AN·03
Table 2.
Transfer Funcllons and EquatIons
High Pass
Band Pass
H(s) = s + wo
H(S)=~
5 + wo
Ho a wos
H(s) = s2 + (twoS + wo2
.
[Ho2wo J '12
IHOw)] =
w 2 + w0 2
IHOw)1
SensHivity
Defining Equation
Ct
= C4
=
SC1 HO = -SC4HO = 1
~R2
(Cl
~C3
~C4)
RS -f C3C4 +
C4 +
C3
Note: The sensitivity of HO
with this implies that if Cl
changes by
1% HOwili al·
so change by
1%. The de·
fining equation for a sensitivity paramo
eter is:
1
1
(C1
SC<>=-----+1 )
3
2
<>wORSC3 C3
1
1
(Cl
SC<>=-----+1 )
4
2
<>wORS = - - - l
<>waRs C3C4
SR2<> = -SRS<> =
wo
=
(
r
1
R2RSC3C4
'12
Sx Y = xdY
Ydx
SR2wa = SRSwa = SC3wa = SC4wa = -
3-23
-1
2
AN·03
Table 5.
Output
Parameters
HO
SensHlvHy
Delinlng Equation
1 + R3/R4
1 +' R1/R2
SR1 HO = -SR2 HO = -1/(1 + R2/R1)
/R
SR3 HO = -SR H0 = 1- ( R3 4 )
HO 1 + R1/R2
4
Low
Pass
Eq. 3
t
"'0
(
R
R3 RSR: C1C2
'"
1 + R4/R3 (R3RSC2) y,
1 + R2/R1 R4RSC1
SR 3"'O = SRS"'O = SRS"'O = SC1"'0 =
Sc2"'0
= -SC4"'0 = - y,
R4 /R 3
SR",=-SR",=-1/2+
4
3
RSC1 "''''0(1 + R2/R1)
SR '" = -SR '" =
1
1
3
1 + R1R2
SRS'" = SC2'" = -SRS'"
HO
1 + R4/R3
1 + R1/R2
=
-SC1'" = y,
SR1HO = -SR2HO = -1/(1 + R2/R1
SR HO = - SR HO = - 1(R4R3 )
3
4
HO 1 + R1/R2
High
Pass
Eq. 4
SAME AS LOW PASS
"'0
'"
C+
R4/R3)C3R6C2) y,
1 + R2/R1 R4RSC1
SR4'" = -SR '"
3
=
-112
+
R4 R3
RSC1 "''''0(1 + R2/R1)
1
SR1'" = -SR '" =
2
1 + R1R2
SR6'" = SC2'" = - SRS'" = -SC1'" = y,
HO
R2
° = 11",
=
-SR2HO
=
-1
SAME AS LOW PASS
"'0
Band
Pass
Eq. S
SR1 HO
R1
C
+ R2/R1)(R4 RSC1) y,
1 + R4/R3 R3R6C2
SRSQ = SC1 Q = -SR60 = -SC2 0 = ,1/2
R4 /R 3
SR Q =SRO=1I24
3
RSC1 "''''0(1 + R2/R1)
SR Q = -SR Q =
1
2
1
1 + R1/R2
3·24
AN·03
Figure 5 shows a typical state-variable configuration
whose characteristic equations are given by Eq. 3,
Eq. 4, and Eq. 5. These equations all have the same denominator, and the numerator is determined by the
point at which the output is taken. This form may also
be used to simulate a band·reject function by summing
the high-pass and low·pass outputs. The defining equations and sensitivity parameters are given in Table 5. It is
noted here that the bi·quad is actually a slight variation
of a second order state-variable.
FSK MODULATOR
XR-2206
6 ••
UNE
TERM.
FSK DEMODULATOR
XR-2211
Figure 6. FSK System.
In this system, the digital data to be transmitted is used
to key the XR-2206. The frequency-shift keyed output of
the XR-2206 is then sent through the hybrid and out onto the line. (The hybrid is used to obtain isolation between data transmitted and data received, and may also be used to amplify the received signaL) In full duplex
operation, this system must be able to receive and
transmit, simultaneously. Due to line losses, the received Signal may range from -12 dBm to - 48 dBm.
The output level of the transmitter is typically - 6 dBm
(allowing for a 6 dB loss in the hybrid). Due to line mismatch, the hybrid may only provide 10 dB of isolation to
the filter. Therefore, the levels at the input of the filter,
assuming a gain of 6 dB from the line through the hybrid, is -6 and -42 dBm for the desired Signal, and
- 16 dBm from the local oscillator. This means that in a
worst case situation, the input level of the received signal is - 42 dBm, with the level of the local oscillator
26 dB above this. For the XR-2211 to operate with a
low-bit error rate, the input should be 6 dB higher than
the interfering Signal. This implies that the stopband,
Amin, from Figure 2 is 32 dB. The XR-2211 has an internal preamplifier with a dynamic range of greater than
60 dB, and requires a minimum input level of - 38 dBm
to cause limiting. If we choose a filter to have a passband ripple of 1 dB, and an overall gain of 5 dB, the input conditions of the XR-2211 will be satisfied. The filters introduce a phase shift that is only linear for approximately 1/2 and 1/3 of the passband; therefore, a
bandwidth of 400 Hz is used for the filter. The general
shape of the filter is shown in Figure 7.
EOp
c,
c,
Figure 5. Typical State-Variable Configuration.
Eq.3
Eq.4
Eq.5
20 log
HII"
",
Amall'
I dB
Modem Filter
A typical application for an active filter is the input
stage of a frequency demodulator. Any noise or spuri·
ous signals at this point would affect the overall quality
of the output. A more specific example can be cited by
considering the FSK system shown in Figure 6.
(Frequency-shift keying is a means oj transmitting digital information, primarily through telecommunications
links.) This type of system is thoroughly covered in Exar's Application Note, AN-01, and will only be briefly discussed here.
1270
2325
2980
Figure 7. General Filter Shape.
Note: The values used in this filter are based on a mo·
dem using an XR-2206 as the modulator, and
XR-2211 as the demodulator. If digital techniques
are used, the filter parameters may be different,
due to the harmonics generated by digital synthesis of a sine wave, and higher signal-to-noise
requirements of the demodulator.
3·25
AN·03
To find the minimum number of poles required for this
response, the nomograph in Figure 1 is used. The point
falls between a 2· and 3·pole filter. The values of Wo + a
are determined from the tables, for a 3rd order Cheby·
chev response with 1 dB ripple.
Where
From the tables:
WD = .997D98
W1
wD
f1
fD
M =.- = - = - = wD
w2
fD
f2
M = 1.D955
f1 = 2317.6
f2 = 1931.1
for Section 3 the real pole Is transformed into a com·
plex pole pair.
complex pole
= .4956D9
WD = .494171
a
( aW 101)2 _ 1
20D
Eq.7
-real pole.
20D
03 = = 10.7
aWB
The geometric center is wD = ";W3W2 or ";f3f2 - fD
and f3 = fa.
The filter
OD = _fD_ = -/(1925)(2325)
f3 - f2
2325 - 1925
= 5.28892
The 3 filter stages are now defined:
f1 = 2317.6
f2 = 1931.1
f3 = 2115.56
The 0 of each section of the filter is determined by,
Equation 6.
01 = 21.49
02 = 21.49
03 = 10.7
In this example, the multiple feedback approach is used
since 3·pole pairs can be generated with 3 op amps, 6·
capacitors, and 9 resistors; an equivalent filter could
have been designed with the state,variable, but this
would have required 9 op amps to realize. The actual
filter is shown in Figure 8. All capacitor values are cho·
sen to be .01 /LF (5%), and all resistors are 1 %. The
values for this filter and a low·band filter are shown in
Table 6.
Eq.6
2 "'1"'1 2
00
01 = 21.49 = 02. Section two is a reflection of section
one, about fa. The center frequencies are found by
Eq.7.
Figure 9 shows a complete Originate or Answer mo·
demo The values for the XR·2206 and XR·2211 are given
",.
"2.
Figure 8. Modem Filter.
Table 6.
10
Wo
00
R1
R2
R2
C1
C2
Ho
Originate
A
B
C
1931.1
2317.6
2115.6
12.1335K
14.562K
13.293K
21.49
21.49
10.7
88.6K
74K
40K
192
160
355
354K
295K
161K
.01
.01
.01
.01
.01
.01
2
2
2
Answer
A
B
C
1362.26
975.51
1152.78
10.115K
6129.3
7.243K
11.827
11.827
5.832
58.5K
96.5K
40.3K
421
421
1219.5
234K
386K
161K
.01
.01
.01
.01
.01
.01
2
2
2
3·26
AN·03
in Table 7. For an originate modem, the transmitting
frequencies are 1070 and 1270, and the receiving
frequencies are 2025 and 2225, for a space and mark,
respectively.
c,.
The first op-amp is connected as an active hybrid which
should supply a minimum of 10 dB isolation, from transmit to receive, while adding 6 dB from the line to the
receiver.
c,.
Figure 9. Originate or Answer Modem.
Table 7. Recommended Component Values for Typical FSK Bands
Componant Values
FSK Band
Baud
Rate
XR·22D6
XR·2211
'L
'H
R6A
R6B
R7A
R7B
C3
RX
RC
RA
Co
Originate
1070
1270
10
18
10
20
.039
10
18
100
.039
Answer
2025
2225
10
16
10
18
.022
10
18
200
.022
Units: Frequency -
Hz; Resistors -
kO; Capacitors -
I'F.
3-27
CA
CF
Co
.01
.005
.05
.0047
.005
.05
AN·04
XR·C277 Low·Voltage PCM Repeater IC
INTRODUCTION
The XR-C277 is a monolithic repeater circuit for PulseCode Modulated (PCM) telephone systems. It is designed to operate as a regenerative repeater at 1.544
Mega bits per second (Mbps) data rates on T-1 type
PCM lines. It is packaged in a hermetic 16-pin CERDIP
package and is designed to operate over a temperature
range of - 40°C to + 85°C. It contains all the basic
functional blocks of a regenerative repeater system including Automatic Line Build-Out (ALBO) and equalization, and is insensitive to reflections caused by cable
discontinuities.
tern would require two XR-C277 IC's, one for each direction of information flow.
Figure 2 shows the functional block diagram of one of
the digital repeater sections, along with the external
zener regulator. The basic system architecture shown
in the figure is the same as that utilized in the design of
the XR-C277 monolithic IC.
In terms of the functional blocks shown in Figure 2, the
basic operation of the repeater can be briefly explained
as follows:
The key feature of the XR-C277 is its ability to operate
with low supply voltages (6.3 volts and 4.4 volts) with a
supply current of less than 13 mAo Compared to conventional repeater designs using discrete components,
the XR-C277 monolithic repeater IC offers greatly improved reliability and performance and provides significant savings in power consumption and system cost.
The bipolar signal, after traversing through a dispersive,
noisy medium, is applied to a linear amplifier and automatic equalizer. It is the function of this circuit to provide the necessary amount of gain and phase equalization and, in addition, to band limit the signal in order to
optimize the performance of the repeater for near-end
crosstalk produced by other systems operating within
the same cable sheath.
FUNDAMENTALS OF PCM REPEATERS
The output signals of the preamplifier which are balanced and of opposite phases are applied to the clock
extraction circuit and also to the pulse regenerator. The
signals applied to the clock extraction circuit are recti·
fied and then applied to a high-Q resonant circuit. This
resonant circuit extracts a 1.544 MHz frequency component from the applied Signal. The extracted signal is
first amplified and then used to control the time at
which the output signals of the preamplifier are sampled and also to control the width of the regenerated
pulse.
Figure 1 shows the block diagram of a tii-directional
PCM repeater system consisting of two identical digital
regenerator or repeater sections, one for each direction
of transmission. These repeaters share a common
power supply. The DC power is simplexed over the
paired cable and is extracted at each repeater by
means of a series zener diode regulator. The XR-C277
monolithic IC replaces about 90% of the electronic
components and circuitry within the digital repeater
sections of Figure 1. Thus, a bi-directional repeater sysSIGNAL F L O W _
BIPOLAR
OUTPUT
I
T,
~II
+6.3V 4 XR..084
P, = >FULL SCALE ADJUST
P2= >ZERO ADJUST
Figure 4. Wide Range Tracking PLl.
3·89
--.
AN·18
put voltage range is 10 mV RMS to 3 V RMS with the
output providing a T2L compatible square wave.
Figure 6 shows the complete wide range synthesizer
circuit. The two 4-bit binary counters, 74161, and magnitude comparator, 8130, form the programmable divider. The output of the divider is a variable duty cycle
pulse so that the flip-flop, 7474, was added so that
phase detector was always presented with a square
wave. Since the flip-flop also divides by two, the minimum value for the divider will be 2 or the actual N of the
overall divider will be the binary input times two, 2N.
The DAC uses the reference voltage of the XR-2212 as
its reference with amplifier A4 used to scale the voltage
to RO correctly. C1 provides loop compensation and its
value will determine not only the response of the circuit
but the short term frequency stability of fO. A trade off
must be made here as decreasing C1 will provide for a
faster responding loop but decrease the short term stability of fO. It is probably most desirable to have a highly
stable output frequency and slower responding loop,
which the values in Figure 6 provide for.
loo--t--=====t--II
FROM VAEF
OF XR·2212
With the values shown, fo will be one kHz to 100 kHz
with fref = 500 Hz and N = 1 to 100. The reference in-
Figure 5. Wide Range Synthesizer Block Diagram.
lOOK
24K
+12...
o - - - - - - - - - - - - - -.....- - - t - - - H
'REF
0 - - - - - - - - - - - - - - - - - 1 I--f----R
10K
loo-----t--~---~~--------.
'5'~-rt==~~~l:n
DIGITAL GND~
ANALOG GND
D---:::L.
A, - A4 = > XR-084
P, = > FULL SCALE ADJUST
P2 = > ZERO A~JUST
I. = 2Nlrol ,,;;N,;;'oo
lrol = 500HZ
10K
LSB
51K
MSB
-12'0-------....-1"
8 3 84 8 s 8 6 8 7 8 8
~
V LC
i
a
VREF- VREF+ 10
+12v
20K
20K
Figure 6. Wide Range Synthesizer.
3-90
AN·18
Calibration is done by first adjusting Pl for a 100 kHz
output with N = 100 and then adjusting P2 for a one
kHz output with N = 1.
Typical input and output waveforms for rref = 500 Hz,
top trace, and fo, bottom trace, with N switching from
40 to 8 are shown in Figure 7.
Figure 7. Typical Input and Output Waveform.
3-91
AN·19
Clock Recovery System
INTRODUCTION
Recovering encoded serial data from floppy disk systems poses a major design problem as the synchronized clock used to encode data is embedded within
the data stream. The clock cannot be readily extracted
using common phase-locked loop techniques as the actual clock may appear for only short periods of time in a
common encoding format such as NRZI. This clock is
necessary to decode the serial data and retrieve the
original data.
Figure 2 shows the block diagram of the clock recovery
system. The XR-320 forms a bi-directional one-shot. It
will produce a positive output pulse for both rising and
falling edges on its input. The period of these output
pulses is set equal to one half the total period of clock.
This is used to provide a frequency component in the
data stream equal to the clock even under worst case
data conditions of five ones, zero, five ones, zero. (Seen
in Figure 1.) This can also be seen to double the frequency of the data stream which is desirable as the
PLL will now be able to lock to the original clock. The
XR-2212 forms the PLL which, when the actual clock
appears in the data stream, locks to and produces a
frequency at its veo output equal to and synchronized
with the clock. The PLI':s phase detector output is connected to the input of a sample and hold (S/H) as well
as the S/H's output through a switch. This switch is held
open by the 74123 as long as the clock appears in the
data stream. Whenever a one is present the clock will
not appear in the data stream and the 74123 places the
sample and hold in the hold mode and closes the
switch. This holds the voltage at the phase detector and
keeps the proper driving voltage to the veo, thus maintaining the frequency at the output of the veo equal to
and synchronized with the clock.
This application note describes the design of a PLL
(phase-locked loop) system which can be used to recover the clock from a serial data stream using NRZI
proto·col with very excellent stability. The design utilizes
the XR-2212 Precision Phase-Locked Loop in conjunction with the XR-320 Monolithic Timer to form the heart
of the system. The system also uses a 74123 Dual OneShot and 398/13333 for timing and sample and hold
purposes.
PRINCIPLES OF OPERATION
Figure 1 shows a data stream and clock using a typical
NRZI protocol. In this protocol changes in levels represents a binary zero, while no transitions a binary one.
From the figure it can be seen that the data stream can
have a maximum rate of change corresponding to a frequency equal to one half the clock frequency with the
actual data being a string of zeros. This format guarantees that there will be no more than five ones in a row.
The slowest rate of change will then be a frequency
corresponding to one twelfth the clock.
ACTUAL DATA
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
0
0
DUAL ONE-SHOT
1
NAZI
ENCODED
DATA STREAM
CLOCK
"
Figure 2. Clock Regenerator Block Diagram.
T,
I h
T2
H
1.2T
When the clock reappears in the data stream the 74121
drives the switch open and S/H to the sample mode
with the PLL once again tracking the clock in the data
stream. The length of T1 is made equal to slightly less
than the period of the clock so that the S/H is always
ready in the event the clock is not in the data stream
and any sample to hold glitches will not be transmitted
to the phase detector's output. The length of T2 is made
slightly longer than the clock period which will cause
the switch to close immediately after one clock pulse is
missed. With a clock period T, these times, T1 and T2,
are set equal to 0.8 T and 1.2 T, respectively.
nL-__.....J..--L
I
RETRIGGERED BEFORE
IT TIMED OUT
~'::!""::~~""~"";·N~C-Y-'-~-P-H-AS...J.*V;:\'-;E-C-TO-"--.J\~
,.
COMPONENT
HELD BY SIH
REGENORATED
CLOCK
Figure 1. System Timing Diagram.
3-92
AN·19
PHASE SHIFT
CIRCUIT DESIGN
v,
BETWEEN
'0 AND '1
The heart of the circuit is the XR-2212 Precision PhaseLocked Loop. Figure 3 shows the XR-2212's internal
blocks and necessary external components. The phase
detector output is a high impedance current source output so it can be forced or held at a particular voltage
easily, as by the S/H. The PLL:s center frequency is
equal to:
1
fo=-RoCO
Figure 4. PLL In/Out Phase Relationships.
The XR-320 Monolithic Timer used for the bi-directional
one-shot is shown in block form with its external components in Figure 5. The control flip-flop can be triggered by either positive or negative edges on its inputs,
which are tied together for this application to provide bidirectional triggering. Once triggered, the output will
provide a low level signal for a period defined by:
RO and Co are calculated using the data stream's clock
frequency set equal to fo . The tracking range of PLL is
given by the following relationship:
R1
af = fo R1
af => tracking range
TLOW = 2 RTCT
These components are calculated with TLOW set equal
to one half the clock period.
c.
Figure 3. XR-2212 Internal Blocks with External
Components.
The phase relationship between the incoming Signal, fi'
and the output signal, fo, will be 90· if fi is equal to fo
and will vary up 90· or down 90· from this nominal if fi
is at either end of the tracking range. The voltage at the
output of the phase detector will also vary linearly with
these phase relationships. These relationships are
shown in Figure 4. The tracking range is made very
large since a constant phase relationship between the
recovered clock is desirable. Therefore, any errors in
the S/H or drops through the switch will not significantly
alter this phase relationship. at is made equal to approximately 0.8 fo, and R1 is calculated accordingly. C1
is used to remove the double frequency component
from the phase detectors output and also in conjunctionwith Co controls the PLL transient response characteristics, according to. the following relationship:
~ =
Figure 5. XR-320 Internal Blocks with External Components_
Table 1 summarizes the previously described formulas
as well as those for the 74121 Dual One-Shot.
Table 1
FOR XR-2212
FOR 74123
(1) ReCe = _1_
'ClK
v....rco
(2) R1 = 1.2 Re
C1
for a loop damping of Y2, C1 =
FOR XR-320
0.8 'elK In 2
(6) REX2CEX2 =
Co
4"
1.2 'ClK In 2
3-93
AN·19
+5VO--------------------~~~----------~~----------~~~~----~_____,
IN914
I
0----------------1.,.....,,00
10K~
-,l-.
1:
F'"
1pr
DATA STREAM
PLUS CLOCK
_ _-...
ltR·J20
V+
5 \..
74123
J
~
Rex,
15K
I'
Vee
7
T
-t:
.r
6
~~
t..:
'OOpF
IN914
II
16
RT
'8K
~ICEXI
LOG~~'_'+--"'_O
______.....__+-_'"'_t'O TR
r3
1
OUT
~~
CT~
10K
~ L..
GND
__
CT
'OOpF
~
GND
f,
8
Q, ~'000PF
rr
GNDo------------------~~~------------~----1_------~~-+--~~----------~~------__,
rll--·
C.I,oF
+12VO----------__~_+--------------------~------------------~--~----------~-,
XR·2212
1
,
~ h4T
,.
e,
~O~ l~
'0
'~~J J
~~
r-~:.::.....--......--.. . . .r_'V\i'V--~_1 Y,N
DET
510pF
V.
o----------------~r_'''t_---l
REGENERA TED
CLOCK
'6K
5
i$
13
Y. ~J
R,
7
v
5
VA-.-!!--
15
Q,01 .. F
LOGIC
y-
5
14
5K
RO
:,p.
-12yo-----------_----------------------------------------~--------------~
P,
= ~.
ADJUST SO POSITIVE PORTION OF Ii IS eQUAL TO
'J
OF THE CLOCK PERIOD
P2 = ;., ADJUST FOR 90 PHASE SHIFT BETWEEN f1 and fo WITH h
='eLK
Figure 6. Complete Clock Regenerator.
Figure 6 shows the complete clock recovery circuit
with values designed for a clock of 122 kHZ. The input
to the system will accept input low levels from 0 V to
0.5 V levels and high levels from 1.5 V to 5 V. The output
provides a 10 V P-P square-wave. Calibration is accomplished by adjusting P1 for the output of the XR-320 to
equal exactly one half of the clock period and P2 for a
90· phase shift between fi and fo with a constant string
of zeros applied at fi.
The oscilloscope photograph in Figure 7 shows the system waveforms with the input data stream on top and fo
on the bottom.
The same circuit can be used to regenerate or clean up
a clock with occasional missing cycles by applying it to
the point labeled fi and eliminating the XR-320 from the
circuit.
Figure 7. System Waveforms.
3-94
LF 13333
V+
MYLAR
8.2K
12
GNY.(:H
0 10.~~A--t--'--<
- y ...
12
V/,
V.
"
Co 820pF
16 - - - ;
LF398
THRESH
4
AN·20
BuUding a Complete FSK Modem Using
XR,,2211 arrnd XR.. 2206
INTRODUCTION
GENERAL DESCRIPTION
phone line, while it will decode to "I 's" and "O's" 2025
Hz and 2225 Hz received from the line. The originate
modem simply reverses the frequencies for send and
receive. The sinewave modulator will produce two discrete frequencies at its output corresponding to a "1"
or a "0" at its data input. The line hybrid will steer these
frequencies to the phone line while causing received
frequencies to go to the bandpass filter and demodulator. This block will therefore provide isolation between
modulator and demodulator at each end. The bandpass
filter is used to remove unwanted signals and noise received from the phone line before they reach the
demodulator.
Figure 1 shows the block diagram of an FSK system.
The complete system is comprised of an answer and
originate modem. The answer modem will convert input
data to either 1070 Hz or 1270 Hz and send it to the
The PLL demodulator will lock onto incoming frequencies at its input and produce" 1's" or "O's" at its output.
The carrier detect output will produce a low, "0" signal
out when valid data is being received.
With the number of digital systems and equipment
growing so rapidly, the need for a method of moving data has also become a fast growing field. This application note describes the construction of a modem system using frequency shift keying, FSK, for serial data
transmission. The system utilizes the XR-2206 as a
modulator, the XR-2211 as a demodulator, and an
XR-084 op amp as a bandpass filter. These three IC's
make up a complete working 300 baud, full duplex, FSK
modem.
ANSWER MODEM
OAIGINA TE MODEM
PHONE LINE
1070,1270 Hz
Figure 1_ Block Diagram of FSK Modem System.
OPERATION AND CALIBRATION
number of bits per second which can be sent and received. The answer can be used to drive the originate
and vice-versa. R19 is then adjusted for a square-wave
on the data received output.
The circuit has been designed for + 12 volt operation.
The data inputs accept TIL compatible signal levels,
while the outputs provide OV to + 12V signal levels.
Calibration is done by first adjusting the modulator. With
a low signal on its input, R21 is adjusted for 1270 Hz or
2225 Hz for originate and answer respectively. Then
with a high signal in, R22 is adjusted for 1070 Hz or
2025.
R20 is used to set the modulator output level. With the
modulator output set at - 6 dBm, the system will operate with an input signal range of + 10 dBm to - 48
dBm.
CIRCUIT CONSTRUCTION
The demodulator is easiest adjusted by feeding into the
modem input an alternating 1070 Hz/1270 Hz or 2025
Hz/2225 Hz signal in a square-wave fashion. The modulating frequency should be 150 Hz, which is one-half
the system baud rate of 300. The baud rate refers to the
Figures 2 and 3 show the circuit schematic and component layout. One PC board is used for answer or originate and should use the appropriate components as
listed in Table 1.
3-95
AN·20
~--~--'-----'-~~~----------------------------~r'-oV'
"12
""
CARRIER
DETECT
DATA
e'2
le2
"'
"2.
"2.
R27
C17
~~~~--------~~
le3
"25
PHO~[
LI~
"2'
"24
Figure 2. Complete FSK Modem Using XR-2211 and XR-2206.
2'
POTENTIOMETER
5.'
POTENTIOMETER
2.
POTENTIOMETER
2.
POTENTIOMETER
PHONE
LINE
Figure 3. XR Modem Foil Side Shown (Not to Scale).
3·96
RECEIVED
AN·20
Table 1. Modem Parts list
XR-084
XR-2211
XR-2206
IC1A-D
IC2
IC3
R1*
R2*
R3*
R4*
R5*
R6*
R7*
RS*
R9*
R10
Rn
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
C1,C6*
C7
Cs
C9
C10
Cn
C12
C13
C14
C15
C16
C17
ANSWER
ORIGINATE
40.2K
499
270K
60AK
680
3S3K
24.9K
1.21K
160K
1K
1K
5.1K
5.1K
510K
510K
100K
47K
7.5K
2K
50K
2K
2K
3.9K
3.6K
200
1M
1M
0.01
0.1
22
0.01
0.1
0.022
0.1
1
0.1
0.1
1
1
47.5K
191
357K
39AK
160
270K
20K
360
160K
1K
1K
5.1K
5.1K
510K
510K
100K
100K
9.1K
2K
50K
2K
2K
8.2K
6.8K
200
1M
1M
0.01
0.1
22
0.01
0.1
0.01
0.047
1
0.1
0.1
1
1
All resistors are 1/4 watt - 5 % tolerance. except as
marked with (*) which are 1 % tolerance. Values given
in (0).
All capacitors are 5% tolerance. except as marked with
(*) which are 1 % tolerance. Values given in p.F.
3-97
AN·21
Precision Narrow-Band Tone Detector
INTROOUCTION
PRINCIPLES OF OPERATION
The Phase-Locked Loop (PLL) is a very versatile building block with a wide range of applications in signal processing and communication systems. As a tone detector or tone discriminator, the PLL is accurate and stable
enough for most applications not requiring very narrow
bandwidths. The smallest, practical detection band is
limited by the temperature stability of the PLL center
frequency and accuracies of external components. For
example, deSigning a tone detector using a single PLL
to discriminate a 10Hz tone out of 100 kHz can present
great difficulty. A PLL with center frequency of 100 kHz
can drift by 2 Hz/oC given a typical center frequency
drift of 20 ppm/oC. A slight change in ambient temperature can cause the PLL to unlock. On the other hand,
there are various applications involving pressure transducers and crystal oscillators that require a very stable
system capable of detecting a small change in frequency over a wide frequency spectrum.
Figure 1 shows the block diagram of the narrow-band
tone detector using the XR-2208 and XR-2213. The
XR-2208 is being operated as a balanced modulator or
frequency mixer. It "mixes" the input frequency, fiN,
with a stable frequency source, fC, to produce the sum
and difference frequencies of fiN and fC. The low pass
filter removes the higher frequency component (fiN +
fC) and passes the difference frequency to the XR-221.3
PLL. The input signal is "mixed-down" in frequency In
this manner, allowing the PLL center frequency, fo, to
be set at a much lower frequency than the input signal.
With a lower fo, the PLL drift (Hz/oC) becomes less,
making the tone detector less susceptible to ambient
temperature changes.
The input signal to the XR-2208 is a periodic waveform
with frequency of:
fiN ± AflN
This application note describes the use of the XR-2213
PLL in conjunction with the XR-2208 analog multiplier
as a frequency mixer. It is capable of detecting a 1 Hz
tone out of a frequency spectrum greater than 1 MHz. It
can accept almost any periodic waveform including
sine, square, and triangular waves. Error due to temperature drift is typically 0.2 %/oC. The tone detector output changes to a high state when the input is within the
detection band.
where AflN is the detection range. The range of frequencies for detection is between fiN - AflN and fiN
+ AfIN. It is necessary to band-limit the input frequency for proper operation of the tone detector. Since the
XR-2208 takes the "absolute" difference in frequency
between fiN and fC, it is possible to obtain the same
output frequency with different values for fiN, .causing
the tone detector to lock onto the "wrong" frequencies.
lIN
2213
r------------,
I
I
I
fiN - fC
I
I
I
I
I
Ie
I
I
I-------t:>--t-<> VOUT
L ___________
.J
,---"1
---.llO
Figure 1. Functional Diagram of Narrow Band Tone Decoder.
3-98
AN·21
Table 1. Tone Decoder Performance vs . .:lflNlfo
In order to band-limit the input frequencies, a low pass
filter with very sharp roll-off (6th order or higher) with
the corner frequency around fiN can be used. For high
frequency applications (fiN> 100 kHz), a bandpass
crystal filter can be used. Crystal filters have stable frequency characteristics and very high Q's (Q > 1000)
making very sharp bandpass filters. Crystal filters are
commercially available through various manufacturers.
±~IIN
10
0.1
0.5
1.0
5.0
10.0
20.0
The control frequency, fC, must come from a very stable and accurate source since any error in fC will directly affect the tone decoder. A crystal oscillator with a
"divide-by-N" counter as shown in Figure 2 can generate a very stable frequency, with temperature stability
in the range of 1 ppm/DC.
%
%
%
%
%
%
TYPICAL
PLL 10
STABILITY
(Hz/DC)
0.02
0.004
0.002
0.0004
0.0002
0.0001
NORMALIZED
RELATIVE
ACQUISITION
TIME
x ~IIN
x AfIN
x AfIN
x ~IIN
x ~flN
x ~flN
0.1
0.5
1.0
5.0
10.0
20.0
fiN
fiN
fiN
fiN
fiN
fiN
+ ~fIN(1999)
+ ~fIN(399)
+ ~fIN(199)
+ ~fIN(39)
+ ~fIN(19)
+ ~fIN(9)
fo = PLL center frequency
input frequency range
~flN =
fiN ±
The control frequency is given by:
MAXIMUM liN
ALLOWED (Hz)
DESIGN EQUATIONS (All R's in ohms; all C's in farads)
fC = fiN + fo
1. The XR-2208 control frequency, fC, is given by:
where fo is the PLL center frequency in Hz. the Choice
of fo is arbitrary, however the larger fo is, the more the
PLL becomes susceptible to temperature variations but
the better the acquisition time or "pull-in" time becomes. One the other hand, if fo is small, then temperature variation has less effect but acquisition time becomes worse. Table 1 shows the relative performances
of the tone decoder with respect to the ratio of .:lfIN/fo.
fC = fiN
+ fo
2. The maximum input frequency allowed is:
fIN(max) s fiN
+ 2fo -
~fC
Where ± .:lfC is the capture range of the PLL.
3. The capture range, ±.:lfC, is set as:
The output of the low pass filter is fed into the pre-amp
of the XR-2213 PLL. When this frequency falls within
the detection band or the PLL (fo ± .:lfC), the voltage
comparator goes to a high state and remains there until
the input frequency falls outside the detection band;
the output voltage then goes to a low state. when there
is no input signal applied to the XR-2208, the PLL output remains low.
±.:lfC = ±.:lfIN
Where ±.:lfIN is the input frequency variation.
4. The lock range, ± .:lfL, is set equal to ± .:lfC:
.:lfC
RO
fo
R1
(Hz)
5. The loop damping factor, 0, is set to 0.63:
'c
0=1.
@Q
4~C;
6. The PLL center frequency, fo, is given by:
fo
= _1_
(Hz)
ROCo
7. Loop detect filter capacitor, Cd, is given by:
' - - - - - - - 1 c,
.:lfC in Hz
RO is set to 470 k!l
Increasing Cd slows down the logic output response
time.
5 Mil - 10 Mil
20 pF
8. The low pass filter time constants, CF and RF:
1 pG - 30 pF
C1 Pulls the crystal down (lower frequency)
RF CF =
.1.
fo
C2 Pulls the crystal up (higher frequency)
Where fo is the PLL center frequency.
Figure 2. Crystal Oscillator.
3-99
AN·21
DESIGN EXAMPLE
5. ±afC =
Consider the design of a narrow-band tone detector
with frequency detection range of 111.7 kHz ± 10Hz
(fiN ± afIN)·
±~fL =
Rl
±10 Hz
= RofolafC =
100 KO
6. The damping factor is set to 0.63:
1. Choose the PLL center frequency to be 100 Hz.
Cl = Co
(~)2
= 0.161'F
fC = 111.8 kHz
7. Loop detect filter constants:
fC can be produced by using a 3.58 MHz crystal (adjusted to 3.5776 MHz) and using a divide-bY-32
counter in a crystal oscillator.
Choose RD = 75 KO to prevent harmonic locking.
Cd = 16/20 Hz = 0.8 I'F
2. Maximum input frequency allowed is:
8. Low pass filter time constants, CF and RF:
fIN(max) = 111,890 Hz
RF = 20 KO
3. Capture range, ±afC is:
CF
±afC = ±10 Hz
1/foRo
= 0.5 I'F
A circuit schematic for the above tone detector is
shown in Figure 3.
4. PLL center frequency is 100 Hz (fa):
Choose Ro = 10 KO (choice is arbitrarily set between 10 KO s Ro s 100 KO)
Co
=
Typical acquisition time for this circuit is less than 100
msec.
= 1/foRo = 1.0 I'F
+10V
~O.'''F
+10Y
~O.''''F
10K!!
RO
8KO+5KOpot
Co = 1.0 /LF (non-polar)
Rl
= 100 KO
Cl = 0.16/LF
+.v
"pF
c· - 3.571 MHz
~'''F
RD
75 KO
CD
0.8/LF
RF
20 KO
CF
0.5/LF
10pF
Figure 3. Circuit Schematic of Narrow Band Tone Decoder_
3-100
AN·22
XfR{a2~ [))/){fR{a2~ 5/XfR aS200
rPrtiJ[ffi$®al(Q)©~®(QJ l(Q)(Q)~s
INTRODUCTION
produces a periodic signal whose frequency is propor·
tional to the error voltage. The VCO is actually a "cur·
rent" controlled oscillator (ICO) in the sense that it is
the current derived from VOUT that actually controls
the frequency of oscillation.
This Application Note discusses the various parameters
and equations used in applying the XR·210, XR·215,
and XR·S200 Phase Lock Loop (PLL) successfully. It de·
scribes the operation of the phase detector and the
voltage controlled oscillator as well as a discussion on
phase comparator gain, VCO gain, lock range, capture
range and free running frequency. A section on low
pass filters contains most common RC filters and a dis·
cussion on damping factor. Finally, a summary of PLL
parameters and a design example are included.
PHASE
COMPARATOR
VOUT
LOW PASS
FIL TEA
XR-210
The functional diagram of the XR·210 Phase Locked
Loop (PLL) is shown in Figure 1. The phase comparator
produces a dc voltage which is directly proportional to
the phase difference between the two input signals.
This error voltage, VOUT, is then filtered and applied to
the voltage controlled oscillator (VCO), which in turn
to
Figure 1. Phase Locked loop Functional Diagram.
V+ o-----------~----------~--------------------------..,
• 6 K!!
3.2 Ku
6 K!!
!
1 mA
1 mA
BtAS
Figure 2. XR-21D/XR-215 Phase Comparator.
3·101
VOUT
AN·22
+V
PHASE COMPARATOR
VIN (41
The circuit diagram of the XR·210 phase comparator is
shown in Figure 2. The input pins (4 and 6) and the bias
pin (5) are externally biased to approximately Y2 V+ to
Insure proper operation. The input signals must be ca·
pacitively coupled to Pins 4 and 6.
-v
VIN (61
+6 V
The output voltage on Pins 2 and 3, VOUT, depends on
the relative phase, 50 mVRMS) to cause limiting in the
differential stage. All calculations are done at V + . = 12
volts.
-v
VIN (61
Case 1: Input voltages are equal to the bias voltage.
YOUT
The operating current is shared equally between tran·
sistors 022, 028, 039, and 040. This causes approxi·
mately 0.5 rnA to flow through the output resistor (6 KG)
and hence VOUT = 0 volts. The voltage on Pin 2 and
Pin 3 is approximately equal to:
Figure 3b. 45° Out of Phase.
PHASE
DIFFERENCE
OUTPUT
VOLTAGE
(VOUTI
V+ - (0.5 mAl (6KO) = 9 volts.
LOCK
RANGE
+6 V
Case 2: Input voltages are both greater than the bias.
6fL
022 and 040 conduct 1 mA each, causing 038 to can·
duct 1 mAo Therefore V2 == 6 volts, V3 == 12 volts and
hence VOUT == -6 volts.
(·1>1
I
'1
I
180
I
I
I
I
OV
90
The same output conditions are obtained if the input
voltages were both less than the bias.
-6V
Case 3. Input voltages are out of phase and VIN (Pin 6)
is greater than the bias.
Figure 4a. Phase Detector With No Saturation.
022 and 039 conduct 1 mA each, causing 035 to can·
duct 1 mA. Therefore, V3 == 6 volts, V2 == 12 volts and
hence VOUT == +6 volts.
PHASE
DIFFERENCE
OUTPUT
VOLTAGE
(YoUTI
(,'·1
+
The same output conditions are obtained if VIN (Pin 4)
were greater than the bias.
T
I
Figure 3 shows the output voltage wave form when the
input signals are 90° and 45° out of phase.
+1.7 V
Notice that the duty cycle of the output waveform
changes as the phase difference of the input signals
change. For illustration purposes, square waves are
shown as input signals, however, other periodic wave·
forms would produce similar output waveforms.
-1.7 V
OV
------ -~- ----~~~~ ~~ ±':
--------,I
fo
Figure 4b. Phase Detector With Saturation.
3·102
180
t+
I
AN·22
It is possible to obtain a tracking range close to 90· ±
90· by connecting an external resistor network to the
phase detector output as shown in Figure 5. This circuitry limits the output swing to 10 ± 1 volt and prevents the internal circuitry from saturating at extreme
phase conditions.
The output of the phase detector is connected to a low
pass filter which converts the square wave output to an
approximate dc voltage. The relationship of this dc voltage, VOUr. with respect to the input phase difference,
.p, Is shown graphically In Figure 4a. Assuming no saturation occurs in the internal circuitry, a PLL can lock onto an input signal with maximum difference of 180· to
o· with respect to the veo signal.
The phase comparator gain for the XR-210 is approximately given by:
Due to internal saturation of the output, the maximum
phase difference the XR-210 can track is approximately
50· or 90· ± 25·. This is because the output transistors
of the phase detector saturate at approximately 8.3
volts and the maximum output voltage, VOUr. obtainable is about ± 1.7 volts. Figure 4b shows the phase
detector characteristic of the XR-210.
K.p == 4.0 VOLTS
RADIAN
With the external bias network, it is approximately:
K.p ==
VOLTS
RADIAN
r-----------,
U2Q
c,
(2)
~ ----- -:,~'- -l_-':~
c,
f.JITERNAl
BIAS
ROUT'" 2.0 Kg
Figure 5. External Resistor Bias Network.
vOUT----l
A,
c,
260 0
Figure 6. XR-210 Current Controlled Oscillator.
3-103
AT
(3)
AN·22
CURRENT CONTROLLED OSCILLATOR (ICO)
The change in timing current with RT is given by:
~ IT :;; 0.17 mA
The functional diagram of the ICO is shown in Figure 6.
The output frequencY,fo , is directly proportional to the
total timing current, ITo seen by the ICO.
(11)
RT
The free running frequency can now be given by:
fo
0/
(4)
IT
fo :;; 200 (1
Co
Any change in output voltage of the phase comparator
causes a change in fo as follows:
~fo
0/
~ VOUT
KO=~
~ VOUT
Combining equations 4 and 5 yields:
2'11' fo
= -
2'11' (200 1
Co
+
0.17)
RT
:;; - - > - - = : - - - - < - (13)
RO IT
RO IT
However, the timing current is now:
(6)
IT:;; (IX +
RO IT
where IT is the total timing current with VOUT = 0 volt.
In this case, IT = IX :;; 1 mA. Substituting this into
equation 6 yields the ICO conversion gain:
KO = ~ :;; 2'11' fo RADIANS/SEC
~ VOUT
RO
VOLT
(12)
The ICO gain is now:
where RO is the external resistor between Pins 11 and
12. It will be shown in the following section how RO sets
the lock range of the PLL.
~ VOUT
0.17 HZ)
RT
where RT is in KO and Co is in p.F.
(5)
RO
~=~
+
°R~)
mA = (1 +
°R~)
mA
(14)
Substituting this into the ICO equation yields:
KO:;; 200(2'11') = 1256 RADIANS/SEC
Co RO
RO Co
VOLT
(7)
(15)
and remains unchanged with the addition of RT
where RO is in KO.
Note: The discrepancy between the calculated and
measured KO can be attributed to tolerances of
internal resistors and errors in approximating IX.
The minimum value ofRO should be approximately
1.7 KO. This is because the maximum current through
RO must be limited to 1 mA and since VOUT has a maximum range of approximately ± 1.7 volts, RO must be
limited to greater than 1.7 KO.
LOCK RANGE
The lock range of a PLL, ± ~wL' is given by:
The free running frequency of the PLL is given by:
F
f0:;; -200C"
0 IS Inp..
Co
(8)
where 8E is the maximum phase difference at the detector inputs in radians. 8E is approximately equal to
0.43 radians (25°).
Substituting this into ICO gain equation 7 yields:
KO:;; 1256 RADIANS/SEC
ROCO
VOLT
(9)
Using measured values for K and KO yields:
± IlwL:;; 1565 RADIANS
where RO is in KO and Co is in p.F.
RO Co
Experimental data yields:
KO :;;
.J!.!Q.. RADIANS/SEC
RO Co
(17)
SEC
where RO is in KO and Co is in p.F.
(10)
VOLT
XR-215
The above equations were calculated without the ICO
tuning resistor, RT, connected to Pin 9. Adding RT increases the timing current and hence increases the
free running frequency. fo:
The XR-215 PLL is basically the same as the XR-210.
The major difference is in the ICO section which is described below.
3-104
AN·22
PHASE COMPARATOR
With the ICO tuning resistor, RX, connected to Pin 10,
the free running frequency is increased by a factor proportional to the change in timing current:
The phase comparator conversion gain is given by:
K == 3.6 VOLTS
RADIAN
(18)
Llf ex Ll IT == 0.7
RX
Saturation of the internal circuitry occurs limiting the
tracking range of the phase detector to about 90 0 ±
25 0 •
The ICO free running frequency is given by:
fo == 220 (1
Co
An external resistor network shown in Figure 5 can increase the range to about 90 0 ± 90 0 • The corresponding conversion gain becomes:
K == 1.3 VOLTS
RADIAN
(23)
+
(24)
0.7)
RX
where RX is in KO and Co is in J.'F.
KO == 1140 RADIANS/SEC
RO Co
VOLT
(19)
(25)
ICO
and remains unchanged with the addition of RX.
The current controlled oscillator of the XR-215 is shown
in Figure 7. The ICO conversion gain is given by:
LOCK RANGE
The lock range of the XR-215, ±LlwL, is given by:
KO
Since IX
=
=
2'/1' fo RADIANS/SEC
RO IX
VOLT
1.1 mA and fo
(20)
± LlwL = (K and KO yields:
= 220,
Co
KO == 1256 RADIANS/SEC
RO Co
VOLT
±LlWL == 1765 RADIANS
RO Co
SEC
(21)
(27)
where RO is in KO and Co is in pF.
where RO is in KO and Co is in J.'F.
Note: Using the external bias network (Figure 5) does
not change KO' To calculate the lock range with
this network, OE should be set to approximately
'/1'/2 radians (90 0 ).
Experimental data yields:
KO == 1140 RADIANS/SEC
RO Co
VOLT
(22)
I----VOUT
RO
r-----------.----~12r_-~·~-~
Co
1 mA
Rx
..1
Figure 7. XR·215 ICO.
3-105
1 mA
AN·22
With Pins 15 and 16 open, fo is given by:
XR-S2oo
==
The XR-S200 PLL is basically. the same as the XR-210
and 215 except that many of the interconnections are
made external to the chip. These external connections
can aid in the flexibility of the chip.
since IX
PHASE COMPARATOR
With Pins 15 and 16 tied high, fo is given by:
fo
==
200 (Ix
Co
==
1 mA, 11
The phase comparator outputs are not tied internally to
the ICO as the XR-210 and 215. The measured phase
comparator gain is approximately:
==
fo
+ 11 + 12) = 500 Hz
(30)
Co
0.5 mA, 12
==
1 mAo
200 (IX) = 200 Hz
Co
Co
(31)
where Co is in /-IF.
K,p
== 4 VOLTS
RADIAN
(28)
With Pins 15 and 16 open:
KO= 211" fo
RO IT
Saturation of the internal circuitry occurs limiting the
tracking range to about 90 0 ± 25 0 • This range can be
increased by using the bias network shown in Figure 5.
where IT = IX
+ 11 + 12
ICo
KO
==
==~
==
2.5 mA, thus
1256 RADIANS/SEC
RO Co
VOLT
The current controlled oscillator of the XR-S200 is
shown in Figure 8. The ICO gain is given by:
(32)
RO Co IT
(33)
where RO is in KO and Co is in /-IF.
KO = 211" fo RADIANS/SEC
RO IT
VOLT
(29)
With Pins 15 and 16 tied high:
Ko==~
where IT is the timing current when VOUT = 0 volts.
(34)
RO Co IT
The ICO free running frequency, fo, can be modified by
applying a digital pulse on Pins 15 and 16 through a diode and a 1 KO resistor. By changing the voltage states
on these Pins, it is possible to obtain four discrete frequencies for fo . By connecting a resistor from either Pin
15 or 16 to ground, it is also possible to modify the center frequency.
where IT = IX
==
KO
1 mAo Thus
==
1256 RADIANS/SEC
RO Co
VOLT
and remains unchanged.
"
I
Co
IX
I mA
0.71<
"
Figure 8, XR-S200 ICD.
3-106
, mA
(35)
AN·22
LAG FILTER
LAG FILTER
1
F(S) = 1 + 2 T1 S
1
F(S) = 1 + T1 S
W1/
=
LAG-LEAD FILTER
LAG-LEAD FILTER
LJ
R.
F(S)
=1+
=
W
j
1/
+ T2 S
S(2T1 + T2)
1 + T2 S
F(S) = 1 + S(T1 + T2)
1
KV
(2T1
+ T2)
/) =
1
2
j
T1
Kv
+ T2
FOR T1 »
/)=
2
~
2KV T1
il = __1 _
(1 +T2KV)
2~
Figure 9. Low Pass Filters.
3-107
(T2 + K1v)
T2
(1
+ T2
KV)
AN·22
Measured value for KO is approximately:
KO;; 1262 RADIANS/SEC
RO Co
VOLT
(36)
LOCK RANGE
Using measured values for K and KO yields:
±awl;; 2170 RADIANS
RO Co
SEC
20
(37)
where RO is in KO, and Co is in I'F.
V
/
LOW PASS FILTER
The low pass filter section for the XR-210/215/S200 is
formed by connecting an external capacitor or RC network across the output of phase comparator section.
Most common passive low pass filters are shown in
Figure 9. R1 is the internal resistor with nominal value
of 6 KO. If an external bias network as shown in Figure
5 is used, R1 = 2 KO. Pin numbers shown in Figure 9
apply to the XR-210 and XR-215.
/
10
V
20
26
V+ (VOLTS)
Figure 10. Maximum Input Voltage vs. Supply VoHage.
The term KV shown in the filters is the total forward gain
of the Pll and is equal to the product of K and KO'
however, by adjusting T, the damping factor as well as
the capture range is changed. These two parameters
can be individually controlled in a lag-lead filter.
CAPTURE RANGE
The capture or acquisition range of the Pll, ± awC,
can be approximated as:
± awC ;; ± aWL IF(j awC) I
General systems and control theory indicates that for
maximum stability the damping factor, 0, must be
greater than 0.7. In many FSK demodulation circuits
using Exar Plls, it was found that with Ii as low as 0.2,
the circuit functions properly at high baud rates.
(38)
where IF(j awC) I is the magnitude of the low pass filter
evaluated at w = awC. Since I F(j awcli is always less
than unity, the capture range is always smaller than the
lock range.
DESIGN EXAMPLE
Design an FSK demodulator using the XR-210 with the
following specifications:
There is no explicit relationship for calculating awC,
however for a simple lag filter, it can be expressed as:
±awC;;
fKV RADIANS
'\1-;;
Mark frequency: 1070 Hz
Space frequency: 1270 Hz
Vcc: + 12 volts
(39)
SEC
1. fo = 1170 Hz
For lag-lead filters, capture range can be roughly estimated by wfl' (See Figure 9.) Actual data indicates that
capture range is larger than wfl and approaches the
lock range.
Co = 200 ;; 0.2 I'F
fo
AT (Pin 9 to GND) for correct fo.
Adjust
DAMPING FACTOR
2. aWL
The advantage of using a lag-lead filter is that generally
speaking, it gives better stability due to the extra zero.
The damping factor can be adjusted without necessarily changing the capture range. With a simple lag filter,
RO =
3-108
=
2"l1' (afLl
=
2"l1' (200 Hz)
1565 = 6.23 KO
aWL Co
=
1256 RAD/SEC
AN·22
3. Set capture range, AwC, equal to AWL. Using a laglead filter, AwC can be approximated by:
4. The damping factor is given by:
li =
1. ~
2
(1
2 KV 71
+
72 KV) == 0.22
Even with critical damping (Il < 1.0), the XR-210
functions properly as an FSK demodulator with baud
rate of 300 BPS.
KV = KOKrJ> == 2921
»
Let R2 = 50 O. Thus 71
5. For V + of 12 volts, the input voltage should be limited to 5 volts PK-PK to avoid internal saturation (see
Figure 10).
72
6. Schematic for the above example is shown in
C1 = 0.15 JLF
Figure 11.
12 V
5K
10 K
5K
16
12 V
2K
4K
4K
Co
=
0.2 MF
RO = 6.23 KH
f"'
01 .. F
15
3K
F5K IN
C1 = 0.15MF
R2
= 50
H
RT
= 10 K!l
11
10 K
RT
Co
RO
Figure 11. XR·210 FSK Demodulation.
3-109
AN·22
Table 1. Summary of PLL Parameters (1)
PARAMETER
Phase Comparator
K
XR-210
4.0 VOLTS
RADIAN
3.6 VOLTS
RADIAN
910 RAD/SEC
VOLT
VCO KO
1140 RAD/SEC
VOLT
RO Co
Lock Range ± ~"'L
XR-S20D
XR-215
ROCO
4.0 VOLTS
RADIAN
1262 RAD/SEC
VOLT
ROCO
1565 RADIANS
-
1765 RADIANS
-
2170 RADIANS
-
RO Co
RO Co
RO Co
SEC
500 Hz
Co
(2)
SEC
Free Running
Frequency fa
200 (1
Co
Capture Range ±~"'C
(Simple Lag) (3)
~KOK
Damping Factor 6
(Simple Lag)
2
+
0.17) Hz
RT
71
200 (1
Co
SEC
+
0.7) Hz
RT
~KOK
~KOK
1~
KOK71
2
71
1~
KOK71
2
(1) RO, Rr. RX in KO
Co in,.F
(2) fa shown for Pins 15 and 16 open
(3) For other filter configurations, refer to the filter section. 71 = R1 C1.
3·110
71
1~
KOK71
AN·23
High-Performance Frequency-lo-Voltage
Converter using the XR-2211
INTRODUCTION
A stable highly linear flv converter can be easily designed using the XR-2211 phase locked loop. The flv
can be used for a dynamic range from ± 1 % to ± 80 %
over a frequency range of .01 Hz to 1 MHz.
Figure 1. F/V Block Diagram.
vo
The block diagram of the flv is shown in Figure 1. The
circuit will perform flv conversion according to the rela·
tionship
X INTERCEPT = K2
SLOPE = Kl
2 VREF
where K1 and K2 are set by the designer.
VREF
The transfer function relating Va to fiN is shown in Figure 2. The carrier detect output, Q, (Pin 5) which goes
high over the tracking range is shown in Figure 3.
10
The basic circuit diagram is shown in Figure 4. The
slope K1 is determined by the relationship
liN
Figure 2. F/V Transfer Function.
K1 = _-_1_
VR COR1
a
where VR = VCcJ2 - VSE
The x intercept or upper frequency, K2 is determined by
the relationship
Vcc
DESIGN EXAMPLE
Figure 3. F/V Carrier Detect Output.
Design a flv converter for the frequency range 100 Hz
to 600 Hz.
resolution "" VCC - VSE
fH - fL
The first step is to calculate the center frequency fo,
(Figure 2) in
18 - 1.3
600 - 100
33.4 mV
Hz
forVCC=18V
fo = fL
+ fH
2
= 100
+
2
600 = 350 Hz
We can now calculate VREF
VREF = VCcJ2 - VSE = 9 V - .65 V = 8.35 V
Supply voltage is directly proportional to the degree of
resolution obtainable.
The center frequency is given by
In order to obtain a greater resolution a higher supply
voltage is used. For this design an 18 V supply is used
giving us a resolution of approximately
fo = _1_
ROCO
3-111
AN·23
'"
l' t 1.
"
'a
Figure 4. FlY Circuit Diagram.
choosing RO = 20 K and rearranging
and a cut-off frequency
1
1
Co = ROFO = (20 KO) (350 Hz)
fC=_12J.1RFCF
Selecting RF = 100, K, CF is then given by
= .143 J.lF
Since
C "" _3_ F
RO = (fH - fL)
F
2 fO RO
(fH - fLl
~ = maximum expected rate of
where
2 (350 Hz) (20K)
(600 - 100) Hz
At
change of input frequency
~
for
=
At
28 K
giving
T
2.... /LF
300
= .01 J.lF
= 1 J.lsecs FC = 160 Hz
A carrier detect output is available at Pins 5 and 6 (0
and 0). The components Co and RO comprise the lockdetect filter. For RO = 470 K, and a capture range approaching the lock range, a minimum value of CD is
given by
C1 "" Co = .143 J.lF = .035 J.lF
4
It should be noted that an increased value of C1 will increase response time but reduce ripple, while a decreased value of C1 will reduce response time; increase capture range, but increase ripple.
CO(J.lF) ~ _1_6- = ...:!§.. = .032 J.lF
fH - fL
500
The slope K1 can now be calculated
RO = 470 K
TEMPERATURE STABILITY
K1 = _ _ _ =
1
VRCOR1
(8.35) (.143 J.lF) (28 K)
The XR-2211 is characterized by excellent temperature
stability, in the order of 50 ppm/aC. The output voltage
temperature coefficient can be calculated by
= 29.91 Hz
V
:i.
and since K2 = fMAX = 600 Hz
°C
The transfer function is then given by
fiN = -29.91 Vo
= 300 cycles/sec
CF =
The selection of C1 , the loop filter capacitor has a degree of flexibility in its value. For a damping coefficient
of .5.
4
AIIAt J.I
2 fo
R1
=
...!.
K1
x 50 ppm x (fH - fL)
ac
substituting
+ 600
= 33.4 mV x 50 ppm x (600 - 100) Hz
Hz
The filter RF CF forms a one-pole post detection filter,
with a time constant
.8mV
ac
3-112
INTRODUCTION
CIRCUIT DESIGN
Most phase-locked loops require manual potentiometer
adjustment if the center frequency of the circuit is critical. Also, once adjusted, if ambient temperature
changes cause the PLL's VCO or center frequency to
shift, the potentiometer would have to be readjusted if
the accurate center frequency was to be maintained.
Readjustments are, of course, an impractical solution.
Figure 2 shows the XR-215 internal blocks and necessary external components. The VCO center frequency,
fo, is calculated by the formula:
f
o
= 200
Co
(1
+
0.6) Co .in JLF
RX RX In KO
(1)
In this application it is desirable to have a variable current drawn from Pin 10, and RX omitted. Equation 1 is
then modified to equation 2 is a current instead of a resistor is used at Pin 10.
This application note describes the design of a digitally
programmable PLL. Being digitally controlled, a microprocessor or other digital circuitry could easily tune or
retune the VCO when necessary. The design uses the
XR-215 monolithic PLL together with the XR-9201 D/A
converter, which provides the tuning function.
f
PRINCIPLES OF OPERATION
o
= 200 (1
Co
+
I
) Co in JLF
PIN 10 IplN 10 in mA
(2)
Equation 2 can now be used to determine IplN 10 for a
given fo adjustment range. Once the center frequency
has been set, RO can be calculated to adjust the tracking range using the relationship:
Figure 1 shows the block diagram of the digitally programmable PLL. The circuit is comprised of two blocks:
the PLL and the D/A converter. The PLL is used for FM
demodulation, synchronizing signals, or frequency synthesis. It processes these signals, which are centered
around its free-running frequency, fo . This fo is set by
the internal voltage-controlled oscillator, VCO, in the
PLL. The VCO within the XR-215 is really a currentcontrolled oscillator, ICO. This is, the frequency of oscillation of the ICO is directly proportional to the timing
current, IT- IT is made up of two components: an internal fixed current and an externally programmable current, IplN 10. This IplN 10 control current is provided by
a D/A converter with a current output. Since the D/A
provides an output current that is directly set by an input digital code, this code will actually control the center frequency of the PLL's ICO, fo .
± /),.wL = 2"11".6.fL '" 1565 rad RO in KO
ROCO sec Co in JLF
or
RO
=
1565 RO in KO, Co in JLF
2"11".6.fLCO
(3)
(4)
Now with RO calculated for .6.fL, the capture range, .6.fC
is set using the loop time constant capacitors C1:
±.6.WC = JKoKq, = 2"11".6.FC
T1
(5)
T1
= Loop Time Constant
Ko = VCO Conversion Gain
Kq, = Phase Detector Conversion Gain
Substituting the values for KoKq, and solving for FC:
Vo
.6.FC
= .J.....
2"11"
loo-f-4----<
or
0.684
ROCOC1
0.017
R in KO C in F
.6.fC2ROCO 0
' . 0 JL
(6)
(7)
The resistors RI and RF are used to set the gain of the
op amp when used for FM demodulation. Cc is op amp
compensation and is in the range of 300 pF for unity
gain to 50 pF for a gain of 10 and up. The resistors going to Pins 4, 5, and 6 are used to dc-bias the phase detector inputs at half supply, with their actual value not
critical. The capacitors C2 and C1 are used for capacitive coupling.
DATA INPUT
Figure 1. Programmable Pll Block Diagram.
3-113
AN·24
r-----------------~--~~C
Rf
5K
2K
O.I.F ~-II,N'w--~~
fin
0--4 f-t-------..J
C,
2K
5K
fo
o----+---------{"5i)----<
10K
Figure 2. XR-215 with External Components.
DATA INPUT
17 - - - - - - - - - -
-- -
10
LATCHES
R
CURRENT
SWITCHES
-VCC
GND
R
Figure 3. XR-9201 D/A with External Components.
Figure 3 shows the D/A converter internal blocks with
external circuitry. Data is fed into the input latches,
which will allow data to flow through to the current
switches when CE is high and hold data when CE is low.
The output currents are related to the digital inputs by:
Also: 10
BN
BN
B7
BO
TO =
IFS = Full-scale Current
IFS = 2IREF(255)
256
(9)
(10)
The full-scale current is set using R by the relationship:
B7 B6 B5 B4 B3 B2 Bl
BO]
10=2 IREF [ -+-+-+-+-+-+-+- (8)
2
4
8 16 32 64 128 256
where
+
VREF
R = - - VREF = 2 V
IREF
= 1 if bit N is high
= 0 if bit N is low
= MSB
= LSB
(11)
The 10 KO potentiometer from Pin 3 to ground is used
to fine-adjust the internal reference to exactly 2.00 V.
3-114
AN·24
DESIGN EXAMPLE
Design a digitally programmable PLL with a center frequency, fo, equal to 20 kHz. Provide for a 10% digital
tuning range. The circuit shall also have the following
lock and capture ranges:
4. C1 is determined by equation 7:
C
±AfL = 5 kHz, ±AfC = 4 kHz
Co = 0.01 p.F
fo = 20 K
IREF
= 5 K!1
O--r------,
o.022~Fl
l
I
·F
O.022I'F
0.1,,'
= 50 p.A
Figure 4 shows the completed design example.
5.
"
" 0--11-1---,
PHASE
DETECTOR
O.I,.F
XFl·215
'. o-+-+-v-tO-~-"f-<
OUTPUT
...
..
O.OI"F
F
7. Calibration of the system is accomplished by adjusting potentiometer R3 for VREF on the XR-9201 to exactly 2.00 V.
3. RO is now calculated from equation 4:
+t2V
p.
R = 2.00 = 40 K!1
50 p.A
+ 2 K Adjustment Range
R =
1565
o
(211") (5 K) (0.01)
= 0.022
6. The reference current setting resistor, R, is now determined using equation 11:
22 K (0.01) -1 = 0.1 mA
200
IplN 10 = _0_ _ 1
(max)
200
0.017
(4 K)2 (5) (0.01)
IplN 10 max = IFS 2 IREF(255)
256
2. This same equation is used to determine the maximum value of IplN 10 for a 10% change in fo . Rearranging equation 2 yields:
f Co
=
5. The D/A components can now by specified, first using equation 10 and the previously calculated IplN
10 maximum current:
1. Using equation 2, first with IplN 10 = 0 (digital inputs all zeros) Co can be determined.
fo = 200
Co
1
GNO
SK
I'P'NIO
DATA INPUT
C,
'0
XA·9201
.,
Figure 4. Digitally Programmable PLL.
3-115
+5Y
-7Y
+Vcc
"''''----+
-VEE
1-'---+-+
AN·25
Full-Duplex 1200 BPS/300 BPS
Modem System
ceived signal range can vary from about 0 dBm to
-45 dBm.
INTRODUCTION
This application note describes the construction of a
full-duplex modem system which operates at either
1200 BPS with phase shift keying encoding (PSK)
or 300 BPS with frequency shift keying (FSK). The
1200 BPS is in a synchronous format or 300 BPS asynchronous.
DEMUX. Demultiplexer to switch transmitted carrier
(Txc) and received data (Rxd) between 300 BPS and
1200 BPS.
AUTO SPEED SELECT. Automatically senses whether
300 BPS or 1200 BPS information is being received
and controls the demux with this information.
This system is not intended to be directly connected to
the telephone network as this requires FCC approval.
SLICER. A voltage comparator used to convert analog receive carriers (Rxcar) into digital signals suitable for the XR-2123 and XR-14412 Rxcar inputs.
PRINCIPLES OF OPERATION
The heart of this system is three LSI integrated circuits.
The XR-2120 is a switched-capacitor filter (SCF) to
provide precise bandpass filtering at 1200 Hz and
2400 Hz. The XR-2123 performs the 1200 BPS PSK
modulation/demodulation and the XR-14412 the 300 BPS
FSK modulation/demodulation. These three devices are
shown with the necessary external functions to perform
a 212A type synchronous modem in Figure 1. These
other functions are described as follows:
CARRIER DETECT (CD). A level sensor with a digital
output to indicate when a Rxcar is present.
TIMING CIRCUIT. This circuit extracts a 600 Hz receive signal timing from the Rxcar for synchronization purposes in the XR-2123.
SCRAMBLER/DESCRAMBLER. These sections scramble the data to be transmitted (Txd) while descrambling the received data (Rxd).
LINE INTERFACE. Provide DC isolation between modem and telephone network. This section, known as
a direct-access arrangement, must be approved by
the FCC for direct connection to the telephone network.
DELAY CIRCUIT. To provide a delay between the request to send (RTS) data and clear to send (CTS) data commands.
AGC. Automatic gain control to provide a constant
Figure 2 shows the complete circuit implementation of
modem, with Table 1 listing the recommended circuit
values.
signal level to other portions of the circuit. Its re-
le,"o.,
t:
Figure 1. 212A Type Modem System.
3-116
CLOCK GENERATOR
TELEPHONE
LINE
_ RING
FULL-WAVE RECTIFIER
Cf
.....
AUTO SPEED SELECT
»
z
•
I\)
Figure 2. XR-212A Type Modem.
en
AN·25
A.
B.
C.
D.
E.
F.
G.
H.
I.
J.
K.
L.
M.
N.
O.
P.
Q.
R.
S.
T.
U.
XR-4741 Quad Op Amp
XR-4741 Quad Op Amp
XR-1458 Dual Op Amp
LM-339 Quad Comparator
XR-14412 FSK ModlDemod 300 BPS
XR-2120 Filter-Switched Cap
XR-2123PSK Mod/Demod 1200 BPS
CD-4049 Hex Inverter
CD-4016 Quad B1-Lateral Switch
CD-4030 Quad Exclusive-OR Gate
CD-4013 Dual D Flip-Flop
CD-4013 Dual D Flip-Flop
Dual 4 Bit Static Register 4015 .
Dual 4 Bit Static Register 4015
Dual 4 Bit Static Register 4015
Dual 4 Bit Static Register 4015
MM7404 Hex Inverter
DM74193 Synchronous Up/Down Counter
XR-1488 Quad Line Driver
XR-1489 Quad Line Receiver
XR-4194 Dual Tracking Regulator
R1
R4
R7
R10
R13
R16
R19
R22
R25
R28
R31
R34
R37
R40
R43
R46
R49
R52
R55
R58
R61
2.2K
2.2K
10K
10K
100K
10K
100K
62K
18K
4.7K
120K
68K
600
10K
39K"
39K"
39K"
13K
10K
10K
10K
R2
R5
R8
R11
R14
R17
R20
R23
R26
R29
R32
R35
R38
R41
R44
R47
R50
R53
R56
R59
2.2K
1.2K
10K
1K
47K
100K
10K
47K
62K
10K
10K
600
10K
10K
180K"
180K"
464"
71.5K
10K
1M
R3
R6
R9
R12
R15
R18
R21
R24
R27
R30
R33
R36
R39
R42
R45
R48
R51
R54
R57
R60
All resistor values are in ohms.
" = > 1 % tolerance.
Crystals
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
82 pF
.033 p.F
.022 p.F
.1 p.F
.033 p.F
_033 p.F
.033 p.F
.033 p.F
.033 p.F
.033 p.F
.1 p.F
0.22 p.F
4.7 p.F
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
CR1 CR2 CR3 -
1 p.F
.1 p.F
.001 p.F
.001 p.F
4.7 p.F
2.2 p.F
4.7 p.F
4.7 p.F
.1 p.F
.1 p.F
4.7 p.F
4.7 p.F
4.7 p.F
4.032 MHz
1,000 MHz
4.608 MHz
MTRON
FOX
X-TRON
Transformer
T1 -
T2220 MICROTRAN
Transistors
Q1 - A854
Q3 -C1741
Q4 -C1741
FEls
Q2 -
Component Ust for 212A Type Modem System
3-118
2N4861
ROHM
ROHM
ROHM
2.2K
1M
1M
62K
62K
470K
10K
100K
1K
1M
1K
300
10K
10K
392"
392"
180K"
10K
10K
10K
AN·26
High-Speed FSK Modem Design
INTRODUCTION
DESIGN EQUATIONS - Refer to Figure 6
As the need for transmitting data increases, some applications require data to be sent faster than the conventional telephone line modems. This application note
describes the design and construction of a high speed
full-duplex, FSK modem using XR-2206 as a modulator
and XR-21 0 as the demodulator transmitting data at the
rate of 100 Kilobaud.
1. The frequency of oscillation of the XR-2206 when
used as a modulator, with the FSK input (Pin 9) is
high is:
R7A
The block diagram in Figure 1 describes the basic
building block in any FSK modem system. The major
difference is that in high speed applications, data is
transmitted over a twisted pair wire or coaxial cable instead of the telephone line with its limited bandwidth.
The complete system is comprised of an answer and
originate modem. Simply stated, the modulator converts the input data to two discrete frequencies corresponding to its 1's and O's and is then sent over a line or
cable. The line hybrid steers these frequencies to the
bandpass filter, where it will remove any unwanted signals that might have gotten through due to the line or
cable before reaching the demodulator. The demodulator, which is a phase locked loop, will lock onto the incoming frequencies and produce 1's and O's on its output. A detailed description on FSK techniques is given
in the EXAR MODEM DESIGN HANDBOOK.
R8A
PLL
DEMODULATOR
ORDER NO
Cl
C2
2
3
4
1.414
3.546
1.082
2.613
1.753
3.235
.7071
1.392
.9241
.3825
1.354
.3090
5
SINEWAVE
C3
.2024
.4214
ANSWER
BANDPASS
BANDPASS
FILTER
PLL
DEMOOULATOR
FILTER
DATA
RECEIVED
16l)/240KHZ
lSO/24OKHZ
MODULATOR
R8B C3
Table 1
S60/640KHl
SENT
+
2. The filter best suited for modem applications is the
butterworth filter due to its linear phase response
within the passband. Table 1 shows the normalized
capacitor values for butterworth filters up to fifth order.
ORIGINATE
DATA
TO BE
R7B C3
When the FSK input (Pin 9) is low the frequency
equals
PRINCIPLES OF OPERATION
DATA
RECEIVED
+
saO/640KHZ
LINE
HYBRID
l.INE
SINEWAVE
HYBRID
MODULATOR
TWISTED
PAIR WIRE OR
COAXIAL CABLE
Figure 1. Block Diagram of High Speed FSK Modem System
3-119
OAT A
lOBE
SENT
AN·26
Figure 3 shows a third order active high pass filter. To
solve for the. actual resistor values we use the formula:
The equations for using the XR-210 as an FSK demodulator are as follows:
AFL = (2)AF
R = :-:-:--::-:-:-WcCNC
AF = Fmark - Fspace
Where CN is the normalized capacitor and Wc = 211"Fc.
In this equation, make all capacitors equal.
AFL = 2(Fmark - Fspace)
Fmark
FO =
After calculating Rx remember for single supply operation the op amp must be biased at 1/2 VCC; therefore
take twice the calculated value for Rx and configure as
shown in Figure 4.
c
-234 ( 1 +.1)
-
Co is in I'f
CO,
RTis in KIl
RT
234
Co =
AW
Fspace
2
FO =
Figure 3.
+
FO
=J
C1 =
AWL
6KC1
AWL
6KAWc2
+V
RO =
C18 =
C19 =
Figure 4.
Figure 5 shows a third order active butterworth low
pass filter. To convert from the normalized capacitor
values to the actual capacitor values, we use the formula:
2(1565)
RO is in KIl
AWLCO
10- 4
211" (Baud Rate)
10- 4
311" (Baud Rate)
DESIGN EXAMPLE
Design a FSK Demodulator with the following specification:
FO = 200 kHz
AFL = 160 kHz
Where CN is the normalized capacitor value and Wc =
211"Fc. In this equation, make all resistors equal.
Baud Rate = 100 Kilobaud
In this example, we musl know the mark and space frequencies. If Fmark = 160 kHz and Fspace = 240 kHz,
the free running frequency is equal to
Fmark
+
Fspace
2
= 200 kHz
In order to calculate the free running frequency, we use
the formula:
FO = 234
Co
Figure 5.
3-120
AN·26
For the filter, 18 dB of attenuation should be sufficient;
therefore:
In this example we will use a variable resistor (RT) in order to fine tune FO to exactly 200 kHz, therefore:
234
F0- - (1
Co
Design a third order high pass butterworth filter with fc
= 100 kHz.
+.1)
-
AT
1) In order to solve for actual resistor values use Table
1 and set all capacitors equal. The design example
is shown below:
The lock range (AFU is equal to twice the difference of
the mark and space frequencies, so
AFL = 2(Fspace - Fmark)
RO, which sets the lock range equals:
R _ 2(1565)
0- AWLCO
AWL = 2"11"FL
6.28 (160 x 103)
= 1004800
2(1565)
1004800.0015
Where Co is in p.f
and RO is in KO
R= __
1_
WcCNC
= 2.0 KO
The Capture Range (AFcl is equal to:
AW
c
_ r;;.wL
-Y6KC17
AWc = 2"11"AFc
AWL = 21rAFL
In order to solve for C17 we rearrange the equation to
read.
C17 =
R15 =
1
= 4500
(6.28 X 100x 103)3.546(1000X 10- 12)
R14=
1
=1.1KO
(6.28 X 100x 103)1.392(1000 X 10- 12)
1
= 7.8KO
R =
x (6.28 x 100 x 103).2024(1000 x 10 -12)
After calculating Rx take twice the value and configure as shown below:
(6K) Wc 2
+v
1004800
= 300x10- 12
(6K) 753600 2
j
R 16 = 15.6K
therefore:
Rx
AW
R17 - 15.6K
1004800
_ /
c - " (6X10 3)300X10- 12
= 118.97 kHz
Design a third order lowpass butterworth filter with Fc
= 300 kHz.
It is important to note C17 and 6K set the loop time constant. When used as an FSK Demodulator, the XR-210
has post detection filtering on the output of the phase
detector. In order to calculate the values for C18 and
C19 we use the relationships:
2) In order to solve the actual capacitances, use Table
1 and set all resistors equal. The design example is
shown below:
C10 • 1660 pI
10- 4
C18=--~--
2"11" (Baud Rate)
10- 4
- - - - . . . . , . - = 160x 10- 12 or 160 pf
6.28 (100 x 103)
C19 =
10- 4
9.42 (100 x 103)
Cg
106x 10- 12 or 106 pf
3·121
=73Bpl
I
AN·26
Design an FSK modulator with Fmark = 560 kHz and
Fspace = 640 kHz. The frequency of oscillation with
the FSK input (Pin 9) is high is equal to:
C = CN
WcR
C =
3.546
= 1880 f
2'11'(300 x 103) 1 x 103
P
------=-R7A + R7B C3
3.546
1884000000
= 1880 pf
1._39_2_
C9 = _ _
1884000000
738 pf
When FSK input (Pin 9) is low the frequency is equal to:
107 pf
Fspace =
C10
C11
=
Fmark =
.2024
1884000000
- - - - - - = 560 x 103 or 560 kHz
1K
+
785(1.0011'f
1
R8A
+
R8BC3
-:--:-::---::-::-:-:--:-:-~ = 640 x 103 or 640 kHz
1K
+
5620.0011'f
"..
,.
twlSTEO 'AUI WIRE 01'1
~ALC.""":::"'--_--=--i
....w
INATI0t4AU
Figure 6. Complete Schematic for 100 Kilobaud FSK Modem
3·122
~
I\)
'"
»
z
Figure 7. P.C. Board Layout for 100 Kilobaud FSK Modem-Component Side
•
I\)
0)
AN·26
PART NO.
ANSWER
ORIGINATE
PART NO.
ANSWER
ORIGINATE
R1-R2
R3
R4
R5
R6-R7
"R8
R9-R10
R11-R13
R14
R15
R16-R17
R18-R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
RO
RT2
R7A
R7B
R8A
A8B
RT1
5.1K
50KO Pot
2000
510
1000
750
10 KO
1 KO
1.1 KO
4500
16 KO
5 KO
2 KO
4 KO
10 KO
5 KO
249 KO
4 KO
3 KO
10 KO
5 KO
5620
1.3 KO
2.4 KO
1 KO Pot
1.4 KO
1 KO Pot
7500
1 KO Pot
500
5.1K
50KO Pot
2000
510
1000
750
10 KO
1 KO
2280
900
3 KO
5 KO
2 KO
4 KO
10 KO
5 KO
249 KO
4 KO
3 KO
10 KO
5 KO
5620
1.3 KO
7.4 KO
1 KO Pot
5620
1 KO Pot
3.3KO
1 KO Pot
1000
C1
C2
C3
C4
C5-C6
C7
C8
C9
C10
C11
C12-C14
C15
C16
C17
C18
C19
C20
C21
C22-C25
Q1
T1
Z1
IC 1
IC 2
IC 3
IC4
IC 5
"1500
J1-J2
47 ",f
4.7 ",f
.OQ1 ",f
4.7 ",f
.1 ",f
4.7 ",f
1 ",f
738 pf
1800 pf
107 pf
1000 pf
.22 ",f
1 ",f
300 pf
150 pf
106 pf
10 pf
.1 ",f
4.7 ",f
2N2222A
PE-5760""
1N5232
XR-2206
LH0033t
XR-5532
XR-5533
XR-210
47 ",f
4.7 ",f
.001 ",f
4.7 ",f
.1 ",f
4.7 ",f
1 ",f
317 pf
807 pf
46 pf
1000 pf
.22 ",f
1 ",f
300 pf
150 pf
106 pf
10 pf
.1 ",f
4.7 ",f
2N2222A
PE-5760""
1N5232
XR-2206
LH0033t
XR-5532
XR-5533
XR-210
JUMPER
WIRE
JUMPER
WIRE
"Twisted Pair Wire
""Pulse Engineering
tNational
Figure 8. Component List lor 100 Kilobaud FSIC Modem
3-124
·'R:"
~
.
,
:.
"
.
I:'
••
AN·27
r,
IHUglh"ftreqlUJelri1cy TTL CompatDbie Output
ffrcm ~[h1e XfR{,,215 Monolithic Pll Circuit
INTRODUCTION
With digital circuitry as common as it is, it is necessary
to be able to interface analog signals to digital systems.
This can be done by using the XR-215, a monolithic PLL
circuit, and an additional buffer circuit.
approximately 3 volts. The veo output is ac coupled in
order to block this dc level. The input signal causes 01
to be overdriven, where the amplitude is 400 mVpp offselted at approximately 0.769 Vdc. When 01 is in the
offstate, the collector voltage will be forced high and
when this voltage exceeds 0.7 Vdc, 02 will turn on and
the collector of 01 will be clamped at 0.7 Vdc. The output of the veo at the TTL buffered output will be in
phase.
When an input signal is present within the capture
range of the PLL system, the XR-215 will lock on the input signal and the veo section of the PLL will synchronize with the input frequency. The veo output can then
be buffered in order to produce a TTL compatible output.
veo
PHASE
RANGE
COMPARATOR
PRINCIPLES OF OPERATION
+Vcc OUTPUTS
TIMING
SELECT CAPACITOR
Figure 1 shows a functional block diagram of the XR215 monolithic PLL system. The circuit contains a
phase comparator, a voltage controlled oscillator (VeO),
and an operational amplifier. A complete phase locked
loop system can be made by simple ac coupling the
veo output to either of the phase comparator inputs,
and by adding a low pass filter to the phase comparator
outputs.
PHASE
COMPARATOR
INPUTS
12
L-_f-":O ~~~T~~'~
PHASE
COMPARATOR o-"-t--~
BIAS
The veo output can be buffered in order to produce a
TTL compatible output at high frequencies by the simple common emitter circuit shown in Figure 2. The amplitude of veo degrades as frequency increases and at
21 MHz, the amplitude is reduced from approximately
2.5 Vpp to 400 mVpp. The dc output level is 2 volts below Vee so with Vee equal to ± 5 volts, the dc level is
-Vee
OUTPUT
veo sweEP
INPUT
OP AMP
INPUT
OP AMP
OUTPUT
OP AMP
COMPENSATION
Figure 1. Functional Block Diagram of XR·215 Monolithic PLL
Circuil.
+5V~~------~~-------,
11K
TTL BUFFERED
OUTPUT
n
.1 uf
FROM PIN =-15
OF XR-215
~
2K
n
Q1 - Q2=92N2369
Figure 2. Common Emitter Buffer Circuit.
3-125
AN·27
veo OUTPUT (PIN 15)
OF XR-215
TTL BUFFERED OUTPUT
AT 21 MHz MEASURED
WITH X100 PROBE.
PROPAGATION DELAY IS
APPROXIMATELY 5 ns
3-126
AN·27
HIGH FREQUENCY SYNTHESIS
An application where a high frequency TTL compatible
output would be useful is in high frequency synthesis,
as shown in Figure 3. The output of the buffer, which
can produce a high frequency TTL compatible output,
is divided down the divider modulus N. When the entire
system is synchronized to an input signal at frequency
fs, the veo output (pin 15) is at frequency Nfs, where N
is the divider modulus. This is useful because a large
number of discrete frequencies can be synthesized
from a given reference frequency.
CB
II I
+5V
C1
~
C1
20K
INPUT
f = fs
n
o----clCc. . . __. .,
>--+~8
XR·215
..r--+-015 VCO OUTPUT
fo = Nfs
14
RT
Ro
Co
-5V
+5V~~-~~.......,
+5V
5
fo = N
11
SN7493
+
1Kn
14
N
BINARY COUNTER
12
Q1 -
Figure 3. High Frequency Synthesis Circuit.
3·127
Q2 2N2369
AN·28
XR·212AS Modem System
INTRODUCTION
XR-212DA 212A1V.22 Modem Filter: This is a switched capacitor type filter to perform precise filtering and equalization for transmitted and received carrier frequencies
of 1200 Hz and 2400 Hz.
This application note describes a four-chip modem set
designed to perform the complete Bell 212A type modem function. Described are the functions of each device, the connection of the four together, and testing
procedures with performance data.
XR-2121 - PSK/FSK Modulator: Complete modulation
functions are performed by this device for both 300
BPS FSK and 1200 BPS PSK.
PRINCIPLES OF OPERATION
XR-2122 - PSK/FSK Demodulator: Demodulation of FSK or
PSK encoded carriers is performed by the XR-2122.
The basic characteristics of the 212A type modem are
listed In Figure 1. As seen, this type of system is basically a dual modem. It can communicate with either
low speed FSK modems (Bell 100 Series) or at 1200
BPS to PSK modems.
XR-2125 - Data Bufter: Performs asynchronous to synchronous and synchronous to asynchronous conversion.
MAJOR 212A TECHNICAL SPECIFICATIONS
Figure 2 illustrates the major components of most modem systems. The four sections are:
DATA RATES:
Low Speed Mode:
0-300 BPS Asynchronous Format
High Speed Mode:
1200 BPS Character-Asynchronous Format
1200 BPS Synchronous Format
1. Modem Signal Processor (MSP): This is the heart of
the modem. It contains the modulator, demodulator, and filtering functions.
2. Data Coupler: This section in the 212A is a direct access arraignment (DM). This type is directly connected to the switched telephone network. The
DM serves to protect the phone network from
modem and vice versa.
ENCODING FORMATS:
Low Speed Mode:
FSK (Frequency Shift Keying)
High Speed Mode:
PSK (Phase Shift Keying)
3. UART: Performs serial to parallel conversion and
timing functions.
OPERATING MODE:
Full-Duplex at all Speeds
4. Handshaking Controls: Timing functions for signals
such as clear to send (CTS) and request to send
(RTS).
LINE REQUIREMENT:
Two-Wire Switched Network
The XR-212A consists of the following four devices
which perform the complete MSP function.
TERMINAL
OR CPU
I
I
I
I
I
I
I
I
I
I
UART
I
I
Figure 1. Major 212A Technical Specifications
I
I
MODEM
SIGNAL
PROCESSOR
DATA
COUPLER
(DAA)
HANDSHAKING
CONTROLS
(RS-232)
Figure 2. Modem Architecture
3-128
I
I
J
i
I
I
I
TELEPHONE
OR LEASED
LINE
AN·28
COMPLETE SYSTEM
Figure 3 is a simplified complete schematic intended to
illustrate the complexity of the system. Detailed pin
connections were not available at the time of printing
this application note.
A test set-up for bit error rate testing is shown in Figure
4, with testing results as well.
XR·2121
1.6432 MHz
XIN
MODULATOR
XOUT
XR·2125
TXD
TXD 0 - -
SYNC
600Q
TXCAR
TXC ClK OUT
TXC
ASYNC
XR·2120A
:r:
TXD
TXCAR
II( mE~HONE
ClKIN
ClKIN
XR·2122
ClK IN
RXCAR
RXD
SYNC
RXD
NETWORK
":'
RXCAR
RXC
600Q
DATA
BUFFER
FilTER
":'
DEMODULATOR
Figure 3. Complete Modem Signal Processor
TXCAR =-3dBm
RXD
RXD
HP1645A
DATA
ERROR
ANALYZER
Rxe
TXD
BRADLEY
2A/26
LINE
IMPAIRMENT
SIMULATOR
MODEM
UNDER
TEST
XR·212AS
RXe
3002
LINE
SIMULATOR
212A
MODEM
TXD
HP1645A
DATA
ERROR
ANALYZER
TXe
TXe
CONDITIONS: RXCAR = -40 dBM, NOISE LEVEL
(1200 BPS)
RETURN LOSS = - 4 dB, 511 DATA PATIERN
MODE
ANSWER
ANSWER
ORIGINATE
ORIGINATE
·ORIGINATE
=
-52 dBM (SIN
FREQUENCY OFFSET
12 dB), HIGH SPEED MODE
BER
o Hz
<1/10-6
±S Hz
<1110-6
o Hz
<1110-6
±S Hz
±S Hz
<1/10-S
<1/10-6
·With additional equalizer selected on XR-2120A filter.
Figure 4. 212AS Performance Testing
3·129
QUALITY ASSURANCE
Quality Assurance Standards ................................................................... 4-2
Quality Assurance
4·1
Quality Assurance Standards
The quality assurance program at Exar Corporation defines and establishes standards and controls on manufacturing, and audits product quality at critical pOints
during manufacturing. The accompanying Manufacturing/QA process flow charts illustrate where quality
assurance audits the manufacturing process, by inspection or test. The insertion of these quality assurance pOints is designed to insure that the highest quality standards are maintained on Exar products during
manufacturing.
Realizing that these standard manufacturing/QA pro·
cess flows do not meet the needs of every customer requirements, Exar Quality Assurance will negotiate any
additional screening needs, to meet any individual customer's specific requirement.
Wafer Fabrlcatlon/QA Flow
High Reliability Assembly/QA Flow
Polished Siricon
Shces
Masks
Materials
Initialte Seriatlzl!'d lot
Traveler to Mslntaln
Traceability Back
to Wafer Aun Numbe,
-@MQCI'S
Wal,r Saw
Break/Plale Dice
VisuallnSp!!cUon for Conlamination. etc.
""'enilor Temperature
Settings, Plck·up
Tools, Operator Audit,
Exar OCI 2007
Per MII·Std·S83,
Method 2010 D
Latest Revision
eQA
Die/Frame Attach
Die Shear Sampl.
Per Mil-Std·S83,
Method 2010
Latest Revision
Verily Layer Ttlickfll!SS ,nd Resistivity,
Inspect lor Stackl'l9 Faults. etc.
Manlier Bo"d Pulls, ( 2 r - .
Power Senings,
Operalor Audit
Ellar OCI 2006:2008
Sond Pull Semple
WI,. Bond
PerMII-8ld-883,
Method 2010
(Precap Visual Inspection)
=Certlllcallon(2rVisual Inspecllon to Ver.fy Proper Mask,
Check Alignment. Undercutting. Proper
a •• de Removal, etc
Seal S1rf!l1gth. Monitor
pl'r Mil-Std-883.
Selll
~
~
Method 2024
TIn PI ..te Leads
150 Micro Inch Minimum
Lead Trim
Stab.il7.8llon'B,Ike.
Mil-Sld·BU, Method lOO8e.
S E.M Analysis
T.mperatu,.~
Indivjdual Wafer S E.M. AnOlllysis loplional
lor rug" reliability militarv program .. only)
Cuns!...t Acceleration,
"'iI-Std·On. Method 200lE,
Cycle
MiI·Std·S83, Method tOtOe.
YI lXis.
Firte LeAk. ""il·Std·BB3.
Method 1014A or 8.
51(10-·8 ATM cc/sec
Gross Leak, MiI·Std-883.
MfOthod tOHC.
AC, DC and
Funclioroal Testa
10 Dlita Sheet
P,r.-
~_ _
Produclion Eleclrical Test
AC. DC, Functiona' Tests.
~
meten ,01 AOL
~25"C. -55"C, and
+12S"C
or per Indi"idu:1I cullomer
requirements
10 further en'o'ironmenlal _ __
preconditlonil'lg,
acreening. burn· in per
indIVIdual cuslomer
requirements.
Wafer probe 100-. probe AC. DC, and Functlona' Testing
Die Son Yield Analysis (optional, lor
high reliability military progr.ms only)
Monitor Marking Permanency
Per MiI·Std·8B3.
Method 2015
High Reliability
"'...mbly
I
C.rdip
Assembly
,
PI ••tlc "'...mbly
4-2
e
M.,k - Applicable
Marking and Oale COdI!'
OA
-1_
OA
Lol Accf!planc~. verily
product IVpe. count
package, COrTlplelion of all
SHIP
Verify required
documenlalion. aCI3001
c;J
proCI!.' requirement •.
Plastic Assembly Q/A Flow
Cerellp Assembly Q/A Flow
100% Ell' aC12004
Scribe'Orea1tlPlale
e--
Oplicallnspr.clion per
100·,~ eur OCI 2004
E.IIIr QCI 2004
(MiI-Sld·BU. Method 2010
CondItion 0 mlJdlhedl
Vllu.1 Monitor
Temp".!ur.5,ning
Diell,lrI''' Ak1.3ch
Ot12001'2005
Bond Pull M,chlnl
Scribe Break/PI.le
e-e
OpUc.llnspeclio" per
E.. , QCI 2004
(MlI·Sid·883, Melhod 2010
Condlhon B Modllled)
Die Bond
QA
Wi,eOond
CertmClUon
Opllullnlp~cllo"
100-'.E .. ,
~
QCI2007,2008~
'OO·.E •• rOCI~
perEl'lIr OCI::IOO72OC13
2001'2008~
(MII·Std-1J1l Mel"od 21)10
Conctllion B MOdlfledl
-""'....
FurnaCeCeT1l1iCaIJOn@-
MonltorSealStl'llngth
Per MiI·Std-883,
Method 202-4
Optical Inlpectlon per
ElI,OC12007!2ool
IMil·Sld·IIl, ""!hod 20~D
Co"dIIlO" B mOdllL,d)
G-
Tin Plale
Fin! L ..k. 5.10-8
Delll$h,Trlm, Form II'dl
A'rM cclnc
SQlde, Dip
OrossL..... Hubble Tesl
S .. b.liution elke, ISOC.
24h".
1'1'".,
SI.blllnlionB.1te
150C, 24 hta. min.
,00'.
MonltorM"king~
Perm.nel'!cy
~-
PrQr/uctlon TIlling. AC, DC.
,,"d Functional fesIII12S C.
OTI3ooo
AC, DC FunClionl'
Tesl Ol'a StiNt
Mark_Applicable
Ml'lklng and 0.11 Cod.
"'/Irking-Applicable
"""king and Dale Cod.
Pa'II,",I.,
OTI3000
100°.. Production T."
AC. DC Function.1 r .., ~ _
C,I.ShI!'flIP,r.mel.r. ~
.1 AQL
.1 AQL
AC. DC Inti Functlon,l
TIII.I.t2SC
Ship
Lot ACClpll/'IU an 3001
PRODUCT ORDERING INFORMATION
Ship
Part Identification
Definition of Symbols:
XXXXX
XR
Package Type
Grade
M
N
C
Hi-Rei
Prime
Electrical
Prime
Electrical
Commercial
K
Kit
P
M
Basic Type
Manufacturer's Prefix
N
P
MD
Ceramic Dual-in-line
Plastic Dual-in-line
Small Outline
N
P
CN
CP
MD
HI-Rei Grade Part, Ceramic Package Only,
and are guaranteed to operate over the
temperature range of - 55 to + 125·C.
Prime Grade Part, Ceramic Package.
Prime Grade Part, Plastic Package.
Commercial Grade Part, Ceramic Package.
Commercial Grade Part, Plastic Package.
Commercial Grade Part, Plastic Small Outline
Package (Marking does not include MD letters)
N, P. CN and CP parts are electrically identical and
guaranteed to operate over O·C to + 70·C range unless
otherwise stated. In addition, Nand P parts generally
have operating parameters more tightly controlled than
the CN or CP parts.
Example:
For details, consult Exar Sales Headquarters or Salesl
Technical Representatives.
XR-2120 eN
I~ ~
Manufacturer'S
Prefix
Basic
Type
Grade
Legend:
o
Package Type
o
4-3
Operation
Surveillance
o
100% inspection
QC = Quality Control
QA = Quality Assurance
General Information
GENERAL INFORMATION
Package Information and Options .•..•••...........•......•...•........•.......................• 5-2
Monolithic Chips for Hybrid Assemblies ................•..................••.•.................. 5-8
Industry-Wide Product Cross Reference ....•.....•...............•.....•....................•..•. 5-9
Distributors and Representatives ..........................................•......•............. 5-10
Technical Literature Request ......................•......•....•.......................••....... 5-16
5-1
Package Information
(Plastic)
8 PIN MOLDED PLASTIC DIP (JAPAN)
8 PIN MOLDED PLASTIC DIP
[ -W.-l
047A~:::::: tr~'
~
R ·1'
I--m-I
031
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153
031
-.t.
:lJ...
~-~~d
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012
BOB
......
rnl
--J I1..· __
~r;;;~:;;;:;;;;~'
..' I~-;;~ 012
_~~
~_~~
..hl1B
142
100' 012
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r"'I
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047R-..
...Ik. ~
600' 012.--....:.1·
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II li li Uij"IIIij ~~
100' 126
012"
Ole
-
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008
-···700012--
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16 PIN MOLDED PLASTIC DIP
14 PIN MOLDED PLASTIC DIP
1035'012
047R
C
....
098£1
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_--.1
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300' 012
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15;--···
I
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126
,
126' 008
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20 PIN MOLDED PLASTIC DIP
18 PIN MOLDED PLASTIC DIP
5-2
___
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Package Information
(Plastic)
t;;---'10~
~9::::::£l~
"
,
'-7
tr
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..... I t ' , ~~'W{FNlFMm-t
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Monolithic Chips for Hybrid Assemblies
HANDLING PRECAUTIONS AND PACKAGING OPTIONS
The major performance characteristics of Exar products are also available in chip form. All chips are 100%
electrically tested for guaranteed dc parameters at
25 D C, and 100% visually inspected at 30x to 100x
magnification using Exar's standard visual inspection
criteria or MIL-STO-883, Method 2010, depending on
the individual customer requirements. Each chip is protected with an inert glass passivation layer over the
metal interconnections. The chips are packaged in
waffle-pack carriers with an anti-static shield and cushioning strip placed over the active surface to assure
protection during shipment. All chips are produced on
the same well-proven production lines that produce
Exar's standard encapsulated devices. The Quality Assurance testing of dice is provided by normal production testing of packaged devices.
Extreme care must be used in the handling of unencapsulated semiconductor chips or dice, to avoid damage
to the chip surface. Exar offers the following two handling or packaging options for monolithic chips supplied to the customer:
Cavity or Waffle Pack: The dice are placed in individual
compartments of the waffle pack (see figure). The plastic snap clips permit inspection and resealing
Wafer Pack: The entire wafer is sandwiched between
two pieces of mylar and vacuum sealed in a plastic
envelope.
FEATURES
Guaranteed dc Parameters at 25 D C
100% Visual Inspection
Care' in Packaging
100% Stabilization Bake (Wafer Form)
CHIPS IN WAFER FORM
Probed and inked wafers are also available from Exar.
The hybrid microcircuit designer can specify either
scribed or unscribed wafers and receive a fully tested
silicon wafer. Rejected die are clearly marked with an
ink dot for easy identification in wafer form.
ELECTRICAL PARAMETERS
Probing the IC chips in die form limits the electrical
testing to low-level dc parameters at 25 D C. These dc
parameters are characteristic of those parameters contained on the individual device data sheet and are guaranteed to an LTPO of 10%.
The ac parameters, which are similar to those in the
standard Exar device data sheets, have been correlated
to selected dc probe parameters.
Typical Cavity Pack
(Waffle Pack)
5-8
~DUSTRY-WIDE
PRODUCT CROSS REFERENCE
X8
Davlca.
Fairchild
Int.,.11
Motorota
N.tlDnal
Rlythaon
Signalits
SlIIcDn
G.ner.1
Sprague
082
083
084
TL082
TL083
TL084
146
246
346
346-2
LM146
LM246
LM346
LM346-2
LM146
LM246
LM346
494
495
555
L555
556
L556
558
559
567
1310
1468
1488
TL494
TL495
UA555
NE555
MC1455
LM555
RC555
NE555
SG555
UA556
NE556
MC3456
LM556
RC556
NE556
S6556
MC1310
MC1468
MC1488
LM1310
1489
1524
1525A
1527A
1543
UA1489A
MC1489A
LM1489A
LM1524
2001
2002
2003
2004
2011
2012
2013
2014
UA9665
UA9666
UA9667
UA9668
2201
2202
SN72555
NE558
NE559
NE567
LM567
UA1488
MC1310
MC1488
MC1411
MC1412
MC1413
MC1416
ULN2001
SG2001
SG2002
S02003
SG2004
SG2011
SG2012
SG2013
S02014
UA9665
MC1411
ULN2001
SG2001
ULN2001
UA9666
MC1412
ULN2002
S02002
ULN2002
2203
UA9667
MC1413
ULN2003
S62003
ULN2003
2204
UA9668
MC1416
ULN2004
ULN2003
ULN2004
UA2240
ULN2004
ICLB240
ULN2001
SN75466
ULN2002
SN75467
ULN2003
SN75468
ULN2004
SN75469
UA2240
LM2524
SG2524
S02524
S02525A
S02527A
SG2543
8C2567
UA3403
MC3403
3470A
MC3403
RC3403
MC3470A
3503
3524
3525A
3527A
3543
UA3503
4136
4151
4194
4195
UA4136
UA4151
4558
UA4558
4739
4741
UA739
MC3503
RC3503
S03524
LM3524
MC4558
LM348
MC4741
LM1458
RC4558
LM348
8C4739
HA4741-5
RC5532
8C5533
RC5534
6118
6128
MC1458
LM13600
5-9
S01458
RC4558
SN72558
NE5532
NE5533
NE5534
NE5532
NE5533
NE5534
ICLB038
LM13600
MC3503
SG3524
804194
NE594
MC14412
803503
S03524
SG3525A
S03527A
S03543
RC4136
RC4136
RC4151
8C4194
8C4195
5532
5533
5534
13600
14412
ULN2001
ULN2002
ULN2003
ULN2004
ULN2011
ULN2012
ULN2013
ULN2014
RC2207
RC2211
2524
2525A
2527A
2543
2567
8038
SN76115N
MC1488
SN75188
SN75189A
S01524
S61489A
8G1524
SG1525A
SG1527A
SG1543
3403
8C1489A
ULN2110
SG1468
SG1488
MC1489A
801524
2207
2211
2240
Taul
In.trumant.
NE5517
ULN6118
ULN6128
AUTHORIZED REPRESENTATIVES
ALABAMA
FLORIDA
KENTUCKY
Rep. Incorporated
11535 Gilleland Rd.!
P.O. Box 4889
Huntsville, AL 35803/35815
(205) 881-9270
TWX 810-726-2102
Donato & Assoc., Inc.
2758 W. Oakland Park Blvd.
Suite 210
P.O. Box 5848
Ft. Lauderdale, FL 33310
(305) 522-2200
TWX 810-850-0244
(See Ohio)
ALASKA
(Call Exar Direct)
ARIZONA
Summit Sales
7825 E. Redfield Rd.
Scottsdale, AZ 85260
(602) 998-4850
TWX 920-950-1283
ARKANSAS
(See Oklahoma)
Donato & Assoc., Inc.
5401 Kirkman Rd., Ste. 785
Orlando, FL 32819
(305) 352-0727
TWX 810-850-0244
Donato & Assoc., Inc.
535 Hollow Ridge Rd.
P.O. Box 1560
Palm Harbor, FL 33563
(831) 785-3327
CALIFORNIA (North)
GEORGIA
Criterion
3350 Scott Blvd, Blvd. 44
Santa Clara, CA 95051
(408) 988-6300
TWX 910-338-7352
Rep. Incorporated
1944 Cool edge Rd.
Tucker, GA 30084
(404) 938-4358
TWX 810-766-0822
LOUISIANA
(See Texas)
MAINE
(See Massachusetts)
MARYLAND
Component Sales, Inc.
106 Old Court Rd.
Suite 204
Baltimore, MD 21208
(301) 484-3647
TWX 710-862-0852
MASSACHUSETTS
Mass Tech Sales
54 Hartford St., Ste. 102
Westwood, MA 02090
(617) 329-8820
TWX 710-321-9335
MICHIGAN (Detro" Area)
J. L. Montgomery Assoc., Inc.
27200 Lahser Rd.!P.O. Box 244
Southfield, MI 48037
(313) 358-2616
TWX 810-224-4981
CALIFORNIA (South)
HAWAII
Harvey King, Inc.
8124 Miramar Rd.
San Diego, CA 92126
(619) 566-5252
(Call Exar Direct)
(See Washington)
J. L. Montgomery Assoc., Inc.
Landa/Minyard, Inc.
1618 Cotner Ave.
Los Angeles, CA 90025
(213) 879-0770
TWX 910-342-6343
ILLINOIS (North)
2214 Oak Industrial Dr., NE
Grand Rapids, MI 49505
(616) 774-9308
COLORADO
(Call EXAR Direct)
IDAHO
Janus, Inc.
3166 Des Plaines Ave.
Suite 14
Des Plaines, IL 60018
(312) 298-9330
TWX 910-692-4024
ILLINOIS (South)
(See Missouri)
INDIANA
MINNESOTA
Dan'l Engineering
1631 E. 79th Street, Ste. S145
Minneapolis, MN 55420
(612) 854-7550
TLX 291008
(DANL ENG BLTN)
MISSISSIPPI
(See Ohio)
(See Alabama)
CONNECTICUT
Phoenix Sales
386 Main sl.
Ridgefield, .CT 06877
(203) 438-9644
TWX 710-467-0662
(Western Michigan Area)
IOWA
MISSOURI
(Call EXAR Direct)
KKB and Company
1610 S. Big Band Blvd.
St. Louis, MO 63117
(314) 647-2400
TWX 910-761·1040
DELAWARE
(See Maryland)
KANSAS
(See Missouri)
5-10
KKB and Company
104 North 12th
Blue Springs, MO 64015
(816) 229·0001
TWX 910-997-0718
MONTANA
OHIO
UTAH
(See Colorado)
McFadden Sales
1093 Fishinger Rd.
Columbus, OH 43221
(614) 459-1280
TWX 810-482-1623
(Cali EXAR Direct)
NEBRASKA
(See Missouri)
NEVADA
(See California No.)
NEW HAMPSHIRE
(See Massachusetts)
NEW JERSEY (North)
(See New York City)
NEW JERSEY (South)
Vantage Sales Co.
6981 North Park Dr., Ste. 110
Pennsauken, NJ 08109
(609) 663-6660
OKLAHOMA
VERMONT
(See Texas)
(See Massachusetts)
OREGON
Components West, Inc.
15255 S.w. 72nd Ave., Ste. A
Tigard, OR 97223
(503) 684-1671
TWX 910-467-8740
PENNSYLVANIA (West)
(See Ohio)
PENNSYLVANIA (East)
NEW MEXICO
(See New Jersey So.)
Syn Tech
8016 A Zuni Rd., SE
Albuquerque, NM 87108
(505) 266-7951
(See Massachusetts)
RHODE ISLAND
SOUTH CAROLINA
NEW YORK (Upstate)
(See North Carolina)
Quality Components
3343 Harlem Rd.
Buffalo, NY 14225
(716) 837-5430
TWX 910-997-1313
(See Minnesota)
Quality Components
116 E. Fayette SI.
Manlius, NY 13104
(315) 682-8885
NEW YORK (City)
Trionic Assoc., Inc.
320 Northern Blvd.
Great Neck, NY 11021
(516) 466-2300
TWX 510-223-0834
NORTH CAROLINA
Zucker Assoc., Inc.
P.O. Box 19868
Raleigh, NC 27619
(919) 782-8433
TWX 510-928-0513
NORTH DAKOTA
(See Minnesota)
SOUTH DAKOTA
TENNESSEE (West)
Rep. Incorporated
113 S. Branner Ave.
Jefferson City, TN 37760
(615) 475-4105
TWX 810-570-4203
TENNESSEE (East)
(See North Carolina)
TEXAS
Technical Marketing
9027 Northgate Blvd., Ste. 140
Austin, TX 78758
(512) 835-0064
Technical Marketing
3320 Wiley Post Rd.
Carrollton, TX 75006
(214) 387-3601
TWX 910-860-5158
Technical Marketing
2901 Wilcrest Drive, Ste. 139
Houston, TX 77042
(713) 783-4497
5-11
VIRGINIA
(See Maryland)
WASHINGTON
Components West
8275 166th NE
Redmond, WA 98052
(206) 885-5880
WASHINGTON, D.C.
(See Maryland)
WEST VIRGINIA
(See Ohio)
WISCONSIN (South East)
Janus, Inc.
11430 Bluemound Rd.
Milwaukee, WI 53026
(414) 476-9104
WISCONSIN (West)
(See Minnesota)
WYOMING
(See Colorado)
CANADA
Clark-Hurman Associates
148 Colonnade Rd., Ste. 205
Nepean, Ontario K2E 7J5
(613) 727-5626, 727-5627
AUTHORIZED DISTRIBUTORS
ALABAMA
Marshall Electronics
3313 Office Center, Ste. 106
Huntsville, AL 35801
205881-9235
Bell Industries
1161 N. Fair Oaks Avenue
Sunnyvale, CA 94086
408 734-8570
TWX: 910-339-9378
Pioneer
1207 Putnam Drive
Huntsville, AL 35805
205 837-9300
Bell Industries
7450 Ronson Road
San Diego, CA 92111
619268-1277
Resisticap
11547-B So. Memorial Parkway
Huntsville, AL 35815-0889
205 883-4270
Diplomat
20151 Bahama Street
Chatsworth, CA 91311
213341-4411
RM Electronics
4702 Governors Drive
Huntsville, AL 35805
205 852-1550
Diplomat
7140 McCormick
Costa Mesa, CA 92626
714549-8401
ARIZONA
Diplomat
9787 Aero Drive. Ste. E
San Diego, CA 92123
619-292-5693
A.C.T.
4016 Youngfield Street
Wheat ridge, CO 80033
303 422-9229
Diplomat
1283 "F" Mtn. View/Alviso Rd.
Sunnyvale, CA 94086
408734-1900
TWX: 910-379-0006
Bell Industries
8155 West 48th Avenue
Wheatridge, CO 80033
303 424-1985
TWX: 910-938-0393
IEC/JACO
20600 Plummer Road
Chatsworth, CA 91311
213998-2200
TWX: 910-494-1923
Diplomat Electronics
96 Inverness Drive, East
Suite R
Englewood, CO 80112
303 740-8300
IEC/JACO
17062 Murphy
Irvine, CA 92714
714660-1055
Marshall Electronics
7000 North Broadway
Denver, CO 80221
303427-1818
Marshall Electronics
8015 Deering Avenue
Canoga Park, CA 91304
818999-5001
CONNECTICUT
Bell Industries
1705 W. 4th Street
Tempe, AZ 85281
602966-7800
TWX: 910-950-0133
Marshall Electronics
835 West 22nd Street
Tempe, AZ 85282
602968-6181
Sterling Electric
3501 E. Broadway Road
Phoenix, AZ 85040
602268-2121
TLX: 667317 "STERLING PHX"
Western Micro
7740 East Redfield Drive
Scottsdale, AZ 85260
602 948-4240
ARKANSAS
Carlton-Bates
3600 West 69th Street
Little Rock, AR 72219
501 562-9100
CALIFORNIA
A.v.E.D
1582 Parkway Loop, Unit G
Tustin, CA 92680
213770-0871
Bell Industries
1-830 Vernon St., Bldg. 1
Roseville, CA 95678
916969-3100
Marshall Electronics
9674 Telstar Avenue
EI Monte, CA 91731-3004
818 442-7204
Marshall Electronics
17321 Murphy Avenue
Irvine, CA 92714
714556-6400
5-12
Marshall Electronics
10105 Carroll Canyon Road
San Diego, CA 92131
619478-9600
Marshall Electronics
788 Palomar Avenue
Sunnyvale, CA 94086
408 732-1100
Western Microtechnology
10040 Bubb Road
Cupertino, CA 95104
408 725-1664
Zeus Components, Inc.
1130 Hawk Circle
Anaheim, CA 92807
714632-6880
COLORADO
Diplomat Electronics
52 Federal Road
Danbury, CT 06810
203 797-9674
J. V. Electronics
690 Main Street
East Haven, CT 06512
203469-2321
Marshall Electronics
Barnes Industrial Park
33 Village Lane
P.O. Box 200
Wallingford, CT 06492
203 265-3822
DELAWARE
IDAHO
IOWA
(See Washington)
Bell Industries
1221 Park Place, N.E.
Cedar Rapids, IA 52412
319395-0730
ILLINOIS
Diplomat Electronics
1071 Judson Street
Bensenville, IL 60160
312595-1000
(See Pennsylvania)
FLORIDA
Diplomat Electronics
2120 Calumet Street
Clearwater, FL 33515
813443-4514
Diplomat Electronics
1300 N.W. 65th Place
Fort Lauderdale, FL 33309
305974-8700
Future Electronics
2073 Range Road
Clearwater, FL 33575
813596-8295
Hammond Electronics
6600 N.W. 21st Avenue
Fort Lauderdale, FL 33309
305'973-7103
Hammond Electronics
1230 W. Central Blvd.
Orlando, FL 32805
305 849-6060
GBL·Gould
610 Bonnie Lane
Elk Grove Village, IL 60007
312490·0155
Marshall Electronics
1261 Wiley Road, Unit F
Schaumburg, IL 60195
312 490·0155
Intercomp
2200 Stongton Ave., Ste. 210
Hoffman Estates, IL 60695
312843-2040
Reptron
721 W. Algonquin Road
Arlington Heights, IL 60005
312593-7070
RM Electronics
265 Eisenhower Lane, South
Lombard, IL 60148
312935-5150
TWX: 910-651-3245
INDIANA
Marshall Electronics
1101 N.w. 62nd Street
Suite 3060
Fort Lauderdale, FL 33309
305928-0661
Altex
12774 N. Meridian
Carmel, IN 46032
317 848-1323
TWX: 810-341-2635
Marshall Electronics
4205 34th Street, S.w.
Orlando, FL 32811
305841-1878
Graham Electronics
133 S. Pennsylvania Street
Indianapolis, IN 46204
317634-8202
TWX: 810-341-3481
GEORGIA
Diplomat Electronics
6659 Peachtree, Suite B
Norcross, GA 30092
404 449-4133
Graham Electronics
3606 E. Maunee Avenue
Ft. Wayne, IN 46803
219423-3422
Marshall Electronics
4350 J International Blvd.
Norcross, GA 30093
404 923-5750
RM Electronics
7031 Corporate Circle
Indianapolis, IN 46278
317 291-7110
Pan American
889 Buford Road
Comming, GA 30130
404 577-2144
Deeco Inc.
2600 16th Avenue, S.w.
Cedar Rapids, IA 52406
319365-7551
TWX: 910-525-1332
KANSAS
(See Missouri)
KENTUCKY
(See Indiana)
LOUISIANA
(See Texas)
MAINE
(See Massachusetts)
MARYLAND
Diplomat Electronics
9150 Rumsey Rd., Ste. A-6
Columbia, MD
301 995-1226
Marshall Electronics
8445 Helgerman Court
Gaithersburg, MD 20877
301 840-9450
Pioneer
9100 Gaither Road
Gaithersburg, MD 20760
301 948-0710
TWX: 710-828-0545
MASSACHUSETTS
Alma Electronics
60 Shawmut Avenue
Canton, MA 02021
617 329-8810
Diplomat Electronics
28 Comming Park
Woburn, MA 01801
617 935-6611
Gerber
128 Carnegie Row
Norwood, MA 02062
617 329-2400
TWX: 710-336-1987
Marshall Electronics
One Wilshire Road
Burlington, MA 01803
617272-8200
5-13
Marshall Electronics
Corp. Support Ctr.lEast
Five Wilshire Road
Burlington, MA 01803
617 272-8200
RC Components
222 Andover Street
Wilmington, MA 01887
617657-4310
TWX: 710-347-1743
MICHIGAN
Ambur Electronics
1344 So. Commerce
Walled Lake, MI 48088
3i3669-3710
Marshall Electronics
13760 Merriman Road
Livonia, MI 48150
313 525-5850
NEVADA
(See California)
NEW HAMPSHIRE
Marshall Electronics
275 Oser Avenue
Hauppauge, LI, NY 11788
516273-2424
(See Massachusetts)
NEW JERSEY
Diplomat Electronics
490 S. River View Drive
Totowa, NJ 07512
201 785-1830
GCI
Route 73
Berlin, NJ 08009
609 768-6767
Marshall Electronics
101 Fairfield Road
Fairfield, NJ 07006
201 882-0320
Marshall Electronics
1280 Scottsville Road
Rochester, NY 14624
716235-7620
SAL
564 Smith Street
Farmingdale, NY 11735
516293-2710
Zeus Components Inc.
100 Midland Avenue
Portchester, NY 10573
914937-7400
TWX: 710-567-1248
NORTH CAROLINA
RM Electronics
4310 Roger B. Chaffee
Memorial Drive
Grand Rapids, MI 49508
616531-9300
TWX: 810-273-8779
Marshall Electronics
102 Gaither Drive
Mt. Laurel, NJ 08054
609234-9100 (NJ)
215627-1920 (PA)
Hammond
2923 Pacific Avenue
Greensboro, NC 27406
919 275-6391
NEW MEXICO
(Call EXAR Direct)
Reptrori Electronics
34404 Glendale Road
Livonia, MI 48150
313525-2700
Bell Industries
11728 Linn N.E.
Albuquerque, NM 87123
505 292-2700
TWX: 910-989-0625
MINNESOTA
Marshall Electronics
13810 24th Avenue, N.S. No_ 460
Plymouth, MN 55441
612559-2211
NORTH DAKOTA
Betatron
2825 B. Broadbent Pkwy, NE
Albuquerque, NM 87123
505344-2381
NEW YORK
Merit Electronics
2525 Nevada Avenue
Warehouse Suite 210
Minneapolis, MN 55427
612 546-5383
MISSISSIPPI
(See Alabama)
Diplomat Electronics
4610 Wetzel Road
Liverpool, NY 13088
315 652-5000
Diplomat Electronics
110 Marcus Drive
Melville, NY 11747
516454-6400
MISSOURI
Olive Electronics
9910 Page Blvd.
SI. Louis, MO 63132
314426-4500
TWX: 910-763-0720
JACO
145 Oser Avenue
Hauppauge, NY 11787
516273-5500
TWX: 510-227-6232
MONTANA
Marshall Electronics
10 Hooper Road
Endwell, NY 13760
607754-1570
(Call EXAR Direct)
NEBRASKA
(See Missouri)
5-14
OHIO
Graham
239 Northland Blvd.
Cincinnati, OH 45246
513772-1661
TWX: 810-461-2896
Marshall Electronics
6212 Executive Blvd.
Dayton, OH 45424
513 236-8088
Marshall Electronics
5905B Harper Road
Salon, OH 44139
216248-1788
Reptron Electronics
830 Busch Court
Columbus, OH 43229
614436-6675
OKLAHOMA
Quality Components
9934 E. 21 st Street, S.
Tulsa, OK 94128
918664-8812
Radio, Inc.
1000 S. Main Street
Tulsa, OK 74119
918587-9123
OREGON
Bell Industries
6024 SW. Jean Road
Lake Oswego, OR 97034
503 241-4115
TWX: 910-455-8177
Marshall Electronics
8230 S.w. Nimbus Avenue
Beaverton, OR 97005
503 644-5050
Radar Electric Co., Inc.
704 S.E. Washington
Portland, OR 97214
503 232-3404
TWX: 910-464-2386
Western Microtechnology
13770 S.w. 24th Street
Beaverton, OR 97005
503641-9312
PENNSYLVANIA
Advacom
5620 West Road
McKean, PA 16426
814476-7774
Almo Electronics
9815 G. Roosevelt Blvd.
Philadelphia, PA 19114
215698-4000
Pioneer
261 Gilbralter Road
Horsham, PA 19044
215674-4000
TWX: 510-665-6778
RHODE ISLAND
(See Massachusetts)
SOUTH CAROLINA
Hammond Electronics
1035 Lowndes Hill Road
Greenville, SC 29607
803 233-4121
International Electronics
10937 Pellicano Drive
EI Paso, TX 79935
915 598-3406
IEC/JACO
1750 124th Avenue, Ste. J
Bellevue, WA 98005
206 455-2727
Marshall Electronics
8705 Shoal Creek Blvd.
Suite 202
Austin, TX 78758
512 458-5654
Marshall Electronics
14102 N.E. 21st Street
Bellevue, WA 98007
206747-9100
Marshall Electronics
14205 Proton Road
Dallas, TX 75234
214233-5200
Marshall Electronics
3698 Westchase Drive
Houston, TX 77042
713789-6600
Quality Components
4257 Kellway Circle
Addison, TX 75001
214387-4949
TWX: 910-860-5459
Quality Components
2427 Rutland
Austin, TX 78758
512835-0220
Quality Components
1005 Industrial Blvd.
Sugarland, TX 77478
713491-2255
TWX: 910-880-4893
Diplomat
3007 S.w. Temple
Salt Lake City, UT 84115
801 486-4134
VERMONT
(See Massachusetts)
TENNESSEE
(See Alabama)
VIRGINIA
(See Maryland)
TEXAS
ERA
1147-B Larry Mahan
EI Paso, TX 79925
915 592-4126
Western Microtechnology
14778 N.E. 95th Avenue
Redmond, WA 98052
206881-6737
WISCONSIN
Bell Industries
W 227 N 913 W. Mound Ave.
Waukesha, WI 53186
414547-8879
RM Electronics
2626 S. 162nd Street
Berlin, WI 53151
414 784-4420
Taylor Electric Co.
1000 W. Donges Bay Road
Mequon, WI 53092
414 241-4321
TWX: 910-262-3414
WYOMING
UTAH
Bell Industries
3639 W_ 2150 So.
Salt Lake City, UT 84120
801 972-6969
TWX: 910-925-5686
SOUTH DAKOTA
(Call EXAR Direct)
Radar Electronic Co., Inc.
168 Western Avenue, W.
Seattle, WA 98119
206 282-2511
TWX: 910-444-2052
WASHINGTON
Bell Industries
1900 132nd Avenue. N.E_
Bellevue, WA 98005
206747-1515
5-15
(See Colorado)
CANADA
Cam Guard Supply ltd.
1777 Ellice Avenue
Winnipeg, Manitobo R3H OW5
504 786-8401
Cam Guard Supply ltd.
2055 Boundary Road
Vancouver, British Columbia V5M 3L2
604291-1441
Cam Guard Supply ltd.
162 - 36 116th Avenue
Edmonton, Alberta T5M 3V4
403 453-6693
Cam Guard Supply ltd.
1501 Ontario Avenue
Sashatoon, Saskatchawan S7K 187
Cam Guard Supply Ltd.
500 Norfinch Drive
Downsview, Ontario M34 1V4
416736-1744
Future Electronics
237 Humus Blvd.
PI. Claire, Montreal,
Quebec H9R 5C7
514694-7710
Intek Electronics Ltd.
10-8385 SI. George Street
Vancouver, British Columbia V5X 4P3
604324-6831
TWX: 610-922-5032
Intek Electronics Ltd.lAlberta
4616 99th Street
Edmonton, Alberta T6E 5H5
403 437-2755
RAE Industrial Electronics
3455 Gardner Court
Burnaby, British Columbia V5G 4J7
604 291-8866
TWX: 610-929-3065
5-16
INTERNATIONAL SALES OFFICES AND REPRESENTATIVES
ARGENTINA
GREECE
LATIN AMERICA
Rayo Electronics SRL
Belgrando 990, Pisos 6Y2
Buenos Aires
Phone: 37 98 90
Telex: (390) 122153 (RAYOX AR)
General Electronics Ltd.
209 Thivon Street
Nikea, Piraeus 7
VGNUJVUY
Phone: 49·13595
Telex: (863) 212949 (GELT GR)
Intectra
2629 Terminal Blvd.
Mtn. View, CA 94043 (USA)
Phone: (415) 967·8818
Telex: 3445 545 (INTECTRA MNTV)
AUSTRALIA
Total Electronics
9 Harker Street
P.M.B. No. 250
Burwood, 3125 Australia
Phone: 288 4044
Telex: (790) 31261 (TOTELEC AA)
HONG KONG
(See Switzerland)
ROHM Electronics (H.K.) Co., Ltd.
Flat 13, 3/F Newport Centre
116, Mataukok Road, Tokwawan
Kowloon
Phone: 3·343481
Telex: (780) 37503 (REHCL HX)
BELGIUM
(See Germany)
BRAZIL
Intectra Do Brazil
AV Paulista 807·S/415
Sao Paulo, Brazil
Phone: 285·6305
Telex: 01139872 (BRCO BR)
ROHM Do Brazil Industria
Electronica Ltda.
AI. Reo Negro, 1356· Alphaville
Cep 06400 . Barueri, Sp.
Phone: (011) 421·4577
Telex: (391) 1135275 (UIEL BR)
DENMARK
Mer·el AJS
Ved Klaedebo 18
DK·2970 Horsholm
Phone: 571000
Telex: (855) 37360 (MEREL DK)
INDIA
Zenith Electronics
106, Mittal Chambers
Nariman Point, Bombay 400021
Phone: 2024464
2027887
Telex: (953) 113152 (ZNTH IN)
Fegu
2584 Wyandotte Street
Mountain View, CA 94043 (USA)
Phone: (415) 961·2380
Telex: 345·599 FEGU ELEC PLA
ISRAEL
MLRN Electronics
15 Kineret S1. Bney·Brak
P.O. Box 10205 Tel·Aviv
Israel 61101
Phone: 03 796 927 or
03807 174·5
Telex: 342107 RNIS
FINLAND
ITALY
Yleiselektroniikka/oy
Luomannotko 6
02200 Espoo 20
Phone: 90·452·1255
Telex: 123212 (YLEOYF)
Eledra 33 S.P.A.
Viale Elvezia, 18
20154 Milano
Phone: 34.93.041
Telex: (843) 332332 (ELEDRA I)
FRANCE
JAPAN
Tekelec/Airtronic
Rue Carle Vernet No.2
Cite des Bruyeres
F·92310 Sevres
Phone: (1) 534 75 35
Telex: (842) 204552 (TKLEC A)
Tokyo Electron Ltd.
Panetron Division
38 FL Shinjuku Nomura Blvd.
1·26·2, Nishi·Shinjuku
Shinjuku·ku, Tokyo 160
Phone: 03·343·4411
Telex: (781) 2322240 (LABTEL J)
GERMANY (WEST)
ROHM Electronics GmbH
D·4051 Korschenbroich
Muehlenstrasse 70
Phone: (02161) 61010
Telex: (841) 852330 (ROHM D)
FAX: 02161·642102
0
LIECHTENSTEIN
KOREA
Spirox Holding, Inc.
3537 Ryder Street
Santa Clara, CA 95051 (USA)
Phone: (408) 739·3334
Telex: 346369 (SUVL)
5·17
LUXEMBOURG
(See Germany)
NETHERLANDS
Nijerk Elektronika B.V.
Drentestraat 71083 HK
Amsterdam, Holland
Phone: 020 462221
Telex: 11625 NESCO NL
NEW ZEALAND
Professional Electronics Ltd.
P.O. Box 31143
22A Milford Road
Milford, Auckland 9
Phone: 46 94 50
Telex: (791) 21084 (PROTON)
NORWAY
Hefro Teknisk AJS
P.O. Box 6596
Rodezokken 80, Trondheimsuir
Oslo 5
Phone: 38 02 86
Telex: (856) 76205 (HEFRO N)
SINGAPORE
ROHM Electronics Co. Pte., Ltd.
Unit A, 3rd Floor
No. 12 Arumug AM Road No. 04.01
Singapore 1440
Phone: 745 9342
Telex: (786) 26648 (ROHMS)
SOUTH AFRICA
South Continental Devices (Pty.) Ltd.
Suite 516, 5th Floor, Randover House
Cor Hendrik Verwoerd, Dover Road
Randburg, Transvaal
Phone: 48 05 15
Telex: (960) H'4849 (SA)
SPAIN
Unitronics, SA
Princesa, 1
Madrid 8
Phone: 242 52·04
Telex: (831) 46786 (UTRON E)
SWEDEN
Lagercrantz Electronix AB
Kanalvagen 5
S-19401 Upplands Vasby
Phone: (0760) 86 120
Telex: (854) 11275 (LAGER S)
SWITZERLAND
Stolz AG
Taefernstr .15
CH-5405
Baden-Daeltwill, Switzerland
Phone: (05) 6480151
Telex: 54070 (STLZ CH)
TAIWAN
Sea Union
P.O. Box 45-95 TAl PEl
Room 303, Hua-Nan Blvd.
No. 162, Chang An East Rd.,
2nd Section
Taipei, Taiwan, Rep. of China
Phone: 751-2063 or 751-6856
Telex: 24209 (SEAUNION TAIPEI)
TURKEY
Testas
Karanfil Sakak No. 41
Bankanliklar, Ankara
UNITED KINGDOM
Thame Components
Thame Park Road
Thame, Oxon OX9 3RS
Phone: (084421) 3146
Telex: (851) 837917 (MEMEC G)
ALL OTHER· COUNTRIES
(Call EXAR Direct)
5-18
Technical Literature
APPLICATION DATA BOOK:
PHASE-LOCKED LOOP DATA BOOK:
This practical applications guide contains a complete
and up-to-date set of application notes prepared by
Exar's technical staff. These application notes cover a
wide range of subjects, such as FSK MODEMS, active
filters, telecommunication circuits, electronic music
synthesis and many more. In each case, specific design examples are given to demonstrate the applica·
tions discussed.
The fundamentals of design and application of monolithic phase-locked loop (PLL) circuits are included in
this data book. A long list of PLL applications are illustrated covering FM demodulation, frequency synthesis,
FSK, and tone detection. Particular emphasis is given
to the application of PLL circuits in data interface and
communication systems such as FSK MODEMS. This
book also contains the data sheets and electrical specifications for all of Exar's PLL products.
FUNCTION GENERATOR DATA BOOK:
PRODUCT GUIDE:
This comprehensive data book contains a number of
technical articles and application notes on monolithic
voltage·controlled oscillators (VeO), and function generator IC products. In addition, the data sheets and
technical specifications for Exar's monolithic veo's
and function generators are included.
A complete short-form catalogue of all of Exar's standard and custom products, quality assurance programs
and technical capabilities. Key features and applications of each of Exar's products are given, along with
their functional block diagrams, package types and operating temperature ranges. Products are grouped according to their applications, and a complete industrywide cross reference chart is provided.
MODEM DESIGN HANDBOOK:
This publication includes all Exar Data Sheets and Application Notes relating to Modem products as well as
section on modem fundamentals. Subjects covered in
this fundamentals section include: Modulation and Demodulation techniques for both FSK and PSK systems,
filter considerations, line interface, and test modes. The
scope of this manual allows even the beginning modem
designer to implement Exar's available integrated circuits into complete working modems.
SWITCHING REGULATOR DATA BOOK:
Exar's entire line of switching regulator Ie products are
specified in this technical data book. In addition, several design and application articles are included, along
with a review of the fundamentals of pulse-width modulated regulator circuits.
OPERATIDNAL AMPLIFIER DATA BOOK:
TIMER DATA BOOK:
A collection of technical articles on the fundamentals of
monolithic Ie op amps is contained in this technical
publication. Some of the basic op amp circuits are
given, and the application of IC op amps in active filter
design is discussed. A complete set of electrical specifications on Exar's bipolar and bipolar JFET op amp
products is included.
Provided in this publication is a collection of technical
articles and application information on monolithic timer
Ie products. Also included are the data sheets and detailed electrical specifications for all of Exar's timer circuits, including the programmable timer/counter, micropower, and long-delay timers.
TECHNICAL LITERATURE REQUEST:
To obtain the technical literature of interest to you, contact the Exar Sales representative nearest you, or write Exar Corporation, P.O. Box
3575, Sunnyvale, CA 94088-3575, on your company letterhead.
Data Books can also be ordered directly from Exar, at a nominal charge, by completing and sending this request card to Exar with an
appropriate check or money order {include $2.00 for postage and handling}. Please make checks payable to Exar Corporation.
PLEASE SEND:
0
Complete Set of Data Books: $15.95
o Exar Applications Data Book: $3.95
o Exar Function Generator Data Book: $3.95
o Exar Modem Design Handbook: $4.95
o Exar Operational Amplifier Data Book: $3.95
0
0
0
0
0
Exar Phase-Locked Loop Data Book: $3.95
Exar Product Guide - No Charge
Exar Semi·Custom Product Guide - No Charge
Exar Switching Regulator Data Book: $3.95
Exar Timer Data Book: $3.95
NAME ___________________________________________ TITLE ___________________________
COMPANY~GENCY
__________________________________________________________________
ADDRESS _______________________________________________________________________
CITY/STATE/ZIP _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
PHONE {_ _} __________~___________ MY COMPANY MANUFACTURES ______________________
5-19
-- NOTES--
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