1985_Intel_Microcontroller_Handbook 1985 Intel Microcontroller Handbook

User Manual: 1985_Intel_Microcontroller_Handbook

Open the PDF directly: View PDF .
Page Count: 860

Download
Open PDF In Browser	View PDF

MICROCONTROLLER
HANDBOOK

1985

About Our Cover:"
The design on our front cover is an abstract portrayal of the basic microcontrol/er function.
The center sphere, symbolic of a microcontroller, contains a molecular orbital diagram of the
architectural construction of a cubic unit of silicon. The red pathways lead!ng from the central
sphere, are symbolic of distant or remote controlled applications.

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in
this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications CIt any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel Products:

'f.

BITBUS, COMMputer, CREDIT, Data Pipeline, GENIUS, i,
ICE, iCS, iDBP,
iDIS, 12 1CE, iLBX, im , iMMX, Insite, Intel, intel, inIeIBOS, Intelevision, inteligent
Identifier, inleligent Programming, Intellec, Intellink, iOSP, iPDS, iSBC, iSBX,
iSDM, iSXM, Library Manager, MCS, Megachassis, MICROMAINFRAME, MULTlBUS, MULTICHANNEL, MULTIMODULE, Plug-A-Bubble, PROMPT,
Promware, QUEST, QUEX, Ripplemode, RMX/80, RUPI, Seamless, SOLO,
SYSTEM 2000, and UPI, and the combination of ICE, iCS, iRMX, iSBC, MCS, or
UPI and a numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data
Sciences Corporation .
• MULTIBUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
.Intel Corporation
literature Department
3065 Bowers Av.enue
Santa Clara, CA ~5()51

@INTEL CORPORATION 1984

Table of Contents
ALPHANUMERIC INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
MCS®-96 FAMILY
CHAPTER 1
Introduction To MCSII!>-96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . '" . 1-1
CHAPTER 2
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
CHAPTER 3
MCSII!>-96 Software Design Information .... " . . . . . . . . . . . . . . . . . . . . . . . . ; . . . . . . . 3-1
CHAPTER 4
MCSII!>-96 Hardware Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
CHAPTER 5
MCSII!>-96 Data Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
CHAPTER 6
MCS®-96 Article Reprint
AR-321: High Performance Event Interface For A Microcomputer . . . . . . . . . . . . . . . . . . . .6-1
MCS®-S1 FAMILY
CHAPTER 7
MCS®-51 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . .7-1
CHAPTER 8
.
MCSII!>-51 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . .S-1
CHAPTER 9
MCS®-51 Data Sheets
S031/S051 S031AH/S051AH S032AH/S052AH S751 H/S751 H-12 . . . . . . . . . . . . . . . . . . . . . 9·1
S052AH-Basic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
SOC51BH/SOC51BH-2 SOC31 BH/SOC31 BH-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
S031 AH/S051 AH S032AH/S052AH S751 H/S751 H Express. . . . . . . . . . . . . .;. . . . . . . . . • ·9-39
CHAPTER 10
'
MCS®-51 Application Notes
AP-69: An Introduction To The Intel MCS®·51
Single-Chip Microcomputer Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
AP-70: Using The Intel MCS®-51 Boolean
Processing Capabilities . . . . . . . . . . . . . . . . . : . . . . . . . . . . ' ..... .' . . . . . . ; ... 10;3~
AP-223: S051 Based CRTlTerminal Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-65
CHAPTER 11
.
MCS®-51 Article Reprint·
AR-224: Controller Chip Takes On Many
Industrial, Computer Uses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
MCS®-48 FAMILY
CHAPTER 12
MCS®-4S Single Component System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .'12-1
CHAPTER 13
MCSII!>-4S Expanded System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13·1
CHAPTER 14
MCS®-4S Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 14·1
CHAPTER 15
MCS®-48 Data Sheets
S243 . . . . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15·1
S048AH/S035AHUS049AH/S039AHUS050AH/S040AHL . . . . . . . . . . . . . . . . . . . . . . . . . 15·7
S748H/S035H/S749H/S039H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15·17
MCS®·48 Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15·30
SOC39·9/S0C49-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-34

THE RUPI'M FAMILY: MICROCONTROLLER
WITH ON-CHIP COMMUNICATION CONTROLLER
CHAPTER 16
The RUPI'"·44 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16·1
CHAPTER 17
8044 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17·1
CHAPTER 18
8044 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-.18·1
CHAPTER 19
8044 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
CHAPTER 20
RUPI'" Data Sheets
8044AH/8344AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
8744 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20
CHAPTER 21
RUPI'· Article Reprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .'21-1

DESIGN CONSIDERATIONS
CHAPTER 22
Application Notes
AP-125: Designing Microcontroller Systems
For Electrically Noisy Environments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
AP-155: Oscillators For Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23

DESIGN CONSIDERATIONS
WHEN USING CHMOS
CHAPTER 23 . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
Article Reprints
AR-302. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . 23-6
AR-332 . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-17

ADVANCED PACKAGING INFORMATION
CHAPTER 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. '.' . . . . . . . . . . . . . . . 24-1

ALPHANUMERICAL INDEX
8031 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9·1
8031AH Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9·1
8031AH Express Data Sheet . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . . . . . . . . . 9·39
8032AH Data Sheet .' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9·1
8032AH Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9·39
8035H Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15·7
8035AHL Data Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..'. 15·7
8039H Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15·7
8039AHL Data Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15·7
8040AHL Data Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15·7
8044 Application Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19·1
8044 Architecture................................................. '. . 17·1
8044 Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . 18·1
8044AH Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20·1
8048AH Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15·7
8049AH Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15·7
8050AH Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . 15·7
8051 Data Sheet . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ' . . . . . . ; ..... 9·1
8051AH . Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : ..... , .... , .. 9·1
8051AH Express Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9~39
8052AH Data Sheet .... ' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '... 9·1
8052AH Basic Data Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9·15
8052AH Express Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9·39
8243 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15·1
8344AH Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
8744 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20·20
8748H Data Sheet . . . . . . . ' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15·17
8749H Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
8751 H Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
8751 H Express Data Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9·39
8751H·12 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9·1
80C31BH Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
80C31BH-2 Data Sheet . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,9·24
8OC39·9 Data Sheet. . . . . . . . . . . . . . . . '.' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15·34
80C51 BH Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9·24
80C51 BH·2 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9·24
ADVANCED Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1

iii

ALPHANUMERICAL INDEX
Design Considerations Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-2, 22-24
Design Considerations When Using CHMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
Design Considerations When Using CHMOS Article Reprints . . . . . . . . . . . . . . . . . . . . . ' .23-6, 23'17
MCS-48 Data Sheets. . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . 15-1,15-7,15-17,15,-30,15-34
MCS-48 Expanded System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
MCS-48 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14·1
MCS-48 Single Component System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
MCS-51 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1,10-31,10-65
MCS-51 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7"1
MCS-51 Article Reprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11 ~ 1
MCS-51 Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1, 9-15, 9-24, 9-39
MCS-51 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
MCS-96 ArchitecturalOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; ... 2-1
MCS-96 Article Reprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6·1
MCS'96 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
MCS-96 Hardware Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
MCS-96 Introduction................................................ ..1-1
MSC-96 Software Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
RUPI Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . ' ... 20-1,20·20
RUPI Article Reprints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
RUPI-44 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ·.... 16-1

Introduction to MCS®,96

CHAPTER 1
INTRODUCTION TO MCS®·96
1.0 CONTINUING MICROCONTROLLER
EVOLUTION
Beginning with the introduction of the world standard
8048 (MCS®-48) Microcontroller in 1976, Intel has continued to drive the evolution of single chip microcontrolleTS. In 1980, Intel introduced the 8051 (MeS-51) offering
performance levels significantly higher than the' 8048.
With the advent of the 8051, the microcontroller applications base took a marked vertical leap. These versatile
chips are used in applications· from keyboards and terminals to controlling automobile engines. The 8051
quickly gained the position of the second generatiOIi world
standard microcontroller.

being pushed to new limits, it has become possible to
integrate more than 100,000 transistors onto a single silIcon chip. Microcontroller designers at Intel have taken
today's process technology achievements and forged a
new genention of single chip microcontrollers called the
MCS-96. The 8096 (generic part nUinber for MCS-96)
offers the highest level of system integration ever achieved
on a single chip microcontroller. It uses over 120,000
transistors to implement a high performance 16-bit CPU,
8K bytes of progTam memory, 232 bytes of data memory
and both\analog and digital types of 110 features. Figure
I-I shows the evolution of single chip microcontroller at
Intel.

Now that the semiconductor process technologies are

8394
, 8395
8396
8397

.8 BIT CPU

8051
8052

• 4/8K ROM
• 1281256 BYTE RAM
• TIMER/COUNTER
• PARALLEL I/O
• SERIAL I/O

MCS~-48

8048
8049

8050
8021
8022

• 16 BIT CPU
.8KROM

• 232 BYTE RAM
•
•
•
•
•

TIMER/COUNTER'
PARALLEL I/O
SERIAL ~O
10 BIT AID
HIGH SPEED ~O

• PWM
• WATCH DOG TIMER

.8 BITqPU
•
•
•
•
•

1/214K ROM
64/1281256 BYTE RAM
TIMER/COUNTER
PARALLEL 110
8 BIT AID

1980

1976

Figure 1·1. Evolution of Microcontrollers at Intel

1-1

1983

INTRODUC:TIO,. TO MCS®·96
, '~

;

1.1 INTRODUCTION TO THE MCS®·96
The 8096 consists of a 16-bit powerful CPU tightly coupled with program and data memory along with several
I/O features all integrated onto a single piece of silicon.
The CPU supports bit, byte, and word operations. 32-bit
dou.ble words are also supported for a subset of the ..instruction set. With· a 12 MHz il!-put frequency, the 80fl6
can perform a 16-bit addition in 1.0 I!-s and 16 x 16
multiply or 32/.16 divide in 6.5 iJ-s.

16-bit software timers can be in operation at once in addition :to the two 16-bit hardware timers.
An optional on-chip AID converter converts up to four
(in the 48-pin version) or 8 (in the 68-pin version) analog
input channels into lO-bit digital values. Also provided
on-chip, is a serial port, a watchdog timer, and a pulsewidth modulated output signal. Table 1.1 shows the features and benefits :rummary for the MCS-96.

Four high-speed trigger inputs are provided to record the
times,at which external eV!!nts oc.cur with a resolution of
2 iJ-S (at 12 MHz crystal frequency). Up to six high-speed
pulse generator outputS are provided to trigger external
events at preset, times. The high speed output unit can
simultaneously perform timer functions, up to four such

Table 1·1

MCS~·96

The'8096.with its 16-bit CPU and all the I/O features and
interface resources on a ,single piece of silicon represents
the highest level of system integration in the world of
micr~ontrollers. It will open up new applications which
had to use multiple chip solutions in the past.

Features and Benefits Summary

FEATURES

BENEFITS

16-BitCPU

Efficient machine with higher throughput

8K Bytes ROM

Large program space for more complex, larger programs.

232 Bytes RAM·

Large on-board register file.

Hardware MUUDIV

Provides good math capability 16 by 16 multiply or 32 by 16 divide
in 6.5 iJ-S @ 12 MHz ..

6 Addressing Modes

Provides greater flexibility of programming and data manipulation.

High Speed I/O Uriit
4 dedicated I/O lines
4 programmable 110 lines

Can measure and generate pulses with high resolution (2 iJ-S @
12 MHz).

10-Bit ND Converter

Reads the' external analog inp\lts.

Full Duplex Serial Port

Provides asynchronous serial link to other processors or systems.

Up to 40 110 Ports

Provides TTL compatible digital data I/O including system expansion
with standard 8 or 16-,bit peripherals.

Programmable 8 Source Priority
Interrupt System

Respond to asynchronous events.

Pulse Width Modulated Output

Provides a programmable pulse train with variable duty cycle. Also
used to generate analog output.

Watchdog Timer

Provides ability to recover from software malfunction or hardware
upset.

48 Pin (DIP) & 68 Pin (Flatpack, Pin
Grid Array) Versions

Offers a variety of package types to choose from to better fit a specific
application need for number of 1I0's and package size.

1-2

INTRODUCTION TO MOS®.96
1.2. MCSall-96 APPLICATIONS

combining analog and digital 110 processing in the single
chip.

'The MCS-96 products are stand-alone high performance
>single chip mili:rocontrollers designed for use in sophisticated real-time demanding applications such as industrial
control, instrumentation and intelligent computer peripherals. The wide base of applications cut across all industry
segments' (see table 1.2). With the 16-bit CPU horsepower, hlgh-speed math processing and high-speed 1/0,
the 8096 is ideal for complex motor control and axis control systems. Examples include three phase, large horse'power AC motors and robotics.
With its 100bit AID converter option, the device finds
usage in data acquisition systems and closed-loop analog
controllers. It permits considerable system integration by

This chip is ideally suited in the area of instrumentation
products such as gas chromatographs, which combine analog processing with high speed number crunching. The
same features make it a desirable component for aerospace
applications like missile guidance and control.

1.3. MCSiIl-96 FAMILY DEVELOPMENT
SUPPORT TOOLS
The product family is supported by a range of Intel software and hardware development tools. These tools shorten
,the product development cycle, thus bringing the product
to the market sooner.

1.3.1. MCS®-96 Software Development
Package ,
The 8096 software development package provides development system support specifically designed for the MCS96 family of single chip microcontrollers. The package
consists of a'symbolic macro assembler ASM-96, Linkerl
Relocator RL-96 and the librarian LIB-96. Among the
high level languages, PLM-96 is offered along with a
floating point math package. Additional high level languages
being developed for the MCS-96 product
family.

Table 1·2 MCS@·96 Broad Base of Applications
INDUSTRIAL
>Motor Control
Robotics
Discrete and Continuous Process Control
,Numerical Control
Intelligent Transducers

are

INStRUMENTATION
Medical Instrumentation
Liquid and Gas Chromat6graphs
Oscillioscopes

1.3.2. ASM-96 MACRO Assembler
The 8096 macro assembler translates the symbolic assembly language instructions into the machine executable object code. ASM-96 enables the programmer to write the
program in a modular fashion. The modular programs
divide a rather complex program into smalltr functional
uriits, thllt are easier to code, to debug, and to change.
The separate modules can then be linked and located into
one program module using the RL-96 utility, This utility
combines the selected input object modules into a single
output object module. It also allocates memory to input
segments and binds the relocatable addresses to absolute
addresses. It then produces a print file that consists of a
link summary, a symbol table listing and an intermediate
cross-reference listing. LlB-96, another utility helps to
create, modify, and examine library files. The ASM-96
runs on Intellec Series III or IV.

CONSUMER
Video Recorder
Laser Disk Drive
High-end Video Games
GUIDANCE & CONTROL
Missile Control
Torpedo Guidance Control
Intelligent Ammunition
Aerospace Guidance Systems
DATA PROCESSING
Plotters
Color and B&W Copiers
Winchester Disk Drive
Tape Drives
Impact and Non-Impact Printers

1.3.3. PLlM-96
The PUM-96 compiler translates the PUM-96 language
into 8096 relocatable object modules, This allows improved programmer productivity and application reliability. This high level language has been efficiently designed
to map into the machine architecture, so as not to trade
off higher programmer productivity with inefficient code.
Since the language and the compiler are optimized for the
8096 and its application environment, developing software
with PUM-96 is a 'low-risk' project.

TELECOMMUNICATIONS
Modems
Intelligent Line Card Control
AUTOMOTIVE
Ignition Control
Transmission Control
Anti Skid Braking
Emission Control

1-3

INTRODUCTION TO. MCS<1ll~96

1.3.4. Hardware Development Support:
iSBE·96

1.4. MCS®-96 'FAMILY .OF PRODUCTS·

The iSBE-96 is a hardware executiDn and debug tDDI fDr
the MCS-96 products. It,cDnsistsDf a mDnitDr/debugger
resident in an 8096 system. This develDpment system interfaces with the user's 8096 system via tWD ribbDn cables,
.one fDr the 8096 I/O PDrts, and the .other fDr the memDry
bus. The iSBE-96 is cDntrDliedby an Intellec Series III
Dr .other cDmputer system .over a serial link. PDwer fDr the
iSBE-96 can be supplied by plugging it intD the MULTIBUS® card slDt, Dr by an external pDwer supply. The
iSBE-96 is cDntained .on .one standard MULTIBUS bDard.

AlthDUgh 8096 is the generic part number .often, used.for
the MCS-96 prDducts throughout this. manual, the product
family cDnsists .of eight cDnfiguratiDns with eight part
numbers including the 8096. This wide variety of products
is offered tD best meet user's application requirements in
terms of number .of 1I0's and package size,. The Dpti.ons
include Dn-bDard 8K bytes .of mask programmed memDry,
lO-bit A/D cDnverter, and 48 Dr 68 pin package type.
Table 1-3 summarizes all the current products in the
MCS®-96 product family.

The iSBE-96 prDvides the mDst .often used features fDr
real-time hardware emulatiDn. The user. can display and
mDdify memDry, set up break pDints, execute with Dr
withDut breakpDints and change the memDry map. In additiDn, the user can single step thrDugh the system
prDgram.

Table 1·3 MCS®·96 Family. of Products
68 PIN

48 PIN

ROMLESS

8096

8094

ROM

8396

8394

OPTIONS

1.3.5. MCS®-96 Workshop
The wDrkshDp provides the design engineer Dr system
designer hands-Dn experience with the MCS-96 family .of
products. The course includes an explanatiDn .of the Intel
8096 architecture, system timing, input/Dutput desigri.
The lab sessiDns allDw the attendees tD gain in-depth
knDwledge .of the MCS-96 product family and SUpPDrt
tDDls.

DlGITAL
I/O

.
ANALOG
AND
DIGITAL
110

1.3.6. Insite ™ Library
The Intel Insite'Library cDntains several applicatiDn p~D
grams. A very useful program cDntained in the Insite is
SIM-96, the sDftware" simulatDr fDr 8096. It allDws SDftware simulatiDns .of user's system. The 'simulatDr prDvides
the ability tD set'breakpDints, examine'and mDdify memDry, disassemble the Dbje,ct cDde and single step thrDugh
the cDde.

ROMLESS

8097

8095

ROM

8397

8395

The 48 pin versiDn is available in a DIP (dual inline)
package.
The 68 pin versiDn CDmes in two packages, the .Plastic
Flatpack and the Pin Grid Array. .

1-4

Architectural Overview

CHAPTER 2
ARCHITECTURAL OVERVIEW
2.0. INTRODUCTION

operations are possible by directly controlling the
110 through the SFRs. The main benefits of this structure
are the ability to quickly change context, the absence of
accumulator bottleneck, and fast throughput ,and 110
times.

The 8096 can be separated into several sections for the
purpose of describing its operation. There is a CPU, a
programmable High Speed I/O Unit, an analog to digital
converter, a serial port, and a Pulse Width Modulated
(PWM) output for digital to analog conversion. In addition
to these functional units, there are some sections which
support overall operation of the chip such as the clock
generator and the back-bias generator. The CPU and the
programmable I/O make the 8096 very different from any
other microcontroller, let us first examine the CPU.

2.1.1. CPU Buses
A "Control Unit" and two buses connect the Register
File and RALU. Figure 2-1 shows the CPU with its major
bus connections. The two buses are the "A-Bus" which
is 8-bits wide, and the "D-Bus" which is 16-bits wide.
The D-Bus transfers data only between the RALU and the
Register File or Special Function Registers (SFRs). The
A-Bus is used as the address bus for the above transfers
or as a multiplexed address/data bus connecting to the
"Memory Controller". Any accesses of either the internal
ROM or external memory are done through the Memory
Controller.

2.1. CPU OPERATION
The major components of the CPU on the 8096 are the
Register File and the RALU. Communication with the
outside world is done through either the Special Function
Registers (SFRs) or the Memory Controller. The RALU
(Register/Arithmetic Logic Unit) does not use an accumulator, it operates directly on the 256-byte register space
made up of the Register File and the SFRs. Efficient 110

VSS

Within the memory controller is a slave program counter
(Slave PC) which keeps track of the PC in the CPU. By
having most program fetches from memory referenced to

VBB

EA
ALE

BHi
AD
ViR

READY

~~::;::==I=:"~ RESET
VREF
ANGND

I
I
I
I

P3l

I
I
I
I
I
I
I
IL __________ _
PO/ACH

ADDRIDATA
BUS

P2lALT. FUNCTIONS

HS1

HSO

Figure 2-1. Block Diagram (For simplicity, lines connecting port registers to port buffers are not shown.)

2-1

ARCHITECTURAL OVERVIEW

the slave PC, the processor saves time as addresses seldom
have to be sent to the memory controller. If the address
jumps sequence !!ten the slave PC is loaded with a new
value and processing continues. Data fetches from memory are also done through the memory controller, but the
slave PC is bypassed for this operation.

Unit decodes the instructions and generates the correct
sequence of signals to have the RALU perform the desired
function. Figure 2-1 shows the instruction register and the
control unit.

2.1.4. RALU
Most calculations performed by the 8096 take place in the
RALU. The RALU, shown in Figure 2-2, contains a 17bit ALU, the Program Status Word (PSW), the Program
Counter (PC), a loop counter, and three temporary registers. All of the registers are 16-bits or 17-bits (16+ sign
extension) wide. Some of the registers have the ability to
perform simple operations to off-load the ALU.

2.1.2. CPU Register File
The Register File contains 232 bytes of RAM which cart
be accessed as bytes, words, or double-words. Since each
of these locations can be used by the RALU, there are
essentially 232 "accumulators". The first word in the
Register File is reserved for use as the stack pointer so
it can not be used for data when stack manipulations are
taking place. Addresses for accessing the Register File
and SFRs are temporarily stored in two 8-bit address registers by the CPU. hardware.

A separate incrementer is used for the PC; however, jumps
must be handled through the ALU. Two of the temporary
registers have their own shift logic. These registers are
used for the operations which require logical shifts, including Normalize, Multiply, and Divide. The "Lower
Word" register is used only when double-word quantities
are being shifted, the "Upper Word" register is used

2.1.3. RALU Control
Instructions to the RALU are taken from the A-Bus and
stored temporarily in the instruction register. The Control

8-BIT
A·BUS

UPPER WORD REGISTER/SHIFTER

LOWER WORD REGISTER/SHIFTER

1-_ _ _ _ _""7'..:.1::.6_ _ _ _-+~ TEMPORARY REGISTER ...._.p.8!----/

CONSTANTS (0,1,2)

LOWER

Figure 2·2. RALU Block D.lagram

2-2

ARCHITECTURAL OVERVIEW'

wheneveJ a shift is perfonned ot as a temporary register
for many instructions, Repetitive shifts are counted by the
5-bit "Loop Counter".
INTERNAL
CIRCUITRY

A temporary .register is used to store the second operand
of two operand instructions. This includes !he multiplier
during, multiplications and the divisor during divisions.
To perfonn.subtractions, the output of this register can be
clding
register). has six entries in it. Since all interrupts are rising
edge triggered. ifIOCl. 7 = 1, the processor will l).ot be
re-interrupted until the FIFO first contains 5 or less rec·
ords. then contains six or more. Interrupts can also
be generated by pin HSI.O. which has its own interrupt
vector.

A block diagram of the HSO unit is shown in Fig\lfe 218.. The Content Addressable Memory (CAM) file is the
center of control. One CAM regi,Ster is, compared with a
time value ~very state time. Theref9re. it takes 8 state
times to cOlJlpare all CAM registers with a timer.

HSI STATUS REGISTER (HSI_STATUS)
LOCATION 08H

2.7.4. HSI Status
Bits 6 and 7 of the 1/0 Status register 1 (lOS 1) indicate
the status of the HSI FIFO. If bit 6 is a 1•. the FIFO '
contains at least six entries. If bit 7 is a 1.· the FIFO
contains at least 1 entry and the holding registet,has been
loaded. The FIFO may be read after verifyillg that it contains valid data. Caution must be used ,when reading or
testing bits in IOSI, as this action dears,the entire byte.
including the software and hardware timer overflow flags:
It is best to store the byte and .then test the stored value.
See Section 3.7.2.

HSI,o STATUS
.....- - - HSI.1 STATUS
L.._ _ _ _ _ HSI.2 STATUS
.....- - - - - - - HSI.3 STATUS
WHERE FOR EACH 2-alT STATUS FIELD THE LOWER
alT INDICATES WHETHER OR NOT AN EVENT HAS 0cCURRED ON THIS PIN AND THE UPPER BIT INDICATES
THE CURRENT STATUS OF THE PIN.

"Figure 2·17.HSI Status Register Diagram

Reading the HSI is done in two steps. First,the HSI Status

2-13,

ARCHITECT.URALOVERVIEW

. 2.0 ,..S CLOCK

CONTROL
LOGIC

HIGH SPEED OUTPUT CONTROLS
6 PINS
4 SOFTWARE TIMERS
2 INTERRUPTS
INITIATE AID CONVERSION
RESET "FIMER 2'

Figure 2"18. High Speed Output Unit
Each CAM register is 23 bits wide. Sixteen bits specify
the time at which the action is to be carried tiut and 7 bits
specify both the nature of the action 'and whether Timer
1 or Timer 2 is the reference, The format of the comm;md
to the HS9 unit is shown iriFigure 2-19:

reference; the minimum time that can be'loadedisTimer
I
1. A' similar restriction applies if Timer 2 is used as
the reference.
"

Care must:be taken when writing the command tag for
the HSO. If an interrupt occurs during the time between
writing the command tag and loading t.l~e,time value, and
the interrupt service routine writes to the HSO time register, the command tag used in the interrupt routine will
be written to the CAM at both the time specified by the
interrupt routine and the time specified by the main 'program. The command tag from the main program will not
be executed. One way of avoiding this problem would be
to disable interrupts when writing co~ands and times
to the HSO unit. See also Section 3: 7,3.
'

To enter a command into the CAM file, write the 7c bit
"Command Tag" into location 0006H followed by the
time at which the action is to be carried out into word
address 0004H. Writing the time value loads the HSO
Holding Register with both the time and the last written
command tag. The comiI]and does not actually enter the
CAM file until an empty CAM register becomes available.
It can take 'up to 8 state times for a command to enter the
CAM. For this reason, if Timer 1 is being used.as the,

'76'S
I

I TID I I

3
I

CHANNEL

O-S HSO.O - HSO.S
6
HSO.oAND HSO.1 ,
7 HSO.2 AND HSO.3
8-a SOFTWARE'TIMERS
E
RESElTIMER 2
F START AlD'CONVERSION
.......-...;;,.--;--- INTERRUPT/NO,INTERRUPT,
......- - - - - - - SET/CLEAR,
......- - - - - -......- - - - - T1~ER 2/T1MER 1 ,

'Figure 2-1c9. HSO Command Tag Format

2-14

ARCHITECTURAL OVERVIEW

2.8.3. HSO Status

2.8.6. Software Timers

Before writing to the HSO, it is desirable to ensure that
the Holding Register is empty. If it is not, writing to the
HSO will overwrite the value in the Holding Register.
110 Status Register 0 (10S0) bits 6 and 7 indicate the
status of the HSO unit. This register is described in section
2.13.4. If IOSO.6 equals 0, the holding register is empty
. and at least one CAM register is empty. If IOSO.7 equals
0, the holding tegister is empty.

The HSO can be programmed to generate interrupts at
preset times. Up to four such "Software Timers" can be
in operation at a time. As each preprogrammed time is
reached, the HSO unit sets a Software Timer Flag. If the
interrupt bit in the command tag was set then a Software
Timer Interrupt will also be generated. The interrupt service routine can then examine 110 Status register 1 (10S 1)
to determine which software timer expired and caused the
interrupt. 'When the HSO resets Timer 2 or starts an A to
D conversion, it can also be programmed to generate a
software timer interrupt but there is no flag to indicate that
this has occurred. See also Section 3.7.4.

One location in the CAM file is checked each state-time.
Thus, it takes 8 state-times for the Holding Register to
have had access to all 8 CAM registers. Similarly, it takes
8 state-times for the comparator to have had access to all
8 CAM registers. This defines the time-resolution of the
HSO unit to be 8 state-times (2.0 JJ-sec, if the oscillator
frequency is 12 MHz1 Note that the comparator does not
look at the holding register, so instructions in the Iiblding
register do not execute.

If more than one software timer interrupt occurs in the
same time frame it is possible t4at multiple software timer
interrupts will be generated.

Each read or test of any bit in lOS 1 will clear the whole
byte. Be certain to save the byte before testing it unless
you are only concerned with 1 bit. See also Section 3.2.2.

2.8.4. Clearing The HSO
All 8 CAM locations of the HSO are compared before
any action is taken. This allows a pending external event
to be cancelled by simply writing the opposite event to
the CAM. However, once an entry. is placed in the CAM,
it cannot be removed until either the specified timer
matches the written value or the chip is reset. Internal
even~ are not synchronized to Timer 1, and therefore
cannot be cleared. This includes events, on HSO channels
8 through F and all interrupts. Since interrupis are not
synchronized it is possible to have multiple interrupts at
the same.time value.

2.8.5. Using Timer 2 With The HSO
Timer 1 is incremented only once every 8 state-times.
When it is being used as the reference timer for an HSO
action" the comparator has a chaqce to look at all 8 CAM
registers before Timer 1 changes its value. Following the
same reasoning, Timer 2 has been synchronized to allow
it to change at a maximum rate of once per 8 state-times.
Timer 2 increments on both edges of the input signal.

A complete listing of the functions of 10SO, 10SI, and
lOCI can be found in section 2.13. The Timers are described in section 2.6 and the HSI is described in section
2.7.

2.9. ANALOG INPUTS
The A to D converter on the 8096 provides a lO-bit result
on one of 8 input channels. Conversion is done using
successive approximation with a result equal to the ratio
of the input voltage divided by the analog supply voltage.
. If the ratio is 1.00, then the result will be all ones. The
AID converter is available on the 8097, 8397, 8095 and
8395 members of the MCS®-96 family.

2.9.1. AID Accuracy
Each conversion requires 168 state-times (42jJ.S at 12
MHz) i1'ldependent of the accuracy desired or value of
input voltage. The input voltage must' be in the range of
o to VREF, the analog reference and s~pply voltage. Fpr
proper operation, VREF (the reference voltage and analog
power supply) must be held at VCC ± 0.3V with
VREF = 5.0 ± 0.5V. The ND result is calculated from the
formula:
.

When using Timer 2 as the HSO reference, caution must
be taken that Timer 2 is not reset prior to the highest value
for a Timer 2 match in the CAM. This is because the
HSO CAM will hold an event pending until a time match
occurs, if that match is to a time vlllue on Timer 2 which
is never reached, the event will remain pending in the
CAM until the part is reset.

1023 )( (input voltage-ANGND) /

(VREF-ANGND~

It can be seen from this formula that changes in VREF or
ANGND effect the output Of the corverter. This can be
advantageous if a ratiometric sensor is used since these
sensors have an output that can be measured as a proportion of VREF.

Additional caution must be used when Timer 2 is being
reset using the HSO unit, since resetting Timer 2 using
the HSO is an internal event and can therefore happen at
,any time within the eight-state-time window. For this reason, any events scheduled to occur at the same time as a
Timer 2 reset should be logged into the CAM with a Timer
2 value of zero. When using this method to make a programmable modulo counter, the count will stay at the
maximum Timer 2 value only until the,Reset T2 command
is recognized. The count will stay at zero for the transition
which would have changed the count from "N" to zero,
and then change to a one on the next transition.

If high absolute accuracy is needed it may be desirable to
use a separate power supply, or power traces, to operate
the ND converter. There is no sample and hold circuit
internal to the chip, so the input voltage must be held
constant for the entire 168 state times. Examples of connecting the ND converter to various devices are given in
section 4.3.
2-15

ARCHITECTURAL OVERVIEW

AID COMMAND REGISTER
(LOCATION 02H)

CHANNEL # SELECTS WHICH OF THE 8 ANALOG INPUT
CHANNELS IS TO BE CONVERTED TO DIGITAL FORM;
' - - - - - - - GO INDICATES WHEN THE CONVERSION IS TO BE
INITIATED (GO=1 MEANS START NOW, GO=O
MEANS THE CONVERSION IS TO BE INITIATED
BY THE HSO UNIT AT A SPECIFIED TIME).

Figure 2·20. AID Command Register

2.9.2. AID Commands

Result Register at locations 02H and 03H. Although these
addresses are on a word boundary, they must be read as
individual bytes. Information in the ND Result register
is formatted as shown in Figure 2-21. Note that the status
bit may not be-set until 8 state times after the go command.
Information on using the HSO is in section 2.8.

Analog signals can' be sampled by anyone of the 8 analog
input pins (ACHO through ACH7) which are shared with
Port O. ACH7 can also be used as anextemal interrupt if
IOCLl is set (see section 2.5). The ND Command Register, at location 02H, selects which channel is to be converted and whether the conversion should start immediately or when the HSO (Channel #OFH) triggers it. A to
D commands are formatted as shown in Figure 2-20.

2.10. PULSE WIDTH MODULATION OUTPUT (D/A)

The command register is double buffered so it is possible
to write a command to start a conversion triggered by the
HSO while one is still in progress. Care must be taken
when' this is done since if a new conversion is started
while one is already in progress, the conversion in progress
is cancelled and the new one is started. When a conversion
is started, the result register is cleared. For this reason the
result register must be read before a new conversion is
started or data will be lost.

Digital to analog conversion can be done with the pulse
width modulation output; a block diagram of the circuit
is shown in Figure 2-22. The 8-bit counter is incremented
every state time. When it equals 0, the PWM output is
set to a one: When the counter matches the value in the
PWM register,' the output is switched low. When the
counter overflows, the output is once again switched high.
A typical output waveform is shown in Figure 2-23. Note
that when the PWM register equals 00, the output is always
low.

2.9.3. AID Results

The output waveform is a variable duty cycle pulse which
repeats every 256 state times (64 p,S at l2MHz). Changes

Results of the arialog conversions are read from the ND

AID RESULT REGISTER

AID CHANNEL NUMBER
' - - - - - STATUS
= AID CURRENTLY IDLE
1 = CONVERSION IN PROCESS

'---------

AID RESULT:
LEAST SIGNIFICANT 2 BITS
MOST SIGNIFICANT BYTE

Figure 2·21. AID Result Register

2-16

ARCHITECTURAL OVERVIEW
some form of buffer and integrator are needed to obtain
the most usefulness from this feature.
The PWM output shares a pin with Port 2, pin 5 so that
these two features cannot be used at the same time. 10CI.0
equal to I selects the PWM function instead of the standard
port function. More information on lOCI is in section
2.13.3.

2.11. SERIAL PORT
The.serial port is compatible with the MCS-Sl serial port.
It is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can
commence reception of a second byte before a previously
received byte has been read from the receive register. The
serial port registers (SBUF) are both accessed at location
07H. A write to this location accesses the transmit register,
and a read accesses a physically separate receive register.

PWM
OUTPUT

STATE TIME CLOCK
(F(XTAL1)/3)

The serial port can operate in 4 modes (explained below).
Selection of these modes is done through the Serial Port
Status/Control register at location IIH, shown in Figure
2-27.

• PERIOD = 64 "S, FREQUENCY = 15.625 KHz
• DUTY FACTOR PROGRAMMABLE IN 256 STEPS

2.11.1. Serial Port Modes

Figure 2·22. Pulse Width Modulated (D/A) Output

MODE 0
Mode 0 is a shift register mode. The 8096 outputs a train
of 8 shift pulses to an external shift register to clock 8
bits of data into or out of the register from or to the 8096.
Serial data enters and exits the 8096 through RXD. TXD
outputs the shift clock. 8 bits are transmitted or received,
LSB first. A timing diagram of this mode is shown in
Figure 2-24. This mode is useful as an 110 expander in
which application external shift registers can be used as
additional parallel 110 ports. An example of using the port
in this mode is given in section 4.5.

in the duty cycle are made by writing to the PWM register
at location 17H. There are several types of motors which
require a PWM waveform for most efficient operation.
Additionally, if this waveform is integrated it will produce
a DC level which can be changed in 256 steps by varying
the duty cycle.
Details about the hardware required for smooth, accurate
D/A conversion can be found in section 4.3.2. Typically,

DUTY
CYCLE

PWM CONTROL
REGISTER VALUE

OUTPUT WAVEFORM

HI
LO

10%

~~Jl~____~n~____~n~_____

50%

128

HI
LO

.-J

90%

230

HI
LO

.-J

99.6%

255

.HI-TI------,------r-----LO

Figure 2·23. Typical PWM Outputs

2-17

ARCHITECTURAL OVERVIEW

TXO

, OUT
RXO

.. IN

Figure 2-24. Serial Port Mode 0 Timing

STOP

Figure 2-25. Serial Port Frame -

Mode 1

STOP

STOP
PROGRAMMABLE 9TH BIT - - _....
11-BIT FRAME

-I

Figure 2-26. Serial Port Frame Modes 2 and 3
MODE 1
IO-bit frames are transmitted through TXD, and received
through RXD: a start bit (0), 8 data bits (LSB first), and
a stop bit (1). If PEN = 1 then an even parity bit is
transmitted instead of the eighth data bit. This mode is
the one commonly used for CRT terminals. The data frame
for Mode 1 is shown in Figure 2-25.

the 9th data bit can be assigned the value of 0 or 1 using
the TB8 bit. If PEN = 1 the 9th bit will be parity. On
receive, the received 91h data bit is stored and the serial
port intenupt is activated regardless of its value. The data
frame for Modes 2 and 3 is shown in Figure 2-26.

2.11.2. Multiprocessor Communications
Mode 2 and 3 are provided for multiprocessor communications. In mode 2 if the received 9th data bit is not I,
the serial port intenupt is not activated. The way to use
this feature in multiprocessor systems is described below.

MODE 2
ll-bit frames are transmitted through TXD and received
through RXD: a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On transmit,
the 9th data bit can be assigned the value of 0 or 1 using
the TB8 bit. This bit is cleared on each transmission. On
receive, the serial port intenupt is not activated unless the
received 9th data bit is 1. Parity cannot be enabled in this
mode. This mode is commonly used along with mode 3
in a multi processor environment.

When the master processor wants to transmit II block of
data to one of several slaves, it first sends out an address
frame which identifies the target slave. An address frame
will differ from a data frame in that the 9th data bit is 1
in an address frame and 0 in a data frame. No slave in
mode 2 will be intenupted by a data frame. An address
frame, however, will intenupt all slaves so that e~ch slave
can examine the received byte and see if it is being ad~
dressed. The addressed slave switches to mode 3 to receive
the coming data frames, while the slaves that were not
addressed stay in mode 2 and go on about their business.

MODE 3
II-bit frames are transmitted through TXD and received
through RXD: a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On transmit,

2-18

ARCHITECTURAL OVERVIEW
2.11.3. Controlling the Serial Port

The unsigned integer represented by the lower 15 bits of
the baud rate register defines a number B, where B has a
maximum value of 32767. The baud rate for the four serial
modes using either XTAL I or T2CLK as the clock source
is givenby:
Using XTALI:
XTALI frequency. B oF 0
Mode 0: Baud
Rate
4*(B + I)
,

Control of the Serial Port is done through the Serial Port
Control/Status register. The fonnat for the control word
is shown in Figure 2-27. Note that reads access only part
of the byte, as do writes, and that TB8 is cleared after
each byte is transmitted.
In Mode 0, if REN = 0, writing to SBUF will start a
transmission. Causing a rising edge on REN, or clearing
RI with REN = I, will start a reception. Setting REN = 0
will stop a reception in progress, and inhibit further receptions. To avoid a partial or complete undesired reception, REN must be set to zero before clearing Rl. This
can be handled in an interrupt environment by using software flags, or in a straight-line code environment by using
the Interrupt Pending register to signal the completion of
a receive. In any mode, it is necessary to set IOCI.5 to
a I to enable the TXD pin. Some examples of the software
involved in using the serial port can be found in section
3.8. More infonnation on lOCI is in section 2.13.3.

Others:

XT ALI frequency
64*(B + I)

Mode 0: Baud
Rate

T2CLK frequency . B oF 0
B
'

Baud
Rate
Using T2CLK:

Others:

Baud
T2CLK frequency. B oF 0
Rate
16*B'
Note that B cannot equal 0, except when using XTALI
in other than mode O.
Common baud rate values, using XTALI at 12MHz, are
shown below.
Baud Register
Value
Baud Rate
Others
Mode 0

2.11.4. Determining Baud Rates
Baud rates in all modes are detennined by the contents of
a 16-bit register at location OOOEH. This register must be
loaded sequentially with 2 bytes (least significant byte
first). The MSB of this register selects one of two sources
for the input frequency to the baud rate generator. If it is
a I, the frequency on the XTALI pin is selected, if not,
the extemal frequency from the T2CLK pin is used. It
should be noted that the maximum speed of T2CLK is
one transition every 2 state times, with a minimum period
of 16 XTALl cycles.

8137H
8270H
84E1H
89C3H
A70FH

9600
4800
2400
1200
300

8013H
8026H
804DH
809BH
8270H

The maximum asynchronous baud rate is 187.5 Kbaud,
with a 12MHz clock.

LOCATION 11H
SP_STAT
(READ ONLy)

IRB8~RPE I

SP_CON
(WRITE ONLY)

6
RI

4
188

3
REN

1 1 J J
2
PEN

L-'~

NOTE:

1
M2

0
M1

SPECIFIES THE MOD E:
0,0 = MODE 0
0,1 = MODE 1
1,0= MODE 2
1,1 = MODE 3

PEN

ENABLE THE PARITY FUNCTION (EVEN PARITY):

REN

ENABLES THE RECEI VE FUNCTION:

TB8
TI

PROGRAMS THE 9TH DATA BIT (IF NOT PARITy) ON
TRANSMISSION: (CLE ARS AFTER TRANSMISSION)
IS THE TRANSMIT INTERRUPT FLAG:

IS THE RECEIVE INTE RRUPTFLAG:

RB8,
RPE

IS THE 9TH DATA BIT RECEIVED (IF NOT PARITy),
IS THE PARITY ERROR INDICATOR (IF PARITY ACTIVE).

AND RI ARE CLEARED WHEN SP _ STAT IS READ.

Figure 2-27. Serial Port Control/Status Register

2·19

ARCHITECTURAL OVERVIEW,
2.12. 1/0 PORTS 0, 1, 2, 3, AND 4

to speed up the O-to-l transition time. See also Sections
3.7.1 and 4.2.2.

There are five 8-bit 110 ports on the 8096. Some of these
ports are input only, some output only, some bidirectional
and some have alternate functions. Input ports connect to
the internal bus through an input buffer. Output ports
connect through an output buffer to an intemal register
that holds the output bits. Bidirectional ports consist of
an internal register, an output buffer, and an input buffer.

2.12.3. Port 2
Port 2 is a multi-functional port. Six of its pins are shared
with other functions in the 8096, as shown below.

AHernate
Function
Port Function
P2.0 output
TXD (serial port
transmit)
P2.1 input
RXD (serial port
receive)
P2.2 input
EXTINT
(external interrupt)
P2.3 input
T2CLK (Timer
2 input)
T2RST (Timer
P2.4 input
2 reset)
P2.S output
PWM
(pulse-width
modulation)
quasi-bidirectional
P2.6
P2.7
quasi-bidirectional

When an instruction accesses a bidirectional port as a
source register, the question often arises as to whether the
value that is brought into the CPU comes from the internal
port register or from the port pins through the input buffer.
In the 8096, the value always comes from the port pins,
never from the internal register.

2.12.1. Port 0
Port 0 is an input only port which shares its pins with the
analog inputs to the AID Converter. One can read Port 0
digitally, and/or, by writing the appropriate control bits
to the AID Command Register, select one of the lines of
this port to be the input to the AID Converter. While a
conversion is in process, the impedance of the selected
line is lower than normal. See the data sheet for the specific
values.

Controlled by
10CI.S
N/A

10Cl.I
lOCO. 7
10CO.S
10CI.O

2.12.2. Port 1
Port I is a quasi-bidirectional 1/0 port. "Quasi-bidirectional" means the port pin has a weak internal pullup that
is always active and an internal pulldown which can either
be on (to output a 0) or off (to output a 1). If the internal
pulldown is left off (by writing a 1 to the pin), the pin's
logic level can be controlled by an external pulldown
'which can either be on (to input a 0) or off (to input a 1).
From the user's point of view the main distinction is that
a quasi-bidirectional input will source current while being
externally held low and will pull itself high if left alone.

2.12.4. Ports 3 and 4
Ports 3 and 4 have two functions. They are either bidirectional ports with open-drain outputs or System Bus pins
which the memory controller uses when it is accessing
off-chip memory. If the EA line is. low, the pins always
act as the System Bus. Otherwise they act as bus pins,
only during a memory access. If these pins are being used
as ports and bus pins, ones must be written to them prior
to bus operations.

In parallel with the weak internal pullup, is a' much
stronger internal pullup that is activated for one state time
when the pin is internally driven from 0 to J. This is done

Strong internal pullups are used during external memory
read or write cycles when the pins are used as address or
data outputs. At any other time, the internal pullups are

HSI.O INPUT ENABLE/DiSABLE
TIMER 2 RESET EACH WRITE
~--- HSI.1 INPUT ENABLE/DISABLE

,1.-_ _ _ _ TIMER'2 EXTERNAL RESET ENABLE/DiSABLE

~----- HSI.2 INPUT ENABLE/DiSABLE
' - - - - - - - - TIMER 2 RESET SOURCE HSI.orT2FiSf
' - - - - - ' - - - - " - - - - - HSI.3 INPUT ENABLE/DISABLE
' - - - - - - - - - - - 'TIMER 2 CLOCK SOURCE HSI.1tT2CLK

Figure, 2-28. 1/0 Control Register

2-20

o (lOCO)

ARCHITECTURAL OVERVIEW

2.13.3. 1/0 Control Register 1 (IOC1)

disabled. The port pins and their system bus functions are
shown below:

Port Pin

System Bus Function

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7

ADO
ADI
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD 10
ADll
ADl2
ADl3
ADI4
ADI5

10C I is used to select some pin functions and enable or
disable some interrupt sources. Its location is 0016H. Port
pin P2.5 can be selected to be the PWM output instead
of a standard output. The external interrupt source can be
selected to be either EXTINT (same pin as P2. 2) or Analog
Channel 7 (ACH7, same pin as PO.7). Timer I and Timer
2 overflow interrupts can be individually enabled or disabled. The HSI interrupt can be selected to activate either
when there is I FIFO entry or 7. Port pin P2.0 can be
selected to be the TXD output. HSO.4 and HSO.5 can be
enabled or disabled to the HSO unit. More information
on interrupts is availabldn section 2.5. The positions of
the lOCI control bits are shown in Figure 2-29.

2.13.4. 1/0 Status Register 0 (1050)
There are two I/O status registers, 10SO and lOS I. 10SO,
located at 0015H, holds the current status of the HSO
lines and CAM. The status bits of 10SO are shown in
Figure 2-30.

- 2.13.5. 1/0 Status Register 1 (IOS1)
10SI is located at 0016H. It contains status bits for the
timers and the HSI. Every access of this register clears
all of the timer overflow and timer expired bits. It is,
therefore, important to first store the byte in a temporary
location before attempting to test any bit unless only one
bit will ever be of importance to the program. The status
bits of 10SI are shown" in Figure 2-31.

2.13. STATUS AND CONTROL REGISTERS
2.13.1. I/O Control Registers
There are two 110 Control registers, lOCO and lOCI.
lOCO controls Timer 2 and the HSI lines. lOCI controls
some pin functions, interrupt sources and 2 HSO pins.
Whenever input lines are switched between two sources,
or enabled, it is possible to generate transitions on these
lines. This could cause problems with respect to edge
sensitive lines such as the HSI lines, Interrupt line, and
Timer 2 control lines.

2.14. WATCHDOG TIMER (WDT)
This feature is provided as a means of graceful recovery
from a software upset. Once the watchdog is initialized,
if the software fails to reset the watchdog at least every
64K state times, a hardware reset will be initiated.

2.13.2. I/O Control Register 0 (lOCO)
lOCO is located at 0015H. The four HSI lines can be
enabled or disabled to the HSI unit by setting or clearing
bits in lOCO. Timer 2 functions including clock and reset
sources are also determined by lOCO. The control bit
locations are shown in Figure 2-28.

The watchdog is initialized by the first write of the clear
WDT code to the WDT register. Once the watchdog is
initialized it cannot be disabied by software. On reset the
watchdog is not active.

LOCATION 16H
17161s141312111 0 1

l:=

SELECT PWMlSELECT P2.5
EXTERNAL INTERRUPT - ACH7/EXTINT
TIMER 1 OVERFLOW INTERRUPT ENABLE/DISABLE
TIMER 2 OVERFLOW INTERRUPT ENABLE/DISABLE
HSO.4 OUTPUT ENABLEIDISABLE
SELECT TXO/SELECT P2.0
HSO.S OUTPUT ENABLE/DiSABLE
HSI INTERRUPT -

FIFO FULLI;:;:HO;::;;L;-;D;;;IN;;;G
......
RE;;;G"'I;:;;ST..E;;;R"L-;:O~A-;;D=ED

Figure 2-29.1/0 Control Register 1 (IOC1)

2-21

ARCHITECTURAL OVERVIEW

LOCATION 1SH
17161S141312111 0 1

L-:=

IHSO •O CURRENT STATE
HSO.1 CURRENT STATE
HSO.2 CURRENT STATE
HSO.3 CURRENT STATE
HSO.4 CURRENT STATE
HSO.S CURRENT STATE
CAM IS FULL OR HOLDING REGISTER IS FULL
HSO HOLDING REGISTER IS FULL

Figure 2-30. 1/0 Status Register 0 (IOSO)

,
LOCATION 16H

17161~14131211101

L-:=

SOFTWARE TIMER 0 EXPIRED
SOFTWARE TIMER 1 EXPIRED
SOFTWARE TIMER 2 EXPIRED
SOFTWARE TIMER 3 EXPIRED
TIMER 2 HAS OVERFLOW
TIMER 1 HAS OVERFLOW
HSI FIFO IS FULL
HSI HOLDING REGISTER DATA AVAILABLE

Figure 2-31. HSIO Status Register 1 (IOS1)

2.14.1. Disabling The Watchdog

The software can be designed so that the watchdog times
out if the program does not progress properly. The watchdog will also time-out if the software error was due to
ESD (Electrostatic Discharge) or other hardware related
problems. This prevents the controller from having a malfunction for longer than 16 mS if a 12 MHz oscillator is
used.

The watchdog should be disabled by software not initializing it. If this is not possible, such as during program
development, the watchdog can be disabled by holding
the RESET pin at 2.0 to 2.5 volts. Voltages over 2.5 volts
on the pin could quickly damage the part. Even at 2.5
volts, using this technique for other than debugging purposes is not recommended, as it may effect long term
reliability. It is further recommended that any part used
in this way for more than several seconds, not be used in
production versions of products.

The watchdog timer is a 16-bit counter which is incremented every state time. When it overflows it pulls down
the RESET pin for at least two state times, resetting the
8096 and any other chips connected to the reset line. To
prevent the timer from overflowing and resetting the system, it must be cleared periodically. Clearing the timer is
done by writing a "OIEH" followed by an "OElH" to
the WDT register at location OOOAH.

2.15. RESET
2.15.1. Reset Signal
As with all processors, the 8096 must be reset each time
the power is turned on. To complete a reset, the RESET
pin must be held active (low) for at least 2 state times
after VCC, the oscillator, and the back bias generator have,
stabilized (-1.0 milliseconds). Then when RESET is
brought high again, the 8096 executes a reset sequence
that takes 10 state times. (It initializes some registers,
clears the PSW and jumps to address 2080H.)

Use of a large reset capacitor on the RESET pin will
increase the length of time required for a 'watchdog initiated reset. This is because the capacitor will keep the
RESET pin ,from responding immediately to the internal
pull-ups and pull-downs. A large capacitor on the RESET
pin may also interfere with the reset of other parts connected to the RESET pin. Under some circumstances, it
may be desirable to use an open collector circuit. See
section 4.4.

The 8096 can be reset using a capacitor, I-shot, or any
other method capable of providing a pulse of at least 2

2-22

ARCHITECTURAL OVERVIEW
NMI

state times longer than required for VCC and the oscillator
to stabilize.
For best functionality, it is suggested that the reset pin pe
pulled low with an open collector device. In this way,
several reset sources can be wire ored together. Remember, the RESET pin itself can be a reset source (see section
2.14). Details of hardware suggestions for reset can be
found in section 4.4.

A low to high transition causes a vector to external memory location OOOOH. Reserved for use in Intel Development systems.
It is important to note that the Stack Pointer and Interrupt
Pending Register are undefined, and need to be initialized
in software. The Interrupts are disabled by both the mask
register and pSW. 9 after a reset.

2.15.2. Reset Status

2.15.3. Reset Sync Mod,

The I/O lines and control of the 8096 will be in their reset
state within 2 state times after reset is low, with VCC and
the oscillator stabilized. Prior to that time, the status of
the 110 lines is indeterminate. After the 10 state time reset
sequence, lite Special Function Registers will be set as
follows:

The RESET line can be used to Starnhe 8096 at an exact
state time to provide for synchronization of test equipment
and multiple chip systems. RESET is active low. To synchronize parts, RESET is brought high on the rising edge
of XTALI. Complete details on synchronizing parts can
be found in section 4.1. 5.

SFR
Port I
Port 2
Port 3
Port 4
PWM Control
Serial Port (Transmit)
Serial Port (Receive)
Baud Rate Register
Serial ControVStatus
AID Command
AID Result
Interrupt Pending
Interrupt Mask
Timer 1
Timer 2
Watchdog Timer
HSI Mode
HSI Status
10SO
lOS 1
lOCO
lOCI

It is very possible that parts which start in sync may not
stay that way. The best example of this would be when
a "jump on 110 bit" is being used to hold the processor
in a loop. If the line changes during the time it is being
tested, one processor may see it as a one, while the other
sees it as a zero. The result is that one processor will do
an extra loop, thus putting it several states out of sync
with the other.

reset-value
llllllllB
1l0XXXXIB
llllllllB
1111111IB
OOH
undefined
undefined
undefined
undefined
undefined
undefined
undefined
OOOOOOOOB
OOOOH
OOOOH
OOOOH
11 11 11 llB
undefined
OOOOOOOOB
OOOOOOOOB
XOXOXOXOB
XOXOXXXIB

2.16. PIN DESCRIPTION

vee
Main supply voltage (5V).

VSS
Digital circuit ground (OV).There are two VSS pins, both
must be tied to ground.

VPD
RAM standby supply voltage (5V). This Voltage must be
present during normal operation. See section 2.4.2 and 4.

VREF
Reference voltage and power supply for the analog portion
of the AID converter. Nominally at 5 volts. See section
2.9.1 and 4.

Other conditions following a reset are:

RD
WR
ALE
BHE
INST

ANGNO
Reference ground for the AID converter. Should be held
at nominally the same potential as VSS. See section 2.9.1
and 4.

reset value
empty
empty
OOOOOOB
OOOOH
undefined
2080H
high
high
low
low
high

vaa
Substrate voltage from the on-chip back-bias generator.
This pin should be connected to ANGND through a 0.01
uf capacitor (and not connected to anything else). The
capacitor is not required if the AID converter is not being
'
used.

XTALl
Input of the oscillator inverter and input to the internal
clock generator. See sections 2.2 and 4.

2·23

ARCHITECTURAL OVERVIEW

XTAL2

Output of the oscillator inverter. See section 2.2.

Write signal output to external memory. WR is activated
only during external memory writes. See section 2.3.6
and 4,6.

CLKOUT
Output of the internal clock generator. The frequency of
CLKOUT is y, the oscillatorfrequency. It has a 33% duty
cycle. CLKOUT can drive' one TTL input. See section
2.2.

SHE
Bus High Enable signal output to external memory. BHE
(O/l) selects/deselects the bank of memory that is connected to the high byte of the data bus. See section 2.3.5
and 4.6.

RESET
Reset input to the chip, also output to other circuits. Input
low for at least 2 state times to reset the chip. RESET has
a strong internal pullup. See section 2.15 and 4.1.

READY

TEST
Input low enables a factory test mode. The user should
tie this pin to VCC for llormal operation.

The READY input is used to lengthen external memory
bus cycles up to the time specified in the data sheet. It
has a weak internal pullup. See section 2.3.6 and 4.6.

NMI
A low to high transition causes a vector to external memory location OOOOH. Reserved for use in Intel Development systems.
INST
Output high while the address is valid during an external
read indicates the read is an instruction fetch. See section
2.3.6 and 4.6.

EA
Input for memory select (External Access). EA = 1 causes
memory accesses to locations 2000H through 3FFFH to
be directed to on-chip ROM. EA = 0 causes accesses to
these locations to be directed to off-chip memory. EA has
an internal puUdown, so it goes to 0 unless driven to 1.
See section 2.3,3.

HSI
High impedance inputs to HSI Unit. Four HSI pins are
available: HSI.O, HSl.l, HSI.2, and HSI.3. Two of them
(HSI.2 and HSI.3) are shared with the HSO Unit. See
section 2.7.

HSO
Outputs from HSO Unit. Six HSO pins are available:
HSO.O, HSO.l, HSO.2, HSO.3, HSOA, and HSO.5.
Two of them (HSOA and HSO.5) are shared with the HSI
Unit. All HSO pins are capable of driving one TTL input.
See section 2.8.

PORT O/ANALOG CHANNEL
High impedance input-only port. These pins can be,used
as digital inputs and/or as analog inputs to the on-chip
AID converter. See sections 2.9 and 2.12.1.

ALE
Address Latch Enable output. ALE is activated only during external memory accesses. It is used to latch the address from the multiplexed address/data bus. See section
.
2.3.5 and 4.6.

PORT 1
Quasi-bidirectional I/O port, All pins of PI are capable
of driving one LS TTL input. See section 2.12.2.

RD
PORT 2
Multi-functional port. Six of its pins are shared with other
functions in the 8096, as shown below.

Read signal output to external memory. RD is activated
only during external memory reads. See section 2.3.5 and
4.6.

Port

Function

P2.0
P2.1
P2.2
P2.3
P2A
P2.5
P2.6
P2.7

output
input
illput
inI1ut
input,
output
quasi-bidirectional
quasi-bidirectional

Alternate Function
TXD (serial port transmit)
RXD (serial port receive)
EXTINT (external interrupt)
T2CLK (Timer 2 input)
T2R~T (Timer 2 reset)
PWM (pulse-width modulator)

2-24

Reference
sectic;m
2.11.3
2.11.3
2.5
2.6.2
2.6.2
2,10

ARCHITECTURAL OVERVIEW

The multi-functional inputs are high impedance. See section 2.12.3.

Name
Pl.1
Pl.2
P1.3
Pl.4
Pl.5
Pl.6
Pl.7
P2.0/TXD
P2.IIRXD
P2.2/EXTINT
P2.3/T2CLK
P2.4!T2RST
P2.5/PWM
P2.6
P2.7
P3.0/ADO
P3.IIADl
P3.2/AD2
P3.3/AD3
P3.4/AD4
P3.5/AD5
P3.6/AD6
P3.7/AD7
P4.0/AD8
P4.IIAD9
P4.2/ADIO
P4.3/AD11
P4.4/ADI2
P4.5/AD13
P4.6/ADI4
P4.7/ADl5
RD
READY
RESET
RXD/P2.1
TEST
TXD/P2.0
T2CLKlP2.3
T2RST/P2.4
VBB
VCC
VPD
VREF
VSS
VSS
WR
XTALl
XTAL2

PORTS 3 AND 4
8-bit bidirectional 110 ports. These pins are shared the
multiplexed address/data bus when accessing external
memory, with the Port 3 pins accessing the low byte and
Port 4 pins accessing the high byte. They are open drain
except when being used as system bus pins. See section
2.3.5.

2.17. PIN LIST
The following is a list of pins in alphabetical order. Where
a pin has two names it has been listed under both names,
except for the system bus pins, ADO-ADI5, which are
listed under Port 3 and Port 4.

Name
ACHO/PO.O
ACHIIPO.1
ACH2/PO.2
ACH3/PO.3
ACH4/PO.4
ACH5/PO.5
ACH6/PO.6
ACH7/PO.7
ALE
ANGND
BHE
CLKOUT
EA
EXTINT/P2.2
HSI.O
HSI.1
HS1.2/HSO.4
HSI.3/HSO.5
HSO.O
HSO.l
HSO.2
HSO.3
HSO .4/HSI. 2
HSO.5/HSI.3
INST
NMI
PWM/P2.5
PO.O/ACHO
PO.IIACHl
PO.'2/ACH2
PO.3/ACH3
PO.4/ACH4
PO.5/ACH5
PO.6/ACH6
PO.7/ACH7
Pl.O

68-Pln
4
5
3
6
67
68
2
1
16
66
37
13
7
63
54
53
52
51
50
49
44
43
52
51
15
7
39
4
5
3
6
67
68
2
1
59

48-Pln
-

43
42
40
41
34
44
15

39
47
3
4
5
6
7
8
9
10
5
6

43
42 ,
40
41

68-Pln
58
57
56
55
48
47
46
60
61
63
34
36
39
45
40
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
17
35
62
61
14
60
34
36
41
9
64
65
10
42
38
11
12

48-Pln

2
I
47

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
33
16
48
1
-

12
38
46
45
11
37
14
36
35

The Following pins are not bonded out in the 48-pin package:
PLO through P1.7, PO.O through PO.3, P2.3, P2.4, P2.6,
P2.7 CLKOUT, INST, NMI, TEST, T2CLK(P2.3),
T2RST(P2.4).

2-25

MCS®,96 Software
Design Information

CHAPTER 3
MCS®-96 SOFTWARE DESIGN INFORMATION
3.0. INTRODUCTION

operators can be applied to WORD operands but the result
must be interpreted modulo 65536. Logical operations on
WORDS are applied bitwise. Bits within words are labeled
from 0 to 15 with 0 being the least significant bit. WORDS
must be aligned at even byte boundaries in the MCS-96
address space. The least significant byte of the WORD
is in the even byte address and the most significant byte
is in the next higher (odd) address. The address of a word
is the address of its least significant byte.

This section provides information which will primarily
interest those who must write programs to execute in the
8096. Several other sources of information are currently
available which will also be of interest:

MCS@·96 MACRO ASSEMBLER USER'S GUIDE
Order Number 122048-001
MCS·96 UTILITIES USER'S GUIDE
Order Number 12204'l-001

3.1.3. Short-Integers
SHORT-INTEGERS are 8-bit signed variables which can
take on the values between - 128 and + 127. Arithmetic
operations which generate results outside of the range of
a SHORT-INTEGER will set the overflow indicators in
the program status word. The actual numeric result returned will be the same as the equivalent operation on
BYTE variables. There are no alignment restrictions on
SHORT-INTEGERS so they may be placed anywhere in
the MCS-96 address space.

MCS·96 MACRO ASSEMBLER AND UTILITIES
POCKET REFERENCE
. Order Number 122050-001
Throughout this chapter short segments of code are used
to illustrate the operation of the device. For these sections
it has been assumed that a set of temporary registers have
been predeclared. The names of these registers have been
chosen as follows:
AX, BX, CX, and DX are 16 bit registers.

3.1.4. Integers

AL is the low byte of AX, AH. is the high byte.
.BL is the low byte of BX

INTEGERS are 16-bit signed variables which can take on
the values between - 32,768 and 32,767. Arithmetic operations which generate results outside of t~e range of an
INTEGER will set the overflow indicators in the program
status word. The actual numeric result returned will be
the same as the equivalent operation on WORD variables.
INTEGERS conform to the same alignment and addressing rules as do WORDS.

CL is the low byte of CX
DL is the low byte of DX
These are the same as the names for the general data
~gisters used in 8086. It is important to note, however,
that in the 8096, these are not dedicated registers but
merely the symbolic names assigned by the programmer
to an eight byte region within onboard register file.

3.1.5. Bits
BITS are single-bit operands which can take on the Boolean'values of true and false. In addition to the normal
support for bits as components of BYTE and WORD operands, the 8096 provides for the direct testing of any bit
in the internal register file. The MCS-96 architecture requires that bits be addressed as components of BYTES
or WORDS, it does not support the direct addressing of
bits that can occur in the MCS-51 architecture.

3.1. OPERAND TYPES
The MCS@-96 architecture provides support for a variety
of data types which are likely to be useful in a control
application. In the discussion of these operand types that
follows, the names adopted by the PLM-96 programming
language will be used where appropriate. To avoid confusion the name of an operand type will be capitalized.
A "BYTE" is an unsigned eight bit variable; a "byte"
is an eight bit unit of data of any type.

3.1.6. Double-Words
DOUBLE-WORDS are unsigned 32-bit variables which
can take on the values between 0 and 4,294,967,295. The
MCS-96 architecture provides direct support for this operand type only for shifts and as the dividend in a 32 by
16 divide and the product of a 16 by 16 mUltiply. For
these operations a DOUBLE-WORD variable must reside
in the on-board register file of the 8096 and be aligned
at an address which is evenly divisible by 4. A DOUBLEWORD operand is addressed by the address of its least
significant byte. DOUBLE-WORD operations which are
not directly supported can be easily implemented with two
WORD operations. For consistency with INTEL provided
software the user should adopt the conventions for addressing DOUBLE-WORD operands w/lich are discussed
in section 3.5.

3.1.1. Bytes
BYTES are unsigned 8-bit variables which can take on
the values between 0 and 255. Arithmetic and relational
operators can be applied to BYTE operands but the result
must be interpreted in modulo 256 arithmetic. Logical
operations on BYTES are applied bitwise. Bits within
BYTES are labeled from 0 to 7 with 0 being the least
significant bit. There are no alignment restrictions for
BYTES so they may be placed anywhere in the MCS-96
address space.

3.1.2. Words
WORDS are unsigned 16-bit variables which can take on
the values between 0 and 65535. Arithmetic and relational

3·1,

MCS®·96 SOFTWARE DESIGN INFORMATION

3.1.7. Long-Integers
address which is evenly divisible by 4. A LONG-INTEGER
is addressed by the address of its least significant byte.

LONG-INTEGERS are 32-bit signed variables which can
take on the values between -2,147,483,648 and
2,147,483,647. The MCS-96 architecture provides direct
support for this data type only for shifts and as the dividend
in a 32 by 16 divide and the product of a 16 by 16 mUltiply.

LONG-INTEGER operations which are not directly supported can be easily implemented with two INTEGER
operations. For consistency with Intel provided software,
the user should adopt the conventions for addressing
LONG operands which are discussed in section 3.5.

LONG-INTEGERS can also be normalized. For these
operations a LONG-INTEGER variable must reside in the
onboard register file of the 8096 and be aligned at an

3.2. OPERAND ADDRESSING
scribed as they are seen through the assembly language.
The six basic addressing modes which will be described
are termed register-direct, indirect, indirect with auto-increment, immediate, short-indexed, and long-indexed.
Several other useful addressing operations can be achieved
by combining these basic addressing modes with specific
registers such as the ZERO register or the stack pointer.

Operands are accessed within the address space of the
8096 with one of six basic addressing modes. Some of
the details of how these addressing modes work are hidden
by the assembly language. If the programmer is to take
full advantage of the architecture, it is important that these
details be understood. This section will describe the addressing modes as they are handled by the hardware. At
the end of this section the addressing modes will be de-

3.2.1. Register-direct References
register address must conform to the alignment rules for
the operand type. Depending on the instruction, up to
three registers can take part in the calculation. .

The register-direct mode is used to directly access a register from the 256 byte on-board register file. The register
is selected by an 8-bit field within the instruction and
Examples
AX,BX,CX
AX,BX
CL

ADD
MUL
INCB

; AX:=BX+CX
; AX:=AX*BX
: CL'=CL+ I

3.2.2. Indirect References
The indirect mode is used to access an operand by placing
its address in a WORD variable in the register file. The
calculated address must conform to the alignment rules
for the operand type. Note that the indirect address can
refer to an operand anywhere within the address space of

the 8096, including the register file. The register which
contains the indirect address is selected by an eight bit
field within the instruction. An instruction can contain
only one indirect reference and th.e remaining operands
of the instruction (if any) must be register-direct references.

Examples
LD
ADDB
POP

AX,[AX]
; AX: = MEM _ WORD(AX)
AL,BL,[CX] ; AL: = BL + MEM _ BYTE(CX)
[AX]
; MEM _ WORD(AX) : = MEM _ WORD(SP), SP. = SP + 2

3.2.3. Indirect with Auto-increment References
This addressing mode is the same as the indirect mode
except that the WORD variable which contains the indirect
address is incremented after it is used to address the operand. If the instruction operates on BYTES or SHORT-

INTEGERS the indirect address variable will be incremented by one, if the instruction operates on WORDS or
INTEGERS the indirect address able will be incremented
by two.

Examples
LD
ADD
PUSH

: AX: = MEM _ WORD(BX); BX: = BX + 2
AX,[BX]+
AL,BL,[CX] + AL:=AL+BL+MEM _ BYTE(CX); CX:=CX+ I
SP: =SP-2;
[AX] +
MEM _ WORD(SP): = MEM _ WORD(AX)
AX:=AX+2

3·2

MCS~.96

SOFTWARE DESIGN INFORMATION

3.2.4. Immediate References
This addressing mode allows an operand to be taken directly from a field in the instruction. For operations on
BYTE or SHORT-INTEGER operands this field is eight
bits wide, for operations on WORD or INTEGER oper-

ands the field is 16 bits wide. An instruction can contain
only one immediate reference and the remaining operand(s) must be register-direct references.

Examples
ADD AX,#340; AX:=AX+340
PUSH #1234H ; SP· =SP-2; MEM _ WORD(SP):= 1234H
DIVB AX,#l0 . AL:=AXIlO; AH:=AX MOD \0

3.2.5. Short-indexed References
In this addressing mode an eight bit field in the instruction
selects a WORD variable in the register file which is
assumed to contain an address. A second eight bit field
in the instruction stream is sign-extended and summed
with the WORD variable to .form the address of the operand which will take part in the calculation. Since the
Examples
LD
MULB

AX,12[BX]
AX,BL,3[CX]

eight bit field is sign-extended the effective address can
be up to 128 bytes before the address in the WORD variable and up to 127 bytes after it. An instruction cpn
contain only one short-indexed reference and the rem "'1'
ing operand(s) must be register-direct references

. AX: = MEM _ WORD(BX + 12)
. AX. = BL *MEM _ BYTE(CX + 3)

3.2.6. Long-indexed References
This addressing mode is like the short-indexed mode except that a 16-bit field is taken from the instruction and
added to the WORD variable to form the address of the

operand. No sign extension is necessary. An instruction
can contain only one long-indexed reference and the reo
maining operand(s) must to register-direct references,

Examples
AND AX,BX,TABLE[CX]
. AX: = BX AND MEM _ WORD(TABLE + CX)
ST
AX,TABLE[BX]
, MEM _ WORD(TABLE + BX) . = AX
ADDB AL,BL,LOOKUP[CX] .. AL' = BL + MEM _ BYTE(LOOKUP + CX)

3.2.7. ZERO Register Addressing
The first two bytes in the register file are fixed at zero by
the 8096 hardware. In addition to providing a fixed source
of the constant zero for calculations and comparisons, this
register can be used as the WORD variable in a longExamples
ADD AX, 1234[0]
POP 5678[0]

3.2~8.

indexed reference. This combination of register selection
and address mode allows any location ID memory to be
addressed directly.

; AX: = AX + MEM _ WORD(l234)
, MEM _ WORD(5678): = MEM _ WORD(SP)
; SP:=SP+2

Stack Pointer Register Addressing

The system stack pointer in the 8096 can be accessed as
register 18H of the internal register file. In addition to
providing for convenient manipulation of the stack pointer,
this also facilitates the accessing of operands in the stack.
The top of the stack, for example, can be accessed by
Examples
PUSH
LD

[SP]
AX,2[SP]

using the stack pointer as the WORD variable in an indirect
reference. In a similar fashion, the stack pointer can be
used in the short-indexed mode to access data within the
stack.

; DUPLICATE TOP _ OF _ STACK
; AX: = NEXT _ TO _ TOP

3-3

MCS®·96 SOFTWARE DESIGN INFORMATION

3.2.9. Assembly Language Addressing Modes
The 8096 assembly language simplifies the choice of addressing modes to be used in several respects:
Indexed Addressing. The assembly language will choose
between short and long indexing depending on the value
of the index expression. If the value can be expressed in
eight bits then short indexing will be used, if it cannot be
expressed in eight bits then long indexing will be used.

Direct Addressing.The assembly language will choose
between register-direct addressing and long-indexed with
the ZERO register depending on where the operand is in
memory. The user can simply refer to an pperand by its
symbolic name; if the operand is in the register file, a
register-direct reference will be used, if the operand is
elsewhere in memory, a long-indexed reference will be
generated.

The use of these features of the assembly language simplifies the programming task and should be used wherever
possible.

3.3 PROGRAM STATUS WORD
The program status word (PSW) is a collection of Boolean
flags which retain information concerning the state of the
user's program. The format of the PSW is shown in figure
3-1. The information in the PSW can be broken down into

two basic categories; interrupt control and condition flags.
The PSW can be saved in the system stack with a single
operation (PUSHF) and restored in a like manner (POPF).

Figure 3-1. PSW Register
eration generated a' negative result. Note that the N flag
will be set to the algebraically correct state even if the
calculation overflows.

3.3.1. Interrupt Flags
The lower eight bits of the PSW are used to individually
mask the various sources of interrupt to the 8096. A logical
'I' in these bit positions enables the servicing of the corresponding interrupt. These mask bits can be accessed as
an eight bit byte (lNT-MASK - address 8) in the onboard register file. Bit 9 in the PSW is the global interrupt
enable. If this bit is cleared then all interrupts will be
locked out except for the Non Maskable Interrupt (NMI).
Note that the various interrupts are collected in the
INT _ PENDING register even if they are locked out.
Execution of the corresponding service routines will
procede according to their priority when they become enabled. Further information on the interrupt structure of the
8096 can be found in sections 2.5 and 3.6.

V. The V (oVerflow) flag is set to indicate that the operation generated a result which is outside the range that
can be expressed in the destination data type.
VT. The VT (oVerflow Trap) flag is set whenever the V
flag is set but can only be cleared by an instruction which
explicitly operates on it such as the CLRVT or IVT instructions. The operation of the VT flag allows for the
testing for a possible overflow condition at the end of a
sequence of related arithmetic operations. This is normally
more efficient than testing the V flag after each instruction.
C. The C (Carry) flag is set to indicate the state of the
arithmetic carry from the most significant bit of the ALU
for an arithmetic operation or the state of the last bit shifted
out of the operand for a shift. Arithmetic Borrow after a
subtract operation is the complement of the C flag (i.e. if
the operation generated a borrow then C=O).

3.3.2. Condition Flags
The remaining bits in the PSW are set as side effects of
instruction execution and can be tested by the conditional
jump instructions.
Z. The Z (Zero) flag is set to indicate that the operation
generated a result equal to zero. For the add-with-carry
(ADDC) and subtract-with-borrow (SUBC) operations the
Z flag is cleared if the result is non-zero but is never set.
These two instructions are normally used in conjunction
with the ADD and SUB instructions to perform multiple
precision arithmetic. The operation of the Z flag for these
instructions leaves it indicating the proper result for the
entire multiple predsion calculation.

ST. The S1 (STicky bit) set to indicate that during a right
shift a I has been shifted first into the C flag and then
been shifted out. The ST flag is undefined after a multiply
operation. The ST flag can be used along with the C flag
to control rounding after a right shift. Consider multiplying two eight bit quantities and then scaling the result'
down to 12 bits:

N. The N (Negativ~) flag is set to indicate that the op-

MULUB
SHR

3-4

AX,CL,DL
AX,#4

: AX:=CL*DL
; Shift right 4 places

,
MCS®-96 SOFTWARE DESIGN INFORMATION

If the C flag is set after the shift it indicates that the bits
shifted off the end of o~rand were greater-than or equalto one half the least signi,ficant bit (LSB) of the result. If
the C flag is clear after the shift it indicates that the bits
shifted off the end of the operand were less than half the
LSB of the result. Without the ST flag, the rounding
decision must be made on the basis of this information
alone. (Normally the result would be rounded up if the
C ,flag is set.) The ST flag allows a finer resolution in the
rounding decision:

CST
00

Value of the bits shifted off
Value = 0

1 0
1 1

Value

performs a 32 bit addition, and the sequence

SUB
SUBC

performs a 32 bit subtraction. Operations on REAL (i.e.
floating point) variables are not supported directly by the
hardware but are supported by the floating point library
for the 8096 (FPAL-96) which implements a single precision subset of the proposed IEEE standard for floating
p6int operations. The performance of this software is significantly improved by the 8096 NORML instruction
which normalizes a 32-bit variable and by the existence
of the ST flag in the PSW.

Value 'S Y2 LSB
Value = Y2 LSB

In addition to the operations on the various data types,
the 8096 supports conversions between these types.
LDBZE (load byte zero extended) converts a BYTE to a
WORD and LDBSE (load byte sign extended) converts a
SHORT-INTEGER into an INTEGER. WORDS can be
converted to DOUBLE-WORDS by simply clearing the
upper WORD of the DOUBLE-WORD (CLR) and INTEGERS can be converted to LONGS with 1he EXT (sign
extend) instruction.,

> Y2 LSB

Figure 3-2. Rounding Alternatives

Imprecise rounding can be a major source of error in a
numerical calculation; use of the ST flag improves the
options available to the programmer.

The MCS-96 instructions for addition, subtraction, and
comparison do not distinguish between unsigned words
and signed integers. Conditional jumps are provided to
allow the user to treat the results of these operations as
either signed or unsigned quantities. As an example, the
CMPB (compare byte) instruction is used to compare both
signed and unsigned eight bit quantities. A JH (jump if
higher) could be used following the compare if unsigned
operands were involved or a JGT (jump if greater-than)
if signed operands were involved.

3.4 INSTRUCTION SET
The MCS-96 instruction set contains a full set of arithmetic
and logical operations for the 8-bit data types BYTE and
SHORT INTEGER and for the 16-bit data types WORD
and INTEGER. The DOUBLE-WORD and LONG data
types (32 bits) are supported for the products of 16 by 16
mUltiplies and the dividends of 32 by 16 divides and for
shift operations. The remaining operations on 32 bit variables can be implemented by combinations of 16 bit operations. As an example the sequence:
ADO
ADOC

AX,CX
BX,OX

Tables 3-1 and 3-2 summarize the operation of each of
the instructions and Tables 3-3 and 3-4 give the opcode,
byte count, and timing information for each of the instructions.

AX,CX
BX,DX

3-5

MCS I8l·96S0F'TWARE DESIGN INFORMATION
Table 3-1. Instruction SLlmmary
Mnemonic

Flags

Operands

ADD/ADDB

D +-D+A

ADD/ADDB

3
2
2

D +-D+A+C

ADDC/ADDeB
SUB/SUBB
SUB/SUBB

Z N C V VT ST Notes
/ / / / t / / / / t ~ / / / t / / / / t / / / / t ~ / / / t -

Operation (Note 1) .
D +- B+A
D+-D-A
D+-B-A

MUUMULU

3
2
2
2

0, D + 2 +- D

MUUMULU

0, D

MULB/MULUB

0,0+ I+- D

MULB/MULUB

0, D +

- - -

DIV/DIVU

D +- (0, D + 2)/A
0+2
remainder

o +- (0,0

DIVBIDIVUB
AND/ANDB

D<-DandA

AND/ANDB

D<-BandA

XORIXORB

3
2
2

o <- D (excl. or) A
D+-A

SUBC/SUBCB
CMP/CMPB

D+-D-A+C-I

/ /

D-A

+ 2 +- B * A

*A
I+- B * A

D+I

ORiORB

+ I)/A
remainder

- -

LD/LDB

ST/STB

A+-D

LDBSE

o +-A; D

LDBZE

D+-A;D+ 1+-0

PUSH

POP

A +- (SP); SP <-- SP + 2

PUSHF

SP <-- SP - 2; (SP) <-- PSW;
PSW <-- ooooH

1+-0
1<--/

+ I +- SIGN(A)
A

POPF

PSW <-- (SP); SP +- SP + 2

SJMP

PC+-PC+ II-bit offset

UMP

- - -

BR(indirect)

PC +- PC + 16-bit offset
PC +- (A)

SCALL

SP <- SP - 2; (SP) +- PC;
PC +- PC + II-bit offset

LCALL

SP +- SP - 2; (SP) +- PC;
PC +- PC + 16-bit offset

RET

PC +- (SP); SP +- SP + 2

J(conditional)

PC +- PC + 8-bit offset

Jump if C

JNC
Note

Jump if C

=I
=0

/ t - - ?
- - ?
- - ?
?

2
2
3
3
2

- - - / t / / 0 0 - / / 0 0 - / / 0 0 - / / 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

D <- Dor A

. SP <-- SP - 2; (SP)

- - -

3,4
3,4

/ / / / / /

- -

- - - - -

5
5

- - -

5
5

1. If the mnemonic ends in "B", a byte operation is performed, otherwise a word operation is done Operands D, B. and A must conform
to the alignment rules for the required operand type. D and B are locations in the register file; A Can be located anywhere in memory.
2. D, D + 2 are consecutive WORDS in memory; D is DOUBLE·WORD aligned.
3. D. D + 1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to a word.
5. Offset is a 2' s complement numbe.r.

3-6

MCS®·96 SOFTWARE DESIGN INFORMATION
Table 3-2. Instruction Summary

Mnemonic
JE
JNE
JOE

1
1
1

JLT
JOT
JLE
JH
JNH
JV
JNV
JVT
JNVT
JST
JNST
JBS
JBC
DJNZ

1
1
1
1
1
1
I
3
3
1

DECIDECB

NEG/NEGB
INCIlNCB
EXT
EXTB

1
1
1
1
1

NOT/NOTB

CLRlCLRB
SRUSHLB/SHLL
SHRlSHRBISHRL
SHRAISHRAB/SHRAL
SETC
CLRC
CLRVT
RST

DI
EI
NOP
SKIP
NORML
TRAP

Flaas

Operands

1
1

I
2
2
2
0
0
0
0
0
0
0
0
2
0

Operation (Note 1)

Z N C V VT ST Notes
- - - - - 5

Jump if Z =
Jump if Z =
Jump if N =
Jump ifN =
Jump if N =
Jump if N =
Jum~ if C =

1
0
0
1
0 and Z = 0
I or Z = 1
1 and Z = 0
Jump if C = 0 or Z = 1
Jump if V = I
Jum~ifV = 0
Jump if VT = I; Clear VT
Jump if VT = 0; Clear VT
Jump if ST = 1
Jump if ST = 0
Jump if Specified Bit = 1
Jump if Specified Bit = 0
D +- D - I; if D*"O then
PC +- PC + 8-bit offset
D+-D-l
D<-O-D
D+-D+I
D +- D; D+ 2 +- Sign (D)
D +- D; D + 1 +- Sign (D)
D <- Logical Not (D)
D+-O
C +- msb - - - - - I s b +-0
o~ msb - - - - - Isb ~ C
msb~ msb-----Isb~

C +-'1
C+-O
VT<-O
PC +- 2080H
Disable All Interrupts (I +- 0)
Enable All Interrupts (I +- I)
PC+-PC+I
PC+-PC+2
Normalize (See sec 3.13.66)
SP +- SP - 2; (SP) +- PC; PC +(2010R)

- - - - -

- - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - -

0 0 -

- - - - - - - - - - - - -

- / / / / t / / / / t / / / / t / / 0 0 - -

/ /
/ /
1 0
/ ?
/ 0

0 .0 0 0
0 0 -

/ / t / 0 - /
/ / / 0 - /
- - 1 - - - - 0 - - -

0 '0

0
0

5
5
5
5
5

5
5,6
5,6
5

2
3

7
7
7

- - - - - - - - - - - - - - - - - / I 0 - - -

- - - -

5
5
5
5
5
5
5

Note
I. If the mnemonic ends in "B", a byte operation is ,performed, otherwise a word operation is done. Operands 0, B and A must conform
to the alignment rules for the required operand type. 0 and B are locations in the register file; A can be located anywhere in memory.
Offset is a 2' s complement number.
.
Specified bit is one of the 2048 bits in the register file.
The "L" (Long) suffix indicates double-word operation.
Initiates a Reset by pulling RESET low. Software should re-initialize all th~ necessary registers with code starting at 2080H.
The assembler will not accept this mnemonic.

5.
6.
7.
8,
9.

3-7

MCS(!!l·96 SOFTWARE DESIGN INFORMATION
Table 3~3. Opcode and State Time Listing
DIRECT

S:!
Z

INDEXED@
SHORT
LONG

f/)

II:

INDIRECT@
NORMAl:.
AUTO-INC.

IMMEDIATE

(,)
Q.

f/)

1IJf/)
!;(W
I-'!
f/)I-

(,)
Q.

f/)

IIJ

Wf/)
!;(W
I-'!
f/)I-

f/)

Elf/)

IIJIIJ

!;(:E
1-'f/)I-

f/)

Elf/)

Ww
!;(:E

~i=

m
m
0
ARITHMETIC INSTRUCTIONS

(,)

f/)

W
I-

Elf/)

f/)

Elf/)

Ww
!;(:E

~i=

Ww
!;(:E
~ 1-'m f/)IW

ADD

6/11

7/12

6/11

ADD

7/12

8/13

7/12

8/13

ADDB

6/11

7/12

6/11

7/12

ADDB

7/12

8/13

7/12

8/13

ADDe

6/11

7/12

6/11

7/12

ADDeB

6/11

7/12

6/11

'1112

SUB

6/11

7/12

6/11

7/12

SUB

7/12

8/13

7/12

8/B

SUBB

6/11

7/12

6/11

7/12

SUBB

7/12

8/13

7/12

8/13

SUBC

6/11

7/12

6/11

7/12

SUBCB

6/11

7/12

6/il

7/12

CMP

6/11

7/12

6/11

7/12

CMPB

6/11

7/12

6/11

7/12
28/33

MULU

27/32

28/33

27/32

MULU

28/33

29/34

28/33

29/34

MU(,UB

19/24

20/25

19/24

20/25

MULUB

17
18

20/25

21126

20/25

21/26

MUL

31/36

32/37

31136

32137

33/38

MULB

®
®
®
®

MULB

®
®
®
®

MUL

®
®
®
®

22.

32/37

33/38

23/28

24/29

25/30

®
®
®
®

32/37

23/28

24129

24/29

25/30

DIVU

28/32

29/33

28/32

29/33

DIVUB

20/24

21/25

20/24

21/25

DIV

32/36

33/37

32/36

33/37

24/28

25/29

®
®

DIVB

®
®

24/28

25/29

Notes:
@ Long indexed and Indirect + instructions have identical opocodes with Short mdexed and Indirect modes, respectively. The second byte

of instructions using any indirect or indexed addressing mode specifies the exact mode used. If the second byte is even, use Indirect
or Short Indexed, If it is odd, use Indirect + or Long indexed. In all cases the second byte of the instruction always specifies an even
.
(word) location for the address referenced.
0 then
PC ~ PC + disp (sign-extended to 16 bits)
end_if

A$sembly Language Format: DJNZ
Object Code Format: [

breg,cadd

11100000

breg

disp

Bytes:
3
States: Jump Not Taken: 5
Jump Taken:
9

3.13.26. EI- ENABLE INTERRUPTS
Operation: Interrupts are enabled following the execution of the next statement. Interrupt-calls cannot occur immediately following this
instruction.
.
Interrupt Enable (PSW.9)
Assembly Language Format: EI
Object Code Format: [

11111011

Bytes: 1
States: 4

3-36

·MCS®-96 SOFTWARE ,DESIGN INFORMATION

3.13.27. EXT -

SIGN EXTEND INTEGER INTO LONG-INTEGER·

Operation: The low order word of the operand is sign-extended throughout
the high order word of the operand.
if (low word DEST)<8000H then
(high word DEST) ~ 0
else
(high word DEST) ~ OFFFFH
end_if
Assembly Language Format: EXT

Ireg

Object Code Format: [ 00000110

Ireg

Bytes: 2
States: 4

3.13.28. EXTB -

SIGN EXTEND SHORT-INTEGER INTO INTEGER

Operation: The low order byte of the operand is sign-extended throughout
.
the high order byte of the operand.
if (low byte DEST)<80H then
(high byte DEST) ~ 0
else
(high byte DEST) ~ OFFH
end_if
Assembly Language Format: EXTB

wreg

Object Code Format: [ 00010110

Bytes: 2
States: 4

.3-37

wreg

MCSI!>·96 SOFTWARE DESIGN INFORMATION

3.13.29. INC -INCREMENT WORD

Operation: The value of the word operand is incremented by 1.
(DEST) +- (DEST)

Assembly Language Format: INC wreg.
Object Code Format: [ 00000111

wreg

Bytes: 2
States: 4

3.13.30. INCB -INCREMENT BYTE

Operation: The value of the byte operand is incremented by 1.
(DEST) +- (DEST)

+ 1

Assembly Language Format: INCB breg
Object COde Format: [ 00010111

Bytes: 2
States: 4

3-38

breg

MCS®-96 SOFTWARE DESIGN INFORMATION

3.13.31. JBC - JUMP IF BIT CLEAR
Operation: The specified bit is tested. If it is clear (Le., 0), the distance from
the end of this instruction to the target label is added to the program counter, effecting the jump. The offset from the end of this
instruction to the target label must be in the range of - 128 to
+ 127. Ifthe bit is set(Le., 1), control passes to the next sequential
instruction.
if (specified bit) = 0 then
PC +- PC + disp (sign-extended to 16 bits)

Assembly Language Format: JBC

breg,bitno,cadd

Object COde Format: [ 00110bbb

breg

disp

where bbb is the bit number within the specified register.
Bytes:
3
States: Jump Not Taken: 5
Jump Taken:
9

3-39

'MCS~96 SO.FTWARIi.iiDESIGN'I,NFORMATION

3.13.32. JBS - JUMP IF BIT SeT
Operation: The specified bit is tested. If it is set (i.e.;, . 1), the distance from
. the end of this instruction .totJile target label is added to the program counter,effecting th~ jump, The offset from the end of this
instruction to the target label must be in the range of - 128 to
+ 127. If the bit is clear (i.e., 0), control passes to the next sequential instruction.
if (specified bit) = 1 then
.. PC ~ PC + disp (sign-extended to 16 bits)
Assembly Language Format: JBS

breg,bitno,cadd

Object Code Format: [ 00111 bbb

1[breg 1[

disp

where bbb is the bit number within the specified register.
Bytes:
3
States: Jump Not Taken: 5 .
Jump Taken:
9

3.13.33. JC - JUMP IF CARRY FLAG IS SeT
Operation: If the carry flag is set (i.e., 1), the distance from the end of this
instruction to the target label is added to the program counter,
effecting the jump. The offset from the end of this instruction to
the target label must be in the range of -128 to + 127. If the
carry flag is clear (i.e" 0), control passes to the next sequential
instruction,
ifC

=
PC

Assembly Language Format: JC

1 then
~ PC

+ disp (sign-extended to 16 bits)

cadd

Object Code Format: [ 11011011

disp

Bytes:
2
States: Jump Not Taken: 4
,Jump Taken:
8

3-40

,MCS®·96.S0FTWARE DESIGN INF,ORMATION

3.13.34. JE - JUMP IF EQUAL
Operation: If the zero flag is set ,(Le., 1), the distance from the end of this
.instruction to the target label is added to the program counter,
effecting .the jump. The offset from the end of this instruction to
the target label must be in the range of - 128 to + 127. If the zero
flag is clear (Le., 0), control passes to the next sequential
instruction.
ifZ = 1 then
PC +- PC
Assembly Language Format: JE
Object Code Format: [

+ disp (sign-extended te:> 16 bits)

cadd

11011111

disp

Bytes:
2
States: Jump Not Taken: 4
Jump Taken:
8

3.13.35. JGE - JUMP IF SIGNED GREATER THAN: OR EQUAL
Operation: If the negative flag is clear (Le., 0), the distance from the end of
this instruction to the target label is added to the program counter,
effecting the jump. The offset from the end of this instruction to
the target label must be in the range of -128 to + 127. If the
negative flag is set (i.e., 1), control passes to the next sequential
instruction.
if N = o then
PC +- PC

+ disp (sign-extended to 16 bits)

Assembly Language Format: JGE cadd
Object Code Format: [

11010110

disp

Bytes:
2
States: Jump Not Taken: 4
Jump Taken:
8

3-41

MCS~.096

SOFTWARE'DESIGN INFORMATION

3:13.36. JGT - JUMP IF SIGNED GREATER THAN
Operation: If both the negative flag and the zero flag are clear (Le., 0), the
distance from the end of this instruction to the target label is added
to the program counter, effecting the jump. The offset from the
end of this' instruction to,the target label must be in the range of
-128 to + 127. If either the ,negative flag or the zero flag are set
(Le., 1,) control passes to the next sequential instruction.

if N

= 0 AND Z = 0 then
PC +- PC + disp (sign-extended to 16 bits)

Assembly Language Format: JGT cadd

Object Code Format: [

11010010 ] [ disp ]

Bytes:
2
States: Jump Not Taken: 4
Jump Taken:
8

3.13.37. JH - JUMP IF HIGHER (UNSIGNED)
, Operation: If the carry flag is set (i.e., 1), but the zero flag is not, the distance
from the end of this instruction to the target label is added to the
program counter, effecting the jump. The offset from the end of
this instruction to the target label must be in the range of - 128
to + 127. If either ,the carry flag is clear or the zero flag is set,
control passes to the next sequential instruction.

ifC = 1 andZ = then '
PC +- PC + disp (sign-extended to 16 bits)
Assembly Language Format: JH cadd
. Object Code Format: [ 11011001

] [ disp

Bytes: ,
2
States: Jump Not Taken: 4
Jump Taken:
8

3-42

MCS®·96 SOFTWARE DESIGN INFORMATION

3.13.38. JLE -

JUMP IF SIGNED LESS THAN OR EQUAL

Operation: If either the negative flag or the zero flag are set (Le., 1), the
distance from the end of this instruction to the target label is added
to the program counter, effecting the jump. The offset from the
end of this instruction to the target label must be in the range of
- 128 to + 127. If both the negative flag and the zero flag are
clear (Le, 0), control passes to the next sequential instruction.
if N

= 1 OR Z = 1 then
PC? PC + disp (sign-extended to 16 bits)

Assembly Language Format: JLE cadd
Object Code Format: [

I [ disp I

11011010

Bytes:
2
States: Jump Not Taken: 4
Jump Taken:
8

3.13.39. JLT -

JUMP IF SIGNED LESS THAN

Operation: If the negative flag is set (Le., 1), the distance from the end of
thiS instruction to the target label is added to the program counter,
effecting the jump. The offset from the end of this instruction to
the target label must be in the range of - 128 to + 127. If the
negative flag is clear (i.e., 0), control passes to the next sequential
instruction.
if N = 1 then
PC ~ PC
Assembly Language Format: JLt
Object Code Format: [

+ disp (sign-extended to 16 bits)

cadd
11011110 ] [ disp

Bytes:
2
States: Jump Not Taken: 4
Jump Taken:
8

3-43

MCS®~96 SOFTWARE DESIGN INFORMATION

3.13.40. JNC -

JUMP IF CARRY FLAG IS CLEAR
Operation: If the carry flag is clear (i.e., 0), the distance from the end of this
instruction to the target label is added to the program counter,
effecting the jump. The offset from the end of this instruction to
the target label must be in the range of - 128 to + 127. If the
carry flag is set (i.e., 1), control passes to the next sequential
instruction.
if C = 0 then
PC ~ PC

Assembly Language Format: JNC
Object Code Format: [

+ disp (sign-extended to 16 bits)

cadd

11010011

] [ disp

]

Bytes:
2
States: Jump Not Taken: 4
8
Jump Taken:.

3.13.41. JNE -

JUMP IF NOT EQUAL
Operation: If the zero flag is clear (i.e., 0); the distance from the end of this
instruction to the target label is added to the program counter,
effecting the jump. The offset from the end of this instruction to
the target label must be in the range of - 128 to + 127. If the zero
flag is set (i.e., 1), control passes to the next sequential instruction.
if Z = 0 then
PC~ PC

Assembly Language Format: JNE
Object Code Format: [

+ disp (sign-extended to

cadd

11010111] [ disp

]

Bytes:
2
States: Jump Not Taken: 4
Jump Taken:
8

3-44

16 bits)

MCS®-96 SOFTWARE DESIGN INFORMATION

3.13.42. JNH -

JUMP IF NOT HIGHER (UNSIGNED)
Operation: If either the carry flag is clear (i.e., 0), or the zero flag is set (i.e.,
1), the distance from the end of this instruction to the target label
is added to program counter, effecting the jump. The offset from
the end of this instruction to the target label must be in the range
of -128 to + 127. If the carry flag is set (i.e., 1), or the zero flag
is not, control passes to the next sequential instruction.
if C = 0 OR Z = 1 then.
PC ~ PC + disp (sign-extended to 16 bits)

Assembly Language Format: JNH
Object Code Format: [

cadd

11010001

disp

Bytes:
2
States: Jump Not Taken: 4
Jump Taken:
8

3.13.43. JNST -

JUMP IF STICKY BIT IS CLEAR
Operation: If the sticky bit flag is clear (i.e., O), the distance from the end of
this instruction to the target label is added to the program counter,
effecting the jump. The offset from the end of this instruction to
the target label must be in the range of - 128 to + 127. If the
sticky bit flag is set (i.e., 1), control passes to the next sequential
instruction.
if ST = 0 then
PC ~ PC

+ disp (sign-extended to 16 bits)

Assembly Language Format: JNST cadd
Object Code Format: [

11010000 ][ disp

Bytes:
2
States: Jump Not Taken: 4
Jump Taken:
8

3-45

MCS®·96 SOfTWARE DESIGN INFORMATION

3.13.44. JNV -

JUMP IF OVERFLOW FLAG IS CLEAR
Operation: If the overflow flag is clear (Le., 0), the distance from the end of
this instruction to the target label is added to the program counter,
effecting the jump. The offset from the end of this instruction to
the target label must be in the range of - 128 to + 127. If the
overflow flag is set (Le., 1), control passes to next sequential
instruction.
ifV=Othen
PC ~ PC

di$p (sign-extended to 16 bits)

Assembly Language Format: JNV cadd
Object Code Format: [

11010101

][ disp

B~es:
2
States: Jump Not Taken: 4
Jump Taken:
8

3.13.45. JNVT -

JUMP IF OVERFLOW TRAP IS CLEAR
Operation: If the overflow trap flag is clear (Le., 0), the distance from the end
of this instruction to the target label is added to the program
counter, effecting the jump. The offset from the end of this instruction to the target label must be in the range of -128 to
+ 127. If the overflow trap flag is set (Le., 1), control passes to
the next sequential instruction.
if VT = 0 then
PC ~ PC

+ disp (sign-extended to 16 bits)

Assembly Language Format: JNVT cadd
Object Code Format: [

11010100

disp

B~es:
2
States: Jump Not Taken: 4
Jumps Taken:
8

3-46

MCS®~96. SOFTWARI:

3.13.46. JST -

DESIGN INFORMATION

JUMP IF STICKY BIT IS SET
Operation: If the sticky bit flag is set (i.e., 1), the distance from the end of
this instruction to the target label is added to the program counter,
effecting the jump. The offset from the end of this instruction to
the target label must be in the range of -128 to + 127. If the
sticky bit flag is clear (i.e., 0), control passes to the next sequential
instruction.
if ST = 1 then
PC ....... PC

Assembly Language Format: JST
Object Code Format: [

disp (sign-extended to 16 bits)

cadd

11011000

disp

Bytes:
2
States: Jump Not Taken: 4
Jump Taken:
8

3.13.47. JV -

JUMP IF OVERFLOW FLAG IS SET
Operation: If the overflow flag is set (i.e., 1), the distance from the end of this
instruction to· the target label is added to the program counter,
effecting the jump. The offset from the end of this instruction to
the target label must be in the range of - 128 to + 127. If the
overflow flag is clear (i.e., 0), control passes to the next sequential
instruction.
if V = 1 then
PC ....... PC

Assembly Language Format: JV
ObjectCodeFormat: [

disp (sign-extended to 16 bits)

cadd

11011101

][ disp

Bytes:
2
States: Jump Not Taken: 4
Jump Taken:
8

3-47

MCS®·96SoFrWARE DESIGN ~INFORMATION

3.13.48. JVT -

JUMP IF OVERFLOW TRAP IS SET
Operation: If the overflow flag is set (Le., 1), the distance from the end of this
instruction to the target label is added to the program counter,
effecting the jump. The offset from the end of this instruction to
the target label must be in the range of - 128 to + 127. If the
overflow trap flag is clear (Le., 0), control passes to the next
sequential instruction.
if VT = 1 then
PC ~ PC

Assembly Language Format: JVT
Object Code Format: [

+ disp (sign-extended to 16 bits)

cadd

11011100 ] [ disp

]

Bytes:
2
States: Jump Not Taken: 4
Jump Taken:
8

3.13.49. LCALL -

LONG CALL
Operation: The contents of the program counter (the return address) is
pushed onto the stack. Then the distance from the end of this
instruction to the target label is added to the program counter,
effecting the call. The operand may be any address in the entire
address space.
SP~SP-2

(SP) ~ PC
PC ~PC + disp
Assembly Language Format: LCALL cadd
Object Code Format: [

11101111

] [ disp-Iow

Bytes:
3
States: Onchip stack: 13
Offchip stack: 16

3-48

][

disp-hi

]

· MCS~-96 SOFTWARE DESIGN INFORMATION

3.13.50. LD -

LOAD WORD

Operation:. The value of the source (rightmost) word operand is stored into
the destination (leftmost) operand.
(DEST) - (SRC)
Assembly Language Format:

LD
Object Code ForJ;nat: [

DST
wreg,

101 OOOaa

SRC
waop

waop

wreg

Bytes: 2+BEA
States: 4+CEA

3.13.51. LDB -

LOAD BYTE.
Operation: The value of the source (rightmost) byte operand is stored into
the destination (leftmost) operand.

(DEST) - (SRC)
Assembly Lang~age Format:

DST
LDB . breg,

Object Code Format: [

1011 OOaa

SRC
baop

Bytes: 2 + BEA
States: 4 + CEA

3-49

baop

breg

MCS®·96 SOFTWARE DESIGN INFORMATION

3.13.52. LDBSE - LOAD INTEGER WITH SHORT·INTEGER
Operation: The value of the source (rightmost) byte operand is sign-extended
and stored into the destination (leftmost) word operand.
(low byte DEST) ~ (SRC)
if (SRC) < 80H'then
(high byte DEST) ~ 0
else
(high byte DEST) ~ OFFH
end_if
.

Assembly Language Format:
LDBSE

DST
wreg,

Object Code Format: [ 101111 aa

SRC
baop
baop

wreg

Bytes: 2 + BEA
States: 4+CEA

3.13.53. LDBZE -

LOAD WORD WITH BYTE
Operation: The value of the source (rightmost) byte operand is zero-extended
and stored into the destination (leftmost) word operand.
(low byte DEST) ~ (SRC)
(high byte DEST) ~ 0

Assembly Language Format:
lDBZE

DST
wreg,

Object Code Format: [ 101011 aa

Bytes: 2 + SEA
States: 4+CEA

3-50

SRC
baop
baop

wreg

MC.S®"96 SOFTWARE DESIGN INf.ORMATION

3.13.54. LJMP - LONG JUMP
Operation: The distance from the end of this instruction to the target label
is added to the program counter, effecting the jump. The operand
may be any address in the entire address space.
PC

~PC

+ disp

Assembly Language Format: LJMP cadd
Object Code Format: [ 11100111

] [ disp-Iow ] [ disp-hi

]

Bytes: 3
States: 8

3.13.55. MUL (Two Operands) - MULTIPLY INTEGERS
Operation: The two INTEGER operands are multiplied using signed arithmetic and the 32-bit result is stored into the destination (leftmost)
LONG-INTEGER operand. The sticky bit flag is undefined after
the instruction is executed.
(DEST)

MUL

DST
Ireg,

Assembly Language Format:

(DEST) • (SRC)
SRC
waop

Object Code Format: [ 11111110 ][ 011011 aa ][ waop ][ Ireg ]
Bytes: 3 + BEA
States: 29 + CEA

3-51

P.i'lCS®~96,S'OFTWARI: DESIGN INFORMATION

3.13.56. MUL (Three Operands) -

MULTIPLY INTEGERS

Operation: ' The second and third INTEGER operands are multiplied using
signed arithmetic and the 32-bit result is stored into the destination
(leftmost) INTEGER operand. The sticky bit flag is undefined after
the instruction is executed.
(PEST) +- (SRC1) * (SRC2)
Assembly Language Format:
MUL
Object Code Format: [

DST
Ireg,

11111110

SRC1
wreg,

SRC2
waop

010011aa

waop

wreg

Ireg

Bytes: 4 + BEA
States: 30 + CEA

3.13.57. MULB (Two Operands) ...... MULTIPLY SHORHNTEGERS
Operation: The two SHORT-INTEGER operands are multiplied using signed
arithmetic and the i 6-bit result is stored into the destination (leftmost) INTEGER operand. The sticky bit flag is undefined after the
instruction is executed.
(DEST) +- (DEST) * (SRC)
Assembly Language Format:
MULB
Object Code Format: [

DST
wreg,

11111110

SRC
baop

Bytes: 3+BEA
States: 21 + CEA

3-52

011111 aa

baop

wreg

MCS®·96 SOFTWARE DESIGN INFORMATION

3.13.58. MULB (Three Operands) -

MULTIPLY SHORt~INTEGERS'

Operation: The second and third SHORT·INTEGER operands are multiplied
using signed arithmetic and the 16·bit result Is stored into the
destination (leftmost) INTEGER operand. The sticky bit flag is
undefined after the instruction is executed.
(DEST)

Assembly Language Format:
MUlB

(SRC1) • (SRC2)

DST
Wreg,

Object Code Format: [ 11111110

SRC1
breg

SRC2
baop

010111aa

baop

breg

wreg

Bytes: 4 + BEA
States: 22 + CEA

3.13.59. MULU (Two Operands) -

MULTIPLY WORDS

Operation: The two WORD operands are multiplied using unsigned arithmetic
and the 32·bit result is stored into the destination (leftmost) DOU·
, BlE·WORD operand. The sticky bit flag is undefined after the
instruction is executed.
(DEST)

Assembly ~anguage Format:

(DEST) • (SRC)

DST
MUlU· Ireg,

Object Code Format: [ 011011 aa

SRC
waop

Bytes: 2 + BEA'
States: 25 + CEA

3-53

waop

Ireg

,; MCS:IRl·96·S0FTWARl: Dl:SI,GN INFORMATION

3.13.60. MULU (Three Ope~nds)-MULTIPLY WORDS
• ·Operatlon:The second an,d third WORP operands are multiplied using unsigned arithmetic and the 32-bit result is stored into the destination
(leftmost) DOUBLE-WORD operand. The sticky bit flag is undefined after the instruction is executed.
(DEST)< - (SRC1) * (SRC2)
DST
Ireg,

Assembly Language Format:
MULU

Object Code Format: [ 010011 aa

SRC1
wreg,

waop

SRC2
waop

wreg

Ireg

Bytes: 3 + BEA
States: 26 + CEA

3.13.61. MULUB (Two Operands) -

MULTIPLY BYTES

Operation: The two BYTE operands are multiplied using unsigned arithmetic
and the WORD result is stored into the destination (leftmost) operand. The sticky bit flag is undefined after the instruction is
executed.
(DEST)
Assembly Language Format:
MULUB
Object Code Format: [

(DEST) * (SRC)
DST
wreg,

011111 aa

SRC
baop

Bytes: 2+BEA
States: 17 + CEA

3-54

baop

wreg

MCS®·96 SOFTWARE DESIGN JNFORMATION

3.13.62. MULUB (Three Operands) -

MULTIPLY BYTES

Operation: The second and third BYTE operands are multiplied using unSigned arithmetic and the WORD result is stored into the destination (leftmost) operand. The sticky bit flag is undefined after the
instruction is executed.
/
(DEST) +- (SRC1) • (SRC2)
Assembly Language Format:
MULUB

DST
wreg,

SRC1
breg,

SRC2
baop

J [ baop J [ breg J [ wreg J

Object Code Format: [ 010111 aa

Bytes: 3+BEA
States: 18 + CEA

3.13.63. NEG -

NEGATE INTEGER
Operation: The value of the INTEGER operand is negated.
(DEST) +- - (DEST)

Assembly Language Format: NEG wreg
Object Code Format: [ 00000011.

J [ wreg J

Bytes: 2
States: 4

3-.55

'MCSI!<-96 SOFTWARE ,DESIGN INFORMATION

3.13.64. NEGB -

NEGATE SHORT-INTEGER'

Operation: The

va.lu~

(DEST) -

ofthe SHORT-INTEGER operand is negated.
- (DEST)

Assembly Language Format: NEGB breg
Object Code Format: [ 00010011

breg

Bytes: 2
States: 4

3.13.65. NOP -

NO OPERATION

Operation: Nothing is done. Control passes to the next sequential instruction.
Assembly Language Format: NOP
Object Code. Format:.[ 11111101
Bytes: 1
States: 4

3·56

MCS®-96 SOFTWARE DESIGN INFORMA110N

3.13.66. NORML - NORMALIZE LONG-INTEGER
Operation: The LONG-INTEGER operand is normalized; Le., it is shifted to
the left until its most significant bit is 1. If the most significant bit
is still 0 after 31 shifts, the process stops and the zero flag is set.
The number of shifts actually performed is stored in the second
operand.

(COUNT) -0
do while (MSB(DEST) = 0) AND «COUNT) < 31)
(PEST) - (DEST) * 2
(COUNT) - (COUNT) + 1
end_while
Assembly Language Format: NORML Ireg,breg
Object Code Format: [ 00001111

] [ breg ] [ Ireg ]

Bytes: 3
States: 8 + No. of shifts performed

3.13.67. NOT - COMPLEMENT WORD
Operation: The value of the WORD operand is complemented: each 1 is
,replaced with a 0, and each 0 with a 1.

(DEST) - NOT(DEST)
Assembly Language Format: NOT wreg
Object Code Format: [ 00000010 ] [ wreg ]

Bytes: 2
States: 4

3-57

1MCS®-SS 'SOFTWARE.DESIGN INFORMATION

3.13.S8. NOTB -

COMPLEMENT BYTE

" '

oper~nd i$·complemented: each 1 is replaced with a 0, and each 0 .with a 1.

Opet:atiQn: The. value of the. BYTE

,(DEST) - NOT .(DE~:r)

Assembly Language Format: NOTB breg
Object Code Format: [. 0001Q010

~reg

Bytes: 2
States:' 4

3.13.S9. OR -

LOGICAL OR WORDS.

Operation: The source (rightmost) WORD is ORed with the destination (leftmost) WORD operand. Each bit is set to 1 if the corresponding
bit in either the source operand or the destination operand is 1.
The result replaces the original destination operand.
(DEST) - (DEST) OR (SRC)
As~em~ly La~g~age Format.:.

DST
wreg~'

Object Code Format: [ 100000aa

SRC
waop

Bytes: 2+BEA
States: 4+CEA

3-58

waop

wreg

·MCS®-96 SOFTWARE DESIGN INFORMATION

3.13.70. ORB -

LOGICAL OR BYTES
Operation: The source (rightmost) BYTE operand is ORed with the destination (leftmost) BYTE operand. Each bit is set to 1 if the corresponding bit in either the source operand or the destination
operand was 1. The result replaces the original destination
operand.
(DEST) +- (DEST) OR (SRC)

Assembly Language Format: ORB
Object Code Format: [

breg,baop

1001 OOaa

][

baop

][

breg

Bytes: 2 + BEA
States: 4+CEA

3.13.71. POP -

POP WORD
Operation: The word on top of the stack is popped and placed at the destination operand.
(DEST) +- (SP)
SP +-SP + 2

Assembly Language Format: POP
Object Code For",a~: [

waop

110011 aa

][

waop

]

Bytes:
1 + BEA
States: Onchip Stack: 12+CEA
Offchip Stack 14 + CEA

§F~S~

rrl:I~ITI

3-59

MCS®·96SGIITWARE DESIGN INFORMATION

3.13.72. POPF -

POP FLAGS
Operation: The word on top of the stack is popped and placed in the PSW.
Interrupt calls cannot occur immediately following this instruction.
(PSW) -(SP)
SP -SP + 2

Assembly Language Format: POPF
Object Code Format: [

11110011

Bytes:
1
States: Onchip Stack: 9
Offchip Stack: 13

ST
j

3.13.73. PUSH -

PUSH WORD
Operation: The specified operand is pushed onto the stack.
SP-SP - 2
(SP) - (DEST)

Assembly Language Format: PUSH
Object Code Format: [

waop

11001 Oaa

waop

Bytes:
1+BEA
States: Onchip Stack: 8 + CEA
Offchip Stack: 12 + CEA

§FI8Q' Affect?

rrl:I~ITI

3-60

MCS®·96 SOFTWARE DESI~N INFORMATION

3.13.74. PUSHF -

PUSH FLAGS
Operation: The PSW is pushed on top of the stack, and then set to all zeroes.
This implies that all interrupts are disabled. Interrupt-calls cannot
occur immediately following this instruction.
SP~SP

(SP)

- 2

~PSW

PSW~O

Assembly Language Format: PUSHF
Object Code Format: [

11110010

Bytes:
1
States: Onchip Stack: 8
Offchip Stack: 12

3.13.75. RET -:-" RETURN FROM SUBROUTINE
Operation: The PC is popped off the top of the stack.
PC

~(SP)

SP~SP

Assembly Language Format: RET
Object Code Format: [

1111 0000

Bytes:
States: Onchip Stack: 12
Offchip Stack: 16

C0A~ Affect~

rrl~I~ITI

MCS®·96 SOFTWARE..DESIGN INFORMATION

3.13.76. RST -

RESET SYSTEM
Operation: The PSW is initialized to zero, and the PC is initialized to 2080H.
The 1/0 registers are set to their initial value (see section 2.15.2,
"Reset Status"). Executing this instruction will cause a pulse to
appear on the reset pin of the 8096.
PSW~O

PC~2080H

Assembly Language Format: RST
Object Code Format: [

11111111

Bytes: 1
States: 16

3.13.n. SCALL - SHORT CALL
Operation: The contents of the program counter (the return address) is
pushed onto the stack. Then the distance from the end of this
instruction to the target label is added to the program cQunter,
effecting the call. The offset from the end of this instruction to the
target label must be in the range of -1024 to + 1023 inclusive.
SP~SP-2

(SP) ~PC
PC ~ PC + disp (sign-extended to 16 bits)
Assembly Language Format: SCALL

cadd

Object Code Format: [ 00101 xxx

disp-Iow,

where xxx holds the three high-order bits of displacement.
Bytes:
2
States: Onchip Stack: 13
Offchip Stack: 16

3-62

,MCS®..gs SOFTWAAE.D.ESIGN INFORMATroN

3.13.78. SETC - SET CARRY FLAG
Operation: The carry flag is set.
C +-1

Assembly Language Format: SETC
Object Code Format: [ 11111001
Bytes: 1
St~tes:

3.13.79. SHL - SHIFT WORD LEFT
Operation: The destination (leftmost) word operand is shifted left as many
times as specified by the count (rightmost) operand. The count
may be specified eit):ler as an immediate value in the range of 0
to 15 inclusive, or as the content of any register, the address of
which is 16. to 255. The right bits of the result are filled with zeroes.
The last bit shifted out is saved in the carry flag.
Temp +- (COUNT)
do while Temp <>0
C +- High order bit of (DEST)
(DEST) +- (DEST)*2
Temp +- Temp - 1
end_while

Assembly Language Format:

SHL

wreg,#count

SHL

wreg,breg

Object Code Format: [ 00001001

cnt/breg

wreg

Bytes: 3
States: 7 + No. of shifts performed
note: 0 place shifts take 8 states.

3-63

MCS®·96 SOFTWARE 0
C +- High order bit of (DEST)
(DES1) +- (DEST)*2
Temp +- Temp - 1
end_while

A81embly Language Format:

SHLB

breg,#count

SHLB

breg,breg

Object Code Format: [

00011001

][

cnt/breg

][

breg

Bytes: 3
States: 7 + No. of shifts performed
note: 0 place shifts take 8 states.

3·64

MCS®..ge,SOFTWARE DESIGN INFORMATION

3.13.81. SHLL - SHIFT DOUBLE-WORD LEFT
Operation: The destination (leftmost) double-word operand is shifted left as
many times as specified by the count (rightmost) operand. The
count may be specified either as an immediate value in the range
of 0 to 15 inclusive, or as the content of any register, the address
of which is 16 to 255. The right bits of the result are filled with
zeroes. The last bit shifted out is saved in the carry flag.
Temp - (COI,JNT)
do while TemP <> 0
.
C - High order bit of (DEST)
(OEST) - (OEST)*2
Temp - Temp - 1
end_while

Assembly Language Format:

SHLL

Ireg ,#count

SHLL

Ireg,breg

Object Code Format: [ 00001101

] [ cnt/breg

][

Ireg

Bytes: 3
States: 7 + No. of shifts performed
nate: 0 place shifts take a, states.

3-65

· MOS®·96 SOF1WARE·OESIGN INFORMATION

3.13.82. SHR - LOGICAL RIGHT SHIFT WOAD
Operation: The destination (leftmost) word operand is shifted right as many
times as specified by tM count (rightmost) operand. The count
maybe specified either as an immediate value in the range of 0
to 15 inclusive, or as the content of any register,_ the address of
which is 16 to 255. The left bits of the result are filled with zeroes.
The last bit shifted out is saved to the carry. The sticky bit flag
is cleared atthe beginning of the Instruction, and set if at any time
during the shift a 1 is shifted first into the carry flag, and a further
shift cycle occurs.
Temp +- (COUNT)
do while Temp <> 0
C +- Low order bit of (DEST)
(DEST) +- (DEST) / 2 where / is unsigned division
Temp +- Temp - 1
end_while
Assembly Language Format:

SHR wreg,#Count
or
SHR wreg,breg_

Object Code Format: [ 00001000

cnt/breg

wreg

Bytes: 3
States: 7 + No. of shifts performed'
note: 0 place shifts take 8 states.

3-66

MCS-96 SOFTWARE DESIGN INFORMATldN
3.13.83. SHRA - ARITHMETIC RIGHT SHIFT WORI)
Operation: The destination (leftmost) word operand is shifted right as many
times as specified by the count (rightmost) operand. The count
may be specified either as an immediate value in the range of 0
to 15 inclusive, or as the content of any register, the address of
which is 16 to 255. If the original high order bit value was 0, zeroes
are shifted in. If the value was 1, ones are shifted in. The last bit
shifted out is saved in the carry. The sticky bit flag is cleared at
the beginning of the instruction, and set if at any time during the
shift a 1 is shifted first into the carry flag, and a further shift cycle
occurs.
Temp - (COUNT)
do while Temp <> 0
C - Low order bit of (DEST)
(DEST) - (DEST) / 2 where / is Signed division
Temp - Temp - 1
end_while

Assembly Language Format:

SHRA

wreg,#count

SHRA

wreg,breg

Object Code Format: [ 00001010

cnVbreg

wreg

Bytes: 3
States: '7 + No. of shifts performed
note: 0 place shifts take 8 states.

3-67

3.13.84. SHRAB -

ARITHMETIC RIGHT SHIFT BYTE
O\,eratlon: The. destination (leftmost) byte operand .is shifted right as many
times.as specified by the count (rightmost) operand. The count
may be specified either as an immediate value in the range of O.
to 15 inclusive, or as the content of any register, the address of
which is 16 to 255. If the original high order bit value was 0, zeroes
are shifted in. If that value was 1, ones are shifted In. The last bit
shifted out is saved in the carry. The sticky bit flag is cleared at
the beginning of the instruction, and set if at any time during the
shift a 1 is shifted first into the carry flag, and a further shift cycle
occurs.
Temp ~ (COUNT)
do while Temp <> 0
C, = Low order bit of (DEST)
(DEST) ~ (DEST) I 2 where lis signed division
Temp ~ Temp - 1
end_while

Assembly Language Format:

SHRAB

breg,#count

SHRAB

breg,breg

Object Code Format: [

00011010

cntlbreg

breg

Bytes: 3
.
States: 7 + No. of shifts performed
. note: 0 place shifts take 8 states.

3-68

MCS®-96 SOFTWARE DESIGN INFORMATION

3.13.85. SHRAL -

ARITHMETIC RIGHT SHIFT DOUBLE-WORD
Operation: The destination (leftmost) double-word operand is shifted right as
many times as specified by the count (rightmost) operand. The
count may be specified either as an immediate value in the rangeof 0 to 15 inclusive, or as the content of any register, the address
of which is 16 to 255. If the original high order bit value was 0,
zeroes are shifted in. If the value was 1, ones are shifted in. The
sticky bit is cleared at the beginning of the instruction, and set if
at any time during the shift a 1 is shifted first into the carry flag,
and a further shift cycle occurs.
Temp - (COUNT)
do while Temp < > 0
C - Low order bit of (DEST)
(DEST) - (DEST) / 2 where/is signed division
Temp - Temp - 1
end_while

Assembly Language Format:

SHRAL

Ireg,#count

SHRAL

Ireg,breg

Object Code Format: [

OQ001110

cnt/breg

Ireg

Bytes: 3
States: 7 + No. of shifts performed
note: 0 place shifts take 8 states.

3-69

MCS®-96· SOFTWARE· DESIGN INFORMATION

3.13.86. SHRB -

LOGICAL RIGHT SHIFT BYTE
Operation: The destination (leftmost) bYte operand is shifted right as many
times as specified by the count (rightmost) operand. The count
may be specified either as an immediate value in the range of 0
to 15 inclusive, or as the content of any register, the address of
which is 16 to 255. The left bits of the result are filled with zeroes.
The last bit shifted out is saved in the carry. The sticky bit flag is
cleared at the beginning of the instruction, and set if at any time
during the shift a 1 is shifted first into the carry flag, and a further
shift cycle occurs.
Temp +- (COUNT)
do while Temp < > 0
C +- Low order bit of (DEST)
(DEST) +- (DEST) / 2 where/is unsigned division
Temp +- Temp - 1
end_while

Assembly Language Format:

SHRB

breg,#count

SHRB

breg,breg

Object Code Format: [

00011000

cnt/breg

breg

Bytes: 3
States: 7 + No. of shifts performed
note: 0 place shifts take 8 states.

3-70

MCS®·96 SOFTWARE DESIGN INFORMATION

3.13.87. SHRL -

LOGICAL RIGHT SHIFT DOUBLE·WORD
Operation: The destination (leftmost) double-word operand is shifted right as
many times as specified by the count (rightmost) operand. The
count may be specified either as an immediate value in the range
of 0 to 15 inclusive, or as the content of any register, the address
of which is 16 to 255. The left bits of the result are filled with
zeroes. The last bit shifted out is saved in the carry. The sticky
bit flag is cleared at the beginning of the instruction, and set if at
any time during the shift a 1 is shifted first into the carry flag, and
a further shift cycle occurs.
Temp - (COUNT)
do while Temp < > 0
C - Low order bit of (DEST)
(DEST) - (DEST) / 2 where/is unsigned division
Temp - Temp - 1
end_while

Assembly Language Format:

SHRL

Ireg,#count

SHRL

Ireg,breg

Object Code Format: [

00001100

cnt/breg

Ireg

Bytes: 3 '
States: 7 + No. of shifts performed
note: 0 place shifts take 8 states.

3-71

MCS®·96 SOFTWARE DESIGN INf:ORMATION
3.13.88. SJMP - SHORT JUMP
Operation: The distance from the end of this instruction to the target label
is added to the program counter, effecting the jump. The offset
from the end of this instruction to the target label must be in the
range of - 1024 to + 1023 inclusive.
PC - PC
Assembly Language Format: SJMP

+ disp (sign-extended to 16 bits)

cadd

Object Code Format: [ 00100xxx

disp-Iow

where xxx holds the three high order bits of the displacement.
Bytes: 2
States: 8

3.13.89. SKIP - TWO BYTE NO·OPERATION
Operation: Nothing is done. This is actually a two-byte NOP where the second
byte can be any value, and is simply ignored. Control passes to
the next sequential instruction.
Assembly Language Format: SKIP

breg

Object Code Format: [ 00000000

Bytes: 2
States: 4

3·72

breg

MCS®·96 SOFTWARE DESIGN INFORMATION
3.13.90. ST - STORE WORD
Operation: The value of the leftmost word operand is stOred into the rightmost
operand.
(DEST) ~ (SRC)

Assembly Language Format:
ST

SRC
wreg,

DST
waop

Object Code Format: [ 110000aa ] [ waop ] [ wreg ]
Bytes: 2+BEA
States: 4 + CEA

3.13.91. STB - STORE BYTE
Operation: The value of the leftmost byte operand is stored into the rightmost
operand.
(DEST) ~ (SRC)

Assembly Language Format:
STB

SRC
breg,

OST
baop

Object Code Format: [ 110001aa ] [ baop ] [ breg ]
Bytes: 2 + BEA
States: 4+CEA

3-73

MCS®·96 SOFl'WARE DESIGN. INFORMATION

3.13.92. SUB (Two Operands) -

SUBTRACT WORDS

O.peratlon: The source (rightmost) word operand is subtracted from the destination (leftmost) word .operand, and the result is stored in the
destination. The carry flaQ is set as complement of borrow.
(DEST)
Assembly Language Format:
SUB

(DEST) -

DST
wreg,

(SRC)

SRC
waop

Object Code Format: [ 01101 Oaa

waop

wreg

Bytes: 2+BEA
States: 4+CEA

3.13.93. SUB (Thre$ Operands) -

. SUBTRACT WORDS
'

Operation: The source (rightmost) won:! operand is subtracted from the second word operand, and the result is stored in the destination (the
leftmost operand). The carry flag is set as complement of borrow.
(DEST)
Assembly Language Format:
SUB

(SRC1) -

DST
wreg,

Object Code Format: [ 01001 Oaa

(SRC2)

SRC1
wreg,

Bytes: 3+ BEA
States: 5+CEA

3-74

waop

SRC2,
waop

Swreg

Dwreg

MCS®·96S()FTWARE DESIGN INFORMATION

3.13.94. SUBB (Two Operands) -

SUBTRACT BYTES

OperatIon: The source (rightmost) byte is subtracted from the destination
(leftmost) byte operand, and the result is stored in the destination.
The carry flag is set 'as complement of borrow.
(DEST)

(DEST) -

(SRC)

DSTSRC
breg,
baop

Assembly Language Format:
SUBB

Object Code Format: [ 011110aa

baop

breg

Bytes: 2 + BEA
States: 4 + CEA

3.13.95. SUBB (Three Operands) -

SUBTRACT BYTES

Operation: The source (rightmost) byte operand is subtracted from the destination (leftmost) byte operand, and the result is stored in the
destination. The carry flag is set as complement of borrow.
(DEST)
Assembly Language Format:

(SRC1) -

DST
SUBB breg,

Object Code Format: [ 01011 Oaa

(SRC2)

SRC1
Sbreg

Bytes: 3 + BEA
States: 5+CEA

3-75

Mop

SRC2
baop

1[Sbreg

) [ Dbreg

MC~~-96$OF:lWARE. DeSIGN INfPRMATION

3.13.96. SUBC -

SUBTRACT WORDS ,WITH a.ORROW
Operation: The source (rightmost) word operandi.s subtracted from the des. tin~tion (I~ftmost) word oper~nd. If the carry flag was clear, 1 is
subtracted from .thE! abt;>ve result. The result replaces the original·
destination operand. The carry flag is set as complement of
borrow.

(DEST)
Assembly Language Format:

SUBC
Object Code Format: [

(DEST) -

DST
wreg;

10101 Oaa

(SRC) -

(1-C)

SRC
weop

1[.

waop

wreg

Bytes: 2 + BEA
States: 4 + CEA

3.13.97. SUBCB- SUBTRACT BYTES WITH BORROW
Operation: The source (rightmost) byte operand is subtracted from the destination (leftmost) byte operand. If the carry flag was clear, 1 is
subtracted from the above result. The result replaces the original
destination operand. The carry flag is set as complement of
borrow.

(DEST)
Assembly Language Format:

SU8CB
Object Code Format: [

(DEST) DST
breg,

10111 Oaa

(SRC) SRC
baop

baop

Bytes: 2+BEA
States: 4 + CEA .

3-7q

(1-C)

breg

MCS®·96 SOFTWARE DESIGN INFORMATION

3.13.98. TRAP -

SOFTWARE TRAP
Operation: This instruction causes an interrupt-call which is vectored through
locatioh 2010H. The operation of this instruction is not effected
by the state of the interrupt enable flag in the PSW (I). Interruptcalls cannot occur immediately following this instruction. This instruction is intended for use by Intel provided development tools.
These tools will not support user-application of this instruction.
SP~SP - 2
(SP) ~PC
PC ~(2010H)

Assembly Language Format: This instruction is not supported by revision 1.0 of the 8096 as·
sembly language.
Object Code Format: [

11110111

]

Bytes:
States: Onchip Sta.ck: 21
Offchip Stack: 24

3.13.99. XOR -

LOGICAL EXCLUSIVE·OR WORDS
Operation: The source (rightmost) word operand is XORed with the desti·
nation (leftmost) word operand. Each bit is set to 1 if the corre·
sponding bit in either the source operand or the destination op·
erand was 1, but not both. The result replaces the original
destination operand.
(DEST)

XOR

DST
wreg,

Assembly Language Format:

Object Code Format: [

(DEST) XOR (SRC)

100001 aa

SRC
waop
] [ waop

] [ wreg

Bytes: 2 + BEA
States: 4 + CEA

[ili~9S
Z
j

N
j

Affected

1TI

I C0 I V0 IVT3-77

]

MCS®-96 SOFTWARE DESIGN INFORMATION

3.13.100. XORB - LOGICAL EXCLUSIVE-OR BYTES
Operation: The source (rightmost) byte operand is XOAed with the destination (leftmost) byte operlind. Each bit is set to 1 if the corresponding bit in either the source operand or the destination operand was 1, but not both. The result replaces the original
destination operand.
(DEST)

Assembly Language Format:
XOAB

(DEST) XOA (SAC)

DST
breg,

SAC
baop

Object Code Format: [ 100101aa ][ baop ][ breg
Bytes: 2 + BEA
States: 4+CEA

3-78

MCS®,96 Hardware
Design Information

CHAPTER 4
,
MCS®·96 HARDWARE DESIGN INFORMATION
4.0. HARDWARE INTERFACING
OVERVIEW

be tied to 5 volts. When the analog to' digital converter
is being used it may be desirable to connect the VREF
pin to a separate power supply, ,or at least a separate power
supply line.

This ~on of the manual is devoted to the hardware
engineer. All of the information you need to connect the
coaect pin to the coaect external circuit is provided. Many
of the special function pins have different characteristics
which are under software control, therefore, it is necessary
to define the system completely before the hardware is
wired-up.

The two VSS pins should be connected together with as
short a lead as possible to avoid problems due to voltage
drops across the wiring. There should be no measurable
voltage difference betWeen VSSI and VSS2. The 2 VSS
pins and the ANGND pin should all be nominally at 0
volts. The maximum current drain of the 8096 is around
200mA, with all lines unloaded. '

Frequently within this section a specification for a current,
voltage, or time period is referred to; the values provided
are to be used as an approximation only. Th~ exact spc:cification can be found in the latest data sheet for the particular part and temperature range that is being used.

When the analog converter is being used, clean, stable
power must be provided to the analog' section of the chip
to assure highest accuracy. To achieve this, it may be
desirable to separate the analog power supply from the
digital power supply. The VREF pin supplies 5 volts to
the analog circuitry and the ANGND pin is the ground for
this section of the chip. More information on the analog
power supply is in section 4.3.1.

4.1. REQUIRED HARDWARE
CONNECTIONS
Although the 8096 is a single-chip microcontroller, it still
requires several external connections to make it work.
Power must be applied, a clock source provided, and some
form of reset circuitry must be present. We will look at
each of these areas of circuitry separately. Figure 4-5
shows the connectionS that, are needed for a single-chip
system.

4.1.2. Other Needed Connections
Several of the pins on the 80% are used to configure the
,mode of operation. In normal operation the following pins
should be tied directly to the indicated power supply.

4.1.1. Power Supply Information

Power for 8096 flows through 6 pins; one vee pin, two
VSS pins, one VREF (analog Vee), one ANGND (Analog VSS), and one VPD (V Power Down) pin. All six
of these pins must be connected to the 8096 for normal
operation. The vee pin, VREF pin and VPD pin should

NMI

vee

TEST

vee

vee (to allow internal execution)
VSS (to force external execution)

TO DIVIDER CIRCUITRY

POWER SUPPLY

, ptVlDER CIRCUITRY

vee

SUBSTRATE

30 pf ..,.

XTAL1

3Qpf

Flgur~ 4-2. Crystal Oscillator Circuit

Figure 4-1. 8096 Oscillator ClrcuH

4-1

MCS~·96

HARDWARE DESIGN INFORMATION

Although the £A' pin' ha~ an" i~~~al pulldO\\lll, it is ~si
to tie this pin to the desired level if it is not left completely
disconnected. This will prevent induced noise from disturbing the system. ,

responsci mode as
iIiduc;ive read~cei~' parallel resonance with capacitance external to the crystal.

The crystal specifications, and capacitance, values (C 1 and
C2 in Figure 4-2) are not critical. 301'1" can be used in
these positions at any frequency with good quality crystals. For 0.5% frequency accuracy, the crystal frequency
can be specified at series resonance or for parallel resonance with any load capacitance. (In other words, for that
degree of frequency accuracy, the load capacitance si!Dply
doesn't matter.) For 0.05% frequency accl!racy the crystal
frequency should be specified for parallel resonance with
25 pF load capacitance, if Cl and C2 are 30 pF.

4.1.3. Oscillator Information
The 8096 requires a clock source to operate. This clock
can be provided to the chip through the XTALl input or
the on-chip oscillator can ~ used. The frequency of operation is, froIll 6.0 MHz to 12 MHz.
The on-Chip circuitry for the 8096 oscillator is a single
stage linear inverter as shown in Figure 4-1. It is intended
for use as a crystal-controll!Xi, po,sitive reactance oscillator
with external connections as shown in Figure 4-2. In this
application, the crystal is being operated in its fundamental

A more in-depth discussion of crystal specifications and
the selection of values for Cl and C2 can be found in the
Intel Application Note, AP-155, "Oscillators for
Microcontrollers. ",

DIVIOER CIRCUITRY

To drive the 8096 with an external clock source, apply
the external clock signal to XTALl and let XTAL2 float.
An example of this circuit is shown in Figure 4-3. The
required voltage levels on XTALl are specified in the data
sheet. The signal on XTALI must be clean with good
solid levels. It is important that the minimum high and
low times are met.

vec

...
VCC
XTAL1

XTAU
FLOAT

74804

There is no specification on rise and fall times, but they
should be reasonably fast (on the order of 30 nanoseconds)
to avoid having the XTALI pin in the transition range for
long periods of time. The longer the signal is in the transition region, the higher the probability that an external
, noise glitch could be seen by the clock generator circuitry.
Nois!l glitches on the 8096 internal clock lines will cause
unreliable operation.
The clock generator provides a 3 phase clock output from
the XTALI pin input. Figure 4-4 shows the waveforms
of the major internal timing signals.

Figure 4-3. External Clock Drive

XTAL1

PHASE A

(CLKOUT)

PHASES

PHASEC

PHASEK

Flg~re

4-4. Internal Timings

4-2

MCS®-96 HARDWARE DESIGN INFORMATION
is only two state times. If this is done, it is possible that
the 8096 will be reset and start running before the other
parts on the board are out of reset. The software must
account for this possible problem.

4.1.4. Reset Information
In order for the 8096 to function properly it must be reset.
This is done by holding the reset pin low for at least 2
state times after the power supply is within tolerance, the
oscillator has stabilized, and the back-bias generator has
stabilized. Typically, the back-bias generator requires bne
millisecond to stabilize.

A capacitor directly connected to RESET cannot be used
to reset the part if the pin is to be used as an output. If
a large capacitor is used, the pin will pull down more
slowly than normal. It will continue to pull down until the
8096 is reset. It could fall so slowly that it never goes
below the internal switch point of the reset signal (I to
1.5 volts), a voltage which may be above the guaranteed
switch point of external circuitry connected to the pin.
Several circuit examples are shown in Figure 4-6.

There are several ways of doing this, the simplest being
just to connect a capacitor from the reset pin to ground.
The capacitor should be on the order of 1 to 2 microfarads
for every millisecond of reset time required. This method
will only work if the rise time of VCC is fast and the total
reset time is less than around 50 milliseconds. It also may
not work if the reset pin is to be used to reset other parts
on the board. An 8096 with the minimum required connections is shown in Figure 4-5.

4.1.5. Sync Mode
If RESET is brought high at the same time as or just after
the rising edge of XTALl, the part will start executing
the 10 state time RST instruction exactly 6'12 XTALl
cycles later. This feature can be used to synchronize several MCS-96 devices. A diagram of a typical connection
is shown in Figure 4-7. It should be noted that parts that
start in sync may not stay that way, due to propagation
delays which may cause the synchronized parts to receive
signals at slightly different times.

The 8096 RESET pin can be used to allow other chips on
the board to make use of the watchdog timer or the RST
instruction. When this is done the reset hardware should
be a one-shot with an open-collector output. The reset
pulse going to the other parts may have to be buffered and
lengthened with a one-shot, since the RESET low duration

+5 VOLTS
SEPARATE

vee TRACE

(2)

VPD
VREF

NMI

(1)

TEST

0.1 ,.f
ANGND

EA
VCC
0.1 TO 1.0 ,.f
VSS1
VSS2

RESET
10,.f
TO
25,.f

+
C,=C.=30pf
XTAL2

SEPARATE GROUND TRACE (2)
":'

NOTES: 1. THESE CAPACITORS ARE NEEDED ONLY IF A TO D IS USED.
2. VREF & ANGND MAY BE CONNECTED TO THE SAME TRACES AS THE DIGITAL POWER SUPPLY IF THE
A TO D IS NOT USED.

FIgure 4·5. MInimum Hardwa~e Connections

4-3

· MCS®·96 HARDWARE DESIGNINFORMA:r:ION

OTHER
CIRCUITRY

I. 1.0,.f

....

8096
OTHER
CIRCUITRY

1000

NOTE: 1. THE DIODE WILL PROVIDE A FASTER CYCLE TIME REPETITIVE POWER-ON-RESETS

Figure 4·6, Multiple Chip Reset Circuits

XTAL1

B096
RESET

Figure 4·7. Reset Sync Mode

4.1.6. Disabling the Watchdog Timer

high indefillitely. Just resetting the .Wlltchdog timer will
not clear the flip-flop which keeps the RESET pull-down
on.

The watchdog timer will pull the RESET pin low when
it overflows. If the pin is being externally held above the
low going threshold, the pull-down transistor will remain
on indefinitely. This means that once the watchdog overflows, the part must be reset or RESET mlist be held

The pull-down is capable of sinking on the order of 30
milliamps if it is held at 2.0 volts. This amount of current

4-4

MCS®~96

HARDWARE DESIGN INFORMATION

may cauSe some long term reliability problems due to
localized chip heating. For this reason, parts that will be
,used in production should, never have had the watchdog
timer over-ridden for more than a second or two.

to operate the 8096 until it has completed its reset
operation.

4.2. DRIVE AND INTERFACE LEVELS
Whenever the reset pin is being pulled high while the pulldown is on, it should be through a resistor that will limit
the voltage on RESET to 2.5 volts and the current through
the pin to 40 milliamps. Figure 4-8 shows a circuit which
will provide the desired results. Using the LED will provide the additional benefit of having a visual indicator that
the part is trying to reset itself, although this circuit only
works at room temperature and vee = 5 Volts.

There are 5 types of 1/0 lines on the 8096. Of these, 2
are inputs and 3 are outputs. All of the pins of the same
type have the same current/voltage characteristics. Some
of the control input pins, such as XTALI and RESET,
may have slightly different characteristics. These pins are
discussed in section 4. I.
'

If it is necessary to disable the watchdog timer for more
than a brief test the software solution of never initiating
the times should be used. See Section 2.14.

While discussing the characteristics of the 110 pins some
approximate current or voltage specifications will be
given. The exact specifications are available in the latest
version of the 8096 Data Sheet.

4.1.7. Power Down Circuitry

4.2.1. Quasi-Bidirectional Ports

Battery backup can be provided on the 8096 with a I rnA
current drain at 5 volts. This mode will hold locations
OFOH through OFFH valid as long as the power to the
VPD pin remains on. The required timings to put the part
into power-down and an overview of this mode are given
in section 2.4.2.

The quasi-bidirectional port is both an input and an output
port. It has, three states, low impedance current sink, low
impedance current source, and high impedance current
source. As a low impedance current sink, the pin has a
specification of sinking up'to around .4 milliamps, while
staying below 0.45 volts. The pin is placed in this condition by writing a '0' to the SFR (Special Function Register) controlling the pin.

A 'key' can be written into power-down RAM while the
part is running. This key can be checked on reset to determine if it is a start-up from power-down or a complete
cold start. In this way the validity of the power-down
RAM can be verified. The length of this key determines
the probability that this procedure will work, however,
there is always a statistical' chance that the RAM will
power up witl1 a replica of the key.

When a 'I' is written to the SFR location controlling the
pin, a low impedance current source is turned on for one
state time, then it is turned off and the depletion pull-up
holds the line at a logical '" state. The low-impedance
pull-up is used to shorten the rise time of the pin, and has
current source capability on the order of '00 times that
of the depletion pull-up. The configuration of a quasibidirectional port pin is shown in Figure 4-9.

Under most circumstances, the power-fljil indicator which
is used to initiljte a power-down condition must come from
the unfiltered, unregulated section of the power supply~
The power supply must have sufficient storage capacity

While the depletion mode pull-up is the only device on,
the pin may be used as an input with a leakage of around

r----1~----

o--VCC

MY5020
TO OTHER
CIRCUITS

LM313
1N4001

IN4001

8096

330fi

22 fi

NOTE: SEE CAUTIONS IN SECTION 4.1.6.

, Figure 4-et. Disabling the WDT

4-5

39fi

VCC

MCS®·96 HARDWARE DESIGN INFORMATIQN

HIGH IMPEDANCE
PULL UP - ALWAYS ON

LOW IMPEDANCE
PULL UP

I1
,I

INPUT

LOW IMPEDANCE
PULL UP

HIGH IMPEDANCE
PULL UP

-SOmA

-160,.A

-30mA

-90 ,.A

LOW IMPEDANCE
PULL DOWN
SOmA

TYPICAL

30mA

10mA

-30/LA

4V
VOH

tt~'
2V

4V
VOL

NOTE: THESE GRAPHS SHOW TYPICAL PIN CAPABILITIES, THEY, ARE NOT GUARANTEED SPECIFICATIONS

Figure 4-9. Quasi-Bidirectional Port

the current to a maximum of 0.2 milliamps per pin. If
several pins are connected to a common ground through
switches, it should be sufficient to limit the current through
the common ground to 0.2 milliamps times the maximum
number of pins that could be switched to ground. Many
switches require a minimum amount of current flow
through them to keep them clean. This could cause problems in long term reliability if it is not considered when
designing a system.

100 microamps from 0.45 volts to VCe. It is ideal for
use with TIL or CMOS chips and may even be used
directly with switches, however if the switch option is
used certain precautions should be taken. It is important
to note that any time the pin is read, the value returned
will be the value on the pin, not the value placed in the
control register. This could prevent logical operations on
these pins while they are being used as inputs.

4.2.2. Quasi-Bidirectional Hardware
Connections

If a switch is used on a long line connected to a quasibidirectional pin, a pull-up resistor is recommended to
reduce the possibility of noise glitches and to decrease the
rise time of the line. On extremely long lines that are
handling slow signals a capacitor may be helpful in addition to the resistor to reduce noise.

When using the quasi-bidirectional ports as inputs tied to
switches, series resistors should pe used if the ports will
be written to internally after the part is initialized. Every
time any quasi-bidirectional pin is written from a zero to
a one, the low impedance pull-up is turned on. If many
of the pins are tied directly to ground, a large current·
spike will be generated when all of these low impedance
devices are turned on at once.

4.2.3. Input Ports, Analog and Digital
.The high impedance input ports on tjte 8096 have an input
leakage of a few microamps and are predominantly capacitive loads on the order of 10 pf. The Port 0 pins have

For this reason, a series resistor is recommended to limit

4-6

MeS.... HARDWARE DESIGN INFORMATION
an ad9itional function when the A to D converter is being
used. These pins are the input to the A to D converter,
and as such, are requiIed to provide current to the comparator when a conversion is in process. This means that
the input characteristics of a pin will change if a conversion
is being done on that pin. See section 4.3.1.

than this. A ISk pull-up resistor will source a maximum
of 0.33 milliamps, so it would be a reasonable value to
choose if no other circuits with pullups were connected
to the pin.

4.2.5. HSO Plna, Contro, Outputs and BUI
Plna

4.2.4. Open Drain PortB '

The control outputs and HSO pins have output buffers
with the same output characteristics as those of the bus
pins. Included in the category of control outputs are: TXD,
RXD(in mode 0), PWM, CLKOUT, ALE, BHE, RD.
,and Wi. The bus pins have 3 states: output higb. output
low. and high impedance input. As a higb output. the pins
are specified to source around 200 pA to 2.4 volts. but
the pins can llOurce on the order of ten times that value
in order to provide fast rise times. When used as a low
output. the pins can sink around 2 mA at .4S volts. and
considerably more as the voltage increases. When in the
higb impedance state. the pin acts as a capacitive load
with a few microamps of leakage. Figure 4-10 shows the
internal configuration of a bus pin.

Ports 3 and 4 on the 8096 are open drain ports. There is
no pull-up when these pins are used as 110 ports. These
pins have different qharacteristics when used as bus pins
as desprib!:d in the next section. A diagram of the output
buffers connected to ports 3 and 4 and the Bus pins is
shown i,n Figure 4·10.
When Ports 3 and 4 are to be used as inputs, or as Bus
pins, they must first be written with a '1', this will put
the ports in a higb impedance mode. When they are used
as outputs, 1\ pull-Up resistor must be used externally. The
sink capability of these pins is on the order of ~.4 milliamps so the total pull-up current to the pin must be less

vee
DATA
IN

JUS OUTPUT

ENAeLE
8u8DATA

-4- PORT 3,4 OPEN DRAIN
DRIVER

PORTENAeLE
POfITDATA

aus PULL DOWN

aus PULL UP
BUS

IUS.

PORT PULL DOWN

P1. P2

IUS. P1. P2
2SmA

10mA

-10mA

e e
~ 1SmA

-30mA

2V
VOlt

SmA

VOl.

NOTE: ntESE GRAPHS SHOW TYPICAL PIN CAPAIIUTIES. ntEl ARE NOT GUARANTEED SPECIFICATIONS

Figure 4-10. Bus and

Port 3 and 4 Pins

4-7

,>MCS@l-96iHARDWARE'DESIGN'1NFORMA'tION

sample and' hold circuit rtlliy vary
(1/2048).'"
" '" '

4.3. ANALOG INTERFACE
Intetfacing tire 8096 to analog signal can be done in several
ways. If the 8096 needs to measure an analog signal the
A to pco~verter can ~ used. Creation of analog outputs
can be done with either the PWM output or theHSb unit.

The 8096 can have 8 analog inputs and can convert one
input at a time. into a digital value. Each conversion takes
42 microseconds with a 12 MHz signai on XTALI. The
input signal is applied to one'ofthe Port O/Analog Channel
inputs. Since there is no sample and hold on the A to D,
the input signal must remain constant over: the sampling
' '
,
'
period,

The converter is a 10-bit, successive approXimation', 'ra~
tiometric converter, so the numerical value obtained from
'
the conversion will be:

When a conversion takes place, the 8096 compares the
external signal to that of its internal D to A. Based on'the
i:esult ofthe comparison it adjusts the D to A and compares
again. Each comparison takes 8 state times and requires
the input to the comparator to be charged up. 20 comparisons are made during a conversion, two times for each
bit of resolution. An additional 8 states are used to load
and store values. The total number of state times required
is 168 fora lO-bit conversion. Attempting to do other
than a 10-bit conversion is not recommended.

1023 * (VINcANGND) 1 (VREF-ANOND)

It can be seen that' the 'power 'supply levels'strongly influence' !he' abs6lute accuracy' of the conversion. For this
reason, it is recommended that the ANGND pin be tied
to a clean ground, as close to the power supply as possible.
VREF should be well regulated and used only for the A
to- D converter. If ratiometric information, is desired,
VREF can be connected to VCC, but this should be done
at the power supply not at the chip. It needs to be able to
source around IS milliamps. Bypass capacitors should be
used between VREF and ANOND.ANGND should be
within about a tenth of a volt of VSS and VREF should
be within a few tenths of a volt of VCC. A 0.01 uf
capacitor.should·be-connected between the ANGND and

Since the capacitance of the comparator input is around
O.Spf, the sample and hold circuit must be able to charge,
a IOpf (20*0.Spt) capacitor without a significant voltage
change. To keep the effect of the sample and hold circuit
blliow ± Y2 Isb on a 10-bit converter, the voltage on the

HSO
OR
PWM

BUFFER
TO MAKE
OUTPUT
SWING
RAIL
TO
RAIL

more than O.OS%
,

The effectiv~ capacitance of the sample and' hold must,
therefore ,be'at least20000pf or 0:02 ufo If there'is external
leakage on the capacitor, its value must be' increased to
compensate for the leakage. At IO~A leakage, 2.S mV
(S/2048) will be lost from a 0.17 ilf capacitor in 42 ~S,
The 'capa"citor connected externally 10 the pin should,
therefore,'be at least 0.2 uffor best reSults. If the external
signal' changes' slowly relative to 42 p,s',' thert a larger
capacitor will work well and also filter out unwanted noise.

4.3.1. Analog Inputs'

8096

FILT~R
(PASSIVE
OR
ACTIVE)

,1~

f----

POWER
AMP

,
ANALOG

f----"- OUTPUT

(OPTIONAL)
(OPTIONAL)

SUGGESTED CIRCUIT FOR NON-CRITicAL APPLICATIONS

8096
HSO
OR
PWM

HIGH
R
IMPEDANCE 'lL._~ ANALOG
X~--"""""""---_-----I
OUTPUT
AMP
CD4049

RAND C ARE CHOSEN FOR BEST
FILTERING AT THE USER'S FREQUENCY

Figure 4-11. D/ABuffer Block Diagram

4-8

MCS®-96 HARDWARE DESIGN INFORMATION
full state time to guarantee that it is recognized. This
restriction applies even if the divide by eight mode is being
used. If two events occur on the same pin within the same
8 state time window, only one of the events will be
recorded. If the events occur on different pins they will
always be recorded, regardless of the time difference. The
8 state time window, (ie. the amount of time during which
Timer 1 remains constant), is stable to within about 20
nanoseconds. The window starts roughly around the rising
edge of CLKOUT, however this timing is very approximate due to the amount of internal circuitry, involved.

VBB pins to reduce the noise on VBB and provide the
highest possible accuracy. Figure 4-5 shows all of these
connections.

4.3.2. Analog Output Suggestions
Analog outputs can be generated by two methods, either
by using the PWM output or the HSO. Either device will
generate a rectangular pulse train that varies in duty cycle
and (for the HSO only} period. If a smooth analog signal
is desired as an output, the rectangular waveform must be
filtered.

4.4.3. Standard 110 Port Pins

In most cases this filtering is best done after the signal is
buffered to make it swing from 0 to 5 volts since both of
the outputs are guaranteed only to TTL levels. A block
diagram of the type of circuit needed is shown in Figure
4-11. By proper selection of components, accounting for
temperature and power supply drift, a highly accurate 8bit D to A converter can be made using either the HSO
or the PWM output. If the HSO is used the accuracy could
be theoretically extended to 16-bits, however the temperature and noise related problems would be extremely hard
to handle.

Port 0 is different from the other digital ports in that it is
actually part of the A to D converter. The port is sampled
once every 8 state times, the same frequency at which the
comparator is charged-up during an A to D conversion.
This 8 state times counter is not synchronized with Timer
1. If this port is used the input signal on the pin must be
stable 8 state times prior to reading the SFR.
Port 1 and Port 2 have quasi-bidirectional 110 pins. When
used as inputs the data on these pins must be stable one
state time prior to reading the SFR. This timing is also
valid for the input-only pins of Port 2. When used as
outputs, the quasi-bidirectional pins will change state
shortly after CLKOUT falls. If the change was from '0'
to a '1' the low impedance pull-up will remain on for one
state time after the change.

When driving some circuits it may be desirable to use
unfiltered Pulse Width Modulation. This is particularly
true for motor drive circuits. The PWM output can be
used to generate these waveforms if a fixed ,period on the
order of 64 uS is acceptable. If this is not the case then
the HSO unit can be used. The HSO can generate a variable waveform with a duty cycle variable in up to 65536
steps and a period of up to 131 milliseconds. Both of these
outputs produce TTL levels.

Ports 3 and 4 are addressed as off-chip memory-mapped
110. The port pins will change state shortly after the rising
edge of CLKOUT. When these pins are used as Ports 3
and 4 they are open drain, their structure is different when
they are used as part of the bus. See Section 2.12A.

4.4. 1/0 TIMINGS

4.5. SERIAL PORT TIMINGS

The 1/0 pins on the 8096 are sampled and changed at
specific times within an instruction cycle. The timings
shown in this section are idealized; no propagation delay
factors have been taken into account. Designing a system
that depends on an 110 pin to change within a window of
less than 50 nanoseconds using the information in this
section is not recommended.

The serial port on the 8096 was designed to be compatible
with the 8051 serial port. Since the 8051 uses a divide by
2 clock and the 8096 uses a divide by 3, the serial port
on the 8096 had to be provided with its own clock circuit
to maximize its compatibility with the 8051 at high baud
rates. This means that the serial port itself does not know
about state times. There is circuitry which is synchronized
to the serial port and to the rest of the 8096 so that information can be' passed back and forth.

4.4.1. HSO Outputs
Changes in the HSO lines are synchronized to Timer 1.
All of the external HSO lines due to change at a certain
value of a timer will change just prior to the incrementing
of Timer 1. This corresponds to an internal change during
Phase C, every eight state times. From an external perspective the HSO pin should change around the rising
edge ofCLKOUT and be stable by its falling edge. Internal
events can occur anytime during the 8 state time window.

The baud rate generator is clocked by either XTALl or
T2CLK, because T2CLK needs to be synchronized to the
XTALl signal its speed must be limited to 1/16 that of
XTAL 1. The serial port will not function during the time
between the consecutive writes to the baud rate register.
Section 2.11 A discusses programming the baud rate generator.

Timer 2 is synchronized to increment no faster than Timer
J, so there will always be at least one incrementing of
Timer 1 while Timer 2 is at a specific value.

4.5.1. Mode 0
Mode 0 is the shift register mode. The TXD pin sends
out a clock train, while the RXD pin transmits or receives
the data. Figure 4-12 shows the waveforms and timing.
Note that the port starts functioning when a 'I' is written

,4.4.2. HSI Input Sampling
The HSI pins are sampled internally once each state time.
Any value on these pins must remain stable for at least 1

4-9

MCS®·96 HARDWARE DESIGN INFORMATION

to the REN (Receiver Enable) bit in the serial port control
register. If REN is already high, clearing the RI flag will
start a reception.

A schematic of a typical circuit is shpwn in Figure 4-13.
This circuit inverts the data coming in; so it must be reinverted in software. The enable and latch connections to
the shift registers can be driven by decoders, rather than
directly fromllie low speed 110 ports, if the software and
hardware are properly designed.

In this mode the serial port can be used to expand the
110 capability of the 8096 by simply adding shift registers.

RXO(O'iiT)\

DO
DO

03
03

06
06

RXO(IN)
EXPANDED:

RXO(OUT) ' ' -_ _

-----''C

,.....:;DO~_---'C,...:__......:;.0;...1
DO
01

---Q----I'~---IDI-----Htl'---

RXO (IN)

Figure 4.12. Serial Port Timings in Mode 0

CLOCK INHIBIT

Figure 4-13. Mode 0 Serial Port Example

4·10

07
07

MCS-96 HARDWARE· DESIGN INFORMATION

4.5.2. Mode 1 Timings

when a 'I to 0' transition (start bit) is received. The transmit clock may therefore not be in sync with the receive
clock, although they will both be at the same frequency.

Mode 1 operation of the serial port makes use of IO-bit
data packages, a start bit, 8 data bits and a stop bit. The
transmit and receive functions are controlled by separate
shift clocks. The transmit shift clock starts when the baud
rate generator is initialized, the receive shift clock is reset

The TI (Transmit Interrupt) and RI (Receive Interrupt)
flags are set to indicate when operations are complete. TI

~n!HCH

CLKOUT

I
I
I

I
I

TCHCL

TCLLH

)

READY

!-TCLYX

VALID

TLLCH
TYLYH

TLHLL

/~ !-TLLYV'"
II

ALE

TLLYH""';"'"

TLLRL

TRHLH

TRLRH

TRXDZ

TAVLL

TLLAX

!-TRLDV_

-~
ADDR OUT

I_TRLAZ

DATA IN

TAVDV
TLLRL

~ !-TWLWH

TAVLL

I--

TLLAX

f----4

,INST

TWXQX

~TQVWX

ADDR OUT

VALID

TWXLH_

DATA OUT

Figure 4-14, Bus Sig~al Timings

4-11

,-\

MCS®·96 HARDWARE DESI~N INFORMATrON

is set when the last data bit of the message has been sent,
not when the stop bit is sent. If an attempt to send another
byte is made before the stop bit is sent the port will hold
off transmission until the stop bit is complete. RI is set
when 8 data bits are received, not when the stog bit is
received. Note that when the serial port status register is
read both TI and RI are cleared.
Caution should be used when using the serial port to connect more than two devices in half-duplex, (ie. one wire
for transmit and receive). If the receiving processor does
Tosc -

Oscillator Period, one cycle time on XTALI.

Timings The Memory System Must Meet
TLLYH - ALE low to READY high: Maximum time
after ALE falls until READY is brought high to ensure
no more wait states. If this time is exceeded unexpected
wait states may result. Nominally I Tosc + 3 Tosc*
number of wait states desired.
TLLYV - ALE low to READY VALID: Maximum time
after ALE falls until READY must be valid. If this time
is exceded the part could malfunction necessitating a chip
reset. Nominally 2 Tosc periods.
TYLYH - READY low to READY high: Maximum time
the part can be in the not-ready state. If it is exceeded,
the 8'096 dynamic nodes which hold the current instruction
may 'forget' how to finish the instruction.
TAVDV - ADDRESS valid to DATA valid: Maximum
time that the memory has to output valid data after the
8096 outputs a valid address. Nominally, a maximum of
5 Tosc periods.
TRLDV - READ low to DATA valid: Maximum time
that the memory has to output data after READ goes low.
Nominally, a maximum of 3 Tosc periods.
TRXDZ - READ not low to DATA float: Time after
READ is no longer low until the memory must float the
bus. The memory signal can be removed as soon as READ
is not low, and must be removed within thespecif\ed
maximum time.
Nominally, a maximum of I Tosc period.

Timings the 8096 Will Provide
TCHCH - CLKOUT high to CLKOUT high: The period
of CLKOUT and the duration of one state time. Always
3 Tosc average, but individual periods could vary by a
few nanoseconds.
.
TCHCL - CLKOUT high to CLKOUT low: Nominally
I Tosc period.

not wait for one bit time after RI is set before starting to
transmit, the stop bit on the link could be squashed .. This
could Gause a problem for other devices listening on the
link.

4.5.3. Mode 2 and 3 Timings
Modes 2 and 3 operate in a manner similar to that of mode
I. The only difference is that the data is now made up of
9 bits, so ll-bit packages are transmitted and received.
This means that TI and RI will be set on the 9th data bit
TCLLH - CLKOUT low to ALE high: A help in deriving
other timings, typically plus or minus 5 to 10 ns.
TLLCH - ALE low to CLKOUT high: Used to derive
other timings, nominally I Tosc period.
TLHLL - ALE high to ALE low: ALE pulse width.
Useful in determining ALE rising edge to ADDRESS valid
time. Nominally I Tosc period.
TAVLL"- ADDRESS valid to ALE low: Length of time
ADDRESS is valid before ALE falls. Important timing
for address latch circuitry. Nominally I Tosc period.
TLLAX - ALE low to ADDRESS invalid: Length of
time ADDRESS is valid after ALE falls. Important timing
for address latch circuitry. Nominally I Tosc period.
TLLRL - ALE low to READ or WRITE low: Length
of time after ALE falls before RD or WR fall. Could be
needed to ensure that proper memory decoding takes place
before it is output enabled. Nominally I Tosc period.
TRLRH - READ low to READ high: RD pulse width,
nominally I Tosc period.
TRHLH - READ high to ALE high: Time between RD
going inactive and next ALE, also used to calculate time
between RD inactive and next ADDRESS valid. Nominally I Tosc period.
TWLWH - WRITE low to WRITE high: Write pulse
width', nominally 2 Tosc periods.
TQVWX - OUTPUT valid to WRITE not low: time that
the OUTPUT data is valid before WR starts to go high.
Nominally 2 Tosc periods.
.
TWXQX - WRITE not low to OUTPUT not valid: Time
that the OUTPUT data is valid after WR starts to rise.
Nominally I Tosc period.
TWXLH - WRITE not low to ALE high: Time between
write starting to rise and next ALE, also used to calculate
the time between WR .starting to rise and next ADDRESS
valid. Nominally 2 Tosc periods.

Figure 4-15. Timing Specification. Explanations

4-12

MCS®·96 HARDWARE DESIGN INFORMATION

rather than the 8th. The 9th bit can be used for parity or
mUltiple processor communications (see section 2.11).

could lock-up. There is no requirement as to when
READY may go high, as long as the maximum READY
low time (TYLYH) is not violated. To ensure that only
one wait state is inserted it is necessary to bring READY
high TLLYH after the falling edge of ALE.

4.6. BUS TIMING AND MEMORY
INTERFACE
4.6.1. Bus Functionality

4.6.4. INST Line Usage

The 8096 has a multiplexed (address/data) 16 bit bus.
There are control lines provided to demultiplex the bus
(ALE), indicate reads or writes (RD, WR), indicate if the
access is for an instruction (lNST), and separate the bus
into high and low bytes (BHE, ADO). 'Section 2.3.5 contains an overview of the bus operation.

The INST (Instruction) line is high during the output of
an address that is for an instruction stream fetch. It is low
during the same time for any other memory access. At
any other time it is not valid. This pin is not present on
the 48-pin versions. The INST signal can be used with
a logic analyzer to debug a system. In this way it is
possible to determine if the fetch was for instrUctions or
data, making the task of tracing the program much easier.

4.6.2. Timing Specifications
Figure 4-14 shows the timing of the bus signals and data
lines. Since this is a new part, the exact timing specifications are subject to change, please refer to the latest
8096 data sheet to ensure that your system is designed to
the proper specifications. The major timing specifications
are described in Figure 4-15.

4.6.5. Address Decoding
The multiplexed bus of the 8096 must be demultiplexed
before it can be used. This ca be done with 2 74LS373
transparent latches. As explained, in section 2.3,5, the
latched address signal will be referred to as MAO through
MAI5. (Memory Address), and the data lines will be
called MOO through MDI5, (Memory Data).

4.6.3. READY Line Usage
When the processor has to address a memory location that
cannot respond within the standard specifications it is necessary to use the READY line to generate wait states.
When the READY line is held low the processor waits
in a loop for the line to come high. There is a maximum
time that the READY line can be held low without risking
a processor malfunction due to dynamic nodes that have
not been refreshed during the wait states. This time is
shown as TYLYH in the data sheet.

Since the 8096 can make accesses to memory for either
bytes or words it is necessary to have a way of determining
the type of access desired. The BHE and MAO lines are
used for this purpose. BHE must be latched, as it is valid
only when the address is valid. The memory system is
typically set up as 32K by 16, instead of 64K by 8. When
the BHE line is low, the upper byte is enabled. When
MAO is low, the lower byte is enabled when MAO is high
BHE will be low, and the upper byte is enabled.

In most cases the READY line is brought low after the
address is decoded and it is determined ,that a wait state
is needed. It is very likely that some addresses, such as
those addressing memory mappe4 peripherals, would need
wait states, and others would not. The READY line must
be stable within the TLLYV specification after ALE falls
(or the TYVCL before CLKOUT falls) or the processor

ALE
AD8-AD15

When external RAM and EPROM are both used in the
system the control logic can be simplified a little to some
of the addresses. The 8096 will always output BHE to
indicate if a read is of the high byte or the low byte, but
it discards the byte it is not going to use. It is therefore
possible to use the BHE and MAO lines only to control

MA8-MA15

8096
ADO-AD7

r£l

A7-A14

1 8

MAO-MA7

373

MAO,

AO-A6

2764
UPPER

2764
LOWER

N.C.

8
I
J

I
RD

Figure 4·16. Memory Wiring Example-EPROM Only System

4-13

MCS®-96 HARDWARE DESIGN INFORMATION
memory writes, arid to ignore these liQes during me~ory
reads. Figure 4-16 and 4-17 show block diagrams'of two
memory systems, an external EPROM only system and
'
a RAM/ROM system.

. signal may be limited by either the ALE timing or the
Address timing, these two cases must be considered.

If Limited by ALE:
Minimum ALE pulse width =

rosc-l0
. (TLHLL)

4.6.6. System Verification Example
To verify that a system such as the one in Figure 4-17 will
work with the 8096, it is necessary to check 'all of the
timing parameters. Let us examine this system one parameter at a time using the proposed 8096 specifications.
These specifications are subject to change, refer to the
latest 8096 data sheet for the current specifications.

Minimum Addr set-up to ALE falling =

Therefore ALE could occur 10 ns before Address valid.
Total delay from 8096 Address stable to MA (Memory
Address) stable would be:

The timings of signals that the processor and memory use
are effected by the latch and buffer circuitry. The timings
of the signal provided by the processor are delayed by
various amounts of time. S imilarly, the signals coming
back from the memory are also delayed. The calculations
involved in verifying this system follow:

Address Valid Delay -

Tosc-20
(TAVLL)

ALE delay from address
74LS373 clock to output

- 10
30
20 nanoseconds

If Limited by Address Valid:
74LS373 Data Valid to Data Output = 18 nanoseconds

20 nanoseconds

In the worst case, the delay in Address valid is
controlled by ALE and has a value of 20 nanoseconds.

The address lines are delayed by passing them through
the 74LS373s, this delay is specified at 18ns after
Address is valid or 30ns after ALE is high. Since the

MA8-MA15

ALE
A7A14

AD8-AD15

MA8-MA15

VCC

MDO-MD7

PR D
CLR
74LS
74

A7A14

LOWER
BYTE OF
MEMORY
(EVEN
LOCATIONS)

8096
ADO-AD7

AOA6

Ht---=,.-----=---,

MAO

UiHE (LATCHED BHE)

'---+--I--~>CK

Figure 4-17. RAM/ROM Memory System

4-14

WRLOW

MCS®·96 HARDWARE DESIGN INFORMATION

Delay of Data Transfer to/from Processor nanoseconds

Read low to Data in;
TRLDV
RD Delay
Data Delay

The RD low to Data valid specification (TRLDV) is
3 Tosc-50, (200 ns at 12 MHz). The 74LS245 is enabled by RD and has a delay of 40 ns from enable.
The enable delay is clearly not a problem.

200.0 ns maximum
00.0 ns maximum
12.0 ns maximum
188.0 ns maximum

Provided by System:

The 74LS245 is enabled except during a read, so there
is no enable delay to consider for write operaions.

Address valid to Control;
TLLRL
TAVLL
Address Delay
. WR Delay

The Data In to Data Out delay of the 74LS245 is
12 ns.
Delay of WR signal to memory -

'. -

15 nanoseconds

63.3
63.3
20.0
00.0

ns
ns
ns
ns

minimum
minimum
maximum
minimum (no spec)

101.6 ns minimum
Latched BHE is delayed by the inverter on ALE and
the 74LS74.
74LS04 delay (Output low to high)
74LS74 delay (Clock to Output)

Write Pulse Width;
TWLWH
151.6 ns minimum
Rising WR Delay: - 15.0 ns maximum
00.0 ns minimum (no spec)
Falling WR Delay:

= 22
= 40

Delay of Latched BHE from ALE falling = 62
nanoseconds

146.6 ns minimum
Data Setup to WR rising;

The 74LS74 requires data valid for 20 ns prior to the
clock, the 8096 will have BHE stable Tosc-20 ns
(TAVLL, 63 ns at 12 MHz) prior to ALE falling. There
is no problem here.

TQVWX
Data Delay
WRDelay

Data Hold after WR;
TWXQX
Data Delay
WRDelay·

WR will fall no sooner than Tosc-20 ns (TLLRL, 63
ns at 12 MHz) after ALE goes low. It will therefore
be valid just after the Latched BHE is valid, so it is
the controlling signal.

The two memory devices which are expected to be used
most often with the 8096 are the 2764 EPROM and the
2128 RAM. The system verification for the 2764 is simple.

2764 \fac
(Address valid to Output) < Address valid to Data in
250 ns < 354 ns O.K.

Address Delay = 20 ns
12 ns
Data Delay
WRDelay
15 ns
RD Delay
o ns

2764 Toe
< Read low to Data in
< 188 ns O.K.

(Output Enable to Output)
100 ns

These calculations assume no address decoder delays and
'no delays on the RD (OE) line. If there are delays in these
signals the delays must be added to the ,2764's timing.
The read calculations for the 2128 are similar to those for
the 2764.

Required by system:
Address valid to Data in;
TAVDV
Address Delay
Data Delay

58.3 ns minimum
0.0 ns minimum (no spec)
15.0 ns maximum .
43.3 ns minimum

WR High and WR Low are valid 15 ns after MAO,
Latched BHE and WR are valid. Since WR is the last
signal to go valid, the delay of WR (High and Low)
to memory is 15 ns.

.Characteristics of a 12 MHz 8096 system
with latches:

136.6 ns minimum
12.0 ns maximum
00.0 ns minimum (no spec)
124.6 ns minimum

MAO is valid prior to ALE falling, since the 20 ns
Address Delay is less than TAVLL.

Delay Summary -

386.6 ns maximum
- 20.0 ns maximum
--' 12.0 ns maximum
354.6 ns maximum

4-15

2128-20 Tac
200 ns

< Address valid to Data in
< 354 ns O.K,

2128-20 Toe
65 ns

< Read low to Data in
< 188 ns O.K.

MCS®.96 HARDWARE DESIGN INFORMATION

this function on the iSBE-96 emulator board. It can be
attached to any 8096 system which has the required address decoding and bus demultiplexing.

The write calculations are a little more involved, but'still
straight-forward.
2128 Twp (Write Pulse) < Write Pulse Width
100 ns < il46 ns O.K.

The output circuitry is basically just a latch that operates
when IFFEH or IFFFH are placed on the MA lines. The
inverters surrounding the latch create an open-collector
output to emulate the open-drain output found on the 8096.
The 'reset' line is used to set the ports to all l's when the
8096 is reset. It should be noted that the voltage and
current characteristics of this port will differ from those
of the 8096, but the basic functionality will be the same.,

2128 Tds (Data Setup) < Data Setup to WR rising
65 ns < 124 ns O,K.
2128 Tdh (Data Hold) < Data Hold after WR
o ns < 43 ns
All of the above calculations have been done assuming
that no components are in the circuit except for' those
shown in Figure 4-17. If additional components are added,
as may be needed for address decoding or memory bank
switching, the calcul)ltions must be updated to reflect the
actual circuit.

The input circuitry is just a bus transceiver that is addressed at IFFEH or IFFFH. If the ports are going to be
used for either input or output, but not both, some of the
circuitry can be eliminated.

4.7. NOISE PROTECTION TIPS

4.6.7. 1/0 Port Reconstruction
When a single-chip system is being designed using a multiple chip system as a prototype, it may be necessary to
reconstruct I/O ports 3 and 4 using a memory-mapped
I/O technique. The circuit shown in Figure 4-18 provides

Designing controllers differs from designing other computer equipment in the area of noise protection. A microcontroller circuit under the hood of a car, in a photocopier, CRT terminal, or a high speed printer is subject

WRLOW----------~~~~--------------_,

OUTPUT

74LS
05
(x11f.!)

MDO-MD7------+--~~~

~---------r~

MD&-MD15---------r--~~8~

RElfEIT------~~----------------------~--~
ADDR = P3, P4 -------+-(lI

AD ---------~

ADO-AD7

AD8-AD15

Figure 4-18. 110 Port Reconstruction

4-16

MCS@-96 HARDWARE DESIGN INFORMATION

to many types of electrical nois~. Noise can get to the
processor directly through the power supply, or it can be
induced onto the board by electromagnetic fields. It is also
possible for the pc board to find itself in the path of
electrostatic discharges. Glitches and noise on the pc board
can cause the processor to act unpredictably, usually by
changing either the memory locations or the program
counter.

structures, bypass capacitors, transient absorbers and
power busses with built-in capacitors can all be of great
help. It is much easier to design a board with these features
than to try to 'retrofit them later. Proper pc board layout
is probably the single most important and, unfortunately,
least understood aspect of project design. Minimizing loop
areas and inductance, as well as providing clean grounds
are very important. More information on protecting
against noise can be found in the Intd Application Note
AP-125, "Designing Microcontroller Systems For Noisy
Environments. "

There are both hardware and software solutions to noise
problems, but the best solution is good design practice
and a few ounces' of prevention. The 8096 has a watchdog
timer which will reset the part if it fails to execute the
software properly. The software should be set up to take
advantage of this feature.

4.8. PACKAGING PINOUTS AND
ENVIRONMENT
The MCS-96 family of products is offered in many versions. They are available in 48-pin or 68-pin packages,
with or without ROM, and with or without an A to D
converter. A summary of the available options is shown
in Figure 4-19.

It is also recommended that unused areas of code be filled
with Naps and periodiC jumps to an error routine or RST
(reset chip) instructions. This is particularly important in
the code around lookup tables, since if lookup tables are
executed all sorts of bad things can happen. Wherever
space allows, each table should be surrounded by 7 Naps
(the longest 8096 instruction has 7 bytes) and a RST or
jump to error routine instruction. This will help to ensure
a speedy recovery should the processor have a glitch in
the program flow.

The 48-pin versions are available in a 48-pin DIP (Dual
In-Line) package, in either ceramic or plastic.
The 68-pin versions are available in a ceramic pin grid
array, and a plastic flatpack. A plastic pin grid array will
be available in the near future.

Many hardware solutions exist for keeping pc board noise
to a minimum. Ground planes, gridded ground and VCC

ROM LESS

WITH ROM

68-pln 48-pln

68-pin 48-pin

Without A to D

8096

8094

8396

8394

With A to D

8097

8095

8397

8395

Figure 4-19. The MCS®-96 Family of Products

4-17

MCS®~96

Data Sheets

8094/8095/8096/8097
8394/8395/8396/8397
16·81T MIC.ROCONTROLLERS
•
-

- 839X: an 809X with 8K Bytes of On-chip ROM
High Speed Pulse 1/0
- 232 Byte Register File
10-bit AID Converter
- Memory-to-Memory Architecture
S Interrupt Sources
- Full Duplex Serial Port
Pulse-Width Modulated Output
_ Five S-bit 1/0 Ports
Four 16-bitSoftware Timers
- Watchdog Timer

The MCS~96 family of 16-bit microcontrollers consists of 8 members, all of which are
control functions.

d~signed

for high-speed

The CPU supports bit, byte, and word operations. 32-bit double-words are supported for a subset of the instruction
set. With a 12 MHz Input frequency the 8096 can do a 16-bit addition in 1.0 p,Sec and a 16 x 16-bit multiply or 321
16-bit divide in 6.5 /Lsec. Instruction execution times average 1 to 2 /Lsec in typical applications.
Four high-speed trigger inputs are provided to record the times at which external events occur. Six high-speed
pulse generator outputs are provided to trigger external events at preset times. The high-speed output unit can
simultaneously perform timer functions. Up to four such 16-bit Software Timers can be in operation at once.
An on-chip AID Converter converts up to 4 (in the 48-pin version) or 8 (in the 68-pin version) analog input channels
to 10-bitdigital values. This feature is only available on the 8095, 8395, 8097 and 8397 .
. Also provided on-chip are a serial port, a watchdog timer, and a pulse-width modulated output signal.

POWER
DOWN

r-------

FREQUENCV
REFERENCE

----~::K-~----:B~E-:
GEN

O~~~IP

(83961

I
I
I
I

CONTROL
SIGNALS

}

HIGH
SPEED
110

PORT 0

Figure 1.

PORT 1

PORT 2
ALT FUNCTIONS

HSI

ADDR
DATA
BUS

I
I PORT 4
I
I
____ ---lI

HSO

Block Diagram (For simplicity, lines connecting port registers to port buffers are not shown.)

5-1

inter

8096

RXD P2.1
TXD P2.0
HSIO
HSI1
HSI2 HS04
H~13 HS05
HSOO
HS01
HS02
HS03
VSS

vee
PWM P2.5

wI!

SHE
READY
AD15 P4.7
AD14 P4.6
AD13 P4.5
AD12 P4.4
AD11 P4.3
AD10 P4.2
AD9 P4.1
AD8 P4 0

1
2·

48
47
46
45
44
43
42
41
40
39
38
37
36
.35
34
33
32
31
30
29
28
27
26
25

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Figure 2.

Figure 1 shows. a block diagram of the MCS-96 parts,
generally referred to as the 8096. The 8096 is available
in 48-pin and 68-pin packages, with and without AID,
and with and witho!J1 on.chip ROM. The MCS-96 nUmbering system is shown below:

RESET
EXTINT P2.2
VPD
VREF
ANGND
ACH4 PO 4
ACH5 PO 5
ACH7 PO 7
ACH6 PO.6

EA
VCC
V$S
XTAL1
XTAL2
ALE
RD
ADO P3 0
AD1 P31
AD2 P3 2
AD3 P3 3
A04 P3 4
ADS P3 5
AD6 P3 6
AD7 P3 7

48 PIN

ROMLESS

8096

8094

ROM

8396

8394

ANALOG
AND
DIGITAL
I/O

ROMLESS

8097

8095

ROM

8397

8395

----

DIGITAL
I/O

Figures 2, 3 & 4 show the pinouts for the 48- and
68-pin packages. The 48-pin version is offered in
Dual-In-Line package while the 68-pin version
comes in a Flat-pack and a Pin Grid Array.

48-Pin Package

ACH5 PO 5
ACH4 PO 4
ANGND
VREF
VPD
EXTINT P2.2
RESET
RXD P21·
TXD P20
P10
P11
P12
P1.3
P14
HSIO
HSI1
HSI2 HS04

68 PIN

OPTIONS

1 2 3 4 5 6 7 8 91011121314151617
18
68
ADO P3.0
67
19
AD1 P31
66
20
AD2 P3.2
65
21
AD3 P3 3
64
22
AD4 P3 4
63
23
ADS P3 5
8096
62
24
AD6 P3.6
61
25
AD7 P3.7
8396
60
26
AD8 P40
8097
59
27
AD9 P4.1
28 1----------, AP10 P4 2
58
8397
57
29
AD11 P4.3
56
30
AD12 P4.4
55
31 1 = = = .AD13 P4.5
54
32
AD14 P4.6
53
33
AD15 P4.7
52
34
T2CLK P2.3

1---=

~W~~~%eMgQ~~~~D~e

I
IL

Figure 3. S8-Pin Package (Flat Pack·Top View)

5-2

inter

1jil1Rl~[bJ Iil:jj)~ INlfo\lRl'1f

8096

Pins Facing Down

Pins Facing Up

3
4

"'-

1
2 68

17
19

68 67

67 68

64 65

22 23

65 64

5
6

7
8

9
10

11
12

13
14

15
16

MCS®-96
68 PIN
GRID ARRAY

52, 53 50
51 49

48
47

46
45

43 41

40 38
39 37

11
12

5
6

15 )3
16 14

7
8

/1
68 2

9
10

MCS®-96
68 PIN
GRID ARRAY

63 62
61

28 29

30 31

36
35

34 36

38 40 42
37 39 41

46
45

48 50 53 52
47' 49 51

Figure 4. Pin Grid Array
Note
I '. When the pin grid array package is mourtted on the PC board, the pins are numbered counterclockwise as seen from the component
side of the board, just like the nat pack when it's mounted in the contactor. Consequently, the PC board layout for pin grid array is
compatible with the nat pack in a contactor except for the footprint size. The pin functions (from -1 to -68) on both packages are
identical. Refer to Intel's Microcontroller handbook for mechanical dimensions on these packages.

5-3

inter

,8096
Table 3-1. InstructIon Summary

MnemonIc

D~B+A

2
2

o +-D+A+C

D~D-A

3
2'

D+-B-A
D+-O-A+C- I
D-A

2
3,

ADDC/ADDCB
SUB/SUBB
SUB/StJBS'

0,0+ 2 +- 0
0,0 +

MULB/MULUB
DIV/DIVU

3
2
3
2

DIVB/DIVUB

AND/ANDB
AND/ANDB

2
3
2

OR/ORB
XOR/XORB
LD/LDB
ST/STB
LDBSE
LDBZE
PUSH

pop
PUSHF
POPF
SJMP
UMP
BR(indirect)

0,0+
0,0+
o +- (0,0 + 2)/A
0+2
remainder
o +- (0, 0 + I)/A
0+1
remainder
D ..... OandA
o +- B and A

D+-A
A<-D
o +-A; 0 + I <- SIGN(A)

2
I

o <-A; 0

I
I
I

LCALL

RET
J(conditional)

0
I
I
I

+ I+-O
SP +- SP - 2; (SP)

A
A +- (SP); SP +- SP + 2
SP +- SP - 2; (SP) +- PSW;
PSW +- OOOOH
PSW +- (SP); SP +- SP + 2

0
0

?
?
?
?

i -

0 0
0

- -

2
2

3
3
2

- - j j 0 0 - - - - - - - - - - - - - - - - - - - - -

2
2
2

0
I

j
j

- - -

I
0

j
j
j

i
i
i
i
i
i
i

- - - - - - - - - - - - - - -

D+-DorA
0+-0 (excl. or) A

SCALL

JC
JNC

t .;
J J

*A
2 ~ B *A
1+-0 * A
I+- B * A

MUUMULU
MULB/MULUB

Z N C V VT ST Notes:

OperatIon (Note 1)
D~D+A

ADD/ADDB
ADD/ADDB

SUBC/SUBCB
CMP/CMPB
MUUMULU

Flags

Operands

3,4
3,4

1+-0
I+-j

- - - - - -

- -

PC <- PC + 8"bit offset
Jump ifC = I

- - - - -

Jump ifC = 0

- -

PC+-PC+ II-bit offset
PC +- PC + 16-bit offset
PC +- (A)
SP +- SP - 2; (SP) +- PC;
PC +- PC + II-bit offset
SP +- SP - 2; (SP) +- PC;
PC +- PC + 16-bit offset
PC <- (SP); SP <- SP + 2

- -

5
5

Note
I. If the mnemonic ends in "B", a byte operation is perfonned. otherwise a word operation is done. Operands D, B. and A must conform
to the alignment rules for the required operand type. D and B are locations in the register file; A can be located anywhere in memory.

2.
3.
4.
S.

D. D + 2 are consecutive WORDS in memory; D is DOUBLE-WORD aligned.
0, D + I are consecutive BYTES in memory; D is WORD aligned.
Changes a byte to a word.
Offset is a 2' s complement number.

8096
Table 3-2. Instruction Summary

Mnemonic

Operands

Flags
Z N C V VT ST Notes
5
- - - - - 5
- - - - - 5
- - - 5
- - - - - 5
- - - - 5
- - - - - - - - 5
5
- - - - - 5
- - - - - 5
- - - - - - - - - 0 5
- - - - 0 5
5
- - - - - 5
- - - - - -

Operation (Note 1)

=1
=0

JumpifZ

JNE

Jump ifZ

JOE

Jump ifN = 0

JLT

Jump ifN = 1

= 0 and Z = 0

JOT

Jump if N

JLE

Jump if N = 1 or Z = 1

Jump if C = 1 and Z = 0

JNH

JumpifC = OorZ = 1

Jump if V = 1

JNV

Jump if V = 0

JVT

Jump if VT

JNVT

Jump if VT = 0; Clear VT

JST

Jump if ST = 1

JNST

Jump if ST = 0

JBS

Jump if Specified Bit

JBC

Jump if Specified Bit = 0

DJNZ

D +- D - 1; if D*-O then
PC +- PC + 8-bit offset

DEC/DECB

D+-D-l

NEG/NEGB

D ..... O-D

INC/INCB

D+-D+l

EXt

D <- D; D + 2 +- Sign (D)

EXTB

D <- D; D + 1 <- Sign (D)

NOT/NOTB

CLRlCLRB

SHLlSHLB/SHLL

C ..... m s b - - - - - l s b <-0

SHRlSHRB/SHRL

O~msb-----lsb~

SHRNSHRAB/SHRAL

msb~ msb-----lsb~

SETC

C <-1

CLRC

C+-O

CLRVT

VT ..... O

RST

PC <- 2080H

Disable All Interrupts (I <- 0)

Enable ·All Interrupts '(I ..... 1)

NOP

PC <-PC + 1

SKIP.

PC <-PC + 2

NORML

Normalize (See sec 3.13.66)

TRAP

SP <- SP - 2; (SP) <- PC; PC +(201OH)

= 1; Clear VT

- - - - -

5,6
5,6

- ./ ./ ./
./ ./ ./
./ ./ ./
./ ./ 0

- -

./ t
./ t
./ t

D <- Logical Not (D)

./ ./
./ ./

D <-0

C
C

./ ? ./ ./ t ./ 0 ./ 0 - ./
./ ./ ./ 0 - ./
- - 1 - - - - 0 - - - - 0 -

7
7
7

- - - - - - - - - - - - - - - - - - - - ./ 1 0 - - -

- -

7
9

Note
1. If the mnemonic ends in "B", a byte operation is performed, otherwise a word operation is.done. Operands D, B and A must conform
to the alignment rules for the required operand type. D and B are locations in the register file; A can be located anywhere in memory.
5. Offset is a 2' s complement number.
6. Specified bit is one of the 2048 bits in the register file.
7. The "L" (Long) suffix indicates double-word operation.
8. Initiates a Reset by pulling RESET low. Software should re-initialize all the necessary registers with code starting at 2080H.
9. The assembler will not accept this mnemonic.

5-5

8096

Table 3-3. Opcode and State Time Listing
DIRECT

I..)

INDIRECT@

IMMEDIATE

NORMAL

INDEXED@

AUTO·INC.

SHORT

LONG

I/)

z
ca:
UJ

UJ
Q

8
D..

.1/)

UJI/)
!cc UJ

UJ
Q

I..)

I/)

UJI/)
!cc UJ

D..

!
>1/)1m ....

UJ
Q

I/)

I..)

UJ
I-

!BI/)

UJUJ

!cc:e

I/)

el/)
UJUJ

!cc:e

UJ
Q

I..)

I/)

el/)

WIIJ

I/)

el/)
UJUJ

.... m 1/)1-

!cc:e

!cc:E

~i=

7/12

.... !
>m 1/)1-

ADD

6/11

7/12

6/11

ADD

7/12

8/13

7/12

8/13

ADDB

6/11

7/12

6/11

7/12

D..

>m.

D..

0_.

~i=

D..

ARITHMETIC INSTRUCTIONS

ADDB

7/12

8/13

7/12

8/13

ADDC

6/11

7/12

6/11

7/12

ADDCB

6/11

7/12

6/11

7/12

SUB

6/11

7/12

6/11

7/12

SUB

7/12

8/13

7/12

8/13

SUBB

6/11

7/12

6/11

7/12

SUBB

7/12

8/13

7/12

8/13

SUBC

6!ll

7/12

6/11

7/12

SUBCB

6/11

7/12

6/11

7/12

CMP

6!ll

7/12

6/11

7/12

CMPB

6/11

7/12

6/11

7/12

MULU

27/32

28/33

27132

28/33

MULU

28/33

29/34

28/33

29/34

MULUB

19/24

20/25

19/24

20/25

MULUB

20/25

21126

20125

21126

MUL

31136

32/37

31/36

32/37

MUL

MULB

®
®
®
®

DIVU

DIVUB

32/37

33/38

23/28

24/29

25/30

®
®
®
®

28/32

29/33

20/24

32/36

®
®

24/28

®
®
®
®

®
®

®
®
®
®

DIV.

DIVB

®
®

Notes:

32/37

33/38

23128

24/29

25/30

28/32

29/33

21125

20/24

21125

33/37

32/36

33/37

25/29

®
®

24128

25/29

Long indexed and Indirect + instructions have identical opocodes with Short indexed and Indirect modes, respectively. The second byte
of instructions using any indirect or indexed addressing mode specifies the exact mode used. If the second byte is even, use Indirect
or Short Indexed. If it is odd, use Indirect + or Long indexed. In all cases the second byte of the instruction always specifies an even
(word) location for the address referenced.
<\) Number of state times shown for internal/external operands.
@ The opcodes for signed multiply and divide are the opcodes for the unsigned functIOns with an "FE" appended as a prefix.

5·6

inter

.8096
Table 303. Continued
DIRECT

u
Z

::E

II:

::E

AND

2
3
2
3
2
2
2
2

w
A.

INDEXED@
SHORT
LONG

INDIRECT@
NORMAL
AUTO-INC.

IMMEDIATE

~f3

U)
w WU)

f t:ID U)ti!1 0f t:ID

tel 0f

~I=

8U)

w Ww
t:ID !c::E1=

.:n

8U)

w Ww

t:ID !c::E
:nl=

w
Q

8U)

w Ww

U
A.

!c::E ~ !c::E
t:ID :nl=
ID :nl=

63
43
73
53
83
93
87
97

4
5
4
5
4
4
4
4

5
6
5
6
5
5
5
5

7/12

LOGICAL INSTRUCTIONS

AND
ANDB
ANnB
OR
ORB
XOR
XORB
LD

LOB
ST
STB
LDBSE
LDBZE

2
2
2
2
2
2

3
4
3
4
3
3
3

70
50
80
90

AO
BO
CO
C4
BC
AC

3
j

3
3
3
3

4
5

4
5
4
4
4
4
4
4
4
4
4
4

61
41
71
51
81
91
85
95

4
5
3
4
4·
3
4
3

5
6
4
5
5
4
5
4

62
42

Al
BI

4.
3

5
4

A2.
B2
C2
C6
BE
AE

7/12

6/11

3'
4
3
4
3
3

6/11

7/12

6/11

3
4
3
4
3
3

52
82

7/12
6/ll
7/12
6111

8/13
7/12
8/13
7/12
7/12

96 3 6/11
3 7/12
DATA TRANSF!ER !N~T~UCTION!3

BD 3
AD 3

4
4

3
3
3
3
3
3

6/11
6/11

7/11
7/11
6/11
6/11

3
3
3
3
3
3

7/12
7/12
8/12
8/12
7/12
7/12

6/11

7/12
6/11
7/12
6/11
6/11
6/11
6/11

4
4
4
4
4
AF 4

6111

8/13
7/12
.8/13
7/12
7/12
7/12
7/12
7/12

6/11

5
5
5
5
5
5

CB 3
CF 3

IIIi5
14/1S

4
4

12/16

CB 3
CF j

15/19.

4
4

16/20

A3
B3
C3
C7
BF

6/11
7/11
7/ll
6/ll

7/12
8/12
8/12
7/12
7/12

STACK OPERATIONS (Internal stack)

PUSH
POP
PUSHF
POPF

I
I
0
0

C8 2
CC 2
F2 I
F3 I

8
12
8
9

- -

CA 2
CE 2

11115
14/18

2
2

12116
14/18

14/18

STACK OPERATIONS (external stack)

PUSH
POP
PUSHF
POPF

I
I
0
0

C8 2
CC 2
F2 I
F3 I

12
14
12
13

- -

CA 2
CE 2

15/19
16/20

2
2

16/20
16/20

16/20

16120

JUMPS AND CALLS
MNEMONIC

UMP
SIMP
BR[]

OPCODE

E7
20-27@
E3

BYTES

STATES

3
2
2

8
8
8

Notes:

MNEMONIC OPCODE
LCALL
EF

SCALL
RET

28-2F@
FO

TRAP@

BYTES

STATES

3
2
I
I

13/16@
13/16@

I2II6@

(j) Number of Slate times shown for mtemal/extemal operands.
~

The assembler does not accept this mnemonic.

The least significant 3 bits of the opc!lde are concatenated with the following 8 bits to form an

relative call or jump.
@ Slate times for stack located intemallextemal.
!B> The assembler uses the generic jump mnemonic (BR) to generate this instruction.

5-7

II-bit, 2's complement, offset for the
.

inter

8096
Table 3-4. CONDITIONAL JUMPS
All condi,ional Jumps are 2 1;lyte instructions. They require 8 state' ilmes if the Jump is taken, 4 if it is not.

MNEMONIC

JC
JNC

OPCODE MNEMONIC OPCODE MNEMONIC OPCODE MNEMONIC OPCODE

'OB
03
09
01

JNH

JE
JNE
JV
' JNV

OF
07
00
05

JOE
JLT
JVT
JNVT

06
.DE
OC
04

JOT
JLE
JS:r
JNST

02
OA
08
00

JUMP ON BIT CLEAR OR BIT Si!T
These instructions are 3-byte instructions. They require 9 state times If the Jump is taken, 5 if it is not

MNEMONIC

JBC
JBS

BIT NUMBER
4
3

30
38

31
39

32
3A

33
3B

34
3C

35
30

36
3E

37
3F

lOOP CONTROL

DJNZ

OP~OOE

EO;

5/9 STATE TIMES (NOT TAKEN/TAKEN)

3 BYTES;

SINGLE REGISTER INSTRUCTIONS
MNEMONIC

OEC
OECB
NEG
NEGB
INC
INCB

OPCODE

BYTES

STATES

2
2
2
2

07
17

4
4
4
4
4
4

. 05
15
03

MNEMONIC OPCODE

EXT
EXTB
NOT
NOTB
CLR
CLRB

06
16
02
12
01
,

BYTES

STATES

2
2
2
2
'2
2

4
4
4
4
4
4

SHIFT INSTRUCTIONS
INSTR
MNEMONIC

SHL
SHR
SHRA

WORD
OP
B
09
3

08
OA

INSTR
BYTE
MNEMONIC OP
B

SHLB
SHRB
SHRAB

3
3

19
18
1A

3
3
3

DBl 'WD
INSTR
MNEMONiC OP
B

SHLL
SHRL
SHRAL

00
OC
OE

3
3

STATE TIMES

7 + 1 PE~ SHIFT(£)
7 + 1 PER SHIFT(£) ,
7 + 1 PER SHIFT(£)

SPECIAL CONTROL INSTRUCTIONS
OPCODE

BYTES

SETC
CLRC
CLRVT
RST

MNEMONIC

F9
F8
FC

1
1
1
1

NORML

STATES

4
4
4
16

MNEMONIC 'OPCODE
Dl
FA

EI
NOP
SKIP

FO
00

BYTES

STATES

1
1
1
2

4
4
4
4

NORMALIZE
3

11 + 1 PER SHIFT

No~:

® This instruction takes 2 states to pull RST low, then holds it low for 2 states to initiate a reset. The reset takes 12 states, at whIch

cr>

time the program restarts at location 2080H.
Execution will take at least 8 states. even for 0 shift.

'5·8

inter

8096

ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS,

'NOTICE Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device, ThiS IS a'stress rating only and functional operation of
the device at these or any other conditions above those
indicated In the operational sections of thiS specificatIOn IS
not Implied Exposure to absolute maximum rating conditions for extended periods may affect deVice reliability

Ambient Temperature Under Bias .......... O°C to +70°C
Storage Temperature ... , ............ -40°C to +150°C
Voltage from Any Pin to V$S or ANGND ... -0 3V to +7 OV
Average Output Current from Any Pin ........... 10 mA
Power Dlsslpa,tlon ......................... 1 5 Watts

OPERATING CONDITIONS
Symbol

Ambient Temperature Under Bias

VCC

Digital Supply Voltage

VREF

Analog Supply Voltage

fOSC

OSCillator Frequency

VPD

Power-Down Supply Voltage

Max

Units

+70

450

550

45
VCC-O,3

55
VCC+03

V
V

MHz

450

550

Parameter

Min

I
I

VBS Should be connected to ANGND through a 0 01 pF capacitor ANGND and VSS should be nominally at the same potential

DC CHARACTERISTICS
Parameter

Symbol
Input Low Voltage

VIL

Min

Max

Units

-0.3

+0.8

Test Conditions

VIH

Input High Voltage (Except RESET)

2.0

VCC+0.5

VIH1

Input High Voltage,

Ri:ID Rising

2.4

VCC+0.5

VIH2

Input High Voltage, ~ Falling

2.0

VCC+0.5

VOL

Output Low Voltage

VOH

Output High Voltage

ICC

VCC Supply Current

200

All outputs
disconnected.

IPD

VPD Supply Current

Normal operation
and Power-Down.

0.45

2.4

IREF

VREF Supply Current

III

Input Leakage Current to all pins of HSI, PO, P3,
P4, and to P2.1.

IIH

Input High Current to EA

ilL

Input Low Current to all pins of P1, and to P2.6,
P2.7.

IIL1
IIL2
Cs

Pin Capacitance (Any Pin to VSS)

±10

See Note 1.
See Note 2.

p.A

Vin=O to VCC
See Note 3

100

p.A

VIH=2.4V

-100

p.A

VIL=0.45V

Input Low Current to ~

-2

VIL=0.45V

Input Low Current P2.2, P2.3, P2.4, READY

-50,

p.A

VIL=0.45V

fTEST=1MHz

NOTES:
IOl ~ 036 rnA for all PinS of P1, for P2 6 an'd P2 7, and for all pins of P3 and P4 when used as ports
IOl ~ 20 rnA for TXD, RXD (In senal port mode 0), PWM, ClKOUT, ALE. SHE. RD, WR, and all pins of HSO and P3 and P4 when used
as external memory bus (ADO-AD1S)
2 IOH

-20 p.A for all pins of P1, for P26 ad P2 7

IOH ~ - 200 p.A for TXD, RXD (In senal port mode 0), PWM, CLKOUT, ALE, SHE, WR, and all pins of HSO and P3 and P4 when used
as external memory bus (ADO-AD1S)
P3 and P4, when used as ports, have open·draln outputs
3 Analog Conversion not In process

5-9

inter

8096

AID CONVERTER SPECIFICATIONS
. Resolution ............................................ :!: 0.001 VREF
Accuracy ................... , ......... " ............... :!: 0.004 VREF
Differential nonlinearity ................ :!: 0.002 VREF max
Integral nonlinearity ..................... :!: 0.004 VREF max
Channel-to-chanel matching .................. " ..... :!: 1 LSS
Crosstalk (DC to 100kHz) ...................... - 60dS max

AID Converter operation is verified only on the 8097,
8397, 8095, 8395.
The absolute conversion accuracy is dependent on the
accuracy of VREF. The specifications given below assume adherence to the Operating Conditions section
of these data sheets. Testing is done at VREF = 5.120
volts.
. .

AC CHARACTERISTICS
Test Conditions: Load capacitance on output pins = 80pf
Oscillator Frequency = 12.00 MHz
4.50 Volts, = VCC ,= 5.50 Volts; 0 C ,= Temperature, = 70 C
Timing Requirements (other system components must meet these specs)
Min

Parameter

Symbol
TCLYX

READY Hold after CLKOUT falling edge

TLLYV

End of ALE to READY Setup

TLLYH

End of ALE to READY high

TYLYH

Non-ready time

TAVDV

Max

o (1)

Units
nsec

2Tosc-60

nsec

4Tosc-60 (2)

nsec

1000

nsec

Address Valid to Input Data Valid

5Tosc-80

nsec

TRLDV

RDf Active to Input Data Valid

3Tosc-60

nsec

TRXDZ

End of RDf to Input Data Float

Tosc-20

nsec

Units

Timing Responses (MCS®-96 parts meet these specs)
Symbol
FXTAL

Parameter
Oscillator Frequency

Min

Max

6.00

12.00

MHz

166

nsec

Tosc

Oscillator Period

TCHCH

CLKOUT Period

3Tosc (3)

nsec

TCHCL

CLKOUT High Time

Tosc-20

Tosc+20

nsec

TCLLH

CLKOUT Low to ALE High

-5

nsec

TLLCH

ALE Low to CLKOUT High

Tosc-20

Tosc+40

nsec

TLHLL

ALE Pulse Width

Tosc-25

Tosc+ 15

nsec

TAVLL

Address Setup to End of AI-E

Tosc-50

nsec

TLLRL

End of ALE to RDf or WRf activE1

Tosc-20

nsec

Address hold after End of ALE

Tosc-20

nsec

TWLWH

WRf Pulse Width

2Tosc-35

nsec

TQVWX

Output Data Setup to End of WRf

2Tosc-60

nsec

TWXQX

Output Data Hold after End of WRf

Tosc-25

nsec

TWXLH

End of WRf to next ALE

2Tosc-30

nsec

TRLRH

RDf Pulse Width

3Tosc-30

nsec

TRHLH

End of RDf to next ALE

Tosc-25

,!lsec

TLLAX.

NOTES:
1. If the 48-pin part is being used then this timing can be generated by assuming that the CLKOUT falling edge has occurred
at 2Tose + 55 (TLLCH(max) + TCHCL(max)) after the falling edge of ALE.
2. If more than one wait state is deSired, add 3Tosc for ~aeh additional wait state.
3. ,CLKOUT is directly generated as a divide by 3 of the oscillator. The period will be 3Tosc :!: 5 nsec if rose is constant and
!he rise and fall times on XTAL 1 are less than 10 n~e.
'

5-10

inter

8096

I
,
,,

_TCHCH

CLK OUT

---J

---"\

I
I
I

TCHCL

TYVCL

I-

TCLLH

)

REA DY

_TCLYX

VALID

TLLCH
TLHtL

TYLYH

ALE

_TLLYV-"

TLLRL

TRHLH

TRLRH

-,
TRXDZ

TAVLL

I-

TLLAX
!-TRLDV_

ADDR OUT

DATA IN

TAVDV

TlLRL

f - !-TWLWH

WR
TAVLL

,TW)'LH_

~
TLLAX
TWXQX

_TQVWX

ADDR OUT

DATA OUT

,INST

VALID

5-11

MCS®,96 Article Reprint.

'.'"

,'I' ,
'

ARTICLE
iREPRINT ~
,

AR~321

February 1984

Reprinted from DIGITAL DESIGN © February 1984, Morgan.Grampian Publishing Company

6-1

. Order Number. 231040.001

COMPONENTS

High-Performance Event
Interface For A Microcomputer
As silicon technology advances to provide
denser geometries, timer structures have
become mOre elegant and powerful.
High Speed Input Unit
Microcontrollers are microprocessors
specially configured to monitor and control mechanisms and processes rather
than manipulate data. The systelljs they
are imbedded in are often called real
time control systems; microcontrollers
always incorporate some form·of timer
structure to allow synchroniza\ion .with
the outside or 'real' world .. As silicon
technology advances to provide denser
geometries, these structures have become
more elegant and powerful.
This trend can be seen in the Intel
8048, the Motorola 6801, and the Intel
8051 which were introduced at approxImately two and a half year intervals
starting in 1976. The 8048 has a single
8-bit timer; the 680 I has a 16-bit timer,
and the 8051 has two 16-bit timers. The
new 16-bit microcontroll~r from Intel,
the 8096, has an independent High
Speed I/O subsystem which provides
the functionality of four to eight 16-pit
timers. While this subsystem is designed
to provide an integrated approach to
measuring and controlling time modulated signals, -it is easier to describe as
separate input and output units.

The purpose of the High Speed Input
unit is to allow the measurement of the
periods of incoming pulse or frequency
modulated inputs with high resolution
and minimal software overhead. A block
diagram of the hardware used to
accomplish this goal is shown in Figure
l. the heart of this unit is a programmable change detector which monitors
.the four I/O pins of the 8096 which are
ctesignated as "High Speed Inputs"
_(HSI.O-HS1.3).
The operatIng mode of the change
detector IS controlled by a byte register
which can be written as register 3 of the
onboard register file. This register has
the prededare9 mIme HSLMODE in
the 8096 assembly language. The register contaInS a separate field for each of

the four HSI pins. There are two bits in
each of these fields and they are encoded
as follows:
•
•

00 Capture every eighth positive
transition
0 I Capture positive transitions
only
10 Capture negative transitions
only
II Capture both positive and
negative transitions

It is also possible to disconnect one or
more of the HSI pins from the change
detector by writing into one of the two
I10 control registers. This register,
known to the assembly language as
lOCO is addressed as register 15H of
the on-board register file. HSI pins th~t

Changes (4)

HSIO
HSI1
HSI2

Control
Event
FIFO
,(8x.20)

Figure 1: Diagram shows the HIgh-Speed Input Unit which is used to measure incoming pulse
or frequency modulated InputS.

6-2

Microcompule(

interrupt can be generated either when
one or more entries exist in the FI FO or
when seven or more entries exist. The
choice is made by the software by setting
a bit in I/O control register I (lOCI).
The 8096 only &UPports byte and
word operands for most operations.
The holding register is 20 bits wide
hence the holding register is broken
down into two registers. The 16-bit time
field is read as a word register and is
known as HSLTlME to the assembler.
The change informati'on is read as an
eight-bit byte known as HSLSTATUS.
The four extra bits in this byte are used
to report the state of the HSI pins at the
time the register is read (not at the time
the reported change occurred). The
holding register is cleared after the HSL
TIMEis read so that HSLSTATUScan
be read at any time to monitor the
actual state of the HSI pins without
losing data from the FIFO.

RESET

HSOO
HSOl
HS02
HS03
HS04
HS05

~----------~------------~~DBUS

Figure 2: Block diagram of the High Speed Output hardware.

have to be disconnected from the change
detector are available for use as normal
digital inputs and two of them (HSI.2
and HSI.3) can be used by the High
Speed Output unit.
When a change (or changes) of the
required type occurs, four bits of change
information, along with the current
value of T1MERI, are loaded .into
a FIFO (first-in, first-out memory).
Each set bit in this field indicates that a
change occurred on the corresponding
input pin.
The time reference for the HSI unit is
T1MERI, a sixteen bit counter which is
incremented every eight state times by
the CPU clock. With a 12 M Hz crystal
this gives a resolution of 2.0 microsec-

onds. TI M ER I is cleared by reset and
then starts incrementing. It cannot be
, written to by the software but can be
. read as a sixteen bit word at any time.
When its count goes from all ones to
zero a flag is set and an interrupt generated. The software can use this flag
and/ or interrrupt to extend the meas, urement range of the HSI unit.
The FIFO that is used to store the
change and time information is eight
levels deep (including the holding register) and 20 bits wide. The oldest entry in
the FIFO is placed in the holding register. When the holding register is read
then the next oldest entry will drop into
it and another cell of the FIFO will
become available for input data. An

High Speed Output Unit
The High Speed Output unit serves the
output reqUirements of the system in the
same way as the HSI unit serves the
mput. It allows the generation of pulse
and frequency modulated Signals with
high resolutIOn and mmimal software
overhead. It can also be used to generate
time delays for the operating software
and to trigger the AI 0 converter at precise time intervals for signal processing
algonthms. A block diagram of the
HSO hardware IS shown in Figure 2.
The HSO unit is dnven by a Content
Addressable Memory (CAM) which is
23 bits wide and eight levels deep The
(contmued on page 120)

o
I TID I

Channel Code

I
T2 ClK -

0-5 HSO.O - HSO 5
6 HSOOAnd HSO 1
7 HSO 2 And HSO 3

...... HSll
- - - - -lOCO?

8-8 Software Timers
E
F

Reset Timer 2
Start AID Conversion

T2RST

'-----lnterruptlNo Interrupt
L..._ _ _ _ _ _

110 Data For HSO X

IOC05
L...___________ Tlmer

2!Tlmer 1

Figure 3: DIagram showsformat of Command Tag . .The lower four
bits specify the basic operation and the remaimng three bits are
options 10 the basIC operation.

FI!(ure4 Figure ,hOH \ tJw c!t)cA. and re\el 0P(/On.\ of TIM ER2 used
hI' the Htl(h Speed Ourpurl/nil

6-3

Microcomputer

23 bits are broken into a 16 bit time tag
and a seven bit command tag. The
command tag tells it when to do it. The
format of the command tag is shown in
Figure 3. The lower four bits of the tag
specify theba~ic, operation and the
remaining three bits specify options to
the basic operation. The ba~ic operations supported are:

•

Write to one of the six pins controlled by the HSO unit (HSO.OHSO.5).
Write to HSO.O and usa. I with
a single command.
Write to HSO.2 and HSO.3 with
a single command.
Set one of four software timer
flags.
Reset Timer 2.
Trigger an AI D conversion.

If an operation on an HSO pin is
specified. then the value to be written to
the pin is taken from bit five of the
'command tag. Note that if two HSO
pins are to be modified with the same
command then both will be set to the
same state. Bit five of the command tag
is ignored for the other HSO operations. Bit four of the command tag enables the generation of an interrupt
which occurs when the command is
executed.
There are two interrupts generated by
the HSO unit. One of them indicates
that an operation involving a HSO pin
has occurred. and the other is used to
signal that one of the internal HSO
functions (such as setting a software
timer flag) has been completed. Bit six
of the command tag controls which {lne
of the two timers available to the HSO
unit will be used as a time base for the
command. If bit six is a zero then the
command tag will be executed when
TIMERI becomes equal to the time tag
stored in the CAM. If bit six is a one
then the command tag is executed based
on TIMER2. In either case the command is flushed from the CAM as soon
as it is executed.
One of the timers (TIMERI) used by
the HSO unit is the same timer that is
used by the HSI unit. The other
(TIMER2) is used only by the HSO
unit. TIMER2 allows HSO events to be
generated on a time base that is different
from that ofthe CPU. Like TIMERI it
is a 16 bit counter that can be read but
not written to by the software. It also

has an overflow flag and interrupt to
indicate that it has incremented from a
source external to the 8096 and can be
reset by a number of paths in addition to
system reset. The options available are
shown in Figure 4.
The clock input can come either from
a specific pin designated as the T2CLK
or it can come from HSI.l depending
on the state of lOCO.; which is set by the
software. In either case the counter is
incremented on both edges of the clock
signal. TIMER2 can be reset by a specific pin designated as T2RST or it can
be reset by HSO.O. It is also possible for
the software to lock out external sources
of reset (by clearing IOCO.3) andlor
reset TIMER2 directly (via lOCO. I) or
indirectly via a command stored in the
CAM. Note that this last possibility
allows TIMER2 to be configured as a
modulatjon counter since the software
can command the HSO unit to clear
TIMER2 when it reaches a given value.
Commands are loaded into the CA M
from the 23 bit wide holding register·
which. like the holding register for the
HSI unit, is actually made up of a byte
register (HSO_COMMAND) which
stores the command tag and a word
register is considered loaded after HSO_
TIME is loaded so the software must
always load HSO_COMMAND and
then load HSO_TIME.
]be software must also ensure that
the loading of the two registers is not
interrupted by an interrupt service routine which uses the HSO unit. If such an
interrupt occurs immediately following
the loading of HSO_COMMAND then
the subsequent loading of HSO_TIME
will reload the command tag written
into the holding register by the interrupt
service routine. The safest procedure is
to lockout interrupts during the loading
of the holding registers, however a care-

ful examination of the control flow of
the program may show this to be
unnecessary.
If there is an empty cell in the CAM
when the holding register is loaded then
the command and its time tag will be
loaded into the CA M within seven state
times (1.75 microseconds at 12 MHz). It
is important to note that a command
will not execute from th~ holding register, it must be loaded into the CAM. If
the CAM is full then the command will'
remain in the holding register until one
of the commands already in the CAM is
executed and flushed.
Two status flags are available to help
the software manage the CAM. One of
them indicates that the holding register
is full or the CAM is full. Once a command is loaded into the CAM it cannot
be read or overwritten, it can only be
flushed after it is executed. To support
those situations where the software
wishes to cancel a command after it has
been loaded, the HSO unit is configured
so that two operations to a HSO pin
which cancel each other will not effect
the setting of the pin if they are executed
with identical time tags.

Application Example
Since the 8096 incorporates a full duplex
asynchronous serial port in its hardware
it may seem strange that one would
want to implement a software driven
serial port using the high speed 110 features. There are, however, many useful
configurations of microcontroller systems which in fact require more than a
single serial port. An obvious example
would be a network of 8096 controllers
which use the hardware serial port for
interprocessor communications. One (or
more) of these controllers might also be
required to communicate with a CRT
terminal used to supervise or monitor

1 10<02:03:0<05:06:07:081
T"0

Figure 5: FIgure shows
standard /O-bit asyn-

chronous frame.

~~J

+1 (+3 (

+5 (

+7 (:)
+9 ( !)
+11 ( ~)
')
+13' (T

')
+15 (T

+17 (+19 (,')

6-4

Micro! omputer

The serial output
process is simpler
than the receive
process because
there is no need to
synchronize with
the outside world.
the system. Another example would be
a simple CRT terminal design based on
an 8096 which needs one $erial port for
communication and another for driving
a slave printer. It l!1lI.y also be true that
this is, in fact, a strange requirement. In
any case it is an excellent example to
show how the high speed 110 features of
the 8096 might be used.
The objective is to add a software
driven asynchronous $erial port to the
8096 that provides full duplex $eriai
communication at 2400 baud. A standard frame consisting of a START bit,
eight data bits and a STOP bit will be
assumed. A high speed input pin
(HSI.O) will be used for received data
and a high speed output pin (HSI.O) for
transmit data.
A standard to-bit asynchronous frame
is shown in Figure 5. The figure also
shows the points in time where the
receive process must sample the incom-

ing data stream and take some action.
timer interrupt at the appropriate time.
The first timing point (labeled T.o) is the
This is done in all states unless the recepleading edge of the start bit, the accurate
tion of the character is complete or a
sensing of this edge is important becau$e
false START bit has been detected.
all subsequent sample times are relative
Under these conditions the receive proto this edge. This event also places the
cess must be reinitialized by enabling
highest burden on the sampling algoHSJ.O into the event FIFO (by setting
rithm because it can occur at any point
IOCO.O) instead ofretriggering the softin time. The rest of the sampling events
ware timer.
occur at some multiple of one-half a bit
The serial output process is simpler
period relative to the edge of the start bit.
than the receive process because there is
The diagram uses the symbol B to
no need to synchronize with the outside
represent a bit period.
world. A transmission can be started at
At the second sample, which occurs
any time by setting the TxD line to a
half way through the start bit, the data
space for one bit time to form the
must be checked to make sure it is still a
START bit. Following the START bit
SPACE. If it is not. a noise pulse has
are the eight data bits and the STOP bit.
caused a false start and the receive proThe HSO interrupt service routine can
cess must be reinitiali7ed. The next eight
be used to transmit the data and the stop
samples are used to shift in the serial
bit but the transmit process must be
data stream. The last sample. which
initialized.
occurs 19 one-half bit times after the
The only real complication in the HSO
leading edge of the start bit. is used to
interrupt service routine is that there are
verify that the stop bit is valid (Le. it is in
no flags available in the 8096 which
the MARK state). If it is not thea framindicate which of the HSO outputs
ing error must be reported since it is _ caused the interrupt. In many systems
likely that the' receiver is not properly
this does not represent a problem
synchronized with the transmitter.
because the HSO unit can be treated as
a write only device. It is given comThe HSI unit is an ideal mechanism
mands which are to be executed at the
for detecting the leading edge of the start
proper time but no feedback is required
bit. All that needs to be done is to set the
to indicate when the proper time has
mode register to detect negative going
been reached. In this case, however, the
edges on HSI.O.
feedback is required since the CAM isn't
The software timer interrupt service
deep enough to hold all of the transiroutine implements a simple state
tions required for a character. Even if it
machine based on the variable count.
were big enough it is unlikely that so
The routine also arranges for the next
,many CAM locations would be dedisample by issuing a command to the
HSO unit to generate another software
0
cated to serial output.

6-5

MCS®~51

Architecture

CHAPTER 7
MCS®-S1 ARCHITECTURE
7.0 INTRODUCTION
The MCS®-51 family of S-bit microcontrollers consists of
the devices listed in Table I, all of which are based on
the MCS-51 architecture shown in Figure 7-1. The original
S051 was built in HMOS I technology. The HMOS II
version, which is the device currently in production, is
called the S05IAH. The te~ "S051," however, is still

often used to generically refer to all of the MCS-51 family
members. This is the case throughout this manual, except
where specifically stated otherwise. Also for brevity, the
term "S052" is used to refer to both the S052 and the
S032, unless otherwise noted.

PO.O-PO.7

,- - - - - - -

-1:ll!::H.:~

.......-L-L.L..L..L..t,- -

-- --,

I
I

~
-=

-- -

I
I

I
I
I

I
I

I
I
I
I
I ,..---=---,

I
I
I

I
I

I ,-,,=::.:..=::..J
I
I
I
I
I r-----.----,

I
I
I

PSEN

ALE

Ell

I
I

RST

I
I
I

Figure 7-1. MCS-51 Architectural Block Diagram

7-.1

MCS®-51 ARCHITECTURE

The newest MCS·51 members, the 8032 and 8052, have
more on-chip memory and an additional 16·bit timer/
counter. The new timer can be used as a timer, a counter,
or to generate baud rates for the serial port. As a timerl
counter, it operates in either a 16·bit auto· reload mode or
a 16-bit "capture" mode. 'This new feature is described
in Section 7.6.2.
Pinouts are shown in the individual data sheets and on the
inside back cover of this handbook.

Table 1. MCS®-S1 Family Members

PART

ON-CHIP ON-CHIP
PROGRAM
DATA
TECHNOLOGY MEMORY MEMORY

8051
8031
875lH

HMOS
HMOS

4K-ROM

HMOS I

NONE
4K-EPROM

80C51

CHMOS

4K-ROM

80C3!

CHMOS

8052
8032

HMOS
HMOS

NONE
8K-ROM

256

NONE

256

128
128
128
128
128

The major MCS@·51 features are:
• 8·Bit CPU
• On·Chip oscillator and clock circuitry
• 32 110 lines
• 64K address space for external data memory
• 64K address space for external program memory
• Two 16·bit timer/counters (three on 8032/8052)
• A five·source interrupt structure (six sources on
8032/8052) with two priority levels
• Full duplex serial port
• Boolean processor

Address
Name
Port 2
OAOH
Port 3
OBOH
Interrupt Priority Control
OB8H
Interrupt Enable Control
OA8H
Timer/Counter Mode
Control
89H
Timer/Counter Control
"TCON
B8H
+ "T2CON Timer/Counter 2 Control
OC8H
THO
Timer/Counter 0
(high byte)
8CH
TLO
Timer/Counter 0
(lOW byte)
BAH
TH1
Timer/Counter 1
(high byte)
BDH
TL1
Timer/Counter 1
(lOW byte)
BBH
+TH2
Timer/Counter 2
(high byte)
OCDH
+TL2
Timer/Counter 2
(lOW byte)
OCCH
+ RCAP2H Timer/Counter 2 Capture
Register (high byte)
OCBH
+ RCAP2L Timer/CoI,mter 2 Capture
OCAH
Register (low byte)
Serial Control
"SCON
98H
SBUF
Serial Data Buff
99H
PCON
Power Control
87H
Symbol
"P2
"P3
"IP
"IE
TMOD

The SFRs marked with an asterisk (*) are both bit· and
byte·addressable. The SFRs marked with a plus sign
( +) are present in the 8052 only. The functions of the
SFRs are described as follows.

7.1 MEMORY ORGANIZATION

ACCUMULATOR

The 8051 has separate address spaces for Program Mem·
ory and Data Memory. The Program Memory can be up
.to 64K bytes long. The lower 4K (8K for 8052) may reside
on·chip. The Data Memory can consist of up to 64K bytes
of off·chip RAM, in addition to which it includes 128
bytes of on·chip RAM (256 bytes for the 8052), plus a
number of "SFRs" (Special Function Registers) as listed
below.

ACC is the Accumulator register. The mnemonics for ac·
cumulator·specific instructions, however, refer to the ac·
cumulator simply as A .

Symbol
"ACC
*B
*PSW
SP
DPTR
"PO
"P1

Name
Address
Accumulator
OEOH
B Register
OFOH
Program Status Word
ODOH
81H
Stack Pointer
Data Pointer (con83H
slsting of DPH and DPL
82H
Port 0
80H
Port 1
90H

B REGISTER
The B register is used during multiply and divide opera·
tions. For other instructions it can be treated as another
scratch pad register.

PROGRAM STATUS WORD
The PSW register contflins program status information as
detailed in Figure 7·2.

STACK POINTER
The Stack Pointer register is 8 bits wide. It is incremented
before data is stored during PUSH and CALL executions.
While the stack may reside anywhere in on·chip RAM,

MCS~~------------~~--------~

,',

A. HMOS Configuration. The enhancement mode transistor is turned
on, for 2 os<:. periods after Q makes a 1-to-0 transition.

Q
FROM PORT
LATCH' , '
INPUT o-~-oC
DATA
READ
PORT PIN

B. :OHMOS, Conflguraiion. pFET 1 is turned on for 2 osc.
periods after Q ~akes a1-to-0 transitlon.,During this.
, time, pFET;1 also turns on pFET 3 throughthe inverter
" to for,m a latch which holds the 1. pFE,T,2!s also on.,'

:. .
~

,
"Fig~re 7:6. Por:ts and 3
and CHMOS Interrllil PlIII·up Configurations.
Port 2 is similar except that It,holds the strong pullup' on 'while emitting 1s that are address bits.
,,,
, ,(See text, "Accessing External Memory."): " "

HMos

about 0.25 rnA when shorted to. ground. In patallel with
the fixed pull-up is an enhancement-mode transistor,
whieh is' activated during SI' whenever the port' bit does
a O-to~ 1 transition. During this interval, if'the port pin is
shorted'th ground, 'this extra transistor' will allow the pin
to source an additional 30 rnA.
:

pFET 1 in Hgure 7-68 is ,the transistor,that.isturned on
for 2 oscillator periods af1;er a,6-to-l transition in the, port
latch. While it's on, it ruins on pFET 3' (a weak pull-up),
through the inverter. This inverter and pFET form a latch
which hold the 1.
'
'

In 'the CHMOS, versions; the pull-up consists of three
pFETs: It should be noted that an n-cl!annel FET (nFET)
~s turned on when a ,logical '1 is applied to its ghte, and '
is 'tubieg qff whim a logical 0 is applied to its gate. A pchanriel FET: (pFET) is the opposite: it is on when its gate
s~e~ a O,:and off ~hen its gate Sees a,l.

-7-7

Note that if the pin is emitting aI, a negative glitch on
the pin from some external source can tum off pFET 3,
cal,lsing the pip to gointo a fio,at state" pFET 2 is a very
weak pull-up which is on. wheneve~ the 'nFET is off, in
tradiiional CMOS style. !t's ~nlyabout 1110 the stren~th
of pFET3. Its function is to restore a' I to the pin in the
~vel,lt the pin had a I ,and lost i~ to a glitch.

Mcs·~1ARCHrrECTURE

7.4.3 Port loading and Interfacing
The output buffers of Ports I, 2, and 3 can each drive 4
LS 1TL inputs. These ports on HMOS versiOlls can be
driven in a nonnal manner by any 1TL or NMOS circuit.
Both HMOS and CHMOS pins can be driven by opencollector and open-drain outputs, but note that O-to-I transitions will not be fast. In the HMOS device, if the pin
is driven by an open collector output, a O-to-I transition
will have to be driven by the relatively weak depletion
mode F£T in Figure 7-6(A). In the CHMOS device, an
input 0 turns off pull-up pFET3, leaving only the very
weak pull-up pFET2 to drive the transition.

. turned on. If the CPU then reads the same port bit at the ,
pin rather than the latch, it will read the base -voltage of
the transistor and interpret it as a O. Reading th~ latch
rather than the pin will return the correct value of 1.

7.5 ACCESSING EXTERNAL MEMORY
Accesses to external memory are of two types: accesses
to external Program Memory and accesses to external Data
Me~Accesses to external Program Memory use signal PSEN (program store enable) as the read strobe. Accesses to external Data Memory U$e RD or WR (alternate
functions of PJ. 7 and P3.6) to strobe the memory.

Port 0 output buffers can each drive 8 LS 1TL inputs.

They do, however, require external pull-ups to drive
NMOS inputs, except when being used as the ADDRESSI
DATA bus.

Fetches from external Program Memory always use a 16bit address. Accesses to external Data Memory can use
either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri).

7.4.4 Read-Modlfy-Wrlte Feature

Whenever a 16-bit address is used, the high byte of the
address comes out on Port 2, where it is held for the
duration o{ the read or write cycle. Note that the Port 2
drivers use the strong puUups during the entire time that
they are emitting address bits that are 1s. This is during
the execution of a MOVX @DPTR instruction. During
this time the Port 2 latch (the Special Function Register)
does not have to contain Is, and the contents of the Port
2 SFR are not modified. If the external memory cycle is
not immediarely followed by another external memory
cycle, the undisturbed contents of the Port 2 SFR will
reappear in the next cycle.

Some instructions that read a port read the latch and others
read the pin. Which ones do which? The instructiolls that
read the latch rather than the pin are the ones that read
a value, possibly change it, and then rewrite it to the latch.
These are called "rea!1-modify-write" instructions. The
mstructions listed below are read-modify-write instructions. When the destination operand is a port, or a port
bit, these instructions read the latch rather than the pin:

ANL
ORL
XRL

(logical AND. e.g., ANL P1,A)
(logical OR, e.g., ORL P2,A)
(logical EX-oR, •.g., XRL
P3,A)
JBC
Oump If bit
1 and clear bit,
e.g., JBC P1.1, LABEL) .
CPL
(complement bit, •• g., CPL
P3.0)
INC ,.
(Increment, •.g., INC P2)
DEC
(decrement, •.g., DEC P2)
DJNZ
(decrement and Jump If not
zero, e.g., DJNZ P3, LABEL)
MOV PX.Y,C(move carry bit to bit Y of
Port X)
CLR PX.Y (clear bit Y of Port X)
SET PX. Y (set bit Y of Port X)

If an 8-bit address is ~ing used (MOVX @Ri), the contents of the Port 2 SFR remairt at the Port 2 pins throughout
the external memory cycle. This will facilitate paging.

In any case, the low byte of the address is time-multiplexed
with the data byte on Port O. The ADDRIDATA signal
drives both FETs in the Port 0 output buffers. Thus, in
this application the Port 0 pins are not open-drain outputs,
and do not require external pull-ups. Signal ALE (address
latch enable) should be used to capture the address byte
into an externaflatch. The address byte is valid at the
negative transition of ALE. Then, in write cycle, the
data byte to be written appears on Port 0 just before WR
is activated, and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at
Port 0 just before the read strobe is deactivated.

During any access to external memory, the CPU writeS
OFFH to the. Port 0 latch (the Special Function Register),
thus obliterating whatever information the Port 0 SFR may
have been holding.

It is not obvious that the last three instructions in this list
are read-modify-write instructions, but they are. They read
the port byte, all 8 bits, modify the addressed bit, then
write the new byte back to the latch.

External Program Memory is accessed under two conditions;

The reason that read-modify-write instructions are directed

1) Whenever signal EA is active; or
2) Whenever the program counter (PC) contains a number
that is larger than OFFFH (lFFFH for the 8052),

to the· latch rather than the pin is to avoid a· possible
misinterpretation of the 'voltage level at the pin. For example, a port bit might be .used to drive the base of a
transistor. When a 1 is written to the bit, the transistor is

This requires that the ROMless versions have EA wired

7-8

MCS(ftl·51 ARCHITECTURE

low to enable the lower 4K (8K for the 8032) program
bytes to be fetched from external memory.

oscillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN, takes 6
oscillator periods. The execution sequence for these two
types of read cycles are shown in Figure 7 -7 for
comparison.

When the CPU is executing out of external Program Memory, all 8 bits of Port 2 are dedicated to an output function
and may not be used for general purpose 110. During
external program fetches they output the high byte of the
PC. During this time the Port 2 drivers use the strong
pullups to emit PC bits that are Is.

7.5.2 ALE
The main function of ALE is to provide a properly timed
signal to latch the low byte of an address from PO to an
external latch during fetches from external Program Memory. For that purpose ALE is activated twice every machine cycle. This activation takes place even when the
cycle involves no external fetch. The only time an .ALE
pulse doesn't come out is during ari access to external
Data Memory. The first ALE of the second cycle of a
MOVX instruction is missing (see Figure 7-7). Consequently, in any· system that does not use external Data
Memory, ALE is activated at a constant rate of 116 the
oscillalor frequency, and can be used for external clocking
or timing purposes.

7.5.1 PSEN
The read strobe for external fetches is PSEN. PSEN is
not activated for internal fetches. When the CPU is accessing external Program Memory, PSEN is activated
twice every cycle (except during a MOVX instruction)
whether or not the byte fetched is actually needed for the
current instruction. When PSEN is activated its timing is
not the same as RD. A complete RD cycle, including
activation and deactivation of ALE and RD, takes 12

ALE

PSEN

AD --------r------------------------+------------~----------,_----

(A)
WITHOUT A
MOVX.

PO
I

I
I

tPCLOUT
VALID

TI
Sl

ALE

PSEN

(8)

RD -------+----------~--__,

WITH A
MOVX.

PO -

PCL OUT
VALID

Figure 7-7. External Program Memory Execution

7-9

MCS®·51 ARCHITECTURE

7.5.3 Overlapping External Program and
Data Memory Spaces
In some applications it is desirable to execute a program
from the same physical memory that is being used to store
data. In the 8051, the external Program and Data Memory
spaces can be combined by ANDingPSEN and RD. A
positive-logic AND of these two signals produces an active-low read strobe that can be used for the combined
E!!xsical memory. Since the PSEN cycle is faster than the
RD cycle, the external memory needs to be fast enough
to accommodate the PSEN cycle.

7.6 TIMER/COUNTERS
The 8051 has two 16-bit timer!counter registers: Timer
o and Timer 1. The 8052 has these two plus one more:
Timer 2. All three can be configured to operate either as
timers or event counters.
In the "timer" function, the register is incremented every
I11achine cycle. Thus, one can think of it as counting
machine cycles. Since a machine cycle consists of 12
oscillator periods, the count rate is 1112 of the oscillator
frequency.
In the "counter" function, the register is incremented in
response to a I-to-O transition at its corresponding external
input pin, TO, TI or (in the 8052) T2. In this function,
the external input is sampled during S5P2 of every machine cycle. When the samples ~how a high in one cycle
and a low in the next cycle, the count is incremented. The
new count value appears in the register during S3Pl of
the cycle following the one in which the transition was
detected. Since it takes 2 machine cycles (24 oscillator
periods) to recognize a I-to-O transition, the maximum
count rate is 1124 of the oscillator frequency. There are

no restrictions on the duty cycle of the external input
'signal, but to ensure that a given level is sampled at least
once before it changes, it should be held for at least one
full machine cycle.
In addition to the "timer" or "counter" selection, Timer
o and Timer I have four operating modes from which to
select. Timer 2, in the 8052, has three modes of operation:
"capture," "auto-reload" and "baud rate generator."

7.6.1 Timer 0 and Timer 1
These timer!counters are present in both the 8051 and the
8052. The "timer" or "counter" function is selected by
control bits CiT in the Special Function Register TMOD
(Figure 6-8). These two timer!counters have four operating
modes, which are selected by bit-pairs (Ml, MO) in
TMOD. Modes 0, 1, and 2 are the same for both timer!
counters. Mode 3 is different. The four operating modes
are described below.

MODE 0
Putting either Timer into mode 0 makes it look like an
8048 Timer, which is an 8-bit counter with a divide-by32 prescaler. Figure 7-9 shows the mode 0 operation as
it applies to Timer 1.
In this mode, the timer register is configured as a 13-bit
register. As the count rolls over from all Is to all Os, it
sets the timer interrupt flag TFI. The counted input is
enabled to the Timer when TRI = 1 and either GATE
= 0 orlNTl= 1. (Setting GATE = 1 allows the Timer
to be controlled by external input INTI, to facilitate pulse
width measurements.) TRI is a control bit in the Special
Function Register TeON (Figure 7-10). GATE is in
TMOD.

(MSB)

(LSB)

~'________~~
_________J~'________~~_________~/

TIMER 1
GATE

CIT

TIMER 0

Gating control When set....I!.!:!!!!Icounter
"x" is enabled only while "INTx" pin is
high and "TRx" control pin is sel When
cleared Tlmer"x" Is enabled
whenever "TRx" control bit is set
Timer or Counter Selector Cleared for
Timer operation (input from internal
system clock). Set for Counter operation (input from "Tx" input pin).

o
o

Operating Mode
MC5-48 Timer "TLx"' serves a8 live-bit
prescsler.
16 bit Timer/Counter "THx" and
"TLx"are cascaded; there is no presealer
a-bit auto-reload timer-counter "THx"
holds a value,which is to be reloaded
into "TLx" each time it overflows.
(Timer 0) TLO is an eight-bit timer
counter-c,ontrolled by the
standard Timer 0 control bits
THO is an eight-bit timer
only controlled by Timer 1
control bit•.
(Timer 1) Timer-counter 1 stopped.

Figure 7·8. TMOD:

TlmerfCo~nter

7-10

Mode Control Register

MCS(8)·51 ARCHITECTURE

The 13-bit register consists of all 8 bits of TH 1 and the
lower 5 bits of TLi. The upper 3 bits of TLi are indetenninate and should be ingored. Setting the run flag (TR 1)
does not clear the registers.

MODE 2
Mode 2 configures the timer register.as an 8-bit counter
(TL 1) with automatic reload, as shown in Figure 7-11.
Overflow from TLI not only sets TFI, but also reloads
TL 1 with the contents of TH I, which is preset by software.
The reload leaves THI unchanged.

Mode 0 operation is the same for Timer 0 as for Timer
1. Substitute TRO, TFO and INTO for the corresponding
Timer 1 signals in Figure 7-9. There are two different
GATE bits, one for Timer 1 (TMOD.7) and one for Timer
o (TMOD.3).

Mode 2 operation is the same for Timer/Counter O.

MODE 1

MODE 3

Mode 1 is the same as Mode 0, except that the Timer
register is being run with all 16 bits.

Timer 1 in Mode 3 simply holds its count. The effect is
the same as, setting TRI = O.

clf = 0
INTERRUPT

Tl PIN

______-'1 cif = 1

CONTROL

TR1------f

GATE

Figure 7-9. Timer/Counter 1 Mode 0: 13-bit Counter

(MSB)

TFl

TRl

TFO

TRO

Symbol

Posilion

TFl

TCON.7 'Timer 1 overflow Flag. Sel by hardware
on tlmerlcounter overflow. Cleared
by hardware _
processor
vector. to Interrupt routlns.
TCON.6 Timer 1 Run conlrol bit. Set/cleared
by software to tum timericounter
on/olt.
TCON.5 Timer 0 overflow, Flag. Set by hardware
on Umer/counter overflow. Cleared
by hardware when processor
vectore to Interrupt routlns.
TCON.4 Timer 0 Run conlrol bit. Set/cleared by
software to lurn timer/counter on/off.

TRl

TFO

TRO

Name and Slgnlllcance

IEl

ITl

lEO

(LSB)

ITO

Symbol

Posllion

Name and Slgnllicance

IEl

tCON.3

ITl

TCON.2

lEO

TCON.l

ItO

TCON.O

Interrupt 1 Edge lIag. Set by hardware
when extemallnlerrupt edge detecled.
Cleared when Interrupt processed.
Inler~pt 1 Type conlrol bit. Set/cleared
by soltware 10 specify lalling edgeflow
level triggered externallnterrupta.
Interrupt 0 Edge lIag. Set by hardware
when external interrupt edge detected.
Cleared when Interrupt processed.
Interrupt 0 Type control bit. Set/cleared
by soltware to specify lalling edgeflow level
Irlggered external interrupts.

Figure 7-10. TCON: Timer/Counter Control Register

7-11

MCS~·51

ARCHITECTURE

turned on and off by switching it out of and into its own
Mode 3, or can still be used by the serial port as a baud
rate generator, or in fact, in any application not requiring
an interrupt.

Timer 0 in Mode 3 establishes TLO and THO as two separate counters. The logic for Mode 3 on Timer 0 is shown
in Figure 7-12. TLO uses the Timer 0 control bits: cif,
GATE, TRO, INTO, and TFO. THO is locked into a timer
function (counting machine cycles) and takes over the use
of TRI and TFI from Timer I. Thus, T.HO now controls
the "Timer I" interrupt.

7.6.2 Timer 2
Timer 2 is a 16-bit timer/counter which is present only in
the 8052. Like Timers 0 and I, it can operate either as a
timer or as an event counter. This is selected by bit
ClT2 in the Special Function Register T2CON (Figure
7-13). It has three operating modes: "capture;" "auto-

Mode 3 is provided for applications requiring an extra 8bit timer or counter. With Timer 0 in Mode 3, an 8051
can look like it has three timer/counters, and an 8052, lik~
it has four. When Timer 0 is in Mode 3, Timer I can be

ciT =0

T1 PIN

______.J

INTERRUPT

CiT = 1

TFI1------I

GATE
INTO PIN

Figure 7-11. Timer/Counter 1 Mode 2: 8·bit Auto·reload

osc

~B-

1/1210SC

1/12 IOSC - - - - - - - - ,

1 - - - INTERRUPT
TO PIN - - - - - - - - '
CONTROL

TRO------I

GATE

1/1210SC----~-------I........ l
TR1

.. I

THO
(8 bl,-)

L.
r--

TF1
.._ _....

_ ____________~CONTROL
-

Figure 7·12. Timer/Counter 0 Mode 3: Two 8·bit Counters

7-12

INTERRUPT

MCSIRl-51 ARCHITECTURE

(MSB)

(LSB)

TF2

EXF2

Symbol

' Pooltton

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

Name and Significance

TF2

T2CON.7

Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be aat when either RCLK = 1 or TCLK = 1.

EXF2

T2CON.6

Timer 2 external flag let when either a capture or reload Is caused by a negative
tranlltlon on T2 EX and EXEN2 = 1. When Timer 2 Interrupt Is enabled, EXF2 = 1
will cause the CPU to vector to the Timer 2 Interrupt routine. EXF2 mUlt be
cleared by IOltware.

RCLK

T2CON.S

Receive clock Ilag. When .et, causes the lerial port to use Timer 2 overflow
pull.llor It. receive clock In model 1 and 3. RCLK =0 causes Timer 1 overflow
to be used lor the receive clock.

TCLK

T2CON.4

Transmit clock flag. When aat, cause. the ,erial port to use Timer 2 overflow
pulses lor Its transmit clock In modes 1 and 3. TCLK = 0 causes Time, 1 overflows to be used lor the t,anlmlt clock.

EXEN2

T2CON.3

Timer 2 external enable Ilag. When ,et, aliowl a capture or reload to occur a, e
result ola negative transition on T2EX II Timer 21s not being usad to clock the
sarlal port. EXEN2 = 0 caus.. Timer 2 to Ignore events at T2EX.

TR2

T2CON.2

Start/stop control lor Timer 2. A logic 1 starts the timer.

cif2

T2CON.1

Timer or counter select. (Timer 2)
0= Intemal timer (OSC/12)
1 = External event counter (Ialling edge triggered).

CP/m

T2CON.O

Capture/Reload Ilag. When set, captures will occur on negative transitions at
T2EX if EXEN2 =1. When cleared, auto reloads will occur either with Timer 2
overflows or negative tranllllons at T2EX when EXEN2 =1. When either RCLK
= 1 or TCLK = 1, this bit is Ignored and the timer Is lorced to auto-reload on
Timer 2 overflow.

Figure 7-13. T2CON: Timer/Counter 2 Control Register

In the auto-reload mode there are again two options, which
are selected by bit EXEN2 in T2CON. If EXEN2 = 0,
then when Timer 2 rolls over it not only sets TF2 but also
causes the Timer 2 registers to be reloaded with the 16bit value in registers RCAP2L and RCAP2H, Which are
preset by software. If EXEN2 = 1, then Timer 2 still
does the above, but with the added feature that a I-to-O
transition at external i1iput T2EX will also trigger the 16bit reload and set EXF2.

load" and "baud rate generator," which are selected by
,bits in T2CON as shown in Table 2.

Table 2. Timer 2 Operating Modes
RCLK+TCLK
0
0
1
X

cpiiK2
0
1
X
X

TR2
I
1
1
0

MODe
16-bit auto-reload
16-bit capture
baud rate generator
(oft)

The auto-reload mode is illustrated in Figure 7-15.
The baud rate generator mode is selected by RCLK = 1
andlor TCLK = 1. It will be described in conjunction
With the serial port.

In the captllre mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then
Timer 2 is a 16-bit timer or counter which upon overflowing sets bit TF2, the Timer 2 overflow bit, which can
be used to generate an interrupt. If EXEN2 = I, then
Timer 2 still does the above, but with the added feature
that a I-to-O transition at external input T2EX causes the
current value in the Timer 2 registers, TL2 and TH2, to
be captured into registers RCAP2L and RCAP2H,respectively. (RCAP2L and RCAP2H are new Special Function Registers in the 8052.) In addition, the transition at
T2EX causes bit EXF2 in T2CON to be set, and EXF2,
like TF2, can generate an interrupt.

7.7 SERIAL INTERFACE
The serial port is full duplex, meaning it can transmit and
receive simUltaneously. It is also receive-buffered, meaning it can commence teception of a second byte before
a previously received byte has been read from the receive
register. (However, if the first byte still hasn't been read
by the time reception of the second byte is complete, one
of the bytes will be lost). The serial port receive and
transmit registers are both accessed at Special Function
Register SBUF. Writing to SBUF lo~ds the transmit reg-

The capture mode is illustrated in Figure 7-14.

7-13

MCS®-5t ARCHITECTURE

TIMER 2
INTERRUPT

EXEN2

Figure 7-14. Timer 2 In Capture Mode

7.7.1 Multiprocessor Communications

ister, and reading SBUF accesses a physically separate
receive register."
,

Modes 2 and 3 have a special provision for multiprocessor
communications. In these modes, 9,data bits are received.
The 9th one goes into RB8. Then comes a stop bit. The
port can be programmed such that when the stop bit is
received, the serial port interrupt will be activated only
If RB8 = 1. This feature is enabled by setting bit SM2
in SeON. A way to use this feature in multiprocessor
systems is as follows.

The serial port can operate in 4 modes:
Mode 0: Serial data enters and exits through RXD. TXD
outputs the shift clock. 8 bits are transmitted/received: 8
data bits (LSB first). The baud rate is fixed at 1112 the
oscillator frequency.
Mode 1: 10 bits aretransn1itted (through TXD) or received
(through RXD): a start bit (0), 8 data bits (LSB first), and
a stop bit (1). On receive, the stop pit goes into RB8 in
Special Function Register SCON. The baud rate is
variable.

When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an address
byte which identifies t1"\e target slave. An address byte
differs from a data byte in that the 9th bit is I in an address
byte and 0 in a data byte.' With SM2 = 1, no slave will
be interrupted by a data byte. An address byte, however,
will interrupt all slaves, so that each slave can examine.
the received byte and see, if it is being addressed. The'
addressed. slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that
weren't being addressed ,leave their SM2s set and go on
about their business, ignoring the coming data bytes. '

are

tr~nsmitted (tIirough TXD) or received
Mode 2: 11 bits
(through RXD): a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (I). On transmit,
the 9th data bit CI:B8 in SeON) can be assigned the value
of 0 or i. Or, for example, the parity bit (P, in the PSW)
could be moved into TB8. On receive, the 9th data bit
goes into RB8 in Special Function Register secm, while
ihe stop bit is ignored. The baud rate is prograriunable to
either 1132 or 1164 the oscillator frequency.

SM2 has no,effect in Mode 0, and in Mode I can be used
to check the validity of the stop bit. In a Mode I reception,
if.SM2=' 1, the receive interrupt will not be activated
unless a valid stop b,it, is .received ..

Mode 3: 11 bits are transmitted (tfirough TXD) d~ ~eceived
(through RXD): a start bit (0), 8 data bits (LSB first), a
programmable 9th'data bit and a stop bit (1). In fact,
Mode 3 is the same as MOde 2 In all 'respects except the
baud rate. The baud rate in Mode 3 is variable:

7.7.2 Serial Port Control Register'
The'serial.port' control 'and istatus register is, the Special
Function Register SeON,. shown in Figure 7-16. This
register contains not only the mode selectiop bits, but also
the 9th data bit for transmit and receive (TB8 and RB8),
and the serial port interrupt ijitsf'fl and· RIJ .

In 'all four modes; 'transmission is'initiated by' any instruction that .uses SBUF as a destination register. Reception
is initiated in Mode 0 by the condition RI = 0 and REN ~ 'I.
Reception is initiated in the other modes by the incoming
start bit if REN = L '
.

.7-14

MCS®-51 ARCHITECTURE

T2 PIN

_ _ _ _....Jt

em =1

TIMER 2
INTERRUPT
T2EX PIN

EXEN2

Figure 7..15. Timer 2 in Auto-Reload Mode

(MSB)

I
~

SMO

(LSB)
SMI

SM2

REN

TB8

where SMO, SMI specify the serial port mode, as follows:
SMO

0
0
1

Descripllon

Baud Rate

0
1
2

shift register
8·bilUART
9-bitUART

losc.l12
variable
losc./64
or
fosc./32

9-blt UART variable

SMI Mode

0
1
0

• 5M2 enables the mulliprocessor communication feature in modes 2 and
3. In mode 2 or 3, if SM2 is set to 1
then RI will not be activated if the
received 9th data bit (RB8) Is O. In
mode 1, if SM2 = 1 then RI will
not be aCllvated if a valid stop bit
was not received. In mode 0, 5M2
shouldbeO.

oREN enables serial reception. Set by
software to enable reception. Clear
by software to disable reception.

RB8

- TB8

is the 9th data bit that will be
transmitted in modes 2 and 3. Set
or clear by sottware as desired.

o RB8

in modes 2 and 3, is the 9th data bit
that was received. In mode 1, If
SM2 = 0, RB8 is the stop bit that
was received. In mode 0, RB8 is
not used.

o TI

Is transmit interrupt flag. Set by
hardware at the end of the 8th bit
time in mode 0, or at the beginning
of the stop bit In the other modes,
in any serial transmission. Must.be
cleared by soltware.

o RI

is receive interrupt flag. Set by
hardware at the end of the 8th bit
time In mode 0, or haltway through
the stop bit time In the other
modes, in any serial reception (ex~
cept see SM2). Must be cleared
by sottware.

Figure 7-16. SCON: Serial Port Control Register

7.7.3 Baud Rates

The baud rate in Mode 2 depends on the value of bit
SMOD in Special Function Register PCON. If SMOD
= 0 (which is its value on reset), the baud rate is 1164
the oscillator frequency. If SMOD = 1, the baud rate is
1132 the oscillator frequency.

The baud rate in Mode 0 is fixed:
Mode 0 Baud Rate

Oscillator Frequency
12

Mode 2 Baud Rate =

7-15

2SMOD
~

x (Oscillator Frequency)

MCS®·51 ARCHITECTURE

In the 8051, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate. In the 8052, these
baud rates can be determined by Timer I, or by Timer 2,
or by both (one for transmit and the other for receive).

= oooIB), and using the Timer 1 interrupt to do a 16-bit
software reload.

Figure 7-17 lists various .commonly used bauq rates and
how they can be obtained from Timer I.

Using Timer 1 to Generate Baud Rates
When Timer 1 is used as the baud rate generator, the baud
rates in Modes 1 and 3 ~e determined by the Timer 1
overflow rate and the value of SMOD as follows:

BAUD RATE

fosc

SMOD

CIT

MODE 0 MAX: lMHZ
MODE 2 M'AX: 375K
MODES 1,3: 62.5K

12MHZ
12MHZ
12MHZ
11.059 MHZ
11.059 MHZ
11.059 Mtfz
11.059 MHZ
11.059 MHZ
11.986 MHZ
6MHZ
12MHZ

X
1
1
1
0
0
0
0
0
0
0

X
X
0
0
0
0
0
0
0
0
0

19.2K

9.6K
4.8K
2.4K
1.2K
137.5
110
110

Modes I, 3 2SMOD
Baud Rate = 32 x (Timer 1 Overflow Rate)
The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either
"timer" or "counterHoperation, and in any of its 3 running modes. In the most typical applications, it is configured for "timer" operation, in the auto-reload mode
(high nibble ofTMOD = ooIOB). In that case, the baud
rate is given by the formula
2SMOD

Modes I, 3 Baud Rate =

32 x

TIMER 1
MODE

Ri~~~D

X
X
2
2
2
2
2
2
2
2
1

X
X
FFH
FDH
FDH
FAH
F4H
E8H
lDH
72H
FEEBH

Figure 7-17. Timer 1 Generated Commonly
Used Baud Rates

Using Timer 2 to Generate Baud Rates

Oscillator Frequency
12x[256-(THI)]

In the 8052, Timer 2 is selected as the baud rate generator
by setting TCLK and/or RCLK in T2CON (Figure 7-13).
Note then the baud rates for transmit and receive can be
simultaneously different. Setting RCLK and/or TCLK
puts Timer 2 into its baud rate generator mode, as shown
in Figure 7-18.
'

One can achieve very low baud rates with Timer 1 by
leaving the Timer 1 interrupt enabled, and configuring the
Timer to run as a 16-bit timer (high nibble of TMOD

TIM-ER 1
OVERFLOW

NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12.

RX CLOCK

TX CLOCK

"TIMER 2"
INTERRUPT

T2EX PIN

EXEN2

NOTE AVAILABILITY OF ADDITIONAL EXTERNAL INTERRUPT

Figure 7-18. Timer 2 In Baud Rate Generator Mode
,

7-16

MCS~·51

ARCHITECTURE'

The baud rate generator mode is similar to the auto-reload
mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers
RCAP2H and RCAP2L, which are preset by software.

Transmission is initiated by any instruction that uses SBUF
as a destination register. The "write to SBVF" signal at
S6P2 also loads a I into the 9th bit position of the transmit
shift register and tells the TX Control block to commence
a transmission. The internal timing is such that one full
machine cycle will elapse between "write to SBVF," and
activation of SEND.

Now, the baud rates in Modes I and 3 are determined by
Timer 2's overflow rate as follows:

SEND enables the output of the shift register to the alttlrnate output function line of P3.0, and also enables
SHIFT CLOCK to the alternate output function line of
P3.1. SHIFT CLOCK is low during S3, S4, and S5 of
every machine cycle, and high during S6, SI and S2. At
S6P2 of e~ery machine cycle in which SEND is active,
the contents of the transmit shift register are shifted to the
right one position.

. Timer 2 Overflow Rate
Modes I, 3 Baud Rate =
16
,The Timer can be configured for either "timer" or·
"counter" operation. In the most typical applications, it
is configured for "timer" operation (C/T2 = 0). "Timer"
operation is a little different for Timer 2 when it's being
used as a baud rate generator. Normally asa timer it would
increment every machine cycle (thUS at 1112 the oscillator
frequency). As a baud rate generator, however, it increments every state time (thUS at 112 the· oscillator frequency). In that case the baud rate is given by the formula
Modes I, 3
Oscillator Frequency
Baud Rate = - - - - - - - - - ' - - - " - - - 32x[65536 - (RCAP2H, RCAP2L)J

As data bits shift out to the right, zeros come in from the
left. When the MSB of the data byte is at the output
. position of the shift register, then the I that was initially
loaded into the 9th position, is just to the left of the MSB,
and all positions to the left of that contain zeros. This
condition flags the TX Control block to do one last shift
and then deactivate SEND and set Tl. Both of these actions occur at SIPI ofthe 10th machine cycle after "write
to SBVE"

where (RCAP2H, RCAP2L) is the content of RCAP2H
and RCAP2L taken as a 16-bit unsigned integer.
Timer 2 as a baud rate generator is shown in Figure 7-18.
This Figure is valid only if RCLK + TCLK = I in
T2tON. Note that a rollover in TH2 does not set TEi,
and will not generate an interrupt. Therefore, the Timer
2 interrupt does not have to be disabled when Timer 2 is
in the baud rate generator mode. Note too, that if EXEN2
is set', a I-to-O transition in T2EX will set EXF2 but will
not cause a reload from (RCAP2H, RCAP2L) to (TH2,
TL2). Thus when Timer 2 is in use as a' baud rate generator, T2EX can be used as an extra external interrupt,
if desired.
It should be noted that when Timer 2 is running (TR2 =
I) in "timer" function in the baud rate generator mode,
one should not try to read or write TH2 or TL2. Under
these conditions the Timer is being incremented every
state time, and the results of a read or write may not be
accurate. The RCAP registers may be read, but shouldn't
be written to, because a write might overlap a reload and
cause write and/or reload errors, Tum the Timer off (clear
TR2) before accessing the Timer 2 or RCAP registers, in
this case.

7.7.4 More About Mode 0
Serial data enters and exits through RXD. TXD outputs
the shift clock, 8 bits are transmitted/received: 8 data bits
(LSB first). The baud rate is fixed at 1112 the oscillator
frequency.
Figure 7-19 shows a simplified functional diagram of the
serial port in mode 0, and associated timing.

Reception is initiated by the condition REN = I and RI
= O. At S6P2 of the next machine cycle, the RX Control
unit write.s. the bits 11111110 to the receive shift register,
and in the next clock phase activates RECEIVE,
RECEIVE enables SHIFT CLOCK to the alternate output
function line of P3.I. SHIFT CLOCK makes transitions
at'S3PI and S6PI of every machine cycle. At S6P2 of
every machine cycle in which RECEIVE is active, the
contents of the receive shift register are shifted to the left
one position. The value that comes in from the right is
the value that was sampled at the P3.0 pin at S5P2 of the
same machine cycle.
As data bits come in from the right, Is shift out to the
left. When the 0 that was initially loaded into the rightmost
position arrives at the leftmost position in the shift register,
it flags the RX Control block to do one last shift and load
SBVE At SIPI of the 10th machine cycle after the write
to SCaN that cleared RI, RECEIVE is cleared and RI is
set.

7.7.5 More About Mode 1
Ten bits are transmitted (through TXD) , or received
(through RXD): a start bit (0), 8 data bits (LSB first), and
a stop bit (I). On receive, the stop bit goes into RB8 in
SCaN. In the 8051 the baud rate is determined by the
Timer I overflow rate. In the 8052 it is determined either
by the Timer I overflow rate, or the Timer 2 overflow
tate, or both (one for transmit and the other for receive).
Figure 7-20 shows a simplified functional diagram of the
serial port in Mode I, and associated timings for transmit
and receive.

7-17

MCSIBl-51 ARCHITECTURE

WRITE
TO --.---wI'----'
SBUF
r---~~----~-------{~

RXD
P3.0ALT
OUTPUT
FUNCTION

S6-...._---..
SERIAL
PORT
INTERRUPT

TXD
P31 ALT
OUTPUT
FUNCTION

' - - - - _.. RXCLOCK

RX CONTROL
REN

SHIFT

........_ _.. START

Ai - - I

.oJ

L----+-i--i-.;--T-ir-i...,..-J
r-.l-l....l...t...I....l-,.--.:~

____

F;!XO
P3.0 ALT
INPUT
FUNCTION

READ
SBUF

51521>3'>4

<;5561

;,!

52Sj 54

~~'j61 51 ~2 SJS4 S', s61 0.1 ~2 51S4 S~<;b

51 52

Sl~" ""'>61 51 ~2 Sl S~ 5'>561 51 ~2S1 54 S~S615'

ALE
~OSBUF

SENOi:S6P2

SHIFT
TRANSMIT

RXD (DATA OUT) \
TXD(SHIFTCLOCK) t
l
T~I~_______
S3_P_1_S_6_~____________________________________________~,-----

--11 WRITE TO SCON (CLEAR RI)

L-R:~~~====Jr====================================================~'----

I!ECEIV.E
SHIFT

RXD(DATAIN).--~~~-~~--~~--n~--~~--n~--~~-~~----

TXD (SHIFT CLOCK)

Figure 7-19. Serial Port Mode 0

7-18

RECEIVE

MCS®·51. ARCHITECTURE

TIMER 1
OVERFLOW

TIMER2
OVERFLOW

WRITE

--~r---===J~~~~--~~:-----~---f--'- ~~'

SBUF
TO

. TCLK-

TXD

TXCONTROL
TXCLOCK

SEND

LOAD
SBUF
SHIFT

1--------.

RXD

TRANSMIT

~16RESET

______________________

________________________________

Figure 7-20. Serial Port Mode 1
TCLK,RCLK, and Timer 2 are present In the 805218032 only.

7·19

(

STOP BIT

~r----

IIIICS®·51 ARCHITECTUflE

'are met or not, the unit goes 'back to looking for a I-tdo transition in RXD.

Transmission is initiated by any instrUction that uses SBUF
as a destination register. The "write to SBUF" signal also
loads a I into the 9th bit position of the transmit shift
register and flags the TX Control unit that a transmission
is requested. Transmission actually commences at SIPI
of the machine cycle following the next rollover in the
divide-by-16 counter. (Thus, the bit times aresynchronized to the divide-by-16 c01,lnter, not to the "write to
SBUF" signal).

7.7.6 More About Modes 2 and 3
Eleven bits are transmitted (through TXD), or. received
(through RXD): a start bit (0), S data bits (LSB ,first), a
programmable 9th data bit, and a stop bit (1). On transmit,
the 9th data bit (TBS) can be assigned the value of 0 or
1. On receive, the 9th data bit goes into RBS in SCON.
The baud rate is programmable to either 1132 or 1164 the
oscillator frequency in mode 2. Mode 3 may have a var,
iable baud rate generated from either Timer I or 2 depending on the state of TCLK and RCLK.

The transmission begins with activation of SEND, which
puts the start bit at TXD. One bit time later, DATA is
activated, which enables the output bit of the transmit
shift register to TXD. The first shift pulse occurs one bit
time after that.
As data bits shift out to the right, zeros are clocked in
from the left. When the MSB of the data byte is at the
output position of the shift register, then the I that was
initially loaded into the 9th position is just to the left of
the MSB, and all positions to the left of that contain
zeroes. This condition flags the TX Control unit to do one
last shift and then deactivate SEND and set TI. This occurs
at the 10th divide-by-16 rollover after "write to SBUF."

Figures 7-21 A and B show a functional diagram of the
'serial port in modes 2 and 3. The receive portion is exactly
the Same as in mode I. The transmit portion differs from
mode I only in the 9th bit of the transmit shift register.
Transmission is initiated by any instruction that uses SBUF
as a destination register: The "write to SBUF" signal also
loads TBS into the 9th bit position of the transmit shift
register and flags the TX Control unit that a transmissiol1
is requested. Transmission commences at S IPI of the
machine cycle following the next rollover in the divideby-16 counter. (Thus, the bit times are synchronized to
the divide-by-16 counter, not to the "write to SBUF"
signal.)

Reception is initiated by a detected I-to-O'transition at
RXD. For this purpose RXD is sampled at a rate of 16
times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is immediately reset, and I FFH is written into the input shift
register. Resetting the divide-by-16 counter aligns its
rollovers with the boundaries of the incoming bit times.
The 16 states of the counter divide each bit time into
16ths. At the 7th,.Sth, and 9th counter states of each bit
time, the bit detector samples the value of RXD. The value
accepted is the value that was seen in at least 2 of the 3
samples. This is done for noise rejection. If the value '
accepted during the first bit time is not 0, the receive
circuits are reset and the unit goes back to looking for
another I-to-O transition. This is to provide rejection of
false start bits. If the start bit proves valid, it is shifted
into the input shift register, and reception of the rest of
the frame will proceed.
As data bits come in from the right, Is shift out to the
left. When the start bit arrives at the leftmost position in
the shift register, (which in mode I is a 9-bit register), it
flags the RX Control block to do one last shift, load SBUF
and RBS, and set RI. The signal to load SBUF and RBS,
and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse
is generated ..

The transmission begins with activation of SEND, which
puts the start bit at TXD. One bit time later, DATA is
activated, which enables the output bit of the transmit
shift register to TXD. The first shift pulse occurs one bit
time after that. The first shift clocks a I (the stop bit) into
the 9th bit position of the shift register. Thereafter, only
zeroes are clocked in. Thus, as data bits shift out to the
right, zeroes are clocked in from the left. When TBS is
at the output position of the shift register, then the stop
bit is just to the left of TBS, and all positions to the left
of thatcontain zeroes. This condition flags the TX Control
unit to do one last shift and then deactivate SEND and
set n. This occurs at the 11th divide-by-16rollover after
"write to SBUF."
Reception is initiated by a det~cted I-to-O transition at,
RXD. For this purpose RXD is sampled at a rate of 16
times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is immediately reset, and'IFFH is written to the input shift register.

I) RI = 0, and
2) Either SM2 = 0, or the received stop bit =' I
If either of these two conditions is not met, the received
frame is irretrievably lost. If both conditions are met, the
stop bit goes into RBS, the S data bits go into SBUF, and .
RI is activated. At this time, whether the above conditions

7-20

At the 7th, Sth and 9th counter states of each bit time, the
bit detector samples the value of RXD. The value accepted
is the value that was seen in at least 2 of the 3 samples.
If the value accepted during the first bit time is not 0, the
receive circuits are reset and the unit goes back to looking
for another I-to-O transition. If the start bit proves valid,
it is shifted into the input shift register, and reception of
the rest of the, frame will proceed.

MCS®-51 ARCHITECTURE

WRITE
TO
--~~----~~~---'

S~UF

r--......:a"---L-_J-.....
TXD

PHASE2CLOCK
(Y" fose)

MODE2
SEND
SMOD =,

SMOD=O

SERIAL
PORT
INTERRUPT

(SMOD IS PCON 7) L.._------J
LOAD
SBUF

RXD

TX
jCLOCKj

~.WRI~T~E~T~O~S~~B~U~F--JL_~L_ _JL_~l~_JL_~IL_~L----.JIL~~L___IL___

- - - 1 SEND
DATA

S1P1 I
TRANSMIT

STOP BIT GEN
CL'6XCK

RECEIVE

STOP BIT
I
-16 RESET

DO
RXD BIT DETECTORI STA.T BIT {
SAMPLE TIMES
SHIFT·
- L_ _IL_ _IL_--.JL~--.JL_--.JIL_-..-JI_ _-..-JI_ _~L_ _~_ __
________________________________________________

·~R~I

~r-----

Figure 7·21A. Serial Port Mode 2

7·21

MCS®-S1 ARCHITECTURE

TIMER1
OVERFLOW

TIMER2
OVERFLOW

WRITE

--~r---===J~~~~--~~:-----~~-{--,- ~~,

TO
SBUF

TXD

TXCONTROL

TCLK -

TXCLOCK

SEND

LOAD
SBUF
SHIFT 1--------,

RXD

TX
_~LOC~~~!~=-~L__~L__~L__~IL-__JL-__~L__~L__~L__~IL-__IL-___
_ 8 WRITE TO SBUF
- - - - - , SEND
DATA C S1P1 I
TRANSMIT
STOP BIT
STOP BIT GEN

--------,':==________________________________--'

~T
RECEIVE

RXD BIT DETECTORI START BIT ,
DO
01
SAMPLE TIMES
~ __~I____~L____JL-_ _~l____~L____IL-__-"l____~L__~IL-____
SHIFT
____________________________________________________________________

-"r-----

~R~I

Figu~e 7.21 B. Serial Port Mode 3
TCLK, RCLK, and Timer 2 are present in the 8052/8032 only.

·7-22

MCS®;;S1,'ARCHITECTURE

As ,data bits come'in from the right, 1s shift out to the
left. When the start bit arrives at the leftmost posiUon in
the shift register (which in modes 2 and 3 is a 9-bit reg, ister),' it flags the RX Control block to do one last shift,
, load SBUFand RBS', and set RI, The signal to 10ad'SBUF
and RB8, anti to set RI, wiU be generated if, imd only,if,
the following conditions are met at' the time the final shift
pulse is generated:
1) RI'= b,'and '
2) Either SM2 "±:! 0 or the received 9th d~ta bit = 1

ITO and ITI in Register TCON. The flags that actually
generate these interrUpts are bits lEO and lEI in TCON.
When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transitionactivated. If the interrupt was level-activated, then the
external requesting'source is what controls the request
flag, rather than the on-chip hardware,
The Timer 0 and Timer 1 Interrupts are generated by TFO
and TFI, which are set by a rollover in their respective
timer/counter registers (except see Section 7. 6.trfor Timer
o in mode 3): When a timer interrupt is generated, the
flag that genenited it'is cleared by the on-chip hardware
when the service routine is vectored to.

If either of these conditions is not met, the received frame
is irretrievably lost, and RI is not set, IF both conditions
are met, the received 9th data bit goes into RB8, and the
/ first 8 data bits go into SBUF, One bit time later, whether
,the above, conditions were met or not" the unit goes back
to loqking for a I-to-O transjt,ion at the RXD input.

The Serial Pon Interrupt is generated by the .logical OR
of RI and TI. Neither of,these flags is cleared by hardware
when the service routine is vectored to. In fact, the service
routine will normally have to determine whether it .was
RI or TI that generated the interrupt, and the, bit will have
to be cleared in software.

Note that the value of the received stop bit is. irrelevant
to SBUF, RB8, or IH.

7.8 INTERRUPTS
In .!he 8052, the Timer 2 Interrupt is generated by the
logical OR of TF2 and EXF2. Neither of these flags is
tle,ared ~y Iwrdware 'Yhen the serv~e routine is vectored
roo In liact, , the service ,routine may have to determine
~hether it was TF2 or EXF2 thargenerated the interrupt,
imd the ,bit will have to be cleared in software.

•The 805 I provides 5 inteITupt sources, The 8052 provides
,
'6. These are show'n in'FigUre 7-22/ ":'
.

The Exttrnal Interrupts'fNTO and INTI can each be eiti1er
level-activated or transition-activated, depending on bits

All of the bits that generat~ interrupts can be set or cleared
by softJiVare:.with the,silJne r~su~~ as though it had been
set or cleared by hardware. That is, interrupts can be
generated or pending interrupts can be canceled in
software ..

(MSB)

(LSB)

1EA I xl ml ES 1En 1EX1 1ETO 1EXO I'
SYlrbo;>1
EA

TFO-~~~~~~~~-~",

INTERRUPT
SOURCES

TF1----------.

Figure 7-22. MCS-S1

Int'~ruptSoure""',

IE.7

ET2

IE.6
IE.5

IE.4

ET1

IE'.3

EX1 '
TF2~
EXF2~

Position

, IE.2

ETO

IE.1

EXO

IE.O

Function
disables ali Interrupts. If EA = 0, no Interrupt
will be acknowledged. IlEA = 1, each Interrupt source Is Individually enabled or disabled by setting or clearing its enable bit.

reserved
enables or disables the Tln"ir 2 overflow'
or capture Interrupt. II ET2 = 0, the Timer 2
Interrupt Is dis,abled.
enables or disables the Serial Port Interrupt. lIES" 0, t~e Serial Port Interrupt Is
, disabled.
enables or disables the Timer 1 Overllow
, interrupt. II En = 0, the Tlm.r 1 Interrupt
'
is disabled.
enables or disables External Interrupt 1.
II EX1 = 0, Extetnal, Interrupt 1 Is dl,sabled.
enables or disables the Timer 0 Overflow
Interrupt. II ETO = 0, the Timer 0 Interrupt
Is disabled.
enables or disables External Interrupt O. II
EXO = 0, External Interrupt 0 I. disabled.

, Flgllre 7-23", IE: Interrupt Enable Register

7-23

MCS®-51 ARCHITECTURE

Each of these interrupt sources can be individually enabled
or disabled by slltting or clearing a bit in Special Function
Register IE (Figure 7-23). Note that IE contains also a
global disable bit, EA, which disables all interrupts at
once.

7.8.1 Priority Level Structure

If two requests of different priority levels are received
simultaneously, the request of higher priority level is serviced. Ifrequests of the same priority level are received
siplUltaneously,. an internal polling sequence determines
which request is serviced. Thus within each priority level
there is a second priority structure determined by the polling sequence, as follows:

Each interrupt source can also be individually programmed
to' one of two priority levels by setting or clearing a bit
in Special Function Register IP (Figure 7-24). A lowpriority interrupt can itself be interrupted by a high-priority
interrupt, but not by another low-priority interrupt. A
high-prillrity. interrupt can't be interrupted by any other
interrupt source.

(MSB)

2.
3.
4.
5.
6.

Position
IP.7

FuncUon
reserved

IP.6

reserved

PT2

IP.5

defines the Timer 2 Int,rrupt priority
level. PT2 =1 programs It to the higher
priority level.

IP.4

defines the Serial Port In,..rupt priority
level. PS =1 program. It to the higher
priority level.

PT1

IP.3

defines the Timer 1 Interrupt priority .
level. PT1 =1 programs It to the higher
priority level.

PX1

IP.2

defines the External Interrupt 1 priority
level. PX1 =1 programs It to the higher
priority level.

PTO

IP.1

defines the Timer 0 Interrupt priority
level. PTO =1 programs It to the higher
priority level.

PXO

IP.O

defines the External Interrupt 0 priority
level. PXO =1 programs It to the higher
priority level.

Figure 7-24. IP: Interrupt Priority Register

PRIORITY WITHIN LEVEL

lEO
TFO
IE1
TFl

(hlgheat)

AI+TI
TF2 + EXF2

(low••')

7.8.2 How Interrupts Are Handled
The interrupt flags are sampled at S5P2 of every machine
cycle. The samples are polled during the following machine cycle. If one of the flags was in a set condition at
S5P2 of 'the preceding cycle, the polling cycle will find
it and the interrupt syste~ will generate an LCALL to the
appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following
conditions:
I. An interrupt of equal or higher priori,ty level is already
in progress.
2. The current (polling) cycle is not the final cycle in the
execution of ,the instruction in progress.
3. The instruction in progress is RETI or any access to
the IE or IP registers.
Any of these three conditions will block the generation
of the LCALL to the interrupt service routine. Condition
-2 ensUf!lS that the instruction in progress will be completed

......~·---C1-_
.. -tI_.- - C 2 - -....-I.....
---C3
ISSP21

SOURCE

Note that the "priority within level" structure is only used
to resolve simultaneous requests of the same priority level.

(LSB)

I X I X I PT2lpsl PTl I pXll PTO I PXO I
Symbol

• I ..

C4--".....1 ••- - C 5 - -.. •..

........ ~'\-,--..L.-~1'\r--..L-.--....,1l'..~- - - ' - - - - -

INTERRUPT
GOES
ACTIVE

INTERRUPT
LATCHED

LONG CALL TO
INTERRUPT
VECTOR ADDRESS

INTERRUPTS
ARE POLLED

This is the last"t possible "sponse when C2 is the final cycle 01
an Instruction other than RETI or an access to IE or IP.

Figure 7-25. Interrupt Response Timing Diagram

7-24

INTERRUPT ROUTINE

MCS®-S1 ARCHITECTURE

before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any
access to IE or IP, then at least one more instruction will
be executed before any interrupt is vectored to.
The polling cycle is repeated with each machine cycle,
and the values polled are the values that were present at
S5P2 of the previous machine cycle. Note then that if an
interrupt flag is active but not being responded to for one
of the above conditions, if the flag is not still active wh,en
the blocking condition is removed, the denied interrupt
will not be serviced. In other words, the fact that the
interrupt flag was once active but not serviced is not rem~mbered. Every polling cycle is new.

7.8.3 External Interrupts
The external sources can be programmed to be levelactivated or transition-activated by setting or clearing bit
IT! or ITO in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INTx pin.
If ITx = I, external interrupt x is edge-triggered. In this
mode if successive samples of the INTx pin show a high
in one cycle and a low in the next cycle, interrupt request
flag lEx in TCON is set. Flag bit lEx then requests the
interrupt.
Since the external interrupt pins are sampled once each
machine cycle, an input high or low should hold for at
least 12 oscillatorperiods ..to ensure sampling. If the external interrupt is transition-activated, the external source
has to hold the request pin high for at least one cycle, and
then hold it low for at least one cycle to ensure that the
transition is seen so that interrupt request flag lEx will be
set. lEx will be automatically cleared by the CPU when
the service routine is called.

The polling cycle/LCALL sequence is illustrated in Figure
7-25.
Note that if an interrupt of higher priority level goes active
prior to S5P2 of the machine cycle labeled C3 in Figure
7-25, then in accordance with the above rules it will be
vectored to during C5 and C6, without any instruction of
the lower priority routine having been executed.

If the external interrupt is level-activated, the external
source has to hold the request active until the requested
interrupt is actually generated. Then it has to deactivate
the request before the interrupt service routine is completed, or else another interrupt will be generated.

Thus the processor acknowledges an interrupt request by
executing a hardware-generated LCALL to the appropriate
servicing routine. In some cases it also clears the flag that
generated the interrupt, and in other cases it doesn't. It
never clears the Serial Port or Timer 2 flags. This has to
be done in the user's software. It clears an external interrupt flag (lEO or lEI) only if it was transition-activated.
The hardware-generated LCALL pushes the contents of
the Program Counter onto the stack (but it does not save
the PSW) and reloads the PC with an address that depends
on the source of the interrupt being vectored to, as shown
below.

SOURCE

VECTOR
ADDRESS

lEO
TFO

OOOBH

IE1
TF1
RI+TI
TF2+EXF2

0013H
001BH
0023H
002BH

7.8.4 Response Time
The INTO and INTI levels are inverted and latched into
lEO and lEI at S5P2 of every machine cycle. The values
are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right
for it to be acknowledged, a hardware subroutine call to
the requested service routine will be the next instruction
to be executed. The call itself takes two cycles. Thus, a
minimum of three complete machine cycles elapse between activation of an external interrupt request and the
beginning of execution of the first instruction of the service
routine. Figure 7-25 shows interrupt response timings.

0003H

A longer response time would result if the request is
blocked by one of the 3 previously listed conditions. If
an interrupt of equal or higher priority level is already in
progress, the additional wait time obviously depends on
the nature of the other interrupt's service routine. If the
instruction in progress is not in its final cycle, the additional wait time cannot be more than 3 cycles, since the
longest instructions (MUL and DIY) are only 4 cycles
long, and if the instruction in progress is RETI or an
access to IE or IP, the additional wait time cannot be more
than 5 cycles (a maximum of one more cycle to complete
the instruction in progress, plus 4 cycles to complete the
next instruction if the instruction is MUL or DIY).

Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs
the processor that this interrupt routine is no longer in
progress, then pops the top two bytes from the stack and
reloads the Program Counter. Execution of the interrupted
program continues from where it left off.
Note that a simple RET instruction would also have returned execution to the interrupted program, but it would
have left the interrupt control system thinking an interrupt
was still in progress.

Thus, in a single-interrupt system, the response time is
always more than 3 cycles and less than 8 cycles.

7-25

MCS®-51 ARCHITECTURF1

7.9 SINGLE-STEP OPERATION
The 8051 intenupt structure allows single-step execution
,with very little software overhead. As previously noted,
an intenupt request will not be responded to while an
intenupt of equal priority level is still in progress, nor
will it be responded to after RETI until at least one other
instruction has been executed. Thus, once an intenupt
routine has been entered, it cannot be re-entered until at
least once instruction of the intenupted program is executed. One way to use this feature for single-step operation
is to program one of the external intenupts (say, INTO)
to be level-activated. The service routine for the intenupt
will terminate with the following code:

JNB

P3.2,$

RETI

;WAIT HERE TILL INTO
GOES HIGH
;NOW WAIT HERE TILL
IT GOES LOW
:GO BACK AND
EXECUTE ONE
INSTRUCTION

Now if the INTO pin, which is also the P3.2 pin, is held
normally low, the epu will go right into the External
Intenupt 0 routine and stay there until INTO is pulsed
(from low to high to low). Then it will execute RETI, go
back to the task program, execute one instruction, and
immediately re-enter the External Intenupt 0 routine to
await the next pulsing of P3.2. One step of the task program is executed each time P3. 2 is pulsed.

7.10 RESET

an internal reset. It also configures the ALE and PSEN
pins as inputs. (They are quasi-bidirectional). The internal
reset is executed during the second cycle in which RST
is high and is repeated every cycle until RST goes low.
It leaves the internal registers as follows:
REGISTER
CONTENT
PC
OOOOH
ACC
OOH
B
OOH
PSW
OOH
SP
07H
DPTR
OOOOH
PO-P3
OFFH
IP (8051)
XXXOOOOOB
IP (8052)
XXOOOOOOB
IE (8051)
OXXOOOOOB
IE (8052)
OXOOOOOOB
TMOD
OOH
TCON
OOH
T2CON (8052 only)
OOH
THO
OOH
TLO
OOH
TH1
OOH
TL1
OOH
TH2
OOH
TL2
OOH
RCAP2H (8052 only)
OOH
RCAP2L (8052 only)
OOH
SCON
OOH
SBUF
Indeterminate
PCON(HMOS)OXXXXXXXB
PCON (CHMOS)
OXXXOOOOB
The internal RAM is not affected by reset. When vee is
turned on, the RAM content is indeterminate unless the
part is returning from a reduced power mode of operation.

The reset input is the RST pin, which is the input to a
Schmitt Trigger.
A reset is accomplished by holding the RST pin high for
at least two machine cycles (24 oscillator periods), while
the oscillator is running. The epu responds by executing

POWER·ON RESET

An automatic reset can be obtained when vee is turned
on by connecting the RST pin to vee through a 10 J-tf
capacitor and to VSS through an 8. 2Kll resistor, providing the vee risetime does not exceed a millisecond and
the oscillator start-up time does not exceed 10 milliseconds. This power-on reset circuit is shown in Figure
7-26. When power comes on, the current drawn by RST
commences to charge the capacitor. The voltage at RST
is the difference between vee and the capacitor voltage,
and decreases from vee as the cap charges. :The larger
the capacitor, the more slowly VRST decreases. VRST
must remain above the lower threshhold of the Schmitt
Trigger long enough to effect a complete reset. The time
required is the oscillator start-up time, plus 2 machine
cycles.

vee

10,<1

='=
vee

8051

. RST

8.2Kn

7.11 POWER-SAVING MODES OF
OPERATION
V.SS

"'":::'"

For applications where power consumption is a critical
factor, both the HMOS and eHMOS versions provide
reduced power modes of operation. For the eHMOS ver-

Figure 7·26. Power on Reset Circuit

7-26

MCS®·51 ARCHITECTURE

sion of tbe 8051 tbe reduced power modes, Idle and Power
Down, are standard features. In the HMOS versions a
reduced power mode is available, but not as a standard
fe~ture. The local sales office will provide ordering information for users requiring this feature.

(MSB)

7.11.1 HMOS Power Down Mode
The power down mode in the HMOS devices allows one
to reduce vee to zero while saving the on-chip RAM
through a backup supply connected to the RST pin. To
use the feature, the user's system, upon detecting that a
power failure is imminent, would interrupt the processor
in some manner to. transfer relevant data to the on-chip
RAM and enable the backup power supply to the RST pin
before vee falls below its operating limit. When power
returns, the backup supply needs. to stay On long enough
to accomplish a reset, and then can be removed Sl) that
normal operation can be resumed.

I GFl

GFO

Symbol

Position

Name and Function

SMOO

PCON.7

GFl
GFO
PD

PCON.&
PCON.S
PCON.4
PCON.3
PCON.2
PCON.l

IDL

PCON.O

Double BaUd rate bit. When set to a
1, the baud rate Is doubled when
the serial port Is being used In
either modes 1, 2 or 3.
(Reserved)
(Reserved)
(Reserved)
General-purpose flag bit.
General-purpose flag bit.
Power Down bit. Setting this bit
activates power down operation.
Idle mode bit. Setting thlsliit activates Idle mode operation.

IOL

If 1s are written to PD and IDL at the same time, PD
takes precedence. The resel value 01 PCON Is
(OXXXOOOO).

Figure 7-28. PCON: Power Control Register

7.11.2 CHMOS Power Reduction Modes
CHMOS ,versions have two power-reducing modes, Idle
and Power Down. The input through which backup power
is supplied d\lring these operations is vee. F,igure 7-27'
shows the internal circuitry which implements these features. In the Idle mode (IDL = I), the oscillator continues
to run and the Interrupt, Serial Port, and Timer blocks
continue to be clocked, but the clock signal is gated off
to the. CPU. In Power Down (PD = 1), the oscillator is
frozen. Tbe Idle and Power Down modes are activated by
setting bits in Special Function Register PeQN. The address of this register is 87H. Figure 7-28 details its
contents.

(LSB)

ISMool

the Idle mode, the internal clock signal is gated off to the
CPU, but not to the Interrupt, Timer, and Serial Port
functions. The CPU status is preserved in its entirety: the
Stack Pointer, Program Counter, Program Status Word,
Accumulator, and all other registers maintain their data
during Idle. The port pins hold the logical states they had
at the time Idle was activated. ALE and PSEN hold at
. logic high levels.

IDLE MODE

There are two ways to terminate the Idle. Activation of
any enabled interrupt will cause PeON. 0 to be cleared by
hardware, terminating the Idle mode. The interrupt will
be serviced, and following RET! the next instruction to
be executed will be the one following the instruction that
put the device into Idle.

An instruction that sets PeON.O causes that to be the last
instruction executed before going into the Idle mode. In

The flag bits GFO and GFl can be used to give an indication if an interrupt occurred during normal operation or

XTAL 2

XTAL 1

INTERRUPT,

I-_--C>. SERIAL PORT,
TIMER BLOCKS

CPU

Figure 7-27. Idle and Power Down Hardware

7-27

MCS®·51 ARCHITECTURE

7.12 8751H

during an Idle. For example, an instruction that activates
Idle can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can
examine the flag bits.

The 8751H is the EPROM member of the MCS-51 family.
This means that the on-chip Program Memory can be
electrically programmed, and can be erased by exposure
to ultraviolet light. The 8751H also has a provision for
denying external access to the on-chip Program Memory ,
in order to protect its contents against software piracy.

The other way of terminating the Idle mode is with a
hardware reset. Since the clock oscillator is still running,
the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the
reset.

7.12.1 Programming the EPROM
To be programmed, the 8751H must be running with a 4
to 6 MHz oscillator. (The reason the oscillator needs to
be running is that the internal bus is being used to transfer
address and program data to appropriate internal registers.)
The address of an EPROM location to be programmed is
applied to Port 1 and pins P2.0-P2.3 of Port 2, while the
data byte is applied to Port O. Pins P2.4--P2.6 and PSEN
should be held low, and P2.7 and RST high. (These are
all TTL levels except RST, which requires 2.5V for a
logic high.) EAlVPP is held normally high, and is pulsed
to +2IV. While EAlVPP is at 21V, the ALE/PROG pin,
which is normally being held high, is pulsed low for 50
msec. Then EAlVPP is returned to high. This setup is
shown in Figure 7.29. Detailed timing specifications are
provided in the 875lH data sheet.

POWER DOWN MODE

An instruction that sets PCON.I causes that to be the last
instruction executed before going into the Power Down
mode. In the Power Down mode, the on-chip oscillator
is stopped. With the clock frozen, all functions are
stopped, but the on-chip RAM and Special Function Registers are held. The port pins output the values held by
their respective SFRs. ALE and PSEN output lows.
'The only exit from Power Down is a hardware reset. Reset
redefines all the SFRs, but does not change the on-chip
RAM.
In the Power dow\l mode of operation, VCC can be reduced to minimize power consumption. Care must be
taken, however, to ensure that VCC is not reduced before
the Power Down mode is invoked, and that vce is restored to its normal operating level, before the Power
Down mode is terminated. The reset that terminates Power
Down also frees the oscillator. The reset should not be
activated before VCC is restored to its normal operating
level, and must be held active long enough to allow the
oscillator to restart and stabilize (normally less than 10
msec).

Note: The EA pin must not be allowed to go above the
maximum specified VPP level of 21.5V for any amount
of time. Even a narrow glitch above that voltage level can
cause permanent damage to the device. The VPP source
should be well regulated and free of glitches.

7.12.2 Program Verification
If the program security bit has not been programmed, the
on-chip Program Memory can be read out for verification

+5V
ADDR.
OOOOHOFFFH

vee

Pl
8751H
P2.0P2.3

TTL HIGH

P2.4
P2.5

ALE/PROG

P2.&
P2.7
XTAL2

EAlVPP

XTALl
VSS

-=-

Figure 7-29. Programming the 8751 H

7-28

MCS®-51 ARCHITECTURE
programming, except that pin P2.6 is held at TTL high.
The setup is shown in Figure 7.31. Port 0, Port 1, and
pins P2.O""P2.3 of Port 2 may be in any state.

purposes, if desired, either during or after the programming operation. The required setup, which is shown in
Figure 7.30, is the same as for programming the EPROM
except that pin P2.7 is held at TTL low (or used as an
active-low read strobe). The address of the Program Memory location to be read is applied to Port I and pins
P2.O""P2.3. The other Port 2 pins and PSEN are held low.
ALE, EA, and RST are held high. The contents of the
addiessed location will come out on Port O. External pullups are required on Port 0 for this operation.

Once the security bit has been programmed, it can be
deactivated only by full erasure of the Program Memory.
While it is programmed, the internal Program Memory
cannot be read out, the device cannot be further programmed, and it cannot execute external program memory. Erasing the EPROM, thus deactivating the security
bit, restores the device's full functionality. It can then be
re-programmed.

7.12.3 Program Memory Security

7.12.4 Erasure Characteristics

The 8751H contains a security bit, which, once programmed, denies electrical access by any external means
to the on-chip Program Memory. The setup and procedure
for programming the security bit are the same as for normal

Erasure of the 8751H Program Memory begins to occur
when the chip is exposed to light with wavelengths shorter

+5V
ADDR. --~---,,....,.,

OOOOHOFFFH

vcc

PGM DATA
(USE 10K PULLUPS)

P2.0P2.3

8751H
8051

P2.4
P2.5

ALe

TTL HIGH

XTAL2

RST

VIH1

XTAL1

PSEN

P2.6
P2.7

VSS

.".

Figure 7-30. Program Verification In the 8751 Hand 8051

+5V

vcc

P2.oP2.3

= "DON'T ·CARE"

8751H
P2.4
P2.5

ALE/PFiOG 50 ms PULSE TO GND

P2.6
P2.7

TTL HIGH

XTAL2
XTAL1
VSS

EAlVPP + 21V PULSE
RST
PSEN

.".

VIH1

.".

Figure 7-31. Programming the Security Bit in the 8751H

7-29

MCS®·51 ARCHITECTURE

than approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about
I week in sunlight, or 3 years in room-level fluorescent ,
lighting) could cause inadvertent erasure. If an application
subjects the 8751H to this type of exposure, it is suggested
that an opaque label be placed over the window.
The recommended erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to an integrated dose of
at least 15 W/cm2 . Exposing the 8751H to an ultraviolet
lamp of 12,000 /LW/cm2 rating for 20 to 30 minutes, at
a distance of about 1 inch, should be sufficient.

Erasure leaves the array in an all Is state.

7.13 MORE ABOUT THE ON·CHIP
OSCILLATOR
7.13.1 HMOS Versions
The on-chip oscillator circuitry for the HMOS (HMOS-I
and HMOS-II) members of the MCS-51 family is a single
stage linear inverter (Figure 7-32), intended for use as a
crystal-controlled, positive reactance oscillator (Figure
7-33). In this application the crystal is operated in its
fundamental response mode as an inductive reactance in
parallel resonance with capacitance external to the crystal.

Vee

TO INTERNAL
TIMING CKTS

XTAL2
XTAL1

SUBST.

Figure 7-32. On-Chip Oscillator Circuitry in the HMOS Versions of the MCS-51 Family

Q2
TO INTERNAL
TIMING CKTS

VSS

8051

XTAL1----

XTAL2------

_--1"-- QUARTZ CRYSTAL
OR CERAMIC ReSONATOR

Figure 7-33. Using tile HMOS On-Chip OSCillator

7-30

MCS®-S1 ARCHITECTURE

ramic resonators, and the selection of values for CI and
C2 can be found in Application Note AP-155, "Oscillators
for Microcontrollers," which is included in this manual.

The crystal specifications and capacitance values (CI and
C2 in Figure 7-33) are not critical. 30 pF can be used in
these positions at any frequency with good quality crystals. A ceramic resonator can be used in place of the crystal
in cost-sensitive applications. When a ceramic resonator
is used, CI and C2 are normally selected to be of somewhat higher values, typically, 47 pF. The manufacturer
of the ceramic resonator should be consulted for recommendations on the values of these capacitors.

To drive the HMOS parts with an external clock source,
apply the external clock signal to XTAL2, and ground
XTALl, as shown in Figure 7-34. A pull-up resistor may
be used (to increase noise margin), but is optional if VOH
of the driving gate exceeds the VIHMIN specification of
XTAL2.

A more in-depth discussion of crystal specifications, ce-

7.13.2 CHMOS
The on-chip oscillator circuitry for the 80C51, shown in
Figure 7-35, consists of a single stage linear inverter intended for use as a crystal-controlled, positive reactance
oscillator in the same manner as the HMOS parts. However, there are some important differences.

Vcc

EXTERNAL
OSCILLATOR
SIGNAL

8051

.;.c>--+---i XTAL2
-

One difference is that the SOC51 is able to turn off its
oscillator under software control (by writing a I to the PD
bit in PeON). Another difference is that in the SOC5l the
internal clocking circuitry is driven by the signal at
XTALl, whereas in the HMOS versions it is by the signal
at XTAL2.

XTAL1

TTL
GATE
WITH
TOTEM-POLE
OUTPUT

>-- VSS

The feedback resistor Rf in Figure 7-35 consists of paralleled n- and p-channel FETs controlled by the PD bit,
such that Rf is opened when 'PD = I. The diodes D I and
D2, which act as clamps to VCC and VSS, are parasitic
to the Rf FETs.

Figure 7-34. Driving the HMOS MCS-51 Parts
with an External Clock Source

Vcc

TO INTERNAL
TIMING cKrs

01
R,

4000
XTAL1

XTAL2

Figure 7-35. On-Chip Oscillator Circuitry in the CHMOS Versions of the MCS-51 Family

7-31

MCS®-51 ARCHITECTURE

VCC
TO INTERNAL
TIMING CKTS

VSS
-------80C51

XTAL1-----

XTAL2------

~-r--

QUARTZ CRYSTAL
OR CERAMIC
RESONATOR

C~ I ~
FIgure 7-36. Using the CHMOS On-Chip Oscillator

The oscillator can be used with the same external components !IS the HMOS versions, as shown in Figure 7-36.
Typically, CI = C2 = ·30 pF when the feedback element
is a quartz crystal, and Cl = C2 = 47 pF when a ceramic
resonator is used.
To drive the.CHMOS parts with an external clock source,
apply the external clock signal to XTALl, and leave
XTAL2 float, as shown in Figure 7-37.
The reason for this change from the way the HMOS part
is driven can be seen by comparing Figures 7-32 and 7-35.
In the HMOS devices the internal timing circuits are driven
by the signal at XTAL2. In the CHMOS devices the internal timing circuits are driven by the signal at XTALI.

80C51
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL

:>0----1

7.14 INTERNAL TIMING
Figures 7-38 through 7-41 show when the various strobe
and port signals are clocked internally. The figures do not
show rise and fall times of the signals, nor do they show
propagation delays between the XTAL2 signal and events
at other pins.
Rise and fall times are dependent on the external loading
that each pin must drive. They are often taken to be some:
thing in the neighborhood of 10 nsec, measured between
0.8V and 2.0V.
Propagation delays are different for different pins. For a
given pin they vary with pin loading, temperature, VCC,
and manufayturing lot. If the XTAL2 waveform is taken
as the timing reference, prop delays may vary from 25 to
125 nsec.
the AC Timings section of the data sheets do not reference
any timing to the XTAL2 waveform. Rather, they relate
the critical edges of control and input signals to each other.
The timings published in the data sheets include the effects
of propagation delays under the specified test conditions.

XTAL1

7.15 MCS-51 PIN DESCRIPTIONS
)Iss

CMOS GATE

VCC: Supply voltage.
VSS: Circuit ground potential.

P9rt 0: Port 0 is an 8-bit open drain bidirectional 1/0 port.
Figure 7-37. DrIvIng the CHMOS MCS-51 Parts
wIth an External Clock Source·

As an open drain output port it can sink 8 LS TTL loads.
Port 0 pins that have 1s written to them float, and in that
state will function as high-impedance inputs. Port 0 is also

7-32

MCS®-51 ARCHITECTURE

the multiplexed low-order address and data bus during
accesses to external memory. In this application it uses
strong internal pullups when emitting Is. Port 0 also emits
code bytes during program verification. In that application, external pullups are required.

The Port 3 output buffers can sourcelsink 4 LS TTL loads.
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device.
ALEJPI«)G: Address Latch Enable output pulse for
latching the low byte of the address during accesses to
external memory. ALE is emitted at a constant rate of
116 of the oscillator frequency, for external timing or
clocking purposes, even when there are no accesses to
external memory. (However, one ALE pulse is skipped
during each acces to external Data Memory) This pin is
also the program pulse input (PROG) during EPROM
programming.

Port 1: Port I is an 8-bit bidirectional I/O port with internal pullups. The port I output buffers can sink/source
4 LS TTL loads. Port I pins that have I s written to them
are pulled high by the internal pullups, and in that state
can be used as inputs. As inputs, Port I pins that are
externally being pulled low will source current (IlL, on
the data sheet) because of the internal pullups.
In the 8052, pins Pl.O and PI.I also serve the alternate
functions of T2 and T2EX. T2 is the Timer 2 external
input. T2EX is the input through which a Timer 2 "cap.
ture" is triggered.

PSEN: Program Store Enable is the read strobe to external
Program Memory. When the device is executing out of
external Program Memory, PSEN is activated twice each
machine cycle (except that two PSEN activations are
skipped during accesses to external Data Memory). PSEN
is not activated when the device is executing out of internal
Program Memory.

Port 2: Port 2 is an 8-bit bidirectional 1/0 port with internal pullups. The Port 2 output buffers can sink/source
4 LS TTL loads. Port 2 emits the high-order address byte
during accesses to external memory that use 16-bit addresses. In this application it uses the strong internal pullups when emitting Is. Port 2 also receives the high-order
address and control bits during 8751H programming and
verification, and during program verification in the 8051AH.

EAlVPP: When EA is held high the CPU executes out
of internal Program Memory (unless the Program Counter
exceeds OFFFH in the 8051AH, or lFFFH in the 8052).
Holding EA low forces the CPU to execute out of external
memory regardless of the Program Counter value. In the
803IAH and 8032, EA must be externally wired low. In
the 8751H, this pin also receives the 21V programming
supply voltage (VPP) during EPROM programming.

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. It also serves the functions of various special features of the MCS-51 Family, as listed below:
PORT PIN

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

ALTERNATE FUNCTION
RXD (serial Input port)
TXD (serial putput port)
iNTO (external Interrupt 0)
INT1 (external. Interrupt 1)
TO (Timer 0 external Input)
!!JTlmer 1 ext,rnal input)
WR (external data memory
write strobe)
RD (external data memory
read str9i:!e)

XTALl: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.

7-33

MCS®-51 ARCHITECTURE

STATE 11 STATE 21 STATE 31 STATE 41 STATE 51 STATE 61 STATE 1.1 STATE 21

~I~

~I~ ~I~

XTAL2:

ALE:

PSEN:

-+I

, - - - I- - - - - '

DATA

k-SAMPLED

po:

P2:

PCH OUT

Figure 7-38. External Program Memory Fetches

I~I~

STATE 41 ~TATE 51 STATE 61 STATE 1 STATE 21 STATE 31 STATE 41 STATE 51

~I~

XTAl2:

ALE:

PCL OUT IF

RD:
DATA SAMPLED
FLOAT

PO:

P2:

PCH OR
P2SFR

DPH OR P2 SFR OUT

Figure 7-39. External Data Memory Read Cycle

7-34

PCH OR
P2SFR

MCS®-S1 ARCHITECTURE

STATE 41 STATE 51 STATE 81 STATE 1 STATE 31 STATE 21 STATE 41 STATE 51

~I~

XTAL2:

ALE:

PCL OUT IF
PROGRAM MEMORY
IS EXTERNAL

WR:

po:

DATA OUT

PCH OR
P2SFR

DPH OR P2 SFR OUT

Figure 7-40. External Data Memory Write c:ycle

41 STATE 51 STATE 61 STATE 1 ISTATE 21 STATE 31 STATE 41 STATE 51
ISTATE
~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~
XTAL2:

INPUTS SAMPLED:

~J~--,PO, Pl

po, P1

= : r ! - P 2 , P3, RST

MOV PORT, SRC:

OLD DATA

-Lt

P2, P3, R S T = : r ! -

NEW DATA

SERIAL PORT
SHIFT CLOCK
(MODE 0)

-.j

~ RXD PIN SAMPLED

Figure 7·41. Port Operation

7-35

RXD SAMPLED ---l

j.c-

MCS®~51lnstruction

Set

CHAPTER 8
MCS®-S1 INSTRUCTION SET
8.0 INTRODUCTION

• MOVX performs a byte move between the External
Data Memory and the accumulator. The external
address can be specified by the 0 PTR register (16bit) or the R I or RO register (8-bit).

The MCS@-51 instruction set includes III instructions,
49 of which are single-byte, 45 two-byte and 17 three
byte. The instruction op code format consists of a function mnemonic followed by a "destination, source"
operand field. This field specifies the data type and
addressing methodes) to be used.

• MOVC moves a byte from Program memory to the
accumulator. The operand in A is used as an index
into a 256-byte table pointed to by the base register
(DPTR or PC). The byte operand accessed is transferred to the accumulator.

8.1 FUNCTIONAL OVERVIEW
ADDRESS-OBJECT TRANSFER

The MCS-51 instruction set is divided into four functional groups:
•
•
•
•

• MOV DPTR, #data loads 16-bits of immediate data
into a pair of destination re~isters, DPH and DPL.

Data Transfer
Arithmetic
Logic
Control Transfer

8.1.2 Arithmetic
The 8051 has four basic mathematical operations. Only
8-bit operations using unsigned arithmetic are supported directly. The overflow flag, however, permits the
addition and subtraction operation to serve for both
unsigned and signed binary integers. Arithmetic can
also be performed directly on packed decimal (BCD)
representations.

8.1.1 Data Transfer
Data transfer operations are divided into three classes:
• General Purpose
• Accumulator-Specific
• Address-Object

ADDITION

None of these operations affect the PSW flag settings
except a pap or MOV directly to the PSW.

• INC (increment) adds one to the source operand and
puts the result in the operand.
• ADD adds A to the source operand and returns the
result to A.

GENERAL-PURPOSE TRANSFERS

• MOV performs a bit or a byte transfer from the
source operand to ,the destination operand.

• ADDC (add with Carry) adds A and the source
operand, then adds one ( I) if CY is set, and puts the
result in A.

• PUSH increments the SP register and then transfers
a byte from the source operand to the stack location
currently addressed by SP.

• DA (decimal-add-adjust for BCD addition) corrects
the sum which results from the binary addition of
two two-digit decimal operands. The packed decimal
sum formed by DA is returned to A. CY is set if the
BCD result is greater than 99; otherwise, it is cleared.

• POP transfer a byte operand from the stack location
addressed by SP to the destination operand and then
decrements SP.

SUBTRACTION
ACCUMULATOR SPECIFIC TRANSFER~

• XCH exchanges the byte source operand with register A (accumulator).

• SUBB (subtract with borrow) subtracts the second
source operand from the first operand (the accumulator), subtracts one (I) if CY is set and returns the
result to A.

• XCHD exchanges the low-order nibble of the byte
source operand with the low-order nibble of A.

• DEC (decrement) subtracts one (I) from the source
operand and returns the result to the operand.

8-1

MCS®·51 INSTRUCTION SET

• RL, RLC, RR, RRC, SWAP are the five rotate
operations that can be performed on A. RL, rotate left,
RR, rotate right, RLC, rotate left through C, RRC,
rotate right through C, and SWAP, rotate left four.
For RLC and RRC the CY flag becomes equal to the
last bit rotated out. SWAP rotates A left four places to
exchange bits 3 through 0 with bits 7 through 4.

MULTIPLICATION

• M U L performs an unsigned multiplication of the A
register by the B register, returning a double-byte
result. A receives the low-order byte, B receives 'the
high-order byte. OV is cleared if the top half of the
result is zero and is set if it is non-zero. CY is cleared.
AC is unaffected.
DIVISION

TWO-OPERAND OPERATIONS

• DIV performs an unsigned division of the A register by
the B register and returns the integer quotient to A and
returns the fractional remainder to the B register.
Division by zero leaves indeterminate data in registers
A and B and sets OV; otherwise OV is cleared. CY is
cleared. AC is unaffected.

• ANL performs bitwise logical and of with two source
operands (for both bit and byte operands) and returns
the result to the location of the first operand.
• 0 R L performs bitwise logical or of two source operands (for both bit and byte operands) and returns the
result of the location of the first operand.

Unless otherwise stated in the above descriptions, the
flags of PSW are affected as follows:

• XRL performs bitwise logical or of two source operands (byte operands) and returns the result to the location of the first operand.

• CY is set if the operation causes a carry to or from the
resulting high-order bit. Otherwise CY is cleared.
• AC is set if the operation results in a carry from the
low-order four bits of the result (during addition), or
a borrow from the high-order bits to the low-order
bits (during subtraction); otherwise AC is cleared.

8.1.4 Control Transfer
There are three classes of control transfer operations:
unconditional calls, returns and jumps; conditional
jumps; and interrupts. All control transfer operations
cause, some upon a specific condition, the program
execution to continue at a non-sequential location in
program memory.

• OV is set if the operation results in a carry to the
high-order bit of the result but not a carry from the
high-order bit, or vice versa; otherwise 0\1 is cleared.
OV is used in two's-complement arithmetic, because
it is set when the signed result cannot be represented
in 8 bits.

UNCONDITIONAL CALLS, RETURNS
AND JUMPS

• P is set if the mod ulo 2 sum of the eight bits in the
accumulator is I (odd parity); otherwise P is cleared
(even parity). When a value is written to the PSW
register, the P bit remains unchanged, as it always
reflects the parity of A.

Unconditional calls, returns and jumps transfer control
from the current value of the Program Counter to the
target address. Both direct and indirect transfers are
supported.

8.1.3 Logic
• ACALL and LCALL push the address of the next
instruction onto the stack and then transfer control
to the target address. ACALL is a 2-byte instruction
used when the ,target address is in the current 2K
page. LCALL is a 3-byte instruction that addresses
the full 64K program space. In ACALL, immediate
data (i.e. an II bit address field) is concatenated to
the five most significant bits of the PC (which is
pointing to the next instruction). If ACALL is in the
last 2 bytes of a 2K page then the call will be made to
the next page since the PC will have been incremented to the next instruction prior to execution.

The 8051 performs basic logic operations on both bit
and byte operands.
SINGLE-OPERAND OPERATIONS

• CLR sets A or any directly addressable bit to zero (0).
• SETB sets any directly addressable bit to one (I).
• CPL is used to compliment the contents of the A
register without affecting any flags, or any directly
addressable bit location.

8-2

MCS$-S1INSTRUCTION SET

• RET transfers control to the return address saved on
the stack by a previous call operation and decrements the SP register by two (2) ,to adjust the SP for
the popped address.

made between A directly addressable bytes in Internal
Data Memory or between an immediate value and
either A, a register in the selected Register Bank, or a
Register-Indirect addressed byte of Internal RAM.

• AJM p, U M P'and SJ M P transfer controlto the target
operand. The operation of AJMP and UMP are
analogous to ACALL and LCALL. The SJMP (short
jump) instruction provides for transfe.rs within a 256
byte range centered a,bout the starting address of the
next instruction (-128 to + 127).

• DJNZ dec;rements the source operand and returns the
result to the operand. Ajump is performed if the result
is not zero. The source operand of the DJNZ instruction may be any byte in the Internal Data Memory.
Either Direct or Register Addressing may be used to
address the source operand.

• JMP @A+DPTR performs a jump relative to the
DPTR register. The operand in A is used as the offset
(0-255) to the address in the DPTR register. Thus, the
effective destination for ajump can be anywhere in the
Program Memory space.

INTERRUPT RETURNS

• RET! transfers control as does RET, but additionally enables interrupts of the current priority level.
1

8.2 INSTRUCTION DEFINITIONS
CONDITIONAL JUMPS

Each of the 51 basic MCS-51 operations, ordered
alphabetically according to the operation mnemonic
are described beginning page 8-8.

,Conditional jumps perform a jump contingent upon a
specific condition. The destination will be within a 256'byte range centered about the starting address of the
next instruction (-128 to +127).

A brief example of how the instruction might be used is
given well as its effect on the PSW flags. The number
of bytes and machine cycles required,the binary machine~
,language encoding, and a symbolic description or restatem~nt of the function is also provided.

• JZ performs a jump if the accumulator is zero.
'. J NZ performs a jump if the accumulator is not zero.
• JC performs a jump if the carry flag is set.

Note: Only the carry, auxiliary-carry, and overflow flags
are discussed. The parity bit is computed after every instruction cycle that alters the accumulator. Similarly,
instructions which alter directly addressed registers could
affect the other status flags if the instruction is applied to
the PSW. Status flap can also be modified by bitmanipUlation.

• JNC performs a jump if the carry flag is not set.
• JB performs ajump if the Direct Addressed bit is set.
• JNB performs a jump if the Direct Addressed bit is
not set.
• JBC performs a jump if the Direct Addressed bit is
set and then clears the Direct Addressed bit.

For details on the MCS-SI assembler, ASM51, refer to
the MCS-51 Macro Assembler User's Guide, publication
number 9800937,

• CJNE compares the first operand to the second operand and performs ajump if they are not equal. CY is
set if the first operand is less than the second operand; otherwise it is cleared. Comparisons can be

Table 8-1 summarized the M ':-51 instruction set.
-

8-3

'--..............

MCSI!!>-51 INSTR!JCrION SEr

, Table 8-1. 8051 Instruction Set Summary
Notes on instruction'set and addressing modes:
Rn
-Register R 7-RO of the currently selected Register
Bank.
-8obit internal data location's address. This cduld be
direct
an Internal Data RAM location (0-127) or'a SFR
[Le., I/O port, control register, status register, etc.
(128-255)]. ,
,
@Ri
-8obit internal data RAM location (0-255) addressed
indirectly through register R I or RO.
#data -8-bit constant included in instruction.
#data 16 -16-b.t constant included in instruction
addr 16 -16-bit destination address. Used by LCALL &
LJ M P. A branch can be anywhere within \he 64Kbyte Program Memory address space. ,
addr II -II-bit destination address. Used by ACALL &
AJMP. The branch will be within the same 2K-byte
page of program memory as' the first byte of the
following instruction.
reI
-Signed (two's complement) 8-bit offset byte. Used
by SJMP and all conditional jumps. Range is -128
to + 127 bytes relative to first byte of the following
instructiol1.
bit
-Direct. Addressed bit in Internal Data RAM or
Special Function Register.
:"'New operation 110t provided by 8048AH/8049AH.

Interrupt Response Time: To fimsh execution of current instruction, respond to the interrupt request, push the PC and to
vector to the first instruction of the interrupt service program
requires 38 to 81 oscillator periods (3 to 7IlS @ 12 MHz).
INSTRUCTIONS THAT AFFECT FLAG SETTINGS'
INSTRUCTION

FLAG

INSTRUCTION

OYAC
X X CLRC
X X CPLC
X, X ANLC,bit
o X
ANL C,/bit
o X
ORLC,bit
X
ORLC,bit
X
MOYC,bit
,X
CJNE
I

ADD
ADDC
SUBB
MUL
DIY
DA
RRC
RLC
SETBC

FLAG
C OYAC

C
X
X
X

o .
X
X
X

X
X
X

'Note that operations on SFR byte address 208 or bi! addresses 209-215 (Le., the PSW or bits in the,PSW) will also
affect flag settIngs.

ARITHMETIC OPERATIONS

Mnemonic
ADD

A,Rn

ADD

A,direct

ADD

A,@Ri

ADD

A,#data

ADDC

A,Rn

ADDC

A,dlrect

ADDC

A,@Ri

ADDC

A,#data

SUBB

A,Rn

SUBB

A,direct

Description
Add register to
Accumulator
Add direct byte to'
Accumulator
Add indirect RAM
to Accumulator
Add immediate
data to
Accumulator
Add register to
Accumulator
with Carry
Add direct byte to
Accumulator
with Carry
Add indirect
RAM to
Accumulator
with Carry
Add immediate
data to Acc
with Carry
Subtract register
from Acc with
borrow
Subtract d.rect
byte from Acc
with borrow

ARITHMETIC QPERATIONS Cont.
Osclllato~

Oscillator
Byte
Period

Mnemonic

12
2

SUBB

A,@Ri

SUBB

A,#data

12
12

12
INC

INC
INC

Rn
direct

INC

@Ri

DEC

direct

DEC

@Ri

INC

DPTR

MUL
DIY
DA

AD
AB
A

Deseription

Byte

Period

S'ubtract indirect
RAM fromAcc
with borrow
Subtract
immediate data
from Acc with
borrow
Increment
Accumulator
Increment register
Increment direct
byte
Increment indirect
RAM
Decrement
Accumulator
Decrement
Register
Decrement direct
byte
Decrement
indirect RAM
Increment Data
Pointer
Multiply A & B
Divide A byB
Decimal Adjust
Accumulator

I
2

12
12

All mnemoniCs copYrighted @lotelCorporation 1980

8-4

.12
12
2

12
12
24
48
48
12

MCS~-51INSTRUCTION

SET

Table 8-1. 8051 Instruction Set Summary (Continued)
LOGICAL OPERATIONS Coni.

LOGICAL OPERATIONS

Mnemonic
ANL
ANL
ANL

ANL

ANL
ANL
ORL
ORL
ORL
ORL

ORL
ORL
XRL

XRL

A,Rn

Description

AND register to
Accumulator
AND direct byte
A,direct
to Accumulator
A,@Ri
AND indirect
RAM to
Accumulator
A,#data
AND immediate
data to
Accumulator
dlrect,A
AND Accumulator
to direct byte
direct,#data AND immediate
data to direct byte
A,Rn
OR register to
Accumulator
A,direct
OR direct byte to
Accumulator
A,@Ri
OR indirect RAM
to Accumulator
A,#data
OR immediate
data to
Accumulator
direct,A
OR Accumulator
to direct byte
direct,#data OR immediate
data to direct byte
A,Rn
ExclUSive-OR
register to
Accumulator
A,direct
Exclusive-OR
direct byte to
Accumulator

Oscillator
Byte
Period
I

Mnemonic
XRL

XRL
12

XRL
2

XRL

CLR

CPL

RLC

RR
2

RRC

SWAP
2

Description

Byte

A,@Ri

Exclusive-OR
indirect RA M to
Accumulator
A,#data
Exclusive-OR
immediate data to
Atcumulator
Exclusive-OR
direct,A
Accumulator to
direct byte
direct,#data Exclusive-OR
immediate data
to direct byte
A
Clear
Accumulator
Complement
A
Accumulator
Rotate
A
Accumulator Left
Rotate
A
Accumulator Left
through the Carry
Rotate
A
Accumulator
Right
A
Rotate
Accumulator
Right through
the Carry
A
Swap nibbles
Within the
Accumulator

All mnemonics copynghted @Intel CorporatIOn 1980

8-5

Oscillator
Period
12

12
12
12
12

MOS@·S1INSTRUOTION SET

Table 8-1. 8051 Instruction Set Summary (Continued)
DATA TRANSFER

DATA TRANSFER Cont.

Mnemonic

Description

MOY

A,Rn

MOY

A,direct

MOY

A,@Ri

MOY

A,#data

MOY

Rn,A

Move
register to
Accumulator
Move direct
byte to
Accumulator
Move indirect
RAMto
Accumulator
Move
immediate
data to
Accumulator
Move

Byte

Oscillator
Period

Mnemonic

MOY

MOYC

MOYX

Accumulator

MOY

Rn,direct

Rn,#data

direct,A

MOY

direct,Rn

MOY

direct,direct

MOY

direct,@Ri

MOY

direct,#data

MOY

@Ri,A

MOY

@Ri,dtrect

MOY

@Ri,#data

to register
Move direct
byte to
register
Move
immediate data
to register
Move
Accumul"tor
to direct byte
Move register
to direct byte
Move direct
byte to direct
Move indirect
RAMto
direct byte
Move
immediate data
to direct byte
Move
Accumulator to
indirect RAM
Move direct
byte to
indirect RAM
Move
immediate
data to
mtlirect RAM

24
MOYX

12
MOYX

12
PUSH

24
POP

24
2

XCH

12
XCH

XCHD

Description

Byte

Oscillator
Period

DPTR,#dataI6 Load Data
Pointer with a
l6-bit constant
A,@A+DPTR Move Code
byte relative fo
DPTR to Ace
A,@A+PC
Move Code
byte relative to
PC to Ace
A,@Ri
Move
External
RAM (8-bit
addr) to Acc
A,@DPTR
Move
External
RAM (l6-bit
addr) to Ace
@Ri,A
Move Aceto
External-RAM
(8-bit addr)
@DPTR,A
Move Aceto
External RAM
(l6-bit addr)
direct
Push direct
byte onto
stack
direct
Pop direct
byte from
stack
A,Rn
Exchange
register with
Accumulator
A,direct
Exchange
direct I>yte
with
Accumulator
A,@Ri
Exchange
indired RAM
with
Accumulator
A,@Ri
Exchange loworder Digit
indirect RA M
with Ace

All mnemoniC!> copYrighted ©Intel Corporation 1980

8-6

MCS®-51 INSTRUCTION SET

Table 8-1. 8051 Instruction Set Summary (Continued)
BOOLEAN VARIABLE MANIPULATION

Mnemonic
CLR
CLR
SETB
SETB
CPL

C
bit
C
bit
C

CPL

bit

ANL

C.bit

ANL

C,/bit

ORL

C.bit

ORL

C,/bit

MOV

C,bit

MOV

bit,C

rei

Description
Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement
Carry
Complement
direct bit
AND direct bit
to Carry
AND compleme~t
of direct bit
to Carry
OR direct bit
to Carry
OR complement
of direct bit
to Carry
Move direct bit
to Carry
Move Carry to
direct bit
Jump if Carry

PROGRAM BRANCHING Conl

Byte
I
2
I
2

O~.cillator

Oscillator
Period

Mnemonic
RETI

12
12
12
12
12

AJMP
LJMP
SJMP

JNZ

JMP

CJNE
2

CJNE

is set

JNC

rei

bit, rei

JNB

bit, rei

JBC

bit,rel

Jump if Carry
not set
JljffiP if direct
Bit is set
Jump if direct
Bit is Not set
Jump if direct
Bit is set &
clear bit

CJNE

24
24

CJNE
24

DJNZ
PROGRAM BRANCHING

Mnemonic
ACALL addrll

LCALL addrl6

RET

Description
- Absolute
Subroutine
Call
Long
Subroutine
Call
Return from
Subroutine

Byte

Oscillator
Period

DJNZ

NOP

Do:scription

Byte

Return from
interrupt
addrll
Absolute'
Jump
addrl6
Long Jump
rei
Short Jump
(relative addr)
@A+DPTR
Jump indirect
relative to the
DPTR
rei
Jump if
Accumulator
is Zero
rei
Jump if
Accumulator
. is Not Zero
A,direct,rel
Compare
direct byte to
Ace and Jump
if Not Equal
A,#data,rel
Compare
immediate to
Acc.and Jump
iLNot Equal
Rn,#data,rel
Compare
immediate to
register and
Jump If Not
Equal
@Ri,#data,rel Compare
immediate to
indirect and
Jump if Not
Equal
Rn,rel
Decrement
register and
Jump if Not
Zero
direct, rei
Decrement
direct byte
and Jump if
Not Zero
No Operation

All mnemonics copYrighted ©Intel Corporation 1980

8-7

Period
24

24
24

MCS@·S1 INSTRUCTION SET

ACALL

addr11

Function:
Description:

Example:

Absolute Call
ACALL unconditionally calls a subroutine located at the indicated address.
The instruction increments the PC twice to obtain the address of the following
instruction, then pushes the 16-bit result onto the stack (low-order byte first)
and increments the stack pointer twice. The destination address is obtained by
successively concatenating the five high-order bits of the incremented PC, opcode bits 7-5, and the second byte of the instruction. The subroutine called must
therefore start within the same 2K block of the program memory as the first
byte of the instruction following ACALL. No flags are affected.
Initially SP equals 07H. The label "SUBRTN" is at program memory location
0345H. After executing the instruction,
ACALL

SUBRTN

at location 0123H, SP will contain 09H, internal RAM locations OSH and O9H
will contain 25H and OIH, respectively, and the PC will contain 0345H.
Bytes:
Cycles:
Encoding:
Operation:

2
2

IaIO

a9 as

I 0 0 0 1

I Ia7

ACALL
(PC)---(PC) + 2
(SP) ~ (S]» + 1
«SP»-(PC7-0)
(SP) ---- (SP) + I
«SP» -(PCI5-S)
(PClO-O)-page address

8-8

a6 as

a41 a3 a2 al

MCS®·51 INSTRUCTION SET'

ADD

Function:
Description:

Add
ADD adds the byte variable indicated to the accumulator, leaving the result in
the accumulator. The carry and auxiliary-carry flags are set, respectively, if
there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit
7 but not bit 6; otherwise OV is cleared. When adding signed integers, OV in-

dicates a negative number produced as the sum of two positive operands, or a
positive sum from two negative operands.

Example:

Four source operand addressing modes are allowed: register, direct, registerindirect, or immediate.
The accumulator holds OC3H (llOOOOllB) and register 0 holds OAAH
(lOlOlOlOB). The instruction,
ADD

A,RO

will leave 6DH (01 101 lOlB) in the accumulator with the AC flag cleared and
both the carry flag and OV set to 1.

ADD

A,Rn
Bytes:
Cycles:

Encoding:
Operation:
ADD

0 0

o 11

r r r

ADD
(A)_ (A) + (Rn)

A,direct
2
Bytes:
Cycles:
1

Encoding:

Operation:

ADD
(A)- (A) + (direct)

01 0

11 Idirect a,ddress I

8-9

MCS®~51

INSTRUCTION S~T

ADD A,@RI
Bytes:
Cycles:

01 0

Encoding:

Operation:

ADD
(A)- (A) + «Ri»

1 1 i

ADD A,#data
Bytes:
Cycles:

Encoding:

Operation:

ADD
(A)_ (A) + #data

0 01 I immediate data I

8-10

MCS@-51 INSTRUCTION SET·

ADDC

Function:
Description:

Add with Carry
ADDC simultaneously adds the byte variable indicated, the carry flag and the
accumulator contents, leaving the result in the accumulator. The carry and
auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit
3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carryout of bit 7
but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV
indicates a negative number produced as the sum of two positive operands or a
positive sum from two negative operands.

Example:

Four source operand addressing modes are allowed: register, direct, registerindirect, or immediate.
The accumulator holds OC3H (llOOOOllB) and register 0 holds OAAH
(lOlOlOlOB) with the carry flag set. The instruction,
ADDC

A,RO

will leave 6EH (OllOlllOB) in the accumulator with AC cleared and both the
carry flag and OV set to 1.
ADDC

A,Rn
Bytes:
Cycles:

Operation:

ADDC
(A)_(A) + (q + (Rn)

r rl

Encoding:

AD DC

A,direct
Bytes:
2
Cycles:
1

Encoding:
Operation:

Idirect address I

ADDC
(A)-(A) + (q + (direct)

8-11

MCS®-51 INSTRUCTION SET

ADDC

A,@Ri
Bytes:
Cycles:

Encoding:
Operation:

100111011

ADDC
(A)- (A)

+ (C) + «RU)

ADDC

A,#data
Bytes:
2
Cycles:

Encoding:
Operation:

AJMP

1 1 0

1 0 0

I Iimmediate data I

ADDC
(A)"-: (A) + (C) + #data

addr11

. Function:
Description:

Example:

Absolute Jump
AJMP transfers program execution to the indicated address, which is formed at
run-time by concatenating the high-order five bits of the PC (after incrementing
the PC twice), opcode bits 7-5, and the second byte of the instruction. The
destination must therefore be within the same 2K block of program memory as
the first byte of the instruction following AJMP.
The label "JMPADR" is at program memory location 0123H. The instru<.:tion,
AJMP

JMPADR

is at location 0345H and will load the PC with 0123H.
Bytes:
Cycles:

2
2

Encoding:

I alO

Operation:

AJMP

a9 as 0 0 0 0

I I a7

(PC)- (PC) + 2

(PClO-O)_ page address

8-12

a6 a5

a41 a3

MCS®-51 INSTRUCTION SET

ANL

Function:
Description:

Logical-AND for byte variables
ANL performs the bitwise logical·AND operation between the variables indicated and stores the results in the destination variable. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the accumulator, the source can use register, direct, register-indirect, or
immediate addressing; when the destination is a direct address, the source can
be the accumulator or immediate data.

Example:

Note: When this instruction is used to modify an output port, the value used as
the original port data will be read from the output data latch, not the input
pins.
If the accumulator holds OC3H (llOOOOllB) and register 0 holds OAAH
(lOlOlOlOB) then the instruction,
ANL

A,RO

will leave 41H (OlOOOOOlB) in the accumulator.
When the destination is a directly addressed byte, this ,instruction will clear
cOIl}binations of bits in any RAM location or hardware register. The mask byte
determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the accumulator at run-time.
The instruction,
ANL

Pl,#OlllOOllB

will clear bits 7, 3, and 1 of output port l.
ANL

A,Rn

Bytes:
Cycles:
Encoding:
Operation:

10
ANL
(A)_ (A)

(Rn)

8-13

MCS®-51 INSTRUCTION SJET

ANL

A,~irect

Bytes:
Cycles:

Encoding:

Operatjpn:

ANL
(A)- (A)

ANL

0 1 0 1 0 1
1
1\

(direct)

A,@RI
Bytes:
Cycles:

Encoding:

10 1 0 1 1 0 1 1 i 1

Operation:

ANL
(A) _

ANL

A,#data
Bytes:
Cycles:

Encoding:
Operation:
ANL

I direct address I

(A)

«Ri»

2
1

lii 0
ANL
(A)_(A)

I immedillte data I

11 0 1 0 01
1\

#data

direct,A
Bytes:
2
Cycles:
1

Encoding:

Operation:

ANL

0 11 0 0 1 01

(direct)-(cJirect)

direct address

(A)

ANL .direct,#data
Bytes:
3
Cycles:
2
Encoding:

Operation:

ANL

0 11 0

(direct) _

(direct)

#data

direct address

8-14

Iimmediate data I

MCS@-51 INSTRUCTION SET

ANL

Function:
Description:

Example:

Logical-AND for bit variables
If the Boolean value of the source bit is a logical 0 then clear the carry flag;
otherwise leave the carry flag in its current state. A slash ("I") preceding the
operand in the assembly language indicates that the logical complement of the
addressed bit is used as the source value, but the source bit itself is not affected.
No other flags are affected.
Only direct bit addressing is allowed for the source operand.
Set the carry flag if, and only if, P 1.0 = 1, ACC. 7 = 1, and OV = 0:
MOV C,Pl.O
ANL C,ACC.7
ANL C,IOV

ANL

C,bit
Bytes:
Cycles:

2
2

Encoding:

Operation:

ANL
(C}-(C) II (bit)

C,/bit
Bytes:
Cycles:
Encoding:

;LOAD CARRY WITH INPUT PIN STATE
;AND CARRY WITH ACCUM. BIT 7
;AND WITH INVERSE OF OVERFLOW
FLAG

0 0 01 0 0

1 01

Ibit address I

Ibit address 1

ANL

Operation:

CJNE

2
2
0

0 0 0 01

ANL
(C) ,, rei

Function:
Description:

Compare and Jump if Not Equal.
CJNE compares the magnitudes<>f the first two operands, and branches if their
values are not equal. The branch destination is computed by adding the signed
relative-displacement in the last instruction byte to the PC, after incrementing
the PC to the start of the next instruction. The carry flag is set if the unsigned
integer value of is less than the unsigned integer value of ;
otherwise, the carry is cleared. Neither operand is affected.
8-15

MCS®-51 INSTRUCTION SET

.Example:

The first two operands allow four addressing mode combinations: the accumulator may be compared with any directly addre~sed byte or immediate
data, and any indirect RAM location or working register can be compared with
an immediate constant.
The accumulator contains 34H. Register 7 contains 56H. The first instruction in
the sequence,
CJNE
NOTJQ:

R7,#60H, NOTJQ
R7 = 60H.
IF R7 <60H.
R7>60H.

sets the carry flag and branches to the instruction at label NOTJQ. By testing
the carry flag, this instruction determines whether R7 is greater or less than
60H.
If the data being presented to port I is also 34H, then the instruction,

WAIT:

CJNE

A,P1,WAIT

clears the carry flag and continues with the next instruction in sequence, since
the accumulator does equal the data read from Pl. (If some other value was being input on PI, the program will loop at this point until the PI data changes to
34H.)

CJNE

A,direct,rel
Bytes:
3
Cycles:
2

Encoding:

Operation:

(PC) ~ (PC) + 3
IF (A) <> (direct)

1 1 0

1 0

I Idirect address I IreI. address I

THEN
(PC)

(PC)

relative offset

IF (A) < (direct)

THEN
(C)

(C)

ELSE

8-16

MCS®-51 INSTRUCTION SET

CJNE

A,#data,rel
Bytes:
3
Cycles:
r:2_ _ _-.-_ _ _--,
Encoding:
1 0 1 1
1 0

I°

Operation:

(PC) -

(PC)

°I

Iimmediate datal I reI. address I

IF (A) <> data

THEN
(PC) -

(PC)

relative offset

IF (A) < data

THEN
(C) -1

ELSE
(C) - 0

CJNE

Rn,#data,rel
Bytes:
3
Cycles:
2

Encoding:
Operation:

1 111

r r

I Iimmediate data I Irei. address I

(PC) - (PC) + 3
IF (Rn) <> data

THEN
(PC) IF (Rn)

(PC)

relative offset

< data

THEN
(C) -1

ELSE
(C) - 0

CJNE

@Ri,#data,rel
Bytes:
3
Cycles:
2

Encoding:

I'-I_O__I_I-LI_O___--'iI I immediate data I IreI. address I

Operation:

(PC) -

«Ri»

+ 3
<> data

(PC)

THEN
(PC) -

(PC)

«Ri» < data

relative offset

THEN
(C) - 1

ELSE
(C) -

8-17

MCS®·51INSTRUCTION,SET

CLR

Function:
Description:
Example:

Clear Accumulator
The accumulator is cleared (all bits set to zero) .. No flags are affected.
The accumulator contains 5CH (OlOIlIOOB). The instruction,
CLR

will leave the accumulator set to OOH (OOOOOOOOB).

Bytes:
Cycles:
Encoding:

Operation:

CLR

0 o_1_0----'0

_I_ _ _-,-I

I' -

CLR
(A)-O

bit

Function:
Description:
Example:

Clear bit
The indicated bit is cleared (reset to zero). No other flags are affected. CLR can
operate on the carry flag or any directly addressable bit~
Port I has previously been written with 5DH (OlOlllOIB). The instruction,
P1.2

CLR

will leave the port set to 59H (OlOllOOIB).

CLR

C
Bytes:
Cycles:

Encoding:

Operation:

CLR
(C)-O

CLR

bit
Bytes:
Cycles:

01 ° 0

° 01 ° ° 1

Encoding:

Operation:

CLR
(bit)-O

01 Ibit address I

8-18

, MCS®·51 INSTRUCTION SET

CPL

Function:
Description:
Example:

Complement Accumulator
Each bit of the accumulator is logically complemented (one's complement). Bits
which previously contained a one are changed to zero and vice-versa. No flags
are affected.
The accumulator contains SCH (010111ooB). The instruction,
CPL

Bytes:
Cycles:

will leave the accumulator set to OA3H (101oooUB).
1
1

Encoding:
Operation:

11 0

O--y]

CPL
'(A)_, (A)

CPL

bit

Function:
Description:

Example:

'Complement bit
The bit variable specified is complemented. A bit which had been a one is
changed to zero and vice-versa. No other flags are affected. CLR can operate
on the carry or any directly addressable bit.

Note: When this instruction is used to modify an output pin, the value used as
the original data: will be read from the output data latch, not the input pin.
Port 1 has previously been written with SBH (01011101B). The instruction sequence,
CPL
CPL

Pl.l
P1.2

will-leave the port set

CPL

to SBH (01011011B). '

C
Bytes:
Cycles:

Encoding:
Operation:

1'-1_0_----'11,-0_0_1---111
CPL

(q---,(q

MCS®~51

CPL

bit
Bytes:
Cycles:

Encoding:
Operation:

INSTRUCTION SET

2
1

1 0 0

1 0

I Ibit address I

CPL
(bit)----, (bit)

Function:
Description:

Decimal-adjust Accumulator for Addition
DA A adjusts the eight-bit value in the accumulator resulting from the earlier
addition of two variables (each in packed-BCD format), producing two four-bit
digits. Any ADD or ADDC instruction may have been used to perform the addition.
If accumulator bits 3-0 are greater than nine 9] v [(AC) = 1]]
THEN (A3-0)_(A3-0) + 6
AND
IF [[(A7.4) >9] v [(C) = 1]]
THEN (A7-4)- (A7-4) + 6

8-21

DEC

byte

Function:
Description:

Example:

Decrement
'I
The variable indica~ed i$, decremented by 1. An original value of OOH will
underflow to OFFH. No flags are affected. Four operanc! ad~ressing modes are
allowed: accumulator, register, direct, or register~indirect.

Note: When this instruction is used to modify an output port, the value used as
the, original port data will be read from the output data latch, not the input
pins.
Register 0 contains 7FH (01111111B). Internal RAM locations 7EH and 7FH
contain OOH and 4OH, respectively. The instrnction sequence,
DEC @RO
DEC RO
DEC @RO
will leave register 0 set to 7EH and internal RAM locations 7EH and 7FH set to
OFFH and 3FH.

DEC' A
Bytes:
Cycles:
Encoding:
Operation:
DEC

10 0 0

11 0 1 0 0 1

DEC
(A)_(A) -' 1

Rn
Bytes:
Cycles:

Encoding:
Operation:

1000111rrr
DEC
(Rn)_ (Rn) - 1

8-22

MCS®-S1 INSTRUCTION SET

DEC

direct
Bytes:
Cycles:

Encoding:

!O 0 0 1!0 1 0

Operation:

DEC
(direct)_ (direct) - 1

DEC

!directaddress!

@Ri
Bytes:
Cycles:

Encoding:
Operation:

10001101

DEC

«Ri»- «Ri» - 1
DIV

Function:
Description:

Example:

Divide
DIV AB divides the unsigned eight-bit integer in the accumulator by the unsigned eight-bit integer in register B. The accumulator receives the integer part
of the quotient; register B receives the integer remainder. The carry and OV
flags will be cleared.
Exception: if B had originally contained OOH, the values returned in the accumulator and B-register will be undefined and the overflow flag will be set.
The carry flag is cleared in any case.
The accumulator contains 251 (OFBH or l1111011B) and B contains 18 (12H or
000100lOB). The instruction,
DIV

Bytes:
Cycles:
. Encoding:
Operation:

will leave 13 in the accumulator (ODH or 0000llOlB) and the value 17 (11 H or
0OOI000IB) in B, since 251 = (13 x 18) + 17. Carry and OV will both be
cleared.
1
4
1100010100
DIV
(A)15-8 _
(B)7-0

(A) / (B)

8-23

MCS®-S1 INSTRUCTION SET

DJNZ·

Function:
Description:

Decrement and Jump if Not Zero
DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original
value of OOH will underflow to OFFH. No flags are affected. The branch
destination would be computed by· adding the signed relative-displacement
value in the last instruction byte to the PC, after incrementing the PC to the
first byte Of the following instruction.
The location decremented may be a register or directly addressed byte.

Example:

Note: When this instruction is used to ~odjfy an output port, the value used as
the original port data will be read from the output data latch, not the input
pins.
Internal RAM locations 4OH, 50H, and 60H contain the values OIH, 70H, and
I5H, respectively. The instruction sequence,
DJNZ
DJNZ
DJNZ

40H,LABEL_I
50H,LABEL~

60H,LABEL_3

will cause a jump to the instruction at label LABEL~ with the values OOH,
·6FH, and I5H in the three RAM locations. The first jump was not taken
because the result was zero.
This instruction provides a simple way of executing a progmm loop a given
number of times, or for adding a moderate time delay (from 2 to 512 machine
cycles) with a single instruction. The instruction sequence,
TOGGLE:

MOV
CPL
DJNZ

R2,#8
Pl.7
R2, TOGGLE

will toggle Pl.7 eight times, causing four output pulses to appear at bit 7 of output port 1. Each pulse will last three machine cycles; two for DJNZ and one to
alter the pin.

8-24

MCS®-S1 INSTRUCTION SET

DJNZ

Rn,rel
Bytes:
Cycles:

Encoding:
Operation:

2
2

1 11

I Idirect address I

r r

DJNZ
(PC)- (PC)

(Rn)_ (Rn) - 1
IF (Rn) > 0 or (Rn) < 0
THEN
(PC)- (PC)

+ rei

DJNZ

direct,rel
Bytes:
3
Cycles:
2

Encoding:
Operation:

1 0 1 0 1

I Idirect address I IreI. address

DJNZ
(PC)- (PC)

(direct)_ (direct) - 1
IF (direct) > 0 or (direct) < '0
THEN
(PC)- (PC) + reI

INC

Function:
Description:

Increment
INC increments the indicated variable by 1. An original value of OFFH will
overflow to OOH. No flags are affected. Three addressing modes are allowed:
register. direct, or register-indirect.

Note: When this instruction is used to modify an output port, the value used as
the original port data wili be read from the output data latch, not the input
pins.

8-25

MCS®·51INSTFlUCTION SET

Example:

Register 0 contains 7EH (011J.11l1OB). Internal RAM locations 7EH and 7FH
contain OFFH and 40H, respectively. The instruction sequence,
INC
INC
INC

@RO
RO
@RO

will leave register 0 set to 7FH and internal RAM loc:ations 7EH and 7FH
holding (respectively) OOH and 41H.

INC

A
Bytes:
Cycles:

Encoding:
Operation:

0 0 0 I0

o-y]

INC
(A)_ (A) +

INC

Rn
Bytes:
Cycles:

Encoding:
Operation:
INC

direct
Bytes:
Cycles:

Encoding:
Operation:

li_r_r iJ

0 0 0

INC
(Rn)-(Rn)

0 0 0 0

1 0

I Idirect address I

INC
(direct),-'- (direct) +

8-26

MCS®-51 INSTRUCTION SET

INC

@Ri
Bytes:
Cycles:

° ° 0\01

Encoding:

Operation:

INC
«Ri»_ «Ri» + 1

INC

DPTR

Function:
Description:

Example:

Increment Data Pointer
Increment the 16-bit data pointer by I. A 16-bit increment (modulo 2 16) is performed; an overflow of the low-order byte of the data pointer (DPL) from
OFFH to OOH will increment the high-order byte (DPH). No flags are affected.
This is the only 16-bit register which can be incremented.
Registers DPH and DPL contain 12H and OFEH, respectively. The instruction
sequence,
INC
INC
INC

DPTR
DPTR
DPTR

will change DPH and DPL to 13H and OIH.

Bytes:
Cycles:
Encoding:
Operation:

1
2

_1_0_ _0-,--10__
0_1_1-,

<-I

INC
(DPTR)_ (DPTR) + 1

8-27

MCS@-51 INSTRUCTION SET

bit,rel

Func::tion:
Description:

Example:

Jump if Bit set
If the indicated bit is a one, jump to the address indicated; otherwise proceed
with the next instruction. The branch destination is computed by adding the
signed relative-displacement in the third instruction byte to the PC" after incrementing the PC to the first byte of the next instruction. The bit tested is not
modified. No flags are affected.
The data present at input port 1 is llOOlOlOB. The accumulator holds 56
(010101 lOB). The instruction sequence,
JB
JB

Bytes:
Cycles:
Encoding:
Operation:

JBC

P1.2,LABELl
ACC.2,LABEL2

will cause program execution to branch to the instruction at label LABEL2.
3
,2

1 0 0 0 0 0

I I bit address I I reI. address I

JB
(PC) - (PC) + 3
IF (bit) = 1
THEN
(PC) -(PC) + reI

bit,rel

Function:
Description:

Example:

Jump if Bit is set and Clear bit
If the indicated bit is one, branch to the address indicated; otherwise proceed
with the next instruction. In either case, clear the designated bit. The branch
destination is computed by adding the signed relative-displacement in the third
instruction byte to the PC, after incrementing the PC to the first byte of the
next instruction. No flags are affected.

Note: When this instruction is used to test an output pin, the value used as the
original data will be read from the output data latch, not the input pin.
The accumulator holds 56H (010101 lOB). The instruction sequence,
JBC
JBC

ACC.3,LABELl
ACC.2,LABEL2

will cause program execution to continue at the instruction identified by the
label LABEL2, with the accumulator modified to 52H (OlOlOOlOB).

8-28

MC$@-511.NSTRUCTION SET

Bytes:
Cycles:
Encoding:.
Operation:

I° 0

°I I

bit address

I IreI. address I

JBC
(PC) (PC) + 3
IF (bit) = 1
THEN
(bit)_O
(PC)- (PC) + reI

rei

Function:
Description:

If the carry flag is set, branch to the address indicated; otherwise proceed with

Example:

the next instruction. The branch destination is computed by adding the signed
relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. No flags are affected.
The carry flag is cleared. The instruction sequence,

Jump if Carry is set

JC
LABELl
CPL C
JC
LABEL2
will set the carry and cause program execution to continue at the instruction
identified by the label LABEL2.
Bytes:
Cycles:
Encoding:
Operation:

2
2

I° 1

°I°

0 0

°I I

reI. address

JC
(PC)-(PC) + 2
IF (C) = 1
THEN
(PC) 4 - (PC) + reI

8-29

MCS®-S1 INSTRUCTION SET

JMP

@A+DPTR

Function:
Description:

Example:

Jump indirect
Add the eight-bit unsigned contents of the accumulator with thlr sixteen-bit data
pointer, and load the resulting sum to the program counter. This will be the address for subsequent instruction fetches. Sixteen-bit addition is performed
(modulo 2 16): a carry-out from the low-order eight bits propagates through the
higher-order bits. Neither the accumulator nor the data pointer is altered. No
flags are affected.
An even number from 0 to 6 is in the accumulator. The following sequence of
instructions will branch to one of four AJMP instructions in a jump table starting at JMP_ TBL:
MOV

JMP_ TBL:

Bytes:
Cycles:

DPTR,#JMP_TBL
@A+DPTR
LABELO
LABELl
LABEL2
LABEL3

If the accumulator equals 04H when starting this sequence, execution will jump
.to label LABEL2. Remember that AJMP is a two-byte instruction, so the jump
instructions start at every other address.
1
2

Encoding:
1

Operation:

JMP
AJMP
AJMP
AJMP
AJMP

JMP
(PC)~(A)

+ (DPTR)

8-30

MCS®-S1 INSTRUCTION SET

JNB

blt,rel

Function:
Description:

Example:

Jump if Bit Not set
If the indicated bit is a zero, branch to the indicated address; otherwise proceed
with the next instruction. The branch destination is computed by adding the
signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not
modified. No flags are affected.
The data present at input port 1 is 11 0010 lOB. The accumulator holds 56H
(010101IOB). The instruction sequence,
JNB
JNB

Bytes:
Cycles:

P1.3,LABELl
ACC.3,LABEL2

will cause program execution to continue at the instruction at label LABEL2.
3
2

Encoding:

Operation:

JNB
(PC)- (PC) + 3
IF (bit) = 0
THEN (PC) -

JNC

1 0 0 0 0

I Ibit actdress I IreI. addres!l

(PC) + reI.

rei

Function:
Description:

Example:

Jump if Carry not set
, If the carry flag is a zero, branch to the address indicated; otherwise proceed
with the next instruction. The branch destination is computed by adding the
signed relative-displacement in the second instruction byte to the PC, after incrementing the 'PC twice to point to the next instruction. Tlie carry flag is not
modified.
The carry flag is set. The instruction sequence,
JNC
CPL
JNC

LABELl
C
LABEL2

will clear the carry and cause program execution to continue at the instruction
identified by the label LABEL2.

8-,31

MCS®·S1 INSTRUCTION SET

Bytes:
Cycles:
Encoding:
Operation:

2
2

[]

I addr15 - addrsl I addr7 - addrO I

addf15-0

8-34

Mcse-51 INSTRUCTION SET

MOV

Function:
Description:

Example:

Move byte variable
The byte variable indicated by the second operand is copied into the location
specified by the first operand. The source byte is not affected. No other register
or flag is affected.
This is by far tHe most flexible operation. Fifteen combinations of source and
destination addressing rpodes are allowed.
Internal RAM location 30H holds 4OH. The value of RAM location. 40H is
lOR. The data present at input port 1 is ll00IOIOB (OCAH).
MOV
MOV
MOV·
MOV
MOV
MOV

RO,#30H
A,@RO
Rl,A
R,@Rl
@Rl,Pl
,P2, PI

;RO<= 30H
;A <. = 40H
;Rl < = 40H
;B < = IOH
;RAM (40H) < = OCAH
;P2 #OCAH

leaves the value 30H in register 0, 40H in both the accumulator and register 1,
lOH in register B, and OCAH (1IOO1010B) both in RAM location 40H and out·
put on port 2.

MOV

A,Rn
Bytes:
Cycles:

1
1

Encoding:

Operation:

MOV
(A)_(Rn)

011

*MOV A,dlrect
Bytes:
2
Cycles:
1
Encoding:

Operation:

MOV
(A)- (direct) .

01 0

Idirect address I

*II/IOV A,ACC Is not a valid Instruction.

8-35

MCS~-51INSTRUCTION

MOV

SEr

A,@Ri
Bytes:
Cycles:

Encoding:
Operation:

01 0

MOV

(A)_ «Ri»
MOV

A,#data
Bytes:
2
Cycles:

Encoding:
Operation:

110

oj] Iimmediate data I

MOV

(A)-#data
MOV

Rn,A
Bytes:
Cycles:

Encoding:
Operation:

1
1
11

r r r

011

r r r

Idirect addr. I

r r r

Iimmediate data I

MOV

(Rn)_(A)
MOV

Rn,direct
Bytes:
2
Cycles:
2

Encoding:
Operation:

11 0
MOV

(Rn)_(direct)
MOV, Rn,#data
Bytes:
2
Cycles:
Encoding:
Operation:

111

MOV

(Rn)_#data

8-36

MCS@·51INSTRUCTION SET

MOV

dlrect,A
Bytes:
2
1
Cycles:

Encoding:

Operation:

MOV
(direct)_ (A)

MOV

1 0

Operation:

MOV
(direct)-(Rn)

0 0 01 1 r

Operation:

MOV
(direct) -

0 01 0

I I direct address I

1 0

I dir. addr. (src)

I Idir. addr. (dest)I

(direct)

direct,@Ri
Bytes:
2
Cycles:
2

Encoding:

Operation:

MOV
(direct) -«Ri»

MOV

r r

dlrect,dlrect
Bytes:
3
Cycles:
2

Encoding:

MOV

I direct address I

dlrect,Rn
Bytes:
2
Cycles:
2

Encoding:

MOV

1 0

0 01 0

1 i ,

Idirect addr.'

direct,#data
Bytes:
3
Cycles:
2

Encoding:

Operation:

MOV
(direct)_#data

1 10

1 0

I Idirect address I Iimmediate data I

8-37

MCSI8l-S1 INSTRUCTION SET

MOV

@Ri,A
Bytes:
Cycles:

Encoding:

1 1 0 1 1 i
1

Operation:

MOV
«Ri»_(A) ,
MOV @Ri,direct
Bytes:
2
Cycles:
2
Encoding:
. Operation:
MOV

01 0 1 1 i

1 immediate

direct addr ·1

MOV
«Ri»_(direct)

@Ri,#data
Bytes:
2
Cycles:

Encoding:
Operation:

MOV

11 0

0 1. 1 1 1 0 1 1 i

MOV
«RI» _

data

#data

Function:
Description:

Example:

Move bit data
The Boolean variable indicated by the second operand is copied into the location specified by the first operand. One of the operands must be the carry flag;
the other may be any directly addressable bit. No other register or flag is affected.
The carry flag is originally set. The data present at input port 3 is llOOO101B.
The data previously written to output port 1 is 35H (OOl10101B).
MOV P1.3,C
MOV C,P3.3
MOV P1.2,C
will leave the carry cleared and change port 1 to 39H (OOll1001B).

8-381

MC$@·51INSTRUCT,ON SeT

MOV

C,blt
Bytes:
Cycles:

2
1

Encoding:

Operation:

MOY
(C)-(bit)

MOV

bit,C
Bytes:
Cycles:

01 0 0

I· bit address

1 01

I bit ~ddress I

2
2

Encoding:

Operation:

MOY
(bit)-(C)

MOV

1 01

0 0

1 10 0

DPTR,#data16

Function:.
Description:

Example:

Load Data Pointer with a 16-bit constant
The data pointer is loaded with the 16-bit constant indicated. The 16-bit constant is loaded into the second and third bytes of the instruction. The second
byte (DPH) is the high~order byte, while the third byte (DPL) holds the loworder byte. No flags are affected.
This is the only instruction which moves 16 bits of data at once.
The instruction,
MOY

Bytes:
Cycles:
Encoding:
Operation:

DPTR,#1234H

will load the value 1234H into the data pointer: DPH will hold 12H and DPL
will hold 34H.
3

0 0

1 0 0 0 0

I Iimmed. data15 • 81 Iimmed. data7 - 0 I

MOY
(DPTR)_ #dataI5-0
DPH 0 DPL-.-.-.#dataI5_8 0 #data7_0

8-39

MOS®·S1INSTRUCTIONse:r.

MOVC

A,@A+

Function:
Description:

Example:

Move Code byte
The MOVC instructions load the accumulator with a code byte, or constant
from program memory. The address of the byte fetched is the sum of the
original unsigned eight-bit accumulator contents and the contents of a sixteenbit base register, which may be either the data pointer or th~ PC. In the latter
case, the PC is incremented to tlie address of the following instruction before
being added with the accumulator: otherwise the base register is not altered.
Sixteen-bit addition is performed so a carry-out from the low-order eight bits
may propagate through higher-order bits. No flags are affected. .
A value between 0 and 3 is in the accumulator. The following instructions will
translate the value in the accumulator to one of four values defined by the DB
(define byte) directive.
REL_PC:

INC
A
A,@A+PC
MOVC
RET
DB
66H
77H
DB
88H
DB
99H
DB
, If the subroutine is called with the accumulator equal to 01 H, 'it will return with
77H in the accumulator. The INC A-before the MOVC instruction is needed to
"get around" the RET instruction above the table. If several bytes of code
separated the MOVC from the table; the corresponding number would be added to the accumulator instead.
MOVC A,@A+ DPTR
Bytes:
1
Cycles:
2
Encoding:
Operation:

MOVC
(A)-«A) + (DPTR»

8-40

MCS®·51 INSTRUCTION SET

MOVC

A,@A + PC
1

Bytes:
Cycles:

Encoding:

11000100111

Operation:

Move
(PC)-(PC) + 1
(A)- «A) + (PC»

MOVX

(dest·byte>,

Function:
Description:

Move External
The MOVX instructions transfer data between the accumulator and a byte of
external data memory, hence the "X" appended to MOV. There are two types of
instructions, differing in whether they provide an eight-bit or sixteen-bit indirect address to the external data RAM.
In the first type, the contents of RO or RI in the current register bank provide an
eight-bit address multiplexed with data on PO. Eight bits are sufficient for external I/O expansion decoding Of a relatively small RAM array. For somewhat
larger arrays, any output port pins can be used to output higher-order address
bits. These pins would be controlled by an output instruction preceding the
MOVX.
In the second type of MOVX instruction, the data pointer generates a sixteenbit address. P2 outputs the high-order eight address bits (the contents of DPH)
while PO multiplexes the low-order eight bits (DPL) with data. The P2 Special
Function Register retains its previous contents while the P2 'output buffers are
emitting the contents of DPH. This form is faster and more efficient when accessing very large data arrays (up to 64K bytes), since no additional instructions
are needed to set up the output ports.
It is possible in some situations to mix the two MOVX types. A large RAM ar-

ray with its high-order address lines driven by P2 can be addressed via the data
pointer, or with code to output high-order address bits to P2 followed by a
MOVX instruction using RO or RI.

8-41

MCS®·51 INSTRUCTION SET

Example:

An external 256 byte RAM using multiplexed address/data lines (e.g., an Inte1®
8155 RAM/I/O/Timer) is connected to the 8051 Port O. Port 3 provides control
lines for the external RAM. Ports 1 and 2 are used for normal I/O. Registers 0
and 1 contain 12H and 34H. Location 34H of the external RAM holds the value
56H. The instruction sequence,
MOVX
MOVX

A,@Rl
@RO,A

copies the value 56H into both the accumulator and external RAM location
12H.

MOVX A,@Ri
Bytes:
2
Cycles:
Encoding:

Operation:

MOVX
(A)_«Ri»

1 1 01 0 0 1

MOVX A,@DPTR
Bytes:
1
Cycles:
2
Encoding:

Operation:

MOVX
(A)_«DPTR»

1 1 01 0 0 0 01

MOVX @Ri,A
Bytes:
1
Cycles:
2

Encoding:

Operation: .

MOVX·
«Ri»- (A)

1 0 0

MOVX @DPTR,A
Bytes:
1
Cycles:
2
Encoding:

Operation:

MOVX
(DPTR)_(A)

1 1 0 0 0 01

8-42

MCS@·51 INSTRUCTION SET

MUL

Function:
Description:

Example:

Multiply
MUL AB multiplies the unsigned eight-bit integers in the accumulator and
register B. The low-order byte of the sixteen-bit product is left in the accumulator, and the high-order byte in B. If the product is greater than 255
(OFFH) the overflow flag is set; otherwise it is cleared. The carry flag is always
cleared.
Originally the accumulator holds the value 80 (50H). Register B holds the value
160 (OAOH). The instruction,
MUL

will give the product 12,800 (3200H), so B is changed to 32H (OOII00IOB) and
the accumulator is cleared. The overflow flag is set, carry is cleared.

Bytes:
Cycles:

I
4

01 0

Encoding:
Operation:

0 01

MUL
(A)7-0-(A) X (8)

(B)15-8

8-43

MC$@:-51INSt:RUCTION SE;T

NOP
Function:
Description:
Example:

No Operation
Execution continues at the following instruction. Other than the PC, no
registers or flags .are affected.
It is desired to produce a low-going output pulse on bit 7 of port 2 lasting exactly 5 cycles. A simple SETB/CLR sequence would generate a one-cycle pulse, so
four additional cycles must be inserted. This may be done (assuming no interrupts are enabled) with the instruction sequence,
CLR
NOP
NOP
NOP
NOP
SETB

P2.7

Bytes:
Cycles:
Encoding:
Operation:

10 0 0 010 0 0 01
NOP
(PC)- (PC)

8-44

MCS®-51 INSTRUCTION SET

ORL

(src·byte>

Function:
Description:

Logical-OR for byte variables
ORL performs the bitwise logical-OR operation between the indicated
variables, storing the results in the destination byte. No flags are affected.
The two operands allow six addressing mode combinations. When: thedestination is the accumulator, the source can use register, direct, register-indirect, or
immediate addressing; when the destination is a direct address, the source can
be the accumulator or immediate data.
-

Example:

Function:
Description

Example:

Logical-OR for bit variables
Set the carry flag if the Boolean value is a logical I; leave the carry in its current
state otherwise. A slash ("I") preceding the operand in the assembly language
indicates that the logical complement of the addressed bit is·used as the 1J0urce
value, but the source bit itself is not affected. No other flags are affected.
Set the carry flag if and only if Pl.O :; 1, ACC.7 = 1, or OV = 0:
MOV C,Pl.O
ORL C,ACC.7
ORL C,IOV

ORL

C,bit
Bytes:
Cycles:

Encoding:
Operation:

;LOAD CARRY WITH INPUT PIN PlO
;OR CARRY WITH THE ACC. BIT 7
:OR CARRY WITH THE INVERSE OF OV

2
2

1 I0

01 I bit address I

ORL
(C)-(C) v (bit)

ORL

C,/bit
Bytes:
Cycles:

Encoding:
Operation:

2
2

11 0

01 0 0 0 01 I bit address 1

ORL
(C)- (C) v (bit)

POP.

direct

Function:
Description:

Pop from stack.
.
.
The contents of the internal RAM location addressed by the stack pointer is
read, and the stack pointer is decremented by one. The value read is the transfer
to the directly addressed byte indicated. No flags are affected.

8-47

MCS®-51 INSTRUCTION SET

Example:

The stack pointer originally contains the value 32H, and internal RAM locations 30H through 32H contain the values 20H, 23H, and OlH, respectively.
The instruction sequence,
POP
POP

DPH
DPL

will leave the stack pointer equal to the value 30H and the data pointer set to
0123H. At this point the instruction,
POP

will leave the stack pointer set to 20H. Note that in this special case the stack
pointer was decremented to 2FH. before being loaded with the value popped
(20H).

Bytes:
Cycles:

2
2

Encoding:
Operation:

PUSH

1 0 O· 0 0

I Idirect address

POP
(direct) ____ «SP»
(SP)_(SP) - 1

direct

Function:
Description:

Example:

Push onto stack
The stack pointer is incremented by one. The contents of the indicated variable
is then copied into the internal RAM location addressed by the stack pointer.
Otherwise no flags are affected.
On entering an interrupt routine the stack pointer contains 09H. The data
pointer holds the value 0123H. The instruction sequence,
PUSH
PUSH

DPL
DPH

will leave the stack pointer set to OBH and store 23Hand OlH in internal RAM
locations OAH apd OBH, respectively.

Bytes:
Cycles:

Encoding:

Operation:

PUSH
(SP)-(SP) +
«SP»_ (direct)

0 0 0 0 0

I Idirect address I

8.. 48

MCS®·S1 INSTRUCTION SET

RET

Function:
Description:

Example:

Return from subroutine,
RET pops the high- and low-order bytes of the PC successively from the stack,
decrementing the stack pointer by two. Program execution continues at the
resulting address, generally the instruction immediately following an ACALL
or LCALL. No flags are affected.
The stack pointer originally contains the value OBH. Internal RAM locations
OAH and OBH contain the values 23H and OlH, respectively. The insttuction,

RET
will leave the stack pointer equal to the value 09H. Program execution will continue at location 0123H.

Bytes:
Cycles:

Encoding:

10 0

Operation:

RET
(PC 15-8)- «SP»
(SP)-(SP) - 1
(PC7-0)_«SP» ,
(SP) __ (SP) - 1

010 0 1 0

RETI

Function:
Description:

Return from interrupt
RETI pops the high- and low-order bytes of the PC successively from the stack,
and restores the interrupt logic to accept additional interrupts at the same
priority level as the one just processed. The stack pointer is left decremented by
two. No other registers are affected; the PSW is not automatically restored to
its pre-interrupt status. Program execution continues at the resuIting address,
which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower- or same-level interrupt had been pending
when the RETI instruction is executed, that one instruction will be executed
before the pending interrupt is processed.

8-49

MCS®·5.1INSTRUCTION SeT

Example:

The stack pointer originally contains the value OBH. An interrupt was detected
during the instruction ending at location 0122H. Internal RAM locations OAH
and OBH contain the values 23H and OlH, respectively. The instruction,
RET!

will leave the stack pointer equal to 09H and return program execution to location 0123H.

Bytes:
Cycles:
Encoding:
Operation:

1
2

10 0
RET!

(PC 15.8)- «SP»
(SP)- (SP) - 1
(PC7-0) _«SP»
(SP)- (SP) - 1

8-50

· MCS®-S1 INSTRUCTION SET

Function:
Description:
Example:

Rotate accumulator Left
The eight bits in the accumulator are rotated one bit to the left. Bit 7is rotated
into the bit 0 position. No flags are affected.
The accumulator holds the value OC5H (1IoooI01B). The instruction,
RL

leaves the accumulator holding the value 8BH (IOOOI011B) with the carry unaffected.
Bytes:
Cycles:

1
1

Encoding:

100101001

Operation:

RL
(An + })_ (An)
(AO)-(A7)

RLC

n=0-6

Function:
Description:

Example:

Rotate accumulator Left through the Carry flag
The eight bits in the accumulator and the carry flag are together rotated one bit .
to the left. Bit 7 moves into the carry flag; the original state of the carry flag
moves into the bit 0 position. No other flags are affected.
The accumulator holds the value OC5H (11000101 B),and the carry is zero. The
instruction,
RLC

leaves the accumulator holding the value 8BH (loooI0IOB) with the carry set.
Bytes:
Cycles:

1
1

Encoding:

10 0

Opera'tion:

RLC
(An + 1 ) - (An)
(AO)--(C)
(C)--(A7)

11001

n=0-6

8-51

MCS®-S1 INSTRUCTION SeT

Function:
Description:
Example:

Rotate accumulator Right
The eight bits iri'the accumulator are rotated one bit to the right. Bit 0 is rotated
into the bit 7 position. No flags are affected.
The accumulator holds the value OC5H (llOOOlOlB). The instruction,
RR

leaves the accumulator holding the value OE2H (lll000lOB) with the carry
unaffected.

Bytes:
Cycles:

1
1

Encoding:

10 0 0 010 0 1 1

Operation:

RR
(An)_ (An + t)
(A7)_(AO)

RRC

n=O-6

Function:
Description:

Example:

Rotate accumulator Right through Carry flag
The eight bits in the accumulator and the carry flag are together rotated one bit .
to the right. Bit 0 moves into the carry flag; the original value of the carry flag
moves into the bit 7 position: No other flags are affected.
The accumulator holds the value OC5H (1100010lB), the carry is zero. The instruction,
RRC

leaves the accumulator holding the value 62 (0110001OB) with the carry set.

Bytes:
Cycles:

1
1

Encoding:

10001100111

Operation:

RRC
(An)_ (An + 1)
(A7)_(C)
(C)_(AO)

n=0-6

8-52

MCS®-S1 INSTRUCTION SET

SETB

Function:
Description:
Example:

Set Bit
SETB sets the indicated bit to one. SETB can operate on the carry flag or any
directly addressable bit. No other flags are affected.
The carry flag is cleared. Output port 1 has been written with the value 34H
(00110100B). The instructions,
SETB
SETB.

.C
Pl.O

will leave the carry flag set to 1 and change the data output on port 1 to 35H
(00110101 B).
C
Bytes:
Cycles:

SETB

Encoding:

Operation:

SETB
(C)--1

bit
Bytes:
Cycles:

1 0 0
1

1 11

1 0 0
1

1 01

SETB

Encoding:
Operation:

Ibit address I

SETB
(bit)~1

SJMP

rei

Function:
Description~

Short Jump
Program control branches unconditionally to the address indicated. The branch
destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range
of destinations allowed is from 128 bytes preceding this instruction to 127 bytes
following it.

8-53

MCS®'·51 INSTRUC:rIONSET

Example:

The label "RELADR" is assigned to an instruction at program memory location
0123H. The instruction,
SJMP

RELADR

will assemble into location OlOOH. After the instruction is executed, the PC will
contain the value 0123H.

(Note: Under the above conditions the instruction following SJMP will be at
102H. Therefore, the displacement byte of the instruction will be the relative
offset (0123H-0102H) = 21H. Put another way, an SJMP with a displacement
of OFEH would be a one-instruction infinite loop.)
Bytes:
Cycles:

2
2

Encoding:

Operation:

SJMP
(PC)- (PC) + 2
(PC) - - (PC) + rei

0 0 0 0 0

y-DJ I reI. address I

8-54

MCS®·51 INSTRUCTION SET

SUBB

A, (src·byte>

Function:
Description:

Subtract with borrow
SUBB subtracts the indicated variable and the carry flag together from the accumulator, leaving the result in the accumulator. SUBB sets the carry (borrow)
flag if a borrow is needed for bit 7, and clears C otherwise. (If C was set be/ore
executing a SUBB instruction, this indicates that a borrow was needed for the
previous step in a multiple precision subtraction, so the carry is subtracted from
the accumulator along with the source operand.) AC is set if a borrow is needed
for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6, but
not into bit 7, or into bit 7, but not bit 6.
When subtracting signed integers OV indicates a negative number produced
when a negative value is subtracted from a positive value, or a positive result
when a positive number is subtracted from a negative number.

Example:

The source operand allows four addressing modes: register, direct, registerindirect, or immediate.
'
The accumulator holds OC9H (11001001B), register 2 holds 54H (01010100B),
and the carry flag is set. The instruction,
SUBB

A,R2

will leave the value 74H (01110100B) in the accumulator, with the carry flag and
AC cleared but OV set.
Notice that OC9H minus 54H is 75H. The difference between this and the above
result is due to the carry (borrow) flag being set before the operation. If the
state of the carry is not known before starting a single or multiple-precision subtraction, it should be explicitly deared by a CLR C instruction.

SUBB

A,Rn
Bytes:
Cycles:

Encoding:
Operation:

1 r

SUBB
(A)_ (A) - (C) - (Rn)

8-55

MCS@)-51INSTRUCTION SET

SUBB

A,direct
Bytes:
2
Cycles:

° 0 1, I° 1

0 1

I Idire~t address I

Encoding:

Operation:

SUBB
(A)-- (A) - (C) - (direct)

SUBB

A,@RI
Bytes:
Oycles:

Encoding:

1100

tlo

1 1

Operation:

SUBB
(A).-.- (A.) - (C) - «Ri»
SUBB A,#data'
Bytes:
2
'Cycles:
1

° ° 1 I°'1

°I Iimmediate data I

Encoding:

Operation:

SUBB
(A)--:'-(A) - (C) - #data

SWAP

Function:
Description:

Example:

Swap nibbles within the Accumulator,
SWAP A interchanges the low- and high.order nibbles (four-bit fields) of the
acc~mulator (bits 3-0 and bits 7-4). The operation can also be thought of as a
four-bit rotate instruction. No flags are affected.
The accumulator holds the value OCSH (11000101B). The instruction,
SWAP

leaves the accumulator holding the value 5CH (01011100B).
Bytes:
Cycles:
Encoding:
Operation:

1
L

1L.. ,. 1____
0 _0-,1,-0_,_1_0_0--,1
SWAP
(A3-0)~(A7.4),

(A7-4)_(A3-0)

8-&6

MCS®-S1 INSTRUCTlo.N SET

XCH

Function:
Description:

Example:

Exchange Accumulator with byte variable
XCH loads the accumulator with the contents of the indicated variable, at the
same time writing the original accumulator contents to the indicated variable.
The source/destination operand can use register, direct, or register-indirect addressing.
RO contains the address 20H. The accumulator holds the value 3FH
(001111118). Internal RAM location 20H holds the 'value 75H (01110101B).
The instruction,
A,@RO

XCH

will leave RAM location 20H holding the values 3FH (001111118) and 75H
(011101018) in the accumulator.
XCH

A,Rn
Bytes:
Cycles:

Encoding:
o.peration:

OOl l r r r l
XCH
(A)~(Rn)

XCH

A,direct
Bytes:
2
Cycles:

Encoding:
Operation:

0I0

11 I direct address I

XCH
(A)~(direct)

XCH

A,@Ri
Bytes:
Cycles:

Encoding:
Operation:

0 10

XCH
(A)~«Ri»

8-57

MCS®-51 INSTRUCTION SET

XCHD

A,@Ri

Function:
Description:

Example:

Exchange Digit
XCHD exchanges the low-order nibble of the accumulator (bits 3-0), generally
representing a hexadecimal or BCD digit), with that of the internal RAM loca~
tion indirectly addressed by the specified register. The high-order nibbles (bits
7-4) of each register are not affected. No flags are affected.
. RO contains the address 20H. The accumulator holds the value 36H
(001101 lOB). Internal RAM location 20H holds the value 75H (01110101B).
The instruction,
XCHD

A,@RO

will leave RAM location 20H holding the value 76H (OlllOllOB) and 35H
(001 10101 B) in the accumulator.
Bytes:
Cycles:

Encoding:

Operation:

XCHD

101 1 0

(A3-0)~«Ri3-0»

8-58

MCS@-S1INSTRUCTION SET

XRL

, (src-byte>

Functi(»n:
Description:

Logical Exclusive·OR for byte variables
XRL performs the bitwise logical Exclusive-OR operation between the indicated variablj::s, storing the results in the destination. No flags are affected.
The two operands allow six addressing mode combinations; When the destination is theaccumuJator, the source can use register, direct, register·indirect, Of
immediate addressing; when the destination is a direct address, the source can
be the accumulator or immediate data.

Example:

(Note: When this instruction is used to· modify an output port, the value used as
the original port' data will be read from the output data latch, not the input
pins.)
If the accumulator holds OC3H (llOOOOllB) and register 0 holds OAAH
(1OIOIOIOB) 'then the instruction,
XRL

A,RO

will leave the accumulator holding the value 69H (OllOIOOIB).
When the destination is a directly addressed byte, this instruction can complement combinations of bits in any RAM location or hardware register. The pattern of bits to be complemented is then d'etermined by a mask byte, either a constant contained in the instruction or a variable computed in the accumulator at
run-time. The instruction,
XRL

PI,#OOllOOOIB

. will complement bits 5, 4, and 0 of output port l.

XRL

A,Rn
Bytes:
Cycles:

Encoding:
Opera~ion:

A,direct
Bytes:
Cycles:
I

Encoding:
Operation:

r r r

XRL
(A)_ (A)

XRL

011
"t

(Rn)

2
1

1'-____
0
0. 1_0
. . __ ~
XRL
(A)_(A)

Idirect address I

(direct)

8·59

XRL

A,@RI
Bytes:
Cycles:

.,
1
1

",'

Encoding:

Operation:

XRL

1 -I

,°1- 0 1

(A)-(A) 'V

XRL

A,#data
Bytes:
Cycles:

Encoding:
Operation:

I, ':

1' i

«It»

'\!

:';-;'

01 0 1 ° 01

1'immediate

data

XRL
(A)_(A) 'V #data

XRL

direct,A
Bytes:
Cycles:

2
1

Encoding:

Operation:

XRL

1 1

01 0 °

(direct)_ (direct)
XRL dlrect,#data
Bytes:
3
Cycles:
2

Encoding:
Operation:

direct address 1

(A)

0____0-'1_0_0___1.. .,1

1direct address I

1. . .

XRL
(direct)_ (direct)

'tf

#data

8-60

1 immediate

data

MCS®~51

Data Sheets

MCS®-S1
a-BIT CONTROL-ORIENTED MICROCOMPUTERS
S031/S051
S031 AH/S051 AH
S032AH/S052AH
S751H/S751H-12
•
•
•
•
•

•
•
•
•
•

High Performance HMOS Process
Internal Timers/Event Counters
2-level Interrupt Priority Structure
32 I/O lines (Four S-Bit Ports)
64K Program Memory Space

Boolean Processor
Bit-Addressable RAM
Programmable Full Duplex Serial Channel
111 Instructions (64 Single-Cycle)
64K Data Memory Space

• Security Feature Protects EPROM Parts Against Software Piracy
The MCS®-51 products are optimized for control applications. Byte-processing and numerical operations on
small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The
instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide in
structions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct
bit manipulation and testing in control and logic systems that require Boolean processing.

Internal Memory
Device

Program

Data

8052AH
8051AH
8051
8032AH
8031AH
8031
8751H
8751H-12

8K x 8 ROM
4K x 8 ROM
4K x 8 ROM
none
none
none
4K x 8 EPROM
4K x 8 EPROM

256 x 8 RAM
128 x 8 RAM
128 x 8 RAM
256 x 8 RAM
128 x 8 RAM
128x8RAM
128 x 8 RAM
128 x 8 RAM

Timersl
Event Counters
3
2
2
3
2
2
2
2

x
x
x
x
x
x
x
x

16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit

Interrupts

6
5
5
6
5
5
5'
5

The 8751 H is an EPROM version of the 8051 AH; that is, the on-Chip Program Memory can be electrically
programmed, and can be erased by exposure to ultraviolet light. It is fully compatible with its predecessor, the
8751-8, but incorporates two new features: a Program Memory Security bit that can be used to protect the
EPROM against unauthorized read-Qut, and a programmable baud rate modification bit (SMOD). SMOD is not
.
.
present in the 8751 H-12.

9-1

803118051 • 8031 AH/8051 AH
8032AH/8052AH • 8751 H/8751 H·12

......,
Vcc

------'-----;.tl~~:;_ '~Wti-----------'--l

Figure 1. MCS®-51 Block Diagram

PIN DESCRIPTIONS
VCC

VSS

Port 0 also receives the code bytes during programmirig of the EPROM parts, and outputs the code bytes
during program verification of the ROM and EPROM
parts. External pullups. are required during program
verification.

Circuit ground.

Port 1

PortO

Port 1 is an a-bit bidirectional lID port with Internal
pullups. The Port 1 output buffers can sink/source 4
LS TTL inputs. Port 1 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low will source
current (ilL, on the data sheet) because of the internal
pullups.

Supply voltage.

Port 0 is an a-bit open drain bidirectional lID port. As
an output port each pin can sink a LS TTL inputs.
Port 0 pins that have 1s written to them float, and in
that state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting 1s, and can source and
sink a LS TTL inputs.

Port 1 also receives the low-order address bytes during programming of the EPROM parts and during
program verification of the ROM and EPROM parts.
9-2

803118051 • 8031AHI8OS1AH
8032AH/80S2AH • 8751H/8761H·12

=:... . . . .~~,~,,...,.=~,..~'~"":["'oA-i.fi.~~i..,..,.i,.....,lli~i!;,...........

r-[-{

vee
T2I!X 1'1.1
1'1.2
1'1.3
P1A

1'1.&
P1.s
1'1.7
R8T
RXDP3.0
lXD 1'3.1
IIi'I'ti P3.2

iR'fi Pu

topu

PO.OADO
PO.l AlII
1'0.2 AlIa
PO.3 AlIa
POAAD4
PO.I ADs
PO.lADe
PO.7,ArR

UMIo
ALIi/IIIfilII

_,.

.PU

PtAA12
PUAl1

XTAL2
XTALI
VS8

r:!-:

POS

111.7

:€]

~~:

flOl

...,

~!]

[~:

".7

• PU

JiJ

r--

I'l

Ne J~]

~~:

]!:]

[~:

ALE

d'_

PI.2 :1!:]

pUAU
1'2.5 A13

W!lpu

r:!t:

):]

Pl1

IIftii

T1PU

L·J. LSJ L~ LJJ LiJ L'J ~J ~ ~ ~~ ~

P1"

p,. :( )

-12-1'1'0- _ONLY

f~: mR

:,~]

r!~

Pl7

1!]

{:!f

1'21

P2.2Al0

1'2.1 Q
P2,oQ

Pad

Figure 2.

MCS~-51

In the 8032AH and 8052AH, Port 1 pins P1.0 and
P1.1 also serve the T2 and T2EX functions, respectively.

Port 2
/ Port 2 is an 8-bit bidirectional I/O port with internal
pullups. The Port 2 output buffers can sink/sOurce 4
LS TTL inputs. Port 2 pins that have 1s written to
them are pulled high by the Intemal pullups, and In
that state can be used as inputs. As inputs, Port 2
pins that are externally being' pulled low will source
current (ilL, on the data sheet) because of the internal
pullups.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOV>< @DPTR). In this application it
uses strong internal pullups when emitting 1s. During
'accesses to external Data Memory that use a·bit addresses (MOVX @Ri), Port 2 emits the contents of
the P2 SpeciEiI Function Register.
Port 2 also receives the high-order address bits during programming of the EPROM parts and during

program verification of the ROM and EPROM parts.

Pin Connections

Port 3
Port 3 is an 8-bit bidirectional I/O port with internal
pullups. The Port 3 output buffers can sink/source 4
LS TTL inputs. Port 3 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source
current (ilL, on the data sheet) because of the pullups.
Port :3 also serves the functions of various special
features of the MeS-51 Family, as listed below:

Port Pin
P3.0

P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

Alternative Function
RXO (serial input p()rt)
TXD {Serial output port)
1m'O (external interrupt 0)
jJij'ff (external interrupt 1)
TO, (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write
strobe)
Jm (external data memory read
strobe) .

.8031/S051 • S031AH/S051AH
S0324H/S052AH • 8751·H/S751H-12

RST

Note, hOwever, that if the Security Bit in the EPROM
devices is programmed, the device will not fetch code
from any location in external Program Memory.

Reset input. A high on this pin for two machine cycles
while the oscillator is running resets the device.

This pin also receives the 21 V programming supply
voltage (VPP) durir;lg programming of the EPROM
parts.

ALE/PROG
Address Latch Enable output pulse for latching the
low byte of the address during accesses to external
memory. ALE can drive 8 LS TTL il utS. This pin is
also the program pulse input (PR G) during programming of the EPROM parts'.

XTAL1

Input to the inverting oscillator amplifier.

XTAL2
In normal operation ALE is emitted at a constant rate
of '/6 the oscillator frequency, and may be used for
external timing or clocking purposes. Note, however,
that one ALE pulse is skipped during each access to
external Data Memory.

Output from the inverting oscillator amplifier.

OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in
Application Note AP-155, "Oscillators for Microcontrollers."

Program Store Enable is the read strobe to external
Program Memory. PSEN can drive 8 LS TTL inputs.
When the device is executing code from external Program Memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped
during each access to external Data Memory.

To drive the device from an external clock source,
XTAL 1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low timesspecified on the Data Sheet must
be observed.

EANPP
External Access enable EA must be externally held
low in order to enable any MCS-51 device to fetch
code from external Program Memory locations 0 to
OFFFH (0 to 1 FFFH, in the 8032AH and 8052AH).

C2
,......--tl~-+---t

XTAL2

EXTERNAL
OSCILLATOR - - - - t XTAL2
SIGNAL

o
t---tl~--e---t

XTALl

t----~---tvss

....- - t vss
Cl, C2 = 30 pF ",10 pF FOR CRYSTALS
= 40 pF "'10.pF FOR CERAMIC RESONATORS

Figure 3,. Oscillator Connections

Figure 4. External Drive Configuration

9-4

8031/8051 e8031 AH/8051 AH
8032AH/8052AH e 8751H/8751H-12

inter

ABSOLUTE MAXIMUM RATINGS·

-NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Ambient Temperature Under Bias ... O·C to 70·C
Storage Temperature . , ... -65·C to + 150·C
Voltage on EANPP Pin to VSS . - 0.5V to + 21.5V
Voltage on Any Other Pin to VSS. - 0.5V to + 7V
Power Dissipation . . . . . . . . . . . . . . . . 1 .5W

D.C. CHARACTERISTICS: (TA = O·C to 70°C; VCC = 5V ± 10%; VSS = OV)
Symbol

Min

Max

Unit

-0.5

0.8

0.7

Input High Voltage (Except XTAL2,
RST)

2.0

VCC+0.5

2.5

VCC+0.5

XTAL1

0.45

IOL

1.6 mA

0.60
0.45

V
V

IOL
IOL

3.2 mA
2.4 mA

0.45

=
=
=

Parameter

VIL

Input· Low Voltage (Except EA Pin of
8751H,8751H-12)

V/.L1

Input Low Voltage to EA Pin of
8751 H, 8751 H-12

VIH
VIH1

Input High Voltage to XTAL2, RST

VOL

Output Low Voltage (Ports 1, 2, ~)*

VOL1

Output Low Voltage (Port 0, ALE,
PSEN)8751H,8751H-12

Test Conditions

VSS

IOL

VOH

Output High Voltage (Ports 1, 2, 3)

2.4

IOH = -80/LA

VOH1

Output High Voltage (Port 0 in
External Bus Mode, ALE, PSEN)

2.4

IOH

ilL

Logical 0 Input Current (Ports 1, 2, 3)
8032AH, 8052AH
All Others

All Others

3.2 mA

= -

400 /LA

-800
-500

!LA

Logical 0 Input Current to EA Pin of
8751H, 8751H-12 Only

-15

1IL2

Logical 0 Input Current (XTAL2)

-3.2

Vin = 0.45 V

III

Input Leakage Current (Port 0)
. 8751H, 8751H-12
All Others

±100
±10

/LA

!LA

0.45 < Vin < VCC
0.45 < Vin < VCC

/LA

1IL1

/LA

Vin = 0.45 V
Vin = 0.45 V

IIH

Logical 1 Input Current to EA Pin of
8751H,8751H-12

500

IIH1

Input Current to RST to Activate Reset

500

!LA

Vln < (VCC - 1.5V)

ICC

Power Supply Current:
8031/8051
8031 AH/8051 AH
8032AH/8052AH
8751H/8751 H-12

160
125
175
250

mA
mA
mA
mAo

All Outputs Disconnected; EA = VCC

CIO

Pin Capacitance

test freq = 1MHz

-Note: Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of .ALE and
Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make
1-to-0 transitions during bus operations. In the worst cases.(capacitive loading> 100 pF), the noise pulse on the ALE line
may exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a
Schmitt Trigger STROBE input.

9-5

803118051 • 803:1 AHf80S1AH
8002AH/8052AH • 8751Ml8751H-12

inter

A.C. CHARACTERISTICS: (TA = () °C to. +70 °C, VCC = 5V ±100/0; VSS=;i OV,
Load Capacitance for Port 0, ALE, and PSEN = 100 pF,
Load Capacitance for All Other Outputs '" 80 pF)

Symbol
1fTCLCL

Parameter

12MHz Osc
Min
Max

Oscillator Frequency

Variable Oscillator
Min
Max
3.5

12.

Units
MHz

127

2TCLCL-40

Address Valid to ALE Low

TCLCL-40

TLLAX

Address Hold After ALE Low

TCLCL-35

TLLlV

ALE Low to Valid Instr In
8751H,8751H-12
All Others

TLHLL

ALE Pulse Width

TAVLL

TLLPL

ALE Low to PSEN Low

TPLPH

PSEN Pulse Width
8751H,8751H-12
All Others

TPLIV

TPXIX

Input Instr Hold After PSEN
Input Instr Float After PSEN

TPXAV
TAVIV

TPLAZ

183
233

PSEN to Address Valid

4TCLCL-150
. 4TCLCL-100

TCLCL-25

190
215

3TCLCL-60
3TCLCL-35

ns
ns

PSEN Low to Valid Instrln
8751H,8751H-12
All Others

TPXIZ

ns
ns·

100
125
O'

3TCLCL-150
3TCLCL:.-125
0

ns
TCLCL-20

63
TCLCL-8

ns
.ns

ns
ns

Address to Valid Instr In
8751H,8751H-12
All Others

267
302

5TCLCL-150
5TCLCL-115

ns
ns

PSEN Low to Address Float

TBD

TRLRH

RD Pulse Width

400

6TCLCL,100

TWLWH

WR Pulse Width

400

6TCLCL-100

TRLDV

RD Low to Valid Data In

TRHDX

Data Hold After RD

TRHDZ

Data Float After RD

TLLDV
TAVDV
TLLWL

ALE Low to RD or WR Low

200

TAVWL

Address to RD or WR Low

203

TOVWX

Data Valid to WR Transition
8751H,8751H-12
All Others

252
0

5TCLCL-165
0

ns
ns

2TCLCL-70

ALE Low to Valid Data In

517

8TCLCL-150

Address to Valid Data In

585

9TCLCL-165

3TCLCL+50

TOVWH

Data Valid to WR High

TWHOX

Data Held After WR'

TRLAZ

RD .Low to Address Float

TWHLH

RD or WR High to ALE High
8751H,8751H-12
All Others

300

13
23
433

3TCLCL-50
4TCLCL-130

TCLCL-70
TCLCL-60

ns
ns

7T~LCL-150

TCLCL-50

33
TBD
33
43

9-S

133
123

TCLCL-50
TCLCL-40.

ns
TBD'

TCLCL+50
TCLCL+40'"

ns
ns

8031/8051 • 8031AH/8051AH
8032AH/8052AH • 8751H/8751H·12

EXTERNAL PROGRAM MEMORY READ CYCLE

ALE

I-TLLPL
j--TPLPH
TLLIV

....--+-1 TPLIV

·PORTO

14---TAVIV - - - + - I

PORT 2

A8-A15

9-7

803118051 e8031AH/8051AH
8032AH/8052AHe 8751Ht8751H":12

EXTERNAL DATA MEMORY READ CYCLE

I----~ TLHLL

ALE

t-----TLLDV----Pl
_~---TRLRH

-r----t

PORTO

~-----TAVDV-----_+i

PORT 2

P2.0-P2.7 OR A8-A15 FROM DPH

9-8

A8-A15 FROM PCH

inter

8031/8051 .' 8031 AH/8051 AH
8032AH/8052AH • 8751H/8751H-12

EXTERNAL DATA MEMORY WRITE CYCLE

TWHLH

"'-_~TLHLL

ALE

TLLWL--+""----TWLWH - - - - + - I

TOVWX
...~~-~~-i----TOVWH--------~
PORTO

PORT 2

DATA OUT

P2.0-P2.7 OR AB-A15 fRO!/! DPH

9~9

INSTR
IN

AB-A 15 fROM PCH

B031/B051.·., B031AH/8051AH
8032AH/8052AH. 8751 H18751 H-12

inter

SERIAL PORT TIMING - SHIFT REGISTER MODE
Test Cpnditions: T A

O·C to 70 ·C; VCC = 5V ± 10%; VSS

Symbol

Parameter

OV; Load Capacitance

80 pF

12MHz Osc

Variable Oscillator

Min

Max

Units

TXLXL

Serial Port Clock Cycle Time

1.0

12TCLCL

JLS

TQVXH

Output Data Setup to Clock Rising
Edge

700

10TCLCL-133

TXHQX

Output Data Hold After Clock
Rising Edge

2TCLCL-117

TXHDX

Input Data Hold After Clock Rising
Edge

TXHDV

Clock Rising Edge to Input Data
Valid

700

10TCLCL-133

SHIFT REGISTER TIMING WAVEFORMS

INSTRUCTION

ALE

CLOCK

OUT1'lIT OATA

'--t

WRITE 1'0 seUF

".0' I--..j

j 1-".0.

X'-~-..JX'-_-..JX'-_-..JX'-_-.JX'-_-.JI

sun

S£TRi

9-10

8031/8051 • 8031 AH/8051 AH
8032AH/8052AH • 8751H/8751H-12

EXTERNAL CLOCK DRIVE
Symbol

Min

Max

Units

1fTClCl

Oscillator Frequency

Paramet,r

3.5

MHz

TCHCX

High Time

TClCX

low TIme

TClCH

Rise Time

TCHCl

Fall Time

EXTERNAL CLOCK DRIVE WAVEFORMS

TCHCL

t-------TCLCL

A.C. TESTING INPUT, OUTPUT WAVEFORM

24=X ?
2.0

TEST POINTS

0.45

0.8

<.
20

0.8

A C TESTING INPUTS ARE DRIVEN AT 2 4 v FOR A lOGIC 1 ANO 045 V FOR
A. lOGIC' 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND 0 BV FOR A lOGIC O'

9-11

------001

intel·

S031/S051 • S031AH/8051AH
S032AH/S052AH • S751H/S751H~12

EPROM CHARACTERISTICS:
Table 3. EPROM Programming Modes
Mode

RST

PSEN

ALE

P2.7

P2.6

P2.5

P2.4

Program

VPP

Inhibit

Verify

Security Set

VPP

Note: "1" = logic high for that pin
"0" = logic low for that pin
"X" = "don't care"
"VPP" = + 21 V ± 0.5V

'ALE is pulsed low for 50 msec.

Note that the EAlVPP pin must not be allowed to go
above the maximum specified VPP level of 21.5V for
any amount of time. Even a narrow glitch above that
voltage level can cause permanent damage to the
device. The VPP source should be well regulated and
free of glitches.

Programming the EPROM
To be programmed, the part must be running with a
4 to 6 MHz oscillator. (The reason the oscillator needs
to be running is that the internal bus is being used to
transfer address and program data to appropriate internal registers.) The address of an EPROM location
to be programmed is applied to Port 1 and pins
P2.0-P2.3 of Port 2, while the code byte to be programmed into that location is ~d to Port O. The
other Port 2 pins, and RST, PSEN, and EA should
be held at the "Program" levels indicated in Table 3.
ALE is pulsed low for SO msec to program the code
byte into the addressed EPROM location. The setup
is shown in Figure S.

Program Verification
If the Security Bit has not been programmed, the onchip Program Memory can be read out for verification
purposes, if desired, either during or after the programming operation. The address of the Program
Memory location to be read is applied to Port 1 and
pins P2.0-P2.3. The other pins should be held at the
"Verify" levels indicated in Table 3. The contents of
the addressed location will come out on Port O. External pullups are required on Port 0 for this operation.

- Normally EA is held at a !2gic high until just before
ALE is to be pulsed. Then EA is raised to + 21 V, ALE
is pulsed, and then EA is returned to a logic high.
Waveforms and detailed timing specifications are
shown in later sections of this data sheet.

The setup, which is shown in Figure 6, is the same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an activelow read strobe.

+5V

L -....HXTAl1

vss

Figure 6. Program Verification

Figure 5. Programming Configuration
9-12

S031/S051 • S031AH/S051AH
S032AH/S052AH • S751H/S751H·12

inter
EPROM Security

The security feature consists of a "locking" bit which
when programmed denies electrical access by any
external means to the on-chip Program Memory. The
bit is programmed as shown in Figure 7. The setup
and procedure are the same as for normal EPROM
programming, except that P2.6 is held at a logic high.
Port 0, Port 1, and pins P2.0~P2.3 may be in any
state. The other pins should be held at the "Security"
levels indicated in Table 3.

+5V

x = ··DON·T CARE··

P20P2.3

8751H

P24

ALEIPROG

P2.5
P26

Once the Security Bit has been programmed, it can
be cleared only by full erasure of the Program Memory. While it is programmed, the internal Program
Memory can not be' read out, the device can not be
further programmed, and it can not execute out of
external program memory. Erasing the EPROM,
thus clearing the Security Bit, restores the device's
full functionality. It can then be reprogrammed.

P2.7

E4'VPP

XTAL2

VIH1
XTALl
VSS

Erasure Characteristics

Figure 7. Programming the Security Bit

Erasure of the EPROM begins to occur when the chip
. is exposed to light with wavelengths shorter than approximately 4,000 Angstroms. Since sunlight and
flourescent lighting have wavelengths in this range,
exposure to these light sources over an extended
time (about 1 week in sunlight, or 3 years in roomlevel flourescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an .opaque label
be placed over the window.

The recommended erasure procedure is exposure to
ultraviolet light (at 2537 Angstroms) to an integrated
dose of at least 15 W-sec/cm 2 . Exposing the EPROM
to an ultraviolet lamp of 12,000 p.W/cm 2 rating for 20
to 30 minutes, at a distance of about 1 inch, should
be sufficient.
Erasure leaves the array in an all 1s state .

.EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS:
(TA

21°C to 27 °C, VCC

5V ±1 0%, VSS

Symbol

OV)

Parameter

Min

Max

20.5

21.5

MHz

Units

VPP

Programming Supply Voltage

IPP

Programming Supply Current

1tTCLCL

Oscillator Frequency

TAVGL

Address Setup to PROG Low

TGHAX

Address Hold After PROG

48TCLCL

TDVGL

Data Setup to PROG Low

48TCLCL

TGHDX

Data Hold After PROG

48TCLCL

TEHSH

P2.7 (ENABLE) High to VPP

48TCLCL

TSHGL

VPP Setup to PROG Low

p,Sec

TGHSL

VPP Hold After PROG

p.sec

TGLGH

PROG Width

TAVQV

Address to Data Valid

TELQV

ENABLE Low to Data Valid

TEHQZ

Data Float After ENABLE

4
48TCLCL.

55
48TCLCL
48TCLCL

0
9-13

48TCLCL

msec

S0311S051 .. S031AH/S051AH
S032AH/S052AH • S751H/S75.1H-12

EPROM PROGRAMMING AND VERIFICATION WAVEFORMS

P1.0-P1.7
P2.0-P2.3

PROGRAMMING

VERIFICATION

ADDRESS

PORTO

~TAVQV

DATA IN
TDVGL
TAVGL!

A LE/PROG

DATA OUT
4!--TGHDX

I-

TGHAX

\~
TSHGL

Ei./VPP T d

TGHSL
TGLGH
21V :I: .SV

TTL HIGH

TEHSH

r-P2.7
(ENABLE)

TELQV---to:

J
FOR PROGRAMMING CONDITIONS SEE FIGURE 5.

9-14

!--TEHQZ

FOR VERIFICATION CONDITIONS SEE FIGURE 6.

8052AH-BASIC
• Full BASIC Interpreter in ROM on a
Single Chip
• BCD Floating Point Math
• Generates All Timing Necessary to
Program EPROMS and E2PROMS
• Fast Tokenlzed Interpreter
• "Stand Alone" Software Development
• All Arithmetic and Utility Routines Can
Be Called From Assembly Language

• Interrupts Can Be Handled By BASIC or
Assembly Language
• Built-In Accurate REAL TIME CLOCK
• Multiple User Programs
• Programs May Reside In RAM, EPROM
or E2PROM,
• Built In Radix Conversion - Hex to
Decimal and Decimal to Hex

8052AH-BASIC is an 8052AH microcontroller with a complete full-featured BASIC interpreter, MCS® BASIC52, resident in the 8K of available ROM. This Software-On-Silicon product is specifically designed to address
the needs of process control, measurement, and instrumentation applications. MCS BASIC-52 allows 8052AH
users to write programs in the popular BASIC language, which is much simpler to write and easier to understand
than assembly language.
In addition tothe standard BASIC commands and functions, such as floating point arithmetic and transcendental
operations, MCS BASIC-52 contains many unique features that allow the user to perform tasks that usually
require assembly language. Bit-wise logical operators, such as AND, OR, and EXCLUSIVE-OR are supported
as well as hexadecimal arithmetic.
A minimum amount of hardware is required to support MCS BASIC-52. Small systems can be constructed with
only a latch, 1K bytes of external memory, and the appropriate serial port drivers. With the addition of a
transistor, a gate, and a couple of passive components, MCS BASIC-52 can program EPROM or E2PROM
devices with the users application program. Both the standard and the inteligent Programming'· algorithms
are supported. '
MCS BASIC-52 is an interpreted language. This aliows the user to develop a program interactively without the
cumbersome and repetitive process of editing, assembling, loading, and running which is required by assemblers
and compilers. MCS BASIC-52 was designed to permit the programmer to develop resident high level language
software using the high performance 8052AH device.

+ 5 VOLTS---l

JC~
LINE PRINTER OUTPUT

RESET
XTAL1

XTAL2

PULSEr----------------------------,
ENABLEr--------------------------,
--------,I
PSENr-----------------~
LEVEL SHIFTERS

~~--------------~~

__M':~':E~~_.1

~r------------'

CONSOLE OUTPUT

CONSOLE INPUT

LEVEL
SHIFTERS

System Block Diagram

9-15

inter

8052AH-BASIC

FEATURES'

\ AUTOSTART

COMMAND SET .
MCS BASIC-52 contains all standard BASIC
commands, statements, and operators. Figure 1 list
the software feature set of MCS BASIC-52.

DATA FORMAT
The range of numbers, that can be represented in
MCS BASIC-52 is:
±1E':'127 to ±.99999999E

+ 127

CONTROL ORIENTED FEATURES
MCS BASIC-52 contains many unique features to
perform task that usually require assembly language
programming. The XBY and DBY operators can read
and/or write external and internal memory
respectively. The CBY operator is used to read
program memory. Additionally, virtually all of the
special function registers on the 8052AH can be
accessed with MCS BASIC-52. This allows the user
to set the timer or interrupt modes within the
constructs of a BASIC program. An accurate interrupt
driven REAL TIME CLOCK that has a 5 millisecond
resolution is also implemented in MCS BASIC-52.
This clock can be enabled, disabled, and used to
generate interrupts. Finally, a CALL statement that
allows the programmer to CALL assembly language
routines is available in MCS BASIC-52. Parameters
can be passed in a number of different ways.

After the user programs an,EPROM o~ E2PROM ;"ith
the desired BASIC program. The PROG2 or FPROG2
commands may be used to enable the unique
AUTOSTART feature of MCSBASIC-52. When
AUTOSTART is enabled, MeS BASIC-52 will execute
the user program after RESET or a power-up
condition. This permits the user to RUN a program
without connecting the MCS BASIC-52 device ,to a
console - a powerful feature for control
environments.

USER ACCESSABLE FUNCTION LIBRARY
Another unique feature of MCS BASIC-52 is that it
contains a complete library of functions that can be
accessed with assembly language. All floating point,
radix conversion, and 1/0 routines contained in MCS
BASIC-52 can be accessed with assembly language
CALL instructions. These complex arithmetic routines
can be used by the programmer in applications
requiring the speed of assembly language, but also
the complex arithmetics offered by BASIC.

8052AH-BASIC PIN DESCRIPTION
(FIGURE 2)
8052AH-BASIC is an 8052AH device, however, MCS
BASIC-52 assumes a particular hardware
configuration. The following pin description outlines
the pin functions defined by MCS BASIC-52.

EPROM/E2PROM FILE

VSS

Most Basic interpreters allow only one program to be
resident in memory, and many require that the
program reside in RAM. MCS BASIC-52 allows
programs to reside in both RAM and EPROMI
E2PROM. Additionally, up to 255 programs may
reside in EPROM/E2PROM. Programs may also be
transfered (XFER) from EPROM/E2PROM to RAM
for editing purposes.

Circuit ground potential.

EPROM/E2PROM PROGRAMMING
A powerful feature of MCS BASIC-52 is that it
generates all of the timing necessary to program any
standard EPROM or E2PROM device with the users'
program (PROG/FPROG). Additionally, very little
external hardware is required .to implement this
feature. Saving programs in EPROM/E2PROM is
much more,attractive and reliable than other
alternatives, such as cassette tape, especially in
control and/or other noisy environments.

VCC
Circuit supply voltage. 5 volts ± 10% relative to VSS.

ADO-AD7
The multiplexed low-order address and data bus used
during accesses to external memory: External pullup
devices (- 10K 0) are required on these pins if the
MCS BASIC-52 EPROM/E2PROM programming
feature is used.

AS"':A15
"Fhe high order address bus used during accesses to
external memory.

9-16

8052AH-BASIC

~ommands

RUN
LIST
L1ST#
NEW
NULL
RAM
ROM
XFER
PROG
PROGl
PROG2
FPROG
FPROGl
FPROG2

Statements

Operators

BAUD
ADD (+)
CALL
DIVIDE (I)
CLEAR
EXPONENTIATION (**)
CLEARS
MULTIPLY (*)
CLEARI
SUBTRACT(-)
CLOCKO
LOGICAL AND (.AND.)
CLOCKl
LOGICAL OR (.OR.)
DATA
LOGICAL X-QR (.xOR.)
READ
LOGICAL NOT
RESTORE
ABS( )
DIM
INT( )
DO-WHILE
SGN ( )
DO-UNTIL
SOR ( )
END
RND
FOR-TO-STEP LOG ( )
NEXT
EXP ( )
GOSUB
SIN ( )
RETURN
COS ( )
GOTO
TAN ( )
ON-GOTO
ATN ( )
ON-GOSUB =, >, >=,

T2/Pl.0
T2EX/P1.l
PWM OUTPUT I Pl.2
ALE DISABLE I Pl.3
PROGRAM PULSE I Pl.4
PROGRAM ENABLE I Pl.5
DMA ACKNOWLEDGE I Pl.&
UNE PRINTER OUTPUT I Pl.7
RESET
CONSOLE SERIAL INPUT
CONSOLE SERIAL OUTPUT
INTO I DMA REQUEST
INTl

TO
Tl
WR
RD
XTAL2
XTALl
VSS

VCC

ADO
ADl
AD2
AD3

AD4
AD5
AD&
AD7
+5 VOLTS
ALE

PSEN
A15
A14
A13
A12

All
Al0
A9
AS

Figure 2. Configuration

<, <=, <>
IF-THEN-ELSE
INPUT
LET
ONERR
ONEXTl
ONTIME
PRINT
PRINT#
PHO.
PHO.#
PH1.
PH1.#
PUSH
POP'
PWM
REM
RETl
STOP
STRING
UIO
Ull
UOO
UOl

ASC( )
CHR ( )
CBY( )
DBY( )
XBY( )
GET
IE
IP
PORTl
PCON
RCAP2
T2CON
TCON
TMOD
TIME
TIMERO
TIMERl
TIMER2
TIME
XTAL
MTOP
LEN
FREE
PI

the T2 trigger function are covered in the
Microcontrollers Handbook. Order Number 210918002.
PORT 1.1 (T2EX)
Can be used as the external input to TIMER/
COUNTER 2. A one (1) must be written to this port
pin output latch in order for this function to operate.
Details of the T2 trigger function are covered in the
Microcontroller Users Manual.
PORT 1.2 (PWM OUTPUT)
This pin is used as the PWM output port when the
PWM statement is executed. PWM stands for Pulse
Width Modulation and is used to generate pulses of
varying duty cycle and frequency.
PORT 1.3 (ALE orSABLE)
This pin is used to disable the ALE signal to the
external address latch when the EP.ROM/E2PROM
programming feature is used. In a system, this pin is
logically anded with ALE.

Figure 1. MCS® BASIC-52 Software Feature Set
PORT 1
A general purpose quasi-bidirectional 8-bit input!
output port. The individual pins on PORT 1 all have
alternate functions which mayor may not be
implemented by the user. The alternate functions are
as follows:

POR,T 1.4 (PROGRAMMING PULSE)
When the EPROM/E2PROM programming feature is
used, this pin provides the proper programming pulse
width to program EPROM and INTElligent EPROM@>
devices. MCS BASIC-52 actually calculates the
proper programming pulse width from the system
crystal value (XTAL) to assure the proper timing of
this pulse. When used to program E2PROM devices,
the length of this pulse is not critical. This pin is active
in the logical zero (0) state.

PORT 1.0 (T2)
Can be used as the trigger input to TIMER/COUNTER
2. A one (1) must be written to this port pin output
latch in order for this function to operate. Details of

9-17

inter .

8052AH~SASIC

PORT 1.5 (PROGRAMMING ENABLE)
When the EPROM/E2PROM pro!ilramming feature
is implemented, this pin is used to enable the
EPROM programming voltage. This pin remains
active (logically low (0» during the entire EPROM
programming process. On E2PROM devices. that do
not require any special programming voltage, this pin
is not used.

A control Signal that is used to enable READ operations to external data memory. This pin is active low
(0).
WR
A control signal that is used to enable WRITE operations to external data memory. This pin is active low
(0).

PORT 1.6 (DMA ACKNOWLEDGE)

When the DMA feature is implemented as described
in the MCS® BASIC-52 users manual, this pin functions as an active low DMA ACKNOWLEDGE output.

This pin can be programmed to be an external input
to TIMER/COUNTER 1.

PORT 1.7 (LINE PRINTER OUTPUT)

This pin functions as a serial output port when the
LlST# or PRINT# command and/or statement is
used. This enables the user to make a "hard copy"
of a program or to print out results of a calculation.

This pin can be programmed to be an external input
to TIMER/COUNTER O.
INT1

RESET

This pin is the external interrupt 1 pin. It is active low
and interrupts on this pin may be handled in either
BASIC or in assembly language.

A high (2.5 volts) on this pin for two machine cycles
while the oscillator is running resets the device. An
external pulldown resistor (-8.2K) from RESET to
VSS permits power-on reset when a capacitdr (-10
uf) is connected from this pin to VCC.

INTO/DMA REQUEST
This is the external interrupt 0 pin. It is active low and
may be optionally programmed to function as a DMA
request input pin. The DMA REQUEST pin is used
by E2PROM devices during programming.

ALE
ALE (address latch enable) is an output pin that is
used to latch the low order address byte during Read,
Write, or program fetch operations to external
memory.

CONSOLE SERIAL OUTPUT
This is the serial output pin to the console device.
Standard ASCII codes are used as "'Iell as a standard
asynchronous frame.

This pin (Program Store ENable) is a control signal
that is used to enable external program memory. In
MCS® BASIC-52, this pin will always remain inactive
(logically high (1» unless the user is running an assembly language program in external memory.

CONSOLE SERIAL INPUT
This is th!'! serial input pin that receives data f~om the
console device. Standard ASCII codes are assumed
to be the input and the data is assumed to be transmitted using a standard asynchronous frame.

XTAL1
Input to the inverting amplifier that forms the
oscillator.

NOTES

XTAL2

If pin 31 is grounded the'8052AH-BASIC will operate
as a standard 8032AH. The tolerances on this pin
are described under DC characteristics.

Output of the.inverting amplifier that forms the oscillator, and input to the internal clock generator. Receives the external oscillator signal when an external
oscillator is used.

For detailed information concerning this product
please refer to the MCS BASIC-52 Users Manual
(Order Number 210918-002). .

9-18

8052AH-BASIC

ABSOLUTE MAXIMUM RATINGS·

"NOTICE: Stresses above those listed under
.. Absolute Maximum Ratings" may cause
permanimt damage to the device. This is a stress
rating only and functional operation of the device at
these or any other conditions above those indic{Jted
in the operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Ambient Temperature Under Bias ... O°C to 70°C
Storage Temperature . . . . . . - 65°C to + 150·C
Voltage on Any' Pin With
Respect to Ground (VSS) . . .. -0.5Y to + 7V
Power Dissipation . . . . . . . . . . . . . . . 2 Watts

DC CHARACTERISTICS (TA = O°C to 70°C, VCC = 4.5V to 5.5V, VSS = OV)
Symbol

Parameter

Min

Max

'Unit

-0.5

O.S

Test Conditions

VIL

Input Low Voltage

VIH

Input High Voltage
(Except RST and XTAL2)

2.0

VCC+ 0.5

VIHl

Input High Voltage to
RST for Reset, XTAL2

2.5

VCC + 0.5

XTALl to VSS

VOL

Output Low Voltage Port 1, AS-15,
Control Functions

0.45

IOL = 1.6mA

VOLl

Output Low Voltage ALE, PSEN
(Note 1)

0.45

IOL = 3.2mA

VOH

Output High Voltage Port 1, AS-15,
Control Functions

2.4

IOH == -SOIlA

VOHl

Output High Voltage ADO-7, ALE, PSEN

2.4

IOH =

ilL

Logical 0 Input Current Port 1, AS-15
Control Functions

-SOO

IlA

Vin = 0.45V

1IL2

Logical 0 Input Current XTAL2

~2.5

XTAL1 at VSS,
Vin=0.45V

III

Input Leakage Current To ADO-7 EA

±10

/LA

0.45V(2.0
OAS

2.oX=

TEST POINTS
..,;0;,;;.8.....;._ _ _ _.....;0;,;;;...8_

FLOAT
2.4

i-----FLOAT - - - + I
2.0

2.0

0.8

2.4

0.45

AC inputs during testing are driven at 2.4V for a logic "1" and 0.45V for a logic "0", Timing measurements are made at 2.0V
for a logic "1" and O.BV for a logic "0". For timing purposes, the float state is defined as the pOint at which an ADO-7 pin sinks
2.4mA or sources 400JLA at the voltage test levels.

9-22

inter

8052AH-BASIC

CLOCK WAVEFORMS
INTERNAL
CLOCK

STATE 4
P11P2

'STATE 5
P11P2

STATE 1

STATE 6
P11P2

I P2

STATE 2,
P1

I P2

STATE 3
P1

I P2

STATE 5

STATE 4
P1

I P2

XTAL2

~------------~.

ALE

EXTERNAL PROGRAM MEMORY FETCH

~I--------------~
THESE

~
.

~_ _.....'

SIGNALS ARE NOT
ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION

I~'

ADO-7
________.....
·.,ND,CATES ADDRESS TRANSIONSI~___________________-'

A6-15
READ CYCLE
RD

PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)

AOO-7

A6-15
WRITE CYCLE
WR

---------------------,

·AOO'-7·

~:.

DPLOR RI
OUT

~--------------~

PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)

O--UT=--=--=--:"'~"*,,: i f
• ..t--tL

---DA1:--A

PCl OUT (IF PROGRAM

...-_____________________________-,MEMORY IS EXTERNAL)

A6-15

PORT OPERATION
MOV PORT, SRC
MOVDEST, P1
(INCLUDES INTO, INT1, TO, T1)

OLD DATA

SERIAL PORT S-H-,FT-C-L-OC--K----,

I NEW DATA

P1, PIN SAMPLED

~RXD

P1,
PIN SAMPLED

SAMPLED

RXDSAMPLED

This diagram indicates when Signals are clocked intemally. The time it takes the signals to propagate to the pins, however,
ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading, Propagation
also varies from output to output and component to component. Typically though, (TA = 25°C, fully loaded) RD and WR
propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the
AC specificlltions.

9·23

-n+ .-I®
I•• ,~
80C51 BH/80C51BH-2
CHMOS SINGLE COMPONENT 8'-BIT MICROCONTROLLER

with Factory Mask-Programmable ROM
, . 80C31 BH/80C31BH-2
CHMOS SINGLE COMPONENT 8-BIT CONTROL-ORIENTED
CPU WITH RAM AND I/O
80C51BH/80C31BH- 3.5 to 12 MHz VCC = 5V ± 20%
80C51BH-2/80C31BH-2 - 0.5 to 12 MHz VCC ::;:: 5V ± 20%
•
•
•
•

128 X 8 RAM
32 Programmable 110 Lines
Two 16-Bit Timer/Counters
64K Program Memory Space

•
•
•
•

Boolean Processor
5 Interrupt Sources
Programmable Serial Port
64K Data Memory Space

The MCS®-51 CHMOS products are fabricated on Intel's advanced CHMOS III process and are functionally
compatible with the standard MCS-51 HMOS and EPROM products, CHMOS III is a technology which combines
the high speed and density characteristics of HMOS with the low power attributes of CMOS, This combination
expands the effectiveness of the powerful MCS-51 ,architecture and instruction set
Like the MCS-51 EPROM and HMOS, the MCS~51 CHMOS products have the following features: 4K of ROM '
(80G51BH/80C51BH-2,only); 128 bytes of RAM; 32 I/O lines; two 16-bit timer/counters; a five-source two-level
interrupt structure; a full duplex serial port; and on-chip oscillator and clock circuitry, In addition, the MCS-51
CHMOS products have two software selectable modes of reduced activity for further' power reduction -.:... Idle
and Power Down.
Idle mode freezes the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue
functioning. Power Down mode saves the RAM contents but freezes the oscillator causing all other chip functions
to be inoperative.

Figure 1. Block Diagram

9-24

aoC51 BH/80C51 BH-2
80C31 BH/80C31 BH-2

inter

INDEX
CORNER

..
Ii:

Ii:

31
LSJ LSJ L4J :L....J
VCC
PO.O
PO.l
PO.2
PO.3
PO.4
PO.S
PO.6
PO.7

Pl.0
Pl.l
Pl.2
Pl.3
Pl.4
Pl.S
Pl.6
Pl.7
RST
P3.0/RXD
P3.1/TXD
P3.21INTO
P3.31NT1
P3.4/TO
P3.S/Tl
P3.6/WR
P3.7/RD
XTAL2
XTALI
VSS

Ii:

'1'
I I
I I

L....J

~J ~~ ~~

t41[

L.J

P1.5

PO.4

Pl.S

PO.S

Pl.7

PO.S

RST

PO.7

P3.0

EA
ALE
PSEN
P2.7
P2.6
P2.S
P2.4
P2.3
P2.2
P2.1
,P2.0

BOC51BH
BOC51BH-2
BOC31BH
aOC31BH-2

NC
P3.1

Ne
ALE

iiftN

P3.2
P3.3

P2.7

P3.4

P2.&

P3.S

,...,

r, r,

r, ,....,

-, ,...,

;18: :19: :20: ;21: ;22: :23: 124:

" "

DIagrams are for Pin reference only
Package sizes are not 10 scale

r' r..,

1
; 25 1 126
I I

P2.S

;271 :28:
~

!i. !i

Pad

,Figure 2. Configurations

IDLE AND POWER DOWN OPERATION

These special modes are activated by software via
the Special Function Register, PCON. Its hardware
address is 87H. PCON is not bit addressable.

Figure 3 shows the jnternal Idle and Power Down
clock configuration. As illustrated, Power Down
operation freezes the oscillator. Idle mode operation
allows the interrupt, serial port, and timer blocks to
continue to function while the clock to the CPU is
halted.

PCON: Power Control Register
(MSB)

(LSB)

ISMODI -

I -

I GF1 I GFO I PO I IDL I

Symbol Position Name and Function
SMOD

PCON.7

Double Baud rate bit. When set to a 1.
the baud rate is doubled when the serial
port is being used in either modes 1. 2

or 3.
XTAL2

XTALI

GF1
GFO
PO

INTERRUPT.

~~-{:::> SERIAL PORT.

TIMER BLOCKS

IDL

CPU

PCON.6 (Reserved)
PCON.5 (Reserved)
PCON.4 (Reserved)
PCON.3 General-purpose flag bit.
PCON.2 General-purpose flag bit.
PCON.1 Power Down bit. Setting this bit
activates power down operation.
PCON.O Idle mode bit. Setting Ihis bit activates
idle mode operation.

If 1's are written to PD and IDL at the same time, PD
takes precedence. The reset value of PCON is
Figure 3. Idle and Power Down Hardware

(OXXXOOOO).

9-25

80C51 BH/80C51 BH~2
80C31 BH/80C31 BH..2

'Idle Mode
The instruction that sets PCON.O is the last instruction
executed in ,the normal operating mode before Idle
mode is activated. Once in the Idle mode, the CPU
, status is preserved in its entirety: the Stack Pointer,
Program Counter, Program Status Werd, Accumu. lator, RAM, and all other registers maintain their data
during Idle. Table 1 describes the status of the external pins during Idle mode.
There are two ways to terminate the Idle mode.
Activation of any enabled interrupt will cause PCON.O
to be cleared by hardware, terminating Idle mode.
The interrupt is serviced, and following RETI, the next
instruction to be executed will be the one following
the instruction that wrote a 1 to PCON.O.

power down mode is entered, and that the voltage is
restored before the hardware reset is applied which
fr,ees the oscillator. Reset should not be released until
the oscillator has restarted and stabilized.
Table 1 describes the status of the external pins while
in the power down mode. It should be noted that if
the power down mode is activated while in external
program memory, the port data that is held in the
Special Function Register P2 is restored to Port 2. If
.the data is a 1, the port pin is held high during the
power down mode by the strong pullup, p1, shown
in figure 4.

80C51 BH I/O Ports
The I/O port drive of the 80C51BH is similar to the
8051. The I/O buffers for Ports 1, 2, and 3 are implemented as shown in figure 4.

The flag bits GFO and GF1 may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.O can also set or clear
one or both flag bits., When Idle mode is terminated
by an enabled interrupt, the service routine can
examine the status of the flag bits.

When the port latch contains a 0, all pFETS in figure
4 are off while the nFET is turned on. When the port
latch makes a 0-to-1 transition, the nFET turns off.
The strong pullup pFET, p1, turns on for two oscillator
periods, pulling the output high very rapidly. As the
output line is drawn high, pFET p3 turns on through
the inverter to supply the IOH source current. This
inverter and p3 form a latch which holds the 1 and is
supported by p2.

The second way of terminating the Idle mode is with
. a hardware reset. S(nce the oscillator is still running,
the hardware reset needs to be active for only 2
machine cycles (24 oscillator periods) to complete the
reset operation.

When Port 2 is used as an address port, for access
to external program of data memory, any address bit
that contains a 1 will have its strong pullup turned on
for the entire duration of the external memory access.

Power Down Mode
The instruction that sets PCON.1 is the last executed
prior to going into power down. Once in power down,
the oscillator is stopped. Only the contents of the onchip RAM is preserved. The Special Function Registers are not saved. A hardware reset is the only way
of exiting the power down mode.

When an I/O pin on Ports 1, 2, or 3is used as an
input, the user should be aware that the external circuit must sink current during the logical 1-to-0 transition. The maximum sink current is specified as ITL
under the D.C. Specifications. When the input goes
below approximately 2V, p3 turns off to save ICC
current. Note, when returning to a logical 1, p2 is the
only internal pullup that is on. This will result in a slow
rise time if the. user's circuit does n~t force the input

In the Power Down mode, VCC may be lowered to
minimize circuit power consumption. Care must be
taken to ensure the voltage is not reduced until the

Table 1. Status of the external pins during Idle and Power Down modes
Mode

Program Memory ALE PSEN

PORTO

Idle:

Internal

Port Data

Idle

External

Power
Down

Int~rhal

Power
Down

External

PORT1

PORT2

. PORT3

Port Data. Port Data

Port Data

Floating

Port Data

Address

Port Data

Floating

Port Data

9-26

SOC51 BH/SOC51 BH~2
SOC31 BH/SOC31 BH~2

vee

VCC

Q
FROM PORT
LATCH

READ
PORT PIN

Figure 4. 1/0 Buffers in the 8OC51 BH (Ports 1, 2, 3)

line high. For additional information, refer to the chapter entitled "Design Considerations When Using
CHMOS" in the 1984 Intel Microcontroller Handbook.

pulled high by the internal pullups, and in that state
can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (ilL, on
the data sheet) because of the internal pullups.

PIN DESCRIPTIONS

'Port 1 also receives the low-order address bytes dur-'
ing program verification.

VCC

Port 2

Supply voltage during normal, Idle, and Power Down
operations.

Port 2 is an 8-bit bi-directional I/O port with internal
pullups. Port 2 pins that have 1's written to them are
pulled high by the internal pullups, and in that state
can be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (ilL, on
the data sheet) because of the internal pullups.

VSS
Circuit ground.

Port 0
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1's. During
accesses to external Data Memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.

Port 0 is an 8-bit open drain bi-directional I/O port.
Port 0 pins that have 1's written to them float, and in
that state can be used as high-impedance inputs.
Porf 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting 1's. Port 0 also outputs the
code bytes during program verification in the
80C51 BH. External pullups are required during program verification.

Port 3
Port 3 is an 8-bit bi-directional I/O port with internal
pullups. Port 3 pins that have 1's written to them are
pulled high by the internal pullups, and in that state
can be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current (ilL, on
the data sheet) because of the pullups.

Port 1
Port 1 is an 8-bit bi-directional I/O port with internal
pullups. Port 1 pins that have 1's written to them are

9-27

80C51 BH/80C51 BH-2
80C31 BH/80C31 BH~2

inter

Port 3 also serves the functions of various special
features of the MCS-51 Family, as. listed below:
Program Store Enable is the read strobe to external
Program Memory,

Port Pin

Alternate Function

,P3.0

RXD (serial input port)

When the 80C51BH is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memory.

P3.1

TXD (serial output port)

P3.2

INTO (external interrupt 0)

P3.3

INT1 (external Interrupt 1)

External Access enable. EA must be externally held
low in order to enable the device to fetch code from
external Program Memory locations OOOOH to
OFFFH.

P3.4

TO (Timer 0 external input)

P3.5

T1 (Timer 1 external input)

P3.6

WR (external data memory write
strobe)

P3.7

RD (external data memory read
strobe)

XTAL1
Input to the inverting oscillator amplifier and input to
the internal clock generator circuits.

XTAL2
Output from the inverting oscillator amplifier.

RST

OSCILLATOR CHARACTERISTICS

Reset input. A high on this pin for two machine cycles
while the oscillator is running resets the device, An
internal diffused resistor to VSS permits Power-On
reset using only an external capacitor to Vcc.

XTAL 1 and XTAL2 are the input and output respectively, of an inverting amplifier which is corifigured for
use as an on-chip oscillator, as shown in Figure 5.
Either a quartz crystal or ceramic resonator may be
used. More detailed information concerning the use
of the on-chip oscillator is available in Application
Note AP-155, "Oscillators for Microcontrollers."

ALE
Address Latch Enable output pulse for latching the
low byte of the address during accesses to external
memory.

To drive the device from an external clock source,
XTAL 1 should be driven while XTAL2 is left unconnected as shown in figure 6. There are no requirements on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data
Sheet must be observed.

In normal operation ALE is emitted at a constant rate
of '/6 the oscillator frequency, and may be used for
external timing or clocking purposes. Note, however,
that one ALE pulse is skipped during each access to
external Data Memory.

Ii 9

XTAL2
-

EXTERNAL
OSCILLATOR
SIGNAL

XTAL 1

-----------1

XTAL2

XTAL 1

VSS

Figure 6. External Drive Configuration

Figure 5. Crystal O.$clllator

9-28

80C51 ~H/80C51 BH-2
80C31 f3H/SOC31 BH-2

inter
ABSOLUTE MAXIMUM RATINGS·

'NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Ambient Temperature Under Bias . . . O°C to 70°C
Storage Temperature .. . . . . - 65°C to + 150°C
Voltage on Any Pin to VSS ... -O.SV to VCC+ 1V
Voltage on VCC to VSS. . . . . .. - 0.5V to + 7V
Power Dissipation . . . . . . . . . . . . . . . . LOW

D.C. CHARACTERISTICS: (TA = O°C to 70°C; VSS = OV; VCC = SV ± 20%)
Symbol

Parameter

Min

Max

Unit

Test Conditions

-0.5

0.2VCC-·1

0.2VCC+·9

VCC+0.5

0.7VCC

VCC+0.5

Output Low Voltage
(Ports 1, 2, 3)

O.4S

IOL = 1.6 mA

VOL1

Output Low Voltage
(Port 0, ALE, PSEN)

0.45

IOL = 3.2 mA (Note 1)

VOH

Output High Voltage
(Ports 1, 2, 3)

2.4

IOH = - 80J,LA VCC = SV ± 10%

O.7SVCC

IOH= - 3OILA

0.9VCC

IOH = -1 OJ,LA

2.4

IOH= -400J,LA VCC=SV±10%

0.7SVCC

IOH = -150J,LA

VIL

Input Low Voltage

VIH

Input High Voltage
(Except XTAL 1, RST)

VIH1

Input High Voltage to
XTAL1, RST

VOL

VOH1

Output High Voltage
(Port 0 in External Bus
Mode, ALE, PSEN)

0.9VCC

IOH = - 40J,LA (Note 2)

IlL

Logical 0 Input Current
(Ports 1, 2, 3)

-50

J,LA

Yin = 0.4SV

ITL

Logical 1 to 0 transition
Current (Ports 1, 2, 3)

-SOO

J,LA

Yin = 2.0V

III

Input Leakage Current
(Port 0, EA)

±10

ILA . 0.45

< Yin < VCC

RRST

RST Pulldown Resistor

12S

Kohm

CIO

Pin Capacitance

tast freq = 1 MHz, TA = 2SoC

IpD

Power Down Current

J,LA

VCC = 2 to 6V (Note 3)

Maximum Operating ICC (mA) (note 4)
VCC
Freq.
0.5 MHz
3.S MHz
8 MHz
12 MHz

1.6
4.3
8.3
12

2.2
5.7
11
16

3
7.5
14
20

Maximum Idle ICC (mA) (note 5)
VCC
Freq.
O.S MHz
3.S MHz
8 MHz
12 MHz

9-29

0.6

0.9
1.6
2.7
3.7

. 1.2
2.2
3.7
S

1.1
1.8
2.5

80C51 BH/SOC51 BH-2
80C31BH/80C31BH.2

Note 1: Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimpt>sed on the' VOLS of ALE, and
Ports 1 and 3. The noise is due to the external bus capacitance discharging into the Port 0 and Port 2 pins when
these pins make a 1-to-0 transition during bus operations. In the worst case (capacitive loading> 100 pF), the nOise
pulse on ALE line may exceed
In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use
an ,address latch with a Schmitt Trigger STROBE input.

o.av.

Note 2: Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the .9VCC
specification when the address bits are stabilizing.
'
Note 3: Power Down ICC is measured with all output pins disconnected; EA=PORTO=VCC; XTAL2 N.C.; RST=VSS.
Note 4: ICC is measured with all output pins disconnected; XTAL 1 driven with TCLCH, TCHCL = 10 ns, Vii = VSS + .5v,
Vih=VCC-.5v; XTAL2 N.C.; EA= RST= PORTO=VCC.
Note 5: Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 10 ns, ViI=VSS+ .5v,
Vih=VCC-·5v; XTAL2 N.C.; EA= PORTO = VCC; RST=VSS.

A.C. CHARACTERISTICS (TA = O°C to 70°C; VSS = OV; VCC = 5V ± 20%;
Load Capacitance for Port 0, ALE, and PSEN = 100 pF, Load Capacitance for
All Other Outputs = 80 pF)

EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS

Min

Max

Units

Oscillator Freq (80C51 BH)

3.5

MHz

Oscillator Freq (80C51BH-2)

0.5

MHz

Parameter

Symbol
lfTCLCL

ALE Pulse Width

2TCLCL-40

Address Valid to ALE Low

TCLCL-40

TLLAX

Address Hold After ALE Low

TCLCL-35

TLHLL
TAVLL

TLLlV

ALE Low to Valid Instr In

TLLPL

ALE Low to PSEN Low

TCLCL-25

TPLPH

PSEN Pulse Width

3TCLCL-35

TPLIV

PSEN Low to Valid Instr In

TPXIX

Input Instr Hold After PSEN

TPXIZ

Input Instr Float After PSEN

TPXAV

PSEN to Address Valid

4TCLCL-150

ns
ns
ns

,3TCLCL - 150

ns
TCLCL-20

TCLCL-8

TAVIV

Address to Valid Instr In

TPLAZ

PSEN Low to Address Float

TRLRH

RD Pulse Width

6TCLCL - 1.00

TWLWH

WR Pulse Width

6TCLCL-l00

TRLDV

RD Low to Valid Data In

ns
5TCLCL-150
0

ns
,

ns
ns
ns

5TCLCL-165

TRHDX

Data Hold After RD

TRHDZ

Data Float After RD

2TCLCL-70

'TLLDV

ALE Low to Valid Data In

8TCLCL-150

9·30

80\;:)1 tst1/6UC515t1-2

inter

SOC31 BH/SOC31 BH-2

EXTERNAL PROGRAM MEMORY READ CYCLE
I·--T~HLL--

ALE

-TAVLL-

TLLPL

---TPLPH---

TLLIV

PSEN

1'Pi:iV

'I.
TLLAX

TPXIZI--

- -

~"J

TPXAV

TAZPL
TPXIX-

"'i

INSTR
IN

AO-A7

>Jl\

AO-A7

TAVIV

PORT 2

AB-A15

A8-A15

EXTERNAL DATA MEMORY READ CYCLE
TWHlH

ALE

I-----TLLDV-----I

--TlLWL--I-----TRLRH-+----1

-TRlAZ

PORTO

I------TAVDV------I

PORT2

P2 O·P2 7 OR

A8~A15

FROM DPH

9-31

A8·A15 FROM PCH

inter

VV"';' l'gn/!II'u",;, I'gn-,r;

80C31 BI1/S0C31 BH-2

A.C. CHARACTERISTICS
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS (Continued)
Parameter

Symbol
TAVDV

Address to Valid Data In

Min

Max

Units

9TCLCL-16S

3TCLCL+SO

TLLWL

ALE Low to RD or WR Low

3TCLCL-SO

TAVWL

Address to RD or WR Low

4TCLCL-130

TQVWX

Data Valid to WR Transition

TCLCL-60

TQVWH

Data Valid to WR High

7TCLCL-1S0

TWHQX

Data Held After WR

TCLCL-SO

TRLAZ

RD Low to Address Float

TWHLH

RD or WR High to ALE High

TCLCL-40

TCLCL+SO

EXTERNAL CLOCK DRIVE
Symbol
1tTCLCL

Min

Max

Units

Oscillator Freq (80CS1 BH)

3.S

MHz

Parameter

Oscillator Freq (80C51 BH-2)

0.5

TCHCX

High Time

TCLCX

Low Time

TCLCH

Rise Time

TCHCL

Fall Time

EXTERNAL CLOCK DRIVE

EXTERNAL
OSCILLATOR
SIGNAL

I---TCLCL----

EXTERNAL
OSCILLATOR
SIGNAL

XTAL,2

XTAL 1

VSS

-::.-

9-32

ns
ns

SOC51 BH/SOC51 BH-2
SOC31 BH/SOC31 BH-2

EXTERNAL DATA MEMORY WRITE CYCLE

ALE

PSEN

-0~_---+--'lh,--------,/
~

\,-----,1

-TllWL-I---TWlWH----!

rQVWx

~
I~+----TQVWH----'•
PORTO

TWHQX

..L

DATA OUT

PORT 2

AS - A15 FROM PCH

P20- P27 OR A8 - A15 FROM DPH

SERIAL PORT TIMING - SHIFT REGISTER MODE
A.C. CHARACTERISTICS: (TA = O°C to 70°C; VSS = OV; VCC = 5V

± 20%;
Load Capacitance = 80 pF)

Symbol

Parameter

TXLXL

Serial Port Clock Cycle Time

TQVXH
TXHQX

Min

Max

Units

12TCLCL

J-LS

Output Data Setup tQ Clock Rising Edge

1OTCLCL - 133

Output Data Hold After Clock Rising Edge

2TCLCL-117

TXHDX

Input Data Hold After Clock Rising Edge

TXHDV

Clock Rising Edge to Input Data Valid

0
10TCLCL-133

SHIFT REGISTER TIMING WAVEFORMS

----...,i-11ILXL-j
1-="'-I1--11IHO'

WfIlTE TO SBUF

X'-_---JX'-_---JX,

11IHD'~ j I--"HO'

X'-_---JX'-_---J1

In
t

SETRI

CLEAR Fli

9-33

80C51 BH/80C51 BH·2
80C31 BH/80C31 BH·2

inter

&[[j)W&[t8~~ ~[t8[?@Iffi[KIJ&un@1J:il

Table 2. MCS®·51 Instruction Set Description
LOGICAL OPERATIONS (CONTINUED)

ARITHMETIC OPERATIONS
Mnemonic
A,Rn
ADD

ADD

A,direct

ADD

A,@Ri

ADD

A,#data

AD DC A,Rn
ADDC A,direct
AD DC A,@RI
ADDC A,#data
SUBB

A,Rn

SUBB

A,direct

SUBB

A,@Ri

SUBB

A,#data

INC
INC'
INC
INC
INC
DEC
DEC
DEC
DEC

A
Rn
direct
@RI
DPTR
A
Rn
direct
@RI

MUL
DIV
DA

AB
AB
A

Mnemonic
A,@RI
ORL

Description
Byte Cyc
Add register to
Accumulator
Add direct byte to
Accumulator
2
Add indirect RAM to
Accumulator
1
Add immediate data to
2
Accumulator
Add register to
Accu mu lator with Carry
Add direct byte to A
with Carry flag
2
Add indirect RAM to A
with Carry flag
Add Immediate data to
A with Carry flag
2
Subtract register from A
with Borrow
Subtract direct byte
from A With Borrow
2
Subtract Indirect RAM
from A with Borrow
Subtract immed data
from A With Borrow
2
1
Increment Accum ulator 1
1
Increment register
1
1
Increment direct byte
2
1
Increment indirect RAM 1
1
I ncrement Data POinter
1
2
Decrement Accumulator 1
1
Decrement register
1
1
2
1
Decrement direct byte
Decrement indirect
RAM
1
Multiply A & B
4
Divide A by B
4
Decimal Adjust
Accumulator

ANL

A,dlrect

ANL

A,@RI

ANL

A,#data

ANL

direct,A

ANL

direct,#data

ORL

A,Rn

ORL

A,direct

A,#data

ORL

direct,A

ORL

direct,#data

XRL

A,Rn

XRL

A,direct

XRL

A,@RI

XRL

A,#data

XRL

direct,A

XRL

direct, #data

CLR
CPL

A
A

RL
RLC

A
A

RRC

SWAP

DATA TRANSFER
Mnemonic
A,Rn
MOV

LOGICAL OPERATIONS
Mnemonic
ANL
A,Rn

ORL

Byte Cyc
Destination
OR indirect RAM to
Accumulator
OR immediate data to
Accumulator
2
OR Accumulator to
direct byte
2
OR immediate data to
direct byte
2
3
Exclusive-OR register to
Accumulator
Exclusive-OR direct
byte to Accumulator
2
Exclusive-OR Indirect
RAMtoA
Exclusive-OR
immediate data to A
2
Exclusive-OR Accumulator to direct byte
2
Exclusive-OR immediate data to direct
2
3
1
Clear Accumulator
Complemeht
Accumulator
Rotate Accumulator Left
Rotate A Left through
the Carry flag
Rotate Accumulator
Right
Rotate A Right through
Carry flag
Swap nibbles within the
Accumulator

Destination
Byte Cyc
AND register to
Accumulator
AND direct byte to
Accumulator
2
AND indirect RAM to
Accumulator
AND Immediate data to
Accumulator
2
AND Accumulator to
direct byte
2
AND immediate data to
direct byte
3
2
OR register to
Accumulator
OR direct byte to
Accumulator
2

9·34

MOV

A,dlrect

MOV

A,@Ri

MOV

A,#data

MOV

Rn,A

MOV

Rn,direct

MOV

Rn,#data

MOV

direct,A

MOV

direct,Rn

MOV

direct, direct

MOV

direct,@Ri

Description
Byte Cyc
Move register to
Accumulator
Move direct byte to
Accumulator
2
Move indirect RAM to
Accumulator
Mov immediate data to
Accumulator
2
Move Accumulator to
register
Move direct byte to
2
2
register
Move immediate data to
register
2
Move Accumulator to
direct byte
2
Move register to direct
byte
2
2
Move direct byte to
direct
2
3
Move indirect RAM to
direct byte
2
2

8OC51 BH/80C51 BH·2
80C31 BH/80C31 BH·2
Table 2. MCS<8>·51 Instruction Set Description (Continued)
DATA TRANSFER (CONTINUED)

PROGRAM AND MACHINE CONTROL

Mnemonic
direct,#data
MOV

Mnemonic
ACALL addrll

MOV
MOV
MOV
MOV
MOVC
MOVC
MOVX
MOVX
MOVX
MOVX
PUSH
POP
XCH
XCH
XCH
XCHD

Description
Byte Cyc
Move immediate data tb
direct byte
2
3
@Ri,A
Move Accumulator to
indirect RAM
@Ri,direct
Move direct byte to
indirect RAM
2
2
@RI,#data
Move immediate data to
indirect RAM
2
DPTR,#data16 Load Data Pointer with
a 16-bit constant
3
2
A,@A+DPTR Move Code byte relative
to DPTRtoA
2
A,@A+PC
Move Code byte relative
to PCtoA
2
A,@Ri
Move External RAM (6bit addr) to A
2
A,@DPTR
Move External RAM (16bit addr) to A
2
@Ri.A
Move A to External RAM
(6-bit addr)
2
@DPTR,A
Move A to External RAM
(l6-bit addr)
2
direct
Push direct byte onto
stack
2
2
direct
Pop direct byte from
stack
2
2
A,Rn
Exchange register with
Accumulator
A,direct
Exchange direct byte
with Accumulator
2
A,@Ri
Exchange Indirect RAM
with A
A,@Ri
Exchange low-order
Digit ind RAM w A

BOOLEAN VARIABLE MANIPULATION
Mnemonic
CLR
C
bit
CLR
SETB C
SETB bit
CPL
C
CPL
bit
ANL
C,bit
ANL

C,/bit

ORL

C/bit

OAL

C.lblt

MOV

C,/blt

MOV

blt,C

Description
Byte eyc
Clear Carry fl1l9
1
1
Clear direct bit
2
1
Set Carry flag
1
1
Set direct Bit
2
1
Complement Carry flag
1
1
Complement direct bit
2
1
AND direct bit to Carry
flag
2
2
AND complement of
direct bit to Carry
2
2
OR direct bit to Carry
flag
2
2
OR complement of
direct bit to Carry
2
2
Move direct bit to Carry
flag
2
Move Carry flag to
direct bit
2
2

Description
Byte Cyc
Absolute Subroutine
Call
2
2
LCALL addr16
Long Subroutine Call
3
2
RET
Return from subroutine 1
2
RETI
Return from ihterrupt
1
2
AJMP addrll
Absolute Jump
2
2
LJMP addr16
Long Jump
2
3
SJMP rei
Short Jump (relative
addr)
2
2
@A+DPTR
JMP
Jump indirect relative to
the DPTR
2
rei
JZ
Jump if Accumulator is
Zero
2
2
rei
JNZ
Jump if Accumulator IS
Not Zero
2
2
rei
JC
Jump if Carry flag is set 2
2
JNC
rei
Jump if No Carry flag
2
2
bit, rei
JB
Jump if direct Bit set
3
2
JNB
blt,rel
Jump If direct Bit Not
set
2
3
bit, rei
Jump if direct Bit is set
JBC
& Clear bit
2
3
CJNE A,dlrect,rel
Compare direct to A &
Jump if Not Equal
3
2
CJNE A,#data,rel
Comp, immed, to A &
Jump If Not Equal
3
2
CJNE Rn,#data,rel Comp, immed, to reg &
Jump If Not Equal
3
2
CJNE @Ri,#data,rel Comp, Immed, to ind, &
;1
Jump if Not Equal
3
DJNZ Rn,rel
Decrement register &
Jump If Not Zero
2
2
Decrement direct &
DJNZ direct, rei
Jump If Not Zero
3
2
NOP
No operation
1
1
Notes on data addressing modes:
Rn
-Working register RO-R7
-128 Internal RAM locations, any I/O port,
direct
control or status register
-Indirect internal RAM location addressed by
@RI
register RO or Rl
-8-blt constant included ,in instruction
#data
#datal6 -16-bit constant Included as bytes 2 & 3 of
instruction
bit
-128 software flags, any 1/0 pin, control or
status bit
Notes on program addressing modes:
addr16 -Destination address for LCALL & LJMP may
be anywhere within the 64-K program
memory address space
Addrl1 -Destination address for ACALL & AJMP will be
within the same 2-K page of program
memory as the first byte of the following
instruction
rei
-SJMP and all conditional jumps include an 8bit offset byte, Range is +127-128 bytes relative
to first byte of the following instruction
All mnemonics copyrighted © Intel Corporation 1979

8OC51 BHJ80C51 BH~2
80C31 BH/80C31 BH~2

inter

Table 3. Instruction Op~odes !n Hexldeclmal Order
Hex
Code

00
01
02
03
04
05
06
07
08
09
OA
08
OC
00
OE
OF

10
11
12
13
14
15
16

17
18
19
1A
18
1C
10
1E
IF
20
21
22
23
24
25
26
27
28
29
2A
28
2C
20
2E
2F
30
31
32

Nun:tber Mnemonic
of Bytes

1
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
2
2
1
1
1
1
1
1
1
1
1
1
3
2
1

NOP
AJMP
LJMP
RR
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
J8C
ACALL
LCALL
RRC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
J8
AJMP
RET
RL
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD'
ADD
ADD
ADD
ADD
JN8
ACALL
RETI

Hex
Code

Operands"

33
34
35
36
37
38
39
3A
38
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
58
5C
50
5E
5F
60
61
62
63
64
65

code addr
code addr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr, code addr
code addr
code addr
A
A
data aridr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr, code addr
code addr
A
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
bit addr, code addr
code addr

9-36

Number Mnemonic
of Byles

1
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2

RLC
ADDC
ADDC
ADDC
AD DC
ADDC
ADDC
AD DC
ADDC
ADDC
ADDC
ADDC
AD DC
JC
AJMP
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
GRL
GRL
GRL
ORL
ORL
JNC
ACALL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
JZ
AJMP
XRL
XRL
XRL
XRL

Operands"

A
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code"addr
code addr
dataaddr,A
data addr,#data
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
codeaddr
dataaddr,A
data addr,#data
A,#data
A,data addr
A,@RO
A@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
codeaddr
code addr
dataaddr,A
data addr,#data
A,#data
A,data addr

80C51 BH/80C51 BH~2.
80C31 iBH/80C31 BH-2

'Table 3. Instruction Opcodes In Hexldeclmal Order (Continued)
Hex
Code

66
67
68
69

SA
6B
6C
60
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
SA
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98

Number Mnemonic
01 Bytes

1
1
1
1
1
1
1
1
1
1
2
2
2
1
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
3
2
2
2
2
2
2
2
2
2
2
3
2
2
1
2
2
1
1
1

XAL
XAL
XAL
XAL
XAL
XAL
XAL
XAL
XAL
XAL
JNZ
ACALL
OAL
JMP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
SJMP
AJMP
ANL
MOVC
OIV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ACALL
MOV
MOVC
SUBB
SUBB
SUBB
SUBB
SUBB

Operands

Hex
Code

A,@AO
A,@A1
A,AO
A,A1
A,A2
A,A3
A,A4

99
9A
9B
9C
90
9E
9F
AD
A1
A2
A3
A4
AS
A6
A7
A8
A9
AA
AB
AC
AO
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB

A,A~

A,A6
A,A7
code addr
code addr
C,bI! addr
@A+OPTA
A,#data
data addr,#data
@AO,#data
@A1,#data
AO,#data
A1,#data
A2,#dah:l
A3,#data
A4,#data
A5,#data
A6,#data
A7,#data
code addr
code addr
C,blt addr
A,@A+PC
AB
data addr, data addr
data addr,@AO
data addr,@A1
data addr,AO
data addr,A 1
data addr,A2
data addr,A3
data addr,A4
data addr,A5
data addr,A6
data addr,A7
OPTA,#data
code addr
bit addr,C
A,@A+OPTA
A,#data
A,data addr
A,@AO
A,@A1
A,AO

9-37

Number Mnemonic
01 Bytes

1
1
1
1
'1
1
1
2
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
1
1
2
1
1
1
1
1
1

SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
OAL
AJMP
MOV
INC
MUL
reserved
MOV
Moll
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ANL
ACALL
CPL
CPL
CJNE
. CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
PUSH
AJMP
CLA
CLA
SWAP
XCH
XCH
XCH
XCH
XCH
XCH
XCH

Operands

A,A1
A,A2
A,A3
A,A4
A,A5
A,A6
A,A7
CJblt addr
codeaddr
C,blt addr
OPTR
AB
@AO,data adr
@R1,data addr
AO,data addr
A1,data addr
A2,data addr
A3,data addr
A4,data addr
A5,data addr
A6,data addr
A7,data addr
C.lbI! addr
code addr
bl't addr
C
A,#data,code addr
A,data addr,code addr
@AO,#data,code addr
@A1,#data,code addr
AO,#data,code addr
A1,#data,code addr
A2,#data,code addr
A3,#data,code addr
A4,#data,code addr
A5,#data,code addr
A6,#data,code addr
A7,#data,code addr
data addr
code addr
bit addr
C
A
A,data addr
A,@AO
A,@Al
A,AD
A,A1
A,A2
A,A3

8q0518ti/80C518H-2
80C31a!"l/8,OC3~BH-2

Table 3. Instruction Opc~es III Hexldeclmal O,der(Cqntlllued)
Hex
Code

CC
CD
CE
CF
DO
01
02
,03
04
05
06
07
08
09
DA
OS
DC
DO
DE
OF
EO
E1
E2
E3
E4
E5

Number Mnemonic
of Bytes

1
1
1
1
2
2
2
1
1
3
1
1
2
2
2
2
2
2
2
2
1
2
1
1
1
2

XCH
XCH
XCH
XCH
POP
ACALL
SETS
SETS
DA
DJNZ
XCHD
XCHD
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
MOVX
AJMP
MOVX
MOVX
CLR
MOV

Hex
Code

Operal1ds

A,R4
A,R5
A,R6
A,R7
data addr
code addr
bit addr
C
A
data addr,code addr
A,@RO
A,@R1
RO,code addr
R1,codeaddr
R2,code addr
R3,code addr
R4,code addr
R5,code addr
R6,code addr
R7,code addr
A,@DPTR
code addr
A,@RO
A,@R1
A
A,data addr

E6
E7
E8
E9
EA
ES
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FS
FC
FD
FE
FF

9-38

Number Mnemonic
of Bytes

1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1

MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVX
ACALL
MOVX
MOVX
CPL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV

Operands

A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
@DPTR,A
code addr
@RO,A
@R1,A
A
data addr,A
@RO,A
@R1,A
RO,A
R1,A
R2,A
R3,A
R4,A
R5,A
R6,A
R7,A

S031 AH/S051 AH
S032AH/S052AH
S751 H/S751 H
EXPRESS
• Extended Temperature Range
• Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in, and an extended
temperature range with or without burn-in.
With the commercial standard temperature range operational characteristics are guaranteed over the temperature range of O°C to 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of -40°C to + 85°C.
The optional burn-in is dynamic, for a minimum time of 160 hours at 125°C with VCC = 5.5V ±0.5V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.

Electrical Deviations from Commercial
Specifications for Extended Temperature
Rahge
D.C. and A.C. parameters not included here are the
same as in the commercial temperature range data
sheets.

D.C. CHARACTERISTICS: (TA = -40°C to +85°C; VCC = 5V ±10%; VSS = OV)
Symbol

Parameter

V,L

Input Low Voltage

V,H

Input High Voltage (Except
XTAL2, RST)

ICC

Power Supply Current:
8051 AH,8031 AH
8052AH,8032AH
8751 H,8751 H

Min

Max

Unit

-0.5

0.75

2.1

VCC+0.5

135
175
265

ma
ma
ma

9-39

Test Conditions

All Outputs
Disconnected;
EA =VCC

[?>1Rl~ulMil~IM~IRlW

MCS(!)·51 EXPRESS

Table 1 - Prefix Identification
Prefix

Package .Type

Temper~ture

Range

Burn-In

plastic

. commercial

cerdip

commercial

ceramic

commercial

plastic

extended

cerdip

extended

ceramic

extended

plastic

commercial

yes

cerdip

commercial

yes

ceramic

commercial

yes

plastic

extended

yes

cerdip

extended

yes

ceramic

extended

yes

Please note:
• Corpmercial temperature range is 0° to. 70°C. Extended temperature range is - 40° to

+ 85°C.

• Burn-in is dynamic, for a minimum time of 160 hours at 125°C, VCC = 5.5V ±0.5V, following guidelines in MIL-STO-883
Method 1015 (Test Condition OJ.
• The following devices are not available in plastic packages:
8751 H,8751 H
• The following devices are not available in ceramic packages:
8051AH,8031AH
.
8052AH,8032AH

Examples: P8031AH indicates 8031AH in a plastic package and specified for commercial temperature range,
without burn-in. LD8751 H indicates 8751 H in a cerdip package and specified for extended temperature range
with burn-in.

9-40

MCS®~51 Application Notes

An Introduction
to the Intel MCS®-S1
Single-Chip
Microcomputer
Family

Contents
1. INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . 10-2
Family Overview . . . . . . . . . . . . . . . . . . . . . . 10-2
Microcomputer Background Concepts. . . . . . . . . . 10-3
2. ARCHITECTURE AND ORGANIZATION ........ 10-5
Central Processing Unit ... .' . . . . . . . . . . . . . . 10-6
Memory Spaces . . . . . . . . . . . . . . . . . . . . . . 10-9
Input/Output Ports . . . . . . . . . . . . . . . . . . . . 10-1 0
Special Peripheral Functions . . . . . . . . . '.' ... 10-11
3. INSTRUCTION SET AND
ADDRESSING MODES . . . . . . . . . . . . . . . . 10-15
Data Addressing Modes. . . . . . . . . . . . . . . . . 10-15
Addressing Mode Combinations . . . . . . . . . . . . 10-18
Advantages of Symbolic Addressing. . . . . . . . . . 10-18
Arithmetic Instruction Usage . . . . . . . . . . . . . . 10-19
Multiplication and Division . . . . . . . . . . . . . . . . 10-20
Logical Byte Operations. . . . . . . . . . . . . . . . . 10-20
Program Control .. '..................... 10-21
Operate-and-Branch Instructions. . . . ~ . . . . . . . 10-22
Stack Operations. . . . . . . . . . . . . . . . . . . . . 10-22
Table Look-Up Instructions . . . . . . . . . . . . . . . 10-23
4•. BOOLEAN PROCESSING INSTRUCTIONS ..... 10-25
Direct Bit Addressing. . . . . . . . . \ . .. . . . . . . 10-~5
Bit Manipulation Instructions . . . . . . . . . . . . . . 10-25
Solving Combinatorial Logic Equations ........ '10-26
5. ON-CHIP PERIPHERAL FUNCTIONS ........ 10-28
VO Ports. . . . . . . . . . . . . . : . . . . . . . . . . . 10-28
Serial' Port and Timer . . . . . . . . . . . . . . . . • .. 10-29
6. SUMMARY . • . . . . . . . . . . . . . . . , ...... 10-30

10-1

vSs

P1.0
P1.1
P1.2
P1.3
P1.4
P1.S
P1.6
P1.7

VPD/RST
P3.0/RXD
P3.1/TXD
P3.2/iMi'O
P3.4/TO
P3.S/T1
P3.6/WR
P3.71Ro
XTAL2
XTAL1

VSS

vee RST /vPD

vee

po.o
PO.1
PO.2
PO.3
PM
PO.S
PO.6
PO.7
VDD/EA
PiiOG/ALE

PSEN
P2.7
P2.6
P2.S

TXD
INTO

P2.4

PORT 3

P2.3
P2.2
P2.1
P2.0

IN~;
RXD

\Vii

Figure 1a. 8051 Microcomputer Pinout Diagram

Figure 1b. 8051 Microcomputer Logic Symbol

1. INTRODUCTION

some microprocessor (preferably Intel's. of course) or
have a background in computer programming and digital
logic.

In 1976 Intel introduced the MCS-48'· family, consisting
of the 8048, 8748, and 8035 microcomputers. These parts
marked the first time a complete microcomputer system.
including an eight-bit CPU, 1024 8-bit words of ROM
or EPROM program memory, 64 words .of data memory,
I/O ports and an eight-bit timer/counter could be integrated onto a single silicon chip. Depending only on the
program memory contents, one chip could control a
limitless variety of products, ranging from appliances or
automobile engines to text or data processing equipment.
Follow-on products stretched the MCS-48'· architecture
in several directions: the 8049 and 8039 doubled the
amount of on-chip memory and ran 83% faster; the 8021
reduced costs by executing a subset of the 8048 instructions with a somewhat slower clock; and the 8022 put a
unique two-channel 8-bit analog-to-digital converter on
the same NMOS chip as the computer. letting the chip
interface directly with analog transducers.

Family Overview

Pinout diagrams for the 8051. 8751. and 8031 are shown
in Figure I. The devices include the following features:
• Single-supply 5 volt operation using HMOS technology.
• 4096 bytes program memory on-chip (not on 8031).
• 128 bytes data memory on-chip.
• Four register banks.
• 128 User-defined software flags.
• 64 Kilobytes each program and external RAM
addressabifity.
• One microsecond instruction cycle with 12 MHz
crystal.
• 32 bidirectional I/O lines organized as four 8-bit
ports (16 lines on 8031).
• Multiple mode. high-speed programmable Serial
Port.
• Two mUltiple mode. 16-bit Timer/Counters.
• Two-level prioritized interrupt structure.
• Full depth stack for subroutine return linkage and
data storage.
• Augmented MCS-48'· instruction set.
• Direct Byte and Bit addressability.
• Binary or Decimal arithmetic.
• Signed-overflow detection and parity computation.
• Hardware Multiple and Divide in 4 usec.
• Integrated Boolean Processor for control applications.
• Upwardly compatible with existing 8048 software.

Now three new high-performance single-chip microcomputers--the Intel® 8051, 8751, and 8031-extend the
advantages of Integrated Electronics to whole new product areas. Thanks to Intel's new HMOS technology. the
MCS-51'· family provides four tlnes the program
memory and twice the data memory as the 8048 on a
single chip. New I/O and peripheral capabilities both
increase the range of applicability and reduce total system
cost. Depending on the use. processing throughput
increases by two and one-half to ten times.
This Application Note is intended to introduce the reader
to the MCS-51'· architecture and features. While it does
not assume intimacy with the MCS-48'· product line on
the part of the reader, he/she should be familiar with

AFN-01502A-04

10-2

ware application examples illustrate many of the concepts.
Several isolated tasks (rather than one complete system
design example) are presented in the hope that some of
them will apply to the reader's experiences or needs.

All three devices come in a standard 40-pin Dual InLine Package, with the same pin-out, the same timing,
and the same electrical characteristics. The primary
difference between the three is the on-chip program
memory-different types are offered to satisfy differing
user reqUirements.

A document this short cannot detail all of a computer
system's capabilities. By no means will all the 80S I instructions be demonstrated; the' intent is to stress new or
unique MCS-Sl '" operations and instructions generally
used in conjunction with each other. For additional hardware information refer to the Intel MCS-51'· Family
User's Manual, publication number 121517. The assembly
language and use of ASM51, the MCS-51'" assembler,
are further described iii the MCS-51'· Macro Assembler
User's Guide, publication number 9800937.

The 87S1 provides 4K bytes of ultraviolet-Erasable,
Programmable Read Only Memory (EPROM) for
program development, prototyping, and limited production runs. (By convention, I K means 2'0 = 1024.
Ik-with a lower case "k"-equals 10.1 = 1000.) This part
may be individually programmed for a specific application using Intel's Universal PROM Programmer (UPP).
If software bugs are detected or design specifications
change the same part may be "erased" in a matter of
minutes by exposure to ultraviolet light and reprogrammed with the modified code. This cycle may be
repeated indefinitely during the design and development
phase.

The next section reviews some of the basic concepts
of microcomputer design and use. Readers familiar
with the 8048 may wish to skim through this section
or skip directly to the next, "ARCHITECTURE AND
ORGANIZATION."

The final version of the software must be programmed
into a large number of production parts. The 80S1 has
4K bytes of ROM which are mask-programmed with the
customer's order when the chip is built. This part is considerably less expensive, but cannot be erased or altered
after fabrication.

Microcomputer Background Concepts
Most digital computers use the binary (base 2) number
system internally. All variables, constants, alphanumeric
characters, program statements, etc., are represented by
groups of binary digits ("bits"), each of which has. the
value 0 or I. Computers are classified by how many bits
they can move or process at a time.

The 8031 does not have any program memory on-chip,
but may be used with up to 64K bytes of external standard
or multiplexed ROMs, PROMs, or EPROMs. The 8031
fits well in applications requiring significantly larger or
smaller amounts of memory than the 4K bytes provided
by its two siblings.

The MCS-51'" microcomputers contain an eight-bit
central processing unit (CPU). Most operations process
variables eight bits wide. All internal RAM and ROM,
and virtually all other registers are also eight bits wide.
An eight-bit ("byte") variable (shown in Figure 2) may
assume one of 28 = 256 distinct values, which usually
represent integers between 0 and '2SS. Other types of
numbers, instructions, and so forth are represented by
one or more bytes using certain conventions.

(The 80S I and 87S1 automatically access external program memory for all addresses greater than the 4096 bytes
on-chip. The External Access input is an override for
all internal program memory-the 80S1 and 87S1 will
each emulate an 8031 when pin 31 is low.)
Throughout this Note, "80SI" is used as a generic term.
Unless specifically stated otherwise, the point applies
equally to all three components. Table I summarizes the
quantitative differences between the members of the
MCS-48'· and MCS-Sl'" famifies.

For example, to represent positive and negative values,
the most significant bit (D7) indicates the sign of the other
seven bits-O if positive, I if negative-allowing integer
variables. between -128 and +127. For integers with
extremely large magnitudes, several bytes are manipulated together as "multiple precision" signed or unsigned
integers-16, 24, or more bits wide.

The remainder of this Note discusses the various MCS-Sl'"
features and how they can be used. Software and/or hard-

Table 1. Features of Intel's Single-Chip Microcomputers
EPROM
Program
Memory
-

8748

8751

ROM
Program
Memory
8021
8022
8048
8049
8051

External
Program
Memory
-

8035
8039
8031

Program
Memory
(Int/Max)

Data
Memory
(Bytes)

Instr.
Cycle
Time

Inputl
Output
Pins

Interrupt
Sources

Reg.
Banks

IKjlK
2K/2K
IK/4K
2K/4K
4K/64K

64
64
64
128
128

8.4I'Sec
8.41'Sec
2.51'Sec
1.361'Sec
1.0 "Sec

21
28
27
27
32

0
2
2
2
5

I
I
2
2
4
AFN-01S02A-05

10-3

a single character, and a word or sequence of letters may
be represented by a series (or "string") of bytes, Since the
ASCII code only uses 128 characters, the most significant
bit of the byte is not needed to distinguish between characters. Often 07 is set to 0 for all characters. In some
coding schemes, 07 is used to indicate the "parity" of the
other seven bits-set or cleared as necessary to ensure
that the total number of "I" bits in the eight-bit code is
even ("even parity") or odd ("odd parity"). The 8051
includes hardware to compute parity when it is needed,

The letters "MCS" have traditionally indicated
a system or family of compatible Intel® microcomputer components, including CPUs, memories, clock generators, I/O expanders, and so
forth. The numerical suffix indicates the microprocessor or microcomputer which serves as
the cornerstone of the family.. Microcomputers
in the MCS-48'· family currently include the
8048-series (8035,8048, & 8748), the 8049-series
(8039 & 8049), and the 8021 and 8022; the
family also includes the 8243, an I/O expander
compatible with each of the microcomputers.
Each computer's CPU is derived from the 8048,
with essentially the same architecture, addressing modes, and instruction set, and a single
assembler (ASM48) serves each.

A computer program consists of an ordered sequence of
specific, simple steps to be executed by the CPU one-ata-time, The method or sequence of steps used collectively
to solve the user's application is called an "algorithm,"
The program is stored inside the computer as a sequence
of binary numbers, where each number corresponds to
one of the basic operations ("opcodes") which the CPU
is capable of executing, In the 8051, each program
memory location is one byte. A complete instruction
consists of a sequence of one or more bytes, where the
first defines the operation to be executed and additional
bytes (if needed) hold additional information, such as
data values or variable addresses. No instruction is longer
than three bytes.

The first members of the MCS-51'· family are
the 8051, 8751, and 8031. The architecture of
the 8051-series, while derived from the 8048,
is not strictly compatible; there are more
addressing modes, more instructions, larger
address spaces, and a few other hardware differences. In this Application Note the letters
"MCS-51" are used when referring to architectural features of the 8051-series-features
which would be included on possible future
microcomputers based on the 8051 CPU. Such
products could have different ,amounts of
memory (as in the 8048/8049) or different
peripheral functions (as in the 8021 and 8022)
while leaving the CPU and instruction set
intact. ASM51 is the assembler used' by all
micr,ocomputers in the 8051 family,

The way in which binary opcodes and modifier bytes are
assigned to the CPU's operations is called the computer's
"machine language," Writing a program directly in
machine language is time-consuming and tedious, Human
beings think in words and concepts rather than encoded
numbers, so each CPU operation and resource is given a
name and standard abbreviation ("mnemonic"), Programs
are more easily discussed using these standard mnemonics,
or "assembly language," and may be typed into an Intel®
Intellec® 800 or Series II® microcomputer development
system in this form. The development system can mechanically translate the program from assembly language
"source" form to machine language "object" code using a
program called an "assembler." The MCS-5I'· assembler
is called ASM51.

Two digit decimal numbers may be "packed" in an eightbit value, using four bits for the binary code of each digit.
This is called Binary-Coded Decimal (BCD) representation, and is often used internally in programs which
interact heavily with human beings,

There are several important differences between a com- puter's machine language and the assembly language used
as a tool to represent it. The machine language or instruction set is the set of operations which the CPU can
perform while a program is executing ("at run-time"), and
is strictly determined by the microcomputer hardware
design.

Alphanumeric characters (letters, numbers, punctuation
marks, etc.) are often represented using the American
Standard Code for Information Interchange (ASCII)
convention, Each character is associated with a unique
seven-bit binary number. Thus one byte may represent

,05

The assembly language is a standard (though more-orless arbitrary) set of symbols including the instruction set
mnemonics. but with additional features which further
simplify the program design process, For example.
ASM51 has controls for creating and formatting a program listing, and a number of directives for allocating
variable storage and inserting arbitrary bytes of data into
the object code for creating tables of constants.

Figure 2. Representation of Bits Within an Eight-Bit
"Byte" (Value shown = 01010001 Binary =
81 decimal).

AFN-01502A-06

10-4

assembly language by a series of ones and zeros
(naturally), followed by the letter "B" (for Biflary); octal
numbers as a series of octal digits (0-7) followed by th'e
letter "0" (for Octal) or "Q" (which doesn't stand for anything, but looks sort of like an "0" and is less likely
to be confused with'a zero).

In addition, ASM51 can perform sophisticated mathematical operations, computing addresses or evaluating
arithmetic expressions to relieve the programmer from
this drudgery. However, these calculations can only use
information known at "assembly time."
For example, the 8051 performs arithmetic calculations
at run-time, eight bits at a time. ASM51 can do similar
operations 16 bits at a time. The 8051 can only do one
simple step per instruction, while ASM51 can perform
complex calculations in each line of source code. How~
ever, the operations performed by the assembler may only
use parameter values fixed at assembly-time, not variables
whose values are unknown until program execution
begins.

Hexadecimal numbers are represented by a series of hexadecimal digits (O-9,A-F), followed by (you guessed it) the
letter "H." A "hex" number must begin with a decimal
digit; otherwise it would look like a user-defined symbol
(to be discussed later). A "dummy" leading zero may be
inserted before the first digit to meet this constraint. The
character string "BACH" could be a legal label for a
Baroque music synthesis routine; the string "OBACH" is
the hexadecimal constant BAC'6' This is a case where
adding 0 makes a big difference.

For example, when the assembly language source line,
ADD

A,#(LOOP_COUNT + I) * 3

Decimal numbers are represented by a sequence of decimal
digits, optionally followed by a "D." If a number has no
suffix, it is assumed to be decimal-so it had better not
contain any non-decimal digits. "OBAC" is not a legal
representation for anything.

is assembled, AS M51 will find the value of the previously-defined constant "LOOP_COUNT" in an internal
symbol table, increment the value, mUltiply the sum by
three, and (assuming it is between -256 and 255 inclusive)
truncate the product to eight bits. When this instruction
is executed, the 8051 ALU will just add that resulting
constant to the accumulator.

When an ASCII code is needed in a program, enclose the
desired character between two apostrophes (as in 'W) and
the assembler will convert it to the appropriate code (in
this case 23H). A string of characters between apostrophes is translated into a series of constants; 'BACH'
becomes 42H, 41H, 43H, 48H.

Some similar differences exist to distinguish number
system ("radix") specifications. The 8051 does all computations in binary (though there are provisions for then
converting the result to decimal form). In the course of
writing a program, though, it may be more convenient
to specify constants using some other radix, such as base
Hr. On other occasions, it is desirable to specify the ASCII
code for some character or string of c'haracters without
refering to tables. ASM51 allows several representations
for constants, which are converted to binary as each
instruction is assembled.

These same conventions are used throughout the associated Intel documentation. Table 2 illustrates some of the
different number formats.
2. ARCHITECTURE AND ORGANIZATION
Figure 3 blocks out the MCS-51'· internal organization.
Each microcomputer combines a Central Processing
Unit, two kinds of memory (data RAM plus program
ROM or EPROM), Input/Output ports"and the mode,

For example, binary numbers are represented in the

Table 2. Notations Used to Represent Numbers
Bit Pattern

Binary

Octal

HexaDecimal

OQ
·IQ

OOH
OIH

Decimal

,0
+1

00000000
00000001

OB
IB

...

00000111
00001000
00001001
00001010

IIIB
10008
100IB
10 lOB

7Q
IOQ
IIQ
12Q

07H
08H
09H
OAH

7
8
9
10

00 0 0 1 1 1 1
00010000

II liB
10000B

17Q
20Q

OFH
IOH

15
16
127
128
129

+127
-128
-127
-2
-I

...............

...............
...............

. ..
. ..

...

0
I

'Signed
Decimal

1 1 1 1 1 1
10000000
10000001

IIIIIIIB
100000008
1000000lB

I77Q
200Q
20lQ

7FH
80H
81H

...

. ..

1 1 1 1 I 1 I 0
1 1 1 II 1 1 1

111111 lOB
IIIIIIIIB

376Q
377Q

OFEH
OFFH

254
255

...............

........

...

....

+7
+8
+9
+10

. ...

+15
+16

. ...

....

AFN-01S02A-07

10-5

TMOD
TlO
THO
Tll

SERIAL

PORT

PORT 3

INTERRUPT
CONTROL

THI
TIMER
CONTROL

Figure 3. BI.ock Diagram of 8051 Internal Structure

status, and data registers and random logic needed for
a variety of peripheral functions. These elements communicate through an eight-bit data bus which runs
throughout the chip, somewhat akin to indoor plumbing.
This bus is buffered to the outside world through an I/O
port when memory or I/O expansion is desired.
Let's summarize what each block does; later chapters dig
into the <;:PU's instruction set and the peripheral registers
in much greater detail.
Central Processing Unit

The CPU is the "brains" of the microcomputer, reading
the user's program and executing the instructions stored
therein. Its primary elements are an eight-bit Arithmetic/
Logic Unit with associated registers A, B, PSW, and SP,
and the sixteen-bit Program Counter and "Data Pointer
registers.
M

AFN-01502A~08

10-.6

Arithmetic Logic Unit

•
•
•
•
•

The ALU can perform (as the name implies) arithmetic
and logic functions on eight-bit variables. The former
include basic addition, subtraction, mUltiplication, and
division; the latter include the logical operations AND,
OR, and Exclusive-OR, as well as rotate, clear, complement, and so forth. The ALU also makes conditional
branching decisions, and provides data paths and temporary registers used for data transfers within the system.
Other instructions are built up from these primitive fUnctions: the addition capability can increment registers or
automatically compute program. destination addresses;
subtraction is also used in decrementing or comparing the
magnitude of two variables.

Arithmetic Operations
Logical Operations for Byte Variables
Data Transfer Instructions
Boolean Variable ManipUlation
Program Branching and Machine Control

MCS_48™ programmers perusing Table 4 will notice the
absence of special categories for Input/Output, Timer/
Counter, or Control instructions, These functions are all
still provided (and indeed many new functions are added),
but as special cases of more generalized operations in
other categories. To explicitly list all the useful instructions involving I/O and peripheral registers would require
a table approximately four times as long,

Thes'e primitive operations are automatically cascaded
and combined with dedicated logic to build complex
instructions such as incrementing a sixteen-bit register
pair. To execute one form of the compare instruction, for
example, the 8051 increments the program counter three
times, reads three bytes of program memory, computes a
register address with logical operations, reads internal
data memory twice, makes an arithmetic comparison of
two variables, computes a sixteen-bit destination address,
and decides whether or not to make a branch-all in two
microseconds!
An important and unique feature of the MCS-51 architecture is that the ALU can also manipulate one-bit as
well as eight-bit data types. Individual bits may be set,
cleared, or complemented, moved, tested, and used in
logic computations. While support for a more primitive
data type may initially seem a 'step backwards in an era
of increasing word length, it makes the 8051 especially
well suited for controller-type applications. Such algorithms inherent~1" involve Boolean (true/false) input
and output variables, which were heretofore difficult to
implement with standard microprocessors. These features
are collectively referred to as the MCS_5ITM "Boolean
Processor," and are described in the so-named chapter
,to come.

Observant readers will also notice that all of the 8048's
page-oriented instructions (conditional jumps, JMPP,
MOVP, MOVP3) have been replaced with corresponding
but non-paged instructions. The 8051 instruction set is
entirely non-page-oriented. The MCS_48™ "MOVP"
instruction replacement and all conditional jump instructions operate relative to the program counter, with the
actual jump address computed by the CPU during instruction execution, The "MOVP3" and "JMPP" replacements
are now made relative to another sixteen-bit register,
which allows the effective destination to be anywhere in
the program memory space, regardless of where, the
instruction itself is located, There are even three-byte
jump and call instructions allowing the destination to be
anywhere in the 64K program address space.
The instruction set is designed to make programs efficient
both in terms of code size and execution speed. No
instruction requires more than three bytes of program
memory, with the majority requiring only one or two
bytes. Virtually all instructions execute in either one or
two instruction cycles-one or two microseconds with
a 12-MHz crystal-with the sole exceptions (multiply
and divide) completing in four cycles.

Thanks to this ,powerful ALU, the 8051 instruction set
fares well at both real-time control and data intensive
algorithms. A total of 51 separate operations move and
manipulate three data types: Boolean (I-bit), byte (8-bit),
and address (l6-bit). All told, there are eleven addressing
modes-seven for data, four for program sequence control (though only eight are used by more than just a few
specialized instructions), Most operations allow several
addressing modes, bringing the total number of instructions (operation/addressing mode combinations) to Ill,
encompassing 255 of the 256 possible eight-bit instruction opcodes.
Instruction Set Overview

Table 4 lists these III instructions classified into five
groups:

Many instructions such as arithmetic and logical functions or program control, provide both a short and a long
form for the same operation, allowing the programmer
to optimize the code produced for a sp~cific application.
The 8051 usually fetches two instruction bytes per instruction cycle, so using a shorter form can lead to faster
execution as welL
For example, any byte of RAM may be loaded with a
with a three-byte, two-cycle instruction, but the
commonly used "working regi~ters" in RAM may be
initialized in One cycle with a two-byte form. Any bit
anywhere on the chip may be set, cleared, or complemented by a single three-byte logical instruction using
two cycles. But critical control bits, I/O pins, and software flags may be controlled by two-byte, single cycle
Instructions. While three-byte jumps and calls can "go
anywhere" in program memory, nearby sections of code
may be reached by.shorter relative or absolute versions.
const~nt

AFN-01S02A-09

1,0-7

(MSB)

(LSB)

Symbol Position
CY
PSW.7

Symbol Position Name and Significance
OV
PSW.2' Overflow flag.
Set/cleared by hardware dunng arithmetic instructions to indicate overflow
conditions.

Name and Significance
Carry flag.
Set/cleared by hardware or software
during certain arithmetic and logical
"
instructions.

P
AC

PSW.6

Auxiliary Carry flag.
Set/cleared by hardware during addition
or subtraction instructions to indicate
carry or borrow ~ut of bit 3.

PSw.s

Flag 0
Set/cleared/tested by software as a
user-defined status flag.
'

PSW.I

(reserved)

psw,o

Parity flag.
Set/cleared by hardware each instruction cycle to indicate an odd / even
number of "one" bits in the accumulator. i.e .• even parity.

Note-

the contents of (RSI. RSO) enable the
working register banks as follows:
(O.O)~ Bank

RSI

PSW.4

PSW.3

(O.I)~Bank

0
I

(1.0)~Bank 2
3

(I.I)~Bank

(OOH-07H)
(OSH-OFH)
(lOH-I7H)
(lSH-IFH)

Figure 4. PSW-Program Status Word Organization

A significant side benefit of an instruction set more
powerful than those of previous single-chip microcomputers is that it is easier to generate applications-oriented
software. Generalized addressing modes for byte and bit
instruction8 reduce the number of source code lines
written and debugged for a given application. This leads
in turn to proportionately lower software costs, greater
reliability, and faster design cycles.

and rotates. The carry also serves as a "Boolean accumulator" for one-bit logical operations and bit manipulation.
instructions. The overflow flag (OV) detects when arithmetic overflow occurs on signed integer operands. making
two's complement arithmetic possible. The parity flag
(P) is updated after every instruction cycle with the evenparity of the accumulator contents.
The, CPU does not control the two register-bank select
bits, RSI and RSO. Rather, they are manipulated by
software to enable one of the four register banks. The
usage of-the PSW flags is demonstrated in the Instruction Set chapter of.this Note.

Accumulator and PSW

The 8051, like its 8048 predecessor, is primarily an
accumulator-based architecture: an eight-bit register
called the accumulator ("A") holds a source operand and
receives 'the result of the arithmetic instructions (addition,
subtraction, multiplication, and division). The accumulator can be the source or destinationJor logical operations
and a number of special data movement, instructions,
including table look-ups and external RAM expansion.
Several functions apply exclusively to the accumulator:
rotates, parity computation, testing for zero, and so on.

Even though the architecture is accumulator-based, provisions have been made to bypass the accumulator in
common instruction situations. Data may be moved from
any location 6n-chip to any register, address, or indirect
address (and vice versa), any register may be loaded with
a constant, etc., all without affecting the accumulator.
Logical operations may be performed against registers or
variables to aIler fields of bits-without using or affecting
the accumulator. Variables may be incremented, decremented, or tested without using the accumulator. Flags
and control bits may be manipulated and tested without
affecting anything else.

Many instructions implicitly or explicitly affect (or are
affected by) several status flags, which are grouped
together to form the Program Status Word shown in
Figure 4.
(The period within entries under the Position column is
called the "dot operator," and indicates a particular bit
position within an eight-bit byte. "PSW.5" specifies bit 5
of the PSW. Both the, documentation and ASM51 use
this notation.)

Other CPU Registers

Aspecial eight-bit register ("B") serves in the execution of
the multiply and divide instructions. This register is used
in conjunction with the accumulator as the second input
operand and to return eight-bits of the result.

The most "active" status bit is called the carry flag (abbreviated "C"). This bit makes possible mUltiple precision
arithmetic operations including addition, subtraction,

The MCS-51 family processors include a hardware stack
within internal RAM, useful for subroutine linkage.
AFN-01502A-10

10-8

passing parameters between routines, temporary variable
storage, or saving status during interrupt service routines.
The Stack Pointer (SP) is an eight-bit pointer register
which indicates the address of the last byte pushed onto
the stack. The stack pointer is automatically i~crelJlented
or decremented on all push or pop instructions and all
subroutine calls and returns. In theory, the stack in the
8051 may be up to a full 128 bytes deep. (In practice, even
simple programs would use a handful of RAM locations
for pointers, variables, and so forth-reducing the stack
depth by that number.) The stack pointer defaults to 7 on
reset, so that the stack will start growing up from location
8, just like in the 8048. By altering the pointer contents the
stack may be relocated anywhere within internal RAM.
Finally, a l6-bit register called the data pointer (OPTR)
serves as a base register in indirect jumps, table look-up
instructions, and external data transfers. The high- and
low-order halves of the data pointer may be manipulated
as separate registers (OPH and OPL, respectively) or
together using special instructions to load or increment
all sixteen bits. Unlike the 8048,look.up tables can there·
fore start anywhere in program memory and be of
arbitrary length.

Memory Spaces

Program memory is separate and distinct from data
memory. Each memory type has a different addressing
mechanism, different control signals, 'and a different
function.
'
The program memory array (ROM or EPROM), like an
elephant, is extremely large and never forgets information, even when power is removed. Program memory is
used for information needed each time power is applied:
initialization values, calibration constants, keyboard
layout tables; etc., as well as the program itself. The program memory has a sixteen-bit address bus; its elements

are addressed using the Program Counter or instructions
which generate a sixteen-bit address.
To stretch our analogy just a bit, data memory is like a
mouse: it is smaller and therefore quicker than program
memory, and it goes into a random state when electrical
power is applied. On-chip data RAM is used for variables
which are determined or may change while the program
is ruiming.
A 'computer spends most of its time manipulating variables, not constants, and a relatively small number of
variables at that. Since eight-bits is more than sufficient
to uniquely address 128 RAM locations, the on-chip
RAM address register is only one byte wide. In contrast
to the program memory, data memory accesses need a
single eight-bit value-a constant or another variableto specify a unique location. Since this is the basic width
of the ALU and the different memory' types, those
resources can be used by the addressing mechanisms,
contributing greatly to the computer's operating efficiency.
The partitioning of program and data memory is extended
to off-chip memory expansion. Each, may be added
independently, and each uses the same address and data
busses, but with different control signals.' External program memory is gated onto the external data bus by the
PSm (Program Store Enable) control output, pin 29.
External data memory is read onto the bus by the RO
output, pin 17, and written with data supplied from. the
microcomputer by the WR output" pin 16. (There is no
control pin to write external program ROM, whichJs by
definition Read Only.) While both types may be expanded
to up to 64K bytes, the external data memory may
optionally be expanded in 256 byte "pages" to preserve
the use of P2 as an I/O port. This is useful with a relatively
small expansion RAM (such as the Intel@ 8155) or for
addressing external peripherals.
Single-chip controller programs are finalized during the
project design cycle, and ar~ not modified after production. Intel's single-chip microcomputers are not ''von
Neumann" architectures common among main-frame
and mini:.computer systems: the MCS-51Tt1 processor
data memory-on-chip and external-may not be used
for program code. Just as there is no write-control signal
for program memory, there is no way for the CPU to
execute instructions out of RAM. In return, this concession allows an architecture optimized for efficient
controller applications: a large, fixed program located in
ROM; a hundred or so variables in RAM, and different
methods for efficiently addressing each.
(Von Neumann machines are helpful for software development and debug. An 8051 system .could be modified to
have a single off-chip memory space by gating together
the two memory-read controls (PSEN and RO) with a
two-input ANO gate (Figure 5). The CPU could then
write data into the common memory array using WIt and
AFN-OI502A-ll

fO-9

'1051

~'ImAII} ~~MORY

till
lID
1IRRt--_
_

IIIIII"IID

ARRAY

~----'

Figure 5. Combining External Program and Data
Memory Arrays

external data transfer instructions, and read instructions
or data with the AND gate output and data transfer or
program memory look-up instructions.)
In addition to the memory arrays, t~re is (yet) another
(albeit sparsely populated) physical address space. Connected to the internal data bus are a score of special~
purpose eight-bit registers scattered throughout the chip.
Some of these-B, sp, PSW, DPH, and DPL-have
been discussed above. Others-I/O ports lind peripheral
functiori registers-will be introduced in the following
sections. Collectively, these registers are designated as the
~special-functjon register" addres~ space. Even the accumulator is assigned a spot in the special-function register
address space for additional flexibility and uniformity. '
Thus, the MCS-Slno'architecture supports ~everal distinct
"physical", address spaces, functionally separated at the
hardware level ,by different addressing mechanisms, read
and write control signals, or both:
•
'.
•
•
•

On-chip program memory;
On-chip data memory;
Off-chip program memory;
Off-chip data memory;
On-chip specfal-function registers.,

What the programmer sees, though, are "logical" address
spaces. For example, as ,far ,as the programmer is
concerned, there is only one type of program memory,
64K bytes in length. :The fact that it is formed by combining on- and off-chip arrays (split 4K/60K on the,80Sl
and 8751) is "invisible" to the programmer; the, CPU
automatically fetches each byte from the appropriate
array, based on its address.
(Presumably, future microcomputers based on' the
MCS-SI'· architecture may have a different physical split, ,
with more or less of the 64K total implemented on-chip.
Using the MCS48'· family as a precedent, the 8048's 4K
potential program address space was split I K/3K betweep
on- and off-chip arrays; the 8049's was split 2K/2K.)
,
Why go into such tedious details a\>out address spaces?
The logical addressing modes are described iri the Instruction Set chapter, in terms of. physical. address spaces.
Understanding their differences now will payoff in understanding and using the chips later. '

Input/Output Ports

The MCS-SI'· I/O port structure is extremely versatile.
The 8051 and 8751 each have 32 I/O pins configured as
four eight-bit parallel ports (PO, PI, P2, and P3). Each pin
will input or output data (or both) under software control, and each may be referenced by a wide repertoire of
byte and bit operations.
In various operating,or expansion modes, some of these
I/O pins are also used for special input or output functions. Instructions which access external memory use
Port 0 as a multiplexed address/data bus: at the beginning
of an external memory cycle eight bits of the address are
output on PO; later data is transferred on the same eight
pins. External data transfer instructions which supply
a sixteen-bit address, and any instruction accessing
external program memory, output the high-order eight
bits on P2 during the access cycle. (The 8031 always uses
the pins of PO and P2 for external addressing, but PI and
P3 are available for standard I/O.)
The eight pins of Port 3 (P3) each have a special function.
Two external interrupts. two counter inputs, two serial
data lines, and two timing control strobes use pins of P3
as de~cribed in Figure 6. Port 3 pins corresponding' to
functions not used are available for conventional I/O.
Even within a si~gle port, I/O functions may be. combined
in many ways: input and output may be performed using
different pins at the same time', or the ~ame pins at different
times; in parallel in some cases, and in serial in others;'as
test pins, or (in the case of Port 3) as additional special
functions.
AFN-01S02A-12

(LSB)

'INT1 ,'NTO , TXO , RXO

Symbol Position Name and Significance
RD
P3.7
Read data control output. Active low
pulse generated by hardware when
external data memory is read.

P3.6

Symbol Position Name and Significance
INTI
P3.3
Interrupt I input pin. Low-level or
falling-edge triggered.

Write data control output. Active low
pulse generated by hardware when
external data memory is written.

P3.5

Timer/counter I external input or test
pin.

P3.4

Timer/counter 0 external input or test
pin.

INTO

P3.2

Interrupt 0 input pin. Low-level or
falling-edge triggered.

TXD

P3.1

Transmit Data pin for serial port in
UART mode. Clock output in shift
register mode.

RXD

P3.0

Receive Data pin for serial port in
UART mode. Data I/O pin in shift
register mode.

Figure 6. P3-Alternate Special Functions of Port 3

software-accessible). These registers are called, naturally
. enough, THO, TLO, THI, and TLI. Each pair may be
independently software programmed to any of a dozen
modes with a mode register designated TMOD (Figure
7), and controlled with register TCON (Figure 8).
The timer modes can be used to measure time intervals,
determine pulse widths, or initiate events, witl) one-microsecond resolution, UP. to a maximum interval of 65,536
instruction cycles (over 65 milliseconds). Longer delays
may easily be accumulated through software. Configured
as a counter, the same hardware will accumulate external
events at frequencies from D.C. to 500 KHz, with up to
sixteen bits of precision.
Serial Port Interface

Until now, microprocessor systems needed peripheral
chips such as timer/counters, USARTs, or interrupt controllers to meet these needs. The 8051 integrates all of
these capabilities on-chip!

Each microcomputer contains a high-speed, full-duplex,
serial port which is software programmable to function
in four basic modes: shift-register I/O expander, 8-bit
UART, 9-bit UART, or interprocessor communications
link. The UART modes will interface with standard I/O
devices (e.g. CRTs, teletypewriters, or modems) at data
rates from 122 baud to 31 kilobaud. Replacing the
standard 12 MHz crystal with a 10.7 MHz crystal allows
110 baud. Even or odd ,parity (if desired) can be included
with simple bit-handling software routines. Inter-processor
communications in distributed systems takes place at 187
kilobaud with hardware for automatic address/data
message recognition. Simple TTL or CMOS shift registers
provide low-cost I/O expansion at a super-fast I Megabaud. The serial port operating modes are controlled by
the contents of register SCON (Figure 9).

Timer/Counters

lriterrupt Capability and Control

There are two sixteen-bit multiple-mode Timer/Counters
on the 8051, each consisting of a "High" byte (corresponding to the 8048 "T" register) and a low byte (similar to the
8048 prescaler, with the additional flexibility of being

(Interrupt capability is generally considered a CPU
function. It is being introduced here since, from an applications point of view, interrupts relate more closely to
peripheral and system interfacing.)

Special Peripheral Functions

There are a few special needs common among controloriented computer systems:
• keeping track of elapsed real-time;
• maintaining a count of signal transitions;
• measuring the precise width of input pulses;
• communicating with other systems or people;
• closely monitoring asynchronous external events.

AFN-01502A-13

10-11

(MSB)

I I I
GATE

CIT

I I I
GATE

CIT

(LSB)

....,..

TIMER 1

TIMER 0

16-bit timer/counter. "THx" and "TLx"
are cascaded; there is no prescaler.

o
GATE

Gating control. When set, Timer/counter
"x" is enabled only while "INTx" pin is
high and "TRx" control bit is set. When
'
cleared, timer/counter is enabled
whenever "TRx" control bit is set.

CjT

Operating Mode
M CS-48 Timer. "TLx" serves as fivebit prescaler.

8-bit auto-reload timer/counter. "THx"
holds a value which is to be reloaded
into "TLx" each time it overflows.
(Timer 0)

Timer or Counter Selector. Cleared for
Timer operation (input from internal
system clock). Set for Counter operation (input from "Tx" input pin).

TLO is an eight-bit timer/
counter controlled by the
standard Timer 0 control
bits.
THO is an eight-bit timer
only controlled by Timer I
control bits.

(Timer 1) Timer/counter I stopped.

Figure 7. TMOD-Timer/Counter Mode Register

(MSB)

(LSB)

I I I I I
Tl'1

TRI

TFO

TRO

lEI

1T1

lEO,

ITO

I
Symbol Position Name and Significance
lEI
TCON.3 Interrupt I Edge flag. Set by hardware
when external interrupt edge detected.
Cleared when interrupt processed.

Symbol Position Name and Significance
TFI
TCON.7 Timer I overflow Flag. Set by hardware
on timer/counter overflow. Cleared
when interrupt processed.
TRI

TCON.6

Timer I Run control bit. Set/cleared
by software to turn timer/counter
on/off.

TFO

TCON.5

Timer 0 overflow Flag. Set by hardware
on timer/counter overflow. Cleared
when interrupt processed.

TRO

TCON.4

Timer 0 Run control bit. Set/cleared by
software to turn timer/counter on/off.

ITI

TCON.2

Interrupt I Type control bit. Set/cleared
by software to specify falling edge/low
level triggered external interrupts.

lEO

TCON.I

Interrupt 0 Edge flag. Set by hardware
when external interrupt edge detected.
Cleared when interrupt processed.

ITO

TCON.O

Interrupt 0 Type control bit. Set/cleared
by software to specify falling edge/low
level triggered external interrupts.

Figure 8. TCON-Tlmer/Counter Control/Status Register

AFN-01502A-14

10·12

(MSB)

Symbol Position Name and Significance
SMO
SCON.7 Serial port Mode control bit O.
Set/cieared by software (see note).

SMI
SM2

REN

TB8

SCON.6
SCON.5

SCON.4

SCON.3

Symbol Position Name and Significance
RB8
SCON.2 Receive Bit 8. Set/cieared by hardware
to indicate state of ninth data bit
received.

Serial port Mode control bit I.
Set/cieared by software (see note).

SCON.I

Serial port Mode control bit 2. Set by
software to disable reception of frames
for which bit 8 is zero.

Transmit Interrupt flag. Set by hardware when byte transmitted. Cleared
by soft ware after servici ng.
.

SCON.O

Received Interrupt flag. Set by hardware when byte received. Cleared by
software after servicing.

Note-

the state of (SMO,SM I) selects:
(O,O)-Shlft regIster 1/0 expansion.
(0,1)-8 bIt UART, variable data rate.
(1,0)-9 bIt UART. fixed data rate.
(1,1)·-9 bIt UART, vanable data rate.

Receiver Enable control bit. Set/cieared
by software to enable/disable serial
data reception.
Transmit Bit 8. Set/cieared by hardware to determine state of ninth data
bit transmitted in 9-bit UART mode.

Figure 9. SCON-Serial Port Control/Status Register

These peripheral functions allow special hardware to
monitor real-time signal interfacing without bothering
the CPU. For example, imagine serial data is arriving from
one CRT while being transmitted to another, and one
timer/counter is tallying high-speed input transitions
while the other measures input pulse widths. During all
of this the CPU is thinking about something else.
But how does the CPU know when a reception, transmission, count, or pulse is finished? The 8051 programmer
can choose from three approaches.
TCON and SCON contain status bits set by the hardware
when a timer overtlows or a serial port operation is completed. The first technique reads the control register into
the accumulator, tests the appropriate bit, and does a
conditional branch based on the result. This "polling"
scheme (typically a three-instruction sequence though
additional instructions to save and restore the accumulator may sometimes be needed) will surely be
familiar to programmers used to multi-chip microcomputer systems and peripheral controller chips. This
process is rather cumbersome, especially when monitoring
multiple peripherals.
As a second approach, the 8051 can perform a conditional
branch. based on the state of any control or status bit or
input pin in a single instruction; a four instruction
sequence could poll the four simultaneous happenings
mentioned above in just eight microseconds.
Unfortunately, the CPU must still drop what it's doing
to test these bits. A manager cannot do his own work
well if he is continuously monitoring his subordinates;
they should interrupt him (or her) only when they need
attention or guidance. So it is with machines: ideally, the
CPU would not have to worry about the peripherals until
they require servicing. At that time, it would postpone the

background task long enough to handle the appropriate
device, then return to the point where it left off.
This is the basis of the third and generally optimal solution, hardware interrupts. The 8051 has five interrupt
sources: one from the serial port when a transmission or
reception is complete; two from the timers when overflows occur, and two from input pins INTO and INTI.
Each source may be independently enabled or disabled
to allow polling on some sources or at some times, and
each may be classified as high or low priority. A high
priority source can Interrupt a low priority service
routine; the manager's boss can interrupt conferences
with subordinates. These options are selected by the interrupt enable and priority control registers, IE and IP
(Figures 10 and II).
Each source has a particular program memory address
associated with it (Table 3), starting at 0003H (as in the
8048) and continuing at -eight-byte intervals. When an
event enabled for interrupts occurs the CPU automatically
executes an internal subroutine call to the corresponding
address . .A user subroutine starting at this location (or
jumped to from this location) then performs the instructions to service that particular source. After completing
the interrupt service routine, execution returns to the
background program.
Table 3. 8051 Interrupt Sources and Service Vectors
Interrupt
Source

Service Routine
Starting Address

(Reset)
External 0
Timer/ Counter 0
External I
Timer/ Counter I
Serial Port

OOOOH
0003H
OOOBH
OOI3H
OOIBH
0023H
AFN-01502A-15

10-13

(LSB)

ET1

EX1

I I I
ETO

EXO

Symbol Position Name and Significance
EA
IE.7
Enable All control bit. Cleared by
software to disable all interrupts,
independent of the state of IE.4-IE.O.

ETl

Symbol Position Name and Significance
EX I
IE.2
Enable External interrupt I control bit.
Set/cleared by software to enable/
disable interrupts from INTl.

IE.6
IE.5

(reserved)
(reserved)

ETO

lE.I

Enable Timer 0 control bit. Set/cleared
by software to enable/disable interrupts
from timer/counter 0

IE.4

Enable Serial port control bit.
Set/cleared by software to enable/
disable interrupts from TI or RI flags.

EXO

IE.O

Enable External interrupt 0 control bit.
Set/cleared by software to enable/
disable interrupts from INTO.

IE.3

Enable TImer I control bit. Set/cleared
by software to enable/disable interrupts
'from timer/counter l.

Figure 10. IE-Interrupt Enable Register

(MSB)

I- I

PT1

PX1

(LSB)

PTO

PXO

Symbol Position
IP.7
IP.6
IP.5

Name and Significance
(reserved)
(reserved)
(reserved)

Symbol Position Name and Significance
PX I
IP.2
Externl\1 interrupt I Priority control
bit. Set/cleared by software to specify
high/low priority interrupts for INTl.

IP.4

Serial- port Priority control bit.
Set/cleared by software to specify
high/low priority interrupts for Serial
port.

PTO

IP.I

Timer 0 Priority control bit.
Set/cleared by software to specify
high/low priority interrupts for
timer/counter O.

PTI

IP.3

Timer I Priority control bit.
Set/cleared by software to specify
high/low priority interrupts for
timer/counter l.

PXO

IP.O

External interrupt 0 Priority control
bit. Set/cleared by software to specify
high/low priority interrupts for INTO.

Figure 11. IP-Interrupt Priority Control Register

AFN-01502A-16

10-14

Table 4. MCS-S1 T. Instruction Set Description
DATA TRANSFER «ont.)

ARITHMETIC OPERATIONS

Mnemonic
ADD
A.Rn
ADD
A.dlrect
A.@R,
ADD
ADD
A.#data
ADDC A.Rn
ADDC A,dlrect
ADDC A.@R,
ADDC A,#data
A.Rn
SUSS
SUSS
A.dlrect
A.@R,
SUBS
A.#data
SUSS
INC
A
INC
Rn
I~C
direct
@R,
INC
A
DEC
DEC
Rn
direct
DEC
@R,
DEC
I'IIC
DPTR
MUL
AB
DlV
AS
DA
A

Byt. Cy<
I
I
2
I
Add indirect RAM to Accumulator
I
I
Add Immediate data to Accumulator
2
I
Add register to Accumulator with Carry
I
I
I
Add direct byte to A with Carry nag
2
Add mdlrect RAM to A with Carry flag
I
I
Add Immediate data to A with Carry nag
2
I
Subtract register from A with Borrow
I
I
Subtract direct byte from A with Borrow
2
I
Subtract IOdlrect RAM from A w, Borrow
I
I
Subtract Immed data from A W Borrow
2
I
Increment Accumulator
I
I
Increment register
I
I
Increment direct byte
I
2
Increment mdlrect RAM.
I
I
Decrement Accumulator
I
I
Decrement register
I
I
Decrement direct byte
2
I
Decrement mdlrect RAM
I
I
Increment Data POlOter
I
2
Multiply A & S
I
4
DIvide A by B
I
4
Decimal Adjust Accumulator
I
I

Description
Add register to Accumll'l.ator
Add direct byte to Accumulator

LOGICAL OPERATIONS

Mnemonic
A~L
A.Rn
A~L
A.dlrect
A.@R,
ANL
A.#data
A~L
A~L
dlrect.A
MIL
dlrect.#data
ORL
A.Rn
A.dlrect
ORL
A.@R,
ORL
ORL
A.#data
dlrect.A
ORL
dlrect.#data
ORI.
XRI.
A.Rn
XRL
A.direct
A.@R,
XRI.
A.#data
XRI.
dlrect,A
XRL
XRL
direct. #da ta
CLR
A
CPI.
A
RL
A
RLC
A
RR
A
RRC
A
SWAP A

Destination
Byte Cy<
AND register to Accumulator
I
I
AND direct byte to Accumulator
I
2
AND mdlrect RAM to Accumulator
I
I
AND Immediate data tn Accumulator
2
I
AND Accumula,tor to direct byte
2
I
AND Immediate data to direct byte
3
2
OR register to Accumuiato-r
I
I
OR dIrect byte to Accumulator
2
I
OR indirect RAM to-Accumulator
I
I
OR Immediate data to Accumulator
2
I
OR Accumulator to direct byte
2
I
OR Immediate data to direct byte
3
2
Excluslve~OR register to Accumulator
I
I
ExclUSive-OR direct byte to Accumulator
2
I
Exciuslve¥OR mdlrect RAM to A
I
I
Excluslve~OR Immedl3te data to A
2
I
Excluslve~OR Accumulator to direct bvte
I
2
ExclUSive-OR unmedtate data to direct
3
2
Clear Accumulator
I
I
Complement Accumulator
I
I
Rotate Accumulator Left
I
I
Rotate A Left through the Carry flag
I
I
Rotate Accumulator Right
I
I
Rotate A Right through Carry flag
I
I
Swap mbbles withm the Accumulator
I
I

DATA TRANSFER

Mnemonic
Description
MOV
A.Rn
Move register to Accumulator
MOY
A.dlrect
Move direct byte to Accumulator
A.@R,
MOV
Move mdlrect RAM to Accumulator
MOV
A.#data
Move Immediate data to Accumulator
MOV
Rn.A
Move Accumulator to register
MOV
Rn.dlrect
Move direct byte to register
MOV
Rn.#data
Move Immediate data to register
MOV
dlrect.A
Move Accumulator to direct byte
dlrect,Rn
MOV
Move register to direct byte
MOV
dlre~t.dlrect
Move direct byte to direct
MOV
dlrect.@RI
Move tndlrect RAM to direct byte
MOV
dlrect.#data
Move Immediate data to direct byte
MOV
@R,.A
Move Accumulator to indirect RAM
MOV
@RI.dlrect
Move direct byte to indirect RAM
@RI,#data
MOV
Move Immediate data to Induect RAM
MOV
DPTR.#dataI6 Load Data Pomter with a 16~blt constant

Mnemonic
MOVC A.@A+DPTR
MOVC A.@A+PC
MOVX A.@R,
MOVX A.@DPTR
MOVX @Ri.A
MOVX @DPTR.A
PUSH direct
POP
direct
XCH
A.Rn
~CH
A.direct
A.@R,
XCH
XCHD A.@R,

Description
Byt. Cy<
Move Code byte relative to DPTR to A
I
2
Move Code byte relative to PC to A
I
2
Move External RAM (8-bat addr) to A
I
2
Move External RAM (I6-bit addr) to A
I
2
Move A to External RA M (8-hlt addrl
I
2
Move A to External RAM (16-blt addr)
I
2
Push direct byte onto stack
2
2
Pop direct byte from stack
2
2
Exchange register with Accumulator
I
I
Exchange direct byte with Accumulator
2
I
Exchange mdlrect RAM with A
I
I
Exchange low-order Digit IOd RAM w/A
I
I

BOOLEAN VARIABLE MANIPlILATION

Mnemonic
CLR
C
CLR
" bit
SETS
C
b,t
SETB
CPL
C
CPL
bit
A~L
Cblt
ANL
C. bit
ORL
C.hlt
ORL
C bit
MOV
Cblt
MOV
blt.C

Description
Clear Carry flag
Clear direct bit
Set Carry flag
Set direct Bit
Complement Carry flag
Complement direct bit
AND direct bit to Carry nag
AND complement of direct bit to Carry
OR direct bit to Carry flag
OR complement of direct bit to Carry
Move direct bit to Carry flag
Move Carry flag to direct bit

Byte eyc
I
I
I
2
I
I
2
I
I
I
I
2

2
2
2
2
2
2

2
2
2
2
I

PROGRAM AND MACHINE CONTROL

Mnemonic
ACALL addrll
LCALL addrl6
RET
RET!
AJMP addrll
LJMP addrl6
SJMP
rei
@A+DPTR
JMP
JZ
rei
JNZ
rei
rei
JC
J~C
rei
JQ
blt.rel
J~S
blt.rel
JSC
blt.rel
CJNE
A.dlrect.rel
CJNE
A'./fdata.rel
CJNE
Rn.#data.rel
CJNE
@RI.#data.rel
DJNZ
Rn.rel
DJ'IIZ
dlrect.rel
~OP

Description
Byte Cyc
Absolute Subroutine Call
2
2
Long Subroutme Call
3
2
Return from subroutme
I
2
Return from mterrupt
I
2
2
Absolute Jump
2
Long Jump
3
2
Short Jump (relative addr)
2
2
Jump indirect relative to the DPTR
I
2
Jump If Accumulator IS Zero
2
2
Jump If Accumulator IS Not Zero
2
2
Jump If Carry flag IS set
2
2
Jump If No Carry flag
2
2
Jump If direct Bit set
3
2
Jump If direct Bit Not set
3
2
Jump If direct Bit IS set & Clear bit
3
2
Compare direct to A & Jump If Not Equal 3
2
Comp Immed to A & Jump If Not Equal
3
2
,Comp Immed to reg & Jump If Not Equal 3
2
2
Comp lmmed to md. & Jump If Not Equal 3
Decrement register & Jump If Not Zero
2
2
Decrement direct & Jump If Not Zero
3
2
No operation
I
I

Note~

Byte Cyc
I
I
2
I
I
I
I
2
I
I

2
2
2
2
3
2
3

2
I
I

2
2
2
2

2
2
3

3. INSTRUCTION SET AND ADDRESSING MODES
The 8051 instruction set is extremely regular. in the sensl'
that most instructions can operate with variables from
several different physical or logical address spaces. Before
getting deeply enmeshed in the instruction set proper, it
is important to understand the details of the most
common data addressing modes. Whereas Table 4 summarizes the instructions set broken down by functional

on data addressing modes:
Working regl.,ter RO-R 7
Rn
direct
128 Internal RAM locatIOns. any I '0 port. control or status register
@R,
Indirect mternal RAM locatIOn addressed by register RO or RI
#data
-8-bJt constant mcluded In In!'>tructlOn
#data 16 16~blt constant mcluded as byte!'> 2 & 3 of lOst ruction
bit
128 <;,oftware flag!'>. any I 0 pm. control or !'>tatus bit
Note~ on program addressing modes:
addrl6
De!'>tmatton addreo;,s for LCAlL & LJMP may be anywhere wlthm
the M-Kllobyte program memory address space.
addrll
De!oJtmatlOn addres~ for ACALL & AJMP will be wtthtn the same
2-Kllobyte page of program memory a<;, the first byte of the follOWing
In!'>tructlOn
rei
SJMP and all conditional Jumps tnclude an 8-blt offset byte Range IS
+ 127 -128 by teo;, relative to ftrst byte of the follOWing lOst ructIOn

All mnemOniC., copynghted © Intel Corporation 1979

group, this chapter starts with the addressing mode
classes and builds to include the related instructions.
Data Addressing Modes
MCS-51 assembly language instructions consist of an
operation mnemonic and zero to three operands separated
by commas. In two operand instructions the destination
is specified first. then the source. Many byte-wide data
AFN-01502A-17

10-15

operations (such as ADD or MOY) inherently use the
as a source operand and/or to receive the
result. For the sake of clarity the letter "A" is specified in
the source or destination field in all such instructions.
For example, the instruction,
accum~lator

ADD

hardware reset enables register bank 0; to select a
different bank the programmer modifies PSW bits 4 and
3 accordingly.
'
Example 2-Selecting Alternate Memory Banks
psw, .000100008

I'IOV

will add the variableto the accumulator, leaving
the sum in the accumulator.
The operand designated '''' above may use any
of four common logical addressing modes:
,. Register-one of the working registers in the currently enabled bank.
• Direct-an internal RAM location, I/O port, or
special-function register.
• Register-indirect-an internal RAM location,
pointed to by a working register.
• Immediate data-an eight.. bit constant incorporated
into the instruction.
The first three modes provide access to the internal RA M
and Hardware Register address spaces, and may therefore
be used as source or destination operands; the last mode
accesses program memory and may be a source operand
only. _
(It is hard to show a "typical application" of any instruction without involving instructions not yet described. The
following description:; use only the self-explanatory ADD
and MOY instructions to demonstrate how the four
addressing modes are specified and used. Subsequent
examples will become increasingly complex.)
Register Addressing

The 8051 programmer has access to eight "working registers," numbered RO-R7. The least-significant three-bits of
the instruction opcode indicate one register within this
logical address space. Thus, a function code and operand
address can be combined to form a short (one byte)
instruction (Figure 12.a).
The 805 I assembly language indicates register addressing
with the symbol Rn (where n is from 0 to 7) or with a
symbolic name previously defined as a register by the
EQUate or SET directives. (For more information on
assembler directives see the Macro Assembler Reference
Manual.)

SELECT BAM'. 2

Register addressing in the 8051 is the same as in the 8048
family, with two enhancements: there are four banks
rather than one or two, and 16 instructions (rather than
12) can access them.
Direct Byte Addressing

Direct addressing can access anyon-chip variable or
hardware register. An additional byte appended to the
opcode specifies the location to be used (Figure 12.b).
Depending on the highest order bit of the direct address
byte, one of two physical memory spaces is selected.
When the direct address is between 0 and 127 (OOH-7FH)
one of the 128 low-order on-chip RAM locations is used.
(Future microcomputers based on the MCS-5I'· architecture may incorporate more than 128 bytes of on-chip
RAM. Even if this is the case, only the low-order 128
bytes will be directly addressable. The remainder wouldbe accessed indirectly or via the stack pointer.)
Example 3-Adding RAM Location Contents
,DrRADR ADD CONTENTS OF RA" LOCATIQN 4'lH
TO CONTENTS OF RAM I-OCATION 40H
DIRADR

1"I0V
ADD

!'tov

At 40H
A,4tH
40H. fit,

All I/O ports and special function, control, or status
registers are assigned addresses between 128 and 255
(80H-OFFH). When the direct address byte is between
these limits the corresponding hardware register is
accessed. For example, Ports 0 and I are assigned direct
addresses 80H and 90H, respectively. A complete list is
presented in Table 5. Don't waste your time trying to
memorize the addresses in Table 5. Since programs using
absolute addresses for function registers would be difficult
to write or understand, ASM51 allows and understands
the abbreviations listed instead.
Example

4 - Adding Input Port Data to Output Port
Data
• PRTADR ADD DATA INPUT ON PORT 1
TO DATA PREVIOUSLY OUTPUT
ON PORT 0

Example I-Adding Two Registers Together

PRTADR

TO CONTENTS OF REGISTER 0

REGADR

MOV

A. AO

ADD
MOV

A.Rt
RO. fit,

f10V

A. PO

ADD

IA. Pi
PO. A

..ov

,REGAOR ADD CONTENTS OF REGISTER 1

There are four such banks of working registers, only one
of which is active at a time. Physically, they occupy the
first 32 bytes of on-chip data RAM (addresses 0-1 FH).
PSW bits 4 and 3, determine which bank is active. A

Direct ,addressing allows all special-function registers in
the 805 I to be read, written, or used as instruction
operands. In general, this is the only method used for
accessing I/O ports and special-function registers. If direct
addressing is used with special-function register addresses
other than those listed, the result of the instruction is
undefined.
AFN-015D2A-18

, 10-16

The 8048 does not have or need any generalized direct
addressing mode, since there are only five special registers
(BUS, PI, P2, PSW, & T) rather than twenty. Instead, 16
special 8048 opcodes control output bits or read or write
each register to the accumulator. These functions are all
subsumed by four of the 27 direct addressing instructions
of the 8051.

Table 5. 8051 Hardware Register Direct Addresses
Register

Address
80H"
81H
82H
83H
88H'
89H
8AH
8BH
8CH
8DH
90H*
98H*
99H
OAOH'
OA8H'
OBOH'
OB8H"
ODOH*
OEOH*
OFOH*

SP
DPL
DPH
TCON
TMOD
TLO
TLI
THO
THI
PI
SCON
SBUF
P2
IE
P3
IP
PSW
ACC
B

Function
Port 0
Stack Pointer
Data Pointer (Low)
Data Pointer (High)
Timer register
Timer Mode register
Timer 0 Low byte
Timer I Low byte
Timer 0 High byte
Timer I High byte
Port I
Serial Port Control register
Serial Port data Buffer
Port 2
Interrupt Enable register
Port 3
Interrupt Priority register
Program Status Word
Accumulator (direct address)
B register

Indirect addressing on the 8051 is the same as in the
8048 family, except that all eight bits of the pointer register
contents are significant; if the contents point to a nonexistent memory location (i.e., an address greater than
7FH on the 8051) the result of the instruction is undefined.
(Future microcomputers based on the MCS-51'" architecture could implement additional memory in the
on-chip RAM logical address space at locations above
7FH.) The 8051 uses register-indirect addressing for five
new instructions plus the 13 on the 8048.

Immediate Addressing
When a source operand is a constant rather than a variable (i.e.-the instruction uses a value known at assembly
time), then the constant can be incorporated into the
instruction. An additional instruction byte specifies the
value used (Figure 12.d).
The value used is fixed at the time of ROM manufacture
or EPROM programming and may not be altered during
program execution. In the assembly language immediate
operands are preceded by a number sign ("#"). The
operand may be either a numeric string, a symbolic
variable, or an arithmetic expression using constants.
Example

6-Adding Constants Using Immediate
Addressing
,IMMAOR ADO THE CONSTANT 12 (DECIMAL)
TO THE CONSTANT 34 (DECIMAL)
LEAVE SUM IN ACCUMULATOR

. =bit addressable register.

IMMAOR

MOV
ADD

A. tU2
A, .34

The preceding example was included for consistency; it
has little practical value. Instead, ASM51 could compute
the sum of two constants at assembly time.

How can you handle variables whose locations in RAM
are determined, computed, or modified while the program
is running? This situation arises when manipulating
sequential memory locations, indexed entries within tables
in RAM, and multiple precision or string operations.
Register or Direct addressing cannot be used, since their
operand addresses are fixed at assembly time.

Example

7 - Adding Constants Using AS M 51
Capabilities
• ASMSUM LOAD Ace WITH THE SUM OF
THE CONSTANT 12 (DEC IMAL) AND
THE CONSTANT 34

ASMSUM

The 8051 solution is "register-indirect RAM addressing."
RO and R I of each register bank may operate as index
or pointer registers, their contents indicating an address
into RAM. The internal RAM location so addressed is
the actual operand used. The least significant bit of the
instruction opcode determines which register is used as
the "pointer" (Figure 12.c).

MDV

(DEC IMAL)

A •• ( 12+34)

a.) Register Addressing:

ADD

A,R

b.) Direct Addressing:

ADD

In the 8051 assembly language, register-indirect addressing
is represented by a commercial "at" sign ("@") preceding
RO, R I, or a symbol defined by the user to be equal to
ROorR!.

I : : +e+ : : I, I

Example 5 - Indirect Addressing

d.) Immediate Addressing:

direct

c.) Register-Indirect AddreSSing:

ADD

A,@R

, JNOADR ADD CONTENTS OF MEMORY LOCATION

ADDRESSED BY REGISTER 1
TO CONTENTS OF RAM LOCATION
ADDRESSED BY REG I srER 0

I NOAOR

MOY

A,@RO

ADD
MOV

A.@R1
@RO.A

ADD

A,#

data

Figure 12. Data Addressing Machine Code Formats

10-17

AFN-01502A-19

Addressing Mode Combinations

The above examples all demonstrated the use of the four
data-addressing modes in two-operand instructions
(MOY, ADD) which use the accumulator as one
operand. The operations ADDC, SUBB, ANL, ORL,
and XRL (all to be discussed later) could be substituted
for ADD in each example. The first three modes may be
also be used for the XCH operation or, in combination
with the Immediate Addressing mode (and an additional
byte), loaded with a constant. The one-operand
instructions INC and DEC, DJNZ, and CJNE may all
operate on the accumulator, or may specify the Register,
Direct, and Register-indirect addressing modes.
. Exception: as in the 8048, DJNZ cannot use the
accumulator or indirect addressing. (The PUSH and
POP operations cannot inherently address the
accumulator as a special register either. However, all
three can directly address the accumulator as one of the
twenty special-function registers by putting the symbol
"ACC" in the operand field.)
Advantages of Symbolic Addressing

Like most assembly or higher-hivel programming
languages, AS MSI allows instructions or variables to be
given appropriate, user~defined symbolic names. This is
done for instruction lines by putting a label followed by a
colon (":") before the instruction proper, as in the above
examples. Such symbols must start with an alphabetic
character (remember what distinguished BACH from
OBACH?), and may include any combination of letters.
numbers. question marks ("?") and underscores ("":'). For
very long names only the first 31 characters are relevant.
Assembly language programs may intermix upper- and
lower-case letters arbitrarily, but ASMSI converts both
to upper-case. For example. ASM51 will internally
process an "I" for an "i" and. of course. "A_TOOTH" for
"a_tooth."
The underscore character makes symbols easier to read
and can eliminate potential ambiguity (as in the label for
a subroutine to switch two entires on a stack,
"S_EXCHANGE"). The underscore is significant. and
would distinguish between otherwise-identical character
strings.
ASM51 allows all var,iables (registers. ports. internal! or
external RAM addresses, constants. etc.) to be assigned
labels according to these rules with the EQUate or SET
directives.
Example

8 -Symbolic Addressing of Yariables
Defined as RAM Locations
VAR 0

SET

20H

VA()

SET

21H

: SYMB t ADD CONTENTS OF VAR 1
TO CONTENTS OF VAR _ 0
SYMB_l

MOV
ADD
MOV

A, VAR_O

A. VAR_l
VAR_O. A

Notice from Table 4 that the MCS-Sl ,. instruction set has
relatively few instruction mnemonics (abbreviations) for
the programmer to memorize. Different data types or
addressing modes are determined by the operands
specified, rather than variations on the mnemonic. For
example, the mnemonic "MOY" is used by 18 different
instructions to operate on three data types (bit. byte, and
address). The fifteen versions which move byte variables
between the logical address spaces are diagrammed in
Figure 13. Each arrow shows the' direction of transfer
from source to destination.
Notice also that for most instructions allowing register
addressing there is a corresponding direct addressing
instruction and vice versa. This lets the programmer
begin writing 80S I programs as if (s)he has access to 128
different registers. When the program has evolved to the
point where the programmer has a fairly accurate idea
how often each variable is used. he/she may allocate the
working registers in each bank to the most "popular"
variables. (The assembly cross-reference option will show
exactly how often and where each symbol IS referenced.)
If symbolic addressing is used in writing the source
program only the lines containing the symbol definition
will need to be changed; the assembler will produce the
appropriate instructions even though the rest of the
program is left untouched. Editing only the first two lines
. of Example 8 will shrink the six-byte' code segment
produced in half.
How are instruction sets "counted"? There is
no standard practice; different people assessing the same CPU using different conventions
may arrive at different totals,
Each operation is then broken down according
to the different addressing modes (or combinations of addressing modes) it can accommodate. The "CLR" mnemonic is used by two
instructions with respect to bit variables ("CLR
C" and "CLR bit") and once ("CLR A") with
regards to bytes. This expansion yields the 111
separate instructions of Table 4.
The method used for the MCS-51 ® instruction
set first breaks it down into "operations": a
basic function applied to a single data type. For
example, the four versions of the ADD instruction are grouped to form one operation - .
addition of eight-bit variables. The six forms of
the ANL instruction for byte variables make up
a different operation; the two forms of ANL
which operate on bits are considered still
another, The MOV mnemonic is used by three
different operation classes, depending on
whether bit, byte, or 16-bit values are affected.
Using this terminology the 8051 can perform
51 different operations.
AFN-01502A-20

10-18

The MCS-SI'· processors detect whether these situations
occur and indicate such errors with the OV flag. (OV may
be tested with the conditional jump instructions JB and
JNB, described under the Boolean Processor chapter.)
At a hardware level, OV is set if there is a carry out of bit 6
but not out of bit 7, or a carry out of bit 7 but not out of
bit 6. When adding signed integers this indicates a
negative number produced as the sum of two positive
operands, or a positive sum from two negative operands;
on S U BB this indicates a negative result after subtracting
a negative number from a positive number, or' a positive
result when a positive number is subtracted from a
negative number.

Figure 13. Road map for moving data bytes

Example

9 - Redeclaring Example 8 Symbols as
Registers
VAR_O

SET

VAR_l

SET

The ADDC and SUBB instructions incorporate the
previous state of the carry (borrow) flag to allow mUltiple
precision calculations by repeating the operation with
successively higher-order operand bytes. In either case,
the carry must be cleared before the first iteration.

.SVP'1B_2 ADD CONTENTS OF VAR_l
TO CONTENTS OF VAR _ 0
A. VAR_O

A. VAR_l
VAR_O. A

Arithmetic Instruction Usage and DA

ADD, ADDe, SUBB

The' ADD instruction adds a byte variable with the
accumulator, leaving the result i~ the accumulator. The
carry flag is set if there is an overflow from bit 7 and
cleared otherwise. The AC flag is set to the carry-out
from bit 3 for use by the DA instruction described later.
ADDC adds the previous contents of the carry flag with
the two byte variables, but otherwise is the same as ADD.
The SUBB (subtract with borrow) instruction subtracts
the byte variable indicated and the contents of the carry
flag together from the accumulator, and puts the result
back in the accumulator. The carry flag serves as a
"Borrow Required" flag during subtraction operations;
when a greater value is subtracted from a lesser value (as
in subtracting S from I) requiring a borrow into the
highest order bit, the carry flag is set; otherwise it is
cleared.
When performing signed binary arithmetic, certain
combinations of input variables can produce results
which seem to violate the Laws of Mathematics. For
example, adding 7FH (127) to itself produces a sum of
OFEH, which is the two's complement representation of
-2 (refer back to Table 2j! In "normal" arithmetic, two
positive values can't have a negative sum. Similarly, it js
normally impossible to subtract a positive value from a
negative value and leave a positive result - but in two's
complement there are instances where this. too may
happen. Fundamentally, such anomolies occur when the
magnitude of the resulting value is too great to "fit" into
the.seven bits allowed for it; there is no one-byte two's
complement representation for 254, the true sum of 127
and 127.

10-19

If the input data for a multiple pre-cision operation is an
unsigned string of integers, upon completion the carry
flag will be set if an overflow (for ADDC) ,or underflow
(for SUBB) occurs. With two's complement s.igned data
(i.e., if the most significant bit of the original input data
indicates the sign of the string), the overflow flag will be
set if overflow or underflow occurred.
Example IO-String Subtraction with Signed Overflow
Detection
,sueSTR SUBTRACT STRING INDICATED BV Ri
FROM STRING INDICATED BY RO TO
PRECISION INDICATED BY R2
CHECK FOR SIONED UNDERFL.OW WHEN DONE
SUB5TR

SUBSI

CLR
MOV

susa
MOV
INC
INC
DJNZ

IN.
Oil_OK

RET

• BORRDWu 0
C
A. (tRO
,SUBTRACT NEXT PLACE
A.I!Rl
IRO. fit
,BUMP POINTERS
RO
Rl
,LOOP AS NEEDED
Ri2. SUBS1
WHEN DONE. TEST IF OVERFLOW OCCURED
ON LAST ITERATION OF LOOP
aV.OV_OK
(OVERFLOW RECOVERY ROUTINE)
. RETURN

Decimal addition is possible by using'the DA instruction
in conjunction with ADD and/or ADDC. The eight-bit
binary value in the accumulator resulting from an earlier
addition of two variables (each a packed BCD digit-pair)
is adjusted to form two BCD digits of four bits each. If the
contents of accumulator bits 3-0 are greater than nine
(xxxx 101 O-xxxx I III), or if the AC flag had been set, six
is added to the accumulator producing the proper BCD
digit in the low-order nibble. (This addition might itself
set - but would not clear - the carry flag.) If the carry
flag is set, or if the four high-order bits now exceed nine
(10 10xxxx-1111 xxxx), these bits are incremented by six.
The carry flag is left set if originally set or if either
addition of six produces a carry out of the highest-order
bit, indicating the sum of the original two BCD variables,
is greater than or equal to decimal 100.
AFN~O'502A-21

Example II - Two Byte Decimal Add with Registers
and Constants
,DCDADO ADD THE CONSTANT 1,234

(DECIMAL)

TO THE

digits in the accumulator and returns the product of the
two individual digits in packed BCD format in the
accumulator.

CONTENTS OF REGISTER PAIR <:R3> ,.. 0 - b3H)
,DIVIDE PRODUCT BY 10
,A HOLDS" OF TENS, B HOLDS REMAJNpER

MOV
DIV

RET

logical Byte Operations - ANl, ORl, XRl
The instructions ANl, ORL, and XRl perform the
logical functions AND, OR, and 1or Exclusive-OR on the
two byte variables indicated, leaving the results in the
first. No flags are affected. (A word to the wise - do not
vocalize the first two mnemonics in mixed company.)
These operations may use all the same addressing modes
as the arithmetics (ADD, etc.) but unlike the arithmetics,
they are not restricted to operating on the accumulator.
Directly addressed byt~s may be used as the destination
with either the accumulator or a constant as the source.
These instructions are useful f,or clearing (ANl), setting
(ORl), or complementing (XRl) one or more bits in a
RAM, output ports, or control registers. The pattern of
bits to be affected is indicated by a suitable mask byte.
Use immediate addressing when the pattern to be affected
is known at assembly time (Figure 14); use the
accumulator versions when the pattern is computed at
run-time.
1/0 ports are often used for parallel data in formats other
than simple eight-bit bytes. For example, (he low-order
five bits of port I may output an alphabetic character
code (hopefully) without disturbing bits 7-5. This can be a
simple two-step proces~. First, clear the low-order five
pins with an ANl instruction; then set those pins corresponding to ones in the accumulator. (This example
assumes the three high-order bits of the accumulator are
originally zero.)

Example 14 - Reconfiguring Port Size with Logical
Byte Instructions

• DIGIT
SWAP
ADD
MOV

A
A, B
,PACK BCD DIGITS IN ACC
TENONE, A

DUT]X

ANL
ORL

Pl,ll1iOOOOOB
PI. A

,CLEAR BITS,Pl 4 - PI 0
,SET P,l PINS CQRRESONDING TO SET Ace

, BITS

RET

The divide instruction can also separate eight bits of data
in the accumulator into sub-fields. For example, pack.ed
BCD data may be separated into two nibbles by dividing
the data by 16, leaving the high-nibble in the accumulator
and the low-order nibble (remainder) in B. The two digits
may then be operated on individually or in conjunction
with each other. This example receives two packed, BCD

,-__op_co_d_e_--,II
ANL

dIrect address

11L.__m_a_Sk_ _...J
ndata

Figure 14. Instruction Pattern for logical, Operation
Special Addressing Modes
10-20

In this example, low-order bits remammg high may
"glitch" low for one machine cycle, If this is undesirable,
use a slightly different approach, First, set all pins
corres'ponding to accumulator one bits, then clear the
pins corresponding to zeroes in low-o.rder accumulator
bits. Not all bits will change from original to final state at
the same instant, but no bit makes an intermediate
transition.
Example 15 - Reconfiguring I I 0 Port Size without
Glitching
AL T _px

ORL
ORL
ANL

Pl. A
A••U 1100000a
PI, A

RET

Program Control -

Jumps, Calls, Returns

Whereas the 8048 only has a singi.e form of the simple
jump instruction, the 8051 has three. Each causes the
program to unconditionally jump to some other address.
They differ in how the machine code represents the
d-estination address.
LJMP (Long Jump) encodes a sixteen-bit address in the
second and third instruction bytes (Figure IS.a); the
destination may be anywhere in the 64 Kilobyte program
memory address space.
The two-byte AJMP (Absolute Jump) instruction
encodes its destination using the same format as the 8048:
addless bits 10 through 8'form a three bit field in the
opcode and address bits 7 through 0 form the second byte
(Figure 15.b). Address bits 15-12 are unchanged from the
(incremented) contents of the P.C, so AJMPcan only be
used when the destination is known to be within the same
2K memory block. (Otherwise ASMSI will point out the
erroL)
A different two-byte jump instruction is legal with any
nearby destination, regardless of memory block
boundaries or "pages." SJMP (Short Jump) encodes the
destination with a program counter-relative address in
the second byte (Figure 15.c). The CPU calculates the

11'--"-.-"-5---.-.-d'-8--'11

addr? -

addrO

b) Absolule Jump (AJMP addr11):

Like SJ M P. all conditional jump instructions use relative
addressing. JZ (Jump if Zero) and JNZ (Jump if Not
Zero) monitor the state of the accumulator as implied by
their names. while JC (Jump on Carry) and JNC (Jump
on No Carry) test whether or not the carry flag is set. All
four are two-byte instructions. with the same format as
Figure 15.c. JB (Jump on Bit), JNB (Jump on No Bit)and
JBC (Jump on Bit then Clear Bit) can test any status bit
or input pin with a three byte instruction; the second byte
specifies which bit to test and the third gives the relative
offset value.
There are two subroutine-call instructidns. LC ALL
(Long Call) and ACALL (Absolute Call). Each
increments the P.C to the first byte of the following
instruction. then pushes it onto the stack (low byte first).
Saving both bytes increments the stack pointer by two.
The subroutine's starting address is encoded in the same
ways as LJ M P and AJ M P. The generic form of the call
operation is the mnemonic CALL, which ASM51 will
translate into LCALL or ACALL as appropriate.
The return instruction RET pops the high- and low-order
bytes of the program counter successively from the stack.
decrementing the stack pointer by two. Program
execution continues at the address previously pushed: the
first byte of the instruction immediately following the
call.

Secondly. the interrupt logic is disabled from accepting
any other interrupts from the same or lower priority.
After completing the interrupt service routine. executing
an RETI (Return from Interrupt) instruction will return
execution to the point where the background program
was interrupted - just like RET - while restoring the
interrupt logic to its previous state.

c) Short Jump (SJMP rei)

I : : >+0: : :

In keeping with the 8051 assembly language goal of
minimizing the number of instruction mnemonics, there
is a "generic" form of the three jump instructions.
AS M 51 recognizes the mnemonic J M P as a '~pseudo
instruction." translating it into the machine instructions
LJMP. AJMP, or SJMP, depending on the destination
address.

When an interrupt request is recognized by the 8051
hardware. two things happen. Program control is
automatically "vectored" toone of the interrupt service
routine starting addresses by. in effect. forcing the CPU
to process an LCALL instead of the next instruction.
This automatically stores the return address on the stack.
(Unlike the 8048. no status information is automatically
saved.)

a) long Jump (lJMP addr16)
opcode

destination at run-time by adding the signed eight-bit
displacement value to the incremented P.C Negative
offset values will cause jumps up to 128 bytes backwards;
positive values up to 127 bytes forwards. (SJMP with
OOH in the machine code offset byte will proceed with th '
following instruction).

_,'_0'."'0_011'0.-------1

ilL--'

Figure 15. Jump Instruction Machine Code
Formats
10-21

Operate-and-branchinstructions - CJNE, DJNZ
Two groups of instructions combine a byte operation
with a conditional jump based on the results.

CJNE (Compare and Jump if Not Equal) compares two
byte operands and executes a jump if they disagree. The
carry flag is set following the rules for subtraction: if the
unsigned integer value of the first operand is less than
that of the second it is set; otherwise, it is cleared.
However, neither operand is modified.

The dollar sign in this example is a special character
meaning "the address of this instruction." It is useful'in
eliminating instruction labels on the same 'or adjacent
source lines. CJNE and DJNZ (like all conditional
jumps) use program-counter relative addressing for the
destination address.
Stack Operations -

PUSH, POP

The PUSH instruction increments the stack pointer by
one, then transfers the contents of the single byte variable
indicated (direct'addressing only) into the internal RAM
location addressed by the stack pointer. Conversely,
POP copies the contents of the internal RAM location
addressed by the stack pointer to the byte variable
indicated, then decrements the stack pointer by one.

The CJNE instruction provides, in effect, a oneinstruction "case" statement. This instruction may be
executed repeatedly, comparing the code variable to a list
of "special case" value: the code segment following the
instruction (up to the destination label) will be executed
only if the operands match. Comparing the accumulator
or a register to a series of constants is a convenient way to
check for special handling or error conditions; if none of
the cases match the program will continue with "normal"
processing.

(Stack Addressing follows the, same rules, and addresses
the same locations as Register-indirect. Future microcomputers based on the MCS-51'· CPU could have up to
256 bytes of RAM for the stack.)

A typical example might be a word processing device
which receives ASCII characters through the serial port
and drives a thermal hard-copy printer. A standard
routine translates "printing" characters to bit patterns,
but control characters «DEL>' . . .
. or value,
OOH, and processed with the printing characters.

Interrupt service routines must not change any variable
or hardware registers modified by the main program, or
else the program may not resume correctly. (Such a
change might look like a spontaneous random error.)
Resources used or altered by the service routine
(Accumulator, PSW, etc.) must be saved and restored to
their previous value before returning from the service
routine. PUSH and POP provide an efficient and
convenient way to save register states on the stack.

Example 16-Case Statements Using CJNE

Example 18-Use of the Stack for Status Saving on
Interrupts

CHAR

EOU

INTERP

CJNE

CHAR, 17FH. I HlP 1
(SPECIAL ROUTINE FOR RUDOUT CODE)

INTP _1

RET
CJNE

INTP _2

RET
CJNE

• CHARACTER CODE VARIABLE

LOC_TMP EGU
ORG
L.JMP

CHAR •• 07H. INTP .•2

(SPECIAL ROUTINE FOR BELL CODE)
CHAR ••OAH. INTP~.3
(SPECIAL ROUTINE FOR LFCED CODE)

SERVER

RET

CHAR ••ODH. INTP_4
(SPECIAL

INTP _3

C.JNE

INTP _4

RET
CJNE

CHAR •• 1BH. INTP_5

INTP _5

RET
CJNE

CHAR •• 20H. INTP_6

RO~TINE

FOR RETURN CODE)

(SPECIAL ROUTINE FOR ESCAPE CODE)

(SPECIAL ROUTINE FOR SPACE CODE)

INTP _b

RET
JC
MOV

NULL CODE
,PROCESS STANDARD PRINTING
CHARACTER

PRINTC
RET

Example l7'-lnserting

a Software

Delay with DJNZ

CLR
MOV

R2 •• 4~

DVNZ

R2."

SETB

psw

PUSH
PUSH
PUSH

B
DPL
DPH

MOV

psw, .000010008

RETI

DJNZ (Decrement and Jump if Not Zero) decrements
the register or direct address indicated and jumps if the
result is not zero, without affecting any flags. This
provides a simple means for executing a program loop a
given numper of times, or for adding a moderate time'
delay (from 2 to 512 machine cycles) with a single
instruction. For example, a 99-usec. software delay loop
can be added to code forcing an 110 pin low with only
two instructions.

LOC_TI'IP • RESTORE LOCATION COUNTER

ORO
PUSM
PUSH

POP
POP
POP
POP
POP

PRINTC
, JUMP IF CODE> 20H
CHAR •• O ,REPLACE CONTROL CHA'RACTERS WITH

,REMEMBER LOCATION COUNTER
0003M, STARTING ADDRESS FOR INTERRUPT ROUTINE
SERVER, -JUMP TO ACTUAL SERVICE RoqTINE LOCATED
, ELSEWHERE

ACC

OPH
OPL
B
ACC

psw

,SAVE ACCUMULATOR (NOTE' DIRECT ADDRESSING
, NOTATION)
,SAVE B REGISTER
,SAVE DATA POINTER
i

. SELE:CT REGISTER BANK 1

I RESTORE REGISTERS IN REVERSE ORnER

· RESTORE PSW AND RE-SELECT ORIGINAL
, REGISTER BANK
• RETURN TO MAIN PROGRAM,'AND RESTORE
• INTERRUPT LOGIC

If the SP register held I FH when the interrupt was
detected, then while the service routine was in progress
the stack would hold the registers shown in Figure 16; SP
would contain 26H.
The example shows the most general situation; if the
service routine doesn't alter the B-register and data
pointer, 'for example, the instructions saving and
restoring those registers would not be necessary.
The stack may also pass parameters to and from
subroutines: The subroutine can indirectly address the
parameters derived frilm the contents' of the, stack
pointer.
AFN-01502A~24

10-22

If the position of the motor is determined by the contents
of variable POSM I (a byte in internal RAM) and the
position of a second motor on Port 2 is determined by the
data input to the low-order nibble of Port 2, a sixinstruction sequence could update them both.

RAM
AOOR

7FH

26H

OPH

25H

OPL

Example 21- Loading and Unloading Stack Direct
from 1;0 Ports

_(SP)

24H

EGU

23H

ACC

PUSH
CALL

PDSMI
NXTPQS

22H

PSW

POP

POSMt

2'H

PC (HIGH)

20H

PC (LOW)

'FH

Figure 16. Stack contents during interrupt
One advantage here is simplicity. Variables need not be
allocated for specific parameters, a potentially large
number of parameters may be passed, and different
calling programs may use different techniques for
determining or handling the variables.
For example, the following subroutine reads out a
parameter stored on the stack by the calling program,
uses the low order bits to access a local look-up table
holding bit patterns for driving the coils of a four phase
stepper motor, and stores the appropriate bit pattern
back in the same position on the stack before returning.
The accumulator contents are left unchanged.
Example I'f- Passing Variable Parameters to Subroutines Using the Stack
MOV

DEC
DEC
XCH

RO, SP
RO

,ACCESS LOCATION PARAMETER PUSHED INTO

RO
A, @FW

,READ INPUT PARAMETER AND SAVE

ANL

A, .03H

,MASK ALL BUT LOW-ORDER TWO B I T5

ADO

A, *2

,ALLOW FOR OFFSET FROM Move TO TABLE

Move

A, @A+PC ,READ LOOK-UP TABLE ENTRY
A, @RO
,PASS BACII. TRANSLATED VALUE AND RESTORE

•

XCH
RET
STPTBL

DB
DB
DB
DB

NXTPOS

POP

Data Pointer and Table Look-up instructions MOV, INC, MOVC, JMP

OOH

NXTPOS

PI
P2

PUSH
CALL

The data pointer can be loaded with a 16-bit value using
the instruction MOV DPTR, #dataI6. The data used is
stored in the second and third instruction bytes, highorder byte first. The data pointer is incremented by INC
DPTR. A 16-bit increment is performed; an overflow
from the low byte will carry into the high-order byte.
Neither instruction affects any flags.
The MOVC (Move Constant) instructions (MOVC
A,@A+DPTR and MOVC A.@A+PC) read into the
accumulator bytes of data from the program memory
logical address space. Both use a form of indexed
addressing: the former adds the unsigned eight-bit
accumulator contents with the sixteen-bit data pointer
register, and uses the resulting sum as the address from
which the byte is fetched. A sixteen-bit addition IS
performed; a carry-out from the low-order eight bits may
propagate through higher-order bits, but the contents of
the DPTR are not altered. The latter form uses the incremented program counter as the "base" value instead of
the DPTR (figure 17). Again, neither version affects the
flags.

ACCUI'1ULATO~

, Ace

Move A @ A + PC
(LOCAL TABLE
LOOK-UP)

,RETURN TO BACKGROUND PROGRAM

011011118
010111118
10011111B
101011118

,POSITION
,POSITION
,POSITION
,POSITION

0
1
2
3

CLR

Ace

POP

16- BIT

JMP @ A+ OPTR
(GLOBAL INDIRECT
JUMP)

~~~;~'~~RESS
DPTR

~ACC

16-BIT

~~~i~'~~RESS
DPTR

~ACC
L.._ _ _'_6-_BI_T.l1 LOADED INTO PC

A
NXTPQS

Move A @ A+ OPTR
(GLOBAL TABLE
LOOK-UP)

~ACC

L.._ _ _'_6-_BI_T..J1
c)

Example 20-Sending and Receiving Data Parameters
Via the Stack
CALL

L.._ _ _'_S-_BI_T..JI

The background program may reach this subroutine with
several different calling sequences, all of which PUSH a
value before calling the routine and POP the result after.
A motor on Port' I may be initialized by placing the
desired position (zero) on the stack before calling the
subroutine and outputing the results directly to a port
afterwards.

PUSH

1-6-BIT

Figure 17. Operation of MOVC instructions
AFN-01S02A-25

10-23

Each can be part of a three step sequence to access lookup tables in ROM. To use the DPTR-relative version.
load the Data Pointer with the starting address of a lookup table; load the accumull!tor with (or compute) the
index of the entry desired; and execute MOVC
A,@A+DPTR. Unlike the similar MOVP3 instructions
in the 8048. the table may be located anywhere in
program memory. The data pointer may be loaded with a
constant for short tables. Or to allow more complicated
data structures. or tables with more than 256 entries. the
values for DPH and DPL may be computed or modified
with the standard arithmetic instruction set.
The PC-relative version has the advantage of not
affecting the data pointer. Again. a look-up sequence
takes three steps: load the accumulator with the index;
compensate for the offset from the look-up instruction to
the start of the table by adding the number of bytes
separating them to the accumulator; then execute the
MOVC A.@A+PC instruction.
Let's look at a non-trivial situation where this instruction
would be used. Some applications store large multidimensional look-up tables of dot matrix patterns. nonlinear calibration parameters. and so on in linear (onedimensionali) vector in program memory. To retrieve
data from the tables. variables representing matrix
indices must be converted to the desired entry's memory
address. For a matrix of dimensions (MDIMEN x
NDIMEN) starting at address BASE and respective
indices INDEXI and INDEXJ. the address of element
(lNDEXI. INDEXJ) is determined by the formula.
Entry Address = BASE + (NDIMEN x INDEX!),+
INDEXJ
The code shown below can access any array with less than
255 entrIes (i.e .. an I I x21 array with 23 I elements). The
table entries are defined using the Data Byte ("DB")
dire~tive. and will be contained in the assembly object
code as part of the accessing subroutine itself.

There are several different means for ,branching to
sections of code determined or selected at run time. (The
'single destination addresses incorporated into
conditional and unconditional jumps are. of course.
determined at assembly time). Each has advantages for
different applications.
The most common is an N-way conditional jump based
on some variable. with all of the potential destinations
known at assembly time. One of a number of small
routines is selected according to the value of an index
variable determined while the program is running. The
most efficient way to solve this problem is with the
MOVC and an indirect jump instruction. using a short
table of one byte offset values in ROM to indicate the
relative starting addresses of the several routines.
JMP @A+DPTR is an instruction which performs an
indirect jump to an address determined during program
execution. The instruction adds the eight-bit unsigned
accumulator contents with the contents of the sixteen-bit
data pointer. just like MOVC A.@A+DPTR. The
resulting sum is loaded into the program counter and IS
used as the address for subsequent instruction fetches.
Again. a sixteen-bit addition is performed; a carry out
from the low-order eight bits may propagate through the
higher-order bits. In this case. neither the accumulator
contents nor the data pointer is altered.
The example subroutine below reads a byte of RA Minto
the accumulator from one of four alternate address
spaces. as selected by the contents of the variable
MEMSEL. The address of the byte to be read is
determined by the contents of RO (and optionally R 1). It
might find use in a printing terminal application. where
four different model printers all use the same ROM code
but use different types and sizes of buffer memory for
different speeds and options.
Example 23 - N-Way Branch and Computed Jump
Instructions via JMP @ ADPTR

Example 22 - Use of MPY and Data Pointer Instructions to Access Entries from a Multidimensional Look-Up Table in ROM

MEMSEL

EQU

,JUMP _4

MEM5PO

MOV
Mav
Move
,JMP
DB
DB
DB
DB
MoV

A. MEMSEL
OPTR ••.JMPTBL
A. ftA+DPTR
@A+DPTR
MEMSPO-JHPTBL
MEMSP l-.JMPTBL
HEMSP2-JHPTBL
HEMSP3-JMPTBL
A. @RO
,READ FROM INTERNAL RAM

MEMSP 1

MOVX

I'1EMSP2

MOV
DPL. RO
MOV DPH, RI
MQVX
A, ItOPTR • READ FROM 64K BYTES OF EXTERNAL RAM

HEH,SP3

MoV
ANL
ANL
ORL
MOVX

,MATRX1 LOAD CONSTANT READ FROM TWO DIMENSIONAL LOOK-UP
TABLE IN PROGRAM MEMORY INTO ACCUMULATOR
'

USING LOCAL TABLE LOO!('-UP I,NSTRUCl ION,

'Move

A, i!A+PC

,JMPTBL

THE TOTAL NUMBER OF TABLE ENTRIES IS ASSUMEO TO
BE SMALL, I E
LESS THAN ABOUT 2:')0 ENTRIES)
TABLE USED IN THIS EXAMPLE IS ( 11 )( 21 )
DESIRED ENTRY ADDRESS 15 GIVEN BY THE FORMULA,
r (BASE ADDRESS) + (21 X INDEXI) ... 1 (INDEXJJ 1

INDEXI

ECiU

INDEXJ

E(lU

Rb
OJH

MOV

A,INDEXJ

MAlRXl

RET

• FIRST COORDINATE OF ENTRY (a-to)
• SECOND COORDINATE OF ENTRY (P-;!O)

Move, *21
I'M.

A, I NDEX,J
ALLOW FOR I NSTRUCT ION BYTE BETWEEN "Move" AND

ENTRY
INe~

(0.0)
A
A. C!A+PC

DB
DB

• (entrll 0.0)
• tl!ntrll 0.1)
21
22

• (entry 0,20)
• tentrll 1. 0)

• (entry 1,20)

231

• (entrll

DB
DB

A, R 1
1>" .07H
Pl •• 11111000B

Pl. A
A. @RO

• READ FROM 4K BYTES OF EXTERNAL RAM

RET

RET
BASEl

• READ FROM 256 BYTES OF EXTERNAL RAM

RET

ADD

Move'

A. eRo

RET

10.20)

NoJe that this approach is suitable whenever the size of
jump table plus the length of the alternate routines is less
than 256 bytes. The jump table and routines may be
located anywhere in program memory. 'independent of
256-byte program memory pages.
AFN-01502A-26

10-24

For applications where up to 128 destinations must be
selected. all of which reside in the same 2K page of
program memory which may be reached by the two-byte
absolute jump instructions. the following technique may
be usel In the above mentioned printing terminal
example. this sequence could "parse" 128 different codes
for ASCII characters arriving via the 8051 serial port.
Example 24-N-Way Branch with 128 Optional
Destinations '
OPTION

EQU

Jf'IP129

NOV

",..

A. OPTION
A
DPTP. _INSTIL
IA"'DPTR

AJKP
A.JI'IP
AJt'tP

PRDCOO. 128 CONSECUTIVE
PRDCOl. AJttF INST~ucl10NS
pAOC02

/It'"

PRDC]E
PRDC7F

"""
INSTIL

• PWL TlPL v 8'1' 2 FOR 2 BYTE JUfIIP TAIILE
• FIRST ENTRY IN JUf'tP TAHI E
• .IlR'IP INTO .lU'1P TABLE

The destinations in the jump table (PROCOOPROC7F) are not all necessarily unique routines. A large
number of special control codes could each be processed
with their own unique routine. with the remaining
printing characters all causing a branch to a common
routine for entering the character into the output queue.
In those rare situations where even 128 options are
insufficient. or where the destination routines may cross a
2K page boundary, the above approach may be modified
slightly as shown below.
Example 25-256-Way Branch Using Address LookUp Tables
RTEHP

EOU

......P256

PlDY
1'10\1

A.OPTION

CLR

RLe
.INC

INC

OPH

MQY
MOVe
lICH..
INC
I'IOVC
PUSH
I'tOv

RTE", A
A.I,,+OPT"
A. RTEMP
•
A.I""OPTR
Ace
A. RTEMP
A.I"+DPTR
Ace

LOW12B

nQ\IC

PUSH

R7
DPTR. _AORTBl

• FIRST ENTRY IN TABLE OF ADDRESSES

ow
ow

• SAVE ACe FOR HIGH BYTE READ
• READ LOW 8VTE FROI'! ..JUMP TABLE
• gET LOW-ORDER BYTE FRDI'! TABL£

• OET

HIC~H-DRDER

BYTE FRctI TABLE

PRocao

• UP TO 256 CONSECUTIVE DATA

PROCOI

• WORDS INDICATINQ STARTINQ ADDRESSES

PROCFF

0Vf'II'I'f'

CDDE ADDRESS DEFINITIONS N!EDEO BV ABOVE
TWO EXAl'lPLES

PROCOO

NOP
NOP

PRotOl
PROC02
PRobE
PRQC1F

NOP
HOP

PR'PCFF

NaP

Direct Bit AddressIng

A number of instructions operate on Boolean (one-bit)
variables. using a direct bit addressing mode comparable
to direct byte addressing. An additional byte appended to
the opcode specifies the Boolean variable. I/O pin. or
control bit used. The state of any of these, bits may be
tested for "true" or "false" with the conditional branch
instructions JB (Jump on Bit) and JNB (Jump on Not
Bit). The JBC (Jump on Bit/ and Clear) instruction
corpbines a test-for-true with an unconditional clear.
As in direct byte addressing, bit 7 of the address byte
switches between two physical address spaces. Values
between 0 and 127 (00H-7FH) define bits in internal
RAM locations 20H to 2FH (Figure 18a); address bytes
between 128 and 255 (80H-OFFH) define bits in the 2 x
"speciaH"unction" register address space (Figure 18b). If
no 2 x "&pecial-function" register corresponds to the
direct bit address used the result of the instruction is
undefined.
Bits so addressed have many wondrous properties. They
may be set, cleared, or complemented with the two byte
instructions SETB. CLR. or CPL. Bits may be moved to
and from the carry flag with MOV. The logical ANL and
ORL functions may be performed between the carry and
ei~her the addressed bit or its complement.

.MULTIPLY BY 2 FOR 2 BVTE .JVI"IP fAYLE

LOWl2B

THE TWO ACe PUSHES HAVE PRODUCED
/It "RETURN ADDRESS" ON THE STACK WHICH CORRESPONDS
TO THE DESIRED STARTiNQ ADDRESS
IT PlAV 8E REACHED BV POPpi ING fHE STACK
INTO THE PC
RET

AnRt8L

Prior to the introduction of the MCS-5I'M family. nice
number-crunchers made bad bit-bangers and vice versa.
The 8051 is the industry's first single-chip microcomputer designed to crunch and bang. (In some circles.
the latter technique is also referred to as "bit-twiddling".
Either is correct.)

NOP

4. BOOLEAN PROCESSING INSTRUCTIONS
The commonly accepted terms for tasks at either end of
the computational vs. control application spectrum are.
respe~tively. "number-crunching" and "bit-banging".

Bit Manipulation Instructions -

MOV

The "MOV" mnemonic can be used to load an
addressable bit into the carry flag ("MOV C, bit") or to
copy the state of the carry to such a bit ("MOV bit. C").
These instructions are often used for implementing serial
I/O algorithms via software or to adapt the standard I/O
port structure ..
It is sometime~ desirable to "re-arrimge" the orderofI/O
pins because of considerations in laying out printed
circuit boards. When interfacing the 8051 to an
immediately adjacent device with "weighted" input pins,
such as .keyboard column decoder, the corresponding
pins are likely to be not aligned (Figure 19).

There is a trade-off in "scrambling" the interconnections with either interwoven circuit board traces or through
software. This' is extremely cumbersome (if not
impossible) to do with byte-oriented computer
architectures. The 8051's unique ~et of ,Boolean
instructions makes it simple to move individual bits
between arbitrary locations.
AFN-01502A-27

10·25

a.) RAM Bit AddresteS.

b.) Hardware Regl,ter Bit Addre,..,.

RAM
BYTE

01_

7l'H

(MSB)

~.:...

(LSB)

2FH

2EH

2DH

2CH

2BH

2AH

29H

41!

28H

27H

26H

25H

24H

23H

1'0

22H

21H

20H

lFH

(LSB)

(MbB)

Hardware
Register
Symbol

OFfH
B

OFOH

F7 1

OEOH

E1J E61

ODOH

071061051041031021011

OB8H

-1-1-1

Bcl

BBJBA.I

B91 'B8

OSOH

B7 I

B61

B41

B31

Bll

OABH

AF 1

-1-1

AC I AB1AA1 A91 A8

OAOH

A7 I

A6 I

98H

.. '1

SCON

90H

97196195194193192J

88H

89 1

TCON

80H

166

F6 1

F51 F41 F3 1

B51

E41

F21 Fl 1

E31 E21 E l l EO

laolsclaa

B21

19AI

ACC

PSW

Bank 3

18H
17H

I 80

I 8C

I 8B

8A 1

184183182181180

Bank 2

10H
OFH

Bank 1

08H
07H
Bank 0
OOH

Figure 18. Bit Address Maps

Example 26 - Re-ordering I/O Port Configuration
ALE

OUT]Z

PSEN

RRC

MOV

P2 b,·C

RRC

MOV

P2, "C

RRC
MOV

P2.7

RRC
MOV

P26

(LSB)

RRC

MOV

•
•
•

P2 4. C
P2 3. C

P2 2. C

• MOVE ORIGINAL. ACC 0 INTO
I STORE CARRY TO PIN P2b
.110VE ORIGINAL. ACC 1 INTO
• STORE CARRY TO PIN P25
,MOVE ORIGINAL. ·ACC 2 INTO
,STORE CARRY TO PIN P24
,MOVE ORIGINAL. AC,C 3 INn::
,STORE CARRY TO PIN P23
,MOVE ORIGINAL. Ace 4 INTO
,STORE CARRY TO PIN P22

CV
CY
CY
cv
CY

RET

8351
8751

P2.5

P2.4

P2.3

DECODER

P2.2

(MSB)

Solving Combinatorial Logic Equations - ANL, ORL

P2.1
P2.0

Figure

19. "Mismatch" Between 1/0
Decoder

port

and

Virtually all hardware designers are familiar with the
problem of solving complex' functions using
combinatorial logic. The technologies involved may vary
greatly. from multiple contact relay logic. vacuum tubes.
TTL. or CMOS to more esoteric approaches like fluidics.
but in each case the goal is the same: a Boolean
(true/false) function is computed on a number of
Boolean variables.
10-26

b.) Relay logic .

•. ) TTL

CR.

CR2
Q:o (U .(V+W)+(XeY)+Z

Figure 20. Implementations of Boolean functions

Figure 20 shows the logic diagram for an arbitrary
function of six variables named U through Z using
standard logic and relay logic symbols. Each is a solution
of the equation.

INPUT. OUTPUT. LOAD. STORE. etc" instead of the
universal MOV.

Q :: (U • (V + W)) + (X • Y) + Z
(While this equation could be reduced using Karnaugh
Maps or algebraic techniques. that is not the purpose of
this example. Even a minor change to the function
equation would require re-reducing from scratch.)
Most digital computers can solve equations of this type
with standard word-wide logical instructions and
conditional jumps. Still. such software solutions seem
somewhat sloppy because of the many paths through the
program the computation can take.
.
Assume U and V are input pins being read by different
input ports. Wand X are status bits for two peripheral
controllers (read as I/O ports). and Y and Z are software
flags set or cleared earlier in the program. The end result
must be written to an output pin on some third port.
For the sake of comparison we will implement this
function with software drawn from three proper subsets
of the MCS-51'· instruction set. The first two
implementations follow the flow chart shown in Figure
21. Program flow would embark on a route down a testand-branch tree and leaves either the "True" or "Not
True" exh ASAP. These exits then write the output port
with the data previously written to the same port with the
result bit respectively one or zero.
In the first case. we assume there are no instructions for
addressing individual bits other than special flags like the
carry. This is typical of many older microprocessors and
mainframe computers designed for number-crunching.
MCS-51'· mnemonics are used here. though for most
other maGhines the issue would be even further clouded
by their· lise of operation-specific mnemonics like

(CONTINUE)

Figure 21. Flow chart for tree-branching logic'
implementation
AFN-01502A-29

10-27

These instructions may be "strung together~' to simulate a
multiple input logic gate. When finished, the carry flag
contains the result, which may be moved directly to the
destination or output pin. No flow chart is needed - it is
simple to code directly from the logic diagrams in Figure
20.

Example 27 -Software Solution to Logic Function of
Figure 20, Using only Byte-Wide Logical
Instructions
,BFUNC 1 SOLVE A RANDOM LOGIC FUNCTION OF 6
VARIABLES BY LOADING AND MASKING THE APPROPRIATE
BITS IN THE ACCUMULATOR, THEN EXECUTING CONDITIONAL
JUMPS BASED 'ON ZERO CONDITION
R r TI) Sf REAO 1 N Ace
IN8243

OP
Ml1'.'
CLR

f\, .. 110100000
1';"', A
,OUTPUT iNSTRl)CTION CODE
p,~ 4
,FAL LING EDGE OF PROG

0111

1-';!,t.oOOOllllB

MO'.

,', P2

,R~AJ)

SEn
SE re

f';' 4
P;-> 5

,RETURN PROG HI~.H
. CE'-SEl EeT CHIP

,SI;T FOIo/ INPur
INPUT OATA

Serial Port and Timer applications
Configuring the 8051's Serial Port for a given data rate
and protocol requires essentially three short sections of
software. On power-up or hardware reset the serial port
and timer control words must be initialized to the
appropriate values. Additional software is also needed in
the transmit routine to load the serial port data register
and in the receive routine to unload the data as it arrives.
This is best illustrated through an arbitrary example.
Assume the 8051 will communicate with a CRT
operating at 2400 baud (bits per second). Each character
is transmitted as seven data bits, odd parity, and one stop
bit., This results in a character rate of 2400/10=240
characters per second.
For the sake of clarity, the transmit and receive
subroutines are driven by simple-minded software status
polling code rather than interrupts. (It might help to refer
back to Figures 7-9 showing the control word formats.)
The serial port must be initialized to 8-bit UART mode
(MO, MI=OI), enabled to receive all messages (M2=O,
REN= I). The flag indicating that the transmit register is
free for more data will be artificially set in order to let the
output software know the output register is available.
This can all be set up with one instruction.

In one operand instructions (INC, DEC, DJNZ and the
Boolean CPL) the output latch rather than the input pin
level is used as the source data. Similarly, two operand
instructions using the port as both one source and the
destination (ANL, ORL, XRL) use the output latches.
This ensures that latch bits corresponding to pins used as
inputs will not be cleared in the process of executing these
instructions.

Example 31 - Serial Port Mode and Control Bits
• SPINIT INITIALIZE SERIAL PORT
FOR 8-BIT UART MODF
, SET TRANS" I T READV FLAG

SPINlT

MOV

SCON ••010100108

..51
8751

The Boolean operation J BC tests the output latch bit,
rather than the input pin, in deciding whether or not to
jump. Like the byte-wise logical operations, Boolean
operations which modify individual pins of a port leave
the other bits of the output latch unchanged.

8243
P4
P2.7
PU
P2.•
P2.4
P2.3
P2.2
P2.1
P2.0

A good example of how these modes may play together
may be taken from the host-processor interface expected
by an 8243 I/O expander. Even though the 8051 does' not
include 8048-type instructions for interfacing with an
8243, the parts can be interconnected (Figure 23) and the
protocol may be emulated with simple software.

} INPUTS

PROG
P23
P22
P21
P20

Figure 23. Connecting an 8051 with an 8243
I/O Expander
AFN-01502A-31

10-Z9

Timer I will be used in auto-reload mode as a data rate
generator. To achieve a data rate of 2400 baud, the timer
must divide the I MHz internal clock by 32 x (desired
data rate):
I x 1()6
(32) (2400)
which equals 13.02 rounded down to 13 instruction
cycles. The timer must reload the value -13, or OF3H.
(ASMSI will accept both the signed decimal or hexadecimal representations.)
Example 32 -'Initializing Timer Mode and Control Bits
,TltNIT INITIALIZE TIMER 1 FOR
AUTO-RELOAD AT 32*2400 HZ
(TO USED AS OATED U.-B IT COUNTER

T1 INIT

MOV
MOV
SETB

)

TCON. *110100109
THI.I-13
TRI

. A simple subroutine to transmit the character passed to it
in the accumulator must first compute the parity bit,
insert it into the data byte, wait untilthe transmitter is
available, output the character, and return. This is nearly
as easy said as done.
Example 33 -Code for UART Output, Adding Parity,
Transmitter Loading
• sp OUT ADD ODD PAR lTV TO Ace AND
TRANSMIT WHEN SERIAL PORT READY
SP _OUT

e.
e

1"101,1

ePL

MOV
JNB

Ace 7. C

eLR

MOV

SOUF. A

TI.

RET

A simple minded routine to wait until a character is
received, set the carry flag if there is an odd-parity error,
and return the masked seven-bit code in the accumulator
is equally short.
Example 34-Code for UART Reception and Parity
Verification
,SP _IN

INPUT NEXT CHARACTER FROM SERIAL PORT
SET CARRY IFF ODD-PARITY ERROR

SP _IN

')NB

RI.

eLA
HOV
MOV

RI
A. SOUF
C. P

CPL

ANL
RET

A.17FH

6. SUMMARY

This Application Note has described the architecture,
instruction set, and on-chip peripheral features of the
first three members of the MCS-51'· microcomputer
family. The examples used throughout were admittedly
(and necessarily) very simple. Additional examples and
techniques may be found in the MCS-SI'· User's Manual
and other application notes written for the MCS-48'· and
MCS-SI'· families.
Since its introduction in 1977, the MCS-48'· family has
become the industry standard single-chip
microcomputer. The MCS-SI ,. architecture expands the
addressing capabilities and instr,uction set of its
predecessor while ensuring flexibility for the future, and
maintaining basic software compatability with the past.
Designers already f<;lmiliar with the 8048 or 8049 will be
able to take with them the education and experience
gained from past designs as ever-increasing system
performance demands force them to move on to state-ofthe-art products, Newcomers will find the power and
regularity of the. 80S I instruction set an advantage ·in
streamlining both the learning and design processes.
Microcomputer system designers will appreciate the 80S I
as basically a single-chip solution to many problems
which previously required board-level computers.
Designers of real-time control systems will find the high
execution speed, on-chip periphj!rals, and interrupt
capabilities vital in meeting the timing constraints of
products previously requiring discrete logic pesigns. And
designers of industrial controllers. will be able to convert
ladder diagrams directly from testeq-and-true TTL or
relay-logic designs to microcomputer software. thanks to
the unique Boolean processing capabilities.
It has not been the intent of this note to gloss over the
difficulty of designing microcomputer-based systems. To
be sure. the hardware and software design aspects of any
new computer system are nontrivial tasks. However. the
system speed,and level of integration of the MCS-SI'·
microcomputers; the power and flexibility of the
instruction set. and the sophisticated assembler and other
support products combine to give both the hardware and
software designer as much of a head start on the problem
as possible.

AFN-01502A-32

10-30

Using the
Intel MCS®-51
Boolean Processing
Capabilities

Contents
1. INTRODUCTION. . . . . . . . . . . . . . . . . . ... 10-32

2. BOOLEAN PROCESSOR OPERATION . . . . . ..
Processing Elements. . . . . . . . . . . . . . . . . . .
Direct Bit Addressing . . . . . . . . . . . . . . . . . . .
Instruction Set. . . . . . . . . . . . . . . . . . . . . . .
Simple Instruction Combinations. . . . . . . . . . . .

10-32
10-33
10-34
10-39
10-40

3. BOOLEAN PROCESSOR APPLICATIONS . . ...
Design Example #1 - Bit Permutation. . . . . . . .
Design Example '/12 - Software Serial 110. . . . . .
Design Example #3 Combinatorial Logic Equations. . . . . . . .. . . .
Design Example #4 Automotive Dashboard Functions. . . . . . . . . .
Design Example #5 Complex Control Functions . . . . . . . . . . . . . .
Additional Functions and Uses. . . . . . . . . . . . .

10-41
10-42
10-45
10-46
10-49
10-54
10-59

4. SUMMARY . . . . . . . . . . . . . . . . . . . . . ... 10-60

APPENDIX A . . . . . . . . . . . . . . . . . . . . . . . 10-61

10-31

1. INTRODUCTION
The Intel microcontroller family now has th~ee new.
memhcr,
the Intel® XOJ I. X051. and X751 ,ingle-chip
microcomputer,. These devices. shown in Figure I.. will
allow whole new classes of pr~ducts to benefit from rec~nt .
advances in Integrated Electronics. Thanks to Intel'sne\\!'
HMOS'" technology. they prO\ ide larger pi'(lgram' and
data memory spaces. more flexible I 0 and peripheral
capahilitie,. greater 'peed. and lower system cost than any
previou~-generatlon single-chip microcomputer.

,\J

C 1

P11 -

C 2

39::1-POO

P12-

t 3

38::::J -POl

P13- [ 4

PH-CS

:J - P03

-P02

Pl.6 -

-P05

P17 -

.....,P06

J -P07

,.15-[ •

VPOIRST -

[

C 10

P311TXD -

[

P321iN'TO -

[

P3.~iNTi P34/TO -

[ 13
[

The 805,1 inco'rporates a number of special features which
support the direct manipulation and testing of individual
bits and allow the use of single-bit variables in performing
logical operations. Taken together. these features are
referred to as the MCS_5I™ Boolean Processor. While the
bit-processing capabilities alone would be adequate. to
solve many control applications. their true power comes
when they are used in conjunction with the microcomputer's byte-processing and numerical capabilities,

4Q:J'-vcc

P1 0 -

P3 O/RXD -

The CPU in each microcomputer is one of the industry's
fas.test and most efficient fo~ 'numerical. calculations on
. byte operands. But controllers often deal with bits. n()t
bytes: in the reaI'worid. sWitch contacts can only be open
or closed. indicators should be ei.ther lit or dark. motors
are either turned on or off. and so forth. For such control
situations the most significant aspect of the MCS_5ITM
architecture is its complete hardware support for one-bit.
or Boolean variables (named in honor of Mathematician
George Boole) a,. a separate data type.

-P04

31 ::J - VDOIEA

6031
6051

8751

J -

PROG/ALE

J -

PSeN

-P27

27:::J -P26

26::1-·25

P35/TI -

C 15

P36/WR -

[ 16

25::]-P24

P37/iiD -

[ 11

24::J -P23

XTAL2 -

23:::J -P22

XTAll -

C 19

22::::J- P21

VSS-[20

Man~ concep" embodied by the Boolean Procc"or will
. certainly be new even to experienced microcomputer system designers. The purpose of this Applicatio'n Note is to
explain these concepts and show how theyare used. It is
assumed the reader has read Application Note AP-69. An
Introduction to the Intel® MCS-5J™ Single-Chip Microcomputer Family, publication number 121518. or has
been exposed to Intel's single-chip microcomputer product line"

-P20

For detailed information on these parts refer to the Intel
MCS-5pM Family User's Manual. publication number
121517, The instruction set. assembly language. and use of
the 8051 assembler (ASM51) are further described in the
MCS·5pM Macro Assembler User's Guide. publication
number 9800937.

Figure 1. 8051 Family Pinout Diagram.
Table I summari7es the quantitative differences between
the members of the MCS_48™ and 8051 families. The 8751
contains 4K bytes of EPROM program memory fabricated on-chip. while the 8051 replaces the EPROM with
4K bytes of lower-cost mask-programmed ROM. The
8031 has no program memory on-chip; instead. it accesses
up to 64K bytes of program memory from external
memory. Otherwise. the three new family members are
identical. Throughout this Note. the term "8051" will
represent all members of the'805! Family. unless specifically stated otherwise.

2. BOOLEAN PROCESSOR OPERATION
The Boolean Processing capabilities of the 8051 are based
on concepts which have been around for some time. Digital computer systems of widely varying designs all have
four functional elements in common (Figure 2):

Table 1. Features of Intel's Single·chipMicrocomputers.
EPROM
Program
Memory

_.
8748
-

8751

ROM
Program
Memory
8021
8022
8048
8049
8051

External
Program
Memory
-

8035
8039
8031 .

Program
Memory
(Int/Max)
IK
2K
IK
2K
4K

IK
2K
4K
4K
64K

Data
Memory
(Bytes)

Instr.
Cycle
Time

Input/'
Output
Pins

Interrupt
Sources

Reg.
Banks

64
64
64
128
128

10 ~Sec
10 ~Sec
2.5 ~Sec

21
28
27
27
32

0
2
2
2
5

I
I

1.36~Sec

1.0

~Sec

2
2
4
01489A-03

10·32

• a central processor (CPU) with the control, timing.
and logic circuits needed to execute stored
instructions;
• a memory to store the sequence of instructions
making up a program or algorithm;
• data memory to store variables used by the program;
and
• some means of communicating with the outside
world.

PROGRAM
MEMORY

INPUTI
OUTPUT
PORTS

LAL

fORLO

DATA
MEMORY

proce,\or, might fir,t IT-create Shake'peure\ c1a,,,c,
and this Application Note)! Thi, fact offer, little consolation to product designers who want program, to run a,
quickly as possible. By definition, a real-time control algorithm must proceed quickly enough to meet the preordained speed constraints of other equipment.
One of the factors determining how long it will take a
microcomputer to complete a given chore is the number of
instructions It must execute. What makes a given computer architecture particularly well-or poorly-,uitcd for a
class of problems is how well its instruction set matches
the tasks to be performed. The better the "primative"
operations correspond to the steps taken by the control
algorithm. the lower the number of instructions needed.
and the quicker the program will run. All else being equal,
a CPU supporting M-bit arithmetic directly could clearly
perform floating-point math faster than a machine
bogged-down by mUltiple-precision subroutines. In the
same way: direct support for bit manipulation n'aturally
leads to more efficient programs handling the binary input
and output conditions inherent in digital control problems.

Processing Elements
Figure 2. Block Diagram for Abstract Digital
Computer.
.
The CPU usually includes one or more accumulators or
special registers for computing or storing values during
program execution. The instruction set of such a processor generally includes. at a minimum. operation classes to
perform arithmetic or logical functions on program variables. move variable, from one place to another. cau~e
program execution to jump or conditionally branch based
on register or variable states. and instructions to call and
return from subroutines. The program and data memory
functions sometimes share a single memory space. but this
is not always the case. When the address spaces are separated. program and data memory'need not even have the
same basic word width.
A digital computer's flexibility comes in part from combining simple fast operations \0 produce more complex
(albeit slower) ones, which in turn link together eventually
solving the problem at hand. A four-bit CPU executing
mUltiple precision subroutines can. for example. perform
M-bit addition and subtraction. The subroutines could in
turn be building blocks for floating-point multiplication
and division routines. Eventually. the four-bit CPU can
simulate a far more complex "virtual" machine. '

In fact. any digital computer with the above four functional elements can (given time) complete any algorithm
(though the proverbial room full of chimpanzees at word

The introductIOn stated that the 8051's bit-handling capabilities alone would be sufficient to !>olve some control
applications. Let's see how the four basic elements of a
digital computer - a CPU with associated registers. program memory. addressable data RAM. and 110 capab,ility - relate to Boolean variables.

cpu. The 8051

('PU incorporates special logic devoted to
executing several bit-wide operations. All told. there are
17 such instructions. all listed in Table 2. Not shown are 94
other (mostly byte-oriented) 8051 instructions.
Pro~ram Memory. Bit-processing instructions are fetched
from the same program memory as other arithmetic and
logical operations. In addition to the instructions of Table
2. several sophisticated program control features like multiple addressing modes. subroutine nesting. and a twolevel interrupt structure are useful in structuring Boolean
Processor-based programs.

Boolean instructions are one. two. or three bytes long.
depending on what function they perform. Those involving only the carry flag have either a single-byte opcode or
an opcode followed by conditional-branch destination
byte (Figure 3.a). The more general instructions add a
"direct address" byte after the opcode to specify the bit
affected. yielding two or three byte encodings (Figure 3. b).
Though this format allows potentially 256 directly addressable bit locations. not all of them are implemented in the
8051 family.

01489A-Q4

10-33

Table 2. MCS-S1TM Boolean Processing Instruction
Subset.
Mnemonic

Description

SETB
SETS
ClR
CLR
CPI
CPL

Set Carry flag
Set direct Bit
Clear Carry flag
Clear direct bIt
Complement Carry flag
Complement direct hit

C
bit
C
bit
C
hit

MOY Chit
MOY bit.C
A"IL
A"II
ORL
ORL

J"IC
JB
J"IB
JBC

Byte Cyc

Jump
Jump
Jump
Jump
Jump

I
2
2
2

If Carry I' flag i, ,et
if \io Carry flag
If direct Bit ,et
3
If direct Bit "lot 'et
3
If direct Bit IS ,et & Clear bit 3

opcode

JC
JNC

displacement

rei
rei

a.) Carry Control and Test Instructions.

I
2
2
2

Carry flag.

bit

128 software flags. any I 0 pin. control or stalus
bit

rei

All conditional jumps include an 8-bit offset byte.
Range is + 127 -128 bytes relative to first byte of
the following instruction.
'

opcode

opcode
JB
JNB
JBC

bit address

bit
bit
bit
bit
bit
bit
bit
bit
bit,C

SETB
CLR
CPL
ANLC,
ANL C,I
ORLC,
ORL C,I
MOVC,
MaV

2
2

Address mode abbreviations:
C

opcode
SETB C
CLR C
CPL C

Chit A "I D direct bit to Carry nag
Chit A"ID complement of direct hit to
Carry 'flag
Cbit OR direct hit to Carry flag
C bit OR complement of direct bit to
Carry nag
rei
rei
blue!
hiLrd
hiLrel

Mme direct hIt to Carry flag
Move Carry flag to direct bit

bit address
bit,
bit,
bit.

displacement

rei
rei
rei

b.) Bit Manipulation and Test Instructions.

All mnemonics copyrighted© Inlel Corporation 1980

Figure 3; Bit Addressing Instruction Formats.

Direct Bit Addressing

DolO Memorr. The instructions in Figure 3.b can operate
directly upon 144 general purpose bits forming the Boolean processor "RAM." Thew bih can be used as sofware
flag' or to store program variables. Two operand instructiom use the CPU's carry flag (HC") as a special one-bit
register: in a sem,c. the carry is a "Boolean accumulator"
for logical operations and data transfers.

The most significant bit of the direct address byte selects
one of two groups of bits. Values between 0 and 127 (OOH
and 7FH) define bits in a block of 32 bytes of on-chip
RAM. between RAM addresses 20H and 2FH (Figure
4.a). They are numbered consecutively from the lowestorder byte's lowest-order bit through the highest-order
byte's highest-order bit.

InflW/OUlflUI. All 32 I' 0 pins can be addressed as individual inputs. outputs. or both. in any combihation. Any
pin can be a control strobe output. status (Test) input. or
serial I 0 link implemented via software. An additional
33 individually addressable bits reconfigure. control. and
monitor the status of the CPU and all on-chip peripheral
functions (timer counters. serial port modes. interrupt
logic. and so forth).

Bit addresses between 128 and 255(80H and OFFH) correspond to bits in a number of special registers. mostly
used for I 0 or peripheral control. These positions are
numbered with a different scheme than RAM: the five
high-order address bits match those of the register's own
address. while the three low-order bits identify the bit
position within that register (Figure 4.b).
01489A-05

10-34

RAM
Byte

(MSB)

Direct
Byte
Address (MSB)

(lSB)

7FH~

Bit Addresses
(lSB)

HaTdw.re
Register
Symbol

OFFH

1"--

1'-

2FH

711

2EH

20H

2CH

2BH

2AH

29H

28H

27H

26H

25H'

24H

23H

22H

21H

llA

20H

OFOH

OEOH

ACC

OOOH

PSW

OB8H

OBOH

OA8H

OAOH

98H

SCON

90H

88H

TCON

80H

1FH
18H
17H

Bank 3

10H
OFH

Bank 2

08H
07H

,Bank 1

BankO

a.) RAM Bit Addresses.

b.) Special Function Register Bit Addresses.
Figure 4. Bit Address Maps.

,Notice the column labeled "Symbol"in Figure 5, Bit, with
special meaning' in the PSW and other regiqers have
corresponding ,ymbolic names, General-purpo~e (as
opposed to carry-specific) instructiom may acce,s the
carry like any other bit byusing the mnemonic CY in place
of CPO. PI. P2. and P3 are the 8051's four 110 ports;
secondary functions assigned to each of the eight pins of
P3 are shown in Figure 6,

Figure 7 ~hows the la,t four bit addre"able regiqers,
TCON (Timer Control) and SCOI\: (Serial port Control)
control and monitor the corresponding peripherab. while
IE (Interrupt Enable) and IP (Interrupt Priority) enable
and prioriti7e the five hardware interrupt ,ource~, Like the
reserved hardware register addres,e,. the five bib not
implemented in I E and \P ,hould not be acces,ed; they can
not be used as software flag',
01489A-06

10-35

(LSB)

(MSB)

I AC I

I RS1 I RSO I OV

PSW.2

Symbol Position Name and significance

PSW.7

Carry flag.
Set/cleared by hardware or softwaredwing certain arithmetic and
logical instructions.

PSW.6

Auxiliary Carry flag.
Set/cleared by hardware during
addition or subtraction instructions to indicate carry or borrow
out of bit 3.

PSW.S

Flag O.
Set/cleared/tested by software as
a user-defined status flag.

RS1
RSO

PSW.4
PSW.3

Overflow flag.
. Set/cleared by hardware during
arithmetic instructi0ns to indicate
overflow conditions.

PSW.1

(reserved)

PSW:O

Parity flag.
Set/cleared by hardware each instruction cycle to indicate an odd/even number of "one" bits in the
accumulator, i.e., even parity.

Note -

the contents of (RS1, RSO) enable
the working register banks as
follows:
(0,0) - Bank 0
(0;1)-Bank1
(1,0) c Bank 2
(1,1)~Bank3

(00H-07H)
(08H-OFH)
(10H-17H)
(18H-1 FH)

Figure 5. PSW - Program Status Word organization.

(MSB)

(LSB)

I WR I T1

IINT1 1lNTO ITXD I RXD I

Symbol Position Name and significance

P3.7

P3.6

Read data control output.

INT1

P3.3

Interrupt 1 Input pin.

Active low pulse generated by

Low-level or falling-edge

hardware when external data
memory is read.

triggered.

Write data control output.
Active low pulse generated by
hardware when external data
memory is written.

P3.S

Timer/counter 1 external input or
test pin.

P3.4

Timer/counter 0 external input or
test pin.

INTO

P32

Interrupt 0 input pi"1.
Low-level or falling-edge
triggered.

TXD

P3.1

Transmit Data pin for serial port
in UART mode. Clock output in
shift register mode

RXD

P3.0

R.eceive Data pin for serial port in
UART mode. Data I/O pin in shift
register mode.

Figure 6. P3 - Alternate 110 Functions of Port 3.
01489A-07

10-36

(MSB)

(LSB)

ITF1 I TR1 I TFO I TRO IIE1

IT1

lEO

ITO

IE1

TCON.3 Interrupt 1 Edge flag.
Set by hardware when external
interrupt edge detected. Cleared
when interrupt processed.

IT1

TCON.6 Timer 1 Run control bit.
Set/cleared by software to turn
timer/counter on/off.

TCON.2 Interrupt 1 Type control bit.
Set/cleared by software to
specify falling edge/low level
triggered external interwpts.

lEO

TCON.5 Timer 0 overflow Flag.
Set by hardware on
timer/counter overflow. Cleared
when interrupt processed.

TCON.1 Interrupt 0 Edge flag.
Set by hardware when external
interrupt edge detected. Cleared
when interrupt processed.

ITO

TCON.O Interrupt 0 Type control bit.
Set/cleared by softrware to
specify falling edge/low level
triggered external interrupts.

RB8

SCON.2 Receive Bit 8.
Set/cleared by hardware to indicate state of ninth data bit
received.

SCON.1 Transmit Interrupt flag.
Set by hardware when byte
transmitted. Cleared by software
after servicing.

SCON.O Receive Interrupt flag.
Set by hardware when byte received. Cleared by software after
servicing.

Symbol Position Name and significance
TF1
TCON.? Timer 1 overflow Flag.
Set by hardware on
timer/counter overflow. Cleared
when interrupt processed.
TR1

TFO

TRO

TCONA Timer 0 Run control bit.
Set/cleared by software to turn
timer/counter on/off.

a.) TCON - Timer/Counter Control/status register.

(MSB)

(LSB)

ISMO ISM1 ISM21 REN ITBsl RBsl

I RI ·1

Symbol Position Name and significance
SMO
SCON.? Serial port Mode control bit O.
Set/cleared by software (see
note).
SM1

SM2

REN

TB8

b.)

SCON.6 Serial port Mode control bit 1.
Set/cleared by software (see
note).
SCON.5 Serial port Mode control bit 2.
Set by software to disable reception of frames for which bit 8 is
zero.
SCONA Receiver Enable control bit.
Set/cleared by software to
enable/disable serial data
reception.

Note -

SCON.3 Transmit Bit 8.
Set/cleared by hardware to determine state of ninth data bit transmitted in 9-bit UART mode.
SCON - Serial Port Control/status register.

the state of (SMO,SM1) selects:
(0,0) - Shift register I/O expansion.
(0,1) - 8 bit UART, variable data rate.
(1,0) - 9 bit UART, fixed data rate.
(1,1) - 9 bit UART, variable data rate.

Figure 7. Peripheral Configuration Registers.
014S9A-08

10-37

(MSB)

(LSB)

I ET1 I EX1 I ET1 I EXO I

Symbol Position Name and significance

Enable All control bit.
Cleared by software to disable all
interrupts, independent of the
state of IE.4 - IE.O.

EX1

IE.2

Enable External interrupt 1
control bit. Set/cleared by
software to ~mable/disable
interrupts from INT1.

1E.6
1E.5

(reserved)

ETa

IE.1

IE4

Enable Serial port control bit
Set/cleared by software to
enable/ disable Interrupts from
TI or RI flags.

Enable Tjmer 0 control bit.
Set/cleared by software to
enable/ disable interrupts from
timer/counter O.

EXO

lEO

Enable External Interrupt a
control bit. Set/cleared by
software to enable/disable
Interrupts from INTO.

PX1

IP.2

External interrupt 1 Priority
control bit. Set/cleared by
software to specify high/low
priority interrupts for INT1.

IE3

ET1

c.)

IE 7

Enable Timer 1 control bit
Set/cleared by software to
enable/ disable interrupts from
timer/counter 1

IE - Interrupt Enable Register.

(MSB)

(LSB)
PS

I PT1 I PX1 I PTO I PXO I

Symbol Position Name and significance

IP.7
IP.6
IP.5

(reserved)
(reserved)
(reserved)

IP4

Serial port Priority control bit.
Set/cleared ,by software to
specify high/low priority
interrupts for Serial port.

PTO

IP 1

Timer 0 Priority control bit.
Set/cleared by software to
specify highiIO"'! priority
interrupts for timdr/counter O.

PT1

IP.3

Timer 1 Priority control bit.
, Set/cleared by software to
specify high/low priority
interrupts for timer/counter 1.

PXO

IP.O

External interrupt a Priority
control bit. Set/cleared by
software to specify high/low
priority interrupts for INTO.

d.)

IP - Interrupt Priority Control Register.
Figure 7. (continued)

Addressable Register Set. There are 20 special function
registers in the 8051, but the advantages of bit addressing
only relate to the II described below. Five potentially
bit-addressable register addresses (OCOH, OCSH, 008H.
OESH, & OF8H) are being reserved for possible future
expansion in microcomputers based on the MCS-5I'M
architecture. Reading or writing non-existent registers in
the 8051 series is pointless, and may cause unpredictable
results. Byteowide logical operations can be used to
manipulate bits in all non-bit addressable registers and
RAM.

The accumulator and B registers (A and B) are normally
involved in byte-wide arithmetic. but their individual bits
can also be used as 16 general software flags. Added with
the 128 flags in RAM, this gives 144 general purpose
variables for· bit-intensive programs. The program status
word (PSW) in Figure 5 is a collection of flags and,
machine statuS bits including the carry flag itself. Byte
operations acting on the PSW can therefore affect the
carry.

10-3a

Instruction Set
Having looked at the bit variables available to the Boolean
Processor. we will now look at the four classes of instructions
that manipulate these bits. It may be helpful to refer back to
Table 2 while reading this section.
State Control. Addressable bits or flags may be set. cleared.
or logically complemented in one instruction cycle with the
two-byte instructions SETB. CLR. and CPL. (The "B"
affixed to SETB distinguishes it from the assembler "SET"
directive used for symbol definition.) SETB and CLR are
analogous to loading a bit with a constant: I ot O. Single
byte versions perform the same three operations on the
carry.
The MCS-5l'· assembly language specifies a bit address in
any of three ways:
• bya number or expression corresponding to the direct
bit address (0-255);

Figure 8. Bit Transfer Instruction Operation.
• by the name or address of the register containing the
bit, the dot operator symbol (a period: ". "). and the
bit's position in the register (7.{);

slash mark ("/ ") before the source operand indicates whether
to use the positive-logic value or the logical complement of
the addressed bit. (The source operand itself is never
affected.)

• in the case of control and status registers. by the predefined assembler symbols listed in the first columns
of Figures 5-7.

Bit-test Instructions. The conditionaljump instructions "JC
reI" (Jump on Carry) and"JNC reI" (Jump on Not Carry)
test the state of the carry flag. branching if it is a one or zero.
respectively. (The letters "reI" denote relative code addressing.) The three-byte instructions "JB bit. reI" and "JNB
bit.rel" (Jump on Bit and Jump on Not Bit) test the state of
any addressable bit in a similar manner. A fifth instruction
combines the Jump on Bit and Clear operations. "JBC
bit.rel"conditionally branches to the indicated address. then
clears the bit in the same two cycle instruction. This operation is the same as the MCS-48'· "JTF" instructions.

Bits may also be given user-defined names with the assembler
"BIT" directive and any of the above techniques. For example. bit 5 of the PSW may be cleared by any of the four
instructions.
USLFLG BIT

PSW.5

User Symbol Definition

CLR
CLR
CLR

OD5H
PSW.5
FO

CLR

USILFLG

Absolute Addressing
Use of Dot Operator
Pre-Defined Assembler
Symbol
User-Defined Symbol

Data Transfers. The two-byte'MOV instructions can transport any addressable bit to the carry in one cycle. or copy the
carry to the bit in two cycles. A bit can be moved between
two arbitrary locations vIa the carry by combining the two
instructions. (If necessary. push and pop the PSW to preserve
the previous contents of the carry.) These instructions can
replace the multi-instruction sequence of Figure 8. a program
structure appearing in controller applications whenever flags
or outputs are conditionally switched on or off.
Logical Operations. Four instructions perform the logicalAND and logical-OR operations between the carry and
another bit. and leave the results in the carry. The instruction
mnemonics are ANL and ORL; the absence or presence ofa

All 8051 conditional jump instructions use program
counter-relative addressing. and all execute in two cycles.
The last instruction byte encodes a signed displacement
ranging from - L28 to + 127. During execution. the CPU adds
this value to the incremented program counter to produce
the jump destination. Put another way. a conditional jump
to the immediately following instruction would encode OOH
in the offset byte.
A section of program or subroutine written using only relative jumps to nearby addresses will have the same machine
code independent of the code's location. An assembled routine may be repositioned anywhere in memory, even crossing
memory page boundaries, without having to modify the
program or recompute destination addresses. To facilitate
this flexibility, there is an unconditional "Short Jump"
(SJMP) which uses relative addressing as well. Since a pro01489A-l0

10-39

grammer would have quite a chore trying to compute relative offset values from one instruction to another, ASM51
automatically computes the displacement needed given only
the destination address or label. An error message will alert
the programmer if the destination is "out of range."
(The so-called "Bit Test" instructions implemented on many
other microprocessors simply perform the logical-AND
operation between a byte varia ble and a constant mask. and
set or clear a 7ero flag depending on the result. This is
essentially equiyalent to the 8051 "MOY C.bit" instruction.
A second instruction is then needed to conditionally branch
based on the state of the zero flag. This does not constitute
abstract bit-addressing in the MCS-51'· sense. A flag exists
only as a field within a register; to reference a bit the programmer must know and specify both the encompassing
register and the bit's position therein. This constraint
severely limits the flexibility of symbolic bit addressing and
reduces the machine's code-efficiency and speed.)

Table 3. Other Instructions Affecting the Carry
Flag.
Mnemonic

Description

ADD

A.Rn

ADD

A.dlfect

ADD

A.@Ri

ADD

A.#data

Add regiqer to
Accumulator
Add direct byte to
Accumulator
Add indlfect RAM to
Accumulator
Add immediate data to
Accumulator
Add regi,ter to
Accumulator with Carry
nag
Add direct byte to
Accumulator with Carry
flag
Add indirect RAM to
Accumulator with Carry
nag
Add Immedl3te data to
Ace with Carn' nag
Subtract regl\ler from
Accumulator with
borrow
Subtract direct byte
from Ace with borrow
Subtract indirect RAM
from Acc with borrow
Subtract Immedl3te data
from Acc with borrow
Multlpl) A & R
Dl\idc A by R
Decimal Adiu,t
Accumulator

ADDC A.Rn

ADDC A. dlfect

ADDCA.@RI

ADDC A.#data

Interaction with Other Instructions. The carry flag is also
affected by the instructions listed in Table 3. It can be rotated
through the accumulator. and altered as a side effect of
arithmetic instructions. Refer to the User's Manual for
details on how these instructions operate.

Simple Instruction Combinations

SURR A.Rn

SURR A.dlrect
SURR A.@RI
SURR A.#data

By combining general purpose bit operations with certain
addressable bits. one can "custom build" seveml hundred
useful instructions. All eight bits of the PS W can be tested
directly with conditional jump instructions to monitor
(among other things) parity and overflow status. Programmers can take advantage of 128 software flags to keep
track of operating modes. resource usage. and so forth.
The Boolean instructions are also the most efficient way to
control or reconfigure peripheral and I 0 registers. All 32
I' 0 lines become "test pins." for example. tested by conditional jump instructions. Any output pin can be toggled
(complemented) ina single instruction cycle. Setting or c1earing the Timer Run flags (TRO and TR I) turn the timer/ counters on or off; polling the same flags elsewhere lets the
program determine if a timer is running. The respective
overflow flags (TFO and TFI) can be tested to determine
when the desired period or count has elapsed. then cleared in
preparation for the next repetition. (For the record. these
bits are all part of the TCON register. Figure 7.a. ThGnks to
symbolic bit addressing. the programmer only needs to
remember the mnemonic associated with each function. In
other words. don't bother memori7ingcontrol word layouts.)
In the MCS-48® family. instructions corresponding to some
of the above functions require specific opcodes. Ten different
opcodes serve to clear! complement the software flags FO
and FI. enable /disable each interrupt. and start' stop the
timer. In the 8051 instruction set. just three opcodes (SETB.

Ml'l.
DIY
DA

AR
AR
A

RLC

RRC

Byte eyc

I
4
4

Rotate Accumulator
Left through the Carry
flag:
Rotate Accumulator
Right through Carry flag

C.I"E A.dlfect.rel

Compare dlfect byte to
Acc & Jump if :-;ot
Equal

C.I"E A.#data.rel

Compare Immediate to

Acc & Jump if "ot
Equal
C.I"E R n.#d~ta.rel Compare immed to
regi,ter & .I ump if "at
Equal
CJ"E @RI.#data.rclCompare immed to
Indirect & .lump If "ot
Equal'

All mnemonic, copYflghtcd

Intel Corporation 19HO
01489A-11

10~40

using awkward sequences of other basic operations. As
mentioned earlier, any CPU can solve any problem given
enough time.
.
Quantitatively, the differences between a solution allowed
by the 8051 and those required by previous architectures
are numerous. What the 80S I Family buys you is a faster,
cleaner, lower-cost solution to microcontroller
applications.

CLR, CPL) with a direct bit address appended perform the
same functions. Two test instructions UB and JNB) can be
combined with bit addresses to test the software flags, the
8048 I/O pins TO, TI, and INT, and the eight accumulator
bits, replacing 15 more different instructions.
Table 4.a shows how 8051 programs implement software
flag and machine control functions associated with special

The opcode space freed by condensing many specific 8048
Table
8048
Instruction

4.a. Contrasting 8048 and 8051

Bit Control and Testing Instructions.
8x51
Instruction

Bytes

Cycles & uSec

C
FO

I
2

I
I

JNC
JB
JB

rei
FO.rel
ACC.7.rel

2
3
3

5.0
5.0
5.0

JB
JNB
JBC

TO.rel
INTO.rel
TFO.rel

3
3
3

2
2
2

2.5
2.5
2.5

SETB
SETB
CLR

TRO
EXO
ETO

2
2
2

I
I
I

Bytes

Cycles

uSec

Flag Control
CLR C
CPL FO

I
I

2.5
2.5

CLR
CPL

Flag Testing
JNC offset
JFO
offset
JB7
offset

2
2
2

5.0
5.0
5.0

Peripheral
JTO
JNI
JTF

2
2
2

Machine and Peripheral Control
I
STRT T
I
EN
I
I
TCNTI
DIS

I
I
I

Polling
offset
offset
offset

2
2

Table 4.b. Replacing 8048 Instruction sequences with single 8x51 Instructions.
8048
Instructions

Bytes

Flag Control
Set carry:
CLR C
CPL C

Set Software Flag:
CLR FO
CPL FO

Cycles

uSec

8051
Instructions

5.0

SETB C

5.0

SETB FO

opcodes in the 8048. In every case the MCS-51'·solution
requires the same number of machine cycles, and executes
2.5 times faster.

3. B.OOLEAN PROCESSOR APPLICATIONS
So what? Then what does all this buy you?

QualiJatively, nothing. All the same capabilities could be
(and often 'have been) implemen~ed on other machines

10-41

Cycles & uSee

Bytes

instructions into a few general operations has been used to
add new functionality to the M CS-S 1'· architecture - both
for byte and bit operations. 144 software flags replace the
8048's two. These flags (and the carry) may be directly set,
not just cleared and complemented, and all can be tested
for either state, not just one. Operating mode bits previously inaccessible may be read, tested, or saved. Situations where the 8051 instruction set provides new capabilities are contrasted with 8048 instructiQn sequences
in Table-4.b. Here the 8051 speed advantage ranges from
5x to 15x!
01489A-12

8048
Instructions

Bytes

Table 4b (Continued)
8x51
Cycles uSec
Instructions

Bytes

Cycles Be uSt!c

Turn Off Output Pin:
ANL PI.#OFBH

5.0

CLR

PI.2

Complement Output Pin:
A.PI
IN
XRL A.#04H
OUTL PI.A

15.0

CPL

PI.2

in RAM:
RO.#FLGADR
A.@RO
A.#FLGMASK
@RO.A
=

15.0

CLR

USER_FLG

10.0

JNB

FO.rel

Jump if Accumulator bit is 0:
A
CPL
JB7
offset
CPL
A
=

10.0

JNB

ACC.7.rel

Peripheral Polling
Test if Input Pin is Grounded:
IN
A.PI
CPL A
offset
183
=

12.5

JNB

PI.3.rel

Test if Interrupt Pin is High:
$+4
JNI
JMP offset
=

10'.0

INTO.rel

Clear Flag
MOY
MOY
ANL
MOY

Flag Testing
Jump if Software Flag is 0:
$+4
JFO
JMP offset

Combining Boolean and byte"wide instructions can produce great synergy. An MCS-5I'· based application will
prove to be:
• simpler to write since the architecture correlates more
closely with the problems being solved;
• easier to debug because more individual instru~tions
have no unexpected or undesirable side-effects;
• more byte efficient due to direct bit addressing and
program counter relative branching;
• faster running because fewer bytes of instruction need
to be fetched and fewer conditional jumps are
processed;
• lower cost because of the high level of systemintergration within one component.
These rather unabashed claims of excellence shall not go
unsubstantiated. The ~est of this chapter examines less
trivial tasks simplified by the Boolean processor: The first

three compare the 8051 with other microprocessors; the last
two go into 8051-based system designs in much greater
depth.

Design Example #1 - Bit Permutation
First off. we'll use the bit-transfer instructions to permute
a lengthy pattern of bits.
A steadily increasing number of data communication
products use encoding methods to protect the security of
sensitive information. By law, interstate financial transactions involving the Federal banking system must be
transmitted using the Federal Information Processing
Data EncryptioI'J Standard (DES).
Basically, the DES combines eight bytes of "plaintext"
data (in binary, ASCII, or any other format) with a 56-bit
"key", prod!lcing a .64-bit encrypted value for transmission. Atthe receiving end the same algorithm is applied to
the incoming data using the .same key, reproducing the
original eight byte message. The algorithm used for these
permutations is fixed; different user-defined keys ensure
data privacy.
01489A-13

It is not the purpose of this note to describe the DES in any
detail. Suffice it to say that encryption/ decryption is a
long. iterative process consisting of rotations. exclusive
-OR operations. function table look-ups. and an extensive
(and quite bizarre) sequence of bit permutation. packing.
and unpacking steps. (For further details refer to the June
21. 1979 issue of Electronics magazine.) The bit manipulation steps are included. it is rumored. to impede a general
purpose digital supercomputer trying to "break" the code.
Any algorithm implementing the DES with previous generation microprocessors would spend virtually all of its
time diddling bits.

The bit manipulation performed is typified by the Key
Schedule Calculation represented in Figure 9. This step is
repeated 16 times for each key used in the course of a
transmission. In essence. a seven-byte. 56-bit "Shifted Key
Buffer" is transformed into ----:=1)-,----

L DASH

l FRNT

81IAKE

II TURN

L .....

--itt

==r:>--l='}--1+---

. . . .H

R REAR
PARK

Applying the brake pedal turns the taillight filaments on
constantly ... unless a turn is in progress, in which case the
blinking taillight is not affected. (Of course. the front turn
signals and dashboard indicators are not affected by the
brake pedal.) Table 6 summarins these operating modes.

---------j--..,.-1'
LO

FREQ
OSCILLATOR

HI
FREO.
OSCILLATOR

Figure 15. TTL logic implementation of
automotive turn signals.

Table 6. Truth table for turn-signal operation.

BRAKE
SWITCH
0
0
0
0
0
0
I
I
I
I
I
I

INPUT SIGNALS
RIGHT
EMERG.
LEFT
TURN
SWITCH
TURN
SWITCH SWITCH
0
0
0
0
0
I
0
I
0
I
0
0
I
0
I
I
I
0
0
0
0
()
0
I
0
0
I
I
0
0
I
0
I
I
I
0

LEFT
FRONT
& DASH

OUTPUT SIGNALS
RIGHT
LEFT
RIGHT
FRONT
REAR
.REAR
& DASH

OFF
OFF

OFF

OFF
OFF

OFF

BLI"'K
RLI"K
BII"K
RII"K

OFF

RLI"K
RLI"K
RII"'K
RI.J"K

OFF

OFF
OFF

OFF

0"1
0"1

0"1

RI.J"IK

BI.J"K
RLINK
BliNK
BLI'\iK

OFF

RI I"IK

RI.J"IK
RII"K
BII"JK

0'1,1
0"1

ON
BLINK

BLINK

0'"

BII"K
BLI"'K
RII"K
BLI"K

RI I"K
RII"K
RII"K
RI I"K
RI.J"JK

01489A·20

10-49

I n most cars, the switching logic to generate these functions requires a number of multiple-throw contacts. As
manyas 18 conductors thread the steering column of some
automobIles solely for turn-sIgnal and emergency blinker
functions. (The author discovered this recently to his
,I'tonishment and dismay when replacing the whole
assembly because of one burned contact.)
A multiple-conductor wiring harness runs to each corner
of the car, behind the dash. up the steering column, and
down to the blinker relay below. Connectors at each termination for each filament lead tp extra cost and labor
during construction, lower reliability and safety, and more
costly repairs. And considering the system's present complexity, increasing its reliability or detectingJailures
would be quite difficult.
There are two reasons for going into such painful detail
describing this example. First, to show that the messi!!st
part of many system designs is determining what the
controller should do. Writing the software to solve these
functions will be comparatively easy. Secondly, to show
the many potential failure points in the system. Later we'll
see how the peripheral functions and intelligence built into
a microcomputer (with a little creativity) can greatly
reduce external interconnections and mechanical part
count.

Design Example #3 demonstrated that symbolic addressing with user-defined bit names makes code and documentation easier to write and maintain .. Accordingly, we'll
assign these I 0 pins names for use throughout the program. (The format of this example· will differ somewhat
from the others. Segments of the overall program will be
presented in sequence as each is described.)

INPUT PIN DECLARATIONS:
(ALL INPUTS ARE POSITIVE-TRUE LOGIC)
BRAKE
EMERG

HIT PLO
HIT PI. I

PARK
HIT PI.2
LTURN AIT PI.3
R....TURN AIT PI.4

OUTPUT PIN DECLARATIONS'
LFRNT HIT P 1.5
R.... FRNT HIT PI.6
LDASH HIT PI.7
R.... DASH HIT P2.0

The Single-chip Solution

L:"REAR HIT P2.1

The circuit shown in Figure 16 indicates five input pins to
the five input variables~--Ieft-turn select, right-turn select,
brake pedal down, emergency SWItch on. and parking
lights on. Six output pins turn on the front, rear. and
dashboard indicators for each side. The microcomputer
implements all logical functions through software, which
periodically updates the output signals as time elapses and
input conditions change.

R.... REAR HIT P2.2

Figure 16. Microcomputer Turn-signal Connections.

.,'"
805.

:~::B""+H+l>"""""P"
UGHlS
TURN

l",E"!-_+-iH->o-"'-1

SWITCH

R1G="''''-----<~....r>O---i

.oDE
SENSORS

RIO.'10...
'/1"-"""'...,. ....

COH"'QlLER

OUTPUT
IUPFEQ

: BRAKE PEDAL DEPRESSED
: EMERGENCY BI.INKER
ACTIVATED
: PARKING I.IGHTS ON
: TURN LEVER DOWN
: TURN LEVER UP

: FRONT I.EFT-TURN
INDICATOR
: FRONT RIGHT-TURN
INDICATOR
: DASHBOARD LEFT-TURN
INDICATOR
: DASHBOARD RIGHT-TURN
INDICATOR
: REAR LEFT-TURN
INDICATOR
: REAR RIGHT-TURN
INDICATOR

Another key advantage of symbolic addressing will
appear further on in the design cycle. The locations of
cable connectors, signal conditioning circuitry, voltage
regulators, heat sinks, and the like all affect P.c. board
layout. It's quite likely that the somewhat arbitrary pin
assignment defined early in the software design cycle will
prove to be less than optimum: rearranging the I/O pin
assignment could well allow a more compact module, or
eliminate costly jumpers on a single-sided board. (These
considerations apply especially to automotive and other
cost-sensitive applications needing single-chip controllers.) Since other architectures mask bytes or use
"clever" algorithms to isolate bits by rotating them into
the carry, re-routing an input signal (from bit I of port I,
for example, to bit 4 of port 3) could require extensive
modifications throughout the software.
The Boolean Processor's direct bit addressing makes such
changes absolutely trivial. The number ofthe port containing the pin is irrelevent, and masks and complex program
structures are not needed. Only the il)itial Boolean varia-

SIGNAl
lULU

01489A-21

10-50

; INTERRUPT RATE SUBDIVIDER
SUB_PIV
DATA
20H
; HIGH-FREQUENCY OSCILLATOR BIT
HLFREQ
BIT
SUB_DIV.O
; LOW-FREQUENCY OSCILLATOR BIT
LO_FREQ
BIT
SUB_DlV.7

JMP

ORG
INIT

OOOOH

ORG
100H
; PUT TIMER 0 IN MODE I
INIT:
MOV
TMOD.#OOOOOOOIB
; INITIALIZE TIMER REGISTERS
MOV
TLO.#O
MOV
THO.#-16
; SUBDIVIDE INTERRUPT RATE BY 244
MOV
SUB_DIV.#244
; ENABLE TIMER INTERRUPTS
SETB
ETO
: GLOBALLY ENABLE ALL INTERRUPTS
SETB
EA
; START TIMER
SETB
TRO
: (CONTINUE WITH BACKGROUND PROGRAM)
: PUT TIMER 0 IN MODE I
: INITIALIZE TIMER REGISTERS

fast to modulate the parking lights; bit 7 will be "tuned "to
approximately I H7 for the turn- and emergencyindicator blinking rate.
Loading THO with -16 will cause an interrupt after 4.096
msec. The interrupt service routine reloads the high-order
byte of timer 0 for the next interval. saves the CPU registers likely to be affected on the stack. and then decrements
SUB_DIY. Loading SUB_DIV. with 244 initially and
each. time it decrements to zero will produce a 0.999
second period for the highest-order bit.
ORG
. MOV
PUSH
PUSH
PUSH
DJNZ
MOV

The code to sample inputs. perform calculations. and
update outputs-the real "meat" of the signal controller
algorithm-may be performed either as part of the interrupt service routine or as part of a background program
loop. The only concern is that it must be executed at least
several dozen times per second to prevent parking light
flickering. We will assume the former case. and insert the
code into the timer 0 service routine.
First. notice from the logic diagram (Figure 15) that the
subterm (PARK' H_FREQ). asserted when the parking
lights are to be on dimly. figures into four of the six output
functions. Accordingly. we will first compute that term
and save it in a temporary location named "DIM". The
PSW contains two general purpose flags: FO. which corresponds to the 8048 flag of the same name. and PSW.I.
Since The PSW has been saved and will be restored to its
previous state after servicing the interrupt. we can use
either bit for temporary storage.

: SUBDIVIDE INTERRUPT RATE BY 244
: ENABLE TIMER INTERRUPTS
: GLOBALLY ENABLE ALL INTERRUPTS
:STARTTIMER
ble declarations need to be changed: AS M51 automatically adjusts all addresses and symbolic references to the
reassigned variables. The user is assured that no additional debugging or software verification will be required.
Timer 0 (one of the two on-chip timer/ counters) replaces
the thermo-mechanical blin~er relay in the dashboard
controller. During system initialization it is configured as
a timer in mode I by setting the least significant bit of the
timer mode register (TMOD). In this configuration the
low-order byte (TLO) is incremented every machine cycle.
overflowing and incrementing the high-order byte (THO)
every 256 ~Sec. Timer interrupt 0 is enabled so that a
hardware interrupt will occur each time THO overflows.
(For details of the numerous timer operating modes see
the MCS-51'· User's Manual.)
An eight-bit variable in the bit-addressable RAM array
will be needed to further subdivide the interrupts via
software. The lowest-order bit ofthis counter toggles very

OOOBH
: TIMER 0 SERVICE VECTOR
THO.#-16
PSW
ACC
B
SUB_DIV.TOSERV
SUB_DIV.#244

DIM

BIT

MOV C.PARK
AN!.

HLFREQ

MOV DlM.C

PSW.I : DECLARE TEMP.
STORAGE FLAG
: GATE PARKING
LIGHT SWITCH
: WITH HIGH
FREQUENCY
SIGNA!.
: AND SAVE IN
TEMP. VARIABLE.

This simple three-line section of code illustrates a remarkable point. The software indicates in very abstract terms
exactly what function is being performed. independeni of
10-51

01489A-22

the hardware configuration. The fact that these three bits
include an input pin, a bit within a program variable, and
a software flag in the PSW is totally invisible to the
programmer.

MOV R_DASH.C
MOV

ORL CDIM
Now generate and output the dashboard left turn signal.
MOV R_FRNT.C
MOV CLTURN
ORI. CEMERG

MOV LDASH.C

: SET CARRY IF
TURN
: OR EMERGENCY
SELECTED.
:GATE IN I HZ
SIGNAL
: AND OUTPUT TO
DASHBOARD.

MOV CBRAKE
ANI. C R_TURN
ORL CFO

ORL CDIM

To generate the left front turn signal we only need to add
the parking light function in FO. But notice that the function in the carry will also be needed for the rear signal. We
can save effort later by saving its current state in FO.
MOV FO.C
ORL CDIM
MOV LFRNT.C

: SAVE FUNCTION
SO FAR.
: ADD IN PARKING
LIGHT FU!\:CTION
: A"D OUTPUT TO
TURN SIG:\,AL.

MOV R_REAR.C

(The perceptive reader may notice that simply rearranging
the steps could eliminate one instruction from each
sequence.)
Now that all six bulbs are in the proper states, we can
return from the interrupt routine. and the program is
finished. ThiS code essentially needs to reverse the status
saving steps at the beginning of the inte'rrupt.

Finally. the rear left turn signal should also be on when the
brake pedal is depressed, provided a left turn is not In
progress:
MOV CBRAKE
ANI. C LTURN
ORL CFO

ORI. CDIM
MOV LREAR.C

: GATE BRAKE
PEDAL SWITCH
: WITH TURN
LEVER.
: INCI.UDE TEMP.
VARIABLE FROM
DASH
: AND PARKI!\:G
LIGHT FU!'.
: SET P2.2 =(12) (23) (34) ( 45) ( 5/i)
MOV CI2

1NL
ANI.
ANI.
A:,\I.

: REI.OAD SCAN LINE
MASK
ACC7.SCAN : LOOP UNTIL ALI.
EIGHT COLUMNS
READ.

RET

C34
C 45
C 5/i
MOV P2.2,C

Intermediate Variah/es. The examination of a typical
relay-logic ladder diagram will show that many of the
rungs control not outputs but rather relays whose contacts figu're into the computation of other functions. In
effect, these relays indicate the state of intermediate variables of a computation.
The MCS-S/'M solution can use any directly addressable
bit for the storage of such intermediate variables. Even
when all 128 bits of the RAM array are dedicated (to input
bit maps in this example), the accumulator, 'PSW, and B
register provide 18 additional flags for intermediate
variables.
For example, suppose switches 0 through 3 control a
safety interlock system. Closing any ofthem should deactivate certain outputs. Figure 22 is a ladder diagram for
this situation. The interlock function could be'recomputed
for every output affected, or it may be computed once and
saved (as implied by the diagram). As the program proceeds this bit can qualify each output.
Exaniple 5.
, outputs.

Incorpdr~ting

Override signal into actuator

CALL INPUT~'iCAN
MOV CO
ORL CI
ORL C2
ORL C3
MOV FO~C

Figure 21. Flowchart for reading In sensor matrix.
01489A·28

1()'·57

COMPUTE FUNCTION 0

Example 6: Simulating a latchinltrelay.
:L~SET

ANI. C. FO
MOY PI.O.C

·SET FI.AG.O IF C=I
ORt C.FO
. MOY -FO.C

LSET:

C01v1PlJTE FUNCTION I
.ANI. C. FO
MOY PI.I.C

:LRSET RESET FLAG 0 IFC=I
LRSET: CPS C,
ANI. c.PO
MOY FO.C

COMPUTE
FUNCTION. 2
.
ANI. .c. FO
MOY PI.2.C

to an input signal until it has been present (or absent) for
some 'predefined time. For example. a ballast or load
resisior may be switched in series with a D.C. motor when
it is first turned on. and shunted from the circuit after one
second. This sort, of time delay may be simulated by an
'interrupt routine driven by one of the two 8051 timer!
counters .. The procedure followed by the routine depends
heavily on the details of tHe'exa'ct function needed: timeouts or time delays .withresettable or non-resettable inputs
are possible. If the interrupt routine is executed every 10
milliseconds the code in Example 7 will clear an intermediate variable set by the background program after it
has been active for two seconds.

"0"

"2"

"3"

Time Delay R;"ars. A time delay relay does not respond

I
I

Example 7. Code to clear USRFLG aftera fixed time delay .
.INB USR~FLG.NXTTST
D.lNZ DI.A Y_C'OUNT.NXTTST
CLR USR-FLG
MOY DI.A Y_COUNT.#200
NXTTST: ...

Figure 22. Ladder diagram 'or output override
circuitry.

Latching Relays. A latching relay can be forced into either
the ON or OFF state by two corresponding input signals.
wl:1ere it will remain until forced ontp the opposite stateanalogous to a TTL Setl Reset flip-flop. The relay is used
as an intermediate variable for other calculations. In the
previous example, the emergency conditiom could be
remembered and remain active until an "emergency
cleared" button is pressed.

Any flag or addressable bit may repre~ent a l!ltching relay
with a few lines of code (see Example 6).

Serial Interface to Remote Processor. When it detects
emergency conditions repr'esented by certain input combinations (such as the earlier Ell]ergency Override). the
controller could shutdqwn the machine immediately
and/ or alert the host processor via the serial port. Code
bytes indicating the nature of the problem could be transmitted to a central computer. In fact. at 17.000 bytes-persecond. the entire contents of both bit maps could be sent
· to the host processor for further analysis in less than a
millisecond! If the host decides that conditions warrant, it
could alert other remote processors in the system that a
problem exists and specify:which snut-down sequence
each should initiate. For more information on using the
serial port; consult the MCS-SI'· User's Manual.
Response Timing.
One difference between relay and programmed industrial
· controllers (when each is considered as a "black box") i~
· their respective reaction times t~ input changes. As
reflected" by a ladder. diagram, relay systems' contaIn a
01489A-29

. to-$8

large number of "rungs" operating in parallel. A change in
input conditions will begin propagating through the system immediately. possibly affecting the output state
within milliseconds.

: EXCLUSIVE-OR FUNCTION IMPOSEDON CARRY
: USING FO IS INPUT VARIABI.E.
XOR_FO: JNB FO.XORCNT : (".IB" FOR X-NOR)
CPI. C
XORCNT: ...

Software. on the other hand. operates sequentially. A
change in input states will not be detected until the next
time an input scan is performed, and will not affect the
outputs until that section of the program is reached. For
that reason the raw speed of computing the logical functions is of extreme importance.

XCH. Thecontents ofth'ecarryand some other bit may be
exchanged (switched) by using the accumulator a& temporary storage. Bits can be moved into and out of the accumulator simultaneously using the Rotate-through-carry
instructions. though this would alter the accumulator
data.

H~re the Boolean processor pays off. Eve~1' instruction
'mentioned in this Note completes in one or two microseconds-the minimum instruction execution time for
ma'ny other microcontrollers! A ladder diagram containing a hundred rungs. with an average of four contacts per
rung can be replaced by approximately five hundred lines
of software. A complete pass through the entire matrix
scanning routine and all computations would require
about a millisecond: less'than the time it takes for most
relays to change state.

: EXCHANGE CARRY WITH USRPLG
XCHBIT: RLC
A
MOV
C.USR_FLG
RRC
A
MOV
USR_FLG.C
RLC
A

Extended Bit Addressing. The 8051 can directly address
144 general-purpose bits for all instructions in figure 3.b.
Similar operations'may be extended to any bit anywhere
on the chip with some loss of efficiency.

A programmed controller which simulates each Boolean
function with a subroutine would be less efficient by at
least an order of magnitude. Extra software is needed for
the simulation routines. and each step takes longer to
execute for three reasons: several byte-wide logical
instructions are executed per user program step (rather
than one Boolean operation):_most of those instructions
take longe'r to execute with microprocessors perfor,ming
multiple off-chip accesses: and calling and returning from
the various subroutines requires overhead for stack
operations.

The logical operations AND. OR. and Exclusive-OR are
performed on byte variables using six different addressing
modes. one of which lets the source be an immediate
mask. and the destination any directly addressable byte.
Any bit may thus be set. cleared. or complemented with a
three-byte. two-cycle instruction if the mask has all bits
but one set or cleared.
Byte variables. registers. and indirectly addressed RA M
may be moved to a bit addressable register (usually the
accumulator) in one instruction. Once transferred. the bits
may be tested with a conditional jump. allowing any bit to
be polled in 3 microseconds-still much faster than most
architectures-or used for logical calculations. (This
technique can also simulate additional bit addressing
modes with byte operations.)

In fact: the speed of the Boolean Processor solution is
likely to be much faster than the system requires. The
CPU might use the time left over to compute feedback
parameters. collect and analY7e execution statistics. perform system diagnostics. and so forth.

Additional functions and uses.

Parill' ofbl'tes or bits. The parity of the current accumu-

With the building-block basics mentioned above many
more operations may be synthesized by short instruction
sequences.

Exclusive-OR. There are no common mechanical devices
or relays analogous to the Exclusive-OR operation. so this
instruction was omitted from the Boolean Processor.
However. the Exclusive-OR or Exclusive-NOR operation
may be performed in two instructions by conditionally
complementing the carry or a Boolean variable based on
the state of any other testable bit.

lato~ c~nients is always available'in the PSW. from

whence it may be moved to the carry and further processed. Error-correcting Hamming codes and similar
applications require computing parity on groups of isolated bits. This can be done by conditionally complementing the carry flag based on those bits or by gathering the
bits into the accumulator (as shown in the DES example)
and then testing the parallel parity flag.

10-59

Multiple byte shift and CRC codes.
Though the 8051 serial port can accommodate eight- or
nine-bit data transmissions, some protocols involve much

longer bit streams. The algorithms presented in Design
Example 2 can be extended quite readjly to 16 or more bits
by using multi-byte input and output buffers.
Many mass data storage peripherals and serial communications protocols include Cyclic Redundancy (eRC)
codes to verify data integrity. The function is generally
computed serially by hardware using shift registers and
Exclusive-OR gates. but it can be done with software. As
each bit is received into the carry. appropriate bits in the
multi-byte data buffer are conditionally complemented
based on the incoming data bit. When finished. the CRC
register contents may be checked for 7ero by ~Ring the
two bytes In the accumulator.

4. SUMMARY
A truly unique facet of the Intel MCS-5I T• microcomputer
family design is the collection offeature, optimi7ed for the
one-bit operations so often de,ired in real-world. real-time
control applications. Included are 17 special instructions.
a Boolean accumulator. implicit and direct addre"ing
modes. program and mass data storage. and many I 0
options. These are the world's fir,t single-chip microcomputers able to efficiently manipulate. operate on. and
transfer either bytes or indi~idual bits as dat'!.

This Application Note has detailed the informat.ion
needed by a microcomputer system designer to make full
use of these capabilities. Five design examples Were useq
to contrast the solutions allowed by the 8051 and those
required by previous architectures. Depending on the
individual application. the 8051 solution will be eas·ier to
design. more reliable to implement. debug .. and verify. use
less program memory. and run up to a.n order of magnitude faster than the same function imp'lemented on previous digital computer architectures.
Combining byte- and bit-handling capabilities in a single
micro,omputer has a strong synergistic ,effect: the power
of the result exceeds the power of byte- and bit-processors
laboring individually. Virtually all user applications will
benefit in some ways from this duality. Data intemive
applications will use bit afJdressing for test pin monitori,ng
or program control flags: control applications will u,e
byte manipUlation for parallel I 0 expansion or arithmetic calculations.
.
It is hoped that these de,ign examples give the reader an
appreciation of these unique features and suggest ways to
exploit them in ni, or her own application. '

01489A-31

10-60

ISIS-II MCS-51 MACRO ASSEMBLER Vl.0
OB'JECT MODULE PLACED IN FO AP70 HEX
ASSEMBLER INVOKED BY:
: 1'1: asm51 ap70 src date(328)
LOC OBJ
LINE
SOURCE

.....
I?
~

0090
0091
0092
0093
00'l'4

0095
0096
0097
OOAO
OOAl
00A2
00A3

0020
0000
0007
00D1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 +1

~i
ID ~

,..M

$XREF TITLE(AP'-70 APPENDIX)

t***************************************************** ***
THE FOLLOWING PROGRAM USES THE BOOLEAN INSTRUCTION SET
OF THE INTEL e051 MICROCOMPUTER TO PERFORM A NUMBER OF
AUTOMOTIVE DASHBOARD CONTROL FUNCTIONS RELATING TO
TURN SIGNAL CONTROL, EMERGENCY BLINKERS, BRAKE LIGHT
CONTROL, AND PARKING LIGHT OPERATION.
o THE ALGORITHMS AND HARDWARE ARE DESCRIBED IN DESIGN
EXAMPLE #4 OF INTEL APPLICATION NOTE AP-70,
"USING THE INTEL MCS-51

In this design N = 80, R = 20, D = 7, L = 270, and
F = 60Hz. Plugging in the numbers results in a dot clock
frequency of I 1. 34MHz.
The retrace number may vary on each design because it
is used to set the left and right hand margins on the CRT.
The number of dots per character is chosen by the designer
to meet the system needs. In this design, a 5 x 7 dot matrix
and 2 blank dots between each character (see Figure 2.1.1)
makes D equal to 5+2=7.

where
H is the number of horizontal lines per character,
Z is the number of character lines per frame,
V is the number of horizontal line times during the
vertical retrace
In this design H is equal to the 7 horizontal dots per
character plus 3 blank dots between each row which adds
up to 10. Also 25 lines of characters are displayed, so
Z = 25. The vertical retrace time is variable to set the top
and bottom margins on the CRT and in this design is equal
to 20. Plugging in the numbers gives L=270 lines per
frame.

2.2 Keyboard
A keyboard is the common way a human enters commands
and data to a computer. A keyboard consists of a matrix
of switches that are scanned every couple of milliseconds
by a keyboard controller to determine if one of the keys
has been pressed. Since the keyboard is made up of mechanical switches that tend to bounce or "make and
break" contact everytime they are pressed, debouncing
of 'the switches must also be a function of the keyboard
controller. There are dedicated keyboard controllers
available that do everything from scanning the keyboard,
debouncing the keys, decoding the ASCII code for that
key closure to flagging the CPU that a valid key has been
depressed. The keyboard controller may present the information to the CPU in parallel form or in a serial data
stream.
This Application Note integrates the function of the keyboard controller into the 8051 which is also the terminal
controller. Provisions have been made to interface the
8051 to a keyboard that uses a dedicated keyboard controller. The 8051 can accept data from the keyboard controller in either parallel or serial format.

2.3

Serial Communications

Communication between a host computer and the CRT
terminal can be in either parallel or serial data format.
Parallel data transmission is needed in high end graphic
terminals where great amounts of information must be
transferred.

Figure 2.1.1

5 x 7 Dot Matrix

One can rarely type faster than 120 words per minute,
which corresponds to 12 characters per second or I character per 83 milliseconds. The utilization of a parallel port
cannot justify the cost associated with the drivers and the
amount of wire needed to perform this transmission. Full
duplex serial data transmission requires 3 wires and two

10-67

AP-223

,-----------

' DR.,

HORIZ?"TAL

AP-223

Appendix 7.2 Dot Timing

CHARACTI!R
COUNTER
STATE

h----~~ll1n.------+l
8Uno

DOT

CLOCK

148113
COUNTER
OUTPUTS
QC

CHAAACTI!R

CLOCK

CHARACTER
CLOCK~TO

8211

CHARACTI!R~~----~I,------~~------~----~~----~~--------~--~~----~-----
FIRST CHAAACTI!R
SECOND CHARACTER
THIRD CHAAACTI!R
OUTPUT

(cco.cce)

RE~~R~----------------~--------~.Ir------Fl-RST--C-H-'-D-'C-TE~R-V-'DE--O-OUT------il,--S-ECON---D-----·-D·-CTE--R~VI~D-O--OU--~~~

-;________________~--------~'I~----__-------RA--_r----------_f

~nAnA

~ ,: 1~"'0pF+-_ 1

lK
vtOEOOUT

330

D
A
T
A

HORIZONTAL

DRIVE

B
U
S

VERTICAL

DRIVE

112 74123

CRT
MONITOR

AP·223

Appendix 7.3 CRT System Timing

r.=1 '
m.

H~C

-=l-DiJiJi!f1i.K1i1
1

1• . . • . . 1

HR,TC

I ·

HRTC
(8278)

...... I

HATC

I
I

~~~r~+4

CHAR CODE
(8276)

C~~:a~ -+-t-+~t--t-t--+-t--+---+-t---1---t-+---t"if-t---t,

:; T_. -,

LINE

SHIFT
REGISTER

J \.1-+-1-+-1--+-+-+-+--+-+-I-+-I--!--......
-+-.j....-+---+--f---.j....-+-+--+-ff+--+
LOAD
LOAD
LOAD

CHAR

VIDEO
FOR BOTH
CHAR

10-87

AP·223

Appendix 7.4 Escape/Control/Display Character Summary

CONTROL
CHARACTERS

000

BIT

001

NUL

0001 .

SOH

010

011

100

101

•

-..C

"--0

(

)

;

[

IJOIJO

ESCAPE
SEQUENCE

OISPLAYABLE
CHARACTER

OLE

110

111

010

100

011

+
+

Ii
OCI
B

0010

STX

R
OC2

0011

ETX

S
OC3

0
0100

EOT

DC4

ENQ

NAK

0111
1000

... •
ACK

.'ll

SYN
ETB

1011

1100

1101

,Q'I,

CAN

Y
EM
Z
SUB

EOS

HOME

J
1010

CLR

1001

NOTE:

RS
0

1111

1110

0110

0101

101

811_ block. - lunctlonolermlnol will react to.

0tI1.,. can bo _ _ but are ignored upon receipt.

10-88

110

111

AP·223

Appendix 7.5

Character Generator

As previously mentioned, the character generator used in
this terminal is a 2716 EPROM. A IK by 8 device would
have' been sufficient since a 'I 28 character 5 by 7 dot matrix
only requires 8K of memory. A custom character set could
have been stored in the second 1K bytes of the 2716. Any
of the free 110 pins on the 8051 could have been used to
switch between the character sets.
The three low-order line count outputs (LCO--LC2) from
the 8276 are connected to the three low-order address lines
of the character generator. The CCO--CC6 output lines are
connected to the A3-A9 lines of the charac~er generator.

The output of the character generator is loaded into the
shift register. The serial output of the shift register is the
video output to the CRT.
Let's assume that the letter "E" is to be displayed. The
ASCII code for '.' E" (45H) is presented to the address
lines A2-A9 of the character generator. The scan lines
(LCO--LC2) will now count from 0 to seven to form the
character as shown in Figure 7.5.0. The same procedure
is used to form all 128 possible characters. For reference
Appendix 7.6 contains the HEX dump of the character
generator used in this terminal.

45H = 01000101
Address to Prom = 01000101
= 228H - 22FH
Depending on state of Scan
lines.
Character generator output
Rom Address
228H
229H
22AH
22BH
22CH
22DH
22EH
22FH

Bit Output"
Rom Hex Output
3E
0 1234567
.A.AA.A
02
02

OE
02
02
3E
00

Bits 0, 6 and 7 are not used.
'note bit output is backward from convention.

Figure 7.5.0

CharaCter Generator

10-89

AP-223

10·90

Ap·223

Appendix 7.7

Composite Video

In this design it was assumed that the CRT monitor required a separate horizontal drive, vertical drive, and
video input. Many monitors require a composite video
signal. The schematic shown in Figure 7.7.0 illustrate how
to generate a composite video from the output of the 8276.

The dual one-shots are used to provide a small delay and
the proper horizontal and vertical pulse to the composite
video monitor. The delay introduced in the horizontal and
vertical timing is used to center the display. The 7486 is
used to mix the vertical and horizontal retrace. Q1 mix
the'video and retrace signals along with .providing the
proper D.C. levels.

4.7K

SOK

10K
74LS221

74LS221

HRTC

B,
A,

VRTC

2.2K

2.2K
470pF 14

lS
4

- RXCX-

.11'F

.001/LF

.OS

7
10

6800
1KO

+S - - - - . . J \ I V I r -...
VIDEO

1KO
>-___-"''VV-_..J

lS00

Figure 7.7.0 Composite Video

10-91

COMPOSITE
VIDEO
OUT

AP-223

Appendix 7.8

Software Documentation

/****.***********************************~.*.'!t**.********.*.*******.***.*******

••••• **********.**** •••• ******* •• ****************** •• ******************.*******

•••••••

*.*****

*--•••
*.****.

*******

OOF'lWllRE IJOClH;NI'ATIl"N FOR TIlE 8051
TEIfIDIAL CXNl'9JILER APFLICATICN Wl'E

*******
*****.*
*.*****

•• *.*.********.********** •• ********************* ••• ****************************
*********** •• **.********************************.***** .**.*~.**********.*.*****
MEM)R'! MAP ASSOCIATal WITH FERJPHERI\L DEVICES (USING MJIIX) :

8051
8051
6276
8276
8276

WR lIND READ DISPLAY RAMADDRESS 10000 oro 17CFH
WR DISPLAY RAM TO TIlE 8276- ADDRESS 180011 TO lFCP1I
CXMWm ADDRESSAOORESS OOOlH
PARl\MEl'ER AOORESsAOORESS 000011
srATUS RmISl'ERAOORESS OOOlH

MEM)R'{

MAP FOR READIm TIlE

KEi~

(USING M:M:) :

AOORESS 10FF11 TO 17FF11

/******************** srARl'

MAIN PIOGRNot

/* BEGIN Irl Pl1l'1'ING TIlE AOCII CODE FOR

********-*******'*******··***1

BLAM(

IN TIlE DISPLAY RAM*/

INIT:
{~'ILL 2000 UX!ATICNS IN TIlE DISPLAY RAM WITH SPl\CES (AOCII 20H)}

INITIALIZE FOINl'ERS, RAM BITS, El'C.

INITIALIZE FOlNl'ERS lIND FLAGS}
INITIALIZE orop OF TIlE em' 'DISPLAY "LINEO"=1800ll}
INITIALIZE 8276 BUFFER FOINl'ER "RASTER" =180OH}
INITIALIZE DISPLAY$RAM$FOlNTER=OOOOO}
/* INITIALIZE TIlE 8276

RESEll' TIlE 8276}
INITIALIZE 8276 oro 80 CHARI\CTElIIKM
INITIALIZE 8276 oro 25 lOiS PER I1'R!\ME
INITIALIZE 8276 oro 10 LINES PER KM}
INITIALIZE 8276 oro ~-BLIRi

BEl'WIiDI FIRSl' CIIlIRl\CTER lIND THE SIDH)

DOl

I*SIDJtID

~ TRlIN!MTl

lCIEAR

CHl\RIlCl'ER

TRlIN!MT$CXllNl'}

ENDI
END;
ELSE

001

,
{TURN THE aJRmR Cl'I IXJRnr; THE III1RYREPFATmcrICl'I}

1* 2 VERl' FlWIES BEl'WIiDI 311) 'ro Nl'H
1* 3R> THlOJGH tmI CIIlIRl\CTER. *1

IF TRlIN!MT$TOOOIE = 1 '!'HEN
CALL TRlIN!MTl
{CXMPLIMiNr TRlIN!MT$'J,'OOO[B}

CHl\RIlCl'ER

ENDI
ENDI

PIO:EIlJRE TRlINl'MlT- CN:E THE IKlSl' VE 'mE REMAINING CXNl'I!Nl'S OF 'mE FIFO UP TO 'mE BmINNIM3 OF TIlE FIFO}
ENABLE SERIAL RlRl' INTERRlPl'}
SET TIlE VALID$RECEPTICN FLAG}
IF {'mE FIFU IS EMPlY} TIIEN {CLEAR 'mE 'SERIAL$INT FLAG AND

RIilJ.Ulti}

IF {'mE NEXT CIIARl\CTER IS AN "ESC' COlE } TIIEN
DO:
{IDCI( AT TIlE CHARl\CTER IN TIlE FIFO AFl'ER '!liE ESC COlE AND CALL TIlE CX>RRIim' SUBI01l'INE}

b.u.

UP$aJRSER;
CALL· OOWN$CIJRSER;
CALL RIGHl'$CIJRSER;
CALL LEFT$aJRSER;
CALL CIEAR$SCRJ;2;N;
CALL MJV$ClJRSER;

CALL ERASE$~$VE 'mE REMAINING CXNl'I!Nl'S OF 'mE FIFO UP TO 'mE BmINNIM:; OF TIlE FIFO}
ENABLE 'mE SERIAL 00Rl' INTERRlPl'}
SET TIlE "VALID$RECEPTICN" FLAG}

IF {'mE FIFU IS EMPlY} TIIEN {ClEAR 'mE SERIAL$INT FLAG AND RIilJ.Ulti}
END;

10-95

AP:'223

IF {'DIB NEXT CHI\RI\C'l.'ER IS A CXlNl'OOL CXlIE} THEN , '

00,

'
{CALL 'DIB RIGill'SUBR:Vl'INE}

/* en:.

/* CTL L */
/* en:. M */

DISABlE 'DIB SERIAL iiOR1' INl'ERRlPl'}
K)VE'DIB RD4AINING CDfRNl'S OF 'DIB PIro UP TO 'DIB BmINNIR; OF 'DIB FU-o}
ENABLE 'DIB SERIAL PORi' IRl'ERHJPr}
SBl' 'DIB "VAt.ID$ma:PrICII" PLI'IG}

BllDI
IP {ID VALID CXlIE WAS RB:EIVD> ("VAt.ID$la::EP'l'ICII" IS O)} THEN
'l'HlOf 'DIB aww:::'l'ER oor lIND ItJUE 'DIB RI!JoIAIN[lI; CDfRNl'S OF 'DIB PIro}
UP TO _
8IilGII«'IING}

IF {'DIB PIro IS SIPlY} THEN {CIBM

TIm

SBRIAL$INT PLI'IG lIND

BB.l'IJaI}

PRlCEilJRE DISPLAY: THIS PKlCEWRE WILL TAKE 'DIB Bl1TE IN RAM IABELED
REX:BIVE lIND P!1l' IT Imo THE DISPLAY Rl\M. */

DISPLIIY:
{P!1l' IIflO THE DISPLAY RAM UJC:M'ICII 1'OINl'm TO Bl1 "DISPLAY$RI\M$POINrER
'DIB CDfRNl'S OF RB:EIVE}

IP ITHE BIID OF 'DIB DISPLI\Y MlM)RC HIlS ~ RPACHm\ THEN
RESEr "DISPLIIY$RI\M$POINrER" TO THE BmINNIR; OF THE RAM}
ELSE

{no&IIiNl' "DISPLAY$lWI$POIN'l'BR"}
IF {THE C1JRSER IS IN THE LA9l' ~ OF THE CRl' DISPLIIY} THEN

00,

{HlYB THE aJJISER JWl( ro THE BmINNIR;OF THE LINE}
IF t'DIB NEW DISPLAY Rl\M :u:oaICli HAS A BIID-OP-LINE CHARI'Cl'ER IN IT} THEN
CALL PILLI
IP {TSE C1JRSER IS CII THE LA9l' LINE OF 'DIB CRl' DISPLAY} THEN
CALL SCKlLL,
ELSE'

{1tJUE THE

,
I TIlE OJRSER ON}
CALL IJJi\D$CXJRSER;
END;
IF !TIIE DISPlAY$Rl\M$POINTER IS ON TIlE LAST LINE IN "TIlE DISPlAY Rl\M} THEN
MJI/E TIlE DISPLAY$Rl\M$POINTER ro TIlE FIRSI' LINE IN TIlE DISPlAY Rl\M}
ElSE
{MJI/E TIlE DISPLAY$Rl\M$POINTER TO TIlE NEXT LINE IN, TIlE DISPlAY Rl\M}
IF {TIlE FIRSI' CHARl'ICTER IN TIlE NEJi LINE CXlNl'AINS AN END-OF-LINE CHARl'ICTER } THEN
CALL FILL;

SCJOLL:

~~vkrICAL REl'RltCE INl'ERRlPr}
IF {TIlE FIRSI' LINE OF TIlE CRl' CXlNl'AINS TIlE LAST LINE OF TIlE DISPlAY MlM)R{} THEN
{ MJI/E TIlE POINTER "LINEO· ro TIlE BJ;X;I:NNIN;; OF TIlE DISPlAY MlM)R{}
"
ElSE
(MJI/E "LINEO· ro TIlE NEXT LINE IN TIlE DISPlAY MlM)R{

{ENABIE VERl'ICAL REll'IW::E INl'ERRJPr}

10-97

AP·223

PR:lCE!lJRE IJ:ME: 'ffiIS PIO:EIXJRE M)VES '1'HE aJRSER TO '1'HE 0,0 POSITICII ,,/

/"
IJ:ME:

foIJIIE TIlE aJRSER ~ITIClii TO TIlE UPPER LEFl' Hl\ND CORNER OF '1'HE eRr}
TUm '1'HE ClJRSER CIiI t
CALL LOI\D$aJllSER1
, {foIJIIE '1'HE DISPlAY$Rl\M$POINTER TO '1'HE OORRB:'r I£CATIClii IN '1'HE DISPlAY Rl\M}

END IDIEI

PRlCEIIJRE ERASE FR:M ClJRSER TO END OF ~:

,,/

ERASE$FR:M$aJRSE~$END$(F$SCREE}I:
,

CALL BLINEI

ERASE aJRRI!Nl' LINE ,,/

oor CIiI TIlE LASl' LiNE OF TIlE eRr DISPlAY} 'l'IIEN
TIlE NEKT LINE,PUT lIN END-OJi'-LINE CIIAR1C1'ER (OFlH)
}
IN '1'HE DISPlAY Rl\M I£CATICliiS THAT OORRESEQIl) TO '1'HE I!Iil;INNIW OF
'1'HE CRr DISPlAY LINES tNl'IL TIlE 00l'l'CM OF '1'HE eRr 9:REEN lIAS BElEN REI\CHED

IF {'1'HE aJRSER IS

srARl'ING wrm

END"

/"PRX:EIlJRE MJV$CURSER: THIS PIO:EIXJRE IS USED IN CCIiIJIJICl'IOO WITH I«)RDSl'ARIF A ESC F IS REX:EIVED FlO! '1'HE HOsr CXMF!1IER, TIlE TElMINAL CCNl'roLLER WILL
READ '1'HE, NEKT 'J:W) If{TE TO DEl'EIMINE WHERE TO mIlE TIlE aJRSER. '1'HE FIRSI' mTE
IS TIlE R:M INFOIt1ATIClii roI.IaiED m THE OOUMI INFOIt1ATIOO */

M:JV$CURSER:

WAIT UNl'IL '1'HE FIro lIAS REX:EIVED '1'HE NEKT 'J:W) CIIAR!\CTERS}
foIJIIE TIlE aJRSER TO TIlE I£CATIClii SPECIFIED IN '1'HE ES:APE ~}
foIJIIE '1'HE DISPlAY $R1IM$POINTER TO TIlE CX>RI!IiX:'l' I£CATICIiI}

IF TIlE FIRSI' CIIARl\CTER IN TIlE ~ LINE lIAS lIN EN:H:lF-LINE
CALLF~I
ENDI

DISABLE '1'HE SERIAL PORr INl'ERRJPl'}
foIJIIE '1'HE REMAIN CCNl'ENl'S OF TIlE FI, ro UP
oa::REMENl' '1'HE FIro m 'J:W)}
ENABLE '1'HE SERIAL PORI' INl'ERRJPl'}

'J:W)

CIIARl\CTER} THEN

I£CATICliiS IN MHlRl}

END I«>V$ClJRSERI

PIO:EIXJRE LEFl' aJRSER: THIS PIO:EIXJRE M)VES '1'HE aJRSER LEFl' CNE roUMI
m SUBl'R!ICTING 1 OF '1'HE aJRSER COUIfi Rl\M I£CATICII 'l'IIEN CALL LON> aJRSER */

LEFl'$aJllSER:
IF {'!HE ClJRSER IS oor IN '1'HE FIRSI' I£CATIClii OF A LINE} 'l'IIEN .
DOl
{foIJIIE TIlE aJRSER LEFl' m CNE I£CATICII}
{TURN '1'HE aJRSER CIiI}
CALL LOI\D$aJRSERI
{oa::REMENl' '!HE DISPlAY$Rl\M$POINTER m CNE}

HolDI
END LEFl'$aJRSER,

10·98

AP·223

/.
If{

PRlCEIXJRE RIGRl' CURSER: THIS PRlCEIXJRE MJIIES TIlE CURSER RIGRl' CNE COLl.tolN
AIDING 1 oro TIlE CURSER COIDlN RAM LOCATICN THEN CALL I£lN) CURSER */

RIGHl'$CURSER:
IF {TIlE CURSER IS NOr IN TIlE LAS!' RlSITICN OF TIlE eRr LINE} THEN

00;
{MJIIE TIlE OJRSER RIGRl' If{ CNE LOCATICN}
{~ TIlE OJRSER CN}
CALL I£lI\D$CURSER;
{INCREMIiNr TIlE DISPLAY$RIIM$FOINTER If{ CNE}
END;
END RIGHl'$OJRSER;

/*
If{

,PRlCEIXJRE UP OJRSER: THIS PRJC:E:IXJRi! MJ\IES TIlE CURSER UP CNE lOi
ro 1m: CURSER lOi RAM LOCATICN TIIEN CALL I£lN) CURSER */

SUBl'Rl\C'l'IN3 1

UP$CURSER:
IF {TIlE CURSER IS NOr CN TIlE FIRS'!' LINE OF TIlE CRr DISPLAY}TIIEN

00;

{MJIIE TIlE OJRSER UP CtIE LINE}
{~ 00 TIlE OJRSER}
CALL I£lN)$CURSER;

ITIIE

IF
DISPLAY$RIIM$FOINTER IS IN TIlE FIRBl' LINE OF DISPLAY MlHlRi} THEN
MJIIE TIlE DISPLAY$RJ\M$FOINTER ro TIlE LAS!' LINE OF DISPLAY MlHlRi}
ELSE
{MJIIE TIlE DI5PLAY$RIIM$FOINTER UP CtIE LINE IN DISPLAY MlM>Ri}
IF {TIlE FIRS'!' LOCATICN
CALL FILL;

/*
If{

oF TIlE Ni;w LINE aE'AINS AN mIH>F-LINE CHARI\C'l'ER}

TIIEN

PRlCEIXJRE lXJWN OJRSER: THIS PRlCEIXJRE MJIIES TIlE OJRSER lXJWN CNE lOi
AIDING 1 oro TIlE OJRSER lOi RAM LOCATICN TIIEN CALL I£lN) CURSER */

lXJWN$CURSER:
IF {TIlE CURSER IS NOr CN TIlE LAS!' 'LINE OF TIlE CRr DISPLAY} THEN

00;

{'!URN TIlE OJRSER OO}
{MJIIE TIlE CURSER ro TIlE NEKT LINE}
CALL LOAD$OJRSER;
IF

ITIIE DI5PIAY$RJ\M$FOINTER IS oor CN TIlE LAS!' LINE OF TIlE DISPLAY MlHlRi}

K>VE TIlE DISPLAY$RIIM$FOINTER
ELSE
{K>VE TIlE DISPLAY$lwt$FOINTER

ro TIlE
ro TIlE

NEKT LINE IN TIlE DISPLAY MlM>Ri}

FIRS'!' LINE IN TIlE DISPLAY MlHlRi}

IF {TIlE FIRS'!' CHARI\C'l'ER IN TIlE Nat LINE IS AN mIH>F-LINE CHARI\C'l'ER} TIIEN
CALL FILL;

10-99

TIIEN

CARRIl\GE$REl.'!lm :

MJIIE TIlE DISPLAY$RI\M$POIm'ER 'ID TIlE Bm~ OF TIlE CURREN!' LINE IN 'mf: DISPLAY MEK>R!}
MJIIE TIlE CURSER 'ID TIlE BmINNIN3 OF TIlE CURRliNr LINE OF TIlE eRl' DISPLI\Y}
'rum TIlE CURSER a.}
CALL I.OI\D$CURSER;
END CARRIAGE$REl.'!lm;

PRX:EWRE LON> CURSER. LON> CURSER TAKES TIlE VAUJE HELD IN Rl\M AND
LCW>S IT nm:> TIlE 8276 CURSER RIDISTER. */

I.OI\D$CURSER:
PRX:EWREI

IF {TIlE CURSER IS a.} 'l'HEN
{MJIIE TIlE CURSER Bl'.CK CNro TIlE CRl' DISPLI\Y}
DISABLE B.lFFER INl'ERHlPr}
{WRITE 'ID TIlE 8276 CURSER RIDISTERS TIlE X,Y u:x::ATIooS}
FlIABLE B.lFFER INl'ERHlPr}
.

PRJCEJlJRE CfIEXl{ Bl\UD RATE: THIS PRX:EWRE READS THE TIffiEE PORI' PINS 00 PI AND SET:;! U.p
TIlE SERIAL PORI' roR TIlE SPEX:IFIED BI\UD RATE */ .
. .

CfIEXl{ $BI\UD$RATE:

SET TIMER 1 'ID MJDE 1 AND
'rum TIMER 001

Al1JX)

RELCWlj
•

FlIABLE SERIAL PORl' :mrERRlPr}
REI\)) Bl\UD RATE SWI'l'CHES AND SET UP RELCWl VAUJE}
;

THl=040H;
THl=OAOH;
THl=ODOH;
THl=OEBH;
THl=OF4H;
THl=OFAII;
THl=OFIlI;

/* 00 IS

NC1l' AI.IaiED • /

150 BI\UD

/* 300
/* 600
/* 1200

/*
/*

BI\UD
BI\UD
BI\UD
2400 BI\UD
4800 BI\UD
9600 BI\UD

*/
*/

10-100

Ap·223

PRXnlJRE REI\DER: TIllS PRXnlJRE IS WRI'1'1'9I IS ASSEJoIBIH ~. 'l'HE
EKTERW. l'RXmJRE OCIINS THE 8 LINES OF 'l'HE KE'i~ AND RE1IDS 'l'HE REl'UltI
LINES. 'l'HE Sl'ATUS OF 'l'HE 8 IlEI.'!Jm LINES ARE 'l'IIm 9roRQ) IN INl'ERNAL
MlH)R{ ARRAY CALLED 0JRRENl'$KE'{ *1

REI\DER:

{INITIALIZE FIAGS "KRl0" ..0, "SIIME"zl, 0 CXlJN1'ER=0}
00 l}Nl'IL {ALL 8 KE'i~ 0ClIN LINES ARE RFAD}
\RFAD KE'i~ 0ClIN}
IF {m KE'i WAS PRESSED} 'l'IIm
I INCRIHNl' 0 CXXlN1'ER}
.
ELSE
IF {'l'HE KE'i PRESSED WAS IVl' THE SlIME KE'i '!HAT WAS PRESSED 'l'HE Li\Sl' TIME
'l'HE KE'i~ WAS RFAD} 'l'IIm
{CIEAR·"SliME" AND WRITE NEW 0ClIN REsuLT TO aJRRENl'$KEY Ri\M ARRAY}

IF {ALL 8
.DIOO'T HAVE A KE'i PmSSED(O roiNrER=B)} 'l'IIm
{8m' KEl( 0, AND CIEAR SlIME}

PRJCE[XJRE BLAII<: TIllS ElCI'ERIAL PRJCE[XJRE FILlS LINEO WITH SPACES {20H AOCII)
WRING THE scroLL IUlTlNES. *1

BU\NK:

00 1= {BEX>INNING OF THE CRl' DISPLAY (LINED)} TO {LINED + SOH}
{DISPLAY Ri\M POINTED ro Ff{ "I" = SPlICE (AOCII 20H)}
NEXT I
am;
am BU\NK;

PRJCEWRE BLINE: TIllS' EXTEmAt. PRJCEWRE BLAIIING ro TIlE WEi: OF
KEllBO!\RD THAT IS (DING ro BE USED.

SWl- SET WIlEN USING AN UNDa:XlDED KE'lBO!\RD IS ro BE USED
SW2- SET WIlEN USING A DEXXlDED OR A SERIAL WEi: OF KE'lBO!\RD

UNDEXXlDED KE'lBOl\RD- CRl'PLM.OBJ ,CRrASM.OBJ ,KE'lBD.OBJ ,PIM51.LIB
DEX))[lE[) KE'lBOl\RD-CRl'PLM.OBJ ,CRrASM.OBJ ,DElXOE.OBJ ,PLM51.LIB
DETl\CIIED KE'lBOl\RD-CRl'PLM.OBJ ,CRrASM.OBJ ,DETl\CII.OBJ ;PIM51.LIB .

*/
$SET (SW1)
$RESET (SW2)

10·102

AP-223

PL/M- 51 CDlPlLER

CRl'$OJN'l'R)LLER:

00;

/************* •••• DECLARE LITERALS .***********************/

4
5
6
7

1
1
1
1

DECIARE
DECIARE
DECIARE
DECLARE
DECIARE
DECIARE
DECIARE
DECIARE
DECIARE
DECIARE
DECLARE

UC LlTERALI.:l 'I£X:AL$LlNE$CIfAN:;E';
am LlTERALI.:l 'amISl'ER';
aJRRENl'$KE:f LITERALI.:l 'aJH:' ,OOH,3FH,OOH,OOH,OOH,
SCAN 3, SHIFf =1; M,<,>,1 *1

OOH, 'AZXCVBN' ,
SCAN 4, SHIFf =1; A,Z,X"C,V,B,N

*1
*/

SCAN 5, SHIFf =1; Y, SPACE, O,F ,G,H

09H, '(JiSERl" ,OOH,
SCAN 6, SHIFf =1; TAB, O,W,S,E,R,T

/* SCAN 7, SHIFf =1;ESC,I,·,',$,%,&
$ENDIF

'Y' ,008,OOH,' DFGH',

lBH,' 1"'$%&' ,OOH);

10·105

AP·223

PL/M-Sl CQ.!PILER

CRro:Nl'lVLLER

$E'..1OCT

j.*****·***·.******DEX:IARE VARIABLES····················/

DI!CIARE

$IF SW2
BIT M(OB4H)

INRlT

$ENDIF
$IF SW1
CAP$I.CQt
SHIP'l'$KE'{
c:x:Nl'R>L$KE'{
$ENDIF

RElG,
BIT M (09511)
BIT M(096H)
BIT M(097H)

RElG,
RElG,
RElG,'

BIT M(OB5H)
BIT M (09311)
D.\TA$TERUNAL$RE1II7i BIT M (094H)

RElG,
RElG,
RElGl

LCCAL$LINE

CU'AR$TO$SaiD

DI!CIARE (

$IF SWl
SlIME,
VALID$KE'{ ,

KE:{O,
LIIST$SHIP'l'$KE'{ ,
LAS'l'$CXNrR)L$KE'{ ,

LIIST$CAP$I.CQt ,.
$ENDIF
$IF SW2
lCVFLG,

snc,

MFlN,
KBDIN!',
ERR>R,
$ENDIF
N&I$I(E:{ ,

TRl\NSUT$'rCXlGlB ,
ClJRSER$QI ,

SERIALSIN!' ,
&:AN$IN!',
TRAN!MIT$J;m' ,
EOCSEQ,
VALID$ROCEPl'ICN ,

uc,

I!NSP)

BIT RlBLICl

10·106

AP-223

PL/M- 51 CCMPILER

DEl:U\RE

I,
J,

K,
ASCII$KEY' ,
TRAN9UT$COONI' ,

TEMP,

SHIFT,
ClJRSER$COL,
ClJRSER$COIDIN ,
ClJRSER$R:M ,
ClJRSER$CaJNl' ,

FIm,

BlCTE PUBLIC;

REr:EIVE)

$IF SWl
19

DFO.ARE LASl'$KEY' (8) BlCTE RlBLIC;

$EH)IF
$IF SW2
DEl:U\RE LASl'$KEY' (2) BlCTE PUBLIC;

$EH)IF
20

DFO.ARE SERIAL(16)

DEl:U\RE DISPLAY$RAM (7CPH) BlCTE AT (10000)

AllXILIJIR{;

1
AT (00000)
AT (OOOlH)

AllXILIJIR{,
AlJXILIJIR{;

BlCTE PUBLIC;

DEl:U\RE (
DISPIAY$RAM$POINl'ER,
RASTER,

LINEO,
L)

PUBLIC;

10-107

Ap"223

PL/M-S1 LL IiOJTINES. */

26
27

2
'1

BLANK: PRJCEWRE EK'I.'ElfiAL,
END BLANKI

28
29

2
1

}

PRJCEIlJRE BLINE: THIS EK'l'ERiIAL PRJCEWRE BLANKS FICM TIlE aJl&:R
TIlE DISPIAY LINE */

BLINE: PRJCEWRE EK'l'ERiIALI
END BLINEI

/* PRJCEWRE FILL: THIS EK'l'ERiIAL PRJCEWRE FILLS THE aJl&:R LINE
WlTII SPICES*/

FILL:
PRJCEWRE EK'I.'ElfiAL;
END FILL,

10-108

oro TIlE

END OF

AP-223

PL/M- 51 CCMPlLER

CRl'O::Nl'IDLLER

$JmCl'

/* PlIX:E!lJRE ClIEXl<

BA1lD RATE: 'IRIS PlIX:E!lJRE READS TIlE THREE KlRl' PINS 00 PI AND SETS UP
TIlE SERIAL KlRl' FOR TIlE SPEX::IFIED BA1lD RATE

ClIEXl<$BA1lD$RATE :
PlIX:E!lJRE;

9Xtl=7OH;

2
2

'.lMJD=IlM)I) OR 20H;

/* TIMER 1 Atrro RELOIW */
/* TIMER 1 00 */
/* ENABLE SERIAL IN1'EIUVPr*/
/* SERIAL IN1'EIUVPl' MAsK FLAG */

KlIJE 1
ENABLE ROCEPrlOO*/

35
36
37
38
39
40
41
42
43

44
45
46
47
48

2
3
3
3
3
3
3
3
3
3
3
1

TRl=I;
ES:a:l;
ENSP=I;
00 CASE (PI AND 0711);
;
'DU-04OH;

THl=MOII;
THl=OOCli;
THl=OEBH;
THI-OF4H;
THl=OFAH;
THl=QJ;lJf;
END;
END ClIEXl<$Bi\llD$RATE;

/*
49

2
2
2
2

51
52
53
54
55
56
57

/* 00 IS ID1' l\Lt.C:MED */
/* ISO BA1lD */
/* 300 BA1lD */
/* 600 BA1lD */
/* 1200 BA1lD */
/* 2400 BA1lD */
/* 4800 Bi\llD */
/* 9600 Bi\llD */

PlIX:E!lJRE LON> amsER: LON> amsER TAKES TIlE VAWE HElD IN lWo\ AND
UWlS IT IN1'O TIlE 8276 CllRSER RmISTERS. */

I£Wl$CdRsER:
PRX:EWRE;
IF OJRSER$QI-l TIIIiJI
0JRSER$CXlL=QJRSER$(X>UI!N;
EKl=O;

(XHWlD$AOORESS=8011;

/*
/*

DISi\BLE IIJWER INl'ERRlPl' */
INITIALIZE OJRSER CXHWID */
ENABLE IIJWER INl'ERRlPl'

PARAMm'ER$AlJ>RESS>aJRSERS(X)L,

2
2
1

EKl=l;
END UlI\D$aJRSER;

/* PlIX:E!lJRE CARRIJ\GE$1IE1.rum

PARAMm'ER$AIJ>R=Im'ER=DISPIAY$R/\M$R>INTER-aJRSER$(XID!N;

60
61
62
63

amsER$OJ~=O;

2
2

ClJRSER$CN=I;
CALL LON>$OJRSER;

END CARRIJ\GE$1IE1.rum;

10-109

PLiM-51 0 THEN
00;
C1JRSER$~KM - I;
ClJRSER$OO=I;
CALL Uli\D$CURSER;
IF DISPLAY$RAM$POINTER<5OO THEN
DISPLAY$RAM$POINI'ER=DISPLAY$RAM$POINl'ERt 7800;

ELSE

DISPLAY$RAM$POINTER=DISPLAY$RAM$POINTER - 50H;
L=DISPLAY$RAM$POlN'l'ER-aJRSER$UlMN;
IF DISPLAY$RAM(L)=OFlH THEN
1* I.O:I{ IiUR END OF LINE*1
00;
1*
CHARl\CTER *1
CALL FILL;
1* IF TRUE FILL WITH *1
DISPLAY$RAM(L)=20H;
1* SPACES *1
END;
END;
END UP$CURSER;

10-1.10

AP-223

PL/M- 51 CDlPILER

/* PRX:EruRE RIGIfI' CURSER: THIS PRX:EruRE MJIIES THE CURSER RIGIfI' OOE OOllJMN
lJi AIDING 1 TO THE CURSER OOllJMN AAM LOCATIOO THEN CALL IIJI\D CURSER

99
100
101
102
103
104
105
106

2
3
3
3
3
3
3
1

RIGIfI'$CURSER :
PRX:EruRE;
IF CURSER$COIllMN < 4FH THEN

00;
ClJRSER$COIllMN"0 THEN
00}

ClJRSER$COllJol"E1'ER1INE- WHERE TO MJ\IE THE aJRSER. THE FIRST W'TE
IS THE R:M INroR1ATIOO R)l.L()oIEJ) W' TIlE O)llJMN INroR1ATlOO */

116

117
118
119
120
121
122
123
124
125
126

3
3
2
2
2
3
3
3
3
3

M:)V$QJRSER:
PRJCEIlJRE ;
00 WHILE FIFO< 4;
/* WAIT UNl'ILL THE M:)V$QJRSER PARAMEl1'ERS*/
END;
/* ARE ROCEIVED INro THE FIR) "/
TEMP=CURSER$R:M;
aJRSER$R:M=SERIAL(2) ;
IF CURSER$R:M>TEMP THEN
00;
L=DISPLAY$Rl\M$POINTERI- ( (aJRSER$lOM'EMP) * SOH) ;
IF L> 7GlI THEN
.
/* IF CX1l' OF RllM RANGE */
DISPLAY$RllM$POIN1'ER=L-7DOH;
/* RAP AR:XJN[) TO BEGINNING */
~

~~RllM~

DISPLAY$Rl\M$POIN1'ER=L;
127
128

3
2

am~,

00;
129
130
131
132
133
134

3
4
4
4
4
4

135
136
137
138
139
140
141

4
3
2
2
2
2
2

142
143
144
145
146
147
148
149
150
151
152
153
154
155
156

2
2
2
2
3
3
3
3
2
3
3
3
2
2
1

IF aJRSER$R:MTE THEN
DISPLAY$Rl\M$POIN1'ER=DISPLAY$Rl\M$POINl'ER+ (~);
ELSE

DISPLAY$RAM$POIN1'ER=DISPLAY$Rl\M$POINTER- (TEMP-<:URSER$OOllJMN) ;
aJRSER$OO=1;
CALL LOAD$aJRSER;

L=DISPLAY$Rl\M$POINTER-aJRSER$OOILt4N;
IF DISPLAY$RllM(L)=OFlH THEN
00;
CALL FILL;
DISPLAY$RllM(L)=2OH;

00;
ES=O;
00 1=2 TO FI~2;
SERIAL (I) =SERIAL (1+2) ;
END;
FIFO=FI~2;

ES=ENSP;

END MJ\I$ (LINEO AND 7FFH));
DISPLAY$RAM(L)=OFlH;
/* ERASE UNrIL LINEO OR */
L=Itl-50H;
/* END OF DISPLAY RAM* /
ENDI
L=O;
00 WHILE L <> (LINEO AND 7FFH);
/* ERASE UNrIL LINEO */
DISPLAY$RAM(L)=OFlH;
L=Itl-50H;
END;
END;
END ERASE$FR:MSOJRSER$TO$END$OF$SCREEN;

/*
173

PRlCEllJRE IDlE: THIS PRX:EIl1RE !tJVES THE aJRSER TO THE 0,0 FOSITIOO

176

IDlE:
PRlCEllJRE;
aJRSER$1OP00;
ClJRSER$CX)IlIl=OO I
aJRSER$OO=ll

177

CALL I.O!\D$CURSER;

178
179

2
1

DISPLAY$RAM$FOINTER=(LINEO AND 7FFH);
END IDIEI

10-113

AP·223

PL/M-51 a:MPlLER

/*
180

181
182
183

2
1

CLFJ\R$SCREEN :
PRlCEllJRE ;
CALL HCME;
_
__
CALL ERASE$FIOI$CURSER$TO$END$OF$SCREEN;
E2ID CLFJ\R$SCREEN;

184

185
186
187
188
189

2
2
2
2
2

190
191

2
1

193
194
195

2
2
2

196
197
198
199
200
201
202

3
3
3
3
2
2
2

203
204
205
206
207
208
209

2
2
3
3
3
3
1

PRlCEllJRE SCRoLL

SCR)LL:
PRlCEllJRE;
CALL BLANK;
EKO=O;
IF LINEO= iF80H THEN
LINEO= 180011;
EUlE
LINEO= LINEOtSOH;
EKO=l;
E2ID SCBOLL;

/* PRlCEllJRE LlNE$FEED
192

PRlCEllJRE CLEAR SCREEN

/* DISABLE VERl'ICAL REFRESH

/* ENABLE VERl'ICAL REFRESH

INl'ERHJPl'

INl'ERRJPl'

LlNE$FEED:
P-RlCEllJRE ;
IF CURSER$JnI=18H THEN
CALL SCBOLL;
ELSE

00;
CURSER$JnI= CURSER$IVWH;
CURSER$CN=1;
CALL UlI\D$CURSER;
E2ID;
IF DISPLAY $1WI$FOINrER >17FH THEN
DISPLAY$R1\M$FOINrER=OISPLAY$R1\M$FOINTER-78OH;
ELSE

DISPLAY$IWI$FOINTER=DISPLAY$R1\M$FOINl'ERI-SOH;
L=DISPLAY$R1\M$FOINrER-aJRSER$OJUHI;
IF DISPLAY$IWI (L) =OFlH THEN

00;

I.C(J{

roR E2ID OF LINE CHARI\CTER*/

/* IF TIllE FILL WITH SPlICES */

CALL FILL;
DISPLAY$IWI(L)=2OH;
E2ID;
E2ID LINE$FEED;

10-114

AP-223

PL/M- 51 a:MPILER

CRrCX:Nl'IVLLER

/* PRJCE!lJRE DISl'tM: THIS PRJCE!lJRE WILL TAKE THE B'tTE IN RAM LABELID
REX:EIVE AND PUT IT INl'O THE DISPLIIY RAM. */
210

211
212
213
214

2
2
2
2

215
216
217
218
219
220
221
222
223
224
225
226

2
3
3
3
3
4
4
4
4
3
3
3

227
228

3
2

229
230
231

2
2
1

DISPLAY:
PRXElJRE;
DISPLAY$RAM (DISPLIIY$RAM$POINTER) zREX:EIVE;
IF DISPLAY$RAM$POINTERa 7CFH THEN
DISPLAY$iW4$POINTER~OOOH;

/* IF END OF RAM */

/* RAP

ELSE

DISPLAY$RAM$POINTERaDISPLIIY$iW4$POINTERI-I;
IF OJRSER$O)UI.!N,,4m THEN
00.;
ClJRSER$COUI4N..oOH;
L--DISPLIIY$iW4$POINTER;
IF DISPLAY$RAM(L)=OFlH THEN
00;
CALL FILL;
DISPLAY$RAM(L)=2OH;
END;
IF OJRSER$1OP1BH THEN
CALL scmLL;

ELSE
OJRSER$~R:Mt11

END;

ELSE
OJRSER$O)UI.!N>OJRSER$OOUJ4NI-l;
0JRSER$QI=1;
CALL I£WOlRSER;
END DISPLAY;

10-115

AlOJND TO BEX;INNItI;

AP~223

PL;M-51 DES THE IJ)Sl' CGlPUTER'S MESSI\GES AND IEl'Elf4INFS
CXNl'R)L lID;)JENCE, OR AN EOCAPE ~

WHImIER IT IS A DISPIJlYABLE CHARIlCTER,

THE PRlCEIlJRE THEN ICrS Aa::ORDm;u *1
232

233

234

2
3
3
3
3
3
2
3
3
3
4
4
4

235
236
237
238
239
240

241
242
243
244
245

246
247
248
249

250
251
252
253
254

255
256
257
258
259

260
261
262
263
264
265

266
267
268
269

270

3
3
3
3
2
3
3
3
3
2

3
3
3
3
3

4
5
5
5
5
5
5
5
5

271
272
273
274
275
276
277

5
5
5
5
5

278

279

DEx::IPHER:
PRXnlJRE:
srARl'$DOCIPIIER:
VALID$REx::EPl'IOO=O:
1=0:
00 WHILE (I0 THEN
00:
ES=O:
1* DISABLE SERIAL INl'ERRJP1' WHILE MJ\TIN3 FIro
K=FIFO-I:
00 J=O TO K:
1* MJVE FIro *1
SERIAL(J)=SERIAL(I):
1=I+1:

FlIDJ
FIFD=K1

ES=ENSP:
1* aw3LE SERIAL INl'ERRJP1'
VALID$REx::EPl'IOO=1:
END:
IF FIRJ=O THEN
00:
SERIAL$lNT=O:
ooro END$DOCIPIIER:
END:
IF (SERIAL(O)=lBH) THEN
00:
IF (ESC$SEQ=l) AND (FIro<2) THEN
ooro END$DOCIPIIER:
K=(SERIAL(l) AND 5m)-40ih
IF (K >OOH) AND (K TIlE SERIAL OORT. *1

322

323
324
325
326
327
328
329
330

2
3
4
4

331
332
333
334
335

3
3
3
3
1

TRAN9oIIT:
PRlCEIlJRE;
IF LOCAL$LINE =1 THEN
00;
00 WHILE (CLEAR.$ro$SlH>=1) OR (TRAN9o\IT$INT=0);
mo;

SSUF=AS::1I$KRi ;

3
3
2

TR!\I&UT$INT=O;
mo;
Eta
00;
SERIAL(FIro)=ASCII~;

FIFOo=FIrot-11
SERIAL$INT=11
mo;
mo TR!\I&UT I

PRlCEIlJRE AU'IO$REPFAT: THIS PRlCEIlJRE WILL PERFOlfoI AN AUro REPEAT FUlCl'IOO
AFTER A FIXED DELAY PERlOO *1

336

337
338
339
340
341
342
343
344

AU'IO$REPEAT :
PRlCEIlJRE ;
IF ~=1 THEN

00;

3
3
3
3
3
2

TRAN9oIIT$TOOOtE=0;
TR!\I&UT$O:XJN1'=OD OOB TIIEN

345
346
347
348
349
350
351
352
353
354

3
4
4
4
5
5
5
'4
3

355
356
357
358
359
360
361
362

4
4
4
4
4
4
3
1

FIRS'!' CllAAACTER

00;
TRAN9o\IT$COONl'='l'RAN9o\IT$COONTt-1;
IF TRAN9o\IT$OlJN'l'ooOFFH THEN
l*r:I8l.N. BImiIiEIiI FIRS'!' CIIARI'Cl'ER AND TIlE
001
CALL TRAN9o\IT;
I*sa:nm CIIARI'Cl'ER *1
TR!\I&UT$O:XJN1'=OO,
. mol
mol
Eta

sa:nm *1

00;
aJRSER$OO"'ll
aJRSER$O:XJN1'=OI
IF TRAN9o\IT$TOOOtE m 1 THEN
1* 2 VERT FRI\MES IIE'.M;EN 3H> ro Nl'H CIIAAACTER
CALL TR!\I&UT I
1* 3R:l '1'IIlO.lGI Nl'H CIIARI'Cl'ER *1
TRAN9o\IT$TOOOtE= NC71' TRAN9o\IT$TOOOtE I
mol
mol
mo AU'IO$REPFAT;

10-118

AP-223

PL/M-Sl .Mr */

INIT:
00 L=O ro 7CFllr
DISPLIIY$RJ>.M(L}=20Hr

ENDr

/*
366
367
368
369
370
371
372
373
374
375
376
377

1
1
1

1
1
1
1
1
1
1
1
1

INITIALIZE roINl'ERS,' RJ>.M BITS, Ell'C.

ESC$SEQ=Or
SCAN$INT=OI
SERIAL$INT=OI
FlFU=OI
ClJRSER$CCUNr=01
ru;=01
llATA$TEiMINAL$RFAI7i=11
'lO:N=05Hl
LlNEO=1800H1
RASTER=180OHI
DISPLIIY$RJ>.M$roINTER=OOOOHI
TRAN94IT$INT=11

$IF SWl
3~8

379
380

2
2

00 1=0

IAS'l'~(I)=OOHI

ENDI

381
382
383

1
1
1

VALI~=OI
IAS'l'$SHIFl'~=11
IAS'l'$(l)NI'R)L~=1r

384

IAS'l'$CAP$UXl(=11
$ENDIF

$IF SW2
1CVFLG=01
~=01

RiFIN=OI
KBDINT=OI
ERR:>R=01
$ENDIF

INITIALIZE THE 8276

385
386
387

1
1
1

aMoIl\ND$AOORESS=OOHI
PARl\MEJI'ER$AOORESS=4FHl
PAlWIF!l'ER$AOORESS=58Hl

388

PAlWIF!l'ER$AOORESS=89Hr

389

PAlWIF!l'ER$AOORESS=OF9HI

*/
/*
/*
/*

RESEll'THE 8276 */
NOR-IAL ImS, 80 CllARJ\C'IE1V1m */
2 1m OOlNl'S PER VERrICAL RErRl\CE
25 RJWS PER FRllME'
/* LINE 9 IS THE UNDERLINE rosITIOO
10 LINES PER 1m */
/* 0FFSEl' LINE CXJUNrER, NCti-TRANSPARENr FIELD roTRIBUTE

10-119

AP·223

PL/M- 51 CXJ.IPILER

CRl'Cl::NI'R)LLER

NJi-BLIMIJXAL$LINE THEN
00,
IF IJXAL$L1NE=0 THEN
00,
ENSP=O,
ES=O;
END;
ELSE
CALL CIIB:K$B!IUD$RATE;
LIC=LOCAL$LINE;
END;
$IF SWl
00 WHILE OCAN$INT=O;
IF SERIAL$INT=1 THEN
CALL OEX:IPIIER;
END;

~IVALEN1'

PR:lGIWtW!LE aJRSER BLIM<

/* IF IJXAL/LINE HAS

CHAtQD srAmS

/* WAIT UNITL VERl'ICAL REll'AACE BEFORE */
/* SCANNItI; TIlE KJ;Y8'JAl1D*/

10-120

AP·223

PL,IM- 51 LLER

CALL RFADER;

VALI~ =1 AND SAME=1 AND (LASl'$SIUFr$KE't=SHIFr$KE\') AND
(LASl'$CAP$LOCK~$LOCK) AND (LASl'$O)NTR)L$KE\'=L$KE't)

THEN

CALL AIJ'ro$REPFAT;

ELSE
00;
IF KE'tO=O AND SAME=O THEN
00;
TEMP =0;
K=O;

00 WHILE LASl'$KE\' (K)=O;
K=K+l;
END;
TEMP=LASl'$KE\' (K) ;
00 I=(K+l) ro 7;
TEMP='I'aoIPtLASl'$KE\' (I) ;
END;
IF TEMP=LASl'$KE\' (K) '!HEN
00;
J=O;
00 WHILE (TEMP AND OlH)=O;
~ (TEMP,I);
J=J+l;
END;
IF TEMP >1 '!HEN
00;
VALID$I 6011) AND (AOCII$KE'{<7BH) '!HEN
AOCII$KE'{"IIISCII$KE'{- 2011;
IF LLC=O '!HEN
00;
IF AOCII$KE'{=lBH '!HEN
ESC$SEtFl;
ELSE
ESC$SEtFO;
END;
END;
END;
LASl'$SIUFr$KE\' =SHIFr$KE'{ ;
LASl'$CAP$LOCK=CAP$LOCK ;
LASl'$O)NTR)L$KE't=L$KE'{ ;
VALID$KE'{=I;
NEW$KE't= 1;
END;
END;
ELSE
00;
VALID$KE\'=O;
NEW$KJ;Y =0;
END;
END;
END;
$ENDIF

10-121

~P·223

PL/M-51 a:MPILER

CRl'
17
I~

l'i

20
21
2C

OUu 1I0cA

Cst.G AICu311)
lIJMP
VEHT

,REStT RA9TEH TO L1NtO AND

fXTRiI ccue CuEIA~H)
CSfG AHu811)
LJMP
UEIAC"

,NEEUEU IF

eSfG ATC 0 1311)
UMP
dUfFf.R

,FILL a276 RUW BuFfEH

D~CUDtD KEY~OARU

SCA~

~EYBUAHD

U~Eu

j!J

OU2.s 1I0eD

2/1

CS~G

2:i

IiJI~P

ArcUHM)

Hh8UF

,STICK StRIAL INFOHMATICN INTO THE FIFU

I'SII

IPUSH HEw UStD BY I'LM51

CSfG

21
OUi!)
o IIi! I
OU21i
01120;1
Oui!t
Ou31
01l3.s
0113'1
0030
01136
OU3A
01l3e

COUO
USUOI/O
05001/0
"/8 UI
ti!
IISIIO
1J2110
uOuO
uOtO
UOOO

OU3~

Ji?

003~

eouo

211
i!Ii

~OuO
CO~O

vEkT;

3u
F
F

31
!il
H

MOV

MaY
MOV
MOVX

3'1
3)
F
F

30
37
311

INC
SETS

I'OP

POP
POP

/III
/I I

COtO
1;0112
COli!
1 HA

t,,01l3
uOll2
uOtO
OUlif "OuO
Ou51 32 .

Ace

0011

"UTtR,LiNtO

,REINITIALIZt

TU LINEO

"A~TfR

"ASTERt1,L,N~Ot1

1(0,*0111
A,ciR~
eCjj~r
SCA~

UOh
ACI.

leLR

8c7~

INTEHRUPI

~LAG

,INCh CUHSER CUUNT RtG1STEH
IFDR DEBDUNCt HOuTINE
,PDP flEGlSTEHS

PS~

"ErI

lie
Oull1
OUH
DUll!>
OuII7
OUIl'l
OUIlIl
Oullll

PU:'H
PUS,",
PUS"

Qj
Q4
4~

lib

47
1111

IIU~ f~~;

I'USI<
I'U~I<

I'US ..

IFILL ti216 RUW 8uFrEH
,POP REG IS I EllS

IICALL.

II~

I'OP

511

1'01'

;PUSH ALL HEb UStO BY

I'USH

POI'

1'01'

50S

~EII

10-123

PL~51

COuE

AP-223

"!;S-Sl

,d"R"

SVM~OL.

I_liLt L.hT!Nb

N • II

ACC,
IlLAI\K.

··

L.
LINt.O.
NUTYE T
DvEH •
D~EIH •
Plllr.T.
Pfili.
RASIE ..

SHIV.
il:N.
THltcTY
TH"'l""
hEr."
VI:,RI

·
·

C
8

0
0

···

St-IIlN!

e
C
C
e

GUeAe~

St. VNTY

OuEu!'
oua::.!'
OUAIIH
OU!I'H
OlAJH
OullllH
ounl'

C
e
e
C

·
..

S!;Ar. •
SI;RI:IUf
St.RUL

0 Aue ..

C
C

F lFTY.
FILL
FuRTY •

Sbllf

VAL U

C
C
C

·
··· · ·

F1Fli

T YP E

c Aue"

IlLII~£.

BUFfE"
CHECK.
CUNll.
CullT2 •
CUU .. T.
CuRli!I<
OIlOI~E •
OMA.
OMAO"'I:
DONI:,
OPH.
OPL.
UGHTT
ESCliEw

e
e
C
D

a
a
0
B

°
· ··

•

CWTASM

AS:.E~8L.f~

e
e
e
C
B

AUOl<
AIIO"
AUO ..
"uO"
Al.ltl<
A1.10 "
AUO"
AuOI<
AuOl<
AIIO ..
AuO"
AUCK
ADDI<
AuOH
AIlOH
AUC ..
AuDH
AutH
Aile\(
AIICI<
AUOI<
AIlDH
AIlOl<
AIlOI<
AuOR
AuOl<
AuO ..
AIlCI<
Aile ...
AuCk
AUOl<
AUCI<
ADOH
AIIDI<
AUel<
AUOl<
AuDK
A"OH
AIIOl<
AuOl<

AT T R 1 8 L T E 5

A PU8
A' PUB
A
A
A
A
E~T

OuFIIH
OuFAH
O,BdH
OlSQH
ouelM
OuecH
01A1H
016:1'"

OOCOH
0151101
OuaQH

A
A
A
A

EXT

A
A

EXT

ExT
A
A PUB
A
A

EXT
EXT

OUHH
Ou!S'lH
Ou711H

A
A

OIlOIlH

01l9'1H

OUSeH

OleUM
017'1H
01 f:lM
01!IIH

A
A
A
A

01i?~H
OU2~H

A
A

EXT
EXT
EXT
EXT
EXT

EAT

REGlSTE" IIAhKlS) uStC: U
lSSEIII:IL Y !;DMPLEre, r.c

E~RUA~

~OuNu

10-124

AP-223

Me8-51 IIA"Ru
lUC

OBJ

OUSe
Ou,S,
0<151
Ou59
Oti5e
Oust.
OIl&U
Oubi!
0064
0060
0060

309'1u4
Cl9'1
F
ulllO
i/O"'!e8
LOOl
A'I9'1
Ci!98
LOIIO
COt.O
COuo
F
LlIIO
F
OllbA 14110
F
,ou&e ~500
Ou&E F8
OU&f' t.q
0111\1 4,;li1
ou1a F6
01l7l bG1BIli!
F
007& DlOO
F
OU7et u5uO
F
OulA ui!UO
0111' uOIiO
Oll1E jiOtO
01l8u DOUO
OUIIi! LlOUI
Ou84 l2
Ou8~

0081
Oua..
0081:1

COIlO
CO.:O
COlli!
COo!
COUO
851101li! F
85UOb3 F
1850

(H,8u
01l8f
OO'lc
OU'l!!
00'17 III~O
OU'l'l fO
Ou'lA A3
OU'l1l u8rA
ou'lu
OulIF
OUAl
OuAJ
OuA~

uOUO
00113
uOlli!
1I0t.0
uOuo

OuA7 ,,2

CHTAS",

AS:.EI"R~e"

llt.~

511
51

So
5~

611
61

6c
U
6~

6!i
6b

61
61:1

69
111

7e
7J

7'1
1!i

16
7(

111
H

81
80l

83
811

lIOuRI:E
I:iEftBuFI IN.
(;lH
/jEre
JB
uveR'
I'U:.H

11'1911AI\ 1.,1

DLANIIJ

PSI'I

811
81
811

89
'IV
'I~

,H lRANlIMlT BiT IItolT au THh C14fC4\ HECElVf.

,ClA THA~SMI:'S~O~ !NfEHA~PT FLAG
;UTii TRAllli Ii'll fOw PLM51 :tUTus CHECK
U:'M
PU::i~

,.CL

i>Ul;i1'
I'U::i1'
PU:'M
MOV

"PI.
uF"

111

MO~

11e

URL
MOv

.\lq

1l~ 1;0hTli
ill>
111
1111
11'1
1211
121
122
12J
12q
Ii!:'
1211
121
12d FILL:
129
1311
131
132

13J

13'1
13~

130
137
1311
lH CONTe! I

140
141
14e
14J
14q
14~

141>
141
1411
14'1
1511

151
,Se +1

MOV

,PuSH

I"S~

lOb
101
lOCI
109
11v

uOtl

uPH.I'C!NI

IIPL.I"CH'I+1
IiP~.UuH

"O.C"R~EH

A• .cUM

MO~X

.O~TH.A

lNe

IlPIR

IN~

,GI:T

kEijlST~R:'

cuRHE~T

POP
POP
I'OP
PO ..
POP

HEr

BY PLM51

01SPLAY RAM

LUCAT10~

,SI:T BIT, l~ tOH hAM AOuRI:SS uECOulhG
,GH C~A~Ek COLUMN I~FO 10 T~LL HO~
,FAR IhTO THI: HO~ YO~ ARE
fASCII S~A~E CHAriACTt.R
,MOV Tu UISPLAY HAM
,INCH TO h~Xl ul~PLAY HAM LOCATluh

CJNE HO •• SOH.COI~T1 ,IF NOT AT THE
, CONTlNUE
POi> 1I0H
,PUP At:GUlEHS
POi> I.IPI1
i>OP uPL
.. Oi> ACC
POP PSi>
HET
PUS ... .. U
PU:;~
ACC
i>UI:iM UPL
I'USM OPH
PU5M 00.,
ClM C
IiP.,.L
MO~
MOV UPL.L+l
URL UP.,.UuH
MOV HO.UFH
INC IIPTR
MOV A•• 2UIi
I'IO~X .OPTH.A
INI. liPT"
UJNZ' HO,CUt.H!

US~O

,P~SH HEGISTI:R~

EI~D

Ot TMt. LII.E

USI:D BY PLM5l

,GET BI:GUH,lhG O~ Ll~E RAM LOC_TJDN
,CALI.ULATEu ~Y PLMSl
,SET BIT 15 fOH UISPLAY HAM ADuRt.8Ii uECOUE
,SET UP CO~NTEH FOI( SOH LOCATluNS
,Gil PAST THE Of1H
,ASCII SPACE CHA~ACT~R
,MUVE 10 DlS~LAY RAM
,INCH lO NEXT Ull:iPLAY HAM LOCATIUN
,If ALL H L~CAno ... s HAVE NOT IIEEN FILLEu
,THEN COI\T1NUE
,PUP RI:GlSTEHS

UOH
OPH
LlPL
AC,,"
PSI'<

iIIEJEI.T

10-126

Ap·223

"~S·51

LuC

MA~R ...

AS~haL.fk

U/o,e

uP J

C"TA5~,

~OuR~E

ISJ
15~

OuFo

~ldB

OuF.
OuFLi
OIOv
0101
OIOc
010:.
0101>
0107
010b
010'11
OIOA
OIOb
010C
0101.1

!!SUO!!3
o5uObi!
e.O
A3
"Oo3~ 3
1:.0
A3
1:.0
A3
1:.0
A3
1:.0
A3
1:.0
A3
<'0
A3
e.0
A3
1:.0
A3
1;.0
A3
1;.0
113
1;.0
A3
e.O
A3

0101:.

o 1 O~
OUu
0111
011e
011j
011'1
011~

0110
011.,
01111
0119
OllA
01111
011~

011U
Ollt
011F
01211
0121
01U
012~
012~

012!>
0120
0121
01211
012'1
OIU
01211
0121.

1\3

F
F

1'5/
i51l
15'1

1.I0"NI:.I

flJMP

Ii~ACI\E

16u

LiMAI

MOV
MOV
MOVX
LNC

",PII."A:JTc.R

H'i

He:

16's
H:'
1611
16.,

1&0
169

171
17.:
173
17'1
17!:>
1711

i71
17d
17~

18Q
1~1

18~

18b
lR7
1811
18'1

l'lU
I'll

.'1 ..

113

1;0
A3
100
A3
1::0

I'IJ
l'I ..
~'1:i

1'10
.'17
1qll
1'19
~OU
~O1

~Oil

':O,s
':0'1
ciO!>
eOo
cOl

Ol2\) 1:.0
012l A3
012~ 1:.0

I&~

l@o!
183
18'1

~OuTI~t

TENI

I'IOV)(
LNC
MOVX
INC
MOVX
IN(,;
MOVX
LNC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
LNC
I'IOVX
IN~

MOVX
IN~

MOVX
INC
MOVX
INC
MOVX
IN'
MOVX

lNC
MOVX
I'"
MOVX
INC
IWI:.N1YI MOVX

LN'

MOVX
INL
I'IOVX

LNC

MOVX

~C~E~

UJ~PL.A'

~FL."ASh.Rt1

~AM

uATA

HO~

~UfFtR

ITHI~

;+++++++++++++++++++++++++++++++++.+++++++++++ •• ++++++++t.t •••••••••

",0
A3
t,0

,tt.+.+ ••••••••••••••••••••••••••••••••••••••••••••••• +t ••••••••••••

IS~

150

ijl16

;LliAII .nR PuJI'th,A Hl(OlI ~YTE,
ILUAU .FtH Pllli\HR LU\'4 11Th,'

A... Ol'lll
~FTR

IIUI- ,'CIIO"E '
A... Ol'h
,uP IA
A... Cl'l"

LIP IQ "
A... e"ll(
liP I,R

A... Cl'l~
uP] R
A... Of'll(
UP Hi
A... CI'TI(
IIPIR
A,'.01'111
'uPIR
A, .. OPTK
uP IR '
A,.Ol'll(
liP IA '
A•• Ol'll(
uPTR

A; .. OPTII
IIPIR
A, .. OI'lI'(
IIPIR
A, .. OPh
"FIR
A, .. OP1H
UPIR
A, .. Ot"K
IIP1~

A... Ol'lH
IIF 11<
A, .. OI'TIC
",PI"
A... el'T"
IIPI~

A, "\l,n K
~P1R

A... CP1"
. LIP TR'
A... Ct'TIC
IIPl"
A, .. CI'Tw

10-127

lIt INll HIGH, TI1EI\ LIMA U

aVE"

AP-223

I'I.S-51
LuC

~tA\.lIu

vl!J

013U A3
0131 toO'
OUi! A3
01!J ~O
o 1 !It A3
013~ toO
013t. 113
0131

01111 Al
011<; c:0
~13A ('3
Olla 1:0
013C A3
OULl toO
OUto A3
OUF "-0
0111U A3
o !Ill 1:0
0111.: Al
0111j c:0
011141 ,,1
0111; 1:0
,0111b A!
01111 1:0
011111 A3
014'1 toO
0111A Al
011111 1:0
Ollie A3
0111U 1'.0
0111t ,,1
0111~ 1:0
015U A3
0151 ~O
015.: A3
015l e.0
0154 ,,3
015:; e.0
01511 Al
~151 toO
01511 Al
015'1 to
015A ,,3
015D toO
0151. A3
01511 1:0
015t ,,3
015f e.O
01&U A3
01"1 1:0
01&': Al
01&j 1:.0
OU.II ,,3
011.:' t.O,
01110 A3

AS:iEIY.BLE ..

L!~~

C",USt,

:,OvIlI.E

.:011
.:0'1
.:U
"I!

':\e

"1~

"lq
,,1~

':'\D
.:11
,,1/1
ct ..

Ci!U
.:21

.:u
c~J

.:24
.:~~
~~b

':21

.:ael

.:2'1
illll
':3,
':l~

c3J
.:311
c3!i

':3D
c3"

,,311
':39
':11\1
~lIl

':lIet

"IIJ

e/l"
ell:>
':lIb
,,117
,,1111
':11'1
,,511

':51
e5':
,,5J

lNI.
MOVX
lNI.
,..OVX
lNI.
MOVX

A... Cl'l"
"PIR
A... OPh
"PIA
11 ... 0;-1"

I~C

IIP1~

MOVX
lNC
MOVX
lNC
MOvX
IN'
THIR1YI MOVX
INC
MOVX
lNC
MDVX
INC
MOVX
lNIl;
MOVJC,
INC
MOYX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
fO"'TYI MO~X
INC
MDVX
INC
MOVX
INC
MOVX
lNC
MOVl(
lNC
MOVX
INC
"'OVX

':5 ..

1"11.

c5~

Mevx

.:511
.:51
,,51!

MOVX

INC
U~C

c59
':6u
~61

efoe!

~UTY:

rlOVX
I1>;C
MOVX
INI.

IIF1~

A... Cl'l"
'III' Iii
A... Cl'l"
uPIIi
A... CPh

uPIR
A... Ot'h
",P1R
11 ... 01'1",
IIPlR

A... CPT"
UPTR
A... OI'T"
"'PTR
A... CP1",
IIP111
A•• OP1"
UPTR
A.":OI'T"
uP11I
A' •• OPT"
uplR
A. "OPTIC
IiPJA
A,.Ol'l ..
UPTII
A,.O .. ll<
liP Iii

A,.OI'Toi
UP1R
A... OPTH
UPIR
A, .. C.. T~
Iip]R
A... OI' 11<
UPTR
A•• 01'1"
IiPIR
A•• OrT"
uPIR
A,.OI"I<
IIPIR
A•• O.. ll<
uPIR
A... C.. 11<
vPTR
A•• Ol'''''
IIPIR

10-128

AP-223

"\oS-51

~,A\oRU

A5:,e"'~LE ..

Cl(lASM

LvC

U~J

011./

~6j

,,3
016'; 1;0

~6"

l~L

,,6:>
,,6b
11.67
e60
,,6'(
,,7V
,,71
c7e

Mev.
lNI.
MOVX
1"(;
MOVX
INC
\'IOVX
IN(;
MOVX
INC
MOVX
INC
MOVX
INI,;
"'OVX
IN(;
MOVX

01,6~

OH.A

OUa 1.0
0161,; A3
01f1U ~O
016l 113
016~ 1;0
017U .3
0171 ~O
017e ,,3
017j 1:.0
01h A!
017:> to
0170 A3
017i

01711
017'1
017A
01711
0171.
017U
Oln
017f
OlaV
0181
018e
OHI,3
Olh
018:'
0180
0181
01611
0169
018A
018a
018(;
0181.1
0181:.
Olef
01'1V
01'11
01'1c
01'1')
01'i141
01CJ!l

to
A3
t.0
A3

1:.0
A3
1::0
A3
1:.0
A3
1;0
A3
~O

II!

1;;0
A3
1;0
43

1:.0
A3

A3
1;0
A3
EO
A3
~o

A3
toO
~lljb A3
01'17 lO
01'111 A3
0199 ~o
019A A3
019b ~O
01'1!;. A3
01'11.1 1;;0

L!~~

:'OURLE
"'O~X

e7~
,,7~

':75
e70
,,71
,,71!
c7'f
o!8U
ol81
,,8ol

"ej
o!84
o!t'~

c80

eel
e8ll
<:8'1
,,'IV
o!'!l
o!9c
c!'!.3
,,'I"
cCJ~

c!CJo
"CJI
"CJII
j!CJ'f
30U

301
jOil
30.3
030 ..
JO)
jOb
JOI
JOIl

J09
J10
J11
j1.:
JU
J1q

~IATYI

INC

MOVX
INC
MOU
INI.
MOVX
INC
MOVX
IIIIC
MOVX
INC
MOVX
INC
MOVX
IN(;
MOVX
INC
MOYX
IN(;
liEvNfY I MOVX
INC
MOVX
1NI,;

MOVX
INC
MOVX
1ll:C
kOVX
INC
MO~X

lNC
MOVX
IN(;

Ji)

M()~X

J1b
:HI

!II:I,;

Mevx

A, .. O"l"
IIFl"
A, .. Cl'll(
liP I';

A,,,CI"T,,

"FIR
A, .. Ol'l"
UPI"
A, .. Ct'ln
liPt~

A, .. Cl'l"
uPlfi
A, .. Ct'TI(
UPtR
/\, .. Ol'lIC
IiPt"
A, .. Ot'T"
uPIR
A, .. Ot'TH '
IIPIR
A,,,Ot'TH
IIPT" '
A, .. OI'TN
UPIR
A,'"OPTIC
IIPTR
A,AOt'TN
LIP /R
.,AOl'lH
UPIR
A,AOI'TH
UPIR
A,.Ol'lH
uP'R
A,.OPTN
UPlR
.,.01'1H
.. PH
A, .. Ot'lN
uP'"
A,AOl'TIC
IIPTR
A, .. Oi'l"
IIP1R

A, .. Ot'lH
UP'R
A, .. Dl'll1
liP ]I.

A, .. CPTH
IIPIA
A, .. Cl'lH
IIPI"

A, .. CI'T"
UPI~

A, .. C~l"

10-129

AP-223

MLS-51 MALRy
LUC

uBJ

olilt.

,,3

AS~hllL.EI<

UI'.t.

HI'

A, .. C~T"
"PIR

~IOVX

A,,,C~lH

11\1.

"PtA

j21
jj!j
Jii!'i

Jii!~

01AI> E.511ii!
01AA d4UOij1
01AI) 15UO 18

7~QOijO

Jii!b
Jii!7
Jell
Jii!9
J!ij
J!1
He

01lIJ d
F
F

t.lbHTY:
I.Ht.CIII

MOV
(;JhE
~IOY

'JNE
MOV

HAntR,.18n

~,Ov

rlA~TI;I"l,*uOI1

MOY
MOV
ICET

HII
331l

1I,*OUOI1,uO"E

tiEl

J3<1

HI>
J37

A,UP"
.. ,U~I1,DuNt
A,,,PI.

J31
J3~

01811 (;3
018C; 1;511ii!
018~ r:!411F
01Cu F511ii!
OlCe :aOUF
OlC" u5t13
OlCb 1I0U8

"~lR

r.Ovx

~41FijC

018 .. b5t13uO
0187 /l5l1eijO
01BA Z2

IN'

jl~

J2u

.lU

01A" 1:.5113

olfilU

:'OURI.E

jl~

0111f 1:.0
OUU 43
01.1 to
OlAe! A3
01A~

Cr;TA5~,

LlO"EI

IlMAONEI CLH
MOV
AOU
MOV

IN!;
INC
lUMP

~IIII

J41
J4i!

hAlilI:.R,Dt'H

tdlJ1I;hl,OI"L

A,LlPi.
A,.HD
UPI., II
LI't.CII

"PH

C~I:;Co\

J4j
JGII

JIIlI

"'Nu

10-130

,.lOU 79 Tu ~UFFt.R PUINTI:.R
ITO GI;;T Tu t.EXT D18Pi.AY L1Nf
'IN THE Dl&PLAY MEMIJRY

AP-223

I~I~-lI ~~S-51'~'~R~ 'S~E~8LEk ~2.1
C~J~Cl ~OuULE PLALf~ !~ l~l;KtY~D.ODJ
'~S~~DL~R I~V~K~~ A,;
AS~51 ;Fll~ETBU.~R~

l.IIC

u8J

~OuR\.E

c:
j
~

0
1
II

IV
11
1~

1.)
111
15
111

J* __ ••••• _.a_a*_. __ * •••• __ ._._ •• __ ._._._ ••• _••

*_. ____ .a,*.,a,_a._aa __ • __ _

*._---•• a,*,*a",'*'t,a,.,.

J****.- ••• *_.a._._ ••• _. __ • __ • __ •• _-_._._-.-_ ••
Ja'*'
,._.~OrThA"E
FuR RtAUI~G AN uhuE~OUEu

"'_
• __ _

,._..

.-.-

K~YDOAAU

a'a'
.*._ .. __ .___ ._ ..... ___ .. _*._* __ *__ * ___ a._.
,*_* •• *"a"att*., •• *_* __ • __ *__ •• *.,.* ___ **_, _____ ._*,*.* __ * __ a _____ ._. __

J'-"
J****.a*.aaa __ a •••••• _. ___ •• ___

,,,

rHIS
THIS

CuhlAI~1I lHt 1I0fT~AkE NtEUEu TO S~Ah AN UNDtCuO~D KtYIlOARU
PWC'~A~ ~uSI liE LIN~EU TO THE ~Arh PRUGkAMS TU FUNCTION

111
19

l!V
21

H~~URY

MA~

fO" HEADING

iii!

ADUR~S~

tCH

~EY

~OARD

~EY

~OARO

lU5ING

~UV~)

10FFH TO 17FFH

illi
2~

ilo
il7
ilil

29
3\1

31
3~

H
311
3!1
31> t1

I'UbLIC RUDEH
~XTAN uATA (LaTKEY)
tXTAN gIl lKtYu,~AMEJ

,-*-.-....... _-.. _.-.'_ ..... _**. __ .-••••••• -._.- •••• _.**-•• _*_.-... _-_._.
I

I·

.
•

,.,_a.* ••• _••••• _•••• _••••• _. __ .*._. __ •. _.*_. __ .. __ *___ • __ .t ... ________ *_*
,-

.eJE~!;T

~RtADE"·WOUT1N~·

•

AP-223

/oI,,5-S1 ",."I'/I,j AS:.HijLE ..
LuC

uBJ

Ll~L

Kt.Y"O

bOuR"E

! I
]11

3'f

~N~E"OuEu_KEY8u."C St.G~E~T
U~DtCI,jD'O_K'YIICAR~

CUOt.

"5tG

~II

~"
4,s

OuliA ei!

ItEADt.RI I'USM
PUSH
I'U::;I'
4:1
40
PUSI'
,",USI'
H
411
I'UI:I"
Q
OUOIl
OuOA
ouoe
01i0t.
OU10

COuO
~O,O

COo2
~O1l3

COuO
caUl
equ2
eou3
'iOIOfF

Oul! l'IuO
Ollt~

1800

'/8ue
L200
li2110
0602

0011
Out'il
Outll
Oulu
Outl'

O~?,O

F
F

0021 Fa

Ou2c bOUS
Ou24 tlSUU4
Ou27
OU29
ou211
ou2t.
Ou2F
Ou31

11005
U501
IISU21D

u!i1l3
UAt:A
oon 0'108011
F
OU36 U200
00311 C2UO F
.01131. U003
0.v3(' (lOU2
Ou3t. UOUI
OUIIO IIOUO
Ouai! uOC13
OU44 110112
\ 011410

DO~O

OU411 UOIIO

IPuSH

I'h

"E~

uStD 8Y I'LMSI

AC"
liFL
UP"
~O~

Uln
,~2H

U3H
uPT~,UOI'FH

"I"OOH
teO,IIL5IKt,Y
1<3,1I08H
KEYO
SA .. E
02",aiRO

,INITIALIZ~

,AIlDjjEU
,CLR ltRu

uPTR Tii KE'BUAHD

COuNTE~
K~YbOAA~ teAM

POINTEH
,INITIALIZt LOUP CUUNTtR
,INITIALIZt. PlMSI STATUS BITS
,G~T

,MUV LAST KEYBUAKO SCAN 10 Oi!M

",,,".DPTH
A
lEHO
A. u2H, NTSAME

,SCAN IIEY8uAHO
,INVtRT
,IF bCAN ftAS ZtRU ~O INCHEMENT ZiRu COUNTEH
,CUMPAHE ~lTH LAST SCAN IF NOT THE S"~E
,THEN eLR SAME B1T AND ~riITE NE~ INFURMAlIu~
,Tu HAM
,IF tQUA~ JMP UVt.R INCH OF URU COuNrEM
,INCH ZERO COUNTt.R

I;QUAL
ult;

A.02H,NTUME
kQ
liP'"
H3,I/URI;
kiII/OSh,bACK
liE 'to

,STEP TO Nt.Xl ~CAN RAM lUCATION
,Nt.XT KEYBOAHD AIlDRE~S
,IF LOOP COUNT~R NOT 0, ~CAN AijAIN
,ChECK TC $EI; l' ALL 8 SCANS wHERE 0
,IF YES SET KEYO BIT

U .. E

0311
02"·

,POP fll;lOlSTEHII

11111

00"
UPIl

UPL
Ace
1'811

8'1

NHAME;

MO~

.. ~O.A

ClH
liJMP

~.~,E

Ou4\. 1.:2uO
OU4, 1I0liE

SI
8c1
89
qU
'11

t.,uAL

,IF ~CA~ ~AS NuT THE SAMt: THEN PUT NEW
,SCAN INtC IwTU HAM
;eLR SAf't. all
;GU UO IIURt

tNu

10-132

AP-223

'" •

v P

··

ALC.
BAC",
01' ....
OI'L.
EwUAL.
KI;YI/ •
UiTl\EY
"URI;
N1SA!'.t
p;,~.

0
C
0
0
C

··
· ·.,
··
·

SAMt;

ZtRIJ

· · .....

RtGlSTEIC

IlAt,1( (SJ

AuOW
A"Ck

01l8~14

"AA

o II 2 E'"

OUluH
OU40:1'"
Ol/OUH
OIiOUH

R
R
A
R PUB

Aue"

AUCk
AUOw
Aue"
AUCk
Autk
e Auek
C StG
C AuOk

USte I

A T T R I BUT [ S

AUC"
AuCk

0
C
C
C
C

U~OtC~OtD_Kt'DDARU

VAL UE
OUEII ...
01/34 ...

e AUOW

REAuEfc

oues ...

5cG;L~O~CyOtO_KtYbOARU

EtGaLhO~CuOtO_KtY~DAR"

EXT
ExT
8I;G;L~0~CUOtO_K~YDO.Ru
StG;L~O~CUOtO_KEYbDARU

SI;G;LNDtCUDtD_KEYbDARU

EXT

OQ5UH
Oll29H

·/it;L;I.NII

StG;~~OtCuOEO_Kt'DOAR"

Al>St;/lIILr COMPLETE. t.C [kRuR:> fOuNu

10-133

AP-223

Dt.CIJOt
I~I~-.I

~~S-51

~AL~~

~S~E~BLEK

ObJtCT

LIIC

UBJ

v2.1

,.IIOtCuOt.USJ

~OUULE PL~L~~ .~
A~St~bLt~ I~VuKtD ell
A5~51

;F1:IJECOUE.S~C

Llt;t
c!
~
~

I
II

IU
11

**._._---

J**************************.************.*************
I-*t._
••• _•• _•• __ • _____ • ___________ *••• _••••• _._ •• _. __ * t t ' t t . t .
J****
_._1****
~OfT~A"E FUR DtCUOEO K~YIIOARu
****
Jt,t_
_a ••
_t.', __ * ____ *_*_ •••• _____ • _____ •• ,._._. ___ ._.***_tt.tt
; •• ****************** •• ********************************a* __ •• _.

,.***_ •••

I
I
I

Ie:
IS
1b

11
111
1'1
20
21
U

PUIIUC DtTACh
EXTR~ UAfA (LS1KtYJ
EXIRN dIT (~8~IhTJ

1*
*
.·CtCuD~· INTERHUPT RUUTI~E FUR DECODED KEYIlDARuS
*
1*
1******·******************** •••• ·*.·**.******** ••• ···.***** •• ******

i!~

I·

241
2:.
211 +1

IiEJECT

10-134

AP-223

"'(.5-51
LIJC

M.C~U

AS:.E~·BLE"

uBJ

L~H

(ItC"O~

~OuR(.E

211
i''I

UEI..OuEu_KErBuAwC StG~E~' C\lOt
wStG DtCUOtC_KtV~CA~u

OuOu ~OuO
OuOc ('Ooi!
OU04 .. Oel3
ouOt> CO"O
OUOIi \lOoO~F
OU~b t a
ouoe 93
OuOU ~5~0
F
ouOF Ui'!UO
F
OUl1 15dC~F
Old .. 15d.r F
OUI7 UOtO
OUl9 "Od3
OUID uOeli'!
Oulu UOuO
OUIF ji!

!I
3.:
3.5
34

uE U(.H: I'U:...,

Mev
CLH
MOVe
MOv
I:>ET8

"U~H

30
31
311

4U
41
4o!
4:$
44

.wF~

I'CSt<

.AC~

1010'1

MOV

1'01'
1'01'

POP
.. OP
KElI

IPUSt1
IUI:>EU

1'5~

"PL

I'US'"

UF'I.,UOfFt1
A

I AUDICEI:>S FI/R Kt.VelOAHU

A,,,~+OP'IC

IFtTCH ASCII eYTt
IM\lV T~ ~EMOHY TU elE Rt.AU bY PL~~l
ILt.T PLIo!~l Kt~OI\ IHtoRt. 18 " BYTI:
ISI:T C~U~Tt.R TU ~FFFH ~O INTI:RICUPT
ION THE ~E~T FALLI,.,G EliGI: UF TU

LSln'+I,A
I\BuI,.,'
ItJ
641

OuOU

~OuO

OuO.: ~0t.0
011041 ':Ou013
OU07 c:Otjll4IA
oeOA 1i2uO
oooe 7StlCfll
OOOF 1StllUO
oute: .. S69
00141 ~2"2
Ouh FSo9

oU111

oO':B

OulA
Oul11
OU2U
OU2.:
OU2S

cOuOl0
c:01l1ll4
1)2uO
7SUOIIO
7SClCt8

60
F

fl7

611
6'1
711
71
71/
73

741
F
F
F

OU211 7SIIlUO
01l2b

11018

OU211
OU311
OuH
Oil311
00311

(5e1et8
75111110

.:Ou014
t5~0

YALIul

NXT81TI

811

F
F

81
811
8'1

9.:
94

90
91
90

JB
JB
:lETB
MOY
MOV
MOY
IIJMP

II~ 11

1'811

kEijISTtR~

YS~O

BY I'LM51

,IF I(E~Elllt fLAG StT GfT Nt~T lilT
,IF TO 1& II 1 THtN NUT A STlHT BIT
,If TO IS U IHtN II II IITART bIT
,S£T Tl~£R TY IN1EkRuPT IN THE "IOOLt UF STAHT 8lT

",lllliO
UEd'
1"100, A

,StT

TI~kR

CUUNTtR TY lIMEH MOllE

FII\I

,GU bACK TU I'RUGKlM

IIYl\C,IIUIIII

,CHE~K If VALlu IITART bIT HAS lIEEN SkEN
,IF NOT CH~CK 4F VALID STAHT BIT
,IF YEa IIET liYNC
, INIT lliTilEY

l,.,PlI, ICS I

SYNC
L8"lKtY"lIOH
r~ U, "IIUUGE 1
TL 0, ,,"IiSU.EO
1'1,,1

I .. O,II11tSUliEl
TLO,IIHSSAliEu
IIYfIN,IITUP
A, LSTKt Y

MOY

C, l~f'ld

,SET T!MtR FUR 1 81T TIM£
,AND GU HACK TU MAIN PHOliRAM
,SET TIM~R FIIR 1 B4T TIME
,CHECK TO SE£ IF ALL 8 BITS HAVE BEEN HECEIYtO
,GkT ~URKING RtG1SIEH
,GET Nf~T dlT fRYM Tl

LSIKtY,A

FJi\I

SETa

IIYfJI\

Cll(
MOV

uE7~

1'01'

LSlKI:Hl,1
ACC

POI'

1'80\

KETl

,PYSH

ACL
HCvFLG,IIALlD
!M'LI,HSI
"CvFLG
11'0,II8IAKI1
TlO,UIAHTu

MOY
JB
MOV

MOv

J(RC
MOY
JNC

911

00111 C2t7

0114'1 32

A2g11

OUIIJ f5uO
011115 uOt.O
Oull7 uOIiO

IIEflLH: PUSH
I'US ..
J8
JB
liEU
MOV
MOV
,"OY
ClH
MOY
UMP

8':
8J

01l3A 13

Ou311 f5uO
Ou3u ::.0116
Ou3~ u2110

7:1
70
71
7&
19

uEfALHA8LE_KtYaOARu ~E~~tNI LOUE
KStG OETACHlaLt~KerBIJA"D

,If NO CARI(Y THEN NOT DOllE
,CLR 81T 7
,MOY FINAL CUOt fO LSTKY.1

~CS·51

,",UC

MA~RU

ASDE~ijLE ..

D~TACH

U~~

II~J

'1'1

OUIiA 30D4u5
OU4U u2uO
OU4F u2UOUO
OUSe: 02uO
Ou511 C2uO
Ou51> 1,;2110
Ou5~ C2vO
Ou5A t.5~9
oose 1J2~2
OuSt. "'So'l
O~fJu 'l'SlICtF
ClUU 'l5~HF
OU61> lIOuD

F
F

100
101
~O"

10j
F
F

F
F

:iOUR~E

bTUPI

I , toR ..

Jlllb
bE18
JMP

1\8uhT
H51

~t.1"L

10~

t.RHI

liETB

tli .. C..

10::'
lOb
101
1011
10'j
llv
111
11.:

hS I:

CLR
ClH
eLI<
MOV

111
-'"

~
~

lid

!:NII

I~H

AP-223

11('5-51

I~AI.AIi

AS;,E~8I.E"

5YI'001.

IAdL~

(,I:iT!~b

"l!;C " E
A

· ·· ·· ·· ·· ·· ·· ··
······
· ·· ·· · · · · ·
·· ·
··
·
· . ··
· . ·· · · · · ·
no!'. ·
·····
·· · · ·· ·· ·· · ·
· ·····

o~ TlICh

, P t.

ACLoR

~Ot:Ot1

OOUOH
UOl>811

H PUll

IIO~~H

Dt TACH.

a AOUR
C AOuA

OtTACHAdLt._~EYBlil"O

lIEli

ACIIA
AOuR
AOUR
AOuR
AOIlR
ACUR
Nl"B
Nll'e
ACIIR
AOUR
ACUR
lOUR
NLMB

8YF1~

EHR
EHRuR

Flt-:!.

I1,PuT

1<1I01NT.
L:>TI\EY.
MtSUbEU.

"~SbAIiEI.
N~TbIT.

P~~

RI,;VfLG.
RliT

I,;

STAHTI/.
SlAHTl.
SyNC.
Tu.
THO
TlO
TMOII.
VAllO

N~"B

I: lOUR
II
II

U
U

Ii
I:

ADUR
ADDR
lCuR
ACuR
lOUR
ACDR

A I I

A I. Ii t:

1 II U T t. b

~XI

~eb.uEI1CHl8LE_KtYaOlRU

HELauNH
~EbaUEl1~HA8LE_Kt.YOOARO

t.XI
0045H
H
VOIlOH." A
VOUOH
VOt8H
~OclDH

A
A
H

OOUOn

1I054H
IIOOOH
OOF4H
OOUH

001l0H.4
OOliCH
IIOUH
0089H
1I0lAH

aEij.UE1A~HABLE_KtYbOARU

tXr
tXT
~Eij.UETACHABLE_KtYbOARIi

A
A

~Eij-UETACHlBLE_KEYbOARD

tiEbauETACHABLE_KfYtlOARD

tXT

A
10
10
Ii

SEb_UETIoCHIo8LE_KfYtlOIoRU

RflHS1EH !lANK(S) UStO; II
A:lSt.l!bL Y COMPLETE, NO EHROR$ f'OUNU

10-141

·APPENDIX B
REFERENCES
1. John Murray and George Alexy, CRT Terminal Design
Using The Intel 8275 and 8279, Intel Application Note
AP·32, Nov., 1977.
2. John Katausky, A Low Cost CRT Terminal Using The
8275, Intel Application Note AP-62, Nov., 1979.

10-142

MCS®~51

Article Reprint

,~'

',1'

AR-224

Extensive I/O subsystems and a tailored instruction set allow a 16-bit
inicrocontroller to set its sights on a widening range of industrial and
computer (and telecomm and consumer) applications.
.

Controller chip takes on many
industrial, computer uses
With industrial and computer control applications
increasing all the time-and telecommunications
and consumer applications emerging-designers increasingly need microcontrollers whose performance
extends beyond that of the conventional 8-bit
architectures. Normally, control system designers
must depend on expensive and complex multiple-chip
microprocessors to achieve high performance. But
now, a 16-bit single-chip controller offers a much
better solution. Not only does the 8096 offer perhaps
the most extensive input/output "services" of any
microcontroller, it also provides an instruction set
and addressing modes tuned for both fast control
operations and high-speed arithmetic.
In industrial applications, the 8096 can be used for
process control, 1'obotics, numerical and motor control, and instrumentation. Figure 1 shows the chip
in a typical closed-loop servo system of the type used
in industrial applications. In computer applications
performance is the key feature, and here the 8096
provides greater throughput in systems in which
simple data structures-a single I/O bit-and relatively small memories are required. Typical applications are computer peripherals such as printers,
plotters, Winch esters, and other hard-disk systems.
In the consumer end, moreover, the 8096 is ideally
suited for automotive engine and other controls (see
"Stopping a Car") and sophisticated video games.
Both applications need the speed, calculating power,
and addressability of a 16-bit microcomputer. For
telecommunications, the controller is intended for
high-speed modems, P ABXs, and central office
switching systems.
In addition to the full 16-bit CPU, the 8096's basic

architecture includes an 8-kbyte ROM and a 232-byte
RAM, which serves as a register file. To meet the
wide needs of controller environments, the chip
contains an eight-channel, lO-bit analog-to-digital
converter, a full-duplex UART (universal asynchronous receiver-transmitter), two 16-bit timers, and a
programmable pulse-width-modulated output.
Since a microcontroller must be able to interface
with various types of transducers and sensors, the
8096 fe~tures built-in, extensive I/O facilities. These
include an eight-level priority interrupt structure,
full-duplex serial I/O, parallel I/O, a watchdog
timer, analog inputs for the a-d converter; a pulsewidth modulated output and a high-resolution pulse
output. Each of these facilities is integrated not only
physically but logically into the chip's structure by
being tightly coupled to the CPU.
The inherently high performance of a CPU suffers
if the controller spends too much time administering
complex real-time I/O operations. The 8096's onboard I/O facilities solve this problem by permitting
the CPU to devote more time to executing
mathematics and control algorithms and less on I/O.

Table 1. Memory allocations ofthe 8096

Steve Wiseman, Product Marketing Manager
Steve Burton, Senior Engineer
John Katausky, Technical Marketing Manager
Intel Corp.
5000 W Williams Field Rd , Chandler, Anz. 85224

Reprinted from ELECTRONIC DESIGi. - August 5, 1982

0001Hl017

On-chip I/O

0018-0019

Data register/stack pointer

001A-OOFF

Data registers (230 bytes)

01OD-1FFD

Off-chip expansion RAM/ROM/I/O

1FFE-1FFF

On-chlp I/O

20Q0-200F

Internal ROM interrupt vectors

201D-207F

Reserved

2OSD-3FFF

Internal ROM user program space

40Q0-FFFF

Off-chlp expansion RAMIROM!lIO

Copynght 1982 Hayden Publishing Co., Inc.

11-1

16-bit microcontroller .
. The instruction set h~~dle!;· signed and uhsigned
16-bit multiplications and divisions. Both S-bit bytes
arid 16-bit double words are supported. and even 32bit double words are supported for a subset of the
main instruction set. A full 64 kbytes of memory
address space is usabl~.

'structions-as the first 256 bytes of the 64-kbyte
RAM address space, This permits. for example. the
use of a portion of the register space as the subro'utine stack on smaller systems'that do not have
external expansion memory (Table 1).
The first 24 bytes of this register space are
reserved for on-chip 110 addresses. 110 locations are
memory-mapped and can be referenced directly as
registers. The word register located at address ISH
serves as the stack pointer. Such a large register
space allows a programmer to keep his most frequently referenced scalar variables in registers.

A flexible register structure

The S096 instruction set directly supports 256
bytes of registers. which can be referenced as 12Sword registers or as 64 double-word n,gisters. These
registers also appear-for memory reference in-

Immediate

0.2 (word)

NA.

Immediate

o (byte)

N.A.

B,#A

Indirect

0.4

1.4

B,(A)

(B) <= (B) + ((A))

Autoincrement

0.6

B,(A)+

(B) <= (B) + ((A)); (A) <= (A)
+

Short Indexed

0.4

1.4

B,C[AI

(B) <= (B) + ((A) + C); where
-128'~l_ s~13.3 Hz per r¢les per ~
timer, at time x and ly the value. operatiOn is eorreet, tile software
. isa typicaLvalue, Four piCkup
at time y,then Eq. 1 and 2 are.
will issue commands to reset the
outputs Ill'e easilyllaitdl:e4 by the
written. as
wat\:hdog. But if a system failure
8096's)l~-speed inputunlt. At
V.y = ~481(I,. - I,.) (4)
prevents a diagnOstic from runeach' _osition of any (1ftbe
ning wjthin a prescribed period,
V yz = 4699%.48I{I. - Iy) (5.)
pickupS', the current vatwi ofijmet
In practice, theeonstaritsIn Eq.
the watchdog timer will reset the
ois saved in the input ""0, The 4 and 5 should he multiplied by a entire systenl. The software ~.
programmable 'edge tt~ in
scaling factor to allow calculations
not reset properly on an erroneous
the high-speed input unit provides
operation, such as a counter overto he performed in integer
a convenient 'device for handling
Ill'ithmetic. A faetoroflOO, for
Bow, excevt by writing to the
the' wide dynamic ra~,', (1f the ' example, gi~llSsjJeed measured in "z'watchdog, titDer twice within its
,period measurement. At· slow
unitlf of lJ19D,ofa~i1epernour.
counting,~e.
'

.' ;' . ,,;1'I:I,e8096 ~bev~!'Y useful in

11-3

", '

16-bit microcontroller
operands in and out of memory locations. In addition,
the chip's' powerful three-operand instructionsAdd,. Subtract, Multiply and Logical And-often
eliminate them. Since programmer productivity
(measured in lines of code written per day) is
reasonably constant, writing fewer Move instructions can lead to reduced development expense.
Register Load and Store instructions, with a full set
of addressing modes, handle moves that cannot be
eliminated.
Keeping addressing simple

Because a study of the ways in which addressing
is used on the 8086 microprocessor indicates that
programmers use complex addressing modes less
than 0.7% of the time, the 8096's instruction set
bypasses those in favor of the more commonly used
addressing modes. But should complex addressing
be needed, programmers can build such modes
through macros. Addressing modes in the 8096
include direct, register-indirect, immediate, autoincrement, and both short (8-bit) and long (16-bit)
indexed-address. Table 2 lists the address modes and
the operations that occur when each is activated.
Indexed-address modes, by adding an 8- or 16-bit
disp!acement to the contents of any 16-bit register

to form the' effective address of an operand, allow
fast access to arrays stored anywhere in memory.
Indexed modes are also useful for, referencing elements of based structures, as in the PL/M language.
However, preliminary calculations are needed to
reference a based array.
The stack pointer is fully addressable, as are all
other 16-bit registers. As a result, it can be the base
register for moded references. Stack-relative addressing, which is easy to program, is often used for
recursive-subroutine parameter passing and dynamically allocated variables. While this technique does
not make the best use of a large register space, it
adds flexibility to the system. The stack need not
be confined to internal RAM, but can fill any
available RAM space in the system. The stack can
flow across the boundary into register space at will,
allowing recursion to very great subroutine depths.
Of the instruction set's 71 instructions, 25 take on
both word and byte form, which increases the total
to 96 instructions. The set includes 16 varieties of
conditional jump, allowing·for both signed and unsigned comparisons. All of the 2048 bits in register
space can be tested individually by a Jump on
Bit/Not Bit instruction. A Decrement and Jump on
Not Zero instruction provides for loop control.

2. Centered around the CPU and memory, the 8096's extensive 1/0 subsystem. Include an ,
analog-to-dlgltal converter, a universal asynchronous recelver-transmltter(UART). high-speed
input and output circuitry. and a pulse-width modulation olltput circuit. $Ilch IntelUgentl/O
allows the CPU to concentrate not on real-time housekeeping but on high-speed arithmetic
and control operations.

11-4

Most of the instructions execute in about 0.8 !lS;
the .Iongest, to normalize a zero, takes 8 !lS. All datarefere'nce instructions except Pop, Push, and
Normalize are available in byte form, and all such
instructions except.Jump on Bit and Normalize are
available in word form. Table 3 lists some typical
8096 instructions' and their run times.
A survey of code frequency usage shows that
although most. multiplications and divisions are
unsigned, a signed form is still necessary. When
unsigned multiplication and division instructions are
preceded by a 0.8-!ls SIGND prefix, they are converted into full two's-complement signed multiplication and division. ;Either type of operation executes
in less than 6 !lS. Word multiplications result in a
double-word product, and byte multiplications produce a word product. With an instruction called
Word Divide, a double-word dividend is divided by
a word divisor to produce a word quotient and
remainders.
Because jumps and calls are PC-relative, code is
easy to relocate. Both Jump and Call instructions
are available in a short 2-byte form with an H-bit
displacement. Jump on Bit is a 3-byte instruction
with an 8-bit displacement. An indirect jump for the
"do-case" is also provided.
In addition to the usual sign-extending (EXT)
instructions for byte-to-word and word-to-doubleword conversions, the set includes instructions
LDBSA and LDBZE, which move a byte into a word
with sign or zero extension. Most one- and twooperand forms execute in 1 !lS. Conditional jumps
run in less than 1.8 !lS, and in about 0.8 !lS when
the jump is not taken.
Shifts, whether by a specific number of bit positions or by a computed number, are provided for all
three operand lengths (byte, word, and double word).
In a floating-point software package, the mantissas
must be aligned before they are added or subtracted,
and the results normalized afterwards. Both functions require a software shift loop.
The Normalize instruction and the computer form
of the Shift Double Word instruction allow fast
software implementations of floating-point arithmetic with up to a 32-bit mantissa. Multibit shift
instructions are very useful for scaling operations
.in scaled-integer arithmetic. Scaled-integer operations are usually faster than floating-point
arithmetic in control applications.
In addition to an overflow flag, which is set by
each arithmetic instruction, there is an overflowtrap flag. It can be checked at the end of a sequence
of instructions to determine whether an overflow has
occurred anywhere in the sequence.
The instruction set is complemented by a variety
of 110 subsystems for handling virtually any com-

0.8

INC,DEC,CLR,
NOT,NEG,SEX

One-operand
Instructions

0.8

XOR,ADDC,SUB,
AND,ADD,SUBC

Two-operand
arithmetics

OR,CMP

Two-op
arithmetics

0.8

LD,LDBSE,
ST

0.8 (not
taken)

Load and store
registers

JC,JNC,ETC.

Conditional jumps

1.0

AND,SUB,ADD

Three-op
arithmetics

1.0 (not
taken)

JBS,JBC

Jump on bill
jump on not bit

1.6 (taken)

JC,JNC,ETC.

Conditional jumps

1.6

SJMP,IJMP,
LJMP

Unconditional
jumps

1.6 (stack
register)

PUSHF

Push PSW

1.6 (stack
register)

PUSH

Stack push

1.8 (taken)

JBS,JBC,DJNZ

Jump on bill
and jump

1.6 +
0.2/shift

SHL,SHR,SHRA

Shift instruc-

1.8

POPF

Pop PSW

NORML

Normalize

2.2

tions

O.2!shlft

2.4

POP

Stack pop

2.4 (stack
register)

LCALL,SCALL,
RET

Subroutines

2.4 (stack
external)

PUSHF

Push PSW

2.4 (stack
external)

PUSH

Stack push

2.6 (stack
external)

POPF

Pop PSW

2.8 (stack
external)

POP

Stack pop

SCALL,CALL

Subroutines

3.0 (stack
external)
3.2 (stack
external)

RET

Subroutine

3.4

MULB

Byte multiplication

3.6

DIVB

Byte division

3.6

MULa

Byte multiplication

5.2

MUL

Word multiplication

5.2

2'
3'

DIV

Word diviSion

MUL

Word multiplication

5.4

these operands may have

11-5

address modes

16-blt microcontroller
puter peripheral or industrial application (Fig. 2).
They include an a-d converter, a DART, timercounters, and a programmable pulse-width -modulated output.
I/O resources inclUde a-d

The controller contains a complete eight-channel,
lO-bit a-d converter. Dsin'g successive approximation
to achieve high speed-33.6 (.LS at a I5-MHz clock rate
-it handles analog input voltages in the range of
o to 5 V. An external reference is required and must
be connected between the reference voltage and
analog ground terminals. The converter generates a
vectored interrupt when it completes a conversion
cycle, allowing the CPD to have rapid access to the
a-d input handler when operating in a multitask
environment.
Conversion is initiated by writing to an 8-bit
a-d command register. The results of a conversion
are read from two 8-bit output data registers.' One
8-bit register contains the eight most significant bits,
and the other holds the two least significant bits,
a 3-bit channel indicator, two unused bits, and a
status bit. The status bit, which indic'Ites whether
the a-d conversion is still in progress, is typically
used in a non interrupt-driven environment.
Just four bits of the a-d command register are
used. Three of the bits specify the channel to be
converted, and the fourth specifies the method of
initiating an a-d conversion cycle. For example, if
the fourth bit is a 1, the cycle begins immediately
after writing to the command register. If it is a 0,

FIFO register
(7 bits X 20 words)

3. One half of the 8096's high-speed 1/0 subsystem is an Input
unit, which contains a user-programmable change detector
that defines Input transitions for the high-speed inputs. Each
ofthe four inputs (HSI. - HSI,) can be programmed to respond
to a different Inputtransition.

the high-speed output logic subsystem initiates the
conversion: The reason for the option is that many
data acquisition algorithms require that conversions
occur at specific intervals. This requirement is often
difficult to manage through software because of
interrupt latency and other conditions. Thus, the
high-speed output subsystem provides the proper
timing for periodic a-d conversions.
The 8096's DART is virtually a carbon copy of the
one on the 8051 microcontroller. One' of its 8-bit
registers receives data, another transmits data, and
another indicates the DART status plus bits to
configure it for a specific operating mode. By setting
the appropriate bits in the third, or control-status,
register, a user can select one of four modes:
• Mode 0 (shift register) is a simple, synchronous
mode in which the 8096 provides a clock to
synchronize incoming or outgoing data. Mode 0 can
also be used to expand the I/O.
• Mode 1 is an 8-bit DART mode in which the
eighth bit is used for parity when it is enabled.
• Mode 2 is a 9-bit DART mode in which the ninth
pit is used for parity when it is enabled.
• Mode 3 is a 9-bit data/address mode in which
the DART transmits and receives nine bits of data.
This is useful for implementing a simple multiprocessor intercommunications link in which the ninth
bit distinguishes address from data.
The remaining six bits of the control-status register are used for six operations: enabling the receiver
section of the DART, enabling parity for both
transmission and reception (even parity); storing the
ninth bit when in the 9-bit transmitting mode;
storing the ninth bit when in the 9-bit receiving
mode, indicating that the receiver is ready, and
indicating that the transmitter is ready. Also on
board are a dedicated I5-bit baud-rate generator and
a baud-rate ~lock that can be driven by either the
·8096's crystal oscillator or an input at pin 1'2CLK.
This gives maximum flexibility in setting baud rates.
The pulse-width modulated output can produce a
pulse train of variable duty cycle, which can be
integrated and clamped to provide an accurate
digital-to-analog output function. The PWM circuit
operates as follows: The 8096 crystal frequency is
divided by three and clocks an 8-bit free-running
counter. The counter output connects to one side of
an 8-bit comparator; the other side of the comparator
is tied to a user-addressable register. When the freerunning counter value is the same'as the one stored
in the addressable register, an R-S flip-flop is set.
The flip-flop is also reset when the counter rolls over
from a count of 255 to O. This produces a simple yet
accurate variable duty-cycle oscillator, which can be
programmed for a variable duty cycle from 0 to 255
in increments of X/256.

11-6

16-bit microcontroller
The watchdog timer offers a simple way to recover
from a software or hardware error. Essentially a 16Wt free-running counter that is clocked by the CPU
clock generator circuitry, the timer is reset by
writing a 01E H followed by a OEIH to byte location
OOOAH. If a resetting does not occur at least once
every 13.107 ms, the timer will overflow, causing the
8096 to be reset-resetting reinitializes the 8096. This
feature makes it virtually impossible for the 8096
to become lost in a program for too long. For
development purposes, the reset terminal can be
connected to Vee to disable the watchdog timer.
More I/O-and faster

Correlating events in real time is one of the most
important considerations in computer-based control
system design. Another common requirement is
generating pulses and pulse trains todrive actuators.
Most single-chip microcontrollers support such
operations by having one or more timer/event counters under software control. The 8096, on the other
hand, offers a complete integrated subsystem to
perform these functions. Called the high-speed I/O
unit, it is intended to be an integrated subsystem,
but it can be viewed as separate units for input and
output.
Figure 3 shows the block diagram of the high-speed
input unit. Its major components are a 16-bit timer,
a programmable change detector and a first-in, firstout (FIFO) memory. Also included are several registers used by the software to control the high-speed
input unit.
The read-only timer is cleared by the system reset
and incremented once every eight CPU cycles (every
1.6 J.LS with a 15-MHz crystal). When the timer
overflows-rolls over from FFFFH to OOO!l!-a status
bit is set and an interrupt is generated. The change
detector monitors four pins on the 8096 and looks
for predefined changes. Change definitions are controlled by the high-speed input unit's mode register,
which is set by the software. This register contains
a 2-bit field for each of the four high-speed inputs.
Using the fields, a programmer can select the type
of change for each input. Fields are encoded in one
of four ways:
• 00 defines positive transitions divided by 8.
• 01 defines positive transitions.
• 10 defines negative transitions.
• 11 defines positive and negative transitions.
Each high-speed input can be disabled through a
second control register. When this is done, inputs
of the high-speed input unit become available as
digital input pins or, if required, two of the pins can
be connected to the high-speed output unit.
As the block diagram in Fig. 4 shows, the 'highspeed output unit uses the same timer as the input

unit and also has a 16-bit event counter. The readonly event counter is similar to the timer in that it
can be read at any time, generates an overflowinterrupt or status indication, and cannot be written
into. It differs from the timer, in that its reset and
clock sources, instead of being fixed by hardware,
can be selected under software control.
Two of the 8096's pins are dedicated to the event
counter. A positive-going pulse on ECRST (Event
Counter Reset) clears the counter, and either edge
of a pulse applied to ECCLK (Event Counter Clock)
increments the counter. A programmer has the
option of using HSI o instead of ECRST or HSI,
instead of ECCLK. These options are available by
setting the appropriate bits in the 110 control register. The event counter can also be cleared under
software control either directly, by setting a bit in
the 110 control register, or indirectly, using the high-

4. The other half of the high-speed I/O subsystem is the
output unit. Using a content-addressable memory to store socalled time-field data, the unit's logic matches this information
with timer or event-counter operations.
::tll== .. "' ....

== . . "' ... -= ...

.0; ...*"1

"'........

6 .• ,4.3'2"',0

; =-,",,, .. .::::.~,,,,=-=.,,,,_,,,-=;:.~_a*==<=;:;:;:

Channel 00Qe

~"--"().6:~l>IIiwt"'"".OII"tlU9h6
:.--:-.:::::-c::t~~,,",_'=%!',tnr<>Ugh$
;

...----- :-~ ... :-

"'---15:'S~Hconvet$iQn

~---- --- -~-"--~==.lIlo
~
m
0
0

•

III

0
-<
0

....
m
s:

SINGLE COMPONENT MCS®-48 SYSTEM

registers in place of locations 0-7 and are then directly
addressable. This second bank of working registers may
be used as an extension of the first bank or reserved for
use during interrupt service subroutines allowing the registers of Bank 0 used in the main program to be instantly
"saved" by a Bank Switch. Note that if this second bank
is not used, locations 24-31 are still addressable as general
purpose RAM. Since the two RAM pointer Registers RO
and RI are a part of the working register array, bank
switching effectively creates two more pointer registers
(ROland Rl!) which can be used with RO and RI to easily
access up to four separate working areas in RAM at one
time. RAM locations (8-23) also serve a dual role in that
they contain the program counter stack as explained in
Section 12.1.6. These locations are addressed by the Stack
Pointer during subroutine calls as well as by RAM Pointer
Registers RO and RI. If the level of subroutine nesting is
less than 8, all stack registers are not required and can be
used as general purpose RAM locations. Each level of
subroutine nesting not used provides the user with two
additional RAM locations.

is stored in location 7. Program memory can be used to
store constants as well as program instructions. Instructions such as MOVP and MOVP3 allow easy access to
data "lookup" tables.

-0

2048~
t
2047~TSELMBO
SELMB1

1024
1023

:t
(.)
z
0

-------

l:
~

...co

Go
:t
(.)
:t
z (.)

8
7
6
5
4

3
2
1

LOCATION 7TIMER INTERRUPT
VECTORS
PROGRAM HERE

63
(127)
«255))

LOCATION 3EXTERNAL

USER RAM
32 x 8
(96 x 8)
«224 x 8))

-r- INTERRUPT

VECTORS
PROGRAM HERE

32
31

7161514131211101+ RESET VECTORS
PROGRAM HERE
ADDRESS

24
23

Figure 12·2. Program Memory Map

12.1.3 Data Memory
Resident data memory is organized as 64, 128, or 256 by
8-bits wide in the 8048AH, 8049AH and 8050AH. All
locations are indirectly addressable through either of two
RAM Pointer Registers which reside at address 0 and 1
of the register array. In addition, as shown in Figure 12-3,
the first 8 locations (0-7) of the array are designated as
working registers and are directly addressable by several
, instructions. Since these registers are more easily addressed, they are usually used to store frequently accessed
intermediate results. The DJNZ instruction makes very
efficient use of the working registers as program loop
counters by allowing the programmer to decrement and
test the register in a single instruction.
By executing a Register Bank Switch instruction (SEL
RB) RAM locations 24-31 are designated as the working

12-3

BANK 1
WORKING
REGISTERS
8x8
-----Rf- - - -

----'Rii'----

.
.

8 LEVEL STACK
OR
USER RAM
16 x 8
8
7

BANKO
WORKING
REGISTERS
8x8

.
.:.=-

-::'=-==RI=':
RO

DIRECTLY
ADDRESSABLE
WHEN BANK 1
IS SELECTED

ADDRESSED
INDIRECTLY
THROUGH
R1 OR RO
(RO' OR R1')

DIRECTLY
ADDRESSABLE
WHEN BANKO
ISSELECTjD

'IN ADDITION RO OR R1 (RO' OR R1')
( ) 8049AH, 8749H,
MAY BE USED TO ADDRESS 256
WORDS OF EXTERNAL RAM.
« )) 8050AH

Figure 12·3. Data Memory Map

SINGLE COMPONENT MCS®-48 SYS1;EM

ORL,ANL

VCC
VCC
Q

INTERNAL
BUS

D
D
FLIP
FLOP

CLK

1/0
PIN
PORT!
AND 2

LOW
IMPEDANCE
PULLDOWN

WRITE
PULSE

-=-

MAX
-500

-400
10H -300 _ _ _~

("A) -200
-!OOf---_
MINL-._ _ __
4V

VOH

VOH(V)

LOW IMPEDANCE PULLUP

HIGH IMPEDANCE PULLUP

2V
VOL

LOW IMPEDANCE PULLDOWN

These graphs are for Informational purposes only and are not guaranteed minimums or maximums.

Figure 12-4. "Quasi-bidirectional" Port Structure

12-4

SINGLE COMPONENT MCS®-48 SYSTEM

12.1.4 Input/Output

statically latched output port or non-latching input port.
Input and output lines on this port cannot be mixed
however.

The 8048AH has 27 lines which can be used for input or
output functions. These lines are grouped as 3 ports of 8
lines each which serve as either inputs, outputs or bidirectional ports and 3 "test" inputs which can alter program sequences when 'tested by conditional jump
instructions.

As a static port, data is written and latched using the OUTL
instruction and inputted using the INS instruction. The
INS and OUTL instructions generate pulses on the corresponding RD and WR output strobe lines; however. in
the static port mode they are generally not used. As a
bidirectional port·the MOVX instructions are used to read
and write the port. A write to the port generates a pulse
on the WR ou~ line and output data is valid at the
trailing edge of WR. A read of the port generates a pulse
on the RD output line and input data must be valid at the
trailing edge of RD. When not being written or read, the
BUS lines are in a high impedance state. See also sections
13.6 and 13.7.

PORTS 1 AND 2
Ports 1 and 2 are each 8 bits wide and have identical
characteristics. Data written to these ports is statically
latched and remains unchanged until rewritten. As input
ports these lines are non-latching, i.e., inputs must be
present until read by an input instruction. Inputs are fully
TTL compatible and outputs will drive one standard TTL
load.
.

12.1.5 Test and INT Inputs
The lines of ports 1 and 2 are called quasi-bidirectional
because of a special output circuit structure which allows
each line to serve as an input, and output, or both even
though outputs are statically latched. Figure 12-4 shows
the circuit configuration in detail. Each line is continuously pulled up to VCC through a resistive device of
relatively high impedance.
'

Three pins serve as inputs and are testable with the~
ditional jump instruction. These are TO, Tl, and INT.
These pins allow inputs to cause program branches without
the necessity to load an.input port into the acoumulator.
The TO, Tl, and INT pins have other possible functions
as well. See the' pin description in Section 12.2.

12.1.6 Program Counter and Stack

This pullup is sufficient to provide the source current for
a TTL high level yet can be pulled low by a standard TTL
gate thus allowing the same pin to be used for both input
and output, To provide fast switching times in a "0" to
" I" transition a relatively low impedance device is
switched in momentarily ('" 115 of a machine cycle) whenever a "I" is written to the line. When a "0" is written
to the line a low impedance device overcomes the light
pullup and provides TTL current sinking capability. Since
the pulldown transistor is a low impedance device a "1"
must first be written to any line which is to be used as an
input. Reset initializes all lines to the high impedance' 'I"
state.

The Program Counter is an independent counter, while the
Program Counter Stack is implemented suing pairs of registers in the Data Memory Array. Only 10, 11, or 12 bits
of the Program Counter are. used to address the 1024,
2048, or 4096 words, of on-board program memory of the
8048AH, 8049AH, or 8050AH, while the most significant
bits can be used for external Program Memory fetches.
See Figure 12.5. The Program Counter is initialized to
zero by activating the Reset line.

1~IArol~I~I~I~I~I~I~~~I~I~1

It is important to note that the ORL and the ANL are read!
write operations. When executed, the p,C "reads" the
port, modifies the data according'to the instruction, then
"writes" the data back to the port. The "writing" (essentially an OUTL instruction) enables the low impedance
pull-up momentarily again even ifthe data was unchanged
from a "I." This specifically ~pplies to configuratkms
that have inputs and outputs mixed together on the same
port. See also .section 13.7.

I
Conventional Program Counter
• Counts OOOH to 7FFH
• Overflows 7FFH to OOOH

Figure 12-5. Program Counter

BUS

An interrupt or CALL to a subroutine causes the contents
of the program counter to be stored in one of the 8 register
pairs of the Program Counter Stack as shown in Figure
12-6. The pair to be used is determined by a 3-bit Stack
Pointer which is part of the Program Status Word (PSW).

Bus is also an 8-bit port which is a true bidirectional port
with associated input and output strobes. If the bidirectional feature is not' needed, Bus can serve as either a
12-5

SINGLE COMPONENT: MCS®-48 SYSTEM

POINTER

the word. The Program Status Word is actually a collection
of flip-flops throughout the machine which can be read or
written as a whole. The ability to write to PSW allows
for easy restoration of machine status after a power down
sequence.

R23.

111
22

110

SAVED IN STACK

STACK POINTER
I

101

....L

011

·,
·
~
·

.-l.

psw

000

PC4-7

Figure 12-7. Program Status Word (PSW)

12
11

....L

001

CARRY
AUXILIARY CARRY
FLAG 0
REGISTER BANK SELECT

....L

010

CY
AC
FO
BS

....L

LSB

MSB

100

The upper four bits of PSW are stored in the Program
Counter Stack with every call to subroutine or interrupt
vector and are optionally restored upon return with the
RETR instruction. The RET return instruction does not
update PSW.

PC8-11

>.PCO-3

MSB

LSB

The PSW bit definitions are as follows:
Bits 0-2: Stack Pointer bits (So' S l' S2)

Figure 12-6. Program Counter Stack

Bit 3:
Data RAM locations 8-23 are available as stack registers
and are used to store the Program Counter and 4 bits of
PSW as shown in Figure 12-6: The Stack Pointer when
initialized to 000 pointS to RAM locations 8 and 9. The
first subroutine jump or interrupt results in the program
counter contents being transferred to locations 8 and 9 of
the RAM array. The stack pointer is then incremented by
one to point to locations 10 and 11 in anticipation of
another CALL. Nesting of subroutines wihtin subroutines
can continue up to 8 times without overflowing the stack,
If overflow does occur the deepest address stored (locations 8 and 9) lNiil be 'overwritten and lost sinoe the stack
pointer overflows from III to.OOO. It also underflows from
000 to 111.
The end of a subroutine, which is signalled by a return
instruction (RET or RETR), causes the Stack Pointer to
be decremented and (the contents of the resulting register
pair to be transferred to the Program Counter.

12.1.7 Program Status Word
An 8-bit status word which can be loaded to arid from the
accumulator exists called the Program 'Status:W ord
(PSW); Figure 12-7 shows the information available in

12-6

Bit 4:

Not used (' '1" level when read)
Working Register Bank Switch Bit(BS)
. 0 = Bank 0
I = Bank I

Bit 5:

Flag 0 bit (FO) user controlled flag which can
be complemented or cleared, and tested with
the conditional jump instruction JFO.

Bit 6:

Auxiliary Carry (AC) carry bit generated by
an ADD instruction and used by the decimal'
adjust instru~tion DA A.

Bit 7:

CatTy (C'Y) carry flag which indicates that the
previous operation has' resulted in overflow of
the accumula~or.

12.1~8

Condltonal Branch Logic

The conditional branch logic within the processsor enables
several conditions internal and external to the processor
to be tested by the users program. By using the conditronal
jump instruction the conditions that are listed in Table
12-1 can effect a change in the sequence of the program
execution.

SINGLE COMPONENT MCS®-48 SYSTEM

Table 12·1

Device Testable
Accumulator
Accumulator Bit
Carry Flag
User Flags (FO, FI)
Timer Overflow Flag
Test Inputs (TO,..!!)
Interrupt Input (INT)

abled by the users program. An interrupt request must be
removed before the RETR instruction is executed upon
return from the service routine otherwise the processor
will re-enter the service routine immediately. Many peripheral devices prevent this situation by resetting their
interrupt request line whenever the processor accesses
(Reads or Writes) the peripherals data buffer register. If
the interrupting device does not require access by the
processor, one output line of the 8048AH may be designated as an "interrupt acknowledge" which is activated
by the service subroutine to reset the interrupt request.
The INT pin may also be tested using the conditional jump
instruction IN!. This instruction may be used to detect the
presence of a pending interrupt before interrupts are enabled. If interrupt is left disabled, INT may be used as
another test input like TO and T!.

Jump Conditions
(Jum On)
All zeros

not all
zeros
1
I

I
I

0
0

12.1.9 Interrupt
An interrupt sequence is initiated by applying a low "0"
level input to the INT pin. Interrupt is level triggered and
active low to allow "WIRE ORing" of several interrupt
sources at the input pin. Figure 12-8 shows the interrupt
logic of the 8048AH. The Interrupt line is s.ampled every
instruction cycle and when detected causes a "call to
subroutine" at location 3 in program memory as soon as
all cycles of the current instruction are complete. On 2cycle instructions the interrupt line is sampled on the 2nd
cycle only. INT must be held low for at least 3 machine
cycles to ensure proper interrupt operations. As in any
CALL to subroutine, the Program Counter and Program
Status word are saved in the stack. For a description of
this operation see the previous section, Program Counter
and Stack. Program Memory location 3 usually contains
an unconditional jump to an interrupt service subroutine
elsewhere in program memory. The end of an interrupt
service subroutine is signalled by the execution of a Return
andRestore Status instruction RETR. The interrupt system
is single level in that once an interrupt is' detected all
further interrupt requests are ignored until execution of an
RETR reenables the interrupt input logic. This occurs ,at
the beginning of the second cycle ofthe RETR instruction.
This sequence holds true also for an internal interrupt
generated by timer overflow. If an internal timer/counter
generated interrupt and an external interrupt are detected
at the same time, the external source will be recognized.
See the following Timer/Counter section for a description
of timer interrupt. If needed, a second external interrupt
can be created by enabling the timer/counter interrupt,
loading FFH in the Counter (ones less than terminal
count), and enabling the event counter mode. A "1" to
"0" transition on the Tl input will then cause an interrupt
vector to location 7.

12.1.10 Time/Counter
The 8048AH contains a counter to aid the user in counting
external events and generating accurate time delays without placing a burden on the processor for these functions.
In b,oth modes the counter operation is the same, the only
difference being the source of the input to the counter.
The timer/event counter is shown in Figure 12-9.

COUNTER
The 8-bit binary counter is presettable and readable with
two MOY instructions which transfer the contents of the
accumulator to the counter and vice versa. 'The counter
content may be affected by Reset and should be initialized '
by software. The counter is stopped by a Reset or STOP
TCNT instruction and remains stopped until started as a
timer by a START T instruction or as an event counter
by a START CNT instruction. Once started the counter
will increment to this maximum count (FF) and overflow
to zero continuing its count until stopped by a STOP TCNT
instruction or Reset.
The increment from maximum count to zero (overflow)
results in the setting of an overflow flag flip-flop and in
the generation of an interrupt request. The state of the
overflow flag is testable with the conditional jump instruction JTF. The flag is reset by executing a JTF or by Reset.
The interrupt request is stored in a latch and then ORed
with the external interrupt input INT. The timer interrupt
may be enabled or disabled independently of external interrupt by the EN TCNT! and DIS TCNT! instructions.
If enabled, the counter overflow will cause a subroutine
call to location 7 where the timer or counter service routine
may be stored,

INTERRUPT TIMING
The interrupt input may be enabled or disabled under
Program Control using the EN I and DIS I instructions.
Interrupts are disabled by Reset and remain so until en-

If timer and external interrupts occur simultaneously, the
external source will be recognized and the Call will be to

12·7

SINGLE. COMPONENT MCS®·48 SYSTEM

CONDITIONAL
JUMP LOGIC

JTF
EXECUTED ~-- .....~~-+_~ R
RESET--_.J'

TIMER
FLAG

INTERRUPT
CALL
EXECUTED

EXTERNAL
INTERRUPT
RECOGNIZED

TIMER
INTERRUPT
RECOGNIZED

CLR
D

------+---1 S

TIMER
OVERFLOW,

TIMER
OVERFLOW
FF

TIMER INT
RECOGNIZED
EXECUTED

CLK

>-----lR

RESET

DIS TCNTI _ _ _.....

TIMER
INT
ENABLE

')----1 R

EXECUTED

S
Q
INTERRUPT
IN
PROGRESS
FF
R

RESET

INTcr--------l D
PIN
RESET

INT
FF

RETR
EXECUTED

Q
CLK
ALE--I'-'"
LAST CYCLE
I------...J
OFINST.
ENI
S
EXECUTED
OISI
EXECUTED __
RESET

INT
ENABLE

---JL/--1' -R-_ _..J

1. WHEN INTERRUPT IN PROGRESS FLIP-FLOP IS SET
ALL FURTHER INTERRUPTS ARE LOCKED OUT
INDEPENDENT OF STATE OF EITHER INTERRUPT
ENABLE FLIP-FLOP.
2. WHILE TIMER INTERRUPTS ARE DISABLED TIMER
OVERFLOW fli WILL NOT STORE ANY OVERFLOW
THAT OCCURS. TIMER FLAG WILL BE SET, HOWEVE,R.

Figure 12·8. Interrupt Logic

. 12-8

SINGLE COMPONENT MCS®-48 SYSTEM

PRESCALER

XTAL-15

732
LOAD OR READ

CLEARED ON START TIMER

EDGE
DETECTOR

START
COUNTER

JUMP ON
TIMER FLAG

8BITTIMERI
EVENT COUNTER

OVERFLOW
FLAG

STOPT

INT
ENABLE--------~L_~

Figure 12-9. Timer/Event Counter
location 3. Since the timer interrupt is latched it will remain pending until the external device is serviced and
immediately be recognized upon return from the service
routine. The pending timer interrupt is reset by the Call
to location 7 or may be removed by executing a DIS
TCNT! instruction.

olution less than 1 count an external clock can be applied
to the T I input and the counter operated in the event
counter mode. ALE divided by 3 or more can serve as
this external clock. Very small delays or "fine tuning"
of larger delays can be easily accomplished by software
delay loops.

AS AN EVENT COUNTER

Often a serial link is desirable in an MCS-48 family member. Table 12-2 lists the timer counts and cycles needed
for a specific baud rate given a crystal frequency.

Execution of a START CNT instruction connects the T!
input pin to the counter input and enables the counter.
The T! input is sampled at the beginning of state 3 or in
later MCS-48 devices in state time 4. Subsequent high to
low transitions on TI will cause the counter to increment.
T! must be held low for at least 1 machine cycle to insure
it won't be missed. The maximum rate at which the
counter may be incremented is once per three instruction
cycles (every 5.7 f.A-sec when using an 8 MHz crystal)there is no minimum frequency. T! input must remain
high for at least 115 machine cycle after each transition.

AS A TIMER
Eexcution of a START T instruction connects an internal
clock to the counter input and enables the counter. The
internal clock is derived bypassing the basic machine cycle
clock through a + 32 prescaler. The prescaler is reset
during the START T instruction. The resulting clock increments the counter every 32 machine cycles. Various
delays from I to 256 counts can be obtained by presetting
the counter and detecting overflow. Times longer than 256
counts may be achieved by accumulating multiple overflows in a register under software control. For time res-

12-9

12.1.11 Clock and Timing Circuits
Timing generation for the 8048AH is completely selfcontained with the exeception of a frequency reference which
can be XTAL, ceramic resonator, or external clock source.
The Clock and Timing circuitry can be divided into the
following functional blocks.

OSCILLATOR
The on-board oscillator is a high gain parallel resonant
circuit with a frequency range of I to II MHz. The XI
external pin is the input to the amplifier stage while X2
is the output. A crystal or ceramic resonator connected
between XI and X2 provides the feedback and phase shift
required for oscillation. If an accurate frequency reference
is not required, ceramic resonator may be used in place
of the crystal.
For accurate clocking, a crystal should be used. An externally generated clock may also be applied to XI-X2
as the frequency source. See the data sheet for more
information.

SINGLE COMPONENT MCS®~48 SYSTEM

Table 12-2. Baud Rate Generation

Baud
Rate

Frequency
(MHz)

Tcy

TO Prr(1/5 Tcy)

Timer Prescaler '

4
6
8
11

3.75MS
2.50MS
1.88MS
1.36MS

750ns
500ns
375ns
275ns

120MS
80MS
60.2MS
43.5MS

4 MHz
Timer Counts +
Instr. Cycles

6 MHz
Timer Counts +
Instr. Cycles

8 MHz
Timer Counts +
Instr. Cycles

11 MHz
Timer Counts +
lnstr. Cycles

151 + 3 Cycles
.01% Error

208 + 28 Cycles
.01% Error

(32T~

110

+ 24 Cycles
.01% Error

113 + 20 Cycles
.01% Error

300

+ 24 Cycles
.1% Error

+ 21 Cycles
.03% Error

+ 13 Cycles
.01% Error

1200

30 Cycles
.1% Error

+ 13 Cycles
.1% Error

+ 27 Cycles
.06% Error

19 + 4 Cycles
.12% Error

1800

30 Cycles
.1% Error

+ 7 Cycles
.17% Error

+ 24 Cycles
.12% Error

2400

15 Cycles
.1% Error

+ 6 Cycles
.4% Error

+ 24 Cycles
.29% Error

+ 18 Cycles
.12% Error

4800

+ 23 Cycles
1.0% Error

+ 14 Cycles
.74% Error

+ 25 Cycles
.12% Error

20 Cycles
.1% Error

19 Cycles
.4% Error

STATE COUNTER

The output of the oscillator is divided by 3 in the State
Counter to create a clock which defines the state times of
the machine (CLK). CLK can be made available on the
external pin TO by executing an ENTO CLK instruction.
The output of CLK on TO is disabled by Reset of the
processor.

+ 18 Cycles
.04% Error

power supply is within tolerance. Only 5 machine cycles
(6.8 MS @ 11 MHz) are required if power is already on
and thl( oscillator has stabilized. ALE and PSEN (if EA
= 1) are active while in Reset.
Reset performs the following functions:
1) Sets program counter to zero.

CYCLE COUNTER

2) Sets stack pointer to zero.

CLK is then divided by 5 in ti1e Cycle Counter to provide
a clock which defines a machine cycle consisting of 5
machine states as shown in Figure 12-10. Figure 12-11
shows the different internal operations as divided into the
machine states. This clock is called Address Latch Enable
(ALE) because of its function in MCS-48 systems with
external memory. It is provided continuously on the ALE'
output pin.

3) Selects register bank O.

4) Selects memory bank O.
5) Sets BUS to high impedance state (except when
EA = 5V).

6) Sets Ports 1 and 2 to input mode.

12.1.12 Reset

7) Disables interrupts (timer and external).

The reset input provides a means for initialization for the
processor. This Schmitt-trigger input has an internal pullup device which in combination with an external 1 M fd
capacitor provides an internal reset pulse of sufficient
length to guarantee all circuitry is reset, as shown in Figure
12-12. If the reset pulse is generated externally the RESET
pin must be held low for at least 10 milliseconds a~ter the

8) Stops timer.

12-10

9) Clears timer flag.
10) Clears FO and Fl.
11) Disables clock output from TO.

SINGLE COMPONENT MCS®-48 SYSTEM

JUMP ON
TEST ~ 1 OR 0

.273

~.ec

(3.67 MHz)

-5
CYCLE
COUNTER

(733 KHz)

' -_ _ _ _..1 1.36

~.ec

DIAGRAM OF S04SAH CLOCK UTILITIES

.
S5

INPUT
I NST.

DECODE

EXECUTION
OUTPUT·
ADDRESS

INC. PC

1.36 ~.ec CYCLE

1
I

INPUT

INSTRUCTION CYCLE
(1 BYTE, 2 CYCLE INSTRUCTION ONLY)

...,It--.....

...

- - - 1 S T CYCLE------I.~I
. 01(------2ND CYCLE----..
~I

PREVIOUS CYCLE-..
STATE TIME:
S2

(02)"TO

ALE
PSEN" ----------~
RD,WR _____________________________________

"EXTERNAL MODE

"IF ENABLED

S04SAH/S049AH TIMING

Figure 12-10. MCS®-48 Timing Generation and Cycle Timing

12.1.13 Single-Step
This feature, as pictured in Figure 12-13, provides the
user with a debug capability in that the processor can be
stepped through the program one instruction at a time.
While stopped, the address of the next instruction to be
fetched is available concurrently on BUS and the lower

12·11

half of Port 2. The user can therefore follow the program
through each of the instruction steps. A timing diagram,
showing the interaction' between output ALE and input
S8, is shown. The BUS buffer contents are lost during
single step; however, a latch may be added to reestablish
the lost 110 capability if needed. Datais valid at the leading
edge of ALE.

CYCLE 1
INSTRUCTION

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

'INCREMENT
TIMER

READ
PORT

OUTLP,A

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

'INCREMENT
TIMER

OUTPUT
TO PORT

'INCREMENT
TIMER

READ PORT

FETCH
IMMEDIATE DATA

'INCREMENT
TIMER

READ PORT

FETCH
IMMEDIATE DATA

INCREMENT
TIMER

READ
PORT

OUTPUT
TO PORT

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

...
......

ORL P,

=DATA

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

....

INS A, BUS

:::J:

3"
:i"
cc
c

ii'

INCREMENT
PROGRAM COUNTER

'OUTPUT
TO PORT

INCREMENT
PROGRAM COUNTER

'OUTPUT
TO PORT

o
o

'OUTPUT
TO PORT

READ PORT

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

'INCREMENT
TIMER

READ PORT

FETCH
IMMEDIATE DATA

INCREMENT
PROGRAM COUNTER

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

OUTPUT RAM
ADDRESS

INCREMENT
TIMER

OUTPUT
DATA TO RAM

MOVXA,@R

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

OUTPUT RAM
ADDRESS

INCREMENT
TIMER

MOVDA,PI

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

OUTPUT
OPCODE/ADDRESS

INCREMENT
TIMER

MOVDPI,A

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

OUTPUT
OPCODE/ADDRESS

INCREMENT
TIMER

OUTPUT DATA
TO P2LOWER

ANLD P,A

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

OUTPUT
OPCODE/ADDRESS

INCREMENT
TIMER

OUTPUT
DATA

C/)

ORLD P,A

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

OUTPUT
OPCODE/ADDRESS

INCREMENT
TIMER

OUTPUT
DATA

-I

J(CONDiTIONAL)

FETCH
INCREMENT'
INSTRUCTION PROGRAM COUNTER

SAMPLE
CONDITION

'INCREMENT
SAMPLE

FETCH
, IMMEDIATE DATA

UPDATE
PROGRAM COUNTER

STRTT
STRTCNT

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

START
COUNTER

STOP TCNT

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

STOP
COUNTER

ENI

FETCH
INClIEMENT
INSTRUCTION PROGRAM COUNTER

ENABLE
INTERRUPT

DISI

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

' DISABLE
INTERRUPT

ENTOCLK

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

=DATA

:::.

0
:;,
-I

'OUTPUT
TO PORT

:::J:

INCREMENT
PROGRAM COUNTER

FETCH
IMMEDIATE DATA

MOVX@'R,A

'INCREMENT
TIMER

2l.
c:
(')

ORL BUS,

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

FETCH
INCREMENT
ANL BUS, =DATA
INSTRUCTION PROGRAM COUNTER

OUTLBUS,A

iii
~
CD

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

INCREMENT
TIMER

CYCLE 2

INA,P

=DATA

;

ANL P,

cO
c:

I\)

ENABLE
CLOCK

READ
DATA
READ P2
LOWER

, -

o
Z

-I

C/)

....
I

'VALID INSTRUCTION ADDRESSES ARE OUTPUT
AT THIS TIME IF EXTERNAL PROGRAM MEMORY IS
BEING ACCESSED,
(1) IN LATER MCS-48 DEVICES TlIS SAMPLED IN S4.

-<
C/)

SINGLE COMPONENT MCS®-4S SYSTEM

dear input. ALE should be buffered since the clear input
of an SN7474 is the equivalent of 3 TTL loads. The
processor is now in the stopped state. The next instruction
is initiated by clocki!!s a "1" into the flip-flop. This' '1"
will not appear on SS unless ALE is high removing clear
from the flip-flop. In response to SS going high the processor be~s an instruction fetch which brings ALE low
resetting SS through the clear input and causing the processor to again enter the stopped state.

EXTERNAL RESET

Vcc
ACTIVE
PULLUP

12.1.14 Power Down Mode
(8048AH, 8049AH, 8050AH,
8039AHL, S035AHL, S040AHL)

POWER ON RESET

Vcc
~

Exqa circuitry has been added to the 8048AHl8049AHI
8050AH ROM version to allow power to be removed from
all but the dllta RAM array for low power standby operation. In the power down mode the contents of data RAM
can be maintained while drawing typically 10% to 15%
of normal operating power requirements.

[

v ce serves as the 5V supply pin for the bulk of circuitry

Figure 12-12

TIMING
The 8048AH operates in a single-step mode as follows:
1) The processor is requested to stop by applying a low
level on SS.
2) The processor responds by stopping during the address
fetch portion of the next instruction. If a double cycle
instruction is in progress when the single step command is received, both cycles will be completed before
stopping.
3) The processor acknowledges it has entered the stopped
state by raising ALE high. In this state (which can be
maintained indefinitely) the address of the next instruction to be fetched is present on BUS and the lower
half of port :2.
4) SS is then raised high to bring the processor out of the
stopped mode allowing it to fetch the next instruction.
The exit from stop is indicated by the processor bringing ALE low.
5) To stop the processor at the next instruction SS must
be brought low again soon after ALE goes low. If SS
is left high the processor· remains in a "Run" mode.
A diagram for implementing the single-step function of
the 8748H is shown in Figure 12-13. D-type flip-flop with
preset and clear is used to generate SS. In the run mode
SS is held high by keeping the flip-flop preset (preset has
precedence over the clear input). To enter single step,
preset is removed allowing ALE to bring SS low via the

12-13

while the VDD pin supplies only the RAM array. In normal
operation both pins are a 5V while in standby, Vee is at
ground and VDD is maintained at its standby value. Applying Reset to the processor through the RESET pin
inhibits any access to the RAM by the processor and
guarantees that RAM cannot be inadvertently altered as
power is removed from Vce'
A typical power down sequence (Figure 12-14) occurs as
follows:
1) Imminent power supply failure is detected by user defined circuitry. Signal must be early enough to allow
8048AH to save all necessary data before Vce falls
below normal operating limits.
2) Power fail sign;!l is used to interrupt processor and
vector it to a power fail service routine.
3) Power fail routine saves all important data and machine
status in the internal data RAM array. Routine may
also initiate transfer of backup supply to the VDD pin
and indicate to external circuitry that power fail routine
is complete.
4) Reset is applied to guarantee data will not be altered
as the power supply falls out of limits. Reset must be
held low until Vce is at ground level.
Recovery from the Power Down mode can occur as any
other power-on sequence with an external capacitor on
the Reset input providing the necessary delay. See the
previous section on Reset.

SINGLE COMPONENT MCS®-48 SYSTEM

+5V

SINGLE
STEP

+5V

MOMENTARY
PUSHBUTTON

10K

~U~N--~------------'

10K

PRESET

+5V

.-------t> CLOCK
10K

DEB OUNCE
LATCH

1/27400
ALE
SINGLE STEP CIRCUIT

I S3 I

.S3

ALEJi

BUS

P20-23

1/0

PC 0-7

;

PC 8-11

SINGLE STEP TI~ING

Figure 12·13. Single Step Operation

12-14

c
1/0

SINGLE COMPONENT MCS®-48 SYSTEM

reset the prescaler and time state generators. TO may then
be brought down with the rising edge of X 1. Two clock
cycles later, with the rising edge of Xl, the device enters
into, Time State I, Phase I, SS' is then brought down to
5 volts 4 clocks later after TO. RESET' is allowed to go
high 5 tCY (75 clocks) later for normal execution of code.
See Figure 12-15.

POWER~
SUPPLY

PROCESSOR

i' "----

INTE~RUPTED I

POWER - - - - - ,
. I
I
SUPPLY
_._ '_ _I _ _ I_ _ _
FAIL SIGNAL
I
I
I
I
I
RESET

NORMAL
POWERON
SEQUENCE
FOLLOWS

12.1.17 Idle Mode

LJ ___ _

:
I

DATA SAVE
ROUTINE
EXECUTED

Along with the standard power down, the'SOC43S, SOC49 ,
SOC50 has added an IDLE mode instruction (OIH) to give
. even further flexibility and power management. In the
IDLE mode, the CPU is frozen while the oscillator, RAM,
timer, and the interrupt circuitry remains fully active.

ACCESS TO
DATA RAM
INHIBITED

When the IDL instruction (OIH) is decoded, the clock to
the CPU is stopped. CPU status is preserved in its entirety:
the Stack Pointer, Program Counter, Program Status
Word, Accumulator, RAM, and all the registers maintain
their data throughout idle.

Figure 12-14. Power Down Sequence

12.1.15 External Access Mode
Normally the first IK (S04SAH), 2K (S049AH), or 4K
(S050AH) words of program memory are automatically
fetched from internal ROM or EPROM. The EA input pin
however allows the user to 'effectively disable internal
program memory by forcing all program memory fetches
. to reference external memory. The following chapter explains how access 1'0 external program memory is
accomplished.
The External Access mode is very useful in system test
and debug because it allows the user to disable his internal
appli~ations program and substitute an external program
of his choice - a diagnostic routine for instance. In addition, section 12.4 explains how internal program memory can be read externally, independent of the processor.
A "I" level on.EA initiates the external accesss mode.
For proper operation, Reset should be applied while the
EA input is changed.

12.1.16 Sync Mode
The S04SAH, S049AH, S050AH has incorporated a new
SYNC mode. The Sync mode is provided to ease the
design of multiple controller circuits by allowing the designer to force the device into known phase and state time.
The SYNC mode may also be utilized by automatic test
equipment (ATE) for quick, easy, and efficient synchronizing between the tester and the DUT (device under test).
SYNC mode is enabled when SS' pin is raised to high
voltage level of + 12 volts. To begin synchronization, TO
is raised to 5 volts at least four clocks cycles after SS'.
TO must be high for at least four X 1 clock cycles to fully

12-15

Externally, the following occurs duriQg idle:
I) The ports remain in the logical state they were in when
idle was executed.
2) The bu's remains in the logical state it was in when
idle was executed if the bus was latched.
If the ,bus was in It high Z condition or if external
program memory is used the bus will remain in the
float state.

3) ALE remains in the inactive state (low).
4) RD', WR' , PROG' , and PSEN' remains in the inactive
state (high).
5) TO outputs clock if enabled.
There are three ways of exiting idle. Activating any enabled interrupt (external or timer) will cause the CPU to
vector to the appropriate interrupt rontine. Following a
RETR instruction, program execution will resume at the
instruction following the address that contained the IDL
instruction.
The FO and FI flags may be used to give an indication if
the interrupt 9ccurred during normal program execution
or during i4le.This is done by setting· or clearing the flags
before going into idle. The interrupt service routine can
examine the flags and act accordingly when idle is terminated by an interrupt.
Resetting the device can also terminate idle. Since the
oscillator is already running, five machine cycles are all
that .is required to insure proper machine operation.

.SINGLE COMPONENT MCS®-48 SYSTEM

PHASE 1- -

PHASE 2- -

TIME STATE
SS

.5V
1..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
12V~r---------------------------------------------'

OV
TO OV-------------------j
5V

5V.
5V

ALE

.------.

OV-------------------------~

1..-_ _ __

OV--------------------------------------SYNC MODE TIMING

Figure 12-15. Sync Mode Timing

12.2 PIN DESCRIPTION

PORT
#1 .

PORT
#2

The MCS-48 processors are packaged in 40 pin Dual InLine Packages (DIP's). Table 12-3 is a summary of the
functions of each pin. Figure 12-16 is the logic symbol
for the 8048AH product family. Where it exists, the second paragraph describes each pin's function in an expanded MCS-48 system. Unless otherwise specified, each
input is TTL compatible and each output will drive one
standard TTL load.

RESET
SINGLE STEP
EXTERNAL
MEM
TEST {
INTERRUPT
BUS

8048AH
8049AH
8050AH

READ
WRITE
PROGRAM
STORE ENABLE
ADDRESS
LATCH ENABLE

Figure 12-16. 8048AH and 8049AH Logic Symbol

12-16

SINGLE COMPONENT MCS®-48 SYSTEM

Table 12-3. Pin Description
"

Designation

Pin
Number·

Function

Vss

Circuit G N D potential

VDD

Programming power supply; 21 V during program for the 8748H18749H; + 5V during
operation for both ROM and EPROM. Low power standby pin in 8048AH and
8049AHl8050AH ROM versions.

Vee

Main power supply; +5V during operation and during 8748H and 8749H programming.

PROG

Program pulse; + 18V input pin during 8748H /8749H programming. Output strobe
for 8243 I/O expander.

PIO-PI7
(Port I)

27-34

8-bit quasi-bidirectional port, (Internal Pullup = 50KH)

P20-P27
(Port 2)

21-24
35-38

8-bit quasi-bidirectional port. (Internal Pullup

= 50KU)

P20-P23 contain the four high order program counter bits during an external program memory fetch and serve as a 4-bit IjO expander bus for 8243.
DO-D7
(BUS)

,12-19

True bidirectional port which can be written or read synchronously using the RD.
WR strobes. The port can also be statically latched.
Contains the 8 low order program counter bits during an external program memory fetch. and receives the addressed instruction under the control of PSEN, Also
contains the address and data during an external RAM data store instruction.
under control of ALE. RD. and WR,

.[0

Input pin testable using the conditional transfer instructions JTO and J NTO. TO
can be designated as a clock output using ENTO CLK instruction. TO is also used
during programming and sync mode.

Input pin testable using the JTI. and JNT I instructions. Can be designated the
event counter input using the STRT CNT instruction. (See Section 2,1.10)

iNT

Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled
after a reset. (Active low)

-RD

Interrupt must re~ain low for at least 3 machine cycles to ensure proper operation.
8

Output strobe activated during a BUS relld. Can be used to enable data onto the
BUS from an external device. (Active low)
Used as a Read Strobe to External Data Memory.

RESET

4
"

Input which is used to initialize the processor, Also used during EPROM programming
and verification. (Active low) (Internal pullup "" 80K 0)

Output strobe during a BUS write. (Active low) Used as write strobe to external
data memory.

ALE

Address Latch Enable. This signal occurs once during each cycle and is useful as
a clock output.
The negative edge ,of A LE strobes address into external data and program memory.

12-17

SINGLE COMPONENT MCS®-48 SYSTEM

Table 12,3. Pin Description (Continued)
Designation

Pin
Number·

Function

PSEN

Program Store Enable. This output occurs only during a fetch to external program
memory. (Active low)

-SS

Single step input can be used in conjunction with ALE to "single step" the processor
through each instruction. (Active low) (Internal pullup 300K!!) + l2V for sync
modes (See 2.1.16)

External Access input which forces all program memory fetches to reference external memory. Useful for emulation and debug, and essential for testing and program verification. (Active high) + 12V for 8048AH /8049AH /8050AH program
verification and +18V for 8748H/8749H program verification (Internal pullup
10M!! on 8048AH/8049AH/8035AHL/8039AHL/8050AH/8040AHL)

XTALI

One side of crystal input for internal oscillator. Also input for external source.

XTAL2

Other side of crystal/external source input.

'Unless otherwise stated. Inputs do not have internal pullup resistors. 8048AH, 8748H, 8049AH, 8050AH, 8040AHL

12.3 PROGRAMMING, VERIFYING AND
ERASING EPROM

8748H AND 8749H ERASURE
CHARACTERISTICS

The internal Program Memory of the 8748H and the
8749H may be erased and reprogrammed by the user as
explained in the following sections. See also the 8748H
and 8749H data sheets.

The erasure characteristics of the 8748H and 8749H are
such that erasure begins to occur when exposed to light
with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000A range. Data show that constant exposure to
room level fluorescent lighting could erase the typical
8748H and 8749H in approximately 3 years while it would
take approximately 1 week to cause erasure when exposed
to direct sunlight. If the 8748H or 8749H is to be exposed
to these types of lighting conditions for extended periods
of time, opaque labels should be placed over the 8748H
window to prevent unintentional erasure.

12.3.1 ProgrammingNerification
In brief, the programming process consists of: activating
the program mode, applying an address, latching the address, applying data, and applying a programming pulse.
This programming algorithm applies to both the 8748H
and 8749H. Each word is programmed completely before
moving on to the next and is followed by a verification
step. The following is a list of the pins used for programming and a descsription of their functions:
Pin
XTAL 1
Reset
Test 0

EA
BUS
P20-1
P20-2
V DD

PROG
Pl(~·PIl

When erased, bits of the 8748H and 8749H Program Memory are in tl\e logic "0" state.

Func;tion
The recommended erasure procedure for the 8748H and
8749H is exposure to shortwave ultraviolet light which
has a wavelength of 2537 Angstroms (A). The integrated
dose (Le., UV intensity X exposure time) for erasure
should be a minimum of l5W-sec/cmz. The erasure time
with this dosage is approximately 15 to 20 minutes using
an ultraviolet lamp with a l2000J.tW/cm z power rating.
The 8748H and 8749H should be placed within one inch
from the lamp tubes during erasure. Some lamps have a
filter in their tubes and this filter should be removed before
erasure.

ClOCk Input (3 to 4 MHz)
Initialization and Address Latching
Selection of Program (OV) or Verify
(5V) Mode
Activation of Program/Verify Modes
Address and Data Input Data Output
During Verify
Address Input for 8748H
Address Input for 8749H
Programming Power Supply
Program Pulse Input
Tied to ground (8749H only)
12-18

SINGLE COMPONENT MCS-48 SYSTEM

COMBINATION PROGRAMIVERIFY MODE (EPROM'. ONLY)

18V
/
EA 5V _ _ _ _....J
I--------PROGRAM--------!+--'VERIFY'--"i----PROGRAMTO
IWW-

IAW-l---t--t-1WA
~

r-~O~A=TA~T=O~B=E-~

DBO-DB7 ~ - -

PROGRAMMED VALID

LAST
ADDRESS

P20-P22

IVDDwnIVD~H

~
'DO

NEXT
ADDRESS

ADDRESS (8-10) VALID

+5----------------

PROG+:: _ _ _ _ _ _ _ _

-------------------------

~:J])--J{l~:

-------==--::-"'\....- - - -

VERIFY MODE (ROM/EPROM)
EA

_--II

·TO

RE~ET ~..._________~;'

DBO-DB7

==>---

P20-P22

\---------/

ADDRESS
(0-7) VALID

ADDRESS (8-10) VALID

NEXT ADDRESS VALID

NOTES:
1. PROG MUST FLOAT IF EA IS LOW (I.E., ¥o18V).

·TO QN EPROM ONLY.

Figure 12-17. ProgramNerlfy Sequence for 8749H/8748H

12-19

Expanded MCS®48 System

CHAPTER 13
EXPANDED MCS®-48 SYSTEM
13.0 INTRODUCTION

1) The contents of the 12-bit program counter will be
output on BUS and the lower half of port 2.
2) Address Latch Enable (ALE) will indicate the time at
which address is valid. The trailing edge of ALE is
used to latch the address externally.

If the capabilities resident on the single-chip 8048AH/

8748H18035AHU8049AHl8749H/8039AHL are not sufficient for your system requirements, special on-board circuitry allows the addition of a wide variety of external
memory, I/O, or special peripherals you may require. The
processors can be directly and simply expanded in the
following areas:

3) Program Store Enable (PSEN) indicates that an external instruction fetch is in progress and serves to enable
the external memory device.
4) BUS 'reverts to input (floating) mode and the processor
accepts its 8-bit contents as an instruction word.

• Program Memory to 4K words
• Data Memory to 320 words (384 words with
8049AH)

• 110 by unlimited amount
• Special Functions using 8080/8085AH peripherals

ALE

By using bank switching techniques, maximum capability
is essentially unlimited. Bank switching is discussed later
in the chapter. Expansion is accomplished in two ways:

PSEN
FLOATING

I) Expander 110 - A special 110 Expander circuit, the
8243, provides for the addition of four 4-bit Input!
Output ports with the sacrifice of only the lower half
(4-bits) of port 2 for inter-device communication. Multiple 8243' s may be added to this 4-bit bus by generating the required "chip select" lines.

BUS

~FLOATING~ FLOATING
ADDRESS

INSTRUCTION

Figure 13-1. Instruction Fetch from
External Program Memory

2) Standard 8085 Bus ~ One port of the 8048AH/
8049AH is like the 8-bit bidirectional data bus of the
8085 microcomputer system allowing interface to the
numerous standard memories and peripherals of the
MCS®-80/85 microcomputer family.

All instruction fetches, including internal addresses, can be
forced to be external by activating the EA pin of the 8048AHI
8049AH!8d50AH. The 8035AHU8039AHLl8040AHL processors without program memory always operate in the external program memory mode (EA = 5V).

MCS-48 systems can be configured using either or both
of these expansion features to optimize system capabilities
to the application.

13.1.2 Extended Program Memory
Addressing (Beyond 2K) .

Both expander devices and standard memories and peripherals can be added in virtually any number and combination required.

For programs of 2K words or less, the 8048AH/8049AH
addresses program memory in the conventional manner.
Addresses beyond 2047 can be reached by executing a
program memory bank switch instruction (SEL MBO, SEL
MBI) followed by a branch instruction (JMP or CALL).
The bank switch feature extends the range of branch instructions beyond their normal 2K range and at the same
time prevents the user from inadvertently. crossing the 2K
boundary.

13.1 EXPANSION OF PROGRAM MEMORY
Program Memory is expanded beyond the resident IK or
2K words by using the 8085 BUS feature of the MCS®48. All program memory fetches from the addresses less
than 1024 on the 8048AH and less than 2048 on the
8049AH occur internally with no external signals being
generated (except ALE which is always present). At address 1024 on the 8048AH, the processor automatically
initiates external program memory fetches.

PROGRAM MEMORY BANK SWITCH

The switching of 2K program memory banks is accomplished by directly setting or resetting the most significant
bit of the program counter (bit II); see Figure 13-2. Bit
11 is not altered by normal incrementing of the program
counter but is loaded with the contents of a special flipflop each time a JMP or CALL instruction is executed.
This special flip-flop is set by executing an SEL MB 1

13.1.1 Instruction Fetch Cycle (External)
As shown in Figure 13-1, for all instruction fetches from
addresses of 1024 (2048) or greater, the following will
occur:
13-1

EXPANDED MCS®-48 SYSTEM

---------instruction and reset by SEL MBO. Therefore, the SEL
MB instruction may be executed at any time prior to the
actual bank switch which occurs during the next branch
instruction encountered. Since all twelve bits of the program counter, including bit 11, are stored in the stack,
when a Call is executed, the user may jump to subroutines
across the 2K boundary and the proper bank will be restored upon return. However, the bank switch flip-flop
will not be altered on return.

counter is held at "0" during the interrupt service routine.
The ~nd of the service routine is signalled by the execution
of an RETR instruction. Interrupt service routines should
therefore be contained entirely in the lower 2K words of
program memory. The execution of a SEL MBO or SEL
MB I instruction within an interrupt routine is not recommended since it will not alter PCII while in the routine,
but will change the internal flip-flop.

13.1.3 Restoring 1/0 Port Information

IAftIAwl~I~I~I~I~I~I~I~I~I~1

Conventional Pr~gram Counter
• Counts OOOH to 7FFH
• Overflows 7FFH to OOOH
JMP or CALL instructions transfer contents
of internal flipflop to All

Although the lower half of Port 2 is used to output the
four most significant bits of address during an external
program memory fetch, the I/O information is still outputed during certain portions of each machine cycle. 110
information is always present on Port 2' slower 4 bits at
the rising edge of ALE and can be sampled or latched at
this time.

• Flipflop set by SEL MBl
• Flipflop reset by SEL MBO
or by RESET

13.1.4 Expansion Examples

During interrupt service routine
All is forced to "0"
All 12 bits are saved in stack

Shown in Figure 13-3 is the addition of 2K words of
program memory using an 2716A 2K x 8 ROM to give
a total of 3K words of program memo!y:"'!!! this case no
chip select decoding is required and PSEN enables the
memory directly through the chip select input. If the system requires. only 2K of program memory, the same configuration can be used with an 8035AHL substituted for
the 8048AH. The 8049AH would provide 4K of program
memory with the same configuration.

Figure 13-2. Program Counter
INTERRUPT ROUTINES
Interrupts always vector the program counter to location
3 or 7 in the first 2K bank, and bit II of the program

PORT 20-22

'(7
8048AH

ALE

BUS
PSEN

rr=V

to..

11 )

8282
LATCH

ADDRESS
2716
EPROM
·DATA
OUT
CS

USING 2K x 8 EPROM

Figure 13-3. Expanding MCS®-48 Program Memory Using Standard Memory Products

13-2

EXPANDED MCS®-48 SYSTEM

Figure 13-4 shows how the 8755/8355 EPROM/ROM with
110 interfaces directly to the 8048AH without the need
for
address latch. The 8755/8355 contains an internal
8-bit address latch eliminating the need for an 8212 latch.
In addition to a 2K x 8 program memory, the 8755/8355
also contains 16 I/O lines addressable as two 8-bit ports.
These ports are addressed as external RAM; therefore the
RD and WR outputs of the 8048AH are required. See the
following section on data memory expansion for more
detail. The subsequent section on 110 expansion explains
the operation of the 16 110 lines.

ALE

iffi
804BAH
B049AH

lOW

2Kx8

lOR

E~~~~
WITH

AlDO_7

8~~1

1/0

8755
Aa-A10. CS

13.2 EXPANSION OF DATA MEMORY
Data Memory is expanded beyond the resident 64 words
by using the 8085AH type bus feature of the MCS®-48.
TEST
INPUTS

13.2.1 ReadlWrite Cycle

1/0

All address and data is transferred over the 8 lines of
BUS. As shown in Figure 13-5, a read or write cycle
occurs as follows:

Figure 13-4. External Program Memory Interface

ALE

>8<___

BUS

FL_O_A_T_IN_G_ __

READ FROM EXTERNAL DATA MEMORY

ALE

BUS

FLOATING

WRITE TO EXTERNAL DATA MEMORY

FIgure 13·5. External Data Memory Timings

13-3

EXPANDED MC.S~-48 SYSTEM

I) The contents of register RO or Rl is outputed on BUS.
2) Address Latch Enable (ALE) indicates addresss is
valid. The trailing edge of ALE is used to latch the
address externally.
3) A read (RD) or write (WR) pulse on the corresponding
output pins of the S04SAH indicates the type of data
memory access i!!.£!.ogress. Output data is valid at the
trailing edge of WR and input data must be valid at
the trailing edge of RD.

1'3.3 EXPANSION OF INPUT/OUTPUt
There are four possible modes of 110 expansion with the
S04SAH: one using a special low-cost expander, the S243;
another using standard MCS-SO/S5 1/0 devices; and a third
using the combination memory 110 ex,pander devices the
S155, S355, and S755. It is also possible to expand using
standard TTL devices as shown in Chapter 5.

13.3.1 I/O Expander Devi.ce

4) Dat (S bits) is transferred in or out over BUS.

13.2.2 Addressing External Data Memory
External Data Memory is accessed with its own two-cycle
move instructions. MOVXA, @R and MOVX@R, A,
which transfer S bits of data between the accumulator and
the external memory location addressed by the contents
of one of the RAM Pointer Registers RO and RI. This
allows 256 locations to be addressed in addition to, the
resident lOCations. Additional pages may be added by
"bank switching" with extra output lines ofthe S04SAH.

13.2.3 Examples of Data Memory Expansion
Figure 13-6 shows how the S04SAH can be expanded
using the SI55 memory and 110 expanding device. Since
the S155 has an internalS-bit address latch, it can interface
directly to the S04SAH without the use of an external
latch. The S155 provides an additional 256 words of static
data memory and also includes 22 1/0 lines and a 14-bit
timer. See the following section on 110 expansion and the
S155 data sheet for more details on these additional
features.

BUS

ALE

8048AH

The most efficient means of 110 expansion for small systems is the S243 110 Expander Device which requires only
4 port lines (lower half of Port 2) for communication with
the 804SAH. The S243 contains four 4-bit 110 ports which
serve as an extension of the on-chip 110 and are addressed
as ports #4-7 (see Figure 13-7). The following operations
may be performed on these ports:
• Transfer Accumulator to Port
• Transfer Port to Accumulator
• AND Accumulator to Port
• OR Accumulator to Port
A 4-bit transfer from a port to the lower half of the Accumulator sets the most significant four bits to zero. All
communication between the S04SAH and the S243 occurs
over Port 2 lower (P2O-P23) with timing provided by an
output pulse on the PROG pin of the processor. Each transfer consists of two 4-bit nibbles: The first containing the
"op code" and port address, and the second containing
the actual 4 bits of data.

ADO_7

ALE 8155
256 x 8
\VA RAM

PORT

3
18

TEST
INPUTS

I/O
TIMER IN
TIMER OUT

101M

) 1/0

Figure 13-6. 8048AHlnterfaceto·256 x 8 Standard Memories

EXPANDED MCS®-48 SYSTEM

fl
-;:-

...I\.
20

1/0

CHIP SELECT CONNECTIO N IF MORE
THAN ONE EXPANDER IS USED
A.

4
A

a050AH
a049AH
8048AH

] T::JTS

1/0

8243
A

P2O-P23

1/0

PROG

1/0

DATA IN
P2

1/0

EXPANDER INTERFACE

BITS 0, 1

MOO

P20-P23

BITS2,3

'--. _ _ _- J/

JX"'_____.-J)>-----

OO} PORT
OO}
READ
01
01
WRITE
OR
10
ADDRESS 10
11
11
AND

---("',_ _ _

DATA (4-BITS)

ADDRESS
ANDOPCODE
(4-BITS)

OUTPUT EXPANDER TIMING

Figure 13-7. 8243 Expander 1/0 Interface

Nibble I
2 I 0

II II IAIA I
Instruction
Code

13.3.2 1/0 Expansion with Standard
Pttr1pherals

Nibble 2
2 I 0

Standard MCS-80/85 type I/O devices may be added to
the MCS@-48 using the same bus and timing used for Data
Memory expansion. Figure 13-8 shows an example of how
an 8048AH: can be connected to an MCS-85 peripheral.
110 devices reside on the Data Memory bus and in the
data memory address space and are accessed with the same
MOVX instructions. (See the previous section on data
memory expansion for a description of timing.) The following are a few of the Standard MCS-80 devices which
are very useful in MCS@-48 systems:
• 8214 Priority Interrupt Encoder
• 8251 Serial Communications Interface
• 8255 General Purpose Programmable 110
• 8279 Keyboard/Display Interface
• 8253 Interval Timer

I did Idid I
Port

data

Address

1_1_ _

00 Read
01 Write
100R
II AND

00
01
10
II

Port
Port
Port
Port

#4
#5
#6
#7

A high to low transition of the PROG line indicates that
address is present, while allow to high transition indicates
the presence of data. Additional 8243's may be added to
the four-bit bus and chip selected using additional output
lines from the 8048AHl8748H.

!/O PORT CHARACTERISTICS

13.3.3 Combination Memory and
1/0 Expanders

Each of the four 4-bit ports of the 8243 can serve as either
input or output and can provide ·high drive capability in
both the high and low state.

As mentioned in the sections on program and data memory
expansion, the 8355/8755 and 8155 expanders also contain
110 capability.

13-5

EXPANDED MCS®,.48 S,YSTEM

8
INT

INT

P20

C/D
8279
KEYBOARD
DISPLAY

8048Ati
RD

BUS

KEYBOARD
INPUTS

SCAN
OUTPUTS
(A) DISPLAY
OUTPUT

DATA
BUS

(B) DISPLAY
OUTPUT

-::-

Figure 13·8. Keyboard/Display Interface
8355/8755: These two parts of ROM and EPROM equivalents and therefore contain the same I/O structure. I/O
consists of two 8-bit ports which normally reside in the
external data memory address space and are accessed with
MOVX instructions. Associated with each port is an 8bit Data Direction Register which defines each bit in the
'port as either an input or an output. The data direction
registers are directly addressable, thereby allowing the
user to define under software control each individual bit
of the ports as either input or output. All outputs are
statically latched and double buffered. Inputs are not
latched.
8155/8156: I/O- on the 8155/8156 is configured as two
8-bit programmable 110 ports and one 6-bit programmable

BUS

PORT l'
8048AH

port. These three registers and a Control/Status register
are accessible as external data memory with the MOVX
instructions., The 'contents of the control register determines the mode of the three ports. The ports can be programmed as input or output with or without associated
handshake communication lines. In the handshake mode,
lines of the six-bit port become input and output strobes
for the two 8-bit ports. Also included in the 8155 is a
14-bit programmable timer. The clock inputto the timer
and the timer overflow output are available on external
pins. The timer can be programmed to stop on terminal
count or to continuously reload itself. A square wave or
pulse output on terminal count can also be specified.

PROGr-------~--~~-----~------4-------------~------------~

Figure 13·9. Low Cost 110 Expansion

13-6

EXPANDED MCS®-48 SYSTEM

110 EXPANSION EXAMPLES

Figure 13-10 shows the 8048AH interface to a standard
MCS$-80 peripheral; in this case, the 8255 Programmable
Peripheral Interface, a 4O-pin part which provides three
8-bit programmable 110 ports. The 8255 bus interface is
typical of programmable MCS$-80 peripherals with an
8-bit bidirectional data bus, a RD and WR input for Read!
Write control, a CS (chip select) input used to enable the
Read!Write control logic and the address inputs used to
select various internal registers.

Figure 13-9 shows the expansion of 110 using multiple
8243's. The only difference from a single 8243 system is
the addition of chip selects provided by additional 8048AH
output lines. Two output liens and a decoder could also
be used to address the four chips. Large numbers of 8243' s
would require a chip select decoder chip such as the 8205
to save 110 pins.

8255
A1 PROGRAM·
MABLE
PERIPHERAL
INTERFACE
RO
WR

8048AH ALE
RO

WR
BUS

00-7

PORT
A

P20
P21

AO
8255
A1 PROGRAM·
MABLE
PERIPHERAL
INTERFACE

PORT
B

8048AH _
RO

PORT
C

BUS

PORT
B
PORT
C

00-7

CS
OPTION #1

PORT
A

-::-

OPTION #2

-::-

Figure 13·10. Interface to MCS®·80 Peripherals
addressing of the various memories and 110 ports. Note
that in this configuration address lines AIO and AlI have
been 0 Red to chip select the 8355. This ensures that the
chip is active for all external program memory fetches in
the IK to 3K range and is disabled for all other addresses.
This gating has been added to allow the I/O port of the
8355 to be used. If the chip was left selected all the time,
there would be conflict between these ports and the RAM
and lIO of the 8156. The NOR gate could be eliminated
and All connected directly to the CE (instead of CEl input
of the 8355; however, this would create a IK word "hole"
in the program memory by causing the 8355 to be active
in the 2K and 4K range instead of the normal IK to 3K
.range.

Interconnection to the 8048AH is very straightforward
with BUS, RD, and WR connecting directly to the corresponding pins on the 8255. The only design consideration is the way in which the internal registers of the 8255
are to be addressed. If the registers are to be addressed
as external data memory using the MOVX instructions,
the appropriate number of address bits (in this case, 2)
must be latched on BUS using ALE as described in the
section on external data memories. If only a single device
is connected to BUS, the 8255 may be continuously selected by' grounding CS. If multiple 8255's are used, additional address bits can be latched and used as chip
selects.
A second addressing method eliminates external latches
and chip select decoders by using output port lines as address and chip select hnes directly, ,rhLS method, of
course, requires the setting of an output port with address
information prior to executlng a MOYX instruction.

In this system the various locations are addressed as
follows:
• Data RAM - Addresses 0 to 255 when Port 2 Bit
o has been previously set = 1 and Bit 1 set = 0
• RAM 110 - Addresses 0 to 3 when Port 2 Bit 0 =
1 and Bit I = 1

13.4 MULTI-CHIP MCS®·48 SYSTEMS

• ROM lIO Bit 3 = I

Figure 13- i I shows the addition of two memory expanders
to the 8048AH, one 8355/8755 ROM and one 8156 RAM.
The main consideration in designing such a system is the

Addresses 0 to 3 when Port 2 Bit 2 or

See the memory map in Figure 13-12.

13-7

EXPANDED MCS®.48 SYSTEM

8156/8355
A8-10

PORT
83551

8755

ROM
EPROM

PORT

ALE
PSEN
8048AH

WR
BUS

TIMER
OUT

Figure 13-11. The Three-Component MCS®-48 System

13.5 MEMORY BANK SWITCHING
Certain systems may require more than the 4K words of
program 'memory which are directly addressable by the
program counter or more than the 256 data memory and
1/0 locations directly addressable by the pointer registers
RO and Rl. These systems can be achieved using "bank
switching" techniques. Bank switching is merely the selection of various blocks of "banks" of memory using
dedicated output port lines from the processor. In the case
of the 8048AH, program memory is selected in blocks of
4K words at a time, while data memory and 110 are enabled 256 words at a time.
The most important consideration in implementing two or
more banks is the software required to cross the 'bank
boundaries. Each crossing of the boundary requires that
the processor first write a control bit to an output port
before accessing memory or 1/0 in the new bank.' If program memory is being switched, programs should be organized to keep boundary crossings to a minimum.

13,8

Jumping to subroutines across the boundary should be
avoided when possible since the programmer must keep
track of which bank to return to after completion of the
subroutine. If these subroutines are to be nested and accessed from either ;bank, a software "stack" should be
implemented to save the bank switch bit just as if it were
another bit of the program counter.
From a hardware standpoint bank switching is very
straightforward and involves only the connection of an
110 line or lines as bank enable signals. These enables are
ANDed with normal memory and 110 chip select signals
to activate the proper bank.

13.6 CONTROL SIGNAL SUMMARY
Table 13 summarizes the instructions which activate the
various control outputs of the MCS@-48 processors. During all other instructions these outputs are driven to the
active state.

EXPANDED MCS®-48 SYSTEM

Table 13-1. MCS®-48 Control Signals
Control
Signal
When Active
RD

During MOVX, A, @R or INS Bus

During MOVX @R, A or OUTL Bus

ALE

Every Machine Cycle

PSEN

During Fetch of external program memory (instruction or immediate data)

PROG

During MOVD, A,P ANLD P,A MOVD
P,A ORLDP,A

The latched mode (INS, OUTL) is intended for use in the
single-chip configuration where BUS is not begin used as
an expander port. OUTL and MOVX instructions can be
mixed if necessary. However, a previously latched output
will be destroyed by executing a MOVX instruction and
BUS will be left in the high impedance state. INS does
not put the BUS in a high impedance state. Therefore,
the use of MOVX after OUTL to put the BUS in a high
impedance state is necessary before an INS instruction
intended to read an external word (as opposed to the previously latched value).
OUTL should never be used in a system with extern,,:
program memory, since latching BUS can cause the nf
instruction, if external, to be fetched improperly.

13.7 PO'RT CHARACTERISTICS'
13.7 BUS Port Operations
The BUS port can operate in three different modes: as a
latched 110 port, as a bidirectional bus port, or as a program memory address output when external memory is
used. The BUS port lines are either active high, active
low, or high impedance (floating).

13.7.2 POl"t 2 Operations
The lower half of Port 2 can be used in three different
ways: as a quasi-bidirectional static port, as an 8243 expander port, and to adddress external program memory.

PROGRAM MEMORY
SPACE
,----'BFFH
MBl
8355
(2K)

EXTERNAL DATA
MEMORY SPACE
MBO 1 - - - - - 1 400H

I ~~5

- - - - - - - - 300H
8155
RESIDENT
I
I 10
RESIDENT DATA
200H r - - - - - t
MEMORY
- - - - - - - - 100H r--~--'--tl
(64)
'--_ _ _-" OOOH 1--------1

--(';Kj--

SECTION

ADDRESS

DESIGNATION

PROG.MEM
DATAMEM
8155 PORTS

OOO-BFF
100-IFF
300
301
302
303
304
305
400
401
402
403

CMD/STATUS
PORTA
PORTB
PORTC
TIMER LOW
TIMER HI
PORTA
PORTB
DORA
DDRB

8355 PORTS

Figure 13-12. Memory Map for Three-Component MCS®-48 Family

13-9

EXPANDED MCS®-48 SYSTEM"

In all cases outputs are driven low by an active device
and driven high momentarily by a low impedance device
and held high by a high impedance device to vcc.
The port may contain latched 110 data prior to its use in
another mode without affecting operation of either. If
lower Port 2 (P20-3) is used to output address for an
external program memory fetch, the 110 information pre-

viously latched will be automatically removed temporarily
while address is present, then retored when the fetch is
complete. However, if lower Port 2 is used to communicate with an 8243, previously latched 110 information
will be removed and not restored. After an input from the
8243, P20-3 will be left in the input mode (floating). After
an output to the 8243, P20-3 will contain the value written,
ANDed, or ORed to the 8243 port.

I/O

8749H
8049AH
8048AH
8748H
8035AHL
8039AHL

,.....-_ _ _- - , ,.....-_ _ _- - , , - -_ _ _ _-.-J

I/O

CJ
CJ

Figure 13-13. MCS®-48 Expansion Capability

13-10

MCS®,48 Instruction Set

CHAPTER 14
MCS®-48 INSTRUCTION SET
14.0 INTRODUCTION

14.0.1 Data Transfers

The MCS$-48 instruction set is extensive for a machine
of its size and has been tailored to be straightforward and
very efficient in its use of program memory. All instructions are either one or two bytes in length and over 80%
are only one byte long. Also, all 'instructions execute in
either one or two cycles and over 50% of all instructions
execute in a single cycle. Double cycle instructions include all immediate instructions, and all 1/0 instructions.

As can be seen in Figure 14.1, the 8-bit accumulator is
the central point for all data transfers within the 8048.
Data can be transferred between the 8 registers of each
working register bank and the accumulator directly, i.e.,
the source or destination register is specified by the instruction. The remaining locations of the internal RAM
array are referred to as Data Memory and are addressed
.indirectly via an address stored in either RO or R I of the
active register bank. RO and R 1 are also used to indirecly
address external data memory when it is present. Transfers
to and from internal RAM require one cycle, while transfers to external RAM require two. Constants stored in
Program Memory can be loaded directly to the accumulator and to the 8 working registers. Data can also be
transferred directly between the accumulator and the on-

The MCS-48 microcomputers have been designed to handle arithmetic operations efficiently in both binary and
BCD as well as handle the single-bit operations required
in control applications. Special instructions have also been
included to simplify loop counters, table look-up routines,
and N-way branch routines.

I~---------l

PROGRAM
MEMORY

(~DATA)

ADD
MOV
. MOVP
MOVP3
ANL
DRL
XRL

DATA
MEtMORY

MOV
WORKING REG

MOV
ADD
ANL
ORL
XRL
XCH

EXPANDER /lIL---,-:~--'-...I'\ r-'.....---------""------'''-,/I::-::-='7.:-:'.J....J''' EXTERNAL
MEMORY
\.rr-'-"-......,-,,,
,F=:.c.,.-,/ AND
PERIPHERALS

~~ PORTS

L----7'<"---""7<:----:--~----'

8749H
8048AH
8049AH
8748H
8035AHL'

.!!L ____

Figure 14·1. Data Transfer Instructions

14·1

I 'NO PROGRAM

8039AH~J

MEMORY

MCS.®·4~

II\ISTflUCTION SET
;',

board timer counter.or the accumulator and the Program
Status word (pSW). Writing to the PSW alters machine
status accordingly and provides a means of restoring status
after an interrupt or of altering· the stack pointer if
necessary.

14.0.2 Accumulator Ope.rations
Immediate data, data memory, or the working registers
can"be added with or without carry to the accumulator.
These sources can also be ANDed, ORed, or Exclusive
ORed to the accumulator. Data may be moved to or from
the accumulator and working registers or data memory.
The two values can also be exchanged in a single
operation.

14.0.4 Flags
There are four user-accessible flags in the 8048AH: Carry,
Auxiliary Carry, FO and PI. Carry indicates overflow of
the accumulator, and Auxiliary Carry is used to indiate
overflow between BCt> digits and is used during decimaladjust operation. Both Carry and Auxiliary Carry are accessible as part of the program status word and are stored
on the stack during subroutines. FO and F1 are undedicated
general-purpose flags to be used as the programmer desires. Both flags can be cleared or complemented and
tested by conditional jump instructions. FO is also accessible via the Program Status word and is stored on the
stack with the carry flags.

14.0.5 Branch Instructions
In addition, the lower 4 bits of the accumulator can be
exchanged with the lower 4-bits of any of the internal
RAM locations. This instruction, along with an instruction
which swaps the upper and lower 4-bit halves of the accumulator, provides for easy handling of 4-bit quantities,
including BCD numbers. To facilitate BCD arithmetic, a
Decimal Adjust instruction is included. This instruction
is used to correct the result of the binary addition ofJwo
2-digit BCD numbers. Performing a decimal adjust on the
result in the accumulator produces the required BCD
result.
Finally, the accumulator can be incremented, decremented, cleared, or complemented and can be rotated left
or right 1 bit at a time with or without carty.
Although there is no subtract instruction in the 8048AH,
this operation can be easily implemented with three singlebyte single-cycle instructions.
A value may be subtracted from the accumulator with the
result in the accumulator by:

The unconditional jump instruction is two bytes and allows
jumps anywhere in the first 2K words of program memory.
Jumps to the second 2K of memory (4K words are directly
addressable) are made first by executing a select memory
bank instruction, then executing the jump instruction. The
. 2K boundary can only be crossed via a jump or subroutine
call instruction, i.e . , the bank switch does not occur until
ajump is executed. Once a memory bank has been selected
all subsequent jumps will be to the selected bank until
another select memory bank instruction is executed. A
subroutine in the opposite bank can be accessed by a select
memory bank instruction followed by a call instruction.
Upon completion of the subroutine, execution will automatically return to the original bank; however, unless the
Original bank is reselected, the next jump instruction encountered will again transfer execution to the opposite
bank.
.
Conditional jumps can test the followihg inputs and machine status:
• TO Input Pin

• Complementing the accumulator

• T1 Input Pin

• Adding the value to the .~ccumulator

• INT Input Pin
• Accumulator Zero

• Complementing the accumulator

• Any bit of Accumulator

14.0.3 Register Operations
The working registers can be accessed via the accumulator
as explained above, or can be loaded immediate with
constants from program memory. In addition, they can be
incremented or decremented or used as loop counters using
the decrement and jump, if not zero instruction, as ex.
plained under branch instructions.
All Data Memory including working registers can be ascessed with indirect instructions via RO and R 1 and can
be incremented.

• Carry Flag
• FO Flag
• FI Flag
Conditional jumps allow a branch to any address within
the current page (256 words) of execution. The conditions
tested are the instantaneous values at the time the conditional jump is executed. For instance, the jump on accumulator zero instruction tests the accumulator itself, not
an intermediate zero flag.

14-2

MCS®·48 INSTRUCTION SeT

The decrement register and jump if not zero instruction
combines a decrement and a branch instruction to create
an instruction very useful in implementing a loop counter.
This instruction can designate anyone of the 8 working
registers as a counter and can effect a branch to any address
within the current page of execution.

The working register bank switch instructions allow the
programmer to immediately subsfitute a second 8-register
working register bank for the one in use. This effectively
provides 16 working registers or it can be used as a means
of quickly saving the contents of the registers in response
to an interrupt. The user has the option to switch or not
to switch banks on interrupt. However, if the banks are
switched, the original bank will be automatically restored
upon execution of a return and restore status instruction
at the end of the interrupt service routine.

A single-byte indirect jump instruction allows the program
to be vectored to anyone of several different locations
based on the contents of the accumulator. The contents
of the accumulator points to a location in program memory
which contains the jump address. The 8-bit jump address
refers to the current page of execution. This instruction
could be used, for instance, to vector to anyone of several
routines based on an ASCII character which has been
loaded in the accumulator. In this way ASCII key inputs
can be used to initiate various routines.

A special instruction enables an internal clock, which is
the XTAL frequency divided by three to be output on pin
TO. This clock can be used as a general-purpose clock in
the user's system. This instruction should be used only to
initialize the system since the clock output can be disabled
only by application of system reset.

14.0.6 Subroutines

14.0.9. Input/Output Instructions

Subroutines are entered by executing a call instruction.
Calls can be made like unconditional jumps to any address
in a 2K word bank, and jumps across the 2K boundary
are executed in the same manner. Two separate return
instructions determine whether or not status (upper 4-bits
of PSW) is restored upon return from the subroutine.

Ports 1 and 2 are 8-bit static I/O ports which can be loaded
to and from the accumulator. Outputs are statically latched
but inputs are not latched and must be read while inputs
are present. In addition, immediate data from program
memory can be ANDed or ORed directly to Port I and
Port 2 with the result remaining on the port. This allows
"masks" stored in program memory to selectively set or
reset individual bits of the I/O ports. Ports 1 and 2 are
configured to allow input on a given pin by first writing
a "I" out to the pin.

The return and restore status instruction also signals the
end of an interrupt service routine if one has been in
progress.

14.0.7 Timer Instructions
The 8-bit on board timer/counter can be loaded or read
via the accumulator while the counter is stopped or while
counting. The counter can be started as a timer with an
internal clock source or an event counter or timer with an
external clock applied to the Tl input pin. The instruction
executed determines which clock source is used. A single
instruction stops the counter whether it is operating with
an internal or an external clock source. In addition, two
instructions allow the timer interrupt to be enabled or
disabled.

14.0.8 Control Instructions
Two instructions allow the external interrupt source to be
enabled or disabled. Interrupts are initially disabled and
are automatically disabled while an interrupt service routines is in progress and re-enabled afterward.
There are four memory bank select instructions, two to
designate the active working register bank and two to
control program memory banks. The operation of the program memory bank switch is explained in section 13.1.2.

An 8-bit port called BUS can also be accessed via the
accumulator and can. have statically latched outputs as
well. It too can have immediate data ANDed or ORed
directly to its outputs, however, unlike ports 1 and 2, all
eight lines of BUS must be treated as either input or output
at anyone time. In addition to being a static port, BUS
can be used as a true synchronous bi-directional port using
the Move External instructions used to access external
data memory. When these instructions are executed, a
corresponding READ or WRITE pulse is generated and
data is valid only at that time. When data is not being
transferred, BUS is in a high impedance state. Note that
the OUTL, ANL, and the ORL instructions for the BUS
are for use with internal program memory only.
The basic three on-board I/O ports can be expanded via
a 4-bit expander bus using half of port 2. I/O expander
devices on this bus consist of four 4-bit ports which are
addressed as ports 4 through 7. These ports have their
own AND and OR instructions like the on-board ports as
well as move instructions to transfer data in or out. The
expander AND and OR instructions, however, combine
the contents of accumulator with the selected port rather
than immediate data as is done with the on-board ports.

14-3

MCS®-48 INSTRUCTION SET

I/O devices can also be added externally using the BUS
port as the expansion bus. In this case the 1/0 ports become
"memory mapped" , i.e., they are addrl:ssed in the same
way as external data memory and exist in the external
data memory address space addressed by pointer register
RO or Rl.

The alphabetical listing includes the following
information.
• Mnemonic
• Machine Code
• Verbal Description
• Symbolic Description
• Assembly Language Example
The machine code is represented with the most significant
bit (7) to the left and two byte instructions are represented
with the first byte on the left. The assembly language
examples are formulated as follows:

14.1 INSTRUCTION SET DESCRIPTION
The following pages describe the MCS®-48 instruction set
in- detail. The instruction set is first summarized with instructions grouped functionally. This summary page is
followed by a detailed description listed alphabetically by
mnemonic opcode.

Arbitrary
Label: Mnemonic, Operand;
Descriptive Comment

14-4.

MCS@·48INSTRUCTION SET
S04SAH/S74SH/S049AH/S050AH/8749H
Instruction Set Summary
Mnemonic

Oescrtptlon

Mnemonic

Bytes Cycle

XRLA,@R
XRL, A, # data
INCA
DECA
CLRA
CPLA
DAA
SWAP A
RLA
RLCA
RRA
RRCA

INCR
INC@R
DECR

Add register to A
Add data memory to A
Add immediate to A
Add register with carry
Add data memory
with carry
Add immediate
with carry
And register to A
And data memory to A
And immediate to A
Or register to A
Or data memory to A
Or immediate to A
Exclusive Or register
toA
Exclusive or data
memory to A
Exclusive or
immediate to A
Increment A
Decrement A
Clear A
Complement A
Decimal adjust A
Swap nibbles of A
Rotate A left
Rotate A left
through carry
Rotate A right
Rotate A right
through carry

1
1
2
1
1

1
1
2
1
1
2
1

1
1
1
1
1
1
1
1

1
1

Input port to A
Output A to port
And immediate to port
Or immediate to port
Input BUS to A
Output A to BUS
And immediate to BUS

1
1
2
2
1
1
2

2
2
2
2
2
2
2

Or immediate to BUS

Input Expander port
toA
Output A to Expander
port
And A to Expander port
Or A to Expander port

MOVA,#data
MOVR,A
MOV@R,A

MOVD P, A

ANLD P,A
ORLD P, A

MOV R, # data

1
1

2
2

MOV@R,
# data
MOVA,PSW
MOVPSW,A

Increment register
Increment data memory
Decrement register

1
1
1

Jump unconditional
Jump indirect
Decrement register
and jump
Jump on carry =1
Jump on carry =0
Jump on A Zero
Jump on A not Zero
Jump on TO =1
Jump on TO =0
Jump on T1 =1
Jump on T1 =0
Jump on FO =1
Jump on F1 =1
Jump on timer flag =1
Jump on INT =0
Jump on Accumulator
Bit

2
1
2

2
2
2

2
2
2
2
2
2
2
2
2
2
2
2
2

Jump to subroutine
Return
Return and restore
status

2
1
1

2
2
2

Clear Carry
Complement Carry
Clear Flag 0
Complement Flag 0
Clear Flag 1
Complement Flag 1

1
1
1
1
1
1

Move register to A
Move data memory
toA
Move immediate to A
Move A to register
Move A to data
memory
Move immediate
to register
Move immediate to
data memory
Move PSW to A
MoveAtoPSW

1
1

2
1
1

1
1

Branch

JMP addr
JMPP@A
DJNZ R, addr
JC addr
JNC addr
JZ addr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JFO addr
JF1 addr
JTF addr
JNI addr
JBb addr
Subroutine

CALL addr
RET
RETR
Flags

CLRC
CPLC
CLR FO
CPL FO
CLR F1
CPL F1

Input/Output

INA,P
OUTL P,A
ANL P, # data
ORL P, # data
'INS A, BUS
'OUTL BUS, A
'ANL BUS,
# data
'ORL BUS,
# data
MOVDA, P

Bytes Cycles

Registers

Accumulator

ADD A, R
ADDA,@R
ADD A, # data
AD DC A, R
ADDCA,
@R
ADDCA,
# data
ANLA, R
ANLA,@R
ANLA, # data
ORLA, R
ORLA@R
ORL A, # data
XRL A, R

Description

Data Moves

MOVA, R
MOVA,@R

Mnemonics copyright Intel Corporation 1983.
'For use with internal memory only.

14-5

MCS®·481NSTRUCTION SET
8048AH/8748H/8049AH/8050AH/8749H

Instruction Set Summary (Con't)
Mnemonic

Description

Data Moves
(Confd)
XCH A, R

DIS TCNTI

Mnemonic
Control
EN I

Exchange A and
register
XCH A,@R
Exchange A and
data memory
XCHDA,@R Exchange nibble of A
and register
MOVXA,@R Move external data
memory to A
MOVX@R,A Move A to external
data memory
MOVPA,@A Move to A from
current page
MOVP3A,@A Move to A from Page 3

Timer/Counter
MOVA. T
MOVT.A
STRTT
STRTCNT
STOP TCNT
EN TCNTI

Bytes Cycle

Read Timer/Counter
Load Timer/Counter
Start Timer
Start Counter
Stop Timer/Counter
Enable Timer/Counter
Interrupt
Disable Timer/Counter
Interrupt

1
1
1
1
1
1

DISI
SEL RBO
SEL RB1
SEL MBO
SEL MB1
ENTOCLK
NOP

Description

Bytes Cycle

Enable external
Interrupt
Disable external
Interrupt
Select register bank 0
Select register bank 1
Select memory bank 0
Select memory bank 1
Enable clock output
onTO

1
1
1
1
1

No Operation

Mnemonics copyright Intel Corporation 1983.

14-6

MCS®-48 INSTRUCTION SET
Symbols and Abbreviations Used

A
AC
addr
Bb
BS
BUS
C
ClK
CNT
CRR
D
data
DBF
FO, F1
I
P
PC
Pp
PSW
Ri
Rr
SP
T
TF
TO, T1
X
#

$
(X)
((X»

,Accumulator
Auxiliary Carry
12-Bit Program Memory Address
Bit Designator (b = 0-7)
Bank Switch
BUS Port
Carry
Clock
Event Counter
Conversion Result Register
Mnemonic for 4-Bit Digit (Nibble)
8-Bit Number or Expression
Memory Bank Flip-Flop
Flag 0, Flag 1
Interrupt
Mnemonic for "in-page" Operation
Program Counter
Port Designator (p = 1, 2 or 4-7)
Program Status Word
Data memory Pointer (i = 0, or 1)
Register Designator (r = 0-7)
Stack Pointer
Timer
Timer Flag
Test 0, Test 1
Mnemonic for External RAM
Immediate Data Prefix
Indirect Address Prefix
Current Value of Program Counter
Contents of X
Contents of location Addressed by X
Is Replaced by

Mnemonics copyright Intel Corporation 1983.

14-7

MCS®-48 INSTRUCTION SET

ADD A,R r

Add Register Contents to Accumulator

Encoding:

I0 1 1 0 I 1 r

68H-6FH

Description: The contents of register 'r' are added to the accumulator. Carry is
affected.
Operation: (A) -

r = 0-7

(A) + (Rr)

Example: ADDREG: ADD A,R6

;ADD REG 6 CONTENTS
;TOACC

ADD A,@R1 Add Data Memory Contents to Accumulator
Encoding;

I0 1 1 0 I 0 0 0 i I

60H-61H

Description: The contents of the resident data memory location addressed by register 'i' bits
O-S** are added to the accumulator. Carry is affected.
i = 0-1
;MOVE '1 F' HEX TO REG 0
;ADD VALUE OF LOCATION
;31 TO ACC

Operation: (A) - (A) + ((Ri))
Example: ADDM: MOV RO, #01 FH
ADD A, @RO

ADD A,#data
Encoding:

Add Immediate Data to Accumulator

I0 0 0 0 I 0 0 1Il I d7

d6 dS d4 d3 d2 d1 dO

03H

Description: This is a 2-cycle instruction. The specified data is added to the accumulator.
Carry is affected.
Operation: (A) -

(A) + data

Example: ADDID: ADD A,#ADDER:

ADDC A,R r
Encoding:

;ADD VALUE OF SYMBOL
;ADDER' TO ACC

Add Carry and Register Contents to Accumulator

I0 1 1 1 I 1 r

r r

78H-7FH

Description: The content of the carry bit is added to accumulator location 0 and the carry
bit cleared. The contents of register 'r' are then ,added to the accumulator.
Carry is affected.
Operation: (A) -

r = 0-7

(A) + (Rr) + (C)

Example: ADDRGC: AD DC A,R4

;ADD CARRY AND REG 4
;CONTENTS TO ACC

•• 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH

14-8

MCS®-48 INSTRUCTION SET

ADDC A,@Ri

Add Carry and Data Memory Contents to Accumulator

Encoding: 1a 1 1 1 1 a

a Oil

70H-71H

Description: The content of the carry bit is added to accumulator location 0 and the carry bit
cleared. Then the contents of the resident data memory location addressed by
register 'j' bits 0-5** are added to the accumulator: Carry is affected.
Operation: (A) -

(A) + «Ai» + (C)

i = 0-1

Example: ADDMC: MOV A1,#40
ADDCA,@A1

ADDC A,@data
Encoding: 10

;MOVE '40' DEC TO AEG 1
;ADD CARAY AND LOCATION 40
;CONTENTS TO ACC

Add Carry and Immediate Data to Accumulator

a a 1 1a a 1

d7 d6 d5 d4

d3 d2 d1 dO

13H'

Description: This is a 2-cycle instruction. The content of the carry bit is added to
accumulator location a and the carry bit cleared. Then the specified data is
added to the accumulator. Carry is affected.
Operation: (A) -

(A) + data + (C)

Example: AD DC A,#225

ANL A,R r

;ADD CAAAY AND '225' DEC
;TOACC

Logical AND Accumulator with Register Mask

Encoding: 10 1

a 1 11

r r r

58H-5FH

Description: Data in the accumulator is logically ANDed with the mask contained in
working register 'r'.
Operation: (A) -

r = 0-7

(A) AND (Ar)

Example: ANDAEG: ANL A,A3

ANL A,@Ri

;'AND' ACC CONTENTS WITH MASK
;IN REG 3

Logical AND Accumulator with memory Mask

Encoding: 10 1

a 1 10 a Oil

50H-51H

Description: Data in the accumulator is logically ANDed with the mask contained in the
data memory location referenced by register 'i' bits 0-5**.
Operation: (A) -

(A) AND«Ai»

i = 0-1
;MOVE '3F' HEX TO AEG a
;'AND' ACC CONTENTS WITH
;MASK IN LOCATION 63

Example: ANDDM: MOV AO,#03FH
ANL A, @AO
** 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH

14-9

MCS@-48INSTRUCTION SET

ANL

~,#data

Logical AND Accumulator with Immediate Mask

Encoding: 10 1 0 1

I0 0 1 1 1

53H

Description: This is a 2-cycle instruction. Data in the accumulator is logically ANDed
with an immediately-specified mask.
Operation: (A) -

(A) AND data
;'AND' ACC CONTENTS
;WITH MASK 10101111
;'AND' ACC CONTENTS
;WITH VALUE OF EXP
;'3 + Xy/y'

Examples: ANDID: ANL A,#OAFH
ANL A,#3 + X/Y

ANL BUS,#data*

Logical AND BUS with Immediate Mask
98H

Encoding: 11 0 0 1 11 0 0 0 1

Description: This is a 2-cycle instruction. Data on the BUS port is logically ANDed
with an immediately-specified mask. This instruction assumes prior
specification of an 'OUTL BUS, A' instruction.
Operation: (BUS) -

(BUS) AND data

Example: ANDBUS: ANL BUS,#MASK

ANL Pp,#data

;'AND' BUS CONTENTS
;WITH MASK EQUAL VALUE
;OF SYMBOL 'MASK'

Logical AND Port 1-2 with Immediate Mask

Encoding: 11 001 11 0 P pi

Id7 de d5 d41 d3 d2 d1

dol

99H-9AH

Description: This is a 2-cycle instruction. Data on port 'p' is logically ANDed with an
immediately-specified mask.
Operation: (Pp) -

p = 1-2

(Pp) AND DATA

;'AND' PORT 2 CONTENTS
;WITH MASK 'FO' HEX
;(CLEAR P20-23)

Example: ANDP2: ANL P2,#OFOH
• For use with internal program memory ONLY.

14-10

MCS®-48 INSTRUCTION SET

ANLD Pp,A

Logical AND Port 4-7 with Accumulator Mask

Encoding: 11 0 0 1 11 1 P P 1

9CH-9FH

Description: This is a 2-cycle instruction. Data on port 'p' is logically ANDed with the
digit mask contained in accumulator bits 0-3.
Operation: (Pp) - (Pp) AND (AO-3)
P = 4-7
Note: The mapping of port 'p' to opcode bits 0-1 is as follows:
1 0 Port
00
01
10
11

4
5
6
7

Example: ANDP4: ANLD P4,A

CALL address

;'AND' PORT 4 CONTENTS
;WITH ACC BITS 0-3

Subroutine Call

Encoding: , a10 a9 as 1 0 1 0 0

Page Hex Op Code

o
1

2
3
4

5
6

14
34
54
74
94
B4
D4
F4

Description: This is a 2-cycle instruction. The program counter and PSW bit!! 4-7 are
saved in the stack. The stack pointer (PSW bits 0-2) is updated. Program
control is then passed to the location specified by 'address'. PC bit 11 is
determined by the most recent SEL MB instruction.
A CALL cannot begin in locati'ons 2046-2047 or 4094-4095. Execution
continues at the instruction following the CALL upon return from the
subroutine.
Operation: ((SP)) - (PC), (PSW4-7)
(SP) - (SP) + 1
(PCS- 10) - (addrS_10)
( PCO- 7) - (addrO_7)
(PC11) - DBF

14-11

MCS@-48INSTRUE::TION SET

Example: Add three groups of two numbers. Put subtotals in locations 50, 51 and
total in location 52.
;MOVE '50' DEC TO ADDRESS
;REGO
;MOV~ CONTENTS OF REG 1
. ;TOACC
;ADD REG 2 TO ACC
;CALL SUBROUTINE 'SUBTOT'
;ADD REG 3 TO ACC
;ADD REG 4 TO ACC
;CALL SUBROUTINE 'SUBTOT'
;ADD REG 5 TO ACC
;ADD REG 6 TO ACC
;CALL SUBROUTINE 'SUBTOT'
;MOVE CONTENTS OF ACC TO
;LOCATION ADDRESSED BY
;REGO
;INCREMENT REG 0 .
;RETURN TO MAIN PROGRAM

MOV RO,#50
BEGADD: MOV A,R1
ADD A,R2
CALL SUBTOT .
AD DC A R3
ADDC A,R4
CALL SUBTOT
ADDC A,R5
ADDCA,R6
CALL SUBTOT
SUBTOT: MOV @RO,A

INC RO
RET
CLR A

Clear Accumulator

Encoding: 10 0 1 0

I0 1

27H

Description: The contents of the accumulator are cleared to zero.
Operation: A CLR C

Clear Carry Bit

Encoding: 11 0 0 1 10 1

97H

Description: During normal programe.xecution, the carry bit can be set to one by the
ADD,ADDC, RLC, CPL C, RRC, and DAA insructions. This instruction
resets the carry bit to zero.
Operation: C CLR F1

Clear Flag 1

Encoding: 11 0 1 0

I0 1 0 1 1

A5H

Description: Flag 1 is cleared to zero.
Operation: (F1) -

14-12

MCS®-48 INSTRUCTION SET

CLR FO

Clear Flag 0

Encoding: 11 0 0 0 1 0 1 0 1

8SH

Description: Flag 0 is cleared to zero.
Operation: (FO) CPL A

Complement Accumulator

Encoding: 10 0 1 1 10 1 1 1 1

37H

Description: The contents of the accumulator are complemented. This is strictly a one's
complement. Each one is changed to zero and vice-versa.
Operation: (A) -

NOT (A)

Example: Assume accumulator contains 01101010.
CPLA: CPL A
;ACC CONTENTS ARE COMPLE;MENTED TO 10010101
CPL C

Complement Carry Bit

Encoding: 11 0 1 0 1 0 1 1 1

A7H

Description: The setting of the carry bit is complemented; one is changed to zero, and
zero is changed to one.
Operation: (C) -

NOT (C)

Example: Set C to one; current setting is unknown.
CT01: CLR C
;C IS CLEARED TO ZERO
CPL C
;C IS SET TO ONE
CPL FO

Complement Flag 0

Encoding: 11 0 0 1 1 0 1 0 11

'95H

Description: The setting of flag 0 is complemented; one is changed to zero, and zero is
changed to one.
Operation: FO CPL F1

NOT (FO)

Complement Flag 1

Encoding: 11 0 1 1 10 1 0 1/

BSH

D!ilscrlptlon: The setting of flag 1 is complemented; one is changed to zero, and zero is
changed to one.
Operation: (F1) -

NOT (F1)

14-13

MCS®·48 INSTRUCTION SET

DA A

Decimal Adjust Accumulator

Encoding:

I0 1 0 1 I0 1 1 11

57H

Description: The S-bit accumulator value is adjusted to form two 4-bit Binary Coded
Decimal (BCD) digits following the binary addition of BCD numbers.
The carry bit C is affected. If the contents of bits 0-3 are greater than nine,
or if AC is one, the accumulator is incremented by six.

The four high-order bits are then checked. If bits 4-7 exceed nine, or if
C is one, these bits are increased by six. If an overflow occurs, C is set
to one.
Example: Assume accumulator contains 10011011.
DA A
;ACC Adjusted to 00000001
;WITH C SET
C AC 7
43
0
0010011011
ADD SIX TO BITS 0-7
00000110
1 0 1 0 0.0 0 1
ADD SIX TO BITS 4-7
1 1 0
OVERFLOW TO C
000 000 0 0

DEC A

Decrement Accumulator

Encoding:

I0 0 0 0 10 1 1 1 I

07H

Description: The contents of the accumulator are decremented by one. The carry flag
is not affected.
Operation: (A)

(A) -1

Example: Decrement contents of external data memory location 63.
MOV RO,#3FH
;MOVE '3F' HEX TO REG 0
MOVX A, @RO
;MOVE CONTENTS OF
;LOCATION 63 TO ACC
DEC A
;DECREMENT ACC
MOVX @RO,A
;MOVE CONTENTS OF ACC TO
;LOCATION 63 IN EXPANDED
;MEMORY
DEC Rr

Decrement Regh}ter

Encoding: 11 1 0 0

I1 r

r r 1

CSH-CFH

Description: The contents of working register 'r' are decremented by one.
Operation: (Rr)

r = 0-7

(Rr) -1

Example: DEeR1: DEC R1

;DECREMENT CONTENTS OF REG 1

14-14

MCS®-48 INSTRUCTION SET

DIS I

External Interrupt

Encoding:

I 0 0 0 1 I0 1 0 1 I

15H

Description: External interrupts are disabled. A low signal on the
no effect.
DIS TCNTI

int~rrupt

input pin has

Disable Timer/Counter Interrupt

Encoding: 10 0 1 1 1 0 1 0 1

35H

Description: Timer/counter interrupts are disabled. Any pending timer interrupt request
is cleared. The interrupt sequence is not initiated by an overflow, but the
timer flag is set and time accumulation continues.
DJNZ Rr • address

Decrement Register and Test

Encoding: 11 1 1 0 11 r r r 1

1a7 a6 a5 a4 1a3 a2 a1 aO 1

E8H-EFH

Description: This is a 2-cycle instruction. Register 'r' is decremented, thEm tested for
zero. If the register contains all zeros, program control falls through to the
next instruction. If the register contents are not zero, control jumps to the
specified 'address'.
The address in this case must evaluate to 8-bits, that is, the jump must be
to a location within the current 256-location page.

Example: (Rr) - (Rr) -1
r =0-7
If Rr not 0
(PCO-7) - addr
Note: A 12-bit address specification does not cause an error if the
DJNZ instruction and the jump target are on the same page. If the DJNZ
instruction begins in location 255 of a page, it must jump to a target
address on the following page.
Example: Incre'ment values in data memory locations 50-54.
MOV RO,#50
;MOVE '50' DEC TO ADDRESS
;REGO
MOV R3,#5
;MOVE '5' DEC TO COUNTER
;REG3
INCRT: INC @RO
;INCREMENT CONTENTS OF
;LOCATION ADDRESSED BY
;REGO
INC RO
;INCREMENT ADDRESS IN REG 0
DJNZ R3, INCRT
;DECREMENT REG 3 - JUMP TO
;'INCRT' IF REG 3 NONZERO
NEXT ;'NEXT' ROUTINE EXECUTED
;IF R3 IS ZERO

14-15

MCS®~48 INSTRUCTION SET

EN I

Enable External Interrupt

Encoding: 10 0 0 0 10 1 0 1 1

05H

Description: External interrupts are enabled. A low signal on the interrupt input pin
initiates the interrupt sequence.
EN TCNTI

Enable Timer/Counter Interrupt

Encoding: 10 0 1 0 0 1 0 1

25H

Description: Timer/counter interrupts are enabled. An overflow of the timer/cc;>unter
initiates the interrupt sequence.
ENTO ClK

Enable Clock Output

Encoding: 10 1 1 1 0 1 0 1.

75H

Description: The test 0 pin is enabled to act as the clock output. This function is
disabled by a system reset.
Example: EMTSTO: ENTO ClK
IN A,Pp

;ENABlE TO AS CLOCK OUTPUT

Input Port or Data to Accumulator

Encoding: 10 0 0 0 11 0 P P 1

09H-OAH

Description: This is a 2-cycle instruction. Data present on port 'p' is
transferred (read) to the accumulator.
p = 1-2
;INPUT PORT 1 CONTENTS TO ACC
;MOVE ACC CONTENTS TO REG 6
;INPUT PORT 2 CONTENTS TO ACC
;MOVE ACC CONTENTS TO REG 7

Operation: (A) - (Pp)
INP12: IN A,P1
MOV R6,A
INA,P2
MOV R7,A
INC A Increment Accumulator
Encoding:

I0 0

0 1 1 0 1 1 1\

17H

Description: The contents of the accumulator are incremented by one. Carry is not
affected.
Operation: (A) -

(A) +1

14·16

MCS®-48 INSTRUCTION SET

Example: Increment contents of location 100 in external data memory.
INCA: MOV RO,#100
;MOVE '100' DEC TO ADDRESS REG 0
MOVX A,@RO
;MOVE CONTENTS OF LOCATION
;100 TO ACC
INC A
;INCREMENT A
MOVX @RO,A
;MOVE ACC CONTENTS TO
;LOCATION 101
INC Rr

Increment Register

Encoding: 10 0 0 1 11 r r r

18H-1FH

Description: The contents of working register 'r' are incremented by one.
Operation: (Rr) -

(Rr) + 1

r = 0-7

Example: INCRO: INC RO

;INCREMENT CONTENTS OF REG 0

INC @R1 Increment Data Memory Location
Encoding:

I0 0 0 1 I 0 0 0 i I

10H-11 H

Description: The contents of the resident data memory location addressed by register 'i' bits
0-5** are incremented by one.
.
Operation: ((Ri)) -

i = 0-1

({Ri)) + 1

;MOVE ONES TO REG 1
;INCREMENT LOCATION 63

Example: INCDM: MOV R1,#03FH
INC @R1

INS A,BUS* Strobed Input of BUS Data to' Accumulator
Encoding:

I0 0 0 0 I 1 0 0 0 I

08H

Description: This is a 2-cycle instruction. Data present on the BUS port is transferred
. (read) to the accumulato~ when the RD pulse is dropped. (Refer to section
on programming memory expansion for details.)
Operation: (A) -

(BUS)

Example: INPBUS: INS A,BUS

;INPUT BUS CONTENTS TO ACC

* For use with internal program memory ONLY.
** 0-5 in B048AH/8748H
.

0-6 in 8049AH/8749H
0-7 in 8050AH

14-17

MCS®~48INSTRUCTION

seT

JBb address ' Jump If Accumulator Bit Is Set

Accumulator Bit

Hex Op Code

12
32
52
72

1
2

3
4
5
6

92
B2

Description: This is a 2-cycle instruction. Control passes to the specified address if
accumulator bit 'b' is set to one.

b = 0-7
If Bb = 1
If Bb = 0
;JUMP TO 'NEXT' ROUTINE
;IF ACC BIT 4 = 1

Operation:
(PCO-7) - addr
(PC) = (PC) + 2
Example: JB4IS1: JB4 NEXT

JC address

Jump If Carry Is Set

Encoding: 11 1 1 1 1 0 1 1 0

1a7 a6 a5 a4

Ia3 a2 a1 aO I

F6H

Description: This is a 2-cycle instruction. Control passes to the specified' address if the
carry bit is set to one.
If C = 1
IfC=O

Operation: (PCO-7) - addr
(PC) = (PC) + 2

Example: JC1: JC OVFLOW

;JUMP TO 'OVFLOW' ROUTINE
;IF C == 1

Description: This is a 2-cycle instruction. Control passes to the specified address if
flag 0 is set to one.
Operation: (PCO-7) - addr
(PC) =(PC) + 2

If FO = 1
If FO = 0
;JUMP TO 'TOTAL' ROUTINE IF FO = 1

Example: JFOIS1: JFO TOTAL

14-18

MCS®·48 INSTRUCTION SET

JF1 address

Jump If Flag 1 Is Set

Encoding: 10 1, 1 1 10 1 1 0 1

1a7 a6 as a41 a3 a2 a1 aol

76H

Description: This is a 2-cycle instruction. Control passes to the specified address if
flag 1 is set to one.
Operation: (PCO-7):O- addr
(PC) =(PC + 2)

If F1 = 1
If F1 = 0

;JUMP TO 'FILBUF'
;RbuTINE IF F1= 1

Example: JF1IS1: JF1 FILBUF

JMP address

Direct Jump within 2K Block

Page Hex Op Code
0
1
2
3
4
[;

6
7

04
24
44
64
84
A4
C4
E4

Description: This is a 2-cycle instruction. Bits 0-10 of the program counter are replaced
with the directly-specified address. The setting of PC bit 11 is
determined by the most recent SELECT MB instruction.
Operation: (PC8-10) - addr 8-10
(PCO-7) - addr 0-7
(PC11) - DBF
;JUMP TO SUBROUTINE 'SUBTOT
;JUMP TO INSTRUCTION SIX
;LOCATIONS BEFORE CURRENT
;LOCATION
;JUMP TO ADDRESS '2F' HEX

Examplel JMP SUBTOT
JMP $-6

JMP 2FH
JMPP @A

Indirect Jump within Page

Encoding: 11 0 1 1 0 0 1 1

B3H

Description: This is a 2-cycle insruction. The contents of the program memory location
pointed to by the accumulator are substituted for the 'page' portion of the
program counter (PC bits 0-7).

14.19

MCS@I·4$ INSTRUCTION SET'

Operation: (PCO-7) -

((A))

Example: Assume accumulator contains OFH.
JMPPAG: JMPP @A
;JUMP TO ADDRESS STORED IN
;LOCATION 151N CURRENT PAGE
JNC address

Jump If Carry Is Not Set

Encoding: 11 1 1 0 10 1 1 0 1
1a7 a6 a5 a4 1a3 a2 a1 aO
ESH
Description: This is a 2-cycle instruction. Control passes to the specified address, if
the carry bit is npt set, thatis, equals zero.
If C = 0
If C = 1

Operation: (PCO-7) - addr
(PC) = (PC) + 2

;JUMP TO 'NOVFLO' ROUTINE.
;IF C= 0

Example: JCO: JNC NOVFLO

JNI address Jump If Interrupt Input Is Low
Encoding: 11 0 0 0 10 1 1 0 1 1a7 as a5 a41 a3 a2 a1 aO 1
B6H
Description: This is a 2-cycle instruction. Control passes to the specified address if the
interrupt input signal is low (= 0), that is, an external interrupt has been
signaled. (This signal initiates an interrupt service sequence if the external
interrupt is enabled.)
Operation: (PCO-7) - addr
(PC) = (PC) + 2
Example: LOC 3: JNI EXTINT

If I = 0
If I = 1
;JUMP TO 'EXTINT' ROUTINE
;IF I = 0

JNTO address Jump If Test 0 is Low
Encoding: 10010101101

ja7a6asa41a3a2a1 aol

2SH

Description: This is 2-cycle instruction. Control passes to the specified address, if the
test 0 signal is low.
If TO = 0
If TO = 1

Operation: (PCa':"7) - addr
(PC) = (PC) + 2
Example: JTOLOW: JNTO 60

;JUMP TO LOCATION 60 DEC
;IF TO = 0'

14-20

MCS®-48

JNT1 address

INST~UCTION

SET

Jump If Test 1 Is Low

Encoding: 10 1 0 0

I0 1 1 0 I Ia7 a6 a5 a4 Ia3 a2 a1 aO I

46H

Description: This is a 2-cycle instruction. Control passes to the specified address, if
the test 1 signal is low.

If T1 = 0
If T1 = 1

Operation: (PCO-7) - addr
(PC) = (PC) + 2
JNZ Address

Jump If Accumulator Is Not Zero

Encoding: 11 0 0 1 1 0 1 1 0 1

Ia7

a6 a5 a4

Ia3

a2 a1 aO

96H

Description: This is a 2-cycle instruction. Control passes to the specified address if the
accumulator contents are nonzero at the time this instruction is executed.

IfA#O
If A = 0

Operation: (PCO-7) - addr
(PC) = (PC) + 2
Example: JACCNO: JNZ OABH

JTF address
Encoding:

;JUMP TO LOCATION 'AB' HEX
;IF ACC VALUE IS NONZERO

Jump If Timer Flag Is Set

I0 0 0 1 I0 1 1 0 I Ia7 a6 a5 a4 I a3 a2 a1 aO I

16H

Description: This is a 2-cycle instruction. Control passes to the specified address if the
timer flag is set to one, that is, the timer/counter register has overflowed.
Testing the timer flag resets it to zero. (This overflow initiates an interrupt
service sequence if the timer-overflow interrupt is enabled.)

If TF = 1
If TF = 0

Operation: (PCO-7) - addr
(PC) = (PC) + 2
Example: JTF1: JTF TIMER

JTO address
Encoding:

;JUMP TO 'TIMER' ROUTINE
;IF TF = 1

Jump If Test 0 Is High

I0 0 1 1 I0 1 1 0 I Ia7 a6 a5 a41 a3 a2 B1 aO I

36H

Description: This is a 2-cycle instruction. Control passes to the specified address if
the test 0 signal is high (= 1).

If TO = 1
If TO= 0

Operation: (PCO-7) - addr
(PC) = (PC) + 2
Example: JTOHI: JTO 53

;JUMP TO LOCATION 53 DEC
;IF TO = 1

14-21

MCS®-48INSTf'UCTION SET

JT1 address

Jump If Test 1 Is High

I0 1 0 1 I0 1 1 0 I Ia7 as as a41 a3 a2 a1

Encoding:

aO 1

SSH

Description: This is a 2-cycle instruction. Control passes to the specified address'if the
test 1 signal is high (= 1).

IfT1 = 1
If T1 = 0

Operation: (PCO-7) - addr
(PC) = (PC) + 2

;JUMP TO 'COUNT' ROUTINE
;IFT1 = 1

Example: JT1 HI: JT1 COUNT

JZ address

Jump If Accumulator Is Zero

Encoding: 11 1 0 0 1 0 1 10 1

Ia7

as as a4 1a3 a2 a1 aO 1

CSH

Description: This is a 2-cycle instruction. Control passes to the specified address if
the accumulator contains all zeros at the time this instruction is executed.

If A =0
If A =;f 1

Operation: (PC O- 7)'- addr
(PC) = (PC) + 2
Example: JACCO: JZ OA3H

MOV A,#data

;JUMP TO LOCATION 'A3' HEX
;IFACC VALUE IS ZERO

Move Immediate Data to Accumulator

Encoding: 1 0 0 1 0

I0 0

1 1

1a7 as as a4 1a3 a2 a1 aO 1

23H

Description: This is a 2-cycle instruction. The 8-bit value specified by 'data' is loaded
in the accumulator.
Operation: (A) -

data

Example: MOV A,#OA3H

MOV A,PSW

;MOVE 'A3' HEX TO ACC

Move PSW Contents to Accumulator

Encoding: 11 1 0 0 1 0 1 1 1 1

C7H

Description: The contents of the program status word are moved to the accumulator.
Operation: (A) -

(PSW)

Example: Jump to 'RB1SET' routine if PSW bank switch, bit 4, is set.
BSCHK: Mov A,PSW
;MOVE PSW CONTENTS TO ACC
JB4 RB1SET
;JUMP TO 'RB1SET' IF ACC BIT 4 = 1

14·22

MCS®·48 INSTRUCTION SET

MOV A,R r

Move Register Contents to Accumulator

Encoding: 11 1 1 1 11 r r r 1

F8H-FFH

Description: 8-bits of data are removed from working register 'r' into the accumulator.
Operation: (A) -

r = 0-7

(Rr)

;MOVE CONTENTS OF REG 3 TO ACC

Example: MAR: MOV A,R3
MOV A,@Ri

Move Data Memory Contents to Accumulator

Encoding 11 1 1 1 10 00 i 1

FOH-F1H

Description: The contents of the resident data memory location addressed by bits 0-5** of
register 'i' are moved to the accumulator. Register 'i' contents are unaffected.
Operation: "(A) -

((Ri»

Example: Assume R1 contains 00110110.
MADM: MOV A,@R1

=0-1

;MOVE CONTENTS OF DATA MEM
;LOCATION 54 TO ACC

MOV A,T. Move Timer/Counter Cont.ents to Accumulator
Encoding: 10 1 0 0 1 0 0 1 0 1

42H

Description: The contents of the timer/event-counter register are moved to the
accumulator.
Operation: (A) -

(T)

Example: Jump to "EXIT" routine when timer reaches '64', that is, when bit 6 setassuming initialization 64,
.
TIMCHK: MOV.A,T
;MOVE TIMER CONTENTS TO ACC
JB6 EXIT
;JUMP TO 'EXIT' IF ACC BIT 6 = 1

MOV pSW,A

Move Accumulator Contents to PSW

•• O-!;i in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH

14-23

MCS®.-48 I NS:t"RUCl'ION SET

MOV Rr,A

Move Accumulator Contents to Register'

Encoding: 11 0 1 0 11 r r r 1

A8H-AFH.

Descrlptlom The contents of the accumulator are moved to register 'r'.
Operation: (Rr) -

(A)

r = 0-7

Example: MRA: MOV RO,A
MOV Rr,#data

;MOVE CONTENTS OF ACC TO REG 0

Move Immediate Data to Register

Encoding: 11 011

B8H-BFH

1 r2 r1 rol

Description: This is a 2-cycle instruction. The 8-bit value specified by 'data' is moved to
register'r'. . .
.
Operation: (Rrf -

r = 0-7

data

Examples: MIR4: MOV R4,#HEXTEN
MIR S: MOV RS,#PI*(R*R)
MIR 6: MOV R6, #OADH
MOV @ Ri,A

;THE VALUE OF THE SYMBOL
;'HEXTEN' IS MOVED INTO REG 4
;THE VALUE OF THE EXPRESSION
;'PI*(R*R)' IS MOVED INTO REG S
;'AD' HEX IS MOVED INTO REG 6

Move Accumulator Contents to Data Memory

Encoding: 11 0 1 0

I0 0 0 i I

AOH-A1H

Description: The contents of the accumulator are moved to the resident data memory
location whose address is specified by bits O-S** of register 'i'. Register 'i'
contents are unaffected.
Operation: ((Ri)) -

. i = 0-1

(A)

Example: Assume RO contains 00000111.
MDMA: MOV @RO,A, .

MOV @ Rj,#data

;MOVE CONTENTS OF ACC TO
;LOCATION 7 (REG 7)

Move Immediate Data to Data memory

Encoding: 11- 0 1 1 0 0 0 i

I Id7 d6 dS d4. 1 d3 d2 d1 dO I

BOH-B1H

Description: This is a 2-cycle instruction. The 8-bit value specified by 'data' is moved
to the resident d\'lta memory location addressed by register 'i', bits o-S**.
Operation: ((Ri)) -

data

i =0-1

Examples: Move the hexadecimal value AC3F to locations 62-63.
MIDM: MOV RO,#62
;MOVE '62' DEC TO ADDR REG 0
MOV @RO,#OACH
;MOVE 'AC' HEX TO LOCATION 62
INC RO
;INCREMENT REG 0 to '63'
MOV @RO,#3FH
;MOVE '3f' HEX TO LOCATION 63
** 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH

MCS®-48 INSTRUCTION SET

MOV T,A

Move Accumulator Contents to Timer/Counter

Encoding:

I0 1 1 0 10 0 1 0 1

62H

Description: The contents of the accumulator are moved to the timer/event-counter
register.
Operation: (T) -

(A)

Example: Initialize and start event counter.
;CLEAR ACC TO ZEROS
INITEC: CLR A
MOVT,A
;MOVE ZEROS TO EVENT COUNTER
START CNT
;START COUNTER
MOVD A,Pp

Move Port 4-7 Data to Accumulator

Encoding: 10 0 0 0 11 1 p pi

OCH-OFH

Description: This is a 2-cycle instruction. Data on 8243 port 'p' is moved (read) to
a~cumulator bits 0-3. Accumulator bits 4-7 are zeroed.
Operation: (0-3) (4-7) -

(Pp)
0

=4-7

Note: Bits 0-7 of the opcode are used to represent ports 4-7. If you are
coding in binary rather than assembly language, the mapping is as
follows:
Bits 10

Port

00
01
10
11

4
5
6
7

Example: INPPT5: MOVD A,P5

MOVD Pp,A
Encoding:

;MOVE PORT 5 DATA TO ACC
;BITS 0-3, ZERO ACC BITS 4-7

Move Accumulator Data to Port 4-7

I0 O· 1 1 11 1 P P I

3CH-3FH

Description: This is a 2-cycle instruction. Data in accumulator bits 0-3 is moved
(written) to 8243 port 'p'. Accumulator bits 4-7 are unaffected. (See NOTE
above regarding port mapping.)
Operation: (Pp) -

P = 4-7

(AO-3)

Example: Move data in accumulator to ports 4 and

;MOVE ACC BITS 0-3 TO PORT 4
;EXCHANGE ACC BITS 0-3 and 4-7
;MOVE ACC BITS 0-3 TO PORT 5

OUTP45: MOVD P4,A
SWAP A
MOVD P5,A

14-25

MCS®-48 INSTRUCTION S.ET

MOVP A,@A

Move Current Page Data to ~ccumulator

Encoding: 11 0 1 0 1 0 0 1 1 1

A3H

Description: The contents of the program memory location addressed by,the
accumulator are moved to the accumulator. Only bits 0-7 of the program
counter are affected, limiting the program memory reference to the
.,
current page. The program counter is restored following this operation.
Operation: (PCO-7) - (A)
(A) - «PC»
Note: This is a 1-byte, 2-cycle instruction. If it appears in location 255 of a
program memory page, @A addresses a location in the following page.
Example: MOV128: MOV A,#128
MOVP A,@A

MOVP3 A,@A

;MOVE '128' DEC TO ACC,
;CONTENTS OF 129th LOCATION IN
;CURRENT PAGE ARE MOVEDTOACC

Move Page 3 Data to Accumulator

Encoding: 11 1 1 0 1 0 0 1 1 1

E3H

Description: This is a 2-cycle instruction. The contents of the program memory location
(within page 3) addressed by the accumulator are moved to the
accumulator. The program counter is restored following this operation.
Operation: (PCO-7) - (A)
(PC8-11) - 0011
(A) - «PC»
Example: Look up ASCII equivalent of hexadecimal code in table contained at the
beginning of page 3. Note that ASCII characters are deSignated by a
7-bit code; the eighth bit is always reset.
TABSCH: MOV A,#OB8H
;MOVE 'B8'HEX TO ACC (10111000)
ANL A,#7FH
;LOGICAL AND ACC TO MASK BIT
;7 (00111000)
;MOVE CONTENTS OF LOCATION '38'
MOVP3 A,@A
;HEX IN PAGE 3 TO ACC (ASCII '8')
Access contents of location' in page 3 labelled TAB1.
Assume current program location is not in page 3.
TABSCH: MOV A,#LOW TAB 1 ;ISOLATE BITS 0-7 OF LABEL
;APDRESS VALUE,
MOVP3 A,@A
;MOVE CONTENTS OF PAGE3,
;LOCATION LABELED 'TAB1' 'rCACe

14-26

.MCS®-48 INSTRUCTION SET
- - - - - - - - - - - - _ .. - - - - _.._ - - - - - - - - - - - - - _ .

MOVX A,@RI

Move External-Data-Memory Contents to Accumulator

Encoding: 11 0 0 0 1 0 0 0 i 1

SOH-S1 H

Description: This is a 2-cycle instruction. The contents of the external data memory
location addressed by register 'i' are moved to the accumulator. Register 'i'
contents are unaffected. A read pulse is generated.
Operation: (A) -

«Ri)) .

Example: Assume R1 contains 01110110.
MAXDM: MOVX A,@R1

MOVX@Rj,A

=0-1

;MOVE CONTENTS OF LOCATION
;118 TO ACC

Move Accumulator Contents to External/Data Memory

Encoding: 11 0 0 1 1 0 0 0 i 1

90H-91H

Description: This is a 2-cycle instruction. The contents of the accumulator are moved to
the external data memory location addressed by register 'i'. Register 'i'
contents are unaffected. A write pulse is generated.
Operation: «Ri)) -

i = 0-1

Example: Assume RO contains 11000111.
MXDMA: MOVX @RO,A

NOP

;MOVE CONTENTS OF ACC TO
;LOCATION 1991N EXPANDED
;DATA MEMORY

The NOP Instruction

Encoding: 10 0 0 0 1 0 0 0 0 1

OOH

Description: No operation is performed. Execution continues with the following
instruction.
ORL A,R r

Logical OR Accumulator With Register Mask

Encoding: 10 1 0 0 11 r r rl

4SH-4FH

Description: Data in the accumulator is logically ORed with the mask contained in
working register 'r'.
Operation: (A) -

(A) OR (Rr)

Example: ORREG: ORL A,R4

=0-7

;'OR' ACC CONTENTS WITH
;MASK IN REG 4

14-27

MCS@·48 JNSTRUCTION SET

ORL A,@RI

Logical OR Accumulator With Memory Mask

Encoding: 10 1 00 10 0 0 i 1

40H-41H

Description: Data in the accumulator is logically ORed with the mask contained in the
resident data memory locati.on referenced by register "i", bits 0-5**.
Operation: (A) -- (A) OR ((Ri))

i = 0-1

Example: ORDM: MOV RO,#3FH;MOVE '3F' HEX TO REG 0
ORL A,@RO
;'OR' AC CONTENTS WITH MASK
;IN LOCATION 63
ORL A,#data

Logical OR Accumulator With Immediate Mask

Encoding: 10 1 0 0 0 0 1 1 1

1d7 d6 d5 d4 1 d3 d2 d1 dO

43H

Description: This is a 2-cycle instruction. Data inthe accumulator is logically ORed with
an immediately-specified mask.
Operation: (A) -- (A) OR data
;'OR' ACC CONTENTS WITH MASK
;01011000 (ASCII VALUE OF 'X')

Example: ORID: ORL A,#'X'

ORL BUS,#data* Logical OR BUS With Immediate Mask
88H

Encoding: 11 0 0 0 11 0 0 0 1

Description: This is a 2-cycle instruction. Data on the BUS port is logically ORed with an
immediately-specified mask. This instruction assumes prior specification
on an 'OUTL BUS,A' instruction.
Operation: (BUS) -- (BUS) OR data
Example: ORBUS: ORLBUS,#HEXMSK

ORLPp, #data

:'OR' BUS CONTENTS WITH MASK
;EQUAL VALUE OF SYMBOL 'HEXMSK'

Logical OR Port 1 or 2 With Immediate Mask

Encoding: 11 0 0 0 11 0 P pi

1d7 d6 d5 d4

I d3 d2 d1

89H-8AH

Description: This isa 2-cycle instruction. Data on port 'p' is logically ORed with an
immediately-specified mask.

p = 1-2

Operation: (Pp) -- (Pp) OR data
Example: ORP1: ORL P1, #OFFH

;'OR' PORT 1 CONTENTS WITH MASK
;'FF' HEX (SET PORT 1 TO ALL ONES)

• For use with internal program memory ONLY.
•• 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH

14-28

MCSS"48 INSTRUCTION SET

ORlD Pp,A
Encoding:

logical OR Port 4-7 With Accumulator Mask

0 0 0

11 1 P P 1

8CH-8FH

Description: This is a 2-cycle instruction. Data on port 'p' is logically ORed with the
digit mask contained in accumulator. bits 0-3.
Operation: (Pp) -

(Pp) OR (AO-3)

Example: ORP7: ORlD P7.A

=4-7

;'OR' PORT 7 CONTENTS WITH ACC
;BITS 0-3

OUTl BUS,A* Output Accumulator Data to BUS
Encoding:

@1 0

0 10 0 1 0

02H

Description: This is a 2-cycle instruction. Data residing in the
accumulator is transferred (written) to the BUS port and
latched. The latched data remains valid until altered by
another OUTl instruction. Any other instruction requiring
use of the BUS port (except INS) destroys the contents of
the BUS latch. This includes expanded memory operations
(such as the MOVX instruction). logical operations on
BUS data (AND, OR) assume the OUTL BUS,A instruction
has been issued previously.
Operation: (BUS) -

(A)

Example: OUTLBP: OUTL BUS, A
OUTl Pp,A

;OUTPUT ACC CONTENTS TO BUS

Output Accumulator Data to Port 1 or 2

Encoding: 10 0 1 1 11 0 P pi

39H-3AH

Description: This is a 2-cycle instruction. Data residing in the accumulator is transferred
(written) to port 'p' and latched.
Operation: (Pp) -

P = 1-2

(A)

Example: OUTLP: MOV A,R7
OUTL P2,A
MOV A, R6
OUTL P1.A

;MOVE REG 7 CONTENTS TO ACC
;OUTPUT ACC CONTENTS TO PORT 2
;MOV REG 6 CONTENTS TO ACC
;OUTPUT ACC CONTENTS TO PORT 1

• For use with internal program memory ONLY.

14-29

MGS®-48INSTR'l,JCTIONSET·

RET

Return Without PSW Restore

Encoding: 11 0 0 0

!0 0 1 1/

83H

Descript!on: Ttlis is a ~-cycle instruction. The stack pointer (PSW bits 0-2) is
decremented. The program counter is then restored from the stack. PSW
bits 4-7 are not restored.
Operation: (SP) - (SP)-1
(PC) -«SP»

RETR

Return with PSW Restore

Encoding: 11 0 0 1 / 0 0 1 1

93H

Description: This is a 2-cycle instruction. The stack pointer is decremented. The
program counter and bits 4-7 of the PSW are then restored from the stack.
Note that RETR should be used to return from an interrupt, but should
not be used within the interrupt service routine as it signals the end of an
interrupt routine by resetting the Interrupt in Progress flip-flop.
Operation: (SP) +-- (SP)-1
(PC) - «SP» .
(PSW 4-7)...,... «SP»

14-30

. MCS@-48 INSTRUCTION SET

RL A

Rotate Left without Carry

Encoding: 11 1 1 0

I0 1 1 1 I

E7H

Description: The contents of the accumulator are rotated left one bit. Bit 7 is rotated'
into the bit 0 position.
Operation: (An + 1) - (An)
(AO) - (A7)

n = 0-6

Example: Assume accumulator contains 10110001.
RLNC: RL A
. ;NEW ACC CONTENTS ARE 01100011
RLC A

Rotate Left through Carry

Encoding: 11 1 1 1

I0 1 1 1 I

F7H

Description: The contents of the accumulator are rotated left one bit. Bit 7 replaces the
carry bit; the carry bit is rotatd into the bit 0 position ..
Operation: (An + 1) - (An)
n =0-6
(AO) - ,(C)
(C) - (A7)
Example: Assume accumulator contains a 'signed' number; isolate sign without
changing value.
RLTC: CLR C
;CLEAR CARRY TO ZERO
RL'CA
;ROTATE ACC LEFT, SIGN
;BIT (7) IS PLACED IN CARRY
;ROTATE ACC RIGHT - VALUE
RRA
;(BITS 0-6) ISRES1b'RED,
;CARRY UNCHANGED, BIT 7
;IS ZERO
RR A

Rotate Right without Carry

Encoding: 10 1 1 1

I0 1 1 1 I

77H

Description: The contents of the accumulator are rotated right one bit. Bit 0 is rotated
into the bit 7 position.
'
Operation: (An) (A7) -

(An + 1)
(AO)

n = 0-6

Example: Assume accumulator contains 10110001.
RRNC: RR A
;NEW ACC CONTENTS ARE 11011000

. 14-31

MCS®·48INSTR.UCTION SET

RRC A

Rotate Right through Carry

Encoding: 10 1 1 0 10 1 1 11

67H

Description: The contents of the accumulator are rotated right one bit. Bit 0 replaces the
carry bit; the carry bit is rotated into the bit 7 position.

n =0-6

Operation: (An) - (An + 1)
(A7) - (C)
(C) - (AO)

Example: Assume carry is not set and accumulator contains 10110001.
;CAAAY IS SET AND ACC
RATC: ARC A
;CONTAINS 01011000·

SEL MBO

Select Memory Bank 0 .

Encoding: 11 1 1 0 1 0 1 0 1 1

E5H

Description: PC bit 11 is set to zero on next JMP or CALL instruction. All references to
program memory addresses fall within the range 0-2047.
Operation: (DBF) -

Example: Assume program counter contains 834 Hex.
SEL MBO
;SELECT MEMORY BANK 0
JMP $+20
;JUMP TO LOCATION 58 HEX

SEL MB1

Select Memory Bank 1

Encoding: 11 1 '·1 101 0 1

F5H

Description: PC bit 11 is set to one on next JMP or CALL instruction. All references to
program memory addresses fall within the range 2048-4095.
Operation: (DBF) -

.14-32

MCSI8~48

INSTRUCTION SET

SEL RBO Select Register Bank 0
Encoding: 11 1 0 0 10 1 0 1 1

C5H

Description: PSW bit 4 is set to zero. References to working registers 0-7 address data
memory locations 0-7. This is the recommended setting for normal
program execution.
Operation: (BS) SEL RB1

Select Register Bank 1

Encoding: 11 1 0 1 10 1 0 1 1

D5H

Description: PSW bit 4 is set to one. References to working registers 0-7 address data
memory locations 24-31. This is the recommended setting for interrupt service
routines, since locations 0-7 are left intact. The setting of PSW bit 4 in
effect at the time of an interrupt is restored by the RETR instruction when
the interrupt service routine is completed.
Operation: (BS) -

Example: Assume an external interrupt has occurred, control has passed to program
melTJory location 3, and PSW bit 4 was zero before the interrupt.
Operation: LOC3: JNI INIT
INIT: MOV R7,A
SEL RB1
. MOV"R7.#OFAH

SEL RBO
MOVA,R7
RETR
STOP TCNT
Encoding:

;JUMP TO ROUTINE 'INIT' IF
;INTERRUPT INPUT IS ZERO
;MOVE ACC CONTENTS TO
;LOCATION 7
;SELECT REG BANK 1
;MOVE 'FA' HEX TO LOCATION 31

;SELECT REG BANK 0
;RESTORE ACC FROM LOCATION 7
;RETURN - RESTORE PC AND PSW

Stop Timer/Event-Counter

I0 1 1 0 10 1 0 1.1

65H

Description: This instruction is used to stop both time accumulation and event counting.

14·33

MCS@-48INSTRUCTION SET

Example: Disable interrupt, but jump to interrupt routine after eight overflows and
stop timer. Count overflows in r~gister 7.
START: DIS TCNTI
;DISABLE TIMER INTERRUPT
CLRA
;CLEAR ACC TO ZEROS
iMOVE ZEROS TO TIMER
MOVT,A
MOV R7,A
;MOVEZEROSTO REG 7·
STRTT
;START TIMER
MAIN: JTF COUNT
;JUMP TO ROUTINE 'COUNT'
;IF TF = 1 AND CLEAR TIMER FLAG
JMP MAIN
;CLOSE LOOP
;INCREMENT REG 7
COUNT: INC R7
MOVA,R7
;MOVE REG 7 CONTENTS TO ACC
JB31NT
;JUMP TO ROUTINE 'INT' IF ACC
;BIT 3 IS SET (REG 7 = 8)
JMP MAIN
;OTHERWISERETURN TO ROUTINE
;MAIN

;STOP TIMER
;JUMP TO LOCATION 7 (TIMER)
;INTERRUPT ROUTINE

INT: STOP TCNT
JMP7H

STRT CNT
Encoding:

Start Event Conter

I0 1 0 0 I0 1 0 1 I

45H

Description: The test 1 (T1) pin is enabled as the event-counter input and the counter
is started. The event-counter register is incremented with each high-to-Iow
transition on the T1 pin.
Example: Initialize and start event counter.
input.
STARTC: EN TCNTI
MOV A,#OFFH
MOVT,A
STRT CNT

Assume overflow is desired with first T1

14-34

;ENABLE COUNTER INTERRUPT
;MOVE 'FF'HEX (ONES) TO ACC
;MOVES ONES TO COUNTER
;ENABLE T1 AS COUNTER
;INPlJT AND START

MCS@-48 INSTRUCTION SET

STRT T

Start Timer

Encoding: 10 1 0 1 1 0 1 0 1 1

55H

Description: Timer accumulation is initiated in the timer register. The register is
incr.emented every 32 instruction cycles. The prescaler which counts the
32 cycles is cleared but the timer register is not.
Example: Initialize and start timer.
;CLEAR ACC TO ZEROS
;MOVE ZEROS TO TIMER
;ENABLE TIMER INTERRUPT
;START TIMER

STARTT: CLR A
MOVT,A
EN TCNTI
STRTT
SWAP A

Swap Nibbles within Accumulator

Encoding: 10 1 0 0

I0 1 1 1 I

47H

Description: Bits 0-3 of the accumulator are swapped with bits 4-7 of the accumulator.
Operation: (A 4-7)!:; (AO-3)
Example: Pack bits 0-3 of locations 50-51 into location 50.
;MOVE '50' DEC TO REG 0
PCKDIG: MOV RO, #50
MOV R1, #51
;MOVE '51' DEC TO REG 1
XCHDA,@RO
;EXCHANGE BITS 0-3 OF ACC
;AND LOCATION 50
;SWAP BITS 0-3 AND 4-7 OF ACC
SWAP A
;EXCHANGE BITS 0-3 OF ACe AND
XCHDA,@R1
;LOCATION 51
MOV@RO,A
;MOVE CONTENTS OF ACC TO
;LOCATION 50
XCH A,R r

Exchange Accumulator-Register Contents

Encoding:

I0 0 1 0 11

r r r

28H-2FH

Description: The contents of the accumulator and the contents of working register 'r'
are exchanged.
Operation: . (A) !:; (Rr)

r = 0-7

Example: Move PSW contents to Reg 7 without losing accumulator contents.
XCHAR7: XCH A,R7
;EXCHANGE CONTENTS OF AEG 7
;AND ACC
MOV A, PSW
;MOVE PSW CONTENTS TO ACC
XCH A,R7
;EXCHANGE CONTENTS OF REG 7
'AND ACC AGAIN

14-35

MCS@·48 INSTRUCTION SET.

XCH A,@R,

Exchange Accumulator and Data Memory Contents

Encoding: 10 0 1 0

0 0 0 i

20H-21H

Des~ription: The contents of the accumulator and the contents of the resident data

memory location addressed bybits 0-5** of register 'i' are exchanged.
Register 'i' contents are unaffected.
Operation: (A) =; «Ri»

i = 0-1

Example: Decrement contents of location 52.
DEC52: MOV RO,#52
;MOVE '52' DEC TO ADDRESS REG 0
;EXCHANGE CONTENTS OF ACC
. XCH A,@RO
;AND LOCATION 52
DECA
;DECREMENT ACC CONTENTS
XCH A,@RO
;EXCHANGE CONTENTS OF ACC
;AND LOC.ATION 52 AGAIN
XCHD A,@Ri

Exchange Accumulator and Data Memory 4-81t Data

Encoding: 10 0 1 1 1 0 0 0 i

30H-31H

Description: This instruction exchanges bits 0-3 of the accumulator with bits 0-3 of
th.e data :memory location addressed by bits 0-5** of register 'i'. Bits 4-7 of
the accumulator, bits 4-7 of the data memory location, and the contents of
register 'i' are unaffected.
Operation: (AO-3) =; «RiO-3»

= 0-1

Example: Assume program counter contents have been stacked in locations 22-23.

XCHNIB: MOV RO,#23
CLRA
XCHD A,@RO

XRL A,R r

;MOVE '23' DEC TO REG 0
;CLEAR ACC TO ZEROS
;EXCHANGE BITS 0-3 OF ACC AND
;LOCATION 23 (BTS 8-11 OF PC ARE
;ZEROED, ADDRESS REFERS
:TO PAGE 0)

Logical XOR Accumulator With Register Mask

Encoding: 11 1 0 1

11 r r r 1

D8H-DFH

Description: Data in the accumulator is EXCLUSIVE ORed with the mask contained in
working register 'r'.
Operation: (A) -

r = 0-7

(A) XOR (Rr)

Example: XORREG: XRL A,R5

;'XOR' ACC CONTENTS WITH
;MASK IN REG 5

•• 0-5 in S04SAH/S74SH
0-6 in S049AH/S749H
0-7 in S050AH

14-36

MCS®-48 INSTRUCTION SET

XRL A,@Ri

Logical XOR Accumulator With Memory Mask

Encoding: 11 1 0 1 1 0 0 0 i 1

DOH-D1H

Description: Data in the accumulator is EXCLUSIVE ORed with the mask contained in the
data memory location addressed by register 'i', bits 0-5,**
Operation: (A) -

i =0-1

(A) XOR «Ri))

Example: XORDM: MOV R1 ,#20H
XRL A,@R1

XRL A,#data

;MOVE '20' HEX TO REG 1
;'XOR' ACC CONTENTS WITH MASK
;IN LOCATION 32

Logical XOR Accumulator With Immediate Mask

Encoding:
1 0 1 10 0 1 1 1
1d7 dS dS d4 1 d3 d2 d1 dO
D3H
Description: This is a 2-cycle instruction. Data in the accumulator is EXCLUSIVE ORed
with an immediately-specified mask.
Operation: (A) -

(A) XOR data

Example: XORID: XOR A,#HEXTEN

;XOR CONTENTS OF ACC WITH MASK
;EQUAL VALUE OF SYMBOL 'HEXTEN'

** 0-5 in 8048AH/8748H

0-6 in 8049AH/8749H
0-7 in 8050AH

14-37

MCS®~48 Data Sheets

",'

8243
MCS®-48 INPUT/OUTPUT EXPANDER
• 00 C to 700 C Operation

PORT 4

PORT 5

PORT 2

PORT 6

PORT 7

Figure 1. 8243
Block Diagram

15-1

P50

Vee

P40

P51

1'141

P52

PI42

P53

PI43

P50

Pel

PROG

Pe2

P23

Pe3

P22

P73

P21

P72

P20

P71

GNO

P70

Figure 2. 8243
Pin Configuration

8243
Table 1. Pin Description
Symbol Pin No.
PROG

Power On Initialization

Function

Clock Input A high to low transition on PROG signifies 'that ad~
dress and contro'l are available on
P20-P23, and a low to high transItion signifies that data IS available
on P20-P23.
CS
Chip Select Input A hl'gh on CS
6
inhibits any change of output or
internal status
P20-P23
11-8
Four (4) bit bl-dlrectlonal port contains the address and control bits
on a high to low trimsltlon of
PROG Dunng a low to high transitton contains the data for a selected output port If a write operation, or the data from a selected
port before the low to high transItion If a read operation.
GND
12
o volt supply
P40-P43
2-5
Four (4) bit bl-dlrectlOnall/O ports
P50-P53 1,23-21 May be programmed to be Input
P60-P63 20-17 (dunng read), low Impedance
P70-P73 13-16 latched output (after write), or a tristate (after read). Data on pins
P20-P23 may be directly wntten,
ANDed O( ORed with prevIous
data.
24
+5 volt supply
VCC

Initial application of power to the device forces
'input/output ports 4, 5, 6, and 7 to the tri-state and
port 2 to the input mode. The PROG pin may ~e
either high or low when power is applied. The first
high to low transition of PROG causes device to
exit power on mode The power on sequence is
initiated if vee drops below 1V.

P21 P20
0
0

Address
Code

0
1
0

Port
Port
Port
Port

4
5
6
7

P23 P22
0
0

0
1
0

Instruction
Code
Read
Write
ORlD
ANlD

Write Modes
The device has three write modes. MOVD Pi, A directly writes new data into the selected port and old
data is lost. ORlD Pi, A takes new data, OR's it with
the old data and then writes it to the port. ANlD Pi, A
takes new data, AND's it with the old data and then
writes it to the port. Operation code and port address are latched from the input port 2 on the high
to low transition of the PROGpin. On the lowto high
transition of PROG data on port 2 is transferred to
the logic block of the specified output port.
After the logic manipulation IS performed, the data
is latched and outputed. The old data remains
latched until new valid outputs are entered.

FUNCTIONAL DESCRIPTION
General Operation
The 8243 contains four 4-blt I/O ports which serve
as an extension of the on-chip I/O and are addressed, as ports 4-7. The following operations may
be performed on these ports.

Read Mode

All communication between the 8048 and the 8243
occurs over Port 2 (P20-P23) with timing provided
by an output pulse on the PROG pin of the processor. Each transfer consists of two 4-bit nibbles:

The device has one read mode. The operation code
and port address are latched from the input port 2 on
the high to low transition of the PROG pin. As soon
as the read operation and port address are decoded,
the appropriate outputs are tri-stated, and the input
buffers switched on. The read operation is terminated by a low to high transition of the PROG pin. The
port (4, 5, 6 or 7) that was selected is switched to the
tri-stated mode while port 2 is returned to the input
mode.

The first containing the "op code" and port address
and the second containing the actual 4-bits of data.
A high to low transition of the PROG line indicates
that address is present while a low to high transition
indicates the presence of data. Additional 8243's
may be added to the 4-bit bus and chip selected
using additional output lines from the 8048/8748/
8035.

Normally, a port will be in an output (write mode) or
input (read mode). If modes are changed during
operation, the first read following a write should
be ignored; all following reads are valid. This is to
allow the external driver on the port to settle after
the first read instruction removes the low impedance drive from the 8243 output. A read of any port
will leave that port in a high impedance state.

•
•
•
•

Transfer Accumulator to Port.
Transfer Port to Accumulator.
AND Accumulator to Port.
OR Accumulator to Port.

15-2

8243
'NOTlCE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the' device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias. . . . . . .. O· C to 70· C
Storage Temperature ............... -6S·C to +1S0·C
Voltage on Any Pin
WIth Respect to Ground .............. -0.5 V to +7V
Power Dissipation ............................. 1 Watt

D.C. CHARACTERISTICS
Symbol

(TA = o·c to 70·C. VCC = 5V

Min

Parameter

± 10%)
Typ

Max

Units

Test
Conditions

Vil

Input low Voltage

-O.S

0.8

VIH

Input High Voltage

2.0

VCC+O.S

VOU

Output low Voltage Ports 4-7

0.45

IOl = 4.5 mA"

VOl2

Output low Voltage Port 7

IOl = 20 mA

VOH1

Output High Voltage Ports 4-7

2.4

Hll

Input leakage Ports 4-7

-10

,uA

Vin = VCC to OV

-10

10
0.45

,uA

Vm = VCC to OV

IOl = 0.6 mA
Note 1

4.5 mA Each Pin

IIl2

Input leakage Port 2. CS. PROG

VOl3

Output low Voltage Port 2

ICC

VCC Supply Current

VOH2

Output Voltage Port 2

IOl

Sum of alilOl from 16 Outputs

IOH = 240,uA

IOH = 100,uA

2.4

'See follOWing graph for addItional srnk current capability

A.C. CHARACTERISTICS
Symbol

(TA

=o·c to 70°C.

Parameter

VCC

Min

=5V ± 10%)
Max

Units

Test Conditions

Code Valid Before PROG

Code Valid After PROG

20 pF load

Data ValId Before PROG

200

80 pF load

Data Valid After PROG

. 20 pF load

Floatmg After PROG

20 pF load

PROG NegatIve Pulse Width

700

tcs

CS ValId Before/After PROG

tpo

Ports 4-7 Valid After PROG

tlPl

Ports 4-7 Valid Before/After PROG

tACC

lS0

ns
ns
700

100

. Port 2 Valid After PROG

100 pF load

ns
6S0

Note 1: ICC~(-40°C to 85°C EXPRESS options) 15 mA tYPIcall25 mA maximum.

15-3

80 pF load

.::=x,......-:>~T-ESTPOINT-S<------..::x~
A C Testing Inputs are dnven al2 4V for d logIc' l'
and 0 45V for a logic "0" Output liming measurements
are made al 2 OV for a logic ''1' and 0 8V for a logic "0"

WAVEFORMS

PROG

~~~

PORT2

______________ 'K ________________

FLOAT

'~;1
OUTPUT

PORT2

VALID

~'x
IpO

PORTS 4-7

OUTPUT
VALID

PREVIOUS OUTPUT VALID

"P
PORTS 4-7

',P

INPUT VALID

les

8243

125

100

..
g

9
"

I-

W
II:
II:

"
Z

iii

GUARANTEEO WORST CASE
C~RRENT SINKING CAPABILITIES
OF ANY 110 PORT PIN VS. TOTAL
SINK CURRENT OF ALL PINS

~
0

I-

MAXIMUM SINK CURRENT ON ANY PIN @ .45Y
MAXIMUM IOL WORST CASE PIN,(mA)

Figure 3
Example: This example shows how the use of the 20 mA
sink capability of Port 7 affects the sinking
capability of the other I/O lines.

Sink Capability
The 8243 can sink 5 mA@ .45V on each of its 161/0
lines simultaneously. If, however, all lines are not
sinking simultaneously or all lines are not fully
loaded., the drive capability of any individual line
increases as is shown by the accompanying curve.

An 8243 will drive the following loads simultaneously.

For example, if only 5 of the 16 lines are to sink
current at one time, the curve shows that each of
those 5 lines is capable of sinking 9 mA @ .45V (if
any lines are to sink 9 mA the total 10L must not
exceed 45 mA or five 9 mA loads).

2 loads-20 mA@ lV (port 7 only)
8 loads-4 mA @ .45V
6 loads-3.2 mA @ .45V
Is thiS within the specified limits?

Example: How many pins can drive 5 TTL loads (1.6 mAl
assuming remaining pins are unloaded?

,10l = (2 x 20) + (8 x 4) + (6 x 3.2) = 91.2 mAo
From the curve. for 10l = 4 mA, ,10l = 93 mAo
since 91.2 mA < 93 mA the loads are within
specified limits.

10l =5 x 1.6 mA =8 mA
dOL = 60 mA from curve
# pins = 60 mA..;- 8 mA/pm = 7.5 = 7
In this case, 7 lines can sink 8 mA for a total of
56mA. This leaves 4 mA sink current capability
which can be divided In any way among the
remaining 8 I/O lines of the 8243.

Although the 20 mA @ 1V loads are used in
calculating dOL. It IS the largest current required @ .45V which determines the maximum
allowable ,10l.

NOTE: Al0 to 50KO pull up resistor to +5V should be added to 8243 outputs when driVing to 5V CMOS directly

15-5

inter

8243

-=CS

I/O

'/0

PROG

TEST
INPUTS

8048

8243
DATA IN

P2O·P23

Figure 4. Expander Interface

PROG

'20·'23

ADDRESS (4·BITSI

BITS 3,2

g~
11

DATA (4·8IT51

1 ~~~~E
I

' AND

BITS 1,0
00
01
10

PORT
ADDRESS

11,

Figure 5. Output Expander Timing

PORT 1

8048

PROG~--------"------~--------------~----------------4---------------~

Figure 6. Using Multiple 8243's

15-6

inter

[pJ1Rl~[lJ Iilal ~INlfo\lRl 11'

S04SAH/S035AHL/S049AH
S039AHL/S050AH/S040AHL
HMOS SINGLE-COMPONENT S-BIT MICROCOMPUTER
•
•
•
•
•

High Performance HMOS II
Interval Timer/Event Counter
Two Single Levellhterrupts
Single 5-Volt Supply
Over 96 Instructions; 90% Single Byte

•
•
•
•

Reduced Pow~r C!>nsumption
Compatible with 8080/8085 Peripl)erals
Easily Expandable Memory and I/O
Up to 1.36 ",Sec Instruction Cycle
All Instructions 1 or 2 cycles

The Intel MCS®·48 family are totally self-sufficient, 8-bit'parallel computers fabricated on single silicon chips
using Intel's advanced N-channel silicon gate- HMOS process.
The family contains 27 I/O lines, an 8-bit timer/counter, and on-board oscillator/clock circuits. For systems that
require extra capability, the family can be expanded using MCS®-80/MCS®-85 peripherals.
To minimize development problems and provide maximum flexibility, a logically and functionally pin-compatible
version of the ROM devices with UV-erasable user-programmable EPROM program memory is available with
'
minor differences.
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for both binary and BCD,arithmetic. Efficient use of program
memory results from an instruction set consisting mostly of single byte instructions .and no instructions over
2 bytes in length.
Device

RAM Standby

Internal Memory
I
256

8,BAM

yes

I
I

128

8 RAM

yes

8 RAM

yes

none

256

8RAM

yes

8039AHL

none

128

8RAM

yes

8035AHl

none

8 RAM

yes

8050AH

8 ROM

8049AH

8 ROM

8048AH

8 ROM

8040AHL

8048AH
8035AHL
8049AH
8039AHL
8OS0AH
8040AHL

TO
XTAL 1
XTAL 2
RE;SET

S5
INT
'EA

AD
PSEN

P22
P21
P20

Figure 1.
Block Diagram

Figure 2.
Logic Symbol

15-7

Figure 3.
Pin Configuration

inter

8048AH/8035AHL/8049AH
8039AHL/8050AH/8040AHL

Table 1. Pin De$crlptlon
Symbol

Pin
No.

VSS

VDD

Pin
Function

Symbol
RD

Circuit GND potential

No:
8

+ 5V during 'normal operatiqn.
Low power stanqby pin.

+ 5V

VCC

Main power supply;
during operation.

PROG

Output strobe for 8243 I/O
expander.

P10-P17
Port 1

27-34 8-bit quasi-bidirectional port.

P20-P23
P24-P27
Port 2

21-24 8-bit quasi-bidirectional port.
35-38 P20-P23 contain the four high
order program counter bits
during an external program
memory fetch and serve as a
4-bit I/O expander bus for
8243.

Used as a read strobe t6
external data memory.
(Active low)
RESET

INT

Input pin testable using the
JT1, and JNT1 instructions.
Can be designated the timer/
counter input using the STRT
CNT instruction.

Interrupt input. Initiates an
interrupt if interrupt is enabled.
Interrupt is disabled after a
reset. Also testable with
conditional jump instruction.
(Active low) interrupt must
remain low for at least 3
machine cycles for proper
operation.

Output strobe during a bus
write. (Active low)
Used as write strobe to
external data memory.

ALE

Address latch enable. This
signal occurs once during each
cycle and is useful as a clock
output.
The negative edge of ALE
strobes address into external
data and program memory.

PSEN

Program store enable. This
output occurs only during a
fetch to external program
memory. (Active low)

Single step input can be used
in conjunction with ALE to
"single step" the processor
through each instruction.
(Active Low)

Input pin testable using the
conditional transfer instructions
JTO and JNTO. TO can be
designated as a clock output
using ENTO CLK instruction

Input which is used to initialize
the processor. (Active low)
(Non TTL VIH)
Used during ROM verification.

Used during power down.

DBO-DB7 12-19 True bidirectional port which
BUS
can be written or read
§y!!'chronously using the RD,
WR strobes. The port can also
be statically latched.

"Function
Output strobe ac\ivated during
a BUS read. Can be used to
enable data onto tl1e bus from
an external device.

Used in sync' mode
External access input which
forces all program memory
fetches to reference external
memory. Useful for emulation
and debug. (Active high)
Used during ROM verification
(12V)

15-8

XTAL1

One side of'crystal input for
internal oscillator. Also input for
external source. (Non TTL VIH)

XTAL2

Other side of crystal input.

S04SAH/S035AHL/S049AH
S039AHLlS050AH/S040AHL

Table 2. Instruction Set
Reglste,.

Accumulator
Mnemonic
ADDA,A
ADDA,@R
ADD A, # data
ADDCA, R
ADDCA,@R

Description
Add register to A
Add data memory to A
Add immediate to A
Add register with carry
Add data memory
with'carry
ADDC A, # data Add immediate
with carry
ANLA, A
And register to A
ANLA,@A
And data memory to A
ANL A, # data
And immediate to A
ORLA, A
Or register to A
ORLA@R
Or data memory to A
ORLA,#data
Or Immediate to A
XRL A, R
Exclusive or register
toA
XRLA,@R
Exclusive or data
memory to A
XRL, A, # data
Exclusive or
immediate to A
INCA
Increment A
DECA
Decrement A
CLRA
Clear A
CPLA
Complement A
DAA
Decimal adjust A
SWAP A
Swap nibbles of A
RLA
Rotate A left
RLCA
Rotate A left
th rough carry
RRA
Aotate A right
RRCA
Rotate A right
through carry

Mnemonic
INCR
INC@R
DECR

Byte. Cycl..
1
1
1
1

2
1
1

1
1
2
1
1
2
1

1
1
1
1
1
1
1
1

1
1

Branch
Mnemonic
JMPaddr
JMPP@A
DJNZR, addr

JC addr
JNCaddr
JZaddr
JNZ addr
JTO addr
JNTO addr
JTl addr
JNT1 addr
JFO addr
JFl addr
JTF addr
JNI addr
JBb addr

MOVDP, A
ANLDP,A
ORLDP,A

Description
Jump unconditional
Jump indirect
Decrement register
and skip
Jump on carry = 1
Jump on carry =0
Jump on A zero
Jump on A not zero
Jump on TO =1
Jump on TO =0
Jump on Tl = 1
Jump on T1 =0
Jumpon FO =1
Jump on Fl =1
Jump on timer flag
Jurnp on INT =0
Jump on accumulator
bit

Byte. Cycle.
2
2
1
2

Description
Jump to subroutine
Return
Retu rn and restore
status

Byte. Cycle.

Description
Clear carry
Coml>lement carry
Clear flag 0 •
Complement flag 0
Clear flag 1
Complement flag 1

Byt.. Cycles
J
1
1
1

2
2

2
2
2

2
2
2
2
2
2
2
2
2
2

2
2
2

2
2

Subroutine
Mnemonic
CALL addr
RET
RETR

Input/Output
Mnemonic
INA, P
OUTLP, A
ANL P,#data
ORL P,#data
INS A, BUS
OUTL BUS,A
ANL BUS, # data
ORL BUS, # data
MOVDA, P

Description
Bytes Cycles
Increment register
1
1
Increment daia memory
Decrement register

Description
Byt.. Cycle.
Input port to A
1
2
Output A to port
1
2
And immediate to port
2
2
Or immediate to port
2
2
Input BUS to A
1
2
Output A to BUS
1
2
And immediate to BUS
2
2
Or immediate to BUS
2
2
Input expander port
2
toA
Output A to expander
2
port
And A to expander port
2
Or A to expander port
2

2
2

Flag.
Mnemonic
CLR C
CPLC
CLR FO
CPL FO
CLR Fl
CPLFl

15-9

8048AM/8035AHU8049AH
8039AH.U8050AH/8040AHL

intel®

Table

Instruction Set (Continued)

Timer/Counter

Data Moves
Mnemonic
MOVA, R
MOVA,@R

Description
Move r!3gister to A
Move data memory
toA
M0VA,#data Move immediate to A
MOV R,A
Move A to register
MOV@R,A
Move A to data
memory
MOV R,#data Move Immediate
to register
MOV @R, # data Move immediate to
data memory
MOVA,PSW
Move PSW to A
MOV PSW, A
MoveAto PSW
XCHA, R
Exchange A and
register
XCHA,@R
Exchange A and
data memory
XCHDA,@R
Exchange nibble of A
and register
MOVXA,@R
Move external data
memory to A
MOVX@R,A
Move A to external
data memory
MOVPA,@A
Move to A from
cu rrent page
MOVP3A,@
Move to A from page 3

[P)1Rl~1L~1%1I~lNIfo\lRl'V

Bytes Cycles
1
1

.Mllemonlc
MOVA, T
MOVT,A
StRTT
STRT CNT
STOP TCNT
EN TCNTI

DIS TCNTI

Description
Read timer/counter
load timer/counter
Start timer
Start timer
Stop timer/counter
Enable timer/counter
interrupt
Disable timer/counter
interrupt

Bytas Cycles
1
1

Description
Enable external
interrupt
Disable external
interrupt
Select register bank 0
Select register bank 1
Select memory bank 0
Select memory bank 1
Enable clock output
onTO

Bytes Cycles
1
1

Description
No operation
Select Idle Operation

Bytes Cycles
1
1
1

Control
Mnemonic
EN I

DISI

2
2

SElRBO
SEl RBl
SEl MBO
SEl MBl
ENTO ClK

Mnemonic
NOP
IDl

15-10

8048AH/8035AHl/8049AH
8039AHLl8050AH/8040AHL

ABSOLUTE MAXIMUM RATINGS·

'NO neE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damageto the device. This is a stress rating only' and
functional operation of device at these or any other
conditions above those indicated in the operational
sections of this specification is not i,!,plied.

Ambient Temperature Under Bias ... 0° C to 70° C
Storage Temperature .......... -65°C to +150°C
Voltage On Any Pin With Respect
to Ground ..................... -0.5V to +7V
Power Dissipation ..................... 1.5 Watt

D.C. CHARACTERISTICS: (TA

=O°C to 70°C; VCC =VDD =5V ± 10%; VSS =OV)
Limits

Symbol

Parameter

Min

VIL

Input Low Voltage (All
Except RESET, X1, X2)

VIL1

Inp~

Low Voltage
(RE ET, X1, X2)

VIH

Input High Voltage
(All Except XTAL 1,
XTAL2, RESET)

VIH1

Input High Voltage
(X1, X2, RESET)

Typ

Test Conditions

Device

Max

Unit

-.5

All

-5

All

2.0

VCC

- All

3.8

VCC

All

VOL

Output Low Voltage
(BUS)

.45

10L

=2.0 mA

All

VOL1

Output Low Voltage
(RD, WR, PSEN, ALE)

.45

IOL

= 1.8 mA

All

VOL2

Output Low Voltage
(PROG)

.45

IOL

= 1.0 mA

All

VOL3

Output Low Voltage
(All Other Outputs)

.45

IOL

= 1.6 mA

All

VOH

Output High Voltage
(BUS)

2.4

IOH

=-400 p.A

All

VOH1

Output High Voltage
(RD, WR, PSEN, ALE)

2.4

IOH

=-100 p.A

All

VOH2

Output High Voltage
(All Other Outputs)

2.4

IOH

=-40 p.A

All

15-11

8048AH/8035AHLl8049AH
8039AHL/8050AH/8040AHL

D.C. CHARACTER.lSTICS: (TA

= O°C to 70°C; VCC = VOO = SV

± 100;",; VSS

= OV) (Continued)

Limits
Symbol

Max

Unit

(T1,INT)

±10

JJA

VSS,;;;VIN';;;VCC

All

Input Leakage Current
(P10·P17, P20·P27,
EA, SS)

-SOO

VSS + .4S,;;;VIN';;;VCC

All

300

/LA

VSS,;;;VIN,;;;3.8V

All

±10

JJA

VSS,,;;VIN";;VCC

All

8048AH
8035AHL

8049AH
8039AHL

80S0AH
8040AHL

rnA

8048AH
8035AHL

8049AH
8039AHL

80S0AH
8040AHL

S.S

Parameter

1L1

Leak~

IU1

IU2

Input Leakage Current
RESET

ILO

100

100+
ICC

VOO

.Mln

Typ

Test Conditions

Device

Current

Leakage Current
(BUS, TO) (High
Impedance State
VOO Supply Current
(RAM Standby)

Total Supply Current"

RAM Standby Voltage'

2.2

Standby Mode Reset
,;;;VIL1

All

"ICC + 100 is measured with all outputs disconnected; SS, RESET, and INT equal to VCC; EA equal to
VSS·
.

15·12

inter

8048AH/8035AHL/8049AH
8039AHL/8050AH/8040AHL

A.C. CHARACTERISTICS: (TA = 0 0 C to 70 0 C; VCC = VOO = 5V ± 10%; VSS = OV)

Parameler

Symbol
t

Clock Period

tLL

ALE Pulse Width

tAL

Addr Setup to ALE

tLA

Addr Hold from ALE

tCC1

Control Pulse Width (Rl5, WR)

tCC2

Control Pulse Width (PSEN)

tow

Data Setup before WR

two

Data Hold after WR

11 MHz

I (I)
(Note 3)

Min

Max

Unl"

Condilions
(Nole 1)

1/xtal freq

90.9

1000

(Note 3)

3.5t-170

150

2t-110

(~!ote

t-40

7.5t-200

480

6t-200

350

6.5t-200

390

t-50

tOR

Data Hold (RD, PSEN)

1.5t-30

tRD1

RD to Data in ,

6t-170

tRD2

PSEN to Data in

4.5t-170

tAW

Addr Setup to WR

tAD1

Addr Setup to Data (RD)

10,5t-220

730

tAD2

Addr Setup to Data (PSEN)

7.5t-200

460

tAFC1

Addr Float to RD, WR

2t-40

140

(Note 2)

tAFC2

Addr Float to PSEN

.5t-40

(Note 2)

tLAFC1

ALE to Control (RD, WR)

3t-75

290

ns
ns

5t-150

ns
110

375

240

ns
ns

300

tLAFC2

ALE to Control (PSEN)

1,5t-75

tCA1

Control to ALE (RD, WR, PROG),

t-65

tCA2

Control to ALE (PSEN)

4t-70

290

1.5t-80

4t-260

100

tcp

, Port Control Setup to PROG

tpc

Port Control Hold to PROG

tpR

PROG to P2 Input Valid

tpF

Input Data Hold from PROG

top
tpo
tpp

PROG Pulse Width

tpL

8.51-120

ns
650

140

1,51

Output Data Setup

6t-290

250

Output Data Hold

1,5t-90

1O.5t-250

700

Port 2 I/O Setup to ALE

4t-200

160

tLP

Port 2 I/O Hold to ALE

.51-30

tpv

Port Output from ALE

4,5t+100

tOPRR

TO Rep Rate

270

tCY

Cycle Time

15t

1.36

ns
5~0

15.0

jJ.S

Notes:
1 Control Outputs CL = 80pF
BUS Outputs CL = lSOpF

2, BUS HIgh Impedance
Load 20pF

15-13

3. I(t) assumes SO% duty cycle on Xl, X2, Max
clock penod IS lor a 1 MHz crystal input.

8048AH/8035AHL/8049AH
8039AHL/S050AH/S040AI-IL

WAVEFORMS
--JtLAFC1L

Jr---"'L-I__

ALE

_ _ _- - - - '

tCA11RD

PSEN

Read From External Data Memory
ALE

L
r---

2.4V - - - - - - ,
0.4SV _ _ _

~X;·~; TEST POINTS::~:~X,--_ __

ADDRESS

A C testing Inputs are driven at 2 4V for a logic "1" and
measurements are
made at 2 OV for a logic "1" and 0 8V for a logic "0 .'

o 45V for a logic "0 " Output timing

Input And Output For A.C. Tests

PORT 1/PORT 2 TIMING
1ST CYCLE

2ND
CYCLE

ALE
PSEN

P24-27
P10-17
OUTPUT

PCH

NEW P20-23 DATA

P9RT 20-23 DATA

'----------c,

~r-----~---P-O-R-T-2-4_-27-,-P-O-RT--10-_-17-D-A-T-A~r-------~----~

tLP
EXPANDER
PORT
OUTPUT

PCH

NEW PORT DATA
I

--------l
-1+---.. tLA---·+I·--tPL~
PCH

r-:-

I ,-------11

r-----,

ItPD

tDP

OUTPUT DATA

' - -_ _ _ _ _ _ _ _ _ _- J

EXPANDER
PORT
INPUT

P20-23
OUTPUT

f+-----tPR

r----~-----,

----I·~I

PCH

PROG

15-14

It)

r------,

"I .

tCA 1

S04SAH/8035AHL/S049AH
S039AHLlS050AH/S040AHL

inter

CRYSTAL OSCILLATOR MODE

CERAMIC RESONATOR MODE
Cl
f-_ _ _ _---'_ _ _2-l XTALl

~.~._'

f-_---r _ _---._ _._-2 j XTAL 1

~:.:

,..,--...1----------,:-1 XTAL2
C3

...

XTAL2
3

C1 ' 5pF ± 1/2pF + (STRAY < 5pF)
C2 ' (CRYSTAL + STRAY) < 8pF
C3 ' 20pF ± 1pF + (STRAY < 5pF)

Crystal series resistance should be less than 30n at 11 MHz;
less than 75!l at 6 MHz; less than lOOn at 3.6 MHz.

DRIVING FROM EXTERNAL SOURCE
+5V

47011

p-+___-.:2:.j XTAL1
+5V

TTL OPEN

COLLECTOR
GATES

47011
'--_...1-_~

For XTAL 1 and XTAL2 deline "high" as voltages above 1.6V
and "low" as voltages below 1.6V. The duty cycle requirements lor externally driving XTAL 1 and XTAL2 using the

XTAL2

circuit shown above are as follows: XTAL 1 must be high 3565% 01 the period and.XTAL2 must be high 36-65% 01 the
period. Rise and fall times must be faster than 20 nS.

15-15

8048AH/8035AHL!8049AH
8039AHL!8050AH/8040AHL

SUGGESTED ROM VERIFICATION ALGORITHM FOR H-MOS DEVICE ONLY
INITIAL ROM DUMP CYCLE

SUBSEQUENT ROM DUMP CYCLES

ALE
(NOTE 1)

!(OUTPUT)
+12V

j
I

: (INPUT)

EA----.J

I
I

A_D~D~R-ES~S--~r1r~R=OM~D~AT~A~~L---AD_D_R_E~S_S~~~------------__

DB-------L__

(INPUT)

(OUTPUT)

--1r-------------i!

RESET _________

(INPUT)

(OUTPUT) :

(INPUT)

I,...:_ _ _ _ _ _ _ _ _ _ _ _ __

-4H'--_____

i._______A_D_D_R_ES_S______

P211-P23 _____

AD_D_R_E_S_S____

~I--------------

I (INPUT)
I

Al0
All

NOTE: ALE is function of Xl, X2 inputs.

15-16

VCC

=VDD =+ 5V

VSS

=OV

8748H/8035H/8749H/8039H
HMOS-E SINGLE-COMPONENT 8-BIT MICROCOMPUTER
•
•
•
•
•

• Compatible with 8080/8085
Peripherals

High Performance HMOS-E
Interval Timer/Event Counter
Two Single Level Interrupts
Single 5-Volt Supply
Over 96 Instruc~lo~s;
90% Single Byte

• Easily Expandable Memory and I/O
• Up to 1.35 pSec Instruction Cycle
All Instructions 1 or 2 cycles

The Intel S749H/S039H/S74SH/S035H are totally self-sufficient, S-bit parallel computers fabricated on single
silicon chips using Intel's advanced N-channel silicon gate HMOS-E process.
The family contains 27 1/0 lines, an 8-bit timer/counter, on-chip RAM and on-board oscillator/clock circuits. For
systems that require extra capability, the family can be expanded using MCSiBl-SO/MCSiBl-S5 peripherals.
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program
memory results from an instruction set consisting mostly of single byte instructions and no instructions over 2
bytes in length.
Internal Memory

Device

, 12S x S RAM

S039H·

none

S035H

none

S749H

2Kx S EPROM

12SxS RAM

S74SH

1Kx S EPROM

64xSRAM

8748H
8035H
8749H
8039H

Vee

P~RT XTA~~
XTAL 2
RESET
PORT
2

INT
EA

RD
PSEN
WR
ALE
DBO
DBl
DB2
DB3
DB4
DBS
DB6
DB7

Vss '--_ _-'
Figure 1.
Block Diagram

Figure 2.
Logic Symbol

15-17

T1
P27
P26
P2S
P24
P17
P16
P15
P14
P13
P12
Pll
Pl0
VDD
PROG
P23
P22
P21
P20

Figure 3..
Pin Configuration

~1F\l~Il.~M~INIAlF\lif

8748H18035H/8749H/8039H

,',I

Table 1. Pin DescrlpUon

Symbol

Pin'
No.

VSS

VOO

Function

'Circuit GNO.. ·
potential
+5V during
normal operation.
P~ogrammlng

power supply
(+21V),
VCC

PROG

P10-P17 27-34
Port 1
P20-P23 21-24
P24-P27 35-38
Port 2

OBOOB7
BUS

12-19

Main power
supply; +5V during operation and
programming.
Output strobe
for 8243
I/O expander.
Program pulse
(+18V) input pin
during
programming.
8-bit quasibidirectional port.
8-bit quasibidirectional port.
P20-P23 contain
the four high
order program
counter bits during an external
program memory
fetch and serve
as a 4-bit I/O
expander bus
for 8243.
True bidirectional
port which can be
written or read
synchronously
using the RO, WR
strobes. The port
'clin also be
static~lIy latched.

Symbol

Device

. Pin
No.

(Con't)

All
All
8748H
8749H
All

All

8748H
8749H
(See Note)

All
All

INT

All.

15-18

Function

Contains the 8
low order program counter bits
during an external
program memory
fetch, and
receives the
addressed instruction under
the control of
PSEN. Also contains the address
and data during
an external RAM
data store instruction, under.
c.ontrol of ALE,
RO, and WR.
Input pin testable
using the conditional transfer
instructions JTO
.and JNTO. TO can
be designated as
a clock output
using ENTO CLK
instruction
Used during
programming.
Input pin testable
using the JT1,
and JNT1 instructions. Can be designated the timer/
counter input
using the STRT
CNT instruction.
Interrupt input.
Initiates an interrupt if interrupt is
enabled. Interrupt
is disabled after a
reset. Also testable
with conditional
jump instruction.
(Active low) interrupt must remain
low for at least 3
machine cycles
for proper
operation.

Device

All

8748H
8749H
All

All

inter

8748H/8035H/8749H/8039H

Table 1. Pin Description (Continued)

Symbol

Pin
No.

Function

Output strobe
activated during
a BUS read. Can
be used to enable
data onto the bus
from an external
device.

Symbol

Device

All

Used as a read
strobe to external
data memory.
(Active low)
RESET

Input which is
used to initialize
the processor.
(Active low)
(Non TTL VIH)

Ail

Used during
programming.

874BH
8749H

Output strobe
during a bus
write. (Active low)

All

Pin
No.

Address latch
enable. ThiS signal occurs once
dunng each cycle
and is useful as
a clock output.
The negative edge
of ALE strobes
address into
external data and
program memory

Device

Program store
enable. This output occurs only
during a fetch to
external program memory.
(Active low)

ALL

Single step input
can be used in
conjunction with
ALE to "single
step" the processor through each
Instruction.

All

E;xternal access
Input which
forces all program memory
fetches to reference external
memory. Useful
for emulation
and debug.
(Active high)

All

Used during
(18V)
programming

8748H
8749H

Used as write
strobe to external
data memory.
ALE

Function

PSEN

All
XTAL1

One side of
crystal input for
internal oscillator.
Also input for
external source.
(Non TTL VI H)

All

XTAL2

Other side of
crystal Input

All

NOTE: On the 8749H!8039H, PROG must be clamped to
Vee when not programming. A diode should be used when
using an 8243; otherwise, a direct connection is permissible.

15-19

inter

8748H/8035H/8749H18039H

. Table 2, Instruction Set
Accumulator

ReglBl.,.

Mnemonic
ADD A, R
ADDA,@R
ADD A, It data
AD DC A, R
ADDCA,@R

Mnemonic
INCR
INC@R
DECR

Description
Bytes Cycles
Add register.to A
1
1
Add data memory to A
1
1
Add immediate to A
2
2
Add register with carry
Add data memory
with carry
AD DC A, It data Add immediate
2
2
with carry
ANLA,R
And register to A
ANLA,@R
And data memory to A
1
1
ANLA,It data
And immedIate to A
2
2
ORLA, R
Or register to A
ORLA@R
Or data memory to A
1
1
ORLA,ltdata
Or Immediate to A
2
2
XRLA, R
Exclusive or register
toA
XRLA,@R
Exclusive or data
memory to A
XRL, A, It d,ata
ExclusIve or
2
2
immediate to A
INCA
IncrementA
DECA
Decrement A
CLRA
Clear A
CPLA
Complement A
DAA
Decimal adjust A
SWAP A
Swap nibbles of A
RLA
Rotate A left
RLCA
Rotate A left
through carry
RRA
Rotate A right
RRCA
Rotate A right
through carry

Branch
Mnemonic
JMPaddr
JMPP@A
DJNZ R, addr
JC addr
JNCaddr
JZaddr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JFO addr
JF1 addr
JTF addr
JNI addr
JBb addr

Description
Jump unconditional
Jump indirect
Decrement register
and skip
Jump on carry = 1
Jump on carry = 0
Jump on A zero
Jump on A not zero
Jump on TO=: 1
Jump on TO =
Jump on T1 = 1
Jump on T1 =0
Jump on FO = 1
Jump on Fl = 1
Jump on timer flag
Jump 9n INT = 0
Jump on accumulator
bit

Byte. Cycles
2
2
1
2
2
2

2
2
2
2
2
2
2
2
2
2
2
2
2

Subroutine
Mnemonic
CALLaddr
RET
RETR

Input/Output
Mnemonic
Description
Bytes Cycles
INA,P
Input port to A
1
2
OUTL.P, A
Output A to port
1
2
ANL P,ltdata
And Immediate to port
2
2
ORL P, It data
Or Immediate to port
2
2
INSA, BUS
Input BUS to A
1
2
OUTLBUS, A
Output A to BUS
1
2
ANL BUS, It data And immediate to BUS
2
2
ORL BUS, It data Or immediate to BUS
2
2
MOVDA, P
Input expander port
1
2
to Pi
MOVDP, A
Output A to expander
1
2
port
ANLD P,A
And A to expander port
1
2
ORLD P,A
Or A to expander port
1
2

Description
Bytes Cyc'"
Increment register
1
1
1
Increment data memory
1
Decrement register

Description
Jump to subroutine
Return
Return and restore
status

' Bytel Cycles

Description
Clear carry
Complement carry
Clear flag 0
Complement flag 0
Clear flag 1
Complement flag 1

Bytes Cyc'"
1
1

2
·1

2
2
2

Flagl
Mnemonic
CLRC
CPLC
CLR FO
CPLFO
'CLR F1
CPLF1

15-20

inter

~1P.l~LO~OINlfA\IRlW

8748H/8035HI8749H.t8039H

Table 2. Inltructlon Set (Continued)
DetaM_
Dncrlptlon
Move register to A
Move data memory
toA
MOV A. # data Move immediate to A
MOVR.A
Move A to register
Move A to data
MOV@R.A
memory
MOV R.#data Move immediate
to register
MOV @R. # data Move immediate to
data memory
MOVA.PSW
MovePSWtoA
MOVPSW.A
Move A to PSW
Exchange A and
XCHA. R
register
XCHA.@R
Exchange A and
data memory
XCHDA.@R
Exchange nibble of A
and register
MOVXA.@R
Move external data
memory to A
MOVX@R.A
Move A to external
. data memory
MOVPA.@A
Move to A from
current page
MOVP3A.@A Move to A from page 3
Mnemonic
MOVA,R
MOVA.@R

Timer/Counter
Byt.s Cycles
1
1

Mnemonic
MOVA. T
MOVT.A
STRTT
STRTCNT
STOP TCNT
EN TCNTI
DIS TCNTI

Dncrlptlon
Read timer/counter
Load timer/counter
Start timer
Start counter
Stop timer/counter
Enable timer/counter
interrupt
Disable timer/counter
interrupt

Bytes Cycl..
1
1

Description
Enable external
interrupt
Disable external
interrupt
Select register bank 0
Select register bank 1
Select memory bank 0
Select memory bank 1
Enable clock output
onTO

Bytes Cycles
1
1

Description
No operation

Bytes Cycles
1
1

Control
Mnemonic
ENI

,,1

0151

SELRBO
SELRB1
SELMBO
SEL MB1
ENTOCLK

2
2
2

,2
Mnemonic
NOP

15-21

. 8T48H/8035H/8749H/8,039H

ABSOLUTE MAXIMUM RATINGS·'
.Ambient Temperature Under Bias ••• ooe to 70 0 e
Storage Temperature ....••.... -65°e to +150oe
.
Voltage On Any Pin With Respect
to Ground ............•.•..•... -O.5Vto +7V
Power Dissipation .•...• : . • . . . . . . . • • .• 1.0 Watt

"NO fleE: Stresses abov~ those listed under "Abso. lute Maximum Ratings" maypause permanent "amage to the device. This is a stress rating only and
functional operation of device at these or any other
.conditions above those indicated in the operational
sections of this specification is not implied.

D.C. CHARACTERISTICS: (TA = 0° C to 70 Q e; Vee = VDD = 5V ± 10°1p; VSS = OV)
Limits
Symbol

Parameter

Min

VIL

Input Low Voltage (All
Except RESET, X1, X2)

VIL1
VIH

Typ

Unit

-.5

All

Input Low Voltage
(RESET, X1, X2)

-.5

All

Input High Voltage
(All Except XTAL 1,
XTAL2, RESET)

2.0

Vee

All

VIH1

Input High Voltage
(X1, X2, RESET)

3.8

Vee

All

VOL

Output Low Voltage
(BUS)

.45

IOL = 2.0 mA

All

VOL1

Output Low Voltage
(RD, WR, PSEN, ALE)

.45

IOL =1.8 mA

All

VOL2

Output Low Voltage
(PROG)

.45

IOL = 1.0 mA

All

VOL3

Output Low Voltage
(All Other Outputs)

.45

IOL = 1.6 mA

All

VOH

Output High Voltage
(BUS)

2.4

IOH = -400 IlA

All

VOH1

Output High Voltage
(RD, WR, PSEN, ALE)

2.4

IOH = -100yA

All

VOH2

Output High Voltage
(All Other Outputs)

2.4

IOH = -40 IlA

All

15·22

Test Conditions

Device

Max

inter

8748H/8035H/8749H/8039H

D.C. CHARACTERISTICS: (TA

=O°C to 70°C; VCC =VOO =5V ± 10%; VSS =OV) (Continued)
Limits
Max

Unit

1L1

Leakage Current
(T1, INT)

±10

VSS,,;;VIN";;VCC

All

ILI1

Input Leakage Current
(P10-P17, P20-P27,
EA,85)

-500

VSS + .45,,;;VIN";;VCC

All

-300

VSS,,;;VIN,,;;3.8V

All

VSS,,;;VIN";;VCC

!)ymbol

Parameter

Input Leakage Current
RESET

·ILl2
ILO

Leakage Current
(BUS, TO) (High
Impedance State)

100 +
ICC

Total Supply Current"

*Iec

Min

Typ

-10

Test Conditions

Device

,.
±10

100

rnA

8035H

110

rnA

8039H

100

rnA

8748H

110

rnA

8749H

IDD is measured with all outputs disconnected; SS, RESET, and INT equal to Vee; EA equal to VSS.

15-23

All

8748H/8035H/8749H/8039H

A.C. CHARACTERISTICS: (TA

Symbol

=0°8 10 70°C;, VCC =VOO =5V ± 10%; VSS =OV),

Parameter

Clock Period

tLL

ALE Pulse Width

tAL

Addr Setup to ALE

tLA

Addr. Hold from ALE

tCC1

Control Pulse WidtlJ (RO. WR)

tCC2

Control Pulse Width (PSEN)

tow

Data Setup before WR

two

Data Hold after WR

11 MHz

f(t)
(Note 3)

Min

Max

Unit

Conditions
(Note 1)

1/xlal freq

90.9

1000

(Note 3)

3.5t-170

150'

2t-110

t-40

7.5t-200

480

6t-2oo

350

6.5t-200

390

t-50

(Note 2)

tOR

Data Hold (RD. PSEN,)

1.5t-30

110

tRD1

RD to Data in

6t-170

375

tRD2

PSEN to Data in

4.5t-170

240

tAW

Addr Setup to WR

tAD1

Addr Setup to Data (RD)

10.5t-g2,0

730

tAD2

Addr Setup to Data (PSEN)

7.5t-200

460

tAFC1

Addr Float to RD. WR

2t-40

140

(Note 2)

tAFC2

Addr Float to PSEN

.5t-40

(Note 2)

tLAFC1

ALE to Control (RD. WR)

3t-75

200

5t-150

300

tLAFC2

ALE to Control (PSEN)

1.5t-75

tCA1

Control to ALE (RD. WR. PROG)

1-65

tCA2

Control to ALE (PSEN)

41-70

290

tcp

Port Control Setup to PROG

1.5t-80

tpc

Port Control Hold to PROG

4t-260

100

tpR

PROG to P2 Input Valid

tpF

Input Data Hold from PROG

8.5t-120

ns
650

140

1.5t

tDP

Output Data Setup

6t-290

250

tpD

Output Data Hold

1.5t-90

tpp

PROG Pulse Width

10.5t-250

700

tpL

Port 2 1/0 Setup to ALE

4t-200

160

tLP

Port 2 1/0 Hold to ALE

.5t-30

tpv

Port Output from .ALE

4.5t+100

tOPRR

TO Rep Rate

270

tCY

Cycle Time

15t

1.36

ns
510

15.0

j.lS

Notes:
1. Control Outputs CL = 80pF
BUS Outputs CL = 150pF

2. BUS High Impedance
Load 20pF

15-24

3. f(t) assumes 50% duty cycle on Xl, X2. Max
clock period is for a 1 MHz crystal input.

inter

8748H/8035H/8749H/8039H

WAVEFORMS

ALE
ICAl

1--

Read From External Data Memory
ALE

L
2.4V - - - - - - - ,

,--_ __

... 2.0X
X 2.0~TEST POINTS -'0.8.
'-._ __

0.45V-----'. . O.S'"

A.C. testing Inputs are driven at 2 4V for a logic "1" and
0.45V for a logic "0." Output timing measurements are
made at 2 OV for a logiC "1" and 0.8V for a logic "0,"

Write To External Data Memory

Input And Output For A.C. Tests

PORT 1/PORT 2 TIMING

ALE
PSEN

P20-23
OUTPUT

PCH

NEW P20-23 DATA
I
~---------~I

P<;lRT 20-23 DATA

P24-27
-+------~------------------7-----~--~
Pl0-17
PORT 24-27. PORT 10-17 DATA
OUTPUT

NEW PORT DATA
I

---1.

ILP
EXPANDER
PORT
OUTPUT

---1..'-L':...
---·+I"·-IPL~
PCH

I rp-O-RT-2-0--2-3-D-A-TA--;',

'PORT CONTROL

IDP

T -I'

OUTPUT DATA

INPUT

1-+-14

r-------~

PCH

r~--~

I-ICP+IPC~
PROG

I,
I'PF I
I
_ I P R _ - - - I _ I f1
IPORT CONTROL I

!-ICAl

IIPD

~--------------~

EXPANDER
PORT

- - - - - - - - - - - - - - -_____-;1

1\.

15-25

PCH

I
'PP

intJ

8748H/8036H/8749H/8039H

CERAMIC RESONATOR MODE

CRYSTAL OSCILLATOR MODE

C1 .
2
- - - - r - - - - . - - - - - - i XTAL 1

~ 'e'o"f~,
-=-

-=-

I-{_ _ _ _ _-r-_ _2-j XTAL1

C1 = C2 = 33pF ± 5%

1-11

~HZ

XTAL2

l - - - - ' - - - - J - - - - , 1 XTAL2

,C1 = 5pF ± 1/2pF + (STRAY < 5pF)
C2 = (CRYSTAL + STRAY) < 8pF
C3 = 20pF ± 1pF + (STRAY < 5pF)

Crystal series resistance should be lessl than 30!! at 11 MHz;
less than 7S!! at 16 MHz; less than 180!! at 3.6 MHz.

DRIVING FROM EXTERNAL SOURCE
+5V

47011

~--t-----i

XTAL 1

+5V'

TTL OpeN
COLLeCTOR
GATES

47011

'-----'----:;;-i3 XTAL2

For XTAL 1 and XTAL2 define "high" as voltages above 1.6V
and "low" as voltages below 1.6V. The duty cycle requirements for externally dnving XTAL1 and XTAL2 uSing the

circuit shown above are as follows:XTAL1 must be high 3S'6S% of the period andXTAL2 must be high 36-6S% of the
period. Rise and fall times must be faster than 20 nS.

PROGRAMMING, VERIFYING, AND
ERASING THE 8749H (8748H) EPROM
Programming Verification
In brief, the programmrng processconsists of: activating the program mode, applying an address,
latching the address, applying data, and applying a
programming pulse. Each word is programmed
completely before moving on to the nexJ and is
followed by a verification step. The following is a
list of the pins used for programming and a description of their functions:

Pin,
XTAL 1
XTAL 2
Reset
Test 0
EA
BUS
P20-P22
VDD
PROG

Function
Clock Input (3 to 4.0 MHz)

WARNING:
An attempt to program a missocketed 8749H (8748H) will
result In severe damage to the part. An indication of a
properly socketed part IS the appearance of the ALE clock
output The lack of thiS clock may be used to disable the
programmer
The ProgramlVerify sequence IS'
1 VOO = SV, Clock applied or Internal oscillator operatIng. RESET =OV, TEST 0 =SV, EA =SV, BUS and
PROG'floatlng P10 and P11 must be lied to ground.
2, Insert 8749H (8748H) In programming socket.
3. TEST 0 = OV (select program mode)
4 EA = 18V (activate progral)1 mode)
S. Address applied to BUS and P20-22
6. RESET = SV (Iatcll address)
7 Data applied to BUS
8. VOO = 21V (programming power)
9. PROG = VCC or float followed by one SOms pulse
to 18V

1I1itialization and Address Latching
,Selection of Program or Verify Mode
Activation of Progrl\mNerify Modes
Address and Data Input
Data Output During Verify
Address Input
Programl1)ing Power Supply
Program Pulse Input

10
11.
12
13,

VOO= SV
TEST 0 = SV (venfy mode)
Read and venfy data on BUS
TEST 0 = OV

14, RESET" OV and repeat from step S
1S. Programmer should be at conditions of step 1 when
8749H (8748H) IS removed from socket.

15-26

8748H/8035H/8749H/8039H

A.C. TIMING SPECIFICATION FOR PROGRAMMING 8748H/8749H ONLY:
(TA

=25°e ± 5°e; Vee =5V ± 5%; Voo =21 ± .5V)

Symbol

Parameter

Min

Max

Unit

tAW

Address Setup Time to ~I

4tCY

tWA

Address Hold Time After ~I

4tCY

tow

Data in Setup Time to PROGI

4tCY

two

Data in Hold Time After PROGI

4tCY

tPH

RESEi Hold Time to Verify

4tCY

tVOOW

VOO Hold Time Before PROGI

1.0

tVOOH

VOO Hold Time After PROGI

1.0

tpw

Program Pulse Width

tTW

Test 0 Setup Time for Program Mode

4tCY

tWT

Test 0 Hold Time After Program Mode

4tCY

too

Test 0 to Data Out Delay

tww

l1ES"E'f Pulse Width to Latch Address

t r • tf

VOO and PROG Rise and Fall Times

4tCY .
0.5

100

j.!s

CPU Operation Cycle Time

3.75

tRE

RESET Setup Time before EAt

4tCY

tCY

NOTE: If Test 0

Test Conditions

high. too can be triggered by RESET!

D.C. TIMING SPECIFICATION FOR PROGRAMMING 8748H/8749H ONLY:
(TA = 25°C ± 5°C; Vee" 5V ± 5%; VOO" 21 ± .5V)
Symbol

Min

Max

Unit

VOOH

VOO Program Voltage High Level

Parameter

20.5

21.5

VOOL

VOO Voltage Low Level

4.75

5.25

VPH

PROG Program Voltage High Level

17.5

18.5

VPL

PROG Voltage Low Level

4.0

VCC

VEAH

EA Program or Verify Voltage High Level

,17.5

18.5

'DO

VOO High Voltage Supply Current

20.0

'pROG

PROG High Voltage Supply Current

1.0

lEA

EA High Voltage Supply Current

1.0

15-27

Test Conditions

8748H/8035H/8749Hf8039H

WAVEFORMS
COMBINATION PROGRAM/VERIFY MODE (EPROM'S ONLY)
VEAH_

!~tRE)lr--------------,-------------------------------------------I

EA
Vee

L
--'PROGRAM ---~----I---VERIFY -----j----PROGRAMl==-tTW~-I'
1

Vee

VIL 1

i--c -- tww _ _ I
r----------------------+----------~

Vee
RESET
VILl

tAWr--~twA
r-~D-AT~A~T~O~BE~~

DBO-DB7 ~ - -

__ -

wchart-Unnumbered Poll

18-17

RUPI~-44

"AM" .-0
"SI" 4-1
·'RBE" .... O
"SER"..,.O
"SES" ... 1

"SI" 4--1
"NS" = NS + 1

..SES" .... O
..SER" .... O

"TBF""'O

Figure 18-7d. SIU AUTO Mode Receive Flowchart-Supervisory Command

18-18

RUPI"'-44

BAD

I COMMAND
NR(P) = NS(S)
NS(P) = NR(S)

"AM"

"NS"

1
=

"ABE" ..... ",
"TBF" ..... \II
Ns~Ns+1

"SES"'" e
"SER".... \II
"51" .... 1

Figlclr.e 18-7e. SIU AUTO Mode Receive Flowchart...,.1 Command: Prior Transmitted I-Field Confirmed,
Current Received I-Field in Sequence

18-19

BAD

I COMMAND

NoIP' ~ Ns(S,
NsIP' - NoIS,

"AM"

1, "Na"

= •

"RBE"..-(t
"SES" ... .

"SER" ... .
"SI" ... 1

Figure 18-7f. SIU AUTO Mode Receive Flowchart":"l Command: Prior Transmitted I·Field Not
Confirmed, Current Received I·Field'Jn Sequence

18-20

BAD

I.cOMMAND
NA(P)
NS(S) + 1
NA(P) *- NS(S)
NS(P) ~ NR(S)
"AM" = 1,
"NB" = 0

"AM" ... ,
.. SES" ...... 1
"SER ........ O
·'RSE" .... O
"SI"

.... 1

Figure 18-1g. $IU AUTO Mode Receive Flowchli/Ft-I Command: Sequence Error Send, Current
Received I-Field in Sequence

18-21

RUP1 1loI;'44

~AD

I COMMAND
NR(P) ~ Ns(S)
NS(P) ¢ NA(S)

+ 1

"AM" = 1 "Na" = 0

"TBF" ..... "
Ns=Ns+1
"SES" ... ,

"SER"-..1
"SI"

..... 1

Figure 18-7h. SIU A,UTO Mode Receive Flowchart-I Command: Prior Transmitted I-Field Confirmed
Sequence Error Receive

18-22

BAD

I COMMAND
NA(P) = NS(S)

~::), :: ~~(S) "NB" =

"BOV" .... 1
"AM" .... ,

"AM" .... ,

"RBE".,

"RBE" ... ,
"51" ... 1

.... 1

Figure 18-7i. SIU AUTO Mode Receive Flowchart-I Command: Prior Transmitted I·Field Not
"
Confirmed, Sequence Error Receive

18-23

BAD

,I COMMAND

1, "NB"

NR(P) ~ NS(S)

~~l~l :: ~=l~l

"AM"

"AM" .......

"RBE"",

"SES" ..... 1
"SER".-1
"SI" .... 1

Figure 18-7j. SIU SU10 Mode Receive Flowchart-I Command: Sequence Error Send and Sequence
Error Receive

18-24

RUPI"'-44

-0

YES

X MIT
I

FRAME

X MIT

FRAME

Figure 18-8. SIU AUTO Mode Transmit Flowchart

18-25

RNR

LOAD I·FIELD
INTO
XMITBUFFER

PROCESS
INFORMATION
OR
SET "RBP"

Figure 18-9. AUtO Mode Response to "SI"

18-26

-----1

1
1
YES

ABORT,
SHORT FRAME
OR INVALID I

BAD

RECEIVE MESSAGE

CTAL FIELD ~RCB.
I FIELD -.REC BUF,
seT BOV ON OVERRUN

- - - i1

RBE
0
(ABORT FROM CPU)

TEST

cRe

Figure 18-10. SIU FLEXIBLE Mode Receive Flowchart

18-27

RU PI 1'...44

Figure 18-11. FLEXIBLE Mode Response to Recei.ve "SI"

r - -

,I
I

TRANSMIT MESSAGE
USING TCB FOR
CONTROL FIELD

-;-BF--=-'- - -

~UT-OFF • LOOP) +
CTS·LOOP
[ABORT FROM PRIMARY]

(ABORT FROM CPU)

CLEAR "TBF"

----,

I
I
I
I
I

'}..:..~!.,.1-~----::::::::::;:J:;:'-=-::::: ______ J

CLEAR "RTS"
SET "SI"
TRANSMIT
ABORT
SEQUENCE

Figure 18-1/!. SIU ,FLIiXIBLE Mode Transmit Flowchart

18-29

RUPI""-44

XMIT

== 1, PENDING

BUFFULL

BUFEMPTY

CTRL FIELO ....TCB
l-fIELD ... XMIT aUF
SET "TBF"
SET "RTS"

Figure 18-13. FLEXIBLE Mode Response to Transmit

"sr'

8044 to get its transmit buffedoaded with new information after an acknowledge.
.3) The 8044 CPU can clear R TS. This will prevent a response from being sent, or abort it if it is already in
progress. A system using external RTS/CTS handshaking could use a one-shot to delay RTS or CTS,
thereby giving the CPU more time to disable the
response.

18.9 MORE DETAILS ON SIU HARDWARE
The SIU divides functionally into two sections-a bit
processor (BIP) and a byte processor (BYP)-sharing
some common timing and control logic. As shown in
Figure 18-14, the BIP operates between the serial port
pins and the SIU bus, and performs all functions
.necessary to transmit/receive a byte of data to/from
the serial data stream. These operations include shifting, NRZI encoding/decoding, zero insertion/deletion,
and FCS generation/checking. The BYP manipulates
bytes of data to perform message formatting, and other
transmitting and receiving functions. It operates between the SIU bus (SIB) and the 8044'5 internal bus (lB).
The interface between the SIU and the CPU involves
an interrupt and some locations in on-chip RAM space
which are managed by the BYP.
The maximum possible data rate for the serial port is
limited to 1/2 the internal clock rate. This limit is imposed by both the maximum rate ofDMA to the on-chip
'RAM, and by the requirements of synchronizing to an
external clock. The internal clock rate for an 8044 running on a 12 MHz crystal is 6 MHz. Thus the maximum
8044 serial data rate is 3 MHz. This data rate drops
down to 2.4 MHz when time is allowed for external
clock synchronization.

adjustment is made if the transition occurs at the count
of 8. In this manner the counter locks in on the point at
which transitions in the data stream occur at the count
of 8, and a clock pulse is generated when the count overflows to O.
In order to perform NRZI decoding, the NRZI decoder
compares each bit of input data to the previous bit.
There are no clock delays in going through the NRZI
decoder.
The zero insert/delete circuitry (ZID) performs zero insertion/deletion, and also detects flags, GA's (GoAhead's), and aborts (same as GA's) in the data stream.
The pattern 1111110 is detected as an early GA, so that
the GA may be turned into a flag for loop mode
transmission.
The shut-off detector monitors the receive data stream
for a sequence of eight zeros, which is a shut-off command for loop tnode transmissions. The shut-off detector
is a three-bit counter which is cleared whenever a one is
found in the receive data stream. Note that the ZID logic could not be used for this purpose, because the receive
data must be monitored even when the ZID is being used
'for transmission.
As an example of the operation of the bit processor, the
following sequence occurs in relation to the receive data:
I) RXD is sampled by SCLK, and then synchronized to
the internal processor clock (IPC).
2) If the NRZI mode is selected, the incoming data is
NRZI decoded.

18.9.1 The Bit Processor
In the asynchronous (self clocked) modes the clock is
extracted from the data stream using the on-chip digital
phase-locked-loop (DPLL). The DPLL requires a clock
input at 16 times the data tate. This 16 X clock may
originate from SCLK, Timer I Overflow, or PH2 (one
half the oscillator frequency). The extra divide by-two
described above allows these sources to be treated
alternatively as 32 X clocks.
The DPLL is a free-running four-bit counter running off
the 16 X clock. When a transition is detected in the receive data stream, a count is dropped (by suppressing
the carry-in) if the current count value is greater than 8.
• A count is added (by injecting a carry into the second
stage rather than the first) if the count is less than 8. No

18-31

3) When receiving other than the flag pattern, the ZID
deletes the '0' after 5 consecutive 'I's (during transmission this zero is inserted). The ZID locates the
byte boundary for the rest of the circuitry. The ZID
deletes the 'O's by preventing the SR (shift register)
from receiving a clocking pulse.
4) The FCS (which is a function of the data between
the flags-not including the flags) is initialized and
started at the detection of the byte boundary at the
end of the opening flag. The FCS is computed each
bit boundary until the closing flag is detected. Note
that the received FCS has gone through the ZID
during transmission.

18.9.2 The Byte Processor
Figure 18-15 is a block diagram of the byte processor
(BYP). The BYP contains the registers and controllers
necessary to perform the data manipulations associated
with SDLC communications. The BYP registers may be
read or written by the CPU over the 8044's internal bus

INTERRUPT

1
RAM

- ----

-------

SHARED
REGISTERS

'--

BYP

CPU

I------------:s;u,

h
(

BIP

L _________________

SIB

I
I
I
I
I
I
I
I

I/O/ RXD
OATA/TXD

_________ J

Figure 18-14. The Bit and Byte Processors

(IB), using standard 8044 hardware register operations.
The 8044 register select PLA controls these operations.
Three of the BYP registers connect to the IB through the
IBS, a sub-bus which also connects to the CPU interrupt
control registers.
Simultaneous access of a register by both the IB and the
SIB is prevented by timing. In particular, RAM access
is restricted to alternate internal processor cycles for the
CPU and the SIU, in such a way that collisions do not
occur.
As an example of the operation of the byte processor, the
following sequence occurs in relation to the receive data:
I) Assuming that there is an address field in the frame,
the BYP takes the station address from the register
file into temporary storage. After the opening flag;

the next field (the address field) is compared to the
station address in the temporary storage. If a match
occurs, the operation continues.
2) Assuming that there is a control field in the frame,
the BYP takes the next byte and loads it into the
RCB register. The RCB register has the logic to update the NSNR register (increment receive count,
set SES and SER flags, etc.).
3) Assuming that there is an information field, the next
byte is dumped into RAM at the RBS locati!ln. The
DMA CNT (RBLat the opening flag) is loaded
from the DMA CNT register into ,the RB register
and decremented. The RFL is then loaded into the
RB register, incremented, and stored back into the
register file.
'

18-32

rr---

-----------'

I
I

I
I
I
I
I
I

I
I
I
I
I

RAM

I
I

SIS

BYP
TIMING
AND

SHARED
REGISTERS

CONTROL

I
I
I
I

SIP

L _________

____

I
~~

Figure 18-15. The Byte Processor

4) This process continues until the D MA CNT reaches
zero, or until a closing flag is received. Upon either
event, the BYP updates the status, and, if the CRC is
good, the NSNR register.

18.1~

DIAGNOSTICS

An SIU test mode has been provided, so that the on-chip
CPU can perform limited diagnostics on the SID. The
test mode utilizes the output latches for P3.0 and P3.1
(pins 10 and 11). These port 3 pins are not useful as
out-put ports, since the pins are taken up by the serial
port functions. Figure 18-16 shows the signal routing
associated with the SIU test mode.
Writing a 0 to P3.! enables the serial test mode (P3.! is
set to 1 by reset). In test mode the P3.0 bit is mapped

18-33

into the received data stream, and the 'write port :3' control signal is mapped into the SCLK path in place ofTl.
Thus, in test mode, the CPU c~n send a serial data
stream to the 8IU by writing to P3.0. The transmit data
stream can be monitored by reading P3.!. Each sucessive bit is transmitted from the SIU by writing to any bit
in Port 3, which generates SCLK.
In test mode, the P3.0 and P3.1 pins are placed in a high
voltage, high impedance state. When the CPU reads
P3.0 and P3.1 the logic level applied to the pin will be
returned. III the test mode, when the CPU reads 3.1, the
transmit data value will be returned, not the voltage on
the pin. The transmit data remains constant for a bit
time. Writing to P3.0 will result in the signal being outputted for a short period of time. However, since the signal is not latched, P3.0 will quickly return to a high
voltage, high impedance state.

CPU
BUS

PIN 15
SClKI

Til

TIMER 1 OYF

P35

SYS ClK

SIUSERIAL

DATA CLOCK

.a"
c::
Ci
....
....

~ ~

(XI
~

0>
I

'"
~

!"
5!!

i!:

a..

r1-

:II

"1J

SOU
~ RECEIVE
DATA
STREAM

READ PORT 3
WRITE PORT 3
PIN11
DATAl

TXDI
P31

SOU
TRANSMIT
DATA
STREAM

l..

oIIo~

RUPI"'-44

The serial test mode is disabled by writing a 1 to P3.1.
Care must be taken that a 0 is never written to P3.1 in
the course of normal operation, since this causes the test
mode to be entered.

opening flag, followed by the station address, a control
field indicating that this is a supervisory frame with an
RNR command, and then a closing flag.
Each byte of the frame is transmitted by writing that
byte into the A register and then calling the subroutine
XMIT8. Two additional SCLKs are generated to guarantee that the last bits in the frame have been clocked
into the SIU. Finally the CPU reads the status register
(STS). If the operation has proceeded correctly, the status will be 072H. If it is not, the program jumps to the
ERROR loop and terminates.

Figure 18-17 is an example of a simple program segment that can be imbedded into the user's diagnostic
program. That example shows how to put the 8044
into "Loop-back mode" to test the basic transmitting
and receiving functions of the SIU.
Loop-back mode is functionally equivalent to a hardwire
connection between pins 10 and lion the 8044.
In this example, the 8044 CPU plays the role of the primary station. The SIU is in the AUTO mode. The CPU
sends the SIU a supervisory frame with the poll bit set
and an RNR command. The SIU responds with a supervisory frame with the poll bit set and an RR command.
The operation proceeds as follows:
~nterrupts

are disabled, and the self test mode is enabled
by writing a zero to P3.1. This estaElishes P3.0 as the
data path from the CPU to the SIU. CTS (clear-tosend) is enabled by writing a zero to P1.7. The station
address is initialized by writing 08AH into the STAD
(station address register).
The SIU is configured for receive operation in the
clocked mode and in AUTO mode. The CPU then transmits a supervisory frame. This frame consists of an

The SIU generates an SI (SIU interrupt) to indicate
that it has received a frame. The CPU clears this interrupt, and then begins to monitor the data stream that is
being generated by the SIU in response to what it has
received. As each bit arrives (via P3.1), it is moved into
the accumulator, and the CPU compares the byte in the
accumulator with 07EH, which is the opening flag.
When a match occurs, the CPU identifies this as byte
boundary, and thereafter processes the information
byte-by-byte.
The CPU calls the RCV8 subroutine to get each byte
into the accumulator. The CPU performs compare operations on (successively) the station address, the control
field (which contains the RR response), and the closing
flag. If any of these do not compare, the program jumps
to the ERROR loop. If no error is found, the program
jumps to the DONE lo?p.

18-35

RUPI"'-44

•

MeS-51 MACRO A;:;S,":HDLER

LOC

C11t.J

DATA

LINE
1

'0000 7sc'eoo
0003, C281
0005 C2fi7

0007 7'CE8A

"
3

INlT

4
5

•

MOV

BT5 ••001-1

CLR
CLR

P3 1
PI 7
BTAD.

MOV

7
8
9

E".b·h ulf test ",ode

CONFIOVRE: RECEIVE OPERATION

ODOA 7'0861!t

MOV

0000: 75e'l01
0010 75C8e2

11
12

MOV

SMD.

MOV

5TS. 'OC2H

13
14

741£
120066
748A
120066

001D' 7495

00lF

1200~6

0022 747E
0024 120066
0027 D280
0029 0280

002B E5C8
002D B4722A

17
18

SEND

19
20
21
22
23
24

.
"7
28

CAL.L
MDV

9E9-0,

A • • SAH

NR(9)-!5.

SERoo()

TBF-I, RBE';'l. AM-I
STATI~

WITH THE POLL

CALL

XMlTS

MDY
CALL
MOV

A: 'Oq~
XMIT8
A• •7EH

MOV
CJNE

2'
30

*01101

.7EH
XMITB

HOV

CALL
SETB
SETB

31
32
33

NS(S)-3,
NFCS-l

NSNR • •6AH

TRANSMIT /It SUPERVISORY FRAME FROM THE PRIMARY
SIT SET AND A RNA COMI1AND

,.
0013
0015
00lS
001A

Enab!.· eTS
1"1tl.11:r.. addl' •••

ISAH

RNR SUP FRAME with P/F-l.
ReCltlVe

XMIT8
P3 0
,P3 0

A, STS
A. '72H.

t,..

SCL.~ ' . to
Inltlate recelV. action

O.n .... t • • •
J

NRCPl-4

clOSing flag

ERROR

PREPARE TO RECEIYE RUP I '5 RESPO~E TO PR lMARY 'S RNA

0030 C2CC
0032 7400
0034 1BOC

0036
0038
00310,
0038
003£
0041
0043

D280
A2Bl
13
847£03
020046
D8F3
02005A

3.
37
38
39
40
41
42
43
44
45

RECY

OLR
"00

Cha" 51
Cha" ACC
T"\I 12 h •• "

MOV

LOOK FOR THE OPENINQ FLAG:
WFLAGI

SETS

5ClK

P3
C. P3 1
A

CJNE
,,"P
DJNZ
.1I1P'

A, 101EH. WFlQl
CNTINV
R3. WFLAGI
ERROR

CALL.
C.JNE

MOV

WFLGI

RRC

Tl"anSlll1tted data

0049 B4BAOE

47
48
49
50
51

004C 1200'C
004F 84BI08

CALL

RCYS
A. IOSAH.
RCVS

CJNE

A. 10BIH. ERROR

CALL
CJ~E

RCVS
A. 107EH.

DONE

JHP

DONE

ERROR

JHP

ERROR

MOV
SETB
MOV

RRC
0"'"

RO. lOB
P3 0
C. P3 t
A
RO. O£TBIT

0046 12005C

0052 12005C

005' 847£02

00510, SOFE
OOSC 7808
005E D2BO
0060 A2B1

0062 13
0063 DBF9

0065 22

CNTINU

57
58
59
.0

.3
.4

RCVS

QET8IT

••
.7

Oet 51U's TranSMitted add"e.s 'ield
ERROR

ERROR

InitIalize the bit counte"
SCLK

Transmi tted data

RET

••

0066 7B090068 13

70
71

XMIT8

MOV

RO • • 9

RRC

OOb9 0801

73
74

OObB 22

DJNZ

RO,

RET

Initialize the bIt count."
Put the blt to be t"ans'lIltt.d
In the Ca""y
When all bits hav. been sllnt
return

7b
OObC 4004

006E C2&0
0070 8OF6

CLR

P3 0

..IMP

SETB
..IMP

P3 0
L3

0072 0280
0074 SOFe!

90
91
92
93
94

.n'

I' the carry bit
POT't P3 0 eh.
c 1 •• ,. port P3 0

Figure 18-17. Loop-Back Mode Software

18-36

set.

!tet

8044 -Application Examples

CHAPTER 19
8044 APPLICATION EXAMPLES
19.0 8044 APPLICATIONS EXAMPLES
19.1 INTERFACING THE 8044 TO A
MICROPROCESSOR
The 8044 is designed to serve as an intelligent controller
for remote peripherals. However, ii'can also be used as an
intelligent HOLC/SOLCfrontend fora microprocessor,
capable of extensively off-loading link control functions
for the CPU. In some applications, the 8044 can even be
used for communications preprocessing, in addition to
data link control.

system with an 8237A OMA controller and an 8259A
intenupt controller.
DMA Channel One transfers a block of memory to the
tri-state latch, while Channel Zero transfers a block of
data from the latch to 8088's memory. The 8044's Interrupt 0 signal vectors the CPU into a routine which reads
from the internal RAM and writes to the latch. The
8044's Interrupt I signal causes the chip to read from
the latch and write to its on-chip data RAM. Both DMA
requests and acknowledges are active low.
Initially, when the power is applied, a reset pulse coming
from the 8284A initializes the SR flip-flops. In this initialization state, the 8044's transmit interrupt and the
8088's transmit DMA request are active; however, the
software keeps these signals disabled until either of the
two processors are ready to transmit. The software
leaves the receive signals enabled, unless the receive
buffers are full. In this way either the 8088 or the 8044
are always ready to receive, but they must enable the
transmit signal when they have prepared a block to
transmit. After a block has been transmitted or received,
the DMA and interrupt signals return to the initial
state.

This section describes a sample hardware interface for
attaching the 8044 to an 8088. It is general enough to be
extended to other microprocessors such as the 8086 or
the 80186.
OVERVIEW

A sample interface is shown in Figure 19-1. Transmission occurs when the 8088 loads a 64 byte block of memory with some known data. The 8088 then enables the
8237A to OMA this data to the 8044. When the 8044
has received all of the data from the 8237 A, it &ends the
data in a SOLC frame. The frame is captured by the
Spectron Datascope@* which displays it ,on. a CRT in
hex format.
',

The receive and transmit buffer sizes for the blocks of
data sent between the 8044 and the 8088 have a maximum fixed length. In this case the buffer size was 64·
bytes. The buffer size must be less than 192 bytes to enable 8044 to buffer the data in its on-chip RAM. This
design allows blocks of data that are less than 64 bytes,
and accommodates networks that allow frames of varying size. The first byte transftlrred between the 8088 and
the 8044 is 'the byte count to follow; thus the 8044 knows
how many bytes to receive before it transmits the SDLC
frame. However, when the 8044 sends data to the 8088's
memory, the 8237 A will not know if the 8044 will send
less than the count the 8237A was programmed for. To
solve this problem, the 8237A is operated in the single
mode. The 8044 uses an I/O !:lit to generate an interrupt
request to the 8259A. In the 8088's interrupt routine,
the 8237A's receive DMA channel is disabled, thus allowing blocks of data less than ,64 bytes to be received.

In reception, the Datascope sends an SDLC information
frame to the 8044. The 8044 receives the SDLC frame,
buffers it, and sends it to the 8088's memory. In this example the 8044 is being operated in the NON-AUTO
mode; therefore, it does not need to be polled by a primary station in order to transmit.
THE INTERFACE'

The 8044 does not have a parallel slave port. The 8044's
32 I/O lines can be configured as a local microprocessor
bus master. In this configuration, the 8644 can expand
the ROM and RAM memory, control peripherals, and
communicate with a microprocessor.
The 8044, like the 8051, does not have a Ready line, so
there is no way to put the 8044 in wait state. The clock
on the 8044 cannot be stopped. Dual port RAM could
still be used, however, software arbitration would be the
only way to prevent collisions. Another way to interface
the 8044 with another CPU is to put a FIFO or queue
between the two processors, and this was the method
chosen for this design.

THE SOFTWARE

The software for the 8044 and the 8088 is shown in Table 19-1. The 8088 software was written in PL/M86,
and the- 8044 software was written in assembly
language.

Figure 19-2 shows the schematic of the 8044/8Q88 interface. It involves two 8 bit tri-state latches, two SR flipflops, and some logic gates (6 TTL packs). The circuitry
implements a one byte FIFO. RS422 transceivers are used,
which can be connected to a multidrop,link. Figure 19-3
shows the 8088 and support circuitry; the memory and
decoders are not shown. It is a b/lSic 8088 Min Mode

The 8044 software begins by initializing the stack, interrupt priorities, and triggering types for the interrupts.
At ,this point, the SIU parameter registers are initialized. The receive and transmit buffer starting addresses
and lengths are loaded for the on-chip 0 MA. This 0 MA
is for the serial port. The serial station address and the
transmit control bytes are loaded too.
January 1985

*Datascope is a trademark of Spectron Inc.

19-1

I-----~--~-------~-I

I
I
I
I
I
I
I
I
I

I
I
I
I
I
I
I

I
I

L_~_~____

DATASCOPE,

Figure 19-1.

Block Diagram of 8088/8044 Interface Test

Once the initialization has taken place, the SIU interrupt is enabled, and the external interrupt which receives bytes from the 8088 is enabl~. Setting the 8044's
Receive Buffer Empty (RBE) bit el\ables the receiver. If
this bit is.reset, no serial data can be received. The 8044
then waits in a loop for either RECEIVE DMA interrupt or the SERIALINT interrupt.
The 'RECEIVE DMA interrupt occurs when the 8237 A
is transferring a block of data to the 8044. The first time
this interrupt occurs; the 8044 reads the latch and loads
the count value into the R2 register. On subsequent interrupts, the 8044 reads the latch, loads the data into the
transmit buffer, and decrements R2. When R2 reaches
zero, the interrupt routine sends the data in an SDLC
frame, and disables the RECEIVE DMA interrupt.
After the frame has been transmitted; a serial interrupt
is generated. The SERIAL INT routine detects that a
frame has been transmitted and ,re-enllbles the RECEIVE DMA interrupt. Thus, while the frame is being
transmitted through the SIU, the 8237A is inhibited
from sending data to the 8044'5 transmit buffer.
The TRANSMIT DMA routine sends a' block of data
from the 8044's receive buffer to the 8088's memory.
Normally this.interrupt·rernains disable,d. Howeyet, if a
serial interrupt' occurs, 'and the SERIAL INT routine
detects that a frame has been received, it caUs the
SEND subroutine. The SEND subroutine loads the
number of bytes which were received in the frame ihto
the receive buffer, Register R I 'points to the receive buff-

er and R2 is loaded with the count. The TRANSMIT
DMA interrupt is enabled, and immediately upon returning from the SERIAL INT routine, the interrupt is
acknowledged. Each time the TRANSMIT DMA interrupt occurs, a byte is read from the receive buffer,
wtitten to the latch, and R2 is decremented. When R2
reaches 0, the TRANSMIJ' DMA interrupt is di,sabled,_
the SIU receiver is re-enabled, and the 8044 interrupts
the 8088.
The 8088 software simply transmits a blOCk of data and
receives a block of data, then stops. The software begins
by initializing the 8237 A, and the 8259A. It then loads a
block of memory with some data and enables the 8237 A
to transmit the data. In the meantime the 8088 waits in a
loop. After, a block of data is received from the 8044, the
, 8088 is interrupted, and it shuts off the 8237A receive
DMA.

CONCLUSION
For the software shown in Table 19-1, the transfer rat!!
from the 8088's rnemory to the 8044 was measured at
75K bytes/sec. This transfer rate lafgely depends upon
the number of instructions in tbe' 8044's interrupt service
routine. Fewer instructions result in a higher transfer rate.
"

There are many ways of interfacing the 8044 locally to
another, microprocessor: FIFO's, dual port RAM with
software arbitration, and 8255's are just a few. Alternative approaches, \vhich 'may be more optimal for Certain
applications, are certainly possible.'
.

19-2

OREQ1
OREQa

OACKl

....

cp
~
CII

.....

i....

A POINTER TO THE TRANSMIT
; BUFFER STARTING ADDRESS
; PUT THE FIRST BYTE INTO
; R2 FOR THE COUNT

L2:

RET!

L1:

MOV

RO, #106

MOVX
MOV
RET!

A,@DPTR
R2,A

0076 EO
0077 FA
0078 32
0079
0003
0003 020079
0079

0079
007A
007B
007C

E7
FO
09
DA08

007E
0080
0082
0084

C2A8
C294
D294
D2CE

0086 32

0087
0023
0023 020087
0087

0087 30CE06
008A 30CFOB
008D 020056
0090
0093
0095
0097

20CBC3
1158
C2CC
32

0098 C2CC

73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98'
99
100
101
102
103
104
105
106
107
108
109
110
III
112
113
114

LOLTMPSET
ORG
LJMP
ORG

,; READ THE LATCH
; PUT IT IN TRANSMIT BUFFER
; AFTER READING BYTES,

0003H
TRANSMILDMA
LOLTMP

TRANSMILDMA

L3:

MOV
MOVX
INC
DJNZ

A,@RI
@DPTR,A
RI
R2, L3

; READ BYTE OUT OF THE RECEIVE BUFFER
; WRITE IT TO THE LATCH

CLR
CLR
SETB
SETB

IE. 0
PI. 4
PI. 4
RBE

; DISABLE INTERRUPT
; CAUSE 8088 INTERRUPT TO TERMINATE DMA

; WHEN ALL BYTES HAVE BEEN SENT

; ENABLE RECEIVER AGAIN

RET!

. LOLTMPSET
ORG
LJMP
ORG

0023H
SERIALINT
LOLTMP

SERIALINT:
JNB
JNB
LJMP

RBE,RCV
TBF,XMIT
ERROR

; WAS A FRAME RECEIVED
; WAS A FRAME TRANSMITTED
; IF NEITHE~ ERROR

RCV:

JB
CALL
CLR
RET!

BOV, ERROR
SEND
SI

; IF BUFFER OVER~UN THEN ERROR
; SEND THE fRAME TO THE 8088

XMIT:

CLR

19-~

RUPI™-44

009A D2AA
009C 32

115
116
117
liS

SETB
RETI

EXI

END

SYMBOL TABLE LISTING

NAME
BOV
. ERROR
EXO
EXI
FIRSLBYTE
IE
INIT
IP
Ll
L2
L3
LOCTMP
PI
RBE
RBL
RBS
RCV
RECEIVE_DMA
RFL
RTS
SEND
SERIALINT
SI
SMD
SP
STAD
TBF
TBL
.TBS
TCB
TCON
THI
TMOD
TRANSMILDMA
XMIT

TYPE
B
C
B
B
B

o
C

o
C
C
C
C

o
B

o
o
C
C

o
B
C
C
B

o
o
o
B

o
o
o
o
D

ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
AD DR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
AD DR
ADDR
ADDR
ADDR
AODR
ADDR
ADDR

C
C ~DDR

ATTRIBUTES

VALUE
00CSH.3
0056H
OOASH.O
OOASH.2
0020H.0
OOASH
0026H
OOBSH
0074H
0073H
OOS6H
00S7H
0090H
OOCSH.6
OOCBH
OOCCH
0090H
0063H
OOCDH
00CSH.5
005SH
OOS7H
OOCSH.4
,OOC9H
OOSlH
OOCEH
OOCSH.7
OODBH
OODCH
OODAH
OOSSH
OOSDH
00S9H
0079H
009SH

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

19-7

Table 19-2. PL/M-86 Compiler Rupi/8088 Interface Example
SERIES-III PL/M-86 VI 0 COMPILATION OF MdDULE RUPI_88
OBJECT MODULE PLACED IN ·FI·R88.0BJ
COMPILER INVOKED BY:
PLM86 86 ·FI R88.SRC

SDEBUG
STITLE

('RUPI/8088 INTERFACE EXAMPLE')

RUPI_88: DO,
DECLARE

LIT
TRUE
FALSE

LITERALLY
LIT
LIT

RECV_BUFFER(64)
XM IT _BUFFER (64 )

BYTE,
BYTE,
BYTE,
BYTE,

WAIT

'LITERALLY' ,
'OlH';
'OOH',

1* 8237 PORTS*I
MASTER_CLEAR_37
COMMAND_37
ALL_MASK_37
SINGLE_MASK_37
STATUS 37
REGUEST_REG _37
MODE_REG_37
CLEAR _BYTE_PTR _37

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

'OFFDDH',
'OFFD8H',
'OFFDFH',
'OFFDAH'.
'OFFD8H',
'OFFD9H',
'OFFDBH' ,
'OFFDCH' ,

CHO_ADDR
CHO_COUNT
CHl_ADDR
CH130UNT
CH2_ADDR
CH2_COUNT
CH3_ADDR
CH3_COUNT

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

'OFFDOH',
'OFFDIH' ,
'OFFD2H',
'OFFD3H',
'OFFD4H',
'OFFD5H',
'OFFD6H',
'OFFD7H'.,

1* 8237 BIT ASSIGNMENTS *1
CHO_SEL
CHI_SEL
CH2_SEL
CH3_SEL
WRITE XFER
READ_XFER
DEMAND_MODE
SINGLE MODE
BLOCK MODE
SET_MASK

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

'OOH' ,
'OlH',
'02H',
'03H',

'04H',
'OSH',
'OOH" ,
'40H',

'BOH',
'04H',

SEJECT

1* 8259 PORTS *1
STATUS_POLL_59
ICWl_59
OCWI_59
OCW2_59
OCW3_59
ICW2_59
ICW3_59
ICW4_59

'OFFEOH',
'OFFEOH',
'OFFEIH',
'OFFEOH',
'OFFEOH',
'OFFEIH' ,
'OFFEIH',
'OFFEIH',

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

1* INTERRUPT SERVICE ROUTINE *1
PROCEDURE

3
4
5
6

2
2
2

INTERRUPT 32.

OUTPUT (SINGLE_MASK_37)=40H,
WAIT=FALSE,
END,

19-8

DISABLE.
1* INITIALIZE 8237 *1

9
10
11

12
13
14
15
'16
17
18
19
20
21

I
I
1
1
1
I
1
I
1
I
'I
I
1
I

OUTPUTCM~ST~R_CLEAR_37)

OUTPUTCCOMMAND 37)

OUTPUTCALL_"AS~37)

OUTPUTCMODE_REQ_37)
OUTPUT CMODE_REQ_37)
OUTPUT CCLEAR_BYTE_PTR_37)
OUTPUTCCHO_ADDR)
OUTPUTCCHO_ADDR)

-OJ
-OOH;
-40Hi

OUTPUTCCHO_COU~T)

-64;

OUTPUT CCHO_CqUNT)
OUTPUT CCHI_ADDR)

=00.
-40Hi

~~~~~~:~~!:~~~:i)

-0,
-040H,
-OFH.
-CSINQLE_MODE OR WRITE_XFER OR CHO_SEL).
-CSINQLE_MODE OR READ_XFER OR CHI_SEL).

-40Hi

-64;

OUTPUTCCHI_COUNT)

-00,

1* INITIALIZE 8259 *1

OUTPUT ( ICWI_59)

23
24
25

OUTPUT< ICW2_59)
OUTPUT< ICW4_59)
OUTPUT (OCWI_59)
$E,JECT
CALL

- 26
27
28
29
30

=13H. I*SINQLE MODE. EDQE TRIQQERED
INPUT. 8086 INTERRUPT TYPE*I
=20H. I*INTERRUPT TYPE 32*1
-03H. I*AUTO-EOI*I
-OFEH. I*ENABLE INTERRUPT LEVEL 0*1

SET$I~TERRUPT

(32,OFF_RECV_DMA). I*LOAD INTERRUPT VECTOR LOCATION*/

XMIT_BUFFER(0)=64. I*THE FIRST BYTE IN THE BLOCK OF DATA IS THE NUMBER
OF BYTES TO BE TRANSFERED. NOT INCLUDINQ THE FIRST BYTE*/

DO 1= I TO 64. 1* FILL UP THE XMIT_BUFFER WITH DATA *1
'XMIT_BVFFERC J )-1'
END.

2
2

OUTPUTCALL_MASK_37)-OFCH.

ENABLE,

33
34
35

WAIT-TRUE.
DO WHILE WAIT.
END,

I
I

I*ENABLE CHANNEL 1 AND 2 *1

1* A BLOCK OF DATA WILL BE TRANSFERRED TO THE RUPI,

WHEN THE RUPI RECEIVES A BLOCK OF DATA IT WILL
SEND IT TO THE 8088 MEMORY AND INTERRUPT THE 8088.
THE INTERRUPT SERVICE ROUTINE WILL SHUT OFF THE DMA
CONTROLLER AND SET 'WAIT' FALSE *1
36
37

DO WHILE I,
END.

I
2

END.

MODULE INFORMATION:
CODE AREA SIZE
CONSTANT AREA SIZE VARIABLE AREA SIZE MAXIMUM STACK SIZE·
124 LINES, READ
o PROQRAM WARNINQ8
o PROQRAM ERROR8

00D7H
OOOOH
0082H
OOIEH

215D
OD
130D
30P

END OF PL/M-B6 COMPILATION

19-9

A HIGH PERFORMANCE NETWORK
USING THE 8044
19.2.1 Introduction
This section describes the design of an SOLC data link
using the 8044 (RUPI) to implement a primary station
and a secondary station. The design was implemented
and tested. The following discussion assumes that the
reader understands the 8044 and SOLe. This section is
divided into two parts. First the data link design
example is discussed. Second the software modules
used to implement the data link are described. To help
the reader understand the discussion of the software,
flow charts and software listings are displayed in
'Appendix A-and Appendix B, respectively.

Application Description
This particular data link design example uses a two wire
half-duplex multidrop topology as showri in figure 19-4.
In an SOLC multidrop topology the primary station
communicates with each secondary station. The
secondary stations communicate only to the primary.
Because of this hierarchial architecture, the logical
topology for an SOLC multidrop is a star as shown in
figure 19-5. Although the physical topology of this data
link is multidrop, the easiest way to understand the
information flow is to think of the logical (star)
topology. The term data link in this case refers to the
logical communication pathways between the primary
station and the seconc\ary stations. The data links are
shown in figure 19-5 as two way arrows.
The application example uses dumb async terminals to
interface to the SOLC network. Each secondary station
has an async terminal connected to it. The secondary
stations are in effect protocol converters which allows any async terminal to communicate with any other async
terminal on the network. The secondary stations use an
8044 with a UART to convert SOLC to async. Figure
19-6 displays a block diagram of the data link. The
primary station, controls the data link. In addition to
data link control the primary provides a higher level
layer which a path control function or networking
layer. The primary serves as a message exchange or
switch. It receives information from one secondary station and retransmits it to another secondary station.
Thus a virtual end to end connection is made between
any two secondary stations on the network.

,Three separate software modules were written for this
network. The first module is a Secondary Station Oriver
(SSO) which provides an SOLC data link interface and
a user interface. This module is a general purpose driver
which requires application software to run it. The uSer
interface to the driver provides four functions: OPEN.

CLOSE, TRANSMIT, and SIU_RECV. Using these
four functions properly will allow any application software to communicate over this SOLC data link without
knowing the details of SOLC. The secondary station
driver uses the 8044's AUTO mode.
The second module is 'an example of application software which is liIiked to the secondary station driver.
This module drives the 8251A, buffers data, and interfaces with the secondary station driver's user interface.
The third module is a primary station, which is a standalone program (I.e., it is not linked to any other
module). The primary station uses the 8044'5 NONAUTO or FLEXIBLE mode. In addition to controlling the data link it acts as a message switch. Each time
a secondary station transmits a frame, it places ,the
destination address of the frame in the first byte of the
information or I field. When the primary station receives
a frame, it removes the first byte in the I field and
retransmits the frame to the secondary station whose
address matches this byte.
This network provides two complete layers of the OSI
(Open Systems Interconnection) -reference model: the
, physical layer and the data link layer. The physical layer
implementation uses the RS-422 electrical interface. The
mechanical medium consists of ribbon cable and connectors. The data link layer is defined by SOLe.
SOLC's use of acknowledgements and frame numbering guarantees that messages will be received in the same
order in which they were sent. It also guarantees message
integrity over the data link. However this network will
not guarantee secondary to secondary message delivery,
since there are acknowledgements between secondary
stations.

19.2.2 Hardware
The schematic of the hardware is given in figure \9-7 .
The 8251A is used as an async communications controller, in support of the 8044. TxROY and RxROY on
the 825 IA are both tied to the two available external
interrupts of the 8044 since the secondary station driver
is totally interrupt driven. The 8044 buffers the data
and some variables in a 2016 (2K x 8 static RAM). The
8254 programmable interval timer is employed as a programmable baud rate generator and system clock driver
for the 8251A. The third output from the 8254 could
be used as an external baud rate generator for the 8044.
The 2732A shown in the diagram was not used since
the software for both the primary and secondary
stations used far less than the 4 Kbytes provided on the
8744. For the async interface. the standard RS-232

PRIMARY
STATION

SECONDARY
STATION

Figure 19-4. SOLC Multidrop Topology

·mechanical and electrical interface was used. For the
SOLe channel, a standard two wire three state RS-422
driver is used. A DIP switch connected to one of the
available ports on the 8044 allows the baud rate,
parity, and stop bits to be changed on the async inter- .
face. The primary station hardware does not use the
USART, 8254, nor the RS-232 drivers.

19.2.3 SOLe Basic Repertoire
The SOLe commands and responses implemented in
the data link include the SOLe Basic Repertoire as
defined in the IBM SOLe General Information manual.
Table 19-3 shows the commands and responses that the
primary and the secondary station in this data link
design recognize and send.

SECONDARY
STATION

PRIMARY
STATION

SECONDARY
STATION

Figure 19-5. SOLC Logical Topology

19-11

>
O:z
~Q
~~

,....---'--.....,

frl:ii
I/)

>
a:z..-_ _ _ _.....
~Q

~~ L!J
zl-

[!]

...I

zi!!:
>::0
a:

I-

::0

Figure 19-6. Block Diagram of the Data Link
Application Example

19-12

: : rJ
: ~;~ ~·T;lll
~,

6
:

iii

-: -~ -1:11
~ 1

,I,

---

'YI'

•
. ,
~

'-!"

gggggggg

, ,I' "'I' "I"

•"
,; S

.. "
"

Figure 19-7. Schematic of Async/SDLC Secondary Station Protocol Converter

19-13

Table 19-3. Data Link Commands and
Responses Implemented for This Design
PRIMARY STATION

Unnumbered

Supervisory
Information

Responses
Recognized

Commands
Sent

UA
OM
FRMR
-RD

SNRM
DISC

RR
RNR

SECONDARY STATION

Unnumbered

CommanGis
Recognized

Responses
Sent

SNRM
. DISC
-TEST

UA
OM
FRMR
-RD
-TEST

Supervisory

RR
RNR
REJ

RR
RNR

Information

- not included in the SDLC Basic Repertoire

The term command specifically means all frames which
the primary station transmits and the secondary stations
receive. Response refers to frames which the secondary
stations transmit and the primary station receives.

Number of Outstanding Frames
This particular data link design only allows one outstanding frame before it must receive an acknowledgement. Immediate acknowledgement allows the
secondary station drivers to use the AUTO mode. In
addition, one outstanding frame uses less memory for
buffering, and the software becomes easier to manage.

19.2.4 Secondary Station Driver using
AUTO mode
The 8044 secondary station driver (SSD) was written
as a general purpose SDLC driver. It was written to be
linked to an application module. The application software implements the actual application in addition to
interfacing to the SSD. The main application could be,
a ·printer or plotter, a medical intrument, or a terminal.
The SSD is independent of the main application, it just
provides the SDLC communications. Existing 8051

applications could add qigh performance SDLC communications capability by linking the SSD to the existing
software and providing additional software to be able
to communicate with/ the SSD.

Data Link Interface and User Interface States
The SSD has two software interfaces: a data link interface and a user interface as show in Figure 19:8. The
data link interface is the part of the software which controls the SDLC communications. It handles link access,
command recognition/response, acknowledgements,
and error recovery. The user interface provides four
functions: OPEN, CLOSE, TRANSMIT, and
SIU RECV. These are the onl~ four functions which
the application software has to interface in order to com~
municate using SDLC. These four functions are common to many 110 drivers like floppy and hard disks,
keyboard/CRT, and async communication drivers.

The data link and the user interface each have their own
states. Each interface can only be in one state at any
time. The SSD uses the states of these two interfaces
to help synchronize the application module to the data
link.
There are three states which the secondary station data
link interface can be in: Logical Disconnect State
(L_D_S). Frame Reject State (FRMR_S), and the
Information Transfer State (1_ T _S). The Logical
Disconnect State is when a station is physically connected to the channel but either the primary or secondary have not agreed to enter the Information Transfer
State. Both the primary and the secondary stations synchronize to enter into the Information Transfer State.
Only when the secondary station is in the 1_T _S is
it able to transfer data or information to the primary.
The Frame Reject State (FRMR_S) indicates that the
secondary station has lost software synchronization with
the primary or encountered some kind of error condition. When the secondary station is in the FRMR_S, the
primary station must reset the secondary to resynchronize.

The user interface has two states, open or closed. In
the closed state the user program does not want to communicate over the network. The communications channel is closed and not available for use. The secondary
station tells the primary this by responding to all commands with DM. The primary continues to poll the
secondary in Case it wants to enter the 1_T _S state.
When the user program hegins communication over the
data link it goes into the open state. It does this by calling the OPEN procedure. When the user interface is
in the open state it may transfer information to the
primary.
19-14

SECONDARY STATION

SECONDARY
STATION
DRIVER
MODULE

APPLICATION
MODULE

DATA
LINK
INTERFACE
SSD
INTERFACE

"
~

USER
INTERFACE

USER STATES

SSD
INTERFACE
PROCEDURES

1. OPEN
2. CLOSED

DATA LINK
STATES
1. LOGICAL
DISCONNECT
STATE
2. INFORMATION
TRANSFER
STATE
3. FRAME
REJECT
STATE

OPEN
CLOSE
TRANSMIT
SIU RECV

Figure 19-8. Secondary Station Software Modules

19-15

Secondary Stations Commands, Responses and

A command can not be recognized by the
secondary station.

There is a buffer overrun.

The Nr that was received from the primary
station is invalid. '

State Transitions

Table 19-4 shows the commands which the secondary
station recognizes and the responses it generates. The
first row in table 19-4 displays commands the secondary station recognizes and each column shows the
potential responses with respect to secondary station.
For example, if the secondary is in the Logical Disconnect State it will only respond with DM, unless it receives
a SNRM command and the user state is open. If this
is the case, then the response will be UA and the secondary station will move into the I_T_S.
Figure 19-9 shows the state diagram of the secondary
station. When power is first applied to the secondary
station, it goes into the Logical Disconnect State. As
mentioned above, the ,_T _S is entered when the
secondary station receives a SNRM command and the
user state is open. The secondary responds with UA to
let the primary know that it has accepted the SNRM
and is entering the I_T_S. The I_T_S can go into
either the L_D_S or the FRMR_S. The ,_T _S goes
into the L_D_S if the primary sends the secondary
DISC. The secondary has to respond with UA, and then
goes into the L_D_S. If the user interface changes
'from open to close state, then the secondary sends RD.
This causes the primary to send a DISC.
The FRMR_S is entered when a secondary station is
in the I~ T _S and either one of the following
conditions occurs.

The secondary station cannot 'eave the FRMR_S until
it receives a SNRM or a DISC command. '
Software description of the SSD

To aid in following the description of the software, the
reader may either look at the flow charts which are given
for each procedure, or read the PLlM-51 listing provided in Appendix A.
A block diagram of the software structure of th~ SSD
is given in figure 19-10. A complete module is identified
by the dotted box, and a procedure is identified by the
solid box. Therefore the SIU _RECV procedure is not
included in the SSD module, it exists in the' application
software. Two or more procedures connected by a solid
line means the procedure above calls the procedure
below. Transmit, Power_on_D, Close, and Open are
all called by the application software. Procedures
without any solid lines connected above are interrupt
procedures. The only interrupt procedure in the SSD
module is the SIU _INT.
The entire SSD module is interrupt driven. Its design
allows the application program could handle real time
events or just dedicate more CPU time to ,the application program. The SIU _INT is the only interrupt pro-

Table 19·4 . Secondary Station Responses to Primary Station Commands
Data Link
States
Information
transfer state

I
RR
RNR
RD
FRMR

Primary Station Commands
RNR
SNRM
I
RR
RNR
RD
FRMR

DISC

TEST

UA
Test

Logical
disconnect state

DM,

UA
Frame
reject state

FRMR

19-16

DISC

~~~ER

____________~

Figure 19-9. State Diagram of Secondary Station

,19-17

1---------------------1
r--

1
1

III
l-

I-

(1)1
u
III

I-

Z
Z

...-- u

~ I-!

'--

.--III
l-

I
I
I

I-

(I)

:I!

...I

'--

III

ILl
~

:I!

'---

(I)

ILl

'---

I-

::)

:I!
0

'--

'---

:I!

...I

I-

r---

I
I

'---

I
I

----- --_..-:_-----,
.--Ii!
~

i r-I

L....

::)'

iii
'--

I
I

1
I

I
I
I
I

r--

I
I

'---

iii

I
I

I
Q

z
z
::)

I-

::)

I
I

-I

II:

:I!

ILl

ILl
ILl

r-Q

t--

I
I

(I)

'--

r--

(I)

.-!-I
i

L---------.....:----l

(I)

z
e~

I-

L...-

1._._._.- _._._._.
Figure 19-10. Secondary Station Driver

19-18

For the second case, if the STATION_STATE is in
the 1_T _S but the SIU left the AUTO mode, then the
CPU must determine why the AUTO mode was exited,
and generate a response to the primary. There are four
reasons for the SIU to automatically leave the AUTO
mode. The following is a list of these reasons, and the
responses given by the SSD based on each reason.

cedure in the SSD. It is automatically entered when an
SIU interrupt occurs. This particular interrupt can be
the lowest priority interrupt in the system.
SSD Initialization

Upon reset the application software is entered first. Tl:le
application software initializies its own variables then
calls Power_On_D which is the SSD's initialization
routine. The SSD's initialization sets up the transmit
and receive data buffer pointers (TBS and RBS), the
receive buffer length (RBL), and loads the State
variables. The STATION_STATE begins in the L_
D_S state, and the USER_STATE begins in the closed
state. Finally Power_On_D initializes XMIT_
BUFFER_EMPTY which is a bit flag. This flag serves
as a semaphore between the SSD and the application
software to indicate the status of the on chip transmit
buffer. The SSD does not set the station address. It is
the application software's responsibility to do this. After
initialization, the SSD is ready to respond to all of the
primary stations commands. Each time a frame is received with a matching station address and a good CRC,
the ~IU _INT procedure is entered.

I. 1.1e SIU has received a command field it does
not recognize.
Response: If the CPU recognizes the command,
it generates the appropriate response. If neither
the SIU nor the CPU recognize the command, then
a FRMR response is sent.
2. The SIU has received a Sequence Error Sent
(SES= I in NSNR register). Nr(P) -# Ns(S)+ I, and
Nr(P) Ns(S).
Response: Send FRMR.

3. A buffer overrun has occured. BOV=I in STS
register.
Response: Send FRMR.
4. An I frame with data was received while RPB= I.
Response: Go back into AUTO mode and send an
AUTO mode response.

SIU_INT Procedure

In addition to the above reasons, there is one condition where the CPU forces the SIU out of the AUTO
mode. This is discussed in the SSD's User Interface Procedures section in the CLOSED procedure description.

The first thing the SIU_INT procedure clears the serial
interrupt _bit (SI) in the STS register. If the SIU_
INT procedure returns with this bit set, another SI interrupt will occur.

Finally, case three is when the STATION_STATE is
in the 1_T _S and the AUtO mode. The CPU first
looks at the TBF bit. If this bit is 0 then the interrupt
may have been caused by a frame which was transmitted and acknowledged. Therefore the XMIT_
BUFFER_EMPTY flag is set again indicating that the
application software can transmit another frame.

The SIU _INT procedure is branches three
independent cases. The first case i~ entered if the
STATION_STATE is not in the I_T_S. If this is
true, then the SIU is not in the AUTO mode, and the
CPU will have to respond to the primary on its own.
(Remember that the AUTO mode is entered when the
STATION_STATE enters into I_T_S.) If the
STATION_STATE is in the I_T_S, then either the
SIU has just left the AUTO mode, or is still in the
AUTO mode. This is the second and third case
respectively.
In the first case, if the STA TION_STATE is not in
the 1_T _S, then it must be in either the L_D _S or
the FRMR_S. In either case a separate procedure is
called based on which state the station is in. The In_
Disconnect_State procedure sends to the primary a DM
response, unless it received a SNRM command and the
Uf?ER_STATE equals open. In that case the SIU sends
an UA and enters into the 1_T _So The In_FRMR_
State procedure· will send the. primary the FRMR
response unless it received either a DISC or an SNRM.
If the primary's command was a DISC, then the secondary will send an UA and enter into the L_D_S. If
the primary's command was a SNRM, then the secondarywill send an UA, enter into the 1_T _S, and clear
NSNR register.

The other reason this section of code could be entered
is if a valid I frame was received. When a good I frame
is received the RBE bit equals O. This means that the
receiver is disabled. If the primary were to poll the 8044
while RBE=O, it would time out since no response would
given. Time outs reduce network throughput. To
improve network performance, the CPU first sets RBP,
then sets Rim. Now when the primary polls the 8044
an immediate RNR response is given. At this point the
SSD calls the application software procedureSIU_RECV
and passes the length of the data as a parameter. The
SIU _RECV procedure reads the data out of the receive
buffer then returns to the SSD module. Now that the
receive information has been transfered, RBP can
be cleared.

19-19

Command_Oecode Procedure

The Command_Decode procedure is called from the
SIU _INT procedure when the STATION_STATE =
1_T _S and the SIU left the AUTO mode as a result

, C·FIELD OF THE REJECTED COMMAND, AS RECEIVED

THIS STATION'S PRESENT Ns

THIS SlATION'S PRESENT Nr

HIGH·ORDER

~
,

RECEIVED DISAGREES WITH tRANSMITTED Ns
BUFFER OVERRUN (I·FIELD IS

too LONG)

PROHIBITED I·FIELD RECEIVED
INVALID OR NONIMPLEMENTED COMMAND

Figure 19-1,1 . Information Field of the FRMR Response, 'as T~ansmltted

of not being able to recognize the receive control byte.
Commands which the SIU' AUTO mode does not
recognize are handled here. The commands recogniz·
ed in this procedure are: SNRM, DISC, and TEST. Any
other command received will generate a Frame Reject
with the nonimplemented command bit set in the third
data byte of the FRMR frame. Any additional unnumbered frame commands which the .secondary station is going to implement, should be implemented in
this procedure. "
If a SNRM is received the command_decode procedure
calls the SNRM_Response procedure. The SNRM_
'Response procedure sets 'the STATION_STATE = I_
T S, clears the NSNR register and responds with an
UA frame. If DISC is received, the command~deCode
procedure sets ,the STATIqN_STATE = L_D_S,
and responds with an UA frame. WheJ) a TEST frame
is received, and there 15 no buffer overrun, the
command_decode procedure responds with a T~ST
- frame retransmitting the same, data it received. However
if a TEST frame is received and there is a buffefover·
rlln, the!! a, TEST frame will b,e sent withQut any data,
instead of a ~RMR with the b}lffer overrun bit set.

Frame Reject Procedures,

There are two procedures which handle the FRMR state:
XMIT _FRMR and IN_FRMR_ST ATE. XMIT':'"
FRMR is entered when. the secondary station first goes
into the FRMR state. The frame reject response frame
contains the FRMR'resporise in the'command field'plus
three' additional data bytes in the I field. Figure 19-11
displays the format for the three data byte in the I field

of a FRMR response. The XMIT _FRMR procedure
sets up the Frame Reject response frame based on the
parameter REASON which is passed to it. Each place
in the SSD code that calls the XMIT _FRMR procedure, passes the REASON that this procedure was
called, which in turn is communicated to the primary
station. The XMIT_FRMR procedure uses three bytes
of internal RAM which it initializes for the correct
response. The'TBS and TBL registers are then changed to point to the FRMR buffer so that when a response
is sent these three bytes will be.included in the I field.
The IN_FRMR_STATE procedure i$ called by the
SIU_INT procedure when the STATION_STATE
already is in the FRMR state and a response is
required. fhe IN_FRMR_STATE procedure will only
allow two commands to remove the secondary station
from the FRMR state: SNRM and DISC. Any other
command which is received while in the FRMR state
will result a FRMR response frame.
XMIT _UNNUMBERED Procedure

This is a general purpose transmit procedure, used
only in the FLEXIBLE mode, which sends unnumbered
responses to the primary. It-accepts the control byte as
a parameter, and also expects·the TBL register to be
set before the procedure·is called. This proeedure waits
until·the frame has been transmitted before returning.
If this procedure returned before the transmit interrupt
was.generated, the SIU::'IN'f routine would be entered.
The SIU _INT rQutine would not be able to distinguish
this condition.
19-20

SSD's User Interface Procedures -- OPEN, ~LOSE,
TRA,NSMIT, SIU_~ECV -- are discussed in the
,
following' s~ction.
The OPEN procedure is the simplest of all, it changes
the USER STATE to OPEN S then returns. This lets
the SSD know that the user wants to open the channel
for communications. When rhe 'SSD receives a SNRM
command, it checks the USER_STATE. If the
USER_STATE is open, then the SSD will respond with
an UA, and the STATION_STATE enters the
I..,-T_S.
'
The' CLOSE procedure is also simple, it changes the
USER_STATE to CLOSED_S and sets the AM bit
to O. Note that when the CPU sets the AM bit to 0 it
puts the SIU out of the AUTO mode. This event is asynchronous to the events on the network. As a result an
I frame can be lost. This is what can happen.

TRANSMIT procedure is called, the SSD expects the
STATION_STATE to be in the I_T_S. If it isn't,
the SSD refuses to transmit the data. The TRANSMIT
procedure first checks to see if the USER_STATE is
open, if not the USER_STATE_CLOSED parameter
is passed back to the application module. The next thing
TRANSMIT checks is the STATION_STATE. If this
is not open, then TRANSMIT passes back LINK_
DISCONNECTED. This means that the USER_
STATE is open, but the SSD hasn't received a SNRM
commmand from the primary yet. Therefore, the
application software should wait awhile and try again.
Based on network performance, one knows the
maximum amount of time it will take for a station to
be polled. If the application software waits this length
of time and tries again but still gets a LINK_
DISCONNECTED parameter passed back, higher level
recovery must be implemented.

I. AM is set to 0 by the CLOSE Procedure.

2. An I frame is received and a SI interrupt occurs.
3. The SIU_INT procedure enters case 2.
(STATION_STATE = I_T_S, and AM = 0)
4. Case 2 detects that the USER_STATE =
CLOSED_S, sends a RD response and ignores
! th,e fact that an I frame was received.
Therefore it is advised to never call the CLOSE procedure or take the stu out of the AUTO mode when
it is receiving I frames or an I (rame will be lost.
For both the TRANSMIT and SIU _RECV procedures,
it is the application software's job to put data into the
transmit buffer, and take data out of the receive buffer. The SSD does not transfer data in or out of its
transmit or receive bllffers because it does not know
what kind of buffering the application software is implementing. What the SSD does do is notify the application software when the transmit buffer is empty,
XMIT _BUFFER'_EMPTY = 1, and when the receive
buffer is full.
One of the functions that the SSD performs to synchronize the application software to ihe SDLC data link.
However some oUhe synchronization must. also b~ done
by the application software. Remember that the S,SD
does not want to hang up the application software
-waiting for some event to occur on the SDLC data link,
therefore the SSD ,always returns to the application software as soon as possible.
For example, when the application software calls the
OPEN procedure; the SSD returns immediately. The
application softWare thinks that the SDLC channel is
now open and it can transmit. This is not the case. For
the channel to be open, the SSD must receive a SNRM
from the primary and respond with a UA. How~ver,
the SSD does not want to hang up the application software waiting for a SNRM' from the primary before
returnlrtg from the OPEN procedure. When the

Before loading the 'transmit buffer and calling the
TRANSMIT procedure, the application software must
check to see that XMIT _BUFFER:"'EMPTY = I. This
flag tells the application software that it can write new
data into the transmit buffer and call the TRANSMIT
procedure. After the application software has verified
that XMIT _BUFFER_EMPTY = 1, it fills the
transmit buffer with the data and calls the TRANSMIT
procedure passing the length of the buffer as a
parameter. The TRANSMIT procedure checks for three
reasons why it might not be able to transmit the frame.
I f any of these three reasons are true, the TRANSMIT
procedure returns a parameter explaining why it
couldn't send the frame. If the application software
receives one of these responses, it must rectify the problem and try again. Assuming these three conditions
are false, then the SSD clears XMIT _BUFFER_
EMPTY, attempts to send the data and returns the
parameter DA TA_ TRANSMITTED. XMIT_
BUFFER_EMPTY will not be set to 1 again until the
data has been transmitted and acknowledged.

The SIU_RECV procedure must be incorporated into the
application software module. When a valid I frame is
received by the SIU, it calls the SIU_RECV procedure
and passes the length ofthe received data as a parameter.
The SIU_RECV procedure must remove all of the data
from the receive buffer before returning to the SIU_INT
procedure.

Linking up to the SSD

Figure 19-12 shows necessary parts to include in a
PLlM-51 application program that will be linked to the
SSD module. RL51 is used to link and locate the SSD
and application modules. The command line used to
do this is:
19-21

RL51

S:;D,obj,filename.obj,PLM~,l.PB

TO filename

& RAMSIZE(192)
$registe~bank(O) ,
user$mod: do;
$include (reg44.dcl)
declare'
lit
buffer'_length
siu_xmit-.:.buffer
(buffer_iength)
siu_recv _buffer
(buffer_length)
, xmit_buffe~_empty

literally

'literally' ,
'60',

, Iii

byte'

external idata,

oyte
bit

, external,
external;

/* external. procedures */

external;

close: procedure
end close;

external

using I;

open: procedure
end open;

external

using I;

/* local procedures

After the secondary station PO~e~s up,' it enters the
'terminal 'mode', whicll accepts data from the tetmimll.
l:Iowever, before any.'data is 'seI),t, 'the user must confi~ure t~(,': station. The station aiidr,ess and destin,ation
address must be set, and the station must be placed
online. To configure the station the ESC character is
entered at the terminal which puts the protocol converter
into the 'configure mode'. Figure 20-13 showS the menu
which appears'on the terminal screenl
( I) 8044 Secondary Statioll

power_on_d: procedure
end power_on_d;

transmit: procedure
(xmit_buffer_length)
,byte
declare
xmit_buffer _length
end transmit;

dress, set th<; destinatio,n, ad4re~s" and go, qnline and
offline. Setting the; station address sets the, byte in the
STAD reiister. The destination addres~,is the first byte
in the I field. Going online or offline results in either
calling the OPE~ or CLOSE procedure, respectively.

external;
byte;

\ 2345-

Set the Station Address
Set the Destination Address
Go Online
Go Offline
Return to terminal mode
Enter option _

Figure 19-13. Menu for the Protocol Converter

*/ '

siu_recv: procedure (length) public
declare
length
byte,

using \;

Figure 19-12. Applications Module
Link
Information
,
,
PUM·51 and Register B~nks
The 8044 has four register banks. PL/M-51 assumes that
an interrupt procedure never uses the same bank as the
procedure
it
interrupts.
The
USING
attribute of a procedure, or the $REGISTERBANK
control, can be used to ensure that.
The SSD module uses the, $REGISTERBANK(l)
attribute. Some procedures are modified witl;! tile
USING attribute based on the register bank level of the
calling' procedure.
19.2.5 APPLICATION MODULE;
Async to SDLC protocol converter
One of the purposes of this application module ino
demonstrate how to interface software to the SSD.
Another purpose is to implement and test a pratical application. This application software perform& 1/0 \Yith
an async terminal ,through a USART, bufferl< data, and
also performs 1/0 with the SSD. In addition, it allows
the user on the async terminal to: set the statiol;l ad-

In the terminal mode data is buffered up in the secondary station. A Line Feed character 'LF' tells the'secondary station to send an I frame. If more 'than 60 bytes
are buffered in the secondary'station when a 'LF' is
received, the applications software packetizes the data
into 60 bytes or less per frame. If a LF is entered when
the station is offline, an error message comes on the
screen which says 'Unable to Oet Online'.
The secondary station also does error checking on the
async interface for Parity, Framing Error, and Overrun ErrQr. If one of these errors are detected, an error
message is displayed on the terminal 'screen.
,

Buffering
There are two separate buffers in the )application
module: a transmit buffer and a receive buffer. THe
transmit buffer receives data from the USART, and
sends data to the SSD. The receive buffer receives data
from the SSD, and transmits data to the USART. Each
buffer 'is a 256 byte software FIFO. If the tranmsit FIFO
becomes full and no 'LF' character 'is received, the
secondary,sta~ion auwmatically begins sending the ~ta.
In addition, the application mOQule will shut 'ofr't,he
terII).i!1al's trllnsmitter, using CTS until the :fIFO has
been partially emptied. A plock diagram of the buffer"
ing for the protQcol converter is given ,in Fi!\~re' 19-14.
Application Module Sbftware'
,-'

'1 i

,,'

, ;-:,',
I

,..~

I .- "

A block diagr~fIl. of fhe, apllli~tion mo~ul~ sQft~a!e
is given in, Figure.-,l 9-15 ., T.her~, are .three il)terruJlt

MULTIDROP
SOLe DATALINK
W",
II:N

i;;;
Nil:

II:
W

IL
IL

III
W

III

!::

iii

Ul
Z

()

W
II:

....
....
C>

II:

C
Ul
oW

III

CD~

Ul
OW

CD~

II:

..J

~~
II:

I-

!lE

Ul
W

I-

>
111CD
N

Si
Ul

II:

--~I

W'
1-;

ii:

)(,

ii:

()

>
Ul

,
I

..J

()~

z:;

>11:
UlW

CI-

..J

W
II:

:;
II:

()

,Figure 19-14.

iii

11:"
i:;:
.... 11:

ro~;

7
,~

t4~

Block Diagram of Secondary Station
Protocol Converter Illustrating Buffering

19-23

routines in this module: USART _RE<;:V_INT,
USART XMIT_INT, and TIMER_O_INT.
, The fir~ two are for servicing theUSART.
TIMER OINT is used if the TRANSMIT pro-.
cedure j;:;- the SSD is called and does not return
with the DATA TRANSMITTED parameter.
TIMER OINT employs Timer 0 to wait a finite
amount of time before tring to transmit again. The
highest priority interrupt is USART_RECV _INT. The
main program and all the procedures it calls use register
bank 0, USART _XMIT _INT and TIMER_O_INT
and FIFO R OUT use bank I, while USART_
RECV n~T allii all the procedures it calls use register
bank 2~
.

on the 8251A is activated,and this interrupt procedure
is entered. The routine reads the USART status register
to determine if there ,are any errors in the character
received. If there are, the character is discarded and the
ERROR procedure is called wllich prints the type of
error on the screen. If there are no errors, the received
character is checked to see if it's an ESC. If it)s an ESC,
the MENU procedure is called which allows the user
to change the configuration. If neither one of these two
conditions exits the received character is inserted
into the transmit FIFO. The received character mayor
may not be echoed back to the terminal based on the
dip switch settings.
Transmit FIFO

Power_On Procedure

The Power_On procedure initializes all of the chips
in the system including the 8044. The 8044 is initialized to use the 'on-chip DPLL with NRZI coding,
PreFrame Sync, and Timer 1 auto reload at a baud rate
of 62.5 Kbps. The 8254 and the .8251A are initialized next based on the DIP switch values attached to port
1 on the 8044. Variables and pointers are initialized,
then the SSD's Power-Up Procedure, Power_On_
D, is called. Finally the interrupt system is enabled and
the main program is entered.
Main Program

The main program is a simple loop which waits for a
frame transmit command. A frame transmit command
is indicated when the variable SEND_DATA is greater
than O. The value of SEND _DATA equals the number
of 'LF' characters in the transmit FIFO, hence it also
indicates the number of ,frames pending transmission.
Each time a frame is sent, SEND_DATA is
decremented by one. Thus when SEND_DATA is
greater than 0, the main program falls down into the
next loop which polls the XMIT _BUFFER_EMPTY
bit. When XMIT_BUFFER_EMPTY equals I, the
SIU XMIT BUFFER can be loaded. The first byte
in th;-buffer ~loaded with the destination address while
the rest of the buffer is loaded with the data. Bytes are
removed from the transmit FIFO and placed into the
SIU XMIT BUFFER until one of three things
hapPe"n: I. a7 LF, character is read out of the FIFO,
2. the number of bytes loaded equals the size of the
SIU_XMIT_BUFFER, or 3. the transmit FIFO is
empty.
After the SIU XMIT BUFFER is filled, the SSD
TRANSMIT procedurels called and the results from
the procedure are checked. Any result other than
DAT A TRANSMITTED will result in several retries
within :0inite amount of time. If all the retries fail then
the LINK_DISC procedure is called which sends a
message to the terminal, 'Unable to Get Online'.
USART _RECV _I NT Procedure

When the 8251A receives a character,the RxRDY pin

The transmit FIFO consists of two procedures: FIFO_
T IN and FIFO_T_OUT. FIFO_T_IN inserts a
character into the FIFO,and FIFO_ T _OUT removes
a character from the FIFO. The FIFO itself is an array
of 256 bytes called FIFO_ T. There are two pointers
used as indexes in the array to address the characters:
IN PTR T and OUT_PTR_T. IN_PTR_T
points to the location in the array which willstore the
next byte of data inserted. OUT _PTR_ T points to
the next byte of data removed from the array. Both
IN PTR T and OUT PTR T are declared as
byte;. TheFIFO_T_ IN Procedme receives a character
from the USART _RECV _INT procedure and stores
it in the array location pointed to by IN_PTR_T, then
IN PTR T is incremented. Similarly, when FIFO_
TOUT ;-; called by the main program, to load the
XMIT BUFFER, the byte in the array pointed
to byOUT_PTR_T is read, then OUT_PTR'--..T is
incremented. Since IN_PTR_ T and OUT _PTR_ T
are always incremented, they must be able to roll over
when they hit the top of the 256 byte address space. This
is done automatically by having both IN_PTR_ T and
OUT PTR T declared as bytes. Each character
inserted intOthe transmit FIFO is tested to see if it's
a .LF. If it is a LF, the variable SEND_DATA is
incremented which lets the main program know that it
is time to send an I frame. Similarily each character
removed from the FIFO is tested. SEND _DATA is
decremented for every LF character removed from the
FIFO.

IN PTR T and OUT PTR T are also used to indic-;Ue ho;-many bytes ;;:e in the FIFO, and whether
it is full or empty. When a character is placed into the
FIFO and IN PTR T is incremented, the FIFO is full
ifINPTR-T eQualS OUT_PTR_T. When a
character is r~d from the FIFO and OUT _PTR_ T
is incremented, the FIFO is empty if OUT _PTR_ T
equals IN_PTR_ T. If the FIFO.is neither full nor
empty, then it is in use. A byte called BUFFER--,STATUS T is used to indicate one of these three conditions. The application module uses the buffer statu~
information to control the flow of data into and out
of the FIFO. When the transmit FIFO is empty, the
main program must stop loading bytes into the SIU_
19-24

r--~-------~--------------------MAIN PROGRAM

-=::J -I 1 11---_ _ _ _ _ _ _ _---,
FIFO_T_OUT

"11

C
c

iiJ

....

'P
....

~
OJ

....

'P
I\:)
U'!

FIFO_T ...,!N

C
-0

-I!

iii'

J,.

1
I

iii
3

1/1

I
I
I

(/)

=
:e

II)

iiJ

I
J
[

TIMER_O_INT]

I
1
I

I FIFO_R_OUT I
:
1_______________________________________________ .....1

•

object code file at compile time, which lists the addresses
of each secondary station on the network.

XMIT_BUFFER. Just before the FIFO is full, the
async input must be shut off using CTS. Also if the
FIFO is full and SEND_DATA=O, then SEND_
DATA must be incremented to automatically send the
data without a LF.

Remote Station Database

The,primary station keeps a record of each secondary
station on the network. This, is called the Remote
Station Database (RSD). The RSD in this software is
an array of structures, which can be found in the listing
and also in Figure 19-16. Each RSD stores the necessary
information about that secondary ,station,

Receive FIFO

Th~ receive FIFO operates in a similiar fashion as the
transmit FIFO does. Data is inserted into the receive
FIFO from the SIU _RECV procedure. The SIU_
RECV procedure is called by the SIU _INT procedure
when a valid I frame is received. The SIU_RECV procedure mearly polls the receive FIFO status to see if it's
full before transfering each byte from the SIU_
RECV _BUFFER into the receive FIFO. If the receive
FIFO is full, the SIU _RECV procedure remains polling the FIFO status until it can insert the rest of the
data. In the meantime, the SIU AUTO mode is responding to all polls from the primary with a RNR supervisory
frame. The USART_XMIT _INT interrupt procedure
removes data from the receive FIFO and transmits it
to the terminal. The USART transmit interrupt remains
enabled while the receive FIFO has data in it. When
the receive FIFO becomes empty, the USART transmit
interrupt is disabled.

To add additional secondary stations to the network,
one simply adjusts the NUMBER_OF _STATIONS
declaration, and adds the additional addresses to the
SECONDARY _ADDRESSES table. The number of
RSDs is automatically allocated at compile time, and
the primary automatically polls each station whose
address is in the SECONDARY _ADDRESSES table.
Memory for the RSDs resides in external RAM. Based
on memory requirements for each RSD, the maximum
number of stations can be easily buffered in external'
RAM. (254 secondary stations is the maximum number
SDLC will address on the datalink; i.e. 8 bit address,
FF H is the broadcast address, and 0 is the nul address.
Each RSD uses 70 bytes of RAM. 70 x 254 = 17,780.)
The station state, in the RSD structure, maintain the
status of the secondary. If this byte indicates that the
secondary is in the DISCONNECT _S, then the primary
tries to put the station in the 1_T _S by sending a
SNRM. If the response is ali VA then the station state
changes into the 1_T _So Any other frame received
results in the station state remaining in the
DISCONNECT_S. When the RSD indicates that the
station state is in the 1_T _S, the primary will send
either a I, RR, or RNR command, depending on the
local and remote buffer status. When the station state
equals GO_ TO--"DISC the primary will send a DISC
command. If the response is an VA frame, the station
state will change to DISCONNECT _S, else the station
state will remain in GO_TO _DISC. The station state
is set to GO_TO_DISC when one of the following
responses occur:

19.2.6 PRIMARY STATION

The primary station is responsible for cQntrolling the
data link. It issues commands to the secondary stations
and receives responses from them. The primary station
controls link access, link level error recovery, and the
flow of information. Secondaries can only transmit
when polled by the primary.
Most primary stations are either micro/minicomputers,
or front end processors to a mainframe compu~er. The
example primary station in this design is standalone.
It is possible for the 8044 to be used as an intelligent
front end processor for a microprocessor, implementing the primary station fUnctions. This latter type of
design would extensively off-load link control functions
for the microprocessor. The code listed in this paper
can be used as the basis for this primary station design.
Additional software is required to interface to the
microprocessor. A hardware design example for interfacing the 8044 to a microprocessor can be found in
the applications section of this handbook.

I. A receive buffer overrun in the primary.

2. An I frame is received and Nr(P) t-Ns(S).
3. An I fral\1e or a Supervisory frame is received and
Ns(P) + 1 f. Nr(S) 'and Ns(P) t-Nr(S).

The primary station must know the addresses of all the
stations which will be on the network. The software for
this primary needs to know this before it is compiled,
however a more flexible system would down load these
parameters.
From the listing of the software it can be seen thai the
variable NUMBER_OF _STATIONS is a literal
declaration, which is 2 in this design example. There
were three stations tested o'n this data link, two secondaries and one ,primary. Following the NUMBER_
OF _STATIONS declaration is a table, loaded into the
19-26

4. A FRMR response is received.
5. An RD response is received.
6. An unknown response is received.
The send count (Ns) and receive count (Nr) are also
maintained in the RSD. Each time an I frame is sent
by the primary and acknowledged by the secondary, Ns
is incremented. Nr is incremented each time a valid I
frame is received, BUFFER_STATUS indicates the
status of the secondary stations buffer. If a RR response
is received, BUFFER_STATUS is set to BUFFER_

several procedures. The POWER_ON procedure
begins by initializing the SIU's DMA and enabling the
receiver. Then each RSD is initialized. The DPLL and
the timers are set, and finally the TIMER 0 interrupt
is enabled.

READY. If a RNR response is received, BUFFER_
STATUS is set to BUFFER_NOT_READY.
Buffering

The buffering for the primary station is as follows:
within each. RSD is a 64 byte array buffer which
is initially empty. When the primary receives an I frame,
it looks for a match between the first byte of the I frame
and the addresses of the secondaries on the network.
If a match exits, the primary places the data in the RSD
buffer of the destination station. The INFO_L.ENGTH
in the RSD indicates how many bytes are in the buffer.
If INFO LENGTH equals O,then the buffer is empty. The Primary can buffer only one I frame per station. If a second I frame is received while the addressed secondary's RSD buffer is full, the primary cannot
receive any more I frames. At this point the primary
continues to poll the secondaries using RNR supervisory
frame.

The main program consists of an iterative do loop· within
a do forever loop. The iterative do loop polls each secondary station once through the do loop. The variable
STATION NUMBER is the counter for the iterative
do statem~ which is also used as an index to the
array of RSD structures. The primary station issues one
command and receives one response from every secondary station each time through the loop. The first statement in the loop loads the secondary station address,
indexed by STATION_NUMBER into the array of the
RSD structures. Now when the primary sends a command it will have the secondary's address in the
addre~s field of the frame. The automatic address
recognition feature is used by the primary to recognize
the response from the secondary.

Primary Station Software

Next the main program determines the secondary
stations state. Based on this state, the primary knows
what command to send. If the station is in the
DISCONNECT _S, the primary calls the SNRM_P

A block diagram of the primary station software is
shown in Figure 19-17. The primary station software consists of a main program, one interrupt routine, and

RSD.

. STATION-ADDRESS
STATION-STATE
NS
NR
BUFFER-STATUS
INFO-LENGTH
DATA (0)

OATA (63)

Figure 19-16. Remote Station Database
Structure

19-27

procedure to try apd ,puUhe secondary in the 1_'I' ~
S. If the station state is in the GO 'I' 0 DISC state
the DISC_P is calJerJ, to try and p~t th;5econdary i~
the L_D _So If the secondary is in neither one of the
above two states, then it is in the I 'I' S. When the
secondary is in the 1_'I' _S, the primarycould send one
of three commands: I, RR, or RNR. If'the RSD's
buffer has data in it, indicated by INFO _LENG'I'H
being greater than zero, and the secondary's
BUFFER_S'I'A'I'US equals BUFFER_READY, then
an I frame will be sent. Else if RPB=O, a RR supervisory frame will be sent. If neither one of these cases
is true, then an RNR will be sent. 'I'he last statement
in the main program checks the RPB bit. If set to one,
the BUFFER_'I'RANSFER procedure is calJed, which
transfers the data from the SIU receive buffer to the
appropriate RSD buffer.
Receive Time Out

Each time a frame is transmitted, the primary sets a
receive time out timer; 'I'imer O. If a response is nOt
received within a certain time, the primary returns to
the main program and continues polling the rest of the
stations. 'I'he minimum length of time the primary
should wait for a response can be calculated as the sum
of -the following parameters.
I. propagation time to the secondary station
2. clear-to-send time at the secondary station's DCE

3. appropriate time for secondary station processing
4. propagation time from the secondary station
5. maximum frame length time
'I'he clear-to-send time and the propagation time are
negligible for a local network at low bit rates. However,
the turnaround time and the maximum frame length
time are significant factors. Using the 8044 secondaries
in the AU'I'O mode minhnizes turnaround time. 'I'he
maximum frame length time comes from the fact the
8044 does not generate an interrupt from a received
frame until it has been completely received, and the CRC
is verified as correct. 'I'his means that the time-out is
bit rate dependent.
Ns and Nr check Procedures

Each time an I frame or supervisory frame is received,
the Nr field in the control byte must be checked. Since
this 'data link onlyalJows one outstanding frame, a valid
Nr would satisfy either one of two equations;
Ns(P) + 1 = Nr(S) the I frame previously sent by the
primary is acknowledged, Ns(P) = Nr(S) the I frame
previously sent is not acknowledged. If either one of
these two cases is}rue, the CHECK_NR procedure
returns a parameter of 'I' RUE; otherwise a FALSE
parameter is returned. If an acknowledgement is
Jeceived,the Ns byte in the RSD structure is incremented, and the Information buffer may be cleared.
Otherwise the information buffer remains full.

MAIN PROGRAM

BUFFER

TRANSFER

\TIMER_O_INT!

Figure 19-17.

Block Diagram of Primary
Station Software Structure

19-28

When an I frame is received, the Ns field has to be
checked also. If Nr(P) = Ns(S), then the procedure
returns TRUE, otherwise a FALSE is returned.
Receive Procedure

The receive procedure is called when a supervisory or
information frame is sent, and a response is received
before the time-out period. The RECEIVE procedure
can be broken down into three parts. The first part is
entered if an I frame is received. When an I frame is
received, Ns, Nr and buffer overrun are checked. If
there is a buffer overrun, or there is an error in either
Ns or Nr, then the station state is set to GO_TO_
DISC. Otherwise Nr in the RSD is incremented, the
receive field length is saved, and the RPB bit is set. By
incrementing the Nr field, the I frame just received is
acknowledged the next time the primary polls the secondary with an I frame or a supervisory frame.
Setting RBP protects the received data, and also tells

the main program that there is data to transfer to one
of the RSD buffers.
If a supervisory frame is received, the Nr field is
checked. If a FALSE is returned, then the station state
is set to GO_TO_DISC. If the supervisory frame
received was an RNR, buffer status is set to not ready.
If the response is not an I frame, nor a supervisory
frame, then it must be an Unnumbered frame.

The only~ Unnumbered frames the primary recognizes
are UA, DM, and FRMR. In any event, the station state
is set to GO TO DISC. However if the frame
received is a FRMR;-Nr in the second data byte of the
I field is checked to see if the secondary acknowledged
an I frame received before it went into the FRMR state.
I f this is not done and the secondary ackoowledged an
I frame which the primary did not recognize, the
primary transmits, the I frame when the secondary
returns to the I_T_So In this case, the secondary would
receive duplicate I frames.

19-29

APPENDIX A
8044 SOFTWARE FLOWCHARTS

1g.:30

POWER-ON-D PROCEDURE'

USER-STATE

= CLOSED-S

STATION-STATION

= DISCONNECT-S

TBS

= SIU-XMIT-BUFFER'STARTING ADDRESS

RBS

= SIU-RECV-BUFFER STARTING ADDRESS

RBL

= BUFFER LENGTH

ENABLE SIU RECEIVER: RBE

XMIT-BUFFER-EMPTY

RE.TURN

CLOSE PROCEDURE

RETURN

OPEN PROCEDURE

USER

STATE = OPEN_S

RETURN

Figure 19-18. Secondary Station Driver Flow Chart
19-31

XMIT-UNNUMBERED

PROCEDU~E

TRANSMIT PROCEDURE
STATUS

= USER-STATE-CLOSE

STATUS =
LINK_DISCONNECTED

STATUS
')VERFLOW

XMIT-BUFFER-EMPTY

TBL

= XMIT-BUFFER-LENGTH

I-FRAME:-LENGTH

STATUS

XMIT-BUFFER-LENG:rH

DATA-TRANSMITTED

Figure 19-19_ Secondary Station Driver Flow Chart

19-32

XMIT-FRMR PROCEDURE

FRMR-BUFFER (2)

= REASON

STATION-STATE

= FRMR-S

SEND FRMR
FRAME

Figure 19-20_ Secondary Station Driver Flow Chart

19-33

IN·DISCONNECT·STATE PROCEDURE

SNRM·RESPONSE PROCEDURE

Figure 19-21. Secondary Station Driver Flow Chart

19-34

RUPI™.44

IN-FRMR-STATE PROCEDURE

Figure 19-22. Secondary Station Driver Flow Chart

19-35

COMMAND DeCODE PROCEDURE

Figure 19-23. Secondary Station Driver Flow Chart

19-36

SIU·INT PROCEDURE

:!!
c:

iil
....

CALL COMMAND·DECODE

.".

(II

n
0

:::J

11---------,

Y
XMIT·BUFFER·EMPTY
1

CALL

CI.

XmJ~~~~~BERED

I»

.... -<

-l

::D

C
"CJ

I»

:::J

CALL XMIT·FRMR

...~

~"
0

':r
I»
~

•I

CALL COMMAND DECODE

t
.".

MAIN PROGRAM

LOAD DESTINATION
ADDRESS IN FIRST
BYTE OF SIU-XMIT
BUFFER

LOAD INFORMATION
INTO SIU XMIT-BUFFER
SIU BUFFER LENGTH
OR FIFO-T EMPTY

OUTPUT MESSAGE
TO TERMINAL
'UNABLE TO GET ON LINE'

Figure

19-25~

Application Module Flow Chart

19-38

RUPI TIt·44

USART·RECV·INT INTERRUPT PROCEDURE

Figure 19-26. Application Module Flow Chart

~1g:.39

OUTPUT MENU
. TO TERMINAL

MENU PROCEDURE

CALL OUTPUT-MESSAGE
'ENTER THE STATION ADDRESS:~_
CALL GET -HEX
SHIFT TO LEFT BY FOUR'

LOAD ADDRESS
INTO STAD
CALL OUTPUT-MESSAGE
'THE NEW STATION ADDRESS:_~

N',

CALL OUTPUT-MESSAGE
'ENTER THE DESTINATION ADDRESS: .. __
CALL GET-HEX
SHIFT TO LEFT BY FOUR

LOAD ADDRESS
INTO DESTINATION-ADDRESS

CALL OUT-MESSAGE
'THE NEW DESTINATION ADDRESS

RETURN

Figure 19-27. Application Module Flow Chart

J 9.:40

IS:~

ERROR PROCEDUR,E

RESET ERROR FLAGS ON USART

Figure 19-28 Application Module Flow Chart

19-41

FIFO-T-OUT PROCEDURE

Figure 19-29 _ Application Module Flow Chart

19--42

FIFO·T·IN PROCEDURE

RETURN

Figure 19-30. Application Module Flow Chart

19-43

SIU·RECV PROCEDURE

Figure 19-31. Application Module Flow Chart

19-44

POWER ON

INITIALIZE SIU REGISTERS

I
FOR EACH STATION
INITIALIZE RSD RECORDS
'1. STATION-ADDRESS
2. STATION-STATE
DISCONNECT
3. BUFFER-STATE = BUFFER-NOT-READV
4. INFO-LENGTH = 0

I
RETURN

Figure 19-32. Primary Station Flow Charts

19-45

ADDRESS NEXT STATION
SET STAD

PRIMARY STATION MAIN PROGRAM

CALL SEND-SNRM

CALL SEND-DISC

Y
CALL XMIT I T S
(T-I-FRAME) t-------~

CALL XMIT·I-T·S
(T-RR)

CALL BUFFER·TRANSFER

Figure 19-33. Primary Station Flow Charts

19-46

SEND·SNRM PROCEDURE

SEND·DISC PROCEDURE

~
N

STATION·STATE = DISCONNECT!S
BUFFER·STATUS = BUFFER·NOT·READY

Figure 19-34. Primary Station Flow Charts

19-47

XMIT·I·T·S PROCEDURE
BUILD CONTROL
FIELD USING EITHER
I, RR, RNR
AND NR AND/OR NS

CALL RECEIVE

XMIT PROCEDURE

Figure 19-35. Primary Station Flow Charts

19-48

BUFFER-TRANSFER PROCEDURE

MOVE DATA FROM
SIU·RECV·BUFFER
TO RSD BUFFER

Figure 19-36. Primary Station Flow Charts

19-49

CHECK_NR PROCEDURE

CHECK-IllS PROCEDURE

F;igure 19-37. Primary Station Flow Charts

19-50

REMOTE BUFFER·STATUS

= BUFFER·READY

"11

cO
c
iil

...
tco

'"0

:::!.

<. . .

18
19
20
21
22
23
24

2
2
2
2
2
2

IDATA,

OPEN: PROCEDURE PUBLIC USING 21

PUBLIC
PUBLIC,

BIT PUBLIC,

2
2
1

~60'.

LIT
BYTE
BYTE

PROCEDVRE

PUBLIC USINg 0,

USER_STATE-CLOSED_S,
STATION_STATE-DISCONNECT _9;
TDS-. SIU_XI"IIT_BUFFSHO),
RBa-. SIU_RECV_BUFFER(O);
RBL-DUFFER_LENGTH,
RBE"l,
/* En.ble the SIU'. receiv.,. *1
XI1I TJlUFFERJ;I1PTY-l,
END POWER_ON_Di

TRANSMIT:

PROtEDURE eXMIT JUFFERJ-ENGTH) BYTE

DECLARE XI1IT _BUFFER_LENOTH
I
StATUS

PUBLIC USING 01

BYTE,
BYTE

AUXILIARY,.

BYTE

AUXILIARY;

IF USER_STATE-CLOSEO_S
THEN STATUS-USER_STATE_CLOSED.
ELSE IF STATION_STATE-DISCONNECT_S
THEN STATUS-LINKJHSCONNECTED,
ELSE IF XI1IT _BUFFER.J-ENOTH>BUFFER_LENQTH
THEN STATUS-tlVERFLOW;
ELSE 00,

19-54

09/20/B3

PAgE

20:

XI'IIT JlUFFERj: .... TY.OI
TBL.XIIITJlUFFER_LENOTH,

3
3

38
39
40
41
42

3
3
3
2
1

TBF-l,
STATUB-D"T"_TRANSI'\ITTEDI
ENDI
RETURN STATUSI
END TR"NSI'fITI

XI'IIT _UNNUtIBERED: PROCEDURE (CONTROL_BYTE) I

45
41>
47
48
49
50

2
2
2
3
3
2

51
2

2
2

54
5'
57
5B
5'
1>0

I_FRN1EJ.ENQT"X"ITJlUFFER~ENOTHi

DECLARE CONTROL_BYTE

BYTE,

TCB.CDNTRDL_BYTE,
TBF-IJ
RTB-l,
DO WHILE NOT 81,

END,
81-01

2
3
3
3
2

_II...RESPONSE: PROCEDURE ,
STATION_STATE-I_T_9;
NSNRaGl
IF (RCB AND 10H) <> 0
Respond if polled
THEN DO,
TBL-o;
CALL XI'IIT_UNNUf18EREDCUA)J

END,
IF XMITJlUFFER-.EI'IPTY-O

/* I' lin I fI ........ ,
tb.n .... ,to". it

THEN DOJ

62
63
64
65

1* Sto". hngtb in ca •• station
,~ ...... t btl FRM. SNAM .tc

END XIIIT _UNNUI'\BEREDI

3
3
3

_I,

h,t p.ndlng 1or.ns.i5sian

TBL-I.,FRAI1EJ-ENQTH,
TBF-l,
ENOl

END SNRI'I...RESPDNSE,

XI'IIT_FRI1R: PROCEDURE (REASON)

TCB-FRI1R.

70
71
72

2
2

TB&-. FRI'IR_BUFFER(O) ,

73
74
75

2
3
3

2~: ~7

DECLARE REASON

BYTE,

TBL-3,
FRI'IR_8UFFER (0)-RC8;
SIHP nibb Ie, in NSNR
FRMR __ UFFER(I)-CSHL(NSNR AND OEH).4) OR
DO CASE REASON,
FRMRJiUFFER(2)-OlH,
UNASSIQNED_C

*'
'*

SHRC0
THEN DO.
TBF-S,

Rn-l,
DO

WHILE~NOT

SII

ENOl

SI-o.
END,

IF (UBER_STATE-OPEN_S) AND «RCB AND O£FH).SNRM})
THEN CALL 9NR"-"ESPONBE,

ELSE IF (RCB AND lQH) <> 0
THEN DO.

TBL-o,

CALL XMIT _lJNNUfII8ERED( DI1);

ENOl
END IN_DISCONNECT_STATEI
IN_FRMR_STATE: PROCEDURE. 1* Called bV StU_tNT when .. freen. ba. be.n l'ec:eived
when in 10he FMMR .'hte *1
IF (RCB AND-OEFH)-SNRM
THEN DO,
CAL.L SNRMJESPONSE.

T8S" SIU_XMIT_BUFFER(O),
ENDI

1* Restore tl'ansllIlt buttl.,. 9tal't address *1

ELSE IF (RCB AND OEFH)-DISC
THEN DO.
STATION_STATE-DISCONNECT _5i

1* RUltor. tT'ansmlt buffe.,. start address */
IF (RCB AND 10H)<> 0
THEN DO,
TBL-Oi
CALL XI'1IT_UNNUMBERED(UA),

T8S-, SIU_XMIT_BUFFER(O)J

ENOl
END;

ELSE DO,

1* Recuve contT'ol bvt. ill somethIng other than DISC
IF (RCB AND 10H) <> 0
THEN 00,
TDF=l,
RTS.. l,

19-56

or SNRM *1

09/li!O/e~

PAGE

intJ
PL'I'I-51 COMPILER
120
121
122
123

5
5
4
3

20- 24: 47

0fP/20/B3

DO WHILE NOT SII
END,

ENOl
EN'"
END IN_FRfItR_STATEI

124

COMMAND_DECODE:

P~OCEDURE

125

126

IF (RCB AND OEFtO-SNRM
T~N
CALL SN~M_RESPONSE'

ELSE: IF (RCB AND OEFH)-DISC
THEN 001

128

130
131

3
3

133
134
135
136

4
4
4
3

137

13'1

141

9T AT ION_ST ATE-D1 SCONNECT _So

IF (RCB AND 10H)OO
THEN DOl
TBL-OJ

CALL XMIT_UNNUr1BERED(UA)I
ENOl
ENOl
ELSE IF (ReB AND OEFH) -TEST
THEN DOl
IF (ReB AND lOH)O 1* Re9pond i f polled *1
THEN DOl
FOR BOY-I, SEND THE TEST RESPONSE WITHOUT AN I FIELQ
IF (BOVat)

THEN DO.
143
144
145
146
147
148
149

5
5
5
5
5
5
5
5

152

154
155

5
5
5

TBL-O,
CALL XMIT_UNNUP1BEREDCTEST OR lOH)1
END.
ELSE DOl 1* If no BOV • • •nd received I Ueld back to primal'W *1
TBL-RFL.
TSS=RBSI
•
CALL XMIT_UNNUMBEREDCTEST OR lOH)J
T88-. SIU_XI'IIT_BUFFER(O),
Resto1'. TBS

END,

1* If an I 'rame .... s pending • • ltt It up again

156

IF XMIT _BUFFER-.EMPTY*O
THEN,DOJ.
TBL'" I _FRAl'IE_LENQTH.
TBF-lj
ENP,
END,

157
158
159

160

162

163

IF XI'1IT _BUFFER_EI1PTY •
THEN TaL ... O.

165

TBF ... 1.

3
ELSE IF (RCB AND 01H) • 0 1* Kicked out of the AUTO mode becaus.
an I f1'a.e was "eceiv.d whlltt RPB • 1 *1
THEN DO,
AM ... 1;

1* Send an AUTO mod. ,..sponse *1

19-57

PAGE

intJ
PL/t'fI-~l

20: 24: 47

CDMPIl.. ER

I ....
167

3
3

168

09/20/83

PAO£

09/20/93

PAGE

RTS" 11
ENOl

169

PROCE~RE

170

171

DECLARE

172
173

2
2

81-0,

175

StU_INT

INTERRUPT 41

BYTE

AUXILIARY,

IF STATION_STAfE<> I_T_9 1* Mu-.t be in NON-AUTO mode *1

THEN DO.

177
178
179
18Q
lSI
IS2
183
IS4

IF RBE-O 1* Received II 'T'ame?

Give response

THEN DO.

DO CASE STATION_STATE,
CALL IN-PISCONNECT_STATE.
CAL.L IN_FRMR_STATEI
ENOl
RBE-!I
ENOl

5
5
5
4
4
3
3

RETURN,
ENOl

1* If the program " •• ch •• this point. STATION_STATE-I_T_S
which m•• ns the SIU eithe" w.s. or shl1 h 1n the AUTO MODE *1
IS5

IS7

IF (RCB AND OEFH)-DISC
THEN CALL COMMAND-PECODE.

189

EL.SE IF USER_STATE-CL.Q9ED_S

I'll
192
193
194

4
4
4
3

196

19S

200
201
202
203
204

4
4
3
3
3

205
206

3
3

208

IF AM-O
THEN DO.

THEN DOl
TaL-Oj

CALL XMIT_UNNUMBERED(REGJ>ISC);
END.
ELSE IF SES=t
THEN CALL XMITJ'RMReSES_ERR).
ELSE IF BOV=1

THEN Dill 1* DON'T SEND FRMR IF A TEST WAS RECEIVED*I

ELS~

IF (RCB AND OEFH)-TEST
THEN CALL COMMAND_DECODE.
ELSE
CALL XHIT_FRMR(BUFF_OVERRUN)I
ENOl
CALL COMMAND_DECODE.

RBE=l.
END.
ELSE DO. 1* MUST STILL BE IN AUTO MODE *1
IF TBF=O
THEN XMITJUFFER~MPTyaL
1* TMANSMITTED A FRAME *1
IF RBE=O
THEN DCh

COMPILER

PL/I't-~l

210

211

212

213

4
4
3
I

214
215

216
:il17

20· 24: 47

RUPI-44 Secondartj Station Driver
RBP-L 1* RNR STATE *1
RBE=l. 1* RE-ENABLE RECEIVER *1
CALL SIU.-RECV{RFU,
RSP-O, 1* RR STATE *1
ENOl

ENDJ
END SlU_INTI

END MAIN*"IJD.

WAANINOS'
4 IS THE HIGHEST USED INTERRUPT

MODULE INFORMATION:
CODE SIZE
CONSTANT SIZE

DIRECT VARIABLE SIZE
INDIRECT VARIABLE SIZE
BIT SIZE
BIT-ADDRESSABLE SIZE
AUXILIARy VARIABLE SIZE
MAXIMUM STACK SIZE
REGISTER-BANKeS) USED:
460 LINES READ
o PROQRAM ERROR e5)
END ,OF PL/M-51 COMPILATION

eSTATlC+OVERLAYABLE)
• 02BFH
6550
= OOOOH
00
3FH+02H
63D+
3CH+00H
60D+
OlH+OOH
1D+
OOH+OOH
00+
'"' 0006H
60
,. 0017H
230

2D
00
OD
00

1 2,

19-58

inter
PL/~-51

COMPILER

IBIS-II

PLlI1-~l

Applic.Uon Moduh' A.... nc:/SDLC PT'otocol convertltl'
VI 0

CDf1PILER INVOKED BY'

.TITLE
.debug

: 412: pl ..

18 '0-:53

'1 :

412- unot • • "e

('AppUc.Uon Module

S,..gi.te"b.nk (0)
5

u •• "tmod: dOl
.NOLIST
DECLARE
LIT
TRUE
FALSE

FOREVER
ESC

LF
CR
BS
BEL
EMPTY
INUSE

FULL
USER_STATESLOSED
LINK_DISCONNECTED
OVERFLOW
DATA_TRANSI1ITTED

LITERALLV
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

'LITERALLY',
'OFFH'.
'OOH'.
'WHILE 1 '.

LIT

'60',

'IBH'.
'OAH',
'ODH',
'08H'.
'07H',
'OOH',
'OJH'.
'02H'.
·OOH'.
'01H',
'02H',

'03H',

1* BUFFERS *1
BUFFER_LENGTH

SIU~MIT _BUFFER (BUFFER_LENGTH)
BYTE
SIU _RECV _BUFFER (BUFFER_LENGTH)
BYTE
FIFO_THiZ36)
BYTE
AUXILIARY.
" AUXILIARY.
IN_PTR_T
BYTE
AUXILIARY,
OUT_PTR_T
BYTE
BUFFER_STATUS_T
BYTE
AUXILIARY,
FIFO_R(256)
BVTI::
AUXILIARY.
IN_PTR_R
BYTE
AUXILIARY.
AUXILIARY,
OUTJ'TRJI
BYTE
AUXILIARY,
BUFFER_STATUS_R
BYTE

LENGTH
CHAR
I

USARTS"D
DESTINATION_ADDRESS
SEND_DATA

RESULT
ERR_I'IESSAOE_INDEX
ERR_"ESSAGEJ'TR

BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
WORD

EXTERNAL

lDATA.

EXTERNAL,

AUXILIARY.
AUXILIARY.
AUXILIARY.
AUXILIARY.
AUXILIARY.
AUXILIARY.
AUXILIARY.
AUXILIARX·
AUXILIARY.

PARITY(*) BYTE CONSTANT (LF. CR. 'PaT'itl,l ET'T'oT' Detected'.LF.CR.OOH).
FRAME<*) BYTE CONSTANT (LF. CR. 'FTamlng ETT'OT' Detected '. LF, CR. OOH).

19-59

09/19/83

PAGE

inter
PL/H-51 COMPILER

Application Moduli. A• .,nc/SDLC Prottlcol conv.,,'hT

lB,50.,53

09/19/83

PAQE

OVEft_RVN(*) BVTE CONSTANT(LF.CR. 'Overrun E,,1'o," D.t.ct.d',t..F.CR,O),
LINKC.) BYTE CONSTANT(LF, CR. 'Unable to O.t Onlln.',LF.CA.OOH),
DEST..ADDR(') BYTE CONSTANT(CR. ~F. ~F.
'Ent ... th. d •• UnatiDn .dd" •••. _'I 8S. BS. 0)'
D..ADDR..AC~(*' BYTE CONSTANTO 1* Th.n conhnue to .end the 1I •••• g. *1
THEN DOl
USART ..,DATA - ~S9AgE(ERRJ1ESSAQE_INDEXlI
ERRJlESSAQE_INDEX-ERR_MESSAQE_I NDEX + 11

ENOl
1* If! m•••• , . h don. T' • • ,.t ERROR_fLAG and .hut off! inte"rupt If FIFO is empty *1
ERROR_FLAQ-O.
IF BUFFER_STATUSJ '. EMPTY
THEN EXt_OJ
END.

ELSE 00;

4
4
ENOl

END USART_XMIT _INTJ

120

SIU_RECV.

PROCEDURE (LENGTH) PUBLIC USING I.

I'll

122

DECLARE LENGTH
I

123
124
125
126
127

3
4
4
3
3

DO X-O TO L.ENOTH-l;
DO WHIL.E BUFFER_STATUSJ-FUL.LJ 1* Check to Ie. if! flfo

BYTE.
BYTE

AUXILIARY,

lSi

full *1

ENOl
CALL FIFO..,R_IN(SIU_RECV_BUFFER( I»,
ENOl

12B
129

FIFO_T_IN: PROCEDURE (CHAR) USING 2;

130

DECLARE CHAR

131
132
133

:I
2

FIFO_T< IN_PTR_T)-CHAR.
IN_PTR_T-IN_PTR_T+l;
IF CHAR-LF
THEN SEND_DATA.SEND_D~TA+l.

135

137

139
140
'141

3
3
3

143
144

3
1

BYTE.

IF BUFFER_STATUS_T-EMPTY
THEN BUFFER_BTATUS_T-INUSEi
,
ELSE IF «BUFFER_STATUS_T-INUSE) AND (IN_PTR_T+20-0UTJTR_T»
THEN DO, 1* Stop recephon u.i.ng CTS *1
USART_BTATUS. UBART_CMD-UBART_CHD AND NOT<2OH)1
BUFFER_STATUS_T-FUL.LI
IF SEND_DATA=-O
THEN SEND_DATA=11 I*If th. buffe" is full and no LF
ha1i b~~n received then •• nd d_t. *1

END.

19-64

PLllt-a! CDIII'ILER

145
146
147
148
149

"a
2

153
154
ISS
ISO

lB' 50. 53

FIFD_T _OUT:

PROCEDURE BVTE
BVTE

CHNI-FIFD_TCOUT _PTR_T).
OUT JTR_T-ouT_PTR_T+ll
IF OUTJlTR_T-IN_PTR_T

/* Th.n FIFO_T is .,.ptv *1

THEN DO.

3
3
3
3
3

EA-OI
BUFFER_STATUS_T-EMPTY,
BEND_DATA-OI
EA-l1

END.
ELSE IF «8UFFER_STATUS_T-FUL.L) AND (OUTJTR_T-eO-IN_PTR_T»

THEN DOl
lSI!
159
100
161
143
160

USART_STATUS. USART_CIIDooUSART_CIID DR 20H.
BUFFER_BTATUS_T-INUSE.

3
3
2
2
1

IF (CHAA""-" AND SENDJ)ATA>O) THEN SEND.JlATA-SEND_DATA-l,
RETURN. CHAR.
END FIFO_T _OUTI

145

ERROR: PROCEDVRE (STATUS) USINO 2.

144

DECLARE STATUS

167

169

171

IF (STATUS AND OSH)<>O
THEN EARJEBSAOE_PTR-. PARITY.
ELSE IF (STATUS AND 10H)<>0
THEN ERR_HESSAOE_PTR•. OVER_RUN.
EL§ IF (STATUS AND 20M) <>0
THEN ERRJlESSAOEJTR-. FRAIIE.

173

17.
175
176

2
2
2

177

179

leo

BYTE.

ERR_IlESSAQE_'NDEX - 0,
ERROR_FL.AQ-1.

£h-1,

1* Tu,," on T. Int_r:rupt */

END ERRoR;

178

181
182
Ie:!
III.

END.

2
2
2
2
3

LINK_DISC: PROCEDURE ,

DECLARE MESBMEJTR WORD
MESSAQE
BASED
.J
BYTE
EX I_STORE
BIT,

EX l_STORE_EXl 1
EXt-O,

AUX ILlAJlv.
IlESSABEJTR ( 1 )
AUXILIARY.

IYTE

CONSTANT,

1* Shut off •• Vnc trAns",lt int."rupt *1

f1ESSAGE_PTR-. lIM!..
~-O,

DO WHILE (t1ESSME(.J)<>O),

19-65

0'l/19/B3

PAQE

inter
PL/I'I-51 Cot1PILEft

195
196
197
lBB
199
190
191

Applic.tian l'Iadul.: AI1Jnc/SDLC Pl'otoco'l converta,.

'* w.it

DO WHILE (UBART_STATUS AND OlH)-o1

END,

3
3
3

USART"pAT A-MESSAGE (J);
,J-,J+IJ

ENOl
EXt-EXt_STORE;

1* R.,to,. ••• ."nc tranl.it int.",.upt *1

END LINKJ)ISC.

192
193

:I
:I

co:

194
195
196

3
3

DO WHILE (uSART _STATUS AND OIH) - 0;

USARTJ)ATAIitCHAR.

197

'aT' TxRDY Dn

PROCEDURE (CHAR) USING 21

DECLARE CHAR

BYTE,

ENDI
END COl

199

199
200
201

3
3
2

202

CI.

PROCEDURE BYTE USING 21
DO WHILE (USART_STATUS AND Oal:H) - 01

END.
RETURN USART 3IATA.
END ell

203'

204

DECLARE CHAR
I

205

LO:

206
207

3
3

209

210
211

2
:I

213

OET,JiEX:

PROCEDURE BYTE USINQ 21

BYTE
BYTE

AUXILIARV,
AUXILIARY;

CHAR-CII

DO 1"'0 TO Hh
IF CHAR-HEX_TABLE( I)
THEN OOTO Lt.
ENDI
LL

CALL COIHEX_TABLE(J)),

IF 1-16
THEN GOTO LO;

214
215
216

RETURN I,
END OET -HEX;

2
2

217

219
219
220

3
3
3

OUTPUT 3IESSAQE: PROCEDUREIM£SSAOEJ'TR) USING 2.
DECLARE MESSAOE_PTR WORD.
MESSAOE
BASED
MESSAGE_PTR 11) BYTE CONS'ANT.
I
BYTE
AUX ILIARY,

00 WHILE PlESSAGE ( t) <> OJ
CALL CO U1ESSAQE II )).
X-X+11

19-66

USA~T

inter
Ap,Uc.Uon Moduh

PL/I"I-:U COMPILER
221

222

ENOl
END OUTPUT _MESSAGEJ

223

224

:1:15

A'Vnc/SDLC Protocol conv.T't.r

226

:127
228

3
3

230

231
:132

I'ENU'

PROCEDURE USING 2;

DECLARE I
BYTE
CHAR
BYTE
STATION_ADDRESS BYTE

AUXIL.IARY,
AUXILIARY,

AUXILIARYI

START:
CALL. OUTPUT_I'tESSAQE(. SIGN_ON),

MO: CHAR-el,
DO 1-0 TO 41
IF CHAR-MENU_CHAR ( I )
THEN OOTO M1.

ENOl
H1

CALL

co (t'IENU_CHAR( I » j

IF 1=5
THEN OCTO I'IOJ
DO CASE I,

234

:135
:136

4
4

237

STATION_ADDRESS-SHLCGET _HEX. 4),

:138

STATION_~ODRESS.(STATION_ADDRESS

239

BTAD-STAT I ON_ADDRESS,

240

CALL OUTPUTJlESSAGE( S_ADDR_AtK),

241
242

4
4

CALL CO(HEX_TABLECSHRCSTATION_ADDREBS. 4})},

243
244

4
4

ENOl

245

DO,

246

247

DESTINATIONjlDDRESS-SHL{GET_HEX.4).

248

DESTINATION_ADDRESS-(DESTINATIONJ'DDRESS OR GET_HEX ),

249

CALL OUTPUT_MESSAOE( D-.ADDR_ACK).

DO;

CALL OUTPUT_I'IESSAOEL STAT_ADDRl.

OR GET_HEX»

CALL. COCHEX_TABLECOFH AND STATION_ADDRESS»,
CALL OUTPUT_MESSAGE(. ADDR_ACK_FIN),

CALL OUTPUTJ1ESSAOE L DEST _ADDR) ,

19-67

lS.50 53

09/19/83

PAGE

inter
PL/M-:U COMPILER

Applic.tian Module:

250
251

4
4

252
253

END,

254
2"
256
257

4
4
4
4

DO.

258
259
260
261

4
4
4
4

262

263

A.~nc/SDL.C

ProtQc,ol· conve,.teT'

18 50 53

09119/93

CALL. COCHEX_TABLECSHRCDESTINATIDN_ADDRESS, 4»),

CALL COCHEX_TABLECOFH AND DESTINATION_ADDRESS»,
CALL OUTPUT_MESSAGE(, ADDR.-ACK.JIN)j

CALL OUTPUT_HESSAGEC FIN);
CALL OPENl

ENOl
DO.
CALL OUTPUT_MESSAGE( FIN),
CALL. CL.oSEI
END.
CALL OUTPUT_MESSAGE( FIN),

END.

F* DO CASE *1

264
26.

266

USART_RECV_INT'

PROCEDURE INTERRUPT 0 USING 21

DECLARE CHAR
STATUS

BYTE
BYTE

267
268
269

2
2
2

CHAR-UBARr _DATAl
ST ATUS-UBART _ST ATUB AND 39H.

271

ELSE IF CHAR-ESC

273
274
27'

3
3

ELSE 001

.277

AUXILIARY.
AUXILIARY,

IF STATUS<>O
THEN CALL ERROR(STATUSh

THEN CALL MENU.

CALL FIFO_T _IN(CHAR),
IF ECHO-O
THEN CALL CO(CHAR)'
END.

278

END UBARr _RECV _INT.

279

BEGIN
CALL POWER_ON.

280
281

2
2

283

284
285
286
287

4
3
3
4

DO FOREVERJ
IF SEND_DATA>O
THEN DO.
DO WHILE NOT(XMIT_BUFFER_EMPTY)J

I-Walt until SIU_XHIT_BUFF.,.
is .mpt\l *1
END.
LENGTH. CHAR '11"1.
SIU_XHI T _BUFFER (0 )-DESTINATION_ADDRESSJ
DO WHILE «CHAR<>LF) AND (LENGTHEMPTY)}I

19:-68

PAOE

lB. ~O·

PL/I1-S1 COI1P ILER

2BB

289

4
4

290
291

293
294

3
3

296
297
298
299

4
4
4
4

300

301
302
303
304

5
4
4

30.
307
308
309
310
311

5
5

312
313

PAQE

END,

1* If thlt line entered .t thlt terllinel is IT •• tel" then BUFFERJ.ENOTH ch.,.. 'lend the
Hrst BUFFERJ.ENOTH che"" thltn •• nd thlt " •• t, .ince thlt SIU buff.,. i . onlv BUFFER_LENQTH bVt •• *1
Ll
1-0.
U •• 1 to caunt thlt numb.", of unsucc •• 'ul
t".-naml t. *1

RETRY'

,.g.

RESUL.T-TRANSI'IIT(LENQTH)J
Send thlt •••
IF RESULT<>DATA_TRANSI1ITTED
THEN DO,
/* Wait 50 ..... e for link to connect thltn tl'lJ .g.1"

WAIT-1,

THO-3CH,
TLO-OAFHI

TRO-I,
DO WHILE WAIT,
ENOl
TRo-O,
I-}+11
IF 1>100 THEN DO.

/* W.dt :J site to gltt on line .1 ••

•• nd 1t1'roT' ,. •••• g. to t.,..in.1
end trV egein
CALL LINK_DISC.
OOTO L1.
END.

OOTO RETRY,

ENOl

4
3
1

09/19/83

CHAR-FIFO_T _OUTI
SIU_XI1IT,JIUFFER (LENQTH I-CHAR,
LENOTH-LENQTH+ 11

292

END,
END.
END USER_MOD.

WARNINOS
2 IS THE HIGflEST USED INTERRUPT

I10DULE INFORI1ATlON
CODE SIZE
CONSTANT SIZE
DIRECT VARIABLE SIZE
INDIRECT VARIABLE SIZE
BIT SIZE
BIT-ADDRESSABLE SIZE
AUXILIARY VARIABLE SIZE
I1AXlI1UI1 STACK SIZE
REGoISTER-BANK(S) USED
713 L.INES READ
PROGRAI1 ERROR (S I
END OF PL/I1-~1 COI1PILATION

(STATIC+OVERLAYABLE)
1714D
01CFH
463D
OOH+05H
00+ 5D
OOH+OOH
OD+ 00
Oii!H+OIH
aD+
ID
OOH+OOH
00+ OD
- 021FH
543D
• 002SH
40D

eo 06B2H

1 "

19-69

PL/M-.'51 COMPILER

RUPI-44 Pr:t.mar", Stahon

ISIS-II PL/M-51 VI 0
COMPILER INVOKED BY

F2 PLM51

20 41 13

F2 PNOTE SRC

$TITLE
('RUPI-44 Prlmar\l Statlon')
$DEBUG
$REGISTERBANK(O)
MAIN$MOD DO.

1* To save paper the RUPI regl'OteT'S aT'~ not 11St.d, but thl'J 15 the steteflll!nt
used to 1nc lude Uem
_INCLUDE ( 92 REG44 DeL) *1
$NOLIST
DECLARE LIT

TRUE
FALSE
FOREVER

LITERALLY

'LITE;RALLY',

LIT
LIT
LIT

'OFFH',
'OOH',
'WHILE 1',

1* SOLC COMMANDS AND RESPONSES *1
6

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

DECLARE SNRM
UA
DISC
OM
FRMR
R~Q_OISC

UP
TEST
RR
RNR

'93H',
'13H',
'53H',
'IFH'.

'97H',
'53H',
'33H',
'OF3H',
'ItH'.
'tSH'.

1* REMOTE STATION BUFFER STATUS *1
BUFFER_READY
BUFFER_NOr _READY

LIT
LIT

'0',
'1',

1* STATION STATES *1
DISCONNECT 5
GO_TO_DISCI_T_S

LIT
LIT
LIT

'OOH',
'OtH',
'02H',

1* LOGICALLY DISCONNECTED STATE*I
1* INFORMATION TRANSFER

1* PARAMETERS PASSED TO XMIT_I_T_S *1
T_I_FRAME
LIT
'OOH',
T _RR
LIT
'OlH',
T_RNR
LIT
'02H',
1* SECONDARY STATION IDENTIFICATION *1
NUMBER_OF _STATIONS LIT
'2',
SECONDARY _ADDRESSES (NUMBER_OF _STAT IONS)
BYTE
CONSTANT (55H, 43H),

19-70

~TATE

09/26/83'

PAGE

P1./1I-5. CDllPIL.ER

RuPJ-44

,,.i.. ,.,,

't.tiDn

20' 47.3

RBOI_EII_DI' JlTATIONII STIIUCTURI
18T...TJON......IIDRISS
IYTI!.
STATlON_STATI
IVTI!.
NIl
BYTE.
NIl
IYTE.
MFFER_STAT\III

IVTE.

INFII....-TM
IlATAI . . ,

/* Tit • •

IYTE.
IYTEI

'.'UI

.f tit • • • cond.", .,.tions

AUXILIMY.

I . YMIA8LES
BT...TION___
IYTE
RECYJIELD",,-TM
aYTI
BIT,
..... IT

AUXILIMY.
AUXlLIMV •

I. BUFFERS *1
SIII~"ITJlUFFERI.41

IYTE
IYTI!,

SIII..,RECYJlIJFI'EJI 1.41

•

IllATA.

POWER_ON: PROCIDURE ,
DECLME I

BYTE

AUXILiARY.

•0

11
.2

a
12

T_, SIII_X,"ITJlIJFI'EJIIOI,
RIS-, SIII..,RECIIJlIIFFf;RIOI •
RL. . . ,
,/. 64 aV'e ".c.lve &tu'f.,. . ,
RIE-I,
En.".* , ... SIU', "eceiv....

-DO I- 0 TO NUI1IER_DI' JlTATJ_ ••

3
3
3
3

".6.7

••
.9
20

II
2

12
2

ABOI iI, STIITJON..AJIDIIESS-SEC_V"""O_ _ I I ,.

:::::'
rU:;~:'J;!=::="~~~::EII/)V.
RSDC I INFO,..LENOTH-(h
J

SA'ID-54H. , . Ulin, DP1...... NAZI. PFS. TIteR , • •
_21M,
THI~.

TCON-4OH,

IE_.

v••

t,..."'0

END POWER_ON;

2
12

X"IT' PROCEDURE ICONTROLJlYTEI.
DECLME CONTROLJlVTE
TClaCONTROLJlYTI!.
TBF-li

BYTE.

15 K", • • /

••,. ,..c •• ve 'i •• out iftt.",.upt . ,

"v".'" ./

09/a./83

PoIIQE

flL/M-51 COMPILER

2.
30
31
32

RUPI-44 PrlmaT'1.,J Stat10n

20"47.'1{3"

RTS=l,
DO WHILE NOT SI.
END.
81=0.

2
3
3

END XMIT.

33
34
35
36

2
2
1

TIMER_O_INT
PROCEDURE INTERRUPT 1
WAIT=O.
END TIMER_O_INT,

TIME_OUT

DECLARE

DO 1=0 TO 3.

40
41
42
43
44
45

3
3
3
3
4
4

47
48
4.

1* Tlme_out returns true 1f there wasn/t:
a frame 'l"ecelved w1thln 200 mse-c,
If,there was' a frame rece1ved, ,I./llthln'
200 msec then tlme_out return5 false

PROCEDURE BYTE,

BYTE

USING ,1'.

AUXILIARY,

WAIT=!.
THO=3CH.
TLO==OAFH,
TRO=l,
DO WHILE WAIT,
IF 91=1
THEN GOTO T _01,
END,
END.

RETURN TRUE,

50
SI=O,
RETURN FALSE.

END TIME_OUT,

52
53

54
55
56

2
2

3
3
3
3
2

60
61
62

SEND_DISC

PROCEDURE.

TBL=O,
CALL XMITWISC),
IF TIME_DUT=FALSE
THEN IP RCB=UA OR RC8=DM
THEN DO.

RSD (STAT ION_NUMBER ) BUFFER_STATUS-BUFFER_NOT _READY,

RSD (STATION_NUMBER) STAT ION_STATE=DISCONNECT _Sf
END,
RBE;;1.

END SEND _D I Be,

SEND_SNRM

PROCEDURE,

TBL=O,

19-~2

09/26/83"

PAGE

PL/M-51 COMPILER

66
67

69
70

3
3

72
73

3
2

20 47 13

09/~6/B3

CALL XHIT SHRCRCS. 5»
THEN RETURN FALSE.

RETURN TRUE.

89
90

RECEIVE

PROCEDURE
DECLARE

BYTE

AUXILIARV.

1* If an RNR was recelved bufler_status wlll be changed 1n the 5uperV1SOl"V
frame decode ~ection futher down 1n thu, proc&'dUf'e. anlj othe,: r.spons.
m.ans the l"emote stations bul'fe.,. is .,..ady *1

IF tRCa AND 01H)=O

THEN DO.
97
98

4
4

1* I Frame Recelved *1
IF CCHECK_NS... TRUE AND BOV=O AND CHECK_NR=TRUE)
THEN DOl
RSOCSTATION_NUMBER) NR=(CRSD(STATlON_NUMBER) NR""l) ANO 07H).
RBP=l,

19-73

PAGE

intJ
PL/M-51 COMP1LER

20· 47 13

Prlmary: Station

~UPI-44

09/26/83

RECV _F IELD_LENGTH=RFL-l.
ENOl
101

102
103

3
2:

105

ELSE RSDCSTATION_NUMJiER) STATION_STATE=...GO_TO_DISCI
END I
ELSE IF (RCB AND 03H)=OlH
THEN DO.
1* SuperV1SOrlj frame "eceived *1

IF CHECK_NR=FAl,.SE
THEN RSI)(STATION....NUMBER). STATION_STATE=OO_TO_DISC,
ELSE IF «RCB AND OFH)"'05H) 1* then'RNR *1
THEN RSD (STAT ION_NUMBER) BUFFr:':R _STATUS-SUFFER _NOT _READY.
END.

107
109
110
111

3
3

113
110
115
116
117

0
0
3
3

lie

119

END.
RSD (STAT ION_NUMBER) STAT ION_STATE=GO_TO_DISC.

END,
RBE-l,
END RECEIVE.

120

12i

DECLARE

TEMP

BYTE.

IF TEMP=T _I_FRAME
THEN DO,
1* Tran~ml t I frame *1
1* Transfer the stat1tm" buHler Into Internal ram *1

122

12'
125
126

1* Unnumbereli f"jlme or unknown h'.me recltlved *1
IF RCB=FRMR
THEN DO.
1* 141 FRMR was T'~celved check NT for an
acknowledged I frame *1
RCO-SIU_RECV_BUFFER( 1) I
I=CHECK_NR;

ELSE DO.

DO TEMP=O TO RSD(STATION_NUMBER), INFO_LENGTH-i.
SIU_XMIT _BUFFER (TEMP )=RSP (STATION_NUMBER) DATA CTEMP ).

4
4

ENOl
1* Bui Id the I fram. control held *1

127

129
129
130

TBL=RSO(STATION_NUMBER). INFO...,LENGTH.

3
3

CALL XMIT =SIU_RECV_BUFFEh(,J>.

END,

163

END BUFFER_TRANSFER;

164

BEGIN·
CALL POWER_ON.

165

166
167
168

3
3

DO FOREVER.
DO STATION_NUMBER=O TO NUMBER_OF _STATIONS-1.
STAD=RSD( STAT ION_NUMBER) STAT ION_ADDRESS,
IF RSD(STATl'ON_NUMBER) STATION_STATE'" DISCONNECT_S
THEN CAL.L. SEND_SNRM.
ELSE IF RSD(STATION_NUMBER) STATION_STATE'"' GO_TO_DISC
THEN CALL SEND _0 I se.
ELSE IF «RSDfSTATION_NUMBER) INPO_LENGTH)O) AND
(RSO(STATION_NUMBER) BUFFER_STATUS=BUFFER_REAOY»
THEN CALL XMIT_I_T_SCT_I_FRAME).
ELSE IF RBP""O
THEN CAL.L XMIT_I_T_S

vee

+ 5V power supply during operation and program
verification,

PORTO
Port 0 is an S-bit open drain bidirectional 110 port, It Is
also the multiplexed low-order address and data bus
when using external'memory, It Is used for data output
during program verification. Port 0 can sink/source eight
LS TIL loads.
'
PORT 1
Port 1 is an 8-bit quasi-bidirectional 1/0 port. It is used for
the low-order address byte during program verification.
Port 1 can sink/source four LS TIL loads.
In non-loop mode two of the 1/0 lines serve alternate
functions:
-FiTS (Pl.6). Request-to-Send output. A low indicates
that the RUPI-44 1$ ready to transmit.
-C'rn (P1,7) Clear-to·Send Input. A low indicates that a
receiving station is ready to receive.

. -SCLK T1 {Pill). In addition to 110, this ,pih~prqvides In~ to counter, 1 or serves as SCLK (serlal:cIOQk) Input .
-WR (P3.6). l'he write control signal latcHes the data
~e from Port 0 into the External Data Memory.
-RO (P3,7). The read control signal enables External
Data Memory ,to. Port O.

RST
A high on this pin fortwo machine cycles while the oscillator
is running resets the device. A small external pulldown
reSistor ("S.2KCl) from ~ST to V58 perniits power-on reset
when a capacitor ("'IOpf) is also connected from this pin
toVcc '
ALEIPROG
Provides Address Latch Enable output used for latQhing
the address Into external 'mElmory during normal operation, It is activitated ellery six OSCillator periods except
during an external data memory access, If also receives
the program pulse input for programming the EPROM
version.
"

PORT 2
Port 2 is an 8-bit quasi-bidirection 110 port. It also emits
the high-order address byte when accessing external
memory. It is 4sed for the high-order address and the
control signals during program verification. Port 2 can
sink/source four LS TIL loads. -

PSEN
The Program Store Enable output is a control signal
that enables the external Program',Memory to the bus
during external fetch oper!ltions. It ill acUvll-ted every
six osciilator periods, except dl,lring external, data
memory accesses. Remains high during i"ternal program execution.

PORT 3
Port 3 is
8-bit quasi-bidirectional 1/0 port. It also
contains the interrupt, timer, serial port and RD and
WR pins that are used by ,various options, The output
latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. Port 3
can sink/source four LS TIL load!,!,

EAtvPP
When held at a TIL high level, the RUPI-44 executes instructions from the internal ROM when the PC is less
than 4096, When held at a TIL low level, the RUPI-44 fetches all instructions from external Program Memory.
The pin also receives the 21V EPROM programming supply voltage on the S744,
.

In addition to 1/0, some of the pins also serve alternate
functions as follows:
-1/0 RxD (P3.0). In point-to-polnt or multipoint configura- '
tions, this pin controls the direction of pin P3.1. Serves
as Receive Data Input In loop and diagnostic modes.
-DATA TxD (P3.1) In polnt-to-point or multipoint con- •
figurations, this pin functions as data inputloutput. In
loop mode, It serves as'transmit pin. A '0' written to
this pin enables diagnostic mode,
-iN'fO ,(P3.2). Interrupt 0 Input or gate control Input for
' .
counter O.
-iiii'R (P3.3). Interrupt 1 Input or gate control Input for
counter 1.
- TO(P3.4). Input to counter O.

XTAL 1

21)-;2

Input to the oscillator's high gain amplifier. Required
when a crystal Is ulled. Connect to VSS when external
s~urce is used on XTAL 2,
'

XTAL2
Output from the oscillator's amplifier. Input to the Internal timing cirCUitry. A crystal or external source-can be
used,
'

inter

8044AH/8344AH

vcc

PI1[
PU[

POI

AOI

PI1 [

•

J PO 2

A02

P03

A03

PIO

~{'
~

DATA

110

T)(O~

RXO __

INTO~

INT' .....
TO-.,

n-.

SCLK

WR.-

&:!

A5 .....

0
G..

ADO

P151

RTS

P161
PI71

RST

VPO[

110

RXO

P30

•

OATA

TXO

P3 II

INTO

P321

"'2

INT1

P331

pul

PHI

1 P2.5

AI3

iVA
iiii

PHI

AI2

P371

J P2,3

All

XTAl21

P22

AIO

"
20

P21

P2.0

SClK

:E~

pul

PO.O

XTAl'

VSS I

"po 7 A07

A04I

10"

13<.
876.

JALE

,VPP
PROG

: jiffi
A15
lP2I

"
"

'"
Figure 2.
Logic Symbol

]P05

AD.
ADS'

At<

Figure 3. Pin
Configuration

FREQUENCE
REFERENCE

r-I
I
I
I

OSCIL
LATOR
&
TIMING

4096 BYTES
PROGRAM
MEMORY
(8044 & 8744)

192 BYTES
DUAL PORT
RAM

SIU
(SERIAL
INTERFACE
UNIT)

,I
I

I
I
I
I
L

INTERRUPTS

TWO 16-BIT
TIMER EVENT
COUNTERS

'-_..,.....,...._...1

I--~-

INTERRUPTS

I
I
I

--l
CONTROL

PARALLEL PORTS
ADDRESS DATA BUS
AND 110 PINS

Figure 4.
Block Diagram

2(}-3

COUNTERS

DATA

110
HDLC/SDLC
SERIAL
COMMUNICATIONS

.8044AH/8344AH

Functional Description
General

The Internal Data RAM address space is 0 to 255.
Four 8-Register Banks occupy loCations 0 through 31.
The stack can be located anywhere in the Internal
Data RAM address space. ·In addition, 128 bit locations of the on-chip RAM are accessible through
Direct Addressing. These bits reside in Internal Data
RAM at byte locations.32 through 47. Currently locations 0 through 191 of the Internal Data RAM address
space are filled with on-chip RAM.

The 8044 integrates the powerful 8051 microcontroller
with an intelligent Serial Communication Controller
to provide a single-chip solution which will efficiently
implement a distributed processing or distributed
control system. The microcontroller is a self-sufficient
unit containing ROM, RAM, ALU, and its own
peripherals. The 8044's architecture and instruction
set are identical to the 8051 'so The 8044 replaces the
8051 's serial interface with an intelligent SDLC/HDLC
Serial Interface Unit (SIU). 64 more bytes of RAM
have been added to the 8051 RAM array. The SIU
can communicate at bit rates up to 2.4 M bps. The
SIU works concurrently with the Microcontroller so
that there is no throughput loss in either unit. Since
the SIU possesses its own intelligence, the CPU is
off-loaded from many of the communications tasks,
thus dedicating more of its computing power to controlling local peripherals or some external process.

SPECIAL
FUNCTION
REGISTERS

,--"---,

25s

INDIRECT

~cPRESS-

The mlcrocontroller is a stand-alone highperformance single-chip computer intended for
use in sophisticated real-time application such as
instrumentation, industrial control, and intelligent
computer peripherals.

•
•

•

{

191

248 F8H
FOH
E8H
EOH
D8H
DOH
C8H

COH

ADDRESS·
ABLE
BITS IN
SFRs
(128 BITS)

98H
90H

88H

-=~12::.8=13~5_-",12~8 80H
127 ,...

ADDRESS·
ABLE
BITS IN
SFRs
(128 BITS)

The major features of the microcontroller are:

•
•

D
RAM

The Microcontroller

•
•
•
•
•
•
•

255

8-bit CPU
on-chip oscillator
4K bytes of ROM
192 bytes of RAM
32 I/O lines
64K address space for external Data Memory
64K address space for external Program
Memory
two fully-programmable 16-bit timer/counters
a five-source interrupt structure with two priority levels
bit addres.sability for Boolean processing
1 ,.,sec instruction cycle time for 60% of the instructions 2 ,.,sec instruction cycle time for
40% of the instructions
.4 ,.,sec cycle time for 8 by 8 bit unsigned
Multiply/Divide

DIRECT
ADDRESSING

~ b-=:d
127

120

REGISTERS

-.-_~A

INTERNAL
DATA RAM

SPECIAL FUNCTION
REGISTERS

Figure 5. Internal Data Memory
Address Space

Parallel 1/0
The 8044 has 32 general-purpose 110 lines which
are arranged into four groups of eight lines. Each
group is called a port. Hence there are four ports;
Port 0, Port 1, Port 2, and Port 3. Up to five lines
from 1 and Port 2 are dedicated to supporting the
serial channel when the SIU is invoked. Due to
the nature of the serial port, two of Port 3's 110
lines (P3.0 and P3.1) do not have latched outputs.
This is true whether or not the serial channel is
used.

Internal Data Memory
Functionally the Internal Data Memory is the most
flexible of the address spaces. The Internal Data
Memory space is subdivided into a 256-byte Internal
Data RAM address space and a 128-byte SpeCial
Function Register address space as shown in Figure

5.
20-4

8044AH/8344AH

Table 1. MCS®-51 Instruction Set Description
LOGICAL OPERATIONS (CONTINUED)

ARITHMETIC OPERATIONS
Mnemonic
ADD
A,Rn

ADD

A,direct

ADD

A,@Ri

ADD

A,#data

ADDC A,Rn
ADDC A,direct
ADDC A,@Ri
ADDC A,#data
SUBB

A,Rn

SUBB

A,direct

SUBB

A,@Ri

SUBB

A,#data

INC
INC
INC
INC
INC
DEC
DEC
DEC
DEC

A
Rn
direct
@Ri
DPTR
A
Rn
direct
@RI

MUL
DIV
DA

AB
AB

Mnemonic
A,@Ri
ORL

Description
Byte Cyc
Add register to
Accumulator
1
1
Add direct byte to
Accumulator
2
1
Add indirect RAM to
Accumulator
1
1
Add immediate data to
Accumulator
2
1
Add register to
Accumulator with Carry 1
1
Add direct byte to A
with Carry flag
2
1
Add indirect RAM to A
with Carry flag
1
1
Add immediate data to
A with Carry flag
1
2
Subtract register from A
1
1
with Borrow
Subtract direct byte
from A with Borrow
2
1
Subtract indirect RAM
from A with Borrow
1
1
Subtract immed data
from A with Borrow
2
1
I ncrement Accumulator 1
1
Increment register
1
1
Increment direct byte
1
2
Increment indirect RAM 1
1
I ncrement Data POinter
1
2
Decrement Accumulator 1
1
Decrement register
1
1
Decrement direct byte
1
2
Decrement indirect
RAM
1
1.
MultiplyA&B
1
4
DIvide A by B
1
4
Decimal Adjust
1
Accumulator
1

ANL

A,dlrect

ANL

A,@Ri

ANL

A,#data

ANL

direct,A

ANL

dlrect,#data

ORL

A,Rn

ORL

A,direct

A,#data

ORL

direct,/!.

ORL

direct;#data

XRL

A,Rn

XRL'

A,direct

XRL

A,@RI

XRL

A,#data

XRL

dlrect,A

XRL

dlrect,#data

CLR
CPL

A
A

RL
RLC

A
A

RRC

SWAP

DATA TRANSFER
Mnemonic
MOV
A,Rn

LOGICAL OPERATIONS
Mnemonic
A,Rn
ANL

ORL

Destination
Byte Cyc
OR indirect RAM to
Accumulator
OR immediate data to
Accumulator
2
OR Accumulator to
direct byte
2
OR immediate data to
direct byte
3
2
Exclusive-OR register to
Accumulator
Exclusive-OR direct
2
byte to Accumulator
Exclusive-OR indirect
RAMtoA
1
Exclusive-OR
Immediate data to A
2
Exclusive-OR Accumulator to direct byte
2
Exclusive-OR Immediate data to direct
3
2
Clear Accumulator
Complement
Accumulator
Rotate Accumulator Left
Rotate A Left through
the Carry flag
Rotate AccumtJiator
Right
Rotate A Right through
Carry flag
Swap nibbles within the
Accumulator

Destination
Byte Cyc
AND register to
Accumulator
1
1
AND direct byte to
Accumulator
1
2
AND indirect RAM to
Accumulator
1
1
AND Immediate data to
Accumulator
1
2
AND Accumulator to
direct byte
2
1
AND immediate data to
3
direct byte
2
OR register to
Accumulator
1
1
OR direct byte to
Accumulator
1
2

20-5,

MOV

A,dlrect

MOV

A,@Ri

MOV

A,#data

MOV

Rn,/!.

MOV

Rn,direct

MOV

Rn,#data

MOV

direct,A

MOV

direct,Rn

MOV

direct,direct

MOV

direct,@Ri

Byte Cyc
Description
Move register to
Accumulator
Move direct byte to
Accumulator
2
Move Indirect RAM to
Accumulator
Mov immediate data to
Accumulator
2
Move Accumulator to
register'
Move direct. byte to
register
2
2
Move immediate data to
register
2
Move Accumulator to
direct byte
2
Move register to direct
byte
2
2
Move direct byte to
2
3
direct
Move indirect RAM to
direct byte
2
2

intJ

8044AH/8344AH

Table 1. (Cont.)
DATA TRANSFER (CONTINUED)

PROGRAM AND MACHINE CONTROL

Mnemonic
direct,#data
MOV

Mnemonic
ACALL addr11

Description
Byte Cyc
Move immediate data to
direct byte
2
3
@Ri,A
Move Accumulator to·
MOV
indirect RAM
MOV
@Ri,direct
Move direct byte to
Indirect RAM
2
2
@Ri,#data
Move immediate data to
MOV
indirect RAM
2
DPTR,#data16 Load Data POinter with
MOV
a 16-bit constant
2
3
MOVC A,@A+DPTR Move Code byte relative
to DPTRtoA
2
MOVC A,@A+PC
Move Code byte relative
to PCtoA
2
MOVX A,@RI
Move External RAM (8bit addr) to A
2
Move External RAM (16MOVX A;@DPTR
bit addr) to A
2
Move A to External RAM
MOVX @Ri,A
(8-bit addr)
2
MOVX @DPTR,A
Move A to External R'AM
(16-bit addr)
2
PUSH direct
Push direct byte onto
stack
2
2
direct
Pop direct byte from
POP
stack
2
2
A,Rn
XCH
Exchange register with
Accumulator
XCH
A,dlrect
Exchange direct byte
with Accumulator
2
A,@RI
XCH
Exchange indirect RAM
with A
XCHD A,@RI
Exchange low-order
Digit Ind RAM w A

Description
Byte Cyc
Absolute Subroutine
Call
2
2
LCALL addr16
Long Subroutine Call
3
2
2
RET
Return from subroutine 1
RETI
Return from interrupt
1
2
AJMP addr11
Absolute Jump
2
2
LJMP addr16
Long Jump
3
2
SJMP rei
Short Jump (relative
addr)
2
2
JMP
@A+DPTR
Jump Indirect relative to
the DPTR
2
JZ
rei
Jump if Accumulator is
Zero
2
2
JNZ
rei
Jump if Accumulator IS
Not Zero
2
2
JC
rei
Jump if Carry flag IS set 2
2
JNC
rei
Jump if No Carry flag
2
2
JB
bit,rel
Jump if direct Bit set
32
JNB
bit, rei
Jump If direct Bit Not
set
3
2
JBC
bit,rel
Jump if direct Bit IS set
& Clear bit
3
2
CJNE A,direct,rel
Compare direct to A &
Jump If Not Equal
3
2
CJNE A,#data,rel
Comp, immed, to A &
Jump if Not Equal
3
2
CJNE Rn,#data,rel Comp, Immed, to reg &
Jump If Not Equal
3
2
CJNE @RI,#data,rel Comp, immed, to ind, &
Jump If Not Equal
3
2
Decrement register &
DJNZ Rn,rel
Jump If Not Zero
2
2
DJNZ dlrect,rel
Decrement direct &
Jump if Not Zero
3
2
NOP
No operation
1
1

BOOLEAN VARIABLE MANIPULATION

Notes on data addressing modes:
-Working register RO-R7
Rn
direct -128 internal RAM locations, any 1/0 port,
control or status register
-Indirect Internal RAM localton addressed by
@Ri
register RO or R1
-8-bit constant included in instruction
#data
#data16 -16-bit constant Included as bytes 2 & 3 of
Instruction
-128 software flags, any 1/0 pin, control or
bit
status bit
Notes on program addressing modes:
addr16 -Destination address for LCALL & LJMP may
be anywhere within the 64-K program
memory address space
Addr11 --Destination address for ACALL & AJMP will be
within the same 2-K page of program
memory as the first byte of the following
instruction
-SJMP and all conditional jumps Include an 8rei
bit offset byte, Range is +127-128 bytes relative
to first byte of the follOWing instruction
All mnemonics copynghted © Intel Corporation 1979

Mnemonic
CLR
C
CLR
bit
SETB C
SETB bit
CPL
C
CPL
bit
ANL
C,blt

ANL

C,/blt

ORL

C/blt

ORL

C,/bit

MOV

C,/blt

MOV

bit,C

Description
Byte Cye
Clear Carry flag
1
1
Clear di'rect bit
1
2
Set Carry flag
1
1
Set direct Bit
1
2
Complement Carry flag
1
1
Complementdtrect bit
2
1
AND direct bit to Carry
flag
2
2
AND complement of
direct bit to Carry
2
2
OR direct bit to Carry
flag
2
2
OR complement of
direct bit to Carry
2
2.
Move direct bit to Carry
flag
2
Move Carry flag to
direct bit
2
2

2()"6

inter

8044AH/8344AH

There are three control registers and eight parameter
registers that are used to operate the serial interface. These registers are shown in Figure 5 and
Figure 6. The control registers set the modes of
operation and provide status information. The eight
parameter registers buffer the station address, receive
and transmit control bytes,and point to the on-chip
transmit and receive buffers.

Port 0 and Port 2 also have an alternate dedicated
function. When placed in the external access
mode, Port 0 and Port 2 become the means by
which the 8044 communicates with external program memory. Port 0 and Port 2 are also the
means by which the 8044 communicates with external data memory. Peripherals can be memory
mapped into the address space and controlled by
the 8044.

Data to be received or transmitted by the SIU must
be buffered anywhere within the 192 bytes of onchip RAM. Transmit and receive buffers are not
allowed to "wrap around" in RAM; a "buffer end"
is generated after address 191 is reached.

Timer/Counters
The 8044 contains two 16-bit counters which can
be used for measuring time intervals" measuring
pulse widths, counting events, generating precise
periodic interrupt requests, and clocking the serial
communications. Internally the Timers are clocked
at 1/12 of the crystal frequency, which is the instruction cycle time. Externally the counters can run up
to 500 KHz.

AUTO Mode
In the AUTO mode the SIU implements in hardware a subset of the SOLC protocol suoh that it
responds to many SOLC frames without CPU intervention. All AUTO mode responses to the
primary station will conform to IBM's SOLC definition. The advantages of the AUTO mode are that
less software is required to implement a secondary
station, and the hardware generated response to polls
is much faster than doing it in software. However, the
Auto mode can not be used at a primary station.

Interrupt System
External events and the real-time driven on-chip
peripherals require service by the CPU asynchronous to the execution of any particular section of code. To tie the asynchronous activities of
these functions to normal program execution, a
sophisticated mUltiple-source, two priority level,
nested interrupt system is provided. Interrupt
response latency ranges from 3 "sec to 7 "sec
when using a 12 MHz clock.

To transmit in the AUTO mode the CPU must load
the Transmit Information Buffer, Transmit Buffer
Start register, Transmit Buffer Length register,
and set the Transmit, Buffer Full bit. The SIU
automatically responds to a poll by transmitting
an information frame with the PIF bit in the control field set. When the SIU receives a positive
acknowledgement from the primary station, it
automatically increments the Ns field in the NSNR
register and interrupts the CPU. A negative acknowledgement would cause the SIU to retransmit the
frams.

All five interrupt sources can be'mapped into one
of the two priority levels. Each interrupt source
can be enabled or disabled individually or the entire interrupt system can be enabled or disabled.
The five interrupt sources are: Serial Interface
Unit, Timer 1, Timer 2, and two external interrupts.
The external interrupts can be either level or edge
triggered.

Serial Interface Unit (SIU)
The Serial Interface Unit is used for HOLC/SOLC
communications.. It handle'S Zero Bit Insertion/Deletion, Flags, automatic address recogni.!ion, and a 16-bit cyclic redundancy check. In addition it implements in hardware a subset of the
SOLC protocol such that it responds to many
SOLC frames without CPU intervention. In certain
applications it is advantageous to have the CPU
control the reception or transmission of every
single frame. For this reason the SIU has two modes
of operation: "AUTO" and "FLEXIBLE" (or "NONAUTO"). It is in the AUTO mode that the SIU
responds to SOLC frames without CPU intervention;
whereas, in the FLEXIBLE mode the reception or
transmission of every single frame will be under CPU
control.

To receive in the AUTO mode, the CPU loads the
Receive Buffer Start register, the Receive Buffer
Length register, clears the Receive Buffer Protect
bit, and sets the Receive Buffer Empty bit. If the
SIU is polled in this state, and the TBF hit indicates that the Transmit Buffer is empty, an
automatic RR response will be gener~ted. When a
valid information' frame is received the SIU will
automatically increment Nr in the NSNR register
and interrupt the CPU:
While in the AUTO mode the SIU can recognize
and respond to the following commands without
'CPU intervention: I (Information), RR (Receive
Ready), RNR (Receive Not Ready), REJ (Reject),
and UP (Unnumbered POll). The StU can generate
20-7

8044AH/8344AH

SYMBOLIC
ADDRESS

B REGISTER
ACCUMULATOR
'THREE BYTE FIFO

TRANSMIT BUFFER START
TRANSMIT BUFFER LENGTH
TRANSMIT CONlROL BYTE
, SIU STATE COUNTER
SEND COUNT RECEIVE COUNT
PROGRAM STATUS WORD
'DMA COUNT
STATldN ADDRESS
RECEIVE ,FIELD LENGTH
RECEIVE BUFFER START
RECEIVE BUFFER LENGTH
RECEIVE CONTROL BYTE
SERIAL MODE
STATUS REGISTER
INTERRUPT PRIORITY CONTROL
,
PORT 3
INTERRUPT ENABLE CONTROL
PORT 2
PORT 1
riMER HIGH 1
TIMER HIGH 0
TIMER LOW 1
TIMER LOW 0
TIMER MODE
TIMER CONTROL
DATA POINTER HIGH
)DATA POINTER LOW
STACK POINTER
PORTO

B'
ACC
FIFO
FIFO
FIFO
TBS
TBL
TCB
SIUST
NSNR
PSW
DMA CNT
STAD
RFL
RBS
RBL
RCB
SMD
STS
IP
P3
IE
P2
Pl
THl
THO

BYTE
ADDRESS,

BIT ADDRESS
~-'- , - - ' > - - ,

247
231

Ihrough
throuah

240
224

223
215

Ihrouah

216
208

fOU

throu h

240
224
223
222,
221
220
219
218
217
216
208
207
206
205
204
203
202
201
200
184
176
168
160
144
141
140
139
138
137

207
191
183
175
167
151

throu
throu
throu

200
184
176
168
160
144

143

throuah

136

128

131'
130
129
128

throu
throu

Tll
TLO
TMOD
TCON
DPH
DPL
SP
PO

135

throuah

(FOHI
(EOHI
(DFHI
(DEHI
(DDHI
(DCH)
(DBH)
(DAH)
(D9HI
(D8H)
(DOHI
(CFHI
(CEH)
(CDHI
(CCH)
(CBH)
(CAHI
(C9HI
(C8HI
(B8HI
(BOHI
(A8H)
(AOHI
(90HI
(8DH)
(8CHI
(BBH)
(8AHI
(89HI
(B8H)
'(83HI
(82H)
(81H)
(80H)

SFR's CONTAINING
DIRECT ADDRESSABLE BITS

·ICE Support Hardware registers. Under normal operating conditions there
is' nb nee'd tor the CPU to access these registers.

Figure 5, Mapping of Special Function registers
SERIAL MODE REGISTER (SMDI SCM2

SCMl

SCMO

NRZI

lOOP

I
STATUS REGISTER (STS)

TBF

RBE

RTS

BOV

PFS

OPB

I I

NFCS

L - - , NO FRAME CHECK SEOUENCE
NON,BUFFERED
PRE, FRAME EYNC
LOOP
NOp!! RETURN TO ZERO INVERTED
SELECT CLOCK MODE

RBP

L - RECEIVE BUFFER PROTECT
AUTO, MODE/ADDRESSED MODE
OPTIONAL POLL BIT
RECEIVE INFORMATION BUFFER OVERRUN
SERIAL INTERFACE UNIT INTERRUPT
REQUEST TO SEND
RECEIVE BUFFER E!'IIPTY
TRANSMIT BUFFER FULL '

SEND COUNT RECEIVE
'COUNT REGISTER (NSNR) r-:=-r-=:;-:-r-:=:-r-,;;"",",--,=",..,;;-:--r-=.-.-...",--,
SEQUENCE ERROR RECEIVED
L _ - L_ _-'-_ _ _ _ RECEIVE SEQUENCE COUNTER

SEQUENCE ERROR SEND
SEND SEQUENCE COUNTER

Figure 6, Serial Interface Unit Control, re!ilisters

20-8

8044AH/8344AH

Frame Format Options

the following responses without CPU intervention: I (Information), RR (Receive Ready), and RNR
(Receive Not Ready).
,,'

In addition to the standard, SOLC frame format,
the 8044 will support the frames displayed in
Figure 7. The standard SOLCframe is shown at
the top of this figure. For th!!l remaining frames
the information field will incorporate the control
or address bytes and the frame check sequences;
therefore these fields wHi be stored in the
Transmit and Receive buffers. For example, in the
non-buffered mode the thkd byte, is treated as the
beginning of the information field.' In the nonaddressed mode, the informatioQ ,field begins after
the opening flag. The mode bits' to set the frame
format options, are foung in ,the Serial Mode
register and the Status register.

When the Receive Buffer Empty bit (BB!:) in·
dicates that the Receive Buffer is empty, the
receiver is enabled, and when the RBE bit in·
dicates that 1he Receive Buffer is full, the receiver
is disabled. Assuming that the Receive Buffer is
empty, the SIU will respond. to a poll vvith an I
frame if the Transmit Buffer is·fuU. If the Transmit
Buffer is empty, the SIU will respond t9 a. poll
with a RR command jf the Receive -Buffer Protect
bit (RBP) is cleared, or an RNR command if RBP is
set.
'

FLEXIBLE (or NON-AUTO) Mode
EXTENDED ADDRESSING

In the FLEXIBLE mode all ,communications are under
control of the CPU. It is the CPU's task to encode
and
decode
control
fields,
manage
acknowledgements, and adhere to the requirements
of the HOLC/SOLC protocols. The 8044 can be used
as a primary or a secondary station in this mqde.

To realize an extended control field or an extended
address field (ising the HOLC prqtocol, the FLEXIBLE mode must' be used. Foran extended control
field, the SIU is progra,r:nm!'ld to b,e in the non-buffered
mode. The extended controHield will be the first and
second bytes in the R~Meive_and Transmit Buffers.
To receive a frame in the FLEXIBLE mode, the CPU
. For extended addressing the SIU i~ placed in the nonmust load the Receive Buffer Start register, the
,addressed mode. In this mode the CPU must impleReceive Buffer Length register, clear the Receive But- . , ment the address rACOgnition for'received frames: The
fer Protect bit, and set the Receive Buffer Empty bit.
addressing field will be the initial bytes in the Transmit
If a valid opening flag is received and,~he address,
and Receive buffers followed by the control field. '
field matches the byte in the Station Address register
or the address field contains a broadcast address, the
The SIU can transmit and receive only frames which
8044 loads the control field in the receive control byte
are multiples of a bits. For frames received with other
register, and loads the I field in the receive buffer.
than a-bit multiples, a CRC error will cause the SIU
If there is no CRC error, the SIU interrupts the CPU,
to reject the frame.
indicating a frame has just been received. If there is
a CRC error, no interrupt occurs. The Receive Field
SOLe Loop Networks
Length register provides the number of bytes that
The SIU can be used in a ADLC loop as a secondary
were received in the information field.
or primary station. When the SIU iS,placed in the Loop
moc;leitreceivesthe data on pin 10 al')d transmits the
To transmit a frame" the CPU must load the transmit
data one bit _time delayed on pin 11. It can also
informatidn buffer, the Transmit Buffer Start register,
rec'ognize the Go ahead signal and chal1ge it into a
the Transmit Buffer Length register, the Transmit
flag when it is ready to transmit. As a secondary staControl Byte, and set theTBF and theflFS bit. The
tion the SIU can be used in the AUTO or FLftXIBLE
SIU,' unsolicited by an HOLC/SOLC frame, will
modes. As a primary station the FLEXIBLE mode is
transmit the' entire information frame, and interrupt
used; however, additional hardware is required for
the C;PU, indicating the completion of transmission.
generating the Go Ahead bit pattern. In the. Loop
For' supervisorY frames or Unnumbered frames, the
mode the maximum data rate is 1 Mbps clocked or
transmit buffer length Yiould be O.
'
375 Kbps self-clocked.

eRC

SDLC Multidrop Networks

The FCS register is initially set to all 1's prior to
calculating the FCS field. The SIU will not interrupt
the CPU if a CRC error occurs (in both AUTO and
FLEXIBLE modes). The GRCerror'is cleared upon,
receiving of an opening flag.

The SIU can be used in a SOLC non-loop configuration as a secondary or' primary station. When the SIU
is placed in the non-loop mode, data is received and
transmitted on pin 11, and pin 10 drives a tri~state
buffer. In non-loop mode; modem interface pins,RTS
and CTS, become available.

20-9

8044AH/8344AH

."','

FRAME OPTION

NFCS

NB'

FRAME FORMAT

AM'

Stondord SDLC
NON·AUTOM_

Stondoni SDLC
AUTO Mode

I F'I>A I C I"

Non-Bullereel M_
NON·AUTO Mode·

I"F

IFcsl F I.

I ~I c I,

I F I A I

No....Addre._ Mode
NON·AUTOM_

IF I

I Fcsi F, I

No ,FCS Field,
NO'I'l-AUTO M_

I FIAlc I

No FCS Field
AUTOM_'

r-I-F-'I-A-rl-c'I----''--'--.I-F--.I''

No FCS Field
Non·Bullered M_
NON·AUTO Mode

I F I A I

=~:;!t~:~~d'Mode

I F, I

IFI

F I

NON·AUTO Mode

Mod. Blto:
AM
- "AUTO" Mode/Addr••••d M_
NB
- Non-Bullered Mod.'
NFCS - No'FCS· Field Mode
,

Key to Abbrevlotlons:
F ~ Fllg (01111110)
A
Addre.. Field
C = Control Field'

. Note 1:

I =Iniormliion Field .
FCS = Frame Chock Sequence

r~e ~M bit function, IS ~ontrolled by the N6 bit Wh~n NB = 0, A~ becomes AUTo'mOde select,
when NB = 1, AM becomes Address mode select

Figure 7. Frame FormatOptioi'ls

Data Clocking Options
The 8044's serial port can operate in an externally
clocked or seifclocked system: A clocked system provides to the 8044 a clock synchronization to the data.
A self-clocked system uses tile 8044'5 on-chip Digital
Phase Locked Loop (DPLL) to recover the clock from
the data, and clock this data into the Serial Receive
Shift Register.
'
,
'
In this mode, a clock synchronized with'thedata ,is
externally fed into the 8044. This clock may be
generated from an External Phase Locked Loop, or
possibly supplied along with the data. The 8044 can
transmit and receive data in this mode at rates u;J to
2.4 Mbps.
."
This self ,clocked.mode, allows data transfer without
a common. system data clock. An or:1-chip Digital
Phase Locked Loop is~mployed to recover the data
clock which is encoded in the data stream. The DPLL
will converge to the nominal 'bit center within eight

bit traositior;ls,worstcase. Th~' DPLL. r,equires 'a
reference clock of either 16 times (16x) pf,32 times
(32x) the data rate. This reference cloc'k may be externally applied or internally generated. When internally generateo ,either the 8044's internal logic clock
(crystal frequency divided t;>y t~o) or ,the timer,1
Overflow is used as the reference clock. Using, the in,ternal timer 1 clock the data reates Can varY fr,om 244
to 62.~ Kbps. Us!r9 the}nternat logic ci9i::k ,at a ~ 6x
sampling rate, receive; C\a~acan either be.187.5 Kbps,
or 379 Kbps. When the reference clock ,for tl:)e DPLL
is externally applied)hegata rates.ci~ vary frO.m 0
to 375 Kbps at a 16x sampling rate.
To aid in a Phase Locked Loop capture, the slufi1:is
a NRZI (Non Return to Zero Inverted) data encoding
and decoding option. Addjtjonallythe.SIl) hs,sapreframe sync opt[on that:transmits two .bY\e~ Qlalternating 1's and O's to ensure that the receive' station
DPLL wil!l~e synchronized with th:e data by the time
it receives the opening flag,

inter

8044AH/8344AH

SCM

Control and Status Registers

~..!...!l
0
0

There are three SIU Control and Status Registers:
Serial Mode Register (SMD)
Status/Command Register (STS)
Send/Receive Count Register (NSNR)
The SMD, STS, and NSNR registers are all cleared by
system reset. This assures that the SIU will power up in
an idle state (neither receiving nor transmitting).

Clock Mode

Data Rate
(BitsLsecl*

Self clocked, external 32x
Self clocked, internal fixed
Self clocked, internal fixed

0-187.SK
375K
187.5k

* Based on a 12 Mhz crysta.I frequency
··0-1 M bps in loop configuration
STS: Status/Command Register (bit-addressable)

These registers and their bit assignments are
describecj below.

Bit:

ITBF IRBE IRTS ISII BOV IOPB lAM I RBP I

SMD: Serial Mode Register (byte-addressable)

The Status/Command Register (Address C8H) provides operational control of the SIU by the 8044 CPU,
and enables the SIU to post status information for the
ISCM21 SCM I ISCMO INRZI ILOOP IPFS INB INFCS I
CPU's access. The SIU can read STS, and can alter certain bits, as indicated below. The CPU can both read
The Serial Mode Register (Address C9H) ~elects the
and write STS asynchronously. However, 2-cyde inoperational modes of the SIU. The 8044 CPU can both
structions that access STS during both cycles (,JBC/B,
read and write SMD. The SIU can read SMD but canREL' and 'MOV /B,C.') should not be used; since the
not write to it. To prevent conflict between CPU and
SIU may write to STS between the two CPU accesses.
SIU access to SMD, the CPU should write SMD only
when the Request To Send (RTS) and Receive Buffer
The individual bits of the Status/Command Register
Empty (RBE) bits (in the STS register) are both false
are as follows:
(0). Normally, SMD is accessed only during
initialization.
Name Description
Bit#
The individual bits of the Serial Mode Register are as
follows:
STS.O
RBP Receive Buffer Protect. Inhibits
writing of data into the receive buffName Description
Bit #
er. In AUTO mode, RBP forces an
NFCS No FCS field in the SDLC frame.
SMD.O
RNR response instead of an RR.
NB
Non-Buffered mode. No control
SMD.I
STS.I
AM
AUTO Mode/Addressed Mode. Sefield in the SDLC frame.
lects AUTO mode where AUTO
mode is allowed. If NB is true,
SMD.2
PFS
Pre-Frame Sync mode. In 'this
(= I), the AM bit selects the admode, the 8044 transmits two bytes
dressed mode. AM may be cleared
before the first flag of a frame, for
by the SIU.
DPLL synchronization. If NRZI is
enabled, OOH' is sent; otherwise,
STS.2
OPB Optional Poll Bit. Determines
SSH is sent. In eithe.r case, 16 prewhether the SIU will generate an
frame transitions are guaranteed.
AUTO response to an optional poll
(UP with P"",O). OPB may be set or
SMD.3
LOOP Loop configuration.
cleared by the SIU.
SMD.4
NRZI NRZI coding option.
STS.3
BOV Receive Buffer Overrun. BOV may
SMD.S
SCMO Select Clock Mode - Bit 0
be set or cleared by the SIU.
SMD.6
SCM I Select Clock Mode - Bit I
STS.4
SIU Interrupt. This is one of the five
SI
SMD.7
SCM2 Select Clock Mode - Bit 2
interrupt sources to the CPU. The
vector location = 23H. SI may be
The SCM bits decode as follows:
set by the SIU. It should be cleared
SCM
Data Rate
l:lY the CPU before returning from
(BitsLsecl*
an interrupt routine.
~..!...!l Clock Mode
Externally clocked
0-2.4M**
0 0 0
STS.5
RTS Request To Send. Indicates that the
8044 is ready to transmit or is trans0 0 I
Reserved
mitting. RTS may be read or writ0
0 . Self clocked, timer overflow 244-62.SK
ten by the CPU. RTS may be read
Reserved
0
I
by the SIU, and in AUTO mode
may be written by the SIU.
Self clocked, external16x
0-37SK
0 0
Bit: 7

20-.11

8044AH18344AH

RBE

STS.6

TBf

STS.7

Receive Buffer Empty. RBE can be
thought of as Receive Enable. RBE
is set to one by the CPU when it is
ready to receive a frame, or has just
read the buffer, and to zero by the
SIU when a frame has been
received.
Transmit Buffer full. Written by
the CPU to indicate that it has filled
the transmit buffer. TBf may be
cleared by the SIU.

INS2INSIINsolsESINR21~RIINROlsERI

The Send/Receive Count Register (Address D8H) contains the transmit and receive sequence nUIllbers, plus
tally error indications. The SIU can both read and write
NSNR. The 8044 CPU can both read and write NSNR
asynchronously. However, 2-cycle instructions that access NSNR during both cycles ('JBC /B, REL', and
'MOV /B,C') should not be used, since the SIU may
write to NSNR between the two 8044 CPU accesses.
The individual bits of the Send/Receive Count Register
are as follows:
BitH
NSNR.O
NSNR.l
NSNR.2
NSNR.3
NSNR.4

NSNR.5
NSNR.6
NSNR.7

~ Descril!tion
SER Receive Sequence Error:
NS (P) "" NR (S)
NRo Receive Sequence Counter-Bit 0

NRI
NR2
SES

NSO
NSI
NS2

TBS: Transmit Buffer'Start Address Register
(byte-addressable)

The Transmit Buffer Start address register (Address
DCH) points to the location in on-chip RAM for the beginning of the I-field of the frame to be transmitted. The
CPU should access TBS only when the SIU is not transmitting a frame (when TBf=O).
TBl: Transmit Buffer length Register
(byte-addressable)

NSNR: Send/Receive Count Register (bitaddressable)

Bit:

and RBE=O). Normally, ~TAD is accessed only during
initialization.

Receive Sequence Counter-Bit I
Receive Sequence Counter-Bit 2
Send Sequence Error:
NR (P) -# NS (S) and
NR (P)-# NS (S) + I

The Transmit Buffer. Length register (Address DBH)
contains the length (in bytes) of the I-field to be transmitted. A blank I-field (TBL=O) is valid. The CPU
should access TBL only when the SIU is not transmitting a frame (when TBF=O).
NOTE: The transmit and recieve buffers are not allowed
to "wrap around" in the on-chip RAM. A "buffer end"
is automatically generated if address 191' (BFH) is
reached.
TCB: Transmit Control Byte Register
(byte-addressable)

The Transmit Control Byte register (Address DAH)
contains the byte which is to be placed in the control
field of the transmitted frame, during NON-AUTO
mode transmission. The CPU should access TCB only
when the SIU is not transmitting a frame (when
TBF=O). The Ns and NR counters are not used in the
NON-AUTO mode.
RBS: Receive Buffer Start Address Register
(byte-addressable) .

The Receive Buffer Start address register (Address
CCH) points to the location in on-chip RAM where the
begi'nning of the I-field of the frame being received is to
be stored. The CPU should write RBS only when the
SIU is not receiving a frame (when RBE=O).

Send Sequence Counter - Bit 0
Send Sequence Counter - Bit I
Send Sequence Counter - Bit 2

RBl: Receive Buffer length' Register
(byte-addressable)

Parameter Registers
There are eight parameter registers that are used in connection with SIU operation. All eight registers may be
read or written by the 8044 CPU. RfL and RCB are
normally loaded by the SIU .
The eight parameter registers are as follows:

The Receive Buffer Length register (Address CBH)
contains the length (in bytes) o(the area in on-chip
RA'M allocated for the received I-field. RBL=O is valid. The CPU should write RBL only when RBE=O.
RFl: Receive Field length Register
(byte-addressable)

STAD: Station Address Register
(byte-addressable)

The Station Address register (Address CEH) contains
the station address. To, prevent ac<;ess conflict, the CPU
should access STAD only when the SIU is idle (RTS=O

The Received Field Length register (Address CDH)
contains the length (in bytes) of the received I -field that
has just been loaded into on-chip RAM. RfL is loaded
by the SIU, RfL=O is valid. RFL should be accesssed
by the CPU only when RBE=O.

20-12

8044AH/8344AH

RCB: Receive Control Byte Register
(byte-addressable)

The Received Control Byte register (Address CAH)
contains the control field of the frame that has just been
received. RCB is loaded by the SIU. The CPU can only
read RCB, and should only access RCB when RBE=O.

ICE Support Registers
The 8044 In-Circuit Emulator (ICE-44) allows the user
to exercise the 8044 application system and monitor the
execution of instructions in real time.
The emulator operates with Intel's Intellec@ development system. The development system interfaces with
the user's 8044 system through an in-cable buffer box.
The cable terminates in a 8044 pin-compatible plug,
which fits into the 8044 socket in the user's system. With

20-13

the emulator plug in place, the user can excercise his system in real time while collecting up to 255 instruction
cycles of 'real-time data. In addition, he can single-step
the program.
Static RAM is available (in the in-cable buffer box) to
emulate the 8044 internal and external program memory and external data memory. The designer can display
and alter the contents of the replacement memory in the
buffer box, the internal data memory, and the internal
8044 registers, including the SFRs.
SIUST: SIU State Counter (byte-addressable)

The SIU State Counter (Address D9H) reflects the
state of the internal logic which is under SIU control.
Therefore, care must be taken not to write into this
register. This register provides a useful means for
debugging 8044 receiver problem,

8044AH/8344AH

• Nollce: Stresses above those ,listed under "Absolute'
Maximum Ratings" may cause perman,ent damage to
the deVice, This IS a stress rating only and functional
operation of the device at these or any other conditions
above those indicated In the operalional sections of
this specificallon IS not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability,

ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias". .
, .,0 to 70'C
Storage Temperature
.. -65'C to + 150'C
Voltage on Any Pin With
Respect to Ground (Vss) ..
, . , - 0,5V to + 7V
Power Dissipation" , .'
,... ,.2 Watts

DC CHARACTERISTICS (TA=O'C to 70'C, VCC = 5V ± 10%, VSS = OV)

Symbol

Parameter

Max

Units

-0.5

0,8

Input High Voltage
(Except RSTIVPD and XTAL2)

VCC +0 5

VIHI

Input High Voltage To
RSTIVPD For Reset, XTAL2

VOL

Output Low Voltage
Ports I, 2, 3 (Note 1)

VOLI

Output Low Voltage
Port 0 ALE, \PSEN (Note 1)

VOH

Outpt High Voltage
Ports I, 2, 3

VOHI

Output High Voltage
Port 0, ALE, \PSEN

IlL

Logical 0 Input Current
Ports I, 2, 3

IIHI
III

VIL

Input Low Voltage

VIH

Min

Typ

Test. Conditions

XTALI to VSS

0.45

V·

10L= 1 6mA

045

IOL=3.2mA

10H= -80flA

2.4

10H= -400"A

-800

XTALI at VSS
VIL = 0,45V

Input High Current.TO
RSTIVPD For Reset

500

Vin=VCC-l.5V

Input Leaka~ Current
To Port 0, \EA

flA

200

TA=25'C

Ic = lMHz

-3,5

XTAl1 = VSS
VIL = 0,45V

ICC

Power Supply Current

CIO

Capacitance of 1/0 Buffer

IIL2

Logical 0 Input Current
XTAL 2

125

0.45V

Vin

< VCC

Note 1: VOL IS degraded when the RUPI·44 rapidly discharges external capacitance This A.C. noise is most pr~nbunced dUring
emission of address data. When uSing external memory, locate the latch or buffer as close to the RUPI·44 as possible.

Datum
Address
Write Data

Degraded
I/O Lines

VOL
(peak)
(max)

P2, PO

PI, P3

,8V

PI, P3, ALE

,8V

Emitting
Ports

2()"t4

8044AH/8344AH

A.C. CHARACTERISTICS (TA O·C to 70·C, VCC = 5V ± 10 0;. 'SS= OV, CL for Port 0, ALE and PSEN Outputs = l00pF;
CL for All Other Outputs

= ao pF)

Program Memory

Symbol

Parameter

12 MHz Clock
Min
Max
Units

Variable Clock
1ITCLCL = 1.2 MHz to 12 MHz
Min
Max
Units

TLHLL

ALE Pulse Width

127

2TCLCL-40

TAVLL

Address Setup to ALE

TCLCL-40

TLLAX'
TLLlV

Address Hold After ALE

TCLCL·35

TLLPL
TPLPH

ALE To Valid Instr In
ALE To PSEN
, PSEN Pulse Width

TPLIV

PSEN To Valid Instr In

TPXIX

Input Instr Hold After PSEN

TPXIZ"

Input Instr Float After PSEN

TPXAV'

Address Valid After

TAVIV
TAZPL

Address To Valid Ins!r In
Address Float To PSEN

PsEN

233

TCLCL·25

215

3TCLCL·35

125

ns,

ns
4TCLCL·l00

ns
ns
3TCLCL·125

ns
302

ns
ns

-25

ns
ns

TCLCL·20

5TCLCL·115

ns
ns

TCLCL-8

-25

Notes:
1, TLLAX for access to program memory IS different from TLLAX for data memory,
2, Interfacing RUPI·44 devices with float times up to 75ns is perrnissible, ThiS limited bus contention Will not cause any damage to Port
o drfvers.'
.

External Data Memory

Symbol

Parameter

12 MHz Clock
Min
Max
Units

Variable Clock
1ITCLCL = 1.2 MHz to 12 MHz
Max
Min
Units

TRLRI:i

Ro Pulse Width

400

I'S

6TCLCL·1OQ

TWLWH

WR Pulse Width

400

6TCLCL·l00

ns
ns

TCLCL·35

Address Hold After ALE
TLLAX'
TRLoV ' . RD· To Valid Data In

250

5TCLCU65

TRHoX

Data !:lold After Ro

TRHDZ

Data Float After Ro

2TCLCL·70

TLLoV

ALE To Valid Data In

517

8TCLCL·150

TAVoV

Address To Vand Data In

585

9TCLCL·165

TLLWL
TAVWL

ALE To WR or Ro
Address To WR or Ro

200
203

300

ns
ns

3TCLCL·50
4TCLCL·130

3TCLCL+50

ns
ns

123

TCLCL+40

TWHLH

WR or Ro High To ALE High

TCLCL·40

ToVWX

pat a Valid To WR Transition

TCLCL·50

TOVWH

Data Setup Before WR

433

7TCLCL·150

TWHOX

Data Hold After WR

TCLCL·50

TRLAZ

Address Float After

Note 1. TLLAX for access· to program memory IS different from TLLAX for access data memory

Serial Interface
Symbol

Parameter

Min

Max

Units

ToCY.

Data Clock

420

TDCL

Data Clock Low

180

ToCH

ollta Clock High

100

20-15

ns
0

inter

8044AH/8344AH -

Serial Interface- (Continl,le(tl -

,2'~~~'--~~~J:l~~'y'---

lTD
toSS
tDHS

Data Setup Time

- - r~-

180

D;t;-HoIdTim~ -

f-- ---- - - - -

- '40~

WAVEFORMS
Memory Access

Program Memory Read Cycle
~------------------------------TCY--------------------------~

ALE

PSEN

~-;-~"jTPXAV

A7-AD

PORTO

PORT2

ADDRESS
OR SFR-P2

ADDRESSA15-A8

INSTR IN

ADDRESS A15-AS

Data Memory Read Cycle
-----TLLDV ------------~

TWHLH

ALE

PSEN
RD

-----------r-------,

~~------·--_+TRLRH'------------~.r_----

TLLAX

TRHDX

A7-AO

PORTO

QATA IN,
TRLAZ

PORT2

ADDRESS
OR SFR-P2

ADDRESS A15-AS OR SFR-P2

Data Memory Write Cycle
TWHUj
ALE

PSEN

___________

-+~------~_{ 14------------TWLWH----------~1,----

TOVWH
DATA OUT

PORTO

PORT 2

ADDRESS A15-A8 OR SFR-p2

20-16

'rWHOX

8044AH/8344AH

SERIAL 1/0 WAVEFORMS

Synchronous Data Transmission

----------~ ~------TDCl----~ r-----------~

SClK

DATA

TID

Synchronous Data Reception

TOCY
SClK

TOCl

TOCH

....;

DATA

\
....,

TOSS

20-17

TDHS

8044AH/8344AH

AC TESTING INPUT, OUTPUT, FLOAT WAVEFORMS

INPUT/OUTPUT

2.4=>(20
0.45

TEST POINTS
~0.::.8_ _ _ _ _ _

2o.'0
8

FlOAT

2.4

2.0

0.45

-FlOAT----....,t
2.0

0.....8 - - - - - - - - - 0 . 8

AC testing Inputs'are driven at 2 4V for a logiC "1" and 0 45V tor a logic "0 ..
TIming measurements are made at 20V for a logiC "1" and 08V for a logiC "0"

EXTERNAL CLOCK DRIVE XTAL2

TCHCl

1-0-------

Symbol
TClCl
TCHCX
TClCX
TClCH
TCHCL

Parameter
Oscillator Period
High Time
low Time
Rise Time
Fall Time

TClCl------~

Variable Clock
Freq = 1.2 MHz to 12 MHz
Min
Max
83.3
287.5
20
TClCl·TClCX
20
TClCl·TCHCX

20
20

20-18

Unit
ns
ns
ns
ns
ns

2.4

0.45

8044AH/8344AH

CLOCK WAVEFORMS
STATE 5

INTERNAL
CLOCK

STATE 6
Pl
P2

I P2

'STATE 1
Pl I P2

STATE 5

STATE 2
Pl I P2

I P2

XTAL2

::2
I

ALE
EXTERNAL PROGRAM MEMORY FETCH
PSEN

'----=-_......1

I
THESE SIGNALS ARE NOT
ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION

I'"

P2(EXT)

_ _ _ _ _..... INDICATES ADDRESS TRANSIONSI..._ _ _ _ _ _ _ _ _ _ _......

READ CYCLE
RD
OOH IS EMITTED
DURING THIS PERIOD
DPL OR RI
OUT

PO
P2
WRITE CYCLE

LY
4j:

PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)

IDATAl

FLOAT SAMPLED

•

in~

INDICATES DPH OR P2 SFR TO PCH TRANSITIONS

I PCL OUT(EVEN IF PROGRAM

L-_ _ _ _ _ _ _ _ _ _---' MEMORY IS INTERNAL) .

DPL OR RI
OUT

DATA OUT

INDICATES DPH OR P2 SFR TO PCH TRANSITIONS

.5.;

tCL OUT :1h;OGRAM

I MEMORY IS EXTERNAL)

PORT OPERATION
MOV PORT, SRC

OLD DATA

I NEW DATA

___LPO PINS SAMPLED

~O~P~I~N~S~S~A~M=P~L=ED=----~-----------~~c::::::::J

MOV DES" PO
MOV DEST, PORT (Pl, P2, P3)

(INCLUDES INTO, INn, TO, n)
SERIAL PORT SHIFT CLOCK

~L.----------------------I- \ - L....Pl, P2, P31'INS SAMPLED

::N~2S:~PLED

~----q:r
RXD SAMPLED

J~gDE O)--------~XD SAMPLED

This diagram indicates when signals are clocked Internally The time It takes the signals to propagate to the pins, however,
ranges from 25 to 125 ns This propagation delay IS dependent on vanables such as temperature and Pin loading Propagation
also vanes from outp6t to output and component to component TYPically though, (TA " 25° C, fully loaded) RD and WR propagation delays are approximately 50 ns The other signals are tYPically 85 ns Propagation delays are Incorporated In the AC
. specifications

20-19

8744H
HIGH PERFORMANCE 8-BIT MICROCONTROLLER
WITH On-CHIP SERIAL COMMUNICATION CONTROLLER
8051 MICROCONTROLLER CORE
• Optimized for Real Time Control
12 MHz Olock, Priority Interrupts,
- 32 Programmable I/O lines,
Two 16·bit Timer/Counters
• Boolean Processor
•

4K x 8 EPROM, 192 x 9 RAM

•

64K Accessible External Program
Memory

•

64K Accessible External Data Memory

.• 4 I-IS Multiply and Divide

SeRIAL INTERFACE UNIT (SIU)
•

Serial Communication Processor that ,
Operates Concurrently to CPU

•

2.4 Mbps Maximum Data Rate

•

375 Kbps using On·Chip Phase
Locked Loop

• Communication Software in Silicon:
.- Complete Data Link Functions
- Automatic Station Responses
• Operates as an SDLC Primary or
Secondary Station

The RUPI-44 family integrates a high performan.ce S-bit Microcontroller, the Intel S051 Core, with an
intelligent/high performance HOLC/SOLC serial communication controller, called the· Serial Interface
Unit (SIU). See Figure 1. This dual architecture allows complex control and high speed data communication functions to be realized cost effectively.
Specifically, the S044's Microcontroller features: 4K byte On-Chip program memory space; 32 I/O lines;
two 16-bit timer/event counters; a 5-source; 2-level interrupt structure; a full duplex serial channel; a
Boolean processor; and on,chip oscillator and clock circuitry. Standard TTL and most byte-oriented
MCS-SO and MCS-S5 peripherals can be used for I/O and memory expansion.
The Serial Interface Unit (SIU) manages the interface to a high speed serial link. The SIU offloads the
On-Chip S051 Microcontroller of communication tasks, thereby freeing the CPU to concentrate on real
time control tasks.
The RUPI-44 family consists of the 8044,8744, and S3t4.'AIi three devices are identical except in respect
of on-chip program memory. The S044 contains 4K bytes of mask-programmable ROM. User programmable EPROM replaces ROM in the S744. The 8344 addresses all program memory externally.
The RUPI-44 devices are fabricated with Intel's reliable +5 volt, Silicon-gate HMOSII technology and
packaged in a 40-pin DIP
The 8744H is available in a hermetically sealed, ceramic, 40-lead dual incline package which includes a
window that allows for EPROM erasure when exposed to ultraviolet light (See Erasure Characteristics).
During normal operation, ambient light may adversely affect the functionality of the chip. Therefore,
applications which expose the 8744H to ambient light may require an opaque label over the window.

8044'5 Dual Controller Architecture
Contro I
Lines

8051
Microcontroller

---

2-port
RAM

S.I.U.

HDLC/
SOLC
port

Figure 1. Dual Controller Architecture
Intel Corporation Assumes No Responsibility for the Use of Any CircUItry Other Than CircUitry Embodied In an Intel Product No Other Circuit Patent Licenses are Implied
• INTEL CORPORATION" 1982

20-20

ORDER NUMBER: 210735-002

· 8744H
Table 1. RUPITM ·44 Family Pin Description

vee

+ 5V power supply during operation and program
verification.

-SCLK T1 (P3.5). In addition to I/O, this pin provides in·
QQ!. to counter 1 or serves as SCLK (serial clock) input.
-WR (P3.6). The write control signal latches the data
~e from Port 0 into the External Data Memory.
-RD (P3.7). The read control signal enables External
Data Memory to Port O.

PORTO
Port 0 is an 8·bit open drain bidirectional I/O port. It is
also the multiplexed low·order address and data bus
when using external memory. It is used for data output
during program verification. Port 0 can sink/source eight
LS TIL I·oads.

RST
A high on this pin for two machine cycles while the
oscillator is running resets the device. A small external
pulldown resistor (""'ll.2kQ) from RST to Vss permits
power·on reset when a capacitor (=10pf) is also connected from this pin to Vcc.

VSS
Circuit ground potential.

PORT 1
Port 1 is an 8·bit quasi·bidirectional I/O port. It is used for
the low·order address byte during program verification.
Port 1 can sink/source four LS TIL loads.
In non·loop mode two of the I/O lines serve alternate
functions: .
-RTS (Pl.6). Request·to·Send output. A low indicates
that the RUPI·44 is ready to transmit.
-CTS (Pl.?) Clear·to·Send input. A low indicates that a
receiving station is ready to receive.

ALEIPROG
Provides Address Latch Enable output used for latching
the address into external memory during normal opera·
tion. It is activitated every six oscillator periods except
during an external data memory acCess. It also receives
the program pulse input for programming the EPROM
version.

PORT 2
Port 2 is an 8-bit quasi-bidirection I/O port. It also emits
the high-order address byte when accessing, external
memory. It is used fo~ the high.order address and the
control signals during program verification. Port 2 can
sink/source four LS TTL loads.

PSEN
The Program Store Enable output is a control Signal
that enables the external Program Memory to the bus
during external fetch operations. It is activated every
six oscillator periods, except during external data
memory accesses. Remains high during i"ternal pro·
gram execution.

PORT 3
Port 3 is. an 8-bit quasi·bidirectional I/O port. It also
contains the interrupt, timer, serial port and RD and
WR pins that are used by vl;lrious options. The output
latch corresponding to a secondary function must be pro·
grammed to a one (1) for that function to operate. Port 3
can sink/source LS TTL loads.

EAlVPP
When held at a TTL high level, the RUPI-44 executes in·
structions from the intesnal ROM when the PC is less
than 4096. When held at a TIL low level, the RUPI-44 fet·
ches all Instructions from external Program Memory.
The pin also receives the 21V EPROM programming supply voltage on the 8744.

In addition to I/O, some of the pins also serve alternate
functions as follows:
-I/O RxD (P3.0). In point·to-point or multipoint configura·
tions, this pin controls the direction of pin P3.1. Serves
as Receive Data input in loop and diagnostic modes.
-DATA TxD (P3.1) In point·to-point or multipoint configurations, this pin functions as data input/output. In
loop mode, it serves as transmit pin. A '0' written to
this pin enables diagnostic mode.
-INTO.(P3.2). Interrupt 0 input or gate.control input for
counter O.
-INTl (P3.3). Interrupt 1 input or gate control input for
counter 1.
- TO(P3.4). Input to counter O.

XTAL 1
Input to the oscillator's high gain amplifier. Required
when a crystal is used. Connect to VSS when external
source is used on XTAL 2.

20-21

XTAL2
Output from the oscillator's amplifier. Input to the internal timing circuitry. A crystal or external source can be
used.

ORDER NUMBER: 210735-002

8744H

P' 2 [

POI

AOI

P' 1 [
P' • [

•
,

PO.2

A02

P' 5 [

RTS

P'SI

J PO 5 ADS

P1T[

J PO.I

RST
RXD

1/0

OATA

~{
!i!g

::11~~~

110

RXo ....

DATA

SClK

~-+-

SCLK

vee

P' 0
P, , [

PO 0 AOO

PO 3 A03
PO.O

ADO
A08

AoT

P30

-ypp

~Pmi

TXo

P3 1 I

INTO

P32

INT1

P33[

13'

)P21

PH [

jP26 'A14

P3 5 I

ViA
iiO

PHI

ALE

PROG
"15

P25

A13

JP24

A'2

All

XTAL2 [

18
"

P2.2 A'O
P21 A9

P2.0

P37

WR'4-

XTALI [

RO~

VSS [

(20

2.4

2.0.)C
TEST POINTS

0.45

;..:0:;:.8:....._ _ _ _ _....::;0.::..8
0.45

2.4

0...

AC testing inputs are driven at 2.4V for a logic 1 and O.45V for a logic 0
Timing measijr$ments a,,~ made at 2.0V for a logic 1 and O.SV for a logic 0
For timing purposes, the float state is defined as the point at which a PO pin sinks 3.2mA or sources 400J'A at the voltage test levels

SERIAL UO WAVEFORMS

Synchronous Data Transmission
~-----------TOCY-----------<~

---------........ t-----'TDCL - - - . I

r-----------""""\

sCLK

~------------~~------TDCH

DATA

TTO
Synchronous Data Reception
~-------------TDCY------------~

sCLK

- - - - - -........

~---TDCL---__l

,..---------"

~---TDCH--__l

DATA

TOSS

~---------TOHS-------------.I

20-25

ORDER NUMBER: 210735·002

~[f,j[g[bOIMlOOO~IfJ~

8744H

Serial Interface
Parameter

Symbol

Min

Max

Units

TDCY

Data Clock

420

TDCL

Data Clock Low

180

TDCH

Data Clock High

100

TTD

Transmit Data Delay

TOSS

Data Setup Time
Data Hold Time

TDHS

180
40
40

ns
ns
ns

Memory Access
Program Memory Read Cycle
~--------------~-------------TCY------------------------~

ALE

PSEN
INSTR IN

A7-AD

PORTO

ADDRESS A15-A8

PORT 2

Data Memory Read Cycle
TWHLH
ALE

----------------~------------~ ~~--------_+TRLRH----------~~/------TRHDX
DATA IN

PORTO
TRLAZ
ADDRESS A15-A8 OR SFR- P2

PORT2

Data Memory Write Cycle
TWHLH
ALE

________________~----------~I.~--------TWLWH----------~~-----

TaVWH

PORT2

TWHOX

DATA OUT

PORTO

ADDR!;SS A15-A8 OR SFR-P2

20-2d

ORDER NUMBER: 210735·002

8744H

NOTE: VOL is degraded when the 8744H rapidly discharges external capacitance. This AC noise is most pronounced
during emission of address data. When using external 'memory, locate the latch or buffer as close to the 8744H
as possible.

Degraded
I/O Lines

VOL
(peak)
(max)

Datum

Emitting
Port,

Address

P2, PO

P1, P3

0.8V

Write Data

P1, P3, ALE

0.8V

,
EXTERNAL CLOCK DRIVIE CHARACTERISTICS (XTAL2)
Symbol

Parameter

Min

Max

Units

83.3

285.7

TCLCL

Oscillator Period: 8751 H

TCHCX

High Time

TClCX

Low Time

TCLCH

Rise Time

TCHCL

Fall Time

ns
ns

l_rCHCL

0.8

l~rCLcx-1

1-------rcLCL-- ------

20-27

ORDER NUMBER: 210735-002

8744H

CLOCK WAVEFORMS

INTERNAL
CLOCK

STATE 4
Pl

I P2

STATE 5

STATES

I P2

STATE 3

I P2

STATE 4

STATE 5

I P2

XTAl2

::2
I

ALE
EXTERNAL PROGRAM MEMORY FETCH

I
THESE SIGNALS ARE NOT
ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION

,----'...._=-----'1

PSEN

=-____.... INDICATES ADDRESS TRANSITIONS

P2(EXT)
READ CYCLE

-J

L.I- : -_ _ _ _ _ _ _- :_ _

RD
OOH IS EMITTED
.
DURING THIS PERIOD

DPl OR Ri
OUT

PO
P2
WRITE CYCLE

L~"

I- ..-:

FLOAT

PCl OUT (IF PROGRAM
MEMORY IS EXTERNAL)

SAMPLED

r\l.-

.•i

INDICATES DPH OR P2 SFR TO PCH TRANSITIONS

I PCl OUT(EVEN iF PROGRAM

1-_ _ _ _ _ _ _ _ _ _---' MEMORY IS INTERNAL)

DPl OR RI
OUT

PO
P2

DATA OUT

INDICATES DPH OR P2 SFR TO PCH TRANSITIONS

.B-:i

tCl OUT ;1h;OGRAM

I MEMORY IS EXTERNAL)

PORT OPERATION

MOV PORT. SRC
MOV DE ST. PO

OLD DATA NEW DATA

MOV DEST, PORT (Pl. P2, P3)
(INCLUDES INTO. INT1. TO. T1]
SERIAL PORT SHIFT CLOCK

SAMPLED

!--4l

~I..______- . - - - - - - - - - - - - - - - - - - J - - - - C P O P I N S

c::::::J

PO PINS SAMPLED

~'-----------------------r,
Pl. P2. P3 PINS SAMPLED

L--

:~N~2S:~PLED

q:r

I . . - -_ _ _

i~gDE O)--------~XDSAMPLED

RXD SAMPLED

ThiS diagram Indicates when signals are clocked Internally. The time It takes the signals to propagate to the pins, however,
r<\nges from 25 to 125 ns. ThiS propagation delay is dependent on variables such as temperature and pin loading. Propagation
also varies from output to output and component to component TYPically though, (TA =25°C, fully loaded) RD and WRpropagatlon delays are approximately 50 ns. The other signals are tYPically 85 ns. Propagation delays are Incorporated In the AC
specifications

20-28

ORDER NUMBER: 21(

inter

8744H

8744H EPROM CHARACTERISTICS
Erasure Characteristics
Erasure of the 8744H Program Memory begins, to
occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 Angstroms.
Since sunlight and fluorescent lighting, have wavelengths in this range, constant exposure to these
light sources over 'an extended period of time (about
1 week in sunlight, or 3 years in room-level fluOfescent lighting) could cause unintentional erasure. If
an application subjects the 8744H to this type of
exposure, it is suggested that an opaque label be
placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm2 rating for 20
to 30 minutes, at a distance of about 1 inch, should
be sufficient.

Program Memory Security
The program memory security feature is developed
around a "security bit" in the 8744H EPROM array.
Once this "hidden bit" is programmed, electrical
access to the contents of the entire program memory
array becomes impossible. Activation of this feature
is accomplished by programming the 8744H as
described in "Programming the EPROM" with the
exception that P2.6 is held at a TIL high rather than
a TIL low. In addition, Port 1 and P2.0-P2.3 may be
in any state. Figure 4 illustrates the security bit programming configuration. Deactivating the security
feature, which again allows programmability of the
EPROM, is accomplished by exposing the EPROM
to ultraviolet light. This exposure, as described in
"Erasure Characteristics," erases the entire EPROM
array. Therefore, attempted retrieval of "protected
code" results in its destruction.

Erasure leaves the array in an all 1s state.
Programming the EPROM
To be programmed, the 8744H must be running with
a 4 to 6 MHz oscillator. (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appropriate registers.) The address of an EPROM location
to be programmed is applied to Port 1 and pins
P2.0-P2.3 of Port 2, while t~ta byte is applied to
Port O. Pins P2.4-P2.6 and PSEN shQuld be held low,
and P2.7 and RST high. (These are all TIb.Jevels
'except RST, which requires 2.5V for high.) EANPP
is held normally high, and is pulsed to +21V. While
EANPP is at 21V, the ALE/PROG pin,. which is
normally being held high, is pulsed low for 50 msec.
Then EANPP is returned to high. This is illustrated
in Figure 3. Detailed timing specifications are pro~
vided in the EPROM Programming and Verification
Characteristics section of this data sheet.

Program Verification
Program Memory may be read only when the
"security feature" has not been activated. Refer to
Figure 5 for Program Verification setup. To read the
Program Memory, the following procedure can be
used. The unit must be running with a 4 to 6 MHz
oscillator. The address of a Program Memory location to be read is applied to Port 1 and pins P2.0P2.3 of Port 2. Pins P2.4-P2.6 and PSEN are held at
TIL low, while the ALE/PROG, RST, and EANPP
pins are held at TIL high. (These are all TTL levels
except RST, which requires 2.5V fOT high.) Port 0
will be the data output lines. P2.7 can be used as a
read strobe. While P2.7 is held high, the Port 0 pins
float. When P2.7 is strobed low, the contents of the
addressed location will appear at Port O. Extemal
pullups (e.g., 10K) are required on Port 0 during
program verification.

20-29

ORDER NUMBER: 210735-002

intJ

8744H

+5V

Vee

ADDR.-

OOOOHOFFFH

f--

8744H
PO

I~ .PGM DAl'~

-- P2.4

-b

P2,5

ALE -

- ALE PROG

P2.6
TTL HIGH

P2.7

0 I
~

EA --"-- l:AIVPP

XTAL2

....L ..L
4-6 MHz

1--

-::-

RST -_._.- VI HI

XTALI
Vss

Figure 3. Programming Configuration

+5V.

P2.0P2.3

Vee
8744H

-::!::-

TTLHI'GH

....L

4-6 MHz

•
-'-

P2.4
P2.5

_ ALE/PROG 50 ms PULSE TO GND

ALE -

P2.6
P2.7
XTAL2

- ~'EA/VPP +21V PULSE

EA -

0 I
T

1-.
~

XTALI
Vss

RST r----.

-- VIHI

PSEN C-',

Figure 4. Security Bit Programming Configuration

20-30

ORDER NUMBER: 210735-002

intJ

8744H

+SV

Vee

P1
8744H
P2.0P2.3

1-------'\ PGM DATA
PO

P2.4
P2.S

ALE

P2.6
P2.7

ENABLE

XTAL2

(USE 10K PULL UPS)

--r-

TTL HIGH.

...J
VIH1

RST

XTALl

VSS

Figure 5. Program Verification Configuration

EPROM PROGRAMMING, SECURITY BIT PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 27°C, VCC = 4.5V to 5.5V, VSS = OV)

Parameter

Symbol
Vpp

Programming Supply Voltage

IPP

Programming Current

Min

Max

20.5

21.5

MHz

1ITCLCL

Oscillator Frequency

TAVGL

Address Setup to PROG

48TCLCL

TGHAX

Address Hold after PROG

48TCLCL

TDVGL

Data Setup to PROG

48TCLCL

TGHDX

Data Hold after PROG

48TCLCL

TEHSH

ENABLE High to Vpp

48TCLCL

TSHGL

Vpp Setup to PROG

TGHSL

Vpp Hold after PROG

TGLGH

PROGWidth

TAVQV

Address to Data Valid

TELQV

ENABLE to Data Valid

TEHQZ

Data Float after ENABLE

Units

J,!sec
J,!sec
msec

55
48TCLCL
48TCLCL

20-31

48TCLCL

ORDER NUMBER: 210735-002

,&144H

EPROM PROGRAMMING, SECURITY BIT PROGRAMMING AND
, VERIFICATION WAVEFORMS

-i

P1.0·P1.7
P2.0.P2.3

PROGRAMMING

VERIFICATION

ADDRESS

»r------

} ______A_D_D_R
__
E_SS
______

~~~--~-------

I~~I

------~I~------------------~(:~~D~A~TA~~OU~T~~=)r---------

PORTO

IroVGl-

1·"--1

TGHDX

i-1'AVGL--

UTGHAXI

AlEPROG
1

TSHGL

'1--- ~~:

. TGlGHi
21V ..5V '

EAVPP

\------TTL HIGH

--I
I-TEHSH

P2.7·

TTL HIGH

)

(ENAiitE!

TTl HIGH

1_ TEHOZ

TELOV

'----_...I

FOR PROGRAMMING CONDITIONS SEE FIG.URE 3.
FOR SECURITY BIT PROGRAMMING CONDITIONS SEE FIGURE 4.
FOR VERIFICATION CONDITIONS SEE FIGURE 5.
I

•

2(}:32

ORDER NUMBER: 210735-002

RUPFM Article Reprints

inter

ARTICLE
REPRINT

AR-307

NOVEMBER'1983

,
@

~anuary

1985

ORDER NUMBER 230876-001
,

INTEL CORPORATION
21-1

AR-307

acknowledgements, error checking/recovery, and data
transparency are not standardized nor supported by
available data comm chips.

SUMMARY

The 8044 offers a lower CO$t and higher performance
solution to networking microcontrollers than conventional solutions. The system cost 'is lowered by
integrating an entire microcomputer with an intelligent
HOLC/SOLC communication processor onto a single
chip. l'he higher performance is realized by integrating
two processors running concurrently on one chip; the
. powerful 8051 microcontroller and the Serial Interface Unit. The 805.1 microcontroller is substantially
off-loaded from the communication tasks when
using the AUTO mode. In the AUTO mode the SIU
handles many of the data link functions in hardware.
The advantages of the AUTO mode· are: less software
is required to implement a secondary station data link,
the 8051 CPU is offloaded, and the turn-around time
is reduced, thus increasing the network throughput.
Currently the 8044 is the only microcontroller with
a sophisticated communications processor on-chip. In
the future there will be more microcontrollers available
following this trend.

SOLC, Synchronous Oata Link Control, meets the
requirements for communications link design. The
physical medium can be used on two or four wire
twisted pair with inexpensive transceivers and connectors. It can also be interfaced through modems, which
allows it to be used on broadband networks, leased
or switched telephone lines. VLSI controllers have
been available from a number of vendors for· years;
higher performance and more user friendly SOLC controllers continue to appear. SOLC has also been
designed to be very reliable. A 16 bit CRC checks the
integrity of the received data, while frame numbering and acknowledgements are also built in. Using
SDLC, up to 254 stations can be uniquely addressed,
while HDLC addressing is unlimited. If an RS-422
only requires a single +5 volt power supply.

INTRODUCTION
Today microcontrollers are being designed into
virtually every type of equipment. For the household,
they are turning lip in refrigerators, thermostats,
burglar alarms, sprinklers, and even water softeners.
At work they are found in laboratory instruments,
copiers, elevators, hospital equipment, and telephones.
In addition, a lot of microcomputer equipment contains more than one microcontroller. Applications
using multiple microcontrollers as well, as the office.
and home, are now faced with the same requirements
that laboratory instruments were faced with 12 year~
ago - they need to connect them together and have
them .communicate. This need was satisfied in the
laboratory with the IEEE-488 General Purpose
Instrumentation Bus (GPIB). However, GPIB does
not meet the current design objectives for-networking microcontrollers.

What will the end user pay for the added value provided by communications? The cost of the communications hardware is not the only additional cost.
There will be performance degradation in the main
application because the mjcrocontroller now has
additional tasks to perform. There are two extremes
to the cost of adding communication capability. One
could spend very little by adding an I/O port and have
the CPU handle everything from the baud rate to the
protocol. Of course the main application would be
idle while the CPU was communicating. The other extreme would be to add another microcontroller to
the system dedicated to communications. This
communications processor could interface to the main
CPU through a high speed parallel link or dual port
RAM. This 'approach would maintain system performance, but it would be costly.

Today there are many communications schemes and
protocols available; some of the popular ones are
GPIB, Async, HOLC/SOLC, and Ethernet. Common
design objectives of today's networks are: low cost,
reliable, efficient throughput, and expandable. In
examining available solutions, GPIB does not meet
these design objectives; first, the cable is too expensive (parallel communications), second, it can only be
used over a limited distance (20 meters), and third,
it can only handle a limited number of stations. For
general networking, serial communications is
preferable because of lower cable costs and higher
reliability (fewer connections). While Ethernet provides ,very high performance, it is more of a system
backbone rather than a microcontroller interconnect. Async, on the other hand, is inexpensive but it is not
art efficient protocol for data block or file transfers.
Even with some new modifications such as a 9 bit protocol for addressing, important functions such as

Adding HDLC/SDLC Networking Capability

21-2

Figure 1 shows a microcomputer system with a conventional HDLC/ SDLe communications solution.
The additional hardware needed to realize the conventional design is:.an HDLCf sDLe communication
chip, additional ROM for the communication software,
part of an interrupt controller, a bilUd rate generator, a
phase locked loop, NRZI encoded/decoder, and a
cable driver locked loop are used when the transmitter
does not send the clock on a s.eparate line from the data
(i.e. over telephone lines, or two wire cable). the NRZI
encoder/'decoder is used in HDLC/ SDLe to combine
the clock into the data line. A phase locked loop is used
to recover the clock from the data line.
The majority of the available communication chips
provide a limited number oJ data link control functions. Most of them will handle Zero Bit Insertion/Deletion (ZBIID), Flags, Aborts, Automatic

AR-307

MICROCONTROLLER

.
SERIAL
COMMUNICATIONS
SDLC/HDLC

BAUD
RATE
GENERATOR

Figure 1. Conventionalmicrocontroller networking solution
address recognition, and CRC generation and checking. It is the CPU's responsibility fo manage
link access, command recognition and response,
acknowledgements and error recovery. Handling these
tasks can take a lot of CPU time. In addition, servicing the transmission and reception of data bytes can
also be very time consuming depending on the method
used.

require 1 LSI chip and about 10 TTL chips. The cost
of CPU throughput degradation can be even greater.
The percentage of time the CPU has to spend servicing the communication tasks can be anywhere from
10-100070, depending on the serial bit rate. These high
costs will prevent consumer acceptance of networking microcomputer equipment.
A Highly Integrated, High Performance Solution
The 8044 reduces the cost of networking microcontrollers without compromising performance. It
contains all of the hardware components necessary to
implement a microcomputer system with communications capability, plus it reduces the CPU and software
overhead of implementing HOLC/SOLC. Figure 2
shows a functional block diagram of the 8044.

U sing a D MA controller can increase the overall system

performance, since it can transfer a block of data in
fewer clock cycles than a CPU. In addition, the CPU
and the DMA cOhtroller can multiplex their access to
the bus so that both can be running at virtually the same
time. However, both the DMA controller and the CPU
are sharing the same bus, therefore, neither one get to
utlize 100%' of the bus bandwidth. Microcontrollers
available today do not support DMA, therefore, they
would have to use interrupts, since polling is
unacceptable in a multitasking environment.

The 8044 integrates the powerful 8051 microcontroller
with an intelligent Serial Interface Unit to provide a
single chip solution which efficiently implements a
distributed processing or distributed control systefiJ..
The microcontroller is a self sufficient unit containing ROM, RAM, ALU and its own peripherals. The
8044's architecture and instruction set are identical to
the 8051's. The Serial Interface Unit (SIU) uses
bit synchronous HOLC/SOLC protocol and can communicate at bit rates up to 2.4 Mbps, externally
clocked, or up to 375 Kbps using the on-chip digital
phase locked loop. The SIU contains its own processor, which operates concurrently with the microcontroller.

In an interrupt driven, the CPU has overhead in addition to servicing the interrupt. During each inter~
rupt request the CPU has to save all of the important
registers, transfer a byte, update pointers and
counters, then restore all of its registers. At low bit
rates this overhead may be insignificant. However, the
percentage of overhead increases linearly with the bit
rate. At high bit rates this overhead would consume
all of the CPU's time. There is another nuisance factor associated with interrupt driven systems, interrupt
latency.> Too much interrupt latency will cause data
to be lost from underrun and overt:un errors.

The CPU and the SIU, in the 8044, interface through
192 bytes of'dual port RAM. There is no hardware
arbitration in the dual port RAM. Both processor's
memory access cycles are interlaced; each processor
has access every 'other clock cycle. Therefore, there

The additional hardware necessary to implement the
coinmunications solution, as shown in Figure I, wQuld
21-3

inter

AA-307

SIU

8051
MICAOCONTROLLER

HDLC/SDLC
COMMUNICATIONS
PROCESSOR

L ______________ _

Figure 2. 8044 single chip microcontroller networking solution

is no throughput loss in either processor as a result
of the dual port RAM, and execution times are deterministic. Since this has always been the method for
memory access on the 8051 microcontroller, 8051 programs have the same execution time in the 8044.

transmitted or received. Also, the nuisance of overrun and underrun errors is totally eliminated since the
dedicated DMA controller is guaranteed to meet the
maximum data rates. Having a dedicated DMA controller means that the ,serial channel interrupt can be
the lowest priority, thus allowing the CPU to have
higher priority real time interrupts.

By integrating all of the communication hardware
onto the 8051 microcontroller, the hardware cost of
the system is reduced. Now several chips have been
integrated into a single chip. This' means that the
system power is reduced, P.C. board space is reduced, inventory and assembly is reduced, and
reliability is improved. The improvement in reliability is a resuit of fewer chips and interconnections
o~the P.C. board.

Figure 3 shows a comparison between the conventional
and the 8044 solution on the percentage of time the
CPU must spend sending data. This diagram was
derived by assuming a 64 byte information frame is ..
being transmitted repeatedly. The conventional solution is interrupt driven, and each interrupt service
routine is assumed to take about IS instructions with
a I Ilsec instruction cycle time. At 533 Kbps, an interrupt would occur every 15 usee. Thus, the CPU
becomes completely dedicated to servicing the serial
communications. The conventional design could not
support bit rates higher than this because of underruns and overruns. For the 8044 to repeatedly send
64 byte frames, it simply has to reinitialize the DMA
controller. As a result, the 8044 can support bit rates
up to 2.4 Mbps.

As mentioned before, there can be two extremes in
a design which adds communications to the microcomputer system. The 8044 solution uses the high end extreme. The SIU on the 8044 contains its own processor
which communicates with the 8051 processor through
dual port RAM and control/status registers. While
the SIU is not a totally independent communications
processor, it substantially offloads the 8051 processor
from the communication tasks.

Some of the other communications tasks the CPU has
to perform, such as link access, commahd recognition/response, and acknowledgements, are performed automatically by the SIU in a mode called
"AUTO." The combination of the dedicated DMA
controller and the AUTO mode, substantially offload

Tbe DMA on the 8044 is dedicated to the SIU. it cannot access external RAM. By having a DMA controller
in the SIU, the 8051 CPU is offloaded. As a result
of the dual port RAM design. the DMA does not share
the running at full speed while the frames are being
,
21-4

inter

AR-307

• CONCURRENT PROCESSING
CONVENTIONAL
SOLUTION

100
90

80
70
PERCENTAGE OF
CPU TIME SPENT
SERVICING SOLC

60
50
40

30
20

8044
SOLUTION

1~~__~======================~
250 K
500 K
750 K
1M
BIT RATE (BITS/SECOf:.lO)

Figure 3. SIU offloads CPU
the CPU, thus allowing it ·to devote more of its power
.
to other tasks.

can directly set a bit Which communicates to the
primary what its transmit and receive bilfferJng status
is.

8044'8 Auto Mode
In the AUTO mode·the SIU implements in hardware
a subset of the SOLC protocol such that it responds
to many SOLC commands without CPU intervention.
All AUTO mode responses to the, primary station conform to IBM's SOLC definition. hi the AUTO mode
the 8044 can only be a secondary station operating
·in SOLC specified "Normal Response Mode."
Normal Response Mode means that the secondary
station' can not transmit unless it is polled by the
primary station. The SIU in the AUTO mode can
'recognize and respond to the following SOLC commands without CPU intervention: I ,(Information), RR
(Receive Ready), RNR (Receive Not Ready), REJ (Reject), and for loop mode UP (Unnumbered Poll). The
SIU can generate the' following responses without
;CPU intervention: I, RR, and RNR: In addition, the
SIU manages Ns and Nr in the control field. If it
'detects an error in either Ns or.Nr,it interrupts the
CPU for error recovery.

When the CPU wants to send a frame, it loads the
transmit buffer with the (iiata,.. loads the starting
. address and tile count of the data into the SIU, then
sets TBF to transmit the frame. The SIU waits for the
primary station to poll it with a RR command. After
the SIU is polled; it automatically sends the information frame to the primary with the proper control field.
The SIU then waits for a positive acknowledgement
from the primary before incremeJ)ting the Ns field and
interrupting the CPU for more data. If a negative
acknowledgement is received, the SIU automatically
retransmits the frame.
When the 8044 is ready to receive information, the
CPU loads the receive buffer starting address and the
buffer lengthinto-the SIU, then enables the receiver.
When a valid information frame with the correct
address and CRe isreceive4, ,the SIU will increment
the Nr field, disable the receiver and interrupt the CPU
indicating that a good I fFame has been received. The
CPU then sets RBP, reenables the receiver and processes the received data. By enabling the receiver with
RBP set, the SIU will automatically respond to polls
with a. Receive Not Ready, thus keeping the link
moving rather than timing out the primary from a
disabled receiver, or interrupting. the CPU with
another poll before it has processed the data. After'
the data has been processed, the CPU clears RBP,
returning to . the Receive Ready respol.l$es:

How does the SIU know what responses to send to
:the primary? It uses two status bits which are set by
, the CPU. The two bits are TBF (Transmit Buffer Full)
.and RBP (Receive Buffer Protect). TBF indicates that
the CPU wants to send data, and Rap indicates that
the receive data buffer is full. Table I shows the
responses the SIU will send based on these two status
bits. This is an innovative approach to communication design, The CPU in the 8044 with one instruction

21-5

AR-307

Table

SIU's automatic responses il') auto mode

RESPONSE

STATUS BITS
,

TBF

RBP

(RR) Receive ready

(RNR) Receive hot ready

,(I) Infol"mation

(I) Information
In the Information Transfer State there are three common events which occur as illustrated in Figure 4, they
are: 1) the primary polls the secondary and the secondary is ready to receive but has nothing to send, 2)
the primary sends the secondary information, and 3)
the secondary sends, information to the primary.
Figures 5, 6, and 7 compare the functions the conventional design and the 8044 must execute in order
, to !"espond to the primary for the cases in Figure 4.

SDLC communications can be broken up into four
states: Logi<;al DiscclDlI,ect State, Initialization State,
Frame Reject State, and Information Transfer State.
Data can only be transferred in the Information
,Transfer State. More than90OJo of the time,a station
will be in the Information Transfer State, which is
where the SIU can run autonomously. In the other
states, where error recovery, online! offline, and initialization takes place, the CPU manages the protocoL",

PRIMARY'

ISECONDARY I

SECONDARY

Case .1. Primary, polls secondary
secondary has nothing to send
Response

Command
RR

RR
Case 2. Primary polls secondary
secondary sends information frame
'CqrnmandResponse,

RR,NR

fnformation frame

RR, NR+1
Case 3.' Primary' sends secondary information frame
Command
"

" ,

Response
\

RR
RR, NR,'
'In'ormation frame
"

, I

, ,Note: RR =, Receive ready

'RR

NR+1, "

Figure ,4. SOlC commands and responses in the information transfer state
21 r6

AR·307

8044
AUTO MODE'

CONVENTIONAL
DESIGN

PRIMARY
-RRPoll

Receive Interrupts
Decode received control field
Check NR field
Load response into transmit control field
Send frame
Transmit interrupts

Figure 5. Primary polls secondary, secondary has nothing to send

CASE 2
8044
AUTO MODE
Load transmit buffer
,Set TBF bit

PRIMARY

-_It---

RR - _
..poll

""'...
,...._- RR - _...
_
poll

Transmit Interrupt

CONVENTIONAL
DESIGN
Load transmit buffer and transmit
control byte
Receive Interrupts
Decode receive control byte
Check NR field
Send frame
Transmit Interrupts
Receive interrupts
Decode receive control byte .
Check NR field
IncrementNS

Flgure.6. Primary polls secondary, secondary sends I.nformatlon frame

21-7

AR-3Q7

.CASE
8044
AUTO MODE

CONVENTIONAL
DESIGN

PRIMARY
- R R ____
poll

Receive Interrupts
Decode received control field
Check NR field
Load response into transmit control
field
Send frame
Transmit interrupts
Receive interrupts
Decode receive control field
Check NS NR fields
Increment NR
Load response into transmit control
field
Send frame
Transmit interrupts

Receive interrupt

-4--1 frame ___

Figure 7. Primary sends information frame to secondary
Using case I as an example, the conventional design
first gets receive interrupts bringing the data from the
SOLC comm chip into memory. The CPU must then
decode the command in the control field and determine the response. In addition, it must check the Nr
field for any pending acknowledgements. The CPU
loads the transmit buffer with the appropriate address
and control field, then transmits the frame. When the
8044 receives this frame in AUTO mode, the CPU
never gets an interrupt because the SIU handles the
entire frame reception and response automatically.

most critical parameter for calculating throughput on
any high speed network is the station turnaround time;
the time it takes a station to respond a~ter receiving,
a frame. Since the 8044 handles all of the commands
and responses of the Information Transfer State in
,hardware, the turnaround time is much faster than
handling it in software, hence a higher throughput.
8044's Flexible Mode
In the "NON-AUTO" mode or Flexible mode, the
SIU does not recognize or reswnd to any commands,
nor does it manage acknowledgements, which means
the CPU must handle link access, command recognition/response, acknowledgements and error recovery
by itself. The Flexible mode allows the 8044 to have
extended address fields and extended control fields,
thus providing HOLC support. In the Flexible mode
the 8044 can operate as a primary station, since it can
transmit without being polled.

In SOLC networks, when' there is no information
'transfers, case I is the activity on the line. Typically
this is 80070 of the network traffic. The CPU in the
conventional design would constantly be getting interrupts and servicing the communications tasks; even
when it has nothing to send or q:ceive. On the other
hand, the 8044 CPU would only get involved in communicating when it has data to send pr receive.

Front End Communications Processor
'The ·8044 can also be used· as an intelligent
HOLC/SOLC front end for a microporcessor, capable
of extensively off-loading link control functions for

Having tbe SIU implement a subsef of the SOLC protocol in hardware· not only offloads the CPU, but it
also improves the throughput on the network. The
21-8

AR·307

computer. Sophisticated secondary stations could also
take advantage of this design.

the microporcessor. In some applications the 8044 can
even be used for communications preprocessing, in
addition to data link control. For this type of design
the S044 would communicate to the Host CPU
through a FIFO, or dual port RAM. A block diagram
of this design is given in Figure S. A tightly coupled
interface between the 8044 and the Host CPU would
be established. the Host CPU would give the S044
high level commands and data which the 8044 would
convert to HDLC/SDLC. This,particular type of
design would be most appropriate for a primary
Station which is normally a micro, mini, or mainframe

Since the 8044 has ROM on chip, all the communications software is non-volatile. The 8044 primary
station could down-line-load software to 8044 secondary stations. Once down-line-loading is implemented,
software updates to the primary and secondary
stations could be done very inexpensively. The only
things which would remain fixed in IWM are the
HDLC/SDLC communications' software and the software interface to'the HOST.

SYSTEM

HOST

M~MORY

SYSTEM DATA BUS

INTERFACE
HARDWARE

8044 DATA BUS

8044
EXPANSION
MEMORY
HDLC/SDLC DATA LINK

Figure 8. 8044 front ehd processor

21-9

Design Considerations

Designing Microcontroller
Systems for Electrically
Noisy Environments

Contents
SYMPTOMS OF NOISE PROBLEMS. . . . ..

22-2

TYPES AND SOURCES OF ELECTRICAL NOISE
Supply Line Transients . . . . . . . . . . . .. 22-2
EMP and RFI. . . . . .. . . . . . . . . . . .. 22-2
ESD . . . . . . . . . . . . . . . . . . . . . .' .. 22-3
Ground Noise. . . . . . . . . . . . . . . . . . . ,22-3
"RADIATED" AND "CONDUCTED" NOISE..

22-3

SIMULATING THE ENVIRONMENT. . . . . ..

22-4

TYPES OF FAILURES AND FAILURE
MECHANISMS . . . . . . . . . . . . . . . . ..

22-4

THE GAME PLAN . . . . . . . . . . . . . . . ..

22-5

CURRENT LOOPS. . . . . . . . . . . . . . . "

22-5

SHIELDING . . . . . . . . . . . . . . . . .
Shielding Against Capacitive Coupling
Shielding Against Inductive Coupling .
RF Shielding . . . . . . . . . . . . . . .

.'.
..
..
..

22-6
22-6
22-6
22-9

GROUNDS. . . . . . . . . . . .'. . . . . . . . . .
Safety Ground . . . . . . . . . . . . . . . . . . .
Signal Ground . . . . . . . . . . . . . . . . . . .
Practical Grounding . . . . . . . . . . . . . . . .
Braided Cable. . . . . . . . . . . . . . . . . . .

22-10
22-10
22-11

.
.
.
.

22~12

22-13

POWER SUPPLY DISTRIBUTION AND
DECOUPLING. . . . . . . . . . . . . . . . . . . . 22-14
Selecting the Value of the Decoupling Cap .. 22-15
The Case for On-Board Voltage Regulation . 22-16
RECOVERING GRACEFULLY FROM A SOFTWARE
UPSET . . . . . . . . . . . . . . . . . . . . . . . . 22-16
SPECIAL PROBLEM AREAS. . . . . . . . . . . 22-18
ESD . . . . . . . . . . . . . . . . '. . . . . . . . . 22-18
Tne Automotive Environment . . . . . . . . . . 22-19
PARTING THOUGHTS. . . . . . . . . . . . . . . 22-21
REFERENCES. . . . . . . . . . . . . . . . . . . . 22-22

22-1

Types and Sources:of Electrical Noise

Digital circuits are often thought of as being immune to
noise problems, but really they're not. Noises in digita:l
systems produce software .. upsets: program jumps to
apparently random locations in memory. Noise-induced
glitches in the signal lines can cause such problems, but
the supply voltage is more sensitive to glitches than the
signal lines.

The name given to electrical noises other thail those that
are inherent in the circuit components (such as thermal
noise) is EMI: electromagnetic interference. Motors,
power switches, fluorescent lights, electrostatic discparges,
etc., are sources of EM!. There is a veritable alphabet
soup of EMI types, and these are briefly described below.

Severe noise conditions, those involving electrostatic discharges, or as found in automotive environments, can do
permanent damage to the hardware. Electrostatic discharges can blow a crater in the silicon. In the automotive environment, in ordinary operation, the "12V" power
line can show + and -400V transients.

SUPPLY LINE TRANSIENTS
Anything that switches heavy current loads onto or off of
AC or DC power lines will cause large transients in these
power lines. Switching an electric typewriter on or off, for
example, can put a IOOOV spike onto the AC power lines.

This Application Note describes some electrical noises.
and noise environments. Design considerations, along the
lines of PCB layout, power supply distribution and
decoupling, and shielding and grounding techniques,. that
may help minimize noise susceptibility are reviewed. Special attention is given to the automotive and ESD
environments.

The basic mechanism behind supply line transients is
shown in Figure I. The battery represents any power
source, AC or DC. The coils represent the line inductance
between the power source and the switchable loads R I
and R2. If both loads are drawing current, the line current flowing through the line inductance establishes a
magnetic field of some value. Then, when one of the
loads is switched off, the field due to that component of
the line current collapses, generating transient voltages,
v =L( di/ dt), which try to maintain the current at its original level. That's called an "inductive kick." Because of
contact bounce, transients are generated whether the
switch is being opened or closed, but they're worse when
the switch is being opened.

Symptoms of Noise Problems
Noise problems are not usually encountered during the
development phase of a microcontroller system. This is
because benches rarely simulate the system's intended
environment. Noise problems tend not to show up until
the system is installed and operating in its intended environment. Then, after a few minutes or hours of normal
operation the system finds itself someplace out in left
field. Inputs are ignored and outputs are gibberish. The
system may respond to a reset, or it may have to. be
turned off physically and then back on again, at which
point it commences operating as though nothing had
happened. There may be an obvious cause, such as an
electrostatic discharge from somebody's fingc;r to a key"
board or the upset occurs every time a copier machine is
turned on or off. Or there may be no obvious cause, and
nothing the operator can do will make the upset repeat
itself. But a few minutes, or a few hours, or a few days
later it happens again.

An inductive kick of one. type or another is involved in
most line transients, including those found in the automotive environment. Other mechanisms for line transients
exist, involving noi~e pickup on the lines. The noise voltages are then conducted to a susceptible circuit right
along with the power.
EMPANDRFI
Anything that produces arcs ?r sparks will radiate electromagnetic pulses (EMP) or radio-frequency interference
(RFI).

One symptom of electrical noise problems is randomness,
both in the occurrence of the problem and in what the .
system does in its failure. All operational upsets that
occur at seemingly random intervals are not necessarily
caused by noise in the system. Marginal VCC, inadequate
decoupling, rarely encountered software conditions, or
timing coincidences can produce upsets that seem to
occur randomly. On the other hand, some noise sources
can produce upsets downright periodically. Nevertheless,
the more difficult it is to characterize an upset as to cause
and effect, the more likely it is to be a noise problem.

v Rl

Figure 1. Supply Line Transients
AFN-02131A

22-2

Spark discharges have probably caused more software
upsets in digill\l equipment than any other single noise
source. ,The upsetting mechanism is the EMP produc\:d
by the spark. The EMP induces transients in the circuit,
which are what actually cause the upset.
Arcs and sparks occur in automotive ignition systems,
electric motors, switches,' static discharges, etc. Electric
motors that have commutator bars produce an arc as the
brushes pass from one bar to the next. DC motors and
the "universal H(AC! DC) motors that are used to power
hand tools are the kinds that have commutator bars. In
switches, ttie same inductive kick that puts transients on
the supply lines will cause an opening or closing 'switch to
throw a' spark.
'

"Radiated" and "Conducted" Noise
Radiated noise is neise that arrives at the victim circuit in
the form of electromagnetic radiation, such as EMP and
RFI. It causes trouble by inducing' extraneous voltages in
the circuit. Conducted noise is neise that arrives at the
victim circuit already in the form,of an extraneous veltage, typically via the AC or DC power lines.
One defends against radiated noise by care in designing
layouts and the use of effective shielding techniques. One
defends against conducted noise with filters and suppres-

ESD

Electrostatic discharge (ESD) is the spark tliat occurs
when a person picks up a static charge .from walking
across a carpet, and then discharges it into a keyboard, ~r
whatever else can be touched. Waiking across a carpet in
a dry climate, a person can accumulate a static voltage of
35kV. The current pulse from an electrostatic discharge
has an extremely fast riseti~e - typically, 4A/ nsec. figure 2 shows ESD 'waveforms that have been observed' by
some investigators of ESD phenomena.
It is enlightening to calculate the L( dij dt) voltage required
to drive an ,ESD current pulse through a couple of inches'
of straight wire. Two inches of straight wire has about
50nH of inductance. That's not very, mueh, but using
50nH for Land 4A/ nsec for di/ dt gives an L( di/ dt) drop
of about 200V. Recent observations by W.M: King sug·
gest even faster risetimes (Figure 2B) and the occurrence
of mUltiple discharges during a single discharge event.

- - EXPERIMENTAL
-',- -- CALCULATED,

~
~,

z
;: 40

~
o

40 50 60 70 80
TIME IN NANOSECONDS

100

110 120

tAl

Obviously, ESD-sensitiyity needs t.o be considered in the
design of equipment that is going to be subjected to it,
'
such as office equipment.
GROUND NOISE

Currents in ground lines are another' source of noise.
These can be 60Hz currents from the power lines, or RF
hash, or crosstalk from other signals that are sharing this
particular wire as a signal return line. Noise in the ground
lines is often referred to as a "ground 100pH preblem. The
basic concept .of the ground loep is shewn in Figure 3.
The preblem is'that true earth-ground is not really at the
, same petential in all locatiens. If the twe ends of a wire
are earth-grounded at different locations, the voltage difference between the two "ground Hpoints can drive significant currents (several amperes) through the wire. Consider the wire to be part of a loop which contains, in
i1ddition to the wire, a voltage source that represents the
difference in petential between the two ground 'points,
and you have the classical "ground loop. ~', By extension,
the term is used to refer to any unWanted (and often
unexpected) currents in a ground line.

Vert: 5 Amps/Diy
Time: 5 "Sec/OJ.

Displayed:
Ip: 40 Amps

Tr.l "Sec

SooV

(8)

Figure 2.

Waveforms of Electrostatic Discharge
Currents From a Hand-Held
MetalliC Object
AFN-02131A

sors, although layouts ,ana' g~ounding' techniques"are
important here, too.

the p'rogram to some random location in memory. The
p~rson Who has to, iron Qui' such problems is tempted to
say 'the program counter went crazy. There is usually no
da'mage to 'the hardware, arid normal operation can
resume as soon as the EM I has passed or the source is
de-activated. Resuming normal operation usually requires
manual or automatic reset, ,and possibly re-entering of
lo~t information. '

Simulating the Environment
Addressing noise problems after the design ofa system
has been completed is an expensive proposition., The ill
will generated by failures in the field is not cheap either.
It's cheaper in the long run to invest a little time and
money in learning about noise and noise, simulation
equipment, so that controlled tests can be made on the
bench as the design is developing.

Electrostatic discharge~ fro~ operating personnel can
cause not only software upsets, but also permanent
("hard') damage, to the system. For this to happen the
system d,oesn't even have to be in operation. Sometimes
the permanent damage is latent, meaning the initial damage may be marginal and require further aggravation
through operating stress and time before permanent failure takes place. Sometimes too the damage is hidden.

Simulating the intended noise environment is a two-step
process: First you have to recognize what the noise environment is, that is, you have to know what kinds of electrical noises are present, and which of them are going to
cause trouble. Don't ignore this first step, because it's
important. If you invest in an induction coil spark: gener-'
ator just because your application is automotive, you1l be
straining at the gnat and swallowing the camel. Spark
plug noise IS the least of your worries in that
environrrient.

One ESD-related failure mechanism that has been identified hItS to do with the bias voltage on the substrate of
the chip. On some CPU chips the substrate' is held at
-2.5V by a phase-shift oscillator working into a capaCi~
tori diode clamping circuit. This is called a "charge pump"
in chip-design circles. If the substrate wanders too far in
either direction, program read errory are noted. Some
designs have been known to allow electrostatic discharge
currents to flow directly into port' pins of an 8048. The
resulting damage to· the oxide causes an increase in leakage current, which' loads down the charge pump, red ucing
the substrate voltage to a margirtal or unacceptable level.
The system is then unreliable or completely inoperative
until the CPU chip' is replaced. But if the CPU chip was
subjected to a discharge spark once, it will eventually
happen again,

The second step is to generate the electrical noise in a'
controlled manner. This is usually more difficult than first
imagined; one first imagines the simulation in terms of a
waveform generator and a few spare parts, and then finds
that a wideband power amplifier with a 200V dynamic
range is alsp required. A good source,of information on
who supplies what, noise-simulating equipment is the 1981
"ITEM" Directory and Design Guide (reference 6).

Types of Failures and Failure Mechanisms

Chips that have a grounded substrate, such as the 8748,
can sometimes sustain some oxide damage without actually becoming inoperative. In this case the damage is
present, and the increased leakage current is noted; however, since the substrate voltage retains its deSign value,
the damage is largely hidden.
'

A major problem that EMI can cause in digital systems is
intermittent operational malfunction. These software
upsets occur when the system isjn operation at the time
an EMI 'ilb~ is 'activated, and ate ,\lSually characterized
by alQS~p( ,ipformation' or ,ajl1mp i~the execution of
":"

','

EARTH-GROUND
ATB

-----\.::"'.L
"GROUND LOOP"

,Figure 3.

'POTENTIAL DIFFERENCE'
BETWEEN A AND B

What a Ground Loop Is
'J:\.FN-02131A

22-4

It must therefore be recognized that connecting port pins

unprotected to a keyboard or to anything else that is subject to electrostatic discharges, makes an extremely dangerous configuration. It doesn't make any difference what
epu chip is being used, or who makes it. If it connects
unprotected to a keyboard, it will eventually be destroyed.
Designing for an ESD-environment will be discussed
further on.
We might note here that MOS chips are not the only
components that are susceptible to permanent ESD damage. Bipolar and linear ohips can also be damaged in this
way. PN junctions are subject to a hard failure mechanism called thermal secondary breakdown, in which a
current spike, such as from an electrostatic discharge,
Causes microscopically localized spots in the junction to
approach melt temperatures. Low power TTL chips are
subject to this type of damage, as are op-amps. Op-amps,
in addition, often carry on-chip MOS capacitors which
are directly across an external pin combination, and these
are susceptible to dielectric brea\ = LI. Holding the feed and return wires close
together so as to promote field cancellation can be described either as minimizing the loop area or as minimizing L. It's the same thing.

trostatically shielded transformer. Here, a conducting foil
is laid between the primary and secondary coils so as to
intercept the capacitive coupling between them. If a· system is being upset by AC line transients, this type of
transformer may provide the fix. To be effective in this
application, the shield must be connected to the 'greenwire ground.
.

Shielding

SHIELDING AGAINST INDUCTIVE COUPLING
With inductive coupling, the physical mechanism involved
is a magnetic flux density B from some external interference source that. links with a current loop in the victim
circuit, and generates a voltage in the . loop in accordance
with Lenz's law: v = -NA(dB/dt}, where in this case N =
I and A is the area of the current loop in the victim
circuit.

There are three basic kinds of shields: shielding against
capacitive coupling, shielding against inductive coupling,
and RF shielding. Capacitive coupling is electric field
coupling, so shielding against it amounts to shielding
against electric fields: As will be seen, this is relatively
easy. Inductive coupling is magnetic field coupling, so
shielding against it is shielding against magnetic fields.
This is a little more difficult. Strangely enough, this type
of shielding does not in general involve the use of magnetic materials. RF shielding, the classical "metallic barrier against all sorts of electromagnetic fields, is what
most people picture when they think about shielding. Its
effectiveness depends partly on the selection of the shielding materi~l, but mostly, as it turns out, on the treatment
of its seams and the geometry of its openings.

There are two aspects to defending a circuit against
inductive pickup. One aspect is to try to mjnimize the
offensive fields at their source. This is done by minimizing
the area of the current loop at the source so as to promote field cancellation, as described in the section on current loops. The other' aspe~t is to minimize the inductive
pickUp in. the victim circuit by minimizing the area of that
current loop, since, from Lenz's law, the induced voltage
is proportional to this area. So the two aspects really
involve the same corrective action: minimize the areas of
the current loops. In other words, niinimizing the offensiveness of a circuit inherently minimizes its susceptibility.

SHIELDING AGAINST CAPACITIVE COUPLING
Capacitive coupling involves the passage of interfering
signals through mutual or stray capacitances that aren't
shown on the circuit diagram, but which the experienced
engineer knows are there. Capacitive coupling to one's
body is what would cause an unstable oscillator to
change its frequency when the person reaches his hand
over the circuit, for example. More importantly, in a digital system it causes crosstalk in multi-wire cables.

C.
NOISE
SOURCE

The way to block ~pacitive coupling is to enclose the
circuit or conductor you want to protect in a metal
shield. That's called an electrostatic or Faraday shield. If
coverage is 100%, the shield does not have to be
grounded, but it usually is, to ensure that circuit-to-shield
capacitances go to signal reference ground rather than act
as feedback and crosstalk elements. Besides, from a
mechanical point of view, grounding it is almost
inevitable.

--~-II---

VICTIM
CKT

(A) Capacitive Coupling

/FARADAY SHIELD

NOISE
SOURCE

A grounded Faraday shield can be used to break capacitive coupling between a noisy circuit and a victim circuit,
as shown in Figure 4. Figure 4A shows two circuits
capacitively coupled through the stray capacitance between them. In Figure 4B the stray capacitance is intercepted by a grounded Faraday shield, so that interference
currents are shunted to ground. For example, a grounded
plane can be inserted between PCBs (printed circuit
boards) to eliminate most of .the capacitive coupling
between them.

-11-- --11-

VICTIM
CKT

J
~

(B) Electrostatic Shielding

Another application of the Faraday shield is in the e1ec-

Figure 4. Use of Faraday Shield

22-6

V.
I

r------:.=.:.--------I

-I

- - - ." ""CURRENT LOOP

Figure 5. External to the Shield, cf>=O
(A)

,Shielding against inductive coupling means nothing more
nor less than c~ntrolling the dimensions of the current
loops in the circuit We must look at four examples of
this type of ushielding": the coaxial cable, the twisted pair,
the ground plane, and the gridded-ground PCB layout

The Coaxial Cable - Figure 5 shows a coaxial cable
carrying a current I from a signal source to a receiving
load, The shield carries the same current as the center
conductor. Outside the shield, the magnetic field produced by +1 flowing in the center conductor is cancelled
by the field produced by -I flowing in the shield. To the
extent that the cable is ideal in producing zero external
magneti<: field, it is immune to inductive pickup from
external sources. The cable adds effectively zero area to
the loop. This is true only if the shield carries the same
current as the center conductor.
In the real world, both the signal source and the receiving
load are likely to have one end connected to a common
signal ground. In that case, should the cable be grounded
at one end, both ends, or neither end? The answer is that
it should be grounded at both ends. Figure 6A shows the
situation when the cable shield is grou\lded at only one
end. In that .case the current loop runs down the center
conductor of the cable, then back through the common
. ground connection. The loop area is not well defined.
The shield not only does not carry the same current as
the center conductor, but it doesn't carry any current at
all. There is no field cancellation at all. The shield has no
effect whatsoever on either the generation of EM! or susceptibility to EM!. (It is, however, still effective as an
electrostatic shield, or at least it would be if the shield
coverage were lOO%.)

Shield Has No Effect

,,;"""' ....

'--

---)
I

\
,----

(8)

':"

,,/'
//
///

"LOW-FREOUENCY
CURRENT PATH

Two Return Paths

Figure 6. Use of Coaxial Cable
inductance is the path of minimum loop area. Hence, for
higher frequencies the shield carries virtually the same
current as the center conductor, and is therefore effective
against both generation and reception of EM!.
Note that we have now introduced the famous "ground
loop" problem, as shown in Figure 7A. Fortunately, a
digital system has some built-in immunity to moderate
ground loop noise. In a noisy environment, however, one
can break the ground loop, and still maintain the shielding effectiveness of the coaxial cable, by inserting an optical coupler, as .shown in Figure 7B. What the optical
coupler does, basically, is allow us to re-define the signal
source as being ungrounded,so that that end of the cable
need not be grounded, and still lets the shield carry the
same current as the center conductor. Obviously, if the
signal source weren't grounded in tht first place, the optical coupler wouldn't be needed.

Figure 68 shows the situation when the cable is grpunded
at both ends. Does the shield carryall of the return current, or only a portion of it on account of the shunting
effect of the common ground connection? The answer to
that question depends on the frequency content of the
signal. In general, the current loop will follow the path of
least impedance. At low frequencies, OHz to several kHz,
where the inductive reactance is insignificant, the current
will follow the path of least resistance. Above a few kHz,
where inductive reactance predominates, the current will
follow the path of least inductance. The path of least

The Twisted Pair - A cbeaper way to minimize loop
area is to run the feed and return wires right next to each
other. This isn~t as effective as a coaxial cable in minimizing Iqop area. An ideal coaxial cable adds zero area to
the loop, whereas merely keeping the feed and return
wires next to each other is bound to add a finite area.
However, two things work to make this cheaper method
almost as good as a coaxial cable. First, real coaxial
cables are not ideal. If the shield current isn't'evenly distributed around the center conductor at every crossAFN-02131A

22-7

POTENTIAL DIFFERENCE
BETWEEN THE TWO
GROUND POINTS

(A) The Ground Loop

(

+5V

OPTICAL COUPLER

r-----~~

~(--'\

~~~:_:_:_:_::_:_:_:_:_:_::_:_:_:_:_::_~_-_-___ J

:
I

R
__ ..... 1

I
I
I

(B) Breaking the Ground Loop

Figure 7. Use of Optical Coupler
ground path impedance is primarily inductive).

section of the cable (it isn't), then field cancellation external to the shield is incomplete. If field cancellation is
incomplete, then the effective area added to the loop by
the cable isn't zero. Second, in the cheaper method the
feed and return wires can be twisted together. This not
only maintains their proximity, but the noise picked up in
one twist tends to cancel out the noise picked up in the
next twist down the line. Thus the "twisted pairn turns
out to be about as good a shield against inductive coupling as coaxial cable is.

Thus, if the feed path for a given signal zigZags its way
across the PCB, the return path for this signal is free to
zigzag right along beneath it on the ground plane, in such
a configuration as to minimize the energy stored in the
magnetic field, produced by this current loop. Minimal
magnetic flux means minimal effective loop area and minimal susceptibility to inductive'coupling.

The Gridded-Ground PCB Layout - The next best
thing to a ground plane is to layout the ground traces on
a PCB in the form of a grid structure, as shown in Figure
8. Laying horizontal traces on one side' of the board and
vertical traces on the other side allows the passage Of signal and power traces. Wherever vertical and horizontal
ground traces cross, they must ,be connected by. a
feed-through.

The twisted pair does not, however,:provide electrostatic
shielding (Le., shielding against capacitive coupling).
Another operational difference between them is that the
coaxial cable works better at higher frequencies. This is
primarily because the twisted pair adds more capacitive
loading to the signal source than the coaxial cable does.
The twisted pair is normally considered useful up to only
about IMHz, as opposed to near a GHz for the coaxial
cable.

Have we not created here a network of "ground loopsn?
Yes, in the literal sense of the word, but loops in the
ground layout on a PCB are not to be feared. Such inoffensive little lOOps' have never caused as much noise pickup as their avoidance has. Trying to avoid innocent little
loops in the ground layout, PCB designers have forced
current loops i~to geometries that. could swallow a whale.
That is exactly the wrong thi,:,g to do.

The Ground Plane - The best way to minimize loop
areas when many current loops are involved is to use a
ground plane. A ground plane is conducting surface
that is to serve as a return conductor for all the current
loops in the circuit. Normally, it would be one or more
layers of a multilayer PCB. All ground points in the circuit go not to a grQunded trace on the PCB, but directly
to the ground .plane. This leaves each current loop in the
circuit freC' to, complete itself in whatever configuration
yields minimum loop area (for frequencies wherein the

The gridded ground structure works almost as w~1l as the
ground plane, as far as minimizing loop area is concerned. For a 'given current loop, the 'primary return path
may have ,to zig once in a while where its' feed path zags,
AFN-02131A

22·8

interference from a whip antenna. A gridded-ground
structure would be less effective.
In the near field of a loop antenna, the E/ H ratio is
lower than 377 ohms, which means it's mainly an H-field
generator. Any current loop is a loop antenna. Interference from a loop antenna would be by magnetic field
coupling, which is basically the same as inductive coupling. Methods to protect a circuit from inductive coupling, such as a gridded-ground structure, woul<;l be effective against RF interference from a loop antenna. A
Faraday shield would be less effective.

~ DIP
t""."",,;;J

0 CAPACITOR,
DECOUPLING

,Figure 8.

GROUND

A more difficult case of RF interference, near field or far
field, may ~equi're a genuine metallic RF shield. The idea'
behind RF shielding is that time-varying EMI fields
induce currents in the shielding material. The induced
currents dissipate energy in two ways: [2R losses iri the
shielding material and radiation losses as they re-radiate
their own EM fields. The energy for both of these mechanisms is drawn from the impinging EMI fields. Hence
the EMI is weakened as it penetrates the shield.

ELECTROLYTIC
CAPACITOR

PCB with Gridded Ground

but you still get a mathematically optimal distribution of
currents in the grid structure, such that the current loop
produces less magnetic flux than if the return path were
restrained to follow any single given ground trace. The
key to attaining minimum loop areas for all the current
loops together is to let the ground currents distribute
themselves around the entire area of the board as freely
as possible. They want to minimize their own magnetic
field. Just let them.

More formally, the [2R losses are referred to as absorption loss, and the re-radiation is called reflection loss. As
it turns out, absorption loss is the primary shielding
mechanism for H-fields, and reflection loss is the primary'
shielding mechanism for E-fields. Reflection loss, being a
surface phenomenon, is pretty much independent of the
thickness of the shielding material. Both loss mechanisms,
however, are dependent on ihe frequency (w) of the
impinging EMI field, and on the permeability (fJ.) and
conductivity (u) of the shielding material. These loss
mechanisms vary approximately as follows:

RF SHIELDING
A time-varying electric field generates a time-varying
magnetic field, and vice versa. Far from the source of a
time-varying EM field, the ratio of the amplitudes of the
electric and magnetic fields is always 377 ohms. Up close
to the source of the fields, however, this ratio can be
quite different, and dependent on the nature of the
source. Where the ratio is near 377 ohms is called the far
field, and where the ratio is significantly different from
377 ohms is called the near field. The ratio itself is called
the wave impedance, E/ H.

reflection loss to an E-field (il) dB) ~ log ~
wfJ.

absorption loss to an H~field (in dB) ~ tv mufJ.
where t is the thickness of the shielding material.
The first expression indicates that E-field shielding is
more effective if the shield material is highly conductive,
and less effective if the shield is ferromagnetic, and that
low-frequency fields are easier to block than highfrequency fields. This is shown in Figure 9.

The near field goes out about 1/6 of a wavelength from
the source. At I M Hz this is about 150 feet, and at
IOMHz it's about 15 feet. That means if an EMI source
is in the same room with the victim circuit, it's likely to
be a near field problem. The reason·this matters is that in
the near field an RF interference problem could be
almost entirely due to E-field coupling or H-field coupling, and that could influence the choice of an RF shield
or whether an RF shield will help at all.

iii"
:!!. 150

" 125
m
0 100
..J

In the near field of a whip antenna, the E/ H ratio is
higher than 377 ohms, which means it's mainly an E-field
generator. A wire-wrap post can be a whip antenna.
Interference from a whip antenna would be by electric
field coupling, which is basically capacitive coupling.
Methods to protect a circuit from capacitive coupling,
such as a Faraday shield, would be effective against RF

50
25

....
LL

0.01

0.1

1.0

100

1000

10,000

FREQUENCY (KILOI:IERTZ)

Figure 9.

E-Field Shielding
AFN-Q2131A

22·9

175
150

1=1

~>25

~200
~

fI)
fI)

----.....

m 150

REFLECTIQN - - - - ; - '

fI)

...

10'

1Q4

105

10'

~~~~"ABSORPTION

O+----,--~~-~-~-~-~-T--~--_,,_--_r--__;
0.01

103

-~-:::--............,'

9 100

...0

PLANE WAVE

10'

0.1

1.0

100

1000

10,000

FREQUENCY (KILOHERTZ)

FREQUENCY (HERTZ)

Figure 10. H·Field Shielding

Figure 11. E- and H-Field Shielding

Copper and aluminum both have the same permeability,
but copper is slightly more conductive, and so provides
slightly greater reflection loss to an E-field., Steel is less
effective for two reasons. First, it has a somewhat elevated permeability due to its iron content, and, second, as
tends to be the case with magnetic materials, it is less
conductive.

allowed to flow freely. If they have to detour around slots
and holes, as shown in Figure 12, the shield loses much
of its effectiveness.

On the other hand, accilrding to the expression for
absorption loss to an H-field, H-field shielding is more
effective at higher frequencies and with shield material
that has both high conductivity and high permeability. In
practice, however, selecting steel for its high permeability
involves some compromise in conductivity. But the
increase in permeabilitr more than makes up for ,the
decrease in conductivity, as can be seen in Figure 10. This
figure also shows the effect of shield thickness.

As can be seen in Figure 12, the severity of the detour
has less to do with the area of the hole than it does with
the geometry of the hole. Comparing Figure 12C with
12.D shows that a long narrow discontinuity such a~ a
seam can cause more RF leakage than a line of holes
with larger total area. A person who is responsible for
designing or selecting rack or chassis enclosures for an
EMI environment needs to be familiar with the techniques that are avajlable for maintaining electrical continuity across seams. Information on these techniques is
available in the references.

A composite of E-field and H-field shielding is shown in
Figure II. However, this type of data is meaningful only
in the far field. In the near field the EMI could be 90%
H-field,. in which case the reflection loss is irrelevant. It
would be advisable then to l;>eef up the absorption loss, at
the expense of reflection loss, by choosing steel. A better
conductor than steel might be less expensive, but quite
ineffective.
,
A different shielding mechanism that can be take,:, advantage, of for low freq\lency magnetic fields is the ability of
a high permeability material such as mumetal to divert
the field by presenting a very low reluctance path to the
magnetic flux. Above a few kHz, however, the permeability of such materials is the same as steel.
In actual fact the selection of a shielding material turns
out to be less important than the presence of seams,
joints and holes in the physiCal structure of the enclosure,
The shielding mechanisms are related' to the induction' of
currents in the shield rnaterial, but the currents must be

Grounds
There are two kinds of grounds: earth-ground and signal
ground. The earth is not an equipotential surface, so
earth ground potential varies. That and its other electrical
properties, are not conducive to its use as a return conductor in a' circuit. However, circuits are often connected
to earth ground for protection against shock hazards. The
other. kind of ground, signal ground, is an arbitrarily
selected reference node in a circuit-the node with respect
to which other node voltages in the circuit are measured.
SAFETY GROUND
The standard 3-wire single-phase AC power distribution
system is represented in Figure 13. The white wire is
earth-grounded at the service entrance. If a load circuit
has a metal enclosure or chassis, and if the black wire
develops a short to the enclosure, there will be a shock
hazard to operating personnel, unless the enclosure itself
is earth-grounded. If the enclosure is earth-grounded, a.
AFN-02131A

22-10

__ INDUCED
SHIELD
CURRENTS

_ RECTANGULAR
SLOT

--SECTION OF
SHIELD

(8)

(A)

(0)

Figure 12. Effect of Shield Discontinuity on Magnetically Induced Shield Current

shor'! results in a blown fuse rather than a "hot" enclosure. The earth-ground connection to the enclosure is
called a safety ground. The advantage of the 3-wire
power system is that it distributes a safety ground along
with the power.
Note that the safety-ground wire carries no current,
except in case of a fault, so that at least for low frequencies it's at earth-ground potential along its entire length.
The white wire, on the other Jland, may be several volts
off ground, due to the IR drop along its length.

/:~~~:CE

..... ----- .....

SLACK

I
I

LOAD
CKT

I
I
I

I
I

I
:
I
I
I
I

WHITE

The series connection is pretty common because it's simple and economical. It's the noisiest of the th~ee, however,
due to common ground impedance coupling between the
circuits. When several circuits share a ground wire, currents from one circuit, flowing through the finite impedance of the common ground line, cause variations in the
ground potential of the other circuits. Given that the currents in a digital system tend to be spiked, and that the
common impedance is mainly inductive reactance, the
variations could be bad enough to cause bit errors in high
current or particularly noisy situations.

METAL
( ENCLOSURE
r--------\

I
I

SIGNAL GROUND
Signal ground is a single point in a circuit that is designated to be the reference nodeJor the circuit. Commonly,
wires that connect to this single point are also referred to
as "signal ground." In some circles "power supply common" or PSC is the preferred terminology for these conductors. In any case, the manner in which these wires
connect to the actual reference point is the basis of distinction . among three kinds of signal-ground wiring
. methods: series, parallel, and mUltipoint. These methods
are shown in Figure 14.

----)

I
I

I~ ___ -

GREEN

The parallel connection eliminates common ground
impedance problems, but uses a lot 'of wire. Other disadvantages are that the impedance of the individual ground
lines can be very high, and the ground lines themselves
can become sources of EM!.

EAR~H-GROUND

Figure 13.

Single-Phase Power Distribution

AFN-02131A

22·11

In the multipoint system, ground impedance is minimized
by using a ground plane with the various circuits connected to it by very short ground leads. This type of connection would be used mainly in RF circuits above
IDMHz.

QUIET
SIGNAL
GROUND

PRACTICAL GROUNDING
A combination of series and, parallel ground-Wiring
methods can be used to trade off economic and the various electrical considerations. The idea is to run series
connections for circuits ~hat have similar noise properties,
and connect them at a single reference point, as in the
parallel method, as shown in Figure 15.

In Figure 15, "noisy signal ground" connects to things
like motors and relays. Hardware ground is the safety
ground connection to chassis, racks, and cabinets. It's a
mistake to use the hardware ground as a return path for
signal currents' because it's fairly noisy (for example, it's
the hardware ground that receives an ESD spark) and
tends to have high resistance due to joints and seams.

NOISY
AND HIGH
CURRENT
SIGNAL
oard voltage regulator chip did the job. ,
Thus, a good case can be made in favor of using a voltage regulator chip on each PCB, instead of doing all the
voltage regulation at the supply circuit. This eases
requirements on the heat-sinking at the supply circuit,
imd alleviates much of the pistribution and board detoupiing headaches. However, it also brings in the possibility
that different boards would be operating at slightly different VCC levels due to tolerance in the regulator chips;
this then learls to slightly different logic levels from board
to board. The implications of that may vary from nothing
to latch-up, depending on what kinds of chips are on the
boards" and how they react to an input "high" that is
perhaps O.4V higher than local VCe.

Recovering Gracefully f,rom a Software
Upset
Even wh~n o~e follows all the best guidelines for designing for a noisy environment, it's always possible for a
noise transient to occur which exceeds the circuit's
immunity level. In that case, one can strive at least for Ii
graceful recovery.
Graceful recovery schemes involve additional hardware
and/ or software which is supposed to return the system
to a normal operating mode after a software upset has
occurred. Two decisions have to be made: How to recognize when an upset has Occurred, and what to do about
it.
If the designer knows what kinds' and combinations of
AFN-02131A

22-16

PIN 40

ALE

(A) No Decoupllng Cap

PIN 40

ALE

(D) 1"fDecoupler Stretched Directly from ~In 40
to Pin 20, under the Socket. (This prevents
the 1MHz ripple, but there's no reduction In
higher frequency components. Further
Increases In capacitance effected no further
Improvement.)

(C) 0.1JJf'Decoupler Stretched Directly from Pin
40 to Pin 20, under the Socket (Tl:le' difference between this and 21B is due only to the
change In loop geometry. Also shown Is the
upward slope of a ripple in Vcc. The ripple
frequency is 1MHz,the same as ALE.)

PIN 40

ALE

(E) Special-Purpose Decoupllng Cap under Development by Rogers Corp. (Further discussion
in tex!.)

Figure 21. Noise on

Vee Line
AFN-02131A

22-17

.,''f'.

:~'
,"1

",t',
,

'."

,",:

:':

SOOmV
"
~.',

tf,

Figure 22.

'.'

..' ~'

EMP·lnduced Glitch

outputs can legally be generated by the system, he can
, use gates to recog'niz~, and flag *,11 ocCuJten~' of an illegal state. of affairs. lhe nag.:can then'tJiggera jump to a
retqVefy' routine 'whi~h then may check, or. re-initialize
data" perhaps, 'output an' error il1essa~;' ;~r generate a
'.'
" ''
,
simple reset: , " ,
,',

",'

J M Ps. It's still possible, of course, to get hung up in a
data· table or something. But you get a lot of,-protection,
for 'tlie c~t,'
'
,
"

FurthetdisCAsslon
graceful, fCC()veI)r schemes can be
found' in refe~ilcei J : ' "
'

-,'"

The' most reliable scheme is to use a s()-'Called watchdog
circuit. Here the CPU ,is pro~mlI!ed to generate a periodic signata, lo~g'as the system is executing instructions
in -~n ,expectcid' inaniier. the periodic si~1 Is then used
to'qold off a circuit 'that will trigger a Jump to. a recovery
rou'tilie: Th~' periodic, 'sigIIIIl needs to be' AC-<:oupled to
the trigger 'Circuit so that a "stUck~~tft fatilt won't continue
to hold otT' the trigger. Then,' if the processor locks up
someplace, the periodic signal is lost and the watchdog
tri~rs a reset. ,
In practice, it may be convenient to drive the watchdog
circuit with a signal which is being generated anyway by
, the system. One needs to be Careful, however, that an
upset does in fact discontinue that signal. Specifically, for
example, one could use one ,of the digit drive signals
going to a multiplexed display. But display scanning is
often handled in response to a timer-interrupt, which may
'continue operating even though the main program is in a
failure mode. Even so, with a little extra software, the
signal can be used to control the watchdog (see reference
8 on this).
Simpler schemes can work well for simpler systems. For
example, if a CPU isn't doing anything but scanning and
decoding a keyboard, there's little to lose and much to
gain by simply resetting it periodically with an astable
multivibrator. It only takes about 13!lsec (at 6M Hz) to
reset an 8048 if the clock oscillator is already running.
A zero-<:ost measure is simply to fill all unused program
memory with NOPs and JMPs to a recovery routine. The
etTectiveness of this method is increased by writing the
program in segments that are separated by NO~s, and,

ESD

M'PS chips hav,eso~ built-in pr~tec~i?n, ~gainst a static
charge ,build-up on t\le pins, as would 'OCCur during normal handling,' but tliere's no protection againSt the kinds
of cur~nt levels and rise times that occur in a genuine
electtostatio spark. These kinds of discharges can blow a
cra,ter in'the silicon.• ,
It must be recognized that connecting CPU pins unprotected to a keyboard or to anything else that is subject to
electrostatic discharges makes an extremely fragile configuration. Buffering them is the very least one can do. But
buffering d~esll 't completely solve the problem,. because
then the.butTer chips",will sustain the !lamage (even TTL);
therefore, one might ,consider mounting. the Duffer chips
in sO£kets for ea~ of I:Cplll:cement, ' '
.

T~nsieni

suppressort. ~uch as ~he Tran,Z9r~@) made by
General'semiconductor Ind.ustries (Tempe, AZ), may in
the lon~ run prQ¥idf the cheapest: protec~on if\heir "zero
inductance"· .structu're is used, The structure and circuit
appli~iqn-:'are shown kt Figure 23.
.
" ' j ,

' . ,

The'~~ppreSsor eleib~nt is ~ fln juncti~n t~t: 9perates like

a Zener diQde. 8ack~tO-back units are available for AC
operation. The element i~ :niQre or less an open circuit at
normal system voltage (the standoff v,oltage rating for the
deXice), and con~~ts ii""~ a'Zent*CJ + J(-F)/(2*PI*(S'2+F~2)CJ
2500 REM
= F~RC(S.F.C) + JFNXC(S.F.C)
2600 REM
2700 DEF F,NRC(SC. FC. CO = SC/(2#*PI*(SC 2+FC2)*CC)
2800 DEF FNXC(SC.FC.CC) = -FC/(2#*PI*(SC'2+FC'2)*CC)
2900 REM
RATIO OF TWO COMPLEX NUMBERS
3000 REM
3100 REM
RA+JXA
RA*RB+XA*XB
XA*RB-RA*XB
3200 REM
+ J
RB"2+XB'2
RB'2+XB"2
3300 REM
RB+JX3
FNRR(RA, XA.RB.IB) + JFNXR(RA. XA.RB.XB)
3400 REM
3500 DEF FNRR(RA,XA,RB.IB) = (RA*RB+XA*XB)/(RB 2+XB 2)
3600 DEF FNXR(RA. XA,RB. XB) = (XA*RB-XB*RAl/(RB 2+XB 2)
3700 REM
PRODUCT OF TWO COMPLEX NUMBERS
3800 REM
3900 REM
RA*RB-XA*XB + J(XA*RB+RA*XB}
FNRM'RA. IA. RS. IB) + JFNXM(RA. XA. RB.·XB).
4000 REM
4100 DEF FNRM(RA. XA.RB. "
PRINT "OTHERWISE, TYPE 0,0 "
INPUT N'l.,X
IF N'l.=O THEN RETvRN
IF N'l.=I' THEN RI
X
IF N'l.=2 THEN L1 = X
IF N'l.=3 THEN Cl
X*lE-12
IF NI.=4 THEN CO
X*lE-12
IF NI.=5 THEN ex
X*lE-12
IF NI.=6 THEN CV
X*IE-12
IF NI.=7 THEN AV# = X
IF NI.=8 THEN RX
X*1000'
IF NY.=9 THEN Ro = x*loao'
GOTO 17400
REM
REM
If

REM **************************************************************
REM
REM
REM
REM
REM
REM
REM
Xl =
RE =
XE =

CIRCUIT ANALYSIS
ThlS

rout~ne

calculate~

Crystal 1npedance

the loop

ga1n at complex frequency SO+JFG

RE + JXE

FNXL(FQ,Ll) + FNXC(SQ,FQ.Cl)
FNRP ( (R ITFNRLCSQ, L1) "FN~C (SQ, FQ, C 1) ), XL FNF>C (SQ, FQ, CO), FNXC (SQ, FQ, CO) )
FNXP«RITFNRL(SQ,Ll)+FNRC(SQ,FQ,CI». XI,FNRC(SQ,FQ,CO),FNXC(SQ,FQ,CO»

REM
(RE+JXE)! 1 (<3mpllf1er feE'dback T'eSlstance)
REM 2
RF T JXF
REM
RF = FNRP(RX,O,RE, XE)
XF = FNXP(RX,O,RE.XE)
REM
Input llnp edance
Zl
RI + JXI
1mpedance of CXTALl
REM 3
REM
RI = FNRC(SQ,FQ,C()
XI = FNXC (SQ, FQ, C.< )
REM
REM 4 Load 1mpedance ZL = llmpedance of CXTAL2): :CCRF+RI>+J(XF+XI)]
REM
RL = FNRP (RF+R I). (XF .... X I), FNRC (SQ, FQ, CY), FNXC (SQ, FO, CY)
(XF .... Xll,FNRC'-SO r-o CY).FNX('(SQ,FQ,CY»
XL = FNXP«PF+RI
REM
REM
REM
REt1
AR* = -AV#*FNRR(RL. XL. (RO+RL), XL)
1

22500
22600
22700
22900
22900
23000
23100 AI# = -AV#-JlFN')(R(RL, XL, (PQ+RL), XL!
23200 REM
23300 REM 6 Feedbatl( ratlo
\beta!
(RJ+pI) !['F!Ftfdl-t,t(XF+XI»)
I

23400 REM

Birt:!dJ'

-r

JI:'(lmaqllldryl

22-51

AP-155

23500 REM
23600 BR# - FNRR(RI.XI. (RI+RF). (XI+XF»
23700 BIll - FNXR(RI. XI. (RI+RF). (XI"F»
23800 REM

23900
24000
24100
24200
24300

REM 7 AmplIfIer gaIn
REM
A - FNZM(AR#.AI#)
AP - FNZP(AR4I. AI41),
REM

1Tl

magnitude/phase form.

25100

25200
25300

25400
25500
25600
25700
25800

25900

26000
26100
26200
26300
26400
26500
26600
26700
26800
26900
27000
27100
27200
27300
27400
27500
27600
27700
27800
27900
28000
28100
28200
28300
28400
28500
28600
28700
28800
28900
29000
29100
29200
29300
29400
29500
29600
29700
29800
29900
30000
30100
30200
30300
30400
30500
30600
30700
30800
30900
31000
31100
31200

A at AP degrees

B at BP degrees
8
(beta) In magnItude/phase form
Bfl+JBI
REM
B = FNZM(BR4I,BI#)
SP - FNZP(BR#,BI#i
REM
REM 9 Loop gaIn G = (BR+JBI)*CAR+JAI)
REM
~ G(real) + JGllmaglnary)
REI1
GR - FNRM(AR#,AI#,BR#.BI#)
GI - FNXM(AR#,AI#,BR#,BI#)
REM
AL at AQ degrees
REM
10
Loop g~ln In magnItude/phase form
GR+JGI
REM
AL - FNZM(GR,GI)
All - FNZP (GR, GIl
RETU'RN
REM
REI1
REM ************~~***********~**~*********************************
!'EM
PRINT CIRCUIT ANALYSIS RESULTS
REM
REM
PRINT
PRINT" FREIlUENCY - ",SIl, " + J",FIl," HZ"
PRINT" XTAL IMPEDANCE - ",FNZM(RE,XE)," OHMS AT ",FNZP(RE, XE)," DEGREES"
(RE - ",CSNG(RE)," OHMS)"
PRINT
PRINT
(KE - ",CSNG(XE)," OHMS)"
LOAD IMPEDANCE - ",FNZM(RL, XL), " OHMS AT ",FNZP(RL,XL)," DEGREES"
PRINT
PRINT
AMPLIFIER GAIN - ",A," AT ",AP," DEGREES"
FEEDBACK RATIO - ",B," AT ",BP," DEGREES"
PRINT
LOOP GAIN - ",AL," AT ",AQ," DEGREES"
PRINT
RETURN
REM
REM
REM **************************************************************
REM
SEARCH FOR FREIlUENCY (S+JF)
REM
AT WHICH LOOP GAIN HAS ZERO PHASE ANGLE
REM
REM
REM ThIS routIne searches for the fre~uency at WhlCh the lmaglnary part
REM of the loop galn lS zero T~e algorlthm lS as follows.
1 Calculate the slgn of the lmaglnary part of the loop galn (GI)
REM
REM
2
Inereme~t the frequency
3
Calculate the 519n of GI at 'the lncremented frequency
REM
4
If the s19n of GJ Has'not changed. go back to 2
REM
S If the 51gn of GJ has changed, and this frequency 15 wlthin
REM
1Hz of the prevlous slgn-change, e~lt the routlne
REM
6 OtherWIse, dlvlde the frequency' lncrement by -10
REM
REM
7 Go bae It to 2
REM The routine 15 entered wlth the startlng frequency SQ+JFQ and
REM 5tartlng lncrement DS+JDF already deflned by the caillng program
REM In actual use either OS or OF lS zero, so the routine searches for
REM a GI=O pOlnt by lncrementlng elther sa or FG whlle holdIng the other
It return~ control to t~e call1ng program with the
REM constant
REM lncremented part of the frequency belng wlthin 1Hz of the actual
REM GI=O pOlnt
REM
REM
CALCULATE THE SIGN OF THE II1AGINARY PART OF THE LOOP GAIN (GI).
REM
GoSUB 20200
GoSUB 26600
IF GI-O THEN RETURN
SXX - INT(SGN(GI»)
IF SXX-+I THEN OS
-OS
REM (REVERSAL OF OS FOR GI: 0 IS F'OR THE POLE-SEARCH ROUTINE. )
REM
INCREMENT THE FREIlUENCY
REM 2
REM
SP = SO

24400 REM

24000
24600
24700
24800
24900
25000

ARtJAI

22-52

AP·155

31300
31400
31500
31600
31700
31800
31900
32000
32100
32200
32300
32400
32500
32600
32700
32800
32900
33000
33100
33200
33300
33400
33500
33600
33700
33800
33900
34000
34100
34200
34300
34400
34500
34600
34700
34800
34900
35000
35100
35200
35300
35400
3-5500
,35600
35700
35800
35900
36000
36100
36200
36300
36400
3~500

36600
36700
36800
36900
37000
37100
37200
37300
37400
37500
37600
37700
37800
37900
38000
38100
38200
38300
38400
38500
38600
38700
38800
38900
39000

FP = FQ
SQ = sa + OS
FQ = FQ + OF
REM
REM 3 CALCL'LATE THE SIGN OF GI AT lHE INCREMENTED FREQUENCY
REM
GOSUe 20200
OOSUB 26600
IF INT(SGN(GI))=O THEN RETURN
REM
REM 4 IF THE SIGN OF GI HAS NOT CrlANGED, GO BACK TO 2
REM
IF SXX+INT(SGN(GI))=O THEN PRINT ELSE 31400
SXX
-SXX
REM
IF THE SIGN OF GI HAS CHANGED, AND IF THIS FREQUENCY IS WITHIN
REM 5
1HZ OF ~'"'IE P~ElJIO",15 S!GN-CHANGE. AND' IF 13! IS NEGATIVE, THEN,
REM
EXIT THEo ROUTINE (THE' ADDITIONAL REQUIREMENT FOR NEGATIVE 01
REM
IS FOR THE POLE-SEARCH ROUTINE )
REM
REM
IF ABS(SP-SQ)EMEIHATION VALUE FOR FQ
FI = FQ
OF = (FA-FI)/IO*
OOSUB 30300
DE
(FQ-Fl)/10#
OF
0
FQ ~ Fl

22·53

AP-155

39100
39200
39300
39400
39~00

:W600
39700
39800
39900
40000
40100
40200
40300
40400
40~

40600
40700
40800
40900
41000
41100
41200
41300
41400
41500
41600
41700
41800
41900
42000
42100
42200
42300
42400
42500
42600

REM
REM 3 INCREMENT Fli
REM
Fli • Fli + DE
REM
REI'! 4. FOR 'THIS VA~UE OF FG, FIt~D THE VA~UE OF SG FOR WHICH THE ~OOP
GAIN HAS ZERO PHASE. (THE ROUTINE WHICH DOES THAT NEEDS OF = O.
REM
SO THAT IT CAN HOLD FG CONSTANT. AND NEEDS AN INITIA~ VA~UE FOR
REM
OS. WHICH IS ARBITRARILV SET TO OS = 1000. )
REM
REM
OS • 100011
SCi = 0
GOSUB 30300
IF A~.I! THEN RETURN
REI'!
REI'! 5. FOR THIS VA~UE OF SG+JFIi. CA~CU~ATE THE SIGN OF (AL-l).
REM 6 IF THE SIGN :OF (A~-I) HAS NOT CHANGED. GO BACK TO 3
REI'!
IF SVX+INT(SQN(A~-I'))=O THEN PRINT E~SE 39400
REM
REM 7. IF THE SIGN OF (AL-I) HAS CHANGED. AND THIS VA~UE OF FG IS WITHIN
1HZ OF THE PREVIOUS SIGN-CHANGE. EXIT THE ROUTINE
REI'!
REM
IF ABS(Fl-FIi)(1 THEN RETURN
REM
.
REI'! 8. DIVIDE THE FG-INCREMENT BV -10.
REM
DE = -DE/IOII
1'1 = FG
SVX • -svx
REI'!
REM 9 GO BACK TO 3
REI'!
GOTO 39400
REI'!
REI'!

42700 REM

42800
42900
43000
43100
43200
43300
43400
43500
43600
43700
43800
43900
44000
44100
44200
44300
44400
44500
44600
44700
44800
44900
45000
45100
45200
45300
4·5400
45500
45600
45700
45800
45900
46000
46100
46200
46300
46400
46500
46600
46700
46800

REM
REI'!
REM
REM
REI'!
REM
REI'!
REM
REM
REM
REI'!
REI'!
REM
REM
REM
REM
REM
REM
REM
REM
REI'!
REM
REM
REM
REM
REM
REM
REM
REM
REM
REM
REM
REM
REI'!
REM
REM
REM
REM
REM
REM
REM

***************************************************************
STEADV-ST,ATE ANALVSIS
The circuit model used In thiS .nal~sls is similar to the one used
In the 'small-slgnel anaIvsi., but differs from it in two r'spects
First, it Includes clamping and clipping effects described in the
text. Second, the voltage .ource in the Thevenln equivalent of the
amplifier 15 controlled b~ t~e input voltage In accordance with an
Input-output curve defined Ilsewhere In the program.
The analYSIS applies a Sinusoidal Input signal of arbitrary
amplitude. at the OSCillation fr~~uencv. to the XTALl pin, then
calculates the resulting waveform from the voltage source USing
standard Fourle" techni~u.s. the fundamental 're,uenCV component of
thiS ~av.form is extracted This fr.qu.nc~ component is th.n
multiplied bV the factor :ZL/(ZL+RO)~l, and the result is tat.n to be
the .,gnal appear1ng at the XTAL2 pin This .,gnal is then
multiplied bV the'feedback rat10 (beta). and the result is taken to
be the Signal appearing at the XTALl pin The algorithm IS no~
rep.ated uSing thiS computed XTALl Ilgnal 85 the assumed input
Sinusoid. EV.TV time the algor1thm is repeated, new valu • • • ppe." at
XTALl and XTAL2. ,but the values Cl\eng8 les. and 1 ••• with each
repeUtlon 'Eventually they stop changing. Thu 10 the steady-state.
The algoTtthm IS • • follows
1. Compute approximate OSCillation fre~u.nc~
2 Call a Circuit analvsls at thiS frequ.nc~,
3 Find the qUiescent levels at XTAL1 and XTAL2 (to establish the
beg1nn1ng DC level at XTAL1)
4 Assume an Initial amplitude ~o~ the XTALl signal
5 Co~r.ct the DC l.vel at )CTALl for clamping effects, if n.c •••• r~
Using the approp~late Input-output cu~ve, extract a DC lev.l and
6
the fundamental frequenc~ component (multiplY1ng the latter by
:Z~/(ZL+RO):)
,
7. Cl1P off the negative partlon of thiS output signal. If the
neqative peak falls below zero
6 If thiS Signal, multiplied by (beta), dlffeY's f~om the Input
amplitude b~ less ,than lmV, OT' If the algorlthm has been repeated
10 times. eXlt the routlne
9 Other"llse. multlpllJ the )CTAL2 amplltude b\l (beta') and feed It
bac~ to ~TA~I. and go bac~ to 5
COMPUTE APPROXIMATE OSCILLATION

F~EQUENCV

AP·155

46900
47000
47100
47200
47300
47400
47500
47600
47700
47800
47900
48000

GOSUB 9700
REM
REM
2, CALL A CIRCUIT ANALYSIS AT THIS FREQUENCY.
GOSUS 20800
PRINT "ASSUMED OSCILLATION FREQUENCY' "
PRINT
PRINT
GOSUB 26600
PRINT
PRINT
REM
REM
3 FIND QUIESCENT POINT
REM (At quiescence the voltages at XTAL1 and XTAL2 a~e equal This
REM
voltage level IS found b~ trlal-and-error, based on the inputREM
output curve. so that a person can change the input-output curve
48100 REM
as desired without havlng to re-calculate the quiescent point )
48200 VI
0
48300 VB = 1
48400 1'.1 = I
48500 VI = VI + VB
48600 GOSUS 13600
48700 IF ABS(VO-VI)( 001 THEN 49200
48800 IF KI+SGN(VO-VI)=O THEN 48900 ELSE 48500
489001'.1 = SGN(VO-VII
49000 VB = -VB/IO
49100 GOTO 48500
49200 VB
VI
49300 PRINT "QUIESCENT POINT = ";VB
49400 REM
49500 REM
4 ASSUME AN INITIAL AMPLITUDE FOR THE XTALI SIGNAL
49600 EI
01
49700 NRX
o
49800 REM
49900 REM
5. CORRECT FOR CLAMPING EFFECTS. IF NECESSARY.
50000 REM OH and K2 are curve-fitting parameters f!lr the ROM parts. )
501001'.1
(2.5-VB)/(3-VB)
502001'.2 = (VB-I.25)/(3-VB)
50300 IF ICX=2 OR ICX=4 THEN IF EI«VB+ 5) THEN EO
VB ELSE EO
EI 5
KUEI+K2
50400 IF ICX=I OR ICX=3 THEN 'IF EIandwidth, In ,addition, staticcolumn decoding simplifies system
design by eliminating critical timing
relationships while providing higher
system speed. Access from column
addresses gives usable speed for
single random accesses wit,hin the
RAM. Also, the CMOS, technology
enhances reliability by incorporatjng
a mechanism to significantly reduce
soft errors. Finally, increased stored
charge creates larger internal: signal

levels, which cat:' more easily bE; differentiated from ,noise. As a result,
the CMOS dynamic RAM has wider
operating margins and system reliability is improved.
Power Consumption
At the system level, dynamic memory has three components of power:
active, standby, and refresh. The
system's power consumption is defined as

where P = system power, V = voltage (5.5 V worst case), IA = active current, IA = standby current, I. =
refresh current, M = number of active devices, K = number of devices
in standby, and N = total number of
devices.
CMOS reduces the first term, the
active current, relative to NMOS by
a factor of 2. In addition, the lower
active current reduces supply voltage
transients, 'thus
simplifying
printed-circuit-board design and
reducing decoupling-capacitor
requirements.
The second term, standby current,
is also reduced by a factor of 2 at TTL
input levels. Driving the RAS signal
to a CMOS level (VDD -O.5 V) phlces
the device in a low-power-standby
mode and typically draws 10 microamperes (/tA)-a factor of 50 reduction over NMOS!
Refresh current, the third term in
the equation, is cycle-time dependent. Current increases with the frequency of refresh., In dynamic IlAMs,
data is stored on a capacitor that must
be replenished or recharged every 2
or 4 milliseconds (ms). This ,refresh
time is a function of the stored charge
and the leakage current. With the
CMOS dynamic RAM, the cell storage capacitance is 0.125 picofarad (pF)
compared to 0:040 pF to 0.085 pF in
an NMOS dynamic RAM. This low
capacitance, coupled with lower leakage currents; permits the CMOS refresh pedod to be extended to 64 ms
in standby.
At the standard 128 refresh cycles/2
ms (equivalent to a 15.625-p.s refresh
period), ,the NMOS device draws
about '4.8 milliamperes (mA) and

,23-14

asymptptically approaches the standby 'current 6f 4 mA as the refresh
period, approaches' infinity. Even
eliminating refresh entir~ly only reduces the current to 4 mA, which is
only a 16 percent improvement. As a
result, extending NMOS refresh does
not significantly reduc~ the system's
power consumption.
Contrast this characteristic to the
improvement CMQS offers. At 15.625
p'S, the CMOS dynamic RAM draws
approximately 10 percent of the
NMOS current, or 0.42 mA at TTL
levels. Extending the refresh period
reduces the current asymptotically to
the standby current of 0.05 mA. At a
64-ms refresh period, the current is
reduced to 0.15 rnA, a 300 percent reduction. When battery powered, the
CMOS system has a 10 times longer
life than does the NMOS system, and
an extended refresh mode offers
another fivefold improvement. A
256K-byte CMOS memory can retain
data for nearly one week on only AA
nickel-cadmium (nicad) cells-more
than sufficient for most portable
systems.
High-Speed
Applications
Ripplemode and Static Column
mode are ideal for applications involving high-speed buffers, telecommunications, and graphics. Bitmapped graphics systems would
seem to be a natural fit with Page
Mode operation. However, this was
not always the case. Prior to the In·
tel 2164A 64K by I-bit NMOS
dynamic RAM, it was difficult to,retrieve all 256 bits within a single row,
of memory because of the RAS-low
time limitation of 10 p.s. Even with a
Page Mode cycle time of 125 ns, to
retrieve all 256 bits would require ,32
p's-three times longer than allowed.
The 2164A e,xtended ,the RAS-low
time to 75 p's, permitting theextraction of all 256 bits during a single
Page Mode cycle.
At the end of the cycl~, the ,device
cannot be reaccessed again until after
a certain off-time allows internal
nodes to be precharged to be ready
for the next cycle. As a result, the
2164Acan stream data at greater than

a 7-MHz rate continuously. This function matches the timing and operation of low-performance, bit-mapped
graphics memories. One 2164A, for
example, can map all the data for the
256 by 256 matrix of a graphics display. During the horizontal. scan time,
the RAM performs a Page Mode cycle and one full line is displayed.
During retrace time, the memory
must be refreshed and can be updated with new data if required. This
type of update is relatively slow; consequently, it limits the speed of
animation on the· screen because the
processor has access to the memory
only 25 percent of the time.
To increase resolution, more lines,
each with more pixels, must be used.
By performing two sequential Page
Mode cycles from two different
RAMs, pixel densities to 512 bits per
line can be achieved. As pixel density increases, the memory cycle time
must decrease to paint more pixels on
a line in the same amount of time.
This cycle-time limitation plus the
fact that memory can be updated
only during blanking has precluded
dynamic ·RAMs from use in
higher-resolution graphics displays.
These systems are usually built with
high-speed, expensive static RAMs.
With Ripplemode, memory update
during screen display time, also
known as cycle stealing, is possible.
As an example, a 512 by 384 display
requires 512 bits/line and 1 bit every
67 ns. Data is read from four memory
devices in a series of eight Ripplemode reads each. Data is temporarily stored in a video-output register
file and then shifted to the video
screen at a rate slower than the Ripplemode reads. Following this,
enough time is available to perform
an update cycle before the next eight
Ripplemode reads are performed to
continue screen refresh. Eight was
the number chosen to minimize the
time the processor must wait to update the memory. In addition to this
cycle stealing, which updates during
display time, memory updates are
also performed during blanking.
Along with this system, a similar system was built using 2164As with Extended Page Mode operation. Each
system used an iAPX 86 processor

and similar software. A comparison

of both systems showed the CHMOS
(complementary high-speed metaloxide semiconductor) system to have
a 42 percent higher drawing speed.
Animation on the CHMOS system
was vastly improved.

Usable Speed

ing the CAS signal from the critical
timing path.
Systems using dynamic RAMs are
typically CAS access-limited because
controllers generate timing signals in
discrete dock increments. A CMOS
dynamic RAM system might operate
at 8 MHz without Wait states. Using
any other 64K-bit dynamic RAM
would require the injection of one or
two Wait states, resulting in a corresponding.performance penalty. Consequently, the advantage of higher
processor speed is negated without
the high-speed dynamic RAM. For
systems incorporating either discrete
or LSI controllers, the CMOS
dynamic RAM simplifies the system
design and offers higher system
performance.

Memory design using dynamic
RAMs has always been a challenge.
Although multiplexing addresses
does reduce the package pin count
and increase system density, it ·limits
the access and cycle times in the
system. To access a dynamic RAM,
low-order row addresses are presented and latched into the dynamic
RAM with RAS. Row addresses must
be held for a period tRAH after the fall
of RAS to guarantee proper operation. Next, the addresses must be High Reliability
Soft errors are random, nonrecurchanged to high-order column addresses and latched into the dynamic ring failures caused by ionizing radiaRAM with CAS, creating a timing tion present within the environment.
window tRCD, which is the RAS-to- All matter contains small amounts of
radioactive material. Alpha particles
CAS delay.
Within this window, the designer emitted by an IC's packaging material
must guarantee row address hold can penetrate the enclosed circuit. As
time, change the addresses, and ac- they do so, they generate hole-eleccount for any timing skew on the tron pairs. Any high-impedance
CAS signal. If column addresses are node in the vicinity sensitive to 1
valid at the maximum specified tRCD , million electrons may be affected,
access time tRAC is measured from the because the difference between a 1
and a 0 (known as the critical charge)
high-to-Iow transition of RAS.
The cycle time is the sum of the ac- :s about 1 million electrons. Consecess time and the cycle precharge quently, data in one cell could change
time tRP ' The access time is a function from a 1 to a 0 or vice versa. Correct
of i RCD, which has contradictory re- data can be rewritten into the affected
quirements. It must be as long as cell and the memory ""ill again funcpossible to simplify system design tion correctly, thus the term "soft
and at the same time as short as error:'
When first discovered during tests
possible to enhance system speed.
Cycle time is affected directly by the of 16K-bit dynamic RAMs, soft errors
length of tRP •
'
occurred at a rate five times greater
Static-column operation eliminates than catastrophic or hard-error failthe tRCD problem. After row addresses ures. While device designers worked
have been latched into the RAM, the to eliminate the alpha-particle sensecond portion of the access begins sitivity, systems designers added
from valid column addresses. In error-correcting circuits (ECC), which
other words, column access does not increased system reliability, but the
wait for CAS to become valid, but systems were larger and more expenoperates in a fashion similar to that sive due to the additional comof a static RAM. This is due to the ponents required. Also, the system
flow-through operation of the CAS had to test and correct the data, slowlatch. CAS serves only to latch the ing the systems performance. All this
addresses and to provide an output was due to soft errors. Obviously,
enable. Access from valid column ad- what is really required is the eliminadresses simplifies design by remov- . tion of soft errors.

23-15.

CMOS teChnology off~rs' such a fo m9re stored charge, which in turn benefit by the elimination of ECC cirsolution.' The CMOS dynamic 'RAM increases the critical' 'charge. The cuits from a cost, performance, and
cell is built on an n-well in: a p·sub- critical charge is the number of par- Simplicity-of-design standpoint. First,
strate, 'crecitirig a' p-n junction or ticles that differentiate a 1 from a O. ECC increases the access time of the
diode at' fhe boundary. When' alpha Increasing the critical charge beyond system by 50 ns'to check and correct
particles create hole-electron pairs in 1 million electrons significantly data. Assuming a 120-ns RAM aca CMOS device, something else oc- reduces the susceptibility to soft er- cess, ECC increases the access by 42
curs. First, the n-well is very shalloW, rors. This, in addition to the n-well percent.' Moreover, the penalty on cyand the majority of hole-electron mechanism, reduces the soft~error cle time is even greater, especially
pairs are created in the p-substrate. rate to much less ,than 0.001 percel'lt when you are writing a single byte inHoles cannot transfer across the per'looo hours.
to a 2-byte word. In this instanc~,
reverse-biased p-n junction, which
Studies' were performed to com- data must be accessed and corrected,
acts as a barrier to soft-error effects. pare reliability of systems with and the new byte merged into the word,
Any electrons that do cross the junc- without error correction for both and check bits generated. Finally, the
tion are gathered at the + 5-V node NMOS and CMOS dynamic RAMs. system must write the new data into
away from the storage cell. The' prob- The'results show one surprise: at memory. Added to this are any sysability that sufficient hole-electron 256K bytes and below, the CMOS tem-timing skews. As a result, a
pairs are created witnin the n-well system without ECC is more reliable 200-ns cycle time stretches to a 335-ns
that cell upset could occur is so low ,than the NMos system with ECC, system cycle time or an increase of 68
that the soft-error rate of CMOS because of the cycle-time depen- percent. Therefore, using a CMOS
dynamic RAMs is typically orders of dence of soft errors. In small systems, dynamic RAM not only improves
magnitude below that of their NMOS the memory is accessed more -fre- system reliability but enhances syscounterparts.
quently, and the probability of a soft tem speed and simplicity of design .•
High storage capacitance also plays error is increased. With a soft-error
a role in the reduction of soft errors. rate at the very minimum 100 times
The number of stored charged elec- less than NMOS, the CMOS
Joe AI/nether IS lechmod marlreling manager al
trons representing a lora 0 is direct- dynamic RAM does not experience
Intel Corp. (21ll N. E 25th Ave., Hdlsboro, OR
ly proportional to the storage capac- this effect.
Systems below 256K-by'te capacities 97123).
itance. Higher capacitance ele
'\:
EPITAXIAL SUBSTRATE
!.
ONn+WAFER
while contained in a minimum area. Thus the chip! designer must use high-gain n-channel t,ransist9rs for the
I ce!I's pass gates and puIldowns. For good soft-error pron 200
p·TYPE EPITAXIAL SUBSTRATE
iii
tection, th~n, the cell must be located in a p-weIl within,
ONP+WAFER~ ,
,
an n-type substrate.
100
The p-weIl approach benefits even full ~.MOS six-transistor static-RAM cells. The area of such ceIls depends
strongly on the distance allowed between n- and p-channel deyices. Using,a straightforward implementation of
10
epitaxial C-MOS, the p-well, approach provides more marn-TO-p SPACING (,dn)
,,'
gin against latchup at small mto-p spacings (Fig. 3).
This phenomenon occurs because of the differing diffusion properties of n- and p-iype dopants. The heavy 3. Powe•• ma~in. With an epitaxial substrate. a p-well structure (updoping in the n-type substrate is less mobile than is the per curve) y~lds a greater margin ageinst latchup than n·well at
p-type dopant, resulting in less outdiffusion during ther- smaHer n- and p-devlce spacings.
mal processing and thus minimizing the shunt resistance
contact etch attacked the silicon substrate or if the conthat controls latchup.
tact was, misaligned toward the field-oxide edge, the plug
Hooking it up
would rejuvenate the resulting weakened junctions. In cOne of the challenges of C-MOS in logic applications is MOS, these sallie attributes must be obtained differently,
interconnection. Designers of noMOS chips are accus- through improved fabrication, cleanliness, new gettering
tomed to buried contacts, which directly connect, n-type techniques, improved dielectrics, and tightly controlled
polysiJicon and ootype transistor source or drain regions. contact etching. Figure 5 shows the difference in impleBecause C-MOS requires contact to. ,both p and n regions, menting a 1.5-,...m contact structure in n~~1Os and C.MOS.
Along with the proliferation of C-MOS technologies has
the traditional n-type buried contact becomes much, less
useful, and a version suitable for ,both ,diffusion polarities come a wave of innovation -in 'C-MOS design techniques:
is quite difficult to implement. This increases the burden For digital logic, the, major contenders for broad U$e are
fuIl complementary design and domino logic, first proon .contact and metallization modules.
For high-density C-MOS logic, the first level of metal is posed by AT&T Bell Laboratories (Fig. 6). For many
all but consumed by ~Ocal connections betwee/l ,p and n applications, traditional C-MOS logic is a winner. It retransistors. The payback from adding a second level of quires no clocks, has larger' operating margins,' and uses
metal for longer-distance routing is very high. A good fewer transistors, for simple gates. For more complex
example exists for the six-transistor statiC-RAM ceIl com- gates, however, domino logic uses fewer transistors and
monly used by logic designers. Figure 4 compares sin- runs faster. The speed results from connecting fewer
gle- and double-metal versions, of this cell, both imple- transistors in series and reducing gate-fanout loading by
mented with 1.5-,...m design rules.
Here the second-metal layer provides
the bit lines for the cell. Similar arguments justify the use of second
metal in global power, clock, and
data routing in complex microproce$sor c h i p s . ,
Contacts themselves are more dif-'
ficult to build in C-MOS. N-MOS technology .accustomed process engineers
to adding a phosphorus contact plug
after the contacts have been etched.
This plug brought several advantages: the phosphorus gettered metallic contaminants from the wafer, reducing junction leakage; and ,the
high-temperature diffusion rounded,
(0)
the profile of the contact sidewall"
easing. the step coverage of the metal 4. PaJbaok, Theuse of double-metal layers for a six-tranSistor static-RAM cell can prodUce's
subsequently deposited. Further, the' large savings in rea~esta'te. In twO cells implemented With a 1.S.pm design rules;,the savings
pl~g had self-aligning features. If the can am\llunl to one1hlrd of the total area: The cell at right uses second-layer metal for bit hnes.

~·TYPE

I
I..

Electron,ical May 3.' 1984

23-20

5. "king conblet. Contacts anI more difficult to build in C-MOS than in convenllOnal nMOS, The phosphorous contact plug used in
noMOS after contact etching (a) adds desirable features such as reduced junction leakage and improved step' coverage by the metal
layer, To gain the same advantages in CMOS reqUIres greater process control (b),

METAL

PHOSPHATE
GLASS

FIELD

OXIDE

(0)

METAL

(b)

~1·~------I~pmBAR-------·~1

up to a factor of two comp~red with full C-MOS.
Interestingly; the choice of design' style influences the
optimal type OrC-MOS well. The speed of full C-MOS is
limited by the slower of the two transistor polarities.
Since the trip point is quite close to half the power
supply, the time required for either transistor type to
discharge its load capacitance by about 2.5 v sets the
gate's speed. Since the p-channe! device is the weaker
one, it pays to choose a well type that improves the pchannel's cor)ductance. P-well- does this because the pdevice is fabricated in an uncompensated substrate and
thus has maximum mobility, Comparisons between n, 6. Logic. Two major contenders for digital logic
design are full complementary (a) and domino
logiC (b), The former requires no clocks and IS
simpler ior many applications. Domino logiC,
which performs best In an
• n-well technology, is faster and simpler for more
complex CirCUitS,

L-._ _....._

and p-well construction show that
the p-channel's conductance may be
improved by as much as 10% with
the proper well type,
By contrast, domino logic is at its
best in an n-well technology, Here,
the n-channel transistor dominates
both performance and transistor
count. Placing the n-channel device
outside the well improves its conduc·tance and reduces the dominant parasitic junction capacitance. Density
also increases because no well contacts are required for the majority of
the transistors.
The twin-well approach to CoMas
blurs these distinctions. In this approach, a high-resistivity epitaxial
layer is grown on a heavily doped
starting wafer. Then the doping for
each transistor polarity may be independently optimized without need
for doping comPt:nsation. Performance arguments based on mobility
or junction capacitance thus become
moot. Nonetheless, domino logic will
still be best on a p-type substrate
(equivalent to n-well) because it does
not require well contacts' to collect the large parasitic
substrate curren'ts from the n-channel transistors, thus
improving packing density.'

Matching process to product
"These and other technical arguments may be conibined
into a consistent strategy (Fig. 7) for creating a line of
C-MOS processes serving a broad marketplace. For at
least the next several years, a complete technology line
must include C-MOS based on both p- and n-type substrates. Fortunately, choosing epitaxial-latchup control
minimizes the development cost of running both process-

OUT

(b)

(0)

Electronicsl May 3; 1964

23-21

es. Dynamic RAMs are supported on' the n-well side to
minimize pattem sensitivities 'induced by substrate currents while protecting the p-channel cell from soft errors.
E·PROMs are built in a similar n-well C-H·MOS process.
Placing Intel's noMOS E·PROM cell in an epitaxial p-type
substrate eliminates parasitic effects caused by high substrate currents flowing during' cell programming.
Microcontrollers land on the n-well side also, so that
they may incorporate on-chip E·PROM cells. Most microcontroller products come in two versions, OJ;le with onchip .E-PROM for system-development and manufacturing
flexibility, and another with on-chip ROM for lowest cost.
Using n-well C·MOS, a single core design can support,
both versions. Telecommunications and signal-processing
products can also take advantage of the n-well E·PROM
process, both for its high-quality polysilicon-polysilicon
capacitors and for the E-PROM cell's programmable features. High-performance static RAMS, whether six-transistor or polysilicon-Ioad, can take advantage of a p-well
C.H.Mosprocess. High-end microprocessors can key off
the dense n-to-p packing and double-metal capability offered by the six-transistor static-RAM process.
Because these processes are modular, development is'
simplified and manufacturing overhead is minimized.
Just as all the 1.5-/-lm C·H-MOS JIl technologies share a
common transistor module, the difficult contact module
was developed Ollce to be shared among all. Specializeli
features such as double polysilicon or double metal are
extensions of the common base.

The future
C-MOS technology is still developing at a frenetic pace.
Surprisingly, the application of some newer techniques
and the demands of next-generation circuits may bring
the various forms of C·MOS closer together, rather than
further splitting the number of integrated processes.
One example of this trend is the development of a
trench-isolation technique for separating nand p devices.
When this module is perfected, there will be no reason to
develop six-transistor static-RAM cells on p-well technology. The near-ideal trench isolation will prevent latchup
on either substrate type. Similarly, if stacked C-MOS statiC-RAM cells can be perfected, there will be no need for
polysilicon loads. The stacked C-MOS cell will have the
same density but with improved performance and softerror immunity. At that time, twin-well C-MOS on a ptype substrl,ite, augmented by specililized features for specific product lines, will become the one approach to a
broad line of coMbs processes.
Another factor affecting future C·MOS integration is the
continued scaling of transistors. It is well known that the
weaker p-channel transistor- is gradually catching up on
the n-channel device as channel lengths enter the 'submicrometer region. Eventually, the performance differences
may become so small that p- and n-channel devi.;:es will
be used interchangeably. Before this level is reached,
however, the 5-Y power-supply standard must. be reduced. Because of the large base of TTL-compatible designs and the impossibility of converting the world to a
new standard ovemight, components operating from the
new reduced supply will need to maintain TTL compatibility and also be able to operate in a system that mixes

E·PROM.
TELECOM
CHIPS

7. TecHnology tr.... A relatively small line·ol C-MOS process variations. or modules. can be matched to a wide vanety of products to
serve a broad marketplac~. The broken hnes Indicate directions of
. potential future growth.
I

older 5-Y components with lower-voltage ones. An onchip 5-to-3-Y converter may be one way to solve the
problem. This technique, however, will waste up to 40%
of the total chip power within the voltage regulator.
C·MOS technology provides an elegant solution because
it can drive TTL-compatible output levels from a system
power supply as low as 3 Y. Since TTL levels. are referenced to the negative (ground) rail, the grounded substrate offered by n-well C·MOS is a much-preferred means
of integrating submicrol)1eter transistors into such a system. This will be a strong motive to standardize on psubstrate C·MOS.
A final factor that tends to drive future C-MOS processes toward commonality is the growing importance of RC
delays in overall chip performance. The latest high-performance static RAMs use an aluminum strap in parallel
with the polysilicon word line because the RC delay
induced by even the best refractory metal polycides is
several nllnoseconds too long. Studies of dynamic RAMS
larger than 1 megabit similarly indicate that refractory
word lines will probably be inadequate, forcing the technology to support two layers of metal. Combining these
observations with those made previously regarding the
evolution of statiC-RAM cells leads to the conclusion that
most future C·MOS technologies will have two layers of
polysilicon as well as two layers of metal.
The development of silicon-on-insulator technology is
the one major factor that could renew the divergence of
C·MOS approaches in the future. However, until the quality of SOl substrates is adequate to support dynamic RAM
and E-PROM cel!!" and not Just static logic, it will not
playa major role in a broad-based and modular tet:hnology strategy.
0

Electronics/May 3, 1984

23·22

i\dvanced
Packaging Information

~lI

CHAPTER 24
ADVANCED PACKAGING
24.1 Introduction

with certain application in mind, such as mounting methods, board material, thermal characteristics and external
features. Intel's Microcontroller Operation offers two varieties of JEDEC packages, both with 50mil spacing, a
square ceramic leadless type and a square plastic leaded
type.

Today, system designers using LSI and VLSI devices are
continuously facing problems associated with achieving
the highest system performance level, and most complex
functional level of a particular system application in the
smallest physical size possible. Until recently the available
solutions to these device problems were limited to the
traditional standard dual-inline-package (DIP) based on
lOOmii center-to-center lead spacing and flat packages
(FP). Today, these device problems are being solved in
a number of new ways; DIPs based on 50 mil center-tocenter lead spacing, surface mounted small outline DIP,
surface mounted chip carriers, surface mounted gull-wing
flat package and pin grid arrays. Among these possible
solutions the two that are emerging as the next standard
IC packages for LSIIVLSI devices are the surface mounted
chip carrier and the pin grid an;ay.
'

In addition to these mechanical packaging advantages,
there are also electrical benefits. The package arrangement
of the chip carriers 110 pads, on all four sides, allows for
package traces to be shorter and more uniform in length.
This allows lower resistance, less capacitance and less
inductance, resulting in higher system performance and
improved switching characteristics.

24.3 Why Chip Carriers?
Figure 24.1 shows the differences between the surface
area (in2) versus pin count of both a ceramic dip and a
ceramic leadless chip carrier device. 'Note that l!ll 18-pad
chip carrier offers a 57% saving in area. As the pin counts
increase, the chip carrier surface area advantage becomes
significantly more obvious. This space efficiency allows
the system designer to increase the number of components
on a board or decrease the overall board size and, thus,
the overall system size.

24.2 What Are Surface Mounted
Chip Carriers?
The chip carrier is basically the business portion of a DIP.
Chip carriers are available in two general types: leadless
and leaded.
The leadless chip carrier construction is accomplished in
much the same manner as the'multi-layer ceramic DIP
package, but it is missing the side-brazed legs and much
of the ceramic surrounding the die cavity area. Instead,
it 'consists of a ceramic package with 1/0 pads on all four
sides, a die cavity area, metalization traces to the 1/0
pads, and a hermetically sealable lid. Leadless chip carriers are available in either square or rectangular package
outlines. The leadless chip carrier can be attached to a
board surface either directly, by socketing, or by the addition of add-on leads.

- - CERAMIC DIP

3.0

- - - - CHIP CARRIER (LEADLESS, CERAMIC)

The leaded- chip carrier construction is accomplished also
in much the same manner as the plastic DIP package, but
has leads that are bent down and under the package on
all four sides rather than like the DIP. It is also missing
much of the plastic surrounding the die platform and consists of plastic material encapsulating the die platform with
110 pads or leads on all four sides. The plastic leaded chip
carrier is available in square or rectangular package outline, that can be attached to a board surface either directly
or by a socket.
Chip carriers are registered JEDEC standard packages.
The standard is based upon two basic package types, one
with 50mil center-to-center terminal spacing, the other
with 40mil spacing. Each package: type was developed

24-1.

..-.-_.---

1.0

~----

..----_.

~-.----

PIN COUNT

FlgLlr.e 24.1. Package Area

ADVANCED PACKAGING

For an 18-pin count, there is a 77% weight saving and as
, the pin counts increase to 28 and to 48. this weight savings
increases to 90% and 95%, respectively. In the case of
the plastic leaded chip carrier, the weight savings over a
plastic DIP is noticeable but not significant. However, it
is in the ability to decrease the board size and, thus,
economizing on material and weight reduction that the
significant advantage exists.

3.0

- - ~ ~ CHIP CARRIER (PLASTIC, LEADED)
- , - PLASTIC blP

24.4 What Are Pin Grid Arrays?

1.0,

,-'

--_-.....
16

.....

_-.AI""''''

PIN COUNT

Figure 24.2. Package Area
Figure 24.2 shows the differences between the surface
area (in2) versus pin count of both a plastic DIP and a
plastic Leaded Chip Carrier device. As can be seen, the
savings in area is also as significant as the pin count
increases, allowing the same system benefits.
However. the biggest advantage a ceramic chip carrier has
over a ceramic dip is in its weight. Figure 24.3 shows the
difference between the weight (grams) versus pin count
of both ceramic DIP and ceramic Leadless Chip Carrier.

The Pin Grid Array is basically a combination of the
ceramic DIP and ceramic Leadless Chip C,arrier. The Pin
Grid Array construction is accomplished in much the same
manner as the multi-layer ceramic DIP, but it is missing
the side-brazed legs and much of the ceramic surrounding
the die cavity. Instead, it consists of a ceramie package
with leads coming off the bottom in rows or circular patterns. The Pin Grid Array is available in square package
outlines with lead spacing of 100 mils and can be attached
to a board in the same manner as a DIP.
Pin Grid Arrays are being proposed as JEDEC standard
packages and will have from 1 to 10 nested rows of legs
and may have a die cavity mounting area oriented up or
down.

24.5 Why Pin Grid Array?
Figure 24.4 shows the difference between the surface area
(in2) versus pin count of both a 50 mil spacing chip carrier
and a 100 mil spacing Pin Grid Array device. Note that
at approximately 68 pins and ab9ve the Pin Grid Array
becomes a better solution for higher pin count requirements than the chip carrier. In addition, the 100 mil lead
spacing and through board mounting'technique provides
customers with an assembly technology that is familiar.

_ _ _ _ _ CHIP CARRIERS (LEAD LESS CERAMIC)

3.0

12
- - . CERAMIC DIP
10

"/,,,

;;-

~ 2.0

_-..t

1.0

28
PIN COUNT

,',',J/,"

,,.

II:

,tI

... -- ---- .... ----- -....... ',.."..,.

"II

,,/1

0.500" CHIP CARRIER

- - - - 0.100' PIN GRID '

2040

120

180

200

240

PIN COUNT

Figure 24.4 Surface Array

Figure 24.3. Package Weight

24-2,

280

300

ADVANCED) PACKAGING
CERAMIC LEADLESS CHIP CARRIER
All dimensions in inches and (millimeters)
44-Leadless Hermetic Chip Carrier
JEDEC Package Type C

.-099(2514)
081 (2057)

::g:::!I+1 B 10101

r--1.rv""V"V' '''('''''}
620 (15 748)

50011210'0)

HAIOO6I
&20-(15748)

6OOqS2401

r-.;-,
L:±:J

o
44

149(3784)
120(3048)

620(15748)

REF

660 (18 764)
640(16256)

[+[Al}tOJ

1
PIN 1 INDEX CORNER

24-3

ADVANCED PACKAGING
CERAMIC LEAD LESS CHIP CARRIER
All dimensions in inches and (millimeters)'

44-Leadl... Hermetic ChIp Cerrler
JEDEC Package Type C

J . - - - " 2 0 (1U4I) R E F ' - - _

TYP4PLCS

24-4

ADVANCED PACKAGING
PLASTIC LEADED CHIP CARRIER
All dimensions In Inches and (millimeters)

44-LMcIed Chip C.rrIer
JEDEC Package Type C

_(1...12)
.II1II(1"'10)

::::::::-1 j

1 44

.G21 (0.133)

~Tc:f::IH=*=- (0.113)
~

PIN 1

INDICATOR

I~_"...

~.1111(17")

24-5

infel"

.ADYANCEDPACKAGING

Pinout.
MCS

r' r-,

l~9_

P2 S

:27; ;28:

. .
&:

)(

:22: :23: ~4:
{!'

"
"':

L6J L5J L4J :3:
L....I

:'-..J
21

'1 '
I 1

P1.S

:411
~~< !43:
....... :42: L..J
~..J

~
140:
'-..J

PO.'

c...J

P16

PO.S

P1.7

PO.6

HIT

PO.7

P3.0

EAlvPP

. 8751H*

P3.1

ALEIPROO

P§EN

P3.3

P2.7

P3.'

P2.6

P3.S

r,
'181
, I

1
I'19 ,

[20:

...

'-,21 , ,r,, r ' -,
:23: :24:
1

. i!..

..J

1221

>'"
'"

r, r ' r., r-,
1

125 1 126
I I
N

'"
0.

,27 1

;28:

"Top View Looking Through Package

P2.S

inter

ADVANCED PACKAGING

Pinouts
MCS®-48 Family

.... .

:'--'3: :'--'2: '"LJ

L&J L5J L4J
fliT'
EA
iifj

JSftR

WI!

Ne
ALE

DB.
DB,
DB.
'083

u
~

u
z

:;!

" "

144 1

;:::

~~ ~5 :41\ :40:
'--'
L~

r-L!'_

=7=J

r--

=~J
=~J

L~8_

r--

L~7_

--,
2~.J

r--

l~6_

--,

r-L~5_

_1.!.J

--,
2~.J
--,
~:!.J

r--

_1~J

--,
~~J
--,
~~j

r, r,
1181
,

'191

:20:,

1211
"

rJ
0

rl
0

01>

co
~

LsJ LsJ L4J :'--'3:

:2 :
'--'

',' LJ
'«' ~~ ~~

1411

u
z

:;!

r, r' r' r,

)(

;:::

l~~
r-l~O_

P1Q

r--

VDD

L~~

1.:

iNf'

P12
PH

:23: :24: ,25; ,126·, :27; :28:
...
zu Ii!
0

...
I .

r, r'
1221

PIS
Pl.

P13

l~t

--,

P,.

r-L~
r--

--,
~~j

P,7

r--

L~_

80C49/39*

P2.

P2'

P17

jjjj

P16

i'SEIiI

P15

WI!

Pl.

8749H*

ALE

P,3

DB.

P12

DB,

PI1

DB.

P1Q

DB3

r., r, r,
1181

1191
I

:20:

r!1
0

rl
0

-,
1211
,

01>

r, r, -, r,
;22: :23: :24: ;25;

u
z

r' r-' c,

1
126
I
,

. .. ..
Ii!

:::l

:27 1

·Top View Looking Through Package

24-7

:28:

"..0a:

VDD

ADVANCED PACKAGtNG

CERAMIC PIN GRID ARRAY
All dimensions in inches and (millimeters)

68-Pln Hermetic Pin Grid Array

1~1.165(29.591)

.030 TYP 3

PLC~~ 1.135 (~8.829)
T@@@:=:@;;;:O=;@;;;:o=;@~@~@;;=;:@F'\h:-

.I030@@@@@@@@@
@
@@
@@
@@
@@
@@
@@

SWEOGE PIN

i[::;:::~:::::

PIN 1

SWEDGE PIN

@@
@@
~~=======F~==~

~~--.,

.055 (1.397)

PIN 110
CORNER

SEATING PLANE

24-8

ADVANCED PACKAGING

Pinouts
MCS®-96 Family

15
16

13
14

11
12

1
2

9
10

7
8

5
6

3
4

MCS®-96*

38 40
35 37 39

42
41

44
43

53
51

MCS®-96 Pin Table
PIN

SYMBOL

ACH7/PO.7

SYMBOL

ADO/P3.0

READY

SYMBOL

HSI2IHS04

ACH8/PO.S

AD1/P3.1

T2RST/P2.4

HSI1

ACH2IPO.2

AD2IP3.2

BHE

ACHO/PO.O

AD3IP3.3

HSIO
Pl.4

ACH1/PO.l

AD4/P3.4

PWMlP2.5

P1.3

ACH3/PO.3

ADSlP3.5

P2.7

P1.2

AD6/P3.6

VBB

Pl.l

NMI
-EA

AD7/P3.7

VSS

Pl.0

VCC

AD8/P4.0

HS03

TXD/P2.0

VSS

AD9/P4.1

HS02

RXD/P2.1

XTALl

AD10/P4.2

P2.6

REsET

XTAL2

ADll/P4.3

Pl.7

EXTINT/P2.2

13
14

CLKOUT

29
30

45
46

ADl21P4.4

Pl.6

TEsT

AD13/P4.5

Pl.5

VPD
VREF

INST

AD141P4.8

HSOl

ANGND

ALE

AD15/P4.7

HSOO

ACH4/PO.4

T2CLKlP2.3

HSI3/HS05

ACH5/PO.5

* Top View Looking Through Package

24-9

DOMESTIC SALES OFFICES

__V

fLORIDA _

~'r:oo~. Street

=.,.~

South

Suite 170

¥~:~.:~~02

AIIIZOIfA
Intel Corp
11225 N. 28th Drive
Suite 2140

Phoenix 85029
Tel (602) 869-4980
Intel Corp
1161 N EI Dorado Place
Suite 301
Tuceon 95715
Tel (602) 299-6815

QED ElectronIcs
139 Terwood: Road
Willow Grove 19090
Tel (215) 657·5600

~ (~N).£~o:'
_

~ual

ParKway

Sulll 200
Norcroes 30092
Tal' (404) 449-0541

B 295

....-

TUAI

IIEXICO

Intel Corp.12300 Ford Road

Boulevard N E.

YOIIK

Intel Corp2550 Gulf Road
Suite 815
AoUtng Meadows 60008

, Parl<: 51508.

FRANCE
Ge.....m
Z.I de
A,.,...

+~J~)

KI~

Bytech Ltd

Unit 57
london Road
Earley, ReadIng
Berkstiire
Tel' (0734) 61031
TELEX 848215

Comway' Mlcrosystems Ltd
Market Street
UK·Bracknell, Berkst)lre

~~t~~ 8~:~bl 55333

Jermyn Industnes

Vestry Estate
Sevenoaks, Kent
Tel' (0732)' 450144
TELEX 95142

MEDL
,pp

ITT SESA
~~3~~ '{Bgel 21, 6 PISO
Tel (34) 14 1954 00
TELEX 27461

,P88

91943

HerlistraS$8 31
CH-8304 .Weillsellen
Tel tOt) 830 50 40
TELEX ~6788 INOEL CH

SWEDEN
AS Gosta Backstrom
Box 12009

~~h~scnhol~

Tel (8) 541 080
TELEX 10135

Metrologle

,La 'Tour d' Asnteres
4, Avenue Laurent Cely
926Q6..Asnleres
Tel (1) 790 62 40
TELEX 611·448

1TALY

Tekelec AJrtronic

B,P 2

E/5
Tel. (02) 82470
TELEX 311351

YUGOBLAVIA.

inter
_. -

INTERNATIONAL SALES OFFICES

_..

NSW, 2065

~=..r:,:)

leYeI~ Highway
Crowe Nest, NSW, 2085
Tel' 011-61·2·957·2744

TELEX 79()..20097
FAX 011-61·2-957-274<4

_KONG
lnlel Semlcqndootor Ltd,-

1701-3 ~Cen1re

tel~5-215-311
TWX 804m ITLHK

~,J~'i

Intel Japan K.t<
5-6 TCiModai, T~
300-26
TELEX 03658-180
InIeI Japan KI<,-'

~:~1.Js~'OP

2·1·15 Naka-machi

~~21~'S4

t:t=:as'\'rkl-Mn
~:ug~~m I!.a

~~3-9"1:~

InIeI SemIconc:IuctIr

"* ltd

~~~y~U

-Seoul 150

m~~l:~l~tr..Kb

InIOI ...".. KK'
2·51·2 Ir:r~~:~

Tel 011-852-5-0-2232,22
TWX' 39114 JINMI HX

~~~I ~~IdCen!re

. . (Conl'O)

~~~~7~

Cho
Nihoobashl CttucH
Tel 011..81)2-5-833-0222

TWX 74166 SCHMC HK

_ee.. .

1041109C Nirmal Industr181 Eatale
Sion (E)

~11.~.4e1.70

TElEX- 011-71447 MOEV IN

~o:r
lcotron SA

~5~~AkoM: 3650-6 Andar

Tel 011·55-11-833-2572

TELEX 1122274 ICOTBR

CHILE
OIN

~~~. ~ehna

C&ell1a 6055.

,="r Nager

Almlak 1ntemItIona1. Inc (Agent)

IRAZJL

204

",-56-2-277-564
TELEX- 352.()()Q3

~~~~""t""d."",

3801 Kennett PIke
Wilmington, Delaware 19807

465 S Mathilda
Suite 302

Avenue

~Tot·,~~
SMa~iS

=rn

~o 't, "8'
Mauldin, South

_..

-ltd.
C<

Po. Jang

J-TEK CorporatiOn

~~3, ~c.cio-~"!

PeneIon 8ktg,

~"P"l'~po-K"

Tel 011..$2-2-782-8039

TElEX' KootGIT K25299

....,.~-

CaroIi", 29657

\~""il;g."AddO:)
Uberty, South carolina 29657

...

K«am

"
S_

Tet (7
TWX'
_
ZI.WIIID

DIGIT LSA

Mcl.aan Information Technology lid
<459 ~ P818 Road, Newmarket,

~~1~~

._..

Tel. 011-64-9-501-219, 501-801, 587037
TELEX, NZ21570 THERMAl

~=:rltd.

.....,.,....
00Ien..

Tel: 01t-92-21..s30-30617
TELEX. 2443<4 GAFAA PK

DOMESTIC SERVICE OFFICES·

. . . - (eoardl

=~Avenue

Suitt 205 '

~.(7J:~~~%7

~~Orlve

Mallland 32151

~<38,~~W

'.... Corp
2000 E 4th Street
SUIte 110
Santa Ana 92705

Suite 150

~: (':t4~~~

''''''
5530 Corp.
N. CortJIn AvenYe
Suitt 120
Tarzana 91356

Tel: (213) 708-0333

ParkwlJ)'

."'"
200 30092Norcron

rei.

(4(4) 441:'171

Denver 80222

~.(~3J~~~:,er

~To'a ~

611y

-_V
Sulle 143

Expressway

f:rh (3~:r ~~'5

Overland Park 68210

Co~

=~C:rlll

''''''

Edllon 08817
Tel: (201) 225-3000

-....-....

Tel: (913) 1}42-8080

!IIAMLANO

-..cur

OHIO

Road

8-3130
Avenue

T .

TWX:

01824
256-1800
3-6333

":,l'

. . . . . . .V.....

~': ;:,g CtMer

Bulle 301 W

Rolling Meadows 60008

~,(3J~~l~~;~

~~
EIam Young Parkway
HIIIeboro 97123
Tel (503) 681-8080
BouIevatd

~~~31a) \~~~S40

Sulle 815

Sulle 170

720 Cheny

---

~~c:: Road

Intel Corp.
8400 W. 110th Street

''''''~
r..?
..

1EIIAI

f"t.,.,...,l108
TWX. 91

52
54.....

74·1347

w_
-

\'JJo~
SuhI
380 "'""
.
Dallal 75234
Tel: (214) 241-8087
TWX: 910·860·5817
Intel Corp
110 11ath Awnue NE.
Suite' 510
Bel..... 98004
Tel' 1-800-525-5580

TWX: 910-443·3002

~~ ~\mnyaJope

Suitt 130
BrocIdleld 53005
Tel (414) 784-8081

Road

Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2014:09:15 18:38:16-08:00 Modify Date : 2014:09:15 18:26:30-07:00 Metadata Date : 2014:09:15 18:26:30-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:6ab8d176-0ea4-ee4f-8095-d274c2621bc3 Instance ID : uuid:7cbe694b-bc4b-1040-be0e-d75447908f93 Page Layout : SinglePage Page Mode : UseNone Page Count : 860
EXIF Metadata provided by EXIF.tools

1985_Intel_Microcontroller_Handbook 1985 Intel Microcontroller Handbook

Navigation menu

Versions of this User Manual:

Views

Navigation