1985_Intel_Microsystem_Components_Handbook_Volume_1 1985 Intel Microsystem Components Handbook Volume 1

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MICROSYSTEM

COMPONENTS HANDBOOK

1985

About Our Cover:
The design on our front cover is an abstract portrayal of microprocessors and associated
peripherals as the building blocks which provide total systems development solutions. Intel
superior technology and reliability provide easier solutions to specific development problems
thereby cutting "time-to-market" and creating a greater market share.

Intel Corporation makes no warranty for the use of Its products and assumes no responsibility for any errors which may appear il)
this document nor does It make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only tie used to identify Intel Products:
BITBUS, COMMputer, CREDIT, Data Pipeline, GENIUS, i,~, ICE, ICS, iDBp, lOIS, 12 1CE,
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intellgent Programming, Intellec, Intel/Ink, iOSp, IPDS, iRMX, ISBC, iSBX, iSDM, iSXM,
KEPROM, Library Manager, MCS, Megachassis, MICROMAINFRAME, MULTI BUS,
MULTICHANNEL, MULTI MODULE, OpeNET, Plug-A-Bubble, PROMPT, Promware,
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(

MDS IS an ordering code only and is not used as a product name or trademark. MDS') is a registered trademark of Mohawk Data
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* MULTIBUS is a patented Intel bus,

Additional copies of this manual or other Intel literature may be obtained from:
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© INTEL CORPORATION 1984

Table of Contents
CHAPTER 1
OVERVIEW
Introduction

1-1

CHAPTER 2
MCS®-80/85 MICROPROCESSORS
8080Al8080A-1/8080A-2, B-Bit N-Channel Microprocessor.. .. ...... .... ...... ....... . ....
2-1
8085AH/8085AH-2/8085AH-1 B-Bit HMOS Microprocessors .............................. 2-10
8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and Timer ....... 2-26
8185/8185-21024 x 8-Bit Static RAM for MC5-85 ........................................ 2-38
8205 High Speed 1 out of 8 Binary Decoder ............................................ 2-43
8224 Clock Generator and Driver for 8080A CPU ........................................ 2-48
8228/8238 System Controller and Bus Driver for 8080A CPU ............................. 2-53
8237A18237A-4/8237A-5 High Performance Programmable DMA Controller................ 2-57
8257/8257-5 Programmable DMA Controller............................................ 2-72
8259A18259A-2/8259A-8 Programmable Interrupt Controller.... .... .... .. .... ....... ..... 2-89
8755A18755A-2 16, 384-Bit EPROM with I/O ............................................ 2-107
AP-59 USing the 8259A Programmable Interrupt Controller ... : ........................... 2-118

CHAPTER 3
IAPX 86, 88, 186, 188 MICROPROCESSORS
iAPX 86/10 16-Bit HMOS Microprocessor...............................................
iAPX 186 High Integration 16-Bit Microprocessor.... .............. .... .. .. ......... .....
iAPX 88110 B-Bit HMOS Microprocessor .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iAPX 188 High Integration B-Bit Microprocessor .........................................
80898& 16-Bit HMOS I/O Processor ..................................................
8087/8087-218087-1 Numeric Data Coprocessor .........................................
80130/80130-2 iAPX 86/30,88/30.186/30.188/30 iRMX'· 86 Operating System Processors ....
80150/80150-2 iAPX 86/50.88/50, 186/50, 188/50 CP/M'-86 Operating System Processors ....
8282/8283 Octal Latch ...............................................................
8284A/8284A-1 Clock Generator and Driver for iAPX 86, 88 Processors ....................
828618287 Octal Bus Transceiver ......................................................
8288 Bus Controller for iAPX 86. 88 Processors .........................................
82188 Integrated Bus Controller for iAPX 86, 88, 186, 188 Processors ..._......... > • • • • • • • • •
8289/8289-1 Bus Arbiter ..............................................................
AP-67 8086 System Design ...........................................................
AP-123 Graphic CRT Design Using the Intel 8089 .......................................
AP-113 Getting Started with the Numeric Data Processor .................................
AP-143 Using the iAPX 86/20 Numeric Data Processor in a Small Business Gomputer .......
AP-144 Three Dimensional Graphics Application of the iAPX 86/20
Numeric Data Processor ......•......................................................
AP-186 Introduction to the 80186 ........................... : ..........................

3-1
3-25
3-79
3-106
3-161
3-175
3-198
3-220
3-232
3-237
3-245
3-250
3-257
3-274
3-285
3-348
3-420
3-481
3-504
3-543

CHAPTER 4
IAPX 286 MICROPROCESSORS
iAPX 286110 High Performance Microprocessor with Memory Management and Protection ..
4-1
80287 8Q-Bit HMOS Numeric Processor Extension ...................................... 4-54
82258 Advanced DMA Controller Architectural Overview ................................. 4-79
82284 Clock Generator and Ready Interface for iAPX 286 Processors ...................... 4-92
82288 Bus Controller for iAPX 286 Processors .......................................... 4-100
82289 Bus Arbiter for iAPX 286 Processor Family .......... ~ ............................ 4-118

'Cp/M is a Trademark of Digital Research. Inc.

iii

CHAPTER 5
MEMORY CONTROLLERS
DATA SHEETS
8202A Dynamic RAM Controller.................................................
8203 64K Dynamic RAM Controller ...................... ,.......................
8206/8206-2 Error Detection and Correction Unit .................... , . . .. . . .. . ...
8207 Dual-Port Dynamic RAM Controller ........................................
8208 Dynamic RAM Controller ............................'. .. . .. .. .. .. .. . .. . . ...
USERS MANUAL
Introduction ...................................................................
Programming the 8207 ........................................................
RAM Interface .................................................................
Microprocessor Interfaces ......................................................
8207 with ECC (8206) ..........................................................
Appendix ......................................................................
APPLICATION NOTES
AP-97A Interfacing Dynamic RAM to iAPX 86/88 Using the 8202A and 8203 ........
AP-141 8203/8206/2164A Memory Design ........................................
AP-167 Interfacing the 8207 Dynamic RAM Controller to the iAPX 186 .............
AP-168 Interfacing the 8207 Advanced Dynamic RAM Controller to the iAPX 286 ...
ARTICLE REPRINTS
AR-364 FAE News 1/84 "8208 with 186" ..........................................
AR-231 Dynamic RAM Controller Orchestrates Memory Systems ..................

5-1
5-15
5-30
5-51
5-98
5-117
5-118
5-123
5-132
5-140
5-143
5-147
5-183
5-189
5-194
5-201
5-212

-VOLUME2SUPPORT PERIPHERALS
DATA SHEETS
8231A Arithmetic Processing Unit .................................................
8253/8253-5 Programmable Interval Timer .........................................
8254 Programmable Interval Timer ................................................
82C54 CHMOS Programmable Interval Timer ......................................
8255A!8255A-5 Programmable Peripheral Interface .................................
82C55A CHMOS Programmable Peripheral Interface ...............................
8256AH Multifunction Microprocessor Support Controller ...........................
8279/8279-5 Programmable Keyboard/Display Interface .............................
APPLICATION NOTES
AP-153 Designing with the 8256 ..................................................
AP-183 8256AH Application Note .................................................
FLOPPY DISK CONTROLLERS
.
DATA SHEETS
8272A Single/Double Density Floppy Disk Controller ...............................
APPLICATION NOTES
AP-116 An Intelligent Data Base System Using the 8272 .............................
AP-121 Software Design and Implementation of Floppy Disk Systems .................
HARD DISK CONTROLLERS
DATA SHEETS
82062 Winchester Disk Controller .................................................
82064 Winchester Disk Controller with On-Chip Error Detection and Correction .......
UPI USERS MANUAL
Introduction .................................. ,., ............ , ...................
Functional Description ........... '................................................
Instruction Set ..................................................................
Single-Step, Programming, and Power-Down Modes ................................
System Operation .................................•..............................
Applications ....................................................................
AP-161 Complex Peripheral Control with the UPI-42 ................................
AP-90 An 8741A/8041A Digital Cassette Controller ..................................

iv

5-219
5-229
5-240
5-256
5-273
5-294
5-317
5-340
5-352
5-427

5-444
5-463
5-504

5-574
5-601
5-635
5-639
5-656
5-683
5-688
5-694
5-750
5-806

DATA SHEETS
8041A/8641 A/8741 A Universal Peripheral Interface 8-Bit Microcomputer ...............
8042/8742 Universal Peripheral Interface 8-Bit Microcomputer. . . . . . . . . . . . . . . . . . . . . . ..
8243 MCS-48 Input/Output Expander .............................................
APPLICATION NOTES
AP-182 Multimode Winchester Controller Using the 82062 ...........................
SYSTEM SUPPORT
ICE-42 8042 In-Circuit Emulator ..................................................
MCS-48 Diskette-Based Software Support Package .................................
iUP-200/iUP-201 Universal PROM Programmers ....................................

5-814
5-826
5-840
5-846
5-910
5-918
5-920

CHAPTER 6
DATA COMMUNICATIONS
INTRODUCTION
Intel Data Communications Family Overview....... .................. .......... .. ..
GLOBAL COMMUNICATIONS
DATA SHEETS
8251 A Programmable Communication Interface.. ........ ................ ...... ....
8273/8273-4 Programmable HDLC/SDLC Protocol Controller ........................
8274 Multi-Protocol Serial Controller (MPSC) ......................................
82530/82530-6 Serial Communications Controller (SCC) ............................
APPLICATION NOTES
AP-16 Using the 8251 Universal Synchronous/Asynchronous
ReceiveriTransmitter ...........................................................
AP-36 Using the 8273 SDLC/HDLC Protocol Controller ...........................
AP-134 Asynchronous Communications with the 8274 Multiple
Protocol Serial Controller .......................................................
AP-145 Synchronous Communications with the 8274 Multiple
Protocol Serial Controller .......................................................
AP-222 Asynchronous SDLC Communications with 82530 ........................
LOCAL AREA NETWORKS
DATA SHEETS
82501 Ethernet Serial Interface ..................................................
82C502 Ethernet Tranceiver Chip Data Sheet .....................................
82586 Local Area Network Coprocessor .........................................
82588 Personal Workstation Lan Control .........................................
ARTICLE REPRINTS
AR-345 Build a VLSI-Based Workstation for the Ethernet
Environment .......................•...........................................
AR-346 VLSI Solutions for Tiered Office Networks ............•...................
AR-342 Chips Support Two Local Area Networks .................................
OTHER DATA COMMUNICATIONS
DATA SHEETS
, 8291A GPIB Talker/Listener .....................................................
8292 GPIB Controller ...........................................................
8294A Data Encryption Unit .....................................................
APPLICATION NOTES
AP-66 Using the 8292 GPIB Controller ...........................................
AP-166 Using the 8291A GPIB Talker/Listener ....................................
ARTICLE REPRINTS
AR-208 SLI Transceiver Chips Complete GPIB Interface ..........................
AR-113 LSI Chips Ease Standard 488 Bus Interfacing .............................
TUTORIAL
Data Encryption Tutorial ........................................................

v

6-1
6-3
6-20
6-48
6-85

6-113
6-144
6-191
6-228
6-268

6-288
6-299
6-302
6-336

6-362
6-370
6-380

6-386
6-415
6-430
6-442
6-496
6-528
6-536
6-546

CHAPTER 7
ALPHANUMERIC TERMINAL CONTROLLERS
DATA SHEETS
8275H Programmable CRT Controller ........•............._. . . . . . . . . . . . . . . . . . . . .
8276H Small System CRT Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPLICATION NOTES
AP-62 A Low Cost CRT Terminal Using the 8275 . \. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ARTICLE REPRINTS
AR-178 A Low Cost CRT Terminal Does More with Less ...........................
GRAPHICS DISPLAY PRODUCTS
DATA SHEETS
82720 Graphics Display Controller ..............................................
ARTICLE REPRINTS
AR-255 Dedicated VLSI Chip Lightens Graphic Display
Design Load ....•.•........................ ; ...................................
AR-298 Graphics Chip Makes Low Cost High Resolution, Color
Displays Possible ..............................................................
TEXT PROCESSING PRODUCTS
DATA SHEETS
82730 Text Coprocessor ........................................................
82731 Video Interface Controller ................................................
ARTICLE REPRINTS
AR-305 Text Coprocessor Brings Quality to CRT Displays .........................
AR-297 VLSI Coprocessor Delivers High Quality Displays .........................
AR-296 Mighty Chips .•........................•................................

vi

7-1
7-25
7-42
7-84
7-91
7-128
7-136
7-143
7-187
7-20p
7-214
7-217

Numeric Index
80130/81030-2 iAPX 86/30,88/30,186/30,188/30 iRMX'· 86 Operating System Processors ...... 3-198
80150/80150-2 iAPX 86/50, 88/50, 186/50, 188/50 C/PM*-86 Operating System Processors ...... 3-220
80186 (iAPX 186) High Integration 16-Bit Microprocessor ................................. 3-25,3-543
80188 (iAPX 188) High Integration 8-Bit Microprocessor ....................................... 3-106
80286 (iAPX 286/10) High Performance Microprocessor with Memory Management
and Protection .......................................................................... 4-1
80287 80-Bit HMOS Numeric Processor Extension ............................................. 4-54
8041A/8641A/8741A Universal Peripheral Interface 8-Bit Microcomputer .......... 5-814,5-635,5-639
8042/8742 Universal Peripheral Interface 8-Bit Microcomputer ............. 5-826,5-635,5-639,5-910
8080A/8080A-1/8080A-2, 8-Bit N-Channel Microprocessor ....................................... 2-1
8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors .................................... 2-10
8086 (iAPX 86/10) 16-Bit HMOS Microprocessor .......................................... 3-1,3-285
8087/8087-2/8087-1 Numeric Data Coprocessor ..................... 3-175,3-420,3-481,3-504,6-362
8088 (iAPX 88/10) 8-Bit HMOS Microprocessor ................................................ 3-79
80898 & 16-Bit HMOS I/O Processor .................. : ................................ 3-161, 3-348
8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and Timer ........... 2-26
8185/8185-2 1024 x 8-Bit Static RAM for MCS®-85 .............................................. 2-38
8202A Dynamic RAM Controller .......................................................... 5-1, 5-147
8203 64K Dynamic RAM Controller ............................................... 5-15,5-147,5-183
8205 High Speed 1 out of 8 Binary Decoder .................................................... 2-43
8206/8206-2 Error Detection and Correction Unit ................................. 5-30,5-183,5-212
82062 Winchester Disk Controller ...................................................... 5-574,5-846
82064 Winchester Disk Controller with On-Chip Error Detection and Correction ............... 5-601
8207 Dual-Port Dynamic RAM Controller ............................ 5-51, 5-118, 5-123, 5-132, 5-140
5-143,5-183,5-189,5-194,5-212
8208 Dynamic RAM Controller .......................................................... 5-98, 5-201
82188 Integrated Bus Controller for iAPX 86, 88, 186, 188 Processors .......................... 3-257
8224 Clock Generator And Driver for 8080A CPU .............................................. 2-48
82258 Advanced DMA Controller Architectural Overview ....................................... 4-79
8228/8238 System Controller and Bus Driver for 8080A CPU ................................... 2-53
82284 Clock Generator and Ready Interface for iAPX 286 Processors ........................... 4-92
82288 Bus Controller for iAPX 286 Processors ................................................ 4-100
82289 Bus Arbiter for iAPX 286 Processor Family ............................................. 4-118
8231 A Arithmetic Processing Unit ............................................................ 5-219
8237 A/8237 A-4/8237 A-5 High Performance Programmable DMA Controller ..................... 2-57
8243 MCS-48 Input/Output Expander .................................................. 5-635,5-840
82501 Ethernet Serial Interface .................................................. 6-288, 6-362, 6-38'0
82C502 Ethernet Tranceiver Chip ............................................................. 6-299
8251 A Programmable Communication Interface ...........................•.............. 6-3,6-113
8253/8253-5 Programmable Interval Timer .................... '" .... '" ...................... 5-229
82530/82530-6 Serial Communications Controller (SCC) ................................. 6-85, 6-268

vii

8254 Programmable Interval Timer ........................................................... 5-240
82C54 CHMOS Programmable Interval Timer ....... '," ....................................... 5-256
8255A/8255A-5 Programmable Peripheral Interface ............................. " ....... 5-273, 7-84
82C55 CHMOS Programmable Peripheral Interface ........................................... 5-294
8256AH Multifunction Microprocessor Support Controller ....... " ............... 5-317, 5-352, 5-427
8257/8257-5 Programmable DMA Controller ................... '" ........................ , ..... 2-72
82586 Local Area Network Coprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-302, 6-362, 6-370, 6-380
82588 Personal Workstation Lan Control ...................................................... 6-336
8259A/8259A-2/8259A-8 Programmable Interrupt Controller .............................. 2-89, 2-118
8272A Single/Double Density Floppy Disk Controller ..................... 5-444,5-463,5-504,7-128
82720 Graphics Display Controller ........................... 7-91,7-128,7-136,7-206,7-214,7-217
8273/8273-4 Programmable HDLC/SDLC Protocol Controller ..................... 6-20,6-144,6-380
82730 Text Coprocessor .................................... 6-262,7-136,7-143,7-206, 7-214, 7-217
82731 Video Interface Controller ...................................................... .7-187,7-206
8274 Multi-Protocol Serial Controller (MPSC) ..............................,6-48,6-191,6-228,6-380
8275H Programm~ble CRT Controller ..................................................... 7-1, 7-42
8276H Small System CRT Controller ..................................................... 7-25, 7-84
8279/8279-5 Programmable Keyboard/Display Interface ...................................... 5-340
8282/8283 Octal Latch ....................................................................... 3-232
8284A/8284A-1 Clock Generator and Driver for iAPX 86, 88 Processors ........................ 3-327
, 8286/8287 Octal Bus Transceiver ............................................................. 3-245
8288 Bus Controller for iAPX 86, 88 Processors .......,.................................. 3-250,6-362
8289/8989-1 Bus Arbiter .............................................., ........................ 3-274
8291A GPIB Talker/Listener .............................................. 6-386,6-496,6-528,6-536
8292 GPIB Controller .................................................... 6-415,6-442,6-528,6-536
8294A Data Encryption Unit .................................................................. 6-430
8755A/8755A-2 16,384-Bit EPROM with I/O ................................................... 2-107

/

viii

j

Overview

1

, I

I

inter
INTRODUCTION

replacing numerous parts, microprocessor and peripheral
solutions can contribute dramatically to lower product
costs.

Intel microprocessors and peripherals provide a complete
solution in increasingly complex application environments. Quite often, a single peripheral device will replace
anywherefrom 20 to 100 TIL devices (and the associated
design time that goes with them).

HIGHER SYSTEM PERFORMANCE

, Intel microprocessors and peripherals provide the highest
system performance for the demands of today's (and
tomorrow's) microprocessor-based applications. For
example, the iAPX 286 CPU, with its on-chip memory
management and protection, offers the highest performance for multitasking, multiuser systems.

Built-in functions and a standard Intel microprocessor/
peripheral interface deliver very real time and performance advantages to the designer of microprocessorbaseq systems.
REDUCED TIME TO MARKET

HOW TO USE THE GUIDE

When you can purchase an off-the-shelf solution that
replaces a number of discrete devices, you're also replacing all the design, testing, and debug time that goes
with them.
'

The following application guide illustrates the range of
microprocessors and peripherals that can be used for the
applications in the vertical column on the left. The
peripherals are grouped by the 1/ 0 function they control:
CRT, datacommunication, universal (user programmable), mass storage dynAmic RAM controllers, and
CPU/bus support.

INCREASED RELIABILITY

At Intel, the rate offailure for devices is carefully tracked.
Highest reliability is a tangible goal that translates to
higher reliability, for your product, reduced downtime,
and reduced repair costs. And as more and more
functions are integrated on a single VLSI device, the
resulting system requires less power, produces less heat,
and requires fewer mechanical connections-again resulting in greater system reliability.

An "X" in a horizontal application row indicates apotential peripheral or CPU, depending upon the features
desired. For example, a conversational terminal could
use either of the three display controllers, depending
upon features like the number of characters per row or
font capability. A "Y" indicates a likely candidate, for
example, the 8272A Floppy Disk Controller in a small
business computer.

LOWER PRODUC~ COST

By minimizing design time, increasing reliability, and

The Intel microprocessor and peripherals family provides
a broad range of time-saving, high performance solutions.

1-1

POTENTIAL CANDIDATE X-TYPICAL CANDIDATE Y
DATACOMM

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Keyboards
MASS STORAGE
Hard Disk
Mini Winchester
Tape
Cassette
Floppy/Mini
COMMUNICATIONS
PBX
LANS
Modems
Bisync
SOLC/HOLC
Serial Back Plane
Central Office
Network Control
OFFICE/BUS
Copier/FAX
Word Processor
Typewriter
Elect. Mail
Transaction System
Data Entry
COMPUTERS
SM Bus Computer
PC
Portable PC
Home Computer

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Medical
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X

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Financial Transfer
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WORKSTATIONS
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MCS®-SO/S5
Microprocessors

2

8080A/8080A·1/8080A·2
8·BIT N.. CHANNEl MICROPROCESSOR
• TIL Drive Capability
• 2 /-'s ( - 1:1.3 /-'s, - 2:1.5 /-,s) Instruction
Cycle
• Powerful Problem Solving Instruction
Set

• 16·Bit Stack Pointer and Stack
Manipulation Instructions for Rapid
Switching of the Program Environment
• Decimal, Binary, and Double Precision
Arithmetic
• Ability to Provide Priority Vectored
Interrupts
• 612 Directly Addressed flO Pons
• Available in EXPRESS
- Standard Temperature Range

• 6 General Purpose Registers and an
Accumulator
• 16·Bit Program Counter for Directly
Addressing up to 64K Bytes of
Memory

The Intel"' aOaOA is a complete a-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip using
Intel's n-channel silicon gate MOS process. This offers the user a high performance solution to control and processing
apQlications.
The aOaOA contains 6 a-bit general purpose working registers and an accumulator. The 6 general purpose registers may be
addressed individually or in pairs providing both single and double precision operators. Arithmetic and logical instructions
set or reset 4 testable flags. A fifth flag provides decimal arithmetic operation.
The aOaOA has an external stack feature wherein any portion of memory may be used as a last in/first out stack to
store/retrieve the contents of the accumulator, flags, program counter, and all of the 6 general purpose registers. The 16-bit
stack pointer controls the addressing,of this external stack. This stack gives the aOaOA the ability to easily handle multiple
level priority interrupts by rapidly storing and restoring processor status. It also provides almost unlimited subroutine
nesting.
This microprocessor has been designed to simplify systems design. Separate 16-line address and a-line bidirectional data
busses are used to facilitate easy interface to memor" and I/O. Signals to control the interface to memory and 110 are
provided directly by the aOaOA. Ultimate control of the address and data busses resides with the HOLD signal. It provides
the ability to suspend processor operation and force the address and data busses into a high impedance state. This permits
OR-tying these busses with other controlling devices for (DMA) direct memory access or multi-processor operation.
NOTE:

The 8080A is functionally and electrically compatible with the Intel"' 8080.

0,°0
&IDIRECTIONAl
DATA BUS

'10

GNO

8080A
RESET
HOLD

INT

SYNC
'5V

Figure 1. Block Diagram

40
3.
3.
37
36
35
34
33
32
31
30
2'
2.
27
26
25
24
23
22

2'

..'.
'3

.,"

+12V

Ao
WAIT
READY

"HLDA

Figure 2. Pin Configuration

2-1

8080AI8080A·118080A·2

Table 1. Pin Description
Symbol

Type

Name and Function

A15.AO

0

Address Bus: The address bus provides the address to memory (up to 64K a-bit words) or denotes the I/O
device number for up to 256 Input and 256 output devices Ao IS the least significant address bit.

DrDo

I/O

Data Bus: The data bus provides bl-dlrectlonal communication betweeen the CPU, memory, and I/O
devices for Instructions and data transfers. Also, dUring the first clock cycle of each machine cycle, the
aOaOA outputs a status word on the data bus that describes the current macHine cycle. Do IS the least
significant bit.

SYNC

0

Synchronizing Signal: The SYNC pin provides a signal to indicate the beginning of each machine cycle

DBIN

0

Data Bus In: The DBIN signal Indicates to external circUits that the data bus IS In the input mode. This
signal should be used to enable the gating of data onto the aOaOA data bus from memory or I/O

READY

I

R!'ady: The READY signal indicates to the aOaOA that valid memory or Input data is available on the aOaOA
data bus This signal is used to synchronize the CPU With slower memory or I/O devices If after sending
an address out the aOaOA does not receive a READY Input, the aOaOAw11i enter a WAITstate for as long as
the READY line IS low. READY can also be used to Single step the CPU.

WAIT

0

Wait: The WAIT signal acknowledges that the CPU IS In a WAIT state.

WR

0

Write: The WR signal IS used for memory WRITE or I/O output control. The data on the data bus IS slable
while the WR signal IS active low (WR ~ 0).

HOLD

,I

Hold: The HOLD signal requests the CPU to enter the HOLD state. The HOLD state allows an external
device to gain control of the aOaOA address and data bus as soon !\S the 8080A has completed its use of
these busses for the current machine cycle. It IS recognized under the following conditions:
• the CPU is in the HALT srate.
• the CPU IS In the T2 or TW state and the READY signal is active. As a result of entering the HOLD state
the CPU ADDRESS BUS (A1S-Ao) and DATA BUS (Dr Do) will be In their high Impedance state. The CPU
acknowledges ItS state With the HOLD ACKNOWLEDGE (HLDA) pin

HLDA

0

Hold Acknowledge: The HLDA signal appears in response to the HOLD signal and indicates that the data
and address bus will go to the high impedance state. The HLDA signal begins at·
• T3 for READ memory or input.
\
• The Clock Period following T3 for WRITE- memory or OUTPUT operation.
In either case, the HLDA signal appears after the rising edge of <1>2

INTE

0

Interrupt Enable: Indicates the content of the Internal Interrupt enable flip/flop This flip/flop may be set
or reset by the Enable and Disable In\;rrupt instructions and inhibits interrupts from being accepted by
tbe CPU when It IS reset It IS automatically reset (disabling further interrupts) at time T1 of the instruction
fetch cycle (M1) when an Interrupt is accepted and is also reset by the RESET signal.

INT

I

Interrupt Request: The CPU recognizes an interrupt request on this line at the end of the current
Instruction or while halted If the CPU IS In the HOLD state or if the Interrupt Enable flip/flop is reset it will
not honor the request

RESET 1

I

Reset: While the RESET signal IS activated, the content of the'program counter is cleared. After RESET,
the program will start at location 0 In memory. The INTE and HLDA flip/flops are also reset. Note that the
flags, accumulator, stack pOinter, and registers are not cleared.

Vss

Ground: Reference

VDD

Power: +12 ±5% Volts

Vee

Power: +5 ±5% Volts.

Vss

Power: -5 ±5% Volts.

<111, <1>2

Clock Phases: 2 externalfy supplied clock phases. (non TTL compatible)

2-2

inter

8080Al8080A·1/8080A·2

ABSOLUTE MAXIMUM RATINGS·

"NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absoluta maximum rating conditions for extended periods may affect
device reliability.

Temperature Under Bias. . . . . . . . . .. . dOc to +70° C
Storage Temperature . . . . . . . . . . . . . -65°C to +150°C
All Input or Output Voltages
With Respect to Vee . . . . . . . . . . . -0.3V to +20V
Vcc , VOO and Vss With Respect to Vee
-0.3V to +20V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 1.5W

D.C. CHARACTERISTICS

(TA = O"C to 70"C, VOO = +12V ±5%,
VCC = +5V ±5%, Vee = -5V ±5%, Vss =OV; unless otherwise noted)

Symbol

Parameter

Typ.

Min.

Max.

Unit

Vss+o.8

V

VILC

Clock Input Low Voltage

VIHC

Clock Input High Voltage

9.0

Vo o +l

V

VIL

Input Low Voltage

Vss-l

Vss+0.8

V

VIH

Input High Voltage

3.3

Vcc+l

V

VOL

Output Low Voltage

VOH

Output High Voltage

Vss-l

0.45

V

} IOL = 1.9mA on all outputs,
IoH =-150~.

V

3.7"

Test Condition

loe(AV)

Avg. Power Supply Current (Voo)

40

70

mA

ICC (AV)

Avg. Power Supply Current (Vcc)

60

80

mA

.01

}O.....

';M

T Cy '" .48 J.Lsec

IBe(AV)

Avg. Power Supply Current (V Be )

1

mA

IlL

Input Leakage

±10

J.LA

Vss .;;;; VIN .;;;; Vcc

ICL

Clock Leakage

±10

J.LA

Vss .;;;; VCLOCK .;;;; Voo

IOL[2]

Data Bus Leakage in Input Mode

-100
-2.0

J.LA
mA

Vss ';;;;VIN ';;;;VSS +0.8V

+10
-100

J.LA

IFL

Address and Data Bus Leakage
During HOLD

VSS+0.8V';;;;VIN ';;;;VCC
VAOOR/OATA = Vcc
V AOOR/OATA = Vss + 0.45V

,.
CAPACITANCE

(TA = 25°C, VCC = VOO =VSS = OV, Vee = -5V)
Typ.

Max.

Unit

C",

Clock Capacitance

17

25

pf

fc = 1 MHz

C IN

I nput Capacitance

6

10

pf

Unmeasured Pins

COUT

Output Capacitance

10

20

pf

Returned to Vss

Symbol

Parameter

Test Condition

NOTES:
1. The RESET SIgnal must be active for a mInimum of 3 clock cycles.
2. 2 +'<1>2 + tf2 + t02 + trl ;;. 480 ns ( - 1:320
ns, - 2:380 ns).

J

TYPICAL L> OUTPUT DELAY VS. L> CAPACITANCE

-.
----+---- -- -.

+20

'FO

,.
c

~~

~'5-AO

~0

..

::>

~

-~

0,.°0

+10

::>
0

-10

 CSPEC, subtract .3nsipF
(from modified delay) If CL < CSPEC.
4. tAW = 2 tCY- t03 - tr2 - 140 ns ( - 1:110 ns, - 2:130 ns).
S. tow = tCY - t03 - tr2 - 170 ns ( - 1:1S0 ns, - 2:170 ns) .
6. If not HLDA, two = tWA = t03 + tr2 + 10 ns. If HLDA, two
= tWA = tWF'
7. tHF = too + tr2 -SO ns).
B. tWF = too + tr2 - 10ns.
9. Data In must be stable for this period during DBIN T3.
Both tOSl and tOS2 must be satisfied.
10. Ready signal must be stable for this period during T2 or T w.
(Must be externally synchronized.)
11. Hold Signal must be stable for this period during T2 or TW
when entering hold mode, and during T3, T4, T 5 and TWH
when in hold mode. (External synchronization is not required.)
12. Interrupt signal must be stable during this period of the last
clock cycle of any instruction in order to be recognized on the
following instruction. (External synchronization is not re,qulred.)
13. this timing diagram shows timing relationships only; it does
not represent any specific machine cycle.

READY

WAIT

HOLD

~

HLDA

INT

.....

INTE

2-6

inter

SOSOAISOSOA·1/&OSOA·2

INSTRUCTION SET
The accumulator group instructions include arithmetic and
logical operators with direct, indirect, and immediate addressing modes_

increment and decrement memory, the six general registers
and the accumulator is provided as well as extended increment and decrement instructions to operate on the register
pairs and stack pointer. Further capability is provided by
the ability to rotate the accumulator I!lft or right through
or around the carry bit.

Move, load, and store instruction groups provide the ability
to move either 8 or 16 bits of data between memory, the
six working registers and the accumulator using direct, indirect, and immediate addressing modes.

Input and output may be accomplished using memory addresses as I/O ports or the directly addressed I/O provided
for in the 8080A instruction set.

The ability to branch to different portions of the program
is provided with jump, jump conditional, and computed
jumps. Also the ability to call to and return from subroutines is provided both conditionally and unconditionally.
The RESTART (or single byte call instruction) is useful for
interrupt vector operation.

The following special instruction group completes the 8080A
instruction set: the NOP instruction, HALT to stop processor execution and the DAA instructions provide decimal
arithmetic capability. STC allows the carry flag to be directly set, and the CMC instruction allows it to be complemented. CMA complements the contents of the accumulator
and XCHG exchanges the contents of two 16-bit register
pairs directly.

Double precision operators such as stack manipulation and
double add instructions extend both the arithmetic and
interrupt handling capability of the 8080A. The ability to

Data and Instruction Formats
Data in the 8080A is stored in the form of 8-bit binary integers. All
same format.

ID7

d~ta

transfers to the system data bus will be in the

D6 D5 D4 D3 D2 D, Dol
DATA WORD

The program instructions may be one, two, or three bytes in length. MUltiple byte instructions must be stored
in successive words in program memory. The instruction formats then depend on the particular operation
executed.
One Byte Instructions

I D7

TYPICAL INSTRUCTIONS

D6 D5 D4 D3 D2 D, Do

I OP CODE

Register to register, memory reference, arithmetic or logical, rotate,
return, push, pop, enable or disable
Interrupt instructions

Two Byte Instructions

I D7

I

D6 D5 D4 D3 D2 D, Do

D7 D6 D5 D4 D3 D2 D, Do

I OPCODE
I OPERAND

Immediate mode or I/O instructions

Three Byte Instructions

ID7 D6 D5 D4 D3 D2 D,
I D7 D6 D5 D4 D3 D2 D,
I D7 D6 D5 D4 D3 D2 D,

I OPCODE
Do I LOWADDRESSOR OPERAND 1
Do I HIGH ADDRESSOR OPERAND 2
DO

Jump, call or direct load and store
instructions

For the 8080A a logic "1" is defined as a high level and a logic "0" is defined as a low level.

2-7

8080Al8080A·118080A·2
Table 2. Instruction Set Summary
Instruction Code [1]
Mnemonic 0] 06 05 04 D:3 D:1 01 DO
MOvE, LOAD, AND STORE
MOVr1,r2
0 1 0 0 0
MOVM,r
0 1 1 1 0

S
S

S
S

S
S

MOVr,M

0

1

0

0

0

1

1

0

MVlr

0

0

0

0

0

1

1

0

MVIM

0

0

1

1

0

1

1

0

LXI B

0

0

0

0

0

0

0

1

LXI 0

0

0

0

1

0

0

0

1

LXI H

0

0

1

0

0

0

0

1

STAXB
STAXO
LOAX B
LOAXO
STA'
LOA
SHLO
LHLO
XCHG

0
0
0
0
0
0
0
0
1

0
0
0
0
0
0
0
0
1

0
0
0
0
1
1
1
1
1

0
1
0
1
1
1
0
0
0

0
0
1
1
0
1
0
1
1

0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1

STACKOPS
1
PUSH B

1

0

0

0

1

0

1

PUSH 0

1

1

0

1

0

1

0

1

PUSH H

1

1

1

0

0, 1

0

1

PUSH
PSW
POPB

1

1

1

1

0

1

0

1

1

1

0

0

0

0

0

1

POP 0

1

1

0

1

0

0

0

1

POPH

1

1

1

0

0

0

0

1

POPPSW

1

1

1

1

0

0

0

1

XTHL

1

1

1

0

0

0

1

1

SPHL
LXISP

1
0

1
0

1
1

1
f

1
0

0
0

0
0

1
1

INXSP
OCXSP

0
0

0
0

1
1

1
1

0
1

0
0

1
1

1
1

JUMP
JMP
JC
JNC
JZ
JNZ
JP
JM
JPE

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

0
0
0
0
0
1
1
1

0
1
1
0
0
1
1
0'

0
1
0
1
0
0
1
1

0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

1
0
0
0
0
0
0
0

Operations
Description
Move register to register
Move register to
memory
Move memory to register
Move immediate re9j5ter
Move immediate
memory
Load immediate register
Pair B & C
Load Immediate register
Pair 0& E
Load immediate register
PalrH&L
Store A Indirect
Store A Indirect
Load A Indirect
Load A indirect
Store A direct
Load A direct
Store H & L direct
Load H & L direct
Exchange 0 & E, H & L
Registers

Clock
Cycle.
[2]

Instruction Code [1]

MnemoniC 0] 06 Os 04 03 02 01

5

JPO
PCHL

7

CALL

7

CALL
CC
CNC

7

CZ

10
10
7
7
7
7
13
13
16
16

4

Push register Pair B &
C on stack
Push register PaH 0 &
E on stack
Push register Pair ~ &
L on stack
Push A and Flags
on stack
Pop register Pair B &
C off stack
Pop register Pair 0 &
E off stack
Pop register Pal r H &
L off stack
Pop A and Flags
off stack
Exchange top of
stack, H & L
H & L to stack pOinter
Load Immediate stack
pOinter
Increment stack pointer
Decrement stack
pointer

11

Jump unconditional
Jump on carry
Jump on no carry
Jump on zero
Jump on no zero
Jump on positive
Jump on minus
Jump on parity even

10
10
10
10
10
10
10
10

1
1

1
1

1
1

0
0

0
1

0
0

1
0

1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1

0
0
0
0
0
1
1
1
1

0
1
1
0
0
1
1
0
0

1
1
0
1
0
0
1
1
0

1
1
1
1
l'
1
1
1
1

0
0
0
0
0
0
0
0

0
0
0
0
0
1
1
1
1

0
1
1
0
0
1
1
0
0

1
1
0
1
0
0
1
1
0

0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0

A A A 1
DECREMENT
0 0 0 1
0 0 0 1
1 1 0 1
1 1 0 1
0 0 0 0

1

1

Restart

0
0
0
0
1

0
1
0
1
1

Increment register
Decrement registe~
Increment memory
Decrement memory
Increment B & C
registers
Increment 0 & E
registers
Increment H & L
registers
Decrement B & C
Decrement D & E
Decrement H & L

CNZ
CP
CM
CPE
CPO
RETURN
1 1
RET
RC
1 1
RNC
1 1
1 1
RZ
RNZ
1 1
RP
1 1
RM
1 1
RPE
1 1
RPO
1 1
RESTART
RST
1 1
INCREMENT AND
INRr
0 0
OCRr
0 0
INRM
0 0
OCRM
0 0
INXB
0 0

10
10

11

0
1

1
0
0
0
0
0
0
0
O. 0
1
0
0
0
0
0
0
0
0

18
5
10

2-8

5

Return
Return on carry
Retu rn on no carry
Return on zero
Return on no zero
Return on positive
Return on minus
Return on parity even
Return on panty odd

10
5111
5111
5111
5111
5111
5111
5111
5/11

0

0

1

0

0

1

1

0

0

1

0

0

0

1

1

OCXB
OCXO
OCXH
ADD
AOOr
AOCr

0
0
0

0
0
0

0
0

i

0
1
0

1
1
1

0
0
0

1
1
1

1
1
1

1 '0
1 0

0
0

0
0

0
1

S

S S Add register to A

S

S

S

AOOM
AOCM

1
1

0
0

0
0

0
0

0
1

1
1

1
1

0
0

AOI
ACI

1
1

1
1

0
0

0
0

0
1

1
1

1
1

0
0

OAOB
DADO
OAOH
OAOSP

0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

1
1
1
1

Q 0

1
1
1
1

0

10

17
11/17
11/17
11/17
11/17
11/17
11/17
11/17
11/17

0

5

5

[2]

unconditional
on carry
on no carry
on zero
on no zero
on positive
on minus
on parity even
on parity odd

INXH
10

10

Call
Call
Call
Call
Call
Call
Call
Call
Call

INXO
11

10

Jump on parity odd
H & L to program
counter

Clock
Cycle.

I

11

10

Operations
Description

Do

0
0
0

0
0
0

Add register to A
With carry
Add memory to A
Add memory to A
With carry
Add Immediate to A
Add immediate to A
With carry
AddB&CtoH&L
AddO&EtoH&L
AddH&LtoH&L
Add stack pointer to
H&L

11

5
5
10
10

5
5
5
5
5
'5
4
4
7
7
7
7
10
10
10
10

inter

8080Al8080A·1/8080A·2
SUm....ry of Proce_r Instructions (Cont.)

Mnemonic

D7

Instruction Code [1]
Ds Ds D4 OJ D2 Dl DO

Clock

Clock
Cycl.s
[2]

Mnemonic

D7

Instruction Code [1 )
De Ds D4 OJ II:! Dl Dc

Cycle.

Operetlons
Description

121

ROTATE

SUBTRACT
SUBr
1 0

0

1

0

SBBr

1

0

0

1

1

SUBM

1

0

0

1

0

SBBM

1

0

0

1

1

SUI

1

1

0

1

0

SBI

1

1

0

1

1

LOGICAL
ANAr
XRAr

1
1

0
0

1
1

0

0
1

ORAr
CMPr
ANAM
XRAM

1
1
1
1

0

1
1

0

0
0

1
1
1
1

0
0

0

ORAM
CMPM

1
1

0
0

1
1

1
1

0

ANI
XRI

1
1

1
1

1
1

0
0

0

ORI
CPI

1
1

1
1

1
1

1
1

0

0

Operations
Description

0

1
1

1

1

1

S S S Subtract regIster
from A
S S S Subtract regIster from
A WIth borrow
1 1 0 Subtrect memory
from A
1 1 0 Subtract memory from
Awlth borrow
1 1 0 Subtract ImmedIate
from A
1 1 0 Subtract immedIate
from A WIth borrow
S S S And regIster with A
S S S ExcltJsive Or register
wIth A
S S S Or regIster WIth A
S S S Compare regIster WIth A
1 1 0 And memory WIth A
1 1 0 ExclUSive Or memory
wIth A
1 1 0 Or memory WIth A
1 1 0 Compare memory WIth
A
1 1 0 And Immediate With A
1 1 0 ExclUSive Or Immediate
wIth A
1 1 0 Or ImmedIate with A
1 1 0 Compare ImmedIate
wIth A

Rotate A lell
Rotate A roght
Rotate A lell through
carry
Rotate A right through
carry

4
4
4

1
1
1
1

Complement A
Set carry
Complement carry
DeCImal adlust A

4
4
4
4

1
1

1
1

Input
Output

0 1
0 1
0 0
1 1

1
1
0

Enable Interrupts
Disable Interrupt
No-operatlDn
Halt

RLC
RRC
RAL

0

0
0
0

0
0
0

0
0
1

0

4

0

1
1
1

1
1
1

1
1
1

7

RAR

0

0

0

1

1

1

1

1

7

SPECIALS
0 0 1
CMA
STC
0 0 1
0 0 1
CMC
OM
0 0 1
INPUT/OUTPUT
IN
1 1 0
1 1 0
OUT
CONTROL
1 1 1
EI
1 1 1
01
0, 0 0
NOP
HLT
0 1 1

0
1
1
0

1
0
1
0

1
1
1
1

1
1
1
1

1
1

1

0

0

0

1
0
0

4

7
7

4
4

4
4

7
7
7
7
7
7
7
7

NOTES:
1 DOD orSSS' B~OOO, C~OOl, D~OlO, E-Oll , H~lOO, L~lOl, Memory~llO, A~111.
2. Two possIble cycle times (6112) Indicate InstructIon cycles dependent on condItion flags.
'All mnemonIcs copyroght Clntel Corporallon 19n

2-9

0
0

1
1
0
1

1

0

0

4

10
10
4
4
4

..

7

SOSSAH/SOSSAH-2/S0SSAH-1
8-BIT HMOS MICROPROCESSORS
• Single + 5V Power Supply with 10%
Voltage Margins

• On-hhiP System Controller; Advanced
Cycle Status Information Available for
Large System Control
• Four Vectored Interrupt Inputs (One is
Non-Maskable) Plus an
SOSOA-Compatible Interrupt
• Serial In/Serial Out Port
• Decimal, Binary and Double Precision
Arithmetic
• Direct Addressing Capability to 64K
Bytes of Memory
• Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range

• 3 MHz, 5 MHz and 6 MHz Selections
Available
• 20% Lower Power Consumption than
SOS5A for 3 MHz and 5 MHz
• 1.3 JLS Instruction Cycle (SOS5AH); O.S
JLS (SOS5AH-2); 0.67 JLs (SOS5AH-1)
• 100% Compatible with SOS5A
• 100% Software Compatible with SOSOA
• On-Chip Clock Generator (with
External Crystal, LC or RC Network)

The Intel® 8085AH is a complete 8 bit parallel Central Processing Unit (CPU) implemented in N-channel, depletion
load, silicon gate technology (HMOS). Its instruction set is 100% software compatible with the 8080A microprocessor, and it is designed to improve the present 8080A:s performance by higher system speed. Its high level of system
integration allows a minimum system ofthree IC's [8085AH (CPU), 8156H (RAM/IO) and 8755A (EPROM/IO)] while
maintaining total system expandability. The 8085AH-2 and 8085AH-1 are faster versions of the 8085 AH.
The 8085AH incorporates all of the features that the 8224 (clock generator) and 8228 (system controller)
provided for the 8080A, thereby offering a high level of system integration.
The 8085AH uses a multiplexed data bus. The address is split between the 8 bit address bus and the 8 bit data bus.
The on-chip address latches of 8155H/8156H/8755A memory products allow a direct interface with the 8085AH.

I

i"NTA

Vee
RESET OUT

SOD
SID

*: :~: ,:
REG

REG

STACK POINTER

1161

PROGRAM COUNTER

11$1

}REGISTER
ARRAV

11~1

HOLD
HLDA
elK (OUT~
RESET IN

READY
101M

5,

AD
ViR

lNTA

ALE

ADo
AD,

So
A15
A14
A13
A12
A11

AD2
AD3
AD,
ADS

INCREMENTERIOECREMENTER

AOORESS LATCH

RST 75
RST 65
RST 5 5
lNTR

3

AlO
A,
A8

AD7-ADo

AODRESSIOATA BUS

Figure 1. BOB5AH CPU Functional Block Diagram

Figure 2. BOB5AH Pin
Configuration

Intel Corporation Assumes No Responsibllty for the Use of Any Circuitry Other Than Circuitry Embodied In an Intel Product. No Other Circuit Patent lIcenses ale Implied

·INTEL CORPORATION. 1981

2-10

intJ

8085AH/8085AH-218085AH-1

r--::---;--;-_r=----._ _:-:-_---,--:-_ _--=T..:8..:b.:.:'e:....1..:.:....;Pln Description
Symbol
lYpe
READY

I

Ready: If READY is high during a
read or wrote cycle, It indicates that
the memory or peropheralls ready to
send or receive data. If READY is
low, the cpu Will walt an Integral
number of clock cycles for READY
to go high before completing the
read or wrote cycle. READY must
conform to specified setup and hold
times.

HOLD

I

Hold: Indicates that another master
IS requesting the use of the address
and data buses. The cpu, upon
receiving the hold request, will
relinquish the use of the bus as
soon as the completion of the current bus transfer Internal processIng can continue. The processor
can regain the bus only after the
HOLD IS removed. When the HOLD
IS acknowledged, the Address,
Data RD, WR, and 101M lines are
3-stated

HLDA

0

Hold Acknowledge: Indicates that
the cpu has received the HOLD request and that It will relinquish the
bus In the next clock cycle. HLDA
goes low after the Hold request IS
removed. The cpu takes the bus one
half clock cycle after HLDA goes
low.

INTR

I

Interrupt Request: Is used as a
general purpose Interrupt. It is
sampled only during the next to the
last clock cycle of an instruction
and during Hold and Halt states. If It
IS active, the Program Counter (PC)
will be I~ited from Incrementing
and an INTA will be Issued. During
this cycle a RESTART or CALL instruction can be inserted to Jump to
the Interrupt service routine. The
INTR IS enabled and disabled by
software It IS disabled by Reset and
immediately after an interrupt IS accepted

INTA

0

Interrupt Acknowledge: Is used InsteaE..,of (and has the same timing
as) RD during the Instruction cycle
after an INTR IS accepted. It can be·
used to activate an 8259A Interrupt
chip or some other Interrupt port.

RST 5.5
RST 6.5
RST 7.5

I

Restart Interrupts: These three Inputs have the same timing as INTR
except they cause an internal
RESTART to be automatically
Inserted.

(

2-11

Name and Funcllon

The priority of these interrupts IS
ordered as shown In Table 2. These
interrupts have a higher priority
than INTR. In addition, they may be
indiVidually masked out using the
SIM instruction.

intJ

8085AH/8085AH-2/8085AH-1

Table 1. Pin Description (Continued)
Symbol

Name and Function

Type

Name and Function

Symbol

lYpe

TRAP

I

Trap:' Trap interrupt IS a non·
maskable RESTART interrupt. It is
recognized at the same time as
INTR or RST 5.5·7.5. It is unaffected
by any mask or Interrupt Enable. It
has the highest priority of any interrupt. (See Table 2.)

RESET OUT

0

Reset Out: Reset Out Indicates cpu
is being reset. Can be used
as a system reset. The signal IS
synchronized to the processor
clock and lasts an.integral number
of clock periods.

XI, X2

I

RE~ETIN

I

R••• t In: Sets the Program
Counter to zero and resefs the Inter·
rupt Enable and HlDA flip-flops.
The data and address buses and the
control lines are 3-stated during
RESET and because of the asyn·
chronous nature of RESET, the processor's internal registers and flags
may be altered by RESET with unpredictable results. RESET IN is a
Schmitt·triggered input, allowing
connection to an R-C network for
power-on RESET delay (see Figure
3). Upon power·up, RESET IN must
remain low for at least 10 ms after
minimum Vee has been reached.
For proper reset operation after the
power-up duration, RESET IN
should be kept Iowa minimum of
three clock periods. The CPU is held
in the reset condition as long as
RESET IN is applied.

XI and X2: Are connected to a
crystal, le, or RC network to drive
the internal clock generator. XI can
also be an external clock input from
a logic gate. The input frequency is
divided by 2 to give the processor's
internal operating frequency.

ClK

0

Clock: Clock output for use as a sys·
tern clock. The period of ClK is
tWice the X1, X2 input period.

SID

I

Serial Input Data line: The data on
thiS line is loaded Into accumulator
bit 7 whenever a RIM instruction IS
executed.

SOD

0

Serial Output Data Line: The output SOD IS set or reset as specifIed
by the SIM instruction

I,

i

Vee

Power: +5 volt supply.

Vss

Ground: Reference.

Table 2. Interrupt Priority, Restart Address, and Sensitivity

Name

Priority

Address Branched To (1)
When Interrupt Occurs

Type Trigger

1

24H

RST 7.5

2

3CH

Rising edge (latched).

RST 6.5

3

34H

High level until sampled.

RST 5.5

4

2CH

High level until sampled.

INTR

5

See Note (21

High level until sampled.

TRAP

Rising edge AND high level until sampled.

NOTES:
1. The processor pushes the PC on the stack before branching to the Indicated address.
2. The address branched to depends on the instruction provided to the cpu when the Interrupt IS acknowledged.

VecO

L~

c,

f

TYPICAL POWER.()N RESET RC VAWES'

I~

R,
C,

~75Kn

~1.,F

"VAWES MAY HAVE TOVARY DUE TO
APPLIED POWER SUPPLY RAMP UP TIME.

Figure 3. Power-On Reset Circuit
2-12

intJ

8085AH/8085AH-218085AH-1

FUNCTIONAL DESCRIPTION

The· three maskable interrupts cause the internal
execution of RESTART (saving the program counter
in the stack and branching to the RESTART address)
ifthe interrupts are enabled and ifthe interrupt mask
is not set. The nonrriaskable TRAP causes the internal execution of a RESTART vector independent
of the state of the interrupt enable or masks. (See
Table 2.)

The 8085AH is a complete 8-bit parallel central processor. It is designed with N-channel, depletion load,
silicon gate technology (HMOS), and requires a single
+5 volt supply. Its basic clock speed is 3 MHz (8085AH),
5 MHz {8085AH-2), or6 MHz (8085AH-1), thus improving on the present 8080A's performance with higher
system speed. Also it is designed to fit into a minimum
system of three IC's: The CPU (8085AH), a RAM/IO
(8156H), and an EPROM/IO chip (8755A).

There are two different types of inputs in the restart
interrupts. RST 5.5 and RST 6.5 are high levelsensitive like INTR (and INT on the 8080) and are
recognized with the same timing as INTR. RST 7.5 is
rising edge-sensitive.

The 8085AH has twelve addressable 8-bit registers.
Four of them can function only as two 16-bit register
pairs. Six others can be used interchangeably as
8-bit registers or as 16-bit register pairs. The 8085AH
register set is as follows:
Mnemonic

Register

Contents

ACC orA
PC
BC,DE,HL

Accumulator
Program Counter
General-Purpose
Registers; data
pointer (HL)
Stack Pointer
Flag Register

8 bits
16-bit address
8 bits x 6 or
16 bits x 3

SP
Flags or F

For RST 7.5, only a pulse is required to set an internal flip-flop which generates the internal interrupt
request (a normally high level signal with a low
going pulse is recommended for highest system
noise immunity). The RST 7.5 request flip-flop
remains set until the request is serviced. Then
it is reset automatically. This flip-flop may also be
reset by using the SIM instruction or by issuing a
RESET IN to the 8085AH. The RST 7.5 internal flipflop will be set by a pulse on the RST 7.5 pin even
when the RST 7.5 interrupt is masked out.

16-bit address
5 flags (8-bit space)

The status of the three RST interrupt masks can only
be affected by the SIM instruction and RESET IN.
'(See SIM, Chapter 5 of the MCS-80/85 User's
ManuaL)

The 8085AH uses a multiplexed Data Bus. The
address is split between the higher 8-bit Address
Bus and the lower 8-bit Address/Data Bus. During
the first T state (clock cycle) of a machine cycle the
low order address is sent out on the Address/Data
bus. These lower 8 bits may be latched externally by
the Address Latch Enable signal (ALE). During the
rest of the machine cycle the data bus is used for
memory or I/O data.

The interrupts are arranged in a fixed priority that
determines which interrupt is to be recognized if
more than one is pending as follows: TRAPhighest priority, RST 7.5, RST 6.5, RST 5.5, INTRlowest priority. This priority scheme does not take
into account the priority of aroutine that was started
by a higher priority interrupt. RST 5.5 can interrupt
an RST 7.5 routine if the interrupts are re-enabled
before the end of the RST 7.5 routine.

The 8085AH provides Fm, WR, So, 51, and 10/M
signals for bus control. An Interrupt Acknowledge
signal (INTA) is-also provided. HOLD and all Interrupts are synchronized with the processor's internal
clock. The 8085AH also provides Serial Input Data
(SID) and Serial Output Data (SOD) lines for simple
serial interface.

The TRAP interrupt is useful for catastrophic events
such as power failure or bus error. The TRAP input is
recognized just as any other interrupt but has the
highest priority. It is not affected by any flag or mask.
The TRAP input is both edge and level sensitive. The
TRAP input must go high and remain high until it is
acknowledged. It will not be recognized again until it
goes low, then high again. This avoids any false
triggering due to noise or logic glitches. Figure 4
illustrates the TRAP interrupt request circuitry
within the 8085AH. Note that the servicing of any
interrupt (TRAP, RST 7.5, RST 6.5, RST 5.5, INTR)
disables all future interrupts (except TRAPs) until an
EI instruction is executed.

In addition to these features, the 8085AH has three
maskable, vector interrupt pins, one nonmaskable
TRAP interrupt, and a bus vectored interrupt, INTR.

INTERRUPT AND SERIAL I/O
The 8085AH has 5 interrupt inputs: INTR, RST 5.5,
RST 6.5, RST 7.5, and TRAP. INTR is identical in
function to the 8080A INT. Each of the three RESTART inputs, 5.5, 6.5, and 7.5,has a programmable
mask. TRAP is also a RESTART interrupt but it is
nonmaskable.
2-13

I

inter

SOS5AH/SOS5AH-2!SOS5AH-1

,

Parallel resonance at twice the clock frequency
desired
CL (load capacitance) .;; 30 pF
Cs (shunt capacitance) .;; 7 pF
Rs (equivalent shunt resistance) .;; 75 Ohms
Drive level: 10 mW
Frequency tolerance: ± .005% (suggested)

IN8IDETHE
EXTERNAL

IICII5AH

TRAP

INTERRUPT
REQUEST

TRAP

SCHMITT
TRIGGER

+5V

D elK

o
FIF

INTERNAL

TRAP F F

TRAP
ACKNOWLEDGE

Note the use of the 20 pF capacitor between X2 and
ground. This capacitor is required with crystal frequencies below 4 MHz to assure oscillator startup at
the correct frequency. A parallel-resonant LC circuit
may be used as the frequency-determining network
for the 8085AH, providing that its frequency
tolerance of approximately ± 10% is acceptable. The
components are chosen from the formula:

Figure 4. TRAP and RESET IN Circuit
The TRAP interrupt is special in that it disables interrupts, but preserves the previous interrupt enable
status. Performing the first RIM instruction following a TRAP interrupt allows you to determine
whether interrupts were enabled or disabled prior to
the TRAP. All subsequent RIM instructions provide
current interrupt enable status. 'Performing a RIM
instruction following INTR, or RST 5.5-7.5 will
provide current Interrupt Enable status, revealing
that Interrupts are disabled. See the description of
the RIM instruction in the MCS-80/85 Family User's
Manual.
The serial I/O system is also controlled by the RIM
and SIM instructions. SID is read by RIM, and SIM
sets the SOD data.

DRIVING THE X 1 AND X 2 INPUTS
You may drive the clock inputs of the 8085AH,
8085AH-2, or 8085AH-1 with a crystal, an LC tuned
circuit, an RC network, or an external clock source.
The crystal frequency must be at least 1 MHz, and
must be twice the desired internal clock frequency;
hence, the 8085AH is operated with a 6 MHz crystal
(for 3 MHz clock), the 8085AH-2 operated with a 10
MHz crystal (for 5 MHz clock), and the 8085AH-1 can
be operated with a 12 MHz crystal (for 6 MHz clock).
If a crystal is used, it must have the following
characteristics:

fF - - - - ' - - - -

To minimize variations in frequency, it is recommended that you choose a value for Cext that is at
least twice that of Cint, or 30 pF. The use of an LC
circuit is not recommended for frequencies higher
than approximately 5 MHz.
An RC circuit may be used as the frequencydetermining network forthe 8085AH if maintaining a
precise clock frequency is of no importance. Variations in the on-Chip timing generation can cause a
wide variation in frequency when using the RC
mod~. Its advantage is its low component cost. The
driving frequency generated by the circuit shown is
approximately 3 MHz. It is not recommended that
frequencies greatly higher or lower than this be
attempted.
Figure 5 shows the recommended clock driver circuits. Note in 0 and E that pullup resistors are required to assure that the high level voltage of the
input is at least 4V and maximum 10"':' level voltage
of 0.8V.
For driving frequencies up to and including 6 MHz
you may supply the driving signal to X1 and leave X2
open-circuited (Figure 50). If the driving frequency
is from 6 MHz to 12 MHz, stability of the clock
generator will be improved by driving both X1 and X2
with a push-pull source (Figure 5E). To prevent
self-oscillation of the 8085AH, be sure that X2 is not
coupled back to X1 through the driving circuit.

2-14

inter

8085AH/8085AH-218085AH-1

X,

---...,

I

I

I C,NT

.,...
I
X
i
2_ _ _ ....J
.L

L-'--4-----t

2

-

+5V
4700

TO

~15pF

1IUl

·20 pF CAPACITORS REQUIRED FOR
CRYSTAL FREQUENCY" 4 MHz ONLY

a. Quartz Crystal Clock Driver

---...,

X,

*
IllllAH

")(2 LEFT FLOATING

d. 1·6 MHz Input Frequency External Clock
Driver Circuit

I

I C'NT
...L.=16pF
LeXT

CEXT

T
2

I

X2_ _ _ ..J

+5V

.......4_700_I'--LOW-i TIME> 40 ..
1c

b. LC Tuned Circuit Clock Driver

X,

4700

'------1X2

e. 1·12 MHz Input Frequency External Clock
Driver Circuit

c. RC Circuit Clock Driver

Figure 5. Clock Driver Circuits

-

GENERATING AN 8085AH WAIT STATE
+

CLEAR
ALE°---. ClK

If your system requirements are such that slow
memories or peripheral devices are being used, the
circuit shown in Figure 6 may be used to insert one
WAIT state in each 8085AH machine cycle.

CLKOUTPUT'

"'D"
F/F
+5V-0

Q

-

TO
IOIIAH

ClK
"0"'
F/F
0

a

READY
INPUT

->---

·AlE AND CLK (OUT) SHOULD BE BUFFERED IF CLK INPUT OF LATCH
EXCEEDS 8085AH IOl OR IOH

The 0 flip-flops should be chosen so that
• ClK is rising edge-triggered
'
• CLEAR is low-level active.

Figure 6. Generation of a Wait State for 8085AH
CPU

2-15

8085AH/8085AH-2/8085AH-1

~

A8-15
~

A

.

ADO-7
ALE

8085AH

r--r--r--r---

RD
WR

101M
elK

vee
Vee

t--

RESET OUl

r-r--

READY

I
I.
:TIMER

RESET

--

I

IN

WARD

ALE

AD

eE

07

A8AIO

101M

AD _ 10/
07 CE M. ALE

RDl"'lW CLKRS~RDY

T6~~R_
8156H

[RAM + 1/0 + COUNTERITIMERJ

"NOTE OPTIONAL CONNECTION

8755A [EPROM + 1/0]

BB B

88

Figure S. MCS-S5® Minimum System (Memory Mapped I/O)·

----

TRAP

x,

x,

HOLD
HLDA

RST6

SOD

8085AH

RST5

AODR

tt-

510_

lNTR

fNfA

-

RESET IN

RST7

s,tRESET

ADDR/
DATA ALE R5

Wl'i:

SotOUT
101M
ROY eLK

'''I~'
~~

101M les)

\VA

RD
DATA

j,.

L

STANDARD
MEMORY

ADDR (CS)

Y

(16)

~

r- l- t -

elK
RESET

101M (es)

I/O POR TS.
lS

\VA

RB
DATA
STANDARD
I/O

B

ADDR

0DI

1 1

v"
v"
Vee

Figure 9. MCS-S5® System (Using Standard Memories)
2-16

I
I.
I

Vee

808SAH/808SAH-2/808SAH-1

As in the 8080, the READY line is used to extend the
read and write pulse lengths so that the 8085AH can
be used with slow memory. HOLD causes the CPU to
relinquish the bus when it is through with it by floating the Address and Data Buses.

SYSTEM INTERFACE
The 8085AH family includes memory component~,
which are directly compatible to the 8085AH cpu. For
example, a system consisting of the three chips,
8085AH, 8156H, and 8755A will have the following
features:

----

riD~

x,

TRAP

x,

TTl

RESET !N

HOLD

AST75

HLDA

RST6,5

RST5,5

ts,tsor-

SlOt-

INTR
RESET

TrilTA
ADOR

ff-

SOD

8085AH

OUT
ADOR/
DATA ALE AD WR IO/M
ROY elK

v"
181

v"

IBI

~ POR:~

IH-

WR
_

PORT

RD

8156H B

ALE
DATAl

fOV

ADDR

•
•
•
•

2K Bytes EPROM
256 Bytes RAM
1 Timer/Counter
4 8-bit I/O Ports
• 1 6-bit I/O Port
• 4 Interrupt Levels
• Serial In/Serial Out Ports

IN

~t-

r-

101M

TIMER

RESET

(8)

PORT~
C
(6)

-

QUlt--

'----

.--tOW
AD
ALE

l+.A

{';=

This minimum system, using the standard I/O technique is as shown in Figure 7.

PORT

A

EE

V

A8-10

~

8755A
DATA!
ADDR

101M

In addition to standard I/O, the memory mapped I/O
offers an efficient I/O addressing technique. With
this technique, an area of memory address space is
assigned for I/O address, thereby, using the memory
address for I/O manipulation. Figure 8 shows the
system configuration of Memory Mapped I/O using
8085AH.

~+-

--

'-

PORT

RESET

B

~
V"

ROY

16R-l

>--- CCK

t

Vss Vee Voo PROG

V"
V"

V
"NOTE

The 8085AH CPU can also interface with the standard
memory that does not have the multiplexed address/
data bus. It will require a simple 8-bit latch as shown in
Figure 9.

OPTIONAL CONNECTION

Figure 7. 8085AH Minimum System (Standard I/O
Technique)

2-17

8085AH!80&5AH-2!8085AH-1

BASIC SYSTEM TIMING

Table 3. 8085AH Machine Cycle Chart

The 8085AH has a multiplexed Data Bus. ALE is used
as a strobe to sample the lower 8-bits of address on
the Data Bus. Figure 10 shows an instruction fetch,
memory read and I/O write cycle (as would occur
during processing of the OUT instruction). Note that
during the I/O write and read cycle that the I/O port
address is copied on both the upper and lower half
of the address.

MACHINE CYCLE
OPCODE FETCH
MEMORY READ

MEMORY WRITE
I/O READ
110 WRITE
ACKNOWLEDGE
OF INTR
BUSIDLE

STATUS
101M S1

SO

RD

WR

INTA

0
0
0
1
1

1
1
0
1
0

1
0
1
0
1

0
0
1
0
1

1
1
0
1
0

1
1
1
1
1

1
0

1
1

1

1
1

1
1

0

0

1
1

10FI
IMRI
IMWI
IIOR)
IIOWI
IINAI
IBII DAD
ACK OF
RST,TRAP
HALT

There are seven possible types of machine cycles.
Which of these seven takes place is defined by the
status of the three status lines (101M, S1, So) and the
three control signals (RD, WR, and INTA). (See Table
3.) The status lines can be used as advanced con~
trois (for device selection, for example), .since they
become active at the T1 state, at the outset of each
machine cycle. Control lines RD and WR become
active later, at the time when the transfer of data is to
take place, so are used as command lines.

CONTROL

1

1

1

1

1

TS

0

0

TS

TS

Table 4, 8085AH Machine State Chart
Status & Buses
Machme
State
81,SO 101M As-A15 ADo-AD7

A machine cycle normally consists of three T states,
with the exception of OPCODE FETCH, which normally has either four or six T states (unless WAIT or
HOLD states are forced by the receipt of READY or
HOLD inputs). Any T state must be one of ten
possible states, shown in Table 4.

Control

Ro,WR iNTA

ALE

T,

X

X

X

X

1

1

l'

T2

X

X

X

X

X

X

0

TWAIT

X

X

X

• X

X

X

0

T3

X

X

X

X

X

X

0

T,

1

X

TS

1

1

0

T5

1

ot
ot

·X

TS

1

1

0

T6

1

0'

X

TS

1

1

0

TRESET

X

TS

TS

TS

TS

1

0

THALT

0

TS

TS

TS'

TS

1

0

THOLD

X

TS

TS

TS

TS

1

0

0= LogiC "0"
1'" LogiC "'"

I

TS = High Impedance
x = Unspecified

.. ALE not generated during 2nd and 3rd machine cycles of DAD instruction

t 101M

=

1 dUring T4 - T6 of INA machine cycle

PC H (HIGH ORDER ADDRESS)

PC,

~ ___ _

(LOW ORDER
ADDRESS)

DATA FROM
MEMORY
(INSTRUCTION)

ALE

WR

101M

STATUS

10 (READ)

Figure 10. 8085AH Basic System Timing
2-18

01 WRITE

11

1

8085AH/8085AH-2/8085AH-1

'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ......... O°C to 70°C
Storage Temperature ............... -65°C to +150°C
Voltage on Any Pin
With Respect to Ground .............. -0.5V to +7V
Power Dissipation ........................... 1.5 Watt

-D.C. CHARACTERISTICS
8085AH,8085AH-2: (TA = O°C to 70°C, Vee = 5V ±10%, VSS =OV; unless otherwise specified)'
8085AH-1: (TA = O°C to 70°C, Vee = 5V ±5%, VSS = OV; unless otherwise specified)

Symbol

Max.

Units

-0.5

+0.8

V

2.0

Vee +0.5

V

0.45

V

IOL = 2mA

V

IOH = -400/LA

Parameter

Min.

VIL

Input low Voltage

VIH

Input High Voltage

VOL

Output low Voltage

VOH

Output High Voltage

lee

Power Supply Current

IlL

Input leakage

ILO

Output leakage

VILR

Input low level, RESET

VIHR

Input High level, RESET

VHY

Hysteresis, RESET

0.15

2.4

Test Conditions

135

rnA

8085AH, 8085AH-2

200

rnA

8085AH-1 (Preliminary)

±10

/LA

0,,;; VIN ,,;; Vee

±10

Ji,A

0.45V ,,;; VOUT ,,;; Vee

-0.5

+0.8

V

2.4

Vee +0.5

V
V

A.C. CHARACTERISTICS
8085AH,8085AH-2: (TA = O°C to 70°C, Vee = 5V ±10%, VSS = OV)'
8085AH-1: (TA = O°C to 70°C, Vee = 5V ±5%, VSS = OV)

Symbol
teye

8085AH[21

8085AH-2[21

8085AH-1

(Final)

(Final)

(Preliminary)

Parameter
ClK Cycle Period

Min.

Max.

Min.

Max.

Min.

Max.

320

2000

200

2000

167

2000

Units
ns

t1

ClK low Time (Standard ClK loading)

80

40

20

ns

t2

ClK High Time (Standard ClK loading)

120

70

50

ns

t r , tf

ClK Rise and Fall Time

tXKR

X1 Rising to ClK Rising

tXKF

X1 Rising to ClK Falling

tAe

Aa-15 Valid to leading Edge of ControPI

270

tAeL

AO-7 Valid to leading Edge of Control

240

tAD

AO-15 Valid to Valid Data In

tAFR

Address Float After leading Edge of
READ (INTA)

tAL

AS- 15 Valid Before Trailing Edge of ALE [11

30

30

ns

20

100

20

100

ns

20

110

20

110

ns

30
20

120

20

150

115
115

ns
ns

60

575

350

225

ns

0

0

0

ns

115

'Nole: For Extended Temperature EXPRESS use MS085AH Electricals Parameters.
2-19

70

50

25

ns

8085AH/8085AH-2!8085AH-1

A.C. CHARACTERISTICS (Continued)
8085AH[21
(Final)

Parameter

Symbol

Min.

Max.

90

8085AH.2[21
(Final)

8085AH·1
(Preliminary)

Min.

Min.

Max.

50

Units

Max.

25

tAll

AO-7 Valid Before Trailing Edge of ALE

tARY

READY Valid from Address Valid

tCA

Address (Aa-1S) Valid After Control

120

60

30

ns

tcc

Width of Control Low (RD, WR, INTA)
Edge of ALE

400

230

150

ns

tCl

Trailing Edge of Control to Leading Edge
of ALE

50

25

0

ns

tow

Data Valid to Trailing Edge of WRITE

420

tHABE

HLDA to Bus Enable

100

220

230
210
210

tHABF

Bus Float After HLDA

tHACK

HLDA Valid to Trailing Edge of CLK

tHOH

HOLD Hold Time

tHOS

HOLD Setup Time to Trailing Edge of CLK

tlNH

INTR Hold Time

tiNS

INTR, RST, and TRAP Setup Time to
Falling Edge of CLK

tLA

ns

40

140

ns

ns

150

150

ns

150

150

ns

110

40

0

ns

0

0

0

ns

170

120

120

ns

0

0

0

ns

160

150

150

ns

Address Hold Time After ALE

100

50

20

ns

tlC

Trailing Edge of ALE to Leading Edge
of Control

130

60

25

ns

tlCK

ALE Low During CLK High

100

tLOR

ALE to Valid Data During Read

tLOW

ALE to Valid Data During Write

tll

ALE Width

50

175

ns

200

140

110

ns

80
110

ALE to READY Stable

tRAE

Trailing Edge of READ to Re-Enabling
of Address

tRO

READ (or INTA) to Valid Data

tRY

Control Trailing Edge to Leading Edge
of Next Control

tROH

ns

270

140

tlRY

15

460

150

50
30
50

90
150

300

ns

10

ns
ns

75

ns

400

220

160

ns

Data Hold Time After READ iN'i'A

0

0

0

ns

tRYH

READY Hold Time

0

0

5

ns

tRYS

READY Setup Time to
of CLK

110

100

100

ns

two

Data Valid After Trailing Edge of WRITE

tWOl

LEADING Edge of WRITE to Data Valid

~eading

Edge

100

60
40

2-20

30
20

ns

30

ns

inter

8085AH/8085AH-2/8085AH-1

NOTES:
1. As-A'5 address Specs apply IO/M, So, and S, except Aa-A'5
are undefined dUring T4-Ts of OF cycle whereas IO/M, SO, and
S, are stable.
2. Test Conditions; tCYC = 320 ns (8085AH)/200 ns (8085AH-2);/
167 ns (8085AH-1); CL = 150 pF.

3. For all output timing where CL 1150 pF use the following
correction factors:
25 pF '" CL < 150 pF: -0.10 ns/pF
150 pF < CL '" 300 pF: +0.30 ns/pF
4. Output timings are measured with purely capacitive load.
5. To calculate timing specifications at other values of tCYC use
Table 5.

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

INPUT/OUTPUT

DEVICE
UNDER
TEST

''}CC_ 15OPF
-::-

A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND 08V FOR A LOGIC 0

Cl=150pF
C L INCLUDES JIG CAPACITANCE

Table 5. Bus Timing Specification as a TCYC Dependent

8085AH

Symbol

8085AH-2

8085AH-1

tAL

(1/2) T - 45

(1/2) T - 50

(1/2) T - 58

Minimum

tlA

(1/2) T - 60

(1/2)T - 50

(1/2) T - 63

Minimum

tll

(1/2) T - 20

(1/2) T - 20

(1/2) T - 33

Minimum

tlCK

(1/2) T - 60

(1/2) T - 50

(1/2) T - 68

Minimum

(1/2) T - 58

Minimum

tlC

(1/2) T - 30

(1/2) T - 40

tAD

(5/2 + N) T - 225

(5/2

+ N)T -180

tRD

(3/2

tRAE

(1/2)T - 10

+ N)T - 150

(5/2

+ N)T -192

Maximum

+ N)T -175

Maximum

(3/2 + N)T - 150

(3/2

(1/2) T - 10

(1/2)T - 33

Minimum

(1/2) T - 40

(1/2) T - 53

Minimum

tCA

(1/2) T - 40

tDW

(3/2

tWD

(1/2) T - 60

tcc

(3/2

tCl

(1/2)T - 110

(1/2) T - 75

(1/2) T - 83

Minimum

tARY

(3/2) T - 260

(3/2) T - 200

(3/2) T - 210

Maximum

tHACK

(1/2) T - 50

(1/2) T - 60

tHABF

(1/2) T

tHABE

+ N) T - 60
+ N) T - 80

(3/2

+ N) T - 70

(1/2) T - 40
(3/2

+ N) T - 70

(3/2

+ N)T -110

(1/2) T - 53
(3/2

+ N)T - 100

Minimum
Minimum
Minimum

(1/2) T - 83

Minimum

+ 50

(1/2) T

+ 67

Maximum

(1/2) T + 50

(1/2) T + 50

(1/2) T

+ 67

Maximum

tAC

(2/2) T - 50

(2/2) T - 85

(2/2) T - 97

Minimum

t1

(1/2) T - 80

(1/2) T - 60

(1/2)T - 63

Minimum

t2

(1/2) T - 40

(1/2) T - 30

(1/2) T - 33

Minimum

tRY

(3/2) T - 80

(3/2) T- 80

(3/2) T - 90

Minimum

tLDR

(4/2) T - 180

(4/2) T - 130

(4/2) T - 159

Maximum

NOTE:

+ 50

(1/2) T

N IS equal to the total WAIT states. T = tCyc.

2-21

inter

SOS5AH/SOS5AH-2/S0SSAH-'

WAVEFORMS (Continued)
READ OPERATION WITH WAIT CYCLE (TYPICAL) TO WRITE
T,
T,

SAME READY TIMING APPLIES
T,

TWAIT

CLK
_tCA_

As A,s

~~--+---------+---------~I~----------+-~~----

ALE

READY
NOTE 1 READY MUST REMAIN STABLE DURING SETUP AND HOLD TIMES

INTERRUPT AND HOLD

1------

BUS FLOATING"

------1

~--------------t-----~----------------~

HOLD

HLDA

"101M IS ALSO FLOATING DURING THIS TIME

2-22

inter

8085AH/8085AH-2/8085AH-1

Table 6. Instruction Set Summary

Mnemonic

I

Operations
Description

Instruction Code
07 06 05 04 03 02 0, 00

Instruction Code

MOVE, LOAD, AND STORE
MOVr1 r2
MOVMr
MOVrM
MVI r
MVIM
LXI B

0
0
0
0
0
0

LXI D

1
1
1

0
0
0

D
1
D
D
1

0

0

0

0

0

1

LXI H

0

0

1

0

STAX B
STAXD
LDAX B
LDAX D
STA
LDA
SHLD
LHLD
XCHG

0

0

0
0
0
0
0
0
0

0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1

1

1

0
0
1 0

STACK OPS
PUSH B

1

1

0

0

0

1

0

1

PUSH D

1

1

0

1

0

1

0

1

PUSH H

1

1

1

0 0

1

0

1

PUSH PSW

1

1

1

1

0

1

0

1

POPB

1

1

0

0

0

0

0

1

POP D

1

1

0

1

0

0

0

1

POP H

1

1

1

0

0

0

0

1

POPPSW

1

1

1

1

0

0 0

1

XTHL

1

1

1

0

0

0

1

1

SPHL
LXI SP

1

1

0

0

1
1

1
1

0 0
0 0 0

1
1

1

0
1
1
1

CZ
1 1 0 0 1
CNZ
1 1 0 0 0
CP
1 1 1 1 0
CM
1 1 1 1 1
CPE
1 1 1 0 1
CPO
1 1 1 0 0
RETURN
RET
1 1 0 0 1
RC
1 1 0 1 1
1 1 0 1 0
RNC
1 1 0 0 1
RZ
RNZ
1 1 0 0 0
RP
1 1 1 1 0
RM
1 1 1 1 1
RPE
1 1 1 0 1
RPO
1 1 1 0 0
RESTART
RST
1 1 A A A
INPUT/OUTPUT
IN
1 0 1 1
OUT
1 0 1 0
INCREMENT AND DECREMENT
INR r
0 0 D D D
DCR r
0 0 D D D
INR M
0 0 1 1 0
DCR M
0 0 1 1 0
INX B
0 0 0 0 0

D S S S Move register to register
0 S S S Move register to memory
D 1 1 0 Move memory to register
D 1 1 0 Move Immediate register
0 1 1 0 Move Immediate memory
0 0 0 1 Load Immediate register
l'alrB&C
0 0 0 1 Load Immediate register
PalrD&E
0 0 0 1 Load Immediate register
PalrH&L
0 0 1 0 Store A Indirect
0 0 1 0 Store A indirect
1 0 1 0 Load A indirect
1 0 1 0 Load A I nd I rect
0 0 1 0 Store A direct
1 0 1 0 Load A direct
0 0 1 0 Store H & L direct
1 0 1 0 Load H & L direct
1 0 1 1 Exchange D & E, H & L
Registers

D
1
D
D
1

I~

Push register Pair B &
C on stack
Push register Pair D &
E on stack
Push register Pair H &
L on stack
Push A and Flags

0 0
0 0

1
1

1
1

0
1

0
0

1
1

1
1

1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1

0
0
0
0
0

CALL
CALL
CC
CNC

1
1
1

1
1
1

0 0
0 1
0 1

1
1
1
1
1

0

0

1
1

1

0
0

0
1

0
1 0

1

0
0
0

1
1

0
1

1
1

0

0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0

Call on zero
Call on no zero

Call on positive
Call on minus
Call on panty even

Call onpantv odd

1

Return

0
0
0
0
0
0
0
0

Return on carry

Return on no carry
Return on zero
Return on no zero

Retu rn on positive
Return on minus
Return on panty even
Return en panty odd

1

1

1

Restart

0
0

1
1

1
1

Input
Output

1
1
1
1
0

0 0
0 1
0 0
0 1
1

1

Increment register

Decrement register
Increment memory
Decrement memory
Increment B & C
registers
Increment 0 & E
registers
Increment H & L
registers

0

0

0

1

0 0

1

1

on stack

0

0

1

0

0 0

1

1

Pop register Pair B &
C off stack
Pop register Pair 0 &
E off stack
Pop register Pair H &
L off stack
Pop A and Flags

DCX
DCX
DCX
ADD
ADD
ADC

B
D
H

0 0 0 0 1 0
0 0 0 1 1 0
0 0 1 0 1 0

1
1
1

1
1
1

r
r

1
1

0
0

0 0 0 S S S Add register to A
0 0 1 S S S Add register to A

ADDM
ADCM

1
1

0

C 0

0

0

0

1

ADI
ACI

1
1

1
1

0

0

0

0 0

DAD B
DAD D
DADH
DADSP

0
0
0
0

0 0
0 0
0 1
0 1

0

SUBTRACT
SUB r

1

SBB r

1

SUB M
SBBM

Exchange top of
stack, H & L
H & L to stack pOinter
Load Immediate stack

Increment stack pOinter
Decrement stack

ralnter
JUMP
JMP
JC
JNC
JZ
JNZ
JP
JM
JPE
JPO
PCHL

0 0
0 0
0 0
0 0
0 0
0 0

INX H

pomter

INX SP
DCX SP

1
1
1
1
1
1

INX D

off stack

1

Operations
Description

Mnemonie 0, 06 05 04 D3 D2 0, 00

0
0
0
0
0
0
0
0
0
0

1 1
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
0 1

1
1
1

0 1 Call unconditIonal
0 0 Call on carry
0 0 Call on no carry

Jump unconditional
Jump on carry
Jump on no carry
Jump on zero
Jump on no zero
Jump on positive
Jump on minus
Jump on panty even
Jump on panty odd
H & L to program
counter

2-23

1
1

1
1

0
0

1

1
1

1
1

0
0

1

1
1
1
1

0 0
0 0
0 0
0 0

1
1
1
1

0 0

1

0

S

S S

0

0

1

1

S

S S

1

0 0

1

0

1

1

0

1

0

0

1

1

1

1

0

SUI

1

1

0

1

0

1

1

0

SBI

1

1

0

1

1

1

1

0

1

0

0

Decrement 8 & C
Decrement 0 & E
Decrement H & L

with carry
Add memory to A
Add memory to A
with carry
Add Immediate to A
Add Immediate to A
with carry
AddB&CtoH&L
AddD&EtoH&L
AddH&LtoH&L
Add stack pOinter to
H&L
Subtract regIster
from A
Subtract register from
A with borrow
Subtract memory
from A
Subtract memory from
A With borrow
Subtract Immediate
from A
Subtract Immediate
from A With borrow

8085AH/8085AH-2/8085AH-1

Table 6. Instruction Set Summary (Continued)
Operations
Description

Instruction Code

Mnemonic 0-, O~ 0 5 04 ~ 02 0, DO
LOGICAL
ANAr
XRA r

1
1

0
0

1
1

0
0

0
1

ORA r
CMPr
ANAM
XRAM

1
1
1
1

0
0
0
0

1
1
1
1

1
1
0
0

0 S
1 S
0 1
1 1

S S S
S S S
S S
S S
1
1

0
0

DRAM
CMPM

1
1

0
0

1
1

1
1

0
1

1
1

1
1

0
0

ANI
XRI

1
1

1
1

1
1

0
0

0
1

1
1

1
1

0
0

ORI
CPI

1
1

1

1

1

0

1

1

I

I

I

I

I

I

0
0

ROTATE
RLC
RRC
RAL

0
0
0

0 0
0 0
0 0

0 0
0 1
I 0

I
I
I

I

I

1
1

1
1

RAR

0

0

1

1

1

1

Mnemonic

And register with A
Exclusive OR register
with A
OR register With A
Compare register With A
And memory With A

Instruction Code~
07 D6 D5 D4 D3 D2 D, Do

SPECIALS
CMA

0

0

1

0

1

1

1

1

Complement

STC
CMC

0
0

0
0

1
1

1
1

0
1

1
1

1
1

1
1

A
Set carry
Complement
carry

DAA

0 0 1 0 0
CONTROL
EI
1 1 1 1 1
01
1 1 1 1 0
NOP
0 0 0 0 0
HLT
0 1 1 1 0
NEW BOB5A]NSTRUCTIONS
RIM
0 0 1 0 0
SIM
0 0 1 1 0

Exclusive OR memory

With A
OR memory With A
Compare
memory With A
And Immediate With A

Exclusive OR Immediate
With A
OR immediate With A
Compare Immediate

With A

0

1

Rotate
Rolate
Rotate
carry
Rotate

A left
A right
A left through
A right through

carry

NOTES:
1. DOS or SSS' BODO, COOl, 0010, EO'", H 100, L 101, Memory 110, A 111
2. Two possible cycle times (6(12) indicate instruction cycles dependent on conditIOn flags

"All mnemonics cOPYrighted ©Intel Corporation 1976

2-24

Operations
Description

1

1

1

Decimal adjust A

0
0
0
1

1
1
0
1

1
1
0
0

Enable Interrupts
Disable Interrupt
Halt

0
0

0
0

0
0

Set Interrupt Mask

No~operatlon

Read Interrupt Mask

intJ

8085AH/8085AH·2/8085AH·1

WAVEFORMS

CLOCK
X1 INPUT
tr _ _ _ _ _ -

t2 _ _ _ _ _ 1 _ _ tf

elK
OUTPUT

----------

READ

tXKf

T,

1

i-

)!

As-A15

}

--

- . l lL

I-

'LA

-

-I----'AC

I

-

-tLC

-

7/11 11111)

_I'D-~

_---ICC

I

r-

I

T,

I

\

I

T3

_______

/

j

r-'OA-I

-

)

I

DATA OUT

tLA-~

-

ALE
_

T,

X

tLDW

ADDRESS

~tLL-1

I

I

ADDRESS

)

1'----

1'' 11

tLDR--~

~

1-

I'
!

r-'''K-I
AD o-AD 7

-1,--

...-.''AE

---I

T,

)

DATA IN

I

leA_

_I)

I RDH ___

..

--_I

eLK

As-A15

-:

t AD -

T,

\
I.

~-

-..-. I Al --.

WRITE

/
I

tAFR ___

ALE

RD/INTA

r---\

-----

ADDRESS

I

T3

1

ADDRESS

)

[-

tlCK -

~ --

~---

AD o-AD 7

------~I

T,

1

/

eLK \ ,

teve

--

____

X

. ~'wo-I

'ow
f--tWDL

Al

~

-

WR
_______ tLc

~'AC
HOLD

T,
elK

\

HOLD

t

1-

t HOS "

I

j

\

"l..

I,HDH

r-

t

HLDA

BUS

T HOlD

T3

/

(ADDRESS, CONTROLS)

-

'CC

=1

_ t CL -

T,

T HOLD

\

\

:~
t HACK --

'\

t HABF -

1>-1

2-25

IHABE-H

I!

8155H/8156H/8155H-2/8156H-2
2048-BIT STATIC HMOS RAM
WITH 1/0 PORTS AND TIMER
Programmable 6·Bit I/O Port
• 1Programmable
14·Blt Binary Counter/

Single +5V Power Supply with 10%
• Voltage
Margins
30% Lower Power Consumption than
• the
8155 and 8156

•
•
•
•
•

• Timer

with 8085AH, 8085A and
• Compatible
8088 CPU

100% Compatible with 8155 and 8156
256 Word x 8 Bits
Completely Static Operation
Internal Address Latch
2 Programmable 8·Blt I/O Ports

• Multiplexed Address and Data Bus
in EXPRESS
• Available
- Standard Temperature Range

- Extended Temperature Range

I

The Intel$ 8155H and 8156H are RAM and 1/0 chips implemented in N-Channel, depletion load, silicon gate technology
(HMOS), to be used in the 8085AH and 8088 microprocessor systems. The RAM portion is designed with 2048 static cells
organized as 256 x 8. They have a maximum access time of 400 ns to permit use with no wait states in 8085AH CPU. The
8155H-2 and 8156H-2 have maximum access times of 33b ns for use with the 8085AH-2 and the 5 MHz 8088 CPU.
The I/O portion consists of three general purpose I/O ports. One of the three ports can be programmed to be status
.
pins, thus allowing the other two ports to operate in handshake mode.
A 14-bit programmable counter/timer is also included on chip to provide either a square wave or terminal count pulse
for the CPU system depending on timer mode.

~

10 1M

ADo 7

256 X 8
STATIC

RAM

*

PAo~7

Rll

iVA
RESET

TIMER

ITIMER eLK

pBo·,

G

~veel+5V)

TIMER OUT

'8155H/815611-2 =

CE, 815811/811811-2 = CE

Figure 1. Block Diagram

vee

PC.

PC 2

TIMER IN

PC,

RESET

PCo

PCs

PB,

TIMER OUT

G

ALE

PC 3

Vss IOV)

PCO- 5

101M

PBs

CE OR CE*

PB.

RJj

PB 3

iNA

PB 2

ALE

PB,

ADo

PBo

AD,

PA,

AD2

PAs

AD3

PAs

AD.

PA.

AD.

PA 3

AD.

PA 2

AD,

PA,

' Vss

PAo

f

Figure 2. Pin Configuration.

Intel Corporation A••ume. No R••ponaibilty for the Use of Any Circuitry Other Than Circuitl")' Embodied In an Intel Product No Other CirCUit Patent Licenses a'. Implied.
1981
2-26

© INTEL CORPORATION,

inter

8155H/8156H/8155H-2/8156H-2

Table 1 Pin Description
Symbol

Type

Name and Function

I

Reset: Pulse provided by the BOB5AH to Initialize the system (connect to BOB5AH RESET OUT). Input
high on thiS line resets the chip and initializes the three 1/0 ports to Input mode The width of RESET
pulse should typically be two BOB5AH clock cycle times

I/O

Address/Data: 3-state AddresslData lines that Interface with the CPU lower B-blt AddresslData Bus
The B-blt address is latched into the address latch inSide the 8155H/56H on the falling edge of ALE. The
address can be either for the memory section or the 1/0 sectIOn depending on the 101M Input The B-bit
data IS either written Into the chip or read from the ChiP, depending on the WR or RD Input signal.

CEorGE:

I

Chip Enable: On the B155H, thiS pin IS CE and IS ACTIVE LOW On the B156H, thiS pin IS CE and is
ACTIVE HIGH

RD

I

Read Control: Input Iowan thiS line with the Chip Enable active enables and ADo_7 buffers If 101M pin
IS low, the RAM content Will be read out to the AD bus OtherWise the content of the selected 1/0 port or
commandlstatus registers Will be read to the AD bus

WR

I

Write Control: Input Iowan thiS line with the Chip Enable active causes the data on the AddresslData
bus to be written to the RAM or 1/0 ports and commandlstatus register, depending on 101M

ALE

I

Address Latch Enable: ThiS control signal latches both the address on the ADO_7 lines and the state
of the Chip Enable and 101M Into the chip at the failing edge of ALE

I

1/0 Memory: Selects memory If low and 1/0 and commandlstatus registers If high

RESET

ADO_7

101M

PAO-7(B)

1/0

Port A: These 8 pinS are general purpose 1i0 pinS The Inlout direciion IS selected by programming
the command register

PB O_7(B)

110

Port B: These B pinS are general purpose 1/0 pms The In/out direction IS selected by programming
the command register

PCo-s(6)

I/O

Port C: These 6 pinS can function as either Input port, output port, or as control Signals for PA and PB
Programming IS done through the command register When PC o- s are used as control Signals, they
Will proVide the follOWing
I;'C o - A INTR (Port A Interrupt)
PC t - ABF (Port A Buffer Full)
PC2 - A STB (Port A Strobe)
PC3 - B INTR (Port B Interrupt)
PC4 - B BF (Port B Buffer Full)
PCs - B STB (Port 8 Strobe)

TIMER IN

I

TIMER OUT

0

-

-

Timer Input: Input to the counter-timer
Timer Output: This output can be either a square wave or a pulse, depending on the timer mode.

Vcc

Voltage: +5 volt supply

Vss

Ground: Ground reference

FUNCTIONAL DESCRIPTION

I
I

I
The 8155H/8156H contains the follOWing:
• 2k Bit Static RAM organized as 256 x 8
• Two 8-blt I/O ports (PA & PB I and one 6-blt I/O port r PC i
• 14-blt timer-counter
The lo/Kii (IO/Memory Select I pin selects either the five
registers (Command, Status, PAO-7, PBo-7, PCO-SI or
the memory r RAM I portion
The 8-blt address on the Address/Data lines, Chip Enable
Input CE or CE, and 10iM are all latched on-chip at the
falling edge of ALE

I
I

I

I

I

I
I
I
I

I
I
I

I

I

I

I

I

L ____ _

_____ ~ ___ J

Figure 3_ 8155H/8156H Internal Registers

2-27

I
I

intJ
CE(8155H)

8155H/8156H/8155H-218156H-2

\

V

\

/

1\

/

\

V

\

oR
CE(81&8H)

101M

,

X

7

ADDRESS

J

1\

V

"

X

DATA VALID

Al E

R

NOTE: FOR DETAILED TIMING INFORMATION, SEE FIGURE 12 AND A.C CHARACTERISTICS.

Figure 4. 8155H/8156H On-Board Memory Read/Write Cycle

PROGRAMMING OF THE
COMMAND REGISTER

76543210

1:=

ITM,ITM11IEBI'EAI pC21 PC,

The command register consists of eight latches Four
bits (0-3) define the mode of the ports, two bits 14-51
enable or disable the Interrupt from port C when It acts
as control port, and the last two bits 16-71 are forthe timer

L - ----'

The command register contents can be altered at any
time by using the 110 address XXXXXOOO dunng a WRITE
operation with the Chip Enable active and lo/fiil = 1 The
meaning of each bit of the command byte IS defined in
Figure 5. The contents of the command register may
never be read.

PB

I PA I

DEFINES PAQ., }

0= INPUT

DEFINES PBo-7

1

11"" ALT 2
01 = AL T 3
10 = ALl 4

~:r~RL:u~RT

A

t
}

L-_ _ _ _ _ _ _•

READING THE STATUS REGISTER
The status register ConSiStS of seven latches, one for each
bit, SIX 10-5) for the status of the ports and one 161 for the
status of the timer.

~TIMER COMMAND

r 00

=

01

=

OUTPUT

OO=ALT1
DEFINES PCo-5 {

L--,-_ _ _ _ _

=

~:TAEBRL:U~RT B

=

ENABLE

0= DISABLE

NOP _ DO NOT AFFECT COUNTER
OPERATION
STOP - NOP IF TIMER HAS NOT STARTED;
STOP COUNTING IF THE TIMER IS
RUNNING

10'" STOP AFTER Te - STOP IMMEDIATELY
AFTER PRESENT Te IS REACHED (NOP
IF TIMER HAS NOT STARTED)
11 = 8T ART - LOAD MODE AND CNT LENGTH
AND START IMMEDIATELY AFTER
LOADING (IF TIMER IS NOT PRESENTLY
RUNNING) IF TIMER IS RUNNING, START
THE NEW MODE AND CNT LENGTH
IMMEDIATELY AFTER PRESENT TC
IS REACHED

The status of the timer and the I/O section can be polled
by reading the Status Register (Address XXXXXOOO)
Status word format is shown in Figure 6. Note that you
may never write to the status register since the command
register shares the same I/O address and the command
register 15 selected when a wnte to that address IS Issued

Figure 5. Command Register Bit Assignment

2-28

inter

8155H/8156H/8155H-2/8156H-2

interrupt that the 8155H sends out. The second is an
output signal indicating whether the buffer is full or
empty, and the third IS an input pin to accept a strobe
for the strobed input mode. (See Table 2.)
AD,

AD6

AD,

IXJTlME'RIIN;EI

AD,

SBF

AD3

ADz

AD,

ADo

When the 'C' port IS programmed to either AL T3 or AL T4,
the control signals for PA and PB are initialized as follows

IIN;RIIN;EI ~ [INIRI

L

I I I L

PORT A INTERRUPT REQUEST

CONTROL

INPUT MODE

~"'.
,"m. >"""-,
(INPUT/OUTPUT)

BF

Low

Low

INTR

Low

High

STB

Input Control

Input Control

PORT A INTERRUPT ENABLE

PORT B INTERRUPT REQUEST

OUTPUT MODE

PORT B BUFFER FULL/EMPTY
(INPUT/OUTPUT I

PORT B INTERRUPT ENABLED
TIMER INTERRUPT (THIS BIT
IS LATCHED HIGH WHEN
TERMINAL COUNT IS
REACHED, AND IS RESET TO
LOW UPON READING OF THE
CIS REGISTER AND BY
HARDWARE RESET)

I/O ADDRESS+
SELECTION
A7 A6

X
X
X
X
X
X

Figure 6. Status Register Bit Assignment

X
X
X
X
X
X

AS A4 A3 A2 A1

X
X
X
X
X
X

X
X
X
X
X
X

0
0

X
X
X
X
X
X

0

0
0
1
1

1
1

0
0

0

AO

0
1

0
1
0
1

Interval Command/Status Register
General Purpose 1.'0 Port A
General Purpose I/O Port B
Port C - General Purpose 1/0 or Control
low-Order 8 bits 01 Timer Count
High 6 bits 01 Timer Count and 2 bits
of Timer Mode

X Don't Care

t

I/OAddress must be qualified by CE "" 1 (8156H) or
order to select the appropnate register

CE "" 0 (8155H) and 101M""

110

INPUT/OUTPUT SECTION
The I/O section of the 8155H/8156H consists of five registers: (See Figure 7.)

Figure 7. I/O Port and Timer Addressing Scheme

• CommandlStatus Register (CIS) - Both registers are
assigned the address XXXXXOOO The CIS address
serves the dual purpose

Figure 8 shows how I/O PORTS A and B are structured
within the 8155H and 8156H:

When the CIS registers are selected during WRITE
operatIOn, a command IS written into the command
register. The contents of this register are not accessible
through the pins

8155H/8156H

ONE BIT OF PORT A OR PORT B

When the CIS (XXXXXOOO) is selected dUring a READ
operation, the status Information of the I/O ports and
the timer becomes available on the ADo-7 lines.
• PA Register - This register can be programmed to be
either Input or output ports depending on the status of
the contents of the CIS Register. Also depending on
the command, this port can operate In either the basic
mode or the strobed mode (See timing diagram) The
I/O pins assigned in relation to this register are PAO-7
The address of this register is XXXXX001.
• PB ,Register - This register functions the same as PA
Register. The I/O PinS assigned are P80-7. The address
of this register is XXXXX010
• PC Register - This register has the address XXXXX011
and contains only 6 bits. The 6 bits can be programmed to be either input ports, output ports or as control
signals for PA and PB by properly programming the
AD2 and AD3 bits of the CIS register.

NOTES
(1) OUTPUT MODE }
(2) SIMPLE INPUT
(3) STROBED INPUT

STO

(4)
MULTIPLEXER
CONTROL

= 1 FOR OUTPUT MODE

'" 0 FOR INPUT MODE

READ PORT = (lO/M=1). (RD=O). (CE ACTIVE). (PORT ADDRESS SELECTED)
WRITE PORT = (IO/M"'1). (WR=O). ICE ACTIVE). (PORT ADDRESS SELECTED)

When PCO-5 is used as a control port, 3 bits are
assigned for Port A and 3 for Port B. The first bit is an

Figure 8. 8155H/8156H Port Functions
2-29

· 8155H/8156H/8155H-218156H-2

Table 2. Port Control Assignment
ALT 1

Pin

PCO
PCl
PC2
PC3
PC4
PC5

Input
Input
Input
Input
Input
Input

Port
Port
Port
Port
Port
Port

ALT2
Output
Output
Output
Output
Output
Output

Port
Port
Port
Port
Port
Port

ALT3

ALT 4

A INTR (Port A Interrupt)
A BF (Port A Buffer Full)
A STB (Port A Strobe)
Output Port
Output Port
Output Port

A INTR (Port A Interrupt)
A BF (Port A Buffer Full)
A STB (port A Strobe)
B INTR (Port B Interrupt)
B BF (Port B Buffer Full)
B STB (Port B Strobe)

Note In the diagram that when the I/O ports are prog rammed to be output ports, the contents of the output
ports can still be read by a READ oper<\.tion when appropriately add ressed.

TIMER SECTION
The timer is a 14-bit down-counter that counts the TIMER
IN pulses and provides either a square wave or pulse
when terminal count (TC) is reached

The outputs olthe 8155H/8156H are "glitch-free" meaning
that you can write a "1" to a bit position that was previously "1" and the level at the output pin will not change.

The timer has the I/O address XXXXX100for the low order
byte of the register and the I/O address XXXXX101 for
the high order byte of the register. (See Figure 7.)

Note also that the output latch is cleared when the port
enters the input mode. The output latch cannot be loaded
by writing to the port if the port is in the input mode. The
result is that each time a port mode is changed from input
to output, the output pins will go low. When the8155H/56H
is RESET, the output latches are all cleared and all 3 ports
enter the input mode.

To program the timer, the COUNT LENGTH REG is loaded
first, one byte at a time, by selecting the timer addresses. Bits
0-13 of the high order count register will specify the length of
the next count and bits 14-15 of the high order register will
specify the timer output mode (see Figure 10). The value
loaded into the count length register can have any value
from 2H through 3FFFH in Bits 0-13.

When in the AL T 1 or AL T 2 modes, the bits of PORT C
are structured like the diagram above in the simple input
or output mode, respectively.
6

Reading from an input port with nothing connected to the
pins will provide unpredictable results.

M2

4

5

2

0

M,

! T13! T'2! T" ! T,o ! T9! Tal
II
I
i
I
MSB OF CNT LENGTH
TIMER MODE

Figure 9 shows how the 8155H/8156H I/O ports might be
configured in a typical MCS-85 system.

6

5

4

LSB OF

3

C~T

o

2

LENGTH

Figure 10. Timer Format

---t .
PORT A

There are four modes to choose from: M2 and Ml define
the timer mode, as shown in Figure 11.

TO 8OB5AH RST INPUT

OUTPUT

t

PORT A

A INTR (SIGNALS DATA RECEIVED)

PORT C

"."''',o,,'"''~,

I

A STB (ACKNOWL DATA RECEIVED)

III

B STS (LOADS PORT B LATCH)
B BF (SIGNALS BUFFER IS FULL)

B INTR (SIGNALS BUFFER

}

TIMER OUT WAVEFORMS
TO/FROM

MODE

PERIPHERAL

1

START
COUNT

BITS

INTERFACE"

M2

Ml

o

0

TERMINAL
COUNT

~

(TERMINAL)
COUNT

_____ l ____ _

1 SINGLE
SQUARE WAVE

READY FOR READINGI.l
PORT B A. INPUT

•

TO INPUT PORT (OPTIONALI

2 CONTINUOUS
SQUARE WAVE

TO BOB5AH RST INPUT

3 SINGLE
PULSE ON,
TERMINAL COUNT
4. CONTINUOUS
PULSES

Figure 9. Example: Command Register

=

00111001
2-30

v-----------

u

Figure 11. Timer Modes

8155H/8156H/8155H-2/8156H-2

The counter in the 8155H is not initialized to any particular
mode or count when hardware RESET occurs, but RESET
does stop the counting. Therefore, counting cannot begin
following RESET until a START command is issued via the
CIS register.

Bits 6-7 (Tfv12 and TM1) of command register contents
are used to start and stop the counter. There are four
commands to choose from:
TM2

TM1

o
o

0

NOP - Do not affect counter operation.
STOP - NOP if timer has not started;
stop counting if the timer is running

o

Please note that the timer circuit on the 8155H/8156H chip
IS designed to be a square-wave timer, not an event
counter. To achieve thiS, it counts down by twos tWice
In completing one cycle. Thus, its registers do not contain values directly representing the number of TIMER IN
pulses received. You cannot load an initial value of 1 into
the count register and cause the timer to operate, as its
terminal count value IS 10 (binary) or 2 (decimal). (For
the detection of single pulses, it is suggested that one
of the hardware interrupt pins on the 8085AH be used.)
After the timer has started counting down, the values
residing in the count registers can be used to calculate
the actual number of TIMER IN pulses required to complete the timer cycle if desired. To obtain the remaining
count, perform the following operations in order:

STOP AFTER TC - Stop Immediately
after present TC is reached (NOP if timer
has not started)
START - Load mode and CNT length
and start immediately after loading (If
timer is not presently running). If timer
is running, start the new mode and CNT
length immediately after present TC is
reached.

Note that while the counter IS counting, you may load a
new count and mode into the count length registers
Before the new count and mode will be used by the
counter, you must issue a START command to the
counter. This applies even though you may only want to
change the count and use the prevIous mode.

Stop the count
2. Read

In

the 16-blt value from the count length registers

3. Reset the upper two mode bits

In case of an odd-numbered count, the first half-cycle
of the squarewave output, which IS high, is one count
longer than the second (low) half-cycle, as shown In
Figure 12.

4. Reset the carry and rotate right one position all 16 bits
through carry
5. If carry IS set, add 1/2 of the full original count (1/2 full
count - 1 if full count is odd).

Note: If you started with an odd count and you read the
count length register before the third count pulse occurs,
you will not be able to discern whether one or two counts
has occurred. Regardless of this, the 8155H/56H always
counts out the right number of pulses in generating the
TIMER OUT waveforms.
NOTE 5 AND 4 REFER TO THE NUMBER OJ" CLOCKS IN THAT TIME PERIOD

Figure 12. Asymmetrical Square-Wave Output
Resulting from Count of 9

2-31

inter,.

8155H/8156H/8155H-2/8156H-2

808SA MINIMUM SYSTEM CONFIGURATION
Figure 13a shows a minimum system using three chips,
containing:
•
•
•
•
•

256 Bytes RAM
2K Bytes EPROM
381/0 Pins
1 Interval Ti mer
4 Interrupt Levels

8085 MINIMUM SYSTEM CONFIGURATION

A8-15

r...
ADO-1

"

I.

ALE

8085AH

~

C>

RD

V

;.

f----.t--t--f----f----f-----

~

101M
elK
RESET OUT
READY

Vee
TIMER

WR AD

IN

RESET

ALE

7-

eE ..;

101M

7-~~~ 7~D
0-7

CE '~I

ALE

iIDliOil I=lKRS

I
T6~~R_

,

B
815611

'--7l

-'-CONTROL

-

LATCHES

I
I
266)( 8
RAM

8755A [EPROM + I/0j

t

~cPcP~

B BB

I

BB

Figure 13a. 8085AH Minimum System Configuration (Memory Mapped 1/0)

2-32

ROY

.

inter

8155H/8156H/8155H-218156H-2

• 381/0 Pins

8088 FIVE CHIP SYSTEM
Figure 13b shows a five chip system containing:

• 1 Interval Timer

• 1.2SK Bytes RAM

• 2 Interrupt Levels

• 2K Bytes EPROM

/}

0-

Vss

Vee

I I

II+-

PORr~

CE
~+---_VIR
_ _ Rij

PORT

~
(8)

815614-2 8

PORT~

ALE
DATAl

C

(6)

-,/ ADDR

IN_
101M TIMER
OUT f-RESET

~

Aa-A19 ~OoR
ClKADo - AD 7

,-

~

ADDRIDATA

lOW
Rij

h
J~

ALE

~

8088

READY

rl

X,

RST

lID

X,
ClK

READY

I--

V

8284

ALE

l-

I-

Rij

l-

f- +-

\vR

l-

101M

I-

--y

ADDR

I

RESET

101M

~-

I-

PORT
8

READY

Vee

VIR
Rij

CD

CE1 8185-2
ALE

\115-1II-I-

CS.
CE,

As.Ag

V

ADo_7
--y

JJ
Vss

Figure l3b. 8088 Five Chip System Configuration

2-33

LROG

Vss Vee Voo

Vee

...."

pV

iOR ....J

111

I-

RESET

RCYl

8755A-2

DATAl

.---

RES

pV

A S_10

MN/MX I--Vee

O

PORT
A

CE

Vee

8155H/8156H/8155H-2/8156H-2

ABSOLUTE MAXIMUM RATINGS*
TemperatureUnderBlas ................ OOeto+70oe
Storage Temperature ........; ....... -65°C to +150 oe
Voltage on Any Pin
With Respect to Ground ............... -0.5V to +7V
Power Dissipation ............................. 1 5W

'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specificatIOn is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

D.C. CHARACTERISTICS

::!:

(TA = ooe to 70°C, Vee = 5V

10%)

Symbol

Parameter

Min.

Max.

Units

VIL

Input Low Voltage

-0.5

0.8

V

VIH

Input High Voltage

2.0

Vee+{)·5

V

VOL

Output Low Voltage

0.45

V

IOL

VOH

Output High Voltage

V

IOH

2.4

IlL

I n put Lea kage

ILO

Output Leakage Current

lec

Vee Supply Current

IIL(CE)

Chip Enable Leakage
815"5H
8156H

A.C. CHARACTERISTICS

= 2mA
= -400!.£A

±10

!.£A

OV,s; VIN ,s; Vee

±1O

!.£A

0.45V <; VOUT <; Vee

125

mA

+100
-100
(TA

Test Conditions

= ooe to 70°C, Vee = 5V

!J.A
!J.A

OV,s; VIN,s; Vee

±10%)

8155H/8156H

8155H-2/8156H-2

Symbol

Parameter

tAL

Address to Latch Set Up Time

50

30

tLA

Address Hold Time after Latch

80

30

ns

tLe

Latch to R EADIWR ITE Control

100

40

ns

tAO

Valid Data Out Delay from READ Control

170

140

ns

tLO

Latch to Data Out Valid

350

270

ns

tAD

Address Stable to Data Out Valid

400

330

ns

Min.

100

Max.

/

Min.

Max.

Units
ns

tlL

Latch Enable Width

tROF

Data Bus Float After READ

0

70

tCl

READ/WRITE Control to Latch Enable

20

10

ns

tee

R EADIWR ITE Control Width

250

200

ns

tow

Data In to WRITE Set Up Time

150

100

ns

two

Data In Hold Time After WR ITE

25

25

ns

tRV

Recovery Time Between Controls

300

200

twp

WR ITE to Port Output

tpA

Port Input Setup Time

70

tAP

Port Input Hold Time

50

tSBF

Strobe to Buffer Full

tss

Strobe Width

tABE

READ to Buffer Empty

400

300

ns

tSI

Strobe to I NTR On

400

300

ns

100

0

400

ns
ns

50

ns

10

200

ns

ns
300

400

2-34

ns
80

300

ns
ns

150

8155H/8156H/8155H-2/8156H-2

A.C. CHARACTERISTICS

(Continued) (TA

= O°C to 70°C, Vee = 5V ±10%)
8155H/8156H

Symbol

Parameter

8155H-2/8156H-2

Max.

Min.

Min.

Max.

Units

300

ns

tRDI

READ to INTR Off

400

tpss

Port Setup Time to Strobe Strobe

50

0

tpHS

Port Hold Time After Strobe

120

100

tSBE

Strobe to Buffer Empty

400

300

ns

tWBF

WR ITE to Buffer Full

400

300

ns

tWI

WRITE to INTR Off

400

300

ns

tTL

TIMER-IN to TIMER-OUT Low

400

300

ns

400

300

ns

ns
ns

tTH

TIMER-IN to TIMER-OUT High

tRDE

Data Bus Enable from READ Control

10

10

ns

t,

TIMER-IN Low Time

80

40

ns

t2

TIMER-IN High Time

120

70

ns

tWT

WRITE to TIMER-IN
(for writes which start counting)

360

200

ns

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

INPUT/OUTPUT
DEVICE
UNDER

rEST

ifcLe1soPF

-=

A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND a BV FOR A LOGIC 0

CL "" 150pF
C L INCLUDES JIG CAPACITANCE

WAVEFORMS
READ
CE (B155H I

--""-

OR

~

CE (8156HI

1\

\

101M

V

\

'AD

1<

7

--'LA--

- t AL AL E

2

ADDRESS

/

DATA VALID

~
I

\
...,t RDE _

--'LL--

\--'RD--

RD

l/

--'CL-

- - - t LC -

r-----'CC'LO
2-35

I-tRDF-

_ t RV -

1"-

8155H/8156H/8155H-2/8156H-2

WAVEFORMS (Continued)
WRITE

\

V

\

CE(8156H)

/

~I\

/

101M

\

V

CE(8155H)
OR

~

ADO_7

~tAL-

~

~tDW~

- t LA -

K

DATA VALID

- - t CL

-

~\

/

ALE

K

ADDRESS

\

~

~tLL-

V
~

'LC

-------:1·

~tWD-

1I

WR

1-----------

tee

----------+-

I~

\-

'WT
tRY

------------

TIMER IN

STROBED INPUT

/

BF

tSBF

\~~-'~~

\

INTR

t pHS

---- tpss
INPUT DATA
FROM PORT

X

~

2-36

'RBE--J
"'i

\

\-) / j

/

8155H/8156H/8155H-2/8156H-2

WAVEFORMS (Continued)
STROBED OUTPUT

/

BF

\ -3 ~~
~K.

STROBE

tWBF

~

INTR

I

'WI

)

\

WR

j

/

/

If~ I--twP

~

OUTPUT DATA
TO PORT

BASIC INPUT

RD

'ee

INPUT

DATA BUS'

BASIC OUTPUT

!._!___"_';~'I,

~-----------K=
~-=

===: ~'-_________

*DATA BUS TIMING IS SHOWN IN FIGURE 7

TIMER OUTPUT COUNTDOWN FROM 5 TO 1
LOAD COUNTER FROM CLR
I

2

I

_I

RELOAD COUNTER FROM CLR

2

1

TIMER IN

our
"

~

TIMER

(PULSE)

{NOTE
1)
___

J"

'T'l"MERouT
(SQUARE WAVE)

"

~

_ _ _(NOTE
_ _1)_ _ _ J "

NOTE 1 THE TIMER OUTPUT IS PERIODIC IF IN AN AUTOMATIC
RELOAD MODE IM1 MODE BIT = 1)

2-37

I

,

inter
8185/8185-2
1024 x 8-BIT STATIC RAM FOR MCS-85@

• Multiplexed Address and Data Bus

• Low Standby Power Dissipation

• Directly Compatible with 8085AH
and iAPX 88 Microprocessors

• Single +5V Supply

• Low Operating Power Dissipation

• High Density 18-Pin Package

The Intel@ 8185 is an 8192-bit static random access memory (RAM) organized as 1024 words by 8-bits using N-channel
Silicon-Gate MOS technology. The multiplexed address and data bus allows the 8185 to interface directly to the 8085A and
iAPX 88 microprocessors to provide a maximum level of system integration. •
The low standby power dissipation minimizes system power requirements when the 8185 is disabled.
The 8185-2 is a high-speed selected version of the 8185 that is compatible with the 5 MHz 8085AH-2 and the 5 MHz iAPX 88.

ADD

Vee

cs

AD,

RD

CE,
CE2
RD
WR
ALE

A~

WR

AD3

ALE

A/W

LOGIC

l
1\
ADo-A07

---v

DATA
BUS

BUFFER

1KxB
RAM
MEMORY
ARRAY

AD.

CS

ADs

CE,

ADs

CE2

A07

As

Vss

As

X-YDECODE

As. As
ALE

~~ur

ADo-A07
As. As
CS
CE,
CE2
ALE
WR

Figure 1. Block Diagram

Figure 2. Pin Configuration

Intel Corporatton Assumes No Responsibilty for the Use of Any Circuitry Other Than CircuItry Embodied

© INTEL CORPORATION. 1980

ADDRESS/DATA LINES
ADDRESS LINES
CHIP SELECT
CHIP ENABLE (101M)
CHIP ENABLE
ADDRESS LATCH ENABLE
WRITE ENABLE

2-38

In

an Intel Product No Other Circuit Patent licenses afe Implied

inter

8185/8185·2

FUNCTIONAL DESCRIPTION
The 8185 has been designed to provide for direct interface
to the multiplexed bus structure and bus timing of the
8085A microprocessor.

---

At the beginning of an 8185 memory access cycle, the 8bit address on ADo-7, As and Ag, and the status of CE, and
CE2 are all latched internally in the8185 by the falling edge
of ALE. If the latched status of both CE, and CE2 are
active, the 8185 powers itself up, but no action occurs until
the CS line goes low and the appropriate Ri5 or WR control
signal input is activated.
The CS input is not latched by the 8185 in order to allow
the maximum amount of time fori address decoding in
selecting the 8185 chip. Maximum power consumption
savings will occur, however, only when CE, and CE2 are
activated selectively to power down the 8185 when it is not
in use. A possible connection would be to wire the 8085A's
101M line to the 8185's CE, input, thereby keeping the
8185 powered down during 1/0 and interrupt cycles.

--

J1D~
X,

X,

TRAP

Vss Vee

III

RESET IN

HOLD

RST7,5

HLDA

RST6.S
RSTS.5

SOD

SOS5A

SID

INTR
RESET

TIiITA
ADDR

---

s,f-s"f--

OUT
AODR/
DATA ALE AD WR IOliVI
ROVelK

18/

Vi' Vr

18/

i~-

CE,

CE2

CS

1

X

X

0

y

IO/Iiit

0

1

1

0

Powered Up and
Function Disable!,]

0

1

0

1

Powered Up and
Enabled

X

0

TIMER

OUT

8

II

W
(6)

~

RD
ALE

~-

~=

CE

"-

PORT
A

AS10

V

fN

8755A
DATAl
ADDR

Power Down and
Function Disable!,]

101M

PORT
B

RESET

RDY

........

~

elK

vs! v!c Joo tROG

NOTES:
X: Don'l Care.
1: Function Disable implies Dala Bus in high impedance slale
and nol writing.
2: CS· = (CEI = 0) • (CE2 = 1). (CS = 0)
CS· = 1 signifies all chip enables and chip selecl aclive

WR
I[!;

eE, 8185
ALE

1+H-

es, eE2
As.A9

Table 2.
Truth Table for
Control and Data Bus Pin Status
(CS·) RD

B

lOW

Power Down and
Function Disablel']

0

PORT

RESET

8185 StatuI

X

WR

ALE
PORT
DATAl
C
ADDR
IN

Table 1.
Truth Table for
Power Down and Function Enable
(CS·)12]·

POR!W

1[!;8156

~

W

eE

ADo.7

v!s

vL

During Data
-WR AD0-7
Portion of Cycle 8185 Function
X Hi-Impedance

X

1

0

1 Data from Memory Read

1

1

0

1

1

1 Hi-Impedance

Data to Memory

Vee

No Function

0

Vee

Figure 3. 8185 In an MCS·85 System

Write
4 Chips:
2K Byles EPROM
1.25K Byles RAM
38110 Lines
1 CounlerlTimer
2 Serial 1/0 Lines
51nterrupllnpuls

Reading, but not·
Driving Data Bus

NOTE:
X: Don'l Care.

2-39

inter

81.85/8185-2

iAPX 88 FIVE CHIP SYSTEM:
•
•
•
•
•

1.25 K Bytes RAM
2K Bytes EPROM
38 I/O Pins
1 Internal Timer
2 Interrupt Levels

Vss

Vee

I I

t--t-T-t----t---t---I

~

POR!

r r - - - - WR
RD
t--t--t--t---J-.

POR~
8155-2

W
W
(8)

PORTW

ALE

DATAl

e

/~~-~~~~--"~ADDR

(6)

IN_

t - - t - - - - I 'O/M TIMER
t - - - . ( RESET OUT I--As- A19 t-----;A"'DC;;CDR;;-----'"

t-+-+---IIOW
t-+-+-t----IRD

ADo - AD7

.---------- eLK

I'-r

ADDRIDATA

t - - t - T - r - - r - - - ,ALE
r--T-t----t---t-t---I CE

f=~~=;:~=;===-1',

8088

-V

, - - READY

vee. ~ D~

~

r-~

I
I'''MA:~~L
GND

RESET

eLK

RES

READY
8284A

I

f- I-r--- r---rr---

ALE
RST®

RD
WR

-

1

RESET t - - - - + - - - - - - - - - t - - - I
Vee
RDY1

....

-

-

POR~~

101M

~-RESET

f

-

101M

r--- [

8755A.2
DATAl
ADDR

MNIMX r--Vcc
I

AB· "

~

READY

Vcr;

iOR -.J

I----t---j--j--t-t-~

1 1 I LROG
Vss Vee Voo

-

t-+-+-t------1RD

(Vss)

t - - i - - - - j eE,
t-i--t-T-r-----1 ALE

8185-2

r--+T--t---t----t------1 CS.
r--+T--t---t----t------1 eE,
r--TT--r---t---t---c- As. Ag
ADO_7

I I

Vss

Figure 4. i,APX 88 Five Chip System Configuration

2-40

Vee

8185/8185-2
ABSOLUTE MAXIMUM RATINGS*

'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Temperature Under Bias .............. O°C to +70°C
Storage Temperature .............. -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .............. -0.5V to +7V
Power Dissipation ............................. 1.5W

D.C. CHARACTERISTICS
Symbol

(TA = O°C to 70°C, Vee = 5V ± 5%)
Min.

Max.

Units

Input Low Voltage

-0.5

0.8

V

V,H

Input High Voltage

2.0

Vee+0.5

V

VOL

Output Low Voltage

0.45

V

VOH

Output High Voltage

V,L

Parameter

Test Conditions

IOL

2.4

IOH

= 2mA
= - 400J,tA

IlL

Input Leakage

±10

J,tA

OV ,;;;V,N ,;;;Vcc

ILO

Output Leakage Current

±10

/J A

0.45V ,.; VOUT ,.; Vee

Icc

Vec Supply Current
Powered Up
Powered Down

100
35

mA
mA

A.C. CHARACTERISTICS

(TA

= O°C to 70°C, Vcc = 5V ±

5%)

8185
Symbol

Parameter

Min.

8185-2
Max.

Min.

Max.

Units

tAL

Address to Latch Set Up Time

50

30

ns

tLA

Address Hold Time After Latch

80

30

ns

tLC

Latch to READ/WRITE Control

100

tRO

Valid Data Out Delay from READ Control

170

140

ns

tLO

ALE to Data Out Valid

300

200

ns

tLL

Latch Enable Width

tRoF

Data Bus Float After READ

80

ns

tCL

READ/WRITE Control to Latch Enable

20

10

ns

tcc

READ/WRITE Control Width

250

200

ns

tow

Data In to WRITE Set Up Time

150

150

ns

two

Data In Hold Time After WRITE

20

20

ns

tsc

Chip Select Set Up to Control Line

10

10

ns

tcs

Chip Select Hold Time After Control

10

10

ns

tALCE

Chip Enable Set Up to ALE Falling

30

10

ns

tLAeE

Chip Enable Hold Time After ALE

50

30

ns

40

100
0

2-41

ns

70
100

0

ns

inter

8185/8185-2

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT
\

INPUT/OUTPUT

=:)(2.0 >

2.4

TEST POINTS

0.8

0.45
A C TESTING

<2.o)C

DEVICE
UNDER
TEST

0.8

iJCL~'50PF

INPUTS ARE DRIVEN AT24V FORA lOGIC 1" AND'045V FOR

A LOGIC "0" TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC "1"

CL = 150 pF,

AND 0 8V FOR A LOGIC "0 .,

CL INCWDES JIG CAPACITANCE

WAVEFORM

ALE

(Ge,"O).
(CE,",)

ADo-AD7

(READ CYCLE)

(AS. AS)

tcc---~'I

(WRITe CYCLE)

---"x-

(SELECTED)

(DESELECTED)

2-42

8205
HIGH SPEED 1 OUT OF 8 BINARY DECODER
• Low Input Load Current - .25 mA
max., 1/6 Standard TTL Input Load
• Minimum Line Reflection - Low
Voltage Diode Input Clamp

• I/O Port or Memory Selector
• Simple Expansion -

Enable Inputs

• High Speed Schottky Bipolar
Technology - 18ns Max. Delay

• Outputs Sink 10 mA min.
• 16-Pin Dual-In-Line Ceramic or
Plastic Package

• Directly Compatible with TTL Logic
Circuits

The Intel@ 8205 decoder can be used for expansion of systems which utilize input ports, output ports, and memory
components with active low chip select input. When the 8205 is enabled, one of its 8 outputs goes "low," thus a single row
of a memory system is selected. The 3-ch ip enable inputs on the 8205 allow easy system expansion. For very large systems,
8205 decoders can be cascaded such that each decoder can drive 8 other decoders for arbitrary memory expansions.
The 8205 is packaged in a standard 16-pin dual in-line package, and its performance is specified over the temperature
range of O°C to + 75°C, ambient. The use of Schottky barrier diode clamped transistors to obtain fast switching speeds
results in higher performance than equivalent devices made with a gold diffussion process.

AO
A,

Ao

16

Vee

A,

A,

15

00

A,

14

0,

8205

13

0,

E,

E,

12

03

E,

E3

11

04

E3

0,

10

°5

GRD

9

06

E1
8205

ADDRESS

ENABLE

A,

A,

A,

E,

E,

E,

0

l

l
l
l
l
H
H
H
H

X
X
X
X
X
X
X

X
X
X
X
X
X
X

X
X
X
X
X
X
X

l
l
l
l
l
l
l
l
l
H
l
H

l
l
l
l
l
l
l
l
l
l
H
H
l
H
H

H
H
H
H
H
H
H
H
l
l
l
l

l

l
H
l
H
l
H

l
l
H
H
l
l
H
H

H

H

l
H

H

H
H

H

H
H
H
H
H
H

H
H

H
H
H
H
H

,

OUTPUTS

7

3

4

H
l
H
H
H
H

H
H
l
H

H

H

H
H

H

l

H

H
H

H
H

H

H

H

H
H
H
H
H

H

H

H
H
H
H

H

H

l
H
H
H
H
H
H
H

H
H
H

H
H
H

H
H

H

H
H

H

H

H
H

"
H
H
H
H
H
L

h

I

H
H
H

H
H

H
H
H

H
H
H

H
H
H
H

l

H
H

H
H
H

l
H
H

H

H

H

H
H
H

H
H
H

H

H

H
H
H
H

Ao A2
E 1 E3
00· 07

Figure 1. Logic Symbol

ADDRESS INPUTS
ENABLE INPUTS
DECODED OUTPUTS

Figure 2. Pin Configuration
2-43

8205

FUNCTIONAL DESCRIPTION
Decoder

o~

A.,

The 8205 contains a one out of eight binary decoder. It ac·
cepts a three bit binary code and by gating this input, creates
an exclusive output that represents the value of the input
code.

A,

0,

A,

6;
0,

For example, if a binary code of 101 was present on the AO,
A 1 and A2 address input lines, and the device was enabled,
an active low signal would appear on the 05 output line.
Note that all of the other output pins are sitting at a logic
high, thus the decoded output is said to be exclusive. The
decoders outputs will follow the truth table shown below in
the same manner for all other input variations.

0.
0;
66
0,

Enable Gate

E,----E,

,,----L..J

When using a decoder it is often necessary to gate the out·
puts with timing or enabling signals so that the exclusive
output of the decoded value is synchronous with the overall
system.

Figure 3. Enable Gate

The 8205 has a built-in function for such gating. The three
enable inputs (El, E2, E3) are ANDed together and create
a single enable signal for the decoder. The combination of
both active "high" and active "low" device enable inputs
provides the designer with a powerfully flexible gating func·
tion to help reduce package count in his system.

ADDRESS

OUTPUTS

A,

A2

E,

E2

E3

a

1

2

3

4

L
H
L
H
L
H

L
L

L
L
L
L
H

L
L
L
L
L
L
L
L
L
H
L
H

L
L
L
L
L
L
L
L
L
L
H
H
L
H
H

H
H
H

L

H
L
H

H
H
L

H
H

H

H
H
H

H

l
H

X
X
X
X
X
X
X

2-44

ENABLE

Ao

H

H
L
L
H
f'

X

H
H

H

X

X
X
X
X
X
X

X

X

X

X
X
X

H
L

H

H
H

H
H
H
L
L
L
L
H

H
H

H
H
H

H
H
H
H
H

H
H
H

H
H
H

H
H
H
H

H
H
H
H

H

H
H
H

H
L
H

H
H
H
L

H
H

H
H

H
H

H
H

H
H

H
H

H
H

H

H
H
H
H

H
H

H

"
.,

6

7

H
H
H

H
H
H

H
H
L

H

H

H
H

H
H
H

L

H
H
H

H

H

H

H

H
H
H

H
H
H
H

H

H

H

H
H
H

H
H
H
H
H

L
H

H
H
H
H
H

H

8205
Applications of the 8205

ray of 8205s can be used to create a simple interface to a
24K memory system.

The 8205 can be used in a wide variety of applications in
microcomputer systems. I/O ports can be decoded from the
address bus, chip select signals can be generated to select
memory devices and the type of machine state such as in
8008 systems can be derived from a simple decoding of the
state lines (SO, Sl, S2) of the 8008 cpu.

1/0 PORT DECODER
Shown in the figure below is a typical application of the
8205. Address input lines are decoded by a group of 82055
(3). Each input has a binary weight. For example, AO is as·
signed a value of 1 and is the LSB; A4 is assigned a value of
16 and is the MSB. By connecting them to the decoders as
shown, an active low signal that is exclusive in nature and
represents the value of the input address lines, i~ available at
the outputs of the 8205s.
This circuit can be used to generate enable signals for I/O
ports or any other decoder related application.
Note that no external gating is required to decode up to 24
exclusive devices and that a simple addition of an inverter
or two will allow expansion to even larger decoder net·
works.

The memory devices used can be either ROM or RAM and
are 1K in storage capacity. 2708s and 2114As are devices
typically used for this application. This type of memory
device has ten (10) address inputs and an active "low"
chip select (CS). The lower order address bits AG-A9
which come from the microprocessor are "bussed" to all
memory elements and the chip select to enable a specific
device or group of devices comes from the array of 8205s.
The output ofthe 8205 is active low so it is directly compatible with the memory components.
8asic operation is that the CPU issues an address to identify
a specific memory location inwhich it wishes to "write" or
"read" data. The most significant address bits A 10·A 14 are
decoded by the array of 8205s and an exclusive, active low,
chip select is generated that enables a specific memory de·
vice. The least significant address bits AO-A9 identify a
specific location within the selected device. Thus, all ad'
dresses throughout the entire memory array are exclusive
in nature and are non· redundant.
This technique can be expanded almost indefinitely to sup·
port even larger systems with the addition of a few inverters
and an extra decoder (8205).

CHIP SELECT DECODER
Using a very similar circuit to the I/O port decoder, an ar·

A"

A,\L _ _ _ _ _ _ _ _- . )

A,

0,
0,

p---p----

A,

A,
A,

0,

p....-

A,

0,

p----

820S

E,

p....0, p....-

E,

0,

E,

0,

°0,
0

A,

~A,

I-I--

p---p---p---p---p---p---o,p---0,

0,

A,

E,

E;

0,

11

0,

12

0,

13

o,p.:-

E,

C--- A,

0,

""RT

eND

' - - - - - A,

0,

c>--

_A,

0,

c>--

c>-- '9

0,

c>-- 20

EN

0,
0,

c>-- 22

E,

0,

c>-- 23

0-7 :::;---

I

Figure 4. 1/0 Port Decoder

::>-- eS a

~A,

0; ::r---- CS'O

0-; :)----- ts;,
8205

0;

_0.

OS;;

r;

0;0-- ~

E,

o,p-- ~4

E,

0;

CHIP
SELECTS

p....- CS;-"

1=>--- CS'6
0, p....- ~
0·, p....- ~
0; p....- CS,-g
O~

-A,
-A,

I
820S

I

CS 7

I

~~A2

I

0------ CS;;

~o-- CS g

I

c>--

E;

E,

~

,
,

I

8205

E,

06

~A,

I

18

0,

Os J------ es,

E;

~A"

15

c>-- 16

0, ::>--- cs-]
6; ::>--- es,

E,

NUMBERS

14

CS,

D------ CS,

I

It-

0,

A,
8205

EN

p---p----

C>--------

6; ::r---- es,
8205

0,

A,

~~MORIES

o,p-- es"

E,

6;p....- cs;,

E,

0;

E,

a,p....- CS;;

p---- CS;;

Figure 5. 24K Memory Interface
2-45

8205

ABSOLUTE MAXIMUM RATINGS·
Tempera~ure underlias:

°
°
Ceramic .......................... -65 C to +125 C
Plastic ............................ -65°C to + 75°C
Stcrage Temperature ............... -65°C to +160°C
All Output or Supply Voltages ........ -0.5 to +7 Volts
All Input Voltages .................. -1.0 to +5.5 Volts
Output Currents ............................. 125 mA

"NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or at any other condition above
those indicated in the operational sections of this specificatioll is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

D.C. CHARACTERISTICS (TA = O°C to +75°C. Vee = 5V ±5%)
Symbol

Parameter

Limit
. MaX:-

Min.

INPUT LOAD CURRENT

IF

Unit

-i--~-

Test Conditions
:~

rnA

-025

"--

Vee = 5.25V, V F = 0.45V

-~

IR

INPUT LEAKAGE CURRENT

Ve

INPUT FORWARD CLAMP VOLTAGE
V
-10
------OUTPUT "LOW" VOL TAGE
V
045
- .. -------.. _ - - -V
OUTPUT HIGH VOLTAGE
24
-_..._------ - - ---- _ . _ - - i-~-.- - _ .
INPUT "LOW" VOLTAGE
0.85
V
- - -1 - - . - - INPUT "HIGH"~VOLTAC;E~' . - 2.0
V
. _ - - - _ . - _._-- . _.. _- - - _ .
-40
OUTPUT HIGH SHORT
-120
rnA
CIRCUIT CURRENT

VOL

10

Vee = 5 25V, V R = '5.25V

I'A

Vee = 4 75V, Ie = -5.0 rnA
Vee = 4 75V. IOL = 10.0 rnA

---~

VOH
V IL
V IH
Ise

Vee = 4.75V. IOH

= -1.5 rnA
~-

Vee=50V

._...

Vee=50V
..-

~.

Vee = 5.0V, VOUT = OV
..

.---~------

Vox

OUTPUT "LOW" VOLTAGE
@ HIGH CURRENT

lee

POWER SUPPL Y CURRENT

A.C. CHARACTERISTICS (TA
Symbol

= O°C to

08
70

+ 75°C. Vee

Parameter

t -+

ADDRESS OR ENABLE TO
OUTPUT DELAY

t+
t
CIN

(1,

1 This parameter

INPUT CAPACITANCE
IS

rnA

Vee = 525V

lox

-

= 40 rnA

Test Conditions

Unit

18

ns

18

ns

18

ns

18

ns

4(typ)
5(typ.)

P8205
C8205

Vee

= 5V ±5%; unless otherwise specified)

Max. Limit

'+ +

= 5.0V,

V

pF
pF

I = , MHz. Vee = OV
VBIAS = 2.0V. TA • 250 e

periOdically sampled and IS not 1 OQ"'o tested

TYPICAL CHARACTERISTICS
OUTPUT CURRENT VS.
OUTPUT "LOW" VOLTAGE

OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE

DATA TRANSFER FUNCTION
50

20

40

40

10

80

i-t-+-r--+'-Ij.

20

·30

20

~40

, 0

~

, 0

OUTPUT "LOW" VOL lAGE (VI

--t-

50 '---'----i-.....~I..--'--_'__'____'_J......I
10
o
20
30
40
50
OUTPUT 'HIGH" VOL TAGE (V)

2-46

4

6

8

10 1214 16 18 20

INPUT VOL lAGE (V)

8205

TYPICAL CHARACTERISTICS (Continued)
ADDRESS OR ENABLE TO OUTPUT
DELAY VS. LOAD CAPACITANCE

ADDRESS OR ENABLE TO OUTPUT
DELAY VS. AMBIENT TEMPERATURE

20,.------------..,
Vee ~ 5.OV
TA = 25"C

..
~~

g

20,-------------,

,,
"

15

t+_,L_

~

Ww

\SO
~5

--------~~---------10

'++

2i§

!;i)

0~0---~2~5---~50~--~75

0
0

50

150

100

200

AMBIENT TEMPERATURE rC)

LOAO CAPACITANCE (PF)

SWITCHING CHARACTERISTICS
TEST LOAD
CONDITIONS OF TEST:

TEST LOAD:
39011

Input pulse amplitudes: 2.5V
Input rise and fall times: 5 nsec
between 1V and 2V
Measurements are made at 1.5V

All TranSIstors 2N2369 or EQuIvalent

CL = 30 pF

WAVEFORMS

ADDRESS OR ENABLE
INPUT PULSE

--I
.

OUTPUT

..

~ -.-.--------------~
~ _______________ _

______ • _______ J

2-47

8224
CLOCK GENERATOR AND DRIVER
FOR 8080A CPU
Single Chip Clock Generator/Driver for
• BOBOA
CPU

• Power-Up Reset for CPU
• Ready Synchronizing Flip-Flop
• Advanced Status Strobe,

O-scillator Output for External System
• Timing
Controlled for Stable System
• Crystal
Operation
• Reduces System Package Count
in EXPRESS
• Available
- Standard Temperature Range

The Intel® 8224 is a single chip clock generator/driver for the 8080A CPU. It is controlled by a crystal, selected by the
designer to meet a variety of system speed requirements.
Also included are circuits to provide power-up

res~t,

advance status strobe, and synchronization of ready.

The 8224 provides the designer with a significant reduction of packages used to generate clocks and timing for 8080A.

I)D

XTAL1
OSC

1!9

XTAL2

@>

TANK

13>

RESET

Vee

RESIN

XTAL 1

RDYIN

¢,

"

XTAL 2

READY

lD>

TANK

rf!2 (TTL)

.,

STSTB

~2

OSC

SYNC

ij9

¢2(TTU[D.

GND

lD

SYNC

'D

RESIN

[D

RDYIN

STSTB

!I>-

RESET

[!>

READY~

RESiN

RESET INPUT

RESET

RESET OUTPUT

RDYIN

READY INPUT

READY

READY OUTPUT

SYNC

SYNC INPUT

XTAL 1
XTAl2
TANK
OSC

STSTB

STATUS STB

¢2 (TTL)

¢2 elK (TTL LEVEL)

Vee

+5V

8090

Voo

+12V

CLOCKS

GND

OV

.,

~

Figure 1. Block Diagram

Voo

!

(ACTIVE LOW)

(

CONNECTIONS
FOR CRVSTAL

USED WITH OVERTONE XTAl
OSCILLATOR OUTPUT

Figure 2. Pin Configuration

2-48

8224
ABSOLUTE MAXIMUM RATINGS·

*NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Temperature Under Bias . . . . . . . . . . . . . . . 2°C to 70:C
Storage Temperature . . . . . . . . . . . . . . -65 C to 15El C
Supply Voltage, Vee . . . . . . . . . . . . . . . . -0.5V to +7V
Supply Voltage, Voo . . . . . . . . . . . . . . -0.5V to +13.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . -1.5V to +7V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 100mA

D.C. CHARACTERISTICS
Symbol

(TA

=

O°C to 70°C. Vee

+5.0V ±5%. VOD

Limits
Typ.

=

+12V ±5%)

Max.

Units

IF

Input Current Loading

-.25

mA

VF

~

.45V

IR

Input Leakage Current

10

/lA

VR

~

5.25V

Ve

I nput Forward Clamp Voltage

1.0

V

Ie

V 1l

Input "Low" Voltage

V 1H

Input "High" Voltage

2.6
2.0

V1WV1l

RESIN Input Hysteresis

.25

VOL

Output "Low" Voltage

VOH

Parameter

=

Output "High" Voltage
<1>, , <1>2
READY, RESET
All Other Outputs

Min.

.8

Vee

Reset Input
All Other Inputs

V

Vee ~ 5.0V

.45

V

(<1>1,<1>2), Ready, Reset, STSTB
IOl ~2.5mA
All Other Outputs
IOl ~ 15mA

Power Supply Current

115

mA

Power Supply Current

12

mA

For crystal frequencies of 18 MHz connect 5100 regIsters between the X11nput and ground as
well as the X2 Input and ground to prevent QscHlatlon at harmonic frequencies

2-49

5.0V

V

Icc

·Wlth tank CirCUit use 3rd overtone mode

~

V

V
V
V

Tolerance: 0.005% at 0·C-70·C
Resonance: Series (Fundamental)*
Load Capacitance: 20-35 pF
Equivalent Resistance: 75-20 ohms
Power Dissipation (Min): 4 mW

-5mA

.45

9.4
3.6
2.4

Crystal Requirements

~

V

IDO
Note 1

Test Conditions

IOH ~ -1 OO/lA
IOH ~ -100/lA
IOH ~ -lmA

".nf_r
'ell

82244

I I

A.C. C;:HARACTERISTICS
Symbol

(Vee

= +5.0V ±5%, Voo = +12.0V ±5%, TA = O°C to 70°C)

Parameter

tq,1

<1>1 Pulse Width,

2tcy _ 20ns
9

t2

<1>2 Pulse Width

5tcy _ 35ns
9

tOl

<1>1 to <1>2 Delay

0

t02

<1>2 to <1>1 Delay

2tcy _ 14ns
9

t03

<1>1 to <1>2 Delay

2tcy
9

tR

<1>1 and <1>2 Rise Time

tF

<1>1 and <1>2 Fall Time

to2

<1>2 to <1>2 (TTL) Delay

toss

Limits
Typ.

Min.

Max.

Units

Test
Conditions

ns
CL = 20pF to 50pF
2tcy + 20ns
9
20
20

-5

+15

<1>2 to STSTB Delay

6tcy _ 30ns
9

6tcy
9

tpw

STSTB Pulse Width

t~y _ 15ns

tORS

RDYIN Setup Time to
Status Strobe

50ns _ 4tcy
9

tORH

RDYIN Hold Time
After STSTB

tOR

RDYIN or RESIN to
<1>2 Delay

tCLK

ClK Period

jf max

Maximum Oscillating
Frequency

27

MHz

Cin

Input Capacitance

8

pF

ns

2TTl,Cl=30
R1=300n
R2=600n

STSTB, Cl=15pF
Rl = 2K
R2 = 4K

9

4tcy
9
Ready & Reset
Cl=10pF
Rl=2K
R2=4K

4tcy _ 25ns
9

tcy
9

,

,

2-50

Vcc=+5.0V
Voo=+12V
VB IAS=2.5V
f=1 MHz

i~·

8224

A.C. CHARACTERISTICS (Continued)

Symbol

Parameter

(For tCY = 488.28 ns) (TA
Voo = +12V ±5%)

Min.

Limits
Typ.

= O·C to 70·C. Voo = +5V ±5%.

Max.

Units

tq,1

t/>1 Pulse Width

89

ns

t4>2

t/>2 Pulse Width

236

ns
ns

t01

Delay t/>1 to t/>2

0

t02

Delay t/>2 to t/>1

95

t03

Delay t/>1 to t/J2 Leading Edges

109

tr
tf
toss

t/>2 to STSTB Delay

t04>2

t/>2 to t/J2 (TTL) Delay

tpw

Status Strobe Pulse Width

40

ns

tORS

RDYIN SetupTimeto STSTB

-167

ns

tORH

RDYIN Hold Time after STSTB

217

ns

tOR

READY or RESET
to t/J2 Delay

192

ns

fMAX

Oscillator Frequency

ns
129

ns

Output Rise Time

20

ns

Output Fall Time

20

ns

296

326

ns

-5

+15

ns

18.432

A.C. TESTING INPUT, OUTPUT WAVEFORM

Test Conditions
tCy=488.28ns

r- t/>1 & t/J2 Loaded to
CL = 20 to 50pF

Ready & Reset Loaded
to 2mA/10pF
All measurements
referenced to 1.5 V
unless specified
otherwise.

MHz

A.C. TESTING LOAD CIRCUIT

INPUT/OUTPUT

j"Vcc

"~u >

045

08

TEST POINTS

<":C

R,
DEVICE
UNDER
TEST

08

R,

-=

,-

AC TESTING INPUTS ARE DRIVENAT24V FORA LOGIC"1 " ANDO.45VFOR
A LOGIC "0 "TIMING MEASUREMENTS ARE MADEAT2 OV FORA LOGIC "1"
AND 0 BV FOR A LOGIC "0" (UNLESS OTHERWISE NOTED)

CL INCWDE$ JIG CAPACITANCE

2-51

inter

8224

WAVEFORMS

.,

\

.,

SYNC
(FROM 8080A)

I

I--.--------toss------

1-------tDRH----~1

"\Ir---------'\I, - - - - - - - - -

- - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - '\~-----+------------

READY OUT

-------------'1'- - - - - - - - - - - - - - - - - - - - - - - - - - - .

RESET OUT

VOLTAGE MEASUREMENT POINTS: <1>,. <1>2 Logic "0"

= 1.0V. logic "'" = a.ov.

All other signals meesured at 1.5V.

CLOCK HIGH AND LOW TIME (USING X1, X2)

18MHz

$

X,
X2

R,

":"

R2

-

2-52

elK

8228/8238
SYSTEM CONTROLLER AND BUS DRIVER
FOR 8080A CPU
• Single Chip System Control for
MCS-80® Systems

• User Selected Single Level Interrupt
Vector (RST 7)
• 28·Pin Dual In· Line Package

• Bullt·ln Bidirectional Bus Driver for
Data Bus Isolation

Ii Reduces System Package Count

• 8238 Had Advanced IOW/MEMW for
Large System Timing Control

• A"ows the Use of Multiple Byte
Instructions (e.g. CALL) for Interrupt
Acknowledge

• Available in EXPRESS
- Standard Temperature Range

The Intel'" 8228 Is a single chip system controller and bus driver for MCS·80. It generates ail signals required to
directly interface MCS·80 family RAM, ROM, and 1/0 components.
A bidirectional bus driver is included to provide high system TTL fan·out. It also provides isolation of the 8080 data bus
from memory and 1/0. This allows for the optimization of control signals, enabling the systems designer to use slower
memory and 1/0. The isolation of the bus driver also provides for enhanced system noise immunity.
A user selected single level interrupt vector (RST 7) is provided to simplify real time, interrupt driven, smail system
requirements. The 8228 also generates the correct control signals to ailow the use of multiple byte instructions (e.g.,
CALL) in response to an interrupt acknowledge by the 8080A. This feature permits large, interrupt driven systems to
have an unlimited number of interrupt levels.
The 8228 is designed to support a wide variety of system bus structures and also reduce system package count for
cost effective, reliable design of the MCS·80 systems.
Note: The specificallons for the 3228/3238 are identical with those for the 8228/8238

CPU
DATA
BUS

r~

-~t
=

0,_

- 0 81

°2°3-

- 0 82

.-,°°5' 0
°6,4 -

g:~

SYSTEM DATA BUS

STSTB

v"

HlDA

I/aw

WR

- 0 85
- D B6

MEMW

i70R

OBIN

- O B7

084
DRIVER CONTROL

~''''"'

MEMR

04

INTA

iiUsEN

DB'
;;m;nI

06

0'

IroM'i

DB3

LATCH

GAriNG
ARRAY

i70R

03

I/OW

DB2

STSTS

DBS
OS

DB.

02

OBIN

01

- - BUS!N

WFi
HLDA

OBl

iNTA

Figure 1. Block Diagram

011

INTA

INTERRUPT ACKNOWLEDGE

0700

DATA BUS !8080 SIDE)

DB7 aBO

DATA BUS (SYSTEM SIDE)

HLDA

HLDA (FROM 8080)

IIOR
I/OW
MEMR

I/ORUD
I/O WRITE
MEMORY READ

\VIi
iJUSEN

WR I FROM 80801
BUS ENABLE INPUT
STATUS STROBe (FROM 8224)

MEMW
OBIN

MEMORY WRITE
OalN (FROM 80801

STSTB

Vee

••v

GNO

o VOLTS

Figure 2. Pin Configuration
2-53

IntJ

8228/8238

ABSOLUTE MAXIMUM RATINGS·

'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This Is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated In the operational sections of this specifi·
cation is not limited. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Temperature Under Bias .....•.•...... - O·C to 70·C
Storage Temperature ...•..•.••..•. - 65°C to 150°C
Supply Voltage, Vee ............••••. -_0.5V to + 7V
Input Voltage ......................• - 1.5V to + 7V
Output Current. ......•................... 100 mA

D.C. CHARACTERISTICS
Symbol

(TA

= o·c to 70·C, Vcc = 5V ±5%)

Parameter

Ve

Input Clamp Voltage. All Inputs

IF

Input Load Current,
STSTB
02&

Os

Limits
Min. Typ.(1) Max.

Unit

.75

V

Vee=4.75V; IC=-5mA

500

IlA

Vcc=5.25V

750

IlA

VF=0.45V

--&,

250

All Other Inputs
Input Leakage Current
STSTB

IlA

Vcc=5.25V

20

IlA

VR =5.25V

All Other Inputs

100

IlA

Input Threshold Volt!lge, All Inputs
Power Supply Current

VOL

2.0

V

190

mA

Output Low Voltage,
00-0 7

.45

V

Vcc=4.75V; 10L =2mA

All Other Outputs

.45

V

10L = 10mA

0.8
140

Output High Voltage,
00-0 7

3.6

All Other Outputs

2.4

los

Short Circu it Cur-rent, All Outputs

10 (off)

Off State Output Current,
All Control Outputs

Not. 1:

IlA

100

Icc

liNT

250

OBo·OB7

VTH

VOH

Test Conditions

~A

00,0,.04. 05,
& 07

IR

-1.0

3.8

15

INTA Current

2-54

Vcc=5.25V

V

Vcc=4.75V; lOH=-10IlA

V

10H = -lmA

90

mA

Vcc=5V

100

IlA

Vcc=5.25V; Vo=5.25

-100

IlA

Vo=·45V

mA

(See INTA Test Circuit)
.-

5

Typical values are for T A = 250 C and nominal supply voltages.

Vcc=5V

--

----

inter

8228/8238

CAPACITANCE
This parameter

IS

(VBIAS

= 2.5V, Vee = 5.0V, TA = 25°C, f = 1 MHz)

periodically sampled and not 100% tested.

limits
Parameter

Symbol

Min.

Typ.lll

Max.

Unit

C,N

Input Capacitance

8

12

pF

GoUT

Output Capacitance
Control Signals

7

15

pF

I/O

I/O Capacitance
(D or DB)

8

15

pF

A.C. CHARACTERISTICS

(TA

=

O°C to 70°C, Vee

=

5V ±5%)

limits
Symbol

Parameter

Min.

Max.

Units

tpw

Width of Status Strobe

22

ns

tss

Setup Time, Status Inputs Do·D 7

8

ns

tSH

Hold Time, Status Inputs Do·D 7

5

toc

Delay from STSTB to any Control Signal

20

Condition

ns
60

--

ns

CL = 100pF

ns

tRR

Delay from DBIN to Control Outputs

30

tRE

Delay from DBIN to Enable/Disable 8080 Bus

45

ns

CL = 100pF
----C L = 25pF

tRO

Delay from System Bus to 8080 Bus dUring Read

30

ns

CL = 25pF

45

ns

CL = 100pF

30

ns

CL = 100pF

ns

CL = 100pF
C L = 100pF

t-~

tWR

Delay from WR to Control Outputs

tWE

Delay to Enable System Bus DBo·DB7 after STSTB

two

Delay from 8080 Bus 0 0 -0 7 to System Bus
DBO-DB7 during Write

/-----f--

5

5

j---------

40

tE

Delay from System Bus Enable to System Bus DB o ·DB 7

30

ns

tHO

HLDA to Read Status Outputs

25

ns

tos

Setup Time, System Bus Inputs to H LOA

10

ns

tOH

Hold Time, System Bus Inputs to HLDA

20

ns

C L = 100pF

+12V

A.C. TESTING LOAD CIRCUIT
1KH'10%

-rVcc
R,
8228

OEVICE

UNOER
TEST

23
INTA

p------~

For 00-07: Rl = 4Kn, R2 = ~n,
CL = 2SpF. For ~II other outputs'
Rl = soon, R2 = 1 KP., CL = 100pF.

INTA Test Circuit (for RST 7)
2-55

8228}8238

WAVEFORM

.,
., _ _ _ _J

________

-+~tMv--~------------,_-~

STATUSSTFioiE

MMroDATABUS _________

OBIN

-J)(~_+_+--~~~------------------------------------------t~
,,;;--1

+= -

\.

-------------r-r----~I

I\,

INTA. lOR. MfpjiR

--1'RR

rlr---------

N-----~------~

I..
HLDA _ _ _ _ _ _ _ _t-;-___;-__--1
'oc-

INTA. lOR. MElitR

DURING HLDA

SYSTEM BUS DURING READ

--------n\'+-___+ ___- +JJI,'I"'"

__

--- -- - -,--------

B0808USDURINGREAD

.1_tDS ___

~

-----I

~

I- ___

_________

'R.-

tD~.

X
Ef
_

'R~ _ _ _ _ _ _ _ _ _ _ _ _ _

r---'_
I",

\

IOWOR

tHO

I

'wR-1 .1-11-'wR
___________ ~\----~l

MEMW

8080 BUS DURING WRITE

SYSTEM BUS DURING WRITE -

-

-

-

-

-

-

-

-,'

<

I

- 'w.SYSTEM BUS ENA8LE

SYSTEMBUSQUTPUTS- -

-

-

-

-

-

-

-

-

-

-

-

J
-

-

'

j

'E~r
 - - - - - - - - - - - - --

VOLTAGE MEASUREMENT POINTS: 00-07 (when outputs) Logic "0"
at 1.5V.
"ADVANCED IOW/MEMW FOR 8238 ONLY.

2-56

= O.BV. Logic "I" = 3.0V.

All other signals measured

8237A/8237A-4/8237A-5

HIGH PERFORMANCE
PROGRAMMABLE DMA CONTROLLER
performance: Transfers up to 1.6M
• High
Bytes/Second with 5 MHz 8237A·5

Enable/Disable Control of Individual
• DMA
Requests

Directly Expandable to any Number of
• Channels
End of Process Input for Terminating
• Transfers
• Software DMA Requests

• Four Independent DMA Channels
Independent Autoinitialization of all
• Channels

• Memory·to·Memory Transfers
• Memory Block Initialization

Independent Polarity Control for DREQ
• and
DACK Signals
in EXPRESS
• Available
- Standard Temperature Range

• Address Increment or Decrement

The 8237A Multimode Direct Memory Access (DMA) Controller is a peripheral interface circuit for microprocessor systems. It is designed to improve system performance by allowing external devices to directly transfer information from
the system memory. Memory-to-memory transfer capability is also provided. The 8237A offers a wide variety of programmable control features to enhance data throughput and system optimization and to allow dynamic reconfiguralion under program control.
The 8237A is designed to be used in conjunction with an external 8-bit address register such as the 8282. It contains
four independent channels and may be expanded to any number of channels by cascading additional controller chips.
The three basic transfer modes allow programmability of the types of DMA service by the user. Each channel can be
individually programmed to Autoinitialize ,to its original condition following an End of Process (EOP).
Each channel has a full 64K address and word count capability.
The 8237A-4 and 8237A-5 are 4 MHz and 5 MHz selected versions of the standard 3 MHz 8237A respectively.

ffiW
MEMW

COMMANO

CONTROL

A'N
Vcc(+5V)

HRQ

'"

OB'

RESET

OB'

Figure 2.
Figure 1. Block Diagram
2-57

Pin Configuration

intJ

8237 A/8237 A-4/8237 A-5
Table 1. Pin Description

Symbol

I
I

Type

Chip Select: Chip Select is an ac·
tive low input used to select the
8237A as an I/O device during the
Idle cycle. This allows CPU com·
munication on the data bus.

RESET

I

Reset: Reset is an active high in·
put which clears the Command,
Status, Request and Temporary
registers. It also clears the
first/last fliplflop and sets the
Mask register. Following a Reset
the device is in the Idle cycle.

I

Ready: Ready is an input used to
extend the memory read and write
pulses from the 823?A to accom·
modate slow memories or 1/0 per·
ipheral devices. Ready must not
make transitions during its speci·
fied setuplhold time.

HLDA

I

Hold Acknowledge: The active
high Hold Acknowledge from the
CPU indicates that it has relin·
quished control of the system
busses.

DREQO-DREQ3

I

DMA Request: The DMA Requfilst
lines are individual asynchronous
channel request inputs used by pe·
ripheral circuits to obtain DMA
service. In fixed Priority, DREQO
has the highest priority arid
DREQ3 has the lowest priority. A
request is generated by activating
the DREQ line of a channel. DACK
will acknowledge the recognition
of DREQ signal. Polarity of DREQ
is programmable. Reset intializes
these lines to active high. DREQ
must be maintained until the corre·
sponding DACK goes active.

1/0

Name and Function

ory·to·memory operations, data
from the memory comes Into the
8237A on the data bus during the
read·from·memory transfer. In the
write·to·memory transfer, the data
bus outputs place the data into the
new memory location.

Clock Input: Clock Input controls
the internal operations of the
8237A and its rate of data trans·
fers. The input may be driven at up
to 3 MHz for the standard 8237A
. and up to 5 M Hz for the 8237A·5.

I

DBO-DB?

Type

Symbol

Ground: Ground.
I

CS

READY

I-----------.--~------------------~---

Power: + 5 volt supply.

Vee
Vss
CLK

Name and Function

lOR

1/0

1/0 Read: 1/0 Read is a bidirec·
tional active low three·state line. In
the Idle cycle, it is an Input control
signal used by the CPU to read the
control registers. In the Active cy·
cle, it is an output control signal
used by the 8237 A to access data
from a peripheral during a DMA
Write transfer.

lOW

1/0

1/0 Write: 1/0 Write is a bidirec·
tional active low three·state line. In
the Idle cycle, it is an input control
signal used by the CPU to load in·
formation into the 8237 A. In the Ac·
tive cycle, it is an output control
signal used by the 8237 A to load
data to the peripheral during a
DMA Read transfer.

EOP

1/0

End of Process: End of Process is
an active low bidirectional signal.
Information concerning the 'com·
pletion of DMA services is avail·
able at the bidirectional EOP pin.
The 8237A allows an external sig·
nal to terminate an active DMA
service. This is accomplished by
pulling the EOP input low with an
external EOP signal. The 8237A al·
so generates a pulse when the ter·
minal count (TC) for any channel is
reached. This generates an EOP
'!ia!!al which is output througtL!.!l.e
EOP Line. The reception of EOP,
either internal or external, will
cause the 8237 A to terminate the
service, reset the request, and, if
Autoinitialize is enabled, to write
the base registers to the current
registers of that ,channel. The mask
bit and TC bit in the status word
will be set for the currently active
channel by EOP unless the channel
is programmed for Autoinitialize. In
that case, the mask bit remains unchanged During memory·to·memory
transfers, EOP will be output when
the TC for channel 1 occurs. EOP
should be tied high with a pull·up
resistor if it is not used to prevent
erroneous end of process inputs.

1/0

Address: The four least significant
address lines are bidirectional
three·state signals. In the Idle cy·
cle they are inpu'ts and are used oy
the CPU to address fh-e- registe-r
to be loaded or read. In the Active
cycle they are outputs and provide
the lower 4 bits of the output
address,

I

Data Bus: The Data Bus lines are
bidirectional three·stilte signals
connected to the system data bus.
The outputs are enabled in the Pro·
gram condition during the 1/0 Read
to output the contents of an Ad·
dress register, a Status register,
the Temporary register or a Word
Count register to the CPU. The out·
puts are disabled and the inputs
are read during an 1/0 Write cycle
when the CPU is programming the
8237A control registers. During
DMA cycles the most significant 8
bits of the address are output onto
the data bus to be strobed into an
external latch by ADSTB. In memo

AO-A3

I

2-58

inter

8237 A/8237 A-4/8237 A-5
Table 1. Pin Description (Continued)

Symbol

Type

Name and Function

Symbol

A4·A7

0

Address: The four most significant
address lines are three·state outputs and provide 4 bits of address.
These lines are e~abled only during
the DMA service.

HRQ

0

Hold Request: This is the Hold Re·
quest to the CPU and Is used to reo
quest control of the system bus. If
the corresponding mask bit is
clear, the presence of any valid
DREQ causes B237A to issue the
HRQ. After HRQ goes active at
least one clock cycle (TCY) must
oecur before HLDA goes active.

DACKO·DACK3

0

DMA Acknowledge: DMA Acknowledge is used to notify the individual peripherals when one has
been granted a DMA cycle. The
sense of these lines is programmable. Reset Initializes them to active low.

Type

Name and Function

AEN

0

Address Enable: Address Enable
enables the B-bit latch containing
the upper B address bits onto the
system address bus. AEN can also
be used to disable other system bus
drivers dUring DMA transfers. AEN
is active HIGH.

ADSTB

0

Address Strobe: The active high,
Address Strobe is used to strobe the
upper address byte into an external
latch.

MEMR

0

Memory Read: The Memory Read
signal is an active low three-state
output used to access data from the
selected memory location during a
DMA Read or a memory-to-memory
transfer.

MEMW

0

Memory Write: The Memory Write
IS an active low three-state output
used to write data to the selected
memory location during a DMA
Write or a memory-to-memory
transfer.

FUNCTIONAL DESCRIPTION
The 8237A block diagram includes the major logic
blocks and all of the internal registers. The data i nterconnection paths are also shown. Not shown are the
various control signals between the blocks. The 8237A
contains 344 bits of internal memory in the form of
registers. Figure 3 lists these registers by name and
shows the size of each. A detailed description of the
registers and their functions can be found under
Register Description.
Name

Base Address Registers
Base Word Count Registers
Current Address Registers
Current Word Count Registers
Temporary Address Register
Temporary Word Count Register

Status Register
Command Register

Temporary Register
Mode Registers
Mask Register
Request Register

Size

Number

16bits
16bits
16 bits
16 bits
16 bits
16 bits
B bits
Bbits
Bbits
6 bits
4 bits
4 bits

4
4
4
4

be the 2 TTL clock from an 8224 or ClK from an
8085AH or 8284A. For 8085AH-2 systems above 3.9 MHz,
the 8085 ClK(OUT) does not satisfy 8237A-5 clock lOW
and HIGH time requirements. In this case, an external
clock should be used to drive the 8237 A·5.

DMA Operation
The 8237A is designed to operate in two major cycles.
These are called Idle and Active cycles. Each device cycle is made up of a number of states. The 8237A can
assume seven separate states, each composed of one
full clock period. State I (SI) is the inactive state. It is
entered when tM 8237A has no valid DMA requests
pending. While in SI, the bMA controller is inactive but
may be in the Program Condition, being programmed by
the processor. State SO (SO) is the first state of a DMA
service. The 8237 A has requested a hold but the processor has not yet returned an acknowledge. The 8237 A
may still be programmed until it receives HlDA from the
CPU. An acknowledge from the CPU will signal that
DMA transfers may begin. S1, S2, S3 and S4 are the
working siates of the DMA service. If more time is
needed to complete a transfer than is available with normal timing, wait states (SW) can be inserted between S2
or S3 and S4 by the use of the Ready line on the 8237A.
Note that the data is transferred directly from the I/O
device to memory (or vice versa) with lOR and MEMW (or
MEMR and lOW) being active at the same time. The data
is not read into or driven out of the 8237 A in I/O-tomemory or memory-to-I/O DMA transfers.

1
1
1
1
1
4

1
1

Figure 3. 8237 A Internal Registers
The 8237 A contains three basic blocks of control logic.
The Timing Control block generates inlernal timing and
external control signals for the 8237 A. The Program
Command Control block decodes the various commands given to the 8237 A by the microprocessor prior
to servicing a DMA Request. It also decodes the Mode
Control word used t9 select the type of DMA during the
servicing. The Priority Encoder block resolves priority
contention between DMA channels requesting service
simultaneously.

Memory-to-memory transfers require a read-from and a
write-to-memory to complete each transfer. The states,
which resemble the normal working states, use two
digit numbers for identification. Eight states are required for a single transfer. The first four states (S11,
S12, S13, S14) are used for the read-from-memory half

The Timing Control block derives internal timing from
the clock input. In 8237A systems this input will usually

2-59

8237A/8237~4/8237A-5

becomes active. Again, an Autoinitialization will occur
at the end of the service if the channel has been pro·
grammed for it.

and the last four states (S21, S22, S23, S24) for the write·
to·memory half of the transfer.
IDLE CYCLE
When no channel is requesting service, the 8237A will
enter the Idle cycle and perform "SI" states. In this
cycle the 8237A will sample the DREQ lines every clock
cycle to determine if any channel Is requesting a DMA
service. The device will also sample CS, looking for an
attempt by the microprocessor to write or read the Inter·
nal registers of the 8237A. When CS Is low and HLDA is
low, the 8237A enters the Program Condition. The CPU
can now establish, change or inspect the internal deflnl·
tion of the part by reading from or writing to the internal
registers. Address lines AO-A3 are inputs to the device
and select which registers will be read or written. The
lOR and lOW lines are used to select and time reads or
writes. Due to the number and size of the internal regis·
ters, an Internal fllp·flop Is used to generate an addl·
tlonal bit of address. This bit is used to determine the
upper or lower byte of the 16·blt Address and Word
Count registers. The fllp·flop Is reset by Master Clear or
Reset. A separate software command can also reset this
fllp·flop.
'
Special software commands can be executed by the
8237A In the Program Condition. These commands are
decoded as sets of addresses with the CS and lOW. The
commands do not make use of the data bus. Instruc·
tions include Clear First/Last Flip·FLop and Master
Clear.

Demand Transfer Mode - In Demand Transfer mode the
device is programmed to continue making transfers
until a TC or external EOP is encountered or until DREQ
goes inactive. Thus transfers may continue until the I/O
device has exhausted Its data capacity. After the I/O
device has had a chance to catch up, the DMA service Is
re·establlshed by means of a DREQ. During the time
between services when the microprocessor is allowed
to operate, the intermediate values of address and word
count are stored in the 8237A Current Address and Cur·
rent Word Count registers. Only an EOP can cause an
Autoinitialize at the end of the service. EOP is generated
either by TC or by an external signal.
Cascade Mode-This mode is used to cascade morethan one
8237 A together for simple system expansion. The HRQ and
HLDA signals from the additional 8237 A are connected to the
DREQ and DACK signals of a channel of the initial 8237A.
This allows the DMA requests of the additional device to
propagate through the priority network circuitry of the preceding device. The priority chain is preserved and the new device
must wait for its turn to acknowledge requests. Since the
cascade channel of the initial 8237 A is used only for prioritizing the additional 'device, it does not output any address
or control signals of its own. These could conflict with the,
outputs of the active channel in the added device. The 8237A
will respond to DREQ and DACK but all other outputs except
HRQ will be disabled. The ready input is ignored.

ACTIVE CYCLE
When the 8237A is in the Idle cycle and a non·masked
channel requests a Dt.1A service, the device will output
an HRQ to the microprocessor and enter the Active cy·
cle. It is in this cycle that the DMA service will take
\.
place, In one of four modes:

Figure 4 shows two additional devices cascaded Into an
Initial device using two of the previous channels. This
forms a two level DMA system. More 8237As could be
added at the second level by USing the remaining channels of the first level. Additional devices can also be
added by cascading Into the channels of the second
level devices, forming a third level.

Single Transfer Mode - In Single Transfer mode the
device Is programmed to make one transfer only. The
word count will be decremented and the address dec·
remented or incremented following each transfer. When
the word count "rolls over", from zero to FFFFH, a Ter·
minal Count (TC) will cause an Autoinitialize if the chan·
nel has been programmed to do so.

2ND LEVEL

8237A

1ST LEVEL

MICRO~ROCESSOR

DREQ must be held active until DACK becomes active in
order to be recognized. If DREQ Is held active through·
out the single transfer, HRQ will go inactive and release
the bus to the system. It will again go active and, upon
receipt of a new HLDA, another single transfer will be
performed, in 8080A, 8085AH, 8088, or 8086 system this
will ensure one full machine cycle execution between
DMA transfers. Details of timillg between the 8237A and
other bus control protocols will depend upon the char·
acteristics of the microprocessor involved.

I--

r---

HRQ

DREQ

1-

HR,Q

HlDA

DACK

t--

HLDA

DREQ

r-

HRQ

DACK

t-"

HLOA

8237A

INITIAL DEVICE

Block Transfer Mode - In Block Transfer mode the
device Is activated by DREQ to continue making trans·
fers during the service until a TC, caused by wor~unt
going to FFFFH, or an external End of Process (EOP) is
encountered. DREQ need only be hE!ld ~ctive until DACK

8237A

ADDITIONAL
DEVICES

Figura' 4. Cascaded 8237As
2-60

inter

8237 A/8237A-4/8237 A-5

TRANSFER TYPES

which fixes the channels in priority order based upon the
descending value oftheir number, The channel with the lowest
priority is 3 followed by 2, 1 and the highest priority channel,
O. After the recognition of anyone channel for service, the
other channels are prevented from interferring with that service until it is completed.

Each of the three active transfer modes can perform three
different types of transfers. These are Read, Write and Verify.
Write transfers move data from and 1/0 device to the memory
by activating MEMW and lOR. Read transfers move data from
memory to an 1/0 device by activating MEMR and lOW. Verify
transfers are pseudo transfers. The 8237 A operates as in
Read or Write transfers generating addresses, and ~esponding
to EOP, etc. However, the memory and 1/0 control lines all
remain inactive. The ready input is ignored in verify mode.

The second scheme is Rotating Priority. The last channel to get service becomes the lowest priority channel
with the others rotating accordingly.

Memory-to-Memory-To perform block moves of data from
one memory address space to another with a minimum of
program effort and time, the 8237 A inc;.Iudes a memory-tomemory transfer feature. Programming a bit in the Command
register selects channels 0 to 1 to operate as memory-tomemory transfer channels. The transfer is initiated by setting
the software DREQ for channel O. The 8237 A requests a DMA
service in the normal manner. After HLDA is true, the device,
using four state transfers in Block Transfer mode, reads data
from the memory. The channel 0 Current Address register is
the source for the address used and is decremented or incremented in the normal manner. The data byte read from the
memory is stored in the 8237 A internal Temporary register.
Channel 1 then performs a four-state transfer of the data from
the Temporary register to memory using the address in its
Current Address register and incrementing or decrementing it
in the normal manner. The channel 1 current Word Count is
decremented. When the word count of channel 1 goes to
FFFFH, a TC is generated causing an EOP output terminating
the service.

1st
Service
highest

lowest

2nd
Service

2. . --

o
service
1 ~ service ' \ 3 - . - request

3rd
Service

\3......-

service

0

2

,0

1

3

1

2

With Rotating Priority in a single chip DMA system, any
device requesting service is guaranteed to be recognized after no more than three higher priority services
have occurred. This prevents anyone channel from
monopolizing the system.

Channel 0 may be programmed to retain the same address for all transfers. This allows a Single wl/lrd to be
written to a block of memory.
The 8237A will: respond to external EOP sign~ls during
memory-to-memory transfers. Data comparators in
block search schemes may use this input to terminate
the service when a match is found. The timing of.
memory-to-memory transfers is found in Figure 12.
Memory-to-memory operations can be detected as an
active AEN with no DACK outputs.
Autoinitialize-By programming a bit in the Mode register, a
channel may be set up as an Autoinitialize channel. During
Autoinitialize initialization, the original values of the Current
Address and Current Word Count registers are automatically
restored from the Base Address and Base Word count registers
of that channel following EOP. The base registers are loaded
simultaneously with the current registers by the microprocessor and remain unchanged throughout the DMA service.
The mask bit is not altered when the channel is in Autoinitialize.
Following Autoinitialize the channel is ready to perform
another DMA service, without CPU intervention, as soon as a
valid DREQ is detected. In order to Autoninitialize both channels in a memory-to-memory transfer, both word counts should
be programmed identically. If interrupted externally, EOP
pulses should be applied in'both bus cycles.

Compressed Timing - In order to achieve even greater
throughput where system characteristics permit, the
8237 A can compress the transfer time to two clOCk
cycles. From Figure 11 it can be seen that state S3 is
used to extend the access time of the read pulse. By
removing state S3, the read pulse width is made equal to
the write pulse width and a transfer consists only of
state 52 to change the address and state S4 to perform
the read/write. S1 states will still occur when A8-A 15
need updating (see Address Generation). Timing for
compressed transfers is found in Figure 14.
Address Generation - In order to reduce pin count, the
8237A multiplexes the eight higher order address bits
on the data lines. State S1 is used to output the higher
order address bits to an external latch from which they
may be placed on the address bus. The falling edge of
Address Strobe (ADSTB) is used to load these bits from
the data lines to the latch. Address Enable (AEN) is used
to enable the bits onto the address bus through a threestate enable. The lower order address bits are output by
the 8237A directly. Lines AO-A7 should be connected to
the address bus. Figure 11 shows the time relationships
between ClK, AEN, ADSTB, DBO-DB7 and AO-A7.
During Block and Demand Transfer mode services,
which include multiple transfers, the addresses generated will be sequential. For many transfers the data held
in the external address latch will remain the same. This
data need only change when a carry or borrow from A7
to A8 takes place in the normal sequence of addresses.
To save time and speed transfers, the 8237A executes
S1 states only when updating of A8-A15 in the latch is
necessary. This means for long services, S1 states and
Address Strobes may occur only once every 256 transfers, a savings of 255 clock cycles for each 256
transfers.

Priority-The 8237 A has two types of priority encoding available as software selectable options, The first is Fixed Priority

2-61

8237A/8237~4/8237~5

REGISTER DESCRIPTION

Command Register
7

3

2

1

0 ""f--Bit Number

1

Memory-te-memory disable
Memory-te-memory enable

o

Y

Channel 0 address hold disable
1 Cllannel 0 address hold enable
X II bit 0=0

I

o

\ 1

Controllet enable
Controller disable

Normal timing
I o, 'Compressed
timing
I X IlbltO='

.

,

f o
I ,

Fixed priority
Rotating priority

I o1
IX

Late write selection
Extended write selection
II bit 3=1

o

DREQ sense active high
DREQ sense active low

o

DACK sense active low
DACK sense active high

f
\ ,
f

I ,

Mode Register

Base Address and Base Word Count Registers - Each
channel has a pair of Base Address and Base Word
Count registers. These 16-bit registers store the original
value of their associated current registers. During Autoinitialize these values are used to restore the current
registers to their original values. The base registers are
written simultaneously with their corresponding current
register in 8-bit bytes in the Program Condition by the
microprocessor. These registers cannot be read by the
microprocessor.
Command Register - This 8-bit register controls the
operation of the 8237A. It is programmed by the microprocessor in the Program Condition and is cleared by
Reset or a Master Clear Instruction. The following table
lists the function of the command bits. See Figure 6 for
address coding.

5~ 4

Yo

Current Address Register - Each channel has a 16·bit
Current Address register. This register holds the value
of the address used during DMA transfers. The address
is automatically incremented or decremented after each
transfer and the intermediate values of the address are
stored in the Current Address register during the transfer. This register is written or read by the microprocessor in successive 8-bit bytes. It may aiso be reinitiallzed by an Autoinitialize back to its original value.
Autoinitialize takes place only after an EOP.
Current Word Register - Each channel has a 16-bit Current Word Count register. This register determines the
number of transfers to be performed. The actual number
of transfers will be one more than the number programmed in the Current Word Count register (i.e., programming a count of 100 will result in 101 transfers). The
word count is decremented after each transfer. The
intermediate value of the word count I~ stored in the register during the transfer. When the value In the register
goes from zero to FFFFH, a TC will be generated. This
register is loaded or read In successive 8-blt bytes by
the microprocessor in the Program Condition. Following the end of a DMA service it may also be reinltialized
by an Autoinitialization back to its original value. AutoInitialize can occur only when an EOP occurs. If 'it Is not
Autoinitialized, this register will have a count of FFFFH
after TC.

•

I I I I I I II I

00
01
' - - - - - { '0
11
XX

'--_ _ _ _-1 0

'--------1

Verily transler
Write transfer
Read transler
Illegal
If bits 6 and 7= 11

1

AutOinitialization disable
AutOinitialization enable

0
1

Address increment select
Address decrement select

00
'--_ _ _ _ _ _ _-{ 01
10
11

Demand mode select
Single mode select
Block mode select
CaScade mode select

Request Register

Mode Register - Each channel has a 6-bit Mode register associated with it. When the register is being written
to by the microprocessor in the Program Condition, bits
oand 1 determine which channel Mode register Is to be
written.

'--__-I

Request Register - The 8237 A can respond to requests
for DMA service which are initiated by software as well
as by a DREQ. Each channel has a request bit associated with it in the 4-bit Request register. These are nonmaskable and subject to prioritization by the Priority
Encoder network. Each register bit is set or reset sepa-

0
,

Reset request bit
Set request bit

rately under software control or is cleared upon generation of a TC or external EOP. The entire register is
cleared by a Reset. To set or reset a bit, the software
loads the proper form of the data word. See Figure 5 for
register address coding. In order to make a software request, the channel must be in Block Mode.

2-62

8237 A/8237 A-4/8237A-5

o ~ Bit Number

Mask Register - Each channel has associated with it a
mask bit which can be set to disable the incoming
DREQ. Each mask bit is set when its associated channel
produces an EOP if the channel is not programmed for
Autoinitialize. Each bit of the 4-bit Mask register may
also be set or cleared separately under software control.
The entire register is also set by a Reset. This disables
all DMA requests until a clear Mask register instruction
allows them to occur. The instruction to separately set
or clear the mask bits is similar in form to that used with
the Request register. See Figure 5 for instruction addressing.

Select
Select
Select
Select

Don't Care

~_ _--!

0

,,~--,-,--,-,--,-,

Channel 0 has reached TC
Channell has re,ached TC
Channel 2 has reached TC

Channel 3 has reached TC
Channel 0 request
Channell request
Channel 2 request
Channel 3 request

Temporary Register - The Temporary register is used
to hold data during memory-to-memory transfers. Following the completion of the transfers, the last word
moved can be read by the microprocessor in the Program Condition. The Temporary register always contains the last byte transferred in the previous memoryto-memory operation, unless cleared by a Reset.

channel 0 mask bit
channell mask bit
channel 2 mask bit
channel 3 mask bit

Software Commands-These are additional special software
commands which can be executed in the Program Condition.
They do not depend on any specific bit pattern on the data
bus. The three software commands are:

Clear mask bit
Set mask bit

Clear First/Last Flip-Flop: This command is executed
prior to writing or reading new address or word count
information to the 8237A. This initializes the flip-flop
to a known state so that subsequent accesses to register contents by the microprocessor will address
upper and lower bytes in the correct sequence.

All four bits of the Mask register may also be written
with a single command.
7

6

5

4

3

2

O~BIINumber

1

0

Clear channel 0 mask bit
Set channel 0 mask bit

0

Clear channell mask bit
Set channell mask bit

0

Clear channel 2 mask bit
Set channel 2 mask bit

0

Clear, channel 3 mask bit

Master Clear: This software instruction has the same
effect as the hardware Reset. The Command, Status,
Request, Temporary, and Internal First/Last Flip-Flop
registers are cleared and the Mask register is set. The
8237A will enter the Idle cycle.
Clear Mask Register: This command clears the mask
bits of all four channels, enabling them to accept
DMA requests.

Set channel 3 mask bit

Register

Operation

Command
Mode
Request
Mask
Mask
Temporary
Status

Write
Write
Write
SetiReset
Write
Read
Read

Figure 6 lists the address codes for the software commands:

Signals

CS

lOR

lOW

A3

A2

Al

AO

0

1
1
1
1
1
0
0

0
0

1
1
1
1
1
1
1

0
0
0
0
1
1
0

0
1
0
1

0
1
1
0
1
1
0

0
0
0
0
0
0

0
0
0
1
1

"

0
0

Signals

Figure 5. Definition of Register Codes

A3

A2

A1

AO

lOR

lOW

1

0

0

0

0

1

1

0

0

0

1

0

Write Command RegIster

1

0

0

1

0

1

Illegal

1

0

0

1

1

0

Wnte Request Register

1

0

1

0

0

1

Illegal

1

0

1

1

0

Write SIngle Mask RegIster elt

0

,

0

1

,

Status Register - The Status register is available to be
read out of the 8237A by the microprocessor. It contains
information about the status of the devices at this point.
This information includes which channels have reached
a terminal count and which channels have pending DMA
requests. Bits 0-3 are set every time a TC is reached by
that channel or an external EOP is applied. These bits
are cleared upon Reset and on each Status Read. Bits
4-7 are set whenever their corresponding channel is
requesting service.

,
,

,

0

,

,

,

,
,

1

0

Write Mode Register

0

0

0

1

Illegal

1

0

0

1

0

1

0

0

,

0

0

0

,

,
, ,
, ,
,
,
, , ,
,
, -, , ,
,
,
0

1

1

0

0

0

0

1

Operation
Read Status RegIster

1

1

0

Illegal

Clear Byte Pomter Fhp/Flop
Read Temporary RegIster
Master Clear
Illegal

Clear Mask Register
Illegal
Wnte All Mask Register Bds

Figure 6. Software Command Codes
2-63

8237 A/8237 A-4/8237 A-5

Signals
Channel

0

Regisler
. Base and Current Address
Current Address
Base and Current Word Count
Current Word Count

1

Base and Current Address
Current Address

Base and,Current Word Count
Current Word Count

2

Base and Current Address

Current Address

Base and Current Word Count
Current Word Count

3

Base and Current Address
Current Address
Base and Current Word Count
Current Word Count

Operalion
Write
Read
Write
Read
Write

Read
Write

Read
Write

Read
Write

Read
Write
Read
Write
Read

Inlernal Fllp·Flop

Oala Bus OBO-OB7

0
0

0

AO-A?
A8-A15

0
0

0'
0

0

0
0

0
0

1
1

0

0
0

0
0

0
0

1
1

0

0
0

0
0

0
0

1
1

0
0

0

0
0

1
1

0
0

0
0

1
1

0
0

0

,0
0

1
1

0
0

0
0

0
0

1
1

1
1

0

0
0

0
0

1
1

0
0

0
0

1
1

1
1

0

0
0

1
1

0
0

0
0

1
1

0
0

0
0

0

0
0

0
0

1
1

0
0

1
1

0
0

0
0

0

0
0

1
1

0
0

0
0

1
1

0
0

1
1

0

0
0

0
0

1
1

0
0

1
1

0
0

1
1

0

0
0

1
1

0
0

0
0

1
1

1
1

0
0

0

0
0

0
0

1
1

0
0

1
1

1
1

0
0

0

0
0

1
1

6

0

0
0

1
1

1
1

1
1

0

0
0

0
0

1
1

0
0

1
1

1
1

1
1

0

CS

~OR

lOW

A3

A2

AI

AO

0
0

I
I

0
0

0
0

0
0

0
0

0
0

0
0

I
I

0
0

0
0

0
0

1
1

0
0

0
0

0
0

0
0

1
1

0
0

1
1

0
0

I
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1

Figure 7. Word Count and Address Register Command Codes
PROGRAMMING

The 8237A will accept programming from the host proc·
essor any time that HLDA is inactive; this is true even if
HRQ is active. The responsibility of the host is to assure
that programming and HLDA are mutually exclusive.
Note that a problem can occur if a DMA request occurs,
on an unmasked channel while the 8237A is being pro·
grammed. For instance, the CPU may be starting to
reprogram the two byte Address register of channel 1
when channel 1 receives a DMA request. If the 8237A is
enabled (bit 2 in the command register is 0) and channel
1 is unmasked, a DMA service will occur after only one
byte of the Address register has been reprogrammed.
This can be avoided by disabling the controller (setting
bit 2 in the command register) or masking the channel
before programming any other registers. Once the pro·
gramming is complete, the controller can be enabled/un·
•
masked.
After power·up it is suggested that all internal locations,
especially the Mode registers, be loaded with some
valid value. This should bd done even if some channels
are unused.

2-64

AO-A?
A8-A15
WP-W?
W8-W15
W)O-W?
W8-W15
AO-A?
AS-A15
AO-A?
A8-A15
WO-W?
W8-W15
WO·W?
W8-W15
AO-A?
A8-A15
AO-A7
A8-A15
WO-W?
W8-W15
W)O-W?
W8-W15
AD-A?
A8-A15
AO-A?
A8-A15
WD-W?
W8-W15
W)O-W?
W8-W15

inter

8237 A/8237 A-4/8237 A-5

APPLICATION INFORMATION

operation comes out in two bytes - the least significant 8 bits on the eight address outputs and the most
significant 8 bits on the data bus. The contents of the
data bus are then latched into the 8~82 8-bit latch to
complete the full 16 bits of the address bus. The 828.2 is
a high speed, 8-bit, three-state latch in a 20-pin package.
After the initial transfer takes place, the latch is updated
only after a carry or borrow is generated in the least significant address byte. Four DMA channels are provided
when one 8237A is used.

Figure 8 shows a convenient method for configuring a
DMA system with the 8237A controller and an 8080AI
8085AH microprocessor system. The multi mode DMA
controller issues a HRQ to the processor whenever
there is at least one valid DMA request from a peripheral
device. When the processor replies with a HLDA signal,
the 8237A takes control of the address bus, the data bus
and the control bus. The address for the first transfer

,)

ADDRESS BUS AO-A1S

....,

~

~

AS-A15

Joo,.
I'"

r-----

J

AO-A3

A4-A7

8282
STB

1

~

AEN

AO-A15

OE

8·BIT LATCH

ADSTB

CS

~

BUSEN
HLDA

8237A

HLDA
I-

HOLD

HRO

:5
()

CPU
CLOCK
RESET

J

w
w
a:

U)

I

l~ I~

@ I~

..,

..,

8w

~

a:
Q

DBODB7

A

.~

~

r

r

()

'"
Q

ft'

MEMR

l~'""

MEMW

BUS

lOR
lOW

DBO-DB7
~

.

i'"

;,..

7
SYSTEM DATA BUS

Figure 8. 8237A System Interface

2-65

,)

8237 A/8237 A-4/8237 A-5

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature under Bias ..•...... O·C to 70·C
Storage Temperature .....•....... - 65·C to + 150·C
Voltage on any Pin with
Respect to Ground ..............
0.5 to 7V
Power Dissipation •.........•.............. 1.5 Watt
c

••••••

_

D.C. CHARACTERISTICS (TA = O°C to 70°C, Vcc =
Symbol

Parameter

Min.

'NOTICE: Stresses above tholie listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

5.0V ±5%, GND = OV)

Typ,(1)

Max.

2.4

Test Conditions

Unit

VOH

Output High Voltage

V

VOL

Output LOW Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

'l

Input Load Current

±10

!LA

ILO

Output Leakage Current

±10

!LA

0.45V os VOUT os Vcc

Icc

VccSupply Current

110

130

mA

TA = +25°C

130

150

mA

TA=O°C

Co

Output Capacitance

4

8

pF

IOH = -200 !LA

V

IOH = -100 !LA (HRQ Only)

.45

V

IOL = 2.0mA (data Bus, EOP)
IOL = 3.2mA (other outputs) (Note 8)
IOL = 2.5mA (ADSTB) (Note 8)

2.2

Vcc+ 0.5

V

-0.5

0.8

3.3

V.

C1

Input Capacitance

8

15

pF

ClO

110 Capacitance

10

18

pF

OV os VIN os Vcc

Ic = 1.0 MHz, Inputs = OV

NOTES:
1. TYPIcal values are for TA =: 25°C, nominal supply voltage and nominal procesSing parameters
2 Input timing parameters assume transition times of 20 ns or less Waveform measurement points for both input and output signals are 2 OV for HIGH and 0 8V

for LOW, unless otherwise noted

Output loading IS 1 TTL gate plus 150pF capacitance, unless otherwise noted
The nel lOW or MEMW Pulse width for normal write will be TCY-1 00 ns and for extended write will be 2TCY-1 00 ns The net lOR or MEMR pulse width for
normal read will be 2TCY-50 ns and for compressed read will be TCY-50 ns
5. TDQ IS specified for two different output HIGH levels TDQ1 IS measured at 2 OV TDQ2 is measured at 3 3V The value for TDQ2 assumes an external 33kll
pull-up resistor connected form HRQ to Vec
6. DREQ should be held active until DACK is returned
7 DREQ and DAC~ signals may be active high or active low TII1;1tng diagrams assume the active hi~h mode

8. A revision of Ihe 8237 A is planned for shipment In April 1985. which will Improve the following characlerlstlcs
1. VIH from 2.2V to 2.0V
2 VOL from 0 45V to O.4V on all outputs Test condilion IOL = 3 2 mA
Please contact your local sales office at that time for more Information.
g. Successive read and/orwrite operations by the external processor to program or examme the controller must be timed to allow at least 600 ns for the 8237 A,
at least 500 ns for the 8237 A-4 and at least 400 ns for the 8237 A-5, as recovery time between active read or write pulses
10. EOP IS an open collector output ThiS parameter assumes the presence of a 2 2K pullup to Vee
11 Pin 5 is an input that should always be at a logic high level An Internal pull-up resistor Will establish a logic high when the pin is left floallng It is recom-

mended however. that pin 5 be lied to VCC
12 Output Loading on the Data Bus

IS ITTL

Gate plus 100 pF capacitance

A.C. TESTING INPUT, OUTPUT WAVEFORM

:=X2.0>

INPUT/OUTPUT

2.4

0••

0.45

-

TEST POINTS

<2oX==
0••

-

AC TESTING INPUTS ARE ORIVENAT24V FOR A LOGIC '1"AND045VFOR
A LOGIC"O" TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC "1"
AND 0 BV FOR A LOGIC "0 .. (Note 2)

2-66

inter

8237 A/8237 A-4/8237 A-5

A.C. CHARACTERISTICS-DMA (MASTER) MODE (TA=O'C to 70'C,
Vee= +5V±5%, GND=OV)
8237A

8237A·4

8237A-5
Max.

Unit

TAEl

AEN HIGH from ClK lOW (S1) DelayTlme

300

225

200

ns

TAET

AEN lOW from ClK HIGH (SI) DelayTlme

200

150

130

ns

TAFAB

ADR Active to Float Delay from ClK HIGH

150

120

90

ns

TAFC

READ or WRITE Float from ClK HIGH

150

120

120

ns

TAFDB

DB Active to Float Delay from ClK HIGH

250.

190

170

ns

TAHR

ADR from READ HIGH Hold Time

TAHS

DB from ADSTB lOW Hold Time

TAHW

ADR from WRITE HIGH Hold Time

Symbol

TAK

Parameter

Min.

:

Max.

Min.

Max.

Min.

TCY-100

TCY-100

40

40

30

TCY-50

TCY-50

TCY-50

.TCY-100

ns
ns
ns

DACK Valid from ClK lOW Delay Time (Note 7)

250

220

170

ns

EOP HIGH from ClK HIGH Delay Time (Note 10)

250

190

170

ns

250

190

170

ns

250

190

170

ns

EOP LOW from CLK HIGH Delay Time

iI

TASM

ADR Stable from ClK HIGH

TA&S

DB to ADSTB lOW Setu p TI me

100

100

100

ns

TCH

Clock High Time (Transitions,;; 10 ns)

120

100

80

ns

TCl

Clock lOW Time (Transitions,;; 10 ns)

150

110

68

ns

TCY

ClK Cycle Time

320

250

200

TDCl

ClK HIGH to READ orWRITE LOW Delay (Note 4)

TDCTR
TDCTW
TD01

I

. READ HIGH from ClK HIGH (S4) Delay Time
(Note 4)
WRITE HIGH from ClK HIGH (S4) DelayTlme
(Note 4)
HROValld from.ClK HIGH Delay Time (Note 5)

TDQ2

ns

270

200

190

ns

270

210

190

ns

200

150

130

ns

160

120

120

ns

250

190

120

ns

60

45

40

300

225

220

ns

TEPS

EOP LOW from ClK lOW Setup Time

TEPW

EOP Pulse Width

TFAAB

ADR Float to Active Delay from ClK HIGH

250

190

170

ns

TFAC

READ or WRITE Active from CLK HIGH

200

150

150

ns

TFADB

DB Float to Active Delay from ClK HIGH

300

225

200

THS

HlDA Valid to ClK HIGH Setup Time

TIDH

Input Data from MEMR HIGH Hold Time

TIDS

Input Data to MEMR HIGH Setup Time

TODH

Output Data from MEMW HIGH Hold Time

TODV

Output Data Valid to MEMW HIGH

TOS

DR EO to ClK lOW (SI, S4) Setup Time (Note 7)

I--~-

100

75

ns

ns

75

ns

0

0

0

ns

250

190

170

ns

20

20

10

ns

200

125

125

ns

0

0

0

ns
ns

TRH

ClK to READY LOW Hold Time

20

20

20

TRS

READY to ClK lOW Setup Time

100

60

60

TSTl

ADSTB HIGH from ClK HIGH DelayTlme

TSTT

ADSTB lOW from ClK HIGH D\,layT!m~

I

2-67

ns

200

150

130

ns

140

110

90

ns

8237A/8237A-4/8237 A·5

A.C. CHARACTERISTICS-PERIPHERAL (SLAVE) MODE

= O°Cto 70°C, VCC = 5.0V ±5%,

(TA

GND = OV)
Symbol

8237A

Parameter

Min.

8237A·4

Max.

Min.

8237A·5

Max.

Min.

'lJnit

Max.

TAR

ADR Valid or CS LOW to READ LOW

50

50

50

ns

TAW

ADRValid to WRITE HIGH Setup Time

200

150

130

ns

TCW

CS LOW to WRITE HIGH Setup Time

200

150

130

ns

TDW

Data Valid to WRITE HIGH Setup Time

200

150

130

ns

TRA

ADR or CS Hold from READ HIGH

0

0

0

TRDE

Data Access from READ LOW (Note 3)

TRDF

DB Float Delay from READ HIGH

TRSTD

Power Supply HIGH to RESET LOW Setup Time

TRSTS

RESET to First IOWR

TRSTW

200
20

ns

200

100

20

100

140

ns

70

ns

0

500

500

500

2TCY

2TCY

2TCY

ns

RESET Pulse Width

300

300

300

ns

TRW

READ Width

300

250

200

ns

TWA

ADR from WRITE HIGH Hold Time

20

20

20

ns

CS HIGH from WRITE HIGH Hold Time

20

20

20

ns

TWD

Data from WRITE HIGH Hold Time

30

30

30

ns

TWWS

Write Width

200

200

160

,~s

TWC

I

ns

WAVEFORMS
SLAVE MODE WRITE TIMING
TCW

I

TWWS

TAW
~

AO-A3

DBO-DB7

---1

~

INPUT VALID

,

TOW

-

j

-

j-TWC
(NOTE B)

I
-TWA

J-TWD

~

INPUT VALID

Figure 9. Slave Mode Write

SLAVE MODE READ TIMING

cs~
AO-A3~

lOR

..:;,V

HM1
h

r(

ADDRESS MUST BE VALID

,
l

TRDE

DBO-DB7

Figure 10. Slave Mode Read

2-68

=E'
:

TRW

t

~OTE9)

TRDF3-

DATA OUT VALID

_

inter

8237 A/8237A-4/8237 A-5

WAVEFORMS (Continued)
DMA TRANSFER TIMING

.,
eLK

DREG

~

TOO_

\\ X l\\

F

\ \ \'

l.LiJ

-

S .\\\\\\\\\

TAEL~I)

TAET

1V'f

TIll

.2!!T

-

IF- 1\

ADSTB

"
TFADa

r f~f--~T'
f::

rFAA.

r-

I

~

••

HF¥ t·

-

r--

TFAC

l-

I TDCL

TDCTA

r-

~

--"

TOCT.

~ v~ ~
TDCTW

TDCTW

~(fDA

-

I-

-TAHA

1\

I

...

_TAFAI
t-TAHW

ADDRESS VALID

:..- I- -TAHA

Ir------.

~ENDED

WAITE)

HPW

\

TAHW

}

I

\

--

TASM

ADDRESS VALID

~
OAeK

~

--TEPS

rr

I

I

i

f-

I

I

INTIIIP

.,

(NOTE 6)

TOG_

.EN

D80-DI7

51

\....J

THS_

HLOA

.,

~~~~~H:~~rl~~ ~~~~~
-;r-

-jTQS rf1/I

HAC

.

\\\\\\\\\\'\.

1- _TAFe
Ir- ....

..Jr"'""'""\
~

t1VIIIIIIIIIII
~}-~

Figure 11. DMA Transfer

2-69

-

'

TAK

TeH

inter

8237A/8237A·4/8237~5

WAVEFORMS (Continued)
!

MEMORY-TO-MEMORY TRANSFER TIMING

AOSTB

AO-A7

OBO-OB7

EXT

EOP

-....,....,~""T'""\

Figure 12. Memory·to·Memory Transfer

READY TIMING

elK

TDCTW-

READY

Figure 13. Ready

2-70

8237AJ8237~4/8237~5
WAVEFORM~ (Continued)

COMPRESSED TRANSFER TIMING

ClK

AO-A7

TDCl-j--+1

READY

~~:

___________TA_K_-_--"'--_~

EXT --------..,....,,~
\TE\~oC--.L~t

tv

EDP

Figure 14. Compressed Transfer

RESET TIMING

~c ______J~r~i~~~~~~~~~~~~~~-T-R-ST-D-------------------_-_-_-_-_-_-_-_~-----~I~I-------------

I
lOR OR RlW

Figure 15. R...t

2-71

8257/8257·5,
PROGRAMMABLE DMA CONTROLLER
• MCS-85@ Compatible 8257-5

• Single TTL Clock

• 4·Channel DMA Controller

• Single + 5V Supply

• Priority DMA Request Logic

• Auto Load Mode

• Channel Inhibit Logic
• Available in EXPRESS
- Standard Temperature Range

• Terminal Count and Modulo 128
Outputs

The Intel' 8257 is a 4-channel direct memory access (DMA) controller_ It is specifically designed to simplify the
transfer of data at high speeds for the Intel"' microcomputer systems. Its primary function is to generate, upon a
peripheral request, a sequential memory address which will allow the peripheral to read or write data directly to or
from memory. Acquisition of the system bus i.n accomplished via the CPU's hold function. The 8257 has priority logic
that resolves the peripherals requests and issues a composite hold request to the CPU. It maintains the DMA cycle
count for each channel and outputs a control signal ·to notify the peripheral that the programmed number of DMA
cycles is complete. Other output control signals simplify sectored data transfers. The 8257 represents a significant
savings in component count for DMA-based microcomputer systems and greatly simplifies the transfer of data at
high speed between peripherals and memories.

\.
DRQO

=n

ORO 1

0Aci("i

ORO 2

.,
.,
.,

...

Dm"l

cs-------'

0,

.,

0,

"

DACI( 3

'EN
AOST8

TC
MARK

:==:::'.J
Figure 2. Pin Configuration

Figure 1. Block. Diagram

2-72

inter

8257/8257 ·5

FUNCTIONAL DESCRIPTION

Block Diagram Description
1. DMA Channels

General

The 8257 provides four separate DMA channels (labeled
CH-O to CH-3). Each channel includes two sixteen-bit
registers' (1) a DMA address register, and (2) a terminal count register. Both registers must be initialized
before a channel IS enabled. The DMA address register is
loaded with the address of the first memory location to be
accessed. The value loaded Into the low-order 14-blts of
the terminal count register specifies the number of DMA
cycles minus one before the Terminal Count (TC) output
IS activated. For Instance, a terminal count of 0 would
cause the TC output to be active in the first DMA cycle for
that channel. In general, If N = the number of desired DMA
cycles, load the value N-1 into the low-order 14-blts of the
terminal count register. The most significant two bits of the
terminal count register specify the type of DMA operation
for that channel

The 8257 IS a programmable, Direct Memory Acess (DMA)
device which, when coupled with a single 8-bit latch
provides a complete four-channel DMA controller for use in
Intel@ microcomputer systems. After being initialized by
software, the 8257 can transfer a block of data, containing up
to 16,384 bytes, between 'memory and a peripheral device
directly, without further intervention reqUired of the CPU.
Upon receiving a DMA transfer request from an enabled
peripheral, the 8257:
1. Acquires control of the system bus.
2. Acknowledges that requesting peripheral which IS
connected to the highest Priority channel
3. Outputs the least significant eight bits of the memory
address onto system address lines ArrA7, outputs the
most significant eight bits of the memory address to the
8-bit latch via the data bus (the outputs of the latch
should drive address lines AIf"A'5), and
4. Generates the appropriate memory and 1/0 readl
write control signals that cause the peripheral to
receive or deposit a data byte directly from or to the
addressed location in memory.
The 8257 will retain control of the system bus and repeat
the transfer sequence, as long as a peripheral maintains ItS
DMA request Thus, the 8257 can transfer a block of data
tolfrom a high speed peripheral (e g , a sector of data on a
floppy disk) In a single "burst". When the specified
number of data bytes have been transferred, the 8257
activates ItS Terminal Count (TC) output, informing the
CPU that the operation IS complete
The 8257 offers three different modes of operation'
(1) DMA read, which causes data to be transferred from
memory to a peripheral, (2) DMA write, which causes
data to be transferred from a peripheral to memory,
and (3) DMA verify, which does not actually Involve the
transfer of data. When an 8257 channel IS In the DMA verify
mode, It will respond the same as described for transfer
operations, except that no memory or 1/0 read/wnte
control signals will be generated, thus preventing the
transfer of data The 8257, however, will gain control of the
sYlltem bus and will acknowledge the peripheral's DMA
request for each DMA cycle The peripheral can use these
acknowledge signals to enable an Internal access of each
byte of a data block In order to execute some verification
procedure, such as the accumulation of a CRC (Cyclic
Redundancy Code) checkword For example, a block of
DMA verify cycles might follow a block of DMA read cycles
(memory to peripheral) to allow the peripheral to verify ItS
newly acqUired data

Figure 3. 8257 Block Diagram Showing DMA
Channels

2-73

8257/8257·5

These two bits are not modified during a DMA cycle, but
can be changed between DMA blocks,

BIT 15

Each channel accepts a DMA Request (DROn) input and
provides a DMA Acknowledge (DACKn) output

(ORO O-DRO 3)

BIT 14

TYPE OF DMA OPERATION

0

0

0
1
1

0

Verily DMA Cycle
Write DMA Cycle
Read DMA Cycle
(Illegal)

1
1

DMA Request: The'S'e are Individual asynchronous channel request inputs used by the peripherals to obtain a DMA
'cycle, If not in the rotating priority mode then DRO 0 has
the highest priority and DRO 3 has the lowest. A request
can be generated by raising the request line and holding It
high until DMA acknowledge, For multiple DMA cycles
(Burst Mode) the request line is held high until the DMA
acknowledge of the last cycle arnves,

(DACK 0 - DACK 3)
DMA Acknowledge: An active low level on the acknowledge output informs the peripheral connected to that
channel that it has been selected for a DMA cycle, The
DACK output acts as a "chip select" for the penpheral
device requesting service_ This line goes active (low)
and inactive (high) once for each byte transferred even if
a burst of data is being transferred,

0Acifl

ORO 2
A,

tmn

2_ Data Bus Buffer

'"

This three-state, br-directional, eight bit buffer interfaces
the 8257 to the system data bus,

A.

A,
A.
A.

(0 0.07)
Data Bus Lines: These are bl-directional three-state hnes
When the 8257 is being programmed by the CPU, elghtbits of data for a DMA address register. a terminal count
register or the Mode Set register are received on the data'
bus, When the CPU reads a DMA address register, a
terminal count register or the Status register, the data is
sent to the, CPU over the data bus, DUring DMA cycles
(when the 8257 is the bus master), the 8257 Will output the
most significant eight-bits of the memory address (from
one of the DMA address registers) to the 8212 iatch via the
data bus, These address bits Will be transferred at the
beginning of the DMA cycle; the bus WI)I then be released
to handle the memory data transfer dUring the balance of
the DMA cycle,

0iC'if"l

MfMR
M'E"MVi

Figure 4. 8257 Block Diagram Showing Data Bus
Buffer

2-74

8257/8257·5

3. ReadlWrite logic

(Ao-A3l

When the CPU is programming or reading one of the
8257's registers (Le., when the 8257 is a "slave" device on
the system bus), the ReadlWrite logic accepts the 110
Read (i7OR) or I/O Write (i7OW) signal, decodes the least
significant four address bits, (Ao-A3), and either writes
the contents of the data bus into the addressed register
(if I/OW is true) or places the contents of the addressed
reJister onto the data bus (if i70R is true).

Address Lines: These least significant four address lines
are bi-directional. In the "slave" mode they are inputs
which select one of the registers to be read or
programmed. In the "master" mode, they are outputs
which constitute the least significant four bits of the 16-bit
memory address generated by the 8257.

DUring DMA cycles (I e, when the 8257 IS the bus
"master"), the Read/Wrote logic generates the I/O read
and memory write (DMA write cycle) or I/O Write and
memory read (DMA read cycle) signals which control the
data link with the peripheral that has been granted the
DMA cycle.

Chip Select An active-low Input which enables the I/O
Read or I/O Wrote Input when the 8257 IS being read or
programmed In the "slave" mode In the "master" mode,
CS is automatically disabled to prevent the chip from
selecting Itself whole performing the DMA function

Note that during DMA transfers Non-DMA I/O devltes
should be de-selected (disabled) uSing "AEN" signal to
Inhibit I/O deVice decoding of the memory address as an
erroneous deVice address.

4. Control logic
ThiS block controls the sequence of operations dUring all
DMA cycles by generatong the appropriate control signals
and the 16-blt address that specifies the memory locallon
to be accessed

(I/OR)
I/O Read' An acllve-Iow, bi-directlonal three-state lone. In
the "slave" mode, It is an Input which allows the 8-blt
status register or the upper/lower byte of a 16-blt DMA
address register or terminal count register to be read. In
the "master" mode, I/OR IS a control output which is used
to access data from a peripheral dUring the DMA write
cycle.

o~oo

(I/OW)
I/O Write' An active-low, bl-dlrectional three-state line In
the "slave" mode, It IS an Input which allows the contents
of the data bus to be loaded onto the 8-blt mode set register
or the upper/lower byte of a 16-blt DMA address register
or terminal count register In the "master" mode, I/OW IS a
control output which allows data to be output to a
peripheral dUring a DMA read cycle

ES----'
A.
A,
A.
A,
CONTROL

LOGIC
AND
MOOE

(ClK)

SH

Clock Input: Generally from an Intel®8224 Clock Generator
device. (¢2 TTL) or Intel ® 8085AH ClK output.
(RESET)
Reset: An asynchronous input (generally from an 8224
or 8085 device) which disables all DMA channels by
clearing the mode register and 3-states all control lines.

Figure 5. 8257 Block Diagram Showing
Read/Write Logic Function

2-75

825718257·5

(Te)

Address lines These four address lines are three-state
outputs which constitute bits 4 through 7 of the 16-blt
memory address generated by the 8257 dUring all DMA
cycles
(READY)

Ready: This asynchronous Input is used to elongate the
memory read and write cycles In the 8257 with wait
states if the selected memory requires longer cycles
READY must conform to specified setup and hold
times
(HRQ)

Hold Request: This output requests control' of the
system bus In systems with only one 8257, HRQ Will
normally be applied to the HOLD input on the CPU HRQ
must conform to specified setup and hold times,
(HLDA)
Hold Acknowledge: This input from the CPU indicates that
the 8257 has acquired control olthe system bus. HLDA must
remain stable during the specified set-up time. '

Terminal Count. ThiS output notifies the currently
selected peripheral that the present DMA cy<;le should be
the last cycle for thiS data block If the TC STOP bit In the
Mode Set register IS set, the selected channel Will be
automatically disabled at the end of that DMA cycle TC is
activated when the 14-bit value in the selected channel's
terminal count register equals zero. Recall that the loworder 14-blts of the terminal count register should be
loaded with the values (n-1), where n =the deSired number
of the DMA cycles.
(MARK)

Modulo 128 Mark ThiS output notifies the selected
peripheral that the current DMA cycle IS the 128th cycle
Since the prevIous MARK output MARK always occurs at
128 (and all multiples of 128) cycles from the end of the
data block Only If the total number of DMA cycles (n) IS
evenly dlvlsable by 128 (and the,termlnal count register
was loaded With n-1). Will MARK occur at 128 (and each
succeeding multiple of 128) cycles from the beginning of
the data block

(MEMR)

Memory Read ThiS active-low three-state output IS used
to read data from the addressed memory location dUring
DMA Read cycles

DROO

(MEMW)

Memory Write ThiS active-low three-state output IS used
to write data Into the addressed memory location during
DMA Write cycles.

OAa,

(ADSTB)

Address Strobe: This output strobes the most significant
byte of the memory address into the latch device from the
data bus.
(AEN)

Address Enable ThiS output IS used to disable Ifloall the
System Data Bus and the System Control Bus It may also
be used to disable Ifloatl the System Address Bus by use
of an enable on the Address Bus drivers In systems to
inhibit non-DMA deVices from responding dUring DMA
cycles It may be further used to Isolate the 8257 data bus
from the System Data Bus to facilitate the transfer of the 8
most significant DMA address bits over the 8257 data 1/0
PinS without sublecting the System Data Bus to any
timing constraints for the transfer When the 8257 IS used
in an 1/0 deVice structure las opposed to memory
mappedl,thls AEN output should be used to disable the
selection of an 1/0 deVice when the DMA address IS on the
address bus The 1/0 deVice selection should be
determined by the DMA acknowledge outputs for the 4
channels

Figure 6. 8257 Block Diagram Showing Control
Logic and Mode Set Register

2-76

825718257·5

5. Mode Set Register
When set, the various bits in the Mode Set register enable
each of the four DMA channels, and allow four different
options for the 8257:
76543210

Enables
Enables
En~ble.
E.. b'..

~II~

I

AUTOLOAD
Enable, DMA
TC STOP
Enables OMA
EXTENDED W R ' T E E M b ' " DMA
ROTATING PR'OR'TY
En,b'.. OMA

Channel 0
Channell
Ch.nn,' 2
Ch,nn"3

The Mode Set register IS normally programmed by the
CPU after the DMA address reglsterts) and terminal
count register(s) are initialized. The Mode Set Register IS
cleared by the RESET Input, thus disabling all optIOns,
inhibiting all channels, and preventing bus conflicts (l)n
power-up. A channel should not be left enabled unless ItS
DMA address and terminal count registers contain valid
values; otherwise, an Inadvertent DMA request (DROn)
from a peripheral could initiate a DMA cycle that would
destroy memory data
The variOus optoons which can be enabled by bits In the
Mode Set register are explained below'

Rotating Priority Bit 4
In the Rotating Priority Mode, the Priority of the channels
has a circular sequence After each DMA cycle. the
Priority of each channel changes The channel wh,ch had
lust been serviced Will have the lowest Priority

Note that rotating priority will prevent anyone channel
from monopolizing the DMA mode; consecutive DMA
cycles will service different channels if more than one
channel is enabled and requesting service. There is no
overhead penalty associated with this mode of opera·
tion. All DMA operations began with Channel 0 initially
assigned to the highest priority for the first DMA cycle.

Extended Write Bit 5
If the EXTENDED WRITE bit IS set, the duration of both the
MEMW and IIOW signals IS extended by activating them
earlier In the DMA cycle Data transfers Within microcomputer systems proceed asynchronously to allow
use of variOus types cif memory and 1/0 devices with
different access times If a device cannot be accessed
Within a spec,flc amount of time ,t returns a "not ready"
indication to the 8257 that causes the 8257 to insert one or
more walt states In ItS Internal sequencing Some devices
are fast enough to be accessed Without the use of wait
states, but If they generate their READY response With the
leading edge of the IIOW or MEMW signal (which
generally occurs late In the transfer sequence), they
would normally cause the 8257 to enter a walt state
because It does not receive READY In time For systems
With these types of devices. the Extended Write option
provides alternative timing for the 1/0 and memory write
s'gnals which allows the devices to return an early READY
and prevents the unnecessary occurrence of walt states In
the 8257. thus increasing system throughput

TC Stop Bit 6
If the TC STOP bit IS set, a channel IS disabled (I e., ItS
enable bit IS reset) after the Terminal Count (TC) output
goes true, thus automatically preventing further DMA
operation on that channel The enable b,t for that channel
must be re-programmed to continue or begin another
DMA operatIOn If the TC STOP bit IS not §et, the
occurrence of the TC output has no effect on the channel
enable bits In thiS case, It IS generally the responsibility of
the peripheral to cease DMA requests In order to terminate
a DMA operation
If the ROTATING PRIORITY bit IS not set (set to a zero),
each DMA channel has a fixed Priority In the flxed,prlorlty
mode, Channel 0 has the highest Priority and Channel 3
has the lowest p'rlorlty If the ROTATING PRIORITY bit IS
set to a one, the Priority of each channel changes after
each DMA cycle (not each DMA request) Each channel
moves up to the next highest Priority assignment. while
the channel which has lust been serviced moves to the
lowest Priority assignment

CHANNEL'" CH-O CH-1 CH-2 CH-3
JUST SERVICED
Priority _
A"'gnman'.

High"'

~

Lowa.'

CH-1
CH-2
CH-3
CH·O

CH-2
CH-3
CH-O
CH·1

CH-3
CH-O
CH·1
CH-2

CH-O
CH-1
CH·2
CH·3

Auto Load Bit 7
The Auto Load mode permits Channel 2 to be used for
repeat block or block chaining operatoons, without
Immediate software Interventoon between blocks Channel 2 registers are Inlt,allzed as usual for the first data
block, Channel 3 registers, however, are used to store the
block re-Inltlallzatlon parameters (DMA starting address,
terminal count and DMA transfer mode) After the first
block of DMA cycles IS executed by Channel 2 (I e , after
the TC output goes true), the parameters stored In the
Channel 3 registers are transferred to Channel 2 dUring an
"update" cycle Note that the TC STOP feature, desCribed
above, has no effect on Channel 2 when the Auto Load bit
IS set

2-77

8257/8257·5

If the Auto Load bit is set, the initial parameters for
Channel 2 are automatically duplicated in the Channel 3
registers when Channel 2 is programmed. This permits
repeat block operations to be set up with the programming
of a single channel. Repeat block operations can be used
in applications such as CRT refreshing. Channels 2 and 3
can still be loaded with separate values if Channel 2 is
loaded before loading Channel 3. Note that in the Auto
Load mode, Channel 3 is still available to the user if the
Channel 3 enable bit is set. but use of this channel will
change thE! values to be auto loaded into Channel 2 at
update time. All that is necessary to use the Auto Load
feature for chaining 'operations is to reload Channel 3
registers at the conclusion of each update cycle with the
new parameters for the next data block transfer.

TC STATUS FOR CHANNEL 0
TC STATUS FOR CHANNEL 1

' - - - - T C STATUS FOR CHANNEL 2
~----TC STATUS FOR CHANNEL 3

The TC status bits are set when the Terminal Count (TC)
output is activated for that channel. These bits remain set
until the status register is read or the 8257 is reset. The
UPDATE FLAG. however. is not affected by a status
register read operation. The UPDATE FLAG can be
cleated by resetting the 8257. by changing to the non-auto
load mode (Le .• by resetting the AUTO LOAD bit in the
Mode Set register) or it can be left to clear itself at the
completion of the update cycle. The purpose of the
UPDATE FLAG~s to prevent the CPU from inadvertently
skipping a data block by overwriting a starting address or
terminal count in the Channel 3 registers before those
parameters are properly auto-loaded into Channel 2.

Each timll that the 8257 enters an update cycle, the update
flag in the status register is set and parameters in Channel
3 are transferred to Channel 2, non-destructivelY for
Channel 3. The actual re-initialization of Channel 2 occurs
at the beginning of the next channel 2 DMA cycle after the
TC cycle. This will be the first DMA cycle of the new data
block for Channel 2. The update flag is cleared at the
conclusion of this DMA cycle. For chaining operations.
the update flag in the status register can be monitored by
the CPU to determine when the re-initialization process
has been completed so that the next block parameters can
be safely loaded into Channel 3.

The user is cautioned against reading the TC status
register and using this information to reenable channels that have not completed operation. Unless the
DMA channels are inhibited a channel could reach ter·
minal count (TC) between the status read and the mode
write. DMA can be inhibited by a hardware gate on the
HRQ line or by disabling channels with a mode word
before reading the TC status ..

6. Status Register
The eight-bit status register indicates which channels
have reached a terminal count condition and includes the
update flag described previously.

_IPARAMETERSI_IPARAMETERSI_
FOR BLOCK 1 I
FOR BLOCK 2

_1:~:AB~~~~R:1c

CHANNEL 2 UPDATE
OCCURS HERE ~

-I

ETC - - - - -

CHANNEL 2 UPDATE
OCCURS HERE ~

I/O WRITE

ORo2

------------~-\.--DATABLDCK

'_1

TC

UflDATE fLAG

Figure 7. Autoload Timing

2-78

--~~~---DATA BLOCK 2 - l

I-TDATA BLOCK 3 -

8257/8257·5

OPERATIONAL SUMMARY
Programming and Reading the 8257 Registers
There are four pairs of "channel registers'" each pair
consisting of a 16-bit DMA address register and a 16-blt
terminal count register (one pair for each channel) The
8257 also includes two "general registers". one 8-bit
Mode Set register and one 8-bit Status register. The
registers are loaded or read when the CPU executes a
write or read instruction that addresses the 8257 device
and the appropriate register within the 8257. The 8228
generates the appropriate read or write control signal
(generally IIOR or IIOW while the CPU places a 16-bit
address on the system address bus, and either outputs the
data to be written 'onto the system data bus or accepts the
data being read from the data bus. All or some of the most
significant 12 address bits A4-A'5 (depending on the
systems memory, liD configuration) are usually decoded
to produce the chip select (CS) Input to the 8257, An liD
Write input (or Memory Write in memory mapped liD
configurations, described below) specifies that the
addressed register is to be programmed, while an liD
Read Input (or Memory Read) specifies that the addressed
register IS to be read Address bit 3 specIfies whether a
"channel register" (A3 = 0) or the Mode Set (program
only)/Status (read only) register (A3 = 1) IS to be accessed.
The least significant three address bitS, Ao-A2, indicate the
specific register to be accessed. When accessing the
Mode Set or Status register, Ao-A2 are all zero. When
accessing a channel register bit Ao differentiates between
the DMA address register (Ao = 0) and the terminal count
register (Ao = 1), while bits A, and A2 specify one of the

CONTROL INPUT

Cs

IIOW

IIOR

A3

Program Hall 01 a
Channel Register

0

0

1

0

Read Hall 01 a
Channel Register

0

1

0

0

Program Mode Set
Register

0

0

1

1

"Read Status Register

0

1

0

1

four channels Because the "channel registers" are 16bits, two program instruction cycles are required to load
or read an entire register. The 8257 contains a first/last
(F/L) flip flop which toggles at the completion of each
channel program or read operation, The F/L flip flop
determines whether the upper or lower byte of the register
IS to be accessed. The F/L flip flop IS reset by the RESET
input and whenever the Mode Set register is loaded. To
maintain proper synchronization when accessing the
"channel registers" all channel command instruction
operations should occur in pairs, with the lower byte of a
register always being accessed firSt. Do not allow CS to
clock while either IIOR or IIOW is active, as thiS Will cause
an erroneous F/L flip flop state In systems utiliZing an
Interrupt structure, Interrupts should be disabled prior to
any paired programming operations to prevent an
Interrupt from splitting them, The result of such a spilt
would leave the F IL F IF In the wrong state This problem is
particularly obVIOUS when other DMA channels are
programmed by an Interrupt structure

8257 Register Selection
'BI-DIRECTIONAL DATA BUS

ADDRESS INPUTS
REGISTER

BYTE

CH-O DMA Address

F/L

A3

A2

A1

Ao

LSB
MSB

0
0

0
0

0
0

0
0

0
1

LSB
MSB

0
0

0
0

0

1

0

0

1

1

LSB
MSB

0

0
0

1
1

0
0

0
1

CH-l Terminal Count

LSB
MSB

0

0
0

1
1

1

0

1

1

CH-2 DMA Addre.s

LSB
MSB

0
0

1

0
0

0
0

0
1

LSB
MSB

0
0

1

0
0

1
1

0
1

LSB
MSB

0
0

1
1

1
1

0

0

0

1

LSB
MSB

0

1
1

1
1

1
1

0

0

MODE SET (Program only)

-

1

0

0

0

0

AL

TCS

EW

RP

EN3 EN2 ENI

ENO

STATUS (Read only)

-

1

0

0

0

0

0

0

0

UP

TC3 TC2 TCI

TCO

CH-O Terminal Count

CH-l DMA Addres.

CH-2 Terminal Count
'CH-3 DMA Addres.
CH-3 Terminal Count

0
0

1
1

0-,

Ds

Ds

D4

D3

D2

D1

Do

A7
A1S
C7
Rd

As
A14
Cs
Wr

As
A13
Cs
C13

A4
A12
C4
C12

A3
A11
C3
C11

A2
A10
C2
C10

A1
Ag

Ao
As

C1
Cg

Co
Ca

Same as Channel 0

I

I I

Same as Channel 0

I I I

Same as Channel 0

1

'AO-A1S: DMA Starting Address, Co-C13:Terminal Count value (N-1), Rd and Wr: DMAVerify (00), Write (01) or Read (10) cycle selection,
AL: Auto Load, TCS: TC STOp, EW: EXTENDED WRITE, RP: ROTATING PRIORITY, EN3-ENO: CHANNEL ENABLE MASK, UP: UPDATE
FLAG, TC3-TCO: TERMINAL COUNT STATUS BITS.

2-79

inter

825718257·5

read and write commands and byte transfer occurs between the selected I/O device and memory. After the
trans'fer is complete, the OACK line is set HIGH and the
HRO line is set LOW to indicate to the CPU that the bus
is now free for use. ORO must remain HIGH until OACK
is issued to be recognized and must go LOW before S4
of the transfer seque,nce to prevent another transfer
from occuring. (See timing diagram.)

RT'
SI
SAMPLE OROn LINES

SET HRO If ORO" '" 1

~DRQt,

Consecutive Transfers
\

so
SAMPLE HLOA

RESOLVE OROn PRIORITIES

l
,--..

HLDA

1

S'
PRESENT AND LATCH
UPPER ADDRESS
PRESENT LOWER ADDRESS

,

~

Control Override

S2
ACTIVATE READ COMMAND
ADVANCED WRITE COMMAND

AND DACKn

~

r--

S3
ACTIVATE WRITE COMMAND
ACTIVATE MARK ANO lC
IF APPROPRIA

re

~ READY

--

OROn HLDA

I

READY
VERIF;

SN

~~
READY
LINE

'-+ VERIFY

S4
RESET ENABLE fOR CHANNEl N If
Te STOP AND TC ARE ACTIVE
DEACTIVATE COMMANDS
DEACTIVATE OACKn MARK AND TO

READY

SAMPLE QROn AND HLOA
RESOLVE OROn PRIORITIES
RESET HRO IF HLOA ~ 0 OR ORO" 0

l

If more than one channel requests service simultaneous·
Iy, the transfer will occur in the same way a burst does.
No overhead is incurred by switching from one channel
to another. In each S4 the ORO lines are sampled and
the highest priority request is recognized during the
next transfer. A burst mode transfer in a lower priority
channel will be overridden by a higher priority request.
Once the high priority transfer has completed control
will return to the lower priority channel if its ORO is still
active. No extra cycles are needed to execute this sequence and the HRO I'ine remains active until all ORO
lines go LOW,

The continuous OMA transfer mode described above
can be interrupted by an external device by.lowering the
HLOA line, After each OMA transfer the 8257 samples
the HLOA line to insure that it is still active. If it is not
active, the 8257 completes the current transfer, releases
the HRO line (LOW) and returns to the idle state. If ORO
lines are still active the 8257 will raise the HRO line in
the third cycle and proceed normally. (See timing
diagram.)

Not Ready
The 8257 has a Ready input similar to the 8080A and the
8085AH, The Ready line is a sampled in State 3. If Ready is
LOW the 8257 enters a waft state. Ready is sampled during
every wait state, When Ready returns HIGH the 8257
proceeds to State 4 to complete the transfer. Ready is used to
interface memory of I/O devices thatcannot meet the bus set
up times required by the 8257.

j.iLOA + oROn

Speed
lORan REFERS TO ANY ORO LINE ON AN ENABLEO OMA CHANNEL

Figure 8. DMA Operation State Diagram

The 8257 uses four clock cycles to transfer a byte of
data. No cycles are lost in the master to master transfer
maximizing bus efficiency. A 2MHz clock input will
allow the 8257 to transfer at a rate of 500K bytes/second.

Memory Mapped I/O Configurations
DMA OPERATION
Single Byte Transfers
A Single byte transfer is initiated by the I/O device raising the ORO line of one channel of the 8257. If the chan·
nel is enabled, the 8257 will output a HRO to the CPU.
The 8257 now waits until a HLOA is received insuring
that the system bus is free for its use. Once HLOA is
received the ~ line for the requesting channel is ac·
tivated (LOW). The ~ line acts as a chip select for
the requesting I/O device. The 8257 then generates the

The 8257 can be connected to the system bus as a memory
deVice Instead of as an I/O deVice for memory mapped I/O
configurations by connecting the system memory control
lines to the 8257's I/O control lioes and the system I/O
control lines to the 8257's memory control lines
ThiS configuration permits use of the 8080's conSiderably
larger repertoire of memory instructions when reading or
loading the 8257's registers. Note that With thiS
connection, the programming of the Read (bit 15) and
Wnte (bit 14) bits In the terminal count register Will have a
different meaning

2-80

inter

825718257·5

ii01i5"

MEMRD

MEMWR

I/OWR

I/O AD

M'E'MA'5

i70WR

MEMWR

8257

Figure 9. System Interface for Memory
Mapped I/O

BIT 15
READ

BIT 14
WRITE

0
0
1
1

0
1
0
1

DMA Verify Cycle
DMA Read Cycle
DMA Write Cycle
Illegal

Figure 10. TC Register for Memory Mapped
I/O Only

SYSTEM APPLICATION EXAMPLES
\
\

\

ADDRESS BUS

fr
II

Jj

CONTROL BUS

1''1

flOW

i70R

DATA BUS

D U

II

I

" "

11 D I

ORO 0

-------

ORO 1

DISK 2

DACK 1

\

U D JJ_

DISK 1

OACK 0

8251
AND
8212

II

I

SYSTEM

RAM

.

MEMORY

------

OR02

DISK 3

OACK 2
DRQ3

-------

DACK 3

DISK 4

OMA CONTROLLER

Figure 11. Floppy Disk Controller (4 Drives)

ORO

8257
AND
8212

DACK

8251
USART

SYSTEM

RAM
MEMORY

MODEM

TElEPHONE

LINES

Figure 12. High-Speed Communication Controller
2-81

\

inter

8257/8257-5

A.C. TESTING INPUT, OUTPUT WAVEFPRM

A.C. TESTING LOAD CIRCUIT

I

INPUT/OUTPUT

"=X >
2.0

08

0.45

<

2.0

TEST POINTS

0.8

x=

DEVICE
UNDER
TEST

ICL~150PF
':"

A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND a 45V FOR
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND 0 8V FOR A LOGIC 0

CL INCWDES JIG CAPACITANCE

Tracking Parameters
Signals labeled as Tracking Parameters (footnotes 1 and 5-7 under A.C. Specifications) are signals that follow similar
paths through the silicon die. The propagation speed of these signals varies in the manufacturing process but the
relationship between all these parameters is constant. The variation is less than or equal to 50 ns.
Suppose the following timing equation is being evaluated,
TA(MIN)

+ T8(MAX) s 150 ns

and only minimum specifications exist for TA and TB. If TA(MIN) is used, and if T A and TB are tracking parameters,
T8(MAX) can be taken as T8(MIN) + 50 ns.
TA(MIN) + (T8(MIN)- + 50 ns) s 150 ns

Olf TA and TBare trackl ng parameters

WAVEFORMS-PERIPHERAL MODE
WRITE
_ _ _"

-TAW--

f.TWA

CHiI'"S£UC'f

READ

__________

DATA BUS

J~----~--~p

__

I/OWR

2-82

inter

825718257 ·5

WAVEFORMS-DMA
CONSECUTIVE CYCLES AND BURST MODE SEQUENCE
~

I

~

I •

I

~

I

g

I

a

I

Y

SI

S2

I

S3

Y

I

SI

SI

SI

CLOCK

DR003 __~__~+-

______

~-4

____-+____

-J~

-+____________

________4-____________~~____

HRO ________J

- \._----

HLDA ____________- / 1

AEN ____________

~--Jj

ADR 07 (LOWER ADR)-

DATA

-

a 7 (UPPER ADR) _ _

-

_

ADR STB _______"

DACK 0 3

MEMIRD/i'7'ORiJ_

READY

Te/MARK

CLOCK
NOTE

The clodo: w..... form

1$

duplicated for clarity
The 8257 requires only
one clock mput

SI

I

SI

so

S1

S2

S3

2-83

Y

S1

a

Y

SI

SI

SI

intJ

825718257·5

WAVEFORMS (Continued)
CONTROL OVERRIDE SEQUENCE
1

54

I so

SI

SI

S1

I.

S2

CLOCK

OROO.3

-----"\.,.,--------T------

HRO

HLOA

-..11 F

HS
T

- - - - - - - . "'"""- _ _ _ _ _

t--

TAEl - - \

AEN

J

J.---

''-_ _ _-'7

NOT READY SEQUENCE

SOl

~

1

S2

~

1

I

~

1

~

54

~

1

SI

1

SI

CLOCK

DR003

_~

--+"Io--_____

____

=~~~~~: TR_·1~:~ F
REAOV

TC/MA.RK

_____

I

2-84

I

:J.,.I-..,. . .T_

11

~

RS_ _ __

\

___ _

in1er

825718257·5

A ..

,
,

A.

~

ALE

r---..!.!.

STB

DS2

13

MD

OS;

01,--01,

,

,
,

r-

r-

AD,

V"

JIll

Wli

~

~Al
~B,

~A2

--!

~

B,

~B3
~A'

;!:

0,
,
,
,
,
0,

~A.

4
7

•

12

~

rrr-

il!l\

lOW

r-

13 B.

CHIP
SelECT

DE
SEL (B)

IO/Q

1

L

:;

HOLD
HLOA

elK (OUT)

RESET iN
RESET OUT

r--

A,

V"

m ~

AD,

....

AODRESS

BUS

00.--00,
8212

-f

G~"
)~'
V

DATA BUS

0,

MEMR

Il!II

I~

READY

I·

"1es

READY
A,
,

:7

-

~7-

0,
82575

RESET

-

r--

'-----

-

"'

----2...:
----l..:
~

MEMR

DRDo

il!l\

OACKo

ORO,

MEMW

----l...,: iOW

OACK,
ORa,

--!.L

HRO

~

HLOA

--.2.!-

elK

~

RESET

DACK,
ORO]

OACK 1
TC
MARK

AEN

•

2.

17

,.

,.,.
'"

•

ADST8

•

j' "

r-13

~

"
,.

2'

DS2

CLR

01,
,
,

8212

01,

MD

STB

DO,
,

,

00,

os;

t l'
Figure 13. Detailed System Interface Schematic

2-85

ORa,

DACK o

ORO,
QACK,

ORO,
DACK 2
OR03

i5'AC'K 1
TC
MARK

CONTROL

BUS

inter

8257/8257-5

ABSOLUTE M~XIMUM RATINGS·
Ambient Temperature Under Bias ......... O°C to 70°C
Storage Temperature ............... -65°C to +150°C
'
Voltage on Any Pin
With Respect to Ground .............. -0.5V to + 7V
Power Dissipation ............................ 1 Watt

D.C. CHARACTERISTICS

"NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

(8257: TA = O°C to 70°C. Vee = 5.0V ±5%. GND = OV)
'(8257-5: TA = O°C to 70°C. Vee = 5.0V ±10%. GND = OV)

Symbol

Parameter

Min.

Max.

Unit

V,L

Input low Voltage

-0.5

0.8

Volts

V,H

Input High Voltage

2.0

Vee+· 5

Volts

VOL

Output low Voltage

0.45

Volts

IOL = 1.6 rnA

VOH

Output High Voltage

2.4

Vee

Volts

IOH =-150IlA for AB.
DB and AEN
IOH =-80IlA for others

3.3

Vee

Volts

IOH = -801lA

120

rnA

\

VHH

HRQ Output High Voltage

Icc

Vee Current Drain

I,L

Input leakage

±10

IlA

IoFL

Output leakage During Float

±10

IlA

CAPACITANCE
Symbol

Test Conditions

OV '" V,N '" Vee
0.45V '" Vour '" Vee

(TA = 25°C; Vee = GND = OV)

Parameter

Min.

Typ.

Test Conditions

Max.

Unit

C'N

Input Capacitance

10

pF

fc = lMHz

CliO

1/0 Capacitance

20

pF

Unmeasured pIns
returned to GN 0

2-86

intJ

8257/8257·5

A.C. CHARACTERISTICS-PERIPHERAL (SLAVE) MODE
(8257: TA = O°C to 70°C, Vee = 5.0V ±5%, GND = OV)
(8257-5: TA = O°C to 70°C, Vee = 5.0V ±10%, GND = OV)
8080 Bus Parameters
READ CYCLE
8257
Symbol

Parameter
CS~

Setup to

Min.

RD~

8257·5

Max.

Min.

Max.

Unit

TAR

Adr or

TRA

Adr or cst Hold from RDt

0

TRo

Data Access from R D ~

0

300

0

220

ns

ToF

D8 .... Float Delay from RDt

20

150

20

120

ns

TRR

RD Width

250

0

Test Conditions

ns

0

ns

0

ns

250

WRITE CYCLE
8257
Symbol

Parameter

Min.

WR~

8257·5
Max.

20

Min.

Max.

Unit

Adr Setup to

TWA

Adr Hold from WRt

0

0

ns

Tow

Data Setu p to WR t

200

200

ns

10

10

ns

200

200

ns

Two

Data Hold from WR t

Tww

WR Width

T est Conditions

ns

TAW

20

OTHER TIMING
8257
Symbol

Parameter

-,

8257-5
Max.

Min.

Min.

Max.

Reset Pulse Width

300

300

ns

TRSTo

Power Supplyt.(Vccl Setup to Reset~

SOO

500

}J.S

T,

Signal Rise Time

20

20

ns

Tf

Signal Fall Time

20

20

ns

TRSTS

Reset to First I/OWR

:t

2

Test Conditions

Unit

T RSTW

tCY

A.C. CHARACTERISTICS-DMA (MASTER) MODE
(8257: TA = O°C to 70°C, Vee = 5.0V ±5%, GND = OV)
(8257-5: TA = O°C to_70°C, Vee = 5.0V ±10%, GND = OV)
TIMING REQUIREMENTS

Symbol

8257·5

8257

Parameter

Min.

Max.

Min.

Max.

Unit

TCY

Cycle Time (Period)

0.320

4

0.320

4

P.s

T6

Clock Active (High)

120

.8TCY

SO

.8TCY

ns

Tas

DROI Setup to ClKI (SI, S4)

120

120

TaH

ORal Hold from HlDAI[1]

0

0

T HS

HlDA I or ISetup to CLKI(SI, S4) [7J

100

T RS

READY Setup Time to ClKI(S3, Sw)

30

30

ns

TRH

READY Hold Time from ClKI(S3, Sw)

30

30

ns

2-87

280

100

ns
ns

280

ns

inter

825718257·5

A.C. CHARACTERISTICS-DMA (MASTER) MODE
(82S7: TA = O'C to 70'C, vcc = S.OV ±S%, GND = OV)
(82S7-S: TA = O'C to 70'C, vcc = S.OV ±10%, GND = OV)

TIMING RESPONSES

8257

Parameter.

Symbol

Min.

8257·5
Max.

Min.

Unit
Max.

Too

HRQi or tDelay from ClKt (SI, S4)
(measured at 2.0V)

160

160

ns

TOOl

HRQi or tDelay from ClK, (SI, S4)
(measured at 3.3V)[3]

2S0

2S0

ns

TAEL

AENt Delay from ClKt (S1)

300

300

ns

TAET

AENt Delay from ClKi (SI)

200

200

ns

TAEA

Adr (AB) (Active) Delay from AENt (81)[1]

TFAAB

Adr ,tAB) (Active) Delay from ClK, (S1 )[2]

2S0

2S0

ns

TAFAB

Adr (AB) (Float) Delay from ClK, (SI)[2]

1S0

1S0

ns

TASM

Adr (AB) (Stable) Delay from ClKt (S1)[2]

2S0

2S0

ns

TAH

Adr (AB) (Stable) Hold from ClKt (S1)[2]

TASM-SO

TASM -SO

ns

TAHR

Adr (AB) (Valid) Hold from RDt (S1, SI)[l]

60

60

ns

TAHW

Adr (AB) (Valid) Hold from Wrt (S1, SI)[l]

300

300

ns

TFAOB

Adr (DB) (Active) Delay from ClKt (S1 )[2]

TAFOB

Adr (DB) (Float) Delay from ClKt (S2)[2]

TASS

Adr (DB) Setup to Adr Stbt (S1-S2)[1]

100

100

TAHS

Adr (DB) (Valid) Hold from Adr Stbt (S2)[1]

20

20

TSTL

Adr Stbi Delay from ClKt (S1)

200

200

ns

TSTT

Adr Stbt Delay from ClKt (S2)

140

140

ns

TSW

Adr Stb Width (S1-S2)[1]

TASC

20

20

300
TSTT+20

2S0

ns

300
TSTT+20

170

ns
ns
ns
. ns

TCy-100

TCy-100

ns

Rdt or Wr(Ext)t Delay from Adr Stb,l
(S2)[1]

70

70

ns

TOBC

RDt OrWR\Ext),l Delay from Adr (DB)
(Float) (S2) 1]

20

20

ns

TAK

DACKt or tDelay from ClKt (S2, S1) and
TC/Markt Delay from ClKt (S3) and
TC/Markt Delay from ClKt (S4)[4]

250

2S0

ns

TOCL

ROt or Wr(Ext),l Delay from ClK, (S2j and
Wrt Delay from ClKt (S3)[2,5]

200

200

ns

TOCT

wrt

Rdt Delay from ClK,l (S1, SI) and
Delay from ClKt (S4)[2,6]

200

200

ns

TFAC

Rd or Wr (Active) from ClKt (S1 )[2]

300

300

ns

TAFC

RdiorWr (Active) from ClKt (S1)[2]

1S0

1S0

ns

TRWM

Rd Width (S2-S1 or SI)[l]

TWWM

WrWidth (S3-S4)[1]

TWWME

WR(Ext) Width (S2·S4)[1]

2TCy+TO-SO

ns

TCY-SO

TCY-SO

ns

2TCY-SO

2TCY-SO

ns

2TCy+TO-SO

NOTES:

1. Tracking Parameter.
2. Load = + 50 pF.
7. HLOA must remain stable during tHS.

3.. Load = VOH = 3.3\1.
4. ATAK < 50 ns.

2-88

5. ATOCL < 50 ns.
6. AToCT < 50 ns.

8259AI 8259A-2 18259A-8
PROGRAMMABLE INTERRUPT CONTROLLER
• iAPX 86, iAPX 88 Compatible

• Individual Request Mask Capability

• MCS-80®, MCS-85® Compatible

• Single

• Eight-Level Priority Controller

• 28-Pin Dual-In-Line Package

• Expandable to 64 Levels

• Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range

• Programmable Interrupt Modes

+ 5V Supply (No Clocks)

The Intel'" 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is
cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28·pin DIP, uses
NMOS technology and requires a single + 5V supply. Circuitry is static, requiring no clock input.
The 8259A is designed to minimize the software and real time overhead in handling multi·level priority interrupts. It has
several modes, permitting optimization for a variety of system requirements.
The 8259A is fully upward compatible with the Intel'" 8259. Software originally written for the 8259
8259A in all 8259 equivalent modes (MCS·80/85. Non·Buffered, Edge Triggered).

°7-°0

DATA
BUS
BUFFER

operate the

CONTROL lOGIC

Cs
Wii

i'i5'
IRO
IRI
IR2

Ri5
WR

cs
CASO

CASCADE
CAS 1

Will

Vee

"0
iNfA

0,

IR7

D.

IR6

0,.

IR5

D,

IR4

D,

IR3

D,

IR2

D,

IR1

Do

IRO

CASO

INT

CAS 1

SP/EN

GND

CAS2

BUFFERI
COMPARATOR

CAS2-

SP/EN

~INTEANAl

BUS

Figure 1. Block Diagram

Intel Corporatton Assumes No Responslbllty for the Use of Any CircUitry Other Than Clrcultrv Embodied
©INTEL CORPORATION, 1 9 8 0 '
2-89

Figure 2. Pin Configuration

In

an Intel Product No Other Circuit Patent licenses afe Implied

8259A/8259A-218259A-8

Table 1. PI!, Description
Symbol

Name and Function

Pin No.

Type

Vee

28

I

Supply: +5V Supply.

GND

14

I

Ground.

1

I

Chip Selact: A low on this pin enables RD and WR communication between the CPU and the 8259A.
INTA functIons are independent of CS.

WR

2,

I

Write: A low on this pin when CS is low enables the 8259A to accept command words from the CPU.

RD

3

I

Raad: A low on this pin when CS is low enables the 8259A to release status onto the data busforthe
CPU.

C§

4-11

I/O

Bidirectional Data Bus: Control, status a,nd Interrupt-vector information Is transferred via thIs bus.

12,13,15

I/O

Cascade Lines: The CAS lines form a private 8259A bus to control a multiple 8259Astructure. These
pins are outputs for a master 8259A and inputs for a sla~e 8259A.

SP/EN

16

I/O

Slave Program/Enable Buffer: This is a dual function pin. When In the Buffered Mode it can be used
as an '!utput to control buffer transceivers (EN). When not in the buffered mode it is used as an input
to designate a master (SP = 1) or slave (SP = 0).

INT

17

0

Interrupt: This pin goes hIgh whenever a valid Interrupt request is asserted, It is used to interruptthe
CPU, thus It IS connected to the CPl!'s interrupt pin.

18-25

I

Interrupt Requests: Asynchronous Inputs. An Interrupt request is executed by raising an IR input
(low to high), and holding it high until it is acknowledged (Edge Triggered Mode), or Just by a high
level on an IR input (Level Triggered Mode).

INTA

26

I

Interrupt Acknowledge: ThIS pin Is used to enable 8259A interrupt-vector data onto the data bus by
a sequence of interrupt acknowledge pulses Issued by the CPU.

Ao

27

I

AO Address Line: This pin acts in conjunction wIth the CS, WR, and RD pins. It IS used by the 8259A
to decipher various Command Words the CPU writes and status the CPU wishes to read. It is typically
connected to the CPU AO'l!ddress line (Al for iAPX 86, 88).

0-,-00
CASo-CAS2

IRO-IR7

2-90

inter

8259A/8259A-2/8259A-8

FUNCTIONAL DESCRIPTION
Interrupts in Microcomputer Systems
Microcomputer system design requires that 1/0 devices
such as keyboards, displays, sensors and other com·
ponents receive servicing in an efficient manner so that
large amounts of the total system tasks can be assumed
by the microcomputer with little or no effect on through·
put.

match his system requirements. The priority modes can
be changed or reconfigured dynamically at any time duro
ing the main program. This means that the complete
interrupt structure can be defined as required, based on
the total system environment.

CPU-DRIVEN
MULTIPLEXOR

CPU

The most common method of servicing such devices is
the Polled approach. This is where the processor must
test each device in sequence and in effect "ask" each
one if it needs servicing. It is easy to see that a large por·
tion of the main program is looping through this con·
tinuous polling cycle and that such a method would
have a serious, detrimental effect on system through·
put, thus limiting the tasks that could be assumed by
the microcomputer and reducing the cost effectiveness
of using such devices.

----

--r~
~Q

\
RAM

A more desirable method would be one that would allow
the microprocessor to be executing its main program
and only stop to service peripheral devices when it is
told to do so by the device itself. In effect, the method
would provide an external asynchronous input that
would Inform the processor that it should complete
whatever instruction that is currently being executed
and fetch a new routine that will service the requesting
device. Once this servicing is complete, however, the
processor would resume exactly where it left off.

ROM

~ ~

I )~

1/0(11

1/0(2)

~

r--

r---,

~L ___
1/0 IN}

I
J

...J

V

This method is called Interrupt. It is easy to see that
system throughput would drastically increase, and thus
more tasks could be assumed by the microcomputer to
further enhance its cost effectiveness.

Figure 3a. Polled Method

The Programmable Interrupt Controller (PIC) functions
as an overall manager in an Interrupt·Driven system
environment. It accepts requests from the peripheral
equipment, determines which of the incoming requests
is of the highest importance (priority), ascertains
whether the incoming request has a higher priority value
than the level currently being serviced, and issues an
interrupt to the CPU based on this determination.

CPU

.NT

RAM

Each peripheral device or structure usually has a special
program or "routine" that is associated with its specific
functional or operational requirements; this is referred
to as a "service routine". The PIC, after issuing an Inter·
rupt to the CPU, must somehow input information into
the CPU that can "point" the Program Counter to the
service routine associated with the requesting device.
This "pointer" is an address In a vectoring table and will
often be referred to, in this document, as vectoring data.

1/01'1

ROM

I/O 121

The 8259A
The 8259A is a device specifically deSigned for use in
real time, interrupt driven microcomputer systems. It
manages eight levels or requests and has built·ln fea·
tures for expandabiiity to other 8259A's (up to 64 levels).
It is programmed by the system's software as an 1/0
peripheral. A selection of priority modes is available to
the programmer so that the manner in which the reo
quests are processed by the 8259A can be configured to

I

I/O{N)

I

1_____ J1

Figure 3b. Interrupt Method

2-91

inter

8259A/8259A-2/8259A-8

INTERRUPT REQUEST REGISTER (IRR) AND
IN-SERVICE REGISTER (ISR)
The interrupts at the IR input lines are handled by two
registers in cascade, the Interrupt Request Register
(IRR) and the In-Service Register (ISR). The IRR is used
to store all the interrupt levels which are requesting service; and the ISR is used to store all the interrupt levels
which are being serviced.
PRIORITY RESOLVER
This logic block determines the priorities of the bits set
in the IRA. The highest priority is selected and strobed
into the corresponding bit of the ISR during INTA pulse.
INTERRUPT MASK REGISTER (IMR)
The IMR stores the bits which mask the interrupt lines
to be masked. The IMR operates on the IRA. Masking of
a higher priority input will not affect the interrupt
request lines of lower priority.
INT (INTERRUPT)
This output goes directly to the CPU interrupt input. The
VOH level on this line is designed to be fully compatible
with the 8080A, 8085A and 8086 input levels.

Figure 4a. 8259A Block Diagram

INTA (INTERRUPT ACKNOWLEDGE)
INTA pulses will cause the 8259A to release vectoring
information onto the data bus. The format of this data
depends on the system mode ("PM) of the 8259A.
DATA BUS BUFFER
This 3-state, bidirectional 8-bit buffer is used to interface the 8259A to the system Data Bus. Control words
and status information are transferred through the Data
Bus Buffer.

',-',

READIWRITE CONTROL LOGIC
The function of this block is to accept OUTput commands from the CPU. It contains the Initialization Command Word (ICW) registers and Operation Command
Word (OCW) registers which store the various control
formats for device operation. This function block also
allows the status of the 8259A to be transferred onto the
Data Bus.

~

CS (CHIP SELECT)

If\lHRfIIAl 8US

A LOW on this input enables the 8259A. No reading or
writing of the chip will occur unless the device is
selected.

Figure 4b. 8259A Block Diagram
WR(WRITE)
A LOW on this input enables the CPU to write control
words (leWs and OCWs) to the 8259A.
Ao
This input signal is used in conjunction with WR and RD
signals to write comr;nands into the various command
registers, as well as reading the various status registers
of the chip. This line can be tied directly to one of the address lines.

RD (READ)
A LOW on this input enables the 8259A to send the
status of the Interrupt Request Register (IRR), In Service
Register (ISR), the Interrupt Mask Register (IMR), or. the
Interrupt level onto the Data Bus.

2-92

8259A18259A-2/8259A-8
THE CASCADE BUFFER/COMPARATOR

This function block stores and compares the IDs of all
8259A's used in the system. The associated three 1/0
pins (CASO-2) are outputs when the 8259A is 'used as a
master and are inputs when the 8259A is used as a
slave. As a master, the 8259A sends the 10 of the inter·
rupting slave device onto the CASO-2 lines. The slave
thus selected will send its preprogrammed subroutine
address onto the Data Bus during the next one or two
consecutive INTA pulses. (See section "Cascading the
8259A".)

If no interrupt request is present at step 4 of either
sequence (Le., the request was too short in duration) the
8259A will issue an interrupt level 7. Both the vectoring
bytes and the CAS lines will look like an interrupt level 7
was req uested.

INTERRUPT SEQUENGE

The powerful features of the 8259A in a microcomputer
system are its programmability and the interrupt routine
addressing capability. The latter allows direct or indirect
jumping to the specific interrupt routine requested
without any polling of the interrupting devices. The nor·
mal sequence of events during an interrupt depends on
the type of CPU being used.
The events occur as follows in an MCS·80/85 system:
1. One or more of the INTERRUPT REQUEST lines
(IR7-0) are raised high, selling the corresponding IRR
bit(s).
2. The 8259A evaluates these requests, and sends an
INT to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds with an
INTA pulse.
4. Upon receiving an' INTA from the CPU group, the
highest priority ISR bit is set, and the corresponding
IRR bit is reset. The 8259A will also release a CALL instruction code, (11001101) onto the 8-bit Data Bus
through'its 07-0 pins.
5. This CALL instruction will initiate two more INTA
pulses to be sent to the 8259A from the CPU group.
6. These two INTA pulses allow the 8259A to release its
preprogrammed subroutine address onto the Data
Bus. The lower 8-bit address is released at the first
INTA pulse and and the higher 8-bit address is released at the second INTA pulse.
7. This completes the 3-byte CALL instruction released
by the 8259A. In the AEOI mode the ISR bit is reset at
the end of the third INTA pulse. Otherwise, the ISR bit
remains set until an appropriate EOI command is
issued at the end of t,he interrupt sequence.

SPIE'N _ __

~INlEflNAl8US

Figure 4c. 8259A Block Diagram

The events occurring in an iAPX 86 system are the same
until step 4.
4. Upon receiving an INTA from the CPU group, the highest priOrity ISR bit is set and the corresponding IRR
bit is reset. The 8259A does not drive the Data Bus
during this cycle.
5. The iAPX 86/10 will initiate a second INTA pulse.
During this pulse, the 8259A releases an 8-bit pointer
onto the Data Bus where it is read by the CPU.

I
INTERRUPT
REQUESTS

6. This completes the interrupt cycle. In the AEOI mode
the ISR bit is reset at the end of the second INTA
pulse. Otherwise, the ISR bit remains set until an
appropriate EOI command is issued at the end of the
interrupt subroutine.

,Figure 5. 8259A Interface to Standard
System Bus
2-93

inter

8259A18259A-2/8259A-8

INTERRUPT SEQUENCE OUTPUTS
MCS-80®,

MCS~85®

This sequence is timed by three INTA pulses. During the
first INTA pulse the CALL opcode is enabled onto the
data bus.
Content 01 First Interrupt
Vector Byte
07

I

CALL CODE

06

1

05

04

0

0

03

02

01

not issue any data to the processor and leaves its data bus
buffers disabled. On the second interrupt acknowledge
cycle In iAPX 86 mode the master (or slave if so programmed) will send a byte of data to the processor with
the acknowledged interrupt code composed as follows'
(note the state of the ADI mode control is ignored and
As-All are unused in iAPX 86 mode):"
Content 01 Interrupt Vector Byte
lor IAPX 86 System Mode

00
1

I

07
IR7
IR6
IR5
IR4
IR3
IR2
IRI
IRO

During the second fIiIiA pulse the lower address of the
appropriate service routine is enabled onto the data bus.
When Interval = 4 bits As-A7 are programmed, while AoA4 are automatically inserted by the 8259A. When Inter·
val = 8 only As and A7 are programmed, while Ao-As are
automatically inserted.
Content 01 Second Interrupt
Vector Byte
IR
7
S
S
4
3
2

1
0

3
2

1
0

06
AS
AS
.AS
AS
AS
AS
A6
A6

05
AS
AS
AS
AS
AS
AS
AS
AS

04
1
1
1
1

03
1
1

02
1

01

00

0

0

T7
T7
T7
T7

T7
T7

OS
T5
T5
T5
TS
T5
T5
T5
T5

04
T4
T4
T4
T4
T4
T4
T4
T4

'03
T3
T3
T3
T3
T3
T3
T3
T3

02

01

1

1

1

1

1

0

DO

1

0

1

1

0

0

0

1

1

0

1

0

0

0

1

0

0

0

0

0

1

0
0

0
0

0

0

0

0

1
0

0
0

0
0

0

1
1

0

0

1

0

0

0

0

0

0

0

07
A7
A7
A7
A7
A7
A7
A7
A7

06
A6
A6
AS
A6
A6
A6
A6
A6

05
1
'1
1
1

04
1
1

03

02

01

00

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

InteN,I=8

PROGRAMMING THE 8259A
The 8259A accepts two types of command words gener·
ated by the CPU:
1. Initialization Command Words (JCWs): Before normal
operation can begin, each 8259A in the system must
be brought to a starting point - by a sequence of 2 to
4 bytes timed by WR pulses.
2. Operation Command Words (OCWs): These are the
command words which command the 8259A to oper·
ate in various interrupt modes. These modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259A anytime after
initialization.

INITIALIZATION COMMAND WORDS
(ICWS)
GENERAL

During the third INTA pulse the higher address of the
appropriate service routine, which was programmed as
byte 2 of the initialization sequence (As - A 1s), is
enabled onto the bus.

07
A1S

T7

OS
T6
T6
TS
TS
TS
T6
T6
TEl

Interv.I.4

07
A7
A7
A7
A7
A7
A7
A7
A7

IR
7
6
S
4

T7

Content 01 Third Interrupt
Vector Byte
06
05
04
03
02
A14
A13
A1l
A10
A12

01

DO

A9

AS

Whenever a command is issued with AO = 0 and D4 = 1,
this is interpreted as Initialization Command Word 1
(ICW1). ICW1 starts the initialization sequence during
which the following automatically occur.
a. The edge sense circuit is reset, which means that following initialization, an interrupt request (IR) input
must make a low-to-high transition to generate an
interrupt.
b. The Interrupt Mask Register is cleared.
c. IR7 input is assigned priority 7.
d. The slave mode address is set to 7.
e. Special Mask Mode is cleared and Status Read is set to
IRR.
f. If IC4=O, then all functions selected in ICW4 are set to
zero. (Non-Buffered mode', no Auto-EOI, MCS-80, 85
system).

iAPX 86, iAPX 88
iAPX 86 mode is similar to MCS-80 mode except that only
two Interrupt Acknowledge cycles are issued by the processor and no CALL opcode is sEmt to the processor. The
first interrupt acknowledge cycle is similar to that of
MCS-80, 85 systems in that the 8259A uses it to internally
freeze the state of the interrupts for priority resolution and
as a master it issues the interrupt code on the cascade
lines attheend of the INTA pulse. On this first cycle it does

• Note: Mast~rlSlave In ICW4 IS only used in the buffered mode.

2-94

intJ

8259A18259A-2/8259A-8
INITIALIZATION COMMAND WORD 3 (ICW3)

INITIALIZATION COMMAND WORDS 1 AND 2
(lCW1, ICW2)

This word is read only when there is more than one
8259A in the system and cascading is used, in which
case SNGL = O. It will load the 8·bit slave register. The
functions of this register are:

A5-A 15: Page starting address of service routines. In an
MCS 80/85 system, the 8 request levels will generate
CALLs to 8 locations equally spaced in memory. These
can be programmed to be spaced at intervals of 4 or 8
memory locations, thus the 8 routines will occupy a
page of 32 or 64 bytes, respectively.
The address format is 2 bytes long (Ao-A15)' When the
routine interval is 4, Ao-A4 are automatically inserted by
the 8259A, while A5-A 15 are programmed externally.
When the routine interval is 8, Ao-A5 are automatically
inserted by the 8259A, while As-A15 are programmed
externally.
The 8·byte interval will maintain compatibility with cur·
rent software, while the 4·byte interval is best for a com·
pact jump table.
'
In an iAPX 86 system A1S-A11 are inserted in the five most
significant bits of the vectoring byte and the 8259A sets
the three least significant bits according to the interrupt
level. A1O-AS are ignored and ADI (Address interval) has
no effect.
LTIM:

If LTIM=1, then the 8259A will operate in the
level Interrupt mode. Edge detect logic on the
Interrupt inputs will be disabled.

ADI:

CALL address Interval. ADI = 1 then interval = 4;
ADI = 0 then Interval = 8.

If this bit Is set - ICW4 has to be read. If ICW4
Is not needed, set IC4 = O.

NO (SINGL

=

SFNM: If SFNM = 1 the special fully nested mode is
programmed.
BUF: If BUF = 1 the b'uffered mode is programmed, In
buffered mode SP/EN becomes an enable output
and the masterlslave determination is by MIS.
MIS: If buffered mode is selected: MIS = 1 means the
8259A is programmed to be a master, MIS = 0
means the 8259A is programmed to be a slave. If
BUF = 0, MIS has no function.
AEOI: If AEOI 1 the automatic end of interrupt mode
is programmed.
"PM: Microprocessor mode: I'PM = 0 sets the 8259A for
MCS-80, 85 system operation. I'PM = 1 sets the
8259A for iAPX 86 system operation.

=

SNGL: Single. Means that this Is the only 8259A In the
system. If SNGL= 1 no ICW3 will be issued.
IC4:

a. In the master mode (either when SP = 1, or in buffered
mode when M/S= 1 in ICW4) a "1" is set for each
slave in the system. The master then will release byte
1 of the call sequence (for MCS·80/85 system) and
will enable the corresponding slave to release bytes 2
and 3 (for iAPX 86 only byte 2) through the cascade
lines.
b. In the slave mode (either when SP = 0, or If BUF = 1
and MIS = 0 in ICW4) bits 2-0 identify the slave. The
slave'compares its cascade input with these bits and,
if they are equal, bytes 2 and 3 of the call sequence (or
just byte 2 for iAPX 86 are released by it on the Data
Bus.
INITIALIZATION COMMAND WORD 4 (lCW4)

1)

NO (IC4 =- 0)

Figure 6. Initialization Sequence

2-95

8259A/8259A·2/8259A·8

ICWl

1 leW4 NEEDEO
o ~ NO lew.. NEEDED

1 '" SINGLE
CASCADE MODE

o=

CALL A[,OAESS INTERVAL
1 ~ INTERVAL OF,.
o~ INTERVAL OF B

1 '" LEVEL TRIGGERED MODE
0= EDGE TRIGGERED~MODE

A7-A5 01 INTERRUPT
VECTOR ADDRESS
(Mes·aO/85 MODE ONL Y)

A 15 -"8 OF INTERRUPT
VECTOR ADDRESS

(McsaD/85 MODE)
T 7- T3 OF INTERRUPT
VECTOR ADDRESS
(808618088 MODE)

ICW) IMASTER DEVICE)

1 - IF! INPUT HAS A SLAVE
o . IR INPuT DOES NOT HAVE
A SLAVE

o o.

1

1

1

1

1 "" 8086/8088 MODE
0= MeS-SO/85 MODE

1

AUTO EOI

O· NORMAl EOI

lliE
1
1

x

0
1

NON BUFFERED MODE
- BUFFEReD MODE/SLAVE
- BUFFERED MODE/MASTER

1 :: SPECIAL FULLY NESTED

'--------~-l
NOTE 1: SLAVE 10 IS EQUAL TO THE CORRESPONDING
MASTER IR INPUT

0 =

~gf~PECIAL FULLY
NESTED MODE

Figure 7. Initialization Command Word Format

2-96

8259A/8259A-2/8259A-8
OPERATION COMMAND WORDS (OCWS)

OPERATION CONTROL WORD 1 (OCW1)

After the Initialization Command Words (ICWs) are programmed into the 8259A, the chip Is ready to accept
Interrupt requests at its input lines. However, during the
8259A operation, a selection of algorithms can command the 8259A to operate in various modes through
the Operation Command Words (OCWs).

OCW1 sets and clears the mask bits in the interrupt
Mask Register (IMR). M 7 - Mo represent the eight mask
bits. M = 1 indicates the channel is masked
(inhibited), M 0 indicates the channel is enabled.

=

OPERATION CONTROL WORD 2 (OCW2)
R, SL, EOI - These three bits control the Rotate and
End of Interrupt modes and combinations of the two. A
chart of these combinations can be found on the Operation Command Word Format.

OPERATION CONTROL WORDS (OCWs)

oew1
AO

~

07

I M7

06

05

04

03

02

01

DO

M6

M5

M4

M3

M2

Ml

MO

L2 , L 1 , Lo-These bits determine the interrupt level acted
upon when the SL bit is active.

I

OPERATIClN CONTROL WORD 3 (OCW3)
oeW2

0

I

R

SL

EOI

0

0

L2

Ll

LO

oeW3

0

0

ESMM

SMM

0

P

RR

RIS

ESMM - Enable Special Mask Mode. When this bit is
set to 1 it enables the SMM bit to set or reset the Special
Mask Mode. When ESMM = 0 the SMM bit becomes a
"don't care".

I

SMM - Special Mask Mode. If ESMM = 1 and SMM = 1
the 8259A will enter Special Mask Mode. If ESMM = 1
and SMM = 0 the 8259A will revert to normal mask mode.
When ESMM = 0, SMM has no effect.

I

2-97

8259A/8259A-2/8259A-8
DCW'
0,

0,

INTERRUPT MASK
1 - MASK SET

o • MASK

.

RESET

DCW.
0,

0,

D.

D.

03

0,

0,

0"

I' " I "I I • I • I I I I
EO'

L,

L,

L,

•
•
•
•

I

r

l

,r.-r.,
ct. r+
P,7,

,
1010 •
r,-rt ,
r,-r,-

r,-I;T
tIt:!: ••

,
,
•
•

IRLEYIlTOIE
ACTED . . . .

,
•,
•

,•••,
, •, •,
, ••, ,
, , , ,
•

I

l

NON-SPECIFIC EOICOMMAND
SPeCIFIC EOI COiIWAND

IND OF INTERRUPT

}

A01lUE ON NDN-8PECIFIC EOI COMMAND
RO'WE IN AUTOMATIC EOI MODE (8E1)

ROTATE .. AUTOMA'IlC EOI MODI (CLEAR)

AUTOMATIC AO'IUION

l

*ROTATE ON SPECIFIC EOI COMMAND
*8ET PRKNUTY COMIIIAND

NO OPERATION

SPECIFIC R01JQ1ON

"LO-U:AR£U8I!D

DCW'

I . I I'WMI I • I ' I I I·IS I
0

SMM

p

RR

I

L

.,

READ RmIITER COMMAND
0

I

1

• I •
NO ACTION

"

I

,
1

.EAD
IR REG

READ

ONNE'(T

ON NEXT

RDPULSE

RDPULSE

ISREG

1.. POLLCOMMAHD

D"'NO POLL COMMAND

J
SPECIAL MASK MODE

• I ,
• I •

•,
RESET

NO ACTION

SPECIAL
MASK

FIgure 8. OperatIon Command Word Format

2-98

,
,
SET
SPECIAL
MASK

8259A!8259A-2/8259A-8
FULLY NESTED MODE
This mode is entered after initialization unless another
mode is programmed. The interrupt requests are
ordered in priority form 0 through 7 (0 highest). When an
interrupt is acknowledged the highest priority request is
determined and its vector placed on the bus. Additional·
Iy, a bit of the Interrupt Service register (ISO-7) is set.
This bit remains set until the microprocessor issues an
End of Interrupt (EOI) command immediately before
returning from the service routine, or if AEOI (Automatic
End of Interrupt) bit is set, until the trailing edge of the
last INTA. While the IS bit is set, all furtfier interrupts of
the same or lower priority are inhibited, while higher
levels will generate an interrupt (which will be
acknowledged only if the microprocessor internal Interrupt enable flip-flop has been re-enabled through software).

AUTOMATIC ROTATION

(Equal Priority Devices)
In some applications there are a number of Interrupting
deviees of equal priority. In this mode a device, after
being serviced, receives the lowest priority, so a device
requesting an interrupt will have to walt, in the worst
case until each of 7 other devices are serviced at most
once. For example, if the priority and "In service" status
is:
Before Rotate (IR4 the highest priority requiring service)
IS7
"IS" Status

lSI IS5 1114 IS3 IS2 lSI

Hlghel~rlOrity

Lowelt Priority
Priority Status

After the Initialization sequence, IRO has the highest
priority and IR7 the lowest. Priorities can be changed, as
will be explained, In the rotating priority mode.

ISO

10ltlol101010101

718 1

1

5

14 13 12 1 lfo 1

After Rota.e (lR4 was serviced, all other priorities
rotated correspondingly)

END OF INTERRUPT (EOI)
The In Service (IS) bit can be reset either automatically
following the trailing edge of the last in sequence INTA
pulse (when P.EOI bit in ICW1 is set) or by a command
word that must be Issued to the 8259A before returning
from a service routine (EOI command). An EOI command
must be issued twice if in the Cascade mode, once for the
master and once for the corresponding slave.

IS7 lSI IS5 1114 IS3 182 lSI

ISO

101 1 1010101010101
Highe" Priority
Priority Status

There are two forms of EOI command: Specific and NonSpecific. When the 825!!A is operated In modes which
preserve the fully nested structure, it can determine
which IS bit to reset on EOL When a Non-Specific EOI
command is issued the 8259A will automatically reset
the highest IS bit of those that are set, since In the
fully nested mode the highest IS level was necessarily the
last level acknowledged and serviced. A non-specific EOI
can be issued with OCW2 (EOI = 1, SL = 0, R = 0).

L_e.. Priority

12 1)0 17EGS 4 I 31

There are two ways to accomplish Automatic Rotation
using OCW2, the Rotation on Non-Specific EOI Command
(R = 1, SL = 0, EOI ,;, 1) and the Rotate in Automatic EOI
Mode which is set by (R = 1, SL = 0, EOI = 0) and cleared
by (R = 0, SL = 0, EOI = 0).

SPECIFIC ROTATION
(Specific Priority)

When a mode IS used which may disturb the fully nested
structure, the 8259A may no longer be able to determine
the last level acknowledged. In this case a Specific End of
Interrupt must be issued which includes·as part onhe
command the IS level to be-reset. A specific EOI can be issued with OCW2 (EOI = 1, SL = 1, R = 0, and LO-L2 is the
binary level of the IS bit to be reset).

The programmer can change priorities by programming
the bottom priority and thus fixing all other priorities;
i.e., if IR5 is programmed as the bottom priority device,
then IR6 will have the highest one.

It should be noted that an IS bit that is ma'sked by an
IMR bit will not be cleared by a non-specific EOI if the
8259A is in the Special Mask Mode.

Observe that in this mode internal status is updated by
software control during OCW2. However, it is independent
of the End of Interrupt (EOI) command (also executed by
OCW2). Priority changes can be executed during an EOI
command by using the Rotate on Specific EOI command
in OCW2 (R = 1, SL = 1, EOI = 1 and LO-L2 = IR level to
receive bottom priority).

The Set Priority command is issued in OCW2 where:
R= 1, SL = 1; LO-L2lsthebinary priority level codeofthe
bottom priority device.

AUTOMATIC END OF INTERRUPT (AEOI) MODE
If AEOI = 1 In ICW4, then 'the 8259A will operate in AEOI
mode continuously until reprogrammed by ICW4. In this
mode the 8259A will automatically perform a nonspecific EOI operation at the trailing edge of the last
interrupt acknowledge pulse (third pulse in MCS-80/85,
second in iAPX 86). Note that from a system standpoint,
this mode should be used only when a nested multilevel
interrupt structure is not required within a single 8259A.

INTERRUPT MASKS
Each Interrupt Request Input can be masked Individually by the Interrupt Mask Register (IMR) programmed
through OCW1. Each bit in the IMR masks one interrupt
channel If It is set (1). Bit 0 masks IRO, Bit 1 masks IR1
and so forth. Masking an IR channel does not affect the
other channels operation.

The AEOI !TIode can only be used in a master 8259A and
not a slave.

2-99

8259A18259A-2/8259A-8
SPECIAL MASK MODE

POLL COMMAND

Some applications may require an interrupt service
routine to dynamically alter the system priority structure during its execution under software control. For
example, the routine may wish to inhibit lower priority
requests for a portion of its execution but enable some
of them for another portion.
.

In this mode the INT output is not used or the microprocessor internal Interrupt Enable flip-flop is reset, disabling
its interrupt input. Service to devices is achieved by
software using a Poll command.
The Poll command is issued by setting P= "1" in OCW3.
The 8259A treats the next RD pulse to the 8259A (i.e.,
RD = 0, CS = 0) as an interrupt acknowledge, sets the
appropriate IS bit if there is a request, and reads the·
priority level. Interrupt is frozen from WR to RD.

The difficulty here is that if an Interrupt Request is
acknowledged and an End of Interrupt command did not
reset its IS bit (i.e., while executing service routine),
the 8259A would have inhibited all lower priority
requests with no easy way for the routine to enable
them

a

The word enabled onto the data bus during ~ is:
07

That is where the Special Mask Mode comes in. In the
special Mask Mode, when a mask bit is set in OCW1, it
inhibits further interrupts at that level and enables interrupts from al/ other levels (lower as well as higher) that
are not masked.

I

05

04

03

02

01

00

W2

Wl

wol

WO-W2: Binary code of the highest priority level
requesting service.
I: Equal to a "1" if there is an interrupt.

Thus, any interrupts may be selectively enabled by
loading the mask register.

This mode is useful if there is a routine command common to several levels so that the Ilii1'A sequence is not
needed (saves ROM space). Another application is to
use the poll mode to expand the number of priority
levels to more than 64.

The special Mask Mode is set by OCW3 where:
SSMM=1, SMM=1, and cleared where SSMM=1,
SMM=O.

l TIM BtT

De

I

TO OTHER PAtORTY CELLS

O=EDGE
,:: lEIJEl

EDGE

+___+-_+__

SENSE

~LA~TC~H~+-_ _

SET

de is programmed using bit 3 in ICW1.
If LTIM = '0', an interrupt request will be recognized by a
low to high transition on an IR input. The IR input can remain high without generating another interrupt.
If LTIM = '1', an interrupt request will be recognized by a
'high' level on IR Input, and there is no need for an edge
detection. The interrupt request must be removed before
the EOI command is issued or the CPU interrupt is enabled
to prevent a second interrupt from occurring.
The priority cell diagram shows a conceptual circuit of the
level sensitive and edge sensitive input circuitry of the
8259A. Be sure to note that the request latch is a transpare.nt D type later.
In both the edge and level triggered modes the IR inputs
must remain high until after the falling edge of the first
INTA. If the IR input goes low before this time a DEFAULT
IR7 will occur when the CPU acknowledges the interrupt.
This can be a useful safeguard for detecting interrupts
caused by spurious noise glitches on the IR inputs. To implement this feature the IR7 routine is used for "clean up"
simply executing a return instruction, thus ignoring the
interrupt. If IR7 is needed for other purposes a default IR7
can still be detected by reading the ISR. A normal IR7
interrupt will set the corresponding ISR bit, a default IR7
won't. If a default IR7 routine occurs during a normallR7
routine, however, the ISR will remain set. In this case it is
necessary to keep track of whether or not the IR7 routine
was previously entered. If another IR7 occurs it is a
default.

IR

8086/8088

INT

8080/8085

-----+--'
8086/8088

INTA -----f------~

8080/8085

LATCH"
ARMED

EARLIEST IR
'EDGE TRIGGERED MODe ONLY

CAN BE REMOVED

Figure 10. IR Triggering Timing Requirements
2-101

LArCH"
ARMED

8259A/8259A-2/8259A-8

THE SPECIAL FULLY NESTED MODE

mode, whenever the 8259A's data bus outputs are ena·
bled, the SP/EN output becomes active.

This mode will be used in the case of a ')Ig system
where cascading is used, and the priority has to be con·
served within each slave. In this case the fully nested
mode will be programmed to the master (using ICW4).
This mode is similar to the normal nested mode with the
following exceptions:

This modification forces the use of software program·
ming to determine whether the 8259A is a master or a
slave. Bit 3 in ICW4 programs the buffered mode, and bit
2 in ICW4 determines whether it is a master or a slave.

CASCADE MODE

a. When an interrupt request from a certain slave is in
service this slave is not locked out from the master's
priority logic and further interrupt requests from
higher priority IR's within the slave will be recognized
by the master and will initiate interrupts to the proc·
essor. (In the normal nested mode a slave is masked
out when its request is in service and no higher
requests from the same slave can be s,erviced.)

The 8259A can be easily interconnected in a system of one
master with up to eight slaves to handle up to 64 priority
levels.
.
The master controls the slaves through the 3 line cascade
bus. The cascade bus acts like chip selects to the slaves
during the INTA sequence.
In a cascade configuration, the slave interrupt outputs are
connected to the master interrupt request inputs. When a
slave request line is activated and afterwards acknowledged, the master will enable the corresponding slave to
release the device routine address during bytes 2 and 3 of
INTA. (Byte 2 only for 8086/8088).

b. When exiting the Interrupt Service routine the soft·
ware has to check whether the interrupt serviced was
the only one from that slave. This is done by sending
a non·specific End of Interrupt (EOI) command to the
slave and then reading its In·Service register and
checking for zero. If it is empty, a non·specific EOI
can be sent to the master too. If not, no EOI should be
sent.

The cascade bus lines are normally low and will contain
the slave address code from the trailing edge of the first
INTA pulse to the trailing edge of the third pulse. Each
8259A in the system must follow a separate initialization
sequence and can be programmed to work in a different
mode. An EOI command must be issued twice: once for
the master and once for the corresponding slave. An
address decoder is required to activate the Chip Select
(CS) input of each 8259A.

BUFFERED MODE

When the 8259A is used in a large system where bus
driving buffers are required on the data bus and the cas·
cadlng mode Is used, there exists the problem of enabl·
Ing buffers.
The buffered mode will structure the 8259A to send an
enable signal on SP/EN to enable the buffers. In this

The cascade lines of the Master 8259A are activated only
for slave inputs, non slave inputs leave the cascade line
inactive (low).

\

ADDRESS BuS (16)

\

CONTROL BUS

,

\

\
INT REO

\

\

OAT A BUS (8)

- -

---

-

--r-

-

---

-- -

r- -- -

-

-

-- -

r-

Ao

,,00-7

INT

INTA

'0

CS

CASO

82S9A

CAS 1

SLAVE A

SPIEN7

GrO

5

•

J

2

J

2

I I• I 1• 1 1
1

I

6

5

I
00-7

~lAVE

SPIEN7

6

G!O 11
]

6

IN'

INTA

CASO
8259A

I - I-

iTl

-

-

I

1-'
cs

-

5

4

e
J

2

1

CAS 1

CAS 1
CAS 2

0

•

3

2

1

0

I
INTERRUPT REQUESTS

Figure 11. Cascading the 8259A
2-102

Ao

00·7

INTA

INT

8259A

CAS 2

1 1 1111
5

CS
CASO

MASTER

SPIENM7 M6 M5 M4 M3 M2 Ml MO

lel,l.l 1 I,
••

!!

1
0

I

8259A/8259A·2/8259A·8
ABSOLUTE MAXIMUM RATINGS*

'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.

Ambient Temperature Under Bias .......... O°C to 70°C
Storage Temperature .............. - 65°C to + 150°C
Voltage on Any Pin
with Respect to Ground ............. -0.5V to + 7V
Power Dissipation .......................... 1 Watt

D.C. CHARACTERISTICS
Symbol

[TA

= O"C to

70"C, Vee

Parameter

Vil

input Low Voltage

= 5V ±5% (8259A-8), vee = 5V ±10% (8259A, 8259A-2)l

Min.
-0.5

VIH

Input High Voltage

Val

Output Low Voltage

VOH

Output High Voltage

VOH(lNT)

Interrupt Output High
Voltage

2.0'

Max.

Units

0.8

V

Test Conditions

Vee +0.5V

V

0.45

V

IOl

2.4

V

IOH - -400p,A

3.5

V

IOH

2.4

V

IOH

= 2.2mA
=
=

-100p,A
-400p,A

III

Input Load Current

-10

+10

p,A

OV ,,;;VIN ,,;;Vee

ILOl

Output Leakage Current

-10

p,A

0.45V ,,;;VOUT ,,;;Vee

Icc

Vee Supply Current

+10
85

mA

ILiR

IR Input Load Current

-300

p,A

VIN - 0

10

p,A

VIN

'Note: For Extended Temperature EXPRESS V 1H

CAPACITANCE

(TA

= Vee

= 2.3V.

= 25°C; Vee = GND = OV)

Symbol

Parameter

Max.

Unit

Test Conditions

CIN

Input Capacitance

Min.

Typ.

10

pF

fc = 1 MHZ

Clio

I/O Capacitance

20

pF

Unmeasured pins returned to Vss

A.C. CHARACTERISTICS [TA = O°C to 70°C, Vee = 5V

±5% (8259A-8), Vee

= 5V

± 10% (8259A, 8259A-2)l

TIMING REQUIREMENTS
Symbol

Parameter

8259A-8
Min.

Max.

8259A
Min.

Max.

8259A-2
Min.

Units

TAHRL

AO/CS Setup to RD/INTAI,

50

0

0

ns

TRHAX

AO/CS Hold after RD/INTAt

5

0

0

ns

TRLRH

RD Pulse Width

420

235

160

ns

TAHWL

AO/CS Setup to WR~

50

0

0

ns

TWHAX

AO/CS Hold after WRt

20

0

0

ns

TWLWH

WR Pulse Width

400

290

190

ns

TDVWH

Data Setup to WRt

300

240

160

ns

TWHDX

Data Hold after WRt

40

0

0

ns

TJLJH

Interrupt Request Width (Low)

100

100

100

ns

TCVIAL

Cascade Setup to Second orThird
INTAj, (Slave Only)

55

55

40

ns

TRHRL

End of RD to next RD
End of INTA to next INTA within
an INTA sequence only

160

160

160

ns

TWHWL

End ofWR to nexlWR

190

190

190

ns

2-103

Test Conditions

Max.

See Note 1

8259A/8259A-2/8259A-8

A.C. CHARACTERISTICS (Continued)
Symbol

Min.
'TCHCL

8259A

8259A·8

Parameter
End of Command to next Command
(Not same command type)

Max.

Min.

500

8259A·2

Max.

Min.

500

Units

Test Conditions

Max.

500

ns

End of INTA sequence to next
INTA sequence.
• Worst case timing for TCHCL In an actual microprocessor system IS tYPically much greater than 500 ns (I.e. 8085A = 1.6I's,
8085A·2 = 11's, 8086 = 11's, 8086·2 = 625 ns)
NOTE: This is the low time required to clear the input latch in the edge triggered mode.

TIMING RESPONSES

Min.
TRLDV

8259A

8259A·8

Parameter

Symbol

Max.

Data Valid from RD !lNTAI

8259A·2

Max.

Min.

300

Units

Test Conditions

Max.

Min.

200

120

ns

C of Data Bus=
100 pF
C of Data Bus
Max text C = 100 pF
Min. test C = 15 pF

TRHDZ

Data Float after RD !lNTA T

85

ns

TJHIH

Interrupt Output Delay

400

350

300

ns

TIALCV

Cascade Valid from First INTAI
(Master Only)

565

565

360

ns

CINT = 100 pF
CCASCADE = 100 pF

10

200

10

100

10

TRLEL

Enable Active from RD I or INTAI

160

125

100

ns

TRHEH

Enable Inactive from ROT or INTA T

325

150

150

ns

TAHDV

Data Valid from Stable Address

350

200

200

ns

TCVDV

Cascade Valid to Valid· Data

300

300

200

ns

A.C. TESTING LOAD CIRCUIT

A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT

'.'=X >
2.0

TEST POINTS

0.8

045

A C TESTING

< )C
2.0

DEVICE

'1CL~100PF

UNDER
TEST

0.8

INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR

A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND 0 BV FOR A lOGIC 0

C L = 100 pF
CL INCLUDES JIG CAPACITANCE

WAVEFORMS
WRITE

TWLWH

\
Ci
ADDRESS IUS

)

TAHWL

-

-

TWHAX

~

K
-TDVWH-

.)

DATA IUS

2-104

-TWHDX

r-

8259A/8259A-2/8259A-8

WAVEFORMS (Continued)
READ/INTA
ROONTA------------~

1 - - - - - - TRLRH------i ,'_ _ _ _ _ _ _ __

TRLEL

i
"

TRHAX

TAHRL

C I - - - - -......
ADDRESS BUS
"" _ _ _ _ _ _ _J

-_-~-~~91._

DATA BUS- _ _ _ _ _ _ _ _ _ _ _

______

T_R_HD_Z___'I_

m m

OTHER TIMING
All
fNfA

WR
All

lIITA
Wi!

All

I~A

\
\
\

A=TRHRL~

!F=TWHWL=1\

/
/

c~""~

/

2-105

82S9A/8'2S9A-2/82S9A-8

1

WAVEFORMS (Continued)
INTA SEQUENCE
'R

/'

'NT-------'
'NTA-----------------~

-- -0--

01------- _____ _

_TCVIAL

TCYDY

C02-------------________~----~L4-------L-----L-L--------------~-TIALCV---.--.-

NOTES: Interrupt output must remain HIGH at least 'until leading edge of first INTA.
1. Cycle 1 in iAPX B6, iAPX BB systems, the Data Bus is not active.

2-106

inter
8755A 18755A-2
16,384-8IT EPROM WITH 1/0
• 2048 Words x 8 Bits

• 2 General Purpose 8·Bit 110 Ports

• Single + 5V Power Supply (Vee>

• Each 1,O Port Line Individually
Programmable as Input or Output

• Directly Compatible with 808SA
and 8088 Microprocessors

• Multiplexed Address and Data Bus
• 40·Pin DIP

• U.V. Erasable and Electrically
Reprogrammable

• Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range

• Internal Address Latch

The Intel@ 8755A is an erasable and electrically reprogrammable ROM (EPROM) and 1/0 chip to be used in the 8085AH and
iAPX 88 microprocessor systems. The EPROM portion is organized as 2048 words by 8 bits It has a maximum access time of
450 ns to permit use with no wait states in an 8085AH CPU.
The 1/0 portion consists of 2 general purpose 1/0 ports. Each 1/0 port has 8 port lines, and each 1/0 port line is individually
•
programmable as input or output.
The 8755A-2 IS a high speed selected version of the 8755A compatible with the 5 MHz 8085AH-2 and the 5 MHz iAPX 88
microprocessor.

ClK----'
ClK

PB,
PBs

READV----I

PB.
PBa
PB,

Aa--10 _ _- V
CE,----ooj
IOiM---.J

2K)( 8
EPROM

AlE---.J
Ril---.J
IOW---.J

G
G

....

PB,

PAo-7
~-~/

PB,
lOW

PA-,

ALE

PA,
PA,

AD,

PA.

AD,

RESET---.J

ADa

PAi

iOR---+I

AD.

PA,

AD,

PA,

PROG/CE,
V DD - - - ' - - - '

AlO

Vee (+5V)

AD,

' - - - - Vss (OVI

Vss

Figure 2. Pin Configuration

Figure 1. Block Diagram

Intel Corporabon Assumes No Responslbllty for the Use of Any Circuitry Other Than Circuitry Embodied In an Intel Product No Other Circuit Patent Licenses are Implied
© INTEL CORPORATION. 1980

2-107

8755A/8755A-2

Table 1. Pin Description"
Type

Name and Function

Symbol

lYpe

ALE

Symbol

I

Address latch Enable: When Address
latch Enable goes high, ADO-7, 10/M,
As-Hi, CE2, and CE, enter t~ address
latches. The signals (AD, 10/M ADs-,o,
CE2, eEl) are latched in at the trailing
edge of ALE.

READY

0

Ready is a 3·state output controlled by
CE" CE2, ALE and ClK. READY is forc·
ed low when the Chip Enables are active
during the time ALE is high, and reo
mains low until the rising edge of the
next ClK. (See Figure 6c.)

ADo-7

I

Bidirectional Address/Data Bus: The
lower 8-bits of the PROM or I/O address
are applied to the bus lines when ALE is
high.

PAO-7

I/O

Port A: These are general purpose I/O
pins. Their input/output direction is determined by the contents of Data Direction Register (DDR). Port A is selected for
write operations when the Chip Enables
are active and lOW is low and a 0 was
previously latched from ADo, AD,.

During an 110 cycle, Port A or B is
selected based on the latched value of
ADo. IF RD or lOR is low when the latched
Chip Enables are active, th}e output buffers present data on the bus.
As-,o

I

Address Bus: These are the high order
bits of the PROM address. They do not
affect 110 operations.

PROG/CE,
CE2

I

Chip Enable Inputs: CE, is active low
and CE2 is active high. The 8755A can be
accessed only when both Chip Enables
are active at the time the ALE signal
latches them up. If either Chip Enable
input is nof active, the ADo-7 and
READY outputs will be in a high impedance state.CE, is also used as a programming pin. (See section on
programming.)

IO/M

I

110 Memory: If the latched 10/M IS high
when RD is low, the output data comes
from an I/O port. If it is low the oulput
data comes from the PROM.

RD

I

Read: If the latched Chip Enables are
active when RD goes low, the ADo-7
output buffers are enabled and output
either the selected PROM location or I/O
port. When both RD and lOR are high,
the ADo-7 output buffers are 3-stated.

lOW

I

I/O Write: If the latched Chip Enables are
active, a Iowan lOW causes the output
port pointed to by the latched value of
ADo to be writte'!..wlth the data on ADo-7.
The state of 10/M is ignored.

ClK

I

Clock: The ClK is used to force the
READY into its high impedan~state
after it has been forced low by GE, low,
CE2 high, and ALE high.

Name and Function

Read Operation is selected by either lOR
low and active C~ Enables and ADo
and AD, low, or 10/M high, RD low, active
Chip Enables, and ADo and AD, low.
PBO-7

I/O

Port B: This general purpose I/O port is
identical to Port A except that It is
selected by a 1 latched from ADo and a'O
from AD,.

RESET

I

Reset: In normal operation, an input
high on RESET causes all pins In Ports A
and B to assume input mode (clear DDR
register).

lOR

I

I/O Read: When the Chip Enables are
active, a Iowan lOR will output the
selected I/O port onto the AD bus. TOfi
low performs the s~me functio~s the
combination of 10/M high and RD low.
When lOR is not used in a system, lOR
should be tied to Vee ("1").

Vee

Power: +5 volt supply.

Vss

Ground: Reference.

Voo

Power Supply: Voo is a programming
voltage, and must be tied to Vee when
the 8755A is being read.
For programming, a high voltage is
supplied with Voo = 25V, typical. (See
section on programming.)

2-108

8755A/8755A-2
FUNCTIONAL DESCRIPTION

8755A

ONE BIT OF PORT A AND ODR A

PROM Section
The 8755A contains an 8-bit address latch which allows it
to interface directly to MCS-48, MCS-85 and iAPX 88/10
Microcomputers without additional hardware.
The PROM section of the chip is addressed by the 11-bit
address and the Chip Enables. The address, CE 1 and
CE2 are latched into the address latches on the falling
edge of ALE. If the latched Chip Enables are active and
10iM is low when RD goes low, the contents of the
PROM location addressed by the latched address are
put out on the ADO_7lines (provided that Voo is tied to
Vee·)

The I/O section of the chip is addressed by the latched
value of ADo-1. Two 8-blt Data Direction Registers (DDR)
In 8755A determine the input/output status of each pin
in the corresponding ports. A "0" In a particular bit positIOn of a DDR signifies that the corresponding I/O port bit
is In the Input mode A "1" In a particular bit position signifies that the corresponding I/O port bit is In the output
mode. I n this manner the I/O ports of the 8755A are bit-bybit programmable as Inputs or outputs. The table
summarizes port and DDR designation. DDR's cannot be
read.
ADo

0
0
1
1

0
1
0
1

~

READ PA
WRITE PA ~ liOW;O)e (CHIP ENABLES ACTIVE). (PORT A ADDRESS SelECTED)

1/0 Section

AD1

Do

Selection
Port
Port
Port
Port

A
B
A Data Direction Register (DDR A)
B Data Direction Register (DDR B)

WRITE CDR A ~ liOW:O). (CHIP ENABLES ACTIVE). (OOR A AODRESS SELECTEO)
REAO PA = {[(IOIM"l). (RD=on+ (jijR"'Dl}. (CHIP ENABLES ACTIVE). (PORT AADDRfSSSELECTED)
NOTE WRITE PA IS NOT nUALIFIED BY 101M

Note that hardware RESET or writing a zero to the DDR
latch will cause the output latch's output buffer to be
disabled, preventing the data in the Output Latch from
being passed through to the pin. This is equivalent to
putting the port In the Input mode. Note also that the data
can be written to the Output Latch even though the Output
Buffer has been disabled. This enables a port to be initialized with a value pnor to enabling the output.
The diagram also shows that the contents of PORT A and
PORT B can be read even when the ports are configured
as outputs.
TABLE 1. 8755A PROGRAMMING MODULE CROSS
REFERENCE

When lOW goes low and the Chip Enables are active,
the data on the ADo_7 is written into 1/0 port selected
by the latched value of AD o_ 1. During this operation all
1/0 bits of the selected port are affected, regardless of
their 1/0 mode and the state of 101M. The actual output
level does not change until lOW returns high. (glitch free
output)

MODULE NAME

USE WITH

UPP 955
UPP UP2(2)
PROMP'F 975
PROMPT 475

UPP(4)
UPP 855
PROMPT 80/85(3)
PROMPT 48(1)

NOTES:
1. Described on p. 13-34 of 1978 Data catalog.
2. Special adaptor socket.
3 Described on p. 13-39 of 1978 Data Catalog.
4.. Described on p. 13-71 of 1978 Data catalog.

'A port can be read out when the latched Chip Enables are
active and either RD goes low with 10iiVi high, or lOR goes
low Both input and output mode bits of a selected port
will appear on lines ADo-7.
To clanfy the function of the I/O Ports and Data Direction
Registers, the following diagram shows the configuration
of one bit of PORT A and DDR A The same logic applies
to PORT Band DDR B.

2-109

inter

8755A/8755A-2

ERASURE CHARACTERISTICS
The erasure characteristics of the 8755A are such that
erasure begins to occur when exposed to light with
wavelengths shorter t/;lan approximately 4000 Angstroms
(}\). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000-4000A
range. Data show that constant exposure to room level
fluorescent lighting could erase the typical 8755A in
approximately 3 years while itwould take approximately 1
week to cause erasure when exposed to direct sunlight.
If the 8755A is to be exposed to these types bf lighting
conditions for extended periods of time, opaque labels
are available from Intel which should be placed over the
8755 window to prevent unintentional erasure.
The recommended erasure procedure for the 8755A is
exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e.,
UV intensity X exposure time) for erasure should be a
minimum of 15W-sec/cm2. The erasure time with this
dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000"W/cm 2 power rating. The
8755A should be placed within one inch fro.m the lamp
tubes during erasure. Some lamps have a filter on their
tubes and this filter should be removed before erasure.

SYSTEM APPLICATIONS
System Interface with 8085AH and iAPX 88
A system using the 8755A can use either one of the two I/O
Interface techniques:
• Standard I/O
• Memory Mapped I/O
If a standard 1/0 technique is used, the system can use
the feature of both CE2 and CE 1. By using a combination of unused address lines A 11 - 15 and the Chip
Enable inputs, the 8085AH system can use up to 5 each
8755A's without requiring a CE decoder. See Figure4a and 4b.
If a memory mapped 1/0 approach is used the 8755A will
be selected by....!he combination of both the Chip
Enables and 101M using ADs_ 15 address lines. See
Figure 3.

...---

K
A

PROGRAMMING

~

)

As-. s

'\J

Initially, and after each erasure, all bits of the EPROM
portions of the 8755A are in tlie "1" state. Information is
introduced by selectively programming "0" into the
desired bit locations. A programmed "0" can only be
changed to a "1" by UV erasure.

8085AH

kl

)

Do7

'\J

ALE
~

RD

~

WR

The 8755A can be programmed on the Intel® Universal
PROM Programmer (UPP), and the PROMPT'" 80/85 and
PROMPT-48'" design aids. Theappropriate programming
modules and adapters for use in programming both
8755A's and 8755's are shown in Table 1.

,--

elK 1$2)

!--

READY

. !---

101M

vl''

-

The program mode itself consists of programming a
single address at a time, giving a single 50 msec pulse
for every address. Generally, it is desirable to have a
verify cycle after a program cycle for the same address
as shown in the attached timing diagram. In the verify
cycle (i.e., normal memory read cycle) 'VDD' should
be at +5V.

I

7

A/ DO_7

iOR

I

AS_10

RD
ALE

eLK

iiiW

101M

READY

8755A

Preliminary timing diagrams and parameter values pertaining to the 8755A programming operation are contained in Figure 7.

Figure 3.

2-110

8755A in 8085AH System
(Memory-Mapped 1/0)

CE

8755A/8755A-2
iAPX 88 FIVE CHIP SYSTEM
Figure 4 shows a five chip system containing:
• 1.2SK Bytes RAM
• 2K Bytes EPROM
.381/0 Pins
• 1 Interval Timer
• 2 Interrupt Levels

Vss

I--r-r-r-+~----ICE

Vee

I I

po~~

>-t-- - - - - iNA
Ril

PORT
8155-2 B

ALE
/'-..... _-'---'---'--'-_ _-"\ OAT AI
ADDR

~IV-:Y
(8)

PORT~
C

(6)

IN_
101M TIMER
_ _ _ RESET OUT

t- - - -

lOW

R_-_V
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GND
MANUAL

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®

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RST

I-

RES

Ril

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Figure 4a. iAPX 88 Five Chip System Configuration

2-111

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>-

8755A/8755A·2
WAVEF:ORMS (Continued)
I/O PORT
A. INPUT MODE

~OR

~"' ----,.~
INPUT

~~

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__________

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~

DATA' BUS

-

-

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-------

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B. OUTPUT MODE

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{
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------------

WAIT STATE (READY = 0)

2-116

_

""--------

intJ

8755A18755A·2

WAVEFORMS (Continued)
8755A PROGRAM MODE
FUNCTION

1....1-------- PROGRAM CYCLE

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...

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DATA TO BE

AlDa.7

PROGRAMMED

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+5 ................................................

\J-*VERIFY CYCLE loS A REGUL~R MEMORY READ CYCLE !WITH VOO = +5V FOR 8755A)

2-117

PROGRAM CYCLE

APPLICATION
NOTE

Ap·59

September 1979

© Intel Corporation, 1979

2-118

121500-001

AP59
INTRODUCTION

The Intel 8259A is a Programmable Interrupt Controller
(PIC) designed for use in real-time interrupt driven
microcomputer systems. The 8259A manages eight
levels of interrupts and has built-in features for expansion up to 64 levels with additional 8259A's. Its versatile
design allows it to be used within MCS-80, MCS-85,
MCS-86, and MCS-88 microcomputer systems. Being
fully programmable, the 8259A provides a wide variety of
modes and commands to tailor 8259A interrupt processing for the specific needs of the user. These modes and
commands control a number of interrupt oriented functions such as interrupt priority selection and masking of
interrupts. The 8259A programming may be dynamically
, changed by the software at any time, thus allowing complete interrupt control throughout program execution.
The 8259A is an enhanced, fully compatible revision of
its predecessor, the 8259. This means the 8259A can use
all hardware and software originally designed for the
8259 without any changes. Furthermore, it provides additional modes that increase its flexibility in MCS-80
and MCS-85 systems and allow it to work in MCS-86 and
MCS-88 systems. These modes are:
•
•
•
•
•

MCS-86/88 Mode •
Automatic End of Interrupt Mode
Level Triggered Mode
Special Fully Nested Mode
Buffered Mode

Each of these are covered in depth further in this application note.
This application note was written to explain completely
how to use the 8259A within MCS-80, MCS-85, MCS-86,
and MCS-88 microcomputer systems. It is divided into
five sections. The first section, "Concepts", explains
the concepts of interrupts and presents an overview of
how the 8259A works with each microcomputer system
mentioned above. The second section, "Functional
Block Diagram", describes the internal functions of the
8259A In block diagram form and provides a detailed
functional description of each device pin. "Operation of
the 8259A", the third section, explains in depth the
operation and use of each of the 8259A modes and commands. For clarity of explanation, this section doesn't
make reference to the actual programming of the 8259A.
Instead, all programming is covered in the fourth section, "Programming the 8259A". This section explains
how to program the 8259A with the modes and commands mentioned in the previous section. These two
sections are referenced in Appendix A. The fifth and
final section "Application Examples", shows the 8259A
in three typical applications. These applications are
fully explained with reference to both hardware and software.
The reader should note that some of the terminology
used throughout this application note may differ
slightly from existing data sheets. This is done to better
clarify and explain the operation and programming of
the 8259A.

1. CONCEPTS
In microcomputer systems there is usually a need for
the processor to communicate with various Input/Out-

put (1/0) devices such as keyboards, displays, sensors,
and other peripherals. From the system viewpOint, the
processor should spend as little time as possible servicing the peripherals since the time required for these 110
chores directly affects the amount of time available for
other tasks. In other words, the system should be
designed so that 1/0 servicing has little or no effect on
the total system throughput. There are two basic
methods of handling the 1/0 chores in a system: status
polling and interrupt servicing.
The status poll method of 1/0 servicing essentially involves having the processor "ask" each peripheral if it
needs servicing by testing the peripheral's status line. If
the peripheral requires service, the processor branches
to the appropriate service routine; if not, the processor
continues with the main program. Clearly, there are
several problems in implementing such an approach.
First, how often a peripheral is polled is an important
constraint. Some idea of the "frequency-of-service"
required by each peripheral must be known and any software written for the system must accommodate this
time dependence by "scheduling" when a device is
polled. Second, there will obviously be times when a
device is polled that is not ready for service, wasting the
processor time that it took to do the poll. And other
times, a ready device would have to wait until the processor "makes its rounds" before it could be serviced,
slowing down the peripheral.
Other problems arise when certain peripherals are more
important than others. The only way to implement the
"priority" of devices is to poli the high priority devices
more frequently than lower priority ones. It may even be
necessary to poll the high priority devices while in a low
priority device service routine. It is easy to see that the
polled approach can be inefficient both time-wise and
software-wise. Overall, the polled method of 1/0 servicing can have a detrimental effect on system throughput,
thus limiting the tasks that can be performed by the
processor.
A more desirable approach in most systems would allow
the processor to be executing its main program and only
stop to service the 1/0 when told to do so by the 1/0
itself. This is called the interrupt service method. In
effe}:t, the device would asynchronously signal the processor when it required service. The processor would
finish its current instruction and then vector to the
service routine for the device requesting service. Once
the service routine is complete, the processor would
resume exactly where it left off. Using the interrupt service method, no processor time is spent testing devices,
scheduling is not needed, and priority schemes are
readily implemented. It is easy to see that, using the interrupt service approach, system throughput would increase, allowing more tasks to be handled by the
processor.
However, to implement the interrupt service method
between processor and peripherals, additional hardware
is usually required. This is because, after interrupting
the processor, the device must supply information for
vectoring program execution. Depending on the processor used, this can be accomplished by the device taking control of the data bus and "jamming" an instruction(s) onto it. The instruction(s) then vectors the pro2-119

121500-001

AP59
gram to the proper service routine. Tl)is of course reo
quires additional control logic for each interrupt reo
questing device. Yet the implementation so far is only in
the most basic form. What if certain peripherals are to
be of higher priority than others? What if certain inter·
rupts must be disabled while others are to be enabled?
The possible variations go on, but they all add up to one
theme; to provide greater flexibility using the interrupt
service method, hardware requirements increase.
So, we're caught in the middle. The status poll method
. is a less desirable way of servicing 1/0 in terms of
throughput, but its hardware requirements are minimal.
On the other hand, the interrupt 'service method is most
desirable in terms ,of flexibility and throughput, but
additional hardware is required.
The perfect situation would be to have the flexibility and
throughput of the interrupt method in an implementation with minimal hardware requirements. The B259A
Programmable Interrupt Controller (PIC) makes this all
possible.
The B259A Programmable Interrupt Controller (PIC) was
designed to function as an overall manager of an inter·
rupt driven system. No additional hardware is required.
The B259A alone can handle eight prioritized interrupt
levels, controlling the complete interface between peripherals and processor. Additional B259A's can be
"cascaded" to increase the number of interrupt levels
processed. A wide variety of modes and commands for
programming the B259A give ft enough flexibility for
almost any interrupt controlled structure. Thus, the
B259A is the feasible answer to handling 1/0 servicing in
microcomputer sY,stems.
Now, before explaining exactly how to use the B259A,
let's go over interrupt structures of the MCS·BO, MCScB5,
MCS-B6, and MCS·BB systems, and how they interact
with the B259A. Figure 1 shows a block diagram of the
B259A interfacing with a standard sy~tem bus. This may
prove useful as reference throughout the rest of the
"Concepts" section.

I
INTERRUPT
REQUESTS

Figure 1. 8259A Interlace 10 Standard Syslem Bus

1.1 MCS·80

-8259A OVERVIEW

In an MCS-BO-B:;!59A interrupt configuration, as in
Figure 2, a device may cause an interrupt by pulling one
of the B259A's interrupt request pins (IRO-IR7) high. If
the B259A accepts the interrupt request (this depends
on its programmed condition), the B259A's INT (inter·
rupt) pin will go high, driving the BOBOA's INT pin high.
The BOBOA, can receive an interrupt request any time,
since its INT input is asynchronous. The BOBOA, however, doesn't always have to acknowledge an interrupt
request immediately. It can accept or disregard requests under software control using the EI (Enable Interrupt) or 01 (Disable Interrupt) instructions. These in·
structions either set or reset an internal interrupt enable
flip·flop. The output of this flip-flop c,ontrols the state of
the INTE (Interrupt Enabled) pin. Upon reset, the BOBOA
interrupts are disabled, making INTE low.
At the end of each instruction cycle, the BOBOA examines the state of its INT pin. If an interrupt request is
present and interrupts are enabled, the BOBOA enters an
interrupt machine cycle. During the interrupt machine
cycle the BOBOA resets the internal interrupt enable flipflop, disabling further interrupts until an EI instruction
is executed. Unlike normal machine cycles, the interrupt
machine cycle doesn't increment the program counter.
This ensures that the B080A can return to the pre·
interrupt program location after the interrupt is completed. The 8080A then issues an INTA (Interrupt
Acknowledge) pulse via the 8228 System Controller ,Bus
Driver. This INTA pulse ~ignals the 8259A that the 8080A
is honoring the request and is ready to process the inter·
rupt.
The B259A can now vector program execution to the cor·
responding service routine. This is done during a se·
quence of the three INTA pulses from the 80BOA via the
822B. Upon receiving the first INTA pulse the 8259A
places the opcode for a CALL instruction on the data
bus. This causes the contents of the program counter to
be pushed onto the stack. In addition, the CALL instruction caus'es two more INTA pulses to be issued, allow·
ing the 8259A to place onto the data bus the starting
address of the corresponding service routine. This
address is called the interrupt·vector address. The lower
B bits (LSB) of the interrupt-vector address are released
during the second INTA pulse and the upper B bits
(MSB) during the third INTA pulse. Once this sequence
is comllieted, program execution then vectors to the
service routine at the interrupt·vector address.
If the same registers are used by both the main program
and the interrupt service routine, their contents should
be saved when entering the service routine. This includes the Program Status Word (PSW) which consists
of the accumulator and flags. The best way to do this is
to "PUSH" each register used onto the stack. The ser·
vice routine can then "POP" each register off the stack
in the reverse order when it is completed. This prevents
any ambiguous operation when returning to the main
\
program.
Once the service routine is completed, the main
program may be re·entered by using a normal RET
(Return) instruction. This will "POP" the original con·

2-120

121500-001

AP59
tents of the program counter back off the stack to
resume program execution where it ,left off. Note, that
because interrupts are disabled during the interrupt
acknowledge sequence, the EI instruction must be
executed either during the service routine or the main
program before further interrupts can be processed.

uration. When an interrupt occurs, a sequence of three
INTA pulses causes the 8259A to release onto the data
bus a CALL instruction and an interrupt-vector address
for the corresponding service routine. Other events that
occur during the 8080A interrupt machine cycle, such as
disabling interrupts and not incrementing the program
counter, also occur in the 8085A interrupt acknowledge
machine cycle. Additionally, the instructions for saving
registers, enabling or disabling of interrupts, and returning from service routines are literally the same.

For additional information on the 8080A interrupt structure and operation, refer to the MCS-80 User's Manual.

1-2 MCS-85' :-8259A OVERVIEW

The 8085A, however, has a different interrupt hardware
scheme as shown in Figure 3. For one, the 8085A supplies Its own INTA output pin rather than using an addi-

An MCS-85-8259A configuration processes interrupts
in much the same format as an MCS-80-8259A con fig-

INTE

A O- 1S

___ HOLD

~

t------·

_ _ _ _ _ _ _ _2AD::.:D"R:=E:::ss"'e"'~:o:r----------V TO MEMORY AND 110

INTI-----------

• 5V
a2S9A

8080A

8,
e,

WI!

WR

91

'K

C ~ECT
CS

TallO

IRO-

e,
INTERRUPT

8224

READY

READY

RESET

RESET

SYNC

SYNC

REQUEST
INPUTS

Figure 2. MCS·80 8259A Basic Configuration Example

TO MULTIPLEXED
Mesas FAMilY

-

-

rD~ t t

Xl

X2 RESET elK
OUT
A8·15

RESET IN

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AO

Al

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8205

00 01 02 03 04 Os 06

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RST 6.5

RST 55

T

ADDRESS BUS

110 SELECT

To STANDARD MEMORY
A NO OTHER 110

MULTIPLEXED ADDRESS/DATA BUS

I

laiM
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Os

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8259A

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WR
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INT CASO_2

I
Flgur. 3. MC5-85

IRO_

IR1
102
103
104
IR5
106
107

-

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,.-1

-

'--i

-

INTERRUPT
REQUEST
INPUTS

'--I
T o SLAVE 8259A

8259A Basic Configuration Example

2-121

121500-001

AP59
tional chip, as the 8080A uses the 8228 System Controller Bus Driver. Another hardware difference is the
8085A has five hardware interrupt pins: INTR, RST 7.5,
RST 6.5, RST 5.5, and TRAP. The INTR (Interrupt Request)
pin Is the equivalent to the 8080A's INT pin. The RST
(Restart) pins and TRAP pin are all restart Interr-upts
which vector program execution to an individual dedicated address when asserted. The important factor
associating these interrupts is their relative priority, as
shown below:
Highest Priority,
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
Lowest Priority

tions. That is, a device can cause an Interrupt by pulling
'on.e of the 8259A's interrupt request pins (I RO-IR7) high.
If the 8259A honors the request, its INT pin will go high,
driving the 808818088's INTR pin high. Like the 8080A
and 8085A, the INTR pin of the 8086/8088 Is asynchronous, thus it can receive an interrupt any time. The
8086/8088 can also accept or disregard requests on
INTR unde(software control using the STI (Set Interrupt)
or CLI (Clear Interrupt) instructions. These instructions
set or clear the interrupf-enabled flag IF. Upon
8086/8088 reset the IF flag is cleared, disabling external
interrupts on INTR. Beside the I!',ITR pin, the 8086/8088
provides an NMI (Non-Maskable Interrupt) pin. The NMI
functions similar to the 8085A's TRAP; it can't be disabled or masked. NMI has higher priority than INTR.
Figure 4 shows an MCS-86 MAX Mode system interfacing with an 8259A on the local bus. This MCS-86-8259A
configuratibn is also representative of an MCS-888259A configuration except for the data bus which is 16
bits for 8086 and 8 bits for 8088 .. In the MCS-86 system.
the 8259A must be on the lower 8 bits of the data bus.
Note that the 8259A could also be interfaced on the
system bus.

The INTR pin has lowest priority among the other 8085A
hardware Interrupts. Thus, precautions to prevent interrupting 8259A service routines may be necessary. This,
of course, depends on how the 8085A Interrupts are
being used in a particular application. Such precautions
can be implemented, however, by masking the RST pins
using the SIM instruction. The TRAP pin on the other
hand Is non-maskable; all interrupt pins but TRAP can
be controlled by the EI (Enable Interrupt) and 01 (Disable
Interrupt) instructions.,

Although there are some basic similarities, the actual
processing of interrupts with an 8086/8088 Is different
than an 8080A or 8085A. When an Interrupt request is
present and interrupts are enabled, the 8086/8088 enters
its Interrupt acknowledge machine cycle. The interrupt
aqknowledge machine cycle pushes the flag registers
onto the stack (as in a PUSHF instruction). It then clears
the IF flag which disables interrupts. The contents of

For a complete description of the 8085A interrupt structure, refer to the MCS-85 User's Manual.

1.3 MCS-88188

-8259A OVERVIEW
Operation of an MCS-86/88-8259A configuration has
basic similarities of the MCS-80/85-8259A conflgura-

r.S;;;YS~T;;EM::-A~D=DR;;;ES;;;:S;-;.;:'U::-S-;'."'1IIII!mi.... l~:~~ORY
A1

MULTIPLEXED ADDRESSIDATA BUS

!

_..J....

I/'----'-.=Y=ST"'EM"""'DA"'TA"'.=U"'.

v--'--"'-'===""--,/

TO MEMORY

AND 110

8259A SELECT

NMI
INTH

---v
Figure 4. MSC-88,

TO SLAVE 825BA

a25IA a ..le Conllgurellon Example (8088 In Max. Mode)

2-122

121500-001

AP59
both the code segment and the instruction pointer are
then also pushed onto the stack. Thus, the stack retains
the pre·interrupt flag status and pre·interrupt program
location which are used to return from the service
routine. The 8086/8088 then issues the first of two INTA
pulses which signal the 8259A that the 8086/8088 has
honored its interrupt request. If the 8086/8088 is used in
its "MIN Mode" the INTA signal is available from the
8086/8088 on its INTA pin. If the 8086/8088 is used in the
"MAX Mode" the INTA signal is available via the 8288
Bus Controller INTA pin. Additionally, in the "MAX
Mode" the 8086/8088 LOCK pin goes low during the interrupt acknowledge sequence. The LOCK signal can be
used to indicate to other system bus masters not to gain
control of the system bus during the interrupt acknowl·
edge sequence. A "HOLD" request won't be honored
while LOCK is low.
The 8259A is now ready to vector program execution to
the corresponding service routine. This is done during
the sequence of the two INTA pulses issued by the 80861
8088. Unlike operation with the 8080A or 8085A, the
8259A doesn't place a CALL instruction and the starting
address of the service routine on the data bus. Instead,
the first INTA pulse is used only to signal the 8259A of
the honored request. The second INTA pulse causes the
8259A to place a single interrupt,vector byte onto the
data bus. Not used as a direct address, this interrupt·
vector byte pertains to one of 256 interrupt "types" sup·
ported by the 8086/8088 memory. Program execution is
vectored to the corresponding service routine by the
contents of a specifie<;l interrupt type.
All 256 interrupt types are located in absolute memory
locations 0 through 3FFH which make up the 80861
8088's interrupt-vector table. Each type in the interrupt·
, vector table requires 4 bytes of memory and stores a
code segment address and an instruction pOinter ad·
dress. Figure 5 shows a block diagram of the interrupt·
vector table. Locations 0 through 3FFH should be
reserved for the interrupt·vector table alone. Further·
more, memory locations 00 through 7FH (types 0-31) are
reserved for use by Intel Corporation for Intel hardware
and software products. To maintain compatibility with
present and future Intel products, these locations
should not be used.

3FFH
INTERRUPT TY~E 255

3FCH
3FBH

INTERRUPT TYPE 254

·•
·

3F8H

BH

INTERRUPT TYPE 2

8H
7H
INTERRUPT TYPE 1

4H
3H
INTERRUPTTYPE 0

OH

Figure 5. 8085/8088 Interrupt Vector Table

When the 8086/8088 receives an interrupt-vector byte
from the 8259A, it multiplies its value by four to acquire
the address of the interrupt type. For example, if the
interrupt·vector byte specifies type 128 (80H), the vec·
tored address in 8086/8088 memory is 4 x 80H, which
equals 200H. Program execution is then vectored to the
service routine whose address is specified by the code
segment and instruction pointer values within type 128
located at 200H. To show how this is done, let's assume
interrupt type 128 is to vector data to 8086/8088 memory
location 2FF5FH. Figure 6 shows two possible ways to
set values of the code segment and instruction pOinter
for vectoring to location 2FF5FH. Address generation
by the code segment and instruction pointer is ac·
complished by an offset (they overlap). Of the total
20·bit address capability, the code segment can desig·
nate the upper 16 bits, the instruction pOinter can
designate the lower 16 bits.

CS(MSB)

2FH
FOH
DOH
5FH

CS(LSB)
IP(MSB)
IP(LSB)

-

:: I

1
1
1 FOH
1 FCH

TYPE 128

-

1~~~

CS(MSB)
CS(LSB)

20H
DOH

1

IP(MSB)
IP(LSB)

FFH
5FH

1 FOH
1FCH

I

TYPE 128

~

Figure 6. Two Examples of 8086/8088 Interrupt Type 128 Vectoring
to Location 2FF5FH

When entering an interrupt service routine, those regis·
ters that are mutually used between the "main program
and service routine should be saved. The best way to do
this is to "PUSH" each register used onto the stack immediately. The service routine can then "POP" each
register off the stack in the same order when it is completed.
Once the service routine is completed the main program
may be re-entered by using a IRET (Interrupt Return) instruction. The IRET instruction will pop the pre-interrupt
instruction pOinter, code segment and flags off the
stack. Thus the main program will resume where it was
interrupted with the same flag status regardless of
changes in the service routine. Note especially that this
includes the state of the IF flag, thus interrupts are reenabled automatically when returning from the service
routine.
Beside external interrupt generation from the INTR pin,
the 8086/8088 is also able to invoke interrupts by soft- .
ware. Three interrupt instructions are provided: INT, INT
(Type 3), and INTO. INT is a two byte instruction, the second byte selects the interrupt type. INT (Type 3) is a one
byte instruction which selects interrupt Type 3. INTO is
a conditional one byte interrupt instruction which
selects interrupt Type 4 if the OF flag (trap on overflow)
is set. All the software interrupts vector program execution as the hardware interrupts do.
2-123

121500-001

AP59
For further information on 8086/8088 interrupt operation
and internal interrupt structure refer to the MCS-86
User's Manual and the 8086 System Design application
note.
2_ 8259A FUNCTIONAL BLOCK DIAGRAM

A block diagram of the 8259A is shown in Figure 7. As
can be seen from this figure, the 8259A consists of eight
major blocks: the Interrupt Request Register (IRR), the
In-Service Register (lSR), the Interrupt Mask Register
(IMR), the Priority Resolver (PR), the cascade buffer/
comparator, the data bus buffer, and logic blocks for
control and read/write. We'll first go over the blocks
directly related to interrupt handling, the IRR, ISR, IMR,
PR, and the control logic. The remaining functional
blocks are then discussed.
2_1 INTERRUPT REGISTERS AND CONTROL LOGIC'

Basically, interrupt requests are handled by three "cascaded" registers: the Interrupt Request Register (IRR) is
use to store all the interrupt levels requesting service;
the In-Service Register (ISR) stores all the levels which
are being serviced; and the Interrupt Mask Register
(IMR) stores the bits of the interrupt lines to be masked.
The Priority Resolver (PR) looks at the IRR, ISR and IMR,
and determines whether an INT should be issued by the
the control logic to the processor.
Figure 8 shows conceptually how the Interrupt Request
(IR) input handles an interrupt request and how the
various interrupt registers interact. The figure repre-

sents one of eight "daisy-chained" priority cells, one for
each IR input.
The best way to explain the operation of the priority cell
is to go through the sequence of internal events that
happen when an interrupt request occurs. However,
first, notice that the input circuitry of the priority cell
allows for both level sensitive and edge sensitive IR inputs. Deciding which method to use is dependent on the
particular application and will be discussed in more
detail later.
When the IR input is in an inactive state (LOW), the edge
sense latch is set. If edge sensitive triggering is
selected, the "Q" output of the edge sense latch will
arm the input gate to the request latch. This input gate
will be disarmed after the IR input goes active (HIGH)
and the interrupt request has been acknowledged. This
disables the input from generating any further interrupts until it has returned low to re-arm the edge sense
latch. If level sensitive triggering is selected, the "Q"
output of the edge sense latch is rendered useless. This
means the level of the IR input is in complete control of
interrupt generation; the input won't be disarmed once
acknowledged.
When an interrupt occurs on the IR input, it propagates
through the request latch and to the PR (assuming the
input isn't masked). The PR looks at the incoming requests and the currently in-service interrupts to ascertain whether an interrupt should be issued to the processor. Let's assume that the request is the only one incoming and no requests are presently in service. The PR
then causes the control logic to pull the INT line to the
processor high.

PIN CONFIGURATION

cs

.

BLOCK DIAGRAM

Vee

WR
AD

II"

0,

IR7

D.

IR6

Os

'R5

D4

IR4

03

'R3

D,

'R2

D,

'AI

INTA

DATA
BUS
BUFFER

CONTROL lOGIC

Do

'AO

CASO

'NT

CAS 1

SP/EN

lA'

GND

CAS2

IR3

IRO

RD

IR'

IR4

ro;=o;;--

PIN NAMES

es

DATA BUS (B'·DIRECTIONALI

-~~--'

~--'-READ INPUT~~-'-'---'-'­

WII--- -wRiTEINi>UT~------'-1\0

COMMAND SELECT ADDRESS

CS
CAS1-CASO

CHIP SELECT
CASCADE LINES

--

SPfEN

SLAVE PROGRAMJENABLEBUFFER

INT

INTA

INTERRUPT OUTPUT
INTERRUPT ACKNOWLEDGE INPUT

IRO-IR7

INTERRUPT REOUEST INPUTS

~

INTERNAL BUS

Figure 7. 8259A Block Diagram and Pin Configuration

2-124

121500-001

AP59
LTiM BIT

TO OTHER PRIORITY CELLS

0= EDGE
1 LEVEL

CLRISR

=

CLR Q

ISA BIT

SET

~~--+-----+----l--l---<~t=ll-;;;~~;j

SET ISA

PRIORITY
RESOLVER

CONTROL

lOGIC

IR

MesaD/as
MODE

NON-

-*-{;>O---+----7rn M7 M6

00-7

INT

INTA

8259A
MASTER

M5 M4 M3 M2 Ml MO

LLl.] 1
5

4

3

111
2

1

0

1

INTERRUPT REQUESTS

Figure 18. Cascaded 8259A'S 22 Interrupt Levels

Besides hardware set-up requirements, all 8259A's must
be software programmed to work in the cascade mode.
Programming the cascade mode is done during the initialization of each 8259A. The 8259A that is selected as
masteJ must receive specification during its initialization as to which of its IR inputs are connected to a
slave's INT pin. Each slave 8259A, on the other hand,
must be designated during its initialization with an ID (0
through 7) corresponding to which of the master's IR inputs its INT pin is connected to. This is all necessary so
the CASO-2 pins of the masters will be able to address
each individual slave. Note that as in normal operation,
each 8259A must also be initialized to give its IR inputs
a unique interrupt vector. More detail on the necessary
programming of the cascade mode is explained in "Programming the 8259A".
Now, with background information on both hardware
and software for the cascade mode, let's go over the
sequence of events that occur during a valid interrupt
request from a slave. Suppose a slave IR input has
received an interrupt request. Assuming this request is
higher priority than other requests and in-service levels
on the slave, the slave's INT pin is driven high. This
signals the master of the request by causing an interrupt request on a designated IR pin of the master. Again,
assuming that this request to the master is higher priority than other master requests and in-service levels
(possibly from other slaves), the master's INT pin is
pulled high, interrupting the processor.
The interrupt acknowledge sequence appears to the
processor the same as the non-cascading interrupt
acknowledge sequence; however, it's different among
the 8259A's. The first INTA pulse is used by all the
8259A's for internal set-up purposes and, if in the
8080/8085 mode, the master will place the CALL opcode
on the data bus. The first INTA pulse also signals the
master to place the requesting slave's ID code on the
CAS lines. This turns control over to the slave for the
rest of the interrupt acknowledge sequence, placing the

appropriate pre-programmed interrupt vector on the
data bus, completing the interrupt request.
During the interrupt acknowledge sequence, the corresponding ISR bit of both the master and the slave get
set. This means two EOI commands must be issued (if
not in the automatic EOI mode), one for the master and
one for the slave.
Special consideration should be taken when mixed
interrupt requests are assigned to a master 8259A; that
is, when some of the master's IR inputs are used for
slave interrupt requests and some are used for individual interrupt requests. In this type of structure, the
master's IRO must not be used for a slave. This is
because when an IR input that isn't initialized as a slave
receives an interrupt request, the CASO-2 lines won't be
activated, thus staying in the default condition addressing for IRO (slave IRO). If a slave is connected to the
master's IRO when a non-slave interrupt occurs on
another master IR input, erroneous conditions may
result. Thus IRO should be the last choice when assigning slaves to IR inputs.
Special Fully Nested Mode
Depending on the application, changes in the nested
structure of the cascade mode may be desired. This is
because the nested structure of a slave 8259A differs
from that of the normal fully nested mode. In the cascade mode, if a slave receives a higher priority interrupt
request than one which is in service (through the same
slave), it won't be recognized by the master. This is
because the master's ISR bit is set, ignoring all requests
of equal or lower priority. Thus, in this case, the higher
priority slave interrupt won't be serviced until after the
master's ISR bit is reset by an EOI command. This is
most likely after the completion of the lower priority
routine.
If the user wishes to have a truly fully nested structure
within a slave 8259A, the special fully nested mode
should be used. The special fully nested mode is pro2-134

121500-001

AP59
grammed in the master only. This is done during the
master's initialization. In this mode the master will
ignore only those interrupt requests of lower priority
than the set ISR bit and will respond to all requests of
equal or higher priority. Thus if a slave receives a higher
priority request than one in service, it will be recognized.
To insure proper interrupt operation when using the
special fully nested mode, the software must determine
if any other slave interrupts are still in service before
issuing an EOI command to the master. This is done by
resetting the appropriate slave ISR bit with an EOI and
then reading its ISR. If the ISR contains all zeros, there
aren't any other interro.jJts from the slave in service and
~ an EOI command ran be sent to the master. If the ISR
isn't all zeros, a:, EOI command shouldn't be sent to the
master. Clearing the master's ISR bit with an EOr com·
mand while there are still slave interrupts in service
would allow lower priority interrupts to be recognized at
the master. An example of this process is shown in the
second application in the "Applications Examples" sec·
tion.

how can it be used for both master-slave selection and
buffer control? The answer to this is the provision for
software programmable master-slave selection when in
the buffer mode. The buffered mode is selected during
each 8259A's initialization. At the same time, the user
can assign each individual 8259A as a master or slave
(see "Programming the 8259A").

4. PROGRAMMING THE 8259A
Programming the 8259A is accomplished by using two
types of command words: Initialization Command
Words (ICWs) and Operational Command Words
(OCWs). All the modes and commands explained in the
previous section, "Operation of the 8259A", are pro·
grammable using the ICWs and OCWs (see Appendix A
for cross reference). The ICWs are issued from the proc·
essor in a sequential format and are used to set-up the
8259A in an initial state of operation. The OCWs are
issued as needed to vary and control 8259A operation.
Both ICWs and OCWs are sent by the processor to the
8259A via the data bus (8259A CS 0, WR 0). The
8259A distinguishes between the different ICWs and
OCWs by the state of its AO pin (controlled by processor
addressing), the sequence they're issued in (ICWs only),
and some dedicated bits among the ICWs and OCWs.
Those bits which are dedicated are indicated so by fixed
values (0 or 1) in the corresponding ICW or OCW pro·
gramming formats which are covered shortly. Note,
when issuing either ICWs or OCWs, the interrupt
request pin of the processor should be disabled.

=

Buffered Mode

The buffered mode is useful in large systems where buf·
fering is required on the data bus. Although not limited
to only 8259A cascading, it's most pertinent in this use.
In the buffered mode, whenever the 8259A's data bus
output is enabled, its SP/EN pin will go low. This signal
can be used to enable data transfer through a buffer
transceiver in the required direction.
Figure 19 shows a conceptual diagram of three 8259A's
in cascade, each slave is controlling an individual 8286
8-bit bidirectional bus driver by means of the buffered
mode. Note the pull·up on the SP/EN. It is used to
enable data transfer to the 8259A for its initial program·
mingo When data transfer is to go from the 8259A to the
processor, SP/EN will go low; otherwise, it will be high.
A question should arise, however,. from the fact that the
SP/EN pin is used to designate a master from a slave;

=

4.1 INITIALIZATION COMMAND WORDS (leWs)

Before normal operation can begin, each 8259A in a
system must be initialized by a sequence of two to four
programming bytes called ICWs (Initialization Com·
mand Words). The ICWs are used to set·up the neces·
sary conditions and modes for proper 8259A operation.

MASTER
8259A

INT

INTR

Figure 19. Cascade·Buffered Mode Example

2-135

121500-001

AP59
Figure 20 shows. the initialization flow of the 8259A.
Both ICW1 and ICW2 must be issued for any form of
8259A operation. However, IGW3 and ICW4 are used
only if designated so in ICW1. Determining the' necessity and use of each ICW is covered shortly in individual
groupings. Note that, once intialized, if any programming changes within the ICWs are to be made, the entire
ICW sequence must be reprogrammed, not just an individuaIICW,.

The ICW programming format, Figure ·21, shows bit
designation and a short definition of each ICW. With the
ICW format as reference, the functions of each ICW will
now be explained individually.

,cw,

Certain internal set-up conditions occur automatically
within the 8259A after the first ICW has been issued.
These are:

1 ICW4NEEoED

o ~ NO ICW4 NEEDED

o"

A. Sequencer logic is set to accept the remain'ng ICWs
as designated in ICW1.

CASCADE MODE

CALL INTERVAL

B. The ISR (In-Service Register) and IMR (Interrupt Mask
Register) are both cleared.

1 ~ INTERVAL OF 4

o ~ INTERVAL OF 8

C. The special mask mode is reset

1 ~ LEVEL TRIGGERED INPUT

0" EDGE TRIGGERED INPUT

D. The rotate in automatic EOI mode flip-flop is c,leared.
E. The IRR (Interrupt Request Register) is selected for
the read register command.
'
F. If the IC4 bit equals 0 in ICW1, all functions in ICW4
are cleared; 8080/8085 mode is selected by default

G. The fully nested mode is entered with an initial priority assignment of IRO highest through IR7 lowest
H. The edge sense latch of each IR priority cell is
cleared, thus requiring a low to high transition to
generate an interrupt (edge triggered mode effected

ICW31MASTER DEVICE I

o~ly).

NO (SNGL=1)

NO

(IC'= 0)

NOH 1 SU\Vf Il) I', I OU/l,L TO lHE' (.ORHfSPONlJIN(, MASI EH If{ INPUT
NOT~

2

x INDICAl,S

DON T CARr

SOME OF THE TERMINOLOGY USED MAY DIFFER SLIGHTLY FROM EXISTING 8259A
DATA SHEETS. THIS IS DONE TO BETTER CLARIFY AND EXPLAIN THE PROGRAM·
MING OF THE 8259A, THE OPERATIONAL RESULTS REMAIN THE SAME.

Figure 20. Initialization Flow

Figure, 21 , Initialization Command Words (ICWS) Programming Format

2-136

121500-001

AP59
ICW1 and ICW2

IT,I T.I T.I T.' T.I

Issuing ICW1 and ICW2 is the minimum,amount of programming needed for any type of 8259A operation_ The
majority of bits within these two ICWs are used to designate the interrupt vector starting address. The remaining bits serve various purposes. Description of the ICW1
and ICW2 bits is as follows:
IC4:

SNGL:

ADI:

LTIM:'

The IC4 bit is used to designate to the 8259A
whether or not ICW4 will be issued. If any of
the ICW4 operations are to be used, ICW4
must equal 1. If they aren't used, then ICW4
needn't be issued and IC4 can equal O. Note
that if IC4 = 0, the 8259A will assume operation
in the MCS-80/85 mode.
The SNGL bit is used to designate whether or
not the 8259A is to be used alone or in the cascade mode. If the cascade mode is desired,
SNGL must equal O. In doing this, the 8259A
will accept ICW3 for further cascade mode programming. If the 8259A is to be used as the
Single 8259A within a system, the SNGL bit
must equal 1; ICW3 won't be accepted.
The ADI bit is used to specify the address interval for the MCS-80/85 mode. If a 4-byte address interval is to be used, ADI must equal 1.
For an 8-byte address interval, ADI must equal
O. The state of ADI is ignored when the 8259A
is in the MCS-86/88 mode.

T3-T7:

The T3-T7 bits are used to select the interrupt
type when the MCS-86/88 mode is used. The
programming of T3-T7 selects the upper 5
bits. The lower 3 bits are automatically inserted, corresponding to the IR level causing
the interrupt. The state of bits A5-A10 will be
ign_ored when in the MCS-86/88 mode. Establishing the actual memory address of the interrupt is shown in Figure 22.

I

I
I

I
I

:

_UPPER 5 BITS OF ~11081
INTERRUPT TYPE (USER PROGRAMMED)

IT21 T1 !TO' - ~EU~~:!~~~AI~L~~~~iRTED BY 826M)

I

I

I

I

r--I

r-...J

'T71T81 T51141T31T21 ill Tof -

COMPLETEIOB6I8088 INTERRUPT TYPE

10 !0 I 0 I 0 IT7 !Ts!Ts!T4!T3!T2! r,j TolD I 0 I_MEMORY
ADDRESS OF 808818088
INTERRUPT TYPE (TYPE x 4)
Figure 22. Establishing Memory Addre•• of 8086/8088 Interrupt Type

ICW3
The 8259A will only accept ICW3 if programmed in the
cascade mode (ICW1, SNGL=O). ICW3 Is used for
specific programming within the cascade mode. Bit
definition of ICW3 differs depending on whether the
8259A is a master or a slave. Definition of the ICW3 bits
is as follows:
SO-7
(Master):

If the 8259A is a master (either when the
SP/EN pin is tied high or in the buffered
mode when MIS = 1 in ICW4), ICW3 bit definition is SO-7, corresponding to "slave 0-7".
These bits are used to establish which IR inputs have slaves connected to them. A 1
designates a slave, a 0 no slave. For example, if a slave was connected to IR3, the S3
bit should be set to a 1. (SO) should be last
choice for slave designation.

100-102
(Slave):

If the 8259A is a slave (either when the SP/EN
pin is low or in the buffered m'ode when
MIS = 0 in ICW4), ICW3 bit definition Is used
to establish its individual identity. The 10
code of a particular slave must correspond
to the number of the masters IR input it is
connected to. For example, if a slave was
connected to IR6 of the master, the slaves
100-2 bits should be set to 100 = 0, 101 = 1,
and 102= 1.

The LTIM bit is used to select between the two
IR input triggering modes. If LTIM = 1, the level
triggered mode is selected. If LTIM = 0, the
edge triggered mode is selected.

A5-A15: The A5-A15 bits are used to select the interrupt vector address when in the MCS-80/85
mode. There are two programming formats
that can be used to do this. Which one is implemented depends upon the selected address
interval (AD I). If ADI is set for the 4-byte interval, then the 8259A will automatically insert
AO-A4 (AO, A1 = 0 and A2, A3, A4= IRO-7).
Thus A5-A15 must be user selected by programming the A5-A15 bits with the desired address. If ADI is set for the 8-byte interval, then
AO-A5 are automatically inserted (AO, A1,
A2=0 and A3, A4, A5=IRO-7). This leaves·
A6-A15 to be selected by programming the
A6-A15 bits with the desired address. The
state of bit 5 is ignored in the latter format.

I

ICW4
The 8259A will only accept ICW4 if it was selected in
ICW1 (bit IC4= 1). Various modes are offered by using
ICW4. Bit definition of ICW4 is as follows:
"PM:

The "PM bit allows for selection of either the
MCS-80/85 or MCS-86/88 mode. If set as a 1 the
MCS-86/88 mode is selected, if a 0, the
MCS-80/85 mode is selected.

AEOI:

The AEOI bit is used to select the automatic
end of interrupt mode. If AEOI = 1, the
automatic end of interrupt mode is selected. If
AEOI = 0, it isn't selected; thus an EOI command must be used durir:Jg a service routine.

MIS:

The MIS bit is used in conjunction with the buffered mode. If in the buffered mode, MIS
defines whether the 8259A is a master or a
slave. When MIS is set to a 1, the 8259A
operates as the master; when MIS is 0, it
operates as a slave. If not programmed in the
buffered mode, the state of the MIS bit is
ignored.

2-137

121500-001

AP59
BUF:

The BUF bit is used to designate operation in
the buffered mode, thus controlling the use of
the SP/EN pin. If BUF is set to a 1, the buffered
mode is programmed and SP/EN is used as a
transceiver enable output. If BUF is 0, the buf·
.fered mode isn't programmed and SP/EN is
used for masterlslave selection. Note if ICW4
isn't programmed, SP/EN is used for masterl
slave selection.

SFNM:

The SFNM bit designates selection of the
special fully nested mode which is used in
conjunction with the cascade mode. Only the
master should be programmed in the special
fully nested mode to assure a truly fully nested
structure among the slave IR inputs. If SFNM
is set to a 1, the special fully nested mode is
selected; if SFNM is 0, it is not selected.

10 'I" I" 1 I 01
0

c,1 c, 1

I

I L
Co

IR LEVEL TO BE ACTED UPON

o

1

2

3

4

5

6

7

f--lO

1

0

1

0

1

0

1

o

0

1

1

0

0

1

T

NON SPECIFIC EOI COMMAND
"SPECIFIC eOI COMMAND
ROTATE ON NON SPECIFIC EOI COMMAND

4.2 OPERATIONAL COMMAND WORD (OCWs)

1

0

ROTATE IN AUTOMATIC Eor MODE ISETI

o

0

ROTATE IN AUTOMATIC EOI MODE ICLEARI

}

AUTOMATIC ROTATION

}

Once initialized by the ICWs, the 8259A will most likely
be operating in the fully nested mode. At this pOint,
operation can be further controlled or modified by the
use of OCWs (Operation Command Words). Three
OCWs are available for programming various modes and
commands. Unlike the ICWs, the OCWs needn't be in
any type of sequential order. Rather, they are issued by
the processor as needed within a program.

I

0

1 '

I"MMI ' 'M 1

0

END OF INTERRUPT

}

SPECifiC ROTATION

1 ' I ' I '" I '"
I IL4_____'{"-O~:-"'ln-'-OO~MM-"TO.~~

---;-+---1----1

Figure 23, the OCW programming format, shows the bit
designation and short definition of each OCW. With the
OCW format as reference, the functions of each OCW
will be explained individually.

READ
IRRlG
ONNE'<.T

ISRfG
ONNf)(T

ROPULSE

AD PULSE

1 - POLL COMMAND

o " NO POL L COMMAND

OCW1
OCW1 is used solely for 8259A masking operations. It
provides a direct link to the IMR (Interrupt Mask Regis·
ter). The processor can write to or read from the IMR via
OCW1. The OCW1 bit definition is as follows:

RESET

SHCIAl

MO-M7: The MO-M7 bits are used to control the mask·
ing of IR inputs. If an M bit is set to a 1, it will
mask the corresponding IR input. A 0 clears
the mask, thus enabling the IR input. These
bits convey the same meaning when being
read by the processor for status update.

'in
SPECIAL

~ASk

SOME OF THE TERMINOLOGY USED MAY DIFFER SLIGHTLY FROM EXISTING 8259A I
DATA SHEETS. THIS IS DONE TO BETTER CLARIFY AND EXPLAIN THE PROGRAM·
MING OF THE 8259A, THE OPERATIONAL RESULTS REMAIN THE SAME.

Figure 23. Operational Command Words (OCWs) Programming Format

OCW2
OCW2 is used for end of interrupt, automatic rotation,
and specific rotation operations. Associated commands
and modes of these operations (with the exception of
AEOI initialization), are selected using the bits of OCW2
in a combined fashion. Selection of a command or
mode should be made with the corresponding table for
OCW2 in the OCW programming format (Figure 20),
rather than on a bit by bit basis. However, for com·
pleteness of explanation, bit definition of OCW2 is as
follows:
LO-L2:

The LO-L2 bits are used to designate an interrupt level (0-7) to be acted upon for the opera·
tion selected by the EOI, SL, and R bits of
OCW2. The level designated will either be
used to reset a specific ISR bit or to set a
specific priority. The LO-L2 bits are enab.led or
disabled by the SL bit.

EOI:

The EOI bit is used for all end of interrupt coin,
mands (not automatic end of interrupt mode).
If set to a 1, a form of an end of interrupt command will be executed depending on the state
of the SL and R bits. If EOI is 0, an end of inter·
rupt command won't be executed.

SL:

The SL bit is used to select a specific level for
a given operation. If SL is set to a 1, the LO-L2
bits are enabled. The operation selected by the
EOI and R bits will be executed on the
specified interrupt level. If SL is 0, the LO-L2
bits are disabled.

R:

The R bit is used to control all 8259A rotation
operations. If the R bit is set to a 1, a form of
priority rotation will be executed depending on
the state of SL and EOI bits. If R is 0, rotation
won't be executed.

2-138

121500-001

AP59
OCW3

OCW3 is used to issue various modes and commands to
the 8259A. There are two main categories of operation
associated with OCW3: interrupt status and interrupt
masking. Bit definition of OCW3 is as follows:
RIS:

The RIS bit is used to select the ISR or IRR for
the read register command. If RIS is set to 1,
ISR is selected. If RIS is 0, IRR is selected. The
state of the RIS is only honored if the RR bit is
a 1.

RR:

The RR bit is used to execute the read register
command. If RR is set to a 1, the read register
command is issued and the state of RIS determines the register to be read. If RR is 0, the
read register command isn't issued.

P:

The P bit is used to issue the poll command. If
P is set to a 1, the poll command is issued. If it
is 0, the poll command isn't issued. The poll
command will override a read register com·
mand if set simultaneously.
'

SMM:

The SMM bit is used to set the special mask
mode. If SMM is set to a 1, the special mask
mode is selected, If it is 0, it is not selected.
The state of the SMM bit is only honored if it is
enabled by the ESMM bit.

ESMM:

The ESMM bit is used to enable or disable the
effect of the SMM bit. If ESMM is set to a 1,
SMM is enabled. If ESMM is 0, SMM is disabled. This bit is useful to prevent interference
of mode and command selections in OCW3.

5. APPLICATION EXAMPLES
In this section, the 8259A is shown in three different application examples. The first is an actual design implementation supporting an 8080A microprocessor system,
"Power Fail/Auto Start wit/l Battery Back-Up RAM". The
second is a conceptual example of incorporating more
than 64 interrupt levels in an 8080A or 8085A system,
"78 Level Interrupt System". The third application is a
conceptual design using an 8086 system, "Timer Controlled Interrupts". Although specific microprocessor
systems are used in each example, these applications
can be applied to either MCS-80, MCS-85, MCS-86, or
MCS-88 systems, providing the necessary hardware and
software changes are made. Overall, these applications
should serve as a useful guide, illustrating the various
procedures in using the 8259A,
5.1 POWER FAIL/AUTO·START WITH BATTERY
BACK-UP RAM

The first application illustrates the 8259A used in an
8080A system, supporting a battery back-up scheme for
the RAM (Random Access Memory) in a microcomputer
system. Such a scheme is important in numerical and
process control applications. The entire microcomputer
system could be supported by a battery back-up
scheme, however, due to the large amount of current
usually required and the fact that most machinery is not
supported by an auxiliary power source, only the state
of calculations and variables usually need to be saved.
In the event of a loss of power, if these items are not
already stored in RAM, they can be transferred there and
saved using a simple battery back-up system.

The vehicle used in this application is the Intel®
SBC·80/20 Single Board Computer. An 8259A is used in
the SBC-80/20 along with control lines helpful in implementing the power-down and automatic restart sequence used in a battery back·up system. The SBC-80/20
also contains user·selectable jumpers which allow the
on·board RAM to be powered by a supply separate from
the supply used for the non-RAM components. Also, the
output of an undedicated latch is available to be connected to the IR inputs of the 8259A (the latch is cleared
via an output port), In addition, an undedicated, buffered
input line is provided, along with an input to the RAM
decoder that will protect memory when asserted.
The additional circuitry to be described was constructed on an SBC-905 prototyping board. 'An SBC-635
power supply was used to power the non-RAM section
of the SBC-80/20 while an external DC supply was used
to simulate the back-up battery supplying power to the
RAM. The SBC-635 was used since it provides an open
collector ACLO output which indicates that the AC
input line voltage is below 103/206 VAC (RMS).
The following is an example of a power-down and restart
sequence that introduces the various power fail signals.

1. An AC power failure occurs and the ACLO goes high
(ACLO is pulled up by the battery supply). This indicates that DC power will be reliable for at most 7.5
ms. The power fail circutry generates a Power Fail Interrupt (PFI) signal. This signal sets the P"R latch,
which is connected to the IRO input of the 8259A, and
sets the Power Fail Sense (PFS) latch. The state of
this latch will indicate to the processor, upon reset,
whether it is coming up from a power failur~ (warm
start) or if it is coming up initially (cold start).
2. The processor is interrupted by the 8259A when the
PFI latch is set. This pushes the pre-power-down program counter onto the stack and calls the service
routine for the IRO input. The IRO service routine
saves the processor status and any other needed
variables. The routine should end with a HALT
instruction to minimize bus transitions.
3. After a predetermined length of time (5 ms in this ex·
ample) the power fail circuitry generates a Memory
Protect (MPRO) signal. All processing for the power
failure (including the interrupt response delays) must
be completed within this 5 ms window. The MPRO
signal ensures that spurious transitions on the system control bus caused by power gOing down do not
alter the contents of the RAM.
4. DC power goes down.
5. AC power returns. The power-on reset circuitry on the
SBC-80/20 generates a system RESET.
6. The processor reads the state of the PFS line to
determine the appropriate start-up sequence. The
PFS latch is cleared, the MPRO signal is removed,
and the PFI latch driving IRO is cleared by the Power
Fail Sense Reset (PFSR) signal. The system then continues from the pre·power-down location for a warm
start by restoring the processor status and popping
the pre-power-down program counter off the stack.
Figure 24 illustrates this timing.
2-139

. 121500-001

AP59

POWER DOWN

RESTART

\~----

ACLO

'---------' 1--_/
IRO
PFS

PFSR

MPRD

---+------------\I-------~

---+---""""\

DC----+------~

"--~J
UP
ROUTINE

POWER

Figure 24. Power Down Restart Timing

Figure 25 shows the block diagram for the system.
Notice that the RAM, the RAM decoder, and the powerdown circuitry are powered by the battery supply.
The schematic of the power-down circuitry and the
SBC-80120 interface is shown in Figure 26. The design is
very straightforward and uses CMOS logic to minimize
the battery current requirements. The cold start switch
is necessary to ensure that during a cold start, the PFS
line is indicating "cold start" sense (PFS high). Thus, for

a cold start, the cold start switch is depressed during
power on. After that, no further action is needed. Notice
that the PFI signal sets the on-board PFI latch. The output of this latch drives the 8259A IRO input. This latch is
cleared during the restart routine by executing an OUTput D4H instruction. The state 01 the PFS line may be
read on the least significant data bus line (080) by executi~g an INput D4H instruction. An 8255 port (8255 #1,
port C, bit 0) is used to control the PFSR line.

BATTERY SUPPLY

CONTROLBUS-i-i-4----~----+_~~

DATABUS-i-4------+-·---1·-*------+_--~~--~+_------·~-~------J

ADDRESSBUS~~-----~----~

Figure 25. Block Diagram of SSC 80/20 with Power Down Circuit

2-140

121500-001

AP59

""
'"

SSC80/20

'"

LATCH

RAMCS

'AM

DECODER

, ,

J.

COLO-j
START

"-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--/I" 1-_ _ _ _ _--'-"'' -10

~=T

Figure 26. Power Down CirculI - SBe 80/20 Inlerlace

The fully nested mode for the 8259A is used in its initial
state to ensure the IRO always has the highest priority.
The remaining IR inputs can be used for any other purpose in the system. The only constraint is that the service routines must enable interrupts as early as possible. Obviously, this is to ensure that the power-down interrupt does not have to wait for service. If a rotating
priority scheme is desired, another 8259A could be
added as a slave and be programmed to operate in a
rotating mode. The master would remain in the initial
state of the fully nested mode so that the IRO still remains the highest priority input.
The software to support the power-down circuitry is
shown in Figure 27. The flow for each label will be
discussed.
After any system reset, the processor starts execution
at location OOOOH (STARn. The PFS status is read and
execution is transferred to CSTART if PFS indicates a
cold start (i.e., someone is depressing the cold start
switch) or WSTART if a warm start is indicated (PFS
LOW). CSTART is the start of the user's program. The
Stack Pointers (SP) and device initialization were included just to remind the reader that these must occur.
The first EI instruction must appear after the 8259A has
received i.ts initialization sequence. The 8259A (and
other devices) are initialized in the INIT subroutine.
When a power failure occurs, execution is vectored by
the 8259A to REGSAV by way of the jump table at
JSTART. The pre-power-down program counter is placed
on the stack. REGSAV saves the processor registers
and flags in the usual manner by pushing them onto the
stack. Other items, such as output port :>tatus, program-

mabie peripheral states, etc., are pushed onto the stack
at this time. The Stack Pointer (SP) could be pushed onto the stack by way of the register pair HL but the top of
the stack can exist anywhere in memory and there is no
way then of knowing where that is when in the power-up
routine. Thus, the SP is saved at a dedicated location in
RAM. It isn't really necessary to send an EOI command
to the 8259A in REGSAV since power will be removed
from the 8259A, but one is included for completeness.
The final instruction before actually losing power is a
HALT. This minimizes somewhat spurious transitions
on the various busses and lets the processor die
gracefully.
On reset, when a warm start is detected, execution is
transf,erred to WSTART. WSTART activates· PFSR by
way of the 8255 (all outputs go low then the 8255 is initialized). In the power-down circuitry, PFSR clears the
PFS latch and removes the MPRO signal which then
allows access to the RAM. WSTART also clears the PFI
latch which arms the 8259A IRO input. Then the 8259A is
re-initialized along with any other devices. The SP is
retrieved from RAM and the processor registers and
flags are restored by popping them off the stack. Interrupts are then enabled. Now the power-down program
counter is on top of the stack, so ~ecuting a RETurn instruction transfers the processor to exactly where it left
off before the power failure.
Aside from illustrating the usefulness of the 8259A (and
the SBC-80/20) in implementing a power failure protected microcomputer system, this application should
also point out a way of preserving the processor status
when using interrupts.

2-141

121500-001

AP59

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Figure 27, Power Down and Restart Software

5.2 78 LEVEL INTERRUPT SYSTEM
CAS BUS

The second application illustrates an interrupt structure
with greater than 64 levels for an 8080A or 8085A sys·
tem. In the cascade mode, the 8259A supports up to 64
levels with direct vectoring to the service routine. Extending the structure to greater than 64 levels requires
polling, using the poll command. A 78 level interrupt
structure is used as an illustration; however, the prin·
ciples apply to systems with up to 512 levels.

SAOO
SAO
INTA

MO
IRO

To implement the 78 level structure, 3 tiers of 8259A's
are used, Nine 8259A's are cascaded in the master·slave
scheme, givihg 64 levels at tier 2. Two additional
8259A's are connected, by way of the INT outputs, to
two of the 64 inputs. The 16 inputs at tier 3, combined
with the 62 remaining tier 2 inputs, give 78 total levels.
The fully nested structure Is preserved over all levels,
although direct vectoring is supplied for only the tier 2
inputs. Software is required to vector any tier 3 re·
quests, Figure 28 shows the tiered structure used In this
example. Notice that tNe tier 3 8259A's are connected to
the bottom level slave (SA7). The master-slaves are inter·
connected as shown in "Interrupt Cascading", while the
tier 3 8259A's are connected as "masters"; that is, the
SP/EN pins are pulled high and the CAS pins are left un·
connected. Since these 8259A's are only gOing to be
used with the poll command, no INTA is required, there·
fore the INTA pins are pulled high.

SP07

INT

SA10

INTA

Sii

INTA

SBOO

SA'
lNTA

SBO

MASTER

IR'

M'

INT

SA'7

INT

SA70

SP

S807

INTA

5810

SA7
INT

S8l

INTA

~

SA76

IR7

M7

INT

SA77

INT

5817

Figure 28. 78 Level Interrupt Structure

2-142

121500-001

AP59
The concept used to implement the 78 levels is to
directly vector to all tier 2 input service routines. If a tier
2 input contains a tier 3 8259A, the service routine for
that input will poll the tier 3 8259A and branch to the tier
3 input service routine based on the poll word read after
the poll command. Figure 29 shows how the jump table
is organized assuming a starting location of 1000H and
contiguous tables for all the tier 2 8259A's. Note that
"SA35" denotes the IR5 input of the slave connected to
the master IR3 input. Also note that for the normal tier 2
inputs, the jump table vectors the processor directly to
the service routine for that input, while for the tier 2 inputs with 8259A's connected to their IR inputs, the processor is vectored to a service routine (i.e., S80) which
will poll to determine the actual tier 3 input requesting
service. The polling routine utilizes the jump table starting at 1200H to vector the processor to the correct tier 3
service routi ne.

LOCATION

8259

CODE

1000 H

SAO

JMP

lOlC H

SAl

1020 H

103C H

• SADa SERVICE ROUTINE

JMP

SA07

, SA07 SERVICE ROUTINE

JMP

SAlO

, SAlO SERVICE ROUTINE

JMP

SA17

-- - - - - - - - - - - - - - - -

, SA 17 SERVICE AOUTINE

--- - - - - - - - -

, SA20-SA67 SERVICE ROUTINES
- ----------------------

10EO H

SA7

10F8 H
10FC H

1200 H

JMP

SA70

• SA7a SERVICE ROUTINE

JMP
JMP

SBO
SBl
SBOO

· S8l POLL ROUTINE

JMP

SBO

121C H
1220 H

SBl

123C H

Each 8259A must receive an initialization sequence
regardless of the mode. Since the tier 1 and 2 8259A's
are in cascade and the special fully nested mode is used
(covered shortly), all ICWs are reqlJired. The tier 3
8259A's don't require ICW3 or ICW4 since only polling •
will be used on them and they are connected as masters
not in the cascade mode. The initialization sequence for
each tier is shown in Figure 30. Notice that the master is
initialized with a "dummy" jump table starting at OOH
since all vectoring is done by the slaves. The tier 3
devices also receive "dummy" tables since only polling
is used on tier 3.
As explained in "Interrupt Cascading", to preserve a
truly fully nested mode within a slave, the master 8259A
should be programmed in the special fully nested mode.
This allows the master to acknowledge all interrupts at
and above the level in service disregarding only those of
lower priority. The special fully nested mode is programmed in the master only, so it only affects the immediate slaves (tier 2 not tier 3). To implement a fully
nested structure among tier 3 slaves some special
housekeeping software is required in all the tier-2-withtier-3-slave routines. The software should simply save
the state of the tier 2 IMR, mask all the lower tier 2 interrupts, then issue a specific EOI, resetting the ISR of the
tier 2 interrupt level. On completion of the routine the
IMR is restored.

COMMENTS
SADQ

• SSO POLL ROUTINE

• S800 SERVICE ROUTINE

JMP

5801

, S807 SERVICE ROUTINE

JMP

S810

• S810 SERVICE ROUTINE

JMP

SB17

• SB17 SI;RVICE ROUTINE

- ----

-----

--

Figure 29. JumlJTable Organization

INITIALIZATION SEQUENCE FOR 78 LEVEL INTERRUPT STRUCTURE
INITIALIze MASTER
MINT:

A,15H

MVI
OUT
MV'
OUT

OUT

MPTA
A,OOH
MPTB
A,OFFH
MPT8

MY'

A,IOH

OUT

MPTB

MY'

~

;
;
;
;
;
;
;
;

ICWI,LTM",O,4DI=1,S=O,IC4=1
MASTER PORT AO ... 0
ICW2, DUMMY ADDRESS
MASTER PORT AD 1
JCW3, S7·SO 1
MASTER PORT AD = 1
ICW4, SFNM", 1
MASTER PORT AO 1

=

=

=

INITIALIZE SA SLAVES - X DENOTES SLAVE 10 (SEE KEy)
SAXINT:

A,.

MVI
OUT
MV'
OUT
MV'
OUT

SAXPTA
A,10H
SAXPTB
AOXH
SAXPTB
A10H
SAXPTS

MY'
OUT

; SEe KEY FaR ICW1, LTM=O, AOI=1, S=O, IC4=1
; SA"X" PORT AO=O
; ICW2. ADDRESS Msa
; SA"X" PORT AO = 1
; ICW3, SAID
; SA"X" PORT AO", 1
; ICW4,SFNM=1
; SA"X" PORT AO=1

REPEAT ABOVE FOR EACH SA SLAVE
INITIALIZE 58 SLAVES ~ X DENOTES 0 or 1 (DO SBO, REPEAT FOR S81)
5BXINT

MV!
OUT

A,I8H
SBXPTA

My'

A,OOH

OUT

SBXPTB

;
;
;
;

ICW1. LTM=O, ADI '" 1, 5=1, lC4=0
SB"X" PORT AD 0 ,
ICW2, DUMMY ADDRESS
S8"X" PORT AO:= 1

=

SA INITIALIZATION KEY

Figure 31 shows an example flow and program for any
tier 2 service routine without a tier 3 8259A. FJgure 32
shows an example flow and program for any tier 2 service routine with a tier 3 8259A. Notice the reading of the
ISR in both examples; this is done to determine whether
. or not to issue an EOI command to the master (refer to
the section on "Special Fully Nested Mode" for further
details).

SA"X"
0

a (ICW1)

1

3.

2
3
4
5
5
7

15

••

1.

9'a.

D5
F5

JUMP TABLE START (H)
1000
1020
1(14D
1060
1080
10AD
lOCO
10EO

Figure 30. Initialization Sequence for 78 le.el Interrupt Structure

2-143

121500-001

AP59

; SA"X" "OUTINE • GENERAL INTERRUPT SERVICE ROUTtNE
; FOR TIER 2 ',NTERRUPTS WITHOUT TIER 3 125M
PUSH D

SAX

j
j

PUSH 8
PUSH H

SAVE DE

SAve Be

• SAYE HL
, SAVE A, FUGS
• ENABLE INTERRUPTS

PUSHPSW

EI
: ,SEAVlqE AOUTtNE ODES HERE

DI
MVI

~PTA

MUI
OUT
IN
ANI

, ocwa. READ REGISTER. ISA

A,OBN
SAXPTA

, SA"X" PORT 401110
• SA"X" PORT AD = 0, SA"X" ISA
I TEST FDA ZERO

SAXPTA
OFFH

JZN

,
,
•
,

SAXRSA

MYI

A,OBH
MASPTA
PSW

OUT
SAXASA

I DISABLE INTERRUPTS
• DCW2, NON·SPECIFIC EOI
j SA"X" PORT AU III 0

20.

OUT

POP

pop
pop
pop

.,

IF NOT ZEAO, RESTORE STATUS
OCW2, NON SPECIFIC E01
MASTER PORT AO ... O
RESTORE A, FLAGS

H
B

: RESTO"E HL

D

• RESTORE DE

• RESTORE Be
• ENABLE INTERRUPTS
• RETURN

. RET

Figure 31. Example Service Routine for Tier 2 Interrupt (SA"X', without ner 3 8259A (SB"X',

• sa"X" ROUTINE. SERVICE ROUTINE FOR TIER 2
j

INTERRUPTS WITH nEA 3 IUlAS
PUSH D
I SAVE DE
PUSH I
, SAVE Be

sax

PUSH H
PUSH paw

IN

SAXPTB

MOV

D.A

MVI
OUT
MVI
OUT

A,xXtt
SAXPT.

LXI
MVI
MYI
OUT
IN
ANI
ADD
ADD
MOV
DAD

: SAVE Hl
i SAVE A, FlAGS
IJ

j

READ SA"X"'MR

I

I

SAVE

; MASK SA"X" LOWER IA
I SA"X" PORT AD '"' 1
A.8XH
; OCW2 SPECIFIC EOI SA"X"
SAXPTA
• SA"X" PORT AD ... '
H,1_H
I JUMP TABLE START
B.cMltt
' CLEAR a
A,oe..
• OCW3. POLL COMMAND
SBlCPTA
; SB"X" PORT AD-O
saXPTA. GET POLL WORD
07H
• LIMIT TO 3 BIT$
A
: GET TABLE OFFSET

A
C,A

I

EI

: OFFSET TO C
: HL HAS TAILE ADDAESS
I ENABLE INTERRUPTS

S8"X"RET ROUTINE - FOR EOI AND MASK RESTORE
AFTER SB"X" ROUTINE
SIXRET

OUT

.....

MVI

",B.

OUT

SAXPTA
saXPTA
OFFH
SIXRSR
A,20H

DI

MYI

'IN,

ANI
JHZ
MVI

OUT
saXRSR" MOV

OUT
PDP

POP
POP

POP
EO

RET

SIXPTA

• DISABLE INTERRUPTS
• OCW2, NON SPECIFIC EOI
, SA"X" PORT AD-O
• ocwa, READ REGISTER ISR
:

:::~::~: =:~\ISA

; TEST FOR ZERO
; IF.ORESTOREIMR

: 0CW2, NON-5PEClftC EOI

MABPTA
A.D

: MASTER PORT AD_ 0
I RESTORE SAlOl(" IMR

SAXPT8

, SA"X" PORT AD-1
• RESTORE A, FLAGS

PSw
H
B
D

, RESTORE HL
; RESTORE BC

, RESTORE IC
i RESTORE DE
; RETURN

Figure 32. Example Service Routine for Tier 2 Interrupt (SA"X") with n.r 3 8259A (SB"X',
2-1~

121500-001

AP59
5.3 TIMER CONTROllED INTERRUPTS
In a large number of controller type microprocessor
designs, certain timing requirements must be imple·
mented throughout program execution. Such time
dependent applications include control of keyboards,
displays, CRTs, printers, and various facets of industrial
control. These examples, however, are just a few of
many designs which require device serviCing at specific
rates or generation of time delays. Trying to maintain
these timing requirements by processor control alone
can be costly in throughput and software complexity.
So, what can be done to alleviate this problem? The
answer, use the 8259A Programmable Interrupt Con·
troller and external timing to interrupt the processor for
time dependent device servicing.
This application example uses the 8259A for timer controlled interrupts in an 8086 system. External timing is
done by two 8253 Programmable Interval Timers. Figure
33 shows a block diagram of the timer controlled inter·
rupt circuitry which was built on the breadboard area of
an SDK·86 (system design kit). Besides the 8259A and
the 8253's, the necessary 1/0 decoding is also shown.
The timer controlled interrupt circuitry interfaces with
the SDK·86 which serves as the vehicle of operation for
this design.
A short overview of how this application operates is as
follows. The 8253's are programmed to generate inter·
rupt requests at specific rates to a number of the 8259A
IR inputs. The 8259A processes these requests by interrupting the 8086 and vectoring program execution to the
appropriate service routine. In this example, the
routines use the SDK-86 display panel to display the
number of the interrupt level being serviced. These
routines are merely for demonstration purposes to show
the necessary procedures to establish the user's own
routines in a timer controlled interrupt scheme.
Let's go over the operation starting with the actual inter·
rupt timing generation which is done by two 8253 Pro·
grammable Interval Timers (8253 #1 and 8253 #2). Each
8253 provides three individual 16-bit counters (counters

0-2) which are software programmable by the proc·
essor. Each counter has a clock input (ClK), gate input
(GATE), and an output (OUT). The output signal is based
on divisions of the clock input signal. Just how or when
the output occurs is determined by one of the 8253's six
programmable modes, a programmable 16-bit count,
and the state of the gate input.
Figure 34 shows the 8253 timing configuration used for
generating interrupts to the 8259A. The SDK·86's PClK
(peripheral clock) signal provides a 400 ns period clock
to ClKO of 8253 #1. Counter 0 is used in mode 3 (square
wave rate generator), and acts as a prescaler to provide
the clock inputs of the other counters with a 10 ms
period square wave. This 10 ms clock period made it
easy to calculate exact timings for the other counters.
Counter 2 of the 8253 #1 is used in mode 2 (rate gener·
ator), it is programmed to output a 10 ms pulse for every
200 pulses it receives (every 2 sec). The output of
counter 2 causes an interrupt on IR1 of the 8259A. All
the 8253 #2 counters are used in mode 5 (hardware triggered strobe) in which the gate input initiates counter
operations. In this case the output of 8253 #1 counter 2
controls the gate of each 8253 #2 counter. When one of
the 8253 #2 counters receive the 8253 #1 counter 2 out·
put pulse on its gate, it will output a pulse (10 ms in
duration) after a certain preprogrammed number of
clock pulses have occurred. The programmed number of
clock pulses for the 8253 #2 counters is as follows: 50
pulses (0.5 sec) for counter 0, 100 pulses (1 sec) for
counter 1, and 150 pulses (1.5 sec) for counter 2. The
outputs of these counters cause interrupt requests on
IR2 through IR4 of the 8259A. Counter 1 of 8253 #1 is
used in mode 0 (interrupt on terminal count). Unlike the
other modes used which initialize operation automatically or by gate triggering, mode 0 allows software
controlled counter initialization. When counter 1 of 8253
,,#1 is set during program execution, it will count 25
clocks (250 ms) and then pull its output high, causing an
interrupt request on IRO of the 8259A. Figure 35 shows
the timing generated by the 8253's which cause inter·
rupt request on the 8259A IR inputs.

EACH DEVICE Vee'" +5V, GND ;; ~

Figure 33. Timer Controlled Interrupt Circuit on SDK 86 Breadboard Area

2-145

121500-001

AP59
GATE1 f+sV
eLK1

GAlEa

I

y+5V

82""
COUNTERO
MODE 3

J

I

GATE2 y+5V

II

OUT 0
(10 ms)

ClK2

J

8~53#1

8253#1

COUNTER 1

MOOED

II

OUT1

I

lOU12

I C~UON.,r:~ I
2

GAlEO

CLKO

_I

I

1

C~~~3T~2R 0
MODES

,.2

I aUTO

I

CLK1

GATE1

J

I

8253*2

COUNTER 1
MODe 5

II
I

OUT1

CLK2

GATE2

I c~~~~~~

-I

2

OUT2

MODES

T
,.4

Figure 34. 8253 Timing Conllguration lor Timer Controlled Interrupts

,.0

8253#1
\
COUNTER 1

82531#2
COUNTER 0

\

,.,
u.-----I·,\ ,.2

u

r------u

u

u..----I\\ ,.3

c~~~~~~ 1 I\-\-----,Ur--------,U
c~a~~:~2

r

\ -\------,'U'r--------,U
I

\

\

\

!

\

I

\

!

S

'R4

\

250 ms PER DIVISION
(EACH SMAL.L PULSE IS 10 ms IN DURATION)

Figure 35. 8259A IR Input Signal From 8253S

There are basically two methods of timing generation
that can be used in a timer controlled interrupt structure: dependent timing and independent timing. Dependent timing uses a single timing occurrence as a reference to base other timing occurrences on. On the other ~
hand, independent timing has no mutual reference between occurrences. Industrial controller type applications are more apt to use dependent timing, whereas independent timing is prone to individual device control.
Although this application uS\lsprimarily dependent timing, independent timing is also incorporated as an
example. The use of dependent timing can be seen back
in Figure 34, where timing for IA2 through IA4 uses the
lAt pulse as reference. Each one of the 8253 #2 counters
will generate an interrupt request a specific amount of
times after the IA1 interrupt request occurs. When using
the dependent method, as in this case, the IA2 through
IA4 requests must occur before the next IA1 request.
Independent timing is used to control the lAO interrupt
request. Note that its timing isn't controlled by any bf
the other IA requests, In this timer controlled interrupt
configuration the dependent timing is initially set to be
self running and the independent timing is software
initialized, However, both methods can work either way
by using the various 8253 modes to generate the same
interrupt timing.

IA jnput becomes active on the rising edge. With this in
mind, Figure 35 shows that lAO will generate an interrupt every half second and IA1 through IA4 will each
generate an interrupt every 2 seconds spaced apart at
half second intervals. Interrupt vectoring in the
MCS-86/88 mode is programmed so lAO, when activated,
will select interrupt type 72. This means IA1 will select
interrupt type 73, IA2 interrupt type 74, and so on
through IA4. Since IA5 through IA7 aren't used, they are
masked off. This prevents the possibility of any accidental interrupts and rids the necessity to tie the
unused IA inputs to a steady level. Figure 36 shows the
8259A IA levels (lAO~IA4) with their corresponding interrupt type in the 8086 interrupt-vector table. Type 77 in
the table is selected by a software "INT" instruction
during program execution. Each type is programmed
with the necessary, code segment and instruction
pOinter values for vectoring to the appropriate service
routine. Since the 8259A is programmed in the automatic EOI Mode, it doesn't require an EOI command 1'0
designate the completion of the service routine.

TYPE 77
TYPE 76
TYPE 7S

The 8259A processes the interrupts generated by the
8253's according to how it is programmed. In this application it is programmed to,operate in the edge triggered
mode, MCS-86/88 mode, and automatic EOI mode. In the
edge triggered mode an interrupt request on an 8259A

SOFTWARE INT
I
'
R4j' 8259A

TYPE 74

I R3
I R2

TYPE 73

I R1

TYPE 72

I RO

Figure 38. Interrupt "Type" Designation

2-146

121500-001

AP59
As mentioned earlier, the interrupt service routines in
this application are used merely'to demonstrate the
timer controlled interrupt scheme, not to implement a
particular design. Thus a service routine simply displays
the number of its interrupting level on the SDK·86 dis·
play panel. The display panel is controlled by the 8279
Keyboard and Display Controller. It is initialized to
display "Ir" in its two left·most digits during the entire
display sequence. When an interrupt from IR1 through
IR4 occurs the corresponding routine will display its IR
number via the 8279. During each IR1 through IR4 servo
ice routine a software "INT77" insiruction is executed.
This instruction vectors pro,Qram execution to the servo
ice routine designated by type 77, which sets the 8253
counter controlling IRO so it will cause an interrupt in
250 ms. When the IRO interrupt occurs its routine will
turn off the digit displayed by the IR1 through IR4
routines. Thus each IR level (IR1-IR4) will be displayed
for 250 ms followed by a 250 ms off time caused by IRO.
Figure 37 shows the entire display sequence of the
timer controlled interrupt application.

.,

I

,.", ,

'R1

, I I , .RO
2

['J'J J

.R2

"1' I I

I I I , .RO

"1' I I

131 I , .R3

,,1, I I

I I I , .RO

.

,

"1' I I

8259A for the edge triggered mode, automatic EOI
mode, and the proper interrupt vectoring (IRO, type 72).
OCW1 is used to mask off the unused IR inputs
(IR5-IR7). The 8279 is then set to display "IR" on its two
left·most digits. After that the 8086 enables interrupts
and a "dummy" main program is executed to wait for in·
terrupt requests.

y

.R4

I I I , .RO

Figure 37. SDK Display Sequence lor Timer Conlrolled Inlerrupls
Program (Each Display Block Shown Is 250 msec
in Duration)

Figure 38. Inilializalion Program Flow for Timer Conlrolled Inlerrupls

There are six different interrupt service routines used in
the program. Five of these routines, "INTR72" through
"INTR76", are vectored to via the 8259A. Figure 39A·C
shows the program flow for all six service routines. Note
that "INTR73" through "INTR76" (IR1-IR4) basically use
the same flow. These four similar routines display the
number of its interrupting IR level on the SDK·86 display
panel. The "INTR77" routine is vectored to by software
during each of the previously mentioned routines and
sets up interrupt timing to cause the "INTR72" (IRO)
routine to be executed. The "INTR72" routine turns off
the number on the SDK·86 display panel.
'

Now that we've covered the operation, let's move on to
the program flow and structure of the timer controlled
interrupt program. The program flow is made up of an
initialization section and six interrupt service routines.
The initialization program flow is shown in Figure 38. It
starts by initializing some of the 8086's registers for pro·
gram operation; this includes the extra segment, data
segment, stack segment, and stack pointer. Next, by
using the extra segement as reference, interrupt types
72 through 77 are set to vector interrupts to the appro·
priate routines. This is done by moving the code seg·
ment and instruction pOinter values of each service
routine into the corresponding type location. The 8253
counters are then programmed with the proper mode
and count to provide the interrupt timing mentioned
earlier. All counters with the exception of the 8253 #1,
counter 1 are fully initialized at this point and will start
counting. Counter 1 of 8253 #1 starts counting wtien its
counter is loaded during the "INTR77" service routine,
which will be covered shortly. Next, the 8259A ill issued
ICW1, ICW2, ICW4, and OCW1. The ICWs program the

(

A INTERRUPT ON

8259AIRO

INTR73-76

B. INTERRUPT ON
8259A IR1-IR4

)

C. SOFTWARE INVOKED
INTERRUPT

Figure 39. A-C. Interrupts Service Routine Flow for
Timer Conlrolled Interrupts.

2-147

121500·001

AP59
To best explain how these service routines work, let's
assume an interrupt occurred on IR·l of the 8259A. The
associated service routine for IRl is "INTR73". Entering
"INTR73", the first thing done is saving the pre·interrupt
program status. This isn't really necessary in this program since a "dummy'\main program is being executed;
however, it is done as an example to show the operation.
Rather than having code for saving the registers in each
separate routine, a mutual call routine, "SAVE", is used.
This routine will save the register status by pushing it
on t~e stack. The next portion of "INTR73" will display
the number of its IR level, "1", in the first digit of the
SDK-86 display panel. After that, a software INT instruc·
tion Is executed to vector program execution to the
"INTR77" service routine. the "INTR77" service routine
simply sets the 8253 #1 counter 1 to cause an interrupt
on IRO in 250 ms and then returns ,to "INTR73". Once
back in "INTR73", the pre·interrupt status Is restored by
a call routine, "RESTORE". It does the opposite of
"SAVE", returning the register status by popping it off
the stack. The "INTR73" routine then returns to the
"dummy" main program. The flow for the "INTR74"
through "INTR76" routines are the same except for the
digit location and the IR level displayed.

After 250 ms have elapsed, counter 1 of 8253 #1 makes
an interrupt request on IRO of the 8259A. This causes
the "INTR72" service routine to be executed. Since this
routine interrupts the main program, it .also uses the
"SAVE" routine to save pre·lnterrupt program status. It
then turns off the digit displaying the IR level. In the
case of the "INTR73" routine, the "1" is blanked out.
The pre-interrupt status Is then restored using the,
"RESTORE" routine and program execution returns to
the "dummy" main program.
The complete program for the timer controlled interrupts application is shown In Appendix B. The program
was executed in SDK-86 RAM starting at location 0500H
(code segment 0050, Instruction pOinter 0).

=

=

CONCLUSION

This application note has explained the 8259A in detail
and gives three applications Illustrating the use of some
of the numerous programmable features available. It
should be evident from these discussions that the
8259A Is an extremely flexible and easily programmable
member of the Intel@ MCS-80, MCS-85, ~CS-86, and
MCS-88 families .

..

2-148

APPENDIX A
Thi.s table is provided merely for reference information between the "Operation of the 8259A" and "Programming the
8259A" sections of this application note. It shouldn't be used as a programming reference guide (see "Programming
the 8259A").
Operational
Description

MCS-80/85

Command
Words

,Mode

Bits

ICW1,ICW4*

IC4,I'PM*

Address Interval for MCS·80/85 Mode

ICW1

ADI

Interrupt Vector Address for MCS·80/85 Mode

ICW1,ICW2

A5-A15

MCS-86/88 Mode

ICW1,ICW4

IC4,I'PM

Interrupt Vector Byte for MCS-86/88 Mode

ICW2

T3-T7

Fully Nested Mode

OCW-Default

Non-Specific EOI Command

OCW2

EOI

Specific EOI Command

OCW2

SEOI, EOI,
LO-L2

Automatic EOI Mode

ICW1,ICW4

IC4, AEOI

Rotate On Non-Specific EOI Command

OCW2

Rotate In Automatic EOI Mode

OCW2

Set Priority Command

OCW2

Rotate on Specific EOI Command

OCW2

R, SEOI, EOI

Interrupt Mask Register

OCW1

MO-M7

Special Mask Mode

OCW3

ESMM-SMM

Level Triggered Mode

ICW1

LTIM

Edge Triggered Mode

ICW1

LTiM

Read Register Command, IRR

OCW3

ERIS, RIS

Read Register Command, ISR

OCW3

ERIS, RIS

Read IMR

OCW1

MO-M7

Poll Command

OCW3

P

Cascade Mode

ICW1,ICW3

SNGL, SO-7,
100-2

Special Fully Nested Mode

ICW1,ICW4

IC4, SFNM

Buffered Mode

ICW1,ICW4

IC4, BUF,
M/S

EOI
. R, SEOI, EOI
LO-L2

*Only needed if ICW4 is used for purposes other than pP mode set

2-149

121500-001

APPI:NDIX 8
t1CS-86 ASSEI'IBLER

TCI59A

PAGe

ISIS-II t1CS-86 ASSCI'IBLER 111. 8 flSSEl'IBL1' OF t10DULE TCI59A
OBJECT MODUlE PLACE!) IN :F1: TCI59A. 08.J
ASSEI'IIllER INYOKED BI': :F1:A5MS6 :F1.TCI59A.SRC
LOC 08J

LINE
1
2
3

9120

9120 9491
9122?m
8124 1801
8126 ????
9128 3801
912ft ????
812C4801
912E m?
8130 6001
8132 ????
91347801
8B6 ????

0000 ????
ilI:l02

m?

0004 ??

4
5
6
7
B
9
19
11
12
13
14

1S
16
17
1S
19
20
21
22
23
24
25
26
27
2B
29
39
31
32

3J
. 34

SOURCE

******************** TIMER CONTROLLEf) INTI:.RRUPTS ******""-****"'''''''****'''

j

i

EXTRA SEGMENT DECLARATIONS

j

EXTRA SI:.UMENl

TP72IP
TP72CS
TPnIP
TPnCS
TP74IP
TP741.'S
TP75IP
TP75CS
lP76IP

ORO
OW
OW
DId
OW
OW
OW
I.lW
OW
I.lW

TP76C5 DW
TP77IP DId
TP77CS OW

B80800
SEC9
887009
8El>B
llll7898

000D SEOO
000F BC8000

j TYPE 72 INSTRUCTION POINTER
; WPE 72 CODE SEGMENT
; T'r'PE i'J INS1RUCTIUN POINTER
; TYPE n CODE SEG/1ENr
; TYPE 74 INSTRUCT ION POINTER
; TYPE i'4. eWE SEGMENT
,TYrE 75 INSTRUCTION PO INTER
; WPE 7S CODE Sf:.Gl'lENl
; lYPE 76 INSTRUCTION POINTER
.' TYPE 76 CODE SEGMENT
; TYrE 77 INSTRUCTION PUINTl:.R
,T'r'PE 77 CODE SEGMENT

?
INTR74
?
INTR7S
?
IN1R76
?

INTR77
?

EXTRA ENDS
DATA SEGMENT DEClAl?.RTI ONS
DATA

SEGMENT

STACK! DW
AXTEMP DId
DIGll DB
DAm

; YARIABlE TO SAllE t;AlL flI.lDRtSS
; VARIABLE TO SAllE AX REGIS rEk
; VARIABLE TO SAVE SELEmD DIGIT

?
?
?

ENl)S

;

35
36

0000
0093
eoos
0008
090A

12aH
INTR72
?
INTR73

CODE SEGMENT DECLARATION

37

CODE

38
39
40
41
42
43
44
45
46
47
4B
49

;

SCGMENT

ASSUI'IE ES: EXTRA, OS: DrlTA, CS: CODE
INITIflLI2E REGISTERS
START:

HOII
1'1011

1'10.,.
MOl/
I'1OV
I'1OV
I'1OV

AX,0H
ES,AX
AX,70H
D$,fil(
AX,?SH
SS,AX
SP,8aH

; CXTRA SCGt1ENT AT 0H
'DATA SEGMENT AT 709H
; S1 ACK SEGMENT fiT 7130H
; STACK POINT£R AT 80H (STflCK=890H)

2-150

121500-001

1

APPENDIX B (continued)
MCS-86 ASSEI'IBLER

0012
0015
9019
901E
9021
9025
002A
Il02l)

0031
0036
0039
903D
9042
0945
0949
904E
9951
9955

TCI59A

PAGE.

LINE

LOC OBJ

B80481
2CH32801
26SC0E2291
881801
26A32491
26SC9E2691
883001
26A32atJ1
268C8E2A91
884881
26A32C81
26SC8E2E91
BI?.6991
26A33001
26SC9E3201
li87881
26fm491
268C0E3691

SOURCE

50
51
52

;

~iJ

Tl'PE.S.

54
55

LOAI) INTcRRUf'l VECTOR TABLE
I'IOV
r10V

:)6

MO\I
r10V

57

I'lO\l

sa
59
69
61
62
63
64
65
66
67
68
69
79
71

1'1011

I'IOY
I'IOY
I'IOY
HOV
MOY
MOY
MOY
MOil
I10V
MOil
1'10'.'
I'IOY

72
73

AX., OFfSET
"iP72IP, AX
"iP72CS, CS
AX.. OFFSET
TP73IP,Al(
lP73CS. I,;S
AX, OFFSET
TP74IP,ffX
lP74CS,CS
AX, OFFSET
TP75IP, AX
Tf'7SCS. CS
AX, OFF5[1
TP76IP,AX
TP76CS,CS
AX.OfFSEf
TPmf', AX
IP77CS, CS

9989 EE

100

998A B000

191
192
103

11011

104

I'IOY

AL,09H

BA8EFF
8036
EE
B071
EE
B0BS
EE
etJ66 BA08FF
0069 B3AS

006B IT
886C
006E
8iI6F
0072
9974
007S
9977
9978
9978
11970
997E
lI889
9081
9983
9984

8061
EE
BAOCFF
B099
EE
BOO2
EE
BA16FF
803B
EE
1l97B
EE
BllBB
EE
BA10FF

9881'

~58

008C EE
808D BA12FF
9999 B0!l0

,

74
7S
76
77
?8
?9
80
81
82
83
84

as
86
87
88
89

99
91
92
93
94
95
96
97
9S

99

•LOAI) TYPI: i'2



,LOAD TYPE 73

(WTR74)

; LOAD PIPE 74

(INTR75>

; LOAI) TYPE 75

(INTR76)

; LOAI) Tl'PE 76

(lNT"'??)

; LOHD T't'PE 7"t

8253 INlTIALIZATION
[)X,eFF8EH
AL,36H
DX,AL
AL.71H
DX,AL
AL,0BSH
ox..AL
OX,0FF08H
AL,0A8H
DX,AL
AL,61H
DX,AL
DX,0FFOCH
AL,90H
DX,AL
AL 92H
DX,AL
ox, 0FF16H
AL, $BH
DX,AL
AL,7BH
DX,AL
AL,9BBH
DX,AL
DX,0FF19H
AL, 59H
DX,AL
AL,90H
DX,AL
Dx.. 0FF12H

985A
005D
995F
9060
9062
0063
9965

(INTR72>

SETS31: 1'1011
I10V
OUT
I'lO\l
OUT
I'lO\l
OUT
1'1011

I10V
OUT
I'lO\l
OUT
I'IOY
I'IOY

OUT
I10V
OUT
SETo32: I'IOV
1'1011

OUT
!'lOY

OUT
I10V
OUT
I10V
!'lOY
OUT
1'1011

OUT

2-151

; 8203 iii CONTROL WORD
•COUNTER 0, MODE 3, BINARY

.; coum!:R

1, MODE 0, BCD

; COUNTER 2. MODE 2, BCD
; LOAI) COlllHER 0 (101'1S)
,LSB
iMSB
; LOAD COUNTER 2 (2SEC)
;LSIi
i I'ISB

i 8253 12 (;ON] ROL WORD
.; COLINTER 0, I'IODI: 5, BCD

; COUNTER

1,

MODE

!),

BCD

.' COUNTER 2, MODE 5, BCD
i LOAI) COUNTER 0 C 5SU;)
iLSB

;I'ISB
;LOAD COUNTER 1
,LSB

(1SE~)

.121500-001

2

APPENDIX ~ (continued)
I1C5-86 f6SEMBLEI?

lOC OBl
0092
0093
a095
0096

EE
Btllil
EE
BA14fr

0099
0fl9B
009C
€IB9E

B05fl
tE
Bt101
Ef:

f'fIGI: . 3

TCI59A

LINE
105
106

5OI.*CE

,

OUT

[):~,AL

MO'}

AL 91H
I)X,AL
OK.8FF14H
AL 5flH
I)X,AL
AL,81H
OX,AL

our
1'101/

107

198
199
110
111
112
113

MOV
OUT

MOV
OUl

114
009F
0BA2
f.l0A4
88A5
OOAB

BA08FF
B£l1:.<
Ef:
Bft!i<:Ff
B043

115
116
117
W3
119
1211

OOAA EE

121

00AB
OOAD
!lBAE
a8Bt]

12'2
123
124
125
126
127

BOO:;
EE
8eE0
EE

0081 BlUFF
00B4 BaD0
OOB6 EE
a0B? EC
eaBa 00ce
OOBA ?2FB
OOBe 8087
eOOE EE
000F 6AE8FF
9!JC2 6006
00(;4 EE
!1OCS BAEAFF
ooee B086
OOCA EE
80CB BAE8FF
OOCE B850
OOoo·E£
13001 FB

.iMSB
. LOA]) tOUNTI::R 2 (1. 5SEe)
iL~B

. MSB

fJ259fl INITIflllZkTION
SET59A: MOIl
MOl{
our
MO~'

MO'1
OUT
MOY
OUT
MOl/

our

,

129
130

-,ET79: MOV

131
132
133
134

(VJT
WAIT79: IN

MO~'

~

JB
MOV

om

136
B7
138
139
140
141
142
143 .
144
145

MOI/

MOil
OUT
~101/

MO','

OUT
MOV
MOI/
OUT
STJ

146

. 825% 00=0
lCW1-L TlM:f1. 5=1, IC4=1

i

;8259A flO=1
.i ICW2-INTERRlJrr TYf'1:: ;'2 (120H)
.i ICfl4-SFNt-1=B, Bur=0, flEOI=1, MPt-1=l
; 0CI41-MASK IRS, 6, 7 (NOT USED)

8279 INITIAL UflTION

128

135

DK.8FFOOH
Al,13H
DK.AL
DX.0FF02H
AL, 48H
DX,Al
AL 0St-1
DX,AL
AL,0EeH
DX,AL

DX, OFFEAlI
AL,ooeH
DX,AL
AL,DX
tiLl
WAlT79
AL, 87H
DX,AL
OX,0FFESH
ALtltolI
DX,AL
DX, aFFEAH
AL,86H
DX,AL
DX,8FFE8H
AL,59H

. 8279 COI'1MANI.l loJORDS ftN!) STATUS
. CLEAR D1SPLA'r'
; ~r.D S1ATlJS
.' "[lU' BIT TO CARRY
; JIJMP 1F DISf'LA'1 IS UNAIIAILABLE
;r,I61T a
; 8279 DATA WORD
i CHARACH:R 'I"
. 8279 COMMAND WORD
. DIGIT 7
; 82(9 DATA WORD
; CHARACTER "RH

DX,K
; ENABLE ltITERRUf'TS

147

148
149

DUMMY PROGRAM

150
0002 EBFE

0004 A30200
000758
0008 A30000
OODB A1B230
00DE !le
OODF 53

151
152
153
154
155
1~

157
1~

159

~'.

JMP

; WAIT FOR INTtRRIJPT

. DUMMY

;

SAllE .

MOV

pop
MOil
110V
PUSH
PUSH

AXTEMP, AX
AX
STACK1, AX
AX,AXTEMP
AX
BX

2-152

; SAI/E AX
; POP CALL RETURN ADOOESS
,SAllE CALL RETlJr~N ADDRl:SS
; RESTORE AX
; SAVE PROCESSOR STft-IIJ5

121500-001

APPENDIX B (continued)
11(:5-86 A:;SEMBLER
LOC OBJ
OOE0
00E1
OOE2
00E3
OOE4
00E5
00E6
00E7
00EA
00EB

!)1
52
55
56
57
1E
06
A10f:l00
50
C3

OOEC 58
00EO A30000
001'0 07
00Fl1F

OOF2 5F
5E
SD
SA
59
58
58
A38280
Al0000
~FF 50
IUOO Al0200
0103 G3
001'3
OOF4
00F5
00F6
00F7
80F8
00F9
00FG

9194
0197
, 010A
0l0D
010£
0111
01:8
0114
0117

ESCDFF
BAEAFF
AOO400
EE
BAESFF
B000
EE
E805FF
CF

TCI59A

PAGE

LINE

SOURCE

160
161
162
163
164
165

PUSH
PUSH
PUSH
PUSH
PUSH

166

PUSH

167
16B
169
170
171
172
173
174
175
176
1(7
178
179
180
181
182
183
184
185
186
1S7
188
189
199
191
192
193
194
195
1%
197
lSS
199
200

1'1011
PUSH
RET

PU5~1

0118
911B
011£
0120
012J
0124
0127
0129
012A
012!:
012~

E8B9FF
Bf1EAFF
B088
A20400
E.E
BAESFF
B006
EE
CD4D
ESBDfF
GF

205
206

MOV
POP
POP
POP
POP
POP
POP

AX
STACK1,AX
ES
OS
01
51
BP
OX

pop

ex

POP
POP

BX
AX
AXTEMP, AX
AX, STACK1
A.'<
AX, AXTEMP

1'1011
i'IO'v'
PUSH
1'10\1
RET

; POP CALL RETURN ADIII1Gll 4

; 82(9 DATA
i CHARA(;T[R "4·
; 1mER DELAY FOR ill ON 'liME
; ROUTINE TO RESTORE PROCESSOR SlATIJS
; RETlJRN FROM INlERRlJ!T
~

INTERRUPT 77. TIMER llELAY. SOFTWARE CONTROLLED
IIITR77: I'IOV

t10V
OOT
t10V
OUT
IRET

DX,IlFF9AH

; LOfb COUNTER 1 8'253 11 (259 I'ISEC)

ftL.25H

iL!'£!

DX,fIl.

; IISB

Al.08H
DX,fIl.

; R[I URN FROI'I INTERRUPT

2-154

12150()"()()1

APPENDIX B (continued)
1ICS-86 ASSEIfJlEl1

TCI59A

PfI(£

LINE

LOG OBJ

6

SOlRCE

270
271

m

27~

CODE

,

274
275

11000

ENDS;

END

START

SYI1BOL TABLE U!.oTlNU

---- ---- ------

NftME

TYPE

VALUE ATTRIBUTES

??SEG .
AXTEMP
CODE
DATA
DIGIT .
DUIt1Y .
EXTFA
INTR7"Z
INTP.7J
INm4
INTR75
INTI176.
INTR77
RESTOR

SI:.GI1ENT
V WOI1[l
SEGMENT
SEGI1ENT
II BYTE
L NEAP,
SEGMENT
L NEAR
L NEAR
L NUIF
L NEAR
L NEAR
L NEAR
L NEfIF
L NEilR
L NEAA
L NEAF
L NEAll
L NEAR
II IoIOIi'D
L NEAR
V WOf1[I
II IO[l
II WOR{)
II IoIORf)

SIZE=98OOH PARA PUBLIC
0002H DATA
SIZE=0182H PAPA
SIZE=01.105H P~A
0004H [lATA
00D2H CODE
SIZE=013SH PARA
0104H COLlE
9118H CODE
913ati CODE
9148H CODE
9160H CODE
9178H CODE

SAVE.
SET531
SET532.
SET59A

SET79
STACK1
START.
TP72CS
TP72IP
TP73CS.
Tf'73IP.
TP74CS
TP74IP.
TP75CS
TP75IP.
TP76CS.
TP76IP
, TP77CS.
TP77IP
TYPES
WAIT79

II WORD
II WORD
II WORD

II WORD
II WOFD
II WORD
II IoIORI)
V IoIORI)
L NEAR
L NEAR

09ECH CODE
0904H CODE
095I*l CODE
09781-1 CODE
0991"H CODE
1l9B1H CODE
1l8e9H

Il8e9H

~

0122H EXTRH
9120H EXTRA
0126H EXTRA
9124H EXTRA
012AH EXTRA
0128H EXTRA
912EH EXIRA
912CH EXTRA
01::;2H EXTRA
9130H EXTRA
0136H EXTRA
0134H EXTRA

0012H CODE
9087H CODE

f:SSEI'IIlL Y COMPLETE. NO EFRORS FruND

~
2~155

121500-001

iAPX 86, 88, ·186, 188
Microprocessors

3

iAPX 86/10
16-81T HMOS MICROPROCESSOR
8086/8086-2/8086-1

Arithmetic in Binary or Decimal
Including Multiply and Divide

• Direct Addressing Capability 1
M Byte of Memory
• Architecture Designed for Powerful
Assembly Language and Efficient
High Level Languages.
• 14 Word, by 16·Bit Register Set with
Symmetrical Operations

• Range of Clock Rates:
5 M Hz for 8086,
8 M Hz for 8086·2,
10 MHz for 8086·1
• MULTIBUSTM System Compatible
Interface

• 24 Operand Addressing Modes

• Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range

• Bit, Byte, Word, and Block Operation.s
• 8 and 16·Bit Signed and Unsigned

The Intel iAPX 86/10 high performance 16-bit CPU is available in three clock rates: 5, 8 and 10 MHz. The CPU is
implemented in N-Channel, depletion load, silicon gate technology (HMOS), and packaged in a 40-pin CerDIP package.
The iAPX 86/10 operates in both single processor and multiple processor configurations to achieve high performance
levels.

BUS INTERFACE UNIT

r
,

REGISTER FILE

-

-

,

RELOCATION
REGISTER FILE

DATA
POINTER AND
INDEX REGS
f8 WORDS}

GND

Vee

A014

A015
A16fS3

A012

A17/S4

AD11

A18/55

AD10

A19fS6

AD9

SHE/S7

ADS

MNIMX

AD7

RO

AD6

ROIGTO (HOLD)

FLAGS

6 BYTE
INSTRUCTION

ADS

RafGl1 (HlDA)

AD.

LOCK

(WIl)

AD3

52

(MliO)

AD2

Si

(DTlR)

AD1

So

(DEN)

ADO

aso

(ALE)

NMI

aS1

(lNTA)

QUEUE

ffi'i_r----......;:"""----,

INTR

INT
NMI- -

2

CONTROL & TIMING

HOlD-

050 aS1

-r---.---.-r .......,~

HlDA---..... . .

i

eLK

I
ReSET

READY

I

JetNIM);

TEST

elK

READY

GND

RESET

40 LEAD

OND

V"
Figure 2. iAPX 86/10 Pin Configuration

Figure 1_ iAPX 86/10 CPU Block Diagram

3-1

iAPX 86/10

Table 1. Pin Description

(

The following pin function descriptions life for iAPX 1J6 systems In either minimum or maximum mode. The "Local
Bus" In these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to additional
bus' buffers).
Symbol

Pin No.

Type

AD15·ADo

2·16,39

I/O

35·38

0

A1g1S6,
A1a1S5,
A17/S 4,
A 16/S 3

Name and Function
Address Data Bus: These lines constitute the time multiplexed memoryllO address (T 1)
and data (T2, T3, Tw, T4) bus. Ao is analogous to BHE for the lower byte of the data bus,
pins DrDo. It is lOW during T1 when a byte is to be transferred on the lower portion of
the bus in memory or I/O operations. Eight·bit oriented devices tied to the IQwer half
would normally use Ao to condition chip select functions. (See BHE.) These lines are
active HIGH and float to 3·state OFF during interrupt acknowledge and local bus "hold
,
acknowledge."
Address/Status: Durir:lg T, these are the four most sign ificant address lines for memory operations. During I/O
operations these lines are lOW. During memory and I/O
operations, . status information is available on these
,Iihes during T2, T3> Tw, and T4. The status of the interrupt
enable FLAG bit (S5l is updated at the beginning of each
ClK cycle. A17/S4 and A,e/S3 are encoded as shown.
This information indicates which relocation register is
presently being used for data accessing.

A17/S4

A,eis3

Characteristics

o (LOW)

0

,
,

Alternate Data

0
'(HIGH)

0

Code or None
Data

,

86

IS

Stack

0

(LOW)

These lines float to 3·state OFF during local bus "hold
acknowledge."
BHE/S 7

34

0

Bus High Enable/Status: During T, the bus high enable
signal (BHE) should be used to enable data onto the
most significant,half cif the data bus, pins 0,5-08' Eightbit oriented devices tied to the upper half of the bus
would normally use BHE to condition chip select func'
tions. BHE'is lOW during T, for read, write, and interrupt acknowledge cycles when a byte is to be transfer·
red on the high portilZln of the bus. The S7 status informa·
tion is available during T2, T3, and T4. The signal is active
lOW, and floats to 3·state OFF in "hold." It is lOW duro
ing T1 for the first interrupt acknowledge cycle.

iiHE

Ao

0

0

0

,
,

,

0

,.

Characteristics
Whole word
Upper byte froml
to odd address
Lower byte froml
to even address
None

RD

32

0

READY

22

I

READY: is the acknowtedgement from the addressed memory or I/O device that it will
complete the data transfer. The READY signal from memory/IO is synchronized by the
8284A Clock Generator to form READY. This signal is active HIGH. The 8086 READY input is not synchronized. Correct operation is not guaranteed if the setup and hold
times are not met.

INTR

18

I

Interrupt Request: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt
acknowfedge operation. A subroutine is vectored to via an interrupt vector lookup table
located in system memory. It can be. internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.

TEST

23

I

TEST: input is examined by the "lIIIait" instruction. If the TEST input is lOW execution
continues, otherwise the processor waits in an "Idle" state. This input is synch~onized
internally during each clock cycle on the leading edge of ClK.

Read: Read strobe indicates that the processor is performing a memory of I/O read cycle, depending on the state =

T

DE
8286
DATA

TRANSCEIVER

(21

~

BHEJliol1
CSOH

CSOL

WE 00

2142 RAM (4)

J11f J1
CE

DE

2716·2 PROM (2)

es

AD Wft

Mes-ao
PERIPHERAL

(21
1Kxs

(21
1Kx8

2K ... 81 2K" 8

Figure 4b. Maximum Mode iAPX 86/10 Typical Configuration
3-7

iAPX 86/10

Status bits S3 through S7 are multiplexed with high·
order address bits and the BHE Signal, and are therefore
valid during ;-2 through T4. S3 and S4 indicate which
segment register (see Instruction Set description) was
used for this bus cycle in forming the address, accord·
ing' to the following table:

BUS OPERATION
The 86/10 has a combined address and data bus commonly referred to as a time multiplexed bus. This tech·
nique provides the most efficient use of pins on the
processor while permitting the use of a standard 40·lead
package. T~is "local bus" can be buffered directly and
us~d throughout the system with ad,dress latching pro·
vided on memory and I/O modules. In addition, the bus
can also be demultiplexed at the processor with a Single
set of address latches if a standard non·multiplexed bus
is desired for the system.

S4

o (LOW)
0
1 (HIGH)
1

Each processor bus cycle consists of at'least four elK
cycles. These are referred to as T 1, T2, T3 and T4 (see
Figure 5). The address is emitted from 'the processor
during T 1 and data transfer occurs on the bus during T3
and T 4' T2 is used primarily for changing the direction of
!tie bus during read operations. In the event that a "NOT
READY" indication is given by the addressed device,
"Wait" states (T w) are inserted between T3 and T4. Each
inserted "Wait" state is of the same duration as a elK
cycle. Periods can occur between 8086 bus cycles.
These are referred to as "Idle" states (T I) or inactive elK
cycles. The processor uses these cycles for internal
housekeeping.
During T1 of any bus cycle the ALE (Address latch
Enable) Signal is emitted (by either the processor or the
8288 bus controller, depending on the MN/MX strap). At
the trailing edge of this pulse, a valid address and cer·
tain status information for the cycle may be latched.
Status bits So, S1, and S2 are used, in maximum mode,
by the bus controller to identify the type of bus transac·
tion according to the following table:
S2

S;

SO

o (LOW)
0
0
0
1 (HIGH)
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

CHARACTERISTICS
Interrupt Acknowledge
Read I/O
WriteI/O
Halt
Instruction Fetch
Read Data from Memory
Write Data to Memory
Passive (no bus cycle)

S3
0

1
0
1

CHARACTERISTICS
Alternate Data (extra segment)
Stack
Code or None
Data

S5 is a reflection of the PSW interrupt enable bit. S6=Oand
S7 is a spare status bit.
.

110 ADDRESSING
In the 86/10, I/O operations can address up to a maximum
of 64K I/O byte registers or 32K I/O word registers. The
I/O address appears in the same format as the memory
address on' bus lines A1s-A o. The address lines A19 -A 16
are zero in I/O operations. The variable I/O instructions
which use register OX as a pointer have full address capability while the direct I/O instructions directly address one
or two of the 256 I/O byte locations in page 0 of the I/O
address space.
. I/O ports are addressed in the same manner as memory
locations. Even addressed bytes are transferred on the
0rOo bus lines and odd addressed bytes on 015-08'
Care must be taken to assure that each register within
an 8·bit peripheral located on the lower portion of the
bus be addressed as even.

3-8

IAPX 86/10

, '0------~

(4

+ NWAlT) '" Tey

n

n

______

-

...'------

-<'~,

~

~

(4

+ NwAITJ =Tcy

n

n

------_,'

_

~

eLK

\
ADDRI

$7-53

STATUS

-----8___

ADDRIDATA

D_A_TA_O_UT_ID_15_-D_O_'- - - - ) - -

READY

READY

READY

WAIT

WAIT

DTiR

.....-- MEMORY ACCESS TIME-+-

Figure 5. Basic System Timing

3-9

~

inter

iAPX86/10

EXTERNAL INTERFACE

sequence, which is used to "vector" through the ap·
propriate element to the new interrupt service program
location.

PROCESSOR RESET AND INITIALIZATION

NON·MASKABLE INTERRUPT (NMI)

Processor initialization or start up is accomplished with
activation (HIGH) of the RESET pin. The 8086 RESET is
required to be HIGH for greater than 4 ClK cycles. The
8086 will terminate operations on the high-going edge of
RESET and will remain dormant as long as RESET is
HIGH. The low-going transition of RESET triggers an
internal reset sequence for approximately 10 ClK cycles.
After this interval the 8086 operates normally beginning.
with the instruction in absolute location FFFFOH (see
Figure 3Bl. The details of ihis operation are specified in the
Instruction Set description of the MCS-86 Family User's
Manual. The RESET input is internally synchronized to the
processor clock. At initialization the HIGH-to-LOW transition of RESET must occur no sooner than 50 /J-s after
power-up, to allow complete initialization of the 8086.

The processor provides a single non·maskable interrupt
pin (NMI) which has higher priority than the maskable in·
terrupt request pin (INTR). A typical use would be to ac·
tivate a power failure routine. The NMI Js edge-triggered
on a lOW-to-HIGH transition. The activation of this pin
causes a type 2 interrupt. (See Instruction Set description.)
NMI is required to have a duration in the HIGH state of
greater than two ClK cycles, but is not required to be
synchronized to the clock. Any high-going transition of
NMI is latched on-chip and will be serviced at the end of
the current instruction or between whole moves of a
block-type instruction. Worst case' response to NMI
would be for multiply, divide, and variable shift instructions. There is no specification on the occurrence of the
low-going edge; it may occur before, during, or after the
servicing of NMI. Another high-going. edge triggers
another response if it occurs after the start of the NMI
procedure. The signal must be free of logical spikes in
general and be free of bounces on the low-going edge to
avoid triggering extraneous responses.

NMI may not be asserted prior to the 2nd CLK cycle following the end of RESET.

INTERRUPT OPERATIONS
Interrupt operations lall into two classes; software or
hardware initiated. The software initiated interrupts and
software aspects of hardware interrupts are specified in
the Instruction Set description. Hardware interrupts can
be classified as non·maskable or maskable.

MASKABLEINTERRUPTPNT~

The 86/10 provides a single interrupt request input (INTR)
which can be masked internally by software with the
resetting of the interrupt enable FLAG status bit. The
interrupt request Signal is level triggered. It is internally
synchronized during each clock cycle on the high-going
edge of ClK . .To be responded to, INTR must be present
(HIGH) during the clock period preceding the end of the
current instruction or the end of a whole move for a
block-type instruction. During the interrupt response
sequence further interrupts are disabled. The enable bit
is reset as part of the response to any interrupt (INTR,
NMI, software interrupt or Single-step), although the

Interrupts result in a transfer of control to a new pro·
gram location. A 256·element table containing address
pointers to the interrupt service program locations
resides in absolute locations 0 through 3FFH (see
Figure 3b), which are reserved for this purpose. Each
element in the table is 4 bytes in size and corresponds
to an interrupt "type". An interrupting device supplies
an 8·bit type number, during the interrupt acknowledge

I
A,E

T,

TJ

T4

\

\

INTA

~FlOAT

n'----

I TI I

J\\.........------t!

[oCR

ADo-AD,s

T2

! I

( 1

rr'

I I
i I

T,

I

T,

/
~

\
\ >-

Figure 6. Interrupt Acknowledge Sequence
3-10

TYPE VECTOR

iAPX 86/10
to become active. It must remai~ active for at least 5
CLK cycles. The WAIT instruction is re·executed
repeatedly until that time. This .activity does not consume bus cycles. The processor remains in an idle state
while waiting. All 8086 drivers go to 3·state OFF if bus
"Hold"is entered. If interrupts are enabled, they may
occur while the processor is waiting. When this occurs
the processor fetches the WAIT instruction one extra
time, processes the interrupt, and then re·fetches and
re·executes the WAIT instruction upon returning from
the interrupt.
.

FLAGS register which is automatically pushed onto the
stack reflects the state of the processor prior to the
interrupt. Until the old FLAGS register is restored the
enable bit will be zero unless specifically set by an
instruction.
During the response sequence (figure 6) the processor
executes two successive (back-to-back) interrupt
acknowledge cycles. The 8086 emits the LOCK signal
from T2 of the first bus cycle until T2 of the second. A
local bus "hold" request will not be honored until the
end of the second bus cycle. In the second bus cycle a
byte is fetched from the external interrupt system (e.g.,
8259A PIC) which identifies the source (type) of the
interrupt. This byte is multiplied by four and used as a
pointer into the interrupt vector lookup table. An INTR
signal left HIGH will be continually responded to within
the limitations of the enable bit and sample period. The
INTERRUPT RETURN instruction includes a FLAGS pop
which returns the status of the original interrupt enable
bit when it restores the FLAGS.

BASIC SYSTEM TIMING
Typical system configurations for the processor
operating in minimum mode and in maximum mode are
shown in Figures 4a and 4b, respectively. In minimum
mode, the MN/MX pin is strapped to Vce and the proc·
essor emits bus control signals in a manner similar to
the 8085. In maximum mode, the MN/MX pin is strapped
to Vss and the processor emits coded status information which the 8288 bus controller uses to generate
MULTIBUS compatible bus control signals. Figure 5 il·
lustrates the signal timing relationships.

HALT
When a software "HALT" instruction is executed the
p~ocessor indicates that it is entering the "HALT" state
in one of two ways depending upon which mode is
strapped. In minimum mode, the processor issues one
ALE with no qualifying bus control signals. In Maximum
Mode, the processor issues appropriate HALT status on
828 180 and the 8288 bus controller issues one ALE. The
8086 will not leave the "HALT" state when a local bus
"hold" is entered while in "HALT". In this case, the
processor reissues the HALT indicator. An interrupt
request or RESET will force the 8086 out of the "HALT"
state.

AX

AH

AL

ACCUMULATOR

BX

BH

BL

BASE

CX

CH

CL

COUNT

OX

DH

DL

DATA

~~

READ/MODIFY/WRITE (SEMAPHORE)
OPERATIONS VIA LOCK

I

The LOCK status information is provided by the proc·
essor when directly consecutive bus cycles are required
during the execution of an instruction. This provides the
processor with the capability of performing read/modify/
write operations on memory (via the Exchange Register
With Memory instruction, for example) without the
,possibility of another system bus master receiving
intervening memory cycles. This is useful in multi·
processor system configurations to accomplish "test
and set lock" operations. The LOCK signal is activated
(forced LOW) in the clock cycle following the one in
which the software "LOCK" prefix instruction is
decoded by the EU. It is deactivated at the end of the
last bus cycle of the instruction following the "LOCK"
prefix instruction. While LOCK is active a request on a
RQ/GT pin will be recorded and then honored at the end
of the LOCK.

BASE POINTER

51

SOURCE INDEX

DI

DESTINATION INDEX

IP
FlAGSH

I
C5

-

STACK POINTER

BP

FLAGSL

I

INSTRUCTION POINTER
STATUS FlAGS

CODE SEGMENT

D5

DATA SEGMENT

55

STACK SEGMENT

E5

EXTRA SEGMENT

Figure 7. iAPX 86/10 Register Model

SYSTEM TIMING -

MINIMUM SYSTEM

The read cycle begins in T1 with the assertion of the
Address Latch Enable (ALE) signal. The trailing (low·
going) edge of this signal is used to latch the address
information, which is valid on the local bus at this time,
into the 8282/8283 latch. The BHE and Ao signals
address the low, high, or both bytes. From T1 to T4 the
M/iO signal indicates a memory or I/O operation. At T2
the address is removed from the local bus and the bus
goes to a high impedance state. The read control signal
is also ass~rted at T2. The rllad (RD) signal causes the
addressed device to enable its data bus drivers to the
local bus. Some time later valid data will be available on
the bus and the addressed device will drive the READY
line HIGH. When the processor returns the read signal

EXTERNAL SYNCHRONIZATION VIA TEST
As an alternative to the interrupts and general I/O
capabilities, 'the 8086 provides a single software·
testable input known as the TEST signal. At any time th.e
program may execute a WAIT instruction. If at that time
the TEST signal is inactive (HIGH), program execution
becomes suspended while the processor waits for TEST

3-11

intJ

iAPX 86/10

to a HIGH level, the addressed device ,will again 3-state
its bus drivers. If a transceiver (8286/8287) is required to
buffer the 8086 local bus, signals oTIA' and DEN are provided by the 8086.
'
,
A write cycle also begins with the assertion of Al.;E and
the emission of thel address. The M/iO signal is again
asserted to indicate a memory or 110 write operation. In
the T2 immediately following the address emission the
processor emits the data to be writtell into the
addressed location. This data remains valid until the
middle of T4' During T2, T3, and Tw the processor asserts
the write control signal. The write (WR) signal becomes
active at the beginning of T2 as opposed to the read
which is delayed somewhat into T2 to provide time for
the bus to float.
The BHE and Ao signals are used to select the proper
byte(s) of the memoryllO word to be read or written
according to the following table:

BHE

AO

0
0

0
1

1

0

1

1

CHARACTERISTICS
Whole word
Upper byte froml
to odd address
Lower byte froml
to even address
None

r

1/0 ports are addressed in the same manner as memory
location. Even addressed bytes are transferred on the
07-00 bus lines and odd addresse~ bytes on 015-08'
The basic difference between the interrupt acknowledge cycle and a read cycle is that the interrupt
acknowledge signal (INTA) is asserted In place of the

read (!W) signal and the address bus is floated. (See
Figure 6.) In the second of two successive INTA cycles,
a byte of Information is read from bus lines 07-00 as
supplied by the interrupt system logic (i.e., 8259A Priority Interrupt Controller). This byte identifies the source
(type) of the interrupt. It is multiplied by four and used
as a pointer into an interrupt vector lookup table, as
described earlier.

BUS TIMING-MEDIUM SIZE SYSTEMS
For medium size systems the MN/MX pin is connected to
Vss and the 8288 Bus Controller is added to the system as
well as an 828218283 latch for latching the system address,
and a 8286/8287 transceiver to allow for bus loading
greater than the 8086 is capable of handling. Signals ALE,
DEN, and OT/R are generated by the 8288 instead of the'
processor in this configuration although their timing remains relatively the same. The 8086 status outputs (52 ,51 ,
and So), provide type-of-cycle information and become
, 8288 inputs. This bus cycle information specifies read
(code, data, or 1/0), write (data or I/0h.interrupt acknowledge, or software halt. The 8288 thus issues control
signals specifying memory read or write, I/O read or write,
or interrupt acknowledge. The 8288 provides two types of
write strobes, normal and advanced, to be applied as required. The normal write strobes have data valid at the
leading edge of write. The advanced' write strobes have
the same timing as read strobes, and hence data isn't valid
at the leading edge of write. The 8286/~287 trl!nsceiv~
receives the usual T and OE inputs from the 8288's OT/R
and DEN.
The pOinter into the interrupt vector table, which is
passed during the second INTA cycle, can derive from
an 8259A located on eitlier the local bus or the -system
bus. If the master 8259A Priority Interrupt Controller is
pOSitioned on the local bus, a TTL gate is required to
disable the 8286/8287 transceiver when reading from the
master 8259A during the interrupt acknowledge
sequence and software "poll".

3-12

..

iAPX 86/10
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ......... O·C to 70·C
Storage Temperature ............. - 65·C to + 150·C
Voltage on Any Pin with
Respect to Ground .................. - 1.0 to + 7V
Power Dissipation ........................ 2.5 Watt

D_C. CHARACTERISTICS

Symbol

"NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

(8086: TA = O°C to 70°C. Vcc = 5V ± 10%)
(8086-1: TA = O°C to 70°C. Vcc = 5V ± 5%)
(8086-2: TA = O°C to 70°C. Vcc = 5V ± 5%)

Parameter

Min.

Test Conditions

Max.

Units

+0.8

V

Vce+ 0.5

V

0.45

V

IOl=2.5 mA

V

10H= -400,..A

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

Icc

Power Supply Current: 8086
8086-1
8086-2

340
360
350

mA

III

Input Leakage Current

±10

IJA

OV "" VIN "" Vce

ILO

Output Leakage Current

±10

IJA

0.45V " VOUT " Vee

Vel

Clock Input Low Voltage

-0.5

+0.6

V

VeH

Clock Input High Voltage

3.9

Vee + 1.0

V

C IN

Capacitance of Input Buffer
(All input except
ADo - AD 15 • RQ/GT)

15

pF

fc= 1 MHz

C IO

Capacitance of 1/0 Buffer
(AD o -AD 15• RQ/GT)

15

pF

fc= 1 MHz

Vil

2.4

Note. 1 V'L tested with MN/MX Pin = av.
2. V,H tested with M N/M X Pi n = 5V
MN/MX Pin is a Strap Pin

3-13

T A= 25°C

iAPX 86/10

A.C. CHARACTERISTICS

(8086: TA = ooe to 70oe. Vcc = 5V
(8086-1: TA = ooe to 70oe. Vcc = 5V
(8086-2: TA" = ooe to 70oe. Vcc = 5V

:!:
:!:
:!:

10%)
5%)
5%)

MINIMUM COMPLEXITY SYSTEM
TIMING REQUIREMENTS
Symbol

Parameter

8086

8086·1 (Preliminary)

8086·2

Units

TJlst
Conditions

Min.

Max.

Min.

Max.

Min.

Max.

TCLCL

CLK Cycle Period

200

500

100

500

125

500

TCLCH

CLKLowTime

118

53

68

TCHCL

CLK High Time

69

39

44

TCH1CH2

CLK Rise Time

10

10

10

ns

From 1.0Vto
3.5V

TCL2CL1

ClK Fall Time

10

10

10

ns

From 3.5Vto
1.0V

ns
ns
ns

TDVeL

Data

30

5

20

TCLDX

Data In Hold Time

10

10

10

ns

TR1VCL

ROY Setup Time
Into 8284A (See
Notes 1. 2)

35

35

35

ns

TCLR1X

ROY Hold Time
into 8284A (See
Notes 1. 2)

0

0

0

ns

TRYHCH

READY Setup
Time Into 8086

118

53

68

ns

TCHRYX

READY Hold Time
into 8086

30

20

20

ns

TRYLCl

READY Inactive to
eLK (See Note 3)

-8

-10

-8

ns

~

In

Setup Time

ns

THVeH

HOLD Setup Time

35

20

20

ns

TINVCH

INTR. NMI. TEST
Setup Time (See
Note 2)

30

15

15

ns

TILIH

Input Rise Time
(Except ClK)

20

20

20

ns

From O.8Vto
2.0V

TIHll

Input Fall Time
(Except elK)

12

12

12

ns

From 2.0Vto
0.8V

3~14

iAPX 86/10
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Symbol

Parameter

8086-1 (Preliminary)

8086

8086-2

Units

Min.

Max.

Min.

Max.

Min.

Max.

TCLAV

Address Valid Delay

10

110

10

5ll

10

60

TCLAX

Address Hold Time

10

TCLAZ

Address Float
Delay

TCLAX

10
80

40

ns
50

ns

TlHll

ALE Width
ALE Active Delay

80

40

50

ns

TCHll

ALE Inactive Delay

85

45

55

ns

TlLAX

Address Hold Time
to ALE Inactive

TClDV

Data Valid Delay

10

TCHDX

Data Hold Time

10

10

10

ns

TWHDX

Data Hold Time
AfterWR

TClCH-30

TClCH-25

TClCH-30

ns

Control Active

TClCH-l0

TCLAX

ns

TCllH

, TCVCTV

TClCH-20

10

10

TCHCl-l0

TClCH-l0

TCHCl-l0
110

10

ns

TCHCl-l0
50

10

Test
Conditions

ns
60

ns

10

110

10

50

10

70

ns

10

110

10

45

10

60

ns

10

110

10

50

10

70

ns

·Cl ~ 20-100 pF
for all 8086 Outputs (In addi-,
tlon to 8086 selfload)

Delay 1
TCHCTV

Control Active

i

Delay 2
TCVCTX

Control Inactive

Delay
TAZRl •

Address Float to
READ Active

TClRl

RD Active Delay

10

165

10

70

10

100

TClRH

RD Inactive Delay

10

150

10

,60

10

80

TRHAV

RD Inactive to Next

TClHAV

HlDA Valid Delay

TRlRH

RDWidth

2TClCl-75

2TClCl-40

2TClCl-50

ns

TWlWH

WRWidth

2TClCl-60

2TClCl-35

2TClCl-40

ns

TClCH-60

TClCH-35

TClCH-40

ns

0

0

TClCl-45

ns

0

TClCl-35

TClCl-40

ns
ns
ns

Address Active

TAVAl

Address Valid to
• ALE low

10

160

10

60

10

100

ns

TOlOH

Output Rise Time

20

20

20

ns

From 0,8Vto
2.0V

TOHOl

Output Fall Time

12

12

12

ns

From 2,OVto
0,8V

NOTES:
1. Signal at 8284A shown for reference only,
2, Setup requirement for asynchronous signal only to guarantee recognition at next ClK,
3, Applies only to T2 state, (8 ns into T3),

3-15

inter

IAPX 86/10

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

INPUT/OUTPUT

24

~'5_T~STPOINTS_1'5~

DEVICE
UND~R

TEST

i } C L . , 0 0 PF

0.45

-=

A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1" AND 0 45V FOR
A LOGIC O· TIMING MEASUREMENTS ARE MADE AT 1 SV FOR BOTH A
LOGIC 1" AND '0"

CL INCLUDES JIG CAPACITANCE

WAVEFORMS
MIN,MUM MODE

T1

T2

T3

T.

Tw

VCHv----\ -TClC~ TCH1CH2, t--=t.='vJ~

CLK (8284A Oulpul)

"de
-

f

i\--.-J

"----I
TCHCTV

~TCHCl

"---Jr\.._TClCH-

M/KI

-

TClAY-

rCLDV fo-'
TClAXI-

TCHDX-

BHE, A19-A18
TCllHALE

f-

87-53

TlHll-=::

I

I

.I-TllAX

r-I

-

TJAl
TCHll-1

RDY (828411 Inpu~
SEE NOlE4

V,H ,....,

"
V'L~

Dc-

-TR1VCl

'R}\\\~~~"\\ ' \,,"'\~~:'

"

TRYlCl-

\

-

---

\

I-iClR1X

~

- h

READY (8088 Inpul)

f

-

1

TClAV-

lAVAL

-

_

-

TLLAX-

TRYHCH-

1--1
I:~ClAZ

TClAX

TAZRlRD
R~AD

CYCLE

=~TCHCTV

(NOTE 1)

!WR, INTA = VOH)

-

~TDVCl- -TClDXII

A1S-ADo

AD,.-ADo

-TCHRYX

DATA IN

~rr

TCLRH-

~
TRLRH

TClRl

DT/R

TCVCTV-

3-16

f

FlO~~

1- f-TRHAV

1

TCVCTX-

I

-TCHCTV

inter

iAPX86/10

WAVEFORMS (Continued)
MINIMUM MODE (Continued)
T,

ClK (8284A OulpuQ

MfiO

I

ALE

r--

WRITE CYCLE

Q !i 

SERIAL
UO

TERMINAL

A1

A2

I

INTO

DISK
INTERFACE
INT11--------------------I HARDWARE

~8
0
DISK

...............

~r-----------------~

DRQOI--------------------I

Figure 39. TyplcallAPX 186 Computer

3-60

210451-1)04

inter

iAPX 186

16 MHz

rD~
Vee

r1

X1

X2
UCS

cs

RD

UF

RES

.I

,----v-'

8282 OR
8283
LATCH

6E

STB

OE

STB

•

ALE
LCS

RESET
ROM

-:?

ns

r:=-

LOW
RAM

CS

BHE
WR

/\

b

ADO-AD19

8282 OR
8283
LATCH
STB

ADDRE$S
BUS

6E

~~6E
STB

80186

t

NMI
HOLD

~

~-----"-:;

,

t

8286 OR
8287
TRANSCEIVER

~

r

;> DATA BUS

~~-

t

DT/R
CLK
ALE

CLKOUT

SO-S2

,-1-

~

8288
SO-52 BUS
--./ CONTROLLER

---

CEN
lOB

MULTI
MAST ER
SYST EM
BUS

> BUS CONTROL
COMMANDS

AEN

1

-:?

[

--=>
PCSO
PCS1
LOCK
SRDY
ARDY

SO-S2
CLK

---r

AEN
8289

AR~~iER

MULTIBUS
ARBITRATION

SYSB/RESB
lOB

~
I

LOCK

RESB

L+ 5v

'-.J.
XACK

Figure 40. Typical iAPX 186 Multi-Master Bus Interface

3-61

210451~004

inter

iAPX 186

PACKAGE

NOTE: The lOT 3M Textool 68-pin JEOEC Socket
is required for 12 1CETM-186 operation. See Figure
42 for details.

The 80186 is housed in a 68-pin, lead less JEOEC type
A hermetic chip carrier. Figure 41 illustrates the
package dimensions.

106

m

.066

:o5ii

[

.050 BSC
TYP

t .LD
.039 TYP (68) PLCS
[m

, 1-lc.006

,

[

.055

:li45

Figure 41. 80186 JEDEC Type A Package

3-62

210451-004

intJ

iAPX 186

-

268-5400-50

268-5400-00

..

,,--k

_

--~l+;-PC OARD PATTE:..:...R_N__
B

}~~mr

~~~r:~~~ \ \ \++I+.

t:J+ ~

• +;*-

SOCKET

ORIENTATION

/1.1

-I~-'~SO

I

.015

-i

Ii

b....i

• +

'

I

•

PIN CLR HOlE-¥+I

'\ '\ '\;+=
~ >>~).m,.. .1.l1l!.
ii.~'i:i'. 800fl ----j
--l t+

L

~'"')o

G.

FRONT

I

1.00

ALUMINUM
(HEATSINK PROVISIO

.

~~i~~~~T ~- ,-

TO SCALE

FRONT

P'N NOl

~ FOR>g~~)~a._'i
12~4)
DEVICEPADS_~71('
~ ~TYP
SHOWN FOR
!+ 7 ,
¥~
++ •• -.i.
(2.54)
~
~
CONTACT
t'+'"

CKEr ORIENTATION PIN
I

'i-•

~I~ OPTIONAL)
CLOSED ~

\

TVP

(2.54)

OPEN

(20.32)
UM TVP 4 PLCS
.020:=1" 8 SPCS@.100TOLNON Ace
(0.51)
(2.54)
CONTACT TAIL
(0.30)

n are for reference only. Please consult 3M Textool for comp lete information on the eocket.

NOTE, Ph....a' d.mens.on. show

1·~==__----::==:~~;::d~C;h~IP~

-

(C::aarrrlier Socket

Figure 42. Textool 68 Lea

3-63

210451-004

iAPX 186
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature under Bias ..... O°C to 70°C
Storage Temperature ........... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .............. -1.0V to +7V
Power Dissipation ......................... 3 Watt

'NOTICE: Stresses above those listed under
"Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximUl:n rating conditions
for extended periods may affect device reliability.

D.C. CHARACTERISTICS (TA = 0°-70°C, Vee = 5V ±10%)
Applicable to 80186 (8 MHz) and 80186·6 (6 MHz) ,
Symbol

Min.

Max.

Units

v"

Input Low Voltage

0.5

+ 08

Volts

V,H

Input High Voltage
(All except Xl and (RES)

2.0

Vee + 0.5

Volts

V,H1

Input High Voltage (RES)

3.0

Vee + 0.5

Volts

Val

Output Low Voltage

0.45

Volts

r--V

la ~ 2.5 mA for OO·~
"
la ~ 2.0 mA for all other outputs

Output High Voltage

Volts

loa ~ -400 ~A

OH

Parameter

2.4

Test Conditions

Icc

Power Supply Current

550
450

rnA

Max measured at TA
TA

III

Input Leakage Current

±10

~A

OV

0.45V

V,N

<

<

ILO

Output Leakage Current

±10

~A

Clock Output Low

06

Volts

la = 4.0 mA

VCHO

Clock Output High

Volts

loa

Veu
VCHI

Clock Input Low Voltage

-0.5

Clock Input High Voltage

3.9

40
0.6

Volts

Vce+ 1.O

Volts

G'N

Input Capacitance

10

pF

G ,O

I/O Capacitance

20

pF

~

VOUT

-200

O°C

lO°C

Vee

Vela

<

~
~

<

Vee

~A

PIN TIMINGS

A.C. CHARACTERISTICS (TA = 0°_70°C, Vee = 5V ± 10%)
80186 Timing Requirements All Timings Measured At 1.5 Volts Unless Otherwise Noted.
Applicable to 80186 (8 MHz) and 80186·6 (6 MHz)
Symbol

Parameter

Min.

Max.

Units

T DVCL

Data in Setup (ND)

20

ns

T CLDX

Data in Hold (AID)

10

ns

TARYHCH

Asynchronous Ready
(AREADY) active setup
time'

20

ns

TARYLCL

AREADY inactive setup
time

35

ns

TCHARYX

AREADY hold time

15

ns

TARYCHL

Asynchronous Ready
inactive hold time
Synchronous Ready
(SREADY) transition setup
time

15

ns

TSRYCL

20

ns

T CLSRY'

SREADY transition hold
time

15

ns

T HVCL

HOLD Setup'

25

ns

Test Conditions

'To guarantee recognition at next clock.

3-64

210451-004

intJ

IAPX 186

80186 Timing Requirements (Continued)
Symbol

Parameter

Min.

T1NVCH

INTR, NMI, TEST, TIMERIN,
Setup'

TINVCL

OROO, OR01, Setup'

Max.

25
25

Units

Test Conditions

ns
ns

'To guarantee recognition at next clock.
80186 Master Interface Timing Rssponsea

80186 (8 MHz)
Symbol
TCLAV

Parameters

Min.

Address Valid Delay

5
10

80188-6 (6 MHz)

Max.
55

Min.

Max.

Units

5

63

ns

TCLAX

Address Hold

TClAZ

Address Aoat Delay

TCHCZ

Command Lines Float Delay

TCHev

Command Lines Valid Delay
(after float)

TLHLL

ALE Width

TCHLH

ALE Active Delay

35

44

ns

TCHLL

ALiE Inactive Delay

35

44

ns

TLLAX

Address Hold to ALE Inactive

TCLOV

Data Valid Delay

10

TCLDOX

Data Hold Time

10

TWHOX

Data Hold after WR

TCVCTV

Control Active Delay 1

10

70

10

87

ns

TCHCTV

Control Active Delay 2

10

55

10

76

ns

TevCTX

Control Inactive Delay

5

55

5

76

ns

TCVOEX

DEN Inactive Delay
(Non-Write Cycle)

10

70

10

87

TAZRL

Address Aoat to RD Acllve

0

TCLRL

RD Active Delay

10

70

10

87

ns

TCLRH

RD Inactive Delay

10

55

10

76

ns

TCLAX

ns

10
35'

TCLAX

45
55
TCLCL-35

44

ns

56

ns

76

ns

TCLCL-35

TCHCL-25

ns

TCHCL-30
44

10

ns
55

10

ns
ns

TCLCL-50

TCLCL-40

ns

ns
ns

0

TRHAV

RD Inactive to Address Active

TCLHA~

HLDA Valid Delay

TCLCL-50

TRLRH

RDWidth

2TcLCL-50

2TCLCL-50

ns

2TcLCL-40

2TCLCL-40

ns

TCLCH-25

TCLCH-45

TCLCL-40
5

5

50

ns
67

ns

TWLWH

WRWidth

TAVAL

Address Valid to ALE Low

TCHSV

Status Active Delay

10

55

10

76

ns

TCLSH

Status Inactive Delay

10

65

10

76

ns

TCLTMV

Timer Output Delay

60

75

ns

TCLRO

Reset Delay

60

75

ns

35

1lIat Condition.
CL - 20-200 pF all outputs

ns

44

100 pF max

ns

TCHQSV

Queue Status Delay

TCHO~

Status Hold Time

10

10

ns

TAVCH

Address Valid to clock high

10

10

ns

80186 Chip-Select Timing Responses
Symbol

Parameter

Min.

TCLCSV

Chip-Select Active Delay

Tcxcsx

Chip-Selct Hold from
Command Inactive

35

TCHCSX

Chip-Select Inactive Delay

'5

Max.

Min.

66

Max.

Units

80

ns
ns

35
35

5

3-65

Test Conditions

47

ns
210451...()()4

intel'

iAPX 186.

A.C. CHARACTERISTICS (Continued)
80186 ClKIN Requirements
80186 (8 MHz)
Symbol

Parameter

80186-6 (6 MHz)

Min.

Max.

Min.

Max.

Units

62.5

250

83

250

ns

Test Conditions

TCKIN

ClKIN Period

TC,KHL

ClKIN Fall Time

10

10

ns

3.5 to 1.0 volts

TCKLH

ClKIN Rise Time

10

10

ns

1.0 to 3.5 volts

TCLC;K

ClKIN'low Time

25

33

ns

1.5 volts

TCHCK

ClKIN High Time

25

33

ns

1.5 volts

80186 ClKOUT Timing (200 pF load)
Symbol

Parameter

TClco

ClKIN to ClKOUT Skew

Min.

Max.

Min.

50
125

167

Units

62.5

ns

500

ns

Test Conditions

TCLCL

ClKOUT Period

TCLCH

ClKOUT low Time

1f, T CLCL-7.5

V,TCLCL-7.5

ns

TCHCL

ClKOUT High Time

V, TCLCL-7.5

1f, T CLCL-7.5

ns

1.5 volts

TCH1CH21 ClKOUT Rise Time
TCL2CLl ' ClKOUT -Fall Time

500

Max.

1.5 volts

15

15

ns

1.0 to 3.5 volts

15

15

ns

3.5 to 1. volts

3-66

210451-004

iAPX 186

WAVEFORMS
MAJOR CYCLE TIMING
T,

T,

CLKOUT
~

T3

Tw

v-t-=n~'A~

VCL~

=-r

f\-----I

1\

I -Tc LAX~ rCLD'

TC i A V -

V

BHE/57 ,
A'9/Ss- A16/S,

"T,.,

.u;-::; f-/,_

r>
~
\

--

~

,"Ii;,

57-53

.,

ALE

' .,

~
./1

~~

'-1 - - - -

I...J~

WRITE CYCLE

~

Tr ;~AZ·_

1:=

-- J

I-

I-

VOH

J

.v.v.n
~_TCLAZ

-+

FLOAT

'I
-=:f-I.I~

INTA CYCLE
DT/R

TCHCTV

\

roon

t

JI~

- ~I
I

RD,~~V9H

A~

NOTE 2

j..

;: ~ ::;~

50FIYOIRE HALT-DTIR ~VOL'
RD, WR, INTA, DEN ~ VO H
PCS,
MC5
LCS,
UCS

1FLOAT

f:J

1

~~

CLDX

1\
V II
1-1

.~.~ -~

tlt1t: - VOL

I--

1-

l-~

AD15-ADo

1-

VTCI:;:;;
1"=.-

IOU·

,,~v~lv-1~ f---+I TLLA:

RQ, INTA,

DT/R

I::

i~5~Ao

AD15-ADo

>--TCHCZ
NOTE 1

--1 - - - -

~~.

TCH

--",~....

-

INval In annA",""
TCLAV_

-

:-

Tr"1

.. _TCLC5V

3-67

TCXCSX-

1-

Jr-

210451-004

intel'

iAPX 186

WAVEFORMS (Continued)
MAJOR CYCLE TIMING (Continued)

BHE/S7,A19/S6-A161S3

r--

AO'5-ADo
READ CYCLE
RD
TCLRL 1-4---+I<-l

OTfil
WR, INTA

=

YOH

PCS,

MCS

----4-..,.

LCS,
UCS

NOTES:
1. FOllowing a Write cycle, the Local Bus is floated by the 80186 only when the
80186 enters a "Hold Acknowledge" state.
2. INTA occurs one clock later in RMX-mode.
3. Status inactive just prior tc? T4

3-68

210451-004

intel'

iAPX 186

WAVEFORMS (Continued)

CLKOUT

----

TCLAV

-

LOCK

CLKOUT

~

INTO-3
TIMERIN

3-69

210451-004

inter

iAPX 186

WAVEFORMS (Continued)
HOLD-HLDA TIMING
T,

T,

T3

CLKOUT

ARDY

TARYLCL-

___

ARDY

CLKOUT

SRDY

T,
CLKOUT

AD1S-ADO - - - - 80186
DEN-----

}---

A19/S6-Al61S3, - - - - RD, WR,
80186
BHE,-----

)---

-

-- ....
__ J

TCHCV_

-- ....
__ J

~

r-TCLAV

80186

80186

DT/R,

52-SO

3-70

210451-004

intel·

iAPX 186

WAVEFORMS (Continued)
TIMER ON 80186

CLKIN

TCKHL

TCH1CH2

~---TCLCH----t-o.".---TCHCL--_,,-

CLKOUT

i-------TCLCL

--------1

I

---./
_TINVCH

TIMERIN

='~rTIMEROUT _ _

~:~~~~~~~~~~~~~~~~~~~~~~~_2_-_6_CL_O_C_KS_ _ _----------f---'~

80186 INSTRUCTION TIMINGS

• All word-data is located on even-address
boundaries.

The following instruction timings represent the minimum execution time in clock cycles for each instruction. The timings given are based on the following
assumptions:

All jumps and calls include the time required to fetch
the opcode of the next instruction at the destination
address.

• The opcode, along with any data or displacement
required for execution of a particular instruction,
has been prefetched and resides in the queue at
the time it is needed,
• No wait states or bus HOLDS occur.

All instructions which involve memory reference can
require one (and in some cases, two) additional
clocks above the minimum timings shown. This is
due to the asynchronous nature of the handshake
between the BIU and the Execution unit.

3-71

inter

iAPX 186

INSTRUCTION SET SUMMARY
FUNCTION

FORMAT

DATA TRANSFER
MOV; Move:
Register to ReglsterlMemory

11 000100w

mod reg

rim

Register/memory to register

11 000101w

mod reg

rim

Immediate to register/memory

11 1 0 0 0 1 1 w

modOOO

rim

Immediate to register

11 01 t w

reg

Clock
Cycles

Comments

8/16-bit
8/16-bit

data

dat.,1 w ~ 1

2/12
2/9
12-13
3-4

datalfw=1

data

Memory to accumulator

11 010000w

addr-Iow

addr-hlgh

9

Accumulator to memory

11 010001w

addr-Iow

addr-hlgh

Register/memory to segment register

11 00 0 1 1 1 0

mod 0 reg

rim

Segment register to register/memory

rim

8
2/9
2/11

11 00 0 1 1 0 0

mod 0 reg

PUSH; Push:
Memory

11 1 1 1 1 1 1 1

mod 1 1 0 rim

Register

10 1 0 1 0

Segment register.

10 0 0 reg 1 1 0

16
10

reg

I

9

'~i~ti!i~:>::/ii:~:;;;" i!.'fi;! ,f::;:f(iI~;;;;.J~;1r;;:Al:;:;:;·l~. .-!lr&C:;;I)·~I):;;"k~!i'~':7'(!~@:r:.,::r,11~:>," :i·.;'I'"l7",·.:'·:o"iIa;C·fa~'~Is""'\.It'·O ,t;.
:'""7"1'

pop; Pop:
Memory

1100011111

Register

10 1 0 1 1

Segment register

1000regllli

reg

20
10
8

modOOO rim

I
(reg ,,01)

.,

.
.'

XCHG ; Exchange:
Reglsterlmemory with register

Register with accumulator

11 00 0 0 1 1 wi
11 00 1 0 reg

IN ; Input trom:
Fixed port

11 1 1 00 lOw

vaflable port

11 1 1 0 1 lOw

OUT; Output to:
Fixed port

11 1 1 001 1 w

vaflable port

11 1101 11 w

XLAT ~ Translate byte to AL

11 1 0 1 0 1 1 1

mod reg

I
I

3
port

10
8

port

9
7
11
6
18
18
2
3
9
8

11 00 0 1 1 0 1

mod reg

rim

LOS ~ Load pOinter to DS

11 1 0 0 0 1 0 1

mod reg

rim

(mod ,,'11)

LES ~ Load pOinter to ES

11 1000100

mod reg

rim

(mod

LAHF ~ Load AH with flags

11 00 1 1 1 1 1

SAHF ~ Store AH IOta flags

11 00 1

11 0

PUSHF ~ Push flags

11 00 1

10 0

POPF ~ Pop flags

11 00 1

10 1

OS

I0 0 1 0 1 1 1 0 I
10 0 1 1 0 1 1 0 I
10 0 1 1 1 1 1 0 I

ES

1001001101

CS

ss

.ii'"

4/17

rim

I

LEA ~ Load EA to register

SEGMENT = Segment Override:

"

~

11)

2'
2
2
2

Shaded areas indicate instructions not available in iAPX 86,88 microsystems.

3-72

210451-004

iAPX 186
INSTRUCTION SET SUMMARY (Continued)

FUNCTION

FORMAT

ARITHMETIC
ADD = Add:
Reg/memory with register to either

10 OOOOOdwl

mod reg

rim

Immediate to register/memory

11 OOOOOswl

modOOO

rim

Immediate to accumulator

10000010wl

data

ADC = Add with carry'
Reg/memory with register to either

10 00 1 0 0 d wi

mod reg

Immediate to register/memory

11 00000 s wi

modOl0 rim

Immediate to accumulator

rim

I
I
I

10001010wl

data

11 111111 wi

modOOO

rim

I

Register

10 1 0 0 0

SUB = Subtract
Reg/memory and register to 8lther

1001010dwi

mod reg

rim

Immediate from register/memory

1100000swi

mod 1 01

rim

Immediate from accumulator

10010110wl

data

I
I
I

SBB = Subtract with borrow:
Reg/memory and register to either

1000110dwi

mod reg

rim

Immediate from register/memory

1100000swi

mod 0 11

rim

Immediate from accumulator

10 00 1 1 lOw

I

data

11 1111 11 wi

Register

10 1 0 0 1

CMP =Compare'
Register/memory With register

10 0 1 1 1 01 w

mod reg

rim

I

Register With register/memory

10 0 1 1 1 00 w

mod reg

rim

Immediate WIth re9l.~ter/memory

1100000sw

mod 111

rim

ImmedIate With accumulator

10 0 1 1 1 lOw

data

NEG = Change sign'

I
I
I

11 11 1 011 w

mod 0 11

AAA=ASCII adJust for add

10 0 1 1 0 1 1 1

DAA = DeCimal adjust for add

10 0 1 0 0 1 1 1

AAS = ASCII adlustfor subtract

10 0 1 1 1 111

DAS = DeCimal adjust for subtract

10 0 1 0 1 1 1 1

MUl = MuJtlply (unsigned)
Register-Byte
Register-Word
Memory-Byte
Memory-Word

11 1 1 1 0 1 1 wi

IMUl = Integer multiply (signed)
Register-Byte
Register-Word
Memory-Byte
Memory-Word

11 1 1 1 0 1 1 wi

~

-"

y

''''''''''",..~

iC,iC'F~'

D!V = DIVide (unsigned)
Register-Byte
Register-Word
Memory-Byte
Memory-Word

·:4

reg

mod 0 0 1 rim

data
datalfw=1

I
I

datalf s w = 01

I
I

datalf s w _. 01

Comments

I

3/10
4/16
3/4

8/16-bit

I

3/10
4/16
3/4

8/16-bit

3/15
3

data
datalf w= 1

I
I
I

DEC =Decrement:
Register/memory

t3lM,\! ,
't

I

data Ifw 1

I
I
I

INC = Increment·
Register/memory

reg

data

Clock
Cycles

data
datalfw-l

I
I

datalfsw-Ol

I
I

datalfsw=OI

r

data

I

I
I

datalfsw-Ol

3/15
3
3/10
3/10
3/10
3/4
3

I

8/16-bit

8
4
7
4

I
mod 1 00

mod 1 01

~htr%:

"Z''"":,; 4]: -.I:: 'Z.'>,T'C' " '
11 1 1 1 0 1 1 wi

8/16-bit

3/4

I

datalfw-l

8/16-bit

3/10
4/16

I

I

rim

3/10
4/16
3/4

I

rim

rim

I

26-28
35-37
32-34
41-43

I

'eJIl!l~r:

'-::";'

mod 11 0 rim

; ,;

25-28
34-37
31-34
40-43
',Ilata
> ..

:.;,;,.r::

,f,'?"'
'0'" :.;:

"',,',:;'.':

I

:"
29
38
35
44

Shaded areas indicate instructions not available in iAPX 86,88 microsystems.
3-73

~;:~~:Z~~;J~

iAPX 186

INSTRUCTION SET SUMMARY (Continued)

FUNCTION

Clock
Cycles

FORMAT

ARITHMETIC (Continued):
11 1 1 1 0 1 1 w

I

IDIV = Integer divide (signed)
Register-Byte
Register-Word
Memory-Byte
Memory-Word
AAM = ASCII adlust lor multiply

mod 111

rim

1110101001000010101

AAD = ASCII adjust lor divide

1110101011000010101

CBW = Convert byte to word

1100110001

CWO = Convert word to double word

11 00 1 1 0 0 1

LOGIC
ShiWRolalelnst,ucltons:
ReglsterlMemory by 1

11 1 0 1 0 0 0 wi· mod Tn rim

ReglsterlMemory by CL

11 1 0 1 0 0 1 w

44-52
53-61
50-58
59-67
19
15
2

I

I

Comments

4

mod TIT rim

I
I

2/15
5+n/17 +n

.. "~~+=Mn-.!1

~~~ilry~rit.
TTT Instruction
o 00
RDL
o 0 1 RDR
o 1 0 RCL
o 1 1 RCR
1 0 0 SHUSAL
10 1
SHR
11 1
SAR
AND=And:
Reg/memory and register to either

mod reg

rim

Immediate to register/memory

10 01000dwi
11000000wl

mod 1 00 rim

data

Immediate to accumulator

10010010wl

data

dat.,lw = 1

TEST = Apd function to flags, no ,esufl:
Register/memory and register
11 000010wl

mod reg

rim

Immediate data and register/memory

11 11 1 011 w

modOOO

rim

Immediate data and accumulator

11 010100wl

OR=Or:
Reg/memory and register to either

1000010dwi

mod reg

rim

Immediate to register/memory

11000000wl

modOOI

rim

Immediate to accumulator

10000110wl

data

I

.ata

datallw=1

dat.,lw= 1

dat.,lw=1

data

data

dat.,lw= 1

dat.,lw=1

3/10
4/16
3/4

8/16-bit

3/10
4/10
3/4

8116-bit

3/10
4/16
3/4

8116-bit

XOR = Exclusive or:
Reg/memory and register to either

10 0 1 1 0 0 d w

Immediate to register/memory

11000000wl

mod 11 0 rim

data

Immediate to accumulator

10011010wl

data

dat.,1 w = 1

NOT = Invert register/memory

11 1 1 1 0 1 1 wi

modOl0

STRING MANIPULATION:
MOVS = ~ove bytelword

11 010010wl

14

CMPS = Compare bytelword

11 01 00 1 1 wi

22

SCAS = Scan byte/word

11 01 0 1 1 1 wi

15

LODS = Load bytelwd to AUAX

11

12

I

mod reg

3/10

rim
dat.,lw= 1

4/16
3/4

8116-bit

3

rim

Shaded areas indicate instructions not available in iAPX 86, 88 microsystems.

3-74

210451-004

IAPX 186

INSTRUCTION SET SUMMARY (Continued)
Clock
Cycles

FUNCTION

FORMAT

STRING MANIPULATION (Contonued)Repeated by count In CX
MOVS - Move string

11 11 1 0 0 1

CMPS - Compare string

11 11 1 0 0 1 z 11 0 1 00 1 1 wi

SCAS - Scan string

11 11 1 0 0 1 z 11 0 1 0 1 1 1 wi

LOOS - Load string

11 11 1 0 0 1

8+8n
5+22n
5+15n
6+11n
6+9n

11010010wl

11 0 1 0 1 lOw

Comments

I

~~},,;
.
'.

CALL; Call
Direct within segment

11 1 1 0 1 0 0 0

Register/memory
mdlrect within segment

11 111 111 1

Direct mtersegment

11 00 1 1 0 1

dlsp-Iow

I

dlsp-hlgh

modOl0rm
segment offset

15
13/19
23

segment selector

Indirect Intersegment

11 111111 1

JMP; Uncond,tlOnallumpShortJlong

11 1 , 0 , 0 ,

dlsp-Iow

Direct within segment

11 1 , 0 1 00

dlsp-Iow

modOll rm

(mod. II)

38

dlsp-hlgh

14
14

,I
I
Reglster/memory mdlrect within segment I1 1'1'11
I
Direct Intersegment
1
1
0
1
0
1
11
oI
I

modl00 r'm

,I

mod'OI r,m

(mod Til)

26

data-low

data-high

16
18
22

data-low

data-high

25

Indirect mtersegment

I'

' 1 ' ""

11/17

segment offset

14

segment selector

RET; Return from CALL
Within segment

11 1 0 0 0 0 , 11

Within seg adding Immed to SP

11 1 0 0 0 0 1 01

Intersegment

11 1 0 0 1 0 1 11

Intersegment adding Immediate to SP

11 1 0 0 1 0 1

oI

Shaded al eas indIcate InstructIons not avaIlable in iAPX 86,88 mlcrosystems

3-75

210451-004

inter

IAPX 186

INSTRUCTION SET SUMMARY (C~ntinued)
Clock
Cycles

FUNCTION

FORMAT

JE/Jl = Jump onequallZero

10 1 1 1 0 1 0 0

dlsp

4/13

JLlJNGE ~ Jump,on lessmot greatel 01 equal

10 1 1 1 1 1 0 0

dlSp

JLElJNG ~ Jump on less o"quaJlnot greater

10 1 1 1 1 1 1 0

dlSp

JB/JNAE ~ Jump on OOI../nolab"" 01 equal

10 1 1 1 0 0 1 0

dlSp

JBElJNA ~ Jump on 001 .. 01 equalmolabove

10 1 1 1 0 1 1 0

dlSp

4/13
4/13
4/13
4/13

JP/JPE ~ Jump on panty/panty even

10 1 1 1 1 0 1 0

dlSp

JO ~ Jump on ""rtlo. ,

101110000

dlSp

JS~JumponSign

10 1 1 1 1 00 0

dlSp

10 1 1 1 0 1 0 1

dlsp

JNLlJGE ~ Jumpon not lesslgreaterorequal

10 1 1 1 1 1 0 1

dlSp

JNLElJG ~ Jumpon not less OI,equai/grealer

10 1 1 1 1 1 1 1

dlSp

4/13

JNB/JAE ~ Jump on nol boo./ab"" or equal

10 1 1 1 0 0 1 1

dlSp

4/13

JNBElJA ~ Jump on not below o"quaVabove

10 1 1 1 0 1 1 1

dlSp

JNP/JPO ~ Jump on not p~/par odd

10 1 1 1 1 0 1 1

dlSp

4/13
4/13

JNO ~ Jump on not""rtlow

10 1 1 1 0 00 1

dlSp

JNS ~ Jumpon not sign

10 1 1 1 1 00 1

dlSp

JeXl ~ Jumpon ex zero

11 1 1 0 0 0 1 1

dlSp

LOOP ~ loop ex times

11 1 1 0 0 0 1 0

dlSp

LOOPZlLOOPE ~ loop_hIIe zero!equal

11 1 1 0 0 0 0 1

dlSp

LOOPNZlLOOPNE ~ loopwhllenot zero/equal

11 1 1 0 0 0 0 0 'I

dlSp

I
I

JMP not
taken/JMP
taken

4/13
4/13
4/13 '

JNElJNl ~ Jump on notequallnotzero

INT~lnt.rrupt:

Comments

4/13
4/13

4/13
4/13
5/15
6/16
6/16
6/16

Type specified

11 1 0 0 1 1 0 1

Type 3

11 1 0 0 1 1 0 0

INTO ~ Interrupt on overflow

11 1 0 0 1 1 1 0 1

45
48/4

IRET ~ Interrupt return

11 1 0 0 1 1 1 11

28

type

LOOP not
taken/LOOP
taken

47

if INT. taken/
if INT. not
taken

Shiided areas indicate instructions not available in iAPX 86, 88 microsystems.

3-76

210451-004

IAPX 186

INSTRUCTION SET SUMMARY (Continued)

FUNCTION

FORMAT

PROCESSOR CONTROL
CLC ~ Clear carry

11 1 1 1 1 00 0

CMC ~ Complement carry

11 1 1 1 0 1 0 1

STC ~ Set carry

11 1 1 1 1 00 1

CLO ~ Clear dlreclion

11 1 1 1 1 1 0 0

STO ~ Set directIOn

11 1 1 1 1 1 0 1

CLI ~ Clear Interrupt

11 1 1 1 1 01 0

STI ~ Set Interrupt

11 1 1 1 1 0 1 1

HLT~Halt

11 1 1 1 0 1 0 0

Clock
Cycles

WAIT~walt

11 00 1 1 0 1 1

LOCK ~ Bus lock prellx

11 1 1 1 0 00 0

ESC ~ Processor Exte,nSlon Escape

mod LLL rim
11 101 1 TT T
(ID LLL are opcode to processor extenSion)

2
2
2
2
2
2
2
2
6
2
6

I

Comments

if test = 0

Shaded areas indicate instructions not available in iAPX 86,88 microsystems.

3-77

210451-004

iAPX 186

FOOTNOTES
The effective Address (EA) of the memory operand is
computed according to the mod and rim fields:

REG is assigned according to the following table:
16-Bit (w = 1)
000 AX
001 CX
010 OX
011 BX
100 SP
101 BP
110 SI
111 01

if mod = 11 then rim is treated as a REG field
if mod = 00 then OISP = 0*, disp-Iow and disp-high
are absent
if mod = 01 then OISP = disp-Iow sign-extended to
16-bits, disp-high is absent
if mod

= 10 then OISP = disp-high: disp-Iow

if rim = 000 then EA = (BX) + (SI) + OISP

8-Bit(w = 0)
000 AL
001 CL
010 OL
011 BL
100 AH
101 CH
110 OH
111 BH

if rim = 001 then EA = (BX) + (01) + OISP

+ (SI) + OISP
+ (01) + OISP
= (SI) + OISP
= (01) + OISP
= (BP) + OISP*
= (BX) + OISP

if rim = 010 then EA = (BP)

if rim = 011 then EA = (BP)
if rim = 100then EA
if rim = 101 then EA
if rim = 110 then EA
if rim

= 111 then EA

the physical addresses of all operands addressed by
the BP register are computed using the SS segment
register. The physical addresses of the destination operands of the string primitive operations (those addressed by the 01 register) are computed using the ES
segment, which may not be overridden.

OISP follows 2nd byte of instruction (before data if
required)
"except If mod

~

00 and ,1m

~

110 then EA

~

disp-high' disp-Iow.

NOTE:
EA CALCULATION TIME IS 4 CLOCK CYCLES FOR ALL MODES, AND IS INCLUDED
IN THE EXECUTION TIMES GIVEN WHENEVER APPROPRIATE

SEGMENT OVERRIDE PREFIX
10 0 1 reg 1 1 0

I

reg is assigned according to the following:
reg

Segment
Register

00
01
10
11

ES
CS
SS
OS

3-78

210451-004

iAPX 88/10
8-BIT HMOS MICROPROCESSOR
8088/8088-2
• 8·Bit Data Bus Interface

• 8·Bit and 16·Bit Signed and Unsigned
Arithmetic in Binary or Decimal,
Including Multiply and Divide

• 16·Bit Internal Architecture
• Direct Addressing Capability to 1
Mbyte of Memory

• Compatible with 8155·2, 8755A·2 and
8185·2 Multiplexed Peripherals

• Direct Software Compatibility with
iAPX 86110 (8086 CPU)

• Two Clock Rates:
5 MHz for 8088
8 MHz for 8088·2

• 14·Word by 16·Bit Register Set with
Symmetrical Operations

• Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range

• 24 Operand Addressing Modes
• Byte, Word, and Block Operations

The Intel® iAPX 88/10 is a new generation, high performance microprocessor implemented in N-channel, depletion load,
silicon gate technology (HMOS), and packaged in a 40-pin CerDIP package. The processor has attributes of both 8- and
16-bit microprocessors. It is directly compatible with iAPX 86/10 software and 8080/8085 hardware and peripherals.

MEMORY INTERFACE
C·BUS

MIN
MODE
GND

Vee

A1'

A15

INSTRUCTION
STREAM BYTE

A13

A16/S3

QUEUE

A1.

A17/S4

A11

A18/55

A10
CS

BUS
INTERFACE
UNIT

A191S6

(HIGH)

A9

SSO

A8

MNIMX

05

AD7

Ali

IP

AD6

HOLD

(ROIGTO)

AD5

HlDA

(RO/GT1)

AD.

WR

(LOCK)

AD3

101M

(52)

AD.

DTiR

AD1

DEN

(51)
(SO)

ADO

ALE

(050)

NMI

INTA

(051)

INTR

TEST

AH

UNIT

1

MODE

55

A·BUs

EXECUTION

(MAX

AL
BL
CL
Dl

BH
CH
DH
SP
BP
51
01

ClK

READY

GND

RESET

FLAGS

Figure 1. iAPX 88/10 CPU Functional Block Diagram

Figure 2. iAPX 88/10 Pin Configuration

Intel Corporatton Assumes No Rssponslbllty for the Use of Any CIrcUItry Other Than Circuitry EmbodIed 1M an Intel Product No Other
©INTEl CORPORATION, 1980

3-79

ClfCUlt

Patent Licenses afe Implied

intJ

iAPX 88/10

Table 1. Pin Description
The following pin function descriptions are for 8088 systems in either minimum or maximum mode. The "local bus" in
these descriptions is the direct multiplexed bus interface connection to the 8088 (without regard to additional bus
buffers).
Symbol

AD7-ADO

A15-A8

A19/56, A18/55,
A17/54, A16/53

Name and Function

Pin No.

Type

9-16

I/O

Address Data Bus: These lines constitute the time multiplexed memory/IO
address (Tl) and data (T2, T3, Tw, and T4) bus. These lines are active HIGH and
float to 3-state OFF during interrupt acknowledge and local bus "hold acknowledge".

2-8,39

0

Address Bus: These lines provide address bits 8 through 15 for the entire bus
cycle (T1-T4). These lines do not have to be latched by ALE to remain valid.
A 15-A8 are active HIGH and float to 3-state OFF during interrupt acknowledge
and local bus "h<:>ld acknowledge".

35-38

0

Address/Status: During T1, these are the four
most significant address lines for memory operations. During I/O operations, these lines are
lOW. During memory and I/O operations, status
information is available on these lines during
T2, T3, Tw, and T4. 56 is always low. The status of
the interrupt enable flag bit (55) is updated at
the beginning of each clock cycle. 54 and 53 are
encoded as shown.

.

O'(LOW)

0

,

1 (HIGHI

53

,
,

0
0

CHARACTERISTICS

AltemateData

Slack
Code or None

Data

S6Is0(LOW)

This information indicates which segment register is presently being used for data accessing.
These lines float to 3-state OFF during local bus
"hold acknowledge".
RD

32

0

Read: Read strobe indicates that the processor is performing a memory or I/O
read cycle, depending on the state of the 10/1VI pin or 52. This signal is used to
read devices which reside on the 8088 local bus. RD is active lOW during T2, T3
and Tw of any read cycle, and is guaranteed to remain HIGH in T2 until the 8088
local bus has floated.

READY

22

I

READY: isthe acknowledgement from the addressed memory or I/O device that
it will complete the data transfer. The RDY Signal from memory or I/O is synchronized by the 8284 clock generator to form READY. This signal is active
HIGH. The 8088 READY input is not synchronized. Correct operation is not
guaranteed if the set up and hold times are not met.

INTR

18

I

Interrupt Request: is a level triggered input which is sampled during the last
clock cycle of each instruction to determine ilthe processor should enter into an
interrupt acknowledge operation. A subroutine is vectored to via an interrupt
vector lookup table located in system memory. It can be internally masked by
software resetting the interrupt enable bit. INTR is internally synchronized. This
signal is active HIGH.

TE5T

23

I

TEST: input is examine~ by the "wait for test" instruction. If the TE5T input is
lOW, execution 
1\

lJ.ll

Jll

V INTS:=~PT
CONTROL

WE 001 I

2142 RAM (2)

-

21162 PROM

OEII

B

IIIIWRI

Mes 80
PERIPHERAL

I

INT

-

¢==='R..'

Figure 6. Demultiplexed Bus Configuration

t
I

GND

rol

U

II284A

CLOCK
GENERATQR

An

~
rr-

K
CL
READY

elK MADe

MN''''' rOND
So

So

S1

S;
S,

s,

RESET

....CPU

RO'

MWTC

IiI!WC _NC

r - - DEN

r----

8288

lORe

C~~~R

lowe

AT6WC -NC

DT/R

ALE
INTA
r---:l
I
I

ST'
GNC-

r---

OE

ADo-AD1

8282

LATCH
(1,20R3)

As-AlIl ~DDRIOA~

INT

5=

F

I
ADDRESS

I

l

T

OE

--j

I

fJ

82"

DATA

TRANSCEIVER

ill
~
V

INT8:~~PT
CONTROL

-

~.

1

II II

I I II

WE

OEIIB

11 001 lln III

2142 RAM (2)

~I~'
Figure 7. Fully Buffered System Using Bus Controller

3-87

I

21162 PROM

IIIIWR

Mesao

PERIPHERAL

,

iAPX 88/10

Bus Operation
The 8088 address/data bus is broken into three parts the lower eight address/data bits (ADO-AD7), the middle
eight a(ldress bits (A8-A15), and the upper four address
bits (A16-A19). The address/data bits and tile highest
four address bits are time multiplexed. This technique
provides the most efficient use of pins on the proc·
essor, permitting the use of a standard 40 lead package.
The middle eight address bits are not multiplexed, i.e.
they remain valid throughout each bus cycle. In addi-

tion, the bus can be demultlplexed at the processor with
a single address latch If a stanpard, non-multiplexed
bus is desired for the system.
Each processor bus cycle consists of at least four elK
cycles. These are referred to as T1, T2, T3, and T4. (See
Figure 8>' The address is emitted from the processor
during T1 and data transfer occurs on the bus during T3
and T4. T2 is used primarily for changing the direction of
the bus during read operations. In the event that a "NOT
READY" \indicatlon. is given by the addressed device,

1-------(4+NwAIT):oTc v - - - - - - , - - - - - - - ( 4 + N w A I T ) .. T e v - - - - - - - - j
T,

T,

T3

TWAIT

I

T4

T1

T2

T3

eLK

\
ADDRISTATUS

ADOR

-----GXI...__

ADDRIDATA

)---<=><=

D_AT_A_O_UT_ID_'._DoI_ _ _ _

READY

DT/R

MeMORY ACCESS TIME

\------/
Figure 8. Basic System Timing

3-88

iAPX 88/10

"wait" states (Tw) are inserted between T3 and T4. Each
inserted "wait" state is of the same duration as a ClK
cycle. Periods can occur between 8088 driven bus cycles.
These are referred to as "idle" states (Ti), or inactive ClK
cycles. The processor uses these cycles for internal
housekeeping.
During T1 of any bus cycle, the ALE (address latch enable)
signal is emitted (by either the processor or the 8288 bus
controller, depending on the MN/MX strap). At the trailing
edge of this pulse, a valid address and certain status
information for the cycle may be latched.
Status bits SO, Sf, and S2 are used by the bus controller, in
maximum mode, to identify the type of bus transaction
according to the following table:

S2

o (LOW)
0
0
0
1 (HIGH)
1
1
1

S;
·0
0
1
1
0
0
1
1

So

CHARACTERISTICS

0
1
0
1
0
1
0
1

Interrupt Acknowledge
Read I/O
Write I/O
Halt
Instruction Fetch
Read Data from Memory
Write Data to Memory
Passive (no bus cycle)

Status bits S3 through S6 are multiplexed with high order
address bits and are therefore valid during T2 through T4.
S3 and S4 indicate which segment register was used for
this bus cycle in forming the address according to the
following table:

S.

S3

o (LOW)

0
1
0
1

0
1 (HIGH)
1

CHARACTERISTICS
Alternate Data (extra segment)
Stack
Code or None
Data

S5 is a reflection of the PSW interrupt enable bit. S6 is
always equal to O.

EXTERNAL INTERFACE
Processor Reset and Initialization
Processor initialization or start up is accomplished with
activation (HIGH) of the RESET pin. The 8088 RESET is
required to be HIGH for greater than four clock cycles. The
8088 will terminate operations on the high-going edge of
RESET and will remain dorl)1ant as long as RESET is HIGH.
The low-going transition of RESET triggers an internal
reset sequence for approximately 7 clock cycles. After this
interval the 8088 operates normally, beginning with the
instruction in absolute location FFFFOH. (See Figure 4.)
The RESET input is internally synchronized to the processor clock. At initialization, the HIGH to lOW transition of
RESET must occur no sooner than 50 JLS after power up, to
allow complete initialization of the 8088.
If INTR is asserted sooner than nine clock cycles after the
end of RESET, the processor may execute one instruction
before responding to the interrupt.
All 3-state outputs float to 3-state OFF during RESET.
Status is active in the idle state for the first clock after
RESET becomes active and then floats to 3-state OFF.

Interrupt Operations
Interrupt operations fall into two classes: software or
hardware initiated. The software initiated interrupts and
software aspects of hardware interrupts are specified in
the instruction set description in the iAPX 88 book or the
iAPX 86,88 User's Manual. Hardware interrupts can be
classified as nonmaskable or maskable.
Interrupts result in a transfer of control to a new program
location. A 256 element table containing address pointers
to the interrupt service program locations resides in absolute locations 0 through 3FFH (see Figure 4), which are
reserved for this purpose. Each element in the table is 4
bytes in size and corresponds to an interrupt "type." An
interrupting device supplies an 8-bit type number, during
the interrupt acknowledge sequence, which is used to
vector through the appropriate element to the new interrupt service program location.

Non-Maskable Interrupt (NMI)
I/O Addressing
In the 8088, I/O operations can address up to a maximum
of 64K I/O registers. The I/O address appears in the same
format as the memory address on bus lines A15-AO. The
address lines A19-A16 are zero in I/O operations. The vari'able I/O instructions, which use register DX as a pointer,
have full address capability, while the direct I/O instructions directly address one or two of the 256 I/O byte
locations in page 0 of the I/O address space. I/O ports are
addressed in the same manner as memory locations.
Designers familiar with the 8085 or upgrading an 8085
design should note that the 8085 addresses I/O with an
8-bit address on both halves of the 16-bit address bus. The
8088 uses a full 16-bit address on its lower 16 address
lines.

The processor provides a single non-maskable interrupt
(NMI) pin which has higher priority than the maskable
interrupt request (INTR) pin. A typical use would be to
activate a power failure routine. The NMI is edge-triggered
on a lOW to HIGH transition. The activation of this pin
causes a type 2 interrupt.
NMI is required to have a duration in the HIGH state of
greater than two clock ·cycles, but is not required to ·be
synchronized to the clock. Any higher going transition of
NMI is latched on-chip and will be serviced at the end of
the current instruction or between whole moves (2 bytes in
the case of word moves) of a block type instruction. Worst
case response to NMI would be for multiply, divide, and
variable shift instructions. There is no specification on
the occurrence of the low-going edge; it may occur

3-89

iAP)( 88/10
before, during, or after the servIcing of NMI.
Another high-going edge triggers another response if it
occurs after the start of the NMI procedure. The signal
must be free of logical spikes in general and be free of
bounces on the 10w-gQing edge to avoid triggering ·extraneous responses.

and sample period. The interrupt return instruction includes a flags pop which returns the status of the
original interrupt enable bit when it restores the flags.

HALT
When a software HALT instruction is executed, the
processor indicates that it is entering the HALT state in
one of two ways, depending upon which mode is
strapped. In minimum mode, the processor issues ALE,
delayed by one clock cycle, to allow the system to latch
the halt status. Halt status is available on 10/M, DT/R,
and SSO. In maximum mode, the processor issues appropriate HALT status on S2, S 1, and SO, and the 8288
bus controller issues one ALE. The 8088 will not leave
the HALT state when a local bus hold is entered while in
HALT. In this case, the processor reissues the HALT indicator at the end of the local bus hold. An interrupt request or RESET will force the 8088 out of the HALT
state.

Maskable Interrupt (INTR)
The 8088 provides a single interrupt request input (INTR)
which can be masked internally by software with the
resetting of the interrupt enable (IF) flag bit. The interrupt request signal is level triggered. It is internally
synchronized during each clock cycle on the high-going
edge of CLK. To be responded to, INTR must be present
(HIGH) during the clock period preceding the end of the
current instruction or the enq of a whole move for a
block type instruction. During interrupt response sequence, further interrupts are disabled. The enable bit is
reset as part of the response to any interrupt (INTR,
NMI, software interrupt, or single step), although the
FLAGS register which is automatically pushed onto the
stack reflects the state of the processor prior to the interrupt. Until the old FLAGS register is restored, the
enable bit will be zero unless specifically set by an instruction.

Read/Modify/Write (Semaphore) Operations
via LOCK
The LOCK status information is provided by' the processor when consecutive bus cycles are required during
the execution of an Instruction. This allows the processor to perform read/modify/write operations on
memory (via the "exchange register with memory"
instruction), without another system bus master receiving intervening memory cycles. This is useful in multiprocessor'system configurations to accomplish "test
and set lock" operations. The ~ signal is activated
(LOW) in the clock cycle following decoding of the
LOCK prefix instruction. It is deactivated at the end of
the last bus cycle of the instruction following the LOCK
prefix. While LOCK is active, a request on a RQ/GT pin will
be recorded, and then honored at the end of the LOCK.

During the response sequence (See Figure 9), the processor executes two successive (back to back) interrupt
acknowledge cycles. The 8088 emits the LOCK signal
(maximum mode only) from T2 01 the lir!lt bus cycle until
T2 of the second. A local bus "hold" request will not be
honored until the end of the second bus cycle. In the
second bus cycle, a byte is letched from the external interrupt system (e.g., 8259A PIC) which identifies the
source (type) of the interrupt. This byte is multiplied by
four and used as a pointer into the interrupt vector
lookup table. An INTR slgnallelt HIGH will be continually responded to within the limitations of the enable bit

ALE

I

JlL.....--_ _nL....-_ _
T1

I

T2

f3

T4

T1

T,

\'------;-_ _----'1

ADo-AD,

FLOAT

Figure 9_ Interrupt Acknowledge Sequence

3-90

T,

iAPX 88/10
External Synchronization via TEST

a byte of information is read from the data bus, as sup·
plied by the interrupt system logic (i.e. 8259A priority in·
terrupt controller). This byte identifies the source (type)
of the interrupt. It is multiplied by four and used as a
pOinter into the interrupt vector lookup table, as de·
scribed earlier.

As an alternative to interrupts, the 8088 provides a
single software·testable input pin (TEST). This input is
utilized by executing a WAIT instruction. The single
WAIT instruction is repeatedly executed until the TEST
input goes active (LOW). The execution of WAIT does
not consume bus cycles once the queue is full.
If a local bus request occurs during WAIT execution, the
8088 3-states all output drivers. If interrupts are enabled,
the 8088 will recognize interrupts and process them.
The WAIT instruction is then refetched, and reexecuted.

Bus Timing (See Figure 10J

For medium complexity systems, the M N/MX pin is con·
nected to GND and the 8288 bus controller is added to
the system, as well as an 8282/8283 latch for latching
the system address, and an 8286/8287 transceiver to
allow for bus loading greater than the 8088 is capable of
handling. Signals ALE, BEN, and DT/R are generated by
the 8288 instead of the processor in this configuration,
although their timing remains relatively the same. The
8088 status outputs (82, S1, and SO) provide type of
cycle information and become 8288 inputs. This bus
cycle information specifies read (code, data, or 110),
write (data or 110), interrupt acknowledge, or software
halt. The 8288 thus issues control signals speCifying
:nemory read or write, 110 read or write, or interrupt
acknowledge. The 8288 provides two types of write
strobes, normal and advanced, to be applied as required.
The normal write strobes have data valid at the leading
edge of write. The advanced write strobes have the
same timing as read strobes, and hence, data is not
valid at the leading edge of write. The 8286/8287 trans·
ceiver receives the usual T and OE inputs from the
8288's DT/R and DEN outputs.

Basic System Timing
In minimum mbde, the MN/MX pin is strapped to Vee
and the processor emits bus control signals compatible
with the 8085 bus structure. In maximum mode, the
MN/MX pin is strapped to GND and the processor emits
coded status rnformation which the 8288 bus controller
uses to generate MULTIBUS compatible bus control
signals.

System Timing -

lIiIedium Complexity Systems

Minimum System

(See Figure 8J
The read cycle begins in T1 with the assertion of the ad·
dress latch enable (ALE) signal. The trailing (lOW going)
edge of this signal is used to latch the address informa·
tion, which is valid on the address/data bus (ADO-AD7)
at this time, into the 8282/8283 latch. Address lines A8
through A15 do not need to be latched because they reo
main valid throughout the bus cycle. From T1 to T4 the
101M signal indicates a memory or 110 operation. At T2
the address is removed from the address/data bus and
1he bus goes to a high impedance state. The~ad con·
trol signal is also asserted at T2. The read (RD) signal
causes the addressed device to enable its data bus
drivers to the local bus. Some time later, valid data will
be available on the bus and the addressed device will
drive the READY line HIGH. When the processor returns
the read signal to a HIGH level, the addressed device
will again 3-state its bus drivers. If a transceiver
(8286/8287) is required to' buffer the 8088 local bus,
signals DT/R and DEN are provided by the 8088.

The pointer into the interrupt vector table, which is
passed during the second INTA cycle, can derive from
an 8259A located on either the local bus or the system
bus. If the master 8289A Priority Interrupt controller IS
positioned on the local bus, a TTL gate is required to
disable the 8286/8287 transceiver when reading from the
master 8259A during the interrupt acknowledge se·
quence and software "poll".

The 8088 Compared to the 8086
The 8088 CPU is an 8-bit processor designed around the
8086 internal structure. Most internal functions of the
8088 are identical to the equivalent 8086 functions. The
8088 handles the external bus the same way the 8086
does with the distinction of handling only 8 bits at a
time. Sixteen·bit operands are fetched or written in two
consecutive bus cycles. Both processors wil'l appear
identical to the software engineer, with the exception of
execution time. The internal register structure is iden·
tical and all instructions have the same end result. The
differences between the 8088 and 8086 are outlined
below. The engineer who is unfamiliar with the 8086 is
referred to the iAPX 86, 88 User's Manual, Chapters 2 and
4, for function description and instruction set information.
Internally, there are three differences between the 8088
and the 8086. All changes are related to the 8-bit bus in·
terface.

A write cycle also begins with the assertion of ALE and
the emission of the address. The 101M signal is again
asserted to indicate a memory or 110 write operation. In
T2, immediately following the address emission, the
processor emits the data to be written into the ad·
dressed location. 'fhis data remains valid until at least
the middle of T4. During T2, T3, and Tw, the processor
asserts tile write control signal. The write (WR) signal
becomes active at the beginning of T2, as opposed to
the read, which is delayed somewhat into T2 to provide
time for the bus to float.
The basiC difference between the interrupt acknowl·
edge cycle and a read cycle is that the interrupt
acknowledge (INTA) signal is asserted in place of the
read (RD) signal and the address bus is floated. (See
Figure 9J:.ln the second of two successive INTA cycles,
3-91

iAPX 88/10
o

The queue length is 4 bytes in the 8088, whereas the
8086 queue contains 6 bytes, or three words. The
queue was shortened to prevent overuse of the bus by
the BIU when prefetching instructions. This was required because of the additional time necessary to
fetch instructions 8 bits at a time.

o

To further optimize the queue, the prefetching algorithm was changed. The 8088 BIU will fetch a new instruction to load into the queue each time there is a 1
byte hole (space available) in the queue. The 8086
waits until a 2-byte space is available . _

o

The internal execution time of the Instruction set is
affected by the 8-bit interface. All 16-bit fetches and
writes fromlto memory take an additional four clock
cycles. The CPU is also limited by the speed of instruction fetches. This latter problem only occurs
when a series of simple operations occur. When the
more sophisticated instructions of the 8088 are being
used, the queue has time to fill and the execution proceeds as fast as the execution unit will allow.

The 808S and 8086 are completely software compattble
by virture of their identical execution units. Software
that is system dependent may not be completely transferable, but software that is not system dependent will
operate equally as well on an 8088 or an 8086.

The hardware interface of the 8088 contains the major
differences between the two CPUs. The pin assignments are nearly identical, however, with the following
functional changes:
o

A8-A 15 - These pins are only address outputs on the
8088. These address lines are latched internally and
remain valid throughout a bus cycle in a manner
similar to the 8085 upper addr~ss lines.

o

BHE has no meaning on the 8088 and has been eliminated.

o

SSO provides the SO status information in the minimum mode. This output occurs on pin 34 in minimum
mode only. DT/R, 101M, and SSO provide the complete
bus status in minimum mode.

o

10iM has been inverted to be compatible with the
MCS-85 bus structure.

,0

3-92

ALE is delayed by one clock cycle in the minimum
mode when entering HALT, to allow the status to be
latched with ALE.

iAPX 88/10

T,
ClK

T,

I'

---.F'

T,

T,

1M

I'

aS1, aso

Y

===>-

$2, Sf, SQ

// / / /

'---

8088

A191S6 - A161S3

A19-A16

ALE

'\

ROY

8284

READV

8088

8288

S6-S3

,--

I

I
I

!

AD7 - ADO

8088

A7

DATA IN

AO

A15-A8

A15-AB

RD
I

Dr/R

8288

MRDC

--------

\
/

DEN

Figure 10. Medium Complexity System Timing

3-93

iAPX 88/10
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ......... O·C to 70·C
Storage Temperature ............. - 65·C to + 150·C
Voltage on Any Pin with
Respect to Ground .................. - 1.0 to + 7V
Power Dissipation ........................ 2.5 Watt

D.C. CHARACTERISTICS
Symbol

. VIL

'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera-'
tion of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

(8088: TA = O°C to 70·C. Vee =.5V ±10%)'
(8088-2: TA = O·C to 70·C. Vee = 5V ±5%)
Min.

Max.

Units

Input Low Voltage

Parameter

-0.5

+0.8

V

(See note 1)

2.0

Vee+ 0.5

V

(See note 1,2)

0.45

V

IOl

V

IOH

Test Conditions

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

lee

340
350
250

mA

TA

III

8088
Power Supply Current: 8088-2
PSOSS
Input Leakage Current

±10

/LA

OV ""VIN' ""Vee

ILO

Output Leakage Current

±10

/LA

0.45V "" Your "'"
Vee

Vel

Clock Input Low Voltage

-0.5

+0.6

V

VeH

Clock Input High Voltage

3.9

Vee+ 1.O

V

CIN

Capacitance if Input Buffer
(All input except
ADo-AD7. RQ/GT

15

pF

fc = 1 MHz

CIO

Capacitance of I/O Buffer
(ADo-AD7 • RQ/GT

15

pF

fc

• Note: For Extended Temperature EXPRESS Vce

2.4

=5V ± 5%

Note 1: VIL tested with MN/MX Pin = OV
VIH tested with MN/MX Pin = 5V
MN/MX Pin is a strap Pin
Note 2: Not applicable to RQ/GTO and RQ/GT1 Pins (Pin 30 and 31)

3-94

= 2.0 mA
= -400 /LA

= 25·C

= 1 MHz

iAPX 88/10

A.C. CHARACTERISTICS

(8088: TA = ODC to 70DC, Vee = 5V ±10%)*
(8088-2: TA = ODC to 70DC, Vee = 5V ±5%)

MININ/UM COMPLEXITY SYSTEM TIMING REQUIREMENTS
8088
Symbol

Parameter

,

8088-2

Min.

Max.

Min.

Max.

Units

500

125

500

ns

Test
Conditions

TCLCL

CLK Cycle Period

200

TCLCH

CLK LowTime

118

68

ns

TCHCL

CLK High Time

69

44

ns

TCH1CH2

CLK Rise Time

10

10

ns

From 1.0V
to 3.5V

TCL2CL1

CLK Fall Time

10

10

ns

From 3.5V
to 1.0V

TDVCL

Data in Setup Time

30

20

ns

TCLDX

Data in Hold Time

10

10

ns

TR1VCL

ROY Setup Time
into 8284 (See
Notes 1,2)

35

35

ns

TCLR1X

ROY Hold Time
into 8284 (See
Notes 1,2)

0

0

ns

118

68

ns

TRYHCH

READY Setup
Time into
8088

TCHRYX

READY Hold Time
into 8088

30

20

ns

TRYLCL

READY Inactive to
CLK (See Note 3)

-8

-8

ns

HOLD Setup Time

35

20

ns

30

15

ns

THVCH
TlNVCH

INTR, NMI, TEST
Setup Time (See
,Note 2)

'"

TILIH

Input Rise Time
(Except CLK)

20

20

ns

From 0.8V
to 2.0V

TIHIL

Input Fall Time
(Except CLK)

12

12

ns

From 2.0V
to 0.8V

*Note: For Extended Temperature EXPRESS Vcc=5V±5%

3-95

iAPX 88/10

A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES

8088
Symbol

Parameter

8088·2

Min.

Max.

Min.

Max.

Units

10

110

10

60

ns

80

TClAX

TClAV

Address Valid Delay

TClAX

Address Hold Time

10

TClAZ

Address Float Delay

TClAX

TlHll

ALE Width

10

TClCH-20

ns
50

TClCH-10

ns
ns

TCllH

ALE Active Delay

80

50

ns

TCHll

ALE Inactive Delay

85

55

ns

TllAX

Address Hold Time to
ALE Inactive

TClDV

Data Valid Delay

10

TCHDX

Data Hold Time

10

TWHDX

Data Hold Time After WR

TCHCl-10

TCHCl-10
110

10

ns
60

10

TClCH-30

Test Conditions

ns

CL = 20·100 pFfor
all 8088 Outputs
in addition to
internal loads

ns

TClCH-30

ns

10

110

Control Active Delay 2

10

Control Inactive Delay

10

TAZRl

Address Float to READ
Active

0

TClRl

RD Active Delay

10

165

10

100

ns

TClRH

RD Inactive Delay

10

150

10

80

ns

TRHAV

RD Inactive to Next
Add ress Active

TClHAV

HLDA Valid Delay

TRlRH

RDWidth

2TClCl-75

2TClCl-50

ns

TWlWH

WRWidth

2TClCl-60

2TClCl-40

ns

TAVAl

Address Valid to ALE low

TClCH-60

TClCH-40

TOlOH

Output Rise Time

20

20

ns

From 0.8V to 2.0V

TOHOL

Output Fall Time

12

12

ns

From 2.0V to O.8V

?TCVCTV

Control Active Delay 1

TCHCTV
TCVCTX

10

70

ns

110

10

60

ns

110

10

70

ns

TClCl-45
10

ns

0

TClCl-40
160

A.C. TESTING INPUT, OUTPUT WAVEFORM

10

ns
100

ns

ns

A.C. TESTING LOAD CIRCUIT

lNPUTIOUTPUT

DEVICE
UNDER
TEST

iJc,

100pF

-=

A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR
A LOGIC 0 THE CLOCK IS DRIVEN AT 4 3V AND 025V TIMING MEASUREMENTS ARE MADE AT 1 5V FOR BOTH A LOGIC 1 AND 0

Cl INCLUDES JIG CAPACITANCE

3-96

iAPX 88/10

WAVEFORMS
BUS TIMING-MINIMUM MODE SYSTEM
T,

T,

T,

Tw

I

I---- TCLCL -rCH1CH2J I- --I i-- TCL2CL1

elK (8284 Output)

VCH,,~}----1

~

TCHCTV

Ir'"'"'"\

\-1

TCHCL

T,

~~
_TCLCH~

IO/M,SSO

-

TCLAV--

TCLLH-

f

A,s

-

I=-T

TClAX-

-Aa (Float during INTAI

-

TCHDX--

DV

&s-Sa

A'9-A16

I-- T~LAX

TLH~L-=:

r-/

ALE

-.:1 -

i--

TCHLL-I

vr :\\~
\'0"""'"

-TAVAL-

ROY (8284 Input)

VIL~

SEe NOTE 5

READY (8088 Input)

----

--.;

TR1VCl

~~~ ~~ ~ ~~

j'~q -

f

-

I

I

1
:-TC~AZ

AD1-ADO

TAZRL-

=----z-

READ CYCLE

(NOTE 1)

(WA, im'A = VOH)

TCHCTV

TDVCL- i--TCLDX_

-hi
I

feLRl

I

DT/R
TCVCTV-

3-97

-TCHRYX

-

TRYHCH-

AD7-ADo

·FrClR1X

~

DATA IN

FLOA::JL
TCLRH-

H

-TRHAV

f---~CHCTV

TRLRH

I!

TCVCTX-

[:.1

fJ

intJ

iAPX88/10

WAVEFORMS (Continued)
BUS TIMING-MINIMUM MODE SYSTEM (Continued)
... -t"
elK (8284 Output)

TCHDX
DATA OUl

AD7-ADO

-TWHOX-TCVCTX
WRITE CYCLE
NOTE 1

--+---r---------+,I·----r-----TWLWH--------~-I,~_+-------

WR
TCVCTX--TCLAZ

AOr-ADo

DT/R
INTA CYCLE
NOTES 1,3

(RD, WR = VOH)

SOFTWARE HALT DEN,Ro,WR,INTA

=0-

INVALID ADDRESS

YOH '

DT/RINDETERMINATE

SOFTWARE HALT

relAV
NOTES:

1. ALL SIGNALS SWITCH BETWEEN VOH\AND VOL UNLESS OTHERWISE

SPECIFIED.

2. ROY IS SAMPLED NEAR THE END OF T2, Ts. Tw TO DETERMINE IF Tw
MACHINES STATES ARE TO BE INSERTED.
3. TWO lNTA CYCLES RUN BACK·YO·BACK. THE 8088 LOCAL ADDRIOATA
BUS 1$ FLOATING DURING BOTH INTA CYCLES. CONTROL SIGNALS

ARE SHOWN FOR THE SECOND INTA CYCLE
4. SIGNALS AT 8284 ARE SHOWN FOR REFERENCE ONLY.

5. ALLTIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE
NOTED.

3-98

inter

iAPX 88/10

A.C. CHARACTERISTICS
MAX MODE SYSTEM (USING 8288 BUS CONTROllER)
TIMING REQUIREMENTS

8088-2

8088
Symbol
TClCl

Min.

Max.

Min.

Max.

Units

ClK Cycle Period

200

500

125

500

ns

Parameter

TClCH

ClK low Time

118

68

ns

TCHCl

ClK High Time

69

44

ns

TCH1CH2

ClK Rise Time

10
10

Test Conditions

10

ns

From 1.OV to 3.5V

10

ns

From 3.5V to 1.OV

TCl2Cl1

ClK Fall Time

TDVCl

Data In Setup TIme

30

20

ns

TClDX

Data In Hold Time

10

10

ns

TR1VCl

ROY Setup Time into 8284
(See Notes 1, 2)

35

35

ns

TClR1X

ROY Hold Time into 8284
(See Notes 1, 2)

0

0

ns

TRYHCH

READY Setup Time into
8088

118

68

ns

TCHRYX

READY Hold Time into 8088

30

20

ns

TRYlCl

READY Inactive to ClK (See
Note 4)

-8

-8

ns

TlNVCH

Setup Time for Recognition
(INTR, NMI, TEST)
(See Note 2)

30

15

ns

TGVCH

RQ/GT Setup Time

30

15

ns

TCHGX

RQ Hold Time into 8086

40

30

ns

TILIH

Input RiseTime
(Except ClK)

20

20

ns

From O.SV to' 2.0V

Input Fall Time (Except ClK)

12

12

ns

From 2.0V to 0.8V

1--'

TIHll

NOTES:
1 Signal at 8284 or 8288 shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next elK.
3. Applies only to T2 state (8 ns into T3 state).
4. Applies only to T2 state (8 ns into T3 state).

3-99

iAPX 88/10

A.C. CHARACTERISTICS
TIMING RESPONSES

8088
Symbol

8088·2

Min.

Max.

Min.

Max.

Units

TCLML

Command Active Delay (See
Note 1)

10

35

10

35

ns

TCLMH

Command inactive Delay (See
Note 1)

10

35

10

35

ns!

TRYHSH

READY Active to Status Passive
(See Note 3)

65

ns
ns

Parameter

110

TCHSV

Status Active Delay

10

110

10

60

TCLSH

Status Inactive Delay

10

130

10

70

ns

TCLAV

Address Valid Delay
Address Hold Time

10
10

110

10
10

60

ns
ns

TCLAZ

Address Float Delay

TCLAX

80

TCLAX

50

ns

TSVLH

Status Valid to ALE High (See
Note 1)

15

15

ns

TSVMCH

Status Valid to MCE High (See
Not~ 1)

15

15

ns

TCLLH

CLK Low to ALE Valid (See
Note 1)

15

15

ns

TCLMCH

CLK Low to MCE High (See
Note 1)

15

15

ns

TCHLL

ALE Inactive Delay (See Note 1)

15

15

ns

TCLMCL

MCE Inactive Delay (See Note 1)

15

15

ns

TCLDV

Data Valid Delay

10

60

ns

TCHDX

Data Hold Time

10

TCVNV

Control Active Delay (See
Note 1)

5

45

5

45

ns

TCVNX

Control Inactive Delay (See
Note 1)

10

45

10

45

ns

TCLAX

110

10
10

ns

Test Conditions

CL = 20-100 pF for
all 8088 Outputs
in addition to
internal loads

TAZRL

Address Float to Read Active

0

TCLRL

RD Active Delay

10

165

10

100

ns

TCLRH

RD Inactive Delay

10

150

10

80

ns

TRHAV

RD Inactive to Next Address
Active

TCHDTL

Direction Control Active Delay
(See Note 1)

50

50

ns

TCHDTH

Direction Control Inactive Delay
(See Note 1)

30

30

ns

TCLGL

GT Active Delay

85

50

ns

TCLGH

GT Inactive Delay

85

50

ns

TRLRH

RDWidth

TOLOH

Output RiseTime

20

20

ns

From 0.8Vto
2.0V

TOHOL

Output Fall Time

12

12

ns

From 2.0V to
0.8V

ns

0

TCLCL-45

TCLCL-40

2TCLCL-75

3-100

ns

2TCLCL-50

ns

iAPX 88/10

WAVEFORMS
BUS TIMING-MAXIMUM MODE

T,

T,

---I

I--TClCl-TCH1CH2--! IClK

.r--\

VCH,f\.
VCl...}

TClAV~

1\---:---1

_

S2,'S1,So (EXCEPT HALT)

I-TCl2Cl1

j\---J

"'--J

I - - TCHCl

TCHSV

-

0/

\

;0f/;7(SEE NOTE 8)
ll~---+---+----~--~~~~

--~~~

l

L-

I--- TClCH_
~+--'""'"'""

-TClSH

S

TSVLH-I

TCLlH~

r-r.=.

---+-,'

-

TCLDV

TCHDX-

-r-+---l--f--+----l----t----.

I----

\.-----

\

Ss·S:3

A19- A 16

SEE NOTE 5

~

1\----11

~--~---+--~---+--~~~~~---+--------

_TClAV
TClAX -

AlE (8288 OUTPUT)

Tw

r'........

.,r--,j

I--

~___

~----

TCHLl

.1

r-I

~----+_--+_+__+--_+----~---.J-----j !--TR1VCL

~§(:~~~~~~

ROY (8284 INPUT)

TRYLCL_

_

-TCHRYX

TYHSH-t

READ CYCLE
TCLAV-I
AD7-ADO

F

..... TeLAX

I-- TRYHCH

-TClAZ

I--

i

TDVCL-~I--TCLDX~

---,('1'

}-W--'-FL-OA-T

AD,-AD,

TAZRL-

L

DATA IN
TCLRH

FLOAT-I
I--+--i+-'TRHAV~

----------~----~~
RD
_ _ _ _ _T_cH_D_T_L_-_1'"'""{

~f.T~C-L+,f-R--1L+-':~~~.~~~T-R-L-RH-_-_~-_-_-_~-_-_-_..I-i'l\~\

TCLML--

-

TCLMH-

8288 OUTPUTS
~~I--

SEE NOTES 5,6

TCVNV-

________

____________________- J

f
TCVNX-

3-101

~

~_.J

It--

-

TCHDTH

inter

iAPX 88/10

- WAVEFORMS (Continued)
T,

BUS TIMING-MAXIMUM
VCH
MODE SYSTEM
CLK
(USING 8288)
VCL

~

f----J

T,

r--.

1'-------/

T,

r--.

ii. 51. so (EXCEPT HALn
WRITE CYCLE

~

~" "---.J~
-----..i!IIIIf
----_.
(1M

r-

rClAY--

~

-

TCL~~j.:-

TCLAX

h-

AD7- AD o

f--TCLSH

TCLMH-

-TCLML

~

note 8)

TCHDX-

r-

TCVNX-

J-

DATA

-

fCVNV-DEN

8288 OUTPIJTS
see NOTES 5,6

Tw

AMWC OR AIOWC

_

{TCLML

-

J_TCLMH

INTA CYCLE
A15- A8
(SEE NOTES 3,4)

J

FlOAT

-

t- -

TCLMCH-

DTIR

FLOAT

r-1/

FLO~
-I \I-

{r"·'

TCLML-

INTA

FLOAT

\

/{TTZ

TCLMCL

MCEI

8288 0lm'UlS
SEE NOTE~ 5,6

CASCADE ADDR

J

TSVMCH-

I'DEN

RESERVED FOR
\

~

-

/

I-TCLDX

TDVCL POINTER

I

FLOAT

\

I

~1

TCVNV

-~MH

DEN
TCVNX-

SOFTWARE
HALT - (DEN.., vOL;IUj,mme,iORC,MWfC.AMWc;IOWC,~.iN"fA, DT/A = VOH.

INVALID ADDRESS

relAV

/r---------"""T' -------

~

\'----~

NOTES:

1. ALL SIGNALS SWITCH BETWEEN YOH AND VOL UNLESS OTHERWISE

SPECIFIED.
2. ROY IS SAMPLED NEAR THE END OF T2, T3. Tw TO DETERMINE IF Tw

MACHINES STATES ARE TO BE INSERTED
3 CASCADE ADDRESS IS VALID BETWEEN FIRST AND SECOND INTA
CYCLES.
4. TWO INTA CYCLES RUN BACK·TO·BACK. THE 8088 LOCAL ADDRfDATA
BUS IS FLOATING DURING 80TH INTA CYCLES. CONTROL FOR
POINTER ADDRESS IS SHOWN FOR SECOND INTA CYCLE.
5. SIGNALS AT 8284 OR 8288 ARE SHOWN FOR REFERENCE ONLY.
6. THE ISSUANCE OF THE 8288 COMMAND AND CONTROL SIGNALS
(M1Il!C, MWTC, AMWl:, lORe, rowe, A1llWe, INTA AND DEN) LAGS THE
ACTIVE HIGH 8288 CEN.
7. ALL TIMING MEASUREMENTS ARE MADE AT 1.SV UNLESS OTHERWISE
NOTED

8, STATUS INACTIVE I~ STATE JUST PRIOR TO T"

3-102

\._-----

r--

----

TCHDTH

iAPX 88/10

WAVEFORMS (Continued)
BUS LOCK SIGNAL TIMING
(MAXIMUM MODE ONLy)

ASYNCHRONOUS
SIGNAL RECOGNITION

Any elK CYCle----j

Any elK Cycle

_I

CLK

LOCK

NOTE 1 SETUP REQUIREMENTS FOR ASYNCHRONOUS
SIGNALS ONLY TO GUARANTEE RECOGNITION AT NEXT elK

REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

~
I

PrevIous grant

A19/SeA:l~

11-----------------1

A07-400

COPROCESSOR

~:~ ~'---------------~

(SEE NOTE 1)

NOTE 1 THE COPROCESSOR MAY NOT DRIVE THE BUSSES OUTSIOE1HE REGION
SHOWN WITHOUT RISKING CONTENTION

HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLy)
_'CLKCVCLE-

CLK

~
_I

_T"VC"

(SEE

NOT",

"\~'-'"

"O'"~
"'OA \--_ _ _ _ _ _ _-\\--_ _-+---' I-r-T-ICI--'"_AV_ _ _--I\--_ _ _

I-------_--<~----_{
.,..

1"'-fCLAZ

---i

J

r---I

C_OP_R-i0~,I_~E-SS-O-R-----~

' -_ _ _ _ _

3-103

':

~{~I_,'-j"I_V_ _ _

iAPX 88/10
iAPX 86/10, 88/10
INSTRUCTION SET SUMMARY
DATA TRANSFER
MOV

MlVI

76543210

11oo010dwlmod reg

Immedlale 10 .e!l'Slerimemorv

j1

I 0

11

(I

Immed,ale 10 1~!I'S1et

(I

0 11

'II

1 1 w reg

I , (I 1 0

(I (I (I

w

I\tcurnulator 10 memory

1 (I 1 0 0 (I 1

'II

Reg,slerimemor, 10 segment reglsler

, 000 11 I0

Memory 10 accumulalo,

7650210

76$4321(}

ReQ,slellmem~!yl0·tlomTeg,sle(

I mild 0 0 0

I
I

,1m
I m

I

I

I

I
a\ld, low

mod 0 reg

!lala ,t

'II

1

I

~d(jr h~
add, hlqtl ]

'II

1

Demment

DEC

1654321(1

-di;ia~
~~~Io ,I

165431111

Compare

eMP

~11(!

regIster

1001 I 10 d

1/1

100000 S

1/1

I mOd

Immed,ale""lh reQ"lel memOly

PUSH

AASI\SCI13dIUSIIOlsubllaCI~

Immed'~le

mOd!!O~

11111111

Register/memory

Reg,ster

01010 reg

~

Segment register

wllh ilHLlIII"lalor

OASDeClmal.dlusllnlsublla~1

~

MUL MultIply [unslgnedl

II

AAM ASCII adlusl 10'

01011

XCHG

reg

11oo001lwimod

ReI/'SItr wIth accumulator

~oregl

lN~lnpYI

mulllpl~

I I 0 I 0 I 0 0

0000 I 0 I 0

II 1 I lOT I '" ImOd 110 I rn:J

~'I",lmOdllllm

I

Gl010101100001~
~
~O 0 t , ~

leg~

from

I

FlJedp0ri

li:1 100 \ 0 w

VarrablepoTI

~

OUT-OutllutiO
fl~ed

1 101 I W ImOd 100 1m

'OIVlnleg~rd'vldelslgned'

CWO Conve!l worD 10 double wo'd

hCblllg'

!

IIIV Olv,deluns,gnedl

CBWConvellbylelowo.(j

R/!gl51erlmemory w'lh register

dala Ifsw 01
data I!W I

I 1 1 101 I w mod 10 I 1m

AADASClladIUSllo,d,v.de

~

Segmenl register

reg

mOd 1 I 11'm

0011110w

IMUL Inlege, multIply Is,gnedl

10001111 ,modO 0 0 ,m

Register/memory

16543210

~

SegmeI11reg,sterto'e9'sler,memoIV [i0001-10~~

PUll!

1654JlIII

11 I I 101 I w :mOdO \ I

JIIEGChanges'gn

Reg,sle, memOly

11m

16543110

~J.6.iil~

I

i

port

1 I t 001 I w

LOGIC

I

I 1 I 1 1 0 11 '" I~0~_O_10--I~

1II0T IlIve"
pori

]

$Hl'SAL SMI

IO~'(~1 ~"Ihnwtoc

lelt

~-O~O~~_ ~

moo! 0 0 l:nl

1

VaflablepO!1

SHRShlltloq'la:llq~1

~~~

XlUTlansfatehyleloAL

SAftS~dla'dhmell{""ght

[2101_00;_~~

AIlLRolafelel1

~OOvwmOdOOOlm

UA-loadEA'oreglsler
lDS Loadpomler laDS

mM

r~g

I! 000101

mod

leg~

111000100 Imod

UMf~loaa

l' 00111 11 I

AH with !lags

r m

10001101

UI=loadpolnlerloES

IAMF SloreAHlnl0 !Jags
PUIMF-Pushl!ags

1,00111101

POI'f=Popflags

110011101

1,0011 1 001

I

reg

1m

I

HOM Rolale lIynt
ACL Rotate

[1"1 0 I 0 0 v w mOd 0 0 1 I m

Ih'ou~n

cafly flag lefl

ACRRolillelhloughca"y"ghl

AND

1 I 0 I 00 v w mod 010 I'm

(!~~-.2_~~

And

Regmemo,yand,eqISlelloelthe'ioo,ooodwl~
Immea,alel0,eg,ste,memOly

il0000oowimodlOO r'm

Immedlille10 Jnumulalol

l~~~

1

dala

I

data ,1 w 1

I

~ata

I

data 11 wI

I

data II wI

I

__d_al~l~~

ARITMMETIC
ADD

A~

Reg Imemory W'lh reglSler10 ellher
Immed,ate 10

reg'slerlmemOI~

Immed'aleto accumulal01

AUC

Add wllhmt¥

Reg Imemory w,1h reg'SIer 10 Mhel

DR

Dr

Reg Imemo,y and leq011 Status Word does not set
the associated ih-service bit. These words are located in two adjacent memory locations in the register file.

Trigger Mode
The four external interrupt pins can be programmed
in either edge- or level-trigger mode. The control
register for each external source has a level-trigger
mode (LTM) bit. All interrupt inputs are active HIGH.
In the edge sense mode or the level-trigger mode, the
interrupt request must remain active (HIGH) until the
interrupt req uest is acknowledged by the 80188 CPU.
In the edge-sense mode, if the level remains high
after the interrupt is acknowledged, the input is disabled and no'further requests will be generated. The
input level must go LOW for at least ol]e clock cycle to
reenable the input. In the level-trigger mode, no such
provision is made: holding the interrupt input HIGH
will cause continuous interrupt requests.

3-134

210706-004

iAPX 188

Interrupt Vectoring
The 80188 Interrupt Controller will generate interrupt vectors for the integrated OMA channels and
the integrated Timers. In addition, the Interrupt Controller will generate interrupt vectors for the external
interrupt lines if they are not configured in Cascade
or Special Fully Nested Mode. The interrupt vectors
generated are fixed and cannot be changed (see
Table 4).

Interrupt Request Register
The internal interrupt sources have interrupt request
bits inside the interrupt controller. The format of this
register is shown in Figure 24. A read from this register yields the status of these bits. The TMR bit is the
logical OR of all timer interrupt requests. DO and 01
are the interrupt request bits for the OMA channels.

The state of the external interrupt input pins is also
indicated. The state of the external interrupt pins is
not a stored condition inside the interrupt controller,
therefore the external interrupt bits cannot be written. The external interrupt request bits show exactly
when an interrupt request is given to the interrupt
controller, so if edge-triggered mode is selected, the
bit in the register will be HIGH only after an inactiveto-active transition. For internal interrupt sources,
the register bits are set when a request arrives and
are reset when the processor acknowledges the
requests.

Interrupt Controller Registers
The Interrupt Controller register model is shown in
Figure 23. It contains 15 registers. All registers can
both be read or written unless specified otherwise.
In-Service Register
This register can be read from or written into. The
format is shown in Figure 24. It contains the InService bit for each' of the interrupt sources. The
In-Service bit is set to indicate that a source's service
routine is in progress. When an In-Service bit is set,
the interrupt controller will not generate interrupts to
the CPU when it receives interrupt requests from
devices with a lower programmed priority level. The
TMR bit is the In-Service bit for all three timers; the
DO and 01 bits are the In-Service bits for the two OMA
channels; the 10-13 are the In-Service bits for the
external interrupt pins. The IS bit is set when the
processor acknowledges an interrupt request either
by an interrupt acknowledge or by reading. the poll
register. The IS bit is reset at the end of the interrupt
service routine by an end-of-interrupt command issued by the CPU.

Mask Register
This is a 16-bit register that contains a mask bit for
each interrupt source. The format for this register is
shown in Figure 24. A one in a bit position corresponding to a particular source serves to mask the
source from generating interrupts. These mask bits
are the exact same bits which are used in the individual control registers; programming a mask bit using
the mask register will also change this bit in the
individual control registers, and vice versa.

80188
INTO

INT

,

8259A
PIC

iNTA

INTAO

Figure 22. Cascade Mode Interrupt Connection

3-135

210706-004

iAPX 188

Priority Mask Register
This register is used to mask all interrupts below
particular interrupt priority levels. The format of this
register is shown in Figure 25. The code in the lower
three bits of this register inhibits interrupts of
priority lower (a higher priority number) than the
code specified. For example, 100 written into this
register masks interrupts of level five (101), six (110),
and seven (111). The register is reset to seven (111)
upon RESET so all interrupts are unmasked.

OFFSET
INT3 CONTROL REGISTER

3EH

INT2 CONTROL REGISTER

3CH

INT1 CONTROL REGISTER

3AH

INTO CONTROL REGISTER

38H

DMA 1 CONTROL REGISTER

36H

DMA 0 CONTROL REGISTER

34H

TIMER CONTROL REGISTER

32H

INTERRUPT STATUS REGISTER

30H

INTERRUPT REQUEST REGISTER

2EH

IN·SERVICE REGISTER

2CH

PRIORITY MASK REGISTER

2AH

MASK REGISTER

28H

POLL STATUS REGISTER

26H

POLL REGISTER

24H

EOI REGISTER

22H

Interrupt Status Register
This register contains general interrupt controller
status information. The format of this register is
shown in Figure 26. The bits in the status register
have the following functions:
DHLT:

DMA Halt Transfer; setting this bit halts all
DMA transfers. It is automatically set
whenever a non-maskableinterrupt occurs,
and it is reset when an IRET instruction is
executed. The purpose of this bit is to allow
prompt service of all non-maskable interrupts. This bit may also be set by the CPU.

IRTx:

These three bits represent the individual
timer interrupt request bits. These bits are
used to differentiate the timer interrupts,
since the timer IR bit in the interrupt request register is the "OR" function of all
timer interrupt requests. Note that setting
anyone of these three bits initiates a,n interrupt request to the interrupt controller.

Figure 23. Interrupt Controller Registers
(Non-iRMX 86 Mode)

15

I

o

14

10

0

o

I

9
0

I

0

~

I

~

I

N

I

~

w

DO

Figure 24. In-Service, Interrupt Request, and Mask Register Formats

15

o

14
J

0

,3

I

2

1

0

o

I PRM21 PRM1J PRMO

0

IIRT2

I

Figure 25. Priority Mask Register Format,

15

14

7

o

I0 I

5

4

0

o

2
I

1

I IRTtI

0
IRTO

I

Figure 26. Interrupt Status Register Format

3-136

210706-004

iAPX 188

Timer, DMA 0, 1; Control Registers
These registers are the control words for all the internal interrupt sources. The format for these registers
is shown in Figure 27. The three bit positions PRO,
PR1, and PR2 represent the programmable priority
level of the interrupt source. The MSK bit inhibits
interrupt requests from the interrupt source. The
MSK bits in the individual control registers are the
exact same bits as are in the Mask Register; modifying them In the individual control registers will also
modify them in the Mask Register, and vice versa.
INTO-INT3 Control Registers
These registers are the control words for the four
external input pins. Figure 28 shows the format of the
INTO and INn Control registers; Figure 29 shows the
format of the INT2 and INT3 Control registers. In
cascade mode or special fully nested mode, the control words for INT2 and INT3 are not used.

level is preceded by an inactive-to-active
transition on the line. In both cases, the
level must remain active until the interrupt
IS acknowledged.

MSK:

Mask bit, 1

=

mask; 0

=

nonmask.

"
C:

Cascade mode bit, 1 = cascade; 0 = direct

SFNM:

Special fully nested mode bit, 1 = SFNM

EOI Register
The end of the interrupt register is a command register which can only be written into. The format of this
register IS shown in Figure 30. It initiates an EOI
command when written to by the 80188 CPU.

The bits in the various control registers are encoded
as follows:

The bits in the EOI register are encoded as follows:

PRO-2:

Sx:

LTM:

Priority programming information. Highest
priority = 000, lowest priority = 111.
Level-trigger mode bit. 1 = level-triggered;
edge-triggered. Interrupt Input levels
are active high. In level-triggered mode, an
interrupt is generated whenever the externalline is high. In edge-triggered mode, an
interr~pt will be generated only when this

o=

15

14

o

0

Encoded information that specifies an interrupt source vector type as shown in
Table 4. For example, to reset the In-Service
bit for DMA channel 0, these bits should be
set to 01010, since the vector type for DMA
channel 0 is 10. Note that to reset the single
In-Service bit for any of the three timers, the
vector type for timer 0 (8) should be written
in this register.

4

3

2

1

0

2

1

0

2

1

0

Figure 27. Tlmer/DMA Control Register Formats

15

5

14

o

4

3

I SFNMI

Figure 28. INTO/INT1 Control Register Formats

15

14

5

o

0

o

4

3

ILTMIMSKlpR21PR11pROI

Figure 29. INT2IINT3 Control Register Formats
3-137

210706-004

intJ

iAPX 188

NSPEC/: A bit that determines the type of EOI comSPEC
mand. Nonspecific = 1, Specific = O.
Poll and Poll Status Registers
These registers contain polling information. The format of these registers is shown in Figure 31. They can
only be read. Reading the Poll register constitutes a
software poll. This will set the IS bit of the highest
priority pending interrupt. Reading the poll status
register will not set the IS bit of the highest priority
pending interrupt; only the status of pending interrupts will be provided.
Encoding of the Poll and Poll Status register bits are
as follows:

Sx:

Encoded information that indicates the
vector type of the highest priority interrupting source. Valid only when INTREQ = 1.

Because of pin limitations caused by the need to
interface to an external 8259A master, the internal
interrupt controller will no longer accept external
inputs. There are however, enough 80188 interrupt
controller inputs (internally) to dedicate one to each
timer. In this mode, each timer interrupt source has
its own mask bit, IS bit, and control word.
The iRMX 86 operating system requires peripherals
to be assigned fixed priority levels. This is incompatible with the normal operation of the 80188 interrupt controller. Therefore, the initialization software
must program the proper priority levels for each
source. The required priority levels for the internal
interrupt sources in iRMX mode are shown ill Table
16.

Table 16. Internal Source Priority Level

INTREQ: This bit determines if an interrupt request is
present. Interrupt Request = 1; no Interrupt
Request = O.

Pr.iority Level

Upon reset, the 80188 interrupt controller will be in
the non-iRMX 86 mode of operation. To set the controller in the iRMX 86 mode, bit 14 of the Relocation
Register should be set.

15

I:~bl

14

o

I

Timer 0
(reserved)
OMAO
OMA1
Timer-1
Timer 2

3
4
5

iRMX 86 COMPATIBILITY MODE
This mode allows iRMX 86-80188 compatibility. The
interrupt model of iRMX 86 reqUires one master and
multiple slave 8259As in cascaded fashion. When
iRMX mode is used, the internal'80188 interrupt controller will be used as a slave controller to an external
master interrupt controller. The internal 80188 resou'rces will be monitored through the internal interrupt controller, while the external controller
functions as the system master interrupt controller.

Interrupt Source

0
1
2

These level assignments must remain fixed in the
iRMX 86 mode of operation.

iRMX 86 Mode External Interface
The configuration of the 80188 with respect to an
external 8259A master is shown in Figure 32. The
INTO input is used as the 80188 CPU interrupt input.
INT3 functions as an output to send the 80188, slaveinterrupt-request to one of the 8 master-PIC-inputs.

0

13

I

0

0

S4

S3

S2

S1

53

52

S1

II
SO

Figure 30. EOI Register Format
15

I:~

14

13

I I
0

5

4

I I I
0

0

54

0

I

so

I

Figure 31. Poll Register Format
3-138

210706-004

iAPX 188

8259A
MASTER
INTA
80188 INT. IN

<==

REQUESTS FROM
OTHER SLAVES

IRO

INT

1

-

IR7
CASo-2

80188

~~

INTO

INT2
INT3

I

SLAVE SELECT

INn

I

-

")

CASCADE
ADDRESS DECODER

80188 SLAVE INTERRUPT OUTPUT

Figure 32. iRMX 86 Interrupt Controller Interconnection

Correct master-slave interface requires decoding of
the slave addresses (CASO-2). Slave 8259As do this
internally. Because of pin limitations, the 80188 slave
address will have to be decoded externally. INT1 is
used as a slave-select input. Note that the slave vector address is transferred internally, but the READY
input must be supplied externally.
INT2 is used as an acknowledge output, suitable to
drive the INTA input of an 8259A.

Specific End-of-Interrupt
In iRMX mode the specific EOI command operates to
reset an in-service bit ofa specific priority. The user
supplies a 3-bit priority-level value that points to an
in-service bit to be reset. The command is executed
by writing the correct value in the Specific EOI register at offset 22H.

Interrupt Controller Registers
in the iRMX 86 Mode

Interrupt Nesting
iRMX 86 mode operation allows nesting of interrupt
requests. When an interrupt is acknowledged, the
priority logic masks off all priority levels except
those with equal or higher priority.

Vector Generation in the iRMX 86 Mode
Vector generation in iRMX mode is exactly like that of
an 8259A slave. The interrupt controller generates an
8-bit vector which the CPU multiplies by four and
uses as an address into a vector table. The significant
five bits of the vector are user-programmable while
the lower three bits are generated by the priority
logic. These bits represent the encoding of the
priority level requesting service. The significant five
bits of the vector are programmed by writing to the
Interrupt Vector register at offset 20H.
3-139

All control and command registers are located inside
the internal peripheral control block. Figure 33
shows the offsets of these registers.
End-of-Interrupt Register
The end-of-interrupt register is a command register
which can only be written. The format of this register
is shown in Figure 34. It initiates an EOI command
when written by the 80188 CPU.

The bits in the EOI register are encoded as follows:

Lx:

Encoded value indicating the priority of the
IS bit to be reset.

In-Service Register
This register can be read from or written into. It
contains the in-service bit for each of the internal
210706-004

inter

iAPX 188

interrupt sources. The format for this register is
shown in Figure 35. Bit positions 2 and 3 correspond
to the DMA channels; positions 0, 4, and 5 correspond to the integral timers. The source's IS bit is set
when the processor acknowledges its interrupt request.

prx:

3-bit encodE;ld field indicating a priority l.evel
for the source; note that each source must
be programmed at specified levels.

msk:

mask bit for the priority level indicated by prx
bits.
OFFSET

Interrupt Request Register
This register indicates which internal peripherals
have interrupt requests pending. The format of this
register is shown in Figure 35. The interrupt request
bits are set when a request arrives from an internal
source, and are reset when the processor acknowledges the request.
Mask Register
This register contains a maSk bit for each interrupt
source. The format for this register is shown in Figure 35. If the bit in this register corresponding to a
particular interrupt source is set, any interrupts from
that source will be masked. These mask bits are
exactly the same bits which are used in the individual
control registers, i.e., changing the state of a mask
bit in this register will also change the state of the
mask bit in the individual interrupt control register
corresponding to the bit.
Control Registers
These registers are the control words for all the internal interrupt sources. The format of these registers is
shown in Figure 36. Each of the timers and both of
the DMA channels have their own Control Register.
The bits of the Control Registers are encoded as
follows:

LEVEL 5 CONTROL REGISTER
(TIMER 2)

3AH

LEVEL 4 CONTROL REGISTER
(TIMER 1)

38H

LEVEL 3 CONTROL REGISTER
(DMl1)

36H

LEVEL 2 CONTROL REGISTER
(DMAO)

34H

LEVEL 0 CONTROL REGISTER
(TIMER 0)

32H

INTERRUPT STATUS REGISTER

30H

INTERRUPT REQUEST REGISTER

2EH

IN-SERVICE REGISTER

2CH

PRIORITY·LEVEL MASK REGISTER

2AH

MASK REGISTER

2BH

SPECIFIC EOI REGISTER

22H

INTERRUPT VECTOR REGISTER

20H

Figure 33. Interrupt Controller Registers
(iRMX 86 Mode)

Figure 34. Specific EOI Register Format

15

14

13

I I I I
Figure 35. In-Service, Interrupt Request, and Mask Register Format
3-140

210706-004

inter

iAPX 188

Interrupt Vector Register
This register provides the upper five bits of the interrupt vector address. The format of this register is
shown in Figure 37. The interrupt controller itself
provides the lower three bits of the interrupt vector
as determined by the priority level of the interrupt
request.
The format of the bits in this register is:
5-bit field indicating the upper five bits of the
vector address.
Priority-Level Mask Register
This register indicates the lowest priority-level interrupt which will be serviced.

tx:

The encoding of the bits in this register is:
mx:

3-bit encoded field indication priority-level
value. All levels of lower priority will be
masked.

Interrupt Status Register
This register is defined exactly as in non-iRMX mode
(see Figure 26).

Interrupt Controller and Reset
Upon RESET, the interrupt controller will perform the
following actions:
• All SFNM bits reset to 0, implying Fully Nested
Mode.
• All PR bits in the various control registers set to 1.
This places all sources at lowest priority (level
111 ).
• All LTM bits reset to 0, resulting in edge-sense
mode.
All Interrupt Service bits reset to O.
All Interrupt Request bits reset to O.
All MSK (Interrupt Mask) bits set to 1 (mask).
All C (Cascade) bits reset to 0 (non-cascade).
All PRM (Priority Mask) bits set to 1, implying no
levels masked.
• Initialized to non-iRMX 86 mode.

•
•
•
•
•

Figure 36. Control Word Format

Figure 37. Interrupt Vector Register Format

Figure 38. Priority Level Mask Register
3-141

210706-004

intJ

iAPX 188

16 MHz

r1
0

Vee

f1
.l

Xl

X2

-

UCS

.---

RES

f~

~ 82::8~R

ADD-AD7,
A8-A1S
ALE t--

I'<-

'="- ~

STB

OE

80188

I'm
WR

I
T

1

MCS0-3
SRDY

RESET
ROM

ADDRESS

1
1
PROGRAM
RAM

r*SV

AROY
NMI
HOLD

~

.

~
~

~

LOW RAM

Tr

LCS

I

TMR INO t--*SV

{

-.

TMROUTO

CLOCK

~

~

8286 OR
8287
TRANSCEIVER
T

~

PCSO
Al
A2

Ft=:i

~

1---+

~

00-07

K==>Ji.;;
T ERMINAL

110

~

I

INTO

DISK
INTERFACE
HARDWARE

INT1
PCS4
ORQO

Figure 39.

,

SERIAL

OE

~8DIS K

Typical iAPX 188 Computer
3-142

210706-004

iAPX 188

16 MHz

rD~
Vee

n

Xl

X2
UCS

CS

FlO
RES

.I

r----V"

8282 OR
8283
LATCH

OE

sTB
STB

DE

•

ALE
LCS

-;:-

RESET
ROM

L1f
Ilb

~

.

'

lOW
RAM

CS

WR

(\

b

ADo-AD7
A8:,.A15

8282 OR
8283
LATCH

ADDRESS
BUS

STB

OE

f

t

~~sTB
OE

80188

NMI
HOLD

R

'-~

8286 OR
8287
TRANSCEIVER

:>DATABUs

OE

T

MULTI
MAST
SYST EM
BUS

ER

r

DT/R
ClK
' - - - ALE

CLKOUT

SO-S2

,-----..--r- t-

f-----

DEN
8288
BUS
CONTROLLER

SO-S2

CEN
lOB

AEN

-;:-

b
PCSO
PCS1

AADY

1

J
SO-S2

AEN
8289

CLK AR':I:ER

====r ./

:>

SYSB/RESB
lOB

lOCK
SRDY

BUS CONTROL
COMMANDS

LOCK

Fa-r~

RESB

~~~Ti~~~ION

~~5V
XACK

,

Figure 40. Typical iAPX 188 Multi·Master Bus Interface
3-143

210706-004

IAPX 188

PACKAGE

NOTE: The lOT 3M Textool 68-pin JEOEC Socket

The 80188 is housed in a 68-pin, leadless JEOEC type
A hermetic chip carrier. Figure 41 illustrates the
package dimensions.

is required for ICE™ operation. See Figure 42 for
details.

[.055
:N5

. Figure 41. 80188 JEDEC Type A Package

3-144

210706-004

inter

iAPX 188

1

~ (30;3) sa~
1210

GUIDE BOSS

--

3PLCS~~ r-lTrIHIDDffBa~HEJLHE4D~~~1\-'

INDEX

'l-~ FRONT

PC BOARD PATTERN
'i.

SOCKET ORIENTATION PIN ~"")-

.rP1N NO 1

~:tt(tttt~ ..
p. ~~~E~E;ATlON -::::: FRONT r
;..:../

DEVICE PADS ~
SHOWN FOR -~
CONTACT,
~~J
LOCATION ~

PIN CLR HOLE:r-:;

+.

FORI .021 OIA

~

--,:+(O.741~ ~-tt.

i

/

I

• . Iii

..r:1

I
(2' : ) TYP

~~i~-.~~T p~ ~-:JJ.)JJ 'I ~~ l
...Q!!.----I
(038)

r--

IIJ

O~~
(0.51)

CONTACT TAIL

~ .l.•• , . . .•.
'i.

ALUMINUM LID

100
(25.4)

~

1

(HEATSINK PROVISIONS OPTIONAL)
TEST PROBE POINT

r --

\

'..--.-

CLOSED

~

'-..

\

1.00

-..j r-(2")TY·

OPEN

e+---(2~2)-~
8 spes" 100 TOl NON ACCUM TVP .. PLes
(2.")

NOTE: PhYSical dimenSions shown are for reference only. Please consuU 3M Textoetl tor complete informatIOn on the socket.

Figure 42. Textool 68 Lead Chip Carrier Socket

3-145

210706-004

inter

iAPX 188
--NOTICE: Stresses above those listed under
"Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature under Bias ..... O°C to 70°C
Storage Temperature ........... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .............. -1.0V to + 7V
Power Dissipation ........................ 3 Watt
D.C. CHARACTERISTICS (TA ~ 0°-70°C. Vcc ~ 5V < 10%)
Symbol

Parameter

V,L

Input Low Voltage

V,H

Input High Voltage
(All except Xl and (RES)

V,H1

Input High Voltage (RES)

VOL

Output Low Voltage

VOH

Output High Voltage

Icc

Power Supply Current

Min.

Max.

Units

- 0.5

+0:8

Volts

2.0

Vcc + 0.5

Volts

3.0

Vee + 0.5

Volts

0.45

Volts

2.4

Volts
550
450

mA

Test Conditions

la ~ 2.5 mA for SO-S2
la = 2.0 mA for all other outputs
loa ~ -400 MA
Max measured at TA
TA

III

Input Leakage Current

±10

MA

OV

ILO

Output Leakage Current

±10

MA

0.45V

VCLO

Clock Output Low

0.6

Volts

I. = 4.0 mA

Volts

loa ~ -200 MA

VCHO

Clock Output High

VCLl

Clock Input Low Voltage

-0.5

VCHI

Clock Input High Voltage

3.9

C'N
C,O

4.0
0.6

Volts

Vcc + 1.0

Volts

Input Capacitance

10

pF

I/O Capacitance

20

pF

V,N

<

<

<

~
~

O°C
70°C

Vcc

Vour

<

Vcc

,

,

PIN TIMINGS
A.C. CHARACTERISTICS

(TA = 0°-70°C. Vee

= 5V

± 10%)

80188 Timing Requirements All Timings Measured At 1.5 Volts Unless Otherwise Noted.
Symbol
TOVCL

If -T-CLOX
.

Parameter

Min.

Max.

Units

Data in Setup (AID)

20

ns

Data

10

ns

In

Hold (AID)

TARYHCH

Asynchronous Ready
(AREADY) active setup
time'

20

ns

TARYLCL

AREADY inactive setup
time

35

ns

Asynchronous Ready
Inactive hold time

15

ns

TCHARYX

AREADY hold time

15

ns

TSRYCL

Synchronous Ready
(SREADY) transition setup
,
time

TARYCHL

20

ns

TCLSRY

SREADY transition hold
time

15

ns

THVCL

HOLD Setup'

25

ns

T,NVCH

INTR. NMI. TEST. TIMERIN.
Setup'

25

ns

T,NVCL

DRao. ORal. Setup'

25

ns

-

Test Conditions

.--

'To guarantee recognition at next clock.
3-146

210706-004

iAPX 188

A.C. CHARACTERISTICS (Continued)

80188 Master Interface Timing Responses
80188 (8 MHz)
Symbol
TCLAV

Parameters
Address Valid Delay

Min.
5

80188-6 (6 MHz)

Max.

Min.

55

5

Max.

Units

63

ns
ns

TCLAX

Address Hold

TCLAZ

Address Float Delay

TCHCZ

Command Lines Float Delay

TCHCV

Command Lines Valid Delay
(after float)

TLHLL

ALE Width

TCHLH

ALE Active Delay

35

44

ns

TCHLl

ALE Inactive Delay

35

44

ns

TLLAX

Address Hold to ALE Inactive

TCLDV

Data Valid Delay

10

TCLDOX

Data Hold Time

10

TWHDX

Data Hold after WR

TCVCTV

Control Active Delay 1

10

70

10

87

ns

TCHCTV

Control Active Delay 2

10

55

10

76

ns

TCVCTX

Control Inactive Delay

5

55

5

76

ns

TCVDEX

DEN Inactive Delay
(Non-Write Cycle)

10

70

10

87

ns

TAlRL

Address Float to RD Active

0

TCLRL

RD Active Delay

10

70

10

87

ns

TCLRH

RD Inactive Delay

10

55

10

76

ns

TRHAV

RD Inactive to Address Active

TCLHAV

HLDA Valid Delay

TRLRH

RDWidth

2T cLcL-5O

2T CLCL-50

ns

TWLWH

WRWidth

2TCLCL-40

2TCLCL-4O

ns

TAVAl

Address Valid to ALE Low

TCLCH-25

TCLCH-45

TCHSV

Status Active Delay

10

55

10

76

ns

TeLsH

Status Inactive Delay

10

65

10

76

ns

T CLTMV

Timer Output Delay

60

75

ns

TeLRo

Reset Delay

60

75

' ns

10

10
TCLAX

35

TeLAX

45
55
TCLCL-35

ns

56

ns

76

ns
ns

ns

TCHCL-3O
10

44

55

10

ns

ns

0

ns

TCLCL-50

TCLCL-4O
50

5

ns
ns

TCLCL-5O

TCLCL-4O

5

44

TCLCL-35

TCHCL-25

67

ns

ns

Queue Status Delay
Status Hold Time

10

10

' ns

T AVCH

Address Valid to clock high

10

10

ns

44

100 pF max

ns

TeHQSV
T CHDX

35

Test Conditions
CL = 20-200 pF all outputs

80188 Chip-Select Timing Responses
Symbol

Parameter

Min.

TeLesv

Chip-Select Active Delay

Texesx

Chlp-Selct Hold from
Command Inactive

35

TCHesx

Chip-Select Inactive Delay

5

Max.

Min.

66

Max.

Units

80

ns

35
5

35

3-147

. Test Conditions

ns
47

ns

210706-004

iAPX 188 .

A.C. CHARACTERISTICS (Continued)
80188 CLKlNRequirements
Symbol
TCKIN

-

80188·6 (6 MHz)

80188 (8 MHz)
Parameters

ClKIN Period

Min.

Max.

Min.

Max.

Units

62.5

250

83

250

ns

Test Conditions

TCKHL

ClKIN Fall Time

10

10

ns

TCKLH

ClKIN Rise Time

10

10

ns

1.0 to 3.5 yolts

TCLCK

ClKIN Low TIme

25

33

ns

1.5 volts

TCHCK

ClKIN High TIme

25

33

ns

1.5 Yolts

-

3.5 to 1.0 Yolts

80188 CLKOUT Timing (200 pF load)
Symbol

Parameter

Tclco

ClKIN 10 ClKOUT Skew

Min.

TCLCL

ClKOUT Period

TCLCH

ClKOUT low Time

TCHCL

ClKOUT High Time

TCH1CH2

ClKOUT Rise Time

15

15

ns

1.0 to 3.5 Yolts

TCL2CL1

CLKOUT Fall TIme

15

15

ns

3.5 to 1. volts

Mix.

Min.

50
125

500

'h TCLCL-75
'h TCLCL-75

167

Max.

Units

62.5

ns

500

ns

Test Conditions

'/2 TCLCL-75

ns

1.5 yolts

'h TCLCL-7.5

ns

1.5 volts

3-148

21070&-004

iAPX 188

WAVEFORMS
MAJOR CYCLE TIMING

~

T
CLKOU

T,

-T~'~~C~JAru

~

!-----

_TCHS'

TCI~AV ___

1\

l-------r

~ITCHCL

1_

_

",Ie,.,.

u,

. -1-'

f-7

-

/r-

-~: ~t~~ ::::
~AO

DATAOU'

1\

INTA CYCLE
DTI

II

-- f

-

.

, ,

..

/

,....... ,

-=:H;

TCl

-ITLLAl

R

-

~ ___ TCLAZ

'
FLOAT

'1
TCHCTV

II_Tn",..,

Ri5.~~
I:5Ht: =

V OH

VOL

,. . . . _[1

SOFnYARE HALT-11!!~ ~ Vo
RD. WR. INTA. DEN ~ Vo H

"
,
,

PCS
MCS
,LCS
lieS

TCLAV_

-

,~

I FLOAT
I___ TCHCTV

1\

1-

...1

V !j
1--1

TCVD!'X-

~

N

I

:::~

TCVC

_';CLDX

A'~'~

- ~I

po;: r"'--iiI

-

\

1

A

-

TCLAZ,_

I~

TOVCTV-

ADI5-ADo

----

.- ----

"~"-1~

iii

Rjj.INTA.
DT/R ~ VOH

~.'::.~'::.L.

'I

~~

T'''~':

WRITE CYCLE

~

~TA' ~~'

1 :LAV-ADI5-ADo

\~. ----

-

S,-S3

S,

TCH~

r--\

"'Tci:CH

-TC~LAX~r(;LLJ'~

'

,.

A LE

' ~,

~~

~~

t

'I~

TCHC! ~X_

_TCLCSV

TCXCSX-

3-149

I-

-

210706-004

iAPX 188

WAVEFORMS (Continued)
MAJOR CYCLE TIMING (Continued)

CLKOUT

~. ~~--~r-----+----+~----r----+~

SHE/S7.A191S8-A111/S3

,r--

ALE

TCHLH

FLOAT

Ao,s-ADo

READ CYCLE

,
TC~L~--~~--+--TRL~IH-----~--~-~

pcs,
Mel! ----I-~I

LeI,
UCS

NOTES:
1. Following a Write cycle, the Local Bus is floated by the 80188 only when the
80188 enters a "Hold Acknowledge" state.
2 INTA occurs one clock later in RMX-mode.
3 Status inactive just prior to T4

3-150

210706-004

inter

iAPX 188

WAVEFORMS (Continued)

CLKOUT

-

TCLAV

-

LOCi(

CLKOUT

TINVCL-

~

INTO-3,
TlMERIN,'-_ _ _ _ _ _---'

CLKOUT

V

J
TCHQSV

\/
QSO, QS1

--------------~/\~------3-151

210706-004

intJ

IAPl( :188

WAVEFORMS (Continued)
HOLD-HLDA TIMING

CLKOUT

ARDY

'~ r~~'

TARYLCL_

ARDY _ _ _ _ __ _

CLKOUT

SRDY

T,

CLKOUT~'HVCL
HOLD

""-t--+--

HLDA

---

---.

AD150ADO - - - 80188

__ J

DEN----

TCHCV

A19/S6-A16/S3, - - - RD, WR,
80188

)---

H,----

---..
__ J

r-

,TCLAV

80188

80188

DT/A,

i2-SiI

3-152

210706-004

IAPX 188

WAVEFORMS (Continued)
TIMER ON 80188

ClKIN

TCKHl

TCH1CH2

'!<+---TCLCH·-:"'·--!-'",,"---TCHCl--_1...

dLKOUT

~-------TCLCl-------~

TINVCH

TIMERIN

'WW~
TIMEROUT _ _

~:~~~~~~~~~~~~~~~~~~~~~~~_2-_6_C_LOC_K_S_"-----------r--~~

80188 INSTRUCTION TIMINGS

• All' word-data is located on even-address
boundaries.

The following instruction timings represent the minimum execution time in clock cycles for each instruction. The timings given are based on the following
assumptions:

All jumps and calls include the time required to fetch
the opcod~ of the next instruction at the destination
address.

• The opcode, along with any data or displacement
required for execution of a particular instruction,
has been prefetched and resides In the queue at
the time it is needed.
• N'o wait states or bus HOLDS occur.

All instructions which involve memory reference can
require one (and in some cases, two) additional
clocks above the minimum timings showl1. This is
due to the asynchronous nature of the handshak~
between the BIU and the Execution unit.

3-153

210706-004

inter

IAPX 188

INSTRUCTION SET SUMMARY
Clock
Cycles

FUNCTION

FORMAT

DATA TRANSFER
MOY: Move:
Reglsterto Reglster'Memory

11 0,00100wl

mod reg

r:rn

Register/memory to register

11 000101wl

mod reg

r'm

Immediate to register memory

11 10001 1 w

modOOO

rim

Immediate to register

11 01 1 w

Memory to accumulator

reg

I
I

0100001'1

I

11 010001wl

Register/memory to segment register

11 00 0 1 1 1 0

mod 0 reg

rim

Segment register to register/memory

11

mod 0 reg

rim

' addr·low

I
00 0 1 1 0 0 I

11 1 1 1 1 1 1 1

RegISter

10 1 0.1 0

Segment register

10 0 0 reg 1 1 0

I
I

dat.,f w-l

addr·hlgh

addr·low

Accumulator to memory

PUSH: Push'
Memory

data
datalfw-l

data

2/12'
2/9'
12-13"
3-4
g"
S"
2/13
2115

mod 11 0 r'm

addr·hlgh

I

I
I
1-

I

POP: Pop
Memory

11 00 0 1 1 1 11

RegISter

10 lOt 1

Segment register

10 00 reg

:.:'

:r·,:~::'·~4,~·,

modOOO rim

I
11 1I

24
14
12

reg

(reg/Ol)

'r_:;".~'i1:i\l,!'f1:~~;:t:;>~'.~:iG~it; 1t":a,ll"~1 Ji;~,

'"

:.• '~,f'.',,:

:"~', ',: '

" "

83,

XCHG : Exchange'
Register/memory with register

11 000011wl

Register with accumulator

11 00 1 0

IN: Input from:
FI""d port

11 1 1 0 \} lOw

va"able port

It

OUT: Output to'
FIXed port

11 1 1 001 1 w

variable port

11 1101 11 w

7"

XLAT c Translate byte to AL

11 1 0 1 0 1 1 1

LEA ~ Load EA to rpglSter

11 00 0 1 1 0 1

mod reg

LOS c Load pOinter to OS

11 1 0 0 0 1 0 1

mod reg

rim

(mod .. 11)

LES ~ Load pOinter to ES

11 1000100

mod reg

rim

(mod" 11)

LAHF - Load AH with flags

11 00 1 1 1 1 1

SAHF - Store AH Into flags

11 001 1 1 1 0

15
6
26
26
2
3
13
12

reg

1 1 0 1 1 '0"",

PUSHF =Push flags

11 00 1 1 1 0 0

POPF - Pop Jlags

11 00 1 1 1 0 1

mod reg

rim

I
I
I

S/16-bit
S/16-bit

20
14
13

reg

I\ij~~~~$) ~;!MI,,~,::i)ii:W-;~~I;,';i):-< .... 0 VOl UNlESS OTHERWISE

Sl'EClfl~D

: ;g~ll~~:;~:TEEA~vr;L~ ~~~~~ET~:t;;V~~I~E~~A::::~Tl~:~~EU~~~~~SL~~~~~~; ~~~~~~fgEcmfs TO ~u,. ANOT"~~ aus
CVCLE Hili LOC"'l'USI$ FlOATED 8V THE ~WHEN Tke ~ ENTEASA AeOUEST BUS ACKNOI'jLEOGE STATE
'SIGIOAL$ATUUOA82MAAESHOI'jNFOAAeFEAE"CEONlV
______ _

5

!~~,~~~::;HG~ G1:NE 82\111 GOMfIIAIOO AND C()NTROt. SIGNALS IMFIOC MI'jTC AMI'jC [OAC 10l'jC A,OWC '''ITA A"O DEN, LAGS THE

6 iIot.L TlMII

30
29

ROtGT1

- iiQmo
' He
_J He

52

'"

§3'"

BUSY
RESET

Figure 2. 8087 Pin Configuration

Figure 1. 8087 Block Diagram

Intel Corporation Assumes No Reaponslbilly for the Use of Any Circuitry other Than CirCUitry Embodied

©INTEL CORPORATION, 1984

3-175

In

an Intel Product No Other CirCUit Patent Licenses 8'f'e Implied

ORDER

NUMBE~~~5~5~~

8087/8087-2/8087-1

Table 1. 8087 Pin Description
Symbol

Type

Name and Function

AD15-ADO

1/0

Address Data; These lines constitute the time ~ultlplexed memory address (T 1) and data (T2. T 3. T w. T 4) bus.
AO is analogous to BHEforthe lower byte of the data bus. pins 07-00. It is lOW during T1 when a byte is
to be transferred on the lower portion of the bus in memory operations. Eight-bit oriented devices tied
to the lower half of the bus would normally use AO to condition chip select functions. These lines are
active HIGH. They are input/output lines for 8087-driven bus cycles and are inputs wtiich the 8087
monitors when the CPU is in control olthe bus. A 15-A8 do not requirean address latch in an iAPX 88/20
or iAPX 188/20. The 8087 will supply an address for the TrT4 penod.

A19/S6.
A18/S5.
A17/S4.
A16/83

1/0

Address Memory: During T1 these are the four most sigmficant address lines./or memory operations.
During memory operations. status information is available on these lines during T 2. T 3• T w. and T 4' For
8087-controlled bus cycles. S6. S4. and S3 are reserved and currently one (HIGH). while S5 is always
lOW.These lines are inputs which the 8087 monitors when the CPU is in control of the bus.

BHE/S7

1/0

Bus High Enable: During T1 the bus high enable signal (BHE) should be used to enable data onto the most
significant half of the data bus. pins D15-D8. Eight-bit-oriented devices tied to the upper half of the bus
would normally use BHE to condition chip select functions. BHE is lOW during T1 for read and write cycles
when a byte is to be transferred on the high portion of the bus. The 87 status information is available during
T2. T3. Tw. and T4' The signal is active LOW. 87 is an input which the 8087 monitors during the CPU-controlled
bus cycles.

82.81.80

1/0

Status: For 8087 -driven bus cycles. these status lines are encoded as follows:

S2

51

1 (HIGH)
1
1
1

X
0
0
1
1

o(lOW)

SO
X
0
1
0
1

Unused
Unused
Read Memory
Write Memory
Passive

Status is driven active during T4. remains valid during T1 and T2 • and is returned to,lhe passive state
(1.1.1) during T3 or during Tw when READY is HIGH. This status is used by the 8288 Bus Controller
(or the 82188 Integrated Bus Controller with an 80186/80188 CPU) to generate all memory access
control signals. Anychange in S2. S1. or SOduring T4 is used to indicate the beginning of a bus cycle.
and the return to the passive state in T3 orTw is used to indicate the end of a bus cycle. These signals
are monitored by the 8087 when the CPU is in control of the bus.

RQ/GTO

1/0

Request/Grant: This request!grant pin is used by the 8087 to gain control of the local bus from the CPU for
operand transfers or on behalf of another bus master. It must be connected to one of the two processor request!
grant pins. The request grant sequence on this pin is as follows:
1. A pulse one clock wide is passed to the CPU to indicate a local bus request by either the 8087 or the master
connected to the 8087 RQ/GT1 pin.
2. The 8087 waits for the grant pulse and when it is received will either initiate bus transfer activity in the clock
cycle following the grant or pass the grant out on the RQ/GT1 pin in this clock if the initial request was for
another bus master.
3: The 8087 will generate a release pulse to the CPU one clock cycle after the completion olthe last 8087 bus cycle
or on receipt of the release pulse from the bus master on RQ/GT1.

--

For iAPX 186/188 systems. the same sequence applies except- RQ/GT signals are converted to
appropriate HOLD. HlDA signals by the 82188 Integrated Bus Controller. ThiS is to conform with iAPX
186/188's HOLD. HlDA bus exchange protpcol. Refer to the 82188 data sheet for further information.

3-176

205835-003

inter

8087/8087-2/8087-1

Table 1. 8087 Pin Description (Continued)
Symbol
RQ/GTI

Type

Name a"d Function

I/O

Requesl/Grant: This request/grant pin is used by another local bus master to force the 8087 to request
the local bus. If the 8087 is not in control of the bus when the request is made the request/grant sequence
is passed through the 8087 on the RQ/GTO pin one cycle later. Subsequent grant and release pulses are
also passed through the 8087 with a two and one clock delay, respectively, for resynchronization. RQ/GTt
has an internal pullup resistor, "nd so may be left unconnected. If the 8087 has control of the bus the request/
grant sequence is as follows:
1. A pulse 1 ClK wide from another local bus master indicates a local bus request to the 8087 (pulse 1).
2 During the 8087's next T4 or T, a pulse 1 ClK wide from the 8087 to the requesting master (pulse 2)
indicates that the 8087 has allowed the local bus to float and that it will enter the "RQ/GT acknowledge"
state at the next ClK. The 8087's control unit is disconnected logically from the local bus during "RQ/GT
acknowledge."
3. A pulse 1 ClK wide from the requesting master indicates to the 8087 (pulse 3) that the "RQ/GT" request
is about to end and that the 8087 can reclaim the local bus at the next ClK.
Each master-master exchange of the local bus is a sequence of 3 pulses. There must be one dead ClK
cycle after each bus exchange. Pulses are active lOW.
For iAPX 186/186 systems, the RQ/GTI line may be connected to the 82188 Integrated Bus Controller In this case, a
third processor with a HOLD, HlDA bus exchange system may acquire the bus from the 8087. Forthis configuration,
RQ/GTI will only be used If the 8087 is the bus master Refer to 82188 data sheet for further information.

QS1,QSO

I

QS1, OSO: QSl and QSO provide the 8087 with status to allow tracking of the CPU instruction queue.
0$1

o (lOW)
0
1 (HIGH)
1

QSO
0
1
0
1

No Operation
First Byte of Op Code from Queue
Empty the Queue
Subsequent Byte from Queue

-

INT

0

Interrupt This line IS used to Indicate that an unmasked exception has occurred during numeric instruction
execution when 8087 interrupts are p-nabled Thissignal is typically routed to an 8259A for 8086 systems and to INTO
for iAPX 186/186 systems INT is active HIGH

BUSY

0

Busy: This signal indicates that the 8087 NEU is executing a numeric instruction. It is connected to the CPU's
TEST pin to provide synchronization. In the case of an unmasked exception BUSY remains active until the
exception is cleared. BUSY is active HIGH.

READY

I

Ready: READY is the acknowledgement from the addressed memory deVice that It will complete the data transfer.
The RDY signal from memory is synchronIZed by the 8284A Clock Generator to form READY for 8086 systems. For
iAPX 186/188 systems, ROY is synchronized by the 82188 Integrated Bus Controller to form READY This Signal IS
active HIGH.

RESET

I

Reset: RESET causes the processor to immediately terminate its present activity. The signal must be active
HIGH for at least four clock cycles. RESET is internally synchronized.

ClK

I

Clock: The clock provides the basic timing for the processor and bus controller. It is asymmetric with a
33% duty cycle to provide optimized internal timing.

Vcc

Power: Vcc is the +5V power supply pin.

GND

Ground: GND are the ground pins.

NOTE:
For the pin descriptions of the 8086, 8088, 80186 and 80188 CPU's, reference the respective data sheets (iAPX 86/10, iAPX 88/10,
iAPX 186, iAPX 188).

3-177

205835-003

8087/8087-218087-1

APPUCATION AREAS

The 8087 is a numeric processor extension that provides
arithmetic and logical instruction support for a variety of
numeric data types. It also executes numerous built-in
transcendental functions (e.g., tangent and log functions). The 8087 executes instructions as a coprocessor'
to a maximum mode CPU. It effectively extends the
register and instruction set of the system and adds
several new data types as we". Figure 3 presents the
registers of the CPU+8087. Table 2 shows the range of
data types supported by the 8087. The 8087 is treated as
an extension to the CPl,), providing register, data types,
control, and instruction capabilities at the hardware
level. At the programmers level the CPU and the 8087,
are viewed as a single unified processor.

The 8087 provides functions meant specifically for high
performance,numeric processing requirements. Trigonometric, logarithmic, and exponential functions are
built into the coprocessor hardware. These functions
are essential in scientific, engineering, navigational,
or military applications.
The 8087 also has capabilities meant for business or
commercial computing. An 8087 can process Binary
Coded Decimal (BCD) numbers up to 18 digits without
roundoff errors. It can also perform arithmetic on integers as large as 64 bits ± 1018).

PROGRAMMING LANGUAGE SUPPORT
System Configuration

Programs for the 8087 can be written in Intel's high-level
languages for iAPX 86/88 and iAPX 186/188 Systems;
A5M-86 (the iAPX 86,88 assembly language), PUM-86,
FORTRAN-86, and PA5CAL-86.

As a coprocessor to an 8086 or 8088, the 8087 is wired in
para"el with the CPU as shown in Figure 4. Figure 5
shows the iAPX 186/188 system configuration. The
CPU's status (50-52) and queue status lilies (OSo-OSl)
enable the 8087 to monitor and decode instructions in
synchronization with the CPU and without any CPU
overhead. For iAPX 1861188 systems, the queue status
signals of the iAPX 1861188 are synchronized to 8087
requirements by the 82188 Integrated Bus Controller.
Once started, the 8087 can process in para"el with, and
independent of, the host Cpu. For resynchronization,
the 8087's BUSY signal informs the CPU that the 8087 is
executing an instruction and the CPlJ WAIT instruction
tests this signal to insure that the 8087 is ready to
execute subsequent instructions. The 8087 can interrupt
the CPU when it detects an error or exception. The

RELATED INFORMATION
For iAPX 86/10, iAPX 88110, iAPX 186 or iAPX 188
details, refer to the respective data sheets. For iAPX 186
or iAPX 188 systems, also refer to the 82188 Integrated
Bus Controller data sheet.

FUNCTIONAL DESCRIPTION
The 8087 Numeric Data Processor's arcHitecture is
designed for high performance numeric computing in
conjunction with general purpose processing.

8087
DATA FIELD

CPU

AX ' i !
FILE 5
0

ax

-a
DX
SI
DI

BP

SP

II "l-gs:f:N~;7~8E~X~PO;N~EN~T~8';83~===:::;S;IG;N~IFI~CAN:;:~D====~O
RI

R2

I
:

III

R3r---r-------+----------------;
R.I--__~------+_---------------;

'i

TAG FIELD
O

RS r---r--,-----+--,--------------;
R8
R71----~------+----------------;
R8 L-_.L..-_ _ _..L....._ _ _ _ _ _ _....J

L __ ,

I----:::-"""P
:::-__
FLAGS

I

-'1'

•

15

CONTROL REGISTER
STATUS REGISTER
T"GWORD

:1

L.. _ _ _ _ --,

I- INSTRUCTION POINTER_

§' i------------fl
..
i

I-

DATA POINTER

-

Figure 3. CPU+8087 Architecture
3-178

205835-003 '

8087/8087-2/8087-1

Integrated Bus Controller. Because the iAPX 186/188
has a HOLD, HLDA bus exchange protocol, an interface
is needed which will translate RQ/GT signals to corresponding HOLD, HDLA signals and visa versa. One of
the functions of the 82188 IBC is to provide this
translation. RQ/GTO is translated to HOLD, HLDA
signals which are then directly connected to the iAPX
186/188. The RQ/GT1 line is also translated into HOLD,
HLDA signals (referred to as SYSHOLD, SYSHLDA
Signals) by the 821881BC. This allows a third processor
(using a HOLD, HLDA bus exchange protocol) to gain
control of the bus.

8087's interrupt request line is typically routed to the
CPU through an 8259A Programmable Interrupt Controller for 8086, 8088 systems and INTO for iAPX
186/188.

The 8087 uses one ofthe request!grant lines of the iAPX
86/88 architecture (typically RQ/GTO)to obtain control
of the local bus for data transfers. The other request!
grant line is available for general system use (for
instance by an I/O processor in LOCAL mode). A bus
master can also be connected to the 8087's RQ/GT1
line. In this configuration the 8087 will pass the request!
grant handshake signals between the CPU and the
attached master when the 8087 is not in control of the
bus and will relinquish the bus to the master directly
when the 8087 is in control. In this way two additional
masters can be configured in an iAPX 86/88 system; one
will share the 8086 bus with the 8087 on a first come first
served basis, and the second will be guaranteed to be
higher in priority than the 8087.

Unlike an iAPX 86/20 system, RQ/GT1 is only used
when the 8087 has bus control. If the third processor
requests the bus when the current bus master is the
iAPX 186/188, the 82188 IBC will directly pass the
request onto the iAPX 186/188 without going through
the 8087. The third processor has the highest bus
priority in the system. If the 8087 requests the bus while
the third processor has bus control, the grant pulse will
not be issued until the third processor releases the bus
(using SYSHOLD). In this configuration, the third processor has the highest priority, the 8087 has the next
highest, and the iAPX 186/188 has the lowest bus
priority.

For iAPX 186/188 systems, RQ/GTO and RQ/GT1 are
connected to the corresponding inputs of the 82188

Table 2. 8087 Data Types
Data
Formats

Range

Most Significant Byte

Precision

7

104

16 Bits

--

i----

109

Short Integer

017

017

017

017

017

32 Bits

017

017

01

115

~ Two's Complement

131

--~

Two's Complement

~-

r-.-10 18

Long Integer

64 Bits

163

---=--=------------------~-

Packed BCD

1018

Short Real

10±38
--

------~-

Long Real
f---

017

--~

-

Word Integer

017

_~_D17D1L

18 Digits
24 Bits

SI E7

I
Two's
10 Complement
101 Dol

~ Fo Implicit

EoIF1

----~

10±308

53 Bits

S IE10

10±4932

64 Bits

~-

-EoIF1

F521 Fo Implicit

---

Temporary Real

EJo

F63[

--~-

j---------~---

Real. (_1)S(2E-BIAS)(Fo;F1' .)

Integer: I
Packed BCD' (-1)S(D17

Sias=127 for Short Real
1023 for Long Real
16383 for Temp Real

Dol

--------

3-179

205835-003

intJ

8087/8087-218087-1

Bus Operation
The 8087 bus structure, operation and timing are
identical to all other processors in the iAPX 86/88 series
(maximum mode configuration). The address is time
multiplexed with, ,the data on the first 16/8 lines of the
address/data bus. A 16 through A 19 are time multiplexed
with four status lines 83-86. 83, 84 and 86 are always
one (HIGH) for 8087-driven bus cycles while S5 is
always zero (LOW). When the 8087 is monitoring CPU
bus cycles (passive mode) 86 is also monitored by the
8087 to differentiate 8086/8088 activity from that of a
local I/O processor or any other local bus master. (The
8086/8088 must be the only processor on the local bus
to drive 86 LOW). 87 is multiplexed with and has the
same value as BHE for all 8087 bus cycles.
The first three Stl\tus lines, 80-82, are used with an 8288
bus controller or 82188 Integrated Bus Controller to
determine the type of bus cycle being run:

S2

Sf

SO

0

X
0
0
1
1

X
0
1
0
1

1
1
1
1

Unused
Unused
Memory Data Read
Memory Data Write
Passive (no bus
cycle)

Table 2 lists the eight data types the 8087 supports
and presents the format for each type. Internally, the
8087 holds all numbers in the temporary real format.
Load and store instructions automatically convert
operands represented in l1Jemory as 16-, 32-, or 64-bit
integers, 32- or 64-bit floating point numbers or 18digit packed BCD numbers into temporary real format
and vice versa. The 8087 also provides the capability
to control round off, underflow, and overflow errors
in each calculation.
Computations in the 8087 use th!l processor's register
stack. These eight 80-bit registers provide the equivalent
capacity of 20 32-bit registers. The 8087 register set
can be accessed as a stack, with instructions operating
on the top one or two stack elements, or as a fixed
register set, with instructions operating on explicitly
designat~d registers.
Table 5 lists the 8087's instructions by class. All appear
as ESCAPE instructions to the host. Assembly language
programs are written in ASM-86, the iAPX 86, 88 assembly language.

Table 3. Execution Times for Selected iAPX 86/20
Numeric Instructions and Corresponding
IAPX 86/10 Emulation
Approximate Execution
Time Vts)

Programming Interface

Floating Point
Instruction

The 8087 includes the' standard iAPX 86/10, 88/10
instruction set for general data manipulation and program control. It also includes 68 numeric instructions
for extended precision integer, floating pOint, trigonometric, logarithmic, and exponential functions. 8ample
execution times for several 8087 functions are shown in
Table 3. Overall performance is up to 100 times that of an
iAPX 86/10 processor for numeric instructions.

IAPX 86/20 iAPX 8611 0
(5 MHz
Clock)
Emulation

Add/Su btract
Multiply (single
precision)
Multiply (extended
precision)
Divide
Compare
Load (double precision)
Store (double precision)
Square Root
Tangent
Exponentiation

Any instruction executed by the 8087 is the combined
result of the, CPU and 8087 activity. The CPU and the
8087 have specialized functions and registers providing
fast concurrent operation. The CPU controls overall
program execution while the 8087 uses the coprocessor
interface to recognize and perform numeric operations.

,

I

3-180

17

1,600

19

1,600

27
39
9
10
21
36
90
100

2,100
3,200
1,300
1,700
1,200
19,600
13,000
17,100

,
205835-003

intJ

8087/8087-2/8087-1

NUMERIC PROCESSOR
EXTENSION ARCHITECTURE

with the CPU while the NEU is busy processing a
numeric instruction.

As Shown in Figure 1, the 8087 is internally divided
into two processing elements, the control unit (CU)
and the numeric execution unit (NEU). The NEU executes all numeric instructions, while the CU receives
and decodes instructions, reads and writes memory
operands and executes 8087 control instructions. The
two elements are able to operate independently of one
another, allowing the CU to maintain synchronization

Control Unit
The CU keeps the 8087 operating in synchronization
with its host CPU. 8087 instructions are intermixed with
CPU instructions in a single instruction stream. The CPU
fetches all instructions from memory; by monitoring the
status (SO-S2, S6) emitted by the CPU, the control unit
determines when an instruction is being fetched. The

Figure 4. iAPX 86/20, 88/20 ~ystem Configuration
r

-..,
INT

t-I-~-~IINTR

8259A

PIC

IAPX86

MULTIMASTER
SYSTEM
BUS

BUS

INTERFACE
COMPONENTS
B284A

CLOCK
GENERATOR

~~:

eLK H---.,.-<>----iCLK

....

_ _ ....J

Figure 5. IAPX 186/20, 188120 System Configuration

......

,

I
.,,,,r. """"
."

W

.....
QlI

-

""

QS011-.:--

oso

IIUSV

1

06111_091

"'w

~"

IItT

II

""

.~

OSD

1AI'II;,88I,18

'~r---

,~

".. I----- ""'

/'-----'\
'v-I

3-181

W

....,.
'"'

.~""

""~-

(::j !I;

205835-003

8087/8087-218087-1

CU monitors the data bus in parallel with the CPU to
obtain instructions that pertain to the 8087.
The CU'maintains an instruction queue that is identical
to the queue in the host CPU. The CU automatically
determines if the CPU is an 8086/186 or an 8088/188
immediately after reset (by monitoring the BRE/S7 line)
and matches its queue length accordingly. By monitoring the CPU's queue status lines (OSO, OS1), the CU
obtains and decodes instructions from the queue in
synchronization with the CPU.
A numeric instruction appears as an ESCAPE instruction
to the CPU. Both the CPU and 8087 decode and execute
the ESCAPE instruction together. The 8087 only
recognizes the numeric instructions shown in Table 5.
The start of a numeric operation is acomplished when
the CPU executes the ESCAPE instruction. The instruction mayor may not identify a memory operand.
The CPU does, however, distinguish between ESC
instructions that reference memory and those that
do not. If the instruction refers to a memory operand,
the CPU ca.lculates the operand's address using any
one of its available addressing modes, and then performs a "dummy read" of the word at that location.
(Any location within the 1M byte address space is
allowed.) This is a normal read cycle except th'at the
CPU ignores the data it receives. If the ESC instruction does n<\lt contain a memory reference (e.g. an
8087 stack operation), the CPU simply proceeds to
the next instruction.
An 8087 instruction can have one of three memory
reference options; (1) not reference memory; (2)
load an operand word from memory into the 8087; or
(3) store an operand word from the 8087 into
memory. If no memory reference is required, the
8087 simply executes its instruction. If a memory
reference is required, the CU uses a "dummy read"
cycle initiated by the CPU to capture and save the
address that the CPU places on the bus. If the instruction is a load, the CU additionally captures the
data word when it becomes available on the local
data bus. If data required is longer than one word,
the CU immediately obtains the bus from the CPU
using the requesVgrant protocol and reads the rest
of the information in consecutive bus cycles. In a
store operation, the CU captures and saves the store
address as in a'ioad, and ignores the data word that
follows in the "dummy read" cycle. When the 8087 is
ready to perform the store, the CU obtains the bus
from the CPU and writes the operand starting 'at the
specified address.
'

Numeric Execution Unit
The NEU executes all\ instructions that involve the
register stack; these include arithmetic, logical,
transcendental, constant and data transfer instructions. The data path in the NEU is 84 bits wide (68
fraction bits, 15 exponent bits and a sign bit) which
allows internal operand transfers to be performed at
very high speeds.
When the NEU begins executing an instruction, it
activates the 8087 BUSY signal. This signal can be
used in conjunction with the CPU WAIT instruction
to resynchronize both processors when the NEU has
completed its current instruction.

Register Set
The CPU+8087 register set is shown in Figure 3. Each of
the eight data registers in the 8087's register stack is 80
bits and is dividecj into "fields" corresponding to the
8087's temporary real data type.
At a given point In time the TOP field in the control word
identifies the c(Jrrent top-of-stack register. A "push"
operation decrements TOP by 1 and loads a value into
the new top 'register. A "pop" operation stores the value
from the current top register and then increments TOP
by 1. Like CPU stacks in memory, the 8087 register
stack grows "down" toward lower-addressed registers.
Instructions may address the data registers either
implicitly or explicitly. Many instructions operate on
the register at the top of the stack. These instruc-,
tions implicitly address the register pointed to by the'
TOP. Other instructions allow the programmer to
explicitly specify the register which is to be used.
Explicit register addressing is "top-relative."

Status Word
The status word shown in Figure 6 reflects the overall state of the 8087; it may be stored in memory and
then inspected by CPU code. The status word is a
16-bit register divided into fields as shown in Figure
6. The busy bit (bit 15) indicates whether the NEU is
either executing an instruction or has an interrupt
request pending (B 1), or is idle (B 0). Several
instructions which store and manipulate the status
word are executed exclusively by the CU, and these
do not set the busy bit themselves.

=

3-182

=

205835-003

8087/8087-2/8087-1

I

B

1 c, .1

I

TOP

C,

1 c, 1 C·I'R 1

X

1

PE

I UE

1 11
OE

ZE

DEl'E

J

l

EXCEPTION FLAGS (1 = EXCEPTION HAS OCCURRED)
INVALID OPERATION
DENORMALIZED OPERAND

ZERO DIVIDE
OVERFLOW
UNDERFLOW

PRECISION
(RESERVED)
INTERRUPT REQUEST(l)
CONDITION CODE(2)
TOP OF STACK POINTER(3)

NEU BUSY
111IR

IS

set

If

any unmasked exception bit

IS

set, cleared otherwise

(2)8ee Table 3 tor condition code Int,erpretatlOn
(3)Top Values
000" Register 0 IS Top of Stack
001 " Register ~ IS Top of Stack

111 = Register 7 IS Top of Slack

Figure 6. 8087 Status Word
The four numeric condition code bits (CO-C3) are similar
to flags in a CPU: various instructions update these bits
to reflect the outcome of 8087 operations. The effect of
these instructions on the condition code bits. is summarized in Table 4.
Bits 14-12 of the status word point to the 8087 register that is the cu~rent top-of-stack (TOP) as
described above.
Bit 7 is the interrupt request bit. This bit is set if any
unmasked exception bit is set and cleared otherwise.

word can be used, however, to interpret the contents
of 8087 registers.

Instruction and Data Pointers
The instruction and data pointers (see Figure 8) are
provided for user-written error handlers. Whenever
the 8087 executes an NEU instruction, the CU saves
the instruction address, the operand address (if
present) and the instruction opcode. 8087 instructions can store this data into memory.

Bits 5-0 are set to indicate that the NEU has
detected an exception while executing an instruction.
TAG VALUES
00 = VAllO
01 = ZERO

Tag Word

10 " SPECIAL
11 = EMPTY

The tag word marks the content of each register as
shown in Figure 7. The principal function of the tag
word is to optimize the 8087's performance. The tag

Figure 7. 8087 Tag Word

3-183

205835-003

8087/8087-2/8087-1

Table 4a. '-Condition Code Interpretation
Instruction
Type
Compare, Test

C:3

C:!

Cl

Co

0
0

0
0
0

0

1

X
X
X
X

01

0

00

02

U

1

U

U

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

1
1
Remainder

Examine

0
0
0
0
0
0
0
0

i

1
'1
1
1
1
1
1
1

1
0

1

1
1
1
1
1
1
1
1

Interpretation
ST
ST
ST
ST

> Source or 0 (FTST)
< Source or 0 (FTST)
\

= Source or 0 (FTST)
is not comparable

Complete reduction with
three low bits of quotient
(See Table 4b)
Incomplete Reduction
Valid, positive unnormalized
Invalid, positive, exponent =0
Valid, negative, un normalized
Invalid, negative, exponent =0
Valid, positive, normalized
Infinity, positive
Valid, negative, normalized
Infinity, negative
Zero, positive
Empty
Zero, negative
Empty
Invalid, positive, exponent = 0
Empty
Invalid, negative, exponent = 0
Empty

NOTES:
1. ST = Top of stack
2. X = value IS not affected by Instruction
3. U = value is undefined following instruction
4. Qn = Quotient bit n

MEMORY
OFFSET
15

Table 4b.

CONTROL WORD

+0

STATUS WORD

+2

Condition Code bterpretation after

As

a Function of
FPREM Instruction
Dividend Value
Dividend Range
Dividend < 2 • Modulus
Dividend < 4 • Modulus
Dividend;;. 4 • Modulus

Q2
C3'
C3'

O2

Ql

,Qa

C1'

00
00
00

0,
0,

TAG WORD

+4

INSTRUCTION POINTER (15-0)

+6

i)1 I

INSTRUCTION
POINTER (19-16) 0

INSTRUCTION
OPCODE (10-0)

DATA POINTER (15-0)
DATA POINTER'I
(19-16)

15

NOTE:
1. Previous value of indicated bit, not affected by FPREM
instruction execution.
'

3-184

0

+8

+10
+12

1211

Flgure8. 8087 Instruction and Data Pointer
Image in Memory

205835-003

inter

8087/8087-2/8087-1

Control Word

Exception Handling

The 8087 provides several processing options which
are selected by loading a word from memory into the
control word. Figure 9 shows the format and encoding of the fields in the control word.

The 8087 detects six different exception conditions
that can occur during instruction execution. Any or
all exceptions will cause an interrupt if unmasked
and interrupts are enabled.

The low order byte of this control word configures
8087 interrupts and e?I~P=, =:

53-65 + EA

~ ~ ~I~P ~

290-310 +EA

J

17-22

STORE

-

1 MOD

0 ,1

I~ ~ ~ ~I~P ~

=

Exchange ST(,) and

ST(O)

ESCAPE

ESCAPE

1

I

MOD

1 1 RIM [

1 1 1 RIM

1-

l' I MOD 1 1 1 RIM [

1

1 1 0 RIM

84-90
+EA

82-92
+EA

15-22

0 ST(,) 1

STORE AND POP

=

-:

1-

~ ~ ~I~P ~

J

~ ~ ~I~P ~

:

94-105 +EA

~ ~ ~I~P ~ ~

52-58 +EA

~ ~ '~I~ ~ T

520-540 +EA

86-92
+EA

84-94
+EA

1 1 ST(,)

1

17-24

0 0 1 ST(,)

I

10-15

l' 0

Comparison
FCOM

= Compare

FCOMP

ESCAPE

ESCAPE

0 0 0 I 1 1

FCOMPP = Compare ST(I) to
ST(O) and Pop Tw,ce

ESCAPE

1 1 0

= Test ST(O)
=

J

60-70
+EA

78-91
+EA

40-50

1

Fk~s;;C,;,:A,;,:PE~M~F~0~1=M~O~D~O~I~I==R~/M====jI_ ~I~P==:

ST(,) to ST(O)

FXAM

1_ ~ ~ ~I~ ~

= Compare and Pop

IntegerlReal Memory to ST(O)

FTST

0

RIM

Exam,ne ST(O)

ES;CAPE }O 0
ESCAPE

1

0 0 1

I

1 1

I1

I

1

1 1

0 1 1 ST(,)

63-73
80-93
+EA
+EA
45-52

1

45-55

1,0 {) 1 0 0

38-48

1 0 0 1 0

12-23

0

1 1 0 0

1

MnemoniCS © Intel 1982

3-194

205835-003

"

inter

8087/8087·2/8087·1

Table 5. 8087 Extensions to the 86/186 Instruction Sets (cant.)

I
Constants

[

MF

~

LOAD + 00 Into ST(O)

IESCAPE

0

oYJ,

FLOl

~

LOAD + 1 0 Into ST(O)

I ESCAPE
I ESCAPE
I ESCAPE
I ESCAPE

0

0

0

0

0

0

~

LOAD

1f

mto ST(O)

FLOL2T
ST(O)

~

LOAD IOg2 10 mto

FLOL2E
ST(O)

~

LOAD log2 e mto

FLOLG2
ST(O)

~

LOAD 1091O 2 Into

FLOLN2
ST(O)

~

1

I' ,

0

1

-'-0--'-0001

15-21

12

1 0

0

0

0

0

0

0

1

IntegeriReal Memory With ST(O)

I ESCAPE

MF

ST(I) and ST(O)

I ESCAPE

d

I ESCAPE
I ESCAPE

MF

I1
I1

1

1 0

1

1 0

1

1 0

,

1

I MOD

0

0

0

RiM

I1

0

0

0

ST(I)

0

11

16-22

~---~Ol

1

10

16 Bit
Integer

'6-22

0~11'0101!l

0

01
11-17

1

0

Clock Count Range
32 Bit
64 Bit
Integer
Real

0:]

1

, I, ,
, ,, I
,I , , , , I

I ESCAPE
I ESCAPE

LOAD log.2 Into

1

32 Bit
Real
00

~

FLOZ

FLOPI

Optional
8,16 Bit
Displacement

15-21

I

18-24

~

17-23

Arithmetic
FAOO

FSUB

~

~

Addition

ST(I) and ST(O)

~

P 0

1

d

0
P 0

I ESCAPE

d

I ESCAPE

MF

I ESCAPE

d

P 0

I

ESCAPE

0

0

1

I

1

1

Scale ST(O) by ST(l)

I ESCAPE

0

0

1

I1

FPREM ~ Partial Remainder of
ST(O) -ST(l)

I ESCAPE

0

0

1

I ESCAPE

0

0

1

FDIV = DIVISion
IntegerlReal Memory With ST(O)
ST(I) and ST(O)

~

FSCALE

Square Root of ST(O)

~

FRNOINT
Integer

~

Round ST(O) to

0
P 0

0

- - -

-,

- _.

.J

I
I

ST(I) and ST(O)

MF

MOD

0

0

1

RIM

1

0

0

1

RIM

I MOD
I1 1

1

1

R

RiM

I1

1

-I
-'

DISi'

I
- - - - -I
DISP
- - - -'

- - - - -I
DISP
- - - -'

I-

90-120
+EA

108-143 95-125
+EA
+EA

90-120 108-143 95-125
+EA
+ EA
+EA

110-125 130-144 112-168
+EA
+EA
+EA

215-225 230-243 220-230
+EA
+ EA
+EA

0

I

180-186

0

1

I

32-38

0

0

0

I

15-190

1

0

0

I

16-50

RIM

1

1

1

0

1

1

1

1

1

1

I1

1

1

1

1

I1

1

1

1

1

124-138
+EA

90-145 (Note 1)

193-203 (Note 1)

R

102-137
+EA

70-100 (Note 1)

I

1

102-137
+EA

70-100 (Note 1)

I

I

,-

DISP

- - -

L-

Multiplication
ESCAPE

- -

I MOD 1 0 R RIM
I 1 1 1 0 R RIM

IntegerlReal Memory With ST(O)

FSQRT

J~
]

Subtraction

IntegerlReal Memory With ST(O)

FMUL

0

224-238
+ EA

NOTE:
1. If P= 1 then add 5 clocks.

3-195

205835-003

8087/8087-2/8087-1

Thble 5. 8087 Extensions to the 86/186 Instructions Sets (cont.)
Optional
8.16 Bit
Displacement
FXTRACT ~ Extract
Components of St(O)

1

1

1

1 0

1 0

0

27-55

0 0 0

1

10-17

ESCAPE

0

0

0

0

o

o

000

FABS
ST(O)

~

Absolute Value of

ESCAPE

FCHS

~

Change Sign of ST(O)

ESCAPE

1

Clock Coun! Range

10-17

Transcendental
~

FPTAN
ST(O)

Partial Tangent of

FPATAN ~ Partial Arctangent
of ST(O) -ST(l)
F2XMl ~ 2 STlO )_1
~

FYL2X
ISl(O)1

Sl(l)· Log2

'FYL2XPl ~ Sl(l)· Log2
[ST(O) +lJ

ESCAPE

0 ____
0 1 L-______________
1 1 1 1 0 0 l' 0

ESCAPE

0

0

ESCAPE

0

0

ESCAPE

o

ESCAPE

o

,1

o

0

o

0

o
o

30-540

~

250-800

o

310-630

o

900-1100

0

700-1000

Processor Control
FINlT

FENI

FOISI

Initialized 8087

~'

= Enable

Interrupts

= Disable

Interrupts

FLDCW ~ Load Control Word

ESCAPE

o

0

o

ESCAPE
ESCAPE

o

0

0

2-8

0

2-8

000

o

ESCAPE

0

2-8

MOD

o

:

7-14 + EA

RI_M~ ~ ~ ~I~~ ~ ~:

12-18 + EA

~ ~ ~I~~ ~ ~

12-18 +EA

RIM

DISP

FSTCW

~

Store Control Word

'-E_S_C_A_P_E_O_O_ _'-M_O_D
_____

FSTSW

~

Store Status Word

'-E_SC_A_P_E_ _ _
O_-'-_M_O_D
_ _ _ _ _R_IM
_ _'--'I

FCLEX

~

Clear Exceptions

ESCAPE

0

1 1

FSTENV

~

Store Environment

ESCAPE

0

0

MOD

FLDENV

~

Load Environment

ESCAPE

0

0

MOD

FSAVE

~

FRSTOR

Save State

ESCAPE

o

MOD

~

ESCAPE

o

MOD

FINCSTP

Restore State

~

~

o

o

2-8

0 0

1 0

o

RIM

--T -DiS;; --:

40-50 + EA

0

RIM

?I~~ _ ~

35-45 +EA

o

RIM

0

RIM

, __

DISP

:

197-207+EA
197 -207 + EA

Increment Stack

POinter

FDECSTP

o

Decrement Stack

ESCAPE

0

o

ESCAPE

0

o

6-12

o

6-12

POinter

3-196

205835-003

8087/8087-2/8087-1

1iIbie 5. 8081 Extensions to the 861186 Instructions Sets (conl)
Clock Count Range
FFREE
FHOP

~

~

FWAIT

Free ST(I)

1 0

ESCAPE

No Operation

= CPU WaH for 8087

1

I1

1

ESCAPE0011 11

o

0

1

o

1

0 0 0 ST(I)

9-16

01000-y]

10-16

1

I

3+5n'

on = number of limes CPU examines TEST line before 8087 lowers BUSY

NOTES:
1. If mod=OO then
if mod=01 then
if mod=10 then
if mod = 11 then
2. if rim =000 then
if r/m=001 then
if r/m=010 then
If r/m=011 then
If r/m=100 then
if r/m=101 then
if r/m=110 then
if r/m=111 then

OISP=O', disp-Iow and disp-high are absent
OISP=disp-low sign-extended to 16-bits, disp-high is absent
OISP=disp-high; disp-Iow
rim is treated as an ST(i) field
EA=(BX) + (SI) +OISP
EA=(BX) + (01) +OISP
EA=(BP) + (SI) +OISP
EA=(BP) + (01) +OISP
EA=(SI) + OISP
EA=(OI) + OISP
EA=(BP) + OISP
EA=(BX) + OISP

"except if mod=OOO and r/m=110 then EA =disp-high; disp-Iow.
3. MF= Memory Format
00-32-bit Real
01-32-bit Integer
10-64-bit Real
11-16-bit Integer
4. ST(O)= Current stack top
ST(i)
ith register below stack top
5. d= Destination
O-Destination is ST(O)
1-Destination is ST(i)
6 P= Pop
O-No pop
1-PopST(O)
7. R= Reverse: When d=1 reverse the sense of R
O-Destination (op) Source
1-Source (op) Destination
8.
For FSQRT:
-0 "" ST(O) "" +:x:
For FSCALE:
_2'5 "" ST(1) < +2'5 and ST(1) integer
0 "" ST(O) "" 2- 1
For F2XM1:
For FYL2X:
0 < ST(O) <:x:
-oc < ST(1) < +:x:
For FYL2XP1:
0"" IST(O)I < (2 -V2)/2
-oc < ST(1) < oc
For FPTAN:
0"" ST(O) ""1T14
For FPATAN:
0"" ST(O) < ST(1) < +oc

3-197

205835-003

( 80130/80130-2
. iAPX 86/30, 88/30, 186/30, 188/30
iRMX 86 OPERATING SYSTEM PROCESSORS
• High-Performance 2-Chip Data
Processors Containing Operating
System Primitives.
• Standard iAPX 86/10, 8811 0 Instruction
Set Plus Task Management, Interrupt
Management, Message Passing,
Synchronization and Memory
Allocation Primitives
• Fully Extendable To and Compatible With
iRMX®86
• Supports Five Operating System Data

'lYpes: Jobs, Thsks, Segments,
Mailboxes, Regions
• 35 Operating System Primitives
• Built-In Operating System Timers and
Interrupt Control Logic Expandable
From 8 to 57 Interrupts

• 8086/80150/80150-218088/80186/80188
Compatible At Up To 8 MHz Without
Wait States
• MULTIBUS® System Compatible Interface

The Intel iAPX 86/30 and iAPX 88/30 are two-chip microprocessors offering gen~ral-purpose CPU (8086)
instructions combined with real-time operating system support. They provide a foundation for multiprogramming and multitasking applications. The iAPX 86/30 consists of an iAPX 86/10 (16-bit 8086 CPU)' and an
Operating System Firmware (OSF) component (80130).'The 88/30 consists of the OSF and an iAPX 88/10 (8-bit
8088 CPU). (80186 or 80188 CPUs may be used in place of the 8086 or 8088.)
Both components of the 86/30 and 88/30 are implemented in N-channel, depletion-load, silicon-gate techno 1. ogy (HMOS), and are housed in 40-pin packages. The 86/30 and 88/30 provide all the functions of the iAPX86/10,
88/10 processors plus 35 operating system primitives, hardware support for eight interrupts, a system timer, a
delay timer and a baud rate generator.

PROGRAM
MEMORY

8284A
CLOCK
DRIVER
RDY

DATA
MEMORY

BUS

INTERFACE

INTERRUPT

CS,LlR

1-'-------'

80130

INTERRUPT
REQUESTS

_J~
BAUD RATE

TIMER

DELAY
TIMER

SYSTEM

IAPX 9130, 88/30

TIMER

Figure 1. iAPX 86/30, 88/30 Block Diagram
Intel Corporabon Assumes No Re.ponslbllty for the Use of Any CirCUitry Other Than Circuitry Embodied In an Intel Product No Other CirCUit Patent Licenses aye Implied

©INTELCORPORATION,1981

.

3-198

OCTOBER 1981
210216-002

80130/80130·2

iAPX 86/30, 88/30, 186/30, 188/30

Vss

Vss

Vee

Vee

A014

A015

(A'4)

A014

AD'S

AD13

SHE

(A'3)

AD13

A16/S3

AD"

IR7

(A'2)

AD12

A17/S4

AD11

IR6

(A11)

AD11

A1B/S5

AD10

IRS

(A'O)

AD10

A19/S6

AD.

IR4

(A9)

AD.

SHEiS7 (HIGH)

AD.

IR3

(AB)

AD.

MN/Mx

Rii

(A'S)

AD7

IR.

AD7

AD6

IR'

ADS

RO/GTO

ADS

IRO

ADS

RO/GT1

AD4

INT

AD4

LOCK

AD3

S.

AD3

S2
51

AD.

51

AD.

AD'

SO

AD'

ADO

ACK

ADO

050

LlR

NMI

as,

INTR

TEST

MEMCS

IOCS

SVSTlCK

ClK

DELAY

ClK

READY

Vss

BAUD

Vss

RESET

Figure 2. iAPX 86/30, 88/30 Pin Configuration
Table 1. 80130 Pin Description
Symbol
AD1S- ADo

Type

Name and Function

I/O

Address Data: These pins constitute the time multiplexed memory address (Tl) and
data (T2' T3, TW, T4) bus. These lines are active HIGH. The address presented duringTl of
a bus cycle will be latched internally and interpreted as an 80130 internal address if
MEMCS or lacs is active for the invoked primitives. The 80130 pins float whenever it is
not chip selected, and drive these pins onlyduringT2-T4 of a read cycle andTl of an INTA
cycle.

Bus High Enable: The 80130 uses the BHE signal from the processor to determine
whether to respond with data on the upper or lower data pins, or both. The signal is active
Law. BHE is latched by the 80130 on the trailing edge of ALE. It controls the80130 output
data as shown.

BHE/S7

-BHE
0
0
1
1

(

S2,Sl' So

I

AO
0
1
0
1

Word on AD1S-ADo
Upper byte on AD 1S -ADa
Lower byte on AD7-ADO
Upper byte on AD7-ADO

Status: For the 80130, the status pins are used as inputs only. 80130 encoding follows:
S2

Sl

So

0
0
0
0
1
1
1

0
0
1
1
0
0
1

0
1
0
1
0
1

X

INTA
lORD
IOWR
Passive
Instruction fetch
MEMRD
Passive

3-199

210216-002

80130/80130·2
iAPX 86/30, 88/30, 186/30, 188/30

Table 1. 80130 Pin Description (Continued)
Type

Name and Function

ClK

I

Clock: The system clock provides the basic timing for the processor and bus controller.
It is asymmetric with a 33% duty cycle to provide optimized internal timing. The 80130
uses the system clock as an input to the SYSTICK and BAUD timers and to syncllronize
operation with the host CPU.

INT

0

Interrupt: INT IS HIGH whenever a valid interrupt request is asserted. It is normally used
to interrupt the CPU by connecting it to INTR.

IRrlRo

I

Interrupt Requests: An Interrupt request can be generated by raising an IR input (lOW
to HIGH) and holding it HIGH until it is acknowledged (Edge-Triggered Mode), or just by a
HIGH level on an IR input (level-Triggered Mode).

ACK

0

Acknowledge: This line is lOW whenever an 80130 resource is being accessed. It is also
lOW dUring the first INTA cycle and second INTA cycle if the 80130 is supplying the
interrupt vector infornlatlon ThiS signal can be used as a bus ready acknowledgement
and/or bus transceiver control.

MEMCS

I

Memory Chip Select: This input must be driven lOW when a kernel primitive is being
fetched by the CPU. AD13-ADo are used to select the instruction.

IOCS

I

Input/Output Chip Select: When this input is low, during an lORD or IOWR cycle, the
801S0's kernel primitives are accessing the appropriate peripheral function as specified
by the following table;

Symbol

LlR

0

BHE

A3

A2

A1

0
X
X
1
1
1
1
1

X
X
0
0
1

X
X

X
X
X
X

Ao
X
1
X
0

1
1
1

a

1
0
1

0
0
0

1
0
0

1
1

a

(

Passive
Passive
Passive
Interrupt Controller
Systlck Timer
Delay Counter
Baud Rate Timer
Timer Control

a

local Bus Interrupt Request: This signal is lOW when the interrupt request is for a
non-slave input or slave input programmed as being a local slave.

Vee

Power: Vee is the +5V supply pin.

Vss

Ground: Vss is the ground pin.

SYSTICK

0

System Clock Tick: Timer 0 Output. Operating System Clock Reference. SYSTICK is
normally wired to IR2 to implement operating system timing interrupt.

DELAY

0

DELAY Timer: Output of timer 1. Reserved by Intel Corporation for future use.

BAUD

0

Baud Rate Generator: 8254 Mode 3 compatible output. Output of 80130 Timer 2.

FUNCTIONAL DESCRIPTION

ment which constantly controls the telephone traffic
in a multiphone office, file servers/disk subsystems
controlling and coordinating multiple disks and multiple disk users, and transaction processing systems
such as electronics funds transfer.

The increased performance and memory space of
iAPX 86/10 and 88/10 microprocessors have proven
sufficient to handle most of today's Single-task or
single-device control applications with performance
to spare, and have led to the increased use of these
microprocessors to control multiple tasks or devices
in real-time. This trend has created a new challenge
to designers-development of real-time, multitasking application systems and software. Examples of
such systems include control systems that monitor
and react to external events in real-time, multifunction desktop and personal computers, PABX equip-

The iAPX 86/30, 88/30 Operating System
Processors
The Intel iAPX 86/30, 88/30 Operating System Processors (OSPs) were developed to help solve this

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r----------------------------------~

I

I

OPERATING SYSTEM UNIT

I
I
I

I
I

00-7

r

I

I

I
I
I
I

I

I

~
I

08-15

-

i

f---------------

I
I

------

SYSTEM
TIMER

~

LE
--

SYSTEM

DElAY

DelAY
TIMER

I

:
:
:I

I
BAUD qATE

GENERATOR

BAUD RATE

I

I
I

-------,-------1

I
I
--r--

k-

I

ADDRESS;
DATA BUS

INTERRUPT OUT

CONTROL
STORE

:

,.

INTERRUPT INP UTS

I
I

:
:

< Z.

I
I

I

:

8

I
PROGRAMMABLE
INTERRUPT
LOGIC

I

I

I

DATA

I

BUFFER

&

AND

I
I
I
I
I

ADDRESS
LATCH

CONTROL

1'-------

BUS
INTERFACE

I

3

I

4

~

STATUS

~BUSCON TROL
~

CONTROL UNIT
L __________________________________

CLOCK

LOCAL

I

INTERRU PT

I

(UFt)

~

Figure 3. OSF Internal Block Diagram

problem. Their goal IS to simplify the design of multitasking application systems by providing a welldefined, fully debugged set of operating system
primitives implemented directly in the hardware,
thereby removing the burden of designing multitasking operating system primitives from the application
programmer.
Both the 86/30 and the 88/30 OSPs are two-chip sets
consisting of a main processor, an 8086 or 8088 CPU,
and the Intel 80130, Operating System Firmware
component (OSF) (see Figure 1). The 80130 provides
a set of multitasking kernel primitives, kernel control
storage, and the additional support hardware, including system timers and interrupt control, required by these primitives. From the application
programmer's viewpoint, the OSF extends the base
iAPX 86, 88 architecture by providing 35 operating
system primitive instructions, and supporting five
new system data types,' making the OSF a logical and

easy-to-use architectural extension to iAPX 86, 88
system designs.

The OSP Approach
The OSP system data types (SOTs) and primitive instructions allocate, manage and share low-level processor resources in an efficient manner. For
example, the OSP implements task context management (managing a task state image consisting of
both hardware register set and software control information) for either the basic 86110 context or the
extended 86/20 (8086+8087) numerics context. The
OSP manages the entire task state image both while
the task is actively executing and while it is inactive.
Tasks can be created, put to sleep for specified periods, suspended, executed to perform their functions, and dynamically deleted when their functions
are complete.
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The Operating System Processors support eventoriented systems designs. Each event may be processed by an individual responding task or along
with other closely related events in a-common task.
External events and interrupts are processed by the
OSP interrupt handler primitives using its bUilt-in
interrupt controller subsystem as they occur in realtime. The multiple tasks and the multiple events are,
coordinated by the OSP integral scheduler whose
preemptive, priority-based scheduling algorithm
and system timers organize and monitor the processing of every task to guarantee that events are processed as they occur in order of relative importance.
The 86130 also provides primitives for interta$k communication (by mailboxes) and for mutual exclusion
(by regions), essential functions for multitasking
appl ications.

(Table 4). A representative ASM86 sequence for calling a primitive is shown in Figure 4. In PL/M the OSP
programmer uses a call to invoke the primitive.

SAMPLE ASSEMBLY LANGUAGE PRIMITIVE CALL
;PUSH PARAMETER 1
;PUSH PARAMETER 2

PUSH P N
:PUSH PARAMETER N
PUSH BP
;STACK CALLING CONVENTION
MOV BP,SP
LEA SI,SS:NUM_BYTES_PARAM , 2[BPI
,$5:$1 POINTS TO FIRST
,PARAMETER ON STACK
,AX seTS PRIMITIVE ENTRY CODE
MOVAX, ENTRY CODE
;OSF INTERRUPT
INT 184
QSP PRIMITIVE INVOKED
POP 8'P
RET NUM_BYTES_PARAM_
,pop PARAMETERS
,ex CONTAINS EXCEPTION CODES
;OL CONTAINS PARAMETER NUMBER
, THAT CAUSED EXCEPTION (IF
, ex IS NON ZERO)
;AX CONTAINS WORD RETURN VALUE
,ES:BX CONTAINS POINTER
:
RETURN VALUE

Programming Language Support
Programs for the OSP can be written in ASM 86/88 or
PL/M 86/88, Intel's standard system languages for
iAPX 86,88 systems.
The Operating System Processor Support Package
(iOSP 86) provides an interface library for application programs written in any model of PL/M-86. This
library also provides 80130 configuration and initialization support as well as complete user
documentation.

Figure 4. ASM/86 OSP Calling Convention

OSP Functional Description
Each major function of the OSP is described below.
These are:
Job and Task Management
Interrupt Management
Free Memory Management
Intertask Communication
Intertask Synchronization
Environmental Control

OSF PROGRAMMING INTERFACE
r

The OSF provides 35 operating system kernel
primitives which implement multitasking, interrupt
management, free memory management, intertask
communication and synchronization. Table 4 shows
each primitive, and Table 5 gives the execution performance of typical primitives.
OSP primitives are executed by a combination of
CPU and OSF (80130) activity. When an OSP primitive is called by an application program task, the
iAPX CPU registers and stacks are used to perform
the appropriate functions and relay the results to the
application programs.

OSP Primitive Calling Sequences
A standard, stack-based, calling sequence is used to
invoke the OSF primitives. Before a primitive is
called, its operand parameters must be pushed on
the task stack. The SI register is loaded with the
offset of the last parameter on the stack. The entry
code for the primitive is loaded into AX. The primitive
invocation call is made with a CPU software interrupt

The system data types'(or SDTs) supported by the
OSP are capitalized in the description. A short
description of each SDT appears in Table 2.

JOB and TASK Management
Each OSP JOB is a controlled environment in which
the applications program executes and the OSF system data types reside. Each individual application
program is normally a separate OSP JOB, whether it
has one initial task (the minimum) or multiple tasks.
JOBs partition the system memory into pools. Each
memory pool provides the storage areas in which the
OSP will allocate TASK state images and other system data types created by the executing TASKs, and
free memory for TASK working space. The OSP supports multiple executing TASKs within a JOB by
managing the resources used by each, including the
CPU registers, NPX registers, stacks, the system data
types, and the available free memory space pool.
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When a TASK is created, the OSP allocates memory
(from the free memory of its JOB environment) for
the TASK'u stack and data area and initializes the
additional TASK attributes such as the TASK priority
level and its error handler location. (As an option, the
caller of CREATE TASK may assign previously
defined stack and data areas to the TASK.) Task
priorities are integers between 0 and 255 (the lower
the priority number the higher the scheduling
priority of the TASK). Generally, priorities up to 128
will be assigned to TASKs which are to process interrupts. Priorities above 128 do not cause interrupts to
be disabled, these priorities (129 to 255) are appropriate for non-interrupt TASKs. If an 8087 Numerics
Processor Extension is used, the error recovery interrupt level assigned to it will have a higher priority
than a TASK executing on it, so that error handling is
performed correctly.

the OSP switches the control of the processor to the
higher priority TASK. First, the OSP saves the outgoing (lower priority) TASK's state including CPU register values in its TASK state image. Then, it restores
the CPU registers from the TASK state image of the
incoming (higher priority) TASK. Finally, it causes the
CPU to start or resume executing the higher priority
TASK.
TASK scheduling is performed by the OSp. The OSP's
priority-oriented preemptive scheduler determines
which TASK executes by comparing their relative
priorities. The scheduler insures that the highest
priority TASK with a status of READY will execute. A
TASK will continue to execute until an interrupt with a
higher priority occurs, or until it requests unavailable
resources, for which it is willing to wait, or until it
makes specific resources available to a higher
priority TASK waiting for those resources.

EXECUTION STATUS
A TASK has an execution status or execution state.
The OSP provides five execution states: RUNNING,
READY, ASLEEP, SUSPENDED, and ASLEEPSUSPENDED.

TASKs can become READY by receiving a message,
receiving control, receivi'ng an interrupt, or by timing
out. The OSP always monitors the status of all the
TASKs (and interrupts) in the system. Preemptive
scheduling allows the system to be responsive to the
external environment while only devoting CPU resources to TASKs with work to be performed.

-

A TASK is RUNNING if it has control of the
processor.

-

A TASK is READY if it is not asleep, suspended, or
asleep-suspended. For a TASK to become the running (executing) TASK, it must be the highest
priority TASK in the ready state.

-

A TASK is ASLEEP if it is waiting for a request to
be granted or a timer event to occur. A TASK may
put itself into the ASLEEP state.

-

A TASK is SUSPENDED if it is placed there by
another TASK or if it suspends itself. A TASK may
have multiple suspensions, the count of suspensions is managed by the OSP as the TASK suspension depth.

-

A TASK is ASLEE"P-SUSPENDED if it is both
waiting and suspended.

TASK attributes, the CPU register values, and the
8087 register values (if the 8087 is configured into
the application) are maintained by the OSP in the
TASK state image. Each TASK will have a unique
TASK state image.
SCHEDULING
The OSP schedules the processor time among the
various TASKs on the basis of priority. A TASK has an
execution priority relative to all other TASKs in the
system, which the OSP maintains for each TASK in its
TASK state image. When a TASK of higher priority
than the executing TASK becomes ready to execute,

TIMED WAIT
The OSP timer hardware facilities support timed
waits and timeouts. Thus, in many primitives, a TASK
can specify the length of time it is prepared to wait
for an event to occur, for the desired resources to
become available or for a message to be received at a
MAILBOX. The timing interval (or System Tick) can
be adjusted, with a lower limit of 1 millisecond.
APPLICATION CONTROL OF TASK EXECUTION
Programs may alter TASK execution status and
priority dynamically. One TASK may suspend its own
execution or the execution of another TASK for a
period of time, then resume its execution later. Multi-'
pie suspensions are provided. A suspended TASK
may be suspended again.

The eight OSP Job and TASK management primitives
are:
CREATE JOB

Partitions system resources and
creates a TASK execution
environment.

CREATE TASK

Creates a TASK state image.
Specifies the location of the
TASK code instruction stream,
its execution priority, and the
other TASK attributes.

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DELETE TASK

Deletes the TASK state image,
removes the instruction stream
from execution and deallocates
litack resources. Does not delete
INTERRUPT TASKS.

SUSPEND TASK

Suspends the specified TASK or,
if already suspended, increments its suspension depth
by one. Execute state is
SUSPEND.

RESUME TASK

Decrements the TASK suspension depth by one. If the suspension depth is then zero,
the primitive changes the task
execution status to READY,
or ASLEEP (if ASLEEP/
SUSPENDED).

SLEEP

SET PRIORITY

Places the requesting TASK in
the ASLEEP state for a specified
number of System Ticks. (The
TICK interval can be configured
down to 1 millisecond.)

INTERRUPT HANDLER can queue for the INTERRUPT TASK can be limited to the value specified in
the SET INTERRUPT primitive. When the INTERRUPT TASK is finished processing, it issues a WAIT
,INTERRUPT primitive, and is immediately ready to
process the queue of interrupts that the INTERRUPT
HANDLER has built with repeated SIGNAL INTERRUPT primitives while the INTERRUPT TASK was
processing. If there were no interrupts at the level,
the queue is empty and the INTERRUPT TASK is
SUSPENDED. See the Example (Figure 5) and Figures 6 and 7.
OSP external INTERRUPT LEVELs are directly
related to internal TASK scheduling priorities. The
OSP maintains a single list of priorities including
both tasks and INTERRUPT LEVELs. The priority of
the executing TASK automatically determines which
interrupts are masked. Interrupts are managed by
INTERRUPT LEVEL number. The OSP supports eight
levels directly and may be extended by means of
slave 8259As to a total of 57.
The nine Interrupt Management OSP primitives are:
DISABLE

Disables an external INTERRUPT LEVEL.

ENABLE

Enables an external INTERRUPT LEVEL.

ENTER INTERRUPT

Gives an Interrupt Handler
its own data segment, separate from the data segment
of the interrupted task.

EXIT INTERRUPT

Performs an "END of INTERRUPT' operation. Used by
an INTERRUPT HANDLER
which does not invoke an INTERRUPT TASK. Reenables
interrupts, when the INTERRUPT HANDLER gives up
control.

GET LEVEL

Returns the interrupt level
number of the executing INTERRUPT HANDLER.

RESET INTERRUPT

Cancels the previous assignment made to an
interrupt level by SET INTERRUPT primitive request.
If an INTERRUPT TASK has
been assigned, it is also
deleted. The interrupt level
is disabled.

SET INTERRUPT

Assigns an INTERRUPT
HANDLER to an interrupt
level and, optionally, an INTERRUPT TASK.

Alters the priority of a TASK.

Interrupt Management
The OSP supports up to 256 interrupt levels organized in an interrupt vector, and up to 57 external
interrupt sources of which one is the NMI (NonMaskable Interrupt). The OSP manages each interrupt level independently. The OSF INTERRUPT
SUBSYSTEM provides two mechanisms for interrupt
management: INTERRUPT HANDLERs and INTERRUPT TASKs. INTERRUPT HANDLERs disable all
maskable interrupts and should be used only for
servicing interrupts that require little processing
time. Within an INTERRUPT HANDLER only certain
OSF Interrupt Management primitives (DISABLE,
ENTER INTERRUPT, EXIT INTERRUPT, GET LEVEL,
SIGNAL INTERRUPT) and basic CPU instructions
can be used, other OSP primitives cannot be. The
INTERRUPT TASK approach permits all OSP
primitives to be issued and masks only lower priority
interrupts.
Work flow between an INTERRUPT HANDLER and an
INTERRUPT TASK assigned to the same level is
regulated with the SIGNAL IN"\ERRUPT and WAIT
INTERRUPT primitives. The flow is asynchronous.
When an INTERRUPT HANDLER signals an INTERRUPT TASK, the INTERRUPT HANDLER becomes
immediately available to process another interrupt.
The number of interrupts (specified for the level) the

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r

CODE. EXAMPLE A

INTERRUPT TASK TO KEEP TRACK OF TIME-OF-DAY

DECLARE SECOND$COUNT BYTE,
MINUTE$COUNT BYTE,
HOURS$COUNT BYTE:
TIME$TASK: PROCEDURE:
DECLARE TIME$EXCEPT$CODE WORD:
ACSCYCLESCOUNT=O:
CALL RQ$SET$INTERRUPT(AC$INTERRUPT$LEVEL, 01H),
@AC$HANDLER,O,@TIME$EXCEPT$CODE):
CALL RQ$RESUME$TASK(INIT$TASK$TOKEN,@TIME$EXCEPT$CODE):
DO HOUR$COUNT=O TO 23:
DO MINUTE$COUNT=O TO 59:
DO SECOND$COUNT=O TO 59:
CALL RQ$WAIT$INTERRUPT(AC$INTERRUPT$lEVEl,
@TIME$EXCEPT$CODE):
IF SECOND$COUNT MDD 5=0
THEN CALL PRDTECTED$CRT$OUT(BEL):
END:
SECOND LOOP '/
END:
MINUTE LOOP '/
END:
HOUR LOOP '/
CALL RQ$RESET$INTERRUPT(AC$INTERRUPT$LEVEL, @TlME$EXCEPT$CODE):
END TIME$TASK:

r

r

r

/' CODE EXAMPLE B
INTERRUPT HANDLER TO SUBDIVIDE A.C. SIGNAL BY 50.
DeCLARE AC$CYCLE$COUNT BYTE;

'/

AC$HANDLER: PROCEDURE INTERRUPT 59:
DECLARE AC$EXCEPTSCODE WORD:
AC$CYCLE$COUNT=AC$CYCLE$COUNT +1:
IF AC$CYCLE$COUNT> =50 THEN DO:
AC$CYCLE$COUNT=O:
CALL RQ$SIGNAL$INTERRUPT(AC$INTERRUPT$LEVEL,@AC$EXCEPT$CODE):
END:
END AC$HANDLER:

Figure 5. OSP Examples

YES

NO

INTERRUPT
HANDLER CALLS
EXIT$INTERRUPT

INTERRUPT
HANDLER CALLS
SIGNAL$INTERRUPT

INTERRUPT TASK
COMPLETES INTERRUPT
SERVICING

CONTROL RETURNS lOAN
APPLICATION TASK

Figure 6. Interrupt Handling Flowchart

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r-----------------------------------------------------------------------------

~.[!]

O
!

~~~::"
I

---

J
........ ,

/ /

"

"

INTERRUPT
TASK

,

~
"

,_.... ,/

"- '\
\

/

 .... __ "'~

\

I @

INTERRUPT
TASK

I

PROCESSES
FULL BUFFER

I

Figure 7. Multiple Buffer Example

SIGNAL INTERRUPT

Used by an INTERRUPT
HANDLER to activate an Interrupt Task.

WAIT INTERRUPT

Suspends the calling Interrupt Task until the INTERRUPT HANDLER performs a
SIGNAL INTERRUPT to invoke it. If a SIGNAL INTERRUPT for the task has
occurred, it is processed.

FREE MEMORY MANAGEMENT
The OSP Free Memory Manager manages the
memory pool which is allocated to each JOB for its
execution needs. (The CREATE JOB primitive allocates the new JOB's memory pool from the
memory pool of the parent JOB.) The memory pool is
part of the JOB resources but is not yet allocated
between the tasks of the JOB. When a TASK, MAILBOX, or REGION system data type structure is
created within that JOB, the OSP implicitly allocates
memory for it from the JOB's memory pool, so that a
separate call to allocate memory is not required. OSP
primitives that use free memory management implicitly include CREATE JOB, CREATE TASK,
DELETE TASK, CREATE MAILBOX, DELETE MAILBOX, CREATE REGION, and DELETE REGION. The

CREATE SEGMENT primitive explicitly allocates a
memory area when one is needed by the TASK. For
example, a TASK may explicitly allocate a SEGMENT
for use as a memory buffer. The SEGMENT length
can be any multiple of 16 bytes between 16 bytes and
64K bytes in length. The programmer may specify
any number of bytes from 1 byte to 64 KB, the OSP
will transparently round the value up to the appropriate segment size.
The two explicit memory
primitives are:

~lIocation/dealiocation

CREATE SEGMENT

Allocates a SEGMENTof specified length (in 16-byte-long
paragraphs) from the JOB
Memory Pool.

DELETE SEGMENT

Deallocates the SEGMENT's
memory area, and returns it
to the JOB memory pool.

Intertask Communication
The OSP has built-in intertask synchronization and
communication, permitting TASKs to pass and share
information with each other. OSP MAILBOXes contain control/ed handshaking facilities which guarantee that a complete message will always be sent from
a sending TASK to a reeeiving TASK. Each MAILBOX
consists of two interlocked queues, one of TASKs

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There are five OSP primitives for mutual exclusion:

and the other of Messages. Four OSP primitives for
intertask synchronization and communication are
provided:

CREATE REGION

Create a REGION (lock).

SEND CONTROL

Give up the REGION.

CREATE MAILBOX

Creates intertask message
exchange.

ACCEPT CONTROL

DELETE MAILBOX

Deletes an intertask message exchange.

Request the REGION, but do
not wait if it is not available.

RECEIVE CONTROL

RECEIVE MESSAGE

Calling TASK receives a message from the MAILBOX.

Request a REGION, wait if
not immediately available.

DELETE REGION

Delete a REGION.

SEND MESSAGE

Calling TASK sends a
message to the MAILBOX.

The OSP also provides dynamic priority adjustment
for TASKs within priority REGIONs: If a higherpriority TASK issues a RECEIVE CONTROL primitive,
while a (lower-priority) TASK has the use of the same
REGION, the lower-priority TASK will be transparently, and temporarily, elevated to the waiting
TASK's priority until it relinquishes the REGION via
SEND CONTROL. At that point, since it is no longer
using the critical resource, the TASK will have its
normal priority restored.

The CREATE MAILBOX primitive allocates a MAILBOX for use as an information exchange between
TASKs. The OSP will post information at the MAILBOX in a FIFO (First-In First-Out) manner when a
SEND MESSAGE instruction is issued. Similarily, a
message is retrieved by the OSP if a TASK issues a
RECEIVE MESSAGE primitive. The TASK which
creates the MAILBOX may make it available to other
TASKs to use.

OSP Control Facilities

If no message is availab!e, the TASK attempting to
receive a message may choose to wait for one or
continue executing.

The OSP also includes system primitives that provide
both control and customization capabilities to a mUltitasking system. These primitives are used to control
the deletion of SDTs and the recovery of free memory
in a system, to allow interrogation of operating system status, and to provide uniform means of adding
user SDTs and type managers.

The queue management method for the task queue
(FIFO or PRIORITY) determines which TASK in the
MAILBOX TASK queue will receive a message from
the MAILBOX. The method is specified in the
CREATE MAILBOX primitive.

Intertask Synchronization and Mutual
Exclusion
Mutual exclusion is essential to multiprogramming
and multiprocessing systems. The REGION system
data type implements mutual exclusion. A REGION is
represented by a queue of TASKS waiting to use a
resource which must be accessed by only one TASK
at a time. The OSP provides primitives to use
REGIONs to manage mutually exclusive data and
resources. Both critical code sections and shared
data structures can be protected by these primitives'
from simultaneous use by more than one task.
REGIONs support both FIFO (First-In First-Out) or
Priority queueing disciplines for the TASKS seeking
to enter the REGION. The REGION SDT can also be
used to implement software locks.

DELETION CONTROL
Deletion of each OSP system data type is explicitly
controlled by the applications programmer by setting a deletion attribute for that structure. For example, if a SEGMENT is to be kept in memory until DMA
activity is completed, its deletion attribute should be
disabled. Each TASK, MAILBOX, REGION, and SEGMENT SDT is created with its deletion attribute enabled (i.e., they may be deleted). Two OSP primitives
control the deletion attribute: ENABLE DELETION
and DISABLE DELETION.
ENVIRONMENTAL CONTROL
The OSP provides inquiry and control operations
. which help the user interrogate the application environment and implement flexible exception handling.
These features aid in run-time decision making and
in application error processing and recovery. There
are five OSP environmental control primitives.

Multiple REGIONs are allowed, and are automatically
exited in the reverse order of entry. While in a
REGION, a TASK cannot be suspended by itself or
any other TASK, and thereby avoids deadlock.

OS EXTENSIONS
The OSP architecture is defined to allow new userdefined System Data Types and the primitives to manipulate them to be added to OSP capabilities
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provided by the built-in System Da~a Types. The type
managers created for the user-defined SDTs are
called user OS extensions and are installed in the
system by the SET OS EXTENSION primitive. Once
installed, the functions of the type manager may be
invoked with user primitives conforming to the OSP
interface. For well-structured extended architectures, each OS extension should support a separate
user-defined system data type, and every OS ext~n­
sion should provide the same calling sequence and
program interface for the user as is provided for a
built-in SDT. The type manager for the extension
would be written to suit the needs of the application.
OSP interrupt vector entries (224-255) are reserved
for user OS extensions and are not used by the OSP.
After assigning an interrupt number to the extension,
the extension user may then call it with the standard
OSP call sequence (Figure 4), and the unique
software interrupt number assigned to the
extension. '

allow the OSP primitives,to, report parameter errors
in primitive calls,and errors in primitive usage. Exception handling procedures are flexible and can be
individually programmed by the application. In general, an exception handler if called will perform one
or more of the following functions:
-Log the Error.
-Delete/Suspend the Task that caused the
exception.
-Ignore the error, presumably because it is not
serious.
An EXCEPTION HANDLER is written as a procedure.
If PLM/86 is used, the "compact," "medium" or
"large" model of computation should be specified for
the compilation of the program. The mode in which
the EXCEPTION HANDLER operates may be specified in the SET EXCEPTION HANDLER primitive. The
return information from a primitive call is shown in
Figure 4 .. CX is used to return standard system error
conditions. Table 7 shows a list of these conditions,
using the default EXCEPTION HANDLER of the OSP.

ENABLE DELETION

jI.llows a specific SEGMENT,
TASK, MAILBOX, or REGION
SDT to be deleted.

DISABLE DELETION

Prevents a specific SEG- .
MENT, TASK, MAILBOX, or
REGION SDT from being
deleted.

GET TYPE

Given a token for an instance of a system data type,
returns the type code.

GET TASK TOKENS

Returns to the caller information about the current
task environment.

GET EXCEPTION
HANDLER

Returns information about
the calling TASK's current information handler: its address, and when it is used.

SET EXCEPTION
HANDLER

Provides the address and
usage of an exception
handler for a TASK.

SET OS EXTENSION

Modifies one of the interrupt
vector entries reserved for
OS extensions (224-255) to
ppint to a user OS extension
procedure.

SIGNAL EXCEPTION

For use in OS extension error processing.

EXCEPTION HANDLING
The OSP supports exception handlers. These are
similar to CPU exception handlers such as OVERFLOW and ILLEGAL OPERATION. Their purpose is to

HARDWARE DESCRIPTION
The 80130 operates in a closely coupled mode with
the iAPX 86/10 or 88/10 CPU. The 80130 resides on
the CPU local multiplexed bus (Figure 8). The main
processor is always configured for maximum mode
operation. The 80130 automatically selects oetween
its 88/30 and 86/30 operating modes.
The 80130 used in the 86/30 configuration, as shown
in Figure 8 (or a similar 88/30 configuration),
operates at both 5 and 8 MHz without requiring processor wait states. Wait state memories are fully supported, however. The 80130 may be configured with
both an 8087 NPX and an 8089 lOP, and provides
full context control over the 8087.
The 80130 (shown in Figure 3) is internally divided
into a control unit (CU) and operating system unit
(OSU). The OSU contains facilities for OSP kernel
support including the system timers for scheduling
and timing waits, and the interrupt controller for
interrupt management support.

iAPX 86/30, iAPX 88/30 System
Configuration
The 80130 is both I/O and memory mapped to the
local CPU bus. The CPU's status SOI-S21 is
decoded along with 10CSI (with BHE and AD3ADo) or MEMCSI (with AD13-ADo). The pins are
internally latched. See Table 1 for the decoding of
these lines.
3-208

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inter

80130/80130·2
iAPX 86/30, 88/30, 186/30, 188/30

Memory Mapping

RAM Requirements

Address lines A19 -A14 can be used to form MEMCS/
since the 80130's memory-mapped portion is aligned
along a 16K-byte boundry. The 80130 can reside on
any 16K-byte boundry excluding the highest
(FCOOOH-FFFFFH) and lowest (00000H-003FFH). The
80130 control store code is position-independent except as limited above, in order to make it compatible
with many decoding logic designs. AD13-ADo are
decoded by the 80130's kernel control store.

The OSP manages its own interrupt vector, which is
assigned to low RAM memory. Working RAM storage
is required as stack space and data area. The
memory space must be allocated in user RAM. .

I/O Mapping
The I/O-mapped portion of the 80130 must be aligned
along a 16-byte boundry. Address lines A1S -A4
should be used to form 10CS/.

System Performance
The approximate performance of representitive OSP
primitives is given in Table 5. These times are shown
for a typical iAPX 86/30 implementation with an 8
MHz clock. These execution times are very comparable to the execution times of similar functions in
minicomputers (where available) and are an order of
magnitude faster than previous generation
microprocessors.

OSP interrupt vector memory locations OH-3FFH
must be RAM based. The OSP requires 2 bytes of
allocated RAM. The processor working storage is
dynamically allocated from free memory. Approximately 300 bytes of stack should be allocated for
each OSP task.

TYPICAL SYSTEM CONFIGURATION
Figure 8 show.s the processing cluster of a "typical"
iAPX 86/30 or iAPX 88/30 OSP system. Not shown are
subsystems likely to vary with the application. The
configuration includes an 8086 (or 8088) operating in
maximum mode, an 8284A clock generator and an
8288 system controller. Note that the 80130 is located
on the CPU side of any latches or transceivers. See
Intel Application Note 130 for further details on
configuration.

OSP Timers
Initialization.
Both application system initialization and OSPspecific initialization/configuration are required to
use the OSp. Configuration is based on a "database"
provided by the user to the iOSP 86 support package.
The OSP-specific initialization and configuration information area is assigned to a user memory address
adjacent to the 80130's memory-mapped location.
(See Application Note 130 for further details.) The
configuration data defines whether 8087 support is
configured in the system, specifies if slave 8259A
interrupt controllers are used in addition to the
80130, and sets the operating system time base (Tick
Interval). Also located in the configuration area are
the exception handler control parameters, the address location of the (separate) application system
configuration area and fhe OSP extensions in use.
The OSP application sY'3tem configuration area may
be located anywhere in the user memory and must
include the starting address of the application instruction code to be executed, plus the locations of
the RAM memory blocks to be managed by the OSP
free memory manager. Complete application system
support and the required 80130 configuration support are provAded by the iAPX 86/30 and iAPX 88/30
OPERATING SYSTEM PROCESSOR SUPPORT
PACKAGE (iOSP 86).

The OSP Timers are connected to the lower half of
the data bus and are addressed at even addresses.
The timers are read as two successive bytes, always
LSB followed by MSB. The MSB is always latched on
a read operation and remains latched until read.
Timers are not gatable.

Baud Rate Generator
The baud rate generator is 8254 compatible (square
wave mode 3). Its output, BAUD, is initially high and
remains high until the Count Register is loaded. The
first falling edge of the clock after the Count Register
is loaded causes the transfer of the internal counter
to the Count Register. The output stays high for N/2
[(N+1)/2 if N is odd] and then goes low for N/2
[(N-1)/2 if N is odd]. On the falling edge of the clock
which signifies the final count for the output in low
state, the output returns to high state and the Count
Register is transferred to the internal counter. The
whole process is then repeated. Baud Rates are
shown in Table 6.
The baud rate generator is located at OCH (12), relative to the 16-byte boundary in the I/O space in which
the 80130 component is located ("OSF" in the following example), the timer control word is located at
3-209

210216-002

intJ

80130/80130·2
iAPX 86/30, 88/30, 186/30, 188/30

elK

0

f-

CONTROL

M

elK

!lii_

~

8288

~

8086

F==il

BHE
A1.

~RESS/O~
INTR

BHE
A1.

ADDRESS

t-----

ADO

AD

'--

-=
8286

C-

INT
elK

S2

/1.

!lii~

ADO
lOCi

~

MEMes

r-

DECODE
LOGIC

015

"
~

b

,
,

DO

J

"

AeK
llA
lAO

lA'
SVSTICK

~~

,

A015

LOCAL
AND
SYSTEM
RESOURCES

J--

8282

INTERRUPT REoueSTS

~

IR2

Figure 8. Typical OSP Configuration

relative address, OEH(14). Timers are addressed with
IOCS=O. Timers 0 and 1 are assigned to the use by
the OSp, and should not be altered by the user.
For most baud-rate generator applications, the command byte
OB6H

Read/Write Baud-Rate Delay Value

will be used. A typical sequence to set a baud rate
of 9600 using a count value of 52 follows (see
Table 6):
;Prepare to Write Delay to
Timer 3.
OUT OSF+14,AX ;Control Word.
MOV AX, 52
OUT OSF+12,AL ;LSB written first
XCHG AL,AH
OUT OSF+12,AL ;MSB written after.
MOV . AX,.OB6H

The 80130 timers are subset compatible with 8254
timers.

Interrupt Controller
The Programmable Interrupt Controller (PIC), is also
an integral unit of the 80130. Its eight input pins
handle eight vectored priority interrupts. One of
these pins must be used for the SYSTICK time function in timing waits, using an external connection as
shown. During the 80130 initialization and configuration sequence, each 80130 interrupt pin is individually programmed as either level or edge sensitive.
External slave 8259A interrupt controllers can be
used to expand the total number of OSP external
interrupts to 57.
In addition to standard PIC. funtions, 80130 PIC unit
has an LlR output signal, which when low indicates
an interrupt acknowledge cycle. LlR=O is provided to
control the 8289 Bus Arbiter SYSB/RESB pin. This
will avoid the need of requesting the system bus to
acknowledge local bus non-slave interrupts. The
user defines the interrupt system as part of the
configuration.
3-210

210216-002

80130/80130-2
iAPX 86/30, 88/30, 186/30, 188/30

INTERRUPT SEQUENCE
The OSP interrupt sequence is as follows:

signal which drives one of 80130 edge-triggered interrupt request pins once each A.C. cycle. The Interrupt Handler responds to the interrupts, keeping
track of one second's A.C. cycles. The Interrupt Task
counts the seconds and after a day deletes itself. In
typical systems it might perform a data logging operation once each day. The Interrupt Handler and InterruptTask are written as separate modular programs.

1. One or more of the interrupts is set by a low-tohigh transition on edge-sensitive IR inputs or by a
high input on level-sensitive IR inputs.
2. The 80130 evaluates these requests, and sends an
INT to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds
with an interrupt acknowledge cycle which is encoded in 8 2 -S 0 .
4. Upon receiving the first interrupt acknowledge
from the CPU, the highest-priority interrupt is set
by the 80130 and the corresponding edge detect
latch is reset. The 80130 does not drive the address/data bus during this bus cycle but does
acknowledge the cycle by making ACK=O and
sending the LlR value for the IR input being
acknowledged.
5. The CPU will then initiate a second interrupt acknowledge cycle. During this cycle, the 80130 will
supply the cascade address of the interrupting
input at T1 on the bus and also release an 8-bit
pointer onto the bus if appropriate, where it is
read by the CPU. If the 80130 does supply the
pointer, then ACK will be low for the cycle. This
cycle also has the value LlR for the IR input being
acknowledged.
6. This completes the interrupt cycle. The ISR bit
remains set until an appropriate EXIT INTERRUPT
primitive (EOI command) is called at the end of
the Interrupt Handler.

OSP APPLICATION EXAMPLE
Figure 5 shows an application of the OSP primitives
to keep track of time of day in a simplified example.
The system design uses a 60 Hz A.C. signal as a time
base. The power supply provides a TTL-compatible

The Interrupt Handler will actually service interrupt
59 when it occurs. It simply counts each interrupt,
and at a count of 60 performs a SIGNAL INTERRUPT
to notify the InterruptTask that a second has elapsed.
The Interrupt Handler (ACS HANDLER) was assigned
to this level by the SET INTERRUPT primitive. After
doing this, the InterruptTask performed the Primitive
RESUME TASK to resume the application task (IN ITS
TASKS TOKEN).
The main body of the task is the counting loop. The
InterruptTask is signaled by the SIGNAL INTERRUPT
primitive in the Interrupt Handler (at interrupt level
ACS INTERRUPTS LEVEL). When the task is signalled by the Interrupt Handler it will execute the
loop exactly one time, increasing the time count
variables. Then it will execute the WAIT INTERRUPT
primitive, and wait until awakened by the Interrupt
Handler. Normally, the task will now wait some period
of time for the next signal. However, since the interface between the Handler and the Task is asynchronous, the handler may have already queued the
interrupt for servicing, the writer of the task does not
have to worry about this possibility.
At the end of the day, the task will exit the loop and
execute RESET INTERRUPT, which disables the interrupt level, and deletes the interrupt task. The OSP
now reclaims the memory used by the Task and
schedules another task. If an exception occurs, the
coded value for the exception is available in TIMES
EXCEPTS CODE after the execution of the primitive.
A typical PL/M-86 calling sequence is illustrated by
the call to RESET INTERRUPT shown in Figure 5.

3-211

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80130/80130-2
iAPX 86/30, 88/30, 186/30, 188/30

Table 2. OSP System Data TYpe Summary
Job

Jobs are the means of organizing the program environment and resources. An application consists of
one or more jobs. Each iAPX 86/30 system data type is contained in some job. Jobs are independent of
each other, but they may share access to resources. Each job has one or more tasks, one of which is an
initial task. Jobs are given pools of memory, and they may create subordinate offspring jobs, which
may borrow memory from their parents.

Task

Tasks are the means by which computations are accomplished. A task is an instruction stream with its
own execution stack and private data. Each task is part of a job and is restricted to the resources
provided by its job. Tasks may perform general interrupt handling as well as other computational
functions. Each task has a set of attributes, which is maintained for it by the iAPX 86/30, which
characterize its status. These attributes are:
its
its
its
its
its
its
its

containing job
register context
priority,(0-255)
execution state (asleep, suspended, ready, running, asleep/suspended).
suspension depth
user-selected exception handler
optional 8087 extended task state

Segment

Segments are the units of memory allocation. A segment is a physically contiguous sequence of
16-byte, 8086 paragraph-length, units. Segments are created dynamically from the free memory
space of aJob as oneof its Tasks requests memory for its use.Asegment is deleted when it is no longer
needed. The iAPX 86/30 maintains and manages free memory in an orderly fashion, it obtains memory
space from the pool al?signed to the containing job of the requesting task and returns the space to the
job memory pool (or the parent job pool) whim it is no longer needed. It does not allocate memory to
create a segment if sufficient free memory is not available to it, in that case it returns an error
I
exception code.

Mailbox

Mailboxes are the means of intertask communication. Mailboxes are used by tasks to send and
receive message segments. The iAPX 86/30 creates and manages two queues for each maHbox. One
of these queues contains message segments sent to the mailbox but not yet received by any task. The
other mailbox queue consists of tasks that are waiting to receive messages. The iAPX 86/30 operation
assures that waiting task.s receive messages as soon as messages are available. Thus at any moment
one or possibly both of two mailbox queues will be empty.

Region

Regions are the means of serialization and mutual exclusion. Regions are familiar as "critical code
regions." The iAPX 86/30 region data type consists of a queue of tasks. Each task waits to execute in
mutually exclusive code or to access a shared data region, for example to update a file record.

Tokens

The OSP interface makes use of a 16-bitTOKEN data type to identify individual OSF data structures.
Each of these (each instance) has its own unique TOKEN. When a primitive is called, it is passed the
TOKENs of the data structures on which it will operate.

3-212

210216-002

inter

80130/80130·2

iAPX 86/30, 88/30, 186/30, 188/30

Table 3. System Data Type Codes and Attributes
Attributes

S.D.T.

Code

Jobs

1

Tasks
Memory Pool
S.D.T. Directory

Tasks

2

Priority
Stack
Code
State
Exception Handler

Mailboxes

3

Queue of S.D.T.s
(generally segments)
Queue ofTasks
waiting for S.D.T.s

Region

5

Queue of Tasks
waiting for mutually
exclusive code or
data

Segments

6

Buffer
Length

Table 4. OSP Primitives
Class
J
0
B

T
A
S
K

I
N
T
E
.R
R
U
P
T

S
E
G
M
E
N
T

OSP
Primitive

Parameters
On Caller's Stack

Interrupt
Number

Entry Code
in AX

CREATE JOB

184

0100H

'See 80130 User Manual

CREATE TASK

184

0200H

DELETE TASK
SUSPEND TASK
RESUME TASK
SET PRIORITY
SLEEP

184
184
184
184
184

0201H
0202H
0203H
0209H
0204H

Priority, IP Ptr, Data Segment, Stack
Seg, Stack Size Task Information,
ExcptPtr
TASK, ExcptPtr
TASK, ExcptPtr
TASK, ExcptPtr
TASK, Priority, ExcptPtr
Time Limit,ExcptPtr

DISABLE
ENABLE
ENTER INTERRUPT
EXIT INTERRUPT
GET LEVEL
RESET INTERRUPT
SET INTERRUPT

190
184
184
186
188
184
184

0705H
0704H
0703H
NONE
0702H
0706H
0701H

SIGNAL INTERRUPT
WAIT INTERRUPT

185
187

NONE
NONE

Level, ExcptPtr
Level #.. ExcptPtr
Level #, ExcptPtr
Level # ,ExcptPtr
Level #, ExcptPtr
Level #, ExcptPtr
Level, Interrupt Task Flag Interrupt
Handler Ptr, Interrupt Handler DataSeg
ExcptPtr
Level, ExcptPtr
Level, ExcptPtr

CREATE SEGMENT
DELETE SEGMENT

184
184

0600H
0603H

Size, ExcptPtr
SEGMENT, ExceptPtr

3-213

210216-002

inter

80130/80130-2
iAPX 86/30, 88/30, 186/30, 188/30

Table 4.
Class
M
A
I
L
B

0

asp

asp Primitives (Continued)

Primitive

Interrupt
Number

Entry Code
In AX

CREATE MAILBOX
DELETE MAILBOX
RECEIVE MESSAGE

184
184
184

0300H
0301H
0303H

SEND MESSAGE

184

0302H

Parameters
On Caller's Stack
Mailbox flags, ExcptPtr
i
MAILBOX, ExcptPtr
MAILBOX, Time Limit ResponsePtr,
ExcptPtr
MAILBOX,Message Response, ExcptPtr

~i

X
R
E
G
I

0

ACCEPT CONTROL
CREATE REGION
DELETE REGION
RECEIVE CONTROL'
SEND CONTROL

184
184
184
184
184

0504H
0500H
0501H
0503H
0502H

REGION, ExcptPtr
Region Flags, ExcptPtr
REGION, ExcptPtr
REGION, Excp~Ptr
ExcptPtr

DISABLE DELETION
ENABLE DELETION
GET EXCEPTION
HANDLER
GET TYPE
GET TASK TOKENS
SET EXCEPTION
HANDLER
SET OS EXTENSION
SIGNAL
EXCEPTION

184
184

0OO1H
0OO2H

TOKEN,ExcptPtr
TOKEN,ExcptPtr

184
184
184

0800H
OOOOH
0206H

Ptr,ExcptPtr
TOKEN,ExcptPtr
Request, ExcptPtr

184
184

0801H
0700H

Ptr, ExcptPtr
Code,lnstPtr, ExcptPtr

184

0802H

Exception Code, Parameter Number,
StackPtr,O,O,ExcptPtr

N
E
N
V
I
R

0
N
M
E
N
T
A
L

,

NOTES:

All parameters are pushed onto the OSP stack. Each parameter is one word. See Figure 3 for Call Sequence.
Explanation of the Symbols
JOB
TASK
REGION
MAILBOX
SEGMENT
TOKEN

OSP JOB SOT Token
OSP TASK SOT Token
OSP, REGION SOT Token
OSP, MAILBOX SOT Token
OSP SEGMI'NT SOT Token
Any SOT Token

Level
ExcptPtr
Message
Ptr
Seg

Interrupt Level Number
Pointer to Exception Code
Message Token
Pointer to Code,Stack etc. Address
Value Loaded into appropriate Segment Register'
Value Parameter.

3-214

210216-002

intJ.

80130/80130-2
iAPX 86/30, 88/30, 186/30, 188/30

Table 5. OSP Primitive Performance Examples '
Primitive Execution Speed(microseconds)

Datatype Class
JOB
TASK
SEGMENT
MAILBOX

CREATE JOB
CREATE TASK (no preemption)
CREATE SEGMENT
SEND MESSAGE (with task switch)
SEND MESSAGE (no task switch)
RECEIVE MESSAGE (task waiting)
RECEIVE MESSAGE (message waiting)
SEND CONTROL
RECEIVE CONTROL

REGION
'8 MHz iAPX 86/30

2950
1360
700
475
265
540
260
170
205

asp Configuation.

Table 6. Baud Rate Count Values (16X)
Baud
Rate

8 MHz Count
Value

5 MHz Count
Value

300
600
1200
2400
4800
9600

1667
833
417
208
104
52

1042
521
260
130
65
33

3-215

210216-002

inter

80130180130-2
IAPX 86/30, 88/30, 186/30, 188/30

Table 7a. Mnemonic Codes for Unavoidable Exceptlo!,s
E$OK

Exception Code Value - 0
the operation was successful

,
E$TIME

Exception Code Value - 1
the specified time limit expired before completion of the operations was possible

E$MEM

Exception Code Value = 2
insufficient nucleus memory is available to satisfy the request

E$BUSY

Exception Code Value = 3
specified region is currently busy

E$LIMIT

Exception Code Value = 4
atte"!1pted violation of a job, semaphore, or system limit

E$CONTEXT

Exception Code Value - 5
the primitive was called in an illegal context (e.g., call to enable for an already enabled
interrupt)

E$EXIST

Exception Code Value = 6
a token argument does not currently refer to any object; note that the object could have
been deleted at any time by Its owner

- E$STATE

Exception Code Value = 7
attempted illegal state transition by a task

E$NOT$CONFIGURED

Exception Code Value = 8
the primitive called is not configured in this system

E$INTERRUPT$SATURATION Exception Code Value - 9
The interrupt task on the requested level has reached its user specified saturation point
for interrupt service requests. No further interrupts will be allowed on the level until the
interrupt task executes a WAIT$INTERRUPT. (This error is only returned, in line, to
interrupt handlers.)
E$INTERRUPT$OVERFLOW

Exception Code Value - 10
The interrupt task on the requested level previously reached its saturation point and
, caused an E$INTERRUPT$SATURATION condition. It subsequently execllted an
ENABLE allowing further interrupts to come in and has received another SIGNAL$INTERRUPTcall, bringing it over its specified saturation point for interrupt service
requests. (This error is only returned, in line, to interrupt handlers).

Table 7b. Mnemonic Codes for Avoidable Exceptions
E$ZERO$DIVIDE

Exception Code Value - 8000H
divide by zero interrupt occurred

E$OVERFLOW

Exception Code Value - 8001 H
overflow interrupt occurred

E$TYPE

Exception Code Value,= 8002H
a token argument referred to an object tha was not of required type

E$BOUNDS
/

Exception Code Value = 8003H
an offset argument is out of segment bounds

E$PARAM

Exception Code Value = 8004H
a (non-token,non-offset) argument has an illegal value

E$BAD$CALL

Exception Code Value = 8005H
an entry code for which there is no corresponding primitive was passed

\

E$ARRAY$BOUNDS - 8006H Hardware or Language has detected an array overflow
E$NDP$ERROR

Exception Code Value - 8007H
an 8087 (Numeric data Processor) error has been detected; (the 8087 status information
is contained in a parameter to the exception handler)

3-216

210216-002

80130/80130-2
iAPX 86/30, 88/30, 186/30, 188/30

ABSOLUTE MAXIMUM RATINGS*

"NOTICE: Stresses above those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability.

Ambient Temperature Under Bins ......... O'G to 70'G
Storage Temperature ................. -65°G to 150°C
Voltage on Any Pin With
Respect to Ground .................. - 1.0V to +7V
Power Dissipation .......................... 1.0 Watts

D.C. CHARACTERISTICS
Symbol

(T. =O°C to 70°C, Vee =4.5 to 5.5V)
Min.

Max.

Units

V'L
V,H

Input Low Voltage

- 0.5

0.8

Input High Voltage

2.0

V
V

VOL
VOH

Output Low Voltage

Icc
III
ILR

,

Parameter

Output High Voltage
Power Supply Current

Vcc +.5
0.45

V

10L ~ 2mA

V
200

rnA

10H ~ -400/LA
T. ~ 25 C

10

/LA

O

FLOAT

®

POINTER

I

-------I
I

r-rCHEH

---v---

TCHEH

J

NOTES
1 CASCADE ADDRESS PRESENTED ON ADS A09 AND A010 CORRESPONDING TO CASO CASt
AND CAS2 RESPECTIVELY A011-A01 5 LINES ARE ACTIVE AND HAVE UNKNOWN VALUES ADO-A07
ARE TRISTATE
2

POINTER VALUE IS ACTIVE ONLY IF POINTER IS GENERATED FROM THE 80150 AND NOT FROM

EXTERNAL SLAVE UNIT
ACTIVE LOWDNlY WHEN POINTER DATA IS BEING SUPPLIED BY T-HF 80150
LOW ONLY FOR LOCAL INTERRUPT

3-231

210705-003

828218283
OCTAL LATCH

• Address Latch for iAPX 86,88,186,
188, MCS®·80, MCS·85 , MCS·48
Famlies

•

3·State Outputs

•

20·Pin Package with 0.3" Center

•

High Output Drive Capability for
Driving System Data Bus

•

No Output Low Noise when Entering
or Leaving High Impedance State

•

Fully Parallel 8·Blt Data Register and
Buffer

•

•

Transparent during Active Strobe

Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range

The 8282 and 8283 are 8-bit bipolar latches with 3-state output buffers_ They can be used to implement latches, buffers,
or multiplexers. The 8283 inverts the input data at its outputs while the 8282 does not. Thus, all of tbe principal peripheral and input/output functions of a microcomputer system can be implemented with these devices.

1

/'

&--

Figure 1. Logic Diagrams

Figure 2. Pin Configurations

3-232

intJ

8282/8283

Table 1. Pin Description
Pin
STB

OE

FUNCTIONAL DESCRIPTION

Description
STROBE (Input). STB is an input control
pulse used to strobe data at the data input
pins (Ao-A7) into the data latches. This
signal is active HIGH to admit Input data.
The data is latched at the H1GH to LOW
transition of STB.
OUTPUT ENABLE (Input). <5E Is an input
control signal which when active LOW
enables the contents of the data latches
onto the data output pin (Bo-B7). OE being
inactive HIGH forces the output buffers to
their high impedance state.

010- 017

DATA INPUT PINS (Input). Data presented
at these pins satisfying setup lime reo
qulrements when STB is strobed and
latched into the data input latches.

000-00 7
(8282)
000-5(j7
(8283)

DATA OUTPUT PINS (Output). When OE is
true, the data in the data latches Is presented as inverted (8283) or non·inverted
(8282) data onto the data output pins.

The 8282 and 8283 octal latches are 8-bit latches with
3-state output buffers. Data having satisfied the setup
time requirements is latched into the data latches by
strobing the STB line HIGH to LOW. Holding the STB
line in its active HIGH state makes the latches appear
transparent. Data is presented to the data output pins by
activating the OE input line. When OE is inactive HIGH
the output buffers are in their high impedance state.
Enabling or disabling the output buffers will not cause
negative·going transients to appear on the data output
bus.

3-233

inter

8282/8283

ABSOLUTE MAXIMUM RATINGS·

'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Temperature Under eias ................. O·C to 70·C
Storage Temperature ............. - 65°C to + 150°C
All Output and Supply Voltages ........ - 0.5V to + 7V
All Input Voltages .................. - 1.0V to + 5.5V
Power Dissipatiol! .......................... 1 Watt

D.C. CHARACTERISTICS
Symbol

(Vcc = 5V ±10%, TA =

Parameter

o·c to 700C)
Max.

Units

Vc

Input Clamp Voltage

-1

V

Icc

Power Supply Current

160

rnA

Min.

Test Conditions
Ic'= -5 rnA

IF

Forward Input Current

-0.2

rnA

VF = 0.45V

IR

Reverse Input Current

50

,.A

V R = 5.25V

VOL

Output low Voltage

.45

V

IOL = 32 rnA

VOH

Output High Voltage

IOFF

Output Off Current

VIL

Input low Voltage

VIH

Input High Voltage

C tN

Input Capacitance,

2.4

V

IOH = -5 rnA

±50

,.A

VO FF = 0.45 to 5.25V

0.8

V

Vcc= 5.0V

See Nole

V

Vcc=5.0V

See Note 1

2.0
12

1

F= 1 MHz
V SIAS =2.5V, Vcc=5V
TA=25°C

pF

NOTE:

1. Output loading ioL = 32 mA, IOH = -5. mA, CL = 300 pF.'

A.C. CHARACTERISTICS
Symbol
TIVOV

TSHOV

o·c

(Vcc = 5V ±100/o, TA =
to 70·C (See Note 2)
loading: Outputs-IOl = 32 rnA, IOH = -5 rnA, Cl = 300 pF')
Min.

Max.

Units

Input to Output Delay
-Inverting
-Non·lnverting

Parameter

5
5

22

30

ns
ns

STe to Output Delay
-Inverting
-Non-Inverting

10
10

40
45

ns
ns

Test Conditions
(See Note 1)

TEHOZ

Output Disable Time

5

18

ns

TElOV

Output Enable Time

10

30

ns

TIVSl

Inpuno STe Setup Time

0

ns

TSLIX

Input to STe Hold Time

25

ns

TSHSl

STe High Time

15

TOlOH

Input, Output Rise Time

20.

ns

From 0.8V to 2.0V

TOHOl

Input, Output Fall Time

12

ns

From 2.0V to 0.8V

ns

NOTE:
'CL = 200 pF for plastic 828218283.
1. See waveforms and test load circuit on following page.
2. For Extended Temperature EXPRESS the Preliminary Maximum Values are TIVOV = 25 vs 22, 35 vs 30;
TSHOV = 45, 55; TEHOZ = 25; TElOV ,= 50.

3·234

8282/8283

A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT

24

-v,

5_

TEST POINTS _ ,

04S~

sV~

AC TESTING. INPUTS ARE DRIVEN AT24V FOR A LOGIC "1" ANDO.45V FOR
A LOGIC "0" TIMING MEASUREMENTS ARE MADE AT 1 5V FOR BOTH A
LOGIC "1" AND "0" INPUT RISE AND FALL TIMES ARE MEASURED FROM

o BV TO 2 OV AND ARE DRIVEN AT 5ns ± 2ns

OUTPUT TEST LOAD CIRCUITS

1.5V

-

1.5V

332

r

OUT 0 - - -

300pF"

3·STATE TO VOL

2.14V

1802

OUTC>--

I300PF"

3·STATE TO VOH

"200 pF for plastic 8282/8283.

3-235

52.72

r

OUT 0 - -

:iOOpF"

SWITCHING

intJ

828218283

WAVEFORMS

\V

\V
/1\

INPUTS

/1\

!---TIVSL- !--TSLIX.

STB

V

--.J

\
T S H S L - \.

,

V

-

\

---- ---t=

,

/

!-TIVOV4

1\

VOH-.W

OUTPUTS

\V
,,<1\.

1>------VOL +.W

SEE NOTE 1
!--TSHOV-

NOTE: 1. OUTPUT MAY BE MOMENTARILY INVALID FOLLOWING THE HIGH GOING STB TRANSITION.
2. ALL TIMING MEASUREMENTS ARE MADE AT 1.SV UNLESS OTHERWISE NOTED.

50

50

40

40

~

~

z 30

z

s

i

III
D

20

10

pFLOAD

pF LOAD

Output Dele, va. Capacitance
3-236

8284A/8284A·1
CLOCK GENERATOR AND DRIVER FOR
iAPX 86, 88 PROCESSORS
• Generates the System Clock for the
iAPX 86, 88 Processors:
5 MHz, 8 MHz with 8284A
10 MHz with 8284A-1
• Uses a Crystal or a TT.L Signal for
Frequency Source
•

• Single +5V Power Supply
• Generates System Reset Output from
Schmitt Trigger Input
• Capable of Clock Synchronization with
Other 8284As

Provides Local READY and MULTIBUS®
READY Synchronization

•

• 18·Pin Package

D

0

RES

Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range

RESET
X1
XTAl
OSCillATOR
X2

OSC

Vee
Fie
~3

PClK

X2

EFI

RDY1

CSYNC

READY

ASYNC
EFI
Fie

RDY1

OSC
ClK

AEN1
RESET
RDY2
AEN2

CKt
Q

D

READY

FF1
ASYNC

~284A/8284A-1

Block Diagram

3-237

8284A/8284A-1 Pin
Configuration

8284A/8284A-1

Table 1. Pin Description
Symbol Type

Name and Function

Name and Function

Symbol Type

AEN1,
AEN2

I

Address Enable: AEN is an active LOW
signal. AEN serves to qualify its respecti~e
Bus Ready Signal (RDYI or RDY2). AENI
validates RDYI while AEN2 validates RDY2.
Two AEN signal inputs are useful in system
configurations which permit the processor to
access two Multi-Master System Busses. In
non Multi-Master configurations the AEN
signal inputs are tied true (LOW).

CLK

0

Processor Clock: CLK is the clock output
used by the processor and all devices which
directly connect to the processor's local bus
(i.e., the bipolar support chips and other MOS
devices). ClK has an output frequency which
is Y3 of the crystal or EFI input frequency and a
Y3 duty cycle. An output HIGH of 4.5 volts
(Vcc= 5V) is provided on this pin to drive MOS
devices.

RDY1,
RDY2

I

Bus Ready: (Transfer Complete). ROY is an
active HIGH signal which is an indication from
a device located on the system data bus that
data has been received, or is available. RDYI
is qualified by AENI while RDY2 is qualified
by AEN2.

PCLK

0

Peripheral Clock: PCLK is a TTL level peripheral clock signal whose output frequency
is Y2 that of CLK and has a 50% duty cycle.

OSC

0

Oscillator Output: OSC is the TTL level output of the internal oscillator circuitry. Its frequency is equal to that of the crystal.

RES

I

Reset In: RES is an active LOW signal which
is used to generate RESET. The 8284A
provides a Schmitt trigger input so that an RC
connection can be used to establish the
power-up reset of proper duration.

RESET

0

Reset: RESET is an active HIGH signal which
is used to resetthe 8086 family processors. Its
timing characteristics are determined by
RES.

CSYNC

I

Clock Synchronization: CSYNC is an active
HIGH signal which allows multiple 8284As to
be synchronized to provide clocks that are in
phase. When CSYNC is HIGH the internal
counters are reset. When CSYNC goes LOW
the internal counters are allowed to resume
counting. CSYNC needs to be externally synchronized to EFI. When using the internal oscillator CSYNC should be hardwired to
ground.

ASYNC

READY

I

0

Ready Synchronization Select: ASYNC is an
input which defines the synchronization
mode of the READY logic. When ASYNC is
low, two stages of READY synchronization
are provided. When ASYNC is left open
(internal pull-up resistor is provided) or HIGH
a single stage of READY synchronization is
provided.
Ready: READY is an active HIGH signal
which is the synchronized ROY signal input.
READY is cleared after the guaranteed hold
time to the processor has been met.

Xl,X2

I

Crystal In: Xl and X2 are the pins to which a
crystal is attached. The crystal frequency is 3
times the desired processor clock frequency.

F/C

I

Frequency/Crystal Select: F/C is a strapping
option. When strapped LOW, FIG permits the
processor's clock to be generated by the crystal. When F/Gis strapped HIGH, CLK is generated from the EFI input.

EFI

I

External Frequency: When F/C is strapped
HIGH, CLK is generated from the input frequency appearing on this pin. The input
signal is a square wave 3 times the frequency
of the desired CLK output.

FUNCTIONAL DESCRIPTION

General
The 8284A is a single chip clock generator/driver for the
iAPX 86, 88 processors. The chip contains a crystal-controlled oscillator, a divide-by-three counter, complete MULTI BUS
"Ready" synchronization and reset logic. Refer to Figure 1
for Block Diagram and Figure 2 for Pin Configuration.

Oscillator
The oscillator circuit of the 8284A is designed primarily
for use with an external series resonant, fundamental
mode, crystal from which the basic operating frequency
is derived.
The crystal frequency should be selected at three times
the required CPU clock. XI and X2 are the two crystal
input crystal connections. For the most stable operation

GND

Ground,

Vee

Power: +5V supply.

. of the oscillator (OSC) output circuit, two series resistors
(Rl = R2 = 510 fl) as shown in the waveform figures are
recommended. The output of the oscillator is buffered and
brought out on OSC so that other system timing signals
can be derived from this stable, crystal-controlled source.
For systems which have a Vee ramp time'" 1Vlms and/or
have inherent board capacitance between XI or X2, exceeding 10 pF (not including 8284A pin capacitance), the
two 510fl resistors should be used. This circuit provides
optimum stability for the OSCIllator in such extreme conditions. It is advisable to limit stray capacitances to less than
10 pF on XI and X2 to minimize deviation from operating
at the fundamental frequency.
If EFI is used and no crystal is connected, it is recommended
that X1 or X2 should be tied to Vcc through a 510n resistor to
prevent the oscillator from free running which might produce
HF noise and additional Icc current.
3-238

8284A/8284A-1

Master system is not being used the A8il pin should be
tied lOW.

Clock Generator
The clock generator consists of a synchronous divideby-three counter with a special clear input that inhibits
the counting. This clear input (CSYNC) allows the output clock to be synchronized with an external event
(such as another 8284A clock). It is necessary to synchronize the CSYNC input to the EFI clock external to
the 8284A. This is accomplished with two Schottky' flipflops. The counter output is a 33% duty cycle clock at
one-third the input frequency.

Synchronization is required for all asynchronous activegoing edges of either ROY input to guarantee that the
ROY setup and hold times are met. Inactive-going edges
of ROY in normally ready systems do not require synchronization but must satisfy ROY setup and hold as a
matter of proper system design.
The ASYNC input defines two modes of READY synchronization operation.

The FIG input is a strapping pin that selects either the
crystal oscillator or the EFI input as the clock for the +3
counter. If the EFI input is selected as the clock source,
the oscillator section can be used independently for
another clock source. Output is taken from OSC.

When ASYNC is lOW, two stages of synchronization
are provided for active READY input signals. Positivegoing asynchronous READY inputs will first be synchronized to flip-flop one at the rising edge of ClK
and then synchronized to flip-flop two at the next falling
edge of ClK, after which time the READY output will go
active (HIGH). Negative-going asynchronous READY inputs will be synchronized directly to flip-flop two at the
falling edge of CLK, after which time the READY output
will go i nactive. This mode of operation is intended for use
by asynchronous (normally not ready) devices in the system which cannot be guaranteed by design to meet the
required ROY setup timing, TR1VCL , on each bus cycle.

Clock Outputs
The ClK output is a 33% duty cycle MOS cloQk driver
designedto drive the iAPX 86, 88 processors directly.
PClK is a TTL level peripheral clock Signal whose output frequency is V2 that of ClK. PClK has a 50% duty
cycle.
.

Reset Logic
The reset logic provides a Schmitt trigger input (RES)
and a synchronizing flip-flop to generate the reset
timing. The reset signal is synchronized to the falling
edge of ClK. A simple RC network can be used to
provide power-on reset by utilizing this function of the
8284A ..

READY Synchronization

When ASYNC is high or left open, the first READY flipflop is bypassed in the READY synchronization logic.
READY inputs are synchronized by flip-flop two on the
falling edge of ClK before they are presented to the
processor. This mode is available for synchronous
devices that can be guaranteed to meet the required
ROY setup time.

Two READY inputs (RDY1, RDY2) are provided to accommodate two Multi-Master system busses. Each input
has a qualifier (AEN1 and AEJii2, respectively). The Am
signals validate their respective ROY signals. If a Multi-

ASYNC can be changed on every bus cycle to select the
appropriate mode of synchronization for each device in
the system.

CLOCK
SYNCHRONIZE

>--+----H 0

EFI

>-.....-f.>O-~>

Q

o
Q

t
.......

_--'
(TO OTHER 8284As)

Figure 3. CSYNC Synchronization

3-239

8284A/8284A-1

-NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ................. O·C to 70·C
Storage Temperature .............. -65·C to +150·C
All Output and Supply Voltages ......... -0.5V to + 7V
All Input Voltages ................... -1.0V to +5.5V
Power Dissipation .......................... 1 Watt

D.C. CHARACTERISTICS (TA=O·C to 70·C, Vcc=5V± 10%)
Symbol

Parameter

Min.

Max.

. Units

Test Conditions

IF

Forward Input Current (ASYNC)
Other Inputs

-1.3
-0.5

mA
mA

VF=0.45V
VF= 0.45V

IA

Reverse Input Current (ASYNC)
Other Inputs

50
50

,..A
,..A

VA= Vcc
VA=5.25V
Ic= -5mA

Vc

Input Forward Clamp Voltage

-1.0

V

Icc

Power Supply Current

162

mA

VIL

Input lOW Voltage

0.8

V

V IH

Input HIGH Voltage

2.0

V

VIHR

Reset Input HIGH Voltage

2.6

V

VOL

Output lOW Voltage

VOH

Output HIGH Voltage ClK
Other Outputs

VIHA - VILA

RES Input Hysteresis

V

5mA

4
2.4

V
V

-1mA
-1mA

0.25

V

0.45

A.C_ CHARACTERISTICS (TA= O·C to 70·C, Vcc= 5V ± 10%)
TIMING REQUIREMENTS
Symbol

Parameter

Min.

Max.

Units

Test Conditions

tEHEL

External Frequency HIGH Time

13

ns

tELEH

External Frequency lOW Time

13

ns

10%-10% VIN

tELEL

EFI Period

33

ns

(Note 1)

90%-90% VIN

XTAl Frequency

12

t A1VCL

RDY1, RDY2 Active Setup to ClK

35

ns

ASYNC= HIGH

t A1 VCH

RDY1, RDY2 Active Setup to ClK

35

ns

ASYNC=lOW

tA1vCL

RDY1, RDY21nactive Setup to ClK

35

ns

tCLA1X

RDY1, RDY2 Hold to ClK

0

ns

tAYVCL

ASYNC Setup to ClK

50

ns

tCLAYX

ASYNC Hold to ClK

0

ns

tA1VA1V

AEN1, AEN2 Setup to RDY1, RDY2

15

ns

tCLA1X

AEN1, AEN2 Hold to ClK

0

ns

tYHEH

CSYNC Setup to EFI

20

ns

tEHYL

CSYNC Hold to EFI

10

ns

t YHYL

CSYNCWidth

2·tELEL

ns

tl1HCL

RES Setup to ClK
RES Hold toClK

65

ns

(Note 1)

20

ns

(Note 1)

tCLl1H

,

3-240

25

MHz

.-

.

8284A/8284A·1

A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Min. 8284A
125

Parameter

Symbol

Min. 8284A-1

Max.

Units

100

ns

(V3 tcLcd + 2

39

ns

(% t cLc d-15

53

ns

tpHPL

PClK HIGH Time

tCLCL -20

tCLCL -20

ns

tPLPH

PClK lOW Time

tCLCL-20

!eLCL -20

ns

tRYlCL

Ready InactIve to ClK (See Note 3)

-6

tRYHCH

Ready Active to ClK (See Note 2)

(2h t cLc d-15

tCUl

ClK to Reset Delay

40

ns

tCLPH

ClK to PClK HIGH DELAY

22

ns

tCLPL

ClK to PClK lOW Delay

22

ns

tOLCH

OSC to ClK HIGH Delay

-5

-5

22

ns

2

2

tCLCl

ClK Cycle Period

tCHCL

ClK HIGH Time

t CLCH

ClK lOW Time

tCH1CH2

ClK Rise or Fall Time

10

Test Conditions

ns

1.0V to 3.5V

tCl2CL1

-8

ns

53

ns

tOlCL

OSC to ClK lOW Delay

35

ns

tOLOH

Output Rise Time (except ClK)

20

ns

From 0.6V to 2.0V

tOHOl

Output Fall Time (except ClK)

12

ns

From 2.0V to 0.6V

NOTES:
1. Setup and hold necessary only to guarantee recognition at next clock.
2. Applies only to T3 and TW states.
3. Applies only to T2 states.

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

INPUT/OUTPUT

-

VL = 2.0BV
RL

DEVICE
UNDER
TEST

r-------

ICC
-=

A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC "1" AND 045V
FOR A LOGIC "0." TIMING MEASUREMENTS ARE MADE AT 1 5V FOR
BOTH A LOGIC "1" AND "0" INPUT RISE AND FALL TIMES (MEASURED
BETWEEN 0
AND 2 OV) ARE 5.± 2 NS

CL ~ 100pF FOR ClK

av

CL ~ 30pF FOR READY

3-241

=

3250

, 8284A/8284A-1

WAVEFORMS
CLOCKS AND RESET SIGNALS

NAME
EFI
OSC

C~K

0

PCLK

0

CSYNC

I

RESET

0

NOTE:

A~~

______~/~--------------~~~t=
TIMING MEASUREMENTS ARE MADE AT 1.5

VO~TS,

UNLESS OTHERWISE NOTED.

READY SIGNAI.S (FOR ASYNCHRONOUS DEVICES)

C~K

RDY1,2

READY
tRYLCL

tRYHCH

3-242

intJ

8284A/8284A-1

WAVEFORMS (Continued)
READY SIGNALS (FOR SYNCHRONOUS DEVICES)
elK

RDY1,2

READY
tRVLCL

IRYHCH

Xl
24MHZD
T

R2

R,

-

I

LOAD
(SEE NOTE 1)

I

X2
FIC

1

CSYNC

J.

-

I

CLK

R

Clock High and Low Time (Using X1, X2)

I

PULSE
GENERATOR

I
J

EFI

CLK

I
I

LOAD
(SEE NOTE 1)

Vee

L

.,r-

FIC

CSYNC

Clock High and Low Time (Using EFI)

3-243

I

inter

8284A/8284A-1

VCC

nm

CLK

X1
24MHz CJ

READY
X2

R,

R2

RDY2
OSC
FIe
AEN2
CSYNC
R, = R. = 510(1.

Ready to Clock (Using X1, X2)

h r - - - - I EFI

CLK 1----1

F/~

nm
t---"'1 RDY2
1IDl2
CSYNC READY'I------1

NOTES:
1 Ct.-100pF
2. CL=30pF

Ready to Clock (Using EFI)

3-244

8286/8287
OCTAL BUS TRANSCEIVER

•

Data Bus Buffer Driver for iAPX
86,88,186,188, MCS·80™, MCS·8S™,
and MCS·48™ Families

•

High Output Drive Capability for
Driving System Data Bus

•

Fully Parallel 8·Bit Transceivers

•

3·State Outputs

•

20·Pin Package with 0.3" Center

•

No Output Low Noise when Entering
or Leaving High Impedance State

•

Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range

The 8286 and 8287 are 8-bit bipolar transceivers with 3-state outputs. The 8287 inverts the Input data at its outputs
while the 8286 does not. Thus, a wide variety of applications for buffering in microcomputer systems can be met.

AO

Vee

AO

Al

BO

Al

A2

Vee
So

Bl

A2

51

B2

A3

B3

A4

ii2
83

B4
BS
B6
B7

GND

Figure 1. Logic Diagrams

T

OE
GND

Figure 2. Pin Configurations

3-245

B6
B7
T

8286/8287

Table 1. Pin Description
Type

Name and Function

T

I

Transmit: T is an input control signal used to control the direction of the transceivers. When HIGH,
it configures the transceiver's Bo-B7 as outputs with Ao-A7 as inputs. T LOW configures Ao-A7 as
the outputs with Bo-B7 serving as the inputs.

DE

I

Output Enable: OE is an input control signal used to enable the appropriate output driver (as
selected by T) onto its respective bus. This signal is active LOW.

Ao-A7

I/O

Local Bus Data Pins: These pins serve to either present data to or accept data from the processor's
local bus depending upon the state of the T pin.

Bo-B7(8286)
60-87(8287)

1/0

System Bus Data Pins: These pins serve to either present deta to or accept data from the system
bus depending upon the state of the T pin.

Symbol

FUNCTIONAL DESCRIPTION
The 8286 and 8287 transceivers are 8-bit transceivers with
high impedance outputs. With T active HIGH and OE active LOW, data at the Ao-A7 pins is driven onto the Bo-B7
pins. With T inactive LOW and OE active LOW, data at the

Bo-B7 pins is driven onto the Ao-A7 pins. No output low
glitching will occur whenever the transceivers are entering or leaving the high impedance state.

A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT

24 J S _ T E S T POINTS
0.45

-'x=

A C TESTING INPUTS ARE DRIVEN AT2 4V FORA LOGIC "1" ANOO 45V
FOR A LOGIC "0" THE CLOCK IS DRIVEN AT 4 3V and 025V TIMING
MEASUREMENTS ARE MADE AT 1 5V FOR BOTH A LOGIC "1" AND "0"
INPUT RISE AND FALL TIMES ARE 5 ± 2 NS , MEASURED BETWEEN 0 BV

AND 2 OV

3-246

8286/8287

TEST LOAD CIRCUITS

2.14V

,",~~N
I

3OOP

F'

SWITCHING

B OUTPUT

2.28V

'"'~""

rl00PF

SWITCHING

A OUTPUT

·200 pF for plastIc 8286/8287

3-247

inter

8286/8281

ABSOLUTE MAXIMUM RATINGS·

'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Temperature Under Bias ................. O·C to 70·C
Storage Temperature ............. -65·C to + 150·C
All Output and Supply Voltages ........ - 0.5V to + 7V
All Input Voltages ....... : .......... - 1.0V to + 5.5V
Power Dissipation .......................... 1 Walt

D.C. CHARACTERISTICS

(Vee = +5V ± 10%, TA = O°C to 70°C)
Max

Units

-1

V

Power Supply Current-8287
-8286

130
160

mA
rnA

IF

Forward Input Current

-0.2

mA

V F =0.45V

IR

Reverse Input Current

50

,..A

V R =5.25V

VOL

Output Low Voltage

.45
.45

V
V

IOl = 32 mA
IOl = 16 rnA

VOH

Outpui High Voltage -B Outputs
-A Outputs

V
V

IOH=-5 rnA
IOH=-1 mA

IOFF
IOFF

Output Off Current
Output Off Current

V,l

Input Low Voltage

V,H

Input High Voltage

C 'N

Input Capacitance

Symbol

Parameter

Min

Ve

Input Clamp Voltage

Icc

NOTE:
1. B Outputs-IOL

=

32 mA, IOH

=

-5 mA,

A.C. CHARACTERISTICS

-B Outputs
-A Outputs
2.4
2.4

Test Conditions
le= -5 mA

V OFF =0.45V
V OFF =5.25V

IF
Itl
-A Side
-B Side

0.8
0.9
2.0
12

Ct.

=

300 pP: A Outputs-IOl

=

V
V

Vee= 5.0V, See Note 1
Vee= 5.0V, See Note 1

V

Vee= 5.0V, See Note 1

pF

F= 1 MHz
V BIAS =2.5V, Vee=5V
TA= 25·C

16 mA, 10H = -1 mA, Cl

=

100 pF.

(Vee = +5V ±10%, TA = O°C to 70°C) (See Note 2)

Loading: B Outputs-Iol = 32 mA, IOH = -5 mA, Cl = 300 pP
A OutputS-IOl = 16 rnA, IOH = -1 rnA, Cl = 100 pF
Symbol
TIVOV

Parameter
Input to Output Delay
Inverting
Non-Inverting

Min

Max

Units

5
5

22
30

ns
ns

Test Conditions
(See Note 1)

TEHTV

TransmitlReceive Hold Time

TTVEl

Transmit/Receive Setup

TEHOZ

Output Disable Time

5

18

ns

TELOV

Output Enable Time

10

30

ns

TOLOH

Input, Output Rise Time

20

ns

From 0.8 V to 2.0V

TOHOL

Input, Output Fall Time

12

ns

From 2.0V to 8.0V

ns

5

10

ns

Cl - 200 pF for plastic 8286/8287
NOTE:
1. See waveforms and test load circuit on following page.
2. For Extended Temperature EXPRESS the Preliminary Maximum Values are TIVOV = 25 vs 22, 35 vs 30;
TEHOZ = 25; TElOV = 50.
3-248

inter

8286/8287

WAVEFORMS

\/

INPUTS

./ \.

V

\

/
I-TIVOV-

-

\V

OUTPUTS

TEH02 :"":.
VOH -

TELOV~

1V

~:------

JI\.

VOL

+

1V

:\

C=

----:----]----t-- TIVEL

_TEHTV

NOTE:
1. All timing measurements are made at1.5V unless otherwise noted.

50

50
8287

40

.,&l
z

;w
Q

10

200

400

200
pf LOAD

400

600
pF LOAD

Output Delay versus Capacitance
3-249

600

1000

8288
BUS CONTROLLER
FOR iAPX 86, 88 PROCESSORS

• Bipolar Drive Capability
• Provides Advanced Commands
Provides Wide Flexibility in System
• Configurations
with 10 MHz iAPX 86 and
• 8Compatible
MHz iAPX 186 based systems.

•

3·State Command Output Drivers

• Conflgurable for U~e with an I/O Bus

••

Facilitates Interface to One or Two
Multl·Master Bus$es

in EXPRESS
• Available
- Standard Temperature Range
- Extended Temperature Range

The Intel® 8288 Bus Controller is a 2o-pin bipolar component for use with medium-to-Iarge iAPX 86, 88 processing
systems. The bus controller provides command and control timing generation as well as bipolar bus drive capability while
optimizing system performance.
A strapping option on the bus controller configures it for use with a multi-master system bus and separate 1/0 bus.

8086
STATUS

{So~-

_

MRDC
STATUS
DECODER

S2-'

~.

COM·
MAND
SIGNAL
GENER·
ATOR

108

MWTC
AMWC
IORC

lowe,

MUlTIBUS™
COMMAND
SIGNALS

AIOWC

{CLKAEN-

CEN-

CONTROL
LOGIC

CONTROL
SIGNAL
GENER·
ATOR

108-

+5V

DT/R
}
DEN
MCE/PDEN
ALE

S1
DTiR

INTA

CONTROL
INPUT

ClK

ADDRESS LATCH. DATA
TRANSCEIVER, AND
INTERRUPT CONTROL
SIGNALS

vcc
so
S2
MCE/PDEN

ALE

DEN

AEN

CEN

MRDC

INTA

AMWC

10RC

MWTC
GND

AIOWC
IOWC

GND

Figure 2_
Pin Configuration

Figure 1. Block Diagram

3-250

intJ

8288

Table 1. Pin Description
Symbol

~pe

GND
So, S" S.

~pe

Status Input Pins: These pins are the
status input pins from the 8086, 8068 or
8089 processors. The 8288 decodes these
inputs to generate command and control
signals at the appropriate time. When
these pins are not in use (passive) they are
all HIGH. (See chart under Command and
Control Logic.)

I

Clock: This is a clock Signal from the
8284 clock generator and serves to establish when command and control signals
are generated.

ALE

a

Address Latch Enable: This signal
serves to strobe an address into the
address latches. This signal is active HIGH
and latching occurs on the falling (HIGH
to LOW) transition. ALE is intended for
use with transparent D type latches.

DEN

a

Data Enable: This signal serves to enable data transceivers onto either the
local or system data bus. This signal is
active HIGH.

DT/R

a

Data Transmit/Receive: This signal establishes the direction of data flow
through the transceivers. A HIGH on this
line indicates Transmit (write to I/O or
memory) and a LOW indicates Receive
(Read).

I

Addres. Enable: AEN enables command
outputs of the 8288 Bus Controller at least
115 ns after it becomes active (LOW). AEN
going inactive immediately 3-states the
command output drivers. AEN does not
affect the I/O command lines If the 8288 is
in the I/O Bus mode (lOB tied HIGH).

CEN

I

Command Enable: When this signal is
LaWall 8288 command outputs and the
DEN and PDEN control outputs are forced
to their inactive state. When this signal is
HIGH, these same outputs are enabled.

lOB

I

Input/Output Bus Mode: When the lOB is
strapped HIGH the 8288 functions in the
I/O Bus mode. When it is strapped LOW,
the 8288 functions in the System Bus
mode. (See sections on I/O Bus and System Bus modes).

3-251

Name and Function

AIOWC

a

Advanced I/O Write Command: The
AIOWC issues an I/O Write Command
earlier in the machine cycle to give I/O
devices an early indication of a write instruction. Its timing is the same as a read
command signal. AIOWC is active Law.

10WC

a

I/O Wrtte Command: This command line
instructs an I/O device to read the data on
the data bus. This Signal is active LOW.

10RC

a

I/O Read Command: This command line
instructs an I/O device to drive its data
onto the data bus. This Signal is active
LOW.

AMWC

a

Advanced Memory Write Command: The AMWC issues a memory write
command earlier in the machine cycle to
give memory devices an early indication
of a write instruction. Its timing is the
same as a read command signal. AMWC is
active LOW.

MWTC

a

Memory Wrlle Command: This command line instructs the memory to record
the data· present on the data bus. This
signal is active LOW.

MRDC

a

Memory Read Command: This command line instructs the memory to drive
its data onto the data bus. This signal is
active Law.

INTA

a

Interrupt Acknowledge: This command
line tells an interrupting device that its
interrupt has been acknowledged and
that it should drive vectoring Information
onto the data bus. ThiS Signal is active
Law.

MCE/PDEN

a

This is a dual function pin.
MCE (lOB is lied LOW): Master Cascade
Enable occurs during an interrupt sequence and serves to read a Cascade
Address from a master PIC (Priority Interrupt Controller) onto the data bus. The
MCE signal is active HIGH.
PDEN (lOB Is lied HIGH): Peripheral
Data Enable enables the data bus transceiver for the I/O bus that DEN performs
for the system bus. PDEN is active Law.

Ground.
I

CLK

AEN

Symbol

Name and Function
Power: +5V supply.

Vcc

inter

8288

FUNCTIONAL DESCRIPTIOH
Co~mand

and Control Logic

The command logic decQdes the three 8086. 8088 or 8089
CPU status lines
Sl. 82) to determine what command
Is to tHllssued.
This chart shows the meaning of each status "word".

(so.

52 S; SO

c

0
0
0
0

0
0
1
1

0

1
-1
1
1

0
0

0

1
1

0

Procenor Stille

0 InterruptAcknowledae
1
1
1
1

Read 1/0 Port
Wrlle 110 Port
Hall
Code Access
Read Memorv
WrrteMemory
Passive

8288 Command
INTA
10RC
. 10WC,AIOWC
None

MRDc

MRDC -

MWfC,AMWC
None

The command Is Issued in one of two ways dependent
on the mode of the 8288 Bus Controller.
1/0 BUll Mode - The 8288 Is in the 110 Bus mode if the
lOB pin is strapped HIGH. In the 110 Bus mode ali 110
command lines (I0RC, lOWe, AIOWe. iNTA) are always
enabled (i.e., not dependent on ~). When an 110 com·
Il)and is initiated by the processor, the 8288 immediately
activates the command lines using Pi'5E'N and DTIR to
control the 110 bus transceiver. The 110 command lines
should not be used to control the system bus in this
configuration because no arbitration IS present. ThiS
mode allows one 8288 Bus Controller to handle two ex·
ternal busses. No waiting is involved when the CPU
wants to gain access to the 110 bus. Normal memory ac·
cess requires a "Bus Ready" signal (AEN LOW) before it
will proceed. It is advantageous to use the lOB mode if
110 or peripherals dedicated to one processor exist in a
multl·processor system.
System Bus Mode - The 8288 is in the System Bus mode
if the lOB pin is strapped LOW. In this mode no command
is Issued until 115 ns after the. AEN Line is activated
(LOW). This mode assumes bus arbitration logic will Inform the bus controller (on the AEiii line) when the bus is
free for use. Both memory and 110 commands wait for bus
arbitration. This mode Is used when only one bus exists.
Here. both 1/0 and memory are shared by more than one
processor.

COMMAND OUTPUTS
The advanced write commands are made available to Initiate write procedures early In the machine cycle. This
signal can be used to prevent the processor from entering an unnecessary walt state.
The command outputs are:

MRi5C -

Memory Read Command
MiiiiTC - Memory Write Command
iORC - 1/0 Read Command
10WC - 1/0 Write Command
AMWC - Advanced Memory Write Command
AIOWC - Advanced 110 Write Command
iN'i'A - Interrupt Acknowledge

•

INTA (Interrupt Acknowledge) acts as an 1/0 read during
an Interrupt cycle. Its purpose Is to Inform an Interrupting device that Its Interrupt is being acknowledged
·and that it should place vectoring informatlon'onto the
data bus.

CONTROL OUTPUTS
The control outputs of the 8288 are Data Enable (DEN).
Data Transmit/Receive (DT/A) and Master Cascade
EnablelPeripheral Data Enable (MCElPi'5E'N). The DEN
signal determines when the external bus should be
enabled ,onto the local bus and the DT/R determines the
direction of data transfer. These two signals usually go
to the chip select and directlCOMMAND/CONTROL

..IClK

...

flI

.....
CD

I\)

en

CD
CD

-"

UJ
'<
IIJ

(,)
I

I\)

0)
-.,j

~:!!
IIJCC
_·c

RQ/GTl

ARDY
SRDY

ClK
RESET
READY
82285

Vee

ClK

74lS
373
ADDRESS

II

::J ...
CC"
-CD
::T.

"...
CD

I\)

CD
CD

S"
CD

0
CD
CD

~c~
RESET
READY

~ElP

9°'
1\

DIR
74LS
245 I

I(

CO
N
CO
CO

) DATA

II:

0

a.

"

nARD:_p~~/MX

~
<"@J

2&
IiiiiI

F
=::0

~

TO SERIAL
INTERFACE

c:::J

231051-8

~

~

~

inter

82188

ABSOLUTE MAXIMUM RATINGS *
Temperature under bias

O"Cto 70°C

Storage temperature

- 65°C to 150°C
-1.0V to 7.0V

Voltage on any pin with
respect to GND
Power Dissipation

0.7 Watts

"NOTICE: Stresses above those listed under ABSOlUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC CHARACTE·RISTICS
(Vee

=

5V ± 10%, TA

Symbol

=

O°C to 70°C)

Parameter

Min

Max

Units

TestCond.

VIL

Input low Voltage

-0.5

+0.8

volts

VIH

Input High Voltage

2.0

Vee + 0.5

volts

VOL

Output Low Voltage

0.45

volts

VOH

Output High Voltage

Icc

Power Supply Current

100

mA

III

Input Leakage Current

±10

p.A

OV.!I.S priority (BPRN true) then

seizes the bus and pulls BUSY low to keep other arbiters
off of the bu~. See waveform timing diagram, Figure 5.
Note that all multl·master system bus transactions are
synchronized to the bus clock (BClK). This allows the
parallel priority resolving circuitry or any other priority
resolving scheme employed to settle.

74148
PRIORITY
ENCODER

74138
3TOB
DECODER

Figure 4. Parallel Priority Resolving Technique

I
2
3

HIGHER PRIORITY BUS ARBITER REQUESTS THE MULTI·MASTER SYSTEM BUS.
ATTAINS PRIORITY.
LOWER PRIORITY BUS ARBITER RELEASES BUSY.

4

HIGHER PRIORITY BUS ARBITER THEN ACQUIRES THE BUS AND PULLS BUSY DOWN.

Figure 5. Higher Priority Arbiter obtaining the Bus from a Lower Priority Arbiter

3-277

inter

8289/8289-1

SERIAL PRIORITY RESOLVING
The serial priority resolving technique eliminates the
need for the priority encoder·decoder arrangement by
daisy·chaining the bus arbiters together, connecting the
higher priority bus arbiter's BPRO (Bus Priority Out) out·
put to the BPRN of the next lower priority. See Figure 6.

THE NUMBER OF ARBITERS THAT MAY BE DAISY-CHAINED TOGETHER IN THE
SERIAL PRIORITY RESOLVING SCHEME IS A FUNCTION OF BCLK AND THE PROPA·
GATION DELAY FROM ARBITER TO ARBITER. NORMALLY, AT 10 MHz ONLY 3 ARBI·
TER MAY BE DAISY-CHAINED

Figure 6. Serial Priority Resolving

ROTATING PRIORITY RESOLVING
The rotating priority resolving technique is similar to
that of the parallel priority resolving technique except
that priority is dynamically re·assigned. The priority en·
coder Is replaced by a more complex circuit which roo
tates priority between requesting arbiters thus allowing
each arbiter an equal chance to use the multl·master
system bus, over time.

Which Priority Resolving Technique To
Use
There are advantages and disadvantages for each of the
techniques described above. The rotating priority
resolving techn,ique requires substantial external logic
to implement while the serial technique uses no exter·
nallogic but can accommodate only a limited number of
bus arbiters before the daisy·chain propagation delay
exceeds the multi·master's system bus clock (BCLK).
The 'parallel priority resolving technique is in general a
good compromise between the other two techniques. It
allows for many arbiters to be present on the bus while
not requiring too much logic to Implement.

8289 MODES OF OPERATION
There are two types of processors in the iAPX 86 family. An
Input/Output processor (the 8089 lOP) and the iAPX 86/10,
88/10 CPUs. Consequently, there are two ba,sic operating
modes in the 8289 bus arbiter. One, the lOB (I/O Peripheral
Bus) mode, permits the processor access to both an I/O
Peripheral Bus and a multi-master system bus. The sec·
ond, the RESB (Resident Bus mode), permits the processor to communicate over both a Resident Bus and a
multi-master system bus. An I/O Peripheral Bus is a bus
where all devices on that bus, including memory, are
treated as I/O devices and are addressed by I/O commands. All memory commands are directed to another
bus, the multi·master system bus. A Resident Bus can
issue both memory and I/O commands, but it is a distinct
and separate bus from the multi·master system bus. The
distinction is that the Resident Bus has only one master,
providing full availability and being dedicated to that one
master.
The lOB strapping option configures the 8289 Bus Ar·
biter into the lOB mode and the strapping option RESB
configures it into the RESB mode. It might be noted at
this point that if both strapping options are strapped
false, the arbiter interfaces the processor to a multi·
master system bus only (see Figure 7). With both op·
tions strapped true, the arbiter interfaces the processor
to a multi·master system bus, a Resident Bus, and an I/O
Bus.
In the lOB mode, the processor communicates and con·
trois a host of peripherals over the Peripheral Bus. When
the I/O Processor needs to communicate with system
memory, it does so over the system memory bus. Figure
8 shows a possible I/O Processor system configuration.
The iAPX 86 and iAPX 88 processors can communicate
with a Resident Bus and a multi-master system bus. Two
bus controllers and only one Bus Arbiter would be needed
in such a configuration as shown in Figure 9. In such a
system configuration the processor would have access to
memory and peripherals of both busses. Memory mapping techniques are applied to select which bus is to be
accessed. The SYSB/RESB input on the arbiter serves to
instruct the arbiter as to whether or not the system bus is
to be accessed. The signal connected to SYSB/RESB also
enables or disables commands from one of the bus
controllers.
A summary of the modes that the 8289 has, along with
its response to its status. lines inputs, is summarized in
Table 2.

*In some system configurations It is possible for a non-1I0 Processor to
have access to more than one Multi-Master System Bus, see 8289
Application Note.

3-278

8289/8289-1

Table 2. Summary of 8289 Modes, Requesting and Relinquishing the Multi-Master System Bus
Single
Status Lines From

8086 or 8088 or 8089

1/0

COMMANDS
HALT

lOB Mode
Only

52

51

So

0
0
0

0
0
1

0
1
0

x
x
x

0

1

1

x

1

0
1
0
1

MEM
COMMANDS

1

1

0
0
1

IDLE

1

1

RESB (Mode) Only
lOB = High RESB = High

lOB Mode RESB Mode
lOB = Low RESB = High

lOB = Low SYSB/RESB = High SYSB/RESB = Low

x

x

x

SYSB/RESB = High SYSB/REsB = Low

x
x
x

x
x
x

x
x

x
x
x
x

x

x

x

x

X

x

Multi·Master System Bus

Pin
Strapping

Requested··

Single Bus
Multi·Master Mode

10B= High
RESB= Low

Whenever the processor's
status lines go active

RESB Mode Only

10B= High
RESB= High

SYSB/J:fESij = High.
ACTIVE STATUS

lOB Mode Only

10B=Low
RESB= Low

Memory Commands

lOB Mode RESB Mode

10B=Low
RESB= High

(Memory Command),.
(SYSB/RESB= High)

SurrenderedHLT + TI- CBRQ+ HPBROt
(SYSB/~ = Low + TI) •

CBRQ+ HLT + HPBRQ

(1/0 Status + TI) • CBRQ +
HLT+ HPBRQ

((1/0 Status Commands) +
SYSB/~ = LOW)) • CBRO
+ HPBRQt + HLT

NOTES:
'LOCK prevents surrender of Bus to any other arbiter, CRQLCK prevents surrender of Bus to any lower priority arbiter.
""Except for HALT and Passive or IDLE Status.
t HPBRQ, Higher priority Bus request or iiPRiii = 1.
1. lOB Active Low.
2. RESB Active High.
3. + is read as "OR" and· as "AND."
4. TI= Processor Idle Status 52, 51,50= 111
5. HLT= Processor Halt Status 52,81, SO=OII

3-279

x

x
x
x

NOTES:
1. X= Multi-Master System Bus IS allowed to be Surrendered.
2. ,., = Multi-Master System Bus is Requested

Mode

~
lOB = High
RESB = Low

x

8289/8289-1

rO~

.......AENa~
Yah T

CLOCtC

CPu

MULn.IlA8TER

SYSTEM BUS

PROCESSOR
LOCAL BUS

C3

'----'\I

DTIR

TRANSCEIVER

IlItIU81

k~================J MULTI MASTER
SYSTEM

DATA

00

-

Figure 7. Typical Medium Complexity CPU System

XACK!IIO BUSI

.....

>----

CLOCK
RDY1

R D Y 2 i - - - - - - - - - - - - - - - - { X A C K MULTI MASTER SYSTeM 8US

.m

READY
C,"

BUS
ARBITER

K======:)MULTIMASTEA
CONTROL
BUS

REAOY CllC

...,
lOP

10
COMMAND
BUS

¢=

MULTI MASTER

~~~==-==l~~~:~ND
BUS

MULTtMASTER

SYSTEM 8US

10

BUS

-t------«

10

DATA
BUS

===:>

SYSTEM
AODRESS

~"elE

BUS

-~-- ----

ADDRESS

MULTI MASTER

K~============>MULTIMASTER
.US
SYSTEM

DATA

Figure 8. Typical Medium Complexity 108 System
3-280

8289/8289-1

o
AEN2

AEN1I>-------,

-..
ct."""

=£NT B U S - - - - - - - - l ADV2

1-------+--------

XACK MULTI-MASTER SYSTEM 8US

Vee
SVS8IiiRJ

"'====::====l

MULTI MASTER SYSTEM

RESIDENT COMMAND \

BUS

COMMAND BUS
MULTI MASTER

"ISIDENT BUS

SYSTEM 8US

PROM

OR
DECODER

RESIDENT ADDRESS

eus

RESIDENT DATA

ADDR

1----

LATCH

\--------1

828218283
(20R3)

MULTI MASTER SYSTEM
ADDRESS BUS

/'--------J\J

IUS

"BY ADDING ANOTHER 8289 ARBITER AND CONNECTING ITS AEN TO THE 8218

WHOSE

nH IS PRESENTLY GROUNDED, THE PROCESSOR COULD HAYE ACCESS

TO TWO MULTI MASTER BUSES

Figure 9. 8289 Bus Arbiter Shown in System-Resident Bus Configuration

3-281

8289/8289-1

'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias .............•.. O·C to 70·C
Storage Temperature ............. - 65·C to + 150·C
All Output and Supply Voltages ........ - 0.5V to + 7V
All Input Voltages .................. -1.0V to + 5.5V
Power Dissipation •........................ 1.5 Watt

D.C. CHARACTERISTICS

(TA

= O°C to 70°C, Vee 1=

+5V ±10%)
Test Condition

Max.

Units

Ve

Input Clamp Voltage

-1.0

V

IF

Input Forward Current

-0.5

mA

Vee = 5.50V, VF = 0.45V

IR

Reverse Input Leakage Current

60

"A

Vee = 5.50, VR = 5.50

VOL

Output Low Voltage
BUSY,CBRQ
AEN
BPRO,BREQ

0.45
0.45
0.45

V
V
V

IOl=20 mA
IOl= 16 mA
IOl= 10 mA

V

IOH=400 "A

Symbol

Min.

Parameter

Output High Voltage
BUSY,CBRQ

VOH

Open Collector
2.4

All Other Outputs
Power Supply Current

Icc
V1l

Input Low Voltage

165

mA

.8

V

Input High Voltage
Input Capacitance

25

pF

Cln (Others)

Input Capacitance

12

pF

(Vee

=

I

V

2.0

V1H
Cin Status

A.C. CHARACTERISTICS

Vee=4.50V, le= -5 mA

+5V ±10%, TA ,;" O°C to 70°C)

TIMING REQUIREMENTS
Symbol

Parameter

Max.

Unit

8289 Min.

8289·1 Min.

125

100

ns

65

53

ns

35

26

TCLCL

CLK Cycle Period"

TCLCH

CLKLowTIme

TCHCL

CLK High Time

TSVCH

Status Active Setup

65

55

TCLCL-10

ns

TSHCL

Status Inactive Setup

50

45

TCLCL·10

ns

THVCH

Status Active Hold

10

10

ns

THVCL

Status Inactive Hold

10

10

ns

TBYSBL

BUSYj J.-Setup to BCLKJ.-

20

20

ns

TCBSBL

CBROjJ.-Setup to BCLKJ.-

20

20

ns

TBLBL

BCLK Cycle TIme

100

• 100

TBHCL

BLCK High Time

30

30

TCLLL1

LOCK Inactive Hold

10

10

TCLLL2

LOCK Active Setup

40

40

ns

TPNBL

BPRNj J.- to BCLK Setup Time

15

15

ns

TCLSR1

SYSB/RESB Setup

0

0

ns

TCLSR2

SYSB/RESB Hold

20

20

ns

TIVIH

Initialization Pulse Width'

3TBLBL+
3 TCLCL

3TBLBL+
3 TCLCL

ns

3-282

ns

ns
,65[TBLBLJ

ns
ns

Test Condition

inter

8289/8289-1

A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Symbol

Parameter

TBLBRL

BCLK to BREa Delay~ t

Min.

Max.

Unit

35

ns

TBLPOH

BCLK to BPROH (See Note 1)

40

ns

TPNPO

BPRN~ tto BPRO~ tDelay

25

ns

Test Condition

(See Note 1)
TBLBYL

BCLK to BUSY Low

60

ns

TBLBYH

BCLK to BUSY Float (See Note 2)

35

ns

TCLAEH

CLK to AEN High

65

ns

TBLAEL

BCLK to AEN Low

40

ns

TBLCBL

BCLK to CBRa Low

60

ns

TRLCRH

BCLK to CBRa Float (See Note 2)

35

ns

TOLOH

Output Rise Time

20

ns

From 0.8V to 2.0V

TOHOL

Output Fall Time

12

ns

From 2.0V to 0.8V

~ t Denotes that spec applies to both transitions of the signal.

NOTES:
1. BCLK generates the first BPRO wherein subsequent BPRO changes lower in the chain are generated through BPRON.
2. Measured at .5V above GND.

A.C. TESTING LOAD CIRCWT

A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT

2.4 = X S _ T E S T P O I N T S
0.45

-'x:=

DEVICE
UNDER
TEST

ICL~'OOPF
-=-

A.C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC "1" AND a 45V
FOR A LOGIC "0" THE CLOCK IS DRIVEN AT 4 3V and 025V TIMING
MEASUREMENTS ARE MADE AT 1 5V FOA BOTH A LOGIC "1" AND "0"
INPUT RISE AND FALL TIMES (MEASURED BETWEEN 0 BV AND 2 OV) ARE
DRIVEN AT 5 ± 2 NS.

C L = 100 pF
C L INCLUDES JIG CAPACITANCE

~

3-283

intJ

8289/8289·1

WAVEFORMS

WfR
(SEE NOTE 1)

AEN
!SEE NOTE 3)

PROCESSOR eLK RELATED

IUS eLK RELATED

1IJiMi ..
(1J5Jm'1)

1I1'l10 ..
(J151IIiI #3)

NOTES:
1 LoCK ACTIVE CAN OCCUR DURING ANY STATE, AS lONG AS THE
RELATIONSHIPS SHOWN ABOVE WITH RESPECT TO THE ClK ARE MAINTAINED.
INACTIVE HAS NO CRITICAL TIME AND CAN BE ASYNCHRONOUS.
-GRQlCK HAS NO CRITICAL TIMING AND IS'CONSIDERED AN ASYNCHRONOUS
INPUT SIGNAL
2 GLiTCHING OF SYSB/REsB PIN IS PERMITIED DURING THIS TIME. AFTER  2 OF
n, AND BEFORE <1>1 OF T4, SYSB/RESBSHOUlD BE STABLE
3 AEN lEADING EDGE IS RELATED TO BClK, TRAILING EDGE TO ClK THE
TRAILING EDGE OF AEN OCCURS AFTER BUS PRIORITY IS lOST.

LoCK

ADDITIONAL NOTES:
The signals related to ClK are typical processor signals, and do not relate to the depicted sequence of events of the
signals referenced to BClK. The signals shown related to the BClK represent a hypothetical sequence of events for
illustration. Assume 3 bus arbiters of priorities 1, 2 and 3 configured In serial priority resolving scheme as shown In
Figure 6. Assume arbiter 1 has the bus and is holding busy low. Arbiter #2 detect~rocessor wants the bus and
pulls low BREO#2. If BPRN#2 is high (as shown), arbiter #2 will pull low CBRO line CBRO signals to the higher priority
arbiter #1 that a lower priority arbiter wants the bus [A higher priority arbiter would be granted BPRN when it makes
the bus request rather than haVing to wait for another arbiter to release the bus through cmm]." Arbiter #1 will relinquish the multi-master system bus when it enters a state not requiring it (see Table 1), by lowering ItS BPROHl (tied to
BPRN#2) and releasing BUSY. Arbiter #2 now sees that It has Priority from BPRN#2 being low and releases CBRO. As
soon as BUSY signifies the bus is available (high), arbiter #2 pulls BUSY low on next failing edge of BClK. Note that if
arbiter #2 didn't want the bus at the time It received priority, It would pass priority to the next lower priority arbiter by
lowering its BPRO #2 [TPNPOj.
··Note that even a higher Priority arbiter which IS acqu"lng the bus through BPAN will momentarily drop

3-284

C'B'R'Q untl!

It has acquired the bus

APPLICATION
NOTE

AP·67

September 1979

@

Intel Corporation 1979

ORDER NUMBER: 230792·001

3-285

8086 System Design

Contents
1. INTRODUCTION ............................ .
2. 8086 OVERVIEW AND BASIC SYSTEM
CONCEPTS . ... : ........................... .

A.
B.
C.
D.

Bus Cycle Definition ...................... .
Address and Data Bus Concepts ............ .
System Data Bus Concepts ................ .
Multiprocessor Environment. .............. .

3. 8086 SYSTEM DETAILS ..... ......, ........... .
A.
B.
C.
D.
E.
F.
G.

Operating Modes., ...................... .
Clock Generation ........................ .
Reset .................................. .
Ready Implementation and Timing .......... .
Interrupt Structure ....................... .
Interpreting the 8086 Bus Timing Diagrams ... .
Bus Control Transfer .. : .................. .

4. INTERFACING WITH 1/0 ..................... .

5. INTERFACING WITH MEMORIES. " ........... .
6. APPENDIX . ................................ .

Intet CorporatIon Assumes No ResponsibIlity for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product No Other Circuit Patent Licenses are Implied

3-286

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AP-67
1. INTRODUCTION

guage Reference Guide (9800749A), AP·28A MULTI·
BUS ™ Interfacing (98005876B), INTEL MULTIBUS®
SPECIFICATION (9800683), AP·45 Using the 8202 Dy·
namic RAM Controller (9800809A), Ap·51 Designing
8086, 8088, 8089 Multiprocessor Systems with the 8289
Bus Arbiter and AP·59 Using the 8259A Programmable
Interrupt Controller. References to other Intel publica·
tions will be made throughout this note.

I

The 8086 family, Intel's new series of microprocessors
and system components, offers the designer an ad·
vanced system architecture which can be structured to
satisfy a broad range of applications. The variety of
speed, configuration and component selections avail·
able within the family enables optimization of a specific
design to both cost and performance objectives. More
important however, the 8086 family concept allows the
designer to develop a family of systems providing multi·
pie levels of enhancement within a single design and a
growth path for future designs.

2. 8086 OVERVIEW AND BASIC SYSTEM CONCEPTS
2A. 8086 Bus Cycle Definition

The 8086 is a true 16·bit microprocessor with 16·bit in·
ternal and external data paths, one megabyte of memory
address space (2**20) and a separate 64K byte (2**16)
1/0 address space. The CPU communicates with its ex·
ternal environment via a twenty·bit time multiplexed ad·
dress, status and data bus and a command bus. To
transfer data or fetch instructions, the CPU executes a
bus cycle (Fig. 2A1). The minimum bus cycle consists of
four CPU clock cycles called T states. During the first T
state (T1), the CPU asserts an address on the twenty·bit

This application note is directed toward the implemen·
tation of the system hardware and will provide an in·
troduction to a representative sample of the systems
configurable with the 8086 CPU member of the family.
Application techniques and timing analysis will be given
to aid the deSigner in understanding the system require·
ments, advantages and limitations. Additional Ihtel
publications the reader may wish to reference are the
8086 User's Manual (9800722A), 8086 Assembly Lan·

-T,- -- - T 2 ClK

---'

~

~

-

~T,JTw

v----.

T.-

-

-,~

-, r---I

A19/S6,Al6JS3

.J..

ADDR

)

-

READY

-

.x.

ADDRESS A1S-Ao \

y"

STATUS

P<

FlOA/'---1X

DATA IN 015-DO

1---

)r;;:OA"T r-----

--- -----

RD
READ
CYCLE

V

DTIR

(

1\

DEN

y.,

"ADDRESS

V

~

DATA OUT

WRITE
CYCLE

/

DEN

DTIR

--- ----Figure 2Al. Basic 8086 Bus Cycle

3-287

230792-001

AP-67
multiplexed address/data/status bus. For the second T
state (T2), the CPU removes the address from the bus
and either three·states Its outputs on the lower slxte~n
bus lines in preparation for a read cycle or asserts write
data. Data bus transceivers are enablee in either T1 or
T2 depending on the 8086 system configuration and the
direction of the transfer (into or out of the CPU). Read,
write or Interrupt acknowledge commands are always
enabled in T2. The maximum mode 8086 configuration
(to be discussed later) also provides a write command
enabled in T3 to guarantee data setup time prior to command activation.
During T2, the upper four multiplexed bus lines switch
,from address (A19·A16) to bus cycle status
(S6,S5,S4,S3). The status Information (Table 2A1) is
available primarily for diagnostic monitoring. However,
a decode of S3 and S4 could be used to select one of
four banks of memory, one assigned to each segment
register. This technique allows partitioning the memory
by segment to expand the memory addressing beyond
one megabyte. It also provides a degree of protection by
preventing erroneous write operations to one segment
from overlapping into another segment and destroying
information in that segment.
The CPU continues to provide status Information on the
upper four bus lines dl.lrlng T3 and will either continue
to assert write data or sample read data on the lower sixteen bus lines. If the selected memory or I/O device is
not capable of transferring data at the maximum CPU
transfer rate, the device must signal the CPU "not
ready" and force the CPU to Insert additional clock
cycles (Wait states TW) after T3. The 'not ready' indication must be presented to the CPU by the start of T3.
Bus activity during TW is the same as T3. When the
selected device has had sufficient time to complete the
transfer, it asserts "Ready" and allows the CPU to continue from the TW states. The CPU will latch the data on
the bus during the last walt state or during T3 if no wait
states are requested. The bus cycle Is terminated In T4
(command lines are disabled and the selected external
device deselects from the bus), The bus cycle appears
to devices in the system as an 'asynchronous event consisting of an address to select the device followed by a
read strobe or data and a write strobe. The selected
device accepts bus data during a. write cycle and drives
the desired data onto the bus during a read cycle. On termination of the command, the device latches write data
or disables its bus drivers. The only control the device
has on the bus cycle is the Insertion of wait cycles.
The 8086 CPU only executes a bus cycle when instructions or operands must be transferred to or from
memory or I/O devices. When not executing a bus cycle,
the bus Interface executes idle cycles (TI). During the
idle cycles, the CPU continues to drive status information from the previous bus cycle on the upper address
lines. If the previous bus cycle was a write, the CPU continues to drive the write data onto the multiplexed bus
until the start of the next bus cycle. If the CPU executes
idle cycles following a read cycle, the CPU will not drive
the lower 16 bus lines until the next bus cycle is
required.

Since the CPU prefetches up to six bytes of the instruction stream for storage and execution from an internal
Instruction queue, the relationship of instruction fetch
and associated operand transfe~s may be skewed In
time and separated by additional Instruction fetch bus
cycles. In general, If an Instruction is fetched into the
8086's Internal Instruction queue, several additional instructions may be fetched before the instruction Is
removed from the queue and executed. If the Instrw;:tlon
being executed from the queue is a jump or other' control transfer instruction, any instructions remaining in
the queue are not executed and are discarded with no effect on the CPU's operation. The bus activity observed
during execution of a specific Instruction is dependent
on the preceding instructions but Is always deterministic within the specific sequence.
Table 2A1

S3

S4

o

o

Alternate (relative to the ES segment)

1

0

Stack (relative to the SS segment)

o

Code/None (relative to the CS seg·
ment or a default of zero)

1

Data (relative to the OS segment)

S5 = IF (interrupt enable flag)
S6 = 0 (Indicates the 8086 Is on the bus)
2B. 8086 Address and Data Bus Concepts
Since the majority of system memories and peripherals
require a stable address for the duration of the bus
cycle, the address on the multiplexed address/data bus
during T1 should be latched and the latChed address
used to select the desired peripheral or memory location. Since the 8086 has a 16-bit data bus, the multiplexed bus components of the 8085 family are not ap·
plicabh~ to the 8086 (a device on address/data bus lines
8-15 will not be able to receive the byte selection address on lines 0-7). To demultiplex the bus (Fig. 2B1a),
the 8086 system provides an Address Latch Enable
signal (ALE) to capture the address in either the 8282 or
8283 8-bit bi-stable latches (Oiag. 2B1). The latches are
either inverting (8283) or non-inverting (8282) and have
outputs driven by three-state buffers that supply 32 mA
drive capability and can switch a 300 pF capacitive load
in 22 ns (inverting) or 30 ns (non-inverting). They propagate the address through to the outputs while ALE is
high and latch the address on the falling edge of ALE.
This only delays address access and chip select
decoding by the propagation delay of the latch. The outputs are enabled through the low active OE input. The
demultiplexing of the multiplexed address/data bus
(Iatchings of the address from the multiplexed bus), can
be done locaily at appropriate points In the system or at
the CPU with a separate address bus distributing the address throughout the system (Fig. 2B1b). For optimum
system performance and compatibility with multiprocessor and MULTIBUS™ configurations, the latter technique is strongly recommended over the first. The remainder of this note will assume the bus is demultiplexed at the CPU.

3-288

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AP-67
The programmer views the 8086 memory address space
as a sequence of one million bytes in which any byte
may contain an eight bit data element and any two con·
secutive bytes may contain a 16-bit data element. There
is no constraint on byte or word addresses (boundaries).
The address space is physically implemented on a sixteen bit data bus by dividing the address space into two
banks of up to 512K bytes (Fig. 2B2). One bank is connected to the lower half of the sixteen-bit data bus (07-0)
and contains even addressed bytes (AD = 0). The other
bank is connected to the upper half of the data bus
(015-8) and contains odd addressed bytes (AO= 1). A
specific byte within each bank is selected by address
lines A19-Al. To perform byte transfers to even addresses (Fig. 2B3a), the information is transferred over
the lower half of the data bus (07-0). AD (active low) is
used to enable the bank connected to the lower half of
the data bus to participate in the transfer. Another
signal provided by the 8086, Bus High Enable (SHE), is
used to disable the bank on the upper half of the data
bus from participating in the transfer. This is necessary
to prevent a write operation to the lower bank from
destroying data in the upper bank. Since BHE is a
multiplexed signal with timing identical to the A19-A16
address lines, it also should be latched with ALE to provide a stable signal during the bus cycle. During T2
through T4, the BHE output is multiplexed with status
line S7 which is equal to BHE. To perform byte transfers
to odd addresses (Fig. 2B3b), the information is transferred over the upper half of the data bus (015-08) while
BHE (active low) enables the upper bank and AD
disables the lower bank. Directing the data transfer to
the appropriate half of the data bus and activation of
BHE and AD is performed by the 8086, transparent to the
programmer. As an example, consider loading a byte of
data into the CL register (lower half of the CX register)
from an odd addressed memory location (referenced
over the upper half of the 16-bit data bus). The data is
transferred into the 8086 over the upper 8 bits of the
data bus, automatically redirected to the lower half of
the 8086 internal 16-bit data path and stored into the CL
register. This capability also allows byte 1/0 transfers
with the AL register to be directed to 1/0 devices connected to either the upper or lower half of the 16-bit data
bus.

8086

ADDRESS
BUS

Figure 2B1a. Demultiplexing the 8086 Bus

ADDRESS BUS

8086
CPU

DATA BUS
SEPARATE ADDRESS AND DATA BUSSES

r------.,
I
I

I
I

I

I

I
I

I

r·----~-+~

f-~----- ALE

8086
CPU

'--.J.....____J\ ADDRESSJDATA
BUS

I

II

I ______ JI
L

MULTIPLEXED BUS WITH lOCAL ADDRESS DEMUlTIPlEXING

I
I

To access even addressed sixteen bit words (two consecutive bytes with the least significant byte at an even

Figure 2B1 b.

T,
ClK

---J

r--"\

r---\

,-I"

-- --- ~

DATA IN OR OUT

T,

T,

,--..

~--

ALE

\

'Tw

T,

r--\
'j

---

---

_X __
,...--

---

I

,Diagram 2B1. ALE Timing

3-289

230792-001

I
I

AP-67
byte address), A 19-A 1 select the appropriate byte within
each bank and AO and BHE (active low) enable both
banks simultaneously (Fig. 2B3c). To access an odd addressed 16-bit word (Fig. 2B3d), the least significant
byte (addressed by A19-A1) is first transferred over the
upper half of the bus (odd addressed byte, upper bank,
BHE low active and AO = 1). The most significant byte is
accessed by incrementing the address (A 19-AO) which
allows A19-A1 to address the next physical word location (remember, AO was equal to one which indicatef! a
word referenced from an odd byte boundary). A second
bus cycle is then executed to perform the transfer of the
most significant byte with the lower bank (AO is now active low and BHE i.s high). The sequence is automatically
executed by the 8086 whenever a word transfer is executed to an odd address. Directing the upper and lower
bytes of the8086's internal sixteen-bit registers to the
appropriate halves of the data bus is also performed
automatically by the 8086 and is transparent to the pro·
grammer.

TRANSFER X + 1, X

r----,

r----,
(X)

Ao(LOW)

Figure 2B3c. Even Addressed Word Transfer

' ' I FIRST BUS CYCLE

~------~.

~------~

(8) PHYSICAL IMPLEMENTATION OF THE

IA) LOGICAL ADDRESS SPACE

ADDRESS SPACE

FFFFF
FFFFE

512K BYTES

51::K BYTES

FFFFF

FFFFE
FFFFC

FfFFD

FFFFO

SHE (LOW)

FFFFC

07-00

Ao(HIGH)

SECOND BUS CYCLE

m

~--~

~~-,

Y+l
X+l

(V)

A.

1 MEGABYTE

Figure 2B2. 8086 Memory

SHE (HIGH)

Ao(LOW)

Figure 2B3d. Odd Addressed Word Transfer

All-A,

015-08

07-00

Ao (LOW)

Figure 2838. Even Addressed Byte Transfer
TRANSFER X + 1

.--J\

rv'

1
All-A,

Y+l

"'"

i'-

'"

7

015-08

Y
X

.J.,

~(X+l);;;:;

1

_I

SHE (LOW)

rv'

During a byte read, the CPU floats the entire sixteerl-bit
, data bus even though data is only expected on the upper
or lower half of the data bus. As will be demonstrated
later, this action simplifies the chip select decoding requirements for read only devices (ROM, EPROM). During
a byte write operation, the 8086 will drive the entire
sixteen-bit data bus. The information on the half of the
data bus not transferring data is indeterminate. These
concepts al.so apply to the 1/0 address space. Specific
examples of 1/0 and memory interfacing are considered
in the corresponding sections.
2C_ System Data Bus Concepts

L.

.>..

""

"7

07-00

Figure 2B3b. Odd Addressed Byte T,ansfer

When referring to the system data bus, two Implementation alternatives must be considered; (a) the multiplexed addressldata bus (Fig. 2C1a) and a data bus buffered from the multiplexed bus by transceivers (Fig.
2C1b). .
Ao (HIGH)

If memory or 1/0 devices are connected directly to the
multiplexed bus, the designer must guarantee the
devices do not corrupt the address on the bus during n.

3-290

230792-001

AP-67
To avoid this, device output drivers should not be enabl·
ed by the device chip select, but should have an output
enable controlled by the system read signal (Fig. 2C2).
The 8086 timing guarantees that read is not valid until
after the address is latched by ALE (Oiag. 2C1). All Intel
peripherals, EPROM products and RAM's for microproc·
essors provide output enable or read inputs to allow
connection to the multiplexed bus.

MULTIPLEXED DATA BUS

8086
ALE

1-4--......- ,

ADDRESS
8282's

ALE----I

ADDRESS BUS

' -_ _ _ _....:..;AD""ccS-.:cAc::;DO'-'\ MULTIPLEXED
ADDRESS/DATA

MULTIPLEXED
BUS

Figure 2Cla. Multiplexed Data Bus

WR------01

BUFFERED DATA BUS

RD------01

Figure 2C2. Devices wilh Output Enables on the Multiplexed Bus
8282

ALE

ADDRESS

1--;'--_1

SYSTEM

BUS

A subsequent limitation on the multiplexed bus is the
8086's drive capability of 2.0 mA and capacitive loading
of 100 pF to guarantee the specified A.C. character·
istics. Assuming capacitive loads of 20 pF per I/O
device, 12 pF per address latch and 5·12 pF per memory
device, a system mix of three peripherals and two to
four memory devices (per bus line) are close to the
loading limit.

DATA

Figure 2Clb. Buffered Data Bus

T1

ALE

Several techniques are available for interfacing devices
without output enables to the multiplexed bus but each
introduces other restrictions or limitations. Consider
Figure 2C3 which has chip select gated with read and
write. Two problems exist with this technique. First, the
chip select access time is reduced to the read access
time, and may require a faster device if maximum
system performance (no wait states) is to be achieved
(Oiag. 2C2). Second, the designer must verify that chip
select to write setup and hold times for the device are
not violated (Oiag. 2C3). Alternate techniques can be ex·
tracted from the bus interfacing techniques given later
in this section but are subject to the associated restric·
tions. In general, the best solution is obtained with
devices having output enables.

T2

T3

T4

,---,:.----

\

Diagram 2Cl. Relationship of ALE to READ

3-291

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AP-67
To satisfy the capacitive Ipading and drive requirements
of larger systems, the data bus must be buffered. The
8286 non-inverting and 8287 inverting octal transceivers
are offered as part of the 8086 family to satisfy this requirement. They have three·state output buffers that
drive 32 mA on the bus interface and 10 mA on the CPU
interface and can switch capacitive loads of 300 pF at
the b.us interface and 100 pF on the CPU interface in 22
ns (8287) or 30 ns (8286). To enable and control the direction of the transceivers, the 808/l-system provides Data
ENable (DEN) and Data Transmit/Receive (DT/Ai signals
(Fig. 2Cl b). These signals provide the appropriate timing to guarantee isolation of the multiplexed bus from
the system during Tl and elimination of bus contention
with the CPU during read and write (Diag. 2C4). Although
'the memory and peripheral devices are isolated from the
CPU (Fig. 2C4), bus contention may still exist in the
system if the devices do not have an output enable control other than chip select. As an example, bus contention will exist during transition from one chip select to
another (the newly selected device begins driving the
bus before the previous device has disabled its drivers).
Another, more severe case exists during a write cycle.
From chip select to write active, a device whose outputs
are controlled only by chip select, will drive the bus
simultaneously with write data being driven through the
transceivers by the CPU (Oiag. 2C5). The same tech·
nique given for circumventing these problems on the
multiplexed bus can be applied here with the same limitations.

Figure 2C3, Device. without Output Enable. on the Multiplexed Bu.

AOORE.. - - < ' -_ _ _ _ _ _ _ _ _ _ _ _ _ __

'\

.

1

_2 __

\

Cs.RDiWR

DATA
1

ACCESS TIME FOR CS GENERATED FROM ADDRESS DeCODe

2

ACCESS TIME IF CS IS GATED WITH AD/WR.

Diagram 2C2. Acce.s Time: CS Gated with RiiIWR

AOOR--<'-_ _ _ _ _ _ _ _ _ _ _ _ _ __

1u

WR---------~

an
1

CS IS NOT VALID PRIOR TO WRITE AND BECOMES ACTIVE ONE OR TWO GATE

DELAYS LATER.
2

~

CS REMAINS VALtO AFTER WRITE ONE OR TWO GATE DELAYS.

Diagram 2C3. CS to WR Set·Up and Hold

One last extension to the bus implementation is a second level of buffering to reduce the tot!).1 load seen by
devices on the system bus (Fig_ 2C5). This is typically
done for multi board systems and isolation of memory
arrays. The concerns with this configuration are the additional delay for access and more important, control of
the second transceiver in relationship to the system bus
and the device being interfaced to the system bus.
Several techniques for controlling the transceiver are
given in Figure 2C6. This first technique (Fig. 2C6a)
simply distributes DEN and DT/R throughout the
system. DT/R is inverted to provide proper direction control for the second level transceivers. The second example (Fig. 2C6b) provides control for devices with output
enables. RD is used to normally direct data from the
system bus to the peripheral. The buffer is selected
whenever a device on the local bus is chip selected. Bus
contention is possible on the device's local bus during a
read as the read simultaneously enables the device output and changes the transceiver direction. The contention may also occur as the read is terminated.
For devices without output enables, the same technique
can be applied (Fig. 2C6c) if the chip select to the device
is conditioned by read or write. Controlling the chip
select with read/write prevents the device from driving
against the transceiver prior to the command being
received. The limitations with this technique are acces~
limited to read/write time and limited CS to write setup
and hold times.

3-292

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AP-67

ADo

-----Tlll~T2 _ _-_T3_~T4-

AD1s~ADo

ADDRESS

A15~Ao

CYCLE

DT/R

1

r--

DATA IN

-------X FLOAT

015- 0 0

--- -----

\

AD

1 READ

- -- D<

I FLOAT

-

i"\
,

DEN

ADDRESS

AD1S"ADo

V

1\

X

DATA OUT

I

FLOAT

ViR
WRITE

CYCLE

V

DEN

Dnil

- --- _J
I

1

DEN IS ENABLED AFTER THE 8086 HAS FLOATED THE MULTIPLEXED BUS

2

DEI'I ENABLES THE TRANSCEIVERS EARLY IN THE CYCLE. BUT DTIR GUARANTEES
THE TRANSCEIVERS ARE IN TRANSMIT RATHER THAN RECEIVE MODE AND WILL
NOT DRIVE AGAINST THE CPU.

Diagram 2C4. Bus Transceiver Control

ADDR~~_____________________________

.:~_?r--_----.~-)+--------

~

BUS CONTENTION ~
BOTH DEVICES DRIVE _______
THE BUS

Figure 2C4. Devices with Output Enables on the System Bus

--<.

.

------------------

Diagram 2C5.

3-293

230792-001

AP-67

CPU LOCAL
BUS

MEMORY/IO
LOCAL BUS

SYSTEM
BUS

Figure 2C5. Fully Bullered System

I \r-;:;C;;;--11

MEMORYniO DEVICES

828817

Figure 2C6a. Controlling System Transceivers with DEN and DT/R

WR----------------------_,

An alternate technique applicable to devices with and
without output enables is shown In Figure 2C6d. RD
again controls the direction of the transceiver but it Is
not enabled until a command and chip select are active.
The possibility for bus contention still exists but Is
reduced to variations in output enable vs. direction
change time for the transceiver. Full access time from
chip select is now available, but data will not be valid
prior to write and will only be held valid after write by the
delay to disable the transceiver.

e!----p------------,

ilI----------~--------_,

RD--------~--~--------~~~

SYSTEM /

L.._ _ _ _.J \1

MEMOAYIlIO

DATA

DEVICE

BUS

8211/7

Figure 2C6b. Bullerlng Devices with

OEiiiO
MEMORY/UO
DEVICE

Figure 2C6d. Sullerlng Devices without
or Separate Input/Output

MEMORY/I/O

DEVICE

Figure 2C6c. Bullerlng Device. without OEiiiO and with Common
or Separate Input/Output

OEliiD and with Common

One last technique Is given for devices with separate Inputs and outputs (Fig. 2C6e). Separate bus receivers and
drivers are provided rather than a single transceiver. The
receiver Is always enabled while the bus driver Is controlled by RD and chip select. The only possibility for
bus contention in this system occurs as multiple
devices on each line of the local read bus are enabled
and disabled during chip selection changes.
Throughout this note, the multiplexed bus will be considered the local CPU bus and the demultlplexed address .and buffered data bus will be the system bus. For
additional information on bus contention and the
system problems associated with It, refer to Appendix 1.

3-294

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AP-67
strapping options) extend the configuration options
beyond a pure CPU interface to ,he multi master system
bus for access to shared resources to include concur·
rent support of a local CPU bus for private resources.
For specific configurations and additional information
on the 8289, refer to application note AP·51.

~~------------------------,

lI1l--qL-'/
WR--------1---------------~

SYSTEM

DATA

74504
OR
748240

-1-------+-;

3. 8086 SYSTEM DETAILS

LOCAL WRITE BUS

o

BUS

MEMORY/I/O
LOCAL READ BUS

DEVICE

748240

Figure 2C6e. Buffering Devices without
Input/Output

OEIRD

and with Separate

3A. Operating Modes
Possibly the most unique feature of the 8086 is the abili·
ty to select the base machine configuration most suited
to the application. The MN/MX Input to the 8086 Is a
strapping option which allows the deSigner to select
between two functional definitio(ls of a subset of the
8086 outputs.
MINIMUM MODE

20. Multiprocessor Environment
The 8086 architecture supports multiprocessor systems
basad on the concept of a shared system bus (Fig. 201).
All CPU's in the system communicate with each other
and share resources via thl! system bus. The bus may be
either the Intel Multibus™ system bus or an extension
of the system bus defined in the previous section. The
major addition required to the demultiplexed system
bus is arbitration logiC to control access to the system
bus. As each CPU asynchronously requests access to
the shared bus, the arbitration logic resolves priorities
and grants bus access to the highest priority CPU. Hav·
ing gained access to the bus, the CPU completes its
transfer and will either relinquish the bus or wait to be
forced to relinquish the bus. For a discussion on
Multibus™ arbitration techniques, refer to AP·28A, Intel
Multibus™ Interfacing.

Figure 201. 8086 Family Multiprocessor System

To support a multimaster interface to the Multibus
system bus for the 8086 family, the 8289 bus arbiter is
included as part of the family. The 8289 is compatible
with the 8086's local bus and in conjunction with the
8288 bus controller, implements the Multibus protocol
for bus arbitration. The 8289 provides a variety of arbitra·
tion and prioritization techniques to allow optimization
of bus availability, throughput and utilization of shared
resources. Additional features (implemented through

The minimum mode 8086 (Fig. 3A1) is optimized for
small to medium (one or two boards), Single CPU
systems. Its system architecture is directed at satisfy·
ing the requirements of the lower to middle segment of
high performance 16·bit applications. The CPU main·
tains the full megabyte memory space, 64K byte 110
space and 16·bit data path. The CPU directly provides all
bus control (DT/R, DEN, ALE, M/iO), commands
(RD,WR,INTA) and a Simple CPU preemption mech·
anism (HOLD, HLDA) compatible with existing DMA
controllers.
MAXIMUM MODE
The maximum mode (Fig. 3A2) extends the system ar·
chitecture to support multiprocessor configurations,
and local instruction set extension processors (co·
processors). Through addition of the 8288 bipolar bus
controller, the 8086 outputs assigned to bus control and
commands in the minimum mode are redefined to allow
these extensions and enhance general system perform·
ance. Specifically, (1) two prioritized levels of processor
preemption (RO/GTO, RO/GT1) allow multiple proc·
essors to reside on the 8086's local bus and share its in·
terface to the system bus, (2) Oueue status (OSO,OS1) is
available to allow external devices like ICeM·86 or
special instruction set extension co·processors to track
the CPU instruction execution, (3) access control to
shared resources in multiprocessor systems is sup·
ported by a hardware bus lock mechanism and (4)
system command and configuration options are ex·
panded via ancillary devices like the 8288 bus controller
and 8289 bus arbiter.
The queue status indicates what information is being
removed from the internal queue and when the queue is
being reset due to a transfer of control (Table 3A 1): By
monitoring the SO,51,52 status lines for instructions
entering the 8086 (1,0,0 indicates code access while AO
and 'BHE indicate word or byte) and OSO, OS1 for in·
structions leaving the 8086's internal queue, it is possi·
ble to track the instruction execution. Since instruc·
tions are executed from the 8086's internal queue, the
queue status is presented each CPU clock cycle and is
not related to the bus cycle activity. This mechanism (1)
allows a co·processor to detect execution of an

3-295

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AP-67
ESCAPE instruction which directs the co-processor to
perform a specific task and (2) allows ICE-S6 to trap execution of a specific memory location. An ex~mple of a
circuit used by ICE is given In Figure 3A3. The first up
down counter tracks the depth of the queue while the
second captures the queue depth on a match. The second counter decrements on further fetches from the
queue until the queue is flushed or the count goes to
zero indicating execution of the match address. The
first counter decrements on fetch from the queue
(050= 1) and increments on code fetches into the

vee

queue. Note that a normal code fetch will transfer two
bytes into the queue so two clock increments are given
to the counter (T201 and T301) unless a single byte is
loaded over the upper half of the bus (AO-P is high).
Since the execution unit (EU) is not synchronized to the
bus interface unit (BIU), a fetch from the queue can occur simultaneously with a transfer into the queue. The
exclusive-or gate driving the ENP input of the first
counter allows these simultaneous operations to cancel
each other and not modify the queue depth.

~O~

~ -,~.

GENERATOR

RES

T

MN/MX "'-Vcc
_

ClK

_

READY

INTA

_

RESET

AD
WR

MIlO

ROY

t

GND

DTiR

DEN
8086 CPU
ALE

}

COMMAND
BUS

----,

----, I
I I
II

A16·A19

BHE

I
I

STB

Of

GND!!

1,.1
ADo~AD15

r----..,I

I I

~

~DDR/~ATA

Y

,---

I I
II
IL

8282
lATCH
2qR 3

J

>

1 MEGABYTE
ADDRESS BUS

J----:1
T---'I

L---'oe
I

8286

TRAN~gEIVER

II
II ~

>

l6·BIT
DATA BUS

OPTIONAL
FOR INCREA'SED
DATA BUS DRIVE

Figure 3Al. Minimum Mode 8086
Vee

~
T

GND

rO~

-

CLOCK

t
_

So
51
52

SO

~NERATOR

RES

ClK

MN/MX J-GND

ClK

S;

. . READY
_
RESET

52

RDY

t

LoCK r-

iOWC
AK!Wl:
INTA

ALE

COMMAND
BUS

-

-

N.C.

GND
ADo-A015 A
A16-A19 rDDR/DATA

BHE

I---

r---

DT;R

-

r---

8288 AMWC
BUS
IORC I - - CTRlR

; - - - - DEN
8086
CPU

MRDC
MWTC

-

-

STB

OS

f"

8282
lATCH
(2 OR 3)

V

\

1 MEGABYTE

V ADDRESS BUS

r

I

Lt;:

T

OS
8286
TRANSCEIVER
(2)

~

III
I~

f"
Y

l6·BIT
DATA BUs'

-~

FIgure 3A2. MaxImum Mode 8086

3-296

230792-001

AP..67
TABLE 3A1. QUEUE STATUS

QS1

QSo

o(LOW)

0
1
0
1

0
1 (HIGH)
1

tion of the locked instruction) without intervention and
possible corruption of the data by another CPU. A
classic use of the mechanism is the 'TEST and SET,
semaphore' during which a CPU must read from a
shared memory location and return data to the location
without allowing another CPU to reference the same
location between the TEST operation (read) and the SET
operation (write). In the 8086 this is accomplished with a
locked exchange instruction.

No Operation
First Byte of Op Code from Queue
Empty the Queue
Subsequent Byte from Queue

The queue status is valid during the CLK cycle after
which the queue operation is performed.
To address the problem of controlling access to shared
resources, the maximum mode 8086 provides a hard·
ware LOCK output. The LOCK output is activated
through the instruction stream by, execution of the
LOCK prefix instruction. The LOCK output goes active
in the first CPU clock cycle following execution of the
prefix and remains active Yntil the clock following the
completion of the instruction following the LOCK prefix.
To provide bus access control in multiprocessor
systems, the LOCK Signal should be incorporated into
the system bus arbitration logic resident to the CPU.
During normal multiprocessor system operation, priority of the shared system bus Is determined by the ar·
bitration circuitry on a cycle by cycle basis. As each
CPU requires a transfer over the system bus, it requests
access to the bus via its resident bus arbitration logic.
When the CPU gains priority (determined by the system
bus arbitration scheme and any associated logic), it
takes control of the bus, performs its bus cycle and
either maintains bus control, voluntarily releases the
bus or is forced off the bus by the loss of priority. The
lock mechanism prevents the CPU from losing bus con·
trol (either voluntarily or by force) and guarantees a CPU
the ability to execute multiple bus cycles (during execu-

LOCK XCHG reg, MEMORY ; reg is any register
;MEMORY is the address of the

;semaphore

The activity of the LOCK output is shown in Diagram
3A 1. Another interesting use of the LOCK for multiprocessor systems. is a locked block move which allows high
speed message transfer from one CPU's message buf·
fer to another.
During the locked instruction, a request for processor
preemption (RQ/GT) is recorded but not acknowledged
until completion of the locked instruction. The LOCK
has no direct affect on interrupts. As an examE.\e, a
locked HALT instruction will cause HOLD (or RQ/GT) reo
quests to be ignored but will allow the CPU to exit the
HALT state on an interrupt. In general, prefix bytes are
considered extensions of the instructions they precede.
Therefore, interrupts that occur during execution of a
, prefix are not acknowledged (assuming interrupts are
enabled) until completion of the instruction following
the prefixes (except for instructions which allow servic·
ing Interrupts during their execution, i.e., HALT, WAIT
and repeated string primitives). Note that multiple prefix
bytes may precede an instruction. As another example,
consider a 'string primitive' preceded by the repetition

. - - - -...D>o----2~CLK

=============!r:~!-------------1-----~~------~8~LOAD74S169
OCTO

MHtlVTE AND 1 CLKA
OS1, QSO
T301, T201
-

SODf-S2t'R'
C ACCESS
OCTO
AO·P

1OOl---:;-"""I

SWI-----.....:.~,/

MATCH CONDITIONS
CPU CLOCK

CPU QUEUE STATUS
T STATES T3 and 12 (CLOCK LOW TIME_01)
CPU STATUS SG-S2
- CODE ACCESS
- QUEUE MATCH
..
- SINGLE BYTE ON UPPER HALF OF THE 8US

-

~13~-----------------------------------------------------CACC~

mR _____-"1,3
74S04

Figur. 3A3. Example Circuit to Track the 8086 Queue

3-297

230792-001

AP-67
prefix (REP) which is interruptible after each execution
of the string primitive. This holds even if the REP prefix
is combined with the lOCK prefix and prevents inter·
rupts from being locked out during a block move or
other repeated string operation. As long as the operation is not interrupted, lOCK remains active. Further information on the operation of an interrupted string
operation with multiple prefixes is presented in the section dealing with the 8086 interrupt structure.
Three additional stah:Js lines (SO, 51, 52) are defined to
provide communications with the 8288 and 8289. The
status lines tell the 8288 when to initiate a bus cycle,
what type of command to issue and when to terminate
the bus cycle. The 8288 samples the status lines at the
beginning of each CPU clock (ClK). To initiate a bus cycle, the CPU drives the status lines from the passive
state (SO, 51, 52 =1) to one of seven possi ble command
codes (Table 3A2). This occurs on the rising edge of the
c,lock during T4 of the previous bus cycle or a TI (idle cycle, no current bus activity). The 8288 detects the status
change by sampling the status lines on the high to low
transition of each clock cycle. The 8288 starts a bus cycle by generating ALE and appropriate buffer direction
control in the clock cycle immediately following detection of the status change (T1). The bus transceivers and
the selected command are enabled in the next clock
cycle (T2) (or T3 for normal write commands). When the
status returns to the passive state, the 8288 will terminate the command as shown in Diagram 3A2. 5ince
the CPU will not return the status to the passive state
until the 'ready' indication is received, the 8288 will
maintain active command and bus control for any
number of wait cycles. The status lines may also be
used by other processors on the 8086's local bus to
monitor bus activity and control the 8288 if they gain
control of the local bus.

TABLE 3A2. STATUS LINE DEcODES

52

51

So

o(lOW)

0
0
1·
1
0
0
1
1

0
>
1
0
1
0
1
0
1

0
0
0
1 (HIGH)
1
1
1

Interrupt Acknowledge
Read 110 Port
Write 110 Port
Halt
Code Access
Read Memory
Write Memory
Passive

The 8288 provides the bus control (DEN, DTlR, ALE) and
commands (INTA, MRDC, 10RC, MWTC, AMWC, 10WC,
AIOWC) removed from the CPU. The command structure
has separate read and write commands for memory, and
110 to provide compatibility with the Multibus command
structure.
The advanced write commands are enabled one clock
period earlier than the normal write to accommodate the
wider write pulse widths often required by peripherals
and static RAMs. The normal write provides data setup
prior to write to accommodate dynamic RAM memories
and 110 devices which strobe data on the leading edge of
write. The advanced write commands do not guarantee
that data is valid prior to the leading edge of the command. The DEN signal in the maximum mode is inverted
from the minimum mode to extend transceiver control
by allowing logical conjunction of DEN with other
signals. While not appearing to be a significant benefit
in the basic maximum mode configuration, introduction
of inter~upt control and various system configurations
will demonstrate the usefulness of qualifying DEN.
Diagram 3A3 compares the timing of the minimum and
maximum mode bus transfer commands. Although. the

CLK

"---------~~

QSO

~--------------------~

LOCK

LOCKED INSTRUCTION

NOP BYTE
FROM THE
QUEUE
(LOCKED NOP)

LOCK
PREFIX
BYTE FROM
QUEUE
1

QUEUE STATUS INDICATES FIRST BYTE OF OPCODE FROM THE QUEUE.

2

THE

3

TWO CLOCKS ARE REQUIRED FOR DECODE OF THE LOCK PREFIX AND
ACTIVATION OF THE LOCK SIGNAL.

4

SINCE QUEUE STATUS REFLECTS THE QUEUE OPERATION IN THE PREVIOUS CLOCK
CYCLE, THE i:OCR OUTPUT ACTUALLY GOES ACTIVE COINCIDENT WITH THE START
OF THE NEXT INSTRUCTION AND REMAINS ACTIVE FOR ONE CLOCK CYCLE
FOLLOWING THE INSTRUCTION.

i:OCR OUTPUT WILL GO INACTIVE BETWEEN SEPARATE LOCKED INSTRUCTIONS.

S IF THE INSTRUCTION FOLLOWING THE LOCK PREFIX IS NOT IN THE QUEUE, THE
LOCK OUTPUT STILL GOES ACTIVE AS SHOWN WHILE THE INSTRUCTION IS BEING
FETCHED.
6

THE BIU WILL STILL PERFORM INSTRUCTION FETCH CYCLES DURING EXECUTION
OF A LOCKED INSTRUCTIQN. THE i:OCR MERELY LOCKS THE BUS TO THIS CPU FOR
WHATEVER BUS CYCLES THE CPU PERFORMS DURING THE LOCKED INSTRUCTION.

Diagram 3A 1. 8086 Lock Activity

3-298

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AP-67
maximum mode configuration is designed for multiprocessor environments, large single CPU designs
(either Multibus systems or greater than two PC boards)
should also use the maximum mode. Since the 8288 is a
bipolar dedicated controller device, Its output drive for
the commands (32 mAl and tolerances on AC characteristics (timing parameters and worse case delays) provide better large system performance than the minimum
mode 8086.

In addition to assuming the functions removed from the
CPU, the 8288 provides additional strapping options and
controls to support multiprocessor configurations and
peripheral devices on the CPU local bus. These capabilities allow assigning resources (memory or I/O) as
shared (available on the Multibus system bus) or private
(accessible only by this CPU) to reduce contention for
access to the Multibus system bus and improve multi~CPU system performance. Specific configuration possibilities are discussed in AP-51.

ClK

GOES INACTIVE IN THE STATE

::~ /=€~'.

\

READY

\\\\~\~

READY

9

WAIT

Diagram 3A2. Status Line Activation and Termination

ClK (8284 OUTPUT)

MN
MODE
8088

TCVCTV

WI!
TCVCTX-

TClMl

TClMH

35

"flIiIjl!ORmJie

MX
MODE
BOS8

WITH
8288

35 ft8

TClMl

.lil.WmOR~

MW'Tl: OR lOWe
Diagram 3A3. 8086 Minimum and Maximum Mode Command Timing

3-299

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AP-67
38. Clock Generation
The 8086 requires a clock signal with fast rise and fall
times (10 ns max) between low and high voltages of
- 0.5 to + 0.6 low and 3.9 to VCC + 1.0 high. The max·
imum clock frequency of the 8086 is 5 MHz and 8 MHz
for the 8086-2. Since the design of the 8086 incorporates
dynamic cells, a minimum frequency of 2 MHz is reo'
quired to retain the state of the machine. Due to the
minimum frequency requirement, single stepping or
cycling of the CPU may not be accomplished by disabling the clock. The timing and voltage requirements of
the CPU clock are shown in Figure 3B1. In general, for
frequencies below the maximum, the CPU clock need
not satisfy the frequency dependent pulse width limitations stated in the 8086 data sheet. The values
specified only reflect the minimllm values which must
be satisfied and are stated in terms of the maximum
clock frequency. As the clock frequency approaches the
maximum frequency of the CPU, the clock must conform to a 33% duty cycle to satisfy the CPU minimum
clock low and high time specifications.

500 ns MAX

Flgur.381. 8086 Clock

An optimum 33% duty cycle clock with the required
voltage levels and transition times can be obtained with
the 8284 clock generator (Fig. 392). Either an external
frequency source or a series resonant crystal may drive
the 8284. The selected source must oscillate at 3X the
desired CPU frequency. To select the crystal Inputs of
the 8284 as the frequency source for clock generation,
the Fie Input to the 8284 must be strapped to ground.
The strapping option allows selecting either the crystal
or the external frequency Input as the source for clock
generation. Although the 8284 provides an Input for a
tank circuit to accommodate overtone mode crystals,
fu ndamental mode crystals are recommended for more
accurate and stable frequency generation. When selec·
tlng a crystal for use with the 8284, the series resistance
should be as low as possible. Since other circuit com·
ponents will tend to shift the operating frequency from
resonance, the operating Impedance will typically be
higher than the specified series resistance. If the attenuation of the oscillator's feedback circuit reduces
the loop gain to less tl1an one, the oscillator will fall.
Since the oscillator delays In the 8284 appear as induc·
tlve elements to the crystal, causing it to run at a fre·
quency below that of the pure series resonanc.e, a
capaCitor should be placed in series with the crystal and
the X2 input of the 8284. This capaCitor serves to cancel
this inductive element. The value of the capaCitor (CL)

must not cause the impedance of the feedback circuit to
reduce the lOOp gain below one. The impedance of the
capaCitor is a fun«tion of the operating frequency and
can be,determined from the following equation:
XCL= 1/211*F*CL

17
XTAL

I:J

Y

OSC

X,

12
8088

8284
18
CL

13

19 elK

CLK

X,
F/I::

Figure 382. 8284 Clock Generalor

It is recommended that the crystal series resistance

plus XCL be kept less than 1K ohms. This capacitor also
serves to debias the crystal and prevent a DC voltage
bias from straining and perhaps damaging the crystalline structure. As the crystal frequency increases, the
amount of capacitance should be decreased. For example, a 12 MHz crystal may require CL 'V 24 pF while 22
MHz may require CL'V 8 pF. If very close correlation
with the pure series resonance Is not necessary, a
nominal CL value of 12-15 pF may be used with a 15 MHz
crystal (5 MHz 8086 operation). Board layout and compo·
nent variances will affect the actual amount of inductance and therefore the series capacitance required to
cancel it out (this is especially true for wire-wrapped
layouts).
Two of the many vendors which supply crystals for Intel
microprocessors are listed in Table 381 along with a list
of crystal part numbers for various frequencies which
may be of interest. For additional Information on specifying crystals for Intel components refer to application
note AP-35.
TAaLE 3al. CRYSTAL VENDORS

f

Parallell
Series

Crystek(l)
Corp.

CTS Knlght,(2
Inc.

15.0 MHz
18.432
24.0 MHz

S
S
S

CY15A
CY198*
CY24A

MP150
MP184*
MP240

, 'Inlel also supplies a cryslal numbered 8801 for Ihls application.
Notea: I. Address: 1000 Crystal Drive, Fort Meyers, Florida 33901
,2. Address: 400 Reimann Ave., SandWich, illinois

If a high accuracy frequency source, externally variable
frequency source or a common source for driving mUltiple 8284's is desired, the External Frequency Input
(EFI) of the 8284 can be selected by strapping the FICinput to 5 volts through 'V1 K ohms (Fig. 383). The external
frequency source should be TIL compatible, have a
50% duty cycle and oscillate at three times the desired
CPU operating frequency. The maximum EFI frequency
the 8284 can accept is slightly above 24 MHz with
minimum clock low and high times of 13 ns. Although

3-300

230792-001

AP-67
no minimum EFI frequency is specified, it should not
violate the CPU minimum clock rate. If a common frequency source is used to drive multiple 8284's
distributed throughout the system, each 8284 should be
driven by its own line from the source. To minimize
noise In the system, each line should be a twisted pair
driven by a buffer like the 74lS04 with the ground of the
twisted pair connecting the grounds of the source and
receiver. To minimize clock skew, the lines to all 8284's
should be of equal length. A simple technique for generating a master frequency source for additional 8284's
is shown in Figure 384. One 8284 with a crystal is used
to generate the desired frequency. The oscillator output
of the 8284 (OSC) equals the crystal frequency and is
used to drive the external frequency to all other 8284's
in the system.

+s
X,
i:X2

EXTERNAL
'Fie
FnEQUENCy----'=-! EFI
SOURCE

ClK

1-=-_ _-""'-1 ClK

8284

8088

Figure 3B3. 8284 with External Frequency Source

There are three frequency outputs from the 8284, the
oscillator (OSC) mentioned above, the system clock
(ClK) which drives the CPU, and a peripheral clock
(PClK) that runs at one half the CPU clock frequency.
The oscillator output is only driven by the crystal and is
not affected by the Fie strapping ortion. If a crystal is
not connected to the 8284 ,when the external frequency
input is used, the oscillator output is indeterminate. The
CPU clock is derived from the selected frequency
source by an internal divide by three counter. The
counter generates the 33% duty cycle clock which is optimum for the CPU at maximum frequency. The
peripheral clock has a 50% duty cycle and is derived
from the CPU clock. Diagram 380 shows the relationship of ClK to OSC and PClK to ClK. The maximum
skew is 20 ns between OSC and ClK, and 22 ns between
ClK and PClK.
Since the state of the 8284 divide by three counter is indeterminate at system initialization (power on), an external sync to the counter (CSYNC) is provided to allow
synchronization of the CPU clock to an external event.
When CSYNC is brought high, the ClK and PClK outputs are forced high. When CSYNC returns low, the next
positive clock from the frequency source starts clock
generation. CSYNC must be active for a minimum of two
periods of the frequency source. If CSYNC is asynchronous to the frequency source, the circuit in Figure 385
should be used for synchronization. The two latches
minimize the probability of a meta-stable state in the
latch driving CSYNC. The latches are clocked with the
inverse of the frequency source to guarantee the 8284
setup and hold time of CSYNC to the frequency source
(Diag. 381). If a single 8284 is to be synchronized to an
external event and an external frequency source is not
used, the oscillator output of the 8284 may be used to

I:J

Y

The oscillator output Is inverted from the oscillator
Signal used to drive the CPU clock generator circuit.
Therefore, the oscillator output of one 8284 should not
drive the EFI input of a second 8284 if both are driving
clock inputs of separate CPU's that are to be synchronized. The variation on EFI to ClK delay over a
range of 8284's may approach 35 to 45 ns. If, however, all
8284's are of the same package type, have the same
relative supply voltage and operate in the same temperature environment, the variation will be reduced to
between 15 and 25 ns.

18

13

+s
Figure 384. External Frequency for Multiple 8284$

O~

ClK

PClK

Diagram 3BO. OSC

~

ClK and ClK

3-301

~

PClK Relationships

230792-001

AP-67
synchronize CSYNC (Fig. 386). Since the oscillator output is inverted from the internal oscillator signal, the inverter in the previous example is not required. If multiple
8284's are to be synchronized, an external frequency
source must drive all 8284's·and a single CSYNC synchronization circuit must drive the CSYNC input of all
8284's (Fig. 387). Since activation of CSYNC may cause
violation of CPU minimum clock low time, it should only
be enabled during reset or CPU clock high. CSYNC must
also be disabled a minimum of four CPU clocks before
the end of reset to guarantee proper CPU reset.

+5

lK

EXTERNAL

TO
L--------------EFI
INPUT

Figure 3B5. Synchronizing CSYNC with EFI

EFI

CSYNC

J,
I

--J

Figure 387. Synchronizing Multiple 8284s

TO
CSYNC
INPUT

SYNC-----(
CONDITION
EXTERNAL
FREQUENCY

I
I
f--TYHEH

Due to the fast transitions and high drive (5 mAl of the
8284 ClK output, it may be necessary to put a 10 to 100
ohm resistor in series with the clock line to eliminate
ringing (reSistor value depending on the amount of drive
required). If multiple sources of ClK are needed with
minimum skew, ClK can be buffered by a high drive
device (74S241) with outputs tied to 5 volts through 100
ohms to guarantee VOH = 3.9 min (8086 minimum clock
input high voltage) (Fig. 388). A single 8284 should not
be used to generate the ClK for multiple CPU's that do
not share a common local (multiplexed) bus since the
8284 synchronizes ready to the CPU and can only accommodate ready for a single CPU. If multiple CPU's
share a local bus, they should be driven with the same
clock to optimize transfer of bus control. Under these
circumstances, only one CPU will be using the bus for a
particular bus cycle which allows sharing a common
READY signal (Fig. 389).

-MAX IS SPEC'ED TO GUARANTEE MAX 8086 CLOCK FREQUENCY

Diagram 3Bl. CSYNC Setup and Hold to EFI
+5

ClK

OSC 12

+5

Cl

~

8284
18

lOOQ

X,
FIC
CSYNC elK 8

SYNC

100Q

Figure 3B6. EFI from 8284 Oscillator

Figure 3B8. Buffering the 8284 ClK Output

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AP-67

MULTIPLEXED BUS

Figure 3B9. 8086 and Co-Processor on the Local Bus Share a
Common 8284

3C. Reset
The 8086 requires a high active reset with minimum
pulse width of four CPU clocks except after power on
which requires a 50 '"'s reset pulse. Since the CPU internally synchronizes reset with the clock, the reset is internally active for up to one clock period after the external reset. Non-Maskable Interrupts (NMI) or hold requests on RQ/GT which occur during the internal reset,
are not acknowledged. A minimum mode hold request
or maximum mode RQ pulses active immediately after
the internal reset will be honored before the first instruction fetch.

guarantee the inactive state of these lines in systems
where leakage currents or bus capacitance may cause
the voltage levels to settle below the minimum high
voltage of devices in the system. In maximum mode
systems, the 8288 contains internal pull-ups on the
SO-52 inputs to maintain the inactive state for these
lines when the CPU floats the bus. The high state of the
status lines during reset causes the 8288 to treat the
reset sequence as a passive state. The condition of the
8288 outputs for the passive state are shown in Table
3C2. If the reset occurs during a bus cycle, the return of
the status lines to the passive state will terminate the
bus cycle and return the command lines to the inactive
state. Note that the 8288 does not three-state the command outputs based on the passive state of the status
lines. If the designer needs to three-state the CPU off
the bus during reset in a single CPU system, the reset
signal should also be connected to the 8288's AEN input
and the output enable of the address latches (Fig. 3C2).
This forces the command and address bus interface to
three-state while the inactive state of DEN from the 8288
three-states the transceivers on the data bus.

From reset, the 8086 will condition the bus as shown in
Table 3C1. The multiplexed bus will three-state upon
detection of reset by the CPU. Other signals which
three-state will be driven to the inactive state for one
clock low interval prior to entering three-state (Fig. 3C1).
In the 'minimum mode, ALE and HLDA are driven inactive and are not three-stated. In the maximum mode
RQ/GT lines are held inactive and the queue status in:
dicates no activity. The queue status will not indicate a
reset of the queue so any user defined external circuits
monitoring the queue should also be reset by the
system reset. 22K ohm pull-up resistors should be connected to the CPU command and bus control lines to

Table 3Ct. 8086.Bus During Reset

Signals

Condition

AD 15·0
A 19.1 slS6-3
BHE/S 7
S2/(M/IQ)
S1/(DT/R)
SOlD EN
LOCKlWR
RD
INTA
ALE
HLDA
RQ/GTO
RQ/GT1
QSO
QS1

Three-State
Three-State
Three-State
Driven to "1" then three-state
Driven to "1" then three-state
Driven to "1" then three-state
Driven to "1" then three-state
Driven to "1" then three-state
Driven to "1" then three-state
0
0
1
1
0
0

CLOCK

RESET INPUT

INTERNAL RESET

BUS

t

LFLOATBUS

~ DRIVE OUTPUT TO INACTIVE STATE

Figure 3Cl. 8086 Bus Conditioning on Reset

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AP-67
TABLE 3C2. 8288 OUTPUTS DURING PASSIVE MODE

o
o

ALE
DEN

DTiA

1
0/1

MCE/PDEN
COMMANDS

1

8088

Figure 3C2. Reset Disable lor Max Mode 8086 Bus Interlace

For multiple processor systems using arbitration of a
multimaster bus, the system reset should be connected
to the INIT input of the 8289 bus arbiter in addition to
the 8284 reset input (Fig. 3C3). The low active INIT input
forces all 8289 outputs to their inactive state. The inactive state of the 8289 AEN output will force the 8288 to
three-state the command outputs and the address
latches to three-state the address bus Interface. DEN inactive from the 8288 will three-state the data bus Jnterface. For the multimaster CPU configuration, the reset
should be common to all CPU's (8289's and 8284's) and
satisfy the maximum of either the CPU reset requirements or 3 TBLBL (3 8289 bus clock times) + 3
TCLCL (3 8086 clock cycle times) to satisfy 8289 reset
requirements.

If the 8288 command outputs are three-stated during
reset, the command lines should be pulled up to Vee
through 2.2K ohm resistors.
The reset signal to the 8086 can be generated by the
8284. The 8284 has a' schmitt trigger Input (RES) for
generating reset from a low active externai res'et. The
hysteresis specified in the 8284 data sheet implies that
at least .25 volts will separate the 0 and 1 switching
point of the 8284 reset input. Inputs without hysteresis
will switch from low to high and high to low at approximately the same voltage threshold. The inputs are
guaranteed to switch at specified low and high voltages
(VIL and VIH) but the actual switching point is anywhere
in-between. Since VIL min is specified at .8 volts, the
hysteresis guarantees that the reset will be active until
the input reaches at least 1.05 volts. A reset will not be
recognized until the input drops at least .25 volts below
the reset inputs VIH of 2.6 volts.
To guarantee reset from power up, the reset input must
remain below 1.05 volts for 50 microseconds after Vcc
has reached the minimum supply voltage of 4.5 volts.
The hysteresis allows the reset input to be driven by a
simple RC circuit as shown in Figure 3C4. The
calculated RC value does not include time for the power
supply to reach 4.5 volts or the charge accumulated during this interval. Without the hysteresis, the reset output might oscillate as the input voltage passes through
the switching voltage of the input. The calcuiated RC
value provides the minimum required reset period 01'50
microseconds for 8284's that switch at the 1.05 voit
level and a reset period of approximately 162 microseconds for 8284's that switch at the 2.6 volt level. If
tighter tolerance between the minimum and maximum
reset times is necessary, the reset circuit shown in
Figure 3C5 might be used rather than the simple RC circuit. This circuit provides a constant current source and
a linear charge rate on the capacitor rather than the inverse exponential charge rate of the RC circuit. The
maximum reset period for this implementation is 124
microseconds.

+Y

RESET IN _ _+-_...;1'-'-11

m
8284

8284
RESET

t

_ SO"sec

Y

Yo

= 4.5
= 1.05

RC

~

188x10- 8

RESET
8086

~

o

Figure 3C3. Reset Disable 01 lor Max Mode 8086 Bus Interlace in
Multi CPU System

Figure 3C4. 8284 Reset Circuit

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AP-67
3D. Ready Implementation and Timing
Vee

As discussed previously, the ready signal is used in the
system to accommodate memory and 1/0 devices that
cannot transfer information at the maximum CPU bus
bandwidth. Ready is also used in multiprocessor
systems to force the CPU to wait for access to the
system bus or Multibus system bus. To insert a wait
state in the bus cycle, the READY signal to the CPU
must be Inactive (low) by the end of T2. To avoid insertion of a wait state, READY must be active (high) within
a specified setup time prior to the positive transition
during T3. Depending on the size and characteristics of
the system, ready implementation may take one of two
approaches.

0,
R, R2 -

02

DETERMINES CURRENT TO CHARGE C
VALUE NOT CRITICAL ~10K

Ie = CHARGE CURRENT = V.olD,
RESET
IF ALL

~ 02 -

T11

SEMICONDU~TORS ARE SILICON. Ie. ~

,~_ _ _ _ ~vee-'6

T

Figure 3C5. Constant Curren! Power·On Reset Circuit

The 8284 synchronizes the reset Input with the CPU
clock to generate the RESET signal to the CPU (Fig.
3C6). The output Is also available as a general reset to
the entire system. The reset has no effect on any clock
circuits in the 8284.

17

t:l

Y
+5

19

8284
18
13

11

SYSTEM
RESET

CLK 8

X,

X,
Fie

CLK

8086
RESET 10

21

RESET

The classical ready implementation is to have the
system 'normally not ready.' When the selected device
receives the command (RD/WR/INTA) and has had sufficient time to complete the command, it activates
READY to the CPU, allowing the CPU to terminate the
bus cycle. This implementation is characteristic of large
multiprocessor, Multibus systems or systems where
propagation delays, bus access delays and device characteristics inherently slow down the system. For maximum system performance, devices that can run with no
wait states must return 'READY' within the previously
described limit. Failure to respond in time will only
result in the insertion of one or more'wait cycles.
An alternate technique is to have the system 'normally
ready.' All devices are assumed to operate at the maximum CPU bus bandwidth. Devices that do not meet the
requirement must disable READY by the,end of T2 to
guarantee the insertion of wait cycles. This implementation is typically applied to small single CPU systems
and reduces the logic required to control the ready
signal. Since the failure of a device requiring wait states
to disable READY by the end of T2 will result in premature termination of the bus cycle, the system timing
must be carefully analyzed when using this approach.
The 8086 has two different timing requirements on
READY depending on the system implementation. For a
'normally ready' system to insert a wait state, the
READY must be disabled within 8 ns (TRYLCL) after the
end of T2 (start of T3) (Diag. 3D1). To guarantee proper

RES

.I

Figure 3C6. 8086 Reset and System Reset

CLOCK

8088 READY

30 ns

READY INACTIVE 8 ns

I--

119 ns TO GUARANTEE THE
NEXT CYCLE IS T4

Diagram 3D1. Normally Ready System Inserting a 'wait State

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operation of the 8086, the READY input must hot change
from ready to not ready during the clock low time of T3.
For a 'normally" not ready' system to avoid wait states"
READY must be active within 119 ns (TRYHCH) of the'

positive clock transition during T3 (Diag. 3D2). For both
cases, READY must satisfy a hold time of 30 ns
(TCH!;,!YX) from the T3 or TW positive clock transition.

CLOCK

8088 READY

Diagram 302. Normally Not Ready Sys em Avoiding a Wait State

To generate a stable READY signal which satisfies the
previous setup and hold times, the 8284 provides two
separate system ready inputs (RDY1, RDY2) and a single
synchronized ready output (READY) for the CPU. The
RDY inputs are qualified with separate access enables
(AEN1,AEN2, low active) to allow selecting one of the
two ready signals (Fig. 3D1). The gated signals are
logically OR'ed and sampled at the beginning of each
ClK cycle to generate READY to the CPU (Diag. 3D3).
The sampled READY signal is valid within 8 ns (TRYlCl)
after ClK to satisfy the CPU timing requirements on
'not ready' and ready. Since READY cannot change until
the next ClK, the hold time requirements are also satisfied. The system ready inputs to the 8284 (RDY1,RDY2)
must be valid 35 ns (TRIVCl) before T3 and AEN must be
valid 60 ns before T3. For a system using only one RDY
input, ~associated AEN is tied to ground while the
other AEN is connected to 5 volts through "'1 K ohms
(Fig. 3D2a). If the system generates a low active ready
Signal, it can be connected to the 8284 AEN input if the
additional setup time required by the 8284 AEN input is
satisfied. In this case, the associated RDY input would
be tied high (Fig. 3D2b).

ClK

CJ

Y
+5

8

19
21

RESET 10
18
13

X,
FIe

22

READY

ClK
RESET
READY
8086

8284

11

RES
AEN1
RDY1
7 AEN2
6 RDY2
3

I

Figure 301. Ready Inputs to the 8284 and Output to the 8086

,

CLOCK

8284 RDY SETUP

8284 READY OUT
(TO 8086)

NOTE: THE 8284 DATA SHEET SPECIFIES READY OUT DELAY (TRYLCl) AS -8 ns
'BEFORE" THE END OF T, WHICH IMPLIES THE TIMING SHOWN.

Diagram 303. 8284 with 8086 Ready Timing

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AP-67
memory. If the access to non·existent memory fails to
enable READY, the system will be caught in an in·
definite wait.

8284

+5

Figure 3D2a. Using RDY1/RDY2 10 Generale Ready

Figure 3D3. Single Wail State Generator
3
4

AEN1

8284

RDY1

3E. Interrupt Structure

~AEN2
RDY2

1K

+5
Figure 3D2b. Using AEN1/AEN2 10 Generale Ready

The majority of memory and peripheral devices which
fail to operate at the maximum CPU frequency typically
do not require more than one wait state. The circuit
given in Figure 3D3 is an example of a simple wait state
generator. The system ready line is driven low whenever
a device requiring one wait state is selected. The flip
flop is cleared by ALE, enabling RDY to the 8284. If no
wait states are required, the flip flop does not change. 'If
the system ready is driven low, the flip flop toggles on
the low to high clock transition of T2 to force one wait
state. The next low to high clock transition toggles the
flip flop again to indicate ready and allow completion of
the bus cycle. Further changes in the state of the flip
flop will not affect the bus cycle. The circuit allows
approximately 100 ns for chip select decode and condi·
tloning of the system ready (Diag. 3D4).

The 8086 interrupt structure is based on a table of inter·
rupt vectors stored in memory locations OH through
003FFH. Each vector consists of two bytes for the in·
struction pOinter and two bytes for the code segment.
These two values combine to form the address of the in·
terrupt service routine. This allows the table to contain
up to 256 interrupt vectors which specify the starting ad·
dress of the service routines anywhere in the one mega·
byte address space of the 8086. If fewer than 256 differ·
ent interrupts are defined in the system, the user need
only allocate enough memory for the interrupt vector
table to provide the vectors for the defined interrupts.
During initial system debug, however, it may be desir·
able to assign all undefined interrupt types to a trap
'routine to detect erroneous interrupts.

If the system is 'normally not ready,' the programmer
should not assign executable code to the last six bytes
of physical memory. Since the 8086 prefetches instruc·
tions, the CPU may attempt to access non·existent
memory when executing code at the end of physical

Each vector is associated with an interrupt type number
which points to the vector's location in the interrupt vec·
tor table. The interrupt type number multiplied by four
gives the displacement of the first byte of the associ·
ated interrupt vector from the beginning of the table. As
an example, interrupt type number 5'points to the sixth
entry in the interrupt vector table. The contents of this
entry in the table points to the interrupt service routine
for type 5 (Fig. 3E1). This structure allows the user to
specify the memory address of each service routine by
placing the address (instruction pOinter and code seg·
ment values) in the table location provided for that type
interrupt.

Diagram 3D4.

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AP-67

INTERRUPT TYPE

TYPE 1 -

MEMORY

r ~U~B!.A - ,-----:::----;:-::O:.OO"'-''=;..,

•

1----;:;,---.;

I

r-----r---~~--~ 004

~§'08

;-;---

I

I

ooe

01'

:--- t==~=::j
L_~__

INTERRUPT

VECTOR

TABLE

3FE :
__~

400

TYPE 5 INTERRUPT
SERVICE ROUTINE

TYPE 2 -

NMI (Non-Maskable Interrupt)

This is the highest priority hardware interrupt and is
non-maskable. The input is edge triggered but is synchronized with the CPU clock and must be active for two
clock cycles to guarantee recognition. The interrupt
signal may be removed prior to entry to the service
routine. Since the input must make a low to high transition to generate an interrupt, spurious tranSitions on the
input should be suppressed. If the input is normally
high, the NMI low time to guarantee triggering is two
CPU clock times. This input is typically reserved for
catastrophic failures like power failure or timeout of a
system watchdog timer.

' - -_ _ _ _..J FFFFE

Figure 3El. Direction to Interrupt Service Routine through the
Interrupt Vector Table

All interrupts in the 8086 must be assigned an interrupt
type which uniquely identifies each interrupt. There are
three classes of interrupt types in the 8086; predefined
interrupt types which are issued by specific functions
within the 8086 and user defined hardware and software
interrupts. Note that any interrupt type Including the
predefined interrupts can be issued by the user's hardware and/or software.

TYPE 3 -

ONE BYTE INTERRUPT

This is invoked by a special form of the software interrupt instruction which requires a Single byte of code
space. Its primary use is as a breakpoint interrupt for
software debug. With full representation within a Single
bytE!, the instruction can map into the smallest instruction for absolute resolution in setting breakpoints. The
interrupt is not maskable.

PREDEFINED INTERRUPTS
The predefined interrupt types in the 8086 are listed
, below with a brief description of how each is invoked.
When invoked, the CPU will transfer control to the
memory location specified by the vector associated
with the specific type. The user must provide the interrupt service routine and initialize the interrupt vector
table with the appropriate service routine address. The
user may additionally invoke these interrupts through
hardware or software. If the preassigned function is not
used in the system, the user may assign some other
function to the associated type. However, for compatibility with future Intel hardware and software products for the 8086 family, interrupt types 0-31 should not
be assigned as user defined interrupts.
TYPE 0 -

SINGLE STEP

This interrupt type occurs one instruction after the TF
(Trap Flag) is set in the flag register. It is used to allow
software single stepping through a sequence of code.
Single stepping is initiated by copying the flags onto the
stack, setting the TF bit on the stack and popping the
flags. The interrupt routine should be the single step
routine. The interrupt sequence saves the flags and program,counter, then resets the TF flag to allow the Single
step routine to execute normally. To return to the
routine under test, an interrupt return restores the IP,
CS and flags with TF set. This allows the execution of
the next instruction in the program under test before
trapping back to the Single step routine. Single Step is
not masked by the IF (Interrupt Flag) bit In the flag
register.

TYPE 4 -

INTERRUPT ON OVERFLOW

This interrupt occurs if the overflow flag (OF) is set in
the flag register and the INTO instruction is executed.
The instruction allows trapping to an overflow error service routine. The interrupt is non-maskable.
Interrupt types 0 and 2 can occur without specific action
by the programmer (except for performing a divide for
Type 0) while types 1, 3, and 4 require a conscious act by
the programmer to generate these interrupt types. All
but type 2 are invoked through software activity and are
directly associated with a specific instruction.

DIVIDE ERROR

This interrupt type is invoked whenever a division operation is attempted during which the quotient exceeds the
maximum value (ex. division by zero). The interrupt is
non-maskable and is entered as part of the execution of
the divide instruction. If interrupts are not reenabled by
the divide error interrupt service routine, the service
routine execution time should be included in the worst
case divide instruction execution time (primarily when
considering the longest instruction execution time and
its effect on latency to servicing hardware interrul1ts).

USER DEFINED SOFTWARE INTERRUPTS
The user can generate an interrupt through the software
with a two byte interrupt instruction INT nn. The first
byte is the INT opcode while the second byte (nn) contains the type, number of the interrupt to be performed.
The INT instruction is not maskable by the interrupt
enable flag. This instruction can be used to transfer control to routines that are dynamically relocatable and
whose location in memory is not known by the c;;tlling

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AP-67
program. This technique also saves the flags of the calling program on the stack prior to transferring control.
The called procedure must return control with an interrupt return (IRET) in,struction to remove the flags from
the stack and fully restore the state of the calling program.

UNINTERRUPTABLE INSTRUCTION SEQUENCE
MOV SS, NEW$STACK$SEGMENT
MOV SP, NEW$STACK$POINTER
Also, since prefixes are considered part of the instruction they precede, the 8086 will not sample the interrupt
line until completion of the instruction the prefix(es)
precede(s). An exception to this (othE1r than HALT or
WAIT) is the string primatives preceded by the repeat
(REP) prefix. The repeated string operations will sample
the interrupt line at the completion of each repetition.
This includes repeat string operations which include the
lock prefix. If multiple prefixes precede a repeated
string operation, and the instruction is Interrupted, only
the prefix immediately preceding the string primative is
restored. To allow correct resumption of the operation,
the following programming technique may be used:

All interrupts invoked through software (all interrupts
discussed thus far with the exception of NMI) are not
maskable with the IF flag and initiate the transfer of
control at the end of the instruction in which they occur.
They do not initiate interrupt acknowledge bus cycles
and will disable subsequent maskable interrupts by
resetting the IF and TF flags. The interrupt vector for
these interrupt types is either implied or specified in the
instruction. Since the NMI is an asynchronous event to
the CPU, the point of recognition and initiation of the
transfer of control is similar to the maskable hardware
interrupts.

LOCKED$BLOCK$MOVE: LOCK REP MOVS DEST, CS:SOURCE
ANDCX,
CX

USER DEFINED HARDWARE INTERRUPTS

JNZ LOCKED$BLOCK$MOVE

The maskable interrupts initiated by the system hardware are activated through the INTR pin of the 8086 and
are masked by the IF bit of the status register (interrupt
flag). During the last clock cycle of each instruction, the
state of the INTR pin is sampled. The 8086 deviates from
this rule when the instruction is a MOV or POP to a segment register. For this case, the interrupts are not
sampled until completion of the following instruction.
This allows a 32-bit pOinter to be loaded to the stack
pointer registers SS and SP without the danger of an interrupt occurring between the two loads. Another exception is the WAIT instruction which waits for a low active
input on the TEST pin. This instruction also continuously samples the interrupt request during its execution
and allows servicing interrupts during the wait. When an
interrupt is detected, the WAIT instruction is again
fetched prior to servicing the interrupt to guarantee the
interrupt routine will return to the WAIT instruction.

T,

ALE

I

T2

~~

T3

T4

TI

The code bytes generated by the 8086 assembler for the
MOVS instruction are (in descending order): LOCK
prefix, REP prefix, Segment Override prefix and MOVS.
Upon return from the interrupt, the segment override
prefix is restored to guarantee one additional transfer is
pertormed between the correct memory locations. The
instructions following the move operation test the
repetition count value to determine if the move was
completed and return if not.
If the INTR pin is high when sampled and the IF bit is set
to enable interrupts, the 8086 executes an interrupt
acknowledge sequence. To guarantee the interrupt will
be acknowledged, the INTR input must be held active
until the interrupt acknowledge is issued by the CPU. If
the BIU is running a bus cycle when the interruptcondition is detected (as would occur if the BIU is fetching an
instruction when the current instruction completes), the

-----,n,---__
TI

Tt

I

T,

_ _

\'------------'/
\
FLOAT

FLOAT

REDRIVEN BY CPU IF QUEUE IS NOT FULL

Figure 3E2. Interrupt Acknowledge Sequence

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AP-67
interrupt must be valid at the 8086 2 clock cycles prior to
T4 of the bus cycle if the next cycle is to be an interrupt
acknowledge cycle. If the 2 clock setup is not satisfied,
another pending bus cycle will be executed before the
interrupt acknowledge is issued. Ita hold request is also
pending (this might occur if an interrupt and hold request are made during execution of a locked instruction), the interrupt is serviced after the hold request is
serviced.
'
The interrupt acknowledge sequence is only generated
in response to an interrupt on the 8086 INTR input. The
associated bus activity is shown in Figure 3E2. The cycle consists of two INTA bus cycles separated by two
idle clock cycles. During the bus cycles the INTA command is issued rather than read. No address is provided
by the 8086 during either bus cycle (BHE and status are
valid), however, ALE is still generated and will load the
address latches with indeterminate information. This
condition requires that devices in the system do not
drive their outputs without being qualified by the Read
Command. As will be shown later, the ALE is useful in'
maximum mode systems with multiple 8259A priority interrupt controllers. During the INTA bus cycles, DTiFi
and DEN are conditioned to allow the 8086 to receive a
one byte interrupt type number from the interrupt
system. The first INTA bus cycle signals an interrupt
acknowledge cycle is in progress and allows the system
to prepare to present the interrupt type number on the
next INTA bus cycle. The CPU does not capture information on the bus during the first cycle. The type number
must be transferred to the 8086 on the lower half of the
16-bit data bus during the second cycle. This implies
that devices which present interrupt type numbers to
the 8086 must be located on the lower half of the 16-bit
data bus. The timing of the INTA bus cycles (with exception of address timing) is similar to read cycle timing.
The 8086 interrl:lpt acknowledge sequence deviates
from the form used on 8080 and 8085 in that no instruction is issued as part of the sequence. The 8080 and
8085 required either a restart or call instruction be
issued to affect the transfer of control.
In the minimum mode system, the MilO signal will be
low indicating 1/0 during the INTA bus cycles. The 8086
internal LOCK signal will be active from T2 of the first
bus cycle until T2 of the second to prevent the BIU from
honoring a hold request between the two INTA cycles.
In the maximum mode, the status lines SO-82 will request the 8288 to activate the INTA output for each cydIe. The LOCK output of the 8086 will be active from T2
of the first cycle until T2 of the second to prevent the
8086 from honoring a hold request on either RQ/GT input and to prevent bus arbitration logic from relinquishing the bus between INTA's in multi-master systems.
The consequences of READY are identical to those for
READ and WRITE cycles,
Once the 8086 has the interrupt type number (from the
bus for hardware interrupts, from the instruction stream
for software interrupts or from the predefined can·
dition), the type number is multiplied by four to form the
displacement to the corresponding interrupt vector in
the interrupt vector table. The four bytes of the interrupt

vector are: least significant byte of the instruction
pointer, most significant byte of the instruction pointer,
least significant byte of the code segment register,
most significant byte of the code segment register. During the transfer of control, the CPU pushes the flags and
current code segment register and instruction pointer
onto the stack. The new code segment and instruction
painter values are loaded and the single step and interrupt flags are reset. Resetting the interrupt flag disables
response to further hardware interrupts in the service
routine unless the flags are specifically re-enabled by
the service routine. The CS and IP values are read from
the interrupt vector table with data read cycles. No segment registers are used when referencing the vector
table during the interrupt context switch. The vector
displacement is added to zero to form the 20-bit address
and S4, S3 10 indicating no segment register selection.

=

The actual bus activity associated with the hardware interrupt acknowledge sequence is as follows: Two interrupt acknowledge bus cycles, read new IP from the interrupt vector table, read new CS from the interrupt vector table, Push flags, Push old CS, Opcode fetch of the
first instruction of the interrupt service roufine, and
Push old IP. After saving the old IP, the BIU will resume
normal operation of prefetching instructions Into the
queue and servicing EU requests for operands, S5 (interrupt enable flag status) will go inactive in the second
clock cycle following reading the new CS.

,

The number of clock cycles from the end of the instruction during which the interrupt occurred to the start of
interrupt routine execution is 61 clock cycles. For software generated interrupts, the sequence of bus cycles
is the same except no interrupt acknowledge bus cycles
are executed. This reduces ihe delay to service routine
execution to 51 clocks for "!NT nn and single step, 52
clocks for INT3 and 53 clocks for INTO. The same interrupt setup requirements with respect to the BIU that
were stated for the hardware interrupts also apply to the
software interrupts. If wait states are inserted by either
the memories or the device supplying the interrupt type
number, the given clock times will increase accordingly.
When considering the precedence of interrupts for
multiple simultaneous interrupts, the following guidelines apply: 1.INTR is the only maskable interrupt and if
detected simultaneously with other interrupts, resetting
of IF by the other interrupts will mask INTR. This causes
INTR to be the lowest priority interrupt serviced after all
other interrupts unless the other interrupt service
routines reenable interrupts. 2. Of the nonmaskable interrupts (NMI, Single Step and software generated), in
general, Single Step has highest priority (will be serviced first) followed by NMI, followed by the software interrupts. This implies that a simultaneous NMI and
Single Step trap will cause the NMI service routine to
fo!low Single step; a simultaneous software trap and
Single Step trap will cause the software interrupt service routine to follow single step and a simultaneous
NMI and software trap will cause the NMI service
routine to be executed followed by the software interrupt service routine. An exception to this priority structure occurs if all three interrupts are pending. For this
case, transfer of control to the software interrupt ser-

3-310

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AP-67
vice routine followed by the NMI trap will cause both the
NMI and software interrupt service routines to be ex·
ecuted without single stepping. Single stepping
resumes upon execution of the instruction following the
instruction causing the software interrupt (the next in·
struction in the routine being single stepped).

TF='
IF=1

INTR

If the user does not wish to single step before INTR ser·
vice routines, the single step routine need only disable
interrupts during execution of the program being single
stepped and reenable interrupts on entry to the single
step routine. Disabling the interrupts during the pro·
gram under test prevents entry into the interrupt service
routine while single step (TF =1) is active. To prevent
single stepping before NMI service routines, the single
step routine must check the return address on the stack
forthe NMI service routine address and return control to
that routine without single step enabled. As examples,
consider Figures 3E3a and 3E3b. In 3E3a Single Step
and NMI occur simultaneously while in 3E3b, NMI, INTR
and a divide error all occur during a divide instruction
being Single stepped.

TF,IF=1

NMI

CONTINUE TO SINGLE STEP
THE PROGRAM

Figure 3E3b. NMI, INTR, Single Step and Divide Error Simultaneous
Interrupts
NORMAL SINGLE STEP
OPERATION

.

SYSTEM CONFIGURATIONS
To accommodate the INTA protocol of the maskable
hardware interrupts, the 8259A is provided as part of the
8086 family. This component is programmable to
operate in both 8080/8085 systems and 8086 systems.
The devices are cascadable in master/slave arrange·
ments to allow up to 64 interrupts in the system. Figures
3E4 and 3E5 are examples of 8259A's in minimum and
maximum mode 8086 systems. The minimum mode con·
figuration (a) shows an 8259A connected to the CPU's

Figure 3E3a. NMI During Single Stepping and Normal Single Step
Operation

3-311

230792-001

AP-67
the 8086/8288 to control the bus transceivers. To select
the proper slave when servicing a slave interrupt, the
master must provide a cascade address to the slave. If
the 8288 is not strapped in the 1/0 bus mode (the 8288
lOB Input connected to ground), the MCE/PDEN output
becomes a MCE or Master Cascade Enable output. This
signal is only active during INTA cycles as shown in
Figure 3E6 and enables the master 8259A's cascade address onto the 8086's local bus during ALE. This allows
the address latches to capture the cascade address with
ALE and allows uS,e of the system address bus for
selecting the proper slave 8259A. The MCE is gated with
LOCK to minimize local bus contention between the
8086 three-stating its bus outputs and the cascade address being enabled onto the bus. The first INTA bus cycle allows the master to resolve internal priorities and
output a cascade address to be transmitted to the
slaves on the subsequent INTA bus cycle. For additional
information on the 8259A, reference application note
AP-59.

multiplexed bus. Configuration (b) illustrates an 8259A
connected to a demultiplexed bus system. These inter·
connects are also applicable to maximum mode
systems. The configuration given for a maximum mode
system shows a master 8259A on the CPU's multiplexed
bus with additional slave 8259A's out on the buffered
system bus. This configuration demonstrates several
unique features of the maximum mode system inter·
face. If the master 8259A receives interrupts from a mix
of slave 8259A's and regular interrupting devices, the
slaves must provide the type number for devices connected to them while the master provides the type
number for devices directly attached to its interrupt inputs. The master 8259A is programmable to determine if
an interrupt is from a direct input or a slave 8259A and
will use this information to enable or disable the data
bus transceivers (via the 'nand' function of DEN and
EN). If the master must provide the type number, it will
disable the data bus transceivers. If the slave provides
the type number, the master will enable the data bus
transceivers. The EN output is normally high to allow

ADDRESS
~-----r-------.-r----~,-----~/BUS

IJL-------------..::..::...------"''"'-----..I\

DATA

~~----------------------------~/BUS

a.

b.
Figure 3E4. Min Mode 8086 with Master 8259A on the Local Bus and Slave 8259As on the System Bus

3-312

230792-001

AP-67

~~----~~r-------4r----+-----4r----+---~INTA

ADDRESS
~'--------r--------",-------~ro--------,/BUS

' -________________-"'0-________-""'-______.... \

DATA

,---------------------------------------'/BUS

Figure 3E5. Max Mode 8086 with Master 8259A on the Local Bus and Slave 8259As on the System Bus

I

ALEf\'----_ _",\---In'---__
I

T1

T2

T3

T4

TI

T[

T1

T,

T3

\~_ _ _ ____J/

FLOAT

\'---------'/

\'-----

Figure 3E6. MCE Timing to Gate 8259A CAS Address onto the 8086 Local Bus

3-313

230792-001

AP-67
3F.

Int~rpretlng

the 8086 Bus Timing Diagrams

At first glance, the 8086 bus timing diagrams (Diag. 3F1
min mode and Diag. 3F2 max mode) appear rather com·
plex. However, with a few words of explanation on how
to interpret them, they become a powerful tool in deter·
mining system requirements. The timing diagrams for
both the minimum and maximum modes may be divided
into six sections: (1) address and ALE timing; (2) read cycle timing; (3) write cycle timing; (4) interrupt acknowledge timing; (5) ready timing; and (6) HOLD/HLDA or
RQ/GT timing. Since the A.C. characteristics of the
Signals are specified relative to the CPU clock, the relationship between the majority of signals can be deduced by simply determining the clock cycles between
the clock edges the signals are relative to and adding or
subtracting the appropriate minimum or maximum
parameter values. One aspect of system timing not compensated for in this approach is the worst case relationship between minimum and maximum parameter values
(also known as tracking relationships). As an example,
consider a signal which has specified minimum and
maximum turn on and turn off delays. Depending on
device characteristics, it may not be possible for the
component to simultaneously demonstrate a maximum
turn-on and minimum turn-off delay even though worst
case analysis might imply the possibility. This argument
is characteristic of MOS devices and is therefore- applicable to the 8086 A.C. characteristics. The message
is: worst case analysis mixing minimum ood maximum
delay parameters will typically exceed the worst case
obtainable and therefore should not be subjected to further subjective degradation to obtain worst-worst case
values. This section will provide guidelines for specific
areas of 8086 timing sensitive to tracking relationships.
A. MINIMUM MODE BUS TIMING
1. ADDRESS and ALE
The address/ALE timing relationship is important to
determine the ability to capture a valid address from the
multiplexed bus. Since the 8282 and 8283 latches capture the address on the trailing edge of ALE, the critical
timing involves the state of the address lines when ALE
terminates. If the address valid delay is assumed to be
maximum TCLAV and ALE terminates at its earliest
pOint, TCHLLmin (assuming zero minimum delay), the
address would be valid only TCLCHmin-TCLAVmax= 8
ns prior to ALE termination. This result is unrealistic in
the assumption of maximum TCLAV and minimum
TCH LL. To provide an accurate measure of the true
worst case, a separate parameter specifies the
minimum time for address valid prior to the end of ALE
(TAVAL). TAVAL = TCLCH-60 ns overrides the clock
related timings and guarantees 58 ns of address setup
to ALE termination for a 5 MHz 8086. The address is
guaranteed to remain valid beyond the end of ALE by the
TLLAX parameter. This specification overrides the relationship between TCHLL and TCLAX which might seem
to imply the address may not be valid by the end of the
latest possible ALE. TLLAX holds .for the entire address
bus. The TCLAXmin spec on the address indicates the
earliest the bus will go invalid if not restrained by a slow
ALE. TLLAX and TCLAX apply to the entire multiplexed
bus for both read and write cycles. AD15-0 is three-

stated for read cycles and immediately switched to
write data during write cycles. AD19-16 immediately
switch from address to status for both read and write
cycles. The minimum ALE pulse width is guaranteed by
TLHLLmin which takes precedence over the value obtained by relating TCLLHmax and TCHLLmin.
To determine the worst case delay to valid address on a·
demultiplexed address bus, two paths must be considered: (1) delay of valid address and (2) delay to ALE.
Since the 8282 and 8283 are flow through latches, a valid
address is not transmitted to the address bus until ALE
is active. A comparison of address valid delay TCLAVmax with ALE active delay TCLLHmax indicates TCLAVmax is the worst case. Subtracting the latch propagation delay gives the worst case address bus valid
delay from the start of the bus cycle.
2. Read Cycle Timing
Read timing consists of conditioning the bus, activating
the read command and establishing the data transceiver
enable and direction controls. DT/R is established early
in the bus cycle and requires no further consideration.
During read, the DEN signal must allow the transceivers
to propagate data to the CPU with the appropriate data
setup time and continue to do so until the required data
hold time. The DEN turn on delay allows TCLCL+
TCHCLmin - TCVCTVmax - TDVCL = 127 ns transceiver
enable time prior to valid data required by the CPU.
Since the CPU data hold time TCLDXmin and minimum
DEN turnoff delay TCVCTXmin are both 10 ns relative to
the same clock edge, the hold time is guaranteed. Additionally, DEN must disable the transceivers prior to the
CPU red riving the bus with the address for the next bus
cycle. The maximum DEN turn off delay (TCVCTXmax)
compared with the minimum delay for addresses out of
the 8086 (TCLCL+ TCLAVmin) indicates the transceivers are disabled at least 105 ns before the CPU
drives the address onto the multiplexed bus ..
If memory or I/O devices are connect.ed directly to the
multiplexed address and data bus, the TAZRL parameter
guarantees the CPU will float the bus before activating
read and allowing the selected device to drive the bus.
At the end of the bus cycle, the TRHAV parameter specifies the bus float delay the device being deselected
must satisfy to avoid contention with the CPU driving
the address for the next bus cycle. The next bus cycle
may start as soon as the cycle following T4 or any
number of clock cycles later.
The minimum delay from read active to valid data at the
CPU is 2TCLCL - TCLRLmax - TDVCL = 205 ns. The
minimum pulse width is 2TCLCL- 75 ns = 325 ns. This
specification (TRLRH) overrides the result which could
be derived from clock relative delays (2TCLCL":
TCLRLmax+ TCLRHmin).
3. Write Cycle Timing
The write cycle involves providing write data to the
system, generating the write command and controlling
data bus transceivers. The transceiver direction control
signal DT/R is conditioned to transmit at the end of each
read cycle and does not change during a write cycle.

3-314

230792-001

AP-67
This allows the transceiver enable signal DEN to be ac·
tive early in the cycle (while addresses are valid) without
corrupting the address on the multiplexed bus. The
write data and write command are both enabled from the
leading edge of T2. Comparing minimum WR active
delay TCVCTVmin with the maximum write data delay
TCLDV indicates that write data may be not valid until
100 ns after write is active. The devices in the system
should capture data on the trailing edge of the write
command rather than the leading edge to guarantee
valid data. The data from the 8086 is valid a minimum of
2TCLCL - TCLDVmax + TCVCTXmin = 300 ns before the
trailing edge of write. The minimum write pulse width is
TWLWH= 2TCLCL- 60 ns= 340 ns. The CPU maintains
valid write data TWHDX ns after write. The TWHDZ spec·
ification overrides the result derived by relaling
TCLCHmin and TCHDZmin which implies write data
may only be valid 18 ns afterWR. The 8086 floats the bus
after write only if being forced off tfle bus by a HOLD or

RQ input. Otherwise, the CPU simply switches the out·
put drivers from data to address at the beginning of the
next bus cycle. As with the read cycle, the next bus cy·
cle may start in the clock cycle following T4 or any clock
cycle later.
DEN is disabled a minimum of TCLCHmin +
TCVCTXmin - TCVCTXmax = 18 ns after write to
guarantee data hold time to the selected device. Since
we are again evaluating a minimum TCVCTX with a max·
imum TCVCTX, the real minimum delay from the end of
write to transceiver disable is approximately 60 ns.
4. Interrupt Acknowledge Timing
The interrupt acknowledge sequence consists of two in·
terrupt acknowledge bus cycles as previously de·
scribed. The detailed timing of each cycle is identical to
the read cycle timing with two exceptions: command
timing and address/data bus timing.

He'
h=C~
T,

T,

T3

eLK (8284 OUTPUn

vfc
-

TCHCTV

I--

MilO

Tw

I
r",

r-----TCLCL--TCH1CH2VCHv----\

T,

-~

r--TCLCH~

TCHCL

I\.
--TCLDV

relAV--

TCLLH---

-J

, - lTcLA;:

f

TCHDX ---

57-53

SKE, A19-A1

-T~LAX

TL1L-=:

r-I

ALE

r--

TCHLL-I
~TAVAl-

RDY (8284 INPUT)

r--

SEE NOTE 4

:n~~

---

_TR1VCl

~~~\\~ ~~~~ ~~~\\\ ~

r-- TCLRIX

+RYLCL ------

- h

READY (8086 INPUT)

1
TCLAV~

-

1

r--

TAVAL

t--

-

--TCHRYX

-

:=TRYHCHl

-

TLLAX-

r-

A15-Ao
TAZRL~

READ CYCLE

NOTE 1

-=y--rCHCTV

TDVCL ___ -TCLDX--

j-TCLAX

f{
J.

TCLRL

I

(WR, INTA=VOH)

DTIR
TCVCTV-

Figure 3F1. 8086 Bus Timing -

3-315

DATA IN

{

TCLRH--

1 FLOA~--J'
1---1 r- TRHAV
~

TRlRH

I

TCVCTX -

TCHCTV

-/

Minimum Mode System

230792-001

AP-67

CLK (8284 OUTPUT)

M/ili

ALE

WRITE CYCLE
NOTE 1

(i'iii, iN'fA,
DTfll=vOH)

TCVCTX-

FLOAT

INTACYCLE
NOTES 1

DTIR

"3

Ri5',

TCVCTV-

W'R=VOH

I!m=VOL)

SOFTWARE HALT - (DEN =
VOL; RD, ViR, TN'TA. DT/Fi =VOH; AD1S-ADO
TI'S FOLLOW n, THEN NMI OR INTR
BEGIN A NEW n.
INVALID ADDRESS

AD1S- AD o
TCLAV
NOTES:

1. ALL SIGNALS SWITCH BETWEEN VOH AND VOl UNLESS OTHERWISE
SPECIFIED.
2. ROY IS SAMPLED NEAR THE END OF T2, T3, TW TO DETERMINE IF Tw
MACHINES STATES ARE TO BE INSERTED.
3. BOTH INTA CYCLES RUN BACK·TO·BACK. THE 8088 LOCAL ADDRJDATA BUS IS
FLOATING DURING THE SECOND INTA CYCLE. CONTROL SIGNALS SHOWN
FOR SECOND INTA CYCLE.
4. SIGNALS AT 8284 ARE SHOWN FOR REFERENCE ONLY.
5. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE
NOTED.

Figure 3Fl. 8086 Bus Timing -

Minimum Mode System (Con't)

I
3-316

230792-001

AP-61

r----TCLCLCLK

VCHr--...

..J

VCL

TCLAV-

r\

~-

:JHCr~ ~n!--TCLCH_

TCHCL

X

I---

-

TCHSV

-TCLSH

'1;/1;; /j/I

s"s"s, (EXCEPT HALT)
~

tTCLAV
TCLAX-

TCLLH~

ALE (8288 OUTPUT)
SEE NOTES

1

~

J

-

\

SEE NOTE 8

~CLOV

-----

'------

TCHoX~

iHE, A19-A16
TSVLH

,

57-53

{TCHLL

'

I

----

~ -'fu~~~~~~ ~~~~~
!-Tr1VCL

~

ROY (8284 INPUT)

r--

'

TRYLCl __

TYHSH~t

TCLAV~

READ CYCLE

f

Ro
TCHDTL-I

--

TRYHCH-

...

-TCLAZ

I-

~
TAZRL- -

- r---------

I

f('

-TCHRYX

-

ToVCL- -TCLoX-

FL~~
TRHAV

TCLRH

i'\

TCLRL
TRLRH

TCLMH-

8288 OUTPUTS
SEE NOTES 5,6
TCVNV-

It-

¥
TCVNX--

Figure 3F2a. 8086 Bus Timing -

~

DATA IN

./'

-

TCLML--

f-

A

TCHoTH

\

-

Maximum Mode System (Using 8288)

3-317

230792-001

AP-67

T,

T,
TW

CLK
VCL

\

Si."!i.SO (EXCEPT HALn
WRITE CYCLE

\._---

TCHDXDATA

TCVNX-DEN

TCLMH8288 OUTPUTS

seE NOTES 5,6

MWfC OR iO'WC

INTACYCLE
AD1S-ADo
seE NOTES 3 • 4

FLOAT
TC OX

FLOAT
TSYMCH

I

r--

MCEI

i'li£N

TCHDTH

DTtR

..... 0lITPIJTS
seE NOTES 5,6

DEN
TCVNX

Ao,,-ADo

INVAUD AOORE118
TCLAV

~
/r-----~\------'--._ _ _ _..J.
\. _____ _

NOTES: 1. ALL SIGNALS SWITCH BETWEEN VOH AND VOL UNLESS OTHERWISE

SPECIFIED.
2. ROY IS SAMPLED NEAR THE END OF T2. T3J Tw TO DETERMINE IF Tw
MACHINES STATES ARE TO BE INSERTED.
3. CABCADE ADDRE118 IS VAUD BElWEEN FIRBT AND SECOND INTA CYCLES.
4. BOTH INTA CYCLES RUN BACK·T().BACK. THE 8088 LOCAL ADDRIDATA BUS IS
FLOATING DURING THE SECOND INTA CYCLE. CONTROL FOR POINTER ADDRE118
IS SHOWN FOR SECOND INTA CYCLE.
5. SIGNALS AT 8284 OR 8211 ARE SHOWN FOR REFERENCE ONLY.
I. THE ISSUANCE OF THE 8211 COMMAND AND CONTROL SIGNALS (IIImC,
1iW'Ill, AII\'Vl:, \mm, ll!Wl:, liIOW1i, 1IITl AND DEN) LAGS THE ACTIVE HIGH
82IICEN.
7. ALL TIMING MEASUREMENTS ARE MADE AT 1.IV UNLESS OTHERWISE
NOTED•
•• STATUS INACTIVE IN STATE JUST PRIOR TO T4.

Figure 3F2b. 8086 Bus Timing -

Maximum Mode System (Using 8286) (Con'l)

3-318

230792-001

AP-67
The multiplexed address/data bus floats from the beginning (T1) of the INTA cycle (within TCLAZ ns). The upper
four multiplexed address/status lines do not three-state.
The address value on A19-A16 is indeterminate but the
status information will be valid (S3 = 0, 84 = 0, S5 = IF,
S6 = 0, S7 = BHE = 0). The multiplexed address/data
lines will remain in three-state until the cycle after T4 of
the INTA cycle. This sequence occurs for each of the
INTA bus cycles. The interrupt type number read by the
8086 on the second INTA bus cycle must satisfy the
same setup and hold times required for data during a
read cycle.

normally ready, devices not requiring wait states do
nothing to RDY while devices n~eding wait states
should disable RDY via the address decode and use a
combination of address decode and command to activate a delay to re-enable RDY.

The DEN and DT/R signals are enabled for each I NTA cycle and do not remain active between the two cycles.
Their timing for each cycle is identical to the read cycle.

6. Other Considerations

ThelNTA command has the same timing as the write
command. It is active within 110 ns of the start of T2 providing 260 ns of access time from command to data
valid at the 8086. The command is active a minimum of
TCVCTXmin = 10 ns into T4 to satisfy the data hold time
of the 8086. ThiS provides minimum INTA pulse width of
300 ns, however taking signal delay tracking into consideration gives a minimum pulse width of 340 ns. Since
the maximum inactive delay of INTA is TCVCTXmax=
110 ns and the CPU will not drive the bus until 15 ns
(TCLAVmin) into the next clock cycle, 105 ns are available for interrupt devices on the local bus to float their
outputs. If the data bus is buffered, DEN provides the
same amount of time for local bus transceivers to threestate their outputs.
5. Ready Timing
The detailed timing requirements of the 8086 ready
signal and the system ready signal into the 8284 are
described in Section 3D. The system ready Signal is
typically generated from either the address decode of
the selected device or the address decode and the command (RD, WR, INTA). For a system which is normally
not ready, the time to generate ready from a valid address and not insert a wait state, is 2TCLCLTCLAVmax - TR1 VCLmax = 255 ns. This time is available for buffer delays and address decoding to determine if the selected device does not require a wait state
and drive the RDY line high. If wait cycles are required,
the user hardware must provide the appropriate ready
delay. Since the address will not change until the next
ALE, the RDY will remain valid throughout the'cycle. If
the system is normally ready, selected devices requiring
wait states also have 255 ns to disable the RDY line. The
user circuitry must delay re-enabling RDY by the appropriate number of wait states.

o

If the RD command is used to enable the RDY Signal,
TCLCL- TCLRLmax- TRIVCLmax= 15 ns are available
for external logic. If the WR command is used, TCLCLTCVCTVmax - TRIVCLmax = 55 ns are available. Comparison of RDY control by address or command indicates that address decoding provides the best timing.
If the system is normally not ready, address decode
alone could be used to provide RDY for devices not requiring wait states while devices requiring wait states
may use a combination of address decode and command to activate a wait state generator. If the system is

If the system requires no wait states for memory and a
fixed number of wait states for RD and WR to all I/O
devices, the M/iO signal can be used as an early indication of the need for wait cycles. This allows a common
circuit to control ready timing for the entire system
without feedback of address decodes.

Detailed HOLD/HLDA timing is covered in the next section and is not examined here. One last signal consideration needs to be mentioned for the minimum
mode system. The TEST input is sampled' by the 8086
only during execution of the WAIT instruction. The TEST
signal should be active for a minimum of 6 clock cycles
during the WAIT instruction to guarantee detection.
B. MAXIMUM MODE BUS TIMING
The maximum mode 8086 bus operations are logically
equivalent to the minimum mode operation. Detailed
timing analysis now involves signals generated by the
CPU and the 8288 bus controller. The 8288 also provides
additional control and command Signals which expand
the flexibility of the system.
1. ADDRESS and ALE
In the maximum mode, the address information continues to come from the CPU while the ALE strobe is
generated by the 8288. To determine the worst case relationships between ALE and the address, we first must
determine 8288 ALE activation relative to the SO-52
status from the CPU. The maximum mode timing
diagram specifies two possible delay paths to generate
ALE. The first is TCHSV + TSVLH measured from the rising edge of the clock cycle preceding T1. The second
path is TCLLH measured from the start of T1. Since the
8288 initiates a bus cycle from the status lines leaving
the passive state (SO-52 = 1), if the 8086 is late in issuing
the status (TCHSVmax) while the clock high time is a
minimum (TCHCLmin), the status will not have changed
by the start of T1 and ALE is issued TSVLH ns after the
status changes. If the status changes prior to the beginning of T1, the 8288 will not issue the ALE until TCLLH
ns after the start of T1. The resulting worst case delay to
enable ALE (relative to the start of T1) is TCHSVmax +
TSVLHmax - TCHCLmin = 58 ns. Note, when calculating signal relationships, be sure to use the proper
maximum mode values rather than equivalent minimum
mode values.

3-319

The trailing edge of ALE is triggered in the 8288 by the
positive clock edge in T1 regardless of the delay to
enable ALE. The resulting minimum ALE pulse width is
TCLCHmax - 58 ns = 75 ns assuming TCHLL = O.
TCLCHmax must be used since TCHCLmin was assumed to derive the 58 ns ALE enable delay. The address is guaranteed to be valid TCLCHmin +
TCHLLmin - TCLAVmax= 8 ns prior to the trailing edge

230792-001

AP-67
of ALE to capture the address in the 8282 or 8283
latches. Again we have assumed a very conservative
TCHLL = O. Note, since the address and ALE are driven
by separate devices, no tracking of A.C. characteristics
can be assumed.
The address hold time to the latches is guaranteed by
the address remaining valid until the end of T1 while
ALE is disabled a maximum of '15 ns' from the positive
clock transition in T1 (TCHCLmin - TCHLLmax = 52 ns
address hold time). The multiplexed bus transitions
from address to status and write data or three·state (for
read) are identical to the minimum mode timing. Also,
since the address valid delay (TCLAV) remains the
critical path in establishing a valid address, the address
access times to valid data and ready are the same as the
minimum mode system.
2. Read Cycle Timing
The maximum mode system offers read signals
generated by both the 8086 and the 8288. The 8086 RD
output signal timing is identical to the minimum mode
system. Since the A.C. characteristics of the read com·
mands generated by the 8288 are significantly better
than the 8086 output, access to devices on the demultiplexed buffered system bus should use the 8288 commands. The 8086 RD signal is available for devices
which reside directly on the multiplexed bus. The
following evaluations for read, write and interrupt
acknowledge only consider the 8288 command timing.
The 8288 provides separate memory and 1/0 read signals
which conform to the same A.C. characteristics_ The
commands are issued TCLML ns after the start of T2
and terminate TCLMH ns after the start of T4. The
minimum command length is 2TCLCL- TCLMLmax+
TCLMLmin = 375 ns. The access time to valid data at the
CPU is 2TCLCL-TCLMLmax-TDVCLmax=335 ns.
Since the 8288 was designed for systems with buffered
data busses, the commands are enabled before the CPU
has three-stated the multiplexed bus and should not be
used with devices which reside directly on the multiplexed bus (to do 50 could result in bus contention during 8086 bus float and device turn-on).

3. Write Cycle Timing
I n the maximum mode, the 8288 provides normal and advanced write commands for memory and 1/0. The advanced write commands are active a full clock cycle
ahead of the normal write commands and have timing
identical to the read commands. The advanced write
pulse width is 2TCLCL- TCLMLmax+ TCLMHmin=375
ns while the normal write pulse width is TCLCLTCLMLmax + TCLMHmin = 175 ns. Write data setup
time to the selected device is a function of either the
data valid delay from the 8086 (TCLDV) or the transceiver
enable delay TCVNV. The worst case delay to valid write
data is TCLDV= 110 ns minus transceiver propagation
delays. This implies the data may not be valid until 100
ns after the advanced write command but will be valid
approximately TCLCL- TCLDVmax + TCLMLmin = 100
ns prior to the leading edge of the normal write command. Data will be valid 2TCLCL- TCLDVmax+
TCLMHmin = 300 ns before the trailing edge of either
write command. The data and command overlap for the
advanced command is 300 ns while the overlap with the
normal write command is 175 ns. The transceivers are
disabled a minimum of TCLCHmin - TCLMHmax +
TCVNXmin = 85 ns after the write command while the
CPU provides valid data a minimum of TCLCHminTCLMHmax + TCHDZmin = 85 ns. This guarantees write
data hold of 85 ns after the write command. The transceivers are disabled TCLCL - TCVNXmax +
TCHDTLmin = 155 ns (assuming TCHDTL= 0) prior to
transceiver direction change for a subsequent read
cycle.
4. Interrupt Acknowledge Timing

The direction control for data bus transceivers is estab,
lished in T1 while the transceivers are not enabled by
DEN until the positive clock transition of T2. This provides TCLCH + TCVNVmin = 123 ns for 8086 bus float
delay and TCHCLmin+TCLCL-TCVNVmaxTDVCLmax = 187 ns of transceiver active to data valid at
the CPU. Since both DEN and command are valid a minimum of 10 ns into T4, the CPU data hold time TCLDX is
guaranteed_ A maximum DEN disable of 45 ns (TCVNX
max) guarantees the transceivers are disabled by the
start of the next 8086 bus cycle (215 ns minimum from
the same clock edge)_ On the positive clock transition of
T4, DT/R is returned to transmit in preparation for a
possible write operation on the next bus cycle. Since
the system memory and 110 devices reside on a buffered
system bus, they must three-state their outputs before
the device for the next bus cycle is selected (approximately 2TCLCL) or the transceivers drive write data onto
the bus (approximately 2TCLCL).

The maximum mode INTA sequence is logically identical to the minimum mode sequence. The transceiver
control (DEN and DT/R) and INTA command timing of
each interrupt acknowledge cycle is identical to the
read cycle. As in the minimum mode system, the multiplexed addressldata bus will float from the leading edge
of T1 for each INTA bus cycle and not be driven by the
CPU until after T4 of each INTA cycle. The setup and
hold times on the vector number for the second cycle
are the same as data setup and hold for the read. If the
device providing the interrupt vector number is connected to the local bus, TCLCL - TCLAZmax +
TCLMLmin = 130 ns are available from 8086 bus float to
INTA command active. The selected device"on the local
bus must disable the system data bus transceivers
since DEN is still generated by the 8288.
If the 8288 is not in the lOB (1/0 Bus) mode, the 8288
MCE/PDEN output becomes the MCE output. This output is active during each INTA cycle and overlaps the
ALE signal during T1. The MCE is available for gating
cascade addresses from a master 8259A onto three of
the upper AD15-AD8 lines and allowing ALE to latch the
cascade address into the address latches. The address
lines may then be used to provide CAS address selection to slave 8259A's located on the system bus (reference Figure 3E5). MCE is active within 15 ns of status or
the start of T1 for each INTA cycle. MCE should not
enable the CAS lines onto the multiplexed bus during
the first cycle since the CPU does not guarantee to float

3-320

230792-001

AP-67
the bus until 80 ns into the first INTA cycle. The first
MCE can be inhibited by gating MCE with LOCK. The
8086 LOCK output is activated during T2 of the first
cycle and disabled during T2 of the second cycle. The
overlap of LOCK with MCE allows the first MCE to be
masked and the second MCE to gate the cascade address onto the local bus. Since the 8259A will not pro·
vide a cascade address until the second cycle, no information is lost. As with ALE, MCE is guaranteed valid
within 58 ns of the start of T1 to allow 75 ns CAS address setup to the trailing edge of ALE. MCE remains
active TCHCLmin - TCHLLmax + TCLMCLmin = 52 ns
after ALE to provide data hold time to the latches.
If the 8288 is strapped in the lOB mode, the MCE output
becomes PDEN and all 1/0 references are assumed to be
devices on the local bus rather than the demultiplexed
system bus. Since INTA cycles are considered 1/0
cycles, all interrupts are assumed to come from the
local system and cascade addresses are not gated onto
the system address bus. Additionally, the DEN signal is
not enabled since no 1/0 transfers occur on the system
bus. If the local 1/0 bus is also buffered by transceivers,
the PDEN signal is used to enable those transceivers.
PDEN A.C. characteristics are identical to DEN with
PDEN enabled for 1/0 references and DEN enabled for
instruction or memory data references.

ments are identical to those stated for the minimum
mode.
To inform the 8288 of HALT status when a HALT instruc·
tion is executed, the 8086 will initiate a status transition
from passive to HALT status. The status change will
cause the 8288 to emit an ALE pulse with an indeterminate address. Since no bus cycle is initiated (no com·
mand is issued), the results of this address will not af·
fect CPU operation (Le., no response such as READY is
expected from the system). This allows external hard·
ware to latch and decode all transitions in system
status.
3G. Bus Control Transfer (HOLD/HLDA and RQ/GT)

The 8086 supports protocols for transferring control of
the local bus between itself and other devices capable
of acting as bus masters. The minimum mode config·
uration offers a signal level handshake similar to the
8080 and 8085 systems. The maximum mode provides
an enhanced pulse sequence protocol designed to optimize utilization of CPU pins while extending the
system configurations to two prioritized levels of alter·
nate bus masters. These protocols are simply tech·
niques for arbitration of control of the CPU's local bus
and should not be confused with the need for arbitration
of a system bus .

•

5. Ready Timing
Ready timing based on address valid timing is the same
for maximum and minimum mode systems. The delay
from 8288 command valid to RDY valid at the 8284 is
TCLCL- TCLMLmax- TRIVCLmin= 130 ns. This time is
available for external circuits to determine the need to
insert wait states and disable RDY or enable RDY to
avoid wait states. INTA, all read commands and advanced write commands provide this timing. The normal
write command is not valid until after the RDY signal
must be valid. Since both normal and advanced write
commands are generated by the 8288 for all write
cycles, the advanced write may be used to generate a
RDY indication even though the selected device uses
the normal write command.
Since sepa~te commands are provided for memory and
1/0, no MilO signal is specifically available as in the
minimum mode to allow an early 'wait state required' in·
dication for 1/0 devices. The S2 status line, however is
logically equivalent to the MilO signal and can be used
for this purpose.
6. Other Considerations
The RQ/GT timing is covered in the next section and will
not be duplicated here. The only additional signals to be
considered in the maximum mode are the queue status
lines QSO, QS1. These signals are changed on the
leading edge of each clock cycle (high to low transition)
including idle and wait cycles (the queue status is in·
dependent of the bus activity). External logic may sam·
pie the lines on the low to high transition of each clock
cycle. When sampled, the signals indicate the queue ac·
tivity in the previous clock cycle and therefore lag the
CPU's activity by one cycle. The TEST input require·

3-321

1. MINIMUM MODE
The minimum mode 8086 system uses a hold request input (HOLD) to the CPU and a hold acknowledge (HLDA)
output from the CPU. To gain control of the bus, a
device must assert HOLD to the CPU and wait for the
HLDA before driving the bus. When the 8086 can relin·
quish the bus, it floats the RD, WR, INTA and M/iO command lines, the DEN and DT/Rbus control lines and the
multiplexed addressldata/status lines. The ALE signal is
not three-stated. The CPU acknowledges the request
with HLDA to allow the requestor to take control of the
bus. The request6r must maintain the HOLD request ac·
tive until it no longer requires the bus. The HOLD request to the 8086 directly affects the bus interface unit
and only indirectly affects the execution unit. The CPU
will continue to execute from its internal queue until
either more instructions are needed or an operand
transfer is required. This allows a high degree of overlap
between CPU and auxiliary bus master operation. When
the requestor drops the HOLD signal, the 8086 will respond by dropping HLDA. The CPU will not re·drive the
bus, command and control signals from three-state until
it needs to perform a bus transfer. Since the 8086 may
still be executing from its internal queue when HOLD
drops, there may exist a period of time during which no
device is driving the bus. To prevent the command lines
from drifting below the minimum VIH level during the
transition of bus control, 22K ohm pull up resistors
should be connected to the bus command lines. The
timing diagram in Figure 3G1 shows the handshake se·
quence and 8086 timing to sample HOLD, float the bus,
and enableldisable HLDA relative to the CPU clock.
To guarantee valid system operation, the designer must
assure that the requesting device does not assert con-

230792-001

AP-67
trol of the bus prior to the 8086 relinquishing control and
that the device relinquishes control of the bus prior to
the 8086 driving the bus. The HOLD request Into the
8086 must be stable THVCH ns prior to the CPU's low to
high clock transition. Since this Input is not synchronized by the CPU, signals driving the HOLD input
should be synchronized with the CPU clock to
guarantee the setup time is not violated. Either clock
edge may be used. The maximum delay between HLDA
and the 8086 floating the bus is TCLAZmaxTCLHAVmin = 70 ns. If the system 'cannot tolerate the
70 ns overlap, HLDA active from the 8086 should be
delayed to the device. The minimum delay for the CPU to
drive the control bus from HOLD inactive is THVCHmln
+ 3TCLCL= 635 ns and THVCHmin + 3TCLCL+
TCHCL = 701 ns to drive, the multiplexed bus. If the
device does not satisfy these requirements, HOLD inactive to the 8086 should be delayed. The delay from HLDA
inactive to driving the busses Is TCLCL + TCLCHmlnTCLHAVmax = 158 ns for the cont1'ol bus and 2TCLCLTCLHAVmax = 240 ns for the data bus.
,1.1 Latency of HLOA to HOLD
The decision to respond to a HOLD request is made In
the bus interface unit. The major factors that Influence
the decision are the current bus activity, the state of the
LOCK signal Internal to the CPU (activated by the software LOCK prefix) and Interrupts.
If the LOCK is not active, an interrupt acknowledge cycle Is not in progress and the BIU (Bus Interface Unit) is
executing a T4'orTI when the HOLD request Is received,
the minimum latency to HUlA Is:

35 ns
65 ns
200 ns
10 ns

THVCH min (Hold setup)
TCHCL min
TCLCL (bus float delay)
TCLHAV min (HLDA delay)

310 ns

@

5 MHz

The maximum delay under these conditions is:
34 ns
200 ns
82 ns
200 ns
'160 ns

Oust missed setup time)
delay to next sample
TCHCL max
TCLCL (bus float delay)
TCLHAV max (HLDA delay)

677 ns

@

5MHz

If the BIU just Initiated a bus cycle when the HOLD Request was receiveq, the worst case response time is:
34 ns
82 ns
7*200
N*200
160 ns

THVCH Oust missed)
TCHCL max
bus cycle execution
N walt states/bus cycle
TCLHAV max (HLDA delay)

1.676/As

@

5 MHz, no wait states

Note, the 200 ns delay for just missing is included in the
delay for bus cycle execution. If the operand transfer is
,a word transfer to an odd byte boundary, two bus cycles
are executed to perform the transfer. The BIU will not
acknowledge' a HOLD request between the two bus
cycles. This type of transfer would extend the above
maximum latency by four additional clocks plus N additional wait states. With no wait states in the bus cycle,
the maximum would be 2.476 microseconds.
Although the minimum mode 8086 does not have a hardware LOCK output, the software LOCK prefix may stili
be Included In the Instruction stream. The CPU Internally reacts to the LOCK prefix as would the maximum
mode 8086. Therefore, the LOCK does not allow a HOLD
request to be honored until completion of the Instruction following the prefix. This allows an instruction
which performs, more ,than one memory reference (ex.
ADD [BX], CX; which adds CX to [BXD to execute without
another bus master gaining control of the bus between
memory references. Since the LOCK signal is active for
one clock longer than the instruction execution, the
maximum latency to HLDA is:

elK

HOLD

CONTROL

HlDA _ _ _ _..J

Figure 3C1. HOLD/HLDA Sequence

3-322

230792-001

AP-67
34 ns
200 ns
82 ns
(M+ 1)'200 ns
200 ns
160 ns

THVCH (just miss)
delay to next sample
TCHCL max
LOCK instruction execution
set up HLDA (internal)
TCLHAV max (HLDA delay)

(M'200 ns)+ 876 ns

@

A typical use of the HOLD/HLDA signals in the minimum
mode 8086 system is bus control exchange with DMA
devices like the Intel 8257-5 or 8237 DMA controllers.
Figure 3G2 gives a general interconnect for this type of
configuration using the 8237-2. The DMA controller
resides on the upper half of the 8086's local bus and
shares the A8-A 15 demultiplexing address latch of the
8086. All registers in the 8237-2 must be assigned odd
addresses to allow initialization and interrogation by the
CPU over the upper half of the data bus. The 8086
RD/WR commands must be demultiplexed to provide
separate 1/0 and memory commands which are compatible with the 8237-2 commands. The AEN control from
the 8237-2 must disable the 8086 commands from the
command bus, disable the address latches from the
lower (AO-A7) and upper (A19-A16) address bus and
select the 8237-2 address strobe (ADSTB) to the A8-A15
address latch. If the data bus is buffered, a pull-up
resistor on the DEN line will keep the buffers disabled.
The DMA controller will only transfer bytes between

5 MHz

If the HOLD request is made at the beginning of an interrupt acknowledge sequence, the maximum latency to
HLDA is:
34 ns
82 ns
2600 ns
160 ns

THVCH (just missed)
TCHCL max
13 clock cycles for INTA
TCLHAV max

2.876 fls

@ 5 MHz

1.2 Minimum Mode DMA Configuration
Vee

T

DEMULTIPLEX
MIN MODE COMMANDS

rD~

I

8284

I

L

I

T

RDIWRIIO/M
BHE
A19-18
8086
READY
CLK
RESET
HOLD

ALE

-

AD150

HLDA

-

EJiIAB[E

8282

_01

00

STB

-r

T

~
=

DOr-

UPPER
DMA
ADDR -

>0-

01

-

8282

110 PORT
LOADED DURING
8237 INITIALIZATION

-

I

LOCAL DATA
BUS

--s2ii2

74LS74
Q
CLR

l~LD

,--

COMMAND

BUS

01

~

00

STB

-

AD7·0

--s2ii2
_01
STB

00

EN

~
-

(AO)

-

0670
AEN
ADSTB

·'1 --

lOR
lOW

8237·2

MOO

HLDA

HRQ CLK

r

4

MEMW

rESET

Figure 3G2. DMA Using the 8237·2

3-323

230792-001

l

memory and 1/0 and requires the 1/0 devices to reside on
an 8·bit bus derived from the 16·blt to 8·bit bus multiplex
circuit given in Section 4. Address lines /!t.7·AO are driven
directly by the 8237 and BHE is generat"ed by inverting
AO.lf A19·A16 are used, they must be provided by an ad·
ditlonal port with either a fixed value or initialized by
software and enabled ont9 the address bus by AEN.
Figure 3G3 gives an Interconnection for placing' the
8257 on the system bus. By using a separate latch to
hold the upper address from the 8257·5 and connecting
the outputs to the address bus as shown, 16·bit DMA
transfers are provided. In this configuration, AEN
simultaneously enables AO and BHE to allow word
transfers. AEN still disables the CPU interface to the
command and address busses.
2. MAXIMUM MODE (RQ/GT)
The maximum mode 8086 configuration supports a sig·
nlficantly different protocol for transferring bus control.
When viewed with respect to the HOLD/HLDA sequence
of the minimum mode, the protocol appears difficult to
i"1plement externally. However, it is necessary to under·
stand the intent of the protocol and its purpose within
the system architecture.

2.1 Shared System Bus (RQ/GT Altemative)
The maximum mode RQ/GT sequence is intended to
transfer control of the CPU local bus between the CPU
and alternate bus masters which reside totally on the
local bus and share the complete CPU interface to the
system bus. The complete interface Includes the ad·
dress latches, data transceivers, 8288 bus controller and
8289 multi master bus arbiter. If the alternate bus'
masters In the system do not reside directly on the 8086
local bus, system bus arbitration is required rather than
local CPU bus arbitration. To satisfy the need for multi·
mallter system bus arbitration at Elach CPU's system in·
terface, the 8289 bus arbiter should be used rather than
.
the CPU RQ/GT logic.
To allow a device, with a simple HOLD/HLDA protocol to
gain control ot a single CPU system bus, the circuit in
Figure 3G4 could be used. The design Is effectively a
simple bus arbiter which isolates the CPU from the
system bus when an alternate bus master Issues a
HOLD request. The output of the Circuit, Ai:N (Address
ENable), disables the 8288 and 8284 when the 8086 in·
dicates idle status (SO,81 ,82 1), LOCK is not active and
a HOLD request is active. With AEN Inactive, the 8288
three·states the command outputs and disables DEN

=

8282
A1916

ALE

01

A19-11

DO

A,.

STB

BtiE

BHE

OE

cpu"
BUS
INTERFACE

8282
AD1S-8

01

A15-9

DO
A,

STB
(jI[

8282

AD7.o

01

A7·1

DO
STB

OE

DTfR

'------'

Ao TO GROUND AND
r-±:-----..",:l-~=-+__:J......, UPPER BITS OF DMA ADDRESS
(FIXED OR REG)
HOLD . . .- - - - - - !
HLDA-------I~I

CONTROLS ARE SAME AS 8-BIT
TRANSFER CONFIGURATION WITH
MANIPULATION OF THE DATA BUS

Figura 303. 8086 Min System, 8257 on System Bus 16-Blt Transfers

3-324

230792-001

AP-67
which three-states the data bus transceivers. AEN must
also three-state the address latch (8282 or 8283) outputs.
These actions remove the 8086 from the system bus and
allow the requesting device to drive the system bus. The
AEN signal to the 8284 disables the ready input and
forclls a bus cycle initiated by the 8086 to wait until the
8086 regains control of the system bus. The CPU may
actively drive its local bus during this interval.

A circuit configuration for an 8257-5 using this technique to interface with a maximum mode 8086 can be
derived from Figure 3G3. The 8257-5 has its own address
latch for buffering the address lines A15-A8 and uses its
AEN output to enable the latch onto the address bus.
The maximum latency from HOLD to HLDA for this circuit is dependent on the state of the system when the
HOLD is issued. For an idle system the maximum delay
is the propagation delay through the nand gate and RlS
flip-flop (TQ1) plus 2TCLCL plus TCLCHmax plus propagation delay of the 74LS74 and 74LS02 (TD2). For a
locked instruction it becomes: TD1 + TD2 + (M + 2)
*TCLCL+ TCLCHmax where M is the number of clocks
required for execution of the locked instruction. For the
interrupt acknowledge cycle the latency is
TD1 + TD2+ 9 *TCLCL+ TCLCHmax.

The requesting device will not gain control of the bus
during an 8086 initiated bus cycle, a locked instruction
or an interrupt acknowledge cycle. The LOCK signal
from the 8086 is active between INTA cycles to
guarantee the CPU maintains control of the bus. Unlike
the minimum mode 8086 HOLD response, this arbitration circuit allows the requestor to gain control of the
bus between consecutive bus cycles which tran,sfer a
word operand on an odd address boundary and are not
locked. Depending on the characteristics of the requesting device, any of the 74LS74 outputs can be used
to generate a HLDA to the device_

2.2 Shared Local Bus (RQ/GT Usage)

Upon completion of its bus operations, the alternate bus
master must relinquish control of the system bus and
drop the HOLD request. After AEN goes inactive, the address latches and data transceivers are enabled but, if a
CPU initiated bus cycle is pending, the 8288 will not
drive the command bus until a minimum of 105 ns or
maximum of 275'ns later. If the system is normally not
ready, the 8284 AEN input may immediately be enabled
with ready returning to the CPU when the selected
device completes the transfer. If the system is normally
ready, the 8284 AEN input must be delay~d long enough
to provide access time equivalent to a normal bus cycle.
The 74LS74 latches in the design provide a minimum of
TCLCHrnin for the alternate device to float the system
bus after releasing HOLD. They also provide 2TCLCL ns
address access and 2TCLCL- TAEVCHmax ns (8288
command enable delay) command access prior to enabling 8284 ready detection. If HLDA is generated as
_shown in Figure 3G4, TCLCL ns are available for the
8086 to release the bus prior to issuing HLDA while
HLDA is dropped almost immediately upon loss of
HOLD.

The RQ/GT protocol was developed to allow up to two i nstruction set extension processors (co-processors) or
other special function processors (like the 8089 I/O
processor in local mode) to reside directly on the 8086
local bus. Each RQ/GT pin of the 8086 supports the full
protocol for exchange of bus control (Fig. 3G5). The sequence consists of a request from the alternate bus
master to gain control of the system bus, a grant from
the CPU to indicate the bus has been relinquished and a
release pulse from the alternate master when done. The
two RQ/GT pins (RQ/GTO and RQ/GT1) are prioritized
with RQ/GTO having the highest priority. The prioritization only occurs if requests have been received on both
pins before a response has be,en given to either. For ex,
ample, if a request is received on RQ/GT1 followed by a
request on RQ/GTO prior to a grant on RQ/GT1, RQ/GTO
will gain priority over RQ/GT1. However, if RQ/GT1 had
already received a grant, a request on RQ/GTO must wait
until a release pulse is received on RQ/GT1.
The request/grant sequence interaction with the bus interface unit is similar to HOLD/HLDA. The CPU continues to execute until a bus transfer for additional instructions or data is required. If the release pulse is

+5

. - - - - - - - - - - - - - - - A f N (TO 8288 & 828213'.)

So
S,

slOCK

HOLD

AEN' (TO 8284)

+5
ClK
HLDA

Figure 3G4. Circuit to Translate HOLD into AEN Disable for Max Mode 8086

3-325

230792-001

Ap·67
received before the CPU needs the bus, it will not drive
the bus until a transfer is required.
Upon receipt of a request pulse, the 8086 floats the
multiplexed address, data and status bus, the SO, 51,
and 52 status lines, the LOCK pin and' RD. This action
does not disable the 8288 command outputs from driving the command bus and does not disable the address
latches from driving the address bus. The 8288 contains
internal pull-up resistors on the SO, 51, and S2 status
lines to maintain the passive state while the 8086 outputs are three-state. The passive state prevents the 8288
from initiating any commands or activating DEN to
enable the transceivers butfering the data bus. If the
device issuing the RQ does not use the 8288, it must
disable the 8288 command outputs by disabling the
8288 AEN input. Also, address latches not used by the
requesting device must be disabled.

GND

Vee

AD14

AD15

AD13

A18/S3

AD12

A17/S4

AD11

A18iS5

AD10

A191sa

ADS

BHElS7

ADS

MN/MX

AD7

iiii

ADa

RQlGTO

AD5

ROtori

AD4

LOCK

AD3

S2

AD2

Si

2.3 RQ/GT Operation
Detailed timing of the RQ/GT ,equence Is given In
Figure 3G6. To request a transfer of bus control via the
RQ/aT lines, the device must drive the line low for no
more than one CPU clock Interval to generate a request
pulse. The pulse must be synchronized with the CPU
clock to guarantee the appropriate setup and hold 'times
to the clock edge which samples the RQ/GT lines in the
CPU. After Issuing a request pulse, the device must
begin sampling for a grant pulse with the next low to
high clock, edge. Since the 8086 can respond with a
grant pulse in the clock cycle immediately following the
request, the RQ/GT line may not return to the positive
level between the request and grant pulses. Therefore
edge triggered logic is not valid for capturing a grant
pulse. It also Implies the circuitry which generates the
request pulse must guarantee the request is removed In
time to detect a grant from the CPU. After receiving the
grant pulse, the requesting device may drive the local
bus. Since the 8086 does not float the address and data
bus, LOCK or RD until the high to low clock transition
following the low to high clock transition the requestor
uses to sample for the grant, the requestor should wait
the float delay of the 8086 (TCLAZ) before driving the
local bus. This precaution prevents bus contention durIng the access of bus control by the requestor.
To return control of the bus to the 8086, the alternate
bus master relinquishes bus control and Issues a
release pulse on the same RQ/GT line. The 8086 may
drive the SO-S2 status lines, RD and LOCK, three clock
cycles after detepting the release pulse and the address/data bus TCHCLmln ns (clock high time) after the
status lines. The alternate bus master should be threestated off the local bus and have other 8086 interface
circuits (8288 and address latches) re-enabled within the
8086 delay to regain control of the bus.

AD1

so

ADO

QSO

NMI

QS1

2.4 RQ/GT Latency

INTR

TEST

CLK

READY

GND

RESET

The RQ to GT latency for a single RQ/GT line is similar
to the HOLD to HLDA latency. The cases given for the
minimum mode 8088 also apply to the maximum mode.
For each case the delay from RQ detection by the CPU
to GT detection by the requestor is:
(HOLD to HLDA delay)- (THVCH + TCHCL+ TCLHAV)

Figure 3G5. 8086 RQ/GT Connections

, THIi/lll88FLQAT8AxDx8usiiiiANOiliCii:ONftlI5EDOI!

I THI anti .. IIIIIsnR Fl..DAT&1i.Ii.1i FROM 111 STAT! OM THIS eDGE

:

;::=~RI!=;'f:~HT~:-mH,ANDmmtQNTHISEDIHi
a THEIOIIREDRNUTHEADo;LlNEI

Flg~re

3G6. Request/Grant Sequence

3-326

230792-001

AP-67
This gives a clock cycle maximum delay for an Idle bus
interface. All other cases are the minimum mode result
minus 476 ns. If the 8086 has previously issued a grant
on one of the RQ/GT lines, a request on the other RQ/GT
line will not receive a grant until the first device releases
the interface with a release pulse on its RQ/GT line. The
delay from release on one RQ/GT line to a grant on the
other is typically one clock period as shown in Figure
3G7. Occasionally the delay from a release on RQ/GT1

to a grant on RQ/GTO will take two clock cycles and is a
function of a pending request for transfer of control
from the execution unit. The latency from request to
grant when the interface is under control of a bus
master on the other RQ/GT line is a function of the other
bus master. The protocol embodies no mechanism for
the CPU to force an alternate bus master off the bus. A
watchdog timer should be used to prevent an errant
alternate bus master from 'hanging' the system.

CHANNEL 0 TO 1
CLOCK

RQIGTO

"----I

RELEASE

"----I

RQIGT1

GRANT

CHANNEL 1 TO 0
CLOCK

RO/GT1

RQIGTO

"----I

RELEASE

\ ' -_ _ _ _/

GRANT
OR

\

/

GRANT

Figure 3G7. Channel TranSler Delay

3-327

230792-001

AP-67
2.5 RQ/GT to HOLD/HLDA Conversion

of HLDA, it may be desirable to delay the acknowledge
one clock period. The H LOA is dropped no later than one
clock period after HOLD is disabled. The HLDA also
drops at the beginning of the release pulse to provide
2TCLCL + TCLCH for the requestor to relinquish control
of the status lines and 3TCLCL to float the remaining
signals.

A circuit for tran·slating a HOLD/HLDA hand-shake sequence into a RQ/GT pulse sequence is given in Figure
3G8. After receiving the grant pulse, the HLDA is enabled TCHCLmin ns before the CPU has three-stated the
bus. If the requesting circuit drives the bus within 20 ns

ClOCK--------------------------------------,

A

741578

fr--rH J

74802
Q t-~----~-....,

ClK
ClR

HlDA

a

HOLD

74502

+5

741578

»-t-..,--H J

Q

ClK
K ClR

a

R
74LS04

RE5ET-----------------------------------"
Figure 3G88. HOLD/HLD~iiQIGr Conversion Circuit

88.3 MIN---1

r-

-1

r-44.6MIN

-I

[ . - DATA BUS FLOATS

ClK

HLDR

A

RQ

HLDA

~

--------------------------~I

Figure 3G8b. HOLDIHLDA--C_Q/GT Conversion Timing

3-328

230792-001

AP-67
4. INTERFACING WITH 110
The 8086 is capable of interfacing with 8· and 16·bit 110
devices using either 110 instructions or memory mapped
110. The 110 instructions allow the 110 devices to reside
in a separate 110 address space while memory mapped
110 allows the full power of the Instruction set to be
used for 110 operations. Up to 64K bytes of 110 mapped
110 may be defined in an 8086 system. To the program·
mer, the separate 110 address space is only accessible
with INPUT and OUTPUT commands which transfer data
between 110 devices and the AX (for 16·bit data trans·
fers) or AL (for 8·bit data transfers) register. The first 256
bytes of the 110 space (0 to 255) are directly addressable
by the 110 instructions while the entire 64K is accessible
via register indirect addressing through the OX register.
The later technique is particularly desirable for service
procedures that handle more than one device by allow·
ing the desired device address to be passed to the pro·
cedure as a parameter. 110 devices may be connected to
the local CPU bus or the buffered system bus.

provide full decoding in a single package and allow in·
serting a new PROM to reconfigure the system 110 map
without circuit board or wiring modifications (Fig. 4A2).

ADDRESS
EVEN ADDRESSED

WORD OR BYTE
PERIPHERALS

000 ADDRESSED
BYTe PERIPHERALS

BHe--+-oj
(0)

EVEN ADDRESSED
BYTE PERIPHERALS

4A. Elght·Blt 110
Eight·bit I/O devices may be connected to either the up·
per or lower half of the data bus. Assigning an equal
number of devices to the upper and lower halves of the
bus will distribute the bus loading. If a device is con·
nected to the upper half of the data bus, all 110 ad·
dresses assigned to the device must be odd (AO= 1). If
the device is on the lower half of the bus, its addresses
must be even (AO = 0). The address assignment directs
the eight·bit transfer to the upper (odd byte address) or
lower (even byte address) half of the sixteen·bit data
bus. Since AO will always be·a one or zero for a specific
device, AO cannot be used as an address input to select
registers within a specific device. If a device on the
upper half of the bus and one on the lower half are
assigned addresses that differ only in AO (adjacent odd
and even addresses), AO and SHE must be conditions of
chip select decode to prevent a write to one device from
erroneously performing a write to the other. Several
techniques for generating 110 device chip selects are
given in Figure 4A 1.

000 ADDRESSED
BYTE PERIPHERALS

(b)

(e)

Figure 4A 1. Techniques tor 110 Device Chip Selects

The first technique (a) uses separate 8205's to generate
chip selects for odd and even addressed byte periph·
erals. If a word transfer is performed to an even ad·
dressed device, the adjacent odd addressed I/O device
is also selected. This allows accessing the devices in·
dividually with byte transfers or simultaneously as a
16·bit device with word transfers. Figure 4A1(b) restricts
the chip selects to byte transfers, however a word
transfer to an odd address will cause the 8086 to run two
byte transfers that the decode technique will not detect.
The third technique simply uses a single 8205 to
generate odd and even device selects for byte transfers
and will only select the even addressed eight·bit device
on a word transfer to an even address.
If greater than 256 bytes of the 110 space or memory
mapped 110 is used, additional decoding beyond what is
shown In the examples may be necessary. This can be
done with additional TTL, 8205's or bipolar PROMs (In·
tel's 3605A). The bipolar PROMs are slightly slower than
multiple levels of TTL (50 ns vs 30 to 40 ns for TTL) but

10

CSl
CS2
Au
A,
380.
A,
A·l
A,
A,
A,

Ao

0,

n

0, 12
02 13

01 14

A.

1.

Ao 16
A,

17

Figure 4A2. Bipolar PROM Decodor

One last technique for interfacing with eight·blt periph·
erals is considered in Figure 4A3. The sixteen·bit data
bus is multiplexed onto an eight·bit bus to accom·
modate byte oriented DMA or block transfers to memory
mapped eight·bit 110. Devices connected to this inter·
face may be assigned a sequence of odd and even ad·
dresses rather than all odd or even.

3-329

230792-001

AP-67

74L802

74LS368

lOR
iffi -~=+=L)o-----t;><>--

~--r.~--------~

A...J'--__J\ a·Blt

I~BIT I

PERIPHERAL
DATA BUS

D:~~ 1 ~-L.LJ\
(L__

DEFINED

EN~:~: _______________+--...J

BHE

PERIPHERAL
CS

NOTE: IF IT IS NOT NECESSARY TO THREE·STATE THE COMMAND LINES, A
DECODER (8205 OR 745138) COULD BE USED. THE 74LS257 IS NOT
RECOMMENDED SINCE THE OUTPUTS MAY EXPERIENCE VOLTAGE
SPIKES WHEN ENTERING OR LEAVING THREE·STATE.

..
Figure 4A3. 16· 10 8·Bil Bus Conversion

4B. Sixteen· Bit 110
For obvious reasons of efficient bus utilization and /lim·
plicity of device selection, sixteen·bit 110 devices should
be assigned even addresses. To guarantee the device Is
selecte:! only for word operations, AO and BHE should
be conditions of chip select code (Fig. 4B1).

ADDRESS

-----'hI

"0·2

"0

-----+-01 E;

lIfE

E;
E3

Figure 4Cl. Decoding Memory and 11.0 lUi and WR Commands lor
Minimum Mode 8086 Syslems

Linear select techniques (Fig. 4C2) for 110 devices can
only be used with devices that either reside in the 1/0 ad·
dress space or require more than one active chip select
(at least one low active and one high active). Devices
with a single chip select input cannot use linear select If
they are memory mapped. This is due to the assignment
of memory address space FFFFFOH·FFFFFFH to reset
startup and memory space 00000H·003FFH to interrupt
vectors.

O.
8205

1

EVEN ADDRESSED
WORD PERIPHERALS

07

(al SEPARATE 110 COMMANDS
Figure 4B1. Sixleen·BilllO Decode

4C. General Design Considerations

ADDRESSI{]S
LINES)
(j!
;1115
1115
110 DEVICE

MINIMAX, MEMORY 110 MAPPED AND LINEAR SELECT
Since the minimum mode 8086 has common read and
write commands for memory and 1/0, if the memory and
1/0 address spaces overlap, the chip selects must be
qualified by MilO to determine which address space the
devices are assigned to. This restriction on chip select
decoding can be removed if the 1/0· and memory ad·
dresses in the system do not overlap and are properly
decoded; all 1/0 is memory mapped; or RD, WR and M/iO
are decoded to provide separate memory and 1/0
readlwrite commands (Fig. 4C1). The 8288 bus controller
in the maximum mode 8086 system generates separate
1/0 and mernory comma[1ds in place of a M/iO signal. An
1/0 device is assigned to the 1/0 space or memory space
(memory mapped 1/0) by connection of either 1/0· or
memory command lines to the command inputs of the
device. To allow overlap of the memory and 1/0 address
space, the device must not respond to chip select alone
but must require a combination of chip select and a read
or write command.

W1\

W1\

(b) MULTIPLE CHIP SELECTS

Figure 4C2. Linear Selecllor 110

4D.

Determf~lng 1/0 Device Compatibility

This section presents a set of A.C. characteristics which
represent the timing of the asynchronous bus interface
of the 8086. The equations are expressed in terms of the
CPU clock (when applicable) and are derived for
minimum and maximum modes of the 8086. They repre·
sent the bus characteristics at the CPU.
The results can be used to determine 1/0 device reo
quirements for operation on a single CPU local bus or
buffered system bus. These values are. not applicable to

3-330

230792-001

AP-67
a Multibus system bus interface. The requirements for a
Multibus system DUS are available in the Multibus interface specification.
A list of bus parameters, their definition and how they
relate to the A.C. characteristics of Intel peripherals are
given in Table 401. Cycle dependent values of the
parameters are given in Table 402. For each equation, if
more than one signal path is involved, the equation
reflects the worst case path.

the relaxed device requirements for even a large complex configuration. The analysis assumes all components are exhibiting the specified worst case parameter values and are under the corresponding temperature, voltage and capacitive load conditions. If the
capacitive loading on the 8282/83 or 8286/87 is less than
the maximum, graphs of delay vs. capacitive loading in
the respective data sheets should be used to determine
the appropriate delay values.

ex. TAVRL(address valid before read active) =
(1) Address from CPU to RO active
(or)
(2) ALE (to enable the address through the
address latches) to RO active

TABLE 402. CYCLE DEPENDENT PARAMETER REQUIREMENTS
FOR PERIPHERALS
(8) Minimum Mode
TAVRL= TCLCL+ TCLRLmln- TCLAVmax= TCLCL-100
TRHAX= TCLCL- TCLRHmax+ TCLLHmln=TCLCL-150
TRLRH =2TCLCL- 60= 2TCLCL- 60
TRLDV = 2TCLCL- TCLRLmax - TOVCLmin = 2TCLCL - '195
TRHOZ= TRHAVmin = 155 ns
TAVDV= 3TCLCL- TDVCLmln- TCLAVmax= 3TCLCL-140
TRLRL = 4TCLCL = 4TCLCL
TAVWL= TCLCL+ TCVCTVmin- TCLAVmax=TCLCL-100
TWHAX= TCLCL+ TCLLHmln- TCVCTXmax= TCLCL-110
TWLWH = 2TCLCL- 40= 2TCLCL- 40
TOVWH = 2TCLCL+ TCVCTXmin- TCLOVmax= 2TCLCL-100
TWHOX = TWHDZmln = 89
TWLCL= 4TCLCL= 4TCLCL
TWHOXB=TCLCHmln+(- TCVCTXmax+ TCVCTXmln)=
TCLCHmin - 50

The worst case delay path is (1).
For the maximum mode 8086 configurations, TAVWLA,
TWLWHA and TWLCLA are relative to the advanced
write signal while TAVWL, TWLWH and TWLCL are
relative to the normal write signal.
,TABLE 401. PARAMETERS FOR PERIPHERAL COMPATIBILITY
TAVRL - Address stable before RO leading edge
TRHAX - Address hold after RO trailing edge
TRLRH

~

Read pulse width

TRLOV - Read to data valid delay
TRHOZ - Read trailing edge to data floating
TAVOV - Address to valid data delay
TRLRL - Read cycle time
TAVWL- Address valid before write leading edge
TAVWLA - Address valid before advanced wnte
TWHAX - Address hold after write trailing edge
TWLWH - Wnte pulse width
TWLWHA - Advanced write pulse width
TOVWH - Data set up to write trailing edge
TWHDX - Data hold from write trailing edge
TWLCL - Write recovery time
TWLCLA - Advanced write recovery time

TSVRL - Chip select stable before RO leading edge
TRHSX - Chip select hold after RO trailing edge
TSLDV -

Chip select to data valid delay

TSVWL - Chip select stable before WR leading edge
TWHSX - Chip select hold after WR trailing edge
TSVWLA - Chip select stable before advanced write

(TAR)
(TRA)
(TRR)
(TRO)

Note Delays relative to chip select are a function of the chip select
decode technique used and are equal to· equivalent delay
from address- chip select decode delay.

(TO F)

(TAD)
(TRCYC)
(TAW)
(TAW)
(TWA)
(TWW)
(TWW)

(b) Maximum Mode
TAVRL= TCLCL+ TCLMLmin- TCLAVmax = TCLCL-100
TRHAX= TCLCL- TCLMHmax + TCLLHmin = TCLCL- 40
TRLRH = 2TCLCL- TCLMLmax + TCLMHmln= 2TCLCL- 25
TRLOV = 2TCLCL - TCLMLmax - TDVCLmln = 2TCLCL - 65
TRHOZ= TRHAVmin = 155
TAVOV= 3TCLCL- TOVCLmln- TCLAVmax= 3TCLCL-140
TRLRL= 4TCLCL= 4TCLCL
TAVWLA= TAVRL= TCLCL-100
TAVWL= TAVRL+ TCLCL= 2TCLCL-100
TWHAX = TRHAX = TCLCL - 40
TWLWHA= TRLRH = 2TCLCL- 25
TWLWH = TRLRH - TCLCL= TCLCL- 25
TOVWH =2TCLCL+ TCLMHmln - TCLDVmax= 2TCLCL-100
TWHOX = TCLCHmln - TCLMHmax + TCHOZmln = TCLCHmln - 30
TWLCL= 3TCLCL= 3T~LCL
TWLCLA = 4TCLCL= 4TCLCL

(TOW)

(TWO)
(TRV)
(TRV)
(TAR)
(TRA)
(TRO)
(TAW)
(TWA)
(TAW)

Symbols In parentheses are equivalent parameters specified for
Intel penpherals

In the given list of equations, TWHOXB is the data hold
time from the trailing edge of write for the minimum
mode with a buffered data bus. For this equation,
TCVCTX cannot be a minimum for data hold and a maximum for write inactive. The maximum difference is 50
ns giving the result TCLCH-50. If the reader wishes to
verify the equations or derive others, refer to Section 3F
for assistance with interpreting the 8086 bus timing
diagrams.

TABLE 403. COMPATIBLE PERIPHERALS (5 MHz 8086)
Configuration

Minimum Mode

8251A
8253·5
8255A·5
8257·5
8259A
8271
8273
8275
8279·5
8041A"
8741A
8291

Figure 401 shows four representative configurations
and the compatible Intel peripherals (including wait
states if required) for e'ach configuration are given in
Table 403. Configuration 1 and 2 are minimum mode
demultiplexed bus 8086 systems without (1) and with (2)
data bus transceivers. Configurations 3 and 4 are maximum mode systems with one (3) and two (4) levels of address and data buffering. The last configuration is
characteristic of a multi-board system with bus buffers
on each board. The 5 MHz parameter values for these
configurations are given in Table 404 and ~emonstrate

Maximum Mode

Unbuffered

Buffered

Buffered

Fully Buffered

v

1W
1W
1W
1W

v
v

v
v

""

""v
""v

v

v
v
v
v
v
v
v
v
"..

v

v
1W
1W
1W
1W
1W
1W
v

""v
v
v
v

v

v""

v
v
v

v

"..

""

"..

"Includes other Intel peripherals based on the 8041A (I.e., 8292, 8294,
8295)
",.. Implies full operation with no walt states
W implies the number of walt states reqUired

3-331

230792-001

AP-67
Peripheral compatibility is determined from the equations given for the CPU by modifying them to account
for additional delays from address latches and data
transceivers in the configuration. Once the system configuration is selected, the system requirements can be
determined at the peripheral interface and used to
evaluate compatibility of the peripheral to the system.
During this process, two areas must be considered.
First, cah the device operate at maximum bus bandwidth and if not, how many wait states are required. Second, are there any problems that cannot be resolved by
wait states.

TABLE 404. PERIPHERAL REQUIREMENTS FOR.FULL SPEED"
OPERATION WITH 5 MHz 8086

Configuration

Minimum Mode
TAVRL
TRHAX
TRLRH
TRLDV
lRHDZ
TAVDV
TRLRL
TAVWL
TAVWLA
TWHAX
TWLWH
TWLWHA
TDVWH
TWHDX
TWLCL
TWLCLA
TSVRL
TRHSX
TSLDV
TSVWL
TWHSX
TSVWLA
-

Unbuffered

Buffered

70
57
340
205
155
430
800
70

72
27
320
150
158
400
770
72

-

-

97
360

67
340

-

-

300
88
800

339
15
772

52
50
412
52
90

54
50
382
54
90

-

-

-

-

Maximum Mode

Buffe.',td
70
169
375
305
382
400
800
270
70
169
175
375
·270
95
600
800
52
171
382
252
171
52

Fully Buffered
58
141
347
261
360
372
772
258

Examples of the first are TRLRH (read pulse width) and
TRLDV (read access or RD active to output data valid).
Consider address access time (valid address to valid
data) for the maximum mode fully buffered configuration.

58
141
147
347
258
13
572
772
40
143
354
240
143
40

TAVDV = 3TCYC - 140 ns - address latch delay
address buffer delay - chip seleot decode delay - 2
transceiver delays
Assuming inverting latches, buffers and transceivers with 22 ns max delays (8283, 8287) and a
bipolar PROM decode with 50 ns delay, the result
is:

Not applicable.

TAVDV=322 ns @ 5 MHz

8.

MINIMUM MODE

b MINIMUM MODE BUFFERED DATA AND COMMAND BUSSES

Figure 401. 8086 System Configurations

3-332

230792-001

AP-67

c MAXIMUM MODE BUFFERED DATA BUS
elK

8284

NOTE FOR OPTIMUM PERFORMANCE WITH INTEL PERIPHERALS,
WRITE) SHOULD BE USED

AiOW (ADVANCED

d MAXIMUM MODE DOUBLE BUFFERED SYSTEM

8284

Figure 401. 8086 System Configurations (Con't)

The result gives the address to data valid delay required
at the peripheral (in this configuration) to satisfy zero
wait state CPU access time. If the maximum delay
specified for the peripheral is less than the result, this
parameter is compatible with zero wait state CPU opera·
tion. If not, wait states must be inserted until TAVDV + n
* TCYC (n is the number of wait states) is greater than
the peripherals maximum delay. If several parameters
require wait states, either the largest number required
should always be used or different transfer cycles can
insert the maximum number required for that cycle.
The second area of concern includes TAVRL (address
set up to read) and TWHDX (data hold after write).
Incompatibilities in this area cannot be resolved by the
insertion of wait states and may require either addi·

3-333

tional hardware, slowing down the CPU (if the parameter
is related to the clock) or not using the device.
As an example consider address valid prior to advanced
write low (TAVWLA) for the maximum mode fully buf·
fered system.
TAVWLA = TCYC - 100 ns - address latch delay address buffer delay - chip select decode delay +
write buffer delay (minimum)
Assuming inverting latches and buffers with 22 ns
delay (8283, 8287) and an 8205 address decoder with
18 ns delay
TAVWLA=38 ns which is the time a 5 MHz 8086
system provides

230792-001

AP-67
4E. 1/0 Examples
1. Consider an Interrupt driven procedure for handling
multiple communication lines. On receiving an interrupt
from one of the lines, the Invoked procedure polls the
lines (reading the status of each) to determine which
line to service. The procedure does not enable lines but'
simply services input and output requests until the
associated output buffer is empty (for output requests)
or until an Input line is terminated (for the example only'
EOT Is considered). On detection of the terminate condl·
tlon, the routine will disable the line. It is 'assumed that
other routines will fill a lines output buffer and enable
the device to request output or empty the input buffer
and enable the device to Input additional characters.
The routine begins operation by loadfng CX with a count
of the number of lines In the system and OX with the I/O
address of the first line. The 1/0 addresses are assigned
as shown In Figure 4E1 with 8251A's as the 1/0 devices.
The status of each line Is read to determine if it needs
service. If yes, the appropriate routine Is called to input
or output a character. After servicing the line or if no
service Is needed, CX Is decremented and OX is incremented to test the next line. After all lines have been
tested and serviced, the routine terminates. If all interrupts from the lines are OR'd together, only one interrupt is used for all lines. If tM Interrupt Is input to the
CPU through an 8259A interrupt controller, the 8259A
should be programmed in the level triggered mode to
guarantee all line Interrupts are serviced.
To service either an Input or output request, the called
routine transfers OX to ax, and shifts ax to form the offset for this device into the table of input or output buffers. The first entry in the buffer is an index to the next
character position in the buffer and Is loaded into the 81
register. By specifying the base address of the table of

buffers as a displacement Into the data segment, the
base + index + displacement addressing mode allows
direct access to the appropriate memory location. 8086
code for part of this example Is shown in Figure 4E2.
2. As a second example, consider using memory
mapped I/O and the 8086 string prlmative instructions to
perform block transfers between memory and I/O. By
assigning a block of the memory' address space
(equivalent in size to the maximum block to be transferred to the I/O device) and decoding this address
space to generate the 1/0 device's chip select, the block
transfer capability Is easily implemented. Figure 4E3
gives an interconnect for 16-bit I/O devices while Figure
4E4 Incorporates the 16-blt bus to 8-blt bus multiplexing
scheme to support 8-bit 1/0 devices. A code example to
perform such a''transfer Is shown In Figure 4E5.
; THts CODE DEMONSTRATES TESTING DEVICE
; STATUS FOR SERVICE, CONSTRUCTING THE
; APPROPRIATE UNE BUFFER ADDRESS FOR INPUT
• AND OUTPUT AND SERVICING AN INPUT
; REQUEST
CHECK_STATUS:

MASK EOU OFFFDH
INPUT AL, OX

AH.AL
AH. READ_OfLWRITLSTATUS

JZ
CALL

NEXT-'O

TEST
JZ
CALL

WHlrLSERVICE.
NEXT_IO.

READ
AH, WRITE STATUS

JZ
CALL
DEC

NEXLJO
WRITE
CX
EXIT
DX.MASK
DX. 3
DX._
CHECLSTATUS
DX.MASJ<
BH,DL
BH
BH
BL, BL

AND

MOV
INC
SHR
XOR
RET
READ'

ADDRESS
AH. READ STATUS
WRITILSEHVICE

TEST

JNC
AND
ADD
OR
JMP
ADDRESS'

; GET 8261A STATUS.

MOV
TEST

; TEST IF DONE.
; YES. RESTORE. RETURN.
; REMOVE A1 AND
i INCREMENT ADDRESS.

; SELECT STATUS FOR
; NEXT INPUT.
; SELECT DATA.
; CONSTRUCT BUFFER
; DISPLACEMENT FOR

; THJS DEVICE.

; ax IS THE DISPLACEMENT.
; READ CHARACTER.

INPUT AL. DX

; GET CHARACTER POINTER.
MOV 81, READJUFFERS [BlCI
MOV READ_BUFFERS [IX + sq, AL ; STORE CHARACTER.
; INCR CHARACTER POJNTER.
INC READJUFFERS [BlCI
i END OF TRANSMISSION?

CMPAL,EOT
JNZ CONT_READ
CALL DISABLE READ
CONT_READ: RET

; YES. DISABLE RECEIVER.
; SEND MESSAGE THAT INPUT
; IS READY.

Figure 4E2.

015-8

\r-------------,
1/0 CHIP SELECT

D,,,, ,,__

":;><:--_ _ _ _---:::""'""_ _- ,

BIPOLAR
PROM

lS·
BIT
1/0
DEVICES ARE CONNECTED TO THE UPPER AND
LOWER HALVES OF THE DATA BUS,
ADDRESS

o
1

2
3
4
5

8
7
ETC.

TRANSFER 256 BYTE BLOCKS TO THE 1/0 DEVICE
DEVICE 0
DEVICE 1
DEVICE 0

DATA
DATA
CONTROUSTATUS

DEVICE 1

CONTROUSTATUS

DEVICE
DEVICE
DEVICE
DEVICE

DATA
DATA
CONTROUSTATUS
CONTROUSTATUS

2
3
2
3

Figure 4El. Dev[ce Assignment

THE ADDRESS SPACE ASSIGNED TO THE 1/0 DEVICE IS

A,.

FROM
THRU

t.- BASE
i+-BASE

ADDRESS

ADDRESS

=*=
8

A7

0',
1',

~

MEMORY DATA NEED NOT BE ALIGNED TO EVEN ADDRESS BOUNDARIES
1/0 TRANSFERS MUST BE WORD TRANSFERS TO EVEN ADDRESS BOUNDARIES

Figure 4E3. Block Transf.r 10 16·BIII/O Using 8086 Siring Primallves

3-334

230792-001

AP-67

A198'-_ _ _----,

number the device can accept, leaving the remaining address lines for chip enable/select decoding. To connect
the devices directly to the multiplexed bus, they must
have output enables. The output enable is also
necessary to avoid bus contention in other configurations. Figure 5A1 shows the bus connections for ROM
and EPROM memories. No special decode techniques
are required for generating chip enables/selects. Each
valid decode selects one device on the upper and lower
halves of bus to allow byte and word access. Byte access is achieved by reading the full word onto the bus
with the 8086 only accepting the desired byte. For the
minimum mode 8086, if RD, WR and M/iO are not decoded to form separate commands for memory and I/O, and
the I/O space overlaps the memory space assigned to
the EPROM/ROM then M/iO (high active) must be a condition of chip enable/select decode. The output enable
is controlled by the system memory read signal.

3605
A·1
CHIP SELECT

0158 \,-,--_ _, /

CS
8·BIT
DATA

1/0

DEVICE

_+----'1 )

HIGH

BAN~E(~-----------,

ADDRESS ASSIGNMENT SAME AS PREVIOUS EXAMPLE. 16·BIT BUS IS
MULTIPLEXED ONTO AN 8·BIT PERIPHERAL BUS.
ADDRESS _ _ _ _ _- ,

Figure 4E4. Block Transfer 10 8·Bit I/O Using 8086 Siring Primalives

; DEFINE THE 1/0 ADDRESS SPACE
1/0 SEGMENT
ORG BLOCK_ADDRESS
I/O_BLOCK, OW 128 DUP (?)
1/0 ENDS

CONTROL
DATA

; ASSUME THE DATA IS FROM THE CURRENT
; DATA SEGMENT
CLD
; OF = FORWARD
LES 01, I/O_BLOCKJDDRESS ; 1/0 BLOCK ADDRESS
; CONTAINS THE ADDRESS
; OF 110 BLOCK
MOV CX, BLOCLLENGTH
MOV SI, SOURCEJDDRESS
MOVS 110 BLOCK
; PERFORM WORD TRANSFERS
; END CODE EXAMPLE

SEL:;~~~~

_ _ _ _ _ _ _ _ _~

NOTE THE CODE IS CAPABLE OF PERFORMING BYTE TRANSFERS BY
CHANGING THE 110 BLOCK DEFINITION FROM 128 WORD TO 256 BYTES

Figure 5.1. 8086 Memory Array

Figure 4ES. Code for Block Transfers

5. INTERFACING WITH MEMORIES

CHIP SELECT

Figure 5.1 is a general block diagram of an 8086
memory. The basic characteristics of the diagram are
the partitioning of the 16-bit word memory into high and
low 8-bit banks on the upper and lower halves of the
data bus and inclusion of BHE and AD in the selection of
the banks. Specific implementations depend on the type
of memory and the system configuratiorf.

0815

----.,....----ct CE
\r---,----.-i

A112 _ _ _ _"

iiO----H

SA. ROM and EPROM
The easiest devices to interface to the system are ROM
and EPROM. Their byte format provides a simple bus interface and since they are read only devices, AO and
BHE need not be included in their chip enable/select
decoding (chip enable is similar to chip select but additionally determines if the device is in active or standby
power mode). The address lines connected to the
devices start with A1 and continue up to the maximum

3-335

00-1

r -_ _- r_ _ _- l 00.7

'----OICE

NOTe Ao AND SHE ARE NOT USED.

Figure SAl. EPROMIROM Bus Inlerface

230792-001

AP-67
Static ROM's and EPROM's have only four parameters
to evaluate when determining their compatibility to the
system. The parameters, equations and evaluation tech'niques given in the I/O section are also applicable to
these devices. The relationship of parameters is given in
Table 5A1. TACC and TCE are related to the same equation and differ only by the delay associated with the chip
, enable/select decoder. As an example, consider a 2716
EPROM memory residing on the multiplexed bus of a
minimum mode configuration:

devices with single chip selects and no output enables
(2114, 2141, 2147). Figure 5B3 gives selection techniques for devices with chip selects and output enables.

cs

TACC = 3TCLCL-140- address bufferdelay= 430 ns
(8282 = 30 ns max delay)

cs
0,

TCE = TACC - decoder delay = 412 ns
(8205 decoder delay= 18 ns)

ADDRESS

0,

WR--~

TOE = 2TCLCL - 195 = 205 ns

00

TDF= =155ns

0,

TABLE SAl. EPROM/ROM PARAMETERS
TOE - Output Enable to Valid Data'" TRLDV
TACC - Address to Valid Data'" TAVDV
TCE - Chip Enable to Valid Data'" TSLDV
TDF - Output Enable High to Output Float'" TRHDZ

Figure SB1. Incorrect Connection of 2142 Acros. Byte Boundarle.

The first group requires inclusion of AO and BHE: to
decode or enable the chip selects. Since these
memories do not have output enables, read and write
are used as enabies for chip select generation to prevent bus contention. If read and write are not used to
enable the chip selects, devices with common input/out·
put pins (like the 2114) will be subjected to severe bus
contention between chip select and write active. For
devices with separate input/output lines (like 2141,
2147), the outputs can be externally buffered with the
buffer enable controlled by read. This solution will only
allow bus contention between memory devices In the array during chip select transition periods. These techniques are considered in more detail in Section 2C.

The results are the times the system configuration requires of the component for full speed compatibility
with the system. Comparing these times with 2716
parameter limits indicates the 2716-2 will work with no
wait states while the 2716 will require one walt state.
Table 5A2 demonstrates EPROM/ROM compatibility for
the configurations presented in the I/O section. Before
designing a ROM or EPROM memory system, refer to
AP-30 for additional information on design techniques
that give the system an upgrade path from 16K'to 32K
and 64K devices.
TABLE 5A2.

COMPA~IBLE

EPROM/ROM (5 MHz 8086)

Configuration
Minimum Mode

2716·1
2716·2
2732
2332
2364

..

Unbuffered

Buffered

Buffered

Fully Buffered

1W

1W
1W

1W
1W

1W
1W

....
....

.
...

For devices with output enables (2142), write may be
gated with BHE and AO to provide upper and lower bank
write strobes. This simplifies chip select decoding by
eliminating BHE and AO as a condition of decode.
Although both devices are selected during a byte write
operation, only ~>ne will receive a write strobe. No bus
contention will exist during the write since a read command must be issued to enable the memory output
drivers.
.

Maximum Mode

...

.
...

58. Static RAM
Interfacing static RAM to the system introduces several
new requirements to the memory design. AO and BHE
must be included in the chip select/chip enable
decoding of the devices and write timing must be considered In the compatibility analysis.
For each device, the data bus connections must be
restricted to either the upper or lower half of the data
bus. Devices like the 2114 or 2142 must not straddle the'
upper and lower halves of the data bus (Fig. 5B1). To
allow selecting 'either the upper byte, lower byte or full
16-bit word for a write operation, BHE must be a condition of decode for selecting the upper byte and AO must
be a condition of decode for selecting the lower byte.
Figure 5B2 gives several selection techniques for

If multiple chip selects are available at the device, SHE
and AO may directly control device selection. This
allows normal chip select decoding of the address
space and direct connection of the read and write com·
mands to the devices. Alternately, the multiple chip
select Inputs of the device could directly decode the ad·
dress space (linear select) and be combined with the
separate write strobe technique to minimize the control
circuitry needed to generate chip selects.
As with the EPROM's and ROM's, if separate commands
are not provided for memory and I/O in the minimum
mod.e 8086 and the address spaces overlap, M/iO (high
active) must be a condition of chip select decode. Also,
the address lines connected to the memory devices
must start with A 1 rather than AO.

3-336

230792-001

Ap...67

2142's

ADDRESS '--_ _ _ _,
A1Q-1 _ _ _ _ _ _ _---,

Ao-----"1

LOW BANK'

RD-----------~

CHIP SELeCTS

"o---.....- - - - - q CSbS2
18)
(a) HIGH AND LOW BANK WRITE STROBES

ADDR '---,.--r-,/

LOW BANK
CHIP SELECT

2142's

A10.1-----------·\

HIGH BANK

CHIP SELECT

iiii----~--__,

WR-------,-,

Ao--------------

AO-------~

BHE---------(~b)~--"

0",.

SHE----......~
Ao-----l~

iiii

CHIP SELECTS

iiilE------t------ Minimum Mode
TW=TWLWH=2TCLCL-60=340 ns
TWR = TCLCL- TCVCTXmax + TCLLHmln = 90 ns
TOW = 2TCLCL - TCLDVmax + TCVCTXmin = 300 ns
TDH=TWHDX=88 ns
TAW=3TCLCL- TCLAVmax+ TCVCTXmin .. SOO ns
TCW = TAW - Chip Select Decode
TASW = TCLCL- TCLAVmax+ TCVCTXmln = 100 ns
(b) Maximum Mode
TW = TCLCL- TCLMLmax + TCLMHmin= 175 ns
TWR = TCLCL - TCLMHmax + TCLLHmin = 165 ns
TDW=TW= 175 ns
TDH=TCLCHm,n- TCLMHmax+ TCHDXmin=93 ns
TAW=3TCLCL- TCLAVmax+ TCLMHmln=SOO ns
TCW=TAW-Chip Select Decode
TASW=2TCLCL-TCLAVmax+ TCLMLmln=3OO ns
TWA'=TW+ TCLCL=375 ns
TDWA'=2TCLCL- TCLDVmax+ TCLMHmln=300 ns
TASWA' = TASW- TCLCL= 100 ns
• Relative to Advanced Write,

Comparing these results with the 2142 family Indicates
the standard 2142 write timing is fully compatible with
this 8086 configuration. Read timing analysis is also
necessary to completely determine compatibility of the
devices.

sc.

Dynamic RAM

Dynamic RAM Is perhaps the most complex device to
design Into a system. To relieve the engineer of most of
this burden, Intel provides the 8202 dynamic RAM con·
troller as part of the 8086 family of peripheral devices.
This section will discuss using the 8202 with the 8086 to
build a dynamic memory system for an 8086 system. For

Figure 5B4. Sample Configuration lor Compatibility Analysis Example

S.C.1 Standard 8086·8202 Interconnect
Figure 5.C.1.1 shows a standard Interconnection for an
8202 into an 8086 system. The configuration accom·
modates 64K words (128K bytes) of dynamic RAM ad·
dressabje as words or bytes. To access the RAM, the
8086 Initiates a bus cycle with an address that selects
the 8202 (via PCS) and the appropriate transfer com·
mand (MRDC or MWTC). If the 8202 is not performing a
refresh cycle, the access starts Immediately, otherwise,
the 8086 must wait for completion of the refresh. XACK
from the 8202 Is conn'ected to the 8284 ROY input to
force the CPU to walt until the RAM cycle Is completed
before the CPU can terminate the bus cycle. This effec·
tlvely synchronizes the asynchronous events of refresh
and CPU bus cycles: The normal write command
(MWTC) is used rather than the advanced command
(AMWC) to guarantee the data Is valid at the dynamic
RAMS before the write command is issued. The gating
of WE" with AO and BFiE provides selective write strobes
to the upper and lower banks of memory to allow byte
and word write operations. The logic which generates
the strobe for the data latches allows read data to prop·
agate to the system as soon as the data Is available and
latches the data on the trailing edge of CAS.
DETAILED TIMING
Read Cycle
For no walt state operation, the 8086 requires data to be
valid from MRDC in:
2TCLCL- TCLML- TDVCL- buffer delays = 291 ns.
Since the 8202 Is CAS access limited, we need only ex·
amine CAs access time. The 8202/2118 guarantees data
valid from 8202 RD low to be:
(tph + 3tp +'100 ns) 8202 TCC delay + TCAC for the 2118

3-338

230792-001

J

AP-67

uyc
BHE

I
I

..

HIGH BYTE

WRITE

8287

XCEIVER

2118

Figure SCI.I. S MHz 808618202/128K Byte System than 64K byles are used)

Double Data, Control and Address Buffering (Note: Bus driver on 8202 Is not needed if less

For a 25 MHz 8202 and 2118-3, we get 297 ns which is insufficient for no walt state operation. If only 64K bytes
are accessed, the 8202 requires only (tph + 3tp + 85 ns)
giving 282 ns access and no walt states required. Refer
to Figure 5.C.l.2 and 5C.l.3 for timing information on
the 8202 and 2118.
Write Cycle
An important consideration for dynamic RAM write
cycles is to guarantee data to the RAM is valid when
both CAS and WE are active. For the 2118, if WE is valid
prior to CAS, the data setup Is to CAS and if CAS is valid
before WE (as would occur during a read modify write
cycle) the data setup time is to WE. For the 8202, the WR
to CAS delay Is analyzed to determine the data setup
time to CAS inherently provided by the 8202 command
to RAS/CAS timing. The minimum delay from WR to
CAS is:
TCCmin = tph + 2tp + 25 = 127 ns

@

25 MHz

Subtracting buffer delays and data setup at the 2118,
we have 83 ns to generate valid data after the write
command is issued by th$ CPU (in this case the 8288).
Since the 8086 will not guarantee valid data until
TCLAVmax-TCLMLmin=100 ns from the advanced

3-339

write signal, the normal write signal is used. The normal
write MWTC guarantees data is valid 100 ns before it is
active. The worst case write pulse width is approximately 175 ns which is sufficient for all 2118's.
Synchronization
To force the 8086 to wait during refresh the XACK or
SACK lines must be returned to the 8284 ready input.
The maximum delay from RO to SACK (if the 8202 is not
performing refresh) is TAC = tp + 40 80 ns. To prevent
a walt state at the 8086, ROY must be valid at the 8284
TCLCHmin - TCLMLmax - TR1VCLmax = 48 ns after
the command is active. This implies that under worst
case conditions, one wait state will be inserted for every
read cycle. Since MWTC does not occur until one clock
later, -two wait states may be inserted for writes.

=

The XACK from command delay will assert ROY TCC +
TCX = (tph + 3tp + 100)+ (5tp + 20) = 460 ns after the
command. This will tYPically insert one or two wait
states.
Unless 2118-3's are used in 64K byte or less memories,
SACK must not be used since it does not guarantee a
wait state. From the previous access time analysis we
saw that other configurations required a wait state.

230792-001

AP-67

IpH

XlCLK

---.

RDORWR

lac

~,P-

-----,\

~leA

r---------------------L __

I

IeHs-;----

lAP

Iec

,

S

-

AO·A

.... ~ I-'..A

11---

1Aeo

t

-

,

1'--

IRO_
IRSH

'(rELAY I
ONLYj

"

I

•
-

-,

lRAH

1-\
ROW

f-J

ADDR

t.-

X

-I

COL

ADDR

leAH
lAse

l-

,

S
!-leA--! _ _ _ _ _ _ _ _
K

\

.1
-

ICAS

-

,------------,

\

tACK-

I

-

WE \WE-VOH
FOR A RD eye LE)

Iww

r----------'j

f

-I

IeKj,"eH

I-

I-

>CAeK
lex

r

£
Ixw-J

.

ICWH

IwC,.s

I-

Figure SC1.2. 8202 Timing Information

3-340

230792-001

AP-67
A.C. CHARACTERISTICS
TA =

Measurements made with respect to RAS,- RAS 4 , CAS,
WE, OUTo- OUT6 are at 2.4V and 0.8V. All other pins are
measured at 1.5V.

o·c to 70·C, VCC= 5V ± 10%
CL= 30 pF
CL= 320 pF
CL=230pF
CL=450 pF
CL=640 pF

Loading:

64 Devices

Symbol

Parameter

tp

Clock (Internal/External) Period (See Note 1)

tAC

Memory Cycle Time

Min

Max

40

54

Units

ns

10 tp- 30

12 tp

ns

tAAH

Row Address Hold Time

tp-10

ns

tASA

Row Address Setup Time

tpH

ns

tCAH

Column Address Hold Time

5 tp

ns

tASC

Column Address Setup Time

tp-35

ns

tACO

RAS to CAS Delay Time

twcs

WE Setup to CAS

2 tp- 10

2 tp+45

ns

tp-40

ns

tASH

RAS Hold Time

5 tp-30

ns

tCAS

CAS Pulse Width

5 tp-30

ns

tRP

RAS Precharge Time (See Note 2)

4 tp-30

ns

tWCH

WE Hold Time to CAS

5 tp-35

ns

tREF

Internally G~nerated Refresh to Refresh Time
64 Cycle
128 Cycle

548 tp
264 tp

576 tp
288 tp

ns
ns
ns

tCR

RD, WR to RAS Delay

tpH+ 30

tpH + tp+ 75

tcc

RD, WR to CAS Delay

tpH+2tp+25

tpH + 3 tp+ 100

ns

tRFR

REFRQ to RAS Delay

1.5 tp+ 30

2.5 tp+ 100

ns

tAS

Ao-A,s to RD, WR Setup Time (See Note 4)

tCA

RD, WR to SACK leading Edge

tCK

RD, WR to XACK, SACK Trailing Edge Delay

tKCH

RD, WR Inactive Hold to SACK Trailing Edge

10

tsc

RD, WR, PCS to X/ClK Setup Time (See Note 3)

15

tcx

CAS to XACK Time

tACK

XACK leading Edge to CAS Trailing Edge Time

txw

XACK Pulse Width

tLL

ns

0

5 tp- 40

tp+ 40

ns

30

ns
ns
ns

5 tp+ 20

ns

10

ns

2 tp-25

ns

REFRQ Pulse Width

20

ns

tCHS

RD, WR, PCS Active Hold to RAS

0

tww

WR to WE Propagation Delay

8

tAL

S, to ALE Setup Time

40

ns

tLA

S, to ALE Hold Time
External Clock low Time

2 tp+40
. 15

ns

tpL
tpH

External Clock High Time

22

ns

External Clock High Time for VCC= 5V ± 5%

18

ns

. tpH

ns
50

ns

ns

Noles:
1. tp minimum determines maximum oscillator frequency.
tp maximum determines mtnlmum frequenqyJg mamtain 2 ms refresh rate and tRP minimum.
2. To achieve the minimum time between the RA-S- of a memory cycle and the ~ of a refresh cycle, such as a transparent refresh, REFRQ should be
pulsed in the previous memory cycle.
,
3. tsc is not required for proper operation which is in agreement with the other specs, but can be used to synchronize external signals with XlCLK if it is
desired.
'
4. If tAS is less than 0 then the only impact is that tASR decreases by a corresponding amount.

Figure SC1.2. 8202 Timing Information (Con't)

3-341

230792-001

AP-67

".

READ CYCLE

iiii

"AS

v"

GY

~

VIL

v,.

@

I

v,.

1""

VIL

K. ~
·1...· --

IA.

r-fAAH-!
ROW I
ADDRESS

V,.

leAs

\\\\ ®

CD

--I"'.

·i

r -...

....

' . .0

~

ADDRESSES

V

.....

IcRP-j

VIL

CAS

J

r---"'---!

...

- , --:--

K

COLUMN
ADDRESS

1-

tRCH-

®~

W.
VIL

0

\
IeAC

DoUT
VOL

~toFF

'RA.

VOH

--------~~~~~--------------------®~.~

WRITE CYCLE

m

<>-+--+=-t

MRDC 1
MWTC 2

~+----,1.,1 C~4LS74 Q

8

CLR
' -_ _----'13

ALE

J

r----

~--------------------------~

EARLY RD

Figure 5C2.1. Early Read and

W~te

3-344

Command Generation

23079:1-001

AP-67
We can now use the slowest 2118 which gives 8202 and
2118 access of 320 ns. Early command to RDY timing is
TCLCL- TCHLLmax - circuit delays - TR1VCLmax =
115 ns and provides 35 ns of margin beyond the 8202
command to SACK delay.
The write timing of the 8202 and write data valid timing
of the 8086 do not allow use of an early write command.
However, if the 8202 clock is reduced from 25 MHz to 20
MHz and WE to the RAM's is gated with CAS, the advanced write command (AMWC) may be used. At 20 MHz
the minimum command to CAS delay is 148 ns while the
maximum data valid delay is 144 ns.

refresh. Delaying SACK until XACK time causes the
CPU to enter wait states until the cycle is completed. If
the cycle is a read cycle, the XACK timing guarantees
data is valid at the CPU before RDY is issued to the CPU.
The use of the early command signals also solves a
proble~ not mentioned previously. The cycle rate of the
8202 @ 20 MHz requires that commands (from leading
edge to leading edge) be separated by a minimum of 695
ns. The maximum mode 8086 however may issue a read
command 600 ns after the normal write command. For
the early read command and advanced write command,
725 ns are guaranteed between commands.

The reduced 8202 clock frequency still satisfies no wait
state read operation from early read and will insert no
more than one wait state for write (assuming no conflict
with refresh). 20 MHz 8202 operation will however require using the 2118-4 to satisfy read access time.
Note that slowing the 8202 to 22.2 MHz guarantees valid
data within 10 ns after CAS and allows using the 2118-7.
Since this analysis is totally based on worst case
minimum and maximum delays, the designer should
evaluate the timing requirements of his specific implementation.
It should be noted that the 8202 SACK is equivalent to
XACK timing if the cycle being executed was delayed by

3-345

EARLY RO--"

AD
8202

AMWC

iNA

WE <---..........---...
CASr--T--<.J._

WE TO RAMS

"----CAS

Figure 5C2.2. Delayed Write to Dynamic RAMs

230792-001

AP-67
APPENDIX I
,BUS CONTENTION AND ITS EFFECT ON SYSTEM INTEGRITY
SYSTEM ARCHITECTURE

As higher performance microprocessors have become
available, the architecture of microprocessor systems
has been evolving, again placing demands on memory, '
For many years, system designers have been plagued
with the problem of bus contention when connecting
multiple memories to a common data bus, There have
been various schemes for avoiding the problem, but
device manufacturers have been unable to design internal circuits that would guarantee that one memory
device would be "off" the bus before another device
was selected. With small memories (512x8 and 1Kx8), it
has been traditional to connect all the system address
lines together and utilize the difference between tACC
and tco to perform a decode to select the correct device
(as shown in Figure 1).

function, chip select (CS), which is very fast (tco= 120
ns) with respect to the overall access time (tACC= 450
ns) of the 2708. It is this time difference (330 ns) that is
used to perform the decode function, as illustrated in
Figure 2. The scheme works well and does not limit
system performance, but it does lead to the possibility
of bus contention.

I

ADDRESS

CS

DATA OUT

==:x
I

tACC

I

I

{

i_o;'i~I,J~~

Figure 2. Single Line Control Architecture

BUS CONTENTION

Figure 1. Single Control Line Architecture

With the 1702A, the chip select to output delay was only
100 ns shorter than the address access time; or to state
it another way, the tACC time was 1000 ns while the tco
time was 900 ns. The 1702A tACC performance of 1000 ns
was suitable for the 4004 series microprocessors, but
the 8080 processor required that the corresponding
numbers be reduced to tACC= 450 ns and tco= 120 ns.
This allowed a substantial improvement in performance
over, the 4004 series of microprocessors, but placed a
substantial burden on the memory. The 2708 was
developed to be compatible with the 8080 both in access time and power supply requirements. A portion of
each 8080 machine cycle time had to be devoted to the
architecture of the system decoding scheme used. This
devoted portion of the machine cycle included the time
required for the system controller (8224) to perform its
function before the actual decode process could begin.
Let's pause here and examine the actual decode
scheme that was used so we can understand how the
control functions that a memory device requires are
related to system architecture.
The 2708 can be used to illustrate the problem of having
a single control Une. The 2708 has only one read control

There are actually two problems with the scheme
described in the previous section. First, if one device in
a multiple memory system has a relatively long deselect
time, and a relatively fast decoder is used, it would be
possible to have another device selected at the same
-time. If the two devices thus selected were reading oppOSite data; that is, device number one reading a HIGH
and device number two reading a LOW, the output transistors of the two memory devices would effectively produce a short circuit, as Figure 3 illustrates. In this case,
the current path is from Vcc on device number one to
GND on device number two. This current is limited only
by the "on" impedance of the MaS output transistors
and can reach levels in excess of 200 mA per device, If
the MaS transistors have a lot of "extra" margin, the
current is usually not destructive; however, an instantaneous load of 400 mA can produce "glitches" on the
Vcc supply-glitches large enough to cause standard
TTL devices to drop bits or otherwise malfunction, thus
causing incorrect address decode or generation.
The second problem with a single control line scheme is
more subtle. As previously mentioned, there is only one
control function available on the 2'708 and any decoding
scheme must use it out of necessity, In addition, any inadvertent changes in the state of the high order address
lines that are inputs to the decoder will cause a cnange
in the device that is selected. The result is the same as
before-bus contention, only from a different source.
The deselected device, cannot get "off" the bus before
the selected one is "on" the bus as the addresses rapidly change state. One approach to solving this problem
would be to deSign (and specify as a maximum) devices

3-346

230792-001

.,

AP-67
with tOF time less than tco time, thereby assuring that if
one device is selected while another is simultaneously
being deselected, there would be some small (20 ns)
margin. Even with this solution, the user would not be
protected from devices which have very fast tco times
(tco is specified as a maximum).

r----270S::!

2708='-----,
Vee
I
I

I

DN1
Vss

I
OR
TIE

I
I
I
I

_______ .J

I
I
I
I
DATA

Vee

I
I
I

Vss

L ______ _

BUS

RESULTS OF IMPROPER TIMING WHEN OR TYING MULTIPLE
MEMORIES.

generate the unique device selecting function, but a
separate and independent Output Enable (OE) control is
now used to gate data "on" and "off" the system data
bus. With this scheme, bus contention is completely
eliminated as the processor determines the time during
which data must be present on the bus and then
releases the bus by way of the Output Enable line, thus
freeing the bus for use by other devices, either
memories or peripheral devices. This type of architec·
ture can be easily accomplished if the memory devices
have two control functions, and the system is im·
plemented according to the block diagram shown in
Figure 5. It differs from the previous block diagram
(shown in Figure 1) in that the control bus, which is connected to all memory Output Enable pins, provides
separate and independent control over the data bus. In
this way, the microprocessor is always in control of the
system; while in the previous system, the microproc·
essor passed control to the particular memory device
and then waited for data to become available. Another
way to look at it is, with a single control line the sytem is
always asynchronous with respect to microprocessor/
memory communications. By using two control lines,
the memory is synchronized to the processor.

Figure 3. Results of Improper Timing when OR Tying Multiple
Memories

The only sure solution appears to be the use of an external bus driver/transceiver that has an independent
enable function. Then that function, not the "device
selecting function," or addresses, could control the
flow of data "on" and "off" the bus, and any contention
problems would be confined to a particular card or area
of a large card. In fact, many systems are implemented
that way-the use of bus drivers is not at all uncommon
in large systems where the drive requirements of long,
highly capacitive interconnecting lines must be taken
into consideration-it also may be the reason why more
system designers were not aware of the bus contention
problem until they took a previously large (multicard)
system and, using an advanced micorprocessor and
higher density memory devices, combined them all on
one card, thereby eliminating the requirement for the
bus drivers, but experiencing the problem of bus contention as described above.

ADDRESS

-V
--"_ _ _ _V-A-

SELECTION

OUTPUT

ENABLE

D~G~ -------~(\-____'}r----

Figure 4. Two Control Line Architecture

THE MICROPROCESSOR/MEMORY INTERFACE

From the foregoing discussion, it becomes clear that
some new concepts, both with regard to architecture
and performance are required. A new generation of two
control line devices is called for with general requirements as listed below:
1. Capability to control the data "on" and "off" the
system bus, independent of the device selecting function identified above.
2. Access time compatible with the high performance
microprocessors that are currently available.
Now let's examine the system architecture that is required to implement the two line control and prevent
bus contention. This is shown in the form of a timing
diagram (Figure 4). As before, addresses are used to

Figure 5. Two Control Line Architecture

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APPLICATION
NOTE

AP-123

March 1982

MARCH 1982
ORDER NUMBER: 210355-001

©INTEL CORPORATION, 1982

3-348

Graphic CRT Design
Using the Intel 8089

Contents
INTRODUCTION
OVERVIEW OF CRT GRAPHIC SYSTEMS ..... .

Typical Design Technique ... -............... .
Performance Requirements ................ .
System Bottlenecks ........................ .
OVERVIEW OF THE 8089 .................... .

Architectural Overview ..................... .
System Configurations ..................... .
Software Interface ......................... .
Timing Details ............................ .
GRAPHIC CRT SYSTEM DESIGN ............. .

System Partitioning ........................ .
8086/8089 Software Interface ............... .
8089 Display Hardware Interface ............ .
8089 Display Functions Software ........... .
System Performance ...................... .
CONCLUSIONS ............................. .
APPENDIX A
APPENDIX B

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INTRODUCTION (

This application note is presented in five sections:
1. Introduction

The purpose of this application note is to provide the reader
with the conceptual tools and factual information needed to
apply the Intel 8089 to graphic CRT de~ign. Particular
attention will be paid to the requirements of high-resolution,
color graphic applications, since these tend to require higher
performance than those which do not use color.
The Intel 8089 is a microprocessor system which contains an
8086 CPU and an 8089 Input! Output Processor. In the
graphic CRT application, the 8089 performs DMA transfers
from the display memory to the CRT controller, and also
serves as a CPU for functions such as keyboard polling and
initialization of the CRT controller chips. The DMA
transfers are done in such a manner that they do not tie up the
system bus.
The system is organized so that the 8086 and the 8089
can perform concurrent processing on separate buses.
Using the inherent ability of the 8089 to execute programs in its own I/O space, the 8086 can successfully
delegate many of the chores that have specifically to do
with the CRT display and keyboard, thus reducing the
8086'8 processing overhead. For these reasons, the capabilities of the 8086 as a CPU can be more fully utilized
to perform calculations dealing with the material to be
displayed. Thus, more complex types of displays can be
undertaken, and the terminal will also be more
interactive.

2. Overview of Graphic CRT Systems
3. Overview of the 8089
4. Graphic CRT System Design
5. Conclusions
Section 2 discusses typical CRT designs, shows how performance requirements increase when the capability for color
graphics is included, and explains' some of the system
bottlenecks that can arise. Section 3 describes the capabilities
of the 8089, which can be brought to bear to resolve these
bottlenecks. Section 4 gives detailed information for a color
graphic CRT system using the Intel 8089 (8086 and 8089).
The reader may obtain useful background information
on the 8086 and 8089 from iAPX 86,88 User's Manual.
It would also be helpful to read the data sheets on the
8086,8089,2118 Dynamic RAM, 8202 Dynamic Ram
Controller, 8275 CRT Controller, 8279
Keyboard/Display Interface, and 2732A EPROM.

OVERVIEW OF CRT GRAPHIC SYSTEMS

Typical Design Technique
A typical microprocessor-based CRT terminal i~ shown
in block diagram form in Figure I. The terminal consists

CHARACTER
GENERATOR ROM

CAT TERMINAL
SERIAL INPUT LINE

CAT TERMINAL
PARALLEL INPUT/OUTPUT

LINES

POWER
SUPPLY

Figure 1. Typical CRT Terminal Block Diagram
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of a CRT monitor, monitor electronics, a CRT controller and character generator ROM, display memory, a
DMA device, a central processor and associated program memory, a keyboard and keyboard interface, and
serial and/or parallel communication devices.
The primary function of the non-graphic CRT controller
is to refresh the display. It does this by controlling the
periodic transfer of information from display memory
to the CRT screen, with the help of the DMA device.
The central processing unit (CPU) coordinates the
transfer of information to and from the external
devices. When information from an external device is
received by the terminal, the CPU performs character
recognition and handling functions, display memory
management functions, and cursor control functions.
The CPU also interrogates the keyboard interface
device. If a key depression is detected, the ASCII character representing that key is sent to the display
memory and/or an external.device.
The design shown in Figure 1 could be implemented
using Intel LSI products. The CPU could be an 8085,
the DMA device an 8237 A DMA controller, the CRT
controller an 8275, the character generator ROM a
2708, program memory ROM a 2716, display memory
2114s (2K x 8), and the keyboard interface an 8279
keyboard controller. These choices would result in a

CRT terminal capable of displaying 25 lines of text
containing 80 characters each.
As the design is upgraded to add color and graphics
capability, performance requirements increase accordingly. The components most likely to require changing
are the CPU, the DMA device, the CRT controller, and
the display memory. Thus, it is desiral;>le at this point to
examine the operation of these components in more
detail to provide a foundation for graphic system operation. Later we shall give a specific example of a more
complex display, and examine the performance requirements imposed. Figure 2 is a block diagram showing only those components involved with the
non-graphic CRT refresh function, with more detail
provided regarding the connecting signal lines.
The refresh function proceeds as follows. The 8275,
having been programmed to the specific screen format,
generates a series ofDMA request signals to the 8237 A.
This results in the transfer of a row of characters from
display memory to one of two row buffers within the
8275. From this row buffer, the characters are sent, via
lines CCO-CC6, to the character generator ROM. The
dot timing and interface circuitry is then utilized to
convert the parallel output data from the character
generator ROM into serial signals for the video input of
the CRT.

DISPLAY

IIEMORY

!J

{

(

SYSTEliauS

~
liE

"0

~7
WR

lOW

IIEIIW

iOii

iiii
Cii

HRO
HACK

IRO

Cii

1237A
OIIA
CONTROLLER

LC~3

ORO

VIDEO SIGNAL

CHARACTER
GENERATOR

OACK
1275
CRT
CONTROLLER

DOT

CC~.

CCLI(

TilliNG
ANO
INTERFACE

HORIZONTAL SYNC
VERTICAL SYNC
INTENSITY

VIDEO CONTROLS

Figure 2. Components Involved in the CRT Refresh Function
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---:.----------------1st
Character

2nd
Character

4th
3rd
Character, Character

5th
Character

6th
Character

7th
Charscter

00 •••• 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0

First Line of a Character Row

1st
Character

2nd
Character

3rd
Character

4th
Character

5th
Character

6th
Character

7th
Character

8~~~~~88:~8g8:gg:~~~~888gg8ggB:~~~~g8~~~~~gg:gB8:g
Second Line of a Character Row

1st
Character

)

2nd
Character

3rd
Character

4th
Character

5th
Character

6th
Character

7th
Character

00 •••• 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
0.0000.00 • • 000.0080000000000000.000.00.000.00.000.0

OWODOO.OOWOODO.OO.ODDODOODDOOOOWODO.OO.OOO.OO.ooowo

Third Lme of a Character Row

-------"----1st
Character

2nd
Character

3rd
Character

4th
Character

5th
Character

6th
Character

7th
Character

00• • • • 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0

o.oooo.oO •• ooo.Qo.OOOOOODOOOOOO.ooo.oo.oOO.OO.ooo.O

O.ODOO.OO.0.OO.CO.000000D0000008000.00.000.00.000.0
0.0000.00.0000.00 • • • • 0000000000 • • • • 000.000.00.0.0.0
0.0000800.00.0.00.00000000'00000.0.0000.000.00.0.0.0

O.OOOO.OO.OOO •• CO.OOOOOODOOOOOO.OO.ODO.OOO.OO.O.O.O

00 • • • • 000.0000.00 • • • • • 000000000.00.0000 • • • 0000.0.00

Seventh Line of a Character Row

Figure 3. Character Row Display

The character rows are displayed on the CRT one line at
a time. Line count signals LCO-LC3 are applied to the
character generator ROM by the 8275, to specify the
specific line count within the row of characters. This
display process is shown in Figure 3, using a seven-line
character for purposes of illustration. The entire process is repeated for each row of characters in the
display.
At the beginning ofthe last display row, the 8275 issues
an interrupt request via the IRQ output line. This interrupt output is normally connected to the interrupt input
of the system CPU. The interrupt causes the CPU to
execute an interrupt service subroutine.- This subroutine typically reinitializes the DMA controller
parameters for the next display refresh cycle, polls the
system keyboard controller, and executes other appropriate functions.

Performance Requirements
In the example we have discussed thus far, a display
consisting of 25 rows, each containing 80 text charac-

ters, with no color or graphic capability, has been assumed. Such a screen can be represented by 80 x 25 =
2000 bytes of data. If the screen is refreshed 60 times
per second, then a total of 120,000 bytes will need to be
transferred each second from display memory to the
8275 CRT controller. This figure is well within the capability of the 8237 A DMA controller, even allowing for
vertical retrace time and other overhead. In this application then, both the display memory and the system
bus remain available to the system CPU most of the
time, and no bottleneck occurs because of the DMA
transfer process.
The situation is quite different when a high-resolution,
color graphics capability is desired. The performance
requirements are obviously much greater. To derive a
quantitative requirement it is necessary to choose, even
if somewhat arbitrarily, a specific display method and
screen format. The display method chosen for the system described in this application note is called the
virtual-bit mapping technique. When this technique is
used, the graphic material to be displayed is haqdled on
a character basis. Figure 4 shows the structure of the
text and graphic characters used. The text character is a

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AP-123

the remaining two bytes are not used. If it is a graphics
character, the second, third, and fourth bytes contain
the color specification for each of the twenty distinct
picture elements (pixels) within the character. Use of
the foreground color is indicated by a one in the respective bit position, while a zero specifies use of the background color.

7 x 5 character in an 8 x 5 matrix. The graphic character
is a 4 x 5 matrix.
The size of a graphic character is the same as the size of
a text character. In addition, the text characters may be
in color. The resolution (horizontal) for a graphic character is twice as coarse as the dot spacing for a text
character. One of eight colors may be selected for foreground and for background within a particular
character.

The screen format chosen has 80 characters per row
and 48 rows. Thus the resolution (in terms of picture
elements) is 640 x 480 for text characters and 320 x 240
for graphic characters. AJull screen contains 80 x 48 =
3840 characters. Thus, a single frame ofthe display can
be represented by 3840 x 4 = 15,360 bytes. If the screen
were updated 60 times per second, the CRT refresh
function would require a DMA transfer rate of 15,360 x
60 = 921,600 bytes per second.

Figure 5 shows how the display character can be specified using four bytes. The first byte determines whether
the character is a text character or a graphic character,
and specifies the colors for foreground and background. If it is a text character, the second byte
specifies the character with a seven-bit ASCII code, and

LINE COUNT (LCO-LC21

COL3
000

I

COL2

COL1

I

I

I

I
I

I

I

COLO

001

I

I

010

I

I
I

I
I

I

011

I
I

I

I

100

I

I
I
I
I

ROWB

I

ROWC

I

I

(AI TEXT CHARACTER
REPRESENTING THE LETTER A.

I
I

ROW A

I

I

I
I

ROWD
ROWE

(B) GRAPHIC CHARACTER

Figure 4. Character Structure

'-----r-"
I
I

I

~
I

I

BACKGROUND COLOR (1 of 8)

I

FOREGROUND COLOR (1 of 8)

MODE-O == ALPHANUMERICS
1 = GRAPHICS
COLOR CODE

COLOR

iiTcK

000
001
010
011
100
101
110
111

RED
GREEN
YELLOW

BWE
MAGENTA
CYAN
WHITE

(a) Byte 0

Figure 5. Display Character ~pecification

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AP-123

06
~~

D.

04

05

_______________

'y-~

02

0'

DO

____________--JI

7 BIT ASCII

MODE"" 1

,

RB2

RBO

RA.

ROW B GRAPHICS

RA2

RA1

RAO

ROW A GRAPHICS

1 = FOREGROUND COLOR
o ~ BACKGROUND COLOR

(b) Byte'

NOTE: RB1 IS INTENTIONALLV MOVED TO BVTE 3 SUCH THAT REPRESENTATION OF A BLANK

CHAAACTER FOR EITHER TEXT OR GRAPHIC IS THE SAME.

RC2

RC1

----

~ \.'---~........
I
I

I
I

RCO

R83

...../'--'

ROW B GRAPHICS

ROW C GRAPHICS

I
ROW 0 GRAPHICS

(c) Byte 2

RB,

,

RE.

,

RE2

RE'

,

REO ,

RD.'

RD2'

'-----"~---.""---_/ ~.
I
ROW 0 GRAPHICS
I

I
I
I

ROW E GRAPHICS

ROW B GRAPHICS
(d) Byte 3

Figure 5.

Displ~y

Character Specification (Cont.)
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AP-123

System Bottlenecks
It can be seen from the above calculation that nearly

one megabyte of data must be transferred per second to
effect the CRT refresh function alone. Even with the
fastest available DMA controllers, this represents the
major part of the bandwidth for such devices. When the
design shown in Figure 1 is used, the system bus must
also be used by the CRT terminal processor for such
functions as keyboard polling and communication with
external devices. In addition, any changes made to the
material being displayed would require use of the system bus for the purpose of storing. the new material in
the display memory, and possibly also for access to
system memory during the calculation process. It is
easy to see, therefore, that severe bottlenecks can occur in terms of system bus utilization. Problems involving bus contention could also be difficult to resolve.
Display underruns could become difficult or impossible
to avoid in some cases, such as when graphics computations require excessive use of the system bus.
The situation can be improved substantially if provision
is made for concurrent processing. One CPU can be
doing calculations on the material to be displayed,
while another CPU can be managing the CRT terminal
functions and the 110 devices simultaneously. Local
buses can be used for access to the respective program
memories, with the system bus used only for transfer of
new display data and for communication between the
two processors.
The Intel 8089 offers a convenient and economical way of
implementing this mUltiprocessing approach. In particular,
the 8089 has unique capabilities that simplify the design
process.

OVERVIEW OF THE 8089
Architectural Overview
The 8089 Input/Output Processor is a complete 110
management system on a single chip. It contains two
independent 110 channels, each of which has the capabilities of a CPU combined with a programmable DMA
controller.
The DMA functions are somewhat more flexible than
those of most DMA controllers. For example, a conventional DMA controller transfers data between an
110 device and a memory. The 8089 DMA function can
operate between one memory and another, between a
memory and an 1/0 device, or between one 110 device
and another. Any device (110 or memory) can physically reside on the system bus or on the 1/0 bus. The bus

width for the source and destination need not be the
same. If the source, for example, is a 16-bit device,
while the destination is an 8-bit device, the 8089 will
disassemble the 16-bit word automatically as part of the
DMA transfer process. The transfer can be synchronized by the source, by the destination, or it can be free
running. The 8089 can effect data transfers at rates up to
1.25 megabytes when a 5 MHz clock is used.
Unlike most DMA controllers, the 8089 uses a twocycle approach to DMA transfer. A fetch cycle reads
the data from the source into the 8089, and a store cycle
writes the data from the 8089 to the destination. This
two-cycle approach enablj:s the 8089 to perform operations on the data being transferred. Typical of such
operations are translating bytes from one code to another (for example, EBCDIC to ASCII) or comparing
data bytes to a search value.
A variety of conditions can be specified for terminating
DMA transfers, including single cycle, byte count (up
to 64K) , external event, and data-dependent conditions, such as the outcome of a masked compare
operation.
The CPU in each channel can execute programs in the
system space (from a memory on the system bus) or in
the 110 space (from a memory on a separate 110 bus).
Thus, complete channel programs can be run by the
8089 without tying up the system bus or interfering with
the operation of the system CPU. Figure 6 is a simplified block diagram of the 8089, showing how the 8089
interfaces with these two buses.
The programs that the 8089 executes may be preexisting
programs stored in ROM or EPROM, or they may be
programs prepared for the 8089 by the system CPU. In
the latter case, the programs are typically in modular
form, contained in "task blocks" that the system CPU
places in a memory location accessible to the 8089.
During normal operation, the system CPU then directs
the 8089 to the various task blocks, according to which
programs are to be executed. The details of how this is
done are given below under Software Interface.
The 8089 has an addressing capability of 64K bytes in
the 110 space, and thus can support multiple peripherals, as illustrated in Figure 7. In the system space,
the 8089 supports I-megabyte addressing, and is directly compatible with the 8086 or 8088, and with Intel's
Multibus. The 8089 operates from a single +5V power
source, and is housed in a standard 40-pin, dual in-line
package. The instruction set for the 8089 lOP is specifically designed and optimized for 1/0 processing and
control. In addition to being able to execute DMA
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AP-123

HOST CPU

SYSTEM BUS

EXT'
CPU
"CHANNEL 1"

DAQ.
SINTR1

CA

SEL

SINTR2

CPU
"CHANNEL 2"

EXT2

..

DAQ2

LOCAL VO BUS AND MEMORY

PERIPHERALS

Figure 6. Simplified Block Diagram of the 8089

transfers under a wide variety of operating conditions,
the 8089 can perform logic operations, bit manipulations, and elementary arithmetic operations on the data
being transferred. A variety of addressing modes may
be used, including register indirect, index auto increment, immediate offset, immediate literal, and indexed.
The register set for the 8089 is shown in Figure 8. Each
channel lias an independent set of these registers, not

accessible to the other channel. Table 1 gives a brief
summary of how these registers are used during a program execution or during a DMA transfer. Four of the
registers can contain memory addresses which refer to
either the system space or the 110 space. These registers each have an associated tag bit. Tag = 0 refers to the
system space and tag = 1 refers to the 110 space. More
details on how the registers are used are given below as
part of the Software Interface section.
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AP-123

DRQ2,EXT2
8089
lOP

DRQ1, EXT1

8088/
8086
CPU

8275
CRT
CONTROLLER

8271

FLOPPY
DISK
CONTROLLER

8279
KEYBOARD
CONTROLLER

Figure 7. 1/0 System with Multiple Peripherals

\

USER PROGRAMMABl£
TAG 19

J

G P ADDRESS A (GA)
G P ADDRESS B (GB)

G P ADDRESS C (GC)

TASK POINTER (TP)
_ _ 1-BIT POINTER TO EITHER 110 OR SYSTEM MEMORY SPACE
15

0

INDEX (IX)
BYTe COUNT (BC)

I.

MASK

logic with the host CPU, They reside on the same bus,
sharing the same system address buffers, data buffers,
and bus timing and control logic, The 8089 requests the
use of the bus by activating the request/grant line to the
host CPU, When the host relinquishes the bus, the lOP
uses all the same hardware, and the host CPU is restricted from accessing the bus until the 8089 returns
control of the bus to the host CPU.

COMPARE (Me)

CHANNEL CONTROL (CC)

NON USER PROGRAMMABLE

(ALWAYS POINTS TO SYSTEM MEMORy)

IL'·_J________~~~~~~~
PARAMETER POINTER (PP) ______~O~
r
CHANNEL CONTROL POINTER (CP)

Figure 8. 8089 Register Set

System Configurations
The hardware relationship between the host CPU and
the 8089 can take one of two basic forms--local configuration or remote configuration, In local configuration (Figure 9) the lOP shares the system bus interface

The local configuration is a very economical configuration in terms of hardware cost, but it does not allow
concurrent processing, and thus it is not able to really
take advantage of the 8089's capabilities for independent operation. In the local configuration, the 8089 acts
as a local DMA controller for the CPU, providing enhanced DMA capabilities and I-megabyte addressing.
For applications such as the color graphics terminal,
where system bus utilization (and other overhead) due
to I/O processing would clearly be excessive in the local
configuration, it is far more desirable to use the remote
configuration, illustrated in Figure 10. The two processors both access VIe system bus, but each may have its
own local bus in addition. Each of the processors may
execute programs from memory on its own local bus, or
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Table 1. Channel Register Summary

Register Size

Program
Access

System
or 1/0
Pointer

Use In DMA Transfers

Use by Channel Programs

GA

20

Update

Either General, base

Source/destination pointer

GB

20

Update

Either General, base

Source/destination pointer

GC

20

Update

Either General, base

Translate table pointer

TP

20

Update

Either Procedure return, instruction pointer Adjusted to reflect cause of termination

PP

20

Reference

IX

16

Update

N/A

General, auto-increment

N/A

BC

16

Update

N/A

General

Byte counter

MC

16

Update

N/A

General, masked compare

Masked compare

CC

16

Update

N/A

Restricted use recommended

Defines transfer options

System Base

N/A

SYSTEM MEMORY
BUS

CONTROLLER

LATCHESf
TRANSCEIVERS

.,

PERIPHERAL

PERIPHERAL

"P2

Figure 9. CPU and lOP in Local Configuration
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AP-123

Figure 10. CPU and lOP in Remote Configuration

on the shared system bus. This creates a much more
flexible arrangement. Concurrent processing may be
used, and it is not necessary to synchronize the processors. An 8086, for example, may run at 8 or 10 MHz
while the 8089 operates at 5 MHz. The specific terminal
design described later in this application note makes
use of one additional technique to further decouple the
operation of the two processors. This is a dual-port
RAM, which is located between the system bus and the
8089, and serves as display memory and as storage for
the task blocks created by the 8086 CPU. Details on
how this dual-port RAM operates are given below in the
sections describing the terminal design itself.

Figure 11 illustrates the method of communication between the CPU and the lOP. The CPU communicates
to the lOP by placing messages in memory and activating the lOP's channel attention (CA) input. The lOP
communicates to the CPU by placing messages in system memory and making an interrupt request on one of
its system interrupt request (SINTR-l or SINTR-2)
outputs.
The messages in memory take the form of linked
blocks. These blocks are of the following five types:
1. System Configuration Pointer (SCP)
2. System Configuration Block (SCB)

3. Channel Control Block (CCB)
4. Parameter Block (PB)

Software Interface

5. Task Block (TB)
Although the 8089 is an intelligent device which hasla
great deal of ability to function independently when
managing the course of I/O operations, it typically
operates under the overall supervision ofthe host CPU.

The SCP and SCB blocks are used by the CPU (only
after reset) to initialize the 8089. The CCB, PB and TB
blocks are used when the CPU wishes to instruct the
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CHANNEL ATTENTION

CPU

MESSAGES
IN
MEMORY

lOP

INTERRUPT

Figure 11. CPU/lOP Communication

lOP to perform a particular sequence of operations.
Figure 12 shows these five blocks and how they are
linked. The SCp, SCB, CB, and PB must be in memory
which is accessible from both the CPU and 8089 (either
system memory or for this application note, dual-port
!l\emory). The TB may be in either system or 8089 local ,
memory.

local configuration or in multiple-lOP systems). Bit 0
specifies the 110 bus width (designated I). When I = 0,
the 110 bus is an 8-bit bus. I = 1 denotes a 16-bit1l0 bus.
The lOP then proceeds to read the double-word pointer
to the channel control block, converts it to the 20-bit
physical address, and stores it in an internal register
(the channel control pointer register). This register is
loaded only during initialization and is not available to
channel programs. For this reason the channel control
block cannot be moved unless the lOP is reset and
reinitialized.

The system configuration pointer is always found at the
same location (FFFF6) in the system memory. The first
time channel attention is activated (after an lOP reset)
the 8089 reads the system configuration pointer from
this location. The SYSBUS field contains only one significant bit (Bit 0), designated by the letterW. If W = 0,
the system bus is an 8-bit bus. W = I denotes a 16-bit
system bus. The lOP first assumes an 8-bit bus and
reads the SYSBUS field. It stores the information as to
the physical width of the system bus, then immediately
uses this information in the process effetching the next
four bytes, which contain the address of the system
configuration block.
The addresses used to link blocks are standard iAPX 86,
88 pointer variables, each occupying two word locations in system memory. The lower-addres~ed word
contains an offset, which is added to the segment base
value (left-shifted four places) found in the upperaddressed word to derive the complete 20-bit physical
address in system memory. If the block is in an 1/0
memory (as a task block might be), only the offset value
is used.
After thus deriving the address of the system configuration block, the lOP reads this block, starting with the
system operation command (SOC) field. Bit 1 of the
SOC field specifies the request/grant mode (used in

The initialization is complete when the channel control
pointer has been stored. The lOP indicates this by clearing the busy flag in the channell control block (which
must be set by the host CPU before the initialization
sequence began). The host CPU can monitor this flag to
determine when initialization is complete, and then to
initialize any other 8089s in the system.
It is the responsibility of the host CPU to make sure that
the SCP and SCB have the proper contents before
issuing the channel attention (CA) that begins the initialization sequence. After initialization, the host CPU
must also assure that the channel control block (CCB),
parameter block (PB), and task block (TB) all have the
proper contents, before issuing a subsequent CA.

The CA may be issued in the form of an 110 write
command to the address of the lOP on the Multibus.
Figure 13 shows a typical decoding circuit for this write
command. The lOP actually occupies two consecutive
address locations on this bus, because the AO line is tied
to the select (SEL) input of the 8089. A zero on the SEL
line specifies lOP channel 1 for the impending operation, while a one specifies lOP channel 2.

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Ap·123

RESET

I
f'

SCB

ADDRESS

SCB

RELOCATION

r-

CB

ADDRESS

L....-

ca'

RELOCATION

I
L-

PB

ADDRESS

PB

RELOCATION

I

INITIALIZATION

SYSTEM

CONFIGURATION
POINTER

FFFFA

SYSTEM
CONFIGURATION
BLOCK

CCW

I

BUSY

FFFF8
FFFF8

SOC

I

BUSY

"-

•

SYSBUS

I
L-

CHANNEL 1

CCW

PB

ADDRESS

PB

RELOCATION

}_R""~'_"

}~""'"

I
TB

ADDRESS

TB

RELOCATION

W

........

~ .....PARAMETER BLOCK

T

T

"m1T

lOP TASK
PROGRAM

1
T

Figure 12. Linked Block Communication Structure

reads the channel command word (CCW). It then sets
or clears the busy flag (FFH = set, OOH = clear). The
encoding of the channel command word is shown in
Figure 14. The CCW provides the lOP with a functional
command (START in 110 space, HALT, etc.) and
specifies some of the operating conditions, such as
interrupt handling, bus load limit, or priority relative to
the other channel. If the CPU is instructing the lOP to
execute a program, it is at this point that the CPU
specifies, via the CCW, whether the instructions are to
be fetched from the system space or from the 8089's 110
space. Refer to iAPX 86,88 User's Manual for specific
details on the setting and clearing ofthe busy flag and on
CCW specifications.

.7----;
.6-----1

.5----;
•• -----1":""'\
.3----~';,I

.2---......;
iCiWl: - - - - - - -......:::::.1

c.

Ao---------PORT FC=CHANNEL 1 CA
PORT FD=CHANNEL 2 CA

Figure 13.

Chan~el

Attention Decoding Circuit

After the CCW has been read, the lOP reads (if appropriate to the command) the address of the parameter
block associated with the impending operation, and
stores the translated address (from the two-word segment and offset pair to the 20-bit physical address) in

The channel control block has a section for each channel. When the CA is received, the lOP goes to the
section corresponding to the selected channel, and
3-361

210355-001

,AP-123

7

0

I I I I I~F I
P

CF
000
001
010
011
100
101
110
, 111

0

B

CF

COMMAND FIELD
UPDATE PSW
START CHANNEL PROGRAM LOCATED IN 1/0 SPACE.
(RESERVED)
START CHANNEL PROGRAM LOCATED IN SYSTEM SPACE.
(RESERVED)
RESUME SUSPENDED CHANNEL OPERATION
SUSPEND CHANNEL OPERATION
HALT CHANNEL OPERATION

ICF
00
01
10
11

INTERRUPT CONTROL FIELD
IGNORE, NO EFFECT ON INTERRUPTS.
REMOVE INTERRUPT REQUEST; INTERRUPT IS ACKNOWLEDGED.
ENABLE INTERRUPTS.
DISABLE INTERRUPTS.

B

o
1

BUS LOAD LIMIT
NO BUS LOAD LIMIT
BUS LOAD LIMIT

P

PRIORITY BIT

Figure 14. Channel Command Word Encoding

the parameter pointer (PP) register. PP is another register which is not programmable by the channel program.
The lOP then goes to this location in system memory,
and fetches the address of the task block itself. The task
block contains the actual program to be executed, while
the parameter block contains parameters to be used by
that program.
Except for the first two words, which contain the task
block address, the parameter block format is up to the
discretion of the user. Similarly, the task block may
have any format whatsoever, as long as the lOP can
execute the program. The parameter block is always in
system memory, but the task block may be either in
system memory or in I/O (local) memory.
The host CPU may prepare as many parameterblock/task-block sets as it wishes. An individual set is
then activated for execution by placing its parameter
block pointer in the desired channel's control block,
loading the appropriate channel control word, and issuing a CA to that channel.
The registers shown in Figure 8 store (in addition to
pointer variables) various flags and parameters associated with the lOP's operation: Some of these registers
are loaded automatically with information fetched during the initialization sequence or during channel attention processing. Others must be set by executing a
program using instructions from the lOP's instruction
set that are specifically designed for loading these
registers.

Channel programs (task blocks) are written in ASM-89,
the 8089 assembly language. About 50 basic instructions are available. The lOP instruction set contains
some instructions similar to those found in CPUs, and
also other instructions specifically tailored to I/O operations. Data transfer, simple arithmetic, logical, and
address manipulation operations are available. Unconditional jump and call instructions are provided so that
channel programs can link to each other. An individual
register or even a single bit may be set or cleared with a
single instruction. Other instructions specify conditional jumps, initiate DMA transfers, perform semaphore operations, and issue interrupt requests to the
CPU.
A channel program typically ends by posting the result
of an operation to a field supplied in the parameter
block, then interrupting the CPU (if interrupts are enabled) and halting. When the channel halts, its associated BUSY flag is cleared in the channel control block.
The CPU can poll this flag (as an alternative to being
interrupted) to determine when the operation ha~ been
completed.

Timing Details
The basic bus timing relationships for the 8089 are
identical to those of the 8086 or 8088, in that all cycles
consist of four states (assuming no wait states), and use
the same time-multiplexing technique for the address/data lines. The address (and ALE signal from the
3-362

210355-001

AP-123

ClK
S2-SO

ADDRESS/STATUS

BHE

S2-SO ACTIVE

=~~J----{ A1~A16 X

~~~A-

____________
S6-S3

\... __ _

~

~

=~ ~ =f-----{L_1Iiii!_H_E_LOW_F_D_R_DA_TA"'ah....RA....E ....N,8"'fs-cER"'.3!Lr_H_IG_H_-Q_R_DE_R--Ir-

ADDRESS/DATA
(AD1S-ADO)

'ALE

52-SO INACTIVE

DATA IN

A15-AO

-F\~

015-00

___________

*MORC or ·IORC

*DT/R

-- T'- - - - - - ,
__ ~'

r-

'---_ _ _ _ _ _ _ _ _~,

-DEN

--------------~

'8288 BUS CONTROllER OUTPUTS

Figure 15, Read Bus Cycle

8288 bus controller) is output during state Tl for either a
read or write cycle, During state T2 for a read cycle
(Figure 15) the address/data lines are floated. During
state T2 for a write cycle (Figure 16) data is output on
these lines. During state T3, the write data is maintained or the read data is sampled. The bus cycle is
concluded in state. T4.
Figure 17 shows some details on the wait state timing
and Figure 18 shows the RESET-CA initialization
timing.
During DMA transfers, the transfer cycle may be
synchronized by either the source or the destination.
Figure 19 (source-synchronized transfers) and Figure
20 (destination-synchronized transfers) show the
relationships among the basic clock cycles, the DRQ
signals, and the DACK signals.
The 8089 does not have a DACK output signal. Rather,
it uses· the more general process of issuing a command
(for example, 110 read or write) to an address on the 110
bus. This command is then hardware decoded to obtain
3-363

a chip select signal for the addressed device. This
method enables the 8089 to relate to a variety of 110
devices in a very flexible manner.
Figures 19 and 20 also show how the 8089 inserts idle
clocks to accommodate various DRQ latency conditions. If maximum efficiency (transfer rate) is desired, it
is usually possible to remove this latency by techniques
such as generating an early DRQ. Another possibility is
to use the unsynchronized DMA transfer mode (DRQ is
not examined) and to use the READY signal for
synchronizing transfers. The early DRQ technique will
be discussed later..

GRAPHIC CRT SYSTEM DESIGN
Having examined the requirements for graphic CRT
systems in general, and having also discussed the capabilities of the 8089, we can now proceed to describe a
specific graphic CRT design using the 8089.
In this design. the system CPU is an 8086. Thus. the entire
system is called an Intel 8089.
210355-001

~AP-123

ClK

52-SO

S2-SO ACTIVE

==~ ~ }--{

ADDRESS/STATUS

A19-A16

52-SO INACTIVE

L~ ~ =

Y

iHE

==~ ~}--{,-_BH_E_LDW
__
FO_R_D_A...
~~,-,T....~...
W,-,1S",1..",~",lD_N_H_IG_iAl_R_DE_R-Jl-­

ADDRESS/DATA
(AD15__AOO)

=~ ~ ~ :>----{'-_A_15--_AO_J1iX'---_ _D_A_~A_D_U_T_D_15--_oo_ __ _ _ ' l - ~'---_ _ _ _ _ _ _ _ _ _ _ _ __

'AlE

,Ai,iWC DR 'AIDWC
*MWTC OR -lowe

---,,
___

-DEN

-',~

_ _ _ _....J

'8288 BUS CDNTRDllER OUTPUTS

Figure 16. Write Bus Cycle

System Partitioning
ONE BUS CYCLE

ClK

'

~

TR1VCl'-.lI_R1VCl-.J1++I ~TClR1X"

va

ROY INPUT

READY
OUTPUT

V/1
NOT READY

READY

fREADY

'*REFER TO THE 8284A CLOCK GENERATOR/DRIVER

SHEET FOR TIMING INFORMATION

Figure 17. Wait-State Timing
(Synchronous ROY Input)

ClK~
RESET

.

MUST BE ACTIVE \
FOR FIVE CLOCK !-.- - - - : - - - CYCLES
1 eLK MIN

I...

CA - - - - - - - - - - ' .
-

-

- - -

-

-

I

.I~CA

- - ' 1 elK MIN

,

The 8086 and 8089 are arranged in the remote configuration. This assures that concurrent processing can occur.
As mentioned earlier, an additional step is taken to
further decrease system bus utilization for I/O-related
processes. This step is the inclusion in the system of a
dual-port RAM, located between the system bus and
the 8089~ This qual-port RAM contains the display
memory and also contains the linked message blocks
used for communication between the 8086 and the 8089.
The system configuration then becomes that shown in
Figure 21. The dual-port RAM becomes the only data
path between the 8086 and the 8089. Access to this
memory is time-shared between the 8086 and the 8089,
with the 8089 taking less than 50% of the total time
available. Since the 8089 does not access the system
bus, the host system can enjoy complete freedom to
allocate its resources between its own local bus and the
system bus. The CPU and the lOP can operate
asynchronously, with the 8086 running on an 8 MHz
clock and the 8089 on a 5 MHz clock.

:LL/.. RECOGNIZED

The division of responsibility between the 8086 and the
8089 is then very clearly defined. The 8086 initializes the
8089 and specifies the task parameters, storing them in

Figure 18. Reset and Channel Attention Timing

3-364

210355"()01

AP-123

TRANSFER CYCLE

1~:'-_T-,------~:~:T~e~H~.~u~S~e~ye~l=:~-------~--~:I~:.--T-,-------s~T~:~R~E~.~us~e~y~C~lE~~---------T-4-:~1
I-.. 0 IDLE

',.... ORO HOLD ....

(FROM 110

~I~

I--CLOCKS 1

FROM READ

2 IDLE ~l....-

1--

CLOCkS 1

410LE

CLOCKS 1

DE~~CQ~:"')--------------.,\:~.,.\U.,.\:\:\.1.\...,J..\~\:\\U3~_....!./_r_-__-_-_-_-:_R_~_F_~_R_:_E-_XT_~_R_:-_N_::_E_;;_e_;_el_;_-_-__-_-__-_-_
OAeK~

(DECODED

1/0 ADDRESS)

VALID 110 ADDRESS
PRESENT

\'--------

NOTES
1) INDICATES THE NUMBER OF IDLE CLOCKS INSERTED AFTER T4 OF THE STORE CYCLE BEFORE THE NEXT TRANSFER CYCLE
BEGINS IF DRO IS RECEIVED BEFORE THE RISING EDGE OF ClK IN THE CURRENT FETCH CYCLE, THE NEXT FETCH BEGINS
IMMEDIATELY AFTER THE CURRENT STORE
2) IF THE 8089 IS IDLE WHEN DRO IS RECOGNIZED, FOUR OR FIVE MORE IDLE ClOCO< CYCLES OCCUR BEFORE THE
ASSOCIATED TRANSFER CYCLE BEGINS (DRO IS lATCHED ON THE RISING EDGE OF ClK )
3) TO PREVENT THE START OF THE NEXT TRANSFER CYCLE, DRO MUST BE BROUGHT lOW BY THE RISING EDGE OF ClK IN T4
OF THE CURRENT FETCH (FOR B/B~W SOURCE SYNCHRONIZED AND W~B/B DESTINATION SYNCHRONIZED IT MUST BE
, lOW BY THE RISING EDG~ OF ClK IN THE FOURTH ClOCK'OF THE CURRENT BUS CYCLE INCLUDING WAIT STATES)

Figure 19. Source-Synchronized Transfer Cycle

TRANSFER CYCLE 1

..

..
FETCH BUS CYCLE 2 2

FETCH BUS CYCLE 1 1

elK

_I_
1
~\\m5 r

ORa HOLD FROM.-I----J ..
ADVANCED WRITE ,-.......
DRQ 4
(FROM 110 DEVICE)

--I

2 IDLE

4 IDLE

..,1"

CLOCKS;'I .. CLOCKS 3

:a-:O:-N:T:A::R

o.

-7---------...\,,\...,..,.,.,\,\
-

"\\U-..J\IL-,.i
-_--

IDLE
CLOCKS 3
OACK

(DECODED 110

AODRES_S_)______J

VALID I/O
ADDRESS PRESENT

\
L-._ _ _ _ _ _ _ _ _ _ _ _ _ _ _...J

L

NOTES
1) FIRST DMA FETCH CYCLE OCCURS IMMEDIATELY AFTER THE lAST TASK PROGRAM INSTRUCTION IS EXECUTED
2) FETCH CYCLE 2 BEGINS IMMEDIATELY AFTER STORE CYCLE 1
3) INDICATES THE NUMBER OF IDLE CLOCKS INSERTED AFTER T4 OF THE FETCH BEFORE STORE CYCLE 2 BEGINS IF ORO IS
RECEIVED BEFORE THE RISING EDGE OF ClK IN THE CURRENT STORE CYCLE, THE NEXT STORE BEGINS IMMEDIATELY
AFTER THE NEXT FETCH
4) IF THE 8089 IS IDLE WHEN ORO IS RECOGNIZED, FOUR OR FIVE MORE IDLE CLOCK CYCLES OCCUR BEFORE THE
ASSOCIATED STORE CYCLE BEGINS (ORO IS lATCHED ON THE RISING EDGE OF ClK )
5) TO PREVENT THE NEXT STORE CYCLE FROM OCCURRING, DRO MUST BE BROUGHT lOW BY THE RISING EDGE OF ClK IN T4
OF THE CURRENT STORE (FOR B/B~W SOURCE SYNCHRONIZED AND W~B/B DESTINATION SYNCHRONIZED, IT MUST BE
lOW BY THE RISING EDGE OF ClK IN THE FOURTH CLOCK OF THE CURRENT STORE CYCLE INCLUDING WAIT STATES)

Figure 20. Destination-Synchronized Transfer Cycle

3-365

210355-001

AP·123

32K BYTE

2732A-2
EPROM

-

~
CPU

-

8K BYTE

2141-4
SRAM

RESIDENT
BUS INTER-

FACE

r--

-

~I

w
C

a:

BUS

ARBITER

.~.--1

...z

iii
W

8289

~

.,"

MULTI BUSTM,
INTERFACE

8259
INTERRUPT
CONTROLLER

"
9

U>

CPU

32K BYTE

8K BYTE
2732A
EPROM

2K BYTE
2~14AL-3

SRAM

8279
KyaO/DISPLAY
CONTROLLER

2118-12
DRAM

-

LOCAL
~

-.

110 BUS
INTERFACE

--

0

...

CRT
CONTROLLERS

-

CONTROL

~

g

4·8275

:
DUAL-PORT
MEMORY

lOP

::E

"9 .,"
U>

w

In
>
U>

;I

"u>
9i1

,
PERIPHERAL CONTROLLER

Figure 21. Remote Configuration with Dual-Port RAM

3-366

210355-001

AP-123

the dual-port RAM. In many cases, the 8086 also prepares the task programs and stores them in the dualport RAM, from which they may be downloaded to a
memory on the 8089's 110 bus. The 8089 executes the
task programs (from the dual-port RAM or from a local
memory on the 110 bus), while the 8086 simultaneously
executes other control or application programs. The.
application programs may encompass a wide variety of
operations, but they will always generate the display
characters and store them in the dual-port RAM. The
8089 returns status to the 8086 when task program
execution has been completed.

BOOTSTRAP LOADER

FFFFF

OPERATING SYSTEM
APPLICATION PROGRAMS

EPROM

- }-."~
FlOG.

DISPLAY BUFFER

PROGRAM STORAGE
(DOWNLINE LOADED)

2118-12
DUA~POAT

DYNAMIC RAM

FOOOO

;..~

~

.21'.

NON-VOLATILE DATA
STORAGE

Figures 22 and 23 show the manner in which the
memories are organized. Figure 22, which shows the
memory configuration for the 8086, should be taken as
an example, since many different configurations are
possible, according to the user's application. Figure 23
shows the memory configuration for the 8089, given the
particular choices made for the application discussed in
this note. Of the memories shown in Figure 22, the 2141
static RAMs and the 2732A EPROMs are located on the
8086's local bus, while the 2816.EEPROM and the 2118
dual-port RAM are interfaced to the Multibus. The 2816
is a non-volatile read/write memory equivalent in its
storage capacity to the 2716 EPROM.

}

11K BYTES

01000

=

~

INTERRUPT VECTOR TABLE
STACK

SCAATCHPAD

01FFF

2141·"
CPU LOCAL
MEMORY

}.~

00000

Figure 22. CPU Memory Organization

....1"""

,.~

VOSPACE

. . . - - - - - - - - - , FFFFF

BUFFER

OFFFF

EEPROM

SYSTEMS.....CE

2 PAGES
DISPLAY

}--

2732A-2

2118·12

12K BYTES

DYNAMIC RAM

1-..,.-------jFlOOO

T
l
VOPORTS

KEYBOARD

caoo
OACK

AOOO
ClKENA

8000
CRT CONTROLLER ,

1000
CRT CONTROLLER 2

4000

CHANNEL
PROGRAM

2732A
EPROM

SCRATCH
.....D

2"4Al-3
RAM

2000
07FF

0000

Figure 23. lOP Memory Organization
3-367

210355-001

AP-123

8086/8089 Software Interface
Comparing Figures 22 and 23, it can be seen that the
2118 dynamic RAM appears in the memory configurations for both the 8086 and the 8089. In the 8086's
system space, this memory occupies addresses FOOOO
through F7FFF, while in the 8089's system space, its
address range is F8000 through FFFFR

FFFFF
LINKED lOP CONTROL BLOCKS

}
FFEFF

Figure 24 shows the organization of the dual-port
RAM. The addresses given are those seen by the 8089.
The display data (for the CRT refresh function) is contained in the two largest blocks-Display Page 0 and
Display Page 1. Each page contains 15K bytes, enough
to refresh a color graphic screen containing 48 rows of
80 characters each. In typical operation, the 8086 and
the 8089 both access the same page of display data. In
special cases, such as animated displays, the 8089 performs repetitive DMA transfers from one of these
pages, while the 8086 is generating new display material
and storing it in the other page. The display page pointer
(DSPLYJG--PTR) in the parameter block specifies
which of these pages is to be displayed at any given
time. This pointer may be changed by the 8086, or by a
command from the terminal keyboard.

SPARE

15K BYTES

DISPLAY PAGE 1

FCOOO
FBFFF

KEYBOARD BUFFER

)

256BYTES

}

256BYTES

}

;56BYTES

FBFDO
FBEFF
EEPROM BUFFER

FBEOO
FBDFF
COMMAND BUFFER
FBODO
FBCFF
SPARE

)

256BYTES

FBCOO
FBBFF

The EEPROM Buffer is a 256-byte area used in connection with the non-volatile EEPROM memory, an optional memory which may be located on the Multibus.
One use of such a memory would be to store ASCII
strings, which could then be recalled by the 8086 upon
recognition of special keyboard control code
sequences. '

The Spare blocks total lK (1024) bytes, and may be
used for any purpose, according to the user's
application.

}m~

FFCOO
FFBFF

The Command Buffer is a 256-byte area set aside for
transferring ASCII characters from the 8086 to the
8089. It is like a second keyboard, scanned by the 8089.
It takes precedence over any real keyboard activity.
The COM_8086 flag in the parameter b.lock is used to
indicate when there are entries in the command block
area.

The Keyboard Buffer/is a 256-brte area which serves as
a storage area for ASCII characters entered from the
terminal keyboard. When this buffer becomes full, or
when a return is entered at the keyboard, an end-of-file
byte is placed after the last entered character, and the
keyboard buffer full (KBD_BUFJULL) flag is set in
the parameter block. This prevents the 8089 from processing any more inputs from the keyboard, until the
8086 resets KBD--I3UFJULL.

256BYTES

FFFOO

DISPLAY PAGE 0

15K BYTES

FIOOO

Figure 24. Organization of the Dual-Port RAM

The Linked lOP Control Blocks are those which have
been discussed above, as part of the 8089 overview. The
specific memory locations are as shown in Figure 25.
Note that there is only one parameter block, and no task
blocks present. Only one task block is used in this
application, and it is stored in the 2732A EPROMs on
the 8089's 1/0 bus.
3-368

210355-001

AP·123

In the above table, DB represents a one-byte quantity,
and DW represents a two-byte quantity.

FFFFF
SPARE

}

4BVTES

FFFFC
FFFFB
SYSTEM CONFIGURATION
POINTER

}

6 BYTES

}

BBYTES

FFFFS
FFFF5
SYSTEM CONFIGURATION
BLOCK
FFFFO
FFFEF

CHANNEL CONTROL BLOCK'

TP_LSW and TP_MSD are the two words making up
the task pointer. However, since in this application the
task program is in the 1/0 space, only the leastsignificant word (LSW) is fetched.
EEP-INH, when not equal to zero, indicates that the
EEPROM buffer is closed to keystrokes or 8086 ASCII
commands.

}. ~.

EEP_BUF_FULL, when not equal to zero, indicates
that the EEPROM buffer is full.

FFFEO
FFFDF

PARAMETER BLOCK

EEP_RECALL, when not equal to zero, indicates that
the 8089 is recalling the contents of an EEPROM buffer
area.
224 BYTES

COL_CH-INH, when not equal to zero, inhibits the
color control keys on the keyboard.
KBD_INH, when not equal to zero, inhibits the processing of keystrokes (entered at the keyboard) by the
8089. Up to 6 keystrokes may be saved in the keyboard
controller and may be processed later.

FFFOO

Figure 25. Organization of the Linked
lOP Control Blocks Area

As mentioned earlier, the structure of the parameter
block is very flexible. Only the first four bytes are fixed
(because of the 8089's requirements). These four bytes
contain the address of the task block. The remaining
space in the parameter block may be defined by the
user. The following list shows the parameter block
structure that is used in support of the channel program
contained in the 2732A EPROMs on the 8089's 110 bus.
TP_LSW
DW
TP-MSD
DW
EEP-INH
DB
EEP_BUF_FULL
DB
EEP-RECALL
DB
COL-CH-INH
DB
KBD-INH
DB
KBD_BUF-FULL
DB
COM-8086
COLOR
STR-PTIL8086
BACICCOL-SW
MON..:.JNH
DSPLYJGJTR
SCROLLREQ

DB
DB
DW
DB
DB
DB
DB

MON_HOM
MON_END
MON_LMARG
MON-RMARG
KBD_BUFJTR

DW
DW
DW
DW
DW

KBD_BUFJULL, when not equal to zero, indicates
that a new line of keyboard data needs to be processed
by the 8086. The 8089 sets KBD-BUF_FULL equal to
, -1 when the return key is pressed. The 8086 resets
KBD_BUF_FULL to zero after it has read this data.
COM-8086, when not equal to zero, indicates that
there are ASCII commands in the command buffer
areas of dual-port RAM that need to be processed by
the 8089.
COLOR determines the foreground and background
colors to be used in connection with ASCII characters
entered at the keyboard, or sent by the 8086 via the
command buffer area. In the COLOR byte, bits BO-B2
determine the background color, while B3-B5 determine the foreground color. The following code is used:
000
001
010
011
100
101
110
111

Black
Red
Green
Yellow
Blue
Magenta
Cyan
White

STR-PTIL8086 is a two-byte quantity that serves as
an offset address for the ASCII characters in the command buffer.
3-369

210355-001

Ap..123

BACIC.COLSW determines whether the 8089 color
control keys will alter the foreground or the background portions of the COLOR byte. If BACK_CQL_SW,equals zero, the foreground color is
altered. If BACLcOLSW is not equal to zero, the
background color is altered.
MON_INH, when not equal to zero, suspends DMA
transfers by the 8089 from display memory to the 8275s.
When M6N----INH is cleared, DMA will resume.
DSPLYJG-PTR determines which of the two display
pages will be used to refresh the CRT. If DSPLY_PG_PTR equals zero, page 0 will be displayed. If
DSPLY_PG-PTR does not equal zero, page 1 will be
displayed.
SCROLL-REQ is set by the 8089 to indicate to the 8086
that the cursor is at the bottom of the page, and that key
entry/command processing has been halted, pending a
display'memory scroll operation. When the 8086 has
performed this operation, it clears SCROLL-REQ.
MON_HOM, MOK_END, MON_LMARG, and
MON_RMARG specify, respectively, the upper, lower,
left, and right boundaries of the region on the screen in
which keyboard entries will be displayed.
KBD-BUF-PTR is a two-byte quantity that serves as
an address for the ASCII characters in the keyboard
buffer.
Note that a number of these parameters support options (e.g., EEPROM buffer) and are not critical to the
graphic operation described in this application note.

8089 Display Hardware Interface
This section describes the hardware of the peripheral
processing module (PPM), which includes everything
between the system bus and the CRT display/keyboard
unit. The overall organization of the PPM is as shown in
Figure 21. The dual-port RAM can be accessed from
either the system bus otthe 8089's local bus. The 8089 is
said to be operating in the system space when it is
accessing the dual-port 'RAM, and in the I/O space
when it is accessing devices on the I/O bus. Included on
the I/O bus are four 8275 CRT controllers, an 8279-5
keyboard controller, two 2732A EPROMs, which are
used to hold channel programs, and four 2114 static
RAMs, which are used as scratch-pad RAM for the
8089.
As explained above (under OVERVIEW OF CRT
GRAPHIC SYSTEMS, Performance Requirements),
four bytes are used to specify ,each 'character in the

display. The first byte determines whether the character
is a text character or a graphic character, and specifies
the colors for foreground <;md background. If it is a text
character, the second byte specifies the character with
a seven-bit ASCII code, and the remaining two bytes
are not used. If it is a graphics character, the second,
third, and fourth bytes contain the color specification
for each ofthe twenty distinct picture elements (pixels)
within the character. Use of the foreground color is
indicated by a one in the respective bit position, while a
zero specifies use of the background color.
The structure of the display characters and the formats
of the individual bytes are shown in Figures 4 and 5.
The four 8275 CRT controllers on the 8089's I/O bus are
used to process the four bytes comprising each character. Since the 8089 can transfer two bytes at a time in
DMA mode, the four bytes are transferred in two
stages. In the first stage, the 8089 fetches the first two
bytes from the dual-port RAM, and transfers these two
bytes into the first pair of CRT controllers. In the
second stage, the 8089 fetches the second two bytes
from the dual-port RAM, and transfers these two bytes
into the second pair of CRT controllers. This process is
repeated 80 times to transfer the 80 characters making
up each row in the display.
The distinction between text and graphic characters is
entirely transparent 4> the 8089. Four bytes are transferred in every case, even though the text information
only requires two bytes per character.
We shall now examine the hardware schematics in
detail, to see how the various functions of the PPM are
implemented. Figure 26 shows the 8089 lOP and its
associated bus controller. At the top left are the inputs
through which the 8089 is controlled. The DRQF signal
(detailed later) is the DMA request that initiates the
transfer of two bytes from the lOP to two of the four
CRT controllers. DRQF comes from the 8275s via a
one-shot, and is connected to the DRQ 1 input of the
8089.
IRQ is an interrupt request that comes from the 8275s.
It is activated after an entire screen's video information
has been transferred from the dual-port RAM to the
8275s: IRQ is connected to the EXT 1 input ofthe 8089.
It is necessary to program the 8089 to terminate the
DMA transfer on an external event, in order for this
signal to be effective.
CA is the channel attention signal. Upon receipt of CA,
the 8089 reads the channel control word (CCW) from
the dual-port RAM. From the CCW, the 8089 determines the nature of the operation assigned to it by the
3-370

210355-001

AP·123

DRQF

IAQ
CA

Am.-.!f"::
ADY
AST

8

31
33
23
24
22
21

OROl

AD/DO 16

EXT1
CA
SEL
ADY
AST

A1/D1
"2/02
"3/D3
"4/04

"DIDO-A 151015
"'6IS3-A19156. iiii

15
14
13
12

52

A&lOB
A71D7
AalD6
A8I09
A101D10

10
9
8
7
8

A11/011 :

A12/D12
",3/D'3
A14/014
A15/015
A1&183
A17I84
"18/85
A19/5&

12
8
11
9

1910

AS/OS 11

381
18 ft
2

Vcc~
15

(

3
2
39
38
37
36
35

AiOWC
~
~

IIim

7

ClK
lOB
CEN

m

"48
8288

iilIl5i!
iOR

13
14
4
5
16
17

iiiTi.(A EADI/O)
DTIlf
"LE
DEN

IImi
P1

("v

~:

SO 27

r--1!

51
iii

A29

fWL

28

A3

$INTR.1 17
SINTR.2 18

41
42

6089

...r

CLK

Figure 26. 8089 I/O Processor and 8288 Bus Controller

, 8086. CA is derived by hardware decoding of an I/O
write command made by the 8086 to address OOH or
address OIH on the Multibus. The lowest-order bit of
this address is used to specify whether channel 1 or
channel 2 of the lOP is to be selected, and is connected
to the 8089's SEL input. In this application, the DMA
transfers are always performed by channel 1.
RDY is the ready signal that comes from the 8202
dynamic RAM controller, and is synchronized by the
8284A clock generator. RDY is low whenever the 8086
is accessing the dual-port RAM. The RDY signal is used
to establish a master/slave relationship between the
8086 and the 8089, with the 8086 as the master. As
mentioned earlier, the 8089 accesses the dual·port
RAM about 50% of the time during DMA transfers. It
can be seen, referring to Figure 20, that ifno idle clocks
occur, the lOP will access the dual-port RAM during
the four clock times of the DMA·fetch bus cycle, and
will access the I/O bus during the four clock times of the
OMA-store bus cycle. While the 8089 is doing the store
operation, the 8086 can access the dual-port RAM.
Once the 8086 has gained this access, the ROY signal
will remain low until the 8086 is finished. The 8089 waits
for ROY to go high before making a subsequent fetch.
3-371

At 5 MHz, the 8089 requires 3.2 microseconds (16 clock
cycles) to transfer the four bytes representing a graphic
character from the display memory to the four 8275s,
assuming that no wait states have been inserted because of the 8086's access to the dual-port RAM, or
because of dynamic RAM refresh functions. A complete row, consisting of 80 characters, requires 80 x 3.2
= 256 microseconds. The time allowed to complete the
transfer of one row must be less than the time it takes to
display that row on the screen. This latter time is equal
to 1/50 of the total screen update time, or 1/3000 of a
second (333 microseconds). Comparing the two figures
(256 vs 333), it can be seen that there are 77 microseconds available for such wait states. It is the responsibility of the software designer to control the 8086's access
to dual-port RAM in such a mannner that the added
wait states do not total more than 77 microseconds in
any span of 333 microseconds. Otherwise, underruns
may occur and the CRT screen will be blanked. See
System Performance (below) for further discussion on
this effect.
RST is the lOP reset signal, which comes from the
8284A clock generator. The first CA after RST causes
the lOP to access address FFFF6 in the dual-port
RAM, in order to read the system configuration pointer.
210355-001

AP-123

Outputs from the lOP are the time-multiplexed address and
data lines, BHE( (bus high enable), status line SO, SI, and S2,
a~d the system interrupt request lines, SINTR-I and SINTR2. The interrupt lines go directly to the MULTIBUS, and
from there they become inputs to the 8086's 8259 A interrupt
controller.

The DACKI signals are generated in the following
manner:
1. Both 8275 pairs are accessed by the 8089 (DMA
mode) via port AOOOH.

2. Hardware is used to select one pair of CRT controllers (bytes 0 aJ;ld I or bytes 2 and 3).
3. As the 8089 reads (DMA) the word from the dualport memory, address bit I (SAl) is' latched with
the memory read command (MRDC/).

Figure 27 shows the 110 address latches and decoder,
and the circuitry used to generate the DACKI signals
for the CRT controllers. The lOP status bit S2 indicates
whether the lOP is accessing the 110 space or the system space. Latched by ALE (address latch enable), S21
generates 10 and 101. 10 and 101. are used to indicate
that the 8089 is not accessing dual-port RAM. 101 goes
to the dual-port RAM controller.

4. When SAl = 0, DACK 11 is activated.
5. When SAl = I, DACK 21 is activated.
6. In this manner the 8089 performs alternating
writes (DMA) to the 8275 pairs.

"49
ALE
AOIDO-AI51DI5

11

STa

I

DIO
DII
DI2
DI3
DI4
DI5
DI6
DI7

A1/D1

2

A2ID2
A3ID3
A4ID4
A5ID5
A6ID6
A7ID7

3
4
5
6
7
8

DOO
DOl
D02
D03
D04
DOS
D06
D07

OE

~

19
18
17
16
15
14
'3
'2

10A0-10A15

10A'3
10A14
f0A1S

•

2
3

A2

8262

r
6

A66
11

•

ABlD8
2
A9/09
A101D10 •
.Al1,Dl1 4
12 5
AI3/D•• 6
A140147
AI51DI58

19
18
17
16
15
.4
.3
.2

A25
15
14

AO
A.

f
i

E.

E2
E1

T
T

.2
11
10

ClK
CRT
KEY

I

7

6205

Vee

SA'~
MiiDcr-JI

6262

A2'

4

.0
9

.2 D A20 Q

~

10
IDE

••

.,

74lS74

Q

""""or;;-

~DA
5-~

8

~DA
_~

.0

8

A2'

Vee"
4
2

~
•

2

A20
5
Q
D
74LS74
6

iii

Ii

10

A'9

RST

3

4

1"

A19

Figure 27. Address Latches, Decoders, and DACK Generator
3-372

210355-001

AP-123

Figure 28 shows the bus transceivers used between the
8089 and the I/O bus, and also shows the 2732
EPROMs.
Figure 29 shows the 2K bytes of 2114 static RAM on
the I/O bus, which are used as scratch-pad RAM for
the 8089.
Figure 30 shows the 8279-5 keyboard controller, and
also shows the 8284A clock generator that produces the
CLK, RDY, and RST signals for the 8089. For more
information on interfacing the 8279-5 to the keyboard
(Cherry Electrical Products B70-05AB), refer to the
8279/8279-5 data sheet and application noteAP-32, CRT
Terminal Design Using the Intel 8275 and 8279.

Figure 31 shows the clock generator for the character
timing and dot timing. The character clock frequency (C
CLK) is 118 of the dot clock frequency (D CLK), 10.8
MHz. Also shown in Figure 31 is a 9602 one-shot used
to generate the video sync pulses.
Figure 32 shows the CRT Controllers #0 and # 1. Bit 6
of Byte 0 determines whether the display character is
text or graphic. If Bit 6 is low, the character is a text
character, and Byte 1 is used to address the 2732A
character generator ROM. Bytes 2 and 3 are ignored.
The line count outputs LCO-LC3 of an 8275 (any 8275
can be used, since they are all synchronized) are also
applied to the character generator to perform the line
select function.

IOAo-IOA15

A.O

DT/R
AO/OO-A15/015

"
1

AD

2

Al

~

I'---"-

t---+
~
r-----.!..
r---!-9

T
BO
Bl
B2

A2
A3
AO

,.
,.

IODO-IOD1S

18

17

B3
1S
BO
10
B.
13
B6
12

A.
A6
A7

A07

,'8

eE

B~

OE
8286

10A1

8

10A2
10A3
10AO
10AS

7
B
S
0
3
2
1

IOA6
10A7
IOA8

A31

"
1

~
3

IOA9 23
IOA10 22
10A11 19
10A12 21

,.

-----.

18
17

----+----+-

10
13
12

~

A2
A3

Do
O.

AO
AS
A6

O.

Ds
Or

A7

9
10
11
13
10

,.

1000

1001
1002

IOD3
1004

10DS

16

1006

17

1007

A8
AS
A10

A"
2732A

1

20

"

-----.L

0,

OE

16

----.!..

00

AD
A1

118

9
8286

•

1008

IOA1

8

IOA2

7
6

10
11
13

1009

4

10
1S
16
17

10012

IOA3

IOA4

lOA'
IOA6
IOA7
IOA8
IOA9

1'CiEPRiiM

Ce

•
3
2
1

A6'

10010

10D11
10013

10014
10015

23

IOA10 22
IDA" 19
IOA12 21
2732A

0-

A18
1

3

, 12D

--./
Figure 28. Bus Transceivers and EPROMs on I/O-Bus

3-373

210355-001

A~·123

10A1-10A1 0
A2I
I

•

7

•
3
2

1
17
11
15

~01

AD
1.1
1.2

V03

1.3

V04

~02

,.
13
12
11

10DD
1001
IOD2
10Dl

M

~
t----.!..
~
~

13
12

1OD4
I0OI
JODI

11

IOD7

r-..--!.
~

AI
AI
1.7
AI
AI

21.AL·3

WE
10

,.

5

1

~

AU

~

21141.1.-3

WE Ci

CS

8

I•

10

12_ _

iOiWi~_----.J
lOA

13

,"
1.2

/

14
13
12

~

r----!-

I---t

11

10Dl
IODI
IOD10
IOD11

~
~
4

.,

,.

10D12

13
12
11

IOD13
IOD1.
10015

~

~

~

t-----!
~

~

~

~
~

All

18

A7.

~

~

~

2144A1.-3

214'41.1.-3
10

I

I

10

I
81

~11
13~
1.21

IODD-10D15

Figure 29. Static RAMs on 1/0 Bus

3-374

210355-001

AP-123

1000- 10015

~
1000

12

1001
1002

13
14
15
18
17
18
19
10
11

1003
1004
1005
1005
1007
10RC
A
-IOWC

22
21

~
OARO
IOAl

~

,...!.

A17
OBO

38
39

RlO
RLl
RL2
RL3
RL4
Rl5
Rl6

OBl
OB2
OB3
OB4
OB5
OB6
OB7
RO
WR

Rl7
STa

CS
AD
RESET
ClK
8279-5

RlO
Rll
RU
RU
RU
RLS
RLI
Rl7

1
2

•

8
7
8

-F-

43
44

45
48

47
48
41
50
STRB

53

~
~
~
r--

51

I--

52

---

69

~ 80

510

Vee

15MHz

~
14

l...-7
SACK

10
M BRW

16

A4 IN914 4 ~

i5:
5

6~110n

--

117

560K

::!:

11

A37

iiSi'

t~F

RST
ClK

A3

-45

510

1Di

~

4

4
RDY1
6
ROY2
7
AEN2

ROY

10

RST

8

ClK

5

RO Y

Fli:

"1i AENi

"i
....,:.

CSYNC
8284A

Figure 30. Keyboard Controller and Clock Generator

3-375

210355-001

AP-123

510
. . - - - - - - - -...- - - - - CCLK

21.' MHz 510

r-------~-------------_+-----------

LDCHAA

1'.1

15

osc

1'.21
185163

12

f
CUi

1.
1

L-__--..,._____....___

Vcc'

1'.15

13

DCLK

F/f
CSYNC

P2

8284A

Vee·

9602

INTVTRC

A2

VCC*1
HRTC _________________________________________-J

Figure 31. Character Clock Generator and Video Sync Pulse

3-376

210355-001

PI

~

CCLK
10lI0
1QD1
1QQ2

1ODO-IOD15

IGD4

,.
17

IODI

1OD7

,.
•
18

22

,

f
2

.,

~cu

ceo ~

OBO

CC1

DBa

DBa

CCI

DBa
DBa
GB4

~)4

2
5

FGR
FGG

2
5

7
A11 4Q 10
12
sa 15

FQ8
BQR

11

10

10

CC2 ~2D
CC2 ~ 3D
CC4 I 27 11 4D
CC5 ~ 50

2Q

3D

- "*
BGQ

iiii
Wii

a

•

10

ID 74LS1741G

13

CLK

r'

DB7

1"
15

Ycc*

1A
IY

1B

2A
211
SA

2Y

3a

4A

3Y

4B
S
o

AD

4Y

_

•

54
II

BLUE

II

~
h

5
DRQ1

DAD

CCLK
cao-caa

LPEN

31

A13 1AD

1275

11

CRT CONTROLLER #0

3

iRAPHMODE

T

OCLK

I,.

10DS

12

1008

13

10010
1QD11

14
15

10012
10013
10014

17

,.
18
19

•

10

ceo
CC1
CC2

CC3
CC4
CC5
CC8

LeO
LC1

21

LC2

22

LC3

A14
8275

Oe
D.

0.

23M
22 AI
18 A10

27

21
21

0"
0..
0,

4
3
2

r-1CFIT
CONTROLLER
#1

00

~A1

t

LC1

5 AI
8 AD

FBO
FB1

15

FB2

14
13

FB3

11
10

FBS
Faa
FB7

17

,

FB4

DH

:: H
G
11 F
': E
4 0
3 C
B

f

13

1

AI

pu;-

A40

! Imr
A

Ycc'-

6 A2

r

LC2

v
,.

2732A
A28

A11 DE
-

~20

CLKINH
SRIN
7nS1..

Lii
15

l.CO-LC2

,

LDCiiiiI

'_Fa7

RYV

- ----

•!
~

7

FE Or .

3 AS
2 M
1 A7

21

6

f

4 A4

23
24
25

30

;

7

A5

10015

~

RED

4

74157

as

• DACK

30

OCLK

~

14
15

10
21

GCCLK

-,

13

lOGS

1000

iOiiC
AiiiWC
iOA1
Ciffi
iiACK1

12

--

Figure 32. CRT Controllers, Color Muniplexer, and Character Generator

AP-123

shades of color. The D CLK signal is ORed with the VSP
(video suppress) si8'nlll from the 8275, to produce complete video blanking when desired.

For each character, the foreground and background
color bits are output from Byte 0 and latched into the
74LS174, from which they are applied to the input of the
74LS157 multiplexer. Selection between foreground
and ba~kground is done by the output of the 74LSl66
parallel-to-serial converter, which operates from either
the text or graphic character generator, as appropriate.
The roles of foreground and background color may be
reversed by the RVV (reverse, video) signal from the
8275, which is exclusive-ORed with this color select
output.

Figure 33 shows the CRT Controllers #2 and #3, the
decoder for the line select function, and latches for the
video control signals. CRT controllers #2 and #3 are
operational in graphics mode only. Synchronization of
the two pairs of CRT controllers is discussed in the 8089
Display Functions Software section.
Figure 34 shows the tri-state butTers used to handle the
color information within a graphic character. The
decoded line count outputs (ROW O/-ROW 4/) are used
to select which butTer is enabled onto the bus. The
butTer A36, enabled by the GRAPH MODE sigllal, is
used to "double up" the four graphic cells to produce
eight (horizontal) dot inputs to the shift register (Figure
32).

Since the RBG (red-blue-green) inputs of the color
monitor (Aydin Controls 8039D) are AC coupled,
return-to-zero type outputs are needed to pass these
signals through the input stages. This is provided by
strobing the gate input of the 74LS157 multiplexer with
the D CLK (dot clock) signal. By varying the duty cycle
of the D CLK, the user can produce many different

- -

""'"

10110-1001'

1001

IOD2

1004
IODI

,.

12
13

"11

IODS

,.

1007

11

17

I

lORe

10

A'IIiR
il!ii'
e1I'i'i'
DACKi

21
22

081
oa2

ceo

cel

CC2
CC3

CC4
085
CCI
OBI
CCI
oa7
RO
WR
AO
ca
OACK

• cell<

2D

GCCLI<

f

22
24

H
21
27
21
21

•

AI.

DRQI

1 ....... 1

i5iiQ

10~

f-!-

r-

AM

CAl
CONTROLLER

#2
Al7

OROI

LCD
LC1

LCD-LC~

GRAPHMDDE

I'
IODS
I

.

12
13

22
24

10011

15

H
21

1DD12
10013

11

'27

17

21

10014

18

21

10015

11
I

, KIDIo

,.

7
C811
call
CB2D

31
35

2D

7

•

f
,

1275
A..

•

"12

! ...!!-

f'

iiiiWo
iiiiii1
RIiiiii
iiOWi
iiiiWi

+
2-

II

Ii
I2DI

74175

IG
r:r=I

I

CAl CONTROLLER #3

iii
1i2

11

•

22

,.

~ 11

AO

AI
At

I

•

call

21

\

1
2
3

LC2

ca,.
ca15

10

CCu(

CI7-C8ft

,

-----J

r!-

~N

117'

C87
C8I
C8I
C810
C811
C812
C811

-'41
10

10

2Q

50

3D

3D

4Q

40

2

~
7

~
I-M15
>JL

RVV
VIP
HlRC
INT~RC

CLI<
CLR

l'

Vee·

Figure 33. CRT Controller., Line Decoder, and Video Control Signal Latch

3-378

210355-001

Ap·123

C80-C820

cao
C81
C8.

ca.
C8.

cno
CBs
C87

A73

2

•
••

11
la

,.
17

lAl
lA.
lA3
lA'
.Al
2.\'
• Aa

,.

lVl 11

IV.
IV.
IV'
,Vl

1

"

.V. "s
.va

.A.
.V.
74lS!44
lG 2G

580
S81
58.
5"

sao

7

S81

a

S8.
S8a

sao

2

SB1

~

SB2

L7,

583

~
,

.

L..!!

18
I.
I.

A36

F80
F81
F8.
F83

•
7

FB.

3

FBI
F87

Fao- FB7

F84~

74LS244

y, 118

'iiCiYo

,.

iiOW1

•

GRAPH MODE

8

']'"

A7
CBI
C8.
C810
CB11

•
•••

C814

,.
,.

Cl15

17

C812
C813

1.

,.
"
I.

A54

S81
S8.

7

S"
S80
S81
S8.
S83

,.

S80
581

•
••

11

S80

74LS244

r

l' 18
C81.

ca17
C81.
C819

•
••

18

"
•"
c+•

8

11
13
15

A55

--!!.

r

74LS244

yl

58.
S8a

,

•

10

Figure 34. Trl·State Buffers for Graphic Color Information

3-379

210355-001

AP-123

The block diagram in Figure 35 shows how the text
characters are processed. The following statements apply to Figure 35:

4. The eight output signals from the text character
generator are transmitted to the parallel-ta-serial
converter.
5. The serial, horizontal dot data is transmitted to.
the multiplexer and selects foreground (dot data
bit = 0) or background (dot data bit = 1) color
signals.
6. The red, blue, and green color signals are transmitted to the color monitor..
7. CRT Controllers #2 and #3 are not operational in
text mode.

1. Byte 0, Bit 6 = 0 indicates text mode.
2. The six color signals from CRT Controller #0
(three foreground and three background) are
latched and transmitted to the multiplexer.
3. The seven character output signals and the three
line count signals from CRT Controller #1 are
transmitted, to the text character generator.

CRT
. CONTROLLER

#0

MULTIPLEXER

LATCH
CCCI-CCIi

FOREGROUND. BACKGROUND 6

6

COLOR SELECT
74LS157

75LS174

U75

r-r-r--

RED

aWE
GREEN

SEIlIAL HORIZONTAL
DOT DATA

j
CRT
CONTROLLER
#1

U75

cco-c:cs

7

LC»-LC2

3

TEXT
CHARACTER
GENERATOR

8
/,

PARALLELTO
SERIAL
CONVERTER

74LS166

2732A

Figure 35. Processing of Text Characters

3-380

210355-001

AP-123

The block diagram in Figure 36 shows how graphic
characters are processed. The following statements apply to Figure 36:

5. The four pixel signals of the selected row (based
on the row select signals) are transmitted to another octal buffer.

I. Byte 0, Bit 6 = I indicates graphic mode.

6. The octal buffer converts these four bits to eight
bits by duplicating each signal. Thus, output bits 0
and I are equal, 2 and 3 are equal, etc.

2. The six color signals from CRT Controller #0
(three foreground and three background) are
latched and transmitted to the mUltiplexer.
3. The three line count signals from CRT Controller
# I are transmitted to a one-of-eight decoder
which generates five row select signals (ROW 0ROW 4).

7. The eight output signals of the octal buffer are
transmitted to the parallel-to-serial converter.
8. The serial, horizontal dot data is transmitted to
the multiplexer and selects foreground (dot data
bit = 0) or background (dot data bit = 1) color
signals.

4. The twenty pixel signals from CRT Controllers
#1, #2, and #3 are transmitted to three octal
buffers.

CRT

CONTROLLER

••

9. The red, blue, and green color signals are transmitted to the color monitor.

lATCH

ceo-ccs

MULTIPLEXER

6

6

FOREGROUND & BACKGROUND

COLOR SELetCT

8275

CRT
CONTROLLER

74LS174

LCO-LC2

•

*'
8275

---,

74LS157

ROW.

DECODER

'--

--

RED

BLUE

GREEN

SERIAL HO AIZONTAL

ooTDATA

(1 OF 8)

ROW 1

8205

I--

6

.

CRT
CONTROLLER

BUFFER

~

•

•

8275

~
~

74LS244

BUFFER

•
---f+74LS244

PARALLElTO
SERIAL
CONVERTER

74LS166

ROW'
ROW.

..

CRT
CONTROLLER

+
BUFFER

~

•

•

'--f--'
74LS244

8275

ROW"

+
BUFFER

~

"
74LS244

Figure 36. ProceSSing of Graphic Characters
3-381

210355-001

Ap·123

cient. To preclude this, the circuit shown in Figure 37
generates a surrogate (early) DRQ signal, DRQF, using
a one-shot triggered by the trailing edge ofDRQ (DRQ 1
AND DRQ 2). The one-shat times out prior to the rising
edge of eLK in T4 of the DMA's store bus cycle.

Figure 37 shows the circuit used to synchronize the
8275s, and also the circuit used to generate the DRQF
signal. As mentioned earlier (see Figure 20), if the 8089
were to wait for a subsequent DRQ signal from the
8275s, some clock cycles would be allocated to idle
clocks, and the DMA transfer would become less effi-

IIlI'f

------4r---,

10DO

CLiffii
iOWc

GCCLK

Vee·

Vee·

Vee·

A7

CCLK

UK

SOpF

Vee

DiiQ

12
11
DRQF

Vee·

10
A2

ORQl
DRQ2
10
SCSTRB

ALi

Figure 37. Circuits to Synchronize CRT Controllers and Generate DRQF

3-382

210355-001

AP·123

Figure 38 shows the relationship between the individual
DRQ signals from the 8275s and the DRQF signal that is
sent to the 8089. DRQ 1 is the data request representing
the 8275s #0 and # I, while DRQ 2 similarly represents
the 8275s #2 and #3. The DACK 1/ and DACK 2/
signals (along with AIOWC/) are used to deactivate
DRQ 1 and DRQ 2, respectively.

Figure 39 shows the multiplexer used to control writing
of data to the dual-port RAM. When 10 and SWTC/ are
both low, the 8089 data is gated to the dual-port RAM.
When BDSELI and SWTC/ are both low, the 8086 data
is gated to the dual-port RAM. BDSELI may be active
only when the 8089 is in the I/O space. Note that the
address range for the dual-port RAM is F8000-FFFFF
as seen by the 8089, and FOOOO-F7FFF as seen by the
8086.

BYTES OAND 1

FETCH

T2

I 13 I

T4

I

BYTES 2 AND 3

STORE

Tl

I

STORE

T2

T2

I T~

ORal
(FADM 8215 #0 and #1)

'-----fl

J- - - - - - - - - - - - - - --

DR02
(FROM 8275 #2 AND #3)

Q
(FROM 9602)

DROF

(TO 8089 ORal INPUT)

DAcK1
(TO 8275 #0 AND #1)

'iiAcK2
(TO 8275 #2 AND #3)

AiOWc
(FROM 8288)

-

-

-

-

-

-

"LAST TRANSFER

Figure 38. Derivation of DRQF Signal

3-383

210355-001

A3

ADii15'

./

AO/DO-Al51015
10

SVifC

1 -"""'- 3

.,

•

iOWC

MiiDC

MwiC
iORc

22

A22
A4

I""' ~
SC STRB

19
20

.,

~

1 010
2 011

DOD
DOl

~ SiffiC
~ SWTC

DI.

002

.2!..-

L.±
~
5

'-------.!...

~ "iACK

A70
8T8

~~CA

SiOii

S-~

lK

014
DIS
004
DOS

,.
14

I

cA.

11

A22

10

..

9
10

~

13

AI. 12

MBRW

5V

lK

8282

8
A18
~

I

To..!.. FE

5V

Di-DiS

I

WSDO-WSD15

~

lIi
D'

69

68

61
62
59
50

~

!

$wiC

8

.--!--

•

Vee"

Do

T
A72
AO
AI
Bl
B.
A.

ii

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U

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AS

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is

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DE

012
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01.

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18

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AOiOO
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17

WSD.

A2ID2

16
15

WSD.
WSD4
WSDS
WSDI
WSD7

A3ID3

,.
13
I.

A71

ABlD6
A7/D7

2
3
4
S

•
~

11
1

WSDI
WSD10
WSD11
WSD12

AtlD9
A101010
A11/D11

3

AU/D12

5

WSDt3

A131013

6

WSD1.

A14/014

7

WSDts

A151D15

8

7
8

I.
12

"

8287

Yee"

WSDe

18
17
18
15

~

A4I04
,AS/05

11
1

19

5
6

9

Vee"

9

11

r-;--

••

1m

,.

8287

2

D9
Dl0

l.-iD"SiL

7

D6
D7

67

64

5
6

~.

70

63

2
3
4

In
154

7'

65
..

Vee·+-

iii

73
74
71

A8/D6

T
AO
AI

A35
SO

Bl
B.

A'
A.

B.

A4
AS

B4

B5
8&

A6
A7

Oe

B7

WSDO
WSD1

U WSD2
16 .~D.
15
14

WSD4
WSDS

13 WSD6
12 WSD?

8286

A53

•

19 WSD8
18 WSDS
17 WSD10

•

•

19
18

16 WSD11
15 WSD12
14 WSD13

'"

13 WSD14
12 WSD1S

8286

A22

==ifY10

Figure 39. Multiplexer for Writing to Dual-Port RAM

~

...l'
~

AP·123

Figure 40 shows the demultiplexer used to control reading of data from the dual-port RAM. The internal transfer acknowledge (SACK!) signal from the dynamic
RAM controller latches this data. If MRDC/ is active,
the data is then gated to the 8089. IfBD ENA! is active,
the data is gated to the Multibus for transmission to the
8086.

Figure 41 shows the multiplexer for the address inputs
to,the dual-port RAM. If the 10 signal is high, the
address on the Multibus is gated into the dual-port
RAM. If 10 is low, the address from the 8089 is gated
into the dual-port RAM.

AOIDO-A 151015
8089 BUS

-

1NT"XAc'K
ASDO-RSD1S

11
1

RSDO

••
•
•

RlI01
RSD2

RSD3

S

RSD4

RSDS
RSOS
RSD7

7
8

•

RSOS
RSD9
RS010
RS011
RSD12
RSD13

RSD1.
RSD1S

11
1

A34
STa
DID
011
01'
01'
01.
DIS
01.
017

DOD
001
DO.
DO.
D04
OOS

00.
007

,.

18
17

15

"

,."

11

AOIOO
Al/Dl
A2/D.
A3JD3
A4/D4
ASIDS

RSDO

RSOl
RSD2
RSD3

RSD'
RSDS

A6/D6

RSD6
RSD1

1.7/07

OE
8.82

AS.

•
•
•

1

••
•
•
S

7

8

•

11

"

"BIDS

000

DID
011
01.
01.
01.
DIS
01.
017

001
DO.

D03
DO.

DOs
60i

Do7

,.
,.

DO

Do-Dii

18

iii

MULTIBUS

17

D'

lS

D4
05
D.
07

"
",.

8283

AG8

"18

58
ii10
0"

A14/014

RSD13

7

,.
,.

Al5/015

RSD1.
RS01S

8
9

"

17 A1OJ010

16 "'1/011
15 "'2/D12
14 .,31013

RS010
RSD1l
RSD12

8.82

Pi

OE

1

R50S
RSD9

,."

A.'
STa

•
•
••
•

18 AIID9

S
8
7
8

•

,.

17

09

lS

Iffi

14

1m
Dl"D1S

828.

Figure 40. Demultiplexer for Reading from Dual-Port RAM

3-385

210355-001

AP·123

AD-A 11.I!HE
ALE
SAD-SA11,BHEN
P1

A3

rA6Ro

::

Aijjff

VCC

*+
2

~
1=

3
4
5

55

milS
. ADiii
AlIIii

I:
1 52

T

1051

-=
~

AD
101
102
103
104

JI

AS

8
9

A6
107
OE

11

~

=
~

11
18
17
16
15
14
13
12

SAO
101

~'SA2
SA3
SA4

A2

A3
10"AS
A6

SA5
SA6.
SA7

107

2
3

•

~
6
7
8
I

I:: ~

~

1: :

••
'5

:!

...

~

*+

1050
19
18

3
4

..!II

,.

5
6
7
8
9

108
A9
1010
1011

SA8
SA9
SA10
sllJ~

·15

&1012

13
12

SA13
5101'
SA1'

1012
,1013
101,'
A..

11
1

::
t-'
1=
127 l-

Doe
D07

SAO

18

SA1

,.
,.
15

13
12

~

SA3
SA<

SA5
SA6
SA;
107

i!!

1033
19
18

2
3

•

.16

5

6
7

SA8
5109
SA10
SA1:

15

f!AJ!.

13

51013
SA1.
SA15

•
9

8292

8287

VCC'..!j-

DI6
DI7

,.

9282

8287

VCC

STBA32
DID
DOO
DI1
DD1
DI2
DD2
DI3
D03
DO<
DI4
DIS
DDS

JJ.

1087
19
SA18
-,!.SA.!.7..
SA",1Z
18
SA19
15
BHEN

2
3
S

1016
101;
A1.8
A19

1010

1

18

2
3
4

18
17
16
15

BH~

SA18
SA1;
SA18
SA19
BH!t!

\

A7

l.r

9

9
8282

9287

iO
10

Figure 41. Multiplexer for Address Inputs to Dual-Port RAM

3-386

210355-001

AP-123

Figure 42 shows the 8202 dynamic RAM controller. The
inputs SAO-SA19 come from the multiplexer shown in
Figure 41. The dynamic RAM controller generates the
control signals (shown at the right of the page) for
operating the dynamic RAM.

8089 Display Functions Software
The 8089 display functions software consists of a single
program which is executed by the 8089 on a continuous
basis. This program performs the following functions:
Initialization for the 8089 itself and for the CRT controllers and the keyboard controller.

Figures 43 and 44 show the dynamic RAM itself.

1K

24 MHz

H(]
36

SAo-SA19

SA1

0

SA2
SA3

8

SA4
SAS

AL2

Oiffi
ffirfi

AL3
AU

i5iffi

ALS

OuTs

14
16
18

SA8
SA9

5
4

. SA10

3
2

SA11

0uT0

AL1

12

SAO
SA?

1

SA12
SA13

39

SA14

38

137

ALO

10

0uT3

0Uri

ALB
AHO
AH1
AH2

CAS

AH3
AH4

RASO

AHS
AH6

We

SA16

ill

12

XAcK

Rli

13
15

OUT4

17

OUTS

19

i5Iffii

0

27
CA
RA

28

WE

2.

IN
SA

33
9

OUT1
OUT2
I5"UT3

A12

11

13

0uT0

11

ViR

A1.

A9

7
9

21

32
31

680

8

~
~

~

PCS

P1

80

SACK

81

30

13
12 .

REFRQ/
ALE
82n.4

I

10

A22

A4

11
~

1

2
O.C.

XACK

(
L
BD

SA19

Si1i

~
.~

1

AS
1

3

J

BD

f

2"'--'

A24

Figure 42. Dynamic RAM Controller

3-387

210355-001

WSOO-WS07
RSDO-RSD7

5

OUTIH)I

t--L

r--!f'---!!..

AD A42

A2

15
3

DtN

2-

WSDO

I---

--'

l.---

WSD1

I---

A4
AS
,06

r--

l.---

.~ A3

~
~
4

A43

r--

A1

DoUT

~f-'

l.---

'RSDO

I---

>--

RSDt

A44

,---

A45

,---

l.--l.---

I--V-l.--V--

,---

r----

WSD2

r-

RSD2

,--,---

,--,---

--

WSD3

~

RSD3

RAS
CAS

I---

WE
2118-12

2118·12

2118·12

2118-12

~.

i

]!
~
~

,---

A46

t'--

A60

i---

~
~
~

fwSo.

r----

i----'

'--

R504

2118-12

>-->---

iWsii's

:.--

I·RSOs

:.-i---

2118·12

V-V-V-V-l.--V-V--

~D6
i----'
RS06

2118-12

AS

We

..

SAO

!::1

8

~

V-V--

A61

Figure 43. Dynamic RAM (Low Data Byte)

A62

r--r---

~7

V-V-V--

I-RSD7

2118-12

WSD8-WSDIS
RSDB-ASD15

OUTG-OUTI

,.--

A63

'--

r--

~

f---'

'-'-'--

iWi

,.-r--

,..--

A64

r----

,.-,.-,.--

f--i-'

r-

,.--

r-r-,..->--r--

,..-,..--

A77

A78

,..--

~

-

,---

,..-,..-,..--

~

-

r-

CA
2118~12

2118·12

:I>

~

]!

I\)

'--

r-r-r--

r--

A79

~

~

-

~

'----

2118-12

>--r->--,---

ABO

f---'

-r->---

W
A81

--'

~

~

r--

f-------'
2118-12

rLr-r
,..--

A82

t--""

,..--

l--~

---'

l--2118-12

AS

WE

~

iiiEN
10

~

I

2118-12

2118-12

Figure 44. Dynamic RAM (High Data Byte)

,..-,..--

!----

2118-12

Ap·123

addresses 0000-07FF). The CRT controllers are accessed by using addresses 4000 and 6000 on the 110
bus. Address 6000 is "CRT Controller I" and actually
refers to the first pair of 8275s. Address 4000 is "CRT
Controller 2," the second pairof8275s. Address 8000 is
a clock enable address. Write commands to this address
enable or disable the GC clock, which is the character
clock for the 8275s. Address AOOO is decoded to produce the DACK signal for the 8275s. Address COOO is
the address of the keyboard controller.

The transfer instruction which causes the DMA
transfer of the CRT refresh data to begin.
Polling routines for the keyboard and the command
buffer.
Figure 45 is a simplified flowchart showing the relationships among these three main functions. The program
begins upon receipt of the second CA (channel attention) following an lOP reset. After the initialization
processes have been completed, the program loops
continuously, alternating between DMA transfer and
polling processes. There are 48 rows of characters on
the screen. The polling processes are carried out during
the vertical retrace time, .which is the equivalent of 2
rows. Thus, it is easy to see that the DMA process uses
up 96% of the 8089's time, leaving 4% for the polling
processes.

The exact manner in which the channel program executes depends on the flag settings and parameter
values in the parameter block.
Appendix A is a flowchart for the complete channel
program. Appendix B is the corresponding ASM-89
assembly language listing. In the paragraphs to follow, a
general overview of the channel program is given. The
reader may refer to the flowchart and listing if a more
detailed description is desired.

CA

~

The first CA after lOP reset causes the 8089 to fetch the
system configuration pointer (SCP) and system configuration block (SCB) from dual-port memory. These
blocks contain certain very basic system-level information for the 8089, as explained above under Overview of

INITIALIZATION

the 8089.

The next CA causes the channel program to begin execution (at the point marked START on the flowchart).
The initialization portion of the channel program consists of the following operations:
CRT
REFRESH

Start and initialize the 8275 CRT controllers.

(OMAJ

Initialize the 8279 keyboard controller.
Initialize the dual-port variables (parameter block).
Synchronize the 8275 CRT controllers.
To initialize and synchronize the 8275s, the channel
program performs the following operations:
POLLING

Figure 45. Channel Program Simplified Flowchart

As mentioned earlier, the channel program is stored in
the 2732A EPROMs on the 1/0 bus. Figure 23 (above)
shows the address assignments for devices on the 110
bus. The 2732As occupy addresses 2000-3FFR The
8089 also uses a scratch-pad static RAM (2K bytes at
3-390

Enable the GC CLK to the 8275s by writing OIH to
110 port address 8000H.
Send the Reset command to the 8275s, followed by
the four screen format parameters (all commands
sent to the 8275s are sent first to the pair of 8275s at
address 6000H and then repeated for the second pair
of 8275s at address 4000H).
Send the Preset Counters command to the 8275s.
Disable the GC CLK by writing OOH to address
8000H.
Send the Start Display command to the 8275s.
Enable the GC CLK again by writing OIH to address
8000H. The 8275s are now initialized and
synchronized.
210355-001

(

AP-123

After the initializations have been completed, the channel program enters its main loop. The 8089 channel
control register is loaded to specify the following DMA
conditions:
Data traJ?sfer from memory to I/O port.
Destination-synchronized transfer.
GA register pointing to data source.
Termination on external event.
Termination offset = O.

CNTRL-W
CNTRL-X
CNTRL-Y
CNTRL-Z
CNTRLCNTRL-I

CNTRL-DEL

System Performance
The 8089 performs DMA transfers on 921,600 bytes of
display data per second. In addition, the 8089 executes
a polling routine (described above) during the vertical
retrace time (the equivalent of two display rows). The
DMA transfer (for a single frame) takes 16.000 milliseconds. This leaves .667 milliseconds for the polling
routine to execute, out of. a total of l/60-second CRT
refresh period. The program listed in Appendix B takes
about 300 microseconds to execute, approximately half
the available time. When the polling process is finished,
the channel program goes back to DMA mode, and
waits for the first DRQ signal from the 8275s .

The 8089 then executes the SINTR instruction, Which
causes an interrupt to be sent to the 8086 (SINTR-lline
on the Multibus), to notify the 8086 that the page transfer has been completed. The 8089 then reads the CRT
controller status registers which causes the IRQ signal
(from the 8275s to the 8089) to be reset.
The channel program then begins the polling process
which checks for ASCII commands from the 8086 (in
the command buffer) and also for key depressions at the
keyboard. In addition to the alphanumeric characters,
. the channel program recognizes the following control
characters: '
Code
Ql
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11

12
13

14
15
16

Set Color to White
Abort Line
Cursor Right
Cursor Down and Left
Cursor Up
Cursor Home
Recall EEPROM Buffer

The first four commands listed above are not recognized if they originate from the physical keyboard, but
are recognized if they appear as ASCII commands in
the command buffer (that is, if they come from the
8086). Refer to the flowchart (Appendix A) for more
details on how the channel program responds to the
control characters:

The source for the DMA transfer (display page 0 or 1) is
then selected according to the value of DSPLY_PG-PTR (the display page pointer initialized by the
host CPU) in the parameter block. The CRT character
clock is then started and the DMA transfer begins.
When the entire screen has been refreshed, the 8275s
activate the 8089's EXT input.

Character
CNTRL-A
CNTRL-B
CNTRL-C
CNTRL-D
CNTRL-E
CNTRL-F
CNTRL-G
CNTRL-H
CNTRL-I
CNTRL-J
CNTRL-K
CNTRL-L
CNTRL-M
CNTRL-N
CNTRL-O
CNTRL-P
CNTRL-Q
CNTRL-R
CNTRL-S
CNTRL-T
CNTRL-U
CNTRL-V

17
18
19
lA
IE
lC
IF

While the polling routine is executing, the 8089 makes
most of its memory accesses in the I/O space, and the
dual-port RAM is available to the 8086. When the 8089
returns to the DMA routine, however, it hangs the
dual-port RAM while waiting for DRQ. This occurs
because the fetch from the dual-port RAM deactivates
the 10 signal which locks out the 8086 from the dualport RAM. The 10 signal is then not activated until
DRQ is received and the data is written to the CRT
controllers. This can adversely affect system throughput. Therefore, if it is desired to increase the. 8086's
access to the dual-port RAM during this period, the
user should insert NOPs into the channel program so
that it spends more time in the I/O space before returning to DMA.

Description
Monitor Inhibit
Monitor Uninhibit
EEPROM Inhibit
EEPROM Uninhibit
Turn on EEPROM Buffer
Display Page 0
Display Page 1
Backspace
TAB (Every 8 Characters)
Linefeed
EEPROM Buffer Off
Erase Page
Carriage Return
Set Background Color
Set Foreground Color
Set Color to Black
Set Color to Red
Set Color to Green
Set Color to Yellow
Set Color to Blue
Set Color to Magenta
Set Color to Cyan

The 8086 may also access dual-port RAM during the
DMA transfer. The dual-port RAM is available to the
8086 on approximately a 50% duty cycle (during the
store portion of the DMA transfer cycle). The 8089's
store cycle.is 800 nanoseconds long (assuming a 5 MHz
clock). The 8086's access to dual-port RAM (assuming
an 8 MHz clock) takes 500 nanoseconds. However,
since the two processors operate asynchronously, the
8086 may begin its access at any point during the 8089's
3-391

210355-001

AP·123

DMA store cycle. Since the 8086 is the master relative
to the dual-port RAM, the ready signal for the 8089's
next fetch operation will not be generated until the 8086
is through. Thus, on occasion, the 8089 will have to
wait.

High-speed DMA transfers (up to 1.25 megabytes/second) without wait states.
Capabilities of a CPU and a DMA controller in a
single 40-pin package.
Support of concurrent operation for the system CPU
and the 110 processor. Ability to access memory and
address devices on both a system bus and a separate
110 bus.
Flexible, memory-based communications between
the 110 processor and the system CPU.

Each row of characters requires 256 microseconds of
DMA transfer time if no such wait states occur. The
repetition rate for rows of characters is 333 microseconds (1/3000 second). Thus, the accumulated wait
states due to the 8086's access to dual-port RAM may
total 77 microseconds before any underrun occurs. The
8086 programs should be written in such a manner that
the added wait states do not total 77 microseconds
during anyone period of 333 microseconds. The most
important single factor in assuring this is to avoid making long burst transfers to or from the dual-port RAM.
If an underrun does occur, the entire screen will be
blanked until the beginning of the next frame.
Aside from the shared access to dual-port RAM, the
two processors may operate concurrently with no coordination necessary. Operations performed by the 8086
(such as numeric processing of display data) may be
programmed without regard to the o:verhead associated
with lOP operations.

Capability for I-megabyte addressing in the system
space.
Capability for 16-bit DMA transfer, with external
event termination.
Support of modular, subsystem development effort
due to the simple software interface (memory-based
communications, plus channel attention and interrupt signals) and the simple hardware interface (CA,
SEL, and SINTR lines).
The following 8089 capabilities were not used in the
design described in this note, but may be useful in other
graphic CRT systems or 110 proce,ssing systems:

Conclusions

Two channels, each of which may execute instructions and perform DMA transfers.
Bit manipUlation instructions.
Support of both 8-bit and 16-bit bus width in the
system space and in the 110 space.
Enhanced DMA capabilities, including:

This application note has demonstrated that a high-performance, color-graphic CRT terminal can be Gonveniently built
using the Intel 8089 microprocessor system, This system
utilizes a high-performance 8086 CPU operating at 8 MHz
and an 8089 I/O processor operating at 5 MHz.

Translation (e.g., ASCII to EBCDIC code).
Termination on masked compare.
Word assembly/disassembly (8-bit word to/from 16bit w<;>rd).

In particular, the unique abilities of the 8089 lend themselves to the graphic CRT application by enabling a true
multiprocessing approach to be used. The following list
summarizes the capabilities used in this specific design:

Memory-to-memory or 1I0-to-II0 transfer.
Synchronization on source, destination, or neither.

3-392

210355-001

APPENDIX AlAP-123

INITIALIZATION AND MAIN LOOP
(

STAP-r

)

--,...------'

+

n

START
AND INITIALIZE 8275
CRT CONTROLLERS

STRIN -

'" .., '!I~I~L

'---

The 8087 adds 15 pF to the total capacitive loading on
the shared address/data and status signals. Like the
8086 or 8088, the 8087 can drive a total of 100 pF
capacitive load above its own self load and sink 2.0 rnA
DC current on these pins. This AC and DC drive is sufficient for an 86121 system with two sets of data
transceivers, address latches, and bus controllers for
two separate busses, an on-board bus and an off-board
MUL TIBUSTM using the 8289 bus arbiter.
Later in this section, what to do with the 8087 INT and
RQ/GT pins, is covered.
It is possible to leave a prewired 4O-pin socket on the

board for the 8087. Adding the 8087 to such a system is
as easy as just plugging it in. If a program attempts to
execute any numeric instructions without the 8087 installed, they will be simply treated as NOP instructions
by the host. Software can test for the existence of the
8087 by initializing it and then storing the control word.
The program of Figure 6 illustrates this technique.

3-425

8282

8282
8088~o:3o~P_;_
QOOOOOOO

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MRDC MWfC AMWC iNfAl
71

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141

~II~II~II~I

AP·113
cution. The host's coprocessor interface can read a
value from memory, or identify a region of memory the
coprocessor should use while performing its function.
All the addressing modes of the host are available to
identify memory based operands to the coprocessor.

WHAT IS THE iAPX 86, 88
COPROCESSOR INTERFACE?
The idea of a coprocessor is based on the observation
that hardware specially designed for a function is the
fastest, smallest, and cheapest implementation. But, it is
too expensive to incorporate all desired functions in
general purpose hardware. Few applications could use
all the functions. To build fast, small, economical systems, we need some way to mix and match components
supporting specialized functions.

Concurrent Execution of Host and
Coprocessor
After the coprocessor has started its operation, the host
may continue on with the program, executing it in parallel while the coprocessor performs the function started
earlier. The parallel operation of the coprocessor does
not normally affect that of the host unless the coprocessor must reference memory or I/O-based operands.
When the host releases the local bus to the coprocessor,
the host may continue to execute from its internal instruction queue. However, the host must stop when it
also needs the local bus currently in use by the coprocessor. Except for the stolen memory cycle, the operation of the coprocessor is transparent to the host.

Purpose of the Coprocessor' Interface
The coprocessor interface of the general purpose 8086
or 8088 microprocessor provides a way to attach specialized hardware in a simple, elegant, and efficient manner. Because the coprocessor hardware is specialized, it
can perform its job much faster than any general purpose CPU of similar size and cost. The coprocessor
interface simply requires connection to the host's local
address/data, status, clock, ready, reset, test and request/grant signals. Being attached to the host's local
bus gives the coprocessor access to all memory and 110
resources available to the host.

This parallel operation of host and coprocessor is called
concurrent execution. Concurrent execution of instructions requires less total time then a strictly sequential
execution would. System performance will be higher
with concurrent execution of instructions between the
host and coprocessor.

The coprocessor is independent of system configuration. Using the local bus as the connection point to the
host isolates the coprocessor from the partil;:ular system
configuration, since the timing and function of local bus
signals are fixed.

SYNCHRONIZATION
In exchange for the higher system performance made
available by concurrent execution, programs must provide what is called synchronization between the host
and coprocessor. Synchronization is necessary whenever
the host and coprocessor must use information available
from the other. Synchronization involves either the host
or coprocessor waiting for the other to finish an operation currently in progress. Since the host executes the
program, and has program control instructions like
jumps, it is given responsibility for synchronization. To
meet this need, a special host instruction exists to synchronize host operation with a coprocessor.

Software's View of the Coprocessor
The coprocessor interface allows specialized hardware
to appear as an integral part of the host's architecture
controlled by the host with special instructions. When
the host encounters these special instructions, both the
host and coprocessor recognize them and work together
to perform the desired function. No status polling loops
or command stuffing sequences are required by software to operate the coprocessor.
More information is available to a coprocessor than
simply an instructio.n opcode and a signal to begin exe-

Test for the existence of an 8087 in the system. This code will always recognize an 8087
independent of the TEST pin usage on the host. No deadlock is possible. Using the 8087
emulator will not change the function of this code since ESC instructions are used. The word
variable control is used for communication between the 8087 and the host. Note: if an 8087 is
present, it will be initialized. Register ax is not transparent across this code.
ESC
XOR
MOV
ESC
OR
JZ

28, bx
ax, ax
control, ax
15, control
ax, control
no_8087

FNINIT if 8087 is present. The contents of bx is irrelevant
These two instructions insert delay while the 8087 initializes itself
Clear intial control word value
FNSTCW if 8087 is present
Control =03ffh if 8087 present
Jump if no 8087 is present
Figure 6. Test for Existence of an 8087

3-427

207865-001

AP·113
The host coprocessor synchronization instruction,
called "WAIT", uses the TEST pin of the host. The
coprocessor can signal that it is still busy to the host via
this pin. Whenever the host .executes a wait instruction,
it will stop program execution while the TEST input is
active. When the TEST pin becomes inactive, the host
will resume program execution with the next instruction
following the WAIT. While waiting on the TEST pin,
the host can be interrupted at 5 clock intervals; however, after the TEST pin becomes inactive, the host will
immediately execute the next instruction, ignoring any
pending interrupts between the WAIT aIid following
.
instruction.
COPROCESSOR CONTROL

The host has the responsibility for overall program control. Coprocessor operation is initiated by special instructions encountered by the host. These instructions
are called "ESCAPE" instructions. When the host en~
counters an ESCAPE instruction, the coprocessor is
expected to perform the action indicated by the instruction. There are 576 different ESCAPE instructions,
allowing the coprocessor to perform many different
actions.
The host's coprocessor interface requires the coprocessor to recognize when the host has encountered an
ESCAPE instruction. Whenever the host begins executing a new instruction, the coprocessor must look to see
if it is an ESCAPE instruction. Since only the host
fetches instructions and executes them, the coprocessor
must monitor the instructions being executed by the
host.

Host Queue Tracking
The host can fetch an instruction at a variable length
time before the host executes the instruction. This is a
characteristic of the instruction queue of an 8086 or
8088 microprocessor. An instruction queue allows prefetching instructions during times when the local bus

would be otherwise idle. The end benefit is faster execution time of host instructions for a given memory bandwidth.
The host does not externally indicate which instruction
it is currently executing. Instead, the host indicates
when it fetches an instruction and when, some time
later, an opcode byte is decoded and executed. To identify the actual instruction the host fetched from its
queue, the coprocessor must also maintain an instruc·
tion stream identical to the host's.
Instructions can be fetched in byte or word increments,
depending on the type of host and the destination address of jump instructions executed by the host. When
the host has filled its queue, it stops prefetching instructions. Instructions are removed from the queue a byte at
a time for decoding and execution. When a jump occurs, the queue is emptied. The coprocessor follows
these actions in the host by monitoring the host's bus
status, queue status, and data bus signals. Figure 7
shows how the bus status signals and queue status
signals are encoded.
IGNORING 1/0 PROCESSORS

The host is not the 'only local bus master capable of
fetching instructions. An Intel 8089 lOP can generate
instruction fetches on the local bus in the course of executing a channel program in system memory. In this
case, the status signals S2, SI, and SO generated by the
lOP are identical to those of the host. The coprocessor
must not interpret these instruction prefetches as going
to the host's instruction queue. This problem is solved
with a status signal called S6. The S6 signal identifies
when the local bus is being used by the host. When the
host is the local bus master, S6 = 0 during T2 and T3 of
the memory cycle. All other bus masters must set S6 = 1
during T2 and T3 of their instruction prefetch cycles.
Any coprocessor must ignore activity on the local bus
when S6= 1.

S2

S1

SO

Function

QS1

QSO

Host Function

Coprocessor Activity

0

0

0

Interrupt Acknowledge

0

0

No Operation

0

0

1

Read I/O Port

0

1

First Byte

Decode Opcode Byte

0

1

0

Write I/O Port

1

0

Empty Queue

Empty Queue

1

1

Subsequent Byte

Flush Byte or if 2nd

No Queue Activity

0

1

1

Halt

1

0

0

Code Fetch

Byte of Escape

1

0

1

Read .Data Memory

Decode it

1

1

0

Write Data Memory

1

1

1

Idle

Figure 7.
3-428

207865-001

Ap·113
They, together with the R/M field, bits 2 through 0,
determine the addressing mode and how many subsequent bytes remain in the instruction.

DECODING ESCAPE INSTRUCTIONS

To recognize ESCAPE instructions, the coprocessor
must examine all instructions executed by the host.
When the host fetches an instruction llyte from its internal queue, the coprocessor must do likewise.
The queue status state, fetch opcode byte, identifies
when an opcode byte is being examined by the host. At
the same time, the coprocessor will check if the byte fetched from its internal instruction queue is an ESCAPE
opcode. If the instruction is not an ESCAPE, the
coprocessor will ignore it. The queue status signals for
fetch subsequent byte and flush queue let the
coprocessor track the host's queue without knowledge
of the length and function of host instructions and addressing modes.

All ESCAPE instructions start with the high-order
5-bits of the instruction being 11011. They have two
basic forms. The non-memory form, listed here, initiates some activity in the coprocessor using the nine
available bits of the ESCAPE instruction to indicate
which function to perform.
MOD

11 I

1

I

I

I

I

I

COPROCESSOR INTERFACE TO MEMORY

The design of a coprocessor is considerably simplified if
it only requires reading memory values of 16 bits or less.
The host can perform all the reads with the coprocessor
latching the value as it appears on the data bus at the
end of T3 during the memory read cycle. The coprocessor need never become a local bus master to read or
write additional information.

I

I

Memory reference forms of the ESCAPE instruction,
shown in Figure 8, allow the host to point out a memory
operand to the coprocessor using any host memory addressing mode. Six bits are available in the memory
reference form to identify what to do with the memory
operand. Of course, the coprocessor may not recognize
all possible ESCAPE instructions, in which case it will
simply ignore them.

If the coprocessor must write information to memory,
or deal with data values longer than one word, then it
must save the memory address and be able to become a
local bus master. The read operation performed by the
host in the course of executing the ESCAPE instruction
places the 2O-bit physical address of the operand on the
address/data pins during T1 of the memory cycle. At
this time the coprocessor can latch the address. If the
coprocessor instruction also requires reading a value, it
will appear on the data bus during T3 of the memory
read. All other memory bytes are addressed relative to
this starting physical address.

Memory reference forms of ESCAPE instructions are
identified by bits 7 and 6 of the byte following the
ESCAPE opcode. These two bits are the MOD field of
the 8086 or 8088 effective address calculation byte.
MOD

11111011111
'15

'14 '13 '12 '11

I
'10

'9

RIM

1°1 0 1 I

I
'8

'7

'6

'5

111111°1
'4

'3

'2

MOD

11111 ° 111111
'15 '14

'13 '12

'11

'10

I
'9

'8

'7

'6

I
'5

I
'4

'15· 114 '13

112

111

I
'10

1°1 1 1 I

I
'9

'8

17

IS

15

I
'3

I
14

I
'2

•

MOD

11111011111

'15 '14

'13 '12 '11

I
'10

I
'9

'7

'6

'1

'0

13

I
'2

10

I
'5

I
'4

I
'3

I
'2

I

I

16·blt direct displacement
I I I
I I I I

I

I

I

I

I

07

D7

05

04

03

D5

D4

1

D8

a·blt displacement
I I I I I I
06

D6

16·blt displacement
I I
I I I

D15 D14 D13 D12 D11 D10 D9

I

I

D8

02

01

DO

D7

D6

DS

I
D3

I
D4

I
D2

I
D3

I

D1

I
D2

D1

I

DO

I

I

DO

I

I

I
'1

I

D15 D14 D13 D12 D11 D10 Dg

I

I
'1

I

I

I

RIM

1°1°1
'8

'0

RIM

I

MOD

11111011111

'1

RIM

111 ° I

Instruction

The memory reference ESCAPE instructions have two
purposes: identify a memory operand and for certain instructions, transfer a word from memory to the
coprocessor.

Escape Instruction Encoding

I

E~cape

Host's Response to an

The host performs one of two possible actions when
encountering an ESCAPE instruction: do nothing or
calculate an effective address and read a word value
beginning at that address. The host ignores the value of
the word read. ESCAPE instructions change no registers in the host other than advancing IP. So, if there is
no coprocessor, or the coprocessor ignores the ESCAPE
instruction, the ESCAPE instruction is effectively a
NOP to the host. Other than calculating a memory address and reading a word of memory, the host makes no
other assumptions regarding coprocessor activity.

'0

Figure 8. Memory Reference Escape Instrucllon Forms

3-429

207865-001

AP·113
Whether the coprocessor becomes a bus master or not,
if the coprocessor has memory reference instruction
forms, it must be able to identify the memory'read performed by the host in the course of executing an
ESCAPE instruction.
Identifying the memory read is straightforward, requiring all the following conditions to be met:
'
1) A MOD value of 00, 01, or 10 in the second byte
of the ESCAPE instruction executed by the host.

The next section examines how the 8087 uses the
coprocessor interface of the 8086 or 8088.

8087 COPROCESSOR OPERATION
The 8086 or 8088 ESCAPE instructions provide 64
memory reference opcodes and 512 non-memory reference opcodes. The 8087 uses 57 of the memory reference
forms and 406 of the non-memory reference forms. Figure 9 shows the ESCAPE instructions not used by the
8087.

2) This is the first data read memory cycle performed
by the host after it encountered the ESCAPE instruction. In particular, the bus status signals
S2-SO will be 101 and S6 will be O.
The coprocessor must continue to track the instruction
queue of the host while it calculates the memory address
and reads the memory value. This is simply a matter of
following the fetch su~sequent byte status commands
occurring on the queue status pins.

11 1 1°1 1 1 1 1

'is

'14 '13 '12 '11

110
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1

HOST PROCESSOR DIFFERENCES
I

A coprocessor must be aware of the bus characteristics
of the host processor. This determines how the host will
read the word operand of a memory reference ESCAPE
instruction. If the host is an 8088, it will always perform
two byte reads at sequential addresses. But if the host is
an 8086, it can either perform a single word read or two
byte reads to sequential addresses.
The 8086 places no restrictions on the alignment 'of
word operands in memory. It will automatically perform two byte operations for word operands starting at
an odd address. The two operations are necessary since
the two bytes of the operand exist in two different memory words. The coprocessor should be able to accept the
two possible methods of reading a word value on the
8086.
A coprocessor can determine whether the 8086 will perform one or two memory cycles as part of the current
ESCAPE instruction execution. The ADO pin during TI
of the first memory read by the host tells if this is the
only read to be performed as part of the ESCAPE instruction. If this pin is a 1 during Tl of the memory
cycle, the 8086 will immediately follow this memory
read cycle with another one at the next byte address.

19
0
0'
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1

IS

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1

15
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

I' 1

'10

'8

14
1
1
1
0
0
0
1
1
1
0
0
0
1

13
0
0
0
0
0
1
0
1
1
0

11 1 1 I
'8 "7

12
0
0
1
0
1
1
1
0
11
1

1

'5

'8

11 10
0 1
1 -

1

'0

1
4

1 -

2

2
1
1
1

-1
1
1

-1

2

1
2

1

8
18

----0
0
0
0
1

I
'1

2

-1
1
0
1
1
0
1

I
'2

Available codas

---- . -0

I

'3

'4

32

0 0 0 1
0 O· 1 0
0 1-1---

1
1
4
8'
18

----

--

105 total

Available Non·Memory Reference Escape Instructions
.

MOD

11 1 1°1 1 1 1 1
'15 '14 '13 '12 '11

110
0
0
0
0
1
1
1

Coprocessor Interface Summary
The host ESCAPE instructions, coprocessor interface,
and WAIT instruction allow easy extension of the host's
architecture with specialized processors. The 8087 is
such a processor, extending the host's architecture as
seen by the programmer. The specialized hardware provided by the 8087 can greatly improve system performance economically in terms of both hardware and
software for numerics applications.

19 IS
0 1
1 1
1.1
1 1
0 1
0 1
1 1

15
0
0
1
1
0
1
0

I

'10

'9

14
0
0
0
1
0
0
0

13
1
1
0
0
1
1
1

Available Memory

I

I
'8

I
'7

~ference

RIM

I
'8

I

'5

I
'4

I

'3

1
'2

'1

1
'0

Escape Instructions

Figure 9.

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\

AP·113

Using the 8087 With Custom
Coprocessors
Custom coprocessors, a designer may care to develop,
should limit their use pf ESCAPE instructions to those
not used by the 8087 to prevent ambiguity about
whether anyone ESCAPE instruction is intended for a
numerics or other custom coprocessor. Using any
escape instruction for a custom coprocessor may conflict with opcodes chosen for future Intel coprocessors.
Operation of an 8087 together with other custom coprocessors is possible under the following constraints:
1) All 8087 errors are masked. The 8087 will update its
opcode and instruction address registers for the unused opcodes. Unused memory reference instructions will also update the operand address value.
Such changes in the 8087 make software-defined
error handling impossible.
2) If the coprocessors provide a BUSY signal, they must
be ORed together for connection to the host TEST
pin. When the host executes a WAIT instruction, it
does not know which coprocessor will be affected by
the following ESCAPE instruction. In general, all
coprocessors must be idle before executing the
ESCAPE instruction.

Operand Addressing by the 8087
The 8087 has seven different memory operand formats.
Six of them are longer than one 'word. All are an even
number of bytes in length and are addressed by the host
at the lowest address word.
When the host executes a memory reference ESCAPE
instruction intended to cause a read operation by the
8087, the host always reads the low-order word of any
8087 memory operand. The 8087 will save the address
and data read. To read any subsequent words of the
operand, the 8087 must become a local bus master.
When the 8087 has the local bus, it increments the 2O-bit
physical address it saved to address the remaining words
of the operand.
When the ESCAPE instruction is intended to cause a
write operation by the 8087, the 8087 will save the address but ignore the data read. Eventually, it will get
control of the local bus, then perform successive write,
increment address operations writing the entire data
value.

8087 OPERATION IN IAPX 86,88 SYSTEMS
The 8087 will work with either an 8086 or 8088 host.
The identity of the host determines the width of the
local bus path. The 8087 will identify the host and
adjust its use of the data bus accordingly; 8 bits for an
8088 or 16 bits for an 8086. No strapping options are
required by the 8087; host identification is automatic.
The 8087 identifies the host each time the host and 8087
are reset via the RESET pin. After the reset signal goes
inactive, the host will begin instruction execution at
memory address FFFFOI6.
If the host is an 8086 it will perform a word read at that

address; an 8088 will perform a byte read.
The 8087 monitors pin 34 on the first memory cycle
after power up. If an 8086 host is used, pin 34 will be the
BHE signal, which will be low for that memory cycle.
For an 8088 host, pin 34 will be the SSO signal, which
will be high during Tl of the ftrst memory cycle. Based
on this signal, the 8087 will then configure' its data bus
width to match that of the host local bus.
For 88/2X systems, pin 34 of the 8087 may be tied to
Vee if not connected to the 8088 SSO pin.
The' width of the data bus and alignment of data operands has no effect, except for execution time and number of memory cycles performed, on 8087 instructions.
A numeric program will always produce the same results
on an 8612X or 8812X with any operand alignment. All
numeric operands have the same relative byte orderings
independent of the host and starting address.
The byte alignment of memory operands can affect the
performance of programs executing on an 86/2X. If a .
word operand, or any numeric operand, starts on an
odd-byte address, more memory cycles are required to
access the operand than if the operand started on an
even address. The extra memory cycles will lower system
performance.
The 86/2X will attempt to minimize the number of extra
memory cycles required for odd-aligned operands. In
these cases, the 8087 will perform first a byte operation,
then a series of word operations, and finally a byte
operation.
88/2X instruction timings are independent of operand
alignment, since byte operations are always performed.
However, it is recommended to align numeric operands
on even boundaries for maximum performance in case
the program is transported to an 8612X.

3-431

207865-001

AP·113

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3-432

207865-001

Ap·113
RQIGT CONNECTION

As Table 2 implies, three factors determine when the
host will release the local bus:

Two decisions must be made when connecting the 8087
to a system. The first is how to interconnect the RQ/GT
signals of all local bus masters. The RQ/GT decision affects the response time to service local bus requests from
other local bus masters, such as an 8089 lOP or other
coprocessor. The interrupt connection affects the
response time to service an interrupt request and how
user-interrupt handlers are written. The implications of
how these pins are connected concern both the hardware
designer and programmer and must be understood by
both.
The RQ/GT issue can be broken into three general categories, depending on system configuration: 86120 or
88/20, 86/21 or 88121, and 86122 or 88122. Remote
operation of an lOP is not effected by the 8087 RQ/GT
connection.

I) What type of host is there, an 8086 or 8088?
2) What is the current instruction being executed?
3) How is the lock prefix being used?
An 8086 host will not release the local bus between the
two consecutive byte operations performed for oddaligned word operands. The 8088, in contrast, will never
release the local bus between the two bytes of a word
transfer, independent of its byte alignment.
Host operations such as acknowledging an interrupt will
not release the local bus for several bus cycles.
Using a lock prefix in front of a host instruction
prevents the host from releasing the local bus during the
execution of that instruction.

8087 RQIGT Function

iAPX 86120, 88120
For an 86120 or 88120 just connect the RQ/GTO pin of
the 8087 to RQ/GTl of the host (see Figure S), and skip
forward to the interrupt discussion on page IS.

iAPX 86121, 88121
For an 86121 or 88121, connect RQ/GTO of the 8087 to
RQ/GTI of the host, connect RQ/GT of the 8089 to
RQ/GTl of the 8087 (see Figure 10, page 12), and skip
forward to the interrupt discussion on page 15.
The RQ/GTl pin of the 8087 exists to provide one 1/0
processor with a low maximum wait time for the local
bus. The maximum wait times to gain control of the
local bus for a device attached to RQ/GTl of an 8087
for an 8086 or 8088 host are shown in Table 2. These
numbers are all dependent on when the host will release
the local bus to the 8087.

The presence of the 8087 in the RQ/GT path from the
lOP to the host has little effect on the maximum wait
time seen by the lOP when requesting the local bus. The
8087 adds two clocks of delay to the basic time required
by the host. This low delay is achieved due to a preemptive protocol implemented by the 8087 on RQ/GTl.
The 8087 always gives higher priority to a request for
the local bus from a device attached to its RQ/GTl pin
than to a request generated internally by the 8087. If the
8087 currently owns the local bus and a request is made
to its RQ/GTl pin, the 8087 will finish the current
memory cycle and release the local bus to the requestor.
If the request from the devices arrives when the 8087
does not own the local bus. then the 8087 will pass the
request on to the host via its RQ/GTO pin.

Table 2. Worst Case Local Bus Request Wait Times in Clocks
I

System
Configuration

No Locked
Instructions

Only Locked
Exchange

Other Locked
Instructions

iAPX 86121
even aligned words

151

35 1

max (lSI' *)

iAPX 86121
odd aligned words

151

43 2

max (43 2, *j

iAPX 88121

151

43 2

max (43 2, *j

Notes: 1. Add two clocks for each wait state inserted per bus cycle
2. Add four clocks for each wait state inserted per bus cycle
• Execution time of longest locked instruction

3-433

207865-001

AP·113

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3-434

207865-001

Ap·113

IAPX 86/22, 88122

ditional clocks for an 8086 or 8088 respectively, for the
equivalent save and restore operations. These operations appear in ·time-critical context-switching functions
of an operating system or interrupt handler. This technique has no affect on the maximum wait time seen by
10PB or wait time seen by 10PA due to 10PB.

An 86122 system offers two alternates regarding to
which lOP to connect an I/O device. Each lOP will offer a different maximum delay time to servide an I/O request. (See Fig. 11)
The second 8089 (lOPA) must use the RQ/OTO pin of
the host. With two lOPs the designer must decide which
lOP services which 110 devices, determined by the maximum wait time allowed between when an I/O device requests lOP service and the lOP can respond. The maximum service delay times of the two lOPs can be very
different. It makes little difference which of the two
host RQ/OT pins are used.

Which lOP to connect to which I/O device in an 86122
or 88/22 system will depend on how quiCkly an 110 request by the device must be serviced by the lOP. This
maximum time must be greater than the sum of the
maximum delay of the lOP and the maximum wait time
to gain control of the local bus by the lOP.
If neither lOP offers a fast enough response time, consider remote operation of the lOP.

The different wait times are due to the non-preemptive
nature of bus grants between the two host RQ/OT pins.
No communication of a need to use the local bus is
possible between lOPA and the 8087/IOPB combination. Any request for the local bus by the 10PA must
wait in the worst case for the host, 8087, and 10PB to
finish their longest sequence of memory cycles. 10PB
must wait in the worst case for the host and 10PA to
finish their longest sequence of memory cycles. The
8087 has little effect on the maximum wait time of
10PB.

8087 INT Connection
The next decision in adding the 8087 to an 8086 or 8088
system is where to attach the INT signal of the 8087.
The INT pin of the 8087 provides an external indication
of software-selected numeric errors. The numeric program will stop until something is done about the error.
Deciding where to connect the INT signal can have important consequences on other interrupt handlers.

WHAT ARE NUMERIC ERRORS?

DELAY EFFECTS OF THE 8087

A numeric error occurs in the NPX whenever an operation is attempted with invalid operands or attempts to
produce a result which cannot be represented. If an incorrect or questionable operation is attempted by a program, the NPX will always indicate the event. Examples
of errors on the NPX are: 1/0, square root of - 1, and
reading from an empty register. For a detailed description of when the 8087 detects a numeric error, refer to
the Numerics Supplement. (See Lit. Ret).

The delay effects of the 8087 on 10PA can be significant. When executing special instructions (FSAVE,
FNSAVE, FRSTOR), the 8087 can perform SO or 96
consecutive memory cycles with an 8086 or 8088 host,
respectively. These instructions do not affect response
time to local bus requests seen by an 10PB.
If the 8087 is performing a series of memory cycles while
executing these instructions, and 10PB requests the
local bus, the 8087 will stop its current memory activity,
then release the local bus to 10PB.

WHAT TO DO ABOUT NUMERIC ERRORS

The 8087 cannot release the bus to lOPA since it cannot
know that 10PA wants to use the local bus, like it can
for IOPB.

REDUCING 8087 DELAY

Two possible courses of action are possible when a
numeric error occurs. The NPX can itself handle the
error, allowing numeric program execution to continue
undisturbed, or software in the host can handle the
error. To have the 8087 handle a numeric error, set its
associated mask bit in the NPX control word. Each
numeric error may be individually masked.

E~FECTS

For 86122 or 88122 systems requiring lower maximum
wait times for lOPA. it is possible to reduce the worst
case bus usage of the 8087. If three 8087 instructions are
never executed; namely FSAVE, FNSA VE, or
FRSTOR, the maximum number of consecutive memory cycles performed by the 8087 is 10 or 16 for an 8086
or 8088 host respectively. The function of these instructions can be emulated with other 8087 instructions.
Appendix B shows an example of how these three instructions can be emulated. This improvment does have
a cost, in the increased execution time of 427 or 747 ad-

The NPX has a default fixup action defined for all possible numeric errors when they are masked. The default
actions were carefully selected for their generality and
safety.
For example, the default fixup for the precision error is
to round the result using the rounding rules currently in
effect. If the invalid error is masked, the NPX will
generate a special value called indefinite as the result of
any invalid operation.

3-435

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AP·113
NUMERIC ERRORS (CON'T)

Any arithmetic operation with an indefinite operand
will always generate an indefinite result. In this manner,
the result of the original invalid operation will propagate throughout the program wherever it is used.
When a questionable operation such as multiplying an
urtnormal value by a normal value occurs, the NPX will
signal this occurrence by generating an unnormal result.
The required response by host software to a numeric
error will depend on the application. The needs of each
application must be understood when deciding on how
to treat numeric errors. There are three attitudes
towards a numeric error:
I) No response required. Let the NPX perform the
default fixup.
2) Stop everything, something terrible has happened!
3) Oh, not again! But don't disrupt doing something
more important.
SIMPLE ERROR HANDLING

Some very simple applications may mask all of the
numeric errors. In this simple case, the 8087 INT signal
may be left unconnected since the 8087 will never assert
this signal. If any numeric errors are detected during the
course of executing the program, the NPX will generate
a safe result. It is sufficient to test the final results of the
calculation to see if they are valid.

The 8086 Family Numerics Supplement recommends
masking all errors except invalid. (See Lit. Ref.). In this
case the NPX will safely handle such errors as
underflow, overflow, or divide by zero. Only truly questionable operations will disturb the numerics program
execution.
An example of how infinities and divide by zero can be
harmless occurs when calculating the parallel resistance
of several values with the standard formula (Figure 12).
If RI becomes zero, the circuit resistance becomes O.
With divide by zero and precision masked, the NPX will
produce the correct result.
NUMERIC EXCEPTION HANDLING

For some applications; a numeric error may not indicate
a severe problem. The numeric error can indicate that a
hardware resource has been exhausted, and the software
must provide more. These cases are called exceptions
since they do not normally arise.
Special host software will handle numeric error exceptions when they infrequently occur. In these cases,
numeric exceptions are expected to be recoverable
although not requiring immediate service by the host. In
effect, these exceptions extend the functionality of the
NDP. Examples of extensiorts are: normalized only
arithmetic, extending the register stl!-ck to memory, or
tracing special data values.

Special values like not-a-number (NAN), infinity, indefinite, denormals, and unnormals indicate the type
and severity of earlier invalid or questionable operations.
SEVERE ERROR HANDLING

For dedicated applications, programs should not generate or use any invalid operands. Furthermore, all numbers should be in range. An operand or result outside
this range indicates a severe fault iIi, the system. This
situation may arise due to invalid input values, program
error, or hardware faults. The integrity of the program
and hardware is in question, and immediate action is required.
In this case, the INT signal can be used to interrupt the
program currently running. Such an interrupt would be
of high priority. The interrupt handler responsible for
numeric errors might perform system integrity tests and
then restart the system at a known, safe state. The
handler would not normally return to the point of errpr.

R,

Unmasked numeric errors are very useful for testing
programs. Correct use of synchronization, (Page 21),
allows the programmer to find out exactly what
operands, instruction, and memory values caused the
error. Once testing has finished, an error then becomes
much more serious.

Equivalent resistance =
1

.1

1

R1

R2

R3

-+-+-

Figure 12. Infinity Arithmetic Example

3-436

207865-001

AP·113
HOST INTERRUPT OVERVIEW

The host has only two possible interrupt inputs, a nonmaskable interrupt (NMI) and a maskable interrupt
(INTR). Attaching the 8087 INT pin to the NMI input is
not recommended. The following problems arise: NMI
cannot be masked, it is usually reserved for more important functions like sanity timers or loss of power signal,
and Intel supplied software for the NDP will not support NMI interrupts. The INTR input pf the host allows
interrupt masking in the CPU, using an Intel 8259A
Programmable Interrupt Controller (PIC) to resolve
mUltiple interrupts, and has Intel support.
NUMERIC INTERRUPT CHARACTERISTICS

Numeric error interrupts are different from regular instruction error interrupts like divide by. zero. Numeric
interrupts from the 8087 can occur long after the
ESCAPE instruction that started the failing operation.
For example, after starting a numeric mUltiply operation, the host may respond to an external interrupt and
be in the process of servicing it when the 8087 detects an
overflow error. In this case the interrupt is a result of
some earlier, unrelated program.
From the point of view of the currently executing interrupt handler, numeric interrupts can come from only
two sources: the current handler or a lower priority program.

To explicitly disable numeric interrupts, it is recommended that numeric interrupts be disabled at the 8087.
The code example of Figure 13 shows how to disable
any pending numeric interrupts then reenable them at
the end of the handler. This code example can be safely
placed in any routine which must prevent numeric interrupts from occurring. Note that the ESCAPE instructions act as NOPs if an 8087 is not present in the system.
It is not recommended to use numeric mnemonics since
they may be converted to emulator calls, which run
comparatively slow, if the 8087 emulator used.
Interrupt systems have specific functions like fast
response to external events or periodic execution of
system routines. Adding an 8087 interrupt should not
effect these functions. Desirable goals of any 8087 interrupt configuration are:
- Hide numeric interrupts from interrupt handlers that
don't use the 8087. Since they didn't cause the
numeric interrupt why should they be interrupted?
- Avoid adding code to interrupt handlers that don't
use the 8087 to prevent interruption by the 8087.
- Allow other higher priority interrupts to be serviced
while executing a numeric exception handler.
- Provide numeric exception handling for interrupt
service routines which use the 8087.
- Avoid deadlock as described in a later section
(page 24)

Disable any possible numeric interrupt from the 8087. This code is safe to place in any
procedure. If an 8087 is not present, the ESCAPE instructions will act as· nops. These
instructions are not affected by the TEST pin of the host. Using the 8087 emulator will not
convert these instructions into interrupts. A word variable, called control, is required to hold
the 8087 control word. Control must not be changed until it is reloaded into the 8087.

,
ESC 15, control
NOP
NOP
ESC 28,cx

(FNSTCW) Save current 8087 control word
Delay while 8087 saves current control
register value
(FNDISI) Disable any 8087 interrupts
Set IEM bit in 8087 control register
The contents of cx is irrelevant
Interrupts can now be enabled
(Your Code Here)

Reenable any pending interrupts in the 8087. This instruction does not disturb any 8087 instruction
currently in progress since all it does is change the IEM bit in the control register.
TEST control,80H
JNZ $+4
ESC 28,ax

Look at IEM bit
If IEM = 1 skip FNENI
(FNENI) reenable 8087 interrupts
Figure 13. Inhibit/Enable 8087 Interrupts
3-437

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AP·113
Recommended Interrupt Configurations

5. Case 4 holds except that interrupt handlers may
also generate numeric interrupts. Connect the 8087
INT signal to multiple interrupt inputs. One input
would still be the lowest priority input as in case 4.
Interrupt handlers that may generate a numeric interrupt will require another 8087 INT connection
to the next highest priority interrupt. Normally the
higher priority numeric interrupt inputs would be
masked and the low priority numeric interrupt
enabled. The higher priority interrupt input would
be unmasked only when servicing an interrupt
which requires 8087 exception handling.

Five categories cover most uses of the 8087 interrupt in
fixed priority interrupt systems. For each category, an
interrupt configuration is suggested based on the goals
mentioned above.
1. All errors on the 8087 are always masked.
Numeric interrupts are not possible. Leave the
8087 INT signal unconnected.

2. The 8087 is the only interrupt in the system. Connect tlie 8087 INT signal directly to the host's
INTR input. (See Figure 14 on page i9). A bus
driver supplies interrupt vector 10 16 for compatibility with Intel supplied software.

All of these configurations hide the 8087 from all interrupt handlers which do not use the 8087. Only those interrupt handlers that use the 8087 are required to perform any special 8087 related interrupt control activities.

3. The 8087 interrupt is a stop everything event.
Choose a high priority interrupt input that will terminate all numerics related activity. This is a
special case since the interrupt handler may never
return to the point of interruption (i.e. reset the
system and restart rather than attempt to continue
operation).

A conflict can arise between the desired PIC interrupt
input and the required interrupt vector of 1016 for compatibility with Intel software for numeric interrupts. A
simple solution is to use more than one interrupt vector
for numeric interrupts, all pointing at the same 8087 interrupt handler. Design the numeric interrupt handler
such that it need not know what the interrupt vector was
(i.e. don't use ,specific EOI commands).

4. Numeric exceptions or numeric programming errors are expected and all interrupt handlers either
don't use the 8087 or only use it with all errors
masked. Use the lowest priority interrupt input,
The 8087 interrupt handler should allow further
interrupts by higher priority events. The PIC's
priority system will automatically prevent the 8087
from disturbing other interrupts without adding
extra code to them.

If an interrupt system uses rotating interrupt priorities,
it will not matter which interrupt input is used.

3-438

207865-001

Ap·113

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3-439

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AP·113
GETTING STARTED IN SOFTWARE

Concurrency Overview

Now we are ready to run numeric programs. Developing
numeric software will be a new experience to some pro·
grammers. This section of the application note is aimed
at describing the programming environment and providing programming guidelines for the NPX. The term
NPX is used to emphasize that no distinction is made
between the 8087 component or an emulated 8087.

With the NPX initialized, the next step in writing a
numeric program is learning about concurrent execution
within the NDP.

Two major areas of numeric software can be identified:
systems software and applications software. Products
such as iRMXThI 86 provide system software as an offthe-shelf product. Some applications use specially
developed systems software optimized to their needs.
Whether the system software is specially tailored or
common, they share issues such as using concurrency,
maintaining synchronization between the host and 8087,
and establishing programming conventions. Applications software directly performs the functions of the
application. All applications will be concerned with initialization and general programming rules for the NPX.
Systems software will be more concerned with context
switching, use of the NPX by interrupt handlers, and
numeric exception handlers.

How to Initialize the NPX
The first action required by the NPX is initialization.
This places the NPX in a known state, unaffected by
other activity performed earlier. This initialization is
similar to that caused by the RESET signal of the 8087.
All the error masks are set, all registers are tagged
empty, the TOP field is set to 0, default rounding, precision, and infinity controls are set. The 8087 emulator
requires more initialization than the component. Before
the emulator may be used, all its interrupt vectors must
be set to point to the correct entry points within the
emulator.
To provide compatibility between the emulator and
component in this special case, a call to an external procedure should be used before the first numeric instruction. In ASM86 the programmer must call the external
function INIT87. (Fig. 15). For PLM86, the
programmer must call the built-in function
INIT$REAUMATHSUNIT. PLM86 will' call INIT87
when executing the INIT$REAUMATHSUNIT builtin function.

Concurrency is a special feature of the 8087, allowing it
and the host to simultaneously execute different instructions. The 8087 emulator does not provide concurrency
since it is implemented by the host.
The benefit of cpncurrency to an application is higher
performance. All Intel high level languages automatically provide for a~d manage concurrency in the NDP.
However, in exchange for the added performance, the
assembly language programmer must understand and
manage some areas of concurrency. This section is for
the assembly language programmer or well-informed,
high level language programmer.
Whether the 8087 emulator or component is used, care
should be taken by the assembly language programmer
to follow the rules described below regarding synchronization. Otherwise, the program may not function correctly with current or future alternatives for implementing the NDP.
Concurrency is possible in the NDP because both the
host and 8087 have separate arithmetic and control
units. The host and coprocessor automatically decide
who will perform any single instruction. The existence
of the 8087 as a separate unit is not normally apparent.
Numeric instructions, which will be executed by the
8087, are simply placed in line with the instructions for
the host. Numeric instructions are executed in the same
order as they are encountered by the host in its instruction stream. Since operations performed by the 3087
generally require more time than operatiuns performed
by the host, the host can execute several of its instructions while the 8087 performs one numedc operation.

r-----------------------------__-----.----,

I

IN PLM86:
CALL INIT$REAL$MATH$UNIT;
IN ASM86:
EXTRN

•
•
•
•

The function supplied for INIT87 will be different,
depending on whether the emulator library, called
EB087.LlB, or component library, called 8087.LIB,
were used at link time. INIT87 will execute either an
FNINIT instruction for the 8087 or initialize the 8087
emulator interrupt vectors, as appropriate.

CALL

INIT87:FAR

INIT87

Figure .15. 8087 Initialization

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MANAGING CONCURRENCY

Instruction Synchronization

Concurrent execution of the host and 8087 is easy to
establish and maintain. The activities of numeric programs can be split into two major areas: program control and arithmetic. The program control part performs
activities like deciding what functions to perform, calculating addresses of numeric operands, and loop control.
The arithmetic part simply performs the adds, subtracts, multiplies, and other operations on the numeric
operands. The NPX and host are designed to handle
these two parts separately and efficiently.

Instruction synchronization is required because the 8087
can only perform one numeric operation at a time. Before any numeric operation is started, the 8087 must
have completed all activity from previous instructions.
The WAIT instruction on the host lets it wait for the
8087 to finish all numeric activity before starting another numeric instruction. The assembler automatically
provides for instruction synchronization since aWAIT
instruction is part of most numeric instructions. A
WAIT instruction requires 1 byte code space and 2.5
clocks average execution time overhead.

Managing concurrency is necessary because the arithmetic and control areas must converge to a well-defined
state when starting another numeric operation. A welldefined state means all previous arithmetic and control
operations are complete and valid.

Instruction synchronization as provided by the assembler or a compiler allows concurrent operation in the
NDP. An execution time comparison of NDP concurrency and non-concurrency is illustrated in Figure 16.
The non-concurrent program places aWAIT instruction
immediately after a multiply instruction ESCAPE instruction. The 8087 must complete the mUltiply operation before the host executes the MOV instruction on
statement 2. In contrast, the concurrent example allows
the host to calculate the effective address of the next
operand while the 8087 performs the mUltiply. The execution time of the concurrent technique is the longest
of the host's execution time from line 2 to 5 and the execution time of the 8087 for a mUltiply instruction. The
execution time of the non-concurrent example is the
sum of the execution times of statements 1 to 5.

Normally, the host waits for the 8087 to finish the current numeric operation before starting another. This
waiting is called synchronization.
Managing concurrent execution of the 8087 involves
three types of synchronization: instruction, data, and
error. Instruction and error synchronization are
automatically provided by the compiler or assembler.
Data synchronization must be provided by the assembly
language progarnmer or compiler.

This code macro defines two instructions which do not allow any concurrency of execution with
the host. A register version and memory version of the instruction is shown. It is assumed that the
8087 is always idle from the previous instruction. Allow space for emulator fixups.
R233 Record RF6:2, Mid3:3, RF7:3
CodeMacro NCMUl dst:T, src:F
RNfix OOOB
R233 (11 B, 001 B, src)
RWfix
EndM
CodeMacro NCMUl memop:Mq
RNfixM 100B, memop
ModRM 001 B, memop
RWfix
EndM
Statement
1

2
3
4

5

Concurrent
FMUl
MOV
MUl
MOV
FMUl

st(O), st(1)
ax, size A
index
bx, ax
A [bx]

Non Concurrent
NCMUl
MOV
MUl
MOV
NCMUl

st(O), st(1)
ax, size A
index
bx, ax
A [bx]

Figure 16. Concurrent Versus Non·Concurrent Program

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Data Synchronization
Managing concurrency requires synchronizing data references by the host and 8087.
Figure 17 shows four possible cases of the host and 8087
sharing a memory value. The second two cases require
the FWAIT instruction shown for data synchronization.
In the first two cases, the -host will finish with the
operand I before the 8087 can reference it. The
coprocessor interface guarantees this. In the second two
cases, the host must wait for the 8087 to finish with the
memory operand before proceeding to reuse it. The
FWAIT instruction in case 3 forces the host to wait for
the 8087 to read I before changing it. In case 4, the
FW AIT prevents the host from reading I before the
8087 sets its value.

The data synchronization purpose of any FWAITor
numeric instruction must be well documented. Otherwise, a change to' the program at a later time may
remove the synchronizing numeric instruction, causing
program failure, as:
FISTP
FMUL
MOV

AX, I

Case 1:

Obviously, the programmer must recognize any form of
the two cases shown above which require explicit data
synchronization. Data synchronization is not a concern
when the host and 8087 are using different memory
operands during th~ course of one numeric instruction.
Figure 16 shows such an example of the host performing
, activity umelated to the current numeric instruction
being executed by the 8087. Correct recognition of these
cases by the programmer is the price to be paid for providing concurrency at the assembly language level.

MOV
FILD

1,1
I

Case 2:

; I is safe to use

Case 3:

FILD
FWAIT
MOV

1,5

Case 4:

MOV AX, I
FISTP I

FISTP
FWAIT
MOV

AX,I

Figure 17. Data Exchange Example

Automatic Data Synchronization
Two methods exist to avoid the need for manual recognition of when data synchronization is needed: use a
high level language which will automatically establish
concurrency and manage it, or sacrifice some performance for automatic data synchronization by the assembler.

This is a code macro to redefine the FIST
instruction to prevent any concurrency
while the instruction runs. A wait
instruction is placed immediately after the
escape to ensure the store is done
before the program may continue. This
code macro will work with the 8087
emulator, automatically replacing thewait escape with a nop.

When a high level language is not adequate, the
assembler can' be changed to always place aWAIT instruction after the ESCAPE instruction. Figure 18
shows an example of how to change the ASM86 code
macro for the FIST instruction to automatically place
an FWAIT instruction after the ESCAPE instruction.
The lack of any possible concurrent execution between
the host and 8087 while the FIST instruction is executing
is the price paid for automatic data synchronization.

,
CodeMacro FIST memop: Mw
RfixM 111 B, memop
ModRM 010B, memop
RWfix
EndM

An explicit FWAIT instruction for data synchronization, can be eliminated by using a subsequent numeric
instruction. After this subsequent instruction has
started execution, all memory references in earlier
.numeric instructions are complete. Reaching the next
'host instruction after the synchronizing numeric instruction indicates previous numeric operands in memory are
available.

Figure 18. Non·Concurrent FIST Instruction
Code Macro

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DATA SYNCHRONIZATION RULES EXCEPTIONS

ERROR SYNCHRONIZATION FOR EXTENSIONS

There are five exceptions to the above rules for data synchro~tion. The 8087 automatically provides data synchronization for these cases. They are necessary to
avoid deadlock (described on page 24). The instructions
FSTSW IFNSTSW, FSTCW IFNSTCW, FLDCW,
FRSTOR, and FLDENV do not require any waiting by
the host before it may read or modify the referenced
memory location.

The NPX can provide a default fixup for all numeric
errors. A program can mask each individual error type
to indicate that the NPX should generate a safe, reasonable result. The default error fixup activity is simply
treated as part of the instruction which caused the error.
No external indication of the error will be given. A flag
in the numeric status register will be set to-indicate that
an error was detected, but no information regarding
where or when will be available.

The 8087 provides the data synchronization by preventing the host from gaining control of the local bus while
these instructions execute. If the host cannot gain control of the local bus, it cannot change a value before the
8087 reads it, or read a value before the 8087 writes into
it.
The coprocessor interface guarantees that, when the
host executes one of these instructions, the 8087 will
immediately request the local bus from the host. This
request is timed such that, when the host finishes the
read operation identifying the memory operand, it will
always grant the local bus to the 8087 before the host
may use the local bus for a data reference while executing a subsequent instruction. The 8087 will not release
the local bus to the host until it has finished executing
the numeric instruction.

Error Synchronization
Numeric errors can occur on almost .any numeric instruction at any time during its execution. Page IS
describes how a numeric error may have many interpretations, depending on the application. Since the response to a numeric error will depend on the application, this section covers topics common to all uses of the
NPX. We will review why error synchronization is needed and how it is provi~ed.
Concurrent execution of the host and 8087 requires synchronization for errors just like data references and
numeric instructions. In fact, the synchronization required for data and instructions automatically provides
error synchronization.
However, incorrect data or instruction synchronization
may not cause a problem until a numeric error occurs. A
further complication is that a programmer may not expect his numeric program to cause numeric errors, but
in some systems they may regularly happen. To better
understand these points, let's look at what can happen
when the NPX detects an error.

If the NPX performs its default action for all errors,
then error synchronization is never exercised. But this is
no reason to ignore error synchronization.
Another alternative exists to the NPX default fixup of
an error. If the default NPX response to numeric errors
is not desired, the host can implement any form of recovery desired for any numeric error detectable by the
NPX. When a numeric error is unmasked, and the error
occurs, the NPX will stop further execution of the
numeric instruction. The 8087 will signal this event on
the INT pin, while the 8087 emulator will cause interrupt 1016 to occur. The 8087 INT signal is normally connected to the host's interrupt system. Refer to page 18
for further discussion on wiring the 8087 INT pin.
Interrupting the host is a request from the NPX for
help. The fact that the error was unmasked indicates -that further numeric program execution under the arithmetic and programming rules of the NPX is unreasonable. Error synchronization serves to insure the NDP is
in a well defined state after an unmasked numeric error
occured. Without It well defined state, it is impossible to
figure out why the error occured.
Allowing a correct analysis of the error is the heart of
error synchronization.
NDP ERROR STATES'
If concurrent execution is allowed, the state of the host

when it recognizes the 'interrupt is undefined. The host
may have changed many of its internal registers and be
executing a totelly different program by the time it is interrupted. To handle this situation, the NPX has special
registers updated at the start of each numeric instruction
to describe the state of the numeric program when the
failed instruction was attempted. (See Lit. Ref. p. iii)
Besides programmer comfort, a well-defined state is important for error recovery routines. They can change the
arithmetic and programming rules of the 8087. These
changes may redefine the default rDmp from an error,
change the appearance of the NPX to the progralnmer,
or change how arithmetic is defined on the NPX.

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EXTENSION EXAMPLES
A change to an error response might be to automatically
normalize all denormals loaded from memory. A
change in appearance might be extending the register
stack to memory to provide an "infinite" numoer of
numeric registers. The arithmetic of the 8087 can be
changed to automatically extend the precision and range
of variables when exceeded. All these functions can be
implemented on the NPX via numeric errors and
associated recovery routines in a manner transparent to
the programmer.
Without correct error synchronization, numeric
subroutines will not work correctly in the above situations.
Incorrect Error Synchronization
An example of how some instructions written without
error synchronization will work initially, but fail when
moved into a new environment is:
FILD

INC

COUNT
COUNT

The BUSY signal will never go inactive during a numeric
instruction which asse~ts INT.
The WAIT instructions supplied for instruction synchroni~tion prevent the host from starting another
numeric instruction until the current error is serviced. In
a like manner, the WAIT instructions required for data
synchronization prevent the host from prematurely
readinl! a value not yet stored, by the 8087, or overwriting a value not yet read by the 8087.
The host has two, responsibilities when handling
numeric errors. I.) It must not disturb the numeric context when an error is detected, and 2.) it must clear the
numeric error and attempt recovery from t~e error. The
recovery program invoked by the numeric error may
resume program execution after proper fixup, display
the state of the NDP for programmer action, or simply
abort the program. In any case, the host must do
something with the 8087. With the INT and BUSY
signals active, the 8087 cannot perform any useful
work. Special instructions exist for controlling the 8087
when in this state. Later, an example is given of how to
save the state of the NPX with an error pending. (See
page 29) ,

FSQRT

Three instructions are shown to load an integer, calculate its square root, then increll.lent the integer. The
coprocessor interface of the 8087 and synchronous execution of the 8087 emulator will allow this program to
execute correctly when no errors occur on the FILD instruction.

An undesirable situation may r~sult if the host cannot
be interrupted by the 8087 when asserting INT. This situation, called deadlock, occurs if the interrupt path
, from the 8087 to the host is broken.

But, this situation changes if the numeric register stack
is extended to memory on an 8087. To extend the NPX
stack to memory, the invalid error is unmasked. A push
to a full 'register or pop from an empty register will
cause an invalid error. The recovery routine for the error must recognize this situation, fllmp the stack, then
perform the original operation.

The 8087 BUSY signal prevents the host from executing
further instructions (for instruction or data synchronization) while the 8087 waits for the host to service
the exception. The host is waiting for the 8087 to finish
the current numeric operation. Both the host and 8087
are waiting on each other. This situation is stable unless
the host is interrupted by some other event.

The recovery routine will not work correctly in the example. The problem is that there is no guarantee that
COUNT will not be incremented before the 8087 can interrupt the host. If COUNT is incremented before the
interrupt, the recovery routine will load a value of
COUNT one too large, probably causing the program to

DeadlOCK has varying affects on the NDP's performance. If no other interrupts in the'system are possible,
the NDP will wait forever. If other interrupts can arise,
then the NDP can perform other functions, but the affected numeric program will remain "frozen".

fu~

.

Error Synchronization and WAITs
Error synchronization relies on the WAIT instructions
required by instruction and data synchronization and
the INT and BUSY signals of the 8087. When an unmasked error occurs in the 8087, it asserts the BUSY
and INT signals. The INT signal is to interrupt the host,
while the BUSY signal prevents the host from destroying the current numeric context.

Deadlock

SOLVING DEADLOCK
Finding the break in the interrupt path is simple. Look
for disabled interrupts in the following places: masked
interrupt enable in the host, explicitly masked interrupt
request in the interrupt controller, implicitly masked interrupt request in the interrupt controller due to a higher
priority interrupt in service, or other gate functions,
usually in TTL, on the host interrupt signal.

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DEADLOCK AVOIDANCE

Application programmers should not be concerned with
deadlock. Normally, applications programs run with
unmasked· numeric errors able to interrupt them. Deadlock is not possible in this case. Traditionally, systems
software or interrupt handlers may run with numeric interrupts disabled. Deadlock prevention lies in this domain. The golden rule to abide by is: "Never wait on the
8087 if an unmasked error is possible and the 8087 interrupt path may be broken."

Error Synchronization Summary
In summary, error synchronization involves protecting
the state of the 8087 after an exception. Although not all
applications may initially require error synchronization,
it is just good programming practice to follow the rules.
The advantage of being a "good" numerics programmer is generality of your program so it can work in
other, more general environments.

Summary
Synchronization is the price for concurrency in the
NDP. Intel high level language compilers will automatically provide concurrency and manage it with synchronization. The assembly language programmer can
choose between using concurrency or not. Placing a
WAIT instruction immediately after any numeric instruction will prevent concurrency and avoid synchronization concerns.
The rules given above are complete and allow concurrency to be used to full advantage.

Synchronization and the Emulator
The above discussion on synchronization takes on
special meaning with the 8087 emulator. The 8087 emulator does not allow any concurrency. All numeric
operand memory references, error tests, and wait for
instruction completion occur within the emulator. As a
result, programs which do not provide proper instruction, data, or error synchronization may work with the
8087 emulator while failing on the component.
Correct programs for the 8087 work correctly on the
emulator.

Special Control Instructions of the NPX
The special control instructions of the NPX: FNINIT,
FNSAVE,FNSTENV,FRSTOR,FLDENV,FLDCW,
FNSTSW, FNSTCW, FNCLEX, FNENI, and FNDISI
remove some of the synchronization requirements mentioned earlier. They are discussed here since they represent exceptions to the rules mentioned on page 21.
The instructions FNINIT, FNSAVE, FNSTENV,
FNSTSW, FNCLEX, FNENI, and FNDISI do not wait

for the current numeric instruction to finish before they
execute. Of these instructions, FNINIT, FNSTSW,
FNCLEX, FNENI and FNDISI will produce different
results, depending on when they are executed relative to
the current numeric instruction.
For example, FNCLEX will cause a different status
value to result from a concurrent arithmetic operation,
depending on whether is is executed before or after the
error status bits are updated at the end of the arithmetic
operation. The intended use of FNCLEX is to clear a
known error status bit which has caused BUSY to be
asserted, avoiding deadlock.
FNSTSW will safely, without deadlock, report the busy
and error status of the NPX independent of the NDP interrupt status.
FNINIT, FNENI, and FNDISI are used to place the
NPX into a known state independent of its current
state. FNDISI will prevent an unmasked error from
asserting BUSY without disturbing the current error
status bits. Appendix A shows an example of using
FNDISI.
The instructions FNSAVE and FNSTENV provide special functions. They allow saving the state,of the NPX in
a single instruction when host interrupts are disabled.
Several host and numeric instructions are necessary to
save the NPX status if the interrupt status of the host is
unknown. Appendix A and B show examples of saving
the NPX state. As the Numerics Supplement explains,
host interrupts must always be disabled when executing
FNSAVE or FNSTENV.
The seven instructions FSTSWIFNSTSW, FSTCW I
FNSTCW, FLDCW, FLDENV, and FRSTOR do not
require explicit WAIT instructions for data synchronization. All of these instructions are used to interrogate
or control the numeric context.
Data synchronization for these instructions is
automatically provided by the coprocessor interface.
The 8087 will take exclusive control of the memory bus,
preventing the host from interfering with the data values
before the 8087 can read them. Eliminating the need for
aWAIT instruction avoids potential deadlock pro. blems.
The three load instructions FLDCW, FLDENV, and
FRSTOR can unmask a numeric error, activating the
8087 BUSY signal. Such an error was the result of a
previous numeric instruction and is not related to any
fault in the instruction.
Data synchronization is automatically provided since
the host's interrupts are usually disabled in context switching or interrupt handling, deadlock might result if the
host executed aWAIT instruction with its interrupts
disabled after these instructions. After the host interrupts are enabled, an interrupt will occur if an unmasked error was pending.
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PROGRAMMING TECHNIQUES

NPX Register Usage

The NPX provides a stack-oriented register set with
stack-oriented instructions for numeric operands. These
registers and instructions are optimized for numeric
programs. For many programmers, these are new resources with new programming options available.

The eight numeric registers in the NDP are stack oriented. All numeric registers are addressed relative to a
value called the TOP pointer, defined in the NDP status
register. A register address given in an instruction is added to the TOP value to form the internal absolute address. Relative addressing of numeric registers has advantages analogous to those of relative addressing of
memory operands.

Using Numeric Registers and
Instructions
The register and instruction set of the NDP is optimized
for the needs of numeric and general purpose programs.
The host CPU provides the instructions and data types
needed for general purpose data processing, while the
8087 provides the data types and instructions for
numeric processing.
The instructions and data types recognized by the 8087
are different from the CPU because numeric program
requirements are different from those of general purpose programs. Numeric programs have long arithmetic
expressions where a few temporary values are used in a
few statements. Within these statements, a single value
may be referenced many times. Due to the time involved
to transfer values between registers and memory, a
significant' speed optimization is possible by keeping
numbers in the NPX register rlie.
In contrast, a general data processor is more concerned
with addressing data in simple expressions and testing
the results. Temporary values, constant across several
instructions, are not as common nor is the penalty as
large for placing them in memory.As a result it is
simpler for compilers and programmers to manage
memory based values.

Two modes are availa~le for addressing the numeric
registers. The first mode implicitly uses the top and optional next element on the stack for operands. This
mode does not require any addressing bits in a numeric
instruction. Special purpose instructions use this mode
since full addressing flexibiiity is not required.
The other addressing mode allows any' other stack element to be used together with the top of stack register.
The top of stack or the other register may be specified as
the destination. Most two-operand arithmetic instructions allow this addressing mode. Short, easy to develop
numeric programs are the result.
Just as relative addressing of memory operands avoids
concerns with memory allocation in other parts of a
program, top relative register addressing allows registers
to be used without regard for numeric register assignments in other parts of the program.

STACK RELATIVE ADDRESSING' EXAMPLE
Consider an example of a main program calling a
subroutine,~ each using register addressing independent
of the other. (Fig. 19) By using different values of the
TOP field, different software can use the same relative
register addresses as other parts of the program, but
refer to different physical registers.

MAIN_PROGRAM:

FLO
FAOO
CALL
FSTP

A
ST, ST(1)
SUBROUTINE
B

Argument is in ST(O)

SUBROUTINE:

FLO
FSQRT
FAOO
FMULP
RET

ST(O) = ST(1) = Argument
Main program ST(1) is
safe in ST(2) here

ST
C
ST(1), ST

Figure 19. Stack Relative Addressing Example

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Of course, there is a limit to any physical resource. The
NDP has eight numeric registers. Normally, program·
mers must ensure a maximum of eight values are pushed
on the numeric register stack at any time. For timecritical inner loops of real-time applications, eight registers should contain all the values needed.

3) Return all numeric values on the numeric stack. The
caller may now take advantage of the extended precision and flexible store modes of the NDP.
4) Finish all memory reads or writes by the NPX before
exiting any subroutine. This guarantees correct data
and error synchronization. A numeric operation
based solely on register contents is safe to leave running on subroutine exit.

REGISTER STACK EXTENSION
This hardware limitation can be hidden by software.
Software can provide "virtual" numeric registers, expanding the register stack size to 6000 or more.

5) The operating mode of the NDP should be transparent across any subroutine. The operating mode is
defined by the control word of the NDP. If the subroutine needs to use a different numeric operating
mode than that of the caller, the subroutine should
first save the current control word, set the new operating mode, then restore the original control word
when completed.

The numeric register stack can be extended into memory
via unmasked numeric invalid errors which cause an interrupt on stack overflow or underflow. The interrupt
handler for the invalid error would manage a memory
image of the numeric stack copying values into and out
of memory as needed.
The NPX will contain all the necessary information to
identify the error, failing instruction, required registers,
and destination register. After correcting for the missing
hardware resource, the original numeric operation
could be repeated. Either the original numeriC>instruction could be single stepped or the affect of the instruction emulated by a composite of table-based numeric instructions executed by the error handler.

PROGRAMMING EXAMPLES
The last section of this application note will discuss five
programming examples. These examples were picked to
illustrate NDP programming techniques and commonly
used functions. All have been coded, assembled, and
tested. However, no guarantees are made regarding
their correctness.

With proper data, error, and instruction synchronization, the activity of the error handler will be transparent
to programs. This type of extension to the NDP allows
programs to push and pop numeric registers without
regard for their usage by other subroutiIles.

The programming examples are: saving numeric
context switching, save numeric context without
FSAVE/FNSAVE, converting ASCII to floating point,
converting floating point to ASCII, and trigonometric
functions. Each example is listed in a different appendix
with a detailed written description in the following text.
The source code is available in machine readable form
from the Intel Insite User's Library, "Interactive 8087
Instruction Interpreter," catalog item AA20.

Programming Conventions
With a better understanding of the stack registers, let's
consider some useful programming conventions. Following these conventions ensures compatibility with
Intel support software and high level language calling
conventions.
1) If the numeric registers are not extended to'
memory, the programmer must ensure that the
number of temporary values left in the NPX stack
and those registers used by the caller does not exceed
8. Values can be stored to memory to provide enough
free NPX registers.
2) Pass the first seven numeric parameters to a subroutine in the numeric stack registers. Any extra parameters can be passed on the host's stack. Push the
values on the register or memory stack in left to right
order. If the subroutine does not need to allocate any
more numeric registers, it can execute solely out of
the numeric register stack. The eighth register can be
used for arithmetic operations. All parameters
should be 'popped off when the subroutine completes.

The examples provide some basic functions needed to
get started with the numeric data processor. They work
with either the 8087 or the 8087 emulator with no source
changes.
The context switching examples are needed for
operating systems or interrupt handlers which may use
numeric instructions and operands. Converting between
floating point and decimal ASCII will be needed to input or output numbers in easy to read form. The trigonometric examples help you get started with sine or
cosine functions and can serve as a basis for optimizations if the angle arguments always fall into a restricted
range.

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APPENDIX A
OVERVIEW,--

Using FSAVE

Appendix A shows deadlock-free examples of numeric
context switching. Numeric context switching is required by interrupt handlers which use the NPX and
operating system context switchers. Context switching
consists of two basic functions, save the numeric context and restore it. These. functions must work independent of the current state of the NPX.

The FSAVE instruction performs the same operation as
FNSAVE but it uses standard instruction synchronization. The host will wait for the FEU to be idle before
initiating the save operation. Since the host ignores all
interrupts between completing a WAIT instruction and
starting the. following ESCAPE instruftion, the FEU is
ready to immediately accept the operation (since it is not
signalling BUSY). No recursion of the save context
operation in the BIU is possible. However, deadlock
must be considered since the host executes a WAIT instruction.

Two versions of the context save function are shown.
They use different versions of the save context instruction. The FNSAVEfFSAVE instructions do all the work
of saving the numeric context. The state of host interrupts will decide which instruction to use.

USing FNSAVE
The FNSAVE instruction is intended to save the NPX
context when host interrupts are disabled. The host does
not have to wait for the 8087 to finish its current operation before starting this operation. Eliminating the instruction synchronization wait avoids any potential
deadlock.
The 8087 Bus Interface Unit (BIU) will save this instruction when encountered by the host and hold it until the
8087 Floating point Execution Unit (FEU) finishes its
current operation. When the FEU becomes idle, the
BIU will start the FEU executing the save context opera~
tion.
The host can execute other non.:numeric instructions
after the FNSAVE while the BIU waits for the FEU to
finish its current operation. The code starting at
NOjNL..NPX~AVE shows how to use the
FNSAVE instruction.
When executing the FNSAVE instruction,. host interrupts must be disabled to avoid recursions of the instruction. The 8087 BIU can hold only one FNSAVE instruction at a time. If host interrupts were not disabled,
another host interrupt might cause a second FNSAVE
instruction to be executed, destroying the previous one
saved in the 8087 BIU.
It is not recommended to explicitly disable host inter-

rupts just to exFCute an FNSAVE instruction. In
general, such an operation may not be the best course of
action or even be allowed.
If host interrupts are enabled during the NPX context
save function, it is recommended to use the FSAVE instruction as shown by the code starting at NP~AVE.
This example will always work, free of deadlock, in"
dependent of the NDP interrupt state.

To avoid deadlock when using the FSAVE instruction,
the 8087 must be prevented from signalling BUSY when
an unmasked error exists.
The Interrupt Enable Mask (IBM) bit in the NPX control word provides this function. When IEM = I, the
8087 will not signal BUSY or INT if an unmasked error
exists. The NPX instruction FNDISI will set the IEM independent of any pending errors without causing
deadlock or any other errors. Using the FNDISI and
FSAVE instructions together with a few other glue instructions allows a general NPX context save function.
Standard data and instruction synchronization is required after executing the FNSAVEIFSAVE instruction. The wait instruction following an FNSAVEl
FSAVE instruction is always safe since all NPX errors
will be masked as part of the instruction execution.
Deadlock is not possible since the 8087 will eventually
signal not busy, allowing the host to continue on.

PLACING THE SAVE CONTEXT FUNCTIQN
Deciding on where to ;save the NPX context in an interrupt handler or context switcher is dependent on
whether interrupts can be enabled inside the function.
Since interrupt latency is measured in terms of the maximum time interrupts are disabled, the maximum wait
time of the host at the data synchronizing wait instruction after the FNSAVE or the FSAVE instruction is important if host interrupts are disabled while waiting.
The wait time will be the maximum single instruction
execution time of the 8087 plus the execution time of the
save operation. This maximum time will be approximately 1300 or 1500 clocks, depending on whether the
host is an 8086 or 8088, respectively. The actual time
will depend on how much concurrency of execution between the host and 8087 is provided. The greater the
concurrency, the lesser the maximum wait time will be.

207865-001

I

AP·113
If host interrupts can be enabled during the context save

Using FRSTOR

function, it is recommended to use the FSA VE instruc·
tion for saving the numeric context in the interruptable
section. The FSAVE instruction allows instruction and
data synchronizing waits to be interruptable. This
technique removes the maximum execution time of 8087
instructions from system interrupt latency time considerations.

Restoring the numeric context with FRSTOR does not
require a data synchronizing wait afterwards since the
8087 automatically prevents the host from interfering
with the memory load operation.

It is recommended to delay starting the numeric save
function as long as possible to maintain the maximum
amount of concurrent execution between the host and
the 8087.

The code starting with NPXJESTORE illustrates the
restore operation. Error synchronization is not
necessary since the FRSTOR instruction itself does not
cause errors, but the previous state of the NPX may indicate an error.
If further numeric instructions are executed after the
FRSTOR, and the error state of the new NPX context is
unknown, deadlock may occur if numeric exceptions
cannot interrupt the host.

NP>Lsave

General purpose save of NPX context. This function will work independent of the interrupt state of
the NDP. Deadlock can not occur. 47 words of memory are required by the variable save_area.
Register ax is not transparent across this code.
NP>L..save:
FNSTCW
NOP
FNDISI
MOV
FSAVE

ax, save_area
save_area

FWAIT
MOV

Save IEM bit status
Delay while 8087 saves control register
Disable 8087 BUSY signal
Get original control word
Save NPX context, the host can be safely interrupted while
waiting for the 8087 to finish. Deadlock is not possible since
IEM = 1.Wait for save to finish. Put original control word into
NPX context-area_ All done

Save the NPX context with host interrupts disabled. No deadlock is possible. 47 words of memory
are required by the variable save_area_
nO_inLNP>L..save:
FNSAVE
save_area
FWAIT

Save NPX context. Wait for save to finish, no deadlock
is possible. Interrupts may be enabled now, all done

NP>Lrestore
Restore the NPX context saved earlier. No deadlock is possible if no further numeric instructions
are executed until the 8087 numeric error interrupt is enabled_ The variable save_area is assumed
to hold an NPX context saved earlier. It must be 47 words long.
N P>L..restore:
FRSTOR

Load new NPX context

3-449

207865-001

AP·113
APPENDIX B
OVERVIEW
Appendix B shows alternative techniques for switching
the numeric context without using the FSAVEl
FNSAVE or FRS TOR instructions. These alternative
techniques are slower than those of Appendix A but
they reduce the worst case continuous local bus usage of
the 8087.
Only an iAPX 86122 or iAPX 88122 could derive any
benefit from this alternative. By replacing all
FSAVE/FNSAVE instructions in the system, the worst
case local bus usage of the 8087 will be 10 or 16 consecutive memory cycles for an 8086 or 8088 host, respectively.
Instead of saving and loading the entire numeric context
in one long series of memory transfers, these routines
use the FSTENV IFNSTENV IFLDENV instructions
and separate numeric register load/store instructions.
Using separate load/store instructions for the numeric
registers forces the 8087 to release the local bus after
each numeric load/store instruction. The longest series
of back-to-back memory transfers required by these
instructions are 8/12 memory cycles for an 8086 or 8088
host, respectively. In contrast, the FSA VEl
FNSAVE/FRSTOR instructions perform 50/94 backto-back memory cycles for an 8086 or 8088 -host.

Compatibility With FSAVE/FNSAVE
This function produces a context area of the same format produced by FSAVE/FNSAVE instructions. Other
software modules expecting such a format will not be
affected. All the same interrupt and deadlock considerations of FSAVE and FNSAVE also apply to FSTENV
and FNSTENV. Except for the fact that the numeric
environment is 7 words rather than the 47 words of the
numeric context, all the discussion of Appendix A also
applies here.

The state of the NPX registers must be saved in memory
in the same format as the FSAVB/FNSAVB instructions." The program example starting at the label
SMALL..-.-BLOCK~PX_SAVE illustrates a software
loop that will store their contents into memory in the
same top relative order as that of FSAVE/FNSAVE.
To save the registers with FSTP instructions, they must
be tagged valid, zero, or special. This function will force
all the registers to be tagged valid, independent of their
contents or old tag, and then save them. No problems
will arise if the tag value conflicts with the register's
content for the FSTP instruction. Saving empty registers insures compatibility with the FSAVE/FNSA VB instructions. After saving all the numeric registers, they
will all be tagged empty, the" same as if an
FSAVE/FNSAVE instruction had been executed.

Compatibility With FRSTOR
Restoring the numeric context reverses the procedure
described above, as shown by the code starting at
SMALL_BLOCK_NP"-.RESTORE.AlI eight regissters are reloaded in the reverse order. With each
register load, a tag value will be assigned to each
register. The tags assigned by the register load does not
matter since the tag word will be overwritten when the
environment is reloaded later with FLDENV.
Two assumptions are required for correct operation of
the restore function: all numeric registers must be empty
and the TOP field must be the same as that in the context being restored. These assumptions will be satisfied
if a matched set of pushes and pops were performed between saving the numeric context and reloading it.
If these assumptions cannot be met, then the code exam-

ple starting at NPX_CLEAN shows how to force all the
NPX registers empty and set the TOP field of the status
word.

3.-450

207865-001

Ap·113
smalLblocLN P><-save
Save the NPX context independent of NDP interrupt state. Avoid using the FSAVE instruction to
limit the worst case memory bus usage of the 8087. The NPX context area formed will appear the
same as if an FSAVE instruction had written into it. The variable save_area will hold the NPX
context and must be 47 words long. The registers ax, bx, and cx will not be transparent.
small_block_N PX_save:
FNSTCW save_area
NOP
FNDISI
MOV
ax, save_area
MOV
cx, 8
XOR
bx, bx
FSTENV save_area
FWAIT
XCHG
save_area + 4, bx
FLDENV save_area
MOV
save_area, ax
MOV
save_area + 4, bx
XOR
bx, bx
reg_store_loop:
FSTP
saved_reg [bx]
ADD
bx, type saved_reg
LOOP
reg_store_loop

;
;
;
;
;

Save current IEM bit
Delay while 8087 saves control register
Disable 8087 BUSY signal
Get original control word
Set numeric register count
Tag field value for stamping all registers as valid
Save NPX environment
Walt for the store to complete
Get original tag value and set new tag value
Force all register tags as valid. BUSY is still masked. No data
synchronization needed. Put original control word into NPX
environment. Put original tag word into NPX environment
Set initial register index
Save register
Bump pointer to next register

; All done

;
;
;
;

Force the NPX into a clean state with TOP matching the TOP field stored in the NPX context and all
numeric registers tagged empty. Save_area must be the NPX environment saved earlier.
Temp_env is a 7 word temporary area used to build a prototype NPX environment. Register ax will
not be transparent.

NPX_clean:
FINIT
MOV
AND
FSTENV

ax, save_area + 2
ax, 3800H
temp_env

FWAIT
OR
FLDENV

temp_env + 2, ax
temp_env

Put NPX into known state
Get original status word
Mask out the top field
Format a temporary environment area with all registers
stamped empty and TOP field =O.
; Wait for the store to finish.
Put in the desired TOP value.
Setup new NPX environment.
Now enter smaILblock_NPX_restore.
3-451

207865-001

Ap·113
smalLbloclLNP>Lrestore
Restore the NPX context without using the FRSTOR instruction. Assume the NPX context is in the
same form as that created by an FSAVElFNSAVE instruction, all the registers are empty, and that
the TOP field of the NPX matches the TOP field of the NPX context. The variable save_area must
be an NPX context save area, 47 words 10f'g. The registers bx and cx will not be transparent.
small_blocLNPLrestore:
MOV
cX,8
MOV
bx, type saved_reg*7
reg_load_loop:
FLO
saved_reg [bx]
SUB
bx, type saved_reg
LOOP
reg_load_loQp
FLOENV save_area

Set register count
Starting offset of ST(7)
Get the register
Bump pOinter to next register
Restore NPX context
All done

APPENDIX C
OVERVIEW

Exception Considerations

Appendix C shows how floating point values can be
converted to decimal ASCII character strings. The function can be called from PLM/86, PASCAL/86, FORTRAN/86, or ASM/86 functions.

Care is taken inside the function to avoid generating exceptions. Any possible numeric value will be accepted.
The only exceptions possible would occur if insufficient
space exists on the numeri~ register stack.

Shortness, speed, and accuracy were chosen rather than
providing the maximum number of significant digits
possible. An attempt is made to keep integers in their
own domain to avoid unnecessary conversion errors.

The value passed in the numeric stack is checked for existence, type (NAN or infinity), and status (unnormal,
denormal, zero, sign). The string size is tested for a
minimum and maximum value. If the top of the register
stack is empty, or the string size is too small, the function will return with an error code.

Using the extended precision real number format, this
routine achieves a worst case accuracy of three units in
the 16th decimal position for a non-integer value or integers greater than lOIS. This is double precision accuracy. With values having decimal exponents less than
100 in magnitude, the accuracy is one unit in the 17th
decimal position.
Higher precision can be achieved with greater care in
programming, larger program size, and lower performance.

Function Partitioning
Three separate modules implement the conversion.
Most of the work of the conversion is done in the module FLOATING_TO.-ASCII. The other modules are
provided separately since they have a more' general use.
One of them, GET-.POWER_tO, is also used by the
ASCII to floating point conversion routine. The other
small module, TOS_STATUS, will identify what, if
anything, is in the top of the numeric register stack.

Overflow and underflow is avoided inside the function
for very large or very small numbers.

Special Instructions
The functions demonstrate the operatIon of several
numeric instructions, different data types, and precision
control. Shown are instructions for automatic conversion to BCD, calculating the value of 10 raised to an integer value, establishing and maintaining concurrency,
data synchronization, and use of directed rounding on
the NPX.
Without the extended precision data type and built-in
exponential function, the double precision accuracy Ofl
this function could not be attained with the size and
speed of the shown example.
The function relies on the numeric BCD data type for
conversion from binary floating point to decimal. It is

3-452

207865-001

Ap·113
not difficult to unpack the BCD digits into separate
ASCII decimal digits. The major work involves scaling
the floating point value to the comparatively limited
range of BCD values. To print a 9·digit result requires
accurately scaling the given value to an integer between
lOS and 109 • For example, the number +0.123456789
requires a scaling factor of 109 to produce the value
+ 123456789.0 which can be stored in 9 BCD digits. The
scale factor must be an exact power of 10 to avoid to
changing any of the printed digit values.
These routines should exactly convert all values exactly
representable in decimal in the field size given. Integer
values which fit in the given string size, will not be
scaled, but directly stored into the BCD form. Non·
integer values exactly representable in decimal within
the string size limits will also be exactly converted. For
example, 0.125 is exactly representable in binary or
., decimal. To convert this floating point value to decimal,
the scaling factor will be 1000, resulting in 125. When
scaling a value, the function must keep track of where
the decimal point lies in the final decimal value.
DESCRIPTION OF OPERATION

Converting a floating point number to decimal ASCII
takes three major steps: identifying the magnitude of
the number, scaling it for the BCD data type, and converting the BCD data type to a decimal ASCII string.
Identifying the magnitude of the result requires finding
the value X such that the number is represented by
1*IOX, where 1.0 < = 1< 10.0. Scaling the number requires multiplying it by a scaling factor lOS, such that
the result is an integer requiring no more decimal digits
than provided for in the ASCII string.
Once scaled, the numeric rounding modes and BCD
conversion put the number in a form easy to convert to
decimal ASCII by host software.
Implementing each of these three steps requires attention to detail. To begin with, not all floating point
values have a numeric meaning. Values such as infinity,
indefinite, or Not A Number (NAN) may be encountered by the conversion routine. The conversion
routine should recognize these values and identify them
uniquely.
Special cases of numeric values also exist. Denormals,
unnormals, and pseudo zero all have a numeric value
but should be recognized since all of them indicate that
precision was lost during some earlier calculations.
Once it has been determined that the number has a
numeric value, and it is normalized setting appropriate
unnorrnal flags, the value must be scaled to the BCD
range.

Scaling the Value
To scale the number, its magnitude must be determined.
It is sufficient to calculate the magnitude to an accuracy
of 1 unit, or within a factor of 10 of the given value.
After scaling the number, a check will be made to see if
the result falls in the range expected. If not, the result
can be adjusted one decimal order of magnitude up or
down. The adjustment test after the scaling is necessary
due to inevitable inaccuracies in the scaling value.
Since the magnitude estimate need only be close, a fast
technique is used. The magnitude is estimated by multiplying the power of 2, the unbiased floating point exponent, associated with the number by log lO2. Rounding
the result to lID integer will produce an estimate of sufficient accuracy. Ignoring the fraction value can introduce a maximum error of 0.32 in the result.
Using the magnitude of the value and size of the number
string, the scaling factor can be calculated. Calculating
the scaling factor is the most inaccurate operation of the
conversion process. The relation IOX=2**(X*log210) is
used for this function. The exponentiate instruction
(F2XM1) will be used.
Due to restrictions on the range of values allowed by the
F2XM I instruction, the power of 2 value will be split into integer and fraction components. The relation
2**(1 + F) = 2**1 * 2**F allows using the FSCALE instruction to recombine the 2**F value, calculated
through F2XMI, and the 2**1 part.

Inaccuracy in Scaling
The inaccuracy of these operations arises because of the
trailing zeroes placed into the fraction value when stripping off the integer valued bits. For each integer valued
bit in the power of 2 value separated from the fraction
bits, one bit of precision is lost in the fraction field due
to the zero fill occurring in the least significant bits.
Up to 14 bits may be lost in the fraction since the largest
allowed floating point exponent value is 214-1.
AVOIDING UNDERFLOW AND OVERFLOW

The fraction and exponent fields of the number are separated to avoid underflow and overflow in calculating
the scaling values. For example, to scale 10- 4932 to 108
requires a scaling factor of 104950 which cannot be represented by the NPX.
By separating the exponent and fraction, the scaling
operation involves adding the exponents separate from
multiplying the fractions. The exponent arithmetic will
involve small integers, all easily represented by the
NPX.

3-453

207865-001

AP·113
FINAL ADJUSTMENTS

Output Format

It is possible that the power function (GeLPower_lO)

For maximum flexibility in output formats, the position
of the decimal point is indicated by a binary integer
called the power value. If the power value is zero, then
the decimal point is assumed to be at the right of the
right-most digit. Power values greater than zero indicate
how many trailing zeroes. are not shown. For each unit
below zero, move the decimal point to the left in the
string.

could produce a scaling value such that it forms a scaled
result larger than the ASCII field could allow.
For example, scaling 9.999999999999999ge4900
by l.OOOOOOOOOOOOOOOlOe-4883 would produce
1.OOOOOOOOOOOOOOOe18. The scale factor is within the
accuracy of the NDP and the result is within the conversion accuracy, but it cannot be represented in BCD format. This is why there is a post-scaling test on the
magnitude of the result. The result can be multiplied or
divided by 10, depending on whether the result was too
small or too large, respectively.

LINE
1
2

3
4
5
6
7
8
9
10

The last step of the conversion is storing the result in
BCD and indicating where the decimal point lies. The
BCD string is then unpacked into ASCII decimal characters. The ASCII sign is set corresponding to the sign
of the original value.

SOURCE
$title(Convert a floating point number to ASCII)
name
floating to ascii
public floating-to-ascii
extrn
get_power_18:near,tos_status:near

16

This subroutine will convert the floating point number in the
top of the 8~87 stack to an ASCII string and separate power of 10
scaling value (in binary)_ The maximum width of the ASCII string
formed is controlled by a parameter which must be > 1. Unnormal values,
denormal values, and psuedo zeroes will be correctly converted.
A returned value will indicate how many binary bits of
precision were lost in an unnormal or denormal value. The maqnitude
(in terms of binary power) of a psuedo zero will also be indicated.
Integers less than 10**18 in magnitude are accurately converted if the
destination ASCII string field is wide enough to hold all the
digits. Otherwise the value is converted to scientific notation.

17
18
19

The status of the conversion is identified by the return value,
it can be:

11
12

13
14
15

20
21
22
23
24

25
26
27
28

29

o
1
2
3
4
5
6
7
8

conversion complete, string size is defined
invalid arguments
exact integer conversion, string size is defined
indefinite
+ NAN (Not A Number)
- NAN
+ Infinity
- Infinity
psuedo zero found, string_size is defined

30

31

The PLM/86 calling convention is:

32

33
34
35
36
37

38
39
40

41

floating to ascii:
procedure (number,denormal ptr,string ptr,size ptr,field size,
power-ptr) word external;
declare (denormal ptr,string ptr,power ptr,size ptr) pointer;
declare field size word, strIng size based size-ptr word;
declare number real;
declare denormal integer based denormal ptr;
declare power integer based power ptr; end floating_to_ascii;
-

42
43

44
45
46
47
48

The floating point value is expected to be on the top of the NPX
stack. This subroutine expects 3 free entries o~ the NPX stack and
will pop the passed value off when done. The generated ASCII string
will have a leading character either '-' or '+' indicating the sign
of the value. 'l'he ASCII decimal digits will immediately follow.
The numeric value of the ASCII str.ing is (ASCII STRING.)*10**POWER.

3-454

207865-001

AP-113

49
50
51
52
53
54
55
56
57

It the given number was zero, the ASCII string will contain a siqn
and a single zero chacter. The value string size indicates the total
length of the ASCII string including the sign character. String(liJ) will
always hold the sign.
It is possible for string size to be less than
field size. This occurs for zeroes or integer values. A psuedo zero
will return a special return code.
The denormal count will indicate
the power of two originally associated with the value.
The power of
ten and ASCII string will be as if the value was an ordinary zero.

~8

This subroutine is accurate up to a maximum of 18 decimal digits for
integers.
Integer values will have a decimal power of zero associated
with them.
For non integers, the result will be accurate to within 2
decimal digits of the 16th decimal place (double precision). The
exponentiate instruction is also used for scalinq the value into the
range acceptable for the BCD data type. The roundinq mode in effect
on entry to the subroutine is used for the conversion.

59
60
61
62

63
64
65
66
67
68
69
70
71
72
73
14

bp_save

15

es save

76
77
78
79
80

81
82
83
84
85
86
87
88
89
90
91
92

93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119

The followinq registers are not transparent:
ax bx cx dx si di flags

Define the stack layout.

return ptr
power ptr
field-size
size ptr
string ptr
denormal_ptr

equ
equ
equ
equ
equ
egu
equ
equ

word ptr [bpJ
bp save + size bp_save
es-save + size es save
return ptr + size-return ptr
power-ptr + size power ptr
field size + size fiela size
size ptr + size size ptr
string_ptr + size string_ptr

parms_size

equ

size power ptr + size field size + size size ptr +
size strinq_ptr + size nenormal_ptr

&

Define constants used
BCD DIGITS
WORD bIZE
BCD irIZE
MINUS
NAN
INFINITY
INDEFINITE
PSUEDO ZERO
INVAL1D
ZERO
DENORMAL
UNNORMAL
NORMAL
EXACT

equ
equ
equ
egu
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

Number of digits in hcd value

18
2
1~

Define return values
The exact values chosen here are
important. They must correspond to
the possihle return values and be in
the same numeric order as tested by
the proqram.

1
4

6
3
8

-2
-4
-6

-8

o
2

Define layout of temporary storage area.
status
power two
power-ten
bcd value
bcd-byte
fraction

equ
equ
equ
equ
equ
equ

word ptr [bp-WORD bIZE)
status - WORD bIZE
power two - WORD bIZE
tbyte-ptr power ten - BCD bIZE
byte ptr bcd value
bcd val ue
-

local size

equ

size status + size power_two + size power_ten
+ size bcd value

&

-

Allocate stack space for the temporaries so the stack will be big enough
stack

segment stack .'stack·
db
(10cal_size+6) dup (?)

stack

ends

3-455

207865-001

inter
128
121
122
123
124
125'
126
127
128
129
130
131
132
133
134

AP-113

cgroup
code

group
code
segment public 'code'
assume cs:cgroup
extrn
power _table:qword
Constants used by this function.
even

const10

; Optimize 'for 16 bits
; Adjustment value for too big BCD

dw

.Convert the C3,C2,C1,C0 encoding from tos status into meanin7ful bIt
flags and values.
status table

db

13 :,

'.J()R~~L,

136

ZERO, INVALID, ZERO + MINUS, INVALID,

137

DENORMAL, INVALID, DENORMAL + MINUS, INVALID

I'IFINITY, NOR"IAL + MINllS, INFINITY + MINUS,

138
139

140
141
142
143
144

call
mov
mov
cmp
jne

145
146
147
148

~T(0)

149
150
151
;

found_infinity:

156

Look at status of ST(0)
Get descriptor trom table

al,status tab1e[bxj
aI, INVALID
not_empty
IS empty!

Look for empty ST(0)

Return the status value.

Remove infinity from stack and exit.

152

153
154
155

tos status
bx,ax

fstp
jmp

st

(9)

OK to leave fstp runninq

short ex i t_proc

157

158
159
169

String space is too small!

Return invalid code.

small_string:

161

162
163
164
165
166

167
168
169
178
171

172
173
174
175
176

177
178

179
188

mov

a1,INVALID

mov
pop
pop
ret

sp,bp
bp
es
parms_size

ST(II IS NAN or indefinite.

Free stack space
Restore registers

Store the value in memory and look

at the ~raction field to separate indefinite ~rom an ordinary NAN.

NAN_Of_indefinite:
fstp
test
hait
jz

fraction
aI,MINUS
e.xltyroc

Remove value from stack for examination
Look at sign bit
Insure store is done
Can't be indefinite If positive

3-456

207865-001

AP-113

181
182
183
184
185
186
187

wov
sub
or
or
or
jnz

bx,0C000H
bx,word ptr
bx,~ord ptr
bx,word ptr
bx,word ptr
exit_proc

1~8

mov
jmp

al,INDEFINITE
exit_proc

189
190
I'll
192
193
194
195
196
197
198
199
200
201
202
2.,3
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
22fi
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
24fi
247
248
249
250
251
252
253
254

fraction+6
fraction+4
fraction+2
fraction

Match against upper 16 bits of fraction
Compare bits 63-48
Bits 32-47 must be zero
Bits 31-16 must be zero
Bits l5~0 must be zero
Set return value for indefinite value

Allocate stack space for local variables and establish parameter
addressibility.
not empty:

-

push
push
mov
sub

es
bp
bp,sp
sp,local size

Save working register

mov
cmp
j1

cx,field size
cx,2
small strinq

Check for enough string space

dec
cmp
jbe

cx
cX,RCD DIGITS
size ok

Adjust for sign character
See if string is too large for BCD

mov

cx,BCD DIGITS

Else set maximum string size

cmp
jge

ill,INFINITY
found_infinity

Look for infinity
Return status value for + or -

cmp
jge

al,NAN
NAN or indefinite

Look for NAN or INDEFINITE

Establish stack addressibility

-

-

size ok:

-

info

-

Set default return values and check that the number is normalized.
fabs

<

mov
xor
mov
mov
mov
mov
cmp
jae c

dx,ax
ax,ax
di ,denormal ptr
word ptr [di] ,ax
bx,power ptr
word ptr-[bx] ,ax
dl,ZERO
real zero

cmp
jae

d 1 ,DENORMAL

Use positive value only
sign bit in al has trua sign of value
Save return vaiue for later
Form 0 constant

Zero denormal count
Zero power of ten value
Test for zero
Skip power code if value is zero
Look for a denormal value
Handle it specially

found_denormal

fxtract
cmp
d 1, UNNORMAL
jb
normal value
sub

Separate exponent from siqnificand
Test for unnormal value

dl,UNNORMAL-NORMAL

; Return normal status with correct sign

Normalize the fraction, adjust the power of two in STIll and set
the denormal count value.
Assert: 0

<=

ST(!'!)

<

1.0

ndl

Load constant to normalize fraction

normalize fraction:
fadd
st (1) ,st
fsub
fxtract

Set integer bit in fraction
Form normalized fraction in ST(9)
Power of two field will be neqative
of denormal count
Put denormal count in ST(9)

fxch

3-457

207865-001

inter
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310

AP-113

word ptr [di]
st(2),st

neg
jnz

word ptr [dil
not_psuedo_zero

Put negative of denorma1 count in memory
Form correct power of two in stell
OK to use word ptr [di] now
Form positive denormal count

A psuedo zero will appear as an unnormal number. When attempting
to normalize it, the resultant fraction field will be zero. Performing
an fxtract on zero will yield a zero exponent value.
fxch
fistp

word ptr [di]

sub
jmp

dl,NORMAL-PSUEDO ZERO
convert_inteqer -

Put power of two value in st(ll)
Set denormal count to power of two value
Word ptr [di] is not used by convert
integer, OK to leave runninq
Set return value savinq the sign bit
Put zero value into me~ory

The number is a real zero, set the return value and setup for
conversion to BCD.

sub
jmp

,

dr, ZERO-NORMAL
convert _i nteger

Convert status to normal value
Treat the zero as an integer

The number is a denormal. FXTRACT will not work correctly in this
case. To correctly separate the exponent and fraction, add a fixed
constant to the exponent to guarantee the result is not a denormal.

found_denormal:
Prepare to bump exponent

fldl
fxch
fprem

Force denormal to smallest representable
extended real format exponent
This will work correctly now

fxtract

The power of the original denormal value has been safely isolated.
Check if the fraction value is an unnor~al.
fxam
fstsw
fxch
fxch
sub
test
jz

st(2)
dl,DENOHMAL-NORMAL
status,4400H
normalize fraction

See if the fraction is an unnormal
Save status for later
Put exponent in ST(0)
Put 1.0 into ST(0), exponent in ST(2)
Return normal status with correct sign
See if C3=C2=0 impling unnormal or NAN
Jump if fraction is an unnormal

fstp

st (0)

Remove unnecessary

status

l.~

from st(ll)

Calculate the decimal magnitude associated with this number to
within one order. This error will always be inevitable due to
rounding and lost precision. As a result, we will deliberately fail
to consider the LOG10 of the fraction value in calculating the order.
Since the fraction will always be 1 (= F ( 2, its LOG10 will not change
the basic accuracy of the function. To get the detimal order of magnitude,
simply multiply the power of two by LOG10(2) and truncate the result to
an integer.

311

312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327

fillt
faddp

1

normal value:

not~psuedo_zero:

fstp
fist
fldlg2
fmul
fistp

Save the fraction field for later use
Save power of two
Get LOG10 (2)
Power two is now safe to use
Form LOG10(of exponent of number)
Any rounding mode will work here

fraction
power_two

power _ten

Check if the magnitUde of the number rules out treating it as
an integer.
CX has the maximum number of decimal digits allowed.

3-458

207865-001

AP-113

328
329
33e
331
332
333
334
335
336
337
338
339

fwa it
mov
sub
ja

Wait for power ten to be valid
Get power of ten of value
Form scaling factor necessary in ax
Jump if number will not fit

ax,power_ten

ax,cx
adjust_result

The number is between
and l"**(field_size).
Test if it is an integer.
power two
si ,dx dl,NORMAL-EXACT
fraction

347

fild
mov
sub
fld
fscale
fst
frndint
fcomp
fstsw
test
jnz

348
349
350

fstp
mov

st(0)
dx,si

340
341
342
343

344
345
346

Restore original number
Save return value
Convert to exact return value
Form full value, this is safe here
Copy value for compare
Test it its an integer
Compare values
Save status
C3=1 implies it was an integer

stell
status
status,4000H
convert_integer

Remove non integer value
Restore original return value

351
352
353
354
355

Scale the number to within the range allowed by the BCD format.
The scaling operation should produce a number within one decimal order
of magnitude of the largest decimal number representable within the
given string width.

356
357
358
359
360

The scaling power ot ten value is in ax.

,

adjust result:

361
362
363
364

mov
neg

word ptr [bxJ ,ax
ax

call

get _power_ 10

fld
fmul
mov
shl
shl
shl
fild
faddp
fscale
fstp

fraction

Set initial power ot ten return value
Subtract one for each order of
magnitude the value is scaled by
Scalinq factor is returned as exponent
and fraction
Get fraction
Comoine fractions
Form power of ten of the maximum
BCD value to fit in the string
Index in si

365
366
367
3<;8
369
37e

371
372
373

j74
375
37h
377
378
379

3-86

fstsw
test
jnz

power _table [si) +type power table; Compare against exact power
entry.
Use the next entry since ex
has been decremented by one
No wait is necessary
status
status,4HHlH
If C3 = CII = " then too big
test for_small

fidiv
and
inc
jmp

constl!!
dl,not EXACT
word ptr [bx)
short in _range

Else adjust value
Remove exact flag
Adjust power of ten value
Convert the value to a BCD integer

power_table lsi I
status

Test relative size
No wait is necessary

feom

393

4""
4"1

Form full value, exponent was safe
Remove exponent

stell

testyower:

387
388
389
390
391
392
394
395
396
397
398
399

Combine powers of two

Test the adjusted value against a table of exact powers of ten.
The combined errors of the maqnitude estimate and power function can
result in a value one order of magnitude too small or too large to fit
correctly in the BCD field.
To handle this problem, pretest the
adjusted value, if it is too small or large, then adjust it by ten and
adjust the power ot ten value.

3110
381
382
383
384
385

si,ex
si ,1
si,l
s i ,1
power_two
st(2) ,st

-

test for_small:

-

fcom
fstsw

3-459

207865-001

AP-113

411J2

test
jz

403

If CIIJ = IIJ then stlllJ) )= lower bound
Convert the value to a BCD integer

status,lllllJH
. in_range

411J4
fimul
dec

4I!J5

411J6
411J7'
4118
411J9

Adjust value into range
Adjust power of ten value

inJ~nge:

4111
411

frndint

; Form integer value

Assert: IIJ <= TOS <= 999,999,999,999,999,999
The TOS number will be exactly rep~esentable in 18 digit BCD format.

412
413
414

415
416

constlllJ
word ptr [bxj

convert_inteqer:
fbstp

417

Store as BCD format number

418
While the store BCD runs, setup registers for the conversion to
ASCII.

419

420
421
422
423

424
425
426
427
428

429
430
431
432
433
43 t
1<"

Y("~itive

si ,BCD SIZE-2
cx ,lIfII4h
bx,l
di,string ptr
ax,ds
es,ax

mov
mov
mov
mov
mov
mov
cld
mov
test
jz

aI, 1+'
dl,MINUS
positive_result

JT'IOV

aI, • -'

Initial BCD index value
Set slitft count and mask
Set initial size of ASCII field for siqn
Get address of start of ASCII string
Copy ds to es
Set autoincrement mode
Clear sign field
Look for aeqative value

r(l~'111t:

"::V

'37
43r.
439441')

Pll~P

C;t0Sr.
~nd

ol,not MINUS

fwa it

rnint~r

nast pinn

Register usaqe:

441

442
443
444
445
446

ah:
"1:'

ox:
ch:
cl:
hx:
si:
eli:
ds,es:

447
448
449

450
451
452
453
454
455
456

q~rin~

Turn off siqn bit
Walt tor fbstp to finish
BCD byte value in use
ASCII character value
Return vAlue
RCD mask = I'Jfh
BCD shift count = 4
ASClI string field wioth
BCD field index
ASCII strinq field pointer
ASCII string seqment base

Remove leading zeroes from the number.
;

skip_leading_zeroes:
mov
mov
shr
and
jnz

ah,bcd _byte[sij
al,ah
alJcl
al,ch
enter odd

Get BC,D byte
Copy value
Get high order digit
Set zero flag
Exit loop if leading non zero found

mov
and
jnz

al,ah
al,ch
enter _even

Get BCD byte again
Get low order digit
Exit loop'if non zero digit found

dec
jns

si
skip_leading _zeroes

Decrement BCD index

467

468
469
4711J
471
472
473
474

mov
stosb
inc
jmp

457

458
459
460

461
462

463
464
465

466

'1'he significand was- all zeroes.
aI, '11lJ'

Set initial zero

bx
short exit_with_value

Bump string length

3-460

207865-001

inter
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
'!>00
501
502
503
504
!>05
506
507
508
509
510

AP-113

NOW

,

expand the BCD string into digit per byte values 0-9.

dieli t_loop:
mov
mov
shr

ah ,bcd_byte [si I
al,ah
al,cl

Get BCD byte

aI, '0

Convert to ASCII
Put digit into ASCII string area
Get low order digit

Get high order digit

enter odd:
add
stosb
mov
and
inc

I

al,ah
al,ch
bx

Bump field size counter

enter even:

-

add
stosb
inc
dec
jns

,

al,'"

Convert to ASCII
Put digit into ASCII area
Bump field size counter
~o to next BCD byte

I

bx
si
digit_loop

Conversion complete.

Set the string size and remainder.

exit_with value:
mov
mov
mov
jmp

di,size ptr
word ptr [di] ,bx
ax,dx
exi t_proc

floating to ascii
code
-

Set return value

endp
ends

511

end

ASSEMBLY COMPLETE, NO ERRORS FOUND

LINE
1
2
3
4

SOURCE
~title(Calculate

This subroutine will calculate the value of l0**ax.
All 8086 registers are transparent and the value is returned on
the TOS as two numbers, exponent in STIll and fraction in ST(I'l).
The exponent value can be larger than the maximum representable
exponent. Three stack entries are used.

5
6
7
8

name
public

!i

10
11
12
13

14
15
16
17
18
19
20
21
22
23

the value of l0**ax)

stack

get power 10

get=power~10,power table

segment stack
'stack'
dw
4 dup (1)

stack

ends

cgroup
code

group
code
segment public 'code'
assume cs:cgroup

Allocate space on the stack

Use exact values from- 1.0 to le18.
even
power table

dq

Optimize 16 bit access
1.",lel,1e2,1e3

3-461

207865-001

AP-113

24

dq

le4,le5,le6,le7

25

dq

le8,le9,le10,lell

26

dq

le12,le13,le14,le15

27

dq

le16,le17,le18

28
29
30
31
32
33
34
35
36
37
38
39

4"

41
42
43
44
45
46
47
48

49

50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71

proc
cmp
ja

ax,18
out_of_range

Test fer"

push
mov
shl
shl
shl
fld
pop
fxtract
ret

bx
bx,ax
bx,l
bx,l
bx,l
power table[bx]
bx-

Get working index register
Form table index

(=

ax < 19

Get exact value
Restore register value
Separate power an~ fraction
OK to leave fxtract running

Calculate the value using the exponentiate instruction.
The following relations are used:
l0**x = 2**(log2(10)*x)
2**(1+F)
2**1 * 2**F
if st(l) = I and st(") = 2**F then fscale produces 2**(1+F)

fldl2t
push
mov
push
push
fimul
fnstcw

bp
bp,sp
ax
ax
word ptr [bp-2]
word ptr [bp-4]

mov
and
or
xchg

ax,word ptr [bp-4)
aX,not 0C00H
ax,04""H
aX,word ptr [bp-4)

fldl
fchs
fld
fldcw
frndint
mov
fldcw

st(l)
word ptr [bp-4)

TOS = LOG2 (Hll)
Establish stack addressibility
Put power (P) in memory
Allocate space for status
TOS,X = LOG2/10)*P = LOG2(l"**P)
Get current control word
Control word is a static value
Get control word. no wait necessary
Mask off current rounding field
Set round to negative infinity
Put new control word in memory
old control word is in ax
Set TOS = -1.0
Copy power value in base t~o
Set new control word value
TOS
I: -inf < I (= X, I is an integer
Restore original rounding control

=

word ptr [bp-4),ax
word ptr [bp-4)

3-462

207865-001

AP-113

72
73
74
75
76
77
78
79
80
81
82
83
84
85

fxch
pop
fsub
pop
fscale
f2xml
pop
fsubr
fmul
ret
qet_power_ 10
code

TOS ~ x, ST(l) = -1.0, ST(2)
Remove oriqinal control word
TOS,F = X-I: 0 <~ TOS < 1.0
Restore power of ten
TOS ~ F/2: 0 <= TOS < 0.5
TOS = 2**(F/2) - 1.0
Restore stack
Form 2** (F/2)
Form 2**F
OK to leave fmu1 runninq

st(2)
ax
st,st (2)
ax
bp
st,st(ll)
endp
ends
end

ASSEMBLY COMPLETE, NO ERRORS FOUND
GOlHIO:

1

$title(Determine TOS reqister contents)

2

This subroutine will return a value from 0-15 in ax correspondinq
to the contents of 8087 TOS. All registers are transparent and no
errors are possihle. The return value corresponds to c3,c2,cl,cll
of FXAM instruction.

3
4
5
6
7
8
9

name
public

tos status
tos-status

II!
11

stack

segment stack 'stack'
dw
3 dup (?)

12
13

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31'l

31
32
33
34
35
36
37

38

stack

ends

cgroup
code

group
code
segment public 'code'
assume

tos _status
fxam
push
push
mov
fstsw
pop
pop
mov
and
shr
shr
shr
or
mov
ret
tos status
code

Allocate space on the stack

cs:cqroup

proc
ax
bp
bp,sp
word ptr [bp+21
bp
ax
al,ah
aX,4""7h
ah,l
ah,1
ah,1
al,ah
ah,0

Get reqister contents status
Allocate space for status value
Establish stack addressibility
Put tos status in memory
Restore reqisters
Get status value, no wait necessary
Put bit 10-8 into bits 2-0
Mask out bits c3,c2,cl,c0
Put bit c3 into bit 11
Put c3 into hit 3
Clear return ~alue

endp
ends
end

ASSEMBLY COMPLETE, NO ERRORS FOUND

3-463

207865-001

AP·113
APPENDIX D
code simply determines the meaning of each character
encountered. Two separate number inputs must be recognized, mantissa and exponent values. Performing the
numerics operations is very straightforward.

OVERVIEW
Appendix D shows a function for converting ASCII
input strings into floating point values. The returned
value can be used by PLM/86, PASCALl86, FORTRAN/86, or ASM/86. The routine will accept a' number in ASCII of standard FORTRAN formats. Up to 18
decimal digits are accepted and the conversiqn accuracy
is the same as for converting in the other direction.
Greater accuracy can also be achieved with similar
tradeoffs, as mentioned earlier.

The length of the number string is determined first to
allow building a BCD number from low digits to high
digits. This technique guarantees that an integerwill be
converted to its exact BCD integer equivalent.
If the number is a floating point value, then the digit
string can be scaled appropriately. If a decimal point oc-'
curs within the string, the scale factor must be decreased
by one for each digit the decimal point is moved to the
right. This factor must be added to any exponent value
specified in the number.

Description of Operation
Converting from ASCII to floating point is less complex
numerically than going from floating point to ASCII. It
consists of four basic steps: determine the size in decimal digits of the number, build a BCD value corresponding to the number string if the decimal point were
at the far right, calculate the exponent value, and scale
the BCD value. The first three steps are performed by
the host software, The fourth step is mainly performed
by numeric operations.

ACCURACY CONSIDERATIONS

All the same considerations for converting floating
point to ASCII apply to calculating the scaling filctOr.
The accuracy of the scale factor determines the accuracy
of the result.
The exponents and fractions are again kept separate to
prevent overflows or underflows during the scaling
operations.

The complexity in this function arises due to the flexible
nature of the input values it will recognize. Most of the
LINE
1

SOURCE
Stitle(ASCII to floating point conversion)'

2
3
4
5
6
7
8
\I

10
11

Define the publicly known names.
name
public
extrn

ascii to floating
ascii-to-floating
get-power_ll!l:near

This function will convert an ASCII character string to a floating
point representation. Character strings in integer or scientific form
will be accepted. The allowed format is:

12
13

14
15

16
17
18

19
20

21
22
23
24
25

[+,-j [digit(s)1 [.1 [digit(s)] [E,e) [+,-) [digit(s)}

Where a digit must have been encountered before the exponent
indicator IE' or'e'..
If a 1+', '_I, or I. I was encountered, then at
least one digit must exist before the optional exponent field. A value
will always be returned in the BA8? stack. In case of invalid numbers,
values like indefinite or infinity will be retur,ned.
The first character not fitting within the format will terminate the
conversion. The address of the terminating character will be returne~
by this.subroutine.

28
29

The result will be left on the top of the NPX stack. This
subroutine expects 3 free NPX stack reqisters. The sign of the result
will correspond to any sign characters in the ASCII string. The rounding
mode in effect at the time the subroutine was ~alled will be used for
the conversion from h,se 10 to base 2. Up to 18 significant decimal

30

digits may appear in the number.

31

exponent riQits ro not count towards the 18 riiQit maximum. Integers
or exactly representable decimal numbers of 18 digits or less will be
exactly converted. The technique used constructs a BCD number

26
27

32
33

Leari~~

7~rne~,

rr~i]jnn

7ArOp.s, or

.
3-464

207865-001

AP-113

representing the siqnificant ASCII digits of the string with the decimal
point removed.

34
35
36
37
38
39

An attempt is made to exactly convert relatively small inteqers or
small fractions.
ror example the values: .1'16125, 1234567891'112345li78,
le17, 1.23456e5, and 125e-3 will be exactly converted to floating point.
The exponentiate instruction is used to scale the generated BCD vaslue
to very large or very small numbers. The basic accuracy of this function
determines the accuracy of this subroutine.
For very large or very small
numbers, the accuracy of this function is 2 units in the llith decimal
place or double precision. The ranqe of decimal powers accepted is
11'1-*-4930 to 11'1**4931'1.

411
41
42
43
44
45
46
47
48
49
50

The PLM/86 calling format is:
ascii to floating:
procedure (string ptr,end ptr,status ptr) real external;
declare (string ptr,end ptr,status ptr) pointer;
declare end based end ptr pointer;declare status based status ptr word;
end;

~l

52
53
54
55

The status value has Ii possible states:

~6

57
58
59

9
1
2
3
4

• 60

61
1i2

63
64
65
li6
67
68
69
711

A number was found.
No number was found, return indefinite.
Exponent was expected but none found, return indefinite •
Too many digits were found, return indefinite.
Exponent was too biq, return a siqned infinity.

The following registers are used by this subroutine:
ax

bx

ex

dx

di

si

Define constants.

71

72
73
74
75
76

LOW EXPONENT
HIGH EXPONENT
WORD-bIZE
BCD bIZE

1116

1"7

Smallest allowed power of 10
Largest allowed power of III

-4931l
4931'1
2
III

Define the parameter layouts involved:

77

78
79
80
81
82
83
84
85
86
87
88
89
91'1
91
92
93
94
95
96
97
98
99
101'1
1111
192
1113
1Il4
IllS

equ
equ
equ
equ

hp save
return ptr
status -ptr
end ptr
strTngytr

equ
equ
equ
equ
equ

word ptr [bp]
bp save + size bp save
return ptr + size-return ptr
status-ptr + size status-ptr
endytr + size end_ptr -

equ

size status_ptr + size endytr + size string_ptr

Define the local variable data layouts
power ten
bed form
local size

equ
equ

word ptr [bp- WORD SIZE] ; power of ten value
tbyte ptr power_ten - BCD_SIZE; BCD representation

equ

size power_ten + size bcd_form

Define common expressions used
bed byte
bcd-count
bcd-sign
bCd:S ign _ bi t

equ
equ
equ
equ

byte ptr bed form
(type(bcd form)-1)*2
byte ptr bed form + 9
811H
-

Current byte in the BCD form
Number of digits in BCD form
Address of BCD sign byte

Define return values.
;

NUMBER FOUND
equ
NO NUMBER
equ
NO-EXPONENT
equ
TOO MANY DIGITS equ
EXPONENT-TOO BIG equ

Number was found
No number was found
No exponent was found when expected
Too many digits were found
Exponent was too big

Il

1
2
3
4

3-465

207865-001

inter
108
U9
110

AP-113

AI-locate stack space to insure enough exists at run time.

,

III

stack

segment stack • st'ack'
(local _size+4) dup (?)
db

113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129

stack

ends

cgroup
code

group
code
segment public 'code'
assume cs:cgroup

112

130
131

132
133
134
135

136
137

Define some of the possible return values.

dd
dd

0FFCI!01H10R
07FF80"'00R

ascii to_floating proc
fldz
push
mov
sub

Get any leading sign character to form initial BCD template.
mov
xor
cld

si ,string ptr
dx,dx
-

Register usage:

140

all
cx:
dx:
si:

141

142
143
144

148

149
150
151

152
153
154

155
156
157
158

159
160

Prepare to zero BCD value
Save callers stack environment
Establ i sh stack addressi bili ty
Allocate space for local variables

bp
bp,sp
sp,local size

138
139

145
14fi
147

Optimize 16 bit access
Single precision real for indefinite
Single precision real for +infinity

even

indefinite
infinity

Get starting address of the number
Set initial decimal digit count
Set auto increment mone

Current character value being examined
Digit count before the necimal point
Total digit count
Pointer to character string

Look for an initial sign and skip it if found.
lodsb
cmp
jz

aI, '+ I
scan_leading diqits

Get first character
Look for a siqn

cmp
jnz

al, ,_I
enter_leading_digits

fchs

If not "-" test current character
Set TOS

= -0
<

Count tbe number of digits appearing before an optional decimal point.
scan_leading_digits:
Get next character

lodsb

161

162
163
164
165
166

167
168

169
170
171
172
173
174
175
176

call
jnc

; Test for digit and bump counter

test digit

scan~leading_digits

Look for a possible decimal point and start fbstp operation.
Tbe fbstp zeroes out the BCD value and sets the correct sign.
fbstp
mov.
cmp
jnz

Set initial sign and value of BCD number
Save count of digits before decimal point

bcd form
cx,dx
a1,' . I
test_for_digits

Count the number of digits appearing after the decimal point.

177
178

179

lodsb

Look at next character

3-466

207865-001

AP-113

188
181
182
183
184
185
186
187
188
189
191'1
191
192
193
194
195
196
197
198
199

call
jnc

test digit
scan:trai1ing_digits

There must be at least one digit counted at this point.

dec
or
jz

si
dx,dx
no _number found

Put si back on terminating character
Test digit count
Jump if no digits were found

push
dec

si
si

Save pointer to terminator
Backup pointer to last digit

Check that the number will fit in the 18 digit BCD format.
CX becomes the initial scaling factor to account for the implied
decimal point.
sub

cX,dx

201
202
203

neg

dx

204

cmp
jb

dX,-bcd count
;
test for unneeded _digi ts

200

21'15
206

For each digit to the right of the
decimal point, subtract one from the
initial scaling power
Use negative digit count so the
test_digit routine can count = 1.
call
fbld
fmul
jmp

509
510

get power Hl
bcd:form -

Get the adjustment power of ten
Get the digits to use
Form converged result

short done

Calculate a power of ten value> 1 then divide the BCD value with
it. This technique is more exact than multiplying the 8CD value by
a fraction since no negative power of ten can be exactly represented
in binary floating point. Using this technique will guarentee exact
conversfon of values like .5 and .0625.

511
512
513
514
515
516

; Adjust string pointer

get negative_power:

517
neg
call
fbld
fdivr
fxch
fchs
fxch

518
519

5213
521
522
523
524
525

534

535
536
537

538
539

540
541
542

543
544
545

546
547

Force positive power
Get the adjustment power of ten
Get the digits to use
Divide fractions
Negate scale factor

All done, set return values.

526

527
528
529
530
531
532
533

ax
get power 10
bcd:=form -

done:
fscale
mov
fstp

Update exponent of the result
Set return value
Remove the scale factor

ax,NUMBER FOUND
stell
-

exit:
mov
mov
mov
mov
mov
pop
fwait
ret

di,status ptr
word ptr Tdil,ax
di ,end ptr
word ptr [dil,si
sp,bp
bp

Set status of the conversion
Set ending string address
Deallocate local storage area
Restore caller's environment
Insure all loads from memory are done

Test if the character in al is an ASCII digit.
If so then convert to binary, bump cx, and clear the carry flag.
Else leave as is and set the carry flag.

3-471

207865-001

AP·113

548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570

,
test_digit:
cmp
ja

aI, '9

See i f a digit

I

not_digi t

cmp

al,' g.

jb

not_digit

Character is a digit.
inc
sub
ret

,

dx
al,'0'

Bump digit count
Convert to binary and clear carry flag

Character is not a digit

not digit:
stc
ret

Leave as is and set the carry flag

ascii to floating endp
code - ends
end

ASSEMBLY COMPLETE, NO ERRORS FOUND

APPENDIX E
OVERVIEW
Appendix E contains three trigonometric functions for
sine, cosine, and tangent. All accept a valid angle argument between - 262 and + 262. They may be called from
PLM/86, PASCALl86, FORTRAN/86 or ASM/86
functions.
They use the partial tangent instruction together with
trigonometric identities to calculate the result. They are
accurate to within 16 units of the low 4 bits of an extended precision value. The functions are coded for
speed and small size, with tradeoffs available for greater
accuracy.

FPTAN and FPREM
These trigonometric functions use the FPTAN instruction of the NPX. FPTAN requires that the angle argument be between 0 and P'I/4 radians, 0 to 45 degrees.
The FPREM instruction is used to reduce the argument
down to this range. The low three quotient bits set by
FPREM identify which octant the original angle was in.
One FPREM instruction iteration can reduce angles of
10 18 radians or less in magnitude to P1I4! Larger values
can be reduced, but the meaning of the result is questionable since any errors in the least significant bits of
that value represent changes of 45 degrees or more in the
reduced angle.

Cosine Uses Sine Code
To save code space, the cosine function uses most of the
sine function code. The relation sin (IAI + PI12) =
cos(A) is used to convert the cosine argument into a sine

argument. Adding PI12 to the angle is performed by
adding 0102 to the FPREM quotient bits identifying the
argument's octant.
It would be very inaccurate to add PI12 to the cosine

argument if it was very much different from PII2.
Depending on which octant the argument falls in, a different relation will be used in the sine apd tangent functions. The program listings show which relations are
used.
For the tangent function, the ratio produced by FPTAN
will be directly evaluated. The sine function will use
either a sine or cosine relation depending on which octant the angle fell into. On exit these functions will normally leave a divide instruction in progress to maintain
concurrency.
If the input angles are of a restricted range, such as from

o to 45

degrees, then considerable optimization is possible since full angle reduction and octant identification
is not necessary.

All three functions begin by looking at the value given
to them. Not a number' (NAN), infinity, or empty registers must be specially treated. Unnormals need to be
converted to normal values before the FPTAN instruction will work correctly. Denormals will be converted to
very small unnormals which do work correctly for the
FPTAN instruction. The sign of the angle is saved to
control the sign of the result.
Within the functions, close attention was paid to maintain concurrent execution of the 8087 and host. The
concurrent execution will effectively hide the execution
time of the decision logic used in the'program.
3-472

207865-001

Ap·113
LINE

SOURCE
$tit1e(8187 Trignometric Functions)

1

2
3
4
5
6 +1
7
8
9
111
11

public
name
$include (:fl:8187.anc)

Define 8187 word packing in the environment area.

,,
,
,,sw 87
,
,tw 87
cw 87

12
13
14
15
16
17
18
19
211
21

record

res871:3,infinity control:1,rounding control:2,
precision control:2,error enable:l,res872:l,
precision-mask:l,underflow mask:l,overflow mask:l,
zero_divlde_mask:l,denormaf_mask:l,invalid:mask:l

record

busy:l,cond3:I,top:3,cond2:I,condl:l,condll:l,
error-pending:l,res873:l,precision error:l,
underflow error:l,overflow error:l;zero divide error:l,
denormal_error:l,invalid_error:l
-

record

reg7 tag:2,reg6 tag:2,regS tag:2,req4 taq:2,
reg3:tag:2,reg2:taq:2,reql:tag:2,req8:taq:2

22

23
24
25
26
27
28
29
311
31
32
33

34
35
36
37
38
39
48

~

low_ip_87

record

low_ip:16

high_ip_op_87

record

hi_ip:4,res874:l,opcode_87:l1

low_op_87

record

low_op:16

high_op_87

record

hi_op:4,resB7S:12

environment_87
env87 cw
env87-sw
env87-tw
env87-low ip
env87nip-op
env87-low-op
env87-hopenvironment_87

struc
dw
dw
dw
dw
dw
dw
dw
ends

41

42
43

sine,cosine,tangent
trig_functions

81187 environemnt layout
?
?
?

?
?
?

?

Define 81187 related constants.
;

TOP_VALUE_INC

equ

VALID TAG
ZERO TAG
SPECrAL TAG
EMPTY TAG
REGISTER MASK

equ
equ
equ
equ
equ

sw 87

44

45
46
47
48
49
58
51
52
53
54

<8,8,l,I,8,8,~,Il,Il,Il,0,1l,0,0>

o

I Tag register values

1
2

3
7

Define local variable areas.
;

stack

segment stack 'stack'

local_area
sw1
local_area

struc
dw
ends

stack

db
ends

size local_area+4

segm~nt

public 'code'
cs:code,ss:stack

55

56
57
58
S9
68
61
62
63
64
"6S
66
67
68
69
78

code

assume

8087 status value

?

Allocate stack space

Define local constants.
;

status

equ

[bpJ.swl

8087 status value location

3FFEC98FDAA22168C235R

PI/4

even

71

72

dt

3-473

207865-001

inter

AP-113

indefinite

73
74
75
76
77
78
79

dd

II FFCIIl0 II I!JIIR

Indefinite special value

This subroutine calculates the sine or cosine of the angle, given in
radians. The angle is in ST(II), the returned value will be in ST(II).
The result is accurate to within 7 units of the least significant three
bits of the NPX extended real format. The PLM/86 definition is:

811
81
82
83

sine:

procedure (angle) real external;
declare angle real;
end sine;

84

85
86
87

cosine: procedure (angle) real external;
declare angle real;
end cosine;

88

89
911
91
92

Three stack registers are required. The result of the function is
defined as follows for the following arguments:
angle

result

93

valid or unnormal less than 2**62 in magnitude
zero
denormal
valid or unnormal greater than 2**62
infinity
NAN
empty

94
95
96
97

98
99

11111
1111
1112
1113
1114
1115
1116
1117
1118
1119

This function is based on the NPX fptan instruction. The fptan
instructioh will only work with an angle of from 0 to PI/4. With this
instruction, the sine or cosine of angles from 0 to PI/4 can be accurately
calculated. The technique used by this routine can calculate a general
sine or cosine by using one of four possib1e'operations:
Let R = lang1e mod PI/41
5 = -lor 1, according to the sign of the angle

110

III
112
113
114
115
116
117
118
119

1) sin(R)

'

octant

sine

cosine

0
1
2

5*1
,5*4
5*2
5*3
-5*1
-5*4
-5*2
-5*3

2
3
-1*1
-1*4
-1*2
-1*3
1
4

124
125

3
4
5
6

126

7

123

132

3) sin(PI/4-R)

2) cos(R)

4) cos(PI/4-R)

The choice of the relation and the sign of the result follows the
decision table shown below based on the octant the anqle falls in:

120
121
122

127
128
129
1311
131

correct value
II or 1
correct denormal
indefinite
indefinite
NAN
empty

.

Angle to sine function is a zero or unnorma1.

sine zero_unnormal:

133
fstp
jnz

134

135
136

Remove PI/4
Jump if angle is unnormal

Angle is a zero.

137
138
139

pop
ret

1411
141
142
143
144
145

stIll
enter_sine_normalize

bp

Return the zero as the result

Angle is an unnormal.
;

enter_sine_normalize:

3-474

207865-001

inter

AP-113

call
jmp

.~6

147

normalize value
short enter_sine

148

149
lSI
151
152
153
154
155
156
157
158
159
169
161
162
163
164
165

cosine

Entry point to cosine

proc
fxam
push
sub
mov
fstsw
fld
mov
pop
lahf
jc

bp
sp,size local_area
bp,sp
status
pi quarter
cl-;"l
ax
funnyyarameter

Look at the value
Establish stack addressibility
Allocate stack space for status
Store status value
Setup for angle reduce
Signal cosine function
Get status value
ZF = C3, PF = C2, CF = Clil
Jump if parameter is
empty, NAN, or infinity

Angle is unnormal, normal, zero, denormal.

166

fxch
jpe

167
168
169
1711
171

fstp
jnz

st(Il)
angle, stell = PI/4
Jump if normal or denormal

enter sine

Angle is an unnormal or zero.
st (1)
enter sine normalize

Remove PI/4

172

Angle is a zero.

173
174
175
176

fstp
pop
fldl
ret

177

178
179
180
181
182
183
184
185
186

187
188
189
190
191
192
193
194
195

st (II)
bp

Remove "
Restore stack
Return 1

All work is done as a sine function. By adding PI/2 to the angle
a cosine is converted to a sine. Of course the angle addition is not
done to the argument but rather to the program looic control values.
Entry point for sine function

sine:
fxam
push
sub
mov
fstsw
fld
pop
lahf
jc

bp
sp,size local_area
bp,sp
status
pi_quarter
ax
funny _parameter

Look at the parameter
Establish stack addressibility
Allocate local space
Look at fxam status
Get PI/4 value
Get fxam status
CF = CIl, PF = C2, ZF = C3
Jump if empty, NAN, or infinity

Angle is unnormal, normal, zero, or denormal.

196

197
198
199
21111

cos(9) = 1.0

fxch
mov
jpo

cl,9
sine_zero_unnormal

=

STell
PI/4, st(ll) angle
Signal sine
Jump if zero or unnormal

2111

2112
293
204
2115
206
2117
298

ST(II) 1S either a normal or denormal value. Both will work.
Use the fprem instruction to accurately reduce the range of the given
angle to within III and PI/4 in magnitude. If fprem cannot reduce the
angle in one shot, the angle is too big to be meaningful, > 2**62
radians. 'Any roundoff error in the calculation of the angle given
could completely change the result of this function.
It is safest to
call this very rare case an error.

209
210

211
212
213
214
215
216

enter sine:
fprem

Reduce angle
Note that fprem will force a
denormal to a very small unnormal
Fptan of a very small unnormal
will be the same very small
unnormal, which is correct.
Allocate stack space for status
rhack if renuction WAS COMplete

217

218
219

mov
fstsw

sp,bp
status

3-475

207865-001

inter
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
2511J
251
252
253
254
255
256
257
258
259
2&0
261
262
263
264
2&5
266
267
268
269
270
271

AP-113

pop
test
jnz

277

278
279
2811J
281
282
283
284
285
286
287
288
289
2911J
291
292
293

Quotient in C0,C3,C1
Get fprem status
, sin (2*N*PI+x) - sin (x)

Set sign flags and test 'for which eighth of the revolution the
angle fell into.
Assert: -PI/4 < st(l) < PI/4
Force the argument positive
condl bit in bx holds the sign
Test for sine or cosine function
Jump if sine function

~abs

cl,cl
sine_select

or
jz

This is a cosine function. Ignore the original sign of the angle
and add a quarter revolution to the octant id from the fprem instruction.
cos (A) • sin(A+PI/2) and cos(IAI) • cos(A)

,

and
or

ah,not high(mask condl)
bh,high(mask busy)

add
mov
rcl
xor

bh,high(mask cond3)
al,1
al,l
bh,al

Turn off sign of argument
Prepare to add III to C0,C3,C1
status value in ax
Set busy bit so carry out from
C3 will go into the carry flag
Extract carry flag
Put carry flag in low bit
Add carry to CI not chanqing
Cl flag
,

See if the argument should be reversed, depending on the octant in
which the argument 'fell during fprem.

sine_select:
test
jz

bh,high(mask cond1)
no_sine_reverse

Reverse angle if Cl

=1

Angle was in octants 1,3,5,7.
fsub
jmp

I

Invert sense of rotation
arg <- PI/4

o<

Angle was in octants 0,2,4,6.
for a zero argument since f~tan will not work if st(lI) • 0

,Test

no_sine":reverse:

272

273
274
275
276

bx
bh,high(mask cond2)
ang1e_too_big

. ;

ftst
mov
fstsw
fstp
pop\
test
jnz

sp,bp
status
st(l)
cx
ch,high(mask cond3)
sine_argument_zero

Test for zero angle
Allocate stack space
cond3 • I if st(0) = 0
Remove PI/4
Get ftst status
If C3-1, argument is zero

Assert: 0 < st(0) <- PI/4
;

do_sine_fptan:
fptan

TAN ST(I) • ST(l)/ST(I) - Y/X

after_sine_fptan:
pop
test
jpo

bp
; Restore stack
bh,high(mask cond3 + mask condl); Look at octant angle fell into
Calculate cosine for octants
X numerator
1.2,5,6

Calculate the sine of the argument.
sin (A) • tan(A)/sqrt(l+tan(A)**2)
sin (A) = Y/sqrt(X*X + y*y)
fld
jmp

if tan (A) • Y/X then
Copy Y value
Put Y value in numerator

st(l)
short finish_sine,

3-476

20786~1

AP-113

294
295
296
297
298
299
31111
31ll
3112
3113
3114
3115
3116
3117
3118
3119
3lll
311
312
313
314
315
316
317
318
319
321l
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
351l
351
352
353
354
355
356
357
358
359
361l
361
362
363
364
365
366

The top of the stack is either NAN, infinity, or empty.
;

funnyyarameter:
fstp
jz

st(ll)
return _empty

Remove PI/4
Return empty if no parm

jpo

return NAN

Jump if st(Il) is NAN

st(Il) is infinity.

Return an indefinite value.

fprem

; STIll can be anything

return NAN:
return:empty:
pop
ret

Restore stack
Ok to leave fprem running

bp

Simulate fptan with st(ll)

Il

sine_argument zero:
fldl
jmp

; Simulate tan(ll)
; Return the zero value

after sine_fptan

The angle was too large. Remove the modulus and dividend from the
stack and return an indefinite result.
;

angle_too_big:
fcompp
fld
pop
fwa i t
ret

,

Pop two values from the stack
Return indefinite
Restore stack
Wait for load to finish

indefinite
bp

Calculate the cosine of ' the argument.
cos (A)
1/sqrt(1+tan(A)**2)
if tan (A)
cos (A) = X/sqrt(X*X + y*y)

Y/X then

X numerator:
fld
fxch

st(ll)
st(2)

Copy X value
Put X in numerator

st,st(ll)

Form X*X + y*y

finish sine:
fmul
fxch
fmul
fadd
fsqrt

st,st(ll)
st (0)
st(ll)

X*X + y*y

= sqrt(X*X

+ y*y)

Form the sign of the ,result. The two conditions are the Cl flag from
FXAM in bh an~ the Cil flag from fprem in ah.
.
•
and
and
or
jpe

bh,high(mask condll)
ah,high(mask condl)
bh,ah
positive_sine

fchs

Look at the fprem C9 flag
Look at the fxam Cl flag
Even number of flags cancel
Two negatives make a positive
Force result negative

positive_sine:
fdiv
ret
cosine

Form final result
Ok to leave fdiv running

endp

3-477

207865-001

AP-113

367
368

This function will calculate the tangent of an angle.
The angle, in radians is passed in ST(Il), the tangent is returned
in ST(Il). The tangent is calculated to an accuracy of 4 units in the
least three significant bits of an extended real format number. The
PLM/86 calling format is:

369

371l
371
372

373
374

tangent:

375

376

procedure (angle) real external;
declare angle real;
end tangent;

377

378

Two stack registers are used. The result of the tangent function is
defined for the following cases:

379

38(1)
381
382

angle

result

valid or unnormal < 2**62 in magnitude

,383

correct value

384

II

II

385

denormal
valid or unnormal
NAN
infinity
empty

correct denormal
indefini te
NAN
indefinite
empty

386
387

388
389

39(1)
391
393
394
395
396
397
398
399
400

tan(R)

1)

octant

o

410

6

417
418

419
420
421
422
423
424
425

426
4"27
428

2)

tan (PI/4-R)

3)

l/tan (R)

4) 1/tan(PI/4-R)

The following table is used to decide which relation to use depen9ing
on in which octant the angle fell.

404
405
406
407
408
409

416

Four possible

Let R = langle MOD PI/41
S = -lor 1 depending on the sign of the angle

401
402
403

414
415

2**62 in magnitude

The tangent instruction uses the fptan instruction.
relations are used:

392

411
412
413

~

1

2
3
4

5

.

7

relation
5*1
5*4
-5*3
-S*2
5*1
5*4
-S*3
-S*2

tangent proc
fxam
push
sub
mov
fstsw

fld
pop
lahf
jc

bp
sp,size local_area
bp,sp
status
pi _quarter
ax

Look at the parameter
Establish stack addressibility
Allocate local variable space
Get fxam status
Get PI/4
CF

funny_parameter

= CIl,

PF

C2, ZF

C3

Angle is unnormal. normal, zero. or denormal.
fxch
jpe

; st(ll) = angle. stIll

PI/4

429

4311
431
432
433
434
435
436
437

438
439
4411

Angle is either an normal or denormal • .
Reduce the angle to the range -PI/4 < result < PI/4.
If fpre~ cannot perform this operation in one try, the magnitude of
angle must be > 2**62. 5uch an angle is so large that any rounding
errors could make a very large difference in the reduced angle.
It is safest to call this very rare case an error.

fprem

th~

Quotient in CIl,C3.Cl
Convert denormals into unnormals

3-478

207865-001

inter

AP-113

441

442
443
444
445

446

mov
fstsw

sp,bp
status

pop
test
jnz

bx
bh,high(mask cond2)
angle_too_big

Allocate stack spce
Quotient identifies octant
original angle fell into
tan(PI*N+x) = tan(x)
Test for complete reduction
Exit if angle was too big

447
See if the angle must be reversed.

448

449
4511
451
452

Assert: -PI/4 < st(II) < PI/4
~ <= st(II) < PI/4
Cl in bx has the sign flag
must be reversed

fabs

453,

454
455

test
jz

bh,high(mask condl)
no tan reverse

456

Angle fell in octants 1,3,5,7.

457
458
459
4611
461
462

fsub
jmp

Reverse it, subtract it from PI/4.
Reverse angle

short do_tangent

Angle is either zero or an unnormal.

463

;

464

tan zero unnormal:

465

466

fstp
jz

467
468

469
4711
471

Remove PI/4

stIll
tan_angIe_zero

Angle is an unnormal.

472
473

474
475
476
477
478

call
jmp

normalize value
tan normar

pop
ret

bp

Restore stack

Angle fell in octants 11,2,4,6.

479

Test for

st(~)

II, fptan won't work.

4811
481

482
483
484
485
486
487
488
489
4911
491

492
493
494
495
496
497
498

no tan reverse:

-

ftst
mov
fstsw
fstp
pop
test
jnz
do tangent:

-

fptan

tan ST(II)

5111

5112
5113
5114

5115
5116
5117
5118
5119
5111

ST( 1) /ST (II)

a fter _tangent:
Decide on the order of the operands and their sign for the divide
operation while the fptan instruction is working.

499

51111

Test for zero angle
Allocate stack space
C3 = 1 if st(II) = II
Remove PI/4
Get ftst status

sp,bp
status
stIll
cx
ch,hiqh(mask cond3)
tan _zero

pop
mov
and
test
jpo

.

bp
Restore stack
al,bh
Get a copy of fprem C3 flag
ax,mask condl + hiqh(mask cond3) ; Examine fprem C3 flag and
; Extract Cl flag
bh,high(mask condl + mask cond3); Use reverse divide i f in
octants 1,2,5,6
reverse_divide
Notel parity works on low
8 bits only!

Angle was in octants 11,3,4,7.
Test for the sign of the result.

Two negatives cancel.

511

512
513

or
jpe

al,ah
positive_divide

3-479

207865-001

514
515
516
517

Force result negative

fchs
positive_divide:

518
Form result
Ok to leave fdiv running

fdiv
ret

519

520
521
522
523

fldl
jmp

524

525
526

Force 1/0

tan(PI/2)

after_tangent

Angle was in octants 1,2,5,6.
Set the correct sign of the result.

527

528
529

530

reverse divide:

531

or
jpe

532
533
534

al,ah
positive_r_divide

fchs

535

Force result negative

536
537

positive_r_divide:

538

Form reciprocal of result
Ok to leave fdiv running

fdivr
ret

539

540
541
542
543
544
545

tangent endp
This funct'on will normalize the value in st(0).
Then PI/4 is placed into stIll.

546

547

normalize value:

548
55e
551

552
553
554
555

556
557
558

559
560
561

Force value positive
o (= st(l!) ( 1
Get normalize bit
Normalize fraction
Restore original value
Form original normalized value
Remove scale factor
Get PI/4

fabs
fxtract
fldl
fadd
stell ,st
fsub
fscale
st (l)
fstp
pi _quarter
fld
fxch
ret

549

code

ends
end

ASSEMBLY COMPLETE, NO ERRORS FOUND

3-480

207865-001

intJ

APPLICATION
NOTE

Ap·143

March 1982

© INTEL CORPORATION, 1982

Order Number

3-481

210383-001

AP-143

• Linear Programming. These calculations require
extensive use of floating point multiplication and
division. One of many applications for linear programming is the determination of optimum production quantities of diverse products when the
quantities of their various constituents are both
overlapping and limited.

INTRODUCTION
As the performance of microcomputers has improved,
the types of functions performed by these microcomputers have grown. One application filled by these
machines has been to perform typical "adding
machine" type calculations, balancing ledgers, etc. This
type of machine has come to be called a "small business
computer." To bea true business computer, however,
the types of operations performed by these machines
need to be expanded beyond simple "balance the
books" types of operations. There are many algorithms
that have been impractical for these small business computers because the number of calculations required by
the algorithms and the performance available from
these machines did not make them feasible. Such operations were available only on large mainframe or minicomputers. With the introduction of the iAPX 86/20, a
microcomputer can finally perform these types of
calculations at a cost level appropriate to small business
co~puters.

The iAPX 86120 features the Intel 8086 with the 8087
numerics co-processor. This combination allows for
high-performance, high-precision numeric calculations.
Many types of operations require this performance to
provide accurate results in a reasonable amount of time.
This increased performance will also be particularly
welcome in the interactive user environment typically
found in small business computers. It is very frustrating
to wait many seconds or even minutes after hitting
"return" for the computer to 'generate results. '
In general, if there are many methods to solving a
" business computer problem, the method requiring the
largest number or calculations will provide the best
results. In many applications, approximate methods
have been used because the speed of the hardware (or
the cost of the computer time) did not allow a more exact method to be used. Because of the high performance
of the iAPX 86120, these numeric intensive methods
, may now be used in small business computer software.
The types of calculations demonstrated in this note are:
• Interest and Annuities. These calculations require
the use of floating point multiplication, division,
exponentiation and logarithms. These calculations
are used to determine the present or future value
of certain types of funds.
• Restocking, These iterative calculations require
extensive use of floating point multiplication and
division. They are used to determine the optimum
restocking times for a given item when the set-up
charges, holding costs and demand for the item
are known or can be estimated.

iAPX 86/20 HARDWARE OVERVIEW
The iAPX 86/20 is a 16-bit microprocessor based on the
Intel 8086 CPU. The 8086 CPU features eight internal
general-purpose 16-bit registers, memory segmentation,
and many other features allowing for efficient code
generation from high-level language compilers. When
augmented with the 8087, it becomes a vehicle for highspeed numerics processing. The 8087 adds eight 80-bit
internal floating point registers, and a floating point
arithmetic logic unit (ALU) which can speed floating
point Qperations up to 100 times over o!her software
floating point simulators or emulators.
The 8086 and 8087 execute a single instruction stream.
The 8087 monitors this stream for numeric instructions.
When a numeric instruction is decoded, the 8086
generates any needed memory addresses for the 8087.
The 8087 then begins instruction execution automatically. No other software interface is required, unlike
other floating point processors currently available
where, for example, the main processor must explicitly
write the floating point numbers and commands into the
floating point unit. The 8086 then continues to execute
non-numeric instructions until another 8087 instruction
is encountered, whereupon it must wait for the 8087 to
complete'the previous numeric instruction. The overlapped 8086 and 8087 processing is known as concurrency; Under ideal conditions, it effectively doubles the
throughput of the processor. However, even when a
steady stream of numeric instructions is being executed
(meaning there is no concurrency), the numeric performance of the 8087 ALU is much greater than that of
the 8086 alone.
The "hardware interface between the 8086 and the 8087 is
equally simple. Hardware handshaking is performed
through two sets of pjps. The RQ/GT pin is used when
the 8087 needs to transfer operands, status, or control
information to or from memory. Because the 8087 can
transfer information to and from memory independent
of the 8086, it must be able to become the "bus
master," that is, the processor with read and write control of all the address, data and status lines. Only one
unit is permitted to have control of these lines at a time;
chaos would exist otherwise, like four people talking at
once with each trying to understand the others.

3-482

210383-001

AP-143

The TEST IBUSY pin is used to manage the concurrency mentioned above. Whenever the 8087 is executing
an instruction, it sets the BUSY pin on high. A single
8086 instruction (the WAIT instruction) tests the state
of this pin. If this pin is high, the WAIT instruction will
cause the 8086 to wait until the pin ~ returned to low.
Therefore, to insure that the 8086 does not attempt to
fetch a 'numeric instruction while the 8087 is still working on a previous numeric instruction, the WAIT instruction needs to be executed. The 8086/87/88
assembler, in addition to a:ll Intel compilers, automatically inserts this WAIT instruction before most
numeric instructions. Software polling can be used to
determine the state of the BUSY pin if hardware handshaking is not desired.

In addition to the 8087 hardware, the 8086 is also supported by Intel compilers for both Pascal and FORTRAN. Code generated by these compilers can easily be
combined with code generated from the other compiler,
from the Intel 8086/87 188 macro assembler or the Intel
PL/M compiler. In addition, these compilers produce'
in line code for the 8087 when numeric operations are
required. By producing in line code rather than calls to
floating point routines, the software overhead of an unnecessary procedure call and return is eliminated. The
combination of both hardware co-processors and software support for the iAPX 86120 provides for greater
performance of both the end product, and its development effort.

Most other lines (address, status, etc.) are connected
directly in parallel between the 8086 and the 8087. An
exception to this is the 8087 interrupt pin which must be
routed to an external interrupt controller. An example
iAPX 86120 system is shown in Figure 1. A more complete discussion of both the handshaking protocol between the 8086 and the 8087 and the internal operation
of the 8087 can be found in the application note Getting
Started With the Numeric Data Processor, AP-l13 by
Bill Rash, or by consulting the numerics section of the
July 1981 iAPX 86,88 Users Manual.

ROUTINES IMPLEMENTED
All routines implemented in this application note were
written entirely in either Pascal 86 or FORTRAN 86. In
addition, a FORTRAN program available from IMSL I
for use in solving linear programs was used. In each

IIMSL, Inc., Sixth Floor-NBC Building, 7500 Bellaire
Boulevard, Houston, Texas, 77036. (713) 722-1927.

-,

r

I
I
I
I
L -- J
INT

-

8259A
PIC

r-

IRn

INTR

jLJ

808618088
CPU

ClK

RaJGT1
OSO OS1

\r
~

TEST

t t t

OSO

!"II'

BUSY

L.., RaJGTO

8284A
CLOCK
GENERATOR
ClK

OS1

;t-

8087

ClK

I

I
L

K
.A

'\j

SYSTEM BUS

V

II)

:::>

'y- ...OJ
.
SOURCE TEXT: :F6:SMCT.PAS
(* This is going to try to find the optimal replacement cost
* for a rather variable demand product over 20 months, when
* the demand is known, an example could be a video game, using
* a single chip ROM programmed microcomputer with an initial set
* up charge of $3000.00, demand varies a lot with peak in october
* and november(for Christmas), droops in may(vacations), etc.
* The cost per part varies from $20.00 per part up to 500,
* $17.50 per part from 500 to 5000, and $15.00 above 5,000.
* The Sliver-Meal heuristic is going to be used.
*)
module silver meal;
public timers;
function rtimer:integer;
procedure stimer;
program silver meal(input,output);
const
months
20;
monthspl
21;
setupcost = 3000.0;
holdcost
0.4;
real large
1.0e10;
rea1l"argei = 32000;
var
,rep1:
(* first time stock goes to 0 for a given month *)
array[l •• months] of integer;
tomake,
(* the number of boxes to make in a month *)
require:
(* number of boxes required in a given month *)
array[1 •• monthsp1] of real;
, trcut,
ho1dcostv:
(* holding costs *)
array[l •• months] of real;
cost,
(* calculated cost in a given situation *)
cost1,
(* production cost *)
cost2,
(* holding cost *)
tota1cost,
(* the total cost of it all *)
1astcost,
(* used in determining the total cost *)
tota1ho1dcost:
(* the total hold cost *)
real;
i, j,k:
(* counters *)
integer;
totcnt,
(* accumulated number of boxes in a batch *)
ho1dcnt:
(* number of boxed holding *)
real;
(* the 10 ms count *)
count:
integer;

=

=
=
=

begin
require[l]
require[2]
require[3]
require[4]

/

500;
1500;
2500;
:= 2000;

:=
:=
:=

3-497

210~3-001

AP·143

SOURCE. TEXT: :F6:SMCT.PAS
require[5] := 2000;
require[6] := 1000;
require[7] := 3500;
require[8] := 2500;
require[9] := 5000;
require[lO] := 7500;
require[ll] := 9500;
require[12] := 10000;
require[13] := 500;
require[14] := 1500;
require[15] := 2500;
require[16] := 2000;
require[17] := 2000;
require[18] := 1000;
requiref19] := 3500;
require[20] := 2500; (* stop here, because the next m~nth is much
higher can assume will restock then *)
require[monthspl] := reallargei;

(* start the timer *)

stimer;
i := 1;
while i <= months do begin
trcut[i] := reallarge;
totcnt := 0;

(* i is the month working on *)

j := i;
while j <= monthspl do begin
totcnt := totcnt + require[j];
if totcnt < 500 then costl := 20.0 * totcnt
else if totcnt < 5000 then costl := 17.5 * totcnt
else costl := 15.0 * totcnt;
cost2' := 0.0;
holdcnt := totcnt;
for k := i to j - 1 do begin
holdcnt := holdcnt - require[k];
cost2 := cost2 + holdcnt * holdcost;
end;
cost := (setupcost + cost2 + costl)/(j - i + 1);
if cost < trcut[i] then begin
trcut[i] := cost;
tomake[i] := totcnt;
holdcostv[i] := cost2;
end
else begin
repl Ci] : = j;
i

:= j;

j := monthspl;
end;
j

:= j

+ 1;

end;

end;
count := rtimer:
j := 1;

3-498

210383·001

AP·143

SERIES-III Pascal-86, Vl.l

SOURCE TEXT: :F6:SMCT.PAS
writeln('month restock# optimal cost per period');
totalcost := 0;
for i := 1 to months do begin
if i = j then begin
write( i: 5, '
, ,tomake[i] :6, '
, ,trcut[i]: 10: 2) :
writeln(' * restocking now');
j : = repl [ j ] ;
lastcost := trcut[i];
totalcost := totalcost + lastcost;
end
else begin
totalcost := total cost + lastcost;
writeln(i:5);
end;
end~

i
j

:= I;

:= 0;

totalholdcost := 0.0;
while i <= months do begin
totalholdcost := totalholdcost + holdcostv[i];
j:=j+l;
i := repl[i];
end;
writeln('the total hold cost is' ,totalholdcost:12:2);
writeln('stock gets replenished' ,j:4,' times');
writeln('replenishment cost is' ,j*setupcost:12:2);
writeln('the total cost thingy is' ,totalcost);
writeln('the 10 ms count is ',count);
end.

Summary Information:
PROCEDURE
SILVER MEAL

OFFSET
0108H

Total

CODE SIZE
05F7H 1527D

DATA SIZE
01ACH
428D

STACK SIZE
OOOEH
14D

06FFH

01ACH

0042H

1791D

428D

66D

135 Lines Read.
o Errors Detected.
41% Utilization of Memory.

3-499

210383-001

AP·143

SERIES-III Pascal-86, Vl.l

Source file: :F6:WAGCT.PAS
Object File: :F6:WAGCT.OBJ
Controls Specified: .
SOURCE TEXT: :F6:WAGCT.PAS
(* This is going to try to find the optimal replacement cost
* for a rather'variable demand product over 20 months, when
* the demand is known, an example could be a video game, using
* a single chip ROM programmed microcomputer with an initial set
* up charge of $3000.00, demand varies a lot with peak in october
* and november(for Christmas), droops in may(vacations), etc.
* The cost per part varies from $20.00 per part up to 500,
" * $17.50 per part from 500 to 5000, and $15.00 above 5,000.

*)
module wag withl
public timersl
function rtimer:integerl
procedure stimerl
program wag with(input,output)1
const
months = 201
monthspl = 211
(* mask set up charge *)
setupcost = 3000.001
(* cost 'per part of maintaining inventory *)
holdcost = 0.41
reallarge
1.Oe91
var
require,
(* number of chips requir~d in a given month *)
tomake:
(* the number of chips to make in a month *)
array[l .• months] of reall
repl:
(* first time stock goes to 0 for a given month *)
array[l .. months] of integer 1
optwz:
(* optimum cost for a given month with zero stock
to start with *)
array[l .. monthspl] of reall
holdcostv:
(* holding costs *)
array[l .. months] of reall
cost,
(* calculated cost in a given situation *)
costl,
(* production cost *)
cost2,
(* holding cost *)
totalcost,
(* the total cost of it all *)
totalholdcost:
(* the total hold cost *)
real:
(* counters *)
i ( I j ,k:
integer:
(* accumulated number'of chips in a batch *)
totcnt,
(* number of boxed holding *)
holdcnt:
reall
(* 10 ms count *)
count:
integer 1
begin
optwz[monthspl] := 01
requ~re[l] := 5001
require[2] := 15001
require[3] := 25001
require[4] := 20001

3-500

210383·001

AP-143

SERIES-III Pascal-86, Vl.l

SOURCE TEXT: :F6:WAGCT.PAS
require[5] := 2000:
require[6] := 1000:
require[7] := 3500:
require[8] := 2500:
require[9] := 5000:
require[lO] := 7500:
require[ll] := 9500:
require[12] := 10000:
require[13] := 500:
require[14] := 1500:
require[15] := 2500:
require[16] := 2000:
require[17] := 2000:
require[18] := 1000:
require[19] := 3500:
require[20] := 2500:

(* stop here, because the next month is much
higher can assume will restock then *)

stimer~

for i := months downto 1 do begin
(* i is the month working on *)
optwz[i] := reallarge:
totcnt := 0:
for j := i to months do begin
(*
is the option working on *)
totcnt := totcnt + require[j]:
costl := setupcost+optwz[j+l]:
if totcnt <= 500 then costl := cost 1 + 20.0*totcnt
else if totcnt <= 5000 then costl := cost1 + 17.5*totcnt
else cost1 := cost1 + 15.0*totcnt:
cost2 := 0.0:
ho1dcnt := totcnt:
for k := i to j - 1 do begin
holdcnt := ho1dcnt - require[k]:
cost2 := cost2 + ho1dcnt * holdcost:
end:
cost := cost1 + cost2:
if cost < optwz[i] then begin
optwz[i] := cost:
repl[i] := j + 1:
tomake[i] := totcnt:
ho1dcostv[i] := cost2:
end:
end:
end:

count := rtimer:
j

:= 1:

writeln('month restock# optimal cost'):
for i := 1 to months do begin
write(i: 5, '
, ,tomake[i]:6, '
, ,optwz[i] :10: 2):
if i = j then begin
writeln(' * restocking now'):
j : = repl[ j] :
end
else write1n:
end:

3-501

210383-001

AP·143

SERIES-III Pascal-86, Vl.l

SOURCE TEXT: :F6:WAGCT.PAS
i
j

:= l;
:= 0;

totalholdcost := 0.0;
while i <= months do begin
totalholdcost := totalholdcost + holdcostv[i];
j

:= j

+ 1;

i := repl[i];
end;
writeln('the total hold cost is',totalholdcost:l2:2);
writeln('stock gets replenished',j:4,' times');
writeln('replenishment cost is' ,j*setupcost:l2:2);
writeln('the 10 ms count is ',count);

end.

Summary Information:
PROCEDURE
WAG WITH

OFFSET
00E5H

Total

CODE SIZE
0576H l398D

DATA SIZE
OlASH
424D

STACK SIZE
OOOEH
l4D

065BH

01A8H

0042H

1627D

424D

66D

119 Lines Read.
o Errors Detected.
41% Utilization of Memory.

3-502

210383·001

AP·143

FORTRAN-86 COMPILER
:Fl:COOKIE.FOR
SERIES-III FORTRAN-B6 COMPILER X023
COMPILER INVOKED BY: FORT86.86
:Fl:COOKIE.FOR

1

2
3

c
c this routine will solve a linear problem using the IMSL fortran
c
library.
the IMSL routine used is "zx3lp" which solves the problem
c
using the revised simplex method.
c
integer ia,n,ml,m2,iw(37),ier
real*8 a(13,4),b(13),c(4),rw(206),psol(11),dsol(13),s
integer*4 rtimer,count

4

*
*

data a/2.,1.,1.,0.,2.25,1.,0.,12.,0., .15,.25,0.,0.,
2. ,1. ,1. ,
,2. 25, 1 • ,
12 . , .5, . 15, .45,
0. ,

°.

*

5
6

°.,

4. ,2. ,0. ,4. ,1.25,0. ,1. ,0., .65, .5, .45,0. ,0./
data b/lOOO. ,600. ,200.,700. ,600. ,150. ,150. ,1500. ,125. ,560.,750. ,0. ,0./
data c/.85,.95,1.10,1.25/

c
c
c
c
c

n is the number of variables
ml is the number of inequality constraints
m2 is the number of equality constraints
ia is the declared number of columns of a

c
7
8
9

ml
m2
n

= 11
=0
=4

10

ia = 13

11

print *, 'the input tableau:'
do 100 i=1,ia-2
write(6,BOO)a(i,1) ,a(i,2) ,a(i,3) ,a(i,4) ,b(i)
format(4flO.4,' <= ',flO.4)
continue

12
13
14
15

°.,

4.,2.,0.,4.,~.25,0.,1.,0.,0.,.5,.25,0.,0.,

BOO
100

16
17
IB

call stimer
call zx3lp(a,ia,b,c,n,ml,m2,s,psol,dsol,rw,iw,ier)
count = rtimer()

19
20
21
22
23
24
25
26
27
28
29
30
31

print *,'ier = f,ier
print *, 'the final value of the objective function(profit!) is:' ,s
print *,'batches of chocolate chip w/o walnuts: ',psol(l)
print *,'batches of chocolate chip with walnuts:' ,psol(2)
print *,'batches of brownies without walnuts:' ,psol(3)
print *, 'batches of brownies with walnuts: ',psol(4)
print *, 'the dual solutions follow:'
do 200 i=1,ia-2
print *,1 var ' ,i, I = ',dsol(i)
continue
print *,'the calculation time here (in seconds .•. ) is: ',count/lOO.
stop
end

200

3-503

APPLICATION
NOTE

Ap·144
~I

October 1983

@

INTEL CORPORATION, 1982

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Order Number

210384-001

AP-144

INTRODUCTION
As the performance of microcomputers has improved,
these machines have been used in many applications.
With the introduction of 16-bit microprocessors (along
with the associated CPU enhancements, especially the
integer multiply instruction) the operations required to
manipulate graphic representations of threedimensional objects were made easier. Only integer
values could be used to define figures, however, because
only integer multiplies were supported in hardware.
While software floating point routines existed, the speed
at which a general purpose microprocessor could execute even the simplest floating point operation precluded the use of these routines because of the number of
floating point operations which must be performed to
manipulate all but the simplest of objects.
The lack of high performance floating point math or the
restriction of using only integer representations severely
limits the types and sizes of objects that can be defined.
Imagine limiting everything in the universe to be less
than 32,000 millimeters long, high, or wide! This limitation could severely impact any system that is used to
model real world objects. An example of such an application is a Computer Aided Design (CAD) system. If
real or floating point numbers are used, however, practically any object can be defined (after all, there are only
9,397,728,000,000,000,000 millimeters in a light year(!),
well within the range of floating point numbers). Witb
the introduction of the iAPX 86120, the performance
required to execute the requisite operations on floating
point representations of three-dimensional figures has
finally been achieved in a microprocessor solution, at a
microprocessor price.
The iAPX 86/20 features the Intel 8086 with the 8087
numerics co-processor. This combination allows for
high performance, high precision numeric operations.
This performance is especially important in the graphics
routines implemented in this note because of the large
number of floating point operations performed for each
line drawn. In addition, the precision is required to
maintain the image quality of the represented figures.
This application note shows the fundamental components of a three-dimensional graphics package. As
stated before, if the objects are to be described in real
size, floating point values must be used. Since the operations performed require many multiplies and divides, a
high performance floating point arithmetic unit is a
must. Note that the operations to be performed by this
software are not those of a "bit map" controller: single
chip devices performing this specialized task are or will
soon be available. Because they are special-purpose
devices, they can also execute this task quickly,
offloading the task from the general purpose
3-505

microprocessor allowing the processor to perform other
work in parallel. In addition, since the size of the
memory used in a bit-mapped controller is constrained
(one could hardly have unlimited memory for the
refresh map), only integer math is required. This
graphics package is a much higher level type of routine,
where the inputs are three-dimensional line drawing
commands (which could be fed into a bit map controller).
The three-dimensional graphics package implemented
in this note allows for the entry of three-dimensional
figures, the manipulation of these figures, the setting of
the viewer's location, the size of the picture to be seen,
and the position of the picture on the graphics output
device. Along the way, it performs perspective transformations, window clipping and projection. All figures
are defined using floating point numbers. Thus, any
figure may be defined "real size" without pre-scaling.
This means that the size of the figure defined within the
package may be the actual size of the object, i.e. the size
of the object is not arbitrarily limited by the machine,
whether the object be a sub-nuclear particle, or a
cellestial body.

iAPX 86/20 HARDWARE OVERVIEW
The iAPX 86120 is a 16-bit microprocessor based on the
Intel 8086 CPU. The 8086 CPU features eight internal
general purpose 16-bit registers, memory segmentation,
and many other features allowing for compact, efficient
code generation from high-level language compilers.
When augmented with the 8087, it becomes a vehicle for
high-speed numerics processing. The 8087 adds eight
80-bit internal floating point registers, and a floating
point arithmetic logic unit (ALU) which can speed
floating point operations by up to'100 times over other
software floating point simulators or emulators.
The 8086 and 8087 execute a single instruction stream.
The 8087 monitors this stream for numeric instructions.
When a numeric instruction is decoded, the 8086
generates any needed memory addresses for the 8087.
The 8087 then begins instruction execution automatically. No other software interface is required, unlike other
floating point processors currently available where, for
example, the main processor must explicitly write the
floating point numbers and commands into the floating
point unit. The 8086 then continues to execute nonnumeric instructions until another 8087 instruction is
encountered, whereupon it must wait for the 8087 to
complete the previous numeric instruction. The parallel
8086 and 8087 processing is known as concurrency.
Under ideal conditions, it effectively doubles the
throughput of the processor. However, even when a
steady stream of numeric insructions is being executed
(meaning there is no concurrency), the numeric perforAFN-02185A

Ap·144

is not desired.

mance of the 8087 ALU is much greater than that of the.
8086 alone.

Most other lines (address, status, etc.) are conn~ed
directly in parallel between the 8086 and the 8087. An
exception to this is the 8087 interrupt pin. This signal
must be routed to an external interrupt controller. An
example iAPX 86120 system is shown in Figure 1. A
more complete discussion of both the handshaking protocol between the 8086 and the 8087 and the internal
operation of the .8087 can be found in the application
note Getting Started With the Numeric Data Processor,
Ap Note #113 by Bill Rash, or by consulting the
numerics section of the July 1981 iAPX 86, 88 Users
Manual.

The hardware interface between the 8086 and the 8087 is
equally simple. Hardware handshaking is performed
through two sets of pins. The RQ/GT pin is used when
the 8087 needs to transfer operands, status, or control
information to or from memory. Because the 8087 can
access memory independently of the 8086, it must be
able to become the "bus master," that is, the processor
with read and write control of all the address, data and
status lines.
The TEST I BUSY pin is used to manage the concurrency mentioned above. Whenever the 8087 is executing an
instruction, it sets the BUSY pin high. A single 8086 instruction (the WAIT instru~tion) tests the state of this
pin. If this pin is high, the WAIT instruction will cause
the 8086 to wait until the pin is returned low. Therefore,
to Insure that the 8086 does not attempt to fetch a
numeric instruction while the 8087 is still working on a
previous numeric instruction, the WAIT instruction
needs to precede most numeric instructions (the only
class of instructions which do not need to be prece<,led
by a WAIT instruction are those which access the control registers of the 8087). The 8086/87/88 assembler,
in addition to all INTEL compilers, automatically inserts this WAIT instruction before most numeric instructions. Software polling can be used to determine
the state of the BUSY pin if the hardware handshaking

INT

I

.

PIC

INTR

-

8259A

I

~n_J

8284A

ROIGT1
QSO QS1

'--

.;U

8086/8088
• CPU

ClK

r-

CLOCK
OENERATOR
ClK

The combination of both hardware co-processors and
software support for the iAPX 86/20 provid.es for
greater performance of the end product, and a quicker,
easier development effort.

-,

r

I
I
L

In addition to the 8087 hardware, the 8086 is also supported by Intel compilers for both Pascal and FORTRAN. Code generated by these compilers can easily be
combined with code generated from the other compiler,
from t!J.e Intel 8086/87/88 macro assembler, or the Intel PLiM compiler. In addition, these compilers produce in-line code for the 8087 when numeric operations
are required. By producing in-line code rather than calls
to floating point routines, the software overhead of an
unnecessary procedure call and return is eliminated.

\r-

TeST

~

t

t

t

QSO

QS1

BUSY

ROIGTO

k= ..

8087

ClK

T

A

\

SYSTEM BUS

"
V

I

:::I
01

...

NOP

~

9

INT
ROIOT1

I
I
I

r
I.

I
L

IV'

8086
FAMilY
BUS
INTERFACE
COMPONENTS

-

-1RQ/GT

lOP

I
I.-

-

I

I

.
,1_

8089

~ClK

I

.

-

~'r-I
....l

Figure 1. Example 86/20 System

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AP-144

Scaling is the mUltiplication of all coordinates of
the points defining a figure by a constant number
such that the object becomes larger or smaller. Example scales are shown in Figures 9-11. This scaling need not be uniformly performed for all
dimensions of an object. If, for example, the Z
coordinates of a cube are all scaled to be twice as
large as they originally were, the image shown in
Figure 9 would be produced. Notice here that the
X and Y coordinates have not been altered; only
the Z coordinates are twice as large as they
originally were, or alternatively, the front and
back of the cube are closer and farther away from
the viewer than in the original, unaltered cube.
Figure 10 shows this same operation being performed on the X coordinates, while Figure 11
shows this operation being performed on Y coordinates.

THREE·DIMENSIONAL GRAPHICS
FUNDAMENTALS
The charter in life of a three-dimensional graphics
package is to take a three-dimensional rendering of an
object and to transform it such that it can be accurately
represented on the two-dimensional surface of a
graphics output device. To fulfill these requirements,
the graphics package 'must:
• AUow for the entry of three-dimensional data.
Since all figures inside the package are represented
as a series of points in three-dimensional space,
there must be a way of entering these figures into
the computer.
• Perform the current transformation. This
transformation rotates, translates and scales the
three-dimensional object throughout threedimensional space. Example rotates, translates
and scales are shown in Figures 2-11. In all
diagrams, the first coordinate indicated is X, the
second Y, the third Z. The viewpoint is the location of the viewer in three-dimensional space in
relationship to an arbitrarily chosen but consistent
origin.
Translations are movements of the object in threedimensional space. Example translations are
shown in Figures 3-5. Figure 3 shows a translation
of two units in the pius Z direction. Since the viewpoint is ten units up along the Z axis, this moves
the cube one-fifth the distance toward the viewer,
or in other words, the cube seems to get larger.
Figure 4 shows the same cube translated two units
in the plus X direction. Since the cube is four units
on a side, this moves the cube such that the viewer
is looking straight down one side of the cube. The
viewer is also looking straight down a side in
Figure 5.

Figure 2. 2 x 2 x 2 Cube Centered at (0,0,0)
Viewed from (0,0,10)

Rotations are movements of the object in threedimensional space about the three-coordinate
axis: X, Y, and Z. The rotation of the object must
specify both the magnitude of the rotation, and
the axis about which the rotation must take place.
Example rotates are shown in Figures 6-8. Figure
6 shows the cube rotated 45 degrees about the Z
axis. Since the viewpoint is straight up the Z axis,
the cube is seen to keep its same face towards the
viewer. Figure 7 shows the cube rotated 45 degrees
about the X axis. Here, the cube no longer shows
the same face it has previously. The face previously turned directly toward the viewer has been
rotated such that the edge between this face and
another face is immediately before the viewer. The
same is also shown in the rotation about the Y axis
in Figure 8.

Figure 3. Same Cube and Viewpoint,
Translation
3-507

+2 Z
210384-001

AP-144

Figure 5. Same Cube, Viewpoint, + 2 Y Translate

Figure 4. Same Cube, Viewpoint, + 2 X Trenslate

B
Figure 8. Same Cube, Viewpoint, 45 Degree
Rotation About Z

Figure 7. Same Cube, Viewpoint, 45 Degree
Rotation About X
.

3-508

210384-001

AP·144

Figure 8. Same Cube, Viewpoint, 45 degree
Rotation About Y

"

./

....-

.......

Figure 9. Same Cube, Viewpont 2 x Scale of Z

Figure 10. Same Cube, Viewpoint, 2 x Scale of X

r\

/

1I

"

Figure 11. Same Cube, Viewpoint, 2 x Scale of Y

3.509

210384-001

Ap·144

'\

/

V

'"

Figure 12. 2 x 2 x 2 Cube Centered at (0,0,0) Viewed from (0,0,10) Then from (10,10,0)

• Perform the viewing transformation. This
transformation moves and rotates the three
dimensional figure according to the viewer's location and orientation (the direction the viewer is
facing) in space. An example of changing the view
location is shown in Figure 12. Again, this location, or viewpoint, is the viewer's location with
relation to an arbitrarily chosen origin.
•

Perform Z-clipping on the three-dimensional
data. This insures that only data in front of the
viewer are displayed. In addition, it allows that
objects beyond a certain distance from the viewer
will not be displayed.

•

Project the three-dimensional data onto a two
dimensional surface. The objects must be projected onto a two-dimensional surface according
to the laws of perspective. By changing the
"vanishing point," interesting effects are also
possible. An example of this is shown in Figure 13.
Here, the first figure shows exaggerated perspective (that is, the difference in perceived size between the front face and the back face of the cube
is exaggerated), where the second figure shows the
object with subdued perspective (the difference in
the perceived sizes of the front and back faces is
much less than in the first figure). Exaggerated
perspective is generated for objects close to the
viewer, while subdued perspective is generated for
objects distant from the viewer. Note that the
same figure, with the same dimensions, is shown
in both figures; only the perspective values have
been changed.

•

Perform X-Y clipping on the projected data. This
cuts off lines in the projected data extending
beyond the specified "window."

•

Perform the window to viewport transformation.
This takes the two-dimensional projected values
and scales them according to the relative sizes of
. the "window" and th~ "viewport." .

The "window" describes the size of the viewer's portal
into the data, whereas the "viewport" describes the size
and position of this portal on the graphics output
device. Whereas the window's size is determined by the
size of the input data, the viewport size is determined by
the physical characteristics of the graphics display
device. For example, the viewport coordinates of a certain CRT display may be constrained to be between O'
and 1023 in both the X and Y dimensions, whereas the
window limits are determined only by the maximum size
of numbers the computer can store. Thus, for maximum
generality and utility, floating point numbers must be
used to represent the three-dimensional figures.
A good reference to the techniques used in this threedimensional graphics implementation can be found in
Newman and Sproull i •

William M. and Robert F. Sproull, Principles of
Interactive Computer Graphics, McGraw-Hill Book Company, New York, 1979.

i Newman,

3-510

210384-001

Ap-144

Figure 13. Example Cube Shown with Exaggerated Perspective, then with Subdued Perspective
quirements is a Computer Aided Design (CAD) system.
However, since these graphics systems often exist in an)
interactive environment, picture processing delays
greater than a few seconds for simple figures, or greater
than a few minutes for very complex figures cannot be
tolerated. Because of these processing requirements, a
mini-computer with a hardware floating point unit has
been required to drive these graphics systems. However,
with the introduction of the 8087, the floating point
processing performance required by these systems can
finally be met in a microcomputer solution.

IMPLEMENTATION
Three·dimensional graphics systems can be split into
three functional modules: the input hardware, the pro·
cessing hardware, and the output hardware. The
graphics software is executed by the processing hard·
ware and is used to receive figure definitions from the
input hardware, store them in one form or another, and
maniplJlate them such that they can be displayed on the
output' hardware.
Input hardware can range from the common typewriter
keyboard to sophisticated three· dimensional input
devices. Output hardware can range from a plotter to a
storage tube terminal to a bit-mapped raster scan
display or a vector drawing CRT.

The microcomputer system used in this threedimensional graphics application is a general purpose
microcomputer embodied in the iAPX 86/12 board
found in an Intel Intellec4l' Series III development
system. All routines 'implemented in this application
note were written entirely in FORTRAN using the Intel
FORTRAN 86 compiler. Any iAPX 86/20 (or iAPX
88120) with enough memory can be used to execute the
programs, however. The amount of memory required
depends on the number and complexity of the figures to
be displayed., The source code for all routines used in
this note are given in the appendix.

The processing hardware can range from general purpose minicomputers to very fast, specialized graphics
processing hardware. General purpose computers are
used because they allow applications programs to be
written in higher level languages. Specialized hardware
is sometimes employed when very fast manipulations
are required, such as in t~e real time graphics applications found in flight simulators. This specialized hardware can be used to perform whole matrix transformations. Many applications do not require figures to be
drawn real time (on the order of one complete picture
every 1130 sec), however, and can be satisfied by the
performancetof the general purpose computer alone. A
typical application which is satisfied by these latter re-

3-511

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AP-144

337
muilimodule

86112 board

Figure 14. Computer System Used in This Graphics Implementation
The graphics output device used was a HP 7225A flat
bed plotter. Communications were performed using the
RS232 serial link on the 86/12 board. The communications speed of the line to the plotter was 600 baud.
Because of the number of lines drawn in the more com. plex figures, the physical characteristics of the plotter,
and the communications line speed,' the amount of time
required to draw a large picture was a function of the
plotter speed, not the execution speed of the iAPX
86/20. As a result, all times quoted in this note do not
reflect the plotting time. Only the time up to placing the
ASCII character into the buffer of a serial communications chip is included for all machines quoted. Higher
speed graphics display devices (which are not limited by
the physical characteristics of plotters) can use the speed
of the iAPX 86120 to full advantage.
The graphics input device used was the standard
alphanumeric keyboard attached to the development
system. This allows entry of figures, as well as control
of the graphics system. Input can also be fetched from
disk storage, however, to allow for greater speed in
defining large figures. A block diagram of the hardware
system used in this implementation is shown in Figure
14.
All routines were run using both the 8087 and the 8087
software emu)ator. The 8087 software emulator is a
software package exactly emulating the internal operation of the 8087 using 8086 instructions. When the
emulator is used, an 8087 is not required. The emulator
is a software product available from Intel as part of the
8087 support library. The performance of the 8087
hardware is much better than that of the software
emulator, as one would expect from a specialized hardware floating point unit.
The 8087 supports various data formats. For real
numbers, these formats are short real (or single precision), long real (or double precision), and temporary
real (or extended precision). The differences among the

three are in the number of bits allocated to represent a
given floating point number.
In all real numbers, the data is split into three fields: the
sign bit, the exponent field and the mantissa field. The
sign bit shows whether the number is positive or
negative. The exponent and mantissa together provide
the value of the number: the exponent providing the
power of two of the number, and the mantissa providing the "normalized" value of the number.
A "no;f1llalized" number is one that always lies within a
certain range. By dividing a number by a certain power
of two, most numbers can be made to lie between the
numbers 1 and 2. The power of two by which the
number must be divided to fit within this range is the exponent of the number, and the result Of this division is
the mantissa. This type of operation will not work on all
numbers (for example, no matter what one divides zero
by, the result is always zero), so the nUlJlber system must
'
allow for these certain "special cases."
As the size of the exponent grows, the range of numbers
representable also grows, that is, larger and .smaller
numbers may be represented. As the size of the mantissa
grows, the resolution of the points within this range
grows. This means the distance between any two adjacent numbers decreases,.or, to put it another way, finer
detail may be represented. Short real numbers provide 8
exponent bits and 23 significand or mantissa bits. Long
real numbers provide 11 exponent bits and 52 significand bits. Temporary real numbers provide 15 exponent
bits and 64 significand bits. These data formats are
shown in Figure 15. Thus, of the three 'data formats implemented, short real provides the least amount of
precision, while temporary real provides the. greatest
amount of precision. These levels of precision represent
only the external mode of storage for the numbers; inside the 8087 all numbers are represented to temporary
real precision. Numbers are automatically converted into the temporary real precision when they are loaded in3-512

210384-001

AP-144

SIGNIFICAND

LONG REAL

II
S

"

BIASED
EXPONENT

83

TEMPORARY REAL

I
52\:

BI,ASED
EXPONENT

lSi

SIGNIFICAND

"

fil

SIGNIFICAND

84 83 1

79
NOTES:

~I _=INTEGER
=:m.~;I=:~Ji'~:R:~~J~
BIT OF SlONIF1CAND; STORED IN TEMPORARY REAL,
IMPLICIT IN SHORT AND LONG REAL

EXPONENT BIAS (NORMALIZED VALUES)
SHORT REAL" 127 (7FH)

LONG REAL 1023 (3FFH)

TEMPORARY REAL: 16383 (3FFFH)

Figure 15. Floating Point Data Fonnats

Three-Dimensional Figure Description
and User Interface

to the 8087. In addition to real format numbers, the
8087 automatically converts to and from external
variables stored as 16, 32 or 64-bit integers, or 80-bit
binary coded decimal (BCD) numbers.

The graphics user interface implemented in this note is
both functional and simple. It does not require the use
of specialized three-dimensional input hardware. All input data is keyed in through the keyboard.

Memory requirements also increase as precision increases. Whereas a short real number requires only four
bytes of storage (32 bits), a long real number requires
eight bytes (64 bits) and a temporary real number ten
bytes (80 bits). In many floating point processors, processing time also increases dramatically as precision is
increased, making this another consideration in the
choice of precision to be used by a routine. The differences in 8087 processing time among_short real, long
real and temporary real numbers are insignificant compared to the processing time, however, since all operations are performed to the internal 80-bit precision. This
makes the choice of which precision to use in an iAPX
86/20 system a function only of memory limitations
and precision requirements.

The package allows for definition of figures for future
use within the' graphics package. This feature could be
useful in generating multiple views of a certain object. It
requires that the object be "defined" at the beginning
of the session, but then allows the user to view the object from any location, with any rotation, scale, or
translation.
Commands to the graphics package consist of a set of
alphanumeric commands followed by the necessary
numeric constants. To enter commands to the graphics
package, one enters an alphanumeric command enclosed within the single quotes followed by the appropriate numeric arguments. The maximum number of
arguments required by any command is six. If less than
six arguments are entered -on a line, the line must be terminated by the 'I' character, however. These requirements (having the command enclosed within single
quotes, explicitly terminating the line) are a result of using the list-directed input format of FORTRAN.

Double precision numbers were chosen for this graphics
implementation because they allow a very wide range of
numbers to be represented with high precision. This is
important, since the package allows the user to magnify
small parts of defined figures. Without the precision
gained by using double precision numbers, the image of
the object could easily be distorted under such scrutiny.

3-513

AFN-02185A

AP-144

The commands recognized by the graphics processor
are:

pop. This command causes the matrix stack to be
popped into the current matrix.

comment argl. This command instructs the
graphics processor to ignore the next argl lines.
This can be used to insert comments within the
graphics commands.

rotate argl arg2 arg3. This command causes the
viewer's perception of the three-dimensional
figure to be rotated around the X, Y, and Z axjs
byargl, arg2 and arg3. The angles are in degrees.
The definition of an obiect is not altered.

define argl. This command instructs the graphics
processor that the next N lines (up to the enddef
command) are to be entered into an internal buffer for future reference as figure argl. The
graphics commands are not interpreted, i.e. they
do not cause figures to be drawn as they are
)entered. In this way, three-dimensional objects
may be defined, or to put it another way, placed
into an internal display list. Up to ten objects may
be defined using the current version of the program. This may be increased to the limits of
available memory. Currently there is in:ternal
storage space for up to SOO total graphics commands. These may be spread in any combination
among the ten figures. This number may also be
modified to reflect memory restrictions.

translate argl arg2 arg3. This command causes the
viewer's perception of the three-dimensional
figure to be translated in the X, Y, and Z directions by argl, arg2 and arg3. Again, the definition
of an object is not altered.
scale argl arg2 arg3. This command causes the
viewer's perception -of the three-dimensional
figure to be scaled in the X, Y and Z directions by
argl, arg2, and arg3.
window argl arg2. This command sets up the window parameters. These parameters determine the
visible side to side portion of the projected images.
This amounts to placing an infinitely tall pyramid
within three-dimensional space with the viewing
location located at its aPex (looking down). All
objects within this pyramid will be visible; all objects outside this pyramid will nqt be visible.

enddef. This command terminates a figure definition, and returns control back to the main
graphics processor.

viewport argl arg2 arg3 arg4. This command sets
up the viewport parameters. These parameters
determine the size and location of the above window on the plotter surface. The center of the area
on the plotter surface is giv~n by argl, arg2 with
the X and Yhalf sizes given by arg3, arg4. The
plotter is assumed to have an X dimension between 0 and 12, and a Y dimension between 0 and
10. The translation to the dimensions the plotter
recognizes is done in a lower level plotter interface
routine. By performing this task in a lower level of
software, the package is maae more general.

call argl. This command causes the graphics processor to fetch graphics commands from the internal buffer of the previously defined figure number
argl.

line argl arg2 arg3 arg4 arg5 arg6. This command
causes a line to be drawn in three-dimensional
space from the point argl, arg2, arg3 to the point
arg4, arg5, arg6. The current object rotation, object scale, object translation, viewer location, window, and viewport are used.
plot argl arg2 arg3 arg4. This command causes a
line to be drawn from the endpoint of the last line
plotted to the point argl, arg2, arg3 using the
"pencode" arg4. The current pen codes supported
are '2' (indicating that a solid line is to be drawn),
and '3' (indicating that no line i,s to be drawn; this
is used only to change the location of the plot
head). Additional pencodes could be implemented
allowing for dashed lines, dotted lines, etc.

viewpoint argl arg2 arg3 arg4 arg5 arg6. This
command sets up the "viewing" transformation.
argl, arg2, arg3 represent the location of the
viewer in three-dimensional space, while arg4,
arg5, arg6 represent the "Iookat" location in
three-dimensional space. Together they form a
vector pointing to the area to be viewed whose
length determines the perspective variables (only
single point perspective is currently implemented).

ident. This command causes the "current" matrix
to be set to the identify matrix. This causes all
rotates to be set to zero, all translates to be set to
the origin, and all scales to be set to one.
push. This command causes the current matrix to
be pushed onto a 10 location matrix stack. The
current matrix is not altered.

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zclip argJ arg2. This command sets up the
"Z·clipping" parameters. These determine the
visible distance in front of the viewer. ArgJ
specifies the near boundary of the viewing area
while arg2 specifies the far boundary of the area.
Together with the window command, it defines a
solid delimiting the visible objects from the not·
visible objects.

THE CURRENT TRANSFORMATION
If each object were to be modified whenever a translate,

rotate, or scale were to be performed, performance of
the package could be quite slow. In addition, the
original definition of the figure would be lost (although
not irreversibly). If there were a method of performing
these three operations at a single time, allowing the
original definition of an object to remain unaltered,
both the performance and ease of use of the graphics
package would be enhanced.

cube argJ arg2 arg3 arg4 arg5 arg6. This com·
mand draws a cube centered at argJ, arg2, arg3
with half·widths of arg4, arg5 and arg6.

One way in which these operations can be combined is
by u$ing what is called the "current" matrix. The cur·
rent matrix is a 4 by 4 double precision real matrix. It
numerically represents any combination of rotates,
translates and scales in any order. The matrix is
multiplied by each 1 by 4 point definition vector on its
way to being plotted. The result of this multiplication is
a point that has been rotated, scaled, and translated the
proper amount. If this matrix is the identity matrix, the
point will pass through unaltered. Thus, the identity
matrix represents no scaling, translating, and rotating.
This multiplication is performed in the routine pline
lines 20 and 21.

arrow. This command draws an arrow from
(0,0,0) to (1,0,0).
pyramid argJ arg2 arg3 arg4 arg5 arg6. This com·
mand draws a four·sided pyramid whose base is
centered at argJ, arg2, arg3 and whose half·widths
are arg4, arg5, arg6. The X half·width arg4 is used
as the height of the pyramid.
current. This command prints the current matrix
on the terminal.
priDtdef. This command prints the definition of
the given figure.

When a rotate, scale, or translate command is interpreted, the current matrix is multiplied by another 4 by
4 matrix representing only this transformation. Since
matrix mUltiplication is not commutative, the order
these operations are performed in is preserved. This is
important, because, for example, a rotate before a
translate is not the same as a rotate after a translate
because all rotations are performed pivoting around the
origin (see Figure 16). Initially, the current matrix is set
to the identity matrix. The first operation is performed
relative to state of the current matrix immediately
preceding the operation.

startt. This command starts the 10 ms timer on the
iSBC 86/12 board.
readt. This command stops the 10 ms timer on the
iSBC 86/12 board and prints the 10 ms count on
the terminal.
end. This command stops execution of the
graphics package, prints the total numbers of
points plotted and "success!!!" on the terminal,
and returns control back to ISIS.

Internal Operation of the Package
All internal operations are performed using 1 by 4 or 4
by 4 double precision real matrices. Points are defined
in 1 by 4 double precision vectors where the first three
coordinates are used to hold the X, Y and Z location of
the point. The fourth location is always set to one, and
is used when the point is projected onto a two·
dimensional plane. In most cases, the routine perform·
ing the task, outlined is named the same thing as the
name of the task outlined (within the six· character limit
imposed by FORTRAN). The order the routines are
described is roughly the order a line would encounter
them on its way from existing as a three· dimensional en·
tity inside the machine to a line drawn on the bed of a
plotter. All routine names are set in boldface.

3-515

Parameters are set up into the current matrix through
the rotate, scale, translate, ident, push, and pop operations. Each name describes the function of the operation performed. The routines performing these tasks (in
order) are: rotate, scale, transI, Ident, pusb, and pop.
Ideot is included to allow all rotates and translates to be
set to zero and all scales to be set to one. The pusb and
pop operations are ,included in order that figures may
save the state of the current matrix, while subsequently
performing operations altering it. This is important
when a large figure is defined as a set of parts, each of
which may merely be rotations, etc., of a simpler list of
parts.

210384-001

AP-144

Figure 16. Example Cube Viewed from (0,0,10) FIrSt Rotated then Translated then Translated then Rotated.

Before an object can be plotted, the viewpoint of the
viewer must be known. This information provides the
location of the viewer in three-dimensional space, and
the direction the viewer is pointing. It is incorporated into the 4 by 4 "view" matrix. It is another rotation performed on the object in order that it is viewed from the
proper viewing angle. All points are passed through the
view matrix after they are passed through the current
matrix. What comes out of these two transformations is
a set of points located in the proper relative positions in
three-dimensional space when the figure is rotated,
translated, and scaled by the operations performed on
the current matrix, and is also rotated properly by the
operations set in the view matrix.
The view matrix is set up by the viewpoint command.
This command will place in the view matrix the proper
rotations in order that the image of the object will be
correct. The routine performing this task is the viewpn
routine.

"Z-clipping." Simply, it examines the Z parameter of
every point being considered and determines if it is in
front of the viewer. In addition, cine may not wish to
display lines a great distance from the viewer. These
lines may be removed by a similar process. The only
complication of clipping is the action performed if only
part of the line is visible. In this instance, the point
where the line leaves the visible area must be calculated.
The method used to calculate this point in this iniplementation is the method of "like triangles."
The Z-clipping parameters are set through the command zclip in the routine zclip. The arguments to this
command are used to determine the visible distance in
front of the viewer. The 'first' argument sets the
minimum distance in front of the viewer before any line
will be visible. Legal values for this parameter are
anything greater than zero. The 'Second argument sets
the far distance beyond which no lines will be visible.
Any value larger than the first argument may be used
for this parameter. The clipping itself is performed in
the routine zclipp.

Z·CLlPPING.

All points passed through the current and view matrices
are located at their proper locatio~s in threedimensional space. How~verl' only a portion of this
space is' visible to the viewer. Specifically, objects
behind the viewer will not be visible. Every point of an
object has been mapped to the viewer's space, however,
including those behind the viewer. These "invisible"
points are removed by an operation called

·3-516

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AP-144

PROJECTION

Projection maps the three-dimensional points previously encountered and projects them onto a twodimensional plane. Only single-point perspective is currently supported in the package. Here, the projection is
performed by using the Z parameter to modify the X
and Y parameters. As the points get more distant, their
deviation from the center of the picture should get
smaller, if the X an_d Y parameters remain constant.
Most people are aware of this effect. For example, if
you look down a set of railroad tracks, the rails seem to
converge, even though the distance between the rails is
constant (see Figure 17). Two or three-point perspective
would be easy to implement; all one must do is generate
the projected X and Y parameters by using the nonprojected X and Y parameters in addition to using the Z
parameter.
This. projection is performed in the graphics package by
multiplying the 1 by 4 point location vector by a 4 by 4
"projection" matrix. This matrix is simply the identity
matrix except the perspective value is placed in location
(3,4) of the matrix.

perspective. This normalization is performed by
dividing every element in the vector by the last element
of the vector. Thus, the Z element of the original vector
has modified the X and Y elements. If two or threepoint perspective is desired, one must only place
perspective values in locations (1,4) and (2,4) of the projection matrix; all subsequent processing will be identical. The routines performing these operations are:
viewpn (sets up vanishing point for perspective), projct
(sets up the projection matrix, and performs the
perspective multiplication), and rtorm (normalizes the
vector).

x·y CLIPPING
Once the data is projected onto a two-dimensional
plane, X-Y clipping must be performed. This operation
could also be performed on the three-dimensional data,
but by deferring it until after the data have been projected, the calculations required are simpler. This is not
true for Z-clipping, since once the data are projected
onto a plane, the Z parameter is no longer in its original
form.
X-Y clipping is performed by comparing X and Y
parameters with the window values set up by the window command. This comparison is a bit more complicated than the comparison required by Z clipping,
however as two clipping parameters are involved.
There ar~ nine possible regions in which each endpoint
of a line ·may reside. For example, some of these regions
are: within the X and Y window regions, less than the X
window region but within the Y region, less than the X
region and less than the Y region, etc. If one or both of
the endpoints of the line are within the visible region,
then at least part of the line will be visible. Also, even if
neither of the endpoints of the line is in the visible
region, part of the line may still be visible. One must
therefore determine whether any part of this line would
be visible. A simple way of performing the task is to
assign a bit of a word for each of less than and greater
than the X and Y window limits. This requires four bits.
The value of the X and Y parameters are then each compared with the window limits. If the value exceeds the
limit of the window, the corresponding bit of this point
descriptor is set. After this "code" has been determined
for both of the points, the codes for two endpoints are
bit-wise ANDed together (an extension to FORTRAN
77 available in FORTRAN 86 allows this operation). If
the result of this ANDing is zero, then part of the line
would be visible. If, however, it is not zero, then the entire line lies outside the visible area. If only part of the
line is visible, then the point where it leaves the visible
area must be calculated. The point where the line leaves
the viewing area is calculated using the same "like
triangle" method used when Z-clipping is performed.

Figure 17. Two Rails, Vanishing into the Distance

This value is calculated from the viewpoint parameters.
After the matrix multiply, the only element modified in
the 1 by 4 point definition vector is the last one (the one
which is supposed to have the value of one). After the
multiplication, this location will contain the number
representing the modification which must be performed
on the X and Y parameters of the vector to exhibit the
projection. When this vector is "normalized," the point
will have been projected using the rules of single-point

3-517

210384-001

AP-144

The routines performing these operations are wtovp
(calls the xyclip routine with the proper parameters),
xyclip (performs the actual clipping), code (returns the
binary code for the point position in relation to the win·
dow), and ppush (calculates the point at which line
leaves the visible area).

PERFORMANCE MEASUREMENTS
The above'routines were compiled using the Intel FORTRAN 86 compiler and exeucted on an Intellec@ Series
III development system. The 8086 hardware consists of
an Intel iSBC® 86/12 board with the 8087 in the
iSBC® 337 card. The iAPX 86/20 (the 8086 with the
8087) operate with a clock frequency of 5 MHz. The on
board memory (64K DRAM) inserts between one and
three wait states per memory fetch. In addition, owing
to the size of the memory arrays, the program size, and
the memory reguirements of the Series III, off board
memory was required to run the program.

WINDOW TO VIEWPORT TRANSFORMATION

Finally, after the points have been processed through all
of the above, comes their day of glory. Because the lines
have been clipped, they are constrained to be within the
given window. Remember, however, that the values for
this window are in "real world" units. These sizes could
be measured in inches or miles. These are not generally
suitable for plotting on a graphics output device. In
order for the "window" to be displayed on the graphics
output device, one more transformation must be performed: the window to viewport transformation. A
viewport represents a physical location and size on the
graphics output device. The viewport command sets up
the appropriate parameters for this transformation. It
requires four arguments, which allow the viewport to be
moved around the graphics display surface, and allow
the' size of the viewport to be set. Notice that the
viewport and the window are not constrained to the
same aspect ratios, that is, the ratios between the vertical sizes and the horizontal sizes of the window and
viewport need not be the same. If these ratios are not the
same, the figures will be distorted. Performing this
transformation is simply a matter of scaling the windowed values to fill the viewport. The code performing
this transformation is contained within the wtovp
routine.

The times shown in the table do not show the plotting
time; only the time to generate the output that would be
sent to the plotter is given. This is because the physical
speed limitation of the plotter used would not allow the
iAPX 86/20 system to produce the plotting commands
at its maximum computational speed. The plotter required approximately half an hour to 45 minutes to actually draw the second demonstration picture.
For each line plotted, five 1 by 4 times 4 by 4 matrix
multiplies must be performed along with a non-trivial
amount of other floating point operations, such as
divides and compares. For example, when clipping is
performed, the line endpoint values must be compared
to the clipping parameters. If only part of the line is visible, then the point the line leaves the visible area must be
calculated. This requires twelve additional floating
point operations. Another example is in the window to
viewport transformation. For each line drawn, four
floating point multiplies, four floating point divides,
and four floating point adds must be performed.
In addition, whenever the rotation, Scale, translation or
viewpoint is changed, 4 by 4 matrix multiplies must be
performed. In addition, various trigonometric routines,
such as sines and cosines, must be performed to set up
the rotation parameters into the matrix.

PLOTTER INTERFACE

This graphics package was written to interface to a
Hewlett-Packard 7225A flat bed plotter. Communications were performed through an RS232 serial link at
600 baud. Physically, this is done using the 8251 serial
controller on the iSBC® 86/12 board inside the Intellec@
Series III. The plotter has a smart interface. The commands it accepts are in ASCII, and are on the level of
"lower the pen," and "draw a line from the current pen
position to another pen position." The routines performing these operations are plot (deter,mines the
characters needing to be sent to the plotter), ponum
(converts a floating point number to an ASCII representation of the integer value of the truncated floating
point number), putout (handles the interface to the 8251
serial controller chip) and plots (initializes the baud rate
generator and 8251 serial controller chip on the iSBC®
86/12 board).

The performance measurements are given in Table 1.
Table 1. Performance Measurements

number of points in picture
number of points actually plotted
execution time of the 86/2O(sec)
execution time of the 86 with 87
emulator(sec)
exection time of PDP11145(sec)2

Picture Number
Two
One
9131
117
117
6114
188
2.84
144.77
9801

1.7

120

2A PDPll/45 mini-computer with 256K MOS RAM, and a
FPll-B floating point unit running the UNIX operating
system during a period of light load. The program was com, piled using the UNIX F77 FORTRAN compiler.

3-518

, 210384-001

AP-144

Figure 18. Demonstration Picture 1

The results show that the performance of the iAPX
86120 is close to the performance of the mini-computer.

The figures drawn are shown in Figure 17 for Picture 1
and Figure 18 for Picture 2. The graphics commands required to generate Picture 1 are given in Appendix B.
Picture 2 shows three views of a single shuttle. (Hint:
you are looking out the window of one of the shuttles!)
The shuttle is defined only once in the input data.
Another point to notice is that each shuttle is a conglomeration of parts. For example, the shuttle wing is
defined only once in input data. Tp.e complete shuttle

contains two views of this same wing, translated and
rotated to attach to the appropriate location on the
fuselage of the shuttle itself. The engine nozzles take
this same approach a bit further. The complete nozzle is
defined only once, and is attached in three places on
each shuttle. In addition, each nozzle is made up of
replications of the same circle scaled and translated
through space. Each circle is, in turn, composed of four
views of one quarter-circle, each rotated a proper
amount to form one complete circle.

3-519

210384-001

AP-144

Figure 19. Demonstration Picture 2

CONCLUSIONS
The routines demonstrated in this note show that the
types of operations required to manipulate and display a
three-dimensional figure on a two-dimensional surface
are far from trivial, involving very many floating point
operations. With the introduction of the iAPX 86120,
the floating point performance required by this type of
application is finally within the performance limits of
microcomputers selling for a fraction of the cost of the
previously required mini- or maxi-computers. Examples
of systems in which this performance is required are

Computer Aided Design (CAD) or Computer Aided
Manufacturing (CAM) systems. In addition, the
availability of a full ANSI 77 standard FORTRAN compiler (FORTRAN 86) for the iAPX 86120 enhances the
production or transportation of existing software to the
machine. This combination of high performance hardware with high performance software allows the iAPX
86120 to fill applications never before filled by a
microprocessor.

3-520

210384-001

AP-144

APPENDIX A

Contents
Main Routine
get
proc
ident
defn
printd
call it
printm
pline
pplot
push
pop
rotate
transl
pscale
window
viewpr
viewpn
zclip
zclipp
projct
norm
wtovp
xyclip
code
ppush
copym
mplot
cube
arrow
pyrmd
mmult4
mmult1
plot
ponum
plots
putout
wastet

3-521

' ' .'

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AP-144

1
2

3
4
5
6
7
8
9
10
,11

12
lJ
14
15
16
17
18
19
20

c
c this is the main routine of the graphics program. basically
c it sets up default parameters for the rest of the routines, then
c enters an infinite loop, alternatively fe~ching lines from the input
c
(using routine getl) and sending them to be prqcessed qy the graphics
c processor (proc)
c
common /windoe/wxh,wyh
common /viewp/vxh,vyh,vxc,vyc
real*8 wxh,wyh,vxh,vyh,vxc,vyc
common /matrix/currm,view,curp
real*8 currm(4,4),view(4,4),curp(4)
common /clip/hither,yon,dee
real*8 hither,yon,dee
common /stacks/stackp,sspace
real*8 sspace(10,4,4)
integer stackp
common /defns/dargl,darg2,darg3,darg4,darg5,darg6,darg7,entry,tailp,ends
character*lO dargl(500)
real*8 darg2(500),darg3(500) ,darg4(500) ,darg5(500),darg6(500) ,darg7(500)
integer entry(lO),enqs(lO)
integer tailp
common /cstack/cnum,cnump
integer cnum(lO),cnump
common /penpos/xpos,ypos,pcount
real*8 xpos,ypos
integer*4 pcount
c

21
c
22

c
23
24
25
26
27
28

29
30
31
32
33
34
35
36
37

initialize the plotting package
call plots
initialize the stack pointer
stackp if 1
set up a few defaults
wxh
10.
wyh
10.
vxh
5.
vyh
5.
vxc
5.
vyc
5.
hither = l.
yon = 100.
dee = 10.
tailp = 1
cnump = 1
xpos = -i.
ypos = -l.
pcount = 0
print * , 'GRAPHICS program entered! ! !

I

C

c
c
38

3~

40
41
42

initialize the current matrix

call ident(currm)
c
c and process all the input lines
c
100
call getl
call proc
goto 100
end

3-522

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AP·144

c
c
c
c
c
c
c
c
c
c
c
c

getl(line)
fetches the next line from the input file, and grabs the first 7
things from it, the first being an alpha command contained within
(') and the rest being numbers. If less than 6 number are input
the input line must be terminated by a (I) in order for the
read statement to be correctly interpreted. The arguments are then
placed in the common block "args". When the 'end' command is
encountered, "success" is printed on the terminal, and the

graphics program terminates.

43
44
45
46

subroutine get 1
common /args/argl,arg2,arg3,arg4,arg5,arg6,arg7
character*lO argl
real*8 arg2,arg3,arg4,arg5,arg6,arg7

47
48
49
50
51
52
53
54

read (5,*)argl,arg2,arg3,arg4,arg5,arg6,arg7
if(argl .eq. 'end') then
call plot(0.,O.,999)
print ., 'success!!1'

stop
endif
return
end
c
c
c
c
c
c

proc
proc() does all the processing for a line.
It gets its arguments
from the common block args, and does it's thing

55

subroutine proc

56
57
58
59
60
61
62
63
64
65
66

common /matrix/currm,view,curp

real*8 currm(4,4),view(4,4),curp(4)
common /args/argl,arg2,arg3,arg4,argS,arg6,arg7
character*lO argl
real*8 arg2,arg3,arg4,arg5,arg6,arg7
common /clip/hither,yon,dee
real*8 hither,yon,dee
common /cstac~/cnum,cnump

integer cnum(lO),cnump
integer i
integer*4 rtimer,countt
c
c
c
c

67
68
69
'70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86

determine the command entered (HUGE if-then-else if-,etc) and
call the appropriate routine with the correct' arguments
if(argl .eq.
i

100
800

=

'comment') then
1

read(5,800)
i = i + 1
if(i .le. int(arg2» got a 100
format(al)
else if(argl .eq. 'define') then
i = int(arg2)
call defn (i)
call printd(i)
else if(argl .eq. 'call') then
cnum(cnump) = int(arg2)
cnump = cnump + 1
if(cnump .gt. 10) then
print *, 'call nesting level too deep, sorry'
cnump = 10
endif
call callit(cnum(cnump - l),cnump - 1)
cnump = cnump - I
else if(argl .eq. 'line') then

3-523

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AP-144

87
8B
89
90
91
92
93
94
95
96
97
9B
99
100
101
102
103
104
105
106
107
108
109
110
III
112
113
114
115
116
117
11B
119
120
121
122
123
124
125
126
127
128
129

call pline(arg2,arg3,arg4,arg5,arg6,arg7,2}
else if(argl .eq. 'plot'} then
i = int(arg5}
call pplot(arg2,arg3,arg4,i}
else if(argl .eq. 'ident'} then
call ident(currm}
else if(argl .eq. 'push'} then
call push(currm}
else if(argl .eq. 'pop'} then
call pop(currm}
else if(argl .eq. 'rotate') then
call rotate(arg2,arg3,arg4,currm}
else if(argl .eq. 'translate'} then
call transl(arq2,arg3,arg4,currm}
else if(argl .eq. 'scale') then
call pscale(arg2,arg3,arg4,currm)
else if(argl .eq. 'window'} then
call window(arg2,arg3)
else if(argl .eq. 'viewport'} then
call viewpr(arg2,arg3,arg4,arg5)
else if(argl .eq. 'viewpoint'} then
call viewpn(arg2,arg3,arg4,arg5,arg6,arg7)
else if(argl .eq. 'zclip') then
call zclip(arg2,arg3}
else if(argl .eq. 'cube'} then
call cube(arg2,arg3,arg4,arg5,arg6,arg7)
else if(argl .eq. 'arrow') then
call arrow
else if(argl .eq. 'pyramid'} then
call pyrmd(arg2,arg3,ar~4,arg5,arg6,arg7)
else if(argl .eq. 'current'} then
call printm(currm}
else if(argl .eq. 'printdef'} then
i = int(arg2)
call printd(i)
else if(argl .eq. 'startt'} then
call stimer
else if(argl .eq. 'readt') then
countt = rtimer(}
print *, 'the time (in seconds) from the last startt is:' ,countt/IOO.
else
print *, 'error, command' ,argl, 'unknown'
endif

130
131

return
end
c
c
c
c
c

ident(matrx)
ident(} sets the given 4 X 4 matrix to the identity matrix.

132
133
134

subroutine ident(matrx}
real*B rnatrx(4,4}
integer i,j

135
136
137
138
139
140
141
142
143

do 100 i=I,4
. do 100 j=1,4
matrx (i, j )
continue
do 110 i=I,4
matrx(i,il
1continue'
return
end

100
110

O.

3-524

210384-001

AP-144

c
c
c
c
c
c
c
c

subroutine defn(number) defines figure number. the defined figure
is contained in a large common block "defns" which contains
enough space for a total of 500 commands. comments are not
stored along with the define commands to save space. the variables
entry and ends contain the starting and ending indexes of the
10 possible defined figures

144
145
146
147
148
149
150
151
152
153
154

subroutine defn(number)
integer number
common /defns/darg1.darg2.darg3.darg4.darg5.darg6.darg7.entry.tailp.ends
character*10 darg1(500)
real*8 darg2(500).darg3(500).darg4(500).darg5(500).darg6(500).darg7(500)
integer entry(10).ends(10)
integer tailp
common /args/arg1.arg2.arg3.arg4.arg5.arg6.arg7
character*10 arg1
rea1*B arg2.arg3.arg4.arg5.arg6.arg7
integer i '

155
156

entry(number) = tailp
print *. 'start of define is at'.tai1p

157

158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183

100
c
c
c

call get 1
check for terminate of define
if(arg1 .eq. 'enddef') then
ends (number)
tailp
print *.'end of figure define is at' .tailp
return
else if(arg1 .ne. 'comment') then
dargl(tailp)
arg1
darg2(tailp)
arg2
darg3(tailp)
arg3
darg4(tailp)
arg4
darg5(tailp)
arg5
darg6(tailp)
arg6
darg7(tai1p)
arg7
tailp = tai1p + 1
if(tai1p .gt. 500) then
print *.'define memory overrun!!!'
tailp = 500
endif
else
i
1
read(5.BOO)

=

150

=

i

=i

+ 1

if(i .1e. int(arg2»
format(al)

800

goto 150

endif
goto 100
end

3-525

210384-001

AP-144

c
c
c
1B4
1B5
1B6
1B7
1BB
1B9
190
191
192
193
194
195
196
197
19B

subroutine printd(number)
integer number
common /defns/darg1,darg2,darg3,darg4,darg5,darg6,darg7,entry,tai1p,ends
character* 10 darg1'( 500)
rea1*B darg2(500) ,darg3(500),darg4(500),darg5(500) ,darg6(500) ,darg7(500)
integer entry(10),ends(10)
integer tai1p
integer i

i = entry(number)
100
BOO

c
c
c
c
c

100

c
c
c
c
223
224
225
226
227
22B
229
230
231

if(i .eq. ends(number»
return
write(6,800)darg1(i),darg2(i),darg3(i),darg4(i),darg5(i),darg6(i),darg7(i)
format(a10,6f11.4)
i
i + 1
goto 100
end

=

subroutine ca11it(rtumber,nest) causes the defined figure number to
be input to the graphics processor, nesting level must be provided
to allow pseudo-recursive type calls •••
subroutine ca11it(number,nest)
integer number, nest
common /defns/darg1,darg2,darg3,darg4,darg5,darg6,darg7,entry,tai1p,ends
character*10 darg1(500)
rea1*8 darg2(500) ,darg3(500) ,darg4(500) ,darg5(500) ,darg6(500) ,darg7(500)
integer entry(10),ends(10)
integer tai1p
common /args/arg1,arg2,arg3,arg4,arg5,arg6,arg7
character*10 arg1
rea1*8 arg2,arg3,arg4,arg5,arg6,arg7
integer i(10)

199
200
201
202
203
204
205
206
207
20B
209
210
211
212
213
214
215
216
217
21B
219
220
221
222

subroutine printd(number) prints the defined figure commands

"

100
BOO

i(nest) = entry(number)
if(i(nest) .eq. ends(number»
arg1
darg1(i(nest»
arg2
darg2(i(nest»
arg3
darg3(i(nest»
arg4
darg4(i(nest»
arg5
darg5(i(nest»
arg6
darg6(i(nest»
arg7
darg7(i(nest»
call proc
i(nest) = i(nest) + 1
goto 100
end

return

printm(matrx)
printm prints out the given 4x4 double precision matrix
subroutine printm(matrx)
rea1*B matrx(4,4)
integer i
do 100 i=l,4
write(6,800)matrx(i,l),matrx(i,2),matrx(i,3),matrx(i,4)
continue
format ( 4f15. 4)
return
end

3-526

210384-001

AP-144

c
c
c
c
c
c
1

\

pline() draws a line from (x,y,z) to (a,b,c) with pencode s, using
the current window, viewpoint, viewport, etc.
subroutine pline(x,y,z,a,b,c,s)
real*R x,y,z,a,b,c
integer s
common /matrix/currm,view,curp
real*A currm(4,4),view(4,4),curp(4)
logical zclipp,junk
real*A tmpf(4),tmpt(4)

2

3
4
5
6
7
8
9
10

tmpf(l) = x
tmpf( ::1)
y
tmpf(3)
z
tmpf(4)
1.
tmpt(l )
a
tmpt(2)
b
tmpt(3)
c
tmpt(4)
1.
curp(l )
a
curp(2)
b
curp(3) = c
curp(4)
1.

11

12
13
14
15
16
17
18

Ie}
c
c
c
20
21
22
23

perform translations, and viewing translation
call
call
call
call

c
• c
c
24
75

mmultl(tmpf,currm,tmpf)
mmultl(tmpt,currm,tmpt)
mmultl(tmpf,view,tmpf)
mmultl(tmpt,view,tmpt)

perform zclipping on both points .••
if(zclipp(tmpf,tmpt).eq . . false.) goto 200
junk=zclipp(tmpt,tmpf)

c
c
c
26

project the vector into ?-D
call projct(tmpf)
call projct(tmpt)

n

c
c
c
28
29
30

pline(x,y,z,a,b,c,s)

do x/y clipping, the window to viewport transform, and plot the vector
call wtovp(tmpf,tmpt,s)

200

return

end

3-527

210384-001

AP-144

c
c
c
c
c
c
c

pplot(x,y,z,t)
plot a line from the current position to (x,y,z) using pencode t.
Basically, sets up a call to pline' from the current position
to the new position using the appropriate pencode.

31

subroutine pplot(x,y,z,t)

3?

real*q x,y,z

33
34
35

integer t
common /matrix/currm,view,curp
real*8 currm(4,4),view(4,4),curp(4)

36
37
38

call plinelcurp(1),curp(2),curp(3),x,y,z,t)
return
end
c
c
c
c
c
c
c

39
40
41
42
43

integer stackp

if(stackp .gt. 10) then
print *, 'stacK overflow'
return

end if
call copym(sspace(l,l,stackp),matrix)
stackp=stackp+l
return
end

~O

c
c
c
c
c
c

55

57
58
59
60
61
62
63
64
65

current matrix.

dimension matrix(4,4)
common /stacks/stackp,sspace

51

56

push() pushes the given matrix onto the matrix stack, checks
for stack overflow, and won't let youl III Does not alter the
subroutine push(matrix)
real*8 matrix,sspace(4,4,10)

44
45
46
47
48
49

52
51
54

pushlmatrix)

pop(matrix)
pop() pops the top of stack into the given matrix.
stack underflow, and again won't let you do it!!I!

Checks for

subroutine pop(matrix)
real*R matrix,sspace(4,4,10)
integer stackp
dimension matrix(4,4)
common /stacks/stackp,sspace
stackp=stackp-l
if(stackp .It. 1) then
print *, 'stack underflow'

sta"kp = 1
return

end if
call copym(matrix,sspace(l,l,stackp»
return
'
end

3-528

210384-001

AP-144

c
c
c
c
c
c
c

rotate(x,y,z,matrix)
rotate() pre-concatenates the given (x,y,z) rotation, to the
supplied matrix(usually the current matrix). x,y,z are given
in degrees.
subroutine rotate(x,y,z,matrix)

1
2
3
4
5

real*B x,y,z,matrix

dimension matrix(4,4)
real*8 tmp
dimension tmp(4,4)

6
7
8
9
10

call ident(tmp)
tmp(2,2)
cos(x * 0.01745329)
tmp( 3,3)
tmp( 2,2)
tmp(2,3)
sin(x * 0.01745329)
tmp(3,2)
- tmp(2,3)

11

call mmult4(tmp,matrix,matrix)

12
14
15
16

call ident(tmp)
tmp(l,l)
cos(y * 0.01745329)
tmp(3,3)
tmp(l,l)
tmp(3,1)
sin(y * 0.01745329)
tmp(1,3)
- tmp(3,1)

17

call mmult4(tmp,matrix,m~trix)

18
19
20
21
22

call ident(tmp)
tmp(l,l)
cos(z * 0.01745329)
tmp ( 2, 2 )
tmp ( 1, 1)
tmp(1,2)
sin(z * 0.01745329)
tmp(2,1)
- tmp(1,2)

23

call mmult4(tmp,matrix,matrix)

24
25

end

13

return

c
c
c
c
c
c

translate( X, y., z, matrix)
translate() pre-concatenates the given tranlation (x,y,z) to the
given matrix(usually the current matrix).

26
27
28

dimension matrix(4,4)

subroutine transl(x,y,z,matrix)

29
30

real*8 tmp
dimension tmp(4,4)

31
32
33
34

call ident(tmp)
tmp(4,1)
x
tmp(4,2) = y
tmp(4,3) = z

35

call'mmult4(tmp,matrix,matrix)

36
37

return
end

real*8 x,y,z,matrix

3-529

210384-001

AP-144

c
c
c
c
c
c

pscale(x,y,z,matrix)
pscale pre-concatenates the given scaling (x,y,z) onto the
given matrix_

38
39
40

dimension matrix(4,4)

41
42

real*8 tmp
dimension tmp(4,4)

43
44
45
46

call ident(tmp)
tmp(l,l) = x
tmp(2,2)
y
tmp(3,3) = z

47

call mmult4(tmp,matrix,matrix)

48
49

return
end

subroutine pscale(x,y,z,matrix)
real*8 x,y,z,rnatrix

c
c
c
c
c
c

window(a,b) viewport(a,b,c,d)
these two routines set up the global variables according to the
given parameters_

50
51
52
53

subroutine window(a,b)
real*8 a,b
reaP'8 wxh,wyh
common /windoe/wxh,wyh

54
55
56
57

wxh = a
wyh = b
return
end
c

58
59
60
61

subroutine viewpr(a,b,c,d)
real*8 a,b,c,d
real*8 vxh,vyh,vxc,vyc
Common /viewp/vxh,vyh,vxc,vyc

62
63
64
65
66
67
68
69
70
71
72

vyc
b
vxh
c
vyh
d
call mplot(vxc
call mplot(vxc
call mplot(vxc
call mplot(vxc
call mplot(vxc
return

vxc

a

- vxh;vyc + vxh,vyc + vxh,vyc +
- vxh,vyc +
- vxh,vyc -

vyh,3)
vyh,2)
vyh,2)
vyh,2)
vyh,2)

~nd

3-530

210384-001

AP-144

c
c
c
c
c
c
c

viewpoint(a,b,c,d,e,f)
viewpoint sets up the viewing transformation for the given
to and from points---the eye position is (a,b,c) the lookat
position is (d,e,f).

1
2

subroutine viewpn(a,b,c,d,e,f)
real*8 a,b,c,d,e,f

3
4
5
6
7
8

real*8
real*8
common
real*8
common
real*8

angle
tmp(4,4),tmpp(4)
/matrix/currm,view,curp
currm(4,4),view(4,4),curp(4)
/clip/hither,yon,dee
hither,yon,dee

c
c
c

initialize the viewing transformation
call ident(view)

9
c
c
c
10

move lookat position to origin
call transl(-d,-e,-f,view)

c
c
c

rotate view matrix per the lookat angle

=a

11

a

12
13
14
15
16
17
18
19

b .. b -

- d

20

call mmult4(view,tmp,view)

21
22
23
24
25
26

angle
atan2(b,sqrtia*a + c*c»
call ident(tmp)
tmp(2,2)
cos(angle)
tmp(3,3)
tmp(2,2)
tmp(2,3)
sin(angle)
tmp(3,2)
- tmp(2,3)

27

call mmult4(view,tmp,view)

28
29
30
31
32
33
34

a
a +
b
b +
c - c +
tmpp(l)
tmpp(2)
tmpp(3)
tmpp(4)

35

call mmultl(tmpp,view,tmpp)

36
37
38

dee" tmpp(3)
return
end

e
c = c - f
angle
- atan2(a,c)
call ident(tmp)
tmp(l,l)
cos(angle)
tmp(3,3) .. tmp(l,l)
tmp(3,l) = sin(angle)
tmp(l,3)
tmp(3,l)

=

=-

=

=

d
e
f
a
b
.. c
1.

3-531

210384-001

AP-144

c
c
c
c
c
c
c
c

zclip(a,b)
zclip() sets up the global clipping parameters, a is the hither,
b the yon, does not allow the hither plane to be behind the
viewer, nor does it allow the yon to be between the viewer
and the hither.

39
40
41
42

subroutine zclip(a,b)
real*8 a,b
real*8 hither,yon,dee
common /clip/hither,yon,dee

43
44
45
46
47
48
49
50
51
52
53
54

if(a .It. 0) then
print *, 'bad hither parameter'
a

= a

end.if
if(b .It. a) then
print *, 'bad yon parameter'
b = a + 100
end if
hither = a
yon = b
return
end
c
c
c
c
c
c
c
c

zclipping(vectl,vect2)
zclipping() performs the zclipping on vectl using the global
zclipping parameters. Modifies ONLY vectl, returns true if
a portion of the vector indicated by (clipped)vectl and vect2
will be visible in the scene.

55
56
57
58

logical function zclipp(vectl,vect2)
real*8 vectl(4),vect2(4)
common /clip/hither,yon,dee
real*8 hither,yon,dee

59

real*8 htr,yn

60
61

htr = dee - hither
yn
dee - yon

62

zclipp = .true.

63
64
65
66

if(vectl(3) .gt. htr) then
if(vect2(3) .gt. htr) then
zclipp = .false.
else

=

c
c
c
c

you must modify the x and y parameters (according to like triangles)
when the z parameter is modified!11

67

vectl(l)

(vectl(l)
(vectl(3)
vectl(2)
(vectl(2)
(vectl(3)
vectl ( 3 )
htr
zclipp
.true.

68
69
70
71
72
73
74
75

-

vect2(1»*«htr - vect2(3»/
vect2(3») + vect2(1)
vect2(2»*«htr - vect2(3»/
vect2(3») + vect2(2)

=

end if
else

i~.(vectl(3)

.It. yn) then
if(vect2(3) .!t. yn) then
zclipp
.false.
else

=

3-532

210384-001

AP-1~4

76

vectl(1 )

*'

77

vectl (2)

*

78
79
80
81
82
83

vectl(3)
zclipp

=

(vect2(1)
(vect2(3)
(vect2(2)
(vect2(3)
yn
.true.

-

vectl(l»*«yn - vectl(3»/
vectl(3») + vectl(l)
vectl(2»*«yn - vectl(3»/
vectl(3») + vectl(2)

end if
end if
return
end
c
c
c
c
c
c

projct(vector)
projct() projects the given vector to a point in 2-D space using
the global "dee" parameter, for single point perspective.

1
2
3
4
5

sUbroutine projct(vector)
real*8 vector(4)
common /clip/hither,yon,dee
real*8 hither,yon,dee
real*8 tmp(4,4)

6

call ident(tmp)
if(dee .ne. 0) then
tmp(3,4)

7

8
9
10

else

11

endif

12

call mmultl(vector,tmp,vector)
call norm(vector)
return
end

tmp(3,4)

13

14
15
c
c
c
c
c
c

1 / dee
- 1000000000.

norm(vector)
norm() normalizes the given vector.

16
17

subroutine norm(vector)
real*8 vector(4)

18
19
20
21
22
23

vector(l)
vector(2)
vector(3)
vector(4) =
return
end

vector(l) / vector(4)
vector(2) I vector(4)
vector(3) / vector(4)
1.

3-533

210384-001

Ap·144

c
c
c
c
c
c
c
c

wtovp(from,to,pencode)
wtovp( ) takes the projected from and to points, and:
1: does x/y clipping on the window
2: does the window to viewport translation
3: plots the transformed points onto the device

24
2"5
26
27
28
29
30
31
32

subroutine wtovp(from,to,pencde)
real*8 from(4),to(4)
integer pencde
common /windoe/wxh,wyh
real*8 wxh,wyh
common /viewp/vxh,vyh,vxc,vyc
real*8 vxh,vyh,vxc,vyc
logical xyclip
real*8 xp,yp

33
34
35

if(xyclip(from,to» then
xp
(from(l» * vxh / wxh + vxc
yp = (from(2» * vyh / wyh + vyc

36
37
38

call mplot(xp,yp,3)
xp
(to(l» * vxh / wxh + vxc
yp = (to(2» * vyh / wyh + vyc

39
40
41
42

call mplot(xp,yp,pencde)
endif
return
end
c
c
c
c
C
C
C

100

xyclip = .false.
call code(from,cf)
call code(to,ct)
if«cf .and. ct) .ne. 0) goto 105
if(cf .ne. 0) call ppush(cf,from,to)
if(ct .ne. 0) call ppush(ct,to,from)
if«cf + ct) .ne. 0) goto 100
xyclip = .true.

50
51
52
53
54
55

xyclip() performs the x/y clipping on both the from and t
vectors in the window cooridinates. Returnes false if
none of the vector would be visible.
logical function xyclip(from,to)
real*8 from(4),to(4)
integer*2 cf,ct

43
44
45
46
47
48
49

xyclip(from,to)

105

return
end

3-534

210384·001

AP-144

c
c
c
c
c
c

code(vector, flag)
code() returns the binary code in flag for vector indicating
it's position relative to the window,

6

subroutine code(vector,flag)
real*8 vector(4)
integer flag
common jwindoejwxh,wyh
real*8 wxh,wyh
real*8 tmp

7

flag = 0

1
2
3
4
5

tmp = vector(l)
if(tmp .It. - wxh) flag = 1
if(tmp .gt. wxh) flag = flag + 2
tmp = vector(2)
if(tmp .It. -wyh) flag = flag + 4
if(tmp .gt. wyh) flag = flag + 8
return
end

8
9
10
11

12
13

14
15
c
c
c
c
c
c
c

ppush(flag,to, from)
ppush() pushes "to" towards "from" according to flag, which
contains the code returned by code(). used to insure that the
line exits the window at the correct point

16
17
18
19
20

subroutine ppush(flag,to,from)
real*8 to(4),from(4)
integer flag
common jwindoejwxh,wyh
real*8 wxh,wyh

21

if( (flag .and. 1) .ne. 0) then

22
23
24
25

to(2)

*

to(l)

to(2)

*

to(l)

to(l)

*

to(2)

+ from(2)

«-wyh - from(2»
j(to(2) - from(2»)*(to(1) - from(l»
-wyh

+ from(l)

endif
if«flag .anll. 8) .ne. 0) then
to(l)

34
35
36
37
38

«wxh - from(l»
j(to(l) - from(1»)*(to(2) - from(2»
wxh

endif
if«flag .and. 4) .ne. 0) then

30
31
32
33

+ from(2)

endif
if«flag .and. 2) .ne. 0) then

26
27
28
29

«-wxh - from(l»
j(to(l) - from(1»)*(to(2) - from(2»
-wxh

*

to(2)

«wyh - from(2»
j(to(2) - from(2»)*(to(1) - from(l»
wyh

+ from(l)

endif
return
end

3-535

210384-001

AP-144

c
c
c
c
c

copym(dst,src)
copym() copies the src 4X4 matrix to the dst 4X4

39
40

subroutine copym(dst,src)
real*8 dst(16),src(16)

41

integer i

42
43
44
45
46

do 100 i
1,16
dst(i) = src(i)
continue
return
end

100

c
c
c
c
c
c
c

mplot(argl,arg2,arg3)
mplo't() calls plot with argl,arg2,arg3.
inserted as another level
of indirection in order to allow the actual plot commands to be
written to a file, etc.

47
48
49

subroutine mplot(argl,arg2,arg3)
real*8 argl,arg2
integer arg3

50
51
52

call plot(argl,arg2,arg3)
return
end
'c
c
c
c
c
c

matri~.

cube(argl,arg2,arg3,arg4,arg5,arg6)
cube() generates a cube centered at (argl,arg2,arg3) with
arg4,arg5.arg6 as it's half widths

1
2

subroutine cube(argl,arg2,arg3,arg4,argS,arg6)
real*8 argl,arg2,arg3,arg4,argS,arg6

3
4
S
6

call pline{argl-arg4,arg2-argS,arg3-arg6.argl+arg4,arg2-arg5.arg3-arg6,2)
call pplot(argl+arg4,arg2+argS,arg3-arg6,2)
call pplot(argl-arg4,arg2+arg5,arg3-arg6,2)
call pplot{argl-arg4,arg2-arg5,arg3-arg6,2)
call pplot(argl-arg4,arg2-argS.arg3+arg6,2)
call pplot(argl+arg4,arg2-argS,arg3+arg6,2)
call pplot(argl+arg4,arg2+argS,arg3+arg6.2)
call pplot(argl-arg4,arg2+arg5,arg3+arg6,2)
call pplot{argl-arg4,arg2-arg5,arg3+arg6,2)
call pline{argl+arg4,arg2-arg5,arg3-arg6,argl+arg4,arg2-arg5,arg3+arg6,2)
call pline{argl+arg4,arg2+arg5,arg3-arg6,argl+arg4,arg2+arg5,arg3+arg6,2)
call pline{argl-arg4,arg2+arg5.arg3-arg6,argl-arg4,arg2+argS,arg3+arg6,2)
return
end

7

8
9

10
11

12
13
14
15
16

3-536

210384-001

Ap·144

c
c
c
c
c

arrow( )
arrow() draws a sort-of arrow from (0,0,0) to (1,0,0)

c
17

subroutine arrow()

18
19
20
21
22
23
24

call p1ine(0.,0.,0.,1.,0.,0.,2)
call p1ine(1. ,0. ,0., .8, .2,0.,2)
call pline(I.,0.,0.,.8,0.,.2,2)
call pline(I.,0.,0.,.8,-.2,0.,2)
call pline(1.,O.,O.,.8,O.,-.2,2)
return
end
c
c
c
c
c
c
c

pyrmd(argl,arg2,arg3,arg4,arg5,arg6)
pyrmd() draws a pyramid with the center of it's base at
(argl,arg2,arg3) and half x,y,z widths of arg4,arg5,arg6.
The height is the x half width.

25
26

subroutine pyrmd(argl,arg2,arg3,arg4,arg5,arg6)
real*8 argl,arg2,arg3,arg4,arg5,arg6

27

real*8 height

28
29
30
31

call
call
call
call

32
33
34
35
36
37
38

height = arg4 - argl
call pline(argl-arg4,arg2-arg5,arg3-arg6,argl,arg2,arg3+height,2)
call pline(argl+arg4,arg2-arg5,arg3-arg6,argl,arg2,arg3+height,2)
call pline(argl-arg4,arg2+arg5,arg3-arg6,argl,arg2,arg3+height,2)
call pline(argl+arg4,arg2+arg5,arg3-arg6,argl,arg2,arg3+height,2)
return
end

pline(argl-arg4,arg2-arg5,arg3-arg6,argl+arg4,arg2-arg5,arg3-arg6,2)
pplot(argl+arg4,arg2+arg5,arg3-arg6,2)
pplot(argl-arg4,arg2+arg5,arg3-arg6,2)
pplot(argl-arg4,arg2-arg5,arg3-arg6,2)

3-537

210384-001

Ap·144

c
c
c
c
c
c
c
c
c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

subroutine mmu1t4(mp1,mp2,mpr)
subroutine mmu1t4 multiplies the mp1 4x4 matrix
and multiplies it by the mp2 4x4 matrix.
the result is
placed in the mpr 4x4 matrix.
internal results are placed
in a temporary matrix, then copied over in order that one of
the operands may be used as the destination matrix
subroutine mmu1t4(mp1,mp2,mpr)
rea1*8 mp1(4,4),mp2(4,4),mpr(4,4)
rea1*8 acc
real*8 temp(4,4)
integer i,j,k

110
100

120

c
c
c
c
c
c
c
c
c

do 100 i=1,4
do 100 j=1,4
acc = O.
do 110 k=1,4
acc
acc + mpl(i,k)*mp2(k,j)
continue
temp(i,j)
acc
continue
do 120 i=1,4
do 120 j=1,4
mpr(i,j)
temp(i,j)
continue
return
end

subroutine mmultl(mp1,mp2,mpr)
subroutine mmu1tl multiplies the mp1 4 position vector
by the mp2 4x4 matrix. _the result is put in the mpr 4
position vector.
results are calculated into a temporary
vector, then copied over so that the mpl vector may be used
as the destination of the result

20
21
22
23
24

subroutine mmu1t1(mp1,mp2,mpr)
real*8 mp1(4),mp2(4,4),mpr(4)
rea1*8 acc
real*8 temp(4)
integeri,j,k

25
26
27
28
29
30
31
32
33
34
35
36

do 100 j=1,4
acc = O.
do 110 k=1,4
acc = acc + mp1(k)*mp2(k,j)
110
100
120

continue

temp(j) = acc
continue
do 120 i=1,4
mpr(i) = temp(i)
continue
return
end

3-538

210384·001

AP·144

c
c
c
c
c
c
c
c
c
c
c
c
c
c

subroutine plot(x,y,penc)
subroutine plot plots a line from the current pen position to
the given pen position using the pencode given. The possible
pen codes are:
2: pen down
3: pen up
999: terminate plotting
the actual interface described here if for the serial port on the
iSBC 86/12a board connected to an HP7225A flat bed plotter. no
handshaking is done.

1
2
3
4
5
6

subroutine plot(x,y,penc)
real*8 x,y
integer penc
common /penpos/xpos,ypos,pcount
real*8 xpos,ypos
integer*4 pcount

7

pcount

8
9
10
11

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

= pcount

+ 1

if(penc .eq. 999) then
call putout( 'p')
call putout('U')
call putout('~ ')
print *, 'the number of points plotted is:' ,pcount
goto 200
endif
if«xpos.eq.x).and.(ypos.eq.y» then
if(penc .eq. 2) then
call putout('P')
call putout('D')
call putout('~')
call putout('P')
call putout('U')
call putout('~')
else
goto 200
endif
else
if(penc .eq.
call
call
else if(penc
call
call
else
call
call
call
goto
endif

3 ) then
putout ( 'P' )
putout ( 'U')
.eq. 2) then
putout ( 'p' )
putout ( , D' )

putout ( 'P' )
putout ( 'U')
putout ( , ~ , )
200

3·539

210384-001

Ap·144

39
40
41
42
43
44
45
46
47
48
49
50
51
52

200

c
c
c
c
c
c
c
c

-end if
xpos = x
ypos .. y
return
end

call
call
call
if(x
call
call
if(y
call
call

putout(';')
putout('p')
putout('A')
.gt. 12) x - 12
ponum(x)
putout(',')
.gt. 10) y - 10
ponum(y)
putout(';')

subroutine ponum(number)
subroutine ponum takes the given double precision real number,
truncates it to integer, then runs the resultant integer out
the iSBC 86/l2a serial port. leading zeros are suppressed.
the maximum number is 99999111

53
54
55
56
57
58

subroutine ponum(number)
real*8 number
character lookup(9)
logical flag
integer multip(5)
integer work

59
60
61
62
63
64
65
'66
67
68
69
70
71
72
73
74
75
76

data lookup/Ill, '2',13','4', '5',16' ,'7','S','9'/
data multip/lOOOO,lOOO,lOO,lO,ll
flag = •falSe.
if(number .It. 0) number" O.
number
number * 800.
do 100 i .. 1,5
work
aint(number 1 real(multip(i»)
if(work .eq. 0) then
if(flag) call putout('O')
el'se
call putout(lookup(work»
flag . . . true.
endif
number .. number - work * multip(i)
continue
if(.not. flag) call putout('O')
return
end

=

=

100

r

3-540

210384-001

AP·144

c
c
c
c
c
c
c
c

subroutine plots
subroutine plots initialized the iSBC86/l2 board baud rate
generator(really part of the 8253 timer) and serial line.
the given numbers will set it up for 600 baud, 8 bits, no
parity

77
78
79

subroutine plots
common /penpos/xpos,ypos
real*8 xpos,ypos

80
81
82
83
84

xpos
10000.
10000.
ypos
call output(#Od6h,intl(#Ob6h»
call output(#Od4h,intl(#80h»
call output(#Od4h,intl(0»

85
86
87
88
89
90
91
92
93
94
95

calloutput(#Odah,intl(#72h»
call wastet
call output(#Odah,intl(#25h»
call wastet
calloutput(#Odah,intl(#62h»
call wastet
call output(#Odah,intl(#Oceh»
call wastet
calloutput(#Odah,intl(#27h»
return
end
c
c
c
c
c
c
c

100

call input(#Odah,status)
status = status .and. 4
if(status .eq. 0) goto 100
calloutput(#Od8h,intl(ichar(c»)
return
end

102
103
104
c
c
c
c
c
c
105
106
107

subroutine putout puts the character given out on the iSBC 86/12
board serial line (checks for transmitter empty, loops on not empty,
on empty puts out the character)
subroutine putout(c)
character c
integer· 1 status

96
97
98
99
100
101

subroutine putout(c)

subroutine wastet
subroutine wastet wastes a little bit of time while the 8253 gets
its act together
subrou~ine

wastet

return
end

3-541

210384-001

APPENDIX B

run : f5:graph
'define' 1 /
'viewport' ?.5
'viewpoint ' 10
, windo\/' l() lrl
'cube' () () () /.
'viewport' 7.5
I rotate I
15 15
'cub(" () 'l () ?
vie\..,port
'.5
I

I

'id~nt'

I

2.5

~

2

10 IO

f)

/

0 0

I

2 ~ /
2.5 ? '2

IS /

/. ;>

/

7.'i 2 '2

/
/

'vlp.wpoint' 10 0 0 0 (l 0
'cub~' 0 () 0 2 ?
'- /
'viewport' 7.S 7.5 2 '1 /
'roti'tte' 3() 30 3() /
'cube' 0 () () :2 ? 2 I

en(lrief'
'call' I
I

I

end

I

I

I

I

I
/

3-542

210384-001

APPLICATION
NOTE

AP-186

March 1983

© INTEL CORPORATION, 1983

ORDER NUMBErR: 210973-003

3-543

AP-186

1.

on a single chip (see Figure 1), system construction is
simplified since many of the peripheral interfaces are integrated onto the device.

INTRODUCTION

As state of the art technology has increased the number
of transistors possible on a single integrated circuit,
these devices have attained new, higher levels of both
performance and functionality. Riding this crest are the
Intel 80186 and 80286 microprocessors. While the
80286 has added memory protection and management
to the basic 8086 architecture, the 80186 has integrated
six separate functional blocks into a single device.

The 80186 family actually consists of two processors: the
80186 and 80188. The only difference between the two
processors is that the 80186 maintains a 16-bit external
!lata bus while the 80188 has an 8-bit external data bus.
Internally, they both implement the same processor with
the same integrated peripheral components. Thus, except where noted, all 80186 information in this note also
applies to the 80188. The implications of having an 8-bit
external data bus on the 80188 are explicitly noted in appendix I. Any parametric values included in this note are
taken from the iAPX 186 Advance Information data
sheet, and pertain to 8Mhz devices.

The purpose of this note is to explain, through example,
the use of the 80186 with various peripheral and memory devices. Because the 80186 integrates a DMA unit,
timer unit, interrupt controller unit, bus controller unit
and chip select and ready generation unit with the CPU

INT3IINTAI
INT2IIIiITAO
CLKOUT Vee GND

rD~
I I

X,

!!

TMR

'EXECUTION

uNiTJ

X,

16·BIT
AW
CLOCK
GENERATOR
16·BIT
GENERAL
PURPOSE
REGISTERS

{(

)

I
I
I
I
I
I
I

t

INi"'

!

!

I~

1

TMR IN

1

t

t

PROGRAMMABLE
TIMERS
0
1
2

BS:S

MAX COUNT
REGISTER B :-.

PROGRAMMABLE
INTERRUPT
CONTROLLER

MAX COUNT
REGISTER A
CONTROL REGISTERS

CONTROL,]
REGISTERS

.J

16·BIT
COUNT REGISTER

{'
INTERNAL BUS

U

J
SRDY
ARDY
TEST
HOLD
tiLDA

liES
RESET

-

......

r

U

.--

DRQO
DRQl

PROGRAMMABLE
DMAUNIT
1

o

2O·BIT
SOURCE POINTERS

CHIP-SELECT
UNIT

..
:::
... ..
-

t

TMR OUT 1 TMR OUT 0

INn
NTI

BUS INTERFACE
UNIT

~

I&-BIT
SEGMENT
REGISTERS
PROGRAMMABLE
CONTROL
REGISTERS

&-BYTE
PREFETCH
QUEUE

I I

1-1

DEN
LOCK

DTIFI

llLH

RD
BHE/S7

II

I

2O·BIT
DESTINATION
POINTERS
16·BIT
TRANSFER COUNT

Il

CONTROL
REGISTERS

u!sl !.L

PCS6IA2

ADO-' AI6/S3AD15
AI91S6

LCS

PCS5IAI

Figure 1. 80186 Block Diagram
3-544

210973-003

inter

2.
2.1

AP-186

OVERVIEW OF THE 80186
The CPU

The 80186 CPU shares a common base architecture
with the 8086, 8088 and 80286. It is completely object
code compatible with the 8086/88. This architecture
features four 16-bit general purpose registers (AX,BX,
CX,DX) which may be used as operands in most arithmetic operations in either 8 or 16 bit units. It also features four 16-bit "pointer" registers (SI,DI,BP,SP)
which may be used both in arithmetic operations and in
accessing memory based variables. Four 16-bit segment
registers (CS,DS,SS,ES) are provided' allowing simple
memory partitioning to aid construction of modular programs. Finally, it has a 16-bit instruction pointer and a
16-bit status register.
Physical memory addresses are generated by the 80186
identically to the 8086. The 16-bit segment value is left
shifted 4 bits and then is added to an offset value which
is derived from combinations of the pointer registers, the
instruction pointer, and immediate values (see Figure
2). Any carry out of this addition is ignored. The result
of this addition is a 20-bit physical address which is presented to the system memory.
The 80186 has a 16-bit ALU which performs 8 or 16-bit
arithmetic and logical operations. It provides for data
movement among registers, memory and I/O space. In
addition, the CPU allows for high speed data transfer
from one area of memory to another using string move
instructions, and to or from an I/O port and memory using block I/O instructions. Finally, the CPU provides a

wealth of conditional branch and other control
instructions .
. In the 80186, as in the 8086, instruction fetching and instruction execution are performed by separate units: the
bus interface unit and the execution unit, respectively.
The 80186 also has a 6-byte prefetch queue as does the
8086. The 80188 has a 4-byte prefetch queue as does the
8088. As a program is executing, opcodes are fetched
from memory by the bus interface unit and placed in this
queue. Whenever the execution unit requires another instruction, it takes it out of the queue. Effective processor
throughput is increased by adding this queue, since the
bus interface unit may continue to fetch instructions
while the execution unit executes a long instruction.
Then, when the CPU completes this instruction, it does
not have to wait for another instruction to be fetched
from memory.

2.2

80186 CPU Enhancements

Although the 80186 is completely object code compatible with the 8086, most of the 8086 instructions require
fewer clock cycles to execute on the 80186 than on the
8086 because of hardware enhancements in the bus interface unit and the execution unit. In addition, the
80186 provides many new instructions which simplify
assembly language programming, enhance the performance of high level language implementations, and reduce object code sizes for the 80186. These new
instructions are also included in the 80286. A complete
description of the architecture and instruction execution
of the 80186 can be found in volume I of the
iAPX86/186 users manual. The algorithms for the new
instructions are also given in appendix H of this note.

\

SEGMENT VALUE

I'
I

-I

16 BITS

I"

'I

16 BITS

I

+
OFFSET

PHYSICAL ADDRESS

=

I

I·
Figure 2.

20 BITS

I
-I

Physical Address GeDeration in the 80186

3-545

210973-003

AP-186

2.3

DMA Unit

The 80186 includes a DMA unit which provides two
high speed DMA channels. This DMA unit will perform
transfers to or from any combination of I/O space and
memory space in either byte or word units. Every DMA
cycle requires two to four bus cycles, one or two to fetch
the data to an internal register, and one or two to deposit
the data. This allows word data to be located on odd
boundaries, or byte data to be moved from odd locations
to even locations. This is normally difficult, since odd
data bytes are transferred on the upper 8 data bits of the
l6-bit data bus, while even data bytes are transferred on
the lower 8 data bits of the data bus.
Each DMA channel maintains independent 20-bit
source and destination pointers which are used to access
the source and destination of the data transferred. Each
of these pointers may independently address either I/O
or memory space. After each DMA cycle, the pointers
may be independently incremented, decremented, or
maintained constant. Each DMA channel also.maintains a transfer count which may be used to terminate a
series of DMA transfers after a pre-programmed number of transfers.
'

2.4 Timers
The 80186 includes a timer unit which contains 3 independent J6-bit timer/counters. Two of these timers can
be used to count external events, to provide waveforms
derived from either the CPU clock or an external clock
of any duty cycle, or to interrupt th'e CPU after a specified number of timer "events." The third timer counts
only CPU clocks and can be used to interrupt the CPU
after a programmable number of CPU clocks, to give a
count pulse to either or both of the other two timers after
a programmable number of CPU clocks, or to give a
DMA request pulse to the integrated DMA unit after a
programmable number of CPU clocks.

2.5

Interrupt Controller

The 80186 includes an interrupt controller. This controller arbitrates interrupt requests between all internal and
external sources. It can be directly cascaded as the master to two external 8259A interrupt controllers. In addition, it can be configured as a slave controller to an
external interrupt controller to allow complete compatibility with an 80130, 80150, and the iRMX@ 86 operating system.

2.6 Clock Generator
The 80186 includes a clock generator and crystal oscillator. The crystal oscillator can be used with a parallel resonant, fundamental mode crystal at 2X the desired CPU
clock speed (i.e., 16 MHz for an 8 MHz 80186), or with
an external oscillator also at 2X the CPU clock. The output of the oscillator is internally divided by two to provide the 50% duty cycle CPU clock from which all

80186 system timing derives. The CPU clock is externally available, and all timing parameters are referenced to
this externally available signal. The clock generator also
provides ready synchronization for the prOCessor.

2.7 Chip Select and Ready Generation Unit
The 80186 includes integrated chip select logic which
can be used to enable memory or peripheral devices. Six
output lines are used for memory addressing and seven
output lines are used for peripheral addressing.
The memory chip select lines are split into 3 groups for
sliparately addressing the major memory areas in a typical 8086 system: upper memory for reset ROM, lower
memory for interrupt vectors, and mid-range memory
for program memory. The size of each of these regions is
user programmable. The starting location and ending
location of lower memory and upper memory are fixed
at OOOOOH and FFFFFH respectively; the starting location of the mid-range memory is user programmable.
Each Of the seven peripheral select lines address one of
seven contiguous 128 byte blocks above a programmable
base address. This base address can be located in either
memory or I/O space in order that peripheral devices
may be I/O or memory mapped.
Each of the programmed chip select areas has associated
with it a set of programmable ready bits. These ready
bits control an integrated wait state generator. This allows a programmable number of wait states (0 to' 3) to
be automatically inserted whenever an access is made to
the area of memory associated with the chip select area.
In addition, each set of ready bits includes a bit which
determines whether the external ready signals (ARDY
and SRDY) will be used, or whether they will be ignored
(i.e., the bus cycle will terminate even though a ready
has not been returned on the external pins). There are 5
total sets of ready bits which allow independent ready
generation for each of upper memory, lower memory,
mid-range memory, peripheral devices 0-3 and peripheral devices 4-6.

2.8

Integrated Peripheral AcceSSing

The integrated peripheral and chip select circuitry is
controlled by sets of l6-bit registers accessed using standard input, output, or memory access instructions.
These peripheral control registers are all located within
a 256 byte block which can be placed in either memory
or I/O ,space. Because they are accessed exactly as if
they were external devices, no new instruction types are
required to access and control the integrated peripheralso For more information concerning the interfacing
and accessing of the integrated 80186 peripherals not in' cluded in this note, please consult the 80186 data sheet,
or volume II of the iAPX86/186'users manual.

3-546

210973-003

AP·186

3.

USING THE 80186

3.1
3.1.1

Bus Interfacing to the 80186

~1

OVERVIEW

The 80186 bus structure is very similar to the 8086 bus
structure. It includes a multiplexed address/data bus,
along with various control and status lines (see Table 1).
Each bus cycle requires a minimum of 4 CPU clock cy·
cles along with any number of wait states required to accommodate the speed access limitations of external
memory or peripheral devices. The bus cycles initiated
by the 80186 CPU are identical to the bus cycles initiated by the 80186 integrated DMA unit.

"""1---'

I
I
I

In the following discussion, all timing values given are
for an 8 MHz 80186. Future speed selections of the part
may have different values for the various parameters.
Each clock cycle of the 80186 bus cycle is called a "T"
state, and are numbered sequentially T I, T 2, T 3, Tw and
T 4 • Additional idle T states (T i ) can occur between T4
and TI when the processor requires no bus activity (instruction fetches, memory writes, I/O reads, etc.). The
ready signals control the number or wait states (Tw) inserted in each bus cycle. This number can vary from 0 to
positive infinity.

Figure 3.

01

02

(LOW

(HIGH

PHASE)

PHASE)

L

T-state in the 80186

The beginning of a T state is signaled by a high to low
transition of the CPU clock. Each T state is divided into
two phases, phase 1 (or the low phase) and phase 2 (or
the high phase) which occur during the low and high levels of the CPU clock respectively (see Figure 3).
Different types of bus activity occur for all of the Tstates (see Figure 4). Address generation information
occurs during T I, data generation during T 2, T 3, Tw and

1,or
• T3

T,

T.

.T.

LINES

DATA
LINES
ADDRESS!

"T----n.~~~~ y----r-----+!--.J

CONTROL

..,-----1"""---__n.

SIGNALS

(RD,WR)

I'

Figure 4.

Example Bus Cycle of the 80186

Table 1. 80186 Bus Signals
Function

Signal Name

address/data
address/status
co-processor control
local bus arbitration
local bus control
multi-master bus
ready (wait) interface
status information

ADO-AD15
A 16/S3-A 19-56,BHE/S7
TEST
HOLD,HLDA
ALE,RD,WR,DT /R,i5EN
LOCK
SRDY,ARDY
SO-S2
3-547

210873-003

AP-186

T 4' The beginning of a bus cycle is signaled by the status
lines of the processor going from a passive state (all
high) to an active state in the middle of the T-state immediately before TI (either a T4 or a TJ Because information concerning an impending bus cycle occurs
during the T-state immediately before the first T-state of
the cycle itself, two different types of T 4 and T; can be
generated: one where the T state is immediately followed by a bus cycle, and one where the T state is immediatly followed by an idle T state.
During the first type of T 4 or T;, status information concerning the impending bus cycle is generated for the bus
cycle immediately to follow. This information will be
available no later than t CHSV (55ns) after the low-tohigh transition of the 80186 clock in the middle of the T
state. During the second type of T 4 or T; the status outputs remain inactive (high), since no bus cycle is to be
started. This means that the decision per the nature of a
T 4 or T; state (Le., whether it is immediately followed by
a T; or a T I) is decided at the beginning of the T-state
immediately preceding the T4 or T; (see Figure 5). This
has consequences for the bus latency time (see section
3.3.2 on bus latency).
3.1.2

PHYSICAL ADDRESS GENERATION

Physical addresses are generated by the 80186 during T 1
of a bus cycle. Since the address and data lines are multiplexed on the same set of pins, addresses must be

latched duri~g TI if they are required to remain stable
for the duration of the bus cycle. To facilitate latching of
the physical address, the 80186 generates an active high
ALE (Address Latch Enable) signal which can be directly connected to a transparent latch's strobe input.
Figure 6 illustrates the physical address generation parameters of the 80186. Addresses are guaranteed valid
no greater then tCLAV (44ns) after the beginning ofT 1,
and remain valid at least tCLAX (IOns) after the end of
T I' The ALE signal is driven high in the middle of the T
state (either T4 or T;) immediately preceding TI and is
driven low in the middle of T I' no sooner than t AVAL (30
ns) after addresses become valid. This parameter
(tAVAL ) is required to satisfy the address latch set-up
times of address valid until strobe inactive. Addresses
remain stable on the address/data bus at least tLLAX (30
ns) after ALE goes inactive to satisfy address latch hold
times of strobe inactive to address invalid.
Because ALE goes high long before addresses become
valid, the delay through the address latches will be chiefly the propagation delay through the latch rather than
the delay from the latch strobe, which is typically longer
than the propagation delay. For the Intel 8282 latch, this
parameter is t,vov> the input valid to output valid'tlelay
when strobe is held active (high). Note that the 80186
drives ALE high one full clock phase earlier than the
8086 or the 8288 bus controller, and keeps it high
throughout the 8086 or 8288 ALE high time (Le., the
80186 ALE pulse is wider).

T. or

Tw

,1

T.

DeciSion No bus actIVity required,
Idle bus cycles will be Inserted

I
CLOCK
OUT
STATUS

ACTIVE
STATUS

INFO

I

1
1

I

'I
T.or

1

Tw

I
I

INACTIVE
STATUS
,T.

T,

Dec!s'On Another bus cycle Immeecome queue status
outputs, reflecting the status of the internal prefetch
queue during each clock cycle. These signals are provided to allow a processor extension (such as the Intel
8087 floating point processor) to track execution of instructions within the 80186. The interpretation of QSO
(ALE) and QSl (WR) are given in Table 2. These signals change on the high-to-Iow clock transition, one
clock phase earlier than on the 8086. Note that since execution unit operation is independent of bus interface
unit operation, queue status lines may change in any T
state.
Table 2.
QS1

QSO

0

no operation

1

first byte of instruction taken
from queue

1

0

queue was reinitialized

1

I

subsequent byte of instruction
taken from queue

Since the ALE, RD, and WR signals are not directly
available from the 80186 when it is configured in queue
status mode, these signals must be derived from the status lines SO-S2 using an external 8288 bus controller
(see below). To prevent the 80186 from accidentally entering queue status mode during reset, the RD line is internally provided with a weak pullup device. RD is the
ONLY three-state or input pin on the 80186 which is
supplied with a pullup or pUlldown device.
3.1.6.3

Status Lines

The 80186 provides 3 status outputs which are used to
indicate the type of bus cycle currently being executed.
These signals go from an inactive state (all high) to one
of seven possible active states during the T state immediately preceding T] of a bus cycle (see Figure 5). The possible status line encodings and their interpretations are
given in Table 3. The stafus lines are driven to their inactive state in the T state (T3 or Tw) immediately preceding T 4 of the current bus cycle.

8288

SO'52
SIGNALS

CLOCK
OUT

ClK

Figure 14.

Table 3.

Interpretation

0

/

BUS CONTROL

80186 Queue Status

0

,3

SO-52

80186/8288 Bus Controller
Interconnection

80186 Status Line Interpretation

S2

S1

SIJ

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Operation

interrupt acknowledge
read I/O
write I/O
halt
instruction fetch
read memory
write memory
passive

The 80186 provides two additional status signals: S6
and S7. S7 is equivalent to BHE (see section 3.1.2) and
appears on the same pin as BHE. BHE/S7 changes
state, reflecting the bus cycle about to b~ run, in the middle of the T state (T 4 or T) immediately preceding T] of
the bus cycle. This means that BHE/S7 does not need to
be latched, i.e., it may be used directly as the BHE signal. S6 provides information concerning the unit generating the bus cycle. It is time multiplexed with A19, and
is available during T 2' T 3' T 4 and Tw' In the 8086 family,
all central processors (e.g., the 8086, 8088 and 8087)
, drive this line low, while all I/O processors (e.g., 8089)
drive this line high during their respective bus cycles.
Following this scheme, the 80186 drives this line low
whenever the bus cycle is generated by the 80186 CPU,
but drives it high when the bus cycle is generated by the
integrated 80186 DMA unit. This allows external devices to distinguish between bus cycles fetching data for
the CPU from those transfering data for the DMA unit.

The status lines may be directly connected to an 8288
bus controller, which can be used to provide local bus
control signals or multi-bus control signals (see Figure
14). Use of the 8288 bus controller does not preclude the
'use of the 80186 generated RD, WR and ALE signals,
however. The 80186 directly generated signals may be
used to provide local bus control signals, while an 8288 is
used to provide multi-bus control signals, for example.

3-554

Three other status signals are available on the 8086 but
not on the 80186. They are S3, S4, and S5. Taken together, S3 and S4 indicate the segment register from
which the current physical address derives. S5 indicates
the state ofthe interrupt flip-flop. On the 80186, these
signals will ALWAYS be low.
3.1.6.4

TEST and LOCK

Finally, the 80186 provides a TEST input and a LOCK
output. The TEST input is used in conjunction with the
210973-003

AP-186

processor WAIT instruction. It is typically driven by a
processor extension (like the 8087) to indicate whether
it is busy. Then, by executing the WAIT (or FWAIT) instruction, the central processor may be forced to temporarily suspend program execution until the processor
extension indicates that it is idle by driving the TEST
line low.

80186 CPU has executed a HLT instruction. It differs
from a normal bus cycle in two important ways.

The LOCK output is driven low whenever the data cycles of a LOCKED instruction are executed. A
LOCKED instruction is generated whenever the LOCK
prefix occurs immediately before an instruction. The
LOCK prefix is active for the single instruction immediately following the LOCK prefix. This signal is used to
indicate to a bus arbiter (e.g., the 8289) that a series of
locked data transfers is occurring. The bus arbiter
should under no circumstances release the bus while
locked transfers are occurring. The 80186 will not recognize a bus HOLD, nor will it allow DMA cycles to be
run by the integrated DMA controller during locked
data transfers. LOCKED transfers are used in multiprocessor systems to access memory based semaphore
variables which control access to shared system resources (see AP-I06, "Multiprogramming with the
iAPX88 and iAPX86 Microsystems," by George Alexy
(Sept. 1980».
On the 80186, the LOCK signal will go active during T}
of the first DATA cycle of the locked transfer. It is driven inactive 3 T-states after the beginning of the last
DATA cycle of the locked transfer. On the 8086, the
LOCK signal is activated immediately after the LOCK
prefix is executed. The LOCK prefix may be executed
well before the processor is prepared to perform the
locked data transfer. This has the unfortunate consequence of activating the LOCK signal before the first
LOCKED data cycle is performed. Since LOCK is active before the processor requires the bus for the data
transfer, opcode pre-fetching can be LOCKED. However, since the 80186 does not activate the LOCK signal
until the processor is ready to actually perform the
locked transfer, locked pre-fetching will not occur with
the 80186.
Note that the LOCK signal does not remain active until
the ehd of the last data cycle of the locked transfer. This
may cause problems in some systems if, for example, the
processor requests memory access from a dual ported
RAM array and is denied immediate access (because of
a DRAM refresh cycle, for example). When the processor finally is able to gain access to the RAM array, it
may have already dropped its LOCK signal, thus allowing the dual port controller to give the other port access
to the RAM array instead. An example circuit which
can be used to hold LOCK active until a RDY has been
received by the 80186 is shown in Figure 15.
3.1.7 HALT TIMING
A HALT bus cycle is used to signal the world that the

b-::-_-L.Jb--e..--- LOCK

Figure 15. Circuit Holding Lock Active Until
RUdy is Returned
The first way in which a HALT bus cycle differs from a
normal bus cycle is tha t since the processor is entering a
halted state, none of the control lines (RD or WR) will
be driven active. Address and data information will not
be driven by the processor, and no data will be returned.
The second way a HALT bus cycle differs from a normal
bus cycle is that the SO-S2 status lines go to their passive
state (all high) during T 2 of the bus cycle, well before
they go to their passive state during a normal bus cycle.
'Like a normal bus cycle, however, ALE is driven active.
Since no valid address information is present, the information strobed into the address latches should be ignored. This ALE pulse can be used, however, to latch the
HALT status from the SO-S2 status lines.
The processor being halted does not interfere with the
operation of any of the 80186 integrated peripheral
units. This means that if a DMA transfer is pending
while the processor is halted, the bus cycles associated
with the DMA transfer will run. In fact, DMA latency
time will improve while the processor is halted because
the DMA unit will not be contending with the processor
for access to the 80186 bus (see section 4.4.1).
3.1.8

8288 AND 8289 INTERFACING

The 8288 and 8289 are the bus controller and multimaster bus arbitration devices used with the 8086 and
8088. Because the 80186 bus is similar to the 8086 bus,
they can be directly used with the 80186. Figure 16
shows an 80186 interconnection to these two devices.
The 8288 bus co!!!roller generates control signals (RD,
WR, ALE, DT fR, DEN, etc.) for an 8086 maximum
mode system. It derives its information by decoding status lines SO-S2 of the processor. Because the 80186 and
the 8086 drive the same status information on these
lines, the 80186 can be directly connected to the 8288
just as in an 8086 system. Using the 8288 with the 80186
does not prevent using the 80186 control signals directly.
Many systems require both local bus control signals and
system bus control signals. In this type of system, the
80186 lines could be used as the local signals, with the

3-555

210973-003

Ap·186

has acquired control of the bus, then it allows the processor to drive address, data and control information onto
the system bus. The system determines when it requires
system bus resources by an address decode. Whenever
the address being driven coincides with the address of an
on-board resource, the system bus is not required and
thus will not be requested. The circuit shown factors the
80186 chip select lines to determine when the system bus
should be requested, or when the 80186 request can be
satisfied using a local resource.

TO MULTI-MASTER BUS
ADDRESS LATCHES.
DATA BUFFERS

80186
8288
Slj-t--_.j SOALE
S2

S2

DEN

DT/R
CLOCKOUT H - f - . j CLK

3.1.9

READY INTERFACING

The 80186 provides two ready lines, a synchronous
ready (SRDY) line and an asynchronous ready
(ARDY) line. These lines signal the processor to insert
wait states (Tw) into a CPU bus cycle. This allows slower
devices to respond to CPU service requests (reads or
writes). Wait states will only be inserted when both
ARDYand SRDY are low, i.e., only one of ARDY or
SRDY need be active to terminate a bus cycle. Any
number of wait states may be inserted into a bus cycle.
The 80186 will ignore the RDY inputs during any accesses·to the integrated peripheral registers, and to any
area where the chip select ready bits indicate that the
external ready should be ignored.

Figure 16. 80186/8288/8289 Interconnection
8288 lines used as the system signals. Note that in an
80186 system, the 8288 generated ALE pulse occurs later than that of the 80186 itself. In many multimaster
bus systems, the 8288 ALE pulse should be used to
strobe the addresses into the system bus address latches
to insure that the address hold times are met.

The timing required by the two RDY lines is different.
The ARDY line is meant to be used with asynchronous
ready inputs. Thus, inputs to this line will be internally
synchronized to the CPU clock before being presented to
the processor. The synchronization circuitry used with
the ARD Y line is shown in Figure 17. Figure 18A and
18B show valid and invalid transitions of the ARDY line
(and subsequent wait state insertion). The first flip-flop
is used to "resolve" the asynchronous transition of the
ARDY line. It will achieve a definite level (either high
or low) before its output is latched into the second flip-

The 8289 bus arbiter arbitrates the use of a multi-master system bus among various devices each of which can
become theJ!.uLmaster. This component also decodes
status lines SO-S2 of the processor directly to determine
when the system bus is required. When the system bus is
required, the 8289 forces the processor to wait until it
ARDY
INPUT , - - - - - - - - 80186

---------;-1

.
I
I
I

D

I
I

---IL...J----

Q ...,(i)",,1

TO BUS
INTERFACE
UNIT

I c c

I

CPU

ILCLOCK________ _

_

_ _ ...J

FROM SYNCHRONOUS
READY

'1 . Asynchronous Resolution Flip Flop
2. Ready Latch Flip Flop
NOTE: The second flip-flop is not actually in the circuit. It is drawn here only
to show the functional equivalent of the interface to the BIU.

Figure 17.' Asynchronous Ready Circuitry 9f the 80186
3-556

210973-003

AP·186

flop for presentation to the CPU. When latched high, it
allows the ~el present on the AROY line to pass directly to the CPU; when latched low, it forces not ready to be
presented to the CPU (see Appendix B for 80186 synchronizer information).

by any inactive going transition of the AROY line. The
reason AROY is implemented in this manner is to allow
a slow device the greatest amount of time to respond
with a not ready after it has been selected. In a normally
ready system, a slow device must respond with a not
ready quickly after it has been selected to prevent the
processor from continuing and accessing invalid data
from the slow device. By implementing AROY in the
above fashion, the slow device has an additional clock
phase to respond with a not ready.

With this scheme, notice that only the active going edge
of the AROY signal is synchronized. Once the synchronization flip-flop has sampled high, the AROY input directly drives the ROY flip-flop. Since inputs to this
ROY flip-flop must satisfy certain setup and hold times,
it is important that these setup and hold times (tARYLCL
= 35ns and tCHARYX = IS ns respectively) be satisfied

If ROY is sampled active into the ROY flip-flop at the
beginning of T3 or Tw (meaning that AROY was sam-

1. No set-up or hold times required
2. tcLARvx: Clock low to ARDY inactive (ARDY active hold time) = 15 ns min

:

T,

T.

:

:

_ Tw

:

T.

OUT
CLOCK~

CD

ARDY

g?g?

.I.I.I.l.I.l.l.l.l.l.l.l.lL----'~WJJII

1. tARYHCH: ~RDY valid until clock high (ARDY inactive set-up time to clock
high) = 20 ns min
2. No set-up or hold time required ONLY if Gl is guaranteed
3. tcLARYX: Clock low to ARDY inactive (ARDY active hold time) = 15 ns min

~

:

~

:

~

:

~

CLOCK~
OUT
CD
0~

ARDY
.w.w.l.W.l.l..I.I.I.L...---I

1. tARYLCL: ARDY low to clock low (ARDY inactive set-up time to clock low) =
35 ns min
must be satisfied since synchronizing FLIP-FLOP has sampled
active
2. tARYHCH: ARDY high to clock high (ARDY active set-up time) = 20 ns min
must be satisfied ONLY to guarantee recognition at the next clock
(Le. to guarantee synchronizing FLIP-FLOP will sample ARDY
active)
3. tCLARYX: Clock low to ARDY inactive (ARDY active hold time) = ~ 5 ns

Figure 18A.

Valid ARDY Transitions

3-557

210973-003

Ap·186

I

CLOCK
OUT

T,

T.

~
I

I

I
I
I

I

ARDY

I

I
I
I

I
,
I

I
I
I

I

I

I

I

CD LESS THAN 35 ns

CLOCK
OUT
ARDY

~
0¥0~

I
I
I

I
I
I

I
I
I

I
I
I

1. Less than 20 ns
2. Less than 35 ns

Figure 18B. Invalid ARDY Transitions
pled high into the synchronization flip-flop in the middle
of a T state, and has remained high until the beginning
of the next T state), that T state will be immediately followed by T 4 • If RDY is sampled low into the RDY flipflop at the beginning of T3 or Tw (meaning that either
ARDY was sampled low into the synchronization flipflop OR that ARDY was sampled high into the synchronization flip-flop, but has subsequently changed to low
before the ARDY setup time) that T state will be imme~iately followed by a wait state (Tw)' Any asynchronous
transition on the ARDY line not occurring during the
above times, that is, when the processor is not "looking
at" the ready lines, will not cause CPU malfunction.

Again, for ARDY to force wait states to be inserted,
SRDY must be driven low, since they are internally
ORed together to form the processor RDY signaL·
The synchronous ready (SRDY) line requires that ALL
transitions on this line during T 2' T 3 or Tw satisfy a certain setup and hold time (tSRYCL = 35 ns and t cLSRY =
15 ns respectively). If these requirements are not met,
the CPU will not function properly. Valid transitions on
this line, and subsequent wait state insertion is shown in
Figure 19. The processor looks at this line at the beginning of each T 3 and Tw' If the line is sampled active at
the beginning of either of these two cycles, that cycle will
I
I

T,

CLOCK
OUT
SRDY

~
~

1. Decision: Not ready. T-state will be followed by a wait state
2. Decision: Ready. T-state will not be followed by a wait state
3. tSRYCl: Synchronous ready stable until clock low (SRDY set-up
time) = 35 ns min
4. tClSRY:
Clock low until synchronous ready transition (SRDY hold time) =
15 ns min

Figure 19. Valid SRDY transitions on the 80186
3-558

210973-003

AP-186

of each bus cycle used for instruction fetching, since
each fetch will access two bytes of information. It is also
good programming practice to locate all word data at
even locations, so that both bytes of the word may be accessed in a single bus cycle (see discussion on data bus
interfacing for further information, section 3.1.3 of this
note).

be immediately followed by T 4' On the other hand, if the
line is sampled inactive at the beginning of either of
these two cycles, that cycle will be followed by a Tw' Any
asynchronous transition on the SRDY line not occurring
at the beginning ofT3 or Two that is, when the processor
is not "looking at" the ready lines will not cause CPU
malfunction.

3.1.10

Although the amount of bus utilization, i.e., the percentage of bus time used by the 80186 for instruction fetching and execution required for top performance will vary
considera bly from one program to another, a typical instruction mix on the 80186 will require greater bus utilization than the 8086. This is caused by the higher
performance execution unit requiring instructions from
the prefetch queue at a greater rate. This also means
that the effect of wait states is more pronounced in an
80186 system than iIi an 8086 system. In all but a few
cases, however, the performance degradation incurred
by adding a wait state is less than might be expected because instruction fetching and execution are performed
by separate units.

BUS PERFORMANCE ISSUES

Bus cycles occur sequentially, but do not necessarily
come immediately one after another, that is the bus may
remain idle for several T states (T) between each bus
access initiated by the 80186. This occurs whenever the
80186 internal queue is full and no read/write cycles are
being requested by the execution unit or integrated
DMA unit. The reader should recall that a separate
unit, the bus interface unit, fetches opcodes (including
immediate data) from memory; while the execution unit
actually executes the pre-fetched instructions. The number of clock cycles required to execute an 80186 instruction vary from 2 clock cycles for a register to register
move to 67 clock cycles for an integer divide.

3.2

If a program contains many long instructions, program
execution will be CPU limited, that is, the instruction
queue will be constantly filled. Thus, the execution unit
does not need to wait for an instruction to be fetched. If a
program contains mainly short instructions or data
move instructions, the execution will be bus limited.
Here, the execution unit will be required to wait often
for an instruction to be fetched before it continues its operation. Programs illustrating this effect and performance degradation of each with the addition of wait
states are given in appendix G.

The addresses are latched using the address generation
circuit shown earlier. Note that the AO line ,of each
EPROM is connected to the Al address line from the
80186, NOT the AO line. Remember, AO only signals a
data transfer on the lower 8 bits of the 16-bit data bus!
The EPROM outputs are connected directly!Q.!he address/data in2!!!§ of the 80186, and the 80186 RD signal
is used as the OE for the EPROMs.

All instruction fetches are word (l6-bit) fetches from
even addresses unless the fetch occurs as a result of a
jump to an odd location. This maximizes the utilization

2764

CE
13
A13
A1

/13

A12

OE

RD

00-07

t
/8

ADO-AD7

/ 8

2764
L.....o. CE
A12

~

AO

/

Example Memory Systems

3.2.1 2764 INTERFACE
With the above knowledge of the 80186 bus, various
memory interfaces may be generated. One of the simplest of these is the example EPROM interface shown in
Figure 20.

I

r-

AO

OE
00-07

,

AD8-AD15

Figure 20.

Example 2764/80186 Interface

3-559

210973-003

inter

AP·186

The chip enable of the EPROM is driven directly by the
chip select output of the 80186 (see section 8). In this
configuration, the access time calculation for the
EPROMsare:
time from
address: (3 + N)*tcLCL -tcLAV - t Nov(8282) - t evcL
= 375 + (N * 125) - 44 - 30 - 20
= 281 + (N * 125) ns
time from
chip select: (3 + N)*tCLCL - tCLCSV - t evcL
= 375 + (N * 125) - 66 - 20
= 289 + (N * 125) ns
time from
RD (OE): (2 + N)tCLCL - tCLRL - t evcL
= 250 + (N * 125) - 70 - 20
= 160 + '(N * 125) ns

t evcL = 186 data valid input setup time until clock
low time of T 4
tCLCSV

time from clock low in T 1 until chip selects
are valid

tCLRL = time from clock low in T 2 until RD goes low
N

=

number of wait states inserted

Thus, for 0 wait state operation, 250ns EPROMs must
be used. The only significant ~ameter not included
above is tRHAV> the time from RD inactive (high) until
tlle 80186 begins driving address information. This parameter is 85ns, which meets the 2764-25 (250ns speed
selection) output float time of 85ns. If slower EPROMs
are used, a discrete data buffer MUST be inserted between the EPROM data lines and the address/data bus,
since these devices may continue to drive data information on the multiplexed address/data bus when the
80186 begins to drive address information for the next
bus cycle.

where:
tCLAV = time from clock low in Tl until addresses
are valid

3.2.2 2186 INTERFACE
An example interface between the 80186 and 2186
iRAMs is shown in Figure 21. This memory component
is almost an ideal match with the 80186, because of its
large integration, and its not requiring address latching.

t CLCL = clock period of processor
t lVOV = time from input valid of 8282 until output
valid of 8282

CLKOUT
LCS

=

---.;;;::-:---:--r-b----r-'"
,\

BHE

AO

----------------------------+-------------------L-"
-------------------------------L~

CLKOUT --.~---1-"\..\___..r__
WR
2186

RD

2186

CE

CE

WE

WE

OE

OE

AO-A12

AO,A12

4.7K

ARDY

ADO- ___________________________________AD~1~3~~______~~~----_+~~----~
AD15

Figure 21.

Example 2186/80186 Interface

3-560

210973-003

Ap·186

The 2186 internally is a dynamic RAM integrated with
refresh and control circuitry. It operates in two modes,
pulse mode and late cycle mode. Pulse mode is entered if
the CE signal is low to the device a maximum of 130ns,
and requires the command input (RO or WE) to go active within 90ns after CEo Because of these requirements, interfacing the 80186 to the 2186 in pulse mode
would be difficult. Instead, the late cycle mode is used.
This affords a much simpler interface with no loss of
performance. The iRAM automatically selects between
these modes by the nature of the control signals.
The 2186 is a leading edge triggered device. This means
that address and data information are strobed into the
device on the active going (high to lo~..transition of the
command signal. This requires both CE and WR be deliyed until the address and data driven by the 80186 are
guaranteed stable. Figure 21 shows a simple circuit
which can pe used to perform this function. Note that
ALE CANNOT be used to delay CE if addresses are not
latched externally, because this would violate the address hold time required by the 2186 (30ns).
Because the 2186s are RAMs, data bus enables (BHE
and AO, see previous section) MUST be used to factor
either the chip enables or write enables of the lower and
upper bytes of the 16-bit RAM memory system. If this is
not done, all memory writes, including single byte
writes, will write to both the upper and lower bytes of the
memory system. The exampl~stem shown uses BHE
and AO as factors to the 2186 CEo This may be done, because both of these signals (AO and BHE) are valid
when the address information is valid from the 80186.
The 2186 requires a certain amount of recovery time between its chip enable going inactive and its chip enable
going active insure proper operation. For a "normal" cycle (a read or write), this time is tEHEL = 40ns. This
means that the 80186 chip select lines will go inactive
soon enough at the end of a bus cycle to provide the required recovery time even if two consecutive accesses are
made to the iRAMs. If the 2186 CE is asserted without a
command signal (WE or OE), a "False Memory Cycle"
(FMC) will be generated. Whenever a FMC is generated, the recovery time is much longer; another memory
cycle must not be initiated for 200ns. As a result, if the
memory system will generate FMCs, CE must be taken
away in the middle of the T state (T 3 or Tw) immediately
preceding T 4 to insure two consecutive cycles to the
iRAM will not violate this parameter. Status going passive (all high) can be used for this purpose. These lines
will all go high during the first phase of the next to last T
state (either T3 or Tw) of a bus cycle (see section 3.1.5).
Finally, since it is a dynamic device, the 2186 requires
refresh cycles to maintain data integrity. The circuitry
to generate these refresh cycles is integrated within the
2186. Because of this, the 2186 has a ready line which is
used to suspend processor operation if a processor RAM
3-561

access coincides with an internally generated refresh cycle. This is an open collector output, allowing many of
them to be wire-OR'ed together, since more than one device may be accessed at at time. These lines are also normally ready, which means that they will be high
whenever the 2186 is not being accessed, i.e., they will
only be driven low if a processor request coincides with
an internal refresh cycle. Thus, the ready lines from the
iRAM must be factored into the 80186 ROY circuit
only during accesses to the iRAM itself. Since the 2186
refresh logic operates asynchronously to the 80186, this
ROY line must be synchronized for proper operation
with the 80186, either by the integrated ready synchronizer or by an external circuit. The example circuit uses
the integrated synchronizer associated with the AROY
processor input.
The ready lines of the 2186 are active unless a processor
access coincides with an internal refresh cycle. These
lines must go inactive soon enough after a cycle is requested to insert wait states into the data c~. The
2186 will drive this line low within 50ns after CE is received, which is early enough to force the 80186 to insert
wait states if they are required. The primary concern
here is that the AROY line be driven not active before
its setup time in the middle of T 2' This is required by the
nature of the asynchronous ready synchronization circuitry of the 80186. Since the ROY pulse of the 2186
may be as narrow as 50ns; if ready was returned after
the first stage of the synchronizer, and subsequently
changed state within the ready setup and hold time of
the high to low going edge of the CPU clock at the end of
T 2, improper operation may occur (see section 3.1.6}.
The example interface shown has a zero wait state RAM
read access time from CE of:
3 * t CLCL - tCLCSV - (TTL delay) - t DvCL
= 375 - 66 - 30 - 20 ns
= 259 ns
where:
t CLCL

=

tCLCSV
t DVCL

=

=

CPU clock cycle time
time from clock low in T 1 until chip selects
are valid
80186 data in setup time before clock low in

T4
The data valid delay from OE active is less than lOOns,
and is therefore not an access time limiter in this interface. Additionally, the 2186 data float time from RO inactive is less than the 85ns 80186 imposed maximum.
The CE generation circuit shown in Figure 21 provides
an address setup time of at least 11 ns, and an address
hold time of at least 35ns (assuming a maximum two
level TTL delay of less than 30ns).
210973-003

Ap·186

Write cycle address setup and hold times an: identical to
the read cycle times. The circuit shown provides at least
Ilns write data setup and -lOOns data hold time from
WE, easily meeting the Ons setup and 40ns hold times
required by the 2186.
For more information concerning 2186 timing and interfacing, please consult the 2186 data sheet, or the application note AP-132, "Designing Memory Systems
with the 8Kx8 iRAM" by John Fallin and William
Righter (June 1982).

3.2.3 8203 DRAM INTERFACE
An example 8203/DRAM interface is shown in Figure
22. The 8203 provides all required DRAM control signals, address multiplexing, and refresh generation. In
this circuit, the 8203 is configured to, interface with 64K
DRAMs.

MCS1
MCSO

J

A17·A1

~

All 8203 cycles are generated off control signals (RD
and WR) provided by the 80186. These signals will not
go active until T 2 of the bus cycle. In addition, since the
8203 clock (generated by the internal crystal oscillator
of the 8203) is asynchronous to the 80186 clock, all
memory requests by the 80186 must be synchronized to
the 8203 before the cycle will be run. To minimize this
synchronization time, the 8203 should be used with the
highest speed crystal that will maintain DRAM compatibility. Even if a 25 MHz crystal is used (the maximum allowed by the 8203) two wait states will be
required by the example circuit when using 150ns
DRAMs with an 8 MHz 80186, three wait states if
200ns DRAMs are used (see timing analysis, Figure
23).
The entire RAM array controlled by the 8203 can be selected by one or a group of the 80 )86 provided chip selects. These chip selects can also be used to insert the
I
wait states required by the interface.

8203
SEL WR
AO'
A16, WE

1~

,

eo

AROY

J

u220
UPPER
BYTE WE

LOWER
BYTEW'E

r-DRAMS,

SACK

.--

220

XACK
RD

1
/..

AOO·AD15

010:15
000·15

8282
~

=n
-

P"- 000·7
i

OE

010·7

I--

P"- I-'- STB

8282
'---

000·7
OE

'-

Figure 22.

STB

010·7

-

Example 8203/DRAM/80186 Interface
3-562

210973-003

AP-186

T,

T,

186 ____-+~,.;;...,
RD
8203

RAS
8203

CAS

--------------"t---___,
------i--------i--......~_+___,

RAM

~~~""~mmmmmmmmmmmmmmmmmmmm""~~'r----+-----------

DATA

~~~~~~~~~~~~~~~~~~~\f---+~---------

LATCH ~""rrri~~mm~""""""~~~mm~""""""~~~r~~-----DATA ~~~~~~~~~~~~"¥~~~~~~~u~_-+______

1. tCLEL: Clock low until read low = 70 ns max
2. tCR: Command active until RAS = 150 ns max'
3. tcc: Command active until CAS = 245 ns max'
4. 'cAC: Access time from CAS = 85 ns max
5. tISOU: Input to output delay = 30 ns max
6. tOVCL: Data valid to clock low (data in set up) = 20 ns min
Total Access Time = 70 + 245 +85 +30 +20 = 450 ns (3.6 T-states)

Figure 23.

CD & ® are 186 specs
® & @ are 8203 specs
@
@

is a 2164A-15 spec
is on 8282 spec

'Assumes 25MHz
8203 operation

8203/2164A-15 Access Time Calculation

Since the 8203 is operating asynchronously to the
80186, the RDY output of the 8203 (used to suspend
processor operation when a processor DRAM request
coincides with a DRAM refresh cycle) must be synchronized to the 80186. The 80186 ARDY line is used to provide the necessary ready synchronization. The 8203
ready outputs operate in a normally not ready mode,
that is, they are only driven active when an 8203 cycle is
being executed, and a refresh cycle is not being run. This
is fundamentally different than the normally ready
mode used.2Y...!!!.e 2186 iRAMs (see previous section).
The 8203 SACK signal is presented to the 80186 only
when the DRAM is being accessed. Notice that the
SACK output of the 8203 is used, rather than the
XACK output. Since the 80186 will insert at least one
full CPU clock cycle between the time RDY is sampled
active, and the time data must be present on the data
bus, using the XACK signal would'insert unnecessary
additional wait states, since it does not indicate ready
until valid data is available from the memory.
For more information about 8203jDRAM interfacing
and timing, please consult the 8203 data sheet, or
AP97A, "Interfacing Dynamic RAM to iAPX86j88

Systems Using the Intel 8202A and 8203" by Brad May
(April 1982).
3.2.4

8207 DRAM INTERFACE

The 8207 advanced dual-port DRAM controller provides a high performance DRAM memory interface
specifically for 80186 or 80286 microcomputer systems.
This controller provides all address multiplexing and
DRAM refresh circuitry. In addition, it synchronizes
and arbitrates memory requests from two different ports
(e.g., an 80186 and a Multibus), allowing the two ports
to share memory. Finally, the 8207 provides a simple interface to the 8206 error detection and correction chip.
The simplest 8207 (and also the highest performance)
interface is shown in Figure 24. This shows the 80186
connected to an 8207 using the 8207 slow cycle, synchronous status interface. In this mode, the 8207 decodes the
type of cycle to be run directly from the status lines of
the 80186. In addition, since the 8207 CLOCKIN is
driven by the CLOCKOUT of the 80186, any performance degradation caused by required memory request
synchronization between the 80186 and the 8207 is not
present. Finally, the entire memory array driven by the

3-563

210973-003

AP-186

8207 may be selected using one or a group of the 80186
memory chip selects, as in the 8203 interface above.

80186

When the 80186 recognizes a bus hold by driving
HLDA high, it will float many of its signals (see Figure
25). ADO - AD15 (address/data 0 - 15) and DEN (data
enable) are floated within tCLAZ (35ns) after the same
clock edge that HLDA is driven active. A16-A19 (addresU6 - 19), RD, WR, BHE (B~Hi.8..h Enable),
DT /R (Data Transmit/Receive) and SO - S2 (status 02) are floated within t CHCZ (45ns) after the clock edge
immediately before the clock edge on which HLDA
comes active.

6207

ClKOUT

ClK

so

WR

Sf

RD

S2

+5

PCTC

U

PCTl

PE

lMCS

AACK
SRDY

-4

CLOCK

I

T.OR T,

OUT

HOLD

--....:....-----,''-::+------"---

HlDA

--";---1'-/0---""

Figure 24. 80186/8207/DRAM Interface
The 8207 AACK signal may be used to generate a synchronous ready signal to the 80186 in the above interface. Since dynamic memory periodically requires
refreshing, 80186 access cycles may occur simultaneously with an 8207 generated refresh cycle. When this
occurs, the 8207 will hold the AACK line high until the
processor initiated access is run (note, the sense of this
line is reversed with respect to the 80186 SRDY input).
This. signal should be factored with the DRAM (8207)
select input and used to drive the SRDY line of the
80186. Remember that only one of SRDY and ARDY
needs to be active for a bus cycle to be terminated. If
asynchronous devices (e.g., a Multibus interface) are
connected to the ARDY line with the 8207 connected to
the SRDY line, care must be taken in design of the ready
circuit such that only one of the ROY lines is driven active at a time to prevent premature termination of the
bus cycle.

3.3

HOLD/HLDA Interface

The 80186 employs a HOLD/HLDA bus exchange protocol. This protocol allows other asynchronous bus master devices (i.e., ones which drive address, data, and
control information on the bus) to gain control of the bus
to perform bus cycles (memory or I/O reads or writes).
3.3.1

AD15-ADO
DEN
A16-A19
RD,WR,BHE

DT/R,SO-S2 _ _-;-_oJ

Figure 25.

In the HOLD/HLDA protocol, a device requiring bus
control (e.g., an external DMA device) raises the
HOLD line. In response to this HOLD request, the
80186 will raise its HLDA line after it has finished its
current bus activity. When the external device is finished
with the bus, it drops its bus HOLD request. The 80186
responds by dropping its HLDA line and resuming bus
operation.

Signal Float/HLDA Timing of tl)e 80186

Only the above mentioned signals are floated during bus
HOLD. Of the signals not floated by the 80186, some
have to do with peripheral functionality (e.g., Tm·rOut).
Many others either directly or indirectly control bus devices. These signals are ALE (Address Latch Enable,
see section 3.1.2) and all the chip select lines (UCS,
LCS, MCSO-3, and PCSO-6). The designer must be
aware that the chip select circuitry does not look at, externally generated addresses (see section 10 for a discussion of the chip select logic). Thus, for memory or
peripheral devices which are addressed by external bus
master devices, discrete chip select and ready generation
logic must be used.
3.3.2

HOLD RESPONSE

--------r------J

HOLD/HLDA TIMING AND BUS LATENCY

The time required between HOLD going active and the
80186 driving HLDA active is known as bus latency.
Many factors affect this latency, including synchronization delays, bus cycle times, locked transfer times and
interrupt acknowledge cycles.
The HOLD request line is internally synchronized by
the 80186, and may therefore be an asynchronous signal. To guarantee recognition on a certain clock edge, it
must satisfy a certain setup and hold time to the falling

3-564

210973-003

AP-186

cuss ion of 80186 synchronizers). If the bus is idle,
HLDA will follow HOLD by two CPU clock cycles plus
a small amount of setup and propagation delay time.
The first clock cycle synchronizes the input; the second
signals the internal circuitry to initiate a bus hold. (see
Figure 26).

edge of the CPU clc~k A full CPU clock cycle is required for this synchronization, that is, the internal
HOLD signal is not presented to the internal bus arbitration circuitry until one full clock cycle after it is
latched from the HOLD input (see Appendix B for a dis-

T,

Many factors influence the number of clock cycles between a HOLD request and a HLDA. These may make
bus latency longer than the best case shown above. 'Perhaps the most important factor is that the 801\86 will not
relinquish the local bus until the bus is idle. An idle bus
occurs whenever the 80186 is not performing any bus
transfers. As stated in section 3.1.1, when the bus is idle,
the 80186 generates idle T-states. The bus can become
idle only at the end of a bus cycle. Thus, the 80186 can
recognize HOLD only after the end of its current bus cycle. The 80186 will normally insert no T j states between
T 4 and T I of the next bus cycle if it requires any bus activity (e.g., instruction fetches or I/O reads). However,
the 80186 may not have an immediate need for the bus
after a bus cycle, and will insert T j states independent of
the HOLD input (see section 3.1.7).

T,

HOLD

HLDA

1. tHVCL: Hold valid until clock low = 25 ns min
2. tCLHAV: Clock low until HLDA active = 50 ns max

Figure 26.

80186 Idle Bus Hold/HLDA Timing

When the HOLD request is active, the 80186 will be

T,

CLOCK
OUT

HOLD

HLDA
1. DecIsion: No additional internal bus cycles required, idle T-states will be
Inserted after T4
2. Greater than 25 ns (tHvCLl
3. Less than 50 ns (tCLHAVl
4. HOLD request internally synchronized
I
I

CLOCK
OUT

HOLD

T 3 0R
Tw

I
I

T.

I

T,

l

~
I

I

I

I

I

I

HLDA -----------------------------------------1. Decision: Additional internal bus cycles required. no idle T-states will be
Inserted. Hold not active soon enough to force idle T-states
2. Greater than 25 ns (tHVCLl: not required since it will not get recognized
anyway
3. HOLD request internally synchronized

Figure 27.

HOLD/HLDA Timing in the 80186

3-565

210973-003

AP-186

CLOCK
OUT
HOLD

HLDA

,.
I
I

.,
I
I

1. HOLD request internally synchronized
2. Decision: HOLD request active, idle t-states will be inserted at end of
current bus cycle
3. Greater than 25 ns
4. Less than 50 ns
Figure 27A.HOLD/HLDA Timing in the 80186

forced to proceed from T 4 to T j in order that the bus may
be relinquished. HOLD must go active 3 T-states before
the end of a bus cycle to force the 80186 to insert idle Tstates after T 4 (one to synchronize the request, and one
to signal the 80186 that T4 of the bus cycle will be followed by idle T-states, see section 3.1.1). After the bus
cycle has ended, the bus hold will be immediately acknowledged. If, however, the 80186 has already determined that an idle T-state will follow T 4 of the current
bus cycle, HOLD need go active only 2 T-states before
the end of a bus cycle to force the 80186 to relinquish the
bus at the end of the current bus cycle. This is because
the external HOLD request is not required to force the
generation of idle T-states. Figure 27 graphically por,trays the scenarios depicted above,

require thousands of bus cycles, bus latency time will
suffer if they are locked.
The final factor affecting bus latency time is interrupt
acknowledge cycles. When an external interrupt controller is used, or if the integrated interrupt controller is
used in iRMX 86 mode (see section 4.4.1) the 80186 will
run two interrupt acknowledge cycles back to back.
These cycles are automatically "locked" and will never
be separated by any bus HOLD, either internal or external. See section 6.5 on interrupt acknowledge timing for
more information concerning interrupt acknowledge
timing.
3.3.3 COMING OUT OF HOLD
After the 80186 recognizes that the HOLD input has
gone inactive, it will drop its HLDA line in a single
clock. Figure 28 shows this timing. The 80186 will insert
only two T j after HLDA has gone inactive, assuming
that the 80186 has' internal bus cycles to run. During the
last T" status information will go active concerning the
"bus cycle about to be run (see section 3.1.1). If the
80186 has no pending bus activity, it will maintain all
lines floating (high impedance) until the last T j before it
begins its first bus cycle after the HOLD.

An external HOLD has higher priority than both the
80186 CPU or integrated DMA unit. However, an external HOLD will not separate the two cycles needed to
perform a word access when the word accessed is located
at an odd location (see section 3.1.3). In addition, an external HOLD will not separate the two-to-four bus ~y­
cles required to perform a DMA transfer using the
integrated controller. Each of these factors will add additional bus cycle times to the bus latency of the 80186.
Another factor influencing bus latency time is locked
transfers. Whenever a locked transfer is occurring, the
80186 will not recognize external HOLDs (nor will it
recognize internal DMA bus requests). Locked, transfers are programmed by preceding an instruction with
the LOCK prefix. Any transfers generated by such a '
prefixed instruction will be locked, and will not be separated by any external bus requesting device. String instructions may be locked. Since string transfers may

3.4

Differences Between the 8086 bus and
the 80186 Bus

The 80186 bus was defined to be upward compatible
with the 8086 bus. As a result, the 8086 bus interface
components (the 8288 bus controller and the 8289 bus
arbiter) may be used directly with the 80186. There are
a few significant differences between the two processors
which should be considered.

3-566

210973-003

AP-186

CLOCK
OUT

HOLD

~--'"

HLDA ----~----"*"\

ADo-AD15

.........

~----""'~""''''''~'''''''''''''''~''''';-~L-

A18/53-A19/S8
RD,WR,BHE -----:------:-----~-~

--i---_....

DT/R,SO-Sl

1. HOLD internally synchronized
2. Greater than 25 ns
3. Less than 50 ns
4. Lines come out of float only if a bus cycle is pending

Figure 28_ 80188 Coming out of Hold
CPU Duty Cycle and Clock Generator

ther two synchronous ready inputs or two
asynchronous ready inputs as a user strapable
option.

The 80186 employs an integrated clock generator which
provides a 50% duty cycle CPU clock (1/2 of the time it
is high, the other 1/2 of the time it is low). This is different that the 8086, which employs an external clock generator (the 8284A) with a: 33% duty cycle CPU clock
(1/3 of the time it is high, the other 2/3 of the time, it is
low). These differences manifest themselves as follows:

6) The CLOCKOUT (CPU clock output signal)
drive capacity of the 80186 is less than the CPU
clock drive capacity of the 8284A. This means
that not as many high speed devices (e.g.,
Schottky TTL flip-flops) may be connected to
this signal as can be used with the 8284A clock
output.

I) No oscillator output is available from the 80186,
as it is available from the 8284A clock generator.

7) The crystal or external oscillator used by the
80186 is twice the CPU clock frequency, while
the crystal or external oscillator used with the
8284A is three times the CPU clock frequency.

2) The 80186 does not provide a PCLK (50% duty
cycle, 1/2 CPU clock frequency) output as does
the 82&4A.
3) The clock low phase of the 8.0186 is narrower,
and the clock high phase is wider than on the
same speed 8086.

Local Bus Controller and Control Signals

4) The 80186 does not internally factor AEN with
RDY. This means that if both RDY inputs
(ARDY and SRDY) are used, external logic
must be used to prevent the RDY not connected
to a certain device from being driven active during an access to this device (remember, only one
RDY input needs to be active to terminate a bus
cycle, see section 3.1.6).
'

The 80186 simultaneously provides both local bus controller outputs (RD, Wlh..ALE, DEN and DT/R) and
status outputs (SO, SI, S2) for use with the 8288 bus
controller. This is different from the 8086 where the local bus controller outputs (generated only in min mode)
are sacrificed if status outputs ( generated only in max
mode) are desired. These differences will manifest
themselves in 8086 systems and 80186 systems as
follows:

5) The 80186 concurrently provides both a single
asynchronous ready input and a single synchronous ready input, while the 8284A provides ei-

1) Because the 80186 can simultaneously provide
local bus control signals and status outputs,
many systems supporting both a system bus (e.g.,

3-567

210973-003

Ap·186

ample the 82586 Ethernet· controller or 82730 high
performance CRT controller /text coprocessor).

a Multibus®) and a local bus will not require two
separate external bus controllers, that is, the
80186 bus control signals may be used to control
the local bus while the 80186 status signals are
concurrently connected to the 8288 bus controller to drive the control signals of the system bus,

Status Information

The 80186 does not provide S3-S5 status information.
On the 8086, S3 and S4 provide information regarding
the segment register used to generate the physical address of the currently executing bus cycle. S5 provides
information concerning the state of the interrupt enable
flip-flop. These status bits are always low on the 80186.

2) The ALEsignal of the 80186 goes active a clock
phase earlier on the 80186 then on the 8086 or
8288. This minimizes address propagation time
through the address latches, since typically the
delay time through these latches from inputs valid is less than the propagation delay from the
strobe input active.

Status signal S6 is used to indicate whether the current
bus cycle is initiated by either the CPU or a DMA device. Subsequently, it- is always low on the 8086. On the
80186, it is low whenever the current bus cycle is initiated by the 80186 CPU, and is high when the current bus
cycle is initiated by the 80186 integrated DMA unit.

3) The 80186 RD input must be tied low to provide
queue status outputs from the 80186 (see Figure
29). When so s~ped into "queue status mode,"
the ALE and WR outputs provide queue status
information. Notice that this queue status information is available one clock phase earlier from
the 80186 than from the 8086 (see Figure 30).

Bus Drive

The 80186 output drivers will' drive 200pF loads. This is
double that of the 8086 (lOOpF). This allows larger systems to be constructed without the need for bus buffers.
It also means that it is very important to provide good
grounds to the 80186, since its large drivers can discharge its outputs very quickly causing large current
transients on the 80186 ground pins.

80186

aso
aS1

ALE
WR

~
Figure 29.

RD

Misc.

The 80186 does not provide early and late write signals,
as does. the 8288 bus controller. The WR signal generated by the 80186 corresponds to the early write signal of
the 8288. This means that data is not stable on the address/data bus when this signal is driven active.

Generating Queue Status Information
from t,he 80186

HOLD/HLDA vs. RQ/GT

The 80186 also does not provide differentiated I/O and
memory read and write command signals. If these signals are desired, an external 8288 bus controller may be
used, or the S2 signal may be used to synthesize differentiated commands (see section 3.1.4).

As discussed earlier, the 80186.uses a HOLD/HLDA
type of protocol for exchanging bus mastership (like the
8086 in min mode) rather than the RQ/GT protocol
used by the 8086 in max mode. This allows compatiblity
with Intel's the new generation of high performance/
high integration bus master peripheral devices (for ex-

"Ethernet is a registered trademark of Xerox Corp.

CLOCK

OUT
166

...

----....:.----..:........,-h)'-J+:.;;...~ ,.:.....;~~--

as _------~------~~--~r~~----~_;.....,----6066 -----;.-----i-----~,r_--~:"\I'---

as __________

~

______

~

______

~~

_____

1. 80186 changes queue status off falling edge of ClK
2.8086 changes queue status off rising edge of ClK

Figure 30.

80186 and 8086 Queue Status Generation
3-568

210973-003

AP-186

4.

DMA UNIT INTERFACING

Programmable generation of DMA requests by:

The 80186 includes a DMA unit which provides two independent high speed DMA channels. These channels
operate independently of the CPU, and drive all integrated bus interface components (bus controller, chip selects, etc.) exactly as the CPU (see Figure 31). This
means that bus cycles initiated by the DMA unit are exactly the same as bus cycles initiated by the CPU (except that S6 = I during all DMA initiated cycles, see
section 3.1). Thus interfacing with the DMA unit itself
is very simple, since except for the addition of the DMA
request connection, it is exactly the same as interfacing
to the CPU.
EXTERNAL ADDRESS/DATA,
CONTROL, CHIP SELECTS,
ETC.

I) the source of the data
2) the destination of the data
3) timer 2 (see section 5)
4) the DMA unit itself (continuous DMA requests)

4.2

DMA Unit Programming

Each of the two DMA channels contains a number of
registers which are used to control channel operation.
These registers are included in the 80186 integrated peripheral control block (see appendix A). These registers
include the source and destination pointer registers, the
transfer count register and the control register. The layout and interpretation of the bits in these registers is given in Figure 32.

BUS INTERFACE

The 20-bit source and destination pointers allow access
to the complete I Mbyte address space of the 80186, and
that all 20 bits are affected by the auto-increment or
auto-decrement unit of the DMA (Le., the DMA
channels address the full I Mbyte address space of the
80186 as a flat, linear array without segments). When
addressing I/O space, the upper 4 bits of the DMA
pointer registers should be programmed to be O. If they
are not programmed 0, then the programmed value
(greater than 64K in I/O space) will be driven onto the
address bus (an. area of I/O space not accessable to the
CPU). The data transfer will occur correctly, however.

&

CHIP SELECT CIRCUITRY

After every DMA transfer the 16-bit DMA transfer
count register it is decremented by I, whether a byte
transfer or a word transfer has occurred. If the TC bit in
the DMA control register is set, the DMA ST /STOP
bit (see below) will be cleared when this register goes to
0, causing all DMA activity to cease. A transfer count of
zero allows 65536 (2 16) transfers.

DMA
REQUESTS

Figure 31.

4.1

80186 CPU/DMA Channel
Internal Model

DMA Features

Each of the two DMA channels provides the following
features:
Independent 20-bit source and destination pointers
which are used to access the I/O or memory location
from which data will be fetched or to which data will
be deposited
Programmable auto-increment, auto-decrement or
neither of the source and destination pointers after
each DMA transfer
Programmable termination of DMA activity after a
certain number of DMA transfers
Programmable CPU interruption at DMA termination
Byte or word DMA transfers to or from even or odd
memory or I/O addresses

The DMA control register (see Figure 33) contains bits
which control various channel characteristics, including
for each of the data source and destination whether the
pointer points to memory or I/O space, or whether the
pointer will be incremented, decremented or left alone
after each DMA transfer. It also contains a bit which selects between byte or word transfers. Two synchronization bits are used to determine the source of the DMA
requests (see section 4.7). The TC bit determines whether DMA activity will cease after a programmed number
of DMA transfers, and the INT bit is used to enable interrupts to the processor when this has occurred (note
that an interrupt will not be generated to the CPU when
the transfer count register reaches zero unless both the
INT bit and the TC bit are set).
The control register also contains a start/stop
(ST /STOP) bit. This bit is used to enable DMA
transfers. Whenever this bit is set, the channel is

3-569

210973-003

AP-186

OFFSET
DEH
DCH
DAH
D8H
D6H

x

i19
15

DOH
CEH

15

C4H
C2H
COH

X

I I Ixl I I

I I I

15

D4H
D2H

CCH
CAH
C8H
C6H

X

I

119

X

X

0
16
0
16
0

TRANSFER COUNT
DESTINATION POINTER
SOURCE POINTER CHANNEL 1

t

X

I I I

I I Ixl I I

x

x

X

119

X

X

X

119

I

CONTROL WORD

15
15
15

0
16
0
16
0

CHANNELOl
CONTROL WORD
TRANSFER COUNT
DESTINATION POINTER
SOURCE POINTER

(1) CONTROL REGISTER LAYOUT:

DESTINATION

----

SOURCE

SYNCHRONIZATION

Figure 32.

80186 DMA Register Layout

Figure 33.

DMA ContrQI Register

"armed," that is, a DMA transfer will occur whenever a
• DMA request is made to the channel. If this bit is
cleared, no DMA transfers will be performed by the
channel. A companion bit, the CHG/NOCHG bit,
allows the contents of the DMA control register to be
changed without modifying the state of the start/stop
bit. The ST /STOP bit will only be modified if the
CHG/NOCHG bit is also set during the write to the
DMA control register. The CHG/NOCHG bit is
write only. It will always be read back as a O. Because
J:>MA transfers could occur immediately after the
ST /STOP bit is set, it should c;mly be set only after all
other DMA controller registers have been programmed.
This bit is automatically cleared when the transfer count
register reaches zero and the TC bit in the DMA control
register is set, or when the transfer count register
reaches zero and unsynchronized DMA transfers are
programmed.

All DMA unit programming registers are directly
accessable by the CPU. This means the CPU can, for example, modify the DMA source pointer register after
137 DMA transfers have occurred, and have the new
pointer value used for the l38th DMA transfer. If more
than one register in the DMA channel is being modified
at any time that a DMA request may be generated and
the DMA channel is enabled (the ST/STOP bit in the
control register is set), the register programming values
should be placed in memory locations and moved into
the DMA registers using a locked string move instruction. This will prevent a DMA transfer from occurring
after only half of the register values have changed. The
above also holds true if a read/modify/write type of operation is being performed (e.g., ANDing off bits in a
pointer register in a single AND instruction to a pointer
register mapped into memory space).

3-570

210973-003

AP-186

CLOCK

'

:

Tn

:

OUT~

DRQ~
ADO- --~----H
AD15

--+----H

RD --..:..----~

I

\

I
I
I

~
: CD I
\

I

I

I

I

I
I

:I~
CD:

CD

~~--~~----~-----------

:\~~----~----~--~/
I

I

1.
2.
3.
4.

I

I

I

0:

I
I
I
I
I
I

:\I

If
I

Source address
Source data
Destination address
Destination data

NOTE: Wait states are Inserted by the bus condition during the bus cycle, not by the DMA controller

Figure 34.

4.3

Example DMA Transfer Cycle on the 80186

DMA Transfers

Every D MA transfer in the 80186 consists of two independent bus cycles, the fetch cycle and the deposit cycle
(see Figure 34). During the fetch cycle, the byte or word
data is accessed from memory or I/O space using the address in the source pointer register. The data accessed is
. placed in an internal temporary register, which is not accessible to the CPU. During the deposit cycle, the byte
or word data in this internal register is placed in memory
or I/O space using the address in the destination pointer
register. These two bus cycles will not be separated by
bus HOLD or by the other DMA channel, and one will
never be run without the other except when the CPU is
RESET. Notice that the bus cycles run by the DMA
unit are exactly the same as memory or I/O bus cycles
run by the CPU. The only difference between the two is
the state of the S6 status line (which is multiplexed on
the AI9line): on all CPU initiated bus cycles, this status
line will be driven low; on all DMA initiated bus cycles,
this status line will be driven high.

4.4

DMA Requests

Each DMA channel has a single DMA request line by
which an external device may request a DMA transfer.
The synchronization bits in the DMA control register
determine whether this line is interpreted to be connected to the source of the DMA data or the destination of
the DMA data. All transfer requests on this line are synchronized to the CPU clock before being presented to in-

ternal DMA logic. This means that any asynchronous
transitions of the DMA request line will not cause the
DMA channel to malfunction. In addition to external
requests, DMA requests may be generated whenever the
internal timer 2 times out, or continuously by programming the synchronization bits in the DMA control register to call for unsynchronized DMA transfers: .

4.4.1

DMA REQUEST TIMING AND LATENCY

Before any DMA request can be generated, the 80186
internal bus must be granted to the D MA unit. A certain
amount of time is required for the CPU to grant this internal bus to the DMA unit. The time between a DMA
request being issued and the DMA transfer being run is
known as DMA latency. Many of the issues concerning
DMA latency are the same as those concerning bus latency (see section 3.3.2). The only important difference
is that external HOLD always has bus priority over an
internal DMA transfer. Thus, the latency time of an internal DMA cycle will suffer during an external bus
HOLD.
Each DMA channel has a programmed priority relative
to the other DMA channel. Both channels may be programmed to be the same priority, or one may be programmed to be of higher priority than the other channel.
If both channels are active, DMA latency will suffer on
the lower priority channel. If both channels are active
and both channels are of the same programmed priority,
DMA transfer cycles will alternate between the two
channels (i.e., the first channel will perform a fetch and
3-571

210973-003

Ap·186

T.or
:
1
1
1
1

DRQ

T.or

T.or

T.or
T, or

Taor,
T. or

1
1
1

Twor
T,

Twor
T,

T.Or
T. or

1
1
1

Tw or
T,

l i T
1
I'
1
T.or
of OMA .
1
T,
1 CYCLE

i

~
I

1

1
1
1
I'
1

I.

Q)

1
1
.1
1

1
.1
1
1
1
1

CD

1
1
1
1
1
1

I

I

1
1
I
I

1. tORCCl = DMA request to clock low = 25 Jls min to guarantee recognition
2. Synchronizer resolution time
3. DMA unit priority arbitration. etc. time
4. Bus Interfa~e Unit latches DMA request and decides to run DMA cycle

Figure 35. DMA Request Timing on the 80"186 '(showing minimum response time to request)
deposit, followed by a fetch and deposit. by the second
channel, etc).
The minimum timing required to generate'a DMA cycle
is shown in Figure 35. Note that the minimum time from
DRQ becoming active until the beginning of the first
DMA. cycle is 4 CPU clock cycles, that is, a DMA request IS sampled 4 clock cycles before the beginning of a
bus cycle to determine if any DMA activity will be required. This time is independent of the number of wait
staters inserted in the bus cycle. The mal(imum DMA latency is a function of other processor activity (see
above).
.

Also notice that if ORQ is sampled active at 1 in Figure
35, the DMA cycle will be executed, even if the DMA
request goes inactive before the beginning of the first
~MA cyc~e. This does not mean that the DMA request
IS latched mto the processor such that any transition on
the D~A request line will cause a DMA cycle eventually. QUIte the contrary, DMA request must be active at a
certain time before the end of a bus cycle for the DMA .
request to be recognized by the processor. If the DMA
request line goes inactive before that window, then no
DMA cycle~ will be rim.

ADDR.
LATCH

80186

A6

DMADEVICE

ALE~----------------------~

ACKNOWLEDGE

PCs0t-------------4-----.J CHIP

SEL

DRQO~---------------~~DMAREQUEST

Figure 36. DMA Acknowledge Synthesis from the 80186
3-572

,210973-003

AP-186

4.5

maximum count register regardless of the state of the
TC bit in the DMA control register.

DMA Acknowledge

The 80186 generates no explicit DMA acknowledge signal. Instead, the 80186 performs a read or write directly
to the DMA requesting device. If required, a DMA acknowledge signal can be generated by a decode of an address, or by merely using one of the PCS lines (see
Figure 36). Note ALE must be used to factor the DACK
because addresses are not guaranteed stable when chip
selects go active. This is required because if the address
is not stable when the PCS goes active, glitches can
occur at the output of the DACK generation circuitry as
the address lines change state. Once ALE has gone low,
the addresses are guaranteed to have been stable for at
least t AvAL (30ns).

4.6

4.7

Internally Generated DMA Requests

There are two types in internally synchronized DMA
transfers, that is, transfe~ initiated by a unit integrated
in the 80186. These two types are transfers in which the
DMA request is generated by timer 2, or where DMA
request is generated by the DMA channel itself.
The DMA channel can be programmed such that whenever timer 2 reaches its maximum count, a DMA request will be generated. This feature is selected by
setting the TDRQ bit in the DMA channel control register. A DMA request generated in this manner will be
latched in the DMA controller, so that once the timer request has been generated, it cannot be cleared except by
running the DMA cycle or by clearing the TDRQ bits in
both DMA control registers. Before any DMA requests
are generated in this mode, timer 2 must be initiated and
enabled.
A timer requested DMA cycle being run by either DMA
channel will reset the timer request. Thus, if both channels are using it to request a DMA cycle, only one DMA
channel will execute a transfer for every timeout of timer 2. Another implication of having a single bit timer
DMA request latch in the DMA controller is that if another timer 2 timeout occurs before a DMA channel has
a chance to run a DMA transfer, the first request will be
lost, i.e., only a single DMA transfer will occur, even
though the timer has timed out twice.
The DMA channel can also be programmed to provide
its own DMA requests. In this mode, DMA transfer cycles will be run continuously at the maximum bus bandwidth, one after the other until the preprogrammed
number of DMA transfers (in the DMA transfer count
register) have occurred. This mode is selected by programming the synchronization bits in the DMA control
register for unsynchronized transfers. Note that in this
mode, the DMA controller will monopolize the CPU
bus, i.e., the CPU will not be able to perform opcode
fetching, memory operations, etc., while the DMA
transfers are occurring. Also notice that the DMA will
only perforIll th,e number of transfers indicated in the

Externally Synchronized DMA
Transfers

There are two types of externally synchronized DMA
transfers, that is, DMA transfers which are requested by
an external device rather than by integrated timer 2 or
by the DMA channel itself (in unsynchronized transfers). These are source synchronized and destination
synchronized transfers. These modes are selected by
programming the synchronization bits in the DMA
channel control register. The only difference between
the two is the time at which the DMA request pin is sampled to determine if another DMA transfer is immediately required after the currently executing DMA
transfer. On source synchronized transfers, this is done
such that two source synchronized DMA transfers may
occur one immediately after the other, while on destination synchronized transfers a certain amount of idle
time is automatically inserted between two DMA transfers to allow time for the DMA requesting device to
drive its DMA request inactive.
4.7.1

SOURCE'SYNCHRONlZED
DMA TRANSFERS

In a source synchronized DMA transfer, the source of
the DMA data requests the DMA cycle. An example of
this would be a floppy disk read from the disk to main
memory. In this type of transfer, the device requesting
the transfer is read during the fetch cycle of the DMA
transfer. Since it takes 4 CPU clock cycles from the time
DMA request is sampled to the time the DMA transfer
is actually begun, and a bus cycle takes a minimum of 4
clock cycles, the earliest time the D MA request pin will
be sampled for another DMA transfer will be at the beginning of the deposit cycle of a DMA transfer. This allows over 3 CPU clock cycles between the time the
DMA requesting device receives an acknowledge to its
D MA request (around the beginning of T 2 of the D MA
fetch cycle), and the time it must drive this request inactive (assuming no wait states) to insure that another
DMA transfer is not performed if it is not desired (see
Figure 37).
4.7.2

DESTINATION SYNCHRONIZED
DMA TRANSFERS

In tlestination synchronized DMA transfers, the destination of the DMA data requests the DMA transfer. An
example of this would be a floppy disk write from main
memory to the disk. In this type of transfer, the device
requesting the transfer is written during the deposit cycle of the DMA transfer. This causes a problem, since
the DMA requesting device will not receive notification
of the DMA cycle being run until 3 clock cycles before
the end of the DMA transfer (if no wait states are being

3-573

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AP-186

DEPOSIT CYCLE

FETCH CYCLE

T,

T,

T,

T,

T,

T2

DRO _....,...._ _.L..._ _~_~--\

80186

DECISION:

1. Current DMA source synchronized transfer will not be immediately
followed by another DMA transfer
NEXT
DMA
TRANSFER

DEPOSIT CYCLE

T,

T,

:

T,

:

T,

Tw

T,

T,

T,

DRO _..I-_ _.L..._ _L--=~--.,

80186

Decision:

1. Current DMA destination synchronized transfer will be followed
immediately by another DMA transfer .

Figure 37.

Source & Destination Synchronized DMA Request Timing

inserted into the deposit cycle of the DMA transfer) and
it takes' 4 clock cycles to determine whether another
DMA cycle should be run immediately following the
current DMA transfer. To get around this problem, the
DMA unit will relinquish the CPU bus after each destination synchronized DMA transfer for at least 2 CPU
clock cycles to allow' the DMA requesting device time to
drop its DMA request if it does not immediately desire
another immediate DMA transfer. When the bus is relinquished by the DMA unit, the CPU may resume bus
operation (e.g., instruction fetching, memory or I/O
reads or writes, etc.) Thus, typically, a CPU initiated
bus cycle will be inserted between each destination synchronized DMA transfer. If no CPU bus activity is required, however (and none can be guaranteed), the
DMA unit will insert only 2 CPU clock cycles between
the deposit cycle of one DMA transfer and the fetch cycle of the next D MA transfer. This means tha t the D MA
destination requesting device must drop its DMA request at least two clock cycles before the end of the deposit cycle regardless of the number of wait states
inserted into the bus cycle. Figure 37 shows the DMA
request going away too late to prevent the immediate
generation of another DMA transfer. Any wait states inserted in the deposit cycle of the DMA transfer will

lengthen the amount of time from the beginning of the
deposit cycle to the time DMA will be sampled for another DMA transfer. Thus, if the amount oftime a device requires to drop its DMA request after receiving a
DMA acknowledge from the 80186 is longer than the 0
wait state 80186 maximum (100 ns), wait states can be
inserted into the DMA cycle to lengthen the amount of
time the device has to drop its DMA request after receiving theDMA acknowledge. Table 4 shows the amount of
time between the beginning of T 2 and the time D MA re. quest is sampled as wait states are inserted in the DMA
deposit cycle.

3-574

Table

4.

DMA Request Inactive Timing

Number of
Wait States

Max Time(ns)
For DRQ Inactive
From Start of T2

0

100

1

225

2

350

3

475
210973-003

AP-186

DMA FETCH CYCLE

DMA DEPOSIT CYCLE

ORQ
(ALWAYS
HIGH)

I

I

I.

Q)

I

NMI

/

I-

CDI

01-

..I
I

·1

CD

/

I
OHLT
(INTERNAL
REGISTER
BIT)

CD

!

1. DMA request synchronization
2. Decision: Will DMA cycle be run?
Answer: No DMA request is active but DHLT is set
(from NMI request)
3. NMI synchronization time
4. Logic delay time from synchronized NMI until DHLT set (note: DHLT is in
the interrupt control status register)

Figure 38.

4.8

NMI and DMA Interaction

DMA Halt and NMI

Whenever a Non-Maskable Interrupt is received by the
80186, all DMA activity will be suspended after the end
of the current DMA transfer. This is performed by the
NMI automatically setting the DMA Halt (DHLT) bit
in the interrupt controller status register (see section
6.3.7). The timing of NMI required to prevent a DMA
cycle from occurring is shown in Figure 38. After the
NMI has been serviced, the DHLT bit should be cleared
by the programmer, and DMA activity will resume exactly where it left off, Le., none of the DMA registers
will have been modified. The DMA Halt bit is not automatically reset after the NMI has been serviced. It is
automatically reset by the IRET instruction. This DMA
halt bit may also be set by the programmer to prevent
DMA activity during any critical section of code.

4.9
4.9.1

Example DMA Interfaces
8272 FLOPPY DISK INTERFACE

An example DMA Interface to the 8272 Floppy Disk
Controller is shown in Figure 39. This shows how a typical DMA device can be interfaced to the 80186. An example floppy disk software driver for this interface is
given in Appendix C.

The data lines of the 8272 are connected, through buffers, to the 80186 ADO-AD7 lines. The buffers are required because the 8272 will not float its output drivers
quickly enough to prevent contention with the 80186
driven address information after a read from the 8272
(see section 3.1.3).
DMA acknowledge for the 8272 is driven by an address
decode within the region assigned to PCS2. If
PCS2 is assigned to be active between I/O locations
OSOOH and OS7FH, then an access to I/O location
OSOOH will enable only the chip select, while an access to
I/O location OS10H will enable both the chip select and
the DMA acknowledge. Remember, ALE must be factored into the DACK generation logic because addresses
are not guaranteed stable when the chip selects become
active. If ALE were not used, the DACK generation circuitry could glitch as address output changed state while
the chip select was active.
.
Notice that the TC line of the 8272 is driven by a very
similar circuit as the one generating DACK (except for
the reversed sense ofthe output!). This line is used to terminate an 8272 command before the command has completed execution. Thus, the TC input to the 8272 is
software driven in this case. Another method of driving
the TC input would be to connect the DACK signal to
one of the 80186 timers, and program the timer to out-

3-575

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"nt_l®
111'e' '

AP-186

,r-

DRO

D
7474

ex

CLKOUT
PCS2

or--

CL

7474
C.

CL

I

1

H>

oj

D

DRO
CLK

CS
A

D-

ALE

DACK

ADDR
LATCH

8272

tP- M
TC
AO

DATA
/

AD7-ADO

8

DISK

NTERFACE

DBO-

aUFFER

FLOPPY

DB7

8'-

RD

RD
WR

WR
RESET

RESET
C. = 7474 CLOCK INPUT
CL

Figure 39.

= 7474 CLEAR INPUT

Example 8272/80186 DMA Interface

put a pulse to the 8272 after a certain number of DMA
cycles have been run (see next section for 80186 timer
information).
The above discussion assumed that a single 80186
PCS line is free to generate all 8272 select, signals. If
more than' one ch.!JL!.elect is free, however, different
80186 generated PCS lines could be used for each
function. For example, PCS2 could be used to select
the 8272, PCS3 could be used to drive the DACK line
of the 8272, etc.
DMA requests are delayed by two clock periods in going
from the 8272 to the 80186. This is require.!!..Qy the 8272
tRQR (time from DMA request to DMA RD going active) spec of 800ns min. This requires 6.4 80186 CPU

clock cycles (at 8 MHz), well beyond the 5 minimum
provided by the 80186 (4 clock cycles to the beginning of
the D MA bus cychl to the beginning ofT2 of the D MA
bus cycle where RD will go active). The two flip-flops
add two complete CPU clock cycles to this response
time.
DMA request will go away 200ns after DACK is presented to the 8272. During a DMA write cycle (i.e., a
destination synchronized transfer), this is not soon
enough to prevent the immediate generation of another
DMA transfer if no wait states are inserted in the deposit cycle to the 8272. Therefore, atleast 1 wait state is required by this interface, regardless of the data access
parameters of the 8272.

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AP-186

4.9.2

5.

8274 SERIAL
COMMUNICATION INTERFACE

The 80186 includes a timer unit which provides three independent 16-bit timers. These timers operate independently of the CPU. Two of these have input and output
pins allowing counting of external events and generation
of arbitrary waveforms. The third timer can be used as a
timer, as a prescaler for the other two timers, or as a
DMA request source.

An example 8274 synchronous/asynchronous serial
chip/80l86 DMA interface is shown in Figure 40. The
8274 interface is even simpler than the 8272 interface,
since it does not require the generation of a DMA acknowledge signal, and the 8274 doe.'! not require the
length of time between a DMA request and the DMA
read or write cycle that the 8272 does. An example serial
driver using the 8274 in DMA mode with the 80186 is
given in Appendix C.

DRQO

8274
TxDRQ.

DRQ1

RxDRQ.

r---

ADDR
LATCH

/

2/

5.1

ADO·AD7

AO,A1

8/

8288
DATA
BUFFER

/

(rf

DBD-DB7

5.2
RD
WR
RESET

Figure 40.

Timer Registers

Each timer is controlled by a block of registers (see Figure 43). Each of these registers can be read or written
whether or not the timer is operating. All processor accesses to these registers are synchronized to all counter
element accesses to these registers, meaning that one
will never read a count register in which only half of the
bits have been modified. Because of this synchronization, one wait state is alftomatically inserted into any access to the timer registers. Unlike the DMA unit,
locking accesses to timer registers will not prevent the
timer's counter element from accessing the timer
registers.

RD
WR
RESET

Example 8274/80186 DMA Interface

The data lines ofthe 8274 are connected through buffers
to the 80186 ADO-AD7lines. Again, these are required
not because of bus drive problems, but because the 8274
will not float its drivers before the 80186 will begin driving address information on its address/data bus. If both
the 8274 and the 8272 are included in the same 80186
system, they could share the same data bus buffer (as
could any other peripheral devices in the system).
The 8274 does not require a DMA acknowledge signal.
The first read from or write to the data register of the
8274 after the 8274 generates the DMA request signal
will clear the DMA request. The time between when the
control signal (RD or WR) becomes active and
when the 8274 will drop its DMA request during a
DMAwrite is 150ns, which will require at least one wait
state be inserted into the DMA write cycle for proper operation of the interfacll.

Timer Operation

The internal timer unit on the 80186 could be modeled
by a single counter element, time multiplexed to three
register banks, each of which contains different control
'and count values. These register banks are, in turn, dual
ported between the counter element and the 80186 CPU
(see Figure 41). Figure 42 shows the timer element sequencing, and the subsequent constraints on input and
output signals. If the CPU modifies one ofthe timer registers, this change will affect the counter element the
next time that register is presented to the counter element. There is no connection between the sequencing of
the counter element through the timer register banks
and the Bus Interface Unit's sequencing through Tstates. Timer operation and bus interface operation are
completely asynchronous.

lV
A"
A./

TIMER UNIT INTERFACING

Each timer has a 16-bit count register. This register is
incremented for each timer event. A timer event can be a
low-to-high transition on the external pin (for timers 0
and I), a CPU clock transition (divided by 4 because of
the counter element multiplexing), or a time out of timer
2 (for timers 0 and 1). Because the count register is 16
bits wide, up to 65536 (2 16) timer events can be counted
by a single timer/couRter. This register can be both read
or written whether the timer is or is not operating.
Each timer includes a maximum count register. Whenever the timer count register is equal to the maximum
count register, the count register will be reset to zero,
that is, the maximum count value will never be stored in
the count register. This maximum count value may be
written while the timer is operating. A maximum count

3-577

210973-003

"1

_I®
Im
I-e-

AP-1.86

To

T,

IN

IN

CPU

DMA
REQUEST

Figure 41.

80186 Timer Model

TI~ER

1

SERVICED

TIMER 0

TIMER 2
SERVICED

DEAD

SERVICED

TIMER IN

o

TIMER IN

1

TIMER OUT

o

TIMER OUT

1

1.
2.
3.
4.

Timer in 0 resolution time
Timer in 1 resolution time
Modified count value written into 80186 timer 0 count register
Modified count value written into 80186 timer 1 count register

Figure 42.

80186 Counter Element Multiplexing and Timer Input Synchronization

3-578

210973-003

AP-186

OFFSET

54H

COUNT REGISTER
----------MAX COUNT REGISTER A
----------MAX COUNT REGISTER B

56H

-

58H

COUNT REGISTER
----------MAX COUNT REGISTER A
----------MAX COUNT REGISTER B

SOH
52H

SAH
5CH
5EH
60H

-

CONTROL REGISTER-d) -

CONTROL REGISTER-(i)

-

TIMER 1

- - - -

64H

COUNT REGISTER
----------MAX COUNT REGISTER
-- - - -X- - - - -XX

66H

-

62H

TIMER 0

--

CONTROL REGISTER-aT -

-

-

TIMER 2

-

CD CONTROL REGISTER LAYOUT
o

15

Figure 43.

80186 Timer Register Layout

value of 0 implies a maximum count of 65536, a maximum count value of 1 implies a maximum count of 1,
etc. The user should be aware that only equivalence between the count value and the maximum count register
value is checked, that is, the count value will not be
cleared if the value in the count register is greater than
the value in-the maximum count register. This could only
occur by programmer intervention, either by setting the
value in the count register greater than the value in the
maximum count register, or by setting the value in the
maximum count register to be less than the value in the
count register. If this is programmed, the timer will
count to the maximum possible count (FFFFH), increment to 0, then count up to the value in the maximum
count register. The TC bit in the timer control register
will not be set when the counter overflows to 0, nor will
an interrupt be generated from the timer unit.
Timers 0 and 1 each contain an additional maximum
count register.-When both maximum count registers are
used, the timer will first count up to the value in maximum count register A, reset to 'zero, count up to the value in maximum count register B, and reset to zero again.
The ALTernate bit in the timer control register determines whether one or both maximum count registers are
used. If this bit is low, only maximum count register A is
used; maximum count register B is ignored. If it is high,
both maximum count register A and maximum count
register B are used. The RIU (register in use) bit in tile
timer control register indicates which maximum count
register is currently being used. This bit is 0 when maximum count register A is being used, 1 when maximum
count register B is being used. This RIU bit is read only.
It is unaffected by any write to the timer control register.
It will always be read 0 in single maximum count regis-

ter mode (since only maximum count register A will be
used).
Each timer can generate an interrupt whenever the timer count value reaches a maximum count value. That is,
an interrupt can be generated whenever the value in
maximum count register A is reached, and whenever the
value in maximum count register B is reached. In addition, the MC (maximum count) bit in the timer control
register is set whenever the timer count reaches a maximum count value. This bit is never automatically
cleared, i.e., programmer intervention is required to
clear this bit. If a timer generates a second interrupt request before. the first interrupt request has been serviced, the first interrupt request to the CPU will be lost.
Each timer has an ENable bit in the timer control register. This bit is used to enable the timer to count. The timer will count timer events only when this bit is set. Any
timer events occurring when this bit is reset are ignored.
Any write to the timer control register will modify the
ENable bit only if the INHibit bit is also set. The timer
ENable bit will not be modified by a write to the timer
control register if the INHibit bit is not set. The INHibit
bit in the timer control register allows selective updating
of the timer ENable bit. The value of the INHibit bit is
not stored in a write to the timer control register; it will
always be read as a 1.
Each timer has a CONTinuous bit in the timer control
register. If this bit is cleared, the timer ENable bit will
be automatically cleared at the end of each timing cycle.
If a single maximum count register is used, the end of a
timing cycle occurs when the count value resets to zero
after reaching the value in maximum count register A. If
dual maximum count registers are used, the end of a

3-579

210973-003

Ap·186

timing'cycle occurs when the count value resets to zero
after reaching the value in maximum count register B. If
the CONTinuous bit is set, the ENable bit in the timer
control register will never be automatically'reset. Thus,
after each timing cycle, another timing cycle will automatically begin. For example, in single maximum count
register mode, the timer will count up to the value in
maximum count register A, reset to zero, count up to the
value in maximum count register A, reset to zero, ad infinitum. In dual maximum count register mode, the timer will count up the the value in maximum count register
A, reset to zero, count up the value in maximum count
register B', reset to zero, count up to the value in maximum count register A, reset to zero, et cetera.

5.3

Timer Events

Each timer counts timer events. All timers can use a
transition of the CPU clock as an event. Because of the
counter element multiplexing, the timer-count value will
be incremented every fourth CPU clock. For timer 2,
this is the only timer event which can be used. For timers
oand I, this event is selected by clearing the EXTernal
and Prescaler bits in the timer control register.
Timers 0 and 1 can use timer 2 reaching its maximum
count as a timer event. This is selected by clearing the
EXTernal bit and setting the Prescaler bit in the timer
control register. When this is done, the timer will increment whenever timer 2 resets to zero having reached its
own maximum count. Note that timer 2 must be initialized and running for the other timer's value to be
incremented.
Timers 0 and 1 can also be programmed to count low-tohigh transitions on the external input pin. Each transition on the external pin is synchronized to the 80186
clock before it is presented to the timer circuitry, and
may, therefore, be asynchronous (see Appendix.B for information on 80186 synchronizers). The timer counts
transitions on the input pin: the input value must go low,
then go high to cause the timer to increment. Any transition on this line is latched. If a transition occurs when a
timer is not being serviced by the counter element, the
transition on the input line will be remembered so that
when the timer does get serviced, the input transition
will be counted. Because of the counter element multiplexing, the maximum rate at which the timer can count
is 1/4 of the CPU clock rate (2 MHz with an 8 MHz
CPU clock).
'

5.4 Timer Input Pin Operation
Timers 0 and 1 each have individual timer input pins.
Alliow-to-high transitions on these input pins are synchronized, latched, and presented to the counter element
when the particular timer is being serviced by the
counter element.
Signals on this input can affect timer operation in three
different ways. The manner in which the pin signals are
used is determined by the EXTernal and RTG (retrig-

ger) bits in ~he timer control register. If the EXTernal
bit is set, transitions on the input pin will cause the timer
count value to increment if the timer is enabled (the ENable bit in the timer control register is set). Thus, the
timer counts external events. If the EXTernal bit is
cleared, all· timer increments are caused by either the
CPU clock or by timer 2 timing out. In this mode, the
RTG bit determines whether the input pin will enable
timer operation, or whether it 'will retrigger timer
operation.

If the EXTernal bit is low and the R TG bit is also low,
the timer will count internal timer events only when the
timer input pin is high and the ENable' bit in the timer
control register is set. Note that in this mode, the pin is
level sensitive, not edge sensitive. A low-to-high transi~
tion on the timer input pin is not required to enable timer
operation. If the input is tied high, the timer will be continually enabled. The timer enable input signal is completely independent of the ENable bit in the timer
control register: both must be high for the timer to
count. Example uses for the timer in this mode would be
a real time clock or a baud rate generator.
If the EXTernal bit is low and the RTG bit is high, the
timer will act as a digital one-shot. In this mode, every
low-to-high transition on the timer input pin will cause
the timer to reset to zero. If the timer is enabled (i.e., the
ENable bit in the timer control register is set) timer operation will begin (the timer will count CPU clock transitions or timer 2 timeouts). Timer operation will cease
at the end of a timer cycle, that is, when the value in ~he
maximum count register A is reached and the timer
count value resets to zero (in single maximum count register mode, remember that the maximum count value is
never stored in the timer count register) or when the value in maximum count register B is reached and the. timer
count value resets to zero (in dual maximum count register mode). If another low-to-high transition occurs on
the input pin before the end of the timer cycle, the timer
will reset to zero and begin the timing cycle again regardless of the state of the CONTinuous bit in the timer
control register the RIU bit will not be changed by the
input transition. If the CONTinuous bit in the timer
control register is cleared, the timer ENable bit will
automatically be cleared at the end of the timer cycle.
This means that any additional transitions on the input
pin will be ignored by the timer. If the CONTinuous bit
in the timer control register is set, the timer will reset to
zero and begin another timing cycle for every low-tohigh transition on the input pin, regardless of whether
the timer had reached the end of a timer cycle, because
the timer ENable bit would not have been cleared at the
end of the timing cycle. The timer will also continue
counting at the end of a timer cycle, whether or not another transition has occurred on the input pin. An example use of the timer in this mode is an alarm clock time
out signal or interr~pt.

3-580
l

210973-003

AP-186

5.5

Timer Output Pin Operation

a baud rate generator.

Timers 0 and 1 each contain a single timer output pin.
This pin can perform two functions at programmer option. The first is a single pulse indicating the end of a
timing cycle. The second is a level indicating the maximum count register currently being used. The timer outputs operate as outlined below whether internal or
external clocking of the timer is used. If external clocking is used, however, the user should remember that the
time between an external transition on the timer input
pin and the time this transition is reflected in the timer
out pin will vary depending on when the input transition
occurs relative to the timer's being serviced by the
counter element.

When the timer is programmed in dual maximum count
register mode (the ALTernate bit in the timer control
register is set), the timer output pin indicates which
maximum count register is being used. It is low if maximum count register B is being used for the current
count, high if maximum count register A is being used.
If the tiIl\er is programmed in continuous mode (the
CONTinuous bit in the timer control register is set), this
pin could generate a waveform of any duty cycle. For example, if maximum count register A contained 10 and
maximum count register B contained 20, a 33% duty cycle waveform would be generated.

When the timer is in single maximum count register
mode (the ALTernate bit in the timer control register is
cleared) the timer output pin will go low for a single
CPU clock the clock after the timer is serviced by the
counter element where maximum count is reached (see
Figure 44). This mode is useful when using the timer as

5.6

Sample 80186 Timer Applications

The 80186 timers can be used for almost any application
for which a discrete timer circuit would be used. These
include real time clocks, baud rate generators, or event
counters.

TIMER 0 SERVICED

INTERNAL
COUNT
VALUE
TMR OUT
PIN

---------""\1-----+----------------------i"1
Figure 44.

80186 Timer Out Signal

80186

r--

+5V

+ 5V
TMRINol

TIMER
TMR IN 1

0
'---

TMR OUT 1

TMROUTO

TxC } SERIAL
RxC
CONTROLLER

TMR INO

Figure 45.

80186 Real Time Clock

Figure 46.
3-581

80186 Baud Rate Generator
210973-003

AP-186

0
0
0

80186

JL
TMR INO

3GLIGHT
~

Figure 47.

5.6.1

80186 TIMER REAL TIME CLOCK

The sample program in appendix D shows the 80186
timer being used with the 80186 CPU to form a real
time clock. In this implementation, timer 2 is programmed to provide an interrupt to the CPU every millisecond. The CPU then increments memory based clock
variables.
5.6.2

80186 TIMER BAUD RATE GENERATOR

The 80186 timers can also be used as baud rate generators for serial communication controllers (e.g., the
8274). Figure 46 shows this simple connection, and the

code to program the timer as a baud rate generator is included in appendix D.
5.6.3

80186 TIMER EVENT COUNTER

The 80186 timer can be used to count events. Figure 47
shows a hypothetical set up in which the 80186 timer
will count the interruptions ill a light source. The number of interruptions can be read directly from the count
register of the timer, since the timer counts up, i.e., each
interruption in the light source will cause the timer
count value to increase. The code to set up the 80186
timer in this mode is included in appendix D.

TIMER TIMER TIMER

o

1

2

INTO

INT1

INT2

INT3

NMI

TIMER
CONTROL REG.

INTERRUPT
REQUEST REG.

DMAO
CONTROL REG.
DMA 1
CONTROL REG.

INTERRUPT
MASK REG.

EXT. INPUT 0
CONTROL REG.
EXT. INPUT 1
CONTROL REG.

INTERRUPT
PRIORITY
RESOLVER

IN-SERVICE
REG.
PRIOR. LEV.
MASK REG.
INTERRUPT
STATUS REG.

EXT. INPUT 2
CONTROL REG.

INTERRUPT
REQUEST TO
PROCESSOR
INTERNAL ADDRESS/DATA BUS

Figure 48.

80186 Interrupt Controller Block Diagram

3-582

210973-003

AP-186

6.

80186 INTERRUPT CONTROLLER
INTERFACING

The 80186 contains an integrated interrupt controller.
This unit performs tasks of the interrupt controller in a
typical system. These include synchronization of interrupt requests, priortization of interrupt requests, and request type vectoring in response to a CPU interrupt
acknowledge. It can be a master to two external 8259A
interrupt controllers or can be a slave to an external interrupt controller to allow compatibility with the iRMX
86 operating system, and the 80130/80150 operating
system firmware chips.

6.1

operates as a slave to an external interrupt controller
which operates as the master interrupt controller for the
system. Some of the interrupt controller registers and in, terrupt controller pins change definition between these
two modes, but the basic charter and function of the interrupt controller remains fundamentally the same. The
difference is when in master mode, the interrupt controller presents its interrupt input directly to the 80186
CPU, while in iRMX 86 mode the interrupt controller
presents its interrupt input to an external controller
(which then presents its interrupt input to the 80186
CPU). Placing the interrupt controller in iRMX 86
mode is done by setting the iRMX mode bit in the peripheral control block pointer (see appendix A).

Interrupt Controller Model
6.3

The integrated interrupt controller block diagram is
shown in Figure 48. It contains registers and a control
element. Four inputs are provided for external interfacing to the interrupt controller. Their functions change
according to the programmed mode of the interrupt controller. Like the other 80186 integrated peripheral registers, the interrupt controller registers are available for
CPU reading or writing at any time.

6.2

Interrupt Controller Registers

The interrupt controller has a number of registers which
are used to control its operation (see Figure 49). Some of
these change their function between the two major
modes of the interrupt controller (master and iRMX 86
mode). The differences are indicated in the following
section. If not indicated, the function and implementation of the registers is the same in the two basic modes of
operation of the interrupt controller. The method of interaction among the various interrupt controller registers is shown in the flowcharts in Figures 57 and 58.

Interrupt Controller Operation

The interrupt controller operates in two major modes,
non-iRMX 86 mode (referred to henceforth as master
mode), and iRMX 86 mode. In master mode the integrated controller acts as the master interrupt controller
for the system, while in iRMX 86 mode the controller

6.3.1. CONTROL REGISTERS
Each source of interrupt to the 80186 has a control register in the internal controller. These registers contain

MASTER MODE

OFFSET ADDRESS

,RMX86 N Mode

INT3 CONTROL REGISTER

3EH

CD

3CH
3AH

===========0===========

38H

TIMER 1 CONTROL REGISTER

DMA1 CONTROL REGISTER

36H

DMA1 CONTROL REGISTER

DMAO CONTROL REGISTER

34H

DMAO CONTROL REGISTER

32H

TIMER 0 CONTROL REGISTER

INTERRUPT CONTROLLER STATUS REGISTER

30H

INTERRUPT CONTROLLER STATUS REGISTER

INTERRUPT REQUEST REGISTER

2EH

INTERRUPT REQUEST REGISTER

IN-SERVICE REGISTER

2CH

PRIORITY MASK REGISTER

----------------------MASK REGISTER

2AH

IN SERVICE REGISTER
----------------------PRIORITY MASK REGISTER

28H

MASK REGISTER

POLL STATUS REGISTER

26H

POLL REGISTER

24H

EOI REGISTER

22H

INT2 CONTROL REGISTER
INn CONTROL REGISTER

----------------------INTO CONTROL REGISTER
----------------------TIMER CONTROL REGISTER

-----------0-----------

20H

TIMER 2 CONTROL REGISTER

SPECIFIC EOI REGISTER
----------------------===========$===========
INTERRUPT VECTOR REGISTER

1. Unsupported in this mode: values written mayor may not be stored

Figure 49.

80186 Interrupt Controller Registers

3-583

210973-003

AP-186

ent

o

15

0

SPECIAL
FULLY
NESTED
BIT

0

CAS-

LEVEL

CADE
MODE

TRIG.

0

I
PRIORITY BITS
I
I

MASK

MOD~CD

:

BIT

1. This bit present only in INTO-INT3 control registers
2. These bits present only in INTO-INT1 control register

Figure 50_

MASTER MODE

15

x

x

Figure 51.

Interrupt Controller Control Register

o

15

x

x

0

x

80186 Interrupt Controller In-Service, Interrupt Request and Mask Register Format

6.3.3 MASK REGISTER AND PRIORITY

three bits which select one of eight different interrupt
priority levels for the interrupt device (0 is highest priority, 7 is lowest priority), and a mask bit to enable the interrupt (see Figure 50). When the mask bit is low, the
interrupt is enabled, when it is high, the interrupt is
masked.

MASK REGISTER

The interrupt controller contains a mask register (see
Figure 51). This register contains a mask bit for each interrupt source associated with an interrupt control register. The bit for an interrupt source in the mask register is
identically the same bit as is provided in the interrupt
control register: modifying a mask bit in the control register will also modify it in the mask register, and vice
versa.

There are seven control registers in the 80186 integrated
interrupt controller. In master mode, four of these serve
the external interrupt inputs, one each for the two DMA
channels, and one for the collective timer interrupts. In
iRMX 86 mode, the external interrupt inputs are not
used, so each timer can have its own individual control
register.

6.3.2

iRMX N 86 MODE

The interrupt controller also contains a priority mask
register (see Figure 52). This register contains three bits
which indicate the lowest priority an interrupt may have
that will cause an interrupt acknowledge. Interrupts
received which have a lower priority will be effectively
masked off. Upon reset this register is set to the lowest
priority of 7 to enable all interrupts of any priority. This
register may be read or written.

REQUEST REGISTER

The interrupt controller includes an interrupt request
register (see Figure 51). This register contains seven active bits, one for each interrupt control register. Whenever an interrupt request is made by the interrupt source
associated with a specific control register, the bit in interrupt request register is set, regardless if the interrupt
is enabled, or if it is of sufficient priority to cause a processor interrupt. The bits in this register which are associated with integrated peripheral devices (the DMA and
timer units) can be read or written, while the bits in this
register which are associated with the external interrupt
pins can only be read (values written to them are not
stored). These interrupt request bits are automatically
cleared when the interrupt is acknowledged.

o

15

x

x

Figure 52.

6.3.4

x
80186 Interrupt Controller Priority
Mask Register Format

IN-SERVICE REGISTER

The interrupt controller contains an in-service register
(see Figure 51). A bit in the in-service register is associated with each interrupt control register so that when an
interrupt request by the device associated with the con-

3-584

210973-003

AP-1S6

trol register is acknowledged by the processor (either by
the processor running the interrupt acknowledge or by
the processor reading the interrupt poll register) the bit
is set. The bit is reset when the CPU issues an End Of
Interrupt to the interrupt controller. This register may
be both read and written, i.e., the CPU may set in-service bits without an interrupt ever occurring, or may reset them without using the EOI function of the interrupt
controller.
6.3.5

sor had acknowledged the interrupt through interrupt
acknowledge cycles. The processor will not actually run
any interrupt acknowledge cycles, and will not vector
through a location in the interrupt vector table. Only the
interrupt request, in-service and priority mask registers
in the interrupt controller are set appropriately. Reading
the poll status register will merely transmit the status of
the polling bits without modifying any of the other interrupt controller registers. These registers are read only:
data written to them is not stored. These registers are
not supported in iRMX 86 mode. The state of the bits in
these registers in iRMX 86 mode is not defined.

POLL AND POLL STATUS REGISTERS

The interrupt controller contains both a poll register and
a poll status register (see Figure 53). Both of these registers contain the same information. They have a single bit
to indicate an interrupt is pending. This bit is set if an
interrupt of sufficient priority has been received. It is
automatically cleared when the interrupt is acknowledged. If (and only if) an interrupt is pending, they also
contain information as to the interrupt type of the highest priority interrupt pending.

6.3.6

o

15

x

x

x

SO-S4 = interrupt type

Figure 53.

80186 Poll & Poll Status
Register Format

Reading the poll register will acknowledge the pending
interrupt to the interrupt controller just as if the proces-

15

o

MASTER MODE

J;SPEC'x

iRMX86 MODE

15

x
SO-S4

Interrupt type

=

x

x

x

o

x

LO-L2 = interrupt priority level

Figure 54.

15r
I I

END OF INTERRUPT REGISTER

The mterrupt controller contains an End Of Interrupt
register (see Figure 54). The programmer issues an End
Of Interrupt to the controller by writing to this register.
After receiving the End Of Interrupt, the interrupt
controller automatically resets the in-service bit for the
interrupt. The value of the word written to this register
determines whether the End Of Interrupt is specific or
non-specific. A non-specific End Of Interrupt is specified
by setting the non-specific bit in the word written to the
End Of Interrupt register. In a non-specific End Of
Interrupt, the in-service bit of the highest priority interrupt
set is automatically cleared, while a specific End Of
Interrupt allows the in-service bit cleared to be explicitly
specified. The in-service bit is reset whether the bit 'Was set
by an interrupt acknowledge or if it was set by the CPU
writing the bit directly to the in-service register. If the

80186 End of Intenupt Register Format

o

DHLT

x

x

Figure 55.

x

x

x

80186 Interrupt Status Register Format

o

15

x
Figure 56.

x

x

80186 Interrupt Vector Register Format (IRMX 86 mode only)
3-585

210973-003

AP-186

highest priority interrupt is reset, the pnonty mask
register bits will change to reflect the,next lowest priority
interrupt to be serviced. If a less than highest priority
interrupt in-service bit is reset, the priority mask register
bits will not be modified (because the highest priority
interrupt being serviced has not c:hanged). Only the
specific EO! is supported in iRMX 86 mode. This register
is write only: data written is not stored and cannot be
read back.
6.3.7

INTERRUPT STATUS REGISTER

The interrupt controller also contains an interrupt status
register (see Figure 55). This register contains four significant bits. There are three bits used to show which
timer is causing an interrupt. This is required because in
master mode, the timers share a single interrupt control
register. A bit in this register is set to indicate which timer has generated an interrupt. The bit associated with a
timer is automatically cleared after the interrupt request for the timer is acknowledged. More than one of
these bits may be set at a time. The fourth bit in the interrupt status register is the DMA halt bit. When set,
this bit prevents any DMA activity. It is automatically
set whenever a NMI is received by the interrupt controller. It can also be set explicitly by the programmer. This
bit is automatically cleared whenever the IRET instruction is executed. All significant bits in this register are
read/write.
6.3.8

INTERRUPT VECTOR REGISTER

Finally, in iRMX 86 mode only, the interrupt controller
contains an interrupt vector register (see Figure 56).
This register is used to specify the 5 most significant bits
of the interrupt type vector placed on the CPU bus in response to an interrupt acknowledgement (the lower 3
significant bits of the interrupt type are determined by
the priority level of the device causing the interrupt in
iRMX 86 mode).

6.4

Interrupt Sources

The 80"'86 interrupt controller receives and arbitrates
among many different interrupt request sources, both
internal and external. Each interrupt source may be programmed to be a different priority level in the interrupt
controller. An interrupt request generation flow chart is
shown in Figure 57. Such a flowchart would be followed
independently by each interrupt source.
6.4.1

INTERNAL INTERRUPT SOURCES

The internal interrupt sources are the three timers and
the two D MA channels. An int~rrupt from each of these
interrupt sources is latched in the interrupt controller, so
that if the condition causing the interrupt is cleared in
the originating integrated peripheral device, the interrupt request will remain pending in the interrupt controller. The state of the pending interrupt can be
obtained by reading the interrupt request register of the

interrupt controller. For all internal interrupts, the
latched interrupt request can be reset by the processor
by writing to the interrupt request register. Note that all
timers share a common bit in the interrupt request register in master mode. The interrupt controller status register may be read to determine which timer is actually
causing the interrupt request in this mode. Each timer
has a unique interrupt vector (see section 6.5.1). Thus
polling is not required to determine which timer has
caused the interrupt in the interrupt service routine.
Also, because the timers share a common interrupt control register, they are placed at a common priority level
as referenced to all other interrupt devices. Among
themselves they have a fixed priority, with timer 0 as the
highest priority timer and timer 2 as the lowest priority
timer.
6.4.2

EXTERNAL INTERRUPT SOURCES

The 80186 interrupt controller will accept external interrupt requests only when it is programmed in master
mode. In this mode, the external pins associated with the
interrupt controller may serve either as direct interrupt
inputs, or as cascaded interrupt inputs from other interrupt controllers as a programmed option. These options
are selected by programming the C and SFNM bits in
the INTO and INTI control registers (see Figure 50).
When programmed as direct interrupt inputs, the four
interrupt inputs are each controlled by an individual interrupt control register. As stated earlier, these registers
contain 3 bits which select the priority level for the interrupt and a single bit which enables the interrupt source
to the processor. In addition each of these control registers contains a bit which selects either edge or level triggered mode for the interrupt input. When edge triggered
mode is selected, a low-to-high transition must occur on
. the interrupt input before an interrupt is generated,
while in level triggered mode, only a high level needs to
be maintained to generate an interrupt. In edge trig~
gered mode, the input must remain low at least 1 clock
cycle before the input is "re-armed." In both modes, the
interrupt level must remain high until the interrupt is
acknowledged, i.e., the interrupt request is not latched
in the interrupt controller. The status of the interrupt input can be shown by reading the interrupt request register. Each of the external pins has a bit in this register
which indicates an interrupt request on the particular
pin. Note that since interrupt requests on these inputs
are not latched by the interrupt controller, if the external
input goes inactive, the interrupt request (and also the
bit in the interrupt request register) will also go inactive
(low). Also, if the interrupt input is in edge triggered
mode, a low-to-high transition on the input pin must occur before the interrupt request bit will be set in the interrupt request register.
If the C (Cascade) bit of the INTO or INTI control registers are set, the interrupt input is cascaded to an external interrupt controller. In this mode, whenever the

3-586

210973-00~

AP-186

Figure 57.

80186lnterrupt.Request Sequencing

interrupt presented to the INTO or INTI line is acknowledged, the integrated interrupt controller will not
provide the interrupt type for the interrupt. Instead, two
INTA bus cycles will be run, with the INT2 and INT3
lines providing the interrupt acknowledge pulses for the
INTO and the INTI interrupt requests respectively. INTO/INT2 and INTI/INT3 may be individually programmed into cascade mode. This allows 128
individually vectored interrupt sources if two banks of 9
external interrupt controllers each are used.

rupt requests only from the integrated peripherals. Any
external interrupt requests must go through an external
interrupt controller. This external interrupt controller
requests interrupt service directly from the 80186 CPU
through the INTO line on the 80186, In this mode, the
function of this line is not affected by the integrated interrupt controller. In addition, in iRMX 86 mode the integrated interrupt controller must request interrupt
service through this external interrupt controller. This
interrupt request is made on the INT3 line (see section
6.7.4 on external interrupt connections).

6.4.3

6.5

iRMX'" 86 MODE INTERRUPT SOURCES

When the interrupt controller is configured in iRMX 86
mode, the integrated interrupt controller accepts inter-

Interrupt Response

The 80186 can respond to an interrupt in two different
ways. The first will occur if the internal controller is pro3-587

210973-003

AP-186

WAIT FOR NEXT
INTERRUPT
ACKNOWLEDGE

GENERATE INTA
CYCLES FOR
EXTERNAL
INTERRUPT
CONTROLLER

PLACE INTERRUPT
TYPE ON INTERNAL ri\
BUS DURING SECOND \.!I
INTACYCLE

YES

PROVIDE HIGHEST
PRIORITY INTERRUPT
VECTOR ON
INTERNAL BUS

1. Before actual interrupt ackno'wledge is run by CPU
2. Two interrupt acknowledge cycles will be run, the interrupt type is read by
the CPU on the second cycle
3. Interrupt acknowledge cycles will not be run, the interrupt vector address is
placed on an internal bus and is not available outside the processor
4. Interrupt type is not driven on external bus in iRMX86 mode

Figure 58.

80186 Interrupt Acknowledge Sequencing

viding the interrupt vector information with the controller in master mode. The second will occur if the CPU
reads interrupt type information from an external interrupt controller or if the interrupt controller is in iRMX
86 mode. In both of these instances the interrupt vector
information driven by the 80186 integrated interrupt
controller is not available outside the 80186
microprocessor.

6.5.1

INTERNAL VECTORING, MASTER MODE

In each interrupt mode, when the integrated interrupt
controller receives an interrupt response, the interrupt
controller will automatically set the in-service bit and
reset the interrupt request bit in the integrated controller.
In addition, unless the interrupt control register for the
interrupt is set in Special Fully Nested Mode, the
interrupt controller will prevent any interrupts from
occurring from the same interrupt line until the in-service
bit for that line has been cleared.

In master mode, the integrated interrupt controller is
the master interrupt controller of the system. As a result, no external interrupt controller need know when
the integrated controller is providing an interrupt vector,
nor when the interrupt acknowledge is taking place. As a
restilt, no interrupt acknowledge bus cycles will be generated. The first external indication that an interrupt
has been acknowledged will be the processor reading the
interrupt vector from the interrupt vector table in low
memory.

In master mode, the interrupt types associated with all
the interrupt sources are fixed and unalterable. These
interrupt types are given in Table 5. In response to an internal CPU interrupt acknowledge the interrupt controller will generate the vector address rather than the
interrupt type. On the 80186 (like the 8086) the interrupt vector address is the interrupt type multiplied by 4.
This speeds interrupt response.

3-588

AP-186

Table 5.

80186 Interrupt Vector Types

Interrupt
Name

Vector
Type

Default
Priority

timer 0
timer I
timer 2
DMAO
DMAI
INTO
INT I
INT 2
INT 3

8
18
19
10
11
12
\3
14
15

Oa
Ob
Oc
2
3
4
5
6
7

6.5.2

In iRMX 86 mode, the integrated interrupt controller
will present the interrupt type to the CPU in response to
the two interrupt acknowledge bus cycles run by the processor. During the first interrupt acknowledge cycle, the
external master interrupt controller determines which
slave interrupt controller will be allowed to place its interru pt vector on the microprocessor bus. During the
second interrupt acknowledge cycle, the processor reads
the interrupt vector from its bus. Thus, these two inter- .
rupt acknowledge cycles must be run, since the integrated controller will present the interrupt type information
only when the external interrupt controller signals the
integrated controller that it has the highest pending interrupt request (see Figure 59). The 80186 samples the

Because the two interrupt acknowledge cycles are not
run, and the interrupt vector address does not need be be
calculated, interrupt response to an internally vectored
interrupt is 42 clock cycles, which is faster then the interrupt response when external vectoring is required, or
if the interrupt controller is run in iRMX 86 mode.
If two interrupts of the same programmed priority occur,
the default priority scheme (as shown in table 5) is used.
T,

T,

T,

CLKOUT

INTERNAL VECTORING, iRMX'" 86 MODE

In iRMX 86 mode, the interrupt types associated with
the various interrupt sources are alterable. The upper 5
most significant bits are taken from the interrupt vector
register, and the lower 3 significant bits are taken from
the priority level of the device causing the interrupt. Because the interrupt type, rather than the interrupt vector
address, is given by the interrupt controller in this mode
the interrupt vector address must be calculated by the
CPU before servicing the interrupt.

T,

T,

T,

1

1

S~S2 ------~------~------~:-r----+-------+-------+----,-+-------+:------~I~~~-------1

1

1

1

1

1

INTE RUPT ACKNOWLEDGE
INTERRUPT ACKNOWLEDGE
INTO ______~------~------~------_+------_+------_+------_+'------_+'-----~'~~~~----(HIGH)
INT3
(HIGH)
CAS

------~------~------~------~------~------_r------_r------_r------~f_---~-----­
~~----~-'j~----~----~----~----~----~----~~~~;80186 SLAVE ENABLE C SCADE ADDRESS FROM 8259A

CD

------~------~---,\-~------~'------~:------~'-------'~---~'~---~'------~---.~--

SLAVE -------+-------+---~
SELECT
1

CD

-

INTA

1

1

,

1

1

~I..._--'_ _-'-_--'...J
;/

I

:\

1

/

LOCK4

,

I'---~----~---+----~----~---+----~
I
'I

1

1

1. SLAVE SELECT = INT1
2. INTA = INT2
3. Driven by external interrupt controller
4, SLAVE SELECT must be driven before Phase 2 of T2 of the second INTA

, QYQ!L--5, SLAVE SELECT read by 80186

Figure 59.

80186 iRMX-86 Mode Interrupt Acknowledge Timing

3-589

210973-003

AP-186

so- S2

INTA

ADO-AD7

:-i.__~_.1j-i-

-~--~--~--~--~--~--~-__

I
I

I

INTERRUPT TYPE
(FROM EXTERNAL
CONTROLLER)

Figure 60.

80186 Cascaded Interrupt Acknowledge Timing

SLAVE SELECT line during the falling edge of the
clock at the beginning of T 3 of the second interrupt acknowledge cycle. This input must be stable 20ns before
and IOns after this edge.
These two interrupt acknowledge cycles will be run back
to back, and will be LOCKED with the LOCK output
active (meaning that DMA requests and HOLD requests will not be honored until both cycles have been
run). Note that the two interrupt acknowledge cycles
will always be separated by two idle T states, and that
wait states will be inserted into the interrupt acknowledge cycle if a ready is not returned by the processor bus
interface. The two idle T states are inserted to allow
compatibility with the timing requirements of an external 8259A interrupt controller.
Because the interrupt acknowledge cycles must be run in
iRMX 86 mode, even for internally generated vectors,
and the integrated controller presents an interrupt type
rather than a vector address, the interrupt response time
here is the same as if an externally vectored interrupt
was required, namely 55 CPU clocks.

6.5.3

EXTERNAL VECTORING

External interrupt vectoring occurs whenever the 80186
interrupt controller is placed in cascade mode, special
fully nested mode, or iRMX 86 mode (and the integrated controller is not enabled by the external master interrupt controller). In this mode, the 80186 generates two
interrupt acknowledge cycles, reading the interrupt type

off the lower 8 bits of the address/data bus on the second
interrupt acknowledge cycle (see Figure 60). This interrupt response is exactly the same as the 8086, so that the
8259A interrupt controller can be used exactly as it
would in an 8086 system. Notice that the two interrupt
acknowledge cycles are LOCKED, and that two idle Tstates are always inserted between the two interrupt acknowledge bus cycles, and that wait states will be
inserted in the interrupt acknowledge cycle if a ready is
not returned to the processor. Also notice that the 80186
provides two interrupt acknowledge signals, one for interrupts signaled by the INTO line, and one for interrupts signaled by the INTI line (on the INT2/INTAO
and INT3/INTAI lines, respectively). These two interrupt acknowledge signals are mutually exclusive. Interr~t acknowledge status will be driven on the status lines
(SO-S2) when either INT2/INTAO or INn/
INTAI signal an interrupt acknowledge.

6.6

Interrupt Controller External
Connections

The four interrupt signals can be programmably configured ,into 3 major options. These are direct interrupt inputs (with the integrated controller providing' the
interrupt vector), cascaded (with an external interrupt
controller providing the interrupt vector), or iRMX 86
mode. In all these modes, any interrupt presented to the
external lines must remain set until the interrupt is
acknowledged.

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6.6.1

DIRECT INPUT MODE

When the Cascade mode bits are cleared, the interrupt
input lines are configured as direct interrupt input lines
(see Figure 61). In this mode an interrupt source (e.g.,
an 8272 floppy disk controller) may be directly connected to the interrupt input line. Whenever an interrupt is
received on the input line, the integrated controller will
do nothing unless the interrupt is enabled, and it is the
highest priority pending interrupt. At this time, the interrupt controller will present the interrupt to the CPU
and wait for an interrupt acknowledge. When the acknowledge occurs, it will present the interrupt vector address to the CPU. In this mode, the CPU will not run any
interrupt acknowledge cycles.

on the SO-S2 status lines. On the second pulse, the interrupt type will be read in. The 80186 externally vectored
interrupt response is covered in more detail in section
6.5.

8259A

80186

INT

INTO

INTA

INT2

8259A
INT

INT1

INTA

INT3

80186
INTO

.

INTERRUPT
SOURCES

,

Figure 61.

Figure 62.

INT1
INT2

INTO/INT2/INTAOand INTI/INT3/INTAI maybe
individually
programmed
into
interrupt
request/acknowledge pairs, or programmed as direct inputs. This means that INTO/INT2/INTAO may be
programmed as an interrupt/acknowledge pair, while
INTI and INT3/INTAI each provide separate internally vectored interrupt inputs.

INT3

80186 Non-Cascaded
Interrupt Connection

These lines can be individually programmed in either
edge or level triggered mode using their respective control registers. In edge triggered mode, a low-to-high
transition must occur before the Interrupt will be generated to the CPU, while in level triggered mode, only a
high level must be present on the input for an interrupt
to be generated. In edge trigger mode, the interrupt input must also be low for at least I CPU clock cycle to
insure recognition. In both modes, the interrupt input
must remain active until acknowledged.

6.6.2

80186 Cascade and SpeCial Fully
Nested Mode Interface

CASCADE MODE

When the Cascade mode bit is set and the SFNM bit is
cleared, the interrupt input lines are configured in cascade mode. In this mode, the interrupt input line is
paired with an interrupt acknowledge line. The INT2/
INTAO and INT3/INTAllines are dual purpose; they
can function as direct input lines, or they can function as
interrupt acknowledge outputs. INT2/INTAO provides
the interrupt acknowledge for an INTO input, and
INT3/INTAI provides the interrupt acknowledge for
an INTI input. Figure 62 shows this connection.
When programmed in this mode, in response to an interrupt request on the INTO line, the 80186 will provide
two interrupt acknowle~ses. These pulses will be
provided on the INT2/INTAO line, and will also be reflected by interrupt acknowledge status being generated
3-591

When an interrupt is received on a cascaded interrupt,
the priority mask bits and the in-service bits in the particular interrupt control register will be set into the interrupt controller's mask and priority mask registers.
This will prevent the controller from generating an
80186 CPU interrupt request from a lower priority interrupt. Also, since the in-service bit is set, any subsequent interrupt requests on the particular interrupt
input line will not cause the integrated interrupt controller to generate an interrupt request to the 80186 CPU.
This means that if the external interrupt controller receives a higher priority interrupt request on one of its interrupt request lines and presents it to the 80186
interrupt request line, it will not subsequently be presented to the 80186 CPU by the integrated interrupt
controller until the in-service bit for the interrupt line
has been cleared.

6.6.3

SPECIAL FULLY NESTED MODE

When both the Cascade mode bit and the SFNM bit are
set, the interrupt input lines are configured in Special
Fully Nested Mode. The external interface in this mode
is exactly as in Cascade Mode. The only difference is in
the conditions allowing an interrupt from the external
interrupt controller to the integrated interrupt controller to interrupt the 80186 CPU.
When an interrupt is received from a special fully nested
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mode interrupt line, it will interrupt the 80186 CPU if it
is the highest priority interrupt pending regardless of the
state of the in-service bit for the interrupt source in the
interrupt controller. When an interrupt is acknowledged
from a special fully nested mode interrupt line, the prioritytmask bits and the in-service bits in the particular
interrupt control register will be set into the interrupt
controller's in-service and priority mask registers. This
will prevent the interrupt controller from generating an
80186 CPU interrupt request from a lower priority interrupt. Unlike cascade mode, however, the interrupt
controller will not prevent additional interrupt requests
generated by the same external interrupt controller
from interrupting the 80186 CPU. This means that if
the external (cascaded) interrupt controller receives a
higher priority interrupt request on one of its interrupt
request lines and presents it to the integrated controller's interrupt request line, it may cause an interrupt to
be generated to the 80186 CPU, regardless of the state
of the in-service bit for the interrupt line.
If the SFNM mode bit is set and the Cascade mode bit is
not also set, the controller will provide internal interrupt
vectoring. It will also ignore the state of the in-service bit
in determining whether to present an interrupt request
to the CPU. In other words, it will use the SFNM conditions of interrupt generation with an internally vectored
interrupt response, i.e., if the interrupt pending is the
highest priority type pending, it will cause a CPU interrupt regardless of the state of the in-service bit for the
interrupt.
'
6.6.4

iRMX™ 86 MODE

When the RMX bit in the peripheral relocation register'
is set, the interrupt controller is set into iRMX 86 mode.

In this mode, all four interrupt controller input lines are
used to perform the necessary handshaking with the external master interrupt controller. Figure 63 shows the
hardware configuration of the 80186 interrupt lines
with an external controller in iRMX 86 mode.

ARDY

,

INTO

INT

INT2

INTA

.

INTl

-

~>

CASCADE
ADDR.
DECODE

INT3

Figure 63.

80186 iAMX86 Mode Interface

Because the integrated interrupt controller is a slave
controller, it must be able to generate an interrupt input
for an external interrupt controller. It also'must be signaled when it has the highest priority pending interrupt
to know when to place its interrupt vector on the bus.
These two signals are provided by thdNT3/Slave Interrupt Output and INTI /Slave Select lines, respectively. The external master interrupt controller must be able
to interrupt the 80186 CPU, and needs to know when the
interru~est is acknowledged. The INTO and
INT2/INTAO lines provide these two functions.

.--.

80186

8259A

80186

OTHERARDY

'U

INTO
10

INT2

EXTERNAL
INTERRUPTS

8259A-2
INTl

/

INT
8"

INT3
ADO-AD7

INTA
DO-D7

RD

RD

WR

WR

SP
CS

U

t

PCSA

Figure 64_

+5V

80186/8259A Interrupt Cascading
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The 80186 generates an interrupt request to the 80130
interrupt controller when one of the 80186 integrated
peripherals has created an interrupt condition, and that
condition is sufficient to generate an interrupt from the
80186 integrated interrupt controller. Note that the
80130 decodes the interrupt acknowledge status directly
from the 80186 status lines; thus, the INT2/INTAO
line of the 80186 need not be connected to the 80130.
Figure 65 uses this interrupt acknowledge signal to enable the cascade address decoder. The 80130 drives the
cascade address on AD8-ADIO during TI of the second
interrupt acknowledge cycle. This cascade address is
latched into the system address latches, and if the proper
cascade address is decoded by the 8205 decoder, the
80186 INTl/SLAVE SELECT line will be driven active, enabling the 80186 integrated interrupt controller
to place its interrupt vector on the internal bus. The code
to configure the 80186 into iRMX 86 mode is presented
in appendix E.

Example 8259A/Cascade Mode
Interface

Figure 64 shows the 80186 and 8259A in cascade interrupt mode. The code to initialize the 80186 interrupt
controller is given in Appendix E. Notice that an "interrupt ready" signal must be returned to the 80186 to prevent the generation of wait states in response to the
interrupt acknowledge cycles. In this configuration the
INTO and INT2 lines are used as direct interrupt input
lines. Thus, this configuration provides 10 external interrupt lines: 2 provided by the 80186 interrupt controller itself, and 8 from the external 8259A. Also, the
8259A is configured as a master interrupt controller. It
will only receive interrupt acknowledge pulses in response to an interrupt it has generated. It may be cascaded again to up to 8 additional 8259As (each of which
would be configured in slave mode).

6.8

Example 80130 iRMX™ 86 Mode
Interface

6.9

Figure 65 shows the 80186 and 80130 connected in
iRMX 86 mode. In this mode, the 80130 interrupt controller is the master interrupt controller of the system.

80186
ALE

ADDR

,2 6

ClK

V3

80130

A8-A 10

,-

ADO-AD15
ClK

MMCS2

MEMCS
IROIOCS IR7

PCS3

SO-52

AO-A15

lATCH

r-

ADO-AD15

Interrupt Latency

Interrupt latency time is the time from when the 80186
receives the interrupt to the time it begins to respond to
the interrupt. This is different from interrupt response

/3

,-

/

2

/

2

INTERRUPT
REQUESTS

..

SO-52

'

BHE

BHE
INT

J

INTO
INT3

U

+5

8205
E2
E3
INT2

El

INT1

7

Figure 65.

80186/80130 iRMX86 Mode Interface
;3-593

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AP-186

time, which is the time from when the processor actually
begins processing the interrupt to when it actually executes the first instruction of the interrupt service routine. The factors affecting interrupt latency are the
instruction being executed and the state of the interrupt
enable flip-flop.
Interrupts will be acknowledged only if the interrupt enable flip-flop in the CPU is set. Thus, interrupt latency
will be very long indeed if interrupts are never enabled
by the processor!
When interrupts are enabled in the CPU, the interrupt
latency is a function of the instructions being executed.
Only repeated instructions will be interrupted before being completed, and those only between their respective
iterations. This means that the interrupt latency time
could be as long as 69 CPU clocks, which is the time it
takes the processor to execute an integer divide instruction (with a segment override prefix, see below), the
longest single instruction on the 80186.

7.

CLOCK GENERATOR

The 80186 includes a clock: generator which generates
the main clock signal for aU 80186 integrated components, and all CPU synchronous devices in the 80186
system. This clock generator includes a crystal oscillator, divide by two counter, reset circuitry, and ready generation logic. A block diagr.am of the clock generator is
shown in Figure 66.

7.1

Crystal Oscillator

The 80186 crystal oscillator is a parallel resonant,
Pierce oscillator. It was designed to be used as shown in
Figure 67. The capacitor values shown are approximate.
As the crystal frequency drops, they should be increased, so that at the 4 MHz minimum crystal frequency supported by the 80186 they take on a value of 30pF.
The output of this oscillator is not directly available outside the 80186.

Other factors can affect interrupt latency. An interrupt
will not be, accepted between the execution of a prefix
(such as segment override prefixes and lock prefixes)
and the instruction. In addition, an interrupt will not be
accepted between an instruction which modifies any of
the segment registers and the instruction immediately
following the instruction. This is required to allow the
stack to be changed. If the interrupt were accepted, the
return address from the interrupt would be placed on a
stack which was not valid (the Stack Segment register
would have been modified but the Stack Pointer register
would not have been). Finally, an interrupt will not be
accepted between the execution of the WAIT instruction
and the instruction immediately following it if the TEST
input is fictive. If the WAIT sees the TEST input inactive, however, the interrupt will be accepted, and the
WAIT will be re-executed after the interrupt return.
This is required, since the WAIT is used to prevent execution by the 80186 of an 8087 instruction while the
8087 is busy.

The following parameters may be used for choosing a
crystal:
Temperature Range:
o to 70° C
ESR (Equivalent Series Resistance):
30n max
Co (Shunt Capacitance of Crystal):
7.0 pf max
C 1 (Load Capacitance):
20 pf ± 2 pf
I mw max
Drive Level:

80186

x,

x, t-------1
I2~F

Figure 67.

x,
x,

80186 Crystal Connection

CPU CLOCK &
CLOCKOUT

ARDY

-------~_Ir_;;;~-,

SRDY

-------It.::==~

FiR

r-----~~-----,

---------1

CPU
READY
CPU RESET
&

RESET OUTPUT

Figure 66.

80186 Clock Generator Block Diagram

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AP-186

EFI

CLKOUT

Figure 68.

7.2

80186 Clock Generator Reset

Using an External Oscillator

An external oscillator may be used with the 80186. The
external frequency input (EFI) signal is connected directly to the X 1 input of the oscillator. X2 should be left
open. This oscillator input is used to drive an internal divide-by-two counter to generate the CPU clock signal,
so the external frequency input can be of practically any
duty cycle, so long as the minimum high and low times
for the signal (as stated in the data sheet) are met.

7.3

Clock Generator

The output of the crystal oscillator (or the external frequency input) drives a divide by two circuit which generates a 50% duty cycle clock for the 80186 system. All
80186 timing is referenced to this signal, which is available on the CLKOUT pin of the 80186. This signal win
change state on the high-to-low transition of the EFI
signal.

7.4

The reset signal presented to the rest of the 80186, and
also the signal present on the RESET output pin of the
80186 is synchronized by the high-to-low transition of
the clockout signal of the 80186. This signal remains active as long as the RES input also remains active. After
the RES input goes inactive, the 80186 will begin to
fetch its first instruction (at memory location FFFFOH)
after 61/2 CPU clock cycles (Le., Tl of the first instruction fetch will occur 61/2 clock cycles later). To ins"ure
that the RESET output will go inactive on the next CPU
clock cycle, the inactive going edge of the RES input
must satisfy certain hold and setup times to the low-tohigh edge of the clockout signal of the 80186 (see Figure
69).

Ready Generation
RESET

The clock generator also includes the circuitry required
for ready generation. Interfacing to the SRDY and
ARDY inputs this provides is covered in section 3.1.6.

-----------,,1..___

Figure 69.

7.5

80186 Coming out of Reset

Reset

The 80186 clock generator also provides a synchronized
reset signal for the system. This signal is generated from
the reset input (RES) to the 80186. The clock generator
synchronizes this signal to the clockout signal.
The reset input signal also resets the divide-by-two
counter. A one clock cycle internal clear pulse is generated when the RES input signal first goes active. This
clear pulse goes active beginning on the first low-to-high
transition of the X 1 input after RES goes active, and
goes inactive on the next low-to-high transition of the X 1
input. In order to insure that the clear pulse is generated
on the next EFI cycle, the RES input signal must satisfy
a 25ns setup time to the high-to-low EFI input signal
(see Figure 68). During this clear, clockout will be high.
On the next high-to-low transition of XI, clockout will
go low, and will change state on every subsequent highto-low transition of EFI.

3-595

8.

CHIP SELECTS

The 80186 includes a chip select unit which generates
hardware chip select signals for memory and I/O accesses generated by the 80186 CPU and DMA units.
This unit is programmable such that it can be used to
fulfill the chip select requirements (in terms of memory
device or bank size and speed) of most small and medium sized 80186 systems.
The chip selects are driven only for internally generated
bus cycles. Any cycles generated by an external unit
(e.g., an external DMA controller) will not cause the
chip selects to go active. Thus, any external bus masters
must be responsible for their own chip select generation.
Also, during a bus HOLD, the 80186 does not float the
chip select lines. Therefore, logic must be included to enable the devices which the external bus master wishes to
access (see Figure 70).
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80186 CHIP SELECT~ _ MEMORY or I/O
E
...X..T...
E..
RN
..A
..L·L"Y"GCPEN
...E"'R..A"'T...
ED..-C"'HwIP....-..;SE
...L·E"'C"'T ~ DEVICE CHIP SELECT

Figure 70.

8.1

80186/External Chip Select/Device Chip Select Generation

Memory Chip Selects

The 80186 provides six discrete chip select lines which
are meant to be connected to memory components in an
80186 system. These signals are named UCS, LCS,
and MCSO-3 for Upper Memory Chip Select, Lower
Memory Chip Select and Midrange Memory Chip Selects 0-3. They are meant (but not limited) to be connected to the three major areas of the 80186 system
memory (see Figure 71).

FFFFF

STARTUP
ROM

MCS3 {

-PROGRAM
MCS2 {.

On reset, only UCS is active. It is programmed by reset
to be active for the top I K memory block, to insert 3 wait
states to all memory fetches, and to factor external
ready for every memory fetch (see section 8.3 for more
information on internal ready generation). All other
chip select registers assume indeterminate states after
reset, but none of the other chip select lines will be active
until all necessary registers for a signal have been accessed (not necessarily written, a read to an uninitialized
register will enable the chip select function controlled by
that register).

8.2

MEMORY

Peripheral Chip Selects

The 80186 provides seven discrete. chip select lines
which are meant to be connected to peripheral components in an 80186 system. These signals are named
PCSO-6. Each of these lines is active for one of seven
contiguous 128 byte areas in memory or I/O space
above a programmed base address.

--MCS1 {

--MCSO {

INTERRUPT
VECTOR
TABLE
0

Figure 71.

The memory chip selects are controlled by 4 registers in
the peripheral control block (see Figure 72). These include I each for UCS and LCS, the values of which determine the size of the memory blocks addressed by
these two lines. The other two registers are used to control the size and base address of the mid-range memory
block.

80186 Memory Areas & Chip Selects

As could be guessed by their names, upper memory, lower memory, and mid-range memory chip selects are designed to address upper, lower, and middle areas of
memory in an 80186 srtem. The upper limit of UCS
and the lower limit of CS are fixed at FFFFFH and
OOOOOH in memory space, respectively. The other limit
of these is set by the memory size programmed into the
control register for the chip select line. Mid-range memory allows both the base address and the block size of the
memory area to be programmed. The only limitation is
that the base address must be programmed to be an integer multiple of the total block size. For example, if the
block size was 128K bytes (4 32K byte chunks) the base
address could be 0 or 20000H, but not 10000H.'

The peripheral chip selects are controlled by two registers in the internal peripheral control block (see Figure
72). These registers allow the base address of the peripherals to be set, and allow the peripherals to be mapped
into memory or I/O space. Both of these registers must
be accessed before any of the peripheral chip selects will
become active.
A bit in the MPCS register allows PCS5 and PCS6
to become latched Al and A2 outputs. When this option
is selected, PCS5 and PCS6 will reflect the state of Al
and A2 throughout a bus cycle. These are provided to allow external peripheral register selection in a system in
which the addresses are not latched. Upon reset, these
lines are driven high. They will only reflect Al and A2
after both PACS and MPCS have been accessed (and
are programmed to provide Al and A2!).

8.3

Ready Generation

The 80186 includes a ready generation unit. This unit
generates an internal ready signal for all accesses to
memory or I/O areas to which the chip select circuitry of
the 80186 responds.

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OFFSET:

1.
2.
3.
4.
5.
6.

AOH

UPPER MEMORY SIZE

A2H

LOWER MEMORY SIZE

A4H

PERIPHERAL CHIP SELECT BASE ADDRESS

A6H

MID·RANGE MEMORY BASE ADDRESS

A8H

MID·RANGE MEMORY SIZE

I~ I ~ I

CD
CD
CD
CD
CD

UMCS
LMCS
PACS
MMCS
MPCS

Upper memory ready bits
Lower memory ready bits
PCSO-PCS3 ready bits
Mid·range memory ready bits
PCS4-PCS6 ready bits
MS: 1 = Peripherals active in memory space
= Peripherals active in I/O space
EX:1 = 7 PCS lines
0= PCS5 = A1, PCS6 = A2

o

Not all bits of every field are used

Figure 72.

80186 Chip Select Control Registers

:or each ready g.eneration area, 0-3 wait states may be
mserted by the mternal unit. Table 6 shows how the
ready c??trol bits should be programmed to provide this.
In addItIOn, the ready generation circuit may be programme~ to ignore the state of the external ready (i.e.,
only the Internal ready circuit will be used) or to factor
the state of the external ready (i.e., a ready will be returned to the processor only after both the internal ready
circuit has gone ready and the external ready has gone
ready). Some kind of circuit must be included to generate an external ready, however, since upon reset the
ready generator is programmed to factor external ready
to all accesses to the top 1K byte memory block. If a
ready was not returned on one of the external ready lines
(ARDYor SRDY) the processor would wait forever to
fetch its first instruction.
Table 6.

80186 Wait State Programming

R2

R1

RO

0
0
0
0
I
I
I
I

0
0
I
I
0
0
I
I

0
I
0
I
0
I
0
I

Number of Wait States

o + external ready
I
2
3

8.4

Examples of Chip Select Usage

M~ny exampl.es of the

use of the chip select lines are given m the bus mterface section of this note (section 3.2).
These examples show how simple it is to use the chip select function provided by the 80186. The key point to remember when using the chip select function is that they
are only activated during bus cycles generated by the
80186 CPU or DMA units. When another master has
the bus, it must generate its own chip select function. In
addition, whenever the bus is given by the 80186 to an
external master (through the HOLD/ HLDA arrange·
ment) the 80186 does NOT float the chip select lines.

8.5

Overlapping Chip Select Areas

Generally, the chip selects of the 80186 should not be
programmed such that any two areas overlap. In addition, none of the programmed chip select areas should
overlap any of the locations of the integrated 256-byte
control register block. The consequences of doing this
are:
Whenever two chip select lines are programmed to
respond to the same area, both will be activated during any access to that area. When this is done, the
ready bits for both areas must be programmed to the
same value. If this is not done, the processor response
to an access in this area is indeterminate.

+ external ready
+ external ready
+ external ready

o(no external ready required)
1 (no external ready required)
2 (no external ready required)
3 (no external ready required)

If any of the chip select areas overlap the integrated
256·byte control register block, the timing on the
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chip select line is altered. As always, any values returned on the external bus from this access are ignored.

9.

SOFTWARE IN AN 80186 SYSTEM

Since the 80186 is object code compatible with the 8086
and 8088, the software in an 80186 system is very similar to that in an 8086 system. Because of the hardware
chip select functions, however, a certain amount of initialization code must be included when using those functions on the 80186.

9.1

System Initialization in an
80186 System

Most programmable components of a computer system
must be initialized before they are used. This is also true
for the 80186. The 80186 includes circuitry which directly affects the ability of the system to address memory and I/O devices, namely the chip select circuitry.
This circuitry must be initialized before the memory
areas and peripheral devices addressed by the chip select
signals are used.
Upon reset, the UMCS register is programmed to be active for all memory fetches within the top 1K byte of
memory space. It is also programmed to insert three
wait states to all memory accesses within this space. If
the hardware chip selects are used, they must be programmed before the processor leaves this 1K byte area
of memory. If a jump to an area for which the chips are
not selected occurs, the microcomputer system will
cease to operate (since the processor will fetch garbage
from the data bus). Appendix F shows a typical initialization sequence for the 80186 chip select unit.
Once the chip selects have been properly initialized, the
rest of the 80186 system may be initialized much like an
8086 system. For example, the interrupt vector table
might get set up, the interrupt controller initialized, a
serial I/O channel initialized, and the main program begun. Note that the integrated peripherals included in the
80186 do not share the same programming model as the
standard Intel peripherals used to implement these
functions in a typical 8086 system, i.e., different values
must be programmed into different registers to achieve
the same function using the integrated peripperals. Appendix F shows a typical initialization sequence for an
interrupt driven system using the 80186 interrupt
controller.

9.2

model is not the same as is implemented by the 80186.
Because of this, the 80186 interrupt controller must be
placed in iRMX 86 mode after reset. This initialization
can be done at any time after reset before jump to the
root task of iRMX 86 System is actually performed. If
need be, a small section of code which initializes both
the 80186 chip selects and the 80186 interrupt controller
can be inserted between the reset vector loca tion and the
beginning of iRMX 86 System (see Figure 73). In this
case, upon reset, the processor would jump to the 80186
initialization code, and when this has been completed,
would jump to the iRMX 86 initialization code (in the
root task). It is "important that the 80186 hardware be
initialized before iRMX 86 operation is begun, since
some of the resources addressed by the 80186 system
may not be initialized properly by iRMX 86 System if
the initialization is done in the reverse manner.

8086

80186

FFFF:O

Figure 73.

9.3

iRMX-86 Initialization with
8086 & 80186

Instruction Execution Differences
Between the 8086 and 80186

There are a few instruction execution differences between the 8086 and the 80186. These differences are:

Initialization for iRMXTM 86 System

Using the iRMX 86 operating system with the 80186 requires an external 8259A and an external 8253/4 or alternatively an external 80130 OSF component. These
are required because the operating system is interrupt
driven, and expects the interrupt controller and timers to
have the register model -of these external devices. This
3-598

Undefined Opcodes:

When the opcodes 63H,64H,65H,66H,67H,F1H,
FEH XX111XXXB and FFH XX111XXXB
are executed, the 80186 will execute an illegal instruction exception, interrupt type 6. The 8086
will ignore the opcode.
OFH opcode:

When the opcode OFH is encountered, the 8086
will execute a POP CS, while the 80186 will execute an illegal instruction exception, interrupt
type 6.
Word Write at Offset FFFFH:

When a word write is performed at offset
FFFFH in a segment, the 8086 will write one
byte at offset FFFFH, and the other at offset 0,
while the 80186 will write one byte at offset
210973-003

AP-186

by 1 to include 8000H and 80H. These numbers
represent the most negative numbers representable using 2's complement arithmetic (equaling
- 32768 and -128 in decimal, respectively).

FFFFH, and the other at offset 10000H (one
byte beyond the end of the segment). One byte
segment underflow will also occur (on the 80186)
if a stack PUSH is executed and the Stack Pointer contains the value 1.

ESCOpcode:
Shift/Rotate by Value Greater Then 31:

The 80186 may be programmed to cause an interrupt type 7 whenever an ESCape instruction
(used for co-processors like the 8087) is executed. The 8086 has no such provision. Before the
80186 performs this trap, it must be programmed to do so.

Before the 80186 performs a shift or rotate by a
value (either in the CL register, or by an immediate value) it ANDs the value with 1FH, limiting
the number of bits rotated to less than 32. The
8086 does not do this.
LOCK prefix:

The 8086 activates its LOCK signal immediately
after executing the LOCK prefix. The 80186
does not activate the LOCK signal until the processor is ready to begin the data cycles associated
with the LOCKed instruction.
Interrupted String Move Instructions:

If an 8086 is interrupted during the execution of
a repeated string move instruction, the return
value it will push on the stack will point to the
last prefix instruction before the string move instruction. If the instruction had more than one
prefix (e.g., a segment override prefix in addition
to the repeat prefix), it will not be re-executed
upon returning from the interrupt. The 80186
will push the value of the first prefix to the repea ted instruction, so long as prefixes are not repeated, allowing the string instruction to
properly resume.
Conditions causing divide error with an integer
divide:

The 8086 will cause a divide error whenever the
absolute value of the quotient is greater then
7FFFH (for word operations) or if the absolute
value of the quotient is greater than 7FH (for
byte operations). The 80186 has expanded the
range of negative numbers allowed as a quotient

These differences can be used to determine whether the
program is being executed on an 8086 or an 80186.
Probably the safest execution difference to use for this
purpose is the difference in multiple bit shifts. For example, if a mUltiple bit shift is programmed where the shift
count (stored in the CL register!) is 33, the 8086 will
shift the value 33 bits, whereas the 80186 will shift it
only a single bit.
In addition to the instruction execution differences noted above, the 80186 includes a number of new instruction types, which simplify assembly language
programming of the processor, and enhance the performance of higher level languages running on the processor. These new instructions are covered in depth in the
8086/80186 users manual and in appendix H of this
note.

10.

CONCLUSIONS

The 80186 is a glittering example of state-of-the art integrated circuit technology applied to make the job of
the microprocessor system designer simpler and faster.
Because many of the required peripherals and their interfaces have been cast in silicon, and because of the
timing and drive latitudes provided by the part, the designer is free to concentrate on other issues of system design. As a result, systems designed around the 80186
allow applications where no other processor has been
able to provide the necessary performance at a comparable size or cost.

3-599

210973-003

AP-186

APPENDIX A:
BLOCK

PERIPHERAL CONTROL

All the integrated peripherals within the 80186 microprocessor are controlled by sets of registers contained
within an integrated peripheral control block. The registers are physically located within the peripheral devices
they control, but are addressed as a single block of registers. This set of registers fills 256 contiguous bytes and
can be located beginning on any 256 byte boundary of
the 80186 memory or I/O space. A map of these registers is shown in Figure A-I.

A.1

Setting the Base Location of the
Peripheral Control Block

In addition to the control registers for each of the integrated 80186 peripheral devices, the peripheral control

block contains the peripheral control block relocation
register. This register allows the peripheral control block
to be re-located 'on any 256 byt~ boundary within the
processor's memory or I/O space. Figure A-2 shows the
layout of this register.
This register is located at offset FEH within the peripheral control block. Since it is itself contained within the
peripheral control block, any time the location of the peripheral control block is moved, the location of the relocation register will also move.
In addition to the peripheral control Qlock relocation information, the relocation register contains two additional bits. One is used to set the interrupt controller into
iRMX86 compatibility mode. The other is used to force
the processor to trap whenever an ESCape (coprocessor)
instruction is encountered.

OFFSET
, Relocation Register

FEH

DAH
DMA Descriptors Channel 1
DOH

CAH
DMA Descriptors Channel 0
COH

ASH
Chip-Select Control Registers
AOH

66H

Timer 2 Control Registers
60H

/

5EH
Timer 1 Control Registers

58H
56H
Timer 0 Control Registers

SOH

Interrupt Controller Registers

3EH
20H

Figure A-1.

80186 Integrated Peripheral Control
3:'600

BI~ck

210973-003

AP-186

11

10

9

8

7

6

5

4

3

2

o

OFFSET: FEHL:~~~-=-i~:L__________~R~el~o~ca~t~io_n_A~d_d_re_S_S_B_it_S_R_1_9_-R_8____________~
ET
MIlO
RMX

= ESC Trap I No ESC Trap (1/0)
= Master Interrupt Controller mode/lRMX compatible

= Register block located in Memory 11/0 Space (1/0)
Interrupt Controller mode (011)

Figure A-2.

80186 Relocation Register Layout

Because the relocation register is contained within the
peripheral control block, upon reset the relocation register is automatically programmed with the value 20FFH.
This means that the peripheral control block will be located at the very top (FFOOH to FFFFH) of I/O space.
Thus, after reset the relocation register will be located at
word location FFFEH in I/O space.
If the user wished to locate the peripheral control block
starting at memory location 10000H he would program.
the peripheral control register with the value IIOOH. By
doing this, he would move all registers within the integrated peripheral control block to memory locations
lOOOOH to lOOFFH. Note that since the relocation register is contained within the peripheral control block, it
too would move to word location lOOFEH in memory
space.
I

Whenever mapping the 188 peripheral control block to
another location, the programming of the relocation
register should be done with a byte write (i.e. OUT
OX,AL). Any access to the control block is done 16 bits at
a time. Thus, internally, the relocation register will get
written with 16 bits of the AX register while externally, the
BI U will run only one 8 bit bus cycle. If a word Instruction
is used (i.e. OUT OX,A~), the relocation register will be
written on the first bus cycle. The BIU will then run a
'second bus cycle which is unnecessary. The address of the
second bus cycle will no longer be within the control block
(i.e. the control block was moved on the first cycle), and
therefore, will require the generation of an external ready
signal to complete the cycle,For this reason we recommend
byte operations to the relocation register. Byte instructions
may also be used for the other registers in the control
block and will eliminate half of the bus cycles required if a
word operation had been specified. Byte operations are
only valid on even addresses though, and are undefined on
odd addresses'.

3-601

A.2

Peripheral Control Block Registers

Each of the integrated peripherals' control and status
registers are located at a fixed location above the programmed base location of the peripheral control block.
There are many locations within the peripheral control
block which are not assigned to any peripheral. If a write
is made to any of these locations, the bus cycle will be
run, but the value will not be stored in any internallocation. This means that if a subsequent read is made to the
same location, the value written will not be read back.
The processor will run an external bus cycle for any
memory or I/O cycle which accesses a location within
the integrated control block. This means that the address, data, and control information will be driven on the
80186 external pins just as if a "normal" bus cycle had
been run. Any information returned by an external device will be ignored, however, even if the access was to a
location which does not correspond to any of the integrated penpheral control registers. The above is also true
for the 80188, except that the word access made to the
integrated registers will be performed in a single bus cycle
internally, while externally, the BIU runs two bus cycles.
The processor internally generates a ready signal whenever any of the integrated peripherals are accessed; thus
any external ready signals are ignored whenever an access is made to any location within the integrated peripheral register control block. This ready will also be
returned if an access is made to a location within the 256
byte area of the periperal control block which does not
correspond to any integrated peripheral control register.
The processor will insert 0 wait states to any access within the integrated peripheral control block except for accesses to the timer registers. ANY access to the timer
control and counting registers will incur I wait state.
This wait state is required to properly multiplex processor and counter element accesses to the timer control
registers.

210973-003

inter

AP-186

All accesses made to the integrated peripheral control
block will be WORD accesses. Any write to the integrated
registers will modify all 16 bits of the register, whether the
opcode specified a byte write or a word write. A byte read
from an even location should cause no problems, but the
qata returned when a byte read is performed from an odd
address within the peripheral control block is undefined.
This is true both for the 80186 AND the 80188. As stated
above, even though the 80188 has an external 8 bit data
bus, internally it is still a 16 bit machine. Thus, the word
~ccesses performed to the integrated registers by the 80188
will each occur in a single bus cycle internally while
externally the BIU runs two bus cycles.

STROBE
/
INPUT ---S""E"',,"".U""P-T""IM""E..I· HOLD TIME

·rr

ACTUAL SAMPLING INSTANT
INVALID

_ _ _....;JII}
1

~

INPUT
RESPONSE

-------1. RESOLUTION TIME _I

VALID~
INPUT

APPENDIX B: 80186 SYNCHRONIZATION
INFORMATION

-..J/

RESPONSE _ _ _ _ _ _ _

Many input signals to the 80186 are asynchronous, that
is, a specified set up or hold time is not required to insure
proper functioning of the device. Associated with each of
these inputs is a synchronizer which samples this external asynchronous signal, and synchronizes it to the internal 80186 clock.

B.1

Why Synchronizers Are Required

Every data latch requires a certain set up and hold time
in order to operate properly. At a certain window within
the specified set up and hold time, the part will actually
try to latch the data. If the input makes a transition
within this window, the output will not attain a stable
state within the given output delay time. The size of this
sampling window is typically much smaller than the actual window specified by the data sheet, however part to
part variation could move this window around within the
specified window in the data sheet.

,

.

Even if the input to a data latch makes a transition while
a data latch is attempting to latch this input, the output
of the latch will attain a stable state after a certain
amount of time, typically much longer than the. normal
strobe to output delay time. Figure B-1 shows a normal
input to output strobed transition and one in which the
input signal makes a transition during the latch's sample
window. In order to synchronize an asynchronous signal,
all one needs to do is to sample the signal into one data
latch, wait a certain amount of time, then latch it into a
second data latch. Since the time between the strobe into
the first data latch and the strobe into the second data
latch allows the first data latch to attain a steady state
(or to resolve the asynchronous signal), the second data
latch will be pre~ented with an input signal which satisfies any set up and hold time requirements it may have.

Figure B-1.

Valid & Invalid Latch Input
Transitions & Responses

Thus, the output of this second latch is a synchronous
signal with respect to its strobe input.
A synchronization failure can occur if the synchronizer
fails to resolve the asynchronous transition within the
time between the two latch's strobe signals. The rate of
failure is determined by the actual size of the sampling
window of the data latch, and by the amount of time between the strobe signals of the two latches. Obviously, as
the sampling window gets smaller, the number of times
an asynchronous transition will occur during the sampling window will drop. In additi<>i1, however, a smaller
sampling window is also indicative of a faster resolution
time for an input transition which manages to fall within
the sampling window.

B.2

80186 Synchronizets

The 80186 contains synchronizers on the RES,
TEST, TmrInO-I, DRQO-I, NMI, INTO-3, ARDY, and
HOLD input lines. Each of these synchronizers use the
two stage synchronization technique described above
(with some minor modifications for the ARDY line, see
section 3.1.6). The sampling window of the latches is designed to be in the tens of pico-seconds, and should allow
operation of the synchronizers with a mean time between failures of over 30 years assuming continuous
operation.

3-602

210973-003

'Im
_I®
•• ~

APPENDIX C:

AP.-186

80186 EXAMPLE DMA INTERFACE CODE

$modl86
name
This file contains an example procedure which initializes the 80186 DMA
controller to perform the DMA transfers between the 80186 system the the
8272 Floppy Disk Controller (FDC). It assumes that the 80186
peripheral control block has not been moved from its reset location.
argl
arg2
arg3
DMA_FROM_LOWER
DMA..FROM_UPPER
DMA_TO_LOWER
DMA..TO_UPPER
DMA_COUNT
DMA..CONTROL
DMA..TO_DlSK.CONTROL

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

word ptr [BP
word ptr [BP
word ptr [BP
OFFCOh
OFFC2h
OFFC4h
OFFC6h
OFFC8h
OFFCAh
01486h

+ 4]
+ 6]
+ 8]
DMA register locations

destination synchronization
source to memory, incremented
destination to 1/0
no terminal count
byte transfers
source synchroniza tion
source to 1/0
destination to memory, incr
no terminal count
byte transfers
FDC DMA address
FDC data register
FDC status register

OA046h

FDC_DMA
FDCDATA
FDCSTATUS

equ
equ
equ

6B8h
688h
680h

cgroup
code

group
segment
public
assume

code
public 'code'
seLdma_
cs:cgroup

seLdma (offset,to) programs the DMA channel to point one side to the
disk DMA address, and the other to memory pointed to by ds:offset. If
'to' = 0 then will be a transfer from disk to memory; if
'to' = I then will be a transfer from memory to disk. The parameters to
the routine are passed on the stack.
seLdma_

proc
enter
push
push
push
test

near
0,0
AX
BX
DX
arg2,1

set stack addressability
save registers used
check to see direction of
transfer

jz
from..disk
performing a transfer from memory to the disk controller
mov
rol

AX,DS
AX,4

get the segment value
gen the upper 4 bits of the
physical address in the lower 4
bits of the register
3-603

210973-003

AP-186

moy
moy
out
and

BX,AX
DX,DMA.FROM_VPPER
DX,AX
AX,OFFFOh

add
moy
out
jnc
inc
moy
moy
out

AX,argl
DX,DMA.FROM_LOWER
DX,AX
no_carry_from
BX
AX,BX
DX,DMA.FROM_VPPER
DX,AX

moy
moy
out
xor
moy
out
moy
moy
out
pop
pop
pop
leaye
ret

AX,FDCDMA
DX,DMA.TO_LOWER
DX,AX
AX,AX
DX,DMA.TO_VPPER
DX,AX
AX,DMA.TO_DISK.CONTROL;
DX,DMA.CONTROL
DX,AX
DX
BX
AX

saye the result. ..
prgm the upper 4 bits of the
DMA source register
form the lower 16 bits of the
physical address
add the offset
prgm the lower 16 bits of the
DMA source register
check for carry out of addition
if carry out, then need to adj
the upper 4 bits of the pointer

no_carry_from:
<

prgm the low 16 bits of the DMA
destina tion register
zero the up 4 bits of the DMA
destination register
I

prgm the DMA ctl reg
note: DMA may begin immediatly
after this word is output

from_disk:
performing a transfer from the disk to memory
moy
rol
moy
out
moy
and
add
moy
out jnc
inc
moy
moy
out

AX,DS

moy

AX,FDCDMA

moy
out
xor
moy
out
moy
moy

DX,DMA.FROM_LOWER
DX,AX
AX,AX
DX,DMA.FROM_VPPER
DX,AX
AX,DMA.FROM_DISK.CONTROL
DX,DMA.CONTROL

A~,4

DX,DMA.TO_VPPER
DX,AX
BX,AX
AX,OFFFOh
AX,argl
DX,DMA.TO_LOWER
DX,AX
no_carry_to
BX
AX,BX
DX,DMA.TO_VPPER
DX,AX

no_carry_to:

3-604

210973-003

AP-186

seLdma_
code

out
pop
pop
pop
leave
ret
endp

DX,AX
DX
BX
AX

ends
end

3-605

210973-003

inter

AP-186

APPENDIX D:

80186 EXAMPLE TIMER INTERFACE CODE

$modl86
name

example_80 I 86_timer_code

this file contains example 80186 timer routines. The first routine
sets up the timer and interrupt controller to cause the timer
to generate an interrupt every 10 milliseconds, and to service
interrupt to implement a real time clock. Timer 2 is used in '
this example because no input or output signals are required.
The code example assumes that the peripheral COnirol block has
not been moved from its reset location (FFOO·FFFF in I/O space).

+ 4]
+ 6]
+ 8]

argl
arg2
arg3
timer_2int
timer_2control
timer.2malLcti
timednLcti
eoi.register
interrupLstat

equ
equ
equ
equ
equ
equ
equ
equ
equ

data
msec_
hour_
minute_
second_
data

segment
public
db
db
db
db
ends

cgroup
dgroup

group
group

code
data

code

segment
public
assume

seUime_
cs:code,ds:dgroup

word ptr [BP
word ptr [BP
word ptr [BP
19
OFF66h
OFF62h
OFF32h
OFF22h
OFF30h

timer 2 has vector type 19

interrupt controller regs

public 'data'
hour_,minute_,second_,msec_

?
?
?
?

public 'code'

,
seUime(hour,minute,second) sets the time variables, initializes the
80186 timer2 to provide interrupts every 10 milliseconds, and
programs the interrupt vector for timer 2.
seUime_

proc
enter
push
push
push
push

near
0,0

xor

AX,AX

mov

OS,AX

mov

SI,4 * timer2..int

set stack addressability
save registers used

AX
OX
SI
OS

set the interrupt vector
the timers have unique
interrupt
vectors even though they share
the same control register

3-606

210973-003

inter

seUime_
timer2JnterrupLroutine

AP-186

mov
inc
inc
mov
pop

os: lSI] ,offset timer_2JnterrupLroutine
SI
SI
OS:[SI],CS
OS

mov
mov
mov
mov
mov
mov
mov

AX,argl
hour_,AL
AX,arg2
minute_,AL
AX,arg3
second.,AL
msec_,O

set the time values

mov
mov

OX,timer2..malLctl
AX,20000

set the max count value
10 ms /500 ns (timer 2 counts
at 1/4 the CPU clock rate)

out
mov
mov

OX,AX
OX,timer2..control
AX, 111 000000000000 1b

out

OX,AX

mov
mov

OX,timerinLctl
AX,OOOOb

out
sti

OX,AX

pop
pop
pop
leave
ret
endp

SI
OX
AX

proc
push
push

far
AX
OX

cmp
jae
inc
jmp

msec_,99
bump..second
msec_
reseLinLctl

see if one second has passed
if above or equal...

mov
cmp
jae
inc
jmp

mscc-,O
second.,59
bumpJIlinute
second_
reseLinLctl

reset millisecond
see if one minute has passed

mov
cmp
jae
inc
jmp

second.,O
minute_,59
bumpJtour
minute_
reseLinLctl

set the control word
enable counting
generate interrupts on TC
continuous counting
'set up the interrupt controller
unmask interrupts
highest priority interrupt
enable processor interrupts

bump..second:

bump_minute:

3-607

see if one hour has passed

210973-003

AP-186

bump.hour:
mov
cmp
jae
inc
jmp

minute.,O
hour., 12
reseLhour
hour.
reseLin Lctl

mov

hour., I

mov
mov
out

OX,eoLregister
AX,8000h
OX,AX

pop
pop
iret
endp
ends
end

OX
AX

see if 12 hours have passed

reseLhour:
reseLinLctl:

timer2.interrupLroutine
code
$modl86
name

non·specific end of interrupt

example.80 I 86.baud.code

this file contains example 80186 timer routines. The second routine
sets up the timer as a baud rate generator. In this mode,
Timer I is used to continually output pulses with a period of
6.S usec for use with a serial controller at 9600 baud
,
programmed in divide by 16 mode (the actual period required
for 9600 baud is 6.S1 usec). This assumes that the 80186 is
running at 8 MHz. The code example also assumes that the
peripheral control block has not been moved from its reset
location (FFOO·FFFF in I/O space).
timer Lcontrol
timer LmalLcnt

equ
equ

OFFSEh
OFFSAh

code

segment
assume

cs:code

public 'code'

seLbaudO initializes the 80186 timer! as a baud rate generator for
a serial port running at 9600 baud
seLbaud.

proc
push
push

near
·AX
OX

save registers used

mov
mov
out
mov
mov

OX,timerLmalLcnt
AX, 13
OX,AX
OX,timerLcontrol
AX, 11 0000000000000 1b

out

OX,AX

pop
pop

OX
AX

3-608

set the max count value
SOOns * 13 = 6.S usec
set the control word
enable counting
no interrupt on TC
continuous counting
single max count register

210973·003

AP-186

seLbaud.
code
$modl86
name

ret
endp
ends
end
example_80 I 86_counLcode

this file contains example 80186 timer routines. The third routine
sets up the timer as an external event counter. In this mode,
Timer I is used to count transitions on its input pin. After
the timer has been set up by the routine, the number of
events counted can be directly read from the timer count
register at location FF58H in I/O space. The timer will
count a maximum of 65535 timer events before wrapping
around to zero. This code examRle also assumes that the
peripheral control block has not been moved from its reset
location (FFOO-FFFF in I/O space).
timer Lcontrol
timer Lmax..cnt
timerLcnLreg

equ
equ
equ

OFF5Eh
OFF5Ah
OFF58H

code

segment
assume

cs:code

public 'code'

seLcountO initializes the 80186 timer! as an event counter
seLcounL

seLcounL
code

proc
pu&h
push

near
AX
DX

mov
mov

DX,timerLmax..cnt
AX,O

out
mov
mov

DX,AX
DX,timer Lcpntrol
AX,! 100000000000 I 0 I b

out

DX,AX

xor
mov
out

AX,AX
DX,timerLcnLreg
DX,AX

pop
pop
ret

DX
AX

save registers used

set the max count value
allows the timer to count
all the way to FFFFH
set the control word
enable counting
no interrupt on TC
continuous counting
single max count register
external clocking

zero AX
and zero the count in the timer
count register

endp
ends
end

3-609

210973-003

AP-186

APPENDIX E: 80186 EXAMPLE
INTERRUPT CONTROLLER INTERFACE
CODE
$mod186
name

example_80 186jnterrupLcode

This routine configures the 80186 interrupt controller to provide
two cascaded interrupt inputs (through an external 8259A
interrupt controller on pins INTO/INT2) and two direct
interrupt inputs (on pins INTI and INn). The default priority
levels are used. Because of this, the priority level programmed
into the control register is set the 111, the level all
interrupts are programmed to at reset.
intO,control
inLmask

equ
equ

OFF38H
OFF28H

cede

segment
assume
proc
push
push

CS:code
near
OX
AX

mov

AX,0100111B

mov
out

OX,intO_control
OX,AX

mov

AX,01001101B

mov
out
pop
pop
ret
endp
ends
end

OX,inLmask
OX, AX
AX
OX

seLinL

seLinL
code
$mod186
name

public 'code'

cascade mode
interrupt unmasked

now unmask the other external
interrupts

example_80 186jnterrupLcode

This routine configures the 80186 interrupt controller into iRMX 86
mode. This code does not initialize anyofthe 80186
integrated peripheral control registers, nor does it initialiie
the external 8259A or 80130 interrupt controller.
{

relocation_reg

equ

OFFFEH

code

segment
assume
proc
push
push

CS:code
near
OX
AX

mov
in
or
out

OX,relocation_reg
AX,OX
AX,O 1OOOOOOOOOOOOOOB
OX,AX

seUmx_

public 'code'

3~61O

read old contents of register
set the RMX mode bit
210973-003

AP·186

seLrmlL
code

pop
pop
ret
endp
ends
end

AX
DX

3-611

210973-003

inter

AP-186

APPENDIX F: 80186/8086 EXAMPLE
SYSTEM INITIALIZATION CODE
name
This file contains a system initialization routine for the 80186
or the 8086. The code determines whether it is running on
an 80186 or an 8086, and ifit is running on an 80186, it
initializes the integrated chip select registers.
restart

segment

at

OFFFFh

This is the processor reset address at OFFFFOH

restart
iniLhw

org
jmp
ends

0
far ptr initialize

extrn
segment
assume

monitor:far
at
CS:iniLhw

OFFFOh

This segment initializes the chip selects. It must be located in the
top lK to insure that the ROM remains selected in the 80186
system until the proper size of the select area can be programmed.
UMCS_reg
LMCS_reg
PACS_reg
MPCS_reg
UMCS_value
LMCS_value
PACS_value
MPCS_value

equ
equ
equ
equ
equ
equ
equ
equ

OFFAOH
OFFA2H
OFFA4H
OFFA8H
OF038H
07F8H
007EH
8lB8H

initialize

proc
mov
mov
shr
test
jz

far
AX,2
CL,33
AX,CL
AX,1
noL80186

mov
mov
out

OX,UMCSJeg
AX,UMCS_value
OX,AX

program the UMCS register

mov
mov
out

OX,LMCS_reg
AX,LMCS_value
OX,AX

program the LMCS register

mov

OX,PACSJeg

set up the peripheral chip
selects (note the mid-range
memory chip selects are not
needed in this system, and
are thus not initialized

mov
out

AX,PACS_value
OX,AX

chip select register locations

64K, no wait states
32K, no wait states
peripheral base at 400H, 2 ws
PCS5 and 6 supplies,
peripherals in I/O space
determine if this is an

, 8086 or an 80186 (checks
to see if the multiple bit
shift value was ANOed)

3-612

210973-003

AP-186

mov
mov
out

DX,MPCS_reg
AX,MPCS_value
DX,AX

Now that the chip selects are all set up, the main program of the
computer may be executed.
noL80186:
initialize
iniLhw

jmp
endp
ends
end

far ptr monitor

3-613

210973-003

inter

AP-186

APPENDIX G: 80186 WAIT STATE
PERFORMANCE
Because the 80186 contains seperate bus interface and
execution units, the actual performance of the processor
will not degrade at a constant rate as wait states are added to the memory cycle time from the processor. The actual rate of pefformace degradation will depend on the
type and mix of instructions actually encountered in the
user's program.
Shown below are two 80186 assembly language programs, and the actual execution time for the two programs as wait states are added to the memory system of
the processor. These programs show the two extremes to
which wait states will or will not effect system performance as wait states are introduced.
Program 1 is very memory intensive. It performs many
memory reads and writes using the more extensive memory addressing modes of the processor (which also take a
greater number of bytes in the opcode for the instruction). As a result, the eX!;lcution unit must constantly
wait for the bus interface unit to fetch and perform the
memory cycles to allow it to continue. Thus, the execution time of this type of routine will grow quickly as wait
states are added, since the execution time is almost totally limited to the speed at which the processor can run bus
cycles.
Note also that this program execution times calculated
by merely summing up the number of clock cycles given
in the data sheet will typically be less than the actual
number of clock cycles actually required to run the program. This is because the numbers quoted in the data
sheet assume that the opcode bytes have been prefetched
and reside in the 80186 prefetch queue for immediate
access by the execution unit. If the execution unit cannot

$modl86
name

access the opcode bytes immediatly upon request, dead
clock cycles will be inserted in which the execution unit
will remain idle, thus increasing the number of clock cycles required to complete execution of the program.
On the other hand, program 2 is more CPU intensive. It
performs many integer multiplies, during which time
the bus interface unit can fill up the instruction prefetch queue in parallel with the execution unit performing the multiply. In this program, the bus interface unit
can perform bus operations faster than the execution
unit actually requires them to be run. In this case, the
performance degradation is much less as wait states are
added to the memory interface. The execution time of
this program is closer to the number of clock cycles calculated by adding the number of cycles per instruction
because the execution unit does not have to wait for the
bus interface unit to place an opcode byte in the prefetch
queue as often. Thus, fewer clock cycles are wasted by
the execution unit laying idle for want of instructions.
Table G-I lists the execution times measured for these
two programs as wait states were introduced with the
80186 running at 8 MHz.

Table G-1

# of
Wait
States
0
I

2
3

Program 1
Exec
Time
Perf
(~sec)
Degr
505
595
669
752

18%
12%
12%

Program 2
Exec
Time
Perf
Degr
(~sec)
294
311
337
347

6%
8%
3%

example_waiLstate_performance

This file contains two programs which demonstrate the 80186 performance
degradation as wait states are inserted. Program I performs a
transformation between two types of characters sets, then copies
the transformed characters back to the original buffer (which is 64
bytes long. Program 2 performs the same type of transformation, however
instead of performing a table lookup, it multiplies each number in the
original 32 word buffer by a constant (3, note the use of the integer
immediate multiply instruction). Program "nothing" is used to measure
the call and return times from the driver program only.
cgroup
dgroup
data

group
group
segment

code
data
public 'data'
3-614

210973-003

inter

AP-186

Ltable
Lstring
IILarray
data

db
db
dw
ends

256 dup (7)
64 dup (7)
32 dup (7)

code

segment
assume
public
proc
push
push
push,
push

public 'code'
eS:cgroup,DS:dgroup
bench_I,bench..2,nothing..,waiLstate_,seUimer_
near
SI
; save registers used
ex
BX
AX

mov
mov
mov

eX,64
SI,O
BH,O

mov
mov
mov
inc
loop

BL,Lstring[SIJ
AL,Ltable[BXJ
Lstring [SIJ,AL
SI
loop_back

pop
pop
pop
pop
ret
endp

AX
BX
ex
SI

proc
push
push
push

near
AX
SI
ex

mov
mov

eX,32
Sl,offset IILarray

multiply 32 numbers

imul
mov
inc
inc
loop

AX,word ptr [SI],3
word ptr [SIJ,AX
SI
SI
loop-back-2

immediate multiply

pop
pop
pop
ret
endp

ex
SI
AX

bench..l

; translate 64 bytes

loop_back:

bench_l
bench..2

get the byte
translate byte
and store it
increment index
do the next byte

save registers used

loop_back-2:

bench..2.

3-615

210973-003

AP-186

nothing.
nothing.

proc
ret
endp

near

waiLstate(n) sets the 80186 LMCS register to the number of wait states
(0 to 3) indicated by the parameter n (which is passed on the stack).
No other bits of the LMCS register are modified.
wait-state.

proc
enter
push
push
push

near
0,0
AX
BX
DX

mov
mov

BX,word ptr [BP
DX,OFFA2h

in

AX,DX

and
and
or
out

AX,OFFFCh
BX,3
AX,BX
DX,AX

pop
pop
pop
leave
ret
endp

DX
BX
AX

set up stack frame
save registers used

+ 4]

get argument
get current LMCS register

contents

waiLstate.

and off existing ready bits
insure ws count is good
adjust the ready bits
and write to LMCS

tear down stack frame

seuimerO initializes the 80186 timers to count microseconds. Timer 2
is set up as a prescaler to timer 0, the microsecond count can be read
directly out of the timer 0 count register at location FF50H in I/O
space.
seUimer.

proc
push
push

near
AX
DX

mov
mov
out

DX,Off66h
AX,4000h
DX,AX

stop timer 2

mov
mov
out

DX,Off50h
AX,O
DX,AX

clear timer 0 count

mov
mov
out

DX,Off52h
AX,O
DX,AX

timer 0 counts up to 65535

3-616

210973-003

AP-186

seLtimer_
code

moy
moy
out

OX,Off56h
AX,OcOO9h
OX,AX

enable timer 0

moy
moy
out

OX,Off60h
AX,O
OX,AX

clear timer 2 count

moy
moy
out

OX,Off62h
AX,2
OX,AX

set maximum count of timer 2

moy
moy
out

OX,Off66h
AX,OcOOlh
OX,AX

re-enable timer 2

pop
pop
ret
endp
ends
end

OX
AX

3-617

210973-003

inter

AP-186

immediate value. This is different from the 8086, where
only a single bit shift can be performed, or a multiple
shift can be perf0rmed where the number of bits to be
shifted is specified in the CL register.

APPENDIX H: 80186 NEW INSTRUCTIONS
The 80186 performs many additional instructions to
those of the 8086. These instructions appear shaded in
the instruction set summary at the back of the 80186
data sheet. This appendix explains the operation of these
new instructions. In order to use these new instructions
with the 8086/186 assembler, the "$mod186" switch
must be given to the assembler. This can be done by placing the line: "$modI86" at the beginning of the assembly language file.

All of the shift/rotate instructions of the 80186 allow
the number of bits shifted· to be specified by an immediate value. Like all multiple bit shift operations performed by the 80186, the number of bits shifted is the
number of bits specified modulus 32 (Le. the mal\imum
number of bits shifted by the 80186 multiple bit shifts is
31).

PUSH immediate

These instructions require two operands: the operand to
be shifted (which may be a register or a memory location
specified by any of the 80186 addressing modes) and the
number of bits to be shifted.

This instruction allows immediate data to be pushed
onto the processor stack. The data can be either an immediate byte or an immediate word. If the data is a byte,
it will be sign extended to a word before it is pushed onto
the stack (since all stack operations are word
opera tions).

block input/output

The 80 18~ adds two new input/output instructions: INS
and OUTS. These instructions perform block input or
output operations. They operate similarly to the string
mov.e instructions of the processor.

PUSHA, POPA

The INS instruction performs block input from an I/O
port to memory. The I/O address is specified by the DX
register; the memory location is pointed to by the DI register. After the operation is performed, the DI register is
adjusted by I (if a byte input is specified) or by 2 (if a
word input is specified). The adjustment is either an increment or a decrement, as determined by the Direction
bit in the flag register of the processor. The ES segment
register is used for memory addressing, and cannot be
overridden. When preceeded by a REPeat prefix, this instruction allows blocks of data to be moved from an I/O
address to a block of memory Note that the I/O address
in the DX register is not modified by this operation.

These instructions allow all of the general purpose
80186 registers to be saved on the stack, or restored from
the stack. The registers saved by this instruction (in the
order they are pushed onto the stack) are AX, CX, DX,
BX, SP, BP, SI, and DI. The SP value pushed onto the
stack is the value of the register before the first PUSH
(AX) is performed; the value popped for the SP register
is ignored.
This instruction does not save any of the segment registers (CS, DS, SS, ES), the instruction pointer (lP), the
flag register, or any of the integrated peripheral
registers.
IMUL by an immediate value

This instruction allows a value to be multiplied by an immediate ·value. The result of this operation is 16 bits
long. One operand for this instruction is obtained using
one of the 80186 addressing modes (meaning it can be in
a register or in memory). The immediate value can be
either a byte or a word, but will be sign extended if it is a.
byte. The 16-bit result of the mUltiplication can btl
placed in any of the 80186 general purpose or pointer
registers.
This instruction requires three operands: the register in
which the result is to be placed. the immediate value,
and the second operand. Again, this second operand can
be any of the 80186 general purpose registers or a speci-.
fied memory location.
shifts/rotates by an immediate value

The 80186 can perform multiple bit shifts or rotates
where the number of bits to be shifted is specified by an

3-618

The OUTS instruction performs block output from
memory to an I/O port. The I/O address is specified by
the DX register; the memory location is pointed to by the
SI register. After the operation is performed, the SI register is adjusted by I (if a byte output is specified) or by
2 (if a word output is specified). The adjustment is either
an increment or a decrement, as determined by the Direction bit in the flag register of the processor. The DS
segment register is used for memory addressing, but can
be overridden by using a segment override prefix. When
preceeded by a REPeat prefix, this instruction allows
blocks of data to be moved from a block of memory to an
I/O address. Again note that the I/O address in the DX
register is not modified by this operation.
Like the string move instruction, these two instructions
require two operands to specify whether word or byte operations are to take place. Additionally, this determination can be supplied by the mnemonic itself by adding a
"B"·or "W" to the basic mnemonic, for example:
lNSB
; perform byte input
REP OUTSW ; perform word block output
210973-003

AP-186

BOUND

The 80186 supplies a BOUND instruction to facilitate
bound checking of arrays. In this instruction, the calculated index into the array is placed in one of the general
purpose registers of the 80186. Located in two adjacent
word memory locations are the lower and upper bounds
for the array index. The BOUND instruction compares
the register contents to the memory locations, and if the
value in the register is not between the values in the
memory locations, an interrupt type 5 is generated. The
comparisons performed are SIGNED comparisons. A
register value equal to either the upper bound or the lower bound will not cause an interrupt.
This instruction requires two arguments: the register in
which the calculated array index is placed, and the word
memory location which contains the lower bound of the
array (which can be specified by any of the 80186 memory addressing modes). The memory location containing
the upper bound of the array must follow immediatly the
memory location containing the lower bound of the
array.
ENTER and LEAVE

The 80186 contains two instructions which are used to
build and tear down stack frames of higher level, block
structured languages. The instruction used to build
these stack frames is the ENTER instruction. The algorithm for this instruction is:
PUSH BP
if level = 0 then
BP:= SP;
else
tempi := SP;

/*

save the previous
pointer */

frame

1* save current frame

pointer

*/

temp2 : = level - I;
do while temp2 > 0

1*

level

BP:= BP- 2;
PUSH [BP];
BP:= tempi;
PUSH BP;

/*

frame

1* in the save area */
SP:= SP - disp;

copy down previous
frame * /
1* pointers */
put current level
pointer */

1*
for

create space on the

*/

stack

1* local variables */
Figure H-I shows the layout of the stack before and
after this operation.
This instruction requires two operands: the first value
(disp) specifies the number of bytes the local variables of
this routine require. This is an unsigned value and can be
as large as 65535. The second value (level) is an unsigned value which specifies the level of the procedure. It
can be as great as 255.
The 80186 includes the LEAVE instruction to tear down
stack frames built up by the ENTER instruction. As can
be seen from the layout of the stack left by the ENTER
instruction, this involves only moving the contents of the
BP register to the SP register, and popping the old BP
value from the stack.
Neither the ENTER nor the LEAVE instructions save
any of the 80186 general purpose registers. If they must
be saved, this must be done in addition to the ENTER
and the LEAVE. In addition, the LEAVE instruction
does not perform a return from a subroutine. If this is
desired, the LEAVE il).struction must be explicitly followed by the RET instruction.

?

BP~

BEFORI:

AFTER

SP-BP_

OLDBP

f--

OLD FRAME
PTRS.

I

CURRENT FRAME
PTR

SP-

Figure ,H-1.

-

LOCAL
VARIABLE
AREA

ENTER Instruction Stack Frame

3-619

210973-003

AP-186

APPENDIX I: 80186/80188 DIFFERENCES

The DMA controller. of the 80188 only performs
byte transfers. The B/W bit in the DMA control
word is ignored.

The 80188 is exactly like the 80186, except it has an 8 bit
external bus. It shares the 'same execution unit, timers,
peripheral control block, interrupt controller, chip select, and DMA logic. The differences between the two
caused by the narrower data bus are:
The 80188 has a 4 byte prefetch queue, rather than
the 6 byte prefetch queue present on the 80186. The
reason for this is since the 80188 fetches opcodes one
byte at a time, the number of bus cycles required to
fill the smaller queue of the 80188 is actually greater
than the number of bus cycles required to fill the
queue of the 80186. As a result, a smaller queue is
required to prevent an inordinate number of bus cycles being wasted by prefetching opcodes to be discarded during a jump.
AD8-ADI5 on the 80186 are transformed to A8A15 on the 80188. Valid address information is present on t~ese lines throughout the bus cycle of the
80188. Valid address information is not guaranteed
on these lines during idle T states.
BHE/S7 is always defined HIGH by the 80188,
since the upper half of the data bus is non-existant.

Execution times for many memory access instructions are increased because the memory access must
be funnelled through a narrower data bus. The
80188 also will be more bus limited than the 80186
(that is, the execution unit will be required to wait
for the opcode information to be fetched more often)
because the data bus is narrower. The execution time
within the processor, however, has not changed between the 80186 and the 80188.
Another important point is that the 80188 internally is a
16-bit machine. This means that any access to the integrated peripheral registers of the 80188 will be done in
16-bit chunks, NOT in 8-bit chunks. All internal peripheral registers are still 16-bits wide, and only a single read
or write is required to access the registers. When an access is made to the internal registers, only a single bus
cycle will be run, and only the lower 8-bits of the written
data will be driven on the external bus. All accesses to
registers within the integrated peripheral block must be
WORD accesses.

3-620

210973-003

iAPX286
Microprocessors

4

iAPX 286/1 0
£@'I§£~©~ O~IF@IRl~£'jj'O@~
HIGH PERFORMANCE MICROPROCESSOR
WITH MEMORY MANAGEMENT AND PROTECTION
(80286-8, 80286-6, 80286-4)
Performance
• High
Processor (Up to six times iAPX 86)
Large Address Space:
• -16-Megabytes
Physical

•
•
•

Optional Processor Extension:
• -iAPX
286/20 High Performance 8o-bit
Numeric Data Processor

-1 Gigabyte Virtual per Task
Integrated Memory Management, FourLevel Memory Protection and Support
for Virtual Memory and Operating
Systems
Two iAPX 86 Upward Compatible
Operating Modes:
-iAPX 86 Real Address Mode
-Protected Virtual Address Mode
Range of clock rates
-8 MHz for 80286-8
-6 MHz for 80286-6
-4 MHz for 80286-4

System Development
• Complete
Support:
-Development Software: Assembler,
PUM, Pascal, FORTRAN, and System
Utilities
-In-Circuit-Emulator (ICE ™ -286)
Bandwidth Bus Interface
• High
(8
Mega~yte/Sec)

• Available in EXPRESS:
-Standard Temperature Range

The IAPX 286/10 (80286 part number) is an advanced, high-performance microprocessor with specially optimized
capabilities for multiple user and multi-tasking systems. The 80286 has built-in memory protection that supports
operating system and task isolation as well as program and data privacy within tasks. An 8 MHz iAPX 286/10 provides
up to six times greater throughout than the standard 5 MHz IAPX 86/10. The 80286 includes memory management
capabilities that map up to 230 (one gigabyte) of virtual address space per task into 224 bytes (16 megabytes)
of physical memory.
The iAPX 286 is upward compatible with iAPX 86 and 88 software. Using iAPX 86 real address mode, the 80286 is
object code compatible with existing iAPX 86, 88 software. In protected virtual address mode, the 80286 is source
code compatible with iAPX 86, 88 software and may require upgrading to use virtlJal addresses supported by the
80286's integrated memory management and protection mechanism. Both modes operate at full 80286 performance
and execute a superset of the iAPX 86 and 88's instructions.
The 80286 provides special operations to support the efficient implementation and execution of operating systems.
For example, one instruction can end execution of one task, save its state, switch to a new task, load its state, and
start execution of the new task. The 80286 also supports virtual memory systems by providing a segment-not-present
exception and restartable instructions.
~ADDRESSUNl'r(AU)

- - --- - - - - - - - - - - - - - -,
A23 - Ao.

I

SHE. MilO

I
I
I

PEACK
I-~-PEREQ

'----i+~~-REAOY. HOLD
S1, so, COD,I~fTA
lOcK, HLDA

I

I
I
I
L __

I
I
I

RESET

I

elK

I

~

~ ~E~u:!'I~N~~T.!.E~ __'--_-_-_-_-_'r_r_.-:r"'..-----:-:--L2~~L==..J

Vee

L-~~~~~~~~~~~Ff~~~~~~~~-~~~~~~~~~~~~~~~~CAP

Figure 1. 80286 Internal Block Diagram
The follOWing are trademarks of Intel Corporation and tts affltlstesand may be used only to Identify Intel products exp, CREDIT, I, ICE, ICS, 1m, InSlte, Intel, INTEl,lnteleVISlon, Intelhnk,

~~e~:~~,~~~~: ~~~~:~~~~~p~: ~~~~h~S!~~:~~~;~n~~~~~;R~~~;s~~~;~~~~~~~2~e~,a~g~~~~u~:C:~::~~;:;:;~~~u~~:~Y~'e~~~;~~~~t~~~' :~~~.~~~~~b~~:p~~~:i;t~~~~t~:r:~
of Any CIrcuItry Other Than CIrcuItry EmbodIed In an Intel Product No Other Patent llcenSf'lS are Implied ©INTEl CORPORATION, 1983

4-1

NOVEMBER 1983

ORDER NUMBER: 210253-007

IAPX 286/10

Component,Pad View-As viewed from
underside of component when mounted on
the board.

P.C: Board View-As viewed from the
component side of the P.C. board.

.

,
""
"

A,
A,

l.JL...JL..JLJL.JLJL.JULJLJLJLJLJ UL.JU

c:

A,

A,
eLK

:~. ~

eLK
Vee
RESET

I:T~

~

NUl

,'
,
""
""

Vss
PEREQ

HOLD

HLDA

eolllllM

MI11l
~

.
Vee
RESET
A,

l

r11r lrlrlnrlrlr lr lnr lr lrlrl rlrl r

A"

PINHO 1 MARK

NOTE: N.C. pads must not be connected.

Figure 2.

80286 Pin Configuration

Table 1. Pin Description
The following pin function descriptions are for the 80286 microprocessor:
Symbol
elK

~pe

I

015-00

I/O

A23-Ao

0

BHE

0

Name and Function
System Clock provides the fundamental timing for IAPX 286 systems. It is divided by two inside
the 80286 to generate the processor clock. The internal dlvlde-by-two circuitry can
be synchronized to an external clock generator by a lOW to HIGH transition on the RESET
Input.

Data Bus inputs data during memory. I/O. and interrupt acknowledge read cycles; outputs data
during memory and I/O write cycles. The data bus is active HIGH and floats to '3-state OFF during
bus hold acknowledge.
Address Bus outputs physioal memory and I/O port addresses. AD is LOW when data is to be
transferred on pins 07-0. A23-A16 are lOW during I/O transfers. The address bus is active HIGH
and floats to 3-state OFF during bus hold acknowledge.
Bus High Enable indicates transfer of data on the upper byte of the data bus. DI5:::a:...Eight-bit
oriented devices ~igne limit.
Data segment may not be written into.
Data segment may be written into.

3
2

Executable (E)
Conforming (C)

E= 1
C = 1

1

Readable (R)

R=O
R= 1

Code segment may not be read.
Code segment may be read.

0

Accessed (A)

A=O
A = 1

Segment has not been accessed.
Segment selector has been loaded into segment register or used
by selector test instructions.

4

3
2

L

Cod,

Sogmoo' ""'"""e ,po ;"

J"J'

Data
Segment
(5 = 1,
E = 0)

Code segment may only be executed when CPL 2:: DPL
and CPL remains unchanged.

~Ode t
egmen
(5 - 1
E =- 1)'

• .

Figure 11. Code and Data Seg'T'ent Descriptor Formats
4-15

210253-007

iAPX 286/10

System Segment Descriptor

Code and data (including stack data) are stored in two
types of segments: code segments and data segments.
Both types are identified and defined by segment descriptors (S = 1). Code segments are identified by the executable (E) bit setto 1 in the descriptor access rights byte. The
access rights byte of both code and data segment descriptor types have three fields in common: present (P) bit,
Descriptor Privilege Level (DPL), and accessed (A) bit.
If P = 0, any attempted use of this segment will cause
a not-present exception. DPL specifies the privilege level
of the segment descriptor. DPL controls when the descriptor may be used by a task (refer to privilege discussion
below). The A bit shows whether the segment has been
previously accessed for usage profiling, a necessity for
virtual memory systems. The CPU will always set this bit
when accessing the descriptor.

o7
+7

+p+1

+5

INTEL RESERVED'

+6

I

+4

TYtE,

BASE23-16

BASE15-0

+3

+2

L1M1T15-0

+1
15

8 7

• MUlt be ••t to 0 for compatablllty with lAPX 386.

System Segment Descriptor Fields

Data segments (S = 1, E = 0) may be either read-only or
read-write as controlled by the W bit of the access rights
byte. Read-only (W = 0) data segments may not be written into. Data'segments may grow in two directions, as
determined by the Expansion Direction (ED) bit: upwards (ED = 0) for data segments, and downwards
(ED = 1) for a segment containing a stack, The limit field
for a data segment descriptor is interpreted differently
depending on the ED bit (see Figure 11),
.

Name

Value

TYPE

1
2

3
0

P

Description
!\vailable Task State Segment (TSS)
Local Descriptor Table
§.i,!§y Task State Segment (TSS)
Descriptor contents are not valid
Descriptor contents are valid

1

Descriptor Privilege Level

DPL

0-3

BASE

24-bit
number

Base Address of special system data
segment in real memory

LIMIT

16-bit
number

Offset of last byte in segment

Figure

12.

System Segment Descriptor Format

A code segment (S = 1, E = 1) may be execute-only
or execute/read as determined by the Readable (R)
bit. Code segments may never be written into and
execute-only code segments (R=O) may not be read.
A code segment may also have an attribute called
conforming (C). A conforming code segment may be
shared by programs that execute at different privilege levels. The DPL of a conforming code segment
defines the range of privilege levels at which the
segment may be executed (refer to privilege discussion below). The limit field identifies the last byte of
a code segment.
"

is a system cClntrol descriptor. The type field specifies
the descriptor type as indicated in Figure 12.
GATE DESCRIPTORS (S =

0, TYPE = 4-7)

Gates are used to control access to entry points within
the target code segment. The gate descriptors 'are call
gates, task ;gates, interrupt gates and !@Q gates. Gates
provide a level of indirection between the source and
destination of the control transfer, This indirection allows
the CPU to automatically perform protection checks and
control entry point of the destination. Call gates are used
to change privilege levels (see Privilege), task gates are
used to perform a task switch, and interrUpt and trap
gates are used to specify interrupt service routines. The
interrupt gate disables interrupts (resets IF) while the
trap gate does not.

SYSTEM SEGMENT DESCRIPTORS (S = 0, TYPE = 1-3)
In addition to code and data segment descriptors, the protected mode 80286 defines System Segment Descriptors,
These descriptors define special system data segments
which contain a table of descriptors (Local Descriptor
Table Descriptor) or segments which contain the execution state of a task (Task State Segment Descriptor).

Figure 13 shows the format of the gate descriptors. The
descriptor contains a destination pointer that points to
the descriptor of the target segment and the entry point
offset. The destination selector in an interrupt gate, trap
gate, and call gate must refer to a code segment descriptor. These gate descriptors contain the entry point
to prevent a program from constructing and using an
illegal entry point. Task gates may only refer to a task
state segment. Since task gates invoke a task switch,
the destination offset is not used in the task gate.

Figure 12 gives the formats for the special system data
segment descriptors. The descriptors contain a 24-bit
base address of the segment and a 16-bit limit. The
access byte defines the type of descriptor, its state and
privilege level. The descriptor contents are valid and the
segment is in physical memory if P = 1. If P = 0, the
segment is not valid. The DPL field is only used in Task
State S,egment descriptors and indicates the privilege
level at which the descriptor may be used (see Privilege).
Since the Local Descriptor Table descriptor may only be
used by a special privileged instruction, the DPL field is
not used. Bit 4 of the access byte is 0 to indicate that it

Exception 13 is generated when the gate is used if a
destination selector does not refer to the correct de-

4-16

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iAPX 286/10

ception 11 if referenced. DPL is the descriptor privilege
level and specifies when this descriptor may be used by
a task (refer to privilege discussion below). Bit 4 must
equal 0 to indicate a system control descriptor. The type
field specifies the descriptor type as indicated in Figure
13.

Gate Descriptor

.7
+5

+6

INTEL RESERVED'

+7
+PLIOI

TYPE

Ix x xl

..

+4

Ix x

+2

~g:r

DESTINAnON SELECTOR,s-.

+3

SEGMENT DESCRIPTOR CACHE REGISTERS

DESTINATION OFFSET'5-0

+1

A segment descriptor cache register is assigned to each
of the four segment registers (es. 55, OS, ES). Segment
descriptors are automatically loaded (cached) into a segment descriptor cache register (Figure 14) whenever the
associated segment register is loaded with a selector.
Only segment descriptors may be loaded into segment
descriptor cache registers. Once loaded, all references
to that segment of memory use the cached descriptor
information instead of reaccessing the descriptor. The
descriptor cache registers are not visible to programs.
No instructions exist to store their contents. They only
change when a segment register is loaded.

87

15

*Mult ba HI to 0 tor compltlbility with IAPX 388. (X I. don't care)

Gate Descriptor Fields
Description
value
-Call Gate
4
5
-Task Gate
TYPE
-Interrupt Gate
6
7
-Trap Gate
-Descriptor Contents are not
P
0
valid
1
-Descriptor Contents are
valid
DPL
Descriptor Privilege Level
0-3
Number of words to copy
WORD
COUNT
from callers stack to called
0-31
procedures stack. Only used
with call gate.
Selector to the target code
segment (Call, Interrupt or
DESTINATION
16-bit Trap Gate)
SELECTOR
selector
Selector to the target task
state segment (Task Gate)
DESTINATION
16-bit Entry pOint within the target
OFFSET
offset code segment

Name

SELECTOR FIELDS
A protected mode selector has three fields: descriptor
entry index, local or global descriptor table indicator (TI),
and selector privilege (RPL) as shown in Figure 15. These
fields select one'of two memory based tables of descriptors, select the appropriate table entry and allow highspeed testing of the selector's privilege attribute (refer
to privilege discussion below).
SELECTOR

II

Figure 13. Gate Descriptor Format
BITS

scriptor type. The word count field is used in the call gate
descriptor to indicate the number of parameters (0-31
words) to be automatically copied from the caller's stack
to the stack of the called routine when a control transfer
changes privilege levels. The word count field is not used
by any other gate descriptor.
The access byte format is the same for all gate descriptors. P = 1 indicates that the gate contents are valid. P
= 0 indicates the contents are not valid and causes ex-

!

,

,

!

3 2 1 0
FUNCTION

NAME

1-0

REQUESTED
PRIVILEGE
LEVEL
(RPL)

INDICATES SELECTOR PRIVILEGE
LEVEL DESIRED

2

TABLE
INDICATOR
(TI)

TI =

15-3

INDEX

SELECT DESCRIPTOR ENTRY IN TABLE

°

USE GLOBAL DESCRIPTOR TABLE
(GDT)
TI = 1 USE LOCAL DESCRIPTOR TABLE
(LDT)

Figure 15. SeleCtor Fields

r---------PRoGR~~~~;---------,

PROGRAM VISIBLE
SEGMENT SELECTORS

I

ACCess

I

RIGHTS

0

SEGMENT REGISTERS
(LOADED BY PROGRAM)

147

I

f

_
SEGMENT PHYSICAL BASE ADDRESS

SEGMENT SIZE

I

I :

~~ill
15

INDEX
!

15

4039

1615

SEGMENT DESCRIPTOR CACHE REGISTERS

L ______ (~~~~L:~~~~C~ _ _ _ _ _ _ _ _ j

I

Figure 14. Descriptor Cache Registers
4-17

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iAPX 286/10

/ LOCAL AND GLOBAL DESCRIPTOR TABLES
Two tables of descriptors, called descriptor tables, contain all descriptors accessible by a task at any given time.
A descriptor table is a linear array of up to 8192 descriptors. The upper 13 bits of the selector value are an index
into a descriptor table, Each table has a 24-bit base register to locate the descriptor table in physical memory
and a 16-bit limit register that confine descriptor access
to the defined limits of the table as shown in Figure 16. A
restartable exception (13) will occur if an attempt is made
to reference a descriptor outside the table limits.
One table, called the Global Descriptor Table (GOT),
contains descriptors available to all tasks. The other table, called the Local Descriptor Table (LOT), contains
descriptors that can be private to a task. Each task may
have its own private LOT. The GOT may contain all descriptor types except interrupt and trap descriptors. The
LOT may contain only segment, task gate, and call gate
descriptors. A segment cannot be accessed by a ta~k if
its segment descriptor does not exist in either descriptor
table at the time of access.
'V

MEMORY

07

+5

INTEL RESERVED'

1

+4

BASE23_16

BASE15_0

+3

+2

LIMITl5-0

+1
15

8 7

.. Must be set to 0 for compatability with IAPX 386.

Figure 17. Global Descriptor Table and Interrupt
Descriptor Table Data Type
INTERRUPT DESCRIPTOR TABLE
The protected mode 80286 has a third descriptor table,
called the Interrupt Descriptor Table (IDT) (see Figure
18), used to define up to 256 interrupts. It may contain
only task gates, interrupt gates and trap gates. The IDT
(Interrupt Descriptor Table) has a 24-bit physical base
and 16-bit limit register in the CPU. The privileged LlDT
instruction loads these registers with a six byte value of
identical form to that of the LGDT instruction (see Figure
17 and Protected Mode Initialization).

'V

CPU

'r "

,~

l

CURRE~T

~~~

15

LOT

I

0

~

u

MEMORY

'V

GATE FOR
INTERRUPT #n
GATE FOR
INTERRUPT #n·1

···

INTERRUPT
DESCRIPTOR

TABLE
(lOT)

GATE FOR
INTERRUPT #1
GATE FOR
INTERRUPT #0

lOT BASE

23

0

~

'V

Figure 18. Interrupt Descriptor Table Definition

Figure 16. Local and Global Descriptor
Table Definition
The LGDT and LLDT instructions load the base and limit
of the global and local descriptor tables. LGDT and LLDT
are privileged, i.e. they may only be executed by trusted
programs operating at level O. The LGDT instruction loads
a six byte field containing the 16-bit table limit and 24-bit
physical base address of the Global Descriptor Table as
shown in Figure 17. The LDT instruction loads a selector
which refers to a Local Descriptor Table descriptor containing the base address and limit for an LDT, as shown
in Figure 12.

References to lOT entries are made via INT instructions, external interrupt vectors, or exceptions. The lOT
must be at least 256 bytes in size to allocate space for
all reserved interrupts.

Privilege
The 80286 has a four-level hierarchical privilege system
which controls the use of privileged instructions and access to descriptors (and their associated segments) within
a task. Four-level privilege, as shown in Figure 19, is an
extension of the user/supervisor mode commonly found
in minicomputers. The privilege levels are numbered 0
through 3. Level 0 is the most privileged level. Privilege

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iAPX 286/10

CPU
ENFORCED
SOFTWARE
INTERFACES

lege Level (DPL) field of the descriptor access byte. DPL
specifies the least trusted task privilege level (CPL) at
which a task may access the descriptor. Descriptors with
DPt = 0 are the most protected. Only tasks executing
at privilege level 0 (CPL = 0) may access them. Descriptors with DPL = 3 are the least protected (I.e. have
the least restricted access) since tasks can access them
when CPL = 0,1,2, or 3. This rule applies to all descriptors, except LDT descriptors.

HIGH SPEED

OPERATING
SYSTEM
INTERFACE

NOTE: PL BECOMES NUMERICALLY LOWER AS PRIVILEGE LEVEL
INCREASES

Figure 19. Hierarchical Privilege Levels
levels provide protection within a task. (Tasks are isolated
by providing private LDT's for each task.) Operating
system routines, interrupt handlers, and other system software can be included and protected within the virtual
address space of each task using the four levels of privilege. Each task in the system has a separate stack for
each of its privilege levels.
Tasks, descriptors, and selectors have a privilege level
attribute that determines whether the descriptor may be
used. Task privilege effects the use of instructions and
descriptors. Descriptor and selector privilege only effect
access to the descriptor.

TASK PRIVILEGE

SELECTOR PRIVILEGE
Selector privilege is specified by the Aequested Privilege Level (APL) field in the least significant two bits of a
selector. Selector APL may establish a less trusted privilege level than the current privilege level for the use of a
selector. This level is called the task's effective privilege
level (EPL). APL can only reduce the scope of a task's
access to data with this selector. A task's effective privilege is the numeric maximum of APL and CPL. A selector with APL = 0 imposes no additional restriction on its
use while a selE.lotor with APL = 3 can only refer to segments at privilege Level 3 regardless of the task's CPL.
APL is generally used to verify that pointer parameters
passed to a more trusted procedure are not allowed to
use data at a more privileged level than the caller (refer
to pointer testing instructions).

Descriptor Access and Privilege Validation
Determining the ability of a task to access a segment
involves the type of segment to be accessed, the instruction used, the type of descriptor used and CPL,
APL, and DPL. The two basic types of segment accesses are control transfer (selectors loaded into CS)
and data (selectors loaded into DS, ES or SS).

A task always executes at one of the four privilege
levels. The task privilege level at any specific instant
is called the Current Privilege Level (CPL) and is
defined by the lower two bits of the CS register. CPL
cannot change during execution in a single code segment. A task's CPL may only be changed by control
transfers through gate descriptors to a new code
segment (See Control Transfer). Tasks begin executing
at the CPL value specified by the code segment selector within TSS when the task is initiated via a task
switch operation (See Figure 20). A task executing at
Level 0 can access all data segments defined in the
GDT and the task's LDT and is considered the most
trusted level. A task executing a Level 3 has the most
restricted access to data and is considered the least
trusted level.

DESCRIPTOR PRIVILEGE
Descriptor privilege is specified by the Descriptor Privi-

DATA SEGMENT ACCESS
Instructions that load selectors into DS and ES must
refer to a data segment descriptor or readable code segment descriptor. The CPL of the task and the APL of the
selector must be the same as or more privileged (numerically equal to or lower than) than the descriptor DPL.
In general, a task can only access data segments at the
same or less privileged levels than the CPL or APL
. (whichever is numerically higher) to prevent a program
from accessing data it cannot be trusted to use.
An exception to the rule is a readable conforming code
segment. This type of code segment can be read from
any privilege level.
If the privilege checks fail (e.g. DPL is numerically less
than the maximum of CPL and APL) or an incorrect type
of descriptor is referenced (e.g. gate descriptor or execute only code segment) exception 13 occurs. If the segment is not present, exception 11 is generated.

4-19

21025~-007

iAPX 286/10

Instructions that load selectors into SS must referlo data
segment descriptors for writable data segments. The
descriptor privilege (DPL) and RPL must equal CPL. All
other descriptor types or a privilege level violation will
cause exception 13. A not present fault causes exception 12.
CONTROL TRANSFER

Four types of control transfer can occur when a selector
i) loaded into CS by a control transfer operation (see
Table 10). Each transfer type can only occur if the operation which loaded the selector references the correct
descriptor type. Any violation of these descriptor usage
Plies (e.g. JMPthrough a call gate or RETtoa Task State
~ egment) will c~use exception 13.
1 he ability to reference a descriptor for control transfer
if, also subject to rules of privilege. A CALL or JUMP
instruction may only reference a code segment descriptor with DPL equal to the task CPL or a conforming segment with DPL of equal or greater privilege than CPL.
The RPL of the selector used to reference the code descriptor must have as much privilege as CPL.
RET and IRET instructions may only reference code
segment descriptors with descriptor privilege equal to or
less privileged than the task CPL. The selector loaded
into CS is the return address from the stack. After the
return, the selector RPL is the task's new CPL. If CPL
changes, the old stack pointer is popped after the return
address.
When a JMP or CALL references a Task State Segment
descriptor, the descriptor DPL must be the same or less
privileged than the task's CPL. Reference to a valid Task

State Segment descriptor causes a task switch (see Task
Switch Operation). Reference to a Task State Segment
descriptor at a more privileged level than the task's CPL
generates exception 13.
When an instruction or interrupt references a gate descriptor, the gate DPL must have the same or less privilege than the task CPL. If DPL is at a more privileged
level than CPL, exception 13 occurs. lithe destination
selector contained in the gate references a code segment descriptor, the code segment descriptor DPL must
be the same or more privileged than the task CPL. If not,
Exception 13is issued. After the control transfer, the
code segment descriptors DPL is the task's new CPL. If
the destination selector in the gate references a task
state segment, a task switch is automatically performed
(see Task Swit?h Operation).
The privilege rules on control transfer require:
-JMP or CALL direct to a code segment (code segment descriptor) can only be to a conforming segment
with DPL of equal or greater privilege than CPL or a
non-conforming segment at the same privilege level.
-interrupts within the task or calls that may change
privilege levels, can only transfer control through a
gate at the same or a less privileged level than CPL to
a code segment at the same or more privileged level
than CPL.
-return instructions that don't switch tasks can only return control to a code segment at the same or less
privileged level.
-task switch can be performed by a call, jump or interrupt which references either a task gate or task state
segment at the same or less privileged level.

Table 10. Descriptor Types Used for Control Transfer
Control Transfer Types

Operation Types

Descriptor
Referenced

Descriptor
Table

Intersegment within the same privilege level

JMP, CALL, RET, IRET'

Code Segment

GOT/LOT

Intersegment to the same or higher privilege level Interrupt
within task may change CPL.

CALL

Call Gate

GOT/LOT

Interrupt Instruction,
Exception, External
Interrupt

Trap or
Interrupt
Gate

lOT

Intersegment to a lower privilege level (changes task CPL)

Task Switch

,

RET,IRET'

Code Segment

GOT/LOT

CALL,JMP

Task State
Segment

GOT

CALL,JMP

Task Gate

GOT/LOT

IRET"
Interrupt Instruction,
Exception, External
Interrupt

Task Gate

lOT

NT (Nested Task bit of flag word) = 0
"NT (Nested Task bit of flag word) = 1

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iAPX 286/10

PRIVILEGE LEVEL CHANGES

Table 11
Segment Register Load Checks

Any control transfer that changes CPL within the task,
causes a change of stacks as part of the operation. Initial
values of SS:SP for privilege levels 0, 1, and 2 are kept
in the task state segment (refer to Task Switch Operation). During a JMP or CALL control transfer, the new
stack pointer is loaded into the SS and SP registers and
the previous stack pointer is pushed onto the new stack.

Descriptor table limit exceeded

When returning to the original privilege level, its stack is
restored as part of the RET or IRET instruction operation. For subroutine calls that pass parameters on the
stack and cross privilege levels, a fixed number of words,
as specified in the gate, are copied from the previous
stack to the current stack. The inter-segment RET instruction with a stack adjustment value will correctly restore the previous stack pointer upon return.

Error Description

Exception
Number
13

Segment descriptor not-present

I1or12

PriVilege rules violated

13

Invalid descriptor/segment type segment register load:
-Read only data segment load to
SS
-Special control descriptor load to
DS, ES,SS
-Execute only segment load to
DS, ES,SS
-Data pegment load to CS
-Read/Execute code segment
10adtoSS

13

Protection
The 80286 includes mechanisms to protect critical instructions that affect the CPU execution state (e.g. HLT)
and code or data segments from improper usage. These
protection mechanisms are grouped into three forms:

Table 12 Operand Reference Checks
Error Description
Write Into code segment
Read from execute-only code
segment
Write to read-only data segment
Segment limit exceeded'

Restricted usage of segments (e.g. no write allowed
to read-only data segments). The only segments
available for use are defined by descriptors in the Local Descriptor Table (LOT) and Global Descriptor Table(GDT).

Exception
Number
13
13
13
120r13

Note 1: Carry out In offset calculations IS Ignored.

Table 13. Privileged Instruction Checks

Restricted access to segments via the rules of privilege and descriptor usage.
Privileged instructions or operations that may only be
executed at certain privilege levels as determined by
the CPL and I/O Privilege Level (IOPL). The 10PL is
defined by bits 14 and 13 of the flag word.

Error Description

Exception
Number

CPL + 0 when executing the following
instructions:
LlDT, LLDT, LGDT, LTR, LMSW,
CTS,HLT

13

CPL> IOPL when executing the following Instructions:
"
INS, IN, OUTS, OUT, STI, CLI,
LOCK

These checks are performed for all instructions and can
be split into three categories: segment load checks (Table 11), operand reference checks (Table 12). and privileged instruction checks (Table 13). Any violation of the
rules shown will result in an exception. A not-present
exception related to the stack segment causes exception 12.

13

EXCEPTIONS
The 80286 detects several types of exceptions and interrupts, in protected mode (see Table 14). Most are restartable after the exceptional condition is removed. Interrupt
handlers for most exceptions can read an error code,
pushed on the stack after the return address, that identifies the selector involved (O if none). The return address
normally pOints to the failing instruction, including all
leading prefixes. For a processor extension segment overrun exception, the return address will not point at the
ESC instruction that caused the exception; however, the
processor extension registers may contain the address
of the failing instruction.

The IRET and POPF instructions do not perform some of
their defined functions if CPL is not of sufficient privilege
(numerically small enough). Precisely these are:
• The IF bit is not changed if CPL > 10PL.
• The IOPL field of the flag word is not changed if CPL > O.
No exceptions or other indication are given when these
conditions occur.

4-21

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iAPX 286/10

Table 14 Protected Mode Exceptions
Interrupt
Vector

Return
Address

Function

At Failing
Instruction?

8
9
10
11
12
13

Double exception detected
Processor extension segment overrun
Invalid task state segment
Segment not present
Stack segment overrun or stack segment not present
General protection

Yes
No
Yes
Yes
Yes
Yes

Always
Restartable?

N02
N02
Yes
Yes
Yes 1
N02

Error
Code
on Stack?

Yes
No
Yes
Yes
Yes
Yes

NOTE 1: When a PUSHA or POPA instruction attempts to wrap around the stack segment, the machine state after the
exception will not be restartable because stack segment wrap around is not permitted. This condition is identified
by the value of the saved SP being eigher OOOO(H), 0001 (H), FFFE(H), or FFFF(H).
NOTE 2: These exceptions indicate a violation to privilege rules or usage rules has occurred. Restart is generally not
attempted under those conditions.

"
These exceptions indicate a violation to privilege
rules
or usage rules has occurred. Restart is generally not
attempted under those conditions.
All these checks are performed for all instructions and
can be split into three categories: segment load checks
(Table 11), operand reference cheCks (Table 12), and
privileged instruction checks (Table 13). Any violation
of the rules shown will result in an exception. A
not-present exception causes exception 11 0(12 and
is restartable.

Special Operations
TASK SWITCH OPERATION

The 80286 provides a built-in task switch operation which
saves the entire 80286 execution state (registers, address space, and a link to the previous task), loads a
new execution state, and commences execution in the
new task. Like gates, the task switch operation is invoked by executing an inter-segment JMP or CALL instruction which refers to a Task State Segment (TSS) or
task gate descriptor in the GOT or LOT. An INT n instruction, exception, or external interrupt may also invoke the
task switch operation by selecting a task gate descriptor
in the associated lOT descriptor entry.
The TSS descriptor pOints at a segment (see Figure 20)
containing the entire 80286 execution state while a
task gate descriptor contains a TSS selector. The limit
field of the descriptor must be >002B(H).
Each task must have a TSS associated with it. The current TSS is identified by a special register in the 80286
called the Task Register (TR). This register contains a
selector referring to the task state segment descriptor
that defines the current TSS. A hidden base and limit
register associated with TR are loaded whenever TR is
loaded with a new selector.
The IRET instruction is used to return control to the
task that called the current task or was interrupted.
Bit 14 iii the flag egister is called the Nested Task (NT)
bit. It controls the function of the IRET instruction. If
NT = 0, the IRET instruction performs the regular current task return by popping values off the stack; when

NT = 1, IRET performs a task switch operation back
to the previous task.
When a CALL, JMP, or INT instruction initiates a task
switch, the old and new TSS will be marked busy and
the back link field of the new TSS set to the old TSS
selector. The NT bit of the new task is set by CALL or
INT initiated task switches. An interrupt that does not
cause a task switch will clear NT. NT may also be set
or cleared by POPF or IRET instructions.
The task state segment is marked busy by changing
the descriptor type field from Type 1 to Type 3. Use
of a selector that references a busy task state segment
causes Exception 13.
PROCESSOR EXTENSION CONTEXT SWITCHING

The context of a processor extension (such as the 80287
numerics processor) is not changed by the task switch
operation. A processor extension context need only be
changed when a different task attempts to use the processor extension (which still contains the context of a
previous task). The 80286 detects the first use of a processor extension after a task switch by causing the processor extension not present exception (7). The interrupt
handler may then decide whether a context change is
necessary.
Whenever the 80286 switches tasks, it sets the Task
Switched (TS) bit of the MSW. TS indicates that a processdr extension context may belong to a different task
than the current one. The processor extension not present exception (7) will occur when attempting to execute
an ESC or WAIT instruction if TS = 1 and a processor
extension is present (MP = 1 in MSW). .
POINTER TESTING INSTRUCTIONS

The iAPX 286 provides several instruqtions to speed
pOinter testing and consistency checks for maintaining system integrity (see Table 15). These instructions use the memory management hardware to
verify that a selector value refers to an appropriate
segment without risking an exception. A condition
flag (ZF) indicates whether use of the selector or
segment will cause an exception.
4-22

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IAPX 286/10

,

';J

CPU

INTEL RESERVED

pJrI+yp~1

TASK REGISTER
SYSTEM

TRD---

,.
,.
I

•
r---------.,
I

I

:I

LIMIT

BASE

I ___
L
23

•

---•

BASE23-16

AN AVAILABLE TASK STATE
SEGMENT. MAY BE USED AS
THE DESTINATION OF A TASK
SWITCH OPERATION.

3

A BUSY TASK STATE SEGMENT
CANNOT BE USED AS THE
DESnNATION OF A TASK
SWITCH.

UMIT15-0

H

------ -----------:

~

I

--'

0

15

BYTE
OFFSET

TASK LOT SELECTOR

4

DSSELECTOR

40

SSSELECTOR

3

CSSELECTOR

3

ESSELECTOR

3

DI

3

SI

3

P

1

0

\

TASK
STATE
SEGMENT

DESCRIPTION

1

BASE15--G

I
I

PROGRAM INVISIBLE

I
I

~ SEGMENT
DESCRIPTOR

TYPE

BP

28

SP

26

BX

2

DX

2

CX

2

AX

1

FLAG WORD

1

IP (ENTRY POINT)

1

SSFOR CPL 2

1

SP FORCPL2

1

SS FOR CPL 1
SP FOR CPL 1

DESCRIPTION
BASE AND LIMIT FIELDS ARE VALID
SEGMENT IS NOT PRESENT IN
MEMORY. BASE AND LIMIT ARE NOT
DEFINED

CURRENT
TASK
STATE

INITIAL
STACKS
FOR CPL 0.1.2

.

SSFORCPLO
SPFORCPLO
BACK LINK SELECTOR TO TSS

,

Fihure 20. Task State Segment and TSS Registers

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iAPX 286/10

Table 15. 80286 Pointer

rest Instructions

Instruction
ARPl

Operands
Selector,
Register

Function
Adjust Requested Privilege Level: adjusts the RPL
of the selector to the numeric.maximum of current
selector RPl value and the
RPL value in the register.
Set zero flag if sel!!ctor RPL
was changed by ARPL.

VERR

Selector

VERW

Selector

lSL

Register,
Selector

LAR

Register,
Selector

VERify for Read: sets the
zero flag if the segment reo
ferred to by the selector can
be read.
VE Rify for Write: sets the
zero flag if the segment referred to by the selector can
be written.
load Segment Umit: reads
the segment limit into the
register if privilege rules and
descriptor type allow. Set
zero flag if successful.
Load Access Rights: reads
the descriptor access rights
byte into the register if priv·
ilege rules allow. Set zero
flag if successful.

To force the 80286 CPU registers to match the initial
protected mode slate assumed by software, execute
a JMP instruction with a selector referring to the
initial TSS used in the system. This will load the task
register, local descriptor table register, segment
registers and initial general register state. The TR
should point at a valid TSS since any task switch
operation involves saving the current task state.

SYSTEM INTERFACE
The 80286 system interface appears in two forms: a
local bus and a system bus. The local bus consists of
address, data, status, and control signals at the pins of
the CPU. A system bus is any buffered version of the
local bus. A system bus may also differ from the local
bus in terms of coding of status and control lines and/or
timing and loading of signals. The iAPX 286 family includes several devices to generate standard system
buses such as the IEEE 796 standard Multibus T• •

Bus Interface Signals and Timing
The iAPX 286 microsystem local bus interfaces the 80286
to local memory and I/O components. The interface has'
24 addre!is lines, 16 data lines, and 8 status and control
signals.

DOUBLE FAULT AND SHUTDOWN

The 80286 CPU, 82284 clock generator, 82288 bus
controller, 82289 bus arbiter, 8286/7 transceivers,
and 8282/3 latches provide a buffered and decoded
system bus interface. The 82284 generates the
system clock and synchronizes READY and RESET.
The 82288 converts bus operation status encoded
by the 80286 into command and bus control signals.
The 82289 bus arbiter generates Multibus bus
arbitration signals. These components can provide
the timing and electrical power drive levels required
for most system bus interfaces including the Multibus.

If two separate exceptions are detected during a single
instruction execution, the 80286 performs the double
fault exception (8). If an exception occurs during processing of the double fault exception, the 82086 will enter shutdown. During shutdown no further instructions
or exceptions are processed. Either NMI (CPU remains
in protected mode) or RESET (CPU exits protected mode)
can force the 80286 out of shutdown. Shutdown is externally signalled via a HALT bus operation with A1 HIGH.
PROTECTED MODE INITIALIZATION
The 80286 initially executes in real address mode
after RESET. To allow initialization code to be placed
at the top of physical memory, A 23 -20 will be HIGH
when the 80286 performs memory references
relative to the CS register until CS is changed. A 23•20
will' be zero for references to the OS, ES, or SS
segments. Changing CS in real address mode will
force A23•20 LOW whenever CS is used again. The
initial CS:IP value of FOOO:FFFO provides 64K bytes
of code space for initialization code without changingCS.

Physical Memory and 1/0 Interface
. A maximum of 16 megabytes of physical memory can
be addressed in protected mode. One megabyte can be
addressed in real address mode. Memory is accessible
as bytes or words. Words consist of any two consecutive
bytes addressed with the least significant byte stored in
the lowest address.
Byte transfers occur on either half ofthe 16·bit local data
bus. Even bytes are accessed over 07-0 while odd bytes
are transferred over 0 15- 8 , Even·addressed words are
transferred over 0 15-0 in one bus cycle, while odd·ad·
dressed words require two bus operations. The first
.transfers data on 0 15-8, and the second transfers data
on 07-0. Both byte data transfers occur automatically,
transparent to software.

Protected mode operation requires several registers to be initialized. The GOT and lOT base registers must refer to a valid GOT and lOT. After
executing the LMSW instruction to set PE, the 80286
must immediately execute an intra-segment JMP
instruction to clear the instruction queue of instructions decoded in real address mode.

Two bus signals, Ao and SHE, control transfers over the
lower and upper halves of the data bus. Even address

4-24

210253-007

iAPX 286/10

byte transfers are indicated by Ao lOW and BRE HIGH.
Odd address byte transfers are indicated by Ao HIGH
and BRE lOW. Bot" Ao and BRE are lOW for even address word transfers.

RESET

The I/O address space contains 64K addresses in both
modes. The 110 space is accessible as either bytes or
words, as is memory. Byte wide peripheral devices may
be attached to either the upper or lower byte of the data
bus. Byte-wide I/O devices attached to the upper data
byte '(015-8) are accessed with odd I/O addresses. Devices on the lower data byte are accessed with even I/O
addresses. An interrupt controller such as Intel's 8259A
must be connected to the lower data byte (07-0) for proper
return of the interrupt vector.
Figure 22. 80286 Bus States

Bus States

Bus Operation
The 80286 uses a double frequency system clock (ClK
input) to control bus timing. All signals on the local bus
are measured relative to the system ClK input. The CPU
divides the system clock by 2 to produce the internal
processor clock, which determines bus state. Each processor clock is composed of two system clock cycles
named phase 1 and phase 2. The 82284 clock generator
output (PClK) identifies the next phase of the processor
clock. (See Figure 21.)

The idle (T i) state indicates that no data transfers are
in progress or requested. The first active state Ts is
signaled by status line S1 or SO going lOW and identifying phase 1 of the processor clock. During Ts, the
command encoding, the address, and data (for a write
operation) are available on the 80286 output pins. The
82288 bus controler decodes the status signals and
generates Multibus compatible read/write command
and local transceiver control signals.
.
After Ts' the perform command (Tcl state is entered.
Memory or I/O devices respond to the bus operation
during Tc, either transferring read data to the CPU or
accepting write data. Tc states may be repeated as
often as necessary to assure sufficient time for the
memory or I/O device to respond. The REAOY signal
determines whether Tc is repeated. A repeated Tc
state is called a wait state.

ONE PROCESSOR CLOCK CYCLE

ClK
_
PClKY

ONE SYSTEM----.J
ClKCYClE -------"l

v

During hold (T h), the 80286 will float all address, data,
and status output pins enabling another bus master
to use the local bus. The 80286 HOLD input signal
is used to place the 80286 into the Th state. The
80286 HlDA output signal indicates that the CPU has
entered Th.

\ ' - -_ _...J

Figure 21. System and Processor
Clock Relationships

Six types of bus operations-are supported; memory read,
memory write, I/O read, I/O write, interrupt acknowledge, and halt/shutdown. Data can be transferred at a
maximum rate of one word per two processor clock cycles.
The iAPX 286 bus has three basic states: idle (Til. send
status (Ts), and perform command (Td. The 80286 CPU
also has a fourth local bus state called hold (Th). Thindicates that the 80286 has surrendered control of the
local bus to another bus master in response to a HOLD
request.
'

Pipelined Addressing
The 80286 uses a local bus interface with pipelined
timing to allow as much time as possible for data
access. Pipelined timing allows a new bus operation
to be initiated every two processor cycles, while allowing each individual bus operation to last for three
processor cycles.
The timing of the address outputs is pipelined such that
the address of the next bus operation becomes available
during the current bus operation. Or in other words, the
first clock of the next bus operation is overlapped with
the'last clock of the current bus operation. Therefore,
address decode and routing logic can operate in ad-

Each bus state is one processor clock long. Figure 22
shows the four 80286 local bus states and allowed
transitions.
4-25

210253-007

iAPX 286/10

F

TI

.,

0 15 - "" - - - - - -

-- -

;

- - -- -

-I"

READ BUS CYCLE N

Ts~'I
Q
I

-

-

-

-

-

-

READ BUS CYCLE N

+1~.

--Tc~~Ts-----------'l _ _ _ _ c
~
I.
~
I
Q
~
I

-

-

-

-

-

--c:::::>- ------------ -----cJVALID READ
DATA (N)

PlPELlNING: VALID ADDRESS (N

Q

VALID REAO
DATA (N + 1)

+ 1) AVAILABLE IN LAST PHASE OF BUS CYCLE (N).

Figure 23. Basic Bus Cycle

Command Timing Controls

vance of the next bus operation. External address latches
may hold the address stable for the entire bus operation,
and provide additional AC and DC buffering.

Two system timing customization options, command extension and command delay, are provided on the iAPX
286 local bus.

The 80286 does not maintain the address of the current
bus operation during all T c states. Instead, the address
for the next bus operation may be emitted during phase
2 of any T c. The address remains valid during phase 1
of the first Tc to guarantee hold time, relative to ALE, for
the address latch inputs.

Command extension allows additional time for external
devices to respond to a command and is analogous to
inserting wait states on the 8086. External logic can control the duration of any bus operation such that the operation is only as long as necessary. The READ? input
signal can extend any bus operation for as long as
necessary.

Bus Control Signals
The 82288 bus controller provides control signals; address latch enable (ALE). ReadlWrite commands, data
transmit/receive (DT/R) , and data enable (DEN) that
control the address latches, data transceivers, write enable, and output enable for memory and 110 systems.

Command delay allows an increase of address or write
data setup time to system bus command active for any
bus operation by delaying when the system bus command becomes active. Command delay is controlled by
the 82288 CMDLY input. After Ts , the bus controller
samples CMDLY at each failing edge of CLK. If CMDLY
is HIGH, the 82288 will not activate the command signal.
When CMDLY is LOW, the 82288 will activatathe command signal. After the command becomes active, the
CMDLY input is not sampled.

The Address Latch Enable (ALE) output determines when
the address may be latched. ALE provides at least one
system CLK period of address hold time from the end of
the previous bus operation until the address for the ne~t
bus operation appears at the latch outputs. This address
hold time is required to support Multibus® and common
memory systems.

When a command is delayed, the available response
time from command active to return read data or accept
write data is less. To customize system bus timing, an
address decoder can determine which bus operations
require delaying the command. The CMDLY input does
not affect the timing of ALE, DEN, or DT/R.

The data bus transceivers are controlled by 82288 outputs Data Enable (DEN) and Data Transmit/Receive (DT/
R). DEN enables the data transceivers; while DT/R controls transceiver direction. DEN and DT/R are timed to
prevent bus contention between the bus master, data
bus transceivers, and system data bus tranceivers.

4-26

210253-007

iAPX 286/10

1 - - - - - - - - READ BUS CYCLE N - 1 - - - - - - - - - I - ! - - - - - READ BUS CYCLE N - - - - . I
elK

PRoe - - - . . ,
elK

S:1 • SO

ALE _ _ _.J

A~ADV

EX'

~

AD COMMAND

CMDLY _ _ _- - '

EX 2

~

RD COMMAND

CMDlY

Figure 24. CMDlY Controls the leading Edge of Command Signal.
Figure 24 illustrates four uses of CMDlY. Example 1
shows delaying the read command two system ClKs for
cycle N-1 and no delay for cycle N, and example 2 shows
delaying the read command one system ClK for cycle
N-1 and one system ClKdelayfo~ cycle N.

current bus operation. The bus master and bus controller must see the same sense of the READY signal,
thereby requiring REA[)? be synchronous to the
system clock.

Synchronous Ready
The 82284 clock generator provides READY synchronization from both synchronous and asynchronous
sources (see Figure 25). The synchronous ready input
(SRlJ'Y) of the clock generator is sampled with the falling
edge of ClK at the end of phase 1 of each Tc' The state
of SRlJ'Y is then broadcast to the bus master and bus
controller via the READY output line.

Bus Cycle lermination
At maximum transfer rates, the iAPX 286 bus alternates
between the status and command states. The bus status
signals become inactive after Ts so that they may correctly signal the start of the next bus operation after the
completion of the current cycle. No external indication of
Tc exists on the iAPX 286 local bus. The bus master and
bus controller enter T c directly after Ts and continue executing T c cycles l:mtil terminated by REAJ:5'i'.

READY Operation
The current bus master and 82288 bus controller terminate each bus operation simultaneously to achieve
maximum bus operation bandwidth. Both are informed
in advance by READY active (open-collector output
from 82284) which identifies the last Tc cycle of the

Asynchronous Ready
Many systems have devices or subsystems that are
asynchronous to the system clock. As a result, their
ready outputs cannot be guaranteed to meet the 82284
~ setup and hold time requirements. But the
82284 asynchronous ready input (AR'Ijy) is designed
to accept such signals. The i\fIDY input is sampled at
the beginning of each Tc cycle by 82284 synchronization logic. This provides one system ClK cycle time to
resolve its value before broadcasting it to the bus
master and bus controller.

4-27

210253-007

iAPX 286/10

•

'

.1.

MEMORY CYCLE N - 1

·1

MEMORY CYCLE N

--Ts--------.l~Tc-------. 4-------1S-------'I"""-- TC-------'I-4------ Tc-------'
I

d>2

I

dot

I

d>2

dJ1

I

2

<.1>1

I

4>2

elK

PROCCLK

A23 -

Ao

---------------7~

FIEAllY

(SEE NOTE 1.)

(SEE NOTE 2.)

-~~
(SEE NOTE 3.)

NOTES:
1. SRDYEN IS active low
2. If SRDYEN IS high, the state of SRDY will not effect READY
3. ARDYEN is active low

Figure 25. Synchronous and Asynchronous Ready

ARDY or ARDYEN must be HIGH at the end of Ts.
used to terminate bus cycle with
no wait states.

The data bus is driven with write data during the second
phase of Ts. The delay in write data timing allows the
read data drivers, from a previous read cycle, sufficient
time to enter 3-state OFF before the 80286 CPU begins
driving the local data bus for write operations. Write data
will always remain valid for one system clock past the
last Tc to provide sufficient hold time for Multibus or other
similar memory or 1/0 systems. During write-read or writeidle sequences the data bus enters 3-state OFF during
the second phase of the processor cycle after the last
Tc. In a write-write sequence the data bus does not enter
3-state OFF between Tc and Ts.

ARDv cannot be

Each ready input of the 82284 has an enable pin

(SRDYEN and ARDYEN) to select whether the current
bus operation will be terminated by the synchronous or
asynchronous ready. Either of the ready inputs may terminate a bus operation. These enable inputs are active
low and have the same timing as their respective ready
inputs. Address decode logic usually selects whether
the current bus operation should be terminated by ARDY
orS"RDY.

Bus Usage
Data Bus Control

The 80286 local bus may be used for several functions:
instruction data transfers, data transfers by other bus
masters, instnJction fetching, processor extension data
transfers, interrupt acknowledge, and halt/shutdown. This
section describes local bus activities which have special
signals or requirements.

Figures 26, 27, and 28 show how the DT/R, DEN, data
bus, and address signals operate for different combinations of read, write, and idle bus operations. DT/R goes
active (LOW) for a read operaton. DT/R remains HIGH
before, during, and between write operations.

4-28

210253-007

IAPX 286/10

1-

READ BUS CYCLE

-I'

--TI~4-----Ts---'-4--Tc~

1,1>2

WRITE BUS CYCLE

~......---T,

4-----Ts--"""-Tc

J>'10I41".11<1>2

,MI.J4Id>11.J4

'b11~

ClK

AZ3 - Ao

SO. S1

MRDC

MWTC

DEN

--------+----J't

DTR

Figure 26. Back to Back Read-Write Cycles

READ CYCLE

WRITE CYCLE

eLK

D1S-Do - - - - - - - - - -

VAUD WRITE DATA

DEN

DTIR

Figure 27. Back to Back Write-Read Cycles

4-29

210253-007

iAPX 286/10

WH ________________

~

___________________________________________

DTfR

Figure 28. Back to Back Write-Write Cycles

HOLD and HLDA

A prefetch bus operation starts when at least two bytes
of the 6-byte prefetch queue are empty.

HOLD and HLDA allow another bus master to gain control of the local bus by placing the 80286 bus into the T h
state. The sequence of events required to pass control
between the 80286 and another local bus master are
shown in Figure 29.

The prefetcher normally performs word prefetches independent of the byte alignment of the code segment
base in physical memory.
The prefetcher will perform only a byte code fetch operation for control transfers to an instruction beginning
on a numerically odd physical address.

In this example, the 80286 is initially in the T h state as
signaled by HLDA being active. Upon leaving T h, as signaled by HLDA going inactive, a write operation is started.
During the write operation another local bus master requests the local bus from the 80286 as shown by the
HOLD signal. After completing the write operation, the
80286 performs one Tj bus cycle, to guarantee write data
hold time, then enters Th as signaled by HLDA going
active.

Prefetching stops whenever a control transfer or HLT
instruction is decoded by the IU and placed into the
instruction queue.
In real address mode, the prefetcher may fetch up
to 6 bytes beyond the last control transfer or HLT
instruction in a code segment.
In protected mode, the prefetcher will never cause a
segment overrun exception. The prefetcher stops at
the last physical memory word of the code segment.
Exception 13 will occur if the program attempts to execute beyond the last full instruction in the code
segment.

The CMDLY signal and.ARO"? ready are used to start
and stop the write bus command, respectively. Note that
S'RD'i" must be inactive or disabled by SRDYEN to guarantee ARO"? will terminate the cycle.

Instruction Fetching

If the last byte of a code segment appears on an even
physical memory address, the prefetcher will read the
next physical byte of memory (perform a word code
fetch). The value of this byte is ignored and any attempt to execute it causes exception 13.

The 80286 Bus Unit (BU) will fetch instructions ahead of
the current instruction being executed. This activity is
. called prefetching. It occurs when the local bus would
otherwise be idle and obeys the following rules:

4-30

210253-007

iAPX 286/10

BUS CYCLE TYPE

I.
.1

BUS HOLD ACKNOWLEDGE

TH

1.2

I

TH

.1

1.2

I

TH

.'

.'I

1.2

BUS HOLD
ACKNOWLED~E

I

WRITE CYCLE

Ts

.1 I 2

I r/!1

T,

I ,p2

¢1

~H 4>2 I

CLK

HOLD

HLDA

r-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _

. }2....

lS:.E~~~

(SEE NOTE 2)

Au - Ao
MIlO, - - - - - - - - - - - - - - - COD/INTA

~~~~~t»»--------(SEE NOTE 3)

BHE, LOCK

------------------·~==t~~==J~7]~ffi7]~~~tZ~tB~---------

D" - DO

------------------------:(I.._______VA_L_'D_ _ _ _ _ _--'-"»t---------

!:E~~'<@&I~~,,&JW'#$Jd
NOT READY

NOT READY

MWTC

VOH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

DTiIi

,'-----

DEN

ALE _______________________~~~________________________________

TS - STATUS CYCLE

Te -- COMMAND CYCLE

NOTES:

1 Status hnes are not dnven by 80286, yet remain high due to pullup resistors In 82288 and 82289 dunng HOLD state
2 Address, M/iO and COD/INTA may start floating dunng any TC depending on when Internal 80286 bus arbiter deCides to release bus to
external HOLD The float starts In·4>2 of TC
3 SHE and LOCK may start floating after the end of any TC depending on when Internal 80286 bus arbiter deCides to release bus to external
HOLD The float starts In 4>1 of TC
4 The minimum HOLD
5 The earliest HOLD

to HLDA

time IS shown MaXimum IS one TH longer

time IS shown It Will always allow a subsequent memory cycle If pending IS shown

6 The minimum HOLD to HLDA
Interrupts, Walts, Lock, etc)

time IS shown MaXimum IS a function of the Instruction, type of bus cycle and other machine status (I e ,

7 Asynchronous ready allows termination of the cycle. Synchronous ready does not Signal ready In thiS example Synchronous ready state
IS Ignored after ready IS Signaled via the asynChronous Input

Figure 29. Multibus Write Terminated by Asynchronous Ready with Bus Hold

4 -31

210253-007

iAPX 286/10

Processor Extension Transfers

Local Bus Usage Priorities

The processor extension interface uses 1/0 port
addresses 00F8(H), OOFA(H), and OOFC(H) which are
part of the 1/0 port address range reserved by Intel.
An ESC instruction with Machine Status Word bits
EM = 0 and TS = 0 will perform 1/0 bus operations to
one or more of these 1/0 port addresses independent
of the value of 10PL and CPL.

The 80286 local bus is shared among several internal
units and external HOLD requests. In case of simultaneous requests, their relative priorities are:

(Highest)

ESC instructions with memory references enable the .
CPU to accept PEREa inputs for processor extension
operand transfers. The CPU will determine the operand
starting address and read/write status of the instruction.
For each operand transfer, two or three bus operations
are performed, one word transfer with I/O port address
OOFA(H) and one or two bus operations with memory.
Three hus operations are required for each word operand aligned on an odd byte address.

Any transfers which assert ITJCK either explicitly (via the LOCK instruction prefix) or
implicitly (Le. segment descriptor access,
interrupt acknowledge sequence, or an
XCHG with memory).
The second of the two byte bus operations
required for an odd aligned word operand.
The second or third cycle of a processor
extension data transfer.
Local bus request via HOLD input.

Interrupt Acknowledge Sequence

Processor extension data operand transfer
via PEREa input.

Figure 30 illustrates an interrupt acknowledge sequence
performed by the 80286 in response to an INTR input.
An interrupt acknowledge sequence consists of two
INTA bus operations. The first allows a master 8259A
Programmable Interrupt Controller (PIC) to determine
which if any of its slaves should return the interrupt
vector. An eight bit vector is read on 00-07 of the
80286 during the second INTA bus operation to select
an interrupt handler routine from the interrupt table.

Data transfer performed by EU as part of an
instruction.
(Lowest)

The Master Cascade Enable (MCE) Signal of the 82288
is used to enable the cascade address drivers, during
INTA bus operations (See Figure 30), onto the local address bus for distribution to slave interrupt controllers via
the system address bus. The 80286 emits the ITJCK
~ignal (active LOW) during Ts of the first INTA bus operation. A local bus "hold" request will not be honored until
the end of the second INTA bus operation.

An instruction prefetch request from BU. The
EU will inhibit prefetching two processor
.clocks in advance of any data transfers to
minimize waiting by EU for a prefetch to finish.

Halt or Shutdown Cycles
The 80286 externally indicates halt or shutdown conditions as a bus operation. These conditions occur due to
a HLT instruction or multiple protection exceptions while
attempting to execute one instruction. A halt or shutdown bus operation is signalled when Sl, "SO and COD/
ll'iITA are Low and MOO is HIGH. A1 HIGH indicates
halt, and A1 LOW indicates shutdown. The 82288 bus
controller does not issue ALE, nor is READ'? required to
terminate a halt or shutdown bus operation.

Three idle processor clocks are provided by the 80286
between INTA bus operations to allow for the minimum
INTA to INTA time and CAS (cascade address) out delay
of the 8259A. The second INTA bus operation must always have at least one extra Testate added via logic
controlling READ'? A23-AO are in'3-state OFF until after
the first Tc state of the second INTA bus operation. This
prevents bus contention between the cascade address
drivers and CPU address drivers. The extra Testate allows time for the 80286 to resume driving th"e address
lines for subsequent bus operations.

During halt or shutdown, the 80286 may service PEREa
or HOLD requests. A processor extension segment
overrun exception during shutdown will inhibit further
service of PEREa. Either NMI or RESET will force the
80286 out of either halt or shutdown. An INTR, if interrupts are enabled, or a processor extension segment
overrun exception will also force the 80286 out of halt.

4-32

210253-007

iAPX 286/10

BUS CYCLE TYPE

I

TC
<1>1

1.1>2

I

"""---INTA CYCLE 1 ~I
.bl

~
I c/fl.

CLK

MlI~,

! ,)"

~
I 1/>2

I 1/1'

~
1,1,2

4>1

~
I c/fl.

I <1>1

~
~
I clfJ.l '

CYCLE

~.
~
I 11 1

~
I c/fl.

,I,'

~
I.ill

I

COOIINTl

liliE

015 -

Do

»»»»)}----------- -<. . .__

DO_N'_TC_AR_E

':"WeV~~'i:~E

_---J}- - -- - - - - - - -

>------- 0- -- --- --- -- --- - - -----

-c=

(SEE NOTE 1)

{VECTOR}- - ON 07·00

(SEE NOTE 2 )
IIEADV

S\\\\\\ 1l111/01/R/I \\\\\\ IIOVllIIOVIIllOlll107IIII1OO/l \\\\\\
NOT READY

NOT READY

READY

MCE

f\

f\

ALE

n

n

DTf"

DEN

\

/

/

I

\
/

\

mmz

REAOY

~

\

/

\

lIlT.{

I

(SEE NOTE 3.)

'---

NOTES:
1. Data is ignored.
2. First INTA cycle should have at least one walt state Inserted to meet 8259A minimum INTA pulse width.
3 Second INTA cycle must have at least one wait state inserted since the CPU Will not drive A23 - Ao, BHE, and [QCj( until after the first
TCstate.
The CPU Imposed one/clock delay prevents bus cQntention between cascade address buffer being disabled by MCE +and address
outputs.
Without the wait state, the 80286 address will not be valid for a memory cycle started Immediately after the second INTA cycle. The
8259A also requires one wait state for minimum INTA pulse Width,
4. [QCj( is active for the first INTA cycle to prevent the 82289 from releasing the bus between INTA cycles in a multi·master system.
5.

Azl - Ao exits 3·state OFF during --l

r*'

ri--H-+-f-l

r--I===:

GRQlCK

BREa
BPRQ

$0

BPRN ~

51

BUSY

READY

caRD

elK

LOCK

AEN

M 10

82289 SLOCK

MUlTiBUS
BUS ARBITRATION

f.---f.----

1f---

r-- -

BUS ARBITER

'-+~H-+-f.j

R=
"

I

_

_

JDREAD
10 WRITE

x,

AES

READY
elK

ENABLE - -

CM:JLY

I

I

~~~~~

I

I

I

I

GENERATOR

II

II

_

RESET

~

~
~

I(

_______ J

II
-

J....,..

READY
S1

An

!

"

ERROR

I

1

I

"

BUSY
PEACK

II

"I

I 1.
r - - - -- -!...,.
1111II
JI'
I

I

I 1

I II

r -

I

I

I"

I I I I I I : 1 I

I

r

-! I

:I

I

~~~~~~g:
(OPTIONAL)

CAPI:;:h
I

0"

IT

1- •

Do

__

I -

L

I

...J

CHIP SELECT

----I

WA

....l\-

SP EN

,...;1---

Do

v--- IRo

' - -_ _ _

--v'

AD

~;59A

>R,

INTERRUPT
CONTROLLER

~

k'l- - :

'.-

cs _

1----+-+-++-f------1 '"'
I
INTA

r------

L _ _ _ _ _ _ _ _ -.J

ADDRESS BUS

8283

/'--CAS 01

I

CPU

r' _ _ _

80287

~-

I~~

B0286

lllilllllr..J
1l l lI_I
__ I_'_'_t_,-+~

I

Ao ~t-=~=:=~=:=:;:~~~
'

INTR

PEREa

I

_J

l.....-

I
BHEr.I-+H-+t-=I

I-;-HOLD

!

-,

t=;=)

STB
DE

__

coo INTA ---,

I

_1_ -

r-

~
_

i--l-I-I-,-HLDA
1

- _ - -11

r=:=--

LOCK -

elK

r-------11

Jf

f

M 10

'I~SO
I I I~NMI

I

-

R -

M 10

RESET r-t,'H-+-IH---'l ~
I I
---.L

ARDVEN

'I

DEN -

CONTROLLER

I

Vee

20K!!

READY

AROY

INTERRUPT ACKNOWLEDGE

;~: ~=tt===tl=t==~-+~

H-~-+-H.j CL~2288 BU~T
I

ENABLE - - SROYEN

MEMORY WRITE

INTA

:~ f4t----1H-+-f·1 :~

SYNC READY - - SROV
ASYNC READY - -

MEMORV READ

lowe

F C

-::!:-

f-H------H---

IORC

I

EFI

--=.....

MRDe
MWTC

PCLK

_

MB

,D t

X2

-:=-1!o::~4-~

AEN

.....--lnh

I

_

~

-r - - .-

OE

' - - - - - - - r - - - - - - y / I T~!~S

~
~

OATA BUS

CEIVER
T

Figure 32. Multibus System Bus Interface
degradation caused by address propogation and decode delays. In addition to selecting memory and 110,
the advanced selects may be used with configurations
supporting local and system buses to enable-the appropriate bus interface for each bus cycle. The COD/Tf\JTA
and MIlO signals are applied to the decode logic to distinguish between interrupt, 110, code and data bus cycles.
By adding the 82289 bus arbiter chip the 80286 provides
a Multibus system bus interface as shown in Figure 32.
The ALE output of the 82288 for the Multibus bus is

connected to its CMDlY input to delay the start of commands one system ClK as required to meet Multibus
address and write data setup times. This arrangement
will add at least one extra Testate to each bus operation
which uses the Multibus.
A second 82288 bus controller and additional latches
and transceivers could be added to the local bus of Figure 32. This configuration allows the 80286 to support
an on-board bus for local memory and peripherals, and
the Multibus for system bus interfacing.

4-35

210253-007

IAPX 286/10

8286

OATAD 15

-

8287

Do

DATA

DRAM
2118,2164

80286
CPU

MULTIBUS SELECT

elK

XACK

STATUS SO.

ii. M/iO

MULTIBUS
COMMAND

(MADe,

iiWfc)

DECODE
lOCAL
SELECT

' - - - - - 1 t-"-----;S;;;:;El"'EC=T

' - - - - - ADDRESS
ADDRESS AZ3 -

Ao. SHE, LOCK

Figure 33. IAPX 286 System Configuration with Dual-Ported Memory
Figure 33 shows the addition of dual ported dynamic
memory between the Multibus system bus and the iAPX
286 local bus. The dual port interface is provided by the
8207 Dual Port DRAM Controller. The 8207 runs synchronously with the CPU to maximize throughput for local memory references. It also arbitrates between
requests from the local and system buses and performs

functions such as refresh, initialization of RAM, and read! \
modify/write cycles. The 8207 combined with the 8206
Error Checking and Correction memory controller provide for single bit error correction. The dual-ported
memory can be combined with a standard Multibus system bus interface to maximize performance and protection in multiprocessor system configurations.

Table 16.80286 Systems Recommended Pull up Resistor Values
80286 Pin and Name
4-81
5-50
6-PEACK
53-ERROR

Purpose

Pullup Value

20KO ± 10%

Pull 50, 'ST, and PEACK inactive during 80286 hold periods

20KO ±.10%

Pull ERROR and BUSY inactive when 80287 not present
(or temporarily removed from socket)

9100 ± 5%

Pull READY inactive within required minimum time (CL
!as 7mA)

54-BUSY
63-READY

4-36

=

150pF,

210253-007

iAPX 286/10

PACKAGE
The 80286 is packaged in a 68-pin, leadless JEDEC
type A hermetic lead less chip carrier. Figure 34 illustrates the package, and Figure 2 shows the pinout.

F
1
----lI

H:
050

.I

(1.68)

.0

.800
('0.3')

(O~~:)l

L_
PIN NO. 18

094

066

PIN NO. 52

iPlNNO.35

(' ~9)

960
('4.38)

~PIN

PINNO.1

NO 1 MARK

130
(3.30)
INCHES

960
(24.38)

(MILLIMETERS)

Figure 34. JEDEC Type A Package

ABSOLUTE MAXIMUM RATINGS·

'NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not Implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AmbientTemperature Under Bias .......... O°C to 70"C
Storage Temperature. . . . . . . . . . . .. - 65°C to + 150°C
Voltage on Any Pin with
Respect to Ground . . . . . . . . . . . . . . .. -1.0 to

+7V

Power Dissipation ...................... 3.3 Watt

D.C. CHARACTERISTICS

(TA =

ooe to 70 oe, Vee = 5V, ±5%)
4MHz

6MHz

8MHz

-4
Min

-4
Max

-6
Min

-6
Max

-8
Min

-8
Max

Unit

Input lOW Voltage

-.5

.8

-.5

.8

-.5

.8

V

VIH

Input HIGH Voltage

2.0

Vee +.5

2.0

Vee +.5

2.0

Vee + .5

V

VILe

ClK Input lOW Voltage

-.5

.6

-.5

.6

-.5

.6

V

3.8

Vee +.5

3.8

Vee + .5

3.8

Vee +.5

V

.45

V

Sym
VIL

Parameter

VI He

ClK Input HIGH Voltage

VOL
VOH

Output lOW Voltage
Output HIGH Voltage

III

Input leakage Current

IlL

Input sustaining Current on
BUSY and ERROR pins

ILO

Output leakage Current

ILO

Output leakage Current

+-1

lee

Supply Current (turn on, O°C)

600

NOTE 1: Low temperature

IS

worst case

.45
2.4

.45
2.4

+-10
30

500

2.4
+-10

30

500

4-37

30

IOL = 2.0mA
IOH

=-400JlA

+-10

JlA

OV-::;VIN-::;V ee

= OV

500

JlA

VIN

+-10

JlA

45V-::;Vour-::;Vee

+-1

+-1

mA

OV-::;V our <.45V

600

600

rnA

Note 1

+-10

+-10

V

Test Condition

210253-007

iAPX 286/10

D.C. CHARACTERISTICS (continued)

(TA = DOC to 7DOC, Vcc = 5V, ±5%)

4 MHz
Sym

Parameter

-4
Min

SMHz

6MHz
-S
Min

-6
Max

-6
Min

-4
Max

-S
Max

Unit

Test Condition

C CLK

ClK Input Capacitance

20

20

20

pF

Fc = 1MHz

C IN

Other Input Capacitance

10

10

10

pF

Fc = 1MHz

Co

Input/Output Capacitance

20

20

20

pF

Fc=1MHz

NOTE 1: Low temperature

IS

worst case

A.C. CHARACTERISTICS

(TA = 0 °G to 55°C, Vcc = 5V, ± 5%)
AC timings are referenced to O.SV and 2.0V points of signals as illustrated in datasheet waveforms,
otherwise noted.
6MHz

4MHz
Parameter

Sym

unles~

SMHz

-4
Min

-4
Max

-6
Min

-6
Max

-S
Min

-S
Max

Unit

124

250

83

250

62

250

ns

Test Condition

1

System Clock (ClK) Period

2

System Clock (ClK) lOW Time

30

210

,20

225

15

225

ns

at 1,OV

3

System Clock (ClK) HIGH Time

40

220

25

230

25

235

ns

at 3,6V

17

System Clock (ClK) Rise Time

10

10

10

ns

1 OV to 3 6V

18

System Clock (ClK) Fall Time

10

10

10

ns

3,6V to 1 OV

4

Asynch Inputs Setup Time

40

30

20

ns

Note 1

5

Asynch, Inputs Hold Time

40

30

20

ns

Note 1

6

RESET Setup Time

40

33

28

ns

7

RESET Hold Time

5

5

5

ns

8

Read Data Setup Time

30

20

10

ns

9

Read Data Hold Time

8

8

8

ns

38

ns

10

READY Setup Time

75

50

11

READY Hold Time

50

35

12

Status/PEACK Valid Delay

1

80

1

55

1

40

ns

Note 2

Note3

13

Address Valid Delay

1

120

1

80

1

60

ns

Note 2

Note 3

14

Wri,te Data Valid Delay

0

100

0

65

0

50

ns

Note 2

Note 3

15

Address/Status/Data Float Delay

0

120

0

80

0

50

ns

Note 2

Note 4

16

HlDA Valid Delay

0

120

0

80

0

50

ns

Note 2

Note 3

ns

25

NOTE 1: Asychronous Inputs are INTR, NMI, HOLD, PEREQ, ERROR, AND BUSY This speCification
assure recognition at a speCific elK edge

IS

given only for testing purposes, to

NOTE 2: Delay from 0 8V on Ihe ClK, to 0 8V or 2 OV or float on the output as appropriate for valid or floating condition
NOTE 3: Ouput load C L

=

100pF

NOTE 4: Float condition occurs when output current

IS

less than ILO

In

magnitude

4-38

210253-007

IAPX 286/10

DEVICE

OUTPUT

I
9:

NOTE

AC Test loading on Outputs

4.0V

ClKINPUT

O.45V

NOTE 6: AC Drive and Measurement POints - ClK Input

4.0V

ClK INPUT
1.0V
O.45V - - - - - - - -

tHOLD

2.4V

OTHER
DEVICE

INPUT

tDELAY ---~

2.0V
DEVICE

OUTPUT
O.BV

NOTE 7.

AC Setup, Hold and Delay Time Measurement - General

4-39

210253-007

"m.;..lt!>

I.

'-e-

iAPX 286/10

A.C. CHARACTERISTICS (Cont.)
82284 Timing Requirements
82284-6

Symbol

Parameter

Min.

11
12
13
14

SRDY/SRDYEN setup time
SRDYISRDYEN hold time
ARDY/ARDYEN setup time
ARDY/ARDYEN hold time

19

PClK delay

82284-8

Max.

25

Min.

Max.

0
5
30
45

0

Max.

Min.
20
0
3

0

Units
ns
ns
ns
ns

15
0
0
16
45

ns

Test Conditions

See note 1
See note 1
CL = 75pF
IOL = 5 ma
IOH=-1ma

NOTE: These times are gIVen for testtng purposes to assure a predetermined acton

82288 Timing Requirements
82288-6

Symbol
12
13
30
29
16
17
19
22
20
21
23
24

Parameter
CMDlY setup time
CMDlT hold time
Command delaylCommand Inactive
From ClK
Command Active
ALE active delay
ALE inactive delay
DTIR read active delay
DTIR read inactive delay
DEN read active delay
DEN read inactive delay
DEN write active delay
DEN write inactive delay

II

Min.
25
0
3
3
3

f5
10
3
3

82288-8

30
40
25
35
40
45
50
40
35
35

3
3

Max.

2Q

3

1.5:

20
40
40
~

30
30

NOTE 1: Asychronous Inputs are INTR, NMI, HOLD, PEREQ, ERROR, AND BUSY This specificatIOn
assure recognitIOn at a specific elK edge

4-40

ns

.2.0
20

0
10
10
3

Units
ns
ns

IS

ns
ns
ns
ns
ns
ns
ns
ns

Test Conditions

CL - 300 pF max
IOL = 32 ma max
IOH = 5 ma max

CL =150pF
IOL = 16 ma max
IOH = -1 ma max

given only for testing purposes, to

210253-007

iAPX 286/10

WAVEFORMS
MAJOR

CYCL~

TIMING
READ

BUS CYCLE TYPE

eLK

S1 •

so

AZ3-AO

7'rTT7"T7CrTT77'l"Ti'm,I,...+---l---+---I. ~;"'I:r-+---+---+----+"'''''''' ,...1---+----

+ __-{'""-LUII'-!-_ _-+___+-__-+f\L.Lf.I.f'-+-_ _-+-':...._ _

M,IO, COOIINTA

CLi.£.I..<..u...2 of a processor cycle.

EXITING AND ENTERING HOLD

BUS CYCLE TYPE

ClK

HLOA

BHE,LOCK
A23 - lAo
M/ID,

----+::::,,1

(SEE NOTE 4.)

(SEE NOTE 5.)
~,-----------

COO/INTA

0 15

-

. '________________
(SEE NOTE _6.)
Do ________

I "-'>..>..~~)-.::....::.:;="'-'~

~[

PClK .

-----'

NOTES:
1 These signals may not be dnven by the 80286 dUring the time shown. The worst case in terms of latest float time
2 The data bus Will be driven as shown If the last cycle before TI in the diagram was a write TC.
3 The 80286 floats Its status pms dUring TH External20Ko reSistors keep these signals high (see Table 16).
4 For HOLD request set up to HLDA. refer to Figure 29.
5 SHE and lOCK are driven at thiS time but Will not become valid until TS
6 The data bus will remain in 3-state OFF If a read cycle IS performed

4-42

IS

shown

210253-007

iAPX 286/10

WAVEFORMS (Continued)
80286 PEREQ/PEACK TIMING FOR ONE TRANSFER ONLY
BUS CYCLE TYPE

ClK

A23 - AO

MilO
CODJINTA

PEACK

PEREQ

ASSUMING WORD·ALlGNED MEMORY OPERAND. IF ODD ALIGNED, 80286 TRANSFERS TO/FROM MEMORY BYTE·AT·A·TIME WITH TWO MEMORY CYCLES.

NOTES:
1. PEACK always goes active during the first bus operation of a processor extension data operand transfer sequence. The first bus operation
Will be either a memory read at operand address or 1/0 read at port address OOFA(H)
2. To prevent a second processor extension data operand transfer, the worst case maximum time (Shown above) IS. 3X G) -@max
-0 m,n . The actual, configuration dependent, maximum time IS' 3X G) -@max-0m,n + A X 2 XG).
A is the number of extra T c states added to either the first or second bus operation of the processor extension data operand transfer
sequence.

INITIAL 80286 PIN STATE DURING RESET
BUS CYCLE TYPE

ClK

RESET

AT lEAST
16 ClK PERIODS

UNKNOWN

UNKNOWN
SHE

MilO
UNKNOWN

COD/INTA

LOCK

UNKNOWN

------5S---------

DATA

IF HOLD IS NOT ACTIVE (SEE NOTE 4).
HLDA

UNKNOWN

NOTES:

1 Setup time for RESET '[ may be violated with the consideration that 01 of the processor clock may begin one system elK period later
2 Setup and hold times for RESET must be met for proper operation, but RESET 1 may occur dUring ,,1 or ",2
3 The data bus IS only guaranteed to be In 3·state OFF at the time shown
4 HOLD IS acknowledged dUring RESET, causing HlDA to go active and the appropriate PinS to float If HOLD remains active while RESET goes
Inactive, the 80286 remains In HOLD state and Will not perform any bus accesses until HOLD IS de-actlVlated

c

4-43

210253-007

iAPX 286/10
I

BYTE 1

BYTE 2

BYTE 3

BYTE 4

r-'"T"T.,...;-nT""':;"r--TTT"'..";""";"'r'-r'-I - - - - ---.,. - - - - - - -"'T
I
I
LOW DISP/DATA
I HIGH DISP/DATA I
'--_.,...;-_......,...........,.............,.........

~---'

-

_ _ _ _ _ _ .... -

______ •

BYTES
-

-

-

BYTES

- - - --y-- - - - - - - . ,

I
I

LOW DATA
___ -

REGISTER OPERAND/REGISTERS TO USE IN OFFSET

-

-

_~

HIGH DATA
__ -

_ _ _ _ ..I

CALCULATIO~

' - - - - REGISTER OPERAND/EXTENSION OF OPCODE
' - - - - - - REGISTER MODE/MEMORY MODE WITH DISPLACEMENT LENGTH
' - - - - - - - WORD/BYTE OPERATION
' - - - - - - - - DIRECTION IS TO REGISTER/DIRECTION IS FROM REGISTER
' - - - - - - - - - - - OPERATION (INSTRUCTION) CODE
A. SHORT OPCODE FORMAT EXAMPLE

BYTE 1

BYTE 2

BYTE 3

BYTE 4

BYTES

B. LONG OPCODE FORMAT EXAMPLE

Figure 35. 80286 Instruction Format Examples

80286 INSTRUCTION SET SUMMARY
Instruction Timing Notes

Instruction Set Summary Notes
Addressing displacements selected by the MOD field
are not shown. If necessary they appear after the instruction fields shown.

The instruction clock counts listed below establish the
maximum execution rate of the 80286. With no delays in
bus cycles, the actual clock count of an 80286 program
will average 5% more than the calculated clock count,
due to instruction sequences which execute faster than
they can be fetched from memory.

Above/below refers to unsigned value
Greater refers to positive signed value
Less refers to less positive (more negative) signed values

=

if d

To calculate elapsed times for instruction sequences,
multiply the sum of all instruction clock counts, as listed
in the table below, by the processor clock period. An 8
MHz processor clock has a clock period of 125 nanoseconds and requires an 80286 system clock (CLK input) of
16 MHz.

1 then to register; if d

= 0 then from register

if w = 1 then word instruction; if w = 0 then byte
instruction
if s = 0 then 16-bit immediate data form the operand
if s = 1 then an immediate data byte is sign-extended
to form the 16-bit operand
x don't care

Instruction Clock Count Assumptions

z used for string primitives for comparison with ZF
FLAG

1. The instruction has been prefetched, decoded, and
is ready for execution. Control transfer instruction clock
counts include all time required to fetch, decode, and
prepare the next instruction for execution.

If two clock counts are given, the smaller refers to a register operand and the larger refers to a memory operand

2. Bus cycles do not require wait states.

•

=

add one clock if offset calculation requires summing 3 elements

3. There are no processor extension data transfer or
local bus HOLD requests.

n = number of times repeated

4. No exceptions occur during instruction execution.

m = number of bytes of code in next instruction
Level (L)-Lexical nesting level of the procedure

4-44

210253-007

iAPX 286/10

not-present exception (11). If the SS register is the
destination, and a segment not-present violation
occurs, a stack exception (12) occurs.

The following comments describe possible exceptions,
side effects, and allowed usage for instructions in both
operating modes of the 80286.

11. All segment descriptor accesses in the GOT or LOT
made by this instruction will automatically assert
IDCK to maintain descriptor integrity in mUltiprocessor systems.

REAL ADDRESS MODE ONLY
1. This is a protected mode instruction. Attempted execution in real address mode will result in an undefined opcode exception (6).
2. A segment overrun exception (13) will occur if a word
operand r~ference at offset FFFF(H) is attempted.

12. JMP, CALL, INT, RET, IRET instructions referring to
another code segment will cause a general protection exception (13) if any privilege rule is violated.

3. This instruction may be executed in real address
mode to initialize the CPU for protected mode.

13. A general protection exception (13) occurs if CPL
oF O.

4. The IOPL and NT fields will remain O.

14. A general protection exception (13) occurs if
CPL> IOPL.

5. Processor extension segment overrun interrupt (9)
will occur if the operand exceeds the segment limit.

15. The IF field of the flag word is not updated if
CPL > IOPL. The IOPL field is updated . only if
CPL = O.

EITHER MODE

16. Any violation of privilege rules as applied to the selector operand do not cause a protection exception;
rather, the instruction does not return a result and
the zero flag is cleared.

6. An exception may occur, depending on the value of
the operand.
7.

IT>CK is automatically asserted regardless of the
presence or absence of the LOCK instruction prefix.

17. If the starting address ·of the memory operand violates a segment limit, or an invalid access is attempted, a general protection exception (13) will
occur before the ESC instruction is executed. A stack
segment overrun exception (12) will occur if the stack
limit is violated by the operand's starting address. If
a segment limit is violated during an attempted data
transfer then a processor extension segment overrun exception (9) occurs.

8. LOCK does not remain active between all operand
transfers.
PROTECTED VIRTUAL ADDRESS MODE ONLY
9. A general protection exception (13) will occur if the
memory operand can not be used due to either a
segment limit or access rights violation. If a stack
segment limit is violated, a stack segment overrun
exception (12) occurs.

18. The destination of an INT, JMP, CALL, RET or
IRET instruction must be in the defined limit of
a code segment or a general protection exception (13) will occur.

10. For segment load operations, the CPL, RPL, and
OPL must agree with privilege rules to avoid an exception. The segment must be present to avoid a

4-45

210253-007

iAPX 286/10

80286 INSTRUCTION SET SUMMARY

""
CLOCK COUNT

COMMENTS

Real
Address
Mode

Protected
Virtual
Address
Mode

Real
Address
Mode

Protected
Virtual
Address
Mode

FUNCTION

FORMAT

DATA TRANSFER
MOY = Move:
Reglsterto ReglsterlMemory

11 000100w

mod reg, rim

2,3'

2,3'

2

9

rim
mod 000 rim

2,5'

2,5'

2

9

Immediate to reglSterlmemory

11 OOOtOlw
11 1000 1 1 w

data

2,3'

2,3'

2

9

Immediate to regIster

11 01 1 W reg

data

datalfw= 1

2

2

Memory to accumulator

11 010000w

addr-Iow

addr-hlgh

5

5

t

9

Accumulator to memory

11 010001w

addr-Iow

addr-hlgh

3

3

2

9

2,5'

17,19'

2

9,10,11

2,3'

2,3'

2

9

5'

5'

2

9

3

3

2

9

ReglSterlmemory to register

mod reg

Reglsterlmemory to segment regISter

11 0001110

mod 0 reg

Segment regISter to reglSterlmemory

11 0001100

mod 0 reg

PUSH = Push:
Memory

11 111111 1

RegISter

,,'

modll0 rim

~Io nOlO's

'"

01

100't (HI 00 ~

PUIIM .. I'Ushldl

11 00 0 1 11 11

RegISter

10 1 0 1 1

Segment regISter

10 00 reg 1 1 11

IiOPA '" P1lj) All; "
XCHG = Exchange:
Reglsterlmemory with regISter

!

<",

I

dala1t,t'"

°I

I

POP = Pop:
Memory

reg

I
I

I
I

,daIa

~ ~,

modOOO rim

I

I

(reg ,,01)

,>

10 l11HlOil 1 I
mod reg

rim

I

datalfw=1

,

10 1 0 1 0 reg
1000 reg 110 1

Segment regISter
~.lmmdl!f'

I
I

rim
rim

I

I

'"

3

3

2

'$;

3

.,2

9

' 9 ','

, 17

a

5'

5'

2

5

5

2

9

5

20

2

9,10,11

19

19

2

j

3,5'

3,5'

2,7

7,9

3

3

5

5

14

5

5

14

,11 '

'" 9,,,

9

RegISter with accumulator

11 000011 wi
11 00 1 0 reg

IN = Input lrom:
Fixed port,

11 110010wl

vanable port

11 1 1 0 1 lOw

OUT = Outputlo:
Fixed port

11 110D11w

3

3

14

vanable port

11 110111w

3

3

14

XLAT = Translate byte to AL

11 1 0 1 0 11 1

5

5

9

LEA = Load EA to "eglSter

11 0,0,01101
11 1 0, 0, 0, 1 0, 1

mod reg

rim

3'

3'

mod reg

r
r

2

9,10,,11

mod reg

rim
rim

21'

11 10,0,0,10,0,
11 0, 0, 11 1 1 1

21'

2

9,10,,11

2

2

LOS = Load pointer to OS
LES = Load pomter to ES
LAHF = Load AH With flags
SAHF = Store AH Into flags

I

I

port

I

I

port

I
I

I

(mod'" 11)
(mod'" 11)

11 0,0,11110,
11 0, 0, 1 1 1 0, 0,

2

2

PUSHF = Push flags

3

3

2

9

POPF = Pop flags

11 0,0,11'101

5

5

2,4

9,15

Shaded areas indicate instructions not aval able in iAPX 86,88 microsystelT)s,

4-46

210253-007

iAPX 286/10

80286 INSTRUCTION SET SUMMARY (Continued)
CLOCK COUNT
FUNCTION

Real
Address
Mode

FORMAT

ARITHMETIC
ADD = Add:
Reglmemory with regISter to either

1000000dwi

mod reg

rim

Immediate to register/memory

1100000swl

modOOO

rim I

Immediate to accumulator

10000010wl

data

I

I

ADC = Add with carry:
Reglmemory with regISter to either

10 0 0 1 0 0 d w I

Immediate to register/memory

1100000swi

Immediate to accumulator

10001010wl

mod reg rim I
modO 1 0 rim I
data
I

INC = Increment:
ReglSterlmemory

11 111111 wi

modOOO rim I

RegISter

10 1 0 0 0

reg

I

data Ilw= 1

I

data

I

data Ilw= 1

I

datallsw=OI

datallsw=OI

I

I

I

SUB = Subtract:
Reglmemory and regISter to either

1001010dwi

mod reg

Immediate lrom reglSterlmemory

1100000swl

mod 101

Immediate from accumulator

10 0 1 o t lOw I

data

SBB = Subtract with borrow:
Reglmemory and regISter to either

10 00110dwl

mod reg

Immediate from register/memory

1100000swl

mod 0 11

rim I
rim I

Immediate from accumulator

IOOO1110wl

data

I

DEC = Decrement:
ReglSterlmemory

11 111111 wi

modOOl

rim I

RegISter

10 1 0 0 1

CMP=Compare'
ReglSterlmemory with regISter

10 0 1 1 1 0 1 wi

mod reg

RegISter with reglSterlmemory

10011100wl

mod reg

rim I
rim I

Immediate with reglSterlmemory

1100000swi

mod 111

rim I

Immediate with accumulator

10 01 1 1 lOw I

data

I

NEG = Change Sign

11 11 1 01 1 wi

mod 0 11

rim I

AM = ASCII adlust lor add

10 0 1 1 0 1 1 11

reg

data

rim I
rim I

data
datalfw=1

I

I

datallsw=OI

I

I

data

I

datallw=1

I

datallsw=OI

I

I

data

I

datall W= 1

I

datallsw=OI I

COMMENTS

Prolecled
Virtual
Address
Mode

Real
Address
Mode

Protected
Virtual
Address
Mode

2,7'

2,7"

2

9

3,7'

3,7"

2

9

3

3

2,7'

2,7"

2

9

3,7'

3,7"

2

9

3

3

2,7"

2,7"

2

9

2

2

2,7'

2,7"

2

9

3,7"

3,7"

2

9

3

3

2,7'

2,7'

2

9

3,7'

3,7'

2

9

3

3

2,7'

2,7'

2

9

2

2

2,6'

2,6'

2

9

2,7"

2,7'

2

9

3,6'

3,6'

2

9

3

3

2

7'

2

7

3

3

DAA= DeCimal adlust lor add

10 0 1 0 0 1 1 11

3

3

AAS = ASCII adjust lorsubtract

10 0 1 1 1 1 1 11

3

3

DAS = D~clmal adlust lor subtract

10 o 1 0 1 1 1 11

3

3

MUL = Multiply (unSigned)
Register-Byte
Register-Word
Memory-Byte
Memory-Word

11 1 1 1 0 1 1 wi

13
21
16'
24'

13
21
16'
24'

2
2

9
9

IMUL = Integer multiply (Signed)
RegISter-Byte
RegISter-Word
Memory-Byte
Memory-Word

11 1 1 1 0 1 1 wi

13
21
16'
24'

13
21
16'
24'

2
2

9
9

21,24'

21,24*

2

9

14
22
17'
25'

14
22
17"
25'

6
6
2,6
2,6

6
6
6,9
6,9

, 1MUl= Integer Immediate multiply
($igftod)

DlV = D,v,de (unSigned)
RegISter-Byte
RegISter-Word
Memory-Byte
Memory-Word

c/o U

0,1 Os

11

11 1 1 1 0 1 1 wi

mod 1 00

mod 1 01

mod!!!l

rim I

rim I

rim

I

data

I

datajls=O

mod 11 0 rim I

J

Shaded areas Indicate instructions not available in IAPX 86, 88 microsystems.

4-47

210253-007

iAPX 286/10

80286 INSTRUCTION SEt SUMMARY (Continued)
CLOCK COUNT
FUNCTION

FORMAT

COMMENTS

Real
Address
Mode

Protected
Virtual
Address
Mode

Real
Address
Mode

Protected
Virtual
Address
Mode

17
25
20'
28'
16

6
6

6
6

2,6
2,S

6,9
6,9

14

ARITHMETIC (Continued):
11 1 1 1 01 1 wi

IDIV ~ Integer divide (Signed)
Register-Byte
Register-Word
Memory-Byte
Memory-Word
AAM ~ ASCII adlust for multiply

11 10101001000010101

17
25
20'
28'
16

AAD ~ ASCII adjust for divide

11 101()'1011000010101

14

caw ~ Convert byte to word

11 00 1 1 00 0
11 00 1 1 00 1

2

CWD ~ Convert word to double word
LOGIC
ShiftlRotate Instructions'
ReglsterlMemory by 1

'1le!llmrlMemory by'COUrrt

rim

I
I

11 1 0 1 000 w

mod

m

rim

I

2,7"

2,7'

11 1 0 1 001 w

mod

m

rim

I

5+',8+,'

5+',8+,'

I
I
11 1 000 D(} wI

ReglsterlMemory by CL

mod 111

TTT Instruction
o0 0
ROL
o 0 1 ROR
o10
RCL
o 1 1 RCR
1 0 0 SHUSAL
101
SHR
111
SAR
AND=And:
Reglmemory and register to either

1001000dwi

mod reg

Immediate to register/memory

11000000wl

mod 1 00 rim

data

Immediate to accumulator

IOO10010wl

data

dat.,fw ~ 1

TEST = And function to flags, no result:
Reglsterlmemory and register
11 0OOO10wl
Immediate data and reglsterlmemory
11 11 1 011 wi

mod reg

rim
dataifw~1

Immediate data and accumulator

11 010100wl

OR=Or:
Reg/memory and register to either

IOOOO10dwi

mod reg

rim

Immediate to reglsterlmemory

11000000wl

modOOl

rim

Immediate to accumulator

10000110wl

data

dat"fw~

data

IOO1100dwi

mod reg

Immediate to register/memory

11000000wl

mod 1 t 0 rim

Immediate to accumulator

10011010wl

data

NOT ~ Invert reglster/memory

11 1 1 1 0 1 1 wi

modOl0 rim

STRING MANIPULATION:
!IIOVS ~ Move bytelword

11 010010wl

CMPS ~ Compare bytelword

11 01 00 1 1 wi

SCAS ~ Scan byte/word

11 01 0 1 1 1 wi

data\fw~1

2,S'
3,S'

2,7'

2,7'

3,7'

3,7'

1

3

rim
data\fw~1

data
data\fw~

2,S'
3,S'
3

1

data
data\fw~

XOR = Exclusive or:
Reglmemory and register to either

dat.,f w~ 1

data

2,7'
3,7"
3

rim

modOOO rim

2,7"
3,7'

2,7'

2,7'

3,7'

3,7'

2,7'

2,7'

1

3

LODS ~ Load bytelwd to AUAX
STOS ~ Stor bytelwd from AUA
.~ It\gut byte/yIIllfumo}( pelf
OUT$"' O\Ifput ~l1imito Ox~'

',

Shaded areas indicate instructions not available in iAPX 86, 88 microsystems.

4-48

210253-007

iAPX 286/10

-

80286 INSTRUCTION SET SUMMARY (Continued)
CLOCK COUNT

COMMENTS

Protected
Virtual
Address
Mode

11 11 1 0 0 1 0 11010010wl

5+4n

5+4n

2

9

5+9n

5+9n

2,8

8,9·

SCAS ~ Scan string

z 11 0 1 00 1 1 wi
11 1 1 1 0 0 1 z 11 0 1 0 1 1 1 wi

LOOS ~ Load string

11 1 1 1 0 0 1 0 11 0 1 0 1 lOw

STOS ~ Store string

11 1 1 1 0 0 1

FORMAT

STRING MANIPULATION (Continued):
Repeated by count In CX
MOVS ~ Move string
CMPS ~ Compare string

11 11 1 0 0 1

::=~:

",'

\

)1

11

Real
Address
Mode

Protected
Virtual
Address
Mode

Real
Address
Mode

FUNCTION

5+8n

5+8n

2,8

8,9

I

5+4n

5+4n

2,8

8,9

o 11010101wl

4+3n

4+3n

2,8

8,9

t'O 0 lD

10,' ,

"',~'t:~ J~::; t ;:.'2\(
;:~:\1i~N:~
. ,: ,'+AtI '<.sWf4n ' ')j:::,:

l,~l11Wl'

'11H1Ul

r;~\~~~(

CONTROL TRANSFER
CALL~Call:

I
I
o0 1 1 0 1 0 I
I

DIrect wlthm segment

11 1 1 0 1 00 0

dlsp-Iow

ReQlster/memory
indirect Within segment
Direct mtersegment

11 111111 1

mod 0 10 rim

11

I
I

dlsp-hlgh

7+m

I
I

segment offset
segment selector

13+m

2il+m

2

18

2,8

8,9,18

2

11,12,18

8,11,12,18
8,11,12,18
8,11,12,18
8,11,12,18
8,11,12,18

41+m

82+m
Bti+4x+m
l77+m
182+m

11 11 11111

I

mod 0 11 rim

I

16+m

(mod" 11)

Protected Mode Only (Indirect intersegment):
Via call gate to same privilege level
Via call gate to different privilege level, no parameters
Via call gate to different privilege level, xparameters
VIaTSS
Via task gate

29+m'

2

11 1 1 0 1 0 1 1

dlsp-Iow

Direct Within segment

11 1 1 0 1 00 1

dlsp-Iow

I
I
Reglsterlmemory ",direct Within segment I1 111111 1 I
Direct ",tersegment
11 1 1 0 1 0 1 o I
I
Protected Mode Only (Direct intersegment):

mod 1 00 rim

I
I
I

dlsp-high

I

segment offset

segment selector

mod 1 01 rim

I

7+m

7+JI1

18

7+m

7+m

18

7+m,ll+m' 7+m,ll+m'

Via call gate to same privilege level
Via TSS
Via task gate
11 1111111

I

.

I
I

11 +m

15+m'

(mod" 11)

8,9,11,12,18
8,9,11,12,18
8,9,11,12,18
8,9,11,12,18
8,9,11,12,18
8,9,11,12,18

44+m'
83+m'
90+4>+m'
180+m'
185+m'

JMP ~ Unconditional jump:
Short/long

Indirect intersegment

7+m

7+m,ll+m' 7+m,11+m'

Protected Mode Only (Direct intersegment):
Via call gate to same privilege level
Via call gate to different privilege level, no parameters
Via call gate to different privilege level, xparameters
V,aTSS
Via task gate

Indirect tntersegment

I

Protected Mode Only (Indirect Intersegment):
Via call gate to same privilege level
VIaTSS
Via task gate

2

9,18

23+m

11,12,18

38+m
175+m
180+m

8,11,12,18
8,11,12,18
8,11,12,18

26+m'

2

41+m'
178+m'
183+m'

8,9,11,12,18

8,9,11,12,18
8,9,11,12,18
8,9,11,12,18

RET ;

Return from CALL:
Within segment

11 1 0 0 0 0 1 1

Within seg adding immed to SP

11 1 0 0 0 0 1 01

Intersegment

11 1 0 0 1 0 1 11

Intersegment adding immediate to SP

11 1 0 0 1 0 1

.

I

oI

data-low

data-low

I

I

data-high

data-high

I
I

Protected Mode Only (RET):
To different privilege level

11+m

11+m

2

II+m

11+m

2

8,9,18

15+m

25+m

2

8,9,11,12,18

2

8,9,11,12,18

15+m

55+m

8,9,18

9,11,12,18

Shaded areas indicate instructions not available in iAPX 86,88 microsystems_

4-49

210253-007

"l1teIe.

I

IAPl;( 286/10

..

80286 INSTRUCTION SET

FUNCTION

~@W~OO©I§ OOO[F@ffi1[M)~ii'O@OO

FORMAT

Re.1

Reel

Addn.s

Addn81

Protected
VlrlUal

Made

Mode

Addn81
MOde

JElJZ=JumponequaJ/l8ro

10 11.1 01 0 0

disp

7+mor3 7+mor3

18

J'{JNGE = Jumpon IessIootgrealerorequ~

10 11 1 1 1 0 0

dlsp

7+mor3 7+mor3

18

JLElJNG =Jumpon less orequallnotgrealer

10 11 1 1 1 1 0

disp

7+mor3 7+mor3

18

JBlJNAE = Jump onbeioo/notaboYe orequ~

10 11 1 001 0

dlsp

7+mor3 7+mor3

18

JBElJNA= JumponbelOOOlequalJnotabove

10 1 1 1 01 1 0

dlsp

7+mor3 7+mor3

18

JP/JPE= JllnponpantylpantyMII

10 11 1 1 01 0

dlsp

7+mor3 7+mor3

18

JO = Jump onoverlllw

10 1 1 1 0 0 0 0

disp

7+mor3 7+mor3

18

JS=JumpooslJi

10 1 1 1 1 00 0

dlsp

7+mor3 7+mor3

18

JNElJNZ = Jumpon notequaVnot18ro

10 1 1 1 01'0 1

dlsp

7+mor3 7+mor3

18

JNLlJGE Jumpon notlesslgreaterorequal

10 11 1 1 1 0 1

dlsp

7+mor3 7+mor3

18

JNLElJG = Jumpon notlessorlQlllilgrealer

10 11 1 1 1 1 1

disp

7+mor3 7+mor3

18

JNB/JAE =Jumpoo notbelowlaboveorequal

10 11 1 001 1

disp

7+mor3 7+mor3

18

=

I

JNBElJA= Jumponnotbeloworequallabove

10 11 1 01 1 1

dlsp

7+mor3 7+mor3

18

JNP/JPO = Jump oonotparlparlidd

10 11 1 1 01 1

dlsp

7+mor3 7+mor3

18

JNO=.ltlnponnotoverlow

10 11 1 000 1

dlsp

7+mor3 7+mor3

18

JNS=Jumponnot~gn

10 1 1 1 1 00 1

dlsp

7+mor3 7+mor3

18

LOOP = loo!i CX1Jmes

11 1 1 0 0 0 1 0

dlsp

8+mor4 8+mor4

18

LOOPZlLOOPE = loopWhiezeroiequai

11 1 1 0 0 0 0 1

disp

8+mor4 8+mor4

18

LOOPllZlLOOPNE = ~ MIle not zero/equal

11 HOOOOO
11 11 0001 1

disp

8+mor4 8+mor4

18

drsp

8+mor4 8+mor4

18.

JC:XZ = Jump 00 CX zero

2,&·

.J.8

2,8

U
INT= Intel'fllpt
Type specified

11 1001 1 0 1

23+m

2,7,8

lYpe3

11 1001 1 0 0

23"tm

2,7,8

INTO = Inlerrupl on overflow

11

2l+mor3
(3dno

(3dno

Ilttrrupti

InIlmrpfj

I
I
1001 1 1 0 I

type

Pnlecled Made Only:
Via interrupt or lrap gate to same privilege level
Via interrupt ortrap gate to 111 different privilege level
Via Task Gate
IRET = Interrupt return

11 1001 11

17+m

.8.9

2,6,8

4O+m
78+m
167+m

11

8.!1

$,9
1/,'

31+m

7,8,11,12,18
7,8,11,12,18
7,8,11,12,18
2,4

8,9,11,12,15,18

PnIIecIe. Mode Only:
To different privilege level
To dlfferenllesk (NT 1)

55+m
169+m

=

8,9,11,12,15,18
8,9,11,12,18

Wlttt.lt

Shaded areas indicate instructions not available in iAPX 86,88 microsystems.

.,

4-50

210253-007

iAPX 286/10

80286 INSTRUCTION SET SUMMARY
Real
Address
Mode

FUNCTION

FORMAT

PROCESSOR CONTROL
CLC = Clear carry

11 1 1 1 1 00 0

I

CMC = Complement carry

11 1 1 1 01 0 1

I

sre = Set carry
CLD = Clear direction

11 1 1 1 1 00 1

sm = Set direction

11

CLI =Clear Interrupt

11

STt = Set interrupt

11

HLT=Halt

11

WAIT =wait

11

LOCK =Bus lock prefix

11

Protected
Vtrtuat
Addres.
Mode

Reel
Address
Mode

I
I
111110 1I
111 1 0 1 0I
111101 1I
111 0 10 0I
00 1 1 0 1 1 I
111 0 00 0I

Protected

Vlrt••1
Addre••
Mode

11 1 1 1 1 1 0 0

14
14
13
14

ESC = Processor Extension Escape

9-20'

5,8

8,17

, 9.13
il
$,13
il
9,11,13
9

9.11.13

9
9.t3
9

9,11.16
9,11,1.

8,9
9,11,16
9,lf.18

Shaded areas indicate instructions not available in iAPX 86, 88 microsystems.

4-51

210253-007

iAPX 286/10

The effective Address (EA) of the memory operand is
computed according to the mod and rim fields:

REG is assigned according to the following table:

16-Bit (w = 1)
000
001
010
011
100
101
110
111

if mod = 11 then rim is treated as a REG field
if mod

= 00 then OISP = 0', disp-Iow and disp-high

are absent
if mod

= 01 then OISP = disp-Iow sign-extended to

16-bits, disp-high is absent
if mod

= 10 then OISP = disp-high: disp-Iow

if rim = 000 then EA = (BX) + (SI) + OISP
if rim = 001 then EA = (BX)
if rim
if rim
if rim
if rim
if rim
if rim

AX
CX
OX
BX
SP
BP
SI
01

a-Bit (w ;= 0)
000
001
010
011
100
101
110
111

AL
CL
OL
BL
AH
CH
OH
BH

+ (01) + OISP

= 010 then EA = (BP) + (SI) + OISP
= 011 then EA = (BP) + (01) + OISP
= 100 then EA = (SI) + OISP
= 101 then EA = (01) + OISP
= 110 then EA = (BP) + OISP'
= 111 then EA = (BX) + OISP

The physical addresses of all operands addressed by
the BP register are computed using the SS segment
register. The physical addresses of the destination operands of the string primitive operations (those addressed by the 01 register) are computed using the ES
, segment, which may not be overridden.

OISP follows 2nd byte of instruction (before data if
required)
'except if mod = 00 and rim = 110then EA

= disp-hlgh.dlsp-Iow.

SEGMENT OVERRIDE PREFIX
10 0 1 reg 1 1 01
reg is assigned according to.the following:

reg

Segment
Register

00
01
10
11

ES
CS
SS
OS

4-52

210253-007

IAPX 286/10

268-5400-00 \0

268-5400-51

'\

GUIDE BOSS

3 PLes

INDEX

J

------+I'f;--PC BOARD PATTERN
~

~~1!~"t:~~~~
~

i%

HOlE~

PIN ClR
•
FOR I .021 OIA +
(O.74)-r.1-Ii.

.oaa :-:J

CONTACT TAil

q'"
~

~I

+0

ALUMINUM LID
00

~54)
......
I'
/+I ;:) TVP

~~~~~~T ~~>-»»»~-!- t
..:!1!
ii.....~••••••••
(0.31)., ti
L ----l
~ 1+
o
(0.51)

I

~E~;rATION .r+I FRONT

-V7+1

DEVICE PADS ! + /"
SHOWN FOR
CONTACT
F)LOCATION ~ !

-'tSOCKET LIENTATION PIN

.rPINNOl

Ii.-.FRONT

1.00
Ii.
(2.54) TVP
.100
(20.32)
I SPCS. ~TOl NON ACCUM TVP 4 PlCS
(2.54)

(HEATSINK PROVISIONS OPTIONAL)
TEST PROBE POINT

.342

!t

(8 .•1)

.100

\

;;:7.--

~JL~_

:.~) TVP 5 PlCS

OPEN

Ii.

(2.54)

Figure 36. Textool 68 Lead Chip Carrier Socket

4... 53

210253-007

80287
80-Bit HMOS
NUMERIC PROCESSOR EXTENSION

80287-3
• Implements Proposed IEEE Floating
Point Standard 754

• Protected Mode Operation Completely
Conforms to the iAPX 286 Memory
Management and Protection
Mechanisms

• Expands iAPX 286/10 Datatypes to
Include 32-, 64-, 80-Bit Floating Point,
32-, 64-Bit Integers and 18-Digit BCD
Operands

• Directly Extends iAPX 286/10 Instruction
Set to Trigonometric, Logarithmic,
Exponential and Arithmetic Instructions
for All Datatypes

• Object Code Compatible with 8087
• BUilt-in Exception Handling

• 8x80-Bit, Individually Addressable,
Numeric Register Stack

• Operates in Both Real and Protected
Mode iAPX 286 Systems

• Available in EXPRESS-Standard
Temperature Range

• High Performance 80-Bit Internal
Architecture

The Intel® 80287 is a high performance numerics processor extension that extends the iAPX 286/10
architecture with floating point, extended integer and BCD data types. The iAPX 286/20 computing system
(80286 with 80287) fully conforms to the proposed IEEE Floating Point Standard. Using a numerics
oriented architecture, the 80287 adds over fifty mnemonics to the iAPX 286/20 instruction set, making the
iAPX 286/20 a complete solution for high performance numeric processing. The 80287 is implemented in
N-channel, depletion load, silicon gate technology (HMOS) and packaged in a 40-pin ceramic package.
The iAPX 286/20 is object code compatible with the iAPX 86/20 and iAPX 88/20.

READY

So
8US INTERFACE UNIT

CKM

COD/INTA

NUMERIC EXECUTION UNIT

N.C.

T~~~--"

DI.
DI'

HLDA

4

CLK286
PEACK

RESET

Ni'S1
NPS2

Vee
Vss

CLK

DID

CMDO

N.C.

NPWR

CMD1

Vss

D9

-

_

~

--~
~

_ L ______

"'""""""
,",

~-_ .~BI~~

_-~ _ _ _ _ _ ~ ~

NPRD
ERROR

D7

BUSY

De

PEREa

DS
D.

DO

D.

D2

NOTE:
N.C. PINS MUST NOT BE CONNECTED.

Figure 2. 80287 Pin Configuration

Figure 1. 80287 Block Diagram

Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit
Patent Licenses are Implied.
January 1985
© INTEL CORPORATION, 1983.
Order Number: 210920-003

4-54

80287

Table 1. 80287 Pin Description
Symbols

Type

Name and Function

ClK

I

Clock input: this clock provides the basic timing for internal 80287 operations. Special MOS level inputs are required. The 82284 or 8284A ClK
outputs are compatible to this input.

CKM

I

Clock Mode signal: indicates whether ClK input is to be divided by 3 or
used directly. A HIGH input will cause ClK to be used directly. This input
may be connected to Vcc or Vss as appropriate. This input must be either
HIGH or lOW 20 ClK cycles before RESET goes lOW.

RESET

I

System Reset: causes the 80287 to immediately terminate its present activity and enter a dormant state. RESET is required to be HIGH for more than
480287 ClK cycles. For proper initialization t~e HIGH-lOW transition must
occur no sooner than 50 f.Ls after Vee and ClK meet their D.C. and A.C.
specifications.

015-00

I/O

Data: 16-bit bidirectional data bus. Inputs to these pins may be applied
asynchronous to the 80287 clock.

BUSY

0

Busy status: asserted by the 80287 to indicate that it is currently executing
a command.

ERROR

0

Error status: reflects the ES bit of the status word. This signal indicates
that an unmasked error condition exists.

PEREa

0

Processor Extension Data Channel operand transfer request: a HIGH on
this output indicates that the 80287 is ready to transfer data. PEREa will be
disabled upon assertion of PEACK or upon actual data transfer, whichever
occurs first, if no more transfers are required.

PEACK

I

Processor Extension Data Channel operand transfer ACKnowledge: acknowledges that the request signal (PEREa) has been recognized. Will
cause the request (PEREa) to be withdrawn in case there are no more
transfers required. PEACK may be asynchronous to the 80287 clock.

NPRD

I

Numeric Processor Read: Enables transfer of data from the 80287. This
input may be asynchronous to the 80287 clock.

NPWR

I

Numeric Processor Write: Enables transfer of data to the 80287. This input
may be asynchronous to the 80287 clock.

NPS1, NPS2

I

Numeric Processor Selects: indicate the CPU is performing an ESCAPE instruction. Concurrent assertion of these signals (i.e., NPSl is lOW and NPS2 is
HIGH) enables the 80287 to perform floating point instructions. No data transfers involving the 80287 will occur unless the device is selected via these
lines. These inputs may be asynchronous to the 80287 clock.

CMD1, CMDO

I

Command lines: These, along with select inputs, allow the CPU to direct the
operation of the 80287These inputs may be asynchronous to' the 80287 clock.

4-55

210920-003

80287

Table 1. 80287 Pin Description (cont.)
Type

Name and Function

ClK286

I

CPU Clock: This input provides a sampling edge for the 80287 inputs S1, SO,
COD/INTA, READY, and HlDA. It must be connected to the 80286 ClK input.

S1,SO
COD/INTA

I

Status: These inputs must be connected to the corresponding 80286 pins.

HlDA

I

Hold Acknowledge: This input informs the 80287 when the 80286 controls
the local bus. It must be connected to the 80286 HlDA output.

READY

I

Ready: The end of a bus cycle is signaled by this input. It must be connected
to the 80286 READY input.

VSS

I

System ground, both pins must be connected to ground.

Vee

I

+5V supply

Symbols

effectively extends the register and instruction set
of an iAPX 286/10 system for existing iAPX 286
data types and adds several new data types as well.
Figure 3 presents the program visible register
model of the iAPX 286/20. Essen~ially, the 80287
can be treated as an additional resource or an
extension to the iAPX 286/10 that can be used as a
single unified system, the iAPX 286/20.

FUNCTIONAL DESCRIPTION
The 80287 Numeric Processor Extension (NPX)
provides arithmetic instructions for a variety of
numeric data types in iAPX 286/20 systems. It also
executes numerous built-in transcendental functions (e.g., tangent and log functions). The 80287
executes instructions in parallel with a 80286. It

80287
STACK:

80286
15

o I

FILE:

I

AX

I
I
I
I

BX
CX
OX
51

I

01

I

BP
SP

I

79
SIGN

R1

78

64 63
EXPONENT

0

TAG FIELD
0
1

SIGNIFICAND

R2
R3
R4
RS
RS
R7
R8

IL _ _ ,
15

I

FLAGS

I:

CONTROL REGISTER
STATUS REGISTER

L _ _ _ _ -.,

15

;11

o

15

o I

IP

0

TAG WORD

I
I

I- INSTRUCTION POINTER -

I

I-

DATA POINTER

1 II

-

Figure 3. iAPX 286/20 Architecture

4-56

210920-003

80287

The 80287 has two operating modes similar to the
two modes of the 80286. When reset, 80287 is in
the real address mode. It can be placed in the
protected virtual address mode by executing .the
SETPM ESC instruction. The 80287 cannot be
switched back to the real address mode except by
reset. In the real address mode, the iAPX 286/20 is
completely software compatible with iAPX 86/20,
88/20.
Once in protected mode, all references to memory
for numerics data or status information, obey the
iAPX 286 memory management and protection
rules giving a fully protected extension of the
80286 CPU. In the protected mode, iAPX 286/20
numerics software is also completely compatible
with iAPX 86/20 and iAPX 88/20.

HARDWARE INTERFACE
Communication of instructions and data operands
between the 80286 and 80287 is handled by the
CMDO, CMD1, NPS1, NPS2, NJ5Ii[), and NJ5WR signals. lID port addresses 00F8H, OOFAH, and OOFCH
are used by the 80286 for this communication. When
any of these addresses are used, the NJ5S1 input
must be lOW and NPS2 input HIGH. The IUIiC and
inWC outputs of the 82288 identify 110 space transfers (see Figure 4). CMDOshould be connected to
latched 80286 A1 and CMD1 should be connected to
latched 80286 A2. The ST, 50, COD/JNTA,REAOY,
HlDA, and ClK pins of the 80286 are connected to
the same named pins on the 80287.
I/O ports 00F8H to OOFFH are reserved for the
80286/80287 interface. To guarantee correct operation of the 80287, programs must not perform any
I/O operations to these ports.

SYSTEM CONFIGURATION
As a processor extension to an 80286, the 80287
can be connected to the CPU as shown in Figure 4.
The data channel control Signals (PEREQ,
PEACK), the BUSY Signal and the NPRD, NPWR
signals, allow the NPX to receive instructions and
data from the CPU. When in the protected mode, all
information received by the NPX is validated by the
80286 memory management and protection unit.
Once started, the 80287 can process in parallel
with and independent of the host CPU, When the
NPX detects an error or exception, it will indicate
this to the CPU by asserting the ERROR signal.

The PEREQ, PEACK, BUSY, and ERROR signals of
the 80287 are connected to the same-named 80286
input. The data pins 0.1 the 80287 should be directly
connected to the 80286 data bus. Note that all bus
drivers connected to the 80286 local bus must be
inhibited when the 80286 reads from the 80287.
The use of COD/INTA and M/ra in the decoder
prevents INTA bus cycles from disabling the data
transceivers.

PROGRAMMING INTERFACE

The NPX uses the processor extension request and
acknowledge pins of the 80286 CPU to implement
data transfers with memory under the protection
model of the CPU. The full virtual and physical
address space of the 80286 is available. Data for
the 80287 in memory is addressed and represented
in the same manner as for an 8087.

Table 2 lists the seven data types the 80287 supports and presents the format for each type. These
values are stored in memory with the least significant digits at the lowest memory address. Programs retrieve these values by generating the
lowest address. All values should start at even
addresses for maximum system performance.

The 80287 can operate either directly from the CPU
clock or with a dedicated clock. Foroperation with
the CPU clock (CKM=O), the 80287 works at onethird the frequency of the system clock (i.e., for an
8 MHz 80286, the 16 MHz system clock is divided
down to 5.3 MHz). The 80287 provides a capability
to internally divide the CPU clock by three to produce the required internal clock (33% duty cycle).
To use a higher performance 80287 (8 MHz), an
8284A clock driver and appropriate crystal may be
used to directly drive the 80287 with a 1/3 duty
cycle clock on the ClK input (CKM=1).

Internally the 80287 holds all numbers in the temporary real format. load instructions automatically convert operands represented in memory as
16-, 32-, or 64~bit integers, 32- or 64-bit floating
point number or 18-digit packed BCD numbers
into temporary real format. Store instructions perform the reverse type conversion.
80287 computations use the processor's register
stack. These eight 80-bit registers provide the
equivalent capacity of 40 16-bit registers. The
80287 register set can be accessed as a stack, with

4-57

210920-003

inter

80287

Vee

;;

20Kn

RESET

a

Vee

iiEADv
82284

-

ClK

"L:.-

Si
So

<;.'

20Kn

20Kn

I

ADDRESS

~--~~'::'--+-----~~~;~~~~~~~~~I<~~~~~[~~~~~~~!C~~~~<~-

~

A'5-Ao

'-~f-I

RESET

iiEADv ~~~~--~~~
ClK

~~"",+-+-~~ClK

Si ~H""""+-I---+-+-I 81
So t-t-I-++-I--t-+--I So

80286
D,s-Do

M/iO t-t-I-++-r.-t-+--I M/iO

--

I- EFiRoR PEREa ' 82288

~

,

BUSY

PEACK

~

COD/iN'i'A HlDA

A2 A1 AO E1
8205
r - - - E2
_
I....,;E:;:3~__..;;G,f_...

DEN

~4-~1

r-----~

DT/R

iOWC

D D

1-C-+--I--_----II Cl:

ALE
IORC

ra a a

COD/INTA HlDA
'---t-H RESET PEACK

-

'---t-i-l READY PEREa -

~

~

<>----I-I--1HOE

t---I-+-I ClK286

'-+---+-+--181

T
D,s-Do -DATA
8:6
80287
t------------------r-r-......-t 8287

'---+--++-1 So
'-----+----+-+-1 NPRD

'-------I--~~-iNPWR

r----,

~

ERROR

~

BUSY
ClK

NPS2 -Vee

=>

-

NPS1t---------~
CMD1 t - - - - - - - - - - - - - '
CMDOt---------------~

CKM

:r:--,
,
/
C'
8284A
------<>'
:i:_JL ___ -',

Figure 4, iAPX 286/20 System Configuration

4-58

210920-003

$0287

Table 2. 80287 Datatype Representation in Memory
Data
Formats

Word Integer

Precision

104

16 Bits

7 017 017 017 017 017 017 017 017 017 01
I (TWO'S
COMPLEMENT)
15

Short Integer

109

0

I (TWO'S
COMPLEMENT)

32 Bits
31

.Long Integer

HIGHEST ADDRESSED BYTE

Most Significant Byte
Range

1019

0

I(TWO'S
COMPLEMENT)

64 Bits
63

Packed BCD

1018

18 Digits

sl
79

Short Real

10±38

24 Bits

0

x

I

MAGNITUDE

d17

10±308

53 Bits

;1 EXPONENT
BIASED I

64 Bits

SIGNIFICAND

23'-

sl

d9

dB

d7

d,

ds

dJ

d,

d2

d,

do

I

SIGNIFICAND

52'-

BIASED
EXPONENT

I
0

I.

I

BIASED
EXPONENT

63

Temporary Real 10±4932

dlO

0

5

sl

d 14 d 13 d 12 d 11

72

31

Long Real

d 1b d 15

hl

I
0

I.

I

SIGNIFICAND

64 63"

79

NOTES:
(1) S = Sign bit (0 = positive, 1 = negative)
(2) dn = Decimal digit (two per byte)
(3) X= Bits have no significance; 8087 ignores when loading, zeros when storing.
(4) • = Position of implicit binary point
(5) I = Integer bit of significand; stored in temporary real,
implicit in short and long real

0

(6) Exponent Bias (normalized values):
Short Real: 127 (7FH)
Long Real: 1023 (3FFH)
Temporary Real: 16383 (3FFFH)
(7) Packed BCD: (-l)s(D17 ... 0 0)
(8) Real: (-1 )S(2E-BIAS)(Fo F1... )

instructions operating on the top one or two stack
elements, or as a fixed register set, with instructions operating on explicitly designated registers.
Table 6 lists the 80287's instructions by class. No
special programming tools are necessary to use
the 80287 since all new instructions and data types
are directly supported by the iAPX 286 assembler

4-59

and appropriate high level languages. All iAPX
86/88 development tools which support the 8087
can also be used to develop software for the iAPX
286/20 in real address mode.

Table 3 gives the execution times of some typical
numeric instructions.

210920-003

80287

Table 3. Execution Time for Selected 80287 Instructions
Approximate Execution
Time (J.Ls)
Floating Point Instruction

80287
(5 MHz Operation)
14/18

Add/Subtract
Multiply (single precision)

19

Multiply (extended precision)

27

Divide

39

Compare

9

Load (double precision)

10

Store (double precision)

21

Square Root

36

Tangent

90

Exponentiation

100

SOFTWARE INTERFACE

PROCESSOR ARCHITECTURE

The iAPX 286/20 is programmed as a single processor. All communication between the 80286 and
the 80287 is transparent to software. The CPU automatically controls the 80287 whenever a numeric
instruction is executed. All memory addressing
modes, physical memory, and virtual memory of .
the CPU are avail~ble for use by the NPX.

As shown in Figure 1, the NPX is internally divided
into two processing elements, the bus interface
unit (BIU) and the numeric execution unit (NEU).
The NEU executes all numeric instructions, while
the BIU receives and decodes instructions,' requests operand transfers to and from memory and
executes processor control instructions. The two
units are able to operate independently of one
another allowing the BIU to maintain asynchronous communication with the CPU while the NEU
is busy processing a numeric instruction.

Since the NPX operates in parallel with the CPU,
any errors detected by the NPX may be reported
after the CPU has executed the ESCAPE instruction which caused it. To allow identification of the
failing numeric instruction, the NPX contains two
pointer registers which identify the address of the
failing numeric instruction and the numeric
memory operand if appropriate for the instruction
encountering this error.

INTERRUPT DESCRIPTION
Several interrupts of the iAPX 286 are used to
report exceptional conditions while executing
numeric programs in either real or protecteq
mode. The interrupts and their functions are
shown in Table 4.
.

4-60

BUS INTERFACE UNIT
The BIU decodes the ESC instruction executed by the
CPU. If the ESC code defines a math instruction, the
BIU transmits the formatted instruction to the NEU. If
the ESC code defines an administrative instruction,
the BIU executes it independently of the NEU. The
parallel operation of the NPX with the CPU is normally
transparant to the user. The BIU generates the BOSY
and ERROR signals for 80826/80287 processor synchronization and error notification, respectively.
The 80287 executes a single numeric instruction at
a time. When executing most ESC instructions, the

210920-003

80287

Table 4. 80286 Interrupt Vectors Reserved for NPX
Interrupt Number

Interrupt Function

7

An ESC instruction was encountered when EM or TS of the 80286 MSW was set.
EM=1 indicates that software emulation of the instruction is required. When TS is
set, either an ESC or WAIT instruction will cause interrupt 7. This indicates that the
current NPX context may not belong to the current task.

9

The second or subsequent words of a numeric operand in memory exceeded a
segment's limit. This interrupt occurs after executing an ESC instruction. The saved
return address will not point at the numeric instruction causing this interrupt. After
processing the addressing error, the iAPX 286 program can be restarted at the
return address with IRET. The address of the failing numeric instruction and
numeric operand are saved in the 80287. An interrupt handler for this interruptmust
execute FNINIT before any other ESC or WAIT instruction.

13

The starting address of a numeric operand is not in the segment's limit. The return
address will point at the ESC instruction, including prefixes, causing this error. The
80287 has not executed this instruction. The instruction and data address in 80287
refer to a previous, correctly executed, instruction.

16

The previous numeric instruction caused an unmasked numeric error. The address
of the faulty numeric instruction or numeric data operand is stored in the 80287.
Only ESC or WAIT instructions can cause this interrupt. The 80286 return address
will point at a WAIT or ESC instruction, including prefixes, which may be restarted
after clearing the error condition in the NPX.

80286 tests the eosY pin and waits until the 80287
indicates that it is not busy before initiating the command. Once initiated, the 80286 continues program
execution while the 80287 executes the ESC instruction. In iAPX 86/20 systems, this synchronization is
achieved by placing a WAIT instruction before an ESC
instruction. For most ESC instructions, the iAPX 286/20
does not require a WAIT instruction before the ESC
opcode. However, the iAPX 286/20 will operate correctly with these WAIT instructions. In all cases, a WAIT
or ESC instruction should be inserted after any 80287
store to memory (except FSTSW and FSTCW) or load
from memory (except FLDENV or FRSTOR) before the
80286 reads or changes the value to be sure the
numeric value has already been written or read by
the NPX.
Data transfers between memory and the 80287,
when needed, are controlled by the PEREQ
PEACK, NPRD, NPWR, NPS1, NPS2 signals. The
80286 does the actual data transfer with memory
through its processor extension data channel.
Numeric data transfers with memory performed by
the 80286 use the same timing as any other bus

cycle. Control signals for the 80287 are generated
by the 80826 as shown in Figure 4, and meet the
timing requirements shown in the AC requirements section.

NUMERIC EXECUTION UNIT
The NEU executes all instructions that involve the
register stack; these include arithmetic, logical, transcendental, constant and data transfer instructions.
The data path in the NEU is 84 bits wide (68 significand bits, 15 exponent bits and a sign bit) which
allows internal operand transfers to be performed at
very high speeds.
When the NEU begins executing an instruction, it
activates the BIU BUSY signal. This signal is used
in conjunction with the CPU WAIT instruction or
automatically with most of the ESC instructions to
synchronize both processors.

REGISTER SET
The 80287 register set is shown in Figure 5. Each of
the eight data registers in the 8087's register stack

4-61

210920-003

"n+_I®
. III-e-

80287

_ DATA FIELD

~~79~r7~8~~~~6~4r6~3__~~~==~~
SIGN

EXPONENT

SIGNIFICAND

____-10

TAG FIELD

1

0

o

15
CONTROL REGISTER
STATUS REGISTER
TAG WORD

r- INSTRUCTION POINTER t-

DATA POINTER

-

Figure 5. 80287 Register Set

is 80 bits wide and is divided into "fields" corresponding to the NPX's temporary real data type.

The instructions FSTSW, FSTSW AX, FSTENV, and
FSAVE which store the status word are executed
exclusively by the BIU and do not set the busy bit
themselves or require the Busy bit be cleared in
order to be executed.

At a given point in time the TOP field in the status
word identifies the current top-of-stack register. A
"push" operation decrements TOP by 1 and loadsa
value into the new top register. A "pop" operation
stores the value from the current top register and
then increments TOP by 1. Like 80286 Stacks in
memory, the 80287 register stack grows "down"
toward lower-addressed registers.

The four numeric condition code bits (C O-C 3) are
similar to the flags in a CPU: instructions that perform
arithmetic operations update these bits to reflect the
outcome of NPX operations. The effect of these
instructions on the condition code bits is summarized
in T~bles 5a and 5b.

Instructions may address the data registers either
implicitly or explicitly. Many instructions operate on
the register at the TOP of the stack. These instructions
implicitly address the register pointed by the TOP.
Other instructions allow the programmer to explicitly
specify the register which is to be used. T\1is explicit
register addressing is also "top-relative."

Bits 14-12 of the status word pOint to the 80287 register that is the current top-of-stack (TOP) as described
above. Figure 6 shows the six error flags in bits 5-0 of
the status word. Bits 5-0 are set to indicate that the
NEU has detected an exception while executing an
instruction. The section on exception handling explains
how they are set and used.

STATUS WORD

Bit 7 is the error summary status bit. This bit is set il
any unmasked exception bit is set and cleared otherwise. II this bit is set, the ERROR signal is asserted.

The 16-bit status word (in the status register)
shown in Figure 6 reflects the overall state of the
80287. It may be read and inspected by CPU code.
The busy bit (bit 15) indicates whether the NEU is
executing an instruction (B = 1) or is idle (B = 0).

4-62

210920-003 I

"nt_I'"
111'eII '

80287

o

15
I B

1c..1 TOP ICd C, ICoIESI X IPEluEloElzEIDEI rEI

.

I

EXCE PTION FLAGS (1 ~ EXCEPTION HAS OCCURRED)
INVALID OPERATION'
DENORMALIZED OPERAND'
ZERO DIVIDE'
OVERFLOW'
UNDERFLOW'
PRECISION'
(RESE RVED)
ERROR SUM!IIARY STATUS!')
COND 1TI01i! COD.:'2)
TOP OF STACK POINTER(3)
NEU BUSY

g:ES IS SET IF ANY UNMASKED EXCEPTION BIT IS SET, CLEARED OTHERWISE.
(3)~g~ ~~~b~~ FOR CONDITION CODE INTERPRETATION.

000
001

~

~

Register 0 is Top of Stack
Register 1 is Top of Stack

"
111

~ Register "
7 Is Top of Stack

"For definitions, see the section on exception handling

Figure 6. 80287 Status Word

TAG WORD
The tag word marks the content of each register as
shown in Figure 7. The principal function of the tag
word is to optimize the NPX's performance. The eight
two-bit tags in the tag word can be used, however, to
interpret the contents of 80287 registers.
INSTRUCTION AND DATA POINTERS
The instruction and data pointers (See Figures 8a
and 8b) are provided for user-written error handlers. Whenever the 80287 executes a new instruction, the BIU saves the instruction address, the
operand address (If present) and the instruction
opcode. 80287 instructions can store this data into
memory.
The instruction and data pointers appear in one of
two formats depending on the operating mode of
the 80287. In real mode, these values are the 20-bit
physical address and 11-bit opcode formatted like
the 8087. In protected mode, these values are the
32-bit virtual addresses used by the program

4-63

which executed an ESC instruction. The same
FLDENV/FSTENV/FSAVE/FRSTOR instructions as
those of the 8087 are used to transfer these values
between the 80287 registers and memory.
The saved instruction address in the 80287 will
point at any prefixes which preceded the instruction. This is different than in the 8087 which only
pointed at the ESCAPE instruction opcode.
CONTROL WORD
The NPX provides several processing options
which are selected by loading a word from memory
into the control word. Figure 9 shows the format
and encoding of fields in the control word.
The low order byte of this control word configures
the 80287 error and exception masking. Bits 5-0 of
the control word contain individual masks for each
of the six exceptions that the 80287 recognizes.
The high order byte of the control word configures
the 80287 operating mode including precision,

210920-003

80287

Table Sa. Condition Code Interpretation
Instruction
Type
Compare, Test

Remainder

Examine

Cs

~

C1

Co

0
0
1
1

0
0
0
1

X
X
X
X

0
1
0
1

01

0

00

~

U

'1

U

U

Complete reduction with
three low bits of quotient
(See Table 5b)
Incomplete Reduction

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Valid, positive unnormalized
Invalid, positive, exponent =0
Valid, negative, un normalized
Invalid"negative, exponent =0
Valid, positive, normalized
Infinity, positive
Valid, negative, normalized
Infinity, negative
Zero, positive
Empty
Zero, negative
Empty
Invalid, positive, exponent = 0
Empty
Invalid, negative, exponent = 0
Empty

"- ,

0
0
0
1
1
1
1

Interpretation
ST
ST
ST
ST

> Source or 0 (FTST)
< Source or 0 (FTST)
= Source or 0 (FTST)
is not comparable

,

NOTES:
1. ST = Top of stack
2. X = value is not affected by instruction
3. U = value is undefined following instruction
4. Qn = Quotient bit n

Table 5b. Condition Code Interpretation after
FPREM Instruction As a Function of
Dividend Value
Dividend Range
Dividend < 2 • Modulus
Dividend < 4 • Modulus
Dividend ~ 4 • Modulus

~

Q1

00

Ca
Ca

C1
01
01

00
00
00

02

NOTE:
1. Previous value of indicated bit, not affected by FPREM
instruction execution.

rounding, and infinity control. The precision control bits (bits 9-8) can be used to set the 80287
internal operating precision at less than the
default of temporary real (80-bit) precision. This
can be useful in providing compatibility with the
early generation arithmetic processors of smaller
precision than the 80287. The rounding control
bits (bits 11-10) provide for directed rounding and
true chop as well as the unbiased round to nearest
even mode specified in the IEEE standard. Control
over closure of the number space at infinity is also
provided (either affine closure: ± 00, or projective
closure: 00, is treated as unsigned, may be
specifieCl).

4-64

210920-003

inter

80287

TAG VALUES:
00 = VALID
01 = ZERO
10 = INVALID or INFINITY
11 = EMPTY

NOTE: The index i of tag(i) is not top-relative. A program
typically uses the "top" field of Status Word to determine which tag(i) field refers to logical top of stack.

Figure 7. 80287 Tag Word

MEMORY OFFSET

o

15
CONTROL WORD

+0

STATUS WORD

+2

TAG WORD

+4

IPOFFSET

+6

CS SELECTOR

+8

DATA OPERAND OFFSET

+10

DATA OPERAND SELECTOR

+12

Figure 8a. Protected Mode 80287 Instruction and Data Pointer Image in Memory

EXCEPTION HANDLING

INDEFINITE, or to propagate already existing NANs
as the calculation result.

The 80287 detects six different exception conditions
that can occur during instruction execution. Any or
all exceptions will cause the assertion of external
El1RCJR" signal and ES bit of the Status Word if the
appropriate exception masks are not set.

Overflow: The result is too large in magnitude to
fit the specified format. The 80287 will generate an
encoding for infinity if this exception is masked.
Zero Divisor: The divisor is zero while the dividend is a non-infinite, non-zero number. Again, the
80287 will generate an encodjng for infinity if this
exception is masked.

The exceptions that the 80287 detects and the 'default'
procedures that will be carried out if the exception is
masked, are as follows:
Invalid Operation: Stack overflow, stack underflow,
indeterminate form (0/0, 00, - 00, etc) or the use of a
Non-Number (NAN) as an operand. An exponent value
of all ones and non-zero significand is reserved to
identify NANs. If this exception is masked, the 80287
default response is to generate a specific NAN called

Underflow: The result is non-zero but too small in
magnitude to fit in the specified format. If this
exception is masked the 82087 will denormalize
(shift right) the fraction until the exponent is in
range. The process is called gradual underflow.

4-65

210920-003

80287

o

15
CONTROL WORD

+0

STATUS WORD

+2

TAG WORD

+4

INSTRUCTION POINTER (1!>-0)

+6

;)1 1

INSTRUCTION
POINTER (19-16) 0

INSTRUCTION
OPCODE (10-0)

+8

DATA POINTER (1!>-0)
DATA POINTER
(19-16)
15

MEMORY
OFFSET

I

+10

+12

0

o

1211

Figure 8b. Real Mode 80287 Instruction and Data POinter Image in Memory

o

16
IxxxllclRCl

PC

1 xl xjPMlu~oMlzMIDt.1IMJ

I

EXCEPTION MASKS (1: EXCEPTION IS MASKED)
INVALID OPERATION
DENORMALIZED OPERAND
ZERO DIVIDE
OVERFLOW
UNDERFLOW
PRECISION
(RESERVED)
(RESERVED)
PRECISION CONTROL 11)
RpUNDING CONTROLI2 )
INFINITY CONTROL (0 : PROJECTIVE, 1 : AFFINE)
(RESERVED)

11)PRECISION CONTROL

00 = 24 BITS (SHORT REAL)
01 = RESERVED
10 53 BITS (LONG REAL)
'1 64 BITS (TEMP REAL)

=
=

(2)ROUNDING CONTROL
00 : ROUND TO NEAREST OR EVEN
01 : ROUND DOWN (TOWARD -x)
10 : ROUND UP (TOWARD +x)
11 : CHOP (TRUNCATE TOWARD ZERO)

Figure 9. 80287 Control Word

4-66

210920-003

80287

Denormallzed Operand: At least one of the
operands is...denormalized; it has the smallest exponent but a non-zero significand. Normal processing continues if this exception is masked off.
Inexact Result: The true result is not exactly representable in the specified format, the result is rounded
according to the rounding mode, and this flag is set.
If this exception is masked, processing will simply
continue.
If the error is not masked, the corresponding error
bi! and the error status bit (ES) in the control word
will be set, and the ERROR output signal will be
asserted. If the CPU attempts to execute another
ESC or WAIT instruction, exception 7 will occur.
The error condition must be resolved via an interrupt service routine. The 80287 saves the address
of the floating point instruction causing the error
as well as the address of the lowest memory location of any memory operand required by that
instruction.

iAPX 86/20 COMPATIBILITY:
iAPX 286/20 supports portability of iAPX 86/20
programs when it is in the real address mode.
However, because of differences in the numeric
error handing techniques, error handling routines
may need to be changed. The differences between
an iAPX 286/20 and iAPX 86/20 are:
1. The NPX error signal does not pass through an
interrupt controller (8087 INT signal does).

4-67

Therefore, any interrupt controller oriented instructions for the iAPX 86/20 may have to be
deleted.
2. Interrupt vector 16 must point at the numeric
error handler routine.
3. The saved floating point instruction address in
the 80287 includes any leading prefixes before
the ESCAPE opcode. The corresponding saved
address of the 8087 does not include leading
prefixes.
4. In protected mode, the format of the saved instruction and operand pointers is different than
for the 8087. The instruction opcode is not
saved-it must be read from memory if needed.
5. Interrupt 7 will occur when executing ESC instructions with eitherTS or EM of MSW=1.lfTS
of MSW=1 then WAIT will also cause interrupt
7. An interrupt handler should be added to handle this situation.
6. Interrupt 9 will occur if the second or subsequent words of a floating point operand fall
outside a segment's size. Interrupt 13 will occur
if the starting address of a numeric operand
falls outside a segment's size. An interrupt
handler should be added to report these programming errors.
In the protected mode, iAPX 86/20 application
code can be directly ported via recompilation if the
286 memory protection rules are not violated.

210920-003

80287

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .. O·C to 70·C
Storage Temperature ........ -65·C to +150·C
Voltage on Any Pin with
Respect to Ground ............... -1.0 to +7V
Power Dissipation .................... 3.0 Watt

·NOT/CE: Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended petiods may affect device
reliability.

D.C. CHARACTERISTICS TA = O°C to 70°C, Vee = 5V, +1-5%
5 MHz
Symbol

Parameter

-3 Min

-3 max

Unit

V1l

Input lOW Voltage

-.5

.8

V

VIH

Input HIGH Voltage

2.0

Vcc +.5

V

VllC

Clock Input lOW Voltage
CKM=1:
CKM=O:

-.5
-.5

.8
.6

V
V

VIHC

Clock Input HIGH Voltage
CKM=1:
CKM=O:

2.0
3.8

Vee + 1
Vcc +1

V
V

Test Conditions
0

VOL

Output lOW Voltage

VOH

Output HIGH Voltage

III

Input leakage Current

ILO

,

.45

V

IOL =3.0 rnA

V

IOH = -400 iJ,A

±10

,.,.A

OV ::sV1N ::sVcc

Output leakage Current

±10

iJ,A

.45V ::s VOUT ::s Vee

Icc

Power Supply Current

600

rnA

CIN

Input Capacitance

10

pF

Fc= 1 MHz

Co

InpuVOutput Capacitance
(00-015)

20

pF

Fc= 1 MHz

CCLK

ClK Capacitance

12

pF

Fc= 1 MHz

2.4

4-68.

210920-003

80287

A.C. CHARACTERISTICS (TA = O°C to 70°C, Vee + 5V,=/-5%)
TIMING REQUIREMENTS
A.C. timings are referenced to O.BV and 2.0V points on signals unless otherwise noted.
5 MHz

Symbol

Parameter

·3 Min

8 MHz

-3 max

Min

max

Unit

Test Conditions

TCLCL

ClK Period
CKM=l:
CKM=O:

200
62.5

500
166

125
62.5

500
166

ns
ns

TCLCH

ClKlOWTime
CKM=l:
CKM=O:

118
15

343
146

68
15

343
146

ns
ns

At 0.8V
AtO.6V

TCHCL

ClK HIGH Time
CKM=l:
CKM=O:

69
20

230
151

43
20

230
151

ns
ns

At2.0V
At3.8V

TCH1CH2

ClK Rise Time

10

10

ns

1.0V to 3.6V if CKM = 1

TCL2CL1

ClK Fall Time

10

10

ns

3.6V to 1.0V If CKM = 1

TOVWH

Data Setup to iii'PWfi Inactive

75

75

ns

TWHOX

Data Hold from ~ Inactive

30

15

ns

TWLWH'
TRLRH

JiIPWR, 'fiII5R[j Active Time.

95

90

ns

TAVRL ,
TAVWL

Command Valid to ~ or
'fiII5R[j Active

0

0

ns

TMHRL

Minimum Delay from PEREQ
Active to 'fiII5R[j Active

130

130

ns

TKLKH

J5EACK Active Time

TKHKL

~ Inactive Time

TKHCH

~ Inactive to ~, 'fiII5R[j

TCHKL

'NPWR, 'fiII5R[j Inactive to ~

TWHAX ,
TRHAX

Command Hold from ~,
'fiII5R[j Inactive

TKLCL

J5EACK Active Setup to

T2CLCL

ClK286 Period

Inactive
Active

'fiII5R[j Active

~,

AtO.8V

85

85

ns

At 0.8V

250

250

ns

At2.0V

50

40

ns

·30

-30

ns

30

30

ns

50

40

ns

62.5

62.5

ns
At 0.8V
At 2.0V

T2CLCH

ClK286 lOW Time

15

15

ns

T2CHCL

ClK286 HIGH Time

20

20

ns

T2SVCL

SO, 'Sl Setup Time to ClK286

22

22

ns

T2CLSH

SO, 'Sl Hold Time from CLK286

0

0

ns

4-69

210920·003

80287

A.C. CHARACTERISTICS, continued
TIMING REQUIREMENTS

8 MHz

5 MHz
Sym

Parameter

. -3 Min -3 Max

TCIVCL COO/INTA Setup Time to ClK286

0

TCLCIH COO/INTA Hold Time from ClK286

,

Min

Max

Unit Test Conditions

0

ns

0

0

ns

38.5

38.5

ns

T RVCL

REAOY Setup Time to ClK286

TCLRH

REAOY Hold Time from ClK286

25

25

ns

T HVCL

HlOA Setup Time to ClK286

0

0

ns

TCLHH

HlOA Hold Time from ClK286

0

0

ns

T 1vCL

NPWR, NPRO to ClK Setup Time

70

70

ns

NOTE 1

TCLIH

NPWR, NPRO from ClK Hold Time

45

45

ns

NOTE 1

T RSCL

RESET to ClK Setup Time

.20

20

ns

NOTE 1

T CLRS

RESET from ClK Hold Time

20

20

ns

NOTE 1

A.C. CHARACTERISTICS,
TIMING RESPONSES
5MHz
Sym

Parameter

-3 Min -3 Max

T RHQZ

NPRO Inactive to Oata Float

T RLQV

NPRO Active to Oata Valid

TILBH

ERROR Active to BUSY Inactive

T wLBV

NPWR Active to BUSY Active

100

TKLML

PEACK Active to PEREQ Inactive

127

TCMDI

Command Inactive Time
Write-to-Write
Read-to-Read
Write-to-Read
Read-to-Write

TRHQH

Data Hold from NPRO Inactive

8MHz
Min

Max

Unit Test Condition

37.5

35

ns

NOTE 2

60

60

ns

NOTE 3

ns

NOTE 4

100

ns

NOTE 5

127

ns

NOTE 6

100

100

2.0V
2.0V
2.0V
2.0V

95
250
·105
95

95
325
95
95

ns
ns
ns
ns

At
At
At
At

5

5

ns

NOTE 7

NOTES:
1. This is an asynchronous input This specification is given for testing purposes only, to assure
recognition at a specific ClK edge.
2. Float condition occurs when output current is less than ILO on 00-015.
3. 00-015 loading: Cl = 100pF
4. BUSY loading: Cl =100pF
5. BUSY loading: Cl = 100pF
6. On last data transfer of numeric instruction.
4. 00-015 loading: Cl = 100pF
4-70
210920-003

80287

4.0V
2.4V

CKM =0
CKM =1
0.4SV CKM = 0
0.2V CKM = 1

NOTE 8:

4.0V
2.4V

CKM=O
CKM = 1

0.4SV
O.45V

CKM =0
CKM = 1

AC Drive and Measurement Points - ClK Input

3.6V CKM = 0
2.0V CKM = 1

ClK
INPUT

CKM=O
CKM =1

1.0V CKM =0
0.8V CKM = 1

tHOLO

OTHER
DEVICE
INPUT

2'4VmFT~m
2.0V

tOELAY

----I

2.0V
DEVICE
OUTPUT
O.8V

NOTE 9:

AC Setup. Hold and Delay Time Measurement - General
DEVICE
OUTPUT

NOTE 10:

AC Test loading on Outputs

4-71

210920-003

inter

80287

WAVEFORMS I(cont.)
DATA TRANSFER TIMING (INmATED BY 80286)

)

CMDO CMD1
Nm,NPS2

_TRLRH
NPRD

l(
..

VALID

~~VRL;
_

,v

--

ILL-'Y

I

1\

DATA OUT
VALID
\.\.\.\.
TAVWL'_ _ TWLW_ ..

1/

..

\

-

-,

BUSY

-

)

-

TWHAX -

I{

DATA IN
VALID

=~

DATA
TRANSFER
FROM
80287

I

DATA
TRANSFER
TO
80287

TWHDX

TDVWH

DATA MAY CHANGE

)

-

TRHQZ_
_TRHQH_

I-

TRLQV

TRHAX

DATA MAY CHANGE

~J---

TWLBN

--4--

DATA CHANNEL TIMING (INITIATED BY 80287)

C~CMD1---1~
NI':;l,NPS2

---l

J---J--.:r

TAVWL
TAVRL

'\

\

_TMHRL

PEACK

-,t TRHAX
TWHAX

..

_TCLML_

-

TKLCL_

_---I

-

VALID

~ r-

-

..
------------i
S...

TKLML_'

TKLKH

4-72

TCMDI_

_TCHKL_

..

TKHCH

__ TKHKL ___

--- }f-

~

"--

210920-003

80287

WAVEFORMS (cont.)
ERROR OUTPUT TIMING

BUSy _ _ _ _,
ERROR

r"'~d'
~

80286 STATUS TIMING

..

NOTES:
1. This input transition occu rs before T5.
2. This input transition occurs after Te.

4-73

210920-003

80287

WAVEFORMS

(Reset, iiiPWR, NPiIDare inpulsasynchronoustoCLk TIming requlremenlsonthispage
are given fortesting purposes only, to assure recognition at a specific ClK edge.)

ClK, RESET TIMING (CKM
f/J 1

f/J 2

f/J 1

=1)
f/J 2

\.

ClK
(IFCKM =1)

~

TOC," _ _•

TNCO.,.

RESET

ClK, NPRD, NPWR TIMING (CKM
1/)2

1/)1

~

ClK
(IFCKM =1)

NPRD,
NPWR

I

1/)1

f/J 2

- T~" ~!TNCO.-

~

\\\\\\\\\
ClK, RESET TIMING (CKM

RESET

=1)

=0)

d::--------1!

NOTE: Reset must meet timing shown to guarantee known phase of internal..;- 3 circuit

CLK, NPRD, NPWR TIMING (CKM = 0)

I

\\\\\\\\\\\
4-74

210920-003

80287

Table 6. 80287 Extensions to the 80286 Instruction Set

I

Data Transfer

Optional
8,16 Bit
Displacement

32 Bit
Real

Clock Count Range
32 Bit
64 Bit
Integer
Real

16 Bit
Integer

I
FLO

LOAD

~

1 MF

1_

Integer/Real Memory to ST(O)

1 ESCAPE

Long Integer Memory to ST(O)

LIE_S_C_A_P_E__
l _ l _l--LI_M_O_D_l__
0_1_R_/M---..J[

Temporary Real Memory to

I ESCAPE

0

1

1 I MOD

1 0

1

R/M

BCD Memory to ST(O)

1 ESCAPE

1

1

1 1 MOD

1 0

0

R/M [

ST(I) to ST(O)

1 ESCAPE

0

0

1 1 1

1

0

0

0

ST(ll

1 1 MOD

0

1 0

1 1 MOD

MF

0 0

0

R/M

ST(O)

FST

ST(O) to ST(I)

~

10

11

38-56

52-60

40-60

46-54

96-104

80-90

98-106

82-92

65-75

72-86

67-77

74-88

60-68

r

53-65

~ ~ ~I~P ~

J

290-310
17-22

1

1 ESCAPE MF
I ESCAPE

1 0

1

1 1 1

0

1

R/M 1- = =

~I~P=

-:

~

84-90

82-92

15-22

STORE AND POP

ST(O) to Integer/Real Memory
ST(O) to Long Integer Memory
ST(O) to Temporary Real
Memory
ST(O) to BCD Memory
ST(O) to STi'l

FXCH
ST(O)

01

STORE

~

ST(O) to Integer/Real Memory

FSTP

==

00

Exchange ST(I) and

~

~IE=S=C=A=P=E==M=F==I~I=M=O=D=O==I=I=R=/=M~I:_ ~ ~ ~I~P ~ J
LIE_S_C_A_P_E__
l_1_'I--LI_M_O_D_l__
1_1_R_/M--lI_

~ ~ ~I~P ~

J

J
~ ~ '~I~ ~ 1

E=S=C=A=P=E===O==I==I==I==M=O=D==I===I==I==R=/M=:::1~ ~ ~ ~I~~

=1

1 ESCAPE 1 1 1 1 MOD 1 1 0 R/M 1_

~======~=======:

1ESCAPE

1 0

1 1 1

1

0

1

1

ST(I) 1

I ESCAPE

0

1 I 1

1

0

0

1

ST(i)

0

86-92

84-94

94-105
52-58
520-540
17-24

I

10-15

Comparison
FCOM

~

Compare

l_0_~_M~I_- ~ ~

Integer/Real Memory to ST(O)

LIE_S_C_A_P_E__
M_F__0--,I_M_O_D_0__

ST(i) to ST (0)

I ESCAPE

FCOMP

~

0

0

0 I 1 1

0

1 0

:=1E=S=C=A=P=E==M=F==0=tI=M=O=D=O==1=1=R=/M===lI_
1 ESCAPE

0

0

0 1 1

1

0

1

1

FCOMPP ~ Compare ST(I) to
ST(O) and Pop TWice

I ESCAPE

1

1 0 I 1

1

0

1

1 0

FTST

I ESCAPE

0

0

1 I 1

1

1 0

I ESCAPE

0

0

1 I 1

1

1 0

~

78-91

Compare and Pop

Integer/Real Memory to ST(O)

FXAM

60-70

40-50

STi'l I

ST(I) to ST(O)

~

DISP

Test ST(O)
Examine ST(O)

STi'l

~I~P==:

63-73

80-93

1

45-52

0

1

I

45-55

0

1 0

0

I

38-48

0

1 0

1

I

12-23

Mnemonlcs@lnteI1982

4-75

210920-003

80287

Tab,le 6. 80287 Extensions to the 80286 Instruction Set (cont.)

I
Constants

I MF
~

LOAD + 0 0 Into ST(O)

I ESCAPE

0

FLD1

~

LOAD + 1 0 Into ST(O)

I ESCAPE

0 0

1

I

0 0

1

~

LOAD" into ST(O)

FLDL2T
ST(O)

~

LOAD log2 10 Into

FLDL2E
ST(O)

~

LOAD log2 e Into

FLDLG2
ST(O)

~

LOAD log, 0 2 Into

FLDLN2
ST(O)

~

LOAD 10ge2 Into

'ESCAPE

0 1

I ESCAPE
I ESCAPE

0

0 1

0

0

I ESCAPE
I ESCAPE

0

0 1

0

0

I ESCAPE
I ESCAF!E

MF

1

1

I1

1

1 0

1

I1
I1
I1
I1

1

1 0

1 0 0

1

1 0

1 0

1 1

1

1 0

1 0

0

1

1 0 1 0

1

1 0

1

1 0 0

1 1

1 0

1

1 0

I MOD

0 0

0

RIM

I

0 0

0

ST(i)

I
I

1

32 Bit
Real

Clock Count Range
32 Bit
64 Bit
Integer
Real

00

~

FLDZ

FLDPI

Optional
8,16 Bit
Displacement

1 1 0

0

1

1 0

1

01

I

11-17

I
I
I
I

15-21

10

16 Bit
Integer

11

16-22
16-22
15-21

I
I

18-24
17-23

Arithmetic
FADD

~

Aadition

IntegerlReal Memory with ST(O)
ST(i) and ST(O)

FSUB

~

ST(i) and ST(O)

~

P 0

DISP

I ESCAPE
I ESCAPE

MF
d

0
P 0

ST(i) and ST(O)
FDIV ~ Division
IntegerlReal Memory with ST(O)
ST(I) and ST(O)

FSQRT ~ Square Root of ST(O)

1

ESCAPE

MF

I ESCAPE

d

I

MF

ESCAPE

I ESCAPE

d

0
P 0

0
P 0

ESCAPE

0 0

1

Scale ST(O) by ST(I)

I ESCAPE

0 0

1

FPREM ~ Partial Remainder of
ST(O) -ST(l)

I ESCAPE

0 0

1

I ESCAPE

0

~

FRNDINT
Integer

~

Round ST(O) to

1

0 1

1

MOD 0

It

I

I
I
1

I
I

I

1 RIM

1-

1 RIM

I

0

0

MOD

1

1 R RIM

1

1 1 1

1

1

1

1 1 0

1 1

1

1 1

1 1

1 1

1

1 1 1

1

-

-I

-,- ....

-'

- -

DISP

90-120 108-143 95-125

110-125 130-144 112-168 124-138

,

-

215-225 230-243 220-230

I

193-203 (Note 1)

I

180-186

1 0

1

I

32-38

1 0 0

0

I

15-190

0

I

16-50

1 0

102-137

90-145 (Note 1)

--

1 0

102-137

70-100 (Note 1)

-,
[ -DISP
- - -'

R RIM

90-120 108-143 95-125
70-100 (Note 1)

-DISP
- - -,_,

0

1

I

-'

L- - -

I MOD 1 0 R RIM
I 1 1 1 0 R RIM

Multiplication

IntegerlReal Memory with ST(O)

FSCALE

1 1

- - -

[ - -I

Subtraction

IntegerlReal Memory with ST(O)

FMUL

d

0

224-238

NOTE:
1. If P= 1 then add 5 clocks.

4-76

210920-003

80287

Table 6. 80287 Extensions to the 80286 Instruction Set (cont.)
Optional
8,16 Bit
Displacement

FXTRACT ~ Extract
Components of St(O)

ESCAPE

FABS
ST(O)

=

Absolute Value of

FCHS

~

Change Sign of ST(O)

0

0

1

1

1

1

ESCAPE

o

1

1

1

1 0

ESCAPE

o

1

1

1

0

1

1

1

1

1

Clock Count Range

1

0

0

27-55

0

0

0

1

10-17

0

0

0

0

0

1

0

30-540

1

1

250-800

1 0

10-17

Transcendental
FPTAN

Partial Tangent of

'='

ESCAPE

0

1

1

ST(O)
FPATAN ~ Partral Arctangent
of ST(O) -ST(1)

ESCAPE

o

1

F2XMl ~ 2 STlOI _l

ESCAPE

o

1

0

1

FYL2X
[ST(O))

~

ST(l)' Log2

ESCAPE

0

ESCAPE

0 0

ESCAPE

0

Enter Protected

ESCAPE

0

~

ESCAPE

1

ESCAPE

o

FYL2XPl ~ ST(l)' Log2
[ST(O) +11

o
o

1

1

1

1

1

1

0

310-630
0

0

900-1100

1

700-1000

Processor Control
FINIT

Initialize NPX

~

~

FSETPM
Mode

FSTSW AX
Word

Store

Contr~1

o
1

1

1

2-8

o

2-8

o

1

o

0

FLDCW

~

Load Control Word

FSTCW

~

Store Control Word

L-E_S_C_A_P_E_ _O_--'L-M_O_D
_____

FSTSW

~

Store Status Word

L-E_S_C_A_P_E_ _0__1_---'-_M_O_D_ _ _ _

FCLEX

~

Clear Exceptions

FSTENV

FLDENV
FSAVE

~

FRSTOR

~

Store Environment

~

Load Environment

Save State
~

FINCSTP
Pomter
FDECSTP
Pomter

Restore State

~

~

RIM

DISP

:

R_I_M~ _ ~ ~I~~ ~ ~:

R~ _ ~ ~I~~ ~

ESCAPE

0

1

LESCAPE
-_ _ _ _ _ _ _ _ _ _

°

1

~

1

o

°

1

J

°

MOD
_
_ _ _ _ _ _ _ _ _RIM
____

~

DISP

35-45

'--E_S_C_A_P_E_ _O
_ _'--M_O_D_ _O_O__
R/_M_----'I_

ESCAPE

0

0

6
1

1

1

0

4-77

12-18

40-50

:

..JI- - Disp -:

°°

12-18

DISP
___
___ _:

L-E_S_C_A_P_E_ _O
_ _L-M_O_D_ _ _O
__
R/_M_ _

ESCAPE

7-14

2-8

li_S_C_A_P_E_O_O_ _L-M_O_D
_ _ _ _O_R_I_M_-----'

Increment Stack

Decrement Stack

MOD

10-16

~ ~~~ =J

205-215
205-215

6-12
1

1

0

6-12

210920-003

80287

Table 6. 80287 Extensions to the 80286 Instruction Set (cont.)
Clock Count Range
FFREE
FNOP

= Free ST(i)

= No Operation

NOTES:
1. if mod=OO then
if mod=Ol then
if mod=10 then
if mod=ll then
2. if r/m=OOO then
if r/m=OOl then
if r/m=010 then
if r/m=Oll then
if r/m=100 then
if r/m=101 then
if r/m=110 then
if r/m=lll then

ESCAPE

1 0 1

ESCAPE

0 0

1

I1
I1

1

0 0

1

0

0

1 0

ST(I)

9-16

0 0 0

10-16 '

DISP=O', disp-Iow and disp-high are absent
DISP=disp-low sign-extended to 16-bits, disp-high is absent
DISP=disp-high; disp-Iow
rim is treated as an ST(i) field
EA=(BX) + (51) +DISP
EA=(BX) + (01) +DISP
EA=(BP) + (51) +DISP
EA=(BP) + (01) +DISP
EA=(SI) + DISP
EA=(DI) + DISP
EA=(BP) + DISP
EA=(BX) + DISP

'except if mod=OOO and r/m=110 then EA =disp-high; disp-Iow.
3. MF= Memory Format
00-32-bit Real
01-32-bit Integer
10-64-bit Real
11-16-bit Integer
4. ST(O) = Current stack top
ST(i)
ith register below stack top
5. d= Destination
O-Destination is ST(O)
I-Destination is ST(i)
6. P= Pop
O-No pop
I-POP ST(O)
7. R= Reverse: When d",l reverse the sense of R
" O-Destination (op) Source
I-Source (op) Destination
8.
For FSQRT:
-0 .;; ST(O) .;; +00
For FSCALE:
_215 .;; ST(l) < +215 and ST(l) integer
For F2XM1:
0.;; ST(O).;; 2- 1
0 < ST(O) <00
For FYL2X:
-00 < ST(l) < + 00
For FYL2XP1:
0.;; IST(O)I < (2 -\1'2)/2
-00 < ST(l) < 00
For FPTAN:
0.;; ST(O) ';;1T/4
For FPATAN:
0.;; ST(O) < ST(l) < +00
9. ESCAPE bit pattern is 11011.

4-78

210920-003

June 1984

82258
Advanced DMA Controller
Architectural Overview

@INTEL CORPORATION. 1984

4-79

Order Number: 230606-002

82258 OVERVIEW

INTRODUCTION
As the processing of microprocessor based systems grows,
it is increasingly necessary to have support components
which relieve the processor from jobs like data movement,
peripheral control, etc., and leave it to do what it can do
best-data processing. Among the support components
necessary is a DMA (Direct Memory Access) controller.
A DMA controller must match the performance and architectural needs of the processor it supports to optimize the
performance.
The 82258 is a 16-bit DMA controller designed primarily
to meet the needs of systems based on the 80286 and 80186
processors. The 80286 is the fastest 16-bit processor available commercially with more than five times the throughput of the standard 8086. The 80186, on the other hand,
integrates the functions of a CPU board (CPU, Clock,
DMA, Interrupt Control, Timer Counter, Chip Select) on
one chip, replacing 15-20 IC's. The 82258 is designed to
support this level of performance and integration by offering features generally found only in mainframe computer
systems.

FEATURES
• 8 MBytes/ second transfer rate in 8 MHz iAPX 286
Systems
• 4 independent channels-each channel having its
own set of registers and control lines
• Multiplexor channel operation for up to 32 I/O
subchannels
• 16 MByte physical addressing range
• Block size (byte count) up to 16 MBytes
• Command chaining
• Data chaining
• Adaptive bus interface for
- 80286
- 80186
- 80188
-8086
- 8088 processors

• Automatic assembly-disassembly for dissimilar bus
widths
• "On the fly" compare, verify and trdnsiate operations
duringDMA
• Single and double bus cycle transfers
• Local (with CPU) and remote (stand-alone) modes
of operation

FLEXIBLE BUS INTERFACE
Although the 82258 is primarily designed for the 80286,
it fits equally well in 8086, 8088, 80188, and 80186 based
systems. This is possible because of its adaptive bus interface. The logic level on a specific pin on RESET configures
the bus interface of the 82258 for the 80286 (demultiplexed)
bus, or for the 80186 or minimum mode' 8086 (multiplexed)"bus, with all the necessary signals and timing. In
the 8086 mode, the 82258 can have RQ/ GT signals for the
maximum mode 8086 or 8088. This adaptive bus interface
makes it very easy to use the 82258 in different processor
systems. It is possible to select 8- or l6-bit wide bus
operations by software. Figure I shows the pin configuration of the 82258 in the 286 and 186 modes.
The high performance (8 MB/sec) pipelined bus of the 286
allows the 82258 to provide maximum performance. This
bus enables the 80286 and the 82258 to read or write a word
(16 bits) in 250 ns, when operating at 8 MHz. Therefore,
in the 286 mode, the 82258 can achieve data transfer rates
of 8 MBytes/ second. In the 186 and 8086 mode, the data
transfer rate is4 MBytes/ second, since each buscycJe is4
clocks or 500 ns at 8 MHz.
The 82258 has four (4) independent channels. Each channel has three (3) dedicated pins; DREQ (DMA request),
DACK (DMA acknowledge) and EOD (End ofDMA). See
Figure 2. A peripheral generates request for DMA over the
DREQ line. DACK is sent by the 82258 to the peripheral,
indicating that a data transfer operation can begin. EOD
is used by the 82258 to generate an interrupt on the completion of a DMA operation. The EOD line can also be
used by a peripheral to terminate the DMA.

4-80

230606-002

82258 OVERVIEW

HOLD

HOLD

HLDA

HLDA

A19/86

CLK
A?3

A16/S3
A!5

RESET

Ail

CLK

Ail

A?

RESET

A7

Ail

DREQ 3
DREQ 0

A~15

DREQ 0

DO

DA~K 3

BHE

82258
(IN 286 MODE)

Ad

DR~Q 3

D15

M/iO

DACK 0

S1
SO

EO~ 3

READY

EODO

82258
(IN 186 MODE)

<==>

ADO
BHE

S2
Sf
SO
SREADY
AREADY
ALE
DT/A

CS
AD

i5Ef.I

WR
RD
WR

Vas Vas Vee Vee
Vas Vas Vee Vee

Figure 1. 82258

82258
CH.O

------------------CH.1

DREQ
PERIPHERAL
CONTROLLER

•

~

CH.2

DACK

<

EOD

INTERRUPT
CONTROLLER

CH.3

~

:,

8259A

•

~

•

,

i'-

'IIi ~
BUS

>

Figure 2. Each Channel with 3 line Interface

4-81

230606-002

82258 OVERVIEW

MULTIPLEXOR CHANNEL
b) Block Multiplex Operation: Here the channel IS
enabled for another device only after transfer of complete
data block. The actual block transfer is carried out at a
rate of 4M Byte/sec (maximum).

For supporting a large number of relatively slow equipment (e.g. 9600 baud) like CRT terminals and line printers
etc., channel 3 of the 82258 can be programmed to be a
multiplexor channel. In this mode channel 3 can service
up to 32 subchannel request lines. The multiplexor network is implemented using 8259A interrupt controllers.
The multiplexor channel has two modes of operation:

Each individual device can be programmed into its own
operating mode so various combinations of bytejword
and block mUltiplex are possible. Each device on the
multiplexor channel has its own program. Command
chaining is supported on the multiplexor channel. Single
cycle transfers are not allowed on the multiplexor
channel.

a) Byte or Word Multiplex Operation: In this case the
channel is enabled for another device after each byte or
word transfer. The maximum cumulative data rate for
multiplexor channel in this mode is approximately 275 K
byte per second.

< >

CH.O
HOLD
HLDA

CH.1

T

0
82258

•
•
•
UPTO
32 REQUEST
LINES

CH.2

C
P
U

IOREQ
MULTIPLEXOR

IOACK

CH.3

MULTIPLEXOR CONSISTS OF ONE
OR MORE 8259A
(INTERRUPT CONTROLLER)

Figure 3. Multiplexor Channel Configuration

4-82

230606-002

intel"

82258 OVERVIEW

TRANSFER IN 1 OR 2 BUS CYCLES
The 82258 is capable of doing single cycle and two cycle
data transfers. See Figure 4. In a single cycle transfer, the
data is transferred between a peripheral and memory (in
either direction) in a single bus cycle. Single cycle transfers
provide the maximum DMA throughput. In a two cycle
operation, the data is read by the 82258 using a normal bus
operation before sending it out to the destination using a
normal bus operation.
The 82258 can do "on the fly" operations like translate and
compare during a two cycle transfer. The data being transrerred can be compared with a given pattern (mask-compare)
and the DMA transfer can be optionally stopped on encountering that pattern. The 82258 supports this mask-compare
operation on 8- and 16-bit patterns. The data can also be
, translated on the fly before sending it to the destination.
Data can be transferred from one memory region to another
in a two cycle transfer mode-this is not possible with single
cycle transfer. Another feature of two cycle transfer is
automatic assembly/ disassem\lly of data. This means that
data can be read as one word (16 bits) and written as

•

two bytes or vice versa. Automatic assembly/disassembly
is very often desirable when using 8-bit wide peripherals
in a 16-bit system. When writing data to the 8-bit peripheral from memory, data could be retched as a 16-bit word
and written out as two 8-bit bytes. The reverse is true for
reading data out of an 8-bit peripheral. This feature saves
time and reduces the number of bus cycles to transfer a
given block of data.

FAST CHANNEL SWITCHING
For high speed DMA controllers with multiple channels,
it is very important to minimize overhead for switching from
one channel to another. The 82258 imposes no performance
penalty for switching channels. Therefore, the maximum
cumulative transfer rate of an 82258 is 8 MBytes/ second
even if multiple channels are used. The priority of different channels can be programmed to be fixed or
rotating. It is also possible to have a combination of the
two, i.e., channels 0 and I, having higher priority than
channels 2 and 3, and rotating priority within each pair.
The channel with the highest priority gets processed first
when multiple channels have to be serviced at the same
time .

SINGLE

MEMORY

PERIPHERAL

ADVANTAGE:
"SPEED1 BUS CYCLEITRANSFER

82258

•

DOUBLE

MEMORY

PERIPHERAL
ADVANTAGE:
"'ON THE FLY"
• MASK/COMPARE
• TRANSLATE
• VERIFY
"MEM. TO MEM.
TRANSFERS
"DISSIMILAR BUS
WIDTH SUPPORT

82258

Figure 4. Single/double cycle transfer

4-83

230606-002

82258 OVERVIEW

are used to specify the bus load which is permissible for
the 82258.

16 MBYTE ADDRESSING
Being the D MA controller for the 80286, the 82258 supports an address range of 16 MBytes in memory and I/O
space. Thus, the source and destination pointers for a
DMA are each twenty-four bits long. The 82258 can
transfer data blocks as big as 16 M Bytes. That is, the byte
count for the transfet is also twenty-four bits long.

MEMORY BASED COMMANDS
The 82258 and the CPU communicate via memory based
commands. All relevant data (parameters) for DMA
transfer is written by the CPU in a "cOJ;nmand block" in
memory which is accessible to the CPU and the 82258. See
Figure 6. the command pointer on the 82258 is loaded
with the based address of the command block by the CPU.
After getting a start channel command from the CPU, the
82258 loads the contents of the command block into its
registers and starts the D MA. After completing operation
on Ii command block, the 82258 writes back the channel
status in the command block in memory. Optionally,
source pointer, destination pointer and byte counter
register may also be written out to the command block.
Although all channel registers are user accessible, they
need to be directly accessed only for diagnostic purposes.

Figure 5 shows the user visible registers of the 82258. A set
of five registers, called the General Registers, is used for
all four channels. There is a set of channel registers for
each of the four channels. The mode register is written
first after reset and describes the 82258 environment-bus
widths, priorities, etc. The General Command Register
(GCR) is used to start and stop the DMA transfer on different channels. The General Status Register (GSR)
shows the status of all four channels: i.e., if the channel is
running, if an interrupt is pending, etc. The General Burst
Register (GBR) and the General Delay Register (GDR)

o

15
GCR

COMMAND

GSR

STATUS
MODE

GMR
GBR
GDR

l
l

BURST
DELAY

o

7

GENERAL REGISTERS

CHANNEL REGISTERS (4 SETS: 1 PER CHANNEL)

o

23
CPR

COMMAND POINTER

SPR

SOURCE POINTER

DPR
TTPR

DESTINTATION POINTER
TRANSLATE TABLE POINTER
LIST POINTER

LPR
BCR

BYTE COUNT

CCR

CHANNEL COMMAND
MASKR

MASK

COMPR

COMPARE

,

ASSEMBLY

DAR

15

CSR

L

CHANNEL STATUS

7

o

Figure 5. 82258 Register Set

4-84

230606-002

inter

82258 OVERVIEW

ON
CHIP

h3

COMMAND POINTER

0

)
IN MEMORY

T

15

lII:

TYPE 1 COMMAND

0

SOURCE POINTER

u

9

-0-

ID
Q

Z
CC
::&
::&

I

DESTINATION POINTER

-0-

0

u

Ii:0

I
BYTE C,OUNT

:I:

-0-

UI

t

I

CHANNEL STATUS
COMMAND EXTENSION

0

iii
z

MASK

t

f---

III

~

~
~

COMMAND

....

82288

HOLD HOLDA
MilO
SO_1
ADDR. r

:i!
w
III

>
III

ADDRESS
8283

7

>

24
82258

l-

DACK 0-3 (
DATA
DREQ 0-3

DATA

8287

}

16

Figure 12. 82258 in 80286 SY8tem

4-90

230606-002

inter

82258 OVERVIEW

-'
.A.

<

,

RESIDENT BUS

"I i'
'<

r--

~

BUS
INTERfACE

,

~
DREQ

~
82258

~

~ ADDRESS
DATA
STATUS

A

BUS
INTERfACE

v

......
-..

r

::;)

::E
w

...

0-3

Ul

DACK

0-3

Ul

ID

>-

J

.A.
~

ADDR.
SELECT

PROCESSOR
BOARD

Ul

I

f

A.

......

v

--y

~

Figure 13. 82258 In Remote or Stand-Alone Configuration

4-91

230606-002

82284
CLOCK GENERATOR AND READY INTERFACE
FOR iAPX 286 PROCESSORS
(82284, 82284-6)

• Generates System Clock for iAPX 286
Processors

• 18-pin Package
• Single

• Uses Crystal or TTL Signal for Frequency
Source

+ 5V Power Supply

• Generates System Reset Output from
Schmitt Trigger Input

• Provides Local READY and Multibus*
READY Synchronization

• Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range

The 82284 is a clock generator/driver which proviQes clock signals for iAPX 286 processors and support components. It also contains logic to supply READY to the CPU from either asynchronous or synchronous sources and
synchronous RESET from an asynchronous input with hysteresis.

RESET

fJ

RESET

SYNCHRONIZER

x1_1--r=-l
X2

1IL=-J

ClK

EFI--t-------'

FIC
ARDYEN
ARDY

-+----------'
-+---<>1'"""'\
-t--d...J

SRDYEN -+-~~
SRDY

-t---d...J

S1

-+--<11"-'"

VCC

2

3
4

5

82284

6
7
8

9

ARDYEN
S1
SO
N.C.
PClK
RESET
RES
ClK

READY

so -+--<:11._

Figure 1.

ARDY
SRDY
SRDYEN
READY
EFI
F/C
X1
X2
GND

PClK

Figure 2.
82284 Pin Configuration

82284 Block Diagram

* Multibus is a patented bus of Intel
Intel Corporation Assumes No Responsibility for the Wae of Any Circuitry Other Than CircUItry Embodied In an Intel Product No Other ClrCUlt Patent Licenses are Imphed
OJ

INTEL CORPORATION 1982

4-92

January 1985
ORDER NUMBER' 210453-003

82284

Table 1. Pin Description
The following pin function descriptions are for the 82284 clock generator.
Type

Name and Function

ClK

a

System Clock is the signal used by the processor and support devices which must be synchronous with the processor. The frequency of the ClK output has twice the desired internal processor clock frequency. ClK can drive both TTL and MaS level inputs.

F/C

I

X1, X2

I

EFI

I

PClK

a

ARDYEN

I

ARDY

I

Asynchronous Ready is an active lOW input used to terminate the current bus cycle. The
ARDY input is qualified by ARDYEN. Inputs to ARDY may be applied asynchronously to ClK.
Setup and hold times are given to assure aguaranteed response to synchronous inputs.

SRDYEN

I

Synchronous Ready Enable is an active lOW input which qualifies SRDY. SRDYEN selects
SRDY as the source for READY to the CPU for the current bus cycle. Setup and hold times
must be satisfied for proper operation.

SRDY

I

Synchronous Ready is an active lOW input used to terminate the current bus cycle. The SRDY
Input IS qualified by the SRDYEN input. Setup and hold times must be satisfied for proper operation.

READY

a

Ready IS an active lOW output which ~nals~ current bus cycle is to be completed. The
SRDY, SRDYEN, ARDY, ARDYEN, S1, SO and RES inputs control READY as explained later in
the READY generator section. READY is an open collector output requiring an external 300
ohm pullup resistor.

SO,S1

I

Status inputs prepare the 82284 for a subsequent bus cycle. SO and S1 synchronize PClK to
the internal processor clock and control READY. These inputs have pullup resistors to keep
them HIGH if nothing is driving them. Setup and hold times must be satisfied for proper operation.

RESET

a

Reset is an active HIGH output which is derived from the RES input. RESET is used to force the
system into an initial state. When RESET is active, READY will be active (lOW).

RES

I

Reset In is an active lOW input which generates the system reset signal RESET. Si~s to
RES may be applied asynchronously to ClK. A Schmitt trigger input is provided on RES, so
that an RC circuit can be used to provide a time delay. Setup and hold times are given to assure
a guaranteed response to synchronous inputs.

Symbol

Vee
GND

Fr~quency/Crystal

Select is a strapping option to select the source for th~ ClK output. When
F/C is strapped lOW, the internal crystal oscillator drives ClK. When Fie is strapped HIGH,
the EFI input drives the ClK output.
Crystal In are the pins to which a parallel resonant fundamental mode crystal is attached for
the internal oscillator. When FIG is lOW, the internal oscillator will drive the ClK output at the
crystal frequency. The crystal frequency must be twice the desired internal processor clock
frequency.
External Frequency In drives ClK when the F/C input is strapped HIGH. The EFI input frequency must be twice the desired internal processor clock frequency.
Peripheral Clock is an output which provides a SO% duty cycle clock with 112 the frequency of
ClK. PlCK will be in phase with the internal processor clock following the first bus cycle after
the processor has been reset.
Asynchronous Ready Enable is an active lOW input which qualifies the ARDY input.
ARDYEN selects ARDY as the source of ready for the current bus cycle. Inputs to ARDYEN
may be applied asynchronously to ClK. Setup and hold times are given to assure a guaranteed
response to synchronous Inputs.

System Power: +SV power supply
System Ground: 0 volts

FUNCTIONAL DESCRIPTION

ready synchronization logic and system reset generation logic.

Introduction

Clock Generator _

The 82284 generates the clock, ready, and reset signals required for iAPX 286 processors and support
components. The 82284 is packaged in an 18-pin DIP
and contains a crystal controlled oscillator, MOS
clock generator, peripheral clock generator, Multibus

The elK output provides the basic timing control for
an iAPX 286 system. elK has output characteristics
sufficient to drive MOS devices. elK is generated by
either an internal crystal oscillator or an external
source as selected by the Fie strapping option. When

4-93

210453-003

82284

Ftc is 'lOW, the crystal oscillator drives the ClK out"
put. When Ftc is HIGH, the EFI input drives the ClK
output.
The 82284 provides a second clock output (PClK) for
peripheral devices. PClK is' ClK divided by two.
PClK has a duty cycle of 50% and TTL output drive
characteristics. PClK is normally synchronized to the
internal processor clock.
After reset, the PClK signal may be out of phase with
the internal processor clock. The 'Sf and 'SO signals of
the first bus cycle are used to synchronize PClK to
the internal processor clock. The phase of the PClK
output changes by extending its HIGH time beyond
one system clock (see waveforms). PClK is forced
HIGH whenever either 'SO or Sf were active (lOW) for
the two previous ClK cycles. PClK continues to oscillate when both 'SO and Sf are HIGH.

Reset Operation
The reset logic provides the RESET output to force
the system into a known, initial state. When the RES
input is active (lOW), the RESET output becomes active (HIGH). RES is synchronized internally at the failing edge of ClK before generating the RESET output
(see waveforms). Synchronization of the RES
input introduces a one or two ClK delay before affecting the RESET output.
At power up, a system does not have have a stable Vce
and ClK. To prevent spurious activity, RES should be
asserted until Vcc and ClK stabilize at their operating
values. iAPX 286 processors and support components
also require their 'RESET inputs be HIGH a minimum of
16 C,lK cycles. An RC network, as shown in Figure 4,
will keep RES lOW long' enough to satisfy both needs.

Since the phase of the internal processor clock will
not change except during reset, the phase of PClK
will not change except during the first bus cycle after
reset.

Vee

Oscillator

82284 '

The oscillator circuit of the 82284 is a linear Pierce oscillator which requires an external parallel resonant,
fundamental mode, crystal. The output of the oscillator is internally buffered. The crystal frequency chosen should be twice the required internal processor
clock frequency. The crystal should have a typical
load capacitance of 32 pF.

Figure 4. lYPical RC RES Timing Circuit

X1 and X2 are the oscillator crystal connections. For
stable operation of the oscillator, two loading capacitors
are recommended, as shown in Table 2. The sum of
the board capacitance and loading capacitance should
equal the values shown. It is advisable to limit stray
board capacitances (not including the effect of the
loading capacitors or crystal capacitance) to less than
10 pF between the X1 and X2 pines. Decouple Vee and
GND as close to the 82284 as possible.

A Schmitt trigger input with hysteresis on RES assures a single transition of RESET.with an RC circuit
on RES. The hysteresis separates the' input voltage
level at which the circuit output switches between
HIGH to lOW from the input voltage level at which the
circuit output switches between lOW to HIGH. The
RES HIGH to lOW input transition voltage is lower
than the RES lOW to HIGH input transition voltage.
As long as the slope of the RES input voltage remains
in the same direction (increasing or decreasing)
around the RES input transition voltage, .the RESET
output will make a single transition.

CLK 1-'1.:..0- - I ClK
Vee

D
8 X2
r -........--'i

SEE TABLE
2 FOR

CAIW:ITOR
VALUES

Ready Operation

'9!~OI c~::O~~k

82284
. __ 4

READY

,APX286
CPU or

h,;:
....Il!:R~'i!A~D~Y_.-J I
,18

I

The 82284 accepts two ready sources for the system
ready signal which terminates the current bus cycle.
Either a synchronous (SRDY) or asynchronous ready
(AROY) source may be used. Each ready input has an
enable (SRDYEN and ARDYEN) for selecting the type
of ready source required to terminate the current bus
cycle. An address decoder would normally select one
of the enable inputs ..

DECOUPLING
CAPlACI10R

Figure 3. Recommended Crystal and RElDV
Connections
4-94

210453-003

intJ

82284

READY

is enabled (lOW), if either SRDY +
SRDYEN = 0 or ARDY + ARDYEN = 0 when sampled by the 82284 READY generation logic. READY
will remain active for at least two ClK cycles.

SRDYEN. These inputs are sampled on the falling
edge of ClK when S1 and SO are inactive and PClK is
HIGH. READY is forced active when both SRDY and
SRDYEN are sampled as lOW.

The READY output has an open-collector driver allowing
other ready circuits to be wire or'ed with it, as shown in
Figure 3. The READY signal of an iAPX 286 system
requires an external 910 ohm ± 5% pull-up resistor. To
force the READ? Signal inactive (HIGH) at the start of a
bus cycle, the READY output floats when either S1 or SO
are sampled lOW at the falling edge of ClK. Two system
clock periods are allowed for the pull-up resistor to pull
the READY signal to V1H • When RESET is active, READY
is forced active one ClK later (see waveforms).

Rgure 6 shows the operation of ARDY and ARlJYEiiI.
These inputs are sampled by an internal synchronizer
at each falling edge of ClK. The output ·of the synchronizer is then sampled when PClK is HIGH. If the synchronizer resolved both the ARDY and ARl:i"Yrn have
been resolved as active, the SRDY and SRDYEN inputs
are ignored. Either ARDY or ARDYEN must be HIGH at
end of Ts (see figure 6).
READY remains active until either 51 or SO are sampl~d LOW, or the ready inputs are sampled as inactive.

Figure 5 illustrates the operation of SRDY and

Table 2. 82284 Crystal Loading Capacitance Values
Crystal Frequency

C1 Capacitance
(pin 7)
60 pF
25 pF

1 to 8 MHz
8 to 16MHz

C2 Capacitance
(pin 8)
40 pF
15 pF

NOTE: Capacitance values must include stray board capacitance.

T,
ClK

PClK

READY - - - - -_ _ _,

Figure 5.

Synchronous Ready Operation

4-95

210453-003

82284

Ts

elK

PClK

READY _ _ _ _ _ _ _ _......l....

Figure 6.

Asynchronous Ready Operation

*Notice: Stresses above those listed under "Absolute
Maxmum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS"
Temperature Under Bias ............ ooe to 70 0 e
Storage Temperature .......... -6Soe to + 1S0oe
All Output and Supply Voltages ....... -O.SV to + 7V
AlllnputVoltages ............... -1.0Vto +S.SV
Power Dissipation . . . . . . . . . . . .. . ....... 1 Watt

D.C. CHARACTERISTICS

(TA = ooe to 7o oe, Vee = SV, ± 5%)
8 MHz

6 MHz
Sym

Parameter

-6
Min

-6
Max

-8
Min

-8

Max

Input lOW Voltage
Input HIGH Voltage

20

2.0

V

V1HR
VHYS

RES and EFI Input HIGH Voltage

2.6

26

V

RES Input hysteresis

0.25

0.25

VOL
VOH

RESET. PClK Output lOW Voltage

VOLR

~, Output lOW Voltage

.45

VOLe
VoHe

ClK Output lOW Voltage

45

Ve

Input Forward Clamp Voltage

RESET. PClK Output HIGH Voltage

----

ClK Output HIGH Voltage

.8

Unit Test Condition

V1L
V1H

8

V
V

IOL -5mA

V

IOH - -1mA

.45

V

IOL =7mA

45

V

IOL =5mA

45

45
24

2.4

4.0

40
-1.0

-

V

IOH - -8001lA

-10

V

le=-5mA

-.5

mA

iF

Forward Input Current

IR

Reverse Input Current

50

50

Icc
C1

Power Supply Current

145

145

Input Capacitance

10

10

-5

4-96

V

VF~

45V

uA VR-Vee
mA
pF

Fe=1MHz
210453-003

82284

(TA = D·C to 7D·C, vee = 5V, ± 5%)
AC timings are referenced to O.SV and 2.0V points of signals as Illustrated In datasheet waveforms, unless otherwise
noted.

A.C. CHARACTERISTICS

6MHz
Sym

Parameter

-6
Min

SMHz

-6
Max

-S
Min

-S
Max

Unit

Test Condition

1

EFI to ClK Delay

2

EFI lOW Time

40

3

EFI HIGH Time

35

4

ClK Penod

83

5

ClK lOW Time

20

15

6

ClK HIGH Time

25

25

7

ClK Rise Time

ns

1.0V to 3.6V Note 1

8

ClK Fall Time

9

Status Setup Time

10

Status Hold Time

11

35

500

30

ns

at 1.5V Note 1

25

ns

at 1 5V Note 1

Note 7

25

ns

at 1.5V Note 1

Note 7

ns

at 1.0V Note 1

Note 2,8

ns

at 3.6V Note 1

Note 2,8

62

10

500

10

10

10

ns

ns

3.6V to 1.0V Note 1

28

22

ns

Note 1

1

1

ns

Note 1

SRDY or SRDYEN Setup Time

25

15

ns

Note 1

12

SRDY or SRDYEN Hold Time

0

0

ns

Note 1

13

ARDY or ARDYEN Setup Time

5

0

ns

Note 1

Note 3

14

ARDY or ARDYEN Hold Time

30

30

ns

Note 1

Note 3

15

RES Setup Time

25

20

ns

Note 1

Note 3

16

RES Hold Time

10

10

ns

Note 1

Note 3

17

READY Inactive Delay

5

5

ns

at 0.8V Note 4

18

READY Active Delay

0

33

0

24

ns

at 0.8V Note 4

19

PClK Delay

0

45

0

45

ns

Note 5

20

RESET Delay

5

50

5

34

ns

NoteS

21

PClK lOW Time

t4-20

t4-20

ns

Note 5

Note 6

22

PClK HIGH Time

t4-20

t4-20

ns

Note 5

Note 6

NOTE 1: ClK loading. C L = 150pF.
NOTE 2: With the internal crystal oscillator uSing recommended crystal and capacitive loading, or with the EFI input meeting
specifications t2, and t3 Use a parallel-resonant, fundamental mode crystal. The recommended crystal loading for
ClK frequencies of8-16MHz are 25pF from pin X1 to ground, and 15pF from pin X2 to ground. These recommended
values are ± 5pF and include all stray capacitance, Decouple Vee and GND as close to the 82284 as possible.
NOTE 3: This is an asynchronous input. This specification is given for testing purposes only, to assure recognition at specific
ClKedge.
NOTE 4:

READY loading:

IOL = 7mA, C L = 150pF. In system application, use 910 ohm ±5% pull up resistor to meet 80286,
80286-6 and 80286-4 timing requirements.

NOTE 5: PClK and RESET loading: C L = 75pF. PClK also has 750 ohm pullup.
NOTE 6: t4 refers to any allowable ClK period.
NOTE 7: When driving the 82284 with EFI, provide minimum EFI HIGH and lOW times as follows:
ClK Output Frequency:

8MHz
ClK

12MHz 16MHz
ClK
ClK"

Min. required EFI HIGH time

52ns

35ns

25ns

Min. required EFI lOW time

52ns

40ns

25ns

At ClK frequencies above 12MHz, ClK output HIGH and lOW times are guaranteed only when using crystal with
recommended capacitive loading per Table 2, not when dnvlng componentfrom EFI All features ofthe 82284 remain
functional whether EFI or crystal is used to drive the 82284.
NOTE S: When using crystal (with recommended capacitive loading per Table 2) appropriate for speed of 80286, ClK output
HIGH and lOW times guaranteed to meet 80286 requirements.

4-97

'210453-003

82284

EFI

~rtv.

and M_ _ PoInIo

I

~
AY

1.SY

1.:/

1.SY

OA5Y

\;

1.DY

NOTE 10:

NOTE 9:

82284
eLK
OUTPUT

DEVICE
INPUT

NOTE 11. AC Setup. HOld and Delay Tome Measurement - General

vq

Ycc

Q

~

j.

75Oohm~

9100hm~

»

peLK
output

...

READY

0_ 0

output

outputs

-1

1~~t

l

~I

NOTE 12. AC Test Loading on Outputs

4-98

210453-003

82284

Waveforms
CLK as a Function of EFI

EFI

CLK

NOTE: The EFllnput lOW and HIGH times as shown are required to
guarentee the elK lOW and HIGH times shown.

RESET and READY Timing as a Function of RES
with S1 and SO HIGH

NOTE 1: This IS an asynchronous input. The setup and hold times
shown are required to guarantee the response shown.

NOTE 2: Tie 910 ohm ""5% pullup resistor to the READY output

READY and PCLK Timing with RES HIGH

NOTE 1: This is an asynchronous input. The setup and hold times
shown are reqUired to guarantee the response shown.

NOTE 2: Tie 910 ohm ±5'10 pullup resistor to the READY output

4-99

210453-003

82288
BUS CONTROLLER
FOR iAPX 286 PROCESSORS
(82288-8, 82288-6)

• Provides Commands and Control for
Local and System Bus

• Optional Multibus· Compatible
Timing

• Offers Wide Flexibility in System
Configurations

• Control Drivers with 16 ma IOL and
3·State Command Drivers with
32 ma IOL

• Flexible Command Timing
• Single + 5V Supply
The Intel 82288 Bus Controller is a 20-pin HMOS component for use in iAPX 286 microsystems. The bus
controller provides command and control outputs with flexible timing options. Separate command outputs are used for memory and I/O devices. The data bus is controlled with separate data enable and direction control signals.
Two modes of operation are possible via a strapping option: Multibus compatible bus cycles, and high
speed bus cycles.

3-STATE
COMMAND
STATU;
[

51

READY

OUTPUTS

r;:D=~T=lo=T~=~=R::;---;::::cg=L~=~=P~=c~=D::;' :~:~]

ClK

VCC

So

51

M/iO

MCE

DTiA"

ALE

DEN

M/iO

Mii5C
MWi'C

MB

ClK-+--i
CONTROL
INPUTS
CEN/AEN

CMDlY

CENl

CEN/AEN
CENl

MRDC

INTA

MWTC

IORC

CMDlY

REAiiY

GND
MB

Figure 1_

82288 Block Diagram

Figure 2.

IOWC

88228 Pin Configuration

*Multibus is a patented bus of Intel.
Intel Corporation Assumes No Responsibility for the Use of Any C)rcultry Other Than Circuitry Embodied In an Intel Product No Other Circuit Patent Licenses are Implied
©INTELCORPORATION,1982

4-100

January 1985

ORDER NUMBER: 210471-004

inter

82288

Table 1. Pin Description

The following pin function descriptions are for the 82288 bus controller.

Symbol

Type

Name and Function

ClK

I

System Clock provides the basic timing control for the 82288 in an iAPX 286 microsystem. Its frequency is twice the internal processor clock frequency. The falling edge
of this input signal establishes when inputs are sampled and command and control
outputs change.

SO, S1

I

Bus Cycle Status starts a bus cycle and, along with MilO, defines the type of bus cycle.
These inputs are active lOW. A bus cycle is started when either S1 or SO is sampled
lOW at the falling edge of ClK. Setup and hold times must be me1 for proper operation.

,

iAPX 286 Bus Cycle Status Definition
MilO

S1

SO

0
0
0
0
1
1
1
1

0
0

0
1
0
1
0
1
0
1

t
1
0
0
1
1

Type of Bus Cycle
Interrupt acknowledge
I/O Read
I/O Write
None; idle
Halt or shutdown
Memory read
Memory write
None, idle

MIlO

I

Memory or I/O Select determines whether the current bus cycle is in the memory space or 110
space. When LOW, the current bus cycle is in the 110 space. Setup and hold times must be met
for proper operation.

MB

I

Multibus Mode Select determines timing of the command and control outputs. When HIGH,
the bus controller operates with Multibus-compatible timings. When LOW, the bus controller
optimizes the command and control output timing for short bus cycles. The function of the
CEN/AEN input pin is selected by this signal. This input is typically a strapping option and not
dynamically changed.

CENL

I

Command Enable Latched is a bus controller select signal which enables the bus controller to
respond to the current bus cycle being initiated. CENL is an active HIGH input latched internally
at the end of each Ts cycle. CENl is used to select the appropriate bus controller for each bus
cycle in a system where the CPU has more than one bus it can use. This input may be connected
to Vcc to select this 82288 for all transfers. No control inputs affect CENL. Setup and hold times
must be met for proper operation.

CMDLY

I

Command Delay allows delaying the start of a command. CMDLY is an active HIGH input. If sampled
HIGH, the command output is not activiated and CMDLY is again sampled at the next eLK cycle.
When sampled LOW the selected command is enabled. If READY is detected LOW before the
command output is activated, the 82288 will terminate the bus cycle, even if no command was
issued. Setup and hold times must be satisfied for proper operation. This input may be connected
to GND if no delays are required before starting a command. This input has no effect on 82288
control outputs.

READY

I

READY indicates the end of the current bus cycle. READY is an active LOW input. Multibus mode
requires at least one wait state to allow the command outputs to become active. READY must be
LOW during reset, to force the 82288 into the idle state. Setup and hold times must be met for
proper operation. The 82284 drives READY LOW during RESET.

4-1Q1

210471-004

inter

82288

Table 2. Command and Control Outputs for Each Type of Bus Cycle
Type of
Bus Cycle

MIlO

S1

SO

Interrupt Acknowledge

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

I/O Read
I/O Write
None; idle
Halt/Shutdown
Memory Read
Memory Write
None; idle

Command
Activated

Command and Control Outputs
The type of bus cycle performed by the local bus
master is encoded in the M/iO, S1, and SO inputs.
Different command and control outputs are activated depending on the type of bus cycle. Table 2
indicates the cycle decode done by the 82288 and
the effect on command, DT/R, ALE, DEN, and MCE
outputs.

ALE, DEN
Issued?

MCE
Issued?
YES
NO

INTA

LOW

10RC

LOW

YES
YES

10WC

HIGH

YES

NO

None
None

HIGH
HIGH
LOW

NO

NO

MRDC
MWTC
None

Operating Modes
Two types of buses are supported by the 82288:
Multibus and non·Multlbus. When the MB input is
strapped HIGH, Multibus timing is used. In
Multibus mode, the 82288 delays command and
data activation to meet IEEE-796 requirements on
address to command active and write data to command active setup timing. Multibus mode requires
at least one wait state in the bus cycle since the
command outputs are delayed. The non-Multi bus
mode does not delay any outputs and does not require wait states. The MB input affects the timing
of the command and DEN outputs.

DT/R
State.

NO

NO

HIGH

YES
YES

NO
NO

HIGH

NO

NO

Bus cycles come in three forms: read, write, and
halt. Read bus cycles Include memory read, I/O
read, and interrupt acknowledge. The timing of the
associated read command outputs (MRDC, 10RC,
and INTA), control outputs (ALE, DEN, DT/R) and
control inputs (CEN/AEiii, CENL, CMDLY, MB, and
READY) are identical for all read bus cycles. Read
cycles differ only in which command output is activated. The MCE control output is only asserted
dl!ring interrupt acknowledge cycles.
Write bus cycles activate different control and
command outputs with different timing than read
bus cycles. Memory write and I/O write are write
bus cycles whose timing for command outputs
(MWi'C and iO"IiV"e), control outputs (ALE, DEN,
DT/R) and control inputs (CEN/AEN, CENL, CMDLY,
MB, and READY) are Identical. They differ only in
which command output is activated.
Halt bus cycles are different because no command
or control output is activated. All control Inputs are
ignored until the next bus cycle Is started via S1
and SO.

4-102

210471-()04

inter

82288

;'

Table 1. Pin Description (Cont.)
Symbol

Type

Name and Function

CEN/AEN

I

Command Enable/Address Enable controls the command and DEN outputs of the bus
controller. CEN/AEN inputs may be asynchronous to CLK. Setup and hold times are
given to assure a guaranteed response to synchronous inputs. This input may be connected to VCC or GND.
When MB is HIGH this pin has the AEN function. AEN is an active LOW input which indicates that the CPU has been granted use of a shared bus and the bus controller command outputs may exit 3-state OFF and become inactive (HIGH). AElii HIGH indicates
that the CPU does not have control of the shared bus and forces the command outputs
into 3-state OFF and DEN inacti~OW). AEN would normally be controlled by an
82289 bus arbiter which activates A N when that arbiter owns the bus to which the bus
controller is attached.
When MB is LOW this pin has the CEN function. CEN is an unlatched active HIGH input which
allows the bus controller to activate its command and DEN outputs. With MB LOW, CEN LOW
forces the command and DEN outputs inactive but does not tristate them.

ALE

0

Address Latch Enable controls the address latches used to hold an address stable during a bus cycle. This control output is active HIGH. ALE will not be issued for the halt
bus cycle and is not affected by any of the control inputs_

MCE

0

Master Cascade Enable signals that a cascade address from a master 8259A interrupt
controller may be placed onto the CPU address bus for latching by the address latches
under ALE control. The CPU's addreSs bus may then be used to broadcast the cascade
address to slave interrupt controllers so only one of them will respond to the interrupt
acknowledge cycle. This control output is active HIGH. MCE is only active during interrupt acknowledge cycles and is not affected by any control input. Using MCE to enable
cascade address drivers requires latches which save the cascade address on the falling
edge of ALE.

DEN

0

Data Enable controls when data transceivers connected to the local data bus should
be enabled. DEN is an active HIGH control output. DEN is delayed for write cycles in
the Multibus mode.

DTIR

0

Data Transmit/Receive establishes the direction of data flow to or from the local data
bus. When HIGH, this control output indicates that a write bus cycle i~being performed.
A LOW indicates a read bus cycle. DEN is always inactive when DTIR changes states.
This output is HIGH when no bus cycle is active. DTiR is not affected by any of the control inputs.

10WC

0

1/0 Write Command instructs an I/O device to read the data on the data bus. This command output is active LOW. The MB and CMDLY inputs control when this output
becomes active. READY controls when it becomes inactive.

10RC

0

I/O Read Command instructs an I/O device to place data onto the data bus. This command output is active LOW. The MB and CMDLY Inputs control when thiS output
becomes active. READY controls when it becomes inactive.

MWTC

0

Memory Write Command instructs a memory device to read the data on the data bus.
T\his command output is active LOW. The MB and CMDLY inputs control when this output becomes active. READY controls when it becomes inactive.

MRDC

0

Memory Read Command instructs the memory device to place data onto the data bus.
This command output Js active LOW. The MB and CMDLY inputs control when this output becomes active. READY controls when it becomes inactive.

INTA

0

Interrupt Acknowledge tells an interrupting device that its interrupt request is being
acknowledged. This command output is active LOW. The MB and CMDLY inputs control when this output becomes active. READY controls when it becomes inactive.

VCC

System Power: + 5V power supply

GND

System Ground: 0 volts

4-103

210471-004

82288

FUNCTIONAL DESCRIPTION
Introduction
The 82288 bus controller is used in iAPX 286
systems to provide address latch control, data
transceiver control, and standard level-type command outputs. The command outputs are timed
and have sufficient drive capabilities for large TTL
buses and meet all IEEE-796 requirements for
Multibus. A special Multibus mode is provided to
statlsfy all address/data setup and hold time requirements. Command timing may be tailored to
special needs via a CMDlY input to determine the
start of a command and READY to determine the
end of a command.
Connection to multiple buses are supported with
a latched enable input (CENl). An address
decoder can determine, which, if any, bus controller should be enabled for the bus cycle. This
input is latched to allow an address decoder to
take full advantage of the pipelined timing on the
iAPX 286 local bus.
Buses shared by several bus controllers are supported. An AEN input prevents the bus controller

from driving the shared bus command and data
signals except when enabled by an external bus
arbiter such as the 82289.
Separate DEN and DT/R outputs control the data
transceivers for all buses. Bus contention is
eliminated by disabling DEN before changing
DT/R. The DEN timing allows sufficient time for
tristate bus drivers to enter 3-state OFF before
enabling other drivers onto the same bus.
The term CPU refers to any iAPX 286 processor or
iAPX 286 support component which ,may become
an iAPX 286 local bus master and thereby drive the
82288 status inputs.

Processor Cycle Definition
Any CPU which drives the local bus uses an internal
clock which is one half the frequency of the system
clock (ClK) (see Figure 3). Knowledge of the phase
of the local bus master internal clock is required for
proper operation of the iAPX 286 local bus. The local
bus master informs the bus controller of its internal
clock phase when it asserts the status signals. Status
signals are always asserted beginning in Phase 1 of
the local bus master's internal clock,

VeH

ClK
Vel

82284
(FOR REFERENCE)

Figure 3.

PClK

_ _I-J

ClK Relationship to the Processor Clock and Bus T·States

4-104

210471-004

inter

82288

Bus State Definition

Bus Cycle Definition

The 82288 bus controller has three bus states (see
Figure 4): Idle
Status (TS> and Command (Te>.
Each bus state Is two ClK cycles long. Bus state
phases correspond to the internal CPU processor
clock phases.

The 51 and SO inputs signal the start of a bus cycle. When either input becomes lOW, a bus cycle
is started. The Ts bus state is defined to be the two
ClK cycles during which either S1 or SO are active
(see Figure 5). These inputs are sampled by the
82288 at every falling edge of ClK. When either S'i
or SO are sampled lOW, the next ClK cycle is considered the second phase of the internal CPU clock
cycle.

m

The TI bus state occurs when no bus cycle is currently active on the IAPX 286 local bus. This state
may be repeated indefinitely. When control of the
local bus is being passed between masters, the
bus remains in the TI state.

The local bus enters the Te bus state after the Ts
state. The shortest bus cycle may have one Ts state
and one Testate. longer bus cycles are formed by
repeating Te states. A repeated Te bus state is
called a walt state.
The READY Input determines whether the current
Te bus state is to be repeated. The RI:AuY input
has the same timing and effect for all bus cycles.
READY is sampled at the end of each Te bus state
to see if it is active. If sampled HIGH, the Te bus
state Is repeated. This is called inserting a wait
state. The control and command outputs do not
change during walt states.
When READY is sampled lOW, the current bus cycle is terminated. Note that the bus controller may
enter the Ts bus state directly from Te if the status
lines are sampled active at the next falling edge of
ClK.

.

READY
NEW CYCLE

Figure 4.

82288 Bus States

VCH
ClK
VeL

iI.iii V.. ....,._""""\
FROM
CPU VOL

Figure 5.

Bus Cycle Definition
4-105

210471-004

82288

Figures 6-10 show the basic command and control
,output timing for read and write bus cycles. Halt
bus cycles are not shown since they activate no
outputs. The basic idle-read-idle and idle-write-idle
bus cycles are shown. The signal label CMD
represents the appropriate command output for
the bus cycle. For Figures 6-10, the CMDLY input is
connected to GND and CENL to Vee. The effects of
CENL and CMDLY are described later in the section on control inputs.

f-o---READ BUS CYCLE

T,

I

'I

T,

+---'

DEN _ _ _ _ _ _

DTfR

CMD

-------"r-\

Figure 6.

Idle· Read· Idle Bus Cycles with MB =0

WRITE BUS CYCLE
Ts

Tc

AlE _ _ _ _---'

Figures 6, 7 and 8 show non-Multibus cycles. MB is
connected to GND while CEN is connected to Vee'
Figure 6 shows a read cycle with no wait states while
Figure 7 shows a write cycle with one wait state, The
"FlEADY input is shown to illustrate how wait states
are added,

T,

I

Ts

ClK

Tc

~WAIT~:ATE

::j

I

T,

elK

ALE _ _ _ _-¥

DEN _ _ _ _- - '

VOH
DTiR

-------f------+------Jr-------

Figure 7.

Idle·Wrlte·ldle Bus Cycles with MB = 0

4-106

210471-004

intJ

82288

Bus cycles can occur back to back with no T, bus
states between Te and Ts. Back to back cycles do
not affect the timing of the command and control
outputs. Command and control outputs always
reach the states shown for the same clock edge
(within Ts , Te , or following bus state) of a bus cycle.

1ST WRITE CYCLE

+

Tc

2ND WRITE CYCLE

I

Ts

I

Tc

ClK

A special case in control timing occurs for back to
back write cycles with MB = O. In this case, DT/R
and DEN remain HIGH between the bus cycles (see
Figure 8). The command and ALE output timing
does not change.
Figures 9 and 10 show a Multibus cycle with
MB=1. AEN and CMDLY are connected to GND.
The effects of CMDLY and AEN are described later
in the section on control inputs. Figure 9 shows a
read cycle with one wait state and Figure 10 shows
a write cycle with two wait states. The second wait
state of the write cycle is shown only for example
purposes and is not required. The READY input is
shown to illustrate how wait states are added.

OE~OH --+---------+
VOH

OT/ii

---+----------j-

CMD _ _ _- - '

Figure 8.

T,

Tc

Ts

Write·Write Bus Cycles with MB = 0

Tc

T,

ClK

AlE _ _ _ _- - '

+--rJ

OEN _ _ _ _ _ _ _

OT/II - - - - - - - - ; - , \

CMO

Figure 9.

Idle·Read·ldle Bus Cycles with MB = 1

4-107

210471-004

inter

82288

T,

T.

To

T,

To

ClK
j§'i.§ii

j

AlE _ _ _ _ _..J

DEN _ _ _ _ _ _ _ _- '

CMD-----------~-~

Figure 10.

Idle·Wrlte·ldle Bus Cycles with MB

=1

The MB control input affects the timing of the command and DEN outputs. These outputs are
automatically delayed in Multibus mode to satisfy
three requirements:

Back to back bus cycles with MB = 1 do not
change the timing of any of the command or control outputs. DEN always becomes inactive between bus cycles with MB= 1.

1) 50 ns minimum setup time for valid address

Except for a halt or shutdown bus cycle, ALE will
be issued during the second half of Ts for any bus
cycle. ALE becomes inactive at the end of the Ts
to allow latching the address to keep it stable during the entire bus cycle. The address outputs may
change during Phase 2 of any Tc bus state. ALE is
not affected by any control input.

before any command output becomes active.
2) 50 ns minimum setup time for'valid write data
before any write command output -becomes active.
3)65 ns maximum time from when any read command becomes inactive until the slave's read
data drivers reach 3-state OFF.
Three signal transitions are delayed by MB = 1 as
compared to MB=O:
1) The HIGH to lOW transition of the' read com-

mand outputs (IORC, MRDe, and INTA) are
delayed one ClK cycle.

Figure 11 shows how MCE is timed during interrupt acknowledge (INTA) bus cycles. MCE is one
ClK cycle longer than ALE to hold the cascade
address from a master 8259A valid after the failing
edge of ALE. With the exception of the MCE control output, an INTA bus cycle is Identical in timing to a read bus cycle. MCE is not affected by any
control input.

2) The HIGH to lOW transition of the write command outputs (IOWC and MWTC) are delayed
two ClK cycles.
3) The lOW to HIGH transition of DEN for write
cycles is delayed one ClK cycle.

4-108

210471-004

intJ

82288

T,

T,

CENL must be sampled HIGH at the end of the Ts
bus state (see waveforms) to enable the bus controller to activate its command and control outputs. If sampled LOW the commands and DEN
will not go active and DT/R will remain HIGH. The
bus controller will ignore the CMDLY, CEN, and
READY inputs until another bus cycle is started
via 51 and SO. Since an address decoder is commonly used to identify which bus is required for
each bus cycle, CENL is latched to avoid the need
for latching its input.

Tc

ClK

ALE _ _ _ _'\--'

MCE _ _ _ _ __

Figure 11.

MCE Operation for an INTA Bus Cycle

Control Inputs
The control inputs can alter the basic timing of
command outputs, allow interfacing to multiple
buses, and share a bus between different
masters. For many iAPX 286 systems, each CPU
will have more than one bus which may be used to
perform a bus cycle. Normally, a CPU will only
have one bus controller active for each bus cycle.
Some buses may be shared by more than one CPU
(Le. Multibus) requiring only one of them use the
bus at a time.
Systems with multiple and shared buses use two
control input signals of the 82288 bus controller,
CENL and AEN (see Figure 12). CENL enables the
bus controller to control the current bus cycle.
The AEN input prevents a bus controller from driv·
ing its command outputs. AEN HIGH means that
another bus controller may be driving the shared
bus.
In Figure 12, two buses are shown: a local bus and
a Multibus. Only one bus is used for each CPU bus
cycle. The CENL inputs of the bus controllers
select which bus controller is to perform ·the bus
cycle. An address decoder determines which bus
to use for each bus cycle. The 82288 connected to
the shared Multibus must be selected by CENL
and be given access to the Multibus by AEN
before it will begin a Multibus operation.

The CENL input can affect the DEN control output. When MB = 0, DEN normally becomes active
during Phase 2 of Ts in write bus cycles. This transition occurs before CENL is sampled. If CENL is.
sampled LOW, the DEN output will be forced LOW
during Tc as shown in the timing waveforms.
When MB = 1, CEN/AEN becomes AEN. AEN controls when the bus controller command outputs
enter and exit 3-state OFF. AEN is intended to be
driven by a bus arbiter, like the 82289, which
assures only one bus controller is driving the
shared bus at any time. When AEN makes a LOW
to HIGH transition, the command outputs immediately enter 3-state OFF and DEN is forced inactive. An inactive DEN should force the local
data transceivers connected to the shared data
bus into 3-state OFF (see Figure 12). The LOW to
HIGH transition of AEN should only occur during
T, or Ts bus states.
The HIGH to LOW transition of AEN signals that
the bus controller may now drive the shared bus
command Signals. Since a bus cycle may be ac·
tive or be in the process of starting, AEN can
become active during any T-state. AEN LOW immediately allows DEN to go to the appropriate
state. Three CLK edges later, the command outputs will go active (see timing waveforms). The
Multibus requires this delay for the address and
data to be valid on the bus before the commands
become active.
When M B = 0, CEN/AEN becomes CEN. CEN is an
asynchronous input which immediately affects
the command and DEN outputs. When CEN
makes a HIGH to LOW transition, the commands

4-109

210471-004

inter

82288

and DEN are immediately forced inactive. When
CEN makes a LOW to HIGH transition, the com·
mands and DEN outputs immediately go to the
appropriate state (see timing waveforms). READY
must still become active to terminate a bus cycle
if CEN remains LOW for a selected bus controller
(CENL was latched HIGH).

Some memory or I/O systems may require more
address or write data setup time to command ac·
tive than provided by the basic command output
timing. To provide flexible command timing, the
CMDLY input can delay the activation of com·
mand outputs. The CM DL Y input must be
sampled LOW to activate the command outputs.
CMDLY does not affect the control outputs ALE,
MCE, DEN, and DTiR.

rD~
X1
READY

F
CMD

<=

X2

SRDffi
ClK

XACK

ARiiY

SRDY

82284 ARDYEN
9100 ±S%
READY

51.S0

READY

CMD
ClK 82288

MiiO

MliO
51,So
CENl

COMM ANDS

READY

CMD 82288 ClK

,..

~

CEN

MB

t

+!v

Jv
READY

~

DTIR
ALE

CENl

MB

~

DEN

S1.So

AEN

t

AEN
CONTROl

ClK 82289
ADDRESS

MliO
S1.So

DECODER

CNTl

SYSIRESB

ADDRESS
DATA

n

MilO

so

20KO

§1

.... +5V

/Si-ii= ,....,
/

L

ADD RESS

8283

II
A 2So0

ClK

READY

MilO
51,So

V~

1.1

/Tm
80286

DATA
D, ..

I - - ----'\

Figure 12.

)

8287

V

System Use of AEN arid CENL
4-110

210471-004

82288

CMDlY is first sampled on the falling edge of the
ClK ending Ts. If sampled HIGH, the command
output is not activated, and CMDlY is again
sampled on the next falling edge of ClK. Once
sampled lOW, the proper command output
becomes active immediately if MB O. If MB 1,
the proper command goes active no earlier than
shown in Figures 9 and 10.

=

sitions of all Signals in all modes. Instead, all
signal timing relationships are shown via the
general cases. Special cases are shown when
needed. The waveforms provide some functional
descriptions of the 82288; however, most functional descriptions are provided in Figures 5
through 11.

=

READY can terminate a bus cycle before CMDlY
allows a command to be issued. In this case no
commands are issued and the bus controller will
deactivate DEN and DT/R in the same manner as if
a command had been issued.

To find the timing specification for a Signal transition in a particular mode, first look for a special
case in the waveforms. If no special case applies,
then use a timing specifi'cation for the same or
related function In another mode.

Waveforms Discussion
The waveforms show the timing relationships of in·
puts and outputs and do not show all possible tran·

4-111

210471-004

intJ

82288

• NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias .... O°C to 70°C
Storage Temperature ......... -65°C to + 150°C
Voltage on Any Pin with
Respect to G N D ............... - O.5V to + 7V
Power Dissipation ...................... 1 Watt

D.C. CHARACTERISTICS (TA ~ ooe to 7ooe, vcc ~ 5V, ± 5%)
8 MHz

6 MHz
-6
Min_

-6
Max.

-8
Min.

-8
Max.

Units

Input lOW Voltage

-.5

.8

-5

.8

V

Vi}:{

Input HIGH Voltage

20

Vcc +.5

2.0

Vcc +.5

V

VILC

ClK Input lOW Voltage

-.5

.6

-.5

.6

V

VIHC

ClK Input HIGH Voltage

3.8

Vcc +.5

3.8

Vcc +.5

V

VOL

Output lOW Voltage
Command Outputs
Control Outputs

.45
45

V
V

IOL
IOL

~

V
V

IOH
IOH

~

-.5

mA

VI

Symbol
VIL

VOH

Parameter

Output HIGH Voltage
Command Outputs
Control Outputs

.45
.45
2.4
2.4

2.4
2.4

Test Conditions

32 mA Note 1
16mA Note 2

~

~

~

IF

Input Current (80 and 81 inputs)

-.5

IlL

Input leakage current (all
other inputs)

±10

±10

~A

OV

ILO

Output leakage Current

±10

± 10

~A

.45V

Icc

Power Supply Current

120

120

mA

-5mA Note 1
-lmANote2

.45V

:5

VI IN
:5

:5

VOUT

CCLK

ClK Input Capacitance

12

12

pF

Fc

~

1 MHz

CI

Input Capacitance

10

10

pF

Fc

~

1 MHz

Co

Input/Output Capacitance

20

20

pF

Fc

~

1 MHz

Vce
:5

Vcc

NOTE: 1: Command Outputs are INTA, IORC, IOWC, MRDC, MWRC.
2. Control Outputs are DTIR, DEN, ALE and MCE.

4-112

210471-004

inter

82288

A.C. CHARACTERISTICS
(TA ~ OOG to 70 o G, Vcc ~ 5V, ± 5%)
AG timings are referenced to O.BV and 2.0V points of signals as illustrated in data sheet waveforms, unless otherwise noted
6 MHz

Sym

Parameter

1

CLK Period

8 MHz

-6

-6

Min.

Max.

-8
Min.

-8
Max.

Unit

83

250

62

250

ns

Test Condition

2

CLK HIGH Time

25

230

20

235

ns

3

CLKLOWT,me

20

225

15

230

ns

all0V

4

CLK Rise Time

10

ns

1 OV 10 3 6V

5

CLK Fall Time

10

ns

36Vlol0V

6

MilO and Status Setup Time

7

MilO and Status Hold Time

8

CENL Setup Time

9

10

,

CENL Hold Time

10
22

28

al36V

ns

1

1

ns

30

20

ns

1

1

ns

10

READY Setup Time

50

38

ns

11

READY Hold Time

35

25

ns

12

CMDLY Setup Time

25

20

ns

13

CMDLY Hold Time

1

1

ns

14

AEN Setup Time

25

20

ns

Note 3

15

AEN Hold Time

0

0

ns

Note 3

16

ALE, MCE Active Delay from CLK

3

20

ns

Note 4

17

ALE, MCE Inactive Delay from CLK

35

25

ns

Note 4

18

DEN (Write) Inactive from CENL

35

35

ns

Note 4

19

DT IR LOW from CLK

40

25

ns

Note 4

20

DEN (Read) Active from DTIR

5

50

5

35

ns

Note 4

21

DEN (Read) Inactive Diy from CLK

3

40

3

35

ns

Nole 4

22

DT IR HIGH from DEN Inactive

5

45

5

35

ns

Note 4

23

DEN (Write) Active Delay from CLK

30

ns

Note 4

24

DEN (Wrile) Inactive Diy from CLK

30

ns

Note 4

25

DEN Inactive from CEN

40

30

ns

Note 4

26

DEN Active from CEN

35

30

ns

Note 4

27

DT IR HIGH from CLK
LOW)

50

35

ns

Note 4

28

DEN Active from AEN

35

30

ns

Note 4

29

CMD Active Delay from CLK

3

40

3

25

ns

Nole5

30

CMD Inactive Delay from CLK

3

30

3

25

ns

Note 5

31

CMD Inactive from CEN

35

25

ns

Note 5

32

CMD Active from CEN

45

25

ns

Nole 5

33

CMD Inactive Enable from AEN

40

40

ns

Note 5

34

CMD Float Oelay from AEN

ns

Note 6

35

MB Setup Time

25

20

ns

36

MB Hold Time

0

0

ns

37

Command Inacllve Enable
fromMBI

40

40

ns

Nole 5

38

Command Floal Time from MBI

40

40

ns

Note 6

39

DEN Inacllve from MBI

40

30

ns

Nole 4

40

DEN Active from MBI

35

30

ns

Note 4

(when CEN

0

25

3

35
3

35

3

40

40

NOTE: 3 AEN IS an asynchronous Input ThiS specification IS for testing purposes only, to assure recognition at a specific

CLK edge
4 Control oulput load CI = 150pF
5 Command' oulpulload CI = 300pF
6 Float conditIOn occurs when output current

IS

less then ILO

4-113

In

magnitude

210471-004

inter

82288

4.0V

O.4SV

NOTE 7:

AC Drive and Measurement Points - ClK Input

4.0V
CLKINPUT
1.OV
O.45V

'HOLD

2.4V
OTHER
DEVICE
:INPUT
O.8V
O.45V
'DELAY

2.0V
DEVICE
OUTPUT
O.8V

NOTE 8:

AC Setup, Hold and Delay Time Measurement - General
DEVICE
OUTPUT

NOTE 9:

AC Test loading on Outputs

4-114

210471-004

inter

82288

WAVEFORMS
ClK CHARACTERISTICS

CLK

STATUS, ALE, MCE, CHARACTERISTICS
1 + - - - - Ta - - - - - t.......- - -

CLK

M/iO,S1,Sii ---t=liLI+<

ALE _ _ _ _ _ _

~

MCE _ _ _ _ _ _---J

CENL, CMDlY, DEN CHARACTERISTICS WITH MB=O AND CEN=1 DURING WRITE CYCLE

CLK

DEN _ _ _ _+-J

CENL

4-115

210471-004

inter

82288

WAVEFORMS (Continued)
READ CYCLE CHARACTERISTICS WITH MB = 0 AND CEN = 1
TS---+/-O----ClK

CMDlY

DTiii"----+-'=\

-+=--,

DEN _ _

CMD----+-'\

CENl

WRITE CYCLE CHARACTERISTICS WITH MB

=0 AND CEN =1

ClK

DEN _ _ _ _ _ _-'

VOH---------H---+--,..---j/-----t----DT/A

CMDlY

CENl

4-116

210471-004

intJ

82288

WAVEFORMS (Continued)
CEN CHARACTERISTICS WITH MB

=O'

ClK

CEN

DEN

CMD

+./

DT/R _ _ _ _ _ _ _ _ _ _ _II___

ill CHARACTERISTICS WITH

MB = 1

ClK

AEN

DEN _ _ _. J

NOTE 1:

AEN is an asynchronous input. AEN setup and hold time is specified to guarantee the response shown

4-117

In

the waveforms.

210471-004

82289
BUS ARBITER
FOR iAPX 286 PROCESSOR FAMILY
• Supports Multi-master System Bus
Arbitration Protocol

• Three Modes of Bus Release Operation for
Flexible System Configuration

• Synchronizes 80286 Processor with Multlmaster Bus

• Supports Parallel, Serial, and Rotating
Priority Resolving Schemes

• Compatible With Intel Bus Standard
Multibus®* (IEEE 796 Standard)

• Available in EXPRESS - Standard
Temperature Range

The Intel 82289 Bus Arbiter is a 5-Volt, 20-pin HMOS III component for use in multiple bus master iAPX 286
systems. The 82289 provides a compact solution to system bus arbitration for the 80286 CPU.
The complete IEEE 796 Standard bus arbitration protocol is supported. Three modes of bus release operation
support a number of bus usage models.

l lOCK#

STATUS lSO#/HOLD -ISl#
INPUTS

-fM/IO# -f-

r
l'

MULTIBUS
INTERFACE'

PROCESSOR
INTERFACE

-IREA~~~ -I-

LOCAL
SYSTEM
CONTROL
LOCK#
ALWAYS #/CBQLCK #

STATE

STATE
MACHINE

~ACHINE

I-

I- -

BPRN# SIGNALS

I-

BPRO#

l- I - BClK#
I- r--'CBRQ#
~

BUS REQUEST
AND
RELEASE
LOGIC

-

MULTIBUS

BREQ# INTERFACE

-

BUSY#
INIT#

SB/~E::E~

SY

AEN#

'1

M/IO#
READY#
SYSB/RESB#
RESET
BCLK#
INIT#
BREQ#
BPRO#
BPRN#
GND

3

6
7

Vee
Sl#
Soo/HOlD
ClK
LOCK#
ALWAYS#
lLOCK# I CBQLCK#
AEN#
CBRQ#
BUSY#

# INDICATES FUNCTION IS ACTIVE LOW

Figure 1. 82289 Block Diagram

Figure 2. 82289 Pin Diagram

Intel Corporation Assumes No Responslblltyforthe Useof Any CircUitry Other Than Circuitry Embodied In an Intel Product No Other CirCUit
, Patent Licenses are Implied Information Contained Herein Supercedes Previously Published SpeCifications of These DeVices from Intel

©INTEl CORPORATION 1984

4-118

ORD~R NUMBER

231095-002

'82289

Table 1. 82289 Pin Definition
Symbol

Pin(s)

Type

Name and Function

ClK

17

I

SO#/HOLD

18

I

SYSTEM CLOCK accepts the ClK signal from the 82284 Clock
Generator chip as the timing reference for the bus arbiter and
processor interface signals,
STATUS INPUT SO# or HOLD is either the SO# status signal from
80286 or the HOLD signal from some other bus master, The function of
this input is established during the processor reset of the 82289 Bus
Arbiter. The 80286 SO# pin meets the setup and hold time requirements
of this pin.

The SO# pin function is selected by forcing this input high during the
falling edgeof processor reset. If the 82289 is used to support an 80286
processor, the SO# output of the processor will be high during reset.
In supporting the 80286 processor, the 82289 decodes the SO# pin
together with the other status input pins, S1# and M/IO#, to determine
the beginning of a processor bus cycle and initiate bus request and
surrender actions.

I-

The HOLD function of the SO#/HOlD pin is selected by holding this
input low during the falling edge of processor reset. When supporting
a bus master other than 80286, the 82289 monitors the HOLD signal to
initiate bus request and surrender actions.

sm.

M/IO#

19, 1

I

,

STATUS INPUTS are the status input signal pins from the 80286
processor. The arbiter decodes these inputs together with SO#/HOlD
input to initiate bus request and surrender actions. A bus cycle is
started when either S1# or SO# is sampled lOW at the falling edge of
ClK. The 80286 S1# and M/IO# pins meet the setup and hold time
requirements of these pins.

80286 Bus Cycle Status Encoding
M/IO#
0
0
0
0
1
1
1
1

S1#
0
0
1
1
0
0
1
1

SO#/HOLD
0
1
0
1
0
1
0
1

Type 01 Bus Cycle
Interrupt acknowledge
I/O Read
I/O Write
None; bus idle
Halt or shutdown
Memory read
Memory write
None; bus idle

When supporting the HOLD output of another bus master, the S1# and
M/IO# pins must be held HIGH during Ts, the Status Cycle, for proper
operation.
SYSB/RESB#

3

I

SYSTEM BUS/RESIDENT BUS# is an Input signal which determines
when the multi-master system bus is required for the current bus cycle.
The signal can originate from address mapping circuitry such as a
decoder or PROM attached to the processor address and status pins.
The arbiter will request or retain control of the multi-master system bus
when the SYSB/RESB# pin is sampled HIGH at the end of the Ts bus
state.

During an interrupt acknowledge cycle, this input is sampled on every
falling edge of ClK starting at the end of .the Ts state until either
SYSB/RESB# is sampled HIGH or the bus cycle is terminated by the
READY# signal. Setup and hold times for this pin must be met for
proper operation.
4-119

231095-002

82289
Table 1. 82289 Pin Definition (continued)
Symbol

Pines)

Type

Name and Function

READY#

2

I

READY# is an active-lOW signal which indicates the end of the bus
cycle. The 80286 halt or shutdown cycle does not require READY# to
terminate the bus cycle. Setup and hold times for this pin must be met
for proper operation.

lOCK#

16

I

LOCK # is a processor-generated signal which when asserted (lOW)
prevents the arbiter from surrendering the multi-master system bus to
ariy other bus arbiter, regardless of its priority. lOCK# is sampled by
the arbiter at the end of the Ts (status) bus state. Setup and hold times
for this pin must be met for proper operation.
ALWAYS RELEASE# or COMMON BUS REQUEST LOCK# can be
programmed at processor reset to be either the ALWAYS RELEASE
(AlWAYS#) strapping option or the COMMON BUS REQUEST lOCK
(CBQlCK#) control input. Setup and hold times for this pin must be
met for proper programming.

AlWAYS#/
CBQlCK#

--15

--

I

When this pin is lOW during the falling edge of processor reset
(AlWAYS# option) the arbiter is programmed to surrender the multimaster system bus after each bus transfer cycle. The 82289 will remain
in the ALWAYS RELEASE mode until it is reprogrammed during the
next processor reset.
The bus arbiter is programmed to support the COMMON BUS
REQUEST lOCK function by forcing this input pin HIGH during the
falling edge of the processor reset.
CBQlCK# itself is an activeclOW signal which when active prevents
the arbiter from surrendering the multi-master system bus to ,a
common bus request through the CBRQ# input pin.
PROCESSOR RESET is an active-HIGH i"nput synchronous to the
system clock (ClK). RESET is the processor initialization ofthe arbiter
to release the mUlti-master bus and clear any pending request.

RESET

4

I

INIT#

6

I

INITIALlZE# is an active-low Multibus signal used to reset all arbiters
on the Multlbus system. It will cause the release of the multi-master
bus, but will not clear the pending bus master request so that the
arbiter can again request the multi-master bus. No arbiters have the
use of the multi-master bus Immediately after initialization. INIT# is an
asynchronous signal to ClK.

BClK#

5

I

BUS CLOCK# is the multi-master system bus clock to which the
multi-master bus interface signalsare synchronized. BClK# can be
asynchronous to ClK.

BREQ#

7

a

BUS REQUEST# is an active-lOW output signal used in the parallel
and rotating priority resolving schemes. The arbiter activates BREQ#
to request the use of the multi-master system bus. The arbiter holds
BREQ# active as long as it is requesting or has possession of the
multi-master system bus.

CBRQ#

12

I/O
(opendrain)

COMMON BUS REQUEST# is a Multibus signal that indicates when
an arbiter is requesting the Multibus. This pin is an open-drain
input/output requiring an external pullup resistor.
As an input CBRQ# indicates that another arbiter is requesting the
multi-master system bus. The input function of this pin is enabled by
the CBQlCK# signal. Setup and hold times forthis pin must be met for
proper operation.
As an output CBRQ# is asserted to indicate that this arbiter is
requesting the Multibus. The arbiter pulls CBRQ# low when it issues a
BREQ#. The arbiter release CBRQ# when it obtains the Multibus.
4-120

231095-002

inter

82289
Table 1. 82289 Pin Definition (continued)

Symbol

Pin(s)

Type

Name and Function

BPRN#

9

I

BUS PRIORITY IN# is an active-low input indicating that this arbiter
has the highest priority of any arbiter requesting the system bus.
BPRN# HIGH signals the arbiter that a higher priority arbiter is
requesting or has possession of the system bus. Setup and hold times
for this pin must be met for proper operation.

BPRO#

8

0

BUS PRIORITY OUT# is an active-low output signal used in the serial
priority resolving scheme. BRPO# is connected to BPRN# of the next
lower priority to ,grant or revoke priority from that arbiter.

BUSY#

11

-I/O
(opendrain)

BUSY# is a Multibus signal which is asserted when the system bus
is in use.
BUSY# is an open drain input/outp'ut requiring an external pullup
resistor.
As an input BUSY# asserted indicates when the Multibus is in use.
Setup and hold times must be met for proper operation,
As an output BUSY# is asserted to signal when this arbiter has taken
control of the Multibus.

AEN#

13

0

ADDRESS ENABLE# is the output of the arbiter which goes directly to
the processor's address latches, the 82288 Bus Controller and the
82284 Clock Generator. AEN# asserted causes the bus controller and
address latches to enable their output drivers. AEN# also drives the
clock generator ARDYEN# input to enable its asynchronous ready
input (ARDY#).
AEN# can also be used as an active-lOW Hold Acknowledge to a bus
master other than 80286. It signals to the bus master that control of the
system bus has been relinquished when AEN# is inactive (HIGH).

llOCK#

14

0

Note that AEN# goes active relative to BClK# and goes inactive
relative to ClK.
LEVEL LOCK# is an active-low output signal decoded from processor
lOCK# signal. llOCK# can be used as Multibus lOCK# when
buffered with a tri-state buffer enabled by the AEN# Signal. llOCK#
will be cleared by RESET but not by INIT#.

Vee

20

I

+5 volts supply voltage

GND

10

I

Ground

FUNCTIONAL DESCRIPTION
The 82289 Bus Arbiter in conj unction with the 82288
Bus Controller and the 82284 Clock Generator
interfaces the 80286 processor or some other bus
master to a multi-master system bus. The arbiter
multiplexes a processor onto a multi-master system
bus. It avoids contention with other bus masters.

determine which bus cycles require the system bus
and to resolve priorities of simultaneous requests
for control of the system bus.

82289 with 80286
In an iAPX 286 system using ar:1 82289 Bus Arbiter,
the 80286 processor is unaware of the arbiter's
existence and issues cammands as though it had
exclusive use of the multi-master system bus such
as Multibus'", If the processor cycle requires
Multibus access, the arbiter requests control of the
Multibus. Until the request is granted the 82289
keeps AEN# disabled to prevent the 82288 Bus
Controller and the address latches from accessing
the Multibus. AEN# inactive also disasserts the

The 82289 has two separate state machines which
communicate through bus request and release
logic. The processor interface state machine is
synchronou~ with the local system clock (ClK) and
the multi-master system bus interface state machine
is synchronous with the bus clock (BClK#).
The 82289 performs all signalling to request, obtain,
and release the system bus. External logic is used to
4-121

231095-002

inter

82289

asynchronous ready enable (ARDYEN#) input of
the 82284 clock chip so that the system bus will
appear a;s "NOT READY" to the 80286 processor.
Once the 82289 Bus Arbiter ha acquired the bus, it
will assert AEN# allowing the 82288 Bus Controller
and the address latches to access the system bus
and asserting the ARDYEN# input of the 82284
Clock chip.
Typically, once the data transfer command has been
issued by the 82288 and the data transfer has taken
place, a transfer acknowledge (XACK#) signal is
returned to the processor on the multi-master
system bus to indicate "Ready" from the accessed
slave device. The processor remains in a series of
"Wait States" (Repeated Tc states) unitl the addressed device responds with XACK# asserted
signal to the 82284 ARDY# input and the 82284
asserts READY# to the processor. The processor
then completes its bus cycle.

82289 with other Bus Masters
When supporting other bus masters, the SO#/HOlD
and READY# pins of the bus arbiter can be connected
to the 'Hold' pin of that master. The inverted AEN#
signal from the 82289 can be used as the hold
acknowledg~ (HlDA) input forthe other bus master.

ClK

~ONE SYSTEM _ I
ClKCYClE-J

PClKY

' ...._ _ _--:1

Figure 3: elK Relationship to Internal Processor
Phase, and Bus T-States

Bus State Definition
The 82289 Bus Arbiter has three processor bus
states (see figure 4): Idle (TI ), Status (T s), Command
(T d. Each bus state is two ClK cycles long. Bus
state phases correspond to the internal CPU processor clock phases.

The bus master sends a HOLD signal to the bus
arbiter when it needs the system bus for a memory
access. If the arbiter currently controls the system
bus, AEN# will be active. Otherwise, AEN# will be
inactive and the arbiter will request control of the
system bus. The bus master will have to wait until
the 82289 has asserted AEN# (lOW), before it starts
its bus cycle.
When the bus master no longer requires the Multibus
it will have to inactivate the HOLD signal. The arbiter
interprets the Multibus access as a single bus cycle
which is terminated by HOLD going inactive (lOW).
Thus the arbiter will not release the Multibus to any
other bus master during a bus access cycle.

Processor Cycle Definition
Any iAPX 286 system which gains access to the
Multibus through the 82289 Bus Arbiter uses an
internal clock which is one half the frequency of the
system clock (ClK) (see figure 3). Knowledge ofthe
phase of the local bus master internal clock is
required for proper 82289 control of the iAPX 286
interface to Multibus. The local bus master informs
the bus arbiter of its internal clock p'hase when it
asserts the status signals. The 80286 SO# and S1#
status signals are always first asserted in phase 1 of
the local bus master's internal clock.

RE~DY

NEW ,CYCLE

Figure 4: 82289

Pr~essor, Bus

States

231095-002

82289
Bus Cycle Definition
The S1# and SO# status inputs are sampled by the
82289 on the falling edge of elK and signal the start
of a bus cycle by going active (lOW). The T s bus
state is defined to be the two elK cycles during
which either S1# or SO# is active (see figure 5).
When either S1# or SO# is sampled lOW, the next
elK cycle is considered the second phase of the
associated processor clock cycle.
The arbiter enters the T c bus state after the T s state.
The shortest bus cycle may have one T s state and
one Testate. longer bus cycles are formed by
repeating Tc states. A repeated Tc bus state is
called a wait state.

The READY# input determines whether the current
T c bus state is to be repeated. The READY# input
has the same timing and effect for all bus cycles.
READY# is sampled at the end of each Tc bus state
to see if it is active. If sampled HIGH, the T c bus
state is repeated. This is called inserting a wait state.
When READY# is sampled lOW, the current bus
cycle is terminated. Note that the bus arbiter may
enter the T s bus state directly from T c if the status
lines are sampled active (l.:OW) at the next falling
edge of elK (see Figure 5). If neither of the status
lines are sample.d active at that time the 82289 will
enter the TI bus state. The TI bus state will be
repeated until the status inputs are sampled active.

VCH

ClK
VCl

51.SO

VIH - - - " "

J

FROM

cpu

Vil

!!I!I!ll!11J
Figure 5: 80286 Bus Cycle Definition (without wait states)

Arbitration Between Bus Masters
The Multibus protocol allows multiple processing
elements to compete with each other to access
common system resources. Since the local 80286
processor does not have exclusive use of the system
bus, if the Multibus is "BUSY" the 80286 processor
will have to wait before it can access the system bus.
The 82289 Bus Arbiter provides an integrated
solution for controlling access to a mUlti-master
system bus. The bus arbiter allows both higher and
lower priority bus masters to acquire the system bus
depending on which release mode is used. In
general, higher priority masters obtain the bus
immediately after any lower priority master completes its present transfer cycle. lower priority bus
masters obtain the bus when a higher priority
master is not accessing the system bus or the
proper surrender conditions exist. The 82289 handles

4-123

this arbitration in a manner completely transparent
to the bus master (e.g. 80286 processor).
At the end of each transfer, the arbiter may retain or
release the system bus. This decision is controlled
by the processor state, bus arbitration inputs and
arbiter strapping options. (See Releasing The
Multibus, ahead).

Priority Resolving Techniques
Some means of resolving priority between bus
masters requesting the multi-master bus simultaneously must be provided. The 82289 Bus Arbiter
supports parallel, serial, and rotating system bus
priority resolving techniques. All of these techniques
are based on the concept that at a given time, one
bus master will have priority above all the others.

231095-002

82289

BCLK ________________________- '

o

o
o
o

HIGHER PRIORITY BUS ARBITER REQUESTS THE MULTI-MASTER SYSTEM BUS.
ATTAINS PRIORITY. (DOES NOT YET OWN BUS)
LOWER PRIORITY BUS ARBITER RELEASES BUSY.
HIGHER PRIORITY BUS ARBITER THEN ACQUIRES THE BUS AND PULLS iiiJSVLOW.

Figure 6: Bus Exchange Timing For The Multibus
An individual arbiter is the highest priority arbiter
requesting the Multibus when its BPRN# input is
asserted (LOW). The highest priority· requesting
arbiter cannot immediately seize the system bus. It
must wait until the present bus transaction is
completed. Upon completing itscurrenttransaction
the present bus owner surrenders the bus by releasing BUSY#.

The 82289 bus Arbiter does not generate a separate
BREQ# for each bus cycle. Instead the 82289
generates BREQ# when it requests the bus and
holds BREQ# active during the time that it has
possession of the bus. Note that all multi-master
system bus requests (via BREQ#) are synchronized
to the system bus clock (BCLK#).
Parallel Priority Resolving Technique

BUSY# is an active-low 'Wired-OR' Multibus signal
which goes to every bus arbiter on the system bus.
When BUSY# goes inactive, the arbiter which has
requested the system bus, and presently has bus
priority (BPRN# LOW), seizes the bus by pullIng
BUSY# LOW (See waveform in Figure 6).
The generation of a multi-master bus request
(BREQ#) is controlled by the type of bus cycle and
the SYSB/RESB# input. Whenever the processor
signals the status for memory read, memory write,
1(0 read, I/O write or interrupt acknowledge cycle,
and SYSB/RESB# is HIGH at the end of T s, a bus
request is generated.
When the status inputs indicate'an interrupt acknowledge bus cycle, tne arbiter allows external logic to
decide (through the SYSB/RESB# input) whether
the interrupt acknowledge cycle should use the
Multibus.

The parallel priority resolving technique requires a.
separate bus request line (BREQ#) for each arbiter
on the multi-master system bus (see Figure 8). Each
BREQ# line enters a priority encoder which generates the binary address of the highest priority
BREQ# line currently active. The binary address is
decoded to select the BPRN# line corresponding to
the highest priority arbiter requesting the bus. In a
parallel schem'e, the BPRO# output is not used.
The arbiter receiving priority (BPRN# LOW) then
allows its associated bus master onto the multimaster system bus as soon as the bus becomes
available (i.e., the bus is no longer busy). Any
number of bus masters may be acomodated in this
way, limited only by the complexity of the external
priority resolving circuitry. SU,ch circuitry must
resolve the priority within one BCLK# period.

Serial Priority Resolving Technique
Figure 7 shows how SYSB/RESB# is repeatedly
sampled until it is sampled HIGH or the bus cycle is
terminated. If the bus cycle is completed (READY#
is sampled LOW) before SYSB/RESB# is sampled
HIGH, the arbiter will not request the Multibus.

The serial priority resolving technique eliminates
the need for the priority circuitry of the parallel
technique by daisy-chaining the bus arbiters together, that is, connecting the higher priority

4-124

231095-002

82289
arbiter's BPRO# output to the BPRN# of the next
lower priority arbiter (see Figure 9). The highest
priority bus arbiter would have its BPRN# tied LOW
in this configuration, signifying to the arbiter that it
always has the highest priority when requesting the
system bus. In a serial scheme, the BREQ# output is
not used.

together in the senal priority is limited by arbiter
BPRN# to BPRO# propagation delay (18 ns). For a
10 MHz Multibus BCLK#, five 82289 Bus Arbiters
may be connected together in senal configuration.

Since arbitration must be resolved within one
BCLK# period the number of arbiters connected

BPRN# to BPRO# delay

Ts

Maximum number of chained-priority devices
BCLK# period

Tc

Tc

=

TC

ClK [

SO#/HOlDoS1# [

Figure 7: Bus Request Timing During an Interrupt Acknowledge Cycle

+vcc

1

4

74148
PRIORITY
ENCODER

74138
~
3T08
DECODER 4

Figure 8: Parallel Priority Resolving Technique

4-125

231095-002

82289

)~

+Vcc

: BUSY

Figure 9:

Connections for Serial Priority Resolving Technique

BPRN#[

~~~.f-'----""f~f-'_ _ _ _ _ __

BPRO#[

~~~'~_-f/F.

BREQ# [

- - - _ _ J / . f - '- - - - _ / . f - '

\>-_ _ _ __

-DT-'Jr------

-----,r·;.--J+-\-\\. .

F_. _ _ _ _

l

THE LOCAL
80286 REQUESTS
THE MULTIBUS

J~

~

THE LOCAL
80286 NO LONGER
NEEDS THE MULTIBU

Note: Events A through F described above.
Figure 10:

Serial Priority Bus Behavior

When using the serial priority resolving scheme, a
higher priority arbiter (for example, arbiter 2, Figure
9) passes priority to the next lower priority arbiter
(arbiter 3) by asserting its BPRO# signal (LOW).
This asserts BPRN# of next arbiter (arbiter 3) as
shown in Figure 10-a & 1(}'b. An arbiter's BPRO# is
asserted if the arbiter has priority (BPRN# is
asserted) but is not accessing or requesting the
system bus (as indicated by BREQ# inactive as
shown in Figure 10-c and 10-e for arbiter 3).
Whenever a higher priority arbiter (arbiter 3) issues
a bus request its BPRO# goes inactive causing the
next lower priority arbiter (arbiter 4) to lose its bus
priority (Figure 10-f). Any arbiter (arbiter 3) will also

bring its BPRO# inactive if its BPRN# goes inactive
(from arbiter 2), thereby passing the loss of bus
priority on to tre lower priority arbiters (e.g. arbiter
4) as shown in Figure 10-d.

Rotating Priority Resolving Technique
The rotating priority resolving technique is similar
to the parallel priority resolving technique except
that priority is dynamically re-assigned. The priority
encoder is replaced by a more complex circuit
which rotates priority between requesting arbiters,
thus allowing each arbiter an equal chance to use
the multi-master system bus over a given period of
time.

I

( 4-126

231095-002

82289
Selecting the Appropriate Priority
Resolving Technique
The choice of a priority resolving technique involves
a tradeoff between external logic complexity and
ease of Multibus access for the different bus masters in the system. The rotating priority resolving
technique requires a substantial amount of external
logic, but guarantees all the bus masters an equal
opportunity to access the system bus. The serial
priority resolving technique uses no external logic
but has fixed bus master priority levels and can
accommodate only a limited number of bus arbiters.
The parallel priority resolving technique is in general
a compromise between the other two techniques.
(For example parallel priority configuration in Fig. 8
allows up to eight arbiters to be present on the
Multibus, with fixed priority levels, while not requiring a large amount of complex external logic to
implement.)

Releasing the Multibus
Following a data transfer cycle on the Multibus, the
82289 Bus Arbiter can either retain control of the
system bus or release the bus for use by some other
bus master. The 82289 can operate in one of three
modes, defining different conditions under which
the arbiter relinquishes control of the multi-master
system bus. These release modes are described in
Table 2.

Release
Mode

Conditions under which the Bus
Arbiter releases the system bus
(unless cycles are LOCKed)

the arbiter is forced off of the bus by the loss of
BPRN# (Mode 2 or 3), or by a common bus request
when the CBRQ# input is enabled by the CBQLCK#
input (Mode 2).
CBRQ# can save the bus exchange overhead in
many cases. If CBRQ# is high, it indicates to the bus
master that no other master is requesting the bus
and therefore the present bus master can retain the
bus. Without CBRQ#, only BPRN# indicates whether
or not another master IS requesting the bus and, that
only if the other master is of higher priority. Between
the master's bus transfer cycles, in order to allow
lower priority masters to take the bus if they need it,
the master must give up the bus. At the start of the
master's next transfer cycle, the bus must be
regained. If no other master has the bus, this can
take approximately two BCLK# periods. To avoid
this overhead of unnecessarily giving up and regaining the bus when no other masters need it, CBRQ#
is extremely useful. Any master that wants but does
not have the bus, must assert CBRQ# (LOW). If
CBRQ# line is not asserted the bus does not haveto
be released, thereby eliminating the delay of
regaining the bus at the start of the next cycle.
The LOQK# input to the arbiter can be used to override any of the conditions shown in Table 2. While
LOCK# is asserted, the arbiter will not surrender
control of the Multibus to any other requesting arbiter. Note that the arbiter will surrender the Multibus
(synchronous to BCLK#) either in response to
RESET or INIT# signals independent of the current
release mode or the state of the arbiter inputs.

Mode 1

The Bus Arbiter always releases the
bus at the end of each transfer cycle

The three bus release modes have the same operation when supporting either the 80286 processor or
some other bus master.

Mode 2

The Bus Arbiter retains the bus until:

Selecting the Appropriate Release Mode

• a higher-priority bus master requests the bus, driving BPRN#
HIGH

The choice of which release mode to use may affect
the bus utilization of the individual subsystems, and
the system as a whole. Mode dependent performance variations are due to the bus acquisition/
release overhead. The effect of these acquire and
release times on system bus efficiency is illustrated
in Figure 11.

• a lower-priority bus master requests
the bus by pulling CBRQ# LOW
Mode 3

The Bus Arbiter retains the bus until:
• a higher-priority bus master requests the bus, driving BPRN#
HIGH. (CBRQ# LOW ignored)

Table 2:

82289 Release Modes

If the arbiter was programmed to operate in the
Always Release mode (Mode 1) during the previous
reset, it will surrender the Multibus after each
complete transfer cycle. If the arbiter is not in the
Always Release mode, it will not surrender the bus
until the local 80286 processor enters a halt state,

An isolated transfer on the multi-master system bus
is depicted in Figure 11-a. Figure 11-b shows utilization for the bus arbiter operating in Mode 1. The
arbiter must request and release the system bus for
each transfer cycle. Lower priority arbiters have
easy access to the system bus, but overall bus efficiency is low. Bus utilization for a bus arbiter operating in Mode 2 or 3 is shown in Figure 11-c. In this
situation the arbiter acquires the bus once for a
sequence of transfers. The arbiter retains the bus
until forced off by another bus master's request as
defined in Table 2

4-127

231095-002

inter

82289

A,

B,

C,

Figure 11:

Effects of Bus Contention on Bus Efficiency

The three release modes of the 82289 allow the
designer to optimize the system use of the Multibus,

Configuring the 82289 Release Mode
The 82289 Bus Arbiter can be configured in any of
its three bus release modes without additional

hardware, the 82289 can also be configured to
switch between Mode 2 and Mode 3 under software
control of the 80286 processor, requiring that a
parallel port or addressable latch be used to drive
the ALWAYS#/CBQLCK# input pin of the 82289 (see
Figure 12),

822889

822889

RESET ---tRESET

RESET----IRESET

vcc _____

~/~

MODE 2

MODEl

822889
822889

RESET-_-----I

RESET

$

MODE3

DATA

PARALLEL
1/0 OR
ADDRESSABLE
LATCH

D

C

' " - -......C.t----MULTIBUS BCLK

ENABLE

SELECTABLE BETWEEN MODES 2 AND 3

* WHEN HIGH THE 82289 IS IN MODE 2;
WHEN LOW THE 82289 IS IN MODE 3,

Figure 12:

82289 Release Mode Configurations
4-128

231095-002

82289

Asserting the LOCK# Signal
Independent of the particular release mode of the
82289 Bus Arbiter, the 80286 processor can assert a
lOCK# signal synchronously to ClK to prevent the
arbiter from releasing the Multibus. This softwarecontrolled lOCK# signal prevents the 82289 from
surrendering the system bus to any other bus master, whether that bus master is of higher or lower
priority. The lOCK# signal is typically used for
implementing software semaphores for shared resources or for' critical processes that must run in
real-time.
The 82289 llOCK# output is the Multibus signal
asserted during all bus cycles which are locked
together. The llOCK# is set or reset depending on
processor lOCK# at the end of the Ts cycle. The
llOCK# will delay going inactive until the termination of the current transfer cycle.
The 82289 will continue to assert the llOCK# signal, retaining. control ofthe Multibus, until the end of
the first 'unlOCKed' 80286 bus cycle (80286 disables its lOCK# output on the last bus cycle indicating that no future locked cycles are needed). While
the lOCK# signal will force the arbiter presently in
control to hold the system bus, it cannot force
another arbiter to surrender the bus any earlier than
it normally would.
The llOCK# signal from the 82289 must be con-

nected to a tri-state buffer in orderto drive the Multibus lOCK# signal. This tri-state buffer should be
enabled by the AEN# signal from the arbiter going
active.

82289 Reset and Initialization
The 82289 Bus Arbiter provides the RESET and
INIT# pins for initialization. RESET is a ClK synchronous signal from the 80286 processor and
INIT# is an asynchronous signal on the multimaster system bus. By having RESET pin high or
INIT# pin low, the BREQ#, BUSY#, and AEN# output
pins will all be cleared and become inactive. RESET
will also clear the llOCK# signal. Unlike RESET,
INIT# will not clear any pending bus request; the
bus request would be asserted after the INIT# signal
goes inactive.
~

I

Note that when the 82289 is initialized by the RESET
input it does not wait until the end of the current bus
cycle to reset. Any bus cycle in process when
RESET goes active will be aborted by the arbiter.
Although the INIT# signal will also interrupt an
active bus cycle, the arbiter can request the Multibus and complete the bus cycle when INIT# goes
inactive.
As mentioned in the Table 1 Pin Description and
Figure 12, the functions of the SO#/HOlD pin and
the release mode (AlWAYS#/CBQlCK# pin) are
programmed at the falling edge of RESET

4-129

231095-002

82289

Ycc

Ycc
XACKI

"'0
DECODE

RELEASE
MODE

"'0
.'"

SYS8IAESB

am

RESET

INIT
BREO

Al.WAYS/
CIOLeK

.,

~

1

.

-

ADDRESS

SO/HOLD

LOcK

Am

MIlO

RESET

INITIf

.

.......

imi
iiiiIV

eBRO

CLK

ocue.

.....
CBRCH

;-

....

uaakLOCK
BU8ARBlTER

1BUS

ARBITRATION

~itttF1~~~~i~"MDAY .
Ycc

CENJAE~B IOi!ii

-".,
iiWI'C
iliiiC
I/lWE

10kn

.,

.,

SO

PCLK

eLX

eLK

EA

ALE

Mct!
DEN

READY

READY

AiiDv
82214

2OKO

..'"

RESET

ARDYEN

GE~'f~~R

:

!
!
I

!

II!iDv

4+

1r

I"'i-.;." ~MI

~ L;>2::===~!~:-~-::-;--:-:-:-~-;::-:--:--:-j-i-H~'~':' ~
II 'I

t-

MilO

HOLD

COOlINTA

I

....

""'!

I --++t+t-{.I\..I.-.:..~
H-'

!

iii:i'W

~~

INTA:

PlACK

p..

STB

=III

ADDRESS BUS

Au-Aotl:=::!:!:::::~:::;;~~:>~ Jf~

tt' _

L-------------t+..~ ...."t--i---..--.LH+
! ! ! I rt------,-tt1. !I:::::
I ...-_.....

A,

-

1111.

umR -

elK

I

, _____________ ..1
:

I

I- r-

l-

CMDLY

SRDY

SRDY!!N

,

~t~=tS=~~l--'NTERRUPTACKNowL£Dal!'

UDS BUS
CONTROLLER

we

Vee

MEMORY WRITI'

liD READ' AD.
110 WRiTe'

=

I

tNT

"Iea
f.- CHIP SELECT

iNTi

~
iT I~~=====t:
SP EN
! : ! ! ! : I i r-- J : I
°0.°,5
:* [
--..
! ! ! ! ! ! ! ! ! f-;:. J
i
~ Do·~
r_iiJ_l_i_l..i_!_J_l_~'________ ____ J
!
PRO'=SOR
-----I
. _ -;-f

:

PEREO

:

CAP

=="
I2I8A

:

L_~

rJ'::I~=

____ ~__ ~ _____ ~ _____J

~-

..-......

r-

~

I

= <:::::>

-

DATA.US

Schematic 1: TypicallAPX 286 Subsystem MULTIBUS Interface

4-130

231095-002

82289
ABSOLUTE MAXIMUM RATINGS·
"Notice: Stresses above those listed under ':4bsolute
Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

Ambient Temperature
Under Bias .................•... O°C to 70°C
Storage Temperature .......... -65°C to +150°C
Voltage on Any Pin With
Respect to GND ., ............... -0.5V to +7V
Power Dissipation ...................... 1 Watt

Electrical Characteristics and Waveforms
D.C. Characteristics

(TA = 0° to 70°C, Vee = 5V ± 5%)
Preliminary

Symbol

Parameter

Min.

Max.

Units

-0.5

.8

V

Test Conditions

VIL

Input low Voltage

VIH

Input High Voltage

2.0

Vee + 0.5

V

VILe

ClK Input low Voltage

-0.5

.6

V

VIHe

ClK Input High Voltage

3.8

Vee + 1.0

V

VOL

Output low Voltage:
BUSY#, CBRQ#
BPRO#,BREQ#,AEN#
llOCK#

.45
.45
.45

V
V
V

VOH

Output High Voltage

IlA
mA

0.45V:O;; VIN :0;; Vee
OV:5; VIN < 0.45V
0.45V:O;; VOUT:O;; Vee

2.4

V

III

Input leakage Current

±10
±1

ILO

Output leakage Current

±10

IlA

120

mA

Icc

Power Supply Current

CeLK

ClK, BClK# Input Capacitance

12

pF

CIN

Input Capacitance

10

pF

Co

Input/Output Capacitance

20

pF

4-131

IOL =32mA
IOL = 16mA
IOL =5mA
IOH

=400llA

=1 MHz
=1 MHz
Fe =1 MHz
Fe

Fe

231095-002

82289
,(,TA =DOC to 70°C, Vee =5V ± 5%)
ACtimings are referenced to 0 8V and 2,OV points of signals as Illustrated in datasheet waveforms, unless
otherwise noted,

A.C. Characteristics

Sym

Parameter

Preliminary
6MHz

Preliminary
8MHz

Min.

Max.

Min.

Max.

Unit

83

t5+
50

62

t5+
50

ns

Test
Conditions

Shown
in
Figure

at 1,0 V

13

1

ClK Cycle Period

2

ClK low Time

20

225

15

230

ns

3

ClK High Time

25

230

20

235

ns

at 36 V

13

4

CLiS Rise/Fail Time

10

hS

10 to 3 6 V

13

5

BClK# Cycle Time

100

00

ns

13

6

BClK# High/low Time

30

30

ns

13

10
100

oc

13

7

SO#/HOlD, S1#, M/IO# Setup

28

22

ns

13

8

SO#/HOLD, S1#, M/IO# Hold

1

1

ns

13

9

READY# Setup

50

38

ns

13

10

READY# Hold Time

35

25

ns

13

11

LOCK#, SYSB/RESB# Setup Time

28

20

ns

13, 18

12

LOCK#, SYSB/RESB# Hold Time

1

1

ns

13, 18

13

RESET Setup Time

28

20

ns

19

14

RESET Hold Time

1

1

ns

19

15

RESET ACTIVE Pulse Width

16

16

CLKs

16

INIT# Setup Time

45

45

ns

Note 9

20

Note 9

20

17

j-----.

INIT# Hold Time

.

,

19

1

1

flS

3(t1)
+3(t14)

3(t1)
+3(t14)

ns

20

20

ns

13, 15, 21

1

1

ns

13,15,21

-~--~~-.--.,---

18

INIT# Active Pulse Width

19

BUSY#, BPRN#, CBRQ#,
CBQLCK#/AlWAYS# Setup
to BCLK# (or to RESET)

20

BUSY#, BPRN#, CBRQ#,
CBQLCK#/ALWAYS# Hold
to BClK# (or to RESET)

,

20

21

BCLK# to BREQ# Delay

30

30

ns

Note 1

22

BCLK# to BPRO# Delay

35

35

ns

Note 2

17

23

BPRN# to BPRO# Delay

25

25

ns

Note 2

17

24

BClK# to BUSY# Active Delay

25

BCLK# to BUSY# Float Delay

26
27

13, 14

60

ns

Note 3

13

35

35

ns

Note 4

13, 14

BCLK# to CBRQ# Active Delay

55

55

'ns

Note 5

13

BCLK# to CBRQ# Float Delay

35

35

ns

Note 4

13, 20

1

60

1

28

BCLK to AEN# Active Delay

1

25

1

25

ns

Note 6

13

29

ClK to AEN# Inactive Delay

3

25

3

25

ns

Note 6

13, 14

30

CLK to LLOCK# Delay

20

20

ns

Note 7

18

31

RESET to LLOCK# Delay

35

35

ns

Note 7

19

32

ClKto BClK# Setup Time

ns

Note 8

13, 16,20

NOTES:
NOTE 1.
NOTE 2
NOTE 3
NOTE 4
NOTE 5
NOTE 6
NOTE?
NOTES

NOTE 9

38

38

BREQ# load C L = 60pF
BPRO# load CL = 60pF
BUSY# load CL = 300pF
Float condition occurs when output current IS less that 1LO

In

magnitude

CBRQ# load C L = 300pF
AEN# load CL = 150pF
llOCK# load CL = 60pF
In actual use, ClK and BClK# are usually asynchronous to each other However, for component tesllng
purposes, this specification IS reqUIred to assure signal recognition at specific ClK and BClK# edges
INIT# IS asynchronous to ClK and to BCLK# However for component tesllng purposes, this specification IS
required to assure signal recognition at specific elK and BCLK# edges

4-132

231095-002

inter

82289

4.0V
(2.4V)

CLKINPUT
(BCLK # INPUT)

NOTE 10: AC Drive and Measurement Points - ClK Input (BClK# Input)

4.0V
(2.4V)

CLKINPUT
(BCLK# INPUT)

-+_'-_____..J

O.4SV - - - - -_ _ _
(O.4SV)

2.4V

OTHER
DEVICE
INPUT

tDELAY

-----I

2.0V

DEVICE
OUTPUT

O.SV

NOTE 11: AC Setup, Hold and Delay Time Measurement - General
DEVICE
OUTPUT

NOTE 12: AC Test loading on Outputs

4-133

231095-002

inter

82289

Wavefonns

clock period in which an input synchronous to one
clock will cause a response synchronous to the
other clock depends on the relative phase and
frequency of ClK and BClK# at the time the inputis
sensed.
.

The waveforms (Figure 13-21) show the timing
relationships of the inputs and the outputs and do
not show all possible transitions of all signals in all
modes. Instead, all signal timing relationships are
shown via the general cases. Special cases are
shown when needed.

One strict relation between ClK and BClK# must
be maintained for proper Multibus arbitration. If the
ClK period is too long relative to BClK# period (t1
greater than t5 + SOns), another arbiter could gain
control of the system bus before this arbiter has
released AEN# synchronous to its ClK. This situation arises since the release of AEN# is synch ronous
to the next falling ClK edge after the processor
cycle ends but the release of BREQ# and BUSY# is
synchronous to the next falling BClK# edge after
the processor cycle ends. In practice, any ClK
frequency greater than 6.66MHz (ie. 80286 processor
speeds greater than 3.33MHz) will avoid conflict
with a 10MHz BClK#. Therefore all 80286 speed
selections are Multibus compatible.

To find the timing specification for a signal transition
in a particular mode, first look for a special case in
the waveforms. If no special case applies, then use a
timing specification for the same or related function
in another mode.
The 82289 Bus Arbiter serves as an interface
between the iAPX 286 subsystem which operates
synchronous to the ClK signal and Multibus which
operates synchronous to BClK# signal. ClK and
BClK# generally operate asynchronously to each
other and at different frequencies. Thus, the exact

Ts

<1>1
ClK

[

SO#/HOloeS1#

[

M/IO#

[

REAOY#

[

lOCK#,
SYSB/RESB#

[

BClK#

[

BREQ#

[

BPRN#

[

BUSY#

[

CBRQ#

[

AEN#

[

Tc

Tc

<1>2

<1>1

<1>2

<1>1

Tc

<1>2

<1>1

<1>2

<1>1.

<1>2

<1>1

'ONlY FOR 82289 TEST PURPOSES

Figure 13:

Multibus Acquisition and Always-Release Operation

4-134

231095-002

inter

82289

TS

TC

Tc

Ts

TC

CLK [

SO#/I:tOLDeS1# [

M/IO#

[7Zl2)C===:t~?Zl2?ZZZrzz~W7Zl2?Z22?Zl2Cll2~x:::=~=:::t:J(~~7Zl27Zl2tzl2?Zl2~

READY#

[ZZZ;m7Zl2?lZ.1?lZ.1~cz?z?ZZ2i7Zl27T-I~~~_-4-....J.qzz~m~7Zl2?Z22?Zl2'1lJ"-I"""\'iZ:;

SYSB/~~~~:' [?Zl2?Zl2?ZZZwrl.....,~?Zl2~~WW7Zl2?Z22?Z22C4?2?Zl2?ZZZ~7Zl2~?Z22?Z22?Z22?Zl2:zz~W~
BCLK# [

BPRN#

[~?Zl2?Zl2?Zl2:zz:zz~~-~~?Z22?Z22?Z22?Zl2?Zl2:zz:zzW~?Z22?Z22?Z22?Zl2?Zl2:zzWW7Zl2~

BUSY#

[-------------------1-+-'

BREQ#

[-------------------1-+-'

AEN# [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~

·ONLY FOR 82289 TEST PURPOSES

Figure 14:

Multibus Release due to BPRN# Inactive

4-135

231095-002

82289

T5
<1>1
CLK

[

SO#/HOLoeS1#

[

M/IO#

[

REAOY#

[

LOCK#,
SYSB/RESB#

[

BCLK#

[

BPRN#

[

CBRO#

[

CRQLCK#

[

BREQ#

[

BUSY#

[

AEN#

[

TC
<1>2

<1>1

Tc
<1>2

<1>1

T5
<1>2

<1>1

Tc
<1>2

<1>1

'ONLY FOR 82289 TEST PURPOSES

Figure 15:

Multibus Release due to CBRQ# Active

4-136

231095-002

inter

82289

T8

4>1

Tc

4>2

TC

Tc

4>1

4>2

4>1

4>2

4>1

4>2

4>1

4>2

ClK [

SO#/HOlDeS1# [

BClK# [

BREQ# [

·ONlY FOR 82289 TEST PURPOSES

Figure 16: Multibus Acquisition During 80286 INTA Cycles

'f

,r/

BREQ# [
THE lOCAL
80286 REQUESTS
THE MUlTIBUS

THE lOCAL
80286 NO LONGER
NEEDS THE MUlTIBUS

Figure 17: BPRN# to BPRO# Timing Relationship

4-137

231095-002

inter

82289

TS

4>1

TS

TC

4>2

4>1

4>2

4>1

Tc

4>2

4>1

4>2

4>1

4>2

CLK [

lLOCK# [
(FROM 82289)

Figure 18: 80286 LOCK# and 82289 LLOCK# Relationship

Tx

ClK

.c

RESET

[

AEN#

[

BCLK#

[

BUSY#

[

BREQ#

[

4>2

4>1

<1>2

4>1

4>2

<1>1

<1>2

4>1

CBRQI! [

lLOCKII [
·FOR 82289.TEST PURPOSES ONLY

Figure 19: RESET Active Pulse

4-138

231095-002

82289

ClK [

INIT# [

AEN#

[ZZZZZZZZZZZZ~~~~~~~r--------------------t---------

BClK# [

BUSY#

[ZZ~~~~~~~ZZZZZZZZ~~r----------------------------

BREQ#

[ZZ~~~ZZ~ZZZZ~~~~~~r----------------------------

CBRO# [

llOCK# [

~

WliI///II//$)/;///)//J///II/I///II////Ii//I@

ZI!I////)IiII//)//(I//I//)IiI/(@/jllOCK# IS UNAFFECTED BY INIT#7I/I/I///;//)//;IIiII)IiI/IJ;jJjjffi
"FOR 82289 TEST PURPOSES ONLY

Figure 20:

Figure 21:

INIT# Active Pulse

Programming the Always-Release/Common-Bus-Request-Release Option

4-139

231095-002

inter
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