1985_Linear_Integrated_Circuit_Handbook 1985 Linear Integrated Circuit Handbook
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SEPTEMBER 1985
LINEAR
INTEGRATED
CIRCUIT
HANDBOOK
.
L=~~ , ' ~1
~.~ ==-J;.___
r
L
165" 370 8
II U Oll 460J
_ _ _. . - - - _. .
...
LINEAR
INTEGRATED
CIRCUIT
HANDBOOK
PLE55EY
Semiconductors
1
©The Plessey Company pic 1985
Publication No. P.S. 1973 October 1985
This publication is issued to provide outline information only and (unless specifically agreed to the contrary by the
Company in writing) is not to be reproduced or to form part of any order or contract or to be regarded as a
representation relating to the products or services concerned. Any applications of products shown in this publication
are for illustration purposes only and do not give or imply any licences or rights to use the information for any
purposes whatsoever. It is the responsibility of any person who wishes to use the application information to obtain
any necessary licence for such use. We reserve the right to alter without notice the specification, design, price or
conditions of supply of any product or service. PLESSEY and the Plessey symbol are registered trademarks of
The Plessey Company pic.
2
Contents
Product index
Product list
The quality concept
Screening to 8S9400
Plessey Hi-Rei screening
Semi-custom design
Thermal design
Technical data
Package outlines
Ordering information
Plessey Semiconductors World-Wide
Page
5
7
8
9
10
11
13
15
161
171
173
3
4
Product index
TYPE No.
DESCRIPTION
PAGE
Matched transistors and arrays
SL301L
SL303L
SL360G
SL362C
SL2363C
SL2364C
SL3046C
SL3127C
SL3145C,E
Dual NPN transistor
400MHz triple NPN transistors
High performance NPN transistor arrays
High performance NPN dual transistor arrays
Very high performance transistor array
Very high performance transistor array
General purpose NPN transistor array
High frequency NPN transistor array
1.6GHz high frequency NPN transistor arrays
17
21
25
25
93
93
99
101
105
Radio-communications
SL610C
SL611C
SL612C
SL621C
SL623C
SL640C
SL641C
SL 1613C
SL6270C
SL6310C
SL6440C
SL6601C
SL6652
SL6653
SL6691C
SL6700A
SL6700C
RF amplifier
RF amplifier
IF amplifier
AGC generator
AM detector/AGC amplifier/SSB demodulator
Double balanced modulator
Double balanced modulator
Wideband log IF strip amplifier
Gain controlled preamplifier
Switchable audio amplifier
High level mixer
Low power IF/AF PLL circuit for narrow band FM
Low power IF/AF circuit for FM cellular radio
Low power IF/AF circuit for FM receivers
Monolithic circuit for paging receivers
IF amplifier and AM detector
IF amplifier and AM detector
71
71
71
75
79
81
81
89
109
113
117
121
127
135
141
145
149
Operational amplifiers
SL541B
SL562
TAB1042
TAB1043
High slew rate operational amplifier
Low noise programmable op-amp
Quad programmable operational amplifier
Quad programmable low noise operational amplifier
43
61
153
157
linear RF amplifiers
SL541B
SL550D & G
SL560C
SL561B,C
High slew rate operational amplifier
Low noise wideband amplifier with external gain control
300MHz low noise amplifier
Ultra low noise preamplifiers
43
47
53
57
5
limiting wide band amplifiers
SL521A,B & C
SL523B,C & HB
SL531C
SL532C
SL565C
SL952
SL1521A & C
SL1523C
SL2521EXP
140MHz wideband log amplifier
120MHz dual wideband log amplifier
250MHz true log IF amplifier
Low phase shift limiter
1GHz wideband amplifier
1GHz limiting wideband amplifier
300MHz wideband amplifier
300MHz dual wideband amplifier
1.3GHz dual wideband log amplifier
27
31
35
39
65
69
83
87
95
EXP products are new designs deSignated 'Experimental' but which are, nevertheless, serious
development projects. Details given may, therefore, change without notice and no undertaking is given
or implied as to future availability. Please consult your local Plessey sales office for details of the current
status.
6
Product list
TYPE No.
SL301L
SL303L
SL360G
SL362C
SL521A,B & C
SL523B,C & HB
SL531C
SL532C
SL541B
SL550D & D
SL560C
SL561B,C
SL562
SL565C
SL952
SL610C
SL611C
SL612C
SL621C
SL623C
SL640C
SL641C
SL1521A,C
SL1523C
SL1613C
SL2363C
SL2364C
SL2521EXP
SL3046C
SL3127C
SL3145C,E
SL6270C
SL6310C
SL6440C
SL6601C
SL6652
SL6653
SL6691C
SL6700A
SL6700C
TAB1042
TAB1043
DESCRIPTION
Dual NPN transistors
400MHz triple NPN transistors
High performance NPN dual transistor arrays
High performance. NPN dual transistor arrays
140MHz wideband log amplifier
120MHz dual wideband log amplifier
250MHz true log IF amplifier
Low phase shift limiter
High slew rate operational amplifier
Low noise wideband amplifier with external gain control
300MHz low noise amplifier
Ultra low noise preamplifiers
Low noise programmable op-amp
1GHz wideband amplifier
1GHz limiting wideband amplifier
RF amplifier
RF amplifier
IF amplifier
AGC generator
AM detectorlAGC amplifierlSSB demodulator
Double balanced modulator
Double balanced modulator
300MHz wideband amplifier
300MHz dual wideband amplifier
Wideband log IF strip amplifier
Very high performance transistor array
Very high performance transistor array
1.3GHz dual wideband log amplifier
General purpose NPN transistor array
High frequency NPN transistor array
1.2GHz high frequency NPN transistor arrays
Gain controlled preamplifier
Switchable audio amplifier
High level mixer
Low power IF/AF PLL circuit for narrow band FM
Low power IF/AF circuit for FM cellular radio
Low power IF/AF circuit for FM receivers
Monolithic circuit for paging receivers
IF amplifier and AM detector
IF amplifier and AM detector
Quad programmable operational amplifier
Quad programmable operational amplifier
PAGE
17
21
25
25
27
31
35
39
43
47
53
57
61
65
69
71
71
71
75
79
81
81
83
87
89
93
93
95
99
101
105
109
113
117
121
127
135
141
145
149
153
157
7
The quality concept
In common with most semiconductor manufacturers, Plessey Semiconductors perform
incoming piece parts check, in-line inspections and final electrical tests. However, quality
cannot be inspected into a product; it is only by careful design and evaluation of materials,
parts and processes - followed by strict control and ongoing assessment to ensure that
design requirements are still being met - that quality products will be produced.
In line with this philosophy, all designs conform to standard layout rules (evolved with
performance and reliability in mind), all processes are thoroughly evaluated before
introduction and all new piece part designs and suppliers are investigated before
authorisation for production use.
The same basic system of evaluation, appraisals and checks is used on all products up to
and including device packing for shipment. It is only at this stage that extra operations are
performed for certain customers in terms of lot qualification or release procedure.
By working to common procedures for materials and processes for all types of customers
advantages accrue to all users - the high reliability user gains the advantage of scale hence
improving the confidence factor in the quality achieved whilst the large scale user gains the
benefits associated with basic high reliability design concepts.
Plessey Semiconductors have the following factory approvals. BS9300 and BS9400 (BSI
Approval No. 1053/M).
DEF-STAN 05-21 (Reg. No. 23H POD).
In addition a number of U.S., European and British customers manufacturing electronics
for space have approved our facilities.
8
Screening to BS9400
I PRODUCTION BATCH I
I
I
I
(1) Internal visual
examination
(2) High temperature storage
(3) Rapid change
of temperature
- air
(5) Acceleration
(6) Leak test
(1) Internal visual
examination
(2) High temperatu re storage
(3) Rapid change
of temperature
- air
(5) Acceleration
(6) Leak test
I
CATEGORY S2
CATEGORY S3
CATEGORY S4
SCREENING LEVEL SCREENING LEVEL SCREENING LEVEL
B C D
10% maximum defectives allowed
between electrical
tests (7) and (11).
I
FULL ASSESSMENT
LEVEL
10% maximum defectives allowed
between electrical
tests (7) and (11).
Sample test to group A,B,C and 0 as appropriate
DESPATCH
9
Plessey Hi-Rei screening
The following Screening Procedures are available from Plessey Semiconductors.
CLASS
S
CLASS
B
* STANDARD
PRODUCTS
PRE CAP
VISUAL
FINAL
ELECTRICAL TEST
QUALIFICATION
OR CONFORMANCE
TESTING AS REQUIRED
* Piessey Semiconductors reserve the right to change the Screening Procedure for
Standard Products.
10
Semi-custom design
Plessey Semiconductors' advanced work in the Semi-Custom field enables us to offer our
customers the opportunity to develop their own high performance circuits using our
CLASSIC software. Among the many advantages are:
• CLASSIC is cost effective and user friendly. Prototypes in as little as 3 weeks. Close
coordination with customer throughout design and production process. State-of-the-art
high performance produces • Up to 10044 gates available
DESIGN LOGIC
SIMULATE
USING
CLASSIC
TEST PATIERNS
AND
FAULT COVERAGE
USING CLASSIC
PLAN
LAYOUT
USING AID
NET LIST
Ask for ...
THE
DESIGN
PROCESS
11
Mlcro,ate-C (51-Gate CMOS)
CLA 2000 SERIES
CLA 3000 SERIES
CLA 5000 SERIES
•
Double layer metallisation
•
Double layer metallisation
•
Double layer metallisation
•
5 micron channel length
•
4 micron channel length
•
2 micron channel length
•
Product family:
CLA 21XX 840 Gates
CLA 23XX 1400 Gates
CLA 25XX 2400 Gates
•
•
•
7ns max. prop delay
(2 input NAND fanout of 2
with 2mm track 0-70° C 4.55.5V)
Product family:
CLA 31XX 840 Gates
CLA 33XX 1440 Gates
CLA35XX 2400 Gates
CLA 37XX 4200 Gates
CLA 39XX 6000 Gates
Product family:
CLA 51XX 640 Gates
CLA 52XX 1232 Gates
CLA 53XX 2016 Gates
CLA 54XX 3060 Gates
CLA 55XX 4408 Gates
CLA 56XX 5984 Gates
CLA 58XX 8064 Gates
CLA 59XX 10044 Gates
•
14MHz system clock rate
•
30MHz toggle rate
•
Fully auto-routed
•
5ns max. prop delay
•
20MHz system clock rate
•
50MHz toggle rate
•
2.5ns max. prop delay
•
Fully auto-routed
•
40MHz system clock rate
•
100MHz toggle rate
•
Fully auto-routed
Plessey Megacell
™
Now there's a VlSI design system available that's perfect for solving your Application
Specific Integrated Circuit (ASIC) problems. It's PLESSEY MEGACELL - a complete set of
advanced computer-aided engineering and design tools coupled with an advanced CMOS
process for implementing VlSI integrated circuits in the system design environment.
PLESSEY MEGACELL redefines semicustom integrated circuit design. It allows system
engineers to design complex circuits with a high level of confidence of first time success in
silicon - thanks to one of the best simulation facilities available in the world. This greatly
reduces time to market, eliminating the many prototyping iterations that are all too common
now in VlSI design.
PLESSEY MEGACELL is just about as close as you can get to achieving hand-crafted
results short of full custom itself. System engineers can directly create their designs using the
advanced layout and routing tools provided - without the aid of integrated circuit designers.
So none of the system designers' application expertise is ever lost in transition, while chips of
the smallest size and lowest production cost are regularly achieved.
Supporting the PLESSEY MEGACELL design capability is one of the most advanced
CMOS processes available. It uses a 2-micron geometry capable of providing performance
comparable with advanced Schottky TTL, with clock speeds to 40MHz and toggle rates of
1OOMHz achievable. And Plessey has established a 200,000 square foot dedicated processing
facility to guarantee the manufacturing capacity required by even the most aggressive
volume considerations.
PLESSEY MEGACELL is truly the gateway to the future - custom VlSI performance, with
confidence of first time success and fast time to market. And it's going to stay that way - with
Plessey's commitment to add future capabilities for high-speed ECl processes, 1 micron and
submicron CMOS processes, and advanced analog capabilities.
12
Thermal design
The temperature of any semiconductor device has an important effect upon its long term
reliability. For this reason, it is important to minimise the chip temperature; and in any case,
the maximum junction temperature should not be exceeded.
Electrical power dissipated in any device is a source of heat. How quickly this heat can be
dissipated is directly related to the rise in chip temperature: ifthe heat can only escape slowly,
then the chip temperature will rise further than if the heat can escape quickly. To use an
electrical analogy: energy from a constant voltage source can be drawn much faster by using
a low resistance load than by using a high resistance load.
The thermal resistance to the flow of heat from the semiconductor junction to the ambient
temperature air surrounding the package is made up of several elements. These are the
thermal resistance of the junction-to-case, case-to-heatsink and heatsink-to-ambient
interfaces. Of course, where no heatsink is used, the case-to-ambient thermal resistance is
used.
These thermal resistances may be represented as
= Bjc + Bch + Bha
whereBja is thermal resistance junction-to-ambient ° C/W
Bjc is thermal resistance junction-to-case ° C/W
Bch is thermal resistance case-to-heatsink ° C/W
Bhais thermal resistance heatsink-to-ambient ° C/W
Bja
The temperature of the junction is also dependent upon the amount of power dissipated in
the device - so the greater the power, the greater the temperature.
Just as Ohm's Law is applied in an electrical circuit, a similar relationship is applicable to
heatsinks.
=
Tj
Tj
=
T amb =
Po =
T amb + Po (8ja)
junction temperature
ambient temperature
dissipated power
From this equation, junction temperature may be calculated, as in the following examples.
Example 1
A device is to be used at an ambient temperature of +50°C.8jafortheDG14packagewith a
chip of approximately 1mm sq is 107° e/W. Assuming the datasheet for the device gives Po =
330mW and Tj max = 175° C.
Tj = T amb + Po 8ja
= 50 + (0.33 x 107)
= 85.31° C (typ.)
Where operation in a higher ambient temperature is necessary, the maximum junction
temperature can easily be exceeded unless suitable measures are taken:
13
Thermal design (cont'd)
Example 2
A device with Tamb max. = +175° C is to be used at an ambient temperature of +150° C.
Again,8ja = 107°C/W, PD = 330mW and Tj max. = +175°C.
Tj
= 150
+ (0.33 x 107)
= + 185.3° C (typ.)
This clearly exceeds the maximum permissible junction temperature and therefore some
means of decreasing the junction-to-ambient thermal resistance is required.
As stated earlier, 8ja is the sum of the individual thermal resistances; of these, 8jc is fixed by
the design of device and package and so only the case-to-ambient thermal resistance, 8ca, can
be reduced.
If 8ca, and therefore 8ja, is reduced by the use of a suitable heatsink, then the maximum T amb
can be increased:
Example 3
Assume that an IERC LlC14A2U dissipator and DC000080B retainer are used. This device
is rated as providing a 8ja of 55° C/w for the DG 14 package. Using th is heatsink with the device
operated as in Example 2 would result in a junction temperature given by:
Tj = 150 + (0.33 x 55)
= 168°C
Nevertheless, it should be noted that these calculations are not necessarily exact. This is
because factors such as 8jc may vary from device type to device type, and the efficacy of the
heatsink may vary according to the air movement in the equipment.
In addition, the assumption has been made that chip temperature and junction temperature
are the same thing. This is not strictly so, as not only can hot spots occur on the chip, but the
thermal conductivity of silicon is a variable with temperature, and thus the 8jc is in fact a
function of chip temperature. Nevertheless, the method outlined above is a practical method
which will give adequate answers for the design of equipment.
It is possible to improve the dissipating capability of the package by the use of heat
dissipating bars under the package, and various proprietary items exist for this purpose.
Under certain circumstances, forced air cooling can become necessary, and although the
simple approach outlined above is useful, more factors must be taken into account.
14
Technical data
15
16
SL301L
er.!I!.!.~!!
_____________
SL301L
400MHz DUAL NPN TRANSISTOR
The SL301 L contains dual monolithic NPN transistors with
close parameter matching and high h.
FEATURES
•
•
•
•
•
Close VSE Matching<3mV
Close hfe Matching>O.9
Good Frequency Response>400MHz
Good Thermal Tracking
Wide Operating Current Range
eMS
Fig.1 Pin connections
APPLICATIONS
•
•
•
•
Differential Amplifier to Very High Frequencies
Comparators
Current Sources
Instrumentation
ABSOLUTE MAXIMUM RATINGS
All electrical ratings apply to individual transistors.
Thermal ratings apply to the total package.
The absolute maximum ratings are limiting values above
which operating life may be shortened or specified parameters may be degraded.
The isolation pin (substrate) must be connected to the
most negative point of the circuit to maintain electrical
isolation between transistors.
Storage temperature -55 0 C to +1750 C
Maximum junction temperature +175°C
Thermal resistance
Chip-to-case 265° CIW (see Note)
Chip-to-ambient 425° C/W
VeB = 20V VEB = 4.0V VeER = 20V (see Fig.7)
VeE = 12V Vel = 25V Ie = 20mA
NOTE:
These figures are worst case, assuming all the power is
dissipated in one transistor. If the power is equally shared
between the two transistors, both thermal resistance figures
can be reduced by 50° C/watt.
17
SL301L
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb
= 22°C ±
2°C
Symbol
Characteristic
Collector base breakdown
Collector emitter breakdown
Collector emitter breakdown
Emitter base leakage current
Emitter base leakage current
Collector isolation breakdown
Forward current transfer ratio
Min.
BVCBO
BVCEO
LVCEO
lEBO
lEBO
BVclo
HFE
Value
Typ.
Max.
20
12
12
25
40
60
50
VCE(SAT)
VBE(SAT)
Collector base leakage current
ICBo
IClo
Collector isolation leakage current
COB
Collector capacitance
Base capacitance
CIB
CCI
Collector isolation capacitance
Transition frequency
fr
0.7
70
100
80
0.36
0.8
400
680
Saturation voltage
=
=
=
=
=
=
=
Ic
10pA
Ic
10pA
Ic
SmA
pA VEB
4V
nA VEB
2V
Ic
10pA
V
VCE
5V, Ic = 100pA
VCE = 5V, Ic = 1mA
VCE = 5V, Ic = 10mA
Ic = 10mA, IB = 1mA
V
Ic = 10mA, IB = 1mA
V
nA VCB = 10V
nA VCI = 10V
VCB = 5V
pF
VSE = OV
pF
pF
VCI = +SV
MHz VCE = SV, Ic = SmA, Freq = 100MHz
V
V
V
1
10
0.6
0.9
10
10
2
4
6
Conditions
Units
Matching
HFE1/HFE2
0.9
0.9
t.VBE
IVBE1 - VBE21
0.45
0.45
2
Temperature coefficient of t. VBE
1.1
1.1
3
3
10
VCE = 5V, Ic =
VCE = SV, Ic =
mV VCE = 5V, Ic =
mV VCE = 5V, Ic =
pV;oC VCE = 5V, Ic =
100pA
1mA
100pA
1mA
100pA
80
2-2
2-0
,-s
1\
\
1\ \
\ \,
40
\ ,,~+'oooc
T,A"'-
'-2
~ r--r---
'-0
o-s
-
Fig. 2 Output capacitance (Cob) v. voltage-
i/
1--
..... 1'
/
(
0
0
a
COLLECTOR-BASE VOLTAGE (VI
18
V
60
lOJ.'A
100J.'A
CURRENT
lmA
lOrnA
lOOmA
Fig. 3 Typical variation of hFE with cOflectorcurrent
SL301L
1000
800
70 0
600
so 0
JV
N
:l:
~
-"
\"
hV
~~~
400
~~
300
r-
VeE! 10V
100
I
~
VeE,SV
"'-
VeE ,2V
VCE!
100
I
sv
I
l"--t--..
'", ...........
.........
I'-['...
IlOO
t--..,J.I'7mVlOC
N:'
0·1 ...... 1'87,","'C
\
VeE'W
500
..........
.........
""- ........... [".. ............ ..........
........
200
100
300
o0'3
Q-7
1'0
7 10
CURRENT (mAl
20
30
'"'"
70
200
-60
-40
-20
0
t20
+40
t60
tlO
tlOO
+120
+140
+160
TEMPEIIATURE (OC'
Fig.4 fTV. col/ector current (f = 100MHz)
Fig. 5 VSE v. temperature
lilA
~
100nA
VCI'SV
VC1"V
r-.
~
~~
0
:9
VCI ,20V
----
20
h V
~~
~V
IOn A
InA
........:: ~
~~
W
--r------
100pA
10pA
o
o
20
40
60
80
100
TEMPERA TURE ('CI
120
Fig. 6 Typical'CIO v. temperature
140
160
100
Ik
10k
lOOk
R (OHMS'
Fig. 7 Relationship between VCER and RSE
19
SL301L
20
FOR MAINTENANCE PURPOSES ONLY NOT RECOMMENDED FOR NEW EQUIPMENT DESIGNS
~~JF~
SL303L
_________________________
SL303L
400MHz TRIPLE NPN TRANSISTORS
The SL303 is a silicon monolithic integrated circuit
comprising three separate transistors, two of which have
closely matched parameters; the third transistor may be used
as, for example, a tail transistor.
,--~-t----o
o---------{
'0
ISOLATlON
TR2
FEATURES
•
•
•
•
Close VBE Matching
High Gain
Good Frequency Response
Excellent Thermal Tracking
CM10
Fig. 1 Circuit diagram
APPLICATIONS
•
•
Differential Amplifier
Comparator
QUICK REFERENCE DATA
•
•
Max voltage
12V to 20V
Operating temperature range - 55°C to
175°C
+
ABSOLUTE MAXIMUM RATINGS
All electrical ratings apply to individual transistors:
thermal ratings apply to total package dissipation.
The isolation pin must always be negative with respect
to the collectors.
No one transistor may dissipate more than 75% of the
total power.
Storage temperature
-55°C to + 175°C
Chip operating temperature + 175°C
Chip-to-ambient thermal resistance:
TO-5 (CM)
425°C/W
Chip-to-case thermal resistance:
see Note
TO-5 (CM)
265°C/W
VCBO
20V
VCEO
12V
VCER
12V to 20V (see Figure 8)
VEBO
4V
VCIO
25V
ICM
20mA
I
NOTE:
These figures are worst case, assuming all the power is
dissipated in one transistor. If the power is equally shared
between the three transistors, both thermal resistance
figures can be reduced by 75° C/watt.
21
SL303L
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = 25°C
Characteristic
Symbol
Min.
BVCBO
BVCEO
lEBO
lEBO
BVclo
HFE
Collector base breakdown
Collector emitter breakdown
Emitter base leakage current
Emitter base leakage current
Collector isolation breakdown
Forward current transfer ratio
VCE(SAT)
VBE(SAT)
Saturation voltage
Base emitter saturation voltage
Collector base leakage current
Collector isolation leakage current
Collector capacitance
Base capacitance
Collector isolation capacitance
Transition frequency
Value
Typ.
20
12
25
30
40
60
50
0.7
400
Conditions
Units
Ic = 10pA
Ic = 5mA
VEB = 4V
VEB = 2V
Ic = 10pA
VCE = 5V, Ic = 10pA
VCE = 5V, Ic = 100pA
VCE = 5V, Ic = 1mA
VCE = 5V, Ic = 10mA
Ic = 10mA, IB = 1mA
V
V
50
70
100
80
0.36
0.8
ICBO
IClo
COB
CIB
CCIO
fT
Max.
1
10
pA
0.6
0.9
V
V
10
10
2
4
6
nA
nA
pF
pF
pF
MHz
680
nA
V
Ic = 10mA, IB = 1mA
VCB = 10V
VCI = 10V
VCB = 5V
VBE = OV
VCI = +5V
VCE = 5V, Ic = 5mA
Matching
TR1 & TR2 only
HFE1/HFE2
0.9
0.9
b.VBE
Input offset voltage
Temperature coefficient
of input offset voltage
24
22
2
a
, 8
'2
1
a
mV
mV
pvrc
= 5V,
= 5V,
= 5V,
= 5V,
= 5V,
Ic = 100pA
Ic = 1mA
Ic = 100pA
Ic = 1mA
Ic = 100pA
1200
\
\~
\\1\.:
\
1000
1\
800
OPcRA"NG REG,ON
\
CASE
1"100·C
~""
,~
------=:
~
't 1\
~
400
::::::--r----
AMB,I-. RA' '. " ' "
200
-20
VOL TAGE I v I
Fig 2 Output capacitance (Cob) v. voltage
RATING
/
600
a
22
VCE
VCE
VCE
VCE
VCE
\
\
14
1.1
1.1
3
3
10
a
+20
60
'""\~
lOa
~
140
18G
220
TEMPERATURE I'C)
Fig. 3 Power dissipation derating curves (TO-5 package)
SL303L
80
800
v
60
,,~
--""
r--i'
600
V
500
V
40
V
h
L ?- ~ " "'"
JV
1\
700
I
~
V
400
~~
....300
\
!
10V
vCE
I
VCE:sv
~CE
I: 2V
VCE :1V
200
20
100
07
lO~A
lOO~A
lmA
lOmA
10
10
7
20
30
70
CURRENT ImA)
lOOmA
CURRENT
Fig. 5 fr v. col/ector current (fr
Fig. 4 Typical variation of hFE with collector current
=
flhr.1 . f
=
100 MHz)
1000
v:::::
y:/-~
IfJA
900
SOD
VCE
, r--.....
~,
.......
700
........-:
~ 5V
1
i'-.... '-... ~IJA
I~OnA
"'-~ '-...i"-..
"'- '-...I'--i'.....
600
O'lmA
500
~ /'
"'mV/'C
,
I'S7rr11foc
........
~V
~~
u
,
InA
VCI =20V
I'-.
400
~~
10nA
VC[:5V
W
Vel:: IV
100pA
300
10pA
200
-60
-40
-20
+20
+40
+60
+so
+100
+120
+140
+1611
o
20
40
TEMPERATURE I'C I
100
120
140
160
Fig. 7 Typicallc/O v. temperature
Fig. 6 V8E v. temperature
20
60
SO
100
TEMPERA T URE I"C)
----
r-....
~
Ik
r--
-----
10k
R
r--
lOOk
(OHMS)
Fig.S Relationship between VeER and RBE
23
SL303L
24
SL360/SL362
SL360G & SL362C
HIGH PERFORMANCE NPN DUAL TRANSISTOR ARRAYS
The SL360G and SL362C are high performance NPN dual
transistor arrays fabricated as monolithic silicon devices.
They feature accurate parameter matching and close
thermal tracking. They have high transition frequencies (typ.
2.2GHz) and low device capacitance. In addition the SL362C
offers good noise performance (1.6dB noise figure at
60MHz).
NC
!OTTOM VIEW
APPLICATIONS
•
•
•
•
Instrumentation
peM Repeaters
Analogue Signal Processing
High Speed Switches - Digital and Analogue
eM8
Fig. 1 Pin connections
FEATURES
•
Accurate Parameter Matching.
•
•
High fr
Low Noise C1.6d8 at 60MHz SL362)
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = 22°C ± 2°C
Characteristic
Symbol
Collector base breakdown
Collector isolation breakdown
Emitter base leakage
Emitter base leakage
Collector emitter breakdown
DC current gain
BVcBo
BVclo
lEBo
lEBo
LVCEO
HFE
Transition frequency
h
Type
Both
Both
SL360/362
SL360
All
SL360
SL362
SL360
SL362
Input offset voltage
Input offset current
Saturation voltage
Noise figure
VBE1 - VBE2
HFE1/HFE2
VCE(SAT)
NF
Collector base capacitance
COB
Collector isolation
capacitance
Emitter base capacitance
CCI
Forward base emitter voltage
Collector base leakage
Collector isolation leakage
CrE
VBE(ON)
ICBo
IClo
SL360
SL362
Both
SL360
SL362
SL360
SL362
SL360
SL362
SL360
SL362
SL360
SL360
SL360
Min.
Value
Typ.
10
16
32
60
Max.
1
1
Units
V
V
j.lA
nA
V
7
30
30
1.6
14
6S
70
2.2
GHz
1.4
2.0
GHz
3
10
5
0.9
1.0
0.25
1.6
mV
mV
1.1
0.6
2.0
V
dB
1
1
pF
pF
pF
pF
pF
pF
V
nA
nA
0.5
1.3
2.3
3.8
0.5
2.1
0.72
Conditions
Ic= 10j.lA
Ic= 10j.lA
VEB= 4V
VEB= 2V
Ic= SmA
VCE= 2V,IE= 5mA
VCE = 2V,IE= 1mA
VCE= 2.SV,IE= 25mA,
f =200MHz
VCE= 5V,IF= 5mA,
f =200MHz
VCE= 2V,IE= 1mA
VCE= 2V,IE= 1mA
VCE= 2V,IE= SmA
IE= 10mA,IB= 1mA
IE = 1mA,Rs= 2000,
f =60MHz
VCB= OV
VCB= OV
VCI =OV
VCI =OV
VBE= OV
VBE= OV
IE = 1mA,VcE= 2V
VCB= 10V
VCI =10V
25
SL360/SL362
I
COLLECTOR
COLLECTOR
'=60 MHz
Rs~
50
--- --,
----V V
NF
CO;
I
I
I
/
~
~
(dB)
I
r--
/'
.,j.
V
__ :;O'02p
EMITTER
ISOLATION
---+ ~~ ~ ~
zooL--
EMITTER
I
Fig.2 Equivalent circuit for SL360, SL362
Ie (mA)
Fig. 3 Typical noise figure emitter current for SL362
I
f=60MHz
\
NF
(dB!
c
~
"I\-
""
So
--
IE=2m~
"-- ~ ~
,/
/
ffi
a:
a:
60
::;)
()
/
a:
:=
lrl
40
::l
o()
:IE
~
---
~
SL362
I'--
20
::;)
:IE
zoo
~
600
JUNCTION TEMPERATURE
Rs ( )
Fig. 4 Typical noise figure v source impedance for SL362
---I
I
--
I
I
I
rC)
Fig.5 Max. continuous col/ector current vs junction temperature
ABSOLUTE MAXIMUM RATINGS
All electrical ratings apply to individual transistors.
Thermal ratings apply to the total package.
The absolute maximum ratings are limiting values above
which life may be shortened or specified parameters may
be degraded.
The isolation pin (substrate) must be connected to the
most negative point of the circuit to maintain electrical
isolation between transistors.
Electrical ratings
VCB = 10V
VEB = 4V VCE = 8V
VCI = 16V IC = 20mA (SL360); 50mA (SL362)
(see Figure 5)
Thermal ratings
eMS
Storage temperature
Operating junction temperature
- 55°C to
150°C
+ 150°C
Thermal resistance (see Note 2)
Chip-ta-case
Chip-ta-ambient
These figures are worst case, assuming all power is
dissipated in one transistor. If the power is equally shared
between the two transistors, both thermal resistance figures can
be reduced by 50° C/watt.
26
265°C/W
425°C/W
__________________________
SL521 AlBIC
CID~~!tJ:~
SL521A, B&C
140MHz WIDEBAND LOG AMPLIFIER
The SL521A, Band C are bipolar monolithic integrated
circuit wideband amplifiers, intended primarily for use in
successive detection logarithmic I F striPS, operating at
centre frequencies between 10MHz and 100MHz. The
devices provide amplification, limiting and rectification, are
suitable for direct coupling and incorporate supply line
decoupling. The mid-band voltage gain of the SL521 is
typically 12 dB (4 times). The SL521A, Band C differ
mainly in the tolerance of voltage gain and upper cut-off
frequency.
OUTPUT
EARTH
I
I
DETECTED
OUTPUT
eM8
Fig. 1 Pin connections
FEATURES
ABSOLUTE MAXIMUM RATINGS
••
••
•••
(Non-simu Itaneous)
Well-defined Gain
4dB Noise Figure
High liP Impedance
Low alP Impedance
165MHz Bandwidth
On-Chip Supply Decoupling
Low External Component Count
Storage temperature range
-55°C to +175°C
Chip operating temperature
+175°C
Chip-to-ambient thermal resistance
250°CIW
Chip-to-case thermal resistance
ao°clW
Maximum instantaneous voltage at
video output
+12V
Supply voltage
+9V
APPLICATIONS
•
Logarithmic I F strips with Gains up to 108 dB
and Linearity Better Than 1 dB.
2+VE
SUPPLY
t. DETECTED
OUTPUT
iD 14 ' 0
T:.25°C
~
Z 12'0
~ 10'0
3 RF
OUTPUT
~
V
"\
.of-
-...-
~
1,\ ,
\
~
\\\
~ 8·0
\
OUTPUT
EARTH
10
30
60
100
FREQUENCY I MHz I
Fig. 2 SL521 Circuit diagram
Fig. 3
Voltage gain v. frequency
27
SL521 AlBIC
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Temperature
= +22°C ± 2°C
Supply voltage
= +6V
DC connection between input and bias pins.
Value
Characteristic
Circuit
Voltage gain, f
= 30MHz
Typ.
Max.
A
B
C
11.5
11.3
11.0
12.5
12.7
13.0
dB
A
B
C
11.3
11.0
10.7
12.7
13.0
13.3
dB
dB
dB
Upper cut·off frequency (Fig. 3)
A
B
C
150
140
130
Lower cut·off frequency (F ig. 3)
ABC
5
Propagation delay
ABC
2
Voltage gain, f
= 60MHz
Maximum rectified video output
current (Fig: 4 and 5)
A
B
C
170
170
170
MHz
7
mA!
mA f
mA
ABC
0.7
db/V
ABC
25
%/V
Maximum input signal before overload
ABC
1.8
A
B
C
12.5
12.5
11.5
= 60MHz, 0.5V rms input
V rms See note below
1.9
4
5.25
dB
15.0
15.0
15.0
1S.0
1S.0
19.0
mA
mA
mA
f
= 60MHz,
Rs
= 450 ohms
Vp·p
1.2
Maxiumum RF output voltage
10 ohms source, SpF load
ns
Variation of gain with supply vQltage
Noise figure (Fig. 6)
10 ohms source, SpF load
MHZ!
MHz 10 ohms source, SpF load
MHz
1.10
1.15
1.20
1.00
0.95
0.90
dB
dB
Variation of maximum rectified
output current with supply voltage
Supply current
Conditions
Units
Min.
Note: Overload occurs when the input signal reaches a level sufficient to forward bias the base-collector junction to TR 1 on peaks.
V
I II
r--.......
'(Mt,
11
//
JOMHz
I II
~
V
5
1
r--....
!OOMH z
V)
\/'CI
V
/
V
0
0·2
0·5
INPUT SIGNAL IVrms}
Fig. 4
28
Rectified output curtent v. input signal
SL521 AlBIC
The 500pF supply decoupling capacitor has a resistance
of, typically, 10 ohms. It is a junction type having a low
breakdown voltage and consequently the positive supply
current will increase rapidly if the supply voltage exceeds
7.5V (see ABSOLUTE MAXIMUM RATINGS).
I
«
E
--
lOMHz
I--I---
-
--
I
......-
-
I--
~MHZ
5'0
I
t--- t----'OMHZ
L-- J..--
INPUT" Q'SV R MS
~
.../
V
t " 50 MHz
Rs = 4~O.n.
0
2·5
o
50
AMBIENT TEMPERATURE 1°C)
-20
-60
Fig. 6
Fig. 5 Maximum rectified output current v. temperature
20
40
GO
TEMPERATURE 1°C)
Typical noise figure v. temperature
1 1 1 1
OPERATING NOTES
The amplifiers are intended for use directly coupled, as
shown in Fig. 8.
The seventh stage in an untuned cascade will be giving
virtually full output on noise.
Noise may be reduced by inserting a single tuned circuit
in the chain. As there is a large mismatch between stages a
simple shunt or series circuit cannot be used. The choice of
network is also controlled by the need to avoid distorting
the logarithmic law; the network must give unity voltage
transfer at resonance. A suitable network is shown in Fig. 9.
The value of C1 must be chosen so that at resonance its
admittance equals the total loss conductance across the
tuned circuit. Resistor R 1 may be introduced to improve
the symmetry of filter response, providing other values are
adjusted for unity gain at resonance.
A simple capacitor may not be suitable for decoupling
the output line if many stages and fast rises times are
required. Alternative arrangements may be derived, based
on the parasitic parameters given.
Values of positive supply line decoupling capacitor
required for untuned cascades are given below. Smaller
values can be used in high frequency tuned cascades.
~8
0-2 mmho
ove-r the frequency range
I
T:-55°C
I
,
- ---
f---- Conductance
~
T=-25°C
1----
T=-125°C
I---
1
o
~ f--
-
1---1-
50
FREQUENCY
I MHz)
Fig. 7 Input admittance with open-circuit output
-+---_--<
OUTPUT
OUTPUT
~ DECOUPLING
Fig. 8
Direct coupled amplifiers
Number of stages
6 or more
I Minimum capacitance
30nF
I
5
110nF
I4 I3
I 3nF 11nF
FROM n th
STAGE
Tl.---.-'
I -------}
Cl
TO
(n
.l)th STAGE
PINS LJNKED)
(BIAS
AND INPUT
RI
The amplifiers have been provided with two earth leads
to avoid the introduction of common earth lead inductance
between input and output circuits. The equipment designer
should take care to avoid the subsequent introduction of
such inductance.
T
L
Fig. 9
-/J7. . . . .--'T
D.C. BLOCKING
CAPAC ITOR
Suitable interstage tuned circuit
29
SL521 AlBIC
Parasitic Feedback Parameters (Approximate)
The quotation of these parameters does not indicate that
elaborate decoupling arrangements are required; the
amplifier has been designed specifically to avoid this
requirement. The parameters have been given so that the
necessity or otherwise of further decoupling, may become a
matter of calculation rather than guess-work.
r;;
V6
RF current component from pin 4
20
Voltage at pin 6
=
h
mm os
(This figure allows for detector being forward biased by
noise signals)
V6
V4
= Effective voltage induced at pin 6 = 0 003
Voltage at pin 4
12
Current from.pin 2
Voltage at pm 6
V6
.
6mmhos (f = 10M Hz)
= Voltage induced ~t pin 6 = 0.03 (f = 10MHz)
[~
V~a
Voltage at pm 2
Voltage at pin 2
(pin 6 joined to pin 7 and
fed from 300 ohms source)
61_
rV
Voltage induced.at pin 6 = 0.01 (f = 10MHz)
lV 2Jb
Voltage at pm 2
Voltage at pin 2
(pin 7 decoupled)
12
rv;j
rV61
~ [v~J a\Y2J
b decrease with frequency above 10MHz
at 6 dB/octave.
30
SL523B/SL523C/SL523H
SL523B,C&HB
120MHz DUAL WIDEBAND LOG AMPLIFIER
The SL523B and Care wideband amplifiers for use in
successive detection logarithmic IF strips operating at centre
frequencies between 10 and 100MHz. They are pincompatible with the SL521 series of logarithmic amplifiers
and' comprise two amplifiers, internally connected in
cascade. Small signal voltage gain is 24dB and an internal
detector with an accurate logarithmic characteristic over a
20dB range produces a maximum output of 2.1 mA. A strip of
SL523s can be directly coupled and decoupling is provided
on each amplifier. RF limiting occurs at an input voltage of
25mV RMS but the device will withstand input voltages up to
1.8V RMS without damage.
The SL523HB is supplied in matched sets of eight devices.
The gain at 60MHz of the devices in the set is matched to
0.75dB. In all other respects the device is identical to an
SL523B. This selection enables very precise log strips to be
produced. Supplied only to Plessey Level B screening
including burn-in.
I
VIDEO OIiTPUT
FEATURES
•
•
•
•
eM8
Small Size/Weight
Lower Power Consumption
Readily Cascadable
Accurate Logarithmic Detector
Characteristic
Fig. 1 Pin connections (view from beneath)
ABSOLUTE MAXIMUM RATINGS
QUICK REFERENCE DATA
•
•
•
•
•
•
Small Signal Voltage Gain
Detector Output Current
Noise Figure
Frequency Range
Supply Voltage
Supply Current
(Non simultaneous)
24dB
2.1mA
4dB
10 -1 OOMHz
Storage temperature range -55°C to + 175°C
Operating temperature range -55°C to + 125 °C
Maximum instantaneous voltage at video output
+12V
Supply voltage
+9V
+6V
30mA
150
2
tve
SUPPLY
r--+_ _-o ~~~~~T
4
3
RF
.l-+.,..c:::::::J-t-4--t----1r----t-t---o OUTPUT
L---_~---~>______O
EARTH
Fig. 2 Circuit diagram (one amplifier)
31
SL523B/SL523C/SL523H
ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise stated):
Ambient temperature 22°C ±2°C
Supply voltage +6V
DC connection between pins 6 and 7
Source impedance 100
Load impedance 8pF
Frequency 60M Hz
Characteristic
Type
Small signal voltage gain
BH
C
BH
C
H
BC&H
BC&H
BC&H
22.6
22
22
21.4
B H
C
BC&H
Small signal voltage gain
Gain variation (set of 8)
Upper cut off frequency
Lower cut-off frequency
Propagation delay
Maximum rectified video
output current
Maximum input signal
before overload
Noise figure
Supply current
1.9
1.8
2.1
2.1
1.8
120
/
Conditions
Units
dB
dB
dB
dB
dB
MHz
MHz
ns
}
}
2.3
2.4
mA
mA
}
1.9
4
5.25
VRMS
dB
30
30
36
38
mA
mA
15
1.2
BC&H
V
Max.
25.4
26
26
26.6
0.75
Freq.
30MHz
Freq.
·60MHz
Freq.
= 60MHz
Vin 0.5VRMS
Source impedance
4500
Vp-p
24~+=~~~P+~~~1l+=~+P~,~4=~
..... r2·0
1'8
Value
Typ.
24
24
24
24
0.5
150
10
4
25
23
BH
C
Maximum RF output
voltage
Min.
~22r-+-r+~-rH+~~/r+++~++H+~~-H
.....
z
2°r-+-r+~-r~H--r~~r++H~-H~H
~ 18r-+-r+~-VH+H-~~~r++H~~H-H
30MHz
~ 16r-~--r+~~H+H-~~~r++H~-+~H
:;
60MHz
~ 14r-+-~~-rH+H--r+++-r++H~~~H
/.
12~~~~~~~10~~~30~~~10~0~~20~OU
1·0
FREQUENCY 101Hz
0·8
0·6
If
/
0·2
o
Fig, 4 Voltage gain v. frequency
.....
1
10
100
1,000
Vin mVrms
Fig. 3 Rectified output current v. input signal
OPERATING NOTES
The amplifier is designed to be directly coupled (see
Fig. 5)
The fourth stage in an untuned cascade will give full
output on the broad band noise generated by the first
stage.
Noise may be reduced by inserting a single tuned
circuit in the chain. As there is a large mismatch between
stages a simple shunt or series circuit cannot be used.
The network chosen must give unity voltage gain at
resonance to avoid distorting the log law. The typical
value for input impedance is 500 ohms in parallel with
5pF and the output impedance is typically 30 ohms.
Although a 1 nF supply line decoupling capacitor is
included in the can an extra capacitor is required when
the amplifiers are cascaded. Minimum values for this
capacitor are: 2 stages - 3nF, 3 or more stages - 30nF.
In cascades of 3 or more stages care must be taken to
avoid oscillations caused either by inductance common
to the input and output earths of the strip or by feedback
32
"F
OUTPUT
'--------4------~~~~~BT
Frequency range: 10 to 100MHz
Log.range:
45dB
RF small signal gain:
48dB
Video output:
2Vpeak
Fig. 5 Simple log.lF strip
along the common video line. The use of a continuous
earth plane will avoid earth inductance problems and a
common base amplifier in the video line isolating the
first two stages as shown in Fig.6 will eliminate feedback on the video line.
SL5238/SL523C/SL523H
~30'
Frequency range:
10 to 90MHz
Log.range:
80dB
RF small signal gain:
72dB
Video output:
8mA peak
Log.accuracy:
-=::0.5dB (Typ.)
Fig. 6 Wide dynamic range log.lF strip
TYPICAL PERFORMANCE
Unselected SL523B devices were tested in a wideband logarithmic amplifier, described in RSRE Memo.
No.3027 and shown in Fig. 7.
The amplifier consists of six logarithmic stages and two
'lift' stages, giving an overall dynamic range of greater
than 80dB. The response and error curves were plotted
on an RHG Log Test Set and bandwidth measurements
were made with a Telonic Sweeper and Tektronix
oscilloscope.
Fig. 8 shows the dynamic range error curve and
frequency response obtained. The stage gains of the
SL523 devices used were as shown in Table 1.
Stages
fo (MHz)
1
2
3
Lift
60
60
60
60
Max.
Gain (dB) Deviation
(dB)
24.123
24.089
23.888
24.086
0.235
Table 1 Stage gains of SL523 used in performance tests
The input v. output characteristic (Fig. 8a) is calibrated at 10dB/cm in the X axis and 1V/cm in the Y
axis. 80dB of dynamic range was attained.
The error characteristic (Fig. 8b) is calibrated at
10dB/cm in the X axis and 1 dB/cm in the Y axis; this
shows the error between the log. input v. output
characteristic and a mean straight line and shows that a
dynamic range of 80dB was obtained with an accuracy
of ±0.5dB.
As a comparison, the log amplifier of Fig. 7 was constructed with randomly selected SL521 Bs (two
SL521 Bs replacing each SL523B). Again, a dynamic
response of 80dB was obtained (Fig. 9a) with an
accuracy of ±0.75dB (Fig. 9b).
Bandwidth curves are shown in Figs. 8c and 9c,
where the amplitude scale is 2dB/cm, with frequency
markers at 10MHz intervals from 20 to 100MHz. Using
SL523Bs (Fig. 8c), the frequency response at 90MHz is
4dB down on maximum and there is a fall-off in response
after 50M Hz. Fig. 9c shows that the frequency response
of the amplifier falls off more gradually after 40M Hz but
again the response at 90MHz is 4dB down on maximum.
These tests show that the SL523 is a very successful
dual-stage log.amplifier element and, since it is pincompatible with the SL521, enables retrofit to be
carried out in existing log.amplifiers. It will be of greatest
benefit however, in the design of new log amplifiers,
enabling very compact units to be realised with a much
shorter summation line.
Fig. 7 Wideband logarithmic amplifier
33
SL523B/SL523C/SL523H
Fig. 9b Error curve
Fig. Bc Frequency response, detected output
Fig. B Characteristics of circuit shown in Fig. 7 using SL523Bs
34
Fig. 9c Frequency response, detected output
Fig. 9 Characteristics of circuit shown in Fig. 7 using SL521 Bs
SL531C
~!:~~~JF.~
__________________________
SL531C
250MHz TRUE LOG IF AMPLIFIER
The SL531C is a wide band amplifier designed for use
in logarithmic IF amplifiers of the true log type. The input
and log output of a true log amplifier are at the same frequency i.e. detection does not occur. In successive detection log amplifiers (using SL521, SL 1521 types) the log
output is detected.
The small signal gain is 10dB and bandwidth is over
500MHz. At high signal levels the gain of a single stage
drops to unity. Acascade of such stages give a close approximation to a log characteristic at centre frequencies
between 10 and 200MHz.
An important feature of the device is that the phase shift
is nearly constant with signal level. Thus any phase information on the input signal is preserved through the strip.
INPUT EARTH
I
/
DECOUPLE
(LFONLYI
VCC2
eMS
Fig. 1 Pin connections
FEATURES
•
•
•
Low Phase Shift vs Amplitude
On-Chip Supply Decoupling
Low External Components Count
APPLICATIONS
True Log Strips with:INPUT
•
•
•
Log Range
Centre frequencies
Phase Shift
70 dB
10 - 200 MHz
± 0.5 degrees / 10 dB
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Storage temperature range
Operating temperature range
+15 volts
-55°C to + 150°C
-55°C to + 125°C
See operating notes
Max junction temperature
Junction - ambient thermal resistance
Junction - case thermal resistance
GROUND
Fig. 2 Circuit diagram
150°C
220°C/Watt
BOoC/Watt
CIRCUIT DESCRIPTION
The SL531 transfer characteristic has two regions. For
small input signals it has a nominal gain of 10 dB, at large
signals the gain falls to unity (see Fig 7). This is achieved by
operating a limiting amplifier and a unity gain amplifier in
parallel (see Fig 3). Tr1 and Tr4 comprise the long tailed
pair limiting amplifier, the tail current being supplied by Tr5,
see Fig 2. Tr2 and Tr3 form the unity gain amplifier the gain
of which is defined by the emitter resistors. The outputs of
both stages are summed in the 300 ohm resistor and Tr7
acts as an emitter follower output buffer. Important
features are the amplitude and phase linearity of the unity
gain stage which is achieved by the use of 5GHz transistors
with carefully optimised geometries.
liMITING
AMP
TR1. TR4
TR2. TR3
UNITY GAIN
AMP
Fig. 3 Block diagram
35
SL531C
ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise stated):
Test circuit Fig (4)
Frequency 60 MHz
Supply voltage 9 volts
Ambient temperature 22± 2°C
Value
Characteristic
Small signal voltage gain
High level slope gain
Upper cut off frequency
Lower cut off frequency
Supply current
Phase change with input amplitude
Input impedance
Output impedance
Units
Typ
Min
Conditions
Max
10
12
0
+1
500
3
10
17
25
1.1
3
2.5pf parallel with 1k
15~series with 25nh
8
-1
250
dB
dB
MHz
MHz
mA
degrees
Vin
= -30dBm
-3dB w.r.t.
± 60 MHz
-Vin = 30 dBm to + 10 dBm
=
f
10 - 200MHz
OPERATING NOTES
3.
1.
The LF response is determined by the on chip capacitors.
It can be extended by extra external decoupling on pins 5
and 1.
Supply Voltage Options
An on cnip resistor is provided which can be used to drop
the supply voltage instead of the external 180 ohms shown
in the test circuit. The extra dissipation in this resistor reduces the maximum ambient operating temperature to
100o C. It is also possible to use a 6 volt supply connected
directly to pins 1 and 2. Problems with feedback on the
supply line etc may occur in this connection and RF chokes
may be required in the supply line between stages.
2.
Low Frequency Response
Layout Precautions
The internal decoupling capacitors help prevent high frequency instability, however normal high frequency layout
precautions are still necessary. Coupling capacitors should
be physically small and be connected with short leads. It is
most important that the ground connections are made with
short leads to a continuous ground plane.
Fig. 4 Test circuit
5
VIN ;:: -40 dBm
10
.-1-- -1-::;.
t:::- I-- -1;1
l---:::::::= ,..-
t:::--
-
...;.-
!
/
......... I--
T= -5SoC
1/
_i250~_ r-i.1250C
--
~
,;;:. ~
- 1\1\\
\~
\ \~
1\
1\ 1\1\
\
I
1\ \
1\
1\
II
o
1M Hz
100M Hz
1QMHz
FREQUENCY
Fig. 5 Small signal frequency response
36
1GHz
SL531C
(I ffEE
-40
-30
-20
-10
0
.10
VIN (dBm)
Fig. 6 Phase v. input
1·0
60 MHz
Vee ·9V
0·8
!en
0·6
GAIN
10 dB
g
~
~
I
I
I
0·4
0·2
TYPICAL APPLICATION - 6 STAGE LOG STIP
Input log range OdBm to -70dBm
Low level gain 60dB (-70dBm in)
Output dynamic range 20dB
Phase shift (over log range) ±3°
Frequency range 10 - 200MHz
/.
LOW LEVEL
!:l
"
,~
/
V
/
/
/
L
I
0·4
0·2
0·6
0·8
VIN VOLTS (rms)
Fig. 7 Transfer characteristics linear plot
1·0
The circuit shown in Fig 9 is designed to illustrate the use
of the SL531 in a complete strip. The supply voltage is fed
to each stage via an external 1800 resistor to allow operation to 125°e ambient. If the ambient can be limited to
+ 100 0 e then the internal resistor can be used to reduce
the external component count. Interstage coupling is very
simple with just a capacitor to isolate bias levels being
necessary. Noconnection is necessary to pin 5 unlessoperation below 10MHz is required. It is important to provide
extra decoupling on pin 1 of the first stage to prevent positive feedback occuring down the supply line. An SL560 is
used as a unity gain buffer, the output of the log strip being
attenuated before the SL560 to give a nominal OdBm output into 500.
0·8
60 MHz
Vee 9VOLTS
/v
0·2
/
/
V
J.----40
-30
-20
VIN (dBm)
Fig. 8 Transfer characteristics logarithmic input scale
ALTERNATIVE Vee CONNECTION
(100"CAMBIENT MAX)
Fig. 9 Circuit diagram 6 stage strip
37
SL531C
~'
/
60 MHz
0·8
I
/
VI
~
~
0·8
I-
::I
~
/
0'4
0·2
LV
-80
V
V
/
-60
-40
-20
INPUT (dBm)
:j§01 I~issl I
-80
-60
-40
-20
0
INPUT (dBm)
Fig. 10 Transfer function of log strip
38
SL532C
SL532C
LOW PHASE SHIFT LIMITER
The SL532C is a monolithic integrated circuit designed
for use in wide band limiting IF strips. It offers a bandwidth
of over 400MHz and very low phase shift with amplitude.
The small signal gain is 12dB and the limited output is
1 volt peak to peak. The use of a 5GHz IC process has
produced a circuit which gives less than 1° phase shift
when overdriven by 12dB. The amplifier has intemal
decoupling capacitors to ease the construction of cascaded strips and the number of external components
required has been minimised.
INPUT GROUND
INPUT"
I
/
DECOUPlE (IF ONlYI
FEATURES
•
•
•
eMS
Low Phase Shift v. Amplitude
Wide Bandwidth
Low External Component Count
Fig.1 Pin connections
APPLICATIONS
•
•••
•
Phase Recovery Strips in Radar and ECM Systems
(e.g. Doppler)
Limiting Amps for SAW Pulse Compression Systems
Phase Monopulse Radars
Phased Array Radars
Low Noise Oscillators
DECOUPLE
(LF)
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Temperature (Ambient) 25°C
Frequency 60 MHz
Vcc =+9V
RL = 1kUII2.5pF
INPUT
OUTPUT
GROUND
GAOUND
Fig.2 Circuit diagram
39
SL532C
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Temperature (ambient) 25° C ± 2° C
Frequency 60MHz : RL = 1kO /5pF : VIN = -3OdBm
+9.0V: Rs
500
Vcc
=
=
Characteristic
Min.
Small signal voltage gain
Small signal voltage gain
-1dB compression point
Limited output voltage
Limited output voltage
Upper cut off frequency
Lower cut off frequency
Supply current
Phase variation with signal level
11
1.0
Value
Typ.
12.8
12.5
-10
1.15
1.10
14
6
1.4
Input impedance
Output impedance
Noise figure
Gain variation with temperature
Phase variation with temperature
Limited output voltage
variation with temperature
8.5
±1
±1.5
-34
-43
-69
1kO/2.SpF
300
7
±1
± 0.5
l.----
, -
30MHZ~ SOMHz
1.1
~SOMHZ
1.0
i' 0.9
~
0.7
w
e:.I-
/
/
/
I
0.4
0.3
0.2
0.1
o k--"'
-50
'/
-40
/'
/
= 150MHz
Vin = +1OdBm
f = 150MHz
-3dB wrt 60MHz
May be extended by decoupling pin 5
No signal
-30dBm to +10dBm
-30dBm to OdBm. f = 1S0MHz
f = 100MHz
f = 1S0MHz
f = 200MHz
De~rees
Degrees
Degrees
Degrees
4000 source impedance. f = 80M Hz
-40°C to +8SoC
-40° C to +85° C at any level
between -30dBm to +10dBm
Vin = +10dBm
-40°C to +8SoC
dB
dB
Degrees
fjl~a~II . H~~1111
1.0
2.0
5.0
10.0 20.0
50.0
FREQUENCY (MHz)
100.0 200.0 400.0
Fig.4 Gain/frequency curve of a typical device
,
O.S
:::I
~ 0.5
f
V p-p
1.3
0.8
10
11
±3
±O.OS
1.2
Conditions
dB
dB
dBm
V p-p
V p-p
MHz
MHz
mA
Degrees
250
Absolute phase shift
input to output
~~
Units
Max.
+1.5
r---~r-----'---"'----"'---r--..,
+1.0
1-~I-J::;=:::!=:::;::t~-I-!1
Ui'
/
~
Cl
w
e.
t:
+O.SI---~i"7"~--i------t----+----"~N;;~-f--;
:i:
I/)
w
-30
-20
VIN (dBm)
-10
+10
~
a.
Fig.3 Transfer characteristic of a single stage
-0·~SL-0--_....I4-:-0--_~3-0---~20::-----~10::---~--+~10
INPUT IN dBm
Fig.5 Phase change with input level
40
SL532C
TYPICAL APPLICATION
Five stage strip
Input signal for full limiting
Limited output
Phase shift (VIN -57 -. + 10dBm)
300,.,Vrms
-57dBm
1Vp-p
±:r'typ.
The recommended output buffer amplifier to drive 50n loads is the SL560C
Fig.6 Five stage IF strip
CIRCUIT DESCRIPTION
The SL532 uses a long-tailed pair limiting amplifier
which combines low phase shift with a symmetrical limiting characteristic. This is followed by a simple emitter
follower output stage. Each stage of a strip is capable of
driving to full output a succeeding SL532 but a buffer
amplifier is needed to drive lower impedance loads. No
external decoupling capacitors are normally required but
for use below 10MHz extra decoupling can be added on
pins 1 and 5. Bias for the long-tailed pair is provided by
connecting the bias (pin 2) to the decoupled supply (pin 1).
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Storage temperature range
Operating temperature range
+ 15 V
- 55°C to + 150°C
- 55°C to + 125°C
41
SL532C
42
SL5418
SL541B
HIGH SLEW RATE OPERATIONAL AMPLIFIER
The SL541 is a monolithic amplifier designed for optimum
pulse response and applications requiring high slew rate
with fast settling time to high accuracy. The high open loop
gain is stable with temperature, allowing the desired closed
loop gain to be achieved using standard operational
amplifier techniques. The device has been designed for
optimum response at a gain of 20d8 when no compensation
is required. The SL5418 has a guaranteed input offset
voltage of ±5mV maximum and replaces the SL541C.
The SL541 8 is tested in two circuit applications (A and 8).
(BOTTOM VIEW)
EARTH
j-V"SUPPlY
\
/' CASE (-VE SUPPLY)
INVERTING liP "
INPUT EMITTER DEGENERATION
(RESISTANCE COMPENSATION)
1/
08
0
7
6
°
j
NON·INV. liP
" COMPENSATION
\
+V"SUPPlY
CM10
FEATURES
•
•
•
•
•
•
•
High Slew Rate: 175V /IlS
Fast Settling Time: 1% in 50ns
Open Loop Gain: 70dB (SL541 B)
Wide Bandwidth: DC to 1OOMHz at 10dB Gain
Very Low Thermal Drift: O.02dB/oC
Temperature Coefficient of Gain
Guaranteed 5mV input offset maximum
Full Military Temperature Range (OIL Only)
Package: 10 Lead TO-5
14 Lead OIL Ceramic
DG14
(TOP VIEW)
Fig. 1 Pin connections
APPLICATIONS
•
•
•
•
•
•
Wideband I F Amplification
Wideband Video Amplification
Fast Settling Pulse Amplifiers
High Speed Integrators
D/A and A/D Conversion
Fast Multiplier Preamps
ABSOLUTE MAXIMUM RATINGS
Supply voltage (V + to V -)
24V
Input voltage (Inv. liP to non inv. I/P)
±9V
Storage temperature
-55°C to +175°C
Chip operating temperature
+175°C
Operating temperature:
TO-5: -55°C to +85°C
OIL: -55°C to +125°C
Thermal resistances
Chip-to-ambient: TO-5
OIL
Chip-to-case:
TO-5
OIL
220°C/W
125°C/W
60°C/W
40°C/W
10
Fig. 2
SL541 circuit diagram (TO-5 pin nos.)
43
SL541B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = 25° C
Rc = 00
Test circuits: see Fig.8
Characteristic
Circuit
Static nominal supply current
Input bias current
Input offset voltage
Dynamic open loop gain
A,B
A,B
A,B
A
B
A,B
A,B
A,B
A,B
Open loop temperature coefficient
Closed loop bandwidth (-3dB)
Slew rate (4V peak)
Settling time to 1 %
Maximum output voltage
(+ve)
(-ve)
(+ve)
(-ve)
Maximum output current
Maximum input voltage
(+ve)
(-ve)
(+ve)
(-ve)
Supply line rejection
(+ve)
(-ve)
Input offset current
Common mode rejection
Input offset voltage drift
Value
Typ.
Min.
Max.
16
7
45
60
54
71
-0.02
100
175
50
100
A
A
B
B
A,B
5.5
100
5.7
-1.9
3.0
-3.0
6.5
2.5
4
A
A
B
B
21
25
5
Units
mA
pA
mV
dB
dB
dB/oC
MHz
Vips
ns
-2.5
V
V
V
V
5
3
-3
54
46
66
54
9.85
60.7
25
6000 load
X10 gain
X10 gain
V
V
V
V
mA
-1.5
-1
A,B
A,B
A,B
A,B
A
Conditions
Non-inverting
modes
dB
dB
pA
dB
jN/oC
ELECTRICAL CHARACTERISTICS (Typical)
Test conditions (unless otherwise stated):
Tamb = -55°C to +85°C (T05)
Tamb = -55°C to +125°C (OIL only)
Rc = 00, Test circuit B
Characteristic
Static nominal supply current
Input bias current
Input offset voltage
Maximum output current
Maximum input voltage
Supply line rejection
Maximum output voltage
Common mode rejection
Input offset current
Output voltage drift
Input bias current drift
Output current drift
44
Min.
Value
Typ.
16
(+ve)
(-ve)
(+ve)
(-ve)
(+ve)
(-ve)
(+ve)
(-ve)
-8
3.5
Max.
25
35
8
6.5
3
-3
50
42
2.3
-2.5
55
16
15
60
40
Units
mA
pA
mV
mV
mA
V
V
dB
dB
V
V
dB
pA
pV/oC
nA/oC
nA/oC
Conditions
Non-inverting modes
SL541B
25
- -0
X10 NON
INVERTING
~ 20
z
:;;:
(!J
15
,./ -~
1 -""-
~~
10
(!J
5
z
:;;:
0
-
Cc
SLEW SETTLING
RATE
TIME
*
0
175
42
22
0
115
50
0
10
70
70
100 22
140
50
X3 NON
~ f..-
r=:: ~
\"'--- K
~
o
39
5
22
10
70
50
150 10
60
50
Q
+5
Xl VOLTAGE
- f-- !-- ~I\
FOLLOWER
~
z
:;;:
(!J
0
\-
-5
\
-10
10
20
50
100
OPERATING NOTES
(ns)
"'
"
INVERTING
~
"
~
10
15
RC
(n.) (pF) (V/~s)
The SL541 may be used as a normal, but non
saturating operational amplifier, in any of the usual
configurations (amplifiers, integrators etc.), provided
that the following points are observed:
1. Positive supply line decoupling back to the output
load earth should always be provided close to the
device terminals.
2. Compensation capacitors should be connected
between pins 4 and 5. These may have any value
greater than that necessary for stability without
causing side offsets.
3. The circuit is generally intended to be fed from a
fairly low impedance « 1 k 0), as seen from pins 6
and 9 - 1000 or less results in optimum speed.
4. The circuit is designed to withstand a certain
degree of capacitive loading (up to 20pF) with
virtually no effect. However, very high capacitive
loads will cause loss of speed due to the extra compensation required and asymmetric output slew rates.
5. Pin 10 does not need to be connected to zero volts
except where the clipping levels need to be defined
accurately w.r.t. zero. If disconnected, an extra ±0.5
volt uncertainty in the clipping levels results, but the
separation remains. However, the supply line rejection
is improved if pin 10 can be left open-circuit (circuit Bonly).
200
FREOUENCY (MHz J
Fig. 3
Performance graphs - gain v. frequency (load =
2kn/10pF) * See operating note 2
+VE
'\ /
I---
\V
SLEW RATE OVER
10% TO 85% POINTS
175 V/JJS
)
(
:;
c
">C?
1/
IL
1\
\
VOUT
\
VIN
J
1"1\
\
1
CC=OpF
RC=On. -
11\
J
\
\
-VE
t (20n5/ DIV J
t (20n5/ DIV)
FigA Slew rate - X10 non-inverting mode
Input square wave OAV pip
Fig.6 Output clipping levels - X10 non-inverting mode
Input moderately overdriven, so that output goes into
clipping both sides
INPUT
S~EP~
f\
\
\
RC= O.n.
>
C
A.
+VE
V
~
V
.l
">
~
I "
-VE
I
V
t (20n5/ DIV)
Fig.S Settling time - X10 non-inverting mode
-VE
\
CC=OpF
j
/
~
+VE
t (20n5/ DIV)
Fig.7 Output clippings levels - X10 non-inverting mode.
Output goes from clipping to zero volts. Vin = 3V peak
45
step, offset +ve or -ve.
SL541B
CIRCUIT A
CIRCUIT B
DYNAMIC TEST CIRCUIT
RC 22.n
Cc = OpF
=
Fig. 8 Test circuits
TEST CONDITIONS AND DEFINITIONS
Both slew rate and settling time are measures of an
amplifier's speed of response to an input. Slew rate is an
inherent characteristic of the amplifier and is generally
less subject to misinterpretation than is settling time,
which is often more dependent upon the test circuit
than the amplifier's ability to perform.
Slew rate defines the maximum rate of change of
output voltage for a large step input change and is
related to the full power frequency response (fp) by the
relationship.
S
=
3
2nfpEo
Fig.9
where Eo is the peak output voltage
Settling time is defined as the time elapsed from
the application of a fast input step to the time when the
amplifier output has entered and remained within a
specified error band that is symmetrical about the final
value. Settling time, therefore, is comprised of an initial
propagation delay, an additional time for the amplifier
Non-saturating sense amplifier (30V/!ls for 5mV)
Note: the output may be caught at a pre-determined
level. (TO-5 pin nos.)
to slew to the vincinity of some value of output voltage,
plus a period to recover from overload and settle within
the given error band.
The SL541 is tested for slew rate in a X10 gain
configuration.
1MHz
100kHz
10MHz
100MHz
FREQUENCY
Fig.10
46
lOAO~
o---=:~=r--IL--r.;:----r:-....J
SL541B open loop gain and phase shift v. frequency
SL5500/G
SL550D&G
LOW NOISE WIDEBAND AMPLIFIER
WITH EXTERNAL GAIN CONTROL
The SL550 is a silicon integrated circuit designed for use
as a general-purpose wideband linear amplifier with remote
gain control. At a frequency of 60MHz, the SL550G noise
figure is 1.8dB (typ.) from a 200 ohm source, giving good
noise performance directly from a microwave mixer. The
SL550 has an external gain control facility which can be used
to obtain a swept gain function and makes the amplifier ideal
for use either in a linear IF strip or as a low noise preamplifier
in a logarithmic strip.
External gain control is performed in the feedback loop of
the main amplifier which is buffered on the input and output,
hence the noise figure and output voltage swing are only
slightly degraded as the gain is reduced. The external gain
control characteristic is specified with an accuracy of ±1dB,
enabling a well-defined gain versus time law to be obtained.
The input transistor can be connected in common emitter
or common base and the quiescent current of the output
emitter follower can be increased to enable low impedance
load to be driven.
CAPACITIVE
LINK
DECOUPLE
INPUT
INPUT
~~eBCE
16
15
14
13
2
3
4
5
~
'---...r--I
GAIN
CAPACITIVE
CONTROL
LINK
6
DECOUPLE
7
'OUTPUT VOUTPUT
Vce
DC16
Fig. 1 Pin connections (top view)
FEATURES
APPLICATIONS
•
•
•
•
200 M Hz Bandwidth
Low Noise Figure
Well- Defined Gain Control Characteristic
25dB Gain Control Range
•
•
•
•
40dB Gain
Output Voltage 0.8Vp-p (Typ.)
Low Noise Preamplifiers
Swept Gain Radar I Fs
VARIABLE
GAIN AMP
AGC
VOUT
0 - - -............... ---1 J
L-----IOUT
I
I
I
- - ....L _ _ _ .... _
VS
= 6V 0-------...--11
'----~
Ie
VARIABLE ATTENUATOR
TRACKING WITH VARIABLE
GAIN AMP
ALL CAPACITORS 10nF (WEECON" TYPE CAPACITORS)
R2
Fig. 2 Functional diagram
=300 SEE OPERATING NOTE
Fig. 3 Test circuit
47
SL550D/G
ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise stated):
f = 30MHz,Vs = +6V, RL = 2000, Ic = 0, R1
Characteristic
Voltage gain
Gain control characteristic
Gain reduction at mid-point
Max. gain reduction
Noise figure
Output voltage
Supply current
Gain variation with supply voltage
Upper cut-off frequency
(-3dB wrt 30M Hz)
Gain variation with temperature
(see note 2)
= 7500, Tamb =
Circuit
Min.
SL550G
SL550D
Both
SL550G
SL550D
SL550G
SL550D
SL550G
SL550G
SL550D
Both
Both
SL550G
SL550G
SL550D
Both
39
35
+25°C
Value
Typ. Max.
42
44
40
45
See note 1
10
9
20
25
25
2.7
2.0
3.5
3.0
0.15
0.3
13
11
15
20
11
0.2
Units
Conditions
dB
dB
= O.24mA
= O.2mA
= 2.0mA
Ie = 2.0mA
Rs = 2000
Rs = 50n
Rs = 2000
R1 = 00
R1 = 750n
R1 = 00
R1 = 7500
R1 = 00
Vs = 6 to 9V
dB
dB
dB
dB
dB
dB
dB
Vrms
Vrms
mA
mA
mA
dB/V
Both
125
MHz
Both
:1:3
dB
Ic
Ie
Ie
Tamb
= -55 to +125°C
NOTES
1.
2.
The external gain control characteristic is specified in terms of the gain reduction obtained when the control current (Ic) is increased
from zero to the specified current.
This can be reduced by using an alternative input configuration (see operating note: 'Wide Temperature Range').
OPERATING NOTES
Input Impedance
The input capacitance, which is typically 12pF at
60M Hz, is independent of frequency, The input resistance, which is approximately 1.5k at 10M Hz, decreases
with frequency and is typically 500 ohms at 60M Hz.
Control Input
Gain control is normally achieved by a current into pin
2. Between pin 2 and ground is a forward biased diode
and so the voltage on pin 2 will vary between 600 mV
at Ie = 11lA to 800 mV at Ie = 2 mA. The amplifier gain
is varied by applying a voltage in this range to pin 3,
To avoid problems associated with the sensitivity of the
control voltage and with operation over a wide
temperature range the diode should be used to convert
a control current to a voltage which is applied to pin 3
by linking pins 2 and 3.
Minimum Supply Current
300 resistor in the emitter of the input transistor. This is
achieved by decoupling pin 13 and leaving pin 12
open-circuit. Gain variation is reduced from :i=3dB to
±1 dB over the temperature range -55°C to +125°C
(Figs, 6 and 7),
Low Input Impedance
A low input impedance (~250) can be obtained by
connecting the input transistor in common base. This is
achieved by decoupling pin 11 and applying the input
to pin 12 (pin 13 open-circuit).
High Frequency Stability
Care must be taken to keep all capacitor leads short
and a ground plane should be used to prevent any earth
inductance common between the input and output
circuits. The 300 resistor (pin 14) shown in the test
circuit eliminates high frequency instabilities due to the
stray capacitances and inductances which are unavoidable in a plug-in test system. If the amplifier is
soldered directly into a printed circuit board then the
30n resistor can be reduced or omitted completely.
If the full output swing is not required, or if high
impedance loads are being driven, the current consumption can be reduced by omitting R1 (Fig. 3), The
function of R1 is to increase the quiescent current of the
output emitter follower.
Vs = 6V
MINIMUM NOISE eONr-IGUAATION
I
0
I
Ie =0
High Output Impedance
t---.
V~
I
le= O·24mA
A high impedance current output can be obtained by
taking the output from pin 6 (leaving pin 7 opencircuit), Maximum output current is 2 mA peak and the
output impedance is 3500.
Wide Temperature Range
The gain variation with temperature can be reduced
at the expense of noise figure by including an internal
48
30
I
/
I
P
Ie = 2·0mA
10
5
I
I
20
30
----40
50 60
80 100
FREQUENCY (MHz)
Fig. 4 Frequency response
200
300
SL5500/G
:---
0
-
r-... f...
...............
.........
........
0
20dBmin
"
........
' ....
m
:!!.
z
:c
20
..............
FREQ :eoMHz
Vs = B·OV
"
.............
~
I--
10
100
1O~A
1mA
10mA
CONTROL CURRENT (lC)
Fig. 5 Gain control characteristic
30H--r--+--+--+--+--+--~-~--+~
CD
~
Z
ic=0·2mA
--r--_
:C25H--r--+--+--+--~~~--+--~--+~
"
vs·ev
-------+--
20H----+--+--+--+--+--+--~-~--+~
251-+-+--+--+---+----l-FREQUENCY. 60MHz
MiNiMUM NOiSE CONFiGURATiON
20
VS:6V
FREQUENCY· 60MHz
DEFiNED GAiN CONFiGURATiON
- -
12~_5~5~_~40~-_~20~~---'~2~0--.~470--~'6~0---'8~0---'1LOO---'1~20~
TEMPERATURE (CC)
-5
40
20
+20
+40
+60
+80
.100
+120
TEMPERATURE (CC)
Fig. 7 ~oltage gain v. temperature (pin 13 decoupled for
Improved gain variation with temperature - see operating
notes)
Fig. 6 Voltage gain v. temperature (pin 12 decoupled,
standard circuit configuration)
3·0
~S'6V I
I
/V
1·0
-55
----
/
V
I
FREQUENCY: 80MHz
NOiSE CONFiGURATiON
SOURCE iMPEDANCE' 200 OHMS
I--- MiNiMUM
V
/""
/"'"
.20
TEMPERATURE (Cc)
Fig. 8 Typical noise figure (SL550G)
49
SL5500/G
50
Fig. 9 Input and output impedances (Vs = 6V)
2
t
Ie
Fig. 10 Circuit diagram
50
5
4
SL5500/G
APPLICATION NOTES
A wideband high gain configuration using two
SL550s connected in series is shown in Fig. 11. The
first stage is connected in common emitter configuration, whilst the second stage is a common base circuit.
Stable gains of up to 65 dB can be achieved by the
proper choice of Rl and R2. The bandwidth is 5 to
130 MHz, with a noise figure only marginally greater
than the 2.0 dB specified for a single stage circuit.
Vs
RF OUTPUT
Fig. 13 Linear swept gain circuit
Vs
POWER
VOLTAGE
GAIN
GAIN
!l1j"
RF INPUT
ALL CAPACITORS 1000pF
RF OUTPUT
Fig. 14 Square law swept gain circuit
Fig. 11 A two-stage wide-band amplifier
A voltage gain control which is linear with control
voltage can be obtained using the circuit shown in
Fig. 12. The input is a voltage ramp which is negative
going with respect to ground. The output drives the
control current pins 2 and 3 directly (see Fig. 13).
If two SL550s in the strip are controlled as shown in
Fig. 14, with a linear ramp input to the linearising circuit,
a fourth power law (power gain v. time) will be obtained
over a 50 dB dynamic range.
h---r------'-------ovs= +6V
All Capacitors 10nF
Gain 46dB
Noise figure 2.0dB (RS = 2000)
Output power +5dBm (R1 = 500)
Frequency response as SL550G
Dynamic range 70dB (1 MHz bandwidth)
Fig. 12 Gain controllinearising circuit
Fig. 15 Applications example of wide dynamic range: 500
load amplifier with AGe using SL500 series
integrated circuit.
51
SL5500/G
ABSOLUTE MAXIMUM RATINGS
Storage temperature
Ambient operating temp.
Max. continuous supply
Voltage wrt pin 1
Max. continuous AGC current
pin 2
pin 3
52
-55°C to + 150°C
-40°C to +125°C
+9V
10mA
1mA
SL560C
~~~~!------------------------SL560C
300 MHz LOW NOISE AMPUFIER
This monolithic integrated circuit contains three very
high performance transistors and associated biasing
components in an eight-lead TO-5 package forming a
300 M Hz low noise amplifier. The configuration employed permits maximum flexibility with minimum use of
external components. The SL 560C is a general-purpose
low noise, high frequency gain block.
INPUT5OnAPPLICATIONs
I
INPUTCOMMON EMITTER
CONFIGURATION
06
GAIN SET
20
-OUTPUT CURRENT SET
/
I
FEATURES
(Non-simultaneous)
DB
eM8
VCC
•
•
Gain up to 40 dB
Noise Figure Less Than 2 dB (RS 200 ohm)
•
•
Bandwidth 300 MHz
Supply Voltage 2-15V (Depending on
Configuration)
•
Low Power Consumption
EARTH
OUTPUT CURRENT SET
INPUTSOn.APPlICATJONS
2
7
INPUT COMMON BASE. CONFIGURATl{)ll
OUTPUT
3
6
INPUT COMMON EMITT ER CONFIGURATION
Vee
4
5
GAIN SET
DP8
Fig. 1 Pin connections (viewed from beneath)
-ALSO AVAILABLE IN CHIP CARRIER
APPLICATIONS
•
•
•
•
•
•
•
•
•
~-----<~-+--
Radar IF Preamplifiers
Infra-Red Systems Head Amplifiers
Amplifiers in Noise Measurement Systems
Low Power Wideband Amplifiers
Instrumentation Preamplifiers
50 ohm Line Drivers
Wide band Power Amplifiers
Wide Dynamic Range RF Amplifiers
Aerial Preamplifiers for VHF TV and FM Radio
__- - - < l
4
\Icc
INPUT
(COMMON EMITTER
CONFIGURATION I 6
O------..-__+__-£
INPUT
(COMMON
BASE
CONFIGURATION)
2 OUTPUT CURRENT
SET
INPUT
ISO ... APPLICATIONSI 8
Fig. 2 SL560C circuit diagram
+VCC
EARTH
,;;;- ,,-
O/P))
(
"-
~'
"
sUBVlsl BNC SOCKET
1
~
LINK
Fig. 3PC layout for 50- Clline driver (see Fig. 6)
-PLEASE ENQUIRE
53
SL560C
ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise stated):
Frequency 30 MHz
Vee 6V
Rs = RL = 500
TA = 25°C
Test Circuit: Fig. 6
Value
Units
Characteristic
Small signal voltage gain
Gain flatness
Upper cut-off frequency
Output swing
Min.
Typ.
Max.
11
14
±1.5
250
+7
+11
1.8
3.5
20
17
+5
Noise figure (common emitter)
Supply current
30
CIRCUIT DESCRIPTION
15
Three high performance transistors of identical geometry are employed. Advanced design and processing
techniques enable these devices to combine a low base
resistance (Rbb') of 17 ohms (for low noise operation)
with a small physical size - giving a transition frequency, fT, in excess of 1 GHz.
The input transistor (TR1) is normally operated in
common base, giving a well defined low input impedance. The full voltage gain is produced by this transistor and the output voltage produced at its collector is
buffered by the two emitter followers (TR2 and TR3).
To obtain maximum bandwidth the capacitance at the
collector of TR1 must be minimised. Hence, to avoid
bonding pad and can capacitances, this point is not
brought out of the package. The collector load resistance
of TR1 is split, the tapping being accessible via pin 5. If
required, an external roll-off capacitor can be fixed to
this point.
The large number of circuit nodes accessible from the
outside of the package affords great flexibility, enabling
the operating currents and circuit configuration to be
optimised for any application. In particular, the input
transistor (TR1) can be operated in common emitter
mode by decoupling pin 7 and using 6 as the input. In
this configuration, a 2 dB noise figure (Rs = 200 Q) can
be achieved. This configuration can give a gain of 35dB
with a bandwidth of 75 M Hz (see Figs. 8 and 9)or, using
feedback, 14dB with a bandwidth of300 MHz (see Figs.
10and11).
Because the transistors used in the SL 560C exhibit a
high value of fT, care must be taken to avoid high
frequency instability. Capacitors of small physical size
should be used, the leads of which must be as short as
possible to avoid oscillation brought about by stray
inductance. The use of a ground plane is recommended.
Further applications information is avaiable in the
'Broadband Amplifier Applications' booklet.
54
Conditions
dB
dB
MHz
dBm
dBm
dB
dB
mA
10 MHz - 220 MHz
Vee = 6V} See Fig. 5
Vee = 9V
Rs = 2000
Rs = 500
-
t--~..............
""
~
--
TA. -
z
~
\
~ ~(b)
"-25°C
Vee -'-- 6V
POUT . . :: (a)
<
CJ
--
\.~
\
~5dBm
(b)OdBm
~
\
\
\(a)
\
II
I
30
FREQUENCY (MHz)
Fig. 4 Frequency response, small signal gain
- '"
-r-I'-
"'-
,(b)
r---...
..............
T" = +-25°C
Vee = (a)6V
(b)9V
"-
~
"
o
10
30
100
200
300
FREQUENCY (MHz)
Fig. 5 Frequency response, output capability (loci of maximum
output power with frequency, for 1dB gain compression)
SL560C
TYPICAL APPLICATIONS
1-8
, - - - - _ - - - + 6V
TA' +2S"C
vce , 101 3 V
Ibl 6V
lei 9 V
1-6
Q:
~,on
~
....
--
101
r-1-4
:)
a..
50.0.. INPUT
~
o---Jt-----'
.......
//
~:...-
/
......:: /
Ibl
./
1·2
lei
Gain14dB
Bandwidth 220 MHz (Pout=1 mW. 50 0)
200 MHz (Pout=5mW. 50 0)
Input SWR 1.5:1
10
Fig. 650 0 line driver. The response of this configuration is shown
in Fig. 4.
100
FREQUENCY
~OO
300 400
(MHz)
Fig. 7 Input standing wave ratio plot of circuit shown in Fig. 6
40
Vee
35
I
OUTPUT
30
~
IOn
~INPUT
-
25
vc~, "!V
~
r- Pout: -10dBm
"I'...
20
Z
~
"
15
L----~~+_-OV
o
Voltage gain 32dB at 6V
35dBat10V
Noise figure 1.8dB (RS=200 0)
Supply current 6mA at 6V
12mAat10V
Bandwidth 75 MHz (see Fig. 9)
10
20
30
50
100
200
300
500
1000
FREQUENCY (MHz)
Fig. 9 Frequency response of circuit shown in Fig. 8
Fig. 8 Low noise preamplifier
470~'n
U
vee
-
In
OUTPUT
o----f
0
o
4
\
0
1
0
IJ
60
101
In
J-------o
.......... Ibl
~ 10~~~++r---+-~~~-H+r---~--~~,+-r+++H
INPUT
z
:;;:
TA:: +25°C
Vee
0
I--l--+---+++++---.
101 6V
Ib I 9 V
H+-l-+++-----+--+-+--+-+-+-H-l
H+-l-+++-----+--+-+--+-+-+-H-l
Gain 13dB at Vcc=9V
-1dBat6MHzand300 MHz
100
FREQUENCY
Fig. 10 Wide bandwidth amplifier
200300400
(MHz)
Fig. 11 Frequency response of circuit shown in Fig. 10
55
SL560C
Fig. 12 Three-stage directly-coupled high gain low noise amplifier
t-- I---
./
60
-I---
''/
/,........,
CD
~
,....--........- - +2V
----- r------....
..........
40
"'-
r--
~I\.
.............
TA: +25°C
Vee' 101 4V
Ibl6V
lei 9V
"I~\
50
70
FREQUENCY
100
200
300
700
E~
600
500
400
.........
300
.........
......... ..........
0
200
........... t--,T05
alp..........
100
40
SO
60
70
so
...........
l'- r--.....
~
90
100
110
120
r---- r---...
130
140
150
TEMPERATURE lOCI
Fig. 15 Ambient operating temperature v. degrees centigrade
ABSOLUTE MAXIMUM RATINGS
Supply voltage (Pin 4)
Storage temperature
+15V
-55° C to 1500 C (CM)
-55° C to 125° C (DP)
150°C (CM) 125°C (DP)
Junction temperature
Thermal resistance
Junction-case
600 CIW (CM)
Junction ambient
220° CIW (CM) 2300 CIW (DP)
Maximum power dissipation
See Fig.15
-55°C to +125°C (CM) at 100mW
Operating temperature range
-55°C to +100°C (DP) at 100mW
56
Gain 13dB
Power supply current 3mA
Bandwidth 125 MHz
Noisefigure 2.5dB (RS=200 0)
(MHzl
Fig. 13 Frequency response of circuit shown in Fig. 12
~
INPUT
~~~-----~---OV
20
~
IOn
--11---0
\.
20
~
OUTPUT
Fig. 14 Low power consumption amplifier
SL561B/C
~~~~~JF~
_________________________
SL561 B, SL561 C
ULTRA LOW NOISE PREAMPLIFIERS
This integrated circuit is a high gain, low noise preamplifier
designed for use in audio and video systems at frequencies
up to 6MHz. Operation at low frequencies is eased by the
small size of the external components and the low 1/f noise.
Noise performance is optimised for source impedances
between 200 and 1kO making the device suitable for use with
a number of transducers including photo-conductive IR
detectors, magnetic tape heads and dynamic microphones.
The SL561 B is only available in the TO-5 package.
The SL561 C is only available in the Plastic package.
FEATURES
•
•
High Gain
Low noise
60dB
O.8nV/yf"Hz (Rs = 50n)
•
•
Bandwidth
Low Power Consumption
6MHz
10mW (Vee = 5V)
eMB
Fig.1 Pin connections (viewed from above) SL561 B
OUTPUT
APPLICATIONS
•
Audio Preamplifiers (low noise from low impedance
source)
•
•
Video Preamplifier
Preamplifier for use in Low Cost Infra-Red Systems
Vcc
GAIN SET
N/C
DPS
Fig.2 Pin connections (viewed from above) SL561C
f - - - H.........-(O)
f - - - - H..............-c OUTPUT
OUTPUT
C3
INPUT
--
~
--~
NOMHZ
".......r
_~OMHZ
~! - -
160MHz
I
INPUT 0-5V RMS
0-4
4-0
0-2
2-D
10
3D
FREQUENCY
60
100
(MHz)
Fig.3 Voltage gain v. frequency
200
SOD
-60
-40
-20
20
40
60
AMBIENT TEMPERATURE
80
100
120
(ac)
Fig.4 Maximum rectified output current v. temperature
83
SL1521
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Temperature = +22"C ± 2"C
Supply voltage = +5.2V
DC connection between input and bias pins.
Characteristic
ClrcuH
Voltage gain, f = 120MHz
Value
Min.
Typ.
11.5
10.8
11.2
10.6
315
300
Lower cut-off frequency
Propagation delay
SL1521A
SL1521C
SL1521A
SL1521C
SL1521A
SL1521C
All types
All types
Maximum rectified video output
current
SL1521A
SL1521C
0.95
0.90
Variation of gain with supply voltage
Variation of maximum rectified
output current with supply voltage
Maximum input signal before overload
Noise figure
Supply current
Maximum RF output voltage
All types
All types
1.0
30
All types
1.5
3
15.0
Voltage gain, f = 160MHz
Upper cut-off frequency
All types
All types
10.0
1.0
Max.
12.5
13.1
12.8
13.4
350
350
6
0.6
10
1.05
1.20
Unhl
CondlUons
dB
j3mV rm. input
50 ohms source
dB
8pF load + 5000
dB
dB
MHz
50 ohms source
MHz
MHz 50 ohms source
ns
\ f ~ 120MHz
0.5V rms input
8pF load, 500 ohms in
parallel
mA
mA
dBN
%N
4.5
20.0
Vrms
dB
mA
V p-p
See note below
f = 120MHz, source
resistance optimised
f = 120MHz
Operating Notes
l---
The amplifiers are intended for use directly coupled, as
shown in Fig.7.
The seventh stage in an untuned cascade will be
giving virtually full output on noise.
Noise may be reduced by inserting a single tuned
circuit in the chain. As there is a large mismatch between stages a simple shunt or series circuit cannot be
used. The choice of network is also controlled by the
need to avoid distorting the logarithmic law; the network must give unity voltage transfer at resonance. A
suitable network is shown in Fig. 9. The value of C1
must be chosen so that at resonance its admittance
equals the total loss conductance across the tuned
circuit.
A simple capacitor may not be suitable for decouplillg
the output line if many stages and fast rise times are
required.
Values of positive supply line decoupling capacitor
required for untuned cascades are given below.
Smaller values can be used in high frequency tuned
cascades.
The amplifiers have been provided with two earth
leads to avoid the introduction of common earth lead
inductance between input and output circuits. The
equipment designer should take care to avoid the
subsequent introduction of such inductance.
V
f = 120 MHz
RS =450"
-40
-20
20
40
60
TEMPERAT URE
80
100
120
(OC ,
Fig.5 Typical noise figure v. temperature
12
10
~
T=-5S OC -
--
I - -~
------
--
r-Number of stages
T=+25°C-T=+lr OC -
6ormore
Minimum capacitance
20
40
60
80
100
FREQUENCY
120
140
160
(MHz I
Fig.6 Input admittance with open-circuit output
84
180
200
30nF
5
4
10nF 3nF
3
1nF
SL 1521
--~---- OUTPUT
.l
OUTPUT
DECOUPLING
Fig.7 Direct coupled amplifier
FROM
STAG~
Ih
Cl
-1. . .---1-.----
---It-1
T
=*=
~
TO(n+lllhSTAGE
(BIAS AND INPUT
PINS LlNKEDI
DC BLOCKING
CAPACITOR
Fig.B Suitable interstage tuned circuit
85
SL 1521
86
SL1523C
SL1523C
300MHz DUAL WIDEBAND LOGARITHMIC AMPLIFIER
The SL 1523 C consists of two SL1521 's in series,
and is intended to reduce the package count and
improve the packing density in logarithmic strips
at frequencies up to 200 MHz.
Absolute Maximum Ratings
(Non-Simultaneous)
The absolute maximum ratings are limiting values
above which operating life may be shortened or
satisfactory performance may be impaired.
-55°C to + 175°C
Storage temperature range
Operating temperature
-55°C to + 125°C
Chip operating temperature:
150°C
Chip-to-ambient thermal
resistance
300°C/W
Chip-to-case thermal
resistance
95° C/W
Maximum instantaneous voltage at
video output
Supply voltage
eM6
Fig. 1
Pin connections (bottom view)
+12V
+ 9V
ISO
2
~----_--_-....--C:::::::J---(J +S.2V
1000p
t--+--t-----t--+---/
""
~
1
-JOMHz
r-
I
60MHz
----
'\..
100 MHz
10 MHz
--- -
/lL
/
/
./
30 MHz
1~MHZ
rINPUT-0·5V RMS
as
02
INPUT SIGNAL IV,ms)
Fig. 4
Rectified output current v. input signal
so
so
100
AMBIENT TEMPERATURE 1°C)
Fig. 5
--
-
Maximum rectified output current v. temperature
-
V~
-
T
I
-~5OC
T
-~5OC
1
t.60MHz
R.. 4i°Jl.
r-f-T
4
B
-60
-40
-20
20
40
60
80
100
120
140
o
10
TEMPERATURE (OCI
Fig. 6
90
Typical noise figure v. temperature
--------
cONLcTANcl.0.2mJho
OVER THE FREQUENCY RANGE
-r
20
5OC
~
,...--
30
40
50
60
70
80
FREQUENCY (MHz)
Fig. 7
-
~
Input admittance with open circuit output
90
100
FROM nth
STAGE
r + - - - - . . - + - - - - -___+--..-o0UTPUT
T t--1..,----1.,--C11
TOln.l)lhSTAGE
IBIAS
AND INPUT
PINS LINKED
I
RI
.,
T
OUTPUT
Fig. 9
Fig. 8
SL1613C
T
I -
D.C BLOC KING
CAPACITOR
Suitable interstage tuned circuit
Direct coupled amplifiers
OPERATING NOTES
The amplifiers are intended for use directly coupled, as
shown in Fig. 8.
The seventh stage in an untuned cascade will be giving
virtually full output on noise.
Noise may be reduced by inserting a single tuned circuit
in the chain. As there is a large mismatch between stages a
simple shunt or series circuit cannot be used. The choice of
network is also controlled by the need to avoid distorting
the logarithmic law; the network must give unity voltage
transfer at resonance. A suitable network is shown in Fig. 9.
The value of C1 must be chosen so that at resonance its
admittance equals the total loss conductance across the
tuned circuit. Resistor R1 may be introduced to improve
the symmetry of filter response, providing other values are
adjusted for unity gain at resonance.
A simple capacitor may not be suitable for decoupling
the output line if many stages and fast rise times are required.
Values of positive supply line decoupling capacitor required for untuned cascades are given below. Smaller
values can be used in high frequency tuned cascades.
The amplifiers have been provided with two earth leads
to avoid the introduction of common earth lead inductance
between input and output circuits. The equipment designer
should take care to avoid the subsequent introduction of
such inductance.
Number of stages
I
Minimum capacitance
6 or more
5
4
3
30nf
10nF
3nF
1nF
The 500pF supply decoupling capacitor has a resistance
of, typically, 1on. It is a junction type having a low breakdown voltage and consequently the positive supply current
will increase rapidly if the supply voltage exceeds 7.5V
(See Absolute Maximum Ratings).
INPUT o---~iH-"f
le1 - 9
VIDEO
OUTPUT
= SL 1613C
Centre frequency
Dynamic Range
Video rise time
Bandwidth
Output voltage
Typical log accuracy
60MHz
-75dBm to +15dBm
70nSec
approx.20MHz
o -1.5V
±2dB
Fig. 10 Circuit diagram of low cost strip
91
SL1613C
92
SL2363/SL2364
SL2363C & SL2364C
VERY HIGH PERFORMANCE TRANSISTOR ARRAYS
The SL2363C and SL2364C are arrays of transistors
internally connected to form a dual long-tailed pair with tail
transistors. They are monolithic integrated circuits
manufactured on a very high speed bipolar process which
has a minimum useable fT of 2.5GHz, (typically 5GHz).
The SL2363 is in a 10 lead T05 encapsulation.
The SL2364 is in a 14 lead DIL plastic encapsulation and a
high performance Dilmon encapsulation.
FEATURES
•
•
•
Complete Dual Long-Tailed Pair in One Package.
Very High fT - Typically 5 GHz
Very Good Matching Including Thermal Matching
SL2363C
CM10
SL2364C
DC14
DP14
APPLICATIONS
•
•
•
•
•
Wide Band Amplification Stages
140 and 560 MBit PCM Systems
Fibre Optic Systems
High Performance Instrumentation
Radio and Satellite Communications
Fig. 1 Pin connections (top view)
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = 22°C ±2°C
Characteristics
BVCBO
LVCEO
BVEBO
BVCIO
hFE
fT
ll. VBE (See note 1)
ll.VBE/TAMB
CCB
CCI
Value
Min.
10
6
2.5
16
20
2.5
Typ.
Max.
20
V
V
V
V
9
5.0
40
SO
5
2
-1.7
0.5
1.0
Units
5
0.8
1.5
GHz
mV
mVrC
pF
pF
Conditions
IC= 10flA
Ie =5mA
IE = 10flA
Ie = 10flA
Ie = SmA, VCE = 2V
Ie (Tail) = SmA, VCE = 2V
IC (Tail) = S rnA, VCE = 2V
IC (Tail) = SmA, VCE = 2V
VeB= 0
VCI = 0
93
SL2363/SL2364
TYPICAL CHARACTERISTICS
/
o
o
/
-~
....-
- -.......
1·0
"
~
'T NORMALISED AT .20·C
VCE • 2V
le· 4 ·5mA
"~
0·7
6
"
10
Ic(mA)
Fig. 2 Col/ector current
60
The substrate should be connected to the most negative
pOint of the circuit to maintain electrical isolation between
the transistors.
94
+20
.60
Fig. 3 Chip temperature
Maximum individual transistor dissipation 200mW
Storage temperature
-55°C to +150 o C
Maximum junction temperature
+150 o C
Package thermal resistance (OC/w):
Chip to case
65 (CM10)
Chip to ambient 225 (CM10) 175 (DP14)
VCBO = 10V, VEBO = 2.5V, VCEO = 6V, VCIO = 15V,
-20
TEMPERATURE (OC)
ABSOLUTE MAXIMUM RATINGS
Ie
(anyone transistor) = 20mA
+100
+140
SL2521
AUGUST 1985
__ Semiconductors
PLESSEY _ _ _ _ _ PRELIMINARY
_ _ _ _INFORMATION
_ _ __
Preliminary Information is issued to advise Customers of potential new products which are designated 'Experimental' but are, nevertheless, serious development
projects and is supplied without liability for errors or omissions. Details given may change without notice and no undertaking is given or implied as to current orfuture
availability.
Customers incorporating 'Experimental' product in their equipment designs do so at their own risk. Please consult your local Plessey Semiconductors sales outlet for
details of the current status.
SL2521 EXP
1.3GHz DUAL WIDEBAND LOGARITHMIC AMPLIFIER
The SL2521 is a revolutionary monolithic integrated circuit
designed on an advanced 3 micron oxide isolated bipolar
process. The amplifier is a successive detection type which
provides linear gain and accurate logarithmic signal
compression over a wide bandwidth.
When six stages (three SL2521s) are cascaded the strip
can be used for IFs between 30-650MHz whilst achieving
greater than 65dB dynamic range with a log accuracy of
<± 1.0dB. The balanced limited output also offers accurate
phase information with input amplitude. One log strip
therefore offers limited IF output, phase and video
information,
>
§:
CI
Z
'"
~
§:
§:
5
5
§ ~
-
§:
>
:!
IF INPUT (B) 19
13 OfT. OUTPUT (B)
IF INPUT (B) 20
12 R SET (B)
GND 1
11 GND (SUBSTRATE)
IF OUTPUT (A) 2
FEATURES
•••
•
IF OUTPUT (A) 3
1.3GHz Bandwidth (-3dB)
Balanced IF Limiting
3ns Rise Times/Sns Fall Times (Six Stages)
20ns Pulse Handling (Six Stages)
INDEX/
CORNER
9 DET. OUTPUT (A)
:;:
CI
ill
:;: :;: :;: :;:
~
~ ~
!!
5
§
•
Temperature Stabilised
•
Full Military Temperature Range/Surface Mountable
APPLICATIONS
•
•
•
10 R SET (A)
i
Fig.1 Pin connections - top view
FUTURE DEVELOPMENTS
Ultra Wideband Log Receivers
Channelised Receivers
Monopulse Apr:;lications
It is the intention of Plessey Semiconductors Ltd. to offer
the SL2521 EXP fully guaranteed over the temperature range
-55° C to + 125° C, with a second variant guaranteed over
-30°C to +85°C.
I-------------------------~
I
~CI
I
II
171 ~~
I
I
131 DETECTED
OUTPUT
161
151 \ IF OUTPUTS
I
1
I
IN~~TS{ 120
I
~-------+-----~
I
I
L
~--+----------~'__ _1~2QIEXTERNAL
L...---r--....
.
I
R SET
180 GROUND
-------------------------~
Fig,2 Circuit diagram (single stage B only)
95
SL2521
DESCRIPTION
Logarithmic and limiting amplifiers are used e)C.~ensively in
radar and EW equipment, where phase performance and
narrow pulse handling capability are essential, coupled with
log accuracy (linearity) and wide dynamic range.
The video output is useable up to 600MHz and offers
excellent temperature tracking. Due to the compact design,
fast rise and fall times can be achieved and the Ie does not
suffer from 'pulse stretching' as with many discrete hybrid
log modules.
ELECTRICAL CHARACTERISTICs'
Test conditions (unless otherwise stated):
Vee = 6V Rs = 500 RL = 1kO; For single stage
Characteristic
Value
Typ.
Min.
Small signal gain
IF upper cut-off frequency
Detected output (bandwidth)
Lower cut-off frequency
Temperature variation detected output
Temperature variation of IF gain
Ripple in band
Supply current
9.5
10
1.3
600
30
±5
±0.2
±0.25
40
Units
Max.
10.5
Conditions
f = 300MHz : T amb = 25° C
-3dB wrt 200MHz
50 % output current wrt 200MHz
dB
GHz
MHz
-55° C to +125° C
-55°C to +125°C
100 to 400MHz
%
dB
dB
mA
RF
INPUT
DETECTED
OUTPUT
Fig.3 Schematic diagram showing configuration of SD amplifier
LOGARITHMIC LINEARITY/ACCURACY
6oo?-----------------------------,
100MHz....... 4--:[ 500
-
......
...
I-
~
..........
450MHz
iii'
400 l--1o------:r''''.........::.,...- - - - - - - - i + 1
°
::J
0
C
300
t;
200
W
tl
C
-1
;0
£Z:
£Z:
W
g
-55
-45
-35
-25
-15
-5
15
INPUT LEVEL (dBm)
Fig.4 Detected output and logarithmic linearity at 4S0MHz.
Detected output at 100MHz also imposed (6-stage strip)
+1
;0.5
- H------ --~--"::- ----\ -- -0.5
-1
I
I
I
100
-65
96
\
-1\.--- -;:;, --- - --~-~--
oJ
o~~~~~~--~--~--~--~~~
100MHz
-55
i\
-45
-35
-25
-15
-5
~
~
ffi
Cl
9
I
l
-65
iii'
15
INPUT LEVEL (dBm)
Fig.S Logarithmic linearity at 100MHz showing greater than
62dB of dynamic range with accuracy of ±O.5dB (6-stage strip)
SL2521
TYPICAL CHARACTERISTICS FOR 6-STAGE STRIP (as shown In Flg.3)
0.8
i
~
0 II
'"
~ ·3
~
u..
~ t:::-
~
·6
a:
~ 0.5
~
00.4
C
t
A
0.3
~ 0.2
L.........II
c
100
200
300
400
500
FREQUENCY(MHz)
700
600
0.1
·80
Fig.6 IF bandwidth measured from output 1.
Output 2 terminated into SOO
·50
·40
·30
·20
INPUT LEVEL (dBm)
·10
.,.10
0.6
~
C
:::I 0.5
LIJ
.50oL~ V~
~
5 If
Q.
~
0
:::I
0
:::&
~
·60
Fig.9 Video output v. CW input at 60, 120, 4S0 and 600MHz
at 2SoC
i
Q.
·70
~~
~V
~~
60 &
120MHz
4S0MHz
600MHz
·3
""""1'\
LIJ
C
:; ·6
100
200
300
400
500
FREQUENCY(MHz)
600
0.4
~
C
LIJ
t
0.3
IiiC
0.2
LIJ
700
~
0.1
·80
Fig.7 Video bandwidth
...,. . . . V
·70
·60
~
~OC
.,.50'C
·50
·40 ·30
·20
INPUT LEVEL (dBm)
-10
·10
Fig.10 Video output v. temperature at 4S0MHz
30~
__________________________________-,
til 20
LIJ
W
a:
Cl
w
0:
o0:
0:
W
J'f'
1/
·20
·70
·60
10
e.
I-p
w ·10
VI
'" ·20
:J:
Q.
·50
·40
·30
·20
·10
·'OdBm
·60dBm
·50dBm
·40dBm
-'-10
INPUT LEVEL (dBm)
Fig.8 IF limiting v. temperature with CW input at 4S0MHz
·30-l-_--r_ _.....-_---,_ _.....-_---,_-'-'....,..._~
600
100
200
300
400
500
700
FREQUENCY (MHz)
Fig.11 Departure from linear phase of a 6·stage SO log strip
97
SL2521
OV
DETECTED
r-------4_~------_+_.------~~~------4_~------~~~~--_oOUTPUT
NB. PIN 11 ON EACH
SL2521 MUST BE
CONNECTED TO THE
MOST NEGATIVE POINT.
-6V----+-----'
-6V
;,;, 100
RESISTOR VALUES IN OHMS
ALL CAPACITORS 1nF UNLESS OTHERWISE STATED
Fig. 12 Circuit diagram for 6-stage log strip (results shown in Figs. 4 to 11 were achieved with this circuit)
98
SL3046
SL3046C
GENERAL PURPOSE NPN TRANSISTOR ARRAY
The SL3046C is a monolithic array of five general purpose
transistors arranged as a differential pair and three isolated
transistors.
FEATURES
•
•
•
•
•
5 General Purpose Monolithic Transistors
Good Thermal Tracking
Wide Operating Current Range
Suitable for Operation from DC to VHF
Low Noise Performance 3.5dB at 1kHz
DP14
Fig. 1 Pin connections
0·8
LV
125
VeE" 3V
/
100
/"
v
--
/
VCE
/
=3v
y
/
,/'
~
J
V
/
>
!
w
ID
V
/
>
-o/'
/'
-----
-
r-- r- -t-
/'
/""
0·1
0'1
100
COLLECTOR CURRENT (rnA)
Fig.2 Transition frequency (fT ) v. col/ector current (Vcs=2V, f= 200MHz)
101
SL3127
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
T amb
= 22" C ±
2° C
Characteristic
Static characteristics
Collector base breakdown
Collector emitter breakdown
Collector substrate breakdown (isolation)
Base to isolation breakdown
Base emitter voltage
Collector emitter saturation voltage
Emitter base leakage current
Base emitter saturation voltage
Base emitter voltage difference,
all transistors
Input offset current
Temperature coefficient of I:::. VBE
Symbol
BVceo
LV CEO
BVclo
BVeio
VeE
VCE(SAT)
IEeo
VBE(SAT)
I:::.VeE
Min.
20
15
20
10
0.64
Value
Typ.
30
18
55
20
0.74
0.26
0.1
0.95
0.45
= 1mA
95
100
100
0.3
O.S
100
0.4
0.4
0.8
nA
nA
nA
pF
pF
pF
VCE = SV, Ic
VCE = SV, Ie
VeE = SV, Ic
VCB = 16V
VCI = 20V
VBI = 5V
VEB = OV
VCB = OV
VCI = OV
1.S
3.S
1
GHz
dB
kHz
Static forward current ratio
HFE
Collector base leakage
Collector isolation leakage
Base isolation leakage
Emitter base capacitance
Collector base capacitance
Collector isolation capacitance
ICBO
IClo
IBIO
CEe
Cce
CCI
fT
NF
ABSOLUTE MAXIMUM RATINGS
The absolute maximum ratings are limiting values above
which operating life maybe shortened or specified parameters may be degraded.
All electrical ratings apply to individual transistors.
Thermal ratings apply to the total package.
The isolation pin (substrate) must be connected to the
most negative voltage applied to the package to maintain
electrical isolation.
VCB == 20 volt
VEB == 4.0 volt
VCE == 15 volt
VCI == 20 volt
Ic
20mA
Maximum individual transistor dissipation 200 mWatt
Storage temperature -55°C to 150°C
Max junction temperature 150°C
=
Package thermal resistance (OC/watt):Package Type
DC16
DP1S
Chip to case
40
Chip to ambient
120
180
NOTE:
If all the power is being dissipated in one transistor, these
thermal resistance figures should be increased by
100°C/watt.
102
Ic = 1~A, IE = 0
Ie = 1mA, IB = 0
Ie = 1~A, IR = IE = 0
IB = 1OpA, Ic = IE = 0
VeE = 6V, Ie = 1mA
Ic = 10mA, IB == 1mA
VEB = 4V
Ie = 10mA, IB == 1mA
VCE == 6V, Ic = 1mA
mV/oC VCE == 6V, Ic
aVeE
Dynamic characteristics
Transition frequency
Wideband noise figure
Knee of 1/f noise curve
V
V
V
V
V
V
JJA
V
mV
-1.6
Temperature coefficient of VeE
35
35
40
5
Conditions
= 1mA
= 1mA
0.2
2.0
ar
0.84
0.5
1
Units
JJA VCE = 6V, Ic
JJvrc VCE == 6V, Ic
I:::.IB
aI:::. VBE
aT
Max.
3
VCE
= 5mA
= 0.1mA
= 1mA
= SV, Ic = 5mA
f ~ 60MHZ! V"" ~ 6V
Ic = 2mA
Rs = 2000
SL3127
10
--
("
r---
1
' -
o·1
12
14
-
16
18
COLLECTOR BASE VOLTAGE (V)
Fig.3 Transition frequency (tT) v. col/ector base voltage
(Ie
= 5mA,Frequency = 200MHz)
3·2
2·0
J:I:
.......
16
----V
"".,.-
.---
-----
-------~
V--
~
~
~ i'...
-r--....~~
~
Vee =sv
Ie =SmA
Vee .2V
Ie = SmA
~~
"'
/"
0·8
0'4
80
60
40
20
20
40
60
80
100
120
140
160
TEMPERATURE (oC)
FigA Variation of transition frequency (tT) with temperature
103
70
60
"...,...
-
~
t-
....... r-.,
50
~ 40
:z:
30
20
10
100n~
10~A
100~A
10mA
lmA
COLLECTOR CURRENT
Fig.S DC current gain v. col/ector current
300
~
.~ 200
~
\1"
t---...
~,~
~
10QMHz
~
--1GHz
FREQUENCY
Fig.6 ZI1 (derived from scattering parameters) v. frequency (Zll,c" rbb)
104
SL3145
SL3145C,E
1.2GHz HIGH FREQUENCY NPN TRANSISTOR ARRAYS
The SL3145C is a monolithic array of five high frequency
low current NPN transistors. The SL3145C consists of 3
isolated transistors and a differential pair in a 14 lead DIL
package. The transistors exhibit typical fTs of 1.6GHz and
wideband noise figures of 3.0dB. The device is pin
compatible with the SL3045C. The SL3145E has guaranteed
CeB and fT figures.
FEATURES
•
•
fT Typically 1.6 GHz
Wideband Noise Figure 3.0dB
•
VSE Matching Better Than 5mV
DC14
DP14
Fig.1 Pin connections SL3145
APPLICATIONS
Ordering information
•
Wide Band Amplifiers
•
•
•
PCM Regenerators
High Speed Interface Circuits
High Performance Instrumentation Amplifiers
•
High Speed Modems
SL3145C-DC
SL3145C-DP
SL3145E-DP
Ceramic/Metal
Plastic
Plastic
10
V-.-
f.--
_r--
-I""-
r-t-
~t-
./
/'
/
0·1
0'1
10
100
COLLECTOR CURRENT (mA)
Fig.2 Transition frequency (fr) v. col/ector current (VeB = 2V, f = 200MHz)
105
SL3145
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = 22°C ± 2°C
Characteristic
Static characteristics
Collector base breakdown
Collector emitter breakdown
Collector substrate breakdown
(isolation)
Base to isolation breakdown
Base emitter voltage
Collector emitter saturation voltage
Emitter base leakage current
Base emitter saturation voltage
Base emitter voltage difference,
all transistors except TR1,TR2
Base emitter voltage difference
TR1, TR2
Input offset current
(except for TR1, TR2)
Input offset current TR1, TR2
Temperature coefficient of l:J.VBE
Temperature coefficient of VBE
Min.
Value
Typ.
BVcBo
LVCEO
BVclo
20
15
20
30
18
55
BVBIO
VBE
VCE(SAT)
lEBO
VBE(SAT)
l:J.VBE
10
0.64
20
0.74
0.26
0.1
0.95
0.45
Symbol
Max.
Units
V
V
V
Ie
Ic
Ic
= 10J.lA,IE = 0
= 1mA,IB = 0
= 10J.lA,IR = IE = 0
5
V
V
V
J.lA
V
mV
IB = 10J.lA,lc = IE = 0
VCE = 6V,lc = 1mA
Ic = 10mA,IB = 1mA
VEB = 4V
Ic = 10mA,IB = 1mA
VCE = 6V,lc = 1mA
0.84
0.5
1
l:J.VBE
0.35
5
mV
VCE
= 6V,lc = 1mA
l:J.IB
0.2
3
J.lA
VCE
= 6V,lc = 1mA
l:J.IB
al:J.VBE
0.2
2.0
2
VCE
J.lA
J.lV;oC
= 6V,lc = 1mA
aVBE
-1.6
mV;oC VCE
= 6V,lc
aT
aT
Static forward current ratio
Collector base leakage
Collector isolation leakage
Base isolation leakage
Emitter base capacitance
Collector base capacitance
SL3145C
SL3145E
Collector isolation capacitance
Dynamic characteristics
Transition frequency
SL3145C
SL3145E
Wideband noise frequency
Conditions
HFE
ICBo
ICIO
IBIO
CEB
40
CCB
100
0.3
0.6
100
0.4
0.4
0.4
0.8
CCI
1.6
fT
Knee of 1/f noise curve
nA
nA
nA
pF
VCE = 6V,lc = 1mA
VCB = 16V
VCI = 20V
VBI = 5V
VEB = OV
pF
pF
pF
VCB
VCB
VCI
3.0
GHz
GHz
dB
1
kHz
1.2
NF
1.1
= 1mA
= OV
= OV
= OV
VCE = 6V,lc = 5mA
VCE = 6V,lc = 10mA
VCE = 2V,Rs = 1kO
Ic = 100J.lA,f = 60MHz
VCE = 6V,Rs = 2000
Ic = 2mA
ABSOLUTE MAXIMUM RATINGS
The absolute maximum ratings are limiting values above
which operating life maybe shortened or specified parameters may be degraded.
All electrical ratings apply to individual transistors.
Thermal ratings apply to the total package.
The isolation pin (substrate) must be connected to the
most negative voltage applied to the package to maintain
electrical isolation.
VCB = 20 volt
VEB = 4.0 volt
VCE
15 volt
VCI = 20 volt
Ic = 20mA
Maximum individual transistor dissipation 200 mWatt
Storage temperature -55°C to 150°C
Max junction temperature 150°C
=
106
Package thermal resistance (OC/watt):Package Type
Chip to case
Chip to ambient
DC14
40
120
DP14
180
NOTE:
If all the power is being dissipated in one transistor, these
thermal resistance figures should be increased by
100°C/watt.
SL3145
10
2
1
--
I
-_ .. -
I---
1
16
COlLECTOR BASE VOLTAGE (V)
Fig.3 Transition frequency (fr) v. collector base voltage (Ie = SmA, frequency = 200MHz)
3·2
2·8
2'4
2·0
.........- i-"""
1·2
,/
V
./
...-
----/'"
--
~~
~
~
~
-
'"~~
Vea· 5V
-~
~
Vea .2V
Ie =SmA
~~
"
0·8
80
60
40
20
20
40
80
80
100
120
140
160
TEMPERATURE (oC)
Fig.4 Variation of transition frequency (fr) with temperature
107
SL3145
70
60
v
j....-
1-
t-..
F::::r--.
50
30
20
10
100~A
100nA
10mA
1mA
COLLECTOR CURRENT
Fig.5 DC current gain v. col/ector curent
300
~
100MHz
............
~
~
~
~
-I--
1GHz
FREQUENCY
Fig.6 Zl1 (derived from scattering parameters) v. frequency (Zl1~r66')
108
-to--
SL6270C
SL6270C
GAIN CONTROLLED PREAMPLIFIER
The SL6270C is a silicon integrated circuit combining the
functions of audio amplifier and voice operated gain
adjusting device (VOGAO).
It is designed to accept signals from a low sensitivity
microphone and to provide an essentially constant output
signal for a 50dB range of input. The dynamic range, attack
and decay times are controlled by external components.
PREAMP INPUT
eMS/S
FEATURES
•
•
•
•
Constant Output Signal
Fast Attack
Low Power Consumption
Simple Circuitry
Fig. 1 Pin connections. SL6270e - eM (bottom view)
AGC TIME CONST
PREAMP OUTPUT
Audio AGC Systems
Transmitter Overmodulation Protection
Tape Recorders
QUICK REFERENCE DATA
•
•
Supply Voltage: 4.5V to 10V
Voltage Gain: 52dB
MAIN AMP OUTPUT
2
7
Vee
3
6
OV
PREAMP INPUT
4
5
PREAMP INPUT
APPLICATIONS
•
•
•
Os
MAIN AMP INPUT
DPS
Fig. 2 Pin connections. SL6270e - DP (top view)
100n~c
;;r;; \
PREAMP
r-_~_~T~~lT 2 _
MAIN AMP
7 IN~T_ _ _ _ _ _ _ ..,
I
I
I
I
I
I
-----.A
,8
ABSOLUTE MAXIMUM RATINGS
Supply voltage: 12V
Storage temperature: -55°C to
MAIN AMP
OUTPUT
I
I
I
+ 125°C
I
I
________ J
1
AGe TIME
CONSTANT
Fig. 3 SL6270e block diagram
109
SL6270C
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Supply voltage Vee: 6V
Input signal frequency: 1 kHz
o
Ambient temperature: -30 e to +85°e
Test circuit shown in Fig. 4
Characteristic
Min.
Supply current
Input impedance
Differential input impedance
Voltage gain
Output level
THD
Equivalent noise input voltage
Value
Typ.
Max.
5
150
300
52
90
2
1
40
55
10
Units
mA
n
n
140
5
Conditions
Pin 4 or 5
dB
7'2/JV rms input pin 4
mVrms 4mV rms input pin 4
%
90mV rms input pin 4
3000 source, 400Hz to 25kHz bandwidth
/JV
.6V
EXTERNAL
4·7n
2·2~
10k
1--+---4--11
J--o OUTPUT
10~
11k ~ MIN LOAD)
.
10kO
Voltage gain = 6800
N.B.
If input not AC coupled the resistance
between pins 4 and 5 must be less than 10 ohms.
Fig. 4 SL6270C test and application circuit
APPLICATION NOTES
Voltage gain
The input to the SL6270C may be single ended or
differential but must be capacitor coupled. In the
single-ended mode the signal can be applied to either
input, the remaining input being decoupled to ground.
Input signals of less than a few hundred microvolts
rms are amplified normally but as the input level is
increased the AGC begins to take effect and the output
is held almost constant at 90mV rms over an input
range of 50dB.
The dynamic range and sensitivity can be reduced by
reducing the main amplifier voltage gain. The connection of a 1 k resistor between pins 7 and 8 will reduce
both by approximately 20dB. Values less than 6800
are not advised.
Frequency response
The low frequency response of the SL6270e is
determined by the input, output and coupling capacitors. Normally the coupling capacitor between pins 2
and 7 is chosen to give a -3dB point at 300Hz,
110
Upper frequency response 1OkO/4.7nF = 3kHz
Lower frequency response 6800/2.2flF = 300Hz
Fig. 5 SL6270C frequency response
corresponding to 2.2flF, and the other capacitors are
chosen to give a response to 100Hz or less.
The SL6270C has an open loop upper frequency
response of a few M Hz and a capacitor should be
connected between pins 7 and 8 to give the required
bandwidth.
Attack and decay times
Normally the SL6270e is required to respond
quickly by holding the output level almost constant as
the input is increased. This 'attack time', the time taken
for the output to return to within 10% of the original
level following a 20dB increase in input level, will be
approximately 20ms with the circuit of Fig. 4. It is
determined by the value of the capacitor connected
between pin 1 and ground and can be calculated
approximately from the formula:
Attack time = O.4ms/flF
The decay time is determined by the discharge rate of
the capacitor and the recommended circuit gives a
decay rate of 20dB/second. Other values of resistance
between pin 1 and ground can be used to obtain
different results.
SL6270C
v
90
v
I
co
60
o
v~== +6V, TA= +2S C, f
=1kHz
/
Z
it:
...: 50
V
::>
~
5
30
~
20
10)N
10mV
100mV
INPUT (RMS)
Fig. 6 Voltage gain (single ended input) (typical)
0
0
0
/
VSIII 8V, h 1kHz
a
/' V
0
/
i.--'V
V
0 ) - - - SECOND HARMONIC
0
I
THIRJ
H~RMON:C I
I
.L
V
i--+--
I
I
10
100
SINGLE ENDED INPUT
I mV RMS)
Fig. 7 Overload characteristics (typical)
g_
o z
IE e
Ul
C
-10
60
...
-20
Z
I
:z:
~ ~ -30
Se
I
L
vs-ev
~ ~-.o
V
ffi~
~ ~ -50
THIRD ORDER
i-'"
FIFTH ORDER
'-""""
V
/
~ !g
§-
-60
_
50
f'
III
~
!
~
40
...
~
~
30
0
10
-70
10
lao
SINGLE ENDED INPUT (mV RMS/
Fig. 8 Typicallntermodulation distortion (1.55 and 1.85kHz tones)
1kHz
10kHz
100kHz
lMHz
10MHz
FREOUENCY
Fig. 9 Open loop frequency response (typical)
111
SL6270C
112
SL6310C
SL6310C
SWITCHABLE AUDIO AMPLIFIER
The SL631 OC is a low power audio amplifier which
can be switched off by applying a mute signal to the
appropriate pin. Despite the low quiescent current
consumption of 5 mA (only O.6mA when muted) a
minimum output power of 400mW is available into an
SO load from a 9V supply.
NONINV, INPUT
INVINPUT
0
8
MUTE'S'
2
7
MUTE 'A'
EARTH
3
6
NC
OUTPUT
4
5
Vee
FEATURES
•
•
•
Can be Muted with High or Low State
Inputs
Operational Amplifier Configuration
Works Over Wide Voltage Range
DG8
DP8
Fig.1 Pin connections SL6310C - (top view)
.-------~-~-_ovcc
APPLICATIONS
•
•
•
Audio Amplifier for Portable Receivers
Power Op. Amp
High Level Active Filter
OUTPUT
8n
LOAD
QUICK REFERENCE DATA
•
•
•
Supply Voltage: 4.5V to 13.6V
Voltage Gain: 70dB
Output into SO on 9V Supply: 400mW
EARTH
Fig.2 SL6310C test circuit
ABSOLUTE MAXIMUM RATINGS
Supply voltage: 15V
Storage temperature: -55°C to
+ 125°C
113
SL631DC
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Supply voltage Vcc: 9V
Ambient temperature: -30°C to +S5°C
Mute facility: Pins 7 and S open circuit frequency = 1kHz
Characteristic
Value
Min.
Supply current
Supply current muted (A)
Supply current muted (B)
Input offset voltage
Input offset current
Input bias current (Note 1)
Voltage gain
Input voltage range
CMRR
Output power
THO
Typ.
40
40
400
5.0
0.55
0.6
2
50
0.2
70
2.1
10.6
60
500
0.4
Units
Max.
Conditions
mA
mA
mA
mV
nA
IlA
dB
V
V
dB
mW
7.5
1
0.9
20
500
1
%
3
Pin 7 via 1 OOk to earth
Pin S = Vcc
Rs::::; 10k
Vcc = 4.5V
Vcc = 13V
Rs::::;10k
RL = SO
POUT = 400mW,
Gain = 2SdB
NOTE
1.
The input bias current flows out of pins 1 and 2 due to PN P input stage
- - . - -_ _~----.-- ,2V
12V LAMP
INPUT
----{==::r---+-'l
Fig.3 SL6310 lamp driver
OPERATING NOTES
Mute facility
The SL6310C has two mute control pins to allow easy
interfacing to inputs of high or low levelS. Mute control 'A',
pin 7, is left open circuit or connected to a voltage within 0.65
volt of Vee (via a 100kO resistor) for normal operation. When
the voltage on pin 7 is reduced to within 1 volt of earth (via a
100kO resistor) the SL6310C is muted.
Mute control 'B', pin 8, is left open circuit or connected to a voltage less than 1 volt for normal operation: a
voltage greater than 2.5V on pin 8 mutes the device.
The input resistance at pin 8 is around 100kO and is
suitable for interfacing with CMOS.
Only one mute control pin may be used at any time;
the unused pin must be left open circuit.
Audio amplifier
As the SL631 OC is an operational amplifier it is easy
to obtain the voltage gain and frequency response
required. To keep the input impedance high it is wise
to feed the signal to the non-inverting input as shown
114
INPUT
---[=:1---'1
Fig.4 SL6310C servo amplifier
in Fig. 2. In this example the input impedance is
approximately 100kO. The voltage gain is determined
by the ratio (R3 +R4)/R3 and should be between 3 and
30 for best results. The capacitor in series with R3,
together with the input and output coupling capacitors,
determines the low frequency rolloff point. The upper
frequency limit is set by the device but can be restricted
by connecting a capacitor across R4.
The output and power supply decoupling capacitors
have to carry currents of several hundred milliamps and
should be rated accordingly.
Applications include hand-held radio equipment,
hi-fi headphone amplifiers and line drivers.
Operational amplifier
It is impossible to list all the application possibilities in a
Single data sheet but the SL6310C offers considerable
advantages over conventional devices in high output current
applications such as lamp drivers (Fig.3) and servo amplifiers
(FigA).
Buffer and output stages for signal generators are another
possibility together with active filter sections requiring a high
output current.
SL6310C
80
70
60
!
~
z
Z 68
<
<
"
"
40
20~------~------~------~
100
10k
66
/
/
/
/
62
100k
4
FREQUENCY (Hz)
12
VOLTAGE
Fig.5 Gain v. frequency
Iv)
Fig.6 Gain v. supply voltage
1500 .------...,.------,...----""'7'1
~
W
I-
~
i
ffi
1000 r----+-----+.r------i
Q
0-8
~
~
:I
~
~
I- 500/-----+--+-""""'-*"'---===---1
::;,
zw
0-4
0
a:
~
u
o
MUTE B PIN 8 TO SUPPLY
MUTE A PIN 7 TO EARTH BY 100k RESISTOR
o
4
8
VOLTAGE
12
o
Iv)
Fig.7 Supply current v. supply voltage
O~---~~------~------~
o
4
8
VOLTAGE
Iv)
Fig.B Output power v. supply voltage at 5 % (max) distortion
115
SL6310C
116
SL6440C
SL6440C
HIGH LEVEL MIXER
The SL6440 is a double balanced mixer intended for use in
radio systems up to 150MHz. A special feature of the circuit
allows external selection of the DC operating conditions by
means of a resistor connected between pin 11 (bias) and Vcc.
When biased for a supply current of 50mA the SL6440 offers
a 3rd order intermodulation intercept point of typically
T30dBm, a value previously unobtainable with integrated
circuits. This makes the device suitable for many
applications where diode ring mixers had previously been
used and offers the advantages of a voltage gain, low local
oscillator drive requirement and superior isolation.
The SL6440C (in a 16-lead OIL plastic package) is
specified for operation from -300 C to +85 0 C.
OUTPUT A
3
LOCAL OSCILLATOR INPUT
5
13
SIGNAL INPUT A
12
SIGNALINPUT B
11
PROGRAMMING CURRENT INPUT
DP16
Fig.1 Pin connections - top view
FEATURES
•
•
•
ABSOLUTE MAXIMUM RATINGS
Supply voltage and output pins: 15V
(Derate above 250 C: BmW/" C)
Storage temperature range: -650 C to +1500 C
Programming current into pin 11: 50mA
+30dBm Input Intercept Point
+15dBm Compression Point (1 dB)
Programmable Performance
APPLICATIONS
•
•
•
PACKAGE THERMAL DATA
Mixers in Radio Tmnsceivers
Phase Comparators
Modulators
Thermal resistance: Junction-Am bient: 1250 CIW
Junction-Case: 400 CIW
Time constant: Junction-Ambient: 1.9 mins.
Max. chip temperature: 1500 C
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Vcc1 = 12V; Vcc2 = 10V; Ip = 25mA; -30 C to +85 C (SL6440C)
Local oscillator input level = OdBm' Test circuit Fig 2
D
D
Characteristic
Signal frequency 3dB point
Oscillator frequency 3dB point
3rd order input intercept point
Third order intermodulation distortion
Second order intermodulation distortion
1dB compression point
Noise fjgure
Conversion gain
Carrier leak to signal input
Level of carrier at I F output
Supply current
Supply current (total from Vcc1 & Vcc2)
Local oscillator input
Local oscillator input impedance
Signal input impedance
Value
Min.
Typ.
100
100
150
150
+30
-60
-75
15
12
11
-1
Max.
-40
100
-25
7
60
250
1.5
500
1000
500
Conditions
Units
MHz
MHz
dBm
dB
dB
dBm
dBm
dB
dB
dB
dBm
mA
mA
mVrms
kO
0
0
~
Two OdBm input
Signals
Vcc1 = 15V Vcc2 = 12V
Vcc1 = 12V Vcc2 = 10V
Fig.B test circuit
50n load Fig.2
Test circuit Fig.8
See applications information
Ip = a
Ip
=
35mA
Single ended
Differential
NOTE Supply current in Pin 3 is equal to that in Pin 14 and is equal to Ip See over. Vpin11 ~ 3 Vbe ~ 2.1 V
117
SL6440C
CIRCUIT DESCRIPTION
The SL6440 is a high level mixer designed to have a linear
RF performance. The linearity can be programmed using the
I~ pin (11).
The output pins are open collector outputs so that the
conversion gain and output loads can be chosen for the
specific application.
Since the outputs are open collectors they should be
returned to a supply Vcc1 through a load.
The choice of Vcc1 is important since it must be ensured
that the voltage on pins 3 and 14 is not low enough to saturate
the output transistors and so limit the signal swing
unnecessarily. If the voltage on pins 3 and 14 is always
greater than Vcc2 the outputs will not saturate. The output
frequency response will reduce as the output transistors near
saturation.
Minimum Vcc1
(Ip x RL) + Vs + Vcc2
where Ip
programmed current
RL
DC load resistance
Vs
max signal swing at output
if the signal swing is not known:
minimum Vcc1
2 (Ip x RL) + Vcc2
In this case the signal will be limiting at theinput before the
output saturates.
The device has a separate supply (Vcc2) for the oscillator
buffer (pin 4).
The current (!p) programmed into pin 11 can be supplied
via a resistor from Vcc1 or from a current source.
The conversion gain is equal to
GdB
RL Ip
.
20 Log 56.6 Ip + 0.0785 for Single-ended output
=
GdB = 20 Log
56.62,:~ 6:0785 for differential output
Device dissipation is calculated using the formula
mW diss
where Va
Vp
2 Ip Va + Vp Ip + Vcc2 Diss
voltage on pin 3 or pin 14
voltage on pin 11
programming current (mA)
dissipation obtained from graph(Fig.5)
~
~
Ip
Vcc2 Diss o
As an example Fig. 7 shows typical dissipations assuming
Vcc1 and Va are equal. This may not be the case in practice
and the device dissipation will have to be calculated for any
particular application.
Fig. 4 shows the intermodulation performance against Ip.
The curves are independent of Vcc1 and Vcc2 but if Vcc1
becomes too low the output signal swing cannot be
accommodated, and if Vcc2 becomes too low the circuit will
not provide enough drive to sink the programmed current.
Examples are shown of performance at various supply
voltages.
-11a COMPRJSSION POlT
LOCAL OSCILLATOR - 30MHz OdBm
RF INPUT - 40 111Hz
-10
OUTPU:l;
IF""10MHz
E
~
VCC20----...--.......-'9
INPUT
"-
~
+10
L07
5
0'001p
I
+{~~~~:~~~
*{~~~~:~~~
"-
50
20
10
f 1~2 I YPICdl dppllcatloll dllei test ClfClIIl
30
40
---
;
+
50
70
(mA)
TOTAL OUTPUT CURRENT (21.)
Fiy.J COIlIPIOSSIOII p01II1 V. lolal oulpul CUllenl
+10~--~----~--~--~r---~--~----~--~
WANTED OUTPUT
./
1
LO·31.4MHzOdBm
I---I--+--+---+--\-- RF IP' ~g.~~M~~~~Bm
/~
/
V
./
V
./V
-301---~-~~---+---1----~--~~--~--~
V
1
./'
89m
"
n
~
~
~
Vcc2(VOLTS)
Fig.5 Supply current v. Vcc2 (Ip
-800~--~--~10~--~1S~--~~~--~~~--~~~--~--~
TOTAL OUTPUT CURRENT (21.) (mA)
Fig.4 /ntermodu/ation v. programming current
118
0)
The current in pin 14 isequal to the current in pin 3which is
equal to the current in pin 11.
SL6440C
~--~--~~~HH+----+--+-+-~++~-----r--'-'~
~
!;
-1
-2
~--~---'~~~f+I+---'~---1---1-+-t~-N,*'-T-- SIGNAL 10MHz HIGHER
\
~ -3
1\
THAN LOCAL OSCILLATOR
\
~ -4~---r--~~~HH+----+--+-+-r+++rHl\~1~~~~~"-H
i-s
N
J: -6
~
-7
\\
RF INPUTLEVEL OdBm
r-~~:~~}
I:j:
\
r- LOCAL OSCILLATOR INPUTLEVEL = OdBm
\
t-~++I+-----1---t--t-+++t-++---\-+--+-+-t-~ttI
+
-81--1,= 24mA
-9
\
r-~~~~ : ~~~}
*
~:: ~1--+ -r~+--tt-t-l-t-+-t++-_-_-_-_++-_-_+t--_+t---i:_t-\-t-+t-+HH-_-_-_-_-l-t-_-_-+-t-_-t-t-_+t--+-t-t-t-+-t-Hti
-i
10
100
1000
LOCAL OSCILLATOR FREQUENCY MHz
Flg.6 Frequency response at constant OLitput IF
APPLICATIONS
DESIGN PROCEDURE
The SL6440 can be used with differential or singleended inputs and outputs. A balanced input will give
better carrier leak. The high input impedance allows stepup transformers to be used if desired, whilst high output
impedance allows a choice of output impedance and
conversioh gain.
Fig. 2 shows the simplest application circuit. The input
and output are single-ended and Ip is supplied from Vcc1
via a resistor. Increasing RL will increase the conversion
gain, care being taken to choose a suitable value for Vcc1.
Fig. 8 shows an application with balanced input, for
improved carrier leak, and balanced output for increased
conversion gain. A lower Vcc1 giving lower device
dissipation can be used with this arrangement.
1. Decide on input configuration using local oscillator data.
If using transformer on input, decide on ratio from noise
considerations.
2. Decide on output configuration and value of conversion
gain required.
3. Decide on value of Ipand Vcc2 using intermodulation and
compression point graphs.
4. Using values of conversion gain, Vcc2, load and Ip
already chosen, decide on value of Vcc1.
5. Calculate device dissipation and decide whether
heatsink is required from maximum operating temperature
considerations.
I10UTPUT
1300
'/
/'
V /
1200
1100
Vce= VOLTAGE ON PINS 3,4 AND 14
1000
900
V ./"" ./
/
./
f- 8~C~~A!!.~HO~H~T!IN~ -/- ....V- i-. V- - /-
800
~
700
f=
--.
~ 600
f/)
C
Vee2
-Vee = 12V
-Vee = 10V
/V
!~
iii
-VCC = 14V
SOO
400
300
200
100
12SoC OPERATION
WlllIOUT HEATSI~
i-
~
/
./V V
V ~
~
/ / . / "7'V
v.::: ..-::::V /.. ~ ~
~ -::;::::. ~
--
-
F"'"
10
,.,
V r;;: ~ ,.,
- :::;: ~
./'"
",
V /' . . . V ......V
15
20
......
-Vee=8V
-Vee=6V
-vee=sv
RF
~
INPu;l
1,1.S+1.SXFMR
1111/
Fig.S Typical application circuit for highest performance
30
IP(mA)
Fig.7 Device dissipation v. Ip
119
SL6440C
120
SL6601
SL6601C
LOW POWER IF/AF PLL CIRCUIT FOR NARROW BAND FM
The SL6601 is a straight through or single conversion IF
amplifier and detector for FM radio applications. Its minimal
power consumption makes it ideal for hand held and remote
applications where battery conservation is important. Unlike
many FM integrated circuits, the SL6601 uses an advanced
phase locked loop detector capable of giving superior signalto-noise ratio with excellent co-channel interference
rejection, and operates with an IF of less than 1MHz.
Normally the SL6601 will be fed with an input signal of up to
17MHz: there is a crystal oscillator and mixer for conversion
to the IF amplifier, a PLL detector and squelch system.
CRYSTAL
1
CRYSTAL
2
MIXER DECOUPLE
3
2ND IFFILTER
4
2ND IF DECOUPLE
5
SQUELCH O/P
6
SQUELCH TRIGGER fiLTER
1
I
LQOP
fiLTER
12
VCOTIMING RESISTOR
FEATURES
••
••
•
VCO
TIMING
CAPACITOR
I
9
10
VCOTIMING RESlsrOR
----."..
DG18
DP18
High Sensitivity: 2jN Typical
Fig.1 Pin connections - top view
Low Power: 2·3mA Typical at 7V
Advanced PLL Detector
Available in Miniature 'Chip Carrier' Package
100% Tested for SINAD
APPLICATIONS
•••
QUICK REFERENCE DATA
Low Power NSFM Receivers
FSK Data Equipment
•
Supply Voltage 7V
Cellular Radio Telephones
•
50dS SIN Ratio
NOTE, RESISTIVE
IMPEDANCE
AT PIN 4 = 25kn(TYP), 36kn (MAX)
~'
"~"
'Ok
r----~:~--k------
'2
-----------l
I
I
I
I
I
I
I
I
IF
'On
Is
I
'~:~T --f1-:-::i>----1
AUDIO
OUTPUT
16
21
I
I
I
I
I
I
I
L - -
-EART!'7 -
MIXER
3 -
DECOUPLE
-
,:;;;,oon
4 FILTER 5 IF - - - DECOUPLE
,:;;;33P
,:;;;,oon
16YiiEcOUPLE -
J.
,:;;;,oon
Fig.2 SL6601 block diagram
7 saUELCH ADJUST
-
-
-
-
-
-
SOUELCH
OUTPUT
--.J
,..;;
121
SL6601
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Supply voltage Vcc : 7V
Input signal frequency: 10.7MHz, frequency modulated with a 1kHz tone with a ±2.5kHz frequency deviation
Ambient temperature: -30°C to +85°C; IF = 100kHz; AF bandwidth = 15kHz
Characteristic
Supply current
Input impedance
Input capacity
Maximum input voltage level
Sensitivity
Audio output
Audio THO
S +N/N
AM rejection
Squelch low level
Squelch high level
Squelch hysteresis
Noise figure
Conversion gain
Input gain compression
Squelch output load
Input voltage range
3rd order intercept point (input)
VCO frequency
Grade 1
Grade 2
Grade 3
Source impedance (pin 4)
AF output impedance
Lock-in dynamic range
External La drive level
Crystal ESR
Min.
Value
Typ.
Max.
2.3
100
0.5
0.5
5
35
30
30
6.5
250
80
2.0
2
90
1.3
50
Note 1
0.2
6.9
1
6
30
100
2.7
300
3.5
140
3.0
0.5
6
100
-38
85
95
105
25
4
±8
50
APPLICATION NOTES
IF Amplifiers and Mixer
The SL6601 can be operated either in a 'straight through'
mode with a maximum recommended input frequency of
800kHz or in a single conversion mode with an input
frequency of 50MHz maximum and an IF of 100kHz or ten
times the peak deviation, whichever is the larger. The crystal
oscillator frequency can be equal to either the sum or
difference of the two IF's; the exact frequency is not critical.
The circuit is designed to use series resonant fundamental
crystals between 1 and 17MHz.
When a suitable crystal frequency is not available a
fundamental crystal of one third of that frequency may be
used, with some degradation in performance.
E.G. If an external oscillator is used the recommended
level is 70mV rms and the unused pin should be left O/C. The
input is AC coupled via a 0.01JiF capacitor.
A capacitor connected between pin 4 and ground will
shunt the mixer output and limit the frequency response of
the mixer output and limit the frequency response of the
input signal to the second IF amplifier. A value of 33pF is
advised when the second IF frequency is 100kHz; 6.8pF is
advised for 455kHz.
Phase Locked Loop
The Phase Locked Loop detector features a voltage
controlled oscillator with nominal frequency set by an
100
110
120
40
10
250
25
Conditions
Units
mA
Source impedance = 2000
0
pF
Vrms At pin 18
JiV rms At pin 18 for S + NIN = 20dB
mV rms
1mV rms input at pin 18
%
1mV rms input at pin 18
dB
100JiV rms input at pin 18,30 % AM
dB
20JiV rms input at pin 18
V dc
No input
V dc
3JiV input at pin 18
dB
500 source
dB
dB
Pin 18 to pin 4
JiV rms Pin 18 to pin 4, 1dB compression
kO
At pin 8; above 20dB S + NIN
dB
Input pin 18, output pin 4
dBm
kHz
kHz
kHz
kO
kO
kHz
mV rms
0
390pF ';m;ng capad'or
390pF timing capacitor
390pF timing capacitor
I
No input
20JiV to 1mV rms at pin 18
At pin 2
10.8MHz
. .
f
external capacitor according to the formula (3"5)pF, where f
is the VCO frequency in MHz. The nominal frequency may
differ from the theoretical but there is provision for a fine
frequency adjustment by means of a variable resistor
between the VCO output pins; a value of 470k has negligible
effect while 6.8k (recommended minimum value) increases
the frequency by approximately 20 %.
Care should be taken to ensure that the free running VCO
frequency is correct; because the VCO and limiting IF
amplifier output produce square waves, it is possible to
obtain lock with the VCO frequency fractionally related to the
IF, e.g. IF = 100kHz, VCO = 150kHz. This condition can
produce good SINAO ratios but poor squelch performance.
The loop filter is connected between pins 11 and 12; a 33k
resistor is also required between pin 11 and Vcc.
The values of the filter resistor R2 and capacitor C1 must
be chosen so that the natural loop frequency and damping
factor are suitable for the FM deviation and modulation
bandwidth required. The recommended values for various
conditions are tabulated below:
Centre frequency
kHz
Deviation
kHz
Resistor
kO
Capacitor
pF
100
100
455
455
5
10
5
10
6.2
5.6
4.7
3.9
2200
1800
1500
1200
Note that the values of loop filter are not critical and in
many cases may be omitted.
122
SL6601
The AF output voltage depends upon the % deviation and
so, for a given deviation, output is inversely proportional to
centre frequency. As the noise is constant, the signal to noise
ratio is also inversely proportional to centre frequency.
veo Frequency Grading
The SL6601 is supplied in 3 selections of VCO centre
frequency. This frequency is measured with a 390pF timing
capacitor and no input signal.
Devices are coded 'SL6601 C' and a '/1', '/2', '/3' to indicate
the selection.
Frequency tolerances are:
/1
85 - 100kHz (or uncoded)
/2
95 - 110kHz
/3
105 - 120kHz
Note that orders cannot be accepted for any particular
selection, but all devices in a tube will be the same selection.
Squelch Facility
When inputs to the product detector differ in phase a series
of current pulses will flow out of pin 7. The feature can be
used to adjust the VCO; when a 1mV unmodulated input
signal is applied to pin 18 the VCO frequency should be
trimmed to maximise the voltage on pin 7.
The squelch level is adjusted by means of a preset variable
resistor between pin 7 and Vcc to set the output signal to
noise ratio at which it is required to mute the output. The
capacitor between pin 7 and ground determines the squelch
attack time. A value between 10nFand 10l1F can be chosen to
give the required characteristics.
Operation at signal to noise ratios outside the range 518dB is not recommended. Where the 'front end' noise is
'high (because of very high front end gain) the squelch may
well never operate. This effect can be obviated by sensible
receiver gain distribution.
The load on the squelch output (pin 6) should not be less
than 250kO. Reduction of the load below this level leads to
hysteresis problems in the squelch circuit.
The use of an external PNP transistor allows hysteresis to
be increased. See Fig.4. The use of capacitors greater than
1000pF from pin 6 to ground is not recommended.
Outputs
High speed data outputs can be taken direct from pins 11
and 12 but normally for audio applications pin 8 is used. A
filter network will be needed to restrict the audio bandwidth
and an RC network consisting of 4.7kO and 4.7nF may be
used.
Layout Techniques and Alignment
The SL6601 is not critical in PCB layout requirements
except in the 'straight through' mode. In this mode, the input
components and circuits should be isolated from the VCO
components, as otherwise the VCO will attempt to 'lock' to
itself, and the ultimate signal to noise ratio will suffer.
The recommended method of VCO adjustment is with a
frequency measurement system on pin 9. The impedance
must be high, and the VCO frequency is adjusted with no
input signal.
LOOP FILTER DESIGN
The design of loop filters in PLL detectors is a straight
forward process. In the case of the SL6601 this part of the
circuit is non-critical, and in any case will be affected by
variations in internal device parameters. The major area of
importance is in ensuring that the loop bandwidth is not so
low as to allow unlocking of the loop with modulation.
Damping Factor can be chosen for maximum flatness of
frequency response or for minimum noise bandwidth, and
values between 0.5 and 0.8 are satisfactory, 0.5 giving
minimum noise bandwidth.
Design starts with an arbitrary choise of fn, the natural loop
frequency. By setting this at slightly higher than the
maximum modulation frequency, the noise rejection can be
slightly improved. The ratio fm/fn highest modulating
frequency to loop frequency can then be evaluated.
From the graph, Fig.3 the value of the function
4>efn
af
can be established for the desired damping factor.
4>e - peak phase error
fn - loop natural frequency
af - maximum deviation of the input signal
and as fn and af are known, 4>e is easily calculated. Values for
4>e should be chosen such '1hat the error in phase is between
0.5 and 1 radian. This is because the phase detector limits at
±TT/2 radians and is non linear approaching these points.
Using a very small peak phase error means that the output
from the phase detector is low, and thus impairs the signal to
noise ratio. Thus the choice of a compromise value, and 0.5
to 1 radian is used. If the value of ~~n
= 0.85
4>e -
0.85af
fn
- 0.85 x 10 - 14 d
6
- . ra s.
This is too large, so increase fn e.g. to 10kHz.
fm
fn
=
0 5 4>efn
. af
= 0.45
..... e = 0.45 x 10 = 045
..,
10
.
- which is somewhat low
123
SL6601
Therefore set fn = 7.5kHz
fm
fn
4>efn
Tt
4>e
~------------------~-1--~---+N
= 0.666
=
471<
0.66
18
17
16
15
0 = 0.88 rads.
14
13
12
11
10
IC
0.66 x 1
=7:5
KoKD = 0.3fo where fo is the VCO frequency
0.3 x 200 x 103
(211' x 7.5 X 103)2 = 2711S
D
mn -
FigA Using an external PNP in the squelch circuit
KoKD
0.5
11' x7.5 x 103
0.3 x 200 x 103
+7V
= 4.5j1s
22.5 X 10-6
20 X 103
C
E..
t1
R
x 20
X
IF INPUT
1.125nF (use 1nF)
10n
R:~~~ER o---J
FILTER
103
100k
S~~~i~H
ADJUST
3
-- ~
22.5x 20 x 10
2 nd CONVERSION
OSCILLATOR
CRYSTAL
L---c=J-_._--o OU~~UT
10·8 MHz
OR
= 41<0 (use 3.9k)
'--+-__-.:..:..c_-j-_-<> ~'t~~~~H
10·6MHz
Actual loop parameters can now be recalculated
POSSIBLE FREQUENCIES
IN RANGE 455kHz "25M Hz
t2 = 3.9j1s
211'fn
5
(KoKD) _ (2 X 10 x 0.3)
= (t1 x t2 - (23.9 x 10-6 )
D
fn(t2
+ _)
Fig.S SL6601 application diagram
(1st IF= 10.7MHz, 2nd IF= 100kHz)
=50.1k rad/sec = 7.97kHz
TYPICAL CHARACTERISTICS
= 0.515
KoKD
35
/'
30
1.0
0.8
t
0.7
~
~
~ ....
0.4
~
0.3
/
0.2
0.1
0=""""" ~
.....
III
III
10
15
J
V
\
10
-120
-110
-100
-70
-60
-30
-20
INPUT LEVEL (dBm) AT PIN 18
Tn"
124
-r---
I{
1m
Fig.3 Damping factor
F MOD 1kHz
AF BANDWIDTH 15kHz
/
10
,
LOOP FILTER 6.2k/2.2n
DEVIATION 3kHz
V
«
10.7~
0.5
I
20
C
.\\
0.6
/
25
1\ 0- 0.5
\
\
0.9
Fig.6 Typical SINAD
(signal
+ noise + distortion/noise + distortion)
SL6601
90
I--
./
0
~
80
g
SO
1
I
a:
~
r--..
.75
.50
TYPICAL
-
~MINIMUM
.25
LOOP FILTER 6.2k12.2n
DEVIATION 3kHz
-I-F MOD 1kHz
40
AREA
\
20
-25
~"r--- t-:;Qo-
~ """'--
0
-50
0
-110
-100
-90
-70
-SO
-60
-40
-30
-20
r---
...--
\
Q
-120
0
r---
OPERATIVE
o
o
~
+85
t----
GUARANTEED
t-
it
I
,
j--- ..... -
80
-10
f---
---
INPUT LEVEL (dBm) AT PIN 18
5
Fig.7 Typical recovered audio v. input level (3kHz deviation)
.8
SUPPLY VOLTAGE (V)
Fig.S Supply voltage v. temperature
VARIATI~>N WITH
TEMPERATURE
Vee::: TV
./
!--
75
35
0'
SO
V
y
VARIATION WITH
SUPPLY VOLTAc:Y'
V·
30
~
w
a:
:::l
~
a:
25
~
~
~
:I
5
-25
I
-1
1\
0
-SO
0
LOOP FILTER 6.2k12.2n
DEVIATION 3kHz
-f-F MOD 1kHz
1\,
I!!
o
\ I'-....
5
i--"""
0
+2
-120
-110
-100
-90
Veo FREQUENCY DRIFT ( '!o)
-80
-SO
-40
-30
-20
10
INPUT LEVEL (dBm) AT PIN 18
Fig.9 Typical VCO characteristics
Fig.10 Typical squelch current v. input level
40
r-
INTER!N~
NblSE LE\EL
(20kHz BANDWIDTH)
30
i
~
25
~
U)
20
a:
1\ V
V
~
"f\
2~d
..z
r--
Ii:
~
IF
J
100kHl
-20
Iiii
~
>
~
w
~ -so
:I
c
/
o
>
I!:
--
/
~
0
1/
-70
:::l
o
-8 0
5
-120
-110
-100
-90
-80
-70
-60
-30
-20
INPUT LEVEL (dBm) AT PIN 18
Fig.11 Typical AM rejection
(the ratio between the audio output produced by:
(a) a 3kHz deviation 1kHz modulation FM signal and
(b) a 30 % modulated 1kHz modulation AM signal at the
same input voltage leveL)
-120
-110
-100
-90
70
-60
40
30
20
-10
INPUT LEVEL (dBm) AT PIN 18
Fig. 12 Typical conversion gain (to pin 4)
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Storage temperature
9V
-55°C to +125°C (DP package)
-55°C to +150°C (DG)
Operating temperature
-55° C to +125° C
(see Electrical Characteristics)
Input voltage
1V RMS at pin 18
125
SL6601
126
SL6652
e !:!;I!.!.!!!________
A_DV_A_N_C_E_IN_F_OR_M_A_T_IO_N
Advance information is issued to advise Customers of new additions to the Plessey Semiconductors range which, nevertheless, still
have 'pre-production' status. Details given may, therefore, change without notice although we would expect this performance data to be
representative of 'full production' status product in most cases. Please contact your local Plessey Semiconductors Sales Office for
details of current status.
SL6652
LOW POWER IF/AF CIRCUIT FOR FM CELLULAR RADIO
The SL6652 is a complete single chip mixer/oscillator, IF
amplifier and detector for FM cellular radio, cordless
telephones and low power radio applications. It features an
exceptionally stable RSSI (Received Signal Strength
Indicator) output using a unique system of detection. Supply
current is less than 2mA from a supply voltage in the range
2.5V to 7.SV.
MIXER OSC
INPUT BIAS
MIXER OSC
INPUT
LIMITER OUTPUT
OUAD COIL
FEATURES
2
AUDIO OUTPUT
3
AUOIO OUTPUT
4
GROUNO
6
18
16
•
Low Power Consumption (1.5mA)
Single Chip Solution
RF INPUT
7
•
Guaranteed 1OOMHz Operation
BAND·GAP REF
OUTPUT
8
•
Exceptionally Stable RSSI
MIXER OUTPUT
REFERENCE
9
12
MIXER OUTPUT
10
11
•
Cellular Radio Telephones
•
Cordless Telephones
OSC EMITTER
OSC CURRENT
SOURCE
•
APPLICATIONS
OSC COllECTOR
14
LIMITER INPUT
LIMITER INPUT
DECOUPLE
LIMITER FEEDBACK
DECOUPLE
RSSIOUTPUT
DG20
QUICK REFERENCE DATA
•
Supply Voltage 2.5V to 7.5V
•
Sensitivity 3)N
•
Co-Channel Rejection 7dB
VCC
----~---4~--.-
__~I~f~~ I-:tt---~---L---.J
OSCILLATOR
INPUT
200mV
RMS
15
~______~~~-r5~~A
6
330p
5
AUDIO
OUTPUTS
OSCILLATOR
TRANSISTOR
SL6652
RSSI
MIXER
I~~T
1"
--f ~~O-:-----'=----'
127
SL6652
ABSOLUTE MAXIMUM RATINGS
10V
-55°C to +150°C
-55° C to +125° C
1V rms
Supply voltage
Storage temperature
Operating temperature
Mixer input
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Vcc
2.5V to 7.5V, Tamb
-30°C to +S5°C, IF
=
=
Characteristic
Min.
Overall
Supply current
Sensitivity
AM rejection
Vblas
Co-channel rejection
1.0
= 455kHz, RF = 50MHz, Quad Coil Working Q = 30
Value
Typ.
1.5
5
3
40
1.2
7
Max.
2.0
10
1.4
Mixer
AF input impedance
OSC input impedance
OSC input bias
Mixer gain
3rd order input intercept
OSC input level
OSC frequency
180
100
300
Oscillator
Current sink
HIe
40
30
70
1
2
5
15
-10
h
IF Amplifier
Gain
Frequency
Diff. input impedance
Detector
Audio output level
Ultimate SIN ratio
THD
Output impedance
Inter-output isolation
RSSI Output(T 8mb = +25° C)
Output current
Output current
Current change
Linear dynamic range
455
/1V
/1V
dB
V
dB
kohm
kohm
/1 A
dB
dBm
mV
MHz
/1 A
MHz
90
1500
20
dB
kHz
kohm
60
0.5
40
65
1.22
20dB SINAD
12dB SINAD
AF input <500/1V
Tamb = 25°C
See Note 2
At Vbias
Aload = 1.5k
Tamb = 25°C
40 ... 70/1A
40 '" 70/1A
125
mV
dB
5
%
}
kohm
dB
1kHz
/1 A
/1 A
/1A/dB
dB
No input pin 14
Pin 14 = 2.5mV
See Note 1
See Note 1
20
SO
50
0.9
70
mA
500
75
Conditions
Units
1.5
5mV into pin 14
NOTES
1. The RSSI output is 100% dynamically tested at 5V and +20 0 C over a lOdS range. First the input to pin 14 is set to 2.5mV and the RSSI current
recorded Then for each step of 1OdS from -40 to +30dS the current is measured again. The current change in each step must meet the specified
figure for current change. The RSSI output is guaranteed monotonic and free from discontinuities over this range.
2. Co-channel rejection is measured by applying a 3kHz deviation, 1kHz modulated signal at an input level to give a 20dS SINAD ratio. Then a
3kHz deviation, 400Hz modulated signal on the same frequency is also applied and its level increased to degrade the SINAD to 14dB.
128
SL6652
200k
L...--I--t:===1===:::::---1~+--BIAS
Fig.3 Internal schematic
GENERAL DESCRIPTION
IF amplifier
The SL6652 is a very low power, high performance
integrated circuit intended for IF amplification and
demodulation in FM radio receivers. It comprises:
The limiting amplifier is capable of operation to at least
1MHz and the input impedance is set by an external resistor
to match the ceramic filter. Because of the high gain, pins 12
and 13 must be adequately bypassed.
•
•
•
•
•
•
A mixer stage for use up to 100MHz
An uncommitted transistor for use as an oscillator
A current sink for biasing this transistor
A limiting amplffier operating up to 1.5MHz
A quadrature detector with differential AF output
An RSSI (Received Signal Strength Indicator) output
Mixer
The mixer is single balanced with an active load. Gain is set
externally by the load resistor although the value is normally
determined by that required for matching into the ceramic
filter. It is possible to use a tuned circuit but an increase in
mixer gain will result in a corresponding reduction of the
mixer input intercept pOint.
The RF input is a diode-biased traneistor with a bias
current of typically 300J.lA. The oscillator input is differential
but would normally be driven single-ended. Special care
should be taken to avoid accidental overload of the oscillator
input.
Oscillator
The oscillator consists of an uncommitted transistor and a
separate current sink. The user should ensure that the design
of oscillator is suitable for the type of crystal and frequency
required; it may not always be adequate to duplicate the
design shown in this data sheet.
Detector
A conventional quadrature detector is fed internally from
the IF amplifier; the quadrature input is fed externally using
an appropriate capacitor and phase shift network. A
differential output is provided to feed a comparator for digital
use, although it can also be used to provide AFC.
RSSloutput
The RSSI output is a current source with value
proportional to the logarithm of the IF input signal amplitude.
There is a small residual current due to nOise within the
amplifier (and mixer) but beyond this pOint there is a
measured and guaranteed 70dB dynamiC range. The typical
range extends to 92dB, independent of frequency, and with
exceptionally good temperature and supply voltage stability.
Supply voltage
The SL6652 will operate reliably from 2.5V to 7.5V. The
supply line must be decoupled with 470nF using short leads.
Intemal bias voltage
The internal band gap reference must be externally
decoupled. It can be used as an external reference but must
not be loaded heavily; the output impedance is typically 14
ohms.
129
SL6652
>40
+2~OC
!
~:
o
o
X
",
I
·73
·63 ·S3 ·43 ·33
INPUT LEVEL (dBm)
·23
·13
·3
o
·103
+7
FigA Audio output vs input and temperature at 2.5V
> 40
I- 30
:::l
II..
I:::l 20
0
....
cc 10
/'
-,-y
~ 40
1-
I- 30
+2SoC
·30 oe
£
o
FR0.:.:f
Non. CHANGE IN OUTPUT
TO
lS
'rCI
rSOi
MIINIMjL.
1
·103 ·93
·83 ·73
·63 ·S3 ·43 ·33 ·23
INPUT LEVEL (dBm)
·13
·3
+7
Fig.6 Audio output vs input and temperature at +7.5V
r,
·93 ·83
·73
·63 -53 -43 -33
INPUT LEVEL (dBm)
-23
-13
-3
+7
Fig.5 Audio output vs input and temperature at 5.0V
l
+8 s oC
!
.~0:C-
,.~
.3r C
·103 ·93 ·83
I
~
~V
~ 10
+~soe
+2~oC
+8 s oC
,
v:
,
I
l
~_
o
20
~ 10
o
I
)5V-
,.sv
/./
s.yv
.,~
-103 -93
I
-83
-73
-63 -53 -43 -33 -23
INPUT LEVEL (dBm)
-13
·3
+7
Fig.7 Audio output vs input and supply voltage at +250 C
AVERAGE
40
~30
~P'"
c
~ 20
iii
10
o
~
'"
'I,
+S
1
·S
~ 'P' AVERAGE FOR vee 2 t TO vee 7.5V r--
·103 ·93 ·83
AND TEMPERATURE ·30 TO +85°e
SIMULTANEOUSLY. ± STANDARD_ t-iEVIAITIONISHOjN A1S +~'
.s.,
·73
·63 ·53 ·43 ·33 ·23
INPUT LEVEL (dBm)
Fig.B SINAD and input level
130
·13
·3
+7
~0~3---~~~~~~~---~~-----2~3----·13---~.3--+~7
Fig.9 AM rejection and input level
SL6652
140
140
130
130
120
120
110
//
100
h~
90
r
7.5V
r5.0V
I
2.5V
1
20
10
o
·103 ·93
·83
.~/
/. V
50
~/
30
20
10
·73 ·63 ·53
·43
·33
·23
·13
·3
~V
~/
:::::: .......
o
·103 ·93
+7
·83
·73
Fig. 10 RSSI output vs input and supply voltage
(Tamb = 20"C)
120
1
110
J /
100
90
/ V
I / /V
JL LV
3 80
70
gj 60
V/
50
b
40
o
·23 ·13
·3
+7
T
V +~5°C
V ~2~oC
J/
/);' /
90
/-.Jooc
:i'
3 80
!;
o
iii
III
II:
/V
60
50
40
30
20
~ ~I'
10
~
·53
·43
·33
·23
·13
·3
+7
o
/J
A~
T
~o°c
/v
1/,/
~ 70
:::)
~/ V
·63
/ /
100
/~I'
·103 ·93 ·83 ·73
130
120
110
~25°C
~ //V
30
10
V+I 5°C
//V
:i'
20
·43 ·33
140
130
II:
·53
Fig.11 RSSI output vs input level and temperature
(Vee = 2.5V)
140
i
·63
INPUT LEVEL (dBm)
INPUT LEVEL (dBm)
§
/v
/
.IV /
40
A~
/~
~
/~O°C
//"
II:
AV
----
I~/
o
gj60
l~ I'
+j5°C
/ /
90
~:
0"
/b/
30
/
100
/.~
40
nl 5°C
110
/v
LV
)'l /
// /
/
~~
·103 ·93
·83 ·73
·63 ·53
·43
·33
·23
·13
·3
+7
INPUT LEVEL (dBm)
INPUT LEVEL (dBm)
Fig. 12 RSSI output vs input level and temperature
(Vee = SV)
Fig.13 RSSI output vs input level and temperature
(Vee = 7.SV)
131
SL6652
2.0
70
I
60
Iw
50
!!l 40
0
Z
~
30
"
20
Z
in
10
o
ME SUR
ME~
T
LI~
1.8
IT
-S~+S
il-
~
~
~
1
~VER1GE
!Zw
II:
II:
;:)
u
i
1.4
_r-
1.2
1.0
0.8
Tamb = 25°C
0.6
;:)
I/)
t
I-- AVERAGE OVER -30 TO +85° e, 2.5 TO 7.5V._
-103 -93
1.6
STAjDAjD DE1VIATI10N SrOWj AS I+S,
-83
Fig. 14 Signal
-73
-63 -53 -43 -33 -23
INPUT LEVEL (dBm)
+ noise to noise ratio
-13
-3
0.4
0.2
+7
5
2.0
!Z
1.6
1.4
w 1.2
II:
II:
;:)
U
V
V
I--"""
-I--
1--1"""
I--' ~
I""""
1.0
>
....I 0.8
Q.
Q.
;:)
I/)
0.6
0.4
0.2
-50 -40 -30 -20 -10
0 +10+20+30+40+50+60+70+80+90
TEMPERATURE ee)
Fig. 16 Supply current vs temperature (Vee = 5V)
132
7
Fig.15 Supply current vs supply voltage
vs input level
1.8
1
6
SUPPLY VOLTAGE (V)
10
SL6652
C11
0.111
.....-L_J-......-+----oQ RSSI
MURATA CERAMIC
FILTER
C18
10~
AF
VCC
AF
RF lIP
L1 330 to 480JlH
Q = 75 at 455kHz
150 turns 44 SWG
Neosld F Assy or
Toko equivalent
Neosld F Is similar to Toko 7MC-81282
L2 250 - 410nH
Q = 100 at 50MHz
Fig.17 Circuit diagram of SL6652 demonstration board
RSSI
RFI/P
A
AF
AF ~
Fig.18 PCB mask of demonstration board (1:1)
Fig.19 Component overlay of demonstration board (1:1 )
133
SL6652
134
e
SL6653
!:!:i!.!.~!! ________A_D_VA_N_C_E_IN_F_OR_M_A_T_IO_N
Advance information is issued to advise Customers of new additions to the Plessey Semiconductors range which, nevertheless, still
have 'pre-production' status. Details given may, therefore, change without notice although we would expect this performance data to be
representative of 'full production' status product in most cases. Please contact your local Plessey Semiconductors Sales Office for
details of current status.
SL6653
LOW POWER IF/AF CIRCUIT FOR FM RECEIVERS
The SL6653 is a complete single chip mixer/oscillator, IF
amplifier and detector for FM cellular radio, cordless
telephones and low power radio applications. Supply current
is less than 2mA from a supply voltage in the range 2.5V to
7.5V
The SL6653 affords maximum flexibility in design and use.
It is supplied in a dual-in-line hermetic package.
:f~~~ g,~~
LIMITER OUTPUT
1
18
QUAD CDIL
2
15
MIXER OSC INPUT
AUDIO OUTPUT
3
14
OSC COLLECTOR
GROUND
5
12
LIMITER INPUT
FEATURES
•
•
•
Low Power Consumption (1 .5mA)
Single Chip Solution
Guaranteed 1OOMHz Operation
BAND·GAP
REF OUTPUT
MIXER OUTPUT REFERENCE
8
11
LIMITER INPUT DECOUPLE
10
LIMITER FEEDBACK DECOUPLE
9
MIXER OUTPUT
QUICK REFERENCE DATA
•
•
DG16
Supply voltage 2.5V to 7.5V
Sensitivity 3~V
Fig.1 Pin connections - top view
ABSOLUTE MAXIMUM RATINGS
APPLICATIONS
•
•
Supply voltage
Storage temperature
Operating temperature
Mixer input
Mobile Radio Telephones
Cordless Telephones
10V
-55° C to +1500 C
-55°C to +125°C
1V rms
VCC
--..--- Vcc
VCC
10p
330p
r-----
OSCILLATOR
INPUT
200mV
rms
I
1
1
1
AUDIO
OUTPUT
(100mV
nns,3kHz
DEVIATION)
J----~-.........---;.
OSCILLATOR
TRANSISTOR
1
1
I
:
14
~------~--~-+~
C
B
1
+15dB (ADJUSTABLE)
100MHz MAX
115 SpA
RFC
RF
INPUT
3pV
10n
I~
116
1
SpA
1
~
----I J---+--c,'""6-~---J
1
Fig.2 Functional diagram
135
SL6653
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Vcc = 2.5V to 7.5V, T amb -30° C to +85° C, Mod.Freq.
=
Characteristic
Min.
Value
Typ.
1.0
1.5
5
3
30
1.2
Overall
Supply current
Sensitivity
AM rejection
Vblas
= 1kHz, Deviation =2.5kHz, Quadrature Circuit Working Q =30
Max.
2.0
10
1.4
Mixer
RF input impedance
OSC input impedance
OSC input bias
Mixer gain
3rd order input intercept
OSC input level
OSC frequency
180
100
300
Oscillator
Current sink
HIe
40
30
70
1
2
5
15
-10
fr
IF Amplifier
Gain
Frequency
Diff. input impedance
Detector
Audio output level
Ultimate SIN ratio
THO
Output impedance
136
455
Units
mA
JJV
JJV
dB
V
kohm
kohm
JJA
dB
dBm
mV
MHz
JJA
500
MHz
90
1500
20
dB
kHz
kohm
75
125
60
0.5
40
5
mV
dB
%
kohm
CondHlons
20dB SINAD
12dB SINAD
RF input
50DlN
Tamb = 25°C
<
At Vbias
Rload = 1.5k
Tamb = 25°C
40 ... 70JJA
40 ... 7OJJA
10mV into pin 12
SL6653
200k
~-I-t=::j:==~I-+--BIAS
Fig.3 Simplified internal schematic
GENERAL DESCRIPTION
The SL6653 is a very low power, high performance
integrated circuit intended for IF amplification and
demodulation in FM radio receivers. It comprises:
•
•
•
•
A mixer stage for use up to 100MHz
A transistor for use as an oscillator
A limiting amplifier operating up to 1.5MHz
IA quadrature detector with AF output
Mixer
The mixer is single balanced with an active load. Gain is set
externally by the load resistor although the value is normally
determined by that required for matching into the ceramic
filter. It is possible to use a tuned circuit but an increase in
mixer gain will result in a corresponding reduction of the
mixer input intercept point.
The RF input is a diode-biased transistor with a bias
current of typically 300#JA. The oscillator input is differential
but would normally be driven single-ended. Special care
should be taken to avoid accidental overload of the oscillator
input.
Oscillator
Detector
A conventional quadrature detector is fed internally from
the IF amplifier; the quadrature input is fed externally using
an appropriate capacitor and phase shift network.
Supply voltage
The SL6653 will operate reliably from 2.5V to 7.5V. The
supply line must be decoupled with 470nF using short leads.
Internal bias voltage
The internal band gap reference must be externally
decoupled. It can be used as an external reference but must
not be loaded heavily; the output impedance is typically 14
ohms.
+10
sldNAL
-10
iii'
~
~
The oscillator consists of a transistor and a current sink.
The user should ensure that the design of oscillator is
suitable for the type of crystal and frequency required; it may
not always be adequate to duplicate the design shown in this
data sheet.
IF amplifier
The limiting amplifier is capable of operation to at least
1MHz and the input impedance is set by an external resistor
to match the ceramic filter.
~
0
0
-20
-30
/
V
- ...
~
is -40
::;)
c
$UPPLY VOLTAGE
Tamb = 25°C
= 5V
.~
\
-so
-60
\
I'..
"
-70
1"-0.. NOISE
(400H~ '" 3kHz UN~ EIGH ED)-
-100
-90
-80
-70
-60
-so
-40
-30
-20
-10
INPUT LEVEL (dBm)
FigA Audio and noise outputs vs input level
137
SL6653
+10
·10
i
~
0
2Q
~
·20
/T~mb
,
'#
Ta~( =~5°C
=' +85°(:
+a~b ~ .30°6
·30
·40
SUPPLY VOLTAGE = 5V
·50
·60
·70
·100
·90
·80
·70
·60
·50
·40
·30
·20
·10
INPUT LEVEL (dBm)
Fig.5 Audio output vs temperature
1
2.0
2.0
1.8
1.8
1.6
1.4
~
Z
w
a:
a:
:::I
(.)
>
....I
1.2
-
1
~
1.6
1.4
Z
w 1.2
a:
a:
:::I
1.0
(.)
0.8
0.6
0.4
0.4
0.2
0.2
:::I
1/1
6
V"
1.0
II.
II.
5
7
10
SUPPLY VOLTAGE (V)
Fig.6 Supply current vs supply VOltage
0.6
·50 ·40 ·30 ·20 ·10 0 +10+20+30+40+50+60+70+80+90
TEMPERATURE eC)
Fig.7 Supply current vs temperature
VCC
R4
10k
L1:150 TURNS 44SWG ON NEOSID TYPE F FORMER
L2: 11 TURNS 28SWG ON 4mm FORMER
X1: 50MHz THIRD OVERTONE CRYSTAL
Fig.B Circuit diagram of SL6653 demonstration board
138
..-
.--I--r--"
>
....I
0.8
II.
II.
Tamb = 25°C
1/1
:::I
/'
.---I--
SL6653
Fig.9 PCB mask of demonstration board (1:1)
Fig. 10 Component overlay of demonstration board (1:1)
139
SL6653
140
SL6691C
SL6691C
MONOLITHIC CIRCUIT FOR PAGING RECEIVERS
The SL6691C is an IF system for paging receivers,
consisting of a limiting IF amplifier, quadrature demodulator,
voltage regulator and audio tone amplifier with Schmitt
trigger.
The voltage regulator requires an external PNP transistor
as the series pass transistor. The frequency response of the
tone audio amplifier is externally defined.
The SL6691C operates over the temperature range -30° C
to +85°C.
SCHMITT TRIGGER DIP
[~J
SUPPLY(VB)
TONE AMPLIFIER DIP [ I
"p SERIES PASS TRANSISTOR DRIVER
TONE AMPLIFIER liP [ 3
14
PREGULATED SUPPLY LINE
DEMODULATOR DIP [ 4
13P IF AMP liP
QUADRATURE COIL [5
IIp If AMP liP
DUADRATURE COIL [6
II P EARTH
DEMODULATOR DRIVER [ 7
10
PLf AMP DIP
DEMODULATOR DRIVER [8
9
PIf AMP DIP
FEATURES
DP16
Flg.1 Pm connections (top view)
•
Very Low Standby Current
•
•
Fast Turn-on
Wide Dynamic Range
•
Minimum External Components
APPLICATIONS
•
•
Pagers
Portable FM Broadcast Receivers
Sl6691C
ABSOLUTE MAXIMUM RATINGS
Storage temperature - 65°C to + 150°C
Supply voltage 6V
Fig.2 SL6691 C test circuit
~
_~'
13
12
TONE
AMPLIFIER
15
16
SCHMITT
TRIGGER
DEMODULATOR
14
11
Fig.3 SL6691C block diagram
141
SL6691C
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Temperatu re
- 30°C to +85°C
Supply voltage (Vc)
2.5V
IF frequency
455kHz (nominal)
500Hz
Modulation frequency
Deviation
±4.5kHz
Value
Characteristic
Min.
Max.
Quiescent current
1.0
1.4
mA
Switch on time
12
18
ms
2.1
V
dB
Voltage regulator
Regulated voltage
Supply line rejection
1.9
Current sink capability pin 15
100
IF amplifier
Input impedance
Output impedance
Dynamic range
Output voltage swing
Amplifier gain
Sensitivity
AM rejection
Amplifier 3dB bandwidth
Demodulator
Audio output
Distortion, TH D
Output impedance
Signal-to-noise ratio
40
8
VB =3V
Pins 2 and 3 SIC
Pins 1 and 4 OIC
Note 1
VB> 2.2V
VB> 2.2V
200mV p-p square wave@ 500 Hz
injected
JlA
k OllpF
kO
dB
mVp-p
dB
JlVrms
dB
MHz
20112
20
Conditions
Units
Typ.
2
100
600
90
16
40
1.5
mVrms
15
1.5
1
40
Tone amplifier
Open loop gain
Peak output current
54
20
Schmitt trigger
Mark space ratio
45/55
3
3
%
kO
dB
Audio 20dB S+NfN ratio
1OOJlV rms lIP @ 30% AM modulation
Quadrature element L-C tuned circuit:
Q=30
1OOJlV rms lIP 3kHz audio bandwidth
dB
JlA
38/62
20JlVrms lIP
NOTES
1. The 'Switch On' time is the time to the zero crossing point of the centre of the first occurrence of a 30/70 or 70/30 mark space wave on the
output of the Schmitt trigger after the supply voltage has been switched on. Conditions: VB = 2V,Tone filter connected (See Fig.2), IF input =
100IJV rms, Modulation 500 Hz @ 2kHz deviation.
CIRCUIT DESCRIPTION
Tone (Audio) Amplifier
IF Amplifier and Detector
The tone amplifier is a simple inverting audio amplifier
with voltage gain determined by the ratio of feedback
resistor to input resistor. The frequency response can
readily be controlled by suitable selection of feedback
components.
The IF amplifier consists of five identical differential
amplifier/emitter follower stages with outputs at the fourth
(pins 9 and 10) and fifth (pins 7 and 8) stages. The outputs
from the fourth stage are used when the lowest turn-on
time is required. Coupling to the quadrature network of the
detector is via external capacitors; otherwise the design is
conventional. The audio output is taken from pin 4 and
filtered externally.
142
Schmitt Trigger
The Schmitt trigger has an open collector output stage
which saturates ·when the input at pin 2 is high. A 20,N rms
input is sufficient.
SL6691C
NOMINAL DC PIN VOLTAGES(DP16)
Function
Pin
Supply
Series pass transistor driver
Regulated supply line
Earth
IF amp liP
IF amp liP
IF amp alP
IF amp alP
Demodulator alP
Quadrature coil
Quadrature coil
Tone amplifier liP
Schmitt trigger alP
Tone amplifier alP
Demodulator driver
Demodulator driver
16
15
14
11
13
12
10
Voltage
Battery voltage
Battery voltage -O.7V
2V
OV
1V
1V
1V
9 1V
4 1V
6 1V
5 1V
3 1.4V
1 OV or pin 16 or pin 14
2 1.4V
7 1V
8 1V
143
SL6691C
144
SL6700A
-_
PLESSEY
INFORMATION
Semiconductors _ _ _ _ _ _ _ADVANCE
___
_ __
Advance Information is issued to advise Customers of new additions to the Plessey Semiconductors range which, nevertheless, still
have 'pre-production' status. Details given may, therefore, change without notice although we would expect this performance data to be
representative of 'full production' status product in most cases. Please contact your local Plessey Semiconductors Sales Office for
details of current status.
SL6700A
IF AMPLIFIER AND AM DETECTOR
The SL6700A is a single or double conversion IF amplifier
and detector for AM radio applications. Its low power
consumption makes it ideal for hand held applications.
Normally the SL6700A will be fed with a first IF signal of
10.7MHz or 21.4MHz; there is a mixer for conversion to the
first or second IF, a detector, an AGC generator with optional
delayed output and a noise blanker monostable. This device
is characterised for operation from -55 0 C to +125 0 C.
AGCOECOUPllNG
1
AGC BIAS
2
INTERSTAGE \
COUPliNG TERMINALS /
3
OELAYEOAGCOUTPUT
5
FEATURES
•
High Sensitivity: 10J,N Minimum
•
Low Power SmA Typical at 6V
•
•
Linear Detector
Full MIL Temperature Range
16
AGC OECOUPLING
15
AUOIOOUTPUT
14
OECOUPLING POINT
13
DETECTOR INPUT
MIXER INPUT
7
12
NOISE BLANKER TIMING CAPACITOR
MIXER OUTPUT
8
11
NOISE BLANKER OUTPUT
lOCAlOSC.INPUT
9
DG18
Fig. 1 Pin connections (top view)
APPLICATIONS
•
Low Power AM/SSB Receivers
ABSOLUTE MAXIMUM RATINGS
QUICK REFERENCE DATA
•
•
Supply voltage
Storage temperature
Operating temperature
Supply Voltage: 4.SV
Input Dynamic Range: 100dB Typical
GROUND
AGC
DECOUPLING
AUDIO
OUTPUT
NOISE
BLANKER
DECDUPLING DETECTOR
TIMING
POINT
INPUT
CAPACITOR
NOISE
BLANKER
OUTPUT
7.5V
-55 0 C to +150 0 C
-55°C to +125°C
tsV
SUPPLY
10
3
AGC
DECOUPLING
AGC
BIAS
,
~
INTERSTAGE
COUPLING
TERMINALS
5
DELAYED
AGC
OUTPUT
IF
OUTPUT
MIXER
INPUT
MIXER
OUTPUT
LOCAL
OSC
INPUT
Fig.2 SL6700A block diagram
145
SL6700A
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb -55°C to +125°C Test circuit Fig.6. Modulation frequency 1kHz
Characteristic
Min.
Supply voltage
Supply current
SIN ratio
TH distortion
Sensitivity
Audio output level change
AGC threshold
AGC range
AF output level
Delayed AGC threshold
Dynamic range
IF frequency response
IF amplifier gain
Detector gain
Detector Zin pin 13
IF amplifier Zin pin 1S
Noise blank le';el
Value
Typ.
Max.
4
10
20
15
40
40
2
1.S
4.0
Noise blank duration
Mixer conversion gain
Mixer Zin (Signal)
Mixer Zin (L.a.)
Mixer L.a. injection
Detector output voltage change
300
1.0R
2
3
50
6
7
7
3.5
40
3
5
6
5
80
40
10
100
25
50
46
4
3
60
55
6.8
4.5
400
1.2R
3
5
100
8
0.3
500
1.5R
5
8
150
8.2
5
Units
V
mA
dB
%
IN
10
dB
JiV
dB
mVrms
mVrms
dB
MHz
dB
dB
kO
kO
V
V
Ji5
kO
kO
kO
mVrms
dB
Conditions
Optimum performance at 4.5V
1mV input SO % modulation
1mV input 30 % modulation
10dB S + NIN ratio, 30%
10JN to 50mV input 80%
30 % modulation 1mV input
80 % modulation
Noise floor to overload
3dB gain reduction
10.7MHz (both amplifiers cascaded)
455kHz SO % AM
Logic 1
Logic 0
C pin 12 = 30nF,R pin 12-11
R is load resistor in kO
= 18k
fc = 10.245MHz
1mV rms input, modulation increased
from 30% to SO%
OPERATING NOTES
The noise blank duration can be varied from the suggested
value of 30Jis using the formula: Duration time = 0.7CR,
where R is value of resistor between pins 11 and 12 and C is
value of capacitor from pin 12 to ground.
There is no squelch in the SL6700A and the delay in the
delayed AGC is too large to make this output suitable.
Squelch is best obtained from a comparator on the AGC
decoupling point, pin 16.
The IF amplifiers may be operated at 455kHz giving a
single conversion system.
The mixer may also be used as a product detector. Further
application information is available on request.
The mixer may also be used as a product detector. Further
application information is available on request in Application
Note AN1001.
AF DIP
Vee
TYPICAL DC PIN VOLTAGES
(Supply 4.SV, Input 1mV)
Pin
Voltage
Pin
Voltage
1
2.25V
2.09V
3.68V
0.7V
0.6V
3.7V
1.5V
4.3V
1.5V
10
11
12
13
14
15
16
17
18
4.5V
3.7V
OV
O.77V
1.5V
1.0V
0.7V
OV
0.7V
2
3
4
5
6
7
8
9
146
Fig.3 SL6700A AM double conversion receiver with noise blanker
SL6700A
~.50
o
~
I
PIN 5 I'-:.n..
LOAD
o
u
10
~
«
53
~
.,---
~
15
O·S
o
o
o
.60
/
a:::. 4 0
I
II
~
~.30
/
W
If)
(5
.
Z +20
V
«
*
z
.10
~
5
INPUT (dB"V RMS)
Fig.4 Typical delayed AGe output variation with input signal
(f = 1O.7MHz, 30 % modulation)
0
~
V
W
If)
/
I
o
.60
INPUT (dBjJV
.80
.100
RMS)
Fig.5 Typical signal to noise ratio (S t N/N) with input signal
(f = 10.7MHz, 30 % modulation)
AF OUTPUT
1
DELAYED
AGe
OUTPUT
Fig.6 Test circuit
147
tJ)
...a.
I;
~
co
NOTE 3
NARROW BAND FILTERS MAY RING BECAUSE
NOISE
POWER
IS
HIGH.
GIVES
EFFECT OF
HETERODYNE WHISTLE ON WEAK SIGNALS. USE
A TUNED CIRCUIT OR A GROUP DELAY
EQUALISED FILTER TO AVOID THIS.
~
o
r-----'
I
I
MI~~~E~~RE
FOR DOUBLE
l>
I
I
~~~~;J
FILTER
~......
(I)
r-
"l_._
I
~.'. AUDIO
~-·'-'OUTPUT
Q)
~
-<
"0
V'GC~SEE
NOTE 4
o·
~
~
(AGC TOTAL RANGE
~
8OdB)
~
2.3V
-
1.6V
-
III
-
-
--
SIGNAL (dB)
g.
NOTE 4
::J
YAGC
VARIES WITH
TEMPERATURE
C)
~.
~Btl?~~~R
~
OUTPUT
en
::s-
O
~.
n4.OV MIN
CQ
s·
I
iii'
~~
~
C)
s·
CQ
MIxER -
-
-
__
--1
alP
R(AND Z)
VDAGClL:
2V
----
Rc2.2k
o
SIGNAL (dB)
NOTE 2
LEAVE Ole IF DEL. AGe NOT REQUIRED.
Ne. VOLTAGES SHOWN ARE TYPICAL
1k!l NOM. 5kCl MAX.
~
L
O.3V MAX
SL6700C
SL6700C
IF AMPLIFIER AND AM DETECTOR
The SL6700C is a single or double conversion IF
amplifier and detector for AM radio applications. Its low
power consumption makes it ideal for hand held
applications. Normally the SL6700C will be fed with a first
IF signal of 10.7MHz or 21.4MHz; there is a mixer for
conversion to the first or second IF, a detector, an AGC
generator with optional delayed output and a noise blanker
monostable.
AGCOECOUPLING
1
AGC BIAS
2
INTERSTAGE!
COUPLING TERMINALS
3
OELAYEO AGC OUTPUT
5
FEATURES
•
•
•
AGCOECOUPLING
AUDIO OUTPUT
14
OECOUPLING POINT
13
OETECTORINPUT
7
12
NOISE BLANKER TIMING CAPACITOR
MIXER OUTPUT
8
11
NOISE BLANKER OUTPUT
LOCAL OSC. INPUT
9
MIXER INPUT
High Sensitivity: 10,N minimum
Low Power: 8mA Typical at 6V
Linear Detector
16
15
DP18
APPLICATIONS
Fig. 1
•
QUICK REFERENCE DATA
•
•
Pin connections (top view)
Low Power AM/SSB Receivers
ABSOLUTE MAXIMUM RATINGS
Supply Voltage: 4.5V
Input Dynamic Range: 1OOdB Typical
tF
INPuT
I
AGC
DECOUPLING
GROUN['I
Supply voltage: 7.5V
Storage temperature: -55°C to +125-C
AGe
DECOUPlING
AUDIO
OUTPUT
3
AGC
BIAS
NOISE
BLANKER
TIMING
CAPACITOR
NOISE
BLANKER
OUTPUT
+6V
SUPPLY
9
4
'----y----J
INTERSTAGE
COUPLING
OECOUPLING DETECTOR
POINT
INPUT
DELAYED
AGC
OUTPUT
IF
OUTPUT
MIXER
MIXfR
J NPUT
OUTPUT
LOCAL
OSC
INPUT
TERMINALS
Fig. 2
SL6700C block diagram
149
SL6700C
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Supply voltage 4.5V
o
TAmb -30 e to +85°e
Characteristic
Min.
Supply voltage
Supply current
SIN ratio
TH distortion
Sensitivity
Audio output level change
AGC threshold
AGC range
AF output level
Delayed AGC threshold
Dynamic range
IF frequency response
IF amplifier gain
Detector gain
Detector lin pin 13
IF amplifier lin pin 18
Noise blank level
Value
Typ.
4
10
40
40
40
2
1.8
2.7
4.5
40
1
5
6
5
80
25
10
100
50
50
46
4
3
Max.
7
6
5
10
60
55
6.8
4.5
0.6
Noise blank duration
Mixer conversion gain
Mixer lin (signal)
Mixer lin (LO)
Mixer LO injection
Detector output voltage change
1.0R
2
3
20
6
300
1.2R
3
5
50
8
1.5R
5
8
150
8.2
Conditions
Units
V
mA
dB
%
jJV
dB
jJV
dB
mVrms
mVrms
dB
MHz
dB
dB
kO
kO
V
V
jJs
kO
kO
kO
mVrms
dB
Optimum performance at 4.5V
1mV input 80 % mod @ 1kHz
1mV input 80% mod @ 1kHz
10dB S + nlN ratio, 30% mod 1kHz
10jJV to 50mV input 80% mod 1kHz
30 % modulation 1kHz
80 % modulation
Noise floor to overload
3dB gain reduction
10.7MHz (both amplifiers cascaded)
455kHz 80 % AM 1kHz
Logic 1
Logic 0
C pin 12 = 30nF
R is load resistor in kO
fc = 10.245MHz
1mV rms input, 1kHz modulation
increased from 30 % to 80 %
OPERATING NOTES
AF O/P
Vee
The noise blank duration can be varied from the
suggested value of 300l-lS using the formula: Duration time
= 0.7CA, where A is value of resistor between pins 11 and
12 and e is value of capacitor from pin 12 to ground.
There is no squelch in the SL6700e and the delay in the
delayed AGe is too large to make this output suitable.
Squelch is best obtained from a comparator on the AGC
decoupling point, pin 16.
The IF amplifiers may be operated at 455kHz giving a
single conversion system.
The mixer may also be used as a product detector. Further
application information is available in Application Note
AN1001.
TYPICAL DC PIN VOLTAGES
(Supply4.5V, Input 1mV)
Pin
Voltage
Pin
Voltage
1
2
3
4
5
2~.25V
10
11
12
13
14
15
16
17
18
4.5V
3.7V
OV
O.77V
1.5V
1.0V
0.7V
OV
0.7V
6
7
8
9
150
2.09V
3.68V
0.7V
0.6V
3.7V
1.5V
4.3V
1.5V
Fig. 3 SL6700C AM double conversion receiver with noise blanker
SL6700C
~+50
o
2'0
~
~
0::+ 4 0
~ "5
::J
5
o
u
/
I
PIN 5 lk.n. LOAD
'-0
4:
o
UJ
~ ~'s
UJ
o
o
o
.60
/
Vl
<5
Z
g+30
V
~
<5
..,
z
+20
/
...J
4:
*...
z
.80
+10
... 100
I
....--
-
/
/
::J
INPUT (dB)JV RMS)
Fig. 4
/
UJ
"-
5
Typical delayed AGe output variation with input signal
(f=10.7MHz, 30% modulation)
0
o
.20
+40
+60
.80
INPUT (dB~V RMS)
Fig.5
Typical signal to noise ratio (S+NIN) with input signal
(f=10. 7MHz, 30% modulation)
151
....en
tn
~
I\)
NOTE.
NARROW BAND F1LTEAS MAY RING BECAUSE
NOISE POWER IS HIGH. GIVES EFFECT OF
HETERODYNE WHIS11£ ON WEAK SIGNALS. USE
A TUNED CIRCUIT OR A GROUP DELAY
EQUALISED ALTER TO AVOID THIS.
o
o
r-----'
I~I
I
FOR DOUBLE
I
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FILTER
~
Ol
f!?
Ol
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00-
ill
01
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1
1-0
10
100
BIAS SET CURRENT Il'A)
Fig,3 Supply current (each amplifier)
v. bias set current
1000
TAB1043
1000
II
I
I
VSUPPlY , t 12V
..
!
fA
=
VS:
~'00
+25°C
t 12V
10
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iii
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01
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/
0
10
1000
10
BIAS
SET
CURRENT (jJAI
100
lOOk
10k
FREQUENCY
I--
~
.-
0·0 1
-
\
10M
(Hz I
Fig. 5 Typical frequency response
Fig. 4 Gain bandwidth product v. ISET
ABSOLUTE MAXIMUM RATINGS
Supply voltages
Common mode input voltage
±15V
Not greater than
supplies
Differential input voltage
±25V
10mA
Bias set current
Storage
-55° C to +125° C
Power dissipation
800mW at 25° C
Derate at 7mW;o C above 25° C
Operating temperature range
-400 C to +850 C
159
TAB1043
160
Package Outlines
161
9.09/9.20 DIA
( 0.358/0.362)
419/469
(0.165/0.185)
12.70/14.22
(0.500/0560 )
5.08 I 0.200 )
PCD BASIC
r
0.25/1.01
10.010/0.040 )
0.3 8/0.76 MAX.RAD
0.015/0030)
I)
r-------,
-
l--J
0.15 MAX.RAD
(0.006)
S LEAD TO-5 - CMS
12 70/14 22
(0' 500/0- 560)
4 19/4 70
(0-165/0-185)
(5
,....
d
u~
C")
•
C")O
0:9
0-
C")N
C").
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1.0 --
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rog
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C")oIX),....
';'2
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f
8010/8·33
(0-318/0-328)
~
JL
(0- 010/0-040)
8 LEAD TO-5 (5.08 mm PCD) - CM8
162
!
4·19/4'70
(0·165/0·185)
1'016/0'381
(0'04010'0151
11--
L
8'50/8·01
(0'335/0'315)
1
ll?
NT- C')
do..
o
~>-
~_
JL
PIN SPACING
2.54 TVP(0.100)
JI.
t
e.
l-
-:
0.36/0.58
(0.014/0.023)
l
0.2010 36
~
[O~O,0141 ~I~
~:!
____ p_D_~~
~
U:~AX
SEATING
PLANE
7.62 (0.30)
CAS NOM.
-
14 LEAD CERAMIC OIL
CERDIP - DG14
165
8.48
(0.334)
MAX
I.
.1
254 MAX
(1.00)
~
§
mwm~~;:;:;:::;;;:;;~jt
JL
JI
~d
~d~
1
A
~lJ
(0·009/0'016)
7-62/8·38
(0'30/0'33 )
eRS NOM
MAX
2300/2200
(0.906/0.866)~
10.24/9.40
(0.403/0.370)
-
INDEX PIN
~-4
!
0
PIN No.1
21
~
+
t
9
16
2.03 MAX
(0.080)
0)
=1
ll!
(fJ
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Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.3
Linearized : No
XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date : 2017:07:14 08:59:18-08:00
Modify Date : 2017:07:14 09:37:31-07:00
Metadata Date : 2017:07:14 09:37:31-07:00
Producer : Adobe Acrobat 9.0 Paper Capture Plug-in
Format : application/pdf
Document ID : uuid:82d3fa35-4025-7043-8a7c-a3936043ca26
Instance ID : uuid:0c925ead-9451-a54f-b54a-35c9313151fe
Page Layout : SinglePage
Page Mode : UseNone
Page Count : 178
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